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module ym6045c_cell_22_mux4bit ( i1, o2, i6, i7, i8, i9, o11, o12, i13, i14, i15, i17, o19);
input wire i1;
output wire o2;
input wire i6;
input wire i7;
input wire i8;
input wire i9;
output wire o11;
output wire o12;
input wire i13;
input wire i14;
input wire i15;
input wire i17;
output wire o19;
assign o2 = i1 ? i7 : i6;
assign o11 = i1 ? i9 : i8;
assign o12 = i1 ? i13 : i14;
assign o19 = i1 ? i17 : i15;
endmodule // ym6045c_cell_22_mux4bit |
module ym6045c_cell_26_xnor ( i2, i4, o5);
input wire i2;
input wire i4;
output wire o5;
assign o5 = ~(i2 ^ i4);
endmodule // ym6045c_cell_26_xnor |
module ym6045c_cell_28_mux ( i1, o2, i5, i6);
input wire i1;
output wire o2;
input wire i5;
input wire i6;
assign o2 = i1 ? i6 : i5;
endmodule // ym6045c_cell_28_mux |
module ym6045c_cell_36_or8 ( i1h, i1l, i2h, i2l, o3, i7h, i7l, i8h, i8l);
input wire i1h;
input wire i1l;
input wire i2h;
input wire i2l;
output wire o3;
input wire i7h;
input wire i7l;
input wire i8h;
input wire i8l;
assign o3 = i1h | i1l | i2h | i2l | i7h | i7l | i8h | i8l;
endmodule // ym6045c_cell_36_or8 |
module ym6045c_cell_25_dec2to4 ( i1, o2, o3, i6, o10, o11);
input wire i1;
output wire o2;
output wire o3;
input wire i6;
output wire o10;
output wire o11;
assign o11 = ~i1 & ~i6;
assign o3 = ~i1 & i6;
assign o10 = i1 & ~i6;
assign o2 = i1 & i6;
endmodule // ym6045c_cell_25_dec2to4 |
module ym6045c_cell_39_oai21 ( o1, i2, i3, i4);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
assign o1 = ~(i3 & (i2 | i4));
endmodule // ym6045c_cell_39_oai21 |
module ym6045c_cell_37_nor8 ( i1, i2, i3, i4, o5, i6, i7, i8, i9);
input wire i1;
input wire i2;
input wire i3;
input wire i4;
output wire o5;
input wire i6;
input wire i7;
input wire i8;
input wire i9;
assign o5 = ~(i1 | i2 | i3 | i4 | i6 | i7 | i8 | i9);
endmodule // ym6045c_cell_37_nor8 |
module ym6045c_cell_14_cnt_bit ( o2, o3, i6, i7, i13, i14, o15, i18);
output wire o2;
output wire o3;
input wire i6;
input wire i7;
input wire i13;
input wire i14;
output wire o15;
input wire i18;
reg data;
wire s = data ^ i18;
assign o15 = data & i18;
assign o2 = data;
assign o3 = ~data;
always @(posedge i6, negedge i7)
begin
if (~i7)
data <= 1'h0;
else if (~i14)
data <= i13;
else
data <= s;
end
endmodule // ym6045c_cell_14_cnt_bit |
module ym6045c_cell_9_dffs ( i3, i4, i7, o11, o13);
input wire i3;
input wire i4;
input wire i7;
output wire o11;
output wire o13;
reg data;
assign o13 = data;
assign o11 = ~data;
always @(posedge i3, negedge i7)
begin
if (~i7)
data <= 1'h1;
else
data <= i4;
end
endmodule // ym6045c_cell_9_dffs |
module ym6045c_cell_2_dffr ( o2, o4, i9, i11, i13);
output wire o2;
output wire o4;
input wire i9;
input wire i11;
input wire i13;
reg data;
assign o4 = data;
assign o2 = ~data;
always @(posedge i13, negedge i9)
begin
if (~i9)
data <= 1'h0;
else
data <= i11;
end
endmodule // ym6045c_cell_2_dffr |
module ym6045c_cell_23_dff ( o2, o5, i10, i11);
output wire o2;
output wire o5;
input wire i10;
input wire i11;
reg data;
assign o5 = data;
assign o2 = ~data;
always @(posedge i11)
begin
data <= i10;
end
endmodule // ym6045c_cell_23_dff |
module ym6045c_cell_17_sr8 ( i2, o3, o10, o16, o23, o29, o36, o42, o49, i56, i57);
input wire i2;
output wire o3;
output wire o10;
output wire o16;
output wire o23;
output wire o29;
output wire o36;
output wire o42;
output wire o49;
input wire i56;
input wire i57;
reg [7:0] data;
assign o3 = data[0];
assign o10 = data[1];
assign o16 = data[2];
assign o23 = data[3];
assign o29 = data[4];
assign o36 = data[5];
assign o42 = data[6];
assign o49 = data[7];
always @(posedge i57, negedge i2)
begin
if (~i2)
data <= 8'h0;
else
data <= { i56, data[7:1] };
end
endmodule // ym6045c_cell_17_sr8 |
module ym6045c_cell_38 ( o1, o2, i10, i12);
output wire o1;
output wire o2;
input wire i10;
input wire i12;
reg data;
assign o1 = ~data;
assign o2 = data;
always @(negedge i12, negedge i10)
begin
if (~i10)
data <= 1'h0;
else
data <= ~data;
end
endmodule // ym6045c_cell_38 |
module ym6045c_cell_31 ( i2, i3, i4, i13, o16, o17);
input wire i2;
input wire i3;
input wire i4;
input wire i13;
output wire o16;
output wire o17;
reg data;
assign o16 = data;
assign o17 = ~data;
always @(negedge i2, negedge i13)
begin
if (~i13)
data <= 1'h0;
else
data <= ~(~(i3 | data) | (i4 & data));
end
endmodule // ym6045c_cell_31 |
module ym6045c_cell_32 ( i1, o2);
input wire i1;
output wire o2;
assign o2 = i1;
endmodule // ym6045c_cell_32 |
module ym6045c_cell_35_not ( o1, i2);
output wire o1;
input wire i2;
assign o1 = ~i2;
endmodule // ym6045c_cell_35_not |
module ym6045
(
input MCLK,
input MCLK_e,
input VCLK,
input ZCLK,
input VD8_i,
input [15:7] ZA_i,
input ZA0_i,
input [22:7] VA_i,
input ZRD_i,
input M1,
input ZWR_i,
input BGACK_i,
input BG,
input IORQ,
input RW_i,
input UDS_i,
input AS_i,
input DTACK_i,
input LDS_i,
input CAS0,
input M3,
input WRES,
input CART,
input OE0,
input WAIT_i,
input ZBAK,
input MREQ_i,
input FC0,
input FC1,
input SRES,
input test_mode_0,
input ZD0_i,
input HSYNC,
output VD8_o,
output ZA0_o,
output [15:8] ZA_o,
output [22:7] VA_o,
output ZRD_o,
output UDS_o,
output ZWR_o,
output BGACK_o,
output AS_o,
output RW_d,
output RW_o,
output LDS_o,
output strobe_dir,
output DTACK_o,
output BR,
output IA14,
output TIME,
output CE0,
output FDWR,
output FDC,
output ROM,
output ASEL,
output EOE,
output NOE,
output RAS2,
output CAS2,
output REF,
output ZRAM,
output WAIT_o,
output ZBR,
output NMI,
output ZRES,
output SOUND,
output VZ,
output MREQ_o,
output VRES,
output VPA,
output VDPM,
output IO,
output ZV,
output INTAK,
output EDCLK,
output vtoz,
output w12,
output w131,
output w142,
output w310,
output w353
);
wire pal_trap = ~1'h1;
wire EDCLK2;
reg edclk_buf;
always @(posedge MCLK)
begin
edclk_buf <= EDCLK2;
end
assign EDCLK = edclk_buf;
assign vtoz = VZ;
ym6045c arb
(
.VA8_d(w131),
.VA21_d(w142),
.TPAL(~pal_trap),
.n_LDS_d(strobe_dir),
.VA8_o(VA_o[7]),
.VA8_i(VA_i[7]),
.VA9_o(VA_o[8]),
.VA9_i(VA_i[8]),
.VA10_o(VA_o[9]),
.VA10_i(VA_i[9]),
.VA11_o(VA_o[10]),
.VA11_i(VA_i[10]),
.VA12_o(VA_o[11]),
.VA12_i(VA_i[11]),
.VA13_o(VA_o[12]),
.VA13_i(VA_i[12]),
.VA14_o(VA_o[13]),
.VA14_i(VA_i[13]),
.VA15_o(VA_o[14]),
.VA15_i(VA_i[14]),
.VA16_o(VA_o[15]),
.VA16_i(VA_i[15]),
.VA17_o(VA_o[16]),
.VA17_i(VA_i[16]),
.VA18_o(VA_o[17]),
.VA18_i(VA_i[17]),
.VA19_o(VA_o[18]),
.VA19_i(VA_i[18]),
.VA20_o(VA_o[19]),
.VA20_i(VA_i[19]),
.VA21_o(VA_o[20]),
.VA21_i(VA_i[20]),
.VA22_o(VA_o[21]),
.VA22_i(VA_i[21]),
.VA23_o(VA_o[22]),
.VA23_i(VA_i[22]),
.FC0(FC0),
.FC1(FC1),
.n_VPA(VPA),
.n_RESET(VRES),
.D8_o(VD8_o),
.D8_d(w12),
.D8_i(VD8_i),
.VCLK(VCLK),
.n_TIME(TIME),
.n_CAS0(CAS0),
.n_DTACK_d(DTACK_o),
.n_DTACK_i(DTACK_i),
.RW_i(RW_i),
.RW_d(RW_d),
.RW_o(RW_o),
.n_LDS_o(LDS_o),
.n_LDS_i(LDS_i),
.n_UDS_o(UDS_o),
.n_UDS_i(UDS_i),
.n_AS_o(AS_o),
.n_AS_i(AS_i),
.n_INTAK(INTAK),
.n_VDPM(VDPM),
.n_BG(BG),
.n_BGACK_i(BGACK_i),
.n_BGACK_d(BGACK_o),
.n_BR(BR),
.i_EOE(EOE),
.IA14(IA14),
.n_NOE(NOE),
.EDCK(EDCLK2),
.n_OE0(OE0),
.n_HSYNC(HSYNC),
.MCLK(MCLK_e),
.n_SOUND(SOUND),
.ZCLK(ZCLK),
.n_WRES(WRES),
.n_ZRAM(ZRAM),
.n_REF(REF),
.n_M1(M1),
.n_ZRES(ZRES),
.n_ZBR(ZBR),
.n_WAIT_d(WAIT_o),
.n_WAIT_i(WAIT_i),
.n_ZBAK(ZBAK),
.n_ZWR_o(ZWR_o),
.n_ZWR_i(ZWR_i),
.n_ZRD_i(ZRD_i),
.n_ZRD_o(ZRD_o),
.n_IREQ(IORQ),
.n_MREQ_i(MREQ_i),
.n_MREQ_o(MREQ_o),
.n_NMI(NMI),
.n_ZA0_i(ZA0_i),
.n_ZA0_o(ZA0_o),
.ZA7(ZA_i[7]),
.ZA8_i(ZA_i[8]),
.ZA8_o(ZA_o[8]),
.ZA9_i(ZA_i[9]),
.ZA9_o(ZA_o[9]),
.ZA10_i(ZA_i[10]),
.ZA10_o(ZA_o[10]),
.ZA11_i(ZA_i[11]),
.ZA11_o(ZA_o[11]),
.ZA12_i(ZA_i[12]),
.ZA12_o(ZA_o[12]),
.ZA13_i(ZA_i[13]),
.ZA13_o(ZA_o[13]),
.ZA14_i(ZA_i[14]),
.ZA14_o(ZA_o[14]),
.ZA15_i(ZA_i[15]),
.ZA15_o(ZA_o[15]),
.ZD0(ZD0_i),
.n_FDWR(FDWR),
.n_FDC(FDC),
.n_ROM(ROM),
.n_ASEL(ASEL),
.n_CAS2(CAS2),
.n_RAS2(RAS2),
.n_CE0(CE0),
.n_VTOZ(VZ),
.n_ZTOV(ZV),
.n_SRES(SRES),
.n_IO(IO),
.n_M3(M3),
.n_CART(CART),
.pin99(w353),
.pin100(w310)
);
endmodule |
module pad_inout ( read_enable, vout_from_core, vin_to_core, pad );
input read_enable;
input vout_from_core;
output vin_to_core;
inout pad;
bufif0 (pad, vout_from_core, read_enable);
assign vin_to_core = pad;
endmodule // pad_inout |
module Z80 (CLK, A, D, n_RFSH, n_M1, n_RESET, n_BUSACK, n_BUSREQ, n_WAIT, n_RD, n_WR, n_IORQ, n_MREQ, n_HALT, n_NMI, n_INT);
input CLK;
output [15:0] A;
inout [7:0] D;
output n_RFSH;
output n_M1;
input n_RESET;
output n_BUSACK;
input n_BUSREQ;
input n_WAIT;
output n_RD;
output n_WR;
output n_IORQ;
output n_MREQ;
output n_HALT;
input n_NMI;
input n_INT;
pad_inout DataPads [7:0] ();
endmodule // Z80 |
module shift_register #(
parameter WIDTH = 8
)(
input wire clk,
input wire rst,
input wire enable,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out,
input wire scan_enable,
input wire scan_in,
output wire scan_out
);
reg [WIDTH-1:0] internal_data;
// Shift register operation
always @(posedge clk) begin
if (rst) begin
internal_data <= {WIDTH{1'b0}};
end else if (scan_enable) begin
if (WIDTH == 1) begin
internal_data <= scan_in;
end else begin
internal_data <= {internal_data[WIDTH-2:0], scan_in};
end
end else if (enable) begin
internal_data <= data_in;
end
end
// Output assignment
assign data_out = internal_data;
assign scan_out = internal_data[WIDTH-1];
endmodule |
module user_proj_example #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output reg wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [15:0] io_in,
output [15:0] io_out,
output [15:0] io_oeb,
// IRQ
output [2:0] irq
);
wire clk;
wire rst;
wire [15:0] io_in;
wire [15:0] io_out;
wire [15:0] io_oeb;
wire [7:0] wbs_adr_int;
wire [15:0] rdata;
wire [15:0] wdata;
wire [15:0] count;
wire valid;
wire [3:0] wstrb;
wire [31:0] la_write;
wire [7:0] p0_io_out;
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
//assign wbs_dat_o = rdata;
//assign wdata = wbs_dat_i[15:0];
assign io_oeb = {8'hff, 8'h00}; //top 8 bits are inputs, bottom 8 bits are outputs
reg[7:0] io_in_reg_pipe;
reg[7:0] io_in_reg;
always @(posedge clk) begin
io_in_reg_pipe <= io_in[15:8];
io_in_reg <= io_in_reg_pipe;
end
// IO
assign io_out[7:0] = p0_io_out;
// IRQ
assign irq[2:1] = 2'b00; // Unused
wire p0_halt_out;
reg [31:0] p0_scan_io;
reg [31:0] p0_scan_wbs;
wire p0_irq_out;
wire [7:0] p0_sig_in;
wire [5:0] p0_sig_out;
reg [7:0] p0_sig_in_reg;
assign p0_sig_in = p0_sig_in_reg;
reg p0_scan_go;
reg p0_scan_enable;
reg [4:0] p0_scan_cnt;
reg p0_scan_in_progress;
reg p0_scan_done_strobe;
wire p0_scan_in = p0_scan_io[31];
wire p0_scan_out;
reg p0_proc_go;
wire p0_scan_in_final, p0_scan_enable_final, p0_proc_en_final;
// // Assuming LA probes [63:32] are for controlling the count register
// assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
// // Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
assign p0_scan_in_final = (~la_oenb[66]) ? la_data_in[66]: p0_scan_in;
assign p0_scan_enable_final = (~la_oenb[67]) ? la_data_in[67]: p0_scan_enable;
assign p0_proc_en_final = (~la_oenb[68]) ? la_data_in[68]: p0_proc_go;
// LA
assign la_data_out = {23'b0, //23
p0_proc_en_final, //1
p0_halt_out, //1
p0_irq_out, //1
p0_scan_enable_final, //1
p0_scan_enable, //1
p0_scan_in_final, //1
p0_scan_in, //1
p0_scan_out, //1
p0_proc_go, //1
p0_scan_done_strobe, //1
p0_scan_in_progress, //1
p0_scan_go, //1
p0_scan_cnt, //5
p0_sig_in_reg, //8
p0_io_out, //8
io_in_reg, //8
p0_scan_wbs, //32
p0_scan_io}; //32
//initial $display("Hello world!");
always@(posedge clk) begin
wbs_ack_o <= 0;
if(rst) begin
p0_scan_wbs <= 0;
p0_proc_go <= 0;
p0_scan_go <= 0;
p0_sig_in_reg <= 0;
end else begin
if(p0_scan_done_strobe) begin
p0_scan_go <= 0;
p0_scan_wbs <= p0_scan_io;
$display("p0_scan_io unloading, = %b", p0_scan_io);
end
if(valid) begin
wbs_ack_o <= 1;
if(wbs_adr_i[7:0] == 8'h00) begin
if(wstrb[0])
//$display("setting p0_scan_wbs[7:0] to %h", wbs_dat_i[7:0]);
p0_scan_wbs[7:0] <= wbs_dat_i[7:0];
if(wstrb[1])
//$display("setting p0_scan_wbs[15:8] to %h", wbs_dat_i[15:8]);
p0_scan_wbs[15:8] <= wbs_dat_i[15:8];
if(wstrb[2])
//$display("setting p0_scan_wbs[23:16] to %h", wbs_dat_i[23:16]);
p0_scan_wbs[23:16] <= wbs_dat_i[23:16];
if(wstrb[3])
//$display("setting p0_scan_wbs[31:24] to %h", wbs_dat_i[31:24]);
p0_scan_wbs[31:24] <= wbs_dat_i[31:24];
end else if(wbs_adr_i[7:0] == 8'h04) begin
if(wstrb[0]) begin
if(wbs_dat_i[0] == 1'b1)
p0_scan_go <= 1;
p0_proc_go <= wbs_dat_i[1];
end
end else if(wbs_adr_i[7:0] == 8'h08) begin
if(wstrb[0]) begin
p0_sig_in_reg <= wbs_dat_i[7:0];
end
end
end
end
end
reg p0_scan_first_cycle = 0;
always@(posedge clk) begin
p0_scan_done_strobe <= 0;
p0_scan_enable <= 0;
if(rst) begin
p0_scan_in_progress <= 0;
p0_scan_first_cycle <= 0;
p0_scan_cnt <= 0;
p0_scan_io <= 0;
end else begin
if(p0_scan_go==1 &&
p0_scan_in_progress == 0 &&
p0_proc_go == 0 &&
p0_scan_first_cycle == 0 &&
p0_scan_done_strobe==0) begin
//$display("p0_scan_io loading, = %h", p0_scan_wbs);
p0_scan_io <= p0_scan_wbs;
p0_scan_cnt <= 5'd31;
p0_scan_first_cycle <= 1;
end else if(p0_scan_first_cycle == 1) begin
p0_scan_in_progress <= 1;
p0_scan_first_cycle <= 0;
p0_scan_enable <= 1;
end else if(p0_scan_in_progress == 1) begin
p0_scan_io <= (p0_scan_io << 1) | p0_scan_out;
if(p0_scan_cnt != 0) begin
p0_scan_enable <= 1;
p0_scan_cnt <= p0_scan_cnt - 1;
end else begin
p0_scan_in_progress <= 0;
p0_scan_done_strobe <= 1;
end
end else if(p0_scan_done_strobe == 1) begin
//p0_scan_enable <= 1;
; //nothing to do here
end
end
end
accumulator_microcontroller #(
.MEM_SIZE(256)
) qtcore_C1_p0 (
.clk(clk),
.rst(rst),
.scan_enable(p0_scan_enable_final),
.scan_in(p0_scan_in_final),
.scan_out(p0_scan_out),
.proc_en(p0_proc_en_final),
.halt(p0_halt_out),
.IO_in(io_in_reg),
.IO_out(p0_io_out),
.INT_out(p0_irq_out),
.SIG_IN(p0_sig_in),
.SIG_OUT(p0_sig_out)
);
assign irq[0] = p0_irq_out & p0_proc_go;
assign wbs_dat_o = (wbs_adr_i[7:0] == 8'h00) ? {p0_scan_wbs} :
(wbs_adr_i[7:0] == 8'h04) ? {29'h0, p0_halt_out, p0_proc_go, p0_scan_enable} :
(wbs_adr_i[7:0] == 8'h08) ? {24'h0, p0_sig_in_reg} :
{26'h0, p0_sig_out};
endmodule |
module memory_bank #(
parameter ADDR_WIDTH = 5,
parameter DATA_WIDTH = 8,
parameter MEM_SIZE = 32
)(
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] address,
input wire [DATA_WIDTH-1:0] data_in,
input wire write_enable,
output reg [DATA_WIDTH-1:0] data_out,
input wire scan_enable,
input wire scan_in,
output wire scan_out
);
// Generate an array of shift registers for the memory
wire [DATA_WIDTH-1:0] mem_data_out [0:MEM_SIZE-1];
wire mem_scan_out [0:MEM_SIZE-1];
genvar i;
generate
for (i = 0; i < MEM_SIZE; i = i + 1) begin : memory
shift_register #(
.WIDTH(DATA_WIDTH)
) mem_cell (
.clk(clk),
.rst(rst),
.enable(write_enable && (address == i)),
.data_in(data_in),
.data_out(mem_data_out[i]),
.scan_enable(scan_enable),
.scan_in(i == 0 ? scan_in : mem_scan_out[i-1]),
.scan_out(mem_scan_out[i])
);
end
endgenerate
// Read operation
integer idx;
always @(*) begin
data_out = {DATA_WIDTH{1'b0}};
for (idx = 0; idx < MEM_SIZE; idx = idx + 1) begin
if (address == idx) begin
data_out = mem_data_out[idx];
end
end
//data_out = mem_data_out[address];
end
// Scan chain output
assign scan_out = mem_scan_out[MEM_SIZE-1];
endmodule |
module control_unit (
input wire clk, // Clock input
input wire rst, // Reset input
input wire processor_enable, // Processor enable signal
input wire illegal_segment_execution, // Signal for illegal segment execution
output reg processor_halted, // Processor halted signal
input wire [7:0] instruction, // Input from the Instruction Register (IR)
input wire ZF, // Zero Flag input, true when ACC is zero
output reg PC_write_enable, // Enables writing to the PC
output reg [1:0] PC_mux_select, // Selects the input for the PC multiplexer
// 00: PC + 1 (FETCH cycle)
// 01: ACC (JMP, JSR)
// 10: PC + Immediate (BEQ_FWD, BNE_FWD, BRA_FWD)
// 11: PC - Immediate (BEQ_BWD, BNE_BWD, BRA_BWD)
output reg ACC_write_enable, // Enables writing to the ACC
output reg [1:0] ACC_mux_select, // Selects the input for the ACC multiplexer
// 00: ALU output
// 01: Memory contents (LDA, LDAR)
// 10: PC + 1 (JSR)
// 11: CSR[RRR] (CSR)
output reg IR_load_enable, // Enables loading new instruction into IR from memory
output wire [3:0] ALU_opcode, // Control signal specifying the ALU operation
output reg ALU_inputB_mux_select, // Selects input B for the ALU multiplexer
// 0: Memory contents (ADD, SUB, AND, OR, XOR)
// 1: Immediate (ADDI)
output reg Memory_write_enable, // Enables writing to memory (STA)
output reg [1:0] Memory_address_mux_select, // Selects input for memory address multiplexer
// 00: {Seg, IR[3:0]} (LDA, STA, ADD, SUB, AND, OR, XOR)
// 01: ACC (LDAR)
// 10: PC (Instruction fetching)
output reg CSR_write_enable, // Enables writing to CSR[RRR] (CSW)
output reg SEG_write_enable, // Enables writing to the Segment Register
output reg [1:0] SEG_mux_select, // Selects the input for the Segment Register multiplexer
// 00: Immediate value (SETSEG)
// 01: ACC value (SETSEG_ACC)
// Scan chain signals
input wire scan_enable, // Scan chain enable signal
input wire scan_in, // Scan chain input
output wire scan_out // Scan chain output
);
// Define state constants
localparam STATE_RESET = 3'b000;
localparam STATE_FETCH = 3'b001;
localparam STATE_EXECUTE = 3'b010;
localparam STATE_HALT = 3'b100;
// Instantiate shift register for state storage (one-hot encoding)
reg [2:0] state_in;
wire [2:0] state_out;
// Instantiate shift register for new 'reserved' connection (one-bit)
reg reserved_in = 1'b0; // Permanently setting to 0
wire reserved_scan_out; // New wire to connect scan_out of reserved_register to scan_in of state_register
shift_register #(
.WIDTH(1)
) reserved_register (
.clk(clk),
.rst(rst),
.enable(1'b0), // Permanently setting enable to 0
.data_in(reserved_in),
.data_out(), // Not used
.scan_enable(scan_enable),
.scan_in(scan_in), // Taking top-level scan_in
.scan_out(reserved_scan_out) // Connecting to new wire reserved_scan_out
);
// Then, connect this output to your existing state_register's scan_in:
// Instantiate shift register for state storage (one-hot encoding)
shift_register #(
.WIDTH(3)
) state_register (
.clk(clk),
.rst(rst),
.enable(processor_enable),
.data_in(state_in),
.data_out(state_out),
.scan_enable(scan_enable),
.scan_in(reserved_scan_out), // Now connected to new wire from reserved register's scan_out
.scan_out(scan_out) // Output connected to top-level scan_out
);
always @(*) begin
// Default state: stay in the current state
state_in = state_out;
// Default processor_halted: set to 0
processor_halted = 0;
// Only advance state and update processor_halted if processor_enable is asserted
if (processor_enable) begin
case (state_out)
STATE_RESET: begin
// Move to STATE_FETCH when reset input is low
if (!rst) begin
state_in = STATE_FETCH;
end
end
STATE_FETCH: begin
// If the processor is halted or illegal segment execution, stay in the HALT state
if (instruction == 8'b11111111 || illegal_segment_execution) begin
state_in = STATE_HALT;
end
// Otherwise, move to the EXECUTE state
else begin
state_in = STATE_EXECUTE;
end
end
STATE_EXECUTE: begin
// If the processor is halted or illegal segment execution, move to the HALT state
if (instruction == 8'b11111111 || illegal_segment_execution) begin
state_in = STATE_HALT;
end
// Otherwise, move back to the FETCH state
else begin
state_in = STATE_FETCH;
end
end
STATE_HALT: begin
// Stay in HALT state unless reset occurs
if (rst) begin
state_in = STATE_FETCH;
end
// Otherwise, maintain the HALT state and set processor_halted
else begin
processor_halted = 1;
end
end
default: begin
// Default behavior (should never be reached in this implementation)
state_in = STATE_FETCH;
processor_halted = 0;
end
endcase
end
end
always @(*) begin
// Default values
ACC_write_enable = 1'b0;
ACC_mux_select = 2'b00;
// Check if the processor is enabled
if (processor_enable) begin
// Check if the current state is EXECUTE
if (state_out == STATE_EXECUTE) begin
// Handle instructions where ACC is written with ALU output
case (instruction[7:4])
4'b0010, // ADD
4'b0011, // SUB
4'b0100, // AND
4'b0101, // OR
4'b0110, // XOR
4'b1000, // ADDI
4'b1001: // LUI
begin
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b00; // ALU output
end
default: ; // Do nothing for other opcodes
endcase
// Handle instructions where ACC is written with memory contents
case (instruction[7:4])
4'b0000: // LDA
begin
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b01; // Memory contents
end
default: ; // Do nothing for other opcodes
endcase
// Control/Status Register Manipulation Instructions
case (instruction[7:3])
5'b10110: begin // CSR
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b11; // CSR[RRR]
end
default: ; // Do nothing for other opcodes
endcase
// Fixed Control and Branching Instructions
case (instruction[7:0])
8'b11110001: begin // JSR
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b10; // PC + 1
end
default: ; // Do nothing for other opcodes
endcase
// Data Manipulation Instructions
case (instruction[7:0])
8'b11110110, // SHL
8'b11110111, // SHR
8'b11111000, // ROL
8'b11111001, // ROR
8'b11111100, // DEC
8'b11111101, // CLR
8'b11111110: // INV
begin
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b00; // ALU output
end
8'b11111010: begin // LDAR
ACC_write_enable = 1'b1;
ACC_mux_select = 2'b01; // Memory contents
end
default: ; // Do nothing for other opcodes
endcase
end
end
end
always @(*) begin
// Default: IR_load_enable is 0 (disabled)
IR_load_enable = 1'b0;
if (processor_enable) begin
// During FETCH cycle, set IR_load_enable to 1 (enabled)
if (state_out == STATE_FETCH) begin
IR_load_enable = 1'b1;
end
end
end
always @(*) begin
// Default values
Memory_write_enable = 1'b0;
Memory_address_mux_select = 2'b00; // Default to IR[3:0]
// Check if processor is enabled
if (processor_enable) begin
// Check if the current state is EXECUTE
if (state_out == STATE_EXECUTE) begin
case (instruction[7:4])
4'b0001: begin // STA
Memory_write_enable = 1'b1;
end
default: ; // Do nothing for other opcodes
endcase
// Check if the current instruction is LDAR
if (instruction == 8'b11111010) begin
Memory_address_mux_select = 2'b01;
end
end
// Instruction fetch cycle uses PC as memory address
else if (state_out == STATE_FETCH) begin
Memory_address_mux_select = 2'b10;
end
end
end
always @(*) begin
if (processor_enable) begin
SEG_write_enable = 1'b0;
SEG_mux_select = 2'b00;
if (state_out == STATE_EXECUTE) begin
// Immediate Data Manipulation Instructions
if (instruction[7:4] == 4'b1010) begin // SETSEG
SEG_write_enable = 1'b1;
SEG_mux_select = 2'b00; // Immediate value
end
// Data Manipulation Instructions
if (instruction[7:0] == 8'b11111011) begin // SETSEG_ACC
SEG_write_enable = 1'b1;
SEG_mux_select = 2'b01; // ACC[3:0]
end
end
end else begin
SEG_write_enable = 1'b0;
SEG_mux_select = 2'b00;
end
end
instruction_decoder decoder (
.instruction(instruction),
.alu_opcode(ALU_opcode)
);
always @(*) begin
// Default values
PC_write_enable = 1'b0;
PC_mux_select = 2'b00;
// Only emit signals if the control unit is enabled
if (processor_enable) begin
if (state_out == STATE_FETCH) begin
// Increment the PC by 1 during FETCH
PC_write_enable = 1'b1;
PC_mux_select = 2'b00; // PC + 1
end
else if (state_out == STATE_EXECUTE) begin
// Control Flow Instructions
case (instruction[7:0])
8'b11110000: begin // JMP
PC_write_enable = 1'b1;
PC_mux_select = 2'b01; // ACC
end
8'b11110001: begin // JSR
PC_write_enable = 1'b1;
PC_mux_select = 2'b01; // ACC
end
default: ; // Do nothing for other opcodes
endcase
case (instruction[7:4])
4'b1100: begin // BEQ
if (ZF) begin
PC_write_enable = 1'b1;
PC_mux_select = instruction[3] ? 2'b11 : 2'b10; // PC + Immediate if sign is 0, PC - Immediate if sign is 1
end
end
4'b1101: begin // BNE
if (!ZF) begin
PC_write_enable = 1'b1;
PC_mux_select = instruction[3] ? 2'b11 : 2'b10; // PC + Immediate if sign is 0, PC - Immediate if sign is 1
end
end
4'b1110: begin // BRA
PC_write_enable = 1'b1;
PC_mux_select = instruction[3] ? 2'b11 : 2'b10; // PC + Immediate if sign is 0, PC - Immediate if sign is 1
end
default: ; // Do nothing for other opcodes
endcase
end
end
end
always @(*) begin
// Default value
ALU_inputB_mux_select = 1'b0; // Memory contents by default
// Only emit signals if the control unit is enabled
if (processor_enable && state_out == STATE_EXECUTE) begin
// ALU Instructions
case (instruction[7:4])
4'b1000: begin // ADDI
ALU_inputB_mux_select = 1'b1; // Immediate value
end
4'b1001: begin // LUI
ALU_inputB_mux_select = 1'b1; // Immediate value
end
default: ; // Do nothing for other opcodes
endcase
end
end
always @(*) begin
// Default values
CSR_write_enable = 1'b0;
// Check if the processor is enabled
if (processor_enable) begin
// Check if the current state is EXECUTE
if (state_out == STATE_EXECUTE) begin
// CSR Manipulation Instructions
case (instruction[7:3])
5'b10111: begin // CSW
CSR_write_enable = 1'b1;
end
default: ; // Do nothing for other opcodes
endcase
end
end
end
endmodule |
module instruction_decoder (
input wire [7:0] instruction,
output reg [3:0] alu_opcode
);
always @(*) begin
case (instruction[7:4])
4'b0000: alu_opcode = 4'b0000; // LDA
4'b0001: alu_opcode = 4'b0000; // STA
4'b0010: alu_opcode = 4'b0000; // ADD
4'b0011: alu_opcode = 4'b0001; // SUB
4'b0100: alu_opcode = 4'b0010; // AND
4'b0101: alu_opcode = 4'b0011; // OR
4'b0110: alu_opcode = 4'b0100; // XOR
4'b1000: alu_opcode = 4'b0000; // ADDI
4'b1001: alu_opcode = 4'b0101; // LUI
4'b1010: alu_opcode = 4'b0000; // SETSEG
4'b1011: alu_opcode = 4'b0000; // CSR, CSW
4'b1111: begin // Control and Data Manipulation Instructions
case (instruction[3:0])
4'b0110: alu_opcode = 4'b0110; // SHL
4'b0111: alu_opcode = 4'b0111; // SHR
4'b1000: alu_opcode = 4'b1000; // ROL
4'b1001: alu_opcode = 4'b1001; // ROR
4'b1100: alu_opcode = 4'b1010; // DEC
4'b1101: alu_opcode = 4'b1100; // CLR
4'b1110: alu_opcode = 4'b1011; // INV
default: alu_opcode = 4'b0000;
endcase
end
default: alu_opcode = 4'b0000;
endcase
end
endmodule |
module Control_Status_Registers #(
parameter WIDTH = 8
)(
input wire clk,
input wire rst,
input wire [2:0] addr,
input wire [WIDTH-1:0] data_in,
input wire wr_enable,
input wire [WIDTH-1:0] IO_IN,
input wire [WIDTH-1:0] SIG_IN, // New input signal SIG_IN
input wire processor_enable,
input wire scan_enable,
input wire scan_in,
output wire [WIDTH-1:0] data_out,
output wire [WIDTH-1:0] SEGEXE_L_OUT,
output wire [WIDTH-1:0] SEGEXE_H_OUT,
output wire [WIDTH-1:0] IO_OUT,
output wire [5:0] SIG_OUT, // New output signal SIG_OUT
output wire INT_OUT,
output wire scan_out
);
wire [WIDTH-1:0] segexe_l_data;
wire [WIDTH-1:0] segexe_h_data;
wire [WIDTH-1:0] io_in_data;
wire [WIDTH-1:0] io_out_data;
wire [WIDTH-1:0] cnt_l_data;
wire [WIDTH-1:0] cnt_h_data;
wire [WIDTH-1:0] status_ctrl_data;
wire [WIDTH-1:0] temp_data;
wire segexe_l_scan_out;
wire segexe_h_scan_out;
wire io_in_scan_out;
wire io_out_scan_out;
wire cnt_l_scan_out;
wire cnt_h_scan_out;
wire status_ctrl_scan_out;
wire temp_scan_out;
shift_register #(.WIDTH(WIDTH)) segexe_l_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b000)),
.data_in(data_in),
.data_out(segexe_l_data),
.scan_enable(scan_enable),
.scan_in(scan_in),
.scan_out(segexe_l_scan_out)
);
shift_register #(.WIDTH(WIDTH)) segexe_h_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b001)),
.data_in(data_in),
.data_out(segexe_h_data),
.scan_enable(scan_enable),
.scan_in(segexe_l_scan_out),
.scan_out(segexe_h_scan_out)
);
shift_register #(.WIDTH(WIDTH)) io_in_reg (
.clk(clk),
.rst(rst),
.enable(processor_enable), // Enable controlled by processor_enable
.data_in(IO_IN), // Data input is IO_IN
.data_out(io_in_data),
.scan_enable(scan_enable),
.scan_in(segexe_h_scan_out),
.scan_out(io_in_scan_out)
);
shift_register #(.WIDTH(WIDTH)) io_out_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b011)),
.data_in(data_in),
.data_out(io_out_data),
.scan_enable(scan_enable),
.scan_in(io_in_scan_out),
.scan_out(io_out_scan_out)
);
reg cnt_toggle = 0;
always @(posedge clk or posedge rst)
begin
if(rst)
cnt_toggle <= 0;
else
cnt_toggle <= ~cnt_toggle;
end
wire cnt_update_enable;
wire [15:0] cnt_update = {cnt_h_data, cnt_l_data} + 1'b1;
wire cnt_enable = cnt_update_enable & cnt_toggle & processor_enable;
shift_register #(.WIDTH(WIDTH)) cnt_l_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b100) | cnt_enable),
.data_in(wr_enable ? data_in : cnt_update[7:0]),
.data_out(cnt_l_data),
.scan_enable(scan_enable),
.scan_in(io_out_scan_out),
.scan_out(cnt_l_scan_out)
);
shift_register #(.WIDTH(WIDTH)) cnt_h_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b101) | cnt_enable),
.data_in(wr_enable ? data_in : cnt_update[15:8]),
.data_out(cnt_h_data),
.scan_enable(scan_enable),
.scan_in(cnt_l_scan_out),
.scan_out(cnt_h_scan_out)
);
shift_register #(.WIDTH(WIDTH)) status_ctrl_reg (
.clk(clk),
.rst(rst),
.enable(wr_enable & (addr == 3'b110)),
.data_in(data_in),
.data_out(status_ctrl_data),
.scan_enable(scan_enable),
.scan_in(cnt_h_scan_out),
.scan_out(status_ctrl_scan_out)
);
shift_register #(.WIDTH(WIDTH)) sig_in_reg (
.clk(clk),
.rst(rst),
.enable(processor_enable), // Enable controlled by processor_enable
.data_in(SIG_IN), // Data input is SIG_IN
.data_out(temp_data),
.scan_enable(scan_enable),
.scan_in(status_ctrl_scan_out),
.scan_out(scan_out)
);
assign data_out = (addr == 3'b000) ? segexe_l_data :
(addr == 3'b001) ? segexe_h_data :
(addr == 3'b010) ? io_in_data :
(addr == 3'b011) ? io_out_data :
(addr == 3'b100) ? cnt_l_data :
(addr == 3'b101) ? cnt_h_data :
(addr == 3'b110) ? status_ctrl_data :
temp_data;
assign SEGEXE_L_OUT = segexe_l_data;
assign SEGEXE_H_OUT = segexe_h_data;
assign IO_OUT = io_out_data;
assign INT_OUT = status_ctrl_data[0]; // INT_OUT is the bottom bit of status_ctrl_data
assign cnt_update_enable = status_ctrl_data[1];
assign SIG_OUT = status_ctrl_data[WIDTH-1:WIDTH-6]; // SIG_OUT is the top 6 bits of status_ctrl_data
endmodule |
module accumulator_microcontroller #(
parameter MEM_SIZE = 256 // Set MEM_SIZE to 256 by default
)
(
input wire clk,
input wire rst,
input wire scan_enable,
input wire scan_in,
output wire scan_out,
input wire proc_en,
output wire halt,
input wire [7:0] IO_in, // Updated to 8-bit IO_in bus
output wire [7:0] IO_out, // Updated to 8-bit IO_out bus
output wire INT_out, // New interrupt output
input wire [7:0] SIG_IN, // New signal input SIG_IN
output wire [5:0] SIG_OUT // New signal output SIG_OUT
);
// Internal Wires
// Wires between the Control Unit and the Datapath
wire PC_write_enable, ACC_write_enable, IR_load_enable, Memory_write_enable, CSR_write_enable, SEG_write_enable;
wire [1:0] PC_mux_select, ACC_mux_select, Memory_address_mux_select, SEG_mux_select;
wire [3:0] ALU_opcode;
wire ALU_inputB_mux_select;
wire illegal_segment_execution;
wire ZF; // zero flag from ALU
// PC - Program Counter
wire [7:0] PC, PC_plus_one, PC_plus_offset, PC_minus_offset, next_PC;
// ACC - Accumulator
wire [7:0] ACC, next_ACC;
// IR - Instruction Register
wire [7:0] IR, next_IR;
// SEG - Segment Register
wire [3:0] SEG, next_SEG;
// ALU - Arithmetic and Logic Unit
wire [7:0] ALU_result;
// Memory
wire [7:0] M_address;
wire [7:0] M_data_in, M_data_out;
// CSR - Control/Status Register
wire [2:0] CSR_address;
wire [7:0] CSR_data_in, CSR_data_out;
// Immediate Values
wire [7:0] IMM;
// Sign + Offset for Branching Instructions
wire sign;
wire [2:0] offset;
// Scan chain
wire scan_in_PC, scan_out_PC; // Scan chain connections for PC
wire scan_in_ACC, scan_out_ACC; // Scan chain connections for ACC
wire scan_in_IR, scan_out_IR; // Scan chain connections for IR
wire scan_in_SEG, scan_out_SEG; // Scan chain connections for SEG
wire scan_in_memory, scan_out_memory; // Scan chain connections for memory
wire scan_in_CSR, scan_out_CSR; // Scan chain connections for CSR
// Define scan chain wires for Control Unit
wire scan_in_CU, scan_out_CU;
control_unit ctrl_unit (
.clk(clk), // Connected to the clock
.rst(rst), // Connected to the reset signal
.processor_enable(proc_en), // Connected to the processor enable signal
.illegal_segment_execution(illegal_segment_execution), // Illegal segment execution signal
.processor_halted(halt), // Connected to the processor halted signal
.instruction(IR), // Connected to the instruction register output
.ZF(ZF), // Zero Flag input from ALU
.PC_write_enable(PC_write_enable), // Enables writing to the PC
.PC_mux_select(PC_mux_select), // Selects the input for the PC multiplexer
.ACC_write_enable(ACC_write_enable), // Enables writing to the ACC
.ACC_mux_select(ACC_mux_select), // Selects the input for the ACC multiplexer
.IR_load_enable(IR_load_enable), // Enables loading new instruction into IR from memory
.ALU_opcode(ALU_opcode), // Control signal specifying the ALU operation
.ALU_inputB_mux_select(ALU_inputB_mux_select), // Selects input B for the ALU multiplexer
.Memory_write_enable(Memory_write_enable), // Enables writing to memory
.Memory_address_mux_select(Memory_address_mux_select), // Selects input for memory address multiplexer
.CSR_write_enable(CSR_write_enable), // Enables writing to CSR
.SEG_write_enable(SEG_write_enable), // Enables writing to the Segment Register
.SEG_mux_select(SEG_mux_select), // Selects the input for the Segment Register multiplexer
.scan_enable(scan_enable), // Scan chain enable signal
.scan_in(scan_in_CU), // Scan chain input
.scan_out(scan_out_CU) // Scan chain output
);
// Multiplexer for selecting SEG input
wire [3:0] SEG_input;
wire [3:0] IMM4 = IR[3:0]; // Immediate 4-bit value from instruction
assign SEG_input = (SEG_mux_select) ? ACC[3:0] : IMM4;
// SEG register instantiation
shift_register #(
.WIDTH(4) // Set width to 4 bits
) SEG_Register (
.clk(clk),
.rst(rst),
.enable(SEG_write_enable),
.data_in(SEG_input),
.data_out(SEG),
.scan_enable(scan_enable),
.scan_in(scan_in_SEG),
.scan_out(scan_out_SEG)
);
// Define a 3-bit immediate value from the bottom three bits of the IR
wire [2:0] IMM3 = IR[2:0];
// Multiplexer for selecting PC input
wire [7:0] PC_input;
assign PC_input = (PC_mux_select == 2'b00) ? PC + 8'b00000001 : // PC + 1 for FETCH cycle
(PC_mux_select == 2'b01) ? ACC : // ACC for JMP and JSR
(PC_mux_select == 2'b10) ? PC + {5'b0, IMM3} - 1 : // PC + IMM - 1 for forward branches
PC - {5'b0, IMM3} - 1; // PC - IMM - 1 for backward branches
// PC register instantiation
shift_register #(
.WIDTH(8) // Set width to 8 bits
) PC_Register (
.clk(clk),
.rst(rst),
.enable(PC_write_enable),
.data_in(PC_input),
.data_out(PC),
.scan_enable(scan_enable), // Scan chain enable signal
.scan_in(scan_in_PC), // Scan chain input
.scan_out(scan_out_PC) // Scan chain output
);
// IR register instantiation
shift_register #(
.WIDTH(8) // Set width to 8 bits
) IR_Register (
.clk(clk),
.rst(rst),
.enable(IR_load_enable),
.data_in(M_data_out),
.data_out(IR),
.scan_enable(scan_enable), // Scan chain enable signal
.scan_in(scan_in_IR), // Scan chain input
.scan_out(scan_out_IR) // Scan chain output
);
// Multiplexer for selecting ACC input
wire [7:0] ACC_input;
assign ACC_input = (ACC_mux_select == 2'b00) ? ALU_result :
(ACC_mux_select == 2'b01) ? M_data_out :
(ACC_mux_select == 2'b10) ? PC :
CSR_data_out;
// ACC register instantiation
shift_register #(
.WIDTH(8) // Set width to 8 bits
) ACC_Register (
.clk(clk),
.rst(rst),
.enable(ACC_write_enable),
.data_in(ACC_input),
.data_out(ACC),
.scan_enable(scan_enable), // Scan chain enable signal
.scan_in(scan_in_ACC), // Scan chain input
.scan_out(scan_out_ACC) // Scan chain output
);
// Define the ALU B input multiplexer
wire [7:0] ALU_inputB;
assign IMM = IR[3:0];
assign ALU_inputB = (ALU_inputB_mux_select == 1'b0) ? M_data_out : IMM;
// ALU instantiation
alu ALU (
.A(ACC),
.B(ALU_inputB),
.opcode(ALU_opcode),
.Y(ALU_result)
);
// Multiplexer for selecting the memory address input
wire [7:0] M_address_input;
assign M_address_input = (Memory_address_mux_select == 2'b00) ? {SEG, IR[3:0]} :
(Memory_address_mux_select == 2'b01) ? ACC :
PC;
// Memory bank instantiation
memory_bank #(
.ADDR_WIDTH(8),
.DATA_WIDTH(8),
.MEM_SIZE(MEM_SIZE)
) mem_bank (
.clk(clk),
.rst(rst),
.address(M_address_input), // Connect the multiplexer output to the memory bank's address input
.data_in(ACC), // Example connection, replace with appropriate input
.write_enable(Memory_write_enable), // Connect the control unit's memory write enable signal
.data_out(M_data_out), // Example connection, replace with appropriate output
.scan_enable(scan_enable), // Scan chain enable signal
.scan_in(scan_in_memory), // Scan chain input
.scan_out(scan_out_memory) // Scan chain output
);
wire [7:0] SEGEXE_L_OUT; // Declare new wire for SEGEXE_L_OUT
wire [7:0] SEGEXE_H_OUT; // Declare new wire for SEGEXE_H_OUT
wire [2:0] CSR_addr; // Renamed wire for CSR address
// Extract bottom 3 bits of the output of the instruction register (IR)
assign CSR_addr = IR[2:0];
Control_Status_Registers #(
.WIDTH(8) // Set WIDTH to 8
) csr_inst (
.clk(clk),
.rst(rst),
.addr(CSR_addr), // Connect CSR_addr to the bottom 3 bits of IR
.data_in(ACC), // Connect data_in to ACC
.wr_enable(CSR_write_enable), // Connect wr_enable to CSR_write_enable
.IO_IN(IO_in), // Connect IO_in to IO_IN
.SIG_IN(SIG_IN), // Connect SIG_IN to SIG_IN
.processor_enable(proc_en), // Connect processor_enable to top-level proc_en
.scan_enable(scan_enable),
.scan_in(scan_in_CSR), // Renamed scan_in signal as scan_in_CSR
.scan_out(scan_out_CSR), // Renamed scan_out signal as scan_out_CSR
.data_out(CSR_data_out), // Connect data_out to CSR_data_out
.SEGEXE_L_OUT(SEGEXE_L_OUT), // Connect SEGEXE_L_OUT to new wire
.SEGEXE_H_OUT(SEGEXE_H_OUT), // Connect SEGEXE_H_OUT to new wire
.IO_OUT(IO_out), // Connect IO_out to IO_OUT
.SIG_OUT(SIG_OUT), // Connect SIG_OUT to SIG_OUT
.INT_OUT(INT_out)
);
assign scan_in_CU = scan_in; // Input to Control Unit (CU)
assign scan_in_SEG = scan_out_CU; // Input to SEG register
assign scan_in_PC = scan_out_SEG; // Input to PC register
assign scan_in_IR = scan_out_PC; // Input to IR register
assign scan_in_ACC = scan_out_IR; // Input to ACC register
assign scan_in_CSR = scan_out_ACC; // Input to CSR module
assign scan_in_memory = scan_out_CSR; // Input to memory bank
assign scan_out = scan_out_memory; // Output of memory bank (final scan chain output)
assign ZF = (ACC == 8'b00000000); // Set ZF to 1 when ACC is 0, otherwise 0
// Extracting the segment address from the upper 4 bits of PC
wire [3:0] seg_addr;
assign seg_addr = PC[7:4];
// Instantiating the SegmentCheck module
SegmentCheck Segment_Check (
.seg_addr(seg_addr),
.SEGEXE_H(SEGEXE_H_OUT),
.SEGEXE_L(SEGEXE_L_OUT),
.illegal_segment_address(illegal_segment_execution)
);
endmodule |
module SegmentCheck(
input wire [3:0] seg_addr,
input wire [7:0] SEGEXE_H,
input wire [7:0] SEGEXE_L,
output reg illegal_segment_address
);
always @(*) begin
if (seg_addr < 8) begin
illegal_segment_address = SEGEXE_L[seg_addr] == 1'b0;
end
else if (seg_addr < 16) begin
illegal_segment_address = SEGEXE_H[seg_addr-8] == 1'b0;
end
else begin
illegal_segment_address = 1'b1; // By default, indicate illegal if out of 16
end
end
endmodule |
module alu (
input wire [7:0] A,
input wire [7:0] B,
input wire [3:0] opcode,
output reg [7:0] Y
);
always @(*) begin
case (opcode)
4'b0000: Y = A + B; // ADD
4'b0001: Y = A - B; // SUB
4'b0010: Y = A & B; // AND
4'b0011: Y = A | B; // OR
4'b0100: Y = A ^ B; // XOR
4'b0101: Y = B << 4; // LUI
4'b0110: Y = A << 1; // SHL
4'b0111: Y = A >> 1; // SHR
4'b1000: Y = A[6:0] | A[7] << 7; // ROL
4'b1001: Y = A[0] << 7 | A[7:1]; // ROR
4'b1010: Y = A - 1; // DEC
4'b1011: Y = ~A; // INV
default: Y = 8'b00000000; // Default case is CLR
endcase
end
endmodule |
module user_project_wrapper #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
user_proj_example mprj (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// MGMT SoC Wishbone Slave
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
// Logic Analyzer
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb (la_oenb),
// IO Pads
.io_in ({io_in[37:30],io_in[7:0]}),
.io_out({io_out[37:30],io_out[7:0]}),
.io_oeb({io_oeb[37:30],io_oeb[7:0]}),
// IRQ
.irq(user_irq)
);
endmodule // user_project_wrapper |
module user_project_wrapper (user_clock2,
wb_clk_i,
wb_rst_i,
wbs_ack_o,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
analog_io,
io_in,
io_oeb,
io_out,
la_data_in,
la_data_out,
la_oenb,
user_irq,
wbs_adr_i,
wbs_dat_i,
wbs_dat_o,
wbs_sel_i);
input user_clock2;
input wb_clk_i;
input wb_rst_i;
output wbs_ack_o;
input wbs_cyc_i;
input wbs_stb_i;
input wbs_we_i;
inout [28:0] analog_io;
input [37:0] io_in;
output [37:0] io_oeb;
output [37:0] io_out;
input [127:0] la_data_in;
output [127:0] la_data_out;
input [127:0] la_oenb;
output [2:0] user_irq;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
user_proj_example mprj (.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.io_in({io_in[37],
io_in[36],
io_in[35],
io_in[34],
io_in[33],
io_in[32],
io_in[31],
io_in[30],
io_in[7],
io_in[6],
io_in[5],
io_in[4],
io_in[3],
io_in[2],
io_in[1],
io_in[0]}),
.io_oeb({io_oeb[37],
io_oeb[36],
io_oeb[35],
io_oeb[34],
io_oeb[33],
io_oeb[32],
io_oeb[31],
io_oeb[30],
io_oeb[7],
io_oeb[6],
io_oeb[5],
io_oeb[4],
io_oeb[3],
io_oeb[2],
io_oeb[1],
io_oeb[0]}),
.io_out({io_out[37],
io_out[36],
io_out[35],
io_out[34],
io_out[33],
io_out[32],
io_out[31],
io_out[30],
io_out[7],
io_out[6],
io_out[5],
io_out[4],
io_out[3],
io_out[2],
io_out[1],
io_out[0]}),
.irq({user_irq[2],
user_irq[1],
user_irq[0]}),
.la_data_in({la_data_in[127],
la_data_in[126],
la_data_in[125],
la_data_in[124],
la_data_in[123],
la_data_in[122],
la_data_in[121],
la_data_in[120],
la_data_in[119],
la_data_in[118],
la_data_in[117],
la_data_in[116],
la_data_in[115],
la_data_in[114],
la_data_in[113],
la_data_in[112],
la_data_in[111],
la_data_in[110],
la_data_in[109],
la_data_in[108],
la_data_in[107],
la_data_in[106],
la_data_in[105],
la_data_in[104],
la_data_in[103],
la_data_in[102],
la_data_in[101],
la_data_in[100],
la_data_in[99],
la_data_in[98],
la_data_in[97],
la_data_in[96],
la_data_in[95],
la_data_in[94],
la_data_in[93],
la_data_in[92],
la_data_in[91],
la_data_in[90],
la_data_in[89],
la_data_in[88],
la_data_in[87],
la_data_in[86],
la_data_in[85],
la_data_in[84],
la_data_in[83],
la_data_in[82],
la_data_in[81],
la_data_in[80],
la_data_in[79],
la_data_in[78],
la_data_in[77],
la_data_in[76],
la_data_in[75],
la_data_in[74],
la_data_in[73],
la_data_in[72],
la_data_in[71],
la_data_in[70],
la_data_in[69],
la_data_in[68],
la_data_in[67],
la_data_in[66],
la_data_in[65],
la_data_in[64],
la_data_in[63],
la_data_in[62],
la_data_in[61],
la_data_in[60],
la_data_in[59],
la_data_in[58],
la_data_in[57],
la_data_in[56],
la_data_in[55],
la_data_in[54],
la_data_in[53],
la_data_in[52],
la_data_in[51],
la_data_in[50],
la_data_in[49],
la_data_in[48],
la_data_in[47],
la_data_in[46],
la_data_in[45],
la_data_in[44],
la_data_in[43],
la_data_in[42],
la_data_in[41],
la_data_in[40],
la_data_in[39],
la_data_in[38],
la_data_in[37],
la_data_in[36],
la_data_in[35],
la_data_in[34],
la_data_in[33],
la_data_in[32],
la_data_in[31],
la_data_in[30],
la_data_in[29],
la_data_in[28],
la_data_in[27],
la_data_in[26],
la_data_in[25],
la_data_in[24],
la_data_in[23],
la_data_in[22],
la_data_in[21],
la_data_in[20],
la_data_in[19],
la_data_in[18],
la_data_in[17],
la_data_in[16],
la_data_in[15],
la_data_in[14],
la_data_in[13],
la_data_in[12],
la_data_in[11],
la_data_in[10],
la_data_in[9],
la_data_in[8],
la_data_in[7],
la_data_in[6],
la_data_in[5],
la_data_in[4],
la_data_in[3],
la_data_in[2],
la_data_in[1],
la_data_in[0]}),
.la_data_out({la_data_out[127],
la_data_out[126],
la_data_out[125],
la_data_out[124],
la_data_out[123],
la_data_out[122],
la_data_out[121],
la_data_out[120],
la_data_out[119],
la_data_out[118],
la_data_out[117],
la_data_out[116],
la_data_out[115],
la_data_out[114],
la_data_out[113],
la_data_out[112],
la_data_out[111],
la_data_out[110],
la_data_out[109],
la_data_out[108],
la_data_out[107],
la_data_out[106],
la_data_out[105],
la_data_out[104],
la_data_out[103],
la_data_out[102],
la_data_out[101],
la_data_out[100],
la_data_out[99],
la_data_out[98],
la_data_out[97],
la_data_out[96],
la_data_out[95],
la_data_out[94],
la_data_out[93],
la_data_out[92],
la_data_out[91],
la_data_out[90],
la_data_out[89],
la_data_out[88],
la_data_out[87],
la_data_out[86],
la_data_out[85],
la_data_out[84],
la_data_out[83],
la_data_out[82],
la_data_out[81],
la_data_out[80],
la_data_out[79],
la_data_out[78],
la_data_out[77],
la_data_out[76],
la_data_out[75],
la_data_out[74],
la_data_out[73],
la_data_out[72],
la_data_out[71],
la_data_out[70],
la_data_out[69],
la_data_out[68],
la_data_out[67],
la_data_out[66],
la_data_out[65],
la_data_out[64],
la_data_out[63],
la_data_out[62],
la_data_out[61],
la_data_out[60],
la_data_out[59],
la_data_out[58],
la_data_out[57],
la_data_out[56],
la_data_out[55],
la_data_out[54],
la_data_out[53],
la_data_out[52],
la_data_out[51],
la_data_out[50],
la_data_out[49],
la_data_out[48],
la_data_out[47],
la_data_out[46],
la_data_out[45],
la_data_out[44],
la_data_out[43],
la_data_out[42],
la_data_out[41],
la_data_out[40],
la_data_out[39],
la_data_out[38],
la_data_out[37],
la_data_out[36],
la_data_out[35],
la_data_out[34],
la_data_out[33],
la_data_out[32],
la_data_out[31],
la_data_out[30],
la_data_out[29],
la_data_out[28],
la_data_out[27],
la_data_out[26],
la_data_out[25],
la_data_out[24],
la_data_out[23],
la_data_out[22],
la_data_out[21],
la_data_out[20],
la_data_out[19],
la_data_out[18],
la_data_out[17],
la_data_out[16],
la_data_out[15],
la_data_out[14],
la_data_out[13],
la_data_out[12],
la_data_out[11],
la_data_out[10],
la_data_out[9],
la_data_out[8],
la_data_out[7],
la_data_out[6],
la_data_out[5],
la_data_out[4],
la_data_out[3],
la_data_out[2],
la_data_out[1],
la_data_out[0]}),
.la_oenb({la_oenb[127],
la_oenb[126],
la_oenb[125],
la_oenb[124],
la_oenb[123],
la_oenb[122],
la_oenb[121],
la_oenb[120],
la_oenb[119],
la_oenb[118],
la_oenb[117],
la_oenb[116],
la_oenb[115],
la_oenb[114],
la_oenb[113],
la_oenb[112],
la_oenb[111],
la_oenb[110],
la_oenb[109],
la_oenb[108],
la_oenb[107],
la_oenb[106],
la_oenb[105],
la_oenb[104],
la_oenb[103],
la_oenb[102],
la_oenb[101],
la_oenb[100],
la_oenb[99],
la_oenb[98],
la_oenb[97],
la_oenb[96],
la_oenb[95],
la_oenb[94],
la_oenb[93],
la_oenb[92],
la_oenb[91],
la_oenb[90],
la_oenb[89],
la_oenb[88],
la_oenb[87],
la_oenb[86],
la_oenb[85],
la_oenb[84],
la_oenb[83],
la_oenb[82],
la_oenb[81],
la_oenb[80],
la_oenb[79],
la_oenb[78],
la_oenb[77],
la_oenb[76],
la_oenb[75],
la_oenb[74],
la_oenb[73],
la_oenb[72],
la_oenb[71],
la_oenb[70],
la_oenb[69],
la_oenb[68],
la_oenb[67],
la_oenb[66],
la_oenb[65],
la_oenb[64],
la_oenb[63],
la_oenb[62],
la_oenb[61],
la_oenb[60],
la_oenb[59],
la_oenb[58],
la_oenb[57],
la_oenb[56],
la_oenb[55],
la_oenb[54],
la_oenb[53],
la_oenb[52],
la_oenb[51],
la_oenb[50],
la_oenb[49],
la_oenb[48],
la_oenb[47],
la_oenb[46],
la_oenb[45],
la_oenb[44],
la_oenb[43],
la_oenb[42],
la_oenb[41],
la_oenb[40],
la_oenb[39],
la_oenb[38],
la_oenb[37],
la_oenb[36],
la_oenb[35],
la_oenb[34],
la_oenb[33],
la_oenb[32],
la_oenb[31],
la_oenb[30],
la_oenb[29],
la_oenb[28],
la_oenb[27],
la_oenb[26],
la_oenb[25],
la_oenb[24],
la_oenb[23],
la_oenb[22],
la_oenb[21],
la_oenb[20],
la_oenb[19],
la_oenb[18],
la_oenb[17],
la_oenb[16],
la_oenb[15],
la_oenb[14],
la_oenb[13],
la_oenb[12],
la_oenb[11],
la_oenb[10],
la_oenb[9],
la_oenb[8],
la_oenb[7],
la_oenb[6],
la_oenb[5],
la_oenb[4],
la_oenb[3],
la_oenb[2],
la_oenb[1],
la_oenb[0]}),
.wbs_adr_i({wbs_adr_i[31],
wbs_adr_i[30],
wbs_adr_i[29],
wbs_adr_i[28],
wbs_adr_i[27],
wbs_adr_i[26],
wbs_adr_i[25],
wbs_adr_i[24],
wbs_adr_i[23],
wbs_adr_i[22],
wbs_adr_i[21],
wbs_adr_i[20],
wbs_adr_i[19],
wbs_adr_i[18],
wbs_adr_i[17],
wbs_adr_i[16],
wbs_adr_i[15],
wbs_adr_i[14],
wbs_adr_i[13],
wbs_adr_i[12],
wbs_adr_i[11],
wbs_adr_i[10],
wbs_adr_i[9],
wbs_adr_i[8],
wbs_adr_i[7],
wbs_adr_i[6],
wbs_adr_i[5],
wbs_adr_i[4],
wbs_adr_i[3],
wbs_adr_i[2],
wbs_adr_i[1],
wbs_adr_i[0]}),
.wbs_dat_i({wbs_dat_i[31],
wbs_dat_i[30],
wbs_dat_i[29],
wbs_dat_i[28],
wbs_dat_i[27],
wbs_dat_i[26],
wbs_dat_i[25],
wbs_dat_i[24],
wbs_dat_i[23],
wbs_dat_i[22],
wbs_dat_i[21],
wbs_dat_i[20],
wbs_dat_i[19],
wbs_dat_i[18],
wbs_dat_i[17],
wbs_dat_i[16],
wbs_dat_i[15],
wbs_dat_i[14],
wbs_dat_i[13],
wbs_dat_i[12],
wbs_dat_i[11],
wbs_dat_i[10],
wbs_dat_i[9],
wbs_dat_i[8],
wbs_dat_i[7],
wbs_dat_i[6],
wbs_dat_i[5],
wbs_dat_i[4],
wbs_dat_i[3],
wbs_dat_i[2],
wbs_dat_i[1],
wbs_dat_i[0]}),
.wbs_dat_o({wbs_dat_o[31],
wbs_dat_o[30],
wbs_dat_o[29],
wbs_dat_o[28],
wbs_dat_o[27],
wbs_dat_o[26],
wbs_dat_o[25],
wbs_dat_o[24],
wbs_dat_o[23],
wbs_dat_o[22],
wbs_dat_o[21],
wbs_dat_o[20],
wbs_dat_o[19],
wbs_dat_o[18],
wbs_dat_o[17],
wbs_dat_o[16],
wbs_dat_o[15],
wbs_dat_o[14],
wbs_dat_o[13],
wbs_dat_o[12],
wbs_dat_o[11],
wbs_dat_o[10],
wbs_dat_o[9],
wbs_dat_o[8],
wbs_dat_o[7],
wbs_dat_o[6],
wbs_dat_o[5],
wbs_dat_o[4],
wbs_dat_o[3],
wbs_dat_o[2],
wbs_dat_o[1],
wbs_dat_o[0]}),
.wbs_sel_i({wbs_sel_i[3],
wbs_sel_i[2],
wbs_sel_i[1],
wbs_sel_i[0]}));
endmodule |
module sha256_stream
(input clk,
input rst,
input mode,
input [511:0] s_tdata_i,
input s_tlast_i,
input s_tvalid_i,
output s_tready_o,
output [255:0] digest_o,
output digest_valid_o);
reg first_block;
always @(posedge clk) begin
if (s_tvalid_i & s_tready_o)
first_block <= s_tlast_i;
if (rst) begin
first_block <= 1'b1;
end
end
sha256_core core
(.clk (clk),
.reset_n (~rst),
.init(s_tvalid_i & first_block),
.next(s_tvalid_i & !first_block),
.mode (mode),
.block(s_tdata_i),
.ready(s_tready_o),
.digest (digest_o),
.digest_valid (digest_valid_o));
endmodule |
module sha256_top #(
parameter
NUM_SHA_UNITS = 8
)(
input wire clk,
input wire reset,
// Blocks input to sha module
input wire ik2sha_vld,
input wire ik2sha_last,
output wire ik2sha_rdy,
input wire [511:0] ik2sha_data,
// Digest output to ik
output wire sha2ik_vld,
input wire sha2ik_rdy,
output wire [255:0] sha2ik_data
);
wire fifo2ik_rdy;
wire fifo2ik_vld;
wire ik2fifo_vld;
wire ik2fifo_rdy;
wire ik2fifo_last;
wire fifo2sha_vld;
reg fifo2sha_rdy;
wire fifo2sha_last;
wire [511:0] ik2fifo_data;
wire [511:0] shafifoout_data[NUM_SHA_UNITS-1:0];
wire [511:0] fifo2sha_data;
wire [9:0] fifo2sha_data_count;
wire [9:0] fifo2ik_data_count;
wire fifo2ik_last;
wire [4:0] shafifoout_data_count[NUM_SHA_UNITS-1:0];
reg [255:0] sha2fifo_data;
wire [255:0] sha_digest[NUM_SHA_UNITS-1:0];
wire [255:0] fifo2ik_data;
reg [NUM_SHA_UNITS-1:0] sha_init;
reg [NUM_SHA_UNITS-1:0] sha_next;
wire [NUM_SHA_UNITS-1:0] sha_ready;
wire [NUM_SHA_UNITS-1:0] sha_valid;
reg [NUM_SHA_UNITS-1:0] sha_busy;
reg [NUM_SHA_UNITS-1:0] sha_last;
reg [NUM_SHA_UNITS-1:0] shafifoout_rdy;
wire [NUM_SHA_UNITS-1:0] shafifoout_last;
wire [NUM_SHA_UNITS-1:0] shafifoin_rdy;
wire [NUM_SHA_UNITS-1:0] shafifoout_vld;
reg [NUM_SHA_UNITS-1:0] sha_out_valid;
reg [31:0] shafifoin_vld;
reg [31:0] selected_sha_unit;
reg [4:0] sha_select;
reg selected_shafifo_free;
reg selected_sha_output_valid;
reg [31:0] sha_read_counter;
reg sha2fifo_input_vld;
wire sha2fifo_output_rdy;
assign ik2sha_rdy = ik2fifo_rdy;
assign ik2fifo_vld = ik2sha_vld;
assign ik2fifo_data = ik2sha_data;
assign ik2fifo_last = ik2sha_last;
assign sha2ik_data = fifo2ik_data;
assign sha2ik_vld = fifo2ik_vld;
assign fifo2ik_rdy = sha2ik_rdy;
// NUM_SHA_UNITS_wide multiplexers:
always @(*) begin
case (sha_select)
5'd0: begin
selected_shafifo_free = ~shafifoout_vld[0];
selected_sha_unit = 32'b00000000000000000000000000000001;
end
5'd1: begin
selected_shafifo_free = ~shafifoout_vld[1];
selected_sha_unit = 32'b00000000000000000000000000000010;
end
5'd2: begin
selected_shafifo_free = ~shafifoout_vld[2];
selected_sha_unit = 32'b00000000000000000000000000000100;
end
5'd3: begin
selected_shafifo_free = ~shafifoout_vld[3];
selected_sha_unit = 32'b00000000000000000000000000001000;
end
5'd4: begin
selected_shafifo_free = ~shafifoout_vld[4];
selected_sha_unit = 32'b00000000000000000000000000010000;
end
5'd5: begin
selected_shafifo_free = ~shafifoout_vld[5];
selected_sha_unit = 32'b00000000000000000000000000100000;
end
5'd6: begin
selected_shafifo_free = ~shafifoout_vld[6];
selected_sha_unit = 32'b00000000000000000000000001000000;
end
5'd7: begin
selected_shafifo_free = ~shafifoout_vld[7];
selected_sha_unit = 32'b00000000000000000000000010000000;
end
5'd8: begin
selected_shafifo_free = ~shafifoout_vld[8];
selected_sha_unit = 32'b00000000000000000000000100000000;
end
5'd9: begin
selected_shafifo_free = ~shafifoout_vld[9];
selected_sha_unit = 32'b00000000000000000000001000000000;
end
5'd10: begin
selected_shafifo_free = ~shafifoout_vld[10];
selected_sha_unit = 32'b00000000000000000000010000000000;
end
5'd11: begin
selected_shafifo_free = ~shafifoout_vld[11];
selected_sha_unit = 32'b00000000000000000000100000000000;
end
5'd12: begin
selected_shafifo_free = ~shafifoout_vld[12];
selected_sha_unit = 32'b00000000000000000001000000000000;
end
5'd13: begin
selected_shafifo_free = ~shafifoout_vld[13];
selected_sha_unit = 32'b00000000000000000010000000000000;
end
5'd14: begin
selected_shafifo_free = ~shafifoout_vld[14];
selected_sha_unit = 32'b00000000000000000100000000000000;
end
5'd15: begin
selected_shafifo_free = ~shafifoout_vld[15];
selected_sha_unit = 32'b00000000000000001000000000000000;
end
5'd16: begin
selected_shafifo_free = ~shafifoout_vld[16];
selected_sha_unit = 32'b00000000000000010000000000000000;
end
5'd17: begin
selected_shafifo_free = ~shafifoout_vld[17];
selected_sha_unit = 32'b00000000000000100000000000000000;
end
5'd18: begin
selected_shafifo_free = ~shafifoout_vld[18];
selected_sha_unit = 32'b00000000000001000000000000000000;
end
5'd19: begin
selected_shafifo_free = ~shafifoout_vld[19];
selected_sha_unit = 32'b00000000000010000000000000000000;
end
5'd20: begin
selected_shafifo_free = ~shafifoout_vld[20];
selected_sha_unit = 32'b00000000000100000000000000000000;
end
5'd21: begin
selected_shafifo_free = ~shafifoout_vld[21];
selected_sha_unit = 32'b00000000001000000000000000000000;
end
5'd22: begin
selected_shafifo_free = ~shafifoout_vld[22];
selected_sha_unit = 32'b00000000010000000000000000000000;
end
5'd23: begin
selected_shafifo_free = ~shafifoout_vld[23];
selected_sha_unit = 32'b00000000100000000000000000000000;
end
5'd24: begin
selected_shafifo_free = ~shafifoout_vld[24];
selected_sha_unit = 32'b00000001000000000000000000000000;
end
5'd25: begin
selected_shafifo_free = ~shafifoout_vld[25];
selected_sha_unit = 32'b00000010000000000000000000000000;
end
5'd26: begin
selected_shafifo_free = ~shafifoout_vld[26];
selected_sha_unit = 32'b00000100000000000000000000000000;
end
5'd27: begin
selected_shafifo_free = ~shafifoout_vld[27];
selected_sha_unit = 32'b00001000000000000000000000000000;
end
5'd28: begin
selected_shafifo_free = ~shafifoout_vld[28];
selected_sha_unit = 32'b00010000000000000000000000000000;
end
5'd29: begin
selected_shafifo_free = ~shafifoout_vld[29];
selected_sha_unit = 32'b00100000000000000000000000000000;
end
5'd30: begin
selected_shafifo_free = ~shafifoout_vld[30];
selected_sha_unit = 32'b01000000000000000000000000000000;
end
5'd31: begin
selected_shafifo_free = ~shafifoout_vld[31];
selected_sha_unit = 32'b10000000000000000000000000000000;
end
default: begin
selected_shafifo_free = ~shafifoout_vld[0];
selected_sha_unit = 32'b00000000000000000000000000000001;
end
endcase
end
// sha output control
// Selecting the next ready sha output, to be written to sha2fifo.
always @(*) begin
case (sha_read_counter)
32'b00000000000000000000000000000001: begin
selected_sha_output_valid = sha_out_valid[0];
sha2fifo_data = sha_digest[0];
end
32'b00000000000000000000000000000010: begin
selected_sha_output_valid = sha_out_valid[1];
sha2fifo_data = sha_digest[1];
end
32'b00000000000000000000000000000100: begin
selected_sha_output_valid = sha_out_valid[2];
sha2fifo_data = sha_digest[2];
end
32'b00000000000000000000000000001000: begin
selected_sha_output_valid = sha_out_valid[3];
sha2fifo_data = sha_digest[3];
end
32'b00000000000000000000000000010000: begin
selected_sha_output_valid = sha_out_valid[4];
sha2fifo_data = sha_digest[4];
end
32'b00000000000000000000000000100000: begin
selected_sha_output_valid = sha_out_valid[5];
sha2fifo_data = sha_digest[5];
end
32'b00000000000000000000000001000000: begin
selected_sha_output_valid = sha_out_valid[6];
sha2fifo_data = sha_digest[6];
end
32'b00000000000000000000000010000000: begin
selected_sha_output_valid = sha_out_valid[7];
sha2fifo_data = sha_digest[7];
end
32'b00000000000000000000000100000000: begin
selected_sha_output_valid = sha_out_valid[8];
sha2fifo_data = sha_digest[8];
end
32'b00000000000000000000001000000000: begin
selected_sha_output_valid = sha_out_valid[9];
sha2fifo_data = sha_digest[9];
end
32'b00000000000000000000010000000000: begin
selected_sha_output_valid = sha_out_valid[10];
sha2fifo_data = sha_digest[10];
end
32'b00000000000000000000100000000000: begin
selected_sha_output_valid = sha_out_valid[11];
sha2fifo_data = sha_digest[11];
end
32'b00000000000000000001000000000000: begin
selected_sha_output_valid = sha_out_valid[12];
sha2fifo_data = sha_digest[12];
end
32'b00000000000000000010000000000000: begin
selected_sha_output_valid = sha_out_valid[13];
sha2fifo_data = sha_digest[13];
end
32'b00000000000000000100000000000000: begin
selected_sha_output_valid = sha_out_valid[14];
sha2fifo_data = sha_digest[14];
end
32'b00000000000000001000000000000000: begin
selected_sha_output_valid = sha_out_valid[15];
sha2fifo_data = sha_digest[15];
end
32'b00000000000000010000000000000000: begin
selected_sha_output_valid = sha_out_valid[16];
sha2fifo_data = sha_digest[16];
end
32'b00000000000000100000000000000000: begin
selected_sha_output_valid = sha_out_valid[17];
sha2fifo_data = sha_digest[17];
end
32'b00000000000001000000000000000000: begin
selected_sha_output_valid = sha_out_valid[18];
sha2fifo_data = sha_digest[18];
end
32'b00000000000010000000000000000000: begin
selected_sha_output_valid = sha_out_valid[19];
sha2fifo_data = sha_digest[19];
end
32'b00000000000100000000000000000000: begin
selected_sha_output_valid = sha_out_valid[20];
sha2fifo_data = sha_digest[20];
end
32'b00000000001000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[21];
sha2fifo_data = sha_digest[21];
end
32'b00000000010000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[22];
sha2fifo_data = sha_digest[22];
end
32'b00000000100000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[23];
sha2fifo_data = sha_digest[23];
end
32'b00000001000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[24];
sha2fifo_data = sha_digest[24];
end
32'b00000010000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[25];
sha2fifo_data = sha_digest[25];
end
32'b00000100000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[26];
sha2fifo_data = sha_digest[26];
end
32'b00001000000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[27];
sha2fifo_data = sha_digest[27];
end
32'b00010000000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[28];
sha2fifo_data = sha_digest[28];
end
32'b00100000000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[29];
sha2fifo_data = sha_digest[29];
end
32'b01000000000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[30];
sha2fifo_data = sha_digest[30];
end
32'b10000000000000000000000000000000: begin
selected_sha_output_valid = sha_out_valid[31];
sha2fifo_data = sha_digest[31];
end
default:
begin
selected_sha_output_valid = sha_out_valid[0];
sha2fifo_data = sha_digest[0];
end
endcase
end
// sha output control
// Selecting the next ready sha output, to be written to sha2fifo.
always @(posedge clk) begin
if (reset) begin
sha_read_counter <= 32'b00000000000000000000000000000001;
sha2fifo_input_vld <= 0;
end
else begin
if (selected_sha_output_valid & sha2fifo_output_rdy & ~sha2fifo_input_vld) begin
// next selected sha unit has a valid digest, and the output fifo has a room to accept it:
sha2fifo_input_vld <= 1'b1;
end
if (sha2fifo_input_vld) begin
// Following the write to sha2fifo, update sha_read_counter to check next sha unit
// Rotate left modulo NUM_SHA_UNITS
if (sha_read_counter[NUM_SHA_UNITS-1])
sha_read_counter <= 32'b00000000000000000000000000000001;
else
sha_read_counter <= sha_read_counter << 1;
sha2fifo_input_vld <= 1'b0;
end
end
end
// sha input fifo (512 x 512 bit, constructed of two 256bit fifos connected in parallel):
axis_512x512b_fifo ik2sha_fifo (
.s_aclk(clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(ik2fifo_vld), // input wire s_axis_tvalid
.s_axis_tready(ik2fifo_rdy), // output wire s_axis_tready
.s_axis_tdata(ik2fifo_data), // input wire [511 : 0] s_axis_tdata
.s_axis_tlast(ik2fifo_last), // input wire s_axis_tlast
.m_axis_tvalid(fifo2sha_vld), // output wire m_axis_tvalid
.m_axis_tready(fifo2sha_rdy), // input wire m_axis_tready
.m_axis_tdata(fifo2sha_data), // output wire [511 : 0] m_axis_tdata
.m_axis_tlast(fifo2sha_last), // output wire m_axis_tlast
.axis_data_count(fifo2sha_data_count) // output wire [9 : 0] axis_data_count
);
// sha results (digests) 512 x 256bit fifo:
axis_512x256b_fifo sha2ik_fifo (
.s_aclk(clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(sha2fifo_input_vld), // input wire s_axis_tvalid
.s_axis_tready(sha2fifo_output_rdy), // output wire s_axis_tready
.s_axis_tdata(sha2fifo_data), // input wire [255 : 0] s_axis_tdata
.s_axis_tlast(1'b1), // input wire s_axis_tlast
.m_axis_tvalid(fifo2ik_vld), // output wire m_axis_tvalid
.m_axis_tready(fifo2ik_rdy), // input wire m_axis_tready
.m_axis_tdata(fifo2ik_data), // output wire [255 : 0] m_axis_tdata
.m_axis_tlast(fifo2ik_last), // output wire m_axis_tlast
.axis_data_count(fifo2ik_data_count) // output wire [9 : 0] axis_data_count
);
// sha units control state machine: Controlling the digest calculation per each sha unit.
localparam
SHA_IDLE = 3'd0,
SHA_READ_FIRST = 3'd1,
SHA_WAIT_NEXT = 3'd2,
SHA_READ_NEXT = 3'd3,
SHA_READ_REST = 3'd4,
SHA_WAIT_OUTPUT_VALID = 3'd5,
SHA_WAIT_OUTPUT_READ = 3'd6;
reg [2:0] sha_state[NUM_SHA_UNITS-1:0];
// sha2fifo state machine: Reading sha units result to output fifo
localparam
FIFO2SHA_IDLE = 3'd0,
FIFO2SHA_WAIT_NEXT_BLOCK = 3'd1,
FIFO2SHA_READ_NEXT_BLOCK = 3'd2,
FIFO2SHA_READ_REST = 3'd3,
FIFO2SHA_LAST_BLOCK = 3'd4;
reg [2:0] fifo2sha_state;
// Input fifo to sha_fifo state machine
// ====================================
// Transferring a complete packet from input fifo to the selected sha fifo.
// The packet transfer begins only if the target sha fifo is empty, to avoid any confusion with possibly previous sha calculation
//
always @(posedge clk) begin
if (reset) begin
fifo2sha_state <= FIFO2SHA_IDLE;
sha_select <= 4'h0000;
shafifoin_vld <= 32'h0000;
end
else begin
case (fifo2sha_state)
FIFO2SHA_IDLE: begin
fifo2sha_rdy <= 1'b0;
shafifoin_vld <= 32'h0000;
if (fifo2sha_vld & selected_shafifo_free) begin
fifo2sha_state <= FIFO2SHA_READ_NEXT_BLOCK;
end
else
fifo2sha_state <= FIFO2SHA_IDLE;
end
FIFO2SHA_LAST_BLOCK: begin
fifo2sha_rdy <= 1'b0;
shafifoin_vld <= 32'h0000;
// Packet transfer is ended: Select next sha unit
fifo2sha_state <= FIFO2SHA_IDLE;
if (sha_select < NUM_SHA_UNITS-1)
sha_select <= sha_select + 5'b00001;
else
sha_select <= 5'b00000;
end
FIFO2SHA_READ_NEXT_BLOCK: begin
fifo2sha_rdy <= 1'b1;
shafifoin_vld <= selected_sha_unit;
fifo2sha_state <= FIFO2SHA_READ_REST;
// fifo2sha_lastQ <= fifo2sha_last;
end
FIFO2SHA_READ_REST: begin
fifo2sha_rdy <= 1'b0;
shafifoin_vld <= 32'h0000;
if (fifo2sha_last)
fifo2sha_state <= FIFO2SHA_LAST_BLOCK;
else
fifo2sha_state <= FIFO2SHA_WAIT_NEXT_BLOCK;
end
FIFO2SHA_WAIT_NEXT_BLOCK: begin
if (fifo2sha_vld)
fifo2sha_state <= FIFO2SHA_READ_NEXT_BLOCK;
else
fifo2sha_state <= FIFO2SHA_WAIT_NEXT_BLOCK;
end
default: begin
fifo2sha_state <= FIFO2SHA_IDLE;
fifo2sha_rdy <= 1'b0;
shafifoin_vld <= 32'h0000;
end
endcase
end
end
generate
genvar j;
for (j = 0; j < NUM_SHA_UNITS ; j = j + 1) begin: sha_id
// Per sha input fifo
// For sha unit j, in a multi-block case, all blocks are loaded to fifo, before proceeding to next sha unit
// Notice that despite its short depth (16 entries only) this fifo still consumes 8 (!!!) 36kb BRAMs
axis_16x512b_fifo sha_fifo (
.s_aclk(clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(shafifoin_vld[j]), // input wire s_axis_tvalid
.s_axis_tready(shafifoin_rdy[j]), // output wire s_axis_tready
.s_axis_tdata(fifo2sha_data), // input wire [511 : 0] s_axis_tdata
.s_axis_tlast(fifo2sha_last), // input wire s_axis_tlast
.m_axis_tvalid(shafifoout_vld[j]), // output wire m_axis_tvalid
.m_axis_tready(shafifoout_rdy[j]), // input wire m_axis_tready
.m_axis_tdata(shafifoout_data[j]), // output wire [511 : 0] m_axis_tdata
.m_axis_tlast(shafifoout_last[j]), // output wire m_axis_tlast
.axis_data_count(shafifoout_data_count[j]) // output wire [4 : 0] axis_data_count
);
// fifo to sha units state machines
// ================================
//
// Separate state machine per each defployed sha unit
// Each SM will load next block to the sha unit, once that unit is free, until tlast reached
//
always @(posedge clk) begin
if (reset) begin
sha_state[j] <= SHA_IDLE;
sha_init[j] <= 1'b0;
sha_next[j] <= 1'b0;
sha_last[j] <= 1'b0;
sha_busy[j] <= 1'b0;
shafifoout_rdy[j] <= 1'b0;
sha_out_valid[j] <= 1'b0;
end
else begin
case (sha_state[j])
SHA_IDLE: begin
sha_init[j] <= 1'b0;
sha_next[j] <= 1'b0;
sha_busy[j] <= 1'b0;
shafifoout_rdy[j] <= 1'b0;
if (shafifoout_vld[j] & ~sha_busy[j]) begin
sha_state[j] <= SHA_READ_FIRST;
end
else
sha_state[j] <= SHA_IDLE;
end
SHA_READ_FIRST: begin
sha_busy[j] <= 1'b1;
sha_init[j] <= 1'b1;
shafifoout_rdy[j] <= 1'b1;
sha_last[j] <= shafifoout_last[j];
sha_state[j] <= SHA_READ_REST;
end
SHA_READ_REST: begin
sha_init[j] <= 1'b0;
sha_next[j] <= 1'b0;
shafifoout_rdy[j] <= 1'b0;
sha_state[j] <= SHA_WAIT_OUTPUT_VALID;
end
SHA_WAIT_NEXT: begin
if (shafifoout_vld[j])
sha_state[j] <= SHA_READ_NEXT;
else
sha_state[j] <= SHA_WAIT_NEXT;
end
SHA_READ_NEXT: begin
sha_next[j] <= 1'b1;
shafifoout_rdy[j] <= 1'b1;
sha_last[j] <= shafifoout_last[j];
sha_state[j] <= SHA_READ_REST;
end
SHA_WAIT_OUTPUT_VALID: begin
if (sha_ready[j]) begin
if (sha_last[j]) begin
// This is the last block (of single or multiple blocks digest operation).
// Prepare for reading the result to output fifo
sha_state[j] <= SHA_WAIT_OUTPUT_READ;
sha_out_valid[j] <= 1'b1;
end
else
// Not the last block... Goto digesting next block
sha_state[j] <= SHA_WAIT_NEXT;
end
else
sha_state[j] <= SHA_WAIT_OUTPUT_VALID;
end
SHA_WAIT_OUTPUT_READ: begin
if (sha2fifo_input_vld & sha_read_counter[j]) begin
// Jth sha unit output is being read to output fifo
// Turn off the Jth output valid indicator
sha_out_valid[j] <= 1'b0;
sha_busy[j] <= 1'b0;
sha_state[j] <= SHA_IDLE;
end
else
sha_state[j] <= SHA_WAIT_OUTPUT_READ;
end
default: begin
sha_state[j] <= SHA_IDLE;
end
endcase
end
end
sha256_core sha256_core (
.clk(clk),
.reset_n(~reset),
.init(sha_init[j]),
.next(sha_next[j]),
.mode(1'b1), // set mode to sha256
.block(shafifoout_data[j]),
.ready(sha_ready[j]),
.digest(sha_digest[j]),
.digest_valid(sha_valid[j])
);
end
endgenerate
endmodule |
module sigmon_logic_blocks (
input wire clk,
input wire reset,
input wire clbs_enable,
input wire [31:0] clb0_in_select,
input wire [31:0] clb0_start_limit,
input wire [31:0] clb0_mid_limit,
input wire [31:0] clb1_in_select,
input wire [31:0] clb1_start_limit,
input wire [31:0] clb1_mid_limit,
input wire [31:0] clb2_in_select,
input wire [31:0] clb2_start_limit,
input wire [31:0] clb2_mid_limit,
input wire [31:0] clb3_in_select,
input wire [31:0] clb3_start_limit,
input wire [31:0] clb3_mid_limit,
input wire [31:0] clbs_logic_eq,
input wire sbu2nwp_rdy,
input wire sbu2nwp_vld,
input wire nwp2sbu_rdy,
input wire nwp2sbu_vld,
input wire sbu2cxp_rdy,
input wire sbu2cxp_vld,
input wire cxp2sbu_rdy,
input wire cxp2sbu_vld,
input wire sbu2nwp_tlast,
input wire nwp2sbu_tlast,
input wire sbu2cxp_tlast,
input wire cxp2sbu_tlast,
input wire nwp2sbu_lossless_credits,
input wire cxp2sbu_lossless_credits,
input wire axi4mm_aw_rdy,
input wire axi4mm_aw_vld,
input wire axi4mm_w_rdy,
input wire axi4mm_w_vld,
input wire axi4mm_w_last,
input wire axi4mm_b_rdy,
input wire axi4mm_b_vld,
input wire axi4mm_ar_rdy,
input wire axi4mm_ar_vld,
input wire axi4mm_r_rdy,
input wire axi4mm_r_vld,
input wire axi4mm_r_last,
input wire sigmon_enable_event,
input wire [15:0] nica_events,
output wire [3:0] clbs_out,
output wire [2:0] clb0_events_out,
output wire [2:0] clb1_events_out,
output wire [2:0] clb2_events_out,
output wire [2:0] clb3_events_out
);
reg [3:0] clbs_outQ;
always @(posedge clk) begin
if (reset) begin
clbs_outQ <= 4'b0000;
end
else begin
clbs_outQ <= clbs_out;
end
end
sigmon_logic_block sigmon_clb0 (
.clk(clk),
.reset(reset),
.clb_enable(clbs_enable),
.sbu2nwp_rdy(sbu2nwp_rdy),
.sbu2nwp_vld(sbu2nwp_vld),
.nwp2sbu_rdy(nwp2sbu_rdy),
.nwp2sbu_vld(nwp2sbu_vld),
.sbu2cxp_rdy(sbu2cxp_rdy),
.sbu2cxp_vld(sbu2cxp_vld),
.cxp2sbu_rdy(cxp2sbu_rdy),
.cxp2sbu_vld(cxp2sbu_vld),
.sbu2nwp_tlast(sbu2nwp_tlast),
.nwp2sbu_tlast(nwp2sbu_tlast),
.sbu2cxp_tlast(sbu2cxp_tlast),
.cxp2sbu_tlast(cxp2sbu_tlast),
.nwp2sbu_lossless_credits(nwp2sbu_lossless_credits),
.cxp2sbu_lossless_credits(cxp2sbu_lossless_credits),
.axi4mm_aw_rdy(axi4mm_aw_rdy),
.axi4mm_aw_vld(axi4mm_aw_vld),
.axi4mm_w_rdy(axi4mm_w_rdy),
.axi4mm_w_vld(axi4mm_w_vld),
.axi4mm_w_last(axi4mm_w_last),
.axi4mm_b_rdy(axi4mm_b_rdy),
.axi4mm_b_vld(axi4mm_b_vld),
.axi4mm_ar_rdy(axi4mm_ar_rdy),
.axi4mm_ar_vld(axi4mm_ar_vld),
.axi4mm_r_rdy(axi4mm_r_rdy),
.axi4mm_r_vld(axi4mm_r_vld),
.axi4mm_r_last(axi4mm_r_last),
.sigmon_enable_event(sigmon_enable_event),
.nica_events(nica_events),
.clbs_in(clbs_outQ),
.clb_in_select(clb0_in_select),
.clb_start_limit(clb0_start_limit),
.clb_mid_limit(clb0_mid_limit),
.clb_logic_eq(clbs_logic_eq[7:0]),
.clb_events_out(clb0_events_out),
.clb_out(clbs_out[0])
);
sigmon_logic_block sigmon_clb1 (
.clk(clk),
.reset(reset),
.clb_enable(clbs_enable),
.sbu2nwp_rdy(sbu2nwp_rdy),
.sbu2nwp_vld(sbu2nwp_vld),
.nwp2sbu_rdy(nwp2sbu_rdy),
.nwp2sbu_vld(nwp2sbu_vld),
.sbu2cxp_rdy(sbu2cxp_rdy),
.sbu2cxp_vld(sbu2cxp_vld),
.cxp2sbu_rdy(cxp2sbu_rdy),
.cxp2sbu_vld(cxp2sbu_vld),
.sbu2nwp_tlast(sbu2nwp_tlast),
.nwp2sbu_tlast(nwp2sbu_tlast),
.sbu2cxp_tlast(sbu2cxp_tlast),
.cxp2sbu_tlast(cxp2sbu_tlast),
.nwp2sbu_lossless_credits(nwp2sbu_lossless_credits),
.cxp2sbu_lossless_credits(cxp2sbu_lossless_credits),
.axi4mm_aw_rdy(axi4mm_aw_rdy),
.axi4mm_aw_vld(axi4mm_aw_vld),
.axi4mm_w_rdy(axi4mm_w_rdy),
.axi4mm_w_vld(axi4mm_w_vld),
.axi4mm_w_last(axi4mm_w_last),
.axi4mm_b_rdy(axi4mm_b_rdy),
.axi4mm_b_vld(axi4mm_b_vld),
.axi4mm_ar_rdy(axi4mm_ar_rdy),
.axi4mm_ar_vld(axi4mm_ar_vld),
.axi4mm_r_rdy(axi4mm_r_rdy),
.axi4mm_r_vld(axi4mm_r_vld),
.axi4mm_r_last(axi4mm_r_last),
.sigmon_enable_event(sigmon_enable_event),
.nica_events(nica_events),
.clbs_in(clbs_outQ),
.clb_in_select(clb1_in_select),
.clb_start_limit(clb1_start_limit),
.clb_mid_limit(clb1_mid_limit),
.clb_logic_eq(clbs_logic_eq[15:8]),
.clb_events_out(clb1_events_out),
.clb_out(clbs_out[1])
);
sigmon_logic_block sigmon_clb2 (
.clk(clk),
.reset(reset),
.clb_enable(clbs_enable),
.sbu2nwp_rdy(sbu2nwp_rdy),
.sbu2nwp_vld(sbu2nwp_vld),
.nwp2sbu_rdy(nwp2sbu_rdy),
.nwp2sbu_vld(nwp2sbu_vld),
.sbu2cxp_rdy(sbu2cxp_rdy),
.sbu2cxp_vld(sbu2cxp_vld),
.cxp2sbu_rdy(cxp2sbu_rdy),
.cxp2sbu_vld(cxp2sbu_vld),
.sbu2nwp_tlast(sbu2nwp_tlast),
.nwp2sbu_tlast(nwp2sbu_tlast),
.sbu2cxp_tlast(sbu2cxp_tlast),
.cxp2sbu_tlast(cxp2sbu_tlast),
.nwp2sbu_lossless_credits(nwp2sbu_lossless_credits),
.cxp2sbu_lossless_credits(cxp2sbu_lossless_credits),
.axi4mm_aw_rdy(axi4mm_aw_rdy),
.axi4mm_aw_vld(axi4mm_aw_vld),
.axi4mm_w_rdy(axi4mm_w_rdy),
.axi4mm_w_vld(axi4mm_w_vld),
.axi4mm_w_last(axi4mm_w_last),
.axi4mm_b_rdy(axi4mm_b_rdy),
.axi4mm_b_vld(axi4mm_b_vld),
.axi4mm_ar_rdy(axi4mm_ar_rdy),
.axi4mm_ar_vld(axi4mm_ar_vld),
.axi4mm_r_rdy(axi4mm_r_rdy),
.axi4mm_r_vld(axi4mm_r_vld),
.axi4mm_r_last(axi4mm_r_last),
.sigmon_enable_event(sigmon_enable_event),
.nica_events(nica_events),
.clbs_in(clbs_outQ),
.clb_in_select(clb2_in_select),
.clb_start_limit(clb2_start_limit),
.clb_mid_limit(clb2_mid_limit),
.clb_logic_eq(clbs_logic_eq[23:16]),
.clb_events_out(clb2_events_out),
.clb_out(clbs_out[2])
);
sigmon_logic_block sigmon_clb3 (
.clk(clk),
.reset(reset),
.clb_enable(clbs_enable),
.sbu2nwp_rdy(sbu2nwp_rdy),
.sbu2nwp_vld(sbu2nwp_vld),
.nwp2sbu_rdy(nwp2sbu_rdy),
.nwp2sbu_vld(nwp2sbu_vld),
.sbu2cxp_rdy(sbu2cxp_rdy),
.sbu2cxp_vld(sbu2cxp_vld),
.cxp2sbu_rdy(cxp2sbu_rdy),
.cxp2sbu_vld(cxp2sbu_vld),
.sbu2nwp_tlast(sbu2nwp_tlast),
.nwp2sbu_tlast(nwp2sbu_tlast),
.sbu2cxp_tlast(sbu2cxp_tlast),
.cxp2sbu_tlast(cxp2sbu_tlast),
.nwp2sbu_lossless_credits(nwp2sbu_lossless_credits),
.cxp2sbu_lossless_credits(cxp2sbu_lossless_credits),
.axi4mm_aw_rdy(axi4mm_aw_rdy),
.axi4mm_aw_vld(axi4mm_aw_vld),
.axi4mm_w_rdy(axi4mm_w_rdy),
.axi4mm_w_vld(axi4mm_w_vld),
.axi4mm_w_last(axi4mm_w_last),
.axi4mm_b_rdy(axi4mm_b_rdy),
.axi4mm_b_vld(axi4mm_b_vld),
.axi4mm_ar_rdy(axi4mm_ar_rdy),
.axi4mm_ar_vld(axi4mm_ar_vld),
.axi4mm_r_rdy(axi4mm_r_rdy),
.axi4mm_r_vld(axi4mm_r_vld),
.axi4mm_r_last(axi4mm_r_last),
.sigmon_enable_event(sigmon_enable_event),
.nica_events(nica_events),
.clbs_in(clbs_outQ),
.clb_in_select(clb3_in_select),
.clb_start_limit(clb3_start_limit),
.clb_mid_limit(clb3_mid_limit),
.clb_logic_eq(clbs_logic_eq[31:24]),
.clb_events_out(clb3_events_out),
.clb_out(clbs_out[3])
);
endmodule |
module sigmon_monitors
(
input wire clk,
input wire reset,
input wire monitoring_enable,
input wire sigmon_enable_event,
input wire timestamp_counter_24toggle,
input wire nwp2sbu_sop,
input wire nwp2sbu_eop,
input wire sbu2nwp_sop,
input wire sbu2nwp_eop,
input wire cxp2sbu_sop,
input wire cxp2sbu_eop,
input wire sbu2cxp_sop,
input wire sbu2cxp_eop,
input wire sbu2cxpfifo_sop,
input wire sbu2cxpfifo_eop,
input wire sbu2nwpfifo_sop,
input wire sbu2nwpfifo_eop,
input wire nwp2sbu_lossless_credits_on,
input wire cxp2sbu_lossless_credits_on,
input wire nwp2sbu_lossless_credits_off,
input wire cxp2sbu_lossless_credits_off,
input wire got_ikwaddr,
input wire got_ikraddr,
input wire got_ddrwaddr,
input wire got_ddrwdata,
input wire got_ddrwdone,
input wire got_ddrraddr,
input wire got_ddrrdata,
input wire axi4mm_aw_rdy,
input wire axi4mm_aw_vld,
input wire axi4mm_w_rdy,
input wire axi4mm_w_vld,
input wire axi4mm_w_last,
input wire axi4mm_b_rdy,
input wire axi4mm_b_vld,
input wire axi4mm_ar_rdy,
input wire axi4mm_ar_vld,
input wire axi4mm_r_rdy,
input wire axi4mm_r_vld,
input wire axi4mm_r_last,
input wire dram_test_enabled,
input wire [15:0] nica_events,
input wire [15:0] count_events,
input wire [2:0] clb0_events,
input wire [2:0] clb1_events,
input wire [2:0] clb2_events,
input wire [2:0] clb3_events,
input wire clb0_out_on,
input wire clb0_out_off,
input wire clb1_out_on,
input wire clb1_out_off,
input wire clb2_out_on,
input wire clb2_out_off,
input wire clb3_out_on,
input wire clb3_out_off,
input wire stream0_match,
input wire stream0_sample,
input wire stream1_match,
input wire stream1_sample,
input wire stream2_match,
input wire stream2_sample,
input wire stream3_match,
input wire stream3_sample,
input wire stream0_merged,
input wire stream1_merged,
input wire stream2_merged,
input wire stream3_merged,
input wire [47:0] stream0_sample_data,
input wire [47:0] stream1_sample_data,
input wire [47:0] stream2_sample_data,
input wire [47:0] stream3_sample_data,
input wire [15:0] monitor0_events_select,
input wire [15:0] monitor1_events_select,
input wire [15:0] monitor2_events_select,
input wire [15:0] monitor3_events_select,
input wire [15:0] monitor4_events_select,
input wire [15:0] monitor5_events_select,
input wire [15:0] monitor6_events_select,
input wire [15:0] monitor7_events_select,
input wire [7:0] monitors_fifo_rd,
output wire [35:0] monitor0_fifo_data,
output wire [35:0] monitor1_fifo_data,
output wire [35:0] monitor2_fifo_data,
output wire [35:0] monitor3_fifo_data,
output wire [35:0] monitor4_fifo_data,
output wire [35:0] monitor5_fifo_data,
output wire [35:0] monitor6_fifo_data,
output wire [35:0] monitor7_fifo_data,
output wire [10:0] monitor0_fifo_data_count,
output wire [10:0] monitor1_fifo_data_count,
output wire [10:0] monitor2_fifo_data_count,
output wire [10:0] monitor3_fifo_data_count,
output wire [10:0] monitor4_fifo_data_count,
output wire [10:0] monitor5_fifo_data_count,
output wire [10:0] monitor6_fifo_data_count,
output wire [10:0] monitor7_fifo_data_count,
output wire [7:0] monitors_valid,
output wire [7:0] monitors_data_loss
);
sigmon_monitor monitor0 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.axi4mm_aw_rdy(axi4mm_aw_rdy),
.axi4mm_aw_vld(axi4mm_aw_vld),
.axi4mm_w_rdy(axi4mm_w_rdy),
.axi4mm_w_vld(axi4mm_w_vld),
.axi4mm_w_last(axi4mm_w_last),
.axi4mm_b_rdy(axi4mm_b_rdy),
.axi4mm_b_vld(axi4mm_b_vld),
.axi4mm_ar_rdy(axi4mm_ar_rdy),
.axi4mm_ar_vld(axi4mm_ar_vld),
.axi4mm_r_rdy(axi4mm_r_rdy),
.axi4mm_r_vld(axi4mm_r_vld),
.axi4mm_r_last(axi4mm_r_last),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor0_events_select),
.data_read(monitors_fifo_rd[0]),
.data_out(monitor0_fifo_data),
.data_count(monitor0_fifo_data_count),
.data_valid(monitors_valid[0]),
.data_loss(monitors_data_loss[0])
);
sigmon_monitor monitor1 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor1_events_select),
.data_read(monitors_fifo_rd[1]),
.data_out(monitor1_fifo_data),
.data_count(monitor1_fifo_data_count),
.data_valid(monitors_valid[1]),
.data_loss(monitors_data_loss[1])
);
sigmon_monitor monitor2 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor2_events_select),
.data_read(monitors_fifo_rd[2]),
.data_out(monitor2_fifo_data),
.data_count(monitor2_fifo_data_count),
.data_valid(monitors_valid[2]),
.data_loss(monitors_data_loss[2])
);
sigmon_monitor monitor3 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor3_events_select),
.data_read(monitors_fifo_rd[3]),
.data_out(monitor3_fifo_data),
.data_count(monitor3_fifo_data_count),
.data_valid(monitors_valid[3]),
.data_loss(monitors_data_loss[3])
);
sigmon_monitor monitor4 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor4_events_select),
.data_read(monitors_fifo_rd[4]),
.data_out(monitor4_fifo_data),
.data_count(monitor4_fifo_data_count),
.data_valid(monitors_valid[4]),
.data_loss(monitors_data_loss[4])
);
sigmon_monitor monitor5 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor5_events_select),
.data_read(monitors_fifo_rd[5]),
.data_out(monitor5_fifo_data),
.data_count(monitor5_fifo_data_count),
.data_valid(monitors_valid[5]),
.data_loss(monitors_data_loss[5])
);
sigmon_monitor monitor6 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor6_events_select),
.data_read(monitors_fifo_rd[6]),
.data_out(monitor6_fifo_data),
.data_count(monitor6_fifo_data_count),
.data_valid(monitors_valid[6]),
.data_loss(monitors_data_loss[6])
);
sigmon_monitor monitor7 (
.clk(clk),
.reset(reset),
.monitor_enable(monitoring_enable),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events(count_events),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.sample0_datain(stream0_sample_data),
.sample1_datain(stream1_sample_data),
.sample2_datain(stream2_sample_data),
.sample3_datain(stream3_sample_data),
.events_id(monitor7_events_select),
.data_read(monitors_fifo_rd[7]),
.data_out(monitor7_fifo_data),
.data_count(monitor7_fifo_data_count),
.data_valid(monitors_valid[7]),
.data_loss(monitors_data_loss[7])
);
endmodule |
module coap_coap_top (
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
ap_clk,
ap_rst_n,
ik_host_metadata_input_V_V_TDATA,
ik_host_data_input_V_V_TDATA,
ik_host_metadata_output_V_V_TDATA,
ik_host_data_output_V_V_TDATA,
ik_net_metadata_input_V_V_TDATA,
ik_net_data_input_V_V_TDATA,
ik_net_metadata_output_V_V_TDATA,
ik_net_data_output_V_V_TDATA,
ik_host_metadata_input_V_V_TVALID,
ik_host_metadata_input_V_V_TREADY,
ik_host_data_input_V_V_TVALID,
ik_host_data_input_V_V_TREADY,
ik_host_metadata_output_V_V_TVALID,
ik_host_metadata_output_V_V_TREADY,
ik_host_data_output_V_V_TVALID,
ik_host_data_output_V_V_TREADY,
ik_net_metadata_input_V_V_TVALID,
ik_net_metadata_input_V_V_TREADY,
ik_net_data_input_V_V_TVALID,
ik_net_data_input_V_V_TREADY,
ik_net_metadata_output_V_V_TVALID,
ik_net_metadata_output_V_V_TREADY,
ik_net_data_output_V_V_TVALID,
ik_net_data_output_V_V_TREADY,
m_axi_ik_mem_mem_V_AWVALID,
m_axi_ik_mem_mem_V_AWREADY,
m_axi_ik_mem_mem_V_AWADDR,
m_axi_ik_mem_mem_V_AWID,
m_axi_ik_mem_mem_V_AWLEN,
m_axi_ik_mem_mem_V_AWSIZE,
m_axi_ik_mem_mem_V_AWBURST,
m_axi_ik_mem_mem_V_AWLOCK,
m_axi_ik_mem_mem_V_AWCACHE,
m_axi_ik_mem_mem_V_AWPROT,
m_axi_ik_mem_mem_V_AWQOS,
m_axi_ik_mem_mem_V_AWREGION,
m_axi_ik_mem_mem_V_AWUSER,
m_axi_ik_mem_mem_V_WVALID,
m_axi_ik_mem_mem_V_WREADY,
m_axi_ik_mem_mem_V_WDATA,
m_axi_ik_mem_mem_V_WSTRB,
m_axi_ik_mem_mem_V_WLAST,
m_axi_ik_mem_mem_V_WID,
m_axi_ik_mem_mem_V_WUSER,
m_axi_ik_mem_mem_V_BREADY,
m_axi_ik_mem_mem_V_BVALID,
m_axi_ik_mem_mem_V_BRESP,
m_axi_ik_mem_mem_V_BID,
m_axi_ik_mem_mem_V_BUSER,
m_axi_ik_mem_mem_V_ARVALID,
m_axi_ik_mem_mem_V_ARREADY,
m_axi_ik_mem_mem_V_ARADDR,
m_axi_ik_mem_mem_V_ARID,
m_axi_ik_mem_mem_V_ARLEN,
m_axi_ik_mem_mem_V_ARSIZE,
m_axi_ik_mem_mem_V_ARBURST,
m_axi_ik_mem_mem_V_ARLOCK,
m_axi_ik_mem_mem_V_ARCACHE,
m_axi_ik_mem_mem_V_ARPROT,
m_axi_ik_mem_mem_V_ARQOS,
m_axi_ik_mem_mem_V_ARREGION,
m_axi_ik_mem_mem_V_ARUSER,
m_axi_ik_mem_mem_V_RVALID,
m_axi_ik_mem_mem_V_RREADY,
m_axi_ik_mem_mem_V_RDATA,
m_axi_ik_mem_mem_V_RLAST,
m_axi_ik_mem_mem_V_RID,
m_axi_ik_mem_mem_V_RRESP,
m_axi_ik_mem_mem_V_RUSER,
ik_events_0_V,
ik_events_1_V,
ik_events_2_V,
ik_events_3_V,
ik_events_4_V,
ik_events_5_V,
ik_events_6_V,
ik_events_7_V,
tc_net_tc_data_counts_V,
tc_net_tc_meta_counts_V,
tc_host_tc_data_counts_V,
tc_host_tc_meta_counts_V
);
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (C_S_AXI_AXILITES_DATA_WIDTH / 8);
parameter C_M_AXI_IK_MEM_MEM_V_CACHE_VALUE = 0;
parameter C_M_AXI_IK_MEM_MEM_V_ID_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_ADDR_WIDTH = 64;
parameter C_M_AXI_IK_MEM_MEM_V_DATA_WIDTH = 512;
parameter C_M_AXI_IK_MEM_MEM_V_AWUSER_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_ARUSER_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_WUSER_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_RUSER_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_BUSER_WIDTH = 1;
parameter C_M_AXI_ID_WIDTH = 1;
parameter C_M_AXI_ADDR_WIDTH = 64;
parameter C_M_AXI_DATA_WIDTH = 32;
parameter C_M_AXI_AWUSER_WIDTH = 1;
parameter C_M_AXI_ARUSER_WIDTH = 1;
parameter C_M_AXI_WUSER_WIDTH = 1;
parameter C_M_AXI_RUSER_WIDTH = 1;
parameter C_M_AXI_BUSER_WIDTH = 1;
parameter C_M_AXI_IK_MEM_MEM_V_WSTRB_WIDTH = (C_M_AXI_IK_MEM_MEM_V_DATA_WIDTH / 8);
parameter C_M_AXI_WSTRB_WIDTH = (C_M_AXI_DATA_WIDTH / 8);
`ifdef FIRST_SHA_UNITS
parameter NUM1_SHA_UNITS = `FIRST_SHA_UNITS;
`else
parameter NUM1_SHA_UNITS = 12;
`endif
`ifdef SECOND_SHA_UNITS
parameter NUM2_SHA_UNITS = `SECOND_SHA_UNITS;
`else
parameter NUM2_SHA_UNITS = 8;
`endif
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1 : 0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
input ap_clk;
input ap_rst_n;
input [255:0] ik_host_metadata_input_V_V_TDATA;
input [295:0] ik_host_data_input_V_V_TDATA;
output [255:0] ik_host_metadata_output_V_V_TDATA;
output [295:0] ik_host_data_output_V_V_TDATA;
input [255:0] ik_net_metadata_input_V_V_TDATA;
input [295:0] ik_net_data_input_V_V_TDATA;
output [255:0] ik_net_metadata_output_V_V_TDATA;
output [295:0] ik_net_data_output_V_V_TDATA;
input ik_host_metadata_input_V_V_TVALID;
output ik_host_metadata_input_V_V_TREADY;
input ik_host_data_input_V_V_TVALID;
output ik_host_data_input_V_V_TREADY;
output ik_host_metadata_output_V_V_TVALID;
input ik_host_metadata_output_V_V_TREADY;
output ik_host_data_output_V_V_TVALID;
input ik_host_data_output_V_V_TREADY;
input ik_net_metadata_input_V_V_TVALID;
output ik_net_metadata_input_V_V_TREADY;
input ik_net_data_input_V_V_TVALID;
output ik_net_data_input_V_V_TREADY;
output ik_net_metadata_output_V_V_TVALID;
input ik_net_metadata_output_V_V_TREADY;
output ik_net_data_output_V_V_TVALID;
input ik_net_data_output_V_V_TREADY;
output m_axi_ik_mem_mem_V_AWVALID;
input m_axi_ik_mem_mem_V_AWREADY;
output [C_M_AXI_IK_MEM_MEM_V_ADDR_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_AWADDR;
output [C_M_AXI_IK_MEM_MEM_V_ID_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_AWID;
output [7:0] m_axi_ik_mem_mem_V_AWLEN;
output [2:0] m_axi_ik_mem_mem_V_AWSIZE;
output [1:0] m_axi_ik_mem_mem_V_AWBURST;
output [1:0] m_axi_ik_mem_mem_V_AWLOCK;
output [3:0] m_axi_ik_mem_mem_V_AWCACHE;
output [2:0] m_axi_ik_mem_mem_V_AWPROT;
output [3:0] m_axi_ik_mem_mem_V_AWQOS;
output [3:0] m_axi_ik_mem_mem_V_AWREGION;
output [C_M_AXI_IK_MEM_MEM_V_AWUSER_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_AWUSER;
output m_axi_ik_mem_mem_V_WVALID;
input m_axi_ik_mem_mem_V_WREADY;
output [C_M_AXI_IK_MEM_MEM_V_DATA_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_WDATA;
output [C_M_AXI_IK_MEM_MEM_V_WSTRB_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_WSTRB;
output m_axi_ik_mem_mem_V_WLAST;
output [C_M_AXI_IK_MEM_MEM_V_ID_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_WID;
output [C_M_AXI_IK_MEM_MEM_V_WUSER_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_WUSER;
output m_axi_ik_mem_mem_V_ARVALID;
input m_axi_ik_mem_mem_V_ARREADY;
output [C_M_AXI_IK_MEM_MEM_V_ADDR_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_ARADDR;
output [C_M_AXI_IK_MEM_MEM_V_ID_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_ARID;
output [7:0] m_axi_ik_mem_mem_V_ARLEN;
output [2:0] m_axi_ik_mem_mem_V_ARSIZE;
output [1:0] m_axi_ik_mem_mem_V_ARBURST;
output [1:0] m_axi_ik_mem_mem_V_ARLOCK;
output [3:0] m_axi_ik_mem_mem_V_ARCACHE;
output [2:0] m_axi_ik_mem_mem_V_ARPROT;
output [3:0] m_axi_ik_mem_mem_V_ARQOS;
output [3:0] m_axi_ik_mem_mem_V_ARREGION;
output [C_M_AXI_IK_MEM_MEM_V_ARUSER_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_ARUSER;
input m_axi_ik_mem_mem_V_RVALID;
output m_axi_ik_mem_mem_V_RREADY;
input [C_M_AXI_IK_MEM_MEM_V_DATA_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_RDATA;
input m_axi_ik_mem_mem_V_RLAST;
input [C_M_AXI_IK_MEM_MEM_V_ID_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_RID;
input [C_M_AXI_IK_MEM_MEM_V_RUSER_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_RUSER;
input [1:0] m_axi_ik_mem_mem_V_RRESP;
input m_axi_ik_mem_mem_V_BVALID;
output m_axi_ik_mem_mem_V_BREADY;
input [1:0] m_axi_ik_mem_mem_V_BRESP;
input [C_M_AXI_IK_MEM_MEM_V_ID_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_BID;
input [C_M_AXI_IK_MEM_MEM_V_BUSER_WIDTH - 1 : 0] m_axi_ik_mem_mem_V_BUSER;
input [0:0] ik_events_0_V;
input [0:0] ik_events_1_V;
input [0:0] ik_events_2_V;
input [0:0] ik_events_3_V;
input [0:0] ik_events_4_V;
input [0:0] ik_events_5_V;
input [0:0] ik_events_6_V;
input [0:0] ik_events_7_V;
input [39:0] tc_host_tc_meta_counts_V;
input [39:0] tc_host_tc_data_counts_V;
input [39:0] tc_net_tc_meta_counts_V;
input [39:0] tc_net_tc_data_counts_V;
wire first_pass_sha_unit_input_stream_TVALID;
wire first_pass_sha_unit_input_stream_TREADY;
wire [511:0] first_pass_sha_unit_input_stream_TDATA;
wire [0:0] first_pass_sha_unit_input_stream_TLAST;
wire first_pass_sha_unit_output_stream_V_data_V_TVALID;
wire first_pass_sha_unit_output_stream_V_data_V_TREADY;
wire [255:0] first_pass_sha_unit_output_stream_V_data_V_TDATA;
wire [511:0] second_pass_sha_unit_input_stream_TDATA;
wire [0:0] second_pass_sha_unit_input_stream_TLAST;
wire second_pass_sha_unit_input_stream_TVALID;
wire second_pass_sha_unit_input_stream_TREADY;
wire [255:0] second_pass_sha_unit_output_stream_V_data_V_TDATA;
wire second_pass_sha_unit_output_stream_V_data_V_TVALID;
wire second_pass_sha_unit_output_stream_V_data_V_TREADY;
///////////////////////////////////////////////////////////////////////////////
// coap_top:
///////////////////////////////////////////////////////////////////////////////
coap_coap_ikernel #(
.C_S_AXI_AXILITES_ADDR_WIDTH(32),
.C_S_AXI_AXILITES_DATA_WIDTH(32)
) coap_ikernel (
.s_axi_AXILiteS_AWVALID(s_axi_AXILiteS_AWVALID),
.s_axi_AXILiteS_AWREADY(s_axi_AXILiteS_AWREADY),
.s_axi_AXILiteS_AWADDR(s_axi_AXILiteS_AWADDR),
.s_axi_AXILiteS_WVALID(s_axi_AXILiteS_WVALID),
.s_axi_AXILiteS_WREADY(s_axi_AXILiteS_WREADY),
.s_axi_AXILiteS_WDATA(s_axi_AXILiteS_WDATA),
.s_axi_AXILiteS_WSTRB(s_axi_AXILiteS_WSTRB),
.s_axi_AXILiteS_ARVALID(s_axi_AXILiteS_ARVALID),
.s_axi_AXILiteS_ARREADY(s_axi_AXILiteS_ARREADY),
.s_axi_AXILiteS_ARADDR(s_axi_AXILiteS_ARADDR),
.s_axi_AXILiteS_RVALID(s_axi_AXILiteS_RVALID),
.s_axi_AXILiteS_RREADY(s_axi_AXILiteS_RREADY),
.s_axi_AXILiteS_RDATA(s_axi_AXILiteS_RDATA),
.s_axi_AXILiteS_RRESP(s_axi_AXILiteS_RRESP),
.s_axi_AXILiteS_BVALID(s_axi_AXILiteS_BVALID),
.s_axi_AXILiteS_BREADY(s_axi_AXILiteS_BREADY),
.s_axi_AXILiteS_BRESP(s_axi_AXILiteS_BRESP),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ik_host_metadata_output_V_V_TDATA(ik_host_metadata_output_V_V_TDATA),
.ik_host_metadata_output_V_V_TVALID(ik_host_metadata_output_V_V_TVALID),
.ik_host_metadata_output_V_V_TREADY(ik_host_metadata_output_V_V_TREADY),
.ik_host_metadata_input_V_V_TDATA(ik_host_metadata_input_V_V_TDATA),
.ik_host_metadata_input_V_V_TVALID(ik_host_metadata_input_V_V_TVALID),
.ik_host_metadata_input_V_V_TREADY(ik_host_metadata_input_V_V_TREADY),
.ik_host_data_output_V_V_TDATA(ik_host_data_output_V_V_TDATA),
.ik_host_data_output_V_V_TVALID(ik_host_data_output_V_V_TVALID),
.ik_host_data_output_V_V_TREADY(ik_host_data_output_V_V_TREADY),
.ik_host_data_input_V_V_TDATA(ik_host_data_input_V_V_TDATA),
.ik_host_data_input_V_V_TVALID(ik_host_data_input_V_V_TVALID),
.ik_host_data_input_V_V_TREADY(ik_host_data_input_V_V_TREADY),
.ik_net_metadata_output_V_V_TDATA(ik_net_metadata_output_V_V_TDATA),
.ik_net_metadata_output_V_V_TVALID(ik_net_metadata_output_V_V_TVALID),
.ik_net_metadata_output_V_V_TREADY(ik_net_metadata_output_V_V_TREADY),
.ik_net_metadata_input_V_V_TDATA(ik_net_metadata_input_V_V_TDATA),
.ik_net_metadata_input_V_V_TVALID(ik_net_metadata_input_V_V_TVALID),
.ik_net_metadata_input_V_V_TREADY(ik_net_metadata_input_V_V_TREADY),
.ik_net_data_output_V_V_TDATA(ik_net_data_output_V_V_TDATA),
.ik_net_data_output_V_V_TVALID(ik_net_data_output_V_V_TVALID),
.ik_net_data_output_V_V_TREADY(ik_net_data_output_V_V_TREADY),
.ik_net_data_input_V_V_TDATA(ik_net_data_input_V_V_TDATA),
.ik_net_data_input_V_V_TVALID(ik_net_data_input_V_V_TVALID),
.ik_net_data_input_V_V_TREADY(ik_net_data_input_V_V_TREADY),
.m_axi_ik_mem_mem_V_AWVALID(m_axi_ik_mem_mem_V_AWVALID),
.m_axi_ik_mem_mem_V_AWREADY(m_axi_ik_mem_mem_V_AWREADY),
.m_axi_ik_mem_mem_V_AWADDR(m_axi_ik_mem_mem_V_AWADDR),
.m_axi_ik_mem_mem_V_AWID(m_axi_ik_mem_mem_V_AWID),
.m_axi_ik_mem_mem_V_AWLEN(m_axi_ik_mem_mem_V_AWLEN),
.m_axi_ik_mem_mem_V_AWSIZE(m_axi_ik_mem_mem_V_AWSIZE),
.m_axi_ik_mem_mem_V_AWBURST(m_axi_ik_mem_mem_V_AWBURST),
.m_axi_ik_mem_mem_V_AWLOCK(m_axi_ik_mem_mem_V_AWLOCK),
.m_axi_ik_mem_mem_V_AWCACHE(m_axi_ik_mem_mem_V_AWCACHE),
.m_axi_ik_mem_mem_V_AWPROT(m_axi_ik_mem_mem_V_AWPROT),
.m_axi_ik_mem_mem_V_AWQOS(m_axi_ik_mem_mem_V_AWQOS),
.m_axi_ik_mem_mem_V_AWREGION(m_axi_ik_mem_mem_V_AWREGION),
.m_axi_ik_mem_mem_V_AWUSER(m_axi_ik_mem_mem_V_AWUSER),
.m_axi_ik_mem_mem_V_WVALID(m_axi_ik_mem_mem_V_WVALID),
.m_axi_ik_mem_mem_V_WREADY(m_axi_ik_mem_mem_V_WREADY),
.m_axi_ik_mem_mem_V_WDATA(m_axi_ik_mem_mem_V_WDATA),
.m_axi_ik_mem_mem_V_WSTRB(m_axi_ik_mem_mem_V_WSTRB),
.m_axi_ik_mem_mem_V_WLAST(m_axi_ik_mem_mem_V_WLAST),
.m_axi_ik_mem_mem_V_WID(m_axi_ik_mem_mem_V_WID),
.m_axi_ik_mem_mem_V_WUSER(m_axi_ik_mem_mem_V_WUSER),
.m_axi_ik_mem_mem_V_BREADY(m_axi_ik_mem_mem_V_BREADY),
.m_axi_ik_mem_mem_V_BVALID(m_axi_ik_mem_mem_V_BVALID),
.m_axi_ik_mem_mem_V_BRESP(m_axi_ik_mem_mem_V_BRESP),
.m_axi_ik_mem_mem_V_BID(m_axi_ik_mem_mem_V_BID),
.m_axi_ik_mem_mem_V_BUSER(m_axi_ik_mem_mem_V_BUSER),
.m_axi_ik_mem_mem_V_ARVALID(m_axi_ik_mem_mem_V_ARVALID),
.m_axi_ik_mem_mem_V_ARREADY(m_axi_ik_mem_mem_V_ARREADY),
.m_axi_ik_mem_mem_V_ARADDR(m_axi_ik_mem_mem_V_ARADDR),
.m_axi_ik_mem_mem_V_ARID(m_axi_ik_mem_mem_V_ARID),
.m_axi_ik_mem_mem_V_ARLEN(m_axi_ik_mem_mem_V_ARLEN),
.m_axi_ik_mem_mem_V_ARSIZE(m_axi_ik_mem_mem_V_ARSIZE),
.m_axi_ik_mem_mem_V_ARBURST(m_axi_ik_mem_mem_V_ARBURST),
.m_axi_ik_mem_mem_V_ARLOCK(m_axi_ik_mem_mem_V_ARLOCK),
.m_axi_ik_mem_mem_V_ARCACHE(m_axi_ik_mem_mem_V_ARCACHE),
.m_axi_ik_mem_mem_V_ARPROT(m_axi_ik_mem_mem_V_ARPROT),
.m_axi_ik_mem_mem_V_ARQOS(m_axi_ik_mem_mem_V_ARQOS),
.m_axi_ik_mem_mem_V_ARREGION(m_axi_ik_mem_mem_V_ARREGION),
.m_axi_ik_mem_mem_V_ARUSER(m_axi_ik_mem_mem_V_ARUSER),
.m_axi_ik_mem_mem_V_RVALID(m_axi_ik_mem_mem_V_RVALID),
.m_axi_ik_mem_mem_V_RREADY(m_axi_ik_mem_mem_V_RREADY),
.m_axi_ik_mem_mem_V_RDATA(m_axi_ik_mem_mem_V_RDATA),
.m_axi_ik_mem_mem_V_RLAST(m_axi_ik_mem_mem_V_RLAST),
.m_axi_ik_mem_mem_V_RID(m_axi_ik_mem_mem_V_RID),
.m_axi_ik_mem_mem_V_RRESP(m_axi_ik_mem_mem_V_RRESP),
.m_axi_ik_mem_mem_V_RUSER(m_axi_ik_mem_mem_V_RUSER),
.ik_events_0_V(ik_events_0_V),
.ik_events_1_V(ik_events_1_V),
.ik_events_2_V(ik_events_2_V),
.ik_events_3_V(ik_events_3_V),
.ik_events_4_V(ik_events_4_V),
.ik_events_5_V(ik_events_5_V),
.ik_events_6_V(ik_events_6_V),
.ik_events_7_V(ik_events_7_V),
.tc_net_tc_data_counts_V(tc_net_tc_data_counts_V),
.tc_net_tc_meta_counts_V(tc_net_tc_meta_counts_V),
.tc_host_tc_data_counts_V(tc_host_tc_data_counts_V),
.tc_host_tc_meta_counts_V(tc_host_tc_meta_counts_V),
.first_pass_sha_unit_input_stream_TDATA(first_pass_sha_unit_input_stream_TDATA),
.first_pass_sha_unit_input_stream_TLAST(first_pass_sha_unit_input_stream_TLAST),
.first_pass_sha_unit_input_stream_TVALID(first_pass_sha_unit_input_stream_TVALID),
.first_pass_sha_unit_input_stream_TREADY(first_pass_sha_unit_input_stream_TREADY),
.first_pass_sha_unit_output_stream_V_data_V_TVALID(first_pass_sha_unit_output_stream_V_data_V_TVALID),
.first_pass_sha_unit_output_stream_V_data_V_TREADY(first_pass_sha_unit_output_stream_V_data_V_TREADY),
.first_pass_sha_unit_output_stream_V_data_V_TDATA(first_pass_sha_unit_output_stream_V_data_V_TDATA),
.second_pass_sha_unit_input_stream_TDATA(second_pass_sha_unit_input_stream_TDATA),
.second_pass_sha_unit_input_stream_TLAST(second_pass_sha_unit_input_stream_TLAST),
.second_pass_sha_unit_input_stream_TVALID(second_pass_sha_unit_input_stream_TVALID),
.second_pass_sha_unit_input_stream_TREADY(second_pass_sha_unit_input_stream_TREADY),
.second_pass_sha_unit_output_stream_V_data_V_TDATA(second_pass_sha_unit_output_stream_V_data_V_TDATA),
.second_pass_sha_unit_output_stream_V_data_V_TVALID(second_pass_sha_unit_output_stream_V_data_V_TVALID),
.second_pass_sha_unit_output_stream_V_data_V_TREADY(second_pass_sha_unit_output_stream_V_data_V_TREADY)
);
///////////////////////////////////////////////////////////////////////////////
// sha1_top:
///////////////////////////////////////////////////////////////////////////////
sha256_top #(
.NUM_SHA_UNITS(NUM1_SHA_UNITS)
) sha1_top (
.clk(ap_clk),
.reset(~ap_rst_n),
.ik2sha_vld(first_pass_sha_unit_input_stream_TVALID),
.ik2sha_last(first_pass_sha_unit_input_stream_TLAST),
.ik2sha_rdy(first_pass_sha_unit_input_stream_TREADY),
.ik2sha_data(first_pass_sha_unit_input_stream_TDATA),
.sha2ik_vld(first_pass_sha_unit_output_stream_V_data_V_TVALID),
.sha2ik_rdy(first_pass_sha_unit_output_stream_V_data_V_TREADY),
.sha2ik_data(first_pass_sha_unit_output_stream_V_data_V_TDATA)
);
///////////////////////////////////////////////////////////////////////////////
// sha2_top:
///////////////////////////////////////////////////////////////////////////////
sha256_top #(
.NUM_SHA_UNITS(NUM2_SHA_UNITS)
) sha2_top (
.clk(ap_clk),
.reset(~ap_rst_n),
.ik2sha_vld(second_pass_sha_unit_input_stream_TVALID),
.ik2sha_last(second_pass_sha_unit_input_stream_TLAST),
.ik2sha_rdy(second_pass_sha_unit_input_stream_TREADY),
.ik2sha_data(second_pass_sha_unit_input_stream_TDATA),
.sha2ik_vld(second_pass_sha_unit_output_stream_V_data_V_TVALID),
.sha2ik_rdy(second_pass_sha_unit_output_stream_V_data_V_TREADY),
.sha2ik_data(second_pass_sha_unit_output_stream_V_data_V_TDATA)
);
endmodule |
module ddr_address_mapping #(
parameter
AXILITE_ADDR_WIDTH = 13,
AXILITE_DATA_WIDTH = 32
)(
input wire clk,
input wire reset,
// Indicating which axi4mm (aw or ar) this instance is serving
// rdwr == 0 - wr instance
// rdwr == 1 - rd instance
input wire rdwr_mode,
// AXI_lites interface
input wire [AXILITE_ADDR_WIDTH-1:0] axi_AWADDR,
input wire axi_AWVALID,
output wire axi_AWREADY,
input wire [AXILITE_DATA_WIDTH-1:0] axi_WDATA,
input wire axi_WVALID,
output wire axi_WREADY,
input wire [AXILITE_DATA_WIDTH/8-1:0] axi_WSTRB, // Not used by this AXILites slave. Assumed always all-1
output wire axi_BVALID,
input wire axi_BREADY,
output wire [1:0] axi_BRESP,
// ikernel <=> addr_map
output ik2map_rdy,
input ik2map_vld,
input [63:0] ik2map_addr,
input [1:0] ik2map_burst,
input [3:0] ik2map_cache,
input [2:0] ik2map_id,
input [7:0] ik2map_len,
input [1:0] ik2map_lock,
input [2:0] ik2map_prot,
input [3:0] ik2map_qos,
input [3:0] ik2map_region,
input [2:0] ik2map_size,
// addr_map <==> ddr:
input map2ddr_rdy,
output map2ddr_vld,
// Only 32 lower addr bits are mapped.
// Upper bits are assigned to a constant in ku*.v top level wrapper
output [31:0] map2ddr_addr,
output [1:0] map2ddr_burst,
output [3:0] map2ddr_cache,
output [2:0] map2ddr_id,
output [7:0] map2ddr_len,
output [1:0] map2ddr_lock,
output [2:0] map2ddr_prot,
output [3:0] map2ddr_qos,
output [3:0] map2ddr_region,
output [2:0] map2ddr_size
);
localparam
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1;
localparam
DDR_ADDR_MAP_START = 13'h1000, // write only
DDR_ADDR_MAP_END = 13'h1400, // write only
DDR_ADDR_MAP_CTRL = 13'h1800, // write only
DDR_ADDR_MAP_WRBASE0 = 13'h1810, // write only
DDR_ADDR_MAP_WRBASE1 = 13'h1814, // write only
DDR_ADDR_MAP_RDBASE0 = 13'h1818, // write only
DDR_ADDR_MAP_RDBASE1 = 13'h181c; // write only
wire axi_aw_hs;
wire axi_w_hs;
reg [1:0] axi_wstate;
reg [1:0] axi_wnext;
reg ddr_adrs_table_wr;
reg [AXILITE_ADDR_WIDTH-1 : 0] axi_waddr;
reg [31:0] ddr_adrs_table_datain;
wire [9:0] map_addr;
wire [31:0] map_out;
reg [31:0] stage3_map;
wire stage1_enable;
reg stage1_vld;
wire stage1_rdy;
wire stage2_enable;
reg stage2_vld;
wire stage2_rdy;
wire stage3_enable;
reg stage3_vld;
wire stage3_rdy;
wire stage4_enable;
reg stage4_vld;
wire stage4_rdy;
reg [31:0] stage1_addr;// N64
reg [1:0] stage1_burst;// N2
reg [3:0] stage1_cache;// N4
reg [2:0] stage1_id;// N3
reg [7:0] stage1_len;// N8
reg [1:0] stage1_lock;// N1
reg [2:0] stage1_prot;// N3
reg [3:0] stage1_qos;// N4
reg [3:0] stage1_region;// N4
reg [2:0] stage1_size;// N3
reg [31:0] stage2_addr;// N64
reg [1:0] stage2_burst;// N2
reg [3:0] stage2_cache;// N4
reg [2:0] stage2_id;// N3
reg [7:0] stage2_len;// N8
reg [1:0] stage2_lock;// N1
reg [2:0] stage2_prot;// N3
reg [3:0] stage2_qos;// N4
reg [3:0] stage2_region;// N4
reg [2:0] stage2_size;// N3
reg [31:0] stage3_addr;// N64
reg [1:0] stage3_burst;// N2
reg [3:0] stage3_cache;// N4
reg [2:0] stage3_id;// N3
reg [7:0] stage3_len;// N8
reg [1:0] stage3_lock;// N1
reg [2:0] stage3_prot;// N3
reg [3:0] stage3_qos;// N4
reg [3:0] stage3_region;// N4
reg [2:0] stage3_size;// N3
reg [31:0] stage4_addr;// N64
reg [1:0] stage4_burst;// N2
reg [3:0] stage4_cache;// N4
reg [2:0] stage4_id;// N3
reg [7:0] stage4_len;// N8
reg [1:0] stage4_lock;// N1
reg [2:0] stage4_prot;// N3
reg [3:0] stage4_qos;// N4
reg [3:0] stage4_region;// N4
reg [2:0] stage4_size;// N3
// ==================================================================================================
// Test mode logic:
// ================
//
// Used to test the mapping scheme, while memcached still not implemented the ikernel virtual_id into aw_addr/ar_addr[40:31]
// In test mode, aw_addr/ar_addr[40:31] are replaced with predetermined values
//
// ddr_adrs_map_ctrl[31:0] - Test mode control register:
// ddr_adrs_map_ctrl[31:17] - reserved
// ddr_adrs_map_ctrl[16] - Bypass axi4mm_ar_addr[40:31] with alternate(ddr_adrs_map_rdbase0, ddr_adrs_map_rdbase1).
// While on, alternate between ddr_adrs_map_rdbase0 and ddr_adrs_map_rdbase1, to drive axi4mm_ar_addr[40:31]
// ddr_adrs_map_ctrl[15:1] - reserved
// ddr_adrs_map_ctrl[0] - Bypass axi4mm_aw_addr[40:31] with alternate(ddr_adrs_map_wrbase0, ddr_adrs_map_wrbase1)
// While on, alternate between ddr_adrs_map_wrbase0 and ddr_adrs_map_wrbase1, to drive axi4mm_aw_addr[40:31]
//
// Enforced ikernel virtual_id for ddr read/write transactions
// ddr_adrs_map_wrbase0
// ddr_adrs_map_wrbase1
// ddr_adrs_map_rdbase0
// ddr_adrs_map_rdbase1
reg [31:0] ddr_adrs_map_ctrl;
reg [31:0] ddr_adrs_map_wrbase0;
reg [31:0] ddr_adrs_map_wrbase1;
reg [31:0] ddr_adrs_map_rdbase0;
reg [31:0] ddr_adrs_map_rdbase1;
reg ddr_adrs_map_wr_toggle;
reg ddr_adrs_map_rd_toggle;
wire [31:0] map_wraddr_test_mode;
wire [31:0] map_wraddr;
wire [31:0] map_rdaddr_test_mode;
wire [31:0] map_rdaddr;
always @(posedge clk) begin
if (reset) begin
ddr_adrs_map_wr_toggle <= 1'b0;
ddr_adrs_map_rd_toggle <= 1'b0;
end
else begin
if (ik2map_rdy & ik2map_vld) begin
ddr_adrs_map_rd_toggle <= rdwr_mode ? ddr_adrs_map_rd_toggle + 1 : ddr_adrs_map_rd_toggle;
ddr_adrs_map_wr_toggle <= rdwr_mode ? ddr_adrs_map_wr_toggle : ddr_adrs_map_wr_toggle + 1;
end
end
end
// ikernel virtual_id bypass in test mode:
// following a rd/wr transaction, *toggle is inverted, to select a different ikernel virtual_id between two successive transactions
assign map_wraddr_test_mode = ddr_adrs_map_wr_toggle ? ddr_adrs_map_wrbase1 : ddr_adrs_map_wrbase0;
assign map_rdaddr_test_mode = ddr_adrs_map_rd_toggle ? ddr_adrs_map_rdbase1 : ddr_adrs_map_rdbase0;
// ======================
// End of test mode logic
// ==================================================================================================
// Final map tabe address, based on module ddr_address_mapping instance mode:
assign map_wraddr = ddr_adrs_map_ctrl[0] ? map_wraddr_test_mode : ik2map_addr[40:31];
assign map_rdaddr = ddr_adrs_map_ctrl[16] ? map_rdaddr_test_mode : ik2map_addr[40:31];
assign map_addr = ~rdwr_mode ? map_wraddr[9:0] : map_rdaddr[9:0];
//------------------------Local AXI write fsm------------------
assign axi_AWREADY = (axi_wstate == WRIDLE);
assign axi_WREADY = (axi_wstate == WRDATA);
assign axi_BRESP = 2'b00; // OKAY
assign axi_BVALID = (axi_wstate == WRRESP);
assign axi_aw_hs = axi_AWVALID & axi_AWREADY;
assign axi_w_hs = axi_WVALID & axi_WREADY;
// wstate
always @(posedge clk) begin
if (reset)
axi_wstate <= WRIDLE;
else
axi_wstate <= axi_wnext;
end
// wnext
always @(*) begin
case (axi_wstate)
WRIDLE:
if (axi_AWVALID)
axi_wnext = WRDATA;
else
axi_wnext = WRIDLE;
WRDATA:
if (axi_WVALID)
axi_wnext = WRRESP;
else
axi_wnext = WRDATA;
WRRESP:
if (axi_BREADY)
axi_wnext = WRIDLE;
else
axi_wnext = WRRESP;
default:
axi_wnext = WRIDLE;
endcase
end
// waddr
always @(posedge clk) begin
if (axi_aw_hs)
axi_waddr <= axi_AWADDR[AXILITE_ADDR_WIDTH-1 : 0];
end
// writing to map table
always @(posedge clk) begin
if (reset) begin
ddr_adrs_table_wr <= 1'b0;
ddr_adrs_map_ctrl <= 32'h00000000;
ddr_adrs_map_wrbase0 <= 32'h00000000;
ddr_adrs_map_wrbase1 <= 32'h00000000;
ddr_adrs_map_rdbase0 <= 32'h00000000;
ddr_adrs_map_rdbase1 <= 32'h00000000;
end
else
begin
if (axi_w_hs && axi_waddr >= DDR_ADDR_MAP_START && axi_waddr < DDR_ADDR_MAP_END) begin
ddr_adrs_table_wr <= 1'b1;
ddr_adrs_table_datain <= axi_WDATA;
end
else
ddr_adrs_table_wr <= 1'b0;
if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_CTRL)
ddr_adrs_map_ctrl <= axi_WDATA;
if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE0)
ddr_adrs_map_wrbase0 <= axi_WDATA;
if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_WRBASE1)
ddr_adrs_map_wrbase1 <= axi_WDATA;
if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE0)
ddr_adrs_map_rdbase0 <= axi_WDATA;
if (axi_w_hs && axi_waddr == DDR_ADDR_MAP_RDBASE1)
ddr_adrs_map_rdbase1 <= axi_WDATA;
end
end
// axi4mm signals pipeline
assign ik2map_rdy = stage1_rdy;
assign stage1_enable = ik2map_vld & ik2map_rdy;
assign stage1_rdy = ~stage1_vld | stage2_rdy;
assign stage2_enable = stage1_vld & stage2_rdy;
assign stage2_rdy = ~stage2_vld | stage3_rdy;
assign stage3_enable = stage2_vld & stage3_rdy;
assign stage3_rdy = ~stage3_vld | stage4_rdy;
assign stage4_enable = stage3_vld & stage4_rdy;
assign stage4_rdy = ~stage4_vld | map2ddr_rdy;
assign map2ddr_vld = stage4_vld;
assign map2ddr_addr = stage4_addr;
assign map2ddr_burst = stage4_burst;
assign map2ddr_cache = stage4_cache;
assign map2ddr_id = stage4_id;
assign map2ddr_len = stage4_len;
assign map2ddr_lock = stage4_lock;
assign map2ddr_prot = stage4_prot;
assign map2ddr_qos = stage4_qos;
assign map2ddr_region = stage4_region;
assign map2ddr_size = stage4_size;
always @(posedge clk) begin
if (reset) begin
stage1_vld <= 1'b0;
stage2_vld <= 1'b0;
stage3_vld <= 1'b0;
stage4_vld <= 1'b0;
end
else begin
if (stage1_enable) begin
stage1_addr <= {1'b0, ik2map_addr[30:0]};
stage1_burst <= ik2map_burst;
stage1_cache <= ik2map_cache;
stage1_id <= ik2map_id;
stage1_len <= ik2map_len;
stage1_lock <= ik2map_lock;
stage1_prot <= ik2map_prot;
stage1_qos <= ik2map_qos;
stage1_region <= ik2map_region;
stage1_size <= ik2map_size;
stage1_vld <= 1'b1;
end
else if (stage1_vld & stage2_rdy) begin
stage1_vld <= 1'b0;
end
if (stage2_enable) begin
stage2_addr <= {1'b0, stage1_addr[30:0]};
stage2_burst <= stage1_burst;
stage2_cache <= stage1_cache;
stage2_id <= stage1_id;
stage2_len <= stage1_len;
stage2_lock <= stage1_lock;
stage2_prot <= stage1_prot;
stage2_qos <= stage1_qos;
stage2_region <= stage1_region;
stage2_size <= stage1_size;
stage2_vld <= 1'b1;
end
else if (stage2_vld & stage3_rdy) begin
stage2_vld <= 1'b0;
end
if (stage3_enable) begin
stage3_map <= map_out;
stage3_addr <= {1'b0, stage2_addr[30:0]};
stage3_burst <= stage2_burst;
stage3_cache <= stage2_cache;
stage3_id <= stage2_id;
stage3_len <= stage2_len;
stage3_lock <= stage2_lock;
stage3_prot <= stage2_prot;
stage3_qos <= stage2_qos;
stage3_region <= stage2_region;
stage3_size <= stage2_size;
stage3_vld <= 1'b1;
end
else if (stage3_vld & stage4_rdy) begin
stage3_vld <= 1'b0;
end
if (stage4_enable) begin
// Mapping current address to its assigned location in ddr space:
stage4_addr <= {1'b0, stage3_addr[30:12] + stage3_map[18:0] , stage3_addr[11:0]};
stage4_burst <= stage3_burst;
stage4_cache <= stage3_cache;
stage4_id <= stage3_id;
stage4_len <= stage3_len;
stage4_lock <= stage3_lock;
stage4_prot <= stage3_prot;
stage4_qos <= stage3_qos;
stage4_region <= stage3_region;
stage4_size <= stage3_size;
stage4_vld <= 1'b1;
end
else if (stage4_vld & map2ddr_rdy) begin
stage4_vld <= 1'b0;
end
end
end
ddr_adrs_mapping ddr_addr_table (
.clka(clk), // input wire clka
// Map table is loaded via axi-lite:
.addra({2'b0, axi_waddr[9:2]}), // input wire [9 : 0]
.wea(ddr_adrs_table_wr), // input wire [0 : 0] wea
.dina(ddr_adrs_table_datain), // input wire [31 : 0] dina
// Table lookup: thread number resides in ik2map_aw/ar_addr[40:31]:
// The table is constantly looked-up. Yet, its output is valid only upon ik2map_vld & ik2map_rdy
.clkb(clk), // input wire clkb
.addrb(map_addr), // input wire [9 : 0] addrb
// map_out[19:0] - Thread base address
// map_out[31:20] - Reserved
.doutb(map_out) // output wire [31 : 0] doutb
);
endmodule |
module csa_32x4(
input wire [31:0] in1,
input wire [31:0] in2,
input wire [31:0] in3,
input wire [31:0] in4,
output wire [31:0] sum,
output wire [31:0] carry
);
wire [31:0] sum1;
wire [31:0] carry1;
csa_32x3 csa_32x3_1(
.in1(in1),
.in2(in2),
.in3(in3),
.sum(sum1),
.carry(carry1)
);
csa_32x3 csa_32x3_2(
.in1(in4),
.in2(sum1),
.in3({carry1[30:0], 1'b0}),
.sum(sum),
.carry(carry)
);
endmodule // csa_32x4 |
module sigmon_counters
(
input wire clk,
input wire reset,
input wire counters_enable,
input wire sigmon_enable_event,
input wire timestamp_counter_24toggle,
input wire nwp2sbu_sop,
input wire nwp2sbu_eop,
input wire nwp2sbu_eop_temp,
input wire sbu2nwp_sop,
input wire sbu2nwp_eop,
input wire cxp2sbu_sop,
input wire cxp2sbu_eop,
input wire sbu2cxp_sop,
input wire sbu2cxp_eop,
input wire sbu2cxpfifo_sop,
input wire sbu2cxpfifo_eop,
input wire sbu2nwpfifo_sop,
input wire sbu2nwpfifo_eop,
input wire nwp2sbu_lossless_credits_on,
input wire cxp2sbu_lossless_credits_on,
input wire nwp2sbu_lossless_credits_off,
input wire cxp2sbu_lossless_credits_off,
input wire got_ikwaddr,
input wire got_ikraddr,
input wire got_ddrwaddr,
input wire got_ddrwdata,
input wire got_ddrwdone,
input wire got_ddrraddr,
input wire got_ddrrdata,
input wire dram_test_enabled,
input wire [15:0] nica_events,
input wire clb0_out,
input wire clb1_out,
input wire [2:0] clb0_events,
input wire [2:0] clb1_events,
input wire clb0_out_on,
input wire clb0_out_off,
input wire clb1_out_on,
input wire clb1_out_off,
input wire clb2_out,
input wire clb3_out,
input wire [2:0] clb2_events,
input wire [2:0] clb3_events,
input wire clb2_out_on,
input wire clb2_out_off,
input wire clb3_out_on,
input wire clb3_out_off,
input wire stream0_match,
input wire stream0_sample,
input wire stream0_merged,
input wire stream1_match,
input wire stream1_sample,
input wire stream1_merged,
input wire stream2_match,
input wire stream2_sample,
input wire stream2_merged,
input wire stream3_match,
input wire stream3_sample,
input wire stream3_merged,
input wire [31:0] events0_select,
input wire [31:0] count0_limit,
input wire [31:0] events1_select,
input wire [31:0] count1_limit,
input wire [31:0] events2_select,
input wire [31:0] count2_limit,
input wire [31:0] events3_select,
input wire [31:0] count3_limit,
input wire [31:0] events4_select,
input wire [31:0] count4_limit,
input wire [31:0] events5_select,
input wire [31:0] count5_limit,
input wire [31:0] events6_select,
input wire [31:0] count6_limit,
input wire [31:0] events7_select,
input wire [31:0] count7_limit,
input wire [31:0] events8_select,
input wire [31:0] count8_limit,
input wire [31:0] events9_select,
input wire [31:0] count9_limit,
input wire [31:0] events10_select,
input wire [31:0] count10_limit,
input wire [31:0] events11_select,
input wire [31:0] count11_limit,
output wire [31:0] count0_out,
output wire [31:0] count1_out,
output wire [31:0] count2_out,
output wire [31:0] count3_out,
output wire [31:0] count4_out,
output wire [31:0] count5_out,
output wire [31:0] count6_out,
output wire [31:0] count7_out,
output wire [31:0] count8_out,
output wire [31:0] count9_out,
output wire [31:0] count10_out,
output wire [31:0] count11_out,
output wire [15:0] events_out
);
sigmon_counter sigmon_counter0
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events0_select),
.count_limit(count0_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:1], 1'b0}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count0_out),
.event_out(events_out[0])
);
sigmon_counter sigmon_counter1
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events1_select),
.count_limit(count1_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:2], 1'b0, events_out[0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count1_out),
.event_out(events_out[1])
);
sigmon_counter sigmon_counter2
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events2_select),
.count_limit(count2_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:3], 1'b0, events_out[1:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count2_out),
.event_out(events_out[2])
);
sigmon_counter sigmon_counter3
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events3_select),
.count_limit(count3_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:4], 1'b0, events_out[2:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count3_out),
.event_out(events_out[3])
);
sigmon_counter sigmon_counter4
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events4_select),
.count_limit(count4_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:5], 1'b0, events_out[3:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count4_out),
.event_out(events_out[4])
);
sigmon_counter sigmon_counter5
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events5_select),
.count_limit(count5_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:6], 1'b0, events_out[4:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count5_out),
.event_out(events_out[5])
);
sigmon_counter sigmon_counter6
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events6_select),
.count_limit(count6_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:7], 1'b0, events_out[5:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count6_out),
.event_out(events_out[6])
);
sigmon_counter sigmon_counter7
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events7_select),
.count_limit(count7_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:8], 1'b0, events_out[6:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count7_out),
.event_out(events_out[7])
);
sigmon_counter sigmon_counter8
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events8_select),
.count_limit(count8_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:9], 1'b0, events_out[7:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count8_out),
.event_out(events_out[8])
);
sigmon_counter sigmon_counter9
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events9_select),
.count_limit(count9_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:10], 1'b0, events_out[8:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count9_out),
.event_out(events_out[9])
);
sigmon_counter sigmon_counter10
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events10_select),
.count_limit(count10_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:11], 1'b0, events_out[9:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count10_out),
.event_out(events_out[10])
);
sigmon_counter sigmon_counter11
(
.clk(clk),
.reset(reset),
.counter_enable(counters_enable),
.events_select(events11_select),
.count_limit(count11_limit),
.sigmon_enable_event(sigmon_enable_event),
.timestamp_counter_24toggle(timestamp_counter_24toggle),
.nwp2sbu_sop(nwp2sbu_sop),
.nwp2sbu_eop(nwp2sbu_eop),
.nwp2sbu_eop_temp(nwp2sbu_eop_temp),
.sbu2nwp_sop(sbu2nwp_sop),
.sbu2nwp_eop(sbu2nwp_eop),
.cxp2sbu_sop(cxp2sbu_sop),
.cxp2sbu_eop(cxp2sbu_eop),
.sbu2cxp_sop(sbu2cxp_sop),
.sbu2cxp_eop(sbu2cxp_eop),
.sbu2cxpfifo_sop(sbu2cxpfifo_sop),
.sbu2cxpfifo_eop(sbu2cxpfifo_eop),
.sbu2nwpfifo_sop(sbu2nwpfifo_sop),
.sbu2nwpfifo_eop(sbu2nwpfifo_eop),
.nwp2sbu_lossless_credits_on(nwp2sbu_lossless_credits_on),
.cxp2sbu_lossless_credits_on(cxp2sbu_lossless_credits_on),
.nwp2sbu_lossless_credits_off(nwp2sbu_lossless_credits_off),
.cxp2sbu_lossless_credits_off(cxp2sbu_lossless_credits_off),
.stream0_match(stream0_match),
.stream0_sample(stream0_sample),
.stream1_match(stream1_match),
.stream1_sample(stream1_sample),
.stream2_match(stream2_match),
.stream2_sample(stream2_sample),
.stream3_match(stream3_match),
.stream3_sample(stream3_sample),
.stream0_merged(stream0_merged),
.stream1_merged(stream1_merged),
.stream2_merged(stream2_merged),
.stream3_merged(stream3_merged),
.got_ikwaddr(got_ikwaddr),
.got_ikraddr(got_ikraddr),
.got_ddrwaddr(got_ddrwaddr),
.got_ddrwdata(got_ddrwdata),
.got_ddrwdone(got_ddrwdone),
.got_ddrraddr(got_ddrraddr),
.got_ddrrdata(got_ddrrdata),
.dram_test_enabled(dram_test_enabled),
.nica_events(nica_events),
.count_events({events_out[15:12], 1'b0, events_out[10:0]}),
.clb0_out(clb0_out),
.clb1_out(clb1_out),
.clb0_events(clb0_events),
.clb1_events(clb1_events),
.clb0_out_on(clb0_out_on),
.clb0_out_off(clb0_out_off),
.clb1_out_on(clb1_out_on),
.clb1_out_off(clb1_out_off),
.clb2_out(clb2_out),
.clb3_out(clb3_out),
.clb2_events(clb2_events),
.clb3_events(clb3_events),
.clb2_out_on(clb2_out_on),
.clb2_out_off(clb2_out_off),
.clb3_out_on(clb3_out_on),
.clb3_out_off(clb3_out_off),
.count_out(count11_out),
.event_out(events_out[11])
);
endmodule |
module csa_32x3(
input wire [31:0] in1,
input wire [31:0] in2,
input wire [31:0] in3,
output wire [31:0] sum,
output wire [31:0] carry
);
assign sum = in1 ^ in2 ^ in3;
assign carry = in1 & in2 | in1 & in3 | in2 & in3;
endmodule // csa_32x3 |
module sha256_w_mem(
input wire clk,
input wire reset_n,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w_sum,
output wire [31 : 0] w_carry
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp_sum;
reg [31 : 0] w_tmp_carry;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w_sum = w_tmp_sum;
assign w_carry = w_tmp_carry;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
w_mem[i] <= 32'h0;
w_ctr_reg <= 6'h0;
end
else begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16) begin
w_tmp_sum = w_mem[w_ctr_reg[3 : 0]];
w_tmp_carry = 32'h00000000;
end
else begin
w_tmp_sum = w_csa_sum;
w_tmp_carry = w_csa_carry;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
always @*
begin : w_mem_update_logic
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
// w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
// w_new calculation, using csa
wire [31:0] w_csa_sum;
wire [31:0] w_csa_carry;
csa_32x4 csa_32x4_1(
.in1(d0),
.in2(d1),
.in3(w_0),
.in4(w_9),
.sum(w_csa_sum),
.carry(w_csa_carry)
);
always @*
begin
w_new = w_csa_sum + {w_csa_carry[30:0], 1'b0};
end
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 6'h0;
w_ctr_we = 1'h0;
if (init)
begin
w_ctr_new = 6'h0;
w_ctr_we = 1'h1;
end
if (next)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1'h1;
end
end // w_ctr
endmodule // sha256_w_mem |
module sha256_k_constants(
input wire [5 : 0] addr,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
00: tmp_K = 32'h428a2f98;
01: tmp_K = 32'h71374491;
02: tmp_K = 32'hb5c0fbcf;
03: tmp_K = 32'he9b5dba5;
04: tmp_K = 32'h3956c25b;
05: tmp_K = 32'h59f111f1;
06: tmp_K = 32'h923f82a4;
07: tmp_K = 32'hab1c5ed5;
08: tmp_K = 32'hd807aa98;
09: tmp_K = 32'h12835b01;
10: tmp_K = 32'h243185be;
11: tmp_K = 32'h550c7dc3;
12: tmp_K = 32'h72be5d74;
13: tmp_K = 32'h80deb1fe;
14: tmp_K = 32'h9bdc06a7;
15: tmp_K = 32'hc19bf174;
16: tmp_K = 32'he49b69c1;
17: tmp_K = 32'hefbe4786;
18: tmp_K = 32'h0fc19dc6;
19: tmp_K = 32'h240ca1cc;
20: tmp_K = 32'h2de92c6f;
21: tmp_K = 32'h4a7484aa;
22: tmp_K = 32'h5cb0a9dc;
23: tmp_K = 32'h76f988da;
24: tmp_K = 32'h983e5152;
25: tmp_K = 32'ha831c66d;
26: tmp_K = 32'hb00327c8;
27: tmp_K = 32'hbf597fc7;
28: tmp_K = 32'hc6e00bf3;
29: tmp_K = 32'hd5a79147;
30: tmp_K = 32'h06ca6351;
31: tmp_K = 32'h14292967;
32: tmp_K = 32'h27b70a85;
33: tmp_K = 32'h2e1b2138;
34: tmp_K = 32'h4d2c6dfc;
35: tmp_K = 32'h53380d13;
36: tmp_K = 32'h650a7354;
37: tmp_K = 32'h766a0abb;
38: tmp_K = 32'h81c2c92e;
39: tmp_K = 32'h92722c85;
40: tmp_K = 32'ha2bfe8a1;
41: tmp_K = 32'ha81a664b;
42: tmp_K = 32'hc24b8b70;
43: tmp_K = 32'hc76c51a3;
44: tmp_K = 32'hd192e819;
45: tmp_K = 32'hd6990624;
46: tmp_K = 32'hf40e3585;
47: tmp_K = 32'h106aa070;
48: tmp_K = 32'h19a4c116;
49: tmp_K = 32'h1e376c08;
50: tmp_K = 32'h2748774c;
51: tmp_K = 32'h34b0bcb5;
52: tmp_K = 32'h391c0cb3;
53: tmp_K = 32'h4ed8aa4a;
54: tmp_K = 32'h5b9cca4f;
55: tmp_K = 32'h682e6ff3;
56: tmp_K = 32'h748f82ee;
57: tmp_K = 32'h78a5636f;
58: tmp_K = 32'h84c87814;
59: tmp_K = 32'h8cc70208;
60: tmp_K = 32'h90befffa;
61: tmp_K = 32'ha4506ceb;
62: tmp_K = 32'hbef9a3f7;
63: tmp_K = 32'hc67178f2;
endcase // case (addr)
end // block: addr_mux
endmodule // sha256_k_constants |
module sha256_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire mode,
input wire [511 : 0] block,
output wire ready,
output wire [255 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA224_H0_0 = 32'hc1059ed8;
parameter SHA224_H0_1 = 32'h367cd507;
parameter SHA224_H0_2 = 32'h3070dd17;
parameter SHA224_H0_3 = 32'hf70e5939;
parameter SHA224_H0_4 = 32'hffc00b31;
parameter SHA224_H0_5 = 32'h68581511;
parameter SHA224_H0_6 = 32'h64f98fa7;
parameter SHA224_H0_7 = 32'hbefa4fa4;
parameter SHA256_H0_0 = 32'h6a09e667;
parameter SHA256_H0_1 = 32'hbb67ae85;
parameter SHA256_H0_2 = 32'h3c6ef372;
parameter SHA256_H0_3 = 32'ha54ff53a;
parameter SHA256_H0_4 = 32'h510e527f;
parameter SHA256_H0_5 = 32'h9b05688c;
parameter SHA256_H0_6 = 32'h1f83d9ab;
parameter SHA256_H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg [31 : 0] f_reg;
reg [31 : 0] f_new;
reg [31 : 0] g_reg;
reg [31 : 0] g_new;
reg [31 : 0] h_reg;
reg [31 : 0] h_new;
reg a_h_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg [31 : 0] H5_reg;
reg [31 : 0] H5_new;
reg [31 : 0] H6_reg;
reg [31 : 0] H6_new;
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [31 : 0] t1;
reg [31 : 0] t2;
wire [31 : 0] k_data;
reg w_init;
reg w_next;
wire [31 : 0] w_data;
wire [31:0] w_data_sum;
wire [31:0] w_data_carry;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha256_k_constants k_constants_inst(
.addr(t_ctr_reg),
.K(k_data)
);
sha256_w_mem w_mem_inst(
.clk(clk),
.reset_n(reset_n),
.block(block),
.init(w_init),
.next(w_next),
.w_sum(w_data_sum),
.w_carry(w_data_carry)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
f_reg <= 32'h0;
g_reg <= 32'h0;
h_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
H5_reg <= 32'h0;
H6_reg <= 32'h0;
H7_reg <= 32'h0;
digest_valid_reg <= 0;
t_ctr_reg <= 6'h0;
sha256_ctrl_reg <= CTRL_IDLE;
end
else begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
t_ctr_reg <= t_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha256_ctrl_we)
sha256_ctrl_reg <= sha256_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H5_new = 32'h0;
H6_new = 32'h0;
H7_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H_we = 1;
if (mode)
begin
H0_new = SHA256_H0_0;
H1_new = SHA256_H0_1;
H2_new = SHA256_H0_2;
H3_new = SHA256_H0_3;
H4_new = SHA256_H0_4;
H5_new = SHA256_H0_5;
H6_new = SHA256_H0_6;
H7_new = SHA256_H0_7;
end
else
begin
H0_new = SHA224_H0_0;
H1_new = SHA224_H0_1;
H2_new = SHA224_H0_2;
H3_new = SHA224_H0_3;
H4_new = SHA224_H0_4;
H5_new = SHA224_H0_5;
H6_new = SHA224_H0_6;
H7_new = SHA224_H0_7;
end
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
reg [31 : 0] sum1;
reg [31 : 0] ch;
always @*
begin : t1_logic
sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
{e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
// t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
// t1 calculation, using csa
wire [31:0] t1_sum;
wire [31:0] t1_carry;
csa_32x6 csa_32x6_1(
.in1(h_reg),
.in2(sum1),
.in3(ch),
.in4(k_data),
.in5(w_data_sum),
.in6({w_data_carry[30:0], 1'b0}),
.sum(t1_sum),
.carry(t1_carry)
);
always @*
begin
t1 = t1_sum + {t1_carry[30:0], 1'b0};
end
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
reg [31 : 0] t2_sum0;
reg [31 : 0] t2_maj;
always @*
begin : t2_logic
t2_sum0 = {a_reg[1 : 0], a_reg[31 : 2]} ^
{a_reg[12 : 0], a_reg[31 : 13]} ^
{a_reg[21 : 0], a_reg[31 : 22]};
t2_maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
// t2 = t2_sum0 + t2_maj;
end // t2_logic
// t2 calculation, using csa
wire [31:0] a_new_sum;
wire [31:0] a_new_carry;
wire [31:0] e_new_sum;
wire [31:0] e_new_carry;
csa_32x4 a_new_csa(
.in1(t1_sum),
.in2({t1_carry[30:0], 1'b0}),
.in3(t2_sum0),
.in4(t2_maj),
.sum(a_new_sum),
.carry(a_new_carry)
);
csa_32x3 e_new_csa(
.in1(t1_sum),
.in2({t1_carry[30:0], 1'b0}),
.in3(d_reg),
.sum(e_new_sum),
.carry(e_new_carry)
);
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
f_new = 32'h0;
g_new = 32'h0;
h_new = 32'h0;
a_h_we = 0;
if (state_init)
begin
a_h_we = 1;
if (first_block)
begin
if (mode)
begin
a_new = SHA256_H0_0;
b_new = SHA256_H0_1;
c_new = SHA256_H0_2;
d_new = SHA256_H0_3;
e_new = SHA256_H0_4;
f_new = SHA256_H0_5;
g_new = SHA256_H0_6;
h_new = SHA256_H0_7;
end
else
begin
a_new = SHA224_H0_0;
b_new = SHA224_H0_1;
c_new = SHA224_H0_2;
d_new = SHA224_H0_3;
e_new = SHA224_H0_4;
f_new = SHA224_H0_5;
g_new = SHA224_H0_6;
h_new = SHA224_H0_7;
end
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
end
end
if (state_update)
begin
// a_new = t1 + t2;
a_new = a_new_sum + {a_new_carry[30:0], 1'b0};
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
// e_new = d_reg + t1;
e_new = e_new_sum + {e_new_carry[30:0], 1'b0};
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 0;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha256_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
if (next)
begin
t_ctr_rst = 1;
w_init = 1;
state_init = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA256_ROUNDS)
begin
sha256_ctrl_new = CTRL_DONE;
sha256_ctrl_we = 1;
end
end
CTRL_DONE:
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 1;
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_core |
module csa_32x6(
input wire [31:0] in1,
input wire [31:0] in2,
input wire [31:0] in3,
input wire [31:0] in4,
input wire [31:0] in5,
input wire [31:0] in6,
output wire [31:0] sum,
output wire [31:0] carry
);
wire [31:0] sum1;
wire [31:0] sum2;
wire [31:0] sum3;
wire [31:0] carry1;
wire [31:0] carry2;
wire [31:0] carry3;
csa_32x3 csa_32x3_1(
.in1(in1),
.in2(in2),
.in3(in3),
.sum(sum1),
.carry(carry1)
);
csa_32x3 csa_32x3_2(
.in1(in4),
.in2(in5),
.in3(in6),
.sum(sum2),
.carry(carry2)
);
csa_32x3 csa_32x3_3(
.in1(sum1),
.in2(sum2),
.in3({carry1[30:0], 1'b0}),
.sum(sum3),
.carry(carry3)
);
csa_32x3 csa_32x3_4(
.in1(sum3),
.in2({carry2[30:0], 1'b0}),
.in3({carry3[30:0], 1'b0}),
.sum(sum),
.carry(carry)
);
endmodule // csa_32x6 |
module cms_heap #(
parameter HEAP_DEPTH = 32,
parameter VALUE_WIDTH = 32,
parameter KEY_WIDTH = 32
) (
input wire ap_clk,
input wire ap_reset,
// A new {key,value} from CMS:
input wire [KEY_WIDTH - 1:0] key_in, // input key from cms
input wire [VALUE_WIDTH - 1:0] value_in, // input value from cms
input wire kv_in_valid, // input {key, value} pair is valid
// heap reading interface:
input wire kv_out_ready, // CMS reads the heap Value part
output wire [KEY_WIDTH-1:0] key_out, // Output bottom key
output wire [VALUE_WIDTH-1:0] value_out, // Output bottom value
output wire kv_out_valid // Output bottom key and value are valid
);
// Heap stages deployment:
// First and last stages are separately instanciated, due to its different wiring
wire [KEY_WIDTH-1:0] key_test_outH[HEAP_DEPTH-1:0];
wire kv_out_validH[HEAP_DEPTH-1:0];
wire [KEY_WIDTH-1:0] key_outH[HEAP_DEPTH-1:0];
wire [VALUE_WIDTH:0] value_outH[HEAP_DEPTH-1:0];
wire [KEY_WIDTH-1:0] key_in_stage0;
wire [VALUE_WIDTH-1:0] value_in_stage0;
reg kv_out_readyQ;
reg bubble_heap;
reg bubble_inflight;
reg kv_valid;
reg kv_validQ;
reg [15:0] heap_settle_window;
// input key & value to top (first) heap stage
assign key_in_stage0 = (bubble_inflight) ? {KEY_WIDTH{1'b0}} : key_in;
assign value_in_stage0 = (bubble_inflight) ? {VALUE_WIDTH{1'b0}} : value_in;
// Output bottom key & value to cms
assign key_out = key_outH[HEAP_DEPTH-1];
assign value_out = value_outH[HEAP_DEPTH-1];
// kv_out_valid is masked for 2*HEAP_DEPTH clocks following latter cms-to-heap write
// This delay is necessary to allow the heap stages to setttle, during which to
// kv_out_valid is masked, to prevent reading the heap (by cms) while the heap stages not settled
assign kv_out_valid = kv_valid & (heap_settle_window == 0);
always @(posedge ap_clk) begin
if (ap_reset) begin
kv_out_readyQ <= 0;
bubble_heap <= 1'b0;
bubble_inflight <= 1'b0;
// kv out from heap (last stage) is always valid. It is dropped to two clocks only when heap is bubbled
kv_valid <= 1'b1;
kv_validQ <= 1'b0;
heap_settle_window <= 16'h0000;
end
// Assert bubble_heap one clock after kv_out_ready was asserted, and keep bubble_heap asserted for 1 clock only
else begin
kv_out_readyQ <= kv_out_ready;
// Bubble-down the heap, following a read by cms
// The heap valid is dropped during this bubble
if (kv_out_ready & ~kv_out_readyQ) begin
bubble_heap <= 1'b1;
kv_valid <= 1'b0;
bubble_inflight <= 1'b1;
end
if (bubble_heap) begin
bubble_heap <= 1'b0;
kv_validQ <= 1'b1;
end
if (kv_validQ) begin
kv_validQ <= 1'b0;
kv_valid <= 1'b1;
bubble_inflight <= 1'b0;
end
// Heap settle window: Count down from latter write-to-heap
// heap settle window is initialized to 2*HEAP_DEPTH, folowing every write-to-heap:
// The heap will be valid for read (by cms) only after the settle window has elapsed (heap being settled)
if (kv_in_valid)
heap_settle_window <= {HEAP_DEPTH, 1'b0};
else if (heap_settle_window > 0)
heap_settle_window <= heap_settle_window -1;
end
end // always @ (posedge ap_clk)
heap_stage # (
.VALUE_WIDTH(32),
.KEY_WIDTH(32)
) heap_top (
.ap_clk(ap_clk),
.ap_reset(ap_reset),
.key_test_in(key_in_stage0),
.key_in(key_in_stage0),
.value_in(value_in_stage0),
.kv_in_valid(kv_in_valid),
.heap_read(bubble_heap),
.key_test_out(key_test_outH[0]),
.key_out(key_outH[0]),
.value_out(value_outH[0]),
.kv_out_valid(kv_out_validH[0])
);
generate
genvar j;
for (j = 1; j < HEAP_DEPTH-1 ; j = j + 1) begin: HeapID
heap_stage # (
.VALUE_WIDTH(32),
.KEY_WIDTH(32)
) heap (
.ap_clk(ap_clk),
.ap_reset(ap_reset),
.key_test_in(key_test_outH[j-1]),
.key_in(key_outH[j-1]),
.value_in(value_outH[j-1]),
.kv_in_valid(kv_out_validH[j-1]),
.heap_read(bubble_heap),
.key_test_out(key_test_outH[j]),
.key_out(key_outH[j]),
.value_out(value_outH[j]),
.kv_out_valid(kv_out_validH[j])
);
end
endgenerate
// This module is a duplicate of the above but with the distinction:
// The output ket_test_out is not not needed, thus dropped.
last_heap_stage # (
.VALUE_WIDTH(32),
.KEY_WIDTH(32)
) heap_last (
.ap_clk(ap_clk),
.ap_reset(ap_reset),
.key_test_in(key_test_outH[HEAP_DEPTH-2]),
.key_in(key_outH[HEAP_DEPTH-2]),
.value_in(value_outH[HEAP_DEPTH-2]),
.kv_in_valid(kv_out_validH[HEAP_DEPTH-2]),
.heap_read(bubble_heap),
// .key_test_out(key_test_outH[HEAP_DEPTH-1]),
.key_out(key_outH[HEAP_DEPTH-1]),
.value_out(value_outH[HEAP_DEPTH-1]),
.kv_out_valid(kv_out_validH[HEAP_DEPTH-1])
);
//-------------------------------------------------
// End of heap stages instatiation
//-------------------------------------------------
endmodule |
module cms_cms_top (
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
ap_clk,
ap_rst_n,
ik_host_metadata_input_V_V_TDATA,
ik_host_data_input_V_V_TDATA,
ik_host_action_V_V_TDATA,
ik_host_metadata_output_V_V_TDATA,
ik_host_data_output_V_V_TDATA,
ik_net_metadata_input_V_V_TDATA,
ik_net_data_input_V_V_TDATA,
ik_net_action_V_V_TDATA,
ik_net_metadata_output_V_V_TDATA,
ik_net_data_output_V_V_TDATA,
ik_host_metadata_input_V_V_TVALID,
ik_host_metadata_input_V_V_TREADY,
ik_host_data_input_V_V_TVALID,
ik_host_data_input_V_V_TREADY,
ik_host_action_V_V_TVALID,
ik_host_action_V_V_TREADY,
ik_host_metadata_output_V_V_TVALID,
ik_host_metadata_output_V_V_TREADY,
ik_host_data_output_V_V_TVALID,
ik_host_data_output_V_V_TREADY,
ik_net_metadata_input_V_V_TVALID,
ik_net_metadata_input_V_V_TREADY,
ik_net_data_input_V_V_TVALID,
ik_net_data_input_V_V_TREADY,
ik_net_action_V_V_TVALID,
ik_net_action_V_V_TREADY,
ik_net_metadata_output_V_V_TVALID,
ik_net_metadata_output_V_V_TREADY,
ik_net_data_output_V_V_TVALID,
ik_net_data_output_V_V_TREADY
);
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (C_S_AXI_AXILITES_DATA_WIDTH / 8);
`ifdef CMS_HEAP_DEPTH
parameter HEAP_DEPTH = `CMS_HEAP_DEPTH;
`else
parameter HEAP_DEPTH = 256;
`endif
`ifdef CMS_VALUE_WIDTH
parameter VALUE_WIDTH = `CMS_VALUE_WIDTH;
`else
parameter VALUE_WIDTH = 32;
`endif
`ifdef CMS_KEY_WIDTH
parameter KEY_WIDTH = `CMS_KEY_WIDTH;
`else
parameter KEY_WIDTH = 32;
`endif
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1 : 0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
input ap_clk;
input ap_rst_n;
input [239:0] ik_host_metadata_input_V_V_TDATA;
input [295:0] ik_host_data_input_V_V_TDATA;
output [7:0] ik_host_action_V_V_TDATA;
output [239:0] ik_host_metadata_output_V_V_TDATA;
output [295:0] ik_host_data_output_V_V_TDATA;
input [239:0] ik_net_metadata_input_V_V_TDATA;
input [295:0] ik_net_data_input_V_V_TDATA;
output [7:0] ik_net_action_V_V_TDATA;
output [239:0] ik_net_metadata_output_V_V_TDATA;
output [295:0] ik_net_data_output_V_V_TDATA;
input ik_host_metadata_input_V_V_TVALID;
output ik_host_metadata_input_V_V_TREADY;
input ik_host_data_input_V_V_TVALID;
output ik_host_data_input_V_V_TREADY;
output ik_host_action_V_V_TVALID;
input ik_host_action_V_V_TREADY;
output ik_host_metadata_output_V_V_TVALID;
input ik_host_metadata_output_V_V_TREADY;
output ik_host_data_output_V_V_TVALID;
input ik_host_data_output_V_V_TREADY;
input ik_net_metadata_input_V_V_TVALID;
output ik_net_metadata_input_V_V_TREADY;
input ik_net_data_input_V_V_TVALID;
output ik_net_data_input_V_V_TREADY;
output ik_net_action_V_V_TVALID;
input ik_net_action_V_V_TREADY;
output ik_net_metadata_output_V_V_TVALID;
input ik_net_metadata_output_V_V_TREADY;
output ik_net_data_output_V_V_TVALID;
input ik_net_data_output_V_V_TREADY;
wire [63:0] kv_out; // cms to heap: A new kv pair
wire kv_valid; // cms to heap: A new kv pair is valid
wire heap_out_ready; // CMS has read current heap out key & value. Use this indicatioin to bubble-down the heap
wire [63:0] heap_out_data; // Heap bottom key & value
wire heap_out_valid; // Heap bottom key & value is valid
///////////////////////////////////////////////////////////////////////////////
// cms_top:
///////////////////////////////////////////////////////////////////////////////
cms_cms_ikernel #(
.C_S_AXI_AXILITES_ADDR_WIDTH(C_S_AXI_AXILITES_ADDR_WIDTH),
.C_S_AXI_AXILITES_DATA_WIDTH(C_S_AXI_AXILITES_DATA_WIDTH)
) cms (
.s_axi_AXILiteS_AWREADY(s_axi_AXILiteS_AWREADY),
.s_axi_AXILiteS_AWVALID(s_axi_AXILiteS_AWVALID),
.s_axi_AXILiteS_AWADDR(s_axi_AXILiteS_AWADDR),
.s_axi_AXILiteS_WVALID(s_axi_AXILiteS_WVALID),
.s_axi_AXILiteS_WREADY(s_axi_AXILiteS_WREADY),
.s_axi_AXILiteS_WDATA(s_axi_AXILiteS_WDATA),
.s_axi_AXILiteS_WSTRB(s_axi_AXILiteS_WSTRB),
.s_axi_AXILiteS_ARVALID(s_axi_AXILiteS_ARVALID),
.s_axi_AXILiteS_ARREADY(s_axi_AXILiteS_ARREADY),
.s_axi_AXILiteS_ARADDR(s_axi_AXILiteS_ARADDR),
.s_axi_AXILiteS_BVALID(s_axi_AXILiteS_BVALID),
.s_axi_AXILiteS_BREADY(s_axi_AXILiteS_BREADY),
.s_axi_AXILiteS_BRESP(s_axi_AXILiteS_BRESP),
.s_axi_AXILiteS_RVALID(s_axi_AXILiteS_RVALID),
.s_axi_AXILiteS_RREADY(s_axi_AXILiteS_RREADY),
.s_axi_AXILiteS_RDATA(s_axi_AXILiteS_RDATA),
.s_axi_AXILiteS_RRESP(s_axi_AXILiteS_RRESP),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ik_host_metadata_output_V_V_TDATA(ik_host_metadata_output_V_V_TDATA),
.ik_host_metadata_output_V_V_TVALID(ik_host_metadata_output_V_V_TVALID),
.ik_host_metadata_output_V_V_TREADY(ik_host_metadata_output_V_V_TREADY),
.ik_host_metadata_input_V_V_TDATA(ik_host_metadata_input_V_V_TDATA),
.ik_host_metadata_input_V_V_TVALID(ik_host_metadata_input_V_V_TVALID),
.ik_host_metadata_input_V_V_TREADY(ik_host_metadata_input_V_V_TREADY),
.ik_host_data_output_V_V_TDATA(ik_host_data_output_V_V_TDATA),
.ik_host_data_output_V_V_TVALID(ik_host_data_output_V_V_TVALID),
.ik_host_data_output_V_V_TREADY(ik_host_data_output_V_V_TREADY),
.ik_host_data_input_V_V_TDATA(ik_host_data_input_V_V_TDATA),
.ik_host_data_input_V_V_TVALID(ik_host_data_input_V_V_TVALID),
.ik_host_data_input_V_V_TREADY(ik_host_data_input_V_V_TREADY),
.ik_host_action_V_V_TDATA(ik_host_action_V_V_TDATA),
.ik_host_action_V_V_TVALID(ik_host_action_V_V_TVALID),
.ik_host_action_V_V_TREADY(ik_host_action_V_V_TREADY),
.ik_net_metadata_output_V_V_TDATA(ik_net_metadata_output_V_V_TDATA),
.ik_net_metadata_output_V_V_TVALID(ik_net_metadata_output_V_V_TVALID),
.ik_net_metadata_output_V_V_TREADY(ik_net_metadata_output_V_V_TREADY),
.ik_net_metadata_input_V_V_TDATA(ik_net_metadata_input_V_V_TDATA),
.ik_net_metadata_input_V_V_TVALID(ik_net_metadata_input_V_V_TVALID),
.ik_net_metadata_input_V_V_TREADY(ik_net_metadata_input_V_V_TREADY),
.ik_net_data_output_V_V_TDATA(ik_net_data_output_V_V_TDATA),
.ik_net_data_output_V_V_TVALID(ik_net_data_output_V_V_TVALID),
.ik_net_data_output_V_V_TREADY(ik_net_data_output_V_V_TREADY),
.ik_net_data_input_V_V_TDATA(ik_net_data_input_V_V_TDATA),
.ik_net_data_input_V_V_TVALID(ik_net_data_input_V_V_TVALID),
.ik_net_data_input_V_V_TREADY(ik_net_data_input_V_V_TREADY),
.ik_net_action_V_V_TDATA(ik_net_action_V_V_TDATA),
.ik_net_action_V_V_TVALID(ik_net_action_V_V_TVALID),
.ik_net_action_V_V_TREADY(ik_net_action_V_V_TREADY),
.to_heap(kv_out),
.to_heap_ap_vld(kv_valid),
.heap_out_V_TDATA(heap_out_data),
.heap_out_V_TVALID(heap_out_valid),
.heap_out_V_TREADY(heap_out_ready),
.k_value_V(HEAP_DEPTH)
);
cms_heap #(
.HEAP_DEPTH(HEAP_DEPTH),
.VALUE_WIDTH(VALUE_WIDTH),
.KEY_WIDTH(KEY_WIDTH)
) heap (
.ap_clk(ap_clk),
.ap_reset(~ap_rst_n),
// A new {key,value} from cms:
.key_in(kv_out[31:0]),
.value_in(kv_out[63:32]),
.kv_in_valid(kv_valid),
// heap reading interface:
.kv_out_ready(heap_out_ready),
.key_out(heap_out_data[31:0]),
.value_out(heap_out_data[63:32]),
.kv_out_valid(heap_out_valid)
);
endmodule |
module heap_stage #(
parameter VALUE_WIDTH = 32,
parameter KEY_WIDTH = 32
) (
input wire ap_clk,
input wire ap_reset,
input wire [KEY_WIDTH - 1:0] key_test_in, // input key to be tested
input wire [KEY_WIDTH - 1:0] key_in, // input key from prev. heap stage
input wire [VALUE_WIDTH - 1:0] value_in, // input value from prev. heap stage
input wire kv_in_valid, // input key,value pair to be tested is ready
input wire heap_read, // heap read request, from AXI-lite mechanism in CMS.
output wire [KEY_WIDTH - 1:0] key_test_out, // key to be tested, out to next heap stage
output wire [KEY_WIDTH - 1:0] key_out, // current stage key, out to next heap stage
output wire [VALUE_WIDTH - 1:0] value_out, // current stage value, out to next heap stage
output wire kv_out_valid // current key,value pair is valid, out to next heap stage
);
//------------------------heap stage fsm-------------------
localparam
K_TEST = 2'd0,
V_TEST = 2'd1,
KV_WRITE = 2'd2,
PASSTHRU = 2'd3;
// heap stage data structures:
// Option 1: Using regs:
reg [KEY_WIDTH - 1:0] key_test;
reg kv_valid;
reg stage_valid;
reg [KEY_WIDTH - 1:0] key;
reg [VALUE_WIDTH - 1:0] value;
reg [KEY_WIDTH - 1:0] key_out_r;
reg [VALUE_WIDTH - 1:0] value_out_r;
// heap stage data structures:
// Option 2: Using distributed RAM
/*
parameter RAM_WIDTH = 256;
parameter RAM_ADDR_BITS = 0; // A single entry RAM
(* RAM_STYLE="{DISTRIBUTED}" *)
reg [RAM_WIDTH-1:0] kv_stage [(2**RAM_ADDR_BITS)-1:0];
wire [RAM_WIDTH-1:0] kv_stage_out;
//wire [RAM_ADDR_BITS-1:0] <addressA>, <addressB>;
wire [RAM_WIDTH-1:0] kv_stage_in;
wire kv_stage_write;
always @(posedge ap_clk) begin
if (<enableA>) begin
if (<kv_stage_write>)
kv_stage[0] <= kv_stage_in;
// kv_stage_out <= kv_stage[0];
end
end
*/
reg [1:0] hstate;
wire key_is_tested;
wire heap_entry_is_bubbled;
assign kv_out_valid = kv_valid;
assign key_test_out = key_test;
assign key_out = key_out_r;
assign value_out = value_out_r;
always @(posedge ap_clk) begin
if (ap_reset) begin
key <= 0;
value <= 0;
key_out_r <= 0;
value_out_r <= 0;
kv_valid <= 0;
hstate <= K_TEST;
stage_valid <= 0;
end
else begin
// Heap stage State Machine
if (hstate == K_TEST) begin
kv_valid <= 1'b0;
if (heap_read) begin
hstate = PASSTHRU;
// Reading thru AXI-lite:
// heap stages are bubbled, two stages per each read request.
// The second bubble in PASSTHRU state
key_out_r <= key;
value_out_r <= value;
key <= key_in;
value <= value_in;
end
else if (kv_in_valid) begin
if (stage_valid & (key_test_in == key) | !stage_valid) begin
hstate = KV_WRITE;
end
else begin
hstate = V_TEST;
end
end
end
else if (hstate == KV_WRITE) begin
// The incoming KV pair is loaded into current stage if:
// 1. Curent stage was empty (!stage_valid), or
// 2. The incoming K matches the existing
// In both cases, nothing is passed down to next stage
hstate = K_TEST;
stage_valid <= 1'b1;
// Replace current kv with the incoming pair.
key <= key_in;
value <= value_in;
// Prev. kv values are NOT forwarded to next heap stage, but still the output kv registers are also written, just to keep its write_enable signal common to all the registers in a heap stage
key_out_r <= key;
value_out_r <= value;
end
else if (hstate == V_TEST) begin
hstate = K_TEST;
kv_valid <= 1'b1;
key_test <= key_test_in;
if (value_in > value) begin
// The new value is greater than current value.
// Replace current kv with the incoming pair and forward prev. kv values to next heap stage
key <= key_in;
value <= value_in;
key_out_r <= key;
value_out_r <= value;
end
else begin
// The new value is not greater than current value.
// Current kv pair is maintained. Incoming pair is forwarded to next heap stage
key_out_r <= key_in;
value_out_r <= value_in;
end
end
else if (hstate == PASSTHRU) begin
hstate = K_TEST;
stage_valid <= 0;
// Reading thru AXI-lite:
// heap stages are bubbled, two stages per each read request.
// The first bubble was done in prev. K_TEST state
key_out_r <= key;
value_out_r <= value;
key <= key_in;
value <= value_in;
end
else
hstate = K_TEST;
end // else (if (ap_reset))
end //always @(posedge ap_clk)
endmodule |
module fpga_top
(
// Inputs
input clk_i
,input clk_x5_i
,input rst_i
// Outputs
,output dvi_red_o
,output dvi_green_o
,output dvi_blue_o
,output dvi_clock_o
);
wire [ 7:0] video_blue_w;
wire video_hsync_w;
wire video_vsync_w;
wire [ 7:0] video_green_w;
wire [ 7:0] video_red_w;
wire video_blank_w;
dvi
u_dvi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.clk_x5_i(clk_x5_i)
,.vga_red_i(video_red_w)
,.vga_green_i(video_green_w)
,.vga_blue_i(video_blue_w)
,.vga_blank_i(video_blank_w)
,.vga_hsync_i(video_hsync_w)
,.vga_vsync_i(video_vsync_w)
// Outputs
,.dvi_red_o(dvi_red_o)
,.dvi_green_o(dvi_green_o)
,.dvi_blue_o(dvi_blue_o)
,.dvi_clock_o(dvi_clock_o)
);
video_gen
u_gen
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
// Outputs
,.vga_red_o(video_red_w)
,.vga_green_o(video_green_w)
,.vga_blue_o(video_blue_w)
,.vga_blank_o(video_blank_w)
,.vga_hsync_o(video_hsync_w)
,.vga_vsync_o(video_vsync_w)
);
endmodule |
module reset_gen
(
input clk_i,
output rst_o
);
reg [3:0] count_q = 4'b0;
reg rst_q = 1'b1;
always @(posedge clk_i)
if (count_q != 4'hF)
count_q <= count_q + 4'd1;
else
rst_q <= 1'b0;
assign rst_o = rst_q;
endmodule |
module artix7_pll
(
// Inputs
input clkref_i
// Outputs
,output clkout0_o
,output clkout1_o
);
wire clkref_buffered_w;
wire clkfbout_w;
wire clkfbout_buffered_w;
wire pll_clkout0_w;
wire pll_clkout0_buffered_w;
wire pll_clkout1_w;
wire pll_clkout1_buffered_w;
// Input buffering
IBUF IBUF_IN
(
.I (clkref_i),
.O (clkref_buffered_w)
);
// Clocking primitive
PLLE2_BASE
#(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
.CLKIN1_PERIOD(10.0), // Input clock period in ns resolution
.CLKFBOUT_MULT(10), // VCO=1000MHz
// CLKOUTx_DIVIDE: Divide amount for each CLKOUT(1-128)
.CLKOUT0_DIVIDE(20), // CLK0=50MHz
.CLKOUT1_DIVIDE(4), // CLK1=250MHz
// CLKOUTx_DUTY_CYCLE: Duty cycle for each CLKOUT
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
// CLKOUTx_PHASE: Phase offset for each CLKOUT
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value (1-56)
.REF_JITTER1(0.0), // Ref. input jitter in UI (0.000-0.999)
.STARTUP_WAIT("TRUE") // Delay DONE until PLL Locks ("TRUE"/"FALSE")
)
u_pll
(
.CLKFBOUT(clkfbout_w),
.CLKOUT0(pll_clkout0_w),
.CLKOUT1(pll_clkout1_w),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKIN1(clkref_buffered_w),
.CLKFBIN(clkfbout_buffered_w)
);
BUFH u_clkfb_buf
(
.I(clkfbout_w),
.O(clkfbout_buffered_w)
);
//-----------------------------------------------------------------
// CLK_OUT0
//-----------------------------------------------------------------
BUFG u_clkout0_buf
(
.I(pll_clkout0_w),
.O(pll_clkout0_buffered_w)
);
assign clkout0_o = pll_clkout0_buffered_w;
//-----------------------------------------------------------------
// CLK_OUT1
//-----------------------------------------------------------------
BUFG u_clkout1_buf
(
.I(pll_clkout1_w),
.O(pll_clkout1_buffered_w)
);
assign clkout1_o = pll_clkout1_buffered_w;
endmodule |
module top
(
input clk100mhz,
output [3:0] tmds_out_p,
output [3:0] tmds_out_n
);
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
wire clk50_w;
wire clk250_w;
wire rst_w;
wire dvi_red_w;
wire dvi_green_w;
wire dvi_blue_w;
wire dvi_clock_w;
artix7_pll
u_pll
(
// Inputs
.clkref_i(clk100mhz)
// Outputs
,.clkout0_o(clk50_w)
,.clkout1_o(clk250_w)
);
reset_gen
u_rst
(
.clk_i(clk50_w),
.rst_o(rst_w)
);
fpga_top
u_top
(
.clk_i(clk50_w)
,.rst_i(rst_w)
,.clk_x5_i(clk250_w)
,.dvi_red_o(dvi_red_w)
,.dvi_green_o(dvi_green_w)
,.dvi_blue_o(dvi_blue_w)
,.dvi_clock_o(dvi_clock_w)
);
OBUFDS u_buf_b
(
.O(tmds_out_p[0]),
.OB(tmds_out_n[0]),
.I(dvi_blue_w)
);
OBUFDS u_buf_g
(
.O(tmds_out_p[1]),
.OB(tmds_out_n[1]),
.I(dvi_green_w)
);
OBUFDS u_buf_r
(
.O(tmds_out_p[2]),
.OB(tmds_out_n[2]),
.I(dvi_red_w)
);
OBUFDS u_buf_c
(
.O(tmds_out_p[3]),
.OB(tmds_out_n[3]),
.I(dvi_clock_w)
);
endmodule |
module video_gen
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 800
,parameter HEIGHT = 600
,parameter REFRESH = 72
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
// Outputs
,output [ 7:0] vga_red_o
,output [ 7:0] vga_green_o
,output [ 7:0] vga_blue_o
,output vga_blank_o
,output vga_hsync_o
,output vga_vsync_o
);
//-----------------------------------------------------------------
// Video Timings
//-----------------------------------------------------------------
localparam H_REZ = WIDTH;
localparam V_REZ = HEIGHT;
localparam CLK_MHZ = (WIDTH == 640 && REFRESH == 60) ? 25.175 :
(WIDTH == 800 && REFRESH == 72) ? 50.00 :
(WIDTH == 1280 && REFRESH == 60) ? 74.25 :
(WIDTH == 1920 && REFRESH == 60) ? 148.5 :
0;
localparam H_SYNC_START = (WIDTH == 640 && REFRESH == 60) ? 656 :
(WIDTH == 800 && REFRESH == 72) ? 856 :
(WIDTH == 1280 && REFRESH == 60) ? 1390:
(WIDTH == 1920 && REFRESH == 60) ? 2008:
0;
localparam H_SYNC_END = (WIDTH == 640 && REFRESH == 60) ? 752 :
(WIDTH == 800 && REFRESH == 72) ? 976 :
(WIDTH == 1280 && REFRESH == 60) ? 1430:
(WIDTH == 1920 && REFRESH == 60) ? 2052:
0;
localparam H_MAX = (WIDTH == 640 && REFRESH == 60) ? 800 :
(WIDTH == 800 && REFRESH == 72) ? 1040:
(WIDTH == 1280 && REFRESH == 60) ? 1650:
(WIDTH == 1920 && REFRESH == 60) ? 2200:
0;
localparam V_SYNC_START = (HEIGHT == 480 && REFRESH == 60) ? 490 :
(HEIGHT == 600 && REFRESH == 72) ? 637 :
(HEIGHT == 720 && REFRESH == 60) ? 725 :
(HEIGHT == 1080 && REFRESH == 60)? 1084 :
0;
localparam V_SYNC_END = (HEIGHT == 480 && REFRESH == 60) ? 492 :
(HEIGHT == 600 && REFRESH == 72) ? 643 :
(HEIGHT == 720 && REFRESH == 60) ? 730 :
(HEIGHT == 1080 && REFRESH == 60)? 1089:
0;
localparam V_MAX = (HEIGHT == 480 && REFRESH == 60) ? 525 :
(HEIGHT == 600 && REFRESH == 72) ? 666 :
(HEIGHT == 720 && REFRESH == 60) ? 750 :
(HEIGHT == 1080 && REFRESH == 60)? 1125:
0;
//-----------------------------------------------------------------
// Colour Bars
//-----------------------------------------------------------------
localparam H_STRIDE = WIDTH / 7;
localparam C0_S = 0;
localparam C0_E = H_STRIDE-1;
localparam C1_S = C0_E + 1;
localparam C1_E = C1_S + H_STRIDE - 1;
localparam C2_S = C1_E + 1;
localparam C2_E = C2_S + H_STRIDE - 1;
localparam C3_S = C2_E + 1;
localparam C3_E = C3_S + H_STRIDE - 1;
localparam C4_S = C3_E + 1;
localparam C4_E = C4_S + H_STRIDE - 1;
localparam C5_S = C4_E + 1;
localparam C5_E = C5_S + H_STRIDE - 1;
localparam C6_S = C5_E + 1;
localparam C6_E = C6_S + H_STRIDE - 1;
//-----------------------------------------------------------------
// HSYNC, VSYNC
//-----------------------------------------------------------------
reg [11:0] h_pos_q;
reg [11:0] v_pos_q;
reg h_sync_q;
reg v_sync_q;
reg active_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
h_pos_q <= 12'b0;
else if (h_pos_q == H_MAX)
h_pos_q <= 12'b0;
else
h_pos_q <= h_pos_q + 12'd1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
v_pos_q <= 12'b0;
else if (h_pos_q == H_MAX)
begin
if (v_pos_q == V_MAX)
v_pos_q <= 12'b0;
else
v_pos_q <= v_pos_q + 12'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
h_sync_q <= 1'b0;
else if (h_pos_q >= H_SYNC_START && h_pos_q < H_SYNC_END)
h_sync_q <= 1'b1;
else
h_sync_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
v_sync_q <= 1'b0;
else if (v_pos_q >= V_SYNC_START && v_pos_q < V_SYNC_END)
v_sync_q <= 1'b1;
else
v_sync_q <= 1'b0;
// 75% white (192, 192, 192)
// 75% yellow (192, 192, 0)
// 75% cyan (0, 192, 192)
// 75% green (0, 192, 0)
// 75% magenta (192, 0, 192)
// 75% red (192, 0, 0)
// 75% blue (0, 0, 192)
reg [7:0] red_r;
reg [7:0] green_r;
reg [7:0] blue_r;
always @ *
begin
red_r = 8'b0;
green_r = 8'b0;
blue_r = 8'b0;
if (h_pos_q <= C0_E)
begin
red_r = 8'd192;
green_r = 8'd192;
blue_r = 8'd192;
end
else if (h_pos_q >= C1_S && h_pos_q <= C1_E)
begin
red_r = 8'd192;
green_r = 8'd192;
blue_r = 8'd0;
end
else if (h_pos_q >= C2_S && h_pos_q <= C2_E)
begin
red_r = 8'd0;
green_r = 8'd192;
blue_r = 8'd192;
end
else if (h_pos_q >= C3_S && h_pos_q <= C3_E)
begin
red_r = 8'd0;
green_r = 8'd192;
blue_r = 8'd0;
end
else if (h_pos_q >= C4_S && h_pos_q <= C4_E)
begin
red_r = 8'd192;
green_r = 8'd0;
blue_r = 8'd192;
end
else if (h_pos_q >= C5_S && h_pos_q <= C5_E)
begin
red_r = 8'd192;
green_r = 8'd0;
blue_r = 8'd0;
end
else //if (h_pos_q >= C6_S && h_pos_q <= C6_E)
begin
red_r = 8'd0;
green_r = 8'd0;
blue_r = 8'd192;
end
end
assign vga_red_o = red_r;
assign vga_green_o = green_r;
assign vga_blue_o = blue_r;
assign vga_hsync_o = h_sync_q;
assign vga_vsync_o = v_sync_q;
assign vga_blank_o = (h_pos_q < H_REZ && v_pos_q < V_REZ) ? 1'b0 : 1'b1;
endmodule |
module dvi
(
// Inputs
input clk_i
,input rst_i
,input clk_x5_i
,input [ 7:0] vga_red_i
,input [ 7:0] vga_green_i
,input [ 7:0] vga_blue_i
,input vga_blank_i
,input vga_hsync_i
,input vga_vsync_i
// Outputs
,output dvi_red_o
,output dvi_green_o
,output dvi_blue_o
,output dvi_clock_o
);
//-----------------------------------------------------------------
// TMDS encoders [clk]
//-----------------------------------------------------------------
wire [9:0] tmds_red_w;
wire [9:0] tmds_green_w;
wire [9:0] tmds_blue_w;
dvi_tmds_encoder
u_tmds_red
(
.clk(clk_i),
.reset(rst_i),
.data(vga_red_i),
.c(0),
.blank(vga_blank_i),
.encoded(tmds_red_w)
);
dvi_tmds_encoder
u_tmds_green
(
.clk(clk_i),
.reset(rst_i),
.data(vga_green_i),
.c(0),
.blank(vga_blank_i),
.encoded(tmds_green_w)
);
dvi_tmds_encoder
u_tmds_blue
(
.clk(clk_i),
.reset(rst_i),
.data(vga_blue_i),
.c({vga_vsync_i,vga_hsync_i}),
.blank(vga_blank_i),
.encoded(tmds_blue_w)
);
//-----------------------------------------------------------------
// Clock crossing (clk -> clk_x5)
//-----------------------------------------------------------------
reg toggle_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
toggle_q <= 1'b0;
else
toggle_q <= ~toggle_q;
wire toggle_x5_w;
dvi_resync
u_resync
(
.clk_i(clk_x5_i)
,.rst_i(rst_i)
,.async_i(toggle_q)
,.sync_o(toggle_x5_w)
);
reg toggle_x5_q;
always @ (posedge clk_x5_i or posedge rst_i)
if (rst_i)
toggle_x5_q <= 1'b0;
else
toggle_x5_q <= toggle_x5_w;
// capture_w is delays the capture in clk_x5_i of the tmds_xx_w signals
// to 2-3 cycles after they were last updated in clk_i.
wire capture_w = toggle_x5_w ^ toggle_x5_q;
reg [9:0] tmds_red_x5_q;
reg [9:0] tmds_green_x5_q;
reg [9:0] tmds_blue_x5_q;
always @ (posedge clk_x5_i or posedge rst_i)
if (rst_i)
begin
tmds_red_x5_q <= 10'b0;
tmds_green_x5_q <= 10'b0;
tmds_blue_x5_q <= 10'b0;
end
else if (capture_w)
begin
tmds_red_x5_q <= tmds_red_w;
tmds_green_x5_q <= tmds_green_w;
tmds_blue_x5_q <= tmds_blue_w;
end
//-----------------------------------------------------------------
// Output serialisers [clk_x5]
//-----------------------------------------------------------------
reg [9:0] dvi_red_q;
reg [9:0] dvi_green_q;
reg [9:0] dvi_blue_q;
reg [9:0] dvi_clock_q;
reg dvi_strobe_q;
always @(posedge clk_x5_i or posedge rst_i)
if (rst_i)
dvi_clock_q <= 10'b0000011111;
else
dvi_clock_q <= {dvi_clock_q[1:0], dvi_clock_q[9:2]};
wire dvi_strobe_w = (dvi_clock_q == 10'b0001111100);
always @(posedge clk_x5_i or posedge rst_i)
if (rst_i)
dvi_strobe_q <= 1'b0;
else
dvi_strobe_q <= dvi_strobe_w;
always @(posedge clk_x5_i or posedge rst_i)
if (rst_i)
begin
dvi_red_q <= 10'b0;
dvi_green_q <= 10'b0;
dvi_blue_q <= 10'b0;
end
else if (dvi_strobe_q)
begin
dvi_red_q <= tmds_red_x5_q;
dvi_green_q <= tmds_green_x5_q;
dvi_blue_q <= tmds_blue_x5_q;
end
else
begin
dvi_red_q <= {2'b00, dvi_red_q[9:2]};
dvi_green_q <= {2'b00, dvi_green_q[9:2]};
dvi_blue_q <= {2'b00, dvi_blue_q[9:2]};
end
dvi_serialiser
u_ddr_r
(
.clk_i(clk_x5_i)
,.rst_i(rst_i)
,.strobe_i(dvi_strobe_q)
,.data_i(dvi_red_q)
,.serial_o(dvi_red_o)
);
dvi_serialiser
u_ddr_g
(
.clk_i(clk_x5_i)
,.rst_i(rst_i)
,.strobe_i(dvi_strobe_q)
,.data_i(dvi_green_q)
,.serial_o(dvi_green_o)
);
dvi_serialiser
u_ddr_b
(
.clk_i(clk_x5_i)
,.rst_i(rst_i)
,.strobe_i(dvi_strobe_q)
,.data_i(dvi_blue_q)
,.serial_o(dvi_blue_o)
);
dvi_serialiser
u_ddr_c
(
.clk_i(clk_x5_i)
,.rst_i(rst_i)
,.strobe_i(dvi_strobe_q)
,.data_i(dvi_clock_q)
,.serial_o(dvi_clock_o)
);
endmodule |
module dvi_framebuffer
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter VIDEO_WIDTH = 800
,parameter VIDEO_HEIGHT = 600
,parameter VIDEO_REFRESH = 72
,parameter VIDEO_ENABLE = 1
,parameter VIDEO_X2_MODE = 0
,parameter VIDEO_FB_RAM = 32'h3000000
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input clk_x5_i
,input cfg_awvalid_i
,input [31:0] cfg_awaddr_i
,input cfg_wvalid_i
,input [31:0] cfg_wdata_i
,input [3:0] cfg_wstrb_i
,input cfg_bready_i
,input cfg_arvalid_i
,input [31:0] cfg_araddr_i
,input cfg_rready_i
,input outport_awready_i
,input outport_wready_i
,input outport_bvalid_i
,input [1:0] outport_bresp_i
,input [3:0] outport_bid_i
,input outport_arready_i
,input outport_rvalid_i
,input [31:0] outport_rdata_i
,input [1:0] outport_rresp_i
,input [3:0] outport_rid_i
,input outport_rlast_i
// Outputs
,output cfg_awready_o
,output cfg_wready_o
,output cfg_bvalid_o
,output [1:0] cfg_bresp_o
,output cfg_arready_o
,output cfg_rvalid_o
,output [31:0] cfg_rdata_o
,output [1:0] cfg_rresp_o
,output intr_o
,output outport_awvalid_o
,output [31:0] outport_awaddr_o
,output [3:0] outport_awid_o
,output [7:0] outport_awlen_o
,output [1:0] outport_awburst_o
,output outport_wvalid_o
,output [31:0] outport_wdata_o
,output [3:0] outport_wstrb_o
,output outport_wlast_o
,output outport_bready_o
,output outport_arvalid_o
,output [31:0] outport_araddr_o
,output [3:0] outport_arid_o
,output [7:0] outport_arlen_o
,output [1:0] outport_arburst_o
,output outport_rready_o
,output dvi_red_o
,output dvi_green_o
,output dvi_blue_o
,output dvi_clock_o
);
//-----------------------------------------------------------------
// Write address / data split
//-----------------------------------------------------------------
// Address but no data ready
reg awvalid_q;
// Data but no data ready
reg wvalid_q;
wire wr_cmd_accepted_w = (cfg_awvalid_i && cfg_awready_o) || awvalid_q;
wire wr_data_accepted_w = (cfg_wvalid_i && cfg_wready_o) || wvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_q <= 1'b0;
else if (cfg_awvalid_i && cfg_awready_o && !wr_data_accepted_w)
awvalid_q <= 1'b1;
else if (wr_data_accepted_w)
awvalid_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_q <= 1'b0;
else if (cfg_wvalid_i && cfg_wready_o && !wr_cmd_accepted_w)
wvalid_q <= 1'b1;
else if (wr_cmd_accepted_w)
wvalid_q <= 1'b0;
//-----------------------------------------------------------------
// Capture address (for delayed data)
//-----------------------------------------------------------------
reg [7:0] wr_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wr_addr_q <= 8'b0;
else if (cfg_awvalid_i && cfg_awready_o)
wr_addr_q <= cfg_awaddr_i[7:0];
wire [7:0] wr_addr_w = awvalid_q ? wr_addr_q : cfg_awaddr_i[7:0];
//-----------------------------------------------------------------
// Retime write data
//-----------------------------------------------------------------
reg [31:0] wr_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wr_data_q <= 32'b0;
else if (cfg_wvalid_i && cfg_wready_o)
wr_data_q <= cfg_wdata_i;
//-----------------------------------------------------------------
// Request Logic
//-----------------------------------------------------------------
wire read_en_w = cfg_arvalid_i & cfg_arready_o;
wire write_en_w = wr_cmd_accepted_w && wr_data_accepted_w;
//-----------------------------------------------------------------
// Accept Logic
//-----------------------------------------------------------------
assign cfg_arready_o = ~cfg_rvalid_o;
assign cfg_awready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~awvalid_q;
assign cfg_wready_o = ~cfg_bvalid_o && ~cfg_arvalid_i && ~wvalid_q;
//-----------------------------------------------------------------
// Register config
//-----------------------------------------------------------------
reg config_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
config_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `CONFIG))
config_wr_q <= 1'b1;
else
config_wr_q <= 1'b0;
// config_x2_mode [internal]
reg config_x2_mode_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
config_x2_mode_q <= VIDEO_X2_MODE;
else if (write_en_w && (wr_addr_w[7:0] == `CONFIG))
config_x2_mode_q <= cfg_wdata_i[`CONFIG_X2_MODE_R];
wire config_x2_mode_out_w = config_x2_mode_q;
// config_int_en_sof [internal]
reg config_int_en_sof_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
config_int_en_sof_q <= 1'd`CONFIG_INT_EN_SOF_DEFAULT;
else if (write_en_w && (wr_addr_w[7:0] == `CONFIG))
config_int_en_sof_q <= cfg_wdata_i[`CONFIG_INT_EN_SOF_R];
wire config_int_en_sof_out_w = config_int_en_sof_q;
// config_enable [internal]
reg config_enable_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
config_enable_q <= VIDEO_ENABLE;
else if (write_en_w && (wr_addr_w[7:0] == `CONFIG))
config_enable_q <= cfg_wdata_i[`CONFIG_ENABLE_R];
wire config_enable_out_w = config_enable_q;
//-----------------------------------------------------------------
// Register status
//-----------------------------------------------------------------
reg status_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
status_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `STATUS))
status_wr_q <= 1'b1;
else
status_wr_q <= 1'b0;
// status_y_pos [external]
wire [15:0] status_y_pos_out_w = wr_data_q[`STATUS_Y_POS_R];
// status_h_pos [external]
wire [15:0] status_h_pos_out_w = wr_data_q[`STATUS_H_POS_R];
//-----------------------------------------------------------------
// Register frame_buffer
//-----------------------------------------------------------------
reg frame_buffer_wr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_buffer_wr_q <= 1'b0;
else if (write_en_w && (wr_addr_w[7:0] == `FRAME_BUFFER))
frame_buffer_wr_q <= 1'b1;
else
frame_buffer_wr_q <= 1'b0;
// frame_buffer_addr [internal]
reg [23:0] frame_buffer_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_buffer_addr_q <= (VIDEO_FB_RAM / 256);
else if (write_en_w && (wr_addr_w[7:0] == `FRAME_BUFFER))
frame_buffer_addr_q <= cfg_wdata_i[`FRAME_BUFFER_ADDR_R];
wire [23:0] frame_buffer_addr_out_w = frame_buffer_addr_q;
wire [15:0] status_y_pos_in_w;
wire [15:0] status_h_pos_in_w;
//-----------------------------------------------------------------
// Read mux
//-----------------------------------------------------------------
reg [31:0] data_r;
always @ *
begin
data_r = 32'b0;
case (cfg_araddr_i[7:0])
`CONFIG:
begin
data_r[`CONFIG_X2_MODE_R] = config_x2_mode_q;
data_r[`CONFIG_INT_EN_SOF_R] = config_int_en_sof_q;
data_r[`CONFIG_ENABLE_R] = config_enable_q;
end
`STATUS:
begin
data_r[`STATUS_Y_POS_R] = status_y_pos_in_w;
data_r[`STATUS_H_POS_R] = status_h_pos_in_w;
end
`FRAME_BUFFER:
begin
data_r[`FRAME_BUFFER_ADDR_R] = frame_buffer_addr_q;
end
default :
data_r = 32'b0;
endcase
end
//-----------------------------------------------------------------
// RVALID
//-----------------------------------------------------------------
reg rvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rvalid_q <= 1'b0;
else if (read_en_w)
rvalid_q <= 1'b1;
else if (cfg_rready_i)
rvalid_q <= 1'b0;
assign cfg_rvalid_o = rvalid_q;
//-----------------------------------------------------------------
// Retime read response
//-----------------------------------------------------------------
reg [31:0] rd_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rd_data_q <= 32'b0;
else if (!cfg_rvalid_o || cfg_rready_i)
rd_data_q <= data_r;
assign cfg_rdata_o = rd_data_q;
assign cfg_rresp_o = 2'b0;
//-----------------------------------------------------------------
// BVALID
//-----------------------------------------------------------------
reg bvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
bvalid_q <= 1'b0;
else if (write_en_w)
bvalid_q <= 1'b1;
else if (cfg_bready_i)
bvalid_q <= 1'b0;
assign cfg_bvalid_o = bvalid_q;
assign cfg_bresp_o = 2'b0;
wire status_wr_req_w = status_wr_q;
//-----------------------------------------------------------------
// Video Timings
//-----------------------------------------------------------------
localparam H_REZ = VIDEO_WIDTH;
localparam V_REZ = VIDEO_HEIGHT;
localparam CLK_MHZ = (VIDEO_WIDTH == 640 && VIDEO_REFRESH == 60) ? 25.175 :
(VIDEO_WIDTH == 640 && VIDEO_REFRESH == 85) ? 36 :
(VIDEO_WIDTH == 800 && VIDEO_REFRESH == 72) ? 50.00 :
(VIDEO_WIDTH == 1280 && VIDEO_REFRESH == 60) ? 74.25 :
(VIDEO_WIDTH == 1920 && VIDEO_REFRESH == 60) ? 148.5 :
0;
localparam H_SYNC_START = (VIDEO_WIDTH == 640 && VIDEO_REFRESH == 60) ? 656 :
(VIDEO_WIDTH == 640 && VIDEO_REFRESH == 85) ? 672 :
(VIDEO_WIDTH == 800 && VIDEO_REFRESH == 72) ? 856 :
(VIDEO_WIDTH == 1280 && VIDEO_REFRESH == 60) ? 1390:
(VIDEO_WIDTH == 1920 && VIDEO_REFRESH == 60) ? 2008:
0;
localparam H_SYNC_END = (VIDEO_WIDTH == 640 && VIDEO_REFRESH == 60) ? 752 :
(VIDEO_WIDTH == 640 && VIDEO_REFRESH == 85) ? 720 :
(VIDEO_WIDTH == 800 && VIDEO_REFRESH == 72) ? 976 :
(VIDEO_WIDTH == 1280 && VIDEO_REFRESH == 60) ? 1430:
(VIDEO_WIDTH == 1920 && VIDEO_REFRESH == 60) ? 2052:
0;
localparam H_MAX = (VIDEO_WIDTH == 640 && VIDEO_REFRESH == 60) ? 800 :
(VIDEO_WIDTH == 640 && VIDEO_REFRESH == 85) ? 832 :
(VIDEO_WIDTH == 800 && VIDEO_REFRESH == 72) ? 1040:
(VIDEO_WIDTH == 1280 && VIDEO_REFRESH == 60) ? 1650:
(VIDEO_WIDTH == 1920 && VIDEO_REFRESH == 60) ? 2200:
0;
localparam V_SYNC_START = (VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 60) ? 490 :
(VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 85) ? 490 :
(VIDEO_HEIGHT == 600 && VIDEO_REFRESH == 72) ? 637 :
(VIDEO_HEIGHT == 720 && VIDEO_REFRESH == 60) ? 725 :
(VIDEO_HEIGHT == 1080 && VIDEO_REFRESH == 60)? 1084 :
0;
localparam V_SYNC_END = (VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 60) ? 492 :
(VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 85) ? 492 :
(VIDEO_HEIGHT == 600 && VIDEO_REFRESH == 72) ? 643 :
(VIDEO_HEIGHT == 720 && VIDEO_REFRESH == 60) ? 730 :
(VIDEO_HEIGHT == 1080 && VIDEO_REFRESH == 60)? 1089:
0;
localparam V_MAX = (VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 60) ? 525 :
(VIDEO_HEIGHT == 480 && VIDEO_REFRESH == 85) ? 525 :
(VIDEO_HEIGHT == 600 && VIDEO_REFRESH == 72) ? 666 :
(VIDEO_HEIGHT == 720 && VIDEO_REFRESH == 60) ? 750 :
(VIDEO_HEIGHT == 1080 && VIDEO_REFRESH == 60)? 1125:
0;
localparam VIDEO_SIZE = (H_REZ * V_REZ) * 2; // RG565
localparam BUFFER_SIZE = 1024;
localparam BURST_LEN = 32;
//-----------------------------------------------------------------
// HSYNC, VSYNC
//-----------------------------------------------------------------
reg [11:0] h_pos_q;
reg [11:0] v_pos_q;
reg h_sync_q;
reg v_sync_q;
reg active_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
h_pos_q <= 12'b0;
else if (h_pos_q == H_MAX)
h_pos_q <= 12'b0;
else
h_pos_q <= h_pos_q + 12'd1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
v_pos_q <= 12'b0;
else if (h_pos_q == H_MAX)
begin
if (v_pos_q == V_MAX)
v_pos_q <= 12'b0;
else
v_pos_q <= v_pos_q + 12'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
h_sync_q <= 1'b0;
else if (h_pos_q >= H_SYNC_START && h_pos_q < H_SYNC_END)
h_sync_q <= 1'b1;
else
h_sync_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
v_sync_q <= 1'b0;
else if (v_pos_q >= V_SYNC_START && v_pos_q < V_SYNC_END)
v_sync_q <= 1'b1;
else
v_sync_q <= 1'b0;
wire blanking_w = (h_pos_q < H_REZ && v_pos_q < V_REZ) ? 1'b0 : 1'b1;
assign status_h_pos_in_w = {4'b0, h_pos_q};
assign status_y_pos_in_w = {4'b0, v_pos_q};
//-----------------------------------------------------------------
// Pixel fetch FIFO
//-----------------------------------------------------------------
wire pixel_valid_w;
wire [31:0] pixel_data_w;
wire pixel_accept_w;
wire pixel_pop_w = pixel_accept_w || ~active_q;
dvi_framebuffer_fifo
u_fifo
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(outport_rvalid_i)
,.data_in_i(outport_rdata_i)
,.accept_o()
,.valid_o(pixel_valid_w)
,.data_out_o(pixel_data_w)
,.pop_i(pixel_pop_w)
);
//-----------------------------------------------------------------
// Enable
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
active_q <= 1'b0;
else if (pixel_accept_w && !pixel_valid_w)
active_q <= 1'b0; // Underrun - abort until next frame
else if (h_pos_q == H_REZ && v_pos_q == V_REZ)
active_q <= config_enable_out_w;
else if (!config_enable_out_w)
active_q <= 1'b0;
//-----------------------------------------------------------------
// FIFO allocation
//-----------------------------------------------------------------
reg [15:0] allocated_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
allocated_q <= 16'b0;
else if (outport_arvalid_o && outport_arready_i)
begin
if (pixel_valid_w && pixel_pop_w)
allocated_q <= allocated_q + {6'b0, outport_arlen_o, 2'b0};
else
allocated_q <= allocated_q + {6'b0, (outport_arlen_o + 8'd1), 2'b0};
end
else if (pixel_valid_w && pixel_pop_w)
allocated_q <= allocated_q - 16'd4;
//-----------------------------------------------------------------
// AXI Request
//-----------------------------------------------------------------
wire fifo_space_w = (allocated_q <= (BUFFER_SIZE - BURST_LEN));
wire [31:0] frame_addr_w = {frame_buffer_addr_out_w, 8'b0};
reg arvalid_q;
reg [31:0] araddr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
arvalid_q <= 1'b0;
else if (outport_arvalid_o && outport_arready_i)
arvalid_q <= 1'b0;
else if (!outport_arvalid_o && fifo_space_w && active_q)
arvalid_q <= 1'b1;
assign outport_arvalid_o = arvalid_q;
// Calculate number of bytes being fetch (burst length x interface width)
wire [31:0] fetch_bytes_w = {22'b0, (outport_arlen_o + 8'd1), 2'b0};
reg [11:0] fetch_h_pos_q;
reg [11:0] fetch_v_pos_q;
localparam H_LINE_LEN_X2 = ((H_REZ / 2) - (BURST_LEN / 2));
localparam H_LINE_LEN_X2_BYTES = H_LINE_LEN_X2 * 2;
localparam H_FETCHES_LINE = ((H_REZ * 2) / BURST_LEN);
localparam H_FETCHES_LINE_X2 = ((H_REZ * 2) / BURST_LEN) / 2;
wire last_fetch_w = config_x2_mode_out_w ? ((fetch_h_pos_q == (H_FETCHES_LINE_X2 - 1)) && (fetch_v_pos_q == (V_REZ - 1))) :
((fetch_h_pos_q == (H_FETCHES_LINE - 1)) && (fetch_v_pos_q == (V_REZ - 1)));
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
fetch_h_pos_q <= 12'b0;
else if (outport_arvalid_o && outport_arready_i)
begin
if (config_x2_mode_out_w && fetch_h_pos_q == (H_FETCHES_LINE_X2 - 1))
fetch_h_pos_q <= 12'b0;
else if (!config_x2_mode_out_w && fetch_h_pos_q == (H_FETCHES_LINE - 1))
fetch_h_pos_q <= 12'b0;
else
fetch_h_pos_q <= fetch_h_pos_q + 12'd1;
end
else if (!active_q)
fetch_h_pos_q <= 12'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
fetch_v_pos_q <= 12'b0;
else if (outport_arvalid_o && outport_arready_i)
begin
if ((config_x2_mode_out_w && fetch_h_pos_q == (H_FETCHES_LINE_X2 - 1)) ||
(!config_x2_mode_out_w && fetch_h_pos_q == (H_FETCHES_LINE - 1)))
begin
if (fetch_v_pos_q == (V_REZ - 1))
fetch_v_pos_q <= 12'b0;
else
fetch_v_pos_q <= fetch_v_pos_q + 12'd1;
end
end
else if (!active_q)
fetch_v_pos_q <= 12'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
araddr_q <= 32'b0;
else if (outport_arvalid_o && outport_arready_i)
begin
if (last_fetch_w)
araddr_q <= frame_addr_w;
else if (config_x2_mode_out_w && !fetch_v_pos_q[0] && fetch_h_pos_q == (H_FETCHES_LINE_X2 - 1))
araddr_q <= araddr_q - H_LINE_LEN_X2_BYTES;
else
araddr_q <= araddr_q + fetch_bytes_w;
end
else if (!active_q)
araddr_q <= frame_addr_w;
assign outport_araddr_o = araddr_q;
assign outport_arburst_o = 2'b01;
assign outport_arid_o = 4'd0;
assign outport_arlen_o = (BURST_LEN / 4) - 1;
assign outport_rready_o = 1'b1;
// Unused
assign outport_awvalid_o = 1'b0;
assign outport_awaddr_o = 32'b0;
assign outport_awid_o = 4'b0;
assign outport_awlen_o = 8'b0;
assign outport_awburst_o = 2'b0;
assign outport_wvalid_o = 1'b0;
assign outport_wdata_o = 32'b0;
assign outport_wstrb_o = 4'b0;
assign outport_wlast_o = 1'b0;
assign outport_bready_o = 1'b0;
//-----------------------------------------------------------------
// RGB expansion
//-----------------------------------------------------------------
reg word_sel_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
word_sel_q <= 1'b0;
else if (!blanking_w && (h_pos_q[0] || !config_x2_mode_out_w))
word_sel_q <= ~word_sel_q;
else if (!active_q)
word_sel_q <= 1'b0;
wire [7:0] blue_w = (config_enable_out_w == 1'b0) ? 8'b0 :
word_sel_q ? {pixel_data_w[4+16:0+16], 3'b0} :
{pixel_data_w[4:0], 3'b0};
wire [7:0] green_w = (config_enable_out_w == 1'b0) ? 8'b0 :
word_sel_q ? {pixel_data_w[10+16:5+16], 2'b0} :
{pixel_data_w[10:5], 2'b0};
wire [7:0] red_w = (config_enable_out_w == 1'b0) ? 8'b0 :
word_sel_q ? {pixel_data_w[15+16:11+16], 3'b0} :
{pixel_data_w[15:11], 3'b0};
assign pixel_accept_w = ~blanking_w & word_sel_q & (h_pos_q[0] || !config_x2_mode_out_w) & active_q;
//-----------------------------------------------------------------
// DVI output
//-----------------------------------------------------------------
dvi u_dvi
(
.clk_i(clk_i),
.rst_i(rst_i),
.clk_x5_i(clk_x5_i),
.vga_red_i(red_w),
.vga_green_i(green_w),
.vga_blue_i(blue_w),
.vga_blank_i(blanking_w),
.vga_hsync_i(h_sync_q),
.vga_vsync_i(v_sync_q),
.dvi_red_o(dvi_red_o),
.dvi_green_o(dvi_green_o),
.dvi_blue_o(dvi_blue_o),
.dvi_clock_o(dvi_clock_o)
);
//-----------------------------------------------------------------
// Interrupt output
//-----------------------------------------------------------------
reg intr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
intr_q <= 1'b0;
else if (config_int_en_sof_out_w && fetch_h_pos_q == 12'b0 && fetch_v_pos_q == 12'b0)
intr_q <= 1'b1;
else
intr_q <= 1'b0;
assign intr_o = intr_q;
endmodule |
module dvi_tmds_encoder
(
input clk
, input reset
, input [7:0] data
, input [1:0] c
, input blank
, output [9:0] encoded
);
/* verilator lint_off WIDTH */
/* verilator lint_off UNOPTFLAT */
reg [9:0] encoded_q;
wire [8:0] xored;
wire [8:0] xnored;
wire [3:0] ones;
reg [8:0] data_word_r;
reg [8:0] data_word_inv_r;
wire [3:0] data_word_disparity;
reg [3:0] dc_bias_q;
// Work our the two different encodings for the byte
assign xored[0] = data[0];
assign xored[1] = data[1] ^ xored[0];
assign xored[2] = data[2] ^ xored[1];
assign xored[3] = data[3] ^ xored[2];
assign xored[4] = data[4] ^ xored[3];
assign xored[5] = data[5] ^ xored[4];
assign xored[6] = data[6] ^ xored[5];
assign xored[7] = data[7] ^ xored[6];
assign xored[8] = 1'b1;
assign xnored[0] = data[0];
assign xnored[1] = ~(data[1] ^ xnored[0]);
assign xnored[2] = ~(data[2] ^ xnored[1]);
assign xnored[3] = ~(data[3] ^ xnored[2]);
assign xnored[4] = ~(data[4] ^ xnored[3]);
assign xnored[5] = ~(data[5] ^ xnored[4]);
assign xnored[6] = ~(data[6] ^ xnored[5]);
assign xnored[7] = ~(data[7] ^ xnored[6]);
assign xnored[8] = 1'b0;
// Count how many ones are set in data
assign ones = data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];
// Decide which encoding to use
always @ *
begin
if(ones > 4 || (ones == 4 && data[0] == 1'b0))
begin
data_word_r = xnored;
data_word_inv_r = ~((xnored));
end
else
begin
data_word_r = xored;
data_word_inv_r = ~((xored));
end
end
// Work out the DC bias of the dataword
assign data_word_disparity = 4'b1100 + data_word_r[0] + data_word_r[1] + data_word_r[2] + data_word_r[3] + data_word_r[4] + data_word_r[5] + data_word_r[6] + data_word_r[7];
// Now work out what the output should be
always @(posedge clk or posedge reset)
if (reset)
begin
encoded_q <= 10'b0;
dc_bias_q <= 4'b0;
end
else if (blank == 1'b1)
begin
// In the control periods, all values have and have balanced bit count
case(c)
2'b00 : encoded_q <= 10'b1101010100;
2'b01 : encoded_q <= 10'b0010101011;
2'b10 : encoded_q <= 10'b0101010100;
default : encoded_q <= 10'b1010101011;
endcase
dc_bias_q <= 4'b0;
end
else
begin
if (dc_bias_q == 4'b00000 || data_word_disparity == 0)
begin
// dataword has no disparity
if(data_word_r[8] == 1'b1)
begin
encoded_q <= {2'b 01,data_word_r[7:0]};
dc_bias_q <= dc_bias_q + data_word_disparity;
end
else
begin
encoded_q <= {2'b 10,data_word_inv_r[7:0]};
dc_bias_q <= dc_bias_q - data_word_disparity;
end
end
else if((dc_bias_q[3] == 1'b0 && data_word_disparity[3] == 1'b0) || (dc_bias_q[3] == 1'b1 && data_word_disparity[3] == 1'b1))
begin
encoded_q <= {1'b1,data_word_r[8],data_word_inv_r[7:0]};
dc_bias_q <= dc_bias_q + data_word_r[8] - data_word_disparity;
end
else
begin
encoded_q <= {1'b0,data_word_r};
dc_bias_q <= dc_bias_q - data_word_inv_r[8] + data_word_disparity;
end
end
assign encoded = encoded_q;
/* verilator lint_on UNOPTFLAT */
/* verilator lint_on WIDTH */
endmodule |
module dvi_serialiser
(
input clk_i
, input rst_i
, input strobe_i
, input [9:0] data_i
, output serial_o
);
`ifndef verilator
ODDR
#(
.DDR_CLK_EDGE("SAME_EDGE")
,.INIT(1'b0)
,.SRTYPE("ASYNC")
)
u_ddr_r
(
.C(clk_i)
,.CE(1'b1)
,.D1(data_i[0])
,.D2(data_i[1])
,.Q(serial_o)
,.R(1'b0)
,.S(1'b0)
);
`else
// Hack - non-functional sim
assign serial_o = clk_i ? data_i[0] : data_i[1];
`endif
endmodule |
module trng_csprng(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input test_mode,
output wire more_seed,
output wire security_error,
input [511 : 0] seed_data,
input wire seed_syn,
output wire seed_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_CTRL = 8'h10;
parameter CTRL_ENABLE_BIT = 0;
parameter CTRL_SEED_BIT = 1;
parameter ADDR_STATUS = 8'h11;
parameter STATUS_RND_VALID_BIT = 0;
parameter ADDR_RND_DATA = 8'h20;
parameter ADDR_NUM_ROUNDS = 8'h40;
parameter ADDR_NUM_BLOCKS_LOW = 8'h41;
parameter ADDR_NUM_BLOCKS_HIGH = 8'h42;
parameter CIPHER_KEYLEN256 = 1'b1; // 256 bit key.
parameter CIPHER_MAX_BLOCKS = 64'h1000000000000000;
parameter CTRL_IDLE = 4'h0;
parameter CTRL_SEED0 = 4'h1;
parameter CTRL_NSYN = 4'h2;
parameter CTRL_SEED1 = 4'h3;
parameter CTRL_INIT0 = 4'h4;
parameter CTRL_INIT1 = 4'h5;
parameter CTRL_NEXT0 = 4'h6;
parameter CTRL_NEXT1 = 4'h7;
parameter CTRL_MORE = 4'h8;
parameter CTRL_CANCEL = 4'hf;
parameter DEFAULT_NUM_ROUNDS = 5'h18;
parameter DEFAULT_NUM_BLOCKS = 64'h1000000000000000;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [255 : 0] cipher_key_reg;
reg [255 : 0] cipher_key_new;
reg cipher_key_we;
reg [63 : 0] cipher_iv_reg;
reg [63 : 0] cipher_iv_new;
reg cipher_iv_we;
reg [63 : 0] cipher_ctr_reg;
reg [63 : 0] cipher_ctr_new;
reg cipher_ctr_we;
reg [511 : 0] cipher_block_reg;
reg [511 : 0] cipher_block_new;
reg cipher_block_we;
reg [63 : 0] block_ctr_reg;
reg [63 : 0] block_ctr_new;
reg block_ctr_inc;
reg block_ctr_rst;
reg block_ctr_we;
reg block_ctr_max;
reg ready_reg;
reg ready_new;
reg ready_we;
reg more_seed_reg;
reg more_seed_new;
reg seed_ack_reg;
reg seed_ack_new;
reg enable_reg;
reg enable_new;
reg enable_we;
reg seed_reg;
reg seed_new;
reg [4 : 0] num_rounds_reg;
reg [4 : 0] num_rounds_new;
reg num_rounds_we;
reg [31 : 0] num_blocks_low_reg;
reg [31 : 0] num_blocks_low_new;
reg num_blocks_low_we;
reg [31 : 0] num_blocks_high_reg;
reg [31 : 0] num_blocks_high_new;
reg num_blocks_high_we;
reg [3 : 0] csprng_ctrl_reg;
reg [3 : 0] csprng_ctrl_new;
reg csprng_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg tmp_error;
reg cipher_init;
reg cipher_next;
wire [511 : 0] cipher_data_out;
wire cipher_data_out_valid;
wire cipher_ready;
wire fifo_more_data;
reg fifo_discard;
wire rnd_syn;
wire [31 : 0] rnd_data;
reg rnd_ack;
reg fifo_cipher_data_valid;
wire [63 : 0] num_blocks;
wire muxed_rnd_ack;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign seed_ack = seed_ack_reg;
assign more_seed = more_seed_reg;
assign debug = rnd_data[7 : 0];
assign security_error = 0;
assign num_blocks = {num_blocks_high_reg, num_blocks_low_reg};
assign muxed_rnd_ack = rnd_ack | debug_update;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
chacha_core cipher_inst(
.clk(clk),
.reset_n(reset_n),
.init(cipher_init),
.next(cipher_next),
.key(cipher_key_reg),
.keylen(CIPHER_KEYLEN256),
.iv(cipher_iv_reg),
.ctr(cipher_ctr_reg),
.rounds(num_rounds_reg),
.data_in(cipher_block_reg),
.ready(cipher_ready),
.data_out(cipher_data_out),
.data_out_valid(cipher_data_out_valid)
);
trng_csprng_fifo fifo_inst(
.clk(clk),
.reset_n(reset_n),
.csprng_data(cipher_data_out),
.csprng_data_valid(fifo_cipher_data_valid),
.discard(fifo_discard),
.more_data(fifo_more_data),
.rnd_syn(rnd_syn),
.rnd_data(rnd_data),
.rnd_ack(muxed_rnd_ack)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
cipher_key_reg <= {8{32'h00000000}};
cipher_iv_reg <= {2{32'h00000000}};
cipher_ctr_reg <= {2{32'h00000000}};
cipher_block_reg <= {16{32'h00000000}};
block_ctr_reg <= {2{32'h00000000}};
more_seed_reg <= 0;
seed_ack_reg <= 0;
ready_reg <= 0;
enable_reg <= 1;
seed_reg <= 0;
num_rounds_reg <= DEFAULT_NUM_ROUNDS;
num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0];
num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32];
csprng_ctrl_reg <= CTRL_IDLE;
end
else
begin
more_seed_reg <= more_seed_new;
seed_ack_reg <= seed_ack_new;
seed_reg <= seed_new;
if (enable_we)
begin
enable_reg <= enable_new;
end
if (cipher_key_we)
begin
cipher_key_reg <= cipher_key_new;
end
if (cipher_iv_we)
begin
cipher_iv_reg <= cipher_iv_new;
end
if (cipher_ctr_we)
begin
cipher_ctr_reg <= cipher_ctr_new;
end
if (cipher_block_we)
begin
cipher_block_reg <= cipher_block_new;
end
if (block_ctr_we)
begin
block_ctr_reg <= block_ctr_new;
end
if (ready_we)
begin
ready_reg <= ready_new;
end
if (csprng_ctrl_we)
begin
csprng_ctrl_reg <= csprng_ctrl_new;
end
if (num_rounds_we)
begin
num_rounds_reg <= num_rounds_new;
end
if (num_blocks_low_we)
begin
num_blocks_low_reg <= num_blocks_low_new;
end
if (num_blocks_high_we)
begin
num_blocks_high_reg <= num_blocks_high_new;
end
end
end // reg_update
//----------------------------------------------------------------
// csprng_api_logic
//----------------------------------------------------------------
always @*
begin : csprng_api_logic
enable_new = 0;
enable_we = 0;
seed_new = 0;
num_rounds_new = 5'h00;
num_rounds_we = 0;
num_blocks_low_new = 32'h00000000;
num_blocks_low_we = 0;
num_blocks_high_new = 32'h00000000;
num_blocks_high_we = 0;
rnd_ack = 0;
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
// Write operations.
case (address)
// Write operations.
ADDR_CTRL:
begin
enable_new = write_data[CTRL_ENABLE_BIT];
enable_we = 1;
seed_new = write_data[CTRL_SEED_BIT];
end
ADDR_NUM_ROUNDS:
begin
num_rounds_new = write_data[4 : 0];
num_rounds_we = 1;
end
ADDR_NUM_BLOCKS_LOW:
begin
num_blocks_low_new = write_data;
num_blocks_low_we = 1;
end
ADDR_NUM_BLOCKS_HIGH:
begin
num_blocks_high_new = write_data;
num_blocks_high_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
// Read operations.
case (address)
// Read operations.
ADDR_CTRL:
begin
tmp_read_data = {30'h00000000, seed_reg, enable_reg};
end
ADDR_STATUS:
begin
tmp_read_data = {30'h00000000, ready_reg, rnd_syn};
end
ADDR_RND_DATA:
begin
tmp_read_data = rnd_data;
rnd_ack = 1;
end
ADDR_NUM_ROUNDS:
begin
tmp_read_data = {27'h0000000, num_rounds_reg};
end
ADDR_NUM_BLOCKS_LOW:
begin
tmp_read_data = num_blocks_low_reg;
end
ADDR_NUM_BLOCKS_HIGH:
begin
tmp_read_data = num_blocks_high_reg;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // cspng_api_logic
//----------------------------------------------------------------
// block_ctr
//
// Logic to implement the block counter. This includes the
// ability to detect that maximum allowed number of blocks
// has been reached. Either as defined by the application
// or the hard coded CIPHER_MAX_BLOCKS value.
//----------------------------------------------------------------
always @*
begin : block_ctr
block_ctr_new = 64'h0000000000000000;
block_ctr_we = 0;
block_ctr_max = 0;
if (block_ctr_rst)
begin
block_ctr_new = 64'h0000000000000000;
block_ctr_we = 1;
end
if (block_ctr_inc)
begin
block_ctr_new = block_ctr_reg + 1'b1;
block_ctr_we = 1;
end
if ((block_ctr_reg == num_blocks) || (block_ctr_reg == CIPHER_MAX_BLOCKS))
begin
block_ctr_max = 1;
end
end // block_ctr
//----------------------------------------------------------------
// csprng_ctrl_fsm
//
// Control FSM for the CSPRNG.
//----------------------------------------------------------------
always @*
begin : csprng_ctrl_fsm
cipher_key_new = {8{32'h00000000}};
cipher_key_we = 0;
cipher_iv_new = {2{32'h00000000}};
cipher_iv_we = 0;
cipher_ctr_new = {2{32'h00000000}};
cipher_ctr_we = 0;
cipher_block_new = {16{32'h00000000}};
cipher_block_we = 0;
cipher_init = 0;
cipher_next = 0;
block_ctr_rst = 0;
block_ctr_inc = 0;
ready_new = 0;
ready_we = 0;
seed_ack_new = 0;
more_seed_new = 0;
fifo_discard = 0;
fifo_cipher_data_valid = 0;
csprng_ctrl_new = CTRL_IDLE;
csprng_ctrl_we = 0;
case (csprng_ctrl_reg)
CTRL_IDLE:
begin
if (!enable_reg)
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (fifo_more_data)
begin
more_seed_new = 1;
csprng_ctrl_new = CTRL_SEED0;
csprng_ctrl_we = 1;
end
end
CTRL_SEED0:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (seed_syn)
begin
seed_ack_new = 1;
cipher_block_new = seed_data;
cipher_block_we = 1;
csprng_ctrl_new = CTRL_NSYN;
csprng_ctrl_we = 1;
end
end
CTRL_NSYN:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else
begin
more_seed_new = 1;
csprng_ctrl_new = CTRL_SEED1;
csprng_ctrl_we = 1;
end
end
CTRL_SEED1:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (seed_syn)
begin
seed_ack_new = 1;
cipher_key_new = seed_data[255 : 0];
cipher_key_we = 1;
cipher_iv_new = seed_data[319 : 256];
cipher_iv_we = 1;
cipher_ctr_new = seed_data[383 : 320];
cipher_ctr_we = 1;
csprng_ctrl_new = CTRL_INIT0;
csprng_ctrl_we = 1;
end
else
begin
more_seed_new = 1;
end
end
CTRL_INIT0:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else
begin
cipher_init = 1;
block_ctr_rst = 1;
csprng_ctrl_new = CTRL_INIT1;
csprng_ctrl_we = 1;
end
end
CTRL_INIT1:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (cipher_ready)
begin
csprng_ctrl_new = CTRL_NEXT0;
csprng_ctrl_we = 1;
end
end
CTRL_NEXT0:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else
begin
cipher_next = 1;
csprng_ctrl_new = CTRL_NEXT1;
csprng_ctrl_we = 1;
end
end
CTRL_NEXT1:
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (cipher_ready)
begin
block_ctr_inc = 1;
fifo_cipher_data_valid = 1;
csprng_ctrl_new = CTRL_MORE;
csprng_ctrl_we = 1;
end
CTRL_MORE:
begin
if ((!enable_reg) || (seed_reg))
begin
csprng_ctrl_new = CTRL_CANCEL;
csprng_ctrl_we = 1;
end
else if (fifo_more_data)
begin
if (block_ctr_max)
begin
more_seed_new = 1;
csprng_ctrl_new = CTRL_SEED0;
csprng_ctrl_we = 1;
end
else
begin
csprng_ctrl_new = CTRL_NEXT0;
csprng_ctrl_we = 1;
end
end
end
CTRL_CANCEL:
begin
fifo_discard = 1;
cipher_key_new = {8{32'h00000000}};
cipher_key_we = 1;
cipher_iv_new = {2{32'h00000000}};
cipher_iv_we = 1;
cipher_ctr_new = {2{32'h00000000}};
cipher_ctr_we = 1;
cipher_block_new = {16{32'h00000000}};
cipher_block_we = 1;
block_ctr_rst = 1;
csprng_ctrl_new = CTRL_IDLE;
csprng_ctrl_we = 1;
end
endcase // case (cspng_ctrl_reg)
end // csprng_ctrl_fsm
endmodule // trng_csprng |
module trng(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire avalanche_noise,
input wire cs,
input wire we,
input wire [11 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
output wire [7 : 0] debug,
input wire debug_update,
output wire security_error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter TRNG_PREFIX = 4'h0;
parameter ENTROPY1_PREFIX = 4'h5;
parameter ENTROPY2_PREFIX = 4'h6;
parameter MIXER_PREFIX = 4'ha;
parameter CSPRNG_PREFIX = 4'hb;
parameter DEBUG_ENTROPY0 = 3'h0;
parameter DEBUG_ENTROPY1 = 3'h1;
parameter DEBUG_ENTROPY2 = 3'h2;
parameter DEBUG_MIXER = 3'h3;
parameter DEBUG_CSPRNG = 3'h4;
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_TRNG_CTRL = 8'h10;
parameter TRNG_CTRL_DISCARD_BIT = 0;
parameter TRNG_CTRL_TEST_MODE_BIT = 1;
parameter ADDR_TRNG_STATUS = 8'h11;
parameter ADDR_DEBUG_CTRL = 8'h12;
parameter ADDR_DEBUG_DELAY = 8'h13;
parameter TRNG_NAME0 = 32'h74726e67; // "trng"
parameter TRNG_NAME1 = 32'h20202020; // " "
parameter TRNG_VERSION = 32'h302e3031; // "0.01"
// 20x/s @ 50 MHz.
parameter DEFAULT_DEBUG_DELAY = 32'h002625a0;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg discard_reg;
reg discard_new;
reg test_mode_reg;
reg test_mode_new;
reg test_mode_we;
reg [7 : 0] debug_out_reg;
reg debug_out_we;
reg [2 : 0] debug_mux_reg;
reg [2 : 0] debug_mux_new;
reg debug_mux_we;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [31 : 0] debug_delay_reg;
reg [31 : 0] debug_delay_new;
reg debug_delay_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg trng_api_cs;
reg trng_api_we;
reg [31 : 0] trng_api_read_data;
reg trng_api_error;
wire mixer_more_seed;
wire [511 : 0] mixer_seed_data;
wire mixer_seed_syn;
wire mixer_seed_ack;
reg mixer_api_cs;
reg mixer_api_we;
wire [31 : 0] mixer_api_read_data;
wire mixer_api_error;
wire mixer_security_error;
wire [7 : 0] mixer_debug;
reg mixer_debug_update;
wire csprng_more_seed;
wire csprng_seed_ack;
reg csprng_api_cs;
reg csprng_api_we;
wire [31 : 0] csprng_api_read_data;
wire csprng_api_error;
wire [7 : 0] csprng_debug;
reg csprng_debug_update;
wire csprng_security_error;
wire entropy0_entropy_enabled;
wire [31 : 0] entropy0_entropy_data;
wire entropy0_entropy_syn;
wire entropy0_entropy_ack;
reg entropy1_api_cs;
reg entropy1_api_we;
wire [31 : 0] entropy1_api_read_data;
wire entropy1_api_error;
wire entropy1_entropy_enabled;
wire [31 : 0] entropy1_entropy_data;
wire entropy1_entropy_syn;
wire entropy1_entropy_ack;
wire entropy1_test_mode;
wire [7 : 0] entropy1_debug;
reg entropy1_debug_update;
wire entropy1_security_error;
reg entropy2_api_cs;
reg entropy2_api_we;
wire [31 : 0] entropy2_api_read_data;
wire entropy2_api_error;
wire entropy2_entropy_enabled;
wire [31 : 0] entropy2_entropy_data;
wire entropy2_entropy_syn;
wire entropy2_entropy_ack;
wire entropy2_test_mode;
wire [7 : 0] entropy2_debug;
reg entropy2_debug_update;
wire entropy2_security_error;
reg [7 : 0] api_address;
reg [31 : 0] tmp_read_data;
reg tmp_error;
reg [7 : 0] tmp_debug;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign security_error = entropy1_security_error | entropy2_security_error;
assign debug = debug_out_reg;
// Patches to get our first version to work.
assign entropy0_entropy_enabled = 0;
assign entropy0_entropy_syn = 0;
assign entropy0_entropy_data = 32'h00000000;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
trng_mixer mixer_inst(
.clk(clk),
.reset_n(reset_n),
.cs(mixer_api_cs),
.we(mixer_api_we),
.address(api_address),
.write_data(write_data),
.read_data(mixer_api_read_data),
.error(mixer_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(mixer_security_error),
.more_seed(csprng_more_seed),
.entropy0_enabled(entropy0_entropy_enabled),
.entropy0_syn(entropy0_entropy_syn),
.entropy0_data(entropy0_entropy_data),
.entropy0_ack(entropy0_entropy_ack),
.entropy1_enabled(entropy1_entropy_enabled),
.entropy1_syn(entropy1_entropy_syn),
.entropy1_data(entropy1_entropy_data),
.entropy1_ack(entropy1_entropy_ack),
.entropy2_enabled(entropy2_entropy_enabled),
.entropy2_syn(entropy2_entropy_syn),
.entropy2_data(entropy2_entropy_data),
.entropy2_ack(entropy2_entropy_ack),
.seed_data(mixer_seed_data),
.seed_syn(mixer_seed_syn),
.seed_ack(csprng_seed_ack),
.debug(mixer_debug),
.debug_update(mixer_debug_update)
);
trng_csprng csprng_inst(
.clk(clk),
.reset_n(reset_n),
.cs(csprng_api_cs),
.we(csprng_api_we),
.address(api_address),
.write_data(write_data),
.read_data(csprng_api_read_data),
.error(csprng_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(csprng_security_error),
.more_seed(csprng_more_seed),
.seed_data(mixer_seed_data),
.seed_syn(mixer_seed_syn),
.seed_ack(csprng_seed_ack),
.debug(csprng_debug),
.debug_update(csprng_debug_update)
);
avalanche_entropy entropy1(
.clk(clk),
.reset_n(reset_n),
.noise(avalanche_noise),
.cs(entropy1_api_cs),
.we(entropy1_api_we),
.address(api_address),
.write_data(write_data),
.read_data(entropy1_api_read_data),
.error(entropy1_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(entropy1_security_error),
.entropy_enabled(entropy1_entropy_enabled),
.entropy_data(entropy1_entropy_data),
.entropy_valid(entropy1_entropy_syn),
.entropy_ack(entropy1_entropy_ack),
.debug(entropy1_debug),
.debug_update(entropy1_debug_update)
);
rosc_entropy entropy2(
.clk(clk),
.reset_n(reset_n),
.cs(entropy2_api_cs),
.we(entropy2_api_we),
.address(api_address),
.write_data(write_data),
.read_data(entropy2_api_read_data),
.error(entropy2_api_error),
.discard(discard_reg),
.test_mode(test_mode_reg),
.security_error(entropy2_security_error),
.entropy_enabled(entropy2_entropy_enabled),
.entropy_data(entropy2_entropy_data),
.entropy_valid(entropy2_entropy_syn),
.entropy_ack(entropy2_entropy_ack),
.debug(entropy2_debug),
.debug_update(entropy2_debug_update)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
discard_reg <= 0;
test_mode_reg <= 0;
debug_mux_reg <= DEBUG_CSPRNG;
debug_delay_reg <= DEFAULT_DEBUG_DELAY;
debug_delay_ctr_reg <= 32'h00000000;
debug_out_reg <= 8'h00;
end
else
begin
discard_reg <= discard_new;
debug_delay_ctr_reg <= debug_delay_ctr_new;
if (debug_out_we)
begin
debug_out_reg <= tmp_debug;
end
if (test_mode_we)
begin
test_mode_reg <= test_mode_new;
end
if (debug_mux_we)
begin
debug_mux_reg <= debug_mux_new;
end
if (debug_delay_we)
begin
debug_delay_reg <= debug_delay_new;
end
end
end // reg_update
//----------------------------------------------------------------
// debug_update_logic
//
// Debug update counter and update logic.
//----------------------------------------------------------------
always @*
begin : debug_update_logic
if (debug_delay_ctr_reg == debug_delay_reg)
begin
debug_out_we = 1;
debug_delay_ctr_new = 32'h00000000;
end
else
begin
debug_out_we = 0;
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
end
end // debug_update
//----------------------------------------------------------------
// debug_mux
//
// Select which of the sub modules that are connected to
// the debug port.
//----------------------------------------------------------------
always @*
begin : debug_mux
entropy1_debug_update = 0;
entropy2_debug_update = 0;
mixer_debug_update = 0;
csprng_debug_update = 0;
tmp_debug = 8'h00;
case(debug_mux_reg)
DEBUG_ENTROPY1:
begin
entropy1_debug_update = debug_update;
tmp_debug = entropy1_debug;
end
DEBUG_ENTROPY2:
begin
entropy2_debug_update = debug_update;
tmp_debug = entropy2_debug;
end
DEBUG_MIXER:
begin
mixer_debug_update = debug_update;
tmp_debug = mixer_debug;
end
DEBUG_CSPRNG:
begin
csprng_debug_update = debug_update;
tmp_debug = csprng_debug;
end
default:
begin
end
endcase // case (debug_mux_reg)
end // debug_mux
//----------------------------------------------------------------
// api_mux
//
// This is a simple decoder that looks at the top 4 bits of
// the given api address and selects which of the sub modules
// or the top level mux that gets to handle any API
// operations.
//----------------------------------------------------------------
always @*
begin : api_mux
trng_api_cs = 0;
trng_api_we = 0;
entropy1_api_cs = 0;
entropy1_api_we = 0;
entropy2_api_cs = 0;
entropy2_api_we = 0;
mixer_api_cs = 0;
mixer_api_we = 0;
csprng_api_cs = 0;
csprng_api_we = 0;
api_address = address[7 : 0];
tmp_read_data = 32'h00000000;
tmp_error = 0;
case (address[11 : 8])
TRNG_PREFIX:
begin
trng_api_cs = cs;
trng_api_we = we;
tmp_read_data = trng_api_read_data;
tmp_error = trng_api_error;
end
ENTROPY1_PREFIX:
begin
entropy1_api_cs = cs;
entropy1_api_we = we;
tmp_read_data = entropy1_api_read_data;
tmp_error = entropy1_api_error;
end
ENTROPY2_PREFIX:
begin
entropy2_api_cs = cs;
entropy2_api_we = we;
tmp_read_data = entropy2_api_read_data;
tmp_error = entropy2_api_error;
end
MIXER_PREFIX:
begin
mixer_api_cs = cs;
mixer_api_we = we;
tmp_read_data = mixer_api_read_data;
tmp_error = mixer_api_error;
end
CSPRNG_PREFIX:
begin
csprng_api_cs = cs;
csprng_api_we = we;
tmp_read_data = csprng_api_read_data;
tmp_error = csprng_api_error;
end
default:
begin
end
endcase // case (address[11 : 8])
end // api_mux
//----------------------------------------------------------------
// trng_api_logic
//
// Implementation of the top level api logic.
//----------------------------------------------------------------
always @*
begin : trng_api_logic
discard_new = 0;
test_mode_new = 0;
test_mode_we = 0;
debug_mux_new = 3'h0;
debug_mux_we = 0;
debug_delay_new = 32'h00000000;
debug_delay_we = 0;
trng_api_read_data = 32'h00000000;
trng_api_error = 0;
if (trng_api_cs)
begin
if (trng_api_we)
begin
// Write operations.
case (api_address)
// Write operations.
ADDR_TRNG_CTRL:
begin
discard_new = write_data[TRNG_CTRL_DISCARD_BIT];
test_mode_new = write_data[TRNG_CTRL_TEST_MODE_BIT];
test_mode_we = 1;
end
ADDR_DEBUG_CTRL:
begin
debug_mux_new = write_data[2 : 0];
debug_mux_we = 1;
end
ADDR_DEBUG_DELAY:
begin
debug_delay_new = write_data;
debug_delay_we = 1;
end
default:
begin
trng_api_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
// Read operations.
case (api_address)
// Read operations.
ADDR_NAME0:
begin
trng_api_read_data = TRNG_NAME0;
end
ADDR_NAME1:
begin
trng_api_read_data = TRNG_NAME1;
end
ADDR_VERSION:
begin
trng_api_read_data = TRNG_VERSION;
end
ADDR_TRNG_CTRL:
begin
end
ADDR_TRNG_STATUS:
begin
end
ADDR_DEBUG_CTRL:
begin
trng_api_read_data = debug_mux_new;
end
ADDR_DEBUG_DELAY:
begin
trng_api_read_data = debug_delay_reg;
end
default:
begin
trng_api_error = 1;
end
endcase // case (address)
end
end
end // trng_api_logic
endmodule // trng |
module trng_debug_ctrl(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
// Debug and control ports
output wire csprng_debug_mode,
output wire [4 : 0] csprng_num_rounds,
output wire csprng_reseed,
input wire csprng_error,
output wire security_error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter CORE_NAME0 = 32'h73686132; // "sha2"
parameter CORE_NAME1 = 32'h2d323536; // "-512"
parameter CORE_VERSION = 32'h302e3830; // "0.80"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
// Read operations.
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // trng_debug_ctrl |
module trng_csprng_fifo(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire [511 : 0] csprng_data,
input wire csprng_data_valid,
input wire discard,
output wire more_data,
output wire rnd_syn,
output wire [31 : 0] rnd_data,
input wire rnd_ack
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam FIFO_ADDR_BITS = 2;
localparam FIFO_ADDR_MAX = FIFO_ADDR_BITS - 1;
localparam FIFO_MAX = (1 << FIFO_ADDR_BITS) - 1;
localparam WR_IDLE = 0;
localparam WR_WAIT = 1;
localparam WR_WRITE = 2;
localparam WR_DISCARD = 7;
localparam RD_IDLE = 0;
localparam RD_ACK = 1;
localparam RD_DISCARD = 7;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [511 : 0] fifo_mem [0 : FIFO_MAX];
reg fifo_mem_we;
reg [3 : 0] mux_data_ptr_reg;
reg [3 : 0] mux_data_ptr_new;
reg mux_data_ptr_inc;
reg mux_data_ptr_rst;
reg mux_data_ptr_we;
reg [FIFO_ADDR_MAX : 0] rd_ptr_reg;
reg [FIFO_ADDR_MAX : 0] rd_ptr_new;
reg rd_ptr_inc;
reg rd_ptr_rst;
reg rd_ptr_we;
reg [FIFO_ADDR_MAX : 0] wr_ptr_reg;
reg [FIFO_ADDR_MAX : 0] wr_ptr_new;
reg wr_ptr_inc;
reg wr_ptr_rst;
reg wr_ptr_we;
reg [FIFO_ADDR_MAX : 0] fifo_ctr_reg;
reg [FIFO_ADDR_MAX : 0] fifo_ctr_new;
reg fifo_ctr_inc;
reg fifo_ctr_dec;
reg fifo_ctr_rst;
reg fifo_ctr_we;
reg fifo_empty;
reg fifo_full;
reg [31 : 0] rnd_data_reg;
reg rnd_syn_reg;
reg rnd_syn_new;
reg rnd_syn_we;
reg [2 : 0] rd_ctrl_reg;
reg [2 : 0] rd_ctrl_new;
reg rd_ctrl_we;
reg [2 : 0] wr_ctrl_reg;
reg [2 : 0] wr_ctrl_new;
reg wr_ctrl_we;
reg more_data_reg;
reg more_data_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] muxed_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rnd_data = rnd_data_reg;
assign rnd_syn = rnd_syn_reg;
assign more_data = more_data_reg;
//----------------------------------------------------------------
// reg_update
//
// Register update. All registers have asynchronous reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
fifo_mem[00] <= {16{32'h00000000}};
fifo_mem[01] <= {16{32'h00000000}};
fifo_mem[02] <= {16{32'h00000000}};
fifo_mem[03] <= {16{32'h00000000}};
mux_data_ptr_reg <= 4'h0;
rd_ptr_reg <= {FIFO_ADDR_BITS{1'b0}};
wr_ptr_reg <= {FIFO_ADDR_BITS{1'b0}};
fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}};
rnd_data_reg <= 32'h00000000;
rnd_syn_reg <= 0;
more_data_reg <= 0;
wr_ctrl_reg <= WR_IDLE;
rd_ctrl_reg <= RD_IDLE;
end
else
begin
rnd_data_reg <= muxed_data;
more_data_reg <= more_data_new;
if (rnd_syn_we)
begin
rnd_syn_reg <= rnd_syn_new;
end
if (fifo_mem_we)
begin
fifo_mem[wr_ptr_reg] <= csprng_data;
end
if (mux_data_ptr_we)
begin
mux_data_ptr_reg <= mux_data_ptr_new;
end
if (rd_ptr_we)
begin
rd_ptr_reg <= rd_ptr_new;
end
if (wr_ptr_we)
begin
wr_ptr_reg <= wr_ptr_new;
end
if (fifo_ctr_we)
begin
fifo_ctr_reg <= fifo_ctr_new;
end
if (rd_ctrl_we)
begin
rd_ctrl_reg <= rd_ctrl_new;
end
if (wr_ctrl_we)
begin
wr_ctrl_reg <= wr_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// output_data_mux
//
// Logic that reads out a 512 bit word from the fifo memory
// and then selects a 32-bit word as output data.
//----------------------------------------------------------------
always @*
begin : output_data_mux
reg [511 : 0] fifo_rd_data;
fifo_rd_data = fifo_mem[rd_ptr_reg];
muxed_data = fifo_rd_data[mux_data_ptr_reg * 32 +: 32];
end // output_data_mux
//----------------------------------------------------------------
// mux_data_ptr
//
// Pointer for selecting output data word from the 512 bit
// word currently being read in the FIFO.
//----------------------------------------------------------------
always @*
begin : mux_data_ptr
mux_data_ptr_new = 4'h0;
mux_data_ptr_we = 0;
if (mux_data_ptr_rst)
begin
mux_data_ptr_new = 4'h0;
mux_data_ptr_we = 1;
end
if (mux_data_ptr_inc)
begin
mux_data_ptr_new = mux_data_ptr_reg + 1'b1;
mux_data_ptr_we = 1;
end
end // mux_data_ptr
//----------------------------------------------------------------
// fifo_rd_ptr
//
// Pointer that selects the current 512 bit word in the FIFO
// to extract data from.
//----------------------------------------------------------------
always @*
begin : fifo_rd_ptr
rd_ptr_new = {FIFO_ADDR_BITS{1'b0}};
rd_ptr_we = 0;
fifo_ctr_dec = 0;
if (rd_ptr_rst)
rd_ptr_we = 1;
if (rd_ptr_inc)
begin
fifo_ctr_dec = 1;
if (rd_ptr_reg == FIFO_MAX)
rd_ptr_we = 1;
else
begin
rd_ptr_new = rd_ptr_reg + 1'b1;
rd_ptr_we = 1;
end
end
end // fifo_rd_ptr
//----------------------------------------------------------------
// fifo_wr_ptr
//
// Pointer to where to store a new 512 bit word in the FIFO.
//----------------------------------------------------------------
always @*
begin : fifo_wr_ptr
wr_ptr_new = {FIFO_ADDR_BITS{1'b0}};
wr_ptr_we = 0;
if (wr_ptr_rst)
wr_ptr_we = 1;
if (wr_ptr_inc)
begin
if (wr_ptr_reg == FIFO_MAX)
wr_ptr_we = 1;
else
begin
wr_ptr_new = wr_ptr_reg + 1'b1;
wr_ptr_we = 1;
end
end
end // fifo_wr_ptr
//----------------------------------------------------------------
// fifo_ctr
//
// fifo counter tracks the number of 512 bit elements currently
// in the fifp. The counter also signals the csprng when more
// data is needed. The fifo also signals applications when
// random numbers are available, that is there is at least
// one elemnt in the fifo with 32-bit words not yet used.
//----------------------------------------------------------------
always @*
begin : fifo_ctr
fifo_ctr_new = {FIFO_ADDR_BITS{1'b0}};
fifo_ctr_we = 0;
fifo_empty = 0;
fifo_full = 0;
if (fifo_ctr_reg == 0)
begin
fifo_empty = 1;
end
if (fifo_ctr_reg == FIFO_MAX)
begin
fifo_full = 1;
end
if (fifo_ctr_rst)
fifo_ctr_we = 1;
if ((fifo_ctr_inc) && (fifo_ctr_reg < FIFO_MAX))
begin
fifo_ctr_new = fifo_ctr_reg + 1'b1;
fifo_ctr_we = 1;
end
if ((fifo_ctr_dec) && (fifo_ctr_reg > 0))
begin
fifo_ctr_new = fifo_ctr_reg - 1'b1;
fifo_ctr_we = 1;
end
end // fifo_ctr
//----------------------------------------------------------------
// rd_ctrl
//
// Control FSM for reading data as requested by the consumers.
//----------------------------------------------------------------
always @*
begin : rd_ctrl
mux_data_ptr_rst = 0;
mux_data_ptr_inc = 0;
rnd_syn_new = 0;
rnd_syn_we = 0;
rd_ptr_inc = 0;
rd_ptr_rst = 0;
rd_ctrl_new = RD_IDLE;
rd_ctrl_we = 0;
case (rd_ctrl_reg)
RD_IDLE:
begin
if (discard)
begin
rd_ctrl_new = RD_DISCARD;
rd_ctrl_we = 1;
end
else
begin
if (!fifo_empty)
begin
rnd_syn_new = 1;
rnd_syn_we = 1;
rd_ctrl_new = RD_ACK;
rd_ctrl_we = 1;
end
end
end
RD_ACK:
begin
if (discard)
begin
rd_ctrl_new = RD_DISCARD;
rd_ctrl_we = 1;
end
else
begin
if (rnd_ack)
begin
if (mux_data_ptr_reg == 4'hf)
begin
rd_ptr_inc = 1;
mux_data_ptr_rst = 1;
end
else
begin
mux_data_ptr_inc = 1;
end
rnd_syn_new = 0;
rnd_syn_we = 1;
rd_ctrl_new = RD_IDLE;
rd_ctrl_we = 1;
end
end
end
RD_DISCARD:
begin
rnd_syn_new = 0;
rnd_syn_we = 1;
rd_ptr_rst = 1;
rd_ctrl_new = RD_IDLE;
rd_ctrl_we = 1;
end
endcase // case (rd_ctrl_reg)
end // rd_ctrl
//----------------------------------------------------------------
// wr_ctrl
//
// FSM for requesting data and writing new data to the fifo.
//----------------------------------------------------------------
always @*
begin : wr_ctrl
wr_ptr_inc = 0;
wr_ptr_rst = 0;
fifo_mem_we = 0;
fifo_ctr_inc = 0;
fifo_ctr_rst = 0;
more_data_new = 0;
wr_ctrl_new = WR_IDLE;
wr_ctrl_we = 0;
case (wr_ctrl_reg)
WR_IDLE:
begin
if (discard)
begin
wr_ctrl_new = WR_DISCARD;
wr_ctrl_we = 1;
end
else
begin
if (!fifo_full)
begin
more_data_new = 1;
end
if (csprng_data_valid)
begin
fifo_mem_we = 1;
wr_ptr_inc = 1;
fifo_ctr_inc = 1;
end
end
end
WR_DISCARD:
begin
fifo_ctr_rst = 1;
wr_ptr_rst = 1;
wr_ctrl_new = WR_IDLE;
wr_ctrl_we = 1;
end
endcase // case (wr_ctrl_reg)
end // wr_ctrl
endmodule // trng_csprng_fifo |
module tb_trng();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
parameter TRNG_PREFIX = 4'h0;
parameter ENTROPY1_PREFIX = 4'h5;
parameter ENTROPY2_PREFIX = 4'h6;
parameter MIXER_PREFIX = 4'ha;
parameter CSPRNG_PREFIX = 4'hb;
parameter ADDR_TRNG_CTRL = 8'h10;
parameter TRNG_CTRL_ENABLE_BIT = 0;
parameter TRNG_CTRL_ENT0_ENABLE_BIT = 1;
parameter TRNG_CTRL_ENT1_ENABLE_BIT = 2;
parameter TRNG_CTRL_ENT2_ENABLE_BIT = 3;
parameter TRNG_CTRL_SEED_BIT = 8;
parameter ADDR_TRNG_STATUS = 8'h11;
parameter ADDR_TRNG_RND_DATA = 8'h20;
parameter ADDR_TRNG_RND_DATA_VALID = 8'h21;
parameter TRNG_RND_VALID_BIT = 0;
parameter ADDR_CSPRNG_CTRL = 8'h10;
parameter CSPRNG_CTRL_ENABLE_BIT = 0;
parameter CSPRNG_CTRL_SEED_BIT = 1;
parameter ADDR_CSPRNG_STATUS = 8'h11;
parameter CSPRNG_STATUS_RND_VALID_BIT = 0;
parameter ADDR_CSPRNG_NUM_ROUNDS = 8'h40;
parameter ADDR_CSPRNG_NUM_BLOCKS_LOW = 8'h41;
parameter ADDR_CSPRNG_NUM_BLOCKS_HIGH = 8'h42;
parameter ADDR_ENTROPY0_RAW = 8'h40;
parameter ADDR_ENTROPY0_STATS = 8'h41;
parameter ADDR_ENTROPY1_RAW = 8'h50;
parameter ADDR_ENTROPY1_STATS = 8'h51;
parameter ADDR_ENTROPY2_RAW = 8'h60;
parameter ADDR_ENTROPY2_STATS = 8'h61;
parameter ADDR_MIXER_CTRL = 8'h10;
parameter MIXER_CTRL_ENABLE_BIT = 0;
parameter MIXER_CTRL_RESTART_BIT = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg tb_clk;
reg tb_reset_n;
reg tb_avalanche_noise;
reg tb_cs;
reg tb_we;
reg [11 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire [7 : 0] tb_debug;
reg tb_debug_update;
wire tb_error;
wire tb_security_error;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
trng dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.avalanche_noise(tb_avalanche_noise),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error),
.debug(tb_debug),
.debug_update(tb_debug_update),
.security_error(tb_security_error)
);
//----------------------------------------------------------------
// Concurrent assignments.
//----------------------------------------------------------------
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_avalanche_noise = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 12'h000;
tb_write_data = 32'h00000000;
tb_debug_update = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// tc1_gen_rnd()
//
// A simple first testcase that tries to make the DUT generate
// a number of random values.
//----------------------------------------------------------------
task tc1_gen_rnd;
reg [31 : 0] i;
begin
$display("*** Starting TC1: Generating random values from entropy.");
tb_debug_update = 1;
#(10 * CLK_PERIOD);
tb_debug_update = 0;
// Enable the csprng and the mixer
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_CTRL}, 32'h00000001);
write_word({MIXER_PREFIX, ADDR_MIXER_CTRL}, 32'h00000001);
// We try to change number of blocks to a low value to force reseeding.
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_LOW}, 32'h00000002);
write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_HIGH}, 32'h00000000);
#(100 * CLK_PERIOD);
i = 0;
while (i < 10000)
begin
$display("Reading rnd word %08x.", i);
i = i + 1;
read_word({CSPRNG_PREFIX, ADDR_TRNG_RND_DATA});
#(2 * CLK_PERIOD);
end
$display("*** TC1 done.");
end
endtask // tc1_gen_seeds
//----------------------------------------------------------------
// trng_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : trng_test
$display(" -= Testbench for TRNG started =-");
$display(" ===============================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
tc1_gen_rnd();
display_test_results();
$display("");
$display("*** TRNG simulation done. ***");
$finish;
end // trng_test
endmodule // tb_trng |
module tb_mixer();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_enable;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg tb_discard;
reg tb_test_mode;
reg tb_more_seed;
wire tb_security_error;
reg tb_entropy0_enabled;
reg tb_entropy0_syn;
reg [31 : 0] tb_entropy0_data;
wire tb_entropy0_ack;
reg tb_entropy1_enabled;
reg tb_entropy1_syn;
reg [31 : 0] tb_entropy1_data;
wire tb_entropy1_ack;
reg tb_entropy2_enabled;
reg tb_entropy2_syn;
reg [31 : 0] tb_entropy2_data;
wire tb_entropy2_ack;
wire [511 : 0] tb_seed_data;
wire tb_syn;
reg tb_ack;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
trng_mixer dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error),
.discard(tb_discard),
.test_mode(tb_test_mode),
.security_error(tb_security_error),
.more_seed(tb_more_seed),
.entropy0_enabled(tb_entropy0_enabled),
.entropy0_syn(tb_entropy0_syn),
.entropy0_data(tb_entropy0_data),
.entropy0_ack(tb_entropy0_ack),
.entropy1_enabled(tb_entropy1_enabled),
.entropy1_syn(tb_entropy1_syn),
.entropy1_data(tb_entropy1_data),
.entropy1_ack(tb_entropy1_ack),
.entropy2_enabled(tb_entropy2_enabled),
.entropy2_syn(tb_entropy2_syn),
.entropy2_data(tb_entropy2_data),
.entropy2_ack(tb_entropy2_ack),
.seed_data(tb_seed_data),
.seed_syn(tb_syn),
.seed_ack(tb_ack)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h00;
tb_write_data = 32'h00000000;
tb_discard = 0;
tb_test_mode = 0;
tb_more_seed = 0;
tb_entropy0_enabled = 0;
tb_entropy0_syn = 0;
tb_entropy0_data = 32'h00000000;
tb_entropy1_enabled = 0;
tb_entropy1_syn = 0;
tb_entropy1_data = 32'h00000000;
tb_entropy2_enabled = 0;
tb_entropy2_syn = 0;
tb_entropy2_data = 32'h00000000;
tb_ack = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// tc1_gen_seeds()
//
// A simple first testcase that tries to make the DUT generate
// a number of seeds based on entropy from source 0 and 2.
//----------------------------------------------------------------
task tc1_gen_seeds;
begin
$display("*** Starting TC1: Setting continious seed generation.");
tb_entropy0_enabled = 1;
tb_entropy0_syn = 1;
tb_entropy0_data = 32'h01010202;
tb_entropy2_enabled = 1;
tb_entropy2_syn = 1;
tb_entropy2_data = 32'haa55aa55;
tb_enable = 1;
tb_more_seed = 1;
tb_ack = 1;
#(50000 * CLK_PERIOD);
$display("*** TC1 done.");
end
endtask // tc1_gen_seeds
//----------------------------------------------------------------
// mixer_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : mixer_test
$display(" -= Testbench for mixer started =-");
$display(" ================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
tc1_gen_seeds();
display_test_results();
$display("");
$display("*** Mixer simulation done. ***");
$finish;
end // mixer_test
endmodule // tb_mixer |
module rosc_entropy(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = 32'h00000000;
assign error = 0;
assign security_error = 0;
assign entropy_enabled = 1;
assign entropy_data = 32'haa55aa55;
assign entropy_valid = 1;
assign debug = 8'h42;
endmodule // ringosc_entropy |
module avalanche_entropy(
input wire clk,
input wire reset_n,
input wire noise,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = 32'h00000000;
assign error = 0;
assign security_error = 0;
assign entropy_enabled = 1;
assign entropy_data = 32'h11223344;
assign entropy_valid = 1;
assign debug = 8'haa;
endmodule // avalanche_entropy |
module pseudo_entropy(
input wire clk,
input wire reset_n,
input wire enable,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] stats,
output wire enabled,
output wire entropy_syn,
output wire [31 : 0] entropy_data,
input wire entropy_ack
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign enabled = enable;
assign raw_entropy = enable ? 32'h00ff00ff : 32'h00000000;
assign stats = enable ? 32'hff00ff00 : 32'h00000000;
assign entropy_syn = enable;
assign entropy_data = enable ? 32'hf1e2d3c4 : 32'h00000000;
endmodule // pseudo_entropy |
module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
);
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule |
module branch_jump (
output branch_taken,
output [31:0] branch_target,
output jump,
output [31:0] jump_target,
input [31:0] inst,
input [31:0] pc,
input [31:0] rd1,
input [31:0] alu_out
);
wire [6:0] opcode = inst[6:0];
wire [2:0] funct3 = inst[9:7];
wire [11:0] split_imm = {inst[31:27], inst[16:10]};
wire [31:0] sext_split_imm = split_imm[11] ? {20'hFFFFF, split_imm} : {20'h0, split_imm};
assign jump = (opcode == `OPCODE_J ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR);
wire [31:0] j_offset = inst[31] ? {6'h3F, inst[31:7], 1'b0} : {6'h0, inst[31:7], 1'b0};
assign jump_target = (opcode == `OPCODE_J || opcode == `OPCODE_JAL) ? j_offset + pc : rd1;
/* branch */
assign branch_target = pc + ($signed(sext_split_imm) << 1);
reg branch_sat;
always @ (*) begin
case (funct3)
`F3_BEQ: branch_sat = (alu_out == 0);
`F3_BNE: branch_sat = (alu_out != 0);
`F3_BLT: branch_sat = (alu_out == 1);
`F3_BGE: branch_sat = (alu_out != 1);
`F3_BLTU: branch_sat = (alu_out == 1);
`F3_BGEU: branch_sat = (alu_out != 1);
default: branch_sat = 0;
endcase
end
assign branch_taken = branch_sat && (opcode == `OPCODE_BRANCH);
endmodule |
module multiplier (
output [31:0] multiplier_result,
input [31:0] op1,
input [31:0] op2,
input [1:0] mul_sel
);
wire [63:0] sext_op1 = op1[31] ? {32'hFFFFFFFF, op1} : {32'h0, op1};
wire [63:0] sext_op2 = op2[31] ? {32'hFFFFFFFF, op2} : {32'h0, op2};
reg [63:0] result;
always @ (*) begin
case (mul_sel)
`MUL_LO, `MUL_HI:
result = $signed(sext_op1) * $signed(sext_op2);
`MUL_HI_SU:
result = $signed(sext_op1) * {32'h0, op2};
`MUL_HI_UU:
result = {32'h0, op1} * {32'h0, op2};
default:
result = 0;
endcase
end
assign multiplier_result = (mul_sel == `MUL_LO) ? result[31:0] : result[63:0];
endmodule |
module arbiter (
input clk,
input reset,
output [31:0] request_data,
output stall,
input [31:0] fetch_addr,
input fetch_request,
output fetch_data_valid,
input [31:0] dmem_addr,
input [31:0] dmem_write_data,
input [3:0] dmem_write_mask,
input dmem_request,
input dmem_request_type,
output dmem_data_valid,
/* memory interface */
output reg [31:0] mem_addr,
output [3:0] mem_mask, /* write */
output mem_enable,
output reg mem_cmd,
input [31:0] mem_data,
output [31:0] mem_wdata,
input mem_valid
);
wire requests_pending = fetch_request | dmem_request;
reg fetch_satisfied;
reg memory_satisfied;
localparam S_IDLE = 3'd0;
localparam S_SVC_FETCH = 3'd1;
localparam S_SVC_MEM_R = 3'd2;
localparam S_SVC_MEM_W = 3'd3;
reg [2:0] state;
reg [2:0] next_state;
always @ (posedge clk) begin
if (reset) begin
state <= S_IDLE;
end else begin
state <= next_state;
end
end
always @ (posedge clk) begin
if (reset) begin
fetch_satisfied <= 1;
end else if (state == S_IDLE && next_state != S_IDLE) begin
fetch_satisfied <= (fetch_request ? 0 : 1);
end else if (state == S_SVC_FETCH && mem_valid) begin
fetch_satisfied <= 1;
end
if (reset) begin
memory_satisfied <= 1;
end else if (state == S_IDLE && next_state != S_IDLE) begin
memory_satisfied <= (dmem_request ? 0 : 1);
end else if (state == S_SVC_MEM_R && mem_valid) begin
memory_satisfied <= 1;
end
end
always @ (*) begin
case (state)
S_IDLE:
if (requests_pending)
if (fetch_request)
next_state = S_SVC_FETCH;
else if (dmem_request)
if (dmem_request_type == `MEM_REQ_WRITE)
next_state = S_SVC_MEM_W;
else
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
else
next_state = S_IDLE;
S_SVC_FETCH:
if (!fetch_satisfied)
next_state = S_SVC_FETCH;
else if (dmem_request)
if (dmem_request_type == `MEM_REQ_WRITE)
next_state = S_SVC_MEM_W;
else
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
S_SVC_MEM_R:
if (!memory_satisfied)
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
S_SVC_MEM_W:
/* allow writes to go... write through */
next_state = S_IDLE;
default:
next_state = S_IDLE;
endcase
end
always @ (*) begin
case (state)
S_SVC_FETCH:
mem_addr = fetch_addr;
S_SVC_MEM_R, S_SVC_MEM_W:
mem_addr = dmem_addr;
default:
mem_addr = 0;
endcase
end
assign stall = (next_state != S_IDLE);
assign fetch_data_valid = (state == S_SVC_FETCH & mem_valid);
assign dmem_data_valid = (state == S_SVC_MEM_R & mem_valid);
assign request_data = mem_data;
assign mem_wdata = dmem_write_data;
assign mem_enable = (state == S_SVC_FETCH && !fetch_satisfied) ||
(state == S_SVC_MEM_R && !memory_satisfied) ||
(state == S_SVC_MEM_W);
assign mem_mask = dmem_write_mask;
always @ (*) begin
case (state)
S_SVC_FETCH: mem_cmd = `MEM_CMD_READ;
S_SVC_MEM_R: mem_cmd = `MEM_CMD_READ;
S_SVC_MEM_W: mem_cmd = `MEM_CMD_WRITE;
default: mem_cmd = 0;
endcase
end
endmodule |
module memory_system (
input clk,
input reset,
output stall,
input vm_enable,
input [31:0] ptbr,
input flush_tlb,
input [31:0] fetch_addr,
input fetch_request,
output fetch_data_valid,
input [31:0] dmem_addr,
input [31:0] dmem_write_data,
input [3:0] dmem_write_mask,
input dmem_request,
input dmem_request_type,
output dmem_data_valid,
output [31:0] request_data
);
localparam S_IDLE = 2'd0;
localparam S_TRANSLATE = 2'd1;
localparam S_MEM_ACCESS = 2'd2;
localparam MM_SELECT_TRANSLATER = 1'd1;
localparam MM_SELECT_ARBITER = 1'd0;
reg [1:0] state;
reg [1:0] next_state;
always @ (posedge clk) begin
if (reset)
state <= S_IDLE;
else
state <= next_state;
end
wire arbiter_stall;
wire arbiter_mem_enable;
wire arbiter_cmd;
wire [31:0] arbiter_addr;
wire [31:0] arbiter_write_data = dmem_write_data;
wire [3:0] arbiter_write_mask = dmem_write_mask;
wire [31:0] arbiter_read_data;
wire arbiter_data_valid;
arbiter arbit(.clk(clk), .reset(reset),
.request_data(request_data), .stall(arbiter_stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(dmem_addr), .dmem_write_data(dmem_write_data), .dmem_write_mask(dmem_write_mask),
.dmem_request(dmem_request), .dmem_request_type(dmem_request_type), .dmem_data_valid(dmem_data_valid),
.mem_addr(arbiter_addr), .mem_mask(arbiter_write_mask), .mem_enable(arbiter_mem_enable), .mem_cmd(arbiter_cmd),
.mem_data(arbiter_read_data), .mem_wdata(arbiter_write_data), .mem_valid(arbiter_data_valid));
wire translater_mem_enable;
wire translater_cmd = `MEM_CMD_READ;
wire [31:0] translater_addr;
wire [31:0] translater_write_data = dmem_write_data;
wire [3:0] translater_write_mask = dmem_write_mask;
wire [31:0] translater_read_data;
wire translater_data_valid;
wire [31:0] translated_addr;
wire translate_enable = vm_enable;
wire translation_complete;
wire launch_translation;
translater t(.clk(clk), .reset(reset),
.vm_enable(translate_enable), .launch_translation(launch_translation),
.physical_address(translated_addr), .virtual_address(arbiter_addr),
.translation_complete(translation_complete), .ptbr(ptbr), .flush_tlb(flush_tlb),
.translate_mem_enable(translater_mem_enable),
.translate_addr(translater_addr), .request_data(translater_read_data), .translate_data_valid(translater_data_valid));
wire mem_enable;
wire mem_cmd;
wire [31:0] mem_addr;
wire [31:0] mem_write_data;
wire [3:0] mem_write_mask;
wire [31:0] mem_data;
wire mem_valid;
wire mm_select;
memory_mux m(.select(mm_select),
.enable_0(arbiter_mem_enable), .command_0(arbiter_cmd), .address_0(arbiter_addr),
.write_data_0(arbiter_write_data), .write_mask_0(arbiter_write_mask),
.read_data_0(arbiter_read_data), /* .valid_0(), */
.enable_1(translater_mem_enable), .command_1(translater_cmd), .address_1(translater_addr),
.write_data_1(translater_write_data), .write_mask_1(translater_write_mask),
.read_data_1(translater_read_data), .valid_1(translater_data_valid),
.enable(mem_enable), .command(mem_cmd), .address(mem_addr),
.write_data(mem_write_data), .write_mask(mem_write_mask),
.read_data(mem_data), .valid(mem_valid));
assign request_data = mm_select ? translater_read_data : arbiter_read_data;
always @ (*) begin
case (state)
S_IDLE:
if (vm_enable && arbiter_mem_enable)
next_state = S_TRANSLATE;
else
next_state = S_IDLE;
S_TRANSLATE:
if (translation_complete)
next_state = S_MEM_ACCESS;
else
next_state = S_TRANSLATE;
S_MEM_ACCESS:
if (mem_valid)
next_state = S_IDLE;
else
next_state = S_MEM_ACCESS;
default:
next_state = S_IDLE;
endcase
end
wire translation_stall = (state != S_IDLE);
assign launch_translation = (next_state == S_TRANSLATE);
assign mm_select = state == S_TRANSLATE ? MM_SELECT_TRANSLATER : MM_SELECT_ARBITER;
assign arbiter_data_valid = vm_enable ? mem_valid : translation_complete && mem_valid;
wire [31:0] physical_address = (vm_enable && translation_complete) ? translated_addr : mem_addr;
assign stall = arbiter_stall || translation_stall;
/* actual memory device */
mem simmem(.clk(clk), .reset(reset),
.addr(physical_address), .mask(mem_write_mask), .enable(mem_enable),
.cmd(mem_cmd), .load_data(mem_data), .write_data(mem_write_data), .valid(mem_valid));
endmodule |
module control_processor (
input clk,
input reset,
input stall,
input [31:0] inst,
input [31:0] pc,
input enable,
output reg [31:0] pcr_data,
input [31:0] pcr_write_data,
input [4:0] pcr,
input [1:0] cmd,
output interrupt,
output reg [31:0] ptbr,
output reg [31:0] evec,
output vm_enable,
output flush_tlb
);
wire [2:0] command = {1'b0, cmd};
wire [11:0] imm12 = inst[21:10];
wire [31:0] sext_imm = imm12[11] ? {20'hFFFFF, imm12} : {20'b0, imm12};
reg [23:0] status; /* top 8 bits are IP */
reg [7:0] interrupts_pending;
reg [31:0] epc;
reg [31:0] badvaddr;
/* evec */
reg [31:0] count;
reg [31:0] compare;
reg [31:0] cause;
/* ptbr */
reg [31:0] k0;
reg [31:0] k1;
reg [31:0] tohost;
reg [31:0] fromhost;
/* Upon reset, only the supervisor bit is set. S64 and U64 are hard-wired
* to zero, as are EC, EV, and EF. */
localparam SR_WRITE_MASK = (`SR_IM | `SR_VM | `SR_S | `SR_PS | `SR_ET);
reg [31:0] write_data;
always @ (*) begin
if (!stall && enable)
case (command)
`F3_MTPCR: write_data = pcr_write_data;
`F3_SETPCR: write_data = pcr_data | sext_imm;
`F3_CLEARPCR: write_data = pcr_data | ~(sext_imm);
default: write_data = 32'b0;
endcase
end
always @ (posedge clk) begin
if (reset)
interrupts_pending <= 8'b0;
if (reset)
status <= (`SR_S);
else if (!stall && enable && pcr == `PCR_STATUS)
status <= write_data & SR_WRITE_MASK;
if (reset)
epc <= 32'h0;
else if (!stall && enable && pcr == `PCR_EPC)
epc <= write_data;
else if (interrupt)
epc <= pc;
if (reset)
badvaddr <= 32'h0;
if (reset)
evec <= 32'h0;
else if (!stall && enable && pcr == `PCR_EVEC)
evec <= write_data & 32'hFFFFFFFC;
if (reset)
count <= 32'h0;
else if (!stall && enable && pcr == `PCR_COUNT)
count <= write_data;
if (reset) begin
compare <= 32'h0;
end else if (!stall && enable && pcr == `PCR_COMPARE) begin
compare <= write_data;
interrupts_pending[`IRQ_TIMER] = 0;
end
if (reset)
cause <= 32'h0;
if (reset)
ptbr <= 32'h0;
else if (!stall && enable && pcr == `PCR_PTBR)
ptbr <= write_data;
if (reset)
k0 <= 32'h0;
else if (!stall && enable && pcr == `PCR_K0)
k0 <= write_data;
if (reset)
k1 <= 32'h0;
else if (!stall && enable && pcr == `PCR_K1)
k1 <= write_data;
if (reset)
tohost <= 32'h0;
else if (!stall && enable && pcr == `PCR_TOHOST)
tohost <= write_data;
if (reset)
fromhost <= 32'h0;
else if (!stall && enable && pcr == `PCR_FROMHOST)
fromhost <= write_data;
end
/* The old value of a PCR is returned on a write */
always @ (*) begin
if (enable)
case (pcr)
`PCR_STATUS: pcr_data = {interrupts_pending, status};
`PCR_EPC: pcr_data = epc;
`PCR_BADVADDR: pcr_data = badvaddr;
`PCR_EVEC: pcr_data = evec;
`PCR_COUNT: pcr_data = count;
`PCR_COMPARE: pcr_data = compare;
`PCR_PTBR: pcr_data = ptbr;
`PCR_K0: pcr_data = k0;
`PCR_K1: pcr_data = k1;
`PCR_TOHOST: pcr_data = tohost;
`PCR_FROMHOST: pcr_data = fromhost;
default: pcr_data = 32'h0;
endcase
else
pcr_data = 32'h0;
end
/* Timer interrupt */
always @ (posedge clk) begin
count <= count + 1;
end
always @ (*) begin
if (count == compare)
interrupts_pending[`IRQ_TIMER] = 1;
end
wire interrupt_mask = status[23:16];
assign interrupt = ((status & `SR_ET) && (interrupt_mask & interrupts_pending));
/* Virtual memory */
assign flush_tlb = (!stall && enable && pcr == `PCR_PTBR);
assign vm_enable = status[8];
endmodule |
module alu_dec (
output reg [4:0] alu_sel,
output [1:0] mul_sel,
output reg [31:0] op1,
output reg [31:0] op2,
input [31:0] rs1,
input [31:0] rs2,
input [31:0] inst
);
wire [6:0] opcode = inst[6:0];
wire [9:7] funct3 = inst[9:7];
wire [4:0] shamt = inst[14:10];
wire [11:0] imm12 = inst[21:10];
wire [31:0] s_ext_imm = imm12[11] ? {20'hFFFFF, imm12} : {20'b0, imm12};
wire [31:0] z_ext_imm = {20'b0, imm12};
wire [19:0] lui_imm = inst[26:7];
wire [4:0] imm12hi = inst[31:27];
wire [6:0] imm12lo = inst[16:10];
wire [11:0] split_imm12 = {imm12hi, imm12lo};
reg [3:0] compute_sel;
always @ (*) begin
/* op1 */
op1 = (opcode == `OPCODE_LUI) ? {12'b0, lui_imm} : rs1;
/* op2 */
case (opcode)
`OPCODE_OP_IMM:
case (funct3)
/* sign-extended immediate */
`F3_ADD, `F3_SLT, `F3_SLTU, `F3_XOR, `F3_OR, `F3_AND:
op2 = s_ext_imm;
/* shifts */
`F3_SLL, `F3_SR:
op2 = shamt;
default:
op2 = 0;
endcase
`OPCODE_STORE:
op2 = split_imm12;
`OPCODE_LOAD:
op2 = imm12;
`OPCODE_OP:
/* subtraction */
op2 = (funct3 == `F3_ADD && inst[16]) ? -rs2 : rs2;
default:
op2 = rs2;
endcase
/* compute_sel, for integer computes with[out] immediates */
case (funct3)
`F3_ADD: compute_sel = `ALU_ADD;
`F3_SLL: compute_sel = `ALU_SLL;
`F3_SLT: compute_sel = `ALU_SLT;
`F3_SLTU: compute_sel = `ALU_SLTU;
`F3_XOR: compute_sel = `ALU_XOR;
`F3_SR: compute_sel = inst[16] ? `ALU_SRA : `ALU_SRL;
`F3_OR: compute_sel = `ALU_OR;
`F3_AND: compute_sel = `ALU_AND;
default: compute_sel = `ALU_NONE;
endcase
/* alu_sel */
case (opcode)
`OPCODE_OP:
/* inst[10] indicates the multiplication/division operations */
if (inst[10] == 1'b1) begin
case (funct3)
`F3_MUL: alu_sel = `ALU_MUL;
`F3_DIV: alu_sel = `ALU_DIV;
`F3_DIVU: alu_sel = `ALU_DIVU;
`F3_REM: alu_sel = `ALU_REM;
`F3_REMU: alu_sel = `ALU_REMU;
default: alu_sel = `ALU_NONE;
endcase
end else begin
alu_sel = compute_sel;
end
`OPCODE_OP_IMM:
alu_sel = compute_sel;
`OPCODE_LOAD, `OPCODE_STORE:
alu_sel = `ALU_ADD;
`OPCODE_LUI:
alu_sel = `ALU_LUI;
`OPCODE_BRANCH:
case (funct3)
`F3_BEQ, `F3_BNE: alu_sel = `ALU_XOR;
`F3_BLT, `F3_BGE: alu_sel = `ALU_SLT;
`F3_BLTU, `F3_BGEU: alu_sel = `ALU_SLTU;
default: alu_sel = `ALU_NONE;
endcase
default:
alu_sel = `ALU_NONE;
endcase
end
/* mul_sel - it maps directly on the funct bits */
assign mul_sel = inst[8:7];
endmodule |
module translater (
input clk,
input reset,
input vm_enable,
input launch_translation,
output reg [31:0] physical_address,
input [31:0] virtual_address,
output translation_complete,
input [31:0] ptbr,
input flush_tlb,
/* memory interface */
output reg [31:0] translate_addr,
output translate_mem_enable,
input [31:0] request_data,
input translate_data_valid
);
wire [31:0] tlb_output_address;
wire tlb_hit;
wire translation_required;
localparam S_IDLE = 2'd0;
localparam S_TLB = 2'd1;
localparam S_TRAN_PPN1 = 2'd2;
localparam S_TRAN_PPN0 = 2'd3;
reg [31:0] address;
reg [1:0] state;
reg [1:0] next_state;
always @ (posedge clk) begin
if (reset)
state <= S_IDLE;
else
state <= next_state;
end
always @ (posedge clk) begin
if (reset)
address <= 0;
else if (state == S_IDLE && launch_translation)
address <= virtual_address;
end
always @ (*) begin
case (state)
S_IDLE:
next_state = launch_translation ? S_TLB : S_IDLE;
S_TLB:
if (tlb_hit)
next_state = S_IDLE;
else if (translation_required)
next_state = S_TRAN_PPN1;
else
next_state = S_TLB;
S_TRAN_PPN1:
next_state = translate_data_valid ? S_TRAN_PPN0 : S_TRAN_PPN1;
S_TRAN_PPN0:
next_state = translate_data_valid ? S_IDLE : S_TRAN_PPN0;
default:
next_state = S_IDLE;
endcase
end
reg [31:0] ppn1_data;
reg ppn1_valid;
reg [31:0] ppn0_data;
reg ppn0_valid;
always @ (posedge clk) begin
if (reset) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else begin
if (state == S_IDLE && launch_translation) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else if (state == S_TRAN_PPN1 && translate_data_valid) begin
ppn1_data <= request_data;
ppn1_valid <= 1;
end else if (state == S_TRAN_PPN0 && translate_data_valid) begin
ppn0_data <= request_data;
ppn0_valid <= 1;
end
end
end
always @ (*) begin
case (state)
S_TRAN_PPN1:
translate_addr = {ptbr[31:12], address[31:22], 2'b0};
S_TRAN_PPN0:
translate_addr = {ppn1_data[31:12], address[21:12], 2'b0};
default:
translate_addr = 32'b0;
endcase
end
assign translate_mem_enable = (state == S_TRAN_PPN1) || (state == S_TRAN_PPN0);
assign translation_complete = (state == S_IDLE);
/* Latch inferred. */
always @ (*) begin
if (translation_complete)
if (tlb_hit)
physical_address = {tlb_output_address[31:12], address[11:0]};
else
physical_address = {ppn0_data[31:12], address[11:0]};
end
/* TLB */
wire tlb_enable = (state == S_TLB);
tlb tlb(.clk(clk), .reset(reset), .flush(flush_tlb),
.vm_enable(vm_enable), .enable(tlb_enable),
.virtual_address(virtual_address), .physical_address(tlb_output_address),
.tlb_hit(tlb_hit), .translation_required(translation_required),
.translated_address(physical_address), .translation_complete(translation_complete));
endmodule |
module decode (
input [31:0] inst,
output [4:0] rs1,
output [4:0] rs2,
output [4:0] wd,
output reg [2:0] wb_sel,
output rf_wr_en,
output memory_request,
output memory_request_type,
output reg pcr_enable,
output reg [1:0] pcr_cmd
);
wire [6:0] opcode = inst[6:0];
assign rs1 = inst[26:22];
assign rs2 = inst[21:17];
assign wd = (opcode == `OPCODE_JAL) ? 5'd1 : inst[31:27];
assign rf_wr_en = (opcode == `OPCODE_OP ||
opcode == `OPCODE_OP_IMM ||
opcode == `OPCODE_LUI ||
opcode == `OPCODE_LOAD ||
opcode == `OPCODE_JAL ||
opcode == `OPCODE_JALR ||
opcode == `OPCODE_PCR);
assign memory_request = (opcode == `OPCODE_LOAD ||
opcode == `OPCODE_STORE);
assign memory_request_type = (opcode == `OPCODE_STORE) ?
`MEM_REQ_WRITE : `MEM_REQ_READ;
always @ (*) begin
case (opcode)
`OPCODE_OP, `OPCODE_OP_IMM, `OPCODE_LUI:
wb_sel = `WB_ALU;
`OPCODE_LOAD:
wb_sel = `WB_MEM;
`OPCODE_JAL, `OPCODE_JALR:
wb_sel = `WB_PC4;
`OPCODE_PCR:
wb_sel = `WB_PCR;
default:
wb_sel = 0;
endcase
end
always @ (*) begin
if (opcode == `OPCODE_PCR) begin
pcr_enable = 1;
/* funct3 map for cmd */
pcr_cmd = inst[8:7];
end else begin
pcr_enable = 0;
pcr_cmd = 2'b00;
end
end
endmodule |
module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
/* Loads by word addresses. Address 0x302c corresponds to 0x0c0b. */
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule |
module datapath (
input clk,
input reset,
input stall,
output [31:0] fetch_addr,
output fetch_request,
input fetch_data_valid,
output [31:0] dmem_addr,
output [31:0] dmem_write_data,
output [3:0] dmem_write_mask,
output dmem_request,
output dmem_request_type,
input dmem_data_valid,
input [31:0] request_data,
output [31:0] ptbr,
output vm_enable,
output flush_tlb
);
reg [31:0] inst;
reg [31:0] pc;
wire [1:0] next_pc_sel;
wire [2:0] wb_sel;
wire rf_wr_en;
wire interrupt;
wire [31:0] evec;
wire branch_taken;
wire [31:0] branch_target;
wire jump_taken;
wire [31:0] jump_target;
reg [31:0] fetch_pc;
always @ (*) begin
if (stall)
fetch_pc = pc;
else if (interrupt)
fetch_pc = evec;
else if (jump_taken)
fetch_pc = jump_target;
else if (branch_taken)
fetch_pc = branch_target;
else
fetch_pc = pc + 4;
end
assign fetch_addr = fetch_pc;
assign fetch_request = !reset;
always @ (posedge clk) begin
/* PC */
if (reset)
pc <= `PC_START;
else
pc <= fetch_pc;
end
always @ (posedge clk) begin
/* Instruction */
if (reset)
inst <= `INSTR_NOP;
else if (fetch_data_valid)
inst <= request_data;
end
/* DECODE and EXECUTE */
wire [4:0] ex_rs1;
wire [4:0] ex_rs2;
wire [4:0] ex_wd;
wire cp_enable;
wire [1:0] pcr_cmd;
decode d(.inst(inst),
.rs1(ex_rs1), .rs2(ex_rs2), .wd(ex_wd),
.wb_sel(wb_sel), .rf_wr_en(rf_wr_en),
.memory_request(dmem_request), .memory_request_type(dmem_request_type),
.pcr_enable(cp_enable), .pcr_cmd(pcr_cmd));
wire [31:0] rf_rd1;
wire [31:0] rf_rd2;
reg [31:0] rf_wdata;
regfile rf(.clk(clk), .reset(reset), .rd1(rf_rd1), .rd2(rf_rd2), .rs1(ex_rs1),
.rs2(ex_rs2), .wd(ex_wd), .w_data(rf_wdata), .w_enable(rf_wr_en),
.stall(stall));
wire [4:0] alu_sel;
wire [1:0] mul_sel;
wire [31:0] alu_op1;
wire [31:0] alu_op2;
alu_dec ad(.alu_sel(alu_sel), .mul_sel(mul_sel),
.op1(alu_op1), .op2(alu_op2),
.rs1(rf_rd1), .rs2(rf_rd2), .inst(inst));
wire [31:0] multiplier_result;
wire [31:0] alu_out;
wire alu_equal;
wire alu_less;
multiplier mul(.multiplier_result(multiplier_result),
.op1(alu_op1), .op2(alu_op2), .mul_sel(mul_sel));
alu alu(.alu_out(alu_out),
.op1(alu_op1), .op2(alu_op2), .multiplier_result(multiplier_result), .alu_sel(alu_sel));
branch_jump bj(.branch_taken(branch_taken), .branch_target(branch_target),
.jump(jump_taken), .jump_target(jump_target),
.inst(inst), .pc(pc), .rd1(rf_rd1), .alu_out(alu_out));
/* MEMORY and WRITEBACK */
wire [31:0] mem_data;
reg [31:0] load_data;
always @ (posedge clk) begin
if (reset)
load_data <= 32'b0;
else if (dmem_data_valid)
load_data <= request_data;
end
data_memory m(.inst(inst), .data(rf_rd2), .addr(alu_out),
.memory_addr(dmem_addr),
.write_data(dmem_write_data), .write_mask(dmem_write_mask),
.load_data(load_data), .output_data(mem_data));
wire [31:0] pcr_data;
control_processor cp(.clk(clk), .reset(reset), .stall(stall),
.inst(inst), .pc(pc),
.enable(cp_enable),
.pcr_write_data({1'b0, pcr_cmd} == `F3_MTPCR ? rf_rd2 : rf_rd1),
.pcr(ex_rs1), .cmd(pcr_cmd), .pcr_data(pcr_data),
.interrupt(interrupt), .evec(evec),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
always @ (*) begin
case (wb_sel)
`WB_ALU: rf_wdata = alu_out;
`WB_MEM: rf_wdata = mem_data;
`WB_PC4: rf_wdata = pc + 4;
`WB_PCR: rf_wdata = pcr_data;
default: rf_wdata = 32'b0;
endcase
end
endmodule |
module tlb (
input clk,
input reset,
input flush,
input vm_enable,
input enable,
input [31:0] virtual_address,
output reg [31:0] physical_address,
output reg tlb_hit,
output reg translation_required,
input [31:0] translated_address,
input translation_complete
);
localparam TLB_ENTRIES = 4;
reg [1:0] entry; /* Next one to replace */
reg [40:0] tlb [TLB_ENTRIES-1:0];
integer i, j;
always @ (posedge clk) begin
if (reset || flush) begin
for (j = 0; j < TLB_ENTRIES; j = j + 1) begin
tlb[j] = 41'b0;
end
entry = 0;
end
end
localparam S_CHECK = 0;
localparam S_WAIT = 1;
reg state;
reg next_state;
always @ (posedge clk) begin
if (reset)
state <= S_CHECK;
else
state <= next_state;
end
always @ (*) begin
case (state)
S_CHECK: begin
tlb_hit = 0;
/* Check each TLB entry for a match */
for (i = 0; i < TLB_ENTRIES; i = i + 1) begin
if (virtual_address[31:12] == tlb[i][39:20] && tlb[i][40]) begin
physical_address = {tlb[i][19:0], virtual_address[11:0]};
tlb_hit = 1;
end
end
translation_required = !tlb_hit && enable && vm_enable;
next_state = !translation_required ? S_CHECK : S_WAIT;
end
S_WAIT:
next_state = translation_complete ? S_CHECK : S_WAIT;
default:
next_state = S_CHECK;
endcase
end
always @ (*) begin
if (state == S_WAIT && translation_complete) begin
tlb[entry] = {1'b1, virtual_address[31:12], translated_address[31:12]};
entry = entry + 1;
end
end
endmodule |
module top (
input clk,
input reset
);
wire stall;
wire [31:0] fetch_addr;
wire fetch_request;
wire fetch_data_valid;
wire [31:0] memory_addr;
wire [31:0] write_data;
wire [3:0] write_mask;
wire memory_request;
wire memory_request_type;
wire memory_data_valid;
wire[31:0] request_data;
wire [31:0] ptbr;
wire vm_enable;
datapath dpath(.clk(clk), .reset(reset), .stall(stall),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid),
.request_data(request_data), .vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb));
memory_system ms(.clk(clk), .reset(reset), .stall(stall),
.request_data(request_data),
.vm_enable(vm_enable), .ptbr(ptbr), .flush_tlb(flush_tlb),
.fetch_addr(fetch_addr), .fetch_request(fetch_request), .fetch_data_valid(fetch_data_valid),
.dmem_addr(memory_addr), .dmem_write_data(write_data), .dmem_write_mask(write_mask),
.dmem_request(memory_request), .dmem_request_type(memory_request_type), .dmem_data_valid(memory_data_valid));
endmodule |
module regfile (
input clk,
input reset,
output [31:0] rd1,
output [31:0] rd2,
input [4:0] rs1,
input [4:0] rs2,
input [4:0] wd,
input [31:0] w_data,
input w_enable,
input stall);
/* Registers */
reg [31:0] registers[31:0];
always @ (posedge clk) begin
if (w_enable & !stall & wd != 0)
registers[wd] <= w_data;
end
/* Outputs */
assign rd1 = rs1 == 0 ? 32'b0 : registers[rs1];
assign rd2 = rs2 == 0 ? 32'b0 : registers[rs2];
endmodule |
module data_memory (
input [31:0] inst,
input [31:0] data,
input [31:0] addr,
output [31:0] memory_addr,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input [31:0] load_data,
output reg [31:0] output_data
);
wire [2:0] funct3 = inst[9:7];
wire [6:0] opcode = inst[6:0];
assign memory_addr = {addr[31:2], 2'b0};
reg [31:0] write_data_masked;
always @ (*) begin
case (funct3)
`F3_SB: write_data_masked = data & 32'hFF;
`F3_SH: write_data_masked = data & 32'hFFFF;
`F3_SW: write_data_masked = data & 32'hFFFFFFFF;
default: write_data_masked = 32'h0;
endcase
end
always @ (*) begin
case (addr[1:0])
2'b00: write_data = write_data_masked;
2'b01: write_data = write_data_masked << 8;
2'b10: write_data = write_data_masked << 16;
2'b11: write_data = write_data_masked << 24;
default: write_data = 32'b0;
endcase
end
always @ (*) begin
case (funct3)
`F3_SB: write_mask = 4'b1 << addr[1:0];
`F3_SH: write_mask = 4'b11 << addr[1:0];
`F3_SW: write_mask = 4'b1111;
default: write_mask = 0;
endcase
end
reg [31:0] load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB, `F3_LBU: case (addr[1:0])
2'b00: load_data_shifted = {24'b0, load_data[7:0]};
2'b01: load_data_shifted = {24'b0, load_data[15:8]};
2'b10: load_data_shifted = {24'b0, load_data[23:16]};
2'b11: load_data_shifted = {24'b0, load_data[31:24]};
default: load_data_shifted = 32'b0;
endcase
`F3_LH, `F3_LHU: case (addr[1:0])
2'b00: load_data_shifted = {16'b0, load_data[15:0]};
2'b10: load_data_shifted = {16'b0, load_data[31:16]};
default: load_data_shifted = 32'b0;
endcase
`F3_LW: load_data_shifted = load_data;
default: load_data_shifted = 32'b0;
endcase
end
wire [31:0] lds = load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB: output_data = lds[7] ? {24'hFFFFFF, lds[7:0]} : {24'h0, lds[7:0]};
`F3_LH: output_data = lds[15] ? {16'hFFFF, lds[15:0]} : {16'h0, lds[15:0]};
`F3_LW, `F3_LHU, `F3_LBU: output_data = lds;
default: output_data = 32'b0;
endcase
end
endmodule |
module alu (
output reg [31:0] alu_out,
input [31:0] op1,
input [31:0] op2,
input [31:0] multiplier_result,
input [4:0] alu_sel
);
always @ (*) begin
case (alu_sel)
`ALU_ADD: alu_out = op1 + op2;
`ALU_SLL: alu_out = op1 << op2;
`ALU_SLT: alu_out = $signed(op1) < $signed(op2) ? 1 : 0;
`ALU_SLTU: alu_out = op1 < op2 ? 1 : 0;
`ALU_XOR: alu_out = op1 ^ op2;
`ALU_SRL: alu_out = op1 >> op2;
`ALU_SRA: alu_out = $signed(op1) >>> op2;
`ALU_OR: alu_out = op1 | op2;
`ALU_AND: alu_out = op1 & op2;
`ALU_MUL: alu_out = multiplier_result;
`ALU_DIV: alu_out = $signed(op1) / $signed(op2);
`ALU_DIVU: alu_out = op1 / op2;
`ALU_REM: alu_out = $signed(op1) % $signed(op2);
`ALU_REMU: alu_out = op1 % op2;
`ALU_LUI: alu_out = op1 << 12;
`ALU_NONE: alu_out = 0;
endcase
end
endmodule |
module bshift_test;
parameter n=32;
reg instr_bit_25;
wire [11:0] imm_value={5'd0,3'd6,4'd0};
//reg [n-1:0] in;
//reg [n-1:0] out;
//reg [7:0] shiftby; // no. bits to be shifted
//reg [n-1:0] junk;
reg [n-1:0] Rm;
reg [n-1:0] Rs;
wire cin=1;
wire c_to_alu;
wire [n-1:0] operand2;
bshift #(32) bshift1(instr_bit_25,imm_value, Rm, Rs, operand2, cin, c_to_alu);
initial begin
instr_bit_25 = 1;
//imm_value =5 ;
Rm= {3'd3,29'd1};
Rs = 32'd100;
//cin = 1;
#2 $display("%b,%b",operand2, c_to_alu);
#5;
end
endmodule |
module mult_test;
parameter N = 7;
wire[N-1:0] result;
reg[N-1:0] Rn;
reg[N-1:0] Rs;
reg[N-1:0] Rm;
reg A;
multiplier#(N) multiplier1( A, Rn, Rs, Rm, result);
initial begin
Rn = 30;
Rs = 20;
Rm = 2;
A = 1;
#2 $display("(%d * %d) + %d = %d", Rm, Rs, Rn, result);
end
endmodule |
module system (
input clk,
input resetn,
output reg led1
);
// set this to 0 for better timing but less performance/MHz
parameter FAST_MEMORY = 1;
// 4096 32bit words = 16kB memory
parameter MEM_SIZE = 4096;
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
wire mem_la_read;
wire mem_la_write;
wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb;
picorv32 picorv32_core (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.mem_la_read (mem_la_read ),
.mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr ),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb)
);
reg [23:0] led_cnt = {24{1'b0}};
always @(posedge clk)
begin
led_cnt <= led_cnt - 1'b1;
if (led_cnt[23] == 1)
led1 <= 0;
else
led1 <= 1;
end
wire trap;
reg [7:0] out_byte;
reg [0:0] out_byte_en;
wire [0:0] trap_ila;
assign trap_ila[0] = trap;
ila_0 inst_ila_0 (.clk(clk), .probe0(out_byte), .probe1(trap_ila), .probe2(out_byte_en));
reg [31:0] memory [0:MEM_SIZE-1];
initial $readmemh("firmware.hex", memory);
reg [31:0] m_read_data;
reg m_read_en;
generate if (FAST_MEMORY) begin
always @(posedge clk) begin
mem_ready <= 1;
out_byte_en[0] <= 0;
mem_rdata <= memory[mem_la_addr >> 2];
if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
end
else
if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
out_byte_en[0] <= 1;
out_byte <= mem_la_wdata;
end
end
end else begin
always @(posedge clk) begin
m_read_en <= 0;
mem_ready <= mem_valid && !mem_ready && m_read_en;
m_read_data <= memory[mem_addr >> 2];
mem_rdata <= m_read_data;
out_byte_en[0] <= 0;
(* parallel_case *)
case (1)
mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
m_read_en <= 1;
end
mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
mem_ready <= 1;
end
mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h1000_0000: begin
out_byte_en[0] <= 1;
out_byte <= mem_wdata;
mem_ready <= 1;
end
endcase
end
end endgenerate
endmodule |
module sirv_plic_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_devices_0_0,
input io_devices_0_1,
input io_devices_0_2,
input io_devices_0_3,
input io_devices_0_4,
input io_devices_0_5,
input io_devices_0_6,
input io_devices_0_7,
input io_devices_0_8,
input io_devices_0_9,
input io_devices_0_10,
input io_devices_0_11,
input io_devices_0_12,
input io_devices_0_13,
input io_devices_0_14,
input io_devices_0_15,
output io_harts_0_0
);
wire plic_irq;
assign io_harts_0_0 = plic_irq;
localparam PLIC_IRQ_NUM = 17;// The number can be enlarged as long as not larger than 1024
wire [PLIC_IRQ_NUM-1:0] plic_irq_i = {
io_devices_0_15 ,
io_devices_0_14 ,
io_devices_0_13 ,
io_devices_0_12 ,
io_devices_0_11 ,
io_devices_0_10 ,
io_devices_0_9 ,
io_devices_0_8 ,
io_devices_0_7 ,
io_devices_0_6 ,
io_devices_0_5 ,
io_devices_0_4 ,
io_devices_0_3 ,
io_devices_0_2 ,
io_devices_0_1 ,
io_devices_0_0 ,
1'b0 };// The IRQ0 must be tied to zero
sirv_plic_man #(
.PLIC_PRIO_WIDTH (3),
.PLIC_IRQ_NUM (PLIC_IRQ_NUM),
.PLIC_IRQ_NUM_LOG2 (6),
.PLIC_ICB_RSP_FLOP (1),
.PLIC_IRQ_I_FLOP (1),
.PLIC_IRQ_O_FLOP (1)
) u_sirv_plic_man(
.clk (clk ),
.rst_n (rst_n ),
.icb_cmd_valid (i_icb_cmd_valid),
.icb_cmd_addr (i_icb_cmd_addr[24-1:0] ),
.icb_cmd_read (i_icb_cmd_read ),
.icb_cmd_wdata (i_icb_cmd_wdata),
.icb_rsp_ready (i_icb_rsp_ready),
.icb_rsp_valid (i_icb_rsp_valid),
.icb_cmd_ready (i_icb_cmd_ready),
.icb_rsp_rdata (i_icb_rsp_rdata),
.plic_irq_i (plic_irq_i),
.plic_irq_o (plic_irq )
);
endmodule |
module e203_subsys_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
input io_pads_bootrom_n_i_ival,
output io_pads_bootrom_n_o_oval,
output io_pads_bootrom_n_o_oe,
output io_pads_bootrom_n_o_ie,
output io_pads_bootrom_n_o_pue,
output io_pads_bootrom_n_o_ds,
input io_pads_aon_erst_n_i_ival,
output io_pads_aon_erst_n_o_oval,
output io_pads_aon_erst_n_o_oe,
output io_pads_aon_erst_n_o_ie,
output io_pads_aon_erst_n_o_pue,
output io_pads_aon_erst_n_o_ds,
input io_pads_aon_pmu_dwakeup_n_i_ival,
output io_pads_aon_pmu_dwakeup_n_o_oval,
output io_pads_aon_pmu_dwakeup_n_o_oe,
output io_pads_aon_pmu_dwakeup_n_o_ie,
output io_pads_aon_pmu_dwakeup_n_o_pue,
output io_pads_aon_pmu_dwakeup_n_o_ds,
input io_pads_aon_pmu_vddpaden_i_ival,
output io_pads_aon_pmu_vddpaden_o_oval,
output io_pads_aon_pmu_vddpaden_o_oe,
output io_pads_aon_pmu_vddpaden_o_ie,
output io_pads_aon_pmu_vddpaden_o_pue,
output io_pads_aon_pmu_vddpaden_o_ds,
input io_pads_aon_pmu_padrst_i_ival,
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_padrst_o_oe,
output io_pads_aon_pmu_padrst_o_ie,
output io_pads_aon_pmu_padrst_o_pue,
output io_pads_aon_pmu_padrst_o_ds,
input [`E203_HART_ID_W-1:0] core_mhartid,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
// * Bus cmd channel
output sysper_icb_cmd_valid,
input sysper_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysper_icb_cmd_addr,
output sysper_icb_cmd_read,
output [`E203_XLEN-1:0] sysper_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysper_icb_cmd_wmask,
//
// * Bus RSP channel
input sysper_icb_rsp_valid,
output sysper_icb_rsp_ready,
input sysper_icb_rsp_err ,
input [`E203_XLEN-1:0] sysper_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
//
// * Bus cmd channel
output sysfio_icb_cmd_valid,
input sysfio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysfio_icb_cmd_addr,
output sysfio_icb_cmd_read,
output [`E203_XLEN-1:0] sysfio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysfio_icb_cmd_wmask,
//
// * Bus RSP channel
input sysfio_icb_rsp_valid,
output sysfio_icb_rsp_ready,
input sysfio_icb_rsp_err ,
input [`E203_XLEN-1:0] sysfio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
// * Bus cmd channel
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
// * Bus RSP channel
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err ,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
`endif//}
input [32-1:0] io_pads_gpioA_i_ival,
output [32-1:0] io_pads_gpioA_o_oval,
output [32-1:0] io_pads_gpioA_o_oe,
input [32-1:0] io_pads_gpioB_i_ival,
output [32-1:0] io_pads_gpioB_o_oval,
output [32-1:0] io_pads_gpioB_o_oe,
input io_pads_qspi0_sck_i_ival,
output io_pads_qspi0_sck_o_oval,
output io_pads_qspi0_sck_o_oe,
input io_pads_qspi0_dq_0_i_ival,
output io_pads_qspi0_dq_0_o_oval,
output io_pads_qspi0_dq_0_o_oe,
input io_pads_qspi0_dq_1_i_ival,
output io_pads_qspi0_dq_1_o_oval,
output io_pads_qspi0_dq_1_o_oe,
input io_pads_qspi0_dq_2_i_ival,
output io_pads_qspi0_dq_2_o_oval,
output io_pads_qspi0_dq_2_o_oe,
input io_pads_qspi0_dq_3_i_ival,
output io_pads_qspi0_dq_3_o_oval,
output io_pads_qspi0_dq_3_o_oe,
input io_pads_qspi0_cs_0_i_ival,
output io_pads_qspi0_cs_0_o_oval,
output io_pads_qspi0_cs_0_o_oe,
input io_pads_jtag_TCK_i_ival,
output io_pads_jtag_TCK_o_oval,
output io_pads_jtag_TCK_o_oe,
output io_pads_jtag_TCK_o_ie,
output io_pads_jtag_TCK_o_pue,
output io_pads_jtag_TCK_o_ds,
input io_pads_jtag_TMS_i_ival,
output io_pads_jtag_TMS_o_oval,
output io_pads_jtag_TMS_o_oe,
output io_pads_jtag_TMS_o_ie,
output io_pads_jtag_TMS_o_pue,
output io_pads_jtag_TMS_o_ds,
input io_pads_jtag_TDI_i_ival,
output io_pads_jtag_TDI_o_oval,
output io_pads_jtag_TDI_o_oe,
output io_pads_jtag_TDI_o_ie,
output io_pads_jtag_TDI_o_pue,
output io_pads_jtag_TDI_o_ds,
input io_pads_jtag_TDO_i_ival,
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
output io_pads_jtag_TDO_o_ie,
output io_pads_jtag_TDO_o_pue,
output io_pads_jtag_TDO_o_ds,
input io_pads_jtag_TRST_n_i_ival,
output io_pads_jtag_TRST_n_o_oval,
output io_pads_jtag_TRST_n_o_oe,
output io_pads_jtag_TRST_n_o_ie,
output io_pads_jtag_TRST_n_o_pue,
output io_pads_jtag_TRST_n_o_ds,
input test_iso_override,
input test_mode
);
wire hfclk;// The PLL generated high-speed clock
wire hfclkrst;// The reset signal to disable PLL
wire corerst;
///////////////////////////////////////
wire [`E203_HART_NUM-1:0] dbg_irq;
wire [`E203_PC_SIZE-1:0] cmt_dpc;
wire cmt_dpc_ena;
wire [3-1:0] cmt_dcause;
wire cmt_dcause_ena;
wire dbg_irq_r;
wire wr_dcsr_ena;
wire wr_dpc_ena ;
wire wr_dscratch_ena;
wire [32-1:0] wr_csr_nxt;
wire [32-1:0] dcsr_r ;
wire [`E203_PC_SIZE-1:0] dpc_r ;
wire [32-1:0] dscratch_r;
wire dbg_mode;
wire dbg_halt_r;
wire dbg_step_r;
wire dbg_ebreakm_r;
wire dbg_stopcycle;
wire inspect_mode;
wire inspect_por_rst;
wire inspect_32k_clk;
wire inspect_pc_29b;
wire inspect_dbg_irq;
wire inspect_jtag_clk;
wire core_csr_clk;
wire dm_icb_cmd_valid;
wire dm_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr;
wire dm_icb_cmd_read;
wire [`E203_XLEN-1:0] dm_icb_cmd_wdata;
//
wire dm_icb_rsp_valid;
wire dm_icb_rsp_ready;
wire [`E203_XLEN-1:0] dm_icb_rsp_rdata;
wire aon_wdg_irq_a ;
wire aon_rtc_irq_a ;
wire aon_rtcToggle_a ;
wire aon_icb_cmd_valid;
wire aon_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] aon_icb_cmd_addr;
wire aon_icb_cmd_read;
wire [`E203_XLEN-1:0] aon_icb_cmd_wdata;
//
wire aon_icb_rsp_valid;
wire aon_icb_rsp_ready;
wire [`E203_XLEN-1:0] aon_icb_rsp_rdata;
wire [`E203_PC_SIZE-1:0] pc_rtvec;
e203_subsys_main u_e203_subsys_main(
.pc_rtvec (pc_rtvec),
.inspect_mode (inspect_mode ),
.inspect_por_rst (inspect_por_rst),
.inspect_32k_clk (inspect_32k_clk),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_jtag_clk(inspect_jtag_clk),
.core_csr_clk (core_csr_clk ),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq[0]),
.aon_wdg_irq_a (aon_wdg_irq_a ),
.aon_rtc_irq_a (aon_rtc_irq_a ),
.aon_rtcToggle_a (aon_rtcToggle_a ),
.aon_icb_cmd_valid (aon_icb_cmd_valid ),
.aon_icb_cmd_ready (aon_icb_cmd_ready ),
.aon_icb_cmd_addr (aon_icb_cmd_addr ),
.aon_icb_cmd_read (aon_icb_cmd_read ),
.aon_icb_cmd_wdata (aon_icb_cmd_wdata ),
.aon_icb_rsp_valid (aon_icb_rsp_valid ),
.aon_icb_rsp_ready (aon_icb_rsp_ready ),
.aon_icb_rsp_err (1'b0 ),
.aon_icb_rsp_rdata (aon_icb_rsp_rdata ),
.dm_icb_cmd_valid (dm_icb_cmd_valid),
.dm_icb_cmd_ready (dm_icb_cmd_ready),
.dm_icb_cmd_addr (dm_icb_cmd_addr ),
.dm_icb_cmd_read (dm_icb_cmd_read ),
.dm_icb_cmd_wdata (dm_icb_cmd_wdata),
.dm_icb_rsp_valid (dm_icb_rsp_valid),
.dm_icb_rsp_ready (dm_icb_rsp_ready),
.dm_icb_rsp_rdata (dm_icb_rsp_rdata),
.io_pads_gpioA_i_ival (io_pads_gpioA_i_ival),
.io_pads_gpioA_o_oval (io_pads_gpioA_o_oval),
.io_pads_gpioA_o_oe (io_pads_gpioA_o_oe),
.io_pads_gpioB_i_ival (io_pads_gpioB_i_ival),
.io_pads_gpioB_o_oval (io_pads_gpioB_o_oval),
.io_pads_gpioB_o_oe (io_pads_gpioB_o_oe),
.io_pads_qspi0_sck_i_ival (io_pads_qspi0_sck_i_ival),
.io_pads_qspi0_sck_o_oval (io_pads_qspi0_sck_o_oval),
.io_pads_qspi0_sck_o_oe (io_pads_qspi0_sck_o_oe),
.io_pads_qspi0_dq_0_i_ival (io_pads_qspi0_dq_0_i_ival),
.io_pads_qspi0_dq_0_o_oval (io_pads_qspi0_dq_0_o_oval),
.io_pads_qspi0_dq_0_o_oe (io_pads_qspi0_dq_0_o_oe),
.io_pads_qspi0_dq_1_i_ival (io_pads_qspi0_dq_1_i_ival),
.io_pads_qspi0_dq_1_o_oval (io_pads_qspi0_dq_1_o_oval),
.io_pads_qspi0_dq_1_o_oe (io_pads_qspi0_dq_1_o_oe),
.io_pads_qspi0_dq_2_i_ival (io_pads_qspi0_dq_2_i_ival),
.io_pads_qspi0_dq_2_o_oval (io_pads_qspi0_dq_2_o_oval),
.io_pads_qspi0_dq_2_o_oe (io_pads_qspi0_dq_2_o_oe),
.io_pads_qspi0_dq_3_i_ival (io_pads_qspi0_dq_3_i_ival),
.io_pads_qspi0_dq_3_o_oval (io_pads_qspi0_dq_3_o_oval),
.io_pads_qspi0_dq_3_o_oe (io_pads_qspi0_dq_3_o_oe),
.io_pads_qspi0_cs_0_i_ival (io_pads_qspi0_cs_0_i_ival),
.io_pads_qspi0_cs_0_o_oval (io_pads_qspi0_cs_0_o_oval),
.io_pads_qspi0_cs_0_o_oe (io_pads_qspi0_cs_0_o_oe),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_addr (sysper_icb_cmd_addr ),
.sysper_icb_cmd_read (sysper_icb_cmd_read ),
.sysper_icb_cmd_wdata (sysper_icb_cmd_wdata),
.sysper_icb_cmd_wmask (sysper_icb_cmd_wmask),
.sysper_icb_rsp_valid (sysper_icb_rsp_valid),
.sysper_icb_rsp_ready (sysper_icb_rsp_ready),
.sysper_icb_rsp_err (sysper_icb_rsp_err ),
.sysper_icb_rsp_rdata (sysper_icb_rsp_rdata),
.sysfio_icb_cmd_valid (sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready (sysfio_icb_cmd_ready),
.sysfio_icb_cmd_addr (sysfio_icb_cmd_addr ),
.sysfio_icb_cmd_read (sysfio_icb_cmd_read ),
.sysfio_icb_cmd_wdata (sysfio_icb_cmd_wdata),
.sysfio_icb_cmd_wmask (sysfio_icb_cmd_wmask),
.sysfio_icb_rsp_valid (sysfio_icb_rsp_valid),
.sysfio_icb_rsp_ready (sysfio_icb_rsp_ready),
.sysfio_icb_rsp_err (sysfio_icb_rsp_err ),
.sysfio_icb_rsp_rdata (sysfio_icb_rsp_rdata),
.sysmem_icb_cmd_valid (sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready (sysmem_icb_cmd_ready),
.sysmem_icb_cmd_addr (sysmem_icb_cmd_addr ),
.sysmem_icb_cmd_read (sysmem_icb_cmd_read ),
.sysmem_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.sysmem_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.sysmem_icb_rsp_valid (sysmem_icb_rsp_valid),
.sysmem_icb_rsp_ready (sysmem_icb_rsp_ready),
.sysmem_icb_rsp_err (sysmem_icb_rsp_err ),
.sysmem_icb_rsp_rdata (sysmem_icb_rsp_rdata),
.test_mode (test_mode),
.ls_clk (lfextclk),
.hfclk (hfclk ),
.hfclkrst (hfclkrst),
.corerst (corerst)
);
sirv_debug_module # (
`ifdef E203_DEBUG_HAS_JTAG //{
.SUPPORT_JTAG_DTM (1),
`else//}{
.SUPPORT_JTAG_DTM (0),
`endif//}
.ASYNC_FF_LEVELS (`E203_ASYNC_FF_LEVELS),
.HART_NUM (`E203_HART_NUM),
.PC_SIZE (`E203_PC_SIZE),
.HART_ID_W(`E203_HART_ID_W)
) u_sirv_debug_module(
.inspect_jtag_clk (inspect_jtag_clk),
.test_mode (test_mode ),
.core_csr_clk (core_csr_clk),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (io_pads_jtag_TCK_o_oval ),
.io_pads_jtag_TCK_o_oe (io_pads_jtag_TCK_o_oe ),
.io_pads_jtag_TCK_o_ie (io_pads_jtag_TCK_o_ie ),
.io_pads_jtag_TCK_o_pue (io_pads_jtag_TCK_o_pue ),
.io_pads_jtag_TCK_o_ds (io_pads_jtag_TCK_o_ds ),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (io_pads_jtag_TMS_o_oval ),
.io_pads_jtag_TMS_o_oe (io_pads_jtag_TMS_o_oe ),
.io_pads_jtag_TMS_o_ie (io_pads_jtag_TMS_o_ie ),
.io_pads_jtag_TMS_o_pue (io_pads_jtag_TMS_o_pue ),
.io_pads_jtag_TMS_o_ds (io_pads_jtag_TMS_o_ds ),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (io_pads_jtag_TDI_o_oval ),
.io_pads_jtag_TDI_o_oe (io_pads_jtag_TDI_o_oe ),
.io_pads_jtag_TDI_o_ie (io_pads_jtag_TDI_o_ie ),
.io_pads_jtag_TDI_o_pue (io_pads_jtag_TDI_o_pue ),
.io_pads_jtag_TDI_o_ds (io_pads_jtag_TDI_o_ds ),
.io_pads_jtag_TDO_i_ival (io_pads_jtag_TDO_i_ival ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (io_pads_jtag_TDO_o_ie ),
.io_pads_jtag_TDO_o_pue (io_pads_jtag_TDO_o_pue ),
.io_pads_jtag_TDO_o_ds (io_pads_jtag_TDO_o_ds ),
.io_pads_jtag_TRST_n_i_ival (io_pads_jtag_TRST_n_i_ival ),
.io_pads_jtag_TRST_n_o_oval (io_pads_jtag_TRST_n_o_oval ),
.io_pads_jtag_TRST_n_o_oe (io_pads_jtag_TRST_n_o_oe ),
.io_pads_jtag_TRST_n_o_ie (io_pads_jtag_TRST_n_o_ie ),
.io_pads_jtag_TRST_n_o_pue (io_pads_jtag_TRST_n_o_pue ),
.io_pads_jtag_TRST_n_o_ds (io_pads_jtag_TRST_n_o_ds ),
.i_icb_cmd_valid (dm_icb_cmd_valid),
.i_icb_cmd_ready (dm_icb_cmd_ready),
.i_icb_cmd_addr (dm_icb_cmd_addr[11:0] ),
.i_icb_cmd_read (dm_icb_cmd_read ),
.i_icb_cmd_wdata (dm_icb_cmd_wdata),
.i_icb_rsp_valid (dm_icb_rsp_valid),
.i_icb_rsp_ready (dm_icb_rsp_ready),
.i_icb_rsp_rdata (dm_icb_rsp_rdata),
.o_dbg_irq (dbg_irq),
.o_ndreset (),
.o_fullreset (),
.hfclk (hfclk),
.corerst (corerst)
);
sirv_aon_top u_sirv_aon_top(
.pc_rtvec (pc_rtvec),
.jtagpwd_iso (),// Currently not used
.inspect_mode (inspect_mode ),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_por_rst (inspect_por_rst ),
.inspect_32k_clk (inspect_32k_clk ),
.inspect_dbg_irq (inspect_dbg_irq ),
.i_icb_cmd_valid (aon_icb_cmd_valid),
.i_icb_cmd_ready (aon_icb_cmd_ready),
.i_icb_cmd_addr (aon_icb_cmd_addr ),
.i_icb_cmd_read (aon_icb_cmd_read ),
.i_icb_cmd_wdata (aon_icb_cmd_wdata),
.i_icb_rsp_valid (aon_icb_rsp_valid),
.i_icb_rsp_ready (aon_icb_rsp_ready),
.i_icb_rsp_rdata (aon_icb_rsp_rdata),
.aon_wdg_irq (aon_wdg_irq_a ),
.aon_rtc_irq (aon_rtc_irq_a ),
.aon_rtcToggle (aon_rtcToggle_a ),
.test_mode (test_mode ),
.test_iso_override (test_iso_override ),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (io_pads_aon_erst_n_o_oval ),
.io_pads_aon_erst_n_o_oe (io_pads_aon_erst_n_o_oe ),
.io_pads_aon_erst_n_o_ie (io_pads_aon_erst_n_o_ie ),
.io_pads_aon_erst_n_o_pue (io_pads_aon_erst_n_o_pue ),
.io_pads_aon_erst_n_o_ds (io_pads_aon_erst_n_o_ds ),
.io_pads_aon_pmu_vddpaden_i_ival (io_pads_aon_pmu_vddpaden_i_ival ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (io_pads_aon_pmu_vddpaden_o_oe ),
.io_pads_aon_pmu_vddpaden_o_ie (io_pads_aon_pmu_vddpaden_o_ie ),
.io_pads_aon_pmu_vddpaden_o_pue (io_pads_aon_pmu_vddpaden_o_pue ),
.io_pads_aon_pmu_vddpaden_o_ds (io_pads_aon_pmu_vddpaden_o_ds ),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_aon_pmu_dwakeup_n_o_oe (io_pads_aon_pmu_dwakeup_n_o_oe ),
.io_pads_aon_pmu_dwakeup_n_o_ie (io_pads_aon_pmu_dwakeup_n_o_ie ),
.io_pads_aon_pmu_dwakeup_n_o_pue (io_pads_aon_pmu_dwakeup_n_o_pue ),
.io_pads_aon_pmu_dwakeup_n_o_ds (io_pads_aon_pmu_dwakeup_n_o_ds ),
.io_pads_aon_pmu_padrst_i_ival (io_pads_aon_pmu_padrst_i_ival ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (io_pads_aon_pmu_padrst_o_oe ),
.io_pads_aon_pmu_padrst_o_ie (io_pads_aon_pmu_padrst_o_ie ),
.io_pads_aon_pmu_padrst_o_pue (io_pads_aon_pmu_padrst_o_pue ),
.io_pads_aon_pmu_padrst_o_ds (io_pads_aon_pmu_padrst_o_ds ),
.io_pads_jtagpwd_n_i_ival (1'b1),// Currently not used
.io_pads_jtagpwd_n_o_oval (),
.io_pads_jtagpwd_n_o_oe (),
.io_pads_jtagpwd_n_o_ie (),
.io_pads_jtagpwd_n_o_pue (),
.io_pads_jtagpwd_n_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (io_pads_bootrom_n_o_oval),
.io_pads_bootrom_n_o_oe (io_pads_bootrom_n_o_oe ),
.io_pads_bootrom_n_o_ie (io_pads_bootrom_n_o_ie ),
.io_pads_bootrom_n_o_pue (io_pads_bootrom_n_o_pue ),
.io_pads_bootrom_n_o_ds (io_pads_bootrom_n_o_ds ),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival),
.hfclkrst (hfclkrst),
.corerst (corerst)
);
endmodule |
module e203_subsys_main(
output core_csr_clk,
output hfxoscen,// The signal to enable the crystal pad generated clock
output inspect_pc_29b ,
output inspect_dbg_irq ,
input inspect_mode,
input inspect_por_rst,
input inspect_32k_clk,
input inspect_jtag_clk,
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// With the interface to debug module
//
// The interface with commit stage
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_irq_a,
output dbg_irq_r,
// The interface with CSR control
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
///////////////////////////////////////
input [`E203_HART_ID_W-1:0] core_mhartid,
input aon_wdg_irq_a,
input aon_rtc_irq_a,
input aon_rtcToggle_a,
output aon_icb_cmd_valid,
input aon_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] aon_icb_cmd_addr,
output aon_icb_cmd_read,
output [`E203_XLEN-1:0] aon_icb_cmd_wdata,
//
input aon_icb_rsp_valid,
output aon_icb_rsp_ready,
input aon_icb_rsp_err,
input [`E203_XLEN-1:0] aon_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output dm_icb_cmd_valid,
input dm_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr,
output dm_icb_cmd_read,
output [`E203_XLEN-1:0] dm_icb_cmd_wdata,
//
input dm_icb_rsp_valid,
output dm_icb_rsp_ready,
input [`E203_XLEN-1:0] dm_icb_rsp_rdata,
input [32-1:0] io_pads_gpioA_i_ival,
output [32-1:0] io_pads_gpioA_o_oval,
output [32-1:0] io_pads_gpioA_o_oe,
input [32-1:0] io_pads_gpioB_i_ival,
output [32-1:0] io_pads_gpioB_o_oval,
output [32-1:0] io_pads_gpioB_o_oe,
input io_pads_qspi0_sck_i_ival,
output io_pads_qspi0_sck_o_oval,
output io_pads_qspi0_sck_o_oe,
input io_pads_qspi0_dq_0_i_ival,
output io_pads_qspi0_dq_0_o_oval,
output io_pads_qspi0_dq_0_o_oe,
input io_pads_qspi0_dq_1_i_ival,
output io_pads_qspi0_dq_1_o_oval,
output io_pads_qspi0_dq_1_o_oe,
input io_pads_qspi0_dq_2_i_ival,
output io_pads_qspi0_dq_2_o_oval,
output io_pads_qspi0_dq_2_o_oe,
input io_pads_qspi0_dq_3_i_ival,
output io_pads_qspi0_dq_3_o_oval,
output io_pads_qspi0_dq_3_o_oe,
input io_pads_qspi0_cs_0_i_ival,
output io_pads_qspi0_cs_0_o_oval,
output io_pads_qspi0_cs_0_o_oe,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
// * Bus cmd channel
output sysper_icb_cmd_valid,
input sysper_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysper_icb_cmd_addr,
output sysper_icb_cmd_read,
output [`E203_XLEN-1:0] sysper_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysper_icb_cmd_wmask,
//
// * Bus RSP channel
input sysper_icb_rsp_valid,
output sysper_icb_rsp_ready,
input sysper_icb_rsp_err ,
input [`E203_XLEN-1:0] sysper_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
//
// * Bus cmd channel
output sysfio_icb_cmd_valid,
input sysfio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysfio_icb_cmd_addr,
output sysfio_icb_cmd_read,
output [`E203_XLEN-1:0] sysfio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysfio_icb_cmd_wmask,
//
// * Bus RSP channel
input sysfio_icb_rsp_valid,
output sysfio_icb_rsp_ready,
input sysfio_icb_rsp_err ,
input [`E203_XLEN-1:0] sysfio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
// * Bus cmd channel
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
// * Bus RSP channel
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err ,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
`endif//}
input test_mode,
input ls_clk,
input corerst, // The original async reset
input hfclkrst, // The original async reset
input hfextclk,// The original clock from crystal
output hfclk // The generated clock by HCLKGEN
);
wire [31:0] inspect_pc;
wire inspect_mem_cmd_valid;
wire inspect_mem_cmd_ready;
wire inspect_mem_rsp_valid;
wire inspect_mem_rsp_ready;
wire inspect_core_clk;
wire inspect_pll_clk;
wire inspect_16m_clk;
assign inspect_pc_29b = inspect_pc[29];
wire [32-1:0] gpioA_o_oval ;
wire [32-1:0] gpioA_o_oe ;
// The GPIO are reused for inspect mode, in which the GPIO
// is forced to be an output
assign io_pads_gpioA_o_oe[0] = inspect_mode ? 1'b1 : gpioA_o_oe[0];
assign io_pads_gpioA_o_oe[1] = inspect_mode ? 1'b1 : gpioA_o_oe[1];
assign io_pads_gpioA_o_oe[2] = inspect_mode ? 1'b1 : gpioA_o_oe[2];
assign io_pads_gpioA_o_oe[3] = inspect_mode ? 1'b1 : gpioA_o_oe[3];
assign io_pads_gpioA_o_oe[4] = inspect_mode ? 1'b1 : gpioA_o_oe[4];
assign io_pads_gpioA_o_oe[5] = inspect_mode ? 1'b1 : gpioA_o_oe[5];
assign io_pads_gpioA_o_oe[6] = inspect_mode ? 1'b1 : gpioA_o_oe[6];
assign io_pads_gpioA_o_oe[7] = inspect_mode ? 1'b1 : gpioA_o_oe[7];
assign io_pads_gpioA_o_oe[8] = inspect_mode ? 1'b1 : gpioA_o_oe[8];
assign io_pads_gpioA_o_oe[9] = inspect_mode ? 1'b1 : gpioA_o_oe[9];
assign io_pads_gpioA_o_oe[10] = inspect_mode ? 1'b1 : gpioA_o_oe[10];
assign io_pads_gpioA_o_oe[11] = inspect_mode ? 1'b1 : gpioA_o_oe[11];
assign io_pads_gpioA_o_oe[12] = inspect_mode ? 1'b1 : gpioA_o_oe[12];
assign io_pads_gpioA_o_oe[13] = inspect_mode ? 1'b1 : gpioA_o_oe[13];
assign io_pads_gpioA_o_oe[14] = inspect_mode ? 1'b1 : gpioA_o_oe[14];
assign io_pads_gpioA_o_oe[15] = inspect_mode ? 1'b1 : gpioA_o_oe[15];
assign io_pads_gpioA_o_oe[16] = inspect_mode ? 1'b1 : gpioA_o_oe[16];
assign io_pads_gpioA_o_oe[17] = inspect_mode ? 1'b1 : gpioA_o_oe[17];
assign io_pads_gpioA_o_oe[18] = inspect_mode ? 1'b1 : gpioA_o_oe[18];
assign io_pads_gpioA_o_oe[19] = inspect_mode ? 1'b1 : gpioA_o_oe[19];
assign io_pads_gpioA_o_oe[20] = inspect_mode ? 1'b1 : gpioA_o_oe[20];
assign io_pads_gpioA_o_oe[21] = inspect_mode ? 1'b1 : gpioA_o_oe[21];
assign io_pads_gpioA_o_oe[22] = inspect_mode ? 1'b1 : gpioA_o_oe[22];
assign io_pads_gpioA_o_oe[23] = inspect_mode ? 1'b1 : gpioA_o_oe[23];
assign io_pads_gpioA_o_oe[24] = inspect_mode ? 1'b1 : gpioA_o_oe[24];
assign io_pads_gpioA_o_oe[25] = inspect_mode ? 1'b1 : gpioA_o_oe[25];
assign io_pads_gpioA_o_oe[26] = inspect_mode ? 1'b1 : gpioA_o_oe[26];
assign io_pads_gpioA_o_oe[27] = inspect_mode ? 1'b1 : gpioA_o_oe[27];
assign io_pads_gpioA_o_oe[28] = inspect_mode ? 1'b1 : gpioA_o_oe[28];
assign io_pads_gpioA_o_oe[29] = inspect_mode ? 1'b1 : gpioA_o_oe[29];
assign io_pads_gpioA_o_oe[30] = inspect_mode ? 1'b1 : gpioA_o_oe[30];
assign io_pads_gpioA_o_oe[31] = inspect_mode ? 1'b1 : gpioA_o_oe[31];
assign io_pads_gpioA_o_oval[0] = inspect_mode ? inspect_pc[0] : gpioA_o_oval[0];
assign io_pads_gpioA_o_oval[1] = inspect_mode ? inspect_pc[1] : gpioA_o_oval[1];
assign io_pads_gpioA_o_oval[2] = inspect_mode ? inspect_pc[2] : gpioA_o_oval[2];
assign io_pads_gpioA_o_oval[3] = inspect_mode ? inspect_pc[3] : gpioA_o_oval[3];
assign io_pads_gpioA_o_oval[4] = inspect_mode ? inspect_pc[4] : gpioA_o_oval[4];
assign io_pads_gpioA_o_oval[5] = inspect_mode ? inspect_pc[5] : gpioA_o_oval[5];
assign io_pads_gpioA_o_oval[6] = inspect_mode ? inspect_pc[6] : gpioA_o_oval[6];
assign io_pads_gpioA_o_oval[7] = inspect_mode ? inspect_pc[7] : gpioA_o_oval[7];
assign io_pads_gpioA_o_oval[8] = inspect_mode ? inspect_pc[8] : gpioA_o_oval[8];
assign io_pads_gpioA_o_oval[9] = inspect_mode ? inspect_pc[9] : gpioA_o_oval[9];
assign io_pads_gpioA_o_oval[10] = inspect_mode ? inspect_pc[10] : gpioA_o_oval[10];
assign io_pads_gpioA_o_oval[11] = inspect_mode ? inspect_pc[11] : gpioA_o_oval[11];
assign io_pads_gpioA_o_oval[12] = inspect_mode ? inspect_pc[12] : gpioA_o_oval[12];
assign io_pads_gpioA_o_oval[13] = inspect_mode ? inspect_pc[13] : gpioA_o_oval[13];
assign io_pads_gpioA_o_oval[14] = inspect_mode ? inspect_pc[14] : gpioA_o_oval[14];
assign io_pads_gpioA_o_oval[15] = inspect_mode ? inspect_pc[15] : gpioA_o_oval[15];
assign io_pads_gpioA_o_oval[16] = inspect_mode ? inspect_pc[16] : gpioA_o_oval[16];
assign io_pads_gpioA_o_oval[17] = inspect_mode ? inspect_pc[17] : gpioA_o_oval[17];
assign io_pads_gpioA_o_oval[18] = inspect_mode ? inspect_pc[18] : gpioA_o_oval[18];
assign io_pads_gpioA_o_oval[19] = inspect_mode ? inspect_pc[19] : gpioA_o_oval[19];
assign io_pads_gpioA_o_oval[20] = inspect_mode ? inspect_pc[20] : gpioA_o_oval[20];
assign io_pads_gpioA_o_oval[21] = inspect_mode ? inspect_pc[21] : gpioA_o_oval[21];
assign io_pads_gpioA_o_oval[22] = inspect_mode ? inspect_mem_cmd_valid : gpioA_o_oval[22];
assign io_pads_gpioA_o_oval[23] = inspect_mode ? inspect_mem_cmd_ready : gpioA_o_oval[23];
assign io_pads_gpioA_o_oval[24] = inspect_mode ? inspect_mem_rsp_valid : gpioA_o_oval[24];
assign io_pads_gpioA_o_oval[25] = inspect_mode ? inspect_mem_rsp_ready : gpioA_o_oval[25];
assign io_pads_gpioA_o_oval[26] = inspect_mode ? inspect_jtag_clk : gpioA_o_oval[26];
assign io_pads_gpioA_o_oval[27] = inspect_mode ? inspect_core_clk : gpioA_o_oval[27];
assign io_pads_gpioA_o_oval[28] = inspect_mode ? inspect_por_rst : gpioA_o_oval[28];
assign io_pads_gpioA_o_oval[29] = inspect_mode ? inspect_32k_clk : gpioA_o_oval[29];
assign io_pads_gpioA_o_oval[30] = inspect_mode ? inspect_16m_clk : gpioA_o_oval[30];
assign io_pads_gpioA_o_oval[31] = inspect_mode ? inspect_pll_clk : gpioA_o_oval[31];
//This is to reset the main domain
wire main_rst;
sirv_ResetCatchAndSync_2 u_main_ResetCatchAndSync_2_1 (
.test_mode(test_mode),
.clock(hfclk),
.reset(corerst),
.io_sync_reset(main_rst)
);
wire main_rst_n = ~main_rst;
wire pllbypass ;
wire pll_RESET ;
wire pll_ASLEEP ;
wire [1:0] pll_OD;
wire [7:0] pll_M;
wire [4:0] pll_N;
wire plloutdivby1;
wire [5:0] plloutdiv;
e203_subsys_hclkgen u_e203_subsys_hclkgen(
.test_mode (test_mode),
.hfclkrst (hfclkrst ),
.hfextclk (hfextclk ),
.pllbypass (pllbypass ),
.pll_RESET (pll_RESET ),
.pll_ASLEEP (pll_ASLEEP ),
.pll_OD (pll_OD),
.pll_M (pll_M ),
.pll_N (pll_N ),
.plloutdivby1(plloutdivby1),
.plloutdiv (plloutdiv ),
.inspect_pll_clk(inspect_pll_clk),
.inspect_16m_clk(inspect_16m_clk),
.hfclk (hfclk ) // The generated clock by this module
);
wire tcm_ds = 1'b0;// Currently we dont support it
wire tcm_sd = 1'b0;// Currently we dont support it
`ifndef E203_HAS_LOCKSTEP//{
wire core_rst_n = main_rst_n;
wire bus_rst_n = main_rst_n;
wire per_rst_n = main_rst_n;
`endif//}
wire ppi_icb_cmd_valid;
wire ppi_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr;
wire ppi_icb_cmd_read;
wire [`E203_XLEN-1:0] ppi_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask;
wire ppi_icb_rsp_valid;
wire ppi_icb_rsp_ready;
wire ppi_icb_rsp_err ;
wire [`E203_XLEN-1:0] ppi_icb_rsp_rdata;
wire clint_icb_cmd_valid;
wire clint_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr;
wire clint_icb_cmd_read;
wire [`E203_XLEN-1:0] clint_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] clint_icb_cmd_wmask;
wire clint_icb_rsp_valid;
wire clint_icb_rsp_ready;
wire clint_icb_rsp_err ;
wire [`E203_XLEN-1:0] clint_icb_rsp_rdata;
wire plic_icb_cmd_valid;
wire plic_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr;
wire plic_icb_cmd_read;
wire [`E203_XLEN-1:0] plic_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] plic_icb_cmd_wmask;
wire plic_icb_rsp_valid;
wire plic_icb_rsp_ready;
wire plic_icb_rsp_err ;
wire [`E203_XLEN-1:0] plic_icb_rsp_rdata;
`ifdef E203_HAS_FIO //{
wire fio_icb_cmd_valid;
wire fio_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr;
wire fio_icb_cmd_read;
wire [`E203_XLEN-1:0] fio_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] fio_icb_cmd_wmask;
wire fio_icb_rsp_valid;
wire fio_icb_rsp_ready;
wire fio_icb_rsp_err ;
wire [`E203_XLEN-1:0] fio_icb_rsp_rdata;
assign sysfio_icb_cmd_valid = fio_icb_cmd_valid;
assign fio_icb_cmd_ready = sysfio_icb_cmd_ready;
assign sysfio_icb_cmd_addr = fio_icb_cmd_addr ;
assign sysfio_icb_cmd_read = fio_icb_cmd_read ;
assign sysfio_icb_cmd_wdata = fio_icb_cmd_wdata;
assign sysfio_icb_cmd_wmask = fio_icb_cmd_wmask;
assign fio_icb_rsp_valid = sysfio_icb_rsp_valid;
assign sysfio_icb_rsp_ready = fio_icb_rsp_ready;
assign fio_icb_rsp_err = sysfio_icb_rsp_err ;
assign fio_icb_rsp_rdata = sysfio_icb_rsp_rdata;
`endif//}
wire mem_icb_cmd_valid;
wire mem_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr;
wire mem_icb_cmd_read;
wire [`E203_XLEN-1:0] mem_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] mem_icb_cmd_wmask;
wire mem_icb_rsp_valid;
wire mem_icb_rsp_ready;
wire mem_icb_rsp_err ;
wire [`E203_XLEN-1:0] mem_icb_rsp_rdata;
wire plic_ext_irq;
wire clint_sft_irq;
wire clint_tmr_irq;
wire tm_stop;
wire core_wfi;
e203_cpu_top u_e203_cpu_top(
.inspect_pc (inspect_pc),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_mem_cmd_valid (inspect_mem_cmd_valid),
.inspect_mem_cmd_ready (inspect_mem_cmd_ready),
.inspect_mem_rsp_valid (inspect_mem_rsp_valid),
.inspect_mem_rsp_ready (inspect_mem_rsp_ready),
.inspect_core_clk (inspect_core_clk),
.core_csr_clk (core_csr_clk ),
.tm_stop (tm_stop),
.pc_rtvec (pc_rtvec),
.tcm_sd (tcm_sd),
.tcm_ds (tcm_ds),
.core_wfi (core_wfi),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq_a),
.ext_irq_a (plic_ext_irq),
.sft_irq_a (clint_sft_irq),
.tmr_irq_a (clint_tmr_irq),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
.test_mode (test_mode),
.clk (hfclk ),
.rst_n (core_rst_n)
);
wire qspi0_irq;
wire qspi1_irq;
wire qspi2_irq;
wire uart0_irq;
wire uart1_irq;
wire uart2_irq;
wire pwm_irq_0;
wire pwm_irq_1;
wire pwm_irq_2;
wire pwm_irq_3;
wire i2c0_mst_irq;
wire i2c1_mst_irq;
wire gpioA_irq;
wire gpioB_irq;
e203_subsys_plic u_e203_subsys_plic(
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.plic_ext_irq (plic_ext_irq),
.wdg_irq_a (aon_wdg_irq_a),
.rtc_irq_a (aon_rtc_irq_a),
.qspi0_irq (qspi0_irq ),
.qspi1_irq (qspi1_irq ),
.qspi2_irq (qspi2_irq ),
.uart0_irq (uart0_irq ),
.uart1_irq (uart1_irq ),
.uart2_irq (uart2_irq ),
.pwm_irq_0 (pwm_irq_0 ),
.pwm_irq_1 (pwm_irq_1 ),
.pwm_irq_2 (pwm_irq_2 ),
.pwm_irq_3 (pwm_irq_3 ),
.i2c0_mst_irq (i2c0_mst_irq),
.i2c1_mst_irq (i2c1_mst_irq),
.gpioA_irq (gpioA_irq ),
.gpioB_irq (gpioB_irq ),
.clk (hfclk ),
.rst_n (per_rst_n)
);
e203_subsys_clint u_e203_subsys_clint(
.tm_stop (tm_stop),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
.clint_tmr_irq (clint_tmr_irq),
.clint_sft_irq (clint_sft_irq),
.aon_rtcToggle_a (aon_rtcToggle_a),
.clk (hfclk ),
.rst_n (per_rst_n)
);
wire qspi0_ro_icb_cmd_valid;
wire qspi0_ro_icb_cmd_ready;
wire [32-1:0] qspi0_ro_icb_cmd_addr;
wire qspi0_ro_icb_cmd_read;
wire [32-1:0] qspi0_ro_icb_cmd_wdata;
wire qspi0_ro_icb_rsp_valid;
wire qspi0_ro_icb_rsp_ready;
wire [32-1:0] qspi0_ro_icb_rsp_rdata;
e203_subsys_perips u_e203_subsys_perips (
.pllbypass (pllbypass ),
.pll_RESET (pll_RESET ),
.pll_ASLEEP (pll_ASLEEP ),
.pll_OD(pll_OD),
.pll_M (pll_M ),
.pll_N (pll_N ),
.plloutdivby1(plloutdivby1),
.plloutdiv (plloutdiv ),
.hfxoscen (hfxoscen),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_addr (sysper_icb_cmd_addr ),
.sysper_icb_cmd_read (sysper_icb_cmd_read ),
.sysper_icb_cmd_wdata (sysper_icb_cmd_wdata),
.sysper_icb_cmd_wmask (sysper_icb_cmd_wmask),
.sysper_icb_rsp_valid (sysper_icb_rsp_valid),
.sysper_icb_rsp_ready (sysper_icb_rsp_ready),
.sysper_icb_rsp_err (sysper_icb_rsp_err ),
.sysper_icb_rsp_rdata (sysper_icb_rsp_rdata),
.aon_icb_cmd_valid (aon_icb_cmd_valid),
.aon_icb_cmd_ready (aon_icb_cmd_ready),
.aon_icb_cmd_addr (aon_icb_cmd_addr ),
.aon_icb_cmd_read (aon_icb_cmd_read ),
.aon_icb_cmd_wdata (aon_icb_cmd_wdata),
.aon_icb_rsp_valid (aon_icb_rsp_valid),
.aon_icb_rsp_ready (aon_icb_rsp_ready),
.aon_icb_rsp_err (aon_icb_rsp_err ),
.aon_icb_rsp_rdata (aon_icb_rsp_rdata),
`ifdef FAKE_FLASH_MODEL//{
.qspi0_ro_icb_cmd_valid (1'b0),
.qspi0_ro_icb_cmd_ready (),
.qspi0_ro_icb_cmd_addr (32'b0 ),
.qspi0_ro_icb_cmd_read (1'b0 ),
.qspi0_ro_icb_cmd_wdata (32'b0),
.qspi0_ro_icb_rsp_valid (),
.qspi0_ro_icb_rsp_ready (1'b0),
.qspi0_ro_icb_rsp_rdata (),
`else//}{
.qspi0_ro_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.qspi0_ro_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.qspi0_ro_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.qspi0_ro_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.qspi0_ro_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.qspi0_ro_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.qspi0_ro_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.qspi0_ro_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
`endif//}
.io_pads_gpioA_i_ival (io_pads_gpioA_i_ival),
.io_pads_gpioA_o_oval (gpioA_o_oval),
.io_pads_gpioA_o_oe (gpioA_o_oe),
.io_pads_gpioB_i_ival (io_pads_gpioB_i_ival),
.io_pads_gpioB_o_oval (io_pads_gpioB_o_oval),
.io_pads_gpioB_o_oe (io_pads_gpioB_o_oe),
.io_pads_qspi0_sck_i_ival (io_pads_qspi0_sck_i_ival ),
.io_pads_qspi0_sck_o_oval (io_pads_qspi0_sck_o_oval ),
.io_pads_qspi0_sck_o_oe (io_pads_qspi0_sck_o_oe ),
.io_pads_qspi0_dq_0_i_ival (io_pads_qspi0_dq_0_i_ival ),
.io_pads_qspi0_dq_0_o_oval (io_pads_qspi0_dq_0_o_oval ),
.io_pads_qspi0_dq_0_o_oe (io_pads_qspi0_dq_0_o_oe ),
.io_pads_qspi0_dq_1_i_ival (io_pads_qspi0_dq_1_i_ival ),
.io_pads_qspi0_dq_1_o_oval (io_pads_qspi0_dq_1_o_oval ),
.io_pads_qspi0_dq_1_o_oe (io_pads_qspi0_dq_1_o_oe ),
.io_pads_qspi0_dq_2_i_ival (io_pads_qspi0_dq_2_i_ival ),
.io_pads_qspi0_dq_2_o_oval (io_pads_qspi0_dq_2_o_oval ),
.io_pads_qspi0_dq_2_o_oe (io_pads_qspi0_dq_2_o_oe ),
.io_pads_qspi0_dq_3_i_ival (io_pads_qspi0_dq_3_i_ival ),
.io_pads_qspi0_dq_3_o_oval (io_pads_qspi0_dq_3_o_oval ),
.io_pads_qspi0_dq_3_o_oe (io_pads_qspi0_dq_3_o_oe ),
.io_pads_qspi0_cs_0_i_ival (io_pads_qspi0_cs_0_i_ival ),
.io_pads_qspi0_cs_0_o_oval (io_pads_qspi0_cs_0_o_oval ),
.io_pads_qspi0_cs_0_o_oe (io_pads_qspi0_cs_0_o_oe ),
.qspi0_irq (qspi0_irq ),
.qspi1_irq (qspi1_irq ),
.qspi2_irq (qspi2_irq ),
.uart0_irq (uart0_irq ),
.uart1_irq (uart1_irq ),
.uart2_irq (uart2_irq ),
.pwm_irq_0 (pwm_irq_0 ),
.pwm_irq_1 (pwm_irq_1 ),
.pwm_irq_2 (pwm_irq_2 ),
.pwm_irq_3 (pwm_irq_3 ),
.i2c0_mst_irq (i2c0_mst_irq),
.i2c1_mst_irq (i2c1_mst_irq),
.gpioA_irq (gpioA_irq ),
.gpioB_irq (gpioB_irq ),
.ls_clk (ls_clk ),
.clk (hfclk ),
.bus_rst_n (bus_rst_n),
.rst_n (per_rst_n)
);
e203_subsys_mems u_e203_subsys_mems(
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
.sysmem_icb_cmd_valid (sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready (sysmem_icb_cmd_ready),
.sysmem_icb_cmd_addr (sysmem_icb_cmd_addr ),
.sysmem_icb_cmd_read (sysmem_icb_cmd_read ),
.sysmem_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.sysmem_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.sysmem_icb_rsp_valid (sysmem_icb_rsp_valid),
.sysmem_icb_rsp_ready (sysmem_icb_rsp_ready),
.sysmem_icb_rsp_err (sysmem_icb_rsp_err ),
.sysmem_icb_rsp_rdata (sysmem_icb_rsp_rdata),
.qspi0_ro_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.qspi0_ro_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.qspi0_ro_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.qspi0_ro_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.qspi0_ro_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.qspi0_ro_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.qspi0_ro_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.qspi0_ro_icb_rsp_err (1'b0 ),
.qspi0_ro_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
.dm_icb_cmd_valid (dm_icb_cmd_valid ),
.dm_icb_cmd_ready (dm_icb_cmd_ready ),
.dm_icb_cmd_addr (dm_icb_cmd_addr ),
.dm_icb_cmd_read (dm_icb_cmd_read ),
.dm_icb_cmd_wdata (dm_icb_cmd_wdata ),
.dm_icb_rsp_valid (dm_icb_rsp_valid ),
.dm_icb_rsp_ready (dm_icb_rsp_ready ),
.dm_icb_rsp_rdata (dm_icb_rsp_rdata ),
.clk (hfclk ),
.bus_rst_n (bus_rst_n),
.rst_n (per_rst_n)
);
`ifdef FAKE_FLASH_MODEL//{
fake_qspi0_model_top u_fake_qspi0_model_top(
.icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.icb_cmd_read (qspi0_ro_icb_cmd_read ),
.icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
.clk (hfclk ),
.rst_n (bus_rst_n)
);
`endif//}
endmodule |
module e203_subsys_nice_core (
// System
input nice_clk ,
input nice_rst_n ,
output nice_active ,
output nice_mem_holdup ,
// output nice_rsp_err_irq ,
// Control cmd_req
input nice_req_valid ,
output nice_req_ready ,
input [`E203_XLEN-1:0] nice_req_inst ,
input [`E203_XLEN-1:0] nice_req_rs1 ,
input [`E203_XLEN-1:0] nice_req_rs2 ,
// Control cmd_rsp
output nice_rsp_valid ,
input nice_rsp_ready ,
output [`E203_XLEN-1:0] nice_rsp_rdat ,
output nice_rsp_err ,
// Memory lsu_req
output nice_icb_cmd_valid ,
input nice_icb_cmd_ready ,
output [`E203_ADDR_SIZE-1:0] nice_icb_cmd_addr ,
output nice_icb_cmd_read ,
output [`E203_XLEN-1:0] nice_icb_cmd_wdata ,
// output [`E203_XLEN_MW-1:0] nice_icb_cmd_wmask , //
output [1:0] nice_icb_cmd_size ,
// Memory lsu_rsp
input nice_icb_rsp_valid ,
output nice_icb_rsp_ready ,
input [`E203_XLEN-1:0] nice_icb_rsp_rdata ,
input nice_icb_rsp_err
);
localparam ROWBUF_DP = 4;
localparam ROWBUF_IDX_W = 2;
localparam ROW_IDX_W = 2;
localparam COL_IDX_W = 4;
localparam PIPE_NUM = 3;
// here we only use custom3:
// CUSTOM0 = 7'h0b, R type
// CUSTOM1 = 7'h2b, R tpye
// CUSTOM2 = 7'h5b, R type
// CUSTOM3 = 7'h7b, R type
// RISC-V format
// .insn r 0x33, 0, 0, a0, a1, a2 0: 00c58533[ ]+add [ ]+a0,a1,a2
// .insn i 0x13, 0, a0, a1, 13 4: 00d58513[ ]+addi[ ]+a0,a1,13
// .insn i 0x67, 0, a0, 10(a1) 8: 00a58567[ ]+jalr[ ]+a0,10 (a1)
// .insn s 0x3, 0, a0, 4(a1) c: 00458503[ ]+lb [ ]+a0,4(a1)
// .insn sb 0x63, 0, a0, a1, target 10: feb508e3[ ]+beq [ ]+a0,a1,0 target
// .insn sb 0x23, 0, a0, 4(a1) 14: 00a58223[ ]+sb [ ]+a0,4(a1)
// .insn u 0x37, a0, 0xfff 18: 00fff537[ ]+lui [ ]+a0,0xfff
// .insn uj 0x6f, a0, target 1c: fe5ff56f[ ]+jal [ ]+a0,0 target
// .insn ci 0x1, 0x0, a0, 4 20: 0511 [ ]+addi[ ]+a0,a0,4
// .insn cr 0x2, 0x8, a0, a1 22: 852e [ ]+mv [ ]+a0,a1
// .insn ciw 0x0, 0x0, a1, 1 24: 002c [ ]+addi[ ]+a1,sp,8
// .insn cb 0x1, 0x6, a1, target 26: dde9 [ ]+beqz[ ]+a1,0 target
// .insn cj 0x1, 0x5, target 28: bfe1 [ ]+j [ ]+0 targe
////////////////////////////////////////////////////////////
// decode
////////////////////////////////////////////////////////////
wire [6:0] opcode = {7{nice_req_valid}} & nice_req_inst[6:0];
wire [2:0] rv32_func3 = {3{nice_req_valid}} & nice_req_inst[14:12];
wire [6:0] rv32_func7 = {7{nice_req_valid}} & nice_req_inst[31:25];
// wire opcode_custom0 = (opcode == 7'b0001011);
// wire opcode_custom1 = (opcode == 7'b0101011);
// wire opcode_custom2 = (opcode == 7'b1011011);
wire opcode_custom3 = (opcode == 7'b1111011);
wire rv32_func3_000 = (rv32_func3 == 3'b000);
wire rv32_func3_001 = (rv32_func3 == 3'b001);
wire rv32_func3_010 = (rv32_func3 == 3'b010);
wire rv32_func3_011 = (rv32_func3 == 3'b011);
wire rv32_func3_100 = (rv32_func3 == 3'b100);
wire rv32_func3_101 = (rv32_func3 == 3'b101);
wire rv32_func3_110 = (rv32_func3 == 3'b110);
wire rv32_func3_111 = (rv32_func3 == 3'b111);
wire rv32_func7_0000000 = (rv32_func7 == 7'b0000000);
wire rv32_func7_0000001 = (rv32_func7 == 7'b0000001);
wire rv32_func7_0000010 = (rv32_func7 == 7'b0000010);
wire rv32_func7_0000011 = (rv32_func7 == 7'b0000011);
wire rv32_func7_0000100 = (rv32_func7 == 7'b0000100);
wire rv32_func7_0000101 = (rv32_func7 == 7'b0000101);
wire rv32_func7_0000110 = (rv32_func7 == 7'b0000110);
wire rv32_func7_0000111 = (rv32_func7 == 7'b0000111);
////////////////////////////////////////////////////////////
// custom3:
// Supported format: only R type here
// Supported instr:
// 1. custom3 lbuf: load data(in memory) to row_buf
// lbuf (a1)
// .insn r opcode, func3, func7, rd, rs1, rs2
// 2. custom3 sbuf: store data(in row_buf) to memory
// sbuf (a1)
// .insn r opcode, func3, func7, rd, rs1, rs2
// 3. custom3 acc rowsum: load data from memory(@a1), accumulate row datas and write back
// rowsum rd, a1, x0
// .insn r opcode, func3, func7, rd, rs1, rs2
////////////////////////////////////////////////////////////
wire custom3_lbuf = opcode_custom3 & rv32_func3_010 & rv32_func7_0000001;
wire custom3_sbuf = opcode_custom3 & rv32_func3_010 & rv32_func7_0000010;
wire custom3_rowsum = opcode_custom3 & rv32_func3_110 & rv32_func7_0000110;
////////////////////////////////////////////////////////////
// multi-cyc op
////////////////////////////////////////////////////////////
wire custom_multi_cyc_op = custom3_lbuf | custom3_sbuf | custom3_rowsum;
// need access memory
wire custom_mem_op = custom3_lbuf | custom3_sbuf | custom3_rowsum;
////////////////////////////////////////////////////////////
// NICE FSM
////////////////////////////////////////////////////////////
parameter NICE_FSM_WIDTH = 2;
parameter IDLE = 2'd0;
parameter LBUF = 2'd1;
parameter SBUF = 2'd2;
parameter ROWSUM = 2'd3;
wire [NICE_FSM_WIDTH-1:0] state_r;
wire [NICE_FSM_WIDTH-1:0] nxt_state;
wire [NICE_FSM_WIDTH-1:0] state_idle_nxt;
wire [NICE_FSM_WIDTH-1:0] state_lbuf_nxt;
wire [NICE_FSM_WIDTH-1:0] state_sbuf_nxt;
wire [NICE_FSM_WIDTH-1:0] state_rowsum_nxt;
wire nice_req_hsked;
wire nice_rsp_hsked;
wire nice_icb_rsp_hsked;
wire illgel_instr = ~(custom_multi_cyc_op);
wire state_idle_exit_ena;
wire state_lbuf_exit_ena;
wire state_sbuf_exit_ena;
wire state_rowsum_exit_ena;
wire state_ena;
wire state_is_idle = (state_r == IDLE);
wire state_is_lbuf = (state_r == LBUF);
wire state_is_sbuf = (state_r == SBUF);
wire state_is_rowsum = (state_r == ROWSUM);
assign state_idle_exit_ena = state_is_idle & nice_req_hsked & ~illgel_instr;
assign state_idle_nxt = custom3_lbuf ? LBUF :
custom3_sbuf ? SBUF :
custom3_rowsum ? ROWSUM :
IDLE;
wire lbuf_icb_rsp_hsked_last;
assign state_lbuf_exit_ena = state_is_lbuf & lbuf_icb_rsp_hsked_last;
assign state_lbuf_nxt = IDLE;
wire sbuf_icb_rsp_hsked_last;
assign state_sbuf_exit_ena = state_is_sbuf & sbuf_icb_rsp_hsked_last;
assign state_sbuf_nxt = IDLE;
wire rowsum_done;
assign state_rowsum_exit_ena = state_is_rowsum & rowsum_done;
assign state_rowsum_nxt = IDLE;
assign nxt_state = ({NICE_FSM_WIDTH{state_idle_exit_ena }} & state_idle_nxt )
| ({NICE_FSM_WIDTH{state_lbuf_exit_ena }} & state_lbuf_nxt )
| ({NICE_FSM_WIDTH{state_sbuf_exit_ena }} & state_sbuf_nxt )
| ({NICE_FSM_WIDTH{state_rowsum_exit_ena }} & state_rowsum_nxt )
;
assign state_ena = state_idle_exit_ena | state_lbuf_exit_ena
| state_sbuf_exit_ena | state_rowsum_exit_ena;
sirv_gnrl_dfflr #(NICE_FSM_WIDTH) state_dfflr (state_ena, nxt_state, state_r, nice_clk, nice_rst_n);
////////////////////////////////////////////////////////////
// instr EXU
////////////////////////////////////////////////////////////
wire [ROW_IDX_W-1:0] clonum = 2'b10; // fixed clonum
//wire [COL_IDX_W-1:0] rownum;
//////////// 1. custom3_lbuf
wire [ROWBUF_IDX_W-1:0] lbuf_cnt_r;
wire [ROWBUF_IDX_W-1:0] lbuf_cnt_nxt;
wire lbuf_cnt_clr;
wire lbuf_cnt_incr;
wire lbuf_cnt_ena;
wire lbuf_cnt_last;
wire lbuf_icb_rsp_hsked;
wire nice_rsp_valid_lbuf;
wire nice_icb_cmd_valid_lbuf;
assign lbuf_icb_rsp_hsked = state_is_lbuf & nice_icb_rsp_hsked;
assign lbuf_icb_rsp_hsked_last = lbuf_icb_rsp_hsked & lbuf_cnt_last;
assign lbuf_cnt_last = (lbuf_cnt_r == clonum);
assign lbuf_cnt_clr = custom3_lbuf & nice_req_hsked;
assign lbuf_cnt_incr = lbuf_icb_rsp_hsked & ~lbuf_cnt_last;
assign lbuf_cnt_ena = lbuf_cnt_clr | lbuf_cnt_incr;
assign lbuf_cnt_nxt = ({ROWBUF_IDX_W{lbuf_cnt_clr }} & {ROWBUF_IDX_W{1'b0}})
| ({ROWBUF_IDX_W{lbuf_cnt_incr}} & (lbuf_cnt_r + 1'b1) )
;
sirv_gnrl_dfflr #(ROWBUF_IDX_W) lbuf_cnt_dfflr (lbuf_cnt_ena, lbuf_cnt_nxt, lbuf_cnt_r, nice_clk, nice_rst_n);
// nice_rsp_valid wait for nice_icb_rsp_valid in LBUF
assign nice_rsp_valid_lbuf = state_is_lbuf & lbuf_cnt_last & nice_icb_rsp_valid;
// nice_icb_cmd_valid sets when lbuf_cnt_r is not full in LBUF
assign nice_icb_cmd_valid_lbuf = (state_is_lbuf & (lbuf_cnt_r < clonum));
//////////// 2. custom3_sbuf
wire [ROWBUF_IDX_W-1:0] sbuf_cnt_r;
wire [ROWBUF_IDX_W-1:0] sbuf_cnt_nxt;
wire sbuf_cnt_clr;
wire sbuf_cnt_incr;
wire sbuf_cnt_ena;
wire sbuf_cnt_last;
wire sbuf_icb_cmd_hsked;
wire sbuf_icb_rsp_hsked;
wire nice_rsp_valid_sbuf;
wire nice_icb_cmd_valid_sbuf;
wire nice_icb_cmd_hsked;
assign sbuf_icb_cmd_hsked = (state_is_sbuf | (state_is_idle & custom3_sbuf)) & nice_icb_cmd_hsked;
assign sbuf_icb_rsp_hsked = state_is_sbuf & nice_icb_rsp_hsked;
assign sbuf_icb_rsp_hsked_last = sbuf_icb_rsp_hsked & sbuf_cnt_last;
assign sbuf_cnt_last = (sbuf_cnt_r == clonum);
//assign sbuf_cnt_clr = custom3_sbuf & nice_req_hsked;
assign sbuf_cnt_clr = sbuf_icb_rsp_hsked_last;
assign sbuf_cnt_incr = sbuf_icb_rsp_hsked & ~sbuf_cnt_last;
assign sbuf_cnt_ena = sbuf_cnt_clr | sbuf_cnt_incr;
assign sbuf_cnt_nxt = ({ROWBUF_IDX_W{sbuf_cnt_clr }} & {ROWBUF_IDX_W{1'b0}})
| ({ROWBUF_IDX_W{sbuf_cnt_incr}} & (sbuf_cnt_r + 1'b1) )
;
sirv_gnrl_dfflr #(ROWBUF_IDX_W) sbuf_cnt_dfflr (sbuf_cnt_ena, sbuf_cnt_nxt, sbuf_cnt_r, nice_clk, nice_rst_n);
// nice_rsp_valid wait for nice_icb_rsp_valid in SBUF
assign nice_rsp_valid_sbuf = state_is_sbuf & sbuf_cnt_last & nice_icb_rsp_valid;
wire [ROWBUF_IDX_W-1:0] sbuf_cmd_cnt_r;
wire [ROWBUF_IDX_W-1:0] sbuf_cmd_cnt_nxt;
wire sbuf_cmd_cnt_clr;
wire sbuf_cmd_cnt_incr;
wire sbuf_cmd_cnt_ena;
wire sbuf_cmd_cnt_last;
assign sbuf_cmd_cnt_last = (sbuf_cmd_cnt_r == clonum);
assign sbuf_cmd_cnt_clr = sbuf_icb_rsp_hsked_last;
assign sbuf_cmd_cnt_incr = sbuf_icb_cmd_hsked & ~sbuf_cmd_cnt_last;
assign sbuf_cmd_cnt_ena = sbuf_cmd_cnt_clr | sbuf_cmd_cnt_incr;
assign sbuf_cmd_cnt_nxt = ({ROWBUF_IDX_W{sbuf_cmd_cnt_clr }} & {ROWBUF_IDX_W{1'b0}})
| ({ROWBUF_IDX_W{sbuf_cmd_cnt_incr}} & (sbuf_cmd_cnt_r + 1'b1) )
;
sirv_gnrl_dfflr #(ROWBUF_IDX_W) sbuf_cmd_cnt_dfflr (sbuf_cmd_cnt_ena, sbuf_cmd_cnt_nxt, sbuf_cmd_cnt_r, nice_clk, nice_rst_n);
// nice_icb_cmd_valid sets when sbuf_cmd_cnt_r is not full in SBUF
assign nice_icb_cmd_valid_sbuf = (state_is_sbuf & (sbuf_cmd_cnt_r <= clonum) & (sbuf_cnt_r != clonum));
//////////// 3. custom3_rowsum
// rowbuf counter
wire [ROWBUF_IDX_W-1:0] rowbuf_cnt_r;
wire [ROWBUF_IDX_W-1:0] rowbuf_cnt_nxt;
wire rowbuf_cnt_clr;
wire rowbuf_cnt_incr;
wire rowbuf_cnt_ena;
wire rowbuf_cnt_last;
wire rowbuf_icb_rsp_hsked;
wire rowbuf_rsp_hsked;
wire nice_rsp_valid_rowsum;
assign rowbuf_rsp_hsked = nice_rsp_valid_rowsum & nice_rsp_ready;
assign rowbuf_icb_rsp_hsked = state_is_rowsum & nice_icb_rsp_hsked;
assign rowbuf_cnt_last = (rowbuf_cnt_r == clonum);
assign rowbuf_cnt_clr = rowbuf_icb_rsp_hsked & rowbuf_cnt_last;
assign rowbuf_cnt_incr = rowbuf_icb_rsp_hsked & ~rowbuf_cnt_last;
assign rowbuf_cnt_ena = rowbuf_cnt_clr | rowbuf_cnt_incr;
assign rowbuf_cnt_nxt = ({ROWBUF_IDX_W{rowbuf_cnt_clr }} & {ROWBUF_IDX_W{1'b0}})
| ({ROWBUF_IDX_W{rowbuf_cnt_incr}} & (rowbuf_cnt_r + 1'b1))
;
//assign nice_icb_cmd_valid_rowbuf = (state_is_idle & custom3_rowsum)
// | (state_is_rowsum & (rowbuf_cnt_r <= clonum) & (clonum != 0))
// ;
sirv_gnrl_dfflr #(ROWBUF_IDX_W) rowbuf_cnt_dfflr (rowbuf_cnt_ena, rowbuf_cnt_nxt, rowbuf_cnt_r, nice_clk, nice_rst_n);
// recieve data buffer, to make sure rowsum ops come from registers
wire rcv_data_buf_ena;
wire rcv_data_buf_set;
wire rcv_data_buf_clr;
wire rcv_data_buf_valid;
wire [`E203_XLEN-1:0] rcv_data_buf;
wire [ROWBUF_IDX_W-1:0] rcv_data_buf_idx;
wire [ROWBUF_IDX_W-1:0] rcv_data_buf_idx_nxt;
assign rcv_data_buf_set = rowbuf_icb_rsp_hsked;
assign rcv_data_buf_clr = rowbuf_rsp_hsked;
assign rcv_data_buf_ena = rcv_data_buf_clr | rcv_data_buf_set;
assign rcv_data_buf_idx_nxt = ({ROWBUF_IDX_W{rcv_data_buf_clr}} & {ROWBUF_IDX_W{1'b0}})
| ({ROWBUF_IDX_W{rcv_data_buf_set}} & rowbuf_cnt_r );
sirv_gnrl_dfflr #(1) rcv_data_buf_valid_dfflr (1'b1, rcv_data_buf_ena, rcv_data_buf_valid, nice_clk, nice_rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) rcv_data_buf_dfflr (rcv_data_buf_ena, nice_icb_rsp_rdata, rcv_data_buf, nice_clk, nice_rst_n);
sirv_gnrl_dfflr #(ROWBUF_IDX_W) rowbuf_cnt_d_dfflr (rcv_data_buf_ena, rcv_data_buf_idx_nxt, rcv_data_buf_idx, nice_clk, nice_rst_n);
// rowsum accumulator
wire [`E203_XLEN-1:0] rowsum_acc_r;
wire [`E203_XLEN-1:0] rowsum_acc_nxt;
wire [`E203_XLEN-1:0] rowsum_acc_adder;
wire rowsum_acc_ena;
wire rowsum_acc_set;
wire rowsum_acc_flg;
wire nice_icb_cmd_valid_rowsum;
wire [`E203_XLEN-1:0] rowsum_res;
assign rowsum_acc_set = rcv_data_buf_valid & (rcv_data_buf_idx == {ROWBUF_IDX_W{1'b0}});
assign rowsum_acc_flg = rcv_data_buf_valid & (rcv_data_buf_idx != {ROWBUF_IDX_W{1'b0}});
assign rowsum_acc_adder = rcv_data_buf + rowsum_acc_r;
assign rowsum_acc_ena = rowsum_acc_set | rowsum_acc_flg;
assign rowsum_acc_nxt = ({`E203_XLEN{rowsum_acc_set}} & rcv_data_buf)
| ({`E203_XLEN{rowsum_acc_flg}} & rowsum_acc_adder)
;
sirv_gnrl_dfflr #(`E203_XLEN) rowsum_acc_dfflr (rowsum_acc_ena, rowsum_acc_nxt, rowsum_acc_r, nice_clk, nice_rst_n);
assign rowsum_done = state_is_rowsum & nice_rsp_hsked;
assign rowsum_res = rowsum_acc_r;
// rowsum finishes when the last acc data is added to rowsum_acc_r
assign nice_rsp_valid_rowsum = state_is_rowsum & (rcv_data_buf_idx == clonum) & ~rowsum_acc_flg;
// nice_icb_cmd_valid sets when rcv_data_buf_idx is not full in LBUF
assign nice_icb_cmd_valid_rowsum = state_is_rowsum & (rcv_data_buf_idx < clonum) & ~rowsum_acc_flg;
//////////// rowbuf
// rowbuf access list:
// 1. lbuf will write to rowbuf, write data comes from memory, data length is defined by clonum
// 2. sbuf will read from rowbuf, and store it to memory, data length is defined by clonum
// 3. rowsum will accumulate data, and store to rowbuf, data length is defined by clonum
wire [`E203_XLEN-1:0] rowbuf_r [ROWBUF_DP-1:0];
wire [`E203_XLEN-1:0] rowbuf_wdat [ROWBUF_DP-1:0];
wire [ROWBUF_DP-1:0] rowbuf_we;
wire [ROWBUF_IDX_W-1:0] rowbuf_idx_mux;
wire [`E203_XLEN-1:0] rowbuf_wdat_mux;
wire rowbuf_wr_mux;
//wire [ROWBUF_IDX_W-1:0] sbuf_idx;
// lbuf write to rowbuf
wire [ROWBUF_IDX_W-1:0] lbuf_idx = lbuf_cnt_r;
wire lbuf_wr = lbuf_icb_rsp_hsked;
wire [`E203_XLEN-1:0] lbuf_wdata = nice_icb_rsp_rdata;
// rowsum write to rowbuf(column accumulated data)
wire [ROWBUF_IDX_W-1:0] rowsum_idx = rcv_data_buf_idx;
wire rowsum_wr = rcv_data_buf_valid;
wire [`E203_XLEN-1:0] rowsum_wdata = rowbuf_r[rowsum_idx] + rcv_data_buf;
// rowbuf write mux
assign rowbuf_wdat_mux = ({`E203_XLEN{lbuf_wr }} & lbuf_wdata )
| ({`E203_XLEN{rowsum_wr}} & rowsum_wdata)
;
assign rowbuf_wr_mux = lbuf_wr | rowsum_wr;
assign rowbuf_idx_mux = ({ROWBUF_IDX_W{lbuf_wr }} & lbuf_idx )
| ({ROWBUF_IDX_W{rowsum_wr}} & rowsum_idx)
;
// rowbuf inst
genvar i;
generate
for (i=0; i<ROWBUF_DP; i=i+1) begin:gen_rowbuf
assign rowbuf_we[i] = (rowbuf_wr_mux & (rowbuf_idx_mux == i[ROWBUF_IDX_W-1:0]))
;
assign rowbuf_wdat[i] = ({`E203_XLEN{rowbuf_we[i]}} & rowbuf_wdat_mux )
;
sirv_gnrl_dfflr #(`E203_XLEN) rowbuf_dfflr (rowbuf_we[i], rowbuf_wdat[i], rowbuf_r[i], nice_clk, nice_rst_n);
end
endgenerate
//////////// mem aacess addr management
wire [`E203_XLEN-1:0] maddr_acc_r;
assign nice_icb_cmd_hsked = nice_icb_cmd_valid & nice_icb_cmd_ready;
// custom3_lbuf
//wire [`E203_XLEN-1:0] lbuf_maddr = state_is_idle ? nice_req_rs1 : maddr_acc_r ;
wire lbuf_maddr_ena = (state_is_idle & custom3_lbuf & nice_icb_cmd_hsked)
| (state_is_lbuf & nice_icb_cmd_hsked)
;
// custom3_sbuf
//wire [`E203_XLEN-1:0] sbuf_maddr = state_is_idle ? nice_req_rs1 : maddr_acc_r ;
wire sbuf_maddr_ena = (state_is_idle & custom3_sbuf & nice_icb_cmd_hsked)
| (state_is_sbuf & nice_icb_cmd_hsked)
;
// custom3_rowsum
//wire [`E203_XLEN-1:0] rowsum_maddr = state_is_idle ? nice_req_rs1 : maddr_acc_r ;
wire rowsum_maddr_ena = (state_is_idle & custom3_rowsum & nice_icb_cmd_hsked)
| (state_is_rowsum & nice_icb_cmd_hsked)
;
// maddr acc
//wire maddr_incr = lbuf_maddr_ena | sbuf_maddr_ena | rowsum_maddr_ena | rbuf_maddr_ena;
wire maddr_ena = lbuf_maddr_ena | sbuf_maddr_ena | rowsum_maddr_ena;
wire maddr_ena_idle = maddr_ena & state_is_idle;
wire [`E203_XLEN-1:0] maddr_acc_op1 = maddr_ena_idle ? nice_req_rs1 : maddr_acc_r; // not reused
wire [`E203_XLEN-1:0] maddr_acc_op2 = maddr_ena_idle ? `E203_XLEN'h4 : `E203_XLEN'h4;
wire [`E203_XLEN-1:0] maddr_acc_next = maddr_acc_op1 + maddr_acc_op2;
wire maddr_acc_ena = maddr_ena;
sirv_gnrl_dfflr #(`E203_XLEN) maddr_acc_dfflr (maddr_acc_ena, maddr_acc_next, maddr_acc_r, nice_clk, nice_rst_n);
////////////////////////////////////////////////////////////
// Control cmd_req
////////////////////////////////////////////////////////////
assign nice_req_hsked = nice_req_valid & nice_req_ready;
assign nice_req_ready = state_is_idle & (custom_mem_op ? nice_icb_cmd_ready : 1'b1);
////////////////////////////////////////////////////////////
// Control cmd_rsp
////////////////////////////////////////////////////////////
assign nice_rsp_hsked = nice_rsp_valid & nice_rsp_ready;
assign nice_icb_rsp_hsked = nice_icb_rsp_valid & nice_icb_rsp_ready;
assign nice_rsp_valid = nice_rsp_valid_rowsum | nice_rsp_valid_sbuf | nice_rsp_valid_lbuf;
assign nice_rsp_rdat = {`E203_XLEN{state_is_rowsum}} & rowsum_res;
// memory access bus error
//assign nice_rsp_err_irq = (nice_icb_rsp_hsked & nice_icb_rsp_err)
// | (nice_req_hsked & illgel_instr)
// ;
assign nice_rsp_err = (nice_icb_rsp_hsked & nice_icb_rsp_err);
////////////////////////////////////////////////////////////
// Memory lsu
////////////////////////////////////////////////////////////
// memory access list:
// 1. In IDLE, custom_mem_op will access memory(lbuf/sbuf/rowsum)
// 2. In LBUF, it will read from memory as long as lbuf_cnt_r is not full
// 3. In SBUF, it will write to memory as long as sbuf_cnt_r is not full
// 3. In ROWSUM, it will read from memory as long as rowsum_cnt_r is not full
//assign nice_icb_rsp_ready = state_is_ldst_rsp & nice_rsp_ready;
// rsp always ready
assign nice_icb_rsp_ready = 1'b1;
wire [ROWBUF_IDX_W-1:0] sbuf_idx = sbuf_cmd_cnt_r;
assign nice_icb_cmd_valid = (state_is_idle & nice_req_valid & custom_mem_op)
| nice_icb_cmd_valid_lbuf
| nice_icb_cmd_valid_sbuf
| nice_icb_cmd_valid_rowsum
;
assign nice_icb_cmd_addr = (state_is_idle & custom_mem_op) ? nice_req_rs1 :
maddr_acc_r;
assign nice_icb_cmd_read = (state_is_idle & custom_mem_op) ? (custom3_lbuf | custom3_rowsum) :
state_is_sbuf ? 1'b0 :
1'b1;
assign nice_icb_cmd_wdata = (state_is_idle & custom3_sbuf) ? rowbuf_r[sbuf_idx] :
state_is_sbuf ? rowbuf_r[sbuf_idx] :
`E203_XLEN'b0;
//assign nice_icb_cmd_wmask = {`sirv_XLEN_MW{custom3_sbuf}} & 4'b1111;
assign nice_icb_cmd_size = 2'b10;
assign nice_mem_holdup = state_is_lbuf | state_is_sbuf | state_is_rowsum;
////////////////////////////////////////////////////////////
// nice_active
////////////////////////////////////////////////////////////
assign nice_active = state_is_idle ? nice_req_valid : 1'b1;
endmodule |
module e203_subsys_plic(
input plic_icb_cmd_valid,
output plic_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
input plic_icb_cmd_read,
input [`E203_XLEN-1:0] plic_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
output plic_icb_rsp_valid,
input plic_icb_rsp_ready,
output plic_icb_rsp_err,
output [`E203_XLEN-1:0] plic_icb_rsp_rdata,
output plic_ext_irq,
input wdg_irq_a,
input rtc_irq_a,
input qspi0_irq,
input qspi1_irq,
input qspi2_irq,
input uart0_irq,
input uart1_irq,
input uart2_irq,
input pwm_irq_0,
input pwm_irq_1,
input pwm_irq_2,
input pwm_irq_3,
input i2c0_mst_irq,
input i2c1_mst_irq,
input gpioA_irq,
input gpioB_irq,
input clk,
input rst_n
);
assign plic_icb_rsp_err = 1'b0;
wire wdg_irq_r;
wire rtc_irq_r;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_rtc_irq_sync(
.din_a (rtc_irq_a),
.dout (rtc_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_wdg_irq_sync(
.din_a (wdg_irq_a),
.dout (wdg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
wire plic_irq_i_0 = wdg_irq_r;
wire plic_irq_i_1 = rtc_irq_r;
wire plic_irq_i_2 = uart0_irq;
wire plic_irq_i_3 = uart1_irq;
wire plic_irq_i_4 = uart2_irq;
wire plic_irq_i_5 = qspi0_irq;
wire plic_irq_i_6 = qspi1_irq;
wire plic_irq_i_7 = qspi2_irq;
wire plic_irq_i_8 = pwm_irq_0;
wire plic_irq_i_9 = pwm_irq_1;
wire plic_irq_i_10 = pwm_irq_2;
wire plic_irq_i_11 = pwm_irq_3;
wire plic_irq_i_12 = i2c0_mst_irq;
wire plic_irq_i_13 = i2c1_mst_irq;
wire plic_irq_i_14 = gpioA_irq;
wire plic_irq_i_15 = gpioB_irq;
sirv_plic_top u_sirv_plic_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (plic_icb_cmd_valid),
.i_icb_cmd_ready (plic_icb_cmd_ready),
.i_icb_cmd_addr (plic_icb_cmd_addr ),
.i_icb_cmd_read (plic_icb_cmd_read ),
.i_icb_cmd_wdata (plic_icb_cmd_wdata),
.i_icb_rsp_valid (plic_icb_rsp_valid),
.i_icb_rsp_ready (plic_icb_rsp_ready),
.i_icb_rsp_rdata (plic_icb_rsp_rdata),
.io_devices_0_0 (plic_irq_i_0 ),
.io_devices_0_1 (plic_irq_i_1 ),
.io_devices_0_2 (plic_irq_i_2 ),
.io_devices_0_3 (plic_irq_i_3 ),
.io_devices_0_4 (plic_irq_i_4 ),
.io_devices_0_5 (plic_irq_i_5 ),
.io_devices_0_6 (plic_irq_i_6 ),
.io_devices_0_7 (plic_irq_i_7 ),
.io_devices_0_8 (plic_irq_i_8 ),
.io_devices_0_9 (plic_irq_i_9 ),
.io_devices_0_10 (plic_irq_i_10),
.io_devices_0_11 (plic_irq_i_11),
.io_devices_0_12 (plic_irq_i_12),
.io_devices_0_13 (plic_irq_i_13),
.io_devices_0_14 (plic_irq_i_14),
.io_devices_0_15 (plic_irq_i_15),
.io_harts_0_0 (plic_ext_irq )
);
endmodule |
module e203_soc_top(
// This clock should comes from the crystal pad generated high speed clock (16MHz)
input hfextclk,
output hfxoscen,// The signal to enable the crystal pad generated clock
// This clock should comes from the crystal pad generated low speed clock (32.768KHz)
input lfextclk,
output lfxoscen,// The signal to enable the crystal pad generated clock
// The JTAG TCK is input, need to be pull-up
input io_pads_jtag_TCK_i_ival,
// The JTAG TMS is input, need to be pull-up
input io_pads_jtag_TMS_i_ival,
// The JTAG TDI is input, need to be pull-up
input io_pads_jtag_TDI_i_ival,
// The JTAG TDO is output have enable
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
// The GPIO are all bidir pad have enables
input [32-1:0] io_pads_gpioA_i_ival,
output [32-1:0] io_pads_gpioA_o_oval,
output [32-1:0] io_pads_gpioA_o_oe,
input [32-1:0] io_pads_gpioB_i_ival,
output [32-1:0] io_pads_gpioB_o_oval,
output [32-1:0] io_pads_gpioB_o_oe,
//QSPI0 SCK and CS is output without enable
output io_pads_qspi0_sck_o_oval,
output io_pads_qspi0_cs_0_o_oval,
//QSPI0 DQ is bidir I/O with enable, and need pull-up enable
input io_pads_qspi0_dq_0_i_ival,
output io_pads_qspi0_dq_0_o_oval,
output io_pads_qspi0_dq_0_o_oe,
input io_pads_qspi0_dq_1_i_ival,
output io_pads_qspi0_dq_1_o_oval,
output io_pads_qspi0_dq_1_o_oe,
input io_pads_qspi0_dq_2_i_ival,
output io_pads_qspi0_dq_2_o_oval,
output io_pads_qspi0_dq_2_o_oe,
input io_pads_qspi0_dq_3_i_ival,
output io_pads_qspi0_dq_3_o_oval,
output io_pads_qspi0_dq_3_o_oe,
// Erst is input need to be pull-up by default
input io_pads_aon_erst_n_i_ival,
// dbgmode are inputs need to be pull-up by default
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
// BootRom is input need to be pull-up by default
input io_pads_bootrom_n_i_ival,
// dwakeup is input need to be pull-up by default
input io_pads_aon_pmu_dwakeup_n_i_ival,
// PMU output is just output without enable
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_vddpaden_o_oval
);
wire sysper_icb_cmd_valid;
wire sysper_icb_cmd_ready;
wire sysfio_icb_cmd_valid;
wire sysfio_icb_cmd_ready;
wire sysmem_icb_cmd_valid;
wire sysmem_icb_cmd_ready;
e203_subsys_top u_e203_subsys_top(
.core_mhartid (1'b0),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (1'b0),
.ext2itcm_icb_cmd_ready (),
.ext2itcm_icb_cmd_addr (`E203_ITCM_ADDR_WIDTH'b0 ),
.ext2itcm_icb_cmd_read (1'b0 ),
.ext2itcm_icb_cmd_wdata (32'b0),
.ext2itcm_icb_cmd_wmask (4'b0),
.ext2itcm_icb_rsp_valid (),
.ext2itcm_icb_rsp_ready (1'b0),
.ext2itcm_icb_rsp_err (),
.ext2itcm_icb_rsp_rdata (),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (1'b0),
.ext2dtcm_icb_cmd_ready (),
.ext2dtcm_icb_cmd_addr (`E203_DTCM_ADDR_WIDTH'b0 ),
.ext2dtcm_icb_cmd_read (1'b0 ),
.ext2dtcm_icb_cmd_wdata (32'b0),
.ext2dtcm_icb_cmd_wmask (4'b0),
.ext2dtcm_icb_rsp_valid (),
.ext2dtcm_icb_rsp_ready (1'b0),
.ext2dtcm_icb_rsp_err (),
.ext2dtcm_icb_rsp_rdata (),
`endif//}
.sysper_icb_cmd_valid (sysper_icb_cmd_valid),
.sysper_icb_cmd_ready (sysper_icb_cmd_ready),
.sysper_icb_cmd_read (),
.sysper_icb_cmd_addr (),
.sysper_icb_cmd_wdata (),
.sysper_icb_cmd_wmask (),
.sysper_icb_rsp_valid (sysper_icb_cmd_valid),
.sysper_icb_rsp_ready (sysper_icb_cmd_ready),
.sysper_icb_rsp_err (1'b0 ),
.sysper_icb_rsp_rdata (32'b0),
.sysfio_icb_cmd_valid(sysfio_icb_cmd_valid),
.sysfio_icb_cmd_ready(sysfio_icb_cmd_ready),
.sysfio_icb_cmd_read (),
.sysfio_icb_cmd_addr (),
.sysfio_icb_cmd_wdata(),
.sysfio_icb_cmd_wmask(),
.sysfio_icb_rsp_valid(sysfio_icb_cmd_valid),
.sysfio_icb_rsp_ready(sysfio_icb_cmd_ready),
.sysfio_icb_rsp_err (1'b0 ),
.sysfio_icb_rsp_rdata(32'b0),
.sysmem_icb_cmd_valid(sysmem_icb_cmd_valid),
.sysmem_icb_cmd_ready(sysmem_icb_cmd_ready),
.sysmem_icb_cmd_read (),
.sysmem_icb_cmd_addr (),
.sysmem_icb_cmd_wdata(),
.sysmem_icb_cmd_wmask(),
.sysmem_icb_rsp_valid(sysmem_icb_cmd_valid),
.sysmem_icb_rsp_ready(sysmem_icb_cmd_ready),
.sysmem_icb_rsp_err (1'b0 ),
.sysmem_icb_rsp_rdata(32'b0),
.io_pads_jtag_TCK_i_ival (io_pads_jtag_TCK_i_ival ),
.io_pads_jtag_TCK_o_oval (),
.io_pads_jtag_TCK_o_oe (),
.io_pads_jtag_TCK_o_ie (),
.io_pads_jtag_TCK_o_pue (),
.io_pads_jtag_TCK_o_ds (),
.io_pads_jtag_TMS_i_ival (io_pads_jtag_TMS_i_ival ),
.io_pads_jtag_TMS_o_oval (),
.io_pads_jtag_TMS_o_oe (),
.io_pads_jtag_TMS_o_ie (),
.io_pads_jtag_TMS_o_pue (),
.io_pads_jtag_TMS_o_ds (),
.io_pads_jtag_TDI_i_ival (io_pads_jtag_TDI_i_ival ),
.io_pads_jtag_TDI_o_oval (),
.io_pads_jtag_TDI_o_oe (),
.io_pads_jtag_TDI_o_ie (),
.io_pads_jtag_TDI_o_pue (),
.io_pads_jtag_TDI_o_ds (),
.io_pads_jtag_TDO_i_ival (1'b1 ),
.io_pads_jtag_TDO_o_oval (io_pads_jtag_TDO_o_oval ),
.io_pads_jtag_TDO_o_oe (io_pads_jtag_TDO_o_oe ),
.io_pads_jtag_TDO_o_ie (),
.io_pads_jtag_TDO_o_pue (),
.io_pads_jtag_TDO_o_ds (),
.io_pads_jtag_TRST_n_i_ival (1'b1 ),
.io_pads_jtag_TRST_n_o_oval (),
.io_pads_jtag_TRST_n_o_oe (),
.io_pads_jtag_TRST_n_o_ie (),
.io_pads_jtag_TRST_n_o_pue (),
.io_pads_jtag_TRST_n_o_ds (),
.test_mode(1'b0),
.test_iso_override(1'b0),
.io_pads_gpioA_i_ival (io_pads_gpioA_i_ival),
.io_pads_gpioA_o_oval (io_pads_gpioA_o_oval),
.io_pads_gpioA_o_oe (io_pads_gpioA_o_oe),
.io_pads_gpioB_i_ival (io_pads_gpioB_i_ival),
.io_pads_gpioB_o_oval (io_pads_gpioB_o_oval),
.io_pads_gpioB_o_oe (io_pads_gpioB_o_oe),
.io_pads_qspi0_sck_i_ival (1'b1),
.io_pads_qspi0_sck_o_oval (io_pads_qspi0_sck_o_oval),
.io_pads_qspi0_sck_o_oe (),
.io_pads_qspi0_dq_0_i_ival (io_pads_qspi0_dq_0_i_ival),
.io_pads_qspi0_dq_0_o_oval (io_pads_qspi0_dq_0_o_oval),
.io_pads_qspi0_dq_0_o_oe (io_pads_qspi0_dq_0_o_oe),
.io_pads_qspi0_dq_1_i_ival (io_pads_qspi0_dq_1_i_ival),
.io_pads_qspi0_dq_1_o_oval (io_pads_qspi0_dq_1_o_oval),
.io_pads_qspi0_dq_1_o_oe (io_pads_qspi0_dq_1_o_oe),
.io_pads_qspi0_dq_2_i_ival (io_pads_qspi0_dq_2_i_ival),
.io_pads_qspi0_dq_2_o_oval (io_pads_qspi0_dq_2_o_oval),
.io_pads_qspi0_dq_2_o_oe (io_pads_qspi0_dq_2_o_oe),
.io_pads_qspi0_dq_3_i_ival (io_pads_qspi0_dq_3_i_ival),
.io_pads_qspi0_dq_3_o_oval (io_pads_qspi0_dq_3_o_oval),
.io_pads_qspi0_dq_3_o_oe (io_pads_qspi0_dq_3_o_oe),
.io_pads_qspi0_cs_0_i_ival (1'b1),
.io_pads_qspi0_cs_0_o_oval (io_pads_qspi0_cs_0_o_oval),
.io_pads_qspi0_cs_0_o_oe (),
.hfextclk (hfextclk),
.hfxoscen (hfxoscen),
.lfextclk (lfextclk),
.lfxoscen (lfxoscen),
.io_pads_aon_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_aon_erst_n_o_oval (),
.io_pads_aon_erst_n_o_oe (),
.io_pads_aon_erst_n_o_ie (),
.io_pads_aon_erst_n_o_pue (),
.io_pads_aon_erst_n_o_ds (),
.io_pads_aon_pmu_dwakeup_n_i_ival (io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval (),
.io_pads_aon_pmu_dwakeup_n_o_oe (),
.io_pads_aon_pmu_dwakeup_n_o_ie (),
.io_pads_aon_pmu_dwakeup_n_o_pue (),
.io_pads_aon_pmu_dwakeup_n_o_ds (),
.io_pads_aon_pmu_vddpaden_i_ival (1'b1 ),
.io_pads_aon_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_aon_pmu_vddpaden_o_oe (),
.io_pads_aon_pmu_vddpaden_o_ie (),
.io_pads_aon_pmu_vddpaden_o_pue (),
.io_pads_aon_pmu_vddpaden_o_ds (),
.io_pads_aon_pmu_padrst_i_ival (1'b1 ),
.io_pads_aon_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_aon_pmu_padrst_o_oe (),
.io_pads_aon_pmu_padrst_o_ie (),
.io_pads_aon_pmu_padrst_o_pue (),
.io_pads_aon_pmu_padrst_o_ds (),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (),
.io_pads_bootrom_n_o_oe (),
.io_pads_bootrom_n_o_ie (),
.io_pads_bootrom_n_o_pue (),
.io_pads_bootrom_n_o_ds (),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival)
);
endmodule |
module e203_lsu(
input commit_mret,
input commit_trap,
input excp_active,
output lsu_active,
`ifdef E203_HAS_ITCM //{
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
output lsu_o_valid, // Handshake valid
input lsu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] lsu_o_wbck_wdat,
output [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag,
output lsu_o_wbck_err ,
output lsu_o_cmt_ld,
output lsu_o_cmt_st,
output [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr,
output lsu_o_cmt_buserr , // The bus-error exception generated
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
input agu_icb_cmd_valid, // Handshake valid
output agu_icb_cmd_ready, // Handshake ready
input [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
input agu_icb_cmd_read, // Read or write
input [`E203_XLEN-1:0] agu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
input agu_icb_cmd_lock,
input agu_icb_cmd_excl,
input [1:0] agu_icb_cmd_size,
// Several additional side channel signals
// Indicate LSU-ctrl module to
// return the ICB response channel back to AGU
// this is only used by AMO or unaligned load/store 1st uop
// to return the response
input agu_icb_cmd_back2agu,
// Sign extension or not
input agu_icb_cmd_usign,
input [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
output agu_icb_rsp_valid, // Response valid
input agu_icb_rsp_ready, // Response ready
output agu_icb_rsp_err , // Response error
output agu_icb_rsp_excl_ok, // Response error
output [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output itcm_icb_cmd_valid,
input itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] itcm_icb_cmd_addr,
output itcm_icb_cmd_read,
output [`E203_XLEN-1:0] itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] itcm_icb_cmd_wmask,
output itcm_icb_cmd_lock,
output itcm_icb_cmd_excl,
output [1:0] itcm_icb_cmd_size,
//
// * Bus RSP channel
input itcm_icb_rsp_valid,
output itcm_icb_rsp_ready,
input itcm_icb_rsp_err ,
input itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output dtcm_icb_cmd_valid,
input dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] dtcm_icb_cmd_addr,
output dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] dtcm_icb_cmd_wmask,
output dtcm_icb_cmd_lock,
output dtcm_icb_cmd_excl,
output [1:0] dtcm_icb_cmd_size,
//
// * Bus RSP channel
input dtcm_icb_rsp_valid,
output dtcm_icb_rsp_ready,
input dtcm_icb_rsp_err ,
input dtcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to BIU
//
// * Bus cmd channel
output biu_icb_cmd_valid,
input biu_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] biu_icb_cmd_addr,
output biu_icb_cmd_read,
output [`E203_XLEN-1:0] biu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] biu_icb_cmd_wmask,
output biu_icb_cmd_lock,
output biu_icb_cmd_excl,
output [1:0] biu_icb_cmd_size,
//
// * Bus RSP channel
input biu_icb_rsp_valid,
output biu_icb_rsp_ready,
input biu_icb_rsp_err ,
input biu_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] biu_icb_rsp_rdata,
`ifdef E203_HAS_NICE//{
input nice_mem_holdup,
input nice_icb_cmd_valid,
output nice_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] nice_icb_cmd_addr,
input nice_icb_cmd_read,
input [`E203_XLEN-1:0] nice_icb_cmd_wdata,
input [`E203_XLEN_MW-1:0] nice_icb_cmd_wmask,
input nice_icb_cmd_lock,
input nice_icb_cmd_excl,
input [1:0] nice_icb_cmd_size,
output nice_icb_rsp_valid,
input nice_icb_rsp_ready,
output nice_icb_rsp_err ,
output nice_icb_rsp_excl_ok ,
output [`E203_XLEN-1:0] nice_icb_rsp_rdata,
`endif//}
input clk,
input rst_n
);
`ifdef E203_HAS_DCACHE //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DCache
//
// * Bus cmd channel
wire dcache_icb_cmd_valid;
wire dcache_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] dcache_icb_cmd_addr;
wire dcache_icb_cmd_read;
wire [`E203_XLEN-1:0] dcache_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] dcache_icb_cmd_wmask;
wire dcache_icb_cmd_lock;
wire dcache_icb_cmd_excl;
wire [1:0] dcache_icb_cmd_size;
//
// * Bus RSP channel
wire dcache_icb_rsp_valid;
wire dcache_icb_rsp_ready;
wire dcache_icb_rsp_err ;
wire dcache_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] dcache_icb_rsp_rdata;
`endif//}
wire lsu_ctrl_active;
e203_lsu_ctrl u_e203_lsu_ctrl(
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_ctrl_active (lsu_ctrl_active),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat),
.lsu_o_wbck_itag (lsu_o_wbck_itag),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld ),
.lsu_o_cmt_st (lsu_o_cmt_st ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock),
.agu_icb_cmd_excl (agu_icb_cmd_excl),
.agu_icb_cmd_size (agu_icb_cmd_size),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifdef E203_HAS_NICE//{
.nice_mem_holdup (nice_mem_holdup ),
.nice_icb_cmd_valid (nice_icb_cmd_valid),
.nice_icb_cmd_ready (nice_icb_cmd_ready),
.nice_icb_cmd_addr (nice_icb_cmd_addr ),
.nice_icb_cmd_read (nice_icb_cmd_read ),
.nice_icb_cmd_wdata (nice_icb_cmd_wdata),
.nice_icb_cmd_wmask (nice_icb_cmd_wmask),
.nice_icb_cmd_lock (1'b0),
.nice_icb_cmd_excl (1'b0),
.nice_icb_cmd_size (nice_icb_cmd_size),
.nice_icb_rsp_valid (nice_icb_rsp_valid),
.nice_icb_rsp_ready (nice_icb_rsp_ready),
.nice_icb_rsp_err (nice_icb_rsp_err ),
.nice_icb_rsp_excl_ok (nice_icb_rsp_excl_ok ),
.nice_icb_rsp_rdata (nice_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DCACHE
.dcache_icb_cmd_valid (dcache_icb_cmd_valid),
.dcache_icb_cmd_ready (dcache_icb_cmd_ready),
.dcache_icb_cmd_addr (dcache_icb_cmd_addr ),
.dcache_icb_cmd_read (dcache_icb_cmd_read ),
.dcache_icb_cmd_wdata (dcache_icb_cmd_wdata),
.dcache_icb_cmd_wmask (dcache_icb_cmd_wmask),
.dcache_icb_cmd_lock (dcache_icb_cmd_lock),
.dcache_icb_cmd_excl (dcache_icb_cmd_excl),
.dcache_icb_cmd_size (dcache_icb_cmd_size),
.dcache_icb_rsp_valid (dcache_icb_rsp_valid),
.dcache_icb_rsp_ready (dcache_icb_rsp_ready),
.dcache_icb_rsp_err (dcache_icb_rsp_err ),
.dcache_icb_rsp_excl_ok(dcache_icb_rsp_excl_ok ),
.dcache_icb_rsp_rdata (dcache_icb_rsp_rdata),
`endif
`ifdef E203_HAS_DTCM
.dtcm_icb_cmd_valid (dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (dtcm_icb_cmd_lock),
.dtcm_icb_cmd_excl (dtcm_icb_cmd_excl),
.dtcm_icb_cmd_size (dtcm_icb_cmd_size),
.dtcm_icb_rsp_valid (dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok (dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (dtcm_icb_rsp_rdata),
`endif
`ifdef E203_HAS_ITCM
.itcm_icb_cmd_valid (itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (itcm_icb_cmd_lock),
.itcm_icb_cmd_excl (itcm_icb_cmd_excl),
.itcm_icb_cmd_size (itcm_icb_cmd_size),
.itcm_icb_rsp_valid (itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (itcm_icb_rsp_ready),
.itcm_icb_rsp_err (itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok (itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (itcm_icb_rsp_rdata),
`endif
.biu_icb_cmd_valid (biu_icb_cmd_valid),
.biu_icb_cmd_ready (biu_icb_cmd_ready),
.biu_icb_cmd_addr (biu_icb_cmd_addr ),
.biu_icb_cmd_read (biu_icb_cmd_read ),
.biu_icb_cmd_wdata (biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (biu_icb_cmd_wmask),
.biu_icb_cmd_lock (biu_icb_cmd_lock),
.biu_icb_cmd_excl (biu_icb_cmd_excl),
.biu_icb_cmd_size (biu_icb_cmd_size),
.biu_icb_rsp_valid (biu_icb_rsp_valid),
.biu_icb_rsp_ready (biu_icb_rsp_ready),
.biu_icb_rsp_err (biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok (biu_icb_rsp_excl_ok ),
.biu_icb_rsp_rdata (biu_icb_rsp_rdata),
.clk (clk),
.rst_n (rst_n)
);
assign lsu_active = lsu_ctrl_active
// When interrupts comes, need to update the exclusive monitor
// so also need to turn on the clock
| excp_active;
endmodule |
module e203_exu_alu(
//////////////////////////////////////////////////////////////
// The operands and decode info from dispatch
input i_valid,
output i_ready,
output i_longpipe, // Indicate this instruction is
// issued as a long pipe instruction
`ifdef E203_HAS_CSR_NICE//{
output nice_csr_valid,
input nice_csr_ready,
output [31:0] nice_csr_addr,
output nice_csr_wr,
output [31:0] nice_csr_wdata,
input [31:0] nice_csr_rdata,
`endif//}
`ifdef E203_HAS_NICE//{
input nice_xs_off,
`endif//}
output amo_wait,
input oitf_empty,
input [`E203_ITAG_WIDTH-1:0] i_itag,
input [`E203_XLEN-1:0] i_rs1,
input [`E203_XLEN-1:0] i_rs2,
input [`E203_XLEN-1:0] i_imm,
input [`E203_DECINFO_WIDTH-1:0] i_info,
input [`E203_PC_SIZE-1:0] i_pc,
input [`E203_INSTR_SIZE-1:0] i_instr,
input i_pc_vld,
input [`E203_RFIDX_WIDTH-1:0] i_rdidx,
input i_rdwen,
input i_ilegl,
input i_buserr,
input i_misalgn,
input flush_req,
input flush_pulse,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Commit Interface
output cmt_o_valid, // Handshake valid
input cmt_o_ready, // Handshake ready
output cmt_o_pc_vld,
output [`E203_PC_SIZE-1:0] cmt_o_pc,
output [`E203_INSTR_SIZE-1:0] cmt_o_instr,
output [`E203_XLEN-1:0] cmt_o_imm,// The resolved ture/false
// The Branch and Jump Commit
output cmt_o_rv32,// The predicted ture/false
output cmt_o_bjp,
output cmt_o_mret,
output cmt_o_dret,
output cmt_o_ecall,
output cmt_o_ebreak,
output cmt_o_fencei,
output cmt_o_wfi,
output cmt_o_ifu_misalgn,
output cmt_o_ifu_buserr,
output cmt_o_ifu_ilegl,
output cmt_o_bjp_prdt,// The predicted ture/false
output cmt_o_bjp_rslv,// The resolved ture/false
// The AGU Exception
output cmt_o_misalgn, // The misalign exception generated
output cmt_o_ld,
output cmt_o_stamo,
output cmt_o_buserr , // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] cmt_o_badaddr,
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
output wbck_o_valid, // Handshake valid
input wbck_o_ready, // Handshake ready
output [`E203_XLEN-1:0] wbck_o_wdat,
output [`E203_RFIDX_WIDTH-1:0] wbck_o_rdidx,
input mdv_nob2b,
//////////////////////////////////////////////////////////////
// The CSR Interface
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input nonflush_cmt_ena,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_usign,
output [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_NICE//{
//////////////////////////////////////////////////////////////
// The nice interface
// * cmd channel
output nice_req_valid, // Handshake valid
input nice_req_ready, // Handshake ready
output [`E203_XLEN -1:0] nice_req_instr,
output [`E203_XLEN -1:0] nice_req_rs1,
output [`E203_XLEN -1:0] nice_req_rs2,
//output nice_req_mmode , // O: current insns' mmode
// * RSP channel will be directly pass to longp-wback module
input nice_rsp_multicyc_valid, //I: current insn is multi-cycle.
output nice_rsp_multicyc_ready, //O:
output nice_longp_wbck_valid, // Handshake valid
input nice_longp_wbck_ready, // Handshake ready
output [`E203_ITAG_WIDTH -1:0] nice_o_itag,
input i_nice_cmt_off_ilgl,
`endif//}
input clk,
input rst_n
);
//////////////////////////////////////////////////////////////
// Dispatch to different sub-modules according to their types
wire ifu_excp_op = i_ilegl | i_buserr | i_misalgn;
wire alu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_ALU);
wire agu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_AGU);
wire bjp_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_BJP);
wire csr_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_CSR);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_MULDIV);
`endif//E203_SUPPORT_SHARE_MULDIV}
`ifdef E203_HAS_NICE//{
wire nice_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_NICE);
`endif//}
// The ALU incoming instruction may go to several different targets:
// * The ALUDATAPATH if it is a regular ALU instructions
// * The Branch-cmp if it is a BJP instructions
// * The AGU if it is a load/store relevant instructions
// * The MULDIV if it is a MUL/DIV relevant instructions and MULDIV
// is reusing the ALU adder
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_valid = i_valid & mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_valid = i_valid & agu_op;
wire alu_i_valid = i_valid & alu_op;
wire bjp_i_valid = i_valid & bjp_op;
wire csr_i_valid = i_valid & csr_op;
wire ifu_excp_i_valid = i_valid & ifu_excp_op;
`ifdef E203_HAS_NICE//{
wire nice_i_valid = i_valid & nice_op;
wire nice_i_ready;
`endif//}
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_ready;
wire alu_i_ready;
wire bjp_i_ready;
wire csr_i_ready;
wire ifu_excp_i_ready;
assign i_ready = (agu_i_ready & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_ready & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
| (alu_i_ready & alu_op)
| (ifu_excp_i_ready & ifu_excp_op)
| (bjp_i_ready & bjp_op)
| (csr_i_ready & csr_op)
`ifdef E203_HAS_NICE//{
| (nice_i_ready & nice_op)
`endif//}
;
wire agu_i_longpipe;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_longpipe;
`endif//E203_SUPPORT_SHARE_MULDIV}
`ifdef E203_HAS_NICE//{
wire nice_o_longpipe;
wire nice_i_longpipe = nice_o_longpipe;
`endif//}
assign i_longpipe = (agu_i_longpipe & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_longpipe & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
`ifdef E203_HAS_NICE//{
| (nice_i_longpipe & nice_op)
`endif//}
;
//////////////////////////////////////////////////////////////
// Instantiate the CSR module
//
wire csr_o_valid;
wire csr_o_ready;
wire [`E203_XLEN-1:0] csr_o_wbck_wdat;
wire csr_o_wbck_err;
wire [`E203_XLEN-1:0] csr_i_rs1 = {`E203_XLEN {csr_op}} & i_rs1;
wire [`E203_XLEN-1:0] csr_i_rs2 = {`E203_XLEN {csr_op}} & i_rs2;
wire [`E203_XLEN-1:0] csr_i_imm = {`E203_XLEN {csr_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] csr_i_info = {`E203_DECINFO_WIDTH{csr_op}} & i_info;
wire csr_i_rdwen = csr_op & i_rdwen;
`ifdef E203_HAS_CSR_NICE//{
wire csr_sel_nice;
`endif//}
`ifdef E203_HAS_NICE//{
wire [`E203_XLEN-1:0] nice_i_rs1 = {`E203_XLEN {nice_op}} & i_rs1;
wire [`E203_XLEN-1:0] nice_i_rs2 = {`E203_XLEN {nice_op}} & i_rs2;
wire [`E203_ITAG_WIDTH-1:0] nice_i_itag = {`E203_ITAG_WIDTH {nice_op}} & i_itag;
wire nice_o_valid;
wire nice_o_ready;
//wire [`E203_XLEN-1:0] nice_o_wbck_wdat;
wire nice_o_wbck_err = i_nice_cmt_off_ilgl;
//wire nice_i_mmode = nice_op & i_mmode;
e203_exu_nice u_e203_exu_nice (
.nice_i_xs_off (nice_xs_off),
.nice_i_valid (nice_i_valid), // Handshake valid
.nice_i_ready (nice_i_ready), // Handshake ready
.nice_i_instr (i_instr),
.nice_i_rs1 (nice_i_rs1), // Handshake valid
.nice_i_rs2 (nice_i_rs2), // Handshake ready
//.nice_i_mmode (nice_i_mmode), // Handshake ready
.nice_i_itag (nice_i_itag),
.nice_o_longpipe (nice_o_longpipe),
// The nice Commit Interface
.nice_o_valid (nice_o_valid), // Handshake valid
.nice_o_ready (nice_o_ready), // Handshake ready
.nice_o_itag_valid (nice_longp_wbck_valid), // Handshake valid
.nice_o_itag_ready (nice_longp_wbck_ready), // Handshake ready
.nice_o_itag (nice_o_itag),
// The nice Response Interface
.nice_rsp_multicyc_valid(nice_rsp_multicyc_valid), //I: current insn is multi-cycle.
.nice_rsp_multicyc_ready(nice_rsp_multicyc_ready), //O:
// The nice Request Interface
.nice_req_valid (nice_req_valid), // Handshake valid
.nice_req_ready (nice_req_ready), // Handshake ready
.nice_req_instr (nice_req_instr), // Handshake ready
.nice_req_rs1 (nice_req_rs1), // Handshake valid
.nice_req_rs2 (nice_req_rs2), // Handshake ready
//.nice_req_mmode (nice_req_mmode), // Handshake ready
.clk (clk),
.rst_n (rst_n)
);
`endif//}
e203_exu_alu_csrctrl u_e203_exu_alu_csrctrl(
`ifdef E203_HAS_CSR_NICE//{
.nice_xs_off (nice_xs_off),
.csr_sel_nice (csr_sel_nice),
.nice_csr_valid (nice_csr_valid),
.nice_csr_ready (nice_csr_ready),
.nice_csr_addr (nice_csr_addr ),
.nice_csr_wr (nice_csr_wr ),
.nice_csr_wdata (nice_csr_wdata),
.nice_csr_rdata (nice_csr_rdata),
`endif//}
.csr_access_ilgl (csr_access_ilgl),
.csr_i_valid (csr_i_valid),
.csr_i_ready (csr_i_ready),
.csr_i_rs1 (csr_i_rs1 ),
.csr_i_info (csr_i_info[`E203_DECINFO_CSR_WIDTH-1:0]),
.csr_i_rdwen (csr_i_rdwen),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.csr_o_valid (csr_o_valid ),
.csr_o_ready (csr_o_ready ),
.csr_o_wbck_wdat (csr_o_wbck_wdat ),
.csr_o_wbck_err (csr_o_wbck_err ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the BJP module
//
wire bjp_o_valid;
wire bjp_o_ready;
wire [`E203_XLEN-1:0] bjp_o_wbck_wdat;
wire bjp_o_wbck_err;
wire bjp_o_cmt_bjp;
wire bjp_o_cmt_mret;
wire bjp_o_cmt_dret;
wire bjp_o_cmt_fencei;
wire bjp_o_cmt_prdt;
wire bjp_o_cmt_rslv;
wire [`E203_XLEN-1:0] bjp_req_alu_op1;
wire [`E203_XLEN-1:0] bjp_req_alu_op2;
wire bjp_req_alu_cmp_eq ;
wire bjp_req_alu_cmp_ne ;
wire bjp_req_alu_cmp_lt ;
wire bjp_req_alu_cmp_gt ;
wire bjp_req_alu_cmp_ltu;
wire bjp_req_alu_cmp_gtu;
wire bjp_req_alu_add;
wire bjp_req_alu_cmp_res;
wire [`E203_XLEN-1:0] bjp_req_alu_add_res;
wire [`E203_XLEN-1:0] bjp_i_rs1 = {`E203_XLEN {bjp_op}} & i_rs1;
wire [`E203_XLEN-1:0] bjp_i_rs2 = {`E203_XLEN {bjp_op}} & i_rs2;
wire [`E203_XLEN-1:0] bjp_i_imm = {`E203_XLEN {bjp_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] bjp_i_info = {`E203_DECINFO_WIDTH{bjp_op}} & i_info;
wire [`E203_PC_SIZE-1:0] bjp_i_pc = {`E203_PC_SIZE {bjp_op}} & i_pc;
e203_exu_alu_bjp u_e203_exu_alu_bjp(
.bjp_i_valid (bjp_i_valid ),
.bjp_i_ready (bjp_i_ready ),
.bjp_i_rs1 (bjp_i_rs1 ),
.bjp_i_rs2 (bjp_i_rs2 ),
.bjp_i_info (bjp_i_info[`E203_DECINFO_BJP_WIDTH-1:0]),
.bjp_i_imm (bjp_i_imm ),
.bjp_i_pc (bjp_i_pc ),
.bjp_o_valid (bjp_o_valid ),
.bjp_o_ready (bjp_o_ready ),
.bjp_o_wbck_wdat (bjp_o_wbck_wdat ),
.bjp_o_wbck_err (bjp_o_wbck_err ),
.bjp_o_cmt_bjp (bjp_o_cmt_bjp ),
.bjp_o_cmt_mret (bjp_o_cmt_mret ),
.bjp_o_cmt_dret (bjp_o_cmt_dret ),
.bjp_o_cmt_fencei (bjp_o_cmt_fencei ),
.bjp_o_cmt_prdt (bjp_o_cmt_prdt ),
.bjp_o_cmt_rslv (bjp_o_cmt_rslv ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the AGU module
//
wire agu_o_valid;
wire agu_o_ready;
wire [`E203_XLEN-1:0] agu_o_wbck_wdat;
wire agu_o_wbck_err;
wire agu_o_cmt_misalgn;
wire agu_o_cmt_ld;
wire agu_o_cmt_stamo;
wire agu_o_cmt_buserr ;
wire [`E203_ADDR_SIZE-1:0]agu_o_cmt_badaddr ;
wire [`E203_XLEN-1:0] agu_req_alu_op1;
wire [`E203_XLEN-1:0] agu_req_alu_op2;
wire agu_req_alu_swap;
wire agu_req_alu_add ;
wire agu_req_alu_and ;
wire agu_req_alu_or ;
wire agu_req_alu_xor ;
wire agu_req_alu_max ;
wire agu_req_alu_min ;
wire agu_req_alu_maxu;
wire agu_req_alu_minu;
wire [`E203_XLEN-1:0] agu_req_alu_res;
wire agu_sbf_0_ena;
wire [`E203_XLEN-1:0] agu_sbf_0_nxt;
wire [`E203_XLEN-1:0] agu_sbf_0_r;
wire agu_sbf_1_ena;
wire [`E203_XLEN-1:0] agu_sbf_1_nxt;
wire [`E203_XLEN-1:0] agu_sbf_1_r;
wire [`E203_XLEN-1:0] agu_i_rs1 = {`E203_XLEN {agu_op}} & i_rs1;
wire [`E203_XLEN-1:0] agu_i_rs2 = {`E203_XLEN {agu_op}} & i_rs2;
wire [`E203_XLEN-1:0] agu_i_imm = {`E203_XLEN {agu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] agu_i_info = {`E203_DECINFO_WIDTH{agu_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] agu_i_itag = {`E203_ITAG_WIDTH {agu_op}} & i_itag;
e203_exu_alu_lsuagu u_e203_exu_alu_lsuagu(
.agu_i_valid (agu_i_valid ),
.agu_i_ready (agu_i_ready ),
.agu_i_rs1 (agu_i_rs1 ),
.agu_i_rs2 (agu_i_rs2 ),
.agu_i_imm (agu_i_imm ),
.agu_i_info (agu_i_info[`E203_DECINFO_AGU_WIDTH-1:0]),
.agu_i_longpipe (agu_i_longpipe ),
.agu_i_itag (agu_i_itag ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.amo_wait (amo_wait),
.oitf_empty (oitf_empty),
.agu_o_valid (agu_o_valid ),
.agu_o_ready (agu_o_ready ),
.agu_o_wbck_wdat (agu_o_wbck_wdat ),
.agu_o_wbck_err (agu_o_wbck_err ),
.agu_o_cmt_misalgn (agu_o_cmt_misalgn ),
.agu_o_cmt_ld (agu_o_cmt_ld ),
.agu_o_cmt_stamo (agu_o_cmt_stamo ),
.agu_o_cmt_buserr (agu_o_cmt_buserr ),
.agu_o_cmt_badaddr (agu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the regular ALU module
//
wire alu_o_valid;
wire alu_o_ready;
wire [`E203_XLEN-1:0] alu_o_wbck_wdat;
wire alu_o_wbck_err;
wire alu_o_cmt_ecall;
wire alu_o_cmt_ebreak;
wire alu_o_cmt_wfi;
wire alu_req_alu_add ;
wire alu_req_alu_sub ;
wire alu_req_alu_xor ;
wire alu_req_alu_sll ;
wire alu_req_alu_srl ;
wire alu_req_alu_sra ;
wire alu_req_alu_or ;
wire alu_req_alu_and ;
wire alu_req_alu_slt ;
wire alu_req_alu_sltu;
wire alu_req_alu_lui ;
wire [`E203_XLEN-1:0] alu_req_alu_op1;
wire [`E203_XLEN-1:0] alu_req_alu_op2;
wire [`E203_XLEN-1:0] alu_req_alu_res;
wire [`E203_XLEN-1:0] alu_i_rs1 = {`E203_XLEN {alu_op}} & i_rs1;
wire [`E203_XLEN-1:0] alu_i_rs2 = {`E203_XLEN {alu_op}} & i_rs2;
wire [`E203_XLEN-1:0] alu_i_imm = {`E203_XLEN {alu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] alu_i_info = {`E203_DECINFO_WIDTH{alu_op}} & i_info;
wire [`E203_PC_SIZE-1:0] alu_i_pc = {`E203_PC_SIZE {alu_op}} & i_pc;
e203_exu_alu_rglr u_e203_exu_alu_rglr(
.alu_i_valid (alu_i_valid ),
.alu_i_ready (alu_i_ready ),
.alu_i_rs1 (alu_i_rs1 ),
.alu_i_rs2 (alu_i_rs2 ),
.alu_i_info (alu_i_info[`E203_DECINFO_ALU_WIDTH-1:0]),
.alu_i_imm (alu_i_imm ),
.alu_i_pc (alu_i_pc ),
.alu_o_valid (alu_o_valid ),
.alu_o_ready (alu_o_ready ),
.alu_o_wbck_wdat (alu_o_wbck_wdat ),
.alu_o_wbck_err (alu_o_wbck_err ),
.alu_o_cmt_ecall (alu_o_cmt_ecall ),
.alu_o_cmt_ebreak (alu_o_cmt_ebreak),
.alu_o_cmt_wfi (alu_o_cmt_wfi ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.clk (clk ),
.rst_n (rst_n )
);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
//////////////////////////////////////////////////////
// Instantiate the MULDIV module
wire [`E203_XLEN-1:0] mdv_i_rs1 = {`E203_XLEN {mdv_op}} & i_rs1;
wire [`E203_XLEN-1:0] mdv_i_rs2 = {`E203_XLEN {mdv_op}} & i_rs2;
wire [`E203_XLEN-1:0] mdv_i_imm = {`E203_XLEN {mdv_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] mdv_i_info = {`E203_DECINFO_WIDTH{mdv_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] mdv_i_itag = {`E203_ITAG_WIDTH {mdv_op}} & i_itag;
wire mdv_o_valid;
wire mdv_o_ready;
wire [`E203_XLEN-1:0] mdv_o_wbck_wdat;
wire mdv_o_wbck_err;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op1;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op2;
wire muldiv_req_alu_add ;
wire muldiv_req_alu_sub ;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_res;
wire muldiv_sbf_0_ena;
wire [33-1:0] muldiv_sbf_0_nxt;
wire [33-1:0] muldiv_sbf_0_r;
wire muldiv_sbf_1_ena;
wire [33-1:0] muldiv_sbf_1_nxt;
wire [33-1:0] muldiv_sbf_1_r;
e203_exu_alu_muldiv u_e203_exu_alu_muldiv(
.mdv_nob2b (mdv_nob2b),
.muldiv_i_valid (mdv_i_valid ),
.muldiv_i_ready (mdv_i_ready ),
.muldiv_i_rs1 (mdv_i_rs1 ),
.muldiv_i_rs2 (mdv_i_rs2 ),
.muldiv_i_imm (mdv_i_imm ),
.muldiv_i_info (mdv_i_info[`E203_DECINFO_MULDIV_WIDTH-1:0]),
.muldiv_i_longpipe (mdv_i_longpipe ),
.muldiv_i_itag (mdv_i_itag ),
.flush_pulse (flush_pulse ),
.muldiv_o_valid (mdv_o_valid ),
.muldiv_o_ready (mdv_o_ready ),
.muldiv_o_wbck_wdat (mdv_o_wbck_wdat),
.muldiv_o_wbck_err (mdv_o_wbck_err ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
.clk (clk ),
.rst_n (rst_n )
);
`endif//E203_SUPPORT_SHARE_MULDIV}
//////////////////////////////////////////////////////////////
// Instantiate the Shared Datapath module
//
wire alu_req_alu = alu_op & i_rdwen;// Regular ALU only req datapath when it need to write-back
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire muldiv_req_alu = mdv_op;// Since MULDIV have no point to let rd=0, so always need ALU datapath
`endif//E203_SUPPORT_SHARE_MULDIV}
wire bjp_req_alu = bjp_op;// Since BJP may not write-back, but still need ALU datapath
wire agu_req_alu = agu_op;// Since AGU may have some other features, so always need ALU datapath
e203_exu_alu_dpath u_e203_exu_alu_dpath(
.alu_req_alu (alu_req_alu ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.bjp_req_alu (bjp_req_alu ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.agu_req_alu (agu_req_alu ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
`ifdef E203_SUPPORT_SHARE_MULDIV //{
.muldiv_req_alu (muldiv_req_alu ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
`endif//E203_SUPPORT_SHARE_MULDIV}
.clk (clk ),
.rst_n (rst_n )
);
wire ifu_excp_o_valid;
wire ifu_excp_o_ready;
wire [`E203_XLEN-1:0] ifu_excp_o_wbck_wdat;
wire ifu_excp_o_wbck_err;
assign ifu_excp_i_ready = ifu_excp_o_ready;
assign ifu_excp_o_valid = ifu_excp_i_valid;
assign ifu_excp_o_wbck_wdat = `E203_XLEN'b0;
assign ifu_excp_o_wbck_err = 1'b1;// IFU illegal instruction always treat as error
//////////////////////////////////////////////////////////////
// Aribtrate the Result and generate output interfaces
//
wire o_valid;
wire o_ready;
wire o_sel_ifu_excp = ifu_excp_op;
wire o_sel_alu = alu_op;
wire o_sel_bjp = bjp_op;
wire o_sel_csr = csr_op;
wire o_sel_agu = agu_op;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire o_sel_mdv = mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
`ifdef E203_HAS_NICE//{
wire o_sel_nice = nice_op;
`endif//}
assign o_valid = (o_sel_alu & alu_o_valid )
| (o_sel_bjp & bjp_o_valid )
| (o_sel_csr & csr_o_valid )
| (o_sel_agu & agu_o_valid )
| (o_sel_ifu_excp & ifu_excp_o_valid)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (o_sel_mdv & mdv_o_valid )
`endif//E203_SUPPORT_SHARE_MULDIV}
`ifdef E203_HAS_NICE//{
| (o_sel_nice & nice_o_valid )
`endif//}
;
assign ifu_excp_o_ready = o_sel_ifu_excp & o_ready;
assign alu_o_ready = o_sel_alu & o_ready;
assign agu_o_ready = o_sel_agu & o_ready;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign mdv_o_ready = o_sel_mdv & o_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign bjp_o_ready = o_sel_bjp & o_ready;
assign csr_o_ready = o_sel_csr & o_ready;
`ifdef E203_HAS_NICE//{
assign nice_o_ready = o_sel_nice & o_ready;
`endif//}
assign wbck_o_wdat =
({`E203_XLEN{o_sel_alu}} & alu_o_wbck_wdat)
| ({`E203_XLEN{o_sel_bjp}} & bjp_o_wbck_wdat)
| ({`E203_XLEN{o_sel_csr}} & csr_o_wbck_wdat)
| ({`E203_XLEN{o_sel_agu}} & agu_o_wbck_wdat)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({`E203_XLEN{o_sel_mdv}} & mdv_o_wbck_wdat)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({`E203_XLEN{o_sel_ifu_excp}} & ifu_excp_o_wbck_wdat)
//| ({`E203_XLEN{o_sel_nice}} & nice_o_wbck_wdat)
;
assign wbck_o_rdidx = i_rdidx;
wire wbck_o_rdwen = i_rdwen;
wire wbck_o_err =
({1{o_sel_alu}} & alu_o_wbck_err)
| ({1{o_sel_bjp}} & bjp_o_wbck_err)
| ({1{o_sel_csr}} & csr_o_wbck_err)
| ({1{o_sel_agu}} & agu_o_wbck_err)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({1{o_sel_mdv}} & mdv_o_wbck_err)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({1{o_sel_ifu_excp}} & ifu_excp_o_wbck_err)
`ifdef E203_HAS_NICE//{
| ({1{o_sel_nice}} & nice_o_wbck_err)
`endif//}
;
// Each Instruction need to commit or write-back
// * The write-back only needed when the unit need to write-back
// the result (need to write RD), and it is not a long-pipe uop
// (need to be write back by its long-pipe write-back, not here)
// * Each instruction need to be commited
wire o_need_wbck = wbck_o_rdwen & (~i_longpipe) & (~wbck_o_err);
wire o_need_cmt = 1'b1;
assign o_ready =
(o_need_cmt ? cmt_o_ready : 1'b1)
& (o_need_wbck ? wbck_o_ready : 1'b1);
assign wbck_o_valid = o_need_wbck & o_valid & (o_need_cmt ? cmt_o_ready : 1'b1);
assign cmt_o_valid = o_need_cmt & o_valid & (o_need_wbck ? wbck_o_ready : 1'b1);
//
// The commint interface have some special signals
assign cmt_o_instr = i_instr;
assign cmt_o_pc = i_pc;
assign cmt_o_imm = i_imm;
assign cmt_o_rv32 = i_info[`E203_DECINFO_RV32];
// The cmt_o_pc_vld is used by the commit stage to check
// if current instruction is outputing a valid current PC
// to guarante the commit to flush pipeline safely, this
// vld only be asserted when:
// * There is a valid instruction here
// --- otherwise, the commit stage may use wrong PC
// value to stored in DPC or EPC
assign cmt_o_pc_vld =
// Otherwise, just use the i_pc_vld
i_pc_vld;
assign cmt_o_misalgn = (o_sel_agu & agu_o_cmt_misalgn)
;
assign cmt_o_ld = (o_sel_agu & agu_o_cmt_ld)
;
assign cmt_o_badaddr = ({`E203_ADDR_SIZE{o_sel_agu}} & agu_o_cmt_badaddr)
;
assign cmt_o_buserr = o_sel_agu & agu_o_cmt_buserr;
assign cmt_o_stamo = o_sel_agu & agu_o_cmt_stamo ;
assign cmt_o_bjp = o_sel_bjp & bjp_o_cmt_bjp;
assign cmt_o_mret = o_sel_bjp & bjp_o_cmt_mret;
assign cmt_o_dret = o_sel_bjp & bjp_o_cmt_dret;
assign cmt_o_bjp_prdt = o_sel_bjp & bjp_o_cmt_prdt;
assign cmt_o_bjp_rslv = o_sel_bjp & bjp_o_cmt_rslv;
assign cmt_o_fencei = o_sel_bjp & bjp_o_cmt_fencei;
assign cmt_o_ecall = o_sel_alu & alu_o_cmt_ecall;
assign cmt_o_ebreak = o_sel_alu & alu_o_cmt_ebreak;
assign cmt_o_wfi = o_sel_alu & alu_o_cmt_wfi;
assign cmt_o_ifu_misalgn = i_misalgn;
assign cmt_o_ifu_buserr = i_buserr;
assign cmt_o_ifu_ilegl = i_ilegl
| (o_sel_csr & csr_access_ilgl)
;
endmodule |
module e203_exu_nice(
input nice_i_xs_off,
input nice_i_valid, // Handshake valid
output nice_i_ready, // Handshake ready
input [`E203_XLEN-1:0] nice_i_instr,
input [`E203_XLEN-1:0] nice_i_rs1,
input [`E203_XLEN-1:0] nice_i_rs2,
//input nice_i_mmode , // O: current insns' mmode
input [`E203_ITAG_WIDTH-1:0] nice_i_itag,
output nice_o_longpipe,
// The nice Commit Interface
output nice_o_valid, // Handshake valid
input nice_o_ready, // Handshake ready
//////////////////////////////////////////////////////////////
// The nice write-back Interface
output nice_o_itag_valid, // Handshake valid
input nice_o_itag_ready, // Handshake ready
output [`E203_ITAG_WIDTH-1:0] nice_o_itag,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The nice Request Interface
input nice_rsp_multicyc_valid , //I: current insn is multi-cycle.
output nice_rsp_multicyc_ready , //O:
output nice_req_valid, // Handshake valid
input nice_req_ready, // Handshake ready
output [`E203_XLEN-1:0] nice_req_instr,
output [`E203_XLEN-1:0] nice_req_rs1,
output [`E203_XLEN-1:0] nice_req_rs2,
//output nice_req_mmode , // O: current insns' mmode
input clk,
input rst_n
);
//assign nice_req_mmode = nice_i_mmode;
wire nice_i_hsked = nice_i_valid & nice_i_ready;
// when there is a valid insn and the cmt is ready, then send out the insn.
wire nice_req_valid_pos = nice_i_valid & nice_o_ready;
assign nice_req_valid = ~nice_i_xs_off & nice_req_valid_pos;
// when nice is disable, its req_ready is assumed to 1.
wire nice_req_ready_pos = nice_i_xs_off ? 1'b1 : nice_req_ready;
// nice reports ready to decode when its cmt is ready and the nice core is ready.
assign nice_i_ready = nice_req_ready_pos & nice_o_ready ;
// the nice isns is about to cmt when it is truly a valid nice insn and the nice core has accepted.
assign nice_o_valid = nice_i_valid & nice_req_ready_pos;
wire fifo_o_vld;
assign nice_rsp_multicyc_ready = nice_o_itag_ready & fifo_o_vld;
assign nice_req_instr = nice_i_instr;
assign nice_req_rs1 = nice_i_rs1;
assign nice_req_rs2 = nice_i_rs2;
assign nice_o_longpipe = ~nice_i_xs_off;
wire itag_fifo_wen = nice_o_longpipe & (nice_req_valid & nice_req_ready);
wire itag_fifo_ren = nice_rsp_multicyc_valid & nice_rsp_multicyc_ready;
wire fifo_i_vld = itag_fifo_wen;
wire fifo_i_rdy;
wire [`E203_ITAG_WIDTH-1:0] fifo_i_dat = nice_i_itag;
wire fifo_o_rdy = itag_fifo_ren;
wire [`E203_ITAG_WIDTH-1:0] fifo_o_dat;
assign nice_o_itag_valid = fifo_o_vld & nice_rsp_multicyc_valid;
//assign nice_o_itag = {`E203_ITAG_WIDTH{nice_o_itag_valid}} & fifo_o_dat;
//ctrl path must be independent with data path to avoid timing-loop.
assign nice_o_itag = fifo_o_dat;
sirv_gnrl_fifo # (
.DP(4),
.DW(`E203_ITAG_WIDTH),
.CUT_READY(1)
) u_nice_itag_fifo(
.i_vld (fifo_i_vld),
.i_rdy (fifo_i_rdy),
.i_dat (fifo_i_dat),
.o_vld (fifo_o_vld),
.o_rdy (fifo_o_rdy),
.o_dat (fifo_o_dat),
.clk (clk ),
.rst_n (rst_n)
);
endmodule |
module e203_exu_alu_csrctrl(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input csr_i_valid, // Handshake valid
output csr_i_ready, // Handshake ready
input [`E203_XLEN-1:0] csr_i_rs1,
input [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
input csr_i_rdwen,
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
`ifdef E203_HAS_CSR_NICE//{
input nice_xs_off,
output csr_sel_nice,
output nice_csr_valid,
input nice_csr_ready,
output [31:0] nice_csr_addr,
output nice_csr_wr,
output [31:0] nice_csr_wdata,
input [31:0] nice_csr_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The CSR Write-back/Commit Interface
output csr_o_valid, // Handshake valid
input csr_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] csr_o_wbck_wdat,
output csr_o_wbck_err,
input clk,
input rst_n
);
`ifdef E203_HAS_CSR_NICE//{
// If accessed the NICE CSR range then we need to check if the NICE CSR is ready
assign csr_sel_nice = (csr_idx[11:8] == 4'hE);
wire sel_nice = csr_sel_nice & (~nice_xs_off);
wire addi_condi = sel_nice ? nice_csr_ready : 1'b1;
assign csr_o_valid = csr_i_valid
& addi_condi; // Need to make sure the nice_csr-ready is ready to make sure
// it can be sent to NICE and O interface same cycle
assign nice_csr_valid = sel_nice & csr_i_valid &
csr_o_ready;// Need to make sure the o-ready is ready to make sure
// it can be sent to NICE and O interface same cycle
assign csr_i_ready = sel_nice ? (nice_csr_ready & csr_o_ready) : csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = sel_nice ? nice_csr_rdata : read_csr_dat;
assign nice_csr_addr = csr_idx;
assign nice_csr_wr = csr_wr_en;
assign nice_csr_wdata = wbck_csr_dat;
`else//}{
wire sel_nice = 1'b0;
assign csr_o_valid = csr_i_valid;
assign csr_i_ready = csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = read_csr_dat;
`endif//}
wire csrrw = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
wire csrrs = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
wire csrrc = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
wire rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
wire rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
wire [4:0] zimm = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];
wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;
assign csr_rd_en = csr_i_valid &
(
(csrrw ? csr_i_rdwen : 1'b0) // the CSRRW only read when the destination reg need to be writen
| csrrs | csrrc // The set and clear operation always need to read CSR
);
assign csr_wr_en = csr_i_valid & (
csrrw // CSRRW always write the original RS1 value into the CSR
| ((csrrs | csrrc) & (~rs1is0)) // for CSRRS/RC, if the RS is x0, then should not really write
);
assign csr_idx = csridx;
assign csr_ena = csr_o_valid & csr_o_ready & (~sel_nice);
assign wbck_csr_dat =
({`E203_XLEN{csrrw}} & csr_op1)
| ({`E203_XLEN{csrrs}} & ( csr_op1 | read_csr_dat))
| ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));
endmodule |
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1en,
output dec_rs2en,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
e203_exu_decode u_e203_exu_decode(
.i_instr(instr),
.i_pc(`E203_PC_SIZE'b0),
.i_prdt_taken(1'b0),
.i_muldiv_b2b(1'b0),
.i_misalgn (1'b0),
.i_buserr (1'b0),
.dbg_mode (1'b0),
.dec_misalgn(),
.dec_buserr(),
.dec_ilegl(),
.dec_rs1x0(),
.dec_rs2x0(),
.dec_rs1en(dec_rs1en),
.dec_rs2en(dec_rs2en),
.dec_rdwen(),
.dec_rs1idx(dec_rs1idx),
.dec_rs2idx(dec_rs2idx),
.dec_rdidx(),
.dec_info(),
.dec_imm(),
.dec_pc(),
`ifdef E203_HAS_NICE//{
.dec_nice (),
.nice_xs_off(1'b0),
.nice_cmt_off_ilgl_o(),
`endif//}
.dec_mulhsu(dec_mulhsu),
.dec_mul (dec_mul ),
.dec_div (dec_div ),
.dec_rem (dec_rem ),
.dec_divu (dec_divu ),
.dec_remu (dec_remu ),
.dec_rv32(dec_rv32),
.dec_bjp (dec_bjp ),
.dec_jal (dec_jal ),
.dec_jalr(dec_jalr),
.dec_bxx (dec_bxx ),
.dec_jalr_rs1idx(dec_jalr_rs1idx),
.dec_bjp_imm (dec_bjp_imm )
);
endmodule |
module e203_cpu #(
parameter MASTER = 1
)(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
output core_wfi,
output tm_stop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// With the interface to debug module
//
// The interface with commit stage
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output dbg_irq_r,
// The interface with CSR control
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
/////////////////////////////////////////////////////
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_a,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
`ifdef E203_HAS_ITCM //{
//input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
//input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM//{
output itcm_ls,
output itcm_ram_cs,
output itcm_ram_we,
output [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
output [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
output clk_itcm_ram,
`endif//}
`ifdef E203_HAS_DTCM//{
output dtcm_ls,
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
`endif//}
input test_mode,
input clk,
input rst_n
);
wire core_cgstop;
wire tcm_cgstop;
wire core_ifu_active;
wire core_exu_active;
wire core_lsu_active;
wire core_biu_active;
// The core's clk and rst
wire rst_core;
wire clk_core_ifu;
wire clk_core_exu;
wire clk_core_lsu;
wire clk_core_biu;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
wire clk_itcm;
wire itcm_active;
`endif
`ifdef E203_HAS_DTCM
wire clk_dtcm;
wire dtcm_active;
`endif
// The Top always on clk and rst
wire rst_aon;
wire clk_aon;
// The reset ctrl and clock ctrl should be in the power always-on domain
e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
.clk (clk_aon ),
.rst_n (rst_n ),
.test_mode (test_mode),
.rst_core (rst_core),
`ifdef E203_HAS_ITCM
.rst_itcm (rst_itcm),
`endif
`ifdef E203_HAS_DTCM
.rst_dtcm (rst_dtcm),
`endif
.rst_aon (rst_aon)
);
e203_clk_ctrl u_e203_clk_ctrl(
.clk (clk ),
.rst_n (rst_aon ),
.test_mode (test_mode ),
.clk_aon (clk_aon ),
.core_cgstop (core_cgstop),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
`ifdef E203_HAS_ITCM
.clk_itcm (clk_itcm ),
.itcm_active (itcm_active),
.itcm_ls (itcm_ls ),
`endif
`ifdef E203_HAS_DTCM
.clk_dtcm (clk_dtcm ),
.dtcm_active (dtcm_active),
.dtcm_ls (dtcm_ls ),
`endif
.core_ifu_active(core_ifu_active),
.core_exu_active(core_exu_active),
.core_lsu_active(core_lsu_active),
.core_biu_active(core_biu_active),
.core_wfi (core_wfi )
);
wire ext_irq_r;
wire sft_irq_r;
wire tmr_irq_r;
e203_irq_sync #(.MASTER(MASTER)) u_e203_irq_sync(
.clk (clk_aon ),
.rst_n (rst_aon ),
.dbg_irq_a (dbg_irq_a),
.dbg_irq_r (dbg_irq_r),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r)
);
`ifdef E203_HAS_ITCM //{
wire ifu2itcm_holdup;
//wire ifu2itcm_replay;
wire ifu2itcm_icb_cmd_valid;
wire ifu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr;
wire ifu2itcm_icb_rsp_valid;
wire ifu2itcm_icb_rsp_ready;
wire ifu2itcm_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata;
wire lsu2itcm_icb_cmd_valid;
wire lsu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr;
wire lsu2itcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask;
wire lsu2itcm_icb_cmd_lock;
wire lsu2itcm_icb_cmd_excl;
wire [1:0] lsu2itcm_icb_cmd_size;
wire lsu2itcm_icb_rsp_valid;
wire lsu2itcm_icb_rsp_ready;
wire lsu2itcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_DTCM //{
wire lsu2dtcm_icb_cmd_valid;
wire lsu2dtcm_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr;
wire lsu2dtcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask;
wire lsu2dtcm_icb_cmd_lock;
wire lsu2dtcm_icb_cmd_excl;
wire [1:0] lsu2dtcm_icb_cmd_size;
wire lsu2dtcm_icb_rsp_valid;
wire lsu2dtcm_icb_rsp_ready;
wire lsu2dtcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_CSR_NICE//{
wire nice_csr_valid;
wire nice_csr_ready;
wire [31:0] nice_csr_addr;
wire nice_csr_wr;
wire [31:0] nice_csr_wdata;
wire [31:0] nice_csr_rdata;
// This is an empty module to just connect the NICE CSR interface,
// user can hack it to become a real one
e203_extend_csr u_e203_extend_csr(
.nice_csr_valid (nice_csr_valid),
.nice_csr_ready (nice_csr_ready),
.nice_csr_addr (nice_csr_addr ),
.nice_csr_wr (nice_csr_wr ),
.nice_csr_wdata (nice_csr_wdata),
.nice_csr_rdata (nice_csr_rdata),
.clk (clk_core_exu ),
.rst_n (rst_core )
);
`endif//}
`ifdef E203_HAS_NICE//{
/* input */ wire nice_mem_holdup ;
/* output*/ wire nice_req_valid ;
/* input */ wire nice_req_ready ;
/* output*/ wire [`E203_XLEN-1:0] nice_req_inst ;
/* output*/ wire [`E203_XLEN-1:0] nice_req_rs1 ;
/* output*/ wire [`E203_XLEN-1:0] nice_req_rs2 ;
/* input */ wire nice_rsp_multicyc_valid ;
/* output*/ wire nice_rsp_multicyc_ready ;
/* input */ wire [`E203_XLEN-1:0] nice_rsp_multicyc_dat ;
/* input */ wire nice_rsp_multicyc_err ;
/* input */ wire nice_icb_cmd_valid ;
/* output*/ wire nice_icb_cmd_ready ;
/* input */ wire [`E203_XLEN-1:0] nice_icb_cmd_addr ;
/* input */ wire nice_icb_cmd_read ;
/* input */ wire [`E203_XLEN-1:0] nice_icb_cmd_wdata ;
/* input */ wire [1:0] nice_icb_cmd_size ;
/* output*/ wire nice_icb_rsp_valid ;
/* input */ wire nice_icb_rsp_ready ;
/* output*/ wire [`E203_XLEN-1:0] nice_icb_rsp_rdata ;
/* output*/ wire nice_icb_rsp_err ;
e203_subsys_nice_core u_e203_nice_core (
.nice_clk (clk_aon),
.nice_rst_n (rst_aon),
.nice_active (),
.nice_mem_holdup (nice_mem_holdup),
.nice_req_valid (nice_req_valid),
.nice_req_ready (nice_req_ready),
.nice_req_inst (nice_req_inst),
.nice_req_rs1 (nice_req_rs1),
.nice_req_rs2 (nice_req_rs2),
.nice_rsp_valid (nice_rsp_multicyc_valid),
.nice_rsp_ready (nice_rsp_multicyc_ready),
.nice_rsp_rdat (nice_rsp_multicyc_dat),
.nice_rsp_err (nice_rsp_multicyc_err),
.nice_icb_cmd_valid (nice_icb_cmd_valid),
.nice_icb_cmd_ready (nice_icb_cmd_ready),
.nice_icb_cmd_addr (nice_icb_cmd_addr),
.nice_icb_cmd_read (nice_icb_cmd_read),
.nice_icb_cmd_wdata (nice_icb_cmd_wdata),
.nice_icb_cmd_size (nice_icb_cmd_size),
.nice_icb_rsp_valid (nice_icb_rsp_valid),
.nice_icb_rsp_ready (nice_icb_rsp_ready),
.nice_icb_rsp_rdata (nice_icb_rsp_rdata),
.nice_icb_rsp_err (nice_icb_rsp_err)
);
`endif//}
e203_core u_e203_core(
.inspect_pc (inspect_pc),
`ifdef E203_HAS_CSR_NICE//{
.nice_csr_valid (nice_csr_valid),
.nice_csr_ready (nice_csr_ready),
.nice_csr_addr (nice_csr_addr ),
.nice_csr_wr (nice_csr_wr ),
.nice_csr_wdata (nice_csr_wdata),
.nice_csr_rdata (nice_csr_rdata),
`endif//}
.tcm_cgstop (tcm_cgstop),
.core_cgstop (core_cgstop),
.tm_stop (tm_stop),
.pc_rtvec (pc_rtvec),
.ifu_active (core_ifu_active),
.exu_active (core_exu_active),
.lsu_active (core_lsu_active),
.biu_active (core_biu_active),
.core_wfi (core_wfi),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (`E203_LIRQ_NUM'b0),// Not implemented now
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (`E203_EVT_NUM'b0),// Not implemented now
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r ),
.dbg_step_r (dbg_step_r ),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
`ifdef E203_HAS_ITCM //{
//.itcm_region_indic (itcm_region_indic),
.itcm_region_indic (`E203_ITCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_DTCM //{
//.dtcm_region_indic (dtcm_region_indic),
.dtcm_region_indic (`E203_DTCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.lsu2itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.lsu2itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_excl_ok(1'b0),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.lsu2dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.lsu2dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_excl_ok(1'b0),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.ppi_icb_enable (ppi_icb_enable),
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic ),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst ),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_NICE//{
///////////////////////////////////////////
// The nice interface
.nice_mem_holdup (nice_mem_holdup), //I: nice occupys the memory. for avoid of dead-loop.
// nice_req interface
.nice_req_valid (nice_req_valid ), //O: handshake flag, cmd is valid
.nice_req_ready (nice_req_ready ), //I: handshake flag, cmd is accepted.
.nice_req_inst (nice_req_inst ), // O: inst sent to nice.
.nice_req_rs1 (nice_req_rs1 ), // O: rs op 1.
.nice_req_rs2 (nice_req_rs2 ), // O: rs op 2.
//.nice_req_mmode (nice_req_mmode ), // O:
// icb_cmd_rsp interface
// for one cycle insn, the rsp data is valid at the same time of insn, so
// the handshake flags is useless.
.nice_rsp_multicyc_valid (nice_rsp_multicyc_valid), //I: current insn is multi-cycle.
.nice_rsp_multicyc_ready (nice_rsp_multicyc_ready), //I: current insn is multi-cycle.
.nice_rsp_multicyc_dat (nice_rsp_multicyc_dat ), //I: one cycle result write-back val.
.nice_rsp_multicyc_err (nice_rsp_multicyc_err ),
// lsu_req interface
.nice_icb_cmd_valid (nice_icb_cmd_valid), //I: nice access main-mem req valid.
.nice_icb_cmd_ready (nice_icb_cmd_ready),// O: nice access req is accepted.
.nice_icb_cmd_addr (nice_icb_cmd_addr ), //I : nice access main-mem address.
.nice_icb_cmd_read (nice_icb_cmd_read ), //I: nice access type.
.nice_icb_cmd_wdata (nice_icb_cmd_wdata),//I: nice write data.
.nice_icb_cmd_size (nice_icb_cmd_size), //I: data size input.
// lsu_rsp interface
.nice_icb_rsp_valid (nice_icb_rsp_valid), // O: main core responds result to nice.
.nice_icb_rsp_ready (nice_icb_rsp_ready), // I: respond result is accepted.
.nice_icb_rsp_rdata (nice_icb_rsp_rdata ), // O: rsp data.
.nice_icb_rsp_err (nice_icb_rsp_err), // O: err flag
`endif//}
.clk_aon (clk_aon ),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
.test_mode (test_mode),
.rst_n (rst_core )
);
`ifdef E203_HAS_ITCM //{
e203_itcm_ctrl u_e203_itcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.itcm_active (itcm_active),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_cmd_read (1'b1 ),
.ifu2itcm_icb_cmd_wdata ({`E203_ITCM_DATA_WIDTH{1'b0}}),
.ifu2itcm_icb_cmd_wmask ({`E203_ITCM_DATA_WIDTH/8{1'b0}}),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_itcm),
.rst_n (rst_itcm)
);
`endif//}
`ifdef E203_HAS_DTCM //{
e203_dtcm_ctrl u_e203_dtcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.dtcm_active (dtcm_active),
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_dtcm),
.rst_n (rst_dtcm)
);
`endif//}
assign inspect_dbg_irq = dbg_irq_a;
assign inspect_mem_cmd_valid = mem_icb_cmd_valid;
assign inspect_mem_cmd_ready = mem_icb_cmd_ready;
assign inspect_mem_rsp_valid = mem_icb_rsp_valid;
assign inspect_mem_rsp_ready = mem_icb_rsp_ready;
assign inspect_core_clk = clk;
assign core_csr_clk = clk_core_exu;
endmodule |
module e203_core(
output[`E203_PC_SIZE-1:0] inspect_pc,
`ifdef E203_HAS_CSR_NICE//{
output nice_csr_valid,
input nice_csr_ready,
output [31:0] nice_csr_addr,
output nice_csr_wr,
output [31:0] nice_csr_wdata,
input [31:0] nice_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
`ifdef E203_HAS_ITCM //{
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
input ifu2itcm_holdup,
//input ifu2itcm_replay,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output lsu2itcm_icb_cmd_valid,
input lsu2itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr,
output lsu2itcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask,
output lsu2itcm_icb_cmd_lock,
output lsu2itcm_icb_cmd_excl,
output [1:0] lsu2itcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2itcm_icb_rsp_valid,
output lsu2itcm_icb_rsp_ready,
input lsu2itcm_icb_rsp_err ,
input lsu2itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output lsu2dtcm_icb_cmd_valid,
input lsu2dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr,
output lsu2dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask,
output lsu2dtcm_icb_cmd_lock,
output lsu2dtcm_icb_cmd_excl,
output [1:0] lsu2dtcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2dtcm_icb_rsp_valid,
output lsu2dtcm_icb_rsp_ready,
input lsu2dtcm_icb_rsp_err ,
input lsu2dtcm_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_NICE//{
input nice_mem_holdup , //O: nice occupys the memory. for avoid of dead-loop庐
// nice_req interface
output nice_req_valid , //O: handshake flag, cmd is valid
input nice_req_ready , //I: handshake flag, cmd is accepted.
output [`E203_XLEN-1:0] nice_req_inst , // O: inst sent to nice.
output [`E203_XLEN-1:0] nice_req_rs1 , // O: rs op 1.
output [`E203_XLEN-1:0] nice_req_rs2 , // O: rs op 2.
//output nice_req_mmode , // O: current insns' mmode
// icb_cmd_rsp interface
// for one cycle insn, the rsp data is valid at the same time of insn, so
// the handshake flags is useless.
input nice_rsp_multicyc_valid , //I: current insn is multi-cycle.
output nice_rsp_multicyc_ready , //O: current insn is multi-cycle.
input [`E203_XLEN-1:0] nice_rsp_multicyc_dat , //I: one cycle result write-back val.
input nice_rsp_multicyc_err,
// lsu_req interface
input nice_icb_cmd_valid , //I: nice access main-mem req valid.
output nice_icb_cmd_ready ,// O: nice access req is accepted.
input [`E203_XLEN-1:0] nice_icb_cmd_addr , //I : nice access main-mem address.
input nice_icb_cmd_read , //I: nice access type.
input [`E203_XLEN-1:0] nice_icb_cmd_wdata ,//I: nice write data.
input [1:0] nice_icb_cmd_size , //I: data size input.
// lsu_rsp interface
output nice_icb_rsp_valid , //O: main core responds result to nice.
input nice_icb_rsp_ready ,// I: respond result is accepted.
output [`E203_XLEN-1:0] nice_icb_rsp_rdata ,// O: rsp data.
output nice_icb_rsp_err , // O : err flag
`endif//}
output exu_active,
output ifu_active,
output lsu_active,
output biu_active,
input clk_core_ifu,
input clk_core_exu,
input clk_core_lsu,
input clk_core_biu,
input clk_aon,
input test_mode,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
wire ifu2biu_icb_cmd_valid;
wire ifu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr;
wire ifu2biu_icb_rsp_valid;
wire ifu2biu_icb_rsp_ready;
wire ifu2biu_icb_rsp_err ;
wire ifu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata;
`endif//}
wire ifu_o_valid;
wire ifu_o_ready;
wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
wire [`E203_PC_SIZE-1:0] ifu_o_pc;
wire ifu_o_pc_vld;
wire ifu_o_misalgn;
wire ifu_o_buserr;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_o_muldiv_b2b;
wire wfi_halt_ifu_req;
wire wfi_halt_ifu_ack;
wire pipe_flush_ack;
wire pipe_flush_req;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] pipe_flush_pc;
`endif//}
wire oitf_empty;
wire [`E203_XLEN-1:0] rf2ifu_x1;
wire [`E203_XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
wire dec2ifu_mulhsu;
wire dec2ifu_div ;
wire dec2ifu_rem ;
wire dec2ifu_divu ;
wire dec2ifu_remu ;
wire itcm_nohold;
e203_ifu u_e203_ifu(
.inspect_pc (inspect_pc),
.ifu_active (ifu_active),
.pc_rtvec (pc_rtvec),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
// The ITCM address region indication signal
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn ),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx ),
.ifu_o_rs2idx (ifu_o_rs2idx ),
.ifu_o_prdt_taken (ifu_o_prdt_taken ),
.ifu_o_muldiv_b2b (ifu_o_muldiv_b2b ),
.ifu_halt_req (wfi_halt_ifu_req),
.ifu_halt_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk_core_ifu ),
.rst_n (rst_n )
);
wire lsu_o_valid;
wire lsu_o_ready;
wire [`E203_XLEN-1:0] lsu_o_wbck_wdat;
wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
wire lsu_o_wbck_err ;
wire lsu_o_cmt_buserr ;
wire lsu_o_cmt_ld;
wire lsu_o_cmt_st;
wire [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr;
wire agu_icb_cmd_valid;
wire agu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr;
wire agu_icb_cmd_read;
wire [`E203_XLEN-1:0] agu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] agu_icb_cmd_wmask;
wire agu_icb_cmd_lock;
wire agu_icb_cmd_excl;
wire [1:0] agu_icb_cmd_size;
wire agu_icb_cmd_back2agu;
wire agu_icb_cmd_usign;
wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
wire agu_icb_rsp_valid;
wire agu_icb_rsp_ready;
wire agu_icb_rsp_err ;
wire agu_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] agu_icb_rsp_rdata;
wire commit_mret;
wire commit_trap;
wire excp_active;
e203_exu u_e203_exu(
`ifdef E203_HAS_CSR_NICE//{
.nice_csr_valid (nice_csr_valid),
.nice_csr_ready (nice_csr_ready),
.nice_csr_addr (nice_csr_addr ),
.nice_csr_wr (nice_csr_wr ),
.nice_csr_wdata (nice_csr_wdata),
.nice_csr_rdata (nice_csr_rdata),
`endif//}
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.test_mode (test_mode),
.core_wfi (core_wfi),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop),
.exu_active (exu_active),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r ),
.ext_irq_r (ext_irq_r ),
.sft_irq_r (sft_irq_r ),
.tmr_irq_r (tmr_irq_r ),
.evt_r (evt_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.i_valid (ifu_o_valid ),
.i_ready (ifu_o_ready ),
.i_ir (ifu_o_ir ),
.i_pc (ifu_o_pc ),
.i_pc_vld (ifu_o_pc_vld ),
.i_misalgn (ifu_o_misalgn ),
.i_buserr (ifu_o_buserr ),
.i_rs1idx (ifu_o_rs1idx ),
.i_rs2idx (ifu_o_rs2idx ),
.i_prdt_taken (ifu_o_prdt_taken ),
.i_muldiv_b2b (ifu_o_muldiv_b2b ),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
`ifdef E203_HAS_NICE//{
.nice_req_valid (nice_req_valid ), //O: handshake flag, cmd is valid
.nice_req_ready (nice_req_ready ), //I: handshake flag, cmd is accepted.
.nice_req_inst (nice_req_inst ), // O: inst sent to nice.
.nice_req_rs1 (nice_req_rs1 ), // O: rs op 1.
.nice_req_rs2 (nice_req_rs2 ), // O: rs op 2.
//.nice_req_mmode (nice_req_mmode ), // O: rs op 2.
.nice_rsp_multicyc_valid (nice_rsp_multicyc_valid), //I: current insn is multi-cycle.
.nice_rsp_multicyc_ready (nice_rsp_multicyc_ready), //I: current insn is multi-cycle.
.nice_rsp_multicyc_dat (nice_rsp_multicyc_dat), //I: one cycle result write-back val.
.nice_rsp_multicyc_err (nice_rsp_multicyc_err ),
`endif//}
.clk_aon (clk_aon),
.clk (clk_core_exu),
.rst_n (rst_n )
);
wire lsu2biu_icb_cmd_valid;
wire lsu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr;
wire lsu2biu_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask;
wire lsu2biu_icb_cmd_lock;
wire lsu2biu_icb_cmd_excl;
wire [1:0] lsu2biu_icb_cmd_size;
wire lsu2biu_icb_rsp_valid;
wire lsu2biu_icb_rsp_ready;
wire lsu2biu_icb_rsp_err ;
wire lsu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata;
e203_lsu u_e203_lsu(
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_active (lsu_active),
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
.dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
`ifdef E203_HAS_NICE//{
.nice_mem_holdup (nice_mem_holdup),
.nice_icb_cmd_valid (nice_icb_cmd_valid),
.nice_icb_cmd_ready (nice_icb_cmd_ready),
.nice_icb_cmd_addr (nice_icb_cmd_addr ),
.nice_icb_cmd_read (nice_icb_cmd_read ),
.nice_icb_cmd_wdata (nice_icb_cmd_wdata),
.nice_icb_cmd_size (nice_icb_cmd_size),
.nice_icb_cmd_wmask (`E203_XLEN_MW'b0),
.nice_icb_cmd_lock (1'b0),
.nice_icb_cmd_excl (1'b0),
.nice_icb_rsp_valid (nice_icb_rsp_valid),
.nice_icb_rsp_ready (nice_icb_rsp_ready),
.nice_icb_rsp_rdata (nice_icb_rsp_rdata),
.nice_icb_rsp_err (nice_icb_rsp_err),
.nice_icb_rsp_excl_ok(),
`endif//}
.clk (clk_core_lsu ),
.rst_n (rst_n )
);
e203_biu u_e203_biu(
.biu_active (biu_active),
.lsu2biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.lsu2biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.lsu2biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.lsu2biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.lsu2biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.lsu2biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.lsu2biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.lsu2biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.lsu2biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.lsu2biu_icb_cmd_burst (2'b0),
.lsu2biu_icb_cmd_beat (2'b0 ),
.lsu2biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.lsu2biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.lsu2biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.lsu2biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_cmd_read (1'b1 ),
.ifu2biu_icb_cmd_wdata (`E203_XLEN'b0),
.ifu2biu_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.ifu2biu_icb_cmd_lock (1'b0 ),
.ifu2biu_icb_cmd_excl (1'b0 ),
.ifu2biu_icb_cmd_size (2'b10),
.ifu2biu_icb_cmd_burst (2'b0),
.ifu2biu_icb_cmd_beat (2'b0),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_cmd_burst (),
.ppi_icb_cmd_beat (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_cmd_burst (),
.plic_icb_cmd_beat (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_cmd_burst (),
.clint_icb_cmd_beat (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_region_indic (fio_region_indic ),
.fio_icb_enable (fio_icb_enable),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_cmd_burst (),
.fio_icb_cmd_beat (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok (mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk (clk_core_biu ),
.rst_n (rst_n )
);
endmodule |
module e203_extend_csr(
// The Handshake Interface
input nice_csr_valid,
output nice_csr_ready,
input [31:0] nice_csr_addr,
input nice_csr_wr,
input [31:0] nice_csr_wdata,
output [31:0] nice_csr_rdata,
input clk,
input rst_n
);
assign nice_csr_ready = 1'b1;
assign nice_csr_rdata = 32'b0;
endmodule |
module io_generic_fifo
#(
parameter DATA_WIDTH = 32,
parameter BUFFER_DEPTH = 2,
parameter LOG_BUFFER_DEPTH = $clog2(BUFFER_DEPTH)
)
(
input wire clk_i,
input wire rstn_i,
input wire clr_i,
output wire [LOG_BUFFER_DEPTH:0] elements_o,
output wire [DATA_WIDTH - 1:0] data_o,
output wire valid_o,
input wire ready_i,
input wire valid_i,
input wire [DATA_WIDTH - 1:0] data_i,
output wire ready_o
);
// Internal data structures
reg [LOG_BUFFER_DEPTH - 1:0] pointer_in; // location to which we last wrote
reg [LOG_BUFFER_DEPTH - 1:0] pointer_out; // location from which we last sent
reg [LOG_BUFFER_DEPTH:0] elements; // number of elements in the buffer
reg [DATA_WIDTH - 1:0] buffer [BUFFER_DEPTH - 1:0];
wire full;
assign full = (elements == BUFFER_DEPTH);
assign elements_o = elements;
always @(posedge clk_i or negedge rstn_i) begin : elements_sequential
if (rstn_i == 1'b0)
elements <= 0;
else if (clr_i)
elements <= 0;
// ------------------
// Are we filling up?
// ------------------
// One out, none in
else if ((ready_i && valid_o) && (!valid_i || full))
elements <= elements - 1;
// None out, one in
else if (((!valid_o || !ready_i) && valid_i) && !full)
elements <= elements + 1;
// Else, either one out and one in, or none out and none in - stays unchanged
end
integer loop1;
always @(posedge clk_i or negedge rstn_i) begin : buffers_sequential
if (rstn_i == 1'b0) begin
for (loop1 = 0; loop1 < BUFFER_DEPTH; loop1 = loop1 + 1) begin
buffer[loop1] <= 0;
end
end else if (valid_i && !full) begin
buffer[pointer_in] <= data_i; // Update the memory
end
end
always @(posedge clk_i or negedge rstn_i) begin : sequential
if (rstn_i == 1'b0) begin
pointer_out <= 0;
pointer_in <= 0;
end else if (clr_i) begin
pointer_out <= 0;
pointer_in <= 0;
end else begin
// ------------------------------------
// Check what to do with the input side
// ------------------------------------
// We have some input, increase by 1 the input pointer
if (valid_i && !full) begin
if (pointer_in == $unsigned(BUFFER_DEPTH - 1))
pointer_in <= 0;
else
pointer_in <= pointer_in + 1;
end
// Else we don't have any input, the input pointer stays the same
// -------------------------------------
// Check what to do with the output side
// -------------------------------------
// We had pushed one flit out, we can try to go for the next one
if (ready_i && valid_o) begin
if (pointer_out == $unsigned(BUFFER_DEPTH - 1))
pointer_out <= 0;
else
pointer_out <= pointer_out + 1;
end
// Else stay on the same output location
end
end
// Update output ports
assign data_o = buffer[pointer_out];
assign valid_o = (elements != 0);
assign ready_o = ~full;
endmodule |
module uart_rx (
input wire clk_i,
input wire rstn_i,
input wire rx_i,
input wire [15:0] cfg_div_i,
input wire cfg_en_i,
input wire cfg_parity_en_i,
input wire [1:0] cfg_parity_sel_i,
input wire [1:0] cfg_bits_i,
// input wire cfg_stop_bits_i,
output wire busy_o,
output reg err_o,
input wire err_clr_i,
output wire [7:0] rx_data_o,
output reg rx_valid_o,
input wire rx_ready_i
);
localparam [2:0] IDLE = 0;
localparam [2:0] START_BIT = 1;
localparam [2:0] DATA = 2;
localparam [2:0] SAVE_DATA = 3;
localparam [2:0] PARITY = 4;
localparam [2:0] STOP_BIT = 5;
reg [2:0] CS, NS;
reg [7:0] reg_data;
reg [7:0] reg_data_next;
reg [2:0] reg_rx_sync;
reg [2:0] reg_bit_count;
reg [2:0] reg_bit_count_next;
reg [2:0] s_target_bits;
reg parity_bit;
reg parity_bit_next;
reg sampleData;
reg [15:0] baud_cnt;
reg baudgen_en;
reg bit_done;
reg start_bit;
reg set_error;
wire s_rx_fall;
assign busy_o = (CS != IDLE);
always @(*) begin
case (cfg_bits_i)
2'b00: s_target_bits = 3'h4;
2'b01: s_target_bits = 3'h5;
2'b10: s_target_bits = 3'h6;
2'b11: s_target_bits = 3'h7;
endcase
end
always @(*) begin
NS = CS;
sampleData = 1'b0;
reg_bit_count_next = reg_bit_count;
reg_data_next = reg_data;
rx_valid_o = 1'b0;
baudgen_en = 1'b0;
start_bit = 1'b0;
parity_bit_next = parity_bit;
set_error = 1'b0;
case (CS)
IDLE: begin
if (s_rx_fall) begin
NS = START_BIT;
baudgen_en = 1'b1;
start_bit = 1'b1;
end
end
START_BIT: begin
parity_bit_next = 1'b0;
baudgen_en = 1'b1;
start_bit = 1'b1;
if (bit_done) NS = DATA;
end
DATA: begin
baudgen_en = 1'b1;
parity_bit_next = parity_bit ^ reg_rx_sync[2];
case (cfg_bits_i)
2'b00: reg_data_next = {3'b0, reg_rx_sync[2], reg_data[4:1]};
2'b01: reg_data_next = {2'b0, reg_rx_sync[2], reg_data[5:1]};
2'b10: reg_data_next = {1'b0, reg_rx_sync[2], reg_data[6:1]};
2'b11: reg_data_next = {reg_rx_sync[2], reg_data[7:1]};
endcase
if (bit_done) begin
sampleData = 1'b1;
if (reg_bit_count == s_target_bits) begin
reg_bit_count_next = 'h0;
NS = SAVE_DATA;
end else begin
reg_bit_count_next = reg_bit_count + 1;
end
end
end
SAVE_DATA: begin
baudgen_en = 1'b1;
rx_valid_o = 1'b1;
if (rx_ready_i) begin
if (cfg_parity_en_i) NS = PARITY;
else NS = STOP_BIT;
end
end
PARITY: begin
baudgen_en = 1'b1;
if (bit_done) begin
case (cfg_parity_sel_i)
2'b00:
if (reg_rx_sync[2] != ~parity_bit) set_error = 1'b1;
2'b01:
if (reg_rx_sync[2] != parity_bit) set_error = 1'b1;
2'b10:
if (reg_rx_sync[2] != 1'b0) set_error = 1'b1;
2'b11:
if (reg_rx_sync[2] != 1'b1) set_error = 1'b1;
endcase
NS = STOP_BIT;
end
end
STOP_BIT: begin
baudgen_en = 1'b1;
if (bit_done) NS = IDLE;
end
default: NS = IDLE;
endcase
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
CS <= IDLE;
reg_data <= 8'hff;
reg_bit_count <= 'h0;
parity_bit <= 1'b0;
end else begin
if (bit_done)
parity_bit <= parity_bit_next;
if (sampleData)
reg_data <= reg_data_next;
reg_bit_count <= reg_bit_count_next;
if (cfg_en_i)
CS <= NS;
else
CS <= IDLE;
end
end
assign s_rx_fall = ~reg_rx_sync[1] & reg_rx_sync[2];
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0)
reg_rx_sync <= 3'b111;
else if (cfg_en_i)
reg_rx_sync <= {reg_rx_sync[1:0], rx_i};
else
reg_rx_sync <= 3'b111;
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end else if (baudgen_en) begin
if (!start_bit && (baud_cnt == cfg_div_i)) begin
baud_cnt <= 'h0;
bit_done <= 1'b1;
end else if (start_bit && (baud_cnt == {1'b0, cfg_div_i[15:1]})) begin
baud_cnt <= 'h0;
bit_done <= 1'b1;
end else begin
baud_cnt <= baud_cnt + 1;
bit_done <= 1'b0;
end
end else begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end
end
always @(posedge clk_i or negedge rstn_i)
if (rstn_i == 1'b0)
err_o <= 1'b0;
else if (err_clr_i)
err_o <= 1'b0;
else if (set_error)
err_o <= 1'b1;
assign rx_data_o = reg_data;
endmodule |
module uart_interrupt
#(
parameter TX_FIFO_DEPTH = 32,
parameter RX_FIFO_DEPTH = 32
)
(
input wire clk_i,
input wire rstn_i,
// registers
input wire [2:0] IER_i, // interrupt enable register
// control logic
input wire error_i,
input wire [$clog2(RX_FIFO_DEPTH):0] rx_elements_i,
input wire [$clog2(TX_FIFO_DEPTH):0] tx_elements_i,
input wire [1:0] trigger_level_i,
input wire [3:0] clr_int_i, // one hot
output wire interrupt_o,
output wire [3:0] IIR_o
);
reg [3:0] iir_n;
reg [3:0] iir_q;
reg trigger_level_reached;
always @(*) begin
trigger_level_reached = 1'b0;
case (trigger_level_i)
2'b00:
if ($unsigned(rx_elements_i) == 1)
trigger_level_reached = 1'b1;
2'b01:
if ($unsigned(rx_elements_i) == 4)
trigger_level_reached = 1'b1;
2'b10:
if ($unsigned(rx_elements_i) == 8)
trigger_level_reached = 1'b1;
2'b11:
if ($unsigned(rx_elements_i) == 14)
trigger_level_reached = 1'b1;
endcase
end
always @(*) begin
if (clr_int_i == 4'b0) begin
// Receive data parity error
if (IER_i[2] & error_i)
iir_n = 4'b1100;
// Trigger level reached in FIFO mode
else if (IER_i[0] & trigger_level_reached)
iir_n = 4'b1000;
// Transmitter holding register empty
else if (IER_i[1] & (tx_elements_i == 0))
iir_n = 4'b0100;
else
iir_n = iir_q;
end else begin
iir_n = iir_q & ~clr_int_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i)
iir_q <= 4'b0;
else
iir_q <= iir_n;
end
assign IIR_o = iir_q;
assign interrupt_o = iir_q[2] | iir_q[3];
endmodule |
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