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module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule |
module tx_engine_formatter_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [7:0] TAG, // External tag
input [3:0] CHNL, // Internal tag (just channel portion)
input [61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
reg rState=`S_TXENGFMTR128_IDLE, _rState=`S_TXENGFMTR128_IDLE;
reg rAddr64=0, _rAddr64=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0] rPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen=0, _rDataWen=0;
reg [9:0] rLen=0, _rLen=0;
reg rDone=0, _rDone=0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [63:0] wHdrData = ({WR_DATA[31:0], ADDR[29:0], 2'b00, ADDR[61:30]})>>(32*(!ADDR_64));
wire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData})>>(32*(!rAddr64));
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR128_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr64 <= #1 _rAddr64;
rPrevData <= #1 _rPrevData;
rDone <= #1 _rDone;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rPrevData = WR_DATA;
_rAddr64 = rAddr64;
case (rState)
`S_TXENGFMTR128_IDLE : begin // FIFO data should be available now (if it's a write)
_rLen = LEN - !ADDR_64; // Subtract 1 for 32 bit (HDR has one)
_rAddr64 = ADDR_64;
_rData = {wHdrData, // DW3, DW2
CONFIG_COMPLETER_ID[15:3], 3'b0, TAG,
(LEN_ONE ? 4'b0 : 4'b1111), 4'b1111, // DW1
1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN}; // DW0
_rDataWen = VALID;
_rDone = (LEN <= {1'b1, 1'b0, !ADDR_64});
_rState = (VALID & WNR & (ADDR_64 | !LEN_ONE) ? `S_TXENGFMTR128_WR : `S_TXENGFMTR128_IDLE);
end
`S_TXENGFMTR128_WR : begin
_rLen = rLen - 3'd4;
_rDone = (rLen <= 4'd8);
_rData = wWrData;
_rState = (rDone ? `S_TXENGFMTR128_IDLE : `S_TXENGFMTR128_WR);
end
endcase
end
endmodule |
module ff(
CLK,
D,
Q
);
input CLK;
input D;
output Q;
reg Q;
always @ (posedge CLK) begin
Q <= #1 D;
end
endmodule |
module syncff(
CLK,
IN_ASYNC,
OUT_SYNC
);
input CLK;
input IN_ASYNC;
output OUT_SYNC;
wire wSyncFFQ;
ff syncFF (
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule |
module riffa_endpoint_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_ALTERA = 1'b1, // 1 if Altera, 0 if Xilinx
// Local parameters
parameter C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
parameter C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL),
parameter C_PCI_DATA_WORD_WIDTH = clog2((C_PCI_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST_IN,
output RST_OUT,
input [C_PCI_DATA_WIDTH-1:0] RX_DATA,
input RX_DATA_VALID,
output RX_DATA_READY,
input RX_TLP_START_FLAG,
input RX_TLP_END_FLAG,
input [3:0] RX_TLP_START_OFFSET,
input [3:0] RX_TLP_END_OFFSET,
input RX_TLP_ERROR_POISON,
output [C_PCI_DATA_WIDTH-1:0] TX_DATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,
output TX_TLP_END_FLAG,
output TX_TLP_START_FLAG,
output TX_DATA_VALID,
output S_AXIS_SRC_DSC,
input TX_DATA_READY,
input [15:0] CONFIG_COMPLETER_ID,
input CONFIG_BUS_MASTER_ENABLE,
input [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=1
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
`include "common_functions.v"
wire [31:0] wIntr0;
wire [31:0] wIntr1;
wire [5:0] wIntTag;
wire wIntTagValid;
wire [C_TAG_WIDTH-1:0] wExtTag;
wire wExtTagValid;
wire wRxEngRdComplete;
wire wTxEngRdReqSent;
wire wTxFcRxSpaceAvail;
wire wRxEngReqWr;
wire wRxEngReqWrDone;
wire wRxEngReqRd;
wire wRxEngReqRdDone;
wire [9:0] wRxEngReqLen;
wire [29:0] wRxEngReqAddr;
wire [31:0] wRxEngReqData;
wire [3:0] wRxEngReqBE;
wire [2:0] wRxEngReqTC;
wire wRxEngReqTD;
wire wRxEngReqEP;
wire [1:0] wRxEngReqAttr;
wire [15:0] wRxEngReqId;
wire [7:0] wRxEngReqTag;
wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn;
wire [C_NUM_CHNL-1:0] wRxEngMainDone;
wire [C_NUM_CHNL-1:0] wRxEngMainErr;
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
wire wRxEngReqAddr00 = (wRxEngReqAddr[3:0] == 4'b0000);
wire wRxEngReqAddr01 = (wRxEngReqAddr[3:0] == 4'b0001);
wire wRxEngReqAddr02 = (wRxEngReqAddr[3:0] == 4'b0010);
wire wRxEngReqAddr03 = (wRxEngReqAddr[3:0] == 4'b0011);
wire wRxEngReqAddr04 = (wRxEngReqAddr[3:0] == 4'b0100);
wire wRxEngReqAddr05 = (wRxEngReqAddr[3:0] == 4'b0101);
wire wRxEngReqAddr06 = (wRxEngReqAddr[3:0] == 4'b0110);
wire wRxEngReqAddr07 = (wRxEngReqAddr[3:0] == 4'b0111);
wire wRxEngReqAddr08 = (wRxEngReqAddr[3:0] == 4'b1000);
wire wRxEngReqAddr09 = (wRxEngReqAddr[3:0] == 4'b1001);
wire wRxEngReqAddr10 = (wRxEngReqAddr[3:0] == 4'b1010);
wire wRxEngReqAddr11 = (wRxEngReqAddr[3:0] == 4'b1011);
wire wRxEngReqAddr12 = (wRxEngReqAddr[3:0] == 4'b1100);
wire wRxEngReqAddr13 = (wRxEngReqAddr[3:0] == 4'b1101);
wire wRxEngReqAddr14 = (wRxEngReqAddr[3:0] == 4'b1110);
reg [1:0] rTxEngReq=0, _rTxEngReq=0;
reg [31:0] rTxEngReqData=0, _rTxEngReqData=0;
reg [31:0] rTxnTxLen=0, _rTxnTxLen=0;
reg [31:0] rTxnTxOffLast=0, _rTxnTxOffLast=0;
reg [31:0] rTxnRxDoneLen=0, _rTxnRxDoneLen=0;
reg [31:0] rTxnTxDoneLen=0, _rTxnTxDoneLen=0;
wire [31:0] wTxEngReqDataSent;
wire wTxEngReqDone;
wire [C_NUM_CHNL-1:0] wTxEngWrReq;
wire [(C_NUM_CHNL*64)-1:0] wTxEngWrAddr;
wire [(C_NUM_CHNL*10)-1:0] wTxEngWrLen;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
wire [C_NUM_CHNL-1:0] wTxEngWrAck;
wire [C_NUM_CHNL-1:0] wTxEngWrSent;
wire [C_NUM_CHNL-1:0] wTxEngRdReq;
wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
wire [(C_NUM_CHNL*64)-1:0] wTxEngRdAddr;
wire [(C_NUM_CHNL*10)-1:0] wTxEngRdLen;
wire [C_NUM_CHNL-1:0] wTxEngRdAck;
wire [C_NUM_CHNL-1:0] wSgRxBufRecvd;
wire [C_NUM_CHNL-1:0] wSgRxLenValid;
wire [C_NUM_CHNL-1:0] wSgRxAddrHiValid;
wire [C_NUM_CHNL-1:0] wSgRxAddrLoValid;
wire [C_NUM_CHNL-1:0] wSgTxBufRecvd;
wire [C_NUM_CHNL-1:0] wSgTxLenValid;
wire [C_NUM_CHNL-1:0] wSgTxAddrHiValid;
wire [C_NUM_CHNL-1:0] wSgTxAddrLoValid;
wire [C_NUM_CHNL-1:0] wTxnRxLenValid;
wire [C_NUM_CHNL-1:0] wTxnRxOffLastValid;
wire [(C_NUM_CHNL*32)-1:0] wTxnRxDoneLen;
wire [C_NUM_CHNL-1:0] wTxnRxDone;
wire [C_NUM_CHNL-1:0] wTxnRxDoneAck; // ACK'd on length read
wire [C_NUM_CHNL-1:0] wTxnTx;
wire [C_NUM_CHNL-1:0] wTxnTxAck; // ACK'd on length read
wire [(C_NUM_CHNL*32)-1:0] wTxnTxLen;
wire [(C_NUM_CHNL*32)-1:0] wTxnTxOffLast;
wire [(C_NUM_CHNL*32)-1:0] wTxnTxDoneLen;
wire [C_NUM_CHNL-1:0] wTxnTxDone;
wire [C_NUM_CHNL-1:0] wTxnTxDoneAck; // ACK'd on length read
reg [4:0] rWideRst=0;
reg rRst=0;
// The Mem/IO read/write address space should be at least 8 bits wide. This
// means we'll need at least 10 bits of BAR 0, at least 1024 bytes. The bottom
// two bits must always be zero (i.e. all addresses are 4 byte word aligned).
// The Mem/IO read/write address space is partitioned as illustrated below.
// {CHANNEL_NUM} {DATA_OFFSETS} {ZERO}
// ------4-------------4-----------2--
// The lower 2 bits are always zero. The middle 4 bits are used according to
// the listing below. The top 4 bits differentiate between channels for values
// defined in the table below.
// 0000 = Length of SG buffer for RX transaction (Write only)
// 0001 = PC low address of SG buffer for RX transaction (Write only)
// 0010 = PC high address of SG buffer for RX transaction (Write only)
// 0011 = Transfer length for RX transaction (Write only)
// 0100 = Offset/Last for RX transaction (Write only)
// 0101 = Length of SG buffer for TX transaction (Write only)
// 0110 = PC low address of SG buffer for TX transaction (Write only)
// 0111 = PC high address of SG buffer for TX transaction (Write only)
// 1000 = Transfer length for TX transaction (Read only) (ACK'd on read)
// 1001 = Offset/Last for TX transaction (Read only)
// 1010 = Link rate, link width, bus master enabled, number of channels (Read only)
// 1011 = Interrupt vector 1 (Read only) (Reset on read)
// 1100 = Interrupt vector 2 (Read only) (Reset on read)
// 1101 = Transferred length for RX transaction (Read only) (ACK'd on read)
// 1110 = Transferred length for TX transaction (Read only) (ACK'd on read)
// Generate a wide reset on PC reset.
assign RST_OUT = rRst;
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST_IN | (wRxEngReqAddr10 & wRxEngReqRdDone))
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Manage tx_engine read completions.
always @ (posedge CLK) begin
rTxEngReq <= #1 (rRst ? {2{1'd0}} : _rTxEngReq);
rTxEngReqData <= #1 _rTxEngReqData;
rTxnTxLen <= #1 _rTxnTxLen;
rTxnTxOffLast <= #1 _rTxnTxOffLast;
rTxnRxDoneLen <= #1 _rTxnRxDoneLen;
rTxnTxDoneLen <= #1 _rTxnTxDoneLen;
end
always @ (*) begin
if (wTxEngReqDone)
_rTxEngReq = 0;
else
_rTxEngReq = ((rTxEngReq<<1) | wRxEngReqRd);
_rTxnTxLen = wTxnTxLen[(32*wRxEngReqAddr[7:4]) +:32];
_rTxnTxOffLast = wTxnTxOffLast[(32*wRxEngReqAddr[7:4]) +:32];
_rTxnRxDoneLen = wTxnRxDoneLen[(32*wRxEngReqAddr[7:4]) +:32];
_rTxnTxDoneLen = wTxnTxDoneLen[(32*wRxEngReqAddr[7:4]) +:32];
case (wRxEngReqAddr[2:0])
3'b000: _rTxEngReqData = rTxnTxLen;
3'b001: _rTxEngReqData = rTxnTxOffLast;
3'b010: _rTxEngReqData = {9'd0, C_PCI_DATA_WIDTH[8:5], CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE, CONFIG_LINK_RATE, CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE, C_NUM_CHNL};
3'b011: _rTxEngReqData = wIntr0;
3'b100: _rTxEngReqData = wIntr1;
3'b101: _rTxEngReqData = rTxnRxDoneLen;
3'b110: _rTxEngReqData = rTxnTxDoneLen;
3'b111: _rTxEngReqData = 'bX;
endcase
end
// Demultiplex the input PIO write notifications to one of the channels.
demux_1_to_n #(C_NUM_CHNL, 1) muxSgRxLenValid ( .IN(wRxEngReqAddr00), .OUT(wSgRxLenValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxSgRxAddrHiValid ( .IN(wRxEngReqAddr02), .OUT(wSgRxAddrHiValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxSgRxAddrLoValid ( .IN(wRxEngReqAddr01), .OUT(wSgRxAddrLoValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxSgTxLenValid ( .IN(wRxEngReqAddr05), .OUT(wSgTxLenValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxSgTxAddrHiValid ( .IN(wRxEngReqAddr07), .OUT(wSgTxAddrHiValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxSgTxAddrLoValid ( .IN(wRxEngReqAddr06), .OUT(wSgTxAddrLoValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxTxnRxLenValid ( .IN(wRxEngReqAddr03), .OUT(wTxnRxLenValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxTxnRxOffLastValid (.IN(wRxEngReqAddr04), .OUT(wTxnRxOffLastValid), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxTxnRxDoneAck ( .IN(wRxEngReqAddr13), .OUT(wTxnRxDoneAck), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
demux_1_to_n #(C_NUM_CHNL, 1) muxTxnTxAck ( .IN(wRxEngReqAddr08), .OUT(wTxnTxAck), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH])); // ACK'd on length read
demux_1_to_n #(C_NUM_CHNL, 1) muxTxnTxDoneAck ( .IN(wRxEngReqAddr14), .OUT(wTxnTxDoneAck), .SEL(wRxEngReqAddr[4 +:C_NUM_CHNL_WIDTH]));
// Generate and link up the channels.
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
channel_128 #(.C_DATA_WIDTH(C_PCI_DATA_WIDTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) channel (
.RST(rRst),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.PIO_DATA(wRxEngReqData),
.ENG_DATA(wRxEngData),
.SG_RX_BUF_RECVD(wSgRxBufRecvd[i]),
.SG_RX_BUF_LEN_VALID(wRxEngReqWr & wSgRxLenValid[i]),
.SG_RX_BUF_ADDR_HI_VALID(wRxEngReqWr & wSgRxAddrHiValid[i]),
.SG_RX_BUF_ADDR_LO_VALID(wRxEngReqWr & wSgRxAddrLoValid[i]),
.SG_TX_BUF_RECVD(wSgTxBufRecvd[i]),
.SG_TX_BUF_LEN_VALID(wRxEngReqWr & wSgTxLenValid[i]),
.SG_TX_BUF_ADDR_HI_VALID(wRxEngReqWr & wSgTxAddrHiValid[i]),
.SG_TX_BUF_ADDR_LO_VALID(wRxEngReqWr & wSgTxAddrLoValid[i]),
.TXN_RX_LEN_VALID(wRxEngReqWr & wTxnRxLenValid[i]),
.TXN_RX_OFF_LAST_VALID(wRxEngReqWr & wTxnRxOffLastValid[i]),
.TXN_RX_DONE_LEN(wTxnRxDoneLen[(32*i) +:32]),
.TXN_RX_DONE(wTxnRxDone[i]),
.TXN_RX_DONE_ACK(wRxEngReqRdDone & wTxnRxDoneAck[i]), // ACK'd on length read
.TXN_TX(wTxnTx[i]),
.TXN_TX_ACK(wRxEngReqRdDone & wTxnTxAck[i]), // ACK'd on length read
.TXN_TX_LEN(wTxnTxLen[(32*i) +:32]),
.TXN_TX_OFF_LAST(wTxnTxOffLast[(32*i) +:32]),
.TXN_TX_DONE_LEN(wTxnTxDoneLen[(32*i) +:32]),
.TXN_TX_DONE(wTxnTxDone[i]),
.TXN_TX_DONE_ACK(wRxEngReqRdDone & wTxnTxDoneAck[i]), // ACK'd on length read
.RX_REQ(wTxEngRdReq[i]),
.RX_REQ_ACK(wTxEngRdAck[i]),
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),
.RX_REQ_ADDR(wTxEngRdAddr[(64*i) +:64]),
.RX_REQ_LEN(wTxEngRdLen[(10*i) +:10]),
.TX_REQ(wTxEngWrReq[i]),
.TX_REQ_ACK(wTxEngWrAck[i]),
.TX_ADDR(wTxEngWrAddr[(64*i) +:64]),
.TX_LEN(wTxEngWrLen[(10*i) +:10]),
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.TX_DATA_REN(wTxEngWrDataRen[i]),
.TX_SENT(wTxEngWrSent[i]),
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.MAIN_DONE(wRxEngMainDone[i]),
.MAIN_ERR(wRxEngMainErr[i]),
.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_RX_DONE(wRxEngSgRxDone[i]),
.SG_RX_ERR(wRxEngSgRxErr[i]),
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_TX_DONE(wRxEngSgTxDone[i]),
.SG_TX_ERR(wRxEngSgTxErr[i]),
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
.CHNL_RX(CHNL_RX[i]),
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
.CHNL_TX(CHNL_TX[i]),
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
);
end
endgenerate
// Connect up the rx_engine
assign wRxEngReqWrDone = wRxEngReqWr;
assign wRxEngReqRdDone = wTxEngReqDone;
rx_engine_128 #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_ALTERA(C_ALTERA)
) rxEng (
.CLK(CLK),
.RST(rRst),
.RX_DATA(RX_DATA),
.RX_DATA_VALID(RX_DATA_VALID),
.RX_DATA_READY(RX_DATA_READY),
.RX_TLP_END_FLAG(RX_TLP_END_FLAG),
.RX_TLP_START_FLAG(RX_TLP_START_FLAG),
.RX_TLP_END_OFFSET(RX_TLP_END_OFFSET),
.RX_TLP_START_OFFSET(RX_TLP_START_OFFSET),
.RX_TLP_ERROR_POISON(RX_TLP_ERROR_POISON),
.REQ_WR(wRxEngReqWr),
.REQ_WR_DONE(wRxEngReqWrDone),
.REQ_RD(wRxEngReqRd),
.REQ_RD_DONE(wRxEngReqRdDone),
.REQ_LEN(wRxEngReqLen),
.REQ_ADDR(wRxEngReqAddr),
.REQ_DATA(wRxEngReqData),
.REQ_BE(wRxEngReqBE),
.REQ_TC(wRxEngReqTC),
.REQ_TD(wRxEngReqTD),
.REQ_EP(wRxEngReqEP),
.REQ_ATTR(wRxEngReqAttr),
.REQ_ID(wRxEngReqId),
.REQ_TAG(wRxEngReqTag),
.INT_TAG(wIntTag),
.INT_TAG_VALID(wIntTagValid),
.EXT_TAG(wExtTag),
.EXT_TAG_VALID(wExtTagValid),
.ENG_DATA(wRxEngData),
.ENG_RD_COMPLETE(wRxEngRdComplete),
.MAIN_DATA_EN(wRxEngMainDataEn),
.MAIN_DONE(wRxEngMainDone),
.MAIN_ERR(wRxEngMainErr),
.SG_RX_DATA_EN(wRxEngSgRxDataEn),
.SG_RX_DONE(wRxEngSgRxDone),
.SG_RX_ERR(wRxEngSgRxErr),
.SG_TX_DATA_EN(wRxEngSgTxDataEn),
.SG_TX_DONE(wRxEngSgTxDone),
.SG_TX_ERR(wRxEngSgTxErr)
);
// Connect up the tx_engine
tx_engine_128 #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_ALTERA(C_ALTERA),
.C_NUM_CHNL(C_NUM_CHNL),
.C_TAG_WIDTH(C_TAG_WIDTH)
) txEng (
.CLK(CLK),
.RST(rRst),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TX_DATA(TX_DATA),
.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),
.TX_TLP_END_FLAG(TX_TLP_END_FLAG),
.TX_TLP_START_FLAG(TX_TLP_START_FLAG),
.TX_DATA_VALID(TX_DATA_VALID),
.S_AXIS_SRC_DSC(S_AXIS_SRC_DSC),
.TX_DATA_READY(TX_DATA_READY),
.WR_REQ(wTxEngWrReq),
.WR_ADDR(wTxEngWrAddr),
.WR_LEN(wTxEngWrLen),
.WR_DATA(wTxEngWrData),
.WR_DATA_REN(wTxEngWrDataRen),
.WR_ACK(wTxEngWrAck),
.WR_SENT(wTxEngWrSent),
.RD_REQ(wTxEngRdReq),
.RD_SG_CHNL(wTxEngRdSgChnl),
.RD_ADDR(wTxEngRdAddr),
.RD_LEN(wTxEngRdLen),
.RD_ACK(wTxEngRdAck),
.INT_TAG(wIntTag),
.INT_TAG_VALID(wIntTagValid),
.EXT_TAG(wExtTag),
.EXT_TAG_VALID(wExtTagValid),
.TX_ENG_RD_REQ_SENT(wTxEngRdReqSent),
.RXBUF_SPACE_AVAIL(wTxFcRxSpaceAvail),
.COMPL_REQ(rTxEngReq[1]),
.COMPL_DONE(wTxEngReqDone),
.REQ_TC(wRxEngReqTC),
.REQ_TD(wRxEngReqTD),
.REQ_EP(wRxEngReqEP),
.REQ_ATTR(wRxEngReqAttr),
.REQ_LEN(wRxEngReqLen),
.REQ_ID(wRxEngReqId),
.REQ_TAG(wRxEngReqTag),
.REQ_BE(wRxEngReqBE),
.REQ_ADDR(wRxEngReqAddr),
.REQ_DATA(rTxEngReqData),
.REQ_DATA_SENT(wTxEngReqDataSent)
);
// Connect the interrupt vector and controller.
interrupt #(.C_NUM_CHNL(C_NUM_CHNL)) intr (
.CLK(CLK),
.RST(rRst),
.RX_SG_BUF_RECVD(wSgRxBufRecvd),
.RX_TXN_DONE(wTxnRxDone),
.TX_TXN(wTxnTx),
.TX_SG_BUF_RECVD(wSgTxBufRecvd),
.TX_TXN_DONE(wTxnTxDone),
.VECT_0_RST(wRxEngReqRdDone && wRxEngReqAddr11),
.VECT_1_RST(wRxEngReqRdDone && wRxEngReqAddr12),
.VECT_RST(wTxEngReqDataSent),
.VECT_0(wIntr0),
.VECT_1(wIntr1),
.INTR_LEGACY_CLR(1'd0),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST)
);
// Track receive buffer flow control credits (header & Data)
recv_credit_flow_ctrl rc_fc (
// Outputs
.RXBUF_SPACE_AVAIL(wTxFcRxSpaceAvail),
// Inputs
.CLK(CLK),
.RST(RST_IN),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_CPL_DATA(CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR(CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.RX_ENG_RD_DONE(wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT(wTxEngRdReqSent)
);
endmodule |
module rx_port_channel_gate #(
parameter C_DATA_WIDTH = 9'd64
)
(
input RST,
input CLK,
input RX, // Channel read signal (CLK)
output RX_RECVD, // Channel read received signal (CLK)
output RX_ACK_RECVD, // Channel read acknowledgment received signal (CLK)
input RX_LAST, // Channel last read (CLK)
input [31:0] RX_LEN, // Channel read length (CLK)
input [30:0] RX_OFF, // Channel read offset (CLK)
output [31:0] RX_CONSUMED, // Channel words consumed (CLK)
input [C_DATA_WIDTH-1:0] RD_DATA, // FIFO read data (CHNL_CLK)
input RD_EMPTY, // FIFO is empty (CHNL_CLK)
output RD_EN, // FIFO read enable (CHNL_CLK)
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal (CHNL_CLK)
input CHNL_RX_ACK, // Channle read received signal (CHNL_CLK)
output CHNL_RX_LAST, // Channel last read (CHNL_CLK)
output [31:0] CHNL_RX_LEN, // Channel read length (CHNL_CLK)
output [30:0] CHNL_RX_OFF, // Channel read offset (CHNL_CLK)
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data (CHNL_CLK)
output CHNL_RX_DATA_VALID, // Channel read data valid (CHNL_CLK)
input CHNL_RX_DATA_REN // Channel read data has been recieved (CHNL_CLK)
);
reg rAckd=0, _rAckd=0;
reg rChnlRxAck=0, _rChnlRxAck=0;
reg [31:0] rConsumed=0, _rConsumed=0;
reg [31:0] rConsumedStable=0, _rConsumedStable=0;
reg [31:0] rConsumedSample=0, _rConsumedSample=0;
reg rCountRead=0, _rCountRead=0;
wire wCountRead;
wire wCountStable;
wire wDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);
assign RX_CONSUMED = rConsumedSample;
assign RD_EN = CHNL_RX_DATA_REN;
assign CHNL_RX_LAST = RX_LAST;
assign CHNL_RX_LEN = RX_LEN;
assign CHNL_RX_OFF = RX_OFF;
assign CHNL_RX_DATA = RD_DATA;
assign CHNL_RX_DATA_VALID = !RD_EMPTY;
// Buffer the input signals that come from outside the rx_port.
always @ (posedge CHNL_CLK) begin
rChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);
end
always @ (*) begin
_rChnlRxAck = CHNL_RX_ACK;
end
// Signal receive into the channel domain.
cross_domain_signal rxSig (
.CLK_A(CLK),
.CLK_A_SEND(RX),
.CLK_A_RECV(RX_RECVD),
.CLK_B(CHNL_CLK),
.CLK_B_RECV(CHNL_RX),
.CLK_B_SEND(CHNL_RX)
);
// Signal acknowledgment of receive into the CLK domain.
syncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));
// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.
always @ (posedge CHNL_CLK) begin
rAckd <= #1 (RST ? 1'd0 : _rAckd);
end
always @ (*) begin
_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));
end
// Count the words consumed by the channel and pass it into the CLK domain.
always @ (posedge CHNL_CLK) begin
rConsumed <= #1 _rConsumed;
rConsumedStable <= #1 _rConsumedStable;
rCountRead <= #1 (RST ? 1'd0 : _rCountRead);
end
always @ (*) begin
_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));
_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);
_rCountRead = !wCountRead;
end
always @ (posedge CLK) begin
rConsumedSample <= #1 _rConsumedSample;
end
always @ (*) begin
_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);
end
// Determine when it's safe to update the count in the CLK domain.
cross_domain_signal countSync (
.CLK_A(CHNL_CLK),
.CLK_A_SEND(rCountRead),
.CLK_A_RECV(wCountRead),
.CLK_B(CLK),
.CLK_B_RECV(wCountStable),
.CLK_B_SEND(wCountStable)
);
endmodule |
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule |
module pcie_reset_delay_v6 # (
parameter PL_FAST_TRAIN = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter TCQ = 1
)
(
input wire ref_clk,
input wire sys_reset_n,
output delayed_sys_reset_n
);
localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;
reg [7:0] reg_count_7_0;
reg [7:0] reg_count_15_8;
reg [7:0] reg_count_23_16;
wire [23:0] concat_count;
assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};
always @(posedge ref_clk or negedge sys_reset_n) begin
if (!sys_reset_n) begin
reg_count_7_0 <= #TCQ 8'h0;
reg_count_15_8 <= #TCQ 8'h0;
reg_count_23_16 <= #TCQ 8'h0;
end else begin
if (delayed_sys_reset_n != 1'b1) begin
reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;
reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ;
reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;
end
end
end
assign delayed_sys_reset_n = concat_count[TBIT];
endmodule |
module tx_engine_selector #(
parameter C_NUM_CHNL = 4'd12
)
(
input CLK,
input RST,
input [C_NUM_CHNL-1:0] REQ_ALL, // Write requests
output REQ, // Write request
output [3:0] CHNL // Write channel
);
reg [3:0] rReqChnl=0, _rReqChnl=0;
reg [3:0] rReqChnlNext=0, _rReqChnlNext=0;
reg rReqChnlsSame=0, _rReqChnlsSame=0;
reg [3:0] rChnlNext=0, _rChnlNext=0;
reg [3:0] rChnlNextNext=0, _rChnlNextNext=0;
reg rChnlNextDfrnt=0, _rChnlNextDfrnt=0;
reg rChnlNextNextOn=0, _rChnlNextNextOn=0;
wire wChnlNextNextOn = (REQ_ALL>>(rChnlNextNext));
reg rReq=0, _rReq=0;
wire wReq = (REQ_ALL>>(rReqChnl));
reg rReqChnlNextUpdated=0, _rReqChnlNextUpdated=0;
assign REQ = rReq;
assign CHNL = rReqChnl;
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
always @ (posedge CLK) begin
rReq <= #1 (RST ? 1'd0 : _rReq);
rReqChnl <= #1 (RST ? 4'd0 : _rReqChnl);
rReqChnlNext <= #1 (RST ? 4'd0 : _rReqChnlNext);
rChnlNext <= #1 (RST ? 4'd0 : _rChnlNext);
rChnlNextNext <= #1 (RST ? 4'd0 : _rChnlNextNext);
rChnlNextDfrnt <= #1 (RST ? 1'd0 : _rChnlNextDfrnt);
rChnlNextNextOn <= #1 (RST ? 1'd0 : _rChnlNextNextOn);
rReqChnlsSame <= #1 (RST ? 1'd0 : _rReqChnlsSame);
rReqChnlNextUpdated <= #1 (RST ? 1'd1 : _rReqChnlNextUpdated);
end
always @ (*) begin
// Go through each channel (RR), looking for requests
_rChnlNextNextOn = wChnlNextNextOn;
_rChnlNext = rChnlNextNext;
_rChnlNextNext = (rChnlNextNext == C_NUM_CHNL - 1 ? 4'd0 : rChnlNextNext + 1'd1);
_rChnlNextDfrnt = (rChnlNextNext != rReqChnl);
_rReqChnlsSame = (rReqChnlNext == rReqChnl);
// Save ready channel if it is not the same channel we're currently on
if (rChnlNextNextOn & rChnlNextDfrnt & rReqChnlsSame & !rReqChnlNextUpdated) begin
_rReqChnlNextUpdated = 1;
_rReqChnlNext = rChnlNext;
end
else begin
_rReqChnlNextUpdated = 0;
_rReqChnlNext = rReqChnlNext;
end
// Assign the new channel
_rReq = wReq;
_rReqChnl = (!rReq ? rReqChnlNext : rReqChnl);
end
endmodule |
module tx_engine_upper_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_FIFO_DEPTH = 512,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_ALTERA = 1'b1,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_MAX_ENTRIES = (11'd128*11'd8/C_PCI_DATA_WIDTH),
parameter C_DATA_DELAY = 3'd6 // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*64)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*10)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*64)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*10)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
output [C_PCI_DATA_WIDTH-1:0] FIFO_DATA, // Formatted read/write request data
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Formatted read/write FIFO count
output FIFO_WEN // Formatted read/write FIFO read enable
);
`include "common_functions.v"
reg rMainState=`S_TXENGUPR128_MAIN_IDLE, _rMainState=`S_TXENGUPR128_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [61:0] rCountAddr=62'd0, _rCountAddr=62'd0;
reg rCountAddr64=0, _rCountAddr64=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountValid=0, _rCountValid=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr = (RD_ADDR>>(wRdReqChnl*64));
wire [9:0] wRdLen = (RD_LEN>>(wRdReqChnl*10));
wire [1:0] wRdSgChnl = (RD_SG_CHNL>>(wRdReqChnl*2));
wire [63:0] wWrAddr = (WR_ADDR>>(wWrReqChnl*64));
wire [9:0] wWrLen = (WR_LEN>>(wWrReqChnl*10));
wire [C_PCI_DATA_WIDTH-1:0] wWrData = (WR_DATA>>wCountChnlShiftDW);
wire [C_PCI_DATA_WIDTH-1:0] wWrDataSwap;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
generate
if(C_ALTERA == 1'b1) begin : altera_data
assign wWrDataSwap = rWrData;
end
else begin : xilinx_data
assign wWrDataSwap = {rWrData[103:96], rWrData[111:104], rWrData[119:112], rWrData[127:120],
rWrData[71:64], rWrData[79:72], rWrData[87:80], rWrData[95:88],
rWrData[39:32], rWrData[47:40], rWrData[55:48], rWrData[63:56],
rWrData[07:00], rWrData[15:08], rWrData[23:16], rWrData[31:24]};
end
endgenerate
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR128_CAP_RD_WR, _rCapState=`S_TXENGUPR128_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_FIFO_DEPTH_WIDTH-1:0] rFifoCount=0, _rFifoCount=0;
reg [9:0] rMaxEntries=0, _rMaxEntries=0;
reg rSpaceAvail=0, _rSpaceAvail=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST ? `S_TXENGUPR128_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = rCapAddr64;
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR128_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_WR_RD);
end
`S_TXENGUPR128_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_RD_WR);
end
`S_TXENGUPR128_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapAddr64 = (rWrAddr[61:30] != 0);
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapAddr64 = (rRdAddr[61:30] != 0);
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR128_CAP_REL;
end
`S_TXENGUPR128_CAP_REL : begin
// Push into the formatting pipeline when ready
if (rSpaceAvail & !rMainState) // S_TXENGUPR128_MAIN_IDLE
_rCapState = (`S_TXENGUPR128_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR128_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR128_CAP_RD_WR;
end
endcase
end
// Calculate the available space in the FIFO, accounting for the
// formatting pipeline depth. This will be conservative.
wire [9:0] wMaxEntries = (C_MAX_ENTRIES<<CONFIG_MAX_PAYLOAD_SIZE) + 3'd5 + C_DATA_DELAY;
always @ (posedge CLK) begin
rFifoCount <= #1 (RST ? {C_FIFO_DEPTH_WIDTH{1'd0}} : _rFifoCount);
rMaxEntries <= #1 (RST ? 10'd0 : _rMaxEntries);
rSpaceAvail <= #1 (RST ? 1'd0 : _rSpaceAvail);
end
always @ (*) begin
_rFifoCount = FIFO_COUNT;
_rMaxEntries = wMaxEntries;
_rSpaceAvail = (rFifoCount + rMaxEntries < C_FIFO_DEPTH);
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST ? `S_TXENGUPR128_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountAddr <= #1 _rCountAddr;
rCountAddr64 <= #1 _rCountAddr64;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountValid <= #1 _rCountValid;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCountLen = rCountLen;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountAddr = rCountAddr;
_rCountAddr64 = rCountAddr64;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountValid = rCountValid;
_rWrDataRen = rWrDataRen;
case (rMainState)
`S_TXENGUPR128_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountAddr = rCapAddr;
_rCountAddr64 = rCapAddr64;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 3'd4);
_rWrDataRen = ((rSpaceAvail & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR128_CAP_REL
_rCountValid = (rSpaceAvail & rCapState[3]);
if (rSpaceAvail && rCapState[3] && rCapIsWr && (rCapAddr64 || (rCapLen != 10'd1))) // S_TXENGUPR128_CAP_REL
_rMainState = `S_TXENGUPR128_MAIN_WR;
end
`S_TXENGUPR128_MAIN_WR : begin
_rCount = rCount - 3'd4;
_rCountDone = (rCount <= 4'd8);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = `S_TXENGUPR128_MAIN_IDLE;
end
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCountIsWr};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCountAddr};
_rAddr64 = {rAddr64[((C_DATA_DELAY-1)*1)-1:0], rCountAddr64};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rLenEQ1 = {rLenEQ1[((C_DATA_DELAY-1)*1)-1:0], (rCountLen == 10'd1)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid};
end
// Format the read or write request into PCI packets. Note that
// the supplied WR_DATA must be synchronized to arrive the same
// cycle that VALID is asserted.
tx_engine_formatter_128 #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)) formatter (
.RST(RST),
.CLK(CLK),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.VALID(rValid[(C_DATA_DELAY-1)*1 +:1]),
.WNR(rWnR[(C_DATA_DELAY-1)*1 +:1]),
.CHNL(rChnl[(C_DATA_DELAY-1)*4 +:4]),
.TAG(rTag[(C_DATA_DELAY-1)*8 +:8]),
.ADDR(rAddr[(C_DATA_DELAY-1)*62 +:62]),
.ADDR_64(rAddr64[(C_DATA_DELAY-1)*1 +:1]),
.LEN(rLen[(C_DATA_DELAY-1)*10 +:10]),
.LEN_ONE(rLenEQ1[(C_DATA_DELAY-1)*1 +:1]),
.WR_DATA(wWrDataSwap),
.OUT_DATA(FIFO_DATA),
.OUT_DATA_WEN(FIFO_WEN)
);
endmodule |
module tx_engine_lower_32 #(
parameter C_PCI_DATA_WIDTH = 9'd32,
parameter C_NUM_CHNL = 4'd12
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
output [C_PCI_DATA_WIDTH-1:0] TX_DATA, // AXI data output
output [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE, // AXI data keep
output TX_TLP_END_FLAG, // AXI data last
output TX_TLP_START_FLAG, // AXI data start
output TX_DATA_VALID, // AXI data valid
output S_AXIS_SRC_DSC, // AXI data discontinue
input TX_DATA_READY, // AXI ready for data
input COMPL_REQ, // RX Engine request for completion
output COMPL_DONE, // Completion done
input [2:0] REQ_TC,
input REQ_TD,
input REQ_EP,
input [1:0] REQ_ATTR,
input [9:0] REQ_LEN,
input [15:0] REQ_ID,
input [7:0] REQ_TAG,
input [3:0] REQ_BE,
input [29:0] REQ_ADDR,
input [31:0] REQ_DATA,
output [31:0] REQ_DATA_SENT, // Actual completion data sent
input [C_PCI_DATA_WIDTH-1:0] FIFO_DATA, // Read/Write FIFO requests + data
input FIFO_EMPTY, // Read/Write FIFO is empty
output FIFO_REN, // Read/Write FIFO read enable
output [C_NUM_CHNL-1:0] WR_SENT // Pulsed at channel pos when write request sent
);
reg [11:0] rByteCount=0;
reg [6:0] rLowerAddr=0;
reg rFifoRen=0, _rFifoRen=0;
reg rFifoRenIssued=0, _rFifoRenIssued=0;
reg rFifoDataEmpty=1, _rFifoDataEmpty=1;
reg [2:0] rFifoDataValid=0, _rFifoDataValid=0;
reg [(3*C_PCI_DATA_WIDTH)-1:0] rFifoData={3*C_PCI_DATA_WIDTH{1'd0}}, _rFifoData={3*C_PCI_DATA_WIDTH{1'd0}};
wire [C_PCI_DATA_WIDTH-1:0] wFifoData = (rFifoData>>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));
wire wFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);
reg [3:0] rState=`S_TXENGLWR32_IDLE, _rState=`S_TXENGLWR32_IDLE;
reg rComplDone=0, _rComplDone=0;
reg rValid=0, _rValid=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg rLast=0, _rLast=0;
reg [C_NUM_CHNL-1:0] rDone=0, _rDone=0;
reg [9:0] rLen=0, _rLen=0;
reg [3:0] rChnl=0, _rChnl=0;
reg r3DW=0, _r3DW=0;
reg rRNW=0, _rRNW=0;
reg rIsLast=0, _rIsLast=0;
assign TX_DATA = rData;
assign TX_DATA_BYTE_ENABLE = {4'hF};
assign TX_TLP_END_FLAG = rLast;
assign TX_TLP_START_FLAG = 1'b0;
assign TX_DATA_VALID = rValid;
assign S_AXIS_SRC_DSC = 1'b0;
assign COMPL_DONE = rComplDone;
assign REQ_DATA_SENT = {rData[7:0], rData[15:8], rData[23:16], rData[31:24]};
assign FIFO_REN = rFifoRen;
assign WR_SENT = rDone;
// Calculate byte count based on byte enable
always @ (REQ_BE) begin
casex (REQ_BE)
4'b1xx1 : rByteCount = 12'h004;
4'b01x1 : rByteCount = 12'h003;
4'b1x10 : rByteCount = 12'h003;
4'b0011 : rByteCount = 12'h002;
4'b0110 : rByteCount = 12'h002;
4'b1100 : rByteCount = 12'h002;
4'b0001 : rByteCount = 12'h001;
4'b0010 : rByteCount = 12'h001;
4'b0100 : rByteCount = 12'h001;
4'b1000 : rByteCount = 12'h001;
4'b0000 : rByteCount = 12'h001;
endcase
end
// Calculate lower address based on byte enable
always @ (REQ_BE or REQ_ADDR) begin
casex (REQ_BE)
4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};
4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};
4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};
endcase
end
// Read in the pre-formatted PCIe data.
always @ (posedge CLK) begin
rFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);
rFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);
rFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoRenIssued = rFifoRen;
_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);
if (rFifoRenIssued) begin
_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);
_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));
end
else begin
_rFifoData = rFifoData;
_rFifoDataValid = rFifoDataValid;
end
end
// Multiplex completion requests and read/write pre-formatted PCIe data onto
// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at
// *any* time during transmission. So be sure to buffer enough data to
// accommodate starts and stops.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGLWR32_IDLE : _rState);
rComplDone <= #1 (RST ? 1'd0 : _rComplDone);
rValid <= #1 (RST ? 1'd0 : _rValid);
rFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);
rDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);
rData <= #1 _rData;
rLast <= #1 _rLast;
rChnl <= #1 _rChnl;
r3DW <= #1 _r3DW;
rRNW <= #1 _rRNW;
rLen <= #1 _rLen;
rIsLast <= #1 _rIsLast;
end
always @ (*) begin
_rState = rState;
_rComplDone = rComplDone;
_rValid = rValid;
_rFifoRen = rFifoRen;
_rData = rData;
_rLast = rLast;
_rChnl = rChnl;
_rDone = rDone;
_r3DW = r3DW;
_rRNW = rRNW;
_rLen = rLen;
_rIsLast = rIsLast;
case (rState)
`S_TXENGLWR32_IDLE : begin
_rFifoRen = (TX_DATA_READY & !COMPL_REQ);
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rData = {wFifoData[31:20], 4'd0, wFifoData[15:0]}; // Revert the reserved 4 bits back to 0.
_rValid = (!COMPL_REQ & wFifoDataValid);
_rLast = 0;
_rChnl = wFifoData[19:16]; // CHNL buried in header
_r3DW = !wFifoData[29]; // !64 bit
_rRNW = !wFifoData[30]; // !Write TLP
_rLen = wFifoData[9:0]; // LEN
if (COMPL_REQ) // PIO read completions
_rState = `S_TXENGLWR32_CPLD_0;
else if (wFifoDataValid) // Read FIFO data if it's ready
_rState = `S_TXENGLWR32_MEM_0;
end
end
`S_TXENGLWR32_CPLD_0 : begin
if (TX_DATA_READY) begin // Check for throttling
_rValid = 1;
_rLast = 0;
_rData = {1'b0, `FMT_TXENGLWR32_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,
REQ_EP, REQ_ATTR, 2'b0, REQ_LEN};
_rState = `S_TXENGLWR32_CPLD_1;
end
end
`S_TXENGLWR32_CPLD_1 : begin
if (TX_DATA_READY) begin // Check for throttling
_rValid = 1;
_rLast = 0;
_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount};
_rState = `S_TXENGLWR32_CPLD_2;
end
end
`S_TXENGLWR32_CPLD_2 : begin
if (TX_DATA_READY) begin // Check for throttling
_rValid = 1;
_rLast = 0;
_rData = {REQ_ID, REQ_TAG, 1'b0, rLowerAddr};
_rState = `S_TXENGLWR32_CPLD_3;
end
end
`S_TXENGLWR32_CPLD_3 : begin
if (TX_DATA_READY) begin // Check for throttling
_rComplDone = 1;
_rValid = 1;
_rLast = 1;
_rData = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};
_rState = `S_TXENGLWR32_CPLD_4;
end
end
`S_TXENGLWR32_CPLD_4 : begin
// Just wait a cycle for the COMP_REQ to drop.
_rComplDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rValid = 0;
_rState = `S_TXENGLWR32_IDLE;
end
end
`S_TXENGLWR32_MEM_0 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rLast = 0;
_rState = (rRNW ? `S_TXENGLWR32_RD_0 : `S_TXENGLWR32_WR_0);
end
end
`S_TXENGLWR32_RD_0 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rLast = r3DW;
_rState = (r3DW ? `S_TXENGLWR32_IDLE : `S_TXENGLWR32_RD_1);
end
end
`S_TXENGLWR32_RD_1 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rLast = 1;
_rState = `S_TXENGLWR32_IDLE;
end
end
`S_TXENGLWR32_WR_0 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rDone = (1'd1<<rChnl);
_rData = wFifoData;
_rValid = 1;
_rLast = 0;
_rIsLast = (rLen == 1'd1);
_rState = (r3DW ? `S_TXENGLWR32_WR_2 : `S_TXENGLWR32_WR_1);
end
end
`S_TXENGLWR32_WR_1 : begin
_rFifoRen = TX_DATA_READY;
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rLast = 0;
_rIsLast = (rLen == 1'd1);
_rState = `S_TXENGLWR32_WR_2;
end
end
`S_TXENGLWR32_WR_2 : begin
_rFifoRen = TX_DATA_READY;
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rLast = rIsLast;
_rLen = rLen - 1'd1;
_rIsLast = (rLen == 2'd2);
_rState = (rIsLast ? `S_TXENGLWR32_IDLE : `S_TXENGLWR32_WR_2);
end
end
default : begin
_rState = `S_TXENGLWR32_IDLE;
end
endcase
end
endmodule |
module reorder_queue_output #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8, // Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5, // Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
output [C_DATA_ADDR_WIDTH-1:0] DATA_ADDR, // Address of stored packet data
input [C_PCI_DATA_WIDTH-1:0] DATA, // Stored packet data
input [C_NUM_TAGS-1:0] TAG_FINISHED, // Bitmap of finished tags
output [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [C_TAG_WIDTH-1:0] TAG, // Tag for which to retrieve packet data
input [5:0] TAG_MAPPED, // Mapped tag (i.e. internal tag)
input [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of packet payload in DWs
input PKT_WORDS_LTE1, // True if total count of packet payload is <= 4 DWs
input PKT_WORDS_LTE2, // True if total count of packet payload is <= 8 DWs
input PKT_DONE, // Packet done flag
input PKT_ERR, // Packet error flag
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
`include "common_functions.v"
reg [1:0] rState=0;
reg [C_DATA_ADDR_WIDTH-1:0] rDataAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rData=0;
reg rTagFinished=0;
reg [C_NUM_TAGS-1:0] rClear=0;
reg [C_TAG_WIDTH-1:0] rTag=0;
reg [C_TAG_WIDTH-1:0] rTagCurr=0;
wire [C_TAG_WIDTH-1:0] wTagNext = rTag + 1'd1;
reg [5:0] rShift;
reg rDone=0;
reg rDoneLast=0;
reg rErr=0;
reg rErrLast=0;
reg [C_PCI_DATA_COUNT_WIDTH-1:0] rDE=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rWords=0;
reg rLTE2Pkts=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataOut={C_PCI_DATA_WIDTH{1'b0}};
reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
reg [(3*16)-1:0] rDoneOut={3*16{1'd0}};
reg [(3*16)-1:0] rErrOut={3*16{1'd0}};
assign DATA_ADDR = rDataAddr;
assign TAG = rTag;
assign TAG_CLEAR = rClear;
assign ENG_DATA = rDataOut;
assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];
assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];
assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];
// Output completed data in increasing tag order, avoid stalls if possible
always @ (posedge CLK) begin
if (RST) begin
rState <= #1 0;
rTag <= #1 0;
rDataAddr <= #1 0;
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
rTagFinished <= #1 0;
end
else begin
rTagFinished <= #1 TAG_FINISHED[rTag];
case (rState)
2'd0: begin // Request initial data and final info, output nothing
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd1: begin // Request initial data and final info, output last data
rDone <= #1 rDoneLast;
rErr <= #1 rErrLast;
rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd2: begin // Initial data now available, output data
rShift <= #1 TAG_MAPPED;
rDoneLast <= #1 PKT_DONE;
rErrLast <= #1 PKT_ERR;
rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
if (PKT_WORDS_LTE1) begin // Guessed wrong, no addl data, need to reset
rDone <= #1 PKT_DONE;
rErr <= #1 PKT_ERR;
rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd0;
end
else if (PKT_WORDS_LTE2) begin // Guessed right, end of data, output last and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // Guessed right, more data, output it and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
2'd3: begin // Next data now available, output data
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
if (rLTE2Pkts) begin // End of data, output last and continue
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // More data, output it and continue
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
endcase
end
end
// Output the data
always @ (posedge CLK) begin
rData <= #1 DATA;
rDataOut <= #1 rData;
if (RST) begin
rDEOut <= #1 0;
rDoneOut <= #1 0;
rErrOut <= #1 0;
end
else begin
rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
rDoneOut <= #1 (rDone | rErr)<<rShift;
rErrOut <= #1 rErr<<rShift;
end
end
endmodule |
module translation_layer_64
#(parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 10'd64,
parameter C_RX_READY_LATENCY = 3'd2,
parameter C_TX_READY_LATENCY = 3'd2)
(
input CLK,
input RST_IN,
// Xilinx Signals
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST, // Not used in the 128 bit interface
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,
input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,
input RERR_FWD,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
output S_AXIS_SRC_DSC,
input S_AXIS_TX_TREADY,
input [15:0] COMPLETER_ID,
input CFG_BUS_MSTR_ENABLE,
input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent
output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)
input RCB,
input [11:0] MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)
input [7:0] MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)
// Altera Signals
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_EMPTY,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY, // NC
input [31:0] TL_CFG_CTL,
input [3:0] TL_CFG_ADD,
input [52:0] TL_CFG_STS,
input [7:0] KO_CPL_SPC_HEADER,
input [11:0] KO_CPL_SPC_DATA,
input APP_MSI_ACK,
output APP_MSI_REQ,
// Unified Signals
output [C_PCI_DATA_WIDTH-1:0] RX_DATA,
output RX_DATA_VALID,
input RX_DATA_READY,
output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,
output RX_TLP_END_FLAG,
output [3:0] RX_TLP_END_OFFSET,
output RX_TLP_START_FLAG,
output [3:0] RX_TLP_START_OFFSET,
output RX_TLP_ERROR_POISON,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,
input TX_TLP_END_FLAG,
input TX_TLP_START_FLAG,
input TX_DATA_VALID,
input TX_TLP_ERROR_POISON,
output TX_DATA_READY,
output [15:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
output [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
output CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byt
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high
);
generate
if(C_ALTERA == 1'b1) begin : altera_translator_64
wire wEP;
wire [9:0] wLength; // Length field of the TLP Header
wire [4:0] wType; // Type field of the TLP header
wire [3:0] wFMT; // Format field of the TLP Header
wire w4DWH;
wire w3DWH;
wire wLenEven; // 1 if even number of TLP data words, else 0
wire wMsg;
wire [64:0] wAddr3DWH;
wire [64:0] wAddr4DWH;
wire wQWA4DWH;
wire wQWA3DWH;
/// Configuration signals
reg [15:0] rCfgCompleterId;
reg rCfgBusMstrEnable;
reg [2:0] rCfgMaxReadRequestSize;
reg [2:0] rCfgMaxPayloadSize;
reg rCfgInterruptMsienable;
reg rReadCompletionBoundarySel;
reg [3:0] rTlCfgAdd,_rTlCfgAdd;
reg [31:0] rTlCfgCtl,_rTlCfgCtl;
reg [52:0] rTlCfgSts,_rTlCfgSts;
reg [63:0] rRxStData;
reg rRxStValid;
reg rRxStEop;
reg rRxStSop;
reg rEP, _rEP;
reg rLenEven,_rLenEven;
reg rMsg,_rMsg;
reg r3DWH,_r3DWH;
reg r4DWH,_r4DWH;
reg rTlpEndOffset, _rTlpEndOffset;
// Valid when RX_ST_SOP & RX_ST_VALID
assign wEP = RX_ST_DATA[14];
assign wLength = RX_ST_DATA[9:0];
assign wType = RX_ST_DATA[28:24];
assign wFMT = RX_ST_DATA[31:29];
assign w4DWH = wFMT[0];
assign w3DWH = ~wFMT[0];
assign wLenEven = ~wLength[0];
assign wMsg = wType[4];
// Valid when rRxStSop & RX_ST_VALID
assign wAddr3DWH = {32'd0,RX_ST_DATA[31:0]};
assign wAddr4DWH = {RX_ST_DATA[31:0],RX_ST_DATA[63:32]};
assign wQWA3DWH = ~wAddr3DWH[2];
assign wQWA4DWH = ~wAddr4DWH[2];
always @(*) begin
// We expect to recieve three different types of packets
// 3 DWH Packets, 4 DWH Packets, and Messages (No address)
_rEP = wEP;
_rLenEven = wLenEven;
_rMsg = wMsg;
_r3DWH = w3DWH;
_r4DWH = w4DWH;
// If the whole TLP is of even length, then the end will be at
// offset byte 7, otherwise the end will be at byte offset 3
_rTlpEndOffset = ( rMsg & rLenEven) |
(~rMsg & (( rLenEven & r3DWH & wQWA3DWH)|
(~rLenEven & r3DWH & ~wQWA3DWH)|
( rLenEven & r4DWH & wQWA4DWH)|
(~rLenEven & r4DWH & ~wQWA4DWH)));
_rTlCfgCtl = TL_CFG_CTL;
_rTlCfgAdd = TL_CFG_ADD;
_rTlCfgSts = TL_CFG_STS;
end
always @(posedge CLK) begin // Should be the same clock as pld_clk
rTlCfgAdd <= _rTlCfgAdd;
rTlCfgCtl <= _rTlCfgCtl;
rTlCfgSts <= _rTlCfgSts;
rRxStData <= RX_ST_DATA;
rRxStValid <= RX_ST_VALID;
if(RX_ST_VALID) begin
rRxStEop <= RX_ST_EOP;
rRxStSop <= RX_ST_SOP;
end
if(rRxStSop) begin
rTlpEndOffset <= _rTlpEndOffset;
end
if(RX_ST_SOP & RX_ST_VALID) begin
rEP <= _rEP;
rLenEven <= _rLenEven;
rMsg <= _rMsg;
r3DWH <= _r3DWH;
r4DWH <= _r4DWH;
end
if(rTlCfgAdd == 4'h0) begin
rCfgMaxReadRequestSize <= rTlCfgCtl[30:28];
rCfgMaxPayloadSize <= rTlCfgCtl[23:21];
end
if(rTlCfgAdd == 4'h2) begin
rReadCompletionBoundarySel <= rTlCfgCtl[19];
end
if(rTlCfgAdd == 4'h3) begin
rCfgBusMstrEnable <= rTlCfgCtl[10];
end
if(rTlCfgAdd == 4'hD) begin
rCfgInterruptMsienable <= rTlCfgCtl[0];
end
if(rTlCfgAdd == 4'hF) begin
rCfgCompleterId <= {rTlCfgCtl[12:0],3'b0};
end
end // always @ (posedge CLK)
// Rx Interface (To PCIe Core)
assign RX_ST_READY = RX_DATA_READY;
// Rx Interface (From PCIe Core)
assign RX_DATA = rRxStData;
assign RX_DATA_VALID = rRxStValid;
assign RX_DATA_BYTE_ENABLE = {{4{rTlpEndOffset}},4'hF};
assign RX_TLP_END_FLAG = rRxStEop;
assign RX_TLP_END_OFFSET = {rTlpEndOffset,2'b11};
assign RX_TLP_START_FLAG = rRxStSop;
assign RX_TLP_START_OFFSET = 4'h0;
assign RX_TLP_ERROR_POISON = rEP;
// Configuration Interface
assign CONFIG_COMPLETER_ID = rCfgCompleterId;
assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;
assign CONFIG_LINK_WIDTH = rTlCfgSts[40:35];
assign CONFIG_LINK_RATE = rTlCfgSts[32:31];
assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;
assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;
assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;
assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;
assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;
assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;
// Interrupt interface
assign APP_MSI_REQ = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = APP_MSI_ACK;
tx_qword_aligner_64
#(
.C_ALTERA(C_ALTERA),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TX_READY_LATENCY(C_TX_READY_LATENCY)
)
aligner_inst
(
// Outputs
.TX_DATA_READY (TX_DATA_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_ST_READY (TX_ST_READY));
end else begin : xilinx_translator_64
// Rx Interface (From PCIe Core)
assign RX_DATA = M_AXIS_RX_TDATA;
assign RX_DATA_VALID = M_AXIS_RX_TVALID;
assign RX_DATA_BYTE_ENABLE = M_AXIS_RX_TKEEP;
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign RX_TLP_END_OFFSET = {3'b000,M_AXIS_RX_TKEEP[4]};
assign RX_TLP_START_FLAG = 1'd0;
assign RX_TLP_START_OFFSET = 4'h0;
assign RX_TLP_ERROR_POISON = RERR_FWD;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_DATA_READY;
// TX Interface (From PCIe Core)
assign TX_DATA_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_DATA;
assign S_AXIS_TX_TVALID = TX_DATA_VALID;
assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;
// Configuration Interface
assign CONFIG_COMPLETER_ID = COMPLETER_ID;
assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;
assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;
assign CONFIG_LINK_RATE = CFG_LINK_RATE;
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = RCB;
assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;
assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
end
endgenerate
endmodule |
module pcie_clocking_v6 # (
parameter IS_ENDPOINT = "TRUE",
parameter CAP_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter CAP_LINK_SPEED = 4'h1, // 1 - Gen1 , 2 - Gen2
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK_FREQ = 3 // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
)
(
input wire sys_clk,
input wire gt_pll_lock,
input wire sel_lnk_rate,
input wire [1:0] sel_lnk_width,
output wire sys_clk_bufg,
output wire pipe_clk,
output wire user_clk,
output wire block_clk,
output wire drp_clk,
output wire clock_locked
);
parameter TCQ = 1;
wire mmcm_locked;
wire mmcm_clkfbin;
wire mmcm_clkfbout;
wire mmcm_reset;
wire clk_500;
wire clk_250;
wire clk_125;
wire user_clk_prebuf;
wire sel_lnk_rate_d;
reg [1:0] reg_clock_locked = 2'b11;
// MMCM Configuration
localparam mmcm_clockin_period = (REF_CLK_FREQ == 0) ? 10 :
(REF_CLK_FREQ == 1) ? 8 :
(REF_CLK_FREQ == 2) ? 4 : 0;
localparam mmcm_clockfb_mult = (REF_CLK_FREQ == 0) ? 10 :
(REF_CLK_FREQ == 1) ? 8 :
(REF_CLK_FREQ == 2) ? 8 : 0;
localparam mmcm_divclk_divide = (REF_CLK_FREQ == 0) ? 1 :
(REF_CLK_FREQ == 1) ? 1 :
(REF_CLK_FREQ == 2) ? 2 : 0;
localparam mmcm_clock0_div = 4;
localparam mmcm_clock1_div = 8;
localparam mmcm_clock2_div = ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) ? 32 :
((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 :
((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) ? 16 :
((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : 2;
localparam mmcm_clock3_div = 2;
// MMCM Reset
assign mmcm_reset = 1'b0;
generate
// PIPE Clock BUFG.
if (CAP_LINK_SPEED == 4'h1) begin : GEN1_LINK
BUFG pipe_clk_bufg (.O(pipe_clk),.I(clk_125));
end else if (CAP_LINK_SPEED == 4'h2) begin : GEN2_LINK
SRL16E #(.INIT(0)) sel_lnk_rate_delay (.Q(sel_lnk_rate_d),
.D(sel_lnk_rate), .CLK(pipe_clk),.CE(clock_locked), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
BUFGMUX pipe_clk_bufgmux (.O(pipe_clk), .I0(clk_125),.I1(clk_250),.S(sel_lnk_rate_d));
end else begin : ILLEGAL_LINK_SPEED
//$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
//$finish;
end
// User Clock BUFG.
if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) begin : x1_GEN1_31_25
BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x1_GEN1_62_50
BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x1_GEN1_125_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x1_GEN1_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) begin : x1_GEN2_62_50
BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x1_GEN2_125_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x1_GEN2_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x2_GEN1_62_50
BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x2_GEN1_125_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x2_GEN1_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x2_GEN2_125_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x2_GEN2_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x4_GEN1_125_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x4_GEN1_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x4_GEN2_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x8_GEN1_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 4)) begin : x8_GEN2_250_00
BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
BUFG block_clk_bufg (.O(block_clk),.I(clk_500));
end else begin : ILLEGAL_CONFIGURATION
//$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
//$finish;
end
endgenerate
// DRP clk
BUFG drp_clk_bufg_i (.O(drp_clk), .I(clk_125));
// Feedback BUFG. Required for Temp Compensation
BUFG clkfbin_bufg_i (.O(mmcm_clkfbin), .I(mmcm_clkfbout));
// sys_clk BUFG.
BUFG sys_clk_bufg_i (.O(sys_clk_bufg), .I(sys_clk));
MMCM_ADV # (
// 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
.CLKFBOUT_MULT_F (mmcm_clockfb_mult),
.DIVCLK_DIVIDE (mmcm_divclk_divide),
.CLKFBOUT_PHASE(0),
// 10 for 100 MHz, 4 for 250 MHz
.CLKIN1_PERIOD (mmcm_clockin_period),
.CLKIN2_PERIOD (mmcm_clockin_period),
// 500 MHz / mmcm_clockx_div
.CLKOUT0_DIVIDE_F (mmcm_clock0_div),
.CLKOUT0_PHASE (0),
.CLKOUT1_DIVIDE (mmcm_clock1_div),
.CLKOUT1_PHASE (0),
.CLKOUT2_DIVIDE (mmcm_clock2_div),
.CLKOUT2_PHASE (0),
.CLKOUT3_DIVIDE (mmcm_clock3_div),
.CLKOUT3_PHASE (0)
) mmcm_adv_i (
.CLKFBOUT (mmcm_clkfbout),
.CLKOUT0 (clk_250), // 250 MHz for pipe_clk
.CLKOUT1 (clk_125), // 125 MHz for pipe_clk
.CLKOUT2 (user_clk_prebuf), // user clk
.CLKOUT3 (clk_500),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.DO (),
.DRDY (),
.CLKFBOUTB (),
.CLKFBSTOPPED (),
.CLKINSTOPPED (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3B (),
.PSDONE (),
.LOCKED (mmcm_locked),
.CLKFBIN (mmcm_clkfbin),
.CLKIN1 (sys_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PWRDWN (1'b0),
.PSCLK (1'b0),
.RST (mmcm_reset)
);
// Synchronize MMCM locked output
always @ (posedge pipe_clk or negedge gt_pll_lock) begin
if (!gt_pll_lock)
reg_clock_locked[1:0] <= #TCQ 2'b11;
else
reg_clock_locked[1:0] <= #TCQ {reg_clock_locked[0], 1'b0};
end
assign clock_locked = !reg_clock_locked[1] & mmcm_locked;
endmodule |
module axi_basic_tx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
output trn_tecrc_gen, // TX ECRC generate
input trn_lnk_up, // PCIe link up
// System
//-----------
input tready_thrtl, // TREADY from thrtl ctl
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Input register stage
reg [C_DATA_WIDTH-1:0] reg_tdata;
reg reg_tvalid;
reg [KEEP_WIDTH-1:0] reg_tkeep;
reg [3:0] reg_tuser;
reg reg_tlast;
reg reg_tready;
// Pipeline utility signals
reg trn_in_packet;
reg axi_in_packet;
reg flush_axi;
wire disable_trn;
reg reg_disable_trn;
wire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready;
wire axi_end_packet = axi_beat_live && s_axis_tx_tlast;
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
// 128-bit: 64-bit: 32-bit: //
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 //
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 //
// TRN DW2 maps to AXI DW1 //
// TRN DW3 maps to AXI DW0 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
assign trn_td = {reg_tdata[31:0],
reg_tdata[63:32],
reg_tdata[95:64],
reg_tdata[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
end
else begin : td_DW_swap_32
assign trn_td = reg_tdata;
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_tsof. If we're not currently in a packet and TVALID goes high, //
// assert TSOF. //
//----------------------------------------------------------------------------//
assign trn_tsof = reg_tvalid && !trn_in_packet;
//----------------------------------------------------------------------------//
// Create trn_in_packet. This signal tracks if the TRN interface is currently //
// in the middle of a packet, which is needed to generate trn_tsof //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
trn_in_packet <= #TCQ 1'b1;
end
else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_in_packet. This signal tracks if the AXI interface is currently //
// in the middle of a packet, which is needed in case the link goes down. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
axi_in_packet <= #TCQ 1'b0;
end
else begin
if(axi_beat_live && !s_axis_tx_tlast) begin
axi_in_packet <= #TCQ 1'b1;
end
else if(axi_beat_live) begin
axi_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create disable_trn. This signal asserts when the link goes down and //
// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn //
// depends on C_PM_PRIORITY, as described below. //
//----------------------------------------------------------------------------//
generate
// In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
// the link goes down until the the AXI interface is ready to accept packets
// again (via assertion of TREADY). By waiting for TREADY, we allow the
// previous value buffer to fill, so we're ready for any throttling by the
// user or the block.
if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b1;
end
else begin
// When the link goes down, disable the TRN interface.
if(!trn_lnk_up)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// When the link comes back up and the AXI interface is ready, we can
// release the pipeline and return to normal operation.
else if(!flush_axi && s_axis_tx_tready) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
assign disable_trn = reg_disable_trn;
end
// In the throttle-controlled pipeline, we don't have a previous value buffer.
// The throttle control mechanism handles TREADY, so all we need to do is
// detect when the link goes down and disable the TRN interface until the link
// comes back up and the AXI interface is finished flushing any packets.
else begin : thrtl_ctl_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b0;
end
else begin
// If the link is down and AXI is in packet, disable TRN and look for
// the end of the packet
if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// AXI packet is ending, so we're done flushing
else if(axi_end_packet) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
// Disable the TRN interface if link is down or we're still flushing the AXI
// interface.
assign disable_trn = reg_disable_trn || !trn_lnk_up;
end
endgenerate
//----------------------------------------------------------------------------//
// Convert STRB to RREM. Here, we are converting the encoding method for the //
// location of the EOF from AXI (tkeep) to TRN flavor (rrem). //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
//---------------------------------------//
// Conversion table: //
// trem | tkeep //
// [1] [0] | [15:12] [11:8] [7:4] [3:0] //
// ------------------------------------- //
// 1 1 | D3 D2 D1 D0 //
// 1 0 | -- D2 D1 D0 //
// 0 1 | -- -- D1 D0 //
// 0 0 | -- -- -- D0 //
//---------------------------------------//
wire axi_DW_1 = reg_tkeep[7];
wire axi_DW_2 = reg_tkeep[11];
wire axi_DW_3 = reg_tkeep[15];
assign trn_trem[1] = axi_DW_2;
assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
end
else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
assign trn_trem = reg_tkeep[7];
end
else begin : tkeep_to_trem_32
assign trn_trem = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Create remaining TRN signals //
//----------------------------------------------------------------------------//
assign trn_teof = reg_tlast;
assign trn_tecrc_gen = reg_tuser[0];
assign trn_terrfwd = reg_tuser[1];
assign trn_tstr = reg_tuser[2];
assign trn_tsrc_dsc = reg_tuser[3];
//----------------------------------------------------------------------------//
// Pipeline stage //
//----------------------------------------------------------------------------//
// We need one of two approaches for the pipeline stage depending on the
// C_PM_PRIORITY parameter.
generate
reg reg_tsrc_rdy;
// If set to FALSE, that means the user wants to use the TX packet boundary
// throttling feature. Since all Block throttling will now be predicted, we
// can use a simple straight-through pipeline.
if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tsrc_rdy <= #TCQ 1'b0;
end
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
// Hold trn_tsrc_rdy low when flushing a packet.
reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn;
end
end
assign trn_tsrc_rdy = reg_tsrc_rdy;
// With TX packet boundary throttling, TREADY is pipelined in
// axi_basic_tx_thrtl_ctl and wired through here.
assign s_axis_tx_tready = tready_thrtl;
end
//**************************************************************************//
// If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
// functionality intact isntead of TX packet boundary throttling. Now the
// Block could back-pressure at any time, which creates the standard problem
// of potential data loss due to the handshaking latency. Here we need a
// previous value buffer, just like the RX data path.
else begin : pm_prioity_pipeline
reg [C_DATA_WIDTH-1:0] tdata_prev;
reg tvalid_prev;
reg [KEEP_WIDTH-1:0] tkeep_prev;
reg tlast_prev;
reg [3:0] tuser_prev;
reg reg_tdst_rdy;
wire data_hold;
reg data_prev;
//------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between AXI and TRN, which causes //
// some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. //
// The added cycle of latency in the path causes the Block to fall behind //
// the AXI interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all //
// s_axis_tx_* signals in case the Block throttles. //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
tvalid_prev <= #TCQ 1'b0;
tkeep_prev <= #TCQ {KEEP_WIDTH{1'b0}};
tlast_prev <= #TCQ 1'b0;
tuser_prev <= #TCQ 4'h 0;
end
else begin
// prev buffer works by checking s_axis_tx_tready. When
// s_axis_tx_tready is asserted, a new value is present on the
// interface.
if(!s_axis_tx_tready) begin
tdata_prev <= #TCQ tdata_prev;
tvalid_prev <= #TCQ tvalid_prev;
tkeep_prev <= #TCQ tkeep_prev;
tlast_prev <= #TCQ tlast_prev;
tuser_prev <= #TCQ tuser_prev;
end
else begin
tdata_prev <= #TCQ s_axis_tx_tdata;
tvalid_prev <= #TCQ s_axis_tx_tvalid;
tkeep_prev <= #TCQ s_axis_tx_tkeep;
tlast_prev <= #TCQ s_axis_tx_tlast;
tuser_prev <= #TCQ s_axis_tx_tuser;
end
end
end
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the Block has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on TDATA
// - the Block has finished throttling, and is a little
// behind the user
// CURRENT state: the buffer passes the current value on TDATA
// - the Block is caught up and ready to receive the
// latest data from the user
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tdst_rdy <= #TCQ 1'b0;
end
else begin
reg_tdst_rdy <= #TCQ trn_tdst_rdy;
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
reg_tdata <= #TCQ tdata_prev;
reg_tvalid <= #TCQ tvalid_prev;
reg_tkeep <= #TCQ tkeep_prev;
reg_tlast <= #TCQ tlast_prev;
reg_tuser <= #TCQ tuser_prev;
end
// CURRENT state
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
// Logic to instruct pipeline to use previous bus values. Always use
// previous value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//------------------------------------------------------------------------//
// Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. //
//------------------------------------------------------------------------//
assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
//------------------------------------------------------------------------//
// Create TREADY //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_tready <= #TCQ 1'b0;
end
else begin
// If the link went down and we need to flush a packet in flight, hold
// TREADY high
if(flush_axi && !axi_end_packet) begin
reg_tready <= #TCQ 1'b1;
end
// If the link is up, TREADY is as follows:
// TREADY = 1 when trn_tsrc_rdy == 0
// - While idle, keep the pipeline primed and ready for the next
// packet
//
// TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
// - While in packet, throttle pipeline based on state of TRN
else if(trn_lnk_up) begin
reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
end
// If the link is down and we're not flushing a packet, hold TREADY low
// wait for link to come back up
else begin
reg_tready <= #TCQ 1'b0;
end
end
end
assign s_axis_tx_tready = reg_tready;
end
//--------------------------------------------------------------------------//
// Create flush_axi. This signal detects if the link goes down while the //
// AXI interface is in packet. In this situation, we need to flush the //
// packet through the AXI interface and discard it. //
//--------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
flush_axi <= #TCQ 1'b0;
end
else begin
// If the AXI interface is in packet and the link goes down, purge it.
if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
flush_axi <= #TCQ 1'b1;
end
// The packet is finished, so we're done flushing.
else if(axi_end_packet) begin
flush_axi <= #TCQ 1'b0;
end
end
end
endgenerate
endmodule |
module GTX_RX_VALID_FILTER_V6 #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [3:0] reg_state_rxvld_ei;
wire [3:0] state_rxvld_ei;
reg [4:0] reg_rxvld_count;
wire [4:0] rxvld_count;
reg [3:0] reg_rxvld_fallback;
wire [3:0] rxvld_fallback;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg gt_rxelecidle_qq;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rxelecidle_qq <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rxvalid_q <= #TCQ GT_RXVALID;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxelecidle_qq <= #TCQ gt_rxelecidle_q;
gt_rx_status_q <= #TCQ GT_RX_STATUS;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
// user_rxvalid generation
always @(posedge USER_CLK) begin
if (RESET) begin
reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
end else begin
case ( state_rxvld_ei )
USER_RXVLD_IDL : begin
if (eios_detected)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;
else
reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
end
USER_RXVLD_EI : begin
if (!gt_rxvalid_q)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;
else if (rxvld_fallback == 4'b1111)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
else
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;
end
USER_RXVLD_EI_DB0 : begin
if (gt_rxvalid_q)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;
else if (!PLM_IN_L0)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
else
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;
end
USER_RXVLD_EI_DB1 : begin
if (rxvld_count > CLK_COR_MIN_LAT)
reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
else
reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;
end
endcase
end
end
assign state_rxvld_ei = reg_state_rxvld_ei;
// RxValid counter
always @(posedge USER_CLK) begin
if (RESET) begin
reg_rxvld_count <= #TCQ 5'b00000;
end else begin
if ((gt_rxvalid_q) && (state_rxvld_ei == USER_RXVLD_EI_DB1))
reg_rxvld_count <= #TCQ reg_rxvld_count + 1'b1;
else
reg_rxvld_count <= #TCQ 5'b00000;
end
end
assign rxvld_count = reg_rxvld_count;
// RxValid fallback
always @(posedge USER_CLK) begin
if (RESET) begin
reg_rxvld_fallback <= #TCQ 4'b0000;
end else begin
if (state_rxvld_ei == USER_RXVLD_EI)
reg_rxvld_fallback <= #TCQ reg_rxvld_fallback + 1'b1;
else
reg_rxvld_fallback <= #TCQ 4'b0000;
end
end
assign rxvld_fallback = reg_rxvld_fallback;
// Delay pipe_rx_elec_idle
SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
reg awake_in_progress_q = 1'b0;
reg awake_see_com_q = 1'b0;
reg [3:0] awake_com_count_q = 4'b0000;
wire awake_see_com_0 = gt_rxvalid_q & (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_COM));
wire awake_see_com_1 = gt_rxvalid_q & (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_COM));
wire awake_see_com = (awake_see_com_0 || awake_see_com_1) && ~awake_see_com_q;
// Count 8 COMs, (not back-to-back), when waking up from electrical idle
// but not for L0s (which is L0).
wire awake_done = awake_in_progress_q && (awake_com_count_q[3:0] >= 4'hb);
wire awake_start = (~gt_rxelecidle_q && gt_rxelecidle_qq) || PLM_IN_RS;
wire awake_in_progress = awake_start || (~awake_done && awake_in_progress_q);
wire [3:0] awake_com_count_inced = awake_com_count_q[3:0] + 4'b0001;
wire [3:0] awake_com_count = (~awake_in_progress_q) ? 4'b0000 :
(awake_start) ? 4'b0000 :
(awake_see_com_q) ? awake_com_count_inced[3:0] :
awake_com_count_q[3:0];
wire rst_l = ~RESET;
always @(posedge USER_CLK) begin
awake_see_com_q <= #TCQ (rst_l) ? awake_see_com : 1'b0;
awake_in_progress_q <= #TCQ (rst_l) ? awake_in_progress : 1'b0;
awake_com_count_q[3:0] <= #TCQ (rst_l) ? awake_com_count[3:0] : 4'h0;
end
assign USER_RXVALID = ((state_rxvld_ei == USER_RXVLD_IDL) && ~awake_in_progress_q) ? gt_rxvalid_q : 1'b0;
assign USER_RXCHARISK[0] = USER_RXVALID ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (USER_RXVALID && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = (gt_rx_is_skp0_q) ? FTSOS_COM : gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = (gt_rx_is_skp1_q) ? FTSOS_COM : gt_rxdata_q[15:8];
assign USER_RX_STATUS = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rx_status_q : 3'b000;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
endmodule |
module tx_engine_formatter_64 #(
parameter C_PCI_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [7:0] TAG, // External tag
input [3:0] CHNL, // Internal tag (just channel portion)
input [61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXENGFMTR64_IDLE, _rState=`S_TXENGFMTR64_IDLE;
reg [61:0] rAddr=62'd0, _rAddr=62'd0;
reg rAddr64=0, _rAddr64=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0] rPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen=0, _rDataWen=0;
reg [9:0] rLen=0, _rLen=0;
reg rInitDone=0, _rInitDone=0;
reg rDone=0, _rDone=0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [C_PCI_DATA_WIDTH-1:0] wHdrData = ({WR_DATA[31:0], rAddr[29:0], 2'b00, rAddr[61:30]})>>(32*(!rAddr64));
wire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData})>>(32*(!rAddr64));
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR64_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rPrevData <= #1 _rPrevData;
rInitDone <= #1 _rInitDone;
rDone <= #1 _rDone;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rPrevData = WR_DATA;
_rAddr64 = rAddr64;
_rAddr = rAddr;
_rInitDone = rInitDone;
_rDone = (rLen <= 3'd4);
case (rState)
`S_TXENGFMTR64_IDLE : begin
_rLen = LEN - !ADDR_64 + 2'd2; // Subtract 1 for 32 bit (HDR has one), add 2 so we can always decrement by 2
_rAddr64 = ADDR_64;
_rAddr = ADDR;
_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, TAG,
(LEN_ONE ? 4'b0 : 4'b1111), 4'b1111, // DW1
1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN}; // DW0
_rDataWen = VALID;
_rInitDone = ((!ADDR_64 & LEN_ONE) | !WNR);
_rState = (VALID ? `S_TXENGFMTR64_HDR : `S_TXENGFMTR64_IDLE);
end
`S_TXENGFMTR64_HDR : begin // FIFO data should be available now (if it's a write)
_rLen = rLen - 2'd2;
_rData = wHdrData;
_rState = (rInitDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);
end
`S_TXENGFMTR64_WR : begin
_rLen = rLen - 2'd2;
_rData = wWrData;
_rState = (rDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);
end
default : begin
_rState = `S_TXENGFMTR64_IDLE;
end
endcase
end
endmodule |
module ram_2clk_1w_1r (
CLKA,
ADDRA,
WEA,
DINA,
CLKB,
ADDRB,
DOUTB
);
`include "common_functions.v"
parameter C_RAM_WIDTH = 32;
parameter C_RAM_DEPTH = 1024;
//Local parameters
parameter C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
input CLKA;
input CLKB;
input WEA;
input [C_RAM_ADDR_BITS-1:0] ADDRA;
input [C_RAM_ADDR_BITS-1:0] ADDRB;
input [C_RAM_WIDTH-1:0] DINA;
output [C_RAM_WIDTH-1:0] DOUTB;
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule |
module rx_port_requester_mux (
input RST,
input CLK,
input SG_RX_REQ, // Scatter gather RX read request
input [9:0] SG_RX_LEN, // Scatter gather RX read request length
input [63:0] SG_RX_ADDR, // Scatter gather RX read request address
output SG_RX_REQ_PROC, // Scatter gather RX read request processing
input SG_TX_REQ, // Scatter gather TX read request
input [9:0] SG_TX_LEN, // Scatter gather TX read request length
input [63:0] SG_TX_ADDR, // Scatter gather TX read request address
output SG_TX_REQ_PROC, // Scatter gather TX read request processing
input MAIN_REQ, // Main read request
input [9:0] MAIN_LEN, // Main read request length
input [63:0] MAIN_ADDR, // Main read request address
output MAIN_REQ_PROC, // Main read request processing
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output REQ_ACK // Request accepted
);
reg rRxReqAck=0, _rRxReqAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
reg [9:0] rLen=0, _rLen=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg rSgRxAck=0, _rSgRxAck=0;
reg rSgTxAck=0, _rSgTxAck=0;
reg rMainAck=0, _rMainAck=0;
reg rAck=0, _rAck=0;
assign SG_RX_REQ_PROC = rSgRxAck;
assign SG_TX_REQ_PROC = rSgTxAck;
assign MAIN_REQ_PROC = rMainAck;
assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
assign RX_REQ_ADDR = rAddr;
assign RX_REQ_LEN = rLen;
assign REQ_ACK = rAck;
// Buffer signals that come from outside the rx_port.
always @ (posedge CLK) begin
rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
end
always @ (*) begin
_rRxReqAck = RX_REQ_ACK;
end
// Handle issuing read requests. Scatter gather requests are processed
// with higher priority than the main channel.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rSgRxAck <= #1 _rSgRxAck;
rSgTxAck <= #1 _rSgTxAck;
rMainAck <= #1 _rMainAck;
rAck <= #1 _rAck;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rAddr = rAddr;
_rSgRxAck = rSgRxAck;
_rSgTxAck = rSgTxAck;
_rMainAck = rMainAck;
_rAck = rAck;
case (rState)
`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_TX_RX;
end
end
`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_RX_TX;
end
end
`S_RXPORTREQ_ISSUE: begin // Issue the request
_rAck = 0;
if (rRxReqAck) begin
_rSgRxAck = 0;
_rSgTxAck = 0;
_rMainAck = 0;
if (rSgRxAck)
_rState = `S_RXPORTREQ_TX_RX;
else
_rState = `S_RXPORTREQ_RX_TX;
end
end
default: begin
_rState = `S_RXPORTREQ_RX_TX;
end
endcase
end
endmodule |
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "common_functions.v"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (rLenValid ? (~LEN_LSB + 1'd1) : {rLenLSB1[rWrPtr], rLenLSB0[rWrPtr]});
_rLenLast = rLenLast;
_rLenLast[rWrPtr] = (rLenValid ? LEN_LAST : rLenLast[rWrPtr]);
end
endmodule |
module sg_list_reader_32 #(
parameter C_DATA_WIDTH = 9'd32
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [2:0] rRdState=`S_SGR32_RD_0, _rRdState=`S_SGR32_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [2:0] rCapState=`S_SGR32_CAP_0, _rCapState=`S_SGR32_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = !rRdState[2]; // Not S_SGR32_RD_0
assign VALID = rCapState[2]; // S_SGR32_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & !rRdState[2]); // Not S_SGR32_RD_0
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR32_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR32_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR32_CAP_0: begin
if (rDataValid) begin
_rAddr[31:0] = rData;
_rCapState = `S_SGR32_CAP_1;
end
end
`S_SGR32_CAP_1: begin
if (rDataValid) begin
_rAddr[63:32] = rData;
_rCapState = `S_SGR32_CAP_2;
end
end
`S_SGR32_CAP_2: begin
if (rDataValid) begin
_rLen = rData;
_rCapState = `S_SGR32_CAP_3;
end
end
`S_SGR32_CAP_3: begin
if (rDataValid)
_rCapState = `S_SGR32_CAP_RDY;
end
`S_SGR32_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR32_CAP_0;
end
default: begin
_rCapState = `S_SGR32_CAP_0;
end
endcase
case (rRdState)
`S_SGR32_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_1;
end
`S_SGR32_RD_1: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_2;
end
`S_SGR32_RD_2: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_3;
end
`S_SGR32_RD_3: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_WAIT;
end
`S_SGR32_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR32_RD_0;
end
default: begin
_rRdState = `S_SGR32_RD_0;
end
endcase
end
endmodule |
module tx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "common_functions.v"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_32 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data.
tx_port_buffer_32 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(),
.TX_SENT(TX_SENT)
);
endmodule |
module tx_engine_formatter_32 #(
parameter C_PCI_DATA_WIDTH = 9'd32,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [7:0] TAG, // External tag
input [3:0] CHNL, // Internal tag (just channel portion)
input [61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
reg [2:0] rState=`S_TXENGFMTR32_IDLE, _rState=`S_TXENGFMTR32_IDLE;
reg [61:0] rAddr=62'd0, _rAddr=62'd0;
reg rAddr64=0, _rAddr64=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0] rPrevData={C_PCI_DATA_WIDTH{1'd0}}, _rPrevData={C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen=0, _rDataWen=0;
reg [9:0] rLen=0, _rLen=0;
reg rLenEQ1=0, _rLenEQ1=0;
reg rWNR=0, _rWNR=0;
reg [7:0] rTag=0, _rTag=0;
reg rInitDone=0, _rInitDone=0;
reg rDone=0, _rDone=0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [31:0] wData = ({rPrevData, WR_DATA}>>(32*rAddr64));
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR32_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rWNR <= #1 _rWNR;
rTag <= #1 _rTag;
rLenEQ1 <= #1 _rLenEQ1;
rInitDone <= #1 _rInitDone;
rDone <= #1 _rDone;
rPrevData <= #1 _rPrevData;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rAddr64 = rAddr64;
_rAddr = rAddr;
_rWNR = rWNR;
_rTag = rTag;
_rLenEQ1 = rLenEQ1;
_rInitDone = rInitDone;
_rDone = rDone;
_rPrevData = WR_DATA;
case (rState)
`S_TXENGFMTR32_IDLE : begin
_rLen = LEN;
_rAddr64 = ADDR_64;
_rAddr = ADDR;
_rWNR = WNR;
_rTag = TAG;
_rLenEQ1 = LEN_ONE;
_rData = {1'b0, {WNR, ADDR_64, 5'd0}, 1'b0, C_TRAFFIC_CLASS, CHNL, 1'b0, 1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER, C_NO_SNOOP, 2'b0, LEN};
_rDataWen = VALID;
_rState = (VALID ? `S_TXENGFMTR32_HDR_0 : `S_TXENGFMTR32_IDLE);
end
`S_TXENGFMTR32_HDR_0 : begin
_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, rTag,
(rLenEQ1 ? 4'b0 : 4'b1111), 4'b1111};
_rInitDone = (!rAddr64 & !rWNR);
_rState = (rAddr64 ? `S_TXENGFMTR32_HDR_1 : `S_TXENGFMTR32_HDR_2);
end
`S_TXENGFMTR32_HDR_1 : begin
_rData = rAddr[61:30];
_rInitDone = !rWNR;
_rState = `S_TXENGFMTR32_HDR_2;
end
`S_TXENGFMTR32_HDR_2 : begin // FIFO data should be available now (if it's a write)
_rData = {rAddr[29:0], 2'b00};
_rDone = rLenEQ1;
_rState = (rInitDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);
end
`S_TXENGFMTR32_WR : begin
_rLen = rLen - 1'd1;
_rData = wData;
_rDone = (rLen == 2'd2);
_rState = (rDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);
end
default : begin
_rState = `S_TXENGFMTR32_IDLE;
end
endcase
end
endmodule |
module cross_domain_signal (
input CLK_A, // Clock for domain A
input CLK_A_SEND, // Signal from domain A to domain B
output CLK_A_RECV, // Signal from domain B received in domain A
input CLK_B, // Clock for domain B
output CLK_B_RECV, // Signal from domain A received in domain B
input CLK_B_SEND // Signal from domain B to domain A
);
// Sync level signals across domains.
syncff sigAtoB (.CLK(CLK_B), .IN_ASYNC(CLK_A_SEND), .OUT_SYNC(CLK_B_RECV));
syncff sigBtoA (.CLK(CLK_A), .IN_ASYNC(CLK_B_SEND), .OUT_SYNC(CLK_A_RECV));
endmodule |
module axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule |
module fifo_packer_64 (
input CLK,
input RST,
input [63:0] DATA_IN, // Incoming data
input [1:0] DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [63:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg [1:0] rPackedCount=0, _rPackedCount=0;
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [95:0] rPackedData=96'd0, _rPackedData=96'd0;
reg [63:0] rDataIn=64'd0, _rDataIn=64'd0;
reg [1:0] rDataInEn=0, _rDataInEn=0;
reg [63:0] rDataMasked=64'd0, _rDataMasked=64'd0;
reg [1:0] rDataMaskedEn=0, _rDataMaskedEn=0;
assign PACKED_DATA = rPackedData[63:0];
assign PACKED_WEN = rPackedCount[1];
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data until 2 words are available, then writes 2 words out.
wire [63:0] wMask = {64{1'b1}}<<(32*rDataInEn);
wire [63:0] wDataMasked = ~wMask & rDataIn;
always @ (posedge CLK) begin
rPackedCount <= #1 (RST ? 2'd0 : _rPackedCount);
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rPackedData <= #1 (RST ? 96'd0 : _rPackedData);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 2'd0 : _rDataInEn);
rDataMasked <= #1 _rDataMasked;
rDataMaskedEn <= #1 (RST ? 2'd0 : _rDataMaskedEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
_rDataMasked = wDataMasked;
_rDataMaskedEn = rDataInEn;
// Count what's in our buffer. When we reach 2 words, 2 words will be written
// out. If flush is requested, write out whatever remains.
if (rPackedFlush && rPackedCount[0])
_rPackedCount = 2;
else
_rPackedCount = rPackedCount + rDataMaskedEn - {rPackedCount[1], 1'd0};
// Shift data into and out of our buffer as we receive and write out data.
if (rDataMaskedEn != 2'd0)
_rPackedData = ((rPackedData>>(32*{rPackedCount[1], 1'd0})) | (rDataMasked<<(32*rPackedCount[0])));
else
_rPackedData = (rPackedData>>(32*{rPackedCount[1], 1'd0}));
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule |
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule |
module async_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2(C_REAL_DEPTH+1)
)
(
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "common_functions.v"
wire wCmpEmpty;
wire wCmpFull;
wire [C_DEPTH_BITS-1:0] wWrPtr;
wire [C_DEPTH_BITS-1:0] wRdPtr;
wire [C_DEPTH_BITS-1:0] wWrPtrP1;
wire [C_DEPTH_BITS-1:0] wRdPtrP1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_2clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
.CLKA(WR_CLK),
.ADDRA(wWrPtr),
.WEA(WR_EN & !WR_FULL),
.DINA(WR_DATA),
.CLKB(RD_CLK),
.ADDRB(wRdPtr),
.DOUTB(RD_DATA)
);
// Compare the pointers.
async_cmp #(.C_DEPTH_BITS(C_DEPTH_BITS)) asyncCompare (
.WR_RST(WR_RST),
.WR_CLK(WR_CLK),
.RD_RST(RD_RST),
.RD_CLK(RD_CLK),
.RD_VALID(RD_EN & !RD_EMPTY),
.WR_VALID(WR_EN & !WR_FULL),
.EMPTY(wCmpEmpty),
.FULL(wCmpFull),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1)
);
// Calculate empty
rd_ptr_empty #(.C_DEPTH_BITS(C_DEPTH_BITS)) rdPtrEmpty (
.RD_EMPTY(RD_EMPTY),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1),
.CMP_EMPTY(wCmpEmpty),
.RD_EN(RD_EN),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST)
);
// Calculate full
wr_ptr_full #(.C_DEPTH_BITS(C_DEPTH_BITS)) wrPtrFull (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.WR_EN(WR_EN),
.WR_FULL(WR_FULL),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.CMP_FULL(wCmpFull)
);
endmodule |
module async_cmp #(
parameter C_DEPTH_BITS = 4,
// Local parameters
parameter N = C_DEPTH_BITS-1
)
(
input WR_RST,
input WR_CLK,
input RD_RST,
input RD_CLK,
input RD_VALID,
input WR_VALID,
output EMPTY,
output FULL,
input [C_DEPTH_BITS-1:0] WR_PTR,
input [C_DEPTH_BITS-1:0] RD_PTR,
input [C_DEPTH_BITS-1:0] WR_PTR_P1,
input [C_DEPTH_BITS-1:0] RD_PTR_P1
);
reg rDir=0;
wire wDirSet = ( (WR_PTR[N]^RD_PTR[N-1]) & ~(WR_PTR[N-1]^RD_PTR[N]));
wire wDirClr = ((~(WR_PTR[N]^RD_PTR[N-1]) & (WR_PTR[N-1]^RD_PTR[N])) | WR_RST);
reg rRdValid=0;
reg rEmpty=1;
reg rFull=0;
wire wATBEmpty = ((WR_PTR == RD_PTR_P1) && (RD_VALID | rRdValid));
wire wATBFull = ((WR_PTR_P1 == RD_PTR) && WR_VALID);
wire wEmpty = ((WR_PTR == RD_PTR) && !rDir);
wire wFull = ((WR_PTR == RD_PTR) && rDir);
assign EMPTY = wATBEmpty || rEmpty;
assign FULL = wATBFull || rFull;
always @(posedge wDirSet or posedge wDirClr)
if (wDirClr)
rDir <= 1'b0;
else
rDir <= 1'b1;
always @(posedge RD_CLK) begin
rEmpty <= (RD_RST ? 1'd1 : wEmpty);
rRdValid <= (RD_RST ? 1'd0 : RD_VALID);
end
always @(posedge WR_CLK) begin
rFull <= (WR_RST ? 1'd0 : wFull);
end
endmodule |
module rd_ptr_empty #(
parameter C_DEPTH_BITS = 4
)
(
input RD_CLK,
input RD_RST,
input RD_EN,
output RD_EMPTY,
output [C_DEPTH_BITS-1:0] RD_PTR,
output [C_DEPTH_BITS-1:0] RD_PTR_P1,
input CMP_EMPTY
);
reg rEmpty=1;
reg rEmpty2=1;
reg [C_DEPTH_BITS-1:0] rRdPtr=0;
reg [C_DEPTH_BITS-1:0] rRdPtrP1=0;
reg [C_DEPTH_BITS-1:0] rBin=0;
reg [C_DEPTH_BITS-1:0] rBinP1=1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign RD_EMPTY = rEmpty;
assign RD_PTR = rRdPtr;
assign RD_PTR_P1 = rRdPtrP1;
// Gray coded pointer
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rRdPtr <= #1 0;
rRdPtrP1 <= #1 0;
end
else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rRdPtr <= #1 wGrayNext;
rRdPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not empty
assign wBinNext = (!rEmpty ? rBin + RD_EN : rBin);
assign wBinNextP1 = (!rEmpty ? rBinP1 + RD_EN : rBinP1);
assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge RD_CLK) begin
if (CMP_EMPTY)
{rEmpty, rEmpty2} <= #1 2'b11;
else
{rEmpty, rEmpty2} <= #1 {rEmpty2, CMP_EMPTY};
end
endmodule |
module wr_ptr_full #(
parameter C_DEPTH_BITS = 4
)
(
input WR_CLK,
input WR_RST,
input WR_EN,
output WR_FULL,
output [C_DEPTH_BITS-1:0] WR_PTR,
output [C_DEPTH_BITS-1:0] WR_PTR_P1,
input CMP_FULL
);
reg rFull=0;
reg rFull2=0;
reg [C_DEPTH_BITS-1:0] rPtr=0;
reg [C_DEPTH_BITS-1:0] rPtrP1=0;
reg [C_DEPTH_BITS-1:0] rBin=0;
reg [C_DEPTH_BITS-1:0] rBinP1=1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign WR_FULL = rFull;
assign WR_PTR = rPtr;
assign WR_PTR_P1 = rPtrP1;
// Gray coded pointer
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rPtr <= #1 0;
rPtrP1 <= #1 0;
end
else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rPtr <= #1 wGrayNext;
rPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not full
assign wBinNext = (!rFull ? rBin + WR_EN : rBin);
assign wBinNextP1 = (!rFull ? rBinP1 + WR_EN : rBinP1);
assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge WR_CLK) begin
if (WR_RST)
{rFull, rFull2} <= #1 2'b00;
else if (CMP_FULL)
{rFull, rFull2} <= #1 2'b11;
else
{rFull, rFull2} <= #1 {rFull2, CMP_FULL};
end
endmodule |
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule |
module pcie_pipe_lane_v6 #
(
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter TCQ = 1 // clock to out delay model
)
(
output wire [ 1:0] pipe_rx_char_is_k_o ,
output wire [15:0] pipe_rx_data_o ,
output wire pipe_rx_valid_o ,
output wire pipe_rx_chanisaligned_o ,
output wire [ 2:0] pipe_rx_status_o ,
output wire pipe_rx_phy_status_o ,
output wire pipe_rx_elec_idle_o ,
input wire pipe_rx_polarity_i ,
input wire pipe_tx_compliance_i ,
input wire [ 1:0] pipe_tx_char_is_k_i ,
input wire [15:0] pipe_tx_data_i ,
input wire pipe_tx_elec_idle_i ,
input wire [ 1:0] pipe_tx_powerdown_i ,
input wire [ 1:0] pipe_rx_char_is_k_i ,
input wire [15:0] pipe_rx_data_i ,
input wire pipe_rx_valid_i ,
input wire pipe_rx_chanisaligned_i ,
input wire [ 2:0] pipe_rx_status_i ,
input wire pipe_rx_phy_status_i ,
input wire pipe_rx_elec_idle_i ,
output wire pipe_rx_polarity_o ,
output wire pipe_tx_compliance_o ,
output wire [ 1:0] pipe_tx_char_is_k_o ,
output wire [15:0] pipe_tx_data_o ,
output wire pipe_tx_elec_idle_o ,
output wire [ 1:0] pipe_tx_powerdown_o ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [15:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_chanisaligned_qq;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_polarity_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [15:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;
assign pipe_rx_data_o = pipe_rx_data_i;
assign pipe_rx_valid_o = pipe_rx_valid_i;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;
assign pipe_rx_status_o = pipe_rx_status_i;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;
assign pipe_rx_polarity_o = pipe_rx_polarity_i;
assign pipe_tx_compliance_o = pipe_tx_compliance_i;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;
assign pipe_tx_data_o = pipe_tx_data_i;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;
end else if (PIPE_PIPELINE_STAGES == 1) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
end else begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;
assign pipe_rx_data_o = pipe_rx_data_q;
assign pipe_rx_valid_o = pipe_rx_valid_q;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;
assign pipe_rx_status_o = pipe_rx_status_q;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;
assign pipe_rx_polarity_o = pipe_rx_polarity_q;
assign pipe_tx_compliance_o = pipe_tx_compliance_q;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;
assign pipe_tx_data_o = pipe_tx_data_q;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;
end else if (PIPE_PIPELINE_STAGES == 2) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
pipe_rx_char_is_k_qq <= #TCQ 0;
pipe_rx_data_qq <= #TCQ 0;
pipe_rx_valid_qq <= #TCQ 0;
pipe_rx_chanisaligned_qq <= #TCQ 0;
pipe_rx_status_qq <= #TCQ 0;
pipe_rx_phy_status_qq <= #TCQ 0;
pipe_rx_elec_idle_qq <= #TCQ 0;
pipe_rx_polarity_qq <= #TCQ 0;
pipe_tx_compliance_qq <= #TCQ 0;
pipe_tx_char_is_k_qq <= #TCQ 0;
pipe_tx_data_qq <= #TCQ 0;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b10;
end else begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;
pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;
assign pipe_rx_data_o = pipe_rx_data_qq;
assign pipe_rx_valid_o = pipe_rx_valid_qq;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;
assign pipe_rx_status_o = pipe_rx_status_qq;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;
assign pipe_tx_data_o = pipe_tx_data_qq;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;
end
endgenerate
endmodule |
module recv_credit_flow_ctrl
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
input RX_ENG_RD_DONE, // Read completed
input TX_ENG_RD_REQ_SENT, // Read completion request issued
output RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
);
reg rCreditAvail=0;
reg rCplDAvail=0;
reg rCplHAvail=0;
reg [12:0] rMaxRecv=0;
reg [11:0] rCplDAmt=0;
reg [7:0] rCplHAmt=0;
reg [11:0] rCplD=0;
reg [7:0] rCplH=0;
assign RXBUF_SPACE_AVAIL = rCreditAvail;
// Determine the completions required for a max read completion request.
always @(posedge CLK) begin
rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
rCplDAmt <= #1 (rMaxRecv>>4);
rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
rCreditAvail <= #1 (rCplHAvail & rCplDAvail);
end
// Count the number of outstanding read completion requests.
always @ (posedge CLK) begin
if (RST) begin
rCplH <= #1 0;
rCplD <= #1 0;
end
else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH;
rCplD <= #1 rCplD;
end
else if (TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH + rCplHAmt;
rCplD <= #1 rCplD + rCplDAmt;
end
else if (RX_ENG_RD_DONE) begin
rCplH <= #1 rCplH - rCplHAmt;
rCplD <= #1 rCplD - rCplDAmt;
end
end
endmodule |
module riffa_endpoint #(
parameter C_PCI_DATA_WIDTH = 9'd64,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_ALTERA = 1'b1 // 1 if Altera, 0 if Xilinx
)
(
input CLK,
input RST_IN,
output RST_OUT,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [4:0] IS_SOF,
input [4:0] IS_EOF,
input RERR_FWD,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
output S_AXIS_SRC_DSC,
input S_AXIS_TX_TREADY,
input [15:0] COMPLETER_ID,
input CFG_BUS_MSTR_ENABLE,
input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent
output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent
input RCB,
input [11:0] MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)
input [7:0] MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)
// Altera Signals
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
input [31:0] TL_CFG_CTL,
input [3:0] TL_CFG_ADD,
input [52:0] TL_CFG_STS,
input [7:0] KO_CPL_SPC_HEADER,
input [11:0] KO_CPL_SPC_DATA,
input APP_MSI_ACK,
output APP_MSI_REQ,
// RIFFA Signals
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
wire INTR_LEGACY_RDY;
wire INTR_MSI_RDY;
wire INTR_MSI_REQUEST;
wire CONFIG_BUS_MASTER_ENABLE;
wire CONFIG_INTERRUPT_MSIENABLE;
wire [1:0] CONFIG_LINK_RATE;
wire [2:0] CONFIG_MAX_PAYLOAD_SIZE;
wire [2:0] CONFIG_MAX_READ_REQUEST_SIZE;
wire [5:0] CONFIG_LINK_WIDTH;
wire [15:0] CONFIG_COMPLETER_ID;
wire [11:0] CONFIG_MAX_CPL_DATA; // Receive credit limit for data
wire [7:0] CONFIG_MAX_CPL_HDR; // Receive credit limit for headers
wire CONFIG_CPL_BOUNDARY_SEL; // Read completion boundary (0=64 bytes, 1=128 byt
wire RX_DATA_READY;
wire RX_DATA_VALID;
wire RX_TLP_END_FLAG;
wire RX_TLP_ERROR_POISON;
wire RX_TLP_START_FLAG;
wire [3:0] RX_TLP_END_OFFSET;
wire [3:0] RX_TLP_START_OFFSET;
wire [C_PCI_DATA_WIDTH-1:0] RX_DATA;
wire [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE;
wire TX_DATA_READY;
wire TX_DATA_VALID;
wire TX_TLP_END_FLAG;
wire TX_TLP_ERROR_POISON;
wire TX_TLP_START_FLAG;
wire [C_PCI_DATA_WIDTH-1:0] TX_DATA;
wire [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE;
translation_layer
#(
// Parameters
.C_ALTERA(C_ALTERA),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
translation_layer_inst
(
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_SRC_DSC (S_AXIS_SRC_DSC),
.CFG_INTERRUPT (CFG_INTERRUPT),
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
.RX_DATA (RX_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_DATA_VALID (RX_DATA_VALID),
.RX_DATA_BYTE_ENABLE (RX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[3:0]),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[3:0]),
.RX_TLP_ERROR_POISON (RX_TLP_ERROR_POISON),
.TX_DATA_READY (TX_DATA_READY),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[15:0]),
.CONFIG_BUS_MASTER_ENABLE (CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH (CONFIG_LINK_WIDTH[5:0]),
.CONFIG_LINK_RATE (CONFIG_LINK_RATE[1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE (CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY (INTR_MSI_RDY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.IS_SOF (IS_SOF[4:0]),
.IS_EOF (IS_EOF[4:0]),
.RERR_FWD (RERR_FWD),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.COMPLETER_ID (COMPLETER_ID[15:0]),
.CFG_BUS_MSTR_ENABLE (CFG_BUS_MSTR_ENABLE),
.CFG_LINK_WIDTH (CFG_LINK_WIDTH[5:0]),
.CFG_LINK_RATE (CFG_LINK_RATE[1:0]),
.CFG_MAX_READ_REQUEST_SIZE (MAX_READ_REQUEST_SIZE[2:0]),
.CFG_MAX_PAYLOAD_SIZE (MAX_PAYLOAD_SIZE[2:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY),
.RCB (RCB),
.MAX_RC_CPLD (MAX_RC_CPLD[11:0]),
.MAX_RC_CPLH (MAX_RC_CPLH[7:0]),
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[31:0]),
.TL_CFG_ADD (TL_CFG_ADD[3:0]),
.TL_CFG_STS (TL_CFG_STS[52:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[7:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[11:0]),
.APP_MSI_ACK (APP_MSI_ACK),
.RX_DATA_READY (RX_DATA_READY),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_BYTE_ENABLE (TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_ERROR_POISON (TX_TLP_ERROR_POISON),
.INTR_MSI_REQUEST (INTR_MSI_REQUEST));
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : endpoint32
riffa_endpoint_32 #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_ALTERA(C_ALTERA)
) endpoint (
.CLK(CLK),
.RST_IN(RST_IN),
.RST_OUT(RST_OUT),
.RX_DATA(RX_DATA),
.RX_TLP_END_FLAG(RX_TLP_END_FLAG),
.RX_DATA_VALID(RX_DATA_VALID),
.RX_DATA_READY(RX_DATA_READY),
.RX_TLP_ERROR_POISON(RX_TLP_ERROR_POISON),
.TX_DATA(TX_DATA),
.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),
.TX_TLP_END_FLAG(TX_TLP_END_FLAG),
.TX_TLP_START_FLAG(TX_TLP_START_FLAG),
.TX_DATA_VALID(TX_DATA_VALID),
.S_AXIS_SRC_DSC(TX_TLP_ERROR_POISON),
.TX_DATA_READY(TX_DATA_READY),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH(CONFIG_LINK_WIDTH),
.CONFIG_LINK_RATE(CONFIG_LINK_RATE),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA(CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR(CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST),
.CHNL_RX_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN),
.CHNL_TX_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
end
else if (C_PCI_DATA_WIDTH == 9'd64) begin : endpoint64
riffa_endpoint_64 #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_ALTERA(C_ALTERA)
) endpoint (
.CLK(CLK),
.RST_IN(RST_IN),
.RST_OUT(RST_OUT),
.RX_DATA(RX_DATA),
.RX_DATA_BYTE_ENABLE(RX_DATA_BYTE_ENABLE),
.RX_TLP_END_FLAG(RX_TLP_END_FLAG),
.TX_TLP_START_FLAG(TX_TLP_START_FLAG),
.RX_DATA_VALID(RX_DATA_VALID),
.RX_DATA_READY(RX_DATA_READY),
.RX_TLP_ERROR_POISON(RX_TLP_ERROR_POISON),
.TX_DATA(TX_DATA),
.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),
.TX_TLP_END_FLAG(TX_TLP_END_FLAG),
.TX_DATA_VALID(TX_DATA_VALID),
.S_AXIS_SRC_DSC(TX_TLP_ERROR_POISON),
.TX_DATA_READY(TX_DATA_READY),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH(CONFIG_LINK_WIDTH),
.CONFIG_LINK_RATE(CONFIG_LINK_RATE),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA(CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR(CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST),
.CHNL_RX_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN),
.CHNL_TX_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
end
else if (C_PCI_DATA_WIDTH == 9'd128) begin : endpoint128
riffa_endpoint_128 #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_ALTERA(C_ALTERA)
) endpoint (
.CLK(CLK),
.RST_IN(RST_IN),
.RST_OUT(RST_OUT),
.RX_DATA(RX_DATA),
.RX_DATA_VALID(RX_DATA_VALID),
.RX_DATA_READY(RX_DATA_READY),
.RX_TLP_END_FLAG(RX_TLP_END_FLAG),
.RX_TLP_START_FLAG(RX_TLP_START_FLAG),
.RX_TLP_END_OFFSET(RX_TLP_END_OFFSET),
.RX_TLP_START_OFFSET(RX_TLP_START_OFFSET),
.RX_TLP_ERROR_POISON(RX_TLP_ERROR_POISON),
.TX_DATA(TX_DATA),
.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),
.TX_TLP_END_FLAG(TX_TLP_END_FLAG),
.TX_TLP_START_FLAG(TX_TLP_START_FLAG),
.TX_DATA_VALID(TX_DATA_VALID),
.S_AXIS_SRC_DSC(TX_TLP_ERROR_POISON),
.TX_DATA_READY(TX_DATA_READY),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH(CONFIG_LINK_WIDTH),
.CONFIG_LINK_RATE(CONFIG_LINK_RATE),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA(CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR(CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST),
.CHNL_RX_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN),
.CHNL_TX_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
end
endgenerate
endmodule |
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input RST,
input CLK,
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "common_functions.v"
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @ (*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @ (posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoData = wFifoData;
end
endmodule |
module tx_qword_aligner_64
#(
parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 9'd64,
parameter C_TX_READY_LATENCY = 3'd1
)
(
input CLK,
input RST_IN,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_VALID,
output TX_DATA_READY,
input TX_TLP_END_FLAG,
input TX_TLP_START_FLAG,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output TX_ST_EMPTY
);
reg [C_TX_READY_LATENCY-1:0] rTxStReady, _rTxStReady;
// Registers for first cycle of pipeline (upper)
// Capture
reg [C_PCI_DATA_WIDTH-1:0] rTxData,_rTxData;
reg rTxDataValid, _rTxDataValid;
reg rTxTlpEndFlag, _rTxTlpEndFlag;
reg rTxTlpStartFlag, _rTxTlpStartFlag;
// Registers for the second cycle of the state machine
reg r3DWHInsBlank,_r3DWHInsBlank;
reg [C_PCI_DATA_WIDTH+32-1:0] rAlignBuffer, _rAlignBuffer;
// Registers for the third cycle of the state machine
reg r4DWHInsBlank,_r4DWHInsBlank;
// State (controls upper pipeline)
reg [1:0] rUpState, _rUpState;
reg rSel, _rSel;
reg rTrigger,_rTrigger;
// Second stage of pipeline (lower)
reg [1:0] rLowState, _rLowState;
// Registered Outputs
reg rTxStValid,_rTxStValid;
reg rTxStEop,_rTxStEop;
reg rTxStSop,_rTxStSop;
// Wires
wire [1:0] wRegEn;
reg r4DWH, _r4DWH;
reg r3DWH, _r3DWH;
reg rDataTLP, _rDataTLP;
reg rLenEven,_rLenEven;
reg rLenOdd,_rLenOdd;
reg r4DWHQWA, _r4DWHQWA;
reg r3DWHQWA, _r3DWHQWA;
wire [127:0] wAlignBufMux;
wire w3DWHInsBlank;
wire w4DWHInsBlank;
wire wOverflow;
wire wSMLowEnable;
wire wSMUpEnable;
wire wTxStEopCondition;
// Unconditional input capture
always @(*) begin
_rTxStReady = (rTxStReady << 1) | TX_ST_READY;
end
always @(posedge CLK) begin
rTxStReady <= _rTxStReady;
end
// Take data when:
assign wRegEn[0] = (~rTxDataValid | wRegEn[1]);
assign wSMUpEnable = wRegEn[0];
assign TX_DATA_READY = wRegEn[0];
always @(*) begin
_rTxData = TX_DATA;
_rTxTlpEndFlag = TX_TLP_END_FLAG & TX_DATA_VALID;
_rTxTlpStartFlag = TX_TLP_START_FLAG & TX_DATA_VALID;
end // always @ begin
always @(posedge CLK) begin
if(wRegEn[0]) begin
rTxData <= _rTxData;
rTxTlpEndFlag <= _rTxTlpEndFlag;
rTxTlpStartFlag <= _rTxTlpStartFlag;
end
end
always @(*) begin
_r4DWH = rTxData[29] & rTxTlpStartFlag;
_r3DWH = ~rTxData[29] & rTxTlpStartFlag;
_rDataTLP = rTxData[30] & rTxTlpStartFlag;
_rLenEven = ~rTxData[0] & rTxTlpStartFlag;
_rLenOdd = rTxData[0] & rTxTlpStartFlag;
_r4DWHQWA = ~TX_DATA[34] & rTxTlpStartFlag;
_r3DWHQWA = ~TX_DATA[2] & rTxTlpStartFlag;
end // always @ begin
always @(posedge CLK) begin
if(wRegEn[0]) begin
r4DWH <= _r4DWH;
r3DWH <= _r3DWH;
rDataTLP <= _rDataTLP;
rLenEven <= _rLenEven;
rLenOdd <= _rLenOdd;
r4DWHQWA <= _r4DWHQWA;
r3DWHQWA <= _r3DWHQWA;
end
end
// State machine for the upper pipeline
// Valid never goes down inside of a TLP.
always @(*) begin
_rTxDataValid = rTxDataValid;
if(wSMUpEnable & TX_DATA_VALID) begin // & TX_TLP_START_FLAG
_rTxDataValid = 1'b1;
end else if ( wSMUpEnable & rTxTlpEndFlag)begin
_rTxDataValid = 1'b0;
end
_rUpState = rUpState;
case (rUpState)
`S_TXALIGNER64UP_IDLE: begin
if (TX_DATA_VALID & wSMUpEnable) begin
_rUpState = `S_TXALIGNER64UP_HDR0;
end
end
`S_TXALIGNER64UP_HDR0: begin
if(wSMUpEnable) begin
_rUpState = `S_TXALIGNER64UP_HDR1;
end
end
`S_TXALIGNER64UP_HDR1: begin
if(wSMUpEnable) begin
casex ({rTxTlpEndFlag,TX_DATA_VALID})
2'b0x: _rUpState = `S_TXALIGNER64UP_PAY;
2'b10: _rUpState = `S_TXALIGNER64UP_IDLE; // No new TLP
2'b11: _rUpState = `S_TXALIGNER64UP_HDR0;
endcase // case (rTxTlpEndFlag)
end
end
`S_TXALIGNER64UP_PAY : begin
if(wSMUpEnable) begin
casex ({rTxTlpEndFlag,TX_DATA_VALID})
2'b0x: _rUpState = `S_TXALIGNER64UP_PAY;
2'b10: _rUpState = `S_TXALIGNER64UP_IDLE; // No new TLP
2'b11: _rUpState = `S_TXALIGNER64UP_HDR0;
endcase // case (rTxTlpEndFlag)
end
end
endcase // case (rUpState)
end // always @ begin
always @(posedge CLK) begin
rTxDataValid <= _rTxDataValid;
if(RST_IN) begin
rUpState <= `S_TXALIGNER64UP_IDLE;
end else begin
rUpState <= _rUpState;
end
end // always @ (posedge CLK)
assign wSMLowEnable = rTxStReady[C_TX_READY_LATENCY-1] | ~rTxStValid;
assign wRegEn[1] = ~(rLowState == `S_TXALIGNER64LOW_PREOVFL & rTrigger) & (wSMLowEnable);
assign w3DWHInsBlank = rDataTLP & r3DWH & r3DWHQWA;
assign w4DWHInsBlank = rDataTLP & r4DWH & ~r4DWHQWA;
assign wOverflow = (w4DWHInsBlank & rLenEven) | (w3DWHInsBlank & rLenOdd);
assign wAlignBufMux = ({{rTxData[31:0],rAlignBuffer[95:64]},rTxData[63:0]}) >> ({rSel,6'd0});
always @(*) begin
_rAlignBuffer = {rTxData[63:32], wAlignBufMux[63:0]};
end // always @ begin
always @(posedge CLK) begin
if(wSMLowEnable) begin
rAlignBuffer <= _rAlignBuffer;
end
end
assign wTxStEopCondition = (rLowState == `S_TXALIGNER64LOW_PREOVFL & rTrigger) |
(rLowState != `S_TXALIGNER64LOW_PREOVFL & {rTxTlpEndFlag,wOverflow,rTxDataValid} == 3'b101);
// Valid never goes down inside of a TLP.
always @(*) begin
_rLowState = rLowState;
_rTrigger = rTrigger;
_rTxStValid = rTxStValid;
_rTxStEop = rTxStEop;
_rTxStSop = rTxStSop;
_rSel = rSel;
_rTxStEop = wTxStEopCondition;
_rTrigger = rTxDataValid & rTxTlpEndFlag;
// Take the next txDataValid if we are taking data (wRegEn[1])
// and it's a start flag and the data is valid
if ( wRegEn[1] & rTxTlpStartFlag & rTxDataValid ) begin
_rTxStValid = 1;
end else if ( wSMLowEnable & rTxStEop | RST_IN ) begin
_rTxStValid = 0;
end
if ( wRegEn[1] & rTxDataValid ) begin
_rTxStSop = rTxTlpStartFlag;
end else if ( wSMLowEnable | RST_IN) begin
_rTxStSop = 0;
end
// rSel should be set on wInsBlank kept high until the end of the packet
// Note: rSel is only applicable in multi-cycle packets
if (wSMLowEnable & (w3DWHInsBlank | w4DWHInsBlank)) begin
_rSel = 1'b1;
end else if (wSMLowEnable & wTxStEopCondition | RST_IN) begin
_rSel = 1'b0;
end
case (rLowState)
`S_TXALIGNER64LOW_IDLE : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // Stay here
3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Process
3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)
3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // Set rTxStEop
3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
`S_TXALIGNER64LOW_PROC : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle
3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Continue processing
3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)
3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // set rTxStEop
3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
`S_TXALIGNER64LOW_PREOVFL : begin
if(wSMLowEnable) begin
if(rTrigger) begin
_rLowState = `S_TXALIGNER64LOW_OVFL;
end
end
end
`S_TXALIGNER64LOW_OVFL : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER64LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle
3'b001: _rLowState = `S_TXALIGNER64LOW_PROC; // Continue processing
3'b011: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (Don't set trigger)
3'b101: _rLowState = `S_TXALIGNER64LOW_PROC; // set rTxStEop
3'b111: _rLowState = `S_TXALIGNER64LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
endcase
end // always @ begin
always @(posedge CLK) begin
if(RST_IN) begin
rLowState <= `S_TXALIGNER64LOW_IDLE;
rTxStValid <= 0;
rTxStSop <= 0;
rSel <= 0;
end else begin
rTxStValid <= _rTxStValid;
rTxStSop <= _rTxStSop;
rSel <= _rSel;
rLowState <= _rLowState;
end
if (RST_IN) begin
rTxStEop <= 1'b0;
end else if (wSMLowEnable) begin
rTxStEop <= _rTxStEop;
end
if (RST_IN) begin
rTrigger <= 1'b0;
end else if (wRegEn[1]) begin
rTrigger <= _rTrigger;
end
end // always @ (posedge CLK)
// Outputs from the aligner to the PCIe Core
assign TX_ST_VALID = (rTxStValid & rTxStReady[C_TX_READY_LATENCY-1]);
assign TX_ST_EOP = rTxStEop;
assign TX_ST_SOP = rTxStSop;
assign TX_ST_EMPTY = 1'b0;
assign TX_ST_DATA = rAlignBuffer[63:0];
endmodule |
module rx_engine_64 #(
parameter C_PCI_DATA_WIDTH = 9'd64,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_ALTERA = 1'b1, // 1 if Altera, 0 if Xilinx
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1)
)
(
input CLK,
input RST,
// Receive
input [C_PCI_DATA_WIDTH-1:0] RX_DATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,
input RX_TLP_END_FLAG,
input RX_DATA_VALID,
output RX_DATA_READY,
input RX_TLP_ERROR_POISON,
// Received read/write memory requests
output REQ_WR, // Memory write request
input REQ_WR_DONE, // Memory write completed
output REQ_RD, // Memory read request
input REQ_RD_DONE, // Memory read complete
output [9:0] REQ_LEN, // Memory length (1DW)
output [29:0] REQ_ADDR, // Memory address (bottom 2 bits are always 00)
output [31:0] REQ_DATA, // Memory write data
output [3:0] REQ_BE, // Memory byte enables
output [2:0] REQ_TC, // Memory traffic class
output REQ_TD, // Memory packet digest
output REQ_EP, // Memory poisoned packet
output [1:0] REQ_ATTR, // Memory packet relaxed ordering, no snoop
output [15:0] REQ_ID, // Memory requestor id
output [7:0] REQ_TAG, // Memory packet tag
// Tag exchange
input [5:0] INT_TAG, // Internal tag to exchange with external
input INT_TAG_VALID, // High to signal tag exchange
output [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
output EXT_TAG_VALID, // High to signal external tag is valid
// Received read completions
output ENG_RD_COMPLETE,
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
`include "common_functions.v"
reg [2:0] rTrigger=0, _rTrigger=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataIn=0, _rDataIn=0;
reg rValidIn=0, _rValidIn=0;
reg rKeepBothIn=0, _rKeepBothIn=0;
reg rLastIn=0, _rLastIn=0;
reg rLenOneIn=0, _rLenOneIn=0;
reg [2:0] rReqState=`S_RXENG64_REQ_PARSE, _rReqState=`S_RXENG64_REQ_PARSE;
reg [29:0] rReqAddr=0, _rReqAddr=0;
reg [31:0] rReqData=0, _rReqData=0;
reg rReqWen=0, _rReqWen=0;
reg rRNW=0, _rRNW=0;
reg [3:0] rBE=0, _rBE=0;
reg [2:0] rTC=0, _rTC=0;
reg rTD=0, _rTD=0;
reg rEP=0, _rEP=0;
reg [1:0] rAttr=0, _rAttr=0;
reg [9:0] rReqLen=0, _rReqLen=0;
reg [15:0] rReqId=0, _rReqId=0;
reg [7:0] rReqTag=0, _rReqTag=0;
reg r3DWHeader=0, _r3DWHeader=0;
reg [2:0] rCplState=`S_RXENG64_CPL_PARSE, _rCplState=`S_RXENG64_CPL_PARSE;
reg rCplErr=0, _rCplErr=0;
reg rLastCPLD=0, _rLastCPLD=0;
reg [C_PCI_DATA_COUNT_WIDTH-1:0]rDataOutCount=0, _rDataOutCount=0;
reg [C_PCI_DATA_WORD-1:0] rDataOutEn=0, _rDataOutEn=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataOut={C_PCI_DATA_WIDTH{1'b0}}, _rDataOut={C_PCI_DATA_WIDTH{1'b0}};
reg rDataDone=0, _rDataDone=0;
reg rDataErr=0, _rDataErr=0;
reg rDataValid=0, _rDataValid=0;
reg [7:0] rChnlShft=0, _rChnlShft=0;
reg rQWACpl,_rQWACpl;
reg rQWAReq,_rQWAReq;
wire wALTERA = C_ALTERA;
wire [31:0] wReqData;
wire [C_PCI_DATA_WIDTH-1:0] wDataOut;
assign wReqData = wALTERA? rReqData :{rReqData[7:0], rReqData[15:8], rReqData[23:16], rReqData[31:24]};
assign wDataOut = wALTERA? rDataOut :{rDataOut[39:32], rDataOut[47:40], rDataOut[55:48], rDataOut[63:56],
rDataOut[07:00], rDataOut[15:08], rDataOut[23:16], rDataOut[31:24]};
assign RX_DATA_READY = 1;
assign ENG_RD_COMPLETE = rDataDone;
// Handle servicing write & read memory requests in a separate state machine.
rx_engine_req #(
.C_NUM_CHNL(C_NUM_CHNL)
) rxEngReq (
.CLK(CLK),
.RST(RST),
.REQ_WR(REQ_WR),
.REQ_WR_DONE(REQ_WR_DONE),
.REQ_RD(REQ_RD),
.REQ_RD_DONE(REQ_RD_DONE),
.REQ_LEN(REQ_LEN),
.REQ_ADDR(REQ_ADDR),
.REQ_DATA(REQ_DATA),
.REQ_BE(REQ_BE),
.REQ_TC(REQ_TC),
.REQ_TD(REQ_TD),
.REQ_EP(REQ_EP),
.REQ_ATTR(REQ_ATTR),
.REQ_ID(REQ_ID),
.REQ_TAG(REQ_TAG),
.WEN(rReqWen),
.RNW(rRNW),
.LEN(rReqLen),
.ADDR(rReqAddr),
.DATA(wReqData),
.BE(rBE),
.TC(rTC),
.TD(rTD),
.EP(rEP),
.ATTR(rAttr),
.ID(rReqId),
.TAG(rReqTag)
);
// Handle reordering completion data.
reorder_queue #(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH)
) reorderQueue (
.CLK(CLK),
.RST(RST),
.VALID(rDataValid),
.DATA(wDataOut),
.DATA_EN(rDataOutEn),
.DATA_EN_COUNT(rDataOutCount),
.DONE(rDataDone),
.ERR(rDataErr),
.TAG(rChnlShft[C_TAG_WIDTH-1:0]),
.INT_TAG(INT_TAG),
.INT_TAG_VALID(INT_TAG_VALID),
.EXT_TAG(EXT_TAG),
.EXT_TAG_VALID(EXT_TAG_VALID),
.ENG_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR)
);
// Handle receiving data from PCIe receive channel.
wire wValid = (RX_DATA_VALID & !RX_TLP_ERROR_POISON);
always @ (posedge CLK) begin
rTrigger <= #1 (RST ? 3'd0 : _rTrigger);
rValidIn <= #1 (RST ? 1'd0 : _rValidIn);
rDataIn <= #1 _rDataIn;
rKeepBothIn <= #1 _rKeepBothIn;
rLastIn <= #1 _rLastIn;
rLenOneIn <= #1 _rLenOneIn;
rQWACpl <= #1 _rQWACpl;
end
always @ (*) begin
_rDataIn = rDataIn;
_rValidIn = rValidIn;
_rKeepBothIn = rKeepBothIn;
_rLastIn = rLastIn;
_rLenOneIn = rLenOneIn;
_rTrigger = rTrigger;
_rQWACpl = rQWACpl;
// Buffer the incoming data
_rDataIn = RX_DATA;
_rValidIn = (RX_DATA_VALID && !RX_TLP_ERROR_POISON);
_rKeepBothIn = (RX_DATA_BYTE_ENABLE == 8'hFF);
_rLastIn = RX_TLP_END_FLAG;
_rLenOneIn = (RX_DATA[9:0] == 10'd1);
_rQWACpl = ~RX_DATA[2];
// Direct the main FSM with what kind of packet this represents
case (RX_DATA[30:24])
`FMT_RXENG64_RD32 : _rTrigger = 3'd1 & ({3{wValid}});
`FMT_RXENG64_RD64 : _rTrigger = 3'd1 & ({3{wValid}});
`FMT_RXENG64_WR32 : _rTrigger = 3'd2 & ({3{wValid}});
`FMT_RXENG64_WR64 : _rTrigger = 3'd2 & ({3{wValid}});
`FMT_RXENG64_CPL : _rTrigger = 3'd3 & ({3{wValid}});
`FMT_RXENG64_CPLD : _rTrigger = 3'd4 & ({3{wValid}});
default : _rTrigger = 3'd5 & ({3{wValid}});
endcase
end
// Handle receiving memory reads and writes.
always @ (posedge CLK) begin
rReqState <= #1 (RST ? `S_RXENG64_REQ_PARSE : _rReqState);
rReqWen <= #1 (RST ? 1'd0 : _rReqWen);
rRNW <= #1 _rRNW;
rTC <= #1 _rTC;
rTD <= #1 _rTD;
rEP <= #1 _rEP;
rAttr <= #1 _rAttr;
rReqLen <= #1 _rReqLen;
rReqId <= #1 _rReqId;
rReqTag <= #1 _rReqTag;
rBE <= #1 _rBE;
r3DWHeader <= #1 _r3DWHeader;
rReqData <= #1 _rReqData;
rReqAddr <= #1 _rReqAddr;
rQWAReq <= #1 _rQWAReq;
end
always @ (*) begin
_rReqState = rReqState;
_rTC = rTC;
_rTD = rTD;
_rEP = rEP;
_rAttr = rAttr;
_rReqLen = rReqLen;
_rReqId = rReqId;
_rReqTag = rReqTag;
_rBE = rBE;
_r3DWHeader = r3DWHeader;
_rReqData = rReqData;
_rReqAddr = rReqAddr;
_rReqWen = rReqWen;
_rRNW = rRNW;
_rQWAReq = rQWAReq;
case (rReqState)
`S_RXENG64_REQ_PARSE : begin // Process DW0, DW1
_rTC = rDataIn[22:20];
_rTD = rDataIn[15];
_rEP = rDataIn[14];
_rAttr = rDataIn[13:12];
_rReqLen = rDataIn[9:0];
_rReqId = rDataIn[63:48];
_rReqTag = rDataIn[47:40];
_rBE = rDataIn[35:32];
_r3DWHeader = !rDataIn[29];
_rReqWen = 0;
// Trigger only set if the packet is valid
case (rTrigger)
3'd0 : _rReqState = rReqState;
3'd1 : _rReqState = (rLenOneIn ? `S_RXENG64_REQ_MEM_RD_0 : `S_RXENG64_REQ_UNHANDLED);
3'd2 : _rReqState = (rLenOneIn ? `S_RXENG64_REQ_MEM_WR_0 : `S_RXENG64_REQ_UNHANDLED);
default : _rReqState = `S_RXENG64_REQ_UNHANDLED;
endcase
end
`S_RXENG64_REQ_UNHANDLED : begin
if (rValidIn & rLastIn)
_rReqState = `S_RXENG64_REQ_PARSE;
end
`S_RXENG64_REQ_MEM_RD_0 : begin
_rReqAddr = (r3DWHeader ? rDataIn[31:2] : rDataIn[63:34]);
_rRNW = 1;
_rReqWen = (rValidIn & rLastIn);
if (rValidIn)
_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_UNHANDLED);
end
`S_RXENG64_REQ_MEM_WR_0 : begin
_rReqData = rDataIn[63:32];
_rReqAddr = (r3DWHeader ? rDataIn[31:2] : rDataIn[63:34]);
_rQWAReq = (~rDataIn[2] & r3DWHeader) | (~r3DWHeader & ~rDataIn[34]);
_rRNW = 0;
_rReqWen = (rValidIn & rLastIn);
if (rValidIn) begin
_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_MEM_WR_1);
end
end
`S_RXENG64_REQ_MEM_WR_1 : begin
_rReqData = rDataIn >> ({5'd0,~(rQWAReq | (~wALTERA))} << 5);
_rReqWen = (rValidIn & rLastIn);
if (rValidIn)
_rReqState = (rLastIn ? `S_RXENG64_REQ_PARSE : `S_RXENG64_REQ_UNHANDLED);
end
default : begin
_rReqState = `S_RXENG64_REQ_PARSE;
end
endcase
end
// When signaled, start processing the packet, handle cpls and cplds.
always @ (posedge CLK) begin
rCplState <= #1 (RST ? `S_RXENG64_CPL_PARSE : _rCplState);
rDataOutEn <= #1 (RST ? 2'd0 : _rDataOutEn);
rDataOutCount <= #1 (RST ? 2'd0 : _rDataOutCount);
rDataDone <= #1 (RST ? 1'd0 : _rDataDone);
rDataErr <= #1 (RST ? 1'd0 : _rDataErr);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rCplErr <= #1 _rCplErr;
rLastCPLD <= #1 _rLastCPLD;
rDataOut <= #1 _rDataOut;
rChnlShft <= #1 _rChnlShft;
end
always @ (*) begin
_rCplState = rCplState;
_rCplErr = rCplErr;
_rLastCPLD = rLastCPLD;
_rDataOut = rDataOut;
_rDataOutEn = rDataOutEn;
_rDataOutCount = rDataOutCount;
_rDataDone = rDataDone;
_rDataErr = rDataErr;
_rDataValid = rDataValid;
_rChnlShft = rChnlShft;
case (rCplState)
`S_RXENG64_CPL_PARSE : begin // Process DW0, DW1
_rDataOutEn = 0;
_rDataOutCount = 0;
_rDataDone = 0;
_rDataErr = 0;
_rDataValid = 0;
_rCplErr = (rDataIn[47:45] != 3'b000); // Completion status code
_rLastCPLD = (rDataIn[43:32] == (rDataIn[9:0]<<2)); // byte_count == length ?
// Trigger only set if the packet is valid
case (rTrigger)
3'd0 : _rCplState = rCplState;
3'd3 : _rCplState = `S_RXENG64_CPL_NO_DATA;
3'd4 : _rCplState = `S_RXENG64_CPL_DATA;
default : _rCplState = `S_RXENG64_CPL_WAIT_FOR_END;
endcase
end
`S_RXENG64_CPL_WAIT_FOR_END : begin // Wait until the end of the TLP
_rDataOutEn = 0;
_rDataOutCount = 0;
_rDataDone = 0;
_rDataErr = 0;
_rDataValid = 0;
if (rValidIn & rLastIn)
_rCplState = `S_RXENG64_CPL_PARSE;
end
`S_RXENG64_CPL_NO_DATA : begin // Process DW2
_rChnlShft = rDataIn[15:8]; // Tag is [15:8]
_rDataValid = rValidIn;
if (rValidIn) begin
_rDataOutEn = 0;
_rDataOutCount = 0;
_rDataErr = rCplErr;
_rDataDone = 1;
_rCplState = (rLastIn ? `S_RXENG64_CPL_PARSE : `S_RXENG64_CPL_WAIT_FOR_END);
end
end
`S_RXENG64_CPL_DATA : begin // Process DW2, DW3
_rChnlShft = rDataIn[15:8]; // Tag is [15:8]
_rDataValid = rValidIn;
_rDataOut = (rDataIn>>32);
if (rValidIn) begin
_rDataOutEn = rKeepBothIn & (~rQWACpl | ~wALTERA);
_rDataOutCount = rKeepBothIn & (~rQWACpl | ~wALTERA);
_rDataDone = (rCplErr | (rLastIn & rLastCPLD));
_rDataErr = rCplErr;
if (rLastIn) // Ends in this packet
_rCplState = `S_RXENG64_CPL_PARSE;
else if (rCplErr) // Bad completion code
_rCplState = `S_RXENG64_CPL_WAIT_FOR_END;
else // Continues past this packet, send 1 DW now
_rCplState = `S_RXENG64_CPL_DATA_CONT;
end
end
`S_RXENG64_CPL_DATA_CONT : begin // Process packet until end
_rDataValid = rValidIn;
_rDataOut = rDataIn;
if (rValidIn) begin // Process and write until last packet
_rDataOutEn = {(!rLastIn | rKeepBothIn), 1'b1};
_rDataOutCount = (2'd1<<(!rLastIn | rKeepBothIn));
_rDataDone = (rLastIn & rLastCPLD);
_rDataErr = 0;
_rCplState = (rLastIn ? `S_RXENG64_CPL_PARSE : `S_RXENG64_CPL_DATA_CONT);
end
end
endcase
end
endmodule |
module pcie_pipe_v6 #
(
parameter NO_OF_LANES = 8,
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k_o ,
output wire [15:0] pipe_rx0_data_o ,
output wire pipe_rx0_valid_o ,
output wire pipe_rx0_chanisaligned_o ,
output wire [ 2:0] pipe_rx0_status_o ,
output wire pipe_rx0_phy_status_o ,
output wire pipe_rx0_elec_idle_o ,
input wire pipe_rx0_polarity_i ,
input wire pipe_tx0_compliance_i ,
input wire [ 1:0] pipe_tx0_char_is_k_i ,
input wire [15:0] pipe_tx0_data_i ,
input wire pipe_tx0_elec_idle_i ,
input wire [ 1:0] pipe_tx0_powerdown_i ,
input wire [ 1:0] pipe_rx0_char_is_k_i ,
input wire [15:0] pipe_rx0_data_i ,
input wire pipe_rx0_valid_i ,
input wire pipe_rx0_chanisaligned_i ,
input wire [ 2:0] pipe_rx0_status_i ,
input wire pipe_rx0_phy_status_i ,
input wire pipe_rx0_elec_idle_i ,
output wire pipe_rx0_polarity_o ,
output wire pipe_tx0_compliance_o ,
output wire [ 1:0] pipe_tx0_char_is_k_o ,
output wire [15:0] pipe_tx0_data_o ,
output wire pipe_tx0_elec_idle_o ,
output wire [ 1:0] pipe_tx0_powerdown_o ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k_o ,
output wire [15:0] pipe_rx1_data_o ,
output wire pipe_rx1_valid_o ,
output wire pipe_rx1_chanisaligned_o ,
output wire [ 2:0] pipe_rx1_status_o ,
output wire pipe_rx1_phy_status_o ,
output wire pipe_rx1_elec_idle_o ,
input wire pipe_rx1_polarity_i ,
input wire pipe_tx1_compliance_i ,
input wire [ 1:0] pipe_tx1_char_is_k_i ,
input wire [15:0] pipe_tx1_data_i ,
input wire pipe_tx1_elec_idle_i ,
input wire [ 1:0] pipe_tx1_powerdown_i ,
input wire [ 1:0] pipe_rx1_char_is_k_i ,
input wire [15:0] pipe_rx1_data_i ,
input wire pipe_rx1_valid_i ,
input wire pipe_rx1_chanisaligned_i ,
input wire [ 2:0] pipe_rx1_status_i ,
input wire pipe_rx1_phy_status_i ,
input wire pipe_rx1_elec_idle_i ,
output wire pipe_rx1_polarity_o ,
output wire pipe_tx1_compliance_o ,
output wire [ 1:0] pipe_tx1_char_is_k_o ,
output wire [15:0] pipe_tx1_data_o ,
output wire pipe_tx1_elec_idle_o ,
output wire [ 1:0] pipe_tx1_powerdown_o ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k_o ,
output wire [15:0] pipe_rx2_data_o ,
output wire pipe_rx2_valid_o ,
output wire pipe_rx2_chanisaligned_o ,
output wire [ 2:0] pipe_rx2_status_o ,
output wire pipe_rx2_phy_status_o ,
output wire pipe_rx2_elec_idle_o ,
input wire pipe_rx2_polarity_i ,
input wire pipe_tx2_compliance_i ,
input wire [ 1:0] pipe_tx2_char_is_k_i ,
input wire [15:0] pipe_tx2_data_i ,
input wire pipe_tx2_elec_idle_i ,
input wire [ 1:0] pipe_tx2_powerdown_i ,
input wire [ 1:0] pipe_rx2_char_is_k_i ,
input wire [15:0] pipe_rx2_data_i ,
input wire pipe_rx2_valid_i ,
input wire pipe_rx2_chanisaligned_i ,
input wire [ 2:0] pipe_rx2_status_i ,
input wire pipe_rx2_phy_status_i ,
input wire pipe_rx2_elec_idle_i ,
output wire pipe_rx2_polarity_o ,
output wire pipe_tx2_compliance_o ,
output wire [ 1:0] pipe_tx2_char_is_k_o ,
output wire [15:0] pipe_tx2_data_o ,
output wire pipe_tx2_elec_idle_o ,
output wire [ 1:0] pipe_tx2_powerdown_o ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k_o ,
output wire [15:0] pipe_rx3_data_o ,
output wire pipe_rx3_valid_o ,
output wire pipe_rx3_chanisaligned_o ,
output wire [ 2:0] pipe_rx3_status_o ,
output wire pipe_rx3_phy_status_o ,
output wire pipe_rx3_elec_idle_o ,
input wire pipe_rx3_polarity_i ,
input wire pipe_tx3_compliance_i ,
input wire [ 1:0] pipe_tx3_char_is_k_i ,
input wire [15:0] pipe_tx3_data_i ,
input wire pipe_tx3_elec_idle_i ,
input wire [ 1:0] pipe_tx3_powerdown_i ,
input wire [ 1:0] pipe_rx3_char_is_k_i ,
input wire [15:0] pipe_rx3_data_i ,
input wire pipe_rx3_valid_i ,
input wire pipe_rx3_chanisaligned_i ,
input wire [ 2:0] pipe_rx3_status_i ,
input wire pipe_rx3_phy_status_i ,
input wire pipe_rx3_elec_idle_i ,
output wire pipe_rx3_polarity_o ,
output wire pipe_tx3_compliance_o ,
output wire [ 1:0] pipe_tx3_char_is_k_o ,
output wire [15:0] pipe_tx3_data_o ,
output wire pipe_tx3_elec_idle_o ,
output wire [ 1:0] pipe_tx3_powerdown_o ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k_o ,
output wire [15:0] pipe_rx4_data_o ,
output wire pipe_rx4_valid_o ,
output wire pipe_rx4_chanisaligned_o ,
output wire [ 2:0] pipe_rx4_status_o ,
output wire pipe_rx4_phy_status_o ,
output wire pipe_rx4_elec_idle_o ,
input wire pipe_rx4_polarity_i ,
input wire pipe_tx4_compliance_i ,
input wire [ 1:0] pipe_tx4_char_is_k_i ,
input wire [15:0] pipe_tx4_data_i ,
input wire pipe_tx4_elec_idle_i ,
input wire [ 1:0] pipe_tx4_powerdown_i ,
input wire [ 1:0] pipe_rx4_char_is_k_i ,
input wire [15:0] pipe_rx4_data_i ,
input wire pipe_rx4_valid_i ,
input wire pipe_rx4_chanisaligned_i ,
input wire [ 2:0] pipe_rx4_status_i ,
input wire pipe_rx4_phy_status_i ,
input wire pipe_rx4_elec_idle_i ,
output wire pipe_rx4_polarity_o ,
output wire pipe_tx4_compliance_o ,
output wire [ 1:0] pipe_tx4_char_is_k_o ,
output wire [15:0] pipe_tx4_data_o ,
output wire pipe_tx4_elec_idle_o ,
output wire [ 1:0] pipe_tx4_powerdown_o ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k_o ,
output wire [15:0] pipe_rx5_data_o ,
output wire pipe_rx5_valid_o ,
output wire pipe_rx5_chanisaligned_o ,
output wire [ 2:0] pipe_rx5_status_o ,
output wire pipe_rx5_phy_status_o ,
output wire pipe_rx5_elec_idle_o ,
input wire pipe_rx5_polarity_i ,
input wire pipe_tx5_compliance_i ,
input wire [ 1:0] pipe_tx5_char_is_k_i ,
input wire [15:0] pipe_tx5_data_i ,
input wire pipe_tx5_elec_idle_i ,
input wire [ 1:0] pipe_tx5_powerdown_i ,
input wire [ 1:0] pipe_rx5_char_is_k_i ,
input wire [15:0] pipe_rx5_data_i ,
input wire pipe_rx5_valid_i ,
input wire pipe_rx5_chanisaligned_i ,
input wire [ 2:0] pipe_rx5_status_i ,
input wire pipe_rx5_phy_status_i ,
input wire pipe_rx5_elec_idle_i ,
output wire pipe_rx5_polarity_o ,
output wire pipe_tx5_compliance_o ,
output wire [ 1:0] pipe_tx5_char_is_k_o ,
output wire [15:0] pipe_tx5_data_o ,
output wire pipe_tx5_elec_idle_o ,
output wire [ 1:0] pipe_tx5_powerdown_o ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k_o ,
output wire [15:0] pipe_rx6_data_o ,
output wire pipe_rx6_valid_o ,
output wire pipe_rx6_chanisaligned_o ,
output wire [ 2:0] pipe_rx6_status_o ,
output wire pipe_rx6_phy_status_o ,
output wire pipe_rx6_elec_idle_o ,
input wire pipe_rx6_polarity_i ,
input wire pipe_tx6_compliance_i ,
input wire [ 1:0] pipe_tx6_char_is_k_i ,
input wire [15:0] pipe_tx6_data_i ,
input wire pipe_tx6_elec_idle_i ,
input wire [ 1:0] pipe_tx6_powerdown_i ,
input wire [ 1:0] pipe_rx6_char_is_k_i ,
input wire [15:0] pipe_rx6_data_i ,
input wire pipe_rx6_valid_i ,
input wire pipe_rx6_chanisaligned_i ,
input wire [ 2:0] pipe_rx6_status_i ,
input wire pipe_rx6_phy_status_i ,
input wire pipe_rx6_elec_idle_i ,
output wire pipe_rx6_polarity_o ,
output wire pipe_tx6_compliance_o ,
output wire [ 1:0] pipe_tx6_char_is_k_o ,
output wire [15:0] pipe_tx6_data_o ,
output wire pipe_tx6_elec_idle_o ,
output wire [ 1:0] pipe_tx6_powerdown_o ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k_o ,
output wire [15:0] pipe_rx7_data_o ,
output wire pipe_rx7_valid_o ,
output wire pipe_rx7_chanisaligned_o ,
output wire [ 2:0] pipe_rx7_status_o ,
output wire pipe_rx7_phy_status_o ,
output wire pipe_rx7_elec_idle_o ,
input wire pipe_rx7_polarity_i ,
input wire pipe_tx7_compliance_i ,
input wire [ 1:0] pipe_tx7_char_is_k_i ,
input wire [15:0] pipe_tx7_data_i ,
input wire pipe_tx7_elec_idle_i ,
input wire [ 1:0] pipe_tx7_powerdown_i ,
input wire [ 1:0] pipe_rx7_char_is_k_i ,
input wire [15:0] pipe_rx7_data_i ,
input wire pipe_rx7_valid_i ,
input wire pipe_rx7_chanisaligned_i ,
input wire [ 2:0] pipe_rx7_status_i ,
input wire pipe_rx7_phy_status_i ,
input wire pipe_rx7_elec_idle_i ,
output wire pipe_rx7_polarity_o ,
output wire pipe_tx7_compliance_o ,
output wire [ 1:0] pipe_tx7_char_is_k_o ,
output wire [15:0] pipe_tx7_data_o ,
output wire pipe_tx7_elec_idle_o ,
output wire [ 1:0] pipe_tx7_powerdown_o ,
// Non PIPE signals
input wire [ 5:0] pl_ltssm_state ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
localparam Tc2o = 1; // clock to out delay model
wire [ 1:0] pipe_rx0_char_is_k_q ;
wire [15:0] pipe_rx0_data_q ;
wire [ 1:0] pipe_rx1_char_is_k_q ;
wire [15:0] pipe_rx1_data_q ;
wire [ 1:0] pipe_rx2_char_is_k_q ;
wire [15:0] pipe_rx2_data_q ;
wire [ 1:0] pipe_rx3_char_is_k_q ;
wire [15:0] pipe_rx3_data_q ;
wire [ 1:0] pipe_rx4_char_is_k_q ;
wire [15:0] pipe_rx4_data_q ;
wire [ 1:0] pipe_rx5_char_is_k_q ;
wire [15:0] pipe_rx5_data_q ;
wire [ 1:0] pipe_rx6_char_is_k_q ;
wire [15:0] pipe_rx6_data_q ;
wire [ 1:0] pipe_rx7_char_is_k_q ;
wire [15:0] pipe_rx7_data_q ;
//synthesis translate_off
// initial begin
// $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
// end
//synthesis translate_on
generate
pcie_pipe_misc_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_misc_i (
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
.pipe_tx_reset_i(pipe_tx_reset_i),
.pipe_tx_rate_i(pipe_tx_rate_i),
.pipe_tx_deemph_i(pipe_tx_deemph_i),
.pipe_tx_margin_i(pipe_tx_margin_i),
.pipe_tx_swing_i(pipe_tx_swing_i),
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
.pipe_tx_reset_o(pipe_tx_reset_o),
.pipe_tx_rate_o(pipe_tx_rate_o),
.pipe_tx_deemph_o(pipe_tx_deemph_o),
.pipe_tx_margin_o(pipe_tx_margin_o),
.pipe_tx_swing_o(pipe_tx_swing_o) ,
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_0_i (
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),
.pipe_rx_data_o(pipe_rx0_data_q),
.pipe_rx_valid_o(pipe_rx0_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
.pipe_rx_status_o(pipe_rx0_status_o),
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
.pipe_tx_data_i(pipe_tx0_data_i),
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
.pipe_rx_data_i(pipe_rx0_data_i),
.pipe_rx_valid_i(pipe_rx0_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
.pipe_rx_status_i(pipe_rx0_status_i),
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
.pipe_tx_data_o(pipe_tx0_data_o),
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
if (NO_OF_LANES >= 2) begin
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_1_i (
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),
.pipe_rx_data_o(pipe_rx1_data_q),
.pipe_rx_valid_o(pipe_rx1_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
.pipe_rx_status_o(pipe_rx1_status_o),
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
.pipe_tx_data_i(pipe_tx1_data_i),
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
.pipe_rx_data_i(pipe_rx1_data_i),
.pipe_rx_valid_i(pipe_rx1_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
.pipe_rx_status_i(pipe_rx1_status_i),
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
.pipe_tx_data_o(pipe_tx1_data_o),
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end
else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx1_char_is_k_o = 2'b00;
assign pipe_rx1_data_o = 16'h0000;
assign pipe_rx1_valid_o = 1'b0;
assign pipe_rx1_chanisaligned_o = 1'b0;
assign pipe_rx1_status_o = 3'b000;
assign pipe_rx1_phy_status_o = 1'b0;
assign pipe_rx1_elec_idle_o = 1'b1;
assign pipe_rx1_polarity_o = 1'b0;
assign pipe_tx1_compliance_o = 1'b0;
assign pipe_tx1_char_is_k_o = 2'b00;
assign pipe_tx1_data_o = 16'h0000;
assign pipe_tx1_elec_idle_o = 1'b1;
assign pipe_tx1_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end
if (NO_OF_LANES >= 4) begin
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_2_i (
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),
.pipe_rx_data_o(pipe_rx2_data_q),
.pipe_rx_valid_o(pipe_rx2_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
.pipe_rx_status_o(pipe_rx2_status_o),
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
.pipe_tx_data_i(pipe_tx2_data_i),
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
.pipe_rx_data_i(pipe_rx2_data_i),
.pipe_rx_valid_i(pipe_rx2_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
.pipe_rx_status_i(pipe_rx2_status_i),
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
.pipe_tx_data_o(pipe_tx2_data_o),
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_3_i (
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),
.pipe_rx_data_o(pipe_rx3_data_q),
.pipe_rx_valid_o(pipe_rx3_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
.pipe_rx_status_o(pipe_rx3_status_o),
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
.pipe_tx_data_i(pipe_tx3_data_i),
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
.pipe_rx_data_i(pipe_rx3_data_i),
.pipe_rx_valid_i(pipe_rx3_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
.pipe_rx_status_i(pipe_rx3_status_i),
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
.pipe_tx_data_o(pipe_tx3_data_o),
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end
else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx2_char_is_k_o = 2'b00;
assign pipe_rx2_data_o = 16'h0000;
assign pipe_rx2_valid_o = 1'b0;
assign pipe_rx2_chanisaligned_o = 1'b0;
assign pipe_rx2_status_o = 3'b000;
assign pipe_rx2_phy_status_o = 1'b0;
assign pipe_rx2_elec_idle_o = 1'b1;
assign pipe_rx2_polarity_o = 1'b0;
assign pipe_tx2_compliance_o = 1'b0;
assign pipe_tx2_char_is_k_o = 2'b00;
assign pipe_tx2_data_o = 16'h0000;
assign pipe_tx2_elec_idle_o = 1'b1;
assign pipe_tx2_powerdown_o = 2'b00;
assign pipe_rx3_char_is_k_o = 2'b00;
assign pipe_rx3_data_o = 16'h0000;
assign pipe_rx3_valid_o = 1'b0;
assign pipe_rx3_chanisaligned_o = 1'b0;
assign pipe_rx3_status_o = 3'b000;
assign pipe_rx3_phy_status_o = 1'b0;
assign pipe_rx3_elec_idle_o = 1'b1;
assign pipe_rx3_polarity_o = 1'b0;
assign pipe_tx3_compliance_o = 1'b0;
assign pipe_tx3_char_is_k_o = 2'b00;
assign pipe_tx3_data_o = 16'h0000;
assign pipe_tx3_elec_idle_o = 1'b1;
assign pipe_tx3_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end
if (NO_OF_LANES >= 8) begin
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_4_i (
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),
.pipe_rx_data_o(pipe_rx4_data_q),
.pipe_rx_valid_o(pipe_rx4_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
.pipe_rx_status_o(pipe_rx4_status_o),
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
.pipe_tx_data_i(pipe_tx4_data_i),
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
.pipe_rx_data_i(pipe_rx4_data_i),
.pipe_rx_valid_i(pipe_rx4_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
.pipe_rx_status_i(pipe_rx4_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
.pipe_tx_data_o(pipe_tx4_data_o),
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_5_i (
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),
.pipe_rx_data_o(pipe_rx5_data_q),
.pipe_rx_valid_o(pipe_rx5_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
.pipe_rx_status_o(pipe_rx5_status_o),
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
.pipe_tx_data_i(pipe_tx5_data_i),
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
.pipe_rx_data_i(pipe_rx5_data_i),
.pipe_rx_valid_i(pipe_rx5_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
.pipe_rx_status_i(pipe_rx5_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
.pipe_tx_data_o(pipe_tx5_data_o),
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_6_i (
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),
.pipe_rx_data_o(pipe_rx6_data_q),
.pipe_rx_valid_o(pipe_rx6_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
.pipe_rx_status_o(pipe_rx6_status_o),
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
.pipe_tx_data_i(pipe_tx6_data_i),
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
.pipe_rx_data_i(pipe_rx6_data_i),
.pipe_rx_valid_i(pipe_rx6_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
.pipe_rx_status_i(pipe_rx6_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
.pipe_tx_data_o(pipe_tx6_data_o),
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
pcie_pipe_lane_v6 # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_7_i (
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),
.pipe_rx_data_o(pipe_rx7_data_q),
.pipe_rx_valid_o(pipe_rx7_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
.pipe_rx_status_o(pipe_rx7_status_o),
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
.pipe_tx_data_i(pipe_tx7_data_i),
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
.pipe_rx_data_i(pipe_rx7_data_i),
.pipe_rx_valid_i(pipe_rx7_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
.pipe_rx_status_i(pipe_rx7_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
.pipe_tx_data_o(pipe_tx7_data_o),
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end
else begin
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx4_char_is_k_o = 2'b00;
assign pipe_rx4_data_o = 16'h0000;
assign pipe_rx4_valid_o = 1'b0;
assign pipe_rx4_chanisaligned_o = 1'b0;
assign pipe_rx4_status_o = 3'b000;
assign pipe_rx4_phy_status_o = 1'b0;
assign pipe_rx4_elec_idle_o = 1'b1;
assign pipe_rx4_polarity_o = 1'b0;
assign pipe_tx4_compliance_o = 1'b0;
assign pipe_tx4_char_is_k_o = 2'b00;
assign pipe_tx4_data_o = 16'h0000;
assign pipe_tx4_elec_idle_o = 1'b1;
assign pipe_tx4_powerdown_o = 2'b00;
assign pipe_rx5_char_is_k_o = 2'b00;
assign pipe_rx5_data_o = 16'h0000;
assign pipe_rx5_valid_o = 1'b0;
assign pipe_rx5_chanisaligned_o = 1'b0;
assign pipe_rx5_status_o = 3'b000;
assign pipe_rx5_phy_status_o = 1'b0;
assign pipe_rx5_elec_idle_o = 1'b1;
assign pipe_rx5_polarity_o = 1'b0;
assign pipe_tx5_compliance_o = 1'b0;
assign pipe_tx5_char_is_k_o = 2'b00;
assign pipe_tx5_data_o = 16'h0000;
assign pipe_tx5_elec_idle_o = 1'b1;
assign pipe_tx5_powerdown_o = 2'b00;
assign pipe_rx6_char_is_k_o = 2'b00;
assign pipe_rx6_data_o = 16'h0000;
assign pipe_rx6_valid_o = 1'b0;
assign pipe_rx6_chanisaligned_o = 1'b0;
assign pipe_rx6_status_o = 3'b000;
assign pipe_rx6_phy_status_o = 1'b0;
assign pipe_rx6_elec_idle_o = 1'b1;
assign pipe_rx6_polarity_o = 1'b0;
assign pipe_tx6_compliance_o = 1'b0;
assign pipe_tx6_char_is_k_o = 2'b00;
assign pipe_tx6_data_o = 16'h0000;
assign pipe_tx6_elec_idle_o = 1'b1;
assign pipe_tx6_powerdown_o = 2'b00;
assign pipe_rx7_char_is_k_o = 2'b00;
assign pipe_rx7_data_o = 16'h0000;
assign pipe_rx7_valid_o = 1'b0;
assign pipe_rx7_chanisaligned_o = 1'b0;
assign pipe_rx7_status_o = 3'b000;
assign pipe_rx7_phy_status_o = 1'b0;
assign pipe_rx7_elec_idle_o = 1'b1;
assign pipe_rx7_polarity_o = 1'b0;
assign pipe_tx7_compliance_o = 1'b0;
assign pipe_tx7_char_is_k_o = 2'b00;
assign pipe_tx7_data_o = 16'h0000;
assign pipe_tx7_elec_idle_o = 1'b1;
assign pipe_tx7_powerdown_o = 2'b00;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
end
endgenerate
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
assign pipe_rx0_data_o = pipe_rx0_data_q;
assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
assign pipe_rx1_data_o = pipe_rx1_data_q;
assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
assign pipe_rx2_data_o = pipe_rx2_data_q;
assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
assign pipe_rx3_data_o = pipe_rx3_data_q;
assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
assign pipe_rx4_data_o = pipe_rx4_data_q;
assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
assign pipe_rx5_data_o = pipe_rx5_data_q;
assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
assign pipe_rx6_data_o = pipe_rx6_data_q;
assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
assign pipe_rx7_data_o = pipe_rx7_data_q;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
endmodule |
module pcie_app_v6 #(
parameter DQ_WIDTH = 64,
parameter C_DATA_WIDTH = 9'd64,
parameter KEEP_WIDTH = (C_DATA_WIDTH/8),
parameter C_NUM_CHNL = 4'd1, // Number of RIFFA channels (set as needed: 1-12)
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes). Setting this higher than PCIe Endpoint's MAX READ value just wastes resources
parameter C_TAG_WIDTH = 5 // Number of outstanding tag requests
)
(
input user_clk,
input user_reset,
input user_lnk_up,
// Tx
input [5:0] tx_buf_av,
input tx_cfg_req,
input tx_err_drop,
output tx_cfg_gnt,
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
// Rx
output rx_np_ok,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
// CFG
input [31:0] cfg_do,
input cfg_rd_wr_done,
output [31:0] cfg_di,
output [3:0] cfg_byte_en,
output [9:0] cfg_dwaddr,
output cfg_wr_en,
output cfg_rd_en,
output cfg_err_cor,
output cfg_err_ur,
output cfg_err_ecrc,
output cfg_err_cpl_timeout,
output cfg_err_cpl_abort,
output cfg_err_cpl_unexpect,
output cfg_err_posted,
output cfg_err_locked,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok,
input cfg_to_turnoff,
output cfg_trn_pending,
output cfg_pm_wake,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_link_width,
input pl_sel_link_rate,
input pl_link_gen2_capable,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_capable,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [63:0] cfg_dsn,
input app_clk,
output app_en,
input app_ack,
output[31:0] app_instr,
//Data read back Interface
input rdback_fifo_empty,
output rdback_fifo_rden,
input[DQ_WIDTH*4 - 1:0] rdback_data
);
////////////////////////////////////
// START RIFFA CODE (do not edit)
////////////////////////////////////
// Core input tie-offs
assign fc_sel = 3'b001; // Always read receive credit limits
assign rx_np_ok = 1'b1; // Allow Reception of Non-posted Traffic
assign s_axis_tx_tuser[0] = 1'b0; // Unused for V7
assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet
assign s_axis_tx_tuser[2] = 1'b1; // We support stream packet (cut-through mode)
assign tx_cfg_gnt = 1'b1; // Always allow to transmit internally generated TLPs
assign cfg_err_cor = 1'b0; // Never report Correctable Error
assign cfg_err_ur = 1'b0; // Never report UR
assign cfg_err_ecrc = 1'b0; // Never report ECRC Error
assign cfg_err_cpl_timeout = 1'b0; // Never report Completion Timeout
assign cfg_err_cpl_abort = 1'b0; // Never report Completion Abort
assign cfg_err_cpl_unexpect = 1'b0; // Never report unexpected completion
assign cfg_err_posted = 1'b0; // Not sending back CPLs for app level errors
assign cfg_err_locked = 1'b0; // Never qualify cfg_err_ur or cfg_err_cpl_abort
assign cfg_err_tlp_cpl_header = 48'h0; // Not sending back CLPs for app level errors
assign cfg_trn_pending = 1'b0; // Not trying to recover from missing request data...
assign cfg_err_atomic_egress_blocked = 1'b0; // Never report Atomic TLP blocked
assign cfg_err_internal_cor = 1'b0; // Never report internal error occurred
assign cfg_err_malformed = 1'b0; // Never report malformed error
assign cfg_err_mc_blocked = 1'b0; // Never report multi-cast TLP blocked
assign cfg_err_poisoned = 1'b0; // Never report poisoned TLP received
assign cfg_err_norecovery = 1'b0; // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout
assign cfg_err_acs = 1'b0; // Never report an ACS violation
assign cfg_err_internal_uncor = 1'b0; // Never report internal uncorrectable error
assign cfg_pm_halt_aspm_l0s = 1'b0; // Allow entry into L0s
assign cfg_pm_halt_aspm_l1 = 1'b0; // Allow entry into L1
assign cfg_pm_force_state_en = 1'b0; // Do not qualify cfg_pm_force_state
assign cfg_pm_force_state = 2'b00; // Do not move force core into specific PM state
assign cfg_err_aer_headerlog = 128'h0; // Zero out the AER Header Log
assign cfg_aer_interrupt_msgnum = 5'b00000; // Zero out the AER Root Error Status Register
assign cfg_pciecap_interrupt_msgnum = 5'b00000; // Zero out Interrupt Message Number
assign cfg_interrupt_di = 8'b0; // Not using multiple vector MSI interrupts (just single vector)
assign cfg_interrupt_assert = 1'b0; // Not using legacy interrupts
assign pl_directed_link_change = 2'b00; // Never initiate link change
assign pl_directed_link_width = 2'b00; // Zero out directed link width
assign pl_directed_link_speed = 1'b0; // Zero out directed link speed
assign pl_directed_link_auton = 1'b0; // Zero out link autonomous input
assign pl_upstream_prefer_deemph = 1'b1; // Zero out preferred de-emphasis of upstream port
assign cfg_dwaddr = 0; // Not allowing any config space reads/writes
assign cfg_rd_en = 0; // Not supporting config space reads
assign cfg_di = 0; // Not supporting config space writes
assign cfg_byte_en = 4'h0; // Not supporting config space writes
assign cfg_wr_en = 0; // Not supporting config space writes
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1}; // Assign the input DSN
assign cfg_pm_wake = 1'b0; // Not supporting PM_PME Message
assign cfg_turnoff_ok = 1'b0; // Currently don't support power down
// RIFFA channel interface
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
// Create a synchronous reset
wire user_lnk_up_int1;
wire user_reset_intl;
wire reset = (!user_lnk_up_int1 | user_reset_intl);
FDCP #(.INIT(1'b1)) user_lnk_up_n_int_i (
.Q (user_lnk_up_int1),
.D (user_lnk_up),
.C (user_clk),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(.INIT(1'b1)) user_reset_n_i (
.Q (user_reset_intl),
.D (user_reset),
.C (user_clk),
.CLR (1'b0),
.PRE (1'b0)
);
// RIFFA Endpoint
reg cfg_bus_mstr_enable;
reg [2:0] cfg_prg_max_payload_size;
reg [2:0] cfg_max_rd_req_size;
reg [5:0] cfg_link_width;
reg [1:0] cfg_link_rate;
reg [11:0] rc_cpld;
reg [7:0] rc_cplh;
reg rcb;
wire [15:0] cfg_completer_id = {cfg_bus_number, cfg_device_number, cfg_function_number};
wire [6:0] m_axis_rbar_hit = m_axis_rx_tuser[8:2];
wire [4:0] is_sof = m_axis_rx_tuser[14:10];
wire [4:0] is_eof = m_axis_rx_tuser[21:17];
wire rerr_fwd = m_axis_rx_tuser[1];
wire riffa_reset;
wire [C_DATA_WIDTH-1:0] bus_zero = {C_DATA_WIDTH{1'b0}};
always @(posedge user_clk) begin
cfg_bus_mstr_enable <= #1 cfg_command[2];
cfg_prg_max_payload_size <= #1 cfg_dcommand[7:5];
cfg_max_rd_req_size <= #1 cfg_dcommand[14:12];
cfg_link_width <= #1 cfg_lstatus[9:4];
cfg_link_rate <= #1 cfg_lstatus[1:0];
rc_cpld <= #1 fc_cpld;
rc_cplh <= #1 fc_cplh;
rcb <= #1 cfg_lcommand[3];
end
riffa_endpoint #(
.C_PCI_DATA_WIDTH(C_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_ALTERA(0)
) endpoint (
.CLK(user_clk),
.RST_IN(reset),
.RST_OUT(riffa_reset),
.M_AXIS_RX_TDATA(m_axis_rx_tdata),
.M_AXIS_RX_TKEEP(m_axis_rx_tkeep),
.M_AXIS_RX_TLAST(m_axis_rx_tlast),
.M_AXIS_RX_TVALID(m_axis_rx_tvalid),
.M_AXIS_RX_TREADY(m_axis_rx_tready),
.IS_SOF(is_sof),
.IS_EOF(is_eof),
.RERR_FWD(rerr_fwd),
.S_AXIS_TX_TDATA(s_axis_tx_tdata),
.S_AXIS_TX_TKEEP(s_axis_tx_tkeep),
.S_AXIS_TX_TLAST(s_axis_tx_tlast),
.S_AXIS_TX_TVALID(s_axis_tx_tvalid),
.S_AXIS_SRC_DSC(s_axis_tx_tuser[3]),
.S_AXIS_TX_TREADY(s_axis_tx_tready),
.COMPLETER_ID(cfg_completer_id),
.CFG_BUS_MSTR_ENABLE(cfg_bus_mstr_enable),
.CFG_LINK_WIDTH(cfg_link_width),
.CFG_LINK_RATE(cfg_link_rate),
.MAX_READ_REQUEST_SIZE(cfg_max_rd_req_size),
.MAX_PAYLOAD_SIZE(cfg_prg_max_payload_size),
.CFG_INTERRUPT_MSIEN(cfg_interrupt_msienable),
.CFG_INTERRUPT_RDY(cfg_interrupt_rdy),
.CFG_INTERRUPT(cfg_interrupt),
.RCB(rcb),
.MAX_RC_CPLD(rc_cpld),
.MAX_RC_CPLH(rc_cplh),
.RX_ST_DATA(bus_zero),
.RX_ST_EOP(1'd0),
.RX_ST_SOP(1'd0),
.RX_ST_VALID(1'd0),
.RX_ST_READY(),
.RX_ST_EMPTY(1'd0),
.TX_ST_DATA(),
.TX_ST_VALID(),
.TX_ST_READY(1'd0),
.TX_ST_EOP(),
.TX_ST_SOP(),
.TX_ST_EMPTY(),
.TL_CFG_CTL(32'd0),
.TL_CFG_ADD(4'd0),
.TL_CFG_STS(53'd0),
.APP_MSI_ACK(1'd0),
.APP_MSI_REQ(),
.CHNL_RX_CLK(chnl_rx_clk),
.CHNL_RX(chnl_rx),
.CHNL_RX_ACK(chnl_rx_ack),
.CHNL_RX_LAST(chnl_rx_last),
.CHNL_RX_LEN(chnl_rx_len),
.CHNL_RX_OFF(chnl_rx_off),
.CHNL_RX_DATA(chnl_rx_data),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid),
.CHNL_RX_DATA_REN(chnl_rx_data_ren),
.CHNL_TX_CLK(chnl_tx_clk),
.CHNL_TX(chnl_tx),
.CHNL_TX_ACK(chnl_tx_ack),
.CHNL_TX_LAST(chnl_tx_last),
.CHNL_TX_LEN(chnl_tx_len),
.CHNL_TX_OFF(chnl_tx_off),
.CHNL_TX_DATA(chnl_tx_data),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid),
.CHNL_TX_DATA_REN(chnl_tx_data_ren)
);
////////////////////////////////////
// END RIFFA CODE
////////////////////////////////////
////////////////////////////////////
// START USER CODE (do edit)
////////////////////////////////////
// Instantiate and assign modules to RIFFA channels.
// The example below connects C_NUM_CHNL instances of the same
// module to each RIFFA channel. Your design will likely not
// do the same. You should feel free to manually instantiate
// your custom IP cores here and remove the code below.
/*
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
chnl_tester #(C_DATA_WIDTH) module1 (
.CLK(user_clk),
.RST(riffa_reset), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[32*i +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*i +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_DATA_WIDTH*i +:C_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[32*i +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*i +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_DATA_WIDTH*i +:C_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate*/
softMC_pcie_app #(.C_PCI_DATA_WIDTH(C_DATA_WIDTH), .DQ_WIDTH(DQ_WIDTH)
) i_soft_pcie(
.clk(app_clk),
.rst(riffa_reset),
.CHNL_RX_CLK(chnl_rx_clk),
.CHNL_RX(chnl_rx),
.CHNL_RX_ACK(chnl_rx_ack),
.CHNL_RX_LAST(chnl_rx_last),
.CHNL_RX_LEN(chnl_rx_len[0 +:32]),
.CHNL_RX_OFF(chnl_rx_off[0 +:31]),
.CHNL_RX_DATA(chnl_rx_data[0 +:C_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid),
.CHNL_RX_DATA_REN(chnl_rx_data_ren),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk),
.CHNL_TX(chnl_tx),
.CHNL_TX_ACK(chnl_tx_ack),
.CHNL_TX_LAST(chnl_tx_last),
.CHNL_TX_LEN(chnl_tx_len[0 +:32]),
.CHNL_TX_OFF(chnl_tx_off[0 +:31]),
.CHNL_TX_DATA(chnl_tx_data[0 +:C_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid),
.CHNL_TX_DATA_REN(chnl_tx_data_ren),
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
//Data read back Interface
.rdback_fifo_empty(rdback_fifo_empty),
.rdback_fifo_rden(rdback_fifo_rden),
.rdback_data(rdback_data)
);
////////////////////////////////////
// END USER CODE
////////////////////////////////////
endmodule |
module tx_port_writer (
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
output TXN_ERR, // Write transaction encountered an error
input TXN_DONE_ACK, // Write transaction actual transfer length read
input NEW_TXN, // Transaction parameters are valid
output NEW_TXN_ACK, // Transaction parameter read, continue
input NEW_TXN_LAST, // Channel last write
input [31:0] NEW_TXN_LEN, // Channel write length (in 32 bit words)
input [30:0] NEW_TXN_OFF, // Channel write offset
input [31:0] NEW_TXN_WORDS_RECVD, // Count of data words received in transaction
input NEW_TXN_DONE, // Transaction is closed
input [63:0] SG_ELEM_ADDR, // Scatter gather element address
input [31:0] SG_ELEM_LEN, // Scatter gather element length (in words)
input SG_ELEM_RDY, // Scatter gather element ready
input SG_ELEM_EMPTY, // Scatter gather elements empty
output SG_ELEM_REN, // Scatter gather element read enable
output SG_RST, // Scatter gather data reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output TX_LAST, // Outgoing write is last request for transaction
input TX_SENT // Outgoing write complete
);
`include "common_functions.v"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rMainState=`S_TXPORTWR_MAIN_IDLE, _rMainState=`S_TXPORTWR_MAIN_IDLE;
reg [31:0] rOffLast=0, _rOffLast=0;
reg rWordsEQ0=0, _rWordsEQ0=0;
reg rStarted=0, _rStarted=0;
reg [31:0] rDoneLen=0, _rDoneLen=0;
reg rSgErr=0, _rSgErr=0;
reg rTxErrd=0, _rTxErrd=0;
reg rTxnAck=0, _rTxnAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rTxState=`S_TXPORTWR_TX_IDLE, _rTxState=`S_TXPORTWR_TX_IDLE;
reg [31:0] rSentWords=0, _rSentWords=0;
reg [31:0] rWords=0, _rWords=0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [31:0] rBufWordsInit=0, _rBufWordsInit=0;
reg rLargeBuf=0, _rLargeBuf=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [2:0] rCarry=0, _rCarry=0;
reg rValsPropagated=0, _rValsPropagated=0;
reg [5:0] rValsProp=0, _rValsProp=0;
reg rCopyBufWords=0, _rCopyBufWords=0;
reg rUseInit=0, _rUseInit=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg rPageSpillInit=0, _rPageSpillInit=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadSize=0, _rMaxPayloadSize=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg rMaxLen=1, _rMaxLen=1;
reg [9:0] rLen=0, _rLen=0;
reg [31:0] rSendingWords=0, _rSendingWords=0;
reg rAvail=0, _rAvail=0;
reg [1:0] rTxnDone=0, _rTxnDone=0;
reg [9:0] rLastLen=0, _rLastLen=0;
reg rLastLenEQ0=0, _rLastLenEQ0=0;
reg rLenEQWords=0, _rLenEQWords=0;
reg rLenEQBufWords=0, _rLenEQBufWords=0;
reg rNotRequesting=1, _rNotRequesting=1;
reg [63:0] rReqAddr=64'd0, _rReqAddr=64'd0;
reg [9:0] rReqLen=0, _rReqLen=0;
reg rReqLast=0, _rReqLast=0;
reg rTxReqAck=0, _rTxReqAck=0;
reg rDone=0, _rDone=0;
reg [9:0] rAckCount=0, _rAckCount=0;
reg rTxSent=0, _rTxSent=0;
reg rLastDoneRead=1, _rLastDoneRead=1;
reg rTxnDoneAck=0, _rTxnDoneAck=0;
reg rReqPartialDone=0, _rReqPartialDone=0;
reg rPartialDone=0, _rPartialDone=0;
assign NEW_TXN_ACK = rMainState[1]; // S_TXPORTWR_MAIN_CHECK
assign TXN = rMainState[2]; // S_TXPORTWR_MAIN_SIG_NEW
assign TXN_DONE = (rMainState[6] | rPartialDone); // S_TXPORTWR_MAIN_SIG_DONE
assign TXN_LEN = rWords;
assign TXN_OFF_LAST = rOffLast;
assign TXN_DONE_LEN = rDoneLen;
assign TXN_ERR = rTxErrd;
assign SG_ELEM_REN = rTxState[2]; // S_TXPORTWR_TX_ADJ_0
assign SG_RST = rMainState[3]; // S_TXPORTWR_MAIN_NEW_ACK
assign TX_REQ = !rNotRequesting;
assign TX_ADDR = rReqAddr;
assign TX_LEN = rReqLen;
assign TX_LAST = rReqLast;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxnAck <= #1 (RST ? 1'd0 : _rTxnAck);
rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);
rSgErr <= #1 (RST ? 1'd0 : _rSgErr);
rTxReqAck <= #1 (RST ? 1'd0 : _rTxReqAck);
rTxSent <= #1 (RST ? 1'd0 : _rTxSent);
end
always @ (*) begin
_rTxnAck = TXN_ACK;
_rTxnDoneAck = TXN_DONE_ACK;
_rSgErr = SG_ERR;
_rTxReqAck = TX_REQ_ACK;
_rTxSent = TX_SENT;
end
// Wait for a NEW_TXN request. Then request transfers until all the data is sent
// or until the specified length is reached. Then signal TXN_DONE.
always @ (posedge CLK) begin
rMainState <= #1 (RST ? `S_TXPORTWR_MAIN_IDLE : _rMainState);
rOffLast <= #1 _rOffLast;
rWordsEQ0 <= #1 _rWordsEQ0;
rStarted <= #1 _rStarted;
rDoneLen <= #1 (RST ? 0 : _rDoneLen);
rTxErrd <= #1 (RST ? 1'd0 : _rTxErrd);
end
always @ (*) begin
_rMainState = rMainState;
_rOffLast = rOffLast;
_rWordsEQ0 = rWordsEQ0;
_rStarted = rStarted;
_rDoneLen = rDoneLen;
_rTxErrd = rTxErrd;
case (rMainState)
`S_TXPORTWR_MAIN_IDLE: begin // Wait for channel write request
_rStarted = 0;
_rWordsEQ0 = (NEW_TXN_LEN == 0);
_rOffLast = {NEW_TXN_OFF, NEW_TXN_LAST};
if (NEW_TXN)
_rMainState = `S_TXPORTWR_MAIN_CHECK;
end
`S_TXPORTWR_MAIN_CHECK: begin // Continue with transaction?
if (rOffLast[0] | !rWordsEQ0)
_rMainState = `S_TXPORTWR_MAIN_SIG_NEW;
else
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_SIG_NEW: begin // Signal new write
_rMainState = `S_TXPORTWR_MAIN_NEW_ACK;
end
`S_TXPORTWR_MAIN_NEW_ACK: begin // Wait for acknowledgement
if (rTxnAck) // ACK'd on PC read of TXN length
_rMainState = (rWordsEQ0 ? `S_TXPORTWR_MAIN_SIG_DONE : `S_TXPORTWR_MAIN_WRITE);
end
`S_TXPORTWR_MAIN_WRITE: begin // Start writing and wait for all writes to complete
_rStarted = (rStarted | rTxState[1]); // S_TXPORTWR_TX_BUF
_rTxErrd = (rTxErrd | rSgErr);
if (rTxState[0] & rStarted) // S_TXPORTWR_TX_IDLE
_rMainState = `S_TXPORTWR_MAIN_DONE;
end
`S_TXPORTWR_MAIN_DONE: begin // Wait for the last transaction to complete
if (rDone & rLastDoneRead) begin
_rDoneLen = rSentWords;
_rMainState = `S_TXPORTWR_MAIN_SIG_DONE;
end
end
`S_TXPORTWR_MAIN_SIG_DONE: begin // Signal the done port
_rTxErrd = 0;
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_RESET: begin // Wait for the channel tx to drop
if (NEW_TXN_DONE)
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
default: begin
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
endcase
end
// Manage sending TX requests to the TX engine. Transfers will be limited
// by each scatter gather buffer's size, max payload size, and must not
// cross a (4KB) page boundary. The request is only made if there is sufficient
// data already written to the buffer.
wire [9:0] wLastLen = (NEW_TXN_WORDS_RECVD - rSentWords);
wire [9:0] wAddrLoInv = ~rAddr[11:2];
wire [10:0] wPageRem = (wAddrLoInv + 1'd1);
always @ (posedge CLK) begin
rTxState <= #1 (RST | rSgErr ? `S_TXPORTWR_TX_IDLE : _rTxState);
rSentWords <= #1 (rMainState[0] ? 0 : _rSentWords);
rWords <= #1 _rWords;
rBufWords <= #1 _rBufWords;
rBufWordsInit <= #1 _rBufWordsInit;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rValsPropagated <= #1 _rValsPropagated;
rValsProp <= #1 _rValsProp;
rLargeBuf <= #1 _rLargeBuf;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPageSpillInit <= #1 _rPageSpillInit;
rCopyBufWords <= #1 _rCopyBufWords;
rUseInit <= #1 _rUseInit;
rPreLen <= #1 _rPreLen;
rMaxPayloadSize <= #1 _rMaxPayloadSize;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rMaxLen <= #1 (RST ? 1'd1 : _rMaxLen);
rLen <= #1 _rLen;
rSendingWords <= #1 _rSendingWords;
rAvail <= #1 _rAvail;
rTxnDone <= #1 _rTxnDone;
rLastLen <= #1 _rLastLen;
rLastLenEQ0 <= #1 _rLastLenEQ0;
rLenEQWords <= #1 _rLenEQWords;
rLenEQBufWords <= #1 _rLenEQBufWords;
end
always @ (*) begin
_rTxState = rTxState;
_rCopyBufWords = rCopyBufWords;
_rUseInit = rUseInit;
_rValsProp = ((rValsProp<<1) | rTxState[3]); // S_TXPORTWR_TX_ADJ_1
_rValsPropagated = (rValsProp == 6'd0);
_rLargeBuf = (SG_ELEM_LEN > rWords);
{_rCarry[0], _rAddr[15:0]} = (rTxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{rTxState[6]}} & {rLen, 2'd0}))); // S_TXPORTWR_TX_WRITE
{_rCarry[1], _rAddr[31:16]} = (rTxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rTxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rTxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
_rSentWords = (rTxState[7] ? NEW_TXN_WORDS_RECVD : rSentWords) + ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rWords = (NEW_TXN_ACK ? NEW_TXN_LEN : (rWords - ({10{rTxState[6]}} & rLen))); // S_TXPORTWR_TX_WRITE
_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);
_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rPageRem = wPageRem;
_rPageSpillInit = (rBufWordsInit > wPageRem);
_rPageSpill = (rBufWords > wPageRem);
_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
_rMaxPayloadSize = CONFIG_MAX_PAYLOAD_SIZE;
_rMaxPayloadShift = (rMaxPayloadSize > 3'd4 ? 3'd4 : rMaxPayloadSize);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rMaxLen = ((rMaxLen & !rValsProp[1]) | rTxState[6]); // S_TXPORTWR_TX_WRITE
_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
_rSendingWords = rSentWords + rLen;
_rAvail = (NEW_TXN_WORDS_RECVD >= rSendingWords);
_rTxnDone = ((rTxnDone<<1) | NEW_TXN_DONE);
_rLastLen = wLastLen;
_rLastLenEQ0 = (rLastLen == 10'd0);
_rLenEQWords = (rLen == rWords);
_rLenEQBufWords = (rLen == rBufWords);
case (rTxState)
`S_TXPORTWR_TX_IDLE: begin // Wait for channel write request
if (rMainState[4] & !rStarted) // S_TXPORTWR_MAIN_WRITE
_rTxState = `S_TXPORTWR_TX_BUF;
end
`S_TXPORTWR_TX_BUF: begin // Wait for buffer length and address
if (SG_ELEM_RDY)
_rTxState = `S_TXPORTWR_TX_ADJ_0;
end
`S_TXPORTWR_TX_ADJ_0: begin // Fix for large buffer
_rCopyBufWords = 1;
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_ADJ_1: begin // Check for page boundary crossing
_rCopyBufWords = 0;
_rUseInit = rCopyBufWords;
_rTxState = `S_TXPORTWR_TX_ADJ_2;
end
`S_TXPORTWR_TX_ADJ_2: begin // Wait for values to propagate
// Fix for page boundary crossing
// Check for max payload
// Fix for max payload
_rUseInit = 0;
if (rValsProp[2])
_rTxState = `S_TXPORTWR_TX_CHECK_DATA;
end
`S_TXPORTWR_TX_CHECK_DATA: begin // Wait for available data
if (rNotRequesting) begin
if (rAvail)
_rTxState = `S_TXPORTWR_TX_WRITE;
else if (rValsPropagated & rTxnDone[1])
_rTxState = (rLastLenEQ0 ? `S_TXPORTWR_TX_IDLE : `S_TXPORTWR_TX_WRITE_REM);
end
end
`S_TXPORTWR_TX_WRITE: begin // Send len and repeat or finish?
if (rLenEQWords)
_rTxState = `S_TXPORTWR_TX_IDLE;
else if (rLenEQBufWords)
_rTxState = `S_TXPORTWR_TX_BUF;
else
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_WRITE_REM: begin // Send remaining data and finish
_rTxState = `S_TXPORTWR_TX_IDLE;
end
default: begin
_rTxState = `S_TXPORTWR_TX_IDLE;
end
endcase
end
// Request TX transfers separately so that the TX FSM can continue calculating
// the next set of request parameters without having to wait for the TX_REQ_ACK.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rNotRequesting <= #1 (RST ? 1'd1 : _rNotRequesting);
rReqAddr <= #1 _rReqAddr;
rReqLen <= #1 _rReqLen;
rReqLast <= #1 _rReqLast;
rDone <= #1 _rDone;
rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);
end
always @ (*) begin
// Start signaling when the TX FSM is ready.
if (rTxState[6] | rTxState[7]) // S_TXPORTWR_TX_WRITE
_rNotRequesting = 0;
else
_rNotRequesting = (rNotRequesting | rTxReqAck);
// Pass off the rAddr & rLen when ready and wait for TX_REQ_ACK.
if (rTxState[6]) begin // S_TXPORTWR_TX_WRITE
_rReqAddr = rAddr;
_rReqLen = rLen;
_rReqLast = rLenEQWords;
end
else if (rTxState[7]) begin // S_TXPORTWR_TX_WRITE_REM
_rReqAddr = rAddr;
_rReqLen = rLastLen;
_rReqLast = 1;
end
else begin
_rReqAddr = rReqAddr;
_rReqLen = rReqLen;
_rReqLast = rReqLast;
end
// Track TX_REQ_ACK and TX_SENT to determine when the transaction is over.
_rDone = (rAckCount == 10'd0);
if (rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + rTxState[6] + rTxState[7] - rTxSent; // S_TXPORTWR_TX_WRITE, S_TXPORTWR_TX_WRITE_REM
// Track when the user reads the actual transfer amount.
_rLastDoneRead = (rMainState[6] ? 1'd0 : (rLastDoneRead | rTxnDoneAck)); // S_TXPORTWR_MAIN_SIG_DONE
end
// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
// has begun sending. This will happen when the workstation detects that it has
// sent/used all its currently mapped scatter gather elements, but it's not enough
// to complete the transaction. The TXN_DONE will let the workstation know it can
// release the current scatter gather mappings and allocate new ones.
always @ (posedge CLK) begin
rPartialDone <= #1 _rPartialDone;
rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
end
always @ (*) begin
// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK,
// we have no outstanding transfer requests, we're not currently requesting a
// transfer, and there are no more scatter gather elements.
_rPartialDone = (rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]); // S_TXPORTWR_TX_BUF
// Keep track of (seemingly superfluous) TXN_ACK requests.
if ((rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]) | rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rReqPartialDone = 0;
else
_rReqPartialDone = (rReqPartialDone | (rTxnAck & !rMainState[3])); // !S_TXPORTWR_MAIN_NEW_ACK
end
endmodule |
module clkgen(input wire clkin, input wire clk25m_on, output wire clkout, output wire [3:0] clk25m, output wire locked);
//reg cnt ;
wire clkout_div ;
//always @ ( posedge clkout )
// cnt <= ~cnt ;
//assign clk25m = cnt ;
//assign clk25m = clkout_div ;
ODDR2 ODDR2_inst0 (
.Q (clk25m[0]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst1 (
.Q (clk25m[1]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst2 (
.Q (clk25m[2]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst3 (
.Q (clk25m[3]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
DCM_CLKGEN #( // {{{
.CLKFXDV_DIVIDE(4), // CLKFXDV divide value (2, 4, 8, 16, 32)
.CLKFX_DIVIDE(1), // Divide value - D - (1-256)
.CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis
.CLKFX_MULTIPLY(4), // Multiply value - M - (2-256)
.CLKIN_PERIOD(40.0), // Input clock period specified in nS
.SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
// "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
) DCM (
.CLKFX(clkout), // 1-bit output: Generated clock output
.CLKFX180(), // 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
.CLKFXDV(clkout_div), // 1-bit output: Divided clock output
.LOCKED(locked), // 1-bit output: Locked output
.PROGDONE(), // 1-bit output: Active high output to indicate the successful re-programming
.STATUS(), // 2-bit output: DCM_CLKGEN status
.CLKIN(clkin), // 1-bit input: Input clock
.FREEZEDCM(1'b0), // 1-bit input: Prevents frequency adjustments to input clock
.PROGCLK(1'b0), // 1-bit input: Clock input for M/D reconfiguration
.PROGDATA(1'b0), // 1-bit input: Serial data input for M/D reconfiguration
.PROGEN(1'b0), // 1-bit input: Active high program enable
.RST(1'b0) // 1-bit input: Reset input pin
); // }}}
endmodule |
module pmi_fifo #(
parameter pmi_data_width = 8,
parameter pmi_data_depth = 16,
parameter pmi_full_flag = 16,
parameter pmi_empty_flag = 0,
parameter pmi_almost_full_flag = 1,
parameter pmi_almost_empty_flag = 0,
parameter pmi_regmode = "noreg",
parameter pmi_family = 0,
parameter module_type = "pmi_fifo",
parameter pmi_implementation = "LUT"
)(
input wire [pmi_data_width - 1 : 0] Data,
input wire Clock,
input wire WrEn,
input wire RdEn,
input wire Reset,
output wire [pmi_data_width - 1 : 0] Q,
output wire Empty,
output wire Full,
output wire AlmostEmpty,
output wire AlmostFull
);
fifo_uart fifo_uart_inst(
.clk(Clock),
.srst(Reset),
.din(Data),
.wr_en(WrEn),
.rd_en(RdEn),
.dout(Q),
.full(Full),
.almost_full(AlmostFull),
.empty(Empty),
.almost_empty(AlmostEmpty)
);
endmodule |
module pmi_addsub #(
parameter pmi_data_width = 32,
parameter pmi_result_width = 32,
parameter pmi_sign = "off", // unused
parameter pmi_family = 0,
parameter module_type= "pmi_addsub"
)(
input wire [pmi_data_width - 1 : 0] DataA,
input wire [pmi_data_width - 1 : 0] DataB,
input wire Cin,
input wire Add_Sub,
output wire [pmi_result_width - 1 : 0]Result,
output wire Cout,
output wire Overflow
);
wire [pmi_data_width : 0] tmp_addResult = DataA + DataB + Cin;
wire [pmi_data_width : 0] tmp_subResult = DataA - DataB - !Cin;
assign Result = (Add_Sub == 1) ? tmp_addResult[pmi_result_width - 1 : 0] : tmp_subResult[pmi_result_width - 1 : 0];
assign Cout = (Add_Sub == 1) ? tmp_addResult[pmi_data_width] : !tmp_subResult[pmi_data_width];
assign Overflow = Cout;
endmodule |
module BB(
input I,
input T,
output wire O,
output wire B
);
assign B = T ? 1'bz : I;
assign O = B;
endmodule |
module sha_core (
input wire clk ,
input wire rst ,
input wire [31:0] SHA256_H0 ,
input wire [31:0] SHA256_H1 ,
input wire [31:0] SHA256_H2 ,
input wire [31:0] SHA256_H3 ,
input wire [31:0] SHA256_H4 ,
input wire [31:0] SHA256_H5 ,
input wire [31:0] SHA256_H6 ,
input wire [31:0] SHA256_H7 ,
output reg [31:0] A0 ,
output reg [31:0] A1 ,
output reg [31:0] A2 ,
output reg [31:0] E0 ,
output reg [31:0] E1 ,
output reg [31:0] E2 ,
input wire init ,//sha core initial
input wire vld ,//data input valid
input wire [31:0] din ,
output reg done ,
output wire [255:0] hash
) ;
reg [6:0] round ;
wire [6:0] round_plus_1 ;
reg [31:0] H0,H1,H2,H3,H4,H5,H6,H7 ;
reg [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14 ;
reg [31:0] Wt,Kt ;
reg [31:0] A,B,C,D,E,F,G,H ;
reg busy ;
wire [31:0] f1_EFG_32,f2_ABC_32,f3_A_32,f4_E_32,f5_W1_32,f6_W14_32,T1_32,T2_32 ;
wire [31:0] next_Wt,next_E,next_A ;
assign f1_EFG_32 = (E & F) ^ (~E & G) ;
assign f2_ABC_32 = (A & B) ^ (B & C) ^ (A & C) ;
assign f3_A_32 = {A[1:0],A[31:2]} ^ {A[12:0],A[31:13]} ^ {A[21:0],A[31:22]} ;
assign f4_E_32 = {E[5:0],E[31:6]} ^ {E[10:0],E[31:11]} ^ {E[24:0],E[31:25]} ;
assign f5_W1_32 = {W1[6:0],W1[31:7]} ^ {W1[17:0],W1[31:18]} ^ {3'b000,W1[31:3]} ;
assign f6_W14_32 = {W14[16:0],W14[31:17]} ^ {W14[18:0],W14[31:19]} ^ {10'b00_0000_0000,W14[31:10]} ;
assign T1_32 = H[31:0] + f4_E_32 + f1_EFG_32 + Kt + Wt ;
assign T2_32 = f3_A_32 + f2_ABC_32 ;
assign next_Wt = f6_W14_32 + W9[31:0] + f5_W1_32 + W0[31:0] ;
assign next_E = D[31:0] + T1_32 ;
assign next_A = T1_32 + T2_32 ;
assign hash = {A,B,C,D,E,F,G,H} ;
assign round_plus_1 = round + 1 ;
always @ ( posedge clk ) begin
if( init ) begin
H0 <= SHA256_H0 ;
H1 <= SHA256_H1 ;
H2 <= SHA256_H2 ;
H3 <= SHA256_H3 ;
H4 <= SHA256_H4 ;
H5 <= SHA256_H5 ;
H6 <= SHA256_H6 ;
H7 <= SHA256_H7 ;
end else if( done ) begin
H0 <= A ;
H1 <= B ;
H2 <= C ;
H3 <= D ;
H4 <= E ;
H5 <= F ;
H6 <= G ;
H7 <= H ;
end
end
//------------------------------------------------------------------
// SHA round
//------------------------------------------------------------------
always @(posedge clk)
begin
if (rst)
begin
round <= 'd0 ;
busy <= 'b0 ;
W0 <= 'b0 ;
W1 <= 'b0 ;
W2 <= 'b0 ;
W3 <= 'b0 ;
W4 <= 'b0 ;
W5 <= 'b0 ;
W6 <= 'b0 ;
W7 <= 'b0 ;
W8 <= 'b0 ;
W9 <= 'b0 ;
W10 <= 'b0 ;
W11 <= 'b0 ;
W12 <= 'b0 ;
W13 <= 'b0 ;
W14 <= 'b0 ;
Wt <= 'b0 ;
A <= 'b0 ;
B <= 'b0 ;
C <= 'b0 ;
D <= 'b0 ;
E <= 'b0 ;
F <= 'b0 ;
G <= 'b0 ;
H <= 'b0 ;
end else if( init ) begin
A <= SHA256_H0 ;
B <= SHA256_H1 ;
C <= SHA256_H2 ;
D <= SHA256_H3 ;
E <= SHA256_H4 ;
F <= SHA256_H5 ;
G <= SHA256_H6 ;
H <= SHA256_H7 ;
end else begin
case (round)
'd0:
if( vld ) begin
W0 <= din ;
Wt <= din ;
busy <= 'b1 ;
round <= round_plus_1 ;
end
'd1:
if( vld ) begin
W1 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
A0<= next_A ;
E0<= next_E ;
round <= round_plus_1 ;
end
'd2:
if( vld ) begin
W2 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
A1<= next_A ;
E1<= next_E ;
round <= round_plus_1 ;
end
'd3:
if( vld ) begin
W3 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
A2<= next_A ;
E2<= next_E ;
round <= round_plus_1 ;
end
'd4:
if( vld ) begin
W4 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd5:
if( vld ) begin
W5 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd6:
if( vld ) begin
W6 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd7:
if( vld ) begin
W7 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd8:
if( vld ) begin
W8 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd9:
if( vld ) begin
W9 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd10:
if( vld ) begin
W10 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd11:
if( vld ) begin
W11 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd12:
if( vld ) begin
W12 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd13:
if( vld ) begin
W13 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd14:
if( vld ) begin
W14 <= din ;
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd15:
if( vld ) begin
Wt <= din ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd16,'d17,'d18,'d19,'d20,'d21,'d22,'d23,'d24,'d25,'d26,'d27,'d28,'d29,'d30,'d31,
'd32,'d33,'d34,'d35,'d36,'d37,'d38,'d39,'d40,'d41,'d42,'d43,'d44,'d45,'d46,'d47,
'd48,'d49,'d50,'d51,'d52,'d53,'d54,'d55,'d56,'d57,'d58,'d59,'d60,'d61,'d62,'d63:
begin
W0 <= W1 ;
W1 <= W2 ;
W2 <= W3 ;
W3 <= W4 ;
W4 <= W5 ;
W5 <= W6 ;
W6 <= W7 ;
W7 <= W8 ;
W8 <= W9 ;
W9 <= W10 ;
W10 <= W11 ;
W11 <= W12 ;
W12 <= W13 ;
W13 <= W14 ;
W14 <= Wt ;
Wt <= next_Wt ;
H <= G ;
G <= F ;
F <= E ;
E <= next_E ;
D <= C ;
C <= B ;
B <= A ;
A <= next_A ;
round <= round_plus_1 ;
end
'd64:
begin
A <= next_A + H0 ;
B <= A + H1 ;
C <= B + H2 ;
D <= C + H3 ;
E <= next_E + H4 ;
F <= E + H5 ;
G <= F + H6 ;
H <= G + H7 ;
round <= 'd0 ;
busy <= 'b0 ;
end
default:
begin
round <= 'd0 ;
busy <= 'b0 ;
end
endcase
end
end
//------------------------------------------------------------------
// Kt generator
//------------------------------------------------------------------
always @ (posedge clk)
begin
if (rst)
begin
Kt <= 'b0 ;
end
else
begin
case (round)
'd00: if(vld) Kt <= `K00 ;
'd01: if(vld) Kt <= `K01 ;
'd02: if(vld) Kt <= `K02 ;
'd03: if(vld) Kt <= `K03 ;
'd04: if(vld) Kt <= `K04 ;
'd05: if(vld) Kt <= `K05 ;
'd06: if(vld) Kt <= `K06 ;
'd07: if(vld) Kt <= `K07 ;
'd08: if(vld) Kt <= `K08 ;
'd09: if(vld) Kt <= `K09 ;
'd10: if(vld) Kt <= `K10 ;
'd11: if(vld) Kt <= `K11 ;
'd12: if(vld) Kt <= `K12 ;
'd13: if(vld) Kt <= `K13 ;
'd14: if(vld) Kt <= `K14 ;
'd15: if(vld) Kt <= `K15 ;
'd16: Kt <= `K16 ;
'd17: Kt <= `K17 ;
'd18: Kt <= `K18 ;
'd19: Kt <= `K19 ;
'd20: Kt <= `K20 ;
'd21: Kt <= `K21 ;
'd22: Kt <= `K22 ;
'd23: Kt <= `K23 ;
'd24: Kt <= `K24 ;
'd25: Kt <= `K25 ;
'd26: Kt <= `K26 ;
'd27: Kt <= `K27 ;
'd28: Kt <= `K28 ;
'd29: Kt <= `K29 ;
'd30: Kt <= `K30 ;
'd31: Kt <= `K31 ;
'd32: Kt <= `K32 ;
'd33: Kt <= `K33 ;
'd34: Kt <= `K34 ;
'd35: Kt <= `K35 ;
'd36: Kt <= `K36 ;
'd37: Kt <= `K37 ;
'd38: Kt <= `K38 ;
'd39: Kt <= `K39 ;
'd40: Kt <= `K40 ;
'd41: Kt <= `K41 ;
'd42: Kt <= `K42 ;
'd43: Kt <= `K43 ;
'd44: Kt <= `K44 ;
'd45: Kt <= `K45 ;
'd46: Kt <= `K46 ;
'd47: Kt <= `K47 ;
'd48: Kt <= `K48 ;
'd49: Kt <= `K49 ;
'd50: Kt <= `K50 ;
'd51: Kt <= `K51 ;
'd52: Kt <= `K52 ;
'd53: Kt <= `K53 ;
'd54: Kt <= `K54 ;
'd55: Kt <= `K55 ;
'd56: Kt <= `K56 ;
'd57: Kt <= `K57 ;
'd58: Kt <= `K58 ;
'd59: Kt <= `K59 ;
'd60: Kt <= `K60 ;
'd61: Kt <= `K61 ;
'd62: Kt <= `K62 ;
'd63: Kt <= `K63 ;
default:Kt <= 'd0 ;
endcase
end
end
//done
always @ ( posedge clk ) begin
if( rst )
done <= 1'b0 ;
else if( round == 7'd64 )
done <= 1'b1 ;
else
done <= 1'b0 ;
end
endmodule |
module sha(
// system clock and reset
input CLK_I,
input RST_I,
// wishbone interface signals
input SHA_CYC_I,//NC
input SHA_STB_I,
input SHA_WE_I,
input SHA_LOCK_I,//NC
input [2:0] SHA_CTI_I,//NC
input [1:0] SHA_BTE_I,//NC
input [4:0] SHA_ADR_I,
input [31:0] SHA_DAT_I,
input [3:0] SHA_SEL_I,
output reg SHA_ACK_O,
output SHA_ERR_O,//const 0
output SHA_RTY_O,//const 0
output [31:0] SHA_DAT_O
);
assign SHA_ERR_O = 1'b0 ;
assign SHA_RTY_O = 1'b0 ;
//-----------------------------------------------------
// WB bus ACK
//-----------------------------------------------------
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
SHA_ACK_O <= 1'b0 ;
else if( SHA_STB_I && (~SHA_ACK_O) )
SHA_ACK_O <= 1'b1 ;
else
SHA_ACK_O <= 1'b0 ;
end
wire sha_cmd_wr_en = SHA_STB_I & SHA_WE_I & ( SHA_ADR_I == 5'h0) & ~SHA_ACK_O ;
wire sha_din_wr_en = SHA_STB_I & SHA_WE_I & ( SHA_ADR_I == 5'h4) & ~SHA_ACK_O ;
wire sha_hi_wr_en = SHA_STB_I & SHA_WE_I & ( SHA_ADR_I == 5'hc) & ~SHA_ACK_O ;
wire sha_cmd_rd_en = SHA_STB_I & ~SHA_WE_I & ( SHA_ADR_I == 5'h0 ) & ~SHA_ACK_O ;
wire sha_hash_rd_en = SHA_STB_I & ~SHA_WE_I & ( SHA_ADR_I == 5'h8 ) & ~SHA_ACK_O ;
wire sha_pre_rd_en = SHA_STB_I & ~SHA_WE_I & ( SHA_ADR_I == 5'h10) & ~SHA_ACK_O ;
//-----------------------------------------------------
// REG SHA_CMD
//-----------------------------------------------------
reg reg_init ;
reg reg_done ;
reg reg_rst ;
reg reg_dbl ;
wire done ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_init <= 1'b0 ;
else if( sha_cmd_wr_en )
reg_init <= SHA_DAT_I[0]||SHA_DAT_I[3] ;
else
reg_init <= 1'b0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_done <= 1'b0 ;
else if( done )
reg_done <= 1'b1 ;
else if( sha_din_wr_en || (sha_cmd_wr_en && SHA_DAT_I[3]))
reg_done <= 1'b0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_rst <= 1'b0 ;
else if( sha_cmd_wr_en )
reg_rst <= SHA_DAT_I[2] ;
else
reg_rst <= 1'b0 ;
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I )
reg_dbl <= 1'b0 ;
else if( sha_cmd_wr_en )
reg_dbl <= SHA_DAT_I[3] ;
else
reg_dbl <= 1'b0 ;
end
//-----------------------------------------------------
// REG SHA_DIN
//-----------------------------------------------------
reg [31:0] reg_din ;
reg vld ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I ) begin
reg_din <= 32'b0 ;
vld <= 1'b0 ;
end else if( sha_din_wr_en ) begin
reg_din <= SHA_DAT_I[31:0] ;
vld <= 1'b1 ;
end else
vld <= 1'b0 ;
end
//-----------------------------------------------------
// REG SHA_HASH
//-----------------------------------------------------
reg [2:0] hash_cnt ;
reg [31:0] reg_hash ;
wire [255:0] hash ;
reg sha_hash_rd_en_r ;
always @ ( posedge CLK_I )
sha_hash_rd_en_r <= sha_hash_rd_en ;
always @ ( * ) begin
case( hash_cnt )
3'd0: reg_hash = hash[32*8-1:32*7] ;
3'd1: reg_hash = hash[32*7-1:32*6] ;
3'd2: reg_hash = hash[32*6-1:32*5] ;
3'd3: reg_hash = hash[32*5-1:32*4] ;
3'd4: reg_hash = hash[32*4-1:32*3] ;
3'd5: reg_hash = hash[32*3-1:32*2] ;
3'd6: reg_hash = hash[32*2-1:32*1] ;
3'd7: reg_hash = hash[32*1-1:32*0] ;
endcase
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I | reg_init )
hash_cnt <= 3'b0 ;
else if( sha_hash_rd_en_r )
hash_cnt <= hash_cnt + 3'b1 ;
end
//-----------------------------------------------------
// REG SHA_HI
//-----------------------------------------------------
reg [8*32-1:0] SHA256_Hx ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I | reg_rst ) begin
SHA256_Hx[8*32-1:7*32] <= `DEF_SHA256_H0 ;
SHA256_Hx[7*32-1:6*32] <= `DEF_SHA256_H1 ;
SHA256_Hx[6*32-1:5*32] <= `DEF_SHA256_H2 ;
SHA256_Hx[5*32-1:4*32] <= `DEF_SHA256_H3 ;
SHA256_Hx[4*32-1:3*32] <= `DEF_SHA256_H4 ;
SHA256_Hx[3*32-1:2*32] <= `DEF_SHA256_H5 ;
SHA256_Hx[2*32-1:1*32] <= `DEF_SHA256_H6 ;
SHA256_Hx[1*32-1:0*32] <= `DEF_SHA256_H7 ;
end else if( sha_hi_wr_en )
SHA256_Hx <= {SHA256_Hx[7*32-1:0],SHA_DAT_I[31:0]} ;
end
//-----------------------------------------------------
// REG SHA_PRE
//-----------------------------------------------------
wire [32*6-1:0] PRE ;
reg [2:0] pre_cnt ;
reg [31:0] reg_pre ;
reg sha_pre_rd_en_r ;
always @ ( posedge CLK_I )
sha_pre_rd_en_r <= sha_pre_rd_en ;
always @ ( * ) begin
case( pre_cnt )
3'd0: reg_pre = PRE[32*1-1:32*0] ;
3'd1: reg_pre = PRE[32*2-1:32*1] ;
3'd2: reg_pre = PRE[32*3-1:32*2] ;
3'd3: reg_pre = PRE[32*4-1:32*3] ;
3'd4: reg_pre = PRE[32*5-1:32*4] ;
3'd5: reg_pre = PRE[32*6-1:32*5] ;
default: reg_pre = 32'b0 ;
endcase
end
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I | reg_init )
pre_cnt <= 3'b0 ;
else if( sha_pre_rd_en_r )
pre_cnt <= pre_cnt + 3'b1 ;
end
//-----------------------------------------------------
// Bus output
//-----------------------------------------------------
reg sha_cmd_rd_en_f ;
reg sha_hash_rd_en_f ;
always @ ( posedge CLK_I or posedge RST_I ) begin
if( RST_I ) begin
sha_cmd_rd_en_f <= 1'b0 ;
sha_hash_rd_en_f <= 1'b0 ;
end else begin
sha_cmd_rd_en_f <= sha_cmd_rd_en ;
sha_hash_rd_en_f <= sha_hash_rd_en ;
end
end
assign SHA_DAT_O = sha_cmd_rd_en_f ? {30'h0,reg_done,1'b0} :
sha_hash_rd_en_f ? reg_hash : reg_pre ;
//-----------------------------------------------------
// Double SHA
//-----------------------------------------------------
wire dbl_vld ;
wire [31:0] dbl_din ;
dbl_sha U_dbl_sha(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
/*input */ .reg_dbl (reg_dbl) ,
/*input */ .done (done ) ,
/*input [255:0]*/ .hash (hash ) ,
/*output */ .dbl_vld (dbl_vld) ,
/*output[31:0] */ .dbl_din (dbl_din)
);
sha_core U_sha_core(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
/*input [31:0] */ .SHA256_H0 (SHA256_Hx[32*8-1:32*7]) ,
/*input [31:0] */ .SHA256_H1 (SHA256_Hx[32*7-1:32*6]) ,
/*input [31:0] */ .SHA256_H2 (SHA256_Hx[32*6-1:32*5]) ,
/*input [31:0] */ .SHA256_H3 (SHA256_Hx[32*5-1:32*4]) ,
/*input [31:0] */ .SHA256_H4 (SHA256_Hx[32*4-1:32*3]) ,
/*input [31:0] */ .SHA256_H5 (SHA256_Hx[32*3-1:32*2]) ,
/*input [31:0] */ .SHA256_H6 (SHA256_Hx[32*2-1:32*1]) ,
/*input [31:0] */ .SHA256_H7 (SHA256_Hx[32*1-1:32*0]) ,
/*output [31:0] */ .A0 (PRE[32*1-1:32*0] ) ,
/*output [31:0] */ .A1 (PRE[32*2-1:32*1] ) ,
/*output [31:0] */ .A2 (PRE[32*3-1:32*2] ) ,
/*output [31:0] */ .E0 (PRE[32*4-1:32*3] ) ,
/*output [31:0] */ .E1 (PRE[32*5-1:32*4] ) ,
/*output [31:0] */ .E2 (PRE[32*6-1:32*5] ) ,
/*input */ .init (reg_init ) ,//sha core initial
/*input */ .vld (vld|dbl_vld ) ,//data input valid
/*input [31:0] */ .din (dbl_vld?dbl_din: reg_din ) ,
/*output */ .done (done ) ,
/*output [255:0]*/ .hash (hash )
) ;
endmodule |
module dbl_sha(
input clk ,
input rst ,
input reg_dbl ,
input done ,
input [255:0] hash ,
output dbl_vld ,
output[31:0] dbl_din
);
/*
_________________________
start __| |___
____ _ __ ___
cnt _0__|_1-------------------31|_0_
*/
reg start ;
reg [3:0] cnt ;//0~31
reg [255:0] hash_r ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
start <= 1'b0 ;
else if( reg_dbl )
start <= 1'b1 ;
else if( cnt == 15 )
start <= 1'b0 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
cnt <= 'b0 ;
else if( start )
cnt <= cnt + 'b1 ;
end
always @ ( posedge clk ) begin
if( done )
hash_r <= hash ;
else if( start && cnt != 7 )
hash_r <= hash_r << 32 ;
else if( start )//cnt == 15
hash_r <= 256'h80000000_00000000_00000000_00000000_00000000_00000000_00000000_00000100 ;
end
assign dbl_vld = start ;
assign dbl_din = hash_r[255:255-31] ;
endmodule |
module alink(
// system clock and reset
input CLK_I ,
input RST_I ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,//NC
input [2:0] ALINK_CTI_I ,//NC
input [1:0] ALINK_BTE_I ,//NC
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output ALINK_ACK_O ,
output ALINK_ERR_O ,//const 0
output ALINK_RTY_O ,//const 0
output [31:0] ALINK_DAT_O ,
//TX.PHY
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N ,
//RX.PHY
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N ,
output [4:0] ALINK_led
);
//-------------------------------------------------
// WBBUS
//-------------------------------------------------
assign ALINK_ERR_O = 1'b0 ;
assign ALINK_RTY_O = 1'b0 ;
wire [31:0] reg_tout ;
wire txfifo_push ;
wire [31:0] txfifo_din ;
wire [3:0] rxcnt ;
wire rxempty ;
wire [3:0] txcnt ;
wire reg_flush ;
wire txfull ;
wire [31:0] reg_mask ;
wire reg_scan ;
wire [31:0] busy ;
assign ALINK_led[0] = ~reg_mask[0] ;
assign ALINK_led[1] = ~reg_mask[1] ;
assign ALINK_led[2] = ~reg_mask[2] ;
assign ALINK_led[3] = ~reg_mask[3] ;
assign ALINK_led[4] = ~reg_mask[4] ;
wire rxfifo_pop ;
wire [31:0] rxfifo_dout ;
wire [31 : 0] tx_din ;
wire tx_wr_en ;
wire tx_rd_en ;
wire [31 : 0] tx_dout ;
wire [10 : 0] tx_data_count ;
wire [31 : 0] rx_din ;
wire rx_wr_en ;
wire [9 : 0] rx_data_count ;
wire tx_phy_start ;
wire [`PHY_NUM-1:0] tx_phy_sel ;
wire tx_phy_done ;
wire [1:0] cur_state ;
wire [1:0] nxt_state ;
wire [32*`PHY_NUM-1:0] timer_cnt ;//to slave
wire task_id_vld ;
wire [31:0] rx_phy_sel ;
wire [31:0] task_id_h ;
wire [31:0] task_id_l ;
//-------------------------------------------------
// Slave
//-------------------------------------------------
alink_slave alink_slave(
// system clock and reset
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
// wishbone interface signals
/*input */ .ALINK_CYC_I (ALINK_CYC_I ) ,//NC
/*input */ .ALINK_STB_I (ALINK_STB_I ) ,
/*input */ .ALINK_WE_I (ALINK_WE_I ) ,
/*input */ .ALINK_LOCK_I(ALINK_LOCK_I ) ,//NC
/*input [2:0] */ .ALINK_CTI_I (ALINK_CTI_I ) ,//NC
/*input [1:0] */ .ALINK_BTE_I (ALINK_BTE_I ) ,//NC
/*input [5:0] */ .ALINK_ADR_I (ALINK_ADR_I ) ,
/*input [31:0] */ .ALINK_DAT_I (ALINK_DAT_I ) ,
/*input [3:0] */ .ALINK_SEL_I (ALINK_SEL_I ) ,
/*output reg */ .ALINK_ACK_O (ALINK_ACK_O ) ,
/*output */ .ALINK_ERR_O (ALINK_ERR_O ) ,//const 0
/*output */ .ALINK_RTY_O (ALINK_RTY_O ) ,//const 0
/*output reg [31:0] */ .ALINK_DAT_O (ALINK_DAT_O ) ,
/*output reg */ .txfifo_push (tx_wr_en ) ,
/*output reg [31:0] */ .txfifo_din (tx_din ) ,
/*input [9:0] */ .rxcnt (rx_data_count ) ,
/*input */ .rxempty (rxempty ) ,
/*input [10:0] */ .txcnt (tx_data_count ) ,
/*output reg */ .reg_flush (reg_flush ) ,
/*input */ .txfull (txfull ) ,
/*output reg [31:0] */ .reg_mask (reg_mask ) ,
/*output reg */ .reg_scan (reg_scan ) ,
/*input [31:0] */ .busy (busy ) ,
/*output */ .rxfifo_pop (rxfifo_pop ) ,
/*input [31:0] */ .rxfifo_dout (rxfifo_dout )
);
//-------------------------------------------------
// TX.FIFO
//-------------------------------------------------
assign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ;//tx fifo almost full
wire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ;//at list ONE task in tx_fifo
tx_fifo tx_fifo(
/*input */ .clk (CLK_I ),
/*input */ .srst (RST_I|reg_flush ),
/*input [31 : 0]*/ .din (tx_din ),
/*input */ .wr_en (tx_wr_en ),
/*input */ .rd_en (tx_rd_en ),
/*output [31 : 0]*/ .dout (tx_dout ),
/*output */ .full ( ),
/*output */ .empty ( ),
/*output [10 : 0]*/ .data_count(tx_data_count )
) ;
//-------------------------------------------------
// RX.FIFO
//-------------------------------------------------
assign rxempty = rx_data_count < `RX_DATA_LEN ;
wire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ; //at list ONE report can be pull into rx_fifo
`ifdef SIM
always @ ( posedge rx_almost_full ) begin
#200 ;
$display("[WAR] rx fifo full:%d",rx_data_count);
end
`endif
rx_fifo rx_fifo(
/*input */ .clk (CLK_I ),
/*input */ .srst (RST_I|reg_flush ),
/*input [31 : 0]*/ .din (rx_din ),
/*input */ .wr_en (rx_wr_en ),
/*input */ .rd_en (rxfifo_pop ),
/*output [31 : 0]*/ .dout (rxfifo_dout ),
/*output */ .full (rx_full ),
/*output */ .empty ( ),
/*output [9 : 0] */ .data_count(rx_data_count )
);
//-------------------------------------------------
// TX.arbiter
//-------------------------------------------------
txc txc(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [`PHY_NUM-1:0] */ .reg_mask (reg_mask ) ,
/*input */ .task_id_vld (task_id_vld ) ,
/*input [31:0] */ .reg_tout (reg_tout ) ,
/*input */ .tx_task_vld (tx_task_vld ) ,//tx fifo not empty
/*output reg */ .tx_phy_start(tx_phy_start ) ,
/*output reg [`PHY_NUM-1:0]*/ .tx_phy_sel (tx_phy_sel ) ,
/*input */ .tx_phy_done (tx_phy_done ) ,
/*output reg [1:0] */ .cur_state (cur_state ) ,
/*output reg [1:0] */ .nxt_state (nxt_state ) ,
/*output [32*`PHY_NUM-1:0] */ .timer_cnt (timer_cnt ) ,//to slave
/*output [`PHY_NUM-1:0] */ .reg_busy (busy )
);
//-------------------------------------------------
// TX.PHY
//-------------------------------------------------
tx_phy tx_phy(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input */ .reg_scan (reg_scan ) ,
/*input */ .tx_phy_start(tx_phy_start ) ,
/*input [31:0] */ .tx_phy_sel (tx_phy_sel ) ,
/*output */ .tx_phy_done (tx_phy_done ) ,
/*input [31:0] */ .tx_dout (tx_dout ) ,
/*output */ .tx_rd_en (tx_rd_en ) ,
/*output reg */ .task_id_vld (task_id_vld ) ,
/*output reg [31:0]*/ .rx_phy_sel (rx_phy_sel ) ,
/*output reg [31:0]*/ .task_id_h (task_id_h ) ,
/*output reg [31:0]*/ .task_id_l (task_id_l ) ,
/*output reg [31:0]*/ .reg_tout (reg_tout ) ,
/*output [31:0] */ .TX_P (TX_P ) ,
/*output [31:0] */ .TX_N (TX_N )
);
/*
// VIO/ILA and ICON {{{
wire [35:0] icon_ctrl_0;
wire [255:0] trig0 = {
4'ha ,//94:91
tx_data_count[10:0],//90:80
rx_data_count[9:0],//79:70
tx_dout[31:0],//69:38
tx_rd_en,//37
TX_P[1] ,//36
TX_N[1] ,//35
RX_P[1] ,//34
RX_N[1] ,//33
rx_wr_en ,//32
rx_din[31:0]//31:0
} ;
icon icon_test(.CONTROL0(icon_ctrl_0));
ila ila_test(.CONTROL(icon_ctrl_0), .CLK(CLK_I), .TRIG0(trig0)
);
*/
//-------------------------------------------------
// RX.PHY
//-------------------------------------------------
rxc rxc(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [31:0]*/ .reg_mask (reg_mask ) ,
/*input [31:0]*/ .reg_busy (busy ) ,
/*input */ .rx_almost_full (rx_almost_full ) ,
/*input */ .tx_phy_start (tx_phy_start ) ,
/*input [31:0]*/ .tx_phy_sel (tx_phy_sel ) ,
/*input */ .task_id_vld (task_id_vld ) ,
/*input [31:0]*/ .rx_phy_sel (rx_phy_sel ) ,
/*input [31:0]*/ .task_id_h (task_id_h ) ,
/*input [31:0]*/ .task_id_l (task_id_l ) ,
/*input [32*`PHY_NUM-1:0]*/ .timer_cnt (timer_cnt ) ,
/*output */ .rx_vld (rx_wr_en ) ,
/*output [31:0]*/ .rx_dat (rx_din ) ,
/*input [31:0]*/ .RX_P (RX_P ) ,
/*input [31:0]*/ .RX_N (RX_N )
);
endmodule |
module tx_timer(
input clk ,
input rst ,
input reg_flush ,
input [31:0] reg_tout ,
input timer_start ,
output reg timer_busy ,
output [31:0] timer_cnt
);
reg [25:0] timer ;
assign timer_cnt = {6'b0,timer} ;
always @ ( posedge clk ) begin
if( rst || (timer == reg_tout) || reg_flush )
timer <= 'b0 ;
else if( timer_start )
timer <= 'b1 ;
else if( |timer && (timer < reg_tout))
timer <= 'b1 + timer ;
end
always @ ( posedge clk ) begin
if( rst )
timer_busy <= 1'b0 ;
else if( timer_start )
timer_busy <= 1'b1 ;
else if ( (timer == reg_tout[25:0]) && |reg_tout[25:0] )
timer_busy <= 1'b0 ;
end
endmodule |
module rx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_busy ,
input task_id_vld ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [31:0] timer_cnt ,
output rx_start ,
output rx_last ,
output rx_vld ,
output [31:0] rx_dat ,
input RX_P ,
input RX_N
);
parameter MY_RXID = 32'd0 ;
/*
>INPUT<
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[task_id_h _________________|0_|_________________________
task_id_l]
>OUTPUT<
__
rx_start __| |____________________________________________________________
__
rx_last ________________________________________________| |______________
_____________________________________________
rx_vld _____| |______________
_____ _____________________________________________ ______________
rx_dat _____|RXID |TaskID_H|TaskID_L|TIME |NONCE |______________
(word0) (word1) (word2) (word3) (word4)
*/
//-------------------------------------------------
// Receive 1/0/start/stop
//-------------------------------------------------
reg [3:0] report_p_d ;
reg [3:0] report_n_d ;
always@(posedge clk or posedge rst )begin
if( reg_flush || rst || ~reg_busy) begin
report_p_d <= 4'hf ;
report_n_d <= 4'hf ;
end else begin
report_p_d <= #1 {report_p_d[2:0], RX_P};
report_n_d <= #1 {report_n_d[2:0], RX_N};
end
end
wire rx_0 = ((~report_n_d[3]) && (&report_n_d[2:1])) && ~(|report_p_d[3:1]);
wire rx_1 = ((~report_p_d[3]) && (&report_p_d[2:1])) && ~(|report_n_d[3:1]);
wire rx_stop = (report_p_d[3]^report_n_d[3]) && (report_p_d[2]^report_n_d[2]) && (report_p_d[1]&report_n_d[1]) ;
/*
wire rx_stop = (&report_p_d[3:1] && ~report_n_d[3] && &report_n_d[2:1]) ||
(&report_n_d[3:1] && ~report_p_d[3] && &report_p_d[2:1]) ||
(~report_p_d[3] && &report_p_d[2:1] && ~report_n_d[3] && &report_n_d[2:1]) ;
*/
reg [31:0] nonce_buf;
always@(posedge clk)begin
if(rx_0)
nonce_buf <= #1 {1'b0, nonce_buf[31:1]};
else if(rx_1)
nonce_buf <= #1 {1'b1, nonce_buf[31:1]};
end
//-------------------------------------------------
// Receive TaskID&Timer
//-------------------------------------------------
reg [31:0] task_id_h_r ;
reg [31:0] task_id_l_r ;
always @ ( posedge clk ) begin
if( ~rx_vld && task_id_vld ) begin
task_id_h_r <= task_id_h ;
task_id_l_r <= task_id_l ;
end
end
//-------------------------------------------------
// Push Out
//-------------------------------------------------
reg [2:0] push_cnt ;
always @ ( posedge clk ) begin
if( rst )
push_cnt <= 3'b0 ;
else if( reg_busy && rx_stop && ~rx_vld)
push_cnt <= 3'b1 ;
else if( |push_cnt && push_cnt < `RX_DATA_LEN )
push_cnt <= push_cnt + 3'b1 ;
else
push_cnt <= 3'b0 ;
end
assign rx_vld = |push_cnt ;
assign rx_dat = push_cnt == 1 ? MY_RXID :
push_cnt == 2 ? task_id_h_r :
push_cnt == 3 ? task_id_l_r :
push_cnt == 4 ? timer_cnt : nonce_buf ;
assign rx_start = reg_busy && rx_stop && ~rx_vld ;
assign rx_last = push_cnt == `RX_DATA_LEN ;
endmodule |
module rxc(
input clk ,
input rst ,
input reg_flush ,
input [31:0] reg_mask ,
input [31:0] reg_busy ,
input rx_almost_full ,
input tx_phy_start ,
input [31:0] tx_phy_sel ,
input task_id_vld ,
input [31:0] rx_phy_sel ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [`PHY_NUM*32-1:0] timer_cnt ,
output reg rx_vld ,
output reg [31:0] rx_dat ,
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N
);
/*
>INPUT<
__
tx_phy_start _____| |_____________________________________
_____ __ _____________________________________
tx_phy_sel _____|0 |_________________dont care___________
__
tx_phy_done ________________________________________| |__
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[rx_phy_sel _________________|0_|_________________________
task_id_h
task_id_l]
>OUTPUT<
_____________________________________________
rx_vld __| |______________
__ _____________________________________________ ______________
rx_dat __|RXID |TaskID_H|TaskID_L|TIME |NONCE |______________
*/
wire [31:0] rx_start ;
wire [31:0] rx_last ;
wire [31:0] rx_vldx ;
wire [`PHY_NUM*32-1:0] rx_datx ;
reg [31:0] rx_sel ;
genvar i ;
generate
for(i=0;i<`PHY_NUM;i=i+1) begin : G
rx_phy #(.MY_RXID(i)) rx_phy(
/*input */ .clk (clk ) ,
/*input */ .rst (rst ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input */ .reg_busy (reg_busy[i] ) ,
/*input */ .task_id_vld (task_id_vld&&rx_phy_sel[i] ) ,
/*input [31:0] */ .task_id_h (task_id_h ) ,
/*input [31:0] */ .task_id_l (task_id_l ) ,
/*input [31:0] */ .timer_cnt (timer_cnt[32*i+32-1:32*i] ) ,
/*output */ .rx_start (rx_start[i] ) ,
/*output */ .rx_last (rx_last[i] ) ,
/*output */ .rx_vld (rx_vldx[i] ) ,
/*output [31:0] */ .rx_dat (rx_datx[32*i+32-1:32*i] ) ,
/*input */ .RX_P (RX_P[i] ) ,
/*input */ .RX_N (RX_N[i] )
);
end
endgenerate
//--------------------------------------------
// RX.Select
//--------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush ) rx_sel <= 32'b0 ;
else if( |(rx_sel&rx_last) ) rx_sel <= 32'b0 ;//clear sel
else if( ~rx_almost_full && rx_start[0 ] ) rx_sel <= 32'b1<<0 ;
else if( ~rx_almost_full && rx_start[1 ] ) rx_sel <= 32'b1<<1 ;
else if( ~rx_almost_full && rx_start[2 ] ) rx_sel <= 32'b1<<2 ;
else if( ~rx_almost_full && rx_start[3 ] ) rx_sel <= 32'b1<<3 ;
else if( ~rx_almost_full && rx_start[4 ] ) rx_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~rx_almost_full && rx_start[5 ] ) rx_sel <= 32'b1<<5 ;
else if( ~rx_almost_full && rx_start[6 ] ) rx_sel <= 32'b1<<6 ;
else if( ~rx_almost_full && rx_start[7 ] ) rx_sel <= 32'b1<<7 ;
else if( ~rx_almost_full && rx_start[8 ] ) rx_sel <= 32'b1<<8 ;
else if( ~rx_almost_full && rx_start[9 ] ) rx_sel <= 32'b1<<9 ;
else if( ~rx_almost_full && rx_start[10] ) rx_sel <= 32'b1<<10 ;
else if( ~rx_almost_full && rx_start[11] ) rx_sel <= 32'b1<<11 ;
else if( ~rx_almost_full && rx_start[12] ) rx_sel <= 32'b1<<12 ;
else if( ~rx_almost_full && rx_start[13] ) rx_sel <= 32'b1<<13 ;
else if( ~rx_almost_full && rx_start[14] ) rx_sel <= 32'b1<<14 ;
else if( ~rx_almost_full && rx_start[15] ) rx_sel <= 32'b1<<15 ;
else if( ~rx_almost_full && rx_start[16] ) rx_sel <= 32'b1<<16 ;
else if( ~rx_almost_full && rx_start[17] ) rx_sel <= 32'b1<<17 ;
else if( ~rx_almost_full && rx_start[18] ) rx_sel <= 32'b1<<18 ;
else if( ~rx_almost_full && rx_start[19] ) rx_sel <= 32'b1<<19 ;
else if( ~rx_almost_full && rx_start[20] ) rx_sel <= 32'b1<<20 ;
else if( ~rx_almost_full && rx_start[21] ) rx_sel <= 32'b1<<21 ;
else if( ~rx_almost_full && rx_start[22] ) rx_sel <= 32'b1<<22 ;
else if( ~rx_almost_full && rx_start[23] ) rx_sel <= 32'b1<<23 ;
else if( ~rx_almost_full && rx_start[24] ) rx_sel <= 32'b1<<24 ;
else if( ~rx_almost_full && rx_start[25] ) rx_sel <= 32'b1<<25 ;
else if( ~rx_almost_full && rx_start[26] ) rx_sel <= 32'b1<<26 ;
else if( ~rx_almost_full && rx_start[27] ) rx_sel <= 32'b1<<27 ;
else if( ~rx_almost_full && rx_start[28] ) rx_sel <= 32'b1<<28 ;
else if( ~rx_almost_full && rx_start[29] ) rx_sel <= 32'b1<<29 ;
else if( ~rx_almost_full && rx_start[30] ) rx_sel <= 32'b1<<30 ;
else if( ~rx_almost_full && rx_start[31] ) rx_sel <= 32'b1<<31 ;
`endif
end
//--------------------------------------------
// RX.MUX
//--------------------------------------------
always @ ( posedge clk ) begin
if( rst )
rx_vld <= 1'b0 ;
else
rx_vld <= |rx_sel ;
rx_dat <= ({32{rx_sel[0 ]}} & rx_datx[32*1 -1:32*0 ])
| ({32{rx_sel[1 ]}} & rx_datx[32*2 -1:32*1 ])
| ({32{rx_sel[2 ]}} & rx_datx[32*3 -1:32*2 ])
| ({32{rx_sel[3 ]}} & rx_datx[32*4 -1:32*3 ])
| ({32{rx_sel[4 ]}} & rx_datx[32*5 -1:32*4 ])
`ifdef PHY_10
| ({32{rx_sel[5 ]}} & rx_datx[32*6 -1:32*5 ])
| ({32{rx_sel[6 ]}} & rx_datx[32*7 -1:32*6 ])
| ({32{rx_sel[7 ]}} & rx_datx[32*8 -1:32*7 ])
| ({32{rx_sel[8 ]}} & rx_datx[32*9 -1:32*8 ])
| ({32{rx_sel[9 ]}} & rx_datx[32*10-1:32*9 ])
| ({32{rx_sel[10]}} & rx_datx[32*11-1:32*10])
| ({32{rx_sel[11]}} & rx_datx[32*12-1:32*11])
| ({32{rx_sel[12]}} & rx_datx[32*13-1:32*12])
| ({32{rx_sel[13]}} & rx_datx[32*14-1:32*13])
| ({32{rx_sel[14]}} & rx_datx[32*15-1:32*14])
| ({32{rx_sel[15]}} & rx_datx[32*16-1:32*15])
| ({32{rx_sel[16]}} & rx_datx[32*17-1:32*16])
| ({32{rx_sel[17]}} & rx_datx[32*18-1:32*17])
| ({32{rx_sel[18]}} & rx_datx[32*19-1:32*18])
| ({32{rx_sel[19]}} & rx_datx[32*20-1:32*19])
| ({32{rx_sel[20]}} & rx_datx[32*21-1:32*20])
| ({32{rx_sel[21]}} & rx_datx[32*22-1:32*21])
| ({32{rx_sel[22]}} & rx_datx[32*23-1:32*22])
| ({32{rx_sel[23]}} & rx_datx[32*24-1:32*23])
| ({32{rx_sel[24]}} & rx_datx[32*25-1:32*24])
| ({32{rx_sel[25]}} & rx_datx[32*26-1:32*25])
| ({32{rx_sel[26]}} & rx_datx[32*27-1:32*26])
| ({32{rx_sel[27]}} & rx_datx[32*28-1:32*27])
| ({32{rx_sel[28]}} & rx_datx[32*29-1:32*28])
| ({32{rx_sel[29]}} & rx_datx[32*30-1:32*29])
| ({32{rx_sel[30]}} & rx_datx[32*31-1:32*30])
| ({32{rx_sel[31]}} & rx_datx[32*32-1:32*31])
`endif
;
end
endmodule |
module alink_slave(
// system clock and reset
input clk ,
input rst ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,//NC
input [2:0] ALINK_CTI_I ,//NC
input [1:0] ALINK_BTE_I ,//NC
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,//NC
output reg ALINK_ACK_O ,
output ALINK_ERR_O ,//const 0
output ALINK_RTY_O ,//const 0
output reg [31:0] ALINK_DAT_O ,
output reg txfifo_push ,
output reg [31:0] txfifo_din ,
input [9:0] rxcnt ,
input rxempty ,
input [10:0] txcnt ,
output reg_flush ,
input txfull ,
output reg [31:0] reg_mask ,
output reg reg_scan ,
input [31:0] busy ,
output rxfifo_pop ,
input [31:0] rxfifo_dout
);
parameter ALINK_TXFIFO = 6'h00 ;
parameter ALINK_STATE = 6'h04 ;
parameter ALINK_MASK = 6'h08 ;
parameter ALINK_BUSY = 6'h0c ;
parameter ALINK_RXFIFO = 6'h10 ;
//-----------------------------------------------------
// WB bus ACK
//-----------------------------------------------------
always @ ( posedge clk or posedge rst ) begin
if( rst )
ALINK_ACK_O <= 1'b0 ;
else if( ALINK_STB_I && (~ALINK_ACK_O) )
ALINK_ACK_O <= 1'b1 ;
else
ALINK_ACK_O <= 1'b0 ;
end
//-----------------------------------------------------
// ADDR MUX
//-----------------------------------------------------
wire alink_txfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_txfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_TXFIFO ) & ~ALINK_ACK_O ;
wire alink_state_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_state_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_STATE ) & ~ALINK_ACK_O ;
wire alink_mask_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_mask_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_MASK ) & ~ALINK_ACK_O ;
wire alink_busy_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_busy_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_BUSY ) & ~ALINK_ACK_O ;
wire alink_rxfifo_wr_en = ALINK_STB_I & ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
wire alink_rxfifo_rd_en = ALINK_STB_I & ~ALINK_WE_I & ( ALINK_ADR_I == ALINK_RXFIFO ) & ~ALINK_ACK_O ;
//-----------------------------------------------------
// Register.txfifo
//-----------------------------------------------------
always @ ( posedge clk ) begin
txfifo_push <= alink_txfifo_wr_en ;
txfifo_din <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.state
//-----------------------------------------------------
reg [3:0] reg_flush_r ;
wire [31:0] rd_state = {reg_scan,1'b0,rxcnt[9:0],3'b0,rxempty,
1'b0,txcnt[10:0],2'b0,reg_flush,txfull} ;
always @ ( posedge clk ) begin
if( alink_state_wr_en )
reg_flush_r <= {3'b0,ALINK_DAT_I[1]} ;
else
reg_flush_r <= reg_flush_r << 1 ;
end
always @ ( posedge clk ) begin
if( rst )
reg_scan <= 1'b0 ;
else if( alink_state_wr_en )
reg_scan <= ALINK_DAT_I[31] ;
end
assign reg_flush = |reg_flush_r ;
//-----------------------------------------------------
// Register.mask
//-----------------------------------------------------
always @ ( posedge clk ) begin
if( alink_mask_wr_en )
reg_mask <= ALINK_DAT_I ;
end
//-----------------------------------------------------
// Register.busy
//-----------------------------------------------------
wire [31:0] rd_busy = busy[31:0] ;
//-----------------------------------------------------
// Register.rxfifo
//-----------------------------------------------------
wire [31:0] rd_rxfifo = rxfifo_dout[31:0] ;
//-----------------------------------------------------
// WB read
//-----------------------------------------------------
assign rxfifo_pop = alink_rxfifo_rd_en ;
always @ ( posedge clk ) begin
case( 1'b1 )
alink_state_rd_en : ALINK_DAT_O <= rd_state ;
alink_busy_rd_en : ALINK_DAT_O <= rd_busy ;
alink_rxfifo_rd_en : ALINK_DAT_O <= rd_rxfifo ;
default: ALINK_DAT_O <= 32'hdeaddead ;
endcase
end
endmodule |
module tx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_scan ,
input tx_phy_start ,
input [31:0] tx_phy_sel ,
output tx_phy_done ,
input [31:0] tx_dout ,//TxFIFO data input
output tx_rd_en ,//TxFIFO pop
output reg task_id_vld ,
output reg [31:0] rx_phy_sel ,
output reg [31:0] task_id_h ,
output reg [31:0] task_id_l ,
output reg [31:0] reg_tout ,
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N
);
/*
__
tx_phy_start _____| |_____________________________________
_____ __ _____________________________________
tx_phy_sel _____|0 |_________________dont care___________
__
tx_phy_done ________________________________________| |__
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[rx_phy_sel _________________|0_|_________________________
task_id_h
task_id_l]
*/
parameter IDLE = 2'd0 ;
parameter TASK = 2'd1 ;
parameter HASH = 2'd2 ;
parameter NONCE= 2'd3 ;
//----------------------------------------------
// Alink.clock.tick
//----------------------------------------------
reg [2:0] cur_state ;
reg [2:0] nxt_state ;
reg [4:0] word_cnt ;
reg [3:0] timing_cnt ;
reg hash_pop ;
reg [31:0] tx_buf_flg ;
reg [31:0] tx_buf ;
reg [2:0] tx_rd_en_cnt ;
reg [31:0] reg_step ;
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
tx_rd_en_cnt <= 3'b0 ;
else if( tx_rd_en && cur_state == TASK )
tx_rd_en_cnt <= tx_rd_en_cnt + 3'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
timing_cnt <= 4'b0 ;
else if( timing_cnt == `TX_PHY_TIMING )
timing_cnt <= 4'b0 ;
else if( cur_state == HASH || cur_state == NONCE )
timing_cnt <= timing_cnt + 4'b1 ;
else
timing_cnt <= 4'b0 ;
end
wire tick = ( timing_cnt == `TX_PHY_TIMING ) ;
reg nonce_over_flow ;
//----------------------------------------------
// FSM
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE : if( tx_phy_start ) nxt_state = TASK ;
TASK : if( tx_rd_en_cnt == `TX_TASKID_LEN-1 ) nxt_state = HASH ;
HASH : if( word_cnt == `TX_DATA_LEN-1 && ~|tx_buf_flg ) nxt_state = NONCE ;
NONCE: if( nonce_over_flow&&tick ) nxt_state = IDLE ;
endcase
end
assign tx_phy_done = (cur_state == NONCE)&&(nxt_state == IDLE) ;
//----------------------------------------------
// TASK.ID
//----------------------------------------------
always @ ( posedge clk ) begin
if( cur_state == IDLE && nxt_state == TASK ) begin
rx_phy_sel <= tx_phy_sel ;
end
if( cur_state == TASK && tx_rd_en_cnt == 2'd0 ) task_id_h <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd1 ) task_id_l <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd2 ) reg_step <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd3 ) reg_tout <= tx_dout ;
if( rst )
task_id_vld <= 1'b0 ;
else if( cur_state == TASK && nxt_state == HASH )
task_id_vld <= 1'b1 ;
else
task_id_vld <= 1'b0 ;
end
wire [31:0] scan_nonce = task_id_l ;
wire [7:0] scan_no = task_id_h[7:0] ;
reg [7:0] scan_cnt ;
//----------------------------------------------
// Shifter
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
word_cnt <= 5'b0 ;
else if( cur_state == HASH && ~|tx_buf_flg )
word_cnt <= word_cnt + 5'b1 ;
end
assign tx_rd_en = ( cur_state == TASK ) || ( hash_pop ) ;
reg TX_Px ;
reg TX_Nx ;
always @ ( posedge clk or posedge rst ) begin
if( rst || (cur_state == NONCE && nxt_state == IDLE) || reg_flush ) begin
TX_Px <= 1'b1 ;
TX_Nx <= 1'b1 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin //START
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end else if( cur_state == HASH || cur_state == NONCE ) begin
if( ~TX_Px && ~TX_Nx && tick ) begin
TX_Px <= tx_buf[0]?1'b1:1'b0 ;
TX_Nx <= (~tx_buf[0])?1'b1:1'b0 ;
end else if( tick ) begin
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end
end
end
genvar i;
generate
for(i = 0; i < `PHY_NUM; i = i + 1) begin
assign {TX_P[i],TX_N[i]} = rx_phy_sel[i] ? {TX_Px,TX_Nx} : 2'b11 ;
end
endgenerate
reg [32:0] nonce_buf ;
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
hash_pop <= 1'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == TASK && nxt_state == HASH ) begin
hash_pop <= 1'b1 ;
end else if( cur_state == HASH && nxt_state != NONCE && ~|tx_buf_flg ) begin
hash_pop <= 1'b1 ;
end else begin
hash_pop <= 1'b0 ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
tx_buf <= 32'b0 ;
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf <= {1'b0,tx_buf[31:1]} ;
end else if( hash_pop ) begin
tx_buf <= tx_dout ;
end else if( cur_state == HASH && nxt_state == NONCE ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | 32'b0 ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
scan_cnt <= reg_scan + scan_cnt ;
end else if( cur_state == NONCE && ~|tx_buf_flg ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | nonce_buf[31:0] ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
nonce_over_flow <= ((nonce_buf)>33'hffff_ffff) ? 1'b1:1'b0 ;
scan_cnt <= reg_scan + scan_cnt ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst || cur_state == IDLE ) begin
tx_buf_flg <= 32'hffffffff ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf_flg <= {1'b0,tx_buf_flg[31:1]} ;
end else if( (cur_state == HASH || cur_state == NONCE) && ~|tx_buf_flg ) begin
tx_buf_flg <= 32'hffffffff ;
end
end
endmodule |
module txc(
input clk ,
input rst ,
input reg_flush ,
input [`PHY_NUM-1:0] reg_mask ,
input task_id_vld ,
input [31:0] reg_tout ,
input tx_task_vld ,//tx fifo not empty
output tx_phy_start,
output reg [`PHY_NUM-1:0]tx_phy_sel ,
input tx_phy_done ,
output reg [1:0] cur_state ,
output reg [1:0] nxt_state ,
output [32*`PHY_NUM-1:0] timer_cnt ,//to slave
output [`PHY_NUM-1:0] reg_busy
);
parameter IDLE = 2'b00 ;
parameter REQ = 2'b01 ;
parameter SENT = 2'b10 ;
wire [`PHY_NUM-1:0] timer_start ;
wire [`PHY_NUM-1:0] timer_busy ;
assign tx_phy_start = cur_state == REQ && nxt_state == SENT ;
//----------------------------------------------
// Timer
//----------------------------------------------
genvar i ;
generate
for( i=0 ; i < `PHY_NUM ; i = i + 1 ) begin : G
assign timer_start[i] = task_id_vld & tx_phy_sel[i] ;
tx_timer tx_timer(
/*input */ .clk (clk ) ,
/*input */ .rst (rst ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [31:0] */ .reg_tout (reg_tout ) ,
/*input */ .timer_start (timer_start[i] ) ,
/*output */ .timer_busy (timer_busy[i] ) ,
/*output reg [31:0]*/ .timer_cnt (timer_cnt[i*32+32-1:i*32] )
);
assign reg_busy[i] = timer_start[i] | timer_busy[i] ;
end
endgenerate
//----------------------------------------------
// State Machine
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE: if( |tx_phy_sel ) nxt_state = REQ ;
REQ : if( tx_task_vld ) nxt_state = SENT ;
SENT: if( tx_phy_done ) nxt_state = IDLE ;
default : nxt_state = IDLE ;
endcase
end
//----------------------------------------------
// Arbiter
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush || (cur_state == SENT && nxt_state == IDLE))
tx_phy_sel <= 32'b0 ;
else if( cur_state == IDLE ) begin
if( ~reg_busy[0 ]&®_mask[0 ] ) tx_phy_sel <= 32'b1<<0 ;
else if( ~reg_busy[1 ]&®_mask[1 ] ) tx_phy_sel <= 32'b1<<1 ;
else if( ~reg_busy[2 ]&®_mask[2 ] ) tx_phy_sel <= 32'b1<<2 ;
else if( ~reg_busy[3 ]&®_mask[3 ] ) tx_phy_sel <= 32'b1<<3 ;
else if( ~reg_busy[4 ]&®_mask[4 ] ) tx_phy_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~reg_busy[5 ]&®_mask[5 ] ) tx_phy_sel <= 32'b1<<5 ;
else if( ~reg_busy[6 ]&®_mask[6 ] ) tx_phy_sel <= 32'b1<<6 ;
else if( ~reg_busy[7 ]&®_mask[7 ] ) tx_phy_sel <= 32'b1<<7 ;
else if( ~reg_busy[8 ]&®_mask[8 ] ) tx_phy_sel <= 32'b1<<8 ;
else if( ~reg_busy[9 ]&®_mask[9 ] ) tx_phy_sel <= 32'b1<<9 ;
else if( ~reg_busy[10]&®_mask[10] ) tx_phy_sel <= 32'b1<<10 ;
else if( ~reg_busy[11]&®_mask[11] ) tx_phy_sel <= 32'b1<<11 ;
else if( ~reg_busy[12]&®_mask[12] ) tx_phy_sel <= 32'b1<<12 ;
else if( ~reg_busy[13]&®_mask[13] ) tx_phy_sel <= 32'b1<<13 ;
else if( ~reg_busy[14]&®_mask[14] ) tx_phy_sel <= 32'b1<<14 ;
else if( ~reg_busy[15]&®_mask[15] ) tx_phy_sel <= 32'b1<<15 ;
else if( ~reg_busy[16]&®_mask[16] ) tx_phy_sel <= 32'b1<<16 ;
else if( ~reg_busy[17]&®_mask[17] ) tx_phy_sel <= 32'b1<<17 ;
else if( ~reg_busy[18]&®_mask[18] ) tx_phy_sel <= 32'b1<<18 ;
else if( ~reg_busy[19]&®_mask[19] ) tx_phy_sel <= 32'b1<<19 ;
else if( ~reg_busy[20]&®_mask[20] ) tx_phy_sel <= 32'b1<<20 ;
else if( ~reg_busy[21]&®_mask[21] ) tx_phy_sel <= 32'b1<<21 ;
else if( ~reg_busy[22]&®_mask[22] ) tx_phy_sel <= 32'b1<<22 ;
else if( ~reg_busy[23]&®_mask[23] ) tx_phy_sel <= 32'b1<<23 ;
else if( ~reg_busy[24]&®_mask[24] ) tx_phy_sel <= 32'b1<<24 ;
else if( ~reg_busy[25]&®_mask[25] ) tx_phy_sel <= 32'b1<<25 ;
else if( ~reg_busy[26]&®_mask[26] ) tx_phy_sel <= 32'b1<<26 ;
else if( ~reg_busy[27]&®_mask[27] ) tx_phy_sel <= 32'b1<<27 ;
else if( ~reg_busy[28]&®_mask[28] ) tx_phy_sel <= 32'b1<<28 ;
else if( ~reg_busy[29]&®_mask[29] ) tx_phy_sel <= 32'b1<<29 ;
else if( ~reg_busy[30]&®_mask[30] ) tx_phy_sel <= 32'b1<<30 ;
else if( ~reg_busy[31]&®_mask[31] ) tx_phy_sel <= 32'b1<<31 ;
`endif
else tx_phy_sel <= 32'b0 ;
end
end
endmodule |
module twi_core (
input clk ,
input rst ,
input wr , //we
input [7:0] data_in,//dat1
input [7:0] wr_addr,//adr1
output [7:0] i2cr ,
output [7:0] i2rd ,
output twi_scl_o ,
input twi_sda_i ,
output twi_sda_oen
);
parameter TWI_F = 3 ;
parameter START_SDA = 600/TWI_F+1 ;
parameter SDA_SET = 700/TWI_F+1 ;
parameter SDA_WAIT = 600/TWI_F+1 ;
parameter START_SCL = START_SDA+100/TWI_F+1 ;
parameter TWI_DONE = START_SCL+1300/TWI_F+1 ;
parameter STOP_SCL = 100/TWI_F+1 ;
reg [7:0] rd_buf ;
reg [11:0] cnt ;
reg done ;
reg [3:0] byte_cnt ;
reg [7:0] i2wd_r ;
reg [7:0] i2rd_r ;
assign i2wd = i2wd_r ;
assign i2rd = rd_buf ;
reg en_r , init_r ;
reg [2:0] cmd_r ;
wire cmd_start = cmd_r == 3'b000 && en_r ;
wire cmd_wr = cmd_r == 3'b001 && en_r ;
wire cmd_rd = cmd_r == 3'b010 && en_r ;
wire cmd_stop = cmd_r == 3'b011 && en_r ;
wire cmd_rd_no = cmd_r == 3'b100 && en_r ;
assign i2cr = {1'b0,cmd_r,1'b0,done,init_r,en_r};
//register twir
always @ ( posedge clk ) begin
if( rst ) begin
en_r <= 1'b0 ;
init_r <= 1'b0 ;
cmd_r <= 3'b0 ;
end
else if( wr_addr == `I2CR && wr ) begin
en_r <= data_in[0] ;
init_r <= data_in[1] ;
cmd_r <= data_in[6:4] ;
end
else begin
init_r <= 1'b0 ;
end
end
always @ ( posedge clk ) begin
if( rst )
i2wd_r <= 8'b0 ;
else if( wr_addr == `I2WD && wr )
i2wd_r <= data_in ;
else if( cmd_wr && cnt == (SDA_SET*2+SDA_WAIT) )
i2wd_r <= {i2wd_r[6:0],1'b1};
end
always @ ( posedge clk ) begin
if( rst )
done <= 1'b0 ;
else if( wr_addr == `I2CR && wr )
done <= data_in[2] ;
else if( init_r )
done <= 1'b0 ;
else if( (cmd_start || cmd_stop ) && cnt == TWI_DONE )
done <= 1'b1 ;
else if( (cmd_wr || cmd_rd) && byte_cnt == 9 )
done <= 1'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
byte_cnt <= 4'b0 ;
else if( init_r )
byte_cnt <= 4'b0 ;
else if( (cmd_wr || cmd_rd) && (cnt == (SDA_SET*2+SDA_WAIT)) )
byte_cnt <= byte_cnt + 4'b1 ;
end
always @ ( posedge clk ) begin
if( rst || ~en_r )
cnt <= 12'b0 ;
else if( (cmd_start || cmd_stop ) && init_r )
cnt <= 12'b1 ;
else if( (cmd_start || cmd_stop ) && cnt != 0 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && init_r )
cnt <= 12'b0 ;
else if( (cmd_wr || cmd_rd) && cnt < (SDA_SET*2+SDA_WAIT) && byte_cnt < 9 )
cnt <= cnt + 12'b1 ;
else if( (cmd_wr || cmd_rd) && cnt == (SDA_SET*2+SDA_WAIT) )
cnt <= 12'b0 ;
end
reg scl_o ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
scl_o <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SCL )
scl_o <= 1'b0 ;
end
else if( cmd_wr || cmd_rd ) begin
scl_o <= cnt == 12'b0 ? 1'b0 :
cnt == SDA_SET ? 1'b1 :
cnt == (SDA_SET+SDA_WAIT) ? 1'b0 : scl_o ;
end
else if( cmd_stop && cnt == SDA_SET ) begin
scl_o <= 1'b1 ;
end
end
reg sda_oen ;
always @ ( posedge clk ) begin
if( rst || ~en_r ) begin
sda_oen <= 1'b1 ;
end
else if( cmd_start ) begin
if( cnt == START_SDA )
sda_oen <= 1'b0 ;
end
else if( cmd_wr ) begin
sda_oen <= i2wd_r[7] ;
end
else if( cmd_rd ) begin
if( byte_cnt == 8 || byte_cnt == 9)
sda_oen <= 1'b0 ;//master read ack
else
sda_oen <= 1'b1 ;
end
else if( cmd_stop ) begin
if( init_r )
sda_oen <= 1'b0 ;
else if( cnt == STOP_SCL+SDA_SET )
sda_oen <= 1'b1 ;
end
else if( cmd_rd_no ) begin
sda_oen <= 1'b1 ;//master read no ack
end
end
always @ ( posedge clk ) begin
if( rst )
rd_buf <= 8'b0 ;
else if( cmd_rd && cnt == (SDA_SET+100) && byte_cnt <=7)
rd_buf <= {rd_buf[6:0],twi_sda_i} ;
end
assign twi_scl_o = scl_o ;
assign twi_sda_oen = sda_oen ;
endmodule |
module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
);
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
//--------------------------------------------------
// shcp counter
//--------------------------------------------------
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
//--------------------------------------------------
// sft_stcp
//--------------------------------------------------
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
//--------------------------------------------------
// done
//--------------------------------------------------
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule |
module adc_clkgen_with_edgedetect(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input wire ena_in, // enable signal from the digital clock core. 0 halts the self-clocked loop
input wire start_conv_in, // triggers a conversion once with edge-detection
input wire ndecision_finish_in, // comparator signalizes finished conversion
output wire clk_dig_out, // digital clock
output wire clk_comp_out, // comparator clock
input wire enable_dlycontrol_in, // 0 = max delays, 1 = configurable delays
input wire [4:0] dlycontrol1_in, // delay 1 of 3 in loop. Delay = 5ns*dlycontrol1
input wire [4:0] dlycontrol2_in, // delay 2 of 3 in loop. Delay = 5ns*dlycontrol2
input wire [4:0] dlycontrol3_in, // delay 3 of 3 in loop. Delay = 5ns*dlycontrol3
input wire [5:0] dlycontrol4_in, // edge detect pulse width. Delay = 5ns*dlycontrol4
// additional buffers for sample matrix
input wire sample_p_in,
input wire sample_n_in,
output wire sample_p_out,
output wire sample_n_out
);
endmodule |
module scboundary(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS // User area ground
`endif
);
endmodule |
module adc_array_matrix_12bit (
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input vcm,
input sample,sample_n,
input [15:0] row_n,
input [15:0] rowon_n,
input [15:0] rowoff_n,
input [31:0] col_n,
input [31:0] col,
input [2:0] en_bit_n,
input en_C0_n,
input sw, sw_n, analog_in,
output ctop);
endmodule |
module adc_vcm_generator(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
output vcm,
input wire clk
);
endmodule |
module adc_comp_latch(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input wire clk,
input wire inp,
input wire inn,
output wire comp_trig,
output wire latch_qn,
output wire latch_q
);
endmodule |
module adc_clkgen_with_edgedetect(
input wire ena_in, // enable signal from the digital clock core. 0 halts the self-clocked loop
input wire start_conv, // triggers a conversion once with edge-detection
input wire ndecision_finish, // comparator signalizes finished conversion
output wire clk_dig, // digital clock
output wire clk_comp, // comparator clock
input wire enable_dlycontrol, // 0 = max delays, 1 = configurable delays
input wire [4:0] dlycontrol1, // delay 1 of 3 in loop
input wire [4:0] dlycontrol2, // delay 2 of 3 in loop
input wire [4:0] dlycontrol3, // delay 3 of 3 in loop
input wire [5:0] dlycontrol4, // edge detect pulse width
input wire sample_p, // sample signals for matrix using additional buffers
input wire sample_n,
input wire nsample_p,
input wire nsample_n,
output wire sample_p_buf,
output wire sample_n_buf,
output wire nsample_p_buf,
output wire nsample_n_buf
);
wire _enable_loop_;
wire _ena_in_buffered_;
wire _start_conv_buffered_;
wire _ndecision_finish_buffered_;
wire _clk_dig_unbuffered_;
wire _clk_comp_unbuffered_;
//Input buffers
sky130_fd_sc_hd__buf_1 inbuf_1 (.A(ena_in),.X(_ena_in_buffered_));
sky130_fd_sc_hd__buf_1 inbuf_2 (.A(start_conv),.X(_start_conv_buffered_));
sky130_fd_sc_hd__buf_1 inbuf_3 (.A(ndecision_finish),.X(_ndecision_finish_buffered_));
//Output buffers
sky130_fd_sc_hd__buf_4 outbuf_1 (.A(_clk_dig_unbuffered_),.X(clk_dig));
sky130_fd_sc_hd__buf_4 outbuf_2 (.A(_clk_comp_unbuffered_),.X(clk_comp));
// Output buffers for integrated sample-signal-buffeing
sky130_fd_sc_hd__buf_4 outbuf_3 (.A(sample_p),.X(sample_p_buf));
sky130_fd_sc_hd__buf_4 outbuf_4 (.A(sample_n),.X(sample_n_buf));
sky130_fd_sc_hd__buf_4 outbuf_5 (.A(nsample_p),.X(nsample_p_buf));
sky130_fd_sc_hd__buf_4 outbuf_6 (.A(nsample_n),.X(nsample_n_buf));
//Circuit
adc_edge_detect_circuit edgedetect (.start_conv(_start_conv_buffered_),
.ena_in(_ena_in_buffered_),
.ena_out(_enable_loop_),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol(dlycontrol4));
adc_clk_generation clkgen (.ndecision_finish(_ndecision_finish_buffered_),
.enable_loop(_enable_loop_),
.clk_dig(_clk_dig_unbuffered_),
.clk_comp(_clk_comp_unbuffered_),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol1(dlycontrol1),
.dlycontrol2(dlycontrol2),
.dlycontrol3(dlycontrol3));
endmodule |
module adc_clk_generation(
input wire ndecision_finish, // 0 = comparator finished
input wire enable_loop, // 1 = self clocked loop enabled
output wire clk_dig, // clk for digital core
output wire clk_comp, // clk for comparator
input wire enable_dlycontrol, // 0 = max delays, 1 = configured delays
input wire [4:0] dlycontrol1, // delay1 = N times 5ns up to 100ns
input wire [4:0] dlycontrol2, // delay2 = N times 5ns up to 100ns
input wire [4:0] dlycontrol3 // delay3 = N times 5ns up to 100ns
);
wire _ndecision_finish_delayed_;
wire _clk_dig_delayed_;
wire _net_1_;
delaycell #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_1
(
.in(ndecision_finish),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol(dlycontrol1),
.out(_ndecision_finish_delayed_)
);
assign clk_dig = ~_ndecision_finish_delayed_;
delaycell #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_2
(
.in(clk_dig),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol(dlycontrol2),
.out(_clk_dig_delayed_)
);
nand(_net_1_,_clk_dig_delayed_,~enable_loop);
delaycell #(.Ntimes5ns(20), .ctrlport_width(5)) delay_100ns_3
(
.in(_net_1_),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol(dlycontrol3),
.out(clk_comp)
);
endmodule |
module adc_edge_detect_circuit(
input wire start_conv, // Tell the ADC to start a conversion
input wire ena_in, // signal from the digital core to enable the self-clocked-loop
output wire ena_out, // enable the self-clocked-loop
input wire enable_dlycontrol, // 0 = max delays, 1 = configured delays
input wire [5:0] dlycontrol // delay = N times 5ns up to 200ns
);
// Internal wires
wire _start_conv_delayed_;
wire _start_conv_edge_;
//combinatoric process
delaycell #(.Ntimes5ns(40), .ctrlport_width(6)) dly200cell
(
.in(start_conv),
.enable_dlycontrol(enable_dlycontrol),
.dlycontrol(dlycontrol),
.out(_start_conv_delayed_)
);
nor(_start_conv_edge_,~start_conv,_start_conv_delayed_);
or(ena_out,_start_conv_edge_,ena_in);
endmodule |
module delaycell #(parameter Ntimes5ns = 20, parameter ctrlport_width = 5)
(
input wire in,
input wire enable_dlycontrol,
input wire [ctrlport_width-1:0] dlycontrol,
output wire out
);
// Conversion from binary (dlycontrol)
// to inverted thermo-code (_bypass_)
// with enable
wire [Ntimes5ns-1:0] _bypass_ = enable_dlycontrol ? {Ntimes5ns{1'b1}}<<dlycontrol : {Ntimes5ns{1'b1}};
// Generate delaycell with bypass function
// ___________ bypass[j]
// _____ | | |-------\
// bypass[j]--o| AND |--sigb[j]--| Delay 5ns |----sigc[j]---|0 mux |--sigd[j]--
// siga[j]-.--|_____| |___________| .--siga[j]-|1______/
// \__________________________________/
//
wire [Ntimes5ns-1:0] _siga_;
wire [Ntimes5ns-1:0] _sigb_;
wire [Ntimes5ns-1:0] _sigc_;
wire [Ntimes5ns-1:0] _sigd_;
genvar j;
generate
for(j=0;j<Ntimes5ns;j=j+1) begin
sky130_fd_sc_hd__and2_1 and1 (.A(~_bypass_[j]),.B(_siga_[j]),.X(_sigb_[j]));
sky130_mm_sc_hd_dlyPoly5ns delay_unit (.in(_sigb_[j]), .out(_sigc_[j]));
sky130_fd_sc_hd__mux2_1 mux1 (.A0(_sigc_[j]),.A1(_siga_[j]),.S( _bypass_[j]),.X(_sigd_[j]));
assign _siga_[j] = (j==0) ? in : _sigd_[j-1];
end
assign out = _sigd_[Ntimes5ns-1];
endgenerate
endmodule |
module adc_control_nonbinary #(parameter MATRIX_BITS = 12, NONBINARY_REDUNDANCY = 3)(
input wire clk,
input wire rst_n,
input wire comparator_in,
input wire [2:0] avg_control_in,
output wire sample_out,
output wire sample_out_n,
output wire enable_loop_out,
output wire conv_finished_strobe_out,
output wire[MATRIX_BITS-1:0] pswitch_out,
output wire[MATRIX_BITS-1:0] nswitch_out,
output reg[MATRIX_BITS-1:0] result_out
);
// combinatoric signals for next register values
wire [MATRIX_BITS-1:0] next_result_w;
wire [4:0] next_average_counter_w;
wire [4:0] next_average_sum_w;
wire [2:0] next_sampled_avg_control_w;
wire [MATRIX_BITS+NONBINARY_REDUNDANCY+1:0] next_shift_register_w;
wire [MATRIX_BITS-1:0] next_data_register_w;
// Average calculation of comparator_in at LSB-region
reg [4:0] average_counter_r;
reg [4:0] average_sum_r;
reg [2:0] sampled_avg_control_r;
wire [4:0] average_count_limit_w;
wire averaged_comparator_in_w;
wire lsb_region_w = (shift_register_r[2] | shift_register_r[3] | shift_register_r[4] | shift_register_r[5]);
wire is_averaging_w = (lsb_region_w && (average_counter_r < average_count_limit_w));
// State-Machine Shift Register
reg [MATRIX_BITS+NONBINARY_REDUNDANCY+1:0] shift_register_r;
reg [MATRIX_BITS-1:0] data_register_r;
wire [MATRIX_BITS-1:0] nonbinary_value_w;
// State machine states
wire is_holding_result_w = shift_register_r[1];
wire is_sampling_w = shift_register_r[0];
wire result_ready_w = ((shift_register_r[2]==1'b1)&~is_averaging_w);
wire result_strobe_w = ((shift_register_r[1]==1'b1)&~is_averaging_w);
/*
*************************************************
//wire hold_data_for_osr = shift_register_r[1];
*************************************************
OSR uses the data-valid strobe as clock-signal for low power,
which can lead to unpredictable problems.
expected:
data_in XXXXX__data___XXXX
data_valid _____/‾‾‾‾‾‾\_____
data_valid_clk ____________/‾‾\__
Possible problem:
data_in XXXXX__data___XXXXXX
data_valid _____/‾‾‾‾‾‾\_______
data_valid_clk ______________/‾‾\__ Clock is delayed
Solution: Data at OSR input is held for two clock cycles
data_in XXXXX__data_________XXXXXX
data_valid _____/‾‾‾‾‾‾\_______
data_valid_clk ______________/‾‾\__ Clock can have delay
*/
// conversion finished set 0 after reset, 1 after conversion ended
wire next_conv_finished_w = result_strobe_w;
reg conv_finished_r;
//******************************************
// Synchronous process and Reset Handling
//******************************************
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) begin
result_out <= {MATRIX_BITS{1'b0}};
shift_register_r <= {{(MATRIX_BITS+NONBINARY_REDUNDANCY+1){1'b0}},1'b1};
sampled_avg_control_r <= 3'b000;
average_counter_r <= 5'd1;
average_sum_r <= 5'd0;
data_register_r <= 12'd2048;
conv_finished_r <= 1'b0;
end
else begin
result_out <= next_result_w;
shift_register_r <= next_shift_register_w;
sampled_avg_control_r <= next_sampled_avg_control_w;
average_counter_r <= next_average_counter_w;
average_sum_r <= next_average_sum_w;
data_register_r <= next_data_register_w;
conv_finished_r <= next_conv_finished_w;
end
end
//*******************************
// Combinatorial Processes
//*******************************
// direct output values determined from internal registers
assign sample_out = is_sampling_w;
assign sample_out_n = ~is_sampling_w;
assign conv_finished_strobe_out = conv_finished_r;
assign enable_loop_out = ~is_sampling_w;
assign pswitch_out = ~data_register_r;
assign nswitch_out = data_register_r;
// shift register and data handling
// save avg_control in a register to prevent changes of this value during conversion
assign next_shift_register_w = is_averaging_w ? shift_register_r : {shift_register_r[0],shift_register_r[MATRIX_BITS+NONBINARY_REDUNDANCY+1:1]};
assign next_sampled_avg_control_w = is_sampling_w ? avg_control_in : sampled_avg_control_r;
wire [MATRIX_BITS-1:0] sar_up = data_register_r+nonbinary_value_w;
wire [MATRIX_BITS-1:0] sar_down = data_register_r-nonbinary_value_w;
assign next_data_register_w = is_sampling_w | is_holding_result_w | result_ready_w ? 12'd2048 :
is_averaging_w ? data_register_r :
averaged_comparator_in_w ? sar_up : sar_down ;
// update the result at end of conversion
//assign next_result_w = result_ready_w ? next_data_register_w : result_out;
assign next_result_w = (result_ready_w & averaged_comparator_in_w) ? data_register_r :
(result_ready_w & ~averaged_comparator_in_w) ? data_register_r-1 :
result_out;
// Get the comparator_in average value.
// Sum up comparator_in while in LSB region.
// Afterwards the result in average_sum is evaluated.
assign next_average_counter_w = is_averaging_w ? average_counter_r+1 : 5'd1;
assign next_average_sum_w = is_averaging_w ? average_sum_r+{4'b0,comparator_in} : {4'b0, comparator_in};
assign averaged_comparator_in_w = (~lsb_region_w) ? comparator_in :
is_averaging_w ? 1'b0 :
(average_count_limit_w == 5'd3) ? average_sum_r[1] :
(average_count_limit_w == 5'd7) ? average_sum_r[2] :
(average_count_limit_w == 5'd15) ? average_sum_r[3] :
(average_count_limit_w == 5'd31) ? average_sum_r[4] :
comparator_in;
//*******************************
// NONBINARY Lookup table
//*******************************
// calculated for 12 Bit Matrix + 3 redundant Bits
assign nonbinary_value_w = (shift_register_r==17'd2**16) ? 12'd806 :
(shift_register_r==17'd2**15) ? 12'd486 :
(shift_register_r==17'd2**14) ? 12'd295 :
(shift_register_r==17'd2**13) ? 12'd180 :
(shift_register_r==17'd2**12) ? 12'd110 :
(shift_register_r==17'd2**11) ? 12'd67 :
(shift_register_r==17'd2**10) ? 12'd41 :
(shift_register_r==17'd2**9 ) ? 12'd25 :
(shift_register_r==17'd2**8 ) ? 12'd15 :
(shift_register_r==17'd2**7 ) ? 12'd9 :
(shift_register_r==17'd2**6 ) ? 12'd6 :
(shift_register_r==17'd2**5 ) ? 12'd4 :
(shift_register_r==17'd2**4 ) ? 12'd2 :
(shift_register_r==17'd2**3 ) ? 12'd1 :
(shift_register_r==17'd2**2 ) ? 12'd0 :
(shift_register_r==17'd2**1 ) ? 12'd0 :
(shift_register_r==17'd2**0 ) ? 12'd0 :
12'dX; // default signal for illegal state
//*******************************
// AVERAGING lookup table
//*******************************
// Amount of measurements to average comparator_in at LSB_region
assign average_count_limit_w = (sampled_avg_control_r == 3'b001) ? 5'd3 :
(sampled_avg_control_r == 3'b010) ? 5'd7 :
(sampled_avg_control_r == 3'b011) ? 5'd15 :
(sampled_avg_control_r == 3'b100) ? 5'd31 :
5'd1;
endmodule |
module adc_osr (
input wire rst_n,
input wire data_valid_strobe,
input wire [2:0] osr_mode_in,
input wire [11:0] data_in,
output wire [15:0] data_out,
output wire conversion_finished_osr_out
);
// internal registers
reg [19:0] result_r;
reg [2:0] osr_mode_r;
reg [8:0] sample_count_r;
reg [15:0] output_r;
reg data_valid_r;
// combinatoric signals for next register values
wire [19:0] next_result_w;
wire [2:0] next_osr_mode_w;
wire [8:0] next_sample_count_w;
wire [15:0] next_output_w;
// Direct signals
assign conversion_finished_osr_out = data_valid_r & data_valid_strobe;
//******************************************
// data_valid_strobe as clock input
//******************************************
// Cave: Handle with care, normally you should
// only use one clk-signal to guarantee synchronous
// execution without problems
always @(posedge data_valid_strobe, negedge rst_n) begin
if (rst_n == 1'b0) begin
result_r <= 20'd0;
osr_mode_r <= 3'd0;
sample_count_r <= 9'd1;
output_r <= 16'd0;
data_valid_r <= 1'b0;
end
else begin
result_r <= next_result_w;
osr_mode_r <= next_osr_mode_w;
sample_count_r <= next_sample_count_w;
output_r <= next_output_w;
data_valid_r <= next_data_valid_w;
end
end
wire next_data_valid_w = is_last_sample;
//*******************************
// State flags
//*******************************
wire bypass_oversampling = ~(osr_mode_in[0] | osr_mode_in[1] | osr_mode_in==3'b100);
wire is_first_sample = bypass_oversampling | (sample_count_r == 9'd1);
wire is_last_sample = bypass_oversampling | ((sample_count_r == osr_count_limit_w)&&(~is_first_sample));
//*******************************
// Combinatoric signals
//*******************************
assign next_result_w = is_first_sample ? {8'd0,data_in} :
{8'd0,data_in} + result_r;
assign next_osr_mode_w = is_first_sample ? osr_mode_in : osr_mode_r;
assign next_sample_count_w = is_last_sample ? 1 : sample_count_r + 1;
//***********************************************
// Output right-shifted result
//***********************************************
assign data_out = output_r;
assign next_output_w = bypass_oversampling ? {next_result_w[11:0],4'b0} :
~is_last_sample ? output_r :
(osr_mode_r == 3'b001) ? {next_result_w[13:1],3'b0} :
(osr_mode_r == 3'b010) ? {next_result_w[15:2],2'b0} :
(osr_mode_r == 3'b011) ? {next_result_w[17:3],1'b0} :
(osr_mode_r == 3'b100) ? {next_result_w[19:4]} :
16'bX;
//***********************************************
// OSR mode lookup table
// mode 001 = 4 samples +1 Bit resolution
// mode 010 = 16 samples +2 Bit resolution
// mode 011 = 64 samples +3 Bit resolution
// mode 100 = 256 samples +4 Bit resolution
//***********************************************
// Amount of oversampling samples (+N Bit SNR per N*4 samples)
wire [8:0] osr_count_limit_w = (osr_mode_r == 3'b001) ? 9'd4 :
(osr_mode_r == 3'b010) ? 9'd16 :
(osr_mode_r == 3'b011) ? 9'd64 :
(osr_mode_r == 3'b100) ? 9'd256 :
9'd1;
endmodule |
module adc_row_col_decoder(
input wire[11:0] data_in,
input wire row_mode,
input wire col_mode,
output wire[15:0] row_out_n,
output wire[15:0] rowon_out_n,
output wire[15:0] rowoff_out_n,
output wire[31:0] col_out_n,
output wire[31:0] col_out,
output wire[2:0] bincap_out_n,
output wire c0p_out_n,
output wire c0n_out_n
);
genvar i;
//[ data ]
//[11][10][9][8][7][6][5][4][3][2][1][0]
//[ row ][ col ][bincap ]
wire[2:0] bincap_w = data_in[2:0];
wire[4:0] col_intermediate_w = data_in[7:3];
wire[3:0] row_intermediate_w = data_in[11:8];
wire row_direction_RL = row_intermediate_w[0] ; // romode = 0 .. even/odd row is left to right
// rowmode = 1 .. lower half rows are left to right
// *********************************************
// Row Decoder
//
// Row Mode 0: from bot to top MSB[8 7 6 5 4 3 2 1]LSB
// Row Mode 1: start at middle MSB[7 5 3 1 2 4 6 8]LSB
// *********************************************
/// Row Down-to-Up mode
wire[15:0] row_bottotop_n = ~(16'h0001<<row_intermediate_w);
wire[15:0] rowon_bottotop_n = (16'hFFFF<<row_intermediate_w);
/// Row Mid-to-Top/Bot mode
wire [15:0] row_midtoside_n;
wire [15:0] rowon_midtoside_n;
generate
for (i=0;i<8;i=i+1) begin
assign row_midtoside_n[8+i] = row_bottotop_n[2*i];
assign row_midtoside_n[7-i] = row_bottotop_n[2*i+1];
assign rowon_midtoside_n[8+i] = rowon_bottotop_n[2*i];
assign rowon_midtoside_n[7-i] = rowon_bottotop_n[2*i+1];
end
endgenerate
/// Row Out
assign row_out_n = row_mode ? row_midtoside_n : row_bottotop_n ;
assign rowon_out_n = row_mode ? rowon_midtoside_n : rowon_bottotop_n ;
// status
wire is_first_row = ~row_out_n[0];
// *********************************************
// Column Decoder
//
// Col Mode 0: Direction from side to side
// even row: direction is left-to-right MSB[8 7 6 5 4 3 2 1]LSB
// odd row: direction is right-to-left MSB[7 5 3 1 2 4 6 8]LSB
// Col Mode 1: Direction from middle to side MSB[8 6 4 2 1 3 5 7]LSB
// *********************************************
// Shift register
wire[32:0] col_shift = (33'h1FFFFFFFE)<<col_intermediate_w;
wire[32:0] col_shift_inv;
generate
for (i=0;i<33;i=i+1) begin
assign col_shift_inv[i] = col_shift[32-i];
end
endgenerate
//-COLUMN START VALUE OF SHIFT REGISTER because cell {0,0} is a Dummy-
// row col | first row other rows
// 0 0 | 10..00 10..00
// 0 1 | 00..00 10..00
// 1 0 | 00..00 00..00
// 1 1 | 00..00 00..00
wire zeroes = row_mode == 1'b1 | (row_mode==1'b0 & col_mode==1'b1 & is_first_row );
wire[31:0] col_even_n = zeroes ? col_shift[32:1] : col_shift[31:0];
wire[31:0] col_odd_n = zeroes ? col_shift_inv[31:0] :
col_shift_inv[32:1] ;
/// Column-Side-to-Side mode
wire[31:0] col_sidetoside_n = row_direction_RL ? col_odd_n : col_even_n;
/// Column Middle-to-Side mode
wire[31:0] col_midtoside_n;
generate
for (i=0;i<16;i=i+1) begin
assign col_midtoside_n[16+i] = col_even_n[2*i];
assign col_midtoside_n[15-i] = col_even_n[2*i+1];
end
endgenerate
/// Column Out
assign col_out_n = col_mode ? col_midtoside_n : col_sidetoside_n;
assign col_out = ~col_out_n;
// *********************************************
// Bincap decoder, C0 decoder, misc
// *********************************************
assign bincap_out_n = ~bincap_w;
// semi-differential wires
assign rowoff_out_n = ~(row_out_n&rowon_out_n);
// LSB capacitor C0 is always enabled or disabled
assign c0p_out_n = 1'b0;
assign c0n_out_n = 1'b1;
endmodule |
module adc_core_digital(
input wire rst_n,
input wire [15:0] config_1_in,
input wire [15:0] config_2_in,
output wire [15:0] result_out,
output wire conv_finished_out,
output wire conv_finished_osr_out,
// Connections to Comparator-Latch
input wire comparator_in,
// Connections to Clockloop-Generator with Edgedetect
input wire clk_dig_in,
output wire enable_loop_out,
// Connections to Cap-Matrix
output wire sample_matrix_out,
output wire sample_matrix_out_n,
output wire sample_switch_out,
output wire sample_switch_out_n,
output wire [31:0] pmatrix_col_out_n,
output wire [31:0] pmatrix_col_out,
output wire [15:0] pmatrix_row_out_n,
output wire [15:0] pmatrix_rowon_out_n,
output wire [15:0] pmatrix_rowoff_out_n,
output wire [2:0] pmatrix_bincap_out_n,
output wire pmatrix_c0_out_n,
output wire [31:0] nmatrix_col_out_n,
output wire [31:0] nmatrix_col_out,
output wire [15:0] nmatrix_row_out_n,
output wire [15:0] nmatrix_rowon_out_n,
output wire [15:0] nmatrix_rowoff_out_n,
output wire [2:0] nmatrix_bincap_out_n,
output wire nmatrix_c0_out_n
);
//Configuration bytes mapping
wire [2:0] avg_control_w = config_1_in[2:0];
wire [2:0] osr_mode_w = config_1_in[5:3];
wire row_mode_w = config_1_in[6];
wire col_mode_w = config_1_in[7];
// Sample switch enable
assign sample_switch_out = sample_cnb;
assign sample_switch_out_n = sample_cnb_n;
// Matrix sampling enable
assign sample_matrix_out = sample_cnb;
assign sample_matrix_out_n = sample_cnb_n;
//*******************************************
// ADC Nonbinary Control-Block
//*******************************************
wire [11:0] result_cnb;
wire [11:0] pswitch_cnb;
wire [11:0] nswitch_cnb;
wire conv_finished_cnb_n;
wire sample_cnb_n;
wire sample_cnb;
adc_control_nonbinary cnb (
.clk(clk_dig_in),
.rst_n(rst_n),
.comparator_in(comparator_in),
.avg_control_in(avg_control_w),
.sample_out(sample_cnb),
.sample_out_n(sample_cnb_n),
.enable_loop_out(enable_loop_out),
.conv_finished_strobe_out(conv_finished_cnb_n),
.pswitch_out(pswitch_cnb),
.nswitch_out(nswitch_cnb),
.result_out(result_cnb)
);
assign conv_finished_out = conv_finished_cnb_n;
//*******************************************
// P/N-Matrix decoder
//*******************************************
adc_row_col_decoder pdc (
.data_in(pswitch_cnb),
.row_mode(row_mode_w),
.col_mode(col_mode_w),
.row_out_n(pmatrix_row_out_n),
.rowon_out_n(pmatrix_rowon_out_n),
.rowoff_out_n(pmatrix_rowoff_out_n),
.col_out_n(pmatrix_col_out_n),
.col_out(pmatrix_col_out),
.bincap_out_n(pmatrix_bincap_out_n),
.c0p_out_n(pmatrix_c0_out_n),
.c0n_out_n(_unused_ok_pin1)
);
adc_row_col_decoder ndc (
.data_in(nswitch_cnb),
.row_mode(row_mode_w),
.col_mode(col_mode_w),
.row_out_n(nmatrix_row_out_n),
.rowon_out_n(nmatrix_rowon_out_n),
.rowoff_out_n(nmatrix_rowoff_out_n),
.col_out_n(nmatrix_col_out_n),
.col_out(nmatrix_col_out),
.bincap_out_n(nmatrix_bincap_out_n),
.c0p_out_n(_unused_ok_pin2),
.c0n_out_n(nmatrix_c0_out_n)
);
//*******************************************
// Oversampling unit
//*******************************************
adc_osr osr (
.rst_n(rst_n),
.data_valid_strobe(conv_finished_cnb_n),
.osr_mode_in(osr_mode_w),
.data_in(result_cnb),
.data_out(result_out),
.conversion_finished_osr_out(conv_finished_osr_out)
);
//Linting
wire [7:0] _unused_ok_1 = config_1_in[15:8];
wire [15:0] _unused_ok_2 = config_2_in[15:0];
wire _unused_ok_pin1;
wire _unused_ok_pin2;
endmodule |
module adc_clkgen_with_edgedetect(
input wire ena_in, // enable signal from the digital clock core. 0 halts the self-clocked loop
input wire start_conv_in, // triggers a conversion once with edge-detection
input wire ndecision_finish_in, // comparator signalizes finished conversion
output wire clk_dig_out, // digital clock
output wire clk_comp_out, // comparator clock
input wire enable_dlycontrol_in, // 0 = max delays, 1 = configurable delays
input wire [4:0] dlycontrol1_in, // delay 1 of 3 in loop. Delay = 5ns*dlycontrol1
input wire [4:0] dlycontrol2_in, // delay 2 of 3 in loop. Delay = 5ns*dlycontrol2
input wire [4:0] dlycontrol3_in, // delay 3 of 3 in loop. Delay = 5ns*dlycontrol3
input wire [5:0] dlycontrol4_in, // edge detect pulse width. Delay = 5ns*dlycontrol4
// integration of additional buffers for sample matrix
input wire sample_p_in,
input wire sample_n_in,
output wire sample_p_out,
output wire sample_n_out
);
wire enable_loop_w;
wire ena_in_buffered_w;
wire start_conv_buffered_w;
wire ndecision_finish_buffered_w;
wire clk_dig_unbuffered_w;
wire clk_comp_unbuffered_w;
//Input buffers
sky130_fd_sc_hd__buf_1 inbuf_1 (.A(ena_in),.X(ena_in_buffered_w));
sky130_fd_sc_hd__buf_1 inbuf_2 (.A(start_conv_in),.X(start_conv_buffered_w));
sky130_fd_sc_hd__buf_1 inbuf_3 (.A(ndecision_finish_in),.X(ndecision_finish_buffered_w));
//Output buffers
sky130_fd_sc_hd__bufbuf_8 outbuf_1 (.A(clk_dig_unbuffered_w),.X(clk_dig_out));
sky130_fd_sc_hd__bufbuf_8 outbuf_2 (.A(clk_comp_unbuffered_w),.X(clk_comp_out));
// Output buffers for sample-signal-buffeing
// with delay, so matrix-sample is switched after gate is disabled
wire sample_p_1;
wire sample_n_1;
//sample enable delay stage
sky130_mm_sc_hd_dlyPoly5ns delay_sample_p11 (.in(sample_p_in), .out(sample_p_1));
sky130_mm_sc_hd_dlyPoly5ns delay_sample_n12 (.in(sample_n_in), .out(sample_n_1));
//sample enable output stage
sky130_fd_sc_hd__bufbuf_8 outbuf_3 (.A(sample_p_1),.X(sample_p_out));
sky130_fd_sc_hd__bufbuf_8 outbuf_4 (.A(sample_n_1),.X(sample_n_out));
//Circuits
adc_edge_detect_circuit edgedetect (.start_conv_in(start_conv_buffered_w),
.ena_in(ena_in_buffered_w),
.ena_out(enable_loop_w),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol_in(dlycontrol4_in));
adc_clk_generation clkgen (.ndecision_finish_in(ndecision_finish_buffered_w),
.enable_loop_in(enable_loop_w),
.clk_dig_out(clk_dig_unbuffered_w),
.clk_comp_out(clk_comp_unbuffered_w),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol1_in(dlycontrol1_in),
.dlycontrol2_in(dlycontrol2_in),
.dlycontrol3_in(dlycontrol3_in));
endmodule |
module adc_clk_generation(
input wire ndecision_finish_in, // 0 = comparator finished
input wire enable_loop_in, // 1 = self clocked loop enabled
output wire clk_dig_out, // clk for digital core
output wire clk_comp_out, // clk for comparator
input wire enable_dlycontrol_in, // 0 = max delays, 1 = configured delays
input wire [4:0] dlycontrol1_in, // delay1 = N times 5ns
input wire [4:0] dlycontrol2_in, // delay2 = N times 5ns
input wire [4:0] dlycontrol3_in // delay3 = N times 5ns
);
wire ndecision_finish_delayed_w;
wire clk_dig_delayed_w;
wire net1_w;
binary_delaycell #(.DLYCONTROL_BITWIDTH(5)) delay_155ns_1
(
.in(ndecision_finish_in),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol_in(dlycontrol1_in),
.out(ndecision_finish_delayed_w)
);
sky130_fd_sc_hd__inv_2 clkdig_inverter (.A(ndecision_finish_delayed_w),.Y(clk_dig_out));
binary_delaycell #(.DLYCONTROL_BITWIDTH(5)) delay_155ns_2
(
.in(clk_dig_out),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol_in(dlycontrol2_in),
.out(clk_dig_delayed_w)
);
sky130_fd_sc_hd__nor2b_1 nor1 (.A(clk_dig_delayed_w),.B_N(enable_loop_in),.Y(net1_w)); //2 input nor, B inverted
binary_delaycell #(.DLYCONTROL_BITWIDTH(5)) delay_155ns_3
(
.in(net1_w),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol_in(dlycontrol3_in),
.out(clk_comp_out)
);
endmodule |
module adc_edge_detect_circuit(
input wire start_conv_in, // Tell the ADC to start a conversion
input wire ena_in, // signal from the digital core to enable the self-clocked-loop
output wire ena_out, // enable the self-clocked-loop
input wire enable_dlycontrol_in, // 0 = max delays, 1 = configured delays
input wire [5:0] dlycontrol_in // delay = N times 5ns
);
// Internal wires
wire start_conv_delayed_w;
wire start_conv_edge_w;
binary_delaycell #(.DLYCONTROL_BITWIDTH(6)) dly_315ns_1
(
.in(start_conv_in),
.enable_dlycontrol_in(enable_dlycontrol_in),
.dlycontrol_in(dlycontrol_in),
.out(start_conv_delayed_w)
);
sky130_fd_sc_hd__nor2b_1 nor1 (.A(start_conv_delayed_w),.B_N(start_conv_in),.Y(start_conv_edge_w)); // 2 input nor, B inverted
sky130_fd_sc_hd__or2_1 or1 (.A(start_conv_edge_w),.B(ena_in),.X(ena_out)); // 2 input or
endmodule |
module binary_delaycell #(parameter DLYCONTROL_BITWIDTH = 5)
(
input wire in,
input wire enable_dlycontrol_in,
input wire [DLYCONTROL_BITWIDTH-1:0] dlycontrol_in,
output wire out
);
wire [DLYCONTROL_BITWIDTH:0] signal_w;
wire enable_dlycontrol_w;
wire [DLYCONTROL_BITWIDTH-1:0] bypass_enable_w;
wire [DLYCONTROL_BITWIDTH-1:0] bypass_w;
sky130_fd_sc_hd__buf_4 enablebuffer (.A(enable_dlycontrol_in),.X(enable_dlycontrol_w));
//instanciate binary coded delay cells
genvar i;
generate
for (i = 0; i < DLYCONTROL_BITWIDTH; i=i+1) begin
sky130_fd_sc_hd__inv_2 control_invert (.A(dlycontrol_in[i]),.Y(bypass_enable_w[i]));
sky130_fd_sc_hd__and2_1 bypass_enable (.A(enable_dlycontrol_w),.B(bypass_enable_w[i]),.X(bypass_w[i])); // 2 input and, A inverted
delaycell #(.N_TIMES_5NS(2**i)) dly_binary (
.in(signal_w[i]),
.bypass_in(bypass_w[i]),
.out(signal_w[i+1])
);
end
endgenerate
assign signal_w[0] = in;
assign out = signal_w[DLYCONTROL_BITWIDTH];
endmodule |
module delaycell #(parameter N_TIMES_5NS = 32)
(
input wire in,
input wire bypass_in,
output wire out
);
wire [N_TIMES_5NS:0] signal_w;
genvar j;
generate
for(j=0;j<N_TIMES_5NS;j=j+1) begin
sky130_mm_sc_hd_dlyPoly5ns delay_unit (.in(signal_w[j]), .out(signal_w[j+1]));
end
endgenerate
sky130_fd_sc_hd__and2b_1 and_bypass_switch (.A_N(bypass_in),.B(in),.X(signal_w[0])); // 2 input and, A inverted
sky130_fd_sc_hd__mux2_1 out_mux (.A0(signal_w[N_TIMES_5NS]),.A1(in),.S(bypass_in),.X(out)); //2 input mux
endmodule |
module adc_top(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input wire clk_vcm, // 32.768Hz VCM generation clock
input wire rst_n, // reset
input wire inp_analog, // P differential input
input wire inn_analog, // N differential input
input wire start_conversion_in,
input wire [15:0] config_1_in,
input wire [15:0] config_2_in,
output wire [15:0] result_out,
output wire conversion_finished_out,
output wire conversion_finished_osr_out,
input wire clk_dig_dummy
);
//Configuration byte 1 mapping
// config_1_in[2:0] = Average control
// config_1_in[5:3] = Oversampling control
// config_1_in[9:6] = unused
wire [5:0] delay_edgedetect_w = config_1_in[15:10];
//_linting
(*keep*)
wire _linting_unused_input_pins = config_1_in[6] | config_1_in[7] | config_1_in[8] | config_1_in[9];
//Configuration byte 2 mapping
wire [4:0] delay_1_w = config_2_in[4:0];
wire [4:0] delay_2_w = config_2_in[9:5];
wire [4:0] delay_3_w = config_2_in[14:10];
wire delaycontrol_en_w = config_2_in[15];
//*******************************************
// Digital Core
//*******************************************
(*keep*)
adc_core_digital core(
.rst_n(rst_n),
.config_1_in(config_1_in),
.config_2_in(config_2_in),
.result_out(result_out),
.conv_finished_out(conversion_finished_out),
.conv_finished_osr_out(conversion_finished_osr_out),
// Connections to Comparator-Latch
.comparator_in(result_comp),
// Connections to Clockloop-Generator with Edgedetect
.clk_dig_in(clk_dig_dummy),
.enable_loop_out(ena_loop_core),
// Connections to Cap-Matrix
.sample_matrix_out(sample_matrix_core),
.sample_matrix_out_n(sample_matrix_core_n),
.sample_switch_out(sample_switch_core),
.sample_switch_out_n(sample_switch_core_n),
.pmatrix_col_out_n(pmatrix_col_core_n),
.pmatrix_col_out(pmatrix_col_core),
.pmatrix_row_out_n(pmatrix_row_core_n),
.pmatrix_rowon_out_n(pmatrix_rowon_core_n),
.pmatrix_rowoff_out_n(pmatrix_rowoff_core_n),
.pmatrix_bincap_out_n(pmatrix_bincap_core_n),
.pmatrix_c0_out_n(pmatrix_c0_core_n),
.nmatrix_col_out_n(nmatrix_col_core_n),
.nmatrix_col_out(nmatrix_col_core),
.nmatrix_row_out_n(nmatrix_row_core_n),
.nmatrix_rowon_out_n(nmatrix_rowon_core_n),
.nmatrix_rowoff_out_n(nmatrix_rowoff_core_n),
.nmatrix_bincap_out_n(nmatrix_bincap_core_n),
.nmatrix_c0_out_n(nmatrix_c0_core_n)
);
wire sample_matrix_core, sample_matrix_core_n;
wire sample_switch_core, sample_switch_core_n;
wire [31:0] pmatrix_col_core_n, nmatrix_col_core_n;
wire [31:0] pmatrix_col_core, nmatrix_col_core;
wire [15:0] pmatrix_row_core_n, nmatrix_row_core_n;
wire [15:0] pmatrix_rowon_core_n, nmatrix_rowon_core_n;
wire [15:0] pmatrix_rowoff_core_n, nmatrix_rowoff_core_n;
wire [2:0] pmatrix_bincap_core_n, nmatrix_bincap_core_n;
wire pmatrix_c0_core_n, nmatrix_c0_core_n;
wire ena_loop_core;
//*******************************************
// Clock Loop with Edge-Detection
// **** HARDENED MACRO ****
//*******************************************
(*keep*)
adc_clkgen_with_edgedetect cgen (
`ifdef USE_POWER_PINS
.VDD(VDD), // User area 1.8V supply
.VSS(VSS), // User area ground
`endif
.ena_in(ena_loop_core),
.start_conv_in(start_conversion_in),
.ndecision_finish_in(decision_finish_comp_n),
.clk_dig_out(clk_dig_cgen),
.clk_comp_out(clk_comp_cgen),
.enable_dlycontrol_in(delaycontrol_en_w),
.dlycontrol1_in(delay_1_w),
.dlycontrol2_in(delay_2_w),
.dlycontrol3_in(delay_3_w),
.dlycontrol4_in(delay_edgedetect_w),
.sample_p_in(sample_matrix_core),
.sample_n_in(sample_matrix_core),
.sample_p_out(sample_pmatrix_cgen),
.sample_n_out(sample_nmatrix_cgen)
);
wire clk_dig_cgen;
wire clk_comp_cgen;
wire sample_pmatrix_cgen, sample_nmatrix_cgen;
//*******************************************
// Matrix P-side
// **** HARDENED MACRO ****
//*******************************************
(*keep*)
adc_array_matrix_12bit pmat (
`ifdef USE_POWER_PINS
.VDD(VDD), // User area 1.8V supply
.VSS(VSS), // User area ground
`endif
.sample(sample_pmatrix_cgen),
.sample_n(~sample_pmatrix_cgen),
.row_n(pmatrix_row_core_n_buffered),
.rowon_n(pmatrix_rowon_core_n_buffered),
.rowoff_n(pmatrix_rowoff_core_n),
.col_n(pmatrix_col_core_n_buffered),
.col(pmatrix_col_core),
.en_bit_n(pmatrix_bincap_core_n),
.en_C0_n(pmatrix_c0_core_n),
.sw(pmat_sample_switch_buffered),
.sw_n(pmat_sample_switch_n_buffered),
.analog_in(inp_analog),
.ctop(ctop_pmatrix_analog)
);
wire ctop_pmatrix_analog;
//Buffering, switch signal must be fast
wire pmat_sample_switch_buffered, pmat_sample_switch_n_buffered;
sky130_fd_sc_hd__buf_8 pmat_sample_buf (.A(sample_switch_core),.X(pmat_sample_switch_buffered));
sky130_fd_sc_hd__buf_8 pmat_sample_buf_n (.A(sample_switch_core_n),.X(pmat_sample_switch_n_buffered));
//*******************************************
// Matrix N-side
// **** HARDENED MACRO ****
//*******************************************
(*keep*)
adc_array_matrix_12bit nmat (
`ifdef USE_POWER_PINS
.VDD(VDD), // User area 1.8V supply
.VSS(VSS), // User area ground
`endif
.sample(sample_nmatrix_cgen),
.sample_n(~sample_nmatrix_cgen),
.row_n(nmatrix_row_core_n_buffered),
.rowon_n(nmatrix_rowon_core_n_buffered),
.rowoff_n(nmatrix_rowoff_core_n),
.col_n(nmatrix_col_core_n_buffered),
.col(nmatrix_col_core),
.en_bit_n(nmatrix_bincap_core_n),
.en_C0_n(nmatrix_c0_core_n),
.sw(nmat_sample_switch_buffered),
.sw_n(nmat_sample_switch_n_buffered),
.analog_in(inn_analog),
.ctop(ctop_nmatrix_analog)
);
wire ctop_nmatrix_analog;
//Buffering, switch signal must be fast
wire nmat_sample_switch_buffered, nmat_sample_switch_n_buffered;
sky130_fd_sc_hd__buf_8 nmat_sample_buf (.A(sample_switch_core),.X(nmat_sample_switch_buffered));
sky130_fd_sc_hd__buf_8 nmat_sample_buf_n (.A(sample_switch_core_n),.X(nmat_sample_switch_n_buffered));
//*******************************************
// Matrix Buffering
// **** HARDENED MACRO ****
//*******************************************
genvar i;
wire [31:0] nmatrix_col_core_n_buffered;
wire [31:0] pmatrix_col_core_n_buffered;
generate
for (i=0;i<32;i=i+1) begin
sky130_fd_sc_hd__buf_8 buf_n_coln (.A(nmatrix_col_core_n[i]),.X(nmatrix_col_core_n_buffered[i]));
sky130_fd_sc_hd__buf_8 buf_p_coln (.A(pmatrix_col_core_n[i]),.X(pmatrix_col_core_n_buffered[i]));
end
endgenerate
wire [15:0] nmatrix_row_core_n_buffered;
wire [15:0] nmatrix_rowon_core_n_buffered;
wire [15:0] pmatrix_row_core_n_buffered;
wire [15:0] pmatrix_rowon_core_n_buffered;
generate
for (i=0;i<16;i=i+1) begin
sky130_fd_sc_hd__buf_4 buf_n_rown (.A(nmatrix_row_core_n[i]),.X(nmatrix_row_core_n_buffered[i]));
sky130_fd_sc_hd__buf_4 buf_n_rowonn (.A(nmatrix_rowon_core_n[i]),.X(nmatrix_rowon_core_n_buffered[i]));
sky130_fd_sc_hd__buf_4 buf_p_rown (.A(pmatrix_row_core_n[i]),.X(pmatrix_row_core_n_buffered[i]));
sky130_fd_sc_hd__buf_4 buf_p_rowonn (.A(pmatrix_rowon_core_n[i]),.X(pmatrix_rowon_core_n_buffered[i]));
end
endgenerate
//*******************************************
// Comparator latch
// **** HARDENED MACRO ****
//*******************************************
(*keep*)
adc_comp_latch comp (
`ifdef USE_POWER_PINS
.VDD(VDD), // User area 1.8V supply
.VSS(VSS), // User area ground
`endif
.clk(clk_comp_cgen),
.inp(ctop_pmatrix_analog),
.inn(ctop_nmatrix_analog),
.comp_trig(decision_finish_comp_n),
.latch_qn(_linting_unused_ok),
.latch_q(result_comp)
);
wire decision_finish_comp_n;
wire result_comp;
wire _linting_unused_ok;
//*******************************************
// VCM generator
// **** HARDENED MACRO ****
//*******************************************
(*keep*)
adc_vcm_generator vcm (
`ifdef USE_POWER_PINS
.VDD(VDD), // User area 1.8V supply
.VSS(VSS), // User area ground
`endif
.clk(clk_vcm)
);
(*keep*)
scboundary obstruction1 ();
(*keep*)
scboundary obstruction2 ();
endmodule |
module adc_core_digital_tb;
reg rst_n;
reg [15:0] config_1_in;
reg [15:0] config_2_in;
wire [15:0] result_out;
wire conv_finished_out;
wire conv_finished_osr_out;
// Connections to Comparator-Latch
reg comparator_in;
// Connections to Clockloop-Generator with Edgedetect
reg clk_dig_in;
wire enable_loop_out;
// Connections to Cap-Matrix
wire sample_matrix_out;
wire sample_matrix_out_n;
wire sample_switch_out;
wire sample_switch_out_n;
wire [31:0] pmatrix_col_out_n;
wire [15:0] pmatrix_row_out_n;
wire [15:0] pmatrix_rowon_out_n;
wire [2:0] pmatrix_bincap_out_n;
wire pmatrix_c0_out_n;
wire [31:0] nmatrix_col_out_n;
wire [15:0] nmatrix_row_out_n;
wire [15:0] nmatrix_rowon_out_n;
wire [2:0] nmatrix_bincap_out_n;
wire nmatrix_c0_out_n;
adc_core_digital core_dut (
.rst_n(rst_n),
.config_1_in(config_1_in),
.config_2_in(config_2_in),
.result_out(result_out),
.conv_finished_out(conv_finished_out),
.conv_finished_osr_out(conv_finished_osr_out),
// Connections to Comparator-Latch
.comparator_in(comparator_in),
// Connections to Clockloop-Generator with Edgedetect
.clk_dig_in(clk_dig_in),
.enable_loop_out(enable_loop_out),
// Connections to Cap-Matrix
.sample_matrix_out(sample_matrix_out),
.sample_matrix_out_n(sample_matrix_out_n),
.sample_switch_out(sample_switch_out),
.sample_switch_out_n(sample_switch_out_n),
.pmatrix_col_out_n(pmatrix_col_out_n),
.pmatrix_row_out_n(pmatrix_row_out_n),
.pmatrix_rowon_out_n(pmatrix_rowon_out_n),
.pmatrix_bincap_out_n(pmatrix_bincap_out_n),
.pmatrix_c0_out_n(pmatrix_c0_out_n),
.nmatrix_col_out_n(nmatrix_col_out_n),
.nmatrix_row_out_n(nmatrix_row_out_n),
.nmatrix_rowon_out_n(nmatrix_rowon_out_n),
.nmatrix_bincap_out_n(nmatrix_bincap_out_n),
.nmatrix_c0_out_n(nmatrix_c0_out_n)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,
rst_n,
config_1_in,
config_2_in,
result_out,
conv_finished_out,
conv_finished_osr_out,
comparator_in,
clk_dig_in,
enable_loop_out,
sample_matrix_out,
sample_matrix_out_n,
sample_switch_out,
sample_switch_out_n,
pmatrix_col_out_n,
pmatrix_row_out_n,
pmatrix_rowon_out_n,
pmatrix_bincap_out_n,
pmatrix_c0_out_n,
nmatrix_col_out_n,
nmatrix_row_out_n,
nmatrix_rowon_out_n,
nmatrix_bincap_out_n,
nmatrix_c0_out_n,
core_dut);
end
initial begin
#1
clk_dig_in = 1'b1;
config_1_in = 16'b0000000000001001; //4 averages, 4 OSR
config_2_in = 16'b0000000000000000; // disable delay configuration, not used here
#2;
comparator_in = 0;
rst_n=1; #2;
rst_n=0; #2;
rst_n=1;
// ************** TEST1 ***************
// 4x Averaging of LSB
// 4x OSR
// Values: a) 972 0x3CC
// b) 1612 0x64C
// c) 4 0x004
// d) 0 0x000
// 16Bit-Sum expected: 0x2870
// Result = {[13:1],3'b0} -> 00[0010110010101]0+[000]
comparator_in = 0; //0001 +2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 1; //4000 +486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0008 -2
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0004 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//OSR hold data
#2 comparator_in = 0; //0001
// FINISHED 1/4 conversions
#2 comparator_in = 0; //+2048
#2 comparator_in = 1; //8000 +806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0008 -2
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0004 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//OSR hold data
#2 comparator_in = 0; //0001
// FINISHED 2/4 conversions
#2 comparator_in = 0; //+2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 1; //0008 +2
#2 comparator_in = 1;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 0; //0004 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//OSR hold data
#2 comparator_in = 0; //0001
// FINISHED 3/4 conversions
#2 comparator_in = 0; //+2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0008 -2
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0004 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//OSR hold data
#2 comparator_in = 0; //0001
// FINISHED 4/4 conversions
#2 comparator_in = 0;
#16 // wait
//RESET EVERYTHING
#2 rst_n=0;
config_1_in = 16'b0000000000000000; //0 averages, 0 OSR
#2 rst_n=1;
// ************** TEST2 ***************
// 0x Averaging of LSB
// 0x OSR
// Values: d806 0x3CC
// Sum expected: 0x3CC0
comparator_in = 0; //0001 //+2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 1; //4000 +486
#2 comparator_in = 0; //2000
#2 comparator_in = 0; //1000
#2 comparator_in = 0; //0800
#2 comparator_in = 0; //0400
#2 comparator_in = 0; //0200
#2 comparator_in = 0; //0100
#2 comparator_in = 0; //0080
#2 comparator_in = 0; //0040
#2 comparator_in = 0; //0020
//averaging
#2 comparator_in = 0; //0010
//averaging
#2 comparator_in = 0; //0008
//averaging
#2 comparator_in = 0; //0004
//averaging
#2 comparator_in = 0; //0002
//OSR hold data
#2 comparator_in = 0;
// FINISHED conversions
#2 comparator_in = 0; //0001
#20
$finish;
end
initial begin
forever begin
#1 clk_dig_in = ~clk_dig_in;
end
end
endmodule |
module adc_osr_tb;
reg rst_n;
reg data_valid_strobe;
reg [2:0] osr_mode;
reg [11:0] data;
wire [15:0] result;
wire conversion_finished;
adc_osr osr_dut (
.data_valid_strobe(data_valid_strobe),
.rst_n(rst_n),
.osr_mode_in(osr_mode),
.data_in(data),
.data_out(result),
.conversion_finished_osr_out(conversion_finished)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,
data_valid_strobe,
rst_n,
osr_mode,
data,
result,
conversion_finished,
osr_dut);
end
integer i;
initial begin
data_valid_strobe=0;
rst_n = 1;
osr_mode = 3'b000;
data=0;
rst_n=1; #2;
rst_n=0; #4;
rst_n=1; #2;
data = 12'h111; #2;
data = 12'h222; #2;
osr_mode = 3'b001;
// 4 samples, result is h0018
for (i = 0; i < 4 ; i = i + 1 ) begin
data = 12'h000 + i; #2;
end
// 16 samples, result is h890
rst_n = 0; #2 rst_n = 1;
osr_mode = 3'b010;
for (i = 0; i < 16 ; i = i + 1 ) begin
data = 12'h890; #2;
end
// 16 samples, result is h8978
osr_mode = 3'b010;
for (i = 0; i < 16 ; i = i + 1 ) begin
data = 12'h890+i; #2;
end
// 64 samples, result is h01F8
osr_mode = 3'b011;
for (i = 0; i < 64 ; i = i + 1 ) begin
data = 12'h000+i; #2;
end
// 256 samples, result is h07F8
osr_mode = 3'b100;
for (i = 0; i < 256 ; i = i + 1 ) begin
data = 12'h000+i; #2;
end
osr_mode = 3'b000;
data = 12'h123; #2;
#1 $finish;
end
initial begin
forever begin
#1 data_valid_strobe = ~data_valid_strobe;
end
end
endmodule |
module adc_control_nonbinary_tb;
parameter MATRIX_BITS = 12;
reg clk;
reg nrst;
reg comparator_in;
reg [2:0] avg_control;
wire sample;
wire nsample;
wire enable;
wire conv_finished;
wire[MATRIX_BITS-1:0] p_switch;
wire[MATRIX_BITS-1:0] n_switch;
wire[MATRIX_BITS-1:0] result;
adc_control_nonbinary testmodule (
.clk(clk),
.rst_n(nrst),
.comparator_in(comparator_in),
.avg_control_in(avg_control),
.sample_out(sample),
.sample_out_n(nsample),
.enable_loop_out(enable),
.conv_finished_strobe_out(conv_finished),
.pswitch_out(p_switch),
.nswitch_out(n_switch),
.result_out(result)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,
clk,
nrst,
comparator_in,
avg_control,
sample,
nsample,
enable,
conv_finished,
p_switch,
n_switch,
result,
testmodule);
end
initial begin
#1 nrst=1;
#1 nrst=0;
#1 nrst=1;
#1 nrst=1; avg_control = 3'b001;
#1 comparator_in = 0;
// first value is 064C
avg_control = 3'b001; //4x averaging
#2 comparator_in = 0; //0001 +2048
#2 comparator_in = 1; //8000 +806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0008 -2
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0004 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 0; // hold_data_for_osr clock gating
// second value is d3CC
avg_control = 3'b000; //0x averaging
#2 comparator_in = 0; //0001 +2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 1; //4000 +486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -4
//averaging
#2 comparator_in = 0; //0008 -2
//averaging
#2 comparator_in = 0; //0004 -1
//averaging
#2 comparator_in = 0; //0002 -1
#2 comparator_in = 0; // hold_data_for_osr clock gating
// third value is d15 0x0F
avg_control = 3'b000; //0x averaging
#2 comparator_in = 0; //0001 +2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 0; //2000 -295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 1; //0010 +4
//averaging
#2 comparator_in = 1; //0008 +2
//averaging
#2 comparator_in = 1; //0004 +1
//averaging
#2 comparator_in = 1; //0002 +0
#2 comparator_in = 0; // hold_data_for_osr clock gating
// fourth value is 0x251 593
avg_control = 3'b010; //8x averaging
#2 comparator_in = 0; //0001 +2048
#2 comparator_in = 0; //8000 -806
#2 comparator_in = 0; //4000 -486
#2 comparator_in = 1; //2000 +295
#2 comparator_in = 0; //1000 -180
#2 comparator_in = 0; //0800 -110
#2 comparator_in = 0; //0400 -67
#2 comparator_in = 0; //0200 -41
#2 comparator_in = 0; //0100 -25
#2 comparator_in = 0; //0080 -15
#2 comparator_in = 0; //0040 -9
#2 comparator_in = 0; //0020 -6
//averaging
#2 comparator_in = 0; //0010 -1
#2 comparator_in = 1;
#2 comparator_in = 0;
#2 comparator_in = 1;
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 0;
//averaging
#2 comparator_in = 0; //0008 -2
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 1; //0010 +1
#2 comparator_in = 0;
#2 comparator_in = 0;
#2 comparator_in = 1;
#2 comparator_in = 0;
#2 comparator_in = 1;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 1; //0010 +0
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 0; // hold_data_for_osr clock gating
// fifth value is max value with max averaging d4095
avg_control = 3'b100; //0x averaging
#2 comparator_in = 0; //0001
#2 comparator_in = 1; //8000
#2 comparator_in = 1; //4000
#2 comparator_in = 1; //2000
#2 comparator_in = 1; //1000
#2 comparator_in = 1; //0800
#2 comparator_in = 1; //0400
#2 comparator_in = 1; //0200
#2 comparator_in = 1; //0100
#2 comparator_in = 1; //0080
#2 comparator_in = 1; //0040
#2 comparator_in = 1; //0020
//averaging
#2 comparator_in = 1; //0010
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 1; //0008
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 1; //0004
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
//averaging
#2 comparator_in = 1; //0002
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 1;
#2 comparator_in = 0; // hold_data_for_osr clock gating
// sixth value zero without averaging
avg_control = 3'b000; //0x averaging
#2 comparator_in = 0; //0001
#2 comparator_in = 0; //8000
#2 comparator_in = 0; //4000
#2 comparator_in = 0; //2000
#2 comparator_in = 0; //1000
#2 comparator_in = 0; //0800
#2 comparator_in = 0; //0400
#2 comparator_in = 0; //0200
#2 comparator_in = 0; //0100
#2 comparator_in = 0; //0080
#2 comparator_in = 0; //0040
#2 comparator_in = 0; //0020
//averaging
#2 comparator_in = 0; //0010
//averaging
#2 comparator_in = 0; //0008
//averaging
#2 comparator_in = 0; //0004
//averaging
#2 comparator_in = 0; //0002
#2 comparator_in = 0; // hold_data_for_osr clock gating
#512 $finish;
end
initial begin
#1 clk=0;
#6 clk=0;
forever begin
#1 clk = ~clk;
end
end
endmodule |
module adc_row_col_decoder_tb;
reg[11:0] data;
reg row_mode;
reg col_mode;
wire[15:0] row_n;
wire[15:0] rowon_n;
wire[15:0] rowoff_n;
wire[31:0] col_n;
wire[31:0] col;
wire[2:0] bincap_n;
wire c0p_n;
wire c0n_n;
adc_row_col_decoder decoder (
.data_in(data),
.row_mode(row_mode),
.col_mode(col_mode),
.row_out_n(row_n),
.rowon_out_n(rowon_n),
.rowoff_out_n(rowoff_n),
.col_out_n(col_n),
.col_out(col),
.bincap_out_n(bincap_n),
.c0p_out_n(c0p_n),
.c0n_out_n(c0n_n)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,
data,
row_mode,
col_mode,
row_n,
rowon_n,
rowoff_n,
col_n,
col,
bincap_n,
c0p_n,
c0n_n,
decoder);
end
integer i;
initial begin
data=0;
row_mode = 1;
col_mode = 1;
for(i=1;i<4096;i=i+1) begin
#1 data=data+1;
end
#1 data=12'd4093;
#1 data=12'd4094;
#1 data=12'd4095;
#1 $finish;
end
endmodule |
module testbench_2k;
// Inputs
reg clk, reset;
reg signed [31:0] x;
// Outputs
wire signed [31:0] y;
// Instantiate the Unit Under Test (UUT)
pipelined_iir uut (
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);
// Generate clock with 100ns period
initial clk = 0;
always #50 clk = ~clk;
// filter coefficients
// A = [1048576, -8218189, 32107544, -81217352, 147076592, -199990256, 208937824, -168854944, 104844152, -48879952, 16314139, -3525584, 379931]
// B = [631178, -5401947, 23050644, -63646908, 125716872, -186294288, 211911376, -186294288, 125716872, -63646908, 23050644, -5401947, 631178]
// Initialize and pass sinusoidal input data of 2kHz with sampling frequency of 48kHz
initial begin
x = 0; reset = 1; clk = 0; #100;
reset = 1; #200;
reset = 0;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
x = 741455; #100;
x = 524288; #100;
x = 271391; #100;
x = 0; #100;
x = -271391; #100;
x = -524288; #100;
x = -741455; #100;
x = -908093; #100;
x = -1012846; #100;
x = -1048576; #100;
x = -1012846; #100;
x = -908093; #100;
x = -741455; #100;
x = -524288; #100;
x = -271391; #100;
x = 0; #100;
x = 271391; #100;
x = 524288; #100;
x = 741455; #100;
x = 908093; #100;
x = 1012846; #100;
x = 1048576; #100;
x = 1012846; #100;
x = 908093; #100;
end
endmodule |
module tb_order_matching_engine;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Inputs
reg clk;
reg rst_n;
reg [31:0] order_data;
reg order_valid;
reg [31:0] tcp_rx_data;
reg tcp_rx_valid;
reg m_axis_ready;
// Outputs
wire [31:0] trade_data;
wire trade_valid;
wire [31:0] tcp_tx_data;
wire tcp_tx_valid;
wire s_axis_ready;
wire [31:0] m_axis_data;
wire m_axis_valid;
// Instantiate the order matching engine module
order_matching_engine dut (
.clk(clk),
.rst_n(rst_n),
.order_data(order_data),
.order_valid(order_valid),
.trade_data(trade_data),
.trade_valid(trade_valid),
.tcp_rx_data(tcp_rx_data),
.tcp_rx_valid(tcp_rx_valid),
.tcp_tx_data(tcp_tx_data),
.tcp_tx_valid(tcp_tx_valid),
.s_axis_data(m_axis_data),
.s_axis_valid(m_axis_valid),
.s_axis_ready(s_axis_ready),
.m_axis_data(m_axis_data),
.m_axis_valid(m_axis_valid),
.m_axis_ready(m_axis_ready)
);
// Clock generation
always begin
clk = 1'b0;
#(CLK_PERIOD/2);
clk = 1'b1;
#(CLK_PERIOD/2);
end
// Testbench stimulus
initial begin
// Initialize inputs
rst_n = 1'b0;
order_data = 32'h0;
order_valid = 1'b0;
tcp_rx_data = 32'h0;
tcp_rx_valid = 1'b0;
m_axis_ready = 1'b1;
// Reset the module
#(CLK_PERIOD*2);
rst_n = 1'b1;
// Test case 1: Send a buy order
#(CLK_PERIOD*2);
order_data = {2'b00, 2'b00, 8'h10, 8'h01, 8'h00, 4'h0}; // Buy limit order with price 16 and quantity 1
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 2: Send a sell order
#(CLK_PERIOD*2);
order_data = {2'b00, 2'b00, 8'h20, 8'h02, 8'h00, 4'h0}; // Sell limit order with price 32 and quantity 2
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 3: Send a matching buy order
#(CLK_PERIOD*2);
order_data = {2'b00, 2'b00, 8'h20, 8'h02, 8'h00, 4'h0}; // Buy limit order with price 32 and quantity 2
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 4: Send a market buy order
#(CLK_PERIOD*2);
order_data = {2'b01, 2'b00, 8'h00, 8'h03, 8'h00, 4'h0}; // Buy market order with quantity 3
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 5: Send a sell stop order
#(CLK_PERIOD*2);
order_data = {2'b10, 2'b00, 8'h30, 8'h04, 8'h40, 4'h0}; // Sell stop order with price 48, quantity 4, and stop price 64
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 6: Send a buy trailing stop order
#(CLK_PERIOD*2);
order_data = {2'b11, 2'b00, 8'h50, 8'h05, 8'h60, 4'h2}; // Buy trailing stop order with price 80, quantity 5, stop price 96, and trail 2
order_valid = 1'b1;
#(CLK_PERIOD);
order_valid = 1'b0;
// Test case 7: Receive a TCP packet
#(CLK_PERIOD*2);
tcp_rx_data = 32'h12345678;
tcp_rx_valid = 1'b1;
#(CLK_PERIOD);
tcp_rx_valid = 1'b0;
// End the simulation
#(CLK_PERIOD*10);
$finish;
end
// Assertion for trade execution
always @(posedge clk) begin
if (trade_valid) begin
$display("Trade executed: price = %d, quantity = %d", trade_data[7:0], trade_data[15:8]);
if (trade_data[7:0] == 8'h20 && trade_data[15:8] == 8'h02)
$display("Trade data is correct");
else
$error("Incorrect trade data");
end
end
// Assertion for TCP transmit data
always @(posedge clk) begin
if (tcp_tx_valid) begin
$display("TCP transmit data: %h", tcp_tx_data);
if (tcp_tx_data == {2'b11, 30'h1234567})
$display("TCP transmit data is correct");
else
$error("Incorrect TCP transmit data");
end
end
endmodule |
module tb_risk_management;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Inputs
reg clk;
reg rst_n;
reg [31:0] trade_data;
reg trade_valid;
reg [31:0] position_update;
reg position_update_valid;
reg [31:0] exposure_update;
reg exposure_update_valid;
// Outputs
wire trade_approved;
wire [31:0] current_position;
wire [31:0] current_exposure;
// Instantiate the risk management module
risk_management dut (
.clk(clk),
.rst_n(rst_n),
.trade_data(trade_data),
.trade_valid(trade_valid),
.trade_approved(trade_approved),
.position_update(position_update),
.position_update_valid(position_update_valid),
.current_position(current_position),
.exposure_update(exposure_update),
.exposure_update_valid(exposure_update_valid),
.current_exposure(current_exposure),
.max_exposure_limit(32'h1000000),
.max_position_limit(32'h100000)
);
// Clock generation
always begin
clk = 1'b0;
#(CLK_PERIOD/2);
clk = 1'b1;
#(CLK_PERIOD/2);
end
// Testbench stimulus
initial begin
// Initialize inputs
rst_n = 1'b0;
trade_data = 32'h0;
trade_valid = 1'b0;
position_update = 32'h0;
position_update_valid = 1'b0;
exposure_update = 32'h0;
exposure_update_valid = 1'b0;
// Reset the module
#(CLK_PERIOD*2);
rst_n = 1'b1;
// Test case 1: Valid trade within risk limits
#(CLK_PERIOD*2);
trade_data = 32'h00010000; // Trade amount: 65536
trade_valid = 1'b1;
#(CLK_PERIOD);
trade_valid = 1'b0;
// Test case 2: Valid position update
#(CLK_PERIOD*2);
position_update = 32'h00020000; // Position update: 131072
position_update_valid = 1'b1;
#(CLK_PERIOD);
position_update_valid = 1'b0;
// Test case 3: Valid exposure update
#(CLK_PERIOD*2);
exposure_update = 32'h00030000; // Exposure update: 196608
exposure_update_valid = 1'b1;
#(CLK_PERIOD);
exposure_update_valid = 1'b0;
// Test case 4: Trade exceeding exposure limit
#(CLK_PERIOD*2);
trade_data = 32'h00800000; // Trade amount: 8388608 (exceeds exposure limit)
trade_valid = 1'b1;
#(CLK_PERIOD);
trade_valid = 1'b0;
// Test case 5: Trade exceeding position limit
#(CLK_PERIOD*2);
trade_data = 32'h00100000; // Trade amount: 1048576 (exceeds position limit)
trade_valid = 1'b1;
#(CLK_PERIOD);
trade_valid = 1'b0;
// End the simulation
#(CLK_PERIOD*10);
$finish;
end
// Assertion for trade approval
always @(posedge clk) begin
if (trade_valid) begin
$display("Trade: amount = %d, approved = %b", trade_data, trade_approved);
if (trade_data <= 32'h00400000) begin
if (!trade_approved)
$display("Trade should have been approved");
end else begin
if (trade_approved)
$display("Trade should have been rejected");
end
end
end
// Assertion for current position and exposure
always @(posedge clk) begin
$display("Current position: %d, Current exposure: %d", current_position, current_exposure);
if (current_position > 32'h100000)
$display("Position limit exceeded");
if (current_exposure > 32'h1000000)
$display("Exposure limit exceeded");
end
endmodule |
module tb_custom_ip_core;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Inputs
reg clk;
reg rst_n;
reg [31:0] s_axis_tdata;
reg s_axis_tvalid;
reg m_axis_tready;
reg [31:0] control_reg;
// Outputs
wire s_axis_tready;
wire [31:0] m_axis_tdata;
wire m_axis_tvalid;
wire [31:0] status_reg;
// Instantiate the custom IP core module
custom_ip_core dut (
.clk(clk),
.rst_n(rst_n),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.control_reg(control_reg),
.status_reg(status_reg)
);
// Clock generation
always begin
clk = 1'b0;
#(CLK_PERIOD/2);
clk = 1'b1;
#(CLK_PERIOD/2);
end
// Testbench stimulus
initial begin
// Initialize inputs
rst_n = 1'b0;
s_axis_tdata = 32'h0;
s_axis_tvalid = 1'b0;
m_axis_tready = 1'b1;
control_reg = 32'h0;
// Reset the module
#(CLK_PERIOD*2);
rst_n = 1'b1;
// Test case 1: Send input data
#(CLK_PERIOD*2);
s_axis_tdata = 32'h12345678;
s_axis_tvalid = 1'b1;
#(CLK_PERIOD);
s_axis_tvalid = 1'b0;
wait(m_axis_tvalid);
#(CLK_PERIOD);
// Test case 2: Configure control register
#(CLK_PERIOD*2);
control_reg = 32'hABCDEF01;
#(CLK_PERIOD*2);
// Test case 3: Send input data with control register configured
#(CLK_PERIOD*2);
s_axis_tdata = 32'h87654321;
s_axis_tvalid = 1'b1;
#(CLK_PERIOD);
s_axis_tvalid = 1'b0;
wait(m_axis_tvalid);
#(CLK_PERIOD);
// Test case 4: Check status register
#(CLK_PERIOD*2);
$display("Status register: %h", status_reg);
if (status_reg[7:0] == 8'd1)
$display("Status register is correct");
else
$error("Incorrect status register value");
// End the simulation
#(CLK_PERIOD*10);
$finish;
end
// Verify the output data
always @(posedge clk) begin
if (m_axis_tvalid) begin
$display("Output data: %h", m_axis_tdata);
if (m_axis_tdata == 32'h12345678 + control_reg)
$display("Output data is correct");
else
$error("Incorrect output data");
end
end
endmodule |
module tb_tcp_ip_stack;
// Parameters
parameter CLK_PERIOD = 10; // Clock period in nanoseconds
// Inputs
reg clk;
reg rst_n;
reg [31:0] app_tx_data;
reg app_tx_valid;
reg [31:0] eth_rx_data;
reg eth_rx_valid;
reg eth_tx_ready;
// Outputs
wire app_tx_ready;
wire [31:0] app_rx_data;
wire app_rx_valid;
wire [31:0] eth_tx_data;
wire eth_tx_valid;
wire eth_rx_ready;
// Instantiate the TCP/IP stack module
tcp_ip_stack dut (
.clk(clk),
.rst_n(rst_n),
.app_tx_data(app_tx_data),
.app_tx_valid(app_tx_valid),
.app_tx_ready(app_tx_ready),
.app_rx_data(app_rx_data),
.app_rx_valid(app_rx_valid),
.app_rx_ready(1'b1),
.eth_tx_data(eth_tx_data),
.eth_tx_valid(eth_tx_valid),
.eth_tx_ready(eth_tx_ready),
.eth_rx_data(eth_rx_data),
.eth_rx_valid(eth_rx_valid),
.eth_rx_ready(eth_rx_ready)
);
// Clock generation
always begin
clk = 1'b0;
#(CLK_PERIOD/2);
clk = 1'b1;
#(CLK_PERIOD/2);
end
// Testbench stimulus
initial begin
// Initialize inputs
rst_n = 1'b0;
app_tx_data = 32'h0;
app_tx_valid = 1'b0;
eth_rx_data = 32'h0;
eth_rx_valid = 1'b0;
eth_tx_ready = 1'b1;
// Reset the module
#(CLK_PERIOD*2);
rst_n = 1'b1;
// Test case 1: Send application data
#(CLK_PERIOD*2);
app_tx_data = 32'h12345678;
app_tx_valid = 1'b1;
#(CLK_PERIOD);
app_tx_valid = 1'b0;
wait(eth_tx_valid);
#(CLK_PERIOD);
// Test case 2: Receive Ethernet data
#(CLK_PERIOD*2);
eth_rx_data = 32'h87654321;
eth_rx_valid = 1'b1;
#(CLK_PERIOD);
eth_rx_valid = 1'b0;
wait(app_rx_valid);
#(CLK_PERIOD);
// Test case 3: Send and receive multiple packets
#(CLK_PERIOD*2);
app_tx_data = 32'hAAAAAAAA;
app_tx_valid = 1'b1;
#(CLK_PERIOD);
app_tx_data = 32'hBBBBBBBB;
#(CLK_PERIOD);
app_tx_data = 32'hCCCCCCCC;
#(CLK_PERIOD);
app_tx_valid = 1'b0;
wait(eth_tx_valid);
#(CLK_PERIOD*3);
eth_rx_data = 32'h11111111;
eth_rx_valid = 1'b1;
#(CLK_PERIOD);
eth_rx_data = 32'h22222222;
#(CLK_PERIOD);
eth_rx_data = 32'h33333333;
#(CLK_PERIOD);
eth_rx_valid = 1'b0;
wait(app_rx_valid);
#(CLK_PERIOD*3);
// End the simulation
#(CLK_PERIOD*10);
$finish;
end
// Verify the transmitted Ethernet data
always @(posedge clk) begin
if (eth_tx_valid) begin
$display("Transmitted Ethernet data: %h", eth_tx_data);
if (eth_tx_data == 32'h12345678)
$display("Ethernet transmit data is correct");
else
$error("Incorrect Ethernet transmit data");
end
end
// Verify the received application data
always @(posedge clk) begin
if (app_rx_valid) begin
$display("Received application data: %h", app_rx_data);
if (app_rx_data == 32'h87654321)
$display("Application receive data is correct");
else
$error("Incorrect application receive data");
end
end
endmodule |
module risk_management (
input wire clk,
input wire rst_n,
input wire [31:0] trade_data,
input wire trade_valid,
output reg trade_approved,
// Position tracking
input wire [31:0] position_update,
input wire position_update_valid,
output reg [31:0] current_position,
// Exposure tracking
input wire [31:0] exposure_update,
input wire exposure_update_valid,
output reg [31:0] current_exposure,
// Risk checks
input wire [31:0] max_exposure_limit,
input wire [31:0] max_position_limit
);
// Risk parameters
parameter RISK_CHECK_EXPOSURE = 1;
parameter RISK_CHECK_POSITION = 1;
// Risk management logic
always @(posedge clk) begin
if (!rst_n) begin
// Reset logic
trade_approved <= 1;
current_position <= 0;
current_exposure <= 0;
end else begin
// Update position
if (position_update_valid) begin
current_position <= current_position + position_update;
end
// Update exposure
if (exposure_update_valid) begin
current_exposure <= current_exposure + exposure_update;
end
// Perform risk checks
if (trade_valid) begin
if (RISK_CHECK_EXPOSURE) begin
if (current_exposure + trade_data[31:0] > max_exposure_limit) begin
// Exposure limit exceeded
trade_approved <= 0;
end else begin
trade_approved <= 1;
end
end
if (RISK_CHECK_POSITION) begin
if (current_position + trade_data[31:0] > max_position_limit) begin
// Position limit exceeded
trade_approved <= 0;
end else begin
trade_approved <= 1;
end
end
end else begin
trade_approved <= 1;
end
end
end
endmodule |
module ethernet_layer (
input wire clk,
input wire rst_n,
// MAC interface
output reg [47:0] mac_tx_data,
output reg mac_tx_valid,
input wire mac_tx_ready,
input wire [47:0] mac_rx_data,
input wire mac_rx_valid,
output reg mac_rx_ready,
// TCP/IP stack interface
input wire [31:0] tcp_ip_tx_data,
input wire tcp_ip_tx_valid,
output reg tcp_ip_tx_ready,
output reg [31:0] tcp_ip_rx_data,
output reg tcp_ip_rx_valid,
input wire tcp_ip_rx_ready
);
// Ethernet frame parameters
parameter PREAMBLE = 64'h55555555555555D5;
parameter SFD = 8'hD5;
parameter ETH_TYPE_IPV4 = 16'h0800;
parameter MAC_ADDR_LOCAL = 48'h000A35000001;
parameter MAC_ADDR_REMOTE = 48'h000A35000002;
// Packet buffers
reg [1023:0] tx_buffer;
reg [10:0] tx_length;
reg [1023:0] rx_buffer;
reg [10:0] rx_length;
// Ethernet layer logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset logic
tx_length <= 0;
rx_length <= 0;
mac_tx_valid <= 0;
tcp_ip_rx_valid <= 0;
tcp_ip_tx_ready <= 1;
mac_rx_ready <= 1;
end else begin
// Transmit packet
if (tcp_ip_tx_valid && tcp_ip_tx_ready) begin
tx_buffer <= {PREAMBLE, SFD, MAC_ADDR_REMOTE, MAC_ADDR_LOCAL, ETH_TYPE_IPV4, tcp_ip_tx_data};
tx_length <= 14 + 20 + tcp_ip_tx_data[31:16];
end
if (mac_tx_ready && tx_length > 0) begin
mac_tx_data <= tx_buffer[1023:976];
mac_tx_valid <= 1;
tx_buffer <= {tx_buffer[975:0], 48'h0};
tx_length <= tx_length - 6;
end else begin
mac_tx_valid <= 0;
end
// Receive packet
if (mac_rx_valid && mac_rx_ready) begin
rx_buffer <= {rx_buffer[975:0], mac_rx_data};
rx_length <= rx_length + 6;
end
if (rx_length >= 14 + 20) begin
if (rx_buffer[1023:976] == MAC_ADDR_LOCAL && rx_buffer[959:944] == ETH_TYPE_IPV4) begin
tcp_ip_rx_data <= rx_buffer[943:912];
tcp_ip_rx_valid <= 1;
end
rx_buffer <= {rx_buffer[911:0], 112'h0};
rx_length <= rx_length - 14 - 20;
end else if (tcp_ip_rx_ready) begin
tcp_ip_rx_valid <= 0;
end
// Update ready signals
tcp_ip_tx_ready <= (tx_length == 0);
mac_rx_ready <= (rx_length < 1024 - 6);
end
end
endmodule |
module tcp_ip_stack (
input wire clk,
input wire rst_n,
// Application layer interface
input wire [31:0] app_tx_data,
input wire app_tx_valid,
output reg app_tx_ready,
output reg [31:0] app_rx_data,
output reg app_rx_valid,
input wire app_rx_ready,
// Ethernet interface
output reg [31:0] eth_tx_data,
output reg eth_tx_valid,
input wire eth_tx_ready,
input wire [31:0] eth_rx_data,
input wire eth_rx_valid,
output reg eth_rx_ready
);
// TCP/IP stack parameters
parameter LOCAL_IP = 32'hC0A80001; // 192.168.0.1
parameter LOCAL_PORT = 16'h1234;
parameter REMOTE_IP = 32'hC0A80002; // 192.168.0.2
parameter REMOTE_PORT = 16'h5678;
// TCP state machine
parameter CLOSED = 2'b00;
parameter SYN_SENT = 2'b01;
parameter ESTABLISHED = 2'b10;
parameter FIN_WAIT = 2'b11;
reg [1:0] tcp_state;
reg [31:0] tcp_seq_num;
reg [31:0] tcp_ack_num;
// Packet buffers
reg [31:0] tx_buffer [0:255];
reg [7:0] tx_head, tx_tail;
reg [31:0] rx_buffer [0:255];
reg [7:0] rx_head, rx_tail;
// TCP/IP stack logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset logic
tcp_state <= CLOSED;
tcp_seq_num <= 0;
tcp_ack_num <= 0;
tx_head <= 0;
tx_tail <= 0;
rx_head <= 0;
rx_tail <= 0;
app_tx_ready <= 0;
app_rx_valid <= 0;
eth_tx_valid <= 0;
eth_rx_ready <= 0;
end else begin
case (tcp_state)
CLOSED: begin
if (app_tx_valid) begin
// Send SYN packet
tcp_state <= SYN_SENT;
tcp_seq_num <= {$random} % 32'hFFFFFFFF;
tx_buffer[tx_tail] <= {tcp_seq_num, 16'h0002}; // SYN flag
tx_tail <= tx_tail + 1;
end
end
SYN_SENT: begin
if (eth_rx_valid && eth_rx_data[31:16] == {LOCAL_IP, LOCAL_PORT} &&
eth_rx_data[15:0] == {REMOTE_IP, REMOTE_PORT} && eth_rx_data[15] == 1'b1) begin
// Received SYN-ACK packet
tcp_state <= ESTABLISHED;
tcp_ack_num <= eth_rx_data[31:0] + 1;
tx_buffer[tx_tail] <= {tcp_seq_num, tcp_ack_num, 16'h0010}; // ACK flag
tx_tail <= tx_tail + 1;
end
end
ESTABLISHED: begin
if (app_tx_valid && app_tx_ready) begin
// Send data packet
tx_buffer[tx_tail] <= {tcp_seq_num, tcp_ack_num, 16'h0018, app_tx_data}; // PSH-ACK flags
tx_tail <= tx_tail + 1;
tcp_seq_num <= tcp_seq_num + 1;
end
if (eth_rx_valid && eth_rx_data[31:16] == {LOCAL_IP, LOCAL_PORT} &&
eth_rx_data[15:0] == {REMOTE_IP, REMOTE_PORT}) begin
if (eth_rx_data[15] == 1'b1 && eth_rx_data[14] == 1'b1) begin
// Received FIN-ACK packet
tcp_state <= FIN_WAIT;
tcp_ack_num <= eth_rx_data[31:0] + 1;
tx_buffer[tx_tail] <= {tcp_seq_num, tcp_ack_num, 16'h0011}; // FIN-ACK flags
tx_tail <= tx_tail + 1;
end else if (eth_rx_data[13] == 1'b1) begin
// Received data packet
rx_buffer[rx_tail] <= eth_rx_data[31:0];
rx_tail <= rx_tail + 1;
tcp_ack_num <= eth_rx_data[31:0] + 1;
tx_buffer[tx_tail] <= {tcp_seq_num, tcp_ack_num, 16'h0010}; // ACK flag
tx_tail <= tx_tail + 1;
end
end
end
FIN_WAIT: begin
// Wait for application to close connection
if (app_rx_ready && app_rx_valid) begin
tcp_state <= CLOSED;
end
end
endcase
// Transmit packet
if (eth_tx_ready && tx_head != tx_tail) begin
eth_tx_data <= {LOCAL_IP, LOCAL_PORT, REMOTE_IP, REMOTE_PORT, tx_buffer[tx_head]};
eth_tx_valid <= 1;
tx_head <= tx_head + 1;
end else begin
eth_tx_valid <= 0;
end
// Receive packet
if (app_rx_ready && rx_head != rx_tail) begin
app_rx_data <= rx_buffer[rx_head];
app_rx_valid <= 1;
rx_head <= rx_head + 1;
end else begin
app_rx_valid <= 0;
end
// Update ready signals
app_tx_ready <= (tcp_state == ESTABLISHED) && (tx_tail - tx_head < 256);
eth_rx_ready <= (tcp_state == ESTABLISHED) && (rx_tail - rx_head < 256);
end
end
endmodule |
module order_matching_engine (
input wire clk,
input wire rst_n,
input wire [31:0] order_data,
input wire order_valid,
output reg [31:0] trade_data,
output reg trade_valid,
// TCP/IP stack interfaces
input wire [31:0] tcp_rx_data,
input wire tcp_rx_valid,
output reg [31:0] tcp_tx_data,
output reg tcp_tx_valid,
// AXI stream interfaces
input wire [31:0] s_axis_data,
input wire s_axis_valid,
output reg s_axis_ready,
output reg [31:0] m_axis_data,
output reg m_axis_valid,
input wire m_axis_ready
);
// Advanced order types
parameter LIMIT_ORDER = 2'b00;
parameter MARKET_ORDER = 2'b01;
parameter STOP_ORDER = 2'b10;
parameter TRAILING_STOP_ORDER = 2'b11;
// Execution strategies
parameter AGGRESSIVE_STRATEGY = 2'b00;
parameter PASSIVE_STRATEGY = 2'b01;
parameter ICEBERG_STRATEGY = 2'b10;
parameter VWAP_STRATEGY = 2'b11;
// Order book data structure
reg [1:0] bid_order_type [0:255];
reg [1:0] bid_execution_strategy [0:255];
reg [31:0] bid_price [0:255];
reg [31:0] bid_quantity [0:255];
reg [31:0] bid_stop_price [0:255];
reg [31:0] bid_iceberg_quantity [0:255];
reg [1:0] ask_order_type [0:255];
reg [1:0] ask_execution_strategy [0:255];
reg [31:0] ask_price [0:255];
reg [31:0] ask_quantity [0:255];
reg [31:0] ask_stop_price [0:255];
reg [31:0] ask_iceberg_quantity [0:255];
reg [7:0] bid_book_size;
reg [7:0] ask_book_size;
// Matching engine logic
always @(posedge clk) begin
if (!rst_n) begin
// Reset logic
bid_book_size <= 0;
ask_book_size <= 0;
trade_valid <= 0;
tcp_tx_valid <= 0;
s_axis_ready <= 1;
m_axis_valid <= 0;
end else begin
// Process incoming orders
if (order_valid) begin
bid_order_type[bid_book_size] <= order_data[1:0];
bid_execution_strategy[bid_book_size] <= order_data[3:2];
bid_price[bid_book_size] <= order_data[11:4];
bid_quantity[bid_book_size] <= order_data[19:12];
bid_stop_price[bid_book_size] <= order_data[27:20];
bid_iceberg_quantity[bid_book_size] <= order_data[31:28];
case (order_data[1:0])
LIMIT_ORDER: begin
// Process limit order
if (order_data[0]) begin
// Buy order
bid_book_size <= bid_book_size + 1;
end else begin
// Sell order
ask_book_size <= ask_book_size + 1;
end
end
MARKET_ORDER: begin
// Process market order
if (order_data[0]) begin
// Buy order
if (ask_book_size > 0) begin
// Match with the best available sell order
trade_data <= {ask_price[ask_book_size - 1], ask_quantity[ask_book_size - 1]};
trade_valid <= 1;
ask_book_size <= ask_book_size - 1;
end
end else begin
// Sell order
if (bid_book_size > 0) begin
// Match with the best available buy order
trade_data <= {bid_price[bid_book_size - 1], bid_quantity[bid_book_size - 1]};
trade_valid <= 1;
bid_book_size <= bid_book_size - 1;
end
end
end
STOP_ORDER: begin
// Process stop order
if (order_data[0]) begin
// Buy stop order
if (order_data[27:20] <= bid_price[bid_book_size - 1]) begin
// Stop price triggered, add to bid book
bid_book_size <= bid_book_size + 1;
end
end else begin
// Sell stop order
if (order_data[27:20] >= ask_price[ask_book_size - 1]) begin
// Stop price triggered, add to ask book
ask_book_size <= ask_book_size + 1;
end
end
end
TRAILING_STOP_ORDER: begin
// Process trailing stop order
if (order_data[0]) begin
// Buy trailing stop order
if (order_data[27:20] <= bid_price[bid_book_size - 1]) begin
// Stop price triggered, add to bid book
bid_book_size <= bid_book_size + 1;
end else begin
// Update stop price based on market movement
bid_stop_price[bid_book_size] <= bid_price[bid_book_size - 1] - order_data[31:28];
end
end else begin
// Sell trailing stop order
if (order_data[27:20] >= ask_price[ask_book_size - 1]) begin
// Stop price triggered, add to ask book
ask_book_size <= ask_book_size + 1;
end else begin
// Update stop price based on market movement
ask_stop_price[ask_book_size] <= ask_price[ask_book_size - 1] + order_data[31:28];
end
end
end
endcase
// Apply execution strategies
case (order_data[3:2])
AGGRESSIVE_STRATEGY: begin
// Implement aggressive execution strategy
// Immediately match the order with the best available price
if (order_data[1:0] == LIMIT_ORDER) begin
if (order_data[0] && ask_book_size > 0 && order_data[11:4] >= ask_price[ask_book_size - 1]) begin
// Aggressive buy order
trade_data <= {ask_price[ask_book_size - 1], order_data[19:12]};
trade_valid <= 1;
ask_book_size <= ask_book_size - 1;
end else if (!order_data[0] && bid_book_size > 0 && order_data[11:4] <= bid_price[bid_book_size - 1]) begin
// Aggressive sell order
trade_data <= {bid_price[bid_book_size - 1], order_data[19:12]};
trade_valid <= 1;
bid_book_size <= bid_book_size - 1;
end
end
end
PASSIVE_STRATEGY: begin
// Implement passive execution strategy
// Add the order to the book without immediate execution
if (order_data[1:0] == LIMIT_ORDER) begin
if (order_data[0]) begin
// Passive buy order
bid_book_size <= bid_book_size + 1;
end else begin
// Passive sell order
ask_book_size <= ask_book_size + 1;
end
end
end
ICEBERG_STRATEGY: begin
// Implement iceberg execution strategy
// Display only a portion of the total order quantity
if (order_data[1:0] == LIMIT_ORDER) begin
if (order_data[0]) begin
// Iceberg buy order
bid_book_size <= bid_book_size + 1;
bid_quantity[bid_book_size] <= order_data[31:28];
end else begin
// Iceberg sell order
ask_book_size <= ask_book_size + 1;
ask_quantity[ask_book_size] <= order_data[31:28];
end
end
end
VWAP_STRATEGY: begin
// Implement VWAP execution strategy
// Execute orders based on the volume-weighted average price
// TODO: Implement VWAP execution logic
end
endcase
end
// Perform matching logic
if (bid_book_size > 0 && ask_book_size > 0) begin
if (bid_price[bid_book_size - 1] >= ask_price[ask_book_size - 1]) begin
// Execute trade
trade_data <= {bid_price[bid_book_size - 1], bid_quantity[bid_book_size - 1]};
trade_valid <= 1;
// Update order books
bid_book_size <= bid_book_size - 1;
ask_book_size <= ask_book_size - 1;
end else begin
trade_valid <= 0;
end
end else begin
trade_valid <= 0;
end
// TCP/IP stack integration
if (tcp_rx_valid) begin
// Process incoming TCP data
case (tcp_rx_data[1:0])
2'b01: begin
// New order
if (tcp_rx_data[0]) begin
// Buy order
bid_book_size <= bid_book_size + 1;
end else begin
// Sell order
ask_book_size <= ask_book_size + 1;
end
end
2'b10: begin
// Cancel order
// Implement order cancellation logic
// TODO: Implement order cancellation logic
end
// Add more cases for other TCP commands
endcase
end
// Generate outgoing TCP data
tcp_tx_valid <= 0;
if (trade_valid) begin
tcp_tx_data <= {2'b11, trade_data[29:0]};
tcp_tx_valid <= 1;
end
// AXI stream interfaces
s_axis_ready <= 1;
m_axis_data <= trade_data;
m_axis_valid <= trade_valid;
end
end
endmodule |
module axi_stream_if #(
parameter DATA_WIDTH = 32,
parameter DEST_WIDTH = 4,
parameter USER_WIDTH = 4,
parameter ID_WIDTH = 4,
parameter HAS_STRB = 0,
parameter HAS_KEEP = 0,
parameter HAS_LAST = 1,
parameter HAS_DEST = 0,
parameter HAS_USER = 0,
parameter HAS_ID = 0
)(
// AXI stream interface signals
input wire aclk,
input wire aresetn,
input wire [DATA_WIDTH-1:0] tdata,
input wire [DEST_WIDTH-1:0] tdest,
input wire [USER_WIDTH-1:0] tuser,
input wire [ID_WIDTH-1:0] tid,
input wire [(DATA_WIDTH/8)-1:0] tstrb,
input wire [(DATA_WIDTH/8)-1:0] tkeep,
input wire tlast,
input wire tvalid,
output wire tready
);
// AXI stream interface assignments
assign tready = 1'b1; // Always ready to accept data
// Implement your custom logic here
// You can access the AXI stream signals (tdata, tdest, tuser, tid, tstrb, tkeep, tlast, tvalid)
// and perform necessary operations based on your requirements
// Example: Logging AXI stream data
always @(posedge aclk) begin
if (tvalid && tready) begin
$display("AXI Stream Data: tdata=%h, tdest=%h, tuser=%h, tid=%h, tstrb=%h, tkeep=%h, tlast=%b",
tdata, tdest, tuser, tid, tstrb, tkeep, tlast);
end
end
endmodule |
module top_level (
input wire clk,
input wire rst_n,
// Ethernet interface
input wire [47:0] eth_rx_data,
input wire eth_rx_valid,
output wire eth_rx_ready,
output wire [47:0] eth_tx_data,
output wire eth_tx_valid,
input wire eth_tx_ready,
// Custom IP core control and status signals
input wire [31:0] custom_ip_control,
output wire [31:0] custom_ip_status
);
// Instantiate the Ethernet layer module
wire [31:0] eth_to_ip_data;
wire eth_to_ip_valid;
wire eth_to_ip_ready;
wire [31:0] ip_to_eth_data;
wire ip_to_eth_valid;
wire ip_to_eth_ready;
ethernet_layer ethernet_inst (
.clk(clk),
.rst_n(rst_n),
.mac_rx_data(eth_rx_data),
.mac_rx_valid(eth_rx_valid),
.mac_rx_ready(eth_rx_ready),
.mac_tx_data(eth_tx_data),
.mac_tx_valid(eth_tx_valid),
.mac_tx_ready(eth_tx_ready),
.tcp_ip_rx_data(eth_to_ip_data),
.tcp_ip_rx_valid(eth_to_ip_valid),
.tcp_ip_rx_ready(eth_to_ip_ready),
.tcp_ip_tx_data(ip_to_eth_data),
.tcp_ip_tx_valid(ip_to_eth_valid),
.tcp_ip_tx_ready(ip_to_eth_ready)
);
// Instantiate the IP layer module
wire [31:0] ip_to_tcp_data;
wire ip_to_tcp_valid;
wire ip_to_tcp_ready;
wire [31:0] tcp_to_ip_data;
wire tcp_to_ip_valid;
wire tcp_to_ip_ready;
ip_layer ip_inst (
.clk(clk),
.rst_n(rst_n),
.eth_rx_data(eth_to_ip_data),
.eth_rx_valid(eth_to_ip_valid),
.eth_rx_ready(eth_to_ip_ready),
.eth_tx_data(ip_to_eth_data),
.eth_tx_valid(ip_to_eth_valid),
.eth_tx_ready(ip_to_eth_ready),
.tcp_rx_data(ip_to_tcp_data),
.tcp_rx_valid(ip_to_tcp_valid),
.tcp_rx_ready(ip_to_tcp_ready),
.tcp_tx_data(tcp_to_ip_data),
.tcp_tx_valid(tcp_to_ip_valid),
.tcp_tx_ready(tcp_to_ip_ready)
);
// Instantiate the TCP layer module
wire [31:0] tcp_to_app_data;
wire tcp_to_app_valid;
wire tcp_to_app_ready;
wire [31:0] app_to_tcp_data;
wire app_to_tcp_valid;
wire app_to_tcp_ready;
tcp_layer tcp_inst (
.clk(clk),
.rst_n(rst_n),
.ip_rx_data(ip_to_tcp_data),
.ip_rx_valid(ip_to_tcp_valid),
.ip_rx_ready(ip_to_tcp_ready),
.ip_tx_data(tcp_to_ip_data),
.ip_tx_valid(tcp_to_ip_valid),
.ip_tx_ready(tcp_to_ip_ready),
.app_rx_data(tcp_to_app_data),
.app_rx_valid(tcp_to_app_valid),
.app_rx_ready(tcp_to_app_ready),
.app_tx_data(app_to_tcp_data),
.app_tx_valid(app_to_tcp_valid),
.app_tx_ready(app_to_tcp_ready)
);
// Instantiate the custom IP core module
wire [31:0] custom_ip_tx_data;
wire custom_ip_tx_valid;
wire custom_ip_tx_ready;
wire [31:0] custom_ip_rx_data;
wire custom_ip_rx_valid;
wire custom_ip_rx_ready;
custom_ip_core custom_ip_inst (
.clk(clk),
.rst_n(rst_n),
.s_axis_tdata(tcp_to_app_data),
.s_axis_tvalid(tcp_to_app_valid),
.s_axis_tready(tcp_to_app_ready),
.m_axis_tdata(custom_ip_tx_data),
.m_axis_tvalid(custom_ip_tx_valid),
.m_axis_tready(custom_ip_tx_ready),
.control_reg(custom_ip_control),
.status_reg(custom_ip_status)
);
// Instantiate the AXI stream interface module for the custom IP core
axi_stream_if #(
.DATA_WIDTH(32),
.DEST_WIDTH(4),
.USER_WIDTH(4),
.ID_WIDTH(4),
.HAS_STRB(0),
.HAS_KEEP(0),
.HAS_LAST(1),
.HAS_DEST(0),
.HAS_USER(0),
.HAS_ID(0)
) axi_stream_inst (
.aclk(clk),
.aresetn(rst_n),
.tdata(custom_ip_tx_data),
.tdest(4'b0),
.tuser(4'b0),
.tid(4'b0),
.tstrb(4'b0),
.tkeep(4'b0),
.tlast(1'b1),
.tvalid(custom_ip_tx_valid),
.tready(custom_ip_tx_ready)
);
// Instantiate the order matching engine module
wire [31:0] order_data;
wire order_valid;
wire [31:0] trade_data;
wire trade_valid;
wire [31:0] position_update;
wire position_update_valid;
wire [31:0] exposure_update;
wire exposure_update_valid;
order_matching_engine order_matching_inst (
.clk(clk),
.rst_n(rst_n),
.order_data(custom_ip_rx_data),
.order_valid(custom_ip_rx_valid),
.trade_data(trade_data),
.trade_valid(trade_valid),
.tcp_rx_data(tcp_to_app_data),
.tcp_rx_valid(tcp_to_app_valid),
.tcp_tx_data(custom_ip_tx_data),
.tcp_tx_valid(custom_ip_tx_valid),
.s_axis_data(custom_ip_tx_data),
.s_axis_valid(custom_ip_tx_valid),
.s_axis_ready(custom_ip_tx_ready),
.m_axis_data(custom_ip_rx_data),
.m_axis_valid(custom_ip_rx_valid),
.m_axis_ready(custom_ip_rx_ready)
);
// Instantiate the risk management module
wire trade_approved;
wire [31:0] current_position;
wire [31:0] current_exposure;
risk_management risk_mgmt_inst (
.clk(clk),
.rst_n(rst_n),
.trade_data(trade_data),
.trade_valid(trade_valid),
.trade_approved(trade_approved),
.position_update(position_update),
.position_update_valid(position_update_valid),
.current_position(current_position),
.exposure_update(exposure_update),
.exposure_update_valid(exposure_update_valid),
.current_exposure(current_exposure),
.max_exposure_limit(32'h1000000), // Example max exposure limit
.max_position_limit(32'h100000) // Example max position limit
);
// Connect signals between modules
assign order_data = custom_ip_rx_data;
assign order_valid = custom_ip_rx_valid && trade_approved;
assign position_update = trade_data;
assign position_update_valid = trade_valid && trade_approved;
assign exposure_update = trade_data;
assign exposure_update_valid = trade_valid && trade_approved;
assign app_to_tcp_data = trade_data;
assign app_to_tcp_valid = trade_valid && trade_approved;
assign custom_ip_rx_ready = tcp_to_app_ready;
endmodule |
module ip_layer (
input wire clk,
input wire rst_n,
// Ethernet layer interface
input wire [31:0] eth_rx_data,
input wire eth_rx_valid,
output wire eth_rx_ready,
output wire [31:0] eth_tx_data,
output wire eth_tx_valid,
input wire eth_tx_ready,
// TCP layer interface
output wire [31:0] tcp_rx_data,
output wire tcp_rx_valid,
input wire tcp_rx_ready,
input wire [31:0] tcp_tx_data,
input wire tcp_tx_valid,
output wire tcp_tx_ready
);
// IP packet parameters
parameter IP_VERSION = 4'h4;
parameter IP_IHL = 4'h5;
parameter IP_TOS = 8'h00;
parameter IP_TTL = 8'h40;
parameter IP_PROTOCOL_TCP = 8'h06;
parameter IP_ADDR_LOCAL = 32'hC0A80001; // 192.168.0.1
parameter IP_ADDR_REMOTE = 32'hC0A80002; // 192.168.0.2
// Packet buffers
reg [31:0] rx_buffer;
reg rx_buffer_valid;
reg [31:0] tx_buffer;
reg tx_buffer_valid;
// IP layer logic
always @(posedge clk) begin
if (!rst_n) begin
// Reset logic
rx_buffer_valid <= 0;
tx_buffer_valid <= 0;
end else begin
// Receive packet
if (eth_rx_valid && eth_rx_ready) begin
rx_buffer <= eth_rx_data;
rx_buffer_valid <= 1;
end else if (tcp_rx_ready) begin
rx_buffer_valid <= 0;
end
// Transmit packet
if (tcp_tx_valid && tcp_tx_ready) begin
tx_buffer <= {IP_VERSION, IP_IHL, IP_TOS, tcp_tx_data[15:0], 16'h0000, IP_TTL, IP_PROTOCOL_TCP, 16'h0000, IP_ADDR_LOCAL, IP_ADDR_REMOTE, tcp_tx_data};
tx_buffer_valid <= 1;
end else if (eth_tx_ready) begin
tx_buffer_valid <= 0;
end
end
end
// Receive path
assign tcp_rx_data = rx_buffer;
assign tcp_rx_valid = rx_buffer_valid && (rx_buffer[31:28] == IP_VERSION) && (rx_buffer[27:24] == IP_IHL) && (rx_buffer[23:16] == IP_PROTOCOL_TCP);
assign eth_rx_ready = !rx_buffer_valid || tcp_rx_ready;
// Transmit path
assign eth_tx_data = tx_buffer;
assign eth_tx_valid = tx_buffer_valid;
assign tcp_tx_ready = !tx_buffer_valid || eth_tx_ready;
endmodule |
module tcp_layer (
input wire clk,
input wire rst_n,
// IP layer interface
input wire [31:0] ip_rx_data,
input wire ip_rx_valid,
output wire ip_rx_ready,
output wire [31:0] ip_tx_data,
output wire ip_tx_valid,
input wire ip_tx_ready,
// Application layer interface
output wire [31:0] app_rx_data,
output wire app_rx_valid,
input wire app_rx_ready,
input wire [31:0] app_tx_data,
input wire app_tx_valid,
output wire app_tx_ready
);
// Instantiate the tcp_ip_stack module
tcp_ip_stack tcp_ip_stack_inst (
.clk(clk),
.rst_n(rst_n),
.app_tx_data(app_tx_data),
.app_tx_valid(app_tx_valid),
.app_tx_ready(app_tx_ready),
.app_rx_data(app_rx_data),
.app_rx_valid(app_rx_valid),
.app_rx_ready(app_rx_ready),
.eth_tx_data(ip_tx_data),
.eth_tx_valid(ip_tx_valid),
.eth_tx_ready(ip_tx_ready),
.eth_rx_data(ip_rx_data),
.eth_rx_valid(ip_rx_valid),
.eth_rx_ready(ip_rx_ready)
);
// TCP packet parameters
parameter TCP_SRC_PORT = 16'h1234;
parameter TCP_DST_PORT = 16'h5678;
parameter TCP_SEQ_NUM_INIT = 32'h00000000;
parameter TCP_ACK_NUM_INIT = 32'h00000000;
parameter TCP_WINDOW_SIZE = 16'h7FFF;
parameter TCP_CHECKSUM_ENABLE = 1;
// TCP states
parameter TCP_STATE_CLOSED = 2'b00;
parameter TCP_STATE_SYN_SENT = 2'b01;
parameter TCP_STATE_ESTABLISHED = 2'b10;
parameter TCP_STATE_FIN_WAIT = 2'b11;
// Packet buffers
reg [31:0] rx_buffer;
reg rx_buffer_valid;
reg [31:0] tx_buffer;
reg tx_buffer_valid;
// TCP state variables
reg [1:0] tcp_state;
reg [31:0] tcp_seq_num;
reg [31:0] tcp_ack_num;
// TCP layer logic
always @(posedge clk) begin
if (!rst_n) begin
// Reset logic
tcp_state <= TCP_STATE_CLOSED;
tcp_seq_num <= TCP_SEQ_NUM_INIT;
tcp_ack_num <= TCP_ACK_NUM_INIT;
rx_buffer_valid <= 0;
tx_buffer_valid <= 0;
end else begin
case (tcp_state)
TCP_STATE_CLOSED: begin
if (app_tx_valid && app_tx_ready) begin
// Send SYN packet
tcp_state <= TCP_STATE_SYN_SENT;
tcp_seq_num <= TCP_SEQ_NUM_INIT;
tx_buffer <= {TCP_SRC_PORT, TCP_DST_PORT, tcp_seq_num, 32'h00000000, 16'h5002, TCP_WINDOW_SIZE, 16'h0000};
tx_buffer_valid <= 1;
end
end
TCP_STATE_SYN_SENT: begin
if (ip_rx_valid && ip_rx_ready && ip_rx_data[31:16] == {TCP_DST_PORT, TCP_SRC_PORT} && ip_rx_data[15:0] == 16'h5012) begin
// Receive SYN-ACK packet
tcp_state <= TCP_STATE_ESTABLISHED;
tcp_ack_num <= ip_rx_data[47:32] + 1;
tx_buffer <= {TCP_SRC_PORT, TCP_DST_PORT, tcp_seq_num, tcp_ack_num, 16'h5010, TCP_WINDOW_SIZE, 16'h0000};
tx_buffer_valid <= 1;
end
end
TCP_STATE_ESTABLISHED: begin
if (app_tx_valid && app_tx_ready) begin
// Send data packet
tx_buffer <= {TCP_SRC_PORT, TCP_DST_PORT, tcp_seq_num, tcp_ack_num, 16'h5018, TCP_WINDOW_SIZE, 16'h0000, app_tx_data};
tx_buffer_valid <= 1;
tcp_seq_num <= tcp_seq_num + 1;
end
if (ip_rx_valid && ip_rx_ready) begin
if (ip_rx_data[31:16] == {TCP_DST_PORT, TCP_SRC_PORT} && ip_rx_data[15:0] == 16'h5011) begin
// Receive FIN-ACK packet
tcp_state <= TCP_STATE_FIN_WAIT;
tcp_ack_num <= ip_rx_data[31:0] + 1;
tx_buffer <= {TCP_SRC_PORT, TCP_DST_PORT, tcp_seq_num, tcp_ack_num, 16'h5011, TCP_WINDOW_SIZE, 16'h0000};
tx_buffer_valid <= 1;
end else if (ip_rx_data[15:0] == 16'h5018) begin
// Receive data packet
rx_buffer <= ip_rx_data;
rx_buffer_valid <= 1;
tcp_ack_num <= ip_rx_data[31:0] + 1;
tx_buffer <= {TCP_SRC_PORT, TCP_DST_PORT, tcp_seq_num, tcp_ack_num, 16'h5010, TCP_WINDOW_SIZE, 16'h0000};
tx_buffer_valid <= 1;
end
end
end
TCP_STATE_FIN_WAIT: begin
if (app_rx_ready && app_rx_valid) begin
// Application acknowledged FIN
tcp_state <= TCP_STATE_CLOSED;
end
end
endcase
// Clear buffer valid flags when data is consumed
if (tx_buffer_valid && ip_tx_ready) begin
tx_buffer_valid <= 0;
end
if (rx_buffer_valid && app_rx_ready) begin
rx_buffer_valid <= 0;
end
end
end
// Receive path
assign app_rx_data = rx_buffer;
assign app_rx_valid = rx_buffer_valid;
assign ip_rx_ready = !rx_buffer_valid || app_rx_ready;
// Transmit path
assign ip_tx_data = tx_buffer;
assign ip_tx_valid = tx_buffer_valid;
assign app_tx_ready = (tcp_state == TCP_STATE_ESTABLISHED) && !tx_buffer_valid;
// Checksum calculation (optional)
// TODO: Implement TCP checksum calculation if enabled
endmodule |
module custom_ip_core (
input wire clk,
input wire rst_n,
// AXI stream interface for input
input wire [31:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg s_axis_tready,
// AXI stream interface for output
output reg [31:0] m_axis_tdata,
output reg m_axis_tvalid,
input wire m_axis_tready,
// Control and status signals
input wire [31:0] control_reg,
output reg [31:0] status_reg
);
// Packet buffer
reg [31:0] packet_buffer [0:255];
reg [7:0] packet_length;
// Internal registers
reg [31:0] internal_reg1;
reg [31:0] internal_reg2;
// State machine
parameter STATE_IDLE = 2'b00;
parameter STATE_PROCESS = 2'b01;
parameter STATE_TRANSMIT = 2'b10;
reg [1:0] current_state;
reg [1:0] next_state;
// Custom IP core logic
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// Reset logic
packet_length <= 0;
internal_reg1 <= 0;
internal_reg2 <= 0;
current_state <= STATE_IDLE;
s_axis_tready <= 1;
m_axis_tvalid <= 0;
status_reg <= 0;
end else begin
case (current_state)
STATE_IDLE: begin
if (s_axis_tvalid && s_axis_tready) begin
// Receive input data
packet_buffer[packet_length] <= s_axis_tdata;
packet_length <= packet_length + 1;
if (s_axis_tdata[31:24] == 8'hFF) begin
// End of packet marker received
next_state <= STATE_PROCESS;
end
end
end
STATE_PROCESS: begin
// Process the received packet
// Perform custom IP core functionality here
internal_reg1 <= packet_buffer[0] + control_reg;
internal_reg2 <= packet_buffer[1] * control_reg;
// ...
// Prepare the output packet
packet_buffer[0] <= internal_reg1;
packet_buffer[1] <= internal_reg2;
// ...
next_state <= STATE_TRANSMIT;
end
STATE_TRANSMIT: begin
if (m_axis_tready && m_axis_tvalid) begin
// Transmit output data
if (packet_length > 0) begin
m_axis_tdata <= packet_buffer[packet_length - 1];
packet_length <= packet_length - 1;
end else begin
// End of packet
m_axis_tdata <= 32'hFFFFFFFF;
next_state <= STATE_IDLE;
end
end
end
endcase
current_state <= next_state;
end
end
// Ready signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
s_axis_tready <= 1;
m_axis_tvalid <= 0;
end else begin
s_axis_tready <= (current_state == STATE_IDLE);
m_axis_tvalid <= (current_state == STATE_TRANSMIT);
end
end
// Status register
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
status_reg <= 0;
end else begin
status_reg <= {24'b0, packet_length};
end
end
endmodule |
module async_mem (/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_data, wr_cs, addr, rd_cs
);
parameter asz = 15,
depth = 32768;
input wr_clk;
input [7:0] wr_data;
input wr_cs;
input [asz-1:0] addr;
inout [7:0] rd_data;
input rd_cs;
reg [7:0] mem [0:depth-1];
always @(posedge wr_clk)
begin
if (wr_cs)
mem[addr] <= #1 wr_data;
end
assign rd_data = (rd_cs) ? mem[addr] : {8{1'bz}};
endmodule // async_mem |
module divider #(parameter DELAY=50000000) (
input wire reset,
input wire clock,
output wire enable);
reg [31:0] count;
wire [31:0] next_count;
always @(posedge clock)
begin
if (reset)
count <= 32'b0;
else
count <= next_count;
end
assign enable = (count == DELAY - 1) ? 1'b1 : 1'b0;
assign next_count = (count == DELAY - 1) ? 32'b0 : count + 1;
endmodule |
module async_mem2(
input wire clkA,
input wire clkB,
input wire [asz-1:0] addrA,
input wire [asz-1:0] addrB,
input wire wr_csA,
input wire wr_csB,
input wire [7:0] wr_dataA,
input wire [7:0] wr_dataB,
output wire [7:0] rd_dataA,
output wire [7:0] rd_dataB
);
parameter asz = 15;
parameter depth = 32768;
reg [7:0] mem [0:depth-1];
always @(posedge clkA) begin
if (wr_csA)
mem[addrA] <= wr_dataA;
end
always @(posedge clkB) begin
if (wr_csB)
mem[addrB] <= wr_dataB;
end
assign rd_dataA = mem[addrA];
assign rd_dataB = mem[addrB];
endmodule |
module s6atlys(
// Global clock
input wire CLK_100M,
// onboard HDMI OUT
//output wire HDMIOUTCLKP,
//output wire HDMIOUTCLKN,
//output wire HDMIOUTD0P,
//output wire HDMIOUTD0N,
//output wire HDMIOUTD1P,
//output wire HDMIOUTD1N,
//output wire HDMIOUTD2P,
//output wire HDMIOUTD2N,
//output wire HDMIOUTSCL,
//output wire HDMIOUTSDA,
// LEDs
output wire [7:0] LED,
// Switches
input wire [7:0] SW,
// Buttons
input wire [5:0] BTN,
// PMOD Connector
inout wire [7:0] JB
);
//
// Initialize outputs -- remove these when they're actually used
//
// Audio output
//assign AUD_L = 0;
//assign AUD_R = 0;
// VGA output
//assign VGA_R = 0;
//assign VGA_G = 0;
//assign VGA_B = 0;
//assign VGA_HSYNC = 0;
//assign VGA_VSYNC = 0;
//
// Clocks (GameBoy clock runs at ~4.194304 MHz)
//
// FPGABoy runs at 33.33 MHz, mostly to simplify the video controller.
// Certain cycle sensitive modules, such as the CPU and Timer are
// internally clocked down to the GameBoy's normal speed.
//
// Core Clock: 33.33 MHz
wire coreclk, core_clock;
DCM_SP core_clock_dcm (.CLKIN(CLK_100M), .CLKFX(coreclk), .RST(1'b0));
defparam core_clock_dcm.CLKFX_DIVIDE = 6;
defparam core_clock_dcm.CLKFX_MULTIPLY = 2;
defparam core_clock_dcm.CLKDV_DIVIDE = 3.0;
defparam core_clock_dcm.CLKIN_PERIOD = 10.000;
BUFG core_clock_buf (.I(coreclk), .O(core_clock));
// Initial Reset
wire reset_init, reset;
SRL16 reset_sr(.D(1'b0), .CLK(core_clock), .Q(reset_init),
.A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1));
// HDMI Clocks
// TODO: No idea what these look like yet.
// Joypad Clock: 1 KHz
wire pulse_1khz;
reg clock_1khz;
divider#(.DELAY(33333)) div_1ms (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_1khz)
);
// CLS Clock: 200 Khz
wire pulse_200khz;
reg clock_200khz;
divider#(.DELAY(166)) div_5us (
.reset(reset_init),
.clock(core_clock),
.enable(pulse_200khz)
);
//
// CPU clock - overflows every 8 cycles
//
reg [2:0] clock_divider;
wire cpu_clock;
BUFG cpu_clock_buf(.I(clock_divider[2]), .O(cpu_clock));
//
// Switches
//
// SW0-SW4 - Breakpoints Switches (Not Implemented)
// SW5 - Step Clock
// SW6 - Step Enable
// SW7 - Power (Reset)
//
wire reset_sync, step_sync, step_enable;
debounce debounce_step_sync(reset_init, core_clock, SW[5], step_sync);
debounce debounce_step_enable(reset_init, core_clock, SW[6], step_enable);
debounce debounce_reset_sync(reset_init, core_clock, !SW[7], reset_sync);
assign reset = (reset_init || reset_sync);
// Game Clock
wire clock;
BUFGMUX clock_mux(.S(step_enable), .O(clock),
.I0(core_clock), .I1(step_sync));
//
// Buttons
//
// BTN0 - Not Implemented
// BTN1 - Joypad
// BTN2 - PC SP
// BTN3 - AF BC
// BTN4 - DE HL
//
reg [1:0] mode;
wire mode0_sync, mode1_sync, mode2_sync, mode3_sync;
debounce debounce_mode0_sync(reset_init, core_clock, BTN[2], mode0_sync);
debounce debounce_mode1_sync(reset_init, core_clock, BTN[3], mode1_sync);
debounce debounce_mode2_sync(reset_init, core_clock, BTN[4], mode2_sync);
debounce debounce_mode3_sync(reset_init, core_clock, BTN[1], mode3_sync);
//
// GameBoy
//
// GB <-> Cartridge + WRAM
wire [15:0] A;
wire [7:0] Di;
wire [7:0] Do;
wire wr_n, rd_n, cs_n;
// GB <-> VRAM
wire [15:0] A_vram;
wire [7:0] Di_vram;
wire [7:0] Do_vram;
wire wr_vram_n, rd_vram_n, cs_vram_n;
// GB <-> Display Adapter
wire [1:0] pixel_data;
wire pixel_clock;
wire pixel_latch;
wire hsync, vsync;
// GB <-> Joypad Adapter
wire [3:0] joypad_data;
wire [1:0] joypad_sel;
// GB <-> Audio Adapter
wire audio_left, audio_right;
// GB <-> CLS SPI
wire [15:0] PC;
wire [15:0] SP;
wire [15:0] AF;
wire [15:0] BC;
wire [15:0] DE;
wire [15:0] HL;
wire [15:0] A_cpu;
wire [7:0] Di_cpu;
wire [7:0] Do_cpu;
gameboy gameboy (
.clock(clock),
.cpu_clock(cpu_clock),
.reset(reset),
.reset_init(reset_init),
.A(A),
.Di(Di),
.Do(Do),
.wr_n(wr_n),
.rd_n(rd_n),
.cs_n(cs_n),
.A_vram(A_vram),
.Di_vram(Di_vram),
.Do_vram(Do_vram),
.wr_vram_n(wr_vram_n),
.rd_vram_n(rd_vram_n),
.cs_vram_n(cs_vram_n),
.pixel_data(pixel_data),
.pixel_clock(pixel_clock),
.pixel_latch(pixel_latch),
.hsync(hsync),
.vsync(vsync),
.joypad_data(joypad_data),
.joypad_sel(joypad_sel),
.audio_left(audio_left),
.audio_right(audio_right),
// debug output
.dbg_led(LED),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.A_cpu(A_cpu),
.Di_cpu(Di_cpu),
.Do_cpu(Do_cpu)
);
// Internal ROMs and RAMs
reg [7:0] tetris_rom [0:32767];
initial begin
$readmemh("data/tetris.hex", tetris_rom, 0, 32767);
end
wire [7:0] Di_wram;
// WRAM
async_mem #(.asz(8), .depth(8192)) wram (
.rd_data(Di_wram),
.wr_clk(clock),
.wr_data(Do),
.wr_cs(!cs_n && !wr_n),
.addr(A),
.rd_cs(!cs_n && !rd_n)
);
// VRAM
async_mem #(.asz(8), .depth(8192)) vram (
.rd_data(Di_vram),
.wr_clk(clock),
.wr_data(Do_vram),
.wr_cs(!cs_vram_n && !wr_vram_n),
.addr(A_vram),
.rd_cs(!cs_vram_n && !rd_vram_n)
);
assign Di = A[14] ? Di_wram : tetris_rom[A];
// Joypad Adapter
wire [15:0] joypad_state;
joypad_snes_adapter joypad_adapter(
.clock(clock_1khz),
.reset(reset),
.button_sel(joypad_sel),
.button_data(joypad_data),
.button_state(joypad_state),
.controller_data(JB[4]),
.controller_clock(JB[5]),
.controller_latch(JB[6])
);
cls_spi cls_spi(
.clock(clock_200khz),
.reset(reset),
.mode(mode),
.ss(JB[0]),
.mosi(JB[1]),
.miso(JB[2]),
.sclk(JB[3]),
.A(A_cpu),
.Di(Di_cpu),
.Do(Do_cpu),
.PC(PC),
.SP(SP),
.AF(AF),
.BC(BC),
.DE(DE),
.HL(HL),
.joypad_state(joypad_state)
);
// driver for divider clocks and debug elements
always @(posedge core_clock) begin
if (reset_init) begin
clock_1khz <= 1'b0;
clock_200khz <= 1'b0;
mode <= 2'b0;
end else begin
if (pulse_1khz)
clock_1khz <= !clock_1khz;
if (pulse_200khz)
clock_200khz <= !clock_200khz;
if (mode0_sync)
mode <= 2'b00;
else if (mode1_sync)
mode <= 2'b01;
else if (mode2_sync)
mode <= 2'b10;
else if (mode3_sync)
mode <= 2'b11;
end
end
always @(posedge clock) begin
if (reset_init) begin
clock_divider <= 1'b0;
end else begin
if (step_enable)
clock_divider <= clock_divider + 4;
else
clock_divider <= clock_divider + 1;
end
end
endmodule |
module gameboy (
input wire clock,
input wire cpu_clock,
input wire reset,
input wire reset_init,
// Main RAM + Cartridge
output wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
output wire wr_n,
output wire rd_n,
output wire cs_n,
// Video RAM
output wire [15:0] A_vram,
input wire [7:0] Di_vram,
output wire [7:0] Do_vram,
output wire wr_vram_n,
output wire rd_vram_n,
output wire cs_vram_n,
// Video Display
output wire [1:0] pixel_data,
output wire pixel_clock,
output wire pixel_latch,
output wire hsync,
output wire vsync,
// Controller
input wire [3:0] joypad_data,
output wire [1:0] joypad_sel,
// Audio
output wire audio_left,
output wire audio_right,
// Debug - CPU Pins
output wire [7:0] dbg_led,
output wire [15:0] PC,
output wire [15:0] SP,
output wire [15:0] AF,
output wire [15:0] BC,
output wire [15:0] DE,
output wire [15:0] HL,
output wire [15:0] A_cpu,
output wire [7:0] Di_cpu,
output wire [7:0] Do_cpu
);
//assign pixel_data = 2'b0;
assign pixel_clock = 1'b0;
//assign pixel_latch = 1'b0;
//assign hsync = 1'b0;
//assign vsync = 1'b0;
assign audio_left = 1'b0;
assign audio_right = 1'b0;
//
// CPU I/O Pins
//
wire reset_n, wait_n, int_n, nmi_n, busrq_n; // cpu inputs
wire m1_n, mreq_n, iorq_n, rd_cpu_n, wr_cpu_n, rfsh_n, halt_n, busak_n; // cpu outputs
//
// Debug - CPU I/O Pins
//
assign dbg_led = {
m1_n,
mreq_n,
iorq_n,
int_n,
halt_n,
reset_n,
rd_n,
wr_n
};
//
// CPU internal registers
//
wire IntE_FF1;
wire IntE_FF2;
wire INT_s;
//
// TV80 CPU
//
tv80s tv80_core(
.reset_n(reset_n),
.clk(cpu_clock),
.wait_n(wait_n),
.int_n(int_n),
.nmi_n(nmi_n),
.busrq_n(busrq_n),
.m1_n(m1_n),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_cpu_n),
.wr_n(wr_cpu_n),
.rfsh_n(rfsh_n),
.halt_n(halt_n),
.busak_n(busak_n),
.A(A_cpu),
.di(Di_cpu),
.do(Do_cpu),
.ACC(AF[15:8]),
.F(AF[7:0]),
.BC(BC),
.DE(DE),
.HL(HL),
.PC(PC),
.SP(SP),
.IntE_FF1(IntE_FF1),
.IntE_FF2(IntE_FF2),
.INT_s(INT_s)
);
assign reset_n = !reset;
assign wait_n = 1'b1;
assign nmi_n = 1'b1;
assign busrq_n = 1'b1;
//
// MMU
//
wire cs_interrupt;
wire cs_timer;
wire cs_sound;
wire cs_joypad;
wire [7:0] Do_mmu;
wire [7:0] Do_interrupt;
wire [7:0] Do_timer;
wire [7:0] Do_sound;
wire [7:0] Do_joypad;
wire [15:0] A_ppu;
wire [7:0] Do_ppu;
wire [7:0] Di_ppu;
wire cs_ppu;
mmu memory (
.clock(clock),
.reset(reset),
// CPU <-> MMU
.A_cpu(A_cpu),
.Di_cpu(Do_cpu),
.Do_cpu(Do_mmu),
.rd_cpu_n(rd_cpu_n),
.wr_cpu_n(wr_cpu_n),
// MMU <-> I/O Registers + External RAMs
.A(A),
.Do(Do),
.Di(Di),
.wr_n(wr_n),
.rd_n(rd_n),
.cs_n(cs_n),
// MMU <-> PPU
.A_ppu(A_ppu),
.Do_ppu(Do_ppu),
.Di_ppu(Di_ppu),
.cs_ppu(cs_ppu),
// Data lines (I/O Registers) -> MMU
.Do_interrupt(Do_interrupt),
.Do_timer(Do_timer),
.Do_sound(Do_sound),
.Do_joypad(Do_joypad),
// MMU -> Modules (I/O Registers)
.cs_interrupt(cs_interrupt),
.cs_timer(cs_timer),
.cs_sound(cs_sound),
.cs_joypad(cs_joypad)
);
//
// Interrupt Controller
//
wire[4:0] int_req;
wire[4:0] int_ack;
wire[7:0] jump_addr;
interrupt_controller interrupt(
.reset(reset),
.clock(clock),
.cs(cs_interrupt),
.rd_n(rd_n),
.wr_n(wr_n),
.m1_n(m1_n),
.int_n(int_n),
.iorq_n(iorq_n),
.int_ack(int_ack),
.int_req(int_req),
.jump_addr(jump_addr),
.A(A),
.Di(Do_cpu),
.Do(Do_interrupt)
);
// During an interrupts the CPU reads the jump address
// from a table in memory. It gets the address of this
// table from the interrupt module which is why this
// mux exists.
assign Di_cpu = (!iorq_n && !m1_n) ? jump_addr : Do_mmu;
//
// Timer Controller
//
timer_controller timer (
.reset(reset),
.clock(cpu_clock),
.cs(cs_timer),
.rd_n(rd_n),
.wr_n(wr_n),
.int_ack(int_ack[2]),
.int_req(int_req[2]),
.A(A),
.Di(Do_cpu),
.Do(Do_timer)
);
//
// Video Controller
//
video_controller video (
.reset(reset),
.clock(clock),
// Interrupts
.int_vblank_ack(int_ack[0]),
.int_vblank_req(int_req[0]),
.int_lcdc_ack(int_ack[1]),
.int_lcdc_req(int_req[1]),
// PPU <-> MMU
.A(A_ppu),
.Di(Do_ppu),
.Do(Di_ppu),
.rd_n(rd_n),
.wr_n(wr_n),
.cs(cs_ppu),
// PPU <-> VRAM
.A_vram(A_vram),
.Di_vram(Do_vram),
.Do_vram(Di_vram),
.rd_vram_n(rd_vram_n),
.wr_vram_n(wr_vram_n),
.cs_vram_n(cs_vram_n),
// LCD Output
.hsync(hsync),
.vsync(vsync),
.pixel_data(pixel_data),
.pixel_latch(pixel_latch)
//.pixel_clock(clock) // TODO ??
);
//
// Input Controller
//
joypad_controller joypad_controller (
.reset(reset),
.clock(clock),
.int_ack(int_ack[4]),
.int_req(int_req[4]),
.A(A),
.Di(Do_cpu),
.Do(Do_joypad),
.cs(cs_timer),
.rd_n(rd_n),
.wr_n(wr_n),
.button_sel(joypad_sel),
.button_data(joypad_data)
);
endmodule |
module video_controller (
input wire reset,
input wire clock,
// Interrupts
input wire int_vblank_ack,
output reg int_vblank_req,
input wire int_lcdc_ack,
output reg int_lcdc_req,
// VRAM + OAM + Registers (PPU <-> MMU)
input wire [15:0] A,
input wire [7:0] Di, // in from MMU
output wire [7:0] Do, // out to MMU
input wire rd_n,
input wire wr_n,
input wire cs,
// VRAM (PPU <-> VRAM)
output wire [15:0] A_vram,
output wire [7:0] Do_vram, // out to VRAM
input wire [7:0] Di_vram, // in from VRAM
output wire rd_vram_n,
output wire wr_vram_n,
output wire cs_vram_n,
// LCD Output -- TODO pixel clock?
output wire hsync,
output wire vsync,
output reg [7:0] line_count,
output reg [8:0] pixel_count,
output reg [7:0] pixel_data_count,
output reg [1:0] pixel_data,
output reg pixel_latch
);
///////////////////////////////////
//
// Video Registers
//
// LCDC - LCD Control (FF40) R/W
//
// Bit 7 - LCD Control Operation
// 0: Stop completeLY (no picture on screen)
// 1: operation
// Bit 6 - Window Screen Display Data Select
// 0: $9800-$9BFF
// 1: $9C00-$9FFF
// Bit 5 - Window Display
// 0: off
// 1: on
// Bit 4 - BG Character Data Select
// 0: $8800-$97FF
// 1: $8000-$8FFF <- Same area as OBJ
// Bit 3 - BG Screen Display Data Select
// 0: $9800-$9BFF
// 1: $9C00-$9FFF
// Bit 2 - OBJ Construction
// 0: 8*8
// 1: 8*16
// Bit 1 - Window priority bit
// 0: window overlaps all sprites
// 1: window onLY overlaps sprites whose
// priority bit is set to 1
// Bit 0 - BG Display
// 0: off
// 1: on
//
// STAT - LCDC Status (FF41) R/W
//
// Bits 6-3 - Interrupt Selection By LCDC Status
// Bit 6 - LYC=LY Coincidence (1=Select)
// Bit 5 - Mode 2: OAM-Search (1=Enabled)
// Bit 4 - Mode 1: V-Blank (1=Enabled)
// Bit 3 - Mode 0: H-Blank (1=Enabled)
// Bit 2 - Coincidence Flag
// 0: LYC not equal to LCDC LY
// 1: LYC = LCDC LY
// Bit 1-0 - Mode Flag (Current STATus of the LCD controller)
// 0: During H-Blank. Entire Display Ram can be accessed.
// 1: During V-Blank. Entire Display Ram can be accessed.
// 2: During Searching OAM-RAM. OAM cannot be accessed.
// 3: During Transfering Data to LCD Driver. CPU cannot
// access OAM and display RAM during this period.
//
// The following are typical when the display is enabled:
//
// Mode 0 000___000___000___000___000___000___000________________ H-Blank
// Mode 1 _______________________________________11111111111111__ V-Blank
// Mode 2 ___2_____2_____2_____2_____2_____2___________________2_ OAM
// Mode 3 ____33____33____33____33____33____33__________________3 Transfer
//
//
// The Mode Flag goes through the values 00, 02,
// and 03 at a cycle of about 109uS. 00 is present
// about 49uS, 02 about 20uS, and 03 about 40uS. This
// is interrupted every 16.6ms by the VBlank (01).
// The mode flag stays set at 01 for 1.1 ms.
//
// Mode 0 is present between 201-207 clks, 2 about 77-83 clks,
// and 3 about 169-175 clks. A complete cycle through these
// states takes 456 clks. VBlank lasts 4560 clks. A complete
// screen refresh occurs every 70224 clks.)
//
// SCY - Scroll Y (FF42) R/W
// Vertical scroll of background
//
// SCX - Scroll X (FF43) R/W
// Horizontal scroll of background
//
// LY - LCDC Y-Coordinate (FF44) R
// The LY indicates the vertical line to which
// the present data is transferred to the LCD
// Driver. The LY can take on any value between
// 0 through 153. The values between 144 and 153
// indicate the V-Blank period. Writing will
// reset the counter.
//
// This is just a RASTER register. The current
// line is thrown into here. But since there are
// no RASTERS on an LCD display it's called the
// LCDC Y-Coordinate.
//
// LYC - LY Compare (FF45) R/W
// The LYC compares itself with the LY. If the
// values are the same it causes the STAT to set
// the coincident flag.
//
// DMA (FF46)
// Implemented in the MMU
//
// BGP - BG Palette Data (FF47) W
//
// Bit 7-6 - Data for Dot Data 11
// Bit 5-4 - Data for Dot Data 10
// Bit 3-2 - Data for Dot Data 01
// Bit 1-0 - Data for Dot Data 00
//
// This selects the shade of gray you what for
// your BG pixel. Since each pixel uses 2 bits,
// the corresponding shade will be selected
// from here. The Background Color (00) lies at
// Bits 1-0, just put a value from 0-$3 to
// change the color.
//
// OBP0 - Object Palette 0 Data (FF48) W
// This selects the colors for sprite palette 0.
// It works exactLY as BGP ($FF47).
// See BGP for details.
//
// OBP1 - Object Palette 1 Data (FF49) W
// This selects the colors for sprite palette 1.
// It works exactLY as BGP ($FF47).
// See BGP for details.
//
// WY - Window Y Position (FF4A) R/W
// 0 <= WY <= 143
//
// WX - Window X Position + 7 (FF4B) R/W
// 7 <= WX <= 166
//
///////////////////////////////////
reg[7:0] LCDC;
wire[7:0] STAT;
reg[7:0] SCY;
reg[7:0] SCX;
reg[7:0] LYC;
reg[7:0] BGP;
reg[7:0] OBP0;
reg[7:0] OBP1;
reg[7:0] WY;
reg[7:0] WX;
// temp registers for r/rw mixtures
reg[4:0] STAT_w;
// timing params -- see STAT register
parameter PIXELS = 456;
parameter LINES = 154;
parameter HACTIVE_VIDEO = 160;
parameter HBLANK_PERIOD = 41;
parameter OAM_ACTIVE = 80;
parameter RAM_ACTIVE = 172;
parameter VACTIVE_VIDEO = 144;
parameter VBLANK_PERIOD = 10;
reg[1:0] mode;
parameter HBLANK_MODE = 0;
parameter VBLANK_MODE = 1;
parameter OAM_LOCK_MODE = 2;
parameter RAM_LOCK_MODE = 3;
reg[3:0] state;
parameter IDLE_STATE = 0;
parameter BG_ADDR_STATE = 1;
parameter BG_ADDR_WAIT_STATE = 2;
parameter BG_DATA_STATE = 3;
parameter BG_DATA_WAIT_STATE = 4;
parameter BG_PIXEL_COMPUTE_STATE = 8;
parameter BG_PIXEL_READ_STATE = 9;
parameter BG_PIXEL_WAIT_STATE = 10;
parameter BG_PIXEL_WRITE_STATE = 11;
parameter BG_PIXEL_HOLD_STATE = 12;
parameter SPRITE_POS_STATE = 13;
parameter SPRITE_POS_WAIT_STATE = 14;
parameter SPRITE_ATTR_STATE = 15;
parameter SPRITE_ATTR_WAIT_STATE = 16;
parameter SPRITE_DATA_STATE = 17;
parameter SPRITE_DATA_WAIT_STATE = 18;
parameter SPRITE_PIXEL_COMPUTE_STATE = 19;
parameter SPRITE_PIXEL_READ_STATE = 20;
parameter SPRITE_PIXEL_WAIT_STATE = 21;
parameter SPRITE_PIXEL_DRAW_STATE = 22;
parameter SPRITE_PIXEL_DATA_STATE = 23;
parameter SPRITE_WRITE_STATE = 24;
parameter SPRITE_HOLD_STATE = 25;
parameter PIXEL_WAIT_STATE = 26;
parameter PIXEL_READ_STATE = 27;
parameter PIXEL_READ_WAIT_STATE = 28;
parameter PIXEL_OUT_STATE = 29;
parameter PIXEL_OUT_HOLD_STATE = 30;
parameter PIXEL_INCREMENT_STATE = 31;
wire [7:0] next_line_count;
wire [8:0] next_pixel_count;
reg [7:0] tile_x_pos;
reg [7:0] tile_y_pos;
reg [4:0] tile_byte_pos1;
reg [4:0] tile_byte_pos2;
reg [3:0] tile_byte_offset1;
reg [3:0] tile_byte_offset2;
reg [7:0] tile_data1;
reg [7:0] tile_data2;
reg render_background;
reg [7:0] sprite_x_pos;
reg [7:0] sprite_y_pos;
reg [7:0] sprite_data1;
reg [7:0] sprite_data2;
reg [7:0] sprite_location;
reg [7:0] sprite_attributes;
reg [1:0] sprite_pixel;
reg [1:0] bg_pixel;
reg [2:0] sprite_pixel_num;
reg [7:0] sprite_palette;
reg [4:0] sprite_y_size;
reg [4:0] tile_col_num; // increments from 0 -> 31
reg [6:0] sprite_num; // increments from 0 -> 39
// OAM
reg [7:0] oam_addrA, oam_addrB;
wire [7:0] oam_outA, oam_outB;
wire wr_oam;
wire cs_oam;
async_mem2 #(.asz(8), .depth(160)) oam (
.clkA(clock),
.clkB(clock),
.addrA(oam_addrA),
.addrB(oam_addrB),
.rd_dataA(oam_outA),
.rd_dataB(oam_outB),
.wr_dataA(Di),
.wr_csA(wr_oam)
);
// VRAM
reg [12:0] vram_addrA, vram_addrB;
wire [7:0] vram_outA, vram_outB;
wire wr_vram;
wire cs_vram;
async_mem2 #(.asz(13), .depth(8192)) vram (
.clkA(clock),
.clkB(clock),
.addrA(vram_addrA),
.addrB(vram_addrB),
.rd_dataA(vram_outA),
.rd_dataB(vram_outB),
.wr_dataA(Di),
.wr_csA(wr_vram)
);
// Scanlines
reg [4:0] scanline1_addrA, scanline1_addrB;
reg [7:0] scanline1_inA, scanline1_inB;
wire [7:0] scanline1_outA, scanline1_outB;
reg wr_scanline1;
async_mem2 #(.asz(5), .depth(20)) scanline1 (
.clkA(clock),
.clkB(clock),
.addrA(scanline1_addrA),
.addrB(scanline1_addrB),
.rd_dataA(scanline1_outA),
.rd_dataB(scanline1_outB),
.wr_dataA(scanline1_inA),
.wr_dataB(scanline1_inB),
.wr_csA(wr_scanline1),
.wr_csB(wr_scanline1)
);
reg [4:0] scanline2_addrA, scanline2_addrB;
reg [7:0] scanline2_inA, scanline2_inB;
wire [7:0] scanline2_outA, scanline2_outB;
reg wr_scanline2;
async_mem2 #(.asz(5), .depth(20)) scanline2 (
.clkA(clock),
.clkB(clock),
.addrA(scanline2_addrA),
.addrB(scanline2_addrB),
.rd_dataA(scanline2_outA),
.rd_dataB(scanline2_outB),
.wr_dataA(scanline2_inA),
.wr_dataB(scanline2_inB),
.wr_csA(wr_scanline2),
.wr_csB(wr_scanline2)
);
// Registers
reg [7:0] Do_reg;
wire cs_reg;
// Clock -> CPU Clock Divider
wire clock_enable;
divider #(8) clock_divider(reset, clock, clock_enable);
always @(posedge clock)
begin
if (reset)
begin
// initialize registers
LCDC <= 8'h00; //91
SCY <= 8'h00; //4f
SCX <= 8'h00;
LYC <= 8'h00;
BGP <= 8'hFC; //fc
OBP0 <= 8'h00;
OBP1 <= 8'h00;
WY <= 8'h00;
WX <= 8'h00;
// reset internal registers
int_vblank_req <= 0;
int_lcdc_req <= 0;
mode <= 0;
state <= 0;
STAT_w <= 0;
pixel_count <= 0;
line_count <= 0;
end
else
begin
// memory r/w
if (cs)
begin
if (!rd_n)
begin
case (A)
16'hFF40: Do_reg <= LCDC;
16'hFF41: Do_reg <= STAT;
16'hFF42: Do_reg <= SCY;
16'hFF43: Do_reg <= SCX;
16'hFF44: Do_reg <= line_count;
16'hFF45: Do_reg <= LYC;
16'hFF47: Do_reg <= BGP;
16'hFF48: Do_reg <= OBP0;
16'hFF49: Do_reg <= OBP1;
16'hFF4A: Do_reg <= WX;
16'hFF4B: Do_reg <= WY;
endcase
end
else if (!wr_n)
begin
case (A)
16'hFF40: LCDC <= Di;
16'hFF41: STAT_w[4:0] <= Di[7:3];
16'hFF42: SCY <= Di;
16'hFF43: SCX <= Di;
//16'hFF44: line_count <= 0; // TODO: reset counter
16'hFF45: LYC <= Di;
16'hFF47: BGP <= Di;
16'hFF48: OBP0 <= Di;
16'hFF49: OBP1 <= Di;
16'hFF4A: WX <= Di;
16'hFF4B: WY <= Di;
endcase
end
end
// clear interrupts
if (int_vblank_ack)
int_vblank_req <= 0;
if (int_lcdc_ack)
int_lcdc_req <= 0;
if (LCDC[7]) // grapics enabled
begin
//////////////////////////////
// STAT INTERRUPTS AND MODE //
//////////////////////////////
// vblank -- mode 1
if (line_count >= VACTIVE_VIDEO)
begin
if (mode != VBLANK_MODE)
begin
int_vblank_req <= 1;
if (STAT[4])
int_lcdc_req <= 1;
end
mode <= VBLANK_MODE;
end
// oam lock -- mode 2
else if (pixel_count < OAM_ACTIVE)
begin
if (STAT[5] && mode != OAM_LOCK_MODE)
int_lcdc_req <= 1;
mode <= OAM_LOCK_MODE;
end
// ram + oam lock -- mode 3
else if (pixel_count < OAM_ACTIVE + RAM_ACTIVE)
begin
mode <= RAM_LOCK_MODE;
// does not generate an interrupt
end
// hblank -- mode 0
else
begin
if (STAT[3] && mode != HBLANK_MODE)
int_lcdc_req <= 1;
mode <= HBLANK_MODE;
end
// lyc interrupt
if (pixel_count == 0 && line_count == LYC)
begin
// stat bit set automatically
if (STAT[6])
int_lcdc_req <= 1;
end
/////////////////////
// RENDER GRAPHICS //
/////////////////////
case (state)
IDLE_STATE: begin
if (mode == RAM_LOCK_MODE) begin
tile_col_num <= 0;
sprite_num <= 0;
pixel_data_count <= 0;
state <= BG_ADDR_STATE;
end
end
// BACKGROUND
BG_ADDR_STATE: begin
// disable writes
wr_scanline1 <= 0;
wr_scanline2 <= 0;
// enable window
if (LCDC[5] && WY < line_count) begin
tile_x_pos <= { tile_col_num, 3'b0 } + (WX - 7);
tile_y_pos <= line_count - WY;
vram_addrA <= { (line_count - WY) >> 3, 5'b0 } +
(({tile_col_num, 3'b0} + (WX - 7)) >> 3) +
((LCDC[6]) ? 16'h1C00 : 16'h1800);
render_background <= 1;
state <= BG_ADDR_WAIT_STATE;
end
// enable background
else if (LCDC[0]) begin
tile_x_pos <= { tile_col_num, 3'b0 } + SCX;
tile_y_pos <= SCY + line_count;
vram_addrA <= { (SCY + line_count) >> 3, 5'b0 } +
(({tile_col_num, 3'b0} + (SCX)) >> 3) +
((LCDC[3]) ? 16'h1C00 : 16'h1800);
render_background <= 1;
state <= BG_ADDR_WAIT_STATE;
end
else begin
tile_x_pos <= { tile_col_num, 3'b0 };
tile_y_pos <= line_count;
render_background <= 0;
state <= BG_PIXEL_COMPUTE_STATE;
end
end
BG_ADDR_WAIT_STATE: begin
state <= BG_DATA_STATE;
end
BG_DATA_STATE: begin
vram_addrA <=
LCDC[4] ? 16'h0000 + { vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } :
{ vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } < 128 ?
16'h1000 + { vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } :
16'h1000 - (~({ vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 }) + 1);
vram_addrB <=
LCDC[4] ? 16'h0000 + { vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } + 1 :
{ vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } + 1 < 128 ?
16'h1000 + { vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } + 1 :
16'h1000 - (~({ vram_outA, 4'b0 } + { tile_y_pos[2:0], 1'b0 } + 1) + 1);
state <= BG_DATA_WAIT_STATE;
end
BG_DATA_WAIT_STATE: begin
state <= BG_PIXEL_COMPUTE_STATE;
end
BG_PIXEL_COMPUTE_STATE: begin
tile_data1 <= vram_outA;
tile_data2 <= vram_outB;
tile_byte_pos1 <= tile_x_pos >> 3;
tile_byte_pos2 <= ((tile_x_pos + 8) & 8'hFF) >> 3;
tile_byte_offset1 <= tile_x_pos[2:0];
tile_byte_offset2 <= 8 - tile_x_pos[2:0];
state <= BG_PIXEL_READ_STATE;
end
BG_PIXEL_READ_STATE: begin
scanline1_addrA <= tile_byte_pos1;
scanline1_addrB <= tile_byte_pos2;
scanline2_addrA <= tile_byte_pos1;
scanline2_addrB <= tile_byte_pos2;
state <= BG_PIXEL_WAIT_STATE;
end
BG_PIXEL_WAIT_STATE: begin
state <= BG_PIXEL_WRITE_STATE;
end
BG_PIXEL_WRITE_STATE: begin
// first byte
scanline1_inA <=
render_background ? scanline1_outA & (8'hFF << tile_byte_offset2) |
(tile_data1 >> tile_byte_offset1) : 0;
scanline2_inA <=
render_background ? scanline2_outA & (8'hFF << tile_byte_offset2) |
(tile_data2 >> tile_byte_offset1) : 0;
// second byte
scanline1_inB <=
render_background ? scanline1_outB & ~(8'hFF << tile_byte_offset2) |
(tile_data1 << tile_byte_offset2) : 0;
scanline2_inB <=
render_background ? scanline2_outB & ~(8'hFF << tile_byte_offset2) |
(tile_data2 << tile_byte_offset2) : 0;
// enable writes
wr_scanline1 <= tile_byte_pos1 < 20 ? 1 : 0;
wr_scanline2 <= tile_byte_pos2 < 20 ? 1 : 0;
state <= BG_PIXEL_HOLD_STATE;
end
BG_PIXEL_HOLD_STATE: begin
// increment col
if (tile_col_num == 31)
state <= SPRITE_POS_STATE;
else begin
tile_col_num <= tile_col_num + 1;
state <= BG_ADDR_STATE;
end
end
endcase
end else begin
mode <= HBLANK_MODE;
end
// failsafe -- if we somehow exceed the allotted cycles for rendering
//if (mode != RAM_LOCK_MODE && state < PIXEL_WAIT_STATE && state > IDLE_STATE)
// state <= PIXEL_WAIT_STATE;
if (mode < RAM_LOCK_MODE)
vram_addrA <= A - 16'h8000;
if (mode < OAM_LOCK_MODE)
oam_addrA <= A - 16'hFE00;
if (clock_enable) begin
pixel_count <= next_pixel_count;
line_count <= next_line_count;
end
end
end
assign next_pixel_count =
LCDC[7] ? (pixel_count == PIXELS - 1 ? 0 : pixel_count + 1) : 0;
assign next_line_count =
LCDC[7] ? (pixel_count == PIXELS - 1 ?
(line_count == LINES - 1 ? 0 : line_count + 1) : line_count) : 0;
assign hsync = (pixel_count > OAM_ACTIVE + RAM_ACTIVE + HACTIVE_VIDEO) ? 1'b1 : 1'b0;
assign vsync = (line_count > VACTIVE_VIDEO) ? 1'b1 : 1'b0;
assign cs_vram = cs && A >= 16'h8000 && A < 16'hA000;
assign cs_oam = cs && A >= 16'hFE00 && A < 16'hFEA0;
assign cs_reg = cs && cs_vram_n && !cs_oam;
assign wr_vram = cs_oam && !wr_n && mode != RAM_LOCK_MODE;
assign wr_oam = cs_oam && !wr_n && mode != RAM_LOCK_MODE && mode != OAM_LOCK_MODE;
assign STAT[7:3] = STAT_w[4:0]; // r/w
assign STAT[2] = (line_count == LYC) ? 1 : 0; // LYC Coincidence flag
assign STAT[1:0] = mode; // read only -- set internally
assign Do =
(cs_vram) ? vram_outA :
(cs_oam) ? oam_outA :
(cs_reg) ? Do_reg : 8'hFF;
endmodule |
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