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module timer_controller (
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire wr_n,
input wire rd_n,
input wire cs
);
////////////////////////////////////////////////
// Timer Registers
//
// DIV - Divider Register (FF04)
// Increments 16384 times a second
//
// TIMA - Timer Counter (FF05)
// Increments at frequency specified by TAC
//
// TMA - Timer Modulo (FF06)
// Value to load into TIMA on overflow
//
// TAC - Timer Control (FF07)
// Bit 2: 0 <= stop, 1 <= start
// Bit 1-0: 00 <= 4.096 KHz
// 01 <= 262.144 KHz
// 10 <= 65.536 KHz
// 11 <= 16.384 KHz
////////////////////////////////////////////////
reg[7:0] DIV;
reg[7:0] TIMA;
reg[7:0] TMA;
reg[7:0] TAC;
reg[7:0] reg_out;
parameter MAX_TIMER = 8'hFF;
wire enable;
wire e0, e1, e2, e3;
divider #(1024) d0(reset, clock, e0);
divider #(16) d1(reset, clock, e1);
divider #(64) d2(reset, clock, e2);
divider #(256) d3(reset, clock, e3);
always @(posedge clock)
begin
if (reset)
begin
DIV <= 8'h0;
TIMA <= 8'h0;
TMA <= 8'h0;
TAC <= 8'h0;
int_req <= 1'b0;
reg_out <= 8'h0;
end
else
begin
// Read / Write for registers
if (cs)
begin
if (!wr_n)
begin
case (A)
16'hFF04: DIV <= 8'h0;
16'hFF05: TIMA <= Di;
16'hFF06: TMA <= Di;
16'hFF07: TAC <= Di;
endcase
end
else if (!rd_n)
begin
case (A)
16'hFF04: reg_out <= DIV;
16'hFF05: reg_out <= TIMA;
16'hFF06: reg_out <= TMA;
16'hFF07: reg_out <= TAC;
endcase
end
end
// Clear overflow interrupt
if (int_ack)
int_req <= 1'b0;
// Increment timers
if (enable)
begin
if (TIMA == MAX_TIMER)
int_req <= 1'b1;
TIMA <= (TIMA == MAX_TIMER) ? TMA : TIMA + 1'b1;
end
if (e3)
begin
DIV <= DIV + 1'b1;
end
end
end
assign Do = (cs) ? reg_out : 8'hZZ;
assign enable =
(TAC[2] == 0) ? 1'b0 :
(TAC[1:0] == 0) ? e0 :
(TAC[1:0] == 1) ? e1 :
(TAC[1:0] == 2) ? e2 :
(TAC[1:0] == 3) ? e3 : 1'b0;
endmodule |
module joypad_controller(
input wire clock,
input wire reset,
input wire int_ack,
output reg int_req,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire rd_n,
input wire wr_n,
input wire cs,
output reg [1:0] button_sel,
input wire [3:0] button_data
);
////////////////////////////////////////////////
// Joypad Registers
//
// JOYP - Joypad (FF00)
// Bit 5: 0 <= select button keys (R/W)
// Bit 4: 0 <= select direction keys (R/W)
// Bit 3: 0 <= Down or Start
// Bit 2: 0 <= Up or Select
// Bit 1: 0 <= Left or B
// Bit 0: 0 <= Right or A
////////////////////////////////////////////////
always @(posedge clock) begin
if (reset)
int_req <= 0;
else begin
if (!wr_n) begin
if (A == 16'hFF00)
button_sel <= Di[5:4];
end
end
end
assign Do = (cs) ? { 2'b11, button_sel[1:0], button_data[3:0] } : 8'hFF;
endmodule |
module interrupt_controller (
input wire clock,
input wire reset,
input wire m1_n,
input wire iorq_n,
output wire int_n,
input wire [4:0] int_req,
output reg [4:0] int_ack,
output wire [7:0] jump_addr,
input wire [15:0] A,
input wire [7:0] Di,
output wire [7:0] Do,
input wire wr_n,
input wire rd_n,
input wire cs
);
//////////////////////////////////////
// Interrupt Registers
//
// IF - Interrupt Flag (FF0F)
// Bit 4: New Value on Selected Joypad Keyline(s) (rst 60)
// Bit 3: Serial I/O transfer end (rst 58)
// Bit 2: Timer Overflow (rst 50)
// Bit 1: LCD (see STAT) (rst 48)
// Bit 0: V-Blank (rst 40)
//
// IE - Interrupt Enable (FFFF)
// Bit 4: New Value on Selected Joypad Keyline(s)
// Bit 3: Serial I/O transfer end
// Bit 2: Timer Overflow
// Bit 1: LCDC (see STAT)
// Bit 0: V-Blank
//
// 0 <= disable
// 1 <= enable
//////////////////////////////////////
wire[7:0] IF;
reg[7:0] IE;
parameter POLL_STATE = 0;
parameter WAIT_STATE = 1;
parameter ACK_STATE = 2;
parameter CLEAR_STATE = 3;
parameter VBLANK_INT = 0;
parameter LCDC_INT = 1;
parameter TIMER_INT = 2;
parameter SERIAL_INT = 3;
parameter INPUT_INT = 4;
parameter VBLANK_JUMP = 8'hA0; // 8'h40;
parameter LCDC_JUMP = 8'hA2; // 8'h48;
parameter TIMER_JUMP = 8'hA4; // 8'h50;
parameter SERIAL_JUMP = 8'hA6; // 8'h58;
parameter INPUT_JUMP = 8'hA8; // 8'h60;
reg[1:0] state;
reg[2:0] interrupt;
reg[7:0] reg_out;
always @(posedge clock)
begin
if (reset)
begin
IE <= 8'h0;
state <= POLL_STATE;
end
else
begin
// Read / Write for registers
if (cs)
begin
if (!wr_n)
begin
case (A)
16'hFFFF: IE <= Di;
endcase
end
else if (!rd_n)
begin
case (A)
16'hFF0F: reg_out <= IF;
16'hFFFF: reg_out <= IE;
endcase
end
end
case (state)
POLL_STATE:
begin
if (IF[VBLANK_INT] && IE[VBLANK_INT])
begin
interrupt <= VBLANK_INT;
state <= WAIT_STATE;
end
else if (IF[LCDC_INT] && IE[LCDC_INT])
begin
interrupt <= LCDC_INT;
state <= WAIT_STATE;
end
else if (IF[TIMER_INT] && IE[TIMER_INT])
begin
interrupt <= TIMER_INT;
state <= WAIT_STATE;
end
else if (IF[SERIAL_INT] && IE[SERIAL_INT])
begin
interrupt <= SERIAL_INT;
state <= WAIT_STATE;
end
else if (IF[INPUT_INT] && IE[INPUT_INT])
begin
interrupt <= INPUT_INT;
state <= WAIT_STATE;
end
end
WAIT_STATE:
begin
if (!m1_n && !iorq_n)
state <= ACK_STATE;
end
ACK_STATE:
begin
int_ack[interrupt] <= 1'b1;
state <= CLEAR_STATE;
end
CLEAR_STATE:
begin
int_ack[interrupt] <= 1'b0;
if (m1_n || iorq_n)
state <= POLL_STATE;
end
endcase
end
end
assign IF = int_req; // this makes the value read only
assign Do = (cs) ? reg_out : 8'hFF;
assign int_n = (state == WAIT_STATE) ? 1'b0 : 1'b1; // active low
assign jump_addr =
(interrupt == VBLANK_INT) ? VBLANK_JUMP :
(interrupt == LCDC_INT) ? LCDC_JUMP :
(interrupt == TIMER_INT) ? TIMER_JUMP :
(interrupt == SERIAL_INT) ? SERIAL_JUMP :
(interrupt == INPUT_INT) ? INPUT_JUMP : 8'hZZ;
endmodule |
module mmu(
input wire clock,
input wire reset,
// CPU
input wire [15:0] A_cpu,
input wire [7:0] Di_cpu, // should be Do from cpu
output wire [7:0] Do_cpu, // should be mux'd to cpu's Di
input wire rd_cpu_n,
input wire wr_cpu_n,
// Main RAM (Cartridge + WRAM)
output wire [15:0] A,
output wire [7:0] Do,
input wire [7:0] Di,
output wire wr_n,
output wire rd_n,
output wire cs_n,
// PPU (VRAM + OAM + Registers)
output wire [15:0] A_ppu,
output wire [7:0] Do_ppu,
input wire [7:0] Di_ppu,
output wire rd_ppu_n,
output wire wr_ppu_n,
output wire cs_ppu,
// I/O Registers (except for PPU)
input wire [7:0] Do_interrupt,
input wire [7:0] Do_timer,
input wire [7:0] Do_sound,
input wire [7:0] Do_joypad,
output wire cs_interrupt,
output wire cs_timer,
output wire cs_sound,
output wire cs_joypad
);
// internal data out pins
wire [7:0] Do_high_ram;
// internal r/w enables
wire cs_boot_rom;
wire cs_jump_rom;
wire cs_high_ram;
// remapped addresses
wire [6:0] A_jump_rom;
wire [6:0] A_high_ram;
// when 8'h01 gets written into FF50h the ROM is disabled
reg boot_rom_enable;
// Internal ROMs
reg [7:0] boot_rom [0:255];
reg [7:0] jump_rom [0:9];
initial begin
$readmemh("data/boot.hex", boot_rom, 0, 255);
$readmemh("data/jump.hex", jump_rom, 0, 9);
end
// High RAM
async_mem #(.asz(8), .depth(127)) high_ram (
.rd_data(Do_high_ram),
.wr_clk(clock),
.wr_data(Di_cpu),
.wr_cs(cs_high_ram && !wr_n),
.addr(A_high_ram),
.rd_cs(cs_high_ram)
);
always @ (posedge clock)
begin
if (reset)
begin
boot_rom_enable <= 1;
end
else
begin
if (!wr_n)
begin
case(A)
16'hFF46:
begin
// TODO: DMA
end
16'hFF50: if (Di == 8'h01) boot_rom_enable <= 1'b0;
endcase
end
end
end
// selector flags
assign cs_n = (A < 16'hFE00) ? 1'b0 : 1'b1; // echo of internal ram
assign cs_ppu =
(A >= 16'h8000 && A < 16'hA000) || // VRAM
(A >= 16'hFE00 && A < 16'hFEA0) || // OAM
(A >= 16'hFF40 && A <= 16'hFF4B && A != 16'hFF46); // registers (except for DMA)
assign cs_boot_rom = boot_rom_enable && A < 16'h0100;
assign cs_jump_rom = A >= 16'hFEA0 && A < 16'hFF00;
assign cs_high_ram = A >= 16'hFF80 && A < 16'hFFFF;
assign cs_interrupt = A == 16'hFF0F || A == 16'hFFFF;
assign cs_sound = A >= 16'hFF10 && A <= 16'hFF3F; // there are some gaps here
assign cs_timer = A >= 16'hFF04 && A <= 16'hFF07;
assign cs_joypad = A == 16'hFF00;
// remap internal addresses
assign A_jump_rom = A - 16'hFEA0;
assign A_high_ram = A - 16'hFF80;
// Main RAM + Cartridge
assign A = A_cpu;
assign Do = Di_cpu;
assign wr_n = wr_cpu_n;
assign rd_n = rd_cpu_n;
// PPU
assign A_ppu = A_cpu;
assign Do_ppu = Di_cpu;
assign wr_ppu_n = wr_cpu_n;
assign rd_ppu_n = rd_cpu_n;
assign Do_cpu =
(cs_boot_rom) ? boot_rom[A_cpu] :
(cs_high_ram) ? Do_high_ram :
(cs_jump_rom) ? jump_rom[A_jump_rom] :
(cs_interrupt) ? Do_interrupt :
(cs_timer) ? Do_timer :
(cs_sound) ? Do_sound :
(cs_joypad) ? Do_joypad :
(cs_ppu) ? Do_ppu :
(!cs_n) ? Di : 8'hFF;
endmodule |
module video_converter (
input wire reset,
input wire clock,
// gameboy signals
input wire [1:0] pixel_data,
input wire hsync, // active high
input wire vsync, // active high
input wire data_latch,
// vga signals
input wire pixel_clock,
output wire [23:0] vga_rgb,
output wire vga_hsync,
output wire vga_vsync
);
// game boy screen size
parameter GB_SCREEN_WIDTH = 10'd160;
parameter GB_SCREEN_HEIGHT = 10'd144;
// toggle for which is the front buffer
// 0 -> buffer1 is front buffer
// 1 -> buffer2 is front buffer
reg front_buffer;
wire[14:0] write_addr;
wire[1:0] read_data;
wire[14:0] b1_addr;
wire b1_clk;
wire[1:0] b1_din;
wire[1:0] b1_dout;
wire b1_we; // active high
wire[14:0] b2_addr;
wire b2_clk;
wire[1:0] b2_din;
wire[1:0] b2_dout;
wire b2_we; // active high
reg[1:0] last_pixel_data;
reg[14:0] last_write_addr;
assign b1_we = front_buffer ? (data_latch) : 0;
assign b2_we = front_buffer ? 0 : (data_latch);
assign read_data = (front_buffer) ? b2_dout : b1_dout;
assign b1_din = (front_buffer) ? pixel_data : 0;
assign b2_din = (front_buffer) ? 0 : pixel_data;
BUFGMUX clock_mux_b1(.S(front_buffer), .O(b1_clk),
.I0(pixel_clock), .I1(clock));
BUFGMUX clock_mux_b2(.S(front_buffer), .O(b2_clk),
.I0(clock), .I1(pixel_clock));
// internal buffer ram
frame_buffer buffer1(
b1_addr,
b1_clk,
b1_din,
b1_dout,
b1_we
);
frame_buffer buffer2(
b2_addr,
b2_clk,
b2_din,
b2_dout,
b2_we
);
reg gb_last_vsync;
reg gb_last_hsync;
reg gb_last_latch;
reg [7:0] gb_line_count;
reg [7:0] gb_pixel_count;
// handle writing into the back_buffer
always @ (posedge clock)
begin
if(reset)
begin
front_buffer <= 1'b0;
gb_last_vsync <= 1'b0;
gb_last_hsync <= 1'b0;
gb_last_latch <= 1'b0;
end
else
begin
gb_last_vsync <= vsync;
gb_last_hsync <= hsync;
gb_last_latch <= data_latch;
end
// negedge hsync
if (gb_last_hsync && !hsync)
begin
gb_line_count <= gb_line_count + 1;
end
// negedge data_latch
if (gb_last_latch && !data_latch)
begin
gb_pixel_count <= gb_pixel_count + 1;
end
// posedge vsync
if(!gb_last_vsync && vsync)
begin
front_buffer <= !front_buffer;
gb_line_count <= 0;
gb_pixel_count <= 0;
end
end
// handle output to the vga module
wire [9:0] pixel_count, line_count;
vga_controller vgac(pixel_clock, reset, vga_hsync, vga_vsync, pixel_count, line_count);
// write to our current counter
assign write_addr = gb_line_count * 160 + gb_pixel_count;
parameter X_OFFSET = 160;
parameter Y_OFFSET = 76;
// read from where the vga wants to read
wire[14:0] buffer_pos = ((line_count - Y_OFFSET) >> 1) * 160 + ((pixel_count - X_OFFSET) >> 1);
assign b1_addr = (front_buffer) ? write_addr : buffer_pos;
assign b2_addr = (front_buffer) ? buffer_pos : write_addr;
// generate a gameboy color
// 00 -> white
// 01 -> light gray
// 10 -> dark gray
// 11 -> black
wire [7:0] my_color = (pixel_count >= X_OFFSET && line_count >= Y_OFFSET && pixel_count < X_OFFSET + 320 && line_count < Y_OFFSET + 288) ?
(read_data == 2'b00) ? 8'b11111111 :
((read_data == 2'b01) ? 8'b10101010 :
((read_data == 2'b10) ? 8'b01010101 : 8'b00000000)) : 8'b00000000;
assign vga_rgb = { my_color, my_color, my_color };
endmodule |
module joypad_snes_adapter_tb;
// Inputs
reg clock;
reg reset;
wire [1:0] button_sel;
wire controller_data;
// Outputs
wire [3:0] button_data;
wire controller_latch;
wire controller_clock;
// Instantiate the Unit Under Test (UUT)
joypad_snes_adapter uut (
.clock(clock),
.reset(reset),
.button_sel(button_sel),
.button_data(button_data),
.controller_data(controller_data),
.controller_latch(controller_latch),
.controller_clock(controller_clock)
);
assign button_sel = 2'b0;
assign controller_data = 1'b0;
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
// Wait 100 ns for module reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule |
module joypad_snes_adapter(
input wire clock,
input wire reset,
// to gameboy
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
// to controller
input wire controller_data,
output wire controller_latch,
output wire controller_clock
);
////////////////////////////////////////////////////////
// http://www.gamefaqs.com/snes/916396-snes/faqs/5395
//
// Note: This implementation does *not* match the
// timings specified in the documentation above.
// Instead, it uses a much simpler and slower 1KHz
// clock which provides pretty good responsiveness
// to button presses. Also note that the Atlys board
// only provides a 3.3V Vcc instead of the spec'd 5V.
//
// Note: Color of wires on my controller ext. cable
// Vcc (+5V) - Green
// Clock - Blue
// Latch - Yellow
// Data - Red
// Ground - Brown
////////////////////////////////////////////////////////
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
//reg [15:0] button_state;
/**
* State transitions occur on the clock's positive edge.
*/
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
/**
* Button reading occurs on the negative edge to give
* values from the controller time to settle.
*/
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
// button order is
// B Y SELECT START UP DOWN LEFT RIGHT A X L R - - - -
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule |
module vga_controller(pixel_clock, reset, hsync, vsync, pixel_count, line_count);
input pixel_clock;
input reset;
output hsync;
output vsync;
output [9:0] pixel_count;
output [9:0] line_count;
// output registers
reg hsync, vsync;
reg [9:0] pixel_count, line_count;
wire [9:0] next_pixel, next_line;
// parameters
// 800x525 pixels for 640x480 display
parameter NUM_LINES = 525;
parameter NUM_PIXELS = 800;
// visible parameters
parameter WIDTH = 640;
parameter HEIGHT = 480;
// horizontal parameters (pixels)
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
// vertical parameters (lines)
parameter V_FRONT_PORCH = 11;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 32;
always @(posedge pixel_clock) begin
if(reset) begin
pixel_count <= 10'b0;
line_count <= 10'b0;
hsync <= 1;
vsync <= 1;
end else begin
pixel_count <= next_pixel;
line_count <= next_line;
// output synchronization signals
hsync <= ~((next_pixel >= WIDTH + H_FRONT_PORCH) &
(next_pixel < WIDTH + H_FRONT_PORCH + H_SYNC));
vsync <= ~((next_line >= HEIGHT + V_FRONT_PORCH) &
(next_line < HEIGHT + V_FRONT_PORCH + V_SYNC));
end
end
// next pixel and line
assign next_pixel = (pixel_count >= NUM_PIXELS - 1) ? 1'b0 : pixel_count + 1'b1;
assign next_line = (pixel_count >= NUM_PIXELS - 1) ?
((line_count >= NUM_LINES - 1) ? 1'b0 : line_count + 1'b1) : line_count;
endmodule |
module oled_spi(
input wire clock,
input wire reset,
input wire shutdown,
output wire cs,
output reg sdin,
output wire sclk,
output reg dc,
output reg res,
output reg vbatc,
output reg vddc
);
parameter WAIT = 1;
parameter SEND = 2; // send 1 byte
parameter SEND2 = 3; // send 2 bytes
parameter SEND3 = 4; // send 3 bytes
parameter SEND4 = 5; // send 4 bytes
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter STARTUP_5 = 14;
parameter STARTUP_6 = 15;
parameter STARTUP_7 = 16;
parameter STARTUP_8 = 17;
parameter STARTUP_9 = 18;
parameter SHUTDOWN_1 = 6;
parameter SHUTDOWN_2 = 7;
parameter SHUTDOWN_3 = 8;
reg [31:0] send_buf;
reg [4:0] send_idx;
reg [1:0] send_ctr;
reg [1:0] send_max;
reg [31:0] wait_ctr;
reg [31:0] wait_max;
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 32'b0;
send_idx <= 5'b0;
send_ctr <= 2'b0;
send_max <= 2'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 1'b0;
sdin <= 1'b0;
dc <= 1'b0;
res <= 1'b1;
vddc <= 1'b1;
vbatc <= 1'b1;
end
// SHUTDOWN
else if (shutdown) begin
if (state > 0 && state < 10) begin
next_state <= SHUTDOWN_1;
end else begin
state <= SHUTDOWN_1;
end
end
// STATES
else begin
// SEND - send up to four serial bytes
if (state == SEND) begin
sdin <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7 && send_ctr == send_max) begin
send_idx <= 0;
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else if (send_idx == 7) begin
send_idx <= 0;
send_ctr <= send_ctr + 1;
end else begin
send_idx <= send_idx + 1;
end
end
// SEND2 - send two bytes
if (state == SEND2) begin
send_max = 1;
state <= SEND;
end
// SEND3 - send three bytes
else if (state == SEND3) begin
send_max = 2;
state <= SEND;
end
// SEND4 - send four bytes
else if (state == SEND4) begin
send_max = 3;
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- apply power to VDD
else if (state == STARTUP_1) begin
dc <= 0;
vddc <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_2;
end
// STARTUP_2 -- send display off cmd
else if (state == STARTUP_2) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- clear screen
else if (state == STARTUP_3) begin
res <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set charge pump
else if (state == STARTUP_4) begin
res <= 1;
send_buf <= 16'h148D;
state <= SEND2;
next_state <= STARTUP_5;
end
// STARTUP_5 -- set pre-charge period
else if (state == STARTUP_5) begin
send_buf <= 16'hF1D9;
state <= SEND2;
next_state <= STARTUP_6;
end
// STARTUP_6 -- apply power to VBAT
else if (state == STARTUP_6) begin
vbatc <= 0;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= STARTUP_7;
end
// STARTUP_7 -- invert the display
else if (state == STARTUP_7) begin
send_buf <= 16'hC8A1;
state <= SEND2;
next_state <= STARTUP_8;
end
// STARTUP_8 -- select squential COM configuration
else if (state == STARTUP_8) begin
send_buf <= 16'h20DA;
state <= SEND2;
next_state <= STARTUP_9;
end
// STARTUP_9 -- send display on cmd
else if (state == STARTUP_9) begin
send_buf <= 8'hAF;
state <= SEND;
next_state <= 0; // TODO
end
// SHUTDOWN_1 -- send display off cmd
else if (state == SHUTDOWN_1) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= SHUTDOWN_2;
end
// SHUTDOWN_2 -- turn off VBAT
else if (state == SHUTDOWN_2) begin
vbatc <= 1;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= SHUTDOWN_3;
end
// SHUTDOWN_4 -- turn off VDD
else if (state == SHUTDOWN_3) begin
vddc <= 1;
state <= 0; // TODO
end
end
end
assign cs = 0;
assign sclk = !clock;
endmodule |
module cls_spi(
input wire clock,
input wire reset,
input wire [15:0] A,
input wire [7:0] Di,
input wire [7:0] Do,
input wire [15:0] PC,
input wire [15:0] SP,
input wire [15:0] AF,
input wire [15:0] BC,
input wire [15:0] DE,
input wire [15:0] HL,
input wire [15:0] joypad_state,
input wire [1:0] mode,
output wire ss,
output reg mosi,
input wire miso,
output wire sclk
);
parameter WAIT = 1;
parameter SEND = 2;
parameter SEND_2 = 3;
parameter SEND_3 = 4;
parameter SEND_4 = 5;
parameter SEND_5 = 6;
parameter SENDHEX = 7;
parameter SENDJOYPAD = 8;
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter LOOP_1 = 20;
parameter LOOP_2 = 21;
parameter LOOP_3 = 22;
parameter LOOP_4 = 23;
parameter LOOP_5 = 24;
parameter LOOP_6 = 25;
parameter LOOP_7 = 26;
parameter LOOP_8 = 27;
parameter LOOP_9 = 28;
parameter LOOP_10 = 29;
parameter LOOP_11 = 30;
parameter LOOP_7b = 31;
parameter LOOP_8b = 32;
reg [63:0] send_buf; // send buffer (8 bytes)
reg [2:0] send_idx; // current bit (0h-7h)
reg [2:0] send_ctr; // current byte (0h-7h)
reg [2:0] send_max; // total bytes (0h-7h)
reg [31:0] wait_ctr; // current cycle
reg [31:0] wait_max; // total cycles
reg [2:0] hex_idx; // current word
reg [3:0] btn_idx; // current joypad button
reg [1:0] mode_latch; // 0-PCSP, 1-AFBC, 2-DEHL
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
reg [7:0] next_state_hex;
reg [7:0] next_state_btn;
reg ss_enable;
reg sclk_enable;
reg [7:0] glyph_rom [15:0];
reg [31:0] data;
reg [1:0] data_idx;
initial begin
$readmemh("data/hexascii.hex", glyph_rom, 0, 15);
end
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 64'b0;
send_idx <= 3'b0;
send_ctr <= 3'b0;
send_max <= 3'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 8'b0;
next_state_hex <= 8'b0;
next_state_btn <= 8'b0;
mode_latch <= 2'b0;
hex_idx <= 3'b0;
btn_idx <= 4'b0;
data <= 32'b0;
data_idx <= 2'b0;
ss_enable <= 0;
sclk_enable <= 0;
mosi <= 1'b0;
end
// STATES
else begin
// SEND - send up to eight serial bytes
if (state == SEND) begin
ss_enable <= 1;
state <= SEND_2;
end
else if (state == SEND_2) begin
state <= SEND_3;
end
else if (state == SEND_3) begin
mosi <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7) begin
send_idx <= 0;
state <= SEND_4;
end else begin
sclk_enable <= 1;
send_idx <= send_idx + 1;
end
end
else if (state == SEND_4) begin
mosi <= 0;
state <= SEND_5;
end
else if (state == SEND_5) begin
sclk_enable <= 0;
ss_enable <= 0;
if (send_ctr == send_max) begin
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else begin
send_ctr <= send_ctr + 1;
state <= SEND;
end
end
// SENDHEX - send a glyph corresponding to a hex value
else if (state == SENDHEX) begin
send_buf <= glyph_rom[(data >> ({hex_idx, 2'b00})) & 4'hF];
send_max <= 0;
if (hex_idx == 0) begin
next_state <= next_state_hex;
end else begin
next_state <= SENDHEX;
hex_idx <= hex_idx - 1;
end
state <= SEND;
end
// SENDJOYPAD - send a glyph corresponding to a joypad button
else if (state == SENDJOYPAD) begin
case (btn_idx)
0: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h42; // B
1: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h59; // Y
2: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h73; // Select
3: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h53; // Start
4: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h5E; // Up
5: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h64; // Down
6: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3C; // Left
7: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3E; // Right
8: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h41; // A
9: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h58; // X
10: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h4C; // L
11: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h52; // R
default: send_buf <= 8'h20;
endcase
send_max <= 0;
if (btn_idx == 15) begin
btn_idx <= 4'b0;
next_state <= next_state_btn;
end else begin
next_state <= SENDJOYPAD;
btn_idx <= btn_idx + 1;
end
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- send display on, backlight on cmd
else if (state == STARTUP_1) begin
send_buf <= 32'h65335B1B; // ESC BRACKET '3' 'e'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_2;
end
// STARTUP_2 -- clear the display
else if (state == STARTUP_2) begin
send_buf <= 32'h6A305B1B; // ESC BRACKET '0' 'j'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- set the cursor mode
else if (state == STARTUP_3) begin
send_buf <= 32'h63305B1B; // ESC BRACKET '0' 'c'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set the display mode
else if (state == STARTUP_4) begin
send_buf <= 32'h68305B1B; // ESC BRACKET '0' 'h'
send_max <= 3;
state <= SEND;
next_state <= LOOP_1;
end
// LOOP_1 -- set cursor to 0,0
else if (state == LOOP_1) begin
send_buf <= 48'h48303B305B1B; // ESC BRACKET '0' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= LOOP_2;
mode_latch <= mode;
end
else if (state == LOOP_2) begin
send_buf <= 24'h3A4120; // A:
send_max <= 2;
state <= SEND;
next_state <= LOOP_3;
end
else if (state == LOOP_3) begin
data <= A;
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_4;
end
else if (state == LOOP_4) begin
send_buf <= 32'h3A4f4920; // IO:
send_max <= 3;
state <= SEND;
next_state <= LOOP_5;
end
else if (state == LOOP_5) begin
data <= { Di, Do };
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_6;
end
else if (state == LOOP_6) begin
send_buf <= 48'h48303B315B1B; // ESC BRACKET '1' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= mode_latch == 2'b11 ? LOOP_7b : LOOP_7;
end
else if (state == LOOP_7) begin
case (mode_latch)
2'b00: send_buf <= 24'h3A4350; // PC:
2'b01: send_buf <= 24'h3A4641; // AF:
2'b10: send_buf <= 24'h3A4544; // DE:
endcase
send_max <= 2;
state <= SEND;
next_state <= LOOP_8;
end
else if (state == LOOP_8) begin
case (mode_latch)
2'b00: data <= PC;
2'b01: data <= AF;
2'b10: data <= DE;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_9;
end
else if (state == LOOP_9) begin
case (mode_latch)
2'b00: send_buf <= 32'h3A505320; // SP:
2'b01: send_buf <= 32'h3A434220; // BC:
2'b10: send_buf <= 32'h3A4C4820; // HL:
endcase
send_max <= 3;
state <= SEND;
next_state <= LOOP_10;
end
else if (state == LOOP_10) begin
case (mode_latch)
2'b00: data <= SP;
2'b01: data <= BC;
2'b10: data <= HL;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_11;
end
else if (state == LOOP_7b) begin
send_buf <= 16'h2020;
send_max <= 1;
state <= SEND;
next_state <= LOOP_8b;
end
else if (state == LOOP_8b) begin
state <= SENDJOYPAD;
next_state_btn <= LOOP_11;
end
else if (state == LOOP_11) begin
wait_max <= 10;
state <= WAIT;
next_state <= LOOP_1;
end
end
end
assign ss = (ss_enable) ? 1'b0 : 1'b1;
assign sclk = (sclk_enable) ? !clock : 1'b1;
endmodule |
module oled_spi_tb;
// Inputs
reg clock;
reg reset;
reg shutdown;
// Outputs
wire cs;
wire sdin;
wire sclk;
wire dc;
wire res;
wire vbatc;
wire vddc;
// Instantiate the Unit Under Test (UUT)
oled_spi uut (
.clock(clock),
.reset(reset),
.shutdown(shutdown),
.cs(cs),
.sdin(sdin),
.sclk(sclk),
.dc(dc),
.res(res),
.vbatc(vbatc),
.vddc(vddc)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
shutdown = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule |
module cls_spi_tb;
// Inputs
reg clock;
reg reset;
reg [31:0] data;
reg miso;
// Outputs
wire ss;
wire mosi;
wire sclk;
// Instantiate the Unit Under Test (UUT)
cls_spi uut (
.clock(clock),
.reset(reset),
.data(data),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sclk(sclk)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
data = 32'h89ABCDEF;
miso = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule |
module pla_8721(
input rom_256,
input va14,
input charen,
input hiram,
input loram,
input ba,
input vma5,
input vma4,
input ms0,
input ms1,
input ms2,
input ms3,
input z80io,
input z80en,
input exrom,
input game,
input rw,
input aec,
input dmaack,
input vicfix,
input a10,
input a11,
input a12,
input a13,
input a14,
input a15,
input clk,
output sden,
output roml,
output romh,
output clrbnk,
output from,
output rom4,
output rom3,
output rom2,
output rom1,
output iocs,
output dir,
output reg dwe,
output reg casenb,
output vic,
output ioacc,
output gwe,
output colram,
output charom);
wire p0;
wire p1;
wire p2;
wire p3;
wire p4;
wire p5;
wire p6;
wire p7;
wire p8;
wire p9;
wire p10;
wire p11;
wire p12;
wire p13;
wire p14;
wire p15;
wire p16;
wire p17;
wire p18;
wire p19;
wire p20;
wire p21;
wire p22;
wire p23;
wire p24;
wire p25;
wire p26;
wire p27;
wire p28;
wire p29;
wire p30;
wire p31;
wire p32;
wire p33;
wire p34;
wire p35;
wire p36;
wire p37;
// p38 removed
wire p39;
wire p40;
wire p41;
wire p42;
wire p43;
wire p44;
wire p45;
wire p46;
wire p47;
wire p48;
wire p49;
wire p50;
wire p51;
wire p52;
wire p53;
wire p54;
wire p55;
wire p56;
wire p57;
wire p58;
wire p59;
wire p60;
wire p61;
wire p62;
wire p63;
wire p64;
wire p65;
wire p66;
wire p67;
wire p68;
wire p69;
wire p70;
wire p71;
wire p72;
// p73 removed
wire p74;
wire p75;
wire p76;
wire p77;
wire p78;
wire p79;
wire p80;
wire p81;
wire p82;
wire p83;
wire p84;
wire p85;
wire p86;
wire p87;
wire p88;
wire p89;
wire casenb_int;
wire casenb_latch;
/* Product terms */
assign p0 = charen && hiram && ba && !ms3 && game && rw && aec && a12 && !a13 && a14 && a15;
assign p1 = charen && hiram && !ms3 && game && !rw && aec && a12 && !a13 && a14 && a15;
assign p2 = charen && loram && ba && !ms3 && game && rw && aec && a12 && !a13 && a14 && a15;
assign p3 = charen && loram && !ms3 && game && !rw && aec && a12 && !a13 && a14 && a15;
assign p4 = charen && hiram && ba && !ms3 && !exrom && !game && rw && aec && a12 && !a13 && a14 && a15;
assign p5 = charen && hiram && !ms3 && !exrom && !game && !rw && aec && a12 && !a13 && a14 && a15;
assign p6 = charen && loram && ba && !ms3 && !exrom && !game && rw && aec && a12 && !a13 && a14 && a15;
assign p7 = charen && loram && !ms3 && !exrom && !game && !rw && aec && a12 && !a13 && a14 && a15;
assign p8 = ba && !ms3 && exrom && !game && rw && aec && a12 && !a13 && a14 && a15;
assign p9 = !ms3 && exrom && !game && !rw && aec && a12 && !a13 && a14 && a15;
assign p10 = ba && !ms2 && ms3 && z80en && rw && aec && a12 && !a13 && a14 && a15;
assign p11 = !ms2 && ms3 && z80en && !rw && aec && a12 && !a13 && a14 && a15;
assign p12 = charen && hiram && ba && !ms3 && game && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p13 = charen && hiram && !ms3 && game && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p14 = charen && loram && ba && !ms3 && game && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p15 = charen && loram && !ms3 && game && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p16 = charen && hiram && ba && !ms3 && !exrom && !game && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p17 = charen && hiram && !ms3 && !exrom && !game && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p18 = charen && loram && ba && !ms3 && !exrom && !game && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p19 = charen && loram && !ms3 && !exrom && !game && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p20 = ba && !ms3 && exrom && !game && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p21 = !ms3 && exrom && !game && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p22 = ba && !ms2 && ms3 && z80en && rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p23 = !ms2 && ms3 && z80en && !rw && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p24 = charen && hiram && ba && !ms3 && game && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p25 = charen && hiram && !ms3 && game && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p26 = charen && loram && ba && !ms3 && game && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p27 = charen && loram && !ms3 && game && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p28 = charen && hiram && ba && !ms3 && !exrom && !game && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p29 = charen && hiram && !ms3 && !exrom && !game && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p30 = charen && loram && ba && !ms3 && !exrom && !game && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p31 = charen && loram && !ms3 && !exrom && !game && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p32 = ba && !ms3 && exrom && !game && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p33 = !ms3 && exrom && !game && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p34 = ba && !ms2 && ms3 && z80en && rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p35 = !ms2 && ms3 && z80en && !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p36 = !aec;
assign p37 = !rw && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p39 = !charen && hiram && !ms3 && game && rw && aec && a12 && !a13 && a14 && a15;
assign p40 = !charen && loram && !ms3 && game && rw && aec && a12 && !a13 && a14 && a15;
assign p41 = !charen && hiram && !ms3 && !exrom && !game && rw && aec && a12 && !a13 && a14 && a15;
assign p42 = va14 && !vma5 && vma4 && !ms3 && game && !aec;
assign p43 = va14 && !vma5 && vma4 && !ms3 && !exrom && !game && !aec;
assign p44 = !ms0 && !ms1 && ms2 && ms3 && z80en && rw && aec && a12 && !a13 && a14 && a15;
assign p45 = hiram && loram && !ms3 && !exrom && rw && aec && !a13 && !a14 && a15;
assign p46 = !ms3 && exrom && !game && aec && !a13 && !a14 && a15;
assign p47 = ms0 && !ms1 && ms3 && rw && aec && !a14 && a15;
assign p48 = !ms0 && ms1 && ms3 && rw && aec && !a14 && a15;
assign p49 = hiram && !ms3 && !exrom && !game && rw && aec && a13 && !a14 && a15;
assign p50 = !ms3 && exrom && !game && aec && a13 && a14 && a15;
assign p51 = vma5 && vma4 && !ms3 && exrom && !game && !aec;
assign p52 = ms0 && !ms1 && ms3 && rw && aec && !a12 && !a13 && a14 && a15;
assign p53 = !ms0 && ms1 && ms3 && rw && aec && !a12 && !a13 && a14 && a15;
assign p54 = !ms0 && !ms1 && ms3 && rw && aec && !a12 && !a13 && a14 && a15;
assign p55 = !ms0 && !ms1 && z80io && !z80en && rw && aec && !a12 && !a13 && !a14 && !a15;
assign p56 = !ms0 && !ms1 && ms3 && rw && aec && !a14 && a15;
assign p57 = !ms0 && !ms1 && ms3 && rw && aec && a14 && !a15;
assign p58 = hiram && !ms3 && game && rw && aec && a13 && a14 && a15;
assign p59 = hiram && !ms3 && !exrom && !game && rw && aec && a13 && a14 && a15;
assign p60 = hiram && loram && !ms3 && game && rw && aec && a13 && !a14 && a15;
assign p61 = !z80io && !z80en && aec && !a10 && !a11 && a12 && !a13 && a14 && a15;
assign p62 = !z80io && !z80en && aec && a12 && !a13 && a14 && a15;
assign p63 = !z80io && !z80en && aec && !a10 && a11 && a12 && !a13 && a14 && a15;
assign p64 = !rw && aec;
assign p65 = rw && aec;
assign p66 = !aec;
assign p67 = !ms2 && !z80en && aec && !a10 && !a11 && a12 && !a13 && !a14 && !a15;
assign p68 = !ms2 && !z80en && !rw && aec && !a10 && !a11 && a12 && !a13 && !a14 && !a15;
assign p69 = !charen && !vma5 && vma4 && ms3 && !aec && dmaack;
assign p70 = !rom_256 && !ms0 && !ms1 && ms3 && rw && aec && a14 && !a15;
assign p71 = !rom_256 && !ms0 && !ms1 && ms3 && rw && aec && !a12 && !a13 && a14 && a15;
assign p72 = !rom_256 && !ms0 && !ms1 && z80io && !z80en && rw && aec && !a12 && !a13 && !a14 && !a15;
//assign p73 = clk;
assign p74 = rw && !aec && vicfix;
assign p75 = !ms0 && !ms1 && ms3 && rw && aec && a13 && a14 && a15;
assign p76 = !rom_256 && !ms0 && !ms1 && ms3 && rw && aec && a13 && a14 && a15;
assign p77 = !ms0 && ms1 && ms3 && rw && aec && a13 && a14 && a15;
assign p78 = !ms0 && ms1 && ms2 && ms3 && rw && aec && a12 && !a13 && a14 && a15;
assign p79 = ms0 && !ms1 && ms3 && rw && aec && a13 && a14 && a15;
assign p80 = ms0 && !ms1 && ms2 && ms3 && rw && aec && a12 && !a13 && a14 && a15;
assign p81 = !ms3 && exrom && !game && aec && a12 && !a14 && !a15;
assign p82 = !ms3 && exrom && !game && aec && a13 && !a14;
assign p83 = !ms3 && exrom && !game && aec && a14 && !a15;
assign p84 = !ms3 && exrom && !game && aec && !a12 && !a13 && a14 && a15;
assign p85 = !loram && ms3 && aec;
assign p86 = !hiram && ms3 && !aec;
/* outputs */
assign sden = p42 || p43 || p66 || p69;
assign roml = p45 || p46 || p47;
assign romh = p49 || p50 || p51 || p52 || p79 || p80;
assign clrbnk = p85 || p86;
assign from = p48 || p53 || p77 || p78;
assign rom4 = p54 || p55 || p75;
assign rom3 = p56 || p70;
assign rom2 = p57;
assign rom1 = p58 || p59 || p60 || p71 || p72 || p76;
assign iocs = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 || p62;
assign dir = p12 || p14 || p16 || p18 || p20 || p22 || p24 || p26 || p28 || p30 || p32 || p34 || p39 || p40 || p41 || p44 || p65;
assign vic = p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p23 || p61;
assign ioacc = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9 || p10 || p11 ||
p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19 || p20 || p21 || p22 || p23 || p61 || p62;
assign gwe = p37 || p68;
assign colram = p24 || p25 || p26 || p27 || p28 || p29 || p30 || p31 || p32 || p33 || p34 || p35 || p36 || p63 || p67;
assign charom = p39 || p40 || p41 || p42 || p43 || p44 || p69;
assign casenb_latch = clk || p74;
assign casenb_int = p0 || p1 || p2 || p3 || p4 || p5 || p6 || p7 || p8 || p9
|| p10 || p11 || p12 || p13 || p14 || p15 || p16 || p17 || p18 || p19
|| p20 || p21 || p22 || p23 || p39 || p40 || p41 || p42 || p43 || p44
|| p45 || p46 || p47 || p48 || p49 || p50 || p51 || p52 || p53 || p54
|| p55 || p56 || p57 || p58 || p59 || p60 || p61 || p62 || p63 || p67
|| p69 || p70 || p71 || p72 || p75 || p76 || p77 || p78 || p79 || p80
|| p81 || p82 || p83 || p84;
/* Latched outputs */
always @ (clk or p64)
if (clk)
dwe <= p64;
always @ (casenb_latch or casenb_int)
if (casenb_latch)
casenb <= casenb_int;
endmodule |
module mmu8722 (
input reset_n,
input rw,
input [15:0] addr,
input clk,
input k4080,
output ms3,
output [7:0] t_addr,
output cas0,
output cas1,
inout [7:0] d
);
reg [7:0] d_r;
wire d_d;
// Internal registers
reg [7:0] cr_r;
reg [7:0] pcr_r[3:0];
reg [11:0] page0_r;
reg [11:0] page1_r;
reg [3:0] page0_h_r;
reg [3:0] page1_h_r;
// Mode Configuration Register
reg cpu_r; // CPU selection: 0 = Z80, 1 = 8502
reg os_r; // OS mode: 0 = C128, 1 = C64
reg fsdir_r; // Fast serial direction: 0 = in, 1 = out
reg game_r; // GAME input from cartridge port
reg exrom_r; // EXROM input from cartridge port
// RAM Configuration Register
reg [1:0] rcr_common_s_r;
reg rcr_common_h_r;
reg rcr_common_l_r;
reg [1:0] vicbank_r;
wire cs_d500 = (addr >= 16'hd500 && addr <= 16'hd50b);
wire cs_ff00 = (addr >= 16'hff00 && addr <= 16'hff04);
assign d_d = rw && (cs_d500 | cs_ff00);
assign d = d_d ? d_r : 8'bz;
/* Register write and chip reset */
always @(negedge clk or negedge reset_n) begin
if (~reset_n) begin
cr_r <= 8'h00;
pcr_r[0] <= 8'h00;
pcr_r[1] <= 8'h00;
pcr_r[2] <= 8'h00;
pcr_r[3] <= 8'h00;
page0_r <= 12'h000;
page0_h_r <= 4'h0;
page1_r <= 12'h000;
page1_h_r <= 4'h0;
cpu_r <= 0;
os_r <= 0;
fsdir_r <= 1;
game_r <= 1;
exrom_r <= 1;
rcr_common_s_r <= 2'b00;
rcr_common_l_r <= 0;
rcr_common_h_r <= 0;
vicbank_r <= 2'b00;
end else if (!rw) begin
if (cs_d500 && os_r == 0) begin
case (addr[4:0])
0 : cr_r <= d;
1 : pcr_r[0] <= d;
2 : pcr_r[1] <= d;
3 : pcr_r[2] <= d;
4 : pcr_r[3] <= d;
5 : begin
cpu_r <= d[0];
fsdir_r <= d[3];
game_r <= d[4];
exrom_r <= d[5];
os_r <= d[6];
end
6 : begin
rcr_common_s_r <= d[1:0];
rcr_common_l_r <= d[2];
rcr_common_h_r <= d[3];
vicbank_r <= d[7:6];
end
7 : begin
page0_r[7:0] <= d;
page0_r[11:8] <= page0_h_r;
end
8 : begin
page0_h_r <= d[3:0];
end
9 : begin
page1_r[7:0] <= d;
page1_r[11:8] <= page1_h_r;
end
10: begin
page1_h_r <= d[3:0];
end
endcase
end else if (cs_ff00) begin
case (addr[4:0])
0 : cr_r <= d;
1 : cr_r <= pcr_r[0];
2 : cr_r <= pcr_r[1];
3 : cr_r <= pcr_r[2];
4 : cr_r <= pcr_r[3];
endcase
end
end
end
always @(*) begin
if (rw && cs_d500 && !os_r) begin
case (addr[4:0])
0 : d_r = cr_r;
1 : d_r = pcr_r[0];
2 : d_r = pcr_r[1];
3 : d_r = pcr_r[2];
4 : d_r = pcr_r[3];
5 : d_r = {k4080, os_r, exrom_r, game_r, fsdir_r, 2'b00, cpu_r};
6 : d_r = {vicbank_r, 2'b00, rcr_common_h_r, rcr_common_l_r, rcr_common_s_r};
7 : d_r = page0_r[7:0];
8 : d_r = {4'b0000, page0_r[11:8]};
9 : d_r = page1_r[7:0];
10: d_r = {4'b0000, page1_r[11:8]};
11: d_r = 8'h20;
endcase
end
end
/* Outputs */
reg [7:0] taddr_r;
assign ms3 = os_r;
assign t_addr = taddr_r;
always @(*) begin
if (os_r == 0) begin
// C128 mode
taddr_r <= addr[15:8];
end else begin
// C64 mode
taddr_r <= addr[15:8];
end
end
endmodule |
module tt_um_rejunity_1_58bit (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // will go high when the design is enabled
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
assign uio_oe = 0; // bidirectional IOs set to INPUT
assign uio_out = 0; // drive bidirectional IO outputs to 0
wire reset = ! rst_n;
// decode ternary weights
wire [3:0] weights_zero = ~ { |ui_in[1:0], |ui_in[3:2], |ui_in[5:4], |ui_in[7:6] };
wire [3:0] weights_sign = { ui_in[1 ], ui_in[3 ], ui_in[5 ], ui_in[7 ] };
// wire [3:0] weights_zero = ~ { |ui_in[7:6], |ui_in[5:4], |ui_in[3:2], |ui_in[1:0] };
// wire [3:0] weights_sign = { ui_in[7 ], ui_in[5 ], ui_in[3 ], ui_in[1 ] };
// @TODO: special weight to initiate readout
wire initiate_read_out = !ena;
systolic_array systolic_array(
.clk(clk),
.reset(reset),
.in_left_zero(weights_zero),
.in_left_sign(weights_sign),
.in_top(uio_in),
.restart_inputs(initiate_read_out),
.reset_accumulators(initiate_read_out),
.copy_accumulator_values_to_out_queue(initiate_read_out),
.restart_out_queue(initiate_read_out),
.out(uo_out)
);
endmodule |
module systolic_array (
input wire clk,
input wire reset,
input wire [3:0] in_left_zero,
input wire [3:0] in_left_sign,
input wire [7:0] in_top,
input wire restart_inputs,
input wire reset_accumulators,
input wire copy_accumulator_values_to_out_queue,
input wire restart_out_queue,
//input wire [2:0] apply_shift_to_out,
//input wire apply_relu_to_out,
output wire [7:0] out
);
localparam SLICES = 3;
localparam SLICE_BITS = $clog2(SLICES);
localparam SLICES_MINUS_1 = SLICES - 1;
localparam W = 1 * SLICES;
localparam H = 4 * SLICES;
localparam ARRAY_SIZE_BITS = $clog2(W*H);
reg [H -1:0] arg_left_zero_curr;
reg [H -1:0] arg_left_sign_curr;
reg [W*8-1:0] arg_top_curr;
reg [H -1:0] arg_left_zero_next;
reg [H -1:0] arg_left_sign_next;
reg [W*8-1:0] arg_top_next;
// wire [H -1:0] arg_left_zero = in_left_zero;
// wire [H -1:0] arg_left_sign = in_left_sign;
// wire [W*8-1:0] arg_top = in_top;
reg [SLICE_BITS-1:0] slice_counter;
reg signed [16:0] accumulators [W*H-1:0];
wire signed [16:0] accumulators_next [W*H-1:0];
reg signed [16:0] out_queue [W*H-1:0];
reg [ARRAY_SIZE_BITS-1:0] out_queue_counter;
integer n;
always @(posedge clk) begin
if (reset | restart_inputs | slice_counter == SLICES_MINUS_1)
slice_counter <= 0;
else
slice_counter <= slice_counter + 1;
if (reset | restart_out_queue)
out_queue_counter <= 0;
else
out_queue_counter <= out_queue_counter + 1;
if (reset) begin
arg_left_zero_next <= 0;
arg_left_sign_next <= 0;
arg_top_next <= 0;
end else begin
arg_left_zero_next[slice_counter*4 +: 4] <= in_left_zero;
arg_left_sign_next[slice_counter*4 +: 4] <= in_left_sign;
arg_top_next[slice_counter*8 +: 8] <= in_top;
end
if (slice_counter == 0) begin
arg_left_zero_curr <= arg_left_zero_next;
arg_left_sign_curr <= arg_left_sign_next;
arg_top_curr <= arg_top_next;
end
for (n = 0; n < W*H; n = n + 1) begin
if (reset | reset_accumulators)
accumulators[n] <= 0;
else
accumulators[n] <= accumulators_next[n];
if (copy_accumulator_values_to_out_queue)
out_queue[n] <= accumulators_next[n];
end
end
genvar i, j;
generate
for (j = 0; j < W; j = j + 1)
for (i = 0; i < H; i = i + 1) begin : mac
wire [16:0] value_curr = accumulators [i*W+j];
wire [16:0] value_next = accumulators_next[i*W+j];
wire [16:0] value_queue = out_queue [i*W+j];
wire pass_through = (j != slice_counter) | arg_left_zero_curr[i];
wire sign = arg_left_sign_curr[i];
wire signed [7:0] addend = $signed(arg_top_curr[j*8 +: 8]);
assign accumulators_next[i*W+j] =
reset ? 0 :
pass_through ? accumulators[i*W+j] + 0 :
( sign ? accumulators[i*W+j] - addend :
accumulators[i*W+j] + addend);
end
endgenerate
assign out = out_queue[out_queue_counter] >> 8;
// assign out = out_queue[out_queue_counter][7:0];
endmodule |
module systolic_array (
input wire clk,
input wire reset,
input wire [3:0] in_left_zero,
input wire [3:0] in_left_sign,
input wire [7:0] in_top,
input wire reset_accumulators,
input wire copy_accumulator_values_to_out_queue,
input wire restart_out_queue,
//input wire [2:0] apply_shift_to_out,
//input wire apply_relu_to_out,
output wire [7:0] out
);
reg signed [16:0] accumulators [3:0];
wire signed [16:0] accumulators_next [3:0];
reg signed [16:0] out_queue [3:0];
reg [1:0] out_queue_index;
integer n;
// // clocked accumulators[]
// always @(posedge clk)
// for (n = 0; n < 4; n = n + 1)
// if (reset | reset_accumulators)
// accumulators[n] <= 0;
// else
// accumulators[n] <= accumulators_next[n];
// // clocked out_queue[]
// always @(posedge clk)
// for (n = 0; n < 4; n = n + 1)
// // if (reset)
// // out_queue[n] <= 0;
// // else
// if (copy_accumulator_values_to_out_queue)
// out_queue[n] <= accumulators[n]; //accumulators_next[n];
// // clocked out_queue_index[]
// always @(posedge clk)
// if (reset | restart_out_queue)
// out_queue_index <= 0;
// else
// out_queue_index <= out_queue_index + 1;
always @(posedge clk)
for (n = 0; n < 4; n = n + 1) begin
if (reset | reset_accumulators)
accumulators[n] <= 0;
else
accumulators[n] <= accumulators_next[n];
if (reset | restart_out_queue)
out_queue_index <= 0;
else
out_queue_index <= out_queue_index + 1;
if (copy_accumulator_values_to_out_queue)
out_queue[n] <= accumulators_next[n];
end
genvar i, j;
generate
for (j = 0; j < 1; j = j + 1)
for (i = 0; i < 4; i = i + 1) begin : mac
wire [16:0] value_curr = accumulators [i*1+j];
wire [16:0] value_next = accumulators_next[i*1+j];
wire [16:0] value_queue = out_queue [i*1+j];
assign accumulators_next[i*1+j] =
reset ? 0 :
in_left_zero[i] ? accumulators[i*1+j] + 0 :
(in_left_sign[i] ? accumulators[i*1+j] - $signed(in_top) :
accumulators[i*1+j] + $signed(in_top));
end
endgenerate
assign out = out_queue[out_queue_index] >> 8;
endmodule |
module systolic_array (
input wire clk,
input wire reset,
input wire [4:0] in_left_zero,
input wire [4:0] in_left_sign,
input wire [7:0] in_top,
input wire restart_inputs,
input wire reset_accumulators,
input wire copy_accumulator_values_to_out_queue,
input wire restart_out_queue,
//input wire apply_shift_to_accumulators,
//input wire apply_relu_to_out,
output wire [7:0] out
);
localparam SLICES = 3;
localparam SLICE_BITS = $clog2(SLICES);
localparam SLICES_MINUS_1 = SLICES - 1;
localparam W = 1 * SLICES;
localparam H = 5 * SLICES;
localparam ARRAY_SIZE_BITS = $clog2(W*H);
reg [H -1:0] arg_left_zero_curr;
reg [H -1:0] arg_left_sign_curr;
reg [W*8-1:0] arg_top_curr;
reg [H -1:0] arg_left_zero_next;
reg [H -1:0] arg_left_sign_next;
reg [W*8-1:0] arg_top_next;
reg [SLICE_BITS-1:0] slice_counter;
reg signed [16:0] accumulators [W*H-1:0];
wire signed [16:0] accumulators_next [W*H-1:0];
reg signed [16:0] out_queue [W*H-1:0];
reg [ARRAY_SIZE_BITS-1:0] out_queue_counter;
integer n;
always @(posedge clk) begin
if (reset | restart_inputs | slice_counter == SLICES_MINUS_1)
slice_counter <= 0;
else
slice_counter <= slice_counter + 1;
if (reset | restart_out_queue)
out_queue_counter <= 0;
else
out_queue_counter <= out_queue_counter + 1;
if (reset) begin
arg_left_zero_next <= 0;
arg_left_sign_next <= 0;
arg_top_next <= 0;
end else begin
arg_left_zero_next[slice_counter*5 +: 5] <= in_left_zero;
arg_left_sign_next[slice_counter*5 +: 5] <= in_left_sign;
arg_top_next[slice_counter*8 +: 8] <= in_top;
end
if (slice_counter == 0) begin
arg_left_zero_curr <= arg_left_zero_next;
arg_left_sign_curr <= arg_left_sign_next;
arg_top_curr <= arg_top_next;
end
// The following loop must be unrolled, otherwise Verilator
// will treat <= assignments inside the loop as errors
// See similar bug report and workaround here:
// https://github.com/verilator/verilator/issues/2782
// Ideally unroll_full Verilator metacommand should be used,
// however it is supported only from Verilator 5.022 (#3260) [Jiaxun Yang]
// Instead BLKLOOPINIT errors are suppressed for this loop
/* verilator lint_off BLKLOOPINIT */
for (n = 0; n < W*H; n = n + 1) begin
if (reset | reset_accumulators)
accumulators[n] <= 0;
else
accumulators[n] <= accumulators_next[n];
if (copy_accumulator_values_to_out_queue)
out_queue[n] <= accumulators_next[n];
end
/* verilator lint_on BLKLOOPINIT */
end
genvar i, j;
generate
for (j = 0; j < W; j = j + 1)
for (i = 0; i < H; i = i + 1) begin : mac
wire [16:0] value_curr = accumulators [i*W+j];
wire [16:0] value_next = accumulators_next[i*W+j];
wire [16:0] value_queue = out_queue [i*W+j];
wire skip = (j != slice_counter) | arg_left_zero_curr[i];
wire sign = arg_left_sign_curr[i];
wire signed [7:0] addend = $signed(arg_top_curr[j*8 +: 8]);
assign accumulators_next[i*W+j] =
reset ? 0 :
skip ? accumulators[i*W+j] + 0 :
(sign ? accumulators[i*W+j] - addend :
accumulators[i*W+j] + addend);
end
endgenerate
assign out = out_queue[out_queue_counter] >> 8;
// assign out = out_queue[out_queue_counter][7:0];
endmodule |
module unpack_ternary_weights(input [7:0] packed_weights,
output reg [4:0] weights_zero,
output reg [4:0] weights_sign);
always @(*) begin
case(packed_weights)
8'd000: begin weights_zero = 5'b11111; weights_sign = 5'b00000; end // 0 0 0 0 0
8'd001: begin weights_zero = 5'b01111; weights_sign = 5'b00000; end // 0 0 0 0 1
8'd002: begin weights_zero = 5'b01111; weights_sign = 5'b10000; end // 0 0 0 0 -1
8'd003: begin weights_zero = 5'b10111; weights_sign = 5'b00000; end // 0 0 0 1 0
8'd004: begin weights_zero = 5'b00111; weights_sign = 5'b00000; end // 0 0 0 1 1
8'd005: begin weights_zero = 5'b00111; weights_sign = 5'b10000; end // 0 0 0 1 -1
8'd006: begin weights_zero = 5'b10111; weights_sign = 5'b01000; end // 0 0 0 -1 0
8'd007: begin weights_zero = 5'b00111; weights_sign = 5'b01000; end // 0 0 0 -1 1
8'd008: begin weights_zero = 5'b00111; weights_sign = 5'b11000; end // 0 0 0 -1 -1
8'd009: begin weights_zero = 5'b11011; weights_sign = 5'b00000; end // 0 0 1 0 0
8'd010: begin weights_zero = 5'b01011; weights_sign = 5'b00000; end // 0 0 1 0 1
8'd011: begin weights_zero = 5'b01011; weights_sign = 5'b10000; end // 0 0 1 0 -1
8'd012: begin weights_zero = 5'b10011; weights_sign = 5'b00000; end // 0 0 1 1 0
8'd013: begin weights_zero = 5'b00011; weights_sign = 5'b00000; end // 0 0 1 1 1
8'd014: begin weights_zero = 5'b00011; weights_sign = 5'b10000; end // 0 0 1 1 -1
8'd015: begin weights_zero = 5'b10011; weights_sign = 5'b01000; end // 0 0 1 -1 0
8'd016: begin weights_zero = 5'b00011; weights_sign = 5'b01000; end // 0 0 1 -1 1
8'd017: begin weights_zero = 5'b00011; weights_sign = 5'b11000; end // 0 0 1 -1 -1
8'd018: begin weights_zero = 5'b11011; weights_sign = 5'b00100; end // 0 0 -1 0 0
8'd019: begin weights_zero = 5'b01011; weights_sign = 5'b00100; end // 0 0 -1 0 1
8'd020: begin weights_zero = 5'b01011; weights_sign = 5'b10100; end // 0 0 -1 0 -1
8'd021: begin weights_zero = 5'b10011; weights_sign = 5'b00100; end // 0 0 -1 1 0
8'd022: begin weights_zero = 5'b00011; weights_sign = 5'b00100; end // 0 0 -1 1 1
8'd023: begin weights_zero = 5'b00011; weights_sign = 5'b10100; end // 0 0 -1 1 -1
8'd024: begin weights_zero = 5'b10011; weights_sign = 5'b01100; end // 0 0 -1 -1 0
8'd025: begin weights_zero = 5'b00011; weights_sign = 5'b01100; end // 0 0 -1 -1 1
8'd026: begin weights_zero = 5'b00011; weights_sign = 5'b11100; end // 0 0 -1 -1 -1
8'd027: begin weights_zero = 5'b11101; weights_sign = 5'b00000; end // 0 1 0 0 0
8'd028: begin weights_zero = 5'b01101; weights_sign = 5'b00000; end // 0 1 0 0 1
8'd029: begin weights_zero = 5'b01101; weights_sign = 5'b10000; end // 0 1 0 0 -1
8'd030: begin weights_zero = 5'b10101; weights_sign = 5'b00000; end // 0 1 0 1 0
8'd031: begin weights_zero = 5'b00101; weights_sign = 5'b00000; end // 0 1 0 1 1
8'd032: begin weights_zero = 5'b00101; weights_sign = 5'b10000; end // 0 1 0 1 -1
8'd033: begin weights_zero = 5'b10101; weights_sign = 5'b01000; end // 0 1 0 -1 0
8'd034: begin weights_zero = 5'b00101; weights_sign = 5'b01000; end // 0 1 0 -1 1
8'd035: begin weights_zero = 5'b00101; weights_sign = 5'b11000; end // 0 1 0 -1 -1
8'd036: begin weights_zero = 5'b11001; weights_sign = 5'b00000; end // 0 1 1 0 0
8'd037: begin weights_zero = 5'b01001; weights_sign = 5'b00000; end // 0 1 1 0 1
8'd038: begin weights_zero = 5'b01001; weights_sign = 5'b10000; end // 0 1 1 0 -1
8'd039: begin weights_zero = 5'b10001; weights_sign = 5'b00000; end // 0 1 1 1 0
8'd040: begin weights_zero = 5'b00001; weights_sign = 5'b00000; end // 0 1 1 1 1
8'd041: begin weights_zero = 5'b00001; weights_sign = 5'b10000; end // 0 1 1 1 -1
8'd042: begin weights_zero = 5'b10001; weights_sign = 5'b01000; end // 0 1 1 -1 0
8'd043: begin weights_zero = 5'b00001; weights_sign = 5'b01000; end // 0 1 1 -1 1
8'd044: begin weights_zero = 5'b00001; weights_sign = 5'b11000; end // 0 1 1 -1 -1
8'd045: begin weights_zero = 5'b11001; weights_sign = 5'b00100; end // 0 1 -1 0 0
8'd046: begin weights_zero = 5'b01001; weights_sign = 5'b00100; end // 0 1 -1 0 1
8'd047: begin weights_zero = 5'b01001; weights_sign = 5'b10100; end // 0 1 -1 0 -1
8'd048: begin weights_zero = 5'b10001; weights_sign = 5'b00100; end // 0 1 -1 1 0
8'd049: begin weights_zero = 5'b00001; weights_sign = 5'b00100; end // 0 1 -1 1 1
8'd050: begin weights_zero = 5'b00001; weights_sign = 5'b10100; end // 0 1 -1 1 -1
8'd051: begin weights_zero = 5'b10001; weights_sign = 5'b01100; end // 0 1 -1 -1 0
8'd052: begin weights_zero = 5'b00001; weights_sign = 5'b01100; end // 0 1 -1 -1 1
8'd053: begin weights_zero = 5'b00001; weights_sign = 5'b11100; end // 0 1 -1 -1 -1
8'd054: begin weights_zero = 5'b11101; weights_sign = 5'b00010; end // 0 -1 0 0 0
8'd055: begin weights_zero = 5'b01101; weights_sign = 5'b00010; end // 0 -1 0 0 1
8'd056: begin weights_zero = 5'b01101; weights_sign = 5'b10010; end // 0 -1 0 0 -1
8'd057: begin weights_zero = 5'b10101; weights_sign = 5'b00010; end // 0 -1 0 1 0
8'd058: begin weights_zero = 5'b00101; weights_sign = 5'b00010; end // 0 -1 0 1 1
8'd059: begin weights_zero = 5'b00101; weights_sign = 5'b10010; end // 0 -1 0 1 -1
8'd060: begin weights_zero = 5'b10101; weights_sign = 5'b01010; end // 0 -1 0 -1 0
8'd061: begin weights_zero = 5'b00101; weights_sign = 5'b01010; end // 0 -1 0 -1 1
8'd062: begin weights_zero = 5'b00101; weights_sign = 5'b11010; end // 0 -1 0 -1 -1
8'd063: begin weights_zero = 5'b11001; weights_sign = 5'b00010; end // 0 -1 1 0 0
8'd064: begin weights_zero = 5'b01001; weights_sign = 5'b00010; end // 0 -1 1 0 1
8'd065: begin weights_zero = 5'b01001; weights_sign = 5'b10010; end // 0 -1 1 0 -1
8'd066: begin weights_zero = 5'b10001; weights_sign = 5'b00010; end // 0 -1 1 1 0
8'd067: begin weights_zero = 5'b00001; weights_sign = 5'b00010; end // 0 -1 1 1 1
8'd068: begin weights_zero = 5'b00001; weights_sign = 5'b10010; end // 0 -1 1 1 -1
8'd069: begin weights_zero = 5'b10001; weights_sign = 5'b01010; end // 0 -1 1 -1 0
8'd070: begin weights_zero = 5'b00001; weights_sign = 5'b01010; end // 0 -1 1 -1 1
8'd071: begin weights_zero = 5'b00001; weights_sign = 5'b11010; end // 0 -1 1 -1 -1
8'd072: begin weights_zero = 5'b11001; weights_sign = 5'b00110; end // 0 -1 -1 0 0
8'd073: begin weights_zero = 5'b01001; weights_sign = 5'b00110; end // 0 -1 -1 0 1
8'd074: begin weights_zero = 5'b01001; weights_sign = 5'b10110; end // 0 -1 -1 0 -1
8'd075: begin weights_zero = 5'b10001; weights_sign = 5'b00110; end // 0 -1 -1 1 0
8'd076: begin weights_zero = 5'b00001; weights_sign = 5'b00110; end // 0 -1 -1 1 1
8'd077: begin weights_zero = 5'b00001; weights_sign = 5'b10110; end // 0 -1 -1 1 -1
8'd078: begin weights_zero = 5'b10001; weights_sign = 5'b01110; end // 0 -1 -1 -1 0
8'd079: begin weights_zero = 5'b00001; weights_sign = 5'b01110; end // 0 -1 -1 -1 1
8'd080: begin weights_zero = 5'b00001; weights_sign = 5'b11110; end // 0 -1 -1 -1 -1
8'd081: begin weights_zero = 5'b11110; weights_sign = 5'b00000; end // 1 0 0 0 0
8'd082: begin weights_zero = 5'b01110; weights_sign = 5'b00000; end // 1 0 0 0 1
8'd083: begin weights_zero = 5'b01110; weights_sign = 5'b10000; end // 1 0 0 0 -1
8'd084: begin weights_zero = 5'b10110; weights_sign = 5'b00000; end // 1 0 0 1 0
8'd085: begin weights_zero = 5'b00110; weights_sign = 5'b00000; end // 1 0 0 1 1
8'd086: begin weights_zero = 5'b00110; weights_sign = 5'b10000; end // 1 0 0 1 -1
8'd087: begin weights_zero = 5'b10110; weights_sign = 5'b01000; end // 1 0 0 -1 0
8'd088: begin weights_zero = 5'b00110; weights_sign = 5'b01000; end // 1 0 0 -1 1
8'd089: begin weights_zero = 5'b00110; weights_sign = 5'b11000; end // 1 0 0 -1 -1
8'd090: begin weights_zero = 5'b11010; weights_sign = 5'b00000; end // 1 0 1 0 0
8'd091: begin weights_zero = 5'b01010; weights_sign = 5'b00000; end // 1 0 1 0 1
8'd092: begin weights_zero = 5'b01010; weights_sign = 5'b10000; end // 1 0 1 0 -1
8'd093: begin weights_zero = 5'b10010; weights_sign = 5'b00000; end // 1 0 1 1 0
8'd094: begin weights_zero = 5'b00010; weights_sign = 5'b00000; end // 1 0 1 1 1
8'd095: begin weights_zero = 5'b00010; weights_sign = 5'b10000; end // 1 0 1 1 -1
8'd096: begin weights_zero = 5'b10010; weights_sign = 5'b01000; end // 1 0 1 -1 0
8'd097: begin weights_zero = 5'b00010; weights_sign = 5'b01000; end // 1 0 1 -1 1
8'd098: begin weights_zero = 5'b00010; weights_sign = 5'b11000; end // 1 0 1 -1 -1
8'd099: begin weights_zero = 5'b11010; weights_sign = 5'b00100; end // 1 0 -1 0 0
8'd100: begin weights_zero = 5'b01010; weights_sign = 5'b00100; end // 1 0 -1 0 1
8'd101: begin weights_zero = 5'b01010; weights_sign = 5'b10100; end // 1 0 -1 0 -1
8'd102: begin weights_zero = 5'b10010; weights_sign = 5'b00100; end // 1 0 -1 1 0
8'd103: begin weights_zero = 5'b00010; weights_sign = 5'b00100; end // 1 0 -1 1 1
8'd104: begin weights_zero = 5'b00010; weights_sign = 5'b10100; end // 1 0 -1 1 -1
8'd105: begin weights_zero = 5'b10010; weights_sign = 5'b01100; end // 1 0 -1 -1 0
8'd106: begin weights_zero = 5'b00010; weights_sign = 5'b01100; end // 1 0 -1 -1 1
8'd107: begin weights_zero = 5'b00010; weights_sign = 5'b11100; end // 1 0 -1 -1 -1
8'd108: begin weights_zero = 5'b11100; weights_sign = 5'b00000; end // 1 1 0 0 0
8'd109: begin weights_zero = 5'b01100; weights_sign = 5'b00000; end // 1 1 0 0 1
8'd110: begin weights_zero = 5'b01100; weights_sign = 5'b10000; end // 1 1 0 0 -1
8'd111: begin weights_zero = 5'b10100; weights_sign = 5'b00000; end // 1 1 0 1 0
8'd112: begin weights_zero = 5'b00100; weights_sign = 5'b00000; end // 1 1 0 1 1
8'd113: begin weights_zero = 5'b00100; weights_sign = 5'b10000; end // 1 1 0 1 -1
8'd114: begin weights_zero = 5'b10100; weights_sign = 5'b01000; end // 1 1 0 -1 0
8'd115: begin weights_zero = 5'b00100; weights_sign = 5'b01000; end // 1 1 0 -1 1
8'd116: begin weights_zero = 5'b00100; weights_sign = 5'b11000; end // 1 1 0 -1 -1
8'd117: begin weights_zero = 5'b11000; weights_sign = 5'b00000; end // 1 1 1 0 0
8'd118: begin weights_zero = 5'b01000; weights_sign = 5'b00000; end // 1 1 1 0 1
8'd119: begin weights_zero = 5'b01000; weights_sign = 5'b10000; end // 1 1 1 0 -1
8'd120: begin weights_zero = 5'b10000; weights_sign = 5'b00000; end // 1 1 1 1 0
8'd121: begin weights_zero = 5'b00000; weights_sign = 5'b00000; end // 1 1 1 1 1
8'd122: begin weights_zero = 5'b00000; weights_sign = 5'b10000; end // 1 1 1 1 -1
8'd123: begin weights_zero = 5'b10000; weights_sign = 5'b01000; end // 1 1 1 -1 0
8'd124: begin weights_zero = 5'b00000; weights_sign = 5'b01000; end // 1 1 1 -1 1
8'd125: begin weights_zero = 5'b00000; weights_sign = 5'b11000; end // 1 1 1 -1 -1
8'd126: begin weights_zero = 5'b11000; weights_sign = 5'b00100; end // 1 1 -1 0 0
8'd127: begin weights_zero = 5'b01000; weights_sign = 5'b00100; end // 1 1 -1 0 1
8'd128: begin weights_zero = 5'b01000; weights_sign = 5'b10100; end // 1 1 -1 0 -1
8'd129: begin weights_zero = 5'b10000; weights_sign = 5'b00100; end // 1 1 -1 1 0
8'd130: begin weights_zero = 5'b00000; weights_sign = 5'b00100; end // 1 1 -1 1 1
8'd131: begin weights_zero = 5'b00000; weights_sign = 5'b10100; end // 1 1 -1 1 -1
8'd132: begin weights_zero = 5'b10000; weights_sign = 5'b01100; end // 1 1 -1 -1 0
8'd133: begin weights_zero = 5'b00000; weights_sign = 5'b01100; end // 1 1 -1 -1 1
8'd134: begin weights_zero = 5'b00000; weights_sign = 5'b11100; end // 1 1 -1 -1 -1
8'd135: begin weights_zero = 5'b11100; weights_sign = 5'b00010; end // 1 -1 0 0 0
8'd136: begin weights_zero = 5'b01100; weights_sign = 5'b00010; end // 1 -1 0 0 1
8'd137: begin weights_zero = 5'b01100; weights_sign = 5'b10010; end // 1 -1 0 0 -1
8'd138: begin weights_zero = 5'b10100; weights_sign = 5'b00010; end // 1 -1 0 1 0
8'd139: begin weights_zero = 5'b00100; weights_sign = 5'b00010; end // 1 -1 0 1 1
8'd140: begin weights_zero = 5'b00100; weights_sign = 5'b10010; end // 1 -1 0 1 -1
8'd141: begin weights_zero = 5'b10100; weights_sign = 5'b01010; end // 1 -1 0 -1 0
8'd142: begin weights_zero = 5'b00100; weights_sign = 5'b01010; end // 1 -1 0 -1 1
8'd143: begin weights_zero = 5'b00100; weights_sign = 5'b11010; end // 1 -1 0 -1 -1
8'd144: begin weights_zero = 5'b11000; weights_sign = 5'b00010; end // 1 -1 1 0 0
8'd145: begin weights_zero = 5'b01000; weights_sign = 5'b00010; end // 1 -1 1 0 1
8'd146: begin weights_zero = 5'b01000; weights_sign = 5'b10010; end // 1 -1 1 0 -1
8'd147: begin weights_zero = 5'b10000; weights_sign = 5'b00010; end // 1 -1 1 1 0
8'd148: begin weights_zero = 5'b00000; weights_sign = 5'b00010; end // 1 -1 1 1 1
8'd149: begin weights_zero = 5'b00000; weights_sign = 5'b10010; end // 1 -1 1 1 -1
8'd150: begin weights_zero = 5'b10000; weights_sign = 5'b01010; end // 1 -1 1 -1 0
8'd151: begin weights_zero = 5'b00000; weights_sign = 5'b01010; end // 1 -1 1 -1 1
8'd152: begin weights_zero = 5'b00000; weights_sign = 5'b11010; end // 1 -1 1 -1 -1
8'd153: begin weights_zero = 5'b11000; weights_sign = 5'b00110; end // 1 -1 -1 0 0
8'd154: begin weights_zero = 5'b01000; weights_sign = 5'b00110; end // 1 -1 -1 0 1
8'd155: begin weights_zero = 5'b01000; weights_sign = 5'b10110; end // 1 -1 -1 0 -1
8'd156: begin weights_zero = 5'b10000; weights_sign = 5'b00110; end // 1 -1 -1 1 0
8'd157: begin weights_zero = 5'b00000; weights_sign = 5'b00110; end // 1 -1 -1 1 1
8'd158: begin weights_zero = 5'b00000; weights_sign = 5'b10110; end // 1 -1 -1 1 -1
8'd159: begin weights_zero = 5'b10000; weights_sign = 5'b01110; end // 1 -1 -1 -1 0
8'd160: begin weights_zero = 5'b00000; weights_sign = 5'b01110; end // 1 -1 -1 -1 1
8'd161: begin weights_zero = 5'b00000; weights_sign = 5'b11110; end // 1 -1 -1 -1 -1
8'd162: begin weights_zero = 5'b11110; weights_sign = 5'b00001; end // -1 0 0 0 0
8'd163: begin weights_zero = 5'b01110; weights_sign = 5'b00001; end // -1 0 0 0 1
8'd164: begin weights_zero = 5'b01110; weights_sign = 5'b10001; end // -1 0 0 0 -1
8'd165: begin weights_zero = 5'b10110; weights_sign = 5'b00001; end // -1 0 0 1 0
8'd166: begin weights_zero = 5'b00110; weights_sign = 5'b00001; end // -1 0 0 1 1
8'd167: begin weights_zero = 5'b00110; weights_sign = 5'b10001; end // -1 0 0 1 -1
8'd168: begin weights_zero = 5'b10110; weights_sign = 5'b01001; end // -1 0 0 -1 0
8'd169: begin weights_zero = 5'b00110; weights_sign = 5'b01001; end // -1 0 0 -1 1
8'd170: begin weights_zero = 5'b00110; weights_sign = 5'b11001; end // -1 0 0 -1 -1
8'd171: begin weights_zero = 5'b11010; weights_sign = 5'b00001; end // -1 0 1 0 0
8'd172: begin weights_zero = 5'b01010; weights_sign = 5'b00001; end // -1 0 1 0 1
8'd173: begin weights_zero = 5'b01010; weights_sign = 5'b10001; end // -1 0 1 0 -1
8'd174: begin weights_zero = 5'b10010; weights_sign = 5'b00001; end // -1 0 1 1 0
8'd175: begin weights_zero = 5'b00010; weights_sign = 5'b00001; end // -1 0 1 1 1
8'd176: begin weights_zero = 5'b00010; weights_sign = 5'b10001; end // -1 0 1 1 -1
8'd177: begin weights_zero = 5'b10010; weights_sign = 5'b01001; end // -1 0 1 -1 0
8'd178: begin weights_zero = 5'b00010; weights_sign = 5'b01001; end // -1 0 1 -1 1
8'd179: begin weights_zero = 5'b00010; weights_sign = 5'b11001; end // -1 0 1 -1 -1
8'd180: begin weights_zero = 5'b11010; weights_sign = 5'b00101; end // -1 0 -1 0 0
8'd181: begin weights_zero = 5'b01010; weights_sign = 5'b00101; end // -1 0 -1 0 1
8'd182: begin weights_zero = 5'b01010; weights_sign = 5'b10101; end // -1 0 -1 0 -1
8'd183: begin weights_zero = 5'b10010; weights_sign = 5'b00101; end // -1 0 -1 1 0
8'd184: begin weights_zero = 5'b00010; weights_sign = 5'b00101; end // -1 0 -1 1 1
8'd185: begin weights_zero = 5'b00010; weights_sign = 5'b10101; end // -1 0 -1 1 -1
8'd186: begin weights_zero = 5'b10010; weights_sign = 5'b01101; end // -1 0 -1 -1 0
8'd187: begin weights_zero = 5'b00010; weights_sign = 5'b01101; end // -1 0 -1 -1 1
8'd188: begin weights_zero = 5'b00010; weights_sign = 5'b11101; end // -1 0 -1 -1 -1
8'd189: begin weights_zero = 5'b11100; weights_sign = 5'b00001; end // -1 1 0 0 0
8'd190: begin weights_zero = 5'b01100; weights_sign = 5'b00001; end // -1 1 0 0 1
8'd191: begin weights_zero = 5'b01100; weights_sign = 5'b10001; end // -1 1 0 0 -1
8'd192: begin weights_zero = 5'b10100; weights_sign = 5'b00001; end // -1 1 0 1 0
8'd193: begin weights_zero = 5'b00100; weights_sign = 5'b00001; end // -1 1 0 1 1
8'd194: begin weights_zero = 5'b00100; weights_sign = 5'b10001; end // -1 1 0 1 -1
8'd195: begin weights_zero = 5'b10100; weights_sign = 5'b01001; end // -1 1 0 -1 0
8'd196: begin weights_zero = 5'b00100; weights_sign = 5'b01001; end // -1 1 0 -1 1
8'd197: begin weights_zero = 5'b00100; weights_sign = 5'b11001; end // -1 1 0 -1 -1
8'd198: begin weights_zero = 5'b11000; weights_sign = 5'b00001; end // -1 1 1 0 0
8'd199: begin weights_zero = 5'b01000; weights_sign = 5'b00001; end // -1 1 1 0 1
8'd200: begin weights_zero = 5'b01000; weights_sign = 5'b10001; end // -1 1 1 0 -1
8'd201: begin weights_zero = 5'b10000; weights_sign = 5'b00001; end // -1 1 1 1 0
8'd202: begin weights_zero = 5'b00000; weights_sign = 5'b00001; end // -1 1 1 1 1
8'd203: begin weights_zero = 5'b00000; weights_sign = 5'b10001; end // -1 1 1 1 -1
8'd204: begin weights_zero = 5'b10000; weights_sign = 5'b01001; end // -1 1 1 -1 0
8'd205: begin weights_zero = 5'b00000; weights_sign = 5'b01001; end // -1 1 1 -1 1
8'd206: begin weights_zero = 5'b00000; weights_sign = 5'b11001; end // -1 1 1 -1 -1
8'd207: begin weights_zero = 5'b11000; weights_sign = 5'b00101; end // -1 1 -1 0 0
8'd208: begin weights_zero = 5'b01000; weights_sign = 5'b00101; end // -1 1 -1 0 1
8'd209: begin weights_zero = 5'b01000; weights_sign = 5'b10101; end // -1 1 -1 0 -1
8'd210: begin weights_zero = 5'b10000; weights_sign = 5'b00101; end // -1 1 -1 1 0
8'd211: begin weights_zero = 5'b00000; weights_sign = 5'b00101; end // -1 1 -1 1 1
8'd212: begin weights_zero = 5'b00000; weights_sign = 5'b10101; end // -1 1 -1 1 -1
8'd213: begin weights_zero = 5'b10000; weights_sign = 5'b01101; end // -1 1 -1 -1 0
8'd214: begin weights_zero = 5'b00000; weights_sign = 5'b01101; end // -1 1 -1 -1 1
8'd215: begin weights_zero = 5'b00000; weights_sign = 5'b11101; end // -1 1 -1 -1 -1
8'd216: begin weights_zero = 5'b11100; weights_sign = 5'b00011; end // -1 -1 0 0 0
8'd217: begin weights_zero = 5'b01100; weights_sign = 5'b00011; end // -1 -1 0 0 1
8'd218: begin weights_zero = 5'b01100; weights_sign = 5'b10011; end // -1 -1 0 0 -1
8'd219: begin weights_zero = 5'b10100; weights_sign = 5'b00011; end // -1 -1 0 1 0
8'd220: begin weights_zero = 5'b00100; weights_sign = 5'b00011; end // -1 -1 0 1 1
8'd221: begin weights_zero = 5'b00100; weights_sign = 5'b10011; end // -1 -1 0 1 -1
8'd222: begin weights_zero = 5'b10100; weights_sign = 5'b01011; end // -1 -1 0 -1 0
8'd223: begin weights_zero = 5'b00100; weights_sign = 5'b01011; end // -1 -1 0 -1 1
8'd224: begin weights_zero = 5'b00100; weights_sign = 5'b11011; end // -1 -1 0 -1 -1
8'd225: begin weights_zero = 5'b11000; weights_sign = 5'b00011; end // -1 -1 1 0 0
8'd226: begin weights_zero = 5'b01000; weights_sign = 5'b00011; end // -1 -1 1 0 1
8'd227: begin weights_zero = 5'b01000; weights_sign = 5'b10011; end // -1 -1 1 0 -1
8'd228: begin weights_zero = 5'b10000; weights_sign = 5'b00011; end // -1 -1 1 1 0
8'd229: begin weights_zero = 5'b00000; weights_sign = 5'b00011; end // -1 -1 1 1 1
8'd230: begin weights_zero = 5'b00000; weights_sign = 5'b10011; end // -1 -1 1 1 -1
8'd231: begin weights_zero = 5'b10000; weights_sign = 5'b01011; end // -1 -1 1 -1 0
8'd232: begin weights_zero = 5'b00000; weights_sign = 5'b01011; end // -1 -1 1 -1 1
8'd233: begin weights_zero = 5'b00000; weights_sign = 5'b11011; end // -1 -1 1 -1 -1
8'd234: begin weights_zero = 5'b11000; weights_sign = 5'b00111; end // -1 -1 -1 0 0
8'd235: begin weights_zero = 5'b01000; weights_sign = 5'b00111; end // -1 -1 -1 0 1
8'd236: begin weights_zero = 5'b01000; weights_sign = 5'b10111; end // -1 -1 -1 0 -1
8'd237: begin weights_zero = 5'b10000; weights_sign = 5'b00111; end // -1 -1 -1 1 0
8'd238: begin weights_zero = 5'b00000; weights_sign = 5'b00111; end // -1 -1 -1 1 1
8'd239: begin weights_zero = 5'b00000; weights_sign = 5'b10111; end // -1 -1 -1 1 -1
8'd240: begin weights_zero = 5'b10000; weights_sign = 5'b01111; end // -1 -1 -1 -1 0
8'd241: begin weights_zero = 5'b00000; weights_sign = 5'b01111; end // -1 -1 -1 -1 1
8'd242: begin weights_zero = 5'b00000; weights_sign = 5'b11111; end // -1 -1 -1 -1 -1
default: {weights_zero, weights_sign} = 10'b0; // Default case
endcase
end
endmodule |
module multiplier(
input signed [`WIDTH - 1 : 0] dataa,
input signed [2 * `WIDTH - 1 : 0] datab,
output signed [2 * `WIDTH - 1 : 0] dataout
);
assign dataout = dataa * datab;
endmodule |
module fourbyfour18mul (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1_in, U2_in, U3_in, U4_in, U5_in, U6_in, U7_in, U8_in, U9_in, U10_in, U11_in, U12_in, U13_in, U14_in, U15_in, U16_in,
I,
Initial_X_in,
clk,
Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out
);
input wire clk;
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1_in, U2_in, U3_in, U4_in, U5_in, U6_in, U7_in, U8_in, U9_in, U10_in, U11_in, U12_in, U13_in, U14_in, U15_in, U16_in;
input wire signed [`WIDTH - 1:0] I;
input wire signed [2 * `WIDTH - 1:0] Initial_X_in;
reg signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
reg signed [2 * `WIDTH - 1:0] X1_in = 0, X2_in = 0, X3_in = 0, X4_in = 0, X5_in = 0, X6_in = 0, X7_in = 0;
reg signed [2 * `WIDTH - 1:0] X8_in = 0, X9_in = 0, X10_in = 0, X11_in = 0, X12_in = 0, X13_in = 0, X14_in = 0, X15_in = 0, X16_in = 0;
reg signed [2 * `WIDTH - 1:0] X;
reg signed [2 * `WIDTH - 1:0] Y1_in = 0, Y2_in = 0, Y3_in = 0, Y4_in = 0, Y5_in = 0, Y6_in = 0, Y7_in = 0;
reg signed [2 * `WIDTH - 1:0] Y8_in = 0, Y9_in = 0, Y10_in = 0, Y11_in = 0, Y12_in = 0, Y13_in = 0, Y14_in = 0, Y15_in = 0, Y16_in = 0;
reg signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
reg [`COUNTER_WIDTH_FOUR_BY_FOUR - 1:0] counter = `COUNTER_WIDTH_FOUR_BY_FOUR'b0;
wire signed [2 * `WIDTH - 1:0] X_onebyoneout;
wire signed [2 * `WIDTH - 1:0] Y_onebyoneout;
reg initial_flag = 1'b1;
// Setting X_next and Y_next to 0 as that would be the initial values.
reg signed [2 * `WIDTH - 1:0] X1_next = 0, X2_next = 0, X3_next = 0, X4_next = 0, X5_next = 0, X6_next = 0;
reg signed [2 * `WIDTH - 1:0] X7_next = 0, X8_next = 0, X9_next = 0, X10_next = 0, X11_next = 0, X12_next = 0, X13_next = 0;
reg signed [2 * `WIDTH - 1:0] X14_next = 0, X15_next = 0, X16_next = 0;
reg signed [2 * `WIDTH - 1:0] Y1_next = 0, Y2_next = 0, Y3_next = 0, Y4_next = 0, Y5_next = 0, Y6_next = 0;
reg signed [2 * `WIDTH - 1:0] Y7_next = 0, Y8_next = 0, Y9_next = 0, Y10_next = 0, Y11_next = 0, Y12_next = 0, Y13_next = 0;
reg signed [2 * `WIDTH - 1:0] Y14_next = 0, Y15_next = 0, Y16_next = 0;
output wire signed [2 * `WIDTH - 1:0] Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out;
assign Y1_out = Y1_next;assign Y2_out = Y2_next;assign Y3_out = Y3_next;assign Y4_out = Y4_next;assign Y5_out = Y5_next;assign Y6_out = Y6_next;assign Y7_out = Y7_next;
assign Y8_out = Y8_next;assign Y9_out = Y9_next;assign Y10_out = Y10_next;assign Y11_out = Y11_next;assign Y12_out = Y12_next;assign Y13_out = Y13_next;
assign Y14_out = Y14_next;assign Y15_out = Y15_next;assign Y16_out = Y16_next;
always @ (posedge clk)
begin
if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0000) begin // 1
// when the initial flag is 0 then set all Y and X to next value of Y and X. if it is 1, set X to initial X.
if (initial_flag == 1'b0) begin
Y16_next = Y_onebyoneout;
X16_next = X_onebyoneout;
Y1_in = Y1_next;
Y2_in = Y2_next;
Y3_in = Y3_next;
Y4_in = Y4_next;
Y5_in = Y5_next;
Y6_in = Y6_next;
Y7_in = Y7_next;
Y8_in = Y8_next;
Y9_in = Y9_next;
Y10_in = Y10_next;
Y11_in = Y11_next;
Y12_in = Y12_next;
Y13_in = Y13_next;
Y14_in = Y14_next;
Y15_in = Y15_next;
Y16_in = Y16_next;
X1_in = X1_next;
X2_in = X2_next;
X3_in = X3_next;
X4_in = X4_next;
X5_in = X5_next;
X6_in = X6_next;
X7_in = X7_next;
X8_in = X8_next;
X9_in = X9_next;
X10_in = X10_next;
X11_in = X11_next;
X12_in = X12_next;
X13_in = X13_next;
X14_in = X14_next;
X15_in = X15_next;
X16_in = X16_next;
end else begin
X1_in = Initial_X_in;
X2_in = Initial_X_in;
X3_in = Initial_X_in;
X4_in = Initial_X_in;
X5_in = Initial_X_in;
X6_in = Initial_X_in;
X7_in = Initial_X_in;
X8_in = Initial_X_in;
X9_in = Initial_X_in;
X10_in = Initial_X_in;
X11_in = Initial_X_in;
X12_in = Initial_X_in;
X13_in = Initial_X_in;
X14_in = Initial_X_in;
X15_in = Initial_X_in;
X16_in = Initial_X_in;
initial_flag = 1'b0;
end
// Each Input matrix is definied. The boundaries will be 0. For examples, around location 2, the inputs will be 0,0,0,U1, U2, U3, U4, U5, U6 and the counter_width
// will be 1
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= `WIDTH'b0;
U5 <= U1_in;
U6 <= U2_in;
U7 <= `WIDTH'b0;
U8 <= U5_in;
U9 <= U6_in;
X <= X1_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y1_in;
Y6 <= Y2_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y5_in;
Y9 <= Y6_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0001) begin // 2
Y1_next <= Y_onebyoneout;
X1_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U1_in;
U5 <= U2_in;
U6 <= U3_in;
U7 <= U5_in;
U8 <= U6_in;
U9 <= U7_in;
X <= X2_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y1_in;
Y5 <= Y2_in;
Y6 <= Y3_in;
Y7 <= Y5_in;
Y8 <= Y6_in;
Y9 <= Y7_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0010) begin // 3
Y2_next <= Y_onebyoneout;
X2_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U2_in;
U5 <= U3_in;
U6 <= U4_in;
U7 <= U6_in;
U8 <= U7_in;
U9 <= U8_in;
X <= X3_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y2_in;
Y5 <= Y3_in;
Y6 <= Y4_in;
Y7 <= Y6_in;
Y8 <= Y7_in;
Y9 <= Y8_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0011) begin // 4
Y3_next <= Y_onebyoneout;
X3_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U3_in;
U5 <= U4_in;
U6 <= `WIDTH'b0;
U7 <= U7_in;
U8 <= U8_in;
U9 <= `WIDTH'b0;
X <= X4_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y3_in;
Y5 <= Y4_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y7_in;
Y8 <= Y8_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0100) begin // 5
Y4_next <= Y_onebyoneout;
X4_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U1_in;
U3 <= U2_in;
U4 <= `WIDTH'b0;
U5 <= U5_in;
U6 <= U6_in;
U7 <= `WIDTH'b0;
U8 <= U9_in;
U9 <= U10_in;
X <= X5_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y1_in;
Y3 <= Y2_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y5_in;
Y6 <= Y6_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y9_in;
Y9 <= Y10_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0101) begin // 6
Y5_next <= Y_onebyoneout;
X5_next <= X_onebyoneout;
U1 <= U1_in;
U2 <= U2_in;
U3 <= U3_in;
U4 <= U5_in;
U5 <= U6_in;
U6 <= U7_in;
U7 <= U9_in;
U8 <= U10_in;
U9 <= U11_in;
X <= X6_in;
Y1 <= Y1_in;
Y2 <= Y2_in;
Y3 <= Y3_in;
Y4 <= Y5_in;
Y5 <= Y6_in;
Y6 <= Y7_in;
Y7 <= Y9_in;
Y8 <= Y10_in;
Y9 <= Y11_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0110) begin // 7
Y6_next <= Y_onebyoneout;
X6_next <= X_onebyoneout;
U1 <= U2_in;
U2 <= U3_in;
U3 <= U4_in;
U4 <= U6_in;
U5 <= U7_in;
U6 <= U8_in;
U7 <= U10_in;
U8 <= U11_in;
U9 <= U12_in;
X <= X7_in;
Y1 <= Y2_in;
Y2 <= Y3_in;
Y3 <= Y4_in;
Y4 <= Y6_in;
Y5 <= Y7_in;
Y6 <= Y8_in;
Y7 <= Y10_in;
Y8 <= Y11_in;
Y9 <= Y12_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0111) begin // 8
Y7_next <= Y_onebyoneout;
X7_next <= X_onebyoneout;
U1 <= U3_in;
U2 <= U4_in;
U3 <= `WIDTH'b0;
U4 <= U7_in;
U5 <= U8_in;
U6 <= `WIDTH'b0;
U7 <= U11_in;
U8 <= U12_in;
U9 <= `WIDTH'b0;
X <= X8_in;
Y1 <= Y3_in;
Y2 <= Y4_in;
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y7_in;
Y5 <= Y8_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y11_in;
Y8 <= Y12_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1000) begin // 9
Y8_next <= Y_onebyoneout;
X8_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U5_in;
U3 <= U6_in;
U4 <= `WIDTH'b0;
U5 <= U9_in;
U6 <= U10_in;
U7 <= `WIDTH'b0;
U8 <= U13_in;
U9 <= U14_in;
X <= X9_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y5_in;
Y3 <= Y6_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y9_in;
Y6 <= Y10_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y13_in;
Y9 <= Y14_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1001) begin // 10
Y9_next <= Y_onebyoneout;
X9_next <= X_onebyoneout;
U1 <= U5_in;
U2 <= U6_in;
U3 <= U7_in;
U4 <= U9_in;
U5 <= U10_in;
U6 <= U11_in;
U7 <= U13_in;
U8 <= U14_in;
U9 <= U15_in;
X <= X10_in;
Y1 <= Y5_in;
Y2 <= Y6_in;
Y3 <= Y7_in;
Y4 <= Y9_in;
Y5 <= Y10_in;
Y6 <= Y11_in;
Y7 <= Y13_in;
Y8 <= Y14_in;
Y9 <= Y15_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1010) begin // 11
Y10_next <= Y_onebyoneout;
X10_next <= X_onebyoneout;
U1 <= U6_in;
U2 <= U7_in;
U3 <= U8_in;
U4 <= U10_in;
U5 <= U11_in;
U6 <= U12_in;
U7 <= U14_in;
U8 <= U15_in;
U9 <= U16_in;
X <= X11_in;
Y1 <= Y6_in;
Y2 <= Y7_in;
Y3 <= Y8_in;
Y4 <= Y10_in;
Y5 <= Y11_in;
Y6 <= Y12_in;
Y7 <= Y14_in;
Y8 <= Y15_in;
Y9 <= Y16_in;
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1011) begin // 12
Y11_next <= Y_onebyoneout;
X11_next <= X_onebyoneout;
U1 <= U7_in;
U2 <= U8_in;
U3 <= `WIDTH'b0;
U4 <= U11_in;
U5 <= U12_in;
U6 <= `WIDTH'b0;
U7 <= U15_in;
U8 <= U16_in;
U9 <= `WIDTH'b0;
X <= X12_in;
Y1 <= Y7_in;
Y2 <= Y8_in;
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y11_in;
Y5 <= Y12_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y15_in;
Y8 <= Y16_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1100) begin // 13
Y12_next <= Y_onebyoneout;
X12_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U9_in;
U3 <= U10_in;
U4 <= `WIDTH'b0;
U5 <= U13_in;
U6 <= U14_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X13_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y9_in;
Y3 <= Y10_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y13_in;
Y6 <= Y14_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1101) begin // 14
Y13_next <= Y_onebyoneout;
X13_next <= X_onebyoneout;
U1 <= U9_in;
U2 <= U10_in;
U3 <= U11_in;
U4 <= U13_in;
U5 <= U14_in;
U6 <= U15_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X14_in;
Y1 <= Y9_in;
Y2 <= Y10_in;
Y3 <= Y11_in;
Y4 <= Y13_in;
Y5 <= Y14_in;
Y6 <= Y15_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1110) begin // 15
Y14_next <= Y_onebyoneout;
X14_next <= X_onebyoneout;
U1 <= U10_in;
U2 <= U11_in;
U3 <= U12_in;
U4 <= U14_in;
U5 <= U15_in;
U6 <= U16_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X15_in;
Y1 <= Y10_in;
Y2 <= Y11_in;
Y3 <= Y12_in;
Y4 <= Y14_in;
Y5 <= Y15_in;
Y6 <= Y16_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1111) begin // 16
Y15_next <= Y_onebyoneout;
X15_next <= X_onebyoneout;
U1 <= U11_in;
U2 <= U12_in;
U3 <= `WIDTH'b0;
U4 <= U15_in;
U5 <= U16_in;
U6 <= `WIDTH'b0;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X16_in;
Y1 <= Y11_in;
Y2 <= Y12_in;
Y3 <= `WIDTH'b0;
Y4 <= Y15_in;
Y5 <= Y16_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end
//Increment the counter at the end of each iteration
counter = counter + `COUNTER_WIDTH_FOUR_BY_FOUR'b1;
end
// Once the inputs are set, they are given to the onebyone module which then does the computation of the outputs.
onebyone18mul u1(
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),
.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),
.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),
.Y1(Y1[2 * `WIDTH - 1:0]),
.Y2(Y2[2 * `WIDTH - 1:0]),
.Y3(Y3[2 * `WIDTH - 1:0]),
.Y4(Y4[2 * `WIDTH - 1:0]),
.Y5(Y5[2 * `WIDTH - 1:0]),
.Y6(Y6[2 * `WIDTH - 1:0]),
.Y7(Y7[2 * `WIDTH - 1:0]),
.Y8(Y8[2 * `WIDTH - 1:0]),
.Y9(Y9[2 * `WIDTH - 1:0]),
.I(I[`WIDTH - 1:0]),
.Xout(X_onebyoneout[2 * `WIDTH - 1:0]),
.Yout(Y_onebyoneout[2 * `WIDTH - 1:0]),
.X(X[2 * `WIDTH - 1:0])
);
endmodule |
module onebyone18mul (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
I,
X,
Xout,
Yout
);
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
input wire signed [`WIDTH - 1:0] I;
input wire signed [2 * `WIDTH - 1:0] X;
output wire signed [2 * `WIDTH - 1:0] Xout;
output wire signed [2 * `WIDTH - 1:0] Yout;
// In A1(A1[`WIDTH - 1:0]), the first A1 is the A1 in eq1 module and the second A1 is the one in this module
// This section is assigning the inputs from onebyone module to the respective inputs in other moudles
eq1 u1(
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),
.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),
.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),
.Y1(Y1[2 * `WIDTH - 1:0]),
.Y2(Y2[2 * `WIDTH - 1:0]),
.Y3(Y3[2 * `WIDTH - 1:0]),
.Y4(Y4[2 * `WIDTH - 1:0]),
.Y5(Y5[2 * `WIDTH - 1:0]),
.Y6(Y6[2 * `WIDTH - 1:0]),
.Y7(Y7[2 * `WIDTH - 1:0]),
.Y8(Y8[2 * `WIDTH - 1:0]),
.Y9(Y9[2 * `WIDTH - 1:0]),
.I(I[`WIDTH - 1:0]),
.out(Xout[2 * `WIDTH - 1:0])
);
eq2 u2(
.X(X[2 * `WIDTH - 1:0]),
.out(Yout[2 * `WIDTH - 1:0])
);
endmodule |
module eq2 (
X,
out
);
input wire signed [2 * `WIDTH - 1:0] X;
wire signed [2 * `WIDTH - 1:0] Xplus1;
wire signed [2 * `WIDTH - 1:0] Xminus1;
wire signed [2 * `WIDTH - 1:0] Xplus;
wire signed [2 * `WIDTH - 1:0] Xminus;
output wire signed [2 * `WIDTH - 1:0] out;
// {{(2 * `WIDTH-1){1'b0}}, 1'b1} this notation basically acts like concatenation
// This would result in a sign extended binary one. This is necessary to make it the same size as X
assign Xplus1 = X + {{(2 * `WIDTH - 1){1'b0}}, 1'b1};
assign Xminus1 = X - {{(2 * `WIDTH - 1){1'b0}}, 1'b1};
// Xplus and Xminus equations check the most significant bit of Xplus1 and Xminus1
// If most significant bit is 1, then get the one's complement of Xplus1 and assign it to Xplus
// If most significant bit is 0, then Xplus is Xplus1 from previous step
assign Xplus = (Xplus1[2 * `WIDTH - 1])?(~Xplus1+{{(2 * `WIDTH - 1){1'b0}}, 1'b1}):Xplus1;
assign Xminus = (Xminus1[2 * `WIDTH - 1])?(~Xminus1+{{(2 * `WIDTH - 1){1'b0}}, 1'b1}):Xminus1;
// Right shift (Xplus - Xminus) by one bit
assign out = (Xplus - Xminus) >>> {{(2 * `WIDTH-1){1'b0}}, 1'b1};
endmodule |
module eq1oneunit(
clk,
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
I,
fin_flag,
counter_flag,
out
);
input wire clk;
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
input wire signed [`WIDTH - 1:0] I;
output wire fin_flag;
output wire counter_flag;
output reg signed [2 * `WIDTH - 1:0] out = 0;
reg signed [2 * `WIDTH - 1:0] outY;
reg signed [2 * `WIDTH - 1:0] adda;
reg signed [2 * `WIDTH - 1:0] addb;
wire signed [2 * `WIDTH - 1:0] data_out;
reg signed [`WIDTH - 1 : 0] dataa;
reg signed [2 * `WIDTH - 1:0] datab;
wire signed [2 * `WIDTH - 1:0] mult_out;
reg signed [2 * `WIDTH - 1:0] sum = {(2 * `WIDTH){1'b0}};
wire signed [2 * `WIDTH - 1:0] add_out;
reg flag = 1'b1;
reg c_flag = 1'b0;
reg [4:0] counter = 5'b11111;
//assign outY = (A1 * Y1)+ (A2 * Y2) + (A3 * Y3) + (A4 * Y4) + (A5 * Y5) + (A6 * Y6) + (A7 * Y7) + (A8 * Y8) + (A9 * Y9);
//assign outU = (B1 * U1)+ (B2 * U2) + (B3 * U3) + (B4 * U4) + (B5 * U5) + (B6 * U6) + (B7 * U7) + (B8 * U8) + (B9 * U9);
assign fin_flag = flag;
assign counter_flag = c_flag;
always @ (posedge clk)
begin
if (counter == 5'b11111) begin
// let Y value be assigned
// this clock cycle is idle
out = data_out;
c_flag = 1'b0;
end else if (counter == 5'b00000) begin
flag <= 1'b0;
dataa <= A1;
datab <= Y1;
sum <= {(2 * `WIDTH){1'b0}};
end else if (counter == 5'b00001) begin
dataa <= A2;
datab <= Y2;
sum <= add_out;
end else if (counter == 5'b00010) begin
dataa <= A3;
datab <= Y3;
sum <= add_out;
end else if (counter == 5'b00011) begin
dataa <= A4;
datab <= Y4;
sum <= add_out;
end else if (counter == 5'b00100) begin
dataa <= A5;
datab <= Y5;
sum <= add_out;
end else if (counter == 5'b00101) begin
dataa <= A6;
datab <= Y6;
sum <= add_out;
end else if (counter == 5'b00110) begin
dataa <= A7;
datab <= Y7;
sum <= add_out;
end else if (counter == 5'b00111) begin
dataa <= A8;
datab <= Y8;
sum <= add_out;
end else if (counter == 5'b01000) begin
dataa <= A9;
datab <= Y9;
sum <= add_out;
end else if (counter == 5'b01001) begin
outY <= add_out;
dataa <= B1;
datab <= U1;
sum <= {(2 * `WIDTH){1'b0}};
end else if (counter == 5'b01010) begin
dataa <= B2;
datab <= U2;
sum <= add_out;
end else if (counter == 5'b01011) begin
dataa <= B3;
datab <= U3;
sum <= add_out;
end else if (counter == 5'b01100) begin
dataa <= B4;
datab <= U4;
sum <= add_out;
end else if (counter == 5'b01101) begin
dataa <= B5;
datab <= U5;
sum <= add_out;
end else if (counter == 5'b01110) begin
dataa <= B6;
datab <= U6;
sum <= add_out;
end else if (counter == 5'b01111) begin
dataa <= B7;
datab <= U7;
sum <= add_out;
end else if (counter == 5'b10000) begin
dataa <= B8;
datab <= U8;
sum <= add_out;
end else if (counter == 5'b10001) begin
dataa <= B9;
datab <= U9;
sum <= add_out;
end else if (counter == 5'b10010) begin
adda <= outY;
addb <= add_out;
end else if (counter == 5'b10011) begin
adda <= I;
addb <= data_out;
c_flag <= 1'b1;
flag <= 1'b1;
counter = 5'b11110;
end
counter = counter + 5'b1;
end
multiplier u1(
.dataa(dataa[`WIDTH - 1:0]),
.datab(datab[2 * `WIDTH - 1:0]),
.dataout(mult_out[2 * `WIDTH - 1:0])
);
adder u2(
.dataa(mult_out[2 * `WIDTH - 1:0]),
.datab(sum[2 * `WIDTH - 1:0]),
.dataout(add_out[2 * `WIDTH - 1:0])
);
adder u3(
.dataa(adda[2 * `WIDTH - 1:0]),
.datab(addb[2 * `WIDTH - 1:0]),
.dataout(data_out[2 * `WIDTH - 1:0])
);
endmodule |
module eq1 (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
I,
out
);
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
// Y matrix will be 16 bits since we are storing the multiplied value of A*Y + B*U
input wire signed [2 * `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
wire signed [2 * `WIDTH - 1:0] outY;
wire signed [2 * `WIDTH - 1:0] outU;
input wire signed [`WIDTH - 1:0] I;
output wire signed [2 * `WIDTH - 1:0] out;
// Implementing the equations here. Multiply the corresponding indexes of the matrices and add them.
// outU and outY are intermediate signals used to store the sum.
assign outY = (A1 * Y1)+ (A2 * Y2) + (A3 * Y3) + (A4 * Y4) + (A5 * Y5) + (A6 * Y6) + (A7 * Y7) + (A8 * Y8) + (A9 * Y9);
assign outU = (B1 * U1)+ (B2 * U2) + (B3 * U3) + (B4 * U4) + (B5 * U5) + (B6 * U6) + (B7 * U7) + (B8 * U8) + (B9 * U9);
assign out = outY + outU + I;
endmodule |
module CNNfourbyfour (
clk,
Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out
);
input wire clk;
wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
wire signed [`WIDTH - 1:0] U1_in, U2_in, U3_in, U4_in, U5_in, U6_in, U7_in, U8_in, U9_in, U10_in, U11_in, U12_in, U13_in, U14_in, U15_in, U16_in;
wire signed [`WIDTH - 1:0] I;
wire signed [2 * `WIDTH - 1:0] Initial_X;
output wire signed [2 * `WIDTH - 1:0] Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out;
//Value type is {signed, 2^3, 2^2, 2^1, 2^0, 2^-1...}
assign A1 = `WIDTH'b0;
assign A2 = `WIDTH'b0;
assign A3 = `WIDTH'b0;
assign A4 = `WIDTH'b0;
assign A5 = `WIDTH'b000010000;
assign A6 = `WIDTH'b0;
assign A7 = `WIDTH'b0;
assign A8 = `WIDTH'b0;
assign A9 = `WIDTH'b0;
assign B1 = `WIDTH'b111110000;
assign B2 = `WIDTH'b111110000;
assign B3 = `WIDTH'b111110000;
assign B4 = `WIDTH'b111110000;
assign B5 = `WIDTH'b001000000;
assign B6 = `WIDTH'b111110000;
assign B7 = `WIDTH'b111110000;
assign B8 = `WIDTH'b111110000;
assign B9 = `WIDTH'b111110000;
assign U1_in = `WIDTH'b0;
assign U2_in = `WIDTH'b0;
assign U3_in = `WIDTH'b0;
assign U4_in = `WIDTH'b0;
assign U5_in = `WIDTH'b0;
assign U6_in = `WIDTH'b000010000;
assign U7_in = `WIDTH'b000010000;
assign U8_in = `WIDTH'b0;
assign U9_in = `WIDTH'b0;
assign U10_in = `WIDTH'b000010000;
assign U11_in = `WIDTH'b000010000;
assign U12_in = `WIDTH'b0;
assign U13_in = `WIDTH'b0;
assign U14_in = `WIDTH'b0;
assign U15_in = `WIDTH'b0;
assign U16_in = `WIDTH'b0;
assign I = `WIDTH'b110110000;
assign Initial_X = {(2 * `WIDTH){1'b0}};
fourbyfour u1(
.clk(clk),
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),
.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),
.U1_in(U1_in[`WIDTH - 1:0]),
.U2_in(U2_in[`WIDTH - 1:0]),
.U3_in(U3_in[`WIDTH - 1:0]),
.U4_in(U4_in[`WIDTH - 1:0]),
.U5_in(U5_in[`WIDTH - 1:0]),
.U6_in(U6_in[`WIDTH - 1:0]),
.U7_in(U7_in[`WIDTH - 1:0]),
.U8_in(U8_in[`WIDTH - 1:0]),
.U9_in(U9_in[`WIDTH - 1:0]),
.U10_in(U10_in[`WIDTH - 1:0]),
.U11_in(U11_in[`WIDTH - 1:0]),
.U12_in(U12_in[`WIDTH - 1:0]),
.U13_in(U13_in[`WIDTH - 1:0]),
.U14_in(U14_in[`WIDTH - 1:0]),
.U15_in(U15_in[`WIDTH - 1:0]),
.U16_in(U16_in[`WIDTH - 1:0]),
.Y1_out(Y1_out[2 * `WIDTH - 1:0]),
.Y2_out(Y2_out[2 * `WIDTH - 1:0]),
.Y3_out(Y3_out[2 * `WIDTH - 1:0]),
.Y4_out(Y4_out[2 * `WIDTH - 1:0]),
.Y5_out(Y5_out[2 * `WIDTH - 1:0]),
.Y6_out(Y6_out[2 * `WIDTH - 1:0]),
.Y7_out(Y7_out[2 * `WIDTH - 1:0]),
.Y8_out(Y8_out[2 * `WIDTH - 1:0]),
.Y9_out(Y9_out[2 * `WIDTH - 1:0]),
.Y10_out(Y10_out[2 * `WIDTH - 1:0]),
.Y11_out(Y11_out[2 * `WIDTH - 1:0]),
.Y12_out(Y12_out[2 * `WIDTH - 1:0]),
.Y13_out(Y13_out[2 * `WIDTH - 1:0]),
.Y14_out(Y14_out[2 * `WIDTH - 1:0]),
.Y15_out(Y15_out[2 * `WIDTH - 1:0]),
.Y16_out(Y16_out[2 * `WIDTH - 1:0]),
.I(I[`WIDTH - 1:0]),
.Initial_X_in(Initial_X[2 * `WIDTH - 1:0])
);
endmodule |
module one_by_one (
clk,
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
I,
Initial_X,
eq1out,
out
);
input clk;
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
input wire signed [`WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
input wire signed [`WIDTH - 1:0] I;
input wire signed [`WIDTH - 1:0] Initial_X;
output wire signed [`WIDTH - 1:0] eq1out;
output wire signed [`WIDTH - 1:0] out;
equation1 u1(
.clk(clk),
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),
.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),
.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),
.Y1(Y1[`WIDTH - 1:0]),
.Y2(Y2[`WIDTH - 1:0]),
.Y3(Y3[`WIDTH - 1:0]),
.Y4(Y4[`WIDTH - 1:0]),
.Y5(Y5[`WIDTH - 1:0]),
.Y6(Y6[`WIDTH - 1:0]),
.Y7(Y7[`WIDTH - 1:0]),
.Y8(Y8[`WIDTH - 1:0]),
.Y9(Y9[`WIDTH - 1:0]),
.I(I[`WIDTH - 1:0]),
.out(eq1out[`WIDTH - 1:0])
);
equation2 u2(
.dX(eq1out[`WIDTH - 1:0]),
.Initial_X(Initial_X[`WIDTH - 1:0]),
.out(out[`WIDTH - 1:0])
);
endmodule |
module multiplier_unit#(parameter WIDTH = 9)
(
input signed[WIDTH-1:0] dataa,
input signed[WIDTH-1:0] datab,
output signed[2*WIDTH-1:0] dataout
);
assign dataout = dataa * datab;
endmodule |
module equation2 (
dX,
Initial_X,
out
);
input wire signed [`WIDTH - 1:0] dX;
input wire signed [`WIDTH - 1:0] Initial_X;
wire signed [`WIDTH - 1:0] X;
wire signed [`WIDTH - 1:0] Xplus1;
wire signed [`WIDTH - 1:0] Xminus1;
wire signed [`WIDTH - 1:0] Xplus;
wire signed [`WIDTH - 1:0] Xminus;
output wire signed [`WIDTH - 1:0] out;
assign X = dX + Initial_X;
assign Xplus1 = X + {{(`WIDTH-1){1'b0}}, 1'b1};
assign Xminus1 = X - {{(`WIDTH-1){1'b0}}, 1'b1};
assign Xplus = (Xplus1[`WIDTH - 1])?(~Xplus1+{{(`WIDTH-1){1'b0}}, 1'b1}):Xplus1;
assign Xminus = (Xminus1[`WIDTH - 1])?(~Xminus1+{{(`WIDTH-1){1'b0}}, 1'b1}):Xminus1;
assign out = (Xplus - Xminus) >>> {{(`WIDTH-1){1'b0}}, 1'b1};
endmodule |
module four_by_four (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1_in, U2_in, U3_in, U4_in, U5_in, U6_in, U7_in, U8_in, U9_in, U10_in, U11_in, U12_in, U13_in, U14_in, U15_in, U16_in,
I,
Initial_X_in,
clk,
Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out
);
input wire clk;
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1_in, U2_in, U3_in, U4_in, U5_in, U6_in, U7_in, U8_in, U9_in, U10_in, U11_in, U12_in, U13_in, U14_in, U15_in, U16_in;
input wire signed [`WIDTH - 1:0] I;
input wire signed [ `WIDTH - 1:0] Initial_X_in;
reg signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
reg signed [`WIDTH - 1:0] X1_in = 0, X2_in = 0, X3_in = 0, X4_in = 0, X5_in = 0, X6_in = 0, X7_in = 0;
reg signed [ `WIDTH - 1:0] X8_in = 0, X9_in = 0, X10_in = 0, X11_in = 0, X12_in = 0, X13_in = 0, X14_in = 0, X15_in = 0, X16_in = 0;
reg signed [ `WIDTH - 1:0] X;
reg signed [ `WIDTH - 1:0] Y1_in = 0, Y2_in = 0, Y3_in = 0, Y4_in = 0, Y5_in = 0, Y6_in = 0, Y7_in = 0;
reg signed [ `WIDTH - 1:0] Y8_in = 0, Y9_in = 0, Y10_in = 0, Y11_in = 0, Y12_in = 0, Y13_in = 0, Y14_in = 0, Y15_in = 0, Y16_in = 0;
reg signed [ `WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
reg [`COUNTER_WIDTH_FOUR_BY_FOUR - 1:0] counter = `COUNTER_WIDTH_FOUR_BY_FOUR'b0;
reg [`Internal_counter_width - 1:0] internal_counter = `Internal_counter_width'b0;
wire signed [ `WIDTH - 1:0] X_onebyoneout;
wire signed [ `WIDTH - 1:0] Y_onebyoneout;
reg initial_flag = 1'b1;
// Setting X_next and Y_next to 0 as that would be the initial values.
reg signed [ `WIDTH - 1:0] X1_next = 0, X2_next = 0, X3_next = 0, X4_next = 0, X5_next = 0, X6_next = 0;
reg signed [`WIDTH - 1:0] X7_next = 0, X8_next = 0, X9_next = 0, X10_next = 0, X11_next = 0, X12_next = 0, X13_next = 0;
reg signed [ `WIDTH - 1:0] X14_next = 0, X15_next = 0, X16_next = 0;
reg signed [`WIDTH - 1:0] Y1_next = 0, Y2_next = 0, Y3_next = 0, Y4_next = 0, Y5_next = 0, Y6_next = 0;
reg signed [`WIDTH - 1:0] Y7_next = 0, Y8_next = 0, Y9_next = 0, Y10_next = 0, Y11_next = 0, Y12_next = 0, Y13_next = 0;
reg signed [`WIDTH - 1:0] Y14_next = 0, Y15_next = 0, Y16_next = 0;
output wire signed [ `WIDTH - 1:0] Y1_out, Y2_out, Y3_out, Y4_out, Y5_out, Y6_out, Y7_out, Y8_out, Y9_out, Y10_out, Y11_out, Y12_out, Y13_out, Y14_out, Y15_out, Y16_out;
assign Y1_out = Y1_next;assign Y2_out = Y2_next;assign Y3_out = Y3_next;assign Y4_out = Y4_next;assign Y5_out = Y5_next;assign Y6_out = Y6_next;assign Y7_out = Y7_next;
assign Y8_out = Y8_next;assign Y9_out = Y9_next;assign Y10_out = Y10_next;assign Y11_out = Y11_next;assign Y12_out = Y12_next;assign Y13_out = Y13_next;
assign Y14_out = Y14_next;assign Y15_out = Y15_next;assign Y16_out = Y16_next;
always @ (posedge clk)
begin
if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0000) begin // 1
if (internal_counter < 9) begin//internally counting to share the hardware units
// when the initial flag is 0 then set all Y and X to next value of Y and X. if it is 1, set X to initial X.
if (initial_flag == 1'b0) begin
Y16_next = Y_onebyoneout;
X16_next = X_onebyoneout;
Y1_in = Y1_next;
Y2_in = Y2_next;
Y3_in = Y3_next;
Y4_in = Y4_next;
Y5_in = Y5_next;
Y6_in = Y6_next;
Y7_in = Y7_next;
Y8_in = Y8_next;
Y9_in = Y9_next;
Y10_in = Y10_next;
Y11_in = Y11_next;
Y12_in = Y12_next;
Y13_in = Y13_next;
Y14_in = Y14_next;
Y15_in = Y15_next;
Y16_in = Y16_next;
X1_in = X1_next;
X2_in = X2_next;
X3_in = X3_next;
X4_in = X4_next;
X5_in = X5_next;
X6_in = X6_next;
X7_in = X7_next;
X8_in = X8_next;
X9_in = X9_next;
X10_in = X10_next;
X11_in = X11_next;
X12_in = X12_next;
X13_in = X13_next;
X14_in = X14_next;
X15_in = X15_next;
X16_in = X16_next;
end else begin
X1_in = Initial_X_in;
X2_in = Initial_X_in;
X3_in = Initial_X_in;
X4_in = Initial_X_in;
X5_in = Initial_X_in;
X6_in = Initial_X_in;
X7_in = Initial_X_in;
X8_in = Initial_X_in;
X9_in = Initial_X_in;
X10_in = Initial_X_in;
X11_in = Initial_X_in;
X12_in = Initial_X_in;
X13_in = Initial_X_in;
X14_in = Initial_X_in;
X15_in = Initial_X_in;
X16_in = Initial_X_in;
initial_flag = 1'b0;
end
// Each Input matrix is definied. The boundaries will be 0. For examples, around location 2, the inputs will be 0,0,0,U1, U2, U3, U4, U5, U6 and the counter_width
// will be 1
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= `WIDTH'b0;
U5 <= U1_in;
U6 <= U2_in;
U7 <= `WIDTH'b0;
U8 <= U5_in;
U9 <= U6_in;
X <= X1_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y1_in;
Y6 <= Y2_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y5_in;
Y9 <= Y6_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0001) begin // 2
if (internal_counter < 18 && internal_counter>8) begin
Y1_next <= Y_onebyoneout;
X1_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U1_in;
U5 <= U2_in;
U6 <= U3_in;
U7 <= U5_in;
U8 <= U6_in;
U9 <= U7_in;
X <= X2_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y1_in;
Y5 <= Y2_in;
Y6 <= Y3_in;
Y7 <= Y5_in;
Y8 <= Y6_in;
Y9 <= Y7_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0010) begin // 3
if (internal_counter>=9 && internal_counter <=17) begin
Y2_next <= Y_onebyoneout;
X2_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U2_in;
U5 <= U3_in;
U6 <= U4_in;
U7 <= U6_in;
U8 <= U7_in;
U9 <= U8_in;
X <= X3_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y2_in;
Y5 <= Y3_in;
Y6 <= Y4_in;
Y7 <= Y6_in;
Y8 <= Y7_in;
Y9 <= Y8_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0011) begin // 4
if (internal_counter >= 18 && internal_counter<=26) begin
Y3_next <= Y_onebyoneout;
X3_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= `WIDTH'b0;
U3 <= `WIDTH'b0;
U4 <= U3_in;
U5 <= U4_in;
U6 <= `WIDTH'b0;
U7 <= U7_in;
U8 <= U8_in;
U9 <= `WIDTH'b0;
X <= X4_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= {(2 * `WIDTH){1'b0}};
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y3_in;
Y5 <= Y4_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y7_in;
Y8 <= Y8_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0100) begin // 5
if (internal_counter >=27 && internal_counter<=35) begin
Y4_next <= Y_onebyoneout;
X4_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U1_in;
U3 <= U2_in;
U4 <= `WIDTH'b0;
U5 <= U5_in;
U6 <= U6_in;
U7 <= `WIDTH'b0;
U8 <= U9_in;
U9 <= U10_in;
X <= X5_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y1_in;
Y3 <= Y2_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y5_in;
Y6 <= Y6_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y9_in;
Y9 <= Y10_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0101) begin // 6
if (internal_counter >=36 && internal_counter<=44) begin
Y5_next <= Y_onebyoneout;
X5_next <= X_onebyoneout;
U1 <= U1_in;
U2 <= U2_in;
U3 <= U3_in;
U4 <= U5_in;
U5 <= U6_in;
U6 <= U7_in;
U7 <= U9_in;
U8 <= U10_in;
U9 <= U11_in;
X <= X6_in;
Y1 <= Y1_in;
Y2 <= Y2_in;
Y3 <= Y3_in;
Y4 <= Y5_in;
Y5 <= Y6_in;
Y6 <= Y7_in;
Y7 <= Y9_in;
Y8 <= Y10_in;
Y9 <= Y11_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0110) begin // 7
if (internal_counter >=45&& internal_counter<=53) begin
Y6_next <= Y_onebyoneout;
X6_next <= X_onebyoneout;
U1 <= U2_in;
U2 <= U3_in;
U3 <= U4_in;
U4 <= U6_in;
U5 <= U7_in;
U6 <= U8_in;
U7 <= U10_in;
U8 <= U11_in;
U9 <= U12_in;
X <= X7_in;
Y1 <= Y2_in;
Y2 <= Y3_in;
Y3 <= Y4_in;
Y4 <= Y6_in;
Y5 <= Y7_in;
Y6 <= Y8_in;
Y7 <= Y10_in;
Y8 <= Y11_in;
Y9 <= Y12_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b0111) begin // 8
if (internal_counter>=54 && internal_counter<=62) begin
Y7_next <= Y_onebyoneout;
X7_next <= X_onebyoneout;
U1 <= U3_in;
U2 <= U4_in;
U3 <= `WIDTH'b0;
U4 <= U7_in;
U5 <= U8_in;
U6 <= `WIDTH'b0;
U7 <= U11_in;
U8 <= U12_in;
U9 <= `WIDTH'b0;
X <= X8_in;
Y1 <= Y3_in;
Y2 <= Y4_in;
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y7_in;
Y5 <= Y8_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y11_in;
Y8 <= Y12_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1000) begin // 9
if (internal_counter >=63 && internal_counter<=71) begin
Y8_next <= Y_onebyoneout;
X8_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U5_in;
U3 <= U6_in;
U4 <= `WIDTH'b0;
U5 <= U9_in;
U6 <= U10_in;
U7 <= `WIDTH'b0;
U8 <= U13_in;
U9 <= U14_in;
X <= X9_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y5_in;
Y3 <= Y6_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y9_in;
Y6 <= Y10_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= Y13_in;
Y9 <= Y14_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1001) begin // 10
if (internal_counter >=72 && internal_counter<=80) begin
Y9_next <= Y_onebyoneout;
X9_next <= X_onebyoneout;
U1 <= U5_in;
U2 <= U6_in;
U3 <= U7_in;
U4 <= U9_in;
U5 <= U10_in;
U6 <= U11_in;
U7 <= U13_in;
U8 <= U14_in;
U9 <= U15_in;
X <= X10_in;
Y1 <= Y5_in;
Y2 <= Y6_in;
Y3 <= Y7_in;
Y4 <= Y9_in;
Y5 <= Y10_in;
Y6 <= Y11_in;
Y7 <= Y13_in;
Y8 <= Y14_in;
Y9 <= Y15_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1010) begin // 11
if (internal_counter >=81 && internal_counter<=89) begin
Y10_next <= Y_onebyoneout;
X10_next <= X_onebyoneout;
U1 <= U6_in;
U2 <= U7_in;
U3 <= U8_in;
U4 <= U10_in;
U5 <= U11_in;
U6 <= U12_in;
U7 <= U14_in;
U8 <= U15_in;
U9 <= U16_in;
X <= X11_in;
Y1 <= Y6_in;
Y2 <= Y7_in;
Y3 <= Y8_in;
Y4 <= Y10_in;
Y5 <= Y11_in;
Y6 <= Y12_in;
Y7 <= Y14_in;
Y8 <= Y15_in;
Y9 <= Y16_in;
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1011) begin // 12
if (internal_counter >=90 && internal_counter<=98) begin
Y11_next <= Y_onebyoneout;
X11_next <= X_onebyoneout;
U1 <= U7_in;
U2 <= U8_in;
U3 <= `WIDTH'b0;
U4 <= U11_in;
U5 <= U12_in;
U6 <= `WIDTH'b0;
U7 <= U15_in;
U8 <= U16_in;
U9 <= `WIDTH'b0;
X <= X12_in;
Y1 <= Y7_in;
Y2 <= Y8_in;
Y3 <= {(2 * `WIDTH){1'b0}};
Y4 <= Y11_in;
Y5 <= Y12_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= Y15_in;
Y8 <= Y16_in;
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1100) begin // 13
if (internal_counter >=99 && internal_counter<=107) begin
Y12_next <= Y_onebyoneout;
X12_next <= X_onebyoneout;
U1 <= `WIDTH'b0;
U2 <= U9_in;
U3 <= U10_in;
U4 <= `WIDTH'b0;
U5 <= U13_in;
U6 <= U14_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X13_in;
Y1 <= {(2 * `WIDTH){1'b0}};
Y2 <= Y9_in;
Y3 <= Y10_in;
Y4 <= {(2 * `WIDTH){1'b0}};
Y5 <= Y13_in;
Y6 <= Y14_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1101) begin // 14
if (internal_counter >=108 && internal_counter<=116) begin
Y13_next <= Y_onebyoneout;
X13_next <= X_onebyoneout;
U1 <= U9_in;
U2 <= U10_in;
U3 <= U11_in;
U4 <= U13_in;
U5 <= U14_in;
U6 <= U15_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X14_in;
Y1 <= Y9_in;
Y2 <= Y10_in;
Y3 <= Y11_in;
Y4 <= Y13_in;
Y5 <= Y14_in;
Y6 <= Y15_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1110) begin // 15
if (internal_counter>=117 && internal_counter<=125) begin
Y14_next <= Y_onebyoneout;
X14_next <= X_onebyoneout;
U1 <= U10_in;
U2 <= U11_in;
U3 <= U12_in;
U4 <= U14_in;
U5 <= U15_in;
U6 <= U16_in;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X15_in;
Y1 <= Y10_in;
Y2 <= Y11_in;
Y3 <= Y12_in;
Y4 <= Y14_in;
Y5 <= Y15_in;
Y6 <= Y16_in;
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end
end else if (counter == `COUNTER_WIDTH_FOUR_BY_FOUR'b1111) begin // 16
if (internal_counter >=126 && internal_counter<=134) begin
Y15_next <= Y_onebyoneout;
X15_next <= X_onebyoneout;
U1 <= U11_in;
U2 <= U12_in;
U3 <= `WIDTH'b0;
U4 <= U15_in;
U5 <= U16_in;
U6 <= `WIDTH'b0;
U7 <= `WIDTH'b0;
U8 <= `WIDTH'b0;
U9 <= `WIDTH'b0;
X <= X16_in;
Y1 <= Y11_in;
Y2 <= Y12_in;
Y3 <= `WIDTH'b0;
Y4 <= Y15_in;
Y5 <= Y16_in;
Y6 <= {(2 * `WIDTH){1'b0}};
Y7 <= {(2 * `WIDTH){1'b0}};
Y8 <= {(2 * `WIDTH){1'b0}};
Y9 <= {(2 * `WIDTH){1'b0}};
end
end
//Increment the counter at the end of each iteration
internal_counter= internal_counter + `Internal_counter_width'b1;
if(internal_counter%9==0)
begin
counter = counter + `COUNTER_WIDTH_FOUR_BY_FOUR'b1;
end
end
// Once the inputs are set, they are given to the onebyone module which then does the computation of the outputs.
one_by_one arr1(
.clk(clk),
.A1(A1[`WIDTH - 1:0]),
.A2(A2[`WIDTH - 1:0]),
.A3(A3[`WIDTH - 1:0]),
.A4(A4[`WIDTH - 1:0]),
.A5(A5[`WIDTH - 1:0]),
.A6(A6[`WIDTH - 1:0]),
.A7(A7[`WIDTH - 1:0]),
.A8(A8[`WIDTH - 1:0]),
.A9(A9[`WIDTH - 1:0]),
.B1(B1[`WIDTH - 1:0]),
.B2(B2[`WIDTH - 1:0]),
.B3(B3[`WIDTH - 1:0]),
.B4(B4[`WIDTH - 1:0]),
.B5(B5[`WIDTH - 1:0]),
.B6(B6[`WIDTH - 1:0]),
.B7(B7[`WIDTH - 1:0]),
.B8(B8[`WIDTH - 1:0]),
.B9(B9[`WIDTH - 1:0]),
.U1(U1[`WIDTH - 1:0]),
.U2(U2[`WIDTH - 1:0]),
.U3(U3[`WIDTH - 1:0]),
.U4(U4[`WIDTH - 1:0]),
.U5(U5[`WIDTH - 1:0]),
.U6(U6[`WIDTH - 1:0]),
.U7(U7[`WIDTH - 1:0]),
.U8(U8[`WIDTH - 1:0]),
.U9(U9[`WIDTH - 1:0]),
.Y1(Y1[ `WIDTH - 1:0]),
.Y2(Y2[ `WIDTH - 1:0]),
.Y3(Y3[ `WIDTH - 1:0]),
.Y4(Y4[`WIDTH - 1:0]),
.Y5(Y5[ `WIDTH - 1:0]),
.Y6(Y6[ `WIDTH - 1:0]),
.Y7(Y7[ `WIDTH - 1:0]),
.Y8(Y8[ `WIDTH - 1:0]),
.Y9(Y9[`WIDTH - 1:0]),
.I(I[`WIDTH - 1:0]),
.eq1out(X_onebyoneout[ `WIDTH - 1:0]),
.out(Y_onebyoneout[ `WIDTH - 1:0]),
.X(X[`WIDTH - 1:0])
);
endmodule |
module adder_unit#(parameter WIDTH=9)
(//input declarations
input signed[WIDTH-1:0] A_in,input signed[WIDTH-1:0] B_in,
//output declarations
output reg signed[WIDTH-1:0] C_out);
always@(*)
begin
if(A_in[WIDTH-1]^B_in[WIDTH-1]==0)
begin
C_out[WIDTH-2:0]<= B_in[WIDTH-2:0] + A_in[WIDTH-2:0];
C_out[WIDTH-1]<= A_in[WIDTH-1];
end
if(A_in[WIDTH-1]^B_in[WIDTH-1]==1)
//if({A_in[WIDTH-1]B_in[WIDTH-1]}==01)
begin
C_out[WIDTH-2:0] <= (B_in[WIDTH-2:0]>A_in[WIDTH-2:0])?(B_in[WIDTH-2:0]-A_in[WIDTH-2:0]):(A_in[WIDTH-2:0]-B_in[WIDTH-2:0]);
C_out[WIDTH-1] <= (B_in[WIDTH-2:0]>A_in[WIDTH-2:0])?(B_in[WIDTH-1]):(A_in[WIDTH-1]);
end
end
endmodule |
module convolution#(parameter WIDTH = 9)
(
input clk,
//input reg [3:0]counter,
input signed [WIDTH-1:0] a0_in,input signed [WIDTH-1:0] a1_in,input signed [WIDTH-1:0] a2_in,input signed [WIDTH-1:0] a3_in,
input signed [WIDTH-1:0] a4_in,input signed [WIDTH-1:0] a5_in,input signed [WIDTH-1:0] a6_in,input signed [WIDTH-1:0] a7_in,input signed [WIDTH-1:0] a8_in,
input signed [WIDTH-1:0] y0_in,input signed [WIDTH-1:0] y1_in,input signed [WIDTH-1:0] y2_in,input signed [WIDTH-1:0] y3_in,
input signed [WIDTH-1:0] y4_in,input signed [WIDTH-1:0] y5_in,input signed [WIDTH-1:0] y6_in,input signed [WIDTH-1:0] y7_in,input signed [WIDTH-1:0] y8_in,
output wire signed [WIDTH-1:0]outreg1
);
reg signed[WIDTH-1:0] a_reg;
reg signed[WIDTH-1:0] y_reg;
wire signed[2*WIDTH-1:0]mult1_out;
//wire[2*WIDTH-1:0] outreg1;
reg signed[2*WIDTH-1:0]multi_out;
reg [3:0]clk_counter;
reg signed[WIDTH-1:0] sum1;
initial
begin
clk_counter=0;
sum1=0;
multi_out=0;
end
//assign mult1_out=0;
multiplier_unit mul1(a_reg,y_reg,mult1_out);
adder_unit add1({mult1_out[2*WIDTH-1],mult1_out[2*WIDTH-11:0]},sum1,outreg1);
always @ (posedge clk)
begin
case(clk_counter)
0:begin
a_reg <= a0_in;
y_reg <= y0_in;
//multi_out<=0;
clk_counter<=clk_counter+1;
end
1:begin
a_reg <= a1_in;//mult1 computed
y_reg <= y1_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
2:begin
a_reg <= a2_in;//mult1 computed
y_reg <= y2_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
3:begin
a_reg <= a3_in;//mult1 computed
y_reg <= y3_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
4:begin
a_reg <= a4_in;//mult1 computed
y_reg <= y4_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
5:begin
a_reg <= a5_in;//mult1 computed
y_reg <= y5_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
6:begin
a_reg <= a6_in;//mult1 computed
y_reg <= y6_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
7:begin
a_reg <= a7_in;//mult1 computed
y_reg <= y7_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
8:begin
a_reg <= a8_in;//mult1 computed
y_reg <= y8_in;
//multi_out<=mult1_out;
sum1<=outreg1;
clk_counter<=clk_counter+1;
end
endcase
end
endmodule |
module equation1 (
clk,
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5, B6, B7, B8, B9,
U1, U2, U3, U4, U5, U6, U7, U8, U9,
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,
I,
out
);
input clk;
input wire signed [`WIDTH - 1:0] A1, A2, A3, A4, A5, A6, A7, A8, A9;
input wire signed [`WIDTH - 1:0] B1, B2, B3, B4, B5, B6, B7, B8, B9;
input wire signed [`WIDTH - 1:0] U1, U2, U3, U4, U5, U6, U7, U8, U9;
input wire signed [`WIDTH - 1:0] Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9;
wire signed [`WIDTH - 1:0] outY;
wire signed [`WIDTH - 1:0] outU;
wire signed [`WIDTH - 1:0] ayplusbu;
input wire signed [`WIDTH - 1:0] I;
output wire signed [`WIDTH - 1:0] out;
//assign outY = (A1 * Y1)+ (A2 * Y2) + (A3 * Y3) + (A4 * Y4) + (A5 * Y5) + (A6 * Y6) + (A7 * Y7) + (A8 * Y8) + (A9 * Y9);
//assign outU = (B1 * U1)+ (B2 * U2) + (B3 * U3) + (B4 * U4) + (B5 * U5) + (B6 * U6) + (B7 * U7) + (B8 * U8) + (B9 * U9);
convolution conv1(clk, A1, A2, A3, A4, A5, A6, A7, A8, A9,Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9,outY);
convolution conv2(clk, B1, B2, B3, B4, B5, B6, B7, B8, B9,U1, U2, U3, U4, U5, U6, U7, U8, U9,outU);
adder_unit add2(outY,outU,ayplusbu);
adder_unit add3(I,ayplusbu,out);
//out = outY + outU + I;
endmodule |
module aib_channel
#(
parameter DATAWIDTH = 20
)
(
inout wire [DATAWIDTH-1:0] iopad_txdat,
inout wire [DATAWIDTH-1:0] iopad_rxdat,
inout wire iopad_txclkb,
inout wire iopad_txclk,
inout wire iopad_txfck,
inout wire iopad_txfckb,
inout wire iopad_stck,
inout wire iopad_stckb,
inout wire iopad_stl,
inout wire iopad_std,
inout wire iopad_rstno,
inout wire iopad_arstno,
inout wire iopad_spareo,
inout wire iopad_sparee,
inout wire iopad_rxclkb,
inout wire iopad_rxclk,
inout wire iopad_rxfckb,
inout wire iopad_rxfck,
inout wire iopad_srckb,
inout wire iopad_srck,
inout wire iopad_srl,
inout wire iopad_srd,
inout wire iopad_rstni,
inout wire iopad_arstni,
input tx_launch_clk, //output data clock
output wire fs_rvc_clk_tomac,
output wire fs_fwd_clk_tomac,
input ns_rvc_clk_frmac,
input iddren,
input idataselb, //output async data selection
input itxen, //data tx enable
input [2:0] irxen,//data input enable
input [DATAWIDTH-1:0] idat0, //output data to pad
input [DATAWIDTH-1:0] idat1, //output data to pad
output wire [DATAWIDTH-1:0] data_out0, //input data from pad
output wire [DATAWIDTH-1:0] data_out1, //input data from pad
input ms_config_done,
input ms_rx_dcc_dll_lock_req,
input ms_tx_dcc_dll_lock_req,
input sl_config_done,
input sl_tx_dcc_dll_lock_req,
input sl_rx_dcc_dll_lock_req,
output wire ms_tx_transfer_en,
output wire ms_rx_transfer_en,
output wire sl_tx_transfer_en,
output wire sl_rx_transfer_en,
output wire [80:0] sr_ms_tomac,
output wire [72:0] sr_sl_tomac,
input ms_adapter_rstn, //ns_adapter_rstn
input sl_adapter_rstn, //ns_adapter_rstn
input ms_rstn, //ns_mac_rdy
input sl_rstn, //ns_mac_rdy
output wire fs_mac_rdy_tomac,
input por_sl,
input ms_nsl,
input por_ms, //from aux channel
input osc_clk, //from aux channel
input jtag_clkdr_in,
output wire scan_out,
input jtag_intest,
input jtag_mode_in,
input jtag_rstb,
input jtag_rstb_en,
input jtag_weakpdn,
input jtag_weakpu,
input jtag_tx_scanen_in,
input scan_in,
input [DATAWIDTH-1:0] tx_shift_en, //tx red. shift enable
input [DATAWIDTH-1:0] rx_shift_en, //rx red. shift enable
input shift_en_txclkb,
input shift_en_txfckb,
input shift_en_stckb,
input shift_en_stl,
input shift_en_arstno,
input shift_en_txclk,
input shift_en_std,
input shift_en_stck,
input shift_en_txfck,
input shift_en_rstno,
input shift_en_rxclkb,
input shift_en_rxfckb,
input shift_en_srckb,
input shift_en_srl,
input shift_en_arstni,
input shift_en_rxclk,
input shift_en_rxfck,
input shift_en_srck,
input shift_en_srd,
input shift_en_rstni,
input [26:0] sl_external_cntl_26_0, //user defined bits 26:0 for slave shift register
input [2:0] sl_external_cntl_30_28, //user defined bits 30:28 for slave shift register
input [25:0] sl_external_cntl_57_32, //user defined bits 57:32 for slave shift register
input [4:0] ms_external_cntl_4_0, //user defined bits 4:0 for master shift register
input [57:0] ms_external_cntl_65_8, //user defined bits 65:8 for master shift register
input vccl_aib,
input vssl_aib );
wire is_master, is_slave;
wire dig_rstb;
wire ms_osc_transfer_en;
//wire ms_rx_transfer_en;
wire ms_osc_transfer_alive;
wire ms_rx_async_rst;
wire ms_rx_dll_lock_req;
wire ms_rx_dll_lock;
wire ms_tx_async_rst;
wire ms_tx_dcc_cal_req;
wire ms_tx_dcc_cal_done;
//wire ms_tx_transfer_en;
wire ms_tx_dcc_cal_doneint;
wire ms_rx_dll_lockint;
wire sl_osc_transfer_en;
//wire sl_rx_transfer_en;
wire sl_fifo_tx_async_rst;
wire sl_tx_dcc_cal_done;
wire sl_tx_dcc_cal_req;
//wire sl_tx_transfer_en;
wire sl_rx_async_rst;
wire sl_rx_dll_lock_req;
wire sl_rx_dll_lock;
wire sl_tx_dcc_cal_doneint;
wire sl_rx_dll_lockint;
wire std_out;
wire stl_out;
wire srd_in;
wire srl_in;
wire sr_ms_load_out;
wire sr_clk_in;
wire sr_clk_out;
wire adpt_rstn;
wire rstn_out, adapter_rstno;
wire sr_ms_data_out;
wire [80:0] ms_data_fr_core, ms_data_to_core;
wire sr_sl_clk_out;
wire [72:0] sl_data_fr_core, sl_data_to_core;
wire sr_sl_data_out;
wire sr_sl_load_out;
wire adapter_rstni;
wire dcc_clk_out;
wire rstn_in;
assign fs_mac_rdy_tomac = rstn_in;
assign sr_ms_tomac[80:0] = ms_data_to_core[80:0];
assign sr_sl_tomac[72:0] = sl_data_to_core[72:0];
assign is_master = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
assign adpt_rstn = is_master ? (ms_adapter_rstn & adapter_rstni) : (sl_adapter_rstn & adapter_rstni);
assign dig_rstb = is_master ? (ms_config_done & ms_rstn): (sl_config_done & sl_rstn);
//assign dig_rstb = is_master ? ms_rstn : sl_rstn;
assign sr_clk_out = is_master ? osc_clk : sr_sl_clk_out;
assign std_out = is_master ? sr_ms_data_out : sr_sl_data_out;
assign stl_out = is_master ? sr_ms_load_out : sr_sl_load_out;
assign adapter_rstno = is_master ? ms_adapter_rstn : sl_adapter_rstn;
assign rstn_out = is_master ? ms_rstn : sl_rstn;
assign ms_data_fr_core[80:0] = {ms_osc_transfer_en,1'b1,ms_tx_transfer_en,2'b11,ms_rx_transfer_en,ms_rx_dll_lock, 5'b11111,ms_tx_dcc_cal_done,1'b0,1'b1, ms_external_cntl_65_8[57:0], 1'b1, 1'b0, 1'b1, ms_external_cntl_4_0[4:0]};
assign sl_data_fr_core[72:0] = {sl_osc_transfer_en,1'b0,sl_rx_transfer_en,sl_rx_dcc_dll_lock_req, sl_rx_dll_lock,3'b0,sl_tx_transfer_en,sl_tx_dcc_dll_lock_req, 1'b0,1'b0,1'b1,1'b0, 1'b1, sl_external_cntl_57_32[25:0], sl_tx_dcc_cal_done, sl_external_cntl_30_28[2:0], 1'b0, sl_external_cntl_26_0[26:0]};
aib_ioring #(.DATAWIDTH(DATAWIDTH)) aib_ioring (
.iopad_txdat(iopad_txdat),
.iopad_rxdat(iopad_rxdat),
.iopad_txclkb(iopad_txclkb),
.iopad_txclk(iopad_txclk),
.iopad_txfck(iopad_txfck),
.iopad_txfckb(iopad_txfckb),
.iopad_stck(iopad_stck),
.iopad_stckb(iopad_stckb),
.iopad_stl(iopad_stl),
.iopad_std(iopad_std),
.iopad_rstno(iopad_rstno),
.iopad_arstno(iopad_arstno),
.iopad_spareo(iopad_spareo),
.iopad_sparee(iopad_sparee),
.iopad_rxclkb(iopad_rxclkb),
.iopad_rxclk(iopad_rxclk),
.iopad_rxfckb(iopad_rxfckb),
.iopad_rxfck(iopad_rxfck),
.iopad_srckb(iopad_srckb),
.iopad_srck(iopad_srck),
.iopad_srl(iopad_srl),
.iopad_srd(iopad_srd),
.iopad_rstni(iopad_rstni),
.iopad_arstni(iopad_arstni),
.tx_launch_clk(dcc_clk_out),
.fs_rvc_clk_tomac(fs_rvc_clk_tomac),
.fs_fwd_clk_tomac(fs_fwd_clk_tomac),
.ns_rvc_clk_frmac(ns_rvc_clk_frmac),
.dig_rstb(dig_rstb), //reset for io
.iddren(iddren),
.idataselb(idataselb),
.itxen(itxen),
.irxen(irxen),
.idat0(idat0),
.idat1(idat1),
.data_out0(data_out0),
.data_out1(data_out1),
.std_out(std_out),
.stl_out(stl_out),
.srd_in(srd_in),
.srl_in(srl_in),
.sr_clk_in(sr_clk_in),
.sr_clk_out(sr_clk_out),
.adapter_rstno(adapter_rstno),
.rstn_out(rstn_out),
.adapter_rstni(adapter_rstni),
.rstn_in(rstn_in),
.jtag_clkdr_in(jtag_clkdr_in),
.scan_out(scan_out),
.jtag_intest(jtag_intest),
.jtag_mode_in(jtag_mode_in),
.jtag_rstb(jtag_rstb),
.jtag_rstb_en(jtag_rstb_en),
.jtag_weakpdn(jtag_weakpdn),
.jtag_weakpu(jtag_weakpu),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.scan_in(scan_in),
.tx_shift_en(tx_shift_en),
.rx_shift_en(rx_shift_en),
.shift_en_txclkb(shift_en_txclkb),
.shift_en_txfckb(shift_en_txfckb),
.shift_en_stckb(shift_en_stckb),
.shift_en_stl(shift_en_stl),
.shift_en_arstno(shift_en_arstno),
.shift_en_txclk(shift_en_txclk),
.shift_en_std(shift_en_std),
.shift_en_stck(shift_en_stck),
.shift_en_txfck(shift_en_txfck),
.shift_en_rstno(shift_en_rstno),
.shift_en_rxclkb(shift_en_rxclkb),
.shift_en_rxfckb(shift_en_rxfckb),
.shift_en_srckb(shift_en_srckb),
.shift_en_srl(shift_en_srl),
.shift_en_arstni(shift_en_arstni),
.shift_en_rxclk(shift_en_rxclk),
.shift_en_rxfck(shift_en_rxfck),
.shift_en_srck(shift_en_srck),
.shift_en_srd(shift_en_srd),
.shift_en_rstni(shift_en_rstni),
.idataselb_stck(1'b1),
.idataselb_std(1'b1),
.idataselb_stl(1'b1),
.idataselb_arstno(1'b1),
.idataselb_rstno(1'b1),
.vccl_aib(vccl_aib),
.vssl_aib(vssl_aib) );
aib_sm aib_sm
(
.osc_clk(osc_clk), //from aux
.sr_ms_clk_in(sr_clk_in), //input ms clock
.ms_config_done(ms_config_done), //master config done
.ms_osc_transfer_en(ms_osc_transfer_en),
.ms_rx_transfer_en(ms_rx_transfer_en),
.ms_osc_transfer_alive(ms_osc_transfer_alive),
.ms_rx_async_rst(ms_rx_async_rst),
.ms_rx_dll_lock_req(ms_rx_dll_lock_req),
.ms_rx_dll_lock(ms_rx_dll_lock),
.ms_tx_async_rst(ms_tx_async_rst),
.ms_tx_dcc_cal_req(ms_tx_dcc_cal_req),
.sl_tx_dcc_cal_req(sl_tx_dcc_cal_req),
.ms_tx_dcc_cal_done(ms_tx_dcc_cal_done),
.ms_tx_transfer_en(ms_tx_transfer_en),
.ms_rx_dcc_dll_lock_req(ms_rx_dcc_dll_lock_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.ms_rx_dll_lockint(ms_rx_dll_lockint),
.ms_tx_dcc_cal_doneint(ms_tx_dcc_cal_doneint),
.ms_tx_dcc_cal_donei(ms_data_to_core[68]),
.ms_rx_dll_locki(ms_data_to_core[74]),
.ms_rx_transfer_eni(ms_data_to_core[75]),
.ms_tx_transfer_eni(ms_data_to_core[78]),
.ms_osc_transfer_eni(ms_data_to_core[80]),
.sl_config_done(sl_config_done), //slave config done
.sl_osc_transfer_en(sl_osc_transfer_en),
.sl_rx_transfer_en(sl_rx_transfer_en),
.sl_fifo_tx_async_rst(sl_fifo_tx_async_rst),
.sl_tx_dcc_cal_done(sl_tx_dcc_cal_done),
.sl_tx_transfer_en(sl_tx_transfer_en),
.sl_rx_async_rst(sl_rx_async_rst),
.sl_rx_dll_lock_req(sl_rx_dll_lock_req),
.sl_rx_dll_lock(sl_rx_dll_lock),
.sl_tx_dcc_dll_lock_req(sl_data_to_core[63]),
.sl_rx_dcc_dll_lock_req(sl_data_to_core[69]),
.sl_rx_dll_lockint(sl_rx_dll_lockint), //from slave internal
.sl_rx_dll_locki(sl_data_to_core[68]), //from sr interface
.sl_tx_dcc_cal_donei(sl_data_to_core[31]), //from sr interface
.sl_tx_dcc_cal_doneint(sl_tx_dcc_cal_doneint), //from slave internal
.sl_rx_transfer_eni(sl_data_to_core[70]),
.sl_osc_transfer_eni(sl_data_to_core[72]),
.ms_nsl(ms_nsl), //ms_adapter_rstn & sl_adapter_rstn
.atpg_mode(1'b0),
.reset_n(adpt_rstn) //ms_adapter_rstn & sl_adapter_rstn
);
aib_sr_ms #(
.MS_LENGTH(7'd81))
aib_sr_ms
(
.osc_clk(osc_clk), //free running osc clock
.ms_data_fr_core(ms_data_fr_core[80:0]),
.ms_data_to_core(ms_data_to_core[80:0]),
.sr_ms_data_out(sr_ms_data_out), //master serial data out
.sr_ms_load_out(sr_ms_load_out), //master load out
.sr_ms_data_in(srd_in), //master serial data out
.sr_ms_load_in(srl_in), //master serial data load inupt
.sr_ms_clk_in(sr_clk_in), //from input por
.ms_nsl(ms_nsl),
.atpg_mode(1'b0),
.reset_n(ms_config_done) //Per email from Tim on 10/17/19. And confirmation from Julie, this is equivalent to HARD_RESET
);
aib_sr_sl #(
.SL_LENGTH(7'd73))
aib_sr_sl
(
.sr_sl_clk_in(sr_clk_in), //From input
.sr_sl_clk_out(sr_sl_clk_out), //to output
.sl_data_fr_core(sl_data_fr_core[72:0]),
.sl_data_to_core(sl_data_to_core[72:0]),
.sr_sl_data_out(sr_sl_data_out), //slave serial data out
.sr_sl_load_out(sr_sl_load_out), //slave load out
.sr_sl_data_in(srd_in), //slave serial data out
.sr_sl_load_in(srl_in), //slave serial data load inupt
.sr_ms_clk_in(sr_clk_in), //input ms clock
.ms_nsl(ms_nsl),
.atpg_mode(1'b0),
.reset_n(sl_config_done) //Per email from Tim on 10/17/19. And confirmation from Julie, this is equivalent to HARD_RESET
);
aib_dcc aib_dcc
(
.clk_in(tx_launch_clk),
.ms_dcc_cal_req(ms_tx_dcc_cal_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.sl_dcc_cal_req(sl_tx_dcc_cal_req),
.sl_rx_dcc_dll_lock_req(sl_rx_dcc_dll_lock_req),
.ms_dcc_cal_done(ms_tx_dcc_cal_doneint),
.sl_dcc_cal_done(sl_tx_dcc_cal_doneint),
.clk_out(dcc_clk_out),
.ms_nsl(ms_nsl),
.atpg_mode(1'b0),
.reset_n(adpt_rstn)
);
dll u_dll
(
.clkp(fs_fwd_clk_tomac),
.clkn(~fs_fwd_clk_tomac),
.rstb(adpt_rstn), // Hold DDR in reset if SDR Mode
.rx_clk_tree_in(clk_dll_out),
.ms_rx_dll_lock_req(ms_rx_dll_lock_req),
.ms_rx_dll_lock(ms_rx_dll_lockint),
.sl_rx_dll_lock_req(sl_rx_dll_lock_req),
.sl_rx_dll_lock(sl_rx_dll_lockint),
.ms_nsl(ms_nsl),
.atpg_mode(1'b0)
);
endmodule // aib_channel |
module aib_sr_sl #(
parameter SL_LENGTH = 7'd73
)
(
input sr_sl_clk_in, //From input
output sr_sl_clk_out, //to output
input [SL_LENGTH-1:0] sl_data_fr_core,
output wire [SL_LENGTH-1:0] sl_data_to_core,
output reg sr_sl_data_out, //slave serial data out
output reg sr_sl_load_out, //slave load out
input sr_sl_data_in, //slave serial data out
input sr_sl_load_in, //slave serial data load inupt
input sr_ms_clk_in, //input ms clock
input ms_nsl,
input atpg_mode,
input reset_n
);
reg [6:0] sl_count;
reg sl_load;
reg [SL_LENGTH-1:0] sl_data_syncr; //master shift output register
reg [SL_LENGTH-1:0] sl_data_revr; //shift receive register
reg [SL_LENGTH-1:0] sl_data_capr; //captured master serial data register
reg sl_shift_en;
wire [SL_LENGTH-1:0] sl_data_sync, sl_data_syncrw, sl_data_revrw, sl_data_caprw;
wire reset_n_sync, reset_n_sync_rev;
wire sr_sl_data_outw; //slave serial data out
wire sr_sl_load_outw; //slave load out
assign sl_data_to_core[SL_LENGTH-1:0] = sl_data_capr[SL_LENGTH-1:0];
assign sr_sl_clk_out = sr_ms_clk_in;
aib_rstnsync aib_rstnsync
(
.clk(sr_sl_clk_out), // Destination clock of reset to be synced
.i_rst_n(reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync) // Synchronized reset output
);
aib_rstnsync aib_rstnsync_rev
(
.clk(sr_sl_clk_in), // Destination clock of reset to be synced
.i_rst_n(reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync_rev) // Synchronized reset output
);
genvar i;
generate
for (i=0; i<SL_LENGTH; i=i+1) begin:sl_data_sync_gen
aib_bitsync i_sl_data_sync
(
.clk(sr_sl_clk_out),
.rst_n(reset_n_sync),
.data_in(sl_data_fr_core[i]),
.data_out(sl_data_sync[i])
);
end
endgenerate
always @(posedge sr_sl_clk_out or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
sl_count[6:0] <= 7'h0;
sl_load <= 1'b0;
sl_shift_en <= 1'b0;
end
else
begin
if (sl_count[6:0]==(SL_LENGTH))
begin
sl_count[6:0] <= 7'h0;
sl_load <= 1'b1;
sl_shift_en <= 1'b0;
end
else
begin // increment counter
sl_count[6:0] <= sl_count[6:0] + 7'h01;
sl_load <= 1'b0;
sl_shift_en <= 1'b1;
end
end
end
assign sr_sl_data_outw = sl_data_syncr[SL_LENGTH-1];
assign sr_sl_load_outw = sl_load;
assign sl_data_syncrw[SL_LENGTH-1:0] = sl_load ? sl_data_sync[SL_LENGTH-1:0] :
sl_shift_en ? {sl_data_syncr[SL_LENGTH-2:0], sl_data_syncr[0]} : sl_data_syncr[SL_LENGTH-1:0];
always @(negedge sr_sl_clk_out or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
sr_sl_data_out <= 1'b0;
sr_sl_load_out <= 1'b0;
end
else
begin
sr_sl_data_out <= sr_sl_data_outw;
sr_sl_load_out <= sr_sl_load_outw;
end
end
always @(posedge sr_sl_clk_out or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
sl_data_syncr[SL_LENGTH-1:0] <= 73'h0;
end
else
begin
sl_data_syncr[SL_LENGTH-1:0] <= sl_data_syncrw[SL_LENGTH-1:0];
end
end
assign sl_data_revrw[SL_LENGTH-1:0] = sr_sl_load_in ? sl_data_revr[SL_LENGTH-1:0] : {sl_data_revr[SL_LENGTH-2:0], sr_sl_data_in};
assign sl_data_caprw[SL_LENGTH-1:0] = sr_sl_load_in ? sl_data_revr[SL_LENGTH-1:0] : sl_data_capr[SL_LENGTH-1:0];
always @(posedge sr_sl_clk_in or negedge reset_n_sync_rev) begin
if (~reset_n_sync_rev)
begin
sl_data_revr[SL_LENGTH-1:0] <= 73'h0;
sl_data_capr[SL_LENGTH-1:0] <= 73'h0;
end
else
begin
sl_data_revr[SL_LENGTH-1:0] <= sl_data_revrw[SL_LENGTH-1:0];
sl_data_capr[SL_LENGTH-1:0] <= sl_data_caprw[SL_LENGTH-1:0];
end
end
assign is_master = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
endmodule // aib_sr_sl |
module aib_redundancy ( //input of input mux
idata0_in1, idata0_in0, idata1_in1, idata1_in0,
idataselb_in1, idataselb_in0, iddren_in1, iddren_in0,
irxen_in1, irxen_in0, itxen_in1, itxen_in0, async_dat_in1, async_dat_in0,
//Output of input mux
idata0_out, idata1_out, idataselb_out, iddren_out,
irxen_out, itxen_out, async_dat_out,
//input of output mux
odat0_in1, odat0_in0, odat1_in1, odat1_in0, odat_async_in1, odat_async_in0,
//Output of output mux
odat0_out, odat1_out, odat_async_out,
//Mux selection signal
shift_en
);
//Mux selection signal
input shift_en;
//input of input mux
input idata0_in1, idata0_in0;
input idata1_in1, idata1_in0;
input idataselb_in1, idataselb_in0;
input iddren_in1, iddren_in0;
input [2:0] irxen_in1, irxen_in0;
input itxen_in1, itxen_in0;
input async_dat_in1, async_dat_in0;
//output of input mux
output idata0_out;
output idata1_out;
output idataselb_out;
output iddren_out;
output [2:0] irxen_out;
output itxen_out;
output async_dat_out;
//input of output mux
input odat0_in1, odat0_in0;
input odat1_in1, odat1_in0;
input odat_async_in1, odat_async_in0;
//output of output mux
output odat0_out;
output odat1_out;
output odat_async_out;
// Buses in the design
//input mux
assign idata0_out = shift_en? idata0_in1 : idata0_in0;
assign idata1_out = shift_en? idata1_in1 : idata1_in0;
assign idataselb_out = shift_en? idataselb_in1 : idataselb_in0 ;
assign iddren_out = shift_en? iddren_in1 : iddren_in0;
assign irxen_out[2] = shift_en? irxen_in1[2] : irxen_in0[2];
assign irxen_out[1] = shift_en? irxen_in1[1] : irxen_in0[1];
assign irxen_out[0] = shift_en? irxen_in1[0] : irxen_in0[0];
assign itxen_out = shift_en? itxen_in1 : itxen_in0;
//Change to CKMUX
//assign async_dat_out = shift_en? async_dat_in1 : async_dat_in0;
aib_mux21 async_dat_out_ckmux (
.mux_in0 (async_dat_in0),
.mux_in1 (async_dat_in1),
.mux_sel (shift_en),
.mux_out (async_dat_out)
);
//output mux
assign odat0_out = shift_en? odat0_in1 : odat0_in0;
assign odat1_out = shift_en? odat1_in1 : odat1_in0;
//Change to CKMUX
//assign odat_async_out = shift_en? odat_async_in1 : odat_async_in0;
aib_mux21 odat_async_out_ckmux (
.mux_in0 (odat_async_in0),
.mux_in1 (odat_async_in1),
.mux_sel (shift_en),
.mux_out (odat_async_out)
);
endmodule |
module aib_bitsync
#(
parameter DWIDTH = 1'b1, // Sync Data input
parameter RESET_VAL = 1'b0 // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
// End users may pass in RESET_VAL with a width exceeding 1 bit
// Evaluate the value first and use 1 bit value
localparam RESET_VAL_1B = (RESET_VAL == 'd0) ? 1'b0 : 1'b1;
reg [DWIDTH-1:0] dff2;
reg [DWIDTH-1:0] dff1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dff2 <= {DWIDTH{RESET_VAL_1B}};
dff1 <= {DWIDTH{RESET_VAL_1B}};
end
else begin
dff2 <= dff1;
dff1 <= data_in;
end
assign data_out = dff2;
endmodule // aib_bitsync |
module aib_sr_ms #(
parameter MS_LENGTH = 7'd81
)
(
// AIB IO Bidirectional
input osc_clk, //free running osc clock
input [MS_LENGTH-1:0] ms_data_fr_core,
output wire [MS_LENGTH-1:0] ms_data_to_core,
output reg sr_ms_data_out, //master serial data out
output reg sr_ms_load_out, //master load out
input sr_ms_data_in, //master serial data out
input sr_ms_load_in, //master serial data load inupt
input sr_ms_clk_in, //from input por
input ms_nsl,
input atpg_mode,
input reset_n
);
reg [6:0] ms_count;
reg ms_load;
reg [MS_LENGTH-1:0] ms_data_syncr; //master shift output register
reg [MS_LENGTH-1:0] ms_data_revr; //shift receive register
reg [MS_LENGTH-1:0] ms_data_capr; //captured master serial data register
reg ms_shift_en;
wire [MS_LENGTH-1:0] ms_data_sync, ms_data_syncrw, ms_data_revrw, ms_data_caprw;
wire reset_n_sync, reset_n_sync_rev;
wire sr_ms_data_outw; //master serial data out
wire sr_ms_load_outw; //master load out
assign ms_data_to_core[MS_LENGTH-1:0] = ms_data_capr[MS_LENGTH-1:0];
aib_rstnsync aib_rstnsync
(
.clk(osc_clk), // Destination clock of reset to be synced
.i_rst_n(reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync) // Synchronized reset output
);
aib_rstnsync aib_rstnsync_rev
(
.clk(sr_ms_clk_in), // Destination clock of reset to be synced
.i_rst_n(reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync_rev) // Synchronized reset output
);
genvar i;
generate
for (i=0; i<MS_LENGTH; i=i+1) begin:ms_data_sync_gen
aib_bitsync i_ms_data_sync
(
.clk(osc_clk),
.rst_n(reset_n_sync),
.data_in(ms_data_fr_core[i]),
.data_out(ms_data_sync[i])
);
end
endgenerate
always @(negedge osc_clk or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
sr_ms_data_out <= 1'b0;
sr_ms_load_out <= 1'b0;
end
else
begin
sr_ms_data_out <= sr_ms_data_outw;
sr_ms_load_out <= sr_ms_load_outw;
end
end
always @(posedge osc_clk or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
ms_count[6:0] <= 7'h0;
ms_load <= 1'b0;
ms_shift_en <= 1'b0;
end
else
begin
if (ms_count[6:0]==(MS_LENGTH))
begin
ms_count[6:0] <= 7'h0;
ms_load <= 1'b1;
ms_shift_en <= 1'b0;
end
else
begin // increment counter
ms_count[6:0] <= ms_count[6:0] + 7'h01;
ms_load <= 1'b0;
ms_shift_en <= 1'b1;
end
end
end
assign sr_ms_data_outw = ms_data_syncr[MS_LENGTH-1];
assign sr_ms_load_outw = ms_load;
assign ms_data_syncrw[MS_LENGTH-1:0] = ms_load ? ms_data_sync[MS_LENGTH-1:0] :
ms_shift_en ? {ms_data_syncr[MS_LENGTH-2:0], ms_data_syncr[0]} : ms_data_syncr[MS_LENGTH-1:0];
always @(posedge osc_clk or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
ms_data_syncr[MS_LENGTH-1:0] <= 81'h0;
end
else
begin
ms_data_syncr[MS_LENGTH-1:0] <= ms_data_syncrw[MS_LENGTH-1:0];
end
end
assign ms_data_revrw[MS_LENGTH-1:0] = sr_ms_load_in ? ms_data_revr[MS_LENGTH-1:0] : {ms_data_revr[MS_LENGTH-2:0], sr_ms_data_in};
assign ms_data_caprw[MS_LENGTH-1:0] = sr_ms_load_in ? ms_data_revr[MS_LENGTH-1:0] : ms_data_capr[MS_LENGTH-1:0];
always @(posedge sr_ms_clk_in or negedge reset_n_sync_rev) begin
if (~reset_n_sync_rev)
begin
ms_data_revr[MS_LENGTH-1:0] <= 81'h0;
ms_data_capr[MS_LENGTH-1:0] <= 81'h0;
end
else
begin
ms_data_revr[MS_LENGTH-1:0] <= ms_data_revrw[MS_LENGTH-1:0];
ms_data_capr[MS_LENGTH-1:0] <= ms_data_caprw[MS_LENGTH-1:0];
end
end
assign is_master = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
endmodule // aib_sr_ms |
module aib_jtag_bscan (
input odat0_aib, //sync data0 RX from AIB
input odat1_aib, //sync data1 RX from AIB
input odat_asyn_aib, //async data RX from AIB
input oclkp_aib, //diff clk RX from AIB
input oclkn_aib, //diff clk RX from AIB
input itxen_adap, //OE TX from HSSI Adapter
input idat0_adap, //SDR dat0 TX from HSSI Adapter
input idat1_adap, //SDR dat1 TX from HSSI Adapter
input async_data_adap, //async data TX from HSSI Adapter
input jtag_tx_scanen_in, //JTAG shift DR, active high
input jtag_clkdr_in, //JTAG boundary scan clock
input jtag_tx_scan_in, //JTAG TX data scan in
input jtag_mode_in, //JTAG mode select
input dig_rstb_adap, //IRSTB from Adaptor
input jtag_rstb_en, //reset_en from TAP
input jtag_rstb, //reset signal from TAP
input jtag_intest, //intest from TAP
input [2:0] irxen_adap, //RXEN from adapter
output jtag_clkdr_out, //CLKDR to remaining BSR
output jtag_rx_scan_out, //JTAG TX scan chain output
output odat0_adap, //sync data0 RX to HSSI Adapter
output odat1_adap, //sync data1 RX to HSSI Adapter
output odat_asyn_adap, //async data RX to HSSI Adapter
output itxen_aib, //OE TX to AIB
output idat0_aib, //SDR dat0 TX to AIB
output idat1_aib, //SDR dat1 TX to AIB
output async_data_aib, //async data TX to AIB
output dig_rstb_aib, //irstb to AIB
output [2:0] irxen_aib, //RXEN to AIB
output jtag_clkdr_outn //inverted clkdr for sync DDR TX
);
reg [6:0] tx_reg;
reg [4:0] rx_reg;
reg rx_nreg;
wire [6:0] tx_shift;
wire [6:0] tx_intst;
wire [4:0] rx_shift;
assign jtag_rx_scan_out = rx_nreg;
assign idat0_aib = (jtag_mode_in)? tx_reg[6] : idat0_adap;
assign idat1_aib = (jtag_mode_in)? tx_reg[5] : idat1_adap;
//Change this to CKMUX
//assign async_data_aib = (jtag_mode_in)? tx_reg[4] : async_data_adap;
aib_mux21 async_data_aib_ckmux (
.mux_in0(async_data_adap),
.mux_in1(tx_reg[4]),
.mux_sel(jtag_mode_in),
.mux_out(async_data_aib)
);
assign itxen_aib = (jtag_mode_in)? tx_reg[3] : itxen_adap;
assign irxen_aib[2] = (jtag_mode_in)? tx_reg[2] : irxen_adap[2];
assign irxen_aib[1] = (jtag_mode_in)? tx_reg[1] : irxen_adap[1];
assign irxen_aib[0] = (jtag_mode_in)? tx_reg[0] : irxen_adap[0];
assign odat0_adap = (jtag_intest)? rx_reg[4] : odat0_aib;
assign odat1_adap = (jtag_intest)? rx_reg[3] : odat1_aib;
//Change this to CKMUX
//assign odat_asyn_adap = (jtag_intest)? rx_reg[0] : odat_asyn_aib;
aib_mux21 odat_asyn_adap_ckmux (
.mux_in0(odat_asyn_aib),
.mux_in1(rx_reg[0]),
.mux_sel(jtag_intest),
.mux_out(odat_asyn_adap)
);
assign dig_rstb_aib = (jtag_rstb_en)? jtag_rstb : dig_rstb_adap;
assign jtag_clkdr_out = jtag_clkdr_in;
assign jtag_clkdr_outn = ~jtag_clkdr_in;
//May need to change to ckinv
/**
c3lib_ckinv_ctn jtag_clkdr_ckinv (
.in(jtag_clkdr_in),
.out(jtag_clkdr_outn)
);
**/
// Change async_data_adap mux to CKMUX
//assign tx_shift = (jtag_tx_scanen_in) ? {jtag_tx_scan_in,tx_reg[6:1]} : tx_intst;
assign tx_shift[6:5] = (jtag_tx_scanen_in) ? {jtag_tx_scan_in,tx_reg[6]} : tx_intst[6:5];
assign tx_shift[3:0] = (jtag_tx_scanen_in) ? {tx_reg[4:1]} : tx_intst[3:0];
aib_mux21 tx_shift_4_ckmux (
.mux_in0(tx_intst[4]),
.mux_in1(tx_reg[5]),
.mux_sel(jtag_tx_scanen_in),
.mux_out(tx_shift[4])
);
// Change async_data_adap mux to CKMUX
assign tx_intst[6:5] = (jtag_intest) ? {idat0_adap,idat1_adap} : tx_reg[6:5];
assign tx_intst[3:0] = (jtag_intest) ? {itxen_adap,irxen_adap[2],irxen_adap[1],irxen_adap[0]} : tx_reg[3:0];
aib_mux21 tx_intst_4_ckmux (
.mux_in0(tx_reg[4]),
.mux_in1(async_data_adap),
.mux_sel(jtag_intest),
.mux_out(tx_intst[4])
);
always @( posedge jtag_clkdr_in )
begin
tx_reg <= tx_shift;
end
//Change oclkn_aib, oclkp_aib and odat_asyn_adap to ckmux
assign rx_shift[4:3] = (jtag_tx_scanen_in) ? {tx_reg[0],rx_reg[4]} : {odat0_adap,odat1_adap};
aib_mux21 rx_shift_2_ckmux (
.mux_in0(oclkn_aib),
.mux_in1(rx_reg[3]),
.mux_sel(jtag_tx_scanen_in),
.mux_out(rx_shift[2])
);
aib_mux21 rx_shift_1_ckmux (
.mux_in0(oclkp_aib),
.mux_in1(rx_reg[2]),
.mux_sel(jtag_tx_scanen_in),
.mux_out(rx_shift[1])
);
aib_mux21 rx_shift_0_ckmux (
.mux_in0(odat_asyn_adap),
.mux_in1(rx_reg[1]),
.mux_sel(jtag_tx_scanen_in),
.mux_out(rx_shift[0])
);
always @( posedge jtag_clkdr_in )
begin
rx_reg <= rx_shift;
end
always @ ( negedge jtag_clkdr_in )
begin
rx_nreg <= rx_reg[0];
end
endmodule |
module aib_aux_channel
(
// AIB IO Bidirectional
inout wire iopad_dev_dect,
inout wire iopad_dev_dectrdcy,
inout wire iopad_dev_por,
inout wire iopad_dev_porrdcy,
input m_por_ovrd, //Master onlhy input, it overrides the por signal. For slave, it is tied to "0"
input m_device_detect_ovrd, //Slave only input, it overrides the device_detect signal. For Master, it is tied to "0"
output wire por_ms,
output wire m_device_detect,
input por_sl,
output wire osc_clk,
input ms_nsl, //"1", this is a Master. "0", this is a Slave
input irstb // Output buffer tri-state enable
);
aib_aliasd aliaspor ( .sig_red(iopad_dev_porrdcy), .sig_in(iopad_dev_por));
aib_aliasd aliasdet ( .sig_red(iopad_dev_dectrdcy), .sig_in(iopad_dev_dect));
wire device_detect_oe;
wire device_detect_ie;
wire por_oe;
wire por_ie;
wire device_detect_sl_main;
wire por_ms_main;
assign m_device_detect = device_detect_sl_main | m_device_detect_ovrd;
assign por_ms = por_ms_main & m_por_ovrd;
assign device_detect_oe = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign device_detect_ie = !device_detect_oe;
assign por_oe = (ms_nsl == 1'b1) ? 1'b0 : 1'b1;
assign por_ie = !por_oe;
aib_io_buffer u_device_detect
(
// Tx Path
.ilaunch_clk (1'b0),
.irstb (irstb),
.idat0 (1'b1),
.idat1 (1'b1),
.async_data (1'b1),
.oclkn (),
// Rx Path
.iclkn (1'b0),
.inclk (1'b0),
.inclk_dist (1'b0),
.oclk (),
.oclk_b (),
.odat0 (),
.odat1 (),
.odat_async (device_detect_sl_main),
// Bidirectional Data
.io_pad (iopad_dev_dect),
// I/O configuration
.async (1'b1),
.ddren (1'b0),
.txen (device_detect_oe),
.rxen (device_detect_ie),
.weaken (device_detect_ie),
.weakdir (1'b0)
);
aib_io_buffer u_device_por
(
// Tx Path
.ilaunch_clk (1'b0),
.irstb (irstb),
.idat0 (por_sl),
.idat1 (por_sl),
.async_data (por_sl),
.oclkn (),
// Rx Path
.iclkn (1'b0),
.inclk (1'b0),
.inclk_dist (1'b0),
.oclk (),
.oclk_b (),
.odat0 (),
.odat1 (),
.odat_async (por_ms_main),
// Bidirectional Data
.io_pad (iopad_dev_por),
// I/O configuration
.async (1'b1),
.ddren (1'b0),
.txen (por_oe),
.rxen (por_ie),
.weaken (por_ie),
.weakdir (1'b1)
);
aib_osc_clk aib_osc_clk
(.osc_clk(osc_clk)
);
endmodule // aib_aux_channel |
module aib_aliasd( sig_in, sig_red );
output sig_red;
input sig_in;
assign sig_red = sig_in;
endmodule |
module aib_sm
(
input osc_clk, //from aux
input sr_ms_clk_in, //input ms clock
input ms_config_done, //master config done
output reg ms_osc_transfer_en,
output reg ms_rx_transfer_en,
output reg ms_osc_transfer_alive,
output reg ms_rx_async_rst,
output reg ms_rx_dll_lock_req,
output reg ms_rx_dll_lock,
output reg ms_tx_async_rst,
output reg ms_tx_dcc_cal_req,
output reg ms_tx_dcc_cal_done,
output reg ms_tx_transfer_en,
input ms_rx_dcc_dll_lock_req,
input ms_tx_dcc_dll_lock_req,
input ms_rx_dll_lockint,
input ms_tx_dcc_cal_doneint,
input ms_tx_dcc_cal_donei,
input ms_rx_dll_locki,
input ms_rx_transfer_eni,
input ms_tx_transfer_eni,
input ms_osc_transfer_eni,
input sl_config_done, //slave config done
output reg sl_osc_transfer_en,
output reg sl_rx_transfer_en,
output reg sl_fifo_tx_async_rst,
output reg sl_tx_dcc_cal_req,
output reg sl_tx_dcc_cal_done,
output reg sl_tx_transfer_en,
output reg sl_rx_async_rst,
output reg sl_rx_dll_lock_req,
output reg sl_rx_dll_lock,
input sl_tx_dcc_dll_lock_req,
input sl_rx_dcc_dll_lock_req,
input sl_rx_dll_lockint, //from slave internal
input sl_rx_dll_locki, //from sr interface
input sl_tx_dcc_cal_donei, //from sr interface
input sl_tx_dcc_cal_doneint, //from slave internal
input sl_rx_transfer_eni,
input sl_osc_transfer_eni,
input ms_nsl, //"1", this is a Master. "0", this is a Slave
input atpg_mode,
input reset_n //ms_adapter_rstn & sl_adapter_rstn
);
parameter ms_wait_rx_osc_rdy = 2'd0, //osc sync states
ms_osc_xfer_en = 2'd1,
ms_osc_xfer_alive = 2'd2,
sl_wait_rx_osc_rdy = 2'd0,
sl_osc_xfer_en = 2'd1,
ms_wait_rx_xfer_req = 3'd0, //slave tx to master rx cal states
ms_wait_remt_tx_dcc_cal_done = 3'd1,
ms_send_ms_rx_dll_lock_req = 3'd2,
ms_rx_dll_lock_st = 3'd3,
ms_rx_xfer_en = 3'd4,
sl_wait_tx_xfer_req = 3'd0,
sl_send_tx_dcc_cal_req = 3'd1,
sl_wait_remt_rx_dll_lock = 3'd2,
sl_wait_remt_rx_transfer_en = 3'd3,
sl_tx_xfer_en = 3'd4,
ms_wait_tx_xfer_req = 3'd0, //master tx to slave rx cal states
ms_send_tx_dcc_cal_req = 3'd1,
ms_wait_remt_rx_dll_lock = 3'd2,
ms_wait_remt_rx_transfer_en = 3'd3,
ms_tx_xfer_en = 3'd4,
sl_wait_rx_xfer_req = 3'd0,
sl_send_rx_dll_lock_req = 3'd1,
sl_rx_dll_lock_st = 3'd2,
sl_rx_xfer_en = 3'd3,
sl_rx_xfer_alive = 3'd4;
reg [1:0] msosc_curst, msosc_nxst;
reg [1:0] slosc_curst, slosc_nxst;
reg [2:0] msrxcal_curst, msrxcal_nxst;
reg [2:0] sltxcal_curst, sltxcal_nxst;
reg [2:0] mstxcal_curst, mstxcal_nxst;
reg [2:0] slrxcal_curst, slrxcal_nxst;
wire is_master, is_slave;
wire ms_reset_n, sl_reset_n;
wire ms_reset_n_sync, sl_reset_n_sync;
wire ms_config_done_sync;
wire ms_rx_dcc_dll_lock_req_sync, ms_rx_dll_lock_sync;
wire ms_tx_dcc_dll_lock_req_sync;
wire sl_rx_dcc_dll_lock_req_sync, sl_rx_transfer_en_sync;
wire sl_tx_dcc_cal_reqw;
wire sl_osc_transfer_en_sync, sl_config_done_sync;
wire sl_tx_dcc_dll_lock_req_sync, sl_tx_dcc_cal_done_slsync;
wire ms_osc_transfer_en_sync, ms_rx_transfer_en_sync, ms_tx_transfer_en_sync;
wire ms_osc_transfer_enw, ms_osc_transfer_alivew, ms_rx_async_rstw;
wire ms_rx_dll_lock_reqw, ms_rx_dll_lockw;
wire ms_rx_transfer_enw, ms_tx_dcc_cal_reqw, ms_tx_dcc_cal_donew;
wire ms_tx_async_rstw, ms_tx_transfer_enw;
wire sl_osc_transfer_enw, sl_fifo_tx_async_rstw;
wire sl_tx_dcc_cal_donew, sl_tx_transfer_enw;
wire sl_rx_async_rstw, sl_rx_dll_lock_reqw, sl_rx_dll_lockw;
wire sl_rx_transfer_enw;
assign ms_reset_n = reset_n & ms_config_done;
assign sl_reset_n = reset_n & sl_config_done;
aib_rstnsync ms_aib_rstnsync
(
.clk(osc_clk), // Destination clock of reset to be synced
.i_rst_n(ms_reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(ms_reset_n_sync) // Synchronized reset output
);
aib_rstnsync ms_confdone_rstnsync
(
.clk(osc_clk), // Destination clock of reset to be synced
.i_rst_n(ms_config_done), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(ms_config_done_sync) // Synchronized reset output
);
aib_rstnsync sl_aib_rstnsync
(
.clk(sr_ms_clk_in), // Destination clock of reset to be synced
.i_rst_n(sl_reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(sl_reset_n_sync) // Synchronized reset output
);
aib_rstnsync sl_confdone_rstnsync
(
.clk(sr_ms_clk_in), // Destination clock of reset to be synced
.i_rst_n(sl_config_done), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(sl_config_done_sync) // Synchronized reset output
);
aib_bitsync i_sloscxferen_sync
(
.clk(osc_clk),
.rst_n(ms_config_done_sync),
.data_in(sl_osc_transfer_eni),
.data_out(sl_osc_transfer_en_sync)
);
aib_bitsync i_sltxdlldcclockreq_sync
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(sl_tx_dcc_dll_lock_req),
.data_out(sl_tx_dcc_dll_lock_req_sync)
);
aib_bitsync i_msrxdlldcclockreq
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(ms_rx_dcc_dll_lock_req),
.data_out(ms_rx_dcc_dll_lock_req_sync)
);
aib_bitsync i_msrxdlllock
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(ms_rx_dll_lockint),
.data_out(ms_rx_dll_lock_sync)
);
aib_bitsync i_sltxdcccaldone
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(sl_tx_dcc_cal_donei),
.data_out(sl_tx_dcc_cal_done_sync)
);
aib_bitsync i_slrxdlldcclockreq
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(sl_rx_dcc_dll_lock_req),
.data_out(sl_rx_dcc_dll_lock_req_sync)
);
aib_bitsync i_mstxdlldcclockreq
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(ms_tx_dcc_dll_lock_req),
.data_out(ms_tx_dcc_dll_lock_req_sync)
);
aib_bitsync i_mstxdcccaldone
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(ms_tx_dcc_cal_doneint),
.data_out(ms_tx_dcc_cal_done_sync)
);
aib_bitsync i_slrxdlllock
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(sl_rx_dll_locki),
.data_out(sl_rx_dll_lock_sync)
);
aib_bitsync i_slrxtranseren
(
.clk(osc_clk),
.rst_n(ms_reset_n_sync),
.data_in(sl_rx_transfer_eni),
.data_out(sl_rx_transfer_en_sync)
);
aib_bitsync i_msoscxferen_sync
(
.clk(sr_ms_clk_in),
.rst_n(sl_config_done_sync),
.data_in(ms_osc_transfer_eni),
.data_out(ms_osc_transfer_en_sync)
);
aib_bitsync i_slsltxdcccaldone
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(sl_tx_dcc_cal_doneint),
.data_out(sl_tx_dcc_cal_done_slsync)
);
aib_bitsync i_slmsrxdlllock
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(ms_rx_dll_locki),
.data_out(ms_rx_dll_lock_slsync)
);
aib_bitsync i_msrxtransferen
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(ms_rx_transfer_eni),
.data_out(ms_rx_transfer_en_sync)
);
aib_bitsync i_slmstxdcccaldone
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(ms_tx_dcc_cal_donei),
.data_out(ms_tx_dcc_cal_done_slsync)
);
aib_bitsync i_slslrxdlllock
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(sl_rx_dll_lockint),
.data_out(sl_rx_dll_lock_slsync)
);
aib_bitsync i_mstxtransferen
(
.clk(sr_ms_clk_in),
.rst_n(sl_reset_n_sync),
.data_in(ms_tx_transfer_eni),
.data_out(ms_tx_transfer_en_sync)
);
assign is_master = (ms_nsl == 1'b1) ? 1'b1 : 1'b0;
assign is_slave = !is_master;
assign ms_osc_transfer_enw = (msosc_curst[1:0]== ms_osc_xfer_en) ? 1'b1 :
(msosc_curst[1:0]== ms_wait_rx_osc_rdy) ? 1'b0 : ms_osc_transfer_en;
assign ms_osc_transfer_alivew = (msosc_curst[1:0]== ms_osc_xfer_alive) ? 1'b1 :
(msosc_curst[1:0]== ms_wait_rx_osc_rdy) ? 1'b0 : ms_osc_transfer_alive;
assign ms_rx_async_rstw = (msrxcal_curst[2:0] != ms_wait_rx_xfer_req) ? 1'b1 :
(msrxcal_curst[2:0] == ms_wait_rx_xfer_req) ? 1'b0 : ms_rx_async_rst;
assign ms_rx_dll_lock_reqw = (msrxcal_curst[2:0] == ms_send_ms_rx_dll_lock_req) ? 1'b1 :
(msrxcal_curst[2:0] == ms_wait_rx_xfer_req) ? 1'b0 : ms_rx_dll_lock_req;
assign ms_rx_dll_lockw = (msrxcal_curst[2:0] == ms_rx_dll_lock_st) ? 1'b1 :
(msrxcal_curst[2:0] == ms_wait_rx_xfer_req) ? 1'b0 : ms_rx_dll_lock;
assign ms_rx_transfer_enw = (msrxcal_curst[2:0] == ms_rx_xfer_en) ? 1'b1 :
(msrxcal_curst[2:0] == ms_wait_rx_xfer_req) ? 1'b0 : ms_rx_transfer_en;
assign ms_tx_async_rstw = (mstxcal_curst[2:0] != ms_wait_tx_xfer_req) ? 1'b1 :
(mstxcal_curst[2:0] == ms_wait_tx_xfer_req) ? 1'b0 : ms_tx_async_rst;
assign ms_tx_dcc_cal_reqw = (mstxcal_curst[2:0] == ms_send_tx_dcc_cal_req) ? 1'b1 :
(mstxcal_curst[2:0] == ms_wait_tx_xfer_req) ? 1'b0 : ms_tx_dcc_cal_req;
assign ms_tx_dcc_cal_donew = (mstxcal_curst[2:0] == ms_wait_remt_rx_dll_lock) ? 1'b1 :
(mstxcal_curst[2:0] == ms_wait_tx_xfer_req) ? 1'b0 : ms_tx_dcc_cal_done;
assign ms_tx_transfer_enw = (mstxcal_curst[2:0] == ms_tx_xfer_en) ? 1'b1 :
(mstxcal_curst[2:0] == ms_wait_tx_xfer_req) ? 1'b0 : ms_tx_transfer_en;
assign sl_osc_transfer_enw = (slosc_curst[1:0]== sl_osc_xfer_en) ? 1'b1 :
(slosc_curst[1:0]== sl_wait_rx_osc_rdy) ? 1'b0 : sl_osc_transfer_en;
assign sl_fifo_tx_async_rstw = (sltxcal_curst[2:0] != sl_wait_tx_xfer_req) ? 1'b1 :
(sltxcal_curst[2:0] == sl_wait_tx_xfer_req) ? 1'b0 : sl_fifo_tx_async_rst;
assign sl_tx_dcc_cal_reqw = (sltxcal_curst[2:0] == sl_send_tx_dcc_cal_req) ? 1'b1 :
(sltxcal_curst[2:0] == sl_wait_tx_xfer_req) ? 1'b0 : sl_tx_dcc_cal_req;
assign sl_tx_dcc_cal_donew = (sltxcal_curst[2:0] == sl_wait_remt_rx_dll_lock) ? 1'b1 :
(sltxcal_curst[2:0] == sl_wait_tx_xfer_req) ? 1'b0 : sl_tx_dcc_cal_done;
assign sl_tx_transfer_enw = (sltxcal_curst[2:0] == sl_tx_xfer_en) ? 1'b1 :
(sltxcal_curst[2:0] == sl_wait_tx_xfer_req) ? 1'b0 : sl_tx_transfer_en;
assign sl_rx_async_rstw = (slrxcal_curst[2:0] != sl_wait_rx_xfer_req) ? 1'b1 :
(slrxcal_curst[2:0] == sl_wait_rx_xfer_req) ? 1'b0 : sl_rx_async_rst;
assign sl_rx_dll_lock_reqw = (slrxcal_curst[2:0] == sl_send_rx_dll_lock_req) ? 1'b1 :
(slrxcal_curst[2:0] == sl_wait_rx_xfer_req) ? 1'b0 : sl_rx_dll_lock_req;
assign sl_rx_dll_lockw = (slrxcal_curst[2:0] == sl_rx_dll_lock_st) ? 1'b1 :
(slrxcal_curst[2:0] == sl_wait_rx_xfer_req) ? 1'b0 : sl_rx_dll_lock;
assign sl_rx_transfer_enw = (slrxcal_curst[2:0] == sl_rx_xfer_en) ? 1'b1 :
(slrxcal_curst[2:0] == sl_wait_rx_xfer_req) ? 1'b0 : sl_rx_transfer_en;
always @ (posedge osc_clk or negedge ms_reset_n_sync)
begin
if(!ms_reset_n_sync)
begin
ms_rx_async_rst <= 1'b0;
ms_rx_dll_lock_req <= 1'b0;
ms_rx_dll_lock <= 1'b0;
ms_rx_transfer_en <= 1'b0;
ms_tx_async_rst <= 1'b0;
ms_tx_dcc_cal_req <= 1'b0;
ms_tx_dcc_cal_done <= 1'b0;
ms_tx_transfer_en <= 1'b0;
end
else
begin
ms_rx_async_rst <= ms_rx_async_rstw;
ms_rx_dll_lock_req <= ms_rx_dll_lock_reqw;
ms_rx_dll_lock <= ms_rx_dll_lockw;
ms_rx_transfer_en <= ms_rx_transfer_enw;
ms_tx_async_rst <= ms_tx_async_rstw;
ms_tx_dcc_cal_req <= ms_tx_dcc_cal_reqw;
ms_tx_dcc_cal_done <= ms_tx_dcc_cal_donew;
ms_tx_transfer_en <= ms_tx_transfer_enw;
end
end
always @ (posedge sr_ms_clk_in or negedge sl_reset_n_sync)
begin
if(!sl_reset_n_sync)
begin
sl_tx_dcc_cal_done <= 1'b0;
sl_tx_dcc_cal_req <= 1'b0;
sl_tx_transfer_en <= 1'b0;
sl_rx_async_rst <= 1'b0;
sl_rx_dll_lock_req <= 1'b0;
sl_rx_dll_lock <= 1'b0;
sl_rx_transfer_en <= 1'b0;
end
else
begin
sl_tx_dcc_cal_done <= sl_tx_dcc_cal_donew;
sl_tx_dcc_cal_req <= sl_tx_dcc_cal_reqw;
sl_tx_transfer_en <= sl_tx_transfer_enw;
sl_rx_async_rst <= sl_rx_async_rstw;
sl_rx_dll_lock_req <= sl_rx_dll_lock_reqw;
sl_rx_dll_lock <= sl_rx_dll_lockw;
sl_rx_transfer_en <= sl_rx_transfer_enw;
end
end
//Master oscillator sync. sequence
always @ (posedge osc_clk or negedge ms_config_done_sync)
begin
if(!ms_config_done_sync)
begin
msosc_curst[1:0] <= 2'b0;
ms_osc_transfer_en <= 1'b0;
ms_osc_transfer_alive <= 1'b0;
end
else
begin
msosc_curst[1:0] <= msosc_nxst[1:0];
ms_osc_transfer_en <= ms_osc_transfer_enw;
ms_osc_transfer_alive <= ms_osc_transfer_alivew;
end
end
always @(*)
begin
case (msosc_curst)
ms_wait_rx_osc_rdy: begin
if (is_master )
msosc_nxst = ms_osc_xfer_en;
else
msosc_nxst = ms_wait_rx_osc_rdy;
end
ms_osc_xfer_en: begin
if (sl_osc_transfer_en_sync)
msosc_nxst = ms_osc_xfer_alive;
else
msosc_nxst = ms_osc_xfer_en;
end
ms_osc_xfer_alive: begin
msosc_nxst = ms_osc_xfer_alive;
end
default: begin
msosc_nxst = ms_wait_rx_osc_rdy;
end
endcase
end
//Slave oscillator sync. sequence
always @ (posedge sr_ms_clk_in or negedge sl_config_done_sync)
begin
if(!sl_config_done_sync)
begin
slosc_curst[1:0] <= 2'b0;
sl_osc_transfer_en <= 1'b0;
end
else
begin
slosc_curst[1:0] <= slosc_nxst[1:0];
sl_osc_transfer_en <= sl_osc_transfer_enw;
end
end
always @(*)
begin
case (slosc_curst)
sl_wait_rx_osc_rdy: begin
if (is_slave & ms_osc_transfer_en_sync)
slosc_nxst = sl_osc_xfer_en;
else
slosc_nxst = sl_wait_rx_osc_rdy;
end
sl_osc_xfer_en: begin
slosc_nxst = sl_osc_xfer_en;
end
default: begin
slosc_nxst = sl_wait_rx_osc_rdy;
end
endcase
end
//Slave_TX to Master_RX calibration sequence
always @ (posedge osc_clk or negedge ms_reset_n_sync)
begin
if(!ms_reset_n_sync)
begin
msrxcal_curst[2:0] <= 3'b0;
end
else
begin
msrxcal_curst[2:0] <= msrxcal_nxst[2:0];
end
end
always @(*)
begin
case (msrxcal_curst)
ms_wait_rx_xfer_req: begin
if (is_master & ms_osc_transfer_alive & (sl_tx_dcc_dll_lock_req_sync | ms_rx_dcc_dll_lock_req_sync))
msrxcal_nxst = ms_wait_remt_tx_dcc_cal_done;
else
msrxcal_nxst = ms_wait_rx_xfer_req;
end
ms_wait_remt_tx_dcc_cal_done: begin
if (!ms_rx_dcc_dll_lock_req_sync | !sl_tx_dcc_dll_lock_req_sync)
msrxcal_nxst = ms_wait_rx_xfer_req;
else if (sl_tx_dcc_cal_done_sync )
msrxcal_nxst = ms_send_ms_rx_dll_lock_req;
else
msrxcal_nxst = ms_wait_remt_tx_dcc_cal_done;
end
ms_send_ms_rx_dll_lock_req: begin
if (!ms_rx_dcc_dll_lock_req_sync | !sl_tx_dcc_dll_lock_req_sync)
msrxcal_nxst = ms_wait_rx_xfer_req;
else if (ms_rx_dll_lock_sync )
msrxcal_nxst = ms_rx_dll_lock_st;
else
msrxcal_nxst = ms_send_ms_rx_dll_lock_req;
end
ms_rx_dll_lock_st: begin
if (!ms_rx_dcc_dll_lock_req_sync | !sl_tx_dcc_dll_lock_req_sync)
msrxcal_nxst = ms_wait_rx_xfer_req;
else
msrxcal_nxst = ms_rx_xfer_en;
end
ms_rx_xfer_en: begin
if (~(sl_tx_dcc_dll_lock_req_sync & ms_rx_dcc_dll_lock_req_sync ))
msrxcal_nxst = ms_wait_rx_xfer_req;
else
msrxcal_nxst = ms_rx_xfer_en;
end
default: begin
msrxcal_nxst = ms_wait_rx_xfer_req;
end
endcase
end
always @ (posedge sr_ms_clk_in or negedge sl_reset_n_sync)
begin
if(!sl_reset_n_sync)
begin
sltxcal_curst[2:0] <= 3'b0;
end
else
begin
sltxcal_curst[2:0] <= sltxcal_nxst[2:0];
end
end
always @(*)
begin
case (sltxcal_curst)
sl_wait_tx_xfer_req: begin
if (is_slave & sl_osc_transfer_en & ~sl_tx_dcc_cal_done)
sltxcal_nxst = sl_send_tx_dcc_cal_req;
else
sltxcal_nxst = sl_wait_tx_xfer_req;
end
sl_send_tx_dcc_cal_req: begin
if (sl_tx_dcc_cal_done_slsync)
sltxcal_nxst = sl_wait_remt_rx_dll_lock;
else
sltxcal_nxst = sl_send_tx_dcc_cal_req;
end
sl_wait_remt_rx_dll_lock: begin
if (ms_rx_dll_lock_slsync)
sltxcal_nxst = sl_wait_remt_rx_transfer_en;
else
sltxcal_nxst = sl_wait_remt_rx_dll_lock;
end
sl_wait_remt_rx_transfer_en: begin
if (ms_rx_transfer_en_sync)
sltxcal_nxst = sl_tx_xfer_en;
else
sltxcal_nxst = sl_wait_remt_rx_transfer_en;
end
sl_tx_xfer_en: begin
if (~ms_rx_transfer_en_sync) //??? clarify, fig6-5
sltxcal_nxst = sl_wait_tx_xfer_req;
else
sltxcal_nxst = sl_tx_xfer_en;
end
default: begin
sltxcal_nxst = sl_wait_tx_xfer_req;
end
endcase
end
//Master_TX to Slave_RX calibration sequence
always @ (posedge osc_clk or negedge ms_reset_n_sync)
begin
if(!ms_reset_n_sync)
begin
mstxcal_curst[2:0] <= 3'b0;
end
else
begin
mstxcal_curst[2:0] <= mstxcal_nxst[2:0];
end
end
always @(*)
begin
case (mstxcal_curst)
ms_wait_tx_xfer_req: begin
if (is_master & ms_osc_transfer_alive & (sl_rx_dcc_dll_lock_req_sync & ms_tx_dcc_dll_lock_req_sync))
mstxcal_nxst = ms_send_tx_dcc_cal_req;
else
mstxcal_nxst = ms_wait_tx_xfer_req;
end
ms_send_tx_dcc_cal_req: begin
if (!ms_tx_dcc_dll_lock_req_sync | !sl_rx_dcc_dll_lock_req_sync )
mstxcal_nxst = ms_wait_tx_xfer_req;
else if (ms_tx_dcc_cal_done_sync )
mstxcal_nxst = ms_wait_remt_rx_dll_lock;
else
mstxcal_nxst = ms_send_tx_dcc_cal_req;
end
ms_wait_remt_rx_dll_lock: begin
if (!ms_tx_dcc_dll_lock_req_sync | !sl_rx_dcc_dll_lock_req_sync )
mstxcal_nxst = ms_wait_tx_xfer_req;
else if (sl_rx_dll_lock_sync )
mstxcal_nxst = ms_wait_remt_rx_transfer_en;
else
mstxcal_nxst = ms_wait_remt_rx_dll_lock;
end
ms_wait_remt_rx_transfer_en: begin
if (!ms_tx_dcc_dll_lock_req_sync | !sl_rx_dcc_dll_lock_req_sync )
mstxcal_nxst = ms_wait_tx_xfer_req;
else if (sl_rx_transfer_en_sync )
mstxcal_nxst = ms_tx_xfer_en;
else
mstxcal_nxst = ms_wait_remt_rx_transfer_en;
end
ms_tx_xfer_en: begin
if (~(sl_rx_dcc_dll_lock_req_sync & ms_tx_dcc_dll_lock_req_sync) )
mstxcal_nxst = ms_wait_tx_xfer_req;
else
mstxcal_nxst = ms_tx_xfer_en;
end
default: begin
mstxcal_nxst = ms_wait_tx_xfer_req;
end
endcase
end
always @ (posedge sr_ms_clk_in or negedge sl_reset_n_sync)
begin
if(!sl_reset_n_sync)
begin
slrxcal_curst[2:0] <= 3'b0;
end
else
begin
slrxcal_curst[2:0] <= slrxcal_nxst[2:0];
end
end
always @(*)
begin
case (slrxcal_curst)
sl_wait_rx_xfer_req: begin
if (is_slave & sl_osc_transfer_en & ms_tx_dcc_cal_done_slsync & ~sl_rx_dll_lock)
slrxcal_nxst = sl_send_rx_dll_lock_req;
else
slrxcal_nxst = sl_wait_rx_xfer_req;
end
sl_send_rx_dll_lock_req: begin
if (sl_rx_dll_lock_slsync)
slrxcal_nxst = sl_rx_dll_lock_st;
else
slrxcal_nxst = sl_send_rx_dll_lock_req;
end
sl_rx_dll_lock_st: begin
slrxcal_nxst = sl_rx_xfer_en;
end
sl_rx_xfer_en: begin
if (ms_tx_transfer_en_sync)
slrxcal_nxst = sl_rx_xfer_alive;
else
slrxcal_nxst = sl_rx_xfer_en;
end
sl_rx_xfer_alive: begin
if (~ms_tx_transfer_en_sync)
slrxcal_nxst = sl_wait_rx_xfer_req;
else
slrxcal_nxst = sl_rx_xfer_alive;
end
default: begin
slrxcal_nxst = sl_wait_rx_xfer_req;
end
endcase
end
endmodule // aib_sm |
module aib #(
parameter DATAWIDTH = 20
)
(
inout wire [DATAWIDTH-1:0] iopad_tx,
inout wire [DATAWIDTH-1:0] iopad_rx,
inout wire iopad_ns_rcv_clkb,
inout wire iopad_ns_rcv_clk,
inout wire iopad_ns_fwd_clk,
inout wire iopad_ns_fwd_clkb,
inout wire iopad_ns_sr_clk,
inout wire iopad_ns_sr_clkb,
inout wire iopad_ns_sr_load,
inout wire iopad_ns_sr_data,
inout wire iopad_ns_mac_rdy,
inout wire iopad_ns_adapter_rstn,
inout wire iopad_spare1, //iopad_spareo
inout wire iopad_spare0,
inout wire iopad_fs_rcv_clkb,
inout wire iopad_fs_rcv_clk,
inout wire iopad_fs_fwd_clkb,
inout wire iopad_fs_fwd_clk,
inout wire iopad_fs_sr_clkb,
inout wire iopad_fs_sr_clk,
inout wire iopad_fs_sr_load,
inout wire iopad_fs_sr_data,
inout wire iopad_fs_mac_rdy,
inout wire iopad_fs_adapter_rstn,
inout wire iopad_device_detect,
inout wire iopad_device_detect_copy,
inout wire iopad_por,
inout wire iopad_por_copy,
input [DATAWIDTH*2 - 1 :0] data_in, //output data to pad
output wire [DATAWIDTH*2 - 1:0] data_out, //input data from pad
input m_ns_fwd_clk, //output data clock
output wire m_fs_rcv_clk,
output wire m_fs_fwd_clk,
input m_ns_rcv_clk,
input ms_ns_adapter_rstn,
input sl_ns_adapter_rstn,
input ms_ns_mac_rdy,
input sl_ns_mac_rdy,
output wire fs_mac_rdy,
input ms_config_done,
input ms_rx_dcc_dll_lock_req,
input ms_tx_dcc_dll_lock_req,
input sl_config_done,
input sl_tx_dcc_dll_lock_req,
input sl_rx_dcc_dll_lock_req,
output wire ms_tx_transfer_en,
output wire ms_rx_transfer_en,
output wire sl_tx_transfer_en,
output wire sl_rx_transfer_en,
output wire [80:0] sr_ms_tomac,
output wire [72:0] sr_sl_tomac,
input ms_nsl,
input iddren,
input idataselb, //output async data selection
input itxen, //data tx enable
input [2:0] irxen,//data input enable
//Aux channel
//input ms_device_detect,
input m_por_ovrd,
input m_device_detect_ovrd,
input m_power_on_reset_i,
output wire m_device_detect,
output wire m_power_on_reset,
//JTAG signals
input jtag_clkdr_in,
output wire scan_out,
input jtag_intest,
input jtag_mode_in,
input jtag_rstb,
input jtag_rstb_en,
input jtag_weakpdn,
input jtag_weakpu,
input jtag_tx_scanen_in,
input scan_in,
//Redundancy control signals for IO buffers
`include "redundancy_ctrl.vh"
input [26:0] sl_external_cntl_26_0, //user defined bits 26:0 for slave shift register
input [2:0] sl_external_cntl_30_28, //user defined bits 30:28 for slave shift register
input [25:0] sl_external_cntl_57_32, //user defined bits 57:32 for slave shift register
input [4:0] ms_external_cntl_4_0, //user defined bits 4:0 for master shift register
input [57:0] ms_external_cntl_65_8, //user defined bits 65:8 for master shift register
input vccl_aib,
input vssl_aib );
wire por_ms, osc_clk;
assign m_power_on_reset = por_ms;
aib_channel #(.DATAWIDTH(DATAWIDTH)) aib_channel
(
.iopad_txdat(iopad_tx),
.iopad_rxdat(iopad_rx),
.iopad_txclkb(iopad_ns_rcv_clkb),
.iopad_txclk(iopad_ns_rcv_clk),
.iopad_txfck(iopad_ns_fwd_clk),
.iopad_txfckb(iopad_ns_fwd_clkb),
.iopad_stck(iopad_ns_sr_clk),
.iopad_stckb(iopad_ns_sr_clkb),
.iopad_stl(iopad_ns_sr_load),
.iopad_std(iopad_ns_sr_data),
.iopad_rstno(iopad_ns_mac_rdy),
.iopad_arstno(iopad_ns_adapter_rstn),
.iopad_spareo(iopad_spare1),
.iopad_sparee(iopad_spare0),
.iopad_rxclkb(iopad_fs_rcv_clkb),
.iopad_rxclk(iopad_fs_rcv_clk),
.iopad_rxfckb(iopad_fs_fwd_clkb),
.iopad_rxfck(iopad_fs_fwd_clk),
.iopad_srckb(iopad_fs_sr_clkb),
.iopad_srck(iopad_fs_sr_clk),
.iopad_srl(iopad_fs_sr_load),
.iopad_srd(iopad_fs_sr_data),
.iopad_rstni(iopad_fs_mac_rdy),
.iopad_arstni(iopad_fs_adapter_rstn),
.tx_launch_clk(m_ns_fwd_clk), //output data clock
.fs_rvc_clk_tomac(m_fs_rcv_clk),
.fs_fwd_clk_tomac(m_fs_fwd_clk),
.ns_rvc_clk_frmac(m_ns_rcv_clk),
.iddren(iddren),
.idataselb(idataselb), //output async data selection
.itxen(itxen), //data tx enable
.irxen(irxen),//data input enable
.idat0(data_in[DATAWIDTH-1:0]), //output data to pad
.idat1(data_in[DATAWIDTH *2 -1 : DATAWIDTH]), //output data to pad
.data_out0(data_out[DATAWIDTH-1:0]), //input data from pad
.data_out1(data_out[DATAWIDTH *2 -1 : DATAWIDTH]), //input data from pad
.ms_config_done(ms_config_done),
.ms_rx_dcc_dll_lock_req(ms_rx_dcc_dll_lock_req),
.ms_tx_dcc_dll_lock_req(ms_tx_dcc_dll_lock_req),
.sl_config_done(sl_config_done),
.sl_tx_dcc_dll_lock_req(sl_tx_dcc_dll_lock_req),
.sl_rx_dcc_dll_lock_req(sl_rx_dcc_dll_lock_req),
.ms_tx_transfer_en(ms_tx_transfer_en),
.ms_rx_transfer_en(ms_rx_transfer_en),
.sl_tx_transfer_en(sl_tx_transfer_en),
.sl_rx_transfer_en(sl_rx_transfer_en),
.sr_ms_tomac(sr_ms_tomac[80:0]),
.sr_sl_tomac(sr_sl_tomac[72:0]),
.ms_adapter_rstn(ms_ns_adapter_rstn),
.sl_adapter_rstn(sl_ns_adapter_rstn),
.ms_rstn(ms_ns_mac_rdy),
.sl_rstn(sl_ns_mac_rdy),
.fs_mac_rdy_tomac(fs_mac_rdy),
.por_sl(m_power_on_reset_i),
.ms_nsl(ms_nsl),
.por_ms(por_ms),
.osc_clk(osc_clk),
//JTAG interface
.jtag_clkdr_in(jtag_clkdr_in),
.scan_out(scan_out),
.jtag_intest(jtag_intest),
.jtag_mode_in(jtag_mode_in),
.jtag_rstb(jtag_rstb),
.jtag_rstb_en(jtag_rstb_en),
.jtag_weakpdn(jtag_weakpdn),
.jtag_weakpu(jtag_weakpu),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.scan_in(scan_in),
.tx_shift_en(shift_en_tx), //tx red. shift enable
.rx_shift_en(shift_en_rx), //rx red. shift enable
.shift_en_txclkb(shift_en_txclkb),
.shift_en_txfckb(shift_en_txfckb),
.shift_en_stckb(shift_en_stckb),
.shift_en_stl(shift_en_stl),
.shift_en_arstno(shift_en_arstno),
.shift_en_txclk(shift_en_txclk),
.shift_en_std(shift_en_std),
.shift_en_stck(shift_en_stck),
.shift_en_txfck(shift_en_txfck),
.shift_en_rstno(shift_en_rstno),
.shift_en_rxclkb(shift_en_rxclkb),
.shift_en_rxfckb(shift_en_rxfckb),
.shift_en_srckb(shift_en_srckb),
.shift_en_srl(shift_en_srl),
.shift_en_arstni(shift_en_arstni),
.shift_en_rxclk(shift_en_rxclk),
.shift_en_rxfck(shift_en_rxfck),
.shift_en_srck(shift_en_srck),
.shift_en_srd(shift_en_srd),
.shift_en_rstni(shift_en_rstni),
.sl_external_cntl_26_0(sl_external_cntl_26_0[26:0]),
.sl_external_cntl_30_28(sl_external_cntl_30_28[2:0]),
.sl_external_cntl_57_32(sl_external_cntl_57_32[25:0]),
.ms_external_cntl_4_0(ms_external_cntl_4_0[4:0]),
.ms_external_cntl_65_8(ms_external_cntl_65_8[57:0]),
.vccl_aib(vccl_aib),
.vssl_aib(vssl_aib) );
aib_aux_channel aib_aux_channel
(
// AIB IO Bidirectional
.iopad_dev_dect(iopad_device_detect),
.iopad_dev_dectrdcy(iopad_device_detect_copy),
.iopad_dev_por(iopad_por),
.iopad_dev_porrdcy(iopad_por_copy),
// .device_detect_ms(ms_device_detect),
.m_por_ovrd(m_por_ovrd),
.m_device_detect_ovrd(m_device_detect_ovrd),
.por_ms(por_ms),
.m_device_detect(m_device_detect),
.por_sl(m_power_on_reset_i),
.osc_clk(osc_clk),
.ms_nsl(ms_nsl),
.irstb(1'b1) // Output buffer tri-state enable
);
endmodule // aib |
module aib_rstnsync
(
input wire clk, // Destination clock of reset to be synced
input wire i_rst_n, // Asynchronous reset input
input wire scan_mode, // Scan bypass for reset
output wire sync_rst_n // Synchronized reset output
);
reg first_stg_rst_n;
wire prescan_sync_rst_n;
always @(posedge clk or negedge i_rst_n)
if (!i_rst_n)
first_stg_rst_n <= 1'b0;
else
first_stg_rst_n <= 1'b1;
aib_bitsync
#(.DWIDTH(1), .RESET_VAL(0) )
i_sync_rst_n
(
.clk (clk ),
.rst_n (i_rst_n ),
.data_in (first_stg_rst_n ),
.data_out (prescan_sync_rst_n)
);
assign sync_rst_n = scan_mode ? i_rst_n : prescan_sync_rst_n;
endmodule |
module aib_mux21
(
input wire mux_in0, // mux in 0
input wire mux_in1, // mux in 1
input wire mux_sel, // mux selector
output wire mux_out // mux out
);
assign mux_out = mux_sel ? mux_in1 : mux_in0;
endmodule |
module aib_bsr_red_wrap ( async_data_out,
dig_rstb_aib, idata0_out, idata1_out,
idataselb_out, iddren_out,
irxen_out,
itxen_out, jtag_clkdr_out, jtag_rx_scan_out,
odat0_out, odat1_out,
odat_async_out,
async_dat_in0, async_dat_in1, dig_rstb_adap,
idata0_in0, idata0_in1, idata1_in0, idata1_in1,
idataselb_in0, idataselb_in1, iddren_in0, iddren_in1,
irxen_in0, irxen_in1,
itxen_in0, itxen_in1, jtag_clkdr_in,
jtag_mode_in, jtag_rstb_en, jtag_rstb,
jtag_tx_scan_in, jtag_tx_scanen_in,
oclk_in, oclkb_in,
odat0_in0, odat0_in1, odat1_in0, odat1_in1,
odat_async_in0, odat_async_in1,
shift_en, jtag_intest, jtag_clkdr_outn, idata0_red, idata1_red, async_dat_red
);
output async_data_out, dig_rstb_aib,
idata0_out, idata1_out, idataselb_out, iddren_out,
itxen_out,
jtag_clkdr_out, jtag_clkdr_outn, jtag_rx_scan_out,
odat0_out, odat1_out, odat_async_out;
input async_dat_in0, async_dat_in1, dig_rstb_adap,
idata0_in0, idata0_in1,
idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0,
iddren_in1,
itxen_in0, itxen_in1, jtag_clkdr_in,
jtag_mode_in, jtag_rstb_en, jtag_rstb,
jtag_tx_scan_in,
jtag_tx_scanen_in,
oclk_in, oclkb_in,
odat0_in0, odat0_in1,
odat1_in0, odat1_in1, odat_async_in0,
odat_async_in1, shift_en;
output [2:0] irxen_out;
output idata0_red;
output idata1_red;
output async_dat_red;
input [2:0] irxen_in0;
input [2:0] irxen_in1;
input jtag_intest;
wire [2:0] irxen_red;
wire odat0_red;
wire odat1_red;
wire odat_async_red;
wire itxen_red;
aib_redundancy xredundancy (
//input of input mux
.idata0_in1(idata0_in1),
.idata0_in0(idata0_red),
.idata1_in1(idata1_in1),
.idata1_in0(idata1_red),
.idataselb_in1(idataselb_in1),
.idataselb_in0(idataselb_in0),
.iddren_in1(iddren_in1),
.iddren_in0(iddren_in0),
.irxen_in1(irxen_in1),
.irxen_in0(irxen_red),
.itxen_in1(itxen_in1),
.itxen_in0(itxen_red),
.async_dat_in1(async_dat_in1),
.async_dat_in0(async_dat_red),
//Output of input mux
.idata0_out(idata0_out),
.idata1_out(idata1_out),
.idataselb_out(idataselb_out),
.iddren_out(iddren_out),
.irxen_out(irxen_out),
.itxen_out(itxen_out),
.async_dat_out(async_data_out),
//input of output mux
.odat0_in1(odat0_in1),
.odat0_in0(odat0_in0),
.odat1_in1(odat1_in1),
.odat1_in0(odat1_in0),
.odat_async_in1(odat_async_in1),
.odat_async_in0(odat_async_in0),
//Output of output mux
.odat0_out(odat0_red),
.odat1_out(odat1_red),
.odat_async_out(odat_async_red),
//Mux selection signal
.shift_en(shift_en)
);
aib_jtag_bscan xjtag(
.odat0_aib(odat0_red), //sync data0 RX from AIB
.odat1_aib(odat1_red), //sync data1 RX from AIB
.odat_asyn_aib(odat_async_red), //async data RX from AIB
.oclkp_aib(oclk_in), //diff clk RX from AIB
.oclkn_aib(oclkb_in), //diff clk RX from AIB
.itxen_adap(itxen_in0), //OE TX from HSSI Adapter
.idat0_adap(idata0_in0), //SDR dat0 TX from HSSI Adapter
.idat1_adap(idata1_in0), //SDR dat1 TX from HSSI Adapter
.async_data_adap(async_dat_in0), //async data TX from HSSI Adapter
.jtag_tx_scanen_in(jtag_tx_scanen_in), //JTAG shift DR, active high
.jtag_clkdr_in(jtag_clkdr_in), //JTAG boundary scan clock
.jtag_tx_scan_in(jtag_tx_scan_in), //JTAG TX data scan in
.jtag_mode_in(jtag_mode_in), //JTAG mode select
.dig_rstb_adap(dig_rstb_adap), //IRSTB from Adaptor
.jtag_rstb_en(jtag_rstb_en), //reset_en from TAP
.jtag_rstb(jtag_rstb), //reset signal from TAP
.jtag_intest(jtag_intest),
.irxen_adap(irxen_in0),
.jtag_clkdr_out(jtag_clkdr_out), //CLKDR to remaining BSR
.jtag_rx_scan_out(jtag_rx_scan_out), //JTAG TX scan chain output
.odat0_adap(odat0_out), //sync data0 RX to HSSI Adapter
.odat1_adap(odat1_out), //sync data1 RX to HSSI Adapter
.odat_asyn_adap(odat_async_out), //async data RX to HSSI Adapter
.itxen_aib(itxen_red), //OE TX to AIB
.idat0_aib(idata0_red), //SDR dat0 TX to AIB
.idat1_aib(idata1_red), //SDR dat1 TX to AIB
.async_data_aib(async_dat_red), //async data TX to AIB
.dig_rstb_aib(dig_rstb_aib), //irstb to AIB
.irxen_aib(irxen_red),
.jtag_clkdr_outn(jtag_clkdr_outn)
);
endmodule |
module aib_dcc
(
// AIB IO Bidirectional
input clk_in,
input ms_dcc_cal_req,
input ms_tx_dcc_dll_lock_req,
input sl_dcc_cal_req,
input sl_rx_dcc_dll_lock_req,
output wire ms_dcc_cal_done,
output wire sl_dcc_cal_done,
output wire clk_out,
input ms_nsl,
input atpg_mode,
input reset_n
);
reg ms_dcc_cal_done_r, sl_dcc_cal_done_r;
wire ms_dcc_cal_donew, sl_dcc_cal_donew;
wire ms_dcc_cal_req_sync, sl_dcc_cal_req_sync;
wire reset_n_sync;
assign clk_out = clk_in;
assign ms_dcc_cal_done = ms_dcc_cal_done_r;
assign sl_dcc_cal_done = sl_dcc_cal_done_r;
assign ms_dcc_cal_donew = !ms_tx_dcc_dll_lock_req ? 1'b0 :
(ms_nsl & ms_dcc_cal_req_sync ) ? 1'b1 : ms_dcc_cal_done_r;
assign sl_dcc_cal_donew = !sl_rx_dcc_dll_lock_req ? 1'b0 :
(!ms_nsl & sl_dcc_cal_req_sync ) ? 1'b1 : sl_dcc_cal_done_r;
aib_rstnsync aib_rstnsync
(
.clk(clk_in), // Destination clock of reset to be synced
.i_rst_n(reset_n), // Asynchronous reset input
.scan_mode(atpg_mode), // Scan bypass for reset
.sync_rst_n(reset_n_sync) // Synchronized reset output
);
aib_bitsync i_mstxdlldcclockreq
(
.clk(clk_in),
.rst_n(reset_n_sync),
.data_in(ms_dcc_cal_req),
.data_out(ms_dcc_cal_req_sync)
);
aib_bitsync i_sltxdlldcclockreq
(
.clk(clk_in),
.rst_n(reset_n_sync),
.data_in(sl_dcc_cal_req),
.data_out(sl_dcc_cal_req_sync)
);
always @(posedge clk_in or negedge reset_n_sync) begin
if (~reset_n_sync)
begin
ms_dcc_cal_done_r <= 1'b0;
sl_dcc_cal_done_r <= 1'b0;
end
else
begin
ms_dcc_cal_done_r <= ms_dcc_cal_donew;
sl_dcc_cal_done_r <= sl_dcc_cal_donew;
end
end
endmodule // aib_dcc |
module aib_buffx1_top ( async_dat_in1_jtag_out, idata0_in1_jtag_out,
idata1_in1_jtag_out, jtag_clkdr_outn,
jtag_rx_scan_out, oclk_aib, oclk_out, oclkb_aib,
oclkb_out, oclkn, odat0_aib, odat0_out, odat1_aib, odat1_out,
odat_async_aib, odat_async_out, iopad,
async_dat_in0, async_dat_in1,
dig_rstb, iclkin_dist_in0, iclkin_dist_in1, iclkn, idata0_in0,
idata0_in1, idata1_in0, idata1_in1, idataselb_in0, idataselb_in1,
iddren_in0, iddren_in1, ilaunch_clk_in0, ilaunch_clk_in1,
irxen_in0, irxen_in1,
istrbclk_in0, istrbclk_in1, itxen_in0, itxen_in1, jtag_clkdr_in,
jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scan_in, jtag_tx_scanen_in, oclk_in1,
oclkb_in1, odat0_in1, odat1_in1, odat_async_in1,
shift_en,
test_weakpd, test_weakpu );
output async_dat_in1_jtag_out, idata0_in1_jtag_out,
idata1_in1_jtag_out, jtag_clkdr_outn,
jtag_rx_scan_out, oclk_aib, oclk_out, oclkb_aib,
oclkb_out, oclkn, odat0_aib, odat0_out, odat1_aib, odat1_out,
odat_async_aib, odat_async_out;
input async_dat_in0, async_dat_in1, dig_rstb,
iclkin_dist_in0, iclkin_dist_in1, iclkn, idata0_in0, idata0_in1,
idata1_in0, idata1_in1, idataselb_in0, idataselb_in1, iddren_in0,
iddren_in1, ilaunch_clk_in0, ilaunch_clk_in1,
istrbclk_in0,
istrbclk_in1, itxen_in0, itxen_in1, jtag_clkdr_in,
jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scan_in, jtag_tx_scanen_in, oclk_in1,
oclkb_in1, odat0_in1, odat1_in1, odat_async_in1,
shift_en,
test_weakpd, test_weakpu;
inout iopad;
input [2:0] irxen_in1;
input [2:0] irxen_in0;
wire odat1_out, odat1_out_pnr, odat_async_out, odat_async_out_pnr, odat0_out, odat0_out_pnr;
// Buses in the design
wire [2:0] irxen_aib;
wire idat1_aib;
wire idat0_aib;
wire itxen_aib;
wire async_data_aib;
wire dig_rstb_aib;
wire idataselb_aib;
wire iddren_aib;
wire iclkin_dist_aib;
wire istrbclk_aib;
wire weak_drvr_en, weak_drvr_dir;
assign weak_drvr_en = test_weakpd | test_weakpu;
assign weak_drvr_dir = test_weakpu ? 1'b1 : 1'b0;
aib_bsr_red_wrap aib_bsr_red_wrap ( .async_dat_red(async_dat_in1_jtag_out),
.idata0_red(idata0_in1_jtag_out),
.idata1_red(idata1_in1_jtag_out),
.jtag_clkdr_outn(jtag_clkdr_outn), .idata1_out(idat1_aib),
.idata0_out(idat0_aib), .oclk_in(oclk_out), .oclkb_in(oclkb_out),
.itxen_out(itxen_aib), .async_data_out(async_data_aib),
.irxen_out(irxen_aib[2:0]), .jtag_intest(jtag_intest),
.jtag_rstb_en(jtag_rstb_en), .dig_rstb_aib(dig_rstb_aib),
.dig_rstb_adap(dig_rstb),
.odat_async_in0(odat_async_aib),
.odat1_in0(odat1_aib), .odat0_in0(odat0_aib), .shift_en(shift_en),
.idataselb_out(idataselb_aib),
.iddren_out(iddren_aib), .odat0_out(odat0_out_pnr),
.odat1_out(odat1_out_pnr), .odat_async_out(odat_async_out_pnr),
.async_dat_in0(async_dat_in0), .async_dat_in1(async_dat_in1),
.idata0_in0(idata0_in0), .idata0_in1(idata0_in1),
.idata1_in0(idata1_in0), .idata1_in1(idata1_in1),
.idataselb_in0(idataselb_in0), .idataselb_in1(idataselb_in1),
.iddren_in0(iddren_in0), .iddren_in1(iddren_in1),
.irxen_in0(irxen_in0[2:0]), .irxen_in1(irxen_in1[2:0]),
.itxen_in0(itxen_in0), .itxen_in1(itxen_in1),
.odat0_in1(odat0_in1), .odat1_in1(odat1_in1),
.odat_async_in1(odat_async_in1), .jtag_clkdr_out(),
.jtag_rx_scan_out(jtag_rx_scan_out),
.jtag_clkdr_in(jtag_clkdr_in), .jtag_mode_in(jtag_mode_in),
.jtag_rstb(jtag_rstb), .jtag_tx_scan_in(jtag_tx_scan_in),
.jtag_tx_scanen_in(jtag_tx_scanen_in));
aib_io_buffer aib_io_buffer
(
// Tx Path
.ilaunch_clk (ilaunch_clk_in0),
.irstb (dig_rstb_aib),
.idat0 (idat0_aib),
.idat1 (idat1_aib),
.async_data (async_data_aib),
.oclkn (oclkn),
// Rx Path
.iclkn (iclkn),
.inclk (istrbclk_in0),
.inclk_dist (iclkin_dist_in0),
.oclk (oclk_aib),
.oclk_b (oclkb_aib),
.odat0 (odat0_aib),
.odat1 (odat1_aib),
.odat_async (odat_async_aib),
// Bidirectional Data
.io_pad (iopad),
// I/O configuration
.async (idataselb_aib),
.ddren (iddren_aib),
.txen (itxen_aib),
.rxen (irxen_aib[0]),
.weaken (weak_drvr_en),
.weakdir (weak_drvr_dir)
);
assign odat1_out = odat1_out_pnr;
assign odat_async_out = odat_async_out_pnr;
assign odat0_out = odat0_out_pnr;
endmodule |
module dbg_test_jtagsm(
tck,
tms,
tdi,
tdo,
reset_n,
update_ir,
update_dr,
capture_dr,
shift_ir,
shift_dr,
test_logic_reset,
instruction,
state_shift_dr_p
);
parameter TOTAL_IR_SIZE = 15;
parameter EFF_IR_SIZE = 7;
input tck;
input tms;
input reset_n;
input tdi;
output tdo;
output update_ir;
output update_dr;
output capture_dr;
output shift_ir;
output shift_dr;
output test_logic_reset;
output [EFF_IR_SIZE-1:0] instruction;
output state_shift_dr_p;
reg [3:0] current_state;
reg [3:0] next_state;
reg [TOTAL_IR_SIZE-1:0] ir;
reg [EFF_IR_SIZE-1:0] instruction;
reg update_ir;
reg update_dr;
reg capture_dr;
reg shift_ir;
reg shift_dr;
reg test_logic_reset;
// TAP state machine
always @(posedge tck or negedge reset_n)
begin
if(reset_n == 1'b0)
current_state <= `CNT_DBG_TEST__TEST_LOGIC_RESET;
else
current_state <= next_state;
end
always @(tms or current_state)
begin
case(current_state)
`CNT_DBG_TEST__TEST_LOGIC_RESET:
begin
if(tms)
next_state = `CNT_DBG_TEST__TEST_LOGIC_RESET;
else
next_state = `CNT_DBG_TEST__RUN_TEST_IDLE;
end
`CNT_DBG_TEST__RUN_TEST_IDLE:
begin
if(tms)
next_state = `CNT_DBG_TEST__SELECT_DR_SCAN;
else
next_state = `CNT_DBG_TEST__RUN_TEST_IDLE;
end
`CNT_DBG_TEST__SELECT_DR_SCAN:
begin
if(tms)
next_state = `CNT_DBG_TEST__SELECT_IR_SCAN;
else
next_state = `CNT_DBG_TEST__CAPTURE_DR;
end
`CNT_DBG_TEST__CAPTURE_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT1_DR;
else
next_state = `CNT_DBG_TEST__SHIFT_DR;
end
`CNT_DBG_TEST__SHIFT_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT1_DR;
else
next_state = `CNT_DBG_TEST__SHIFT_DR;
end
`CNT_DBG_TEST__EXIT1_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__UPDATE_DR;
else
next_state = `CNT_DBG_TEST__PAUSE_DR;
end
`CNT_DBG_TEST__PAUSE_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT2_DR;
else
next_state = `CNT_DBG_TEST__PAUSE_DR;
end
`CNT_DBG_TEST__EXIT2_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__UPDATE_DR;
else
next_state = `CNT_DBG_TEST__SHIFT_DR;
end
`CNT_DBG_TEST__UPDATE_DR:
begin
if(tms)
next_state = `CNT_DBG_TEST__SELECT_DR_SCAN;
else
next_state = `CNT_DBG_TEST__RUN_TEST_IDLE;
end
`CNT_DBG_TEST__SELECT_IR_SCAN:
begin
if(tms)
next_state = `CNT_DBG_TEST__TEST_LOGIC_RESET;
else
next_state = `CNT_DBG_TEST__CAPTURE_IR;
end
`CNT_DBG_TEST__CAPTURE_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT1_IR;
else
next_state = `CNT_DBG_TEST__SHIFT_IR;
end
`CNT_DBG_TEST__SHIFT_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT1_IR;
else
next_state = `CNT_DBG_TEST__SHIFT_IR;
end
`CNT_DBG_TEST__EXIT1_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__UPDATE_IR;
else
next_state = `CNT_DBG_TEST__PAUSE_IR;
end
`CNT_DBG_TEST__PAUSE_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__EXIT2_IR;
else
next_state = `CNT_DBG_TEST__PAUSE_IR;
end
`CNT_DBG_TEST__EXIT2_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__UPDATE_IR;
else
next_state = `CNT_DBG_TEST__SHIFT_IR;
end
`CNT_DBG_TEST__UPDATE_IR:
begin
if(tms)
next_state = `CNT_DBG_TEST__SELECT_DR_SCAN;
else
next_state = `CNT_DBG_TEST__RUN_TEST_IDLE;
end
default:
next_state = `CNT_DBG_TEST__TEST_LOGIC_RESET;
endcase
end
always @(current_state)
begin
shift_ir = 1'b0;
shift_dr = 1'b0;
capture_dr = 1'b0;
update_ir = 1'b0;
update_dr = 1'b0;
test_logic_reset = 1'b0;
case(current_state)
`CNT_DBG_TEST__SHIFT_IR:
shift_ir = 1'b1;
`CNT_DBG_TEST__SHIFT_DR:
shift_dr = 1'b1;
`CNT_DBG_TEST__CAPTURE_DR:
capture_dr = 1'b1;
`CNT_DBG_TEST__UPDATE_IR:
update_ir = 1'b1;
`CNT_DBG_TEST__UPDATE_DR:
update_dr = 1'b1;
`CNT_DBG_TEST__TEST_LOGIC_RESET:
test_logic_reset = 1'b1;
endcase
end
// TAP IR
// SHIFT-IR operation
always @(posedge tck or negedge reset_n)
begin
if(reset_n == 1'b0)
ir <= {TOTAL_IR_SIZE{1'b0}};
else if(test_logic_reset == 1'b1)
ir <= {TOTAL_IR_SIZE{1'b0}};
else if(shift_ir)
ir <= {tdi,ir[TOTAL_IR_SIZE-1:1]};
end
assign tdo = ir[0];
// UPDATE-IR operation
always @(negedge tck or negedge reset_n)
begin
if(reset_n == 1'b0)
instruction <= {EFF_IR_SIZE{1'b0}};
else if(update_ir == 1'b1)
instruction <= ir[EFF_IR_SIZE-1:0];
end
assign state_shift_dr_p = (next_state == `CNT_DBG_TEST__SHIFT_DR) ? 1'b1: 1'b0;
endmodule |
module aibcr3aux_cnup_clktree ( strbclk0, strbclk1, strbclk2, strbclk3,
strbclk4, strbclk5, strbclk6, strbclk7, strbclk8, strbclk9,
strbclk10, strbclk11, strbclk12, strbclk13, strbclk14, strbclk15,
strbclk16, strbclk17, strbclk18, strbclk19, strbclk20, strbclk21,
strbclk22, strbclk23, strbclk24, strbclk25, clkin, clkinb,
csr_dly_ovrd, csr_dly_ovrden, ib50u_ring, ib50uc, iosc_fuse_trim,
vcc_aibcr3aux, vss_aibcr3aux );
output strbclk0, strbclk1, strbclk2, strbclk3, strbclk4, strbclk5,
strbclk6, strbclk7, strbclk8, strbclk9, strbclk10, strbclk11,
strbclk12, strbclk13, strbclk14, strbclk15, strbclk16, strbclk17,
strbclk18, strbclk19, strbclk20, strbclk21, strbclk22, strbclk23,
strbclk24, strbclk25;
input clkin, clkinb, csr_dly_ovrden, ib50u_ring, ib50uc, vcc_aibcr3aux,
vss_aibcr3aux;
input [3:0] csr_dly_ovrd;
input [9:0] iosc_fuse_trim;
wire clk25, net56;
wire clkout_r;
wire lvl0_out;
wire clkout_l;
wire net57;
wire net066;
wire clkb25;
assign clk25 = net56;
/*
aibcr3_clkbuf xbuf_lvl1_r ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(clkout_r), .in(lvl0_out));
aibcr3_clkbuf xbuf_lvl1_m ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(net56), .in(lvl0_out));
aibcr3_clkbuf xbuf_lvl1_l ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(clkout_l), .in(lvl0_out));
*/
assign clkout_r = lvl0_out;
assign net56 = lvl0_out;
assign clkout_l = lvl0_out;
aibcr3_aliasd aliasv1 ( .rb(strbclk0), .ra(clkout_l));
aibcr3_aliasd aliasv18 ( .rb(strbclk23), .ra(net56));
aibcr3_aliasd aliasv10 ( .rb(strbclk16), .ra(clkout_r));
aibcr3_aliasd aliasv13 ( .rb(strbclk19), .ra(clkout_r));
aibcr3_aliasd aliasv14 ( .rb(strbclk17), .ra(clkout_r));
aibcr3_aliasd aliasv11 ( .rb(strbclk18), .ra(clkout_r));
aibcr3_aliasd aliasv8 ( .rb(strbclk12), .ra(clkout_r));
aibcr3_aliasd aliasv15 ( .rb(strbclk15), .ra(clkout_r));
aibcr3_aliasd aliasv9 ( .rb(strbclk14), .ra(clkout_r));
aibcr3_aliasd aliasv16 ( .rb(strbclk13), .ra(clkout_r));
aibcr3_aliasd aliasv17 ( .rb(strbclk11), .ra(clkout_r));
aibcr3_aliasd aliasv7 ( .rb(strbclk10), .ra(clkout_r));
aibcr3_aliasd aliasv25 ( .rb(strbclk21), .ra(net56));
aibcr3_aliasd aliasv6 ( .rb(strbclk25), .ra(net57));
aibcr3_aliasd aliasv24 ( .rb(strbclk20), .ra(net56));
aibcr3_aliasd aliasv19 ( .rb(strbclk9), .ra(clkout_l));
aibcr3_aliasd aliasv4 ( .rb(strbclk6), .ra(clkout_l));
aibcr3_aliasd aliasv5 ( .rb(strbclk8), .ra(clkout_l));
aibcr3_aliasd aliasv20 ( .rb(strbclk7), .ra(clkout_l));
aibcr3_aliasd aliasv2 ( .rb(strbclk2), .ra(clkout_l));
aibcr3_aliasd aliasv21 ( .rb(strbclk5), .ra(clkout_l));
aibcr3_aliasd aliasv12 ( .rb(strbclk22), .ra(net56));
aibcr3_aliasd aliasv3 ( .rb(strbclk4), .ra(clkout_l));
aibcr3_aliasd aliasv0 ( .rb(strbclk24), .ra(net56));
aibcr3_aliasd aliasv23 ( .rb(strbclk1), .ra(clkout_l));
aibcr3_aliasd aliasv22 ( .rb(strbclk3), .ra(clkout_l));
assign net066 = clkin;
assign lvl0_out = net066;
//sa_buf01_ulvt x6 ( .vssesa(vss_aibcr3aux), .vccesa(vcc_aibcr3aux), .out(net066), .in(clkin));
//aibcr3_preclkbuf xbuf_lvl0 ( .vss_pl(vss_aibcr3aux),
// .vcc_pl(vcc_aibcr3aux), .out(lvl0_out), .in(net066));
aibcr3aux_outclkdly xoutclkdly ( .ib50uc(ib50uc),
.ib50u_ring(ib50u_ring), .clkinb(clkb25),
.csr_dly_ovrd(csr_dly_ovrd[3:0]), .csr_dly_ovrden(csr_dly_ovrden),
.vssl_aibcr3aux(vss_aibcr3aux), .clkin(clk25),
.vcc_aibcr3aux(vcc_aibcr3aux), .clkout(net57),
.iosc_fuse_trim(iosc_fuse_trim[9:0]));
assign clkb25 = !net56;
// sa_invg2_ulvt x8 ( .vssesa(vss_aibcr3aux), .vccesa(vcc_aibcr3aux), .out(clkb25), .in(net56));
endmodule |
module aibcr3aux_osc_divby8 ( out_divby2, out_divby4, out_divby8,
scan_out, vcc_aibcr3aux, vss_aibcr3aux, clkin, por, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n );
output out_divby2, out_divby4, out_divby8, scan_out;
inout vcc_aibcr3aux, vss_aibcr3aux;
input clkin, por, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
wire out_divby2, net119, net114, out_divby4, net118, net113, net117, net120, out_divby8;
wire so0;
wire so1;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_osc_divby8";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign out_divby2 = ~net119;
assign net119 = ~net114;
assign out_divby4 = ~net118;
assign net118 = ~net113;
assign net117 = ~net120;
assign out_divby8 = ~net117;
aibcr3aux_osc_div2_asyn_clr xdiv8_1 ( .scan_shift_n(scan_shift_n),
.scan_clk(scan_clk), .scan_out(so0), .scan_in(scan_in),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
.clkout(net114), .irstb(por), .clkin(clkin));
aibcr3aux_osc_div2_asyn_clr xdiv8_2 ( .scan_shift_n(scan_shift_n),
.scan_clk(scan_clk), .scan_out(so1), .scan_in(so0),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
.clkout(net113), .irstb(por), .clkin(net114));
aibcr3aux_osc_div2_asyn_clr xdiv8_3 ( .scan_shift_n(scan_shift_n),
.scan_clk(scan_clk), .scan_out(scan_out), .scan_in(so1),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
.clkout(net120), .irstb(por), .clkin(net113));
endmodule |
module aibcr3aux_osc_sync ( en_out, resetb_out, scan_out, vcc_aibcraux,
vss_aibcraux, clk, d, resetb, scan_clk, scan_in, scan_mode_n,
scan_rst_n, scan_shift_n );
output en_out, resetb_out, scan_out;
inout vcc_aibcraux, vss_aibcraux;
input clk, d, resetb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
wire scanmoden, scan_mode_n, scanrstn, scan_rst_n, scanclk, scan_clk, scanin, scan_in, scanshftn, scan_shift_n, resetb_out, net062, dff_clk, net036, net044, resetb, clk;
wire so0;
wire scanshft;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_sync";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign scanmoden = scan_mode_n;
assign scanrstn = scan_rst_n;
assign scanclk = scan_clk;
assign scanin = scan_in;
assign scanshftn = scan_shift_n;
assign scanshft = ~scan_shift_n;
assign resetb_out = scanmoden ? net062 : scanrstn;
assign dff_clk = scanmoden ? net036 : scanclk;
/*aibcr3aux_osc_ff xreset_sync ( .cdn(net044), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(net062), .so(so0), .cp(dff_clk), .d(vcc_aibcraux),
.se_n(scanshftn), .si(scanin));*/
assign net044 = scanmoden ? resetb : scanrstn;
/*aibcr3aux_osc_sync_ff x7 (
.CDN(resetb_out), .CP(dff_clk), .D(d), .Q(en_out),
.so(scan_out),
.se_n(scanshftn), .si(so0));*/
aibcr3_ulvt16_2xarstsyncdff1_b2 x99(.CLR_N(resetb_out), .CK(dff_clk), .D(d), .Q(en_out), .SE(scanshft), .SI(so0));
assign scan_out = en_out;
// reset synchronizer
aibcr3_ulvt16_2xarstsyncdff1_b2 x31(.CLR_N(net044),.CK(dff_clk), .D(vcc_aibcraux), .Q(net062), .SE(scanshft), .SI(scanin));
assign so0 = net062;
assign net036 = ~clk;
endmodule |
module aibcr3aux_osc_div2_asyn_clr ( clkout, scan_out, vcc_aibcraux,
vss_aibcraux, clkin, irstb, scan_clk, scan_in, scan_mode_n,
scan_rst_n, scan_shift_n );
output clkout, scan_out;
inout vcc_aibcraux, vss_aibcraux;
input clkin, irstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
wire net26, clkout, dff_clk, scan_modn, net019, clkin, dff_rstb, scan_rstn, irstb, scanshftn, scan_shift_n, scan_clk, scan_mode_n, scan_rst_n;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_osc_div2_asyn_clr";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net26 = ~clkout;
aibcr3aux_osc_ff x0 ( .cdn(dff_rstb), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(clkout), .so(scan_out), .cp(dff_clk), .d(net26),
.se_n(scanshftn), .si(scan_in));
assign dff_clk = scan_modn ? clkin : net019;
assign dff_rstb = scan_modn ? irstb : scan_rstn;
assign scanshftn = scan_shift_n;
assign net019 = scan_clk;
assign scan_modn = scan_mode_n;
assign scan_rstn = scan_rst_n;
endmodule |
module aibcr3aux_top_wrp ( jtag_clkdr_out, jtag_clksel_out,
jtag_intest_out, jtag_mode_out, jtag_rstb_en_out, jtag_rstb_out,
jtag_rx_scan_out, jtag_tx_scanen_out, jtag_weakpdn_out,
jtag_weakpu_out, last_bs_out, o_cnocdn, o_cnocdn_clkp, o_dn_por,
o_dn_rst_n, o_io_in, o_io_oe, o_jt_tck, o_jt_tdi, o_jt_tms,
o_por_vcchssi, o_por_vccl, o_por_vccl_1p8, oatpg_scan_out,
odft_in_async, oosc_aibdft2osc, oosc_atb0, oosc_atb1, oosc_clkout_dup, oosc_clkout,
oosc_monitor, oosc_reserved, aib_aux0, aib_aux1, aib_aux2,
aib_aux3, aib_aux4, aib_aux5, aib_aux6, aib_aux7, aib_aux8,
aib_aux9, aib_aux10, aib_aux11, aib_aux12, aib_aux13, aib_aux14,
aib_aux15, aib_aux16, aib_aux17, aib_aux18, aib_aux19, aib_aux20,
aib_aux21, aib_aux22, aib_aux23, aib_aux24, aib_aux25, aib_aux26,
aib_aux27, aib_aux28, aib_aux29, aib_aux30, aib_aux31, aib_aux32,
aib_aux33, aib_aux34, aib_aux35, aib_aux36, aib_aux37, aib_aux38,
aib_aux39, aib_aux40, aib_aux41, aib_aux42, aib_aux43, aib_aux44,
aib_aux45, aib_aux46, aib_aux47, aib_aux48, aib_aux49, aib_aux50,
aib_aux51, aib_aux52, aib_aux53, aib_aux54, aib_aux55, aib_aux56,
aib_aux57, aib_aux58, aib_aux59, aib_aux60, aib_aux61, aib_aux62,
aib_aux63, aib_aux64, aib_aux65, aib_aux66, aib_aux67, aib_aux68,
aib_aux69, aib_aux70, aib_aux71, aib_aux72, aib_aux73, aib_aux74,
aib_aux75, aib_aux76, aib_aux77, aib_aux78, aib_aux79, aib_aux80,
aib_aux81, aib_aux82, aib_aux83, aib_aux84, aib_aux85, aib_aux86,
aib_aux87, aib_aux88, aib_aux89, aib_aux90, aib_aux91, aib_aux92,
aib_aux93, aib_aux94, aib_aux95, aib_aux_ctrl_bus0,
aib_aux_ctrl_bus1, aib_aux_ctrl_bus2, c4por_vccl_ovrd, i_actred1,
i_actred2, i_cnocup, i_cnocup_clkp, i_io_out, i_jtr_tck,
i_jtr_tdo, i_jtr_tms, i_tstmx, iactred_txen1, iactred_txen2,
iaib_aibdll2dft, iatpg_mode_n, iatpg_pipeline_global_en,
iatpg_rst_n, iatpg_scan_clk, iatpg_scan_in, iatpg_scan_shift_n,
idft_bypass_en, idft_out_async, iosc_aibdft2osc, iosc_bypclk,
iosc_fuse_trim, iosc_ic50u, iosc_it50u, ired_idataselb_in_chain1,
ired_idataselb_in_chain2, ired_shift_en_in_chain1,
ired_shift_en_in_chain2, irstb, jtag_clkdr_in, jtag_clksel_in,
jtag_intest_in, jtag_mode_in, jtag_rstb_en_in, jtag_rstb_in,
jtag_tx_scan_in, jtag_tx_scanen_in, jtag_weakpdn_in,
jtag_weakpu_in, last_bs_in, osc_extrref); //vcc_aibcraux, vcca_aibcraux,
//vccl_aibcraux, vccr_aibcraux, vssl_aibcraux );
wire vcc_aibcraux, vcca_aibcraux, vccl_aibcraux, vccr_aibcraux, vssl_aibcraux;
output jtag_clkdr_out, jtag_clksel_out, jtag_intest_out,
jtag_mode_out, jtag_rstb_en_out, jtag_rstb_out, jtag_rx_scan_out,
jtag_tx_scanen_out, jtag_weakpdn_out, jtag_weakpu_out,
last_bs_out, o_cnocdn_clkp, o_dn_por, o_dn_rst_n, o_jt_tck,
o_jt_tdi, o_jt_tms, o_por_vcchssi, o_por_vccl, o_por_vccl_1p8,
oatpg_scan_out, oosc_atb0, oosc_atb1, oosc_clkout_dup, oosc_clkout, oosc_monitor;
inout aib_aux0, aib_aux1, aib_aux2, aib_aux3, aib_aux4, aib_aux5,
aib_aux6, aib_aux7, aib_aux8, aib_aux9, aib_aux10, aib_aux11,
aib_aux12, aib_aux13, aib_aux14, aib_aux15, aib_aux16, aib_aux17,
aib_aux18, aib_aux19, aib_aux20, aib_aux21, aib_aux22, aib_aux23,
aib_aux24, aib_aux25, aib_aux26, aib_aux27, aib_aux28, aib_aux29,
aib_aux30, aib_aux31, aib_aux32, aib_aux33, aib_aux34, aib_aux35,
aib_aux36, aib_aux37, aib_aux38, aib_aux39, aib_aux40, aib_aux41,
aib_aux42, aib_aux43, aib_aux44, aib_aux45, aib_aux46, aib_aux47,
aib_aux48, aib_aux49, aib_aux50, aib_aux51, aib_aux52, aib_aux53,
aib_aux54, aib_aux55, aib_aux56, aib_aux57, aib_aux58, aib_aux59,
aib_aux60, aib_aux61, aib_aux62, aib_aux63, aib_aux64, aib_aux65,
aib_aux66, aib_aux67, aib_aux68, aib_aux69, aib_aux70, aib_aux71,
aib_aux72, aib_aux73, aib_aux74, aib_aux75, aib_aux76, aib_aux77,
aib_aux78, aib_aux79, aib_aux80, aib_aux81, aib_aux82, aib_aux83,
aib_aux84, aib_aux85, aib_aux86, aib_aux87, aib_aux88, aib_aux89,
aib_aux90, aib_aux91, aib_aux92, aib_aux93, aib_aux94, aib_aux95;
inout osc_extrref;
input c4por_vccl_ovrd, i_actred1, i_actred2, i_cnocup_clkp, i_jtr_tck,
i_jtr_tdo, i_jtr_tms, iactred_txen1, iactred_txen2, iatpg_mode_n,
iatpg_pipeline_global_en, iatpg_rst_n, iatpg_scan_clk,
iatpg_scan_in, iatpg_scan_shift_n, idft_bypass_en, iosc_bypclk,
iosc_ic50u, iosc_it50u, ired_idataselb_in_chain1,
ired_idataselb_in_chain2, ired_shift_en_in_chain1,
ired_shift_en_in_chain2, irstb, jtag_clkdr_in, jtag_clksel_in,
jtag_intest_in, jtag_mode_in, jtag_rstb_en_in, jtag_rstb_in,
jtag_tx_scan_in, jtag_tx_scanen_in, jtag_weakpdn_in,
jtag_weakpu_in, last_bs_in; //vcc_aibcraux, vcca_aibcraux,
//vccl_aibcraux, vccr_aibcraux, vssl_aibcraux;
//
assign vcc_aibcraux = 1'b1;
assign vcca_aibcraux = 1'b1;
assign vccl_aibcraux = 1'b1;
assign vccr_aibcraux = 1'b1;
assign vssl_aibcraux =1'b0;
assign aib_aux24 =1'b0;
assign aib_aux89 =1'b0;
assign aib_aux91 =1'b0;
output [9:0] odft_in_async;
output [31:0] o_cnocdn;
output [7:0] o_io_in;
output [1:0] o_io_oe;
output [12:0] oosc_aibdft2osc;
output [3:0] oosc_reserved;
input [12:0] iaib_aibdll2dft;
input [31:0] aib_aux_ctrl_bus0;
input [31:0] aib_aux_ctrl_bus1;
input [31:0] aib_aux_ctrl_bus2;
input [49:0] i_cnocup;
input [7:0] i_io_out;
input [7:0] i_tstmx;
input [7:0] idft_out_async;
input [2:0] iosc_aibdft2osc;
input [9:0] iosc_fuse_trim;
/////////////////////////////////
// for VCS and ICC compatibility
/////////////////////////////////
`ifdef WREAL
real oosc_atb0, oosc_atb1;
`endif
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_top_wrp";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_top xaibcraux_top ( .vccr_aibcraux(vccr_aibcraux),
.iactred_shiften_chain2(ired_shift_en_in_chain2),
.iactred_shiften_chain1(ired_shift_en_in_chain1),
.jtag_rstb_en_in(jtag_rstb_en_in),
.jtag_rstb_en_out(jtag_rstb_en_out), .u_crdet_r(aib_aux75),
.u_crdet(aib_aux74), .iatpg_scan_shift_n(iatpg_scan_shift_n),
.oatpg_scan_out(oatpg_scan_out),
.odft_in_async(odft_in_async[9:0]), .iatpg_mode_n(iatpg_mode_n),
.iatpg_pipeline_global_en(iatpg_pipeline_global_en),
.iatpg_rst_n(iatpg_rst_n), .iatpg_scan_clk(iatpg_scan_clk),
.iatpg_scan_in(iatpg_scan_in), .idft_bypass_en(idft_bypass_en),
.o_jt_tck(o_jt_tck), .vssl_aibcr3aux(vssl_aibcraux),
.vccl_aibcr3aux(vccl_aibcraux), .vcca_aibcr3aux(vcca_aibcraux),
.vcc_aibcr3aux(vcc_aibcraux), .o_jt_tms(o_jt_tms),
.iaib_aibdll2dft(iaib_aibdll2dft[12:0]),
.jtag_clkdr_out(jtag_clkdr_out),
.jtag_clksel_out(jtag_clksel_out),
.jtag_intest_out(jtag_intest_out), .jtag_mode_out(jtag_mode_out),
.jtag_rstb_out(jtag_rstb_out),
.jtag_rx_scan_out(jtag_rx_scan_out),
.jtag_tx_scanen_out(jtag_tx_scanen_out),
.jtag_weakpdn_out(jtag_weakpdn_out),
.jtag_weakpu_out(jtag_weakpu_out), .last_bs_out(last_bs_out),
.o_cnocdn(o_cnocdn[31:0]), .o_cnocdn_clkp(o_cnocdn_clkp),
.o_dn_por(o_dn_por), .o_dn_rst_n(o_dn_rst_n),
.o_io_in(o_io_in[7:0]), .o_io_oe(o_io_oe[1:0]),
.o_jt_tdi(o_jt_tdi), .o_por_vcchssi(o_por_vcchssi),
.o_por_vccl(o_por_vccl), .o_por_vccl_1p8(o_por_vccl_1p8),
.oosc_aibdft2osc(oosc_aibdft2osc[12:0]), .oosc_atb0(oosc_atb0),
.oosc_atb1(oosc_atb1), .oosc_clkout_dup(oosc_clkout_dup), .oosc_clkout(oosc_clkout),
.oosc_monitor(oosc_monitor), .oosc_reserved(oosc_reserved[3:0]),
.u_actred1(aib_aux20), .u_actred2(aib_aux18),
.u_auxactred1(aib_aux94), .u_auxactred2(aib_aux93),
.u_cnocup({aib_aux26, aib_aux42, aib_aux44, aib_aux43, aib_aux41,
aib_aux16, aib_aux22, aib_aux23, aib_aux21, aib_aux14, aib_aux12,
aib_aux13, aib_aux15, aib_aux8, aib_aux10, aib_aux6, aib_aux4,
aib_aux5, aib_aux7, aib_aux0, aib_aux2, aib_aux3, aib_aux1,
aib_aux19, aib_aux17}), .u_cnocup_clkn(aib_aux11),
.u_cnocup_clkp(aib_aux9), .u_io_out({aib_aux65, aib_aux67,
aib_aux60, aib_aux62, aib_aux63, aib_aux61, aib_aux58,
aib_aux56}), .u_jtr_tck(aib_aux77), .u_jtr_tck_r(aib_aux76),
.u_jtr_tdo(aib_aux78), .u_jtr_tdo_r(aib_aux79),
.u_jtr_tms(aib_aux73), .u_jtr_tms_r(aib_aux72),
.u_tstmx({aib_aux95, aib_aux92, aib_aux68, aib_aux70, aib_aux71,
aib_aux69, aib_aux66, aib_aux64}),
.aib_aux_ctrl_bus0(aib_aux_ctrl_bus0[31:0]),
.aib_aux_ctrl_bus1(aib_aux_ctrl_bus1[31:0]),
.aib_aux_ctrl_bus2(aib_aux_ctrl_bus2[31:0]),
.c4por_vccl_ovrd(c4por_vccl_ovrd), .i_actred1(i_actred1),
.i_actred2(i_actred2), .i_cnocup(i_cnocup[49:0]),
.i_cnocup_clkp(i_cnocup_clkp), .i_io_out(i_io_out[7:0]),
.i_jtr_tck(i_jtr_tck), .i_jtr_tdo(i_jtr_tdo),
.i_jtr_tms(i_jtr_tms), .i_tstmx(i_tstmx[7:0]),
.iactred_txen(iactred_txen1),
.idft_out_async(idft_out_async[7:0]),
.iosc_aibdft2osc(iosc_aibdft2osc[2:0]), .iosc_bypclk(iosc_bypclk),
.iosc_fuse_trim(iosc_fuse_trim[9:0]), .iosc_ic50u(iosc_ic50u),
.iosc_it50u(iosc_it50u), .irstb(irstb),
.jtag_clkdr_in(jtag_clkdr_in), .jtag_clksel_in(jtag_clksel_in),
.jtag_intest_in(jtag_intest_in), .jtag_mode_in(jtag_mode_in),
.jtag_rstb_in(jtag_rstb_in), .jtag_tx_scan_in(jtag_tx_scan_in),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.jtag_weakpdn_in(jtag_weakpdn_in),
.jtag_weakpu_in(jtag_weakpu_in), .last_bs_in(last_bs_in),
.u_cnocdn({aib_aux47, aib_aux45, aib_aux40, aib_aux46, aib_aux37,
aib_aux39, aib_aux38, aib_aux36, aib_aux35, aib_aux33, aib_aux29,
aib_aux31, aib_aux30, aib_aux28, aib_aux27, aib_aux25}),
.u_cnocdn_clkn(aib_aux32), .u_cnocdn_clkp(aib_aux34),
.u_dn_por(aib_aux85), .u_dn_por_r(aib_aux87),
.u_dn_rst_n(aib_aux90), .u_dn_rst_n_r(aib_aux88),
.u_io_in({aib_aux52, aib_aux54, aib_aux55, aib_aux53, aib_aux50,
aib_aux48, aib_aux49, aib_aux51}), .u_io_oe({aib_aux57,
aib_aux59}), .u_jt_tck(aib_aux83), .u_jt_tck_r(aib_aux81),
.u_jt_tdi(aib_aux86), .u_jt_tdi_r(aib_aux84),
.u_jt_tms(aib_aux80), .u_jt_tms_r(aib_aux82), .osc_extrref(osc_extrref));
endmodule |
module aibcr3aux_cndn_clktree ( lstrbclk_l_0, lstrbclk_l_1,
lstrbclk_l_2, lstrbclk_l_3, lstrbclk_l_4, lstrbclk_l_5,
lstrbclk_l_6, lstrbclk_l_7, lstrbclk_l_8, lstrbclk_l_9,
lstrbclk_l_10, lstrbclk_l_11, lstrbclk_mimic0, lstrbclk_mimic1,
lstrbclk_mimic2, lstrbclk_r_0, lstrbclk_r_1, lstrbclk_r_2,
lstrbclk_r_3, lstrbclk_r_4, lstrbclk_r_5, lstrbclk_r_6,
lstrbclk_r_7, lstrbclk_r_8, lstrbclk_r_9, lstrbclk_r_10,
lstrbclk_r_11, lstrbclk_rep, clkin, clkinb, csr_dly_ovrd,
csr_dly_ovrden, ib50u_ring, ib50uc, iosc_fuse_trim, vcc_aibcr3aux,
vss_aibcr3aux );
output lstrbclk_l_0, lstrbclk_l_1, lstrbclk_l_2, lstrbclk_l_3,
lstrbclk_l_4, lstrbclk_l_5, lstrbclk_l_6, lstrbclk_l_7,
lstrbclk_l_8, lstrbclk_l_9, lstrbclk_l_10, lstrbclk_l_11,
lstrbclk_mimic0, lstrbclk_mimic1, lstrbclk_mimic2, lstrbclk_r_0,
lstrbclk_r_1, lstrbclk_r_2, lstrbclk_r_3, lstrbclk_r_4,
lstrbclk_r_5, lstrbclk_r_6, lstrbclk_r_7, lstrbclk_r_8,
lstrbclk_r_9, lstrbclk_r_10, lstrbclk_r_11, lstrbclk_rep;
input clkin, clkinb, csr_dly_ovrden, ib50u_ring, ib50uc, vcc_aibcr3aux,
vss_aibcr3aux;
input [9:0] iosc_fuse_trim;
input [3:0] csr_dly_ovrd;
wire clkint;
wire clkout_r;
wire lvl0_out;
wire clkout_l;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_cndn_clktree";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_inclkdly xinclkdly ( .ib50uc(ib50uc),
.ib50u_ring(ib50u_ring), .clkinb(clkinb),
.csr_dly_ovrd(csr_dly_ovrd[3:0]), .csr_dly_ovrden(csr_dly_ovrden),
.vssl_aibcr3aux(vss_aibcr3aux), .clkin(clkin),
.vcc_aibcr3aux(vcc_aibcr3aux), .clkout(clkint),
.iosc_fuse_trim(iosc_fuse_trim[9:0]));
/*
aibcr3_clkbuf xbuf_lvl1_r ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(clkout_r), .in(lvl0_out));
aibcr3_clkbuf xbuf_lvl1_l ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(clkout_l), .in(lvl0_out));
aibcr3_preclkbuf xbuf_lvl0 ( .vss_pl(vss_aibcr3aux),
.vcc_pl(vcc_aibcr3aux), .out(lvl0_out), .in(clkint));
*/
assign clkout_r = lvl0_out;
assign clkout_l = lvl0_out;
assign lvl0_out = clkint;
aibcr3_aliasd aliasv23 ( .rb(lstrbclk_l_4), .ra(clkout_l));
aibcr3_aliasd aliasv5 ( .rb(lstrbclk_l_11), .ra(clkout_l));
aibcr3_aliasd aliasv27 ( .rb(lstrbclk_mimic2), .ra(clkout_r));
aibcr3_aliasd aliasv10 ( .rb(lstrbclk_r_7), .ra(clkout_r));
aibcr3_aliasd aliasv13 ( .rb(lstrbclk_r_10), .ra(clkout_r));
aibcr3_aliasd aliasv14 ( .rb(lstrbclk_r_6), .ra(clkout_r));
aibcr3_aliasd aliasv11 ( .rb(lstrbclk_r_11), .ra(clkout_r));
aibcr3_aliasd aliasv8 ( .rb(lstrbclk_r_1), .ra(clkout_r));
aibcr3_aliasd aliasv15 ( .rb(lstrbclk_r_2), .ra(clkout_r));
aibcr3_aliasd aliasv9 ( .rb(lstrbclk_r_3), .ra(clkout_r));
aibcr3_aliasd aliasv16 ( .rb(lstrbclk_r_0), .ra(clkout_r));
aibcr3_aliasd aliasv26 ( .rb(lstrbclk_mimic1), .ra(clkout_r));
aibcr3_aliasd aliasv17 ( .rb(lstrbclk_r_4), .ra(clkout_r));
aibcr3_aliasd aliasv7 ( .rb(lstrbclk_r_5), .ra(clkout_r));
aibcr3_aliasd aliasv12 ( .rb(lstrbclk_l_8), .ra(clkout_l));
aibcr3_aliasd aliasv20 ( .rb(lstrbclk_l_6), .ra(clkout_l));
aibcr3_aliasd aliasv18 ( .rb(lstrbclk_r_8), .ra(clkout_r));
aibcr3_aliasd aliasv25 ( .rb(lstrbclk_mimic0), .ra(clkout_l));
aibcr3_aliasd aliasv19 ( .rb(lstrbclk_l_10), .ra(clkout_l));
aibcr3_aliasd aliasv6 ( .rb(lstrbclk_r_9), .ra(clkout_r));
aibcr3_aliasd aliasv4 ( .rb(lstrbclk_l_7), .ra(clkout_l));
aibcr3_aliasd aliasv3 ( .rb(lstrbclk_l_3), .ra(clkout_l));
aibcr3_aliasd aliasv21 ( .rb(lstrbclk_l_2), .ra(clkout_l));
aibcr3_aliasd aliasv24 ( .rb(lstrbclk_rep), .ra(clkout_l));
aibcr3_aliasd aliasv22 ( .rb(lstrbclk_l_0), .ra(clkout_l));
aibcr3_aliasd aliasv2 ( .rb(lstrbclk_l_1), .ra(clkout_l));
aibcr3_aliasd aliasv0 ( .rb(lstrbclk_l_9), .ra(clkout_l));
aibcr3_aliasd aliasv1 ( .rb(lstrbclk_l_5), .ra(clkout_l));
endmodule |
module aibcr3aux_osc_dft ( osc2dft_out, scan_out, testpin_cntr_code,
vcc_aibcraux, vss_aibcraux, counter, osc_clkin, scan_clk, scan_in,
scan_mode_n, scan_rst_n, scan_shift_n, testpin_clk,
testpin_enable, testpin_resetb );
output scan_out;
inout vcc_aibcraux, vss_aibcraux;
input osc_clkin, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n, testpin_clk, testpin_enable, testpin_resetb;
output [5:0] testpin_cntr_code;
output [8:6] osc2dft_out;
input [2:0] counter;
wire net167, net165, so3, vss_aibcraux, net050, scanmoden, scanrstn, net033, dff_clk, scanclk, net038, sync_in, net092, net162, net093, scanin, scan_in, scan_clk, scan_rst_n, scan_mode_n, testpin_resetb, testpin_clk, enable, resetb, scanshftn, scanshft, scan_shift_n;
wire so6;
wire so5;
wire so4;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_dft";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_osc_6bcntr x6bcntr ( .scan_shift_n(scanshftn),
.scan_out(scan_out), .scan_clk(scanclk), .scan_in(so6),
.scan_mode_n(scanmoden), .scan_rst_n(scanrstn),
.vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
.out_bin(testpin_cntr_code[5:0]), .clk(osc_clkin),
.cntr(counter[2:0]), .en(enable), .reset_n(resetb));
assign net167 = net165 ? vss_aibcraux : so3;
assign net050 = scanmoden ? net033 : scanrstn;
assign dff_clk = scanmoden ? net038 : scanclk;
assign sync_in = scanmoden ? net092 : scanclk;
assign net162 = scanmoden ? net093 : scanrstn;
assign scanin = scan_in;
assign scanclk = scan_clk;
assign scanrstn = scan_rst_n;
assign scanmoden = scan_mode_n;
assign net033 = testpin_resetb;
assign net038 = testpin_clk;
assign osc2dft_out[6] = enable;
assign osc2dft_out[8] = sync_in;
assign osc2dft_out[7] = resetb;
aibcr3aux_osc_sync xsync ( .scan_shift_n(scanshftn), .scan_out(so6),
.scan_clk(scanclk), .scan_in(so5), .scan_mode_n(scanmoden),
.scan_rst_n(scanrstn), .vss_aibcraux(vss_aibcraux),
.vcc_aibcraux(vcc_aibcraux), .en_out(enable), .resetb_out(resetb),
.clk(osc_clkin), .d(sync_in), .resetb(net162));
aibcr3aux_osc_ff x23 ( .cdn(net162), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(net092), .so(so4), .cp(dff_clk), .d(net167), .se_n(scanshftn),
.si(so3));
aibcr3aux_osc_ff x22 ( .cdn(net162), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(net165), .so(so5), .cp(sync_in), .d(vcc_aibcraux),
.se_n(scanshftn), .si(so4));
aibcr3_sync_2ff xsync0 ( .SE(scanshft), .D(vcc_aibcraux), .Q(net093), .CP(dff_clk), .SI(scanin), .CDN(net050));
aibcr3_sync_2ff x27 ( .SE(scanshft), .D(testpin_enable), .Q(so3), .CP(dff_clk), .SI(net093), .CDN(net162));
assign scanshftn = ~scanshft;
assign scanshft = ~scan_shift_n;
endmodule |
module aibcr3aux_osc_lsbuf ( out, vccl, vccreg, vss, vssreg, in );
output out;
inout vccl, vccreg, vss, vssreg;
input in;
wire in2b, in2, out, inb, in;
assign in2b = ~in2;
assign out = ~in2b;
assign in2 = ~inb;
assign inb = ~in;
endmodule |
module aibcr3aux_inclkdly
#(
parameter PERIOD = 500
)
(
output clkout,
input clkin, clkinb, csr_dly_ovrden, ib50u_ring, ib50uc, vcc_aibcr3aux,
vssl_aibcr3aux,
input [3:0] csr_dly_ovrd,
input [9:0] iosc_fuse_trim
);
//wire vssl , net033 , nbias , vbias , nocon0 , net032 ;
assign #PERIOD clkout = clkin;
endmodule |
module aibcr3aux_osc ( ib50u1, ib50u2, ib50u3, ib50u4, oaib_dft2osc,
oosc_atb0, oosc_atb1, oosc_clkout, oosc_monitor, oosc_reserved,
scan_out, vcca_aibcraux, vcc_aibcraux, vss_aibcraux, iaib_dft2osc, iosc_atbmuxsel,
iosc_bypclk, iosc_bypclken, iosc_cr_dftcounter, iosc_cr_ld_cntr,
iosc_cr_pdb, iosc_cr_rdy_dly, iosc_cr_trim, iosc_cr_vccdreg_vsel,
iosc_cr_vreg_rdy, iosc_fuse_trim, iosc_ic50u, iosc_it50u,
iosc_monitoren, iosc_reserved, pipeline_global_en, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n, osc_extrref );
output ib50u1, ib50u2, ib50u3, ib50u4, oosc_atb0, oosc_atb1,
oosc_clkout, oosc_monitor, scan_out;
input vcca_aibcraux, vcc_aibcraux, vss_aibcraux, iosc_bypclk, iosc_bypclken, iosc_cr_pdb,
iosc_cr_rdy_dly, iosc_ic50u, iosc_it50u, iosc_monitoren,
pipeline_global_en, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
inout osc_extrref;
output [12:0] oaib_dft2osc;
output [3:0] oosc_reserved;
input [2:0] iosc_cr_vreg_rdy;
input [4:0] iosc_cr_vccdreg_vsel;
input [3:0] iosc_atbmuxsel;
input [2:0] iaib_dft2osc;
input [2:0] iosc_cr_dftcounter;
input [8:0] iosc_cr_trim;
input [2:0] iosc_cr_ld_cntr;
input [7:0] iosc_reserved;
input [9:0] iosc_fuse_trim;
wire chicken_bit;
wire comparator_out;
wire osc_2x;
/////////////////////////////////
// for VCS and ICC compatibility
/////////////////////////////////
aibcr3aux_osc_ana ana ( // .ib50u({ib50u3,ib50u1}), .ib100u({ib50u4,ib50u2}),
.ib50u_1(ib50u1), .ib50u_2(ib50u3), .ib100u_1(ib50u2), .ib100u_2(ib50u4), .chicken_bit(chicken_bit),
.comp_out(comparator_out), .osc_atb1(oosc_atb1),
.osc_atb0(oosc_atb0), .vcca_aibcr3aux(vcca_aibcraux), .vcc_aibcr3aux(vcc_aibcraux),
.vss_aibcr3aux(vss_aibcraux), .iosc_atbmuxsel(iosc_atbmuxsel[3:0]),
.osc_out(osc_2x), .iosc_cr_pdb(iosc_cr_pdb),
.iosc_cr_trim(iosc_cr_trim[8:0]),
.iosc_cr_vccdreg_vsel(iosc_cr_vccdreg_vsel[4:0]),
.iosc_cr_vreg_rdy(iosc_cr_vreg_rdy[2:0]),
.iosc_fuse_trim(iosc_fuse_trim[9:0]), .iosc_ic50u(iosc_ic50u),
.iosc_it50u(iosc_it50u), .osc_extrref(osc_extrref));
aibcr3aux_osc_dig dig ( .scan_shift_n(scan_shift_n),
.pipeline_global_en(pipeline_global_en), .scan_out(scan_out),
.scan_clk(scan_clk), .scan_in(scan_in), .scan_mode_n(scan_mode_n),
.scan_rst_n(scan_rst_n), .chicken_bit(chicken_bit),
.vss_aibcr3aux(vss_aibcraux), .vcc_aibcr3aux(vcc_aibcraux),
.comp_in(comparator_out), .iosc_cr_ld_cntr(iosc_cr_ld_cntr[2:0]),
.oosc_monitor(oosc_monitor), .oaib_dft2osc(oaib_dft2osc[12:0]),
.oosc_clkout(oosc_clkout), .iaib_dft2osc(iaib_dft2osc[2:0]),
.iosc_bypclk(iosc_bypclk), .iosc_bypclken(iosc_bypclken),
.iosc_cr_dftcounter(iosc_cr_dftcounter[2:0]),
.iosc_monitoren(iosc_monitoren), .irstb(iosc_cr_rdy_dly),
.oscin_2x(osc_2x));
endmodule |
module aibcr3aux_osc_ff ( q, so, vbb, vdd, vpp, vss, cdn, cp, d, se_n,
si );
output q, so;
inout vbb, vdd, vpp, vss;
input cdn, cp, d, se_n, si;
wire so, q, net68, se_n, si, SE;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_ff";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign SE = ~se_n;
// aibcr3_ff_r x0 ( .CDN(cdn), .CP(cp), .D(net68), .Q(q));
aibcr3_svt16_scdffcdn_cust x0 (.CDN(cdn), .CK(cp), .D(d), .Q(q), .SI(si), .SE(SE), .scQ(so));
endmodule |
module aibcr3aux_osc_ana (
////////////////////////////////
// inputs and output pins
////////////////////////////////
input [3:0] iosc_atbmuxsel,
input [4:0] iosc_cr_vccdreg_vsel, // controls supply to osc, not implemented
input [2:0] iosc_cr_vreg_rdy, // comparator reference, not implemented
input iosc_ic50u, // 50uA supply, not implemented
input iosc_it50u, // 50uA supply, not implemented
input [9:0] iosc_fuse_trim,
input [8:0] iosc_cr_trim, // trim osc freq, not implemented
// except iosc_cr_trim[7] (chicken bit)
input iosc_cr_pdb, // 0: turn off oscillator
inout vss_aibcr3aux,
inout vcc_aibcr3aux,
inout vcca_aibcr3aux,
output osc_out, // oscillator output
output osc_atb0,
output osc_atb1,
output chicken_bit,
output comp_out, // deprecate
// output [2:1] ib50u,
output ib50u_1,
output ib50u_2,
// output [2:1] ib100u,
output ib100u_2,
output ib100u_1,
inout osc_extrref
);
////////////////////////////////
// constants
////////////////////////////////
parameter PERIOD = 500; // oscillator period
parameter CYCLE = 100000000; // number of cycles
////////////////////////////////
// local variables
////////////////////////////////
reg osc_clk;
reg q;
////////////////////////////////
// generate oscillator clock
////////////////////////////////
initial begin
osc_clk = 1'b0;
end
always begin
#250 osc_clk = ~osc_clk; // 250ps is the half period of clock
end
////////////////////////////////
// osc power up/down condition
////////////////////////////////
// need to add case statement to allow oscillator to spin, only if the
// osc_extrref is weakly pulled down at the chip level. update pending
and (osc_out, osc_clk, iosc_cr_pdb);
assign chicken_bit = iosc_fuse_trim[9] ? iosc_fuse_trim[7] : iosc_cr_trim[7];
assign {osc_atb0,osc_atb1} = 2'bzz;
endmodule |
module aibcr3aux_pasred_baldwin
(
dn_por,
iopad_crdet,
iopad_dn_por,
vccl_aibcr3aux,
vssl_aibcr3aux );
output dn_por;
inout iopad_crdet,
iopad_dn_por;
input vccl_aibcr3aux,
vssl_aibcr3aux;
wire csr_iocsr_sel, vssl_aibcr3aux, vcc_aibcr3aux, csr_pred_txen_int, csr_pred_txen;
// Buses in the design
wire [1:0] csr_pred_pdrv_int;
wire [2:0] csr_pred_rxen_int;
wire [1:0] csr_pred_ndrv_int;
wire net0266;
wire net087;
wire net075;
wire net076;
wire net077;
wire net078;
wire net0276;
wire net080;
wire net086;
wire net051;
wire net085;
wire net052;
wire net084;
wire net082;
wire net050;
wire net083;
wire net081;
wire net0291;
wire net0255;
wire net0206;
wire net0210;
wire net0214;
wire net0218;
wire net0183;
wire net0222;
wire net0251;
wire net054;
wire net0247;
wire net053;
wire net0243;
wire net0235;
wire net055;
wire net0239;
wire net0231;
wire net0283;
wire net0253;
wire net0204;
wire net0208;
wire net0212;
wire net0216;
wire net0220;
wire net0249;
wire net062;
wire net0245;
wire net063;
wire net0241;
wire net0233;
wire net064;
wire net0237;
wire net0229;
wire net0282;
wire net0101;
wire net088;
wire net089;
wire net090;
wire net091;
wire net093;
wire net0100;
wire net068;
wire net099;
wire net070;
wire net098;
wire net096;
wire net069;
wire net097;
wire net095;
wire net0277;
wire net0263;
wire net0224;
wire net0225;
wire net0226;
wire net0227;
wire net0228;
wire net0262;
wire net067;
wire net0261;
wire net065;
wire net0260;
wire net0258;
wire net066;
wire net0259;
wire net0257;
wire net0285;
wire net0115;
wire net0103;
wire net0104;
wire net0105;
wire net0106;
wire net0108;
wire net0114;
wire net073;
wire net0113;
wire net071;
wire net0112;
wire net0110;
wire net072;
wire net0111;
wire net0109;
wire net0288;
wire net0130;
wire net0442;
wire net0416;
wire net028;
wire net029;
wire net0402;
wire net0129;
wire net0267;
wire net0128;
wire net0265;
wire net0127;
wire net0125;
wire net074;
wire net0126;
wire net0124;
wire net0281;
wire net0254;
wire net0205;
wire net0209;
wire net0213;
wire net0217;
wire net0184;
wire net0221;
wire net0250;
wire net056;
wire net0246;
wire net057;
wire net0242;
wire net0234;
wire net058;
wire net0238;
wire net0230;
wire net0286;
wire net0256;
wire net0207;
wire net0211;
wire net0215;
wire net0219;
wire net0185;
wire net0223;
wire net0252;
wire net061;
wire net0248;
wire net060;
wire net0244;
wire net0236;
wire net059;
wire net0240;
wire net0232;
wire net0307;
wire net0334;
wire net0336;
wire net0123;
wire net0122;
wire net0284;
wire net0314;
wire net0299;
wire net0312;
wire net0305;
wire net0320;
wire net0107;
wire net0327;
wire net0278;
wire net0333;
wire net0325;
wire net0297;
wire net0290;
wire net0102;
wire net0323;
wire net0335;
wire net0120;
wire net0121;
wire net0119;
wire net0117;
wire net0116;
wire net0118;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_pasred";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
//assign csr_pred_rxen_int[2:0] = csr_iocsr_sel ? csr_pred_rxen[2:0] : vssl_aibcr3aux;
//assign csr_pred_pdrv_int[1:0] = csr_iocsr_sel ? csr_pred_pdrv[1:0] : {vcc_aibcr3aux, vssl_aibcr3aux};
//assign csr_pred_txen_int = csr_iocsr_sel ? csr_pred_txen : vcc_aibcr3aux;
//assign csr_pred_ndrv_int[1:0] = csr_iocsr_sel ? csr_pred_ndrv[1:0] : {vcc_aibcr3aux, vssl_aibcr3aux};
aibcr3_buffx1_top xporvccl ( .idata1_in1_jtag_out(net0307),
.idata0_in1_jtag_out(net0334), .async_dat_in1_jtag_out(net0336),
.prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0266),
.vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vccl_aibcr3aux),
.por_aib_vccl(vssl_aibcr3aux), .por_aib_vcchssi(vssl_aibcr3aux),
.anlg_rstb(vccl_aibcr3aux), .pd_data_aib(net087), .oclk_out(net075),
.oclkb_out(net076), .odat0_out(net077), .odat1_out(net078),
.odat_async_out(net0276), .pd_data_out(net080),
.async_dat_in0(vccl_aibcr3aux), .async_dat_in1(vssl_aibcr3aux),
.iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
.idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
.idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
.idataselb_in0(vssl_aibcr3aux), .idataselb_in1(vssl_aibcr3aux),
.iddren_in0(vssl_aibcr3aux), .iddren_in1(vssl_aibcr3aux),
.ilaunch_clk_in0(vssl_aibcr3aux), .ilaunch_clk_in1(vssl_aibcr3aux),
.ilpbk_dat_in0(vssl_aibcr3aux), .ilpbk_dat_in1(vssl_aibcr3aux),
.ilpbk_en_in0(vssl_aibcr3aux), .ilpbk_en_in1(vssl_aibcr3aux),
.indrv_in0({vccl_aibcr3aux,vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux,
vssl_aibcr3aux}), .ipdrv_in0({vccl_aibcr3aux,vssl_aibcr3aux}),
.ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in0({vssl_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in1({vssl_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux}),
.istrbclk_in0(vssl_aibcr3aux), .istrbclk_in1(vssl_aibcr3aux),
.itxen_in0(vccl_aibcr3aux), .itxen_in1(vssl_aibcr3aux),
.oclk_in1(vssl_aibcr3aux), .odat_async_aib(net086),
.oclkb_in1(vssl_aibcr3aux), .jtag_clksel(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(vccl_aibcr3aux),
.jtag_clkdr_out(net051), .jtag_intest(vssl_aibcr3aux),
.odat1_aib(net085), .jtag_rx_scan_out(net052), .odat0_aib(net084),
.oclk_aib(net082), .last_bs_out(net050), .oclkb_aib(net083),
.jtag_clkdr_in(vssl_aibcr3aux), .jtag_rstb_en(vssl_aibcr3aux),
.jtag_mode_in(vssl_aibcr3aux), .jtag_rstb(vssl_aibcr3aux),
.jtag_tx_scan_in(vssl_aibcr3aux),
.jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
.iopad(iopad_crdet), .oclkn(net081), .iclkn(vssl_aibcr3aux),
.test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xtstmx2 ( .idata1_in1_jtag_out(net0123),
// .idata0_in1_jtag_out(net0122), .async_dat_in1_jtag_out(net0284),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0291),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0255), .oclk_out(net0206), .oclkb_out(net0210),
// .odat0_out(net0214), .odat1_out(net0218),
// .odat_async_out(net0183), .pd_data_out(net0222),
// .async_dat_in0(jtr_tms), .async_dat_in1(vssl_aibcr3aux),
// .iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
// .idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
// .idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
// .idataselb_in0(csr_pred_dataselb), .idataselb_in1(vssl_aibcr3aux),
// .iddren_in0(vssl_aibcr3aux), .iddren_in1(vssl_aibcr3aux),
// .ilaunch_clk_in0(vssl_aibcr3aux), .ilaunch_clk_in1(vssl_aibcr3aux),
// .ilpbk_dat_in0(vssl_aibcr3aux), .ilpbk_dat_in1(vssl_aibcr3aux),
// .ilpbk_en_in0(vssl_aibcr3aux), .ilpbk_en_in1(vssl_aibcr3aux),
// .indrv_in0(csr_pred_ndrv_int[1:0]), .indrv_in1({vssl_aibcr3aux,
// vssl_aibcr3aux}), .ipdrv_in0(csr_pred_pdrv_int[1:0]),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in1({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .istrbclk_in0(vssl_aibcr3aux), .istrbclk_in1(vssl_aibcr3aux),
// .itxen_in0(csr_pred_txen_int), .itxen_in1(vssl_aibcr3aux),
// .oclk_in1(vssl_aibcr3aux), .odat_async_aib(net0251),
// .oclkb_in1(vssl_aibcr3aux), .odat0_in1(vssl_aibcr3aux),
// .odat1_in1(vssl_aibcr3aux), .odat_async_in1(vssl_aibcr3aux),
// .shift_en(vssl_aibcr3aux), .pd_data_in1(vssl_aibcr3aux),
// .dig_rstb(dig_rstb), .jtag_clkdr_out(net054), .odat1_aib(net0247),
// .jtag_rx_scan_out(net053), .odat0_aib(net0243),
// .oclk_aib(net0235), .last_bs_out(net055), .oclkb_aib(net0239),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jtr_tms), .oclkn(net0231), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xjt_tms ( .idata1_in1_jtag_out(net0314),
// .idata0_in1_jtag_out(net0299), .async_dat_in1_jtag_out(net0312),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0283),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0253), .oclk_out(net0204), .oclkb_out(net0208),
// .odat0_out(net0212), .odat1_out(net0216), .odat_async_out(jt_tms),
// .pd_data_out(net0220), .async_dat_in0(vssl_aibcr3aux),
// .async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
// .iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
// .idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
// .idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
// .idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
// .iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
// .ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
// .ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
// .ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
// vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0(csr_pred_rxen_int[2:0]), .irxen_in1({vssl_aibcr3aux,
// vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
// .istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
// .itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
// .odat_async_aib(net0249), .oclkb_in1(vssl_aibcr3aux),
// .odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
// .odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
// .pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
// .jtag_clkdr_out(net062), .odat1_aib(net0245),
// .jtag_rx_scan_out(net063), .odat0_aib(net0241),
// .oclk_aib(net0233), .last_bs_out(net064), .oclkb_aib(net0237),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jt_tms), .oclkn(net0229), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xjt_tdi ( .idata1_in1_jtag_out(net0305),
// .idata0_in1_jtag_out(net0320), .async_dat_in1_jtag_out(net0107),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0282),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0101), .oclk_out(net088), .oclkb_out(net089),
// .odat0_out(net090), .odat1_out(net091), .odat_async_out(jt_tdi),
// .pd_data_out(net093), .async_dat_in0(vssl_aibcr3aux),
// .async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
// .iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
// .idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
// .idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
// .idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
// .iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
// .ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
// .ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
// .ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
// vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0(csr_pred_rxen_int[2:0]), .irxen_in1({vssl_aibcr3aux,
// vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
// .istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
// .itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
// .odat_async_aib(net0100), .oclkb_in1(vssl_aibcr3aux),
// .odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
// .odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
// .pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
// .jtag_clkdr_out(net068), .odat1_aib(net099),
// .jtag_rx_scan_out(net070), .odat0_aib(net098), .oclk_aib(net096),
// .last_bs_out(net069), .oclkb_aib(net097),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jt_tdi), .oclkn(net095), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xjt_tck ( .idata1_in1_jtag_out(net0327),
// .idata0_in1_jtag_out(net0278), .async_dat_in1_jtag_out(net0333),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0277),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0263), .oclk_out(net0224), .oclkb_out(net0225),
// .odat0_out(net0226), .odat1_out(net0227), .odat_async_out(jt_tck),
// .pd_data_out(net0228), .async_dat_in0(vssl_aibcr3aux),
// .async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
// .iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
// .idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
// .idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
// .idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
// .iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
// .ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
// .ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
// .ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
// vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0(csr_pred_rxen_int[2:0]), .irxen_in1({vssl_aibcr3aux,
// vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
// .istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
// .itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
// .odat_async_aib(net0262), .oclkb_in1(vssl_aibcr3aux),
// .odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
// .odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
// .pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
// .jtag_clkdr_out(net067), .odat1_aib(net0261),
// .jtag_rx_scan_out(net065), .odat0_aib(net0260),
// .oclk_aib(net0258), .last_bs_out(net066), .oclkb_aib(net0259),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jt_tck), .oclkn(net0257), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
aibcr3_buffx1_top xdn_por ( .idata1_in1_jtag_out(net0325),
.idata0_in1_jtag_out(net0297), .async_dat_in1_jtag_out(net0290),
.prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0285),
.vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vccl_aibcr3aux),
.por_aib_vccl(vssl_aibcr3aux), .por_aib_vcchssi(vssl_aibcr3aux),
.jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
.jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(vccl_aibcr3aux),
.pd_data_aib(net0115), .oclk_out(net0103), .oclkb_out(net0104),
.odat0_out(net0105), .odat1_out(net0106), .odat_async_out(net0269),
.pd_data_out(net0108), .async_dat_in0(vssl_aibcr3aux),
.async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
.iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
.idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
.idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
.idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
.iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
.ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
.ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
.ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
.irxen_in0({vssl_aibcr3aux, vssl_aibcr3aux, vssl_aibcr3aux}), .irxen_in1({vssl_aibcr3aux,
vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
.istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
.itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
.odat_async_aib(dn_por), .oclkb_in1(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(vccl_aibcr3aux),
.jtag_clkdr_out(net073), .odat1_aib(net0113),
.jtag_rx_scan_out(net071), .odat0_aib(net0112),
.oclk_aib(net0110), .last_bs_out(net072), .oclkb_aib(net0111),
.jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
.jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
.jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
.iopad(iopad_dn_por), .oclkn(net0109), .iclkn(vssl_aibcr3aux),
.test_weakpu(vssl_aibcr3aux), .test_weakpd(vccl_aibcr3aux));
// aibcr3_buffx1_top xdn_rst_n ( .idata1_in1_jtag_out(net0102),
// .idata0_in1_jtag_out(net0323), .async_dat_in1_jtag_out(net0335),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0288),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0130), .oclk_out(net0442), .oclkb_out(net0416),
// .odat0_out(net028), .odat1_out(net029), .odat_async_out(dn_rst_n),
// .pd_data_out(net0402), .async_dat_in0(vssl_aibcr3aux),
// .async_dat_in1(vssl_aibcr3aux), .iclkin_dist_in0(vssl_aibcr3aux),
// .iclkin_dist_in1(vssl_aibcr3aux), .idata0_in0(vssl_aibcr3aux),
// .idata0_in1(vssl_aibcr3aux), .idata1_in0(vssl_aibcr3aux),
// .idata1_in1(vssl_aibcr3aux), .idataselb_in0(vssl_aibcr3aux),
// .idataselb_in1(vssl_aibcr3aux), .iddren_in0(vssl_aibcr3aux),
// .iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
// .ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
// .ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
// .ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
// vssl_aibcr3aux}), .indrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0(csr_pred_rxen_int[2:0]), .irxen_in1({vssl_aibcr3aux,
// vssl_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
// .istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
// .itxen_in1(vssl_aibcr3aux), .oclk_in1(vssl_aibcr3aux),
// .odat_async_aib(net0129), .oclkb_in1(vssl_aibcr3aux),
// .odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
// .odat_async_in1(vssl_aibcr3aux), .shift_en(vssl_aibcr3aux),
// .pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
// .jtag_clkdr_out(net0267), .odat1_aib(net0128),
// .jtag_rx_scan_out(net0265), .odat0_aib(net0127),
// .oclk_aib(net0125), .last_bs_out(net074), .oclkb_aib(net0126),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_dn_rst_n), .oclkn(net0124), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xtstmx0 ( .idata1_in1_jtag_out(net0120),
// .idata0_in1_jtag_out(net0121), .async_dat_in1_jtag_out(net0119),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0281),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0254), .oclk_out(net0205), .oclkb_out(net0209),
// .odat0_out(net0213), .odat1_out(net0217),
// .odat_async_out(net0184), .pd_data_out(net0221),
// .async_dat_in0(jtr_tdo), .async_dat_in1(vssl_aibcr3aux),
// .iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
// .idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
// .idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
// .idataselb_in0(csr_pred_dataselb), .idataselb_in1(vssl_aibcr3aux),
// .iddren_in0(vssl_aibcr3aux), .iddren_in1(vssl_aibcr3aux),
// .ilaunch_clk_in0(vssl_aibcr3aux), .ilaunch_clk_in1(vssl_aibcr3aux),
// .ilpbk_dat_in0(vssl_aibcr3aux), .ilpbk_dat_in1(vssl_aibcr3aux),
// .ilpbk_en_in0(vssl_aibcr3aux), .ilpbk_en_in1(vssl_aibcr3aux),
// .indrv_in0(csr_pred_ndrv_int[1:0]), .indrv_in1({vssl_aibcr3aux,
// vssl_aibcr3aux}), .ipdrv_in0(csr_pred_pdrv_int[1:0]),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in1({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .istrbclk_in0(vssl_aibcr3aux), .istrbclk_in1(vssl_aibcr3aux),
// .itxen_in0(csr_pred_txen_int), .itxen_in1(vssl_aibcr3aux),
// .oclk_in1(vssl_aibcr3aux), .odat_async_aib(net0250),
// .oclkb_in1(vssl_aibcr3aux), .odat0_in1(vssl_aibcr3aux),
// .odat1_in1(vssl_aibcr3aux), .odat_async_in1(vssl_aibcr3aux),
// .shift_en(vssl_aibcr3aux), .pd_data_in1(vssl_aibcr3aux),
// .dig_rstb(dig_rstb), .jtag_clkdr_out(net056), .odat1_aib(net0246),
// .jtag_rx_scan_out(net057), .odat0_aib(net0242),
// .oclk_aib(net0234), .last_bs_out(net058), .oclkb_aib(net0238),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jtr_tdo), .oclkn(net0230), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
// aibcr3_buffx1_top xio_oe0 ( .idata1_in1_jtag_out(net0117),
// .idata0_in1_jtag_out(net0116), .async_dat_in1_jtag_out(net0118),
// .prev_io_shift_en(vssl_aibcr3aux), .jtag_clkdr_outn(net0286),
// .vssl(vssl_aibcr3aux), .vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux),
// .por_aib_vccl(por_vccl), .por_aib_vcchssi(por_vcchssi),
// .jtag_clksel(vssl_aibcr3aux), .jtag_intest(vssl_aibcr3aux),
// .jtag_rstb_en(vssl_aibcr3aux), .anlg_rstb(anlg_rstb),
// .pd_data_aib(net0256), .oclk_out(net0207), .oclkb_out(net0211),
// .odat0_out(net0215), .odat1_out(net0219),
// .odat_async_out(net0185), .pd_data_out(net0223),
// .async_dat_in0(jtr_tck), .async_dat_in1(vssl_aibcr3aux),
// .iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
// .idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
// .idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
// .idataselb_in0(csr_pred_dataselb), .idataselb_in1(vssl_aibcr3aux),
// .iddren_in0(vssl_aibcr3aux), .iddren_in1(vssl_aibcr3aux),
// .ilaunch_clk_in0(vssl_aibcr3aux), .ilaunch_clk_in1(vssl_aibcr3aux),
// .ilpbk_dat_in0(vssl_aibcr3aux), .ilpbk_dat_in1(vssl_aibcr3aux),
// .ilpbk_en_in0(vssl_aibcr3aux), .ilpbk_en_in1(vssl_aibcr3aux),
// .indrv_in0(csr_pred_ndrv_int[1:0]), .indrv_in1({vssl_aibcr3aux,
// vssl_aibcr3aux}), .ipdrv_in0(csr_pred_pdrv_int[1:0]),
// .ipdrv_in1({vssl_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in0({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .irxen_in1({vssl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux}),
// .istrbclk_in0(vssl_aibcr3aux), .istrbclk_in1(vssl_aibcr3aux),
// .itxen_in0(csr_pred_txen_int), .itxen_in1(vssl_aibcr3aux),
// .oclk_in1(vssl_aibcr3aux), .odat_async_aib(net0252),
// .oclkb_in1(vssl_aibcr3aux), .odat0_in1(vssl_aibcr3aux),
// .odat1_in1(vssl_aibcr3aux), .odat_async_in1(vssl_aibcr3aux),
// .shift_en(vssl_aibcr3aux), .pd_data_in1(vssl_aibcr3aux),
// .dig_rstb(dig_rstb), .jtag_clkdr_out(net061), .odat1_aib(net0248),
// .jtag_rx_scan_out(net060), .odat0_aib(net0244),
// .oclk_aib(net0236), .last_bs_out(net059), .oclkb_aib(net0240),
// .jtag_clkdr_in(vssl_aibcr3aux), .jtag_mode_in(vssl_aibcr3aux),
// .jtag_rstb(vssl_aibcr3aux), .jtag_tx_scan_in(vssl_aibcr3aux),
// .jtag_tx_scanen_in(vssl_aibcr3aux), .last_bs_in(vssl_aibcr3aux),
// .iopad(iopad_jtr_tck), .oclkn(net0232), .iclkn(vssl_aibcr3aux),
// .test_weakpu(vssl_aibcr3aux), .test_weakpd(vssl_aibcr3aux));
endmodule |
module aibcr3aux_osc_6bcntr ( out_bin, scan_out, vcc_aibcraux,
vss_aibcraux, clk, cntr, en, reset_n, scan_clk, scan_in,
scan_mode_n, scan_rst_n, scan_shift_n );
output scan_out;
inout vcc_aibcraux, vss_aibcraux;
input clk, en, reset_n, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
output [5:0] out_bin;
input [2:0] cntr;
wire clkin, net77, overflow, net78, en, clk, clkdiv2, net038, net037, scan_out;
// Buses in the design
wire [5:0] cnt;
wire so0;
wire so1;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_6bcntr";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign clkin = ~net77;
assign overflow = ~cnt[2];
assign out_bin[5:0] = cnt[5:0];
assign net77 = ~(net78 & en);
assign net78 = cntr[0] ? clkdiv2 : clk;
aibcr3aux_osc_div2_asyn_clr x13 ( .scan_shift_n(scan_shift_n),
.scan_out(so0), .scan_clk(scan_clk), .scan_in(scan_in),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
.clkout(clkdiv2), .irstb(reset_n), .clkin(clk));
aibcr3aux_osc_3bcntr xbincntr_lsb ( .scan_shift_n(scan_shift_n),
.scan_out(so1), .scan_clk(scan_clk), .scan_in(so0),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
.bin_cnt(cnt[2:0]), .clk(clkin), .rstb(reset_n));
aibcr3aux_osc_3bcntr xbincntr_msb ( .scan_shift_n(scan_shift_n),
.scan_out(net037), .scan_clk(scan_clk), .scan_in(so1),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcraux(vss_aibcraux), .vcc_aibcraux(vcc_aibcraux),
.bin_cnt(cnt[5:3]), .clk(overflow), .rstb(reset_n));
assign net038 = ~net037;
assign scan_out = ~net038;
endmodule |
module aibcr3aux_osc_dig ( oaib_dft2osc, oosc_clkout, oosc_monitor,
scan_out, chicken_bit, comp_in, iaib_dft2osc, iosc_bypclk,
iosc_bypclken, iosc_cr_dftcounter, iosc_cr_ld_cntr,
iosc_monitoren, irstb, oscin_2x, pipeline_global_en, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n, vcc_aibcr3aux,
vss_aibcr3aux );
output oosc_clkout, oosc_monitor, scan_out;
input chicken_bit, comp_in, iosc_bypclk, iosc_bypclken,
iosc_monitoren, irstb, oscin_2x, pipeline_global_en, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n, vcc_aibcr3aux,
vss_aibcr3aux;
output [12:0] oaib_dft2osc;
input [2:0] iosc_cr_dftcounter;
input [2:0] iosc_cr_ld_cntr;
input [2:0] iaib_dft2osc;
wire test_clk, net089, bypass_clk, net092, net091, net090, net136, net137, clkgateout, iosc_monitoren, scanclk, scan_clk, oosc_clkout, clkmux_out, oosc_monitor, mon_out, scanmoden, scan_mode_n, scanrstn, scan_rst_n, scanin, scan_in, scanshftn, scan_shift_n, net046, syncrstb_dly, net060, net0100, vss_aibcr3aux, testpin_en, resetb, net099, iosc_bypclk, chicken_bit, irstb, syncrstb, net032;
// Buses in the design
wire [5:0] cntr_code;
wire so0;
wire divout;
wire so3;
wire so2;
wire so1;
wire clkout_buf;
wire net140;
wire net139;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_osc_dig";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign test_clk = ~net089;
assign bypass_clk = ~net092;
assign net091 = ~net090;
assign net136 = ~net137;
assign net137 = ~(clkgateout & iosc_monitoren);
aibcr3aux_osc_div2_syn_clr xdiv2sync ( .scan_shift_n(scanshftn),
.scan_out(so0), .scan_clk(scanclk), .scan_in(scanin),
.scan_mode_n(scanmoden), .scan_rst_n(scanrstn),
.vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
.syncrstb(syncrstb), .clkout(divout), .irstb(resetb),
.clkin(oscin_2x));
aibcr3aux_osc_clkmux xclkmux ( .vss_aibcraux(vss_aibcr3aux),
.vcc_aibcraux(vcc_aibcr3aux), .ina(clkgateout),
.sel(iosc_bypclken), .out(clkmux_out), .inb(bypass_clk));
aibcr3aux_osc_dft xdft ( .scan_shift_n(scanshftn), .scan_out(scan_out),
.scan_clk(scanclk), .scan_rst_n(scanrstn),
.scan_mode_n(scanmoden), .scan_in(so3),
.osc2dft_out(oaib_dft2osc[8:6]), .vss_aibcraux(vss_aibcr3aux),
.vcc_aibcraux(vcc_aibcr3aux), .testpin_cntr_code(cntr_code[5:0]),
.counter(iosc_cr_dftcounter[2:0]), .osc_clkin(clkmux_out),
.testpin_clk(test_clk), .testpin_enable(testpin_en),
.testpin_resetb(iaib_dft2osc[2]));
assign scanclk = scan_clk;
assign oosc_clkout = clkmux_out;
assign oosc_monitor = mon_out;
assign scanmoden = scan_mode_n;
assign oaib_dft2osc[5:0] = cntr_code[5:0];
assign scanrstn = scan_rst_n;
assign scanin = scan_in;
assign scanshftn = scan_shift_n;
aibcr3aux_osc_clkgatesync xclkgatesync ( .scan_shift_n(scanshftn),
.scan_rst_n(scanrstn), .scan_out(so2), .scan_clk(scanclk),
.clkgatesyncout(clkgateout), .scan_in(so1),
.vss_aibcraux(vss_aibcr3aux), .vcc_aibcraux(vcc_aibcr3aux),
.scan_mode_n(scanmoden), .ckin(clkout_buf), .en(syncrstb),
.rstb(syncrstb_dly));
aibcr3aux_osc_monitor xmonitor ( .scan_shift_n(scanshftn),
.scan_out(so3), .scan_clk(scanclk), .scan_in(so2),
.scan_mode_n(scanmoden), .scan_rst_n(scanrstn),
.vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
.out_divby16(mon_out), .out_divby32(net140), .out_divby64(net139),
.clkin(net136), .por(syncrstb_dly));
assign net046 = ~(syncrstb_dly & net060);
assign net0100 = ~vss_aibcr3aux;
assign net092 = ~net091;
assign oaib_dft2osc[12] = testpin_en;
aibcr3aux_osc_dly xdly ( .rstb(syncrstb), .clkout(clkout_buf),
.vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
.q(syncrstb_dly), .scan_out(so1), .clk(divout),
.scan_clk(scanclk), .scan_in(so0), .scan_mode_n(scanmoden),
.scan_rst_n(scanrstn), .scan_shift_n(scanshftn));
assign net089 = ~iaib_dft2osc[0];
assign resetb = ~net099;
assign testpin_en = ~net046;
assign net090 = ~iosc_bypclk;
assign net032 = 1'b0;
assign net099 = ~(net032 | irstb);
assign oaib_dft2osc[10] = syncrstb;
assign oaib_dft2osc[11] = iaib_dft2osc[2];
assign oaib_dft2osc[9] = resetb;
assign net060 = iaib_dft2osc[1];
endmodule |
module aibcr3aux_lvshift ( out, vccl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux, in);
output out;
input vccl_aibcr3aux, vcc_aibcr3aux, vssl_aibcr3aux;
input in;
reg out;
//wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vccl_aibcr3aux, vcc_aibcr3aux and vssl_aibcr3aux tracking as of now.
always @ (in, vccl_aibcr3aux, vcc_aibcr3aux)
begin
if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b0)
begin
out = 1'b0;
end
else if (vccl_aibcr3aux == 1'b0 && vcc_aibcr3aux == 1'b1)
begin
out = 1'b1;
end
else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b0)
begin
out = 1'b0;
end
else if (vccl_aibcr3aux == 1'b1 && vcc_aibcr3aux == 1'b1)
begin
out = in;
end
else
begin
out = 1'bx;
end
end
endmodule |
module aibcr3aux_osc_clkgatesync ( clkgatesyncout, scan_out,
vcc_aibcraux, vss_aibcraux, ckin, en, rstb, scan_clk, scan_in,
scan_mode_n, scan_rst_n, scan_shift_n );
output clkgatesyncout, scan_out;
inout vcc_aibcraux, vss_aibcraux;
input ckin, en, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
wire net023, ckin, clkgatesyncout, net027, net024, scanshft, scan_shift_n, scan_modn, scan_rstn, scan_out, dff_rstb, rstb, dff_clk, scan_ck, scan_mode_n, scan_clk, scan_rst_n;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_clkgatesync";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net023 = ~ckin;
assign clkgatesyncout = ~net027;
assign net027 = ~(net024 & ckin);
assign scanshft = ~scan_shift_n;
assign net024 = scan_modn ? scan_out : scan_rstn;
assign dff_rstb = scan_modn ? rstb : scan_rstn;
assign dff_clk = scan_modn ? net023 : scan_ck;
aibcr3_sync_2ff xsync0 ( .SE(scanshft), .D(en), .Q(scan_out), .CP(dff_clk), .SI(scan_in), .CDN(dff_rstb));
assign scan_modn = scan_mode_n;
assign scan_ck = scan_clk;
assign scan_rstn = scan_rst_n;
endmodule |
module aibcr3aux_osc_dly_unit ( q, so, cdn, cp, d, se_n, si, vbb, vdd,
vpp, vss );
output q, so;
input cdn, cp, d, se_n, si, vbb, vdd, vpp, vss;
wire net21;
wire net22;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_dly_unit";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_osc_ff x0 ( .cdn(cdn), .vbb(vbb), .vss(vss), .vdd(vdd),
.vpp(vpp), .q(net21), .so(net22), .cp(cp), .d(d), .se_n(se_n),
.si(si));
aibcr3aux_osc_ff x1 ( .cdn(cdn), .vbb(vbb), .vss(vss), .vdd(vdd),
.vpp(vpp), .q(q), .so(so), .cp(cp), .d(net21), .se_n(se_n),
.si(net22));
endmodule |
module aibcr3aux_osc_3bcntr ( bin_cnt, scan_out, vcc_aibcraux,
vss_aibcraux, clk, rstb, scan_clk, scan_in, scan_mode_n,
scan_rst_n, scan_shift_n );
output scan_out;
inout vcc_aibcraux, vss_aibcraux;
input clk, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
output [2:0] bin_cnt;
wire net150, net152, net147, net144, vcc_aibcraux, net065, scanmoden, scanclk, clk, net064, net063, net151, scanshftn, scan_shift_n, scanin, scan_in, scan_mode_n, scanrstn, scan_rst_n, scan_clk, net017, rstb;
// Buses in the design
wire [2:0] binary;
wire so0;
wire so1;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_3bcntr";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net150 = net152 ^ binary[2];
assign net147 = binary[0] ^ binary[1];
assign net144 = vcc_aibcraux ^ binary[0];
assign net065 = scanmoden ? clk : scanclk;
assign net064 = scanmoden ? clk : scanclk;
assign net063 = scanmoden ? clk : scanclk;
assign net152 = ~net151;
assign net151 = ~(binary[1] & binary[0]);
assign scanshftn = scan_shift_n;
assign scanin = scan_in;
assign scanmoden = scan_mode_n;
assign scanrstn = scan_rst_n;
assign scanclk = scan_clk;
assign bin_cnt[2:0] = binary[2:0];
aibcr3aux_osc_ff x8 ( .cdn(net017), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(binary[0]), .so(so0), .cp(net064), .d(net144),
.se_n(scanshftn), .si(scanin));
aibcr3aux_osc_ff x18 ( .cdn(net017), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(binary[2]), .so(scan_out), .cp(net065), .d(net150),
.se_n(scanshftn), .si(so1));
aibcr3aux_osc_ff x16 ( .cdn(net017), .vbb(vss_aibcraux),
.vss(vss_aibcraux), .vdd(vcc_aibcraux), .vpp(vcc_aibcraux),
.q(binary[1]), .so(so1), .cp(net063), .d(net147),
.se_n(scanshftn), .si(so0));
assign net017 = scanmoden ? rstb : scanrstn;
endmodule |
module aibcr3aux_osc_sync_ff ( Q, so,
CDN, CP, D, se_n, si );
output Q, so;
//inout inh_BN, inh_BP, inh_VN, inh_VP;
input CDN, CP, D, se_n, si;
wire net95, se_n, so, Q;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_sync_ff";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net95 = ~se_n;
aibcr3_sync_3ff xsync0 ( .SE(net95), .D(D), .Q(Q), .CP(CP), .SI(si), .CDN(CDN));
assign so = Q;
endmodule |
module aibcr3_clkbuf ( out, vcc_pl, vss_pl, in );
output out;
inout vcc_pl, vss_pl;
input in;
// List of primary aliased buses
//FIXIT in CASE 405142:
assign out = ~in;
/*
sa_invg8_ulvt xinv1_1_ ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out),
.in(in));
sa_invg8_ulvt xinv1_0_ ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out),
.in(in));
*/
endmodule |
module aibcr3aux_osc_dly ( clkout, q, scan_out, clk, rstb, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n, vcc_aibcr3aux,
vss_aibcr3aux );
output clkout, q, scan_out;
input clk, rstb, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n, vcc_aibcr3aux, vss_aibcr3aux;
wire net060, scan_rst_n, net059, rstb, net28, scan_clk, se_n, scan_shift_n, scanmodn, scan_mode_n, cdn, net30, net27, clk, cp, clkout;
wire net45;
wire net46;
wire net32;
wire net31;
wire net34;
wire net33;
wire net35;
wire net36;
wire net42;
wire net41;
wire net44;
wire net43;
wire net39;
wire net40;
wire net38;
wire net37;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_osc_dly";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_osc_ff x12 ( .cdn(vss_aibcr3aux), .vbb(vss_aibcr3aux),
.vss(vss_aibcr3aux), .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux),
.q(net45), .so(net46), .cp(vss_aibcr3aux), .d(vss_aibcr3aux),
.se_n(vss_aibcr3aux), .si(vss_aibcr3aux));
aibcr3aux_osc_ff x11 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(q), .so(scan_out),
.cdn(cdn), .cp(cp), .d(net32), .se_n(se_n), .si(net31));
aibcr3aux_osc_dly_unit x10 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net32), .so(net31),
.cdn(cdn), .cp(cp), .d(net34), .se_n(se_n), .si(net33));
aibcr3aux_osc_dly_unit x9 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net34), .so(net33),
.cdn(cdn), .cp(cp), .d(net35), .se_n(se_n), .si(net36));
aibcr3aux_osc_dly_unit x5 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net42), .so(net41),
.cdn(cdn), .cp(cp), .d(net44), .se_n(se_n), .si(net43));
aibcr3aux_osc_dly_unit x6 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net39), .so(net40),
.cdn(cdn), .cp(cp), .d(net42), .se_n(se_n), .si(net41));
aibcr3aux_osc_dly_unit x7 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net38), .so(net37),
.cdn(cdn), .cp(cp), .d(net39), .se_n(se_n), .si(net40));
aibcr3aux_osc_dly_unit x8 ( .vbb(vss_aibcr3aux), .vss(vss_aibcr3aux),
.vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux), .q(net35), .so(net36),
.cdn(cdn), .cp(cp), .d(net38), .se_n(se_n), .si(net37));
aibcr3aux_osc_dly_unit x0 ( .cdn(cdn), .vbb(vss_aibcr3aux),
.vss(vss_aibcr3aux), .vdd(vcc_aibcr3aux), .vpp(vcc_aibcr3aux),
.q(net44), .so(net43), .cp(cp), .d(vcc_aibcr3aux), .se_n(se_n),
.si(scan_in));
assign net060 = scan_rst_n;
assign net059 = rstb;
assign net28 = scan_clk;
assign se_n = scan_shift_n;
assign scanmodn = scan_mode_n;
assign cdn = scanmodn ? net059 : net060;
assign net30 = scanmodn ? net27 : net28;
assign net27 = ~clk;
assign cp = net30;
assign clkout = ~cp;
endmodule |
module aibcr3aux_actred ( jtag_rx_scan_out_01x1, jtag_rx_scan_out_01x2,
last_bs_out_01x1, last_bs_out_01x2, iopad_actred_chain1,
iopad_actred_chain2, actred_chain1, actred_chain2,
actred_shiften_chain1, actred_shiften_chain2, anlg_rstb,
csr_actred_dataselb, csr_actred_ndrv, csr_actred_pdrv,
csr_actred_txen, dig_rstb, jtag_clkdr5l, jtag_clkdr6l,
jtag_clksel, jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scan_in_01x1, jtag_tx_scan_in_01x2, jtag_tx_scanen_in,
jtag_weakpdn, jtag_weakpu, last_bs_in_01x1, last_bs_in_01x2,
por_vcchssi, por_vccl, vcc_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux
);
output jtag_rx_scan_out_01x1, jtag_rx_scan_out_01x2, last_bs_out_01x1,
last_bs_out_01x2;
inout iopad_actred_chain1, iopad_actred_chain2;
input actred_chain1, actred_chain2, actred_shiften_chain1,
actred_shiften_chain2, anlg_rstb, csr_actred_dataselb,
csr_actred_txen, dig_rstb, jtag_clkdr5l, jtag_clkdr6l,
jtag_clksel, jtag_intest, jtag_mode_in, jtag_rstb, jtag_rstb_en,
jtag_tx_scan_in_01x1, jtag_tx_scan_in_01x2, jtag_tx_scanen_in,
jtag_weakpdn, jtag_weakpu, last_bs_in_01x1, last_bs_in_01x2,
por_vcchssi, por_vccl, vcc_aibcr3aux, vccl_aibcr3aux, vssl_aibcr3aux;
input [1:0] csr_actred_ndrv;
input [1:0] csr_actred_pdrv;
wire net026;
wire net089;
wire net072;
wire net073;
wire net074;
wire net075;
wire net053;
wire net076;
wire net088;
wire net025;
wire net087;
wire net086;
wire net084;
wire net085;
wire net083;
wire net024;
wire net096;
wire net078;
wire net079;
wire net080;
wire net081;
wire net097;
wire net082;
wire net095;
wire net023;
wire net094;
wire net093;
wire net091;
wire net092;
wire net090;
wire net031;
wire net032;
wire net033;
wire net030;
wire net029;
wire net028;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_actred";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3_buffx1_top xio_in0 ( .idata1_in1_jtag_out(net031),
.idata0_in1_jtag_out(net032), .async_dat_in1_jtag_out(net033),
.prev_io_shift_en(actred_shiften_chain1),
.jtag_clkdr_outn(net026), .vssl(vssl_aibcr3aux),
.vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux), .por_aib_vccl(por_vccl),
.por_aib_vcchssi(por_vcchssi), .jtag_clksel(jtag_clksel),
.jtag_intest(jtag_intest), .jtag_rstb_en(jtag_rstb_en),
.anlg_rstb(anlg_rstb), .pd_data_aib(net089), .oclk_out(net072),
.oclkb_out(net073), .odat0_out(net074), .odat1_out(net075),
.odat_async_out(net053), .pd_data_out(net076),
//.async_dat_in0(vssl_aibcr3aux), .async_dat_in1(actred_chain2),
.async_dat_in0(vssl_aibcr3aux), .async_dat_in1(actred_chain1),
.iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
.idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
.idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
.idataselb_in0(vssl_aibcr3aux),
.idataselb_in1(csr_actred_dataselb), .iddren_in0(vssl_aibcr3aux),
.iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
.ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
.ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
.ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
vssl_aibcr3aux}), .indrv_in1(csr_actred_ndrv[1:0]),
.ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in1(csr_actred_pdrv[1:0]), .irxen_in0({vssl_aibcr3aux,
vcc_aibcr3aux, vssl_aibcr3aux}), .irxen_in1({vssl_aibcr3aux,
vcc_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
.istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
.itxen_in1(csr_actred_txen), .oclk_in1(vssl_aibcr3aux),
.odat_async_aib(net088), .oclkb_in1(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(actred_shiften_chain1),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net025), .odat1_aib(net087),
.jtag_rx_scan_out(jtag_rx_scan_out_01x2), .odat0_aib(net086),
.oclk_aib(net084), .last_bs_out(last_bs_out_01x2),
.oclkb_aib(net085), .jtag_clkdr_in(jtag_clkdr5l),
.jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb),
.jtag_tx_scan_in(jtag_tx_scan_in_01x2),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.last_bs_in(last_bs_in_01x2), .iopad(iopad_actred_chain2),
.oclkn(net083), .iclkn(vssl_aibcr3aux), .test_weakpu(jtag_weakpu),
.test_weakpd(jtag_weakpdn));
aibcr3_buffx1_top xio_in1 ( .idata1_in1_jtag_out(net030),
.idata0_in1_jtag_out(net029), .async_dat_in1_jtag_out(net028),
.prev_io_shift_en(actred_shiften_chain2),
.jtag_clkdr_outn(net024), .vssl(vssl_aibcr3aux),
.vccl(vccl_aibcr3aux), .vcc(vcc_aibcr3aux), .por_aib_vccl(por_vccl),
.por_aib_vcchssi(por_vcchssi), .jtag_clksel(jtag_clksel),
.jtag_intest(jtag_intest), .jtag_rstb_en(jtag_rstb_en),
.anlg_rstb(anlg_rstb), .pd_data_aib(net096), .oclk_out(net078),
.oclkb_out(net079), .odat0_out(net080), .odat1_out(net081),
.odat_async_out(net097), .pd_data_out(net082),
//.async_dat_in0(vssl_aibcr3aux), .async_dat_in1(actred_chain1),
.async_dat_in0(vssl_aibcr3aux), .async_dat_in1(actred_chain2),
.iclkin_dist_in0(vssl_aibcr3aux), .iclkin_dist_in1(vssl_aibcr3aux),
.idata0_in0(vssl_aibcr3aux), .idata0_in1(vssl_aibcr3aux),
.idata1_in0(vssl_aibcr3aux), .idata1_in1(vssl_aibcr3aux),
.idataselb_in0(vssl_aibcr3aux),
.idataselb_in1(csr_actred_dataselb), .iddren_in0(vssl_aibcr3aux),
.iddren_in1(vssl_aibcr3aux), .ilaunch_clk_in0(vssl_aibcr3aux),
.ilaunch_clk_in1(vssl_aibcr3aux), .ilpbk_dat_in0(vssl_aibcr3aux),
.ilpbk_dat_in1(vssl_aibcr3aux), .ilpbk_en_in0(vssl_aibcr3aux),
.ilpbk_en_in1(vssl_aibcr3aux), .indrv_in0({vssl_aibcr3aux,
vssl_aibcr3aux}), .indrv_in1(csr_actred_ndrv[1:0]),
.ipdrv_in0({vssl_aibcr3aux, vssl_aibcr3aux}),
.ipdrv_in1(csr_actred_pdrv[1:0]), .irxen_in0({vssl_aibcr3aux,
vcc_aibcr3aux, vssl_aibcr3aux}), .irxen_in1({vssl_aibcr3aux,
vcc_aibcr3aux, vssl_aibcr3aux}), .istrbclk_in0(vssl_aibcr3aux),
.istrbclk_in1(vssl_aibcr3aux), .itxen_in0(vssl_aibcr3aux),
.itxen_in1(csr_actred_txen), .oclk_in1(vssl_aibcr3aux),
.odat_async_aib(net095), .oclkb_in1(vssl_aibcr3aux),
.odat0_in1(vssl_aibcr3aux), .odat1_in1(vssl_aibcr3aux),
.odat_async_in1(vssl_aibcr3aux), .shift_en(actred_shiften_chain2),
.pd_data_in1(vssl_aibcr3aux), .dig_rstb(dig_rstb),
.jtag_clkdr_out(net023), .odat1_aib(net094),
.jtag_rx_scan_out(jtag_rx_scan_out_01x1), .odat0_aib(net093),
.oclk_aib(net091), .last_bs_out(last_bs_out_01x1),
.oclkb_aib(net092), .jtag_clkdr_in(jtag_clkdr6l),
.jtag_mode_in(jtag_mode_in), .jtag_rstb(jtag_rstb),
.jtag_tx_scan_in(jtag_tx_scan_in_01x1),
.jtag_tx_scanen_in(jtag_tx_scanen_in),
.last_bs_in(last_bs_in_01x1), .iopad(iopad_actred_chain1),
.oclkn(net090), .iclkn(vssl_aibcr3aux), .test_weakpu(jtag_weakpu),
.test_weakpd(jtag_weakpdn));
endmodule |
module aibcr3aux_osc_monitor ( out_divby16, out_divby32, out_divby64,
scan_out, vcc_aibcr3aux, vss_aibcr3aux, clkin, por, scan_clk,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n );
output out_divby16, out_divby32, out_divby64, scan_out;
inout vcc_aibcr3aux, vss_aibcr3aux;
input clkin, por, scan_clk, scan_in, scan_mode_n, scan_rst_n,
scan_shift_n;
wire s0;
wire net30;
wire net31;
wire divby8;
// specify
// specparam CDS_LIBNAME = "aibcr3aux_lib";
// specparam CDS_CELLNAME = "aibcr3aux_osc_monitor";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
aibcr3aux_osc_divby8 xdiv8_1 ( .scan_shift_n(scan_shift_n),
.scan_out(s0), .scan_clk(scan_clk), .scan_in(scan_in),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
.out_divby2(net30), .out_divby4(net31), .out_divby8(divby8),
.clkin(clkin), .por(por));
aibcr3aux_osc_divby8 xdiv8_2 ( .scan_shift_n(scan_shift_n),
.scan_out(scan_out), .scan_clk(scan_clk), .scan_in(s0),
.scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.vss_aibcr3aux(vss_aibcr3aux), .vcc_aibcr3aux(vcc_aibcr3aux),
.out_divby2(out_divby16), .out_divby4(out_divby32),
.out_divby8(out_divby64), .clkin(divby8), .por(por));
endmodule |
module aibcr3aux_lvshift_1p8 ( out1p8, vccl_aibcr3aux, vcca_aibcr3aux, vssl_aibcr3aux, in);
output out1p8;
input vccl_aibcr3aux, vcca_aibcr3aux, vssl_aibcr3aux;
input in;
reg out1p8;
//wire NET58 , in_shift , in_shiftb , inb , in_sw , NET59 ;
//no vccl_aibcr3aux, vcca_aibcr3aux and vssl_aibcr3aux tracking as of now.
always @ (in, vccl_aibcr3aux, vcca_aibcr3aux)
begin
if (vccl_aibcr3aux == 1'b0 && vcca_aibcr3aux == 1'b0)
begin
out1p8 = 1'b0;
end
else if (vccl_aibcr3aux == 1'b0 && vcca_aibcr3aux == 1'b1)
begin
out1p8 = 1'b1;
end
else if (vccl_aibcr3aux == 1'b1 && vcca_aibcr3aux == 1'b0)
begin
out1p8 = 1'b0;
end
else if (vccl_aibcr3aux == 1'b1 && vcca_aibcr3aux == 1'b1)
begin
out1p8 = in;
end
else
begin
out1p8 = 1'bx;
end
end
endmodule |
module aibcr3aux_osc_clkmux ( out, vcc_aibcraux, vss_aibcraux, ina, inb,
sel );
output out;
inout vcc_aibcraux, vss_aibcraux;
input ina, inb, sel;
wire net66, ina, net64, net010, net65, sel, inb, out;
// specify
// specparam CDS_LIBNAME = "aibcraux_lib";
// specparam CDS_CELLNAME = "aibcraux_osc_clkmux";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net66 = ~(ina & net64);
assign net010 = ~(net66 & net65);
assign net65 = ~(sel & inb);
assign net64 = ~sel;
assign out = net010;
endmodule |
module aibcr3pnr_dll_pnr
#(
//-----------------------------------------------------------------------------------------------------------------------
// Local calculated parameters
//-----------------------------------------------------------------------------------------------------------------------
parameter FF_DELAY = 200
)
(
input wire [2:0] core_dll, // input from core to dll; DFT pins
input wire clk_pll, // incoming clock, used to clock FSM
input [51:0] csr_reg, // AVMM bits from AIB adapter
input wire reinit, // initialization enable
input wire entest, // test enable
input wire t_up, // output of phase detector outside of this RTL block
input wire t_down, // output of phase detector outside of this RTL block
output wire launch, // Decode from gate_shf, Used as the input to the delay line
output wire measure, // Decode from gate_shf, Used as the clock for the phase detector
output wire [7:0] f_gray, // gray code for nand delay chain, which is the coarse delay chain; increase to 8 bits
output wire [2:0] i_gray, // gray code for phase interpolator, which is the fine delay chain
output wire [12:0] dll_core, // output from dll to core; DFT pins
output wire [10:0] pvt_ref_gry, // filtered delay setting from dll, representing 1-clock-cycle worth of delay; increase to 11 bits
output wire [10:0] pvt_ref_half_gry, // filtered delay setting from dll, representing 1/2-cycle worth of delay; increase to 11 bits
output wire dll_phdet_reset_n, //
output wire dll_lock,
output wire [6:0] gate_shf, // for synchronizing purpose
input wire test_clk_pll_en_n, // ATPG :
input wire [2:0] rb_clkdiv,
input wire rb_selflock,
input wire rb_half_code,
input wire pipeline_global_en,
input wire scan_mode_n,
input wire scan_shift_n,
input wire scan_rst_n,
input wire scan_clk_in,
input wire scan_in,
output wire scan_out
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
//----------------------------------------------------------------------------------------------------------------------------------------------------------------
//--- wire & reg -------------------------------------------------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------------------------------------------------------------
wire clk_pll_gated;
wire clk_pll_gated_tmux;
wire clk_pll_tmux;
wire reset_n_tmux;
// reg clk_pll_obs;
// reg reset_n_obs;
wire rb_dll_rst_en;
wire rb_dll_en;
wire rb_ndllrst_prgmnvrt;
wire rb_core_up_prgmnvrt;
wire rb_core_dn_prgmnvrt;
wire rb_core_updnen;
wire rb_spare;
wire [10:0] rb_dly_pst; // increase to 11 bits
wire rb_ctlsel;
wire [10:0] rb_ctl_static; // increase to 11 bits
wire [21:0] rb_dftmuxsel;
// wire [3:0] rb_new_dll;
wire core_up_in;
wire core_dn_in;
wire [10:0] pvt_ref_binary; // increase to 11 bits
wire [10:0] internal_pvt_binary; // binary pvt value for dll internal delay chain; increae to 11 bits
wire search_overflow;
wire [3:0] gate_state;
reg [10:0] dll_dftout;
wire up_core;
wire dn_core;
wire core_up;
wire core_dn;
wire ndllrst;
wire ndllrst_in;
wire dll_reset_n;
wire test_clk_en;
// wire test_clk_gated;
wire scan_shift;
//========================================================================================================================================================================
// test_clk muxes
//========================================================================================================================================================================
assign test_clk_en = ~test_clk_pll_en_n;
assign scan_shift = ~scan_shift_n;
/* aibcrpnr_dll_atech_clkgate_cgc00 gated_clk_pll_inst
(
.clk (clk_pll),
.en (1'b1),
.clkout (clk_pll_gated)
);
*/
assign clk_pll_gated = clk_pll; // replace the clock gating cell with buffer, since the en is always 1b'1
//aibcrpnr_dll_atech_clkgate_cgc01 gated_test_clk_inst
/*
Removed after discussion with DFT team (Joseph)
c3lib_ckg_posedge_ctn gated_test_clk_inst
(
.tst_en (scan_shift),
.clk_en (test_clk_en),
.clk (scan_clk_in),
.gated_clk (test_clk_gated)
);
*/
// aibcrpnr_dll_atech_clkmux muxed_pll_gated_inst
c3lib_mux2_ctn muxed_pll_gated_inst
(
.ck0 (scan_clk_in),
.ck1 (clk_pll_gated),
.s0 (scan_mode_n),
.ck_out (clk_pll_gated_tmux)
);
// aibcrpnr_dll_atech_clkmux muxed_pll_inst
c3lib_mux2_ctn muxed_pll_inst
(
.ck0 (scan_clk_in),
.ck1 (clk_pll),
.s0 (scan_mode_n),
.ck_out (clk_pll_tmux)
);
assign dll_phdet_reset_n = scan_mode_n ? reset_n_tmux : 1'b0 ;
//always @(posedge scan_clk_in) clk_pll_obs <= #FF_DELAY clk_pll;
//always @(posedge scan_clk_in) reset_n_obs <= #FF_DELAY reset_n_tmux;
//========================================================================================================================================================================
//end csr for phase alignment
//========================================================================================================================================================================
assign rb_dll_rst_en = csr_reg[0]; //core reset enable
assign rb_dll_en = csr_reg[1]; //dll enable
assign rb_ndllrst_prgmnvrt = csr_reg[2]; //core reset signal programmable inv
assign rb_core_up_prgmnvrt = csr_reg[3]; //core_up signal programmable inv
assign rb_core_dn_prgmnvrt = csr_reg[4]; //core_dn signal programmable inv
assign rb_core_updnen = csr_reg[5]; //core updown control enable
assign rb_dly_pst[10:0] = csr_reg[16:6]; //delay preset setting; change - increase 1 bit
assign rb_ctlsel = csr_reg[17]; //dll setting selection
assign rb_ctl_static[10:0] = {csr_reg[50],csr_reg[27:18]}; //dll static setting; Crete 3 change - increase 1 bit
assign rb_dftmuxsel[21:0] = csr_reg[49:28]; //dft mux selection; change - change from [19:0] to [21:0]
assign rb_spare = csr_reg[51]; //Not used
// assign rb_new_dll[3:0] = csr_reg[51:48];
assign core_up = core_dll[0];
assign core_dn = core_dll[1];
assign ndllrst = core_dll[2];
always @(*)
case (rb_dftmuxsel[21:20]) // change - add 2 csr bits to observe bit[10]
2'b00 : dll_dftout[10] = pvt_ref_half_gry[10];
2'b01 : dll_dftout[10] = pvt_ref_binary[10];
2'b10 : dll_dftout[10] = internal_pvt_binary[10];
2'b11 : dll_dftout[10] = 1'b0;
default : dll_dftout[10] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[19:18])
2'b00 : dll_dftout[9] = pvt_ref_half_gry[9];
2'b01 : dll_dftout[9] = pvt_ref_binary[9];
2'b10 : dll_dftout[9] = internal_pvt_binary[9];
2'b11 : dll_dftout[9] = 1'b0;
default : dll_dftout[9] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[17:16])
2'b00 : dll_dftout[8] = pvt_ref_half_gry[8];
2'b01 : dll_dftout[8] = pvt_ref_binary[8];
2'b10 : dll_dftout[8] = internal_pvt_binary[8];
2'b11 : dll_dftout[8] = 1'b0;
default : dll_dftout[8] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[15:14])
2'b00 : dll_dftout[7] = pvt_ref_half_gry[7];
2'b01 : dll_dftout[7] = pvt_ref_binary[7];
2'b10 : dll_dftout[7] = internal_pvt_binary[7];
2'b11 : dll_dftout[7] = 1'b0;
default : dll_dftout[7] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[13:12])
2'b00 : dll_dftout[6] = pvt_ref_half_gry[6];
2'b01 : dll_dftout[6] = pvt_ref_binary[6];
2'b10 : dll_dftout[6] = internal_pvt_binary[6];
2'b11 : dll_dftout[6] = 1'b0;
default : dll_dftout[6] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[11:10])
2'b00 : dll_dftout[5] = pvt_ref_half_gry[5];
2'b01 : dll_dftout[5] = pvt_ref_binary[5];
2'b10 : dll_dftout[5] = internal_pvt_binary[5];
2'b11 : dll_dftout[5] = gate_state[3];
default : dll_dftout[5] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[9:8])
2'b00 : dll_dftout[4] = pvt_ref_half_gry[4];
2'b01 : dll_dftout[4] = pvt_ref_binary[4];
2'b10 : dll_dftout[4] = internal_pvt_binary[4];
2'b11 : dll_dftout[4] = gate_state[2];
default : dll_dftout[4] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[7:6])
2'b00 : dll_dftout[3] = pvt_ref_half_gry[3];
2'b01 : dll_dftout[3] = pvt_ref_binary[3];
2'b10 : dll_dftout[3] = internal_pvt_binary[3];
2'b11 : dll_dftout[3] = gate_state[1];
default : dll_dftout[3] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[5:4])
2'b00 : dll_dftout[2] = pvt_ref_half_gry[2];
2'b01 : dll_dftout[2] = pvt_ref_binary[2];
2'b10 : dll_dftout[2] = internal_pvt_binary[2];
2'b11 : dll_dftout[2] = gate_state[0];
default : dll_dftout[2] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[3:2])
2'b00 : dll_dftout[1] = pvt_ref_half_gry[1];
2'b01 : dll_dftout[1] = pvt_ref_binary[1];
2'b10 : dll_dftout[1] = internal_pvt_binary[1];
2'b11 : dll_dftout[1] = search_overflow;
default : dll_dftout[1] = 1'b0;
endcase
always @(*)
case (rb_dftmuxsel[1:0])
2'b00 : dll_dftout[0] = pvt_ref_half_gry[0];
2'b01 : dll_dftout[0] = pvt_ref_binary[0];
2'b10 : dll_dftout[0] = internal_pvt_binary[0];
2'b11 : dll_dftout[0] = reset_n_tmux;
default : dll_dftout[0] = 1'b0;
endcase
assign dll_core[12] = dn_core;
// assign dll_core[11] = up_core;
assign dll_core[11] = scan_mode_n ? dll_lock : clk_pll_gated; //dft request; change - change from [10] to [11]
assign dll_core[10:0] = dll_dftout; //change - [10] is now for delay code[10] observability
assign ndllrst_in = (rb_ndllrst_prgmnvrt) ? ~ndllrst : ndllrst; //core reset
assign core_up_in = (rb_core_up_prgmnvrt) ? ~core_up : core_up; //core up signal
assign core_dn_in = (rb_core_dn_prgmnvrt) ? ~core_dn : core_dn; //core dn signal
aibcr3pnr_dll_ctrl xdll_ctrl (
.clk(clk_pll_tmux),
.reinit(reinit),
.entest(entest),
.ndllrst_in(ndllrst_in),
.rb_dll_en(rb_dll_en),
.rb_dll_rst_en(rb_dll_rst_en),
.atpg_en_n(scan_mode_n),
.test_clr_n(scan_rst_n),
.dll_reset_n(reset_n_tmux)
);
//t_up and t_down synchronization
wire t_up_sync,t_down_sync;
//hd_dpcmn_bitsync3 xsync_tup ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_up), .data_out(t_up_sync) );
//hd_dpcmn_bitsync3 xsync_tdown ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_down), .data_out(t_down_sync) );
c3lib_sync3_ulvt_bitsync xsync_tup ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_up), .data_out(t_up_sync) );
c3lib_sync3_ulvt_bitsync xsync_tdown ( .rst_n(reset_n_tmux), .clk(clk_pll_gated_tmux), .data_in(t_down), .data_out(t_down_sync) );
aibcr3pnr_dll_core xdll_core (
.clk ( clk_pll_gated_tmux ),
.reset_n ( reset_n_tmux ),
.rb_ctlsel ( rb_ctlsel ),
.rb_ctl_static ( rb_ctl_static[10:0] ),
.rb_core_updnen ( rb_core_updnen ),
.rb_clkdiv ( rb_clkdiv[2:0] ),
.rb_selflock ( rb_selflock ),
.rb_half_code ( rb_half_code ),
.rb_dly_pst ( rb_dly_pst[10:0] ),
.core_up ( core_up_in ),
.core_dn ( core_dn_in ),
.t_up ( t_up_sync ),
.t_down ( t_down_sync ),
.launch ( launch ),
.measure ( measure ),
.f_gray ( f_gray[7:0] ),
.i_gray ( i_gray[2:0] ),
.up_core ( up_core ),
.dn_core ( dn_core ),
.scan_mode_n ( scan_mode_n ),
.lock ( dll_lock ),
.pvt_ref_binary ( pvt_ref_binary[10:0] ),
.internal_pvt_binary ( internal_pvt_binary[10:0] ),
.search_overflow ( search_overflow ),
.gate_state ( gate_state[3:0] ),
.gate_shf ( gate_shf[6:0] ),
.pvt_ref_gry ( pvt_ref_gry[10:0] ),
.pvt_ref_half_gry ( pvt_ref_half_gry[10:0] )
);
endmodule // aibcr3pnr_dll_pnr |
module aibcr3pnr_self_lock_assertion
#(
parameter FF_DELAY = 200
)
(
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [2:0] rb_clkdiv, //select division factor for clock
input wire rb_selflock, //select between lock signal from self-timed logics or FSM lock monitor
input wire fsm_lock, //lock signal from FSM lock monitor
input wire scan_mode_n,
output wire prelock, //prelock signal for fast binary search
output wire lock //lock signal to core
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
wire clkdiv_2, clkdiv_4, clkdiv_8, clkdiv_16, clkdiv_32, clkdiv_64;
wire clkdiv_128, clkdiv_256, clkdiv_512, clkdiv_1024;
reg [7:0] cntr256;
reg pre_lock;
reg self_lock;
wire divclk;
reg [9:0] count1024;
always @(posedge clk or negedge reset_n)
begin
if(~reset_n) begin
count1024 <= #FF_DELAY 10'b0;
end
else
count1024 <= #FF_DELAY (count1024 == 10'b11111_11111)? 0 : count1024+1;
end
assign clkdiv_2 = count1024[0];
assign clkdiv_4 = count1024[1];
assign clkdiv_8 = count1024[2];
assign clkdiv_16 = count1024[3];
assign clkdiv_32 = count1024[4];
assign clkdiv_64 = count1024[5];
assign clkdiv_128 = count1024[6];
assign clkdiv_256 = count1024[7];
assign clkdiv_512 = count1024[8];
assign clkdiv_1024 = count1024[9];
/*
always @(posedge clk or negedge reset_n)
if (~reset_n) divclk <= #FF_DELAY 1'b0;
else case (rb_clkdiv)
3'b000 : divclk <= #FF_DELAY clkdiv_8; //div8 when rb_clkdiv=000
3'b001 : divclk <= #FF_DELAY clkdiv_16; //div16 when rb_clkdiv=001
3'b010 : divclk <= #FF_DELAY clkdiv_32; //div32 when rb_clkdiv=010
3'b011 : divclk <= #FF_DELAY clkdiv_64; //div64 when rb_clkdiv=011
3'b100 : divclk <= #FF_DELAY clkdiv_128; //div128 when rb_clkdiv=100
3'b101 : divclk <= #FF_DELAY clkdiv_256; //div256 when rb_clkdiv=101
3'b110 : divclk <= #FF_DELAY clkdiv_512; //div512 when rb_clkdiv=110
3'b111 : divclk <= #FF_DELAY clkdiv_1024; //div1024 when rb_clkdiv=111
default : divclk <= #FF_DELAY clkdiv_8;
endcase
*/
wire clk8_16,clk32_64,clk128_256,clk512_1024,clk8_16_32_64,clk128_256_512_1024;
/*aibcrpnr_dll_atech_clkmux clkmux_clk8_16
(
.clk1 (clkdiv_16),
.clk2 (clkdiv_8),
.s (rb_clkdiv[0]),
.clkout (clk8_16)
);
aibcrpnr_dll_atech_clkmux clkmux_clk32_64
(
.clk1 (clkdiv_64),
.clk2 (clkdiv_32),
.s (rb_clkdiv[0]),
.clkout (clk32_64)
);
aibcrpnr_dll_atech_clkmux clkmux_clk128_256
(
.clk1 (clkdiv_256),
.clk2 (clkdiv_128),
.s (rb_clkdiv[0]),
.clkout (clk128_256)
);
aibcrpnr_dll_atech_clkmux clkmux_clk512_1024
(
.clk1 (clkdiv_1024),
.clk2 (clkdiv_512),
.s (rb_clkdiv[0]),
.clkout (clk512_1024)
);
aibcrpnr_dll_atech_clkmux clkmux_clk8_16_32_64
(
.clk1 (clk32_64),
.clk2 (clk8_16),
.s (rb_clkdiv[1]),
.clkout (clk8_16_32_64)
);
aibcrpnr_dll_atech_clkmux clkmux_clk128_256_512_1024
(
.clk1 (clk512_1024),
.clk2 (clk128_256),
.s (rb_clkdiv[1]),
.clkout (clk128_256_512_1024)
);
*/
c3lib_mux4_ctn clkmux_clk8_16_32_64 // change
(
.ck0 (clkdiv_8),
.ck1 (clkdiv_16),
.ck2 (clkdiv_32),
.ck3 (clkdiv_64),
.s0 (rb_clkdiv[0]),
.s1 (rb_clkdiv[1]),
.ck_out (clk8_16_32_64)
);
c3lib_mux4_ctn clkmux_clk128_256_512_1024 // change
(
.ck0 (clkdiv_128),
.ck1 (clkdiv_256),
.ck2 (clkdiv_512),
.ck3 (clkdiv_1024),
.s0 (rb_clkdiv[0]),
.s1 (rb_clkdiv[1]),
.ck_out (clk128_256_512_1024)
);
//aibcrpnr_dll_atech_clkmux clkmux_divclk
c3lib_mux2_ctn clkmux_divclk_int // change
(
.ck0 (clk8_16_32_64),
.ck1 (clk128_256_512_1024),
.s0 (rb_clkdiv[2]),
.ck_out (divclk_int)
);
c3lib_mux2_ctn clkmux_divclk // change
(
.ck0 (clk),
.ck1 (divclk_int),
.s0 (scan_mode_n),
.ck_out (divclk)
);
always @(posedge divclk or negedge reset_n) begin
if (~reset_n) begin
cntr256 <= #FF_DELAY 8'b0000_0000;
pre_lock <= #FF_DELAY 1'b0;
self_lock <= #FF_DELAY 1'b0;
end
else if ((cntr256 >= 8'd0) & (cntr256 < 8'd150)) begin
cntr256 <= #FF_DELAY cntr256 + 8'b0000_0001;
end
else if ((cntr256 >= 8'd150) & (cntr256 < 8'd255)) begin
pre_lock <= #FF_DELAY 1'b1;
cntr256 <= #FF_DELAY cntr256 + 8'b0000_0001;
end
else begin
self_lock <= #FF_DELAY 1'b1;
end
end
wire lock_presync;
assign lock_presync = rb_selflock ? self_lock : fsm_lock;
//lock synchronization
//hd_dpcmn_bitsync2 prelock_sync ( .rst_n(reset_n), .clk(clk), .data_in(pre_lock), .data_out(prelock) );
//hd_dpcmn_bitsync2 lock_sync ( .rst_n(reset_n), .clk(clk), .data_in(lock_presync), .data_out(lock) );
c3lib_sync2_ulvt_bitsync prelock_sync ( .rst_n(reset_n), .clk(clk), .data_in(pre_lock), .data_out(prelock) );
c3lib_sync2_ulvt_bitsync lock_sync ( .rst_n(reset_n), .clk(clk), .data_in(lock_presync), .data_out(lock) );
endmodule // aibcr3pnr_self_lock_assertion |
module aibcr3pnr_half_cycle_code_gen
#(
parameter FF_DELAY = 200
)
(
input wire clk, //reference clock from pll
input wire reset_n, //output for dll reset
input wire [10:0] pvt_ref_binary, //output binary pvt value for delay chain; changed from [9:0] to [10:0]
input wire rb_half_code, //select between original or half cycle codes
output reg [10:0] pvt_ref_half_binary //half cycle code (binary) for delay chain; change from [9:0] to [10:0]
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
wire [7:0] coarse_bin; // change from [6:0] to [7:0]
wire [2:0] fint_bin, fint_bin_inc;
wire [2:0] fine_bin;
wire [8:0] coarse_divided_bin; // change from [7:0] to [8:0]
wire [3:0] fine_divided_bin, coarse_frac_bin;
assign coarse_divided_bin[8:0] = {1'b0,pvt_ref_binary[10:3]}; // changed from pvt_ref_binary[9:3] to [10:3]
assign fine_divided_bin[3:0] = {1'b0,pvt_ref_binary[2:0]};
assign coarse_frac_bin[3:0] = {coarse_divided_bin[0],3'b000};
assign fint_bin[2:0] = coarse_frac_bin[3:1] + fine_divided_bin[3:1];
assign fint_bin_inc[2:0] = ((fine_divided_bin[0] >= 1'd1) && (fint_bin < 3'd7)) ? fint_bin[2:0] + 3'b001 : fint_bin[2:0];
assign coarse_bin = coarse_divided_bin[8:1]; // change from [7:1] to [8:1]
assign fine_bin = fint_bin_inc;
always @(posedge clk or negedge reset_n)
begin
if(~reset_n) begin
pvt_ref_half_binary <= #FF_DELAY 11'b000_0000_0000;
end
else case (rb_half_code)
1'b0 : pvt_ref_half_binary <= #FF_DELAY pvt_ref_binary;
1'b1 : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
default : pvt_ref_half_binary <= #FF_DELAY {coarse_bin,fine_bin};
endcase
end
endmodule // aibcr3pnr_half_cycle_code_gen |
module aibcr3_2to4dec ( nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b,
psel_out0, psel_out1, psel_out2, psel_out3, vccl, vssl, enable,
nsel_in, psel_in );
output nsel_out0b, nsel_out1b, nsel_out2b, nsel_out3b, psel_out0,
psel_out1, psel_out2, psel_out3;
inout vccl, vssl;
input enable;
input [1:0] nsel_in;
input [1:0] psel_in;
wire nsel_out2b, enable, nsel_out3b, pserl_out3b, nsel1_en, psel0_en, psel0_enb, nsel_out0b, psel_out1, psel_out1b, nsel0_en, nsel0_enb, psel_out2, pserl_out2b, psel_out3, psel_out0, nsel_out1b;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_2to4dec";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign nsel_out2b = !(nsel_in[1] & enable);
assign nsel_out3b = !(enable & nsel_in[0] & nsel_in[1]);
assign pserl_out3b = !(enable & psel_in[0] & psel_in[1]);
assign nsel1_en = !nsel_out2b;
assign psel0_en = !psel0_enb;
assign nsel_out0b = !enable;
assign psel_out1 = !psel_out1b;
assign nsel0_en = !nsel0_enb;
assign psel_out2 = !pserl_out2b;
assign psel_out3 = !pserl_out3b;
assign psel_out0 = enable;
assign psel_out1b = !(psel0_en | psel_out2);
assign nsel_out1b = !(nsel0_en | nsel1_en);
assign pserl_out2b = !(psel_in[1] & enable);
assign nsel0_enb = !(nsel_in[0] & enable);
assign psel0_enb = !(psel_in[0] & enable);
endmodule |
module aibcr3_svt16_scdffsdn_cust ( Q, scQ, CK,
D, SDN, SE, SI );
output Q, scQ;
input SDN, CK, D, SE, SI;
wire Q, net023, se_n, SI, D;
reg scQ;
assign se_n = !SE;
assign Q = scQ;
assign net023 = se_n ? D : SI;
always@(posedge CK or negedge SDN) begin
if (!SDN) begin
scQ <= 1'b1;
end
else begin
scQ <= net023;
end
end
endmodule |
module aibcr3_dll_ibkmux ( SO_OUT, grey, igray, CK, RSTb,
SE, code_valid, si, sm_grey, sm_igray );
output SO_OUT;
input CK, RSTb, SE, code_valid, si;
output [2:0] igray;
output [6:0] grey;
input [6:0] sm_grey;
input [2:0] sm_igray;
wire code_valid_buf;
wire code_valid_sync;
assign tieHi = 1'b1;
assign net0101 = code_valid_buf? sm_grey[6] : grey[6];
assign net0100 = code_valid_buf? sm_grey[5] : grey[5];
assign net104 = code_valid_buf? sm_grey[4] : grey[4];
assign net107 = code_valid_buf? sm_grey[3] : grey[3];
assign net106 = code_valid_buf? sm_grey[2] : grey[2];
assign net108 = code_valid_buf? sm_grey[1] : grey[1];
assign net109 = code_valid_buf? sm_grey[0] : grey[0];
assign net0104 = code_valid_buf? sm_igray[2] : igray[2];
assign net0103 = code_valid_buf? sm_igray[1] : igray[1];
assign net0102 = code_valid_buf? sm_igray[0] : igray[0];
assign code_valid_buf = code_valid_sync;
assign SO0 = code_valid_sync;
aibcr3_svt16_scdffcdn_cust x25 ( igray[2], SO_OUT, RSTb,
CK, net0104, SE, SO9);
aibcr3_svt16_scdffcdn_cust x23 ( igray[1], SO9, RSTb, CK,
net0103, SE, SO8);
aibcr3_svt16_scdffcdn_cust x21 ( igray[0], SO8, RSTb, CK,
net0102, SE, SO7);
aibcr3_svt16_scdffcdn_cust x19 ( grey[6], SO7, RSTb, CK,
net0101, SE, SO6);
aibcr3_svt16_scdffcdn_cust x17 ( grey[5], SO6, RSTb, CK,
net0100, SE, SO5);
aibcr3_svt16_scdffcdn_cust x7 ( grey[4], SO5, RSTb, CK,
net104, SE, SO4);
aibcr3_svt16_scdffcdn_cust x6 ( grey[2], SO3, RSTb, CK,
net106, SE, SO2);
aibcr3_svt16_scdffcdn_cust x4 ( grey[3], SO4, RSTb, CK,
net107, SE, SO3);
aibcr3_svt16_scdffcdn_cust x2 ( grey[1], SO2, RSTb, CK,
net108, SE, SO1);
aibcr3_svt16_scdffcdn_cust I316 ( grey[0], SO1, RSTb, CK,
net109, SE, SO0);
aibcr3_ulvt16_2xarstsyncdff1_b2 I99 (
.Q(code_valid_sync), .CLR_N(RSTb), .CK(CK),
.SE(SE), .D(code_valid), .SI(si));
endmodule |
module aibcr3_dll_lock_dly ( SOoutd, dcc_done, dll_lock_reg,
RSTb, clk_dcd, dll_lock_mux, rb_cont_cal, scan_in,
scan_shift_n );
output SOoutd, dcc_done, dll_lock_reg;
input RSTb, clk_dcd, dll_lock_mux, rb_cont_cal, scan_in, scan_shift_n;
wire net50;
assign tieHI = 1'b1;
assign tieLO = 1'b0;
assign net079 = net50;
assign SE = !scan_shift_n;
assign dll_lock_reg = rb_cont_cal? tieLO : net079;
aibcr3_svt16_scdffcdn_cust I17 ( net53, net50, RSTb,
dll_lock_mux, tieHI, SE, scan_in);
aibcr3_svt16_scdffcdn_cust I13 ( net61, net60, RSTb,
clk_dcd, net53, SE, net50);
aibcr3_svt16_scdffcdn_cust I14 ( net69, net68, RSTb,
clk_dcd, net61, SE, net60);
aibcr3_svt16_scdffcdn_cust I4 ( net59, net54, RSTb,
clk_dcd, net42, SE, net45);
aibcr3_svt16_scdffcdn_cust I2 ( net67, net64, RSTb,
clk_dcd, net59, SE, net54);
aibcr3_svt16_scdffcdn_cust I1 ( net77, net74, RSTb,
clk_dcd, net67, SE, net64);
aibcr3_svt16_scdffcdn_cust I316 ( dcc_done, SOoutd, RSTb,
clk_dcd, net77, SE, net74);
aibcr3_svt16_scdffcdn_cust I15 ( net76, net75, RSTb,
clk_dcd, net69, SE, net68);
aibcr3_svt16_scdffcdn_cust I16 ( net42, net45, RSTb,
clk_dcd, net76, SE, net75);
endmodule |
module aibcr3_dll_dlyline64 ( a63, dlyout, b63, bk, dlyin, CLKIN, iSE, RSTb, iSI, SOOUT
);
output a63, dlyout, SOOUT;
input b63, dlyin, CLKIN, iSE, RSTb, iSI;
input [63:0] bk;
wire [62:0] a;
wire [62:0] b;
wire [62:0] so;
aibcr3_dlycell_dll UD00 [63:0] (
.in_p ( {a[62:0],dlyin} ),
.bk ( bk[63:0] ),
.ci_p ( {b63,b[62:0]} ),
.out_p ( {b[62:0], dlyout} ),
.co_p ( {a63,a[62:0]} ),
.ck ( CLKIN ),
.si ( {so[62:0],iSI} ),
.SE ( iSE ),
.RSTb ( RSTb ),
.so ( {SOOUT,so[62:0]} )
);
endmodule |
module aibcr3_ulvt16_dffcdn_cust (
input wire CK,
input wire CDN,
input wire D,
output reg Q
);
always@(posedge CK or negedge CDN) begin
if (!CDN) begin
Q <= 1'b0;
end
else begin
Q <= D;
end
end
endmodule |
module aibcr3_ulvt16_dffsdn_cust (
input wire CK,
input wire SDN,
input wire D,
output reg Q
);
always@(posedge CK or negedge SDN) begin
if (!SDN) begin
Q <= 1'b1;
end
else begin
Q <= D;
end
end
endmodule |
module aibcr3_str_ioload ( in, vcc, vssl );
input in, vcc, vssl;
// Buses in the design
wire net5;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_str_ioload";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign net5 = ~in ;
endmodule |
module aibcr3_rambit_buf ( sig_out, sig_in, vcc, vssl );
output sig_out;
input sig_in, vcc, vssl;
wire sig_out, sig_in;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_rambit_buf";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign sig_out = sig_in;
endmodule |
module aibcr3_clktree_mimic
#(
parameter SKEW_DELAY = 60 //min:20ps; typ :60ps; max:100ps
)
(
input wire clkin, //clock source
output wire lstrbclk_l_0, //buffered clock
output wire lstrbclk_l_1, //buffered clock
output wire lstrbclk_l_2, //buffered clock
output wire lstrbclk_l_3, //buffered clock
output wire lstrbclk_l_4, //buffered clock
output wire lstrbclk_l_5, //buffered clock
output wire lstrbclk_l_6, //buffered clock
output wire lstrbclk_l_7, //buffered clock
output wire lstrbclk_l_8, //buffered clock
output wire lstrbclk_l_9, //buffered clock
output wire lstrbclk_l_10, //buffered clock
output wire lstrbclk_l_11, //buffered clock
output wire lstrbclk_rep, //replica for DLL
output wire lstrbclk_mimic0 //mimic path for load matching
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
assign #SKEW_DELAY lstrbclk_l_0 = clkin;
assign #SKEW_DELAY lstrbclk_l_1 = clkin;
assign #SKEW_DELAY lstrbclk_l_2 = clkin;
assign #SKEW_DELAY lstrbclk_l_3 = clkin;
assign #SKEW_DELAY lstrbclk_l_4 = clkin;
assign #SKEW_DELAY lstrbclk_l_5 = clkin;
assign #SKEW_DELAY lstrbclk_l_6 = clkin;
assign #SKEW_DELAY lstrbclk_l_7 = clkin;
assign #SKEW_DELAY lstrbclk_l_8 = clkin;
assign #SKEW_DELAY lstrbclk_l_9 = clkin;
assign #SKEW_DELAY lstrbclk_l_10 = clkin;
assign #SKEW_DELAY lstrbclk_l_11 = clkin;
assign #SKEW_DELAY lstrbclk_rep = clkin;
assign #SKEW_DELAY lstrbclk_mimic0 = clkin;
endmodule // aibcr_clktree_mimic |
module aibcr3_io_cmos_8ph_interpolator (
input nfrzdrv,
input fout_p,
input fout_n,
input [2:0] gray,
output out_p,
output out_n,
output osc_out_p,
output osc_out_n
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
parameter NAND_DELAY = 20;
wire a_in_p;
wire b_in_p;
wire c_in_p;
wire a_in_n;
wire b_in_n;
wire c_in_n;
wire x_p;
wire x_n;
wire x_pb;
wire x_nb;
wire [6:0] sn;
reg [6:0] sp;
assign #(0 * NAND_DELAY) a_in_p = nfrzdrv? fout_p : 1'b0;
assign #(2 * NAND_DELAY) b_in_p = nfrzdrv? fout_p : 1'b0;
assign #(4 * NAND_DELAY) c_in_p = nfrzdrv? fout_p : 1'b0;
assign #(0 * NAND_DELAY) a_in_n = nfrzdrv? fout_n : 1'b1;
assign #(2 * NAND_DELAY) b_in_n = nfrzdrv? fout_n : 1'b1;
assign #(4 * NAND_DELAY) c_in_n = nfrzdrv? fout_n : 1'b1;
always @(*)
case (gray[2:0])
3'b000 : sp[6:0] = 7'b000_0000;
3'b001 : sp[6:0] = 7'b000_0001;
3'b011 : sp[6:0] = 7'b000_0011;
3'b010 : sp[6:0] = 7'b000_0111;
3'b110 : sp[6:0] = 7'b000_1111;
3'b111 : sp[6:0] = 7'b001_1111;
3'b101 : sp[6:0] = 7'b011_1111;
3'b100 : sp[6:0] = 7'b111_1111;
endcase
assign sn[6:0] = ~sp[6:0];
aibcr3_io_ip8phs x8phs_n (
.c_in ( {c_in_n, b_in_n, a_in_n} ),
.sp ( sp[6:0] ),
.sn ( sn[6:0] ),
.c_out ( x_n )
);
aibcr3_io_ip8phs x8phs_p (
.c_in ( {c_in_p, b_in_p, a_in_p} ),
.sp ( sp[6:0] ),
.sn ( sn[6:0] ),
.c_out ( x_p )
);
//cross couple
assign x_pb = ~x_p;
assign x_nb = ~x_n;
assign out_p = ~x_pb;
assign out_n = ~x_nb;
assign osc_out_p = ~x_pb;
assign osc_out_n = ~x_nb;
`ifdef LEC
assign x_p = ~x_n;
assign x_n = ~x_p;
`endif
endmodule |
module aibcr3_buffx1 ( oclk, oclkb, oclkn, odat0, odat1, odat_async,
pd_data, iopad, async_dat, clkdr, iclkin_dist,
iclkn, idat0, idat1, idataselb, iddren, ilaunch_clk, ilpbk_dat,
ilpbk_en, indrv, ipadrstb, ipdrv, irstb, irxen, istrbclk, itxen,
por_aib_vcc1, por_aib_vcchssi, test_weakpd, test_weakpu,
testmode_en);
output oclk, oclkb, oclkn, odat0, odat1, odat_async, pd_data;
inout iopad;
input async_dat, clkdr, iclkin_dist, iclkn, idat0, idat1, idataselb,
iddren, ilaunch_clk, ilpbk_dat, ilpbk_en, ipadrstb, irstb,
istrbclk, itxen, por_aib_vcc1, por_aib_vcchssi, test_weakpd,
test_weakpu, testmode_en;
input [1:0] ipdrv;
input [1:0] indrv;
input [2:0] irxen;
// Buses in the design
wire [1:0] ipdrv_buf;
wire [1:0] indrv_buf;
aibcr3_analog x0 ( oclkb, oclk, rx_idat, odat_async,
iopad, clkbuf_en, datbuf_en, iclkn, indrv_buf[1:0],
ipdrv_buf[1:0], itx_en_buf, por_aib_vcc1, por_aib_vcchssi, tx_dat,
weak_pulldownen, weak_pullupenb);
aibcr3_digital x1 ( clkbuf_en, datbuf_en, indrv_buf[1:0],
ipdrv_buf[1:0], itx_en_buf, odat0, odat1, pd_data, net18, net17,
net16, tx_dat, weak_pulldownen, weak_pullupenb,
async_dat, clkdr, iclkin_dist, idat0, idat1, idataselb, iddren,
ilaunch_clk, ilpbk_dat, ilpbk_en, indrv[1:0], ipadrstb,
ipdrv[1:0], irstb, irxen[2:0], istrbclk, itxen, rx_idat,
test_weakpd, test_weakpu, testmode_en);
/*
rm5xa R0 ( .PLUS(iopad), .MINUS(oclkn));
*/
assign oclkn = iopad;
endmodule |
module aibcr3_data_buf ( sig_out, sig_in, vcc, vssl );
output sig_out;
input sig_in, vcc, vssl;
wire sig_out, sig_in;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_data_buf";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign sig_out = sig_in;
endmodule |
module aibcr3_preclkbuf ( out, vcc_pl, vss_pl, in );
output out;
inout vcc_pl, vss_pl;
input in;
// specify
// specparam CDS_LIBNAME = "aibcr_lib";
// specparam CDS_CELLNAME = "aibcr_preclkbuf";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
//sa_invg8_ulvt xinv1 ( .vssesa(vss_pl), .vccesa(vcc_pl), .out(out), .in(in));
assign out = !in;
endmodule |
module aibcr3_dcc_dlyline64 ( a63, dlyout, b63, bk, dlyin
);
output a63, dlyout;
input b63, dlyin;
input [63:0] bk;
wire [62:0] a;
wire [62:0] b;
aibcr3_dlycell_dcc UD00 [63:0] (
.in_p ( {a[62:0],dlyin} ),
.bk ( bk[63:0] ),
.ci_p ( {b63,b[62:0]} ),
.out_p ( {b[62:0], dlyout} ),
.co_p ( {a63,a[62:0]} )
);
endmodule |
module aibcr3_red_custom_dig ( anlg_rstb_out, anlg_rstb,
prev_io_shift_en, shift_en );
output anlg_rstb_out;
input anlg_rstb, prev_io_shift_en, shift_en;
wire anlg_rst_nd_out;
wire io_disable_b;
assign anlg_rstb_out = !anlg_rst_nd_out;
assign prev_io_shenb = !prev_io_shift_en;
assign anlg_rst_nd_out = !(io_disable_b & anlg_rstb);
assign io_disable_b = !(prev_io_shenb & shift_en);
endmodule |
module aibcr3_dcc_dll ( clk_dcc, dcc_done, odll_dll2core, odll_lock,
pvt_ref_half_gry, scan_out, clk_dcd, clk_pll,
csr_reg, idll_core2dll, idll_entest, nfrzdrv, nrst,
pipeline_global_en, rb_clkdiv, rb_cont_cal, rb_dcc_byp,
rb_half_code, rb_selflock, reinit, scan_clk_in, scan_in,
scan_mode_n, scan_rst_n, scan_shift_n, test_clk_pll_en_n );
output clk_dcc, dcc_done, odll_lock, scan_out;
input clk_dcd, clk_pll, idll_entest, nfrzdrv, nrst,
pipeline_global_en, rb_cont_cal, rb_dcc_byp, rb_half_code,
rb_selflock, reinit, scan_clk_in, scan_in, scan_mode_n,
scan_rst_n, scan_shift_n, test_clk_pll_en_n;
output [12:0] odll_dll2core;
output [10:0] pvt_ref_half_gry;
input [2:0] idll_core2dll;
input [2:0] rb_clkdiv;
input [51:0] csr_reg;
// Buses in the design
wire [2:0] i_gray;
wire [10:0] pvt_ref_gry;
wire [7:0] f_gray;
wire [6:0] gate_shf;
wire dll_phdet_reset_n;
wire launch;
aibcr3_dll_custom I0 ( clk_dcc, dcc_done, so_dll_custom, t_down, t_up,
clk_dcd, odll_lock, dll_phdet_reset_n, f_gray[7:0],
i_gray[2:0], launch, measure, nfrzdrv, nrst,
pvt_ref_half_gry[10:0], rb_cont_cal, rb_dcc_byp, scan_clk_in,
scan_in, scan_mode_n, scan_rst_n, scan_shift_n);
aibcr3pnr_dll_pnr I1 ( .dll_core(odll_dll2core[12:0]), .dll_lock(odll_lock),
.dll_phdet_reset_n(dll_phdet_reset_n), .f_gray(f_gray[7:0]), .gate_shf(gate_shf[6:0]), .i_gray(i_gray[2:0]),
.launch (launch), .measure(measure), .pvt_ref_gry(pvt_ref_gry[10:0]), .pvt_ref_half_gry(pvt_ref_half_gry[10:0]),
.scan_out(scan_out), .clk_pll(clk_pll), .core_dll(idll_core2dll[2:0]), .csr_reg(csr_reg[51:0]), .entest(idll_entest),
.pipeline_global_en(pipeline_global_en), .rb_clkdiv(rb_clkdiv[2:0]), .rb_half_code(rb_half_code), .rb_selflock(rb_selflock),
.reinit(reinit), .scan_clk_in(scan_clk_in), .scan_in(so_dll_custom), .scan_mode_n(scan_mode_n), .scan_rst_n(scan_rst_n),
.scan_shift_n(scan_shift_n), .t_down(t_down), .t_up(t_up), .test_clk_pll_en_n(test_clk_pll_en_n));
endmodule |
module aibcr3_nd2d0_custom (zn, a1, a2, vcc_regphy, vss_io );
output zn;
input a2;
input a1;
input vss_io;
input vcc_regphy;
assign zn = ~(a1 && a2) ;
endmodule |
module aibcr3_dcc_top ( clk_dcc, dcc_done, odll_dll2core, scan_out,
clk_dcd, clktree_out, csr_reg, dcc_dft_nrst,
dcc_dft_nrst_coding, dcc_dft_up, dcc_req, idll_core2dll,
idll_entest, nfrzdrv, pipeline_global_en, rb_clkdiv, rb_cont_cal,
rb_dcc_byp, rb_dcc_dft, rb_dcc_dft_sel, rb_dcc_en,
rb_dcc_manual_dn, rb_dcc_manual_up, rb_half_code, rb_selflock,
scan_clk_in, scan_in, scan_mode_n, scan_rst_n, scan_shift_n,
test_clk_pll_en_n );
output clk_dcc, dcc_done, scan_out;
input clk_dcd, clktree_out, dcc_dft_nrst, dcc_dft_nrst_coding,
dcc_dft_up, dcc_req, idll_entest, nfrzdrv, pipeline_global_en,
rb_cont_cal, rb_dcc_byp, rb_dcc_dft, rb_dcc_dft_sel, rb_dcc_en,
rb_half_code, rb_selflock, scan_clk_in, scan_in, scan_mode_n,
scan_rst_n, scan_shift_n, test_clk_pll_en_n;
output [12:0] odll_dll2core;
input [2:0] rb_clkdiv;
input [4:0] rb_dcc_manual_up;
input [4:0] rb_dcc_manual_dn;
input [51:0] csr_reg;
input [2:0] idll_core2dll;
// Buses in the design
wire [10:0] pvt_ref_half_gry;
wire [12:0] dll2core;
wire so_nrst;
wire net0277;
wire net0274;
wire net0214;
wire buf_rb_dcc_en;
wire dcc_req_mux;
wire dcc_req_synced;
wire odll_lock;
wire buf_rb_dcc_byp;
wire net0275;
wire rb_dcc_byp_b;
wire dcc_done_nonbyp;
wire dcc_done_byp;
wire rb_dcc_en_b;
wire clk_prebuf;
wire net057;
wire dccen_dccreq;
wire net052;
wire clk_mindly_cont;
wire clk_mindly_1time;
wire net054;
wire clk_dly_cont;
wire clk_dly_1time;
assign tieHi = 1'b1;
assign tieLo = 1'b0;
assign so_nrst_dly = so_nrst;
assign net0288 = net0277;
assign scan_clk_in_buf = scan_clk_in;
assign dcc_done = net0274;
assign buf_rb_cont_cal = rb_cont_cal;
assign scan_out = net0214;
assign scan_in_buf = scan_in;
assign scan_mode_n_buf = scan_mode_n;
assign buf_rb_dcc_dft_sel = rb_dcc_dft_sel;
assign scan_rst_n_buf = scan_rst_n;
assign scan_shift_n_buf = scan_shift_n;
assign csr_reg6 = csr_reg[6];
assign nfrzdrv_nrst_b = !(nfrzdrv & buf_rb_dcc_en);
assign net0224 = !(tieLo & tieLo);
assign net0225 = !(tieLo & tieLo);
assign net0276 = !(dcc_req_mux & buf_rb_dcc_en);
assign reinit = !(dcc_req_synced & buf_rb_dcc_en);
assign odll_dll2core[12] = buf_rb_dcc_dft_sel ? tieLo : dll2core[12];
assign odll_dll2core[11] = buf_rb_dcc_dft_sel ? tieLo : dll2core[11];
assign odll_dll2core[10] = buf_rb_dcc_dft_sel ? tieLo : dll2core[10];
assign odll_dll2core[9] = buf_rb_dcc_dft_sel ? tieLo : dll2core[9];
assign odll_dll2core[8] = buf_rb_dcc_dft_sel ? tieLo : dll2core[8];
assign odll_dll2core[7] = buf_rb_dcc_dft_sel ? tieLo : dll2core[7];
assign odll_dll2core[6] = buf_rb_dcc_dft_sel ? tieLo : dll2core[6];
assign odll_dll2core[5] = buf_rb_dcc_dft_sel ? tieLo : dll2core[5];
assign odll_dll2core[4] = buf_rb_dcc_dft_sel ? tieLo : dll2core[4];
assign odll_dll2core[3] = buf_rb_dcc_dft_sel ? tieLo : dll2core[3];
assign odll_dll2core[2] = buf_rb_dcc_dft_sel ? tieLo : dll2core[2];
assign odll_dll2core[1] = buf_rb_dcc_dft_sel ? dcc_done : dll2core[1];
assign odll_dll2core[0] = buf_rb_dcc_dft_sel ? odll_lock : dll2core[0];
assign dll_lock_mux = scan_mode_n_buf ? odll_lock : scan_clk_in_buf;
assign dccen_dccreq_mux = scan_mode_n_buf ? dccen_dccreq : scan_rst_n_buf;
assign net0247 = scan_mode_n_buf ? dcc_req_synced : scan_rst_n; // net0247 was dcc_req_synced_mux in t20
assign net0277 = scan_mode_n_buf ? dcc_req_mux : scan_rst_n_buf;
assign dcc_req_mux = csr_reg6 ? idll_core2dll[2] : dcc_req;
assign dcc_byp_mux = csr_reg6 ? idll_core2dll[1] : buf_rb_dcc_byp;
assign nrst_coding = scan_mode_n_buf ? net0275 : scan_rst_n_buf;
assign net0274 = rb_dcc_byp_b ? dcc_done_nonbyp : dcc_done_byp;
assign net0226 = !tieLo;
assign net0242 = !tieLo;
assign net0228 = !tieLo;
assign net0223 = !tieLo;
assign net0221 = !scan_shift_n_buf;
assign net0248 = !scan_shift_n_buf;
assign buf_rb_dcc_en = !rb_dcc_en_b;
assign rb_dcc_en_b = !rb_dcc_en;
assign rb_dcc_byp_b = !rb_dcc_byp;
assign buf_rb_dcc_byp = !rb_dcc_byp_b;
assign nfrzdrv_nrst = !nfrzdrv_nrst_b;
assign so_sync = dcc_req_synced;
assign net0227 = !scan_shift_n_buf;
assign dccen_dccreq = !net0276;
assign clk_dcd_buf = clk_dcd;
assign clk_buf0 = clk_prebuf;
assign clk_prebuf = scan_mode_n_buf ? clk_dcd_buf : scan_clk_in_buf;
aibcr3_svt16_scdffcdn_cust I53 (.Q(dcc_done_byp), .scQ(so_dcc_done), .CDN(net0247), .CK(clk_buf0), .D(dcc_req_synced), .SE(net0248), .SI(so_nrst_dly));
aibcr3_svt16_scdffcdn_cust I48 (.Q(net0275), .scQ(so_nrst), .CDN(dccen_dccreq_mux), .CK(dll_lock_mux), .D(tieHi), .SE(net0227), .SI(so_sync));
aibcr3_dcc_dll I82 ( clk_dcc, dcc_done_nonbyp, dll2core[12:0],
odll_lock, pvt_ref_half_gry[10:0], net0214, clk_buf0,
clk_buf0, csr_reg[51:0], idll_core2dll[2:0], idll_entest,
nfrzdrv_nrst, nrst_coding, pipeline_global_en, rb_clkdiv[2:0],
buf_rb_cont_cal, dcc_byp_mux, rb_half_code, rb_selflock, reinit,
scan_clk_in_buf, so_dcc_done, scan_mode_n_buf, scan_rst_n_buf,
scan_shift_n_buf, test_clk_pll_en_n);
// 2-stage reset synchronization
aibcr3_ulvt16_2xarstsyncdff1_b2 I99 (.CLR_N(net0288), .CK(clk_buf0), .D(tieHi), .SE(net0221), .SI(scan_in_buf), .Q(dcc_req_synced));
endmodule |
module aibcr3_anaio_esd (osc_extrref);
inout osc_extrref;
endmodule |
module aibcr3_cmos_fine_dly (
input [2:0] gray,
input ck, fout_p, nrst, se_n, si,code_valid,
output so, out_p
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
wire pg0,ng0,pg1,ng1,pg2,ng2;
wire sp0,sn0,sp1,sn1,sp2,sn2,sp3,sn3,sp4,sn4,sp5,sn5,sp6,sn6,sp7,sn7;
wire sp1_a,sn1_a,sp2_a,sn2_a,sp3_a,sn3_a,sp4_a,sn4_a,sp5_a,sn5_a,sp6_a,sn6_a,sp7_a,sn7_a;
wire so0,so1,so2,so3,so4,so5,so6,so7,so8,so9,so10,so11,so12;
wire sp0_a;
wire sn0_a;
integer intrinsic, step, calc_delay, total_delay;
assign ng2 = ~gray[2];
assign pg2 = gray[2];
assign ng1 = ~gray[1];
assign pg1 = gray[1];
assign ng0 = ~gray[0];
assign pg0 = gray[0];
assign sp7_a = ~(pg2&ng1&ng0);
assign sn7_a = ~sp7_a;
assign sp6_a = ~((pg2&ng1&pg0) | sn7_a);
assign sn6_a = ~sp6_a;
assign sp5_a = ~((pg2&pg1&pg0) | sn6_a);
assign sn5_a = ~sp5_a;
assign sp4_a = ~((pg2&pg1&ng0) | sn5_a);
assign sn4_a = ~sp4_a;
assign sp3_a = ~((ng2&pg1&ng0) | sn4_a);
assign sn3_a = ~sp3_a;
assign sp2_a = ~((ng2&pg1&pg0) | sn3_a);
assign sn2_a = ~sp2_a;
assign sp1_a = ~((ng2&ng1&pg0) | sn2_a);
assign sn1_a = ~sp1_a;
assign sp0_a = ~((ng2&ng1&ng0) | sn1_a);
assign sn0_a = ~sp0_a;
aibcr3_str_ff x127 ( .se_n(se_n), .so(so), .si(so12),.CDN(nrst), .CP(ck), .D(sn7_a), .code_valid(code_valid), .Q(sn7));
aibcr3_str_ff x118 ( .se_n(se_n), .so(so0), .si(si), .CDN(nrst), .CP(ck), .D(sp1_a), .code_valid(code_valid), .Q(sp1));
aibcr3_str_ff x104 ( .se_n(se_n), .so(so1), .si(so0), .CDN(nrst), .CP(ck), .D(sp2_a), .code_valid(code_valid), .Q(sp2));
aibcr3_str_ff x101 ( .se_n(se_n), .so(so2), .si(so1), .CDN(nrst), .CP(ck), .D(sp3_a), .code_valid(code_valid), .Q(sp3));
aibcr3_str_ff x99 ( .se_n(se_n), .so(so3), .si(so2), .CDN(nrst), .CP(ck), .D(sp4_a), .code_valid(code_valid), .Q(sp4));
aibcr3_str_ff x97 ( .se_n(se_n), .so(so4), .si(so3), .CDN(nrst), .CP(ck), .D(sp5_a), .code_valid(code_valid), .Q(sp5));
aibcr3_str_ff x95 ( .se_n(se_n), .so(so5), .si(so4), .CDN(nrst), .CP(ck), .D(sp6_a), .code_valid(code_valid), .Q(sp6));
aibcr3_str_ff x93 ( .se_n(se_n), .so(so6), .si(so5), .CDN(nrst), .CP(ck), .D(sp7_a), .code_valid(code_valid), .Q(sp7));
aibcr3_str_ff x129 ( .se_n(se_n), .so(so12),.si(so11),.CDN(nrst), .CP(ck), .D(sn6_a), .code_valid(code_valid), .Q(sn6));
aibcr3_str_ff x131 ( .se_n(se_n), .so(so11),.si(so10),.CDN(nrst), .CP(ck), .D(sn5_a), .code_valid(code_valid), .Q(sn5));
aibcr3_str_ff x133 ( .se_n(se_n), .so(so10),.si(so9), .CDN(nrst), .CP(ck), .D(sn4_a), .code_valid(code_valid), .Q(sn4));
aibcr3_str_ff x135 ( .se_n(se_n), .so(so9), .si(so8), .CDN(nrst), .CP(ck), .D(sn3_a), .code_valid(code_valid), .Q(sn3));
aibcr3_str_ff x137 ( .se_n(se_n), .so(so8), .si(so7), .CDN(nrst), .CP(ck), .D(sn2_a), .code_valid(code_valid), .Q(sn2));
aibcr3_str_ff x140 ( .se_n(se_n), .so(so7), .si(so6), .CDN(nrst), .CP(ck), .D(sn1_a), .code_valid(code_valid), .Q(sn1));
initial step = 10; //min:1.5ps; typ:2ps; max:4ps
always @(*)
if (sn7 == 1'b1) calc_delay = (7 * step);
else if (sn6 == 1'b1) calc_delay = (6 * step);
else if (sn5 == 1'b1) calc_delay = (5 * step);
else if (sn4 == 1'b1) calc_delay = (4 * step);
else if (sn3 == 1'b1) calc_delay = (3 * step);
else if (sn2 == 1'b1) calc_delay = (2 * step);
else if (sn1 == 1'b1) calc_delay = (1 * step);
else calc_delay = (0 * step);
initial intrinsic = 50; //min:10ps; typ:50ps; max:80ps
// assign delay = intrinsic + calc_delay;
always @(*) total_delay = intrinsic + calc_delay;
assign #total_delay out_p = fout_p;
endmodule |
module aibcr3_str_ff ( Q, so , CDN, CP,
D, code_valid, se_n, si );
output Q, so;
input CDN, CP, D, code_valid, se_n, si;
wire Q, so, net030, code_valid, D, net023, se_n, si;
assign Q = so;
assign net030 = code_valid ? D : so;
assign net023 = se_n ? net030 : si;
aibcr3_ff_r xff0 ( .Q(so), .CDN(CDN), .CP(CP), .D(net023));
endmodule |
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