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module calibration # (
parameter CALIBRATION_DATA_WIDTH = 256
)(
input wire clk,
input wire rst,
input wire [15:0] estimate_photonic_slack_cycle_length,
input wire calibration_start,
input wire [15:0] calibration_length,
input wire [15:0] calibration_wave_type, // select different types of calibration waveform
input wire [CALIBRATION_DATA_WIDTH-1:0] input_tdata,
input wire input_tvalid,
output reg [CALIBRATION_DATA_WIDTH-1:0] output_tdata,
output reg output_tvalid,
output reg [15:0] loss,
output reg loss_valid
);
wire [CALIBRATION_DATA_WIDTH-1:0] sine_wave_dc = 256'hCF07_A57F_89C3_8003_89C3_A57F_CF07_FFFF_30F8_5A80_763C_7FFC_763C_5A80_30F8_0000;
wire [CALIBRATION_DATA_WIDTH-1:0] sine_wave_positive = 256'hCF07_A57F_89C3_8003_89C3_A57F_CF07_FFFF_30F8_5A80_763C_7FFC_763C_5A80_30F8_0000;
wire [CALIBRATION_DATA_WIDTH-1:0] square_wave_positive = 256'h0000_0000_0000_0000_0000_0000_0000_0000_7FFC_7FFC_7FFC_7FFC_7FFC_7FFC_7FFC_7FFC;
integer i;
reg [CALIBRATION_DATA_WIDTH-1:0] output_tdata_buffer;
reg output_tvalid_buffer;
reg [15:0] photonic_slack_cycle_count;
reg [15:0] counter;
wire [CALIBRATION_DATA_WIDTH-1:0] post_preamble_tdata;
wire post_preamble_tvalid;
reg calibration_start_reg;
reg calibration_started_reg;
wire [15:0] matched_pattern;
always @ (posedge clk)
if (rst) begin
calibration_start_reg <= 1'b0;
calibration_started_reg <= 1'b0;
end else begin
if (!calibration_started_reg && calibration_start_reg) begin
calibration_start_reg <= calibration_start;
calibration_started_reg <= 1'b1;
end else begin
calibration_start_reg <= 1'b0;
end
end
always @ (posedge clk)
if (rst) begin
photonic_slack_cycle_count <= 0;
counter <= 0;
end else begin
counter <= counter + 1;
end
// send out a full sine wave
always @ (posedge clk)
if (rst) begin
output_tdata <= {CALIBRATION_DATA_WIDTH{1'b0}};
output_tvalid <= 1'b0;
end else begin
output_tdata <= output_tdata_buffer;
output_tvalid <= output_tvalid_buffer;
end
always @ (posedge clk)
if (rst) begin
output_tdata_buffer <= {CALIBRATION_DATA_WIDTH{1'b0}};
output_tvalid_buffer <= 1'b0;
end else if (calibration_start && calibration_wave_type[0]) begin
output_tdata_buffer <= sine_wave_dc;
output_tvalid_buffer <= 1'b1;
end else if (calibration_start && calibration_wave_type[1]) begin
output_tdata_buffer <= sine_wave_positive; // the length of the signal is until calibration_start lasts
output_tvalid_buffer <= 1'b1;
end else if (calibration_start && calibration_wave_type[2]) begin
output_tdata_buffer <= square_wave_positive; // the length of the signal is until calibration_start lasts
output_tvalid_buffer <= 1'b1;
end
reg [CALIBRATION_DATA_WIDTH-1:0] accumulated_tdata;
reg accumulated_tvalid;
reg [15:0] accumulated_times;
reg [CALIBRATION_DATA_WIDTH-1:0] ratio;
reg ratio_valid;
reg [CALIBRATION_DATA_WIDTH-1:0] ratio_relay;
reg ratio_valid_relay;
always @ (posedge clk) begin
ratio_relay <= ratio;
ratio_valid_relay <= ratio_valid;
end
// analyze the received waveform
always @ (posedge clk)
if (rst) begin
accumulated_tdata <= {CALIBRATION_DATA_WIDTH{1'b0}};
accumulated_tvalid <= 1'b0;
accumulated_times <= 16'd0;
ratio_valid <= 1'b0;
end else if (input_tvalid) begin
accumulated_times <= accumulated_times + 16'd1;
if (!accumulated_tvalid) begin
accumulated_tdata <= post_preamble_tdata;
accumulated_tvalid <= post_preamble_tvalid;
end else begin
for (i=0; i<CALIBRATION_DATA_WIDTH/16; i=i+1) begin
accumulated_tdata[i*16 +: 16] <= accumulated_tdata[i*16 +: 16]/2 + post_preamble_tdata[i*16 +: 16]/2;
end
accumulated_tvalid <= post_preamble_tvalid;
if (accumulated_times > 16'd0) begin
for (i=0; i<CALIBRATION_DATA_WIDTH/16; i=i+1) begin
if (output_tdata_buffer[i*16+7 +: 8] == 8'd0) begin
ratio[i*16 +: 16] <= 16'd0;
end else begin
ratio[i*16 +: 16] <= accumulated_tdata[i*16 +: 16] << 8;
end
end
ratio_valid <= 1'b1;
end
end
end
wire [15:0] loss_wire;
wire loss_valid_wire;
always @ (posedge clk)
if (rst) begin
loss <= 16'd0;
loss_valid <= 1'b0;
end else begin
loss <= loss_wire;
loss_valid <= loss_valid_wire;
end
generate
averager_tree # (
) averager_tree_calibration_inst(
.clk(clk),
.rst(rst),
.start_signal(accumulated_tvalid ^ ratio_valid_relay),
.persist_cycle_length(calibration_length + estimate_photonic_slack_cycle_length),
.s_tdata(ratio_relay),
.s_tvalid(ratio_valid_relay),
.m_tdata(loss_wire),
.m_tvalid(loss_valid_wire)
);
endgenerate
generate
preamble_detect # (
) preamble_detect_inst (
.clk(clk),
.rst(rst),
.state_changed(calibration_start_reg),
.input_adc_tdata(input_tdata),
.input_adc_tvalid(input_tvalid),
.monitor_cycle_length(calibration_length + estimate_photonic_slack_cycle_length + 100),
.preamble_cycle_length(calibration_length), // let us say we use first half calibration cycles for detection
.pattern_match_agg(),
.matched_pattern(matched_pattern),
.output_detected_tdata(post_preamble_tdata),
.output_detected_tvalid(post_preamble_tvalid)
);
endgenerate
endmodule |
module wb_data_resize
#(parameter aw = 32, //Address width
parameter mdw = 32, //Master Data Width
parameter sdw = 8, //Slave Data Width
parameter [47:0] endian = "big") // Endian for byte reads/writes
(//Wishbone Master interface
input wire [aw-1:0] wbm_adr_i,
input wire [mdw-1:0] wbm_dat_i,
input wire [3:0] wbm_sel_i,
input wire wbm_we_i,
input wire wbm_cyc_i,
input wire wbm_stb_i,
input wire [2:0] wbm_cti_i,
input wire [1:0] wbm_bte_i,
output wire [mdw-1:0] wbm_dat_o,
output wire wbm_ack_o,
output wire wbm_err_o,
output wire wbm_rty_o,
// Wishbone Slave interface
output wire [aw-1:0] wbs_adr_o,
output wire [sdw-1:0] wbs_dat_o,
output wire wbs_we_o,
output wire wbs_cyc_o,
output wire wbs_stb_o,
output wire [2:0] wbs_cti_o,
output wire [1:0] wbs_bte_o,
input wire [sdw-1:0] wbs_dat_i,
input wire wbs_ack_i,
input wire wbs_err_i,
input wire wbs_rty_i);
assign wbs_adr_o[aw-1:2] = wbm_adr_i[aw-1:2];
generate if (endian == "little") begin : le_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2'd3 :
wbm_sel_i[2] ? 2'd2 :
wbm_sel_i[1] ? 2'd1 : 2'd0;
end else begin : be_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2'd0 :
wbm_sel_i[2] ? 2'd1 :
wbm_sel_i[1] ? 2'd2 : 2'd3;
end endgenerate
assign wbs_dat_o = wbm_sel_i[3] ? wbm_dat_i[31:24] :
wbm_sel_i[2] ? wbm_dat_i[23:16] :
wbm_sel_i[1] ? wbm_dat_i[15:8] :
wbm_sel_i[0] ? wbm_dat_i[7:0] : 8'b0;
assign wbs_we_o = wbm_we_i;
assign wbs_cyc_o = wbm_cyc_i;
assign wbs_stb_o = wbm_stb_i;
assign wbs_cti_o = wbm_cti_i;
assign wbs_bte_o = wbm_bte_i;
assign wbm_dat_o = (wbm_sel_i[3]) ? {wbs_dat_i, 24'd0} :
(wbm_sel_i[2]) ? {8'd0 , wbs_dat_i, 16'd0} :
(wbm_sel_i[1]) ? {16'd0, wbs_dat_i, 8'd0} :
{24'd0, wbs_dat_i};
assign wbm_ack_o = wbs_ack_i;
assign wbm_err_o = wbs_err_i;
assign wbm_rty_o = wbs_rty_i;
endmodule |
module wb_mux
#(parameter dw = 32, // Data width
parameter aw = 32, // Address width
parameter num_devices = 2, // Number of devices
parameter num_slaves = num_devices, // Number of devices (deprecated)
parameter [num_slaves*aw-1:0] MATCH_ADDR = 0,
parameter [num_slaves*aw-1:0] MATCH_MASK = 0)
(
input wire wb_clk_i,
input wire wb_rst_i,
// Master Interface
input wire [aw-1:0] wbm_adr_i,
input wire [dw-1:0] wbm_dat_i,
input wire [3:0] wbm_sel_i,
input wire wbm_we_i,
input wire wbm_cyc_i,
input wire wbm_stb_i,
input wire [2:0] wbm_cti_i,
input wire [1:0] wbm_bte_i,
output wire [dw-1:0] wbm_dat_o,
output wire wbm_ack_o,
output wire wbm_err_o,
output wire wbm_rty_o,
// Wishbone Slave interface
output wire [num_slaves*aw-1:0] wbs_adr_o,
output wire [num_slaves*dw-1:0] wbs_dat_o,
output wire [num_slaves*4-1:0] wbs_sel_o,
output wire [num_slaves-1:0] wbs_we_o,
output wire [num_slaves-1:0] wbs_cyc_o,
output wire [num_slaves-1:0] wbs_stb_o,
output wire [num_slaves*3-1:0] wbs_cti_o,
output wire [num_slaves*2-1:0] wbs_bte_o,
input wire [num_slaves*dw-1:0] wbs_dat_i,
input wire [num_slaves-1:0] wbs_ack_i,
input wire [num_slaves-1:0] wbs_err_i,
input wire [num_slaves-1:0] wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Master/slave connection
///////////////////////////////////////////////////////////////////////////////
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter slave_sel_bits = num_slaves > 1 ? $clog2(num_slaves) : 1;
reg wbm_err;
wire [slave_sel_bits-1:0] slave_sel;
wire [num_slaves-1:0] match;
genvar idx;
generate
for(idx=0; idx<num_slaves ; idx=idx+1) begin : addr_match
assign match[idx] = (wbm_adr_i & MATCH_MASK[idx*aw+:aw]) == MATCH_ADDR[idx*aw+:aw];
end
endgenerate
//
// Find First 1 - Start from MSB and count downwards, returns 0 when no bit set
//
function [slave_sel_bits-1:0] ff1;
input [num_slaves-1:0] in;
integer i;
begin
ff1 = 0;
for (i = num_slaves-1; i >= 0; i=i-1) begin
if (in[i])
/* verilator lint_off WIDTH */
ff1 = i;
/* verilator lint_on WIDTH */
end
end
endfunction
assign slave_sel = ff1(match);
always @(posedge wb_clk_i)
wbm_err <= wbm_cyc_i & !(|match);
assign wbs_adr_o = {num_slaves{wbm_adr_i}};
assign wbs_dat_o = {num_slaves{wbm_dat_i}};
assign wbs_sel_o = {num_slaves{wbm_sel_i}};
assign wbs_we_o = {num_slaves{wbm_we_i}};
/* verilator lint_off WIDTH */
assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel);
/* verilator lint_on WIDTH */
assign wbs_stb_o = {num_slaves{wbm_stb_i}};
assign wbs_cti_o = {num_slaves{wbm_cti_i}};
assign wbs_bte_o = {num_slaves{wbm_bte_i}};
assign wbm_dat_o = wbs_dat_i[slave_sel*dw+:dw];
assign wbm_ack_o = wbs_ack_i[slave_sel];
assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err;
assign wbm_rty_o = wbs_rty_i[slave_sel];
endmodule |
module wb_cdc
#(parameter AW = 32)
(input wire wbm_clk,
input wire wbm_rst,
input wire [AW-1:0] wbm_adr_i,
input wire [31:0] wbm_dat_i,
input wire [3:0] wbm_sel_i,
input wire wbm_we_i,
input wire wbm_cyc_i,
input wire wbm_stb_i,
output wire [31:0] wbm_dat_o,
output wire wbm_ack_o,
input wire wbs_clk,
input wire wbs_rst,
output wire [AW-1:0] wbs_adr_o,
output wire [31:0] wbs_dat_o,
output wire [3:0] wbs_sel_o,
output wire wbs_we_o,
output wire wbs_cyc_o,
output wire wbs_stb_o,
input wire [31:0] wbs_dat_i,
input wire wbs_ack_i);
wire wbm_m2s_en;
reg wbm_busy = 1'b0;
wire wbm_cs;
wire wbm_done;
wire wbs_m2s_en;
reg wbs_cs = 1'b0;
cc561
#(.DW (AW+32+4+1))
cdc_m2s
(.aclk (wbm_clk),
.arst (wbm_rst),
.adata ({wbm_adr_i, wbm_dat_i, wbm_sel_i, wbm_we_i}),
.aen (wbm_m2s_en),
.bclk (wbs_clk),
.bdata ({wbs_adr_o, wbs_dat_o, wbs_sel_o, wbs_we_o}),
.ben (wbs_m2s_en));
assign wbm_cs = wbm_cyc_i & wbm_stb_i;
assign wbm_m2s_en = wbm_cs & ~wbm_busy;
always @(posedge wbm_clk) begin
if (wbm_ack_o | wbm_rst)
wbm_busy <= 1'b0;
else if (wbm_cs)
wbm_busy <= 1'b1;
end
always @(posedge wbs_clk) begin
if (wbs_ack_i)
wbs_cs <= 1'b0;
else if (wbs_m2s_en)
wbs_cs <= 1'b1;
end
assign wbs_cyc_o = wbs_m2s_en | wbs_cs;
assign wbs_stb_o = wbs_m2s_en | wbs_cs;
cc561
#(.DW (32))
cdc_s2m
(.aclk (wbs_clk),
.arst (wbs_rst),
.adata (wbs_dat_i),
.aen (wbs_ack_i),
.bclk (wbm_clk),
.bdata (wbm_dat_o),
.ben (wbm_ack_o));
endmodule |
module sie
#(parameter IN_CTRL_MAXPACKETSIZE = 'd8,
parameter IN_BULK_MAXPACKETSIZE = 'd8, // 8, 16, 32, 64
parameter IN_INT_MAXPACKETSIZE = 'd8, // <= 64
parameter IN_ISO_MAXPACKETSIZE = 'd8, // <= 1023
parameter BIT_SAMPLES = 'd4)
(
// ---- to/from USB_CDC module ------------------------------------
output [10:0] frame_o,
// frame_o shall be last recognized frame number and shall be
// updated at the end of next valid Start-of-Frame token packet.
// When clk_gate_i is high, frame_o shall be updated.
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES.
input rstn_i,
// While rstn_i is low (active low), the module shall be reset.
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
// ---- to/from IN/OUT Endpoints ------------------------------------
output bus_reset_o,
// When dp_rx_i/dn_rx_i change and stay in SE0 condition for 2.5us, bus_reset_o shall be high.
// When dp_rx_i/dn_rx_i change from SE0 condition, bus_reset_o shall return low.
// While usb_detach_i is high and a usb detach has started, bus_reset_o shall be high.
// When clk_gate_i is high, bus_reset_o shall be updated.
output [3:0] endp_o,
// endp_o shall be last recognized endpoint address and shall be
// updated at the end of next valid token packet.
// When clk_gate_i is high, endp_o shall be updated.
input stall_i,
// While a bulk, interrupt or control pipe is addressed and is in
// stall state, stall_i shall be high, otherwise shall be low.
// When clk_gate_i is high, stall_i shall be updated.
// ---- to/from OUT Endpoints ------------------------------------
output [7:0] out_data_o,
output out_valid_o,
// While out_valid_o is high, the out_data_o shall be valid and both
// out_valid_o and out_data_o shall not change until consumed.
// When clk_gate_i is high, out_valid_o shall be updated.
output out_err_o,
// When both out_err_o and out_ready_o are high, SIE shall abort the
// current packet reception and OUT Endpoints shall manage the error
// condition.
// When clk_gate_i is high, out_err_o shall be updated.
output setup_o,
// While last correctly checked PID (USB2.0 8.3.1) is SETUP, setup_o shall
// be high, otherwise shall be low.
// When clk_gate_i is high, setup_o shall be updated.
output out_ready_o,
// When both out_valid_o and out_ready_o are high, the out_data_o shall
// be consumed.
// When setup_o is high and out_ready_o is high, a new SETUP transaction shall be
// received.
// When setup_o, out_valid_o and out_err_o are low and out_ready_o is high, the
// on-going OUT packet shall end (EOP).
// out_ready_o shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, out_ready_o shall be updated.
input out_nak_i,
// When out_nak_i is high at the end of an OUT packet, SIE shall send a NAK
// packet.
// When clk_gate_i is high, out_nak_i shall be updated.
// ---- to/from IN Endpoints -------------------------------------
output in_req_o,
// When both in_req_o and in_ready_o are high, a new IN packet shall be requested.
// When clk_gate_i is high, in_req_o shall be updated.
output in_ready_o,
// When both in_ready_o and in_valid_i are high, in_data_i or zero length
// packet shall be consumed.
// When in_data_i or zlp is consumed, in_ready_o shall be high only for
// one clk_gate_i multi-cycle period.
// When clk_gate_i is high, in_ready_o shall be updated.
output in_data_ack_o,
// When in_data_ack_o is high and out_ready_o is high, an ACK packet shall be received.
// When clk_gate_i is high, in_data_ack_o shall be updated.
input in_valid_i,
// While IN Endpoints have data or zero length packet available, IN Endpoints
// shall put in_valid_i high.
// When clk_gate_i is high, in_valid_i shall be updated.
input [7:0] in_data_i,
// While in_valid_i is high and in_zlp_i is low, in_data_i shall be valid.
input in_zlp_i,
// While IN Endpoints have zero length packet available, IN Endpoints
// shall put both in_zlp_i and in_valid_i high.
// When clk_gate_i is high, in_zlp_i shall be updated.
input in_nak_i,
// When in_nak_i is high at the start of an IN packet, SIE shall send a NAK
// packet.
// When clk_gate_i is high, in_nak_i shall be updated.
// ---- to/from CONTROL Endpoint ---------------------------------
input usb_en_i,
// While usb_en_i is low, the phy_rx module shall be disabled.
// When clk_gate_i is high, usb_en_i shall be updated.
input usb_detach_i,
// When usb_detach_i is high, a usb detach shall be requested.
// When clk_gate_i is high, usb_detach_i shall be updated.
input [6:0] addr_i,
// addr_i shall be the device address.
// addr_i shall be updated at the end of SET_ADDRESS control transfer.
// When clk_gate_i is high, addr_i shall be updated.
input [15:0] in_bulk_endps_i,
// While in_bulk_endps_i[i] is high, endp=i shall be enabled as IN bulk endpoint.
// endp=0 is reserved for IN control endpoint.
// When clk_gate_i is high, in_bulk_endps_i shall be updated.
input [15:0] out_bulk_endps_i,
// While out_bulk_endps_i[i] is high, endp=i shall be enabled as OUT bulk endpoint
// endp=0 is reserved for OUT control endpoint.
// When clk_gate_i is high, out_bulk_endps_i shall be updated.
input [15:0] in_int_endps_i,
// While in_int_endps_i[i] is high, endp=i shall be enabled as IN interrupt endpoint.
// endp=0 is reserved for IN control endpoint.
// When clk_gate_i is high, in_int_endps_i shall be updated.
input [15:0] out_int_endps_i,
// While out_int_endps_i[i] is high, endp=i shall be enabled as OUT interrupt endpoint
// endp=0 is reserved for OUT control endpoint.
// When clk_gate_i is high, out_int_endps_i shall be updated.
input [15:0] in_iso_endps_i,
// While in_iso_endps_i[i] is high, endp=i shall be enabled as IN isochronous endpoint.
// endp=0 is reserved for IN control endpoint.
// When clk_gate_i is high, in_iso_endps_i shall be updated.
input [15:0] out_iso_endps_i,
// While out_iso_endps_i[i] is high, endp=i shall be enabled as OUT isochronous endpoint
// endp=0 is reserved for OUT control endpoint.
// When clk_gate_i is high, out_iso_endps_i shall be updated.
input [15:0] in_toggle_reset_i,
// When in_toggle_reset_i[i] is high, data toggle synchronization of
// IN bulk/int pipe at endpoint=i shall be reset to DATA0.
// When clk_gate_i is high, in_toggle_reset_i shall be updated.
input [15:0] out_toggle_reset_i,
// When out_toggle_reset_i[i] is high, data toggle synchronization of
// OUT bulk/int pipe at endpoint=i shall be reset to DATA0.
// When clk_gate_i is high, out_toggle_reset_i shall be updated.
// ---- to/from USB bus physical transmitters/receivers ----------
output dp_pu_o,
// While dp_pu_o is high, a 1.5KOhm resistor shall pull-up the dp line.
// At power-on or when usb_detach_i is high, dp_pu_o shall be low.
// After TSIGATT time from power-on or from usb_detach_i change to low, dp_pu_o shall be high.
output tx_en_o,
output dp_tx_o,
output dn_tx_o,
input dp_rx_i,
input dn_rx_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
function [4:0] crc5;
input [10:0] data;
localparam [4:0] POLY5 = 5'b00101;
integer i;
begin
crc5 = 5'b11111;
for (i = 0; i <= 10; i = i + 1) begin
if ((data[i] ^ crc5[4]) == 1'b1)
crc5 = {crc5[3:0], 1'b0} ^ POLY5;
else
crc5 = {crc5[3:0], 1'b0};
end
end
endfunction
function [4:0] rev5;
input [4:0] data;
integer i;
begin
for (i = 0; i <= 4; i = i + 1) begin
rev5[i] = data[4-i];
end
end
endfunction
function [15:0] crc16;
input [7:0] data;
input [15:0] crc;
localparam [15:0] POLY16 = 16'h8005;
integer i;
begin
crc16 = crc;
for (i = 0; i <= 7; i = i + 1) begin
if ((data[i] ^ crc16[15]) == 1'b1)
crc16 = {crc16[14:0], 1'b0} ^ POLY16;
else
crc16 = {crc16[14:0], 1'b0};
end
end
endfunction
function [7:0] rev8;
input [7:0] data;
integer i;
begin
for (i = 0; i <= 7; i = i + 1) begin
rev8[i] = data[7-i];
end
end
endfunction
localparam [15:0] RESI16 = 16'h800D; // = rev16(~16'h4FFE)
localparam [3:0] ENDP_CTRL = 'd0;
localparam [3:0] PHY_IDLE = 4'd0,
PHY_RX_PID = 4'd1,
PHY_RX_ADDR = 4'd2,
PHY_RX_ENDP = 4'd3,
PHY_RX_DATA0 = 4'd4,
PHY_RX_DATA = 4'd5,
PHY_RX_WAIT_EOP = 4'd6,
PHY_TX_HANDSHAKE_PID = 4'd7,
PHY_TX_DATA_PID = 4'd8,
PHY_TX_DATA = 4'd9,
PHY_TX_CRC16_0 = 4'd10,
PHY_TX_CRC16_1 = 4'd11;
localparam [3:0] PID_RESERVED = 4'b0000,
PID_OUT = 4'b0001,
PID_IN = 4'b1001,
PID_SOF = 4'b0101,
PID_SETUP = 4'b1101,
PID_DATA0 = 4'b0011,
PID_DATA1 = 4'b1011,
PID_ACK = 4'b0010,
PID_NAK = 4'b1010,
PID_STALL = 4'b1110;
localparam IN_WIDTH = ceil_log2(1+`max(IN_CTRL_MAXPACKETSIZE,
`max(IN_BULK_MAXPACKETSIZE,
`max(IN_INT_MAXPACKETSIZE, IN_ISO_MAXPACKETSIZE))));
reg [3:0] phy_state_q, phy_state_d;
reg [3:0] pid_q, pid_d;
reg [6:0] addr_q, addr_d;
reg [3:0] endp_q, endp_d;
reg [10:0] frame_q, frame_d;
reg [15:0] data_q, data_d;
reg [15:0] crc16_q, crc16_d;
reg [15:0] in_toggle_q, in_toggle_d;
reg [15:0] out_toggle_q, out_toggle_d;
reg [15:0] in_zlp_q, in_zlp_d;
reg [IN_WIDTH-1:0] in_byte_q, in_byte_d;
reg out_valid;
reg out_err;
reg out_eop;
reg in_data_ack;
reg [7:0] tx_data;
reg tx_valid;
reg in_ready;
reg in_req;
reg [ceil_log2(8)-1:0] delay_cnt_q;
reg out_err_q;
reg out_eop_q;
reg in_req_q;
reg in_data_ack_q;
wire [7:0] rx_data;
wire rx_valid;
wire rx_err;
wire bus_reset;
wire rstn;
wire rx_ready;
wire tx_ready;
wire delay_end;
wire [15:0] in_toggle_endps;
wire [15:0] out_toggle_endps;
wire [15:0] in_valid_endps;
wire [15:0] out_valid_endps;
assign bus_reset_o = bus_reset;
assign endp_o = endp_q;
assign frame_o = frame_q;
assign out_data_o = data_q[15:8];
assign out_valid_o = out_valid;
assign out_err_o = out_err_q;
assign in_req_o = in_req_q;
assign setup_o = (pid_q == PID_SETUP) ? 1'b1 : 1'b0;
assign in_data_ack_o = in_data_ack_q;
assign delay_end = (({1'b0, delay_cnt_q} == (8-1)) ? 1'b1 : 1'b0);
assign out_ready_o = (rx_ready & out_valid) |
(delay_end & (out_err_q | out_eop_q));
assign in_ready_o = (tx_ready & in_ready) | in_data_ack_q | in_req_q;
assign rstn = rstn_i & ~bus_reset;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
delay_cnt_q <= 'd0;
out_err_q <= 1'b0;
out_eop_q <= 1'b0;
in_req_q <= 1'b0;
in_data_ack_q <= 1'b0;
end else begin
if (clk_gate_i) begin
in_req_q <= in_req & rx_ready;
in_data_ack_q <= in_data_ack & (rx_ready | tx_ready);
if (phy_state_q == PHY_RX_PID || phy_state_q == PHY_RX_ENDP ||
phy_state_q == PHY_RX_DATA) begin
delay_cnt_q <= 'd0;
if (rx_ready) begin
if (phy_state_q == PHY_RX_DATA)
out_err_q <= out_err | out_err_q;
out_eop_q <= out_eop | out_eop_q;
end
end else if (!delay_end) begin
delay_cnt_q <= delay_cnt_q + 1;
end else begin
out_err_q <= 1'b0;
out_eop_q <= 1'b0;
end
end
end
end
localparam [15:0] CTRL_ENDPS = 16'h01;
assign in_toggle_endps = in_bulk_endps_i|in_int_endps_i|CTRL_ENDPS;
assign out_toggle_endps = out_bulk_endps_i|out_int_endps_i|CTRL_ENDPS;
assign in_valid_endps = in_bulk_endps_i|in_int_endps_i|in_iso_endps_i|CTRL_ENDPS;
assign out_valid_endps = out_bulk_endps_i|out_int_endps_i|out_iso_endps_i|CTRL_ENDPS;
integer i;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
phy_state_q <= PHY_IDLE;
pid_q <= PID_RESERVED;
addr_q <= 7'd0;
endp_q <= ENDP_CTRL;
frame_q <= 11'd0;
data_q <= 16'd0;
crc16_q <= 16'd0;
in_toggle_q <= 16'd0;
out_toggle_q <= 16'd0;
in_zlp_q <= 16'd0;
in_byte_q <= 'd0;
end else begin
if (clk_gate_i) begin
if (rx_ready | tx_ready) begin
phy_state_q <= phy_state_d;
pid_q <= pid_d;
addr_q <= addr_d;
endp_q <= endp_d;
frame_q <= frame_d;
data_q <= data_d;
crc16_q <= crc16_d;
in_toggle_q <= in_toggle_d & in_toggle_endps;
out_toggle_q <= out_toggle_d & out_toggle_endps;
in_zlp_q <= in_zlp_d & in_valid_endps;
in_byte_q <= in_byte_d;
end
for (i = 0; i < 16; i = i + 1) begin
if (in_toggle_reset_i[i] & in_toggle_endps[i] & ~CTRL_ENDPS[i])
in_toggle_q[i] <= 1'b0;
if (out_toggle_reset_i[i] & out_toggle_endps[i] & ~CTRL_ENDPS[i])
out_toggle_q[i] <= 1'b0;
end
end
end
end
always @(/*AS*/addr_i or addr_q or crc16_q or data_q or endp_q
or frame_q or in_bulk_endps_i or in_byte_q or in_data_i
or in_int_endps_i or in_iso_endps_i or in_nak_i
or in_toggle_endps or in_toggle_q or in_valid_endps
or in_valid_i or in_zlp_i or in_zlp_q or out_iso_endps_i
or out_nak_i or out_toggle_endps or out_toggle_q
or out_valid_endps or phy_state_q or pid_q or rx_data
or rx_err or rx_valid or stall_i) begin
phy_state_d = phy_state_q;
pid_d = pid_q;
addr_d = addr_q;
endp_d = endp_q;
frame_d = frame_q;
data_d = {8'd0, rx_data};
crc16_d = crc16_q;
in_toggle_d = in_toggle_q;
out_toggle_d = out_toggle_q;
in_zlp_d = in_zlp_q;
in_byte_d = 'd0;
out_valid = 1'b0;
out_err = 1'b0;
out_eop = 1'b0;
in_data_ack = 1'b0;
tx_data = 8'd0;
tx_valid = 1'b0;
in_ready = 1'b0;
in_req = 1'b0;
if (rx_err == 1'b1) begin
phy_state_d = PHY_IDLE;
out_err = 1'b1;
end else begin
case (phy_state_q)
PHY_RX_WAIT_EOP : begin
if (rx_valid == 1'b0) begin
phy_state_d = PHY_IDLE;
end
end
PHY_IDLE : begin
if (rx_valid == 1'b1) begin
phy_state_d = PHY_RX_PID;
end
end
PHY_RX_PID : begin
pid_d = PID_RESERVED;
if (data_q[7:4] == ~data_q[3:0]) begin
pid_d = data_q[3:0];
case (data_q[1:0])
2'b01 : begin // Token
if (rx_valid == 1'b1) begin
phy_state_d = PHY_RX_ADDR;
end else begin
phy_state_d = PHY_IDLE;
end
end
2'b11 : begin // Data
if (rx_valid == 1'b1) begin
if ((data_q[3:2] == PID_DATA0[3:2] || data_q[3:2] == PID_DATA1[3:2]) &&
(pid_q == PID_SETUP || pid_q == PID_OUT) &&
addr_q == addr_i && out_valid_endps[endp_q] == 1'b1) begin
phy_state_d = PHY_RX_DATA0;
end else begin
phy_state_d = PHY_RX_WAIT_EOP;
end
end else begin
phy_state_d = PHY_IDLE;
end
end
2'b10 : begin // Handshake
if (rx_valid == 1'b0) begin
phy_state_d = PHY_IDLE;
if (data_q[3:2] == PID_ACK[3:2] && addr_q == addr_i &&
in_toggle_endps[endp_q] == 1'b1) begin // ACK
in_toggle_d[endp_q] = ~in_toggle_q[endp_q];
in_data_ack = 1'b1;
end
end else begin
phy_state_d = PHY_RX_WAIT_EOP;
end
end
default : begin // Special -> Not valid
if (rx_valid == 1'b0) begin
phy_state_d = PHY_IDLE;
end else begin
phy_state_d = PHY_RX_WAIT_EOP;
end
end
endcase
end else if (rx_valid == 1'b1) begin
phy_state_d = PHY_RX_WAIT_EOP;
end else begin
phy_state_d = PHY_IDLE;
end
crc16_d = 16'hFFFF;
end
PHY_RX_ADDR : begin
if (rx_valid == 1'b1) begin
phy_state_d = PHY_RX_ENDP;
end else begin
phy_state_d = PHY_IDLE;
end
data_d[15:8] = data_q[7:0];
end
PHY_RX_ENDP : begin
addr_d[0] = ~addr_i[0]; // to invalid addr_q in case of token error
if (rx_valid == 1'b0) begin
phy_state_d = PHY_IDLE;
if (crc5({data_q[2:0], data_q[15:8]}) == rev5(~data_q[7:3])) begin
if (pid_q == PID_SOF) begin
frame_d = {data_q[2:0], data_q[15:8]};
end else begin
addr_d = data_q[14:8];
endp_d = {data_q[2:0], data_q[15]};
if (data_q[14:8] == addr_i) begin
if (pid_q == PID_IN) begin
phy_state_d = PHY_TX_DATA_PID;
in_req = 1'b1;
end else if (pid_q == PID_SETUP) begin
in_toggle_d[ENDP_CTRL] = 1'b1;
out_toggle_d[ENDP_CTRL] = 1'b0;
out_eop = 1'b1; // will be delayed for ctrl_enpd to capture new endp_q
end
end
end
end
end else begin
phy_state_d = PHY_RX_WAIT_EOP;
end
end
PHY_RX_DATA0 : begin
if (rx_valid == 1'b1) begin
phy_state_d = PHY_RX_DATA;
end else begin
phy_state_d = PHY_IDLE;
end
data_d[15:8] = data_q[7:0];
crc16_d = crc16(data_q[7:0], crc16_q);
end
PHY_RX_DATA : begin
if (rx_valid == 1'b1) begin
out_valid = 1'b1;
end else begin
if (crc16(data_q[7:0], crc16_q) == RESI16) begin
if ((out_toggle_q[endp_q] == pid_q[3] && out_toggle_endps[endp_q] == 1'b1) ||
out_iso_endps_i[endp_q] == 1'b1) begin
out_toggle_d[endp_q] = ~out_toggle_q[endp_q];
out_eop = 1'b1;
end else begin
out_err = 1'b1;
end
if (out_toggle_endps[endp_q] == 1'b1)
phy_state_d = PHY_TX_HANDSHAKE_PID;
else
phy_state_d = PHY_IDLE;
if (stall_i == 1'b1) begin
pid_d = PID_STALL;
end else if (out_nak_i == 1'b1) begin
out_toggle_d[endp_q] = out_toggle_q[endp_q];
pid_d = PID_NAK;
end else begin
pid_d = PID_ACK;
end
end else begin
out_err = 1'b1;
phy_state_d = PHY_IDLE;
end
end
data_d[15:8] = data_q[7:0];
crc16_d = crc16(data_q[7:0], crc16_q);
end
PHY_TX_HANDSHAKE_PID : begin
tx_data = {~pid_q, pid_q};
phy_state_d = PHY_IDLE;
tx_valid = 1'b1;
end
PHY_TX_DATA_PID : begin
tx_valid = 1'b1;
if (in_valid_endps[endp_q] == 1'b0) begin // USB2.0 8.3.2 pag.197)
tx_valid = 1'b0;
phy_state_d = PHY_IDLE;
end else if (stall_i == 1'b1) begin
if (in_toggle_endps[endp_q] == 1'b1) begin
pid_d = PID_STALL;
tx_data = {~PID_STALL, PID_STALL};
end else begin
tx_valid = 1'b0;
end
phy_state_d = PHY_IDLE;
end else if ((in_nak_i == 1'b1) || (in_valid_i == 1'b0 && in_zlp_q[endp_q] == 1'b0)) begin
if (in_toggle_endps[endp_q] == 1'b1) begin
pid_d = PID_NAK;
tx_data = {~PID_NAK, PID_NAK};
end else begin
tx_valid = 1'b0;
end
phy_state_d = PHY_IDLE;
end else begin
if (in_toggle_q[endp_q] == 1'b0) begin
pid_d = PID_DATA0;
tx_data = {~PID_DATA0, PID_DATA0};
end else begin
pid_d = PID_DATA1;
tx_data = {~PID_DATA1, PID_DATA1};
end
if ((in_valid_i == 1'b0) || (in_zlp_i == 1'b1)) begin
phy_state_d = PHY_TX_CRC16_0;
end else begin
in_ready = 1'b1;
phy_state_d = PHY_TX_DATA;
end
end
data_d[7:0] = in_data_i;
crc16_d = 16'hFFFF;
in_zlp_d[endp_q] = 1'b0;
end
PHY_TX_DATA : begin
tx_data = data_q[7:0];
if ((endp_q == ENDP_CTRL && in_byte_q == IN_CTRL_MAXPACKETSIZE[IN_WIDTH-1:0]-1) ||
(in_bulk_endps_i[endp_q] == 1'b1 && in_byte_q == IN_BULK_MAXPACKETSIZE[IN_WIDTH-1:0]-1) ||
(in_int_endps_i[endp_q] == 1'b1 && in_byte_q == IN_INT_MAXPACKETSIZE[IN_WIDTH-1:0]-1) ||
(in_iso_endps_i[endp_q] == 1'b1 && in_byte_q == IN_ISO_MAXPACKETSIZE[IN_WIDTH-1:0]-1)) begin
phy_state_d = PHY_TX_CRC16_0;
in_zlp_d[endp_q] = 1'b1;
end else if (in_valid_i == 1'b0) begin
phy_state_d = PHY_TX_CRC16_0;
end else begin
in_ready = 1'b1;
end
data_d[7:0] = in_data_i;
crc16_d = crc16(data_q[7:0], crc16_q);
tx_valid = 1'b1;
in_byte_d = in_byte_q + 1;
end
PHY_TX_CRC16_0 : begin
tx_data = rev8(~crc16_q[15:8]);
phy_state_d = PHY_TX_CRC16_1;
tx_valid = 1'b1;
end
PHY_TX_CRC16_1 : begin
tx_data = rev8(~crc16_q[7:0]);
phy_state_d = PHY_IDLE;
tx_valid = 1'b1;
if (in_iso_endps_i[endp_q] == 1'b1)
in_data_ack = 1'b1;
end
default : begin
phy_state_d = PHY_IDLE;
end
endcase
end
end
wire tx_en;
wire rx_en;
assign tx_en_o = tx_en;
assign rx_en = ~tx_en & usb_en_i;
phy_rx #(.BIT_SAMPLES(BIT_SAMPLES))
u_phy_rx (.rx_data_o(rx_data),
.rx_valid_o(rx_valid),
.rx_err_o(rx_err),
.dp_pu_o(dp_pu_o),
.bus_reset_o(bus_reset),
.rx_ready_o(rx_ready),
.clk_i(clk_i),
.rstn_i(rstn_i),
.clk_gate_i(clk_gate_i),
.rx_en_i(rx_en),
.usb_detach_i(usb_detach_i),
.dp_rx_i(dp_rx_i),
.dn_rx_i(dn_rx_i));
phy_tx
u_phy_tx (.tx_en_o(tx_en),
.dp_tx_o(dp_tx_o),
.dn_tx_o(dn_tx_o),
.tx_ready_o(tx_ready),
.clk_i(clk_i),
.rstn_i(rstn),
.clk_gate_i(clk_gate_i),
.tx_valid_i(tx_valid),
.tx_data_i(tx_data));
endmodule |
module bulk_endp
#(parameter IN_BULK_MAXPACKETSIZE = 'd8,
parameter OUT_BULK_MAXPACKETSIZE = 'd8,
parameter USE_APP_CLK = 0,
parameter APP_CLK_FREQ = 12) // app_clk frequency in MHz
(
// ---- to/from Application ------------------------------------
input app_clk_i,
input [7:0] app_in_data_i,
input app_in_valid_i,
// While app_in_valid_i is high, app_in_data_i shall be valid.
output app_in_ready_o,
// When both app_in_ready_o and app_in_valid_i are high, app_in_data_i shall
// be consumed.
output [7:0] app_out_data_o,
output app_out_valid_o,
// While app_out_valid_o is high, the app_out_data_o shall be valid and both
// app_out_valid_o and app_out_data_o shall not change until consumed.
input app_out_ready_i,
// When both app_out_valid_o and app_out_ready_i are high, the app_out_data_o shall
// be consumed.
// ---- from USB_CDC module ------------------------------------
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES
input rstn_i,
// While rstn_i is low (active low), the module shall be reset
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
input bus_reset_i,
// While bus_reset_i is high, the module shall be reset
// When clk_gate_i is high, bus_reset_i shall be updated.
// ---- to/from SIE module ------------------------------------
output [7:0] in_data_o,
// While in_valid_o is high, in_data_o shall be valid.
output in_valid_o,
// While IN FIFO is not empty, in_valid_o shall be high.
// When clk_gate_i is high, in_valid_o shall be updated.
input in_req_i,
// When both in_req_i and in_ready_i are high, a new IN packet shall be requested.
// When clk_gate_i is high, in_req_i shall be updated.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall be consumed.
// in_ready_i shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, in_ready_i shall be updated.
input in_data_ack_i,
// When both in_data_ack_i and in_ready_i are high, an ACK packet shall be received.
// When clk_gate_i is high, in_data_ack_i shall be updated.
output out_nak_o,
// While out_valid_i is high, when OUT FIFO is full, out_nak_o shall be
// latched high.
// When either out_valid_i or out_err_i is low and out_ready_i is high,
// out_nak_o shall be low.
// When clk_gate_i is high, out_nak_o shall be updated.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
// When clk_gate_i is high, out_valid_i shall be updated.
input out_err_i,
// When both out_err_i and out_ready_i are high, SIE shall abort the
// current packet reception and OUT Bulk Endpoint shall manage the error
// condition.
// When clk_gate_i is high, out_err_i shall be updated.
input out_ready_i
// When both out_valid_i and out_ready_i are high, the out_data_i shall
// be consumed.
// When out_valid_i and out_err_i are low and out_ready_i is high, the
// on-going OUT packet shall end (EOP).
// out_ready_i shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, out_ready_i shall be updated.
);
wire rstn;
wire app_rstn;
assign rstn = rstn_i & ~bus_reset_i;
generate
if (USE_APP_CLK == 0) begin : u_sync_app_rstn
assign app_rstn = 1'b0;
end else begin : u_async_app_rstn
reg [1:0] app_rstn_sq;
assign app_rstn = app_rstn_sq[0];
always @(posedge app_clk_i or negedge rstn) begin
if (~rstn) begin
app_rstn_sq <= 2'd0;
end else begin
app_rstn_sq <= {1'b1, app_rstn_sq[1]};
end
end
end
endgenerate
in_fifo #(.IN_MAXPACKETSIZE(IN_BULK_MAXPACKETSIZE),
.USE_APP_CLK(USE_APP_CLK),
.APP_CLK_FREQ(APP_CLK_FREQ))
u_in_fifo (.in_empty_o(),
.in_full_o(),
.in_data_o(in_data_o),
.in_valid_o(in_valid_o),
.app_in_ready_o(app_in_ready_o),
.clk_i(clk_i),
.app_clk_i(app_clk_i),
.rstn_i(rstn),
.app_rstn_i(app_rstn),
.clk_gate_i(clk_gate_i),
.in_req_i(in_req_i),
.in_data_ack_i(in_data_ack_i),
.app_in_data_i(app_in_data_i),
.app_in_valid_i(app_in_valid_i),
.in_ready_i(in_ready_i));
out_fifo #(.OUT_MAXPACKETSIZE(OUT_BULK_MAXPACKETSIZE),
.USE_APP_CLK(USE_APP_CLK),
.APP_CLK_FREQ(APP_CLK_FREQ))
u_out_fifo (.out_empty_o(),
.out_full_o(),
.out_nak_o(out_nak_o),
.app_out_valid_o(app_out_valid_o),
.app_out_data_o(app_out_data_o),
.clk_i(clk_i),
.app_clk_i(app_clk_i),
.rstn_i(rstn),
.app_rstn_i(app_rstn),
.clk_gate_i(clk_gate_i),
.out_data_i(out_data_i),
.out_valid_i(out_valid_i),
.out_err_i(out_err_i),
.out_ready_i(out_ready_i),
.app_out_ready_i(app_out_ready_i));
endmodule |
module out_fifo
#(parameter OUT_MAXPACKETSIZE = 'd8,
parameter USE_APP_CLK = 0,
parameter APP_CLK_FREQ = 12) // app_clk frequency in MHz
(
// ---- to/from Application ------------------------------------
input app_clk_i,
input app_rstn_i,
// While app_rstn_i is low (active low), the app_clk_i'ed registers shall be reset
output [7:0] app_out_data_o,
output app_out_valid_o,
// While app_out_valid_o is high, the app_out_data_o shall be valid and both
// app_out_valid_o and app_out_data_o shall not change until consumed.
input app_out_ready_i,
// When both app_out_valid_o and app_out_ready_i are high, the app_out_data_o shall
// be consumed.
// ---- from top module ---------------------------------------
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES
input rstn_i,
// While rstn_i is low (active low), the clk_i'ed registers shall be reset
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
output out_empty_o,
// While the OUT FIFO is empty out_empty_o shall be high. Unconfirmed data is not condidered.
// When clk_gate_i is high, out_empty_o shall be updated.
output out_full_o,
// While the OUT FIFO is full, including the presence of unconfirmed data waiting for EOP,
// in_full_o shall be high.
// When clk_gate_i is high, out_full_o shall be updated.
// ---- to/from SIE module ------------------------------------
output out_nak_o,
// While out_valid_i is high, when OUT FIFO is full, out_nak_o shall be
// latched high.
// When either out_valid_i or out_err_i is low and out_ready_i is high,
// out_nak_o shall be low.
// When clk_gate_i is high, out_nak_o shall be updated.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
// When clk_gate_i is high, out_valid_i shall be updated.
input out_err_i,
// When both out_err_i and out_ready_i are high, SIE shall abort the
// current packet reception and OUT FIFO shall manage the error condition.
// When clk_gate_i is high, out_err_i shall be updated.
input out_ready_i
// When both out_valid_i and out_ready_i are high, the out_data_i shall
// be consumed.
// When out_valid_i and out_err_i are low and out_ready_i is high, the
// on-going OUT packet shall end (EOP).
// out_ready_i shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, out_ready_i shall be updated.
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
localparam OUT_LENGTH = OUT_MAXPACKETSIZE + 'd1; // the contents of the last addressed byte is meaningless
reg [8*OUT_LENGTH-1:0] out_fifo_q;
reg [ceil_log2(OUT_LENGTH)-1:0] out_first_q;
reg [ceil_log2(OUT_LENGTH)-1:0] out_last_q, out_last_d;
reg [ceil_log2(OUT_LENGTH)-1:0] out_last_qq, out_last_dd;
reg out_nak_q, out_nak_d;
wire out_full;
assign out_full = (out_first_q == ((out_last_qq == OUT_LENGTH-1) ? 'd0 : out_last_qq+1) ? 1'b1 : 1'b0);
assign out_full_o = out_full;
assign out_nak_o = out_nak_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
out_fifo_q <= {OUT_LENGTH{8'd0}};
out_last_q <= 'd0;
out_last_qq <= 'd0;
out_nak_q <= 1'b0;
end else begin
if (clk_gate_i) begin
out_fifo_q[{out_last_qq, 3'd0} +:8] <= out_data_i;
if (out_ready_i) begin
out_last_q <= out_last_d;
out_last_qq <= out_last_dd;
out_nak_q <= out_nak_d;
end
end
end
end
always @(/*AS*/out_err_i or out_full or out_last_q or out_last_qq
or out_nak_q or out_valid_i) begin
out_last_d = out_last_q;
out_last_dd = out_last_qq;
out_nak_d = 1'b0;
if (out_err_i) begin
out_last_dd = out_last_q;
end else if (~out_valid_i) begin
if (out_nak_q == 1'b1)
out_last_dd = out_last_q;
else
out_last_d = out_last_qq;
end else if (out_full | out_nak_q) begin
out_nak_d = 1'b1;
end else begin
if (out_last_qq == OUT_LENGTH-1)
out_last_dd = 'd0;
else
out_last_dd = out_last_qq + 1;
end
end
wire [7:0] app_out_data;
wire out_empty;
wire app_out_buffer_empty;
assign app_out_data = out_fifo_q[{out_first_q, 3'd0} +:8];
assign out_empty = ((out_first_q == out_last_q) ? 1'b1 : 1'b0);
assign out_empty_o = out_empty && app_out_buffer_empty;
generate
if (USE_APP_CLK == 0) begin : u_sync_data
reg [7:0] app_out_data_q;
reg app_out_valid_q, app_out_valid_qq;
assign app_out_data_o = app_out_data_q;
assign app_out_valid_o = app_out_valid_q;
assign app_out_buffer_empty = ~app_out_valid_qq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
out_first_q <= 'd0;
app_out_data_q <= 8'd0;
app_out_valid_q <= 1'b0;
app_out_valid_qq <= 1'b0;
end else begin
if (app_out_ready_i & app_out_valid_q)
app_out_valid_q <= 1'b0;
if (clk_gate_i) begin
app_out_valid_qq <= app_out_valid_q;
if (~out_empty) begin
if (~app_out_valid_q | (app_out_ready_i & app_out_valid_q)) begin
app_out_data_q <= app_out_data;
app_out_valid_q <= 1'b1;
app_out_valid_qq <= 1'b1;
if (out_first_q == OUT_LENGTH-1)
out_first_q <= 'd0;
else
out_first_q <= out_first_q + 1;
end
end
end
end
end
end else if (APP_CLK_FREQ <= 12) begin : u_lte12mhz_async_data
reg [15:0] app_out_data_q;
reg [1:0] app_out_valid_q;
reg app_out_valid_qq, app_out_valid_qqq;
reg app_out_consumed_q;
reg [2:0] app_clk_sq; // BIT_SAMPLES >= 4
assign app_out_data_o = app_out_data_q[7:0];
assign app_out_valid_o = app_out_valid_qq;
assign app_out_buffer_empty = ~app_out_valid_qqq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
out_first_q <= 'd0;
app_out_data_q <= 16'd0;
app_out_valid_q <= 2'b00;
app_out_valid_qq <= 1'b0;
app_out_valid_qqq <= 1'b0;
app_clk_sq <= 3'b000;
end else begin
app_clk_sq <= {app_clk_i, app_clk_sq[2:1]};
if (app_clk_sq[1:0] == 2'b10) begin
app_out_valid_qq <= app_out_valid_q[0];
if (app_out_consumed_q) begin
if (app_out_valid_q[1]) begin
app_out_data_q[7:0] <= app_out_data_q[15:8];
app_out_valid_q <= 2'b01;
app_out_valid_qq <= 1'b1;
end else begin
app_out_valid_q <= 2'b00;
app_out_valid_qq <= 1'b0;
end
end
end
if (clk_gate_i) begin
app_out_valid_qqq <= |app_out_valid_q;
if (~out_empty) begin
if (app_out_valid_q != 2'b11 ||
(app_clk_sq[1:0] == 2'b10 && app_out_consumed_q == 1'b1)) begin
if (app_out_valid_q[1] == 1'b1 &&
(app_clk_sq[1:0] == 2'b10 && app_out_consumed_q == 1'b1)) begin
app_out_data_q[15:8] <= app_out_data;
app_out_valid_q[1] <= 1'b1;
app_out_valid_qqq <= 1'b1;
end else if (app_out_valid_q[0] == 1'b0 ||
(app_clk_sq[1:0] == 2'b10 && app_out_consumed_q == 1'b1)) begin
app_out_data_q[7:0] <= app_out_data;
app_out_valid_q[0] <= 1'b1;
app_out_valid_qqq <= 1'b1;
end else begin
app_out_data_q[15:8] <= app_out_data;
app_out_valid_q[1] <= 1'b1;
app_out_valid_qqq <= 1'b1;
end
if (out_first_q == OUT_LENGTH-1)
out_first_q <= 'd0;
else
out_first_q <= out_first_q + 1;
end
end
end
end
end
always @(posedge app_clk_i or negedge app_rstn_i) begin
if (~app_rstn_i) begin
app_out_consumed_q <= 1'b0;
end else begin
app_out_consumed_q <= app_out_ready_i & app_out_valid_qq;
end
end
end else begin : u_gt12mhz_async_data
reg [1:0] app_out_consumed_sq;
reg [7:0] app_out_data_q;
reg app_out_valid_q;
reg app_out_consumed_q;
assign app_out_buffer_empty = ~app_out_valid_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
out_first_q <= 'd0;
app_out_data_q <= 8'd0;
app_out_valid_q <= 1'b0;
app_out_consumed_sq <= 2'b00;
end else begin
app_out_consumed_sq <= {app_out_consumed_q, app_out_consumed_sq[1]};
if (clk_gate_i) begin
if (app_out_consumed_sq[0])
app_out_valid_q <= 1'b0;
else if (~out_empty & ~app_out_valid_q) begin
app_out_data_q <= app_out_data;
app_out_valid_q <= 1'b1;
if (out_first_q == OUT_LENGTH-1)
out_first_q <= 'd0;
else
out_first_q <= out_first_q + 1;
end
end
end
end
reg [1:0] out_valid_sq;
assign app_out_data_o = app_out_data_q;
assign app_out_valid_o = out_valid_sq[0] & ~app_out_consumed_q;
always @(posedge app_clk_i or negedge app_rstn_i) begin
if (~app_rstn_i) begin
out_valid_sq <= 2'b00;
app_out_consumed_q <= 1'b0;
end else begin
out_valid_sq <= {app_out_valid_q, out_valid_sq[1]};
if (~out_valid_sq[0])
app_out_consumed_q <= 1'b0;
else if (app_out_ready_i & ~app_out_consumed_q)
app_out_consumed_q <= 1'b1;
end
end
end
endgenerate
endmodule |
module usb_cdc
#(parameter VENDORID = 16'h0000,
parameter PRODUCTID = 16'h0000,
parameter CHANNELS = 'd1,
parameter IN_BULK_MAXPACKETSIZE = 'd8,
parameter OUT_BULK_MAXPACKETSIZE = 'd8,
parameter BIT_SAMPLES = 'd4,
parameter USE_APP_CLK = 0,
parameter APP_CLK_FREQ = 12) // app_clk frequency in MHz
(
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES
input rstn_i,
// While rstn_i is low (active low), the module shall be reset
// ---- to/from Application ------------------------------------
input app_clk_i,
output [8*CHANNELS-1:0] out_data_o,
output [CHANNELS-1:0] out_valid_o,
// While out_valid_o is high, the out_data_o shall be valid and both
// out_valid_o and out_data_o shall not change until consumed.
input [CHANNELS-1:0] out_ready_i,
// When both out_valid_o and out_ready_i are high, the out_data_o shall
// be consumed.
input [8*CHANNELS-1:0] in_data_i,
input [CHANNELS-1:0] in_valid_i,
// While in_valid_i is high, in_data_i shall be valid.
output [CHANNELS-1:0] in_ready_o,
// When both in_ready_o and in_valid_i are high, in_data_i shall
// be consumed.
output [10:0] frame_o,
// frame_o shall be last recognized USB frame number sent by USB host.
output configured_o,
// While USB_CDC is in configured state, configured_o shall be high.
// ---- to USB bus physical transmitters/receivers --------------
output dp_pu_o,
output tx_en_o,
output dp_tx_o,
output dn_tx_o,
input dp_rx_i,
input dn_rx_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
reg [1:0] rstn_sq;
wire rstn;
assign rstn = rstn_sq[0];
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rstn_sq <= 2'd0;
end else begin
rstn_sq <= {1'b1, rstn_sq[1]};
end
end
reg [ceil_log2(BIT_SAMPLES)-1:0] clk_cnt_q;
reg clk_gate_q;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
clk_cnt_q <= 'd0;
clk_gate_q <= 1'b0;
end else begin
if ({1'b0, clk_cnt_q} == BIT_SAMPLES-1) begin
clk_cnt_q <= 'd0;
clk_gate_q <= 1'b1;
end else begin
clk_cnt_q <= clk_cnt_q + 1;
clk_gate_q <= 1'b0;
end
end
end
localparam CTRL_MAXPACKETSIZE = 'd8;
localparam [3:0] ENDP_CTRL = 'd0;
reg [7:0] sie2i_in_data;
reg sie2i_in_valid, sie2i_out_nak;
wire [3:0] endp;
wire [7:0] ctrl_in_data;
wire [8*CHANNELS-1:0] bulk_in_data;
wire ctrl_in_valid;
wire [CHANNELS-1:0] bulk_in_valid;
wire [CHANNELS-1:0] bulk_out_nak;
always @(/*AS*/bulk_in_data or bulk_in_valid or bulk_out_nak
or ctrl_in_data or ctrl_in_valid or endp) begin : u_mux
integer j;
sie2i_in_data = ctrl_in_data;
sie2i_in_valid = (endp == ENDP_CTRL) ? ctrl_in_valid : 1'b0;
sie2i_out_nak = 1'b0;
for (j = 0; j < CHANNELS; j = j+1) begin
if (endp == 2*j[2:0]+1) begin
sie2i_in_data = bulk_in_data[8*j +:8];
sie2i_in_valid = bulk_in_valid[j];
sie2i_out_nak = bulk_out_nak[j];
end
end
end
wire [6:0] addr;
wire [7:0] sie_out_data;
wire sie_out_valid;
wire sie_in_req;
wire sie_out_err;
wire setup;
wire [15:0] in_bulk_endps;
wire [15:0] out_bulk_endps;
wire [15:0] in_int_endps;
wire [15:0] out_int_endps;
wire [15:0] in_toggle_reset;
wire [15:0] out_toggle_reset;
wire bus_reset;
wire sie_in_ready;
wire sie_in_data_ack;
wire sie_out_ready;
wire usb_en;
wire sie2i_in_zlp, ctrl_in_zlp;
wire sie2i_in_nak;
wire sie2i_stall, ctrl_stall;
assign sie2i_in_zlp = (endp == ENDP_CTRL) ? ctrl_in_zlp : 1'b0;
assign sie2i_in_nak = in_int_endps[endp];
assign sie2i_stall = (endp == ENDP_CTRL) ? ctrl_stall : 1'b0;
sie #(.IN_CTRL_MAXPACKETSIZE(CTRL_MAXPACKETSIZE),
.IN_BULK_MAXPACKETSIZE(IN_BULK_MAXPACKETSIZE),
.BIT_SAMPLES(BIT_SAMPLES))
u_sie (.bus_reset_o(bus_reset),
.dp_pu_o(dp_pu_o),
.tx_en_o(tx_en_o),
.dp_tx_o(dp_tx_o),
.dn_tx_o(dn_tx_o),
.endp_o(endp),
.frame_o(frame_o),
.out_data_o(sie_out_data),
.out_valid_o(sie_out_valid),
.out_err_o(sie_out_err),
.in_req_o(sie_in_req),
.setup_o(setup),
.out_ready_o(sie_out_ready),
.in_ready_o(sie_in_ready),
.in_data_ack_o(sie_in_data_ack),
.in_bulk_endps_i(in_bulk_endps),
.out_bulk_endps_i(out_bulk_endps),
.in_int_endps_i(in_int_endps),
.out_int_endps_i(out_int_endps),
.in_iso_endps_i(16'b0),
.out_iso_endps_i(16'b0),
.clk_i(clk_i),
.rstn_i(rstn),
.clk_gate_i(clk_gate_q),
.usb_en_i(usb_en),
.usb_detach_i(1'b0),
.dp_rx_i(dp_rx_i),
.dn_rx_i(dn_rx_i),
.addr_i(addr),
.in_valid_i(sie2i_in_valid),
.in_data_i(sie2i_in_data),
.in_zlp_i(sie2i_in_zlp),
.out_nak_i(sie2i_out_nak),
.in_nak_i(sie2i_in_nak),
.stall_i(sie2i_stall),
.in_toggle_reset_i(in_toggle_reset),
.out_toggle_reset_i(out_toggle_reset));
wire ctrl2i_in_req, ctrl2i_out_ready, ctrl2i_in_ready;
assign ctrl2i_in_req = (endp == ENDP_CTRL) ? sie_in_req : 1'b0;
assign ctrl2i_out_ready = (endp == ENDP_CTRL) ? sie_out_ready : 1'b0;
assign ctrl2i_in_ready = (endp == ENDP_CTRL) ? sie_in_ready : 1'b0;
ctrl_endp #(.VENDORID(VENDORID),
.PRODUCTID(PRODUCTID),
.CHANNELS(CHANNELS),
.CTRL_MAXPACKETSIZE(CTRL_MAXPACKETSIZE),
.IN_BULK_MAXPACKETSIZE(IN_BULK_MAXPACKETSIZE),
.OUT_BULK_MAXPACKETSIZE(OUT_BULK_MAXPACKETSIZE))
u_ctrl_endp (.configured_o(configured_o),
.usb_en_o(usb_en),
.addr_o(addr),
.in_data_o(ctrl_in_data),
.in_zlp_o(ctrl_in_zlp),
.in_valid_o(ctrl_in_valid),
.stall_o(ctrl_stall),
.in_bulk_endps_o(in_bulk_endps),
.out_bulk_endps_o(out_bulk_endps),
.in_int_endps_o(in_int_endps),
.out_int_endps_o(out_int_endps),
.in_toggle_reset_o(in_toggle_reset),
.out_toggle_reset_o(out_toggle_reset),
.clk_i(clk_i),
.rstn_i(rstn),
.clk_gate_i(clk_gate_q),
.bus_reset_i(bus_reset),
.out_data_i(sie_out_data),
.out_valid_i(sie_out_valid),
.out_err_i(sie_out_err),
.in_req_i(ctrl2i_in_req),
.setup_i(setup),
.in_data_ack_i(sie_in_data_ack),
.out_ready_i(ctrl2i_out_ready),
.in_ready_i(ctrl2i_in_ready));
genvar i;
generate
for (i = 0; i < CHANNELS; i = i+1) begin : u_bulk_endps
wire bulk2i_in_req, bulk2i_out_ready, bulk2i_in_ready;
assign bulk2i_in_req = (endp == 2*i+1) ? sie_in_req : 1'b0;
assign bulk2i_out_ready = (endp == 2*i+1) ? sie_out_ready : 1'b0;
assign bulk2i_in_ready = (endp == 2*i+1) ? sie_in_ready : 1'b0;
bulk_endp #(.IN_BULK_MAXPACKETSIZE(IN_BULK_MAXPACKETSIZE),
.OUT_BULK_MAXPACKETSIZE(OUT_BULK_MAXPACKETSIZE),
.USE_APP_CLK(USE_APP_CLK),
.APP_CLK_FREQ(APP_CLK_FREQ))
u_bulk_endp (.in_data_o(bulk_in_data[8*i +:8]),
.in_valid_o(bulk_in_valid[i]),
.app_in_ready_o(in_ready_o[i]),
.out_nak_o(bulk_out_nak[i]),
.app_out_valid_o(out_valid_o[i]),
.app_out_data_o(out_data_o[8*i +:8]),
.clk_i(clk_i),
.app_clk_i(app_clk_i),
.rstn_i(rstn),
.clk_gate_i(clk_gate_q),
.bus_reset_i(bus_reset),
.out_data_i(sie_out_data),
.out_valid_i(sie_out_valid),
.out_err_i(sie_out_err),
.in_req_i(bulk2i_in_req),
.in_data_ack_i(sie_in_data_ack),
.app_in_data_i(in_data_i[8*i +:8]),
.app_in_valid_i(in_valid_i[i]),
.out_ready_i(bulk2i_out_ready),
.in_ready_i(bulk2i_in_ready),
.app_out_ready_i(out_ready_i[i]));
end
endgenerate
endmodule |
module ctrl_endp
#(parameter VENDORID = 16'h0000,
parameter PRODUCTID = 16'h0000,
parameter CHANNELS = 'd1,
parameter CTRL_MAXPACKETSIZE = 'd8,
parameter IN_BULK_MAXPACKETSIZE = 'd8,
parameter OUT_BULK_MAXPACKETSIZE = 'd8)
(
// ---- to/from USB_CDC module ---------------------------------
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES.
input rstn_i,
// While rstn_i is low (active low), the module shall be reset.
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
output configured_o,
// While USB_CDC is in configured state, configured_o shall be high.
// When clk_gate_i is high, configured_o shall be updated.
// ---- to/from SIE module ------------------------------------
input bus_reset_i,
// While bus_reset_i is high, the module shall be reset.
// When bus_reset_i is high, the device shall be in DEFAULT_STATE
// When clk_gate_i is high, bus_reset_i shall be updated.
output usb_en_o,
// While device is in POWERED_STATE and bus_reset_i is low, usb_en_o shall be low.
// When clk_gate_i is high, usb_en_o shall be updated.
output [6:0] addr_o,
// addr_o shall be the device address.
// addr_o shall be updated at the end of SET_ADDRESS control transfer.
// When clk_gate_i is high, addr_o shall be updated.
output stall_o,
// While control pipe is addressed and is in stall state, stall_o shall
// be high, otherwise shall be low.
// When clk_gate_i is high, stall_o shall be updated.
output [15:0] in_bulk_endps_o,
// While in_bulk_endps_o[i] is high, endp=i shall be enabled as IN bulk endpoint.
// endp=0 is reserved for IN control endpoint.
// When clk_gate_i is high, in_bulk_endps_o shall be updated.
output [15:0] out_bulk_endps_o,
// While out_bulk_endps_o[i] is high, endp=i shall be enabled as OUT bulk endpoint
// endp=0 is reserved for OUT control endpoint.
// When clk_gate_i is high, out_bulk_endps_o shall be updated.
output [15:0] in_int_endps_o,
// While in_int_endps_o[i] is high, endp=i shall be enabled as IN interrupt endpoint.
// endp=0 is reserved for IN control endpoint.
// When clk_gate_i is high, in_int_endps_o shall be updated.
output [15:0] out_int_endps_o,
// While out_int_endps_i[i] is high, endp=i shall be enabled as OUT interrupt endpoint
// endp=0 is reserved for OUT control endpoint.
// When clk_gate_i is high, out_int_endps_o shall be updated.
output [15:0] out_toggle_reset_o,
// When out_toggle_reset_o[i] is high, data toggle synchronization of
// OUT bulk pipe at endpoint=i shall be reset to DATA0.
// When clk_gate_i is high, out_toggle_reset_o shall be updated.
output [15:0] in_toggle_reset_o,
// When in_toggle_reset_o[i] is high, data toggle synchronization of
// IN bulk pipe at endpoint=i shall be reset to DATA0.
// When clk_gate_i is high, in_toggle_reset_o shall be updated.
output [7:0] in_data_o,
// While in_valid_o is high and in_zlp_o is low, in_data_o shall be valid.
output in_zlp_o,
// While IN Control Endpoint have to reply with zero length packet,
// IN Control Endpoint shall put both in_zlp_o and in_valid_o high.
// When clk_gate_i is high, in_zlp_o shall be updated.
output in_valid_o,
// While IN Control Endpoint have data or zero length packet available,
// IN Control Endpoint shall put in_valid_o high.
// When clk_gate_i is high, in_valid_o shall be updated.
input in_req_i,
// When both in_req_i and in_ready_i are high, a new IN packet shall be requested.
// When clk_gate_i is high, in_req_i shall be updated.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o or zero length
// packet shall be consumed.
// When in_data_o or zlp is consumed, in_ready_i shall be high only for
// one clk_gate_i multi-cycle period.
// When clk_gate_i is high, in_ready_i shall be updated.
input setup_i,
// While last correctly checked PID (USB2.0 8.3.1) is SETUP, setup_i shall
// be high, otherwise shall be low.
// When clk_gate_i is high, setup_i shall be updated.
input in_data_ack_i,
// When in_data_ack_i is high and out_ready_i is high, an ACK packet shall be received.
// When clk_gate_i is high, in_data_ack_i shall be updated.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
// When clk_gate_i is high, out_valid_i shall be updated.
input out_err_i,
// When both out_err_i and out_ready_i are high, SIE shall abort the
// current packet reception and OUT Control Endpoint shall manage the error
// condition.
// When clk_gate_i is high, out_err_i shall be updated.
input out_ready_i
// When both out_valid_i and out_ready_i are high, the out_data_i shall
// be consumed.
// When setup_i is high and out_ready_i is high, a new SETUP transaction shall be
// received.
// When setup_i, out_valid_i and out_err_i are low and out_ready_i is high, the
// on-going OUT packet shall end (EOP).
// out_ready_i shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, out_ready_i shall be updated.
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
function [7:0] master_interface;
input integer channel;
begin
master_interface = 2*channel[6:0];
end
endfunction
function [7:0] slave_interface;
input integer channel;
begin
slave_interface = 2*channel[6:0]+1;
end
endfunction
function [3:0] bulk_endp;
input integer channel;
begin
bulk_endp = 2*channel[2:0]+1;
end
endfunction
function [3:0] int_endp;
input integer channel;
begin
int_endp = 2*channel[2:0]+2;
end
endfunction
function [15:0] bulk_endps;
input integer channels;
integer i;
begin
bulk_endps = 16'b0;
for (i = 0; i < channels; i = i+1) begin
bulk_endps[bulk_endp(i)] = 1'b1;
end
end
endfunction
function [15:0] int_endps;
input integer channels;
integer i;
begin
int_endps = 16'b0;
for (i = 0; i < channels; i = i+1) begin
int_endps[int_endp(i)] = 1'b1;
end
end
endfunction
localparam [15:0] IN_BULK_ENDPS = bulk_endps(CHANNELS);
localparam [15:0] OUT_BULK_ENDPS = bulk_endps(CHANNELS);
localparam [15:0] IN_INT_ENDPS = int_endps(CHANNELS);
localparam [15:0] OUT_INT_ENDPS = 16'b0;
function [7:0] string_index;
input integer channel;
begin
string_index = channel[7:0]+8'd1;
end
endfunction
// String Descriptor Zero (in reverse order)
localparam [8*'h4-1:0] STRING_DESCR_00 = {8'h04, // wLANGID[1] (US English)
8'h09, // wLANGID[0]
8'h03, // bDescriptorType (STRING)
8'h04 // bLength
}; // String Descriptor Zero, USB2.0 9.6.7, page 273-274, Table 9-15
localparam SDL = 'h0A; // STRING_DESCR_XX Length
// String Descriptor (in reverse order)
localparam [8*SDL-1:0] STRING_DESCR_XX = {8'h00, "0",
8'h00, "C",
8'h00, "D",
8'h00, "C",
8'h03, // bDescriptorType (STRING)
SDL[7:0] // bLength
}; // UNICODE String Descriptor, USB2.0 9.6.7, page 273-274, Table 9-16
// Device Descriptor (in reverse order)
localparam [8*'h12-1:0] DEV_DESCR = {8'h01, // bNumConfigurations
8'h00, // iSerialNumber (no string)
8'h00, // iProduct (no string)
8'h00, // iManufacturer (no string)
8'h01, // bcdDevice[1] (1.10)
8'h10, // bcdDevice[0]
PRODUCTID[15:8], // idProduct[1]
PRODUCTID[7:0], // idProduct[0]
VENDORID[15:8], // idVendor[1]
VENDORID[7:0], // idVendor[0]
CTRL_MAXPACKETSIZE[7:0], // bMaxPacketSize0
(CHANNELS>1) ? {
8'h01, // bDeviceProtocol (Interface Association Descriptor)
8'h02, // bDeviceSubClass (Common Class)
8'hEF // bDeviceClass (Miscellaneous Device Class)
} : {
8'h00, // bDeviceProtocol (specified at interface level)
8'h00, // bDeviceSubClass (specified at interface level)
8'h02 // bDeviceClass (Communications Device Class)
},
8'h02, // bcdUSB[1] (2.00)
8'h00, // bcdUSB[0]
8'h01, // bDescriptorType (DEVICE)
8'h12 // bLength
}; // Standard Device Descriptor, USB2.0 9.6.1, page 261-263, Table 9-8
function [8*'h3A-1:0] cdc_descr;
input integer i;
begin
// CDC Interfaces Descriptor (in reverse order)
cdc_descr = {8'h00, // bInterval
8'h00, // wMaxPacketSize[1]
IN_BULK_MAXPACKETSIZE[7:0], // wMaxPacketSize[0]
8'h02, // bmAttributes (bulk)
8'h80+{4'd0, bulk_endp(i)}, // bEndpointAddress (1 IN)
8'h05, // bDescriptorType (ENDPOINT)
8'h07, // bLength
// Standard Endpoint Descriptor, USB2.0 9.6.6, page 269-271, Table 9-13
8'h00, // bInterval
8'h00, // wMaxPacketSize[1]
OUT_BULK_MAXPACKETSIZE[7:0], // wMaxPacketSize[0]
8'h02, // bmAttributes (bulk)
8'h00+{4'd0, bulk_endp(i)}, // bEndpointAddress (1 OUT)
8'h05, // bDescriptorType (ENDPOINT)
8'h07, // bLength
// Standard Endpoint Descriptor, USB2.0 9.6.6, page 269-271, Table 9-13
8'h00, // iInterface (no string)
8'h00, // bInterfaceProtocol
8'h00, // bInterfaceSubClass
8'h0A, // bInterfaceClass (CDC-Data)
8'h02, // bNumEndpoints
8'h00, // bAlternateSetting
slave_interface(i), // bInterfaceNumber
8'h04, // bDescriptorType (INTERFACE)
8'h09, // bLength
// Standard Interface Descriptor, USB2.0 9.6.5, page 267-269, Table 9-12
8'hFF, // bInterval (255 ms)
8'h00, // wMaxPacketSize[1]
8'h08, // wMaxPacketSize[0]
8'h03, // bmAttributes (interrupt)
8'h80+{4'd0, int_endp(i)}, // bEndpointAddress (2 IN)
8'h05, // bDescriptorType (ENDPOINT)
8'h07, // bLength
// Standard Endpoint Descriptor, USB2.0 9.6.6, page 269-271, Table 9-13
slave_interface(i), // bSlaveInterface0
master_interface(i), // bMasterInterface
8'h06, // bDescriptorSubtype (Union Functional)
8'h24, // bDescriptorType (CS_INTERFACE)
8'h05, // bFunctionLength
// Union Functional Descriptor, CDC1.1 5.2.3.8, Table 33
8'h00, // bmCapabilities (none)
8'h02, // bDescriptorSubtype (Abstract Control Management Functional)
8'h24, // bDescriptorType (CS_INTERFACE)
8'h04, // bFunctionLength
// Abstract Control Management Functional Descriptor, CDC1.1 5.2.3.3, Table 28
8'h01, // bDataInterface
8'h00, // bmCapabilities (no call mgmnt)
8'h01, // bDescriptorSubtype (Call Management Functional)
8'h24, // bDescriptorType (CS_INTERFACE)
8'h05, // bFunctionLength
// Call Management Functional Descriptor, CDC1.1 5.2.3.2, Table 27
8'h01, // bcdCDC[1] (1.1)
8'h10, // bcdCDC[0]
8'h00, // bDescriptorSubtype (Header Functional)
8'h24, // bDescriptorType (CS_INTERFACE)
8'h05, // bFunctionLength
// Header Functional Descriptor, CDC1.1 5.2.3.1, Table 26
(CHANNELS>1) ? string_index(i) : 8'h00, // iInterface (string / no string)
8'h01, // bInterfaceProtocol (AT Commands in ITU V.25ter)
8'h02, // bInterfaceSubClass (Abstract Control Model)
8'h02, // bInterfaceClass (Communications Device Class)
8'h01, // bNumEndpoints
8'h00, // bAlternateSetting
master_interface(i), // bInterfaceNumber
8'h04, // bDescriptorType (INTERFACE)
8'h09 // bLength
}; // Standard Interface Descriptor, USB2.0 9.6.5, page 267-269, Table 9-12
end
endfunction
function [8*'h08-1:0] ia_descr;
input integer i;
begin
// Interfaces Association Descriptor (in reverse order)
ia_descr = {8'h00, // iFunction (no string)
8'h01, // bFunctionProtocol (AT Commands in ITU V.25ter)
8'h02, // bFunctionSubClass (Abstract Control Model)
8'h02, // bFunctionClass (Communications Device Class)
8'h02, // bInterfaceCount
master_interface(i), // bFirstInterface
8'h0B, // bDescriptorType (INTERFACE ASSOCIATION)
8'h08 // bLength
}; // Interface Association Descriptor, USB2.0 ECN 9.X.Y, page 4-5, Table 9-Z
end
endfunction
localparam CDL = (CHANNELS>1) ? ('h3A+'h08)*CHANNELS+'h09 : 'h3A+'h09; // CONF_DESCR Length
function [8*CDL-1:0] conf_descr;
input dummy;
integer i;
begin
conf_descr[0 +:8*'h09] = {8'h32, // bMaxPower (100mA)
8'h80, // bmAttributes (bus powered, no remote wakeup)
8'h00, // iConfiguration (no string)
8'h01, // bConfigurationValue
8'd2*CHANNELS[7:0], // bNumInterfaces
CDL[15:8], // wTotalLength[1]
CDL[7:0], // wTotalLength[0]
8'h02, // bDescriptorType (CONFIGURATION)
8'h09 // bLength
}; // Standard Configuration Descriptor, USB2.0 9.6.3, page 264-266, Table 9-10
if (CHANNELS>1) begin
for (i = 0; i < CHANNELS; i = i+1) begin
conf_descr[i*8*('h3A+'h08)+8*'h09 +:8*('h3A+'h08)] = {cdc_descr(i), ia_descr(i)};
end
end else begin
conf_descr[8*'h09 +:8*'h3A] = cdc_descr('d0);
end
end
endfunction
// Configuration Descriptor (in reverse order)
localparam [8*CDL-1:0] CONF_DESCR = conf_descr(0);
localparam [2:0] ST_IDLE = 3'd0,
ST_STALL = 3'd1,
ST_SETUP = 3'd2,
ST_IN_DATA = 3'd3,
ST_OUT_DATA = 3'd4,
ST_PRE_IN_STATUS = 3'd5,
ST_IN_STATUS = 3'd6,
ST_OUT_STATUS = 3'd7;
localparam [1:0] REC_DEVICE = 2'd0,
REC_INTERFACE = 2'd1,
REC_ENDPOINT = 2'd2;
// Supported Standard Requests
localparam [7:0] STD_REQ_GET_STATUS = 'd0,
STD_REQ_CLEAR_FEATURE = 'd1,
STD_REQ_SET_ADDRESS = 'd5,
STD_REQ_GET_DESCRIPTOR = 'd6,
STD_REQ_GET_CONFIGURATION = 'd8,
STD_REQ_SET_CONFIGURATION = 'd9,
STD_REQ_GET_INTERFACE = 'd10;
// Supported ACM Class Requests
localparam [7:0] ACM_REQ_SET_LINE_CODING = 'h20,
ACM_REQ_GET_LINE_CODING = 'h21,
ACM_REQ_SET_CONTROL_LINE_STATE = 'h22,
ACM_REQ_SEND_BREAK = 'h23;
localparam [3:0] REQ_NONE = 4'd0,
REQ_CLEAR_FEATURE = 4'd1,
REQ_GET_CONFIGURATION = 4'd2,
REQ_GET_DESCRIPTOR = 4'd3,
REQ_GET_DESCRIPTOR_DEVICE = 4'd4,
REQ_GET_DESCRIPTOR_CONFIGURATION = 4'd5,
REQ_GET_DESCRIPTOR_STRING = 4'd6,
REQ_GET_INTERFACE = 4'd7,
REQ_GET_STATUS = 4'd8,
REQ_SET_ADDRESS = 4'd9,
REQ_SET_CONFIGURATION = 4'd10,
REQ_DUMMY = 4'd11,
REQ_UNSUPPORTED = 4'd12;
localparam [1:0] POWERED_STATE = 2'd0,
DEFAULT_STATE = 2'd1,
ADDRESS_STATE = 2'd2,
CONFIGURED_STATE = 2'd3;
localparam BC_WIDTH = ceil_log2(1+`max('h12, `max(CDL, (CHANNELS>1) ? SDL : 0)));
localparam [15:0] CTRL_ENDPS = 16'h01;
reg [2:0] state_q, state_d;
reg [BC_WIDTH-1:0] byte_cnt_q, byte_cnt_d;
reg [BC_WIDTH-1:0] max_length_q, max_length_d;
reg in_dir_q, in_dir_d;
reg class_q, class_d;
reg [1:0] rec_q, rec_d;
reg [3:0] req_q, req_d;
reg [7:0] string_index_q, string_index_d;
reg [1:0] dev_state_q, dev_state_d;
reg [1:0] dev_state_qq, dev_state_dd;
reg [6:0] addr_q, addr_d;
reg [6:0] addr_qq, addr_dd;
reg in_endp_q, in_endp_d;
reg [3:0] endp_q, endp_d;
reg [7:0] in_data;
reg in_zlp;
reg in_valid;
reg [15:0] in_toggle_reset, out_toggle_reset;
wire rstn;
wire [15:0] in_toggle_endps, out_toggle_endps;
assign configured_o = (dev_state_qq == CONFIGURED_STATE) ? 1'b1 : 1'b0;
assign addr_o = addr_qq;
assign stall_o = (state_q == ST_STALL) ? 1'b1 : 1'b0;
assign in_data_o = in_data;
assign in_zlp_o = in_zlp;
assign in_valid_o = in_valid;
assign in_bulk_endps_o = IN_BULK_ENDPS;
assign out_bulk_endps_o = OUT_BULK_ENDPS;
assign in_int_endps_o = IN_INT_ENDPS;
assign out_int_endps_o = OUT_INT_ENDPS;
assign in_toggle_reset_o = in_toggle_reset;
assign out_toggle_reset_o = out_toggle_reset;
assign in_toggle_endps = IN_BULK_ENDPS|IN_INT_ENDPS|CTRL_ENDPS;
assign out_toggle_endps = OUT_BULK_ENDPS|OUT_INT_ENDPS|CTRL_ENDPS;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
dev_state_qq <= POWERED_STATE;
end else begin
if (clk_gate_i) begin
if (bus_reset_i)
dev_state_qq <= DEFAULT_STATE;
else if (in_ready_i | out_ready_i)
dev_state_qq <= dev_state_dd;
end
end
end
assign usb_en_o = (dev_state_qq == POWERED_STATE) ? 1'b0 : 1'b1;
assign rstn = rstn_i & ~bus_reset_i;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
state_q <= ST_IDLE;
byte_cnt_q <= 'd0;
max_length_q <= 'd0;
in_dir_q <= 1'b0;
class_q <= 1'b0;
rec_q <= REC_DEVICE;
req_q <= REQ_NONE;
string_index_q <= 'd0;
dev_state_q <= DEFAULT_STATE;
addr_q <= 7'd0;
addr_qq <= 7'd0;
in_endp_q <= 1'b0;
endp_q <= 4'b0;
end else begin
if (clk_gate_i) begin
if (in_ready_i | out_ready_i) begin
byte_cnt_q <= 'd0;
if (out_ready_i & out_err_i) begin
if (state_q != ST_STALL)
state_q <= ST_IDLE;
end else if (out_ready_i & setup_i) begin
state_q <= ST_SETUP;
end else if ((in_ready_i == 1'b1 &&
((state_q == ST_SETUP) ||
(state_q == ST_OUT_DATA && in_req_i == 1'b0) ||
(state_q == ST_PRE_IN_STATUS && in_req_i == 1'b0) ||
(state_q == ST_IN_STATUS && in_data_ack_i == 1'b0) ||
(state_q == ST_OUT_STATUS && in_req_i == 1'b0 && in_data_ack_i == 1'b0))) ||
(out_ready_i == 1'b1 &&
((state_q == ST_IN_DATA) ||
(state_q == ST_PRE_IN_STATUS) ||
(state_q == ST_IN_STATUS) ||
(state_q == ST_OUT_STATUS && out_valid_i == 1'b1)))) begin
state_q <= ST_STALL;
end else begin
state_q <= state_d;
byte_cnt_q <= byte_cnt_d;
max_length_q <= max_length_d;
in_dir_q <= in_dir_d;
class_q <= class_d;
rec_q <= rec_d;
req_q <= req_d;
string_index_q <= (CHANNELS>1) ? string_index_d : 8'd0;
dev_state_q <= dev_state_d;
addr_q <= addr_d;
addr_qq <= addr_dd;
in_endp_q <= in_endp_d;
endp_q <= endp_d;
end
end
end
end
end
always @(/*AS*/addr_q or addr_qq or byte_cnt_q or class_q
or dev_state_q or dev_state_qq or endp_q or in_data_ack_i
or in_dir_q or in_endp_q or in_req_i or in_toggle_endps
or max_length_q or out_data_i or out_toggle_endps
or out_valid_i or rec_q or req_q or state_q
or string_index_q) begin
state_d = state_q;
byte_cnt_d = 'd0;
max_length_d = max_length_q;
in_dir_d = in_dir_q;
class_d = class_q;
rec_d = rec_q;
req_d = req_q;
string_index_d = string_index_q;
dev_state_d = dev_state_q;
dev_state_dd = dev_state_qq;
addr_d = addr_q;
addr_dd = addr_qq;
in_endp_d = in_endp_q;
endp_d = endp_q;
in_data = 8'd0;
in_zlp = 1'b0;
in_valid = 1'b0;
in_toggle_reset = 16'b0;
out_toggle_reset = 16'b0;
case (state_q)
ST_IDLE, ST_STALL : begin
end
ST_SETUP : begin
if (out_valid_i) begin
byte_cnt_d = byte_cnt_q + 1;
case (byte_cnt_q)
'd0 : begin // bmRequestType
in_dir_d = out_data_i[7];
class_d = out_data_i[5];
rec_d = out_data_i[1:0];
if (out_data_i[6] == 1'b1 || |out_data_i[4:2] != 1'b0 || out_data_i[1:0] == 2'b11)
req_d = REQ_UNSUPPORTED;
else
req_d = REQ_NONE;
end
'd1 : begin // bRequest
req_d = REQ_UNSUPPORTED;
if (req_q == REQ_NONE) begin
if (class_q == 1'b0) begin
case (out_data_i)
STD_REQ_CLEAR_FEATURE : begin
if (in_dir_q == 1'b0 && dev_state_qq != DEFAULT_STATE)
req_d = REQ_CLEAR_FEATURE;
end
STD_REQ_GET_CONFIGURATION : begin
if (in_dir_q == 1'b1 && rec_q == REC_DEVICE && dev_state_qq != DEFAULT_STATE)
req_d = REQ_GET_CONFIGURATION;
end
STD_REQ_GET_DESCRIPTOR : begin
if (in_dir_q == 1'b1 && rec_q == REC_DEVICE)
req_d = REQ_GET_DESCRIPTOR;
end
STD_REQ_GET_INTERFACE : begin
if (in_dir_q == 1'b1 && rec_q == REC_INTERFACE && dev_state_qq == CONFIGURED_STATE)
req_d = REQ_GET_INTERFACE;
end
STD_REQ_GET_STATUS : begin
if (in_dir_q == 1'b1 && dev_state_qq != DEFAULT_STATE)
req_d = REQ_GET_STATUS;
end
STD_REQ_SET_ADDRESS : begin
if (in_dir_q == 1'b0 && rec_q == REC_DEVICE)
req_d = REQ_SET_ADDRESS;
end
STD_REQ_SET_CONFIGURATION : begin
if (in_dir_q == 1'b0 && rec_q == REC_DEVICE && dev_state_qq != DEFAULT_STATE)
req_d = REQ_SET_CONFIGURATION;
end
default : begin
end
endcase
end else begin
if (dev_state_qq == CONFIGURED_STATE &&
((out_data_i == ACM_REQ_SET_LINE_CODING) ||
(out_data_i == ACM_REQ_GET_LINE_CODING) ||
(out_data_i == ACM_REQ_SET_CONTROL_LINE_STATE) ||
(out_data_i == ACM_REQ_SEND_BREAK)))
req_d = REQ_DUMMY;
end
end
end
'd2 : begin // wValue LSB
case (req_q)
REQ_CLEAR_FEATURE : begin // ENDPOINT_HALT
if (!(rec_q == REC_ENDPOINT && |out_data_i == 1'b0))
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR : begin
if (CHANNELS > 1 && out_data_i <= CHANNELS)
string_index_d = out_data_i;
else if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_INTERFACE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (out_data_i[7] == 1'b0)
addr_d = out_data_i[6:0];
else
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (out_data_i == 8'd0)
dev_state_d = ADDRESS_STATE;
else if (out_data_i == 8'd1)
dev_state_d = CONFIGURED_STATE;
else
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
'd3 : begin // wValue MSB
case (req_q)
REQ_CLEAR_FEATURE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR : begin
if (out_data_i == 8'd1 && |string_index_q == 1'b0)
req_d = REQ_GET_DESCRIPTOR_DEVICE;
else if (out_data_i == 8'd2 && |string_index_q == 1'b0)
req_d = REQ_GET_DESCRIPTOR_CONFIGURATION;
else if (CHANNELS > 1 && out_data_i == 8'd3)
req_d = REQ_GET_DESCRIPTOR_STRING;
else
req_d = REQ_UNSUPPORTED;
end
REQ_GET_INTERFACE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
'd4 : begin // wIndex LSB
in_endp_d = out_data_i[7];
endp_d = out_data_i[3:0];
case (req_q)
REQ_CLEAR_FEATURE : begin
if (!((rec_q == REC_ENDPOINT) &&
((out_data_i[7] == 1'b1 && in_toggle_endps[out_data_i[3:0]] == 1'b1) ||
(out_data_i[7] == 1'b0 && out_toggle_endps[out_data_i[3:0]] == 1'b1))))
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_DEVICE, REQ_GET_DESCRIPTOR_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_STRING : begin
end
REQ_GET_INTERFACE : begin
if (!(out_data_i < 2*CHANNELS))
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (!(((rec_q == REC_DEVICE) && (|out_data_i == 1'b0)) ||
((rec_q == REC_INTERFACE) && (out_data_i < 2*CHANNELS)) ||
((rec_q == REC_ENDPOINT) &&
((out_data_i[7] == 1'b1 && in_toggle_endps[out_data_i[3:0]] == 1'b1) ||
(out_data_i[7] == 1'b0 && out_toggle_endps[out_data_i[3:0]] == 1'b1)))))
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
'd5 : begin // wIndex MSB
case (req_q)
REQ_CLEAR_FEATURE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_DEVICE, REQ_GET_DESCRIPTOR_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_STRING : begin
end
REQ_GET_INTERFACE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
'd6 : begin // wLength LSB
max_length_d[`min(BC_WIDTH-1, 7):0] = out_data_i[`min(BC_WIDTH-1, 7):0];
case (req_q)
REQ_CLEAR_FEATURE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (out_data_i != 8'd1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_DEVICE, REQ_GET_DESCRIPTOR_CONFIGURATION, REQ_GET_DESCRIPTOR_STRING : begin
if (BC_WIDTH < 8 && |out_data_i[7:`min(BC_WIDTH, 7)] == 1'b1)
max_length_d = {BC_WIDTH{1'b1}};
end
REQ_GET_INTERFACE : begin
if (out_data_i != 8'd1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (out_data_i != 8'd2)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
'd7 : begin // wLength MSB
if (BC_WIDTH > 8)
max_length_d[BC_WIDTH-1:`min(8, BC_WIDTH-1)] = out_data_i[BC_WIDTH-1-`min(8, BC_WIDTH-1):0];
case (req_q)
REQ_CLEAR_FEATURE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_DESCRIPTOR_DEVICE, REQ_GET_DESCRIPTOR_CONFIGURATION, REQ_GET_DESCRIPTOR_STRING : begin
if (BC_WIDTH < 16 && |out_data_i[7:`min(`max(BC_WIDTH-8, 0), 7)] == 1'b1)
max_length_d = {BC_WIDTH{1'b1}};
end
REQ_GET_INTERFACE : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_GET_STATUS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_ADDRESS : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
REQ_SET_CONFIGURATION : begin
if (|out_data_i == 1'b1)
req_d = REQ_UNSUPPORTED;
end
default : begin
end
endcase
end
default : begin
end
endcase
end else begin // Setup Stage EOP
if (byte_cnt_q == 'd8) begin
if (req_q == REQ_UNSUPPORTED)
state_d = ST_STALL;
else if (in_dir_q == 1'b1) begin // Control Read Data Stage
state_d = ST_IN_DATA;
end else begin
if (max_length_q == 'd0) begin // No-data Control Status Stage
state_d = ST_PRE_IN_STATUS;
end else begin // Control Write Data Stage
state_d = ST_OUT_DATA;
end
end
end else
state_d = ST_STALL;
end
end
ST_IN_DATA : begin
byte_cnt_d = byte_cnt_q;
if (byte_cnt_q == max_length_q ||
(byte_cnt_q == 'h12 && req_q == REQ_GET_DESCRIPTOR_DEVICE) ||
(byte_cnt_q == CDL[BC_WIDTH-1:0] && req_q == REQ_GET_DESCRIPTOR_CONFIGURATION) ||
(byte_cnt_q == 'h04 && req_q == REQ_GET_DESCRIPTOR_STRING && CHANNELS > 1 && string_index_q == 'h00) ||
(byte_cnt_q == SDL[BC_WIDTH-1:0] && req_q == REQ_GET_DESCRIPTOR_STRING && CHANNELS > 1 && string_index_q != 'h00 && string_index_q <= CHANNELS)) begin
if (in_data_ack_i) // Control Read Status Stage
state_d = ST_OUT_STATUS;
else if (~in_req_i)
state_d = ST_STALL;
end else begin
if (~in_req_i & ~in_data_ack_i)
byte_cnt_d = byte_cnt_q + 1;
case (req_q)
REQ_GET_CONFIGURATION : begin
if (dev_state_qq == ADDRESS_STATE) begin
in_data = 8'd0;
in_valid = 1'b1;
end else if (dev_state_qq == CONFIGURED_STATE) begin
in_data = 8'd1;
in_valid = 1'b1;
end
end
REQ_GET_DESCRIPTOR_DEVICE : begin
in_data = DEV_DESCR[{byte_cnt_q[ceil_log2('h12)-1:0], 3'd0} +:8];
in_valid = 1'b1;
end
REQ_GET_DESCRIPTOR_CONFIGURATION : begin
in_data = CONF_DESCR[{byte_cnt_q[ceil_log2(CDL)-1:0], 3'd0} +:8];
in_valid = 1'b1;
end
REQ_GET_DESCRIPTOR_STRING : begin
if(CHANNELS > 1 ) begin
if (string_index_q == 8'd0) begin
in_data = STRING_DESCR_00[{byte_cnt_q[ceil_log2('h4)-1:0], 3'd0} +:8];
in_valid = 1'b1;
end else if (string_index_q <= CHANNELS) begin
if (byte_cnt_q == SDL-2) begin
in_data = STRING_DESCR_XX[{byte_cnt_q[ceil_log2(SDL)-1:0], 3'd0} +:8] + string_index_q;
in_valid = 1'b1;
end else if (byte_cnt_q <= SDL-1) begin
in_data = STRING_DESCR_XX[{byte_cnt_q[ceil_log2(SDL)-1:0], 3'd0} +:8];
in_valid = 1'b1;
end
end
end
end
REQ_GET_INTERFACE : begin
in_data = 8'd0;
in_valid = 1'b1;
end
REQ_GET_STATUS : begin
in_data = 8'd0;
in_valid = 1'b1;
end
default : begin
in_data = 8'd0;
in_valid = 1'b1;
end
endcase
end
end
ST_OUT_DATA : begin
if (in_req_i) // Control Write Status Stage
state_d = ST_IN_STATUS;
end
ST_PRE_IN_STATUS : begin
state_d = ST_IN_STATUS;
end
ST_IN_STATUS : begin
byte_cnt_d = byte_cnt_q;
in_zlp = 1'b1;
in_valid = 1'b1;
state_d = ST_IDLE; // Status Stage ACK
case (req_q)
REQ_SET_ADDRESS : begin
addr_dd = addr_q;
if (addr_q == 7'd0)
dev_state_dd = DEFAULT_STATE;
else
dev_state_dd = ADDRESS_STATE;
end
REQ_CLEAR_FEATURE : begin
if (in_endp_q == 1'b1)
in_toggle_reset[endp_q] = 1'b1;
else
out_toggle_reset[endp_q] = 1'b1;
end
REQ_SET_CONFIGURATION : begin
dev_state_dd = dev_state_q;
in_toggle_reset = 16'hFFFF;
out_toggle_reset = 16'hFFFF;
end
default : begin
end
endcase
end
ST_OUT_STATUS : begin
if (~in_req_i & ~in_data_ack_i) begin // Status Stage EOP
state_d = ST_IDLE;
end
end
default : begin
state_d = ST_IDLE;
end
endcase
end
endmodule |
module phy_rx
#(parameter BIT_SAMPLES = 'd4)
(
// ---- to/from SIE module ------------------------------------
output [7:0] rx_data_o,
// While rx_valid_o is high, the rx_data_o shall be valid and both
// rx_valid_o and rx_data_o shall not change until consumed.
output rx_valid_o,
// When both rx_valid_o and rx_ready_o are high, rx_data_o shall be consumed by SIE module.
// When clk_gate_i is high, rx_valid_o shall be updated.
output rx_err_o,
// When both rx_err_o and rx_ready_o are high, PHY_RX module shall abort the
// current packet reception and SIE module shall manage the error condition.
// When clk_gate_i is high, rx_err_o shall be updated.
output bus_reset_o,
// When dp_rx_i/dn_rx_i change and stay in SE0 condition for 2.5us, bus_reset_o shall be high.
// When dp_rx_i/dn_rx_i change from SE0 condition, bus_reset_o shall return low.
// While usb_detach_i is high and a usb detach has started, bus_reset_o shall be high.
// When clk_gate_i is high, bus_reset_o shall be updated.
output rx_ready_o,
// rx_ready_o shall be high only for one clk_gate_i multi-cycle period.
// While rx_valid_o and rx_err_o are both low, rx_ready_o shall be high to signal the
// end of packet (EOP).
// When clk_gate_i is high, rx_ready_o shall be updated.
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES.
input rstn_i,
// While rstn_i is low (active low), the module shall be reset.
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
input rx_en_i,
// While rx_en_i is low, the module shall be disabled.
// When rx_en_i changes from low to high, the module shall start monitoring the dp/dn
// lines for the beginning of a new packet.
// When clk_gate_i is high, rx_en_i shall be updated.
input usb_detach_i,
// When usb_detach_i is high, a USB detach process shall be initiated.
// When usb_detach_i changes from high to low, the attaching timing process shall begin.
// When clk_gate_i is high, usb_detach_i shall be updated.
// ---- to/from USB bus ------------------------------------------
output dp_pu_o,
// While dp_pu_o is high, a 1.5KOhm resistor shall pull-up the dp line.
// At power-on or when usb_detach_i is high, dp_pu_o shall be low.
// After TSIGATT time from power-on or from usb_detach_i change to low, dp_pu_o shall be high.
input dp_rx_i,
input dn_rx_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
reg [2:0] dp_q, dn_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
dp_q <= 3'b000;
dn_q <= 3'b000;
end else begin
dp_q <= {dp_rx_i, dp_q[2:1]};
dn_q <= {dn_rx_i, dn_q[2:1]};
end
end
localparam [1:0] SE0 = 2'd0,
DJ = 2'd1,
DK = 2'd2,
SE1 = 2'd3;
reg [1:0] nrzi;
always @(/*AS*/dn_q or dp_q) begin
if (dp_q[0] == 1'b1 && dn_q[0] == 1'b0)
nrzi = DJ;
else if (dp_q[0] == 1'b0 && dn_q[0] == 1'b1)
nrzi = DK;
else if (dp_q[0] == 1'b0 && dn_q[0] == 1'b0)
nrzi = SE0;
else // dp or dn at 1'bX too
nrzi = SE1;
end
reg [ceil_log2(BIT_SAMPLES)-1:0] sample_cnt_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
sample_cnt_q <= 'd0;
end else begin
if (dp_q[1] == dp_q[0] && dn_q[1] == dn_q[0]) begin
if ({1'b0, sample_cnt_q} == BIT_SAMPLES-1)
sample_cnt_q <= 'd0;
else
sample_cnt_q <= sample_cnt_q + 1;
end else begin // dp or dn at 1'bX too
sample_cnt_q <= 'd0;
end
end
end
localparam VALID_SAMPLES = BIT_SAMPLES/2; // consecutive valid samples
reg [3:0] nrzi_q;
reg se0_q;
wire sample_clk;
assign sample_clk = ({1'b0, sample_cnt_q} == (VALID_SAMPLES-1)) ? 1'b1 : 1'b0;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
nrzi_q <= {SE0, SE0};
se0_q <= 1'b0;
end else begin
if (sample_clk) begin
nrzi_q <= {nrzi, nrzi_q[3:2]};
end
if (clk_gate_i) begin
if (nrzi_q[1:0] == SE0 && nrzi_q[3:2] == SE0)
se0_q <= 1'b1;
else
se0_q <= 1'b0;
end
end
end
localparam CNT_WIDTH = ceil_log2((2**14+1)*12);
localparam [2:0] ST_RESET = 3'd0,
ST_DETACHED = 3'd1,
ST_ATTACHED = 3'd2,
ST_ENABLED = 3'd3,
ST_DETACH = 3'd4;
reg [CNT_WIDTH-1:0] cnt_q, cnt_d;
reg [2:0] state_q, state_d;
reg dp_pu_q, dp_pu_d;
reg bus_reset_q, bus_reset_d;
reg rx_en_q;
assign dp_pu_o = dp_pu_q;
assign bus_reset_o = bus_reset_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
cnt_q <= 'd0;
state_q <= ST_RESET;
dp_pu_q <= 1'b0;
bus_reset_q <= 1'b0;
rx_en_q <= 1'b0;
end else begin
if (clk_gate_i) begin
cnt_q <= cnt_d;
state_q <= state_d;
dp_pu_q <= dp_pu_d;
bus_reset_q <= bus_reset_d;
end
if (sample_clk) begin
if (rx_en_i == 1'b1 && state_q == ST_ENABLED)
rx_en_q <= 1'b1;
else
rx_en_q <= 1'b0;
end
end
end
always @(/*AS*/bus_reset_q or cnt_q or se0_q or state_q
or usb_detach_i) begin
cnt_d = 'd0;
state_d = state_q;
dp_pu_d = 1'b0;
bus_reset_d = 1'b0;
if (usb_detach_i == 1'b1 && state_q != ST_DETACH) begin
state_d = ST_DETACH;
end else begin
case (state_q)
ST_RESET : begin
state_d = ST_DETACHED;
end
ST_DETACHED : begin
cnt_d = cnt_q + 1;
if (cnt_q[CNT_WIDTH-1 -:2] == 2'b11) // TSIGATT=16ms < 100ms (USB2.0 Tab.7-14 pag.188)
state_d = ST_ATTACHED;
end
ST_ATTACHED : begin
cnt_d = cnt_q + 1;
dp_pu_d = 1'b1;
if (cnt_q[CNT_WIDTH-1-8 -:2] == 2'b11) // 16ms + 64us
state_d = ST_ENABLED;
end
ST_ENABLED : begin
dp_pu_d = 1'b1;
bus_reset_d = bus_reset_q & se0_q;
if (se0_q) begin
cnt_d = cnt_q + 1;
if (cnt_q[5] == 1'b1) // 2.5us < TDETRST=2.67us < 10ms (USB2.0 Tab.7-14 pag.188)
bus_reset_d = 1'b1;
end
end
ST_DETACH : begin
bus_reset_d = 1'b1;
if (~usb_detach_i)
state_d = ST_DETACHED;
end
default : begin
state_d = ST_RESET;
end
endcase
end
end
localparam [2:0] ST_RX_IDLE = 3'd0,
ST_RX_SYNC = 3'd1,
ST_RX_DATA = 3'd2,
ST_RX_EOP = 3'd3,
ST_RX_ERR = 3'd4;
reg [2:0] rx_state_q, rx_state_d;
reg [8:0] shift_register_q, shift_register_d;
reg [7:0] rx_data_q, rx_data_d;
reg [2:0] stuffing_cnt_q, stuffing_cnt_d;
assign rx_data_o = rx_data_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rx_state_q <= ST_RX_IDLE;
shift_register_q <= 9'b100000000;
rx_data_q <= 8'd0;
stuffing_cnt_q <= 3'd0;
end else begin
if (sample_clk) begin
rx_state_q <= rx_state_d;
shift_register_q <= shift_register_d;
rx_data_q <= rx_data_d;
stuffing_cnt_q <= stuffing_cnt_d;
end
end
end
reg rx_valid;
reg rx_err;
reg rx_eop;
always @(/*AS*/nrzi_q or rx_data_q or rx_en_q or rx_state_q
or shift_register_q or stuffing_cnt_q) begin
rx_state_d = rx_state_q;
shift_register_d = 9'b100000000;
rx_data_d = rx_data_q;
stuffing_cnt_d = 3'd0;
rx_valid = 1'b0;
rx_err = 1'b0;
rx_eop = 1'b0;
if (~rx_en_q) begin
rx_state_d = ST_RX_IDLE;
end else begin
case (rx_state_q)
ST_RX_IDLE : begin
if (nrzi_q[1:0] == DJ && nrzi_q[3:2] == DK) begin
rx_state_d = ST_RX_SYNC;
end
end
ST_RX_SYNC : begin
if ((nrzi_q[3:2] == SE1) || (nrzi_q[3:2] == SE0)) begin
rx_state_d = ST_RX_IDLE;
end else begin
if (nrzi_q[1:0] == nrzi_q[3:2]) begin
if (shift_register_q[8:3] == 6'b000000 && nrzi_q[3:2] == DK) begin
rx_state_d = ST_RX_DATA;
stuffing_cnt_d = stuffing_cnt_q + 1;
end else begin
rx_state_d = ST_RX_IDLE;
end
end else begin
shift_register_d = {1'b0, shift_register_q[8:1]};
end
end
end
ST_RX_DATA : begin
if (nrzi_q[3:2] == SE1) begin
rx_state_d = ST_RX_ERR;
end else if (nrzi_q[3:2] == SE0) begin
// 1 or 2 SE0s for EOP: USB2.0 Tab.7-2 pag.145
// dribble bit: USB2.0 Fig.7-33 pag.158
if (shift_register_q == 9'b110000000) begin
rx_state_d = ST_RX_EOP;
end else if (shift_register_q[0] == 1'b1 && stuffing_cnt_q != 3'd6) begin
shift_register_d = 9'b110000000;
rx_data_d = shift_register_q[8:1];
rx_valid = 1'b1;
end else begin
rx_state_d = ST_RX_ERR;
end
end else if (nrzi_q[1:0] == SE0) begin
rx_state_d = ST_RX_ERR;
end else if (stuffing_cnt_q == 3'd6) begin
if (nrzi_q[1:0] == nrzi_q[3:2]) begin
rx_state_d = ST_RX_ERR;
end else begin
shift_register_d = shift_register_q;
end
end else begin
if (nrzi_q[1:0] == nrzi_q[3:2]) begin
shift_register_d[8] = 1'b1;
stuffing_cnt_d = stuffing_cnt_q + 1;
end else begin
shift_register_d[8] = 1'b0;
end
if (shift_register_q[0] == 1'b1) begin
shift_register_d[7:0] = 8'b10000000;
rx_data_d = shift_register_q[8:1];
rx_valid = 1'b1;
end else begin
shift_register_d[7:0] = shift_register_q[8:1];
end
end
end
ST_RX_EOP : begin
if (nrzi_q[3:2] == DJ) begin
rx_state_d = ST_RX_IDLE;
rx_eop = 1'b1;
end else begin
rx_state_d = ST_RX_ERR;
end
end
ST_RX_ERR : begin
rx_state_d = ST_RX_IDLE;
rx_err = 1'b1;
end
default : begin
rx_state_d = ST_RX_ERR;
end
endcase
end
end
reg rx_valid_q, rx_valid_qq;
reg rx_err_q, rx_err_qq;
reg rx_eop_q, rx_eop_qq;
assign rx_ready_o = rx_valid_qq | rx_err_qq | rx_eop_qq;
assign rx_valid_o = rx_valid_qq;
assign rx_err_o = rx_err_qq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rx_valid_q <= 1'b0;
rx_err_q <= 1'b0;
rx_eop_q <= 1'b0;
rx_valid_qq <= 1'b0;
rx_err_qq <= 1'b0;
rx_eop_qq <= 1'b0;
end else begin
if (sample_clk) begin
if (rx_valid)
rx_valid_q <= 1'b1;
if (rx_err)
rx_err_q <= 1'b1;
if (rx_eop)
rx_eop_q <= 1'b1;
end
if (clk_gate_i) begin
if ((rx_valid & sample_clk) | rx_valid_q) begin
rx_valid_qq <= 1'b1;
rx_valid_q <= 1'b0;
end else begin
rx_valid_qq <= 1'b0;
end
if ((rx_err & sample_clk) | rx_err_q) begin
rx_err_qq <= 1'b1;
rx_err_q <= 1'b0;
end else begin
rx_err_qq <= 1'b0;
end
if ((rx_eop & sample_clk) | rx_eop_q) begin
rx_eop_qq <= 1'b1;
rx_eop_q <= 1'b0;
end else begin
rx_eop_qq <= 1'b0;
end
end
end
end
endmodule |
module in_fifo
#(parameter IN_MAXPACKETSIZE = 'd8,
parameter USE_APP_CLK = 0,
parameter APP_CLK_FREQ = 12) // app_clk frequency in MHz
(
// ---- to/from Application ------------------------------------
input app_clk_i,
input app_rstn_i,
// While app_rstn_i is low (active low), the app_clk_i'ed registers shall be reset
input [7:0] app_in_data_i,
input app_in_valid_i,
// While app_in_valid_i is high, app_in_data_i shall be valid.
output app_in_ready_o,
// When both app_in_ready_o and app_in_valid_i are high, app_in_data_i shall
// be consumed.
// ---- from top module ---------------------------------------
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES
input rstn_i,
// While rstn_i is low (active low), the clk_i'ed registers shall be reset
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
output in_empty_o,
// While the IN FIFO is empty and there is no unconfirmed data waiting for ACK packet,
// in_empty_o shall be high.
// When clk_gate_i is high, in_empty_o shall be updated.
output in_full_o,
// While the IN FIFO is full, including the presence of unconfirmed data waiting for ACK packet,
// in_full_o shall be high.
// When clk_gate_i is high, in_full_o shall be updated.
// ---- to/from SIE module ------------------------------------
output [7:0] in_data_o,
// While in_valid_o is high, in_data_o shall be valid.
output in_valid_o,
// While the IN FIFO is not empty, in_valid_o shall be high.
// When in_valid_o is low, either in_req_i or in_data_ack_i shall be high
// at next in_ready_i high.
// When both in_ready_i and clk_gate_i are high, in_valid_o shall be updated.
// When clk_gate_i is high, in_valid_o shall be updated.
input in_req_i,
// When both in_req_i and in_ready_i are high, a new IN packet shall be requested.
// When clk_gate_i is high, in_req_i shall be updated.
input in_ready_i,
// When both in_req_i and in_data_ack_i are low and in_ready_i is high,
// in_valid_o shall be high and in_data_o shall be consumed.
// in_ready_i shall be high only for one clk_gate_i multi-cycle period.
// When clk_gate_i is high, in_ready_i shall be updated.
input in_data_ack_i
// When both in_data_ack_i and in_ready_i are high, an ACK packet shall be received.
// When clk_gate_i is high, in_data_ack_i shall be updated.
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
localparam IN_LENGTH = IN_MAXPACKETSIZE + 'd1; // the contents of the last addressed byte is meaningless
reg [ceil_log2(IN_LENGTH)-1:0] in_first_q, in_first_qq;
reg [ceil_log2(IN_LENGTH)-1:0] in_last_q, in_last_qq;
reg [8*IN_LENGTH-1:0] in_fifo_q;
assign in_data_o = in_fifo_q[{in_first_qq, 3'd0} +:8];
assign in_valid_o = (in_first_qq == in_last_qq) ? 1'b0 : 1'b1;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
in_first_q <= 'd0;
in_first_qq <= 'd0;
end else begin
if (clk_gate_i) begin
if (in_ready_i) begin
if (in_req_i) begin
in_first_qq <= in_first_q; // shall retry one more time if in_first_q wasn't updated
end else if (in_data_ack_i) begin
in_first_q <= in_first_qq;
end else begin
if (in_first_qq == IN_LENGTH-1)
in_first_qq <= 'd0;
else
in_first_qq <= in_first_qq + 1;
end
end
end
end
end
wire in_full, app_in_buffer_empty;
assign in_full = (in_first_q == ((in_last_q == IN_LENGTH-1) ? 'd0 : in_last_q+1) ? 1'b1 : 1'b0);
assign in_full_o = in_full;
assign in_empty_o = ((in_first_q == in_last_q && app_in_buffer_empty == 1'b1) ? 1'b1 : 1'b0);
generate
if (USE_APP_CLK == 0) begin : u_sync_data
reg [7:0] app_in_data_q;
reg app_in_valid_q, app_in_valid_qq;
reg app_in_ready_q;
assign app_in_ready_o = app_in_ready_q;
assign app_in_buffer_empty = ~app_in_valid_qq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
in_fifo_q <= {IN_LENGTH{8'd0}};
in_last_q <= 'd0;
in_last_qq <= 'd0;
app_in_data_q <= 8'd0;
app_in_valid_q <= 1'b0;
app_in_valid_qq <= 1'b0;
app_in_ready_q <= 1'b0;
end else begin
if (clk_gate_i) begin
in_fifo_q[{in_last_q, 3'd0} +:8] <= app_in_data_q;
app_in_valid_qq <= app_in_valid_q;
if (in_ready_i)
in_last_qq <= in_last_q;
if (~in_full & app_in_valid_qq) begin
app_in_valid_q <= 1'b0;
app_in_valid_qq <= 1'b0;
app_in_ready_q <= 1'b1;
if (in_last_q == IN_LENGTH-1) begin
in_last_q <= 'd0;
if (in_ready_i)
in_last_qq <= 'd0;
end else begin
in_last_q <= in_last_q + 1;
if (in_ready_i)
in_last_qq <= in_last_q + 1;
end
end
end
if (~app_in_valid_q)
app_in_ready_q <= 1'b1;
if (app_in_valid_i & app_in_ready_q) begin
app_in_data_q <= app_in_data_i;
app_in_valid_q <= 1'b1;
if (clk_gate_i)
app_in_valid_qq <= 1'b1;
app_in_ready_q <= 1'b0;
end
end
end
end else if (APP_CLK_FREQ <= 12) begin : u_lte12mhz_async_data
reg [2:0] app_clk_sq; // BIT_SAMPLES >= 4
reg [15:0] app_in_data_q;
reg [1:0] app_in_valid_q, app_in_valid_qq, app_in_valid_qqq;
reg app_in_first_q, app_in_first_qq, app_in_first_qqq;
reg [1:0] app_in_consumed_q, app_in_consumed_qq;
reg app_in_ready_q;
assign app_in_ready_o = app_in_ready_q;
assign app_in_buffer_empty = ~|app_in_valid_qqq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
in_fifo_q <= {IN_LENGTH{8'd0}};
in_last_q <= 'd0;
in_last_qq <= 'd0;
app_clk_sq <= 3'b000;
app_in_valid_qq <= 2'b00;
app_in_valid_qqq <= 2'b00;
app_in_first_qq <= 1'b0;
app_in_first_qqq <= 1'b0;
app_in_consumed_q <= 2'b00;
app_in_consumed_qq <= 2'b00;
app_in_ready_q <= 1'b0;
end else begin
app_clk_sq <= {app_clk_i, app_clk_sq[2:1]};
if (app_clk_sq[1:0] == 2'b10) begin
app_in_ready_q <= |(~(app_in_valid_q & ~app_in_consumed_q));
app_in_consumed_q <= 2'b00;
app_in_consumed_qq <= app_in_consumed_q;
app_in_valid_qq <= app_in_valid_q & ~app_in_consumed_q;
if (^app_in_consumed_q)
app_in_first_qq <= app_in_consumed_q[0];
else
app_in_first_qq <= app_in_first_q;
end
if (clk_gate_i) begin
if (app_in_first_qqq == 1'b0)
in_fifo_q[{in_last_q, 3'd0} +:8] <= app_in_data_q[7:0];
else
in_fifo_q[{in_last_q, 3'd0} +:8] <= app_in_data_q[15:8];
if (in_ready_i)
in_last_qq <= in_last_q;
app_in_valid_qqq <= app_in_valid_qq;
app_in_first_qqq <= app_in_first_qq;
if (app_clk_sq[1:0] == 2'b10) begin
app_in_valid_qqq <= app_in_valid_q & ~app_in_consumed_q;
if (^app_in_consumed_q)
app_in_first_qqq <= app_in_consumed_q[0];
else
app_in_first_qqq <= app_in_first_q;
end
if (~in_full & |app_in_valid_qqq) begin
if (app_in_first_qqq == 1'b0) begin
app_in_valid_qq[0] <= 1'b0;
app_in_valid_qqq[0] <= 1'b0;
app_in_first_qq <= 1'b1;
app_in_first_qqq <= 1'b1;
app_in_consumed_q[0] <= 1'b1;
end else begin
app_in_valid_qq[1] <= 1'b0;
app_in_valid_qqq[1] <= 1'b0;
app_in_first_qq <= 1'b0;
app_in_first_qqq <= 1'b0;
app_in_consumed_q[1] <= 1'b1;
end
if (in_last_q == IN_LENGTH-1) begin
in_last_q <= 'd0;
if (in_ready_i)
in_last_qq <= 'd0;
end else begin
in_last_q <= in_last_q + 1;
if (in_ready_i)
in_last_qq <= in_last_q + 1;
end
end
end
end
end
always @(posedge app_clk_i or negedge app_rstn_i) begin
if (~app_rstn_i) begin
app_in_data_q <= 16'd0;
app_in_valid_q <= 2'b00;
app_in_first_q <= 1'b0;
end else begin
app_in_valid_q <= app_in_valid_q & ~app_in_consumed_qq;
if (^app_in_consumed_qq)
app_in_first_q <= app_in_consumed_qq[0];
if (app_in_valid_i & app_in_ready_q) begin
if (~(app_in_valid_q[0] & ~app_in_consumed_qq[0])) begin
app_in_data_q[7:0] <= app_in_data_i;
app_in_valid_q[0] <= 1'b1;
app_in_first_q <= app_in_valid_q[1] & ~app_in_consumed_qq[1];
end else if (~(app_in_valid_q[1] & ~app_in_consumed_qq[1])) begin
app_in_data_q[15:8] <= app_in_data_i;
app_in_valid_q[1] <= 1'b1;
app_in_first_q <= ~(app_in_valid_q[0] & ~app_in_consumed_qq[0]);
end
end
end
end
end else begin : u_gt12mhz_async_data
reg [1:0] app_in_valid_sq;
reg [7:0] app_in_data_q;
reg app_in_valid_q, app_in_valid_qq;
reg app_in_ready_q;
assign app_in_buffer_empty = ~app_in_valid_qq;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
in_fifo_q <= {IN_LENGTH{8'd0}};
in_last_q <= 'd0;
app_in_valid_sq <= 2'd0;
app_in_valid_qq <= 1'b0;
app_in_ready_q <= 1'b0;
end else begin
app_in_valid_sq <= {app_in_valid_q, app_in_valid_sq[1]};
if (~app_in_valid_sq[0])
app_in_ready_q <= 1'b1;
if (clk_gate_i) begin
in_fifo_q[{in_last_q, 3'd0} +:8] <= app_in_data_q;
app_in_valid_qq <= app_in_valid_sq[0] & app_in_ready_q;
if (in_ready_i)
in_last_qq <= in_last_q;
if (~in_full & app_in_valid_qq) begin
app_in_valid_qq <= 1'b0;
app_in_ready_q <= 1'b0;
if (in_last_q == IN_LENGTH-1) begin
in_last_q <= 'd0;
if (in_ready_i)
in_last_qq <= 'd0;
end else begin
in_last_q <= in_last_q + 1;
if (in_ready_i)
in_last_qq <= in_last_q + 1;
end
end
end
end
end
reg [1:0] app_in_ready_sq;
assign app_in_ready_o = app_in_ready_sq[0] & ~app_in_valid_q;
always @(posedge app_clk_i or negedge app_rstn_i) begin
if (~app_rstn_i) begin
app_in_data_q <= 8'd0;
app_in_valid_q <= 1'b0;
app_in_ready_sq <= 2'b00;
end else begin
app_in_ready_sq <= {app_in_ready_q, app_in_ready_sq[1]};
if (~app_in_ready_sq[0])
app_in_valid_q <= 1'b0;
else if (app_in_valid_i & ~app_in_valid_q) begin
app_in_data_q <= app_in_data_i;
app_in_valid_q <= 1'b1;
end
end
end
end
endgenerate
endmodule |
module phy_tx
(
// ---- to USB bus physical transmitters ----------------------
output tx_en_o,
output dp_tx_o,
output dn_tx_o,
// dp_tx_o and dn_tx_o shall have a negligible timing mismatch
// (< clk_i period /2).
// ---- to/from SIE module ------------------------------------
output tx_ready_o,
// tx_ready_o shall be high only for one clk_gate_i multi-cycle period.
// When both tx_valid_i and tx_ready_o are high, the 8-bit tx_data_i shall be consumed.
// When clk_gate_i is high, tx_ready_o shall be updated.
input clk_i,
// clk_i clock shall have a frequency of 12MHz*BIT_SAMPLES.
input rstn_i,
// While rstn_i is low (active low), the module shall be reset.
input clk_gate_i,
// clk_gate_i shall be high for only one clk_i period within every BIT_SAMPLES clk_i periods.
// When clk_gate_i is high, the registers that are gated by it shall be updated.
input tx_valid_i,
// When tx_valid_i changes from low to high, PHY_TX shall start a
// new packet transmission as soon as possible (USB2.0 7.1.18.1).
// When the last packet byte is consumed, tx_valid_i shall return low.
// When clk_gate_i is high, tx_valid_i shall be updated.
input [7:0] tx_data_i
// While tx_valid_i is high, the tx_data_i shall be valid and both
// tx_valid_i and tx_data_i shall not change until consumed.
);
localparam [1:0] ST_IDLE = 2'd0,
ST_SYNC = 2'd1,
ST_DATA = 2'd2,
ST_EOP = 2'd3;
reg [1:0] tx_state_q, tx_state_d;
reg [2:0] bit_cnt_q, bit_cnt_d;
reg [7:0] data_q, data_d;
reg [2:0] stuffing_cnt_q, stuffing_cnt_d;
reg nrzi_q, nrzi_d;
reg tx_ready;
assign tx_en_o = (tx_state_q == ST_IDLE) ? 1'b0 : 1'b1;
assign dp_tx_o = (tx_state_q == ST_EOP && data_q[0] == 1'b0) ? 1'b0 : nrzi_q;
assign dn_tx_o = (tx_state_q == ST_EOP && data_q[0] == 1'b0) ? 1'b0 : ~nrzi_q;
assign tx_ready_o = tx_ready;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
tx_state_q <= ST_IDLE;
bit_cnt_q <= 3'd7;
data_q <= 8'b10000000;
stuffing_cnt_q <= 3'd0;
nrzi_q <= 1'b1;
end else begin
if (clk_gate_i) begin
tx_state_q <= tx_state_d;
bit_cnt_q <= bit_cnt_d;
data_q <= data_d;
stuffing_cnt_q <= stuffing_cnt_d;
nrzi_q <= nrzi_d;
end
end
end
always @(/*AS*/bit_cnt_q or data_q or nrzi_q or stuffing_cnt_q
or tx_data_i or tx_state_q or tx_valid_i) begin
tx_state_d = tx_state_q;
bit_cnt_d = bit_cnt_q;
data_d = data_q;
stuffing_cnt_d = stuffing_cnt_q;
nrzi_d = nrzi_q;
tx_ready = 1'b0;
if (stuffing_cnt_q == 3'd6) begin
stuffing_cnt_d = 3'd0;
nrzi_d = ~nrzi_q;
end else begin
bit_cnt_d = bit_cnt_q - 1;
data_d = (data_q >> 1);
if (data_q[0] == 1'b1) begin
stuffing_cnt_d = stuffing_cnt_q + 1;
end else begin
stuffing_cnt_d = 3'd0;
nrzi_d = ~nrzi_q;
end
case (tx_state_q)
ST_IDLE : begin
if (tx_valid_i == 1'b1) begin
tx_state_d = ST_SYNC;
end else begin
bit_cnt_d = 3'd7;
data_d = 8'b10000000;
nrzi_d = 1'b1;
end
stuffing_cnt_d = 3'd0;
end
ST_SYNC : begin
if (bit_cnt_q == 3'd0) begin
if (tx_valid_i == 1'b1) begin
tx_state_d = ST_DATA;
bit_cnt_d = 3'd7;
data_d = tx_data_i;
tx_ready = 1'b1;
end else begin
tx_state_d = ST_IDLE;
bit_cnt_d = 3'd7;
data_d = 8'b10000000;
stuffing_cnt_d = 3'd0;
nrzi_d = 1'b1;
end
end
end
ST_DATA : begin
if (bit_cnt_q == 3'd0) begin
if (tx_valid_i == 1'b1) begin
bit_cnt_d = 3'd7;
data_d = tx_data_i;
tx_ready = 1'b1;
end else begin
tx_state_d = ST_EOP;
bit_cnt_d = 3'd3;
data_d = 8'b11111001;
end
end
end
ST_EOP : begin
if (bit_cnt_q == 3'd0) begin
tx_state_d = ST_IDLE;
bit_cnt_d = 3'd7;
data_d = 8'b10000000;
end
stuffing_cnt_d = 3'd0;
nrzi_d = 1'b1;
end
default : begin
tx_state_d = ST_IDLE;
bit_cnt_d = 3'd7;
data_d = 8'b10000000;
stuffing_cnt_d = 3'd0;
nrzi_d = 1'b1;
end
endcase
end
end
endmodule |
module app
(
input clk_i,
input rstn_i,
// ---- to/from USB_CDC ------------------------------------------
output [7:0] in_data_o,
output in_valid_o,
// While in_valid_o is high, in_data_o shall be valid.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall
// be consumed.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
output out_ready_o
// When both out_valid_i and out_ready_o are high, the out_data_i shall
// be consumed.
);
function [31:0] crc32;
input [7:0] data;
input [31:0] crc;
localparam [31:0] POLY32 = 32'h04C11DB7;
reg [3:0] i;
begin
crc32 = crc;
for (i = 0; i <= 7; i = i + 1) begin
if ((data[i[2:0]] ^ crc32[31]) == 1'b1)
crc32 = {crc32[30:0], 1'b0} ^ POLY32;
else
crc32 = {crc32[30:0], 1'b0};
end
end
endfunction
function [7:0] rev8;
input [7:0] data;
reg [3:0] i;
begin
for (i = 0; i <= 7; i = i + 1) begin
rev8[i[2:0]] = data[7-i];
end
end
endfunction
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
localparam [31:0] RESI32 = 32'hC704DD7B; // = rev32(~32'h2144DF1C)
localparam [23:0] LFSR_POLY24 = 24'b111000010000000000000000;
reg [1:0] rstn_sq;
wire rstn;
assign rstn = rstn_sq[0];
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rstn_sq <= 2'd0;
end else begin
rstn_sq <= {1'b1, rstn_sq[1]};
end
end
localparam [3:0] RESET_STATE = 4'd0,
LOOPBACK_STATE = 4'd1,
CMD0_STATE = 4'd2,
CMD1_STATE = 4'd3,
CMD2_STATE = 4'd4,
CMD3_STATE = 4'd5,
IN_STATE = 4'd6,
OUT_STATE = 4'd7,
READ0_STATE = 4'd8,
READ1_STATE = 4'd9,
READ2_STATE = 4'd10,
READ3_STATE = 4'd11,
READ_ROM_STATE = 4'd12,
READ_RAM_STATE = 4'd13;
localparam [7:0] NO_CMD = 8'd0,
IN_CMD = 8'd1,
OUT_CMD = 8'd2,
ADDR_CMD = 8'd3,
WAIT_CMD = 8'd4,
LFSR_WRITE_CMD = 8'd5,
LFSR_READ_CMD = 8'd6,
ROM_READ_CMD = 8'd7,
RAM_READ_CMD = 8'd8;
localparam ROM_SIZE = 'd1024; // byte size
localparam RAM_SIZE = 'd1024; // byte size
reg [7:0] out_data_q;
reg out_valid_q;
reg [3:0] state_q, state_d;
reg [7:0] cmd_q, cmd_d;
reg [31:0] crc32_q, crc32_d;
reg [23:0] lfsr_q, lfsr_d;
reg [23:0] byte_cnt_q, byte_cnt_d;
reg [7:0] wait_q, wait_d;
reg [7:0] wait_cnt_q, wait_cnt_d;
reg mem_valid_q, mem_valid_d;
reg [23:0] mem_addr_q, mem_addr_d;
reg out_ready;
wire wait_end;
wire out_valid;
assign wait_end = ~|wait_cnt_q;
assign out_valid = out_valid_i & wait_end;
assign out_ready_o = (~out_valid_q | out_ready) & wait_end;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
out_data_q <= 8'd0;
out_valid_q <= 1'b0;
state_q <= RESET_STATE;
cmd_q <= NO_CMD;
crc32_q <= 32'd0;
lfsr_q <= 24'd0;
byte_cnt_q <= 24'd0;
wait_q <= 8'd0;
wait_cnt_q <= 8'd0;
mem_valid_q <= 1'b0;
mem_addr_q <= 'd0;
end else begin
if (out_valid & (~out_valid_q | out_ready)) begin
out_data_q <= out_data_i;
out_valid_q <= 1'b1;
end else if (out_ready)
out_valid_q <= 1'b0;
state_q <= state_d;
cmd_q <= cmd_d;
crc32_q <= crc32_d;
lfsr_q <= lfsr_d;
byte_cnt_q <= byte_cnt_d;
wait_q <= wait_d;
if (~wait_end)
wait_cnt_q <= wait_cnt_q - 1;
else
wait_cnt_q <= wait_cnt_d;
mem_valid_q <= mem_valid_d;
mem_addr_q <= mem_addr_d;
end
end
reg [7:0] in_data;
reg in_valid;
reg rom_clke;
reg ram_clke;
reg ram_we;
wire in_ready;
wire [7:0] rom_data;
wire [7:0] ram_rdata;
assign in_data_o = in_data;
assign in_valid_o = in_valid & wait_end;
assign in_ready = in_ready_i & wait_end;
always @(/*AS*/byte_cnt_q or cmd_q or crc32_q or in_ready or lfsr_q
or mem_addr_q or mem_valid_q or out_data_q or out_valid_q
or ram_rdata or rom_data or state_q or wait_q) begin
state_d = state_q;
cmd_d = cmd_q;
crc32_d = crc32_q;
lfsr_d = lfsr_q;
byte_cnt_d = byte_cnt_q;
wait_d = wait_q;
wait_cnt_d = 8'd0;
mem_valid_d = mem_valid_q;
mem_addr_d = mem_addr_q;
in_data = out_data_q;
in_valid = 1'b0;
out_ready = 1'b0;
rom_clke = 1'b0;
ram_clke = 1'b0;
ram_we = 1'b0;
case (state_q)
RESET_STATE: begin
if (out_valid_q == 1'b1)
state_d = LOOPBACK_STATE;
end
LOOPBACK_STATE: begin
if (out_valid_q == 1'b1) begin
if (out_data_q == 8'h00) begin
state_d = CMD0_STATE;
out_ready = 1'b1;
end else begin
in_valid = 1'b1;
out_ready = in_ready;
if (in_ready == 1'b1) begin
ram_clke = 1'b1;
ram_we = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
end
end
end
CMD0_STATE: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD1_STATE;
cmd_d = out_data_q;
end
mem_valid_d = 1'b0;
end
CMD1_STATE: begin
case (cmd_q)
IN_CMD, OUT_CMD, ROM_READ_CMD, RAM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
byte_cnt_d[7:0] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
mem_addr_d[7:0] = out_data_q;
end
end
WAIT_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
wait_d = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
lfsr_d[7:0] = out_data_q;
end
end
LFSR_READ_CMD: begin
state_d = READ0_STATE;
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
CMD2_STATE: begin
case (cmd_q)
IN_CMD, OUT_CMD, ROM_READ_CMD, RAM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
byte_cnt_d[15:8] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
mem_addr_d[15:8] = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
lfsr_d[15:8] = out_data_q;
end
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
CMD3_STATE: begin
case (cmd_q)
IN_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = IN_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
OUT_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = OUT_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
mem_addr_d[23:16] = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
lfsr_d[23:16] = out_data_q;
end
end
ROM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = READ_ROM_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
RAM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = READ_RAM_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
crc32_d = 32'hFFFFFFFF;
end
IN_STATE: begin
in_data = lfsr_q[7:0];
in_valid = 1'b1;
if (in_ready == 1'b1) begin
crc32_d = crc32(lfsr_q[7:0], crc32_q);
lfsr_d = {lfsr_q[22:0], ~^(lfsr_q & LFSR_POLY24)};
if (byte_cnt_q == 24'd0)
state_d = READ0_STATE;
else
byte_cnt_d = byte_cnt_q - 1;
wait_cnt_d = wait_q;
end
end
OUT_STATE: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
crc32_d = crc32(out_data_q, crc32_q);
if (byte_cnt_q == 24'd0)
state_d = READ0_STATE;
else
byte_cnt_d = byte_cnt_q - 1;
wait_cnt_d = wait_q;
end
end
READ0_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ1_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[7:0];
else
in_data = rev8(~crc32_q[31:24]);
end
READ1_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ2_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[15:8];
else
in_data = rev8(~crc32_q[23:16]);
end
READ2_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ3_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[23:16];
else
in_data = rev8(~crc32_q[15:8]);
end
READ3_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = LOOPBACK_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = 8'd0;
else
in_data = rev8(~crc32_q[7:0]);
end
READ_ROM_STATE: begin
if (mem_valid_q == 1'b0) begin
rom_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
in_data = rom_data;
in_valid = mem_valid_q;
if (in_ready == 1'b1 && mem_valid_q == 1'b1) begin
mem_valid_d = 1'b0;
if (byte_cnt_q == 24'd0) begin
state_d = LOOPBACK_STATE;
mem_addr_d = 'd0;
end else begin
byte_cnt_d = byte_cnt_q - 1;
rom_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
wait_cnt_d = wait_q;
end
end
READ_RAM_STATE: begin
if (mem_valid_q == 1'b0) begin
ram_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
in_data = ram_rdata;
in_valid = mem_valid_q;
if (in_ready == 1'b1 && mem_valid_q == 1'b1) begin
mem_valid_d = 1'b0;
if (byte_cnt_q == 24'd0) begin
state_d = LOOPBACK_STATE;
mem_addr_d = 'd0;
end else begin
byte_cnt_d = byte_cnt_q - 1;
ram_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
wait_cnt_d = wait_q;
end
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
rom #(.VECTOR_LENGTH(ROM_SIZE),
.WORD_WIDTH('d8),
.ADDR_WIDTH(ceil_log2(ROM_SIZE)))
u_rom (.data_o(rom_data),
.clk_i(clk_i),
.clke_i(rom_clke),
.addr_i(mem_addr_q[ceil_log2(ROM_SIZE)-1:0]));
ram #(.VECTOR_LENGTH(RAM_SIZE),
.WORD_WIDTH('d8),
.ADDR_WIDTH(ceil_log2(RAM_SIZE)))
u_ram (.rdata_o(ram_rdata),
.clk_i(clk_i),
.clke_i(ram_clke),
.we_i(ram_we),
.addr_i(mem_addr_q[ceil_log2(RAM_SIZE)-1:0]),
.mask_i(8'd0),
.wdata_i(out_data_q));
endmodule |
module app
(
input clk_i,
input rstn_i,
// ---- to/from USB_CDC ------------------------------------------
output [7:0] in_data_o,
output in_valid_o,
// While in_valid_o is high, in_data_o shall be valid.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall
// be consumed.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
output out_ready_o,
// When both out_valid_i and out_ready_o are high, the out_data_i shall
// be consumed.
// ---- to TOP --------------------------------------------------
output sleep_o
);
reg [1:0] rstn_sq;
wire rstn;
assign rstn = rstn_sq[0];
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rstn_sq <= 2'd0;
end else begin
rstn_sq <= {1'b1, rstn_sq[1]};
end
end
localparam [3:0] ST_RESET = 'd0,
ST_OUT_CKECK0 = 'd1,
ST_OUT_CKECK1 = 'd2,
ST_OUT_SLEEP = 'd3,
ST_OUT0 = 'd4,
ST_OUT1 = 'd5,
ST_EXE = 'd6,
ST_IN_CKECK0 = 'd7,
ST_IN_CKECK1 = 'd8,
ST_IN_SLEEP = 'd9,
ST_IN = 'd10;
reg [3:0] status_q, status_d;
reg fifo_irq_q, fifo_irq_d;
reg [7:0] data_q, data_d;
assign sleep_o = (status_q == ST_OUT_SLEEP || status_q == ST_IN_SLEEP) ? 1'b1 : 1'b0;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
status_q <= ST_RESET;
fifo_irq_q <= 1'b0;
data_q <= 'd0;
end else begin
status_q <= status_d;
fifo_irq_q <= fifo_irq_d;
data_q <= data_d;
end
end
reg [7:0] cpu_wrdata;
reg [1:0] cpu_addr;
reg cpu_rd, cpu_wr;
reg fifo_sel;
wire [7:0] fifo_rddata;
wire fifo_out_irq, fifo_in_irq;
always @(/*AS*/data_q or fifo_in_irq or fifo_irq_q or fifo_out_irq
or fifo_rddata or status_q) begin
status_d = status_q;
fifo_irq_d = fifo_irq_q | fifo_out_irq | fifo_in_irq;
data_d = data_q;
cpu_addr = 2'b00;
cpu_rd = 1'b0;
cpu_wr = 1'b0;
cpu_wrdata = 8'd0;
fifo_sel = 1'b0;
case (status_q)
ST_RESET : begin
status_d = ST_OUT_CKECK0;
end
ST_OUT_CKECK0 : begin
fifo_irq_d = 1'b0;
cpu_addr = 2'b10;
cpu_rd = 1'b1;
fifo_sel = 1'b1;
status_d = ST_OUT_CKECK1;
end
ST_OUT_CKECK1 : begin
if (fifo_rddata[0] == 1'b1)
status_d = ST_OUT0;
else
status_d = ST_OUT_SLEEP;
end
ST_OUT_SLEEP : begin
if (fifo_irq_q)
status_d = ST_OUT_CKECK0;
end
ST_OUT0 : begin
cpu_addr = 2'b11;
cpu_rd = 1'b1;
fifo_sel = 1'b1;
status_d = ST_OUT1;
end
ST_OUT1 : begin
data_d = fifo_rddata[7:0];
status_d = ST_EXE;
end
ST_EXE : begin
if ((data_q >= "a" && data_q <= "z") ||
(data_q >= "A" && data_q <= "Z"))
data_d = data_q ^ 8'h20;
else if (data_q >= "0" && data_q <= "8")
data_d = data_q + 1;
else if (data_q == "9")
data_d = "0";
status_d = ST_IN_CKECK0;
end
ST_IN_CKECK0 : begin
fifo_irq_d = 1'b0;
cpu_addr = 2'b01;
cpu_rd = 1'b1;
fifo_sel = 1'b1;
status_d = ST_IN_CKECK1;
end
ST_IN_CKECK1 : begin
if (fifo_rddata[0] == 1'b1)
status_d = ST_IN;
else
status_d = ST_IN_SLEEP;
end
ST_IN_SLEEP : begin
if (fifo_irq_q)
status_d = ST_IN_CKECK0;
end
ST_IN : begin
cpu_addr = 2'b01;
cpu_wr = 1'b1;
fifo_sel = 1'b1;
cpu_wrdata = data_q;
status_d = ST_OUT_CKECK0;
end
default : begin
status_d = ST_OUT_CKECK0;
end
endcase
end
fifo_if u_fifo_if (.clk_i(clk_i),
.rstn_i(rstn),
.sel_i(fifo_sel),
.read_i(cpu_rd),
.write_i(cpu_wr),
.addr_i(cpu_addr),
.data_i(cpu_wrdata),
.data_o(fifo_rddata),
.in_irq_o(fifo_in_irq),
.out_irq_o(fifo_out_irq),
.in_data_o(in_data_o),
.in_valid_o(in_valid_o),
.in_ready_i(in_ready_i),
.out_data_i(out_data_i),
.out_valid_i(out_valid_i),
.out_ready_o(out_ready_o));
endmodule |
module sync
(
input rstn_i,
input iclk_i,
input [7:0] idata_i,
input ivalid_i,
output iready_o,
input oclk_i,
output [7:0] odata_o,
output ovalid_o,
input oready_i
);
reg [1:0] iready_sq;
reg iready_mask_q;
reg [7:0] idata_q;
assign iready_o = iready_sq[0] & ~iready_mask_q;
always @(posedge iclk_i or negedge rstn_i) begin
if (~rstn_i) begin
iready_sq <= 2'b00;
iready_mask_q <= 1'b0;
idata_q <= 8'd0;
end else begin
iready_sq <= {~ovalid_mask_q, iready_sq[1]};
if (~iready_sq[0])
iready_mask_q <= 1'b0;
else if (ivalid_i & ~iready_mask_q) begin
idata_q <= idata_i;
iready_mask_q <= 1'b1;
end
end
end
reg [1:0] ovalid_sq;
reg ovalid_mask_q;
assign ovalid_o = ovalid_sq[0] & ~ovalid_mask_q;
assign odata_o = idata_q;
always @(posedge oclk_i or negedge rstn_i) begin
if (~rstn_i) begin
ovalid_sq <= 2'b00;
ovalid_mask_q <= 1'b0;
end else begin
ovalid_sq <= {iready_mask_q, ovalid_sq[1]};
if (~ovalid_sq[0])
ovalid_mask_q <= 1'b0;
else if (oready_i & ~ovalid_mask_q)
ovalid_mask_q <= 1'b1;
end
end
endmodule |
module prescaler
(
input clk_i,
input rstn_i,
output clk_div16_o,
output clk_div8_o,
output clk_div4_o,
output clk_div2_o
);
reg [3:0] prescaler_cnt;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
prescaler_cnt <= 'd0;
end else begin
prescaler_cnt <= prescaler_cnt + 1;
end
end
assign clk_div16_o = prescaler_cnt[3];
assign clk_div8_o = prescaler_cnt[2];
assign clk_div4_o = prescaler_cnt[1];
assign clk_div2_o = prescaler_cnt[0];
endmodule |
module fifo_if
(
input clk_i,
input rstn_i,
// ---- to/from uC -----------------------------------------------
input sel_i,
input read_i,
input write_i,
input [1:0] addr_i,
input [7:0] data_i,
output [7:0] data_o,
output in_irq_o,
output out_irq_o,
// ---- to/from USB_CDC ------------------------------------------
output [7:0] in_data_o,
output in_valid_o,
// While in_valid_o is high, in_data_o shall be valid and both
// in_valid_o and in_data_o shall not change until consumed.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall
// be consumed.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid.
output out_ready_o
// When both out_valid_i and out_ready_o are high, the out_data_i shall
// be consumed.
);
reg [7:0] in_buffer_q;
reg in_valid_q;
reg in_irq_q;
assign in_data_o = in_buffer_q;
assign in_valid_o = in_valid_q;
assign in_irq_o = in_irq_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
in_buffer_q <= 8'd0;
in_valid_q <= 1'b0;
in_irq_q <= 1'b0;
end else begin
in_irq_q <= 1'b0;
if (in_valid_q == 1'b1) begin
if (in_ready_i == 1'b1) begin
in_valid_q <= 1'b0;
in_irq_q <= 1'b1;
end
end else
if (write_i == 1'b1 && sel_i == 1'b1 && addr_i == 2'b01) begin
in_buffer_q <= data_i;
in_valid_q <= 1'b1;
end
end
end
reg [1:0] addr_q;
reg [7:0] out_buffer_q;
reg out_ready_q;
reg out_irq_q;
reg started_q;
assign out_ready_o = out_ready_q;
assign out_irq_o = out_irq_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
started_q <= 1'b0;
addr_q <= 2'd0;
out_buffer_q <= 8'd0;
out_ready_q <= 1'b0;
out_irq_q <= 1'b0;
end else begin
started_q <= 1'b1;
if (read_i == 1'b1 && sel_i == 1'b1)
addr_q <= addr_i;
out_irq_q <= 1'b0;
if ((read_i == 1'b1 && sel_i == 1'b1 && addr_i == 2'b11) || ~started_q)
out_ready_q <= 1'b1;
if (out_valid_i == 1'b1 && out_ready_q == 1'b1) begin
out_buffer_q <= out_data_i;
out_ready_q <= 1'b0;
out_irq_q <= 1'b1;
end
end
end
reg [7:0] rdata;
assign data_o = rdata;
always @(/*AS*/addr_q or in_valid_q or out_buffer_q or out_ready_q) begin
case (addr_q)
2'b01: begin
rdata = {7'b0, ~in_valid_q};
end
2'b10: begin
rdata = {7'b0, ~out_ready_q};
end
2'b11: begin
rdata = out_buffer_q;
end
default: begin
rdata = 8'b0;
end
endcase
end
endmodule |
module spi
#(parameter SCK_PERIOD_MULTIPLIER = 'd2)
(
input clk_i,
input rstn_i,
// While rstn_i is low (active low), the module shall be reset
// ---- to/from application module --------------
input en_i,
// When en_i changes from high to low, the current bitstream shall end at the
// end of current byte transmission.
input [7:0] wr_data_i,
// While wr_valid_i is high, the wr_data_i shall be valid.
input wr_valid_i,
// While en_i is high and when wr_valid_i changes from low to high, SPI shall start a
// new bitstream transmission as soon as possible.
output wr_ready_o,
// While en_i is high and when both wr_valid_i and wr_ready_o are high, the 8-bit
// wr_data_i shall be consumed.
output [7:0] rd_data_o,
// While en_i is high and when both rd_valid_o and rd_ready_i are high, rd_data_o
// shall be consumed by application module.
output rd_valid_o,
// When rd_data_o is valid, rd_valid_o shall be high only for one clk_i period.
input rd_ready_i,
// While both en_i and rd_ready_i are high, a read bitstream shall continue at
// the end of the current byte transmission.
// ---- to/from serial bus ----------------------
output sck_o,
// While en_i is high and both wr_valid_o and rd_ready_i are low, sck_o shall
// wait at the end of current byte transmission.
output csn_o,
// When both en_i and wr_valid_i are high, csn_o shall go low.
// When en_i changes from high to low, csn_o shall go high at the end of current
// byte transmission.
output mosi_o,
input miso_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
localparam CLK_STEPS = (SCK_PERIOD_MULTIPLIER+1)/2;
wire clk_gate;
generate
if (CLK_STEPS <= 1) begin : u_single_clk_period
assign clk_gate = 1'b1;
end else begin : u_multiple_clk_periods
reg [ceil_log2(CLK_STEPS)-1:0] clk_cnt_q;
assign clk_gate = ({1'b0, clk_cnt_q} == CLK_STEPS-1) ? 1'b1 : 1'b0;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
clk_cnt_q <= 'd0;
end else begin
if ({1'b0, clk_cnt_q} == CLK_STEPS-1)
clk_cnt_q <= 'd0;
else
clk_cnt_q <= clk_cnt_q + 1;
end
end
end
endgenerate
localparam [1:0] ST_RESET = 2'd0,
ST_IDLE = 2'd1,
ST_DATA_SHIFT = 2'd2,
ST_DATA_WAIT = 2'd3;
reg [1:0] state_q, state_d;
reg [2:0] bit_cnt_q, bit_cnt_d;
reg [7:0] wr_data_q, wr_data_d;
reg [7:0] rd_data_q, rd_data_d;
reg en_q, en_d;
reg sck_q, sck_d;
assign csn_o = (state_q != ST_DATA_SHIFT && state_q != ST_DATA_WAIT) ? 1'b1 : 1'b0;
assign sck_o = sck_q;
assign mosi_o = wr_data_q[7];
assign rd_data_o = rd_data_q;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
state_q <= ST_RESET;
bit_cnt_q <= 'd0;
wr_data_q <= 'd0;
rd_data_q <= 'd0;
en_q <= 1'b0;
sck_q <= 1'b0;
end else begin
en_q <= en_i & en_q;
if (clk_gate) begin
state_q <= state_d;
bit_cnt_q <= bit_cnt_d;
wr_data_q <= wr_data_d;
rd_data_q <= rd_data_d;
en_q <= en_d;
sck_q <= sck_d;
end
end
end
reg wr_ready;
reg rd_valid;
wire wr_valid;
wire rd_ready;
assign wr_ready_o = wr_ready & clk_gate;
assign rd_valid_o = rd_valid & clk_gate;
assign wr_valid = wr_valid_i & en_i;
assign rd_ready = rd_ready_i & en_i;
always @(/*AS*/bit_cnt_q or en_i or en_q or miso_i or rd_data_q
or rd_ready or sck_q or state_q or wr_data_i or wr_data_q
or wr_valid) begin
state_d = state_q;
bit_cnt_d = bit_cnt_q;
wr_data_d = wr_data_q;
rd_data_d = rd_data_q;
en_d = en_i & en_q;
sck_d = 1'b0;
wr_ready = 1'b0;
rd_valid = 1'b0;
case (state_q)
ST_RESET : begin
state_d = ST_IDLE;
end
ST_IDLE : begin
bit_cnt_d = 'd7;
wr_ready = 1'b1;
if (wr_valid) begin
en_d = 1'b1;
wr_data_d = wr_data_i;
state_d = ST_DATA_SHIFT;
end
end
ST_DATA_SHIFT : begin
sck_d = ~sck_q;
if (sck_q) begin
wr_data_d = {wr_data_q[6:0], 1'b0};
if (bit_cnt_q == 'd0) begin
bit_cnt_d = 'd7;
rd_valid = 1'b1;
if (en_q) begin
wr_ready = 1'b1;
if (wr_valid) begin
wr_data_d = wr_data_i;
end else
state_d = ST_DATA_WAIT;
end else
state_d = ST_DATA_WAIT;
end else begin
bit_cnt_d = bit_cnt_q - 1;
end
end else begin
rd_data_d = {rd_data_q[6:0], miso_i};
end
end
ST_DATA_WAIT : begin
bit_cnt_d = 'd7;
if (en_q) begin
wr_ready = 1'b1;
if (wr_valid) begin
wr_data_d = wr_data_i;
state_d = ST_DATA_SHIFT;
end else if (rd_ready) begin
sck_d = 1'b1;
rd_data_d = {rd_data_q[6:0], miso_i};
state_d = ST_DATA_SHIFT;
end
end else
state_d = ST_IDLE;
end
default : begin
bit_cnt_d = 'd7;
state_d = ST_IDLE;
end
endcase
end
endmodule |
module flash_spi
#(parameter SCK_PERIOD_MULTIPLIER = 'd2,
parameter CLK_PERIODS_PER_US = 'd10,
parameter FLASH_SIZE = 'd1048576,
parameter BLOCK_SIZE = 'd4096,
parameter PAGE_SIZE = 'd256,
parameter RESUME_US = 'd10,
parameter BLOCK_ERASE_US = 'd60000,
parameter PAGE_PROG_US = 'd700)
(
input clk_i,
input rstn_i,
// While rstn_i is low (active low), the module shall be reset
// ---- to/from application module --------------
input out_en_i,
// When out_en_i changes from low to high, a new program operation shall start.
// When out_en_i changes from high to low, the current program operation shall end.
input in_en_i,
// When in_en_i changes from low to high, a new read operation shall start.
// When in_en_i changes from high to low, the current read operation shall end.
input [ceil_log2(FLASH_SIZE)-ceil_log2(BLOCK_SIZE)-1:0] start_block_addr_i,
input [ceil_log2(FLASH_SIZE)-ceil_log2(BLOCK_SIZE)-1:0] end_block_addr_i,
input [ceil_log2(BLOCK_SIZE)-1:0] read_addr_offset_i,
input [7:0] out_data_i,
// While out_valid_i is high, the out_data_i shall be valid.
input out_valid_i,
// When both out_en_i and out_valid_i change from low to high, a new programming
// operation shall start.
output out_ready_o,
// While out_en_i is high and when both out_valid_i and out_ready_o are high, out_data_i
// shall be consumed.
output [7:0] in_data_o,
// While in_valid_o is high, the in_data_o shall be valid.
output in_valid_o,
// While in_en_i is high and when both in_valid_o and in_ready_i are high, in_data_o
// shall be consumed by application module.
// in_valid_o shall be high only for one clk_i period.
input in_ready_i,
// When both in_en_i and in_ready_i change from low to high, a new read
// operation shall start.
input clear_status_i,
// While status_o reports an error or the end of programming/read operation (4'bF),
// when clear_status_i is high, status_o shall be cleared to 4'h0.
output [3:0] status_o,
// status_o shall report an error (4'h5, 4'h7 or 4'h8) or the end of a correct
// programming/read operation (4'hF), otherwise shall be 4'h0.
output erase_busy_o,
output program_busy_o,
// ---- to/from serial bus ----------------------
output sck_o,
output csn_o,
output mosi_o,
input miso_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
function [15:0] crc16;
input [7:0] data;
input [15:0] crc;
localparam [15:0] POLY16 = 16'h8005;
reg [3:0] i;
begin
crc16 = crc;
for (i = 0; i <= 7; i = i + 1) begin
if ((data[i[2:0]] ^ crc16[15]) == 1'b1)
crc16 = {crc16[14:0], 1'b0} ^ POLY16;
else
crc16 = {crc16[14:0], 1'b0};
end
end
endfunction
localparam [31:0] RESUME_WAIT = `min(RESUME_US*CLK_PERIODS_PER_US+(SCK_PERIOD_MULTIPLIER+1)/2, {16'h00, 16'hFF}),
BLOCK_ERASE_WAIT = `min(BLOCK_ERASE_US*CLK_PERIODS_PER_US/10, {16'h00, 16'hFF}),
PAGE_PROG_WAIT = `min(PAGE_PROG_US*CLK_PERIODS_PER_US/10, {16'h00, 16'hFF});
localparam [3:0] STATUS_OK = 4'h0,
STATUS_errCHECK_ERASED = 4'h5,
STATUS_errVERIFY = 4'h7,
STATUS_errADDRESS = 4'h8,
STATUS_END = 4'hF;
localparam [7:0] FLASH_CMD_RESUME_DPD = 8'hAB,
FLASH_CMD_DATA_READ = 8'h0B,
FLASH_CMD_DPD = 8'hB9,
FLASH_CMD_WRITE_ENABLE = 8'h06,
FLASH_CMD_4KB_ERASE = 8'h20,
FLASH_CMD_SR1_READ = 8'h05,
FLASH_CMD_DATA_WRITE = 8'h02;
localparam [4:0] ST_IDLE = 'd0,
ST_RESUME_DPD = 'd1,
ST_RD_DATA_CMD = 'd2,
ST_RD_DATA = 'd3,
ST_WR_ERASE_ENABLE = 'd4,
ST_WR_ERASE = 'd5,
ST_WR_ERASE_STATUS = 'd6,
ST_WR_ERASE_RD_DATA_CMD = 'd7,
ST_WR_ERASE_RD_DATA = 'd8,
ST_WR_ERASE_END = 'd9,
ST_WR_ERASE_ERROR = 'd10,
ST_WR_DATA_ENABLE = 'd11,
ST_WR_DATA_CMD = 'd12,
ST_WR_DATA = 'd13,
ST_WR_EOP = 'd14,
ST_WR_DATA_STATUS = 'd15,
ST_WR_RD_DATA_CMD = 'd16,
ST_WR_RD_DATA = 'd17,
ST_WR_DATA_CHECK = 'd18,
ST_WR_DATA_ERROR = 'd19,
ST_WR_ADDR_ERROR = 'd20,
ST_DPD = 'd21,
ST_DPD_END = 'd22,
ST_END = 'd23;
localparam BYTE_CNT_WIDTH = ceil_log2(PAGE_SIZE);
localparam PAGE_ADDR_WIDTH = ceil_log2(FLASH_SIZE)-BYTE_CNT_WIDTH;
localparam PAGES_WIDTH = ceil_log2(BLOCK_SIZE)-BYTE_CNT_WIDTH;
reg [BYTE_CNT_WIDTH-1:0] byte_cnt_q, byte_cnt_d;
reg [BYTE_CNT_WIDTH-1:0] last_byte_q, last_byte_d;
reg [PAGE_ADDR_WIDTH-1:0] page_addr_q, page_addr_d;
reg [4:0] state_q, state_d;
reg [15:0] wait_cnt_q, wait_cnt_d;
reg [15:0] crc16_q, crc16_d;
reg out_en_q, out_en_d;
reg in_en_q, in_en_d;
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
state_q <= ST_IDLE;
byte_cnt_q <= 'd0;
page_addr_q <= 'd0;
wait_cnt_q <= 'd0;
crc16_q <= 16'd0;
last_byte_q <= 'd0;
out_en_q <= 1'b0;
in_en_q <= 1'b0;
end else begin
state_q <= state_d;
byte_cnt_q <= byte_cnt_d;
page_addr_q <= page_addr_d;
wait_cnt_q <= wait_cnt_d;
crc16_q <= crc16_d;
last_byte_q <= last_byte_d;
out_en_q <= out_en_d;
in_en_q <= in_en_d;
end
end
reg spi_en;
reg [7:0] spi_wr_data;
reg spi_wr_valid;
reg spi_rd_ready;
reg [7:0] in_data;
reg in_valid;
reg out_ready;
reg [23:0] cmd_addr;
reg [23:0] cmd_rdaddr;
wire spi_wr_ready;
wire [7:0] spi_rd_data;
wire spi_rd_valid;
wire out_valid;
wire in_ready;
assign in_data_o = in_data;
assign in_valid_o = in_valid;
assign out_ready_o = out_ready;
assign out_valid = out_valid_i & out_en_i;
assign in_ready = in_ready_i & in_en_i;
assign status_o = (state_q == ST_END) ? STATUS_END :
(state_q == ST_WR_ERASE_ERROR) ? STATUS_errCHECK_ERASED :
(state_q == ST_WR_DATA_ERROR) ? STATUS_errVERIFY :
(state_q == ST_WR_ADDR_ERROR) ? STATUS_errADDRESS :
STATUS_OK;
assign erase_busy_o = (state_q == ST_WR_ERASE_ENABLE || state_q == ST_WR_ERASE ||
state_q == ST_WR_ERASE_STATUS || state_q == ST_WR_ERASE_RD_DATA_CMD ||
state_q == ST_WR_ERASE_RD_DATA || state_q == ST_WR_ERASE_END) ?
1'b1 : 1'b0;
assign program_busy_o = (state_q == ST_WR_DATA_ENABLE || state_q == ST_WR_DATA_CMD ||
state_q == ST_WR_DATA || state_q == ST_WR_EOP ||
state_q == ST_WR_DATA_STATUS || state_q == ST_WR_RD_DATA_CMD ||
state_q == ST_WR_RD_DATA || state_q == ST_WR_DATA_CHECK) ?
1'b1 : 1'b0;
always @(/*AS*/byte_cnt_q or clear_status_i or crc16_q
or end_block_addr_i or in_en_i or in_en_q or in_ready
or last_byte_q or out_data_i or out_en_i or out_en_q
or out_valid or page_addr_q or read_addr_offset_i
or spi_rd_data or spi_rd_valid or spi_wr_ready
or start_block_addr_i or state_q or wait_cnt_q) begin
state_d = state_q;
byte_cnt_d = byte_cnt_q;
page_addr_d = page_addr_q;
wait_cnt_d = wait_cnt_q;
crc16_d = crc16_q;
last_byte_d = last_byte_q;
out_en_d = out_en_i & out_en_q;
in_en_d = in_en_i & in_en_q;
spi_en = 1'b0;
spi_wr_data = 'd0;
spi_wr_valid = 1'b0;
spi_rd_ready = 1'b0;
in_data = 'd0;
in_valid = 1'b0;
out_ready = 1'b0;
cmd_addr = 24'd0;
cmd_addr[PAGE_ADDR_WIDTH-1+BYTE_CNT_WIDTH:BYTE_CNT_WIDTH] = page_addr_q;
cmd_rdaddr = 24'd0;
cmd_rdaddr[PAGE_ADDR_WIDTH-1+BYTE_CNT_WIDTH:BYTE_CNT_WIDTH+PAGES_WIDTH] = page_addr_q[PAGE_ADDR_WIDTH-1: PAGES_WIDTH];
cmd_rdaddr[ceil_log2(BLOCK_SIZE)-1:0] = read_addr_offset_i;
case (state_q)
ST_IDLE : begin
if (out_en_i | in_en_i) begin
state_d = ST_RESUME_DPD;
if (in_en_i)
in_en_d = 1'b1;
else
out_en_d = 1'b1;
end
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
ST_RESUME_DPD : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_RESUME_DPD;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd1 : begin
if (spi_rd_valid == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd2 : begin // wait to resume from Deep Power Down
wait_cnt_d = wait_cnt_q + 1;
if (wait_cnt_q == RESUME_WAIT[15:0]) begin
byte_cnt_d = byte_cnt_q + 1;
wait_cnt_d = 'd0;
end
end
default : begin
if (~(out_en_q | in_en_q)) begin
state_d = ST_DPD;
byte_cnt_d = 'd0;
end else if (in_en_q & in_ready) begin
state_d = ST_RD_DATA_CMD;
byte_cnt_d = 'd0;
end else if (out_en_q & out_valid) begin
state_d = ST_WR_ERASE_ENABLE;
byte_cnt_d = 'd0;
end
page_addr_d[PAGE_ADDR_WIDTH-1:PAGES_WIDTH] = start_block_addr_i;
page_addr_d[PAGES_WIDTH-1:0] = {PAGES_WIDTH{1'b0}};
end
endcase
end
ST_RD_DATA_CMD : begin
spi_en = 1'b1;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
case (byte_cnt_q)
'd0 : begin
spi_wr_data = FLASH_CMD_DATA_READ;
end
'd1 : begin
spi_wr_data = cmd_rdaddr[23:16];
end
'd2 : begin
spi_wr_data = cmd_rdaddr[15:8];
end
'd3 : begin
spi_wr_data = cmd_rdaddr[7:0];
end
'd4 : begin
spi_wr_data = 'd0;
end
default : begin
page_addr_d[PAGES_WIDTH-1:0] = read_addr_offset_i[ceil_log2(BLOCK_SIZE)-1:BYTE_CNT_WIDTH];
if (spi_rd_valid == 1'b1) begin
state_d = ST_RD_DATA;
byte_cnt_d = read_addr_offset_i[BYTE_CNT_WIDTH-1:0];
end
end
endcase
end
ST_RD_DATA : begin
if (in_en_q) begin
spi_en = 1'b1;
in_data = spi_rd_data;
in_valid = spi_rd_valid;
spi_rd_ready = in_ready;
if (spi_rd_valid & in_ready) begin
byte_cnt_d = byte_cnt_q + 1;
if (&byte_cnt_q) begin
page_addr_d = page_addr_q + 1;
if (&page_addr_q[PAGES_WIDTH-1:0] &&
page_addr_q[PAGE_ADDR_WIDTH-1:PAGES_WIDTH] == end_block_addr_i)
in_en_d = 'b0;
end
end
end else begin
state_d = ST_DPD_END;
byte_cnt_d = 'd0;
end
end
ST_WR_ERASE_ENABLE : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_WRITE_ENABLE;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
default : begin
state_d = ST_WR_ERASE;
byte_cnt_d = 'd0;
end
endcase
end
ST_WR_ERASE : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_4KB_ERASE;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd1 : begin
spi_en = 1'b1;
spi_wr_data = cmd_addr[23:16];
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd2 : begin
spi_en = 1'b1;
spi_wr_data = cmd_addr[15:8];
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd3 : begin
spi_en = 1'b1;
spi_wr_data = cmd_addr[7:0];
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
default : begin
state_d = ST_WR_ERASE_STATUS;
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
endcase
end
ST_WR_ERASE_STATUS : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_SR1_READ;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd1 : begin
spi_en = 1'b1;
if (spi_rd_valid == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd2 : begin
spi_en = 1'b1;
spi_rd_ready = 1'b1;
if (spi_rd_valid == 1'b1) begin
if (spi_rd_data[0] == 1'b0) begin
byte_cnt_d = byte_cnt_q + 1;
end else begin
byte_cnt_d = 'd4;
end
end
end
'd3 : begin
state_d = ST_WR_ERASE_RD_DATA_CMD;
byte_cnt_d = 'd0;
end
default : begin // wait before next status check
wait_cnt_d = wait_cnt_q + 1;
if (wait_cnt_q == BLOCK_ERASE_WAIT[15:0]) begin
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
end
endcase
end
ST_WR_ERASE_RD_DATA_CMD : begin
spi_en = 1'b1;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
case (byte_cnt_q)
'd0 : begin
spi_wr_data = FLASH_CMD_DATA_READ;
end
'd1 : begin
spi_wr_data = cmd_addr[23:16];
end
'd2 : begin
spi_wr_data = cmd_addr[15:8];
end
'd3 : begin
spi_wr_data = cmd_addr[7:0];
end
'd4 : begin
spi_wr_data = 'd0;
end
default : begin
if (spi_rd_valid == 1'b1) begin
state_d = ST_WR_ERASE_RD_DATA;
page_addr_d[PAGES_WIDTH-1:0] = {PAGES_WIDTH{1'b0}};
byte_cnt_d = 'd0;
end
end
endcase
end
ST_WR_ERASE_RD_DATA : begin
spi_en = 1'b1;
spi_rd_ready = 1'b1;
if (spi_rd_valid) begin
if (&spi_rd_data) begin
byte_cnt_d = byte_cnt_q + 1;
if (&byte_cnt_q) begin
page_addr_d = page_addr_q + 1;
byte_cnt_d = 'd0;
if (&page_addr_q[PAGES_WIDTH-1:0]) begin
state_d = ST_WR_ERASE_END;
page_addr_d = {page_addr_q[PAGE_ADDR_WIDTH-1:PAGES_WIDTH], {PAGES_WIDTH{1'b0}}};
end
end
end else begin
state_d = ST_WR_ERASE_ERROR;
end
end
end
ST_WR_ERASE_END : begin
state_d = ST_WR_DATA_ENABLE;
end
ST_WR_ERASE_ERROR : begin
if (clear_status_i)
state_d = ST_IDLE;
end
ST_WR_DATA_ENABLE : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_WRITE_ENABLE;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
default : begin
state_d = ST_WR_DATA_CMD;
byte_cnt_d = 'd0;
end
endcase
end
ST_WR_DATA_CMD : begin
spi_en = 1'b1;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
case (byte_cnt_q)
'd0 : begin
spi_wr_data = FLASH_CMD_DATA_WRITE;
end
'd1 : begin
spi_wr_data = cmd_addr[23:16];
end
'd2 : begin
spi_wr_data = cmd_addr[15:8];
end
default : begin
spi_wr_data = cmd_addr[7:0];
crc16_d = 16'hFFFF;
if (spi_wr_ready == 1'b1) begin
state_d = ST_WR_DATA;
byte_cnt_d = 'd0;
end
end
endcase
end
ST_WR_DATA : begin
if (out_en_q) begin
spi_en = 1'b1;
spi_wr_data = out_data_i;
spi_wr_valid = out_valid;
out_ready = spi_wr_ready;
if (spi_wr_ready & out_valid) begin
crc16_d = crc16(out_data_i, crc16_q);
byte_cnt_d = byte_cnt_q + 1;
last_byte_d = byte_cnt_q;
if (&byte_cnt_q) begin
state_d = ST_WR_EOP; // End Of Page
end
end
end else begin
state_d = ST_WR_DATA_STATUS;
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
end
ST_WR_EOP : begin
state_d = ST_WR_DATA_STATUS;
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
ST_WR_DATA_STATUS : begin
case (byte_cnt_q)
'd0 : begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_SR1_READ;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd1 : begin
spi_en = 1'b1;
if (spi_rd_valid == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end
'd2 : begin
spi_en = 1'b1;
spi_rd_ready = 1'b1;
if (spi_rd_valid == 1'b1) begin
if (spi_rd_data[0] == 1'b0) begin
byte_cnt_d = byte_cnt_q + 1;
end else begin
byte_cnt_d = 'd4;
end
end
end
'd3 : begin
state_d = ST_WR_RD_DATA_CMD;
byte_cnt_d = 'd0;
end
default : begin // wait before next status check
wait_cnt_d = wait_cnt_q + 1;
if (wait_cnt_q == PAGE_PROG_WAIT[15:0]) begin
byte_cnt_d = 'd0;
wait_cnt_d = 'd0;
end
end
endcase
end
ST_WR_RD_DATA_CMD : begin
spi_en = 1'b1;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
case (byte_cnt_q)
'd0 : begin
spi_wr_data = FLASH_CMD_DATA_READ;
end
'd1 : begin
spi_wr_data = cmd_addr[23:16];
end
'd2 : begin
spi_wr_data = cmd_addr[15:8];
end
'd3 : begin
spi_wr_data = cmd_addr[7:0];
end
'd4 : begin
spi_wr_data = 'd0;
end
default : begin
if (spi_rd_valid == 1'b1) begin
wait_cnt_d = crc16_q;
crc16_d = 16'hFFFF;
state_d = ST_WR_RD_DATA;
byte_cnt_d = 'd0;
end
end
endcase
end
ST_WR_RD_DATA : begin
spi_en = 1'b1;
spi_rd_ready = 1'b1;
if (spi_rd_valid) begin
crc16_d = crc16(spi_rd_data, crc16_q);
byte_cnt_d = byte_cnt_q + 1;
if (byte_cnt_q == last_byte_q) begin
state_d = ST_WR_DATA_CHECK;
byte_cnt_d = 'd0;
end
end
end
ST_WR_DATA_CHECK : begin
if (crc16_q == wait_cnt_q) begin
byte_cnt_d = 'd0;
if (out_en_q) begin
page_addr_d = page_addr_q + 1;
if (&page_addr_q[PAGES_WIDTH-1:0]) begin
if (page_addr_q[PAGE_ADDR_WIDTH-1:PAGES_WIDTH] == end_block_addr_i) begin
if (out_valid)
state_d = ST_WR_ADDR_ERROR;
else
page_addr_d = page_addr_q;
end else
state_d = ST_WR_ERASE_ENABLE;
end else
state_d = ST_WR_DATA_ENABLE;
end else
state_d = ST_DPD_END;
end else begin
state_d = ST_WR_DATA_ERROR;
end
end
ST_WR_DATA_ERROR : begin
if (clear_status_i)
state_d = ST_IDLE;
end
ST_WR_ADDR_ERROR : begin
if (clear_status_i)
state_d = ST_IDLE;
end
ST_DPD, ST_DPD_END : begin
if (byte_cnt_q == 'd0) begin
spi_en = 1'b1;
spi_wr_data = FLASH_CMD_DPD;
spi_wr_valid = 1'b1;
if (spi_wr_ready == 1'b1)
byte_cnt_d = byte_cnt_q + 1;
end else begin
if (state_q == ST_DPD_END)
state_d = ST_END;
else
state_d = ST_IDLE;
byte_cnt_d = 'd0;
end
end
ST_END : begin
if (clear_status_i)
state_d = ST_IDLE;
end
default : begin
state_d = ST_IDLE;
byte_cnt_d = 'd0;
end
endcase
end
spi #(.SCK_PERIOD_MULTIPLIER(SCK_PERIOD_MULTIPLIER))
u_spi (.clk_i(clk_i),
.rstn_i(rstn_i),
.en_i(spi_en),
.wr_data_i(spi_wr_data),
.wr_valid_i(spi_wr_valid),
.wr_ready_o(spi_wr_ready),
.rd_data_o(spi_rd_data),
.rd_valid_o(spi_rd_valid),
.rd_ready_i(spi_rd_ready),
.sck_o(sck_o),
.csn_o(csn_o),
.mosi_o(mosi_o),
.miso_i(miso_i));
endmodule |
module ram
#(parameter VECTOR_LENGTH = 'd512,
parameter WORD_WIDTH = 'd16,
parameter ADDR_WIDTH = ceil_log2(VECTOR_LENGTH))
(
output [WORD_WIDTH-1:0] rdata_o,
input clk_i,
input clke_i,
input we_i,
input [ADDR_WIDTH-1:0] addr_i,
input [WORD_WIDTH-1:0] mask_i,
input [WORD_WIDTH-1:0] wdata_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
wire [7:0] addr;
wire [31:0] rdata32;
wire [31:0] wdata32;
wire [31:0] mask32;
generate
if (WORD_WIDTH == 'd8) begin : u_8bit
reg byte_addr_q;
assign rdata_o = byte_addr_q ? rdata32[15:8] : rdata32[7:0];
assign addr = addr_i[`min(8,ADDR_WIDTH-1):1];
assign wdata32 = {16'h0000, wdata_i, wdata_i};
assign mask32 = (addr_i[0] == 1'b0) ? {16'hFFFF, 8'hFF, mask_i} : {16'hFFFF, mask_i, 8'hFF};
always @(posedge clk_i) begin
if (clke_i ==1'b1 && we_i == 1'b0)
byte_addr_q <= addr_i[0];
end
end else if (WORD_WIDTH == 'd16) begin : u_16bit
assign rdata_o = rdata32[15:0];
assign addr = addr_i[`min(7,ADDR_WIDTH-1):0];
assign wdata32 = {16'h0000, wdata_i};
assign mask32 = {16'hFFFF, mask_i};
end else begin : u_32bit
assign rdata_o = rdata32;
assign addr = addr_i[`min(7,ADDR_WIDTH-1):0];
assign wdata32 = wdata_i;
assign mask32 = mask_i;
end
endgenerate
localparam RAM_WORDS = (WORD_WIDTH == 'd32) ? 2 : 1;
localparam RAM_BLOCKS = (((WORD_WIDTH == 'd8) ? (VECTOR_LENGTH+1)/2 : VECTOR_LENGTH)+255)/256;
wire [16*RAM_BLOCKS*RAM_WORDS-1:0] rdata;
wire [`max(ceil_log2(RAM_BLOCKS)-1, 0):0] block_addr;
generate
if (RAM_BLOCKS > 1) begin : u_multi_bank
reg [ceil_log2(RAM_BLOCKS)-1:0] block_addr_q;
assign block_addr = addr_i[ADDR_WIDTH-1 -:ceil_log2(RAM_BLOCKS)];
assign rdata32[15:0] = rdata[16*RAM_WORDS*block_addr_q +:16];
if (RAM_WORDS > 1) begin : u_high_word
assign rdata32[31:16] = rdata[16*(RAM_WORDS*block_addr_q+1) +:16];
end
always @(posedge clk_i) begin
if (clke_i == 1'b1 && we_i == 1'b0)
block_addr_q <= block_addr;
end
end else begin : u_single_bank
assign block_addr = 0;
assign rdata32[15:0] = rdata[15:0];
if (RAM_WORDS > 1) begin : u_high_word
assign rdata32[31:16] = rdata[31:16];
end
end
endgenerate
localparam [256*16*2-1:0] RAM_DATA = {256'hC1D4816ED2646D089AE661690164DABE1B873D7F8EC3AF7D8C7DA5C43F9743CD,
256'hC2FA7C36540E7700BDAC2AFFF42F77777F077A45A204B6274AE8965088EAA7DE,
256'h83863B4C3D0D002FEDA8C8806A7BC889D79C5AAE9736B416E9D6DA525773D584,
256'h4A0B90E9CDA6050D51719A2267926CBA03855F698F55CA97178015499BF1B937,
256'h96CE2E60E1513C6FF180F8F9311D6130777B3F337A0AEC075E278893A872436F,
256'hB0F7D959D47313F7C2130EDC97E63C4FCAE3CAA66C823BC63EA4F7684CF29649,
256'hDA32ACFEF1B1AF8C261DA967BB797182429BF220CF49C388C903BA1A36D3C986,
256'h3B5D98A13C514ECD18A7BA4FB34891B3309FBACE1907F5A134247D57D90A325B,
256'h3CF03A082F42F0B4D4F6BF9D0A2D6EB16E2BA8BC4E943C31C31D73120C1975D9,
256'hB32852C021BCD1A3DD59887C4C6E49435C5C08180B267667F7FBD044DE82BF74,
256'h78839C7F82B455D8FF1BCC32EE5FE613E221369A55CEE4B9391E1F5B7805FBF8,
256'h61103711B59FACD8277E00A69ADD8A95C9A1F57D36A338268429586157D6D3FC,
256'hF3D27A5C509539F960CA39F2071F7DB19227CAB90A66D0EC4A5A9BFE1B1C3D62,
256'h3627910C12045120AAEBEB2614142A709F85B4510BAE7A7DA7A9A098E1D74564,
256'hAC0890217D4DE966E44E68D1B36111C8D35D87573182754ABF29B7BFFBB8555D,
256'h4964D879A2D4826B1F68D49D1EF07EDF7DE586970A1304E902EF7754D722C8FF,
256'hABAC0E61FE578C814D146F0F2707AFE0EE2A22EB0FE41881DD80BE2727E1C9F6,
256'h5A5E34C6B6454ACA633B8730DACB19A3DD74E8B93672CC2E17BBBBC583EB66B8,
256'h08C7DEA00021F84186CA1F14329D83CFAF6ABE1015AAD6BE901C534EDAD49EB4,
256'hE2C09734B901B715DF59B2AC37504F9113FE7166FE00223DD3579BD73AB3817C,
256'hA6B0E6F8E6375000F84D79DB4613BD1A48872F850CF87FAAC7DD664922ACEE8A,
256'h4A74546376D57AD2DAD89AD100073076BED6D224292456E276EE3D95FA052B51,
256'hCB34EC22270804CEEAE6F1B8667B847651945A69658E758377A37BFF854D7C3F,
256'h2F6FA55973278DC04BF19C26A2DFE912617FEACC8CE3F098099CAF98980E696C,
256'h7BD8B21B22E37D4A15AAA76D6541C7932ADDD3ADD2A1E0C609FD8B57EE729721,
256'h60EFC3C3C433737B47CDDF1E4BA9849FF6601365A7E6E7752A7CEF56333792EB,
256'h613698187C59A3765CC248F5B5DF943B20097B779708D12A7E6723AAE792DE14,
256'h0B0C6F3F9D4A10A8E6FB097C658C11F68C4C26B1E05F534AA418BED25324A246,
256'h1ED9655323CE82A8E31812001FFE6AA0E8BB562B81B4E5CCB7EAFF0817ADB955,
256'h4D43BF34C0A091F49F6410926E5CA9FF116D5AE344DC0362B23E788FE20D8D06,
256'hDB06F2655983015722DF8BBC539FBD0430A921207E035D10CDD029D72DD727F7,
256'h440A49737ED1A47239E2824653E8CEF7544C19B1B04F0B19AABAA3B447985F96};
genvar i,j;
generate
for (i = 0; i < RAM_BLOCKS; i = i+1) begin : u_ram_blocks
wire re, we;
assign re = (i == block_addr && we_i == 1'b0) ? 1'b1 : 1'b0;
assign we = (i == block_addr && we_i == 1'b1) ? 1'b1 : 1'b0;
for (j = 0; j < RAM_WORDS; j = j+1) begin : u_ram_words
SB_RAM256x16 #(.INIT_0(RAM_DATA[256*((RAM_WORDS*(0+16*i)+j)%(2*16)) +:256]),
.INIT_1(RAM_DATA[256*((RAM_WORDS*(1+16*i)+j)%(2*16)) +:256]),
.INIT_2(RAM_DATA[256*((RAM_WORDS*(2+16*i)+j)%(2*16)) +:256]),
.INIT_3(RAM_DATA[256*((RAM_WORDS*(3+16*i)+j)%(2*16)) +:256]),
.INIT_4(RAM_DATA[256*((RAM_WORDS*(4+16*i)+j)%(2*16)) +:256]),
.INIT_5(RAM_DATA[256*((RAM_WORDS*(5+16*i)+j)%(2*16)) +:256]),
.INIT_6(RAM_DATA[256*((RAM_WORDS*(6+16*i)+j)%(2*16)) +:256]),
.INIT_7(RAM_DATA[256*((RAM_WORDS*(7+16*i)+j)%(2*16)) +:256]),
.INIT_8(RAM_DATA[256*((RAM_WORDS*(8+16*i)+j)%(2*16)) +:256]),
.INIT_9(RAM_DATA[256*((RAM_WORDS*(9+16*i)+j)%(2*16)) +:256]),
.INIT_A(RAM_DATA[256*((RAM_WORDS*(10+16*i)+j)%(2*16)) +:256]),
.INIT_B(RAM_DATA[256*((RAM_WORDS*(11+16*i)+j)%(2*16)) +:256]),
.INIT_C(RAM_DATA[256*((RAM_WORDS*(12+16*i)+j)%(2*16)) +:256]),
.INIT_D(RAM_DATA[256*((RAM_WORDS*(13+16*i)+j)%(2*16)) +:256]),
.INIT_E(RAM_DATA[256*((RAM_WORDS*(14+16*i)+j)%(2*16)) +:256]),
.INIT_F(RAM_DATA[256*((RAM_WORDS*(15+16*i)+j)%(2*16)) +:256]))
u_ram256x16 (.RDATA(rdata[16*(RAM_WORDS*i+j) +:16]),
.RADDR(addr),
.RCLK(clk_i),
.RCLKE(clke_i),
.RE(re),
.WADDR(addr),
.WCLK(clk_i),
.WCLKE(clke_i),
.WDATA(wdata32[16*j +:16]),
.WE(we),
.MASK(mask32[16*j +:16]));
end
end
endgenerate
endmodule |
module rom
#(parameter VECTOR_LENGTH = 'd512,
parameter WORD_WIDTH = 'd16, // 8, 16 or 32
parameter ADDR_WIDTH = ceil_log2(VECTOR_LENGTH))
(
output [WORD_WIDTH-1:0] data_o,
input clk_i,
input clke_i,
input [ADDR_WIDTH-1:0] addr_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
wire [31:0] rdata32;
wire [7:0] addr;
generate
if (WORD_WIDTH == 'd8) begin : u_8bit
reg byte_addr_q;
assign data_o = byte_addr_q ? rdata32[15:8] : rdata32[7:0];
assign addr = addr_i[`min(8,ADDR_WIDTH-1):1];
always @(posedge clk_i) begin
if (clke_i)
byte_addr_q <= addr_i[0];
end
end else if (WORD_WIDTH == 'd16) begin : u_16bit
assign data_o = rdata32[15:0];
assign addr = addr_i[`min(7,ADDR_WIDTH-1):0];
end else begin : u_32bit
assign data_o = rdata32;
assign addr = addr_i[`min(7,ADDR_WIDTH-1):0];
end
endgenerate
localparam ROM_WORDS = (WORD_WIDTH == 'd32) ? 2 : 1;
localparam ROM_BLOCKS = (((WORD_WIDTH == 'd8) ? (VECTOR_LENGTH+1)/2 : VECTOR_LENGTH)+255)/256;
wire [16*ROM_BLOCKS*ROM_WORDS-1:0] rdata;
wire [`max(ceil_log2(ROM_BLOCKS)-1, 0):0] block_addr;
generate
if (ROM_BLOCKS > 1) begin : u_multi_bank
reg [ceil_log2(ROM_BLOCKS)-1:0] block_addr_q;
assign block_addr = addr_i[ADDR_WIDTH-1 -:ceil_log2(ROM_BLOCKS)];
assign rdata32[15:0] = rdata[16*ROM_WORDS*block_addr_q +:16];
if (ROM_WORDS > 1) begin : u_high_word
assign rdata32[31:16] = rdata[16*(ROM_WORDS*block_addr_q+1) +:16];
end
always @(posedge clk_i) begin
if (clke_i)
block_addr_q <= block_addr;
end
end else begin : u_single_bank
assign block_addr = 0;
assign rdata32[15:0] = rdata[15:0];
if (ROM_WORDS > 1) begin : u_high_word
assign rdata32[31:16] = rdata[31:16];
end
end
endgenerate
localparam [256*16*2-1:0] ROM_DATA = {256'h6D331DDB26D153A5B677F5093BBB2DDF689DAC0074F3292285BEA438F37C2984,
256'h5537818752892D52892CC66E0799AFD3439EB6F21668948E6E7D38998BFDB692,
256'h012235F6270610D0670129736137B590494FFF2A11C294B22415529CB4E76DC1,
256'h1991AAE9DB1381A74C2505F0160D0426A7E0E3A1A18F18F73AE7E63FCB45E36D,
256'h8D508E74DF4C083652BF4BA8C8A9A103A9807CB69AAF546E3744DF9BB3DA4499,
256'hCCD2F056C832A3122E81F9D3EF6F6BC79B1E442FFF413C2A2468DEF0BFF3954B,
256'hF62F9CA07F8607AA3C9BD09B2F7ED8B0F084AC6E0873A14E36BD492B29EA1617,
256'h70BD1BE5E40980220D504634930E82ACE905A24DE8030FADF6AE572B69E7A6B0,
256'h2EB97F3B3CEC95526D43F131750ECCA56A389B00BEAA3E64B0525F450ACB164D,
256'h347C301CDB370650D88A2AEC52C14C9D9A0CE27FB988AD066D6DF60FDF3F7FB4,
256'h43C7E94CD1B7C9FECBA311F3A06C10D84CD13ADF67337DCDA8D0DE715987F3B3,
256'hDFDF779E14A1000A6E4DC1431CDDD932CF3D99E642AE2EF5CAE093C9F73D61AB,
256'h04091CA820D4B1774E22802335C2D1AAA44426CD5C2CF6D52FCF8DCE8B469C66,
256'hA03E404CC381CDA9DCC1A70BA0F3F067E22F65D4E456C6DC9E08E532D4CD7A7D,
256'hBC44068112661B60E9CA7768AD20D81FF9C769A60EEF63039E091DCAE008B745,
256'h28A87B0CF7112A239C329C5D04C6DC84C42ADB328B66203DB44B1324CE8C003A,
256'hD7A5C3CD0203DD451D4E48774153A7FAC62AAB526D6637A3A4E91D4211D72405,
256'hC91DC8CC90377F1EA3BD9DFD5B76EC44E3BE7C42DD912E60D7713513AD8904CB,
256'h0E7E3FD65E9FE9D4E09E2DF878ABCDD7958610730BD3C52DCEB19CCB365A1E7B,
256'h5C05AA6573A66EC30543476D4ED7AF7458CF1436A8FACD38D940D72460683ED3,
256'h82973E47B9E62E45A6D5A6EF61DDFD205D0B932CBEB0E4D75B9B5232355E5E79,
256'h555DC8BC5B111C1E6CA30C14C14E17FE3DB60C663AD22D7AD465955F2F541260,
256'h83007D7E943D305F62F1B974EE8545175DC423C95AE9A8D794568AF6B9809E4E,
256'hF594CE66FB6668C44BE805CC4CE3E24C0653429E0F4B4B283328034E2132BE6C,
256'h4CAE3CA135E4A1687C6867CF412EB915158990B50EA16A84B8D1698D763001BD,
256'hD3493CF28ADE5F98B7F21218171FF47E634EA49C4E491E7CFD67A5DC8FB2A378,
256'hCF1CE078B591D073D6A82ACE248A7F25BF035D2F71B5EB659A4F407E2D88E9CC,
256'h0CD51007D1C56720D8B4F5D58B6EFED77B9947109D85A7603021AC6633F83953,
256'h8B552F6D6227BF85C9E5031FE0139BD1F3B6EE57F9DF9B0FE61A10F529F9636C,
256'hE4D333CD6DE06FBAF6E0847725216D416357B51B9A09B47BB1B3817667708D93,
256'hD07F8C6DBD91B75A8C81BD4B1009248657FEA9EA0C88EA3AB5F7F9318920C642,
256'h6CA93E9696812BC756AA23ABA720A1B0F76A1F284C757BF364505334F670FF6B};
genvar i,j;
generate
for (i = 0; i < ROM_BLOCKS; i = i+1) begin : u_rom_blocks
wire re;
assign re = (i == block_addr) ? 1'b1 : 1'b0;
for (j = 0; j < ROM_WORDS; j = j+1) begin : u_rom_words
SB_RAM256x16 #(.INIT_0(ROM_DATA[256*((ROM_WORDS*(0+16*i)+j)%(2*16)) +:256]),
.INIT_1(ROM_DATA[256*((ROM_WORDS*(1+16*i)+j)%(2*16)) +:256]),
.INIT_2(ROM_DATA[256*((ROM_WORDS*(2+16*i)+j)%(2*16)) +:256]),
.INIT_3(ROM_DATA[256*((ROM_WORDS*(3+16*i)+j)%(2*16)) +:256]),
.INIT_4(ROM_DATA[256*((ROM_WORDS*(4+16*i)+j)%(2*16)) +:256]),
.INIT_5(ROM_DATA[256*((ROM_WORDS*(5+16*i)+j)%(2*16)) +:256]),
.INIT_6(ROM_DATA[256*((ROM_WORDS*(6+16*i)+j)%(2*16)) +:256]),
.INIT_7(ROM_DATA[256*((ROM_WORDS*(7+16*i)+j)%(2*16)) +:256]),
.INIT_8(ROM_DATA[256*((ROM_WORDS*(8+16*i)+j)%(2*16)) +:256]),
.INIT_9(ROM_DATA[256*((ROM_WORDS*(9+16*i)+j)%(2*16)) +:256]),
.INIT_A(ROM_DATA[256*((ROM_WORDS*(10+16*i)+j)%(2*16)) +:256]),
.INIT_B(ROM_DATA[256*((ROM_WORDS*(11+16*i)+j)%(2*16)) +:256]),
.INIT_C(ROM_DATA[256*((ROM_WORDS*(12+16*i)+j)%(2*16)) +:256]),
.INIT_D(ROM_DATA[256*((ROM_WORDS*(13+16*i)+j)%(2*16)) +:256]),
.INIT_E(ROM_DATA[256*((ROM_WORDS*(14+16*i)+j)%(2*16)) +:256]),
.INIT_F(ROM_DATA[256*((ROM_WORDS*(15+16*i)+j)%(2*16)) +:256]))
u_ram256x16 (.RDATA(rdata[16*(ROM_WORDS*i+j) +:16]),
.RADDR(addr),
.RCLK(clk_i),
.RCLKE(clke_i),
.RE(re),
.WADDR(8'd0),
.WCLK(1'b0),
.WCLKE(1'b0),
.WDATA(16'b0),
.WE(1'b0),
.MASK(16'b0));
end
end
endgenerate
endmodule |
module SB_PLL40_CORE (
input REFERENCECLK,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
output SDO,
input SDI,
input SCLK
);
parameter FEEDBACK_PATH = "SIMPLE";
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
parameter SHIFTREG_DIV_MODE = 1'b0;
parameter FDA_FEEDBACK = 4'b0000;
parameter FDA_RELATIVE = 4'b0000;
parameter PLLOUT_SELECT = "GENCLK";
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0000000;
parameter DIVQ = 3'b000;
parameter FILTER_RANGE = 3'b000;
parameter ENABLE_ICEGATE = 1'b0;
parameter TEST_MODE = 1'b0;
parameter EXTERNAL_DIVIDE_FACTOR = 1;
localparam CLK_RATIO = (DIVF+1)/(2**DIVQ*(DIVR+1));
time ref_per;
time clk_per;
time last_ref_rising;
integer timeout;
reg clk;
reg lock_reg;
assign #(clk_per/4) PLLOUTGLOBAL = clk; // glitch filter
assign #(clk_per+ref_per) LOCK = lock_reg; // glitch filter
initial begin
ref_per = 0;
clk_per = 10;
last_ref_rising = $time;
clk = 0;
lock_reg = 1;
timeout = 4*CLK_RATIO;
#1 lock_reg = 0; // negedge to trigger reset
#100;
ref_per = 0;
clk_per = 100000000;
end
always @(posedge REFERENCECLK) begin
if (`abs($time - last_ref_rising - ref_per)*100/ref_per < 1)
lock_reg = 1;
else
lock_reg = 0;
ref_per = $time - last_ref_rising;
last_ref_rising = $time;
if (clk_per != 2**DIVQ * (DIVR + 1) * ref_per / (DIVF + 1)) begin
clk_per = 2**DIVQ * (DIVR + 1) * ref_per / (DIVF + 1);
clk <= ~clk;
end
timeout = 4*CLK_RATIO;
end
always @(clk)
if (timeout > 0) begin
clk <= #(clk_per/2) ~clk;
if (clk)
timeout = timeout - 1;
end else
lock_reg = 0;
endmodule |
module SB_RAM256x16
#(parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000)
(
output [15:0] RDATA,
input RCLK,
input RCLKE,
input RE,
input [7:0] RADDR,
input WCLK,
input WCLKE,
input WE,
input [7:0] WADDR,
input [15:0] MASK,
input [15:0] WDATA
);
SB_RAM40_4K #(.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F))
u_ram40_4k (.RDATA(RDATA),
.RADDR({3'b0, RADDR}),
.RCLK(RCLK),
.RCLKE(RCLKE),
.RE(RE),
.WADDR({3'b0, WADDR}),
.WCLK(WCLK),
.WCLKE(WCLKE),
.WDATA(WDATA),
.WE(WE),
.MASK(MASK));
endmodule |
module app
(
input clk_i,
input rstn_i,
// ---- to/from USB_CDC ------------------------------------------
output [7:0] in_data_o,
output in_valid_o,
// While in_valid_o is high, in_data_o shall be valid.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall
// be consumed.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
output out_ready_o,
// When both out_valid_i and out_ready_o are high, the out_data_i shall
// be consumed.
input heartbeat_i,
output boot_o,
output sck_o,
output csn_o,
output mosi_o,
input miso_i
);
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
reg [1:0] rstn_sq;
wire rstn;
assign rstn = rstn_sq[0];
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rstn_sq <= 2'd0;
end else begin
rstn_sq <= {1'b1, rstn_sq[1]};
end
end
localparam [2:0] ST_IDLE = 3'd0,
ST_WR_LO_LENGTH = 3'd1,
ST_WR_HI_LENGTH = 3'd2,
ST_RD_LO_LENGTH = 3'd3,
ST_RD_HI_LENGTH = 3'd4,
ST_WR_DATA = 3'd5,
ST_RD_DATA = 3'd6,
ST_BOOT = 3'd7;
localparam TIMER_MSB = ceil_log2(2*16000000); // 2 sec
reg [2:0] state_q, state_d;
reg [15:0] wr_length_q, wr_length_d;
reg [15:0] rd_length_q, rd_length_d;
reg [TIMER_MSB:0] timer_q, timer_d;
reg boot_q, boot_d;
reg [2:0] heartbeat_sq;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
state_q <= ST_IDLE;
wr_length_q <= 'd0;
rd_length_q <= 'd0;
timer_q <= 'd0;
boot_q <= 1'b0;
heartbeat_sq <= 3'd0;
end else begin
state_q <= state_d;
wr_length_q <= wr_length_d;
rd_length_q <= rd_length_d;
timer_q <= timer_d;
boot_q <= boot_d;
heartbeat_sq <= {heartbeat_i, heartbeat_sq[2:1]};
end
end
reg en;
reg wr_valid;
reg rd_ready;
reg in_valid;
reg out_ready;
wire wr_ready;
wire [7:0] rd_data;
wire rd_valid;
assign in_data_o = rd_data;
assign in_valid_o = in_valid;
assign out_ready_o = out_ready;
assign boot_o = boot_q;
always @(/*AS*/heartbeat_sq or in_ready_i or out_data_i
or out_valid_i or rd_length_q or rd_valid or state_q
or timer_q or wr_length_q or wr_ready) begin
state_d = state_q;
wr_length_d = wr_length_q;
rd_length_d = rd_length_q;
if (heartbeat_sq[1] != heartbeat_sq[0])
timer_d = 'd0;
else
timer_d = timer_q + 1;
boot_d = 1'b0;
en = 1'b0;
wr_valid = 1'b0;
rd_ready = 1'b0;
in_valid = 1'b0;
out_ready = 1'b0;
if (timer_q[TIMER_MSB])
state_d = ST_BOOT;
case (state_q)
ST_IDLE : begin
out_ready = 1'b1;
if (out_valid_i == 1'b1) begin
if (out_data_i == 8'h00)
state_d = ST_BOOT;
else if (out_data_i == 8'h01)
state_d = ST_WR_LO_LENGTH;
end
end
ST_WR_LO_LENGTH : begin
out_ready = 1'b1;
if (out_valid_i == 1'b1) begin
state_d = ST_WR_HI_LENGTH;
wr_length_d[7:0] = out_data_i;
end
end
ST_WR_HI_LENGTH : begin
out_ready = 1'b1;
if (out_valid_i == 1'b1) begin
state_d = ST_RD_LO_LENGTH;
wr_length_d[15:8] = out_data_i;
end
end
ST_RD_LO_LENGTH : begin
out_ready = 1'b1;
if (out_valid_i == 1'b1) begin
state_d = ST_RD_HI_LENGTH;
rd_length_d[7:0] = out_data_i;
end
end
ST_RD_HI_LENGTH : begin
out_ready = 1'b1;
if (out_valid_i == 1'b1) begin
state_d = ST_WR_DATA;
rd_length_d[15:8] = out_data_i;
end
end
ST_WR_DATA : begin
en = 1'b1;
if (wr_length_q == 'd0) begin
if (rd_length_q == 'd0)
state_d = ST_IDLE;
else if (rd_valid)
state_d = ST_RD_DATA;
end else begin
wr_valid = out_valid_i;
out_ready = wr_ready;
if (wr_ready & out_valid_i)
wr_length_d = wr_length_q - 1;
end
end
ST_RD_DATA : begin
en = 1'b1;
if (rd_length_q == 'd0) begin
state_d = ST_IDLE;
end else begin
in_valid = rd_valid;
rd_ready = in_ready_i;
if (rd_valid & in_ready_i)
rd_length_d = rd_length_q - 1;
end
end
ST_BOOT : begin
boot_d = 1'b1;
end
default : begin
state_d = ST_IDLE;
end
endcase
end
spi #(.SCK_PERIOD_MULTIPLIER('d2))
u_spi (.clk_i(clk_i),
.rstn_i(rstn),
.en_i(en),
.wr_data_i(out_data_i),
.wr_valid_i(wr_valid),
.wr_ready_o(wr_ready),
.rd_data_o(rd_data),
.rd_valid_o(rd_valid),
.rd_ready_i(rd_ready),
.sck_o(sck_o),
.csn_o(csn_o),
.mosi_o(mosi_o),
.miso_i(miso_i));
endmodule |
module bootloader
(
input clk, // 16MHz Clock
output led, // User LED ON=1, OFF=0
inout usb_p, // USB+
inout usb_n, // USB-
output usb_pu, // USB 1.5kOhm Pullup EN
output sck,
output ss,
output sdo,
input sdi
);
localparam CHANNELS = 'd1;
localparam BIT_SAMPLES = 'd4;
localparam [6:0] DIVF = 12*BIT_SAMPLES-1;
wire clk_pll;
wire lock;
wire dp_pu;
wire dp_rx;
wire dn_rx;
wire dp_tx;
wire dn_tx;
wire tx_en;
wire [7:0] out_data;
wire out_valid;
wire in_ready;
wire [7:0] in_data;
wire in_valid;
wire out_ready;
wire boot;
wire [10:0] frame;
wire configured;
assign led = (configured) ? frame[9] : ~&frame[4:3];
// if FEEDBACK_PATH = SIMPLE:
// clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
SB_PLL40_CORE #(.DIVR(4'd0),
.DIVF(DIVF),
.DIVQ(3'd4),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0))
u_pll (.REFERENCECLK(clk), // 16MHz
.PLLOUTCORE(),
.PLLOUTGLOBAL(clk_pll), // 48MHz
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'd0),
.LOCK(lock),
.BYPASS(1'b0),
.RESETB(1'b1),
.SDI(1'b0),
.SDO(),
.SCLK(1'b0),
.LATCHINPUTVALUE(1'b1));
app u_app (.clk_i(clk),
.rstn_i(lock),
.out_data_i(out_data),
.out_valid_i(out_valid),
.in_ready_i(in_ready),
.out_ready_o(out_ready),
.in_data_o(in_data),
.in_valid_o(in_valid),
.heartbeat_i(configured & frame[0]),
.boot_o(boot),
.sck_o(sck),
.csn_o(ss),
.mosi_o(sdo),
.miso_i(sdi));
usb_cdc #(.VENDORID(16'h1D50),
.PRODUCTID(16'h6130),
.CHANNELS(CHANNELS),
.IN_BULK_MAXPACKETSIZE('d8),
.OUT_BULK_MAXPACKETSIZE('d8),
.BIT_SAMPLES(BIT_SAMPLES),
.USE_APP_CLK(1),
.APP_CLK_FREQ(16)) // 16MHz
u_usb_cdc (.frame_o(frame),
.configured_o(configured),
.app_clk_i(clk),
.clk_i(clk_pll),
.rstn_i(lock),
.out_ready_i(out_ready),
.in_data_i(in_data),
.in_valid_i(in_valid),
.dp_rx_i(dp_rx),
.dn_rx_i(dn_rx),
.out_data_o(out_data),
.out_valid_o(out_valid),
.in_ready_o(in_ready),
.dp_pu_o(dp_pu),
.tx_en_o(tx_en),
.dp_tx_o(dp_tx),
.dn_tx_o(dn_tx));
SB_WARMBOOT u_warmboot (.S1(1'b0),
.S0(1'b1),
.BOOT(boot));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_p (.PACKAGE_PIN(usb_p),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dp_tx),
.D_IN_0(dp_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_n (.PACKAGE_PIN(usb_n),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dn_tx),
.D_IN_0(dn_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
// drive usb_pu to 3.3V or to high impedance
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_pu (.PACKAGE_PIN(usb_pu),
.OUTPUT_ENABLE(dp_pu),
.D_OUT_0(1'b1),
.D_IN_0(),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
endmodule |
module loopback_2ch
(
input clk, // 16MHz Clock
output led, // User LED ON=1, OFF=0
inout usb_p, // USB+
inout usb_n, // USB-
output usb_pu // USB 1.5kOhm Pullup EN
);
localparam CHANNELS = 'd2;
localparam BIT_SAMPLES = 'd4;
localparam [6:0] DIVF = 12*BIT_SAMPLES-1;
wire clk_pll;
wire clk_prescaler;
wire clk_usb;
wire clk_app;
wire clk_div2;
wire clk_div4;
wire clk_div8;
wire clk_div16;
wire lock;
wire dp_pu;
wire dp_rx;
wire dn_rx;
wire dp_tx;
wire dn_tx;
wire tx_en;
wire [8*CHANNELS-1:0] out_data;
wire [CHANNELS-1:0] out_valid;
wire [CHANNELS-1:0] in_ready;
wire [10:0] frame;
wire configured;
localparam CONF = 0;
localparam [2:0] DIVQ =
(CONF == 0) ? 3'd2 : // 192MHz
(CONF == 1) ? 3'd4 : // 48MHz
(CONF == 2) ? 3'd4 : // 48MHz
3'd4; // 48MHz
localparam APP_CLK_FREQ =
(CONF == 0) ? 192 : // 192MHz
(CONF == 1) ? 12 : // 12MHz
(CONF == 2) ? 2 : // 2MHz
12; // Not used
localparam USE_APP_CLK =
(CONF == 0) ? 1 :
(CONF == 1) ? 1 :
(CONF == 2) ? 1 :
0;
generate
if (CONF == 0) begin : u_conf_0
assign clk_prescaler = clk_pll; // 192MHz
assign clk_app = clk_pll;
assign clk_usb = clk_div4; // 48MHz
end else if (CONF == 1) begin : u_conf_1
assign clk_prescaler = clk_pll; // 48MHz
assign clk_app = clk_div4; // 12MHz
assign clk_usb = clk_pll;
end else if (CONF == 2) begin : u_conf_2
assign clk_prescaler = clk; // 16MHz
assign clk_app = clk_div8; // 2MHz
assign clk_usb = clk_pll;
end else begin : u_conf_3
assign clk_prescaler = 1'b0; // Not used
assign clk_app = 1'b0; // Not used
assign clk_usb = clk_pll;
end
endgenerate
assign led = (configured) ? frame[9] : ~&frame[4:3];
// if FEEDBACK_PATH = SIMPLE:
// clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
SB_PLL40_CORE #(.DIVR(4'd0),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0))
u_pll (.REFERENCECLK(clk), // 16MHz
.PLLOUTCORE(),
.PLLOUTGLOBAL(clk_pll),
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'd0),
.LOCK(lock),
.BYPASS(1'b0),
.RESETB(1'b1),
.SDI(1'b0),
.SDO(),
.SCLK(1'b0),
.LATCHINPUTVALUE(1'b1));
prescaler u_prescaler (.clk_i(clk_prescaler),
.rstn_i(lock),
.clk_div2_o(clk_div2),
.clk_div4_o(clk_div4),
.clk_div8_o(clk_div8),
.clk_div16_o(clk_div16));
usb_cdc #(.VENDORID(16'h1D50),
.PRODUCTID(16'h6130),
.CHANNELS(CHANNELS),
.IN_BULK_MAXPACKETSIZE('d8),
.OUT_BULK_MAXPACKETSIZE('d8),
.BIT_SAMPLES(BIT_SAMPLES),
.USE_APP_CLK(USE_APP_CLK),
.APP_CLK_FREQ(APP_CLK_FREQ))
u_usb_cdc (.frame_o(frame),
.configured_o(configured),
.app_clk_i(clk_app),
.clk_i(clk_usb),
.rstn_i(lock),
.out_ready_i(in_ready),
.in_data_i(out_data),
.in_valid_i(out_valid),
.dp_rx_i(dp_rx),
.dn_rx_i(dn_rx),
.out_data_o(out_data),
.out_valid_o(out_valid),
.in_ready_o(in_ready),
.dp_pu_o(dp_pu),
.tx_en_o(tx_en),
.dp_tx_o(dp_tx),
.dn_tx_o(dn_tx));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_p (.PACKAGE_PIN(usb_p),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dp_tx),
.D_IN_0(dp_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_n (.PACKAGE_PIN(usb_n),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dn_tx),
.D_IN_0(dn_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
// drive usb_pu to 3.3V or to high impedance
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_pu (.PACKAGE_PIN(usb_pu),
.OUTPUT_ENABLE(dp_pu),
.D_OUT_0(1'b1),
.D_IN_0(),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
endmodule |
module demo
(
input clk, // 16MHz Clock
output led, // User LED ON=1, OFF=0
inout usb_p, // USB+
inout usb_n, // USB-
output usb_pu, // USB 1.5kOhm Pullup EN
output sck,
output ss,
output sdo,
input sdi
);
localparam CHANNELS = 'd1;
localparam BIT_SAMPLES = 'd4;
localparam [6:0] DIVF = 12*BIT_SAMPLES-1;
wire clk_pll;
wire clk_prescaler;
wire clk_usb;
wire clk_app;
wire clk_div2;
wire clk_div4;
wire clk_div8;
wire clk_div16;
wire lock;
wire dp_pu;
wire dp_rx;
wire dn_rx;
wire dp_tx;
wire dn_tx;
wire tx_en;
wire [8*CHANNELS-1:0] out_data;
wire [CHANNELS-1:0] out_valid;
wire [CHANNELS-1:0] in_ready;
wire [8*CHANNELS-1:0] in_data;
wire [CHANNELS-1:0] in_valid;
wire [CHANNELS-1:0] out_ready;
localparam CONF = 2;
localparam [2:0] DIVQ =
(CONF == 0) ? 3'd2 : // 192MHz
(CONF == 1) ? 3'd4 : // 48MHz
(CONF == 2) ? 3'd4 : // 48MHz
3'd4; // 48MHz
localparam APP_CLK_FREQ =
(CONF == 0) ? 192 : // 192MHz
(CONF == 1) ? 12 : // 12MHz
(CONF == 2) ? 2 : // 2MHz
12; // Not used
localparam USE_APP_CLK =
(CONF == 0) ? 1 :
(CONF == 1) ? 1 :
(CONF == 2) ? 1 :
0;
generate
if (CONF == 0) begin : u_conf_0
assign clk_prescaler = clk_pll; // 192MHz
assign clk_app = clk_pll;
assign clk_usb = clk_div4; // 48MHz
end else if (CONF == 1) begin : u_conf_1
assign clk_prescaler = clk_pll; // 48MHz
assign clk_app = clk_div4; // 12MHz
assign clk_usb = clk_pll;
end else if (CONF == 2) begin : u_conf_2
assign clk_prescaler = clk; // 16MHz
assign clk_app = clk_div8; // 2MHz
assign clk_usb = clk_pll;
end else begin : u_conf_3
assign clk_prescaler = 1'b0; // Not used
assign clk_app = 1'b0; // Not used
assign clk_usb = clk_pll;
end
endgenerate
assign led = ~dp_pu;
// if FEEDBACK_PATH = SIMPLE:
// clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
SB_PLL40_CORE #(.DIVR(4'd0),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0))
u_pll (.REFERENCECLK(clk), // 16MHz
.PLLOUTCORE(),
.PLLOUTGLOBAL(clk_pll),
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'd0),
.LOCK(lock),
.BYPASS(1'b0),
.RESETB(1'b1),
.SDI(1'b0),
.SDO(),
.SCLK(1'b0),
.LATCHINPUTVALUE(1'b1));
prescaler u_prescaler (.clk_i(clk_prescaler),
.rstn_i(lock),
.clk_div2_o(clk_div2),
.clk_div4_o(clk_div4),
.clk_div8_o(clk_div8),
.clk_div16_o(clk_div16));
app u_app (.clk_i(clk_app),
.rstn_i(lock),
.out_data_i(out_data),
.out_valid_i(out_valid),
.in_ready_i(in_ready),
.out_ready_o(out_ready),
.in_data_o(in_data),
.in_valid_o(in_valid),
.sck_o(sck),
.csn_o(ss),
.mosi_o(sdo),
.miso_i(sdi));
usb_cdc #(.VENDORID(16'h1D50),
.PRODUCTID(16'h6130),
.CHANNELS(CHANNELS),
.IN_BULK_MAXPACKETSIZE('d8),
.OUT_BULK_MAXPACKETSIZE('d8),
.BIT_SAMPLES(BIT_SAMPLES),
.USE_APP_CLK(USE_APP_CLK),
.APP_CLK_FREQ(APP_CLK_FREQ))
u_usb_cdc (.frame_o(),
.configured_o(),
.app_clk_i(clk_app),
.clk_i(clk_usb),
.rstn_i(lock),
.out_ready_i(out_ready),
.in_data_i(in_data),
.in_valid_i(in_valid),
.dp_rx_i(dp_rx),
.dn_rx_i(dn_rx),
.out_data_o(out_data),
.out_valid_o(out_valid),
.in_ready_o(in_ready),
.dp_pu_o(dp_pu),
.tx_en_o(tx_en),
.dp_tx_o(dp_tx),
.dn_tx_o(dn_tx));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_p (.PACKAGE_PIN(usb_p),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dp_tx),
.D_IN_0(dp_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_n (.PACKAGE_PIN(usb_n),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dn_tx),
.D_IN_0(dn_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
// drive usb_pu to 3.3V or to high impedance
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_pu (.PACKAGE_PIN(usb_pu),
.OUTPUT_ENABLE(dp_pu),
.D_OUT_0(1'b1),
.D_IN_0(),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
endmodule |
module app
(
input clk_i,
input rstn_i,
// ---- to/from USB_CDC ------------------------------------------
output [7:0] in_data_o,
output in_valid_o,
// While in_valid_o is high, in_data_o shall be valid.
input in_ready_i,
// When both in_ready_i and in_valid_o are high, in_data_o shall
// be consumed.
input [7:0] out_data_i,
input out_valid_i,
// While out_valid_i is high, the out_data_i shall be valid and both
// out_valid_i and out_data_i shall not change until consumed.
output out_ready_o,
// When both out_valid_i and out_ready_o are high, the out_data_i shall
// be consumed.
output sck_o,
output csn_o,
output mosi_o,
input miso_i
);
function [31:0] crc32;
input [7:0] data;
input [31:0] crc;
localparam [31:0] POLY32 = 32'h04C11DB7;
reg [3:0] i;
begin
crc32 = crc;
for (i = 0; i <= 7; i = i + 1) begin
if ((data[i[2:0]] ^ crc32[31]) == 1'b1)
crc32 = {crc32[30:0], 1'b0} ^ POLY32;
else
crc32 = {crc32[30:0], 1'b0};
end
end
endfunction
function [7:0] rev8;
input [7:0] data;
reg [3:0] i;
begin
for (i = 0; i <= 7; i = i + 1) begin
rev8[i[2:0]] = data[7-i];
end
end
endfunction
function integer ceil_log2;
input [31:0] arg;
integer i;
begin
ceil_log2 = 0;
for (i = 0; i < 32; i = i + 1) begin
if (arg > (1 << i))
ceil_log2 = ceil_log2 + 1;
end
end
endfunction
localparam [31:0] RESI32 = 32'hC704DD7B; // = rev32(~32'h2144DF1C)
localparam [23:0] LFSR_POLY24 = 24'b111000010000000000000000;
reg [1:0] rstn_sq;
wire rstn;
assign rstn = rstn_sq[0];
always @(posedge clk_i or negedge rstn_i) begin
if (~rstn_i) begin
rstn_sq <= 2'd0;
end else begin
rstn_sq <= {1'b1, rstn_sq[1]};
end
end
localparam [3:0] RESET_STATE = 4'd0,
LOOPBACK_STATE = 4'd1,
CMD0_STATE = 4'd2,
CMD1_STATE = 4'd3,
CMD2_STATE = 4'd4,
CMD3_STATE = 4'd5,
IN_STATE = 4'd6,
OUT_STATE = 4'd7,
READ0_STATE = 4'd8,
READ1_STATE = 4'd9,
READ2_STATE = 4'd10,
READ3_STATE = 4'd11,
READ_ROM_STATE = 4'd12,
READ_RAM_STATE = 4'd13,
READ_FLASH_STATE = 4'd14,
WRITE_FLASH_STATE = 4'd15;
localparam [7:0] NO_CMD = 8'd0,
IN_CMD = 8'd1,
OUT_CMD = 8'd2,
ADDR_CMD = 8'd3,
WAIT_CMD = 8'd4,
LFSR_WRITE_CMD = 8'd5,
LFSR_READ_CMD = 8'd6,
ROM_READ_CMD = 8'd7,
RAM_READ_CMD = 8'd8,
FLASH_READ_CMD = 8'd9,
FLASH_WRITE_CMD = 8'd10,
FLASH_READ_STATUS_CMD = 8'd11,
FLASH_CLEAR_STATUS_CMD = 8'd12;
localparam ROM_SIZE = 'd1024; // byte size
localparam RAM_SIZE = 'd1024; // byte size
localparam FLASH_SIZE = 'd1048576; // byte size
localparam FLASH_BLOCK_SIZE = 'd4096; // byte size
reg [7:0] out_data_q;
reg out_valid_q;
reg [3:0] state_q, state_d;
reg [7:0] cmd_q, cmd_d;
reg [31:0] crc32_q, crc32_d;
reg [23:0] lfsr_q, lfsr_d;
reg [23:0] byte_cnt_q, byte_cnt_d;
reg [7:0] wait_q, wait_d;
reg [7:0] wait_cnt_q, wait_cnt_d;
reg mem_valid_q, mem_valid_d;
reg [23:0] mem_addr_q, mem_addr_d;
reg out_ready;
wire wait_end;
wire out_valid;
assign wait_end = ~|wait_cnt_q;
assign out_valid = out_valid_i & wait_end;
assign out_ready_o = (~out_valid_q | out_ready) & wait_end;
always @(posedge clk_i or negedge rstn) begin
if (~rstn) begin
out_data_q <= 8'd0;
out_valid_q <= 1'b0;
state_q <= RESET_STATE;
cmd_q <= NO_CMD;
crc32_q <= 32'd0;
lfsr_q <= 24'd0;
byte_cnt_q <= 24'd0;
wait_q <= 8'd0;
wait_cnt_q <= 8'd0;
mem_valid_q <= 1'b0;
mem_addr_q <= 'd0;
end else begin
if (out_valid & (~out_valid_q | out_ready)) begin
out_data_q <= out_data_i;
out_valid_q <= 1'b1;
end else if (out_ready)
out_valid_q <= 1'b0;
state_q <= state_d;
cmd_q <= cmd_d;
crc32_q <= crc32_d;
lfsr_q <= lfsr_d;
byte_cnt_q <= byte_cnt_d;
wait_q <= wait_d;
if (~wait_end)
wait_cnt_q <= wait_cnt_q - 1;
else
wait_cnt_q <= wait_cnt_d;
mem_valid_q <= mem_valid_d;
mem_addr_q <= mem_addr_d;
end
end
localparam USERDATA_ADDR = 'h50000;
reg [7:0] in_data;
reg in_valid;
reg rom_clke;
reg ram_clke;
reg ram_we;
reg flash_out_en;
reg flash_in_en;
reg flash_in_ready;
reg flash_out_valid;
reg flash_clear_status;
reg [ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)-1:0] start_block_addr;
reg [ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)-1:0] end_block_addr;
wire in_ready;
wire flash_out_ready;
wire flash_in_valid;
wire [7:0] flash_in_data;
wire [7:0] rom_data;
wire [7:0] ram_rdata;
wire [3:0] flash_status;
assign in_data_o = in_data;
assign in_valid_o = in_valid & wait_end;
assign in_ready = in_ready_i & wait_end;
always @(/*AS*/byte_cnt_q or cmd_q or crc32_q or flash_in_data
or flash_in_valid or flash_out_ready or flash_status
or in_ready or lfsr_q or mem_addr_q or mem_valid_q
or out_data_q or out_valid_q or ram_rdata or rom_data
or state_q or wait_q) begin
state_d = state_q;
cmd_d = cmd_q;
crc32_d = crc32_q;
lfsr_d = lfsr_q;
byte_cnt_d = byte_cnt_q;
wait_d = wait_q;
wait_cnt_d = 8'd0;
mem_valid_d = mem_valid_q;
mem_addr_d = mem_addr_q;
in_data = out_data_q;
in_valid = 1'b0;
out_ready = 1'b0;
rom_clke = 1'b0;
ram_clke = 1'b0;
ram_we = 1'b0;
flash_out_en = 1'b0;
flash_in_en = 1'b0;
start_block_addr = {(ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)){1'b1}};
end_block_addr = {(ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)){1'b1}};
flash_in_ready = 1'b0;
flash_out_valid = 1'b0;
flash_clear_status = 1'b0;
case (state_q)
RESET_STATE: begin
if (out_valid_q == 1'b1)
state_d = LOOPBACK_STATE;
end
LOOPBACK_STATE: begin
if (out_valid_q == 1'b1) begin
if (out_data_q == 8'h00) begin
state_d = CMD0_STATE;
out_ready = 1'b1;
end else begin
in_valid = 1'b1;
out_ready = in_ready;
if (in_ready == 1'b1) begin
ram_clke = 1'b1;
ram_we = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
end
end
if (&flash_status)
flash_clear_status = 1'b1;
end
CMD0_STATE: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD1_STATE;
cmd_d = out_data_q;
end
mem_valid_d = 1'b0;
end
CMD1_STATE: begin
case (cmd_q)
IN_CMD, OUT_CMD, ROM_READ_CMD, RAM_READ_CMD, FLASH_READ_CMD, FLASH_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
byte_cnt_d[7:0] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
mem_addr_d[7:0] = out_data_q;
end
end
WAIT_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
wait_d = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD2_STATE;
lfsr_d[7:0] = out_data_q;
end
end
LFSR_READ_CMD: begin
state_d = READ0_STATE;
end
FLASH_READ_STATUS_CMD: begin
state_d = READ0_STATE;
end
FLASH_CLEAR_STATUS_CMD: begin
flash_clear_status = 1'b1;
state_d = LOOPBACK_STATE;
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
CMD2_STATE: begin
case (cmd_q)
IN_CMD, OUT_CMD, ROM_READ_CMD, RAM_READ_CMD, FLASH_READ_CMD, FLASH_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
byte_cnt_d[15:8] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
mem_addr_d[15:8] = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = CMD3_STATE;
lfsr_d[15:8] = out_data_q;
end
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
CMD3_STATE: begin
case (cmd_q)
IN_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = IN_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
OUT_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = OUT_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
ADDR_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
mem_addr_d[23:16] = out_data_q;
end
end
LFSR_WRITE_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = LOOPBACK_STATE;
lfsr_d[23:16] = out_data_q;
end
end
ROM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = READ_ROM_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
RAM_READ_CMD: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = READ_RAM_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
FLASH_READ_CMD: begin
flash_in_en = 1'b1;
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = READ_FLASH_STATE;
byte_cnt_d[23:16] = out_data_q;
end
end
FLASH_WRITE_CMD: begin
flash_out_en = 1'b1;
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
state_d = WRITE_FLASH_STATE;
byte_cnt_d[23:16] = out_data_q;
end
if (mem_addr_q[ceil_log2(FLASH_SIZE)-1:ceil_log2(FLASH_BLOCK_SIZE)] < USERDATA_ADDR[ceil_log2(FLASH_SIZE)-1:ceil_log2(FLASH_BLOCK_SIZE)])
mem_addr_d = USERDATA_ADDR;
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
crc32_d = 32'hFFFFFFFF;
end
IN_STATE: begin
in_data = lfsr_q[7:0];
in_valid = 1'b1;
if (in_ready == 1'b1) begin
crc32_d = crc32(lfsr_q[7:0], crc32_q);
lfsr_d = {lfsr_q[22:0], ~^(lfsr_q & LFSR_POLY24)};
if (byte_cnt_q == 24'd0)
state_d = READ0_STATE;
else
byte_cnt_d = byte_cnt_q - 1;
wait_cnt_d = wait_q;
end
end
OUT_STATE: begin
out_ready = 1'b1;
if (out_valid_q == 1'b1) begin
crc32_d = crc32(out_data_q, crc32_q);
if (byte_cnt_q == 24'd0)
state_d = READ0_STATE;
else
byte_cnt_d = byte_cnt_q - 1;
wait_cnt_d = wait_q;
end
end
READ0_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ1_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[7:0];
else if (cmd_q == FLASH_READ_STATUS_CMD)
in_data = {4'd0, flash_status};
else
in_data = rev8(~crc32_q[31:24]);
end
READ1_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ2_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[15:8];
else if (cmd_q == FLASH_READ_STATUS_CMD)
in_data = 8'd0;
else
in_data = rev8(~crc32_q[23:16]);
end
READ2_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = READ3_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = lfsr_q[23:16];
else if (cmd_q == FLASH_READ_STATUS_CMD)
in_data = 8'd0;
else
in_data = rev8(~crc32_q[15:8]);
end
READ3_STATE: begin
in_valid = 1'b1;
if (in_ready == 1'b1) begin
state_d = LOOPBACK_STATE;
end
if (cmd_q == LFSR_READ_CMD)
in_data = 8'd0;
else if (cmd_q == FLASH_READ_STATUS_CMD)
in_data = 8'd0;
else
in_data = rev8(~crc32_q[7:0]);
end
READ_ROM_STATE: begin
if (mem_valid_q == 1'b0) begin
rom_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
in_data = rom_data;
in_valid = mem_valid_q;
if (in_ready == 1'b1 && mem_valid_q == 1'b1) begin
mem_valid_d = 1'b0;
if (byte_cnt_q == 24'd0) begin
state_d = LOOPBACK_STATE;
mem_addr_d = 'd0;
end else begin
byte_cnt_d = byte_cnt_q - 1;
rom_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
wait_cnt_d = wait_q;
end
end
READ_RAM_STATE: begin
if (mem_valid_q == 1'b0) begin
ram_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
in_data = ram_rdata;
in_valid = mem_valid_q;
if (in_ready == 1'b1 && mem_valid_q == 1'b1) begin
mem_valid_d = 1'b0;
if (byte_cnt_q == 24'd0) begin
state_d = LOOPBACK_STATE;
mem_addr_d = 'd0;
end else begin
byte_cnt_d = byte_cnt_q - 1;
ram_clke = 1'b1;
mem_valid_d = 1'b1;
mem_addr_d = mem_addr_q + 1;
end
wait_cnt_d = wait_q;
end
end
READ_FLASH_STATE: begin
flash_in_en = 1'b1;
start_block_addr = mem_addr_q[ceil_log2(FLASH_SIZE)-1:ceil_log2(FLASH_BLOCK_SIZE)];
end_block_addr = {(ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)){1'b1}};
flash_in_ready = in_ready;
in_data = flash_in_data;
in_valid = flash_in_valid;
if (|flash_status) begin // End of operation
flash_in_ready = 1'b0;
in_valid = 1'b0;
state_d = LOOPBACK_STATE;
end else if (in_ready == 1'b1 && flash_in_valid == 1'b1) begin
if (byte_cnt_q == 24'd0) begin
state_d = LOOPBACK_STATE;
end else begin
byte_cnt_d = byte_cnt_q - 1;
end
wait_cnt_d = wait_q;
end
end
WRITE_FLASH_STATE: begin
flash_out_en = 1'b1;
start_block_addr = mem_addr_q[ceil_log2(FLASH_SIZE)-1:ceil_log2(FLASH_BLOCK_SIZE)];
end_block_addr = {(ceil_log2(FLASH_SIZE)-ceil_log2(FLASH_BLOCK_SIZE)){1'b1}};
out_ready = flash_out_ready;
flash_out_valid = out_valid_q;
if (|flash_status) begin // End of operation
out_ready = 1'b1;
flash_out_valid = 1'b0;
if (out_valid_q) begin
if (byte_cnt_q == 24'd0) begin
state_d = READ0_STATE;
end else begin
byte_cnt_d = byte_cnt_q - 1;
end
end
end else if (out_valid_q == 1'b1 && flash_out_ready == 1'b1) begin
crc32_d = crc32(out_data_q, crc32_q);
if (byte_cnt_q == 24'd0) begin
state_d = READ0_STATE;
end else begin
byte_cnt_d = byte_cnt_q - 1;
end
wait_cnt_d = wait_q;
end
end
default: begin
state_d = LOOPBACK_STATE;
end
endcase
end
rom #(.VECTOR_LENGTH(ROM_SIZE),
.WORD_WIDTH('d8),
.ADDR_WIDTH(ceil_log2(ROM_SIZE)))
u_rom (.data_o(rom_data),
.clk_i(clk_i),
.clke_i(rom_clke),
.addr_i(mem_addr_q[ceil_log2(ROM_SIZE)-1:0]));
ram #(.VECTOR_LENGTH(RAM_SIZE),
.WORD_WIDTH('d8),
.ADDR_WIDTH(ceil_log2(RAM_SIZE)))
u_ram (.rdata_o(ram_rdata),
.clk_i(clk_i),
.clke_i(ram_clke),
.we_i(ram_we),
.addr_i(mem_addr_q[ceil_log2(RAM_SIZE)-1:0]),
.mask_i(8'd0),
.wdata_i(out_data_q));
flash_spi #(.SCK_PERIOD_MULTIPLIER('d2),
.CLK_PERIODS_PER_US('d2),
.FLASH_SIZE(FLASH_SIZE),
.BLOCK_SIZE(FLASH_BLOCK_SIZE),
.PAGE_SIZE('d256),
.RESUME_US('d10),
.BLOCK_ERASE_US('d60000),
.PAGE_PROG_US('d700))
u_flash_spi (.clk_i(clk_i),
.rstn_i(rstn),
.out_en_i(flash_out_en),
.in_en_i(flash_in_en),
.start_block_addr_i(start_block_addr),
.end_block_addr_i(end_block_addr),
.read_addr_offset_i(mem_addr_q[ceil_log2(FLASH_BLOCK_SIZE)-1:0]),
.out_data_i(out_data_q),
.out_valid_i(flash_out_valid),
.out_ready_o(flash_out_ready),
.in_data_o(flash_in_data),
.in_valid_o(flash_in_valid),
.in_ready_i(flash_in_ready),
.clear_status_i(flash_clear_status),
.status_o(flash_status),
.erase_busy_o(),
.program_busy_o(),
.sck_o(sck_o),
.csn_o(csn_o),
.mosi_o(mosi_o),
.miso_i(miso_i));
endmodule |
module soc
(
input clk, // 16MHz Clock
output led, // User LED ON=1, OFF=0
inout usb_p, // USB+
inout usb_n, // USB-
output usb_pu // USB 1.5kOhm Pullup EN
);
localparam BIT_SAMPLES = 'd4;
localparam [6:0] DIVF = 12*BIT_SAMPLES-1;
wire clk_pll;
wire clk_1mhz;
wire clk_2mhz;
wire clk_4mhz;
wire clk_8mhz;
wire lock;
wire dp_pu;
wire dp_rx;
wire dn_rx;
wire dp_tx;
wire dn_tx;
wire tx_en;
wire [7:0] out_data;
wire out_valid;
wire in_ready;
wire [7:0] in_data;
wire in_valid;
wire out_ready;
// if FEEDBACK_PATH = SIMPLE:
// clk_freq = (ref_freq * (DIVF + 1)) / (2**DIVQ * (DIVR + 1));
SB_PLL40_CORE #(.DIVR(4'd0),
.DIVF(DIVF),
.DIVQ(3'd4),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0))
u_pll (.REFERENCECLK(clk), // 16MHz
.PLLOUTCORE(),
.PLLOUTGLOBAL(clk_pll), // 48MHz
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'd0),
.LOCK(lock),
.BYPASS(1'b0),
.RESETB(1'b1),
.SDI(1'b0),
.SDO(),
.SCLK(1'b0),
.LATCHINPUTVALUE(1'b1));
prescaler u_prescaler (.clk_i(clk),
.rstn_i(lock),
.clk_div16_o(clk_1mhz),
.clk_div8_o(clk_2mhz),
.clk_div4_o(clk_4mhz),
.clk_div2_o(clk_8mhz));
reg [1:0] rstn_sync;
wire rstn;
assign rstn = rstn_sync[0];
always @(posedge clk_1mhz or negedge lock) begin
if (~lock) begin
rstn_sync <= 2'd0;
end else begin
rstn_sync <= {1'b1, rstn_sync[1]};
end
end
reg [20:0] up_cnt;
reg [1:0] sleep_sq;
wire sleep;
always @(posedge clk_1mhz or negedge rstn) begin
if (~rstn) begin
up_cnt <= 'd0;
sleep_sq <= 2'b00;
end else begin
sleep_sq <= {sleep, sleep_sq[1]};
if (up_cnt[20] == 1'b0)
up_cnt <= up_cnt + 1;
else if (~sleep_sq[0])
up_cnt <= 21'hE0000;
end
end
assign led = ~dp_pu | ~up_cnt[20];
app u_app (.clk_i(clk_2mhz),
.rstn_i(rstn),
.sleep_o(sleep),
.out_data_i(out_data),
.out_valid_i(out_valid),
.in_ready_i(in_ready),
.out_ready_o(out_ready),
.in_data_o(in_data),
.in_valid_o(in_valid));
usb_cdc #(.VENDORID(16'h1D50),
.PRODUCTID(16'h6130),
.IN_BULK_MAXPACKETSIZE('d8),
.OUT_BULK_MAXPACKETSIZE('d8),
.BIT_SAMPLES(BIT_SAMPLES),
.USE_APP_CLK(1),
.APP_CLK_FREQ(2)) // 2MHz
u_usb_cdc (.frame_o(),
.configured_o(),
.app_clk_i(clk_2mhz),
.clk_i(clk_pll),
.rstn_i(rstn),
.out_ready_i(out_ready),
.in_data_i(in_data),
.in_valid_i(in_valid),
.dp_rx_i(dp_rx),
.dn_rx_i(dn_rx),
.out_data_o(out_data),
.out_valid_o(out_valid),
.in_ready_o(in_ready),
.dp_pu_o(dp_pu),
.tx_en_o(tx_en),
.dp_tx_o(dp_tx),
.dn_tx_o(dn_tx));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_p (.PACKAGE_PIN(usb_p),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dp_tx),
.D_IN_0(dp_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_n (.PACKAGE_PIN(usb_n),
.OUTPUT_ENABLE(tx_en),
.D_OUT_0(dn_tx),
.D_IN_0(dn_rx),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
// drive usb_pu to 3.3V or to high impedance
SB_IO #(.PIN_TYPE(6'b101001),
.PULLUP(1'b0))
u_usb_pu (.PACKAGE_PIN(usb_pu),
.OUTPUT_ENABLE(dp_pu),
.D_OUT_0(1'b1),
.D_IN_0(),
.D_OUT_1(1'b0),
.D_IN_1(),
.CLOCK_ENABLE(1'b0),
.LATCH_INPUT_VALUE(1'b0),
.INPUT_CLK(1'b0),
.OUTPUT_CLK(1'b0));
endmodule |
module riscv_tcm_wrapper
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter BOOT_VECTOR = 0
,parameter CORE_ID = 0
,parameter TCM_MEM_BASE = 0
,parameter MEM_CACHE_ADDR_MIN = 0
,parameter MEM_CACHE_ADDR_MAX = 32'hffffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input rst_cpu_i
,input axi_i_awready_i
,input axi_i_wready_i
,input axi_i_bvalid_i
,input [ 1:0] axi_i_bresp_i
,input [ 3:0] axi_i_bid_i
,input axi_i_arready_i
,input axi_i_rvalid_i
,input [ 31:0] axi_i_rdata_i
,input [ 1:0] axi_i_rresp_i
,input [ 3:0] axi_i_rid_i
,input axi_i_rlast_i
,input axi_t_awvalid_i
,input [ 31:0] axi_t_awaddr_i
,input [ 3:0] axi_t_awid_i
,input [ 7:0] axi_t_awlen_i
,input [ 1:0] axi_t_awburst_i
,input axi_t_wvalid_i
,input [ 31:0] axi_t_wdata_i
,input [ 3:0] axi_t_wstrb_i
,input axi_t_wlast_i
,input axi_t_bready_i
,input axi_t_arvalid_i
,input [ 31:0] axi_t_araddr_i
,input [ 3:0] axi_t_arid_i
,input [ 7:0] axi_t_arlen_i
,input [ 1:0] axi_t_arburst_i
,input axi_t_rready_i
,input [ 31:0] intr_i
// Outputs
,output axi_i_awvalid_o
,output [ 31:0] axi_i_awaddr_o
,output [ 3:0] axi_i_awid_o
,output [ 7:0] axi_i_awlen_o
,output [ 1:0] axi_i_awburst_o
,output axi_i_wvalid_o
,output [ 31:0] axi_i_wdata_o
,output [ 3:0] axi_i_wstrb_o
,output axi_i_wlast_o
,output axi_i_bready_o
,output axi_i_arvalid_o
,output [ 31:0] axi_i_araddr_o
,output [ 3:0] axi_i_arid_o
,output [ 7:0] axi_i_arlen_o
,output [ 1:0] axi_i_arburst_o
,output axi_i_rready_o
,output axi_t_awready_o
,output axi_t_wready_o
,output axi_t_bvalid_o
,output [ 1:0] axi_t_bresp_o
,output [ 3:0] axi_t_bid_o
,output axi_t_arready_o
,output axi_t_rvalid_o
,output [ 31:0] axi_t_rdata_o
,output [ 1:0] axi_t_rresp_o
,output [ 3:0] axi_t_rid_o
,output axi_t_rlast_o
);
wire [ 31:0] ifetch_pc_w;
wire [ 31:0] dport_tcm_data_rd_w;
wire dport_tcm_cacheable_w;
wire dport_flush_w;
wire [ 3:0] dport_tcm_wr_w;
wire ifetch_rd_w;
wire dport_axi_accept_w;
wire dport_cacheable_w;
wire dport_tcm_flush_w;
wire [ 10:0] dport_resp_tag_w;
wire [ 10:0] dport_axi_resp_tag_w;
wire ifetch_accept_w;
wire [ 31:0] dport_data_rd_w;
wire dport_tcm_invalidate_w;
wire dport_ack_w;
wire [ 10:0] dport_axi_req_tag_w;
wire [ 31:0] dport_data_wr_w;
wire dport_invalidate_w;
wire [ 10:0] dport_tcm_req_tag_w;
wire [ 31:0] dport_tcm_addr_w;
wire dport_axi_error_w;
wire dport_tcm_ack_w;
wire dport_tcm_rd_w;
wire [ 10:0] dport_tcm_resp_tag_w;
wire dport_writeback_w;
wire [ 31:0] cpu_id_w = CORE_ID;
wire dport_rd_w;
wire dport_axi_ack_w;
wire dport_axi_rd_w;
wire [ 31:0] dport_axi_data_rd_w;
wire dport_axi_invalidate_w;
wire [ 31:0] boot_vector_w = BOOT_VECTOR;
wire [ 31:0] dport_addr_w;
wire ifetch_error_w;
wire [ 31:0] dport_tcm_data_wr_w;
wire ifetch_flush_w;
wire [ 31:0] dport_axi_addr_w;
wire dport_error_w;
wire dport_tcm_accept_w;
wire ifetch_invalidate_w;
wire dport_axi_writeback_w;
wire [ 3:0] dport_wr_w;
wire ifetch_valid_w;
wire [ 31:0] dport_axi_data_wr_w;
wire [ 10:0] dport_req_tag_w;
wire [ 31:0] ifetch_inst_w;
wire dport_axi_cacheable_w;
wire dport_tcm_writeback_w;
wire [ 3:0] dport_axi_wr_w;
wire dport_axi_flush_w;
wire dport_tcm_error_w;
wire dport_accept_w;
riscv_core
#(
.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
)
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_cpu_i)
,.mem_d_data_rd_i(dport_data_rd_w)
,.mem_d_accept_i(dport_accept_w)
,.mem_d_ack_i(dport_ack_w)
,.mem_d_error_i(dport_error_w)
,.mem_d_resp_tag_i(dport_resp_tag_w)
,.mem_i_accept_i(ifetch_accept_w)
,.mem_i_valid_i(ifetch_valid_w)
,.mem_i_error_i(ifetch_error_w)
,.mem_i_inst_i(ifetch_inst_w)
,.intr_i(intr_i[0:0])
,.reset_vector_i(boot_vector_w)
,.cpu_id_i(cpu_id_w)
// Outputs
,.mem_d_addr_o(dport_addr_w)
,.mem_d_data_wr_o(dport_data_wr_w)
,.mem_d_rd_o(dport_rd_w)
,.mem_d_wr_o(dport_wr_w)
,.mem_d_cacheable_o(dport_cacheable_w)
,.mem_d_req_tag_o(dport_req_tag_w)
,.mem_d_invalidate_o(dport_invalidate_w)
,.mem_d_writeback_o(dport_writeback_w)
,.mem_d_flush_o(dport_flush_w)
,.mem_i_rd_o(ifetch_rd_w)
,.mem_i_flush_o(ifetch_flush_w)
,.mem_i_invalidate_o(ifetch_invalidate_w)
,.mem_i_pc_o(ifetch_pc_w)
);
dport_mux
#(
.TCM_MEM_BASE(TCM_MEM_BASE)
)
u_dmux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_addr_w)
,.mem_data_wr_i(dport_data_wr_w)
,.mem_rd_i(dport_rd_w)
,.mem_wr_i(dport_wr_w)
,.mem_cacheable_i(dport_cacheable_w)
,.mem_req_tag_i(dport_req_tag_w)
,.mem_invalidate_i(dport_invalidate_w)
,.mem_writeback_i(dport_writeback_w)
,.mem_flush_i(dport_flush_w)
,.mem_tcm_data_rd_i(dport_tcm_data_rd_w)
,.mem_tcm_accept_i(dport_tcm_accept_w)
,.mem_tcm_ack_i(dport_tcm_ack_w)
,.mem_tcm_error_i(dport_tcm_error_w)
,.mem_tcm_resp_tag_i(dport_tcm_resp_tag_w)
,.mem_ext_data_rd_i(dport_axi_data_rd_w)
,.mem_ext_accept_i(dport_axi_accept_w)
,.mem_ext_ack_i(dport_axi_ack_w)
,.mem_ext_error_i(dport_axi_error_w)
,.mem_ext_resp_tag_i(dport_axi_resp_tag_w)
// Outputs
,.mem_data_rd_o(dport_data_rd_w)
,.mem_accept_o(dport_accept_w)
,.mem_ack_o(dport_ack_w)
,.mem_error_o(dport_error_w)
,.mem_resp_tag_o(dport_resp_tag_w)
,.mem_tcm_addr_o(dport_tcm_addr_w)
,.mem_tcm_data_wr_o(dport_tcm_data_wr_w)
,.mem_tcm_rd_o(dport_tcm_rd_w)
,.mem_tcm_wr_o(dport_tcm_wr_w)
,.mem_tcm_cacheable_o(dport_tcm_cacheable_w)
,.mem_tcm_req_tag_o(dport_tcm_req_tag_w)
,.mem_tcm_invalidate_o(dport_tcm_invalidate_w)
,.mem_tcm_writeback_o(dport_tcm_writeback_w)
,.mem_tcm_flush_o(dport_tcm_flush_w)
,.mem_ext_addr_o(dport_axi_addr_w)
,.mem_ext_data_wr_o(dport_axi_data_wr_w)
,.mem_ext_rd_o(dport_axi_rd_w)
,.mem_ext_wr_o(dport_axi_wr_w)
,.mem_ext_cacheable_o(dport_axi_cacheable_w)
,.mem_ext_req_tag_o(dport_axi_req_tag_w)
,.mem_ext_invalidate_o(dport_axi_invalidate_w)
,.mem_ext_writeback_o(dport_axi_writeback_w)
,.mem_ext_flush_o(dport_axi_flush_w)
);
tcm_mem
u_tcm
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_i_rd_i(ifetch_rd_w)
,.mem_i_flush_i(ifetch_flush_w)
,.mem_i_invalidate_i(ifetch_invalidate_w)
,.mem_i_pc_i(ifetch_pc_w)
,.mem_d_addr_i(dport_tcm_addr_w)
,.mem_d_data_wr_i(dport_tcm_data_wr_w)
,.mem_d_rd_i(dport_tcm_rd_w)
,.mem_d_wr_i(dport_tcm_wr_w)
,.mem_d_cacheable_i(dport_tcm_cacheable_w)
,.mem_d_req_tag_i(dport_tcm_req_tag_w)
,.mem_d_invalidate_i(dport_tcm_invalidate_w)
,.mem_d_writeback_i(dport_tcm_writeback_w)
,.mem_d_flush_i(dport_tcm_flush_w)
,.axi_awvalid_i(axi_t_awvalid_i)
,.axi_awaddr_i(axi_t_awaddr_i)
,.axi_awid_i(axi_t_awid_i)
,.axi_awlen_i(axi_t_awlen_i)
,.axi_awburst_i(axi_t_awburst_i)
,.axi_wvalid_i(axi_t_wvalid_i)
,.axi_wdata_i(axi_t_wdata_i)
,.axi_wstrb_i(axi_t_wstrb_i)
,.axi_wlast_i(axi_t_wlast_i)
,.axi_bready_i(axi_t_bready_i)
,.axi_arvalid_i(axi_t_arvalid_i)
,.axi_araddr_i(axi_t_araddr_i)
,.axi_arid_i(axi_t_arid_i)
,.axi_arlen_i(axi_t_arlen_i)
,.axi_arburst_i(axi_t_arburst_i)
,.axi_rready_i(axi_t_rready_i)
// Outputs
,.mem_i_accept_o(ifetch_accept_w)
,.mem_i_valid_o(ifetch_valid_w)
,.mem_i_error_o(ifetch_error_w)
,.mem_i_inst_o(ifetch_inst_w)
,.mem_d_data_rd_o(dport_tcm_data_rd_w)
,.mem_d_accept_o(dport_tcm_accept_w)
,.mem_d_ack_o(dport_tcm_ack_w)
,.mem_d_error_o(dport_tcm_error_w)
,.mem_d_resp_tag_o(dport_tcm_resp_tag_w)
,.axi_awready_o(axi_t_awready_o)
,.axi_wready_o(axi_t_wready_o)
,.axi_bvalid_o(axi_t_bvalid_o)
,.axi_bresp_o(axi_t_bresp_o)
,.axi_bid_o(axi_t_bid_o)
,.axi_arready_o(axi_t_arready_o)
,.axi_rvalid_o(axi_t_rvalid_o)
,.axi_rdata_o(axi_t_rdata_o)
,.axi_rresp_o(axi_t_rresp_o)
,.axi_rid_o(axi_t_rid_o)
,.axi_rlast_o(axi_t_rlast_o)
);
dport_axi
u_axi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_axi_addr_w)
,.mem_data_wr_i(dport_axi_data_wr_w)
,.mem_rd_i(dport_axi_rd_w)
,.mem_wr_i(dport_axi_wr_w)
,.mem_cacheable_i(dport_axi_cacheable_w)
,.mem_req_tag_i(dport_axi_req_tag_w)
,.mem_invalidate_i(dport_axi_invalidate_w)
,.mem_writeback_i(dport_axi_writeback_w)
,.mem_flush_i(dport_axi_flush_w)
,.axi_awready_i(axi_i_awready_i)
,.axi_wready_i(axi_i_wready_i)
,.axi_bvalid_i(axi_i_bvalid_i)
,.axi_bresp_i(axi_i_bresp_i)
,.axi_bid_i(axi_i_bid_i)
,.axi_arready_i(axi_i_arready_i)
,.axi_rvalid_i(axi_i_rvalid_i)
,.axi_rdata_i(axi_i_rdata_i)
,.axi_rresp_i(axi_i_rresp_i)
,.axi_rid_i(axi_i_rid_i)
,.axi_rlast_i(axi_i_rlast_i)
// Outputs
,.mem_data_rd_o(dport_axi_data_rd_w)
,.mem_accept_o(dport_axi_accept_w)
,.mem_ack_o(dport_axi_ack_w)
,.mem_error_o(dport_axi_error_w)
,.mem_resp_tag_o(dport_axi_resp_tag_w)
,.axi_awvalid_o(axi_i_awvalid_o)
,.axi_awaddr_o(axi_i_awaddr_o)
,.axi_awid_o(axi_i_awid_o)
,.axi_awlen_o(axi_i_awlen_o)
,.axi_awburst_o(axi_i_awburst_o)
,.axi_wvalid_o(axi_i_wvalid_o)
,.axi_wdata_o(axi_i_wdata_o)
,.axi_wstrb_o(axi_i_wstrb_o)
,.axi_wlast_o(axi_i_wlast_o)
,.axi_bready_o(axi_i_bready_o)
,.axi_arvalid_o(axi_i_arvalid_o)
,.axi_araddr_o(axi_i_araddr_o)
,.axi_arid_o(axi_i_arid_o)
,.axi_arlen_o(axi_i_arlen_o)
,.axi_arburst_o(axi_i_arburst_o)
,.axi_rready_o(axi_i_rready_o)
);
endmodule |
module dport_mux
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter TCM_MEM_BASE = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input [ 31:0] mem_tcm_data_rd_i
,input mem_tcm_accept_i
,input mem_tcm_ack_i
,input mem_tcm_error_i
,input [ 10:0] mem_tcm_resp_tag_i
,input [ 31:0] mem_ext_data_rd_i
,input mem_ext_accept_i
,input mem_ext_ack_i
,input mem_ext_error_i
,input [ 10:0] mem_ext_resp_tag_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 31:0] mem_tcm_addr_o
,output [ 31:0] mem_tcm_data_wr_o
,output mem_tcm_rd_o
,output [ 3:0] mem_tcm_wr_o
,output mem_tcm_cacheable_o
,output [ 10:0] mem_tcm_req_tag_o
,output mem_tcm_invalidate_o
,output mem_tcm_writeback_o
,output mem_tcm_flush_o
,output [ 31:0] mem_ext_addr_o
,output [ 31:0] mem_ext_data_wr_o
,output mem_ext_rd_o
,output [ 3:0] mem_ext_wr_o
,output mem_ext_cacheable_o
,output [ 10:0] mem_ext_req_tag_o
,output mem_ext_invalidate_o
,output mem_ext_writeback_o
,output mem_ext_flush_o
);
//-----------------------------------------------------------------
// Dcache_if mux
//-----------------------------------------------------------------
wire hold_w;
/* verilator lint_off UNSIGNED */
wire tcm_access_w = (mem_addr_i >= TCM_MEM_BASE && mem_addr_i < (TCM_MEM_BASE + 32'd65536));
/* verilator lint_on UNSIGNED */
reg tcm_access_q;
reg [4:0] pending_q;
assign mem_tcm_addr_o = mem_addr_i;
assign mem_tcm_data_wr_o = mem_data_wr_i;
assign mem_tcm_rd_o = (tcm_access_w & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_tcm_wr_o = (tcm_access_w & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_tcm_cacheable_o = mem_cacheable_i;
assign mem_tcm_req_tag_o = mem_req_tag_i;
assign mem_tcm_invalidate_o = (tcm_access_w & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_tcm_writeback_o = (tcm_access_w & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_tcm_flush_o = (tcm_access_w & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_ext_addr_o = mem_addr_i;
assign mem_ext_data_wr_o = mem_data_wr_i;
assign mem_ext_rd_o = (~tcm_access_w & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_ext_wr_o = (~tcm_access_w & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_ext_cacheable_o = mem_cacheable_i;
assign mem_ext_req_tag_o = mem_req_tag_i;
assign mem_ext_invalidate_o = (~tcm_access_w & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_ext_writeback_o = (~tcm_access_w & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_ext_flush_o = (~tcm_access_w & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_accept_o =(tcm_access_w ? mem_tcm_accept_i : mem_ext_accept_i) & !hold_w;
assign mem_data_rd_o = tcm_access_q ? mem_tcm_data_rd_i : mem_ext_data_rd_i;
assign mem_ack_o = tcm_access_q ? mem_tcm_ack_i : mem_ext_ack_i;
assign mem_error_o = tcm_access_q ? mem_tcm_error_i : mem_ext_error_i;
assign mem_resp_tag_o = tcm_access_q ? mem_tcm_resp_tag_i : mem_ext_resp_tag_i;
wire request_w = mem_rd_i || mem_wr_i != 4'b0 || mem_flush_i || mem_invalidate_i || mem_writeback_i;
reg [4:0] pending_r;
always @ *
begin
pending_r = pending_q;
if ((request_w && mem_accept_o) && !mem_ack_o)
pending_r = pending_r + 5'd1;
else if (!(request_w && mem_accept_o) && mem_ack_o)
pending_r = pending_r - 5'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pending_q <= 5'b0;
else
pending_q <= pending_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tcm_access_q <= 1'b0;
else if (request_w && mem_accept_o)
tcm_access_q <= tcm_access_w;
assign hold_w = (|pending_q) && (tcm_access_q != tcm_access_w);
endmodule |
module tcm_mem_pmem
(
// Inputs
input clk_i
,input rst_i
,input axi_awvalid_i
,input [ 31:0] axi_awaddr_i
,input [ 3:0] axi_awid_i
,input [ 7:0] axi_awlen_i
,input [ 1:0] axi_awburst_i
,input axi_wvalid_i
,input [ 31:0] axi_wdata_i
,input [ 3:0] axi_wstrb_i
,input axi_wlast_i
,input axi_bready_i
,input axi_arvalid_i
,input [ 31:0] axi_araddr_i
,input [ 3:0] axi_arid_i
,input [ 7:0] axi_arlen_i
,input [ 1:0] axi_arburst_i
,input axi_rready_i
,input ram_accept_i
,input ram_ack_i
,input ram_error_i
,input [ 31:0] ram_read_data_i
// Outputs
,output axi_awready_o
,output axi_wready_o
,output axi_bvalid_o
,output [ 1:0] axi_bresp_o
,output [ 3:0] axi_bid_o
,output axi_arready_o
,output axi_rvalid_o
,output [ 31:0] axi_rdata_o
,output [ 1:0] axi_rresp_o
,output [ 3:0] axi_rid_o
,output axi_rlast_o
,output [ 3:0] ram_wr_o
,output ram_rd_o
,output [ 7:0] ram_len_o
,output [ 31:0] ram_addr_o
,output [ 31:0] ram_write_data_o
);
//-------------------------------------------------------------
// calculate_addr_next
//-------------------------------------------------------------
function [31:0] calculate_addr_next;
input [31:0] addr;
input [1:0] axtype;
input [7:0] axlen;
reg [31:0] mask;
begin
mask = 0;
case (axtype)
`ifdef SUPPORT_FIXED_BURST
2'd0: // AXI4_BURST_FIXED
begin
calculate_addr_next = addr;
end
`endif
`ifdef SUPPORT_WRAP_BURST
2'd2: // AXI4_BURST_WRAP
begin
case (axlen)
8'd0: mask = 32'h03;
8'd1: mask = 32'h07;
8'd3: mask = 32'h0F;
8'd7: mask = 32'h1F;
8'd15: mask = 32'h3F;
default: mask = 32'h3F;
endcase
calculate_addr_next = (addr & ~mask) | ((addr + 4) & mask);
end
`endif
default: // AXI4_BURST_INCR
calculate_addr_next = addr + 4;
endcase
end
endfunction
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [7:0] req_len_q;
reg [31:0] req_addr_q;
reg req_rd_q;
reg req_wr_q;
reg [3:0] req_id_q;
reg [1:0] req_axburst_q;
reg [7:0] req_axlen_q;
reg req_prio_q;
reg req_hold_rd_q;
reg req_hold_wr_q;
wire req_fifo_accept_w;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
req_len_q <= 8'b0;
req_addr_q <= 32'b0;
req_wr_q <= 1'b0;
req_rd_q <= 1'b0;
req_id_q <= 4'b0;
req_axburst_q <= 2'b0;
req_axlen_q <= 8'b0;
req_prio_q <= 1'b0;
end
else
begin
// Burst continuation
if ((ram_wr_o != 4'b0 || ram_rd_o) && ram_accept_i)
begin
if (req_len_q == 8'd0)
begin
req_rd_q <= 1'b0;
req_wr_q <= 1'b0;
end
else
begin
req_addr_q <= calculate_addr_next(req_addr_q, req_axburst_q, req_axlen_q);
req_len_q <= req_len_q - 8'd1;
end
end
// Write command accepted
if (axi_awvalid_i && axi_awready_o)
begin
// Data ready?
if (axi_wvalid_i && axi_wready_o)
begin
req_wr_q <= !axi_wlast_i;
req_len_q <= axi_awlen_i - 8'd1;
req_id_q <= axi_awid_i;
req_axburst_q <= axi_awburst_i;
req_axlen_q <= axi_awlen_i;
req_addr_q <= calculate_addr_next(axi_awaddr_i, axi_awburst_i, axi_awlen_i);
end
// Data not ready
else
begin
req_wr_q <= 1'b1;
req_len_q <= axi_awlen_i;
req_id_q <= axi_awid_i;
req_axburst_q <= axi_awburst_i;
req_axlen_q <= axi_awlen_i;
req_addr_q <= axi_awaddr_i;
end
req_prio_q <= !req_prio_q;
end
// Read command accepted
else if (axi_arvalid_i && axi_arready_o)
begin
req_rd_q <= (axi_arlen_i != 0);
req_len_q <= axi_arlen_i - 8'd1;
req_addr_q <= calculate_addr_next(axi_araddr_i, axi_arburst_i, axi_arlen_i);
req_id_q <= axi_arid_i;
req_axburst_q <= axi_arburst_i;
req_axlen_q <= axi_arlen_i;
req_prio_q <= !req_prio_q;
end
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
req_hold_rd_q <= 1'b0;
req_hold_wr_q <= 1'b0;
end
else
begin
if (ram_rd_o && !ram_accept_i)
req_hold_rd_q <= 1'b1;
else if (ram_accept_i)
req_hold_rd_q <= 1'b0;
if ((|ram_wr_o) && !ram_accept_i)
req_hold_wr_q <= 1'b1;
else if (ram_accept_i)
req_hold_wr_q <= 1'b0;
end
//-----------------------------------------------------------------
// Request tracking
//-----------------------------------------------------------------
wire req_push_w = (ram_rd_o || (ram_wr_o != 4'b0)) && ram_accept_i;
reg [5:0] req_in_r;
wire req_out_valid_w;
wire [5:0] req_out_w;
wire resp_accept_w;
always @ *
begin
req_in_r = 6'b0;
// First cycle of read burst
if (axi_arvalid_i && axi_arready_o)
req_in_r = {1'b1, (axi_arlen_i == 8'd0), axi_arid_i};
// First cycle of write burst
else if (axi_awvalid_i && axi_awready_o)
req_in_r = {1'b0, (axi_awlen_i == 8'd0), axi_awid_i};
// In burst
else
req_in_r = {ram_rd_o, (req_len_q == 8'd0), req_id_q};
end
tcm_mem_pmem_fifo2
#( .WIDTH(1 + 1 + 4) )
u_requests
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input
.data_in_i(req_in_r),
.push_i(req_push_w),
.accept_o(req_fifo_accept_w),
// Output
.pop_i(resp_accept_w),
.data_out_o(req_out_w),
.valid_o(req_out_valid_w)
);
wire resp_is_write_w = req_out_valid_w ? ~req_out_w[5] : 1'b0;
wire resp_is_read_w = req_out_valid_w ? req_out_w[5] : 1'b0;
wire resp_is_last_w = req_out_w[4];
wire [3:0] resp_id_w = req_out_w[3:0];
//-----------------------------------------------------------------
// Response buffering
//-----------------------------------------------------------------
wire resp_valid_w;
tcm_mem_pmem_fifo2
#( .WIDTH(32) )
u_response
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input
.data_in_i(ram_read_data_i),
.push_i(ram_ack_i),
.accept_o(),
// Output
.pop_i(resp_accept_w),
.data_out_o(axi_rdata_o),
.valid_o(resp_valid_w)
);
//-----------------------------------------------------------------
// RAM Request
//-----------------------------------------------------------------
// Round robin priority between read and write
wire write_prio_w = ((req_prio_q & !req_hold_rd_q) | req_hold_wr_q);
wire read_prio_w = ((!req_prio_q & !req_hold_wr_q) | req_hold_rd_q);
wire write_active_w = (axi_awvalid_i || req_wr_q) && !req_rd_q && req_fifo_accept_w && (write_prio_w || req_wr_q || !axi_arvalid_i);
wire read_active_w = (axi_arvalid_i || req_rd_q) && !req_wr_q && req_fifo_accept_w && (read_prio_w || req_rd_q || !axi_awvalid_i);
assign axi_awready_o = write_active_w && !req_wr_q && ram_accept_i && req_fifo_accept_w;
assign axi_wready_o = write_active_w && ram_accept_i && req_fifo_accept_w;
assign axi_arready_o = read_active_w && !req_rd_q && ram_accept_i && req_fifo_accept_w;
wire [31:0] addr_w = ((req_wr_q || req_rd_q) ? req_addr_q:
write_active_w ? axi_awaddr_i : axi_araddr_i);
wire wr_w = write_active_w && axi_wvalid_i;
wire rd_w = read_active_w;
// RAM if
assign ram_addr_o = addr_w;
assign ram_write_data_o = axi_wdata_i;
assign ram_rd_o = rd_w;
assign ram_wr_o = wr_w ? axi_wstrb_i : 4'b0;
assign ram_len_o = axi_awvalid_i ? axi_awlen_i:
axi_arvalid_i ? axi_arlen_i : 8'b0;
//-----------------------------------------------------------------
// Response
//-----------------------------------------------------------------
assign axi_bvalid_o = resp_valid_w & resp_is_write_w & resp_is_last_w;
assign axi_bresp_o = 2'b0;
assign axi_bid_o = resp_id_w;
assign axi_rvalid_o = resp_valid_w & resp_is_read_w;
assign axi_rresp_o = 2'b0;
assign axi_rid_o = resp_id_w;
assign axi_rlast_o = resp_is_last_w;
assign resp_accept_w = (axi_rvalid_o & axi_rready_i) |
(axi_bvalid_o & axi_bready_i) |
(resp_valid_w & resp_is_write_w & !resp_is_last_w); // Ignore write resps mid burst
endmodule |
module tcm_mem_pmem_fifo2
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram [DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr;
reg [ADDR_W-1:0] wr_ptr;
reg [COUNT_W-1:0] count;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count <= {(COUNT_W) {1'b0}};
rd_ptr <= {(ADDR_W) {1'b0}};
wr_ptr <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram[wr_ptr] <= data_in_i;
wr_ptr <= wr_ptr + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr <= rd_ptr + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count <= count + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count <= count - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign accept_o = (count != DEPTH);
assign valid_o = (count != 0);
/* verilator lint_on WIDTH */
assign data_out_o = ram[rd_ptr];
endmodule |
module tcm_mem_ram
(
// Inputs
input clk0_i
,input rst0_i
,input [ 13:0] addr0_i
,input [ 31:0] data0_i
,input [ 3:0] wr0_i
,input clk1_i
,input rst1_i
,input [ 13:0] addr1_i
,input [ 31:0] data1_i
,input [ 3:0] wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 64KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [16383:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i[0])
ram[addr0_i][7:0] <= data0_i[7:0];
if (wr0_i[1])
ram[addr0_i][15:8] <= data0_i[15:8];
if (wr0_i[2])
ram[addr0_i][23:16] <= data0_i[23:16];
if (wr0_i[3])
ram[addr0_i][31:24] <= data0_i[31:24];
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i[0])
ram[addr1_i][7:0] <= data1_i[7:0];
if (wr1_i[1])
ram[addr1_i][15:8] <= data1_i[15:8];
if (wr1_i[2])
ram[addr1_i][23:16] <= data1_i[23:16];
if (wr1_i[3])
ram[addr1_i][31:24] <= data1_i[31:24];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule |
module tcm_mem
(
// Inputs
input clk_i
,input rst_i
,input mem_i_rd_i
,input mem_i_flush_i
,input mem_i_invalidate_i
,input [ 31:0] mem_i_pc_i
,input [ 31:0] mem_d_addr_i
,input [ 31:0] mem_d_data_wr_i
,input mem_d_rd_i
,input [ 3:0] mem_d_wr_i
,input mem_d_cacheable_i
,input [ 10:0] mem_d_req_tag_i
,input mem_d_invalidate_i
,input mem_d_writeback_i
,input mem_d_flush_i
,input axi_awvalid_i
,input [ 31:0] axi_awaddr_i
,input [ 3:0] axi_awid_i
,input [ 7:0] axi_awlen_i
,input [ 1:0] axi_awburst_i
,input axi_wvalid_i
,input [ 31:0] axi_wdata_i
,input [ 3:0] axi_wstrb_i
,input axi_wlast_i
,input axi_bready_i
,input axi_arvalid_i
,input [ 31:0] axi_araddr_i
,input [ 3:0] axi_arid_i
,input [ 7:0] axi_arlen_i
,input [ 1:0] axi_arburst_i
,input axi_rready_i
// Outputs
,output mem_i_accept_o
,output mem_i_valid_o
,output mem_i_error_o
,output [ 31:0] mem_i_inst_o
,output [ 31:0] mem_d_data_rd_o
,output mem_d_accept_o
,output mem_d_ack_o
,output mem_d_error_o
,output [ 10:0] mem_d_resp_tag_o
,output axi_awready_o
,output axi_wready_o
,output axi_bvalid_o
,output [ 1:0] axi_bresp_o
,output [ 3:0] axi_bid_o
,output axi_arready_o
,output axi_rvalid_o
,output [ 31:0] axi_rdata_o
,output [ 1:0] axi_rresp_o
,output [ 3:0] axi_rid_o
,output axi_rlast_o
);
//-------------------------------------------------------------
// AXI -> PMEM Interface
//-------------------------------------------------------------
wire ext_accept_w;
wire ext_ack_w;
wire [ 31:0] ext_read_data_w;
wire [ 3:0] ext_wr_w;
wire ext_rd_w;
wire [ 7:0] ext_len_w;
wire [ 31:0] ext_addr_w;
wire [ 31:0] ext_write_data_w;
tcm_mem_pmem
u_conv
(
// Inputs
.clk_i(clk_i),
.rst_i(rst_i),
.axi_awvalid_i(axi_awvalid_i),
.axi_awaddr_i(axi_awaddr_i),
.axi_awid_i(axi_awid_i),
.axi_awlen_i(axi_awlen_i),
.axi_awburst_i(axi_awburst_i),
.axi_wvalid_i(axi_wvalid_i),
.axi_wdata_i(axi_wdata_i),
.axi_wstrb_i(axi_wstrb_i),
.axi_wlast_i(axi_wlast_i),
.axi_bready_i(axi_bready_i),
.axi_arvalid_i(axi_arvalid_i),
.axi_araddr_i(axi_araddr_i),
.axi_arid_i(axi_arid_i),
.axi_arlen_i(axi_arlen_i),
.axi_arburst_i(axi_arburst_i),
.axi_rready_i(axi_rready_i),
.ram_accept_i(ext_accept_w),
.ram_ack_i(ext_ack_w),
.ram_error_i(1'b0),
.ram_read_data_i(ext_read_data_w),
// Outputs
.axi_awready_o(axi_awready_o),
.axi_wready_o(axi_wready_o),
.axi_bvalid_o(axi_bvalid_o),
.axi_bresp_o(axi_bresp_o),
.axi_bid_o(axi_bid_o),
.axi_arready_o(axi_arready_o),
.axi_rvalid_o(axi_rvalid_o),
.axi_rdata_o(axi_rdata_o),
.axi_rresp_o(axi_rresp_o),
.axi_rid_o(axi_rid_o),
.axi_rlast_o(axi_rlast_o),
.ram_wr_o(ext_wr_w),
.ram_rd_o(ext_rd_w),
.ram_len_o(ext_len_w),
.ram_addr_o(ext_addr_w),
.ram_write_data_o(ext_write_data_w)
);
//-------------------------------------------------------------
// Dual Port RAM
//-------------------------------------------------------------
// Mux access to the 2nd port between external access and CPU data access
wire [13:0] muxed_addr_w = ext_accept_w ? ext_addr_w[15:2] : mem_d_addr_i[15:2];
wire [31:0] muxed_data_w = ext_accept_w ? ext_write_data_w : mem_d_data_wr_i;
wire [3:0] muxed_wr_w = ext_accept_w ? ext_wr_w : mem_d_wr_i;
wire [31:0] data_r_w;
tcm_mem_ram
u_ram
(
// Instruction fetch
.clk0_i(clk_i)
,.rst0_i(rst_i)
,.addr0_i(mem_i_pc_i[15:2])
,.data0_i(32'b0)
,.wr0_i(4'b0)
// External access / Data access
,.clk1_i(clk_i)
,.rst1_i(rst_i)
,.addr1_i(muxed_addr_w)
,.data1_i(muxed_data_w)
,.wr1_i(muxed_wr_w)
// Outputs
,.data0_o(mem_i_inst_o)
,.data1_o(data_r_w)
);
assign ext_read_data_w = data_r_w;
//-------------------------------------------------------------
// Instruction Fetch
//-------------------------------------------------------------
reg mem_i_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_i_valid_q <= 1'b0;
else
mem_i_valid_q <= mem_i_rd_i;
assign mem_i_accept_o = 1'b1;
assign mem_i_valid_o = mem_i_valid_q;
assign mem_i_error_o = 1'b0;
//-------------------------------------------------------------
// Data Access / Incoming external access
//-------------------------------------------------------------
reg mem_d_accept_q;
reg [10:0] mem_d_tag_q;
reg mem_d_ack_q;
reg ext_ack_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_d_accept_q <= 1'b1;
// External request, do not accept internal requests in next cycle
else if (ext_rd_w || ext_wr_w != 4'b0)
mem_d_accept_q <= 1'b0;
else
mem_d_accept_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_d_ack_q <= 1'b0;
mem_d_tag_q <= 11'b0;
end
else if ((mem_d_rd_i || mem_d_wr_i != 4'b0 || mem_d_flush_i || mem_d_invalidate_i || mem_d_writeback_i) && mem_d_accept_o)
begin
mem_d_ack_q <= 1'b1;
mem_d_tag_q <= mem_d_req_tag_i;
end
else
mem_d_ack_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ext_ack_q <= 1'b0;
// External request accepted
else if ((ext_rd_w || ext_wr_w != 4'b0) && ext_accept_w)
ext_ack_q <= 1'b1;
else
ext_ack_q <= 1'b0;
assign mem_d_ack_o = mem_d_ack_q;
assign mem_d_resp_tag_o = mem_d_tag_q;
assign mem_d_data_rd_o = data_r_w;
assign mem_d_error_o = 1'b0;
assign mem_d_accept_o = mem_d_accept_q;
assign ext_accept_w = !mem_d_accept_q;
assign ext_ack_w = ext_ack_q;
`ifdef verilator
//-------------------------------------------------------------
// write: Write byte into memory
//-------------------------------------------------------------
function write; /*verilator public*/
input [31:0] addr;
input [7:0] data;
begin
case (addr[1:0])
2'd0: u_ram.ram[addr/4][7:0] = data;
2'd1: u_ram.ram[addr/4][15:8] = data;
2'd2: u_ram.ram[addr/4][23:16] = data;
2'd3: u_ram.ram[addr/4][31:24] = data;
endcase
end
endfunction
//-------------------------------------------------------------
// read: Read byte from memory
//-------------------------------------------------------------
function [7:0] read; /*verilator public*/
input [31:0] addr;
begin
case (addr[1:0])
2'd0: read = u_ram.ram[addr/4][7:0];
2'd1: read = u_ram.ram[addr/4][15:8];
2'd2: read = u_ram.ram[addr/4][23:16];
2'd3: read = u_ram.ram[addr/4][31:24];
endcase
end
endfunction
`endif
endmodule |
module dport_axi
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input [ 3:0] axi_bid_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
,input [ 3:0] axi_rid_i
,input axi_rlast_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output [ 3:0] axi_awid_o
,output [ 7:0] axi_awlen_o
,output [ 1:0] axi_awburst_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_wlast_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output [ 3:0] axi_arid_o
,output [ 7:0] axi_arlen_o
,output [ 1:0] axi_arburst_o
,output axi_rready_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire write_complete_w;
wire read_complete_w;
reg request_pending_q;
wire req_pop_w = read_complete_w | write_complete_w;
wire req_valid_w;
wire [69-1:0] req_w;
// Push on transaction and other FIFO not full
wire req_push_w = (mem_rd_i || mem_wr_i != 4'b0) && res_accept_w;
dport_axi_fifo
#(
.WIDTH(32+32+4+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = (mem_rd_i || mem_wr_i != 4'b0) && req_accept_w;
dport_axi_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
assign mem_ack_o = axi_bvalid_i || axi_rvalid_i;
assign mem_error_o = axi_bvalid_i ? (axi_bresp_i != 2'b0) : (axi_rresp_i != 2'b0);
wire request_in_progress_w = request_pending_q & !mem_ack_o;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
reg awvalid_inhibit_q;
reg wvalid_inhibit_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_inhibit_q <= 1'b0;
else if (axi_awvalid_o && axi_awready_i && axi_wvalid_o && !axi_wready_i)
awvalid_inhibit_q <= 1'b1;
else if (axi_wvalid_o && axi_wready_i)
awvalid_inhibit_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_inhibit_q <= 1'b0;
else if (axi_wvalid_o && axi_wready_i && axi_awvalid_o && !axi_awready_i)
wvalid_inhibit_q <= 1'b1;
else if (axi_awvalid_o && axi_awready_i)
wvalid_inhibit_q <= 1'b0;
assign axi_awvalid_o = req_is_write_w && !awvalid_inhibit_q;
assign axi_awaddr_o = {req_w[31:2], 2'b0};
assign axi_wvalid_o = req_is_write_w && !wvalid_inhibit_q;
assign axi_wdata_o = req_w[63:32];
assign axi_wstrb_o = req_w[67:64];
assign axi_awid_o = 4'd0;
assign axi_awlen_o = 8'b0;
assign axi_awburst_o = 2'b01;
assign axi_wlast_o = 1'b1;
assign axi_bready_o = 1'b1;
assign write_complete_w = (awvalid_inhibit_q || axi_awready_i) &&
(wvalid_inhibit_q || axi_wready_i) && req_is_write_w;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign axi_arvalid_o = req_is_read_w;
assign axi_araddr_o = {req_w[31:2], 2'b0};
assign axi_arid_o = 4'd0;
assign axi_arlen_o = 8'b0;
assign axi_arburst_o = 2'b01;
assign axi_rready_o = 1'b1;
assign mem_data_rd_o = axi_rdata_i;
assign read_complete_w = axi_arvalid_o && axi_arready_i;
//-------------------------------------------------------------
// Outstanding Request Tracking
//-------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (write_complete_w || read_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
endmodule |
module icache
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI_ID = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input req_rd_i
,input req_flush_i
,input req_invalidate_i
,input [ 31:0] req_pc_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input [ 3:0] axi_bid_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
,input [ 3:0] axi_rid_i
,input axi_rlast_i
// Outputs
,output req_accept_o
,output req_valid_o
,output req_error_o
,output [ 31:0] req_inst_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output [ 3:0] axi_awid_o
,output [ 7:0] axi_awlen_o
,output [ 1:0] axi_awburst_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_wlast_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output [ 3:0] axi_arid_o
,output [ 7:0] axi_arlen_o
,output [ 1:0] axi_arburst_o
,output axi_rready_o
);
//-----------------------------------------------------------------
// This cache instance is 2 way set associative.
// The total size is 16KB.
// The replacement policy is a limited pseudo random scheme
// (between lines, toggling on line thrashing).
//-----------------------------------------------------------------
// Number of ways
localparam ICACHE_NUM_WAYS = 2;
// Number of cache lines
localparam ICACHE_NUM_LINES = 256;
localparam ICACHE_LINE_ADDR_W = 8;
// Line size (e.g. 32-bytes)
localparam ICACHE_LINE_SIZE_W = 5;
localparam ICACHE_LINE_SIZE = 32;
localparam ICACHE_LINE_WORDS = 8;
// Request -> tag address mapping
localparam ICACHE_TAG_REQ_LINE_L = 5; // ICACHE_LINE_SIZE_W
localparam ICACHE_TAG_REQ_LINE_H = 12; // ICACHE_LINE_ADDR_W+ICACHE_LINE_SIZE_W-1
localparam ICACHE_TAG_REQ_LINE_W = 8; // ICACHE_LINE_ADDR_W
`define ICACHE_TAG_REQ_RNG ICACHE_TAG_REQ_LINE_H:ICACHE_TAG_REQ_LINE_L
// Tag fields
`define CACHE_TAG_ADDR_RNG 18:0
localparam CACHE_TAG_ADDR_BITS = 19;
localparam CACHE_TAG_VALID_BIT = CACHE_TAG_ADDR_BITS;
localparam CACHE_TAG_DATA_W = CACHE_TAG_VALID_BIT + 1;
// Tag compare bits
localparam ICACHE_TAG_CMP_ADDR_L = ICACHE_TAG_REQ_LINE_H + 1;
localparam ICACHE_TAG_CMP_ADDR_H = 32-1;
localparam ICACHE_TAG_CMP_ADDR_W = ICACHE_TAG_CMP_ADDR_H - ICACHE_TAG_CMP_ADDR_L + 1;
`define ICACHE_TAG_CMP_ADDR_RNG 31:13
// Address mapping example:
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// |--------------| | | | | | | | | | | | | | | | |
// +--------------------+ +--------------------+ +------------+
// | Tag address. | | Line address | Address
// | | | | within line
// | | | |
// | | | |- ICACHE_TAG_REQ_LINE_L
// | | |- ICACHE_TAG_REQ_LINE_H
// | |- ICACHE_TAG_CMP_ADDR_L
// |- ICACHE_TAG_CMP_ADDR_H
// Tag addressing and match value
wire [ICACHE_TAG_REQ_LINE_W-1:0] req_line_addr_w = req_pc_i[`ICACHE_TAG_REQ_RNG];
// Data addressing
localparam CACHE_DATA_ADDR_W = ICACHE_LINE_ADDR_W+ICACHE_LINE_SIZE_W-2;
wire [CACHE_DATA_ADDR_W-1:0] req_data_addr_w = req_pc_i[CACHE_DATA_ADDR_W+2-1:2];
//-----------------------------------------------------------------
// States
//-----------------------------------------------------------------
localparam STATE_W = 2;
localparam STATE_FLUSH = 2'd0;
localparam STATE_LOOKUP = 2'd1;
localparam STATE_REFILL = 2'd2;
localparam STATE_RELOOKUP = 2'd3;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// States
reg [STATE_W-1:0] next_state_r;
reg [STATE_W-1:0] state_q;
reg invalidate_q;
reg [0:0] replace_way_q;
//-----------------------------------------------------------------
// Lookup validation
//-----------------------------------------------------------------
reg lookup_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
lookup_valid_q <= 1'b0;
else if (req_rd_i && req_accept_o)
lookup_valid_q <= 1'b1;
else if (req_valid_o)
lookup_valid_q <= 1'b0;
//-----------------------------------------------------------------
// Lookup address
//-----------------------------------------------------------------
reg [31:0] lookup_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
lookup_addr_q <= 32'b0;
else if (req_rd_i && req_accept_o)
lookup_addr_q <= req_pc_i;
wire [ICACHE_TAG_CMP_ADDR_W-1:0] req_pc_tag_cmp_w = lookup_addr_q[`ICACHE_TAG_CMP_ADDR_RNG];
//-----------------------------------------------------------------
// TAG RAMS
//-----------------------------------------------------------------
reg [ICACHE_TAG_REQ_LINE_W-1:0] tag_addr_r;
// Tag RAM address
always @ *
begin
tag_addr_r = flush_addr_q;
// Cache flush
if (state_q == STATE_FLUSH)
tag_addr_r = flush_addr_q;
// Line refill
else if (state_q == STATE_REFILL || state_q == STATE_RELOOKUP)
tag_addr_r = lookup_addr_q[`ICACHE_TAG_REQ_RNG];
// Lookup
else
tag_addr_r = req_line_addr_w;
end
// Tag RAM write data
reg [CACHE_TAG_DATA_W-1:0] tag_data_in_r;
always @ *
begin
tag_data_in_r = {(CACHE_TAG_DATA_W){1'b0}};
// Cache flush
if (state_q == STATE_FLUSH)
tag_data_in_r = {(CACHE_TAG_DATA_W){1'b0}};
// Line refill
else if (state_q == STATE_REFILL)
begin
tag_data_in_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_r[`CACHE_TAG_ADDR_RNG] = lookup_addr_q[`ICACHE_TAG_CMP_ADDR_RNG];
end
end
// Tag RAM write enable (way 0)
reg tag0_write_r;
always @ *
begin
tag0_write_r = 1'b0;
// Cache flush
if (state_q == STATE_FLUSH)
tag0_write_r = 1'b1;
// Line refill
else if (state_q == STATE_REFILL)
tag0_write_r = axi_rvalid_i && axi_rlast_i && (replace_way_q == 0);
end
wire [CACHE_TAG_DATA_W-1:0] tag0_data_out_w;
icache_tag_ram
u_tag0
(
.clk_i(clk_i),
.rst_i(rst_i),
.addr_i(tag_addr_r),
.data_i(tag_data_in_r),
.wr_i(tag0_write_r),
.data_o(tag0_data_out_w)
);
wire tag0_valid_w = tag0_data_out_w[CACHE_TAG_VALID_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag0_addr_bits_w = tag0_data_out_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag0_hit_w = tag0_valid_w ? (tag0_addr_bits_w == req_pc_tag_cmp_w) : 1'b0;
// Tag RAM write enable (way 1)
reg tag1_write_r;
always @ *
begin
tag1_write_r = 1'b0;
// Cache flush
if (state_q == STATE_FLUSH)
tag1_write_r = 1'b1;
// Line refill
else if (state_q == STATE_REFILL)
tag1_write_r = axi_rvalid_i && axi_rlast_i && (replace_way_q == 1);
end
wire [CACHE_TAG_DATA_W-1:0] tag1_data_out_w;
icache_tag_ram
u_tag1
(
.clk_i(clk_i),
.rst_i(rst_i),
.addr_i(tag_addr_r),
.data_i(tag_data_in_r),
.wr_i(tag1_write_r),
.data_o(tag1_data_out_w)
);
wire tag1_valid_w = tag1_data_out_w[CACHE_TAG_VALID_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag1_addr_bits_w = tag1_data_out_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag1_hit_w = tag1_valid_w ? (tag1_addr_bits_w == req_pc_tag_cmp_w) : 1'b0;
wire tag_hit_any_w = 1'b0
| tag0_hit_w
| tag1_hit_w
;
//-----------------------------------------------------------------
// DATA RAMS
//-----------------------------------------------------------------
reg [CACHE_DATA_ADDR_W-1:0] data_addr_r;
reg [CACHE_DATA_ADDR_W-1:0] data_write_addr_q;
// Data RAM refill write address
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_write_addr_q <= {(CACHE_DATA_ADDR_W){1'b0}};
else if (state_q == STATE_LOOKUP && next_state_r == STATE_REFILL)
data_write_addr_q <= axi_araddr_o[CACHE_DATA_ADDR_W+2-1:2];
else if (state_q == STATE_REFILL && axi_rvalid_i)
data_write_addr_q <= data_write_addr_q + 1;
// Data RAM address
always @ *
begin
data_addr_r = req_data_addr_w;
// Line refill
if (state_q == STATE_REFILL)
data_addr_r = data_write_addr_q;
// Lookup after refill
else if (state_q == STATE_RELOOKUP)
data_addr_r = lookup_addr_q[CACHE_DATA_ADDR_W+2-1:2];
// Lookup
else
data_addr_r = req_data_addr_w;
end
// Data RAM write enable (way 0)
reg data0_write_r;
always @ *
begin
data0_write_r = axi_rvalid_i && replace_way_q == 0;
end
wire [31:0] data0_data_out_w;
icache_data_ram
u_data0
(
.clk_i(clk_i),
.rst_i(rst_i),
.addr_i(data_addr_r),
.data_i(axi_rdata_i),
.wr_i(data0_write_r),
.data_o(data0_data_out_w)
);
// Data RAM write enable (way 1)
reg data1_write_r;
always @ *
begin
data1_write_r = axi_rvalid_i && replace_way_q == 1;
end
wire [31:0] data1_data_out_w;
icache_data_ram
u_data1
(
.clk_i(clk_i),
.rst_i(rst_i),
.addr_i(data_addr_r),
.data_i(axi_rdata_i),
.wr_i(data1_write_r),
.data_o(data1_data_out_w)
);
//-----------------------------------------------------------------
// Flush counter
//-----------------------------------------------------------------
reg [ICACHE_TAG_REQ_LINE_W-1:0] flush_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flush_addr_q <= {(ICACHE_TAG_REQ_LINE_W){1'b0}};
else if (state_q == STATE_FLUSH)
flush_addr_q <= flush_addr_q + 1;
// Invalidate specified line
else if (req_invalidate_i && req_accept_o)
flush_addr_q <= req_line_addr_w;
else
flush_addr_q <= {(ICACHE_TAG_REQ_LINE_W){1'b0}};
//-----------------------------------------------------------------
// Replacement Policy
//-----------------------------------------------------------------
// Using random replacement policy - this way we cycle through the ways
// when needing to replace a line.
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
replace_way_q <= 0;
else if (axi_rvalid_i && axi_rlast_i)
replace_way_q <= replace_way_q + 1;
//-----------------------------------------------------------------
// Instruction Output
//-----------------------------------------------------------------
assign req_valid_o = lookup_valid_q && ((state_q == STATE_LOOKUP) ? tag_hit_any_w : 1'b0);
// Data output mux
reg [31:0] inst_r;
always @ *
begin
inst_r = data0_data_out_w;
case (1'b1)
tag0_hit_w: inst_r = data0_data_out_w;
tag1_hit_w: inst_r = data1_data_out_w;
endcase
end
assign req_inst_o = inst_r;
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// STATE_FLUSH
//-----------------------------------------
STATE_FLUSH :
begin
if (invalidate_q)
next_state_r = STATE_LOOKUP;
else if (flush_addr_q == {(ICACHE_TAG_REQ_LINE_W){1'b1}})
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_LOOKUP
//-----------------------------------------
STATE_LOOKUP :
begin
// Tried a lookup but no match found
if (lookup_valid_q && !tag_hit_any_w)
next_state_r = STATE_REFILL;
// Invalidate a line / flush cache
else if (req_invalidate_i || req_flush_i)
next_state_r = STATE_FLUSH;
end
//-----------------------------------------
// STATE_REFILL
//-----------------------------------------
STATE_REFILL :
begin
// End of refill
if (axi_rvalid_i && axi_rlast_i)
next_state_r = STATE_RELOOKUP;
end
//-----------------------------------------
// STATE_RELOOKUP
//-----------------------------------------
STATE_RELOOKUP :
begin
next_state_r = STATE_LOOKUP;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_FLUSH;
else
state_q <= next_state_r;
assign req_accept_o = (state_q == STATE_LOOKUP && next_state_r != STATE_REFILL);
//-----------------------------------------------------------------
// Invalidate
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
invalidate_q <= 1'b0;
else if (req_invalidate_i && req_accept_o)
invalidate_q <= 1'b1;
else
invalidate_q <= 1'b0;
//-----------------------------------------------------------------
// AXI Request Hold
//-----------------------------------------------------------------
reg axi_arvalid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
axi_arvalid_q <= 1'b0;
else if (axi_arvalid_o && !axi_arready_i)
axi_arvalid_q <= 1'b1;
else
axi_arvalid_q <= 1'b0;
//-----------------------------------------------------------------
// AXI Error Handling
//-----------------------------------------------------------------
reg axi_error_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
axi_error_q <= 1'b0;
else if (axi_rvalid_i && axi_rready_o && axi_rresp_i != 2'b0)
axi_error_q <= 1'b1;
else if (req_valid_o)
axi_error_q <= 1'b0;
assign req_error_o = axi_error_q;
//-----------------------------------------------------------------
// AXI
//-----------------------------------------------------------------
// AXI Write channel (unused)
assign axi_awvalid_o = 1'b0;
assign axi_awaddr_o = 32'b0;
assign axi_awid_o = 4'b0;
assign axi_awlen_o = 8'b0;
assign axi_awburst_o = 2'b0;
assign axi_wvalid_o = 1'b0;
assign axi_wdata_o = 32'b0;
assign axi_wstrb_o = 4'b0;
assign axi_wlast_o = 1'b0;
assign axi_bready_o = 1'b0;
// AXI Read channel
assign axi_arvalid_o = (state_q == STATE_LOOKUP && next_state_r == STATE_REFILL) || axi_arvalid_q;
assign axi_araddr_o = {lookup_addr_q[31:ICACHE_LINE_SIZE_W], {(ICACHE_LINE_SIZE_W){1'b0}}};
assign axi_arburst_o = 2'd1; // INCR
assign axi_arid_o = AXI_ID;
assign axi_arlen_o = 8'd7;
assign axi_rready_o = 1'b1;
endmodule |
module dcache_pmem_mux
(
// Inputs
input clk_i
,input rst_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
,input select_i
,input [ 3:0] inport0_wr_i
,input inport0_rd_i
,input [ 7:0] inport0_len_i
,input [ 31:0] inport0_addr_i
,input [ 31:0] inport0_write_data_i
,input [ 3:0] inport1_wr_i
,input inport1_rd_i
,input [ 7:0] inport1_len_i
,input [ 31:0] inport1_addr_i
,input [ 31:0] inport1_write_data_i
// Outputs
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
,output inport0_accept_o
,output inport0_ack_o
,output inport0_error_o
,output [ 31:0] inport0_read_data_o
,output inport1_accept_o
,output inport1_ack_o
,output inport1_error_o
,output [ 31:0] inport1_read_data_o
);
//-----------------------------------------------------------------
// Output Mux
//-----------------------------------------------------------------
reg [ 3:0] outport_wr_r;
reg outport_rd_r;
reg [ 7:0] outport_len_r;
reg [ 31:0] outport_addr_r;
reg [ 31:0] outport_write_data_r;
reg select_q;
always @ *
begin
case (select_i)
1'd1:
begin
outport_wr_r = inport1_wr_i;
outport_rd_r = inport1_rd_i;
outport_len_r = inport1_len_i;
outport_addr_r = inport1_addr_i;
outport_write_data_r = inport1_write_data_i;
end
default:
begin
outport_wr_r = inport0_wr_i;
outport_rd_r = inport0_rd_i;
outport_len_r = inport0_len_i;
outport_addr_r = inport0_addr_i;
outport_write_data_r = inport0_write_data_i;
end
endcase
end
assign outport_wr_o = outport_wr_r;
assign outport_rd_o = outport_rd_r;
assign outport_len_o = outport_len_r;
assign outport_addr_o = outport_addr_r;
assign outport_write_data_o = outport_write_data_r;
// Delayed version of selector to match phase of response signals
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
select_q <= 1'b0;
else
select_q <= select_i;
assign inport0_ack_o = (select_q == 1'd0) && outport_ack_i;
assign inport0_error_o = (select_q == 1'd0) && outport_error_i;
assign inport0_read_data_o = outport_read_data_i;
assign inport0_accept_o = (select_i == 1'd0) && outport_accept_i;
assign inport1_ack_o = (select_q == 1'd1) && outport_ack_i;
assign inport1_error_o = (select_q == 1'd1) && outport_error_i;
assign inport1_read_data_o = outport_read_data_i;
assign inport1_accept_o = (select_i == 1'd1) && outport_accept_i;
endmodule |
module icache_tag_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 7:0] addr_i
,input [ 19:0] data_i
,input wr_i
// Outputs
,output [ 19:0] data_o
);
//-----------------------------------------------------------------
// Single Port RAM 0KB
// Mode: Read First
//-----------------------------------------------------------------
reg [19:0] ram [255:0] /*verilator public*/;
reg [19:0] ram_read_q;
// Synchronous write
always @ (posedge clk_i)
begin
if (wr_i)
ram[addr_i] <= data_i;
ram_read_q <= ram[addr_i];
end
assign data_o = ram_read_q;
endmodule |
module dcache_if_pmem
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dcache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire request_complete_w;
wire req_pop_w = request_complete_w;
wire req_valid_w;
wire [70-1:0] req_w;
// Cache requests are dropped
// NOTE: Should not actually end up here if configured correctly.
wire drop_req_w = mem_invalidate_i || mem_writeback_i || mem_flush_i;
wire request_w = drop_req_w || mem_rd_i || mem_wr_i != 4'b0;
// Push on transaction and other FIFO not full
wire req_push_w = request_w && res_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(32+32+4+1+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({drop_req_w, mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = request_w && req_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
//-------------------------------------------------------------
// Request
//-------------------------------------------------------------
reg request_pending_q;
wire request_in_progress_w = request_pending_q & !mem_ack_o;
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
wire req_is_drop_w = ((req_valid_w & !request_in_progress_w) ? req_w[69] : 1'b0);
assign outport_wr_o = req_is_write_w ? req_w[67:64] : 4'b0;
assign outport_rd_o = req_is_read_w;
assign outport_len_o = 8'd0;
assign outport_addr_o = {req_w[31:2], 2'b0};
assign outport_write_data_o = req_w[63:32];
assign request_complete_w = req_is_drop_w || ((outport_rd_o || outport_wr_o != 4'b0) && outport_accept_i);
// Outstanding Request Tracking
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (request_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
//-------------------------------------------------------------
// Response
//-------------------------------------------------------------
reg dropped_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
dropped_q <= 1'b0;
else if (req_is_drop_w)
dropped_q <= 1'b1;
else
dropped_q <= 1'b0;
assign mem_ack_o = dropped_q || outport_ack_i;
assign mem_data_rd_o = outport_read_data_i;
assign mem_error_o = outport_error_i;
endmodule |
module dcache_core
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
);
//-----------------------------------------------------------------
// This cache instance is 2 way set associative.
// The total size is 16KB.
// The replacement policy is a limited pseudo random scheme
// (between lines, toggling on line thrashing).
// The cache is a write back cache, with allocate on read and write.
//-----------------------------------------------------------------
// Number of ways
localparam DCACHE_NUM_WAYS = 2;
// Number of cache lines
localparam DCACHE_NUM_LINES = 256;
localparam DCACHE_LINE_ADDR_W = 8;
// Line size (e.g. 32-bytes)
localparam DCACHE_LINE_SIZE_W = 5;
localparam DCACHE_LINE_SIZE = 32;
localparam DCACHE_LINE_WORDS = 8;
// Request -> tag address mapping
localparam DCACHE_TAG_REQ_LINE_L = 5; // DCACHE_LINE_SIZE_W
localparam DCACHE_TAG_REQ_LINE_H = 12; // DCACHE_LINE_ADDR_W+DCACHE_LINE_SIZE_W-1
localparam DCACHE_TAG_REQ_LINE_W = 8; // DCACHE_LINE_ADDR_W
`define DCACHE_TAG_REQ_RNG DCACHE_TAG_REQ_LINE_H:DCACHE_TAG_REQ_LINE_L
// Tag fields
`define CACHE_TAG_ADDR_RNG 18:0
localparam CACHE_TAG_ADDR_BITS = 19;
localparam CACHE_TAG_DIRTY_BIT = CACHE_TAG_ADDR_BITS + 0;
localparam CACHE_TAG_VALID_BIT = CACHE_TAG_ADDR_BITS + 1;
localparam CACHE_TAG_DATA_W = CACHE_TAG_ADDR_BITS + 2;
// Tag compare bits
localparam DCACHE_TAG_CMP_ADDR_L = DCACHE_TAG_REQ_LINE_H + 1;
localparam DCACHE_TAG_CMP_ADDR_H = 32-1;
localparam DCACHE_TAG_CMP_ADDR_W = DCACHE_TAG_CMP_ADDR_H - DCACHE_TAG_CMP_ADDR_L + 1;
`define DCACHE_TAG_CMP_ADDR_RNG 31:13
// Address mapping example:
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// |--------------| | | | | | | | | | | | | | | | |
// +--------------------+ +--------------------+ +------------+
// | Tag address. | | Line address | Address
// | | | | within line
// | | | |
// | | | |- DCACHE_TAG_REQ_LINE_L
// | | |- DCACHE_TAG_REQ_LINE_H
// | |- DCACHE_TAG_CMP_ADDR_L
// |- DCACHE_TAG_CMP_ADDR_H
//-----------------------------------------------------------------
// States
//-----------------------------------------------------------------
localparam STATE_W = 4;
localparam STATE_RESET = 4'd0;
localparam STATE_FLUSH_ADDR = 4'd1;
localparam STATE_FLUSH = 4'd2;
localparam STATE_LOOKUP = 4'd3;
localparam STATE_READ = 4'd4;
localparam STATE_WRITE = 4'd5;
localparam STATE_REFILL = 4'd6;
localparam STATE_EVICT = 4'd7;
localparam STATE_EVICT_WAIT = 4'd8;
localparam STATE_INVALIDATE = 4'd9;
localparam STATE_WRITEBACK = 4'd10;
// States
reg [STATE_W-1:0] next_state_r;
reg [STATE_W-1:0] state_q;
//-----------------------------------------------------------------
// Request buffer
//-----------------------------------------------------------------
reg [31:0] mem_addr_m_q;
reg [31:0] mem_data_m_q;
reg [3:0] mem_wr_m_q;
reg mem_rd_m_q;
reg [10:0] mem_tag_m_q;
reg mem_inval_m_q;
reg mem_writeback_m_q;
reg mem_flush_m_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_addr_m_q <= 32'b0;
mem_data_m_q <= 32'b0;
mem_wr_m_q <= 4'b0;
mem_rd_m_q <= 1'b0;
mem_tag_m_q <= 11'b0;
mem_inval_m_q <= 1'b0;
mem_writeback_m_q <= 1'b0;
mem_flush_m_q <= 1'b0;
end
else if (mem_accept_o)
begin
mem_addr_m_q <= mem_addr_i;
mem_data_m_q <= mem_data_wr_i;
mem_wr_m_q <= mem_wr_i;
mem_rd_m_q <= mem_rd_i;
mem_tag_m_q <= mem_req_tag_i;
mem_inval_m_q <= mem_invalidate_i;
mem_writeback_m_q <= mem_writeback_i;
mem_flush_m_q <= mem_flush_i;
end
else if (mem_ack_o)
begin
mem_addr_m_q <= 32'b0;
mem_data_m_q <= 32'b0;
mem_wr_m_q <= 4'b0;
mem_rd_m_q <= 1'b0;
mem_tag_m_q <= 11'b0;
mem_inval_m_q <= 1'b0;
mem_writeback_m_q <= 1'b0;
mem_flush_m_q <= 1'b0;
end
reg mem_accept_r;
always @ *
begin
mem_accept_r = 1'b0;
if (state_q == STATE_LOOKUP)
begin
// Previous access missed - do not accept new requests
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && !tag_hit_any_m_w)
mem_accept_r = 1'b0;
// Write followed by read - detect writes to the same line, or addresses which alias in tag lookups
else if ((|mem_wr_m_q) && mem_rd_i && mem_addr_i[31:2] == mem_addr_m_q[31:2])
mem_accept_r = 1'b0;
else
mem_accept_r = 1'b1;
end
end
assign mem_accept_o = mem_accept_r;
// Tag comparison address
wire [DCACHE_TAG_CMP_ADDR_W-1:0] req_addr_tag_cmp_m_w = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
assign mem_resp_tag_o = mem_tag_m_q;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [0:0] replace_way_q;
wire [ 3:0] pmem_wr_w;
wire pmem_rd_w;
wire [ 7:0] pmem_len_w;
wire pmem_last_w;
wire [ 31:0] pmem_addr_w;
wire [ 31:0] pmem_write_data_w;
wire pmem_accept_w;
wire pmem_ack_w;
wire pmem_error_w;
wire [ 31:0] pmem_read_data_w;
wire evict_way_w;
wire tag_dirty_any_m_w;
wire tag_hit_and_dirty_m_w;
reg flushing_q;
//-----------------------------------------------------------------
// TAG RAMS
//-----------------------------------------------------------------
reg [DCACHE_TAG_REQ_LINE_W-1:0] tag_addr_x_r;
reg [DCACHE_TAG_REQ_LINE_W-1:0] tag_addr_m_r;
// Tag RAM address
always @ *
begin
// Read Port
tag_addr_x_r = mem_addr_i[`DCACHE_TAG_REQ_RNG];
// Lookup
if (state_q == STATE_LOOKUP && (next_state_r == STATE_LOOKUP || next_state_r == STATE_WRITEBACK))
tag_addr_x_r = mem_addr_i[`DCACHE_TAG_REQ_RNG];
// Cache flush
else if (flushing_q)
tag_addr_x_r = flush_addr_q;
else
tag_addr_x_r = mem_addr_m_q[`DCACHE_TAG_REQ_RNG];
// Write Port
tag_addr_m_r = flush_addr_q;
// Cache flush
if (flushing_q || state_q == STATE_RESET)
tag_addr_m_r = flush_addr_q;
// Line refill / write
else
tag_addr_m_r = mem_addr_m_q[`DCACHE_TAG_REQ_RNG];
end
// Tag RAM write data
reg [CACHE_TAG_DATA_W-1:0] tag_data_in_m_r;
always @ *
begin
tag_data_in_m_r = {(CACHE_TAG_DATA_W){1'b0}};
// Cache flush
if (state_q == STATE_FLUSH || state_q == STATE_RESET || flushing_q)
tag_data_in_m_r = {(CACHE_TAG_DATA_W){1'b0}};
// Line refill
else if (state_q == STATE_REFILL)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Invalidate - mark entry (if matching line) not valid (even if dirty...)
else if (state_q == STATE_INVALIDATE)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b0;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Evict completion
else if (state_q == STATE_EVICT_WAIT)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Write - mark entry as dirty
else if (state_q == STATE_WRITE || (state_q == STATE_LOOKUP && (|mem_wr_m_q)))
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b1;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
end
// Tag RAM write enable (way 0)
reg tag0_write_m_r;
always @ *
begin
tag0_write_m_r = 1'b0;
// Cache flush (reset)
if (state_q == STATE_RESET)
tag0_write_m_r = 1'b1;
// Cache flush
else if (state_q == STATE_FLUSH)
tag0_write_m_r = !tag_dirty_any_m_w;
// Write - hit, mark as dirty
else if (state_q == STATE_LOOKUP && (|mem_wr_m_q))
tag0_write_m_r = tag0_hit_m_w;
// Write - write after refill
else if (state_q == STATE_WRITE)
tag0_write_m_r = (replace_way_q == 0);
// Write - mark entry as dirty
else if (state_q == STATE_EVICT_WAIT && pmem_ack_w)
tag0_write_m_r = (replace_way_q == 0);
// Line refill
else if (state_q == STATE_REFILL)
tag0_write_m_r = pmem_ack_w && pmem_last_w && (replace_way_q == 0);
// Invalidate - line matches address - invalidate
else if (state_q == STATE_INVALIDATE)
tag0_write_m_r = tag0_hit_m_w;
end
wire [CACHE_TAG_DATA_W-1:0] tag0_data_out_m_w;
dcache_core_tag_ram
u_tag0
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(tag_addr_x_r),
.data0_o(tag0_data_out_m_w),
// Write
.addr1_i(tag_addr_m_r),
.data1_i(tag_data_in_m_r),
.wr1_i(tag0_write_m_r)
);
wire tag0_valid_m_w = tag0_data_out_m_w[CACHE_TAG_VALID_BIT];
wire tag0_dirty_m_w = tag0_data_out_m_w[CACHE_TAG_DIRTY_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag0_addr_bits_m_w = tag0_data_out_m_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag0_hit_m_w = tag0_valid_m_w ? (tag0_addr_bits_m_w == req_addr_tag_cmp_m_w) : 1'b0;
// Tag RAM write enable (way 1)
reg tag1_write_m_r;
always @ *
begin
tag1_write_m_r = 1'b0;
// Cache flush (reset)
if (state_q == STATE_RESET)
tag1_write_m_r = 1'b1;
// Cache flush
else if (state_q == STATE_FLUSH)
tag1_write_m_r = !tag_dirty_any_m_w;
// Write - hit, mark as dirty
else if (state_q == STATE_LOOKUP && (|mem_wr_m_q))
tag1_write_m_r = tag1_hit_m_w;
// Write - write after refill
else if (state_q == STATE_WRITE)
tag1_write_m_r = (replace_way_q == 1);
// Write - mark entry as dirty
else if (state_q == STATE_EVICT_WAIT && pmem_ack_w)
tag1_write_m_r = (replace_way_q == 1);
// Line refill
else if (state_q == STATE_REFILL)
tag1_write_m_r = pmem_ack_w && pmem_last_w && (replace_way_q == 1);
// Invalidate - line matches address - invalidate
else if (state_q == STATE_INVALIDATE)
tag1_write_m_r = tag1_hit_m_w;
end
wire [CACHE_TAG_DATA_W-1:0] tag1_data_out_m_w;
dcache_core_tag_ram
u_tag1
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(tag_addr_x_r),
.data0_o(tag1_data_out_m_w),
// Write
.addr1_i(tag_addr_m_r),
.data1_i(tag_data_in_m_r),
.wr1_i(tag1_write_m_r)
);
wire tag1_valid_m_w = tag1_data_out_m_w[CACHE_TAG_VALID_BIT];
wire tag1_dirty_m_w = tag1_data_out_m_w[CACHE_TAG_DIRTY_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag1_addr_bits_m_w = tag1_data_out_m_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag1_hit_m_w = tag1_valid_m_w ? (tag1_addr_bits_m_w == req_addr_tag_cmp_m_w) : 1'b0;
wire tag_hit_any_m_w = 1'b0
| tag0_hit_m_w
| tag1_hit_m_w
;
assign tag_hit_and_dirty_m_w = 1'b0
| (tag0_hit_m_w & tag0_dirty_m_w)
| (tag1_hit_m_w & tag1_dirty_m_w)
;
assign tag_dirty_any_m_w = 1'b0
| (tag0_valid_m_w & tag0_dirty_m_w)
| (tag1_valid_m_w & tag1_dirty_m_w)
;
localparam EVICT_ADDR_W = 32 - DCACHE_LINE_SIZE_W;
reg evict_way_r;
reg [31:0] evict_data_r;
reg [EVICT_ADDR_W-1:0] evict_addr_r;
always @ *
begin
evict_way_r = 1'b0;
evict_addr_r = flushing_q ? {tag0_addr_bits_m_w, flush_addr_q} :
{tag0_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data0_data_out_m_w;
case (replace_way_q)
1'd0:
begin
evict_way_r = tag0_valid_m_w && tag0_dirty_m_w;
evict_addr_r = flushing_q ? {tag0_addr_bits_m_w, flush_addr_q} :
{tag0_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data0_data_out_m_w;
end
1'd1:
begin
evict_way_r = tag1_valid_m_w && tag1_dirty_m_w;
evict_addr_r = flushing_q ? {tag1_addr_bits_m_w, flush_addr_q} :
{tag1_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data1_data_out_m_w;
end
endcase
end
assign evict_way_w = (flushing_q || !tag_hit_any_m_w) && evict_way_r;
wire [EVICT_ADDR_W-1:0] evict_addr_w = evict_addr_r;
wire [31:0] evict_data_w = evict_data_r;
//-----------------------------------------------------------------
// DATA RAMS
//-----------------------------------------------------------------
// Data addressing
localparam CACHE_DATA_ADDR_W = DCACHE_LINE_ADDR_W+DCACHE_LINE_SIZE_W-2;
reg [CACHE_DATA_ADDR_W-1:0] data_addr_x_r;
reg [CACHE_DATA_ADDR_W-1:0] data_addr_m_r;
reg [CACHE_DATA_ADDR_W-1:0] data_write_addr_q;
// Data RAM refill write address
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_write_addr_q <= {(CACHE_DATA_ADDR_W){1'b0}};
else if (state_q != STATE_REFILL && next_state_r == STATE_REFILL)
data_write_addr_q <= pmem_addr_w[CACHE_DATA_ADDR_W+2-1:2];
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
data_write_addr_q <= data_addr_m_r + 1;
else if (state_q == STATE_REFILL && pmem_ack_w)
data_write_addr_q <= data_write_addr_q + 1;
else if (state_q == STATE_EVICT && pmem_accept_w)
data_write_addr_q <= data_write_addr_q + 1;
// Data RAM address
always @ *
begin
data_addr_x_r = mem_addr_i[CACHE_DATA_ADDR_W+2-1:2];
data_addr_m_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
// Line refill / evict
if (state_q == STATE_REFILL || state_q == STATE_EVICT)
begin
data_addr_x_r = data_write_addr_q;
data_addr_m_r = data_addr_x_r;
end
else if (state_q == STATE_FLUSH || state_q == STATE_RESET)
begin
data_addr_x_r = {flush_addr_q, {(DCACHE_LINE_SIZE_W-2){1'b0}}};
data_addr_m_r = data_addr_x_r;
end
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
begin
data_addr_x_r = {mem_addr_m_q[`DCACHE_TAG_REQ_RNG], {(DCACHE_LINE_SIZE_W-2){1'b0}}};
data_addr_m_r = data_addr_x_r;
end
// Lookup post refill
else if (state_q == STATE_READ)
begin
data_addr_x_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
end
// Possible line update on write
else
data_addr_m_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
end
// Data RAM write enable (way 0)
reg [3:0] data0_write_m_r;
always @ *
begin
data0_write_m_r = 4'b0;
if (state_q == STATE_REFILL)
data0_write_m_r = (pmem_ack_w && replace_way_q == 0) ? 4'b1111 : 4'b0000;
else if (state_q == STATE_WRITE || state_q == STATE_LOOKUP)
data0_write_m_r = mem_wr_m_q & {4{tag0_hit_m_w}};
end
wire [31:0] data0_data_out_m_w;
wire [31:0] data0_data_in_m_w = (state_q == STATE_REFILL) ? pmem_read_data_w : mem_data_m_q;
dcache_core_data_ram
u_data0
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(data_addr_x_r),
.data0_i(32'b0),
.wr0_i(4'b0),
.data0_o(data0_data_out_m_w),
// Write
.addr1_i(data_addr_m_r),
.data1_i(data0_data_in_m_w),
.wr1_i(data0_write_m_r),
.data1_o()
);
// Data RAM write enable (way 1)
reg [3:0] data1_write_m_r;
always @ *
begin
data1_write_m_r = 4'b0;
if (state_q == STATE_REFILL)
data1_write_m_r = (pmem_ack_w && replace_way_q == 1) ? 4'b1111 : 4'b0000;
else if (state_q == STATE_WRITE || state_q == STATE_LOOKUP)
data1_write_m_r = mem_wr_m_q & {4{tag1_hit_m_w}};
end
wire [31:0] data1_data_out_m_w;
wire [31:0] data1_data_in_m_w = (state_q == STATE_REFILL) ? pmem_read_data_w : mem_data_m_q;
dcache_core_data_ram
u_data1
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(data_addr_x_r),
.data0_i(32'b0),
.wr0_i(4'b0),
.data0_o(data1_data_out_m_w),
// Write
.addr1_i(data_addr_m_r),
.data1_i(data1_data_in_m_w),
.wr1_i(data1_write_m_r),
.data1_o()
);
//-----------------------------------------------------------------
// Flush counter
//-----------------------------------------------------------------
reg [DCACHE_TAG_REQ_LINE_W-1:0] flush_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flush_addr_q <= {(DCACHE_TAG_REQ_LINE_W){1'b0}};
else if ((state_q == STATE_RESET) || (state_q == STATE_FLUSH && next_state_r == STATE_FLUSH_ADDR))
flush_addr_q <= flush_addr_q + 1;
else if (state_q == STATE_LOOKUP)
flush_addr_q <= {(DCACHE_TAG_REQ_LINE_W){1'b0}};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flushing_q <= 1'b0;
else if (state_q == STATE_LOOKUP && next_state_r == STATE_FLUSH_ADDR)
flushing_q <= 1'b1;
else if (state_q == STATE_FLUSH && next_state_r == STATE_LOOKUP)
flushing_q <= 1'b0;
reg flush_last_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flush_last_q <= 1'b0;
else if (state_q == STATE_LOOKUP)
flush_last_q <= 1'b0;
else if (flush_addr_q == {(DCACHE_TAG_REQ_LINE_W){1'b1}})
flush_last_q <= 1'b1;
//-----------------------------------------------------------------
// Replacement Policy
//-----------------------------------------------------------------
// Using random replacement policy - this way we cycle through the ways
// when needing to replace a line.
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
replace_way_q <= 0;
else if (state_q == STATE_WRITE || state_q == STATE_READ)
replace_way_q <= replace_way_q + 1;
else if (flushing_q && tag_dirty_any_m_w && !evict_way_w && state_q != STATE_FLUSH_ADDR)
replace_way_q <= replace_way_q + 1;
else if (state_q == STATE_EVICT_WAIT && next_state_r == STATE_FLUSH_ADDR)
replace_way_q <= 0;
else if (state_q == STATE_FLUSH && next_state_r == STATE_LOOKUP)
replace_way_q <= 0;
else if (state_q == STATE_LOOKUP && next_state_r == STATE_FLUSH_ADDR)
replace_way_q <= 0;
else if (state_q == STATE_WRITEBACK)
begin
case (1'b1)
tag0_hit_m_w: replace_way_q <= 0;
tag1_hit_m_w: replace_way_q <= 1;
endcase
end
//-----------------------------------------------------------------
// Output Result
//-----------------------------------------------------------------
// Data output mux
reg [31:0] data_r;
always @ *
begin
data_r = data0_data_out_m_w;
case (1'b1)
tag0_hit_m_w: data_r = data0_data_out_m_w;
tag1_hit_m_w: data_r = data1_data_out_m_w;
endcase
end
assign mem_data_rd_o = data_r;
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// STATE_RESET
//-----------------------------------------
STATE_RESET :
begin
// Final line checked
if (flush_last_q)
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_FLUSH_ADDR
//-----------------------------------------
STATE_FLUSH_ADDR : next_state_r = STATE_FLUSH;
//-----------------------------------------
// STATE_FLUSH
//-----------------------------------------
STATE_FLUSH :
begin
// Dirty line detected - evict unless initial cache reset cycle
if (tag_dirty_any_m_w)
begin
// Evict dirty line - else wait for dirty way to be selected
if (evict_way_w)
next_state_r = STATE_EVICT;
end
// Final line checked, nothing dirty
else if (flush_last_q)
next_state_r = STATE_LOOKUP;
else
next_state_r = STATE_FLUSH_ADDR;
end
//-----------------------------------------
// STATE_LOOKUP
//-----------------------------------------
STATE_LOOKUP :
begin
// Previous access missed in the cache
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && !tag_hit_any_m_w)
begin
// Evict dirty line first
if (evict_way_w)
next_state_r = STATE_EVICT;
// Allocate line and fill
else
next_state_r = STATE_REFILL;
end
// Writeback a single line
else if (mem_writeback_i && mem_accept_o)
next_state_r = STATE_WRITEBACK;
// Flush whole cache
else if (mem_flush_i && mem_accept_o)
next_state_r = STATE_FLUSH_ADDR;
// Invalidate line (even if dirty)
else if (mem_invalidate_i && mem_accept_o)
next_state_r = STATE_INVALIDATE;
end
//-----------------------------------------
// STATE_REFILL
//-----------------------------------------
STATE_REFILL :
begin
// End of refill
if (pmem_ack_w && pmem_last_w)
begin
// Refill reason was write
if (mem_wr_m_q != 4'b0)
next_state_r = STATE_WRITE;
// Refill reason was read
else
next_state_r = STATE_READ;
end
end
//-----------------------------------------
// STATE_WRITE/READ
//-----------------------------------------
STATE_WRITE, STATE_READ :
begin
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_EVICT
//-----------------------------------------
STATE_EVICT :
begin
// End of evict, wait for write completion
if (pmem_accept_w && pmem_last_w)
next_state_r = STATE_EVICT_WAIT;
end
//-----------------------------------------
// STATE_EVICT_WAIT
//-----------------------------------------
STATE_EVICT_WAIT :
begin
// Single line writeback
if (pmem_ack_w && mem_writeback_m_q)
next_state_r = STATE_LOOKUP;
// Evict due to flush
else if (pmem_ack_w && flushing_q)
next_state_r = STATE_FLUSH_ADDR;
// Write ack, start re-fill now
else if (pmem_ack_w)
next_state_r = STATE_REFILL;
end
//-----------------------------------------
// STATE_WRITEBACK: Writeback a cache line
//-----------------------------------------
STATE_WRITEBACK:
begin
// Line is dirty - write back to memory
if (tag_hit_and_dirty_m_w)
next_state_r = STATE_EVICT;
// Line not dirty, carry on
else
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_INVALIDATE: Invalidate a cache line
//-----------------------------------------
STATE_INVALIDATE:
begin
next_state_r = STATE_LOOKUP;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_RESET;
else
state_q <= next_state_r;
reg mem_ack_r;
always @ *
begin
mem_ack_r = 1'b0;
if (state_q == STATE_LOOKUP)
begin
// Normal hit - read or write
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && tag_hit_any_m_w)
mem_ack_r = 1'b1;
// Flush, invalidate or writeback
else if (mem_flush_m_q || mem_inval_m_q || mem_writeback_m_q)
mem_ack_r = 1'b1;
end
end
assign mem_ack_o = mem_ack_r;
//-----------------------------------------------------------------
// AXI Request
//-----------------------------------------------------------------
reg pmem_rd_q;
reg pmem_wr0_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_rd_q <= 1'b0;
else if (pmem_rd_w)
pmem_rd_q <= ~pmem_accept_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_wr0_q <= 1'b0;
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
pmem_wr0_q <= 1'b1;
else if (pmem_accept_w)
pmem_wr0_q <= 1'b0;
reg [7:0] pmem_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_len_q <= 8'b0;
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
pmem_len_q <= 8'd7;
else if (pmem_rd_w && pmem_accept_w)
pmem_len_q <= pmem_len_w;
else if (state_q == STATE_REFILL && pmem_ack_w)
pmem_len_q <= pmem_len_q - 8'd1;
else if (state_q == STATE_EVICT && pmem_accept_w)
pmem_len_q <= pmem_len_q - 8'd1;
assign pmem_last_w = (pmem_len_q == 8'd0);
reg [31:0] pmem_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_addr_q <= 32'b0;
else if (|pmem_len_w && pmem_accept_w)
pmem_addr_q <= pmem_addr_w + 32'd4;
else if (pmem_accept_w)
pmem_addr_q <= pmem_addr_q + 32'd4;
//-----------------------------------------------------------------
// Skid buffer for write data
//-----------------------------------------------------------------
reg [3:0] pmem_wr_q;
reg [31:0] pmem_write_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_wr_q <= 4'b0;
else if ((|pmem_wr_w) && !pmem_accept_w)
pmem_wr_q <= pmem_wr_w;
else if (pmem_accept_w)
pmem_wr_q <= 4'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_write_data_q <= 32'b0;
else if (!pmem_accept_w)
pmem_write_data_q <= pmem_write_data_w;
//-----------------------------------------------------------------
// AXI Error Handling
//-----------------------------------------------------------------
reg error_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
error_q <= 1'b0;
else if (pmem_ack_w && pmem_error_w)
error_q <= 1'b1;
else if (mem_ack_o)
error_q <= 1'b0;
assign mem_error_o = error_q;
//-----------------------------------------------------------------
// Outport
//-----------------------------------------------------------------
wire refill_request_w = (state_q != STATE_REFILL && next_state_r == STATE_REFILL);
wire evict_request_w = (state_q == STATE_EVICT) && (evict_way_w || mem_writeback_m_q);
// AXI Read channel
assign pmem_rd_w = (refill_request_w || pmem_rd_q);
assign pmem_wr_w = (evict_request_w || (|pmem_wr_q)) ? 4'hF : 4'b0;
assign pmem_addr_w = (|pmem_len_w) ?
pmem_rd_w ? {mem_addr_m_q[31:DCACHE_LINE_SIZE_W], {(DCACHE_LINE_SIZE_W){1'b0}}} :
{evict_addr_w, {(DCACHE_LINE_SIZE_W){1'b0}}} :
pmem_addr_q;
assign pmem_len_w = (refill_request_w || pmem_rd_q || (state_q == STATE_EVICT && pmem_wr0_q)) ? 8'd7 : 8'd0;
assign pmem_write_data_w = (|pmem_wr_q) ? pmem_write_data_q : evict_data_w;
assign outport_wr_o = pmem_wr_w;
assign outport_rd_o = pmem_rd_w;
assign outport_len_o = pmem_len_w;
assign outport_addr_o = pmem_addr_w;
assign outport_write_data_o = pmem_write_data_w;
assign pmem_accept_w = outport_accept_i;
assign pmem_ack_w = outport_ack_i;
assign pmem_error_w = outport_error_i;
assign pmem_read_data_w = outport_read_data_i;
//-------------------------------------------------------------------
// Debug
//-------------------------------------------------------------------
`ifdef verilator
/* verilator lint_off WIDTH */
reg [79:0] dbg_state;
always @ *
begin
dbg_state = "-";
case (state_q)
STATE_RESET:
dbg_state = "RESET";
STATE_FLUSH_ADDR:
dbg_state = "FLUSH_ADDR";
STATE_FLUSH:
dbg_state = "FLUSH";
STATE_LOOKUP:
dbg_state = "LOOKUP";
STATE_READ:
dbg_state = "READ";
STATE_WRITE:
dbg_state = "WRITE";
STATE_REFILL:
dbg_state = "REFILL";
STATE_EVICT:
dbg_state = "EVICT";
STATE_EVICT_WAIT:
dbg_state = "EVICT_WAIT";
STATE_INVALIDATE:
dbg_state = "INVAL";
STATE_WRITEBACK:
dbg_state = "WRITEBACK";
default:
;
endcase
end
/* verilator lint_on WIDTH */
`endif
endmodule |
module icache_data_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 10:0] addr_i
,input [ 31:0] data_i
,input wr_i
// Outputs
,output [ 31:0] data_o
);
//-----------------------------------------------------------------
// Single Port RAM 8KB
// Mode: Read First
//-----------------------------------------------------------------
reg [31:0] ram [2047:0] /*verilator public*/;
reg [31:0] ram_read_q;
// Synchronous write
always @ (posedge clk_i)
begin
if (wr_i)
ram[addr_i] <= data_i;
ram_read_q <= ram[addr_i];
end
assign data_o = ram_read_q;
endmodule |
module dcache_core_tag_ram
(
// Inputs
input clk0_i
,input rst0_i
,input [ 7:0] addr0_i
,input clk1_i
,input rst1_i
,input [ 7:0] addr1_i
,input [ 20:0] data1_i
,input wr1_i
// Outputs
,output [ 20:0] data0_o
);
//-----------------------------------------------------------------
// Tag RAM 0KB (256 x 21)
// Mode: Write First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [20:0] ram [255:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [20:0] ram_read0_q;
always @ (posedge clk1_i)
begin
if (wr1_i)
ram[addr1_i] = data1_i;
ram_read0_q = ram[addr0_i];
end
assign data0_o = ram_read0_q;
endmodule |
module dcache_mux
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input [ 31:0] mem_cached_data_rd_i
,input mem_cached_accept_i
,input mem_cached_ack_i
,input mem_cached_error_i
,input [ 10:0] mem_cached_resp_tag_i
,input [ 31:0] mem_uncached_data_rd_i
,input mem_uncached_accept_i
,input mem_uncached_ack_i
,input mem_uncached_error_i
,input [ 10:0] mem_uncached_resp_tag_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 31:0] mem_cached_addr_o
,output [ 31:0] mem_cached_data_wr_o
,output mem_cached_rd_o
,output [ 3:0] mem_cached_wr_o
,output mem_cached_cacheable_o
,output [ 10:0] mem_cached_req_tag_o
,output mem_cached_invalidate_o
,output mem_cached_writeback_o
,output mem_cached_flush_o
,output [ 31:0] mem_uncached_addr_o
,output [ 31:0] mem_uncached_data_wr_o
,output mem_uncached_rd_o
,output [ 3:0] mem_uncached_wr_o
,output mem_uncached_cacheable_o
,output [ 10:0] mem_uncached_req_tag_o
,output mem_uncached_invalidate_o
,output mem_uncached_writeback_o
,output mem_uncached_flush_o
,output cache_active_o
);
wire hold_w;
reg cache_access_q;
assign mem_cached_addr_o = mem_addr_i;
assign mem_cached_data_wr_o = mem_data_wr_i;
assign mem_cached_rd_o = (mem_cacheable_i & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_cached_wr_o = (mem_cacheable_i & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_cached_cacheable_o = mem_cacheable_i;
assign mem_cached_req_tag_o = mem_req_tag_i;
assign mem_cached_invalidate_o = (mem_cacheable_i & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_cached_writeback_o = (mem_cacheable_i & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_cached_flush_o = (mem_cacheable_i & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_uncached_addr_o = mem_addr_i;
assign mem_uncached_data_wr_o = mem_data_wr_i;
assign mem_uncached_rd_o = (~mem_cacheable_i & ~hold_w) ? mem_rd_i : 1'b0;
assign mem_uncached_wr_o = (~mem_cacheable_i & ~hold_w) ? mem_wr_i : 4'b0;
assign mem_uncached_cacheable_o = mem_cacheable_i;
assign mem_uncached_req_tag_o = mem_req_tag_i;
assign mem_uncached_invalidate_o = (~mem_cacheable_i & ~hold_w) ? mem_invalidate_i : 1'b0;
assign mem_uncached_writeback_o = (~mem_cacheable_i & ~hold_w) ? mem_writeback_i : 1'b0;
assign mem_uncached_flush_o = (~mem_cacheable_i & ~hold_w) ? mem_flush_i : 1'b0;
assign mem_accept_o =(mem_cacheable_i ? mem_cached_accept_i : mem_uncached_accept_i) & !hold_w;
assign mem_data_rd_o = cache_access_q ? mem_cached_data_rd_i : mem_uncached_data_rd_i;
assign mem_ack_o = cache_access_q ? mem_cached_ack_i : mem_uncached_ack_i;
assign mem_error_o = cache_access_q ? mem_cached_error_i : mem_uncached_error_i;
assign mem_resp_tag_o = cache_access_q ? mem_cached_resp_tag_i : mem_uncached_resp_tag_i;
wire request_w = mem_rd_i | mem_wr_i != 4'b0 | mem_flush_i | mem_invalidate_i | mem_writeback_i;
reg [4:0] pending_r;
reg [4:0] pending_q;
always @ *
begin
pending_r = pending_q;
if ((request_w && mem_accept_o) && !mem_ack_o)
pending_r = pending_r + 5'd1;
else if (!(request_w && mem_accept_o) && mem_ack_o)
pending_r = pending_r - 5'd1;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pending_q <= 5'b0;
else
pending_q <= pending_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
cache_access_q <= 1'b0;
else if (request_w && mem_accept_o)
cache_access_q <= mem_cacheable_i;
assign hold_w = (|pending_q) && (cache_access_q != mem_cacheable_i);
assign cache_active_o = (|pending_q) ? cache_access_q : mem_cacheable_i;
endmodule |
module riscv_top
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CORE_ID = 0
,parameter MEM_CACHE_ADDR_MIN = 0
,parameter MEM_CACHE_ADDR_MAX = 32'hffffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input axi_i_awready_i
,input axi_i_wready_i
,input axi_i_bvalid_i
,input [ 1:0] axi_i_bresp_i
,input [ 3:0] axi_i_bid_i
,input axi_i_arready_i
,input axi_i_rvalid_i
,input [ 31:0] axi_i_rdata_i
,input [ 1:0] axi_i_rresp_i
,input [ 3:0] axi_i_rid_i
,input axi_i_rlast_i
,input axi_d_awready_i
,input axi_d_wready_i
,input axi_d_bvalid_i
,input [ 1:0] axi_d_bresp_i
,input [ 3:0] axi_d_bid_i
,input axi_d_arready_i
,input axi_d_rvalid_i
,input [ 31:0] axi_d_rdata_i
,input [ 1:0] axi_d_rresp_i
,input [ 3:0] axi_d_rid_i
,input axi_d_rlast_i
,input intr_i
,input [ 31:0] reset_vector_i
// Outputs
,output axi_i_awvalid_o
,output [ 31:0] axi_i_awaddr_o
,output [ 3:0] axi_i_awid_o
,output [ 7:0] axi_i_awlen_o
,output [ 1:0] axi_i_awburst_o
,output axi_i_wvalid_o
,output [ 31:0] axi_i_wdata_o
,output [ 3:0] axi_i_wstrb_o
,output axi_i_wlast_o
,output axi_i_bready_o
,output axi_i_arvalid_o
,output [ 31:0] axi_i_araddr_o
,output [ 3:0] axi_i_arid_o
,output [ 7:0] axi_i_arlen_o
,output [ 1:0] axi_i_arburst_o
,output axi_i_rready_o
,output axi_d_awvalid_o
,output [ 31:0] axi_d_awaddr_o
,output [ 3:0] axi_d_awid_o
,output [ 7:0] axi_d_awlen_o
,output [ 1:0] axi_d_awburst_o
,output axi_d_wvalid_o
,output [ 31:0] axi_d_wdata_o
,output [ 3:0] axi_d_wstrb_o
,output axi_d_wlast_o
,output axi_d_bready_o
,output axi_d_arvalid_o
,output [ 31:0] axi_d_araddr_o
,output [ 3:0] axi_d_arid_o
,output [ 7:0] axi_d_arlen_o
,output [ 1:0] axi_d_arburst_o
,output axi_d_rready_o
);
wire icache_valid_w;
wire icache_flush_w;
wire dcache_flush_w;
wire dcache_invalidate_w;
wire dcache_ack_w;
wire [ 10:0] dcache_resp_tag_w;
wire [ 31:0] icache_inst_w;
wire [ 31:0] cpu_id_w = CORE_ID;
wire dcache_rd_w;
wire [ 31:0] dcache_addr_w;
wire dcache_accept_w;
wire icache_invalidate_w;
wire dcache_writeback_w;
wire [ 10:0] dcache_req_tag_w;
wire dcache_cacheable_w;
wire icache_error_w;
wire [ 31:0] dcache_data_rd_w;
wire icache_accept_w;
wire [ 3:0] dcache_wr_w;
wire [ 31:0] icache_pc_w;
wire icache_rd_w;
wire dcache_error_w;
wire [ 31:0] dcache_data_wr_w;
dcache
u_dcache
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dcache_addr_w)
,.mem_data_wr_i(dcache_data_wr_w)
,.mem_rd_i(dcache_rd_w)
,.mem_wr_i(dcache_wr_w)
,.mem_cacheable_i(dcache_cacheable_w)
,.mem_req_tag_i(dcache_req_tag_w)
,.mem_invalidate_i(dcache_invalidate_w)
,.mem_writeback_i(dcache_writeback_w)
,.mem_flush_i(dcache_flush_w)
,.axi_awready_i(axi_d_awready_i)
,.axi_wready_i(axi_d_wready_i)
,.axi_bvalid_i(axi_d_bvalid_i)
,.axi_bresp_i(axi_d_bresp_i)
,.axi_bid_i(axi_d_bid_i)
,.axi_arready_i(axi_d_arready_i)
,.axi_rvalid_i(axi_d_rvalid_i)
,.axi_rdata_i(axi_d_rdata_i)
,.axi_rresp_i(axi_d_rresp_i)
,.axi_rid_i(axi_d_rid_i)
,.axi_rlast_i(axi_d_rlast_i)
// Outputs
,.mem_data_rd_o(dcache_data_rd_w)
,.mem_accept_o(dcache_accept_w)
,.mem_ack_o(dcache_ack_w)
,.mem_error_o(dcache_error_w)
,.mem_resp_tag_o(dcache_resp_tag_w)
,.axi_awvalid_o(axi_d_awvalid_o)
,.axi_awaddr_o(axi_d_awaddr_o)
,.axi_awid_o(axi_d_awid_o)
,.axi_awlen_o(axi_d_awlen_o)
,.axi_awburst_o(axi_d_awburst_o)
,.axi_wvalid_o(axi_d_wvalid_o)
,.axi_wdata_o(axi_d_wdata_o)
,.axi_wstrb_o(axi_d_wstrb_o)
,.axi_wlast_o(axi_d_wlast_o)
,.axi_bready_o(axi_d_bready_o)
,.axi_arvalid_o(axi_d_arvalid_o)
,.axi_araddr_o(axi_d_araddr_o)
,.axi_arid_o(axi_d_arid_o)
,.axi_arlen_o(axi_d_arlen_o)
,.axi_arburst_o(axi_d_arburst_o)
,.axi_rready_o(axi_d_rready_o)
);
riscv_core
#(
.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
)
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_d_data_rd_i(dcache_data_rd_w)
,.mem_d_accept_i(dcache_accept_w)
,.mem_d_ack_i(dcache_ack_w)
,.mem_d_error_i(dcache_error_w)
,.mem_d_resp_tag_i(dcache_resp_tag_w)
,.mem_i_accept_i(icache_accept_w)
,.mem_i_valid_i(icache_valid_w)
,.mem_i_error_i(icache_error_w)
,.mem_i_inst_i(icache_inst_w)
,.intr_i(intr_i)
,.reset_vector_i(reset_vector_i)
,.cpu_id_i(cpu_id_w)
// Outputs
,.mem_d_addr_o(dcache_addr_w)
,.mem_d_data_wr_o(dcache_data_wr_w)
,.mem_d_rd_o(dcache_rd_w)
,.mem_d_wr_o(dcache_wr_w)
,.mem_d_cacheable_o(dcache_cacheable_w)
,.mem_d_req_tag_o(dcache_req_tag_w)
,.mem_d_invalidate_o(dcache_invalidate_w)
,.mem_d_writeback_o(dcache_writeback_w)
,.mem_d_flush_o(dcache_flush_w)
,.mem_i_rd_o(icache_rd_w)
,.mem_i_flush_o(icache_flush_w)
,.mem_i_invalidate_o(icache_invalidate_w)
,.mem_i_pc_o(icache_pc_w)
);
icache
u_icache
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.req_rd_i(icache_rd_w)
,.req_flush_i(icache_flush_w)
,.req_invalidate_i(icache_invalidate_w)
,.req_pc_i(icache_pc_w)
,.axi_awready_i(axi_i_awready_i)
,.axi_wready_i(axi_i_wready_i)
,.axi_bvalid_i(axi_i_bvalid_i)
,.axi_bresp_i(axi_i_bresp_i)
,.axi_bid_i(axi_i_bid_i)
,.axi_arready_i(axi_i_arready_i)
,.axi_rvalid_i(axi_i_rvalid_i)
,.axi_rdata_i(axi_i_rdata_i)
,.axi_rresp_i(axi_i_rresp_i)
,.axi_rid_i(axi_i_rid_i)
,.axi_rlast_i(axi_i_rlast_i)
// Outputs
,.req_accept_o(icache_accept_w)
,.req_valid_o(icache_valid_w)
,.req_error_o(icache_error_w)
,.req_inst_o(icache_inst_w)
,.axi_awvalid_o(axi_i_awvalid_o)
,.axi_awaddr_o(axi_i_awaddr_o)
,.axi_awid_o(axi_i_awid_o)
,.axi_awlen_o(axi_i_awlen_o)
,.axi_awburst_o(axi_i_awburst_o)
,.axi_wvalid_o(axi_i_wvalid_o)
,.axi_wdata_o(axi_i_wdata_o)
,.axi_wstrb_o(axi_i_wstrb_o)
,.axi_wlast_o(axi_i_wlast_o)
,.axi_bready_o(axi_i_bready_o)
,.axi_arvalid_o(axi_i_arvalid_o)
,.axi_araddr_o(axi_i_araddr_o)
,.axi_arid_o(axi_i_arid_o)
,.axi_arlen_o(axi_i_arlen_o)
,.axi_arburst_o(axi_i_arburst_o)
,.axi_rready_o(axi_i_rready_o)
);
endmodule |
module dcache
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter AXI_ID = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input [ 3:0] axi_bid_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
,input [ 3:0] axi_rid_i
,input axi_rlast_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output [ 3:0] axi_awid_o
,output [ 7:0] axi_awlen_o
,output [ 1:0] axi_awburst_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_wlast_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output [ 3:0] axi_arid_o
,output [ 7:0] axi_arlen_o
,output [ 1:0] axi_arburst_o
,output axi_rready_o
);
wire mem_uncached_invalidate_w;
wire pmem_cache_accept_w;
wire mem_uncached_accept_w;
wire [ 7:0] pmem_cache_len_w;
wire [ 3:0] mem_cached_wr_w;
wire [ 31:0] pmem_cache_read_data_w;
wire mem_cached_invalidate_w;
wire pmem_uncached_ack_w;
wire [ 7:0] pmem_len_w;
wire pmem_uncached_accept_w;
wire mem_cached_accept_w;
wire pmem_cache_ack_w;
wire [ 31:0] pmem_cache_addr_w;
wire pmem_cache_rd_w;
wire pmem_error_w;
wire [ 31:0] pmem_addr_w;
wire [ 10:0] mem_cached_req_tag_w;
wire mem_uncached_ack_w;
wire pmem_ack_w;
wire [ 31:0] mem_uncached_data_wr_w;
wire [ 31:0] pmem_uncached_addr_w;
wire [ 31:0] mem_cached_data_rd_w;
wire [ 31:0] pmem_uncached_read_data_w;
wire mem_uncached_flush_w;
wire pmem_uncached_error_w;
wire [ 31:0] mem_uncached_data_rd_w;
wire [ 31:0] pmem_write_data_w;
wire [ 3:0] pmem_uncached_wr_w;
wire mem_cached_rd_w;
wire [ 10:0] mem_cached_resp_tag_w;
wire [ 7:0] pmem_uncached_len_w;
wire [ 31:0] mem_cached_data_wr_w;
wire [ 3:0] pmem_wr_w;
wire pmem_select_w;
wire mem_cached_flush_w;
wire mem_uncached_cacheable_w;
wire [ 31:0] mem_cached_addr_w;
wire mem_uncached_writeback_w;
wire [ 3:0] pmem_cache_wr_w;
wire pmem_cache_error_w;
wire [ 10:0] mem_uncached_req_tag_w;
wire [ 31:0] pmem_uncached_write_data_w;
wire [ 10:0] mem_uncached_resp_tag_w;
wire pmem_rd_w;
wire mem_cached_cacheable_w;
wire [ 3:0] mem_uncached_wr_w;
wire mem_uncached_error_w;
wire mem_uncached_rd_w;
wire pmem_accept_w;
wire [ 31:0] pmem_cache_write_data_w;
wire mem_cached_error_w;
wire [ 31:0] mem_uncached_addr_w;
wire pmem_uncached_rd_w;
wire [ 31:0] pmem_read_data_w;
wire mem_cached_ack_w;
wire mem_cached_writeback_w;
dcache_if_pmem
u_uncached
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_uncached_addr_w)
,.mem_data_wr_i(mem_uncached_data_wr_w)
,.mem_rd_i(mem_uncached_rd_w)
,.mem_wr_i(mem_uncached_wr_w)
,.mem_cacheable_i(mem_uncached_cacheable_w)
,.mem_req_tag_i(mem_uncached_req_tag_w)
,.mem_invalidate_i(mem_uncached_invalidate_w)
,.mem_writeback_i(mem_uncached_writeback_w)
,.mem_flush_i(mem_uncached_flush_w)
,.outport_accept_i(pmem_uncached_accept_w)
,.outport_ack_i(pmem_uncached_ack_w)
,.outport_error_i(pmem_uncached_error_w)
,.outport_read_data_i(pmem_uncached_read_data_w)
// Outputs
,.mem_data_rd_o(mem_uncached_data_rd_w)
,.mem_accept_o(mem_uncached_accept_w)
,.mem_ack_o(mem_uncached_ack_w)
,.mem_error_o(mem_uncached_error_w)
,.mem_resp_tag_o(mem_uncached_resp_tag_w)
,.outport_wr_o(pmem_uncached_wr_w)
,.outport_rd_o(pmem_uncached_rd_w)
,.outport_len_o(pmem_uncached_len_w)
,.outport_addr_o(pmem_uncached_addr_w)
,.outport_write_data_o(pmem_uncached_write_data_w)
);
dcache_pmem_mux
u_pmem_mux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_accept_i(pmem_accept_w)
,.outport_ack_i(pmem_ack_w)
,.outport_error_i(pmem_error_w)
,.outport_read_data_i(pmem_read_data_w)
,.select_i(pmem_select_w)
,.inport0_wr_i(pmem_uncached_wr_w)
,.inport0_rd_i(pmem_uncached_rd_w)
,.inport0_len_i(pmem_uncached_len_w)
,.inport0_addr_i(pmem_uncached_addr_w)
,.inport0_write_data_i(pmem_uncached_write_data_w)
,.inport1_wr_i(pmem_cache_wr_w)
,.inport1_rd_i(pmem_cache_rd_w)
,.inport1_len_i(pmem_cache_len_w)
,.inport1_addr_i(pmem_cache_addr_w)
,.inport1_write_data_i(pmem_cache_write_data_w)
// Outputs
,.outport_wr_o(pmem_wr_w)
,.outport_rd_o(pmem_rd_w)
,.outport_len_o(pmem_len_w)
,.outport_addr_o(pmem_addr_w)
,.outport_write_data_o(pmem_write_data_w)
,.inport0_accept_o(pmem_uncached_accept_w)
,.inport0_ack_o(pmem_uncached_ack_w)
,.inport0_error_o(pmem_uncached_error_w)
,.inport0_read_data_o(pmem_uncached_read_data_w)
,.inport1_accept_o(pmem_cache_accept_w)
,.inport1_ack_o(pmem_cache_ack_w)
,.inport1_error_o(pmem_cache_error_w)
,.inport1_read_data_o(pmem_cache_read_data_w)
);
dcache_mux
u_mux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_addr_i)
,.mem_data_wr_i(mem_data_wr_i)
,.mem_rd_i(mem_rd_i)
,.mem_wr_i(mem_wr_i)
,.mem_cacheable_i(mem_cacheable_i)
,.mem_req_tag_i(mem_req_tag_i)
,.mem_invalidate_i(mem_invalidate_i)
,.mem_writeback_i(mem_writeback_i)
,.mem_flush_i(mem_flush_i)
,.mem_cached_data_rd_i(mem_cached_data_rd_w)
,.mem_cached_accept_i(mem_cached_accept_w)
,.mem_cached_ack_i(mem_cached_ack_w)
,.mem_cached_error_i(mem_cached_error_w)
,.mem_cached_resp_tag_i(mem_cached_resp_tag_w)
,.mem_uncached_data_rd_i(mem_uncached_data_rd_w)
,.mem_uncached_accept_i(mem_uncached_accept_w)
,.mem_uncached_ack_i(mem_uncached_ack_w)
,.mem_uncached_error_i(mem_uncached_error_w)
,.mem_uncached_resp_tag_i(mem_uncached_resp_tag_w)
// Outputs
,.mem_data_rd_o(mem_data_rd_o)
,.mem_accept_o(mem_accept_o)
,.mem_ack_o(mem_ack_o)
,.mem_error_o(mem_error_o)
,.mem_resp_tag_o(mem_resp_tag_o)
,.mem_cached_addr_o(mem_cached_addr_w)
,.mem_cached_data_wr_o(mem_cached_data_wr_w)
,.mem_cached_rd_o(mem_cached_rd_w)
,.mem_cached_wr_o(mem_cached_wr_w)
,.mem_cached_cacheable_o(mem_cached_cacheable_w)
,.mem_cached_req_tag_o(mem_cached_req_tag_w)
,.mem_cached_invalidate_o(mem_cached_invalidate_w)
,.mem_cached_writeback_o(mem_cached_writeback_w)
,.mem_cached_flush_o(mem_cached_flush_w)
,.mem_uncached_addr_o(mem_uncached_addr_w)
,.mem_uncached_data_wr_o(mem_uncached_data_wr_w)
,.mem_uncached_rd_o(mem_uncached_rd_w)
,.mem_uncached_wr_o(mem_uncached_wr_w)
,.mem_uncached_cacheable_o(mem_uncached_cacheable_w)
,.mem_uncached_req_tag_o(mem_uncached_req_tag_w)
,.mem_uncached_invalidate_o(mem_uncached_invalidate_w)
,.mem_uncached_writeback_o(mem_uncached_writeback_w)
,.mem_uncached_flush_o(mem_uncached_flush_w)
,.cache_active_o(pmem_select_w)
);
dcache_core
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(mem_cached_addr_w)
,.mem_data_wr_i(mem_cached_data_wr_w)
,.mem_rd_i(mem_cached_rd_w)
,.mem_wr_i(mem_cached_wr_w)
,.mem_cacheable_i(mem_cached_cacheable_w)
,.mem_req_tag_i(mem_cached_req_tag_w)
,.mem_invalidate_i(mem_cached_invalidate_w)
,.mem_writeback_i(mem_cached_writeback_w)
,.mem_flush_i(mem_cached_flush_w)
,.outport_accept_i(pmem_cache_accept_w)
,.outport_ack_i(pmem_cache_ack_w)
,.outport_error_i(pmem_cache_error_w)
,.outport_read_data_i(pmem_cache_read_data_w)
// Outputs
,.mem_data_rd_o(mem_cached_data_rd_w)
,.mem_accept_o(mem_cached_accept_w)
,.mem_ack_o(mem_cached_ack_w)
,.mem_error_o(mem_cached_error_w)
,.mem_resp_tag_o(mem_cached_resp_tag_w)
,.outport_wr_o(pmem_cache_wr_w)
,.outport_rd_o(pmem_cache_rd_w)
,.outport_len_o(pmem_cache_len_w)
,.outport_addr_o(pmem_cache_addr_w)
,.outport_write_data_o(pmem_cache_write_data_w)
);
dcache_axi
#(
.AXI_ID(AXI_ID)
)
u_axi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.outport_awready_i(axi_awready_i)
,.outport_wready_i(axi_wready_i)
,.outport_bvalid_i(axi_bvalid_i)
,.outport_bresp_i(axi_bresp_i)
,.outport_bid_i(axi_bid_i)
,.outport_arready_i(axi_arready_i)
,.outport_rvalid_i(axi_rvalid_i)
,.outport_rdata_i(axi_rdata_i)
,.outport_rresp_i(axi_rresp_i)
,.outport_rid_i(axi_rid_i)
,.outport_rlast_i(axi_rlast_i)
,.inport_wr_i(pmem_wr_w)
,.inport_rd_i(pmem_rd_w)
,.inport_len_i(pmem_len_w)
,.inport_addr_i(pmem_addr_w)
,.inport_write_data_i(pmem_write_data_w)
// Outputs
,.outport_awvalid_o(axi_awvalid_o)
,.outport_awaddr_o(axi_awaddr_o)
,.outport_awid_o(axi_awid_o)
,.outport_awlen_o(axi_awlen_o)
,.outport_awburst_o(axi_awburst_o)
,.outport_wvalid_o(axi_wvalid_o)
,.outport_wdata_o(axi_wdata_o)
,.outport_wstrb_o(axi_wstrb_o)
,.outport_wlast_o(axi_wlast_o)
,.outport_bready_o(axi_bready_o)
,.outport_arvalid_o(axi_arvalid_o)
,.outport_araddr_o(axi_araddr_o)
,.outport_arid_o(axi_arid_o)
,.outport_arlen_o(axi_arlen_o)
,.outport_arburst_o(axi_arburst_o)
,.outport_rready_o(axi_rready_o)
,.inport_accept_o(pmem_accept_w)
,.inport_ack_o(pmem_ack_w)
,.inport_error_o(pmem_error_w)
,.inport_read_data_o(pmem_read_data_w)
);
endmodule |
module riscv_tcm_top
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter BOOT_VECTOR = 32'h00002000
,parameter CORE_ID = 0
,parameter TCM_MEM_BASE = 0
,parameter MEM_CACHE_ADDR_MIN = 0
,parameter MEM_CACHE_ADDR_MAX = 32'hffffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input rst_cpu_i
,input axi_i_awready_i
,input axi_i_wready_i
,input axi_i_bvalid_i
,input [ 1:0] axi_i_bresp_i
,input axi_i_arready_i
,input axi_i_rvalid_i
,input [ 31:0] axi_i_rdata_i
,input [ 1:0] axi_i_rresp_i
,input axi_t_awvalid_i
,input [ 31:0] axi_t_awaddr_i
,input [ 3:0] axi_t_awid_i
,input [ 7:0] axi_t_awlen_i
,input [ 1:0] axi_t_awburst_i
,input axi_t_wvalid_i
,input [ 31:0] axi_t_wdata_i
,input [ 3:0] axi_t_wstrb_i
,input axi_t_wlast_i
,input axi_t_bready_i
,input axi_t_arvalid_i
,input [ 31:0] axi_t_araddr_i
,input [ 3:0] axi_t_arid_i
,input [ 7:0] axi_t_arlen_i
,input [ 1:0] axi_t_arburst_i
,input axi_t_rready_i
,input [ 31:0] intr_i
// Outputs
,output axi_i_awvalid_o
,output [ 31:0] axi_i_awaddr_o
,output axi_i_wvalid_o
,output [ 31:0] axi_i_wdata_o
,output [ 3:0] axi_i_wstrb_o
,output axi_i_bready_o
,output axi_i_arvalid_o
,output [ 31:0] axi_i_araddr_o
,output axi_i_rready_o
,output axi_t_awready_o
,output axi_t_wready_o
,output axi_t_bvalid_o
,output [ 1:0] axi_t_bresp_o
,output [ 3:0] axi_t_bid_o
,output axi_t_arready_o
,output axi_t_rvalid_o
,output [ 31:0] axi_t_rdata_o
,output [ 1:0] axi_t_rresp_o
,output [ 3:0] axi_t_rid_o
,output axi_t_rlast_o
);
wire [ 31:0] ifetch_pc_w;
wire [ 31:0] dport_tcm_data_rd_w;
wire dport_tcm_cacheable_w;
wire dport_flush_w;
wire [ 3:0] dport_tcm_wr_w;
wire ifetch_rd_w;
wire dport_axi_accept_w;
wire dport_cacheable_w;
wire dport_tcm_flush_w;
wire [ 10:0] dport_resp_tag_w;
wire [ 10:0] dport_axi_resp_tag_w;
wire ifetch_accept_w;
wire [ 31:0] dport_data_rd_w;
wire dport_tcm_invalidate_w;
wire dport_ack_w;
wire [ 10:0] dport_axi_req_tag_w;
wire [ 31:0] dport_data_wr_w;
wire dport_invalidate_w;
wire [ 10:0] dport_tcm_req_tag_w;
wire [ 31:0] dport_tcm_addr_w;
wire dport_axi_error_w;
wire dport_tcm_ack_w;
wire dport_tcm_rd_w;
wire [ 10:0] dport_tcm_resp_tag_w;
wire dport_writeback_w;
wire [ 31:0] cpu_id_w = CORE_ID;
wire dport_rd_w;
wire dport_axi_ack_w;
wire dport_axi_rd_w;
wire [ 31:0] dport_axi_data_rd_w;
wire dport_axi_invalidate_w;
wire [ 31:0] boot_vector_w = BOOT_VECTOR;
wire [ 31:0] dport_addr_w;
wire ifetch_error_w;
wire [ 31:0] dport_tcm_data_wr_w;
wire ifetch_flush_w;
wire [ 31:0] dport_axi_addr_w;
wire dport_error_w;
wire dport_tcm_accept_w;
wire ifetch_invalidate_w;
wire dport_axi_writeback_w;
wire [ 3:0] dport_wr_w;
wire ifetch_valid_w;
wire [ 31:0] dport_axi_data_wr_w;
wire [ 10:0] dport_req_tag_w;
wire [ 31:0] ifetch_inst_w;
wire dport_axi_cacheable_w;
wire dport_tcm_writeback_w;
wire [ 3:0] dport_axi_wr_w;
wire dport_axi_flush_w;
wire dport_tcm_error_w;
wire dport_accept_w;
riscv_core
#(
.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
,.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
)
u_core
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_cpu_i)
,.mem_d_data_rd_i(dport_data_rd_w)
,.mem_d_accept_i(dport_accept_w)
,.mem_d_ack_i(dport_ack_w)
,.mem_d_error_i(dport_error_w)
,.mem_d_resp_tag_i(dport_resp_tag_w)
,.mem_i_accept_i(ifetch_accept_w)
,.mem_i_valid_i(ifetch_valid_w)
,.mem_i_error_i(ifetch_error_w)
,.mem_i_inst_i(ifetch_inst_w)
,.intr_i(intr_i[0:0])
,.reset_vector_i(boot_vector_w)
,.cpu_id_i(cpu_id_w)
// Outputs
,.mem_d_addr_o(dport_addr_w)
,.mem_d_data_wr_o(dport_data_wr_w)
,.mem_d_rd_o(dport_rd_w)
,.mem_d_wr_o(dport_wr_w)
,.mem_d_cacheable_o(dport_cacheable_w)
,.mem_d_req_tag_o(dport_req_tag_w)
,.mem_d_invalidate_o(dport_invalidate_w)
,.mem_d_writeback_o(dport_writeback_w)
,.mem_d_flush_o(dport_flush_w)
,.mem_i_rd_o(ifetch_rd_w)
,.mem_i_flush_o(ifetch_flush_w)
,.mem_i_invalidate_o(ifetch_invalidate_w)
,.mem_i_pc_o(ifetch_pc_w)
);
dport_mux
#(
.TCM_MEM_BASE(TCM_MEM_BASE)
)
u_dmux
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_addr_w)
,.mem_data_wr_i(dport_data_wr_w)
,.mem_rd_i(dport_rd_w)
,.mem_wr_i(dport_wr_w)
,.mem_cacheable_i(dport_cacheable_w)
,.mem_req_tag_i(dport_req_tag_w)
,.mem_invalidate_i(dport_invalidate_w)
,.mem_writeback_i(dport_writeback_w)
,.mem_flush_i(dport_flush_w)
,.mem_tcm_data_rd_i(dport_tcm_data_rd_w)
,.mem_tcm_accept_i(dport_tcm_accept_w)
,.mem_tcm_ack_i(dport_tcm_ack_w)
,.mem_tcm_error_i(dport_tcm_error_w)
,.mem_tcm_resp_tag_i(dport_tcm_resp_tag_w)
,.mem_ext_data_rd_i(dport_axi_data_rd_w)
,.mem_ext_accept_i(dport_axi_accept_w)
,.mem_ext_ack_i(dport_axi_ack_w)
,.mem_ext_error_i(dport_axi_error_w)
,.mem_ext_resp_tag_i(dport_axi_resp_tag_w)
// Outputs
,.mem_data_rd_o(dport_data_rd_w)
,.mem_accept_o(dport_accept_w)
,.mem_ack_o(dport_ack_w)
,.mem_error_o(dport_error_w)
,.mem_resp_tag_o(dport_resp_tag_w)
,.mem_tcm_addr_o(dport_tcm_addr_w)
,.mem_tcm_data_wr_o(dport_tcm_data_wr_w)
,.mem_tcm_rd_o(dport_tcm_rd_w)
,.mem_tcm_wr_o(dport_tcm_wr_w)
,.mem_tcm_cacheable_o(dport_tcm_cacheable_w)
,.mem_tcm_req_tag_o(dport_tcm_req_tag_w)
,.mem_tcm_invalidate_o(dport_tcm_invalidate_w)
,.mem_tcm_writeback_o(dport_tcm_writeback_w)
,.mem_tcm_flush_o(dport_tcm_flush_w)
,.mem_ext_addr_o(dport_axi_addr_w)
,.mem_ext_data_wr_o(dport_axi_data_wr_w)
,.mem_ext_rd_o(dport_axi_rd_w)
,.mem_ext_wr_o(dport_axi_wr_w)
,.mem_ext_cacheable_o(dport_axi_cacheable_w)
,.mem_ext_req_tag_o(dport_axi_req_tag_w)
,.mem_ext_invalidate_o(dport_axi_invalidate_w)
,.mem_ext_writeback_o(dport_axi_writeback_w)
,.mem_ext_flush_o(dport_axi_flush_w)
);
tcm_mem
u_tcm
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_i_rd_i(ifetch_rd_w)
,.mem_i_flush_i(ifetch_flush_w)
,.mem_i_invalidate_i(ifetch_invalidate_w)
,.mem_i_pc_i(ifetch_pc_w)
,.mem_d_addr_i(dport_tcm_addr_w)
,.mem_d_data_wr_i(dport_tcm_data_wr_w)
,.mem_d_rd_i(dport_tcm_rd_w)
,.mem_d_wr_i(dport_tcm_wr_w)
,.mem_d_cacheable_i(dport_tcm_cacheable_w)
,.mem_d_req_tag_i(dport_tcm_req_tag_w)
,.mem_d_invalidate_i(dport_tcm_invalidate_w)
,.mem_d_writeback_i(dport_tcm_writeback_w)
,.mem_d_flush_i(dport_tcm_flush_w)
,.axi_awvalid_i(axi_t_awvalid_i)
,.axi_awaddr_i(axi_t_awaddr_i)
,.axi_awid_i(axi_t_awid_i)
,.axi_awlen_i(axi_t_awlen_i)
,.axi_awburst_i(axi_t_awburst_i)
,.axi_wvalid_i(axi_t_wvalid_i)
,.axi_wdata_i(axi_t_wdata_i)
,.axi_wstrb_i(axi_t_wstrb_i)
,.axi_wlast_i(axi_t_wlast_i)
,.axi_bready_i(axi_t_bready_i)
,.axi_arvalid_i(axi_t_arvalid_i)
,.axi_araddr_i(axi_t_araddr_i)
,.axi_arid_i(axi_t_arid_i)
,.axi_arlen_i(axi_t_arlen_i)
,.axi_arburst_i(axi_t_arburst_i)
,.axi_rready_i(axi_t_rready_i)
// Outputs
,.mem_i_accept_o(ifetch_accept_w)
,.mem_i_valid_o(ifetch_valid_w)
,.mem_i_error_o(ifetch_error_w)
,.mem_i_inst_o(ifetch_inst_w)
,.mem_d_data_rd_o(dport_tcm_data_rd_w)
,.mem_d_accept_o(dport_tcm_accept_w)
,.mem_d_ack_o(dport_tcm_ack_w)
,.mem_d_error_o(dport_tcm_error_w)
,.mem_d_resp_tag_o(dport_tcm_resp_tag_w)
,.axi_awready_o(axi_t_awready_o)
,.axi_wready_o(axi_t_wready_o)
,.axi_bvalid_o(axi_t_bvalid_o)
,.axi_bresp_o(axi_t_bresp_o)
,.axi_bid_o(axi_t_bid_o)
,.axi_arready_o(axi_t_arready_o)
,.axi_rvalid_o(axi_t_rvalid_o)
,.axi_rdata_o(axi_t_rdata_o)
,.axi_rresp_o(axi_t_rresp_o)
,.axi_rid_o(axi_t_rid_o)
,.axi_rlast_o(axi_t_rlast_o)
);
dport_axi
u_axi
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.mem_addr_i(dport_axi_addr_w)
,.mem_data_wr_i(dport_axi_data_wr_w)
,.mem_rd_i(dport_axi_rd_w)
,.mem_wr_i(dport_axi_wr_w)
,.mem_cacheable_i(dport_axi_cacheable_w)
,.mem_req_tag_i(dport_axi_req_tag_w)
,.mem_invalidate_i(dport_axi_invalidate_w)
,.mem_writeback_i(dport_axi_writeback_w)
,.mem_flush_i(dport_axi_flush_w)
,.axi_awready_i(axi_i_awready_i)
,.axi_wready_i(axi_i_wready_i)
,.axi_bvalid_i(axi_i_bvalid_i)
,.axi_bresp_i(axi_i_bresp_i)
,.axi_arready_i(axi_i_arready_i)
,.axi_rvalid_i(axi_i_rvalid_i)
,.axi_rdata_i(axi_i_rdata_i)
,.axi_rresp_i(axi_i_rresp_i)
// Outputs
,.mem_data_rd_o(dport_axi_data_rd_w)
,.mem_accept_o(dport_axi_accept_w)
,.mem_ack_o(dport_axi_ack_w)
,.mem_error_o(dport_axi_error_w)
,.mem_resp_tag_o(dport_axi_resp_tag_w)
,.axi_awvalid_o(axi_i_awvalid_o)
,.axi_awaddr_o(axi_i_awaddr_o)
,.axi_wvalid_o(axi_i_wvalid_o)
,.axi_wdata_o(axi_i_wdata_o)
,.axi_wstrb_o(axi_i_wstrb_o)
,.axi_bready_o(axi_i_bready_o)
,.axi_arvalid_o(axi_i_arvalid_o)
,.axi_araddr_o(axi_i_araddr_o)
,.axi_rready_o(axi_i_rready_o)
);
endmodule |
module riscv_mmu
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter MEM_CACHE_ADDR_MIN = 32'h80000000
,parameter MEM_CACHE_ADDR_MAX = 32'h8fffffff
,parameter SUPPORT_MMU = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 1:0] priv_d_i
,input sum_i
,input mxr_i
,input flush_i
,input [ 31:0] satp_i
,input fetch_in_rd_i
,input fetch_in_flush_i
,input fetch_in_invalidate_i
,input [ 31:0] fetch_in_pc_i
,input [ 1:0] fetch_in_priv_i
,input fetch_out_accept_i
,input fetch_out_valid_i
,input fetch_out_error_i
,input [ 31:0] fetch_out_inst_i
,input [ 31:0] lsu_in_addr_i
,input [ 31:0] lsu_in_data_wr_i
,input lsu_in_rd_i
,input [ 3:0] lsu_in_wr_i
,input lsu_in_cacheable_i
,input [ 10:0] lsu_in_req_tag_i
,input lsu_in_invalidate_i
,input lsu_in_writeback_i
,input lsu_in_flush_i
,input [ 31:0] lsu_out_data_rd_i
,input lsu_out_accept_i
,input lsu_out_ack_i
,input lsu_out_error_i
,input [ 10:0] lsu_out_resp_tag_i
// Outputs
,output fetch_in_accept_o
,output fetch_in_valid_o
,output fetch_in_error_o
,output [ 31:0] fetch_in_inst_o
,output fetch_out_rd_o
,output fetch_out_flush_o
,output fetch_out_invalidate_o
,output [ 31:0] fetch_out_pc_o
,output fetch_in_fault_o
,output [ 31:0] lsu_in_data_rd_o
,output lsu_in_accept_o
,output lsu_in_ack_o
,output lsu_in_error_o
,output [ 10:0] lsu_in_resp_tag_o
,output [ 31:0] lsu_out_addr_o
,output [ 31:0] lsu_out_data_wr_o
,output lsu_out_rd_o
,output [ 3:0] lsu_out_wr_o
,output lsu_out_cacheable_o
,output [ 10:0] lsu_out_req_tag_o
,output lsu_out_invalidate_o
,output lsu_out_writeback_o
,output lsu_out_flush_o
,output lsu_in_load_fault_o
,output lsu_in_store_fault_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Local defs
//-----------------------------------------------------------------
localparam STATE_W = 2;
localparam STATE_IDLE = 0;
localparam STATE_LEVEL_FIRST = 1;
localparam STATE_LEVEL_SECOND = 2;
localparam STATE_UPDATE = 3;
//-----------------------------------------------------------------
// Basic MMU support
//-----------------------------------------------------------------
generate
if (SUPPORT_MMU)
begin
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [STATE_W-1:0] state_q;
wire idle_w = (state_q == STATE_IDLE);
// Magic combo used only by MMU
wire resp_mmu_w = (lsu_out_resp_tag_i[9:7] == 3'b111);
wire resp_valid_w = resp_mmu_w & lsu_out_ack_i;
wire resp_error_w = resp_mmu_w & lsu_out_error_i;
wire [31:0] resp_data_w = lsu_out_data_rd_i;
wire cpu_accept_w;
//-----------------------------------------------------------------
// Load / Store
//-----------------------------------------------------------------
reg load_q;
reg [3:0] store_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
load_q <= 1'b0;
else if (lsu_in_rd_i)
load_q <= ~lsu_in_accept_o;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
store_q <= 4'b0;
else if (|lsu_in_wr_i)
store_q <= lsu_in_accept_o ? 4'b0 : lsu_in_wr_i;
wire load_w = lsu_in_rd_i | load_q;
wire [3:0] store_w = lsu_in_wr_i | store_q;
reg [31:0] lsu_in_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
lsu_in_addr_q <= 32'b0;
else if (load_w || (|store_w))
lsu_in_addr_q <= lsu_in_addr_i;
wire [31:0] lsu_addr_w = (load_w || (|store_w)) ? lsu_in_addr_i : lsu_in_addr_q;
//-----------------------------------------------------------------
// Page table walker
//-----------------------------------------------------------------
wire itlb_hit_w;
wire dtlb_hit_w;
reg dtlb_req_q;
// Global enable
wire vm_enable_w = satp_i[`SATP_MODE_R];
wire [31:0] ptbr_w = {satp_i[`SATP_PPN_R], 12'b0};
wire ifetch_vm_w = (fetch_in_priv_i != `PRIV_MACHINE);
wire dfetch_vm_w = (priv_d_i != `PRIV_MACHINE);
wire supervisor_i_w = (fetch_in_priv_i == `PRIV_SUPER);
wire supervisor_d_w = (priv_d_i == `PRIV_SUPER);
wire vm_i_enable_w = (ifetch_vm_w);
wire vm_d_enable_w = (vm_enable_w & dfetch_vm_w);
// TLB entry does not match request address
wire itlb_miss_w = fetch_in_rd_i & vm_i_enable_w & ~itlb_hit_w;
wire dtlb_miss_w = (load_w || (|store_w)) & vm_d_enable_w & ~dtlb_hit_w;
// Data miss is higher priority than instruction...
wire [31:0] request_addr_w = idle_w ?
(dtlb_miss_w ? lsu_addr_w : fetch_in_pc_i) :
dtlb_req_q ? lsu_addr_w : fetch_in_pc_i;
reg [31:0] pte_addr_q;
reg [31:0] pte_entry_q;
reg [31:0] virt_addr_q;
wire [31:0] pte_ppn_w = {`PAGE_PFN_SHIFT'b0, resp_data_w[31:`PAGE_PFN_SHIFT]};
wire [9:0] pte_flags_w = resp_data_w[9:0];
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
pte_addr_q <= 32'b0;
pte_entry_q <= 32'b0;
virt_addr_q <= 32'b0;
dtlb_req_q <= 1'b0;
state_q <= STATE_IDLE;
end
else
begin
// TLB miss, walk page table
if (state_q == STATE_IDLE && (itlb_miss_w || dtlb_miss_w))
begin
pte_addr_q <= ptbr_w + {20'b0, request_addr_w[31:22], 2'b0};
virt_addr_q <= request_addr_w;
dtlb_req_q <= dtlb_miss_w;
state_q <= STATE_LEVEL_FIRST;
end
// First level (4MB superpage)
else if (state_q == STATE_LEVEL_FIRST && resp_valid_w)
begin
// Error or page not present
if (resp_error_w || !resp_data_w[`PAGE_PRESENT])
begin
pte_entry_q <= 32'b0;
state_q <= STATE_UPDATE;
end
// Valid entry, but another level to fetch
else if (!(resp_data_w[`PAGE_READ] || resp_data_w[`PAGE_WRITE] || resp_data_w[`PAGE_EXEC]))
begin
pte_addr_q <= {resp_data_w[29:10], 12'b0} + {20'b0, request_addr_w[21:12], 2'b0};
state_q <= STATE_LEVEL_SECOND;
end
// Valid entry, actual valid PTE
else
begin
pte_entry_q <= ((pte_ppn_w | {22'b0, request_addr_w[21:12]}) << `MMU_PGSHIFT) | {22'b0, pte_flags_w};
state_q <= STATE_UPDATE;
end
end
// Second level (4KB page)
else if (state_q == STATE_LEVEL_SECOND && resp_valid_w)
begin
// Valid entry, final level
if (resp_data_w[`PAGE_PRESENT])
begin
pte_entry_q <= (pte_ppn_w << `MMU_PGSHIFT) | {22'b0, pte_flags_w};
state_q <= STATE_UPDATE;
end
// Page fault
else
begin
pte_entry_q <= 32'b0;
state_q <= STATE_UPDATE;
end
end
else if (state_q == STATE_UPDATE)
begin
state_q <= STATE_IDLE;
end
end
//-----------------------------------------------------------------
// IMMU TLB
//-----------------------------------------------------------------
reg itlb_valid_q;
reg [31:12] itlb_va_addr_q;
reg [31:0] itlb_entry_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
itlb_valid_q <= 1'b0;
else if (flush_i)
itlb_valid_q <= 1'b0;
else if (state_q == STATE_UPDATE && !dtlb_req_q)
itlb_valid_q <= (itlb_va_addr_q == fetch_in_pc_i[31:12]); // Fetch TLB still matches incoming request
else if (state_q != STATE_IDLE && !dtlb_req_q)
itlb_valid_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
itlb_va_addr_q <= 20'b0;
itlb_entry_q <= 32'b0;
end
else if (state_q == STATE_UPDATE && !dtlb_req_q)
begin
itlb_va_addr_q <= virt_addr_q[31:12];
itlb_entry_q <= pte_entry_q;
end
// TLB address matched (even on page fault)
assign itlb_hit_w = fetch_in_rd_i & itlb_valid_q & (itlb_va_addr_q == fetch_in_pc_i[31:12]);
reg pc_fault_r;
always @ *
begin
pc_fault_r = 1'b0;
if (vm_i_enable_w && itlb_hit_w)
begin
// Supervisor mode
if (supervisor_i_w)
begin
// User page, supervisor cannot execute
if (itlb_entry_q[`PAGE_USER])
pc_fault_r = 1'b1;
// Check exec permissions
else
pc_fault_r = ~itlb_entry_q[`PAGE_EXEC];
end
// User mode
else
pc_fault_r = (~itlb_entry_q[`PAGE_EXEC]) | (~itlb_entry_q[`PAGE_USER]);
end
end
reg pc_fault_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pc_fault_q <= 1'b0;
else
pc_fault_q <= pc_fault_r;
assign fetch_out_rd_o = (~vm_i_enable_w & fetch_in_rd_i) || (itlb_hit_w & ~pc_fault_r);
assign fetch_out_pc_o = vm_i_enable_w ? {itlb_entry_q[31:12], fetch_in_pc_i[11:0]} : fetch_in_pc_i;
assign fetch_out_flush_o = fetch_in_flush_i;
assign fetch_out_invalidate_o = fetch_in_invalidate_i; // TODO: ...
assign fetch_in_accept_o = (~vm_i_enable_w & fetch_out_accept_i) | (vm_i_enable_w & itlb_hit_w & fetch_out_accept_i) | pc_fault_r;
assign fetch_in_valid_o = fetch_out_valid_i | pc_fault_q;
assign fetch_in_error_o = fetch_out_valid_i & fetch_out_error_i;
assign fetch_in_fault_o = pc_fault_q;
assign fetch_in_inst_o = fetch_out_inst_i;
//-----------------------------------------------------------------
// DMMU TLB
//-----------------------------------------------------------------
reg dtlb_valid_q;
reg [31:12] dtlb_va_addr_q;
reg [31:0] dtlb_entry_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
dtlb_valid_q <= 1'b0;
else if (flush_i)
dtlb_valid_q <= 1'b0;
else if (state_q == STATE_UPDATE && dtlb_req_q)
dtlb_valid_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
dtlb_va_addr_q <= 20'b0;
dtlb_entry_q <= 32'b0;
end
else if (state_q == STATE_UPDATE && dtlb_req_q)
begin
dtlb_va_addr_q <= virt_addr_q[31:12];
dtlb_entry_q <= pte_entry_q;
end
// TLB address matched (even on page fault)
assign dtlb_hit_w = dtlb_valid_q & (dtlb_va_addr_q == lsu_addr_w[31:12]);
reg load_fault_r;
always @ *
begin
load_fault_r = 1'b0;
if (vm_d_enable_w && load_w && dtlb_hit_w)
begin
// Supervisor mode
if (supervisor_d_w)
begin
// User page, supervisor user mode not enabled
if (dtlb_entry_q[`PAGE_USER] && !sum_i)
load_fault_r = 1'b1;
// Check exec permissions
else
load_fault_r = ~(dtlb_entry_q[`PAGE_READ] | (mxr_i & dtlb_entry_q[`PAGE_EXEC]));
end
// User mode
else
load_fault_r = (~dtlb_entry_q[`PAGE_READ]) | (~dtlb_entry_q[`PAGE_USER]);
end
end
reg store_fault_r;
always @ *
begin
store_fault_r = 1'b0;
if (vm_d_enable_w && (|store_w) && dtlb_hit_w)
begin
// Supervisor mode
if (supervisor_d_w)
begin
// User page, supervisor user mode not enabled
if (dtlb_entry_q[`PAGE_USER] && !sum_i)
store_fault_r = 1'b1;
// Check exec permissions
else
store_fault_r = (~dtlb_entry_q[`PAGE_READ]) | (~dtlb_entry_q[`PAGE_WRITE]);
end
// User mode
else
store_fault_r = (~dtlb_entry_q[`PAGE_READ]) | (~dtlb_entry_q[`PAGE_WRITE]) | (~dtlb_entry_q[`PAGE_USER]);
end
end
reg store_fault_q;
reg load_fault_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
store_fault_q <= 1'b0;
else
store_fault_q <= store_fault_r;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
load_fault_q <= 1'b0;
else
load_fault_q <= load_fault_r;
wire lsu_out_rd_w = vm_d_enable_w ? (load_w & dtlb_hit_w & ~load_fault_r) : lsu_in_rd_i;
wire [3:0] lsu_out_wr_w = vm_d_enable_w ? (store_w & {4{dtlb_hit_w & ~store_fault_r}}) : lsu_in_wr_i;
wire [31:0] lsu_out_addr_w = vm_d_enable_w ? {dtlb_entry_q[31:12], lsu_addr_w[11:0]} : lsu_addr_w;
wire [31:0] lsu_out_data_wr_w = lsu_in_data_wr_i;
wire lsu_out_invalidate_w = lsu_in_invalidate_i;
wire lsu_out_writeback_w = lsu_in_writeback_i;
reg lsu_out_cacheable_r;
always @ *
begin
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
if (lsu_in_invalidate_i || lsu_in_writeback_i || lsu_in_flush_i)
lsu_out_cacheable_r = 1'b1;
else
lsu_out_cacheable_r = (lsu_out_addr_w >= MEM_CACHE_ADDR_MIN && lsu_out_addr_w <= MEM_CACHE_ADDR_MAX);
/* verilator lint_on CMPCONST */
/* verilator lint_on UNSIGNED */
end
wire [10:0] lsu_out_req_tag_w = lsu_in_req_tag_i;
wire lsu_out_flush_w = lsu_in_flush_i;
assign lsu_in_ack_o = (lsu_out_ack_i & ~resp_mmu_w) | store_fault_q | load_fault_q;
assign lsu_in_resp_tag_o = lsu_out_resp_tag_i;
assign lsu_in_error_o = (lsu_out_error_i & ~resp_mmu_w) | store_fault_q | load_fault_q;
assign lsu_in_data_rd_o = lsu_out_data_rd_i;
assign lsu_in_store_fault_o = store_fault_q;
assign lsu_in_load_fault_o = load_fault_q;
assign lsu_in_accept_o = (~vm_d_enable_w & cpu_accept_w) | (vm_d_enable_w & dtlb_hit_w & cpu_accept_w) | store_fault_r | load_fault_r;
//-----------------------------------------------------------------
// PTE Fetch Port
//-----------------------------------------------------------------
reg mem_req_q;
wire mmu_accept_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_req_q <= 1'b0;
else if (state_q == STATE_IDLE && (itlb_miss_w || dtlb_miss_w))
mem_req_q <= 1'b1;
else if (state_q == STATE_LEVEL_FIRST && resp_valid_w && !resp_error_w && resp_data_w[`PAGE_PRESENT] && (!(resp_data_w[`PAGE_READ] || resp_data_w[`PAGE_WRITE] || resp_data_w[`PAGE_EXEC])))
mem_req_q <= 1'b1;
else if (mmu_accept_w)
mem_req_q <= 1'b0;
//-----------------------------------------------------------------
// Request Muxing
//-----------------------------------------------------------------
reg read_hold_q;
reg src_mmu_q;
wire src_mmu_w = read_hold_q ? src_mmu_q : mem_req_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
read_hold_q <= 1'b0;
src_mmu_q <= 1'b0;
end
else if ((lsu_out_rd_o || (|lsu_out_wr_o)) && !lsu_out_accept_i)
begin
read_hold_q <= 1'b1;
src_mmu_q <= src_mmu_w;
end
else if (lsu_out_accept_i)
read_hold_q <= 1'b0;
assign mmu_accept_w = src_mmu_w & lsu_out_accept_i;
assign cpu_accept_w = ~src_mmu_w & lsu_out_accept_i;
assign lsu_out_rd_o = src_mmu_w ? mem_req_q : lsu_out_rd_w;
assign lsu_out_wr_o = src_mmu_w ? 4'b0 : lsu_out_wr_w;
assign lsu_out_addr_o = src_mmu_w ? pte_addr_q : lsu_out_addr_w;
assign lsu_out_data_wr_o = lsu_out_data_wr_w;
assign lsu_out_invalidate_o = src_mmu_w ? 1'b0 : lsu_out_invalidate_w;
assign lsu_out_writeback_o = src_mmu_w ? 1'b0 : lsu_out_writeback_w;
assign lsu_out_cacheable_o = src_mmu_w ? 1'b1 : lsu_out_cacheable_r;
assign lsu_out_req_tag_o = src_mmu_w ? {1'b0, 3'b111, 7'b0} : lsu_out_req_tag_w;
assign lsu_out_flush_o = src_mmu_w ? 1'b0 : lsu_out_flush_w;
end
//-----------------------------------------------------------------
// No MMU support
//-----------------------------------------------------------------
else
begin
assign fetch_out_rd_o = fetch_in_rd_i;
assign fetch_out_pc_o = fetch_in_pc_i;
assign fetch_out_flush_o = fetch_in_flush_i;
assign fetch_out_invalidate_o = fetch_in_invalidate_i;
assign fetch_in_accept_o = fetch_out_accept_i;
assign fetch_in_valid_o = fetch_out_valid_i;
assign fetch_in_error_o = fetch_out_error_i;
assign fetch_in_fault_o = 1'b0;
assign fetch_in_inst_o = fetch_out_inst_i;
assign lsu_out_rd_o = lsu_in_rd_i;
assign lsu_out_wr_o = lsu_in_wr_i;
assign lsu_out_addr_o = lsu_in_addr_i;
assign lsu_out_data_wr_o = lsu_in_data_wr_i;
assign lsu_out_invalidate_o = lsu_in_invalidate_i;
assign lsu_out_writeback_o = lsu_in_writeback_i;
assign lsu_out_cacheable_o = lsu_in_cacheable_i;
assign lsu_out_req_tag_o = lsu_in_req_tag_i;
assign lsu_out_flush_o = lsu_in_flush_i;
assign lsu_in_ack_o = lsu_out_ack_i;
assign lsu_in_resp_tag_o = lsu_out_resp_tag_i;
assign lsu_in_error_o = lsu_out_error_i;
assign lsu_in_data_rd_o = lsu_out_data_rd_i;
assign lsu_in_store_fault_o = 1'b0;
assign lsu_in_load_fault_o = 1'b0;
assign lsu_in_accept_o = lsu_out_accept_i;
end
endgenerate
endmodule |
module riscv_csr_regfile
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MTIMECMP = 1,
parameter SUPPORT_SUPER = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i
,input rst_i
,input ext_intr_i
,input timer_intr_i
,input [31:0] cpu_id_i
,input [31:0] misa_i
,input [5:0] exception_i
,input [31:0] exception_pc_i
,input [31:0] exception_addr_i
// CSR read port
,input csr_ren_i
,input [11:0] csr_raddr_i
,output [31:0] csr_rdata_o
// CSR write port
,input [11:0] csr_waddr_i
,input [31:0] csr_wdata_i
,output csr_branch_o
,output [31:0] csr_target_o
// CSR registers
,output [1:0] priv_o
,output [31:0] status_o
,output [31:0] satp_o
// Masked interrupt output
,output [31:0] interrupt_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
// CSR - Machine
reg [31:0] csr_mepc_q;
reg [31:0] csr_mcause_q;
reg [31:0] csr_sr_q;
reg [31:0] csr_mtvec_q;
reg [31:0] csr_mip_q;
reg [31:0] csr_mie_q;
reg [1:0] csr_mpriv_q;
reg [31:0] csr_mcycle_q;
reg [31:0] csr_mcycle_h_q;
reg [31:0] csr_mscratch_q;
reg [31:0] csr_mtval_q;
reg [31:0] csr_mtimecmp_q;
reg csr_mtime_ie_q;
reg [31:0] csr_medeleg_q;
reg [31:0] csr_mideleg_q;
// CSR - Supervisor
reg [31:0] csr_sepc_q;
reg [31:0] csr_stvec_q;
reg [31:0] csr_scause_q;
reg [31:0] csr_stval_q;
reg [31:0] csr_satp_q;
reg [31:0] csr_sscratch_q;
//-----------------------------------------------------------------
// Masked Interrupts
//-----------------------------------------------------------------
reg [31:0] irq_pending_r;
reg [31:0] irq_masked_r;
reg [1:0] irq_priv_r;
reg m_enabled_r;
reg [31:0] m_interrupts_r;
reg s_enabled_r;
reg [31:0] s_interrupts_r;
always @ *
begin
if (SUPPORT_SUPER)
begin
irq_pending_r = (csr_mip_q & csr_mie_q);
m_enabled_r = (csr_mpriv_q < `PRIV_MACHINE) || (csr_mpriv_q == `PRIV_MACHINE && csr_sr_q[`SR_MIE_R]);
s_enabled_r = (csr_mpriv_q < `PRIV_SUPER) || (csr_mpriv_q == `PRIV_SUPER && csr_sr_q[`SR_SIE_R]);
m_interrupts_r = m_enabled_r ? (irq_pending_r & ~csr_mideleg_q) : 32'b0;
s_interrupts_r = s_enabled_r ? (irq_pending_r & csr_mideleg_q) : 32'b0;
irq_masked_r = (|m_interrupts_r) ? m_interrupts_r : s_interrupts_r;
irq_priv_r = (|m_interrupts_r) ? `PRIV_MACHINE : `PRIV_SUPER;
end
else
begin
irq_pending_r = (csr_mip_q & csr_mie_q);
irq_masked_r = csr_sr_q[`SR_MIE_R] ? irq_pending_r : 32'b0;
irq_priv_r = `PRIV_MACHINE;
end
end
reg [1:0] irq_priv_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
irq_priv_q <= `PRIV_MACHINE;
else if (|irq_masked_r)
irq_priv_q <= irq_priv_r;
assign interrupt_o = irq_masked_r;
reg csr_mip_upd_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
csr_mip_upd_q <= 1'b0;
else if ((csr_ren_i && csr_raddr_i == `CSR_MIP) || (csr_ren_i && csr_raddr_i == `CSR_SIP))
csr_mip_upd_q <= 1'b1;
else if (csr_waddr_i == `CSR_MIP || csr_waddr_i == `CSR_SIP || (|exception_i))
csr_mip_upd_q <= 1'b0;
wire buffer_mip_w = (csr_ren_i && csr_raddr_i == `CSR_MIP) | (csr_ren_i && csr_raddr_i == `CSR_SIP) | csr_mip_upd_q;
//-----------------------------------------------------------------
// CSR Read Port
//-----------------------------------------------------------------
reg [31:0] rdata_r;
always @ *
begin
rdata_r = 32'b0;
case (csr_raddr_i)
// CSR - Machine
`CSR_MSCRATCH: rdata_r = csr_mscratch_q & `CSR_MSCRATCH_MASK;
`CSR_MEPC: rdata_r = csr_mepc_q & `CSR_MEPC_MASK;
`CSR_MTVEC: rdata_r = csr_mtvec_q & `CSR_MTVEC_MASK;
`CSR_MCAUSE: rdata_r = csr_mcause_q & `CSR_MCAUSE_MASK;
`CSR_MTVAL: rdata_r = csr_mtval_q & `CSR_MTVAL_MASK;
`CSR_MSTATUS: rdata_r = csr_sr_q & `CSR_MSTATUS_MASK;
`CSR_MIP: rdata_r = csr_mip_q & `CSR_MIP_MASK;
`CSR_MIE: rdata_r = csr_mie_q & `CSR_MIE_MASK;
`CSR_MCYCLE,
`CSR_MTIME: rdata_r = csr_mcycle_q;
`CSR_MTIMEH: rdata_r = csr_mcycle_h_q;
`CSR_MHARTID: rdata_r = cpu_id_i;
`CSR_MISA: rdata_r = misa_i;
`CSR_MEDELEG: rdata_r = SUPPORT_SUPER ? (csr_medeleg_q & `CSR_MEDELEG_MASK) : 32'b0;
`CSR_MIDELEG: rdata_r = SUPPORT_SUPER ? (csr_mideleg_q & `CSR_MIDELEG_MASK) : 32'b0;
// Non-std behaviour
`CSR_MTIMECMP: rdata_r = SUPPORT_MTIMECMP ? csr_mtimecmp_q : 32'b0;
// CSR - Super
`CSR_SSTATUS: rdata_r = SUPPORT_SUPER ? (csr_sr_q & `CSR_SSTATUS_MASK) : 32'b0;
`CSR_SIP: rdata_r = SUPPORT_SUPER ? (csr_mip_q & `CSR_SIP_MASK) : 32'b0;
`CSR_SIE: rdata_r = SUPPORT_SUPER ? (csr_mie_q & `CSR_SIE_MASK) : 32'b0;
`CSR_SEPC: rdata_r = SUPPORT_SUPER ? (csr_sepc_q & `CSR_SEPC_MASK) : 32'b0;
`CSR_STVEC: rdata_r = SUPPORT_SUPER ? (csr_stvec_q & `CSR_STVEC_MASK) : 32'b0;
`CSR_SCAUSE: rdata_r = SUPPORT_SUPER ? (csr_scause_q & `CSR_SCAUSE_MASK) : 32'b0;
`CSR_STVAL: rdata_r = SUPPORT_SUPER ? (csr_stval_q & `CSR_STVAL_MASK) : 32'b0;
`CSR_SATP: rdata_r = SUPPORT_SUPER ? (csr_satp_q & `CSR_SATP_MASK) : 32'b0;
`CSR_SSCRATCH: rdata_r = SUPPORT_SUPER ? (csr_sscratch_q & `CSR_SSCRATCH_MASK) : 32'b0;
default: rdata_r = 32'b0;
endcase
end
assign csr_rdata_o = rdata_r;
assign priv_o = csr_mpriv_q;
assign status_o = csr_sr_q;
assign satp_o = csr_satp_q;
//-----------------------------------------------------------------
// CSR register next state
//-----------------------------------------------------------------
// CSR - Machine
reg [31:0] csr_mepc_r;
reg [31:0] csr_mcause_r;
reg [31:0] csr_mtval_r;
reg [31:0] csr_sr_r;
reg [31:0] csr_mtvec_r;
reg [31:0] csr_mip_r;
reg [31:0] csr_mie_r;
reg [1:0] csr_mpriv_r;
reg [31:0] csr_mcycle_r;
reg [31:0] csr_mscratch_r;
reg [31:0] csr_mtimecmp_r;
reg csr_mtime_ie_r;
reg [31:0] csr_medeleg_r;
reg [31:0] csr_mideleg_r;
reg [31:0] csr_mip_next_q;
reg [31:0] csr_mip_next_r;
// CSR - Supervisor
reg [31:0] csr_sepc_r;
reg [31:0] csr_stvec_r;
reg [31:0] csr_scause_r;
reg [31:0] csr_stval_r;
reg [31:0] csr_satp_r;
reg [31:0] csr_sscratch_r;
wire is_exception_w = ((exception_i & `EXCEPTION_TYPE_MASK) == `EXCEPTION_EXCEPTION);
wire exception_s_w = SUPPORT_SUPER ? ((csr_mpriv_q <= `PRIV_SUPER) & is_exception_w & csr_medeleg_q[{1'b0, exception_i[`EXCEPTION_SUBTYPE_R]}]) : 1'b0;
always @ *
begin
// CSR - Machine
csr_mip_next_r = csr_mip_next_q;
csr_mepc_r = csr_mepc_q;
csr_sr_r = csr_sr_q;
csr_mcause_r = csr_mcause_q;
csr_mtval_r = csr_mtval_q;
csr_mtvec_r = csr_mtvec_q;
csr_mip_r = csr_mip_q;
csr_mie_r = csr_mie_q;
csr_mpriv_r = csr_mpriv_q;
csr_mscratch_r = csr_mscratch_q;
csr_mcycle_r = csr_mcycle_q + 32'd1;
csr_mtimecmp_r = csr_mtimecmp_q;
csr_mtime_ie_r = csr_mtime_ie_q;
csr_medeleg_r = csr_medeleg_q;
csr_mideleg_r = csr_mideleg_q;
// CSR - Super
csr_sepc_r = csr_sepc_q;
csr_stvec_r = csr_stvec_q;
csr_scause_r = csr_scause_q;
csr_stval_r = csr_stval_q;
csr_satp_r = csr_satp_q;
csr_sscratch_r = csr_sscratch_q;
// Interrupts
if ((exception_i & `EXCEPTION_TYPE_MASK) == `EXCEPTION_INTERRUPT)
begin
// Machine mode interrupts
if (irq_priv_q == `PRIV_MACHINE)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_MPIE_R] = csr_sr_r[`SR_MIE_R];
csr_sr_r[`SR_MPP_R] = csr_mpriv_q;
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_MIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_MACHINE;
// Record interrupt source PC
csr_mepc_r = exception_pc_i;
csr_mtval_r = 32'b0;
// Piority encoded interrupt cause
if (interrupt_o[`IRQ_M_SOFT])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_SOFT;
else if (interrupt_o[`IRQ_M_TIMER])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_TIMER;
else if (interrupt_o[`IRQ_M_EXT])
csr_mcause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_M_EXT;
end
// Supervisor mode interrupts
else
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_SPIE_R] = csr_sr_r[`SR_SIE_R];
csr_sr_r[`SR_SPP_R] = (csr_mpriv_q == `PRIV_SUPER);
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_SIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_SUPER;
// Record fault source PC
csr_sepc_r = exception_pc_i;
csr_stval_r = 32'b0;
// Piority encoded interrupt cause
if (interrupt_o[`IRQ_S_SOFT])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_SOFT;
else if (interrupt_o[`IRQ_S_TIMER])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_TIMER;
else if (interrupt_o[`IRQ_S_EXT])
csr_scause_r = `MCAUSE_INTERRUPT + 32'd`IRQ_S_EXT;
end
end
// Exception return
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
begin
// MRET (return from machine)
if (exception_i[1:0] == `PRIV_MACHINE)
begin
// Set privilege level to previous MPP
csr_mpriv_r = csr_sr_r[`SR_MPP_R];
// Interrupt enable pop
csr_sr_r[`SR_MIE_R] = csr_sr_r[`SR_MPIE_R];
csr_sr_r[`SR_MPIE_R] = 1'b1;
// TODO: Set next MPP to user mode??
csr_sr_r[`SR_MPP_R] = `SR_MPP_U;
end
// SRET (return from supervisor)
else
begin
// Set privilege level to previous privilege level
csr_mpriv_r = csr_sr_r[`SR_SPP_R] ? `PRIV_SUPER : `PRIV_USER;
// Interrupt enable pop
csr_sr_r[`SR_SIE_R] = csr_sr_r[`SR_SPIE_R];
csr_sr_r[`SR_SPIE_R] = 1'b1;
// Set next SPP to user mode
csr_sr_r[`SR_SPP_R] = 1'b0;
end
end
// Exception - handled in super mode
else if (is_exception_w && exception_s_w)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_SPIE_R] = csr_sr_r[`SR_SIE_R];
csr_sr_r[`SR_SPP_R] = (csr_mpriv_q == `PRIV_SUPER);
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_SIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_SUPER;
// Record fault source PC
csr_sepc_r = exception_pc_i;
// Bad address / PC
case (exception_i)
`EXCEPTION_MISALIGNED_FETCH,
`EXCEPTION_FAULT_FETCH,
`EXCEPTION_PAGE_FAULT_INST: csr_stval_r = exception_pc_i;
`EXCEPTION_ILLEGAL_INSTRUCTION,
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE: csr_stval_r = exception_addr_i;
default: csr_stval_r = 32'b0;
endcase
// Fault cause
csr_scause_r = {28'b0, exception_i[3:0]};
end
// Exception - handled in machine mode
else if (is_exception_w)
begin
// Save interrupt / supervisor state
csr_sr_r[`SR_MPIE_R] = csr_sr_r[`SR_MIE_R];
csr_sr_r[`SR_MPP_R] = csr_mpriv_q;
// Disable interrupts and enter supervisor mode
csr_sr_r[`SR_MIE_R] = 1'b0;
// Raise priviledge to machine level
csr_mpriv_r = `PRIV_MACHINE;
// Record fault source PC
csr_mepc_r = exception_pc_i;
// Bad address / PC
case (exception_i)
`EXCEPTION_MISALIGNED_FETCH,
`EXCEPTION_FAULT_FETCH,
`EXCEPTION_PAGE_FAULT_INST: csr_mtval_r = exception_pc_i;
`EXCEPTION_ILLEGAL_INSTRUCTION,
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE: csr_mtval_r = exception_addr_i;
default: csr_mtval_r = 32'b0;
endcase
// Fault cause
csr_mcause_r = {28'b0, exception_i[3:0]};
end
else
begin
case (csr_waddr_i)
// CSR - Machine
`CSR_MSCRATCH: csr_mscratch_r = csr_wdata_i & `CSR_MSCRATCH_MASK;
`CSR_MEPC: csr_mepc_r = csr_wdata_i & `CSR_MEPC_MASK;
`CSR_MTVEC: csr_mtvec_r = csr_wdata_i & `CSR_MTVEC_MASK;
`CSR_MCAUSE: csr_mcause_r = csr_wdata_i & `CSR_MCAUSE_MASK;
`CSR_MTVAL: csr_mtval_r = csr_wdata_i & `CSR_MTVAL_MASK;
`CSR_MSTATUS: csr_sr_r = csr_wdata_i & `CSR_MSTATUS_MASK;
`CSR_MIP: csr_mip_r = csr_wdata_i & `CSR_MIP_MASK;
`CSR_MIE: csr_mie_r = csr_wdata_i & `CSR_MIE_MASK;
`CSR_MEDELEG: csr_medeleg_r = csr_wdata_i & `CSR_MEDELEG_MASK;
`CSR_MIDELEG: csr_mideleg_r = csr_wdata_i & `CSR_MIDELEG_MASK;
// Non-std behaviour
`CSR_MTIMECMP:
begin
csr_mtimecmp_r = csr_wdata_i & `CSR_MTIMECMP_MASK;
csr_mtime_ie_r = 1'b1;
end
// CSR - Super
`CSR_SEPC: csr_sepc_r = csr_wdata_i & `CSR_SEPC_MASK;
`CSR_STVEC: csr_stvec_r = csr_wdata_i & `CSR_STVEC_MASK;
`CSR_SCAUSE: csr_scause_r = csr_wdata_i & `CSR_SCAUSE_MASK;
`CSR_STVAL: csr_stval_r = csr_wdata_i & `CSR_STVAL_MASK;
`CSR_SATP: csr_satp_r = csr_wdata_i & `CSR_SATP_MASK;
`CSR_SSCRATCH: csr_sscratch_r = csr_wdata_i & `CSR_SSCRATCH_MASK;
`CSR_SSTATUS: csr_sr_r = (csr_sr_r & ~`CSR_SSTATUS_MASK) | (csr_wdata_i & `CSR_SSTATUS_MASK);
`CSR_SIP: csr_mip_r = (csr_mip_r & ~`CSR_SIP_MASK) | (csr_wdata_i & `CSR_SIP_MASK);
`CSR_SIE: csr_mie_r = (csr_mie_r & ~`CSR_SIE_MASK) | (csr_wdata_i & `CSR_SIE_MASK);
default:
;
endcase
end
// External interrupts
// NOTE: If the machine level interrupts are delegated to supervisor, route the interrupts there instead..
if (ext_intr_i && csr_mideleg_q[`SR_IP_MEIP_R]) csr_mip_next_r[`SR_IP_SEIP_R] = 1'b1;
if (ext_intr_i && ~csr_mideleg_q[`SR_IP_MEIP_R]) csr_mip_next_r[`SR_IP_MEIP_R] = 1'b1;
if (timer_intr_i && csr_mideleg_q[`SR_IP_MTIP_R]) csr_mip_next_r[`SR_IP_STIP_R] = 1'b1;
if (timer_intr_i && ~csr_mideleg_q[`SR_IP_MTIP_R]) csr_mip_next_r[`SR_IP_MTIP_R] = 1'b1;
// Optional: Internal timer compare interrupt
if (SUPPORT_MTIMECMP && csr_mcycle_q == csr_mtimecmp_q)
begin
if (csr_mideleg_q[`SR_IP_MTIP_R])
csr_mip_next_r[`SR_IP_STIP_R] = csr_mtime_ie_q;
else
csr_mip_next_r[`SR_IP_MTIP_R] = csr_mtime_ie_q;
csr_mtime_ie_r = 1'b0;
end
csr_mip_r = csr_mip_r | csr_mip_next_r;
end
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
`ifdef verilator
`define HAS_SIM_CTRL
`endif
`ifdef verilog_sim
`define HAS_SIM_CTRL
`endif
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
// CSR - Machine
csr_mepc_q <= 32'b0;
csr_sr_q <= 32'b0;
csr_mcause_q <= 32'b0;
csr_mtval_q <= 32'b0;
csr_mtvec_q <= 32'b0;
csr_mip_q <= 32'b0;
csr_mie_q <= 32'b0;
csr_mpriv_q <= `PRIV_MACHINE;
csr_mcycle_q <= 32'b0;
csr_mcycle_h_q <= 32'b0;
csr_mscratch_q <= 32'b0;
csr_mtimecmp_q <= 32'b0;
csr_mtime_ie_q <= 1'b0;
csr_medeleg_q <= 32'b0;
csr_mideleg_q <= 32'b0;
// CSR - Super
csr_sepc_q <= 32'b0;
csr_stvec_q <= 32'b0;
csr_scause_q <= 32'b0;
csr_stval_q <= 32'b0;
csr_satp_q <= 32'b0;
csr_sscratch_q <= 32'b0;
csr_mip_next_q <= 32'b0;
end
else
begin
// CSR - Machine
csr_mepc_q <= csr_mepc_r;
csr_sr_q <= csr_sr_r;
csr_mcause_q <= csr_mcause_r;
csr_mtval_q <= csr_mtval_r;
csr_mtvec_q <= csr_mtvec_r;
csr_mip_q <= csr_mip_r;
csr_mie_q <= csr_mie_r;
csr_mpriv_q <= SUPPORT_SUPER ? csr_mpriv_r : `PRIV_MACHINE;
csr_mcycle_q <= csr_mcycle_r;
csr_mscratch_q <= csr_mscratch_r;
csr_mtimecmp_q <= SUPPORT_MTIMECMP ? csr_mtimecmp_r : 32'b0;
csr_mtime_ie_q <= SUPPORT_MTIMECMP ? csr_mtime_ie_r : 1'b0;
csr_medeleg_q <= SUPPORT_SUPER ? (csr_medeleg_r & `CSR_MEDELEG_MASK) : 32'b0;
csr_mideleg_q <= SUPPORT_SUPER ? (csr_mideleg_r & `CSR_MIDELEG_MASK) : 32'b0;
// CSR - Super
csr_sepc_q <= SUPPORT_SUPER ? (csr_sepc_r & `CSR_SEPC_MASK) : 32'b0;
csr_stvec_q <= SUPPORT_SUPER ? (csr_stvec_r & `CSR_STVEC_MASK) : 32'b0;
csr_scause_q <= SUPPORT_SUPER ? (csr_scause_r & `CSR_SCAUSE_MASK) : 32'b0;
csr_stval_q <= SUPPORT_SUPER ? (csr_stval_r & `CSR_STVAL_MASK) : 32'b0;
csr_satp_q <= SUPPORT_SUPER ? (csr_satp_r & `CSR_SATP_MASK) : 32'b0;
csr_sscratch_q <= SUPPORT_SUPER ? (csr_sscratch_r & `CSR_SSCRATCH_MASK) : 32'b0;
csr_mip_next_q <= buffer_mip_w ? csr_mip_next_r : 32'b0;
// Increment upper cycle counter on lower 32-bit overflow
if (csr_mcycle_q == 32'hFFFFFFFF)
csr_mcycle_h_q <= csr_mcycle_h_q + 32'd1;
`ifdef HAS_SIM_CTRL
// CSR SIM_CTRL (or DSCRATCH)
if ((csr_waddr_i == `CSR_DSCRATCH || csr_waddr_i == `CSR_SIM_CTRL) && ~(|exception_i))
begin
case (csr_wdata_i & 32'hFF000000)
`CSR_SIM_CTRL_EXIT:
begin
//exit(csr_wdata_i[7:0]);
$finish;
$finish;
end
`CSR_SIM_CTRL_PUTC:
begin
$write("%c", csr_wdata_i[7:0]);
end
endcase
end
`endif
end
//-----------------------------------------------------------------
// CSR branch
//-----------------------------------------------------------------
reg branch_r;
reg [31:0] branch_target_r;
always @ *
begin
branch_r = 1'b0;
branch_target_r = 32'b0;
// Interrupts
if (exception_i == `EXCEPTION_INTERRUPT)
begin
branch_r = 1'b1;
branch_target_r = (irq_priv_q == `PRIV_MACHINE) ? csr_mtvec_q : csr_stvec_q;
end
// Exception return
else if (exception_i >= `EXCEPTION_ERET_U && exception_i <= `EXCEPTION_ERET_M)
begin
// MRET (return from machine)
if (exception_i[1:0] == `PRIV_MACHINE)
begin
branch_r = 1'b1;
branch_target_r = csr_mepc_q;
end
// SRET (return from supervisor)
else
begin
branch_r = 1'b1;
branch_target_r = csr_sepc_q;
end
end
// Exception - handled in super mode
else if (is_exception_w && exception_s_w)
begin
branch_r = 1'b1;
branch_target_r = csr_stvec_q;
end
// Exception - handled in machine mode
else if (is_exception_w)
begin
branch_r = 1'b1;
branch_target_r = csr_mtvec_q;
end
// Fence / SATP register writes cause pipeline flushes
else if (exception_i == `EXCEPTION_FENCE)
begin
branch_r = 1'b1;
branch_target_r = exception_pc_i + 32'd4;
end
end
assign csr_branch_o = branch_r;
assign csr_target_o = branch_target_r;
`ifdef verilator
function [31:0] get_mcycle; /*verilator public*/
begin
get_mcycle = csr_mcycle_q;
end
endfunction
`endif
endmodule |
module riscv_exec
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input hold_i
// Outputs
,output branch_request_o
,output branch_is_taken_o
,output branch_is_not_taken_o
,output [ 31:0] branch_source_o
,output branch_is_call_o
,output branch_is_ret_o
,output branch_is_jmp_o
,output [ 31:0] branch_pc_o
,output branch_d_request_o
,output [ 31:0] branch_d_pc_o
,output [ 1:0] branch_d_priv_o
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-------------------------------------------------------------
// Opcode decode
//-------------------------------------------------------------
reg [31:0] imm20_r;
reg [31:0] imm12_r;
reg [31:0] bimm_r;
reg [31:0] jimm20_r;
reg [4:0] shamt_r;
always @ *
begin
imm20_r = {opcode_opcode_i[31:12], 12'b0};
imm12_r = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
bimm_r = {{19{opcode_opcode_i[31]}}, opcode_opcode_i[31], opcode_opcode_i[7], opcode_opcode_i[30:25], opcode_opcode_i[11:8], 1'b0};
jimm20_r = {{12{opcode_opcode_i[31]}}, opcode_opcode_i[19:12], opcode_opcode_i[20], opcode_opcode_i[30:25], opcode_opcode_i[24:21], 1'b0};
shamt_r = opcode_opcode_i[24:20];
end
//-------------------------------------------------------------
// Execute - ALU operations
//-------------------------------------------------------------
reg [3:0] alu_func_r;
reg [31:0] alu_input_a_r;
reg [31:0] alu_input_b_r;
always @ *
begin
alu_func_r = `ALU_NONE;
alu_input_a_r = 32'b0;
alu_input_b_r = 32'b0;
if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD) // add
begin
alu_func_r = `ALU_ADD;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND) // and
begin
alu_func_r = `ALU_AND;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_OR_MASK) == `INST_OR) // or
begin
alu_func_r = `ALU_OR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SLL_MASK) == `INST_SLL) // sll
begin
alu_func_r = `ALU_SHIFTL;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SRA_MASK) == `INST_SRA) // sra
begin
alu_func_r = `ALU_SHIFTR_ARITH;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SRL_MASK) == `INST_SRL) // srl
begin
alu_func_r = `ALU_SHIFTR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SUB_MASK) == `INST_SUB) // sub
begin
alu_func_r = `ALU_SUB;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_XOR_MASK) == `INST_XOR) // xor
begin
alu_func_r = `ALU_XOR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SLT_MASK) == `INST_SLT) // slt
begin
alu_func_r = `ALU_LESS_THAN_SIGNED;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_SLTU_MASK) == `INST_SLTU) // sltu
begin
alu_func_r = `ALU_LESS_THAN;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = opcode_rb_operand_i;
end
else if ((opcode_opcode_i & `INST_ADDI_MASK) == `INST_ADDI) // addi
begin
alu_func_r = `ALU_ADD;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_ANDI_MASK) == `INST_ANDI) // andi
begin
alu_func_r = `ALU_AND;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_SLTI_MASK) == `INST_SLTI) // slti
begin
alu_func_r = `ALU_LESS_THAN_SIGNED;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU) // sltiu
begin
alu_func_r = `ALU_LESS_THAN;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_ORI_MASK) == `INST_ORI) // ori
begin
alu_func_r = `ALU_OR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_XORI_MASK) == `INST_XORI) // xori
begin
alu_func_r = `ALU_XOR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = imm12_r;
end
else if ((opcode_opcode_i & `INST_SLLI_MASK) == `INST_SLLI) // slli
begin
alu_func_r = `ALU_SHIFTL;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = {27'b0, shamt_r};
end
else if ((opcode_opcode_i & `INST_SRLI_MASK) == `INST_SRLI) // srli
begin
alu_func_r = `ALU_SHIFTR;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = {27'b0, shamt_r};
end
else if ((opcode_opcode_i & `INST_SRAI_MASK) == `INST_SRAI) // srai
begin
alu_func_r = `ALU_SHIFTR_ARITH;
alu_input_a_r = opcode_ra_operand_i;
alu_input_b_r = {27'b0, shamt_r};
end
else if ((opcode_opcode_i & `INST_LUI_MASK) == `INST_LUI) // lui
begin
alu_input_a_r = imm20_r;
end
else if ((opcode_opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC) // auipc
begin
alu_func_r = `ALU_ADD;
alu_input_a_r = opcode_pc_i;
alu_input_b_r = imm20_r;
end
else if (((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL) || ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR)) // jal, jalr
begin
alu_func_r = `ALU_ADD;
alu_input_a_r = opcode_pc_i;
alu_input_b_r = 32'd4;
end
end
//-------------------------------------------------------------
// ALU
//-------------------------------------------------------------
wire [31:0] alu_p_w;
riscv_alu
u_alu
(
.alu_op_i(alu_func_r),
.alu_a_i(alu_input_a_r),
.alu_b_i(alu_input_b_r),
.alu_p_o(alu_p_w)
);
//-------------------------------------------------------------
// Flop ALU output
//-------------------------------------------------------------
reg [31:0] result_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
result_q <= 32'b0;
else if (~hold_i)
result_q <= alu_p_w;
assign writeback_value_o = result_q;
//-----------------------------------------------------------------
// less_than_signed: Less than operator (signed)
// Inputs: x = left operand, y = right operand
// Return: (int)x < (int)y
//-----------------------------------------------------------------
function [0:0] less_than_signed;
input [31:0] x;
input [31:0] y;
reg [31:0] v;
begin
v = (x - y);
if (x[31] != y[31])
less_than_signed = x[31];
else
less_than_signed = v[31];
end
endfunction
//-----------------------------------------------------------------
// greater_than_signed: Greater than operator (signed)
// Inputs: x = left operand, y = right operand
// Return: (int)x > (int)y
//-----------------------------------------------------------------
function [0:0] greater_than_signed;
input [31:0] x;
input [31:0] y;
reg [31:0] v;
begin
v = (y - x);
if (x[31] != y[31])
greater_than_signed = y[31];
else
greater_than_signed = v[31];
end
endfunction
//-------------------------------------------------------------
// Execute - Branch operations
//-------------------------------------------------------------
reg branch_r;
reg branch_taken_r;
reg [31:0] branch_target_r;
reg branch_call_r;
reg branch_ret_r;
reg branch_jmp_r;
always @ *
begin
branch_r = 1'b0;
branch_taken_r = 1'b0;
branch_call_r = 1'b0;
branch_ret_r = 1'b0;
branch_jmp_r = 1'b0;
// Default branch_r target is relative to current PC
branch_target_r = opcode_pc_i + bimm_r;
if ((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL) // jal
begin
branch_r = 1'b1;
branch_taken_r = 1'b1;
branch_target_r = opcode_pc_i + jimm20_r;
branch_call_r = (opcode_rd_idx_i == 5'd1); // RA
branch_jmp_r = 1'b1;
end
else if ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR) // jalr
begin
branch_r = 1'b1;
branch_taken_r = 1'b1;
branch_target_r = opcode_ra_operand_i + imm12_r;
branch_target_r[0] = 1'b0;
branch_ret_r = (opcode_ra_idx_i == 5'd1 && imm12_r[11:0] == 12'b0); // RA
branch_call_r = ~branch_ret_r && (opcode_rd_idx_i == 5'd1); // RA
branch_jmp_r = ~(branch_call_r | branch_ret_r);
end
else if ((opcode_opcode_i & `INST_BEQ_MASK) == `INST_BEQ) // beq
begin
branch_r = 1'b1;
branch_taken_r= (opcode_ra_operand_i == opcode_rb_operand_i);
end
else if ((opcode_opcode_i & `INST_BNE_MASK) == `INST_BNE) // bne
begin
branch_r = 1'b1;
branch_taken_r= (opcode_ra_operand_i != opcode_rb_operand_i);
end
else if ((opcode_opcode_i & `INST_BLT_MASK) == `INST_BLT) // blt
begin
branch_r = 1'b1;
branch_taken_r= less_than_signed(opcode_ra_operand_i, opcode_rb_operand_i);
end
else if ((opcode_opcode_i & `INST_BGE_MASK) == `INST_BGE) // bge
begin
branch_r = 1'b1;
branch_taken_r= greater_than_signed(opcode_ra_operand_i,opcode_rb_operand_i) | (opcode_ra_operand_i == opcode_rb_operand_i);
end
else if ((opcode_opcode_i & `INST_BLTU_MASK) == `INST_BLTU) // bltu
begin
branch_r = 1'b1;
branch_taken_r= (opcode_ra_operand_i < opcode_rb_operand_i);
end
else if ((opcode_opcode_i & `INST_BGEU_MASK) == `INST_BGEU) // bgeu
begin
branch_r = 1'b1;
branch_taken_r= (opcode_ra_operand_i >= opcode_rb_operand_i);
end
end
reg branch_taken_q;
reg branch_ntaken_q;
reg [31:0] pc_x_q;
reg [31:0] pc_m_q;
reg branch_call_q;
reg branch_ret_q;
reg branch_jmp_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
branch_taken_q <= 1'b0;
branch_ntaken_q <= 1'b0;
pc_x_q <= 32'b0;
pc_m_q <= 32'b0;
branch_call_q <= 1'b0;
branch_ret_q <= 1'b0;
branch_jmp_q <= 1'b0;
end
else if (opcode_valid_i)
begin
branch_taken_q <= branch_r && opcode_valid_i & branch_taken_r;
branch_ntaken_q <= branch_r && opcode_valid_i & ~branch_taken_r;
pc_x_q <= branch_taken_r ? branch_target_r : opcode_pc_i + 32'd4;
branch_call_q <= branch_r && opcode_valid_i && branch_call_r;
branch_ret_q <= branch_r && opcode_valid_i && branch_ret_r;
branch_jmp_q <= branch_r && opcode_valid_i && branch_jmp_r;
pc_m_q <= opcode_pc_i;
end
assign branch_request_o = branch_taken_q | branch_ntaken_q;
assign branch_is_taken_o = branch_taken_q;
assign branch_is_not_taken_o = branch_ntaken_q;
assign branch_source_o = pc_m_q;
assign branch_pc_o = pc_x_q;
assign branch_is_call_o = branch_call_q;
assign branch_is_ret_o = branch_ret_q;
assign branch_is_jmp_o = branch_jmp_q;
assign branch_d_request_o = (branch_r && opcode_valid_i && branch_taken_r);
assign branch_d_pc_o = branch_target_r;
assign branch_d_priv_o = 2'b0; // don't care
endmodule |
module riscv_trace_sim
(
input valid_i
,input [31:0] pc_i
,input [31:0] opcode_i
);
//-----------------------------------------------------------------
// get_regname_str: Convert register number to string
//-----------------------------------------------------------------
`ifdef verilator
function [79:0] get_regname_str;
input [4:0] regnum;
begin
case (regnum)
5'd0: get_regname_str = "zero";
5'd1: get_regname_str = "ra";
5'd2: get_regname_str = "sp";
5'd3: get_regname_str = "gp";
5'd4: get_regname_str = "tp";
5'd5: get_regname_str = "t0";
5'd6: get_regname_str = "t1";
5'd7: get_regname_str = "t2";
5'd8: get_regname_str = "s0";
5'd9: get_regname_str = "s1";
5'd10: get_regname_str = "a0";
5'd11: get_regname_str = "a1";
5'd12: get_regname_str = "a2";
5'd13: get_regname_str = "a3";
5'd14: get_regname_str = "a4";
5'd15: get_regname_str = "a5";
5'd16: get_regname_str = "a6";
5'd17: get_regname_str = "a7";
5'd18: get_regname_str = "s2";
5'd19: get_regname_str = "s3";
5'd20: get_regname_str = "s4";
5'd21: get_regname_str = "s5";
5'd22: get_regname_str = "s6";
5'd23: get_regname_str = "s7";
5'd24: get_regname_str = "s8";
5'd25: get_regname_str = "s9";
5'd26: get_regname_str = "s10";
5'd27: get_regname_str = "s11";
5'd28: get_regname_str = "t3";
5'd29: get_regname_str = "t4";
5'd30: get_regname_str = "t5";
5'd31: get_regname_str = "t6";
endcase
end
endfunction
//-------------------------------------------------------------------
// Debug strings
//-------------------------------------------------------------------
reg [79:0] dbg_inst_str;
reg [79:0] dbg_inst_ra;
reg [79:0] dbg_inst_rb;
reg [79:0] dbg_inst_rd;
reg [31:0] dbg_inst_imm;
reg [31:0] dbg_inst_pc;
wire [4:0] ra_idx_w = opcode_i[19:15];
wire [4:0] rb_idx_w = opcode_i[24:20];
wire [4:0] rd_idx_w = opcode_i[11:7];
`define DBG_IMM_IMM20 {opcode_i[31:12], 12'b0}
`define DBG_IMM_IMM12 {{20{opcode_i[31]}}, opcode_i[31:20]}
`define DBG_IMM_BIMM {{19{opcode_i[31]}}, opcode_i[31], opcode_i[7], opcode_i[30:25], opcode_i[11:8], 1'b0}
`define DBG_IMM_JIMM20 {{12{opcode_i[31]}}, opcode_i[19:12], opcode_i[20], opcode_i[30:25], opcode_i[24:21], 1'b0}
`define DBG_IMM_STOREIMM {{20{opcode_i[31]}}, opcode_i[31:25], opcode_i[11:7]}
`define DBG_IMM_SHAMT opcode_i[24:20]
always @ *
begin
dbg_inst_str = "-";
dbg_inst_ra = "-";
dbg_inst_rb = "-";
dbg_inst_rd = "-";
dbg_inst_pc = 32'bx;
if (valid_i)
begin
dbg_inst_pc = pc_i;
dbg_inst_ra = get_regname_str(ra_idx_w);
dbg_inst_rb = get_regname_str(rb_idx_w);
dbg_inst_rd = get_regname_str(rd_idx_w);
case (1'b1)
((opcode_i & `INST_ANDI_MASK) == `INST_ANDI) : dbg_inst_str = "andi";
((opcode_i & `INST_ADDI_MASK) == `INST_ADDI) : dbg_inst_str = "addi";
((opcode_i & `INST_SLTI_MASK) == `INST_SLTI) : dbg_inst_str = "slti";
((opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU) : dbg_inst_str = "sltiu";
((opcode_i & `INST_ORI_MASK) == `INST_ORI) : dbg_inst_str = "ori";
((opcode_i & `INST_XORI_MASK) == `INST_XORI) : dbg_inst_str = "xori";
((opcode_i & `INST_SLLI_MASK) == `INST_SLLI) : dbg_inst_str = "slli";
((opcode_i & `INST_SRLI_MASK) == `INST_SRLI) : dbg_inst_str = "srli";
((opcode_i & `INST_SRAI_MASK) == `INST_SRAI) : dbg_inst_str = "srai";
((opcode_i & `INST_LUI_MASK) == `INST_LUI) : dbg_inst_str = "lui";
((opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC) : dbg_inst_str = "auipc";
((opcode_i & `INST_ADD_MASK) == `INST_ADD) : dbg_inst_str = "add";
((opcode_i & `INST_SUB_MASK) == `INST_SUB) : dbg_inst_str = "sub";
((opcode_i & `INST_SLT_MASK) == `INST_SLT) : dbg_inst_str = "slt";
((opcode_i & `INST_SLTU_MASK) == `INST_SLTU) : dbg_inst_str = "sltu";
((opcode_i & `INST_XOR_MASK) == `INST_XOR) : dbg_inst_str = "xor";
((opcode_i & `INST_OR_MASK) == `INST_OR) : dbg_inst_str = "or";
((opcode_i & `INST_AND_MASK) == `INST_AND) : dbg_inst_str = "and";
((opcode_i & `INST_SLL_MASK) == `INST_SLL) : dbg_inst_str = "sll";
((opcode_i & `INST_SRL_MASK) == `INST_SRL) : dbg_inst_str = "srl";
((opcode_i & `INST_SRA_MASK) == `INST_SRA) : dbg_inst_str = "sra";
((opcode_i & `INST_JAL_MASK) == `INST_JAL) : dbg_inst_str = "jal";
((opcode_i & `INST_JALR_MASK) == `INST_JALR) : dbg_inst_str = "jalr";
((opcode_i & `INST_BEQ_MASK) == `INST_BEQ) : dbg_inst_str = "beq";
((opcode_i & `INST_BNE_MASK) == `INST_BNE) : dbg_inst_str = "bne";
((opcode_i & `INST_BLT_MASK) == `INST_BLT) : dbg_inst_str = "blt";
((opcode_i & `INST_BGE_MASK) == `INST_BGE) : dbg_inst_str = "bge";
((opcode_i & `INST_BLTU_MASK) == `INST_BLTU) : dbg_inst_str = "bltu";
((opcode_i & `INST_BGEU_MASK) == `INST_BGEU) : dbg_inst_str = "bgeu";
((opcode_i & `INST_LB_MASK) == `INST_LB) : dbg_inst_str = "lb";
((opcode_i & `INST_LH_MASK) == `INST_LH) : dbg_inst_str = "lh";
((opcode_i & `INST_LW_MASK) == `INST_LW) : dbg_inst_str = "lw";
((opcode_i & `INST_LBU_MASK) == `INST_LBU) : dbg_inst_str = "lbu";
((opcode_i & `INST_LHU_MASK) == `INST_LHU) : dbg_inst_str = "lhu";
((opcode_i & `INST_LWU_MASK) == `INST_LWU) : dbg_inst_str = "lwu";
((opcode_i & `INST_SB_MASK) == `INST_SB) : dbg_inst_str = "sb";
((opcode_i & `INST_SH_MASK) == `INST_SH) : dbg_inst_str = "sh";
((opcode_i & `INST_SW_MASK) == `INST_SW) : dbg_inst_str = "sw";
((opcode_i & `INST_ECALL_MASK) == `INST_ECALL) : dbg_inst_str = "ecall";
((opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK) : dbg_inst_str = "ebreak";
((opcode_i & `INST_ERET_MASK) == `INST_ERET) : dbg_inst_str = "eret";
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) : dbg_inst_str = "csrrw";
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) : dbg_inst_str = "csrrs";
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) : dbg_inst_str = "csrrc";
((opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI) : dbg_inst_str = "csrrwi";
((opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI) : dbg_inst_str = "csrrsi";
((opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI) : dbg_inst_str = "csrrci";
((opcode_i & `INST_MUL_MASK) == `INST_MUL) : dbg_inst_str = "mul";
((opcode_i & `INST_MULH_MASK) == `INST_MULH) : dbg_inst_str = "mulh";
((opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) : dbg_inst_str = "mulhsu";
((opcode_i & `INST_MULHU_MASK) == `INST_MULHU) : dbg_inst_str = "mulhu";
((opcode_i & `INST_DIV_MASK) == `INST_DIV) : dbg_inst_str = "div";
((opcode_i & `INST_DIVU_MASK) == `INST_DIVU) : dbg_inst_str = "divu";
((opcode_i & `INST_REM_MASK) == `INST_REM) : dbg_inst_str = "rem";
((opcode_i & `INST_REMU_MASK) == `INST_REMU) : dbg_inst_str = "remu";
((opcode_i & `INST_IFENCE_MASK) == `INST_IFENCE) : dbg_inst_str = "fence.i";
endcase
case (1'b1)
((opcode_i & `INST_ADDI_MASK) == `INST_ADDI) , // addi
((opcode_i & `INST_ANDI_MASK) == `INST_ANDI) , // andi
((opcode_i & `INST_SLTI_MASK) == `INST_SLTI) , // slti
((opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU) , // sltiu
((opcode_i & `INST_ORI_MASK) == `INST_ORI) , // ori
((opcode_i & `INST_XORI_MASK) == `INST_XORI) , // xori
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) , // csrrw
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) , // csrrs
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) , // csrrc
((opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI) ,// csrrwi
((opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI) ,// csrrsi
((opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI) :// csrrci
begin
dbg_inst_rb = "-";
dbg_inst_imm = `DBG_IMM_IMM12;
end
((opcode_i & `INST_SLLI_MASK) == `INST_SLLI) , // slli
((opcode_i & `INST_SRLI_MASK) == `INST_SRLI) , // srli
((opcode_i & `INST_SRAI_MASK) == `INST_SRAI) : // srai
begin
dbg_inst_rb = "-";
dbg_inst_imm = {27'b0, `DBG_IMM_SHAMT};
end
((opcode_i & `INST_LUI_MASK) == `INST_LUI) : // lui
begin
dbg_inst_ra = "-";
dbg_inst_rb = "-";
dbg_inst_imm = `DBG_IMM_IMM20;
end
((opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC) : // auipc
begin
dbg_inst_ra = "pc";
dbg_inst_rb = "-";
dbg_inst_imm = `DBG_IMM_IMM20;
end
((opcode_i & `INST_JAL_MASK) == `INST_JAL) : // jal
begin
dbg_inst_ra = "-";
dbg_inst_rb = "-";
dbg_inst_imm = pc_i + `DBG_IMM_JIMM20;
if (rd_idx_w == 5'd1)
dbg_inst_str = "call";
end
((opcode_i & `INST_JALR_MASK) == `INST_JALR) : // jalr
begin
dbg_inst_rb = "-";
dbg_inst_imm = `DBG_IMM_IMM12;
if (ra_idx_w == 5'd1 && `DBG_IMM_IMM12 == 32'b0)
dbg_inst_str = "ret";
else if (rd_idx_w == 5'd1)
dbg_inst_str = "call (R)";
end
// lb lh lw lbu lhu lwu
((opcode_i & `INST_LB_MASK) == `INST_LB) ,
((opcode_i & `INST_LH_MASK) == `INST_LH) ,
((opcode_i & `INST_LW_MASK) == `INST_LW) ,
((opcode_i & `INST_LBU_MASK) == `INST_LBU) ,
((opcode_i & `INST_LHU_MASK) == `INST_LHU) ,
((opcode_i & `INST_LWU_MASK) == `INST_LWU) :
begin
dbg_inst_rb = "-";
dbg_inst_imm = `DBG_IMM_IMM12;
end
// sb sh sw
((opcode_i & `INST_SB_MASK) == `INST_SB) ,
((opcode_i & `INST_SH_MASK) == `INST_SH) ,
((opcode_i & `INST_SW_MASK) == `INST_SW) :
begin
dbg_inst_rd = "-";
dbg_inst_imm = `DBG_IMM_STOREIMM;
end
endcase
end
end
`endif
endmodule |
module riscv_alu
(
// Inputs
input [ 3:0] alu_op_i
,input [ 31:0] alu_a_i
,input [ 31:0] alu_b_i
// Outputs
,output [ 31:0] alu_p_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result_r;
reg [31:16] shift_right_fill_r;
reg [31:0] shift_right_1_r;
reg [31:0] shift_right_2_r;
reg [31:0] shift_right_4_r;
reg [31:0] shift_right_8_r;
reg [31:0] shift_left_1_r;
reg [31:0] shift_left_2_r;
reg [31:0] shift_left_4_r;
reg [31:0] shift_left_8_r;
wire [31:0] sub_res_w = alu_a_i - alu_b_i;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (alu_op_i or alu_a_i or alu_b_i or sub_res_w)
begin
shift_right_fill_r = 16'b0;
shift_right_1_r = 32'b0;
shift_right_2_r = 32'b0;
shift_right_4_r = 32'b0;
shift_right_8_r = 32'b0;
shift_left_1_r = 32'b0;
shift_left_2_r = 32'b0;
shift_left_4_r = 32'b0;
shift_left_8_r = 32'b0;
case (alu_op_i)
//----------------------------------------------
// Shift Left
//----------------------------------------------
`ALU_SHIFTL :
begin
if (alu_b_i[0] == 1'b1)
shift_left_1_r = {alu_a_i[30:0],1'b0};
else
shift_left_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_left_2_r = {shift_left_1_r[29:0],2'b00};
else
shift_left_2_r = shift_left_1_r;
if (alu_b_i[2] == 1'b1)
shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
else
shift_left_4_r = shift_left_2_r;
if (alu_b_i[3] == 1'b1)
shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
else
shift_left_8_r = shift_left_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_left_8_r[15:0],16'b0000000000000000};
else
result_r = shift_left_8_r;
end
//----------------------------------------------
// Shift Right
//----------------------------------------------
`ALU_SHIFTR, `ALU_SHIFTR_ARITH:
begin
// Arithmetic shift? Fill with 1's if MSB set
if (alu_a_i[31] == 1'b1 && alu_op_i == `ALU_SHIFTR_ARITH)
shift_right_fill_r = 16'b1111111111111111;
else
shift_right_fill_r = 16'b0000000000000000;
if (alu_b_i[0] == 1'b1)
shift_right_1_r = {shift_right_fill_r[31], alu_a_i[31:1]};
else
shift_right_1_r = alu_a_i;
if (alu_b_i[1] == 1'b1)
shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
else
shift_right_2_r = shift_right_1_r;
if (alu_b_i[2] == 1'b1)
shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
else
shift_right_4_r = shift_right_2_r;
if (alu_b_i[3] == 1'b1)
shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
else
shift_right_8_r = shift_right_4_r;
if (alu_b_i[4] == 1'b1)
result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
else
result_r = shift_right_8_r;
end
//----------------------------------------------
// Arithmetic
//----------------------------------------------
`ALU_ADD :
begin
result_r = (alu_a_i + alu_b_i);
end
`ALU_SUB :
begin
result_r = sub_res_w;
end
//----------------------------------------------
// Logical
//----------------------------------------------
`ALU_AND :
begin
result_r = (alu_a_i & alu_b_i);
end
`ALU_OR :
begin
result_r = (alu_a_i | alu_b_i);
end
`ALU_XOR :
begin
result_r = (alu_a_i ^ alu_b_i);
end
//----------------------------------------------
// Comparision
//----------------------------------------------
`ALU_LESS_THAN :
begin
result_r = (alu_a_i < alu_b_i) ? 32'h1 : 32'h0;
end
`ALU_LESS_THAN_SIGNED :
begin
if (alu_a_i[31] != alu_b_i[31])
result_r = alu_a_i[31] ? 32'h1 : 32'h0;
else
result_r = sub_res_w[31] ? 32'h1 : 32'h0;
end
default :
begin
result_r = alu_a_i;
end
endcase
end
assign alu_p_o = result_r;
endmodule |
module riscv_divider
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
// Outputs
,output writeback_valid_o
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg valid_q;
reg [31:0] wb_result_q;
//-------------------------------------------------------------
// Divider
//-------------------------------------------------------------
wire inst_div_w = (opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV;
wire inst_divu_w = (opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU;
wire inst_rem_w = (opcode_opcode_i & `INST_REM_MASK) == `INST_REM;
wire inst_remu_w = (opcode_opcode_i & `INST_REMU_MASK) == `INST_REMU;
wire div_rem_inst_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) ||
((opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU) ||
((opcode_opcode_i & `INST_REM_MASK) == `INST_REM) ||
((opcode_opcode_i & `INST_REMU_MASK) == `INST_REMU);
wire signed_operation_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) || ((opcode_opcode_i & `INST_REM_MASK) == `INST_REM);
wire div_operation_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) || ((opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU);
reg [31:0] dividend_q;
reg [62:0] divisor_q;
reg [31:0] quotient_q;
reg [31:0] q_mask_q;
reg div_inst_q;
reg div_busy_q;
reg invert_res_q;
wire div_start_w = opcode_valid_i & div_rem_inst_w;
wire div_complete_w = !(|q_mask_q) & div_busy_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
div_busy_q <= 1'b0;
dividend_q <= 32'b0;
divisor_q <= 63'b0;
invert_res_q <= 1'b0;
quotient_q <= 32'b0;
q_mask_q <= 32'b0;
div_inst_q <= 1'b0;
end
else if (div_start_w)
begin
div_busy_q <= 1'b1;
div_inst_q <= div_operation_w;
if (signed_operation_w && opcode_ra_operand_i[31])
dividend_q <= -opcode_ra_operand_i;
else
dividend_q <= opcode_ra_operand_i;
if (signed_operation_w && opcode_rb_operand_i[31])
divisor_q <= {-opcode_rb_operand_i, 31'b0};
else
divisor_q <= {opcode_rb_operand_i, 31'b0};
invert_res_q <= (((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) && (opcode_ra_operand_i[31] != opcode_rb_operand_i[31]) && |opcode_rb_operand_i) ||
(((opcode_opcode_i & `INST_REM_MASK) == `INST_REM) && opcode_ra_operand_i[31]);
quotient_q <= 32'b0;
q_mask_q <= 32'h80000000;
end
else if (div_complete_w)
begin
div_busy_q <= 1'b0;
end
else if (div_busy_q)
begin
if (divisor_q <= {31'b0, dividend_q})
begin
dividend_q <= dividend_q - divisor_q[31:0];
quotient_q <= quotient_q | q_mask_q;
end
divisor_q <= {1'b0, divisor_q[62:1]};
q_mask_q <= {1'b0, q_mask_q[31:1]};
end
reg [31:0] div_result_r;
always @ *
begin
div_result_r = 32'b0;
if (div_inst_q)
div_result_r = invert_res_q ? -quotient_q : quotient_q;
else
div_result_r = invert_res_q ? -dividend_q : dividend_q;
end
always @(posedge clk_i or posedge rst_i)
if (rst_i)
valid_q <= 1'b0;
else
valid_q <= div_complete_w;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
wb_result_q <= 32'b0;
else if (div_complete_w)
wb_result_q <= div_result_r;
assign writeback_valid_o = valid_q;
assign writeback_value_o = wb_result_q;
endmodule |
module riscv_lsu
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter MEM_CACHE_ADDR_MIN = 32'h80000000
,parameter MEM_CACHE_ADDR_MAX = 32'h8fffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input [ 31:0] mem_data_rd_i
,input mem_accept_i
,input mem_ack_i
,input mem_error_i
,input [ 10:0] mem_resp_tag_i
,input mem_load_fault_i
,input mem_store_fault_i
// Outputs
,output [ 31:0] mem_addr_o
,output [ 31:0] mem_data_wr_o
,output mem_rd_o
,output [ 3:0] mem_wr_o
,output mem_cacheable_o
,output [ 10:0] mem_req_tag_o
,output mem_invalidate_o
,output mem_writeback_o
,output mem_flush_o
,output writeback_valid_o
,output [ 31:0] writeback_value_o
,output [ 5:0] writeback_exception_o
,output stall_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [ 31:0] mem_addr_q;
reg [ 31:0] mem_data_wr_q;
reg mem_rd_q;
reg [ 3:0] mem_wr_q;
reg mem_cacheable_q;
reg mem_invalidate_q;
reg mem_writeback_q;
reg mem_flush_q;
reg mem_unaligned_e1_q;
reg mem_unaligned_e2_q;
reg mem_load_q;
reg mem_xb_q;
reg mem_xh_q;
reg mem_ls_q;
//-----------------------------------------------------------------
// Outstanding Access Tracking
//-----------------------------------------------------------------
reg pending_lsu_e2_q;
wire issue_lsu_e1_w = (mem_rd_o || (|mem_wr_o) || mem_writeback_o || mem_invalidate_o || mem_flush_o) && mem_accept_i;
wire complete_ok_e2_w = mem_ack_i & ~mem_error_i;
wire complete_err_e2_w = mem_ack_i & mem_error_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pending_lsu_e2_q <= 1'b0;
else if (issue_lsu_e1_w)
pending_lsu_e2_q <= 1'b1;
else if (complete_ok_e2_w || complete_err_e2_w)
pending_lsu_e2_q <= 1'b0;
// Delay next instruction if outstanding response is late
wire delay_lsu_e2_w = pending_lsu_e2_q && !complete_ok_e2_w;
//-----------------------------------------------------------------
// Dummy Ack (unaligned access /E2)
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_unaligned_e2_q <= 1'b0;
else
mem_unaligned_e2_q <= mem_unaligned_e1_q & ~delay_lsu_e2_w;
//-----------------------------------------------------------------
// Opcode decode
//-----------------------------------------------------------------
wire load_inst_w = (((opcode_opcode_i & `INST_LB_MASK) == `INST_LB) ||
((opcode_opcode_i & `INST_LH_MASK) == `INST_LH) ||
((opcode_opcode_i & `INST_LW_MASK) == `INST_LW) ||
((opcode_opcode_i & `INST_LBU_MASK) == `INST_LBU) ||
((opcode_opcode_i & `INST_LHU_MASK) == `INST_LHU) ||
((opcode_opcode_i & `INST_LWU_MASK) == `INST_LWU));
wire load_signed_inst_w = (((opcode_opcode_i & `INST_LB_MASK) == `INST_LB) ||
((opcode_opcode_i & `INST_LH_MASK) == `INST_LH) ||
((opcode_opcode_i & `INST_LW_MASK) == `INST_LW));
wire store_inst_w = (((opcode_opcode_i & `INST_SB_MASK) == `INST_SB) ||
((opcode_opcode_i & `INST_SH_MASK) == `INST_SH) ||
((opcode_opcode_i & `INST_SW_MASK) == `INST_SW));
wire req_lb_w = ((opcode_opcode_i & `INST_LB_MASK) == `INST_LB) || ((opcode_opcode_i & `INST_LBU_MASK) == `INST_LBU);
wire req_lh_w = ((opcode_opcode_i & `INST_LH_MASK) == `INST_LH) || ((opcode_opcode_i & `INST_LHU_MASK) == `INST_LHU);
wire req_lw_w = ((opcode_opcode_i & `INST_LW_MASK) == `INST_LW) || ((opcode_opcode_i & `INST_LWU_MASK) == `INST_LWU);
wire req_sb_w = ((opcode_opcode_i & `INST_LB_MASK) == `INST_SB);
wire req_sh_w = ((opcode_opcode_i & `INST_LH_MASK) == `INST_SH);
wire req_sw_w = ((opcode_opcode_i & `INST_LW_MASK) == `INST_SW);
wire req_sw_lw_w = ((opcode_opcode_i & `INST_SW_MASK) == `INST_SW) || ((opcode_opcode_i & `INST_LW_MASK) == `INST_LW) || ((opcode_opcode_i & `INST_LWU_MASK) == `INST_LWU);
wire req_sh_lh_w = ((opcode_opcode_i & `INST_SH_MASK) == `INST_SH) || ((opcode_opcode_i & `INST_LH_MASK) == `INST_LH) || ((opcode_opcode_i & `INST_LHU_MASK) == `INST_LHU);
reg [31:0] mem_addr_r;
reg mem_unaligned_r;
reg [31:0] mem_data_r;
reg mem_rd_r;
reg [3:0] mem_wr_r;
always @ *
begin
mem_addr_r = 32'b0;
mem_data_r = 32'b0;
mem_unaligned_r = 1'b0;
mem_wr_r = 4'b0;
mem_rd_r = 1'b0;
if (opcode_valid_i && ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW))
mem_addr_r = opcode_ra_operand_i;
else if (opcode_valid_i && load_inst_w)
mem_addr_r = opcode_ra_operand_i + {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
else
mem_addr_r = opcode_ra_operand_i + {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:25], opcode_opcode_i[11:7]};
if (opcode_valid_i && req_sw_lw_w)
mem_unaligned_r = (mem_addr_r[1:0] != 2'b0);
else if (opcode_valid_i && req_sh_lh_w)
mem_unaligned_r = mem_addr_r[0];
mem_rd_r = (opcode_valid_i && load_inst_w && !mem_unaligned_r);
if (opcode_valid_i && ((opcode_opcode_i & `INST_SW_MASK) == `INST_SW) && !mem_unaligned_r)
begin
mem_data_r = opcode_rb_operand_i;
mem_wr_r = 4'hF;
end
else if (opcode_valid_i && ((opcode_opcode_i & `INST_SH_MASK) == `INST_SH) && !mem_unaligned_r)
begin
case (mem_addr_r[1:0])
2'h2 :
begin
mem_data_r = {opcode_rb_operand_i[15:0],16'h0000};
mem_wr_r = 4'b1100;
end
default :
begin
mem_data_r = {16'h0000,opcode_rb_operand_i[15:0]};
mem_wr_r = 4'b0011;
end
endcase
end
else if (opcode_valid_i && ((opcode_opcode_i & `INST_SB_MASK) == `INST_SB))
begin
case (mem_addr_r[1:0])
2'h3 :
begin
mem_data_r = {opcode_rb_operand_i[7:0],24'h000000};
mem_wr_r = 4'b1000;
end
2'h2 :
begin
mem_data_r = {{8'h00,opcode_rb_operand_i[7:0]},16'h0000};
mem_wr_r = 4'b0100;
end
2'h1 :
begin
mem_data_r = {{16'h0000,opcode_rb_operand_i[7:0]},8'h00};
mem_wr_r = 4'b0010;
end
2'h0 :
begin
mem_data_r = {24'h000000,opcode_rb_operand_i[7:0]};
mem_wr_r = 4'b0001;
end
default :
;
endcase
end
else
mem_wr_r = 4'b0;
end
wire dcache_flush_w = ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) && (opcode_opcode_i[31:20] == `CSR_DFLUSH);
wire dcache_writeback_w = ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) && (opcode_opcode_i[31:20] == `CSR_DWRITEBACK);
wire dcache_invalidate_w = ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) && (opcode_opcode_i[31:20] == `CSR_DINVALIDATE);
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_addr_q <= 32'b0;
mem_data_wr_q <= 32'b0;
mem_rd_q <= 1'b0;
mem_wr_q <= 4'b0;
mem_cacheable_q <= 1'b0;
mem_invalidate_q <= 1'b0;
mem_writeback_q <= 1'b0;
mem_flush_q <= 1'b0;
mem_unaligned_e1_q <= 1'b0;
mem_load_q <= 1'b0;
mem_xb_q <= 1'b0;
mem_xh_q <= 1'b0;
mem_ls_q <= 1'b0;
end
// Memory access fault - squash next operation (exception coming...)
else if (complete_err_e2_w || mem_unaligned_e2_q)
begin
mem_addr_q <= 32'b0;
mem_data_wr_q <= 32'b0;
mem_rd_q <= 1'b0;
mem_wr_q <= 4'b0;
mem_cacheable_q <= 1'b0;
mem_invalidate_q <= 1'b0;
mem_writeback_q <= 1'b0;
mem_flush_q <= 1'b0;
mem_unaligned_e1_q <= 1'b0;
mem_load_q <= 1'b0;
mem_xb_q <= 1'b0;
mem_xh_q <= 1'b0;
mem_ls_q <= 1'b0;
end
else if ((mem_rd_q || (|mem_wr_q) || mem_unaligned_e1_q) && delay_lsu_e2_w)
;
else if (!((mem_writeback_o || mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i))
begin
mem_addr_q <= 32'b0;
mem_data_wr_q <= mem_data_r;
mem_rd_q <= mem_rd_r;
mem_wr_q <= mem_wr_r;
mem_cacheable_q <= 1'b0;
mem_invalidate_q <= 1'b0;
mem_writeback_q <= 1'b0;
mem_flush_q <= 1'b0;
mem_unaligned_e1_q <= mem_unaligned_r;
mem_load_q <= opcode_valid_i && load_inst_w;
mem_xb_q <= req_lb_w | req_sb_w;
mem_xh_q <= req_lh_w | req_sh_w;
mem_ls_q <= load_signed_inst_w;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
mem_cacheable_q <= (mem_addr_r >= MEM_CACHE_ADDR_MIN && mem_addr_r <= MEM_CACHE_ADDR_MAX) ||
(opcode_valid_i && (dcache_invalidate_w || dcache_writeback_w || dcache_flush_w));
/* verilator lint_on CMPCONST */
/* verilator lint_on UNSIGNED */
mem_invalidate_q <= opcode_valid_i & dcache_invalidate_w;
mem_writeback_q <= opcode_valid_i & dcache_writeback_w;
mem_flush_q <= opcode_valid_i & dcache_flush_w;
mem_addr_q <= mem_addr_r;
end
assign mem_addr_o = {mem_addr_q[31:2], 2'b0};
assign mem_data_wr_o = mem_data_wr_q;
assign mem_rd_o = mem_rd_q & ~delay_lsu_e2_w;
assign mem_wr_o = mem_wr_q & ~{4{delay_lsu_e2_w}};
assign mem_cacheable_o = mem_cacheable_q;
assign mem_req_tag_o = 11'b0;
assign mem_invalidate_o = mem_invalidate_q;
assign mem_writeback_o = mem_writeback_q;
assign mem_flush_o = mem_flush_q;
// Stall upstream if cache is busy
assign stall_o = ((mem_writeback_o || mem_invalidate_o || mem_flush_o || mem_rd_o || mem_wr_o != 4'b0) && !mem_accept_i) || delay_lsu_e2_w || mem_unaligned_e1_q;
wire resp_load_w;
wire [31:0] resp_addr_w;
wire resp_byte_w;
wire resp_half_w;
wire resp_signed_w;
riscv_lsu_fifo
#(
.WIDTH(36)
,.DEPTH(2)
,.ADDR_W(1)
)
u_lsu_request
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.push_i(((mem_rd_o || (|mem_wr_o) || mem_writeback_o || mem_invalidate_o || mem_flush_o) && mem_accept_i) || (mem_unaligned_e1_q && ~delay_lsu_e2_w))
,.data_in_i({mem_addr_q, mem_ls_q, mem_xh_q, mem_xb_q, mem_load_q})
,.accept_o()
,.valid_o()
,.data_out_o({resp_addr_w, resp_signed_w, resp_half_w, resp_byte_w, resp_load_w})
,.pop_i(mem_ack_i || mem_unaligned_e2_q)
);
//-----------------------------------------------------------------
// Load response
//-----------------------------------------------------------------
reg [1:0] addr_lsb_r;
reg load_byte_r;
reg load_half_r;
reg load_signed_r;
reg [31:0] wb_result_r;
always @ *
begin
wb_result_r = 32'b0;
// Tag associated with load
addr_lsb_r = resp_addr_w[1:0];
load_byte_r = resp_byte_w;
load_half_r = resp_half_w;
load_signed_r = resp_signed_w;
// Access fault - pass badaddr on writeback result bus
if ((mem_ack_i && mem_error_i) || mem_unaligned_e2_q)
wb_result_r = resp_addr_w;
// Handle responses
else if (mem_ack_i && resp_load_w)
begin
if (load_byte_r)
begin
case (addr_lsb_r[1:0])
2'h3: wb_result_r = {24'b0, mem_data_rd_i[31:24]};
2'h2: wb_result_r = {24'b0, mem_data_rd_i[23:16]};
2'h1: wb_result_r = {24'b0, mem_data_rd_i[15:8]};
2'h0: wb_result_r = {24'b0, mem_data_rd_i[7:0]};
endcase
if (load_signed_r && wb_result_r[7])
wb_result_r = {24'hFFFFFF, wb_result_r[7:0]};
end
else if (load_half_r)
begin
if (addr_lsb_r[1])
wb_result_r = {16'b0, mem_data_rd_i[31:16]};
else
wb_result_r = {16'b0, mem_data_rd_i[15:0]};
if (load_signed_r && wb_result_r[15])
wb_result_r = {16'hFFFF, wb_result_r[15:0]};
end
else
wb_result_r = mem_data_rd_i;
end
end
assign writeback_valid_o = mem_ack_i | mem_unaligned_e2_q;
assign writeback_value_o = wb_result_r;
wire fault_load_align_w = mem_unaligned_e2_q & resp_load_w;
wire fault_store_align_w = mem_unaligned_e2_q & ~resp_load_w;
wire fault_load_bus_w = mem_error_i && resp_load_w;
wire fault_store_bus_w = mem_error_i && ~resp_load_w;
wire fault_load_page_w = mem_error_i && mem_load_fault_i;
wire fault_store_page_w = mem_error_i && mem_store_fault_i;
assign writeback_exception_o = fault_load_align_w ? `EXCEPTION_MISALIGNED_LOAD:
fault_store_align_w ? `EXCEPTION_MISALIGNED_STORE:
fault_load_page_w ? `EXCEPTION_PAGE_FAULT_LOAD:
fault_store_page_w ? `EXCEPTION_PAGE_FAULT_STORE:
fault_load_bus_w ? `EXCEPTION_FAULT_LOAD:
fault_store_bus_w ? `EXCEPTION_FAULT_STORE:
`EXCEPTION_W'b0;
endmodule |
module riscv_core
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter SUPPORT_SUPER = 0
,parameter SUPPORT_MMU = 0
,parameter SUPPORT_LOAD_BYPASS = 1
,parameter SUPPORT_MUL_BYPASS = 1
,parameter SUPPORT_REGFILE_XILINX = 0
,parameter EXTRA_DECODE_STAGE = 0
,parameter MEM_CACHE_ADDR_MIN = 32'h80000000
,parameter MEM_CACHE_ADDR_MAX = 32'h8fffffff
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_d_data_rd_i
,input mem_d_accept_i
,input mem_d_ack_i
,input mem_d_error_i
,input [ 10:0] mem_d_resp_tag_i
,input mem_i_accept_i
,input mem_i_valid_i
,input mem_i_error_i
,input [ 31:0] mem_i_inst_i
,input intr_i
,input [ 31:0] reset_vector_i
,input [ 31:0] cpu_id_i
// Outputs
,output [ 31:0] mem_d_addr_o
,output [ 31:0] mem_d_data_wr_o
,output mem_d_rd_o
,output [ 3:0] mem_d_wr_o
,output mem_d_cacheable_o
,output [ 10:0] mem_d_req_tag_o
,output mem_d_invalidate_o
,output mem_d_writeback_o
,output mem_d_flush_o
,output mem_i_rd_o
,output mem_i_flush_o
,output mem_i_invalidate_o
,output [ 31:0] mem_i_pc_o
);
wire mmu_lsu_writeback_w;
wire [ 1:0] fetch_in_priv_w;
wire [ 4:0] mul_opcode_rd_idx_w;
wire mmu_flush_w;
wire [ 31:0] lsu_opcode_pc_w;
wire fetch_accept_w;
wire [ 4:0] csr_opcode_rd_idx_w;
wire [ 31:0] branch_exec_source_w;
wire [ 31:0] csr_opcode_rb_operand_w;
wire [ 31:0] writeback_div_value_w;
wire csr_opcode_valid_w;
wire branch_csr_request_w;
wire [ 31:0] mmu_ifetch_inst_w;
wire [ 31:0] opcode_pc_w;
wire [ 4:0] opcode_rb_idx_w;
wire mmu_lsu_error_w;
wire mul_opcode_valid_w;
wire mmu_mxr_w;
wire [ 1:0] branch_d_exec_priv_w;
wire mmu_ifetch_valid_w;
wire csr_opcode_invalid_w;
wire [ 5:0] csr_writeback_exception_w;
wire fetch_instr_mul_w;
wire branch_exec_is_ret_w;
wire [ 31:0] csr_writeback_exception_addr_w;
wire [ 3:0] mmu_lsu_wr_w;
wire fetch_in_fault_w;
wire branch_request_w;
wire [ 31:0] csr_opcode_pc_w;
wire writeback_mem_valid_w;
wire [ 5:0] csr_result_e1_exception_w;
wire [ 31:0] branch_csr_pc_w;
wire [ 31:0] mmu_lsu_data_wr_w;
wire fetch_fault_page_w;
wire [ 10:0] mmu_lsu_resp_tag_w;
wire [ 10:0] mmu_lsu_req_tag_w;
wire [ 31:0] opcode_ra_operand_w;
wire squash_decode_w;
wire fetch_dec_fault_page_w;
wire [ 31:0] mul_opcode_opcode_w;
wire exec_hold_w;
wire fetch_instr_invalid_w;
wire [ 31:0] branch_pc_w;
wire [ 4:0] mul_opcode_ra_idx_w;
wire [ 4:0] csr_opcode_rb_idx_w;
wire lsu_stall_w;
wire branch_exec_is_not_taken_w;
wire [ 31:0] branch_exec_pc_w;
wire [ 31:0] opcode_opcode_w;
wire [ 31:0] mul_opcode_pc_w;
wire branch_d_exec_request_w;
wire [ 31:0] mul_opcode_ra_operand_w;
wire branch_exec_is_taken_w;
wire fetch_dec_fault_fetch_w;
wire fetch_dec_valid_w;
wire fetch_fault_fetch_w;
wire lsu_opcode_invalid_w;
wire [ 31:0] mmu_lsu_addr_w;
wire mul_hold_w;
wire mmu_ifetch_accept_w;
wire mmu_lsu_ack_w;
wire [ 31:0] fetch_pc_w;
wire mmu_ifetch_invalidate_w;
wire [ 31:0] mul_opcode_rb_operand_w;
wire [ 1:0] branch_csr_priv_w;
wire branch_exec_request_w;
wire [ 31:0] lsu_opcode_ra_operand_w;
wire div_opcode_valid_w;
wire [ 1:0] branch_priv_w;
wire mmu_lsu_rd_w;
wire [ 31:0] fetch_dec_pc_w;
wire interrupt_inhibit_w;
wire mmu_ifetch_error_w;
wire [ 5:0] writeback_mem_exception_w;
wire fetch_instr_lsu_w;
wire [ 1:0] mmu_priv_d_w;
wire [ 4:0] opcode_ra_idx_w;
wire [ 31:0] csr_opcode_ra_operand_w;
wire [ 31:0] writeback_mem_value_w;
wire writeback_div_valid_w;
wire [ 4:0] mul_opcode_rb_idx_w;
wire opcode_invalid_w;
wire fetch_instr_branch_w;
wire [ 31:0] mmu_ifetch_pc_w;
wire mmu_ifetch_rd_w;
wire mmu_ifetch_flush_w;
wire [ 4:0] lsu_opcode_rd_idx_w;
wire [ 31:0] lsu_opcode_opcode_w;
wire mmu_load_fault_w;
wire [ 31:0] mmu_satp_w;
wire [ 31:0] csr_result_e1_wdata_w;
wire [ 31:0] opcode_rb_operand_w;
wire mmu_lsu_invalidate_w;
wire fetch_dec_accept_w;
wire [ 4:0] csr_opcode_ra_idx_w;
wire ifence_w;
wire fetch_instr_exec_w;
wire [ 4:0] opcode_rd_idx_w;
wire [ 31:0] csr_writeback_wdata_w;
wire csr_writeback_write_w;
wire take_interrupt_w;
wire [ 31:0] csr_result_e1_value_w;
wire [ 31:0] branch_d_exec_pc_w;
wire fetch_valid_w;
wire [ 11:0] csr_writeback_waddr_w;
wire branch_exec_is_jmp_w;
wire mmu_lsu_cacheable_w;
wire fetch_instr_csr_w;
wire lsu_opcode_valid_w;
wire [ 31:0] fetch_dec_instr_w;
wire csr_result_e1_write_w;
wire [ 31:0] csr_opcode_opcode_w;
wire fetch_instr_div_w;
wire [ 31:0] fetch_instr_w;
wire mul_opcode_invalid_w;
wire fetch_instr_rd_valid_w;
wire [ 31:0] mmu_lsu_data_rd_w;
wire exec_opcode_valid_w;
wire [ 31:0] writeback_mul_value_w;
wire mmu_lsu_flush_w;
wire [ 4:0] lsu_opcode_rb_idx_w;
wire mmu_lsu_accept_w;
wire [ 31:0] lsu_opcode_rb_operand_w;
wire mmu_sum_w;
wire [ 31:0] writeback_exec_value_w;
wire [ 4:0] lsu_opcode_ra_idx_w;
wire [ 31:0] csr_writeback_exception_pc_w;
wire mmu_store_fault_w;
wire branch_exec_is_call_w;
riscv_exec
u_exec
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.opcode_valid_i(exec_opcode_valid_w)
,.opcode_opcode_i(opcode_opcode_w)
,.opcode_pc_i(opcode_pc_w)
,.opcode_invalid_i(opcode_invalid_w)
,.opcode_rd_idx_i(opcode_rd_idx_w)
,.opcode_ra_idx_i(opcode_ra_idx_w)
,.opcode_rb_idx_i(opcode_rb_idx_w)
,.opcode_ra_operand_i(opcode_ra_operand_w)
,.opcode_rb_operand_i(opcode_rb_operand_w)
,.hold_i(exec_hold_w)
// Outputs
,.branch_request_o(branch_exec_request_w)
,.branch_is_taken_o(branch_exec_is_taken_w)
,.branch_is_not_taken_o(branch_exec_is_not_taken_w)
,.branch_source_o(branch_exec_source_w)
,.branch_is_call_o(branch_exec_is_call_w)
,.branch_is_ret_o(branch_exec_is_ret_w)
,.branch_is_jmp_o(branch_exec_is_jmp_w)
,.branch_pc_o(branch_exec_pc_w)
,.branch_d_request_o(branch_d_exec_request_w)
,.branch_d_pc_o(branch_d_exec_pc_w)
,.branch_d_priv_o(branch_d_exec_priv_w)
,.writeback_value_o(writeback_exec_value_w)
);
riscv_decode
#(
.EXTRA_DECODE_STAGE(EXTRA_DECODE_STAGE)
,.SUPPORT_MULDIV(SUPPORT_MULDIV)
)
u_decode
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.fetch_in_valid_i(fetch_dec_valid_w)
,.fetch_in_instr_i(fetch_dec_instr_w)
,.fetch_in_pc_i(fetch_dec_pc_w)
,.fetch_in_fault_fetch_i(fetch_dec_fault_fetch_w)
,.fetch_in_fault_page_i(fetch_dec_fault_page_w)
,.fetch_out_accept_i(fetch_accept_w)
,.squash_decode_i(squash_decode_w)
// Outputs
,.fetch_in_accept_o(fetch_dec_accept_w)
,.fetch_out_valid_o(fetch_valid_w)
,.fetch_out_instr_o(fetch_instr_w)
,.fetch_out_pc_o(fetch_pc_w)
,.fetch_out_fault_fetch_o(fetch_fault_fetch_w)
,.fetch_out_fault_page_o(fetch_fault_page_w)
,.fetch_out_instr_exec_o(fetch_instr_exec_w)
,.fetch_out_instr_lsu_o(fetch_instr_lsu_w)
,.fetch_out_instr_branch_o(fetch_instr_branch_w)
,.fetch_out_instr_mul_o(fetch_instr_mul_w)
,.fetch_out_instr_div_o(fetch_instr_div_w)
,.fetch_out_instr_csr_o(fetch_instr_csr_w)
,.fetch_out_instr_rd_valid_o(fetch_instr_rd_valid_w)
,.fetch_out_instr_invalid_o(fetch_instr_invalid_w)
);
riscv_mmu
#(
.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
,.SUPPORT_MMU(SUPPORT_MMU)
,.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
)
u_mmu
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.priv_d_i(mmu_priv_d_w)
,.sum_i(mmu_sum_w)
,.mxr_i(mmu_mxr_w)
,.flush_i(mmu_flush_w)
,.satp_i(mmu_satp_w)
,.fetch_in_rd_i(mmu_ifetch_rd_w)
,.fetch_in_flush_i(mmu_ifetch_flush_w)
,.fetch_in_invalidate_i(mmu_ifetch_invalidate_w)
,.fetch_in_pc_i(mmu_ifetch_pc_w)
,.fetch_in_priv_i(fetch_in_priv_w)
,.fetch_out_accept_i(mem_i_accept_i)
,.fetch_out_valid_i(mem_i_valid_i)
,.fetch_out_error_i(mem_i_error_i)
,.fetch_out_inst_i(mem_i_inst_i)
,.lsu_in_addr_i(mmu_lsu_addr_w)
,.lsu_in_data_wr_i(mmu_lsu_data_wr_w)
,.lsu_in_rd_i(mmu_lsu_rd_w)
,.lsu_in_wr_i(mmu_lsu_wr_w)
,.lsu_in_cacheable_i(mmu_lsu_cacheable_w)
,.lsu_in_req_tag_i(mmu_lsu_req_tag_w)
,.lsu_in_invalidate_i(mmu_lsu_invalidate_w)
,.lsu_in_writeback_i(mmu_lsu_writeback_w)
,.lsu_in_flush_i(mmu_lsu_flush_w)
,.lsu_out_data_rd_i(mem_d_data_rd_i)
,.lsu_out_accept_i(mem_d_accept_i)
,.lsu_out_ack_i(mem_d_ack_i)
,.lsu_out_error_i(mem_d_error_i)
,.lsu_out_resp_tag_i(mem_d_resp_tag_i)
// Outputs
,.fetch_in_accept_o(mmu_ifetch_accept_w)
,.fetch_in_valid_o(mmu_ifetch_valid_w)
,.fetch_in_error_o(mmu_ifetch_error_w)
,.fetch_in_inst_o(mmu_ifetch_inst_w)
,.fetch_out_rd_o(mem_i_rd_o)
,.fetch_out_flush_o(mem_i_flush_o)
,.fetch_out_invalidate_o(mem_i_invalidate_o)
,.fetch_out_pc_o(mem_i_pc_o)
,.fetch_in_fault_o(fetch_in_fault_w)
,.lsu_in_data_rd_o(mmu_lsu_data_rd_w)
,.lsu_in_accept_o(mmu_lsu_accept_w)
,.lsu_in_ack_o(mmu_lsu_ack_w)
,.lsu_in_error_o(mmu_lsu_error_w)
,.lsu_in_resp_tag_o(mmu_lsu_resp_tag_w)
,.lsu_out_addr_o(mem_d_addr_o)
,.lsu_out_data_wr_o(mem_d_data_wr_o)
,.lsu_out_rd_o(mem_d_rd_o)
,.lsu_out_wr_o(mem_d_wr_o)
,.lsu_out_cacheable_o(mem_d_cacheable_o)
,.lsu_out_req_tag_o(mem_d_req_tag_o)
,.lsu_out_invalidate_o(mem_d_invalidate_o)
,.lsu_out_writeback_o(mem_d_writeback_o)
,.lsu_out_flush_o(mem_d_flush_o)
,.lsu_in_load_fault_o(mmu_load_fault_w)
,.lsu_in_store_fault_o(mmu_store_fault_w)
);
riscv_lsu
#(
.MEM_CACHE_ADDR_MAX(MEM_CACHE_ADDR_MAX)
,.MEM_CACHE_ADDR_MIN(MEM_CACHE_ADDR_MIN)
)
u_lsu
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.opcode_valid_i(lsu_opcode_valid_w)
,.opcode_opcode_i(lsu_opcode_opcode_w)
,.opcode_pc_i(lsu_opcode_pc_w)
,.opcode_invalid_i(lsu_opcode_invalid_w)
,.opcode_rd_idx_i(lsu_opcode_rd_idx_w)
,.opcode_ra_idx_i(lsu_opcode_ra_idx_w)
,.opcode_rb_idx_i(lsu_opcode_rb_idx_w)
,.opcode_ra_operand_i(lsu_opcode_ra_operand_w)
,.opcode_rb_operand_i(lsu_opcode_rb_operand_w)
,.mem_data_rd_i(mmu_lsu_data_rd_w)
,.mem_accept_i(mmu_lsu_accept_w)
,.mem_ack_i(mmu_lsu_ack_w)
,.mem_error_i(mmu_lsu_error_w)
,.mem_resp_tag_i(mmu_lsu_resp_tag_w)
,.mem_load_fault_i(mmu_load_fault_w)
,.mem_store_fault_i(mmu_store_fault_w)
// Outputs
,.mem_addr_o(mmu_lsu_addr_w)
,.mem_data_wr_o(mmu_lsu_data_wr_w)
,.mem_rd_o(mmu_lsu_rd_w)
,.mem_wr_o(mmu_lsu_wr_w)
,.mem_cacheable_o(mmu_lsu_cacheable_w)
,.mem_req_tag_o(mmu_lsu_req_tag_w)
,.mem_invalidate_o(mmu_lsu_invalidate_w)
,.mem_writeback_o(mmu_lsu_writeback_w)
,.mem_flush_o(mmu_lsu_flush_w)
,.writeback_valid_o(writeback_mem_valid_w)
,.writeback_value_o(writeback_mem_value_w)
,.writeback_exception_o(writeback_mem_exception_w)
,.stall_o(lsu_stall_w)
);
riscv_csr
#(
.SUPPORT_SUPER(SUPPORT_SUPER)
,.SUPPORT_MULDIV(SUPPORT_MULDIV)
)
u_csr
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.intr_i(intr_i)
,.opcode_valid_i(csr_opcode_valid_w)
,.opcode_opcode_i(csr_opcode_opcode_w)
,.opcode_pc_i(csr_opcode_pc_w)
,.opcode_invalid_i(csr_opcode_invalid_w)
,.opcode_rd_idx_i(csr_opcode_rd_idx_w)
,.opcode_ra_idx_i(csr_opcode_ra_idx_w)
,.opcode_rb_idx_i(csr_opcode_rb_idx_w)
,.opcode_ra_operand_i(csr_opcode_ra_operand_w)
,.opcode_rb_operand_i(csr_opcode_rb_operand_w)
,.csr_writeback_write_i(csr_writeback_write_w)
,.csr_writeback_waddr_i(csr_writeback_waddr_w)
,.csr_writeback_wdata_i(csr_writeback_wdata_w)
,.csr_writeback_exception_i(csr_writeback_exception_w)
,.csr_writeback_exception_pc_i(csr_writeback_exception_pc_w)
,.csr_writeback_exception_addr_i(csr_writeback_exception_addr_w)
,.cpu_id_i(cpu_id_i)
,.reset_vector_i(reset_vector_i)
,.interrupt_inhibit_i(interrupt_inhibit_w)
// Outputs
,.csr_result_e1_value_o(csr_result_e1_value_w)
,.csr_result_e1_write_o(csr_result_e1_write_w)
,.csr_result_e1_wdata_o(csr_result_e1_wdata_w)
,.csr_result_e1_exception_o(csr_result_e1_exception_w)
,.branch_csr_request_o(branch_csr_request_w)
,.branch_csr_pc_o(branch_csr_pc_w)
,.branch_csr_priv_o(branch_csr_priv_w)
,.take_interrupt_o(take_interrupt_w)
,.ifence_o(ifence_w)
,.mmu_priv_d_o(mmu_priv_d_w)
,.mmu_sum_o(mmu_sum_w)
,.mmu_mxr_o(mmu_mxr_w)
,.mmu_flush_o(mmu_flush_w)
,.mmu_satp_o(mmu_satp_w)
);
riscv_multiplier
u_mul
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.opcode_valid_i(mul_opcode_valid_w)
,.opcode_opcode_i(mul_opcode_opcode_w)
,.opcode_pc_i(mul_opcode_pc_w)
,.opcode_invalid_i(mul_opcode_invalid_w)
,.opcode_rd_idx_i(mul_opcode_rd_idx_w)
,.opcode_ra_idx_i(mul_opcode_ra_idx_w)
,.opcode_rb_idx_i(mul_opcode_rb_idx_w)
,.opcode_ra_operand_i(mul_opcode_ra_operand_w)
,.opcode_rb_operand_i(mul_opcode_rb_operand_w)
,.hold_i(mul_hold_w)
// Outputs
,.writeback_value_o(writeback_mul_value_w)
);
riscv_divider
u_div
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.opcode_valid_i(div_opcode_valid_w)
,.opcode_opcode_i(opcode_opcode_w)
,.opcode_pc_i(opcode_pc_w)
,.opcode_invalid_i(opcode_invalid_w)
,.opcode_rd_idx_i(opcode_rd_idx_w)
,.opcode_ra_idx_i(opcode_ra_idx_w)
,.opcode_rb_idx_i(opcode_rb_idx_w)
,.opcode_ra_operand_i(opcode_ra_operand_w)
,.opcode_rb_operand_i(opcode_rb_operand_w)
// Outputs
,.writeback_valid_o(writeback_div_valid_w)
,.writeback_value_o(writeback_div_value_w)
);
riscv_issue
#(
.SUPPORT_REGFILE_XILINX(SUPPORT_REGFILE_XILINX)
,.SUPPORT_LOAD_BYPASS(SUPPORT_LOAD_BYPASS)
,.SUPPORT_MULDIV(SUPPORT_MULDIV)
,.SUPPORT_MUL_BYPASS(SUPPORT_MUL_BYPASS)
,.SUPPORT_DUAL_ISSUE(1)
)
u_issue
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.fetch_valid_i(fetch_valid_w)
,.fetch_instr_i(fetch_instr_w)
,.fetch_pc_i(fetch_pc_w)
,.fetch_fault_fetch_i(fetch_fault_fetch_w)
,.fetch_fault_page_i(fetch_fault_page_w)
,.fetch_instr_exec_i(fetch_instr_exec_w)
,.fetch_instr_lsu_i(fetch_instr_lsu_w)
,.fetch_instr_branch_i(fetch_instr_branch_w)
,.fetch_instr_mul_i(fetch_instr_mul_w)
,.fetch_instr_div_i(fetch_instr_div_w)
,.fetch_instr_csr_i(fetch_instr_csr_w)
,.fetch_instr_rd_valid_i(fetch_instr_rd_valid_w)
,.fetch_instr_invalid_i(fetch_instr_invalid_w)
,.branch_exec_request_i(branch_exec_request_w)
,.branch_exec_is_taken_i(branch_exec_is_taken_w)
,.branch_exec_is_not_taken_i(branch_exec_is_not_taken_w)
,.branch_exec_source_i(branch_exec_source_w)
,.branch_exec_is_call_i(branch_exec_is_call_w)
,.branch_exec_is_ret_i(branch_exec_is_ret_w)
,.branch_exec_is_jmp_i(branch_exec_is_jmp_w)
,.branch_exec_pc_i(branch_exec_pc_w)
,.branch_d_exec_request_i(branch_d_exec_request_w)
,.branch_d_exec_pc_i(branch_d_exec_pc_w)
,.branch_d_exec_priv_i(branch_d_exec_priv_w)
,.branch_csr_request_i(branch_csr_request_w)
,.branch_csr_pc_i(branch_csr_pc_w)
,.branch_csr_priv_i(branch_csr_priv_w)
,.writeback_exec_value_i(writeback_exec_value_w)
,.writeback_mem_valid_i(writeback_mem_valid_w)
,.writeback_mem_value_i(writeback_mem_value_w)
,.writeback_mem_exception_i(writeback_mem_exception_w)
,.writeback_mul_value_i(writeback_mul_value_w)
,.writeback_div_valid_i(writeback_div_valid_w)
,.writeback_div_value_i(writeback_div_value_w)
,.csr_result_e1_value_i(csr_result_e1_value_w)
,.csr_result_e1_write_i(csr_result_e1_write_w)
,.csr_result_e1_wdata_i(csr_result_e1_wdata_w)
,.csr_result_e1_exception_i(csr_result_e1_exception_w)
,.lsu_stall_i(lsu_stall_w)
,.take_interrupt_i(take_interrupt_w)
// Outputs
,.fetch_accept_o(fetch_accept_w)
,.branch_request_o(branch_request_w)
,.branch_pc_o(branch_pc_w)
,.branch_priv_o(branch_priv_w)
,.exec_opcode_valid_o(exec_opcode_valid_w)
,.lsu_opcode_valid_o(lsu_opcode_valid_w)
,.csr_opcode_valid_o(csr_opcode_valid_w)
,.mul_opcode_valid_o(mul_opcode_valid_w)
,.div_opcode_valid_o(div_opcode_valid_w)
,.opcode_opcode_o(opcode_opcode_w)
,.opcode_pc_o(opcode_pc_w)
,.opcode_invalid_o(opcode_invalid_w)
,.opcode_rd_idx_o(opcode_rd_idx_w)
,.opcode_ra_idx_o(opcode_ra_idx_w)
,.opcode_rb_idx_o(opcode_rb_idx_w)
,.opcode_ra_operand_o(opcode_ra_operand_w)
,.opcode_rb_operand_o(opcode_rb_operand_w)
,.lsu_opcode_opcode_o(lsu_opcode_opcode_w)
,.lsu_opcode_pc_o(lsu_opcode_pc_w)
,.lsu_opcode_invalid_o(lsu_opcode_invalid_w)
,.lsu_opcode_rd_idx_o(lsu_opcode_rd_idx_w)
,.lsu_opcode_ra_idx_o(lsu_opcode_ra_idx_w)
,.lsu_opcode_rb_idx_o(lsu_opcode_rb_idx_w)
,.lsu_opcode_ra_operand_o(lsu_opcode_ra_operand_w)
,.lsu_opcode_rb_operand_o(lsu_opcode_rb_operand_w)
,.mul_opcode_opcode_o(mul_opcode_opcode_w)
,.mul_opcode_pc_o(mul_opcode_pc_w)
,.mul_opcode_invalid_o(mul_opcode_invalid_w)
,.mul_opcode_rd_idx_o(mul_opcode_rd_idx_w)
,.mul_opcode_ra_idx_o(mul_opcode_ra_idx_w)
,.mul_opcode_rb_idx_o(mul_opcode_rb_idx_w)
,.mul_opcode_ra_operand_o(mul_opcode_ra_operand_w)
,.mul_opcode_rb_operand_o(mul_opcode_rb_operand_w)
,.csr_opcode_opcode_o(csr_opcode_opcode_w)
,.csr_opcode_pc_o(csr_opcode_pc_w)
,.csr_opcode_invalid_o(csr_opcode_invalid_w)
,.csr_opcode_rd_idx_o(csr_opcode_rd_idx_w)
,.csr_opcode_ra_idx_o(csr_opcode_ra_idx_w)
,.csr_opcode_rb_idx_o(csr_opcode_rb_idx_w)
,.csr_opcode_ra_operand_o(csr_opcode_ra_operand_w)
,.csr_opcode_rb_operand_o(csr_opcode_rb_operand_w)
,.csr_writeback_write_o(csr_writeback_write_w)
,.csr_writeback_waddr_o(csr_writeback_waddr_w)
,.csr_writeback_wdata_o(csr_writeback_wdata_w)
,.csr_writeback_exception_o(csr_writeback_exception_w)
,.csr_writeback_exception_pc_o(csr_writeback_exception_pc_w)
,.csr_writeback_exception_addr_o(csr_writeback_exception_addr_w)
,.exec_hold_o(exec_hold_w)
,.mul_hold_o(mul_hold_w)
,.interrupt_inhibit_o(interrupt_inhibit_w)
);
riscv_fetch
#(
.SUPPORT_MMU(SUPPORT_MMU)
)
u_fetch
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.fetch_accept_i(fetch_dec_accept_w)
,.icache_accept_i(mmu_ifetch_accept_w)
,.icache_valid_i(mmu_ifetch_valid_w)
,.icache_error_i(mmu_ifetch_error_w)
,.icache_inst_i(mmu_ifetch_inst_w)
,.icache_page_fault_i(fetch_in_fault_w)
,.fetch_invalidate_i(ifence_w)
,.branch_request_i(branch_request_w)
,.branch_pc_i(branch_pc_w)
,.branch_priv_i(branch_priv_w)
// Outputs
,.fetch_valid_o(fetch_dec_valid_w)
,.fetch_instr_o(fetch_dec_instr_w)
,.fetch_pc_o(fetch_dec_pc_w)
,.fetch_fault_fetch_o(fetch_dec_fault_fetch_w)
,.fetch_fault_page_o(fetch_dec_fault_page_w)
,.icache_rd_o(mmu_ifetch_rd_w)
,.icache_flush_o(mmu_ifetch_flush_w)
,.icache_invalidate_o(mmu_ifetch_invalidate_w)
,.icache_pc_o(mmu_ifetch_pc_w)
,.icache_priv_o(fetch_in_priv_w)
,.squash_decode_o(squash_decode_w)
);
endmodule |
module riscv_fetch
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MMU = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input fetch_accept_i
,input icache_accept_i
,input icache_valid_i
,input icache_error_i
,input [ 31:0] icache_inst_i
,input icache_page_fault_i
,input fetch_invalidate_i
,input branch_request_i
,input [ 31:0] branch_pc_i
,input [ 1:0] branch_priv_i
// Outputs
,output fetch_valid_o
,output [ 31:0] fetch_instr_o
,output [ 31:0] fetch_pc_o
,output fetch_fault_fetch_o
,output fetch_fault_page_o
,output icache_rd_o
,output icache_flush_o
,output icache_invalidate_o
,output [ 31:0] icache_pc_o
,output [ 1:0] icache_priv_o
,output squash_decode_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg active_q;
wire icache_busy_w;
wire stall_w = !fetch_accept_i || icache_busy_w || !icache_accept_i;
//-------------------------------------------------------------
// Buffered branch
//-------------------------------------------------------------
reg branch_q;
reg [31:0] branch_pc_q;
reg [1:0] branch_priv_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
branch_q <= 1'b0;
branch_pc_q <= 32'b0;
branch_priv_q <= `PRIV_MACHINE;
end
else if (branch_request_i)
begin
branch_q <= 1'b1;
branch_pc_q <= branch_pc_i;
branch_priv_q <= branch_priv_i;
end
else if (icache_rd_o && icache_accept_i)
begin
branch_q <= 1'b0;
branch_pc_q <= 32'b0;
end
wire branch_w = branch_q;
wire [31:0] branch_pc_w = branch_pc_q;
wire [1:0] branch_priv_w = branch_priv_q;
assign squash_decode_o = branch_request_i;
//-------------------------------------------------------------
// Active flag
//-------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
active_q <= 1'b0;
else if (branch_w && ~stall_w)
active_q <= 1'b1;
//-------------------------------------------------------------
// Stall flag
//-------------------------------------------------------------
reg stall_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
stall_q <= 1'b0;
else
stall_q <= stall_w;
//-------------------------------------------------------------
// Request tracking
//-------------------------------------------------------------
reg icache_fetch_q;
reg icache_invalidate_q;
// ICACHE fetch tracking
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
icache_fetch_q <= 1'b0;
else if (icache_rd_o && icache_accept_i)
icache_fetch_q <= 1'b1;
else if (icache_valid_i)
icache_fetch_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
icache_invalidate_q <= 1'b0;
else if (icache_invalidate_o && !icache_accept_i)
icache_invalidate_q <= 1'b1;
else
icache_invalidate_q <= 1'b0;
//-------------------------------------------------------------
// PC
//-------------------------------------------------------------
reg [31:0] pc_f_q;
reg [31:0] pc_d_q;
wire [31:0] icache_pc_w;
wire [1:0] icache_priv_w;
wire fetch_resp_drop_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pc_f_q <= 32'b0;
// Branch request
else if (branch_w && ~stall_w)
pc_f_q <= branch_pc_w;
// NPC
else if (!stall_w)
pc_f_q <= {icache_pc_w[31:2],2'b0} + 32'd4;
reg [1:0] priv_f_q;
reg branch_d_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
priv_f_q <= `PRIV_MACHINE;
// Branch request
else if (branch_w && ~stall_w)
priv_f_q <= branch_priv_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
branch_d_q <= 1'b0;
// Branch request
else if (branch_w && ~stall_w)
branch_d_q <= 1'b1;
// NPC
else if (!stall_w)
branch_d_q <= 1'b0;
assign icache_pc_w = pc_f_q;
assign icache_priv_w = priv_f_q;
assign fetch_resp_drop_w = branch_w | branch_d_q;
// Last fetch address
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pc_d_q <= 32'b0;
else if (icache_rd_o && icache_accept_i)
pc_d_q <= icache_pc_w;
//-------------------------------------------------------------
// Outputs
//-------------------------------------------------------------
assign icache_rd_o = active_q & fetch_accept_i & !icache_busy_w;
assign icache_pc_o = {icache_pc_w[31:2],2'b0};
assign icache_priv_o = icache_priv_w;
assign icache_flush_o = fetch_invalidate_i | icache_invalidate_q;
assign icache_invalidate_o = 1'b0;
assign icache_busy_w = icache_fetch_q && !icache_valid_i;
//-------------------------------------------------------------
// Response Buffer
//-------------------------------------------------------------
reg [65:0] skid_buffer_q;
reg skid_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
skid_buffer_q <= 66'b0;
skid_valid_q <= 1'b0;
end
// Instruction output back-pressured - hold in skid buffer
else if (fetch_valid_o && !fetch_accept_i)
begin
skid_valid_q <= 1'b1;
skid_buffer_q <= {fetch_fault_page_o, fetch_fault_fetch_o, fetch_pc_o, fetch_instr_o};
end
else
begin
skid_valid_q <= 1'b0;
skid_buffer_q <= 66'b0;
end
assign fetch_valid_o = (icache_valid_i || skid_valid_q) & !fetch_resp_drop_w;
assign fetch_pc_o = skid_valid_q ? skid_buffer_q[63:32] : {pc_d_q[31:2],2'b0};
assign fetch_instr_o = skid_valid_q ? skid_buffer_q[31:0] : icache_inst_i;
// Faults
assign fetch_fault_fetch_o = skid_valid_q ? skid_buffer_q[64] : icache_error_i;
assign fetch_fault_page_o = skid_valid_q ? skid_buffer_q[65] : icache_page_fault_i;
endmodule |
module riscv_xilinx_2r1w
(
// Inputs
input clk_i
,input rst_i
,input [ 4:0] rd0_i
,input [ 31:0] rd0_value_i
,input [ 4:0] ra_i
,input [ 4:0] rb_i
// Outputs
,output [ 31:0] ra_value_o
,output [ 31:0] rb_value_o
);
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] reg_rs1_w;
wire [31:0] reg_rs2_w;
wire [31:0] rs1_0_15_w;
wire [31:0] rs1_16_31_w;
wire [31:0] rs2_0_15_w;
wire [31:0] rs2_16_31_w;
wire write_enable_w;
wire write_banka_w;
wire write_bankb_w;
//-----------------------------------------------------------------
// Register File (using RAM16X1D )
//-----------------------------------------------------------------
genvar i;
// Registers 0 - 15
generate
for (i=0;i<32;i=i+1)
begin : reg_loop1
RAM16X1D reg_bit1a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd0_i[0]), .A1(rd0_i[1]), .A2(rd0_i[2]), .A3(rd0_i[3]), .D(rd0_value_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(rs1_0_15_w[i]), .SPO(/* open */));
RAM16X1D reg_bit2a(.WCLK(clk_i), .WE(write_banka_w), .A0(rd0_i[0]), .A1(rd0_i[1]), .A2(rd0_i[2]), .A3(rd0_i[3]), .D(rd0_value_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rs2_0_15_w[i]), .SPO(/* open */));
end
endgenerate
// Registers 16 - 31
generate
for (i=0;i<32;i=i+1)
begin : reg_loop2
RAM16X1D reg_bit1b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd0_i[0]), .A1(rd0_i[1]), .A2(rd0_i[2]), .A3(rd0_i[3]), .D(rd0_value_i[i]), .DPRA0(ra_i[0]), .DPRA1(ra_i[1]), .DPRA2(ra_i[2]), .DPRA3(ra_i[3]), .DPO(rs1_16_31_w[i]), .SPO(/* open */));
RAM16X1D reg_bit2b(.WCLK(clk_i), .WE(write_bankb_w), .A0(rd0_i[0]), .A1(rd0_i[1]), .A2(rd0_i[2]), .A3(rd0_i[3]), .D(rd0_value_i[i]), .DPRA0(rb_i[0]), .DPRA1(rb_i[1]), .DPRA2(rb_i[2]), .DPRA3(rb_i[3]), .DPO(rs2_16_31_w[i]), .SPO(/* open */));
end
endgenerate
//-----------------------------------------------------------------
// Combinatorial Assignments
//-----------------------------------------------------------------
assign reg_rs1_w = (ra_i[4] == 1'b0) ? rs1_0_15_w : rs1_16_31_w;
assign reg_rs2_w = (rb_i[4] == 1'b0) ? rs2_0_15_w : rs2_16_31_w;
assign write_enable_w = (rd0_i != 5'b00000);
assign write_banka_w = (write_enable_w & (~rd0_i[4]));
assign write_bankb_w = (write_enable_w & rd0_i[4]);
reg [31:0] ra_value_r;
reg [31:0] rb_value_r;
// Register read ports
always @ *
begin
if (ra_i == 5'b00000)
ra_value_r = 32'h00000000;
else
ra_value_r = reg_rs1_w;
if (rb_i == 5'b00000)
rb_value_r = 32'h00000000;
else
rb_value_r = reg_rs2_w;
end
assign ra_value_o = ra_value_r;
assign rb_value_o = rb_value_r;
endmodule |
module riscv_multiplier
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input hold_i
// Outputs
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
localparam MULT_STAGES = 2; // 2 or 3
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg [31:0] result_e2_q;
reg [31:0] result_e3_q;
reg [32:0] operand_a_e1_q;
reg [32:0] operand_b_e1_q;
reg mulhi_sel_e1_q;
//-------------------------------------------------------------
// Multiplier
//-------------------------------------------------------------
wire [64:0] mult_result_w;
reg [32:0] operand_b_r;
reg [32:0] operand_a_r;
reg [31:0] result_r;
wire mult_inst_w = ((opcode_opcode_i & `INST_MUL_MASK) == `INST_MUL) ||
((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH) ||
((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) ||
((opcode_opcode_i & `INST_MULHU_MASK) == `INST_MULHU);
always @ *
begin
if ((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else if ((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH)
operand_a_r = {opcode_ra_operand_i[31], opcode_ra_operand_i[31:0]};
else // MULHU || MUL
operand_a_r = {1'b0, opcode_ra_operand_i[31:0]};
end
always @ *
begin
if ((opcode_opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU)
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
else if ((opcode_opcode_i & `INST_MULH_MASK) == `INST_MULH)
operand_b_r = {opcode_rb_operand_i[31], opcode_rb_operand_i[31:0]};
else // MULHU || MUL
operand_b_r = {1'b0, opcode_rb_operand_i[31:0]};
end
// Pipeline flops for multiplier
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
else if (hold_i)
;
else if (opcode_valid_i && mult_inst_w)
begin
operand_a_e1_q <= operand_a_r;
operand_b_e1_q <= operand_b_r;
mulhi_sel_e1_q <= ~((opcode_opcode_i & `INST_MUL_MASK) == `INST_MUL);
end
else
begin
operand_a_e1_q <= 33'b0;
operand_b_e1_q <= 33'b0;
mulhi_sel_e1_q <= 1'b0;
end
assign mult_result_w = {{ 32 {operand_a_e1_q[32]}}, operand_a_e1_q}*{{ 32 {operand_b_e1_q[32]}}, operand_b_e1_q};
always @ *
begin
result_r = mulhi_sel_e1_q ? mult_result_w[63:32] : mult_result_w[31:0];
end
always @(posedge clk_i or posedge rst_i)
if (rst_i)
result_e2_q <= 32'b0;
else if (~hold_i)
result_e2_q <= result_r;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
result_e3_q <= 32'b0;
else if (~hold_i)
result_e3_q <= result_e2_q;
assign writeback_value_o = (MULT_STAGES == 3) ? result_e3_q : result_e2_q;
endmodule |
module riscv_regfile
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_REGFILE_XILINX = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [ 4:0] rd0_i
,input [ 31:0] rd0_value_i
,input [ 4:0] ra0_i
,input [ 4:0] rb0_i
// Outputs
,output [ 31:0] ra0_value_o
,output [ 31:0] rb0_value_o
);
//-----------------------------------------------------------------
// Xilinx specific register file (single issue)
//-----------------------------------------------------------------
generate
if (SUPPORT_REGFILE_XILINX)
begin: REGFILE_XILINX_SINGLE
riscv_xilinx_2r1w
u_reg
(
// Inputs
.clk_i(clk_i)
,.rst_i(rst_i)
,.rd0_i(rd0_i)
,.rd0_value_i(rd0_value_i)
,.ra_i(ra0_i)
,.rb_i(rb0_i)
// Outputs
,.ra_value_o(ra0_value_o)
,.rb_value_o(rb0_value_o)
);
end
//-----------------------------------------------------------------
// Flop based register file
//-----------------------------------------------------------------
else
begin: REGFILE
reg [31:0] reg_r1_q;
reg [31:0] reg_r2_q;
reg [31:0] reg_r3_q;
reg [31:0] reg_r4_q;
reg [31:0] reg_r5_q;
reg [31:0] reg_r6_q;
reg [31:0] reg_r7_q;
reg [31:0] reg_r8_q;
reg [31:0] reg_r9_q;
reg [31:0] reg_r10_q;
reg [31:0] reg_r11_q;
reg [31:0] reg_r12_q;
reg [31:0] reg_r13_q;
reg [31:0] reg_r14_q;
reg [31:0] reg_r15_q;
reg [31:0] reg_r16_q;
reg [31:0] reg_r17_q;
reg [31:0] reg_r18_q;
reg [31:0] reg_r19_q;
reg [31:0] reg_r20_q;
reg [31:0] reg_r21_q;
reg [31:0] reg_r22_q;
reg [31:0] reg_r23_q;
reg [31:0] reg_r24_q;
reg [31:0] reg_r25_q;
reg [31:0] reg_r26_q;
reg [31:0] reg_r27_q;
reg [31:0] reg_r28_q;
reg [31:0] reg_r29_q;
reg [31:0] reg_r30_q;
reg [31:0] reg_r31_q;
// Simulation friendly names
wire [31:0] x0_zero_w = 32'b0;
wire [31:0] x1_ra_w = reg_r1_q;
wire [31:0] x2_sp_w = reg_r2_q;
wire [31:0] x3_gp_w = reg_r3_q;
wire [31:0] x4_tp_w = reg_r4_q;
wire [31:0] x5_t0_w = reg_r5_q;
wire [31:0] x6_t1_w = reg_r6_q;
wire [31:0] x7_t2_w = reg_r7_q;
wire [31:0] x8_s0_w = reg_r8_q;
wire [31:0] x9_s1_w = reg_r9_q;
wire [31:0] x10_a0_w = reg_r10_q;
wire [31:0] x11_a1_w = reg_r11_q;
wire [31:0] x12_a2_w = reg_r12_q;
wire [31:0] x13_a3_w = reg_r13_q;
wire [31:0] x14_a4_w = reg_r14_q;
wire [31:0] x15_a5_w = reg_r15_q;
wire [31:0] x16_a6_w = reg_r16_q;
wire [31:0] x17_a7_w = reg_r17_q;
wire [31:0] x18_s2_w = reg_r18_q;
wire [31:0] x19_s3_w = reg_r19_q;
wire [31:0] x20_s4_w = reg_r20_q;
wire [31:0] x21_s5_w = reg_r21_q;
wire [31:0] x22_s6_w = reg_r22_q;
wire [31:0] x23_s7_w = reg_r23_q;
wire [31:0] x24_s8_w = reg_r24_q;
wire [31:0] x25_s9_w = reg_r25_q;
wire [31:0] x26_s10_w = reg_r26_q;
wire [31:0] x27_s11_w = reg_r27_q;
wire [31:0] x28_t3_w = reg_r28_q;
wire [31:0] x29_t4_w = reg_r29_q;
wire [31:0] x30_t5_w = reg_r30_q;
wire [31:0] x31_t6_w = reg_r31_q;
//-----------------------------------------------------------------
// Flop based register File (for simulation)
//-----------------------------------------------------------------
// Synchronous register write back
always @ (posedge clk_i )
if (rst_i)
begin
reg_r1_q <= 32'h00000000;
reg_r2_q <= 32'h00000000;
reg_r3_q <= 32'h00000000;
reg_r4_q <= 32'h00000000;
reg_r5_q <= 32'h00000000;
reg_r6_q <= 32'h00000000;
reg_r7_q <= 32'h00000000;
reg_r8_q <= 32'h00000000;
reg_r9_q <= 32'h00000000;
reg_r10_q <= 32'h00000000;
reg_r11_q <= 32'h00000000;
reg_r12_q <= 32'h00000000;
reg_r13_q <= 32'h00000000;
reg_r14_q <= 32'h00000000;
reg_r15_q <= 32'h00000000;
reg_r16_q <= 32'h00000000;
reg_r17_q <= 32'h00000000;
reg_r18_q <= 32'h00000000;
reg_r19_q <= 32'h00000000;
reg_r20_q <= 32'h00000000;
reg_r21_q <= 32'h00000000;
reg_r22_q <= 32'h00000000;
reg_r23_q <= 32'h00000000;
reg_r24_q <= 32'h00000000;
reg_r25_q <= 32'h00000000;
reg_r26_q <= 32'h00000000;
reg_r27_q <= 32'h00000000;
reg_r28_q <= 32'h00000000;
reg_r29_q <= 32'h00000000;
reg_r30_q <= 32'h00000000;
reg_r31_q <= 32'h00000000;
end
else
begin
if (rd0_i == 5'd1) reg_r1_q <= rd0_value_i;
if (rd0_i == 5'd2) reg_r2_q <= rd0_value_i;
if (rd0_i == 5'd3) reg_r3_q <= rd0_value_i;
if (rd0_i == 5'd4) reg_r4_q <= rd0_value_i;
if (rd0_i == 5'd5) reg_r5_q <= rd0_value_i;
if (rd0_i == 5'd6) reg_r6_q <= rd0_value_i;
if (rd0_i == 5'd7) reg_r7_q <= rd0_value_i;
if (rd0_i == 5'd8) reg_r8_q <= rd0_value_i;
if (rd0_i == 5'd9) reg_r9_q <= rd0_value_i;
if (rd0_i == 5'd10) reg_r10_q <= rd0_value_i;
if (rd0_i == 5'd11) reg_r11_q <= rd0_value_i;
if (rd0_i == 5'd12) reg_r12_q <= rd0_value_i;
if (rd0_i == 5'd13) reg_r13_q <= rd0_value_i;
if (rd0_i == 5'd14) reg_r14_q <= rd0_value_i;
if (rd0_i == 5'd15) reg_r15_q <= rd0_value_i;
if (rd0_i == 5'd16) reg_r16_q <= rd0_value_i;
if (rd0_i == 5'd17) reg_r17_q <= rd0_value_i;
if (rd0_i == 5'd18) reg_r18_q <= rd0_value_i;
if (rd0_i == 5'd19) reg_r19_q <= rd0_value_i;
if (rd0_i == 5'd20) reg_r20_q <= rd0_value_i;
if (rd0_i == 5'd21) reg_r21_q <= rd0_value_i;
if (rd0_i == 5'd22) reg_r22_q <= rd0_value_i;
if (rd0_i == 5'd23) reg_r23_q <= rd0_value_i;
if (rd0_i == 5'd24) reg_r24_q <= rd0_value_i;
if (rd0_i == 5'd25) reg_r25_q <= rd0_value_i;
if (rd0_i == 5'd26) reg_r26_q <= rd0_value_i;
if (rd0_i == 5'd27) reg_r27_q <= rd0_value_i;
if (rd0_i == 5'd28) reg_r28_q <= rd0_value_i;
if (rd0_i == 5'd29) reg_r29_q <= rd0_value_i;
if (rd0_i == 5'd30) reg_r30_q <= rd0_value_i;
if (rd0_i == 5'd31) reg_r31_q <= rd0_value_i;
end
//-----------------------------------------------------------------
// Asynchronous read
//-----------------------------------------------------------------
reg [31:0] ra0_value_r;
reg [31:0] rb0_value_r;
always @ *
begin
case (ra0_i)
5'd1: ra0_value_r = reg_r1_q;
5'd2: ra0_value_r = reg_r2_q;
5'd3: ra0_value_r = reg_r3_q;
5'd4: ra0_value_r = reg_r4_q;
5'd5: ra0_value_r = reg_r5_q;
5'd6: ra0_value_r = reg_r6_q;
5'd7: ra0_value_r = reg_r7_q;
5'd8: ra0_value_r = reg_r8_q;
5'd9: ra0_value_r = reg_r9_q;
5'd10: ra0_value_r = reg_r10_q;
5'd11: ra0_value_r = reg_r11_q;
5'd12: ra0_value_r = reg_r12_q;
5'd13: ra0_value_r = reg_r13_q;
5'd14: ra0_value_r = reg_r14_q;
5'd15: ra0_value_r = reg_r15_q;
5'd16: ra0_value_r = reg_r16_q;
5'd17: ra0_value_r = reg_r17_q;
5'd18: ra0_value_r = reg_r18_q;
5'd19: ra0_value_r = reg_r19_q;
5'd20: ra0_value_r = reg_r20_q;
5'd21: ra0_value_r = reg_r21_q;
5'd22: ra0_value_r = reg_r22_q;
5'd23: ra0_value_r = reg_r23_q;
5'd24: ra0_value_r = reg_r24_q;
5'd25: ra0_value_r = reg_r25_q;
5'd26: ra0_value_r = reg_r26_q;
5'd27: ra0_value_r = reg_r27_q;
5'd28: ra0_value_r = reg_r28_q;
5'd29: ra0_value_r = reg_r29_q;
5'd30: ra0_value_r = reg_r30_q;
5'd31: ra0_value_r = reg_r31_q;
default : ra0_value_r = 32'h00000000;
endcase
case (rb0_i)
5'd1: rb0_value_r = reg_r1_q;
5'd2: rb0_value_r = reg_r2_q;
5'd3: rb0_value_r = reg_r3_q;
5'd4: rb0_value_r = reg_r4_q;
5'd5: rb0_value_r = reg_r5_q;
5'd6: rb0_value_r = reg_r6_q;
5'd7: rb0_value_r = reg_r7_q;
5'd8: rb0_value_r = reg_r8_q;
5'd9: rb0_value_r = reg_r9_q;
5'd10: rb0_value_r = reg_r10_q;
5'd11: rb0_value_r = reg_r11_q;
5'd12: rb0_value_r = reg_r12_q;
5'd13: rb0_value_r = reg_r13_q;
5'd14: rb0_value_r = reg_r14_q;
5'd15: rb0_value_r = reg_r15_q;
5'd16: rb0_value_r = reg_r16_q;
5'd17: rb0_value_r = reg_r17_q;
5'd18: rb0_value_r = reg_r18_q;
5'd19: rb0_value_r = reg_r19_q;
5'd20: rb0_value_r = reg_r20_q;
5'd21: rb0_value_r = reg_r21_q;
5'd22: rb0_value_r = reg_r22_q;
5'd23: rb0_value_r = reg_r23_q;
5'd24: rb0_value_r = reg_r24_q;
5'd25: rb0_value_r = reg_r25_q;
5'd26: rb0_value_r = reg_r26_q;
5'd27: rb0_value_r = reg_r27_q;
5'd28: rb0_value_r = reg_r28_q;
5'd29: rb0_value_r = reg_r29_q;
5'd30: rb0_value_r = reg_r30_q;
5'd31: rb0_value_r = reg_r31_q;
default : rb0_value_r = 32'h00000000;
endcase
end
assign ra0_value_o = ra0_value_r;
assign rb0_value_o = rb0_value_r;
//-------------------------------------------------------------
// get_register: Read register file
//-------------------------------------------------------------
`ifdef verilator
function [31:0] get_register; /*verilator public*/
input [4:0] r;
begin
case (r)
5'd1: get_register = reg_r1_q;
5'd2: get_register = reg_r2_q;
5'd3: get_register = reg_r3_q;
5'd4: get_register = reg_r4_q;
5'd5: get_register = reg_r5_q;
5'd6: get_register = reg_r6_q;
5'd7: get_register = reg_r7_q;
5'd8: get_register = reg_r8_q;
5'd9: get_register = reg_r9_q;
5'd10: get_register = reg_r10_q;
5'd11: get_register = reg_r11_q;
5'd12: get_register = reg_r12_q;
5'd13: get_register = reg_r13_q;
5'd14: get_register = reg_r14_q;
5'd15: get_register = reg_r15_q;
5'd16: get_register = reg_r16_q;
5'd17: get_register = reg_r17_q;
5'd18: get_register = reg_r18_q;
5'd19: get_register = reg_r19_q;
5'd20: get_register = reg_r20_q;
5'd21: get_register = reg_r21_q;
5'd22: get_register = reg_r22_q;
5'd23: get_register = reg_r23_q;
5'd24: get_register = reg_r24_q;
5'd25: get_register = reg_r25_q;
5'd26: get_register = reg_r26_q;
5'd27: get_register = reg_r27_q;
5'd28: get_register = reg_r28_q;
5'd29: get_register = reg_r29_q;
5'd30: get_register = reg_r30_q;
5'd31: get_register = reg_r31_q;
default : get_register = 32'h00000000;
endcase
end
endfunction
//-------------------------------------------------------------
// set_register: Write register file
//-------------------------------------------------------------
function set_register; /*verilator public*/
input [4:0] r;
input [31:0] value;
begin
//case (r)
//5'd1: reg_r1_q <= value;
//5'd2: reg_r2_q <= value;
//5'd3: reg_r3_q <= value;
//5'd4: reg_r4_q <= value;
//5'd5: reg_r5_q <= value;
//5'd6: reg_r6_q <= value;
//5'd7: reg_r7_q <= value;
//5'd8: reg_r8_q <= value;
//5'd9: reg_r9_q <= value;
//5'd10: reg_r10_q <= value;
//5'd11: reg_r11_q <= value;
//5'd12: reg_r12_q <= value;
//5'd13: reg_r13_q <= value;
//5'd14: reg_r14_q <= value;
//5'd15: reg_r15_q <= value;
//5'd16: reg_r16_q <= value;
//5'd17: reg_r17_q <= value;
//5'd18: reg_r18_q <= value;
//5'd19: reg_r19_q <= value;
//5'd20: reg_r20_q <= value;
//5'd21: reg_r21_q <= value;
//5'd22: reg_r22_q <= value;
//5'd23: reg_r23_q <= value;
//5'd24: reg_r24_q <= value;
//5'd25: reg_r25_q <= value;
//5'd26: reg_r26_q <= value;
//5'd27: reg_r27_q <= value;
//5'd28: reg_r28_q <= value;
//5'd29: reg_r29_q <= value;
//5'd30: reg_r30_q <= value;
//5'd31: reg_r31_q <= value;
//default :
// ;
//endcase
end
endfunction
`endif
end
endgenerate
endmodule |
module riscv_issue
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter SUPPORT_DUAL_ISSUE = 1
,parameter SUPPORT_LOAD_BYPASS = 1
,parameter SUPPORT_MUL_BYPASS = 1
,parameter SUPPORT_REGFILE_XILINX = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input fetch_valid_i
,input [ 31:0] fetch_instr_i
,input [ 31:0] fetch_pc_i
,input fetch_fault_fetch_i
,input fetch_fault_page_i
,input fetch_instr_exec_i
,input fetch_instr_lsu_i
,input fetch_instr_branch_i
,input fetch_instr_mul_i
,input fetch_instr_div_i
,input fetch_instr_csr_i
,input fetch_instr_rd_valid_i
,input fetch_instr_invalid_i
,input branch_exec_request_i
,input branch_exec_is_taken_i
,input branch_exec_is_not_taken_i
,input [ 31:0] branch_exec_source_i
,input branch_exec_is_call_i
,input branch_exec_is_ret_i
,input branch_exec_is_jmp_i
,input [ 31:0] branch_exec_pc_i
,input branch_d_exec_request_i
,input [ 31:0] branch_d_exec_pc_i
,input [ 1:0] branch_d_exec_priv_i
,input branch_csr_request_i
,input [ 31:0] branch_csr_pc_i
,input [ 1:0] branch_csr_priv_i
,input [ 31:0] writeback_exec_value_i
,input writeback_mem_valid_i
,input [ 31:0] writeback_mem_value_i
,input [ 5:0] writeback_mem_exception_i
,input [ 31:0] writeback_mul_value_i
,input writeback_div_valid_i
,input [ 31:0] writeback_div_value_i
,input [ 31:0] csr_result_e1_value_i
,input csr_result_e1_write_i
,input [ 31:0] csr_result_e1_wdata_i
,input [ 5:0] csr_result_e1_exception_i
,input lsu_stall_i
,input take_interrupt_i
// Outputs
,output fetch_accept_o
,output branch_request_o
,output [ 31:0] branch_pc_o
,output [ 1:0] branch_priv_o
,output exec_opcode_valid_o
,output lsu_opcode_valid_o
,output csr_opcode_valid_o
,output mul_opcode_valid_o
,output div_opcode_valid_o
,output [ 31:0] opcode_opcode_o
,output [ 31:0] opcode_pc_o
,output opcode_invalid_o
,output [ 4:0] opcode_rd_idx_o
,output [ 4:0] opcode_ra_idx_o
,output [ 4:0] opcode_rb_idx_o
,output [ 31:0] opcode_ra_operand_o
,output [ 31:0] opcode_rb_operand_o
,output [ 31:0] lsu_opcode_opcode_o
,output [ 31:0] lsu_opcode_pc_o
,output lsu_opcode_invalid_o
,output [ 4:0] lsu_opcode_rd_idx_o
,output [ 4:0] lsu_opcode_ra_idx_o
,output [ 4:0] lsu_opcode_rb_idx_o
,output [ 31:0] lsu_opcode_ra_operand_o
,output [ 31:0] lsu_opcode_rb_operand_o
,output [ 31:0] mul_opcode_opcode_o
,output [ 31:0] mul_opcode_pc_o
,output mul_opcode_invalid_o
,output [ 4:0] mul_opcode_rd_idx_o
,output [ 4:0] mul_opcode_ra_idx_o
,output [ 4:0] mul_opcode_rb_idx_o
,output [ 31:0] mul_opcode_ra_operand_o
,output [ 31:0] mul_opcode_rb_operand_o
,output [ 31:0] csr_opcode_opcode_o
,output [ 31:0] csr_opcode_pc_o
,output csr_opcode_invalid_o
,output [ 4:0] csr_opcode_rd_idx_o
,output [ 4:0] csr_opcode_ra_idx_o
,output [ 4:0] csr_opcode_rb_idx_o
,output [ 31:0] csr_opcode_ra_operand_o
,output [ 31:0] csr_opcode_rb_operand_o
,output csr_writeback_write_o
,output [ 11:0] csr_writeback_waddr_o
,output [ 31:0] csr_writeback_wdata_o
,output [ 5:0] csr_writeback_exception_o
,output [ 31:0] csr_writeback_exception_pc_o
,output [ 31:0] csr_writeback_exception_addr_o
,output exec_hold_o
,output mul_hold_o
,output interrupt_inhibit_o
);
`include "riscv_defs.v"
wire enable_muldiv_w = SUPPORT_MULDIV;
wire enable_mul_bypass_w = SUPPORT_MUL_BYPASS;
wire stall_w;
wire squash_w;
//-------------------------------------------------------------
// Priv level
//-------------------------------------------------------------
reg [1:0] priv_x_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
priv_x_q <= `PRIV_MACHINE;
else if (branch_csr_request_i)
priv_x_q <= branch_csr_priv_i;
//-------------------------------------------------------------
// Issue Select
//-------------------------------------------------------------
wire opcode_valid_w = fetch_valid_i & ~squash_w & ~branch_csr_request_i;
// Branch request (CSR branch - ecall, xret, or branch instruction)
assign branch_request_o = branch_csr_request_i | branch_d_exec_request_i;
assign branch_pc_o = branch_csr_request_i ? branch_csr_pc_i : branch_d_exec_pc_i;
assign branch_priv_o = branch_csr_request_i ? branch_csr_priv_i : priv_x_q;
//-------------------------------------------------------------
// Instruction Decoder
//-------------------------------------------------------------
wire [4:0] issue_ra_idx_w = fetch_instr_i[19:15];
wire [4:0] issue_rb_idx_w = fetch_instr_i[24:20];
wire [4:0] issue_rd_idx_w = fetch_instr_i[11:7];
wire issue_sb_alloc_w = fetch_instr_rd_valid_i;
wire issue_exec_w = fetch_instr_exec_i;
wire issue_lsu_w = fetch_instr_lsu_i;
wire issue_branch_w = fetch_instr_branch_i;
wire issue_mul_w = fetch_instr_mul_i;
wire issue_div_w = fetch_instr_div_i;
wire issue_csr_w = fetch_instr_csr_i;
wire issue_invalid_w = fetch_instr_invalid_i;
//-------------------------------------------------------------
// Pipeline status tracking
//-------------------------------------------------------------
wire pipe_squash_e1_e2_w;
reg opcode_issue_r;
reg opcode_accept_r;
wire pipe_stall_raw_w;
wire pipe_load_e1_w;
wire pipe_store_e1_w;
wire pipe_mul_e1_w;
wire pipe_branch_e1_w;
wire [4:0] pipe_rd_e1_w;
wire [31:0] pipe_pc_e1_w;
wire [31:0] pipe_opcode_e1_w;
wire [31:0] pipe_operand_ra_e1_w;
wire [31:0] pipe_operand_rb_e1_w;
wire pipe_load_e2_w;
wire pipe_mul_e2_w;
wire [4:0] pipe_rd_e2_w;
wire [31:0] pipe_result_e2_w;
wire pipe_valid_wb_w;
wire pipe_csr_wb_w;
wire [4:0] pipe_rd_wb_w;
wire [31:0] pipe_result_wb_w;
wire [31:0] pipe_pc_wb_w;
wire [31:0] pipe_opc_wb_w;
wire [31:0] pipe_ra_val_wb_w;
wire [31:0] pipe_rb_val_wb_w;
wire [`EXCEPTION_W-1:0] pipe_exception_wb_w;
wire [`EXCEPTION_W-1:0] issue_fault_w = fetch_fault_fetch_i ? `EXCEPTION_FAULT_FETCH:
fetch_fault_page_i ? `EXCEPTION_PAGE_FAULT_INST: `EXCEPTION_W'b0;
riscv_pipe_ctrl
#(
.SUPPORT_LOAD_BYPASS(SUPPORT_LOAD_BYPASS)
,.SUPPORT_MUL_BYPASS(SUPPORT_MUL_BYPASS)
)
u_pipe_ctrl
(
.clk_i(clk_i)
,.rst_i(rst_i)
// Issue
,.issue_valid_i(opcode_issue_r)
,.issue_accept_i(opcode_accept_r)
,.issue_stall_i(stall_w)
,.issue_lsu_i(issue_lsu_w)
,.issue_csr_i(issue_csr_w)
,.issue_div_i(issue_div_w)
,.issue_mul_i(issue_mul_w)
,.issue_branch_i(issue_branch_w)
,.issue_rd_valid_i(issue_sb_alloc_w)
,.issue_rd_i(issue_rd_idx_w)
,.issue_exception_i(issue_fault_w)
,.issue_pc_i(opcode_pc_o)
,.issue_opcode_i(opcode_opcode_o)
,.issue_operand_ra_i(opcode_ra_operand_o)
,.issue_operand_rb_i(opcode_rb_operand_o)
,.issue_branch_taken_i(branch_d_exec_request_i)
,.issue_branch_target_i(branch_d_exec_pc_i)
,.take_interrupt_i(take_interrupt_i)
// Execution stage 1: ALU result
,.alu_result_e1_i(writeback_exec_value_i)
,.csr_result_value_e1_i(csr_result_e1_value_i)
,.csr_result_write_e1_i(csr_result_e1_write_i)
,.csr_result_wdata_e1_i(csr_result_e1_wdata_i)
,.csr_result_exception_e1_i(csr_result_e1_exception_i)
// Execution stage 1
,.load_e1_o(pipe_load_e1_w)
,.store_e1_o(pipe_store_e1_w)
,.mul_e1_o(pipe_mul_e1_w)
,.branch_e1_o(pipe_branch_e1_w)
,.rd_e1_o(pipe_rd_e1_w)
,.pc_e1_o(pipe_pc_e1_w)
,.opcode_e1_o(pipe_opcode_e1_w)
,.operand_ra_e1_o(pipe_operand_ra_e1_w)
,.operand_rb_e1_o(pipe_operand_rb_e1_w)
// Execution stage 2: Other results
,.mem_complete_i(writeback_mem_valid_i)
,.mem_result_e2_i(writeback_mem_value_i)
,.mem_exception_e2_i(writeback_mem_exception_i)
,.mul_result_e2_i(writeback_mul_value_i)
// Execution stage 2
,.load_e2_o(pipe_load_e2_w)
,.mul_e2_o(pipe_mul_e2_w)
,.rd_e2_o(pipe_rd_e2_w)
,.result_e2_o(pipe_result_e2_w)
,.stall_o(pipe_stall_raw_w)
,.squash_e1_e2_o(pipe_squash_e1_e2_w)
,.squash_e1_e2_i(1'b0)
,.squash_wb_i(1'b0)
// Out of pipe: Divide Result
,.div_complete_i(writeback_div_valid_i)
,.div_result_i(writeback_div_value_i)
// Commit
,.valid_wb_o(pipe_valid_wb_w)
,.csr_wb_o(pipe_csr_wb_w)
,.rd_wb_o(pipe_rd_wb_w)
,.result_wb_o(pipe_result_wb_w)
,.pc_wb_o(pipe_pc_wb_w)
,.opcode_wb_o(pipe_opc_wb_w)
,.operand_ra_wb_o(pipe_ra_val_wb_w)
,.operand_rb_wb_o(pipe_rb_val_wb_w)
,.exception_wb_o(pipe_exception_wb_w)
,.csr_write_wb_o(csr_writeback_write_o)
,.csr_waddr_wb_o(csr_writeback_waddr_o)
,.csr_wdata_wb_o(csr_writeback_wdata_o)
);
assign exec_hold_o = stall_w;
assign mul_hold_o = stall_w;
//-------------------------------------------------------------
// Pipe1 - Status tracking
//-------------------------------------------------------------
assign csr_writeback_exception_o = pipe_exception_wb_w;
assign csr_writeback_exception_pc_o = pipe_pc_wb_w;
assign csr_writeback_exception_addr_o = pipe_result_wb_w;
//-------------------------------------------------------------
// Blocking events (division, CSR unit access)
//-------------------------------------------------------------
reg div_pending_q;
reg csr_pending_q;
// Division operations take 2 - 34 cycles and stall
// the pipeline (complete out-of-pipe) until completed.
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
div_pending_q <= 1'b0;
else if (pipe_squash_e1_e2_w)
div_pending_q <= 1'b0;
else if (div_opcode_valid_o && issue_div_w)
div_pending_q <= 1'b1;
else if (writeback_div_valid_i)
div_pending_q <= 1'b0;
// CSR operations are infrequent - avoid any complications of pipelining them.
// These only take a 2-3 cycles anyway and may result in a pipe flush (e.g. ecall, ebreak..).
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
csr_pending_q <= 1'b0;
else if (pipe_squash_e1_e2_w)
csr_pending_q <= 1'b0;
else if (csr_opcode_valid_o && issue_csr_w)
csr_pending_q <= 1'b1;
else if (pipe_csr_wb_w)
csr_pending_q <= 1'b0;
assign squash_w = pipe_squash_e1_e2_w;
//-------------------------------------------------------------
// Issue / scheduling logic
//-------------------------------------------------------------
reg [31:0] scoreboard_r;
always @ *
begin
opcode_issue_r = 1'b0;
opcode_accept_r = 1'b0;
scoreboard_r = 32'b0;
// Execution units with >= 2 cycle latency
if (SUPPORT_LOAD_BYPASS == 0)
begin
if (pipe_load_e2_w)
scoreboard_r[pipe_rd_e2_w] = 1'b1;
end
if (SUPPORT_MUL_BYPASS == 0)
begin
if (pipe_mul_e2_w)
scoreboard_r[pipe_rd_e2_w] = 1'b1;
end
// Execution units with >= 1 cycle latency (loads / multiply)
if (pipe_load_e1_w || pipe_mul_e1_w)
scoreboard_r[pipe_rd_e1_w] = 1'b1;
// Do not start multiply, division or CSR operation in the cycle after a load (leaving only ALU operations and branches)
if ((pipe_load_e1_w || pipe_store_e1_w) && (issue_mul_w || issue_div_w || issue_csr_w))
scoreboard_r = 32'hFFFFFFFF;
// Stall - no issues...
if (lsu_stall_i || stall_w || div_pending_q || csr_pending_q)
;
// Primary slot (lsu, branch, alu, mul, div, csr)
else if (opcode_valid_w &&
!(scoreboard_r[issue_ra_idx_w] ||
scoreboard_r[issue_rb_idx_w] ||
scoreboard_r[issue_rd_idx_w]))
begin
opcode_issue_r = 1'b1;
opcode_accept_r = 1'b1;
if (opcode_accept_r && issue_sb_alloc_w && (|issue_rd_idx_w))
scoreboard_r[issue_rd_idx_w] = 1'b1;
end
end
assign lsu_opcode_valid_o = opcode_issue_r & ~take_interrupt_i;
assign exec_opcode_valid_o = opcode_issue_r;
assign mul_opcode_valid_o = enable_muldiv_w & opcode_issue_r;
assign div_opcode_valid_o = enable_muldiv_w & opcode_issue_r;
assign interrupt_inhibit_o = csr_pending_q || issue_csr_w;
assign fetch_accept_o = opcode_valid_w ? (opcode_accept_r & ~take_interrupt_i) : 1'b1;
assign stall_w = pipe_stall_raw_w;
//-------------------------------------------------------------
// Register File
//-------------------------------------------------------------
wire [31:0] issue_ra_value_w;
wire [31:0] issue_rb_value_w;
wire [31:0] issue_b_ra_value_w;
wire [31:0] issue_b_rb_value_w;
// Register file: 1W2R
riscv_regfile
#(
.SUPPORT_REGFILE_XILINX(SUPPORT_REGFILE_XILINX)
)
u_regfile
(
.clk_i(clk_i),
.rst_i(rst_i),
// Write ports
.rd0_i(pipe_rd_wb_w),
.rd0_value_i(pipe_result_wb_w),
// Read ports
.ra0_i(issue_ra_idx_w),
.rb0_i(issue_rb_idx_w),
.ra0_value_o(issue_ra_value_w),
.rb0_value_o(issue_rb_value_w)
);
//-------------------------------------------------------------
// Issue Slot 0
//-------------------------------------------------------------
assign opcode_opcode_o = fetch_instr_i;
assign opcode_pc_o = fetch_pc_i;
assign opcode_rd_idx_o = issue_rd_idx_w;
assign opcode_ra_idx_o = issue_ra_idx_w;
assign opcode_rb_idx_o = issue_rb_idx_w;
assign opcode_invalid_o= 1'b0;
reg [31:0] issue_ra_value_r;
reg [31:0] issue_rb_value_r;
always @ *
begin
// NOTE: Newest version of operand takes priority
issue_ra_value_r = issue_ra_value_w;
issue_rb_value_r = issue_rb_value_w;
// Bypass - WB
if (pipe_rd_wb_w == issue_ra_idx_w)
issue_ra_value_r = pipe_result_wb_w;
if (pipe_rd_wb_w == issue_rb_idx_w)
issue_rb_value_r = pipe_result_wb_w;
// Bypass - E2
if (pipe_rd_e2_w == issue_ra_idx_w)
issue_ra_value_r = pipe_result_e2_w;
if (pipe_rd_e2_w == issue_rb_idx_w)
issue_rb_value_r = pipe_result_e2_w;
// Bypass - E1
if (pipe_rd_e1_w == issue_ra_idx_w)
issue_ra_value_r = writeback_exec_value_i;
if (pipe_rd_e1_w == issue_rb_idx_w)
issue_rb_value_r = writeback_exec_value_i;
// Reg 0 source
if (issue_ra_idx_w == 5'b0)
issue_ra_value_r = 32'b0;
if (issue_rb_idx_w == 5'b0)
issue_rb_value_r = 32'b0;
end
assign opcode_ra_operand_o = issue_ra_value_r;
assign opcode_rb_operand_o = issue_rb_value_r;
//-------------------------------------------------------------
// Load store unit
//-------------------------------------------------------------
assign lsu_opcode_opcode_o = opcode_opcode_o;
assign lsu_opcode_pc_o = opcode_pc_o;
assign lsu_opcode_rd_idx_o = opcode_rd_idx_o;
assign lsu_opcode_ra_idx_o = opcode_ra_idx_o;
assign lsu_opcode_rb_idx_o = opcode_rb_idx_o;
assign lsu_opcode_ra_operand_o = opcode_ra_operand_o;
assign lsu_opcode_rb_operand_o = opcode_rb_operand_o;
assign lsu_opcode_invalid_o = 1'b0;
//-------------------------------------------------------------
// Multiply
//-------------------------------------------------------------
assign mul_opcode_opcode_o = opcode_opcode_o;
assign mul_opcode_pc_o = opcode_pc_o;
assign mul_opcode_rd_idx_o = opcode_rd_idx_o;
assign mul_opcode_ra_idx_o = opcode_ra_idx_o;
assign mul_opcode_rb_idx_o = opcode_rb_idx_o;
assign mul_opcode_ra_operand_o = opcode_ra_operand_o;
assign mul_opcode_rb_operand_o = opcode_rb_operand_o;
assign mul_opcode_invalid_o = 1'b0;
//-------------------------------------------------------------
// CSR unit
//-------------------------------------------------------------
assign csr_opcode_valid_o = opcode_issue_r & ~take_interrupt_i;
assign csr_opcode_opcode_o = opcode_opcode_o;
assign csr_opcode_pc_o = opcode_pc_o;
assign csr_opcode_rd_idx_o = opcode_rd_idx_o;
assign csr_opcode_ra_idx_o = opcode_ra_idx_o;
assign csr_opcode_rb_idx_o = opcode_rb_idx_o;
assign csr_opcode_ra_operand_o = opcode_ra_operand_o;
assign csr_opcode_rb_operand_o = opcode_rb_operand_o;
assign csr_opcode_invalid_o = opcode_issue_r && issue_invalid_w;
//-------------------------------------------------------------
// Checker Interface
//-------------------------------------------------------------
`ifdef verilator
riscv_trace_sim
u_pipe_dec0_verif
(
.valid_i(pipe_valid_wb_w)
,.pc_i(pipe_pc_wb_w)
,.opcode_i(pipe_opc_wb_w)
);
wire [4:0] v_pipe_rs1_w = pipe_opc_wb_w[19:15];
wire [4:0] v_pipe_rs2_w = pipe_opc_wb_w[24:20];
function [0:0] complete_valid0; /*verilator public*/
begin
complete_valid0 = pipe_valid_wb_w;
end
endfunction
function [31:0] complete_pc0; /*verilator public*/
begin
complete_pc0 = pipe_pc_wb_w;
end
endfunction
function [31:0] complete_opcode0; /*verilator public*/
begin
complete_opcode0 = pipe_opc_wb_w;
end
endfunction
function [4:0] complete_ra0; /*verilator public*/
begin
complete_ra0 = v_pipe_rs1_w;
end
endfunction
function [4:0] complete_rb0; /*verilator public*/
begin
complete_rb0 = v_pipe_rs2_w;
end
endfunction
function [4:0] complete_rd0; /*verilator public*/
begin
complete_rd0 = pipe_rd_wb_w;
end
endfunction
function [31:0] complete_ra_val0; /*verilator public*/
begin
complete_ra_val0 = pipe_ra_val_wb_w;
end
endfunction
function [31:0] complete_rb_val0; /*verilator public*/
begin
complete_rb_val0 = pipe_rb_val_wb_w;
end
endfunction
function [31:0] complete_rd_val0; /*verilator public*/
begin
if (|pipe_rd_wb_w)
complete_rd_val0 = pipe_result_wb_w;
else
complete_rd_val0 = 32'b0;
end
endfunction
function [5:0] complete_exception; /*verilator public*/
begin
complete_exception = pipe_exception_wb_w;
end
endfunction
`endif
endmodule |
module riscv_csr
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter SUPPORT_SUPER = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input intr_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input csr_writeback_write_i
,input [ 11:0] csr_writeback_waddr_i
,input [ 31:0] csr_writeback_wdata_i
,input [ 5:0] csr_writeback_exception_i
,input [ 31:0] csr_writeback_exception_pc_i
,input [ 31:0] csr_writeback_exception_addr_i
,input [ 31:0] cpu_id_i
,input [ 31:0] reset_vector_i
,input interrupt_inhibit_i
// Outputs
,output [ 31:0] csr_result_e1_value_o
,output csr_result_e1_write_o
,output [ 31:0] csr_result_e1_wdata_o
,output [ 5:0] csr_result_e1_exception_o
,output branch_csr_request_o
,output [ 31:0] branch_csr_pc_o
,output [ 1:0] branch_csr_priv_o
,output take_interrupt_o
,output ifence_o
,output [ 1:0] mmu_priv_d_o
,output mmu_sum_o
,output mmu_mxr_o
,output mmu_flush_o
,output [ 31:0] mmu_satp_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire ecall_w = opcode_valid_i && ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL);
wire ebreak_w = opcode_valid_i && ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK);
wire eret_w = opcode_valid_i && ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET);
wire [1:0] eret_priv_w = opcode_opcode_i[29:28];
wire csrrw_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW);
wire csrrs_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS);
wire csrrc_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC);
wire csrrwi_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI);
wire csrrsi_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI);
wire csrrci_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI);
wire wfi_w = opcode_valid_i && ((opcode_opcode_i & `INST_WFI_MASK) == `INST_WFI);
wire fence_w = opcode_valid_i && ((opcode_opcode_i & `INST_FENCE_MASK) == `INST_FENCE);
wire sfence_w = opcode_valid_i && ((opcode_opcode_i & `INST_SFENCE_MASK) == `INST_SFENCE);
wire ifence_w = opcode_valid_i && ((opcode_opcode_i & `INST_IFENCE_MASK) == `INST_IFENCE);
//-----------------------------------------------------------------
// CSR handling
//-----------------------------------------------------------------
wire [1:0] current_priv_w;
reg [1:0] csr_priv_r;
reg csr_readonly_r;
reg csr_write_r;
reg set_r;
reg clr_r;
reg csr_fault_r;
reg [31:0] data_r;
always @ *
begin
set_r = csrrw_w | csrrs_w | csrrwi_w | csrrsi_w;
clr_r = csrrw_w | csrrc_w | csrrwi_w | csrrci_w;
csr_priv_r = opcode_opcode_i[29:28];
csr_readonly_r = (opcode_opcode_i[31:30] == 2'd3);
csr_write_r = (opcode_ra_idx_i != 5'b0) | csrrw_w | csrrwi_w;
data_r = (csrrwi_w |
csrrsi_w |
csrrci_w) ?
{27'b0, opcode_ra_idx_i} : opcode_ra_operand_i;
// Detect access fault on CSR access
csr_fault_r = SUPPORT_SUPER ? (opcode_valid_i && (set_r | clr_r) && ((csr_write_r && csr_readonly_r) || (current_priv_w < csr_priv_r))) : 1'b0;
end
wire satp_update_w = (opcode_valid_i && (set_r || clr_r) && csr_write_r && (opcode_opcode_i[31:20] == `CSR_SATP));
//-----------------------------------------------------------------
// CSR register file
//-----------------------------------------------------------------
wire timer_irq_w = 1'b0;
wire [31:0] misa_w = SUPPORT_MULDIV ? (`MISA_RV32 | `MISA_RVI | `MISA_RVM): (`MISA_RV32 | `MISA_RVI);
wire [31:0] csr_rdata_w;
wire csr_branch_w;
wire [31:0] csr_target_w;
wire [31:0] interrupt_w;
wire [31:0] status_reg_w;
wire [31:0] satp_reg_w;
riscv_csr_regfile
#( .SUPPORT_MTIMECMP(1)
,.SUPPORT_SUPER(SUPPORT_SUPER) )
u_csrfile
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.ext_intr_i(intr_i)
,.timer_intr_i(timer_irq_w)
,.cpu_id_i(cpu_id_i)
,.misa_i(misa_w)
// Issue
,.csr_ren_i(opcode_valid_i)
,.csr_raddr_i(opcode_opcode_i[31:20])
,.csr_rdata_o(csr_rdata_w)
// Exception (WB)
,.exception_i(csr_writeback_exception_i)
,.exception_pc_i(csr_writeback_exception_pc_i)
,.exception_addr_i(csr_writeback_exception_addr_i)
// CSR register writes (WB)
,.csr_waddr_i(csr_writeback_write_i ? csr_writeback_waddr_i : 12'b0)
,.csr_wdata_i(csr_writeback_wdata_i)
// CSR branches
,.csr_branch_o(csr_branch_w)
,.csr_target_o(csr_target_w)
// Various CSR registers
,.priv_o(current_priv_w)
,.status_o(status_reg_w)
,.satp_o(satp_reg_w)
// Masked interrupt output
,.interrupt_o(interrupt_w)
);
//-----------------------------------------------------------------
// CSR Read Result (E1) / Early exceptions
//-----------------------------------------------------------------
reg rd_valid_e1_q;
reg [ 31:0] rd_result_e1_q;
reg [ 31:0] csr_wdata_e1_q;
reg [`EXCEPTION_W-1:0] exception_e1_q;
// Inappropriate xRET for the current exec priv level
wire eret_fault_w = eret_w && (current_priv_w < eret_priv_w);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
rd_valid_e1_q <= 1'b0;
rd_result_e1_q <= 32'b0;
csr_wdata_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
else if (opcode_valid_i)
begin
rd_valid_e1_q <= (set_r || clr_r) && ~csr_fault_r;
// Invalid instruction / CSR access fault?
// Record opcode for writing to csr_xtval later.
if (opcode_invalid_i || csr_fault_r || eret_fault_w)
rd_result_e1_q <= opcode_opcode_i;
else
rd_result_e1_q <= csr_rdata_w;
// E1 CSR exceptions
if ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL)
exception_e1_q <= `EXCEPTION_ECALL + {4'b0, current_priv_w};
// xRET for priv level above this one - fault
else if (eret_fault_w)
exception_e1_q <= `EXCEPTION_ILLEGAL_INSTRUCTION;
else if ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET)
exception_e1_q <= `EXCEPTION_ERET_U + {4'b0, eret_priv_w};
else if ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK)
exception_e1_q <= `EXCEPTION_BREAKPOINT;
else if (opcode_invalid_i || csr_fault_r)
exception_e1_q <= `EXCEPTION_ILLEGAL_INSTRUCTION;
// Fence / MMU settings cause a pipeline flush
else if (satp_update_w || ifence_w || sfence_w)
exception_e1_q <= `EXCEPTION_FENCE;
else
exception_e1_q <= `EXCEPTION_W'b0;
// Value to be written to CSR registers
if (set_r && clr_r)
csr_wdata_e1_q <= data_r;
else if (set_r)
csr_wdata_e1_q <= csr_rdata_w | data_r;
else if (clr_r)
csr_wdata_e1_q <= csr_rdata_w & ~data_r;
end
else
begin
rd_valid_e1_q <= 1'b0;
rd_result_e1_q <= 32'b0;
csr_wdata_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
assign csr_result_e1_value_o = rd_result_e1_q;
assign csr_result_e1_write_o = rd_valid_e1_q;
assign csr_result_e1_wdata_o = csr_wdata_e1_q;
assign csr_result_e1_exception_o = exception_e1_q;
//-----------------------------------------------------------------
// Interrupt launch enable
//-----------------------------------------------------------------
reg take_interrupt_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
take_interrupt_q <= 1'b0;
else
take_interrupt_q <= (|interrupt_w) & ~interrupt_inhibit_i;
assign take_interrupt_o = take_interrupt_q;
//-----------------------------------------------------------------
// TLB flush
//-----------------------------------------------------------------
reg tlb_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tlb_flush_q <= 1'b0;
else
tlb_flush_q <= satp_update_w || sfence_w;
//-----------------------------------------------------------------
// ifence
//-----------------------------------------------------------------
reg ifence_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ifence_q <= 1'b0;
else
ifence_q <= ifence_w;
assign ifence_o = ifence_q;
//-----------------------------------------------------------------
// Execute - Branch operations
//-----------------------------------------------------------------
reg branch_q;
reg [31:0] branch_target_q;
reg reset_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
branch_target_q <= 32'b0;
branch_q <= 1'b0;
reset_q <= 1'b1;
end
else if (reset_q)
begin
branch_target_q <= reset_vector_i;
branch_q <= 1'b1;
reset_q <= 1'b0;
end
else
begin
branch_q <= csr_branch_w;
branch_target_q <= csr_target_w;
end
assign branch_csr_request_o = branch_q;
assign branch_csr_pc_o = branch_target_q;
assign branch_csr_priv_o = satp_reg_w[`SATP_MODE_R] ? current_priv_w : `PRIV_MACHINE;
//-----------------------------------------------------------------
// MMU
//-----------------------------------------------------------------
assign mmu_priv_d_o = status_reg_w[`SR_MPRV_R] ? status_reg_w[`SR_MPP_R] : current_priv_w;
assign mmu_satp_o = satp_reg_w;
assign mmu_flush_o = tlb_flush_q;
assign mmu_sum_o = status_reg_w[`SR_SUM_R];
assign mmu_mxr_o = status_reg_w[`SR_MXR_R];
endmodule |
module riscv_decode
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter EXTRA_DECODE_STAGE = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input fetch_in_valid_i
,input [ 31:0] fetch_in_instr_i
,input [ 31:0] fetch_in_pc_i
,input fetch_in_fault_fetch_i
,input fetch_in_fault_page_i
,input fetch_out_accept_i
,input squash_decode_i
// Outputs
,output fetch_in_accept_o
,output fetch_out_valid_o
,output [ 31:0] fetch_out_instr_o
,output [ 31:0] fetch_out_pc_o
,output fetch_out_fault_fetch_o
,output fetch_out_fault_page_o
,output fetch_out_instr_exec_o
,output fetch_out_instr_lsu_o
,output fetch_out_instr_branch_o
,output fetch_out_instr_mul_o
,output fetch_out_instr_div_o
,output fetch_out_instr_csr_o
,output fetch_out_instr_rd_valid_o
,output fetch_out_instr_invalid_o
);
wire enable_muldiv_w = SUPPORT_MULDIV;
//-----------------------------------------------------------------
// Extra decode stage (to improve cycle time)
//-----------------------------------------------------------------
generate
if (EXTRA_DECODE_STAGE)
begin
wire [31:0] fetch_in_instr_w = (fetch_in_fault_page_i | fetch_in_fault_fetch_i) ? 32'b0 : fetch_in_instr_i;
reg [66:0] buffer_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
buffer_q <= 67'b0;
else if (squash_decode_i)
buffer_q <= 67'b0;
else if (fetch_out_accept_i || !fetch_out_valid_o)
buffer_q <= {fetch_in_valid_i, fetch_in_fault_page_i, fetch_in_fault_fetch_i, fetch_in_instr_w, fetch_in_pc_i};
assign {fetch_out_valid_o,
fetch_out_fault_page_o,
fetch_out_fault_fetch_o,
fetch_out_instr_o,
fetch_out_pc_o} = buffer_q;
riscv_decoder
u_dec
(
.valid_i(fetch_out_valid_o)
,.fetch_fault_i(fetch_out_fault_page_o | fetch_out_fault_fetch_o)
,.enable_muldiv_i(enable_muldiv_w)
,.opcode_i(fetch_out_instr_o)
,.invalid_o(fetch_out_instr_invalid_o)
,.exec_o(fetch_out_instr_exec_o)
,.lsu_o(fetch_out_instr_lsu_o)
,.branch_o(fetch_out_instr_branch_o)
,.mul_o(fetch_out_instr_mul_o)
,.div_o(fetch_out_instr_div_o)
,.csr_o(fetch_out_instr_csr_o)
,.rd_valid_o(fetch_out_instr_rd_valid_o)
);
assign fetch_in_accept_o = fetch_out_accept_i;
end
//-----------------------------------------------------------------
// Straight through decode
//-----------------------------------------------------------------
else
begin
wire [31:0] fetch_in_instr_w = (fetch_in_fault_page_i | fetch_in_fault_fetch_i) ? 32'b0 : fetch_in_instr_i;
riscv_decoder
u_dec
(
.valid_i(fetch_in_valid_i)
,.fetch_fault_i(fetch_in_fault_fetch_i | fetch_in_fault_page_i)
,.enable_muldiv_i(enable_muldiv_w)
,.opcode_i(fetch_out_instr_o)
,.invalid_o(fetch_out_instr_invalid_o)
,.exec_o(fetch_out_instr_exec_o)
,.lsu_o(fetch_out_instr_lsu_o)
,.branch_o(fetch_out_instr_branch_o)
,.mul_o(fetch_out_instr_mul_o)
,.div_o(fetch_out_instr_div_o)
,.csr_o(fetch_out_instr_csr_o)
,.rd_valid_o(fetch_out_instr_rd_valid_o)
);
// Outputs
assign fetch_out_valid_o = fetch_in_valid_i;
assign fetch_out_pc_o = fetch_in_pc_i;
assign fetch_out_instr_o = fetch_in_instr_w;
assign fetch_out_fault_page_o = fetch_in_fault_page_i;
assign fetch_out_fault_fetch_o = fetch_in_fault_fetch_i;
assign fetch_in_accept_o = fetch_out_accept_i;
end
endgenerate
endmodule |
module riscv_decoder
(
input valid_i
,input fetch_fault_i
,input enable_muldiv_i
,input [31:0] opcode_i
,output invalid_o
,output exec_o
,output lsu_o
,output branch_o
,output mul_o
,output div_o
,output csr_o
,output rd_valid_o
);
// Invalid instruction
wire invalid_w = valid_i &&
~(((opcode_i & `INST_ANDI_MASK) == `INST_ANDI) ||
((opcode_i & `INST_ADDI_MASK) == `INST_ADDI) ||
((opcode_i & `INST_SLTI_MASK) == `INST_SLTI) ||
((opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU) ||
((opcode_i & `INST_ORI_MASK) == `INST_ORI) ||
((opcode_i & `INST_XORI_MASK) == `INST_XORI) ||
((opcode_i & `INST_SLLI_MASK) == `INST_SLLI) ||
((opcode_i & `INST_SRLI_MASK) == `INST_SRLI) ||
((opcode_i & `INST_SRAI_MASK) == `INST_SRAI) ||
((opcode_i & `INST_LUI_MASK) == `INST_LUI) ||
((opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC) ||
((opcode_i & `INST_ADD_MASK) == `INST_ADD) ||
((opcode_i & `INST_SUB_MASK) == `INST_SUB) ||
((opcode_i & `INST_SLT_MASK) == `INST_SLT) ||
((opcode_i & `INST_SLTU_MASK) == `INST_SLTU) ||
((opcode_i & `INST_XOR_MASK) == `INST_XOR) ||
((opcode_i & `INST_OR_MASK) == `INST_OR) ||
((opcode_i & `INST_AND_MASK) == `INST_AND) ||
((opcode_i & `INST_SLL_MASK) == `INST_SLL) ||
((opcode_i & `INST_SRL_MASK) == `INST_SRL) ||
((opcode_i & `INST_SRA_MASK) == `INST_SRA) ||
((opcode_i & `INST_JAL_MASK) == `INST_JAL) ||
((opcode_i & `INST_JALR_MASK) == `INST_JALR) ||
((opcode_i & `INST_BEQ_MASK) == `INST_BEQ) ||
((opcode_i & `INST_BNE_MASK) == `INST_BNE) ||
((opcode_i & `INST_BLT_MASK) == `INST_BLT) ||
((opcode_i & `INST_BGE_MASK) == `INST_BGE) ||
((opcode_i & `INST_BLTU_MASK) == `INST_BLTU) ||
((opcode_i & `INST_BGEU_MASK) == `INST_BGEU) ||
((opcode_i & `INST_LB_MASK) == `INST_LB) ||
((opcode_i & `INST_LH_MASK) == `INST_LH) ||
((opcode_i & `INST_LW_MASK) == `INST_LW) ||
((opcode_i & `INST_LBU_MASK) == `INST_LBU) ||
((opcode_i & `INST_LHU_MASK) == `INST_LHU) ||
((opcode_i & `INST_LWU_MASK) == `INST_LWU) ||
((opcode_i & `INST_SB_MASK) == `INST_SB) ||
((opcode_i & `INST_SH_MASK) == `INST_SH) ||
((opcode_i & `INST_SW_MASK) == `INST_SW) ||
((opcode_i & `INST_ECALL_MASK) == `INST_ECALL) ||
((opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK) ||
((opcode_i & `INST_ERET_MASK) == `INST_ERET) ||
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) ||
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) ||
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) ||
((opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI) ||
((opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI) ||
((opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI) ||
((opcode_i & `INST_WFI_MASK) == `INST_WFI) ||
((opcode_i & `INST_FENCE_MASK) == `INST_FENCE) ||
((opcode_i & `INST_IFENCE_MASK) == `INST_IFENCE) ||
((opcode_i & `INST_SFENCE_MASK) == `INST_SFENCE) ||
(enable_muldiv_i && (opcode_i & `INST_MUL_MASK) == `INST_MUL) ||
(enable_muldiv_i && (opcode_i & `INST_MULH_MASK) == `INST_MULH) ||
(enable_muldiv_i && (opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) ||
(enable_muldiv_i && (opcode_i & `INST_MULHU_MASK) == `INST_MULHU) ||
(enable_muldiv_i && (opcode_i & `INST_DIV_MASK) == `INST_DIV) ||
(enable_muldiv_i && (opcode_i & `INST_DIVU_MASK) == `INST_DIVU) ||
(enable_muldiv_i && (opcode_i & `INST_REM_MASK) == `INST_REM) ||
(enable_muldiv_i && (opcode_i & `INST_REMU_MASK) == `INST_REMU));
assign invalid_o = invalid_w;
assign rd_valid_o = ((opcode_i & `INST_JALR_MASK) == `INST_JALR) ||
((opcode_i & `INST_JAL_MASK) == `INST_JAL) ||
((opcode_i & `INST_LUI_MASK) == `INST_LUI) ||
((opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC) ||
((opcode_i & `INST_ADDI_MASK) == `INST_ADDI) ||
((opcode_i & `INST_SLLI_MASK) == `INST_SLLI) ||
((opcode_i & `INST_SLTI_MASK) == `INST_SLTI) ||
((opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU) ||
((opcode_i & `INST_XORI_MASK) == `INST_XORI) ||
((opcode_i & `INST_SRLI_MASK) == `INST_SRLI) ||
((opcode_i & `INST_SRAI_MASK) == `INST_SRAI) ||
((opcode_i & `INST_ORI_MASK) == `INST_ORI) ||
((opcode_i & `INST_ANDI_MASK) == `INST_ANDI) ||
((opcode_i & `INST_ADD_MASK) == `INST_ADD) ||
((opcode_i & `INST_SUB_MASK) == `INST_SUB) ||
((opcode_i & `INST_SLL_MASK) == `INST_SLL) ||
((opcode_i & `INST_SLT_MASK) == `INST_SLT) ||
((opcode_i & `INST_SLTU_MASK) == `INST_SLTU) ||
((opcode_i & `INST_XOR_MASK) == `INST_XOR) ||
((opcode_i & `INST_SRL_MASK) == `INST_SRL) ||
((opcode_i & `INST_SRA_MASK) == `INST_SRA) ||
((opcode_i & `INST_OR_MASK) == `INST_OR) ||
((opcode_i & `INST_AND_MASK) == `INST_AND) ||
((opcode_i & `INST_LB_MASK) == `INST_LB) ||
((opcode_i & `INST_LH_MASK) == `INST_LH) ||
((opcode_i & `INST_LW_MASK) == `INST_LW) ||
((opcode_i & `INST_LBU_MASK) == `INST_LBU) ||
((opcode_i & `INST_LHU_MASK) == `INST_LHU) ||
((opcode_i & `INST_LWU_MASK) == `INST_LWU) ||
((opcode_i & `INST_MUL_MASK) == `INST_MUL) ||
((opcode_i & `INST_MULH_MASK) == `INST_MULH) ||
((opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) ||
((opcode_i & `INST_MULHU_MASK) == `INST_MULHU) ||
((opcode_i & `INST_DIV_MASK) == `INST_DIV) ||
((opcode_i & `INST_DIVU_MASK) == `INST_DIVU) ||
((opcode_i & `INST_REM_MASK) == `INST_REM) ||
((opcode_i & `INST_REMU_MASK) == `INST_REMU) ||
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) ||
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) ||
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) ||
((opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI) ||
((opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI) ||
((opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI);
assign exec_o = ((opcode_i & `INST_ANDI_MASK) == `INST_ANDI) ||
((opcode_i & `INST_ADDI_MASK) == `INST_ADDI) ||
((opcode_i & `INST_SLTI_MASK) == `INST_SLTI) ||
((opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU)||
((opcode_i & `INST_ORI_MASK) == `INST_ORI) ||
((opcode_i & `INST_XORI_MASK) == `INST_XORI) ||
((opcode_i & `INST_SLLI_MASK) == `INST_SLLI) ||
((opcode_i & `INST_SRLI_MASK) == `INST_SRLI) ||
((opcode_i & `INST_SRAI_MASK) == `INST_SRAI) ||
((opcode_i & `INST_LUI_MASK) == `INST_LUI) ||
((opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC)||
((opcode_i & `INST_ADD_MASK) == `INST_ADD) ||
((opcode_i & `INST_SUB_MASK) == `INST_SUB) ||
((opcode_i & `INST_SLT_MASK) == `INST_SLT) ||
((opcode_i & `INST_SLTU_MASK) == `INST_SLTU) ||
((opcode_i & `INST_XOR_MASK) == `INST_XOR) ||
((opcode_i & `INST_OR_MASK) == `INST_OR) ||
((opcode_i & `INST_AND_MASK) == `INST_AND) ||
((opcode_i & `INST_SLL_MASK) == `INST_SLL) ||
((opcode_i & `INST_SRL_MASK) == `INST_SRL) ||
((opcode_i & `INST_SRA_MASK) == `INST_SRA);
assign lsu_o = ((opcode_i & `INST_LB_MASK) == `INST_LB) ||
((opcode_i & `INST_LH_MASK) == `INST_LH) ||
((opcode_i & `INST_LW_MASK) == `INST_LW) ||
((opcode_i & `INST_LBU_MASK) == `INST_LBU) ||
((opcode_i & `INST_LHU_MASK) == `INST_LHU) ||
((opcode_i & `INST_LWU_MASK) == `INST_LWU) ||
((opcode_i & `INST_SB_MASK) == `INST_SB) ||
((opcode_i & `INST_SH_MASK) == `INST_SH) ||
((opcode_i & `INST_SW_MASK) == `INST_SW);
assign branch_o = ((opcode_i & `INST_JAL_MASK) == `INST_JAL) ||
((opcode_i & `INST_JALR_MASK) == `INST_JALR) ||
((opcode_i & `INST_BEQ_MASK) == `INST_BEQ) ||
((opcode_i & `INST_BNE_MASK) == `INST_BNE) ||
((opcode_i & `INST_BLT_MASK) == `INST_BLT) ||
((opcode_i & `INST_BGE_MASK) == `INST_BGE) ||
((opcode_i & `INST_BLTU_MASK) == `INST_BLTU) ||
((opcode_i & `INST_BGEU_MASK) == `INST_BGEU);
assign mul_o = enable_muldiv_i &&
(((opcode_i & `INST_MUL_MASK) == `INST_MUL) ||
((opcode_i & `INST_MULH_MASK) == `INST_MULH) ||
((opcode_i & `INST_MULHSU_MASK) == `INST_MULHSU) ||
((opcode_i & `INST_MULHU_MASK) == `INST_MULHU));
assign div_o = enable_muldiv_i &&
(((opcode_i & `INST_DIV_MASK) == `INST_DIV) ||
((opcode_i & `INST_DIVU_MASK) == `INST_DIVU) ||
((opcode_i & `INST_REM_MASK) == `INST_REM) ||
((opcode_i & `INST_REMU_MASK) == `INST_REMU));
assign csr_o = ((opcode_i & `INST_ECALL_MASK) == `INST_ECALL) ||
((opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK) ||
((opcode_i & `INST_ERET_MASK) == `INST_ERET) ||
((opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW) ||
((opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS) ||
((opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC) ||
((opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI) ||
((opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI) ||
((opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI) ||
((opcode_i & `INST_WFI_MASK) == `INST_WFI) ||
((opcode_i & `INST_FENCE_MASK) == `INST_FENCE) ||
((opcode_i & `INST_IFENCE_MASK) == `INST_IFENCE) ||
((opcode_i & `INST_SFENCE_MASK) == `INST_SFENCE) ||
invalid_w || fetch_fault_i;
endmodule |
module riscv_pipe_ctrl
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_LOAD_BYPASS = 1
,parameter SUPPORT_MUL_BYPASS = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i
,input rst_i
// Issue
,input issue_valid_i
,input issue_accept_i
,input issue_stall_i
,input issue_lsu_i
,input issue_csr_i
,input issue_div_i
,input issue_mul_i
,input issue_branch_i
,input issue_rd_valid_i
,input [4:0] issue_rd_i
,input [5:0] issue_exception_i
,input take_interrupt_i
,input issue_branch_taken_i
,input [31:0] issue_branch_target_i
,input [31:0] issue_pc_i
,input [31:0] issue_opcode_i
,input [31:0] issue_operand_ra_i
,input [31:0] issue_operand_rb_i
// Execution stage 1: ALU result
,input [31:0] alu_result_e1_i
// Execution stage 1: CSR read result / early exceptions
,input [ 31:0] csr_result_value_e1_i
,input csr_result_write_e1_i
,input [ 31:0] csr_result_wdata_e1_i
,input [ 5:0] csr_result_exception_e1_i
// Execution stage 1
,output load_e1_o
,output store_e1_o
,output mul_e1_o
,output branch_e1_o
,output [ 4:0] rd_e1_o
,output [31:0] pc_e1_o
,output [31:0] opcode_e1_o
,output [31:0] operand_ra_e1_o
,output [31:0] operand_rb_e1_o
// Execution stage 2: Other results
,input mem_complete_i
,input [31:0] mem_result_e2_i
,input [5:0] mem_exception_e2_i
,input [31:0] mul_result_e2_i
// Execution stage 2
,output load_e2_o
,output mul_e2_o
,output [ 4:0] rd_e2_o
,output [31:0] result_e2_o
// Out of pipe: Divide Result
,input div_complete_i
,input [31:0] div_result_i
// Commit
,output valid_wb_o
,output csr_wb_o
,output [ 4:0] rd_wb_o
,output [31:0] result_wb_o
,output [31:0] pc_wb_o
,output [31:0] opcode_wb_o
,output [31:0] operand_ra_wb_o
,output [31:0] operand_rb_wb_o
,output [5:0] exception_wb_o
,output csr_write_wb_o
,output [11:0] csr_waddr_wb_o
,output [31:0] csr_wdata_wb_o
,output stall_o
,output squash_e1_e2_o
,input squash_e1_e2_i
,input squash_wb_i
);
//-------------------------------------------------------------
// Includes
//-------------------------------------------------------------
`include "riscv_defs.v"
wire squash_e1_e2_w;
wire branch_misaligned_w = (issue_branch_taken_i && issue_branch_target_i[1:0] != 2'b0);
//-------------------------------------------------------------
// E1 / Address
//-------------------------------------------------------------
`define PCINFO_W 10
`define PCINFO_ALU 0
`define PCINFO_LOAD 1
`define PCINFO_STORE 2
`define PCINFO_CSR 3
`define PCINFO_DIV 4
`define PCINFO_MUL 5
`define PCINFO_BRANCH 6
`define PCINFO_RD_VALID 7
`define PCINFO_INTR 8
`define PCINFO_COMPLETE 9
`define RD_IDX_R 11:7
reg valid_e1_q;
reg [`PCINFO_W-1:0] ctrl_e1_q;
reg [31:0] pc_e1_q;
reg [31:0] npc_e1_q;
reg [31:0] opcode_e1_q;
reg [31:0] operand_ra_e1_q;
reg [31:0] operand_rb_e1_q;
reg [`EXCEPTION_W-1:0] exception_e1_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_e1_q <= 1'b0;
ctrl_e1_q <= `PCINFO_W'b0;
pc_e1_q <= 32'b0;
npc_e1_q <= 32'b0;
opcode_e1_q <= 32'b0;
operand_ra_e1_q <= 32'b0;
operand_rb_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
// Stall - no change in E1 state
else if (issue_stall_i)
;
else if ((issue_valid_i && issue_accept_i) && ~(squash_e1_e2_o || squash_e1_e2_i))
begin
valid_e1_q <= 1'b1;
ctrl_e1_q[`PCINFO_ALU] <= ~(issue_lsu_i | issue_csr_i | issue_div_i | issue_mul_i);
ctrl_e1_q[`PCINFO_LOAD] <= issue_lsu_i & issue_rd_valid_i & ~take_interrupt_i; // TODO: Check
ctrl_e1_q[`PCINFO_STORE] <= issue_lsu_i & ~issue_rd_valid_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_CSR] <= issue_csr_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_DIV] <= issue_div_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_MUL] <= issue_mul_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_BRANCH] <= issue_branch_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_RD_VALID] <= issue_rd_valid_i & ~take_interrupt_i;
ctrl_e1_q[`PCINFO_INTR] <= take_interrupt_i;
ctrl_e1_q[`PCINFO_COMPLETE] <= 1'b1;
pc_e1_q <= issue_pc_i;
npc_e1_q <= issue_branch_taken_i ? issue_branch_target_i : issue_pc_i + 32'd4;
opcode_e1_q <= issue_opcode_i;
operand_ra_e1_q <= issue_operand_ra_i;
operand_rb_e1_q <= issue_operand_rb_i;
exception_e1_q <= (|issue_exception_i) ? issue_exception_i :
branch_misaligned_w ? `EXCEPTION_MISALIGNED_FETCH : `EXCEPTION_W'b0;
end
// No valid instruction (or pipeline flush event)
else
begin
valid_e1_q <= 1'b0;
ctrl_e1_q <= `PCINFO_W'b0;
pc_e1_q <= 32'b0;
npc_e1_q <= 32'b0;
opcode_e1_q <= 32'b0;
operand_ra_e1_q <= 32'b0;
operand_rb_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
wire alu_e1_w = ctrl_e1_q[`PCINFO_ALU];
assign load_e1_o = ctrl_e1_q[`PCINFO_LOAD];
assign store_e1_o = ctrl_e1_q[`PCINFO_STORE];
wire csr_e1_w = ctrl_e1_q[`PCINFO_CSR];
wire div_e1_w = ctrl_e1_q[`PCINFO_DIV];
assign mul_e1_o = ctrl_e1_q[`PCINFO_MUL];
assign branch_e1_o = ctrl_e1_q[`PCINFO_BRANCH];
assign rd_e1_o = {5{ctrl_e1_q[`PCINFO_RD_VALID]}} & opcode_e1_q[`RD_IDX_R];
assign pc_e1_o = pc_e1_q;
assign opcode_e1_o = opcode_e1_q;
assign operand_ra_e1_o = operand_ra_e1_q;
assign operand_rb_e1_o = operand_rb_e1_q;
//-------------------------------------------------------------
// E2 / Mem result
//-------------------------------------------------------------
reg valid_e2_q;
reg [`PCINFO_W-1:0] ctrl_e2_q;
reg csr_wr_e2_q;
reg [31:0] csr_wdata_e2_q;
reg [31:0] result_e2_q;
reg [31:0] pc_e2_q;
reg [31:0] npc_e2_q;
reg [31:0] opcode_e2_q;
reg [31:0] operand_ra_e2_q;
reg [31:0] operand_rb_e2_q;
reg [`EXCEPTION_W-1:0] exception_e2_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_e2_q <= 1'b0;
ctrl_e2_q <= `PCINFO_W'b0;
csr_wr_e2_q <= 1'b0;
csr_wdata_e2_q <= 32'b0;
pc_e2_q <= 32'b0;
npc_e2_q <= 32'b0;
opcode_e2_q <= 32'b0;
operand_ra_e2_q <= 32'b0;
operand_rb_e2_q <= 32'b0;
result_e2_q <= 32'b0;
exception_e2_q <= `EXCEPTION_W'b0;
end
// Stall - no change in E2 state
else if (issue_stall_i)
;
// Pipeline flush
else if (squash_e1_e2_o || squash_e1_e2_i)
begin
valid_e2_q <= 1'b0;
ctrl_e2_q <= `PCINFO_W'b0;
csr_wr_e2_q <= 1'b0;
csr_wdata_e2_q <= 32'b0;
pc_e2_q <= 32'b0;
npc_e2_q <= 32'b0;
opcode_e2_q <= 32'b0;
operand_ra_e2_q <= 32'b0;
operand_rb_e2_q <= 32'b0;
result_e2_q <= 32'b0;
exception_e2_q <= `EXCEPTION_W'b0;
end
// Normal pipeline advance
else
begin
valid_e2_q <= valid_e1_q;
ctrl_e2_q <= ctrl_e1_q;
csr_wr_e2_q <= csr_result_write_e1_i;
csr_wdata_e2_q <= csr_result_wdata_e1_i;
pc_e2_q <= pc_e1_q;
npc_e2_q <= npc_e1_q;
opcode_e2_q <= opcode_e1_q;
operand_ra_e2_q <= operand_ra_e1_q;
operand_rb_e2_q <= operand_rb_e1_q;
// Launch interrupt
if (ctrl_e1_q[`PCINFO_INTR])
exception_e2_q <= `EXCEPTION_INTERRUPT;
// If frontend reports bad instruction, ignore later CSR errors...
else if (|exception_e1_q)
begin
valid_e2_q <= 1'b0;
exception_e2_q <= exception_e1_q;
end
else
exception_e2_q <= csr_result_exception_e1_i;
if (ctrl_e1_q[`PCINFO_DIV])
result_e2_q <= div_result_i;
else if (ctrl_e1_q[`PCINFO_CSR])
result_e2_q <= csr_result_value_e1_i;
else
result_e2_q <= alu_result_e1_i;
end
reg [31:0] result_e2_r;
wire valid_e2_w = valid_e2_q & ~issue_stall_i;
always @ *
begin
// Default: ALU result
result_e2_r = result_e2_q;
if (SUPPORT_LOAD_BYPASS && valid_e2_w && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]))
result_e2_r = mem_result_e2_i;
else if (SUPPORT_MUL_BYPASS && valid_e2_w && ctrl_e2_q[`PCINFO_MUL])
result_e2_r = mul_result_e2_i;
end
wire load_store_e2_w = ctrl_e2_q[`PCINFO_LOAD] | ctrl_e2_q[`PCINFO_STORE];
assign load_e2_o = ctrl_e2_q[`PCINFO_LOAD];
assign mul_e2_o = ctrl_e2_q[`PCINFO_MUL];
assign rd_e2_o = {5{(valid_e2_w && ctrl_e2_q[`PCINFO_RD_VALID] && ~stall_o)}} & opcode_e2_q[`RD_IDX_R];
assign result_e2_o = result_e2_r;
// Load store result not ready when reaching E2
assign stall_o = (ctrl_e1_q[`PCINFO_DIV] && ~div_complete_i) || ((ctrl_e2_q[`PCINFO_LOAD] | ctrl_e2_q[`PCINFO_STORE]) & ~mem_complete_i);
reg [`EXCEPTION_W-1:0] exception_e2_r;
always @ *
begin
if (valid_e2_q && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]) && mem_complete_i)
exception_e2_r = mem_exception_e2_i;
else
exception_e2_r = exception_e2_q;
end
assign squash_e1_e2_w = |exception_e2_r;
reg squash_e1_e2_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
squash_e1_e2_q <= 1'b0;
else if (~issue_stall_i)
squash_e1_e2_q <= squash_e1_e2_w;
assign squash_e1_e2_o = squash_e1_e2_w | squash_e1_e2_q;
//-------------------------------------------------------------
// Writeback / Commit
//-------------------------------------------------------------
reg valid_wb_q;
reg [`PCINFO_W-1:0] ctrl_wb_q;
reg csr_wr_wb_q;
reg [31:0] csr_wdata_wb_q;
reg [31:0] result_wb_q;
reg [31:0] pc_wb_q;
reg [31:0] npc_wb_q;
reg [31:0] opcode_wb_q;
reg [31:0] operand_ra_wb_q;
reg [31:0] operand_rb_wb_q;
reg [`EXCEPTION_W-1:0] exception_wb_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_wb_q <= 1'b0;
ctrl_wb_q <= `PCINFO_W'b0;
csr_wr_wb_q <= 1'b0;
csr_wdata_wb_q <= 32'b0;
pc_wb_q <= 32'b0;
npc_wb_q <= 32'b0;
opcode_wb_q <= 32'b0;
operand_ra_wb_q <= 32'b0;
operand_rb_wb_q <= 32'b0;
result_wb_q <= 32'b0;
exception_wb_q <= `EXCEPTION_W'b0;
end
// Stall - no change in WB state
else if (issue_stall_i)
;
else if (squash_wb_i)
begin
valid_wb_q <= 1'b0;
ctrl_wb_q <= `PCINFO_W'b0;
csr_wr_wb_q <= 1'b0;
csr_wdata_wb_q <= 32'b0;
pc_wb_q <= 32'b0;
npc_wb_q <= 32'b0;
opcode_wb_q <= 32'b0;
operand_ra_wb_q <= 32'b0;
operand_rb_wb_q <= 32'b0;
result_wb_q <= 32'b0;
exception_wb_q <= `EXCEPTION_W'b0;
end
else
begin
// Squash instruction valid on memory faults
case (exception_e2_r)
`EXCEPTION_MISALIGNED_LOAD,
`EXCEPTION_FAULT_LOAD,
`EXCEPTION_MISALIGNED_STORE,
`EXCEPTION_FAULT_STORE,
`EXCEPTION_PAGE_FAULT_LOAD,
`EXCEPTION_PAGE_FAULT_STORE:
valid_wb_q <= 1'b0;
default:
valid_wb_q <= valid_e2_q;
endcase
csr_wr_wb_q <= csr_wr_e2_q; // TODO: Fault disable???
csr_wdata_wb_q <= csr_wdata_e2_q;
// Exception - squash writeback
if (|exception_e2_r)
ctrl_wb_q <= ctrl_e2_q & ~(1 << `PCINFO_RD_VALID);
else
ctrl_wb_q <= ctrl_e2_q;
pc_wb_q <= pc_e2_q;
npc_wb_q <= npc_e2_q;
opcode_wb_q <= opcode_e2_q;
operand_ra_wb_q <= operand_ra_e2_q;
operand_rb_wb_q <= operand_rb_e2_q;
exception_wb_q <= exception_e2_r;
if (valid_e2_w && (ctrl_e2_q[`PCINFO_LOAD] || ctrl_e2_q[`PCINFO_STORE]))
result_wb_q <= mem_result_e2_i;
else if (valid_e2_w && ctrl_e2_q[`PCINFO_MUL])
result_wb_q <= mul_result_e2_i;
else
result_wb_q <= result_e2_q;
end
// Instruction completion (for debug)
wire complete_wb_w = ctrl_wb_q[`PCINFO_COMPLETE] & ~issue_stall_i;
assign valid_wb_o = valid_wb_q & ~issue_stall_i;
assign csr_wb_o = ctrl_wb_q[`PCINFO_CSR] & ~issue_stall_i; // TODO: Fault disable???
assign rd_wb_o = {5{(valid_wb_o && ctrl_wb_q[`PCINFO_RD_VALID] && ~stall_o)}} & opcode_wb_q[`RD_IDX_R];
assign result_wb_o = result_wb_q;
assign pc_wb_o = pc_wb_q;
assign opcode_wb_o = opcode_wb_q;
assign operand_ra_wb_o = operand_ra_wb_q;
assign operand_rb_wb_o = operand_rb_wb_q;
assign exception_wb_o = exception_wb_q;
assign csr_write_wb_o = csr_wr_wb_q;
assign csr_waddr_wb_o = opcode_wb_q[31:20];
assign csr_wdata_wb_o = csr_wdata_wb_q;
`ifdef verilator
riscv_trace_sim
u_trace_d
(
.valid_i(issue_valid_i)
,.pc_i(issue_pc_i)
,.opcode_i(issue_opcode_i)
);
riscv_trace_sim
u_trace_wb
(
.valid_i(valid_wb_o)
,.pc_i(pc_wb_o)
,.opcode_i(opcode_wb_o)
);
`endif
endmodule |
module FFT #(
parameter WIDTH = 16
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
//----------------------------------------------------------------------
// Data must be input consecutively in natural order.
// The result is scaled to 1/N and output in bit-reversed order.
// The output latency is 71 clock cycles.
//----------------------------------------------------------------------
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
SdfUnit #(.N(64),.M(64),.WIDTH(WIDTH)) SU1 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (di_en ), // i
.di_re (di_re ), // i
.di_im (di_im ), // i
.do_en (su1_do_en ), // o
.do_re (su1_do_re ), // o
.do_im (su1_do_im ) // o
);
SdfUnit #(.N(64),.M(16),.WIDTH(WIDTH)) SU2 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su1_do_en ), // i
.di_re (su1_do_re ), // i
.di_im (su1_do_im ), // i
.do_en (su2_do_en ), // o
.do_re (su2_do_re ), // o
.do_im (su2_do_im ) // o
);
SdfUnit #(.N(64),.M(4),.WIDTH(WIDTH)) SU3 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su2_do_en ), // i
.di_re (su2_do_re ), // i
.di_im (su2_do_im ), // i
.do_en (do_en ), // o
.do_re (do_re ), // o
.do_im (do_im ) // o
);
endmodule |
module SdfUnit #(
parameter N = 64, // Number of FFT Point
parameter M = 64, // Twiddle Resolution
parameter WIDTH = 16, // Data Bit Length
parameter T4_EN = 0, // Use TwiddleConvert4
parameter T8_EN = 1, // Use TwiddleConvert8
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1, // Use TwiddleConvert Output Register
parameter B1_RH = 0, // 1st Butterfly Round Half Up
parameter B2_RH = 1, // 2nd Butterfly Round Half Up
parameter LP = 0 // Power Saving
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
// log2 constant function
function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam LOG_N = log2(N); // Bit Length of N
localparam LOG_M = log2(M); // Bit Length of M
// When using Twiddle Conversion, start counting 1T earlier
localparam TC_EN = T4_EN | T8_EN;
localparam EARLY = TC_EN & TW_FF & TC_FF;
//----------------------------------------------------------------------
// Internal Regs and Nets
//----------------------------------------------------------------------
// 1st Butterfly
reg [LOG_N-1:0] di_count; // Input Data Count
wire bf1_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag)
reg bf1_sp_en; // Single-Path Data Enable
reg [LOG_N-1:0] bf1_count; // Single-Path Data Count
wire bf1_start; // Single-Path Output Trigger
wire bf1_end; // End of Single-Path Data
wire bf1_mj; // Twiddle (-j) Enable
reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real)
reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag)
// 2nd Butterfly
reg bf2_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag)
reg bf2_ct_en; // Single-Path Data Count Enable
reg [LOG_N-1:0] bf2_count; // Single-Path Data Count
wire bf2_start_0t;// Single-Path Output Trigger
reg bf2_start_1t;// Single-Path Output Trigger
wire bf2_start; // Single-Path Output Trigger
wire bf2_end; // End of Single-Path Data
reg bf2_ct_en_1d;// Single-Path Data Enable When Using TC
wire bf2_sp_en; // Single-Path Data Enable
reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real)
reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag)
reg bf2_do_en; // 2nd Butterfly Output Data Enable
// Multiplication
wire[1:0] tw_sel; // Twiddle Select (2n/n/3n)
wire[LOG_N-3:0] tw_num; // Twiddle Number (n)
wire[LOG_N-1:0] tw_addr; // Twiddle Table Address
wire[LOG_N-1:0] tc_addr; // Twiddle Address from TwiddleConvert
wire[LOG_N-1:0] tw_addr_tc; // Twiddle Address after TC_EN Switch
wire[WIDTH-1:0] tw_re; // Twiddle Data from Table (Real)
wire[WIDTH-1:0] tw_im; // Twiddle Data from Table (Imag)
wire[WIDTH-1:0] tc_re; // Twiddle Data from TwiddleConvert (Real)
wire[WIDTH-1:0] tc_im; // Twiddle Data from TwiddleConvert (Imag)
reg tw_nz; // Multiplication Enable
reg tw_nz_1d; // Multiplication Enable
wire mu_en; // Multiplication Enable
wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real)
wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag)
wire[WIDTH-1:0] mu_b_re; // Twiddle Data to Multiplier (Real)
wire[WIDTH-1:0] mu_b_im; // Twiddle Data to Multiplier (Imag)
wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real)
wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag)
reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real)
reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag)
reg mu_do_en; // Multiplication Output Data Enable
//----------------------------------------------------------------------
// 1st Butterfly
//----------------------------------------------------------------------
always @(posedge clock or posedge reset) begin
if (reset) begin
di_count <= {LOG_N{1'b0}};
end else begin
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_bf = di_count[LOG_M-1];
// Reducing signal changes may reduce power consumption
// Set unknown value x for verification
assign bf1_x0_re = bf1_bf ? db1_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf1_x0_im = bf1_bf ? db1_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf1_x1_re = bf1_bf ? di_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf1_x1_im = bf1_bf ? di_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(B1_RH)) BF1 (
.x0_re (bf1_x0_re ), // i
.x0_im (bf1_x0_im ), // i
.x1_re (bf1_x1_re ), // i
.x1_im (bf1_x1_im ), // i
.y0_re (bf1_y0_re ), // o
.y0_im (bf1_y0_im ), // o
.y1_re (bf1_y1_re ), // o
.y1_im (bf1_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
.clock (clock ), // i
.di_re (db1_di_re ), // i
.di_im (db1_di_im ), // i
.do_re (db1_do_re ), // o
.do_im (db1_do_im ) // o
);
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf1_sp_en <= 1'b0;
bf1_count <= {LOG_N{1'b0}};
end else begin
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
assign bf1_end = (bf1_count == (2**LOG_N-1));
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
always @(posedge clock) begin
bf1_do_re <= bf1_sp_re;
bf1_do_im <= bf1_sp_im;
end
//----------------------------------------------------------------------
// 2nd Butterfly
//----------------------------------------------------------------------
always @(posedge clock) begin
bf2_bf <= bf1_count[LOG_M-2];
end
// Reducing signal changes may reduce power consumption
// Set unknown value x for verification
assign bf2_x0_re = bf2_bf ? db2_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf2_x0_im = bf2_bf ? db2_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf2_x1_re = bf2_bf ? bf1_do_re : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
assign bf2_x1_im = bf2_bf ? bf1_do_im : LP ? {WIDTH{1'b0}} : {WIDTH{1'bx}};
// Negative bias occurs when RH=0 and positive bias occurs when RH=1.
// Using both alternately reduces the overall rounding error.
Butterfly #(.WIDTH(WIDTH),.RH(B2_RH)) BF2 (
.x0_re (bf2_x0_re ), // i
.x0_im (bf2_x0_im ), // i
.x1_re (bf2_x1_re ), // i
.x1_im (bf2_x1_im ), // i
.y0_re (bf2_y0_re ), // o
.y0_im (bf2_y0_im ), // o
.y1_re (bf2_y1_re ), // o
.y1_im (bf2_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
.clock (clock ), // i
.di_re (db2_di_re ), // i
.di_im (db2_di_im ), // i
.do_re (db2_do_re ), // o
.do_im (db2_do_im ) // o
);
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_ct_en <= 1'b0;
bf2_count <= {LOG_N{1'b0}};
end else begin
bf2_ct_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_ct_en;
bf2_count <= bf2_ct_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
end
end
// When using Twiddle Conversion, start counting 1T earlier
assign bf2_start_0t = (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
always @(posedge clock) begin
bf2_start_1t <= bf2_start_0t;
end
assign bf2_start = EARLY ? bf2_start_0t : bf2_start_1t;
assign bf2_end = (bf2_count == (2**LOG_N-1));
always @(posedge clock) begin
bf2_ct_en_1d <= bf2_ct_en;
end
assign bf2_sp_en = EARLY ? bf2_ct_en_1d : bf2_ct_en;
always @(posedge clock) begin
bf2_do_re <= bf2_sp_re;
bf2_do_im <= bf2_sp_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_do_en <= 1'b0;
end else begin
bf2_do_en <= bf2_sp_en;
end
end
//----------------------------------------------------------------------
// Multiplication
//----------------------------------------------------------------------
assign tw_sel[1] = bf2_count[LOG_M-2];
assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle #(.TW_FF(TW_FF)) TW (
.clock (clock ), // i
.addr (tw_addr_tc ), // i
.tw_re (tw_re ), // o
.tw_im (tw_im ) // o
);
generate if (T4_EN) begin
TwiddleConvert4 #(.LOG_N(LOG_N),.WIDTH(WIDTH),.TW_FF(TW_FF),.TC_FF(TC_FF)) TC (
.clock (clock ), // i
.tw_addr (tw_addr), // i
.tw_re (tw_re ), // i
.tw_im (tw_im ), // i
.tc_addr (tc_addr), // o
.tc_re (tc_re ), // o
.tc_im (tc_im ) // o
);
end else if (T8_EN) begin
TwiddleConvert8 #(.LOG_N(LOG_N),.WIDTH(WIDTH),.TW_FF(TW_FF),.TC_FF(TC_FF)) TC (
.clock (clock ), // i
.tw_addr (tw_addr), // i
.tw_re (tw_re ), // i
.tw_im (tw_im ), // i
.tc_addr (tc_addr), // o
.tc_re (tc_re ), // o
.tc_im (tc_im ) // o
);
end else begin
assign tc_addr = {LOG_N{1'bx}};
assign tc_re = {WIDTH{1'bx}};
assign tc_im = {WIDTH{1'bx}};
end endgenerate
assign tw_addr_tc = TC_EN ? tc_addr : tw_addr;
assign mu_b_re = TC_EN ? tc_re : tw_re;
assign mu_b_im = TC_EN ? tc_im : tw_im;
// Multiplication is bypassed when twiddle address is 0.
always @(posedge clock) begin
tw_nz <= (tw_addr != {LOG_N{1'b0}});
tw_nz_1d <= tw_nz;
end
// When using Twiddle Conversion, address generated 1T Earlier
assign mu_en = EARLY ? tw_nz_1d : tw_nz;
// Set unknown value x for verification
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
Multiply #(.WIDTH(WIDTH)) MU (
.a_re (mu_a_re), // i
.a_im (mu_a_im), // i
.b_re (mu_b_re), // i
.b_im (mu_b_im), // i
.m_re (mu_m_re), // o
.m_im (mu_m_im) // o
);
always @(posedge clock) begin
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
mu_do_en <= 1'b0;
end else begin
mu_do_en <= bf2_do_en;
end
end
// No multiplication required at final stage
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
endmodule |
module SdfUnit2 #(
parameter WIDTH = 16, // Data Bit Length
parameter BF_RH = 0 // Butterfly Round Half Up
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output reg do_en, // Output Data Enable
output reg [WIDTH-1:0] do_re, // Output Data (Real)
output reg [WIDTH-1:0] do_im // Output Data (Imag)
);
//----------------------------------------------------------------------
// Internal Regs and Nets
//----------------------------------------------------------------------
reg bf_en; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf_sp_im; // Single-Path Data Output (Imag)
reg bf_sp_en; // Single-Path Data Enable
//----------------------------------------------------------------------
// Butterfly Add/Sub
//----------------------------------------------------------------------
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_en <= 1'b0;
end else begin
bf_en <= di_en ? ~bf_en : 1'b0;
end
end
// Set unknown value x for verification
assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
assign x1_re = bf_en ? di_re : {WIDTH{1'bx}};
assign x1_im = bf_en ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
.x0_re (x0_re ), // i
.x0_im (x0_im ), // i
.x1_re (x1_re ), // i
.x1_im (x1_im ), // i
.y0_re (y0_re ), // o
.y0_im (y0_im ), // o
.y1_re (y1_re ), // o
.y1_im (y1_im ) // o
);
DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
.clock (clock ), // i
.di_re (db_di_re ), // i
.di_im (db_di_im ), // i
.do_re (db_do_re ), // o
.do_im (db_do_im ) // o
);
assign db_di_re = bf_en ? y1_re : di_re;
assign db_di_im = bf_en ? y1_im : di_im;
assign bf_sp_re = bf_en ? y0_re : db_do_re;
assign bf_sp_im = bf_en ? y0_im : db_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf_sp_en <= 1'b0;
do_en <= 1'b0;
end else begin
bf_sp_en <= di_en;
do_en <= bf_sp_en;
end
end
always @(posedge clock) begin
do_re <= bf_sp_re;
do_im <= bf_sp_im;
end
endmodule |
module DelayBuffer #(
parameter DEPTH = 32,
parameter WIDTH = 16
)(
input clock, // Master Clock
input [WIDTH-1:0] di_re, // Data Input (Real)
input [WIDTH-1:0] di_im, // Data Input (Imag)
output [WIDTH-1:0] do_re, // Data Output (Real)
output [WIDTH-1:0] do_im // Data Output (Imag)
);
reg [WIDTH-1:0] buf_re[0:DEPTH-1];
reg [WIDTH-1:0] buf_im[0:DEPTH-1];
integer n;
// Shift Buffer
always @(posedge clock) begin
for (n = DEPTH-1; n > 0; n = n - 1) begin
buf_re[n] <= buf_re[n-1];
buf_im[n] <= buf_im[n-1];
end
buf_re[0] <= di_re;
buf_im[0] <= di_im;
end
assign do_re = buf_re[DEPTH-1];
assign do_im = buf_im[DEPTH-1];
endmodule |
module FFT #(
parameter WIDTH = 16
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
//----------------------------------------------------------------------
// Data must be input consecutively in natural order.
// The result is scaled to 1/N and output in bit-reversed order.
// The output latency is 137 clock cycles.
//----------------------------------------------------------------------
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
wire su3_do_en;
wire[WIDTH-1:0] su3_do_re;
wire[WIDTH-1:0] su3_do_im;
SdfUnit #(.N(128),.M(128),.WIDTH(WIDTH)) SU1 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (di_en ), // i
.di_re (di_re ), // i
.di_im (di_im ), // i
.do_en (su1_do_en ), // o
.do_re (su1_do_re ), // o
.do_im (su1_do_im ) // o
);
SdfUnit #(.N(128),.M(32),.WIDTH(WIDTH)) SU2 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su1_do_en ), // i
.di_re (su1_do_re ), // i
.di_im (su1_do_im ), // i
.do_en (su2_do_en ), // o
.do_re (su2_do_re ), // o
.do_im (su2_do_im ) // o
);
SdfUnit #(.N(128),.M(8),.WIDTH(WIDTH)) SU3 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su2_do_en ), // i
.di_re (su2_do_re ), // i
.di_im (su2_do_im ), // i
.do_en (su3_do_en ), // o
.do_re (su3_do_re ), // o
.do_im (su3_do_im ) // o
);
SdfUnit2 #(.WIDTH(WIDTH)) SU4 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su3_do_en ), // i
.di_re (su3_do_re ), // i
.di_im (su3_do_im ), // i
.do_en (do_en ), // o
.do_re (do_re ), // o
.do_im (do_im ) // o
);
endmodule |
module TwiddleConvert4 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
)(
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, // Twiddle Number
input [WIDTH-1:0] tw_re, // Twiddle Value (Real)
input [WIDTH-1:0] tw_im, // Twiddle Value (Imag)
output [LOG_N-1:0] tc_addr, // Converted Twiddle Number
output [WIDTH-1:0] tc_re, // Converted Twiddle Value (Real)
output [WIDTH-1:0] tc_im // Converted Twiddle Value (Imag)
);
// Internal Nets
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
// Convert Twiddle Number
assign tc_addr[LOG_N-1:LOG_N-2] = 2'd0;
assign tc_addr[LOG_N-3:0] = tw_addr[LOG_N-3:0];
// Convert Twiddle Value
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-3:0] == {LOG_N-2{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
2'd1 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {1'b1,{WIDTH-1{1'b0}}}};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
2'd1 : {mx_re, mx_im} <= { tw_im, -tw_re};
2'd2 : {mx_re, mx_im} <= {-tw_re, -tw_im};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule |
module TwiddleConvert8 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
)(
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, // Twiddle Number
input [WIDTH-1:0] tw_re, // Twiddle Value (Real)
input [WIDTH-1:0] tw_im, // Twiddle Value (Imag)
output [LOG_N-1:0] tc_addr, // Converted Twiddle Number
output [WIDTH-1:0] tc_re, // Converted Twiddle Value (Real)
output [WIDTH-1:0] tc_im // Converted Twiddle Value (Imag)
);
// Define Constants
localparam[WIDTH-1:0] COSMQ = (((32'h5A82799A<<1) >> (32-WIDTH)) + 1)>>1; // cos(-pi/4)
localparam[WIDTH-1:0] SINMH = 32'h80000000 >> (32-WIDTH); // sin(-pi/2)
// Internal Nets
reg [LOG_N-1:0] ff_addr;
wire[LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
// Convert Twiddle Number
assign tc_addr[LOG_N-1:LOG_N-3] = 3'd0;
assign tc_addr[LOG_N-4:0] = tw_addr[LOG_N-3] ? -tw_addr[LOG_N-4:0] : tw_addr[LOG_N-4:0];
// Convert Twiddle Value
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-4:0] == {LOG_N-3{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
3'd1 : {mx_re, mx_im} <= { COSMQ , -COSMQ };
3'd2 : {mx_re, mx_im} <= {{WIDTH{1'b0}}, SINMH };
3'd3 : {mx_re, mx_im} <= {-COSMQ , -COSMQ };
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0 : {mx_re, mx_im} <= { tw_re, tw_im};
3'd1 : {mx_re, mx_im} <= {-tw_im, -tw_re};
3'd2 : {mx_re, mx_im} <= { tw_im, -tw_re};
3'd3 : {mx_re, mx_im} <= {-tw_re, tw_im};
3'd4 : {mx_re, mx_im} <= {-tw_re, -tw_im};
3'd5 : {mx_re, mx_im} <= { tw_im, tw_re};
default : {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule |
module Twiddle #(
parameter TW_FF = 1 // Use Output Register
)(
input clock, // Master Clock
input [6:0] addr, // Twiddle Factor Number
output [15:0] tw_re, // Twiddle Factor (Real)
output [15:0] tw_im // Twiddle Factor (Imag)
);
wire[15:0] wn_re[0:127]; // Twiddle Table (Real)
wire[15:0] wn_im[0:127]; // Twiddle Table (Imag)
wire[15:0] mx_re; // Multiplexer output (Real)
wire[15:0] mx_im; // Multiplexer output (Imag)
reg [15:0] ff_re; // Register output (Real)
reg [15:0] ff_im; // Register output (Imag)
assign mx_re = wn_re[addr];
assign mx_im = wn_im[addr];
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tw_re = TW_FF ? ff_re : mx_re;
assign tw_im = TW_FF ? ff_im : mx_im;
//----------------------------------------------------------------------
// Twiddle Factor Value
//----------------------------------------------------------------------
// Multiplication is bypassed when twiddle address is 0.
// Setting wn_re[0] = 0 and wn_im[0] = 0 makes it easier to check the waveform.
// It may also reduce power consumption slightly.
//
// wn_re = cos(-2pi*n/128) wn_im = sin(-2pi*n/128)
assign wn_re[ 0] = 16'h0000; assign wn_im[ 0] = 16'h0000; // 0 1.000 -0.000
assign wn_re[ 1] = 16'h7FD9; assign wn_im[ 1] = 16'hF9B8; // 1 0.999 -0.049
assign wn_re[ 2] = 16'h7F62; assign wn_im[ 2] = 16'hF374; // 2 0.995 -0.098
assign wn_re[ 3] = 16'h7E9D; assign wn_im[ 3] = 16'hED38; // 3 0.989 -0.147
assign wn_re[ 4] = 16'h7D8A; assign wn_im[ 4] = 16'hE707; // 4 0.981 -0.195
assign wn_re[ 5] = 16'h7C2A; assign wn_im[ 5] = 16'hE0E6; // 5 0.970 -0.243
assign wn_re[ 6] = 16'h7A7D; assign wn_im[ 6] = 16'hDAD8; // 6 0.957 -0.290
assign wn_re[ 7] = 16'h7885; assign wn_im[ 7] = 16'hD4E1; // 7 0.942 -0.337
assign wn_re[ 8] = 16'h7642; assign wn_im[ 8] = 16'hCF04; // 8 0.924 -0.383
assign wn_re[ 9] = 16'h73B6; assign wn_im[ 9] = 16'hC946; // 9 0.904 -0.428
assign wn_re[10] = 16'h70E3; assign wn_im[10] = 16'hC3A9; // 10 0.882 -0.471
assign wn_re[11] = 16'h6DCA; assign wn_im[11] = 16'hBE32; // 11 0.858 -0.514
assign wn_re[12] = 16'h6A6E; assign wn_im[12] = 16'hB8E3; // 12 0.831 -0.556
assign wn_re[13] = 16'h66D0; assign wn_im[13] = 16'hB3C0; // 13 0.803 -0.596
assign wn_re[14] = 16'h62F2; assign wn_im[14] = 16'hAECC; // 14 0.773 -0.634
assign wn_re[15] = 16'h5ED7; assign wn_im[15] = 16'hAA0A; // 15 0.741 -0.672
assign wn_re[16] = 16'h5A82; assign wn_im[16] = 16'hA57E; // 16 0.707 -0.707
assign wn_re[17] = 16'h55F6; assign wn_im[17] = 16'hA129; // 17 0.672 -0.741
assign wn_re[18] = 16'h5134; assign wn_im[18] = 16'h9D0E; // 18 0.634 -0.773
assign wn_re[19] = 16'h4C40; assign wn_im[19] = 16'h9930; // 19 0.596 -0.803
assign wn_re[20] = 16'h471D; assign wn_im[20] = 16'h9592; // 20 0.556 -0.831
assign wn_re[21] = 16'h41CE; assign wn_im[21] = 16'h9236; // 21 0.514 -0.858
assign wn_re[22] = 16'h3C57; assign wn_im[22] = 16'h8F1D; // 22 0.471 -0.882
assign wn_re[23] = 16'h36BA; assign wn_im[23] = 16'h8C4A; // 23 0.428 -0.904
assign wn_re[24] = 16'h30FC; assign wn_im[24] = 16'h89BE; // 24 0.383 -0.924
assign wn_re[25] = 16'h2B1F; assign wn_im[25] = 16'h877B; // 25 0.337 -0.942
assign wn_re[26] = 16'h2528; assign wn_im[26] = 16'h8583; // 26 0.290 -0.957
assign wn_re[27] = 16'h1F1A; assign wn_im[27] = 16'h83D6; // 27 0.243 -0.970
assign wn_re[28] = 16'h18F9; assign wn_im[28] = 16'h8276; // 28 0.195 -0.981
assign wn_re[29] = 16'h12C8; assign wn_im[29] = 16'h8163; // 29 0.147 -0.989
assign wn_re[30] = 16'h0C8C; assign wn_im[30] = 16'h809E; // 30 0.098 -0.995
assign wn_re[31] = 16'h0648; assign wn_im[31] = 16'h8027; // 31 0.049 -0.999
assign wn_re[32] = 16'h0000; assign wn_im[32] = 16'h8000; // 32 0.000 -1.000
assign wn_re[33] = 16'hF9B8; assign wn_im[33] = 16'h8027; // 33 -0.049 -0.999
assign wn_re[34] = 16'hF374; assign wn_im[34] = 16'h809E; // 34 -0.098 -0.995
assign wn_re[35] = 16'hxxxx; assign wn_im[35] = 16'hxxxx; // 35 -0.147 -0.989
assign wn_re[36] = 16'hE707; assign wn_im[36] = 16'h8276; // 36 -0.195 -0.981
assign wn_re[37] = 16'hxxxx; assign wn_im[37] = 16'hxxxx; // 37 -0.243 -0.970
assign wn_re[38] = 16'hDAD8; assign wn_im[38] = 16'h8583; // 38 -0.290 -0.957
assign wn_re[39] = 16'hD4E1; assign wn_im[39] = 16'h877B; // 39 -0.337 -0.942
assign wn_re[40] = 16'hCF04; assign wn_im[40] = 16'h89BE; // 40 -0.383 -0.924
assign wn_re[41] = 16'hxxxx; assign wn_im[41] = 16'hxxxx; // 41 -0.428 -0.904
assign wn_re[42] = 16'hC3A9; assign wn_im[42] = 16'h8F1D; // 42 -0.471 -0.882
assign wn_re[43] = 16'hxxxx; assign wn_im[43] = 16'hxxxx; // 43 -0.514 -0.858
assign wn_re[44] = 16'hB8E3; assign wn_im[44] = 16'h9592; // 44 -0.556 -0.831
assign wn_re[45] = 16'hB3C0; assign wn_im[45] = 16'h9930; // 45 -0.596 -0.803
assign wn_re[46] = 16'hAECC; assign wn_im[46] = 16'h9D0E; // 46 -0.634 -0.773
assign wn_re[47] = 16'hxxxx; assign wn_im[47] = 16'hxxxx; // 47 -0.672 -0.741
assign wn_re[48] = 16'hA57E; assign wn_im[48] = 16'hA57E; // 48 -0.707 -0.707
assign wn_re[49] = 16'hxxxx; assign wn_im[49] = 16'hxxxx; // 49 -0.741 -0.672
assign wn_re[50] = 16'h9D0E; assign wn_im[50] = 16'hAECC; // 50 -0.773 -0.634
assign wn_re[51] = 16'h9930; assign wn_im[51] = 16'hB3C0; // 51 -0.803 -0.596
assign wn_re[52] = 16'h9592; assign wn_im[52] = 16'hB8E3; // 52 -0.831 -0.556
assign wn_re[53] = 16'hxxxx; assign wn_im[53] = 16'hxxxx; // 53 -0.858 -0.514
assign wn_re[54] = 16'h8F1D; assign wn_im[54] = 16'hC3A9; // 54 -0.882 -0.471
assign wn_re[55] = 16'hxxxx; assign wn_im[55] = 16'hxxxx; // 55 -0.904 -0.428
assign wn_re[56] = 16'h89BE; assign wn_im[56] = 16'hCF04; // 56 -0.924 -0.383
assign wn_re[57] = 16'h877B; assign wn_im[57] = 16'hD4E1; // 57 -0.942 -0.337
assign wn_re[58] = 16'h8583; assign wn_im[58] = 16'hDAD8; // 58 -0.957 -0.290
assign wn_re[59] = 16'hxxxx; assign wn_im[59] = 16'hxxxx; // 59 -0.970 -0.243
assign wn_re[60] = 16'h8276; assign wn_im[60] = 16'hE707; // 60 -0.981 -0.195
assign wn_re[61] = 16'hxxxx; assign wn_im[61] = 16'hxxxx; // 61 -0.989 -0.147
assign wn_re[62] = 16'h809E; assign wn_im[62] = 16'hF374; // 62 -0.995 -0.098
assign wn_re[63] = 16'h8027; assign wn_im[63] = 16'hF9B8; // 63 -0.999 -0.049
assign wn_re[64] = 16'hxxxx; assign wn_im[64] = 16'hxxxx; // 64 -1.000 -0.000
assign wn_re[65] = 16'hxxxx; assign wn_im[65] = 16'hxxxx; // 65 -0.999 0.049
assign wn_re[66] = 16'h809E; assign wn_im[66] = 16'h0C8C; // 66 -0.995 0.098
assign wn_re[67] = 16'hxxxx; assign wn_im[67] = 16'hxxxx; // 67 -0.989 0.147
assign wn_re[68] = 16'hxxxx; assign wn_im[68] = 16'hxxxx; // 68 -0.981 0.195
assign wn_re[69] = 16'h83D6; assign wn_im[69] = 16'h1F1A; // 69 -0.970 0.243
assign wn_re[70] = 16'hxxxx; assign wn_im[70] = 16'hxxxx; // 70 -0.957 0.290
assign wn_re[71] = 16'hxxxx; assign wn_im[71] = 16'hxxxx; // 71 -0.942 0.337
assign wn_re[72] = 16'h89BE; assign wn_im[72] = 16'h30FC; // 72 -0.924 0.383
assign wn_re[73] = 16'hxxxx; assign wn_im[73] = 16'hxxxx; // 73 -0.904 0.428
assign wn_re[74] = 16'hxxxx; assign wn_im[74] = 16'hxxxx; // 74 -0.882 0.471
assign wn_re[75] = 16'h9236; assign wn_im[75] = 16'h41CE; // 75 -0.858 0.514
assign wn_re[76] = 16'hxxxx; assign wn_im[76] = 16'hxxxx; // 76 -0.831 0.556
assign wn_re[77] = 16'hxxxx; assign wn_im[77] = 16'hxxxx; // 77 -0.803 0.596
assign wn_re[78] = 16'h9D0E; assign wn_im[78] = 16'h5134; // 78 -0.773 0.634
assign wn_re[79] = 16'hxxxx; assign wn_im[79] = 16'hxxxx; // 79 -0.741 0.672
assign wn_re[80] = 16'hxxxx; assign wn_im[80] = 16'hxxxx; // 80 -0.707 0.707
assign wn_re[81] = 16'hAA0A; assign wn_im[81] = 16'h5ED7; // 81 -0.672 0.741
assign wn_re[82] = 16'hxxxx; assign wn_im[82] = 16'hxxxx; // 82 -0.634 0.773
assign wn_re[83] = 16'hxxxx; assign wn_im[83] = 16'hxxxx; // 83 -0.596 0.803
assign wn_re[84] = 16'hB8E3; assign wn_im[84] = 16'h6A6E; // 84 -0.556 0.831
assign wn_re[85] = 16'hxxxx; assign wn_im[85] = 16'hxxxx; // 85 -0.514 0.858
assign wn_re[86] = 16'hxxxx; assign wn_im[86] = 16'hxxxx; // 86 -0.471 0.882
assign wn_re[87] = 16'hC946; assign wn_im[87] = 16'h73B6; // 87 -0.428 0.904
assign wn_re[88] = 16'hxxxx; assign wn_im[88] = 16'hxxxx; // 88 -0.383 0.924
assign wn_re[89] = 16'hxxxx; assign wn_im[89] = 16'hxxxx; // 89 -0.337 0.942
assign wn_re[90] = 16'hDAD8; assign wn_im[90] = 16'h7A7D; // 90 -0.290 0.957
assign wn_re[91] = 16'hxxxx; assign wn_im[91] = 16'hxxxx; // 91 -0.243 0.970
assign wn_re[92] = 16'hxxxx; assign wn_im[92] = 16'hxxxx; // 92 -0.195 0.981
assign wn_re[93] = 16'hED38; assign wn_im[93] = 16'h7E9D; // 93 -0.147 0.989
assign wn_re[94] = 16'hxxxx; assign wn_im[94] = 16'hxxxx; // 94 -0.098 0.995
assign wn_re[95] = 16'hxxxx; assign wn_im[95] = 16'hxxxx; // 95 -0.049 0.999
assign wn_re[96] = 16'hxxxx; assign wn_im[96] = 16'hxxxx; // 96 -0.000 1.000
assign wn_re[97] = 16'hxxxx; assign wn_im[97] = 16'hxxxx; // 97 0.049 0.999
assign wn_re[98] = 16'hxxxx; assign wn_im[98] = 16'hxxxx; // 98 0.098 0.995
assign wn_re[99] = 16'hxxxx; assign wn_im[99] = 16'hxxxx; // 99 0.147 0.989
assign wn_re[100] = 16'hxxxx; assign wn_im[100] = 16'hxxxx; // 100 0.195 0.981
assign wn_re[101] = 16'hxxxx; assign wn_im[101] = 16'hxxxx; // 101 0.243 0.970
assign wn_re[102] = 16'hxxxx; assign wn_im[102] = 16'hxxxx; // 102 0.290 0.957
assign wn_re[103] = 16'hxxxx; assign wn_im[103] = 16'hxxxx; // 103 0.337 0.942
assign wn_re[104] = 16'hxxxx; assign wn_im[104] = 16'hxxxx; // 104 0.383 0.924
assign wn_re[105] = 16'hxxxx; assign wn_im[105] = 16'hxxxx; // 105 0.428 0.904
assign wn_re[106] = 16'hxxxx; assign wn_im[106] = 16'hxxxx; // 106 0.471 0.882
assign wn_re[107] = 16'hxxxx; assign wn_im[107] = 16'hxxxx; // 107 0.514 0.858
assign wn_re[108] = 16'hxxxx; assign wn_im[108] = 16'hxxxx; // 108 0.556 0.831
assign wn_re[109] = 16'hxxxx; assign wn_im[109] = 16'hxxxx; // 109 0.596 0.803
assign wn_re[110] = 16'hxxxx; assign wn_im[110] = 16'hxxxx; // 110 0.634 0.773
assign wn_re[111] = 16'hxxxx; assign wn_im[111] = 16'hxxxx; // 111 0.672 0.741
assign wn_re[112] = 16'hxxxx; assign wn_im[112] = 16'hxxxx; // 112 0.707 0.707
assign wn_re[113] = 16'hxxxx; assign wn_im[113] = 16'hxxxx; // 113 0.741 0.672
assign wn_re[114] = 16'hxxxx; assign wn_im[114] = 16'hxxxx; // 114 0.773 0.634
assign wn_re[115] = 16'hxxxx; assign wn_im[115] = 16'hxxxx; // 115 0.803 0.596
assign wn_re[116] = 16'hxxxx; assign wn_im[116] = 16'hxxxx; // 116 0.831 0.556
assign wn_re[117] = 16'hxxxx; assign wn_im[117] = 16'hxxxx; // 117 0.858 0.514
assign wn_re[118] = 16'hxxxx; assign wn_im[118] = 16'hxxxx; // 118 0.882 0.471
assign wn_re[119] = 16'hxxxx; assign wn_im[119] = 16'hxxxx; // 119 0.904 0.428
assign wn_re[120] = 16'hxxxx; assign wn_im[120] = 16'hxxxx; // 120 0.924 0.383
assign wn_re[121] = 16'hxxxx; assign wn_im[121] = 16'hxxxx; // 121 0.942 0.337
assign wn_re[122] = 16'hxxxx; assign wn_im[122] = 16'hxxxx; // 122 0.957 0.290
assign wn_re[123] = 16'hxxxx; assign wn_im[123] = 16'hxxxx; // 123 0.970 0.243
assign wn_re[124] = 16'hxxxx; assign wn_im[124] = 16'hxxxx; // 124 0.981 0.195
assign wn_re[125] = 16'hxxxx; assign wn_im[125] = 16'hxxxx; // 125 0.989 0.147
assign wn_re[126] = 16'hxxxx; assign wn_im[126] = 16'hxxxx; // 126 0.995 0.098
assign wn_re[127] = 16'hxxxx; assign wn_im[127] = 16'hxxxx; // 127 0.999 0.049
endmodule |
module Twiddle #(
parameter TW_FF = 1 // Use Output Register
)(
input clock, // Master Clock
input [5:0] addr, // Twiddle Factor Number
output [15:0] tw_re, // Twiddle Factor (Real)
output [15:0] tw_im // Twiddle Factor (Imag)
);
wire[15:0] wn_re[0:63]; // Twiddle Table (Real)
wire[15:0] wn_im[0:63]; // Twiddle Table (Imag)
wire[15:0] mx_re; // Multiplexer output (Real)
wire[15:0] mx_im; // Multiplexer output (Imag)
reg [15:0] ff_re; // Register output (Real)
reg [15:0] ff_im; // Register output (Imag)
assign mx_re = wn_re[addr];
assign mx_im = wn_im[addr];
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tw_re = TW_FF ? ff_re : mx_re;
assign tw_im = TW_FF ? ff_im : mx_im;
//----------------------------------------------------------------------
// Twiddle Factor Value
//----------------------------------------------------------------------
// Multiplication is bypassed when twiddle address is 0.
// Setting wn_re[0] = 0 and wn_im[0] = 0 makes it easier to check the waveform.
// It may also reduce power consumption slightly.
//
// wn_re = cos(-2pi*n/64) wn_im = sin(-2pi*n/64)
assign wn_re[ 0] = 16'h0000; assign wn_im[ 0] = 16'h0000; // 0 1.000 -0.000
assign wn_re[ 1] = 16'h7F62; assign wn_im[ 1] = 16'hF374; // 1 0.995 -0.098
assign wn_re[ 2] = 16'h7D8A; assign wn_im[ 2] = 16'hE707; // 2 0.981 -0.195
assign wn_re[ 3] = 16'h7A7D; assign wn_im[ 3] = 16'hDAD8; // 3 0.957 -0.290
assign wn_re[ 4] = 16'h7642; assign wn_im[ 4] = 16'hCF04; // 4 0.924 -0.383
assign wn_re[ 5] = 16'h70E3; assign wn_im[ 5] = 16'hC3A9; // 5 0.882 -0.471
assign wn_re[ 6] = 16'h6A6E; assign wn_im[ 6] = 16'hB8E3; // 6 0.831 -0.556
assign wn_re[ 7] = 16'h62F2; assign wn_im[ 7] = 16'hAECC; // 7 0.773 -0.634
assign wn_re[ 8] = 16'h5A82; assign wn_im[ 8] = 16'hA57E; // 8 0.707 -0.707
assign wn_re[ 9] = 16'h5134; assign wn_im[ 9] = 16'h9D0E; // 9 0.634 -0.773
assign wn_re[10] = 16'h471D; assign wn_im[10] = 16'h9592; // 10 0.556 -0.831
assign wn_re[11] = 16'h3C57; assign wn_im[11] = 16'h8F1D; // 11 0.471 -0.882
assign wn_re[12] = 16'h30FC; assign wn_im[12] = 16'h89BE; // 12 0.383 -0.924
assign wn_re[13] = 16'h2528; assign wn_im[13] = 16'h8583; // 13 0.290 -0.957
assign wn_re[14] = 16'h18F9; assign wn_im[14] = 16'h8276; // 14 0.195 -0.981
assign wn_re[15] = 16'h0C8C; assign wn_im[15] = 16'h809E; // 15 0.098 -0.995
assign wn_re[16] = 16'h0000; assign wn_im[16] = 16'h8000; // 16 0.000 -1.000
assign wn_re[17] = 16'hxxxx; assign wn_im[17] = 16'hxxxx; // 17 -0.098 -0.995
assign wn_re[18] = 16'hE707; assign wn_im[18] = 16'h8276; // 18 -0.195 -0.981
assign wn_re[19] = 16'hxxxx; assign wn_im[19] = 16'hxxxx; // 19 -0.290 -0.957
assign wn_re[20] = 16'hCF04; assign wn_im[20] = 16'h89BE; // 20 -0.383 -0.924
assign wn_re[21] = 16'hC3A9; assign wn_im[21] = 16'h8F1D; // 21 -0.471 -0.882
assign wn_re[22] = 16'hB8E3; assign wn_im[22] = 16'h9592; // 22 -0.556 -0.831
assign wn_re[23] = 16'hxxxx; assign wn_im[23] = 16'hxxxx; // 23 -0.634 -0.773
assign wn_re[24] = 16'hA57E; assign wn_im[24] = 16'hA57E; // 24 -0.707 -0.707
assign wn_re[25] = 16'hxxxx; assign wn_im[25] = 16'hxxxx; // 25 -0.773 -0.634
assign wn_re[26] = 16'h9592; assign wn_im[26] = 16'hB8E3; // 26 -0.831 -0.556
assign wn_re[27] = 16'h8F1D; assign wn_im[27] = 16'hC3A9; // 27 -0.882 -0.471
assign wn_re[28] = 16'h89BE; assign wn_im[28] = 16'hCF04; // 28 -0.924 -0.383
assign wn_re[29] = 16'hxxxx; assign wn_im[29] = 16'hxxxx; // 29 -0.957 -0.290
assign wn_re[30] = 16'h8276; assign wn_im[30] = 16'hE707; // 30 -0.981 -0.195
assign wn_re[31] = 16'hxxxx; assign wn_im[31] = 16'hxxxx; // 31 -0.995 -0.098
assign wn_re[32] = 16'hxxxx; assign wn_im[32] = 16'hxxxx; // 32 -1.000 -0.000
assign wn_re[33] = 16'h809E; assign wn_im[33] = 16'h0C8C; // 33 -0.995 0.098
assign wn_re[34] = 16'hxxxx; assign wn_im[34] = 16'hxxxx; // 34 -0.981 0.195
assign wn_re[35] = 16'hxxxx; assign wn_im[35] = 16'hxxxx; // 35 -0.957 0.290
assign wn_re[36] = 16'h89BE; assign wn_im[36] = 16'h30FC; // 36 -0.924 0.383
assign wn_re[37] = 16'hxxxx; assign wn_im[37] = 16'hxxxx; // 37 -0.882 0.471
assign wn_re[38] = 16'hxxxx; assign wn_im[38] = 16'hxxxx; // 38 -0.831 0.556
assign wn_re[39] = 16'h9D0E; assign wn_im[39] = 16'h5134; // 39 -0.773 0.634
assign wn_re[40] = 16'hxxxx; assign wn_im[40] = 16'hxxxx; // 40 -0.707 0.707
assign wn_re[41] = 16'hxxxx; assign wn_im[41] = 16'hxxxx; // 41 -0.634 0.773
assign wn_re[42] = 16'hB8E3; assign wn_im[42] = 16'h6A6E; // 42 -0.556 0.831
assign wn_re[43] = 16'hxxxx; assign wn_im[43] = 16'hxxxx; // 43 -0.471 0.882
assign wn_re[44] = 16'hxxxx; assign wn_im[44] = 16'hxxxx; // 44 -0.383 0.924
assign wn_re[45] = 16'hDAD8; assign wn_im[45] = 16'h7A7D; // 45 -0.290 0.957
assign wn_re[46] = 16'hxxxx; assign wn_im[46] = 16'hxxxx; // 46 -0.195 0.981
assign wn_re[47] = 16'hxxxx; assign wn_im[47] = 16'hxxxx; // 47 -0.098 0.995
assign wn_re[48] = 16'hxxxx; assign wn_im[48] = 16'hxxxx; // 48 -0.000 1.000
assign wn_re[49] = 16'hxxxx; assign wn_im[49] = 16'hxxxx; // 49 0.098 0.995
assign wn_re[50] = 16'hxxxx; assign wn_im[50] = 16'hxxxx; // 50 0.195 0.981
assign wn_re[51] = 16'hxxxx; assign wn_im[51] = 16'hxxxx; // 51 0.290 0.957
assign wn_re[52] = 16'hxxxx; assign wn_im[52] = 16'hxxxx; // 52 0.383 0.924
assign wn_re[53] = 16'hxxxx; assign wn_im[53] = 16'hxxxx; // 53 0.471 0.882
assign wn_re[54] = 16'hxxxx; assign wn_im[54] = 16'hxxxx; // 54 0.556 0.831
assign wn_re[55] = 16'hxxxx; assign wn_im[55] = 16'hxxxx; // 55 0.634 0.773
assign wn_re[56] = 16'hxxxx; assign wn_im[56] = 16'hxxxx; // 56 0.707 0.707
assign wn_re[57] = 16'hxxxx; assign wn_im[57] = 16'hxxxx; // 57 0.773 0.634
assign wn_re[58] = 16'hxxxx; assign wn_im[58] = 16'hxxxx; // 58 0.831 0.556
assign wn_re[59] = 16'hxxxx; assign wn_im[59] = 16'hxxxx; // 59 0.882 0.471
assign wn_re[60] = 16'hxxxx; assign wn_im[60] = 16'hxxxx; // 60 0.924 0.383
assign wn_re[61] = 16'hxxxx; assign wn_im[61] = 16'hxxxx; // 61 0.957 0.290
assign wn_re[62] = 16'hxxxx; assign wn_im[62] = 16'hxxxx; // 62 0.981 0.195
assign wn_re[63] = 16'hxxxx; assign wn_im[63] = 16'hxxxx; // 63 0.995 0.098
endmodule |
module Multiply #(
parameter WIDTH = 16
)(
input signed [WIDTH-1:0] a_re,
input signed [WIDTH-1:0] a_im,
input signed [WIDTH-1:0] b_re,
input signed [WIDTH-1:0] b_im,
output signed [WIDTH-1:0] m_re,
output signed [WIDTH-1:0] m_im
);
wire signed [WIDTH*2-1:0] arbr, arbi, aibr, aibi;
wire signed [WIDTH-1:0] sc_arbr, sc_arbi, sc_aibr, sc_aibi;
// Signed Multiplication
assign arbr = a_re * b_re;
assign arbi = a_re * b_im;
assign aibr = a_im * b_re;
assign aibi = a_im * b_im;
// Scaling
assign sc_arbr = arbr >>> (WIDTH-1);
assign sc_arbi = arbi >>> (WIDTH-1);
assign sc_aibr = aibr >>> (WIDTH-1);
assign sc_aibi = aibi >>> (WIDTH-1);
// Sub/Add
// These sub/add may overflow if unnormalized data is input.
assign m_re = sc_arbr - sc_aibi;
assign m_im = sc_arbi + sc_aibr;
endmodule |
module FFT #(
parameter WIDTH = 32
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
//----------------------------------------------------------------------
// Data must be input consecutively in natural order.
// The result is scaled to 1/N and output in bit-reversed order.
//----------------------------------------------------------------------
wire su1_do_en;
wire[WIDTH-1:0] su1_do_re;
wire[WIDTH-1:0] su1_do_im;
wire su2_do_en;
wire[WIDTH-1:0] su2_do_re;
wire[WIDTH-1:0] su2_do_im;
wire su3_do_en;
wire[WIDTH-1:0] su3_do_re;
wire[WIDTH-1:0] su3_do_im;
wire su4_do_en;
wire[WIDTH-1:0] su4_do_re;
wire[WIDTH-1:0] su4_do_im;
SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (di_en ), // i
.di_re (di_re ), // i
.di_im (di_im ), // i
.do_en (su1_do_en ), // o
.do_re (su1_do_re ), // o
.do_im (su1_do_im ) // o
);
SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su1_do_en ), // i
.di_re (su1_do_re ), // i
.di_im (su1_do_im ), // i
.do_en (su2_do_en ), // o
.do_re (su2_do_re ), // o
.do_im (su2_do_im ) // o
);
SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su2_do_en ), // i
.di_re (su2_do_re ), // i
.di_im (su2_do_im ), // i
.do_en (su3_do_en ), // o
.do_re (su3_do_re ), // o
.do_im (su3_do_im ) // o
);
SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su3_do_en ), // i
.di_re (su3_do_re ), // i
.di_im (su3_do_im ), // i
.do_en (su4_do_en ), // o
.do_re (su4_do_re ), // o
.do_im (su4_do_im ) // o
);
SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
.clock (clock ), // i
.reset (reset ), // i
.di_en (su4_do_en ), // i
.di_re (su4_do_re ), // i
.di_im (su4_do_im ), // i
.do_en (do_en ), // o
.do_re (do_re ), // o
.do_im (do_im ) // o
);
endmodule |
module Butterfly #(
parameter WIDTH = 16,
parameter RH = 0 // Round Half Up
)(
input signed [WIDTH-1:0] x0_re, // Input Data #0 (Real)
input signed [WIDTH-1:0] x0_im, // Input Data #0 (Imag)
input signed [WIDTH-1:0] x1_re, // Input Data #1 (Real)
input signed [WIDTH-1:0] x1_im, // Input Data #1 (Imag)
output signed [WIDTH-1:0] y0_re, // Output Data #0 (Real)
output signed [WIDTH-1:0] y0_im, // Output Data #0 (Imag)
output signed [WIDTH-1:0] y1_re, // Output Data #1 (Real)
output signed [WIDTH-1:0] y1_im // Output Data #1 (Imag)
);
wire signed [WIDTH:0] add_re, add_im, sub_re, sub_im;
// Add/Sub
assign add_re = x0_re + x1_re;
assign add_im = x0_im + x1_im;
assign sub_re = x0_re - x1_re;
assign sub_im = x0_im - x1_im;
// Scaling
assign y0_re = (add_re + RH) >>> 1;
assign y0_im = (add_im + RH) >>> 1;
assign y1_re = (sub_re + RH) >>> 1;
assign y1_im = (sub_im + RH) >>> 1;
endmodule |
module SdfUnit #(
parameter N = 64, // Number of FFT Point
parameter M = 64, // Twiddle Resolution
parameter WIDTH = 16 // Data Bit Length
)(
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
output do_en, // Output Data Enable
output [WIDTH-1:0] do_re, // Output Data (Real)
output [WIDTH-1:0] do_im // Output Data (Imag)
);
// log2 constant function
function integer log2;
input integer x;
integer value;
begin
value = x-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
localparam LOG_N = log2(N); // Bit Length of N
localparam LOG_M = log2(M); // Bit Length of M
//----------------------------------------------------------------------
// Internal Regs and Nets
//----------------------------------------------------------------------
// 1st Butterfly
reg [LOG_N-1:0] di_count; // Input Data Count
wire bf1_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf1_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf1_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf1_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf1_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf1_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db1_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db1_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db1_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db1_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf1_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf1_sp_im; // Single-Path Data Output (Imag)
reg bf1_sp_en; // Single-Path Data Enable
reg [LOG_N-1:0] bf1_count; // Single-Path Data Count
wire bf1_start; // Single-Path Output Trigger
wire bf1_end; // End of Single-Path Data
wire bf1_mj; // Twiddle (-j) Enable
reg [WIDTH-1:0] bf1_do_re; // 1st Butterfly Output Data (Real)
reg [WIDTH-1:0] bf1_do_im; // 1st Butterfly Output Data (Imag)
// 2nd Butterfly
reg bf2_bf; // Butterfly Add/Sub Enable
wire[WIDTH-1:0] bf2_x0_re; // Data #0 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x0_im; // Data #0 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_x1_re; // Data #1 to Butterfly (Real)
wire[WIDTH-1:0] bf2_x1_im; // Data #1 to Butterfly (Imag)
wire[WIDTH-1:0] bf2_y0_re; // Data #0 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y0_im; // Data #0 from Butterfly (Imag)
wire[WIDTH-1:0] bf2_y1_re; // Data #1 from Butterfly (Real)
wire[WIDTH-1:0] bf2_y1_im; // Data #1 from Butterfly (Imag)
wire[WIDTH-1:0] db2_di_re; // Data to DelayBuffer (Real)
wire[WIDTH-1:0] db2_di_im; // Data to DelayBuffer (Imag)
wire[WIDTH-1:0] db2_do_re; // Data from DelayBuffer (Real)
wire[WIDTH-1:0] db2_do_im; // Data from DelayBuffer (Imag)
wire[WIDTH-1:0] bf2_sp_re; // Single-Path Data Output (Real)
wire[WIDTH-1:0] bf2_sp_im; // Single-Path Data Output (Imag)
reg bf2_sp_en; // Single-Path Data Enable
reg [LOG_N-1:0] bf2_count; // Single-Path Data Count
reg bf2_start; // Single-Path Output Trigger
wire bf2_end; // End of Single-Path Data
reg [WIDTH-1:0] bf2_do_re; // 2nd Butterfly Output Data (Real)
reg [WIDTH-1:0] bf2_do_im; // 2nd Butterfly Output Data (Imag)
reg bf2_do_en; // 2nd Butterfly Output Data Enable
// Multiplication
wire[1:0] tw_sel; // Twiddle Select (2n/n/3n)
wire[LOG_N-3:0] tw_num; // Twiddle Number (n)
wire[LOG_N-1:0] tw_addr; // Twiddle Table Address
wire[WIDTH-1:0] tw_re; // Twiddle Factor (Real)
wire[WIDTH-1:0] tw_im; // Twiddle Factor (Imag)
reg mu_en; // Multiplication Enable
wire[WIDTH-1:0] mu_a_re; // Multiplier Input (Real)
wire[WIDTH-1:0] mu_a_im; // Multiplier Input (Imag)
wire[WIDTH-1:0] mu_m_re; // Multiplier Output (Real)
wire[WIDTH-1:0] mu_m_im; // Multiplier Output (Imag)
reg [WIDTH-1:0] mu_do_re; // Multiplication Output Data (Real)
reg [WIDTH-1:0] mu_do_im; // Multiplication Output Data (Imag)
reg mu_do_en; // Multiplication Output Data Enable
//----------------------------------------------------------------------
// 1st Butterfly
//----------------------------------------------------------------------
always @(posedge clock or posedge reset) begin
if (reset) begin
di_count <= {LOG_N{1'b0}};
end else begin
di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_bf = di_count[LOG_M-1];
// Set unknown value x for verification
assign bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
assign bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
assign bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
assign bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
.x0_re (bf1_x0_re ), // i
.x0_im (bf1_x0_im ), // i
.x1_re (bf1_x1_re ), // i
.x1_im (bf1_x1_im ), // i
.y0_re (bf1_y0_re ), // o
.y0_im (bf1_y0_im ), // o
.y1_re (bf1_y1_re ), // o
.y1_im (bf1_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
.clock (clock ), // i
.di_re (db1_di_re ), // i
.di_im (db1_di_im ), // i
.do_re (db1_do_re ), // o
.do_im (db1_do_im ) // o
);
assign db1_di_re = bf1_bf ? bf1_y1_re : di_re;
assign db1_di_im = bf1_bf ? bf1_y1_im : di_im;
assign bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ? db1_do_im : db1_do_re;
assign bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf1_sp_en <= 1'b0;
bf1_count <= {LOG_N{1'b0}};
end else begin
bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
end
end
assign bf1_start = (di_count == (2**(LOG_M-1)-1));
assign bf1_end = (bf1_count == (2**LOG_N-1));
assign bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
always @(posedge clock) begin
bf1_do_re <= bf1_sp_re;
bf1_do_im <= bf1_sp_im;
end
//----------------------------------------------------------------------
// 2nd Butterfly
//----------------------------------------------------------------------
always @(posedge clock) begin
bf2_bf <= bf1_count[LOG_M-2];
end
// Set unknown value x for verification
assign bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
assign bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
assign bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
assign bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
// Negative bias occurs when RH=0 and positive bias occurs when RH=1.
// Using both alternately reduces the overall rounding error.
Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
.x0_re (bf2_x0_re ), // i
.x0_im (bf2_x0_im ), // i
.x1_re (bf2_x1_re ), // i
.x1_im (bf2_x1_im ), // i
.y0_re (bf2_y0_re ), // o
.y0_im (bf2_y0_im ), // o
.y1_re (bf2_y1_re ), // o
.y1_im (bf2_y1_im ) // o
);
DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
.clock (clock ), // i
.di_re (db2_di_re ), // i
.di_im (db2_di_im ), // i
.do_re (db2_do_re ), // o
.do_im (db2_do_im ) // o
);
assign db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
assign db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
assign bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
assign bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_sp_en <= 1'b0;
bf2_count <= {LOG_N{1'b0}};
end else begin
bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
end
end
always @(posedge clock) begin
bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
end
assign bf2_end = (bf2_count == (2**LOG_N-1));
always @(posedge clock) begin
bf2_do_re <= bf2_sp_re;
bf2_do_im <= bf2_sp_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
bf2_do_en <= 1'b0;
end else begin
bf2_do_en <= bf2_sp_en;
end
end
//----------------------------------------------------------------------
// Multiplication
//----------------------------------------------------------------------
assign tw_sel[1] = bf2_count[LOG_M-2];
assign tw_sel[0] = bf2_count[LOG_M-1];
assign tw_num = bf2_count << (LOG_N-LOG_M);
assign tw_addr = tw_num * tw_sel;
Twiddle TW (
.clock (clock ), // i
.addr (tw_addr), // i
.tw_re (tw_re ), // o
.tw_im (tw_im ) // o
);
// Multiplication is bypassed when twiddle address is 0.
always @(posedge clock) begin
mu_en <= (tw_addr != {LOG_N{1'b0}});
end
// Set unknown value x for verification
assign mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
assign mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
Multiply #(.WIDTH(WIDTH)) MU (
.a_re (mu_a_re), // i
.a_im (mu_a_im), // i
.b_re (tw_re ), // i
.b_im (tw_im ), // i
.m_re (mu_m_re), // o
.m_im (mu_m_im) // o
);
always @(posedge clock) begin
mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
end
always @(posedge clock or posedge reset) begin
if (reset) begin
mu_do_en <= 1'b0;
end else begin
mu_do_en <= bf2_do_en;
end
end
// No multiplication required at final stage
assign do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
assign do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
assign do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
endmodule |
module rst_gen (
input clk_i,
input rst_i,
output rst_o
);
/* try to generate a reset */
reg [2:0] rst_cpt;
always @(posedge clk_i) begin
if (rst_i)
rst_cpt = 3'b0;
else begin
if (rst_cpt == 3'b100)
rst_cpt = rst_cpt;
else
rst_cpt = rst_cpt + 3'b1;
end
end
assign rst_o = !rst_cpt[2];
endmodule |
module blink (
input clk_i,
output reg led_o
);
localparam MAX = 2_500_000;
localparam WIDTH = $clog2(MAX);
wire rst_s;
wire clk_s;
assign clk_s = clk_i;
//pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));
rst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));
reg [WIDTH-1:0] cpt_s;
wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
wire end_s = cpt_s == MAX-1;
always @(posedge clk_s) begin
cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;
if (rst_s)
led_o <= 1'b0;
else if (end_s)
led_o <= ~led_o;
end
endmodule |
module blink (
input clk_i,
output P2_3, P2_4, P2_5, P2_6,
P2_25, P2_26, P2_27, P2_28
);
localparam MAX = 2_500_000;
localparam WIDTH = $clog2(MAX);
wire rst_s;
wire clk_s;
assign clk_s = clk_i;
//pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));
rst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));
reg [WIDTH-1:0] cpt_s;
wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
wire end_s = cpt_s == MAX-1;
reg [7:0] counter = 0;
assign P2_28 = !counter[7];
assign P2_27 = !counter[6];
assign P2_26 = !counter[5];
assign P2_25 = !counter[4];
assign P2_3 = !counter[3];
assign P2_4 = !counter[2];
assign P2_5 = !counter[1];
assign P2_6 = !counter[0];
always @(posedge clk_s) begin
cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;
if (rst_s)
counter <= 1'b0;
else if (end_s)
counter <= counter + 1;
end
endmodule |
module pll
(
input clki, // 25 MHz, 0 deg
output clko, // 31.25 MHz, 0 deg
output locked
);
(* FREQUENCY_PIN_CLKI="25" *)
(* FREQUENCY_PIN_CLKOP="31.25" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.OUTDIVIDER_MUXA("DIVA"),
.OUTDIVIDER_MUXB("DIVB"),
.OUTDIVIDER_MUXC("DIVC"),
.OUTDIVIDER_MUXD("DIVD"),
.CLKI_DIV(4),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_DIV(19),
.CLKOP_CPHASE(9),
.CLKOP_FPHASE(0),
.FEEDBK_PATH("CLKOP"),
.CLKFB_DIV(5)
) pll_i (
.RST(1'b0),
.STDBY(1'b0),
.CLKI(clki),
.CLKOP(clko),
.CLKFB(clko),
.CLKINTFB(),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b1),
.PHASESTEP(1'b1),
.PHASELOADREG(1'b1),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.LOCK(locked)
);
endmodule |
module pong(clk25, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, vga_R1, vga_G1, vga_B1, vga_R2, vga_G2, vga_B2, vga_R3, vga_G3, vga_B3, quadA, quadB);
input clk25;
output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, vga_R1, vga_G1, vga_B1, vga_R2, vga_G2, vga_B2, vga_R3, vga_G3, vga_B3;
input quadA, quadB;
wire inDisplayArea;
wire [9:0] CounterX;
wire [8:0] CounterY;
wire clk;
/* 640x480 55Hz */
/* icepll -o 31.5Mhz */
/* please refer to http://tinyvga.com/vga-timing */
/*
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
//.DIVF(7'b1010011), // DIVF = 83
.DIVF(7'b0111000), // DIVF = 83
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (
.RESETB(1'b1),
.BYPASS(1'b0),
.PACKAGEPIN(clk25),
.PLLOUTCORE(clk)
);
*/
wire locked;
pll pll(
.clki(clk25),
.clko(clk),
.locked(locked)
);
hvsync_generator syncgen(.clk(clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync),
.inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));
/////////////////////////////////////////////////////////////////
reg [8:0] PaddlePosition;
reg [2:0] quadAr, quadBr;
always @(posedge clk) quadAr <= {quadAr[1:0], quadA};
always @(posedge clk) quadBr <= {quadBr[1:0], quadB};
always @(posedge clk)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1])
begin
if(~&PaddlePosition) // make sure the value doesn't overflow
PaddlePosition <= PaddlePosition + 1;
end
else
begin
if(|PaddlePosition) // make sure the value doesn't underflow
PaddlePosition <= PaddlePosition - 1;
end
end
/////////////////////////////////////////////////////////////////
reg [9:0] ballX;
reg [8:0] ballY;
reg ball_inX, ball_inY;
always @(posedge clk)
if(ball_inX==0) ball_inX <= (CounterX==ballX) & ball_inY; else ball_inX <= !(CounterX==ballX+16);
always @(posedge clk)
if(ball_inY==0) ball_inY <= (CounterY==ballY); else ball_inY <= !(CounterY==ballY+16);
wire ball = ball_inX & ball_inY;
/////////////////////////////////////////////////////////////////
wire border = (CounterX[9:3]==0) || (CounterX[9:3]==79) || (CounterY[8:3]==0) || (CounterY[8:3]==59);
wire paddle = (CounterX>=PaddlePosition+8) && (CounterX<=PaddlePosition+120) && (CounterY[8:4]==27);
wire BouncingObject = border | paddle; // active if the border or paddle is redrawing itself
reg ResetCollision;
always @(posedge clk) ResetCollision <= (CounterY==500) & (CounterX==0); // active only once for every video frame
reg CollisionX1, CollisionX2, CollisionY1, CollisionY2;
always @(posedge clk) if(ResetCollision) CollisionX1<=0; else if(BouncingObject & (CounterX==ballX ) & (CounterY==ballY+ 8)) CollisionX1<=1;
always @(posedge clk) if(ResetCollision) CollisionX2<=0; else if(BouncingObject & (CounterX==ballX+16) & (CounterY==ballY+ 8)) CollisionX2<=1;
always @(posedge clk) if(ResetCollision) CollisionY1<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY )) CollisionY1<=1;
always @(posedge clk) if(ResetCollision) CollisionY2<=0; else if(BouncingObject & (CounterX==ballX+ 8) & (CounterY==ballY+16)) CollisionY2<=1;
/////////////////////////////////////////////////////////////////
wire UpdateBallPosition = ResetCollision; // update the ball position at the same time that we reset the collision detectors
reg ball_dirX, ball_dirY;
always @(posedge clk)
if(UpdateBallPosition)
begin
if(~(CollisionX1 & CollisionX2)) // if collision on both X-sides, don't move in the X direction
begin
ballX <= ballX + (ball_dirX ? -1 : 1);
if(CollisionX2) ball_dirX <= 1; else if(CollisionX1) ball_dirX <= 0;
end
if(~(CollisionY1 & CollisionY2)) // if collision on both Y-sides, don't move in the Y direction
begin
ballY <= ballY + (ball_dirY ? -1 : 1);
if(CollisionY2) ball_dirY <= 1; else if(CollisionY1) ball_dirY <= 0;
end
end
/////////////////////////////////////////////////////////////////
wire R = BouncingObject | ball | (CounterX[3] ^ CounterY[3]);
wire G = BouncingObject | ball;
wire B = BouncingObject | ball;
reg vga_R, vga_G, vga_B;
reg vga_R1, vga_G1, vga_B1;
reg vga_R2, vga_G2, vga_B2;
reg vga_R3, vga_G3, vga_B3;
always @(posedge clk)
begin
vga_R <= R & inDisplayArea;
vga_R1 <= R & inDisplayArea;
vga_R2 <= R & inDisplayArea;
vga_R3 <= R & inDisplayArea;
vga_G <= G & inDisplayArea;
vga_G1 <= G & inDisplayArea;
vga_G2 <= G & inDisplayArea;
vga_G3 <= G & inDisplayArea;
vga_B <= B & inDisplayArea;
vga_B1 <= B & inDisplayArea;
vga_B2 <= B & inDisplayArea;
vga_B3 <= B & inDisplayArea;
end
endmodule |
module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [8:0] CounterY;
/* 640 x 480 @ 55Hz */
//////////////////////////////////////////////////
reg [9:0] CounterX;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==10'h2FF); /* 768: 0-767 */
always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else
CounterX <= CounterX + 1;
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX[9:4]==6'h2D); // 45, change this value to move the display horizontally
vga_VS <= (CounterY==500); // change this value to move the display vertically
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
inDisplayArea <= !(CounterX==639);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule |
module vgatestsrc(i_pixclk, i_reset,
// External connections
i_width, i_height,
i_rd, i_newline, i_newframe,
// VGA connections
o_pixel);
parameter BITS_PER_COLOR = 4,
HW=12, VW=12;
//HW=13,VW=11;
localparam BPC = BITS_PER_COLOR,
BITS_PER_PIXEL = 3 * BPC,
BPP = BITS_PER_PIXEL;
//
input wire i_pixclk, i_reset;
input wire [HW-1:0] i_width;
input wire [VW-1:0] i_height;
//
input wire i_rd, i_newline, i_newframe;
//
output reg [(BPP-1):0] o_pixel;
wire [BPP-1:0] white, black, purplish_blue, purple, dark_gray,
darkest_gray, mid_white, mid_cyan, mid_magenta,
mid_red, mid_green, mid_blue, mid_yellow;
wire [BPC-1:0] midv, mid_off;
assign midv = { 2'b11, {(BPC-2){1'b0}} };
assign mid_off = { (BPC){1'b0} };
assign white = {(BPP){1'b1}};
assign black = {(BPP){1'b0}};
assign purplish_blue = {
{(BPC){1'b0}},
3'b001, {(BPC-3){1'b0}},
2'b01, {(BPC-2){1'b0}} };
assign purple = { {2'b00, {(BPC-2){1'b1}} }, {(BPC){1'b0}},
{ 1'b0, {(BPC-1){1'b1}} } };
assign dark_gray = {(3){ { 4'b0010, {(BPC-4){1'b0}} } }};
assign darkest_gray = {(3){ { 4'b0001, {(BPC-4){1'b0}} } }};
assign mid_white = { midv, midv, midv };
assign mid_yellow = { midv, midv, mid_off };
assign mid_red = { midv, mid_off, mid_off };
assign mid_green = { mid_off, midv, mid_off };
assign mid_blue = { mid_off, mid_off, midv };
assign mid_cyan = { mid_off, midv, midv };
assign mid_magenta = { midv, mid_off, midv };
reg [HW-1:0] hpos, hedge;
reg [VW-1:0] ypos, yedge;
reg [3:0] yline, hbar;
//
//
// 1 Border
// 8 BARS
// 1 short bar
// 3 fat bars
// 1 border
// 1 gradient bar
// 1 border
//
reg dline;
always @(posedge i_pixclk)
if ((i_reset)||(i_newframe)||(i_newline))
dline <= 1'b0;
else if (i_rd)
dline <= 1'b1;
always @(posedge i_pixclk)
if ((i_reset)||(i_newframe))
begin
ypos <= 0;
yline <= 0;
yedge <= { 4'h0, i_height[(VW-1):4] };
end else if (i_newline)
begin
ypos <= ypos + { {(VW-1){1'h0}}, dline };
if (ypos >= yedge)
begin
yline <= yline + 1'b1;
yedge <= yedge + { 4'h0, i_height[(VW-1):4] };
end
end
initial hpos = 0;
initial hbar = 0;
initial hedge = 0; // { 4'h0, i_width[(HW-1):4] };
always @(posedge i_pixclk)
if ((i_reset)||(i_newline))
begin
hpos <= 0;
hbar <= 0;
hedge <= { 4'h0, i_width[(HW-1):4] };
end else if (i_rd)
begin
hpos <= hpos + 1'b1;
if (hpos >= hedge)
begin
hbar <= hbar + 1'b1;
hedge <= hedge + { 4'h0, i_width[(HW-1):4] };
end
end
reg [BPP-1:0] topbar, midbar, fatbar, gradient, pattern;
always @(posedge i_pixclk)
case(hbar[3:0])
4'h0: topbar <= black;
4'h1: topbar <= mid_white;
4'h2: topbar <= mid_white;
4'h3: topbar <= mid_yellow;
4'h4: topbar <= mid_yellow;
4'h5: topbar <= mid_cyan;
4'h6: topbar <= mid_cyan;
4'h7: topbar <= mid_green;
4'h8: topbar <= mid_green;
4'h9: topbar <= mid_magenta;
4'ha: topbar <= mid_magenta;
4'hb: topbar <= mid_red;
4'hc: topbar <= mid_red;
4'hd: topbar <= mid_blue;
4'he: topbar <= mid_blue;
4'hf: topbar <= black;
endcase
always @(posedge i_pixclk)
case(hbar[3:0])
4'h0: midbar <= black;
4'h1: midbar <= mid_blue;
4'h2: midbar <= mid_blue;
4'h3: midbar <= black;
4'h4: midbar <= black;
4'h5: midbar <= mid_magenta;
4'h6: midbar <= mid_magenta;
4'h7: midbar <= black;
4'h8: midbar <= black;
4'h9: midbar <= mid_cyan;
4'ha: midbar <= mid_cyan;
4'hb: midbar <= black;
4'hc: midbar <= black;
4'hd: midbar <= mid_white;
4'he: midbar <= mid_white;
4'hf: midbar <= black;
endcase
always @(posedge i_pixclk)
case(hbar[3:0])
4'h0: fatbar <= black;
4'h1: fatbar <= purplish_blue;
4'h2: fatbar <= purplish_blue;
4'h3: fatbar <= purplish_blue;
4'h4: fatbar <= white;
4'h5: fatbar <= white;
4'h6: fatbar <= white;
4'h7: fatbar <= purple;
4'h8: fatbar <= purple;
4'h9: fatbar <= purple;
4'ha: fatbar <= darkest_gray;
4'hb: fatbar <= black;
4'hc: fatbar <= dark_gray;
4'hd: fatbar <= darkest_gray;
4'he: fatbar <= black;
4'hf: fatbar <= black;
endcase
reg [(HW-1):0] last_width;
always @(posedge i_pixclk)
last_width <= i_width;
// Attempt to discover 1/i_width in h_step
localparam FRACB=16;
//
reg [(FRACB-1):0] hfrac, h_step;
always @(posedge i_pixclk)
if ((i_reset)||(i_newline))
hfrac <= 0;
else if (i_rd)
hfrac <= hfrac + h_step;
always @(posedge i_pixclk)
if ((i_reset)||(i_width != last_width))
h_step <= 1;
else if ((i_newline)&&(hfrac > 0))
begin
if (hfrac < {(FRACB){1'b1}} - { {(FRACB-HW){1'b0}}, i_width })
h_step <= h_step + 1'b1;
else if (hfrac < { {(FRACB-HW){1'b0}}, i_width })
h_step <= h_step - 1'b1;
end
always @(posedge i_pixclk)
case(hfrac[FRACB-1:FRACB-4])
4'h0: gradient <= black;
// Red
4'h1: gradient <= { 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)], {(2){mid_off}} };
4'h2: gradient <= { 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)], {(2){mid_off}} };
4'h3: gradient <= black;
// Green
4'h4: gradient <= { mid_off, 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)], mid_off };
4'h5: gradient <= { mid_off, 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)], mid_off };
4'h6: gradient <= black;
// Blue
4'h7: gradient <= { {(2){mid_off}}, 1'b0, hfrac[(FRACB-5):(FRACB-3-BPC)] };
4'h8: gradient <= { {(2){mid_off}}, 1'b1, hfrac[(FRACB-5):(FRACB-3-BPC)] };
4'h9: gradient <= black;
// Gray
4'ha: gradient <= {(3){ 2'b00, hfrac[(FRACB-5):(FRACB-2-BPC)] }};
4'hb: gradient <= {(3){ 2'b01, hfrac[(FRACB-5):(FRACB-2-BPC)] }};
4'hc: gradient <= {(3){ 2'b10, hfrac[(FRACB-5):(FRACB-2-BPC)] }};
4'hd: gradient <= {(3){ 2'b11, hfrac[(FRACB-5):(FRACB-2-BPC)] }};
4'he: gradient <= black;
//
4'hf: gradient <= black;
endcase
always @(posedge i_pixclk)
case(yline)
4'h0: pattern <= black;
4'h1: pattern <= topbar; //
4'h2: pattern <= topbar;
4'h3: pattern <= topbar;
4'h4: pattern <= topbar;
4'h5: pattern <= topbar;
4'h6: pattern <= topbar;
4'h7: pattern <= topbar;
4'h8: pattern <= topbar;
4'h9: pattern <= midbar; //
4'ha: pattern <= fatbar; //
4'hb: pattern <= fatbar;
4'hc: pattern <= fatbar;
4'hd: pattern <= black;
4'he: pattern <= gradient;
4'hf: pattern <= black;
endcase
always @(posedge i_pixclk)
if (i_newline)
o_pixel <= white;
else if (i_rd)
begin
if (hpos == i_width-12'd3)
o_pixel <= white;
else if ((ypos == 0)||(ypos == i_height-1))
o_pixel <= white;
else
o_pixel <= pattern;
end
endmodule |
module TMDS_encoder(
input clk, // 250 MHz
input [7:0] VD, // video data (red, green or blue)
input [1:0] CD, // control data
input VDE, // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
output reg [9:0] TMDS = 0
);
wire [3:0] Nb1s = {3'b0, VD[0]} + {3'b0, VD[1]} + {3'b0, VD[2]}
+ {3'b0, VD[3]} + {3'b0, VD[4]} + {3'b0, VD[5]}
+ {3'b0, VD[6]} + {3'b0, VD[7]};
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
// To keep Verilator happy, we create individual wires, determine
// their values and then merge them into q_m[]
wire QM0, QM1, QM2, QM3, QM4, QM5, QM6, QM7, QM8;
assign QM0= VD[0];
assign QM1= QM0 ^ VD[1] ^ XNOR;
assign QM2= QM1 ^ VD[2] ^ XNOR;
assign QM3= QM2 ^ VD[3] ^ XNOR;
assign QM4= QM3 ^ VD[4] ^ XNOR;
assign QM5= QM4 ^ VD[5] ^ XNOR;
assign QM6= QM5 ^ VD[6] ^ XNOR;
assign QM7= QM6 ^ VD[7] ^ XNOR;
assign QM8= ~XNOR;
wire [8:0] q_m = { QM8, QM7, QM6, QM5, QM4, QM3, QM2, QM1, QM0 };
reg [3:0] balance_acc = 0;
wire [3:0] balance = {3'b0, q_m[0]} + {3'b0, q_m[1]} + {3'b0, q_m[2]}
+ {3'b0, q_m[3]} + {3'b0, q_m[4]} + {3'b0, q_m[5]}
+ {3'b0, q_m[6]} + {3'b0, q_m[7]} - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance
- {3'b0,
({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0)) };
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);
always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;
endmodule |
module clock
(
input clkin_25MHz,
output clk_125MHz,
output clk_250MHz,
output clk_25MHz,
output clk_83M333Hz,
output locked
);
wire int_locked;
(* ICP_CURRENT="9" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL
#(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.CLKOS_FPHASE(0),
.CLKOP_FPHASE(0),
.CLKOS3_CPHASE(5),
.CLKOS2_CPHASE(0),
.CLKOS_CPHASE(1),
.CLKOP_CPHASE(3),
.OUTDIVIDER_MUXD("DIVD"),
.OUTDIVIDER_MUXC("DIVC"),
.OUTDIVIDER_MUXB("DIVB"),
.OUTDIVIDER_MUXA("DIVA"),
.CLKOS3_ENABLE("ENABLED"),
.CLKOS2_ENABLE("ENABLED"),
.CLKOS_ENABLE("ENABLED"),
.CLKOP_ENABLE("ENABLED"),
.CLKOS3_DIV(0),
.CLKOS2_DIV(20),
.CLKOS_DIV(2),
.CLKOP_DIV(4),
.CLKFB_DIV(5),
.CLKI_DIV(1),
.FEEDBK_PATH("CLKOP")
)
pll_i
(
.CLKI(clkin_25MHz),
.CLKFB(clk_125MHz),
.CLKOP(clk_125MHz),
.CLKOS(clk_250MHz),
.CLKOS2(clk_25MHz),
.CLKOS3(clk_83M333Hz),
.RST(1'b0),
.STDBY(1'b0),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b0),
.PHASESTEP(1'b0),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.ENCLKOS(1'b0),
.ENCLKOS2(1'b0),
.ENCLKOS3(1'b0),
.LOCK(locked),
.INTLOCK(int_locked)
);
endmodule |
module llhdmi(
i_tmdsclk, i_pixclk,
i_reset, i_red, i_grn, i_blu,
o_rd, o_newline, o_newframe,
`ifdef VERILATOR
o_TMDS_red, o_TMDS_grn, o_TMDS_blu,
`endif
o_red, o_grn, o_blu);
input wire i_tmdsclk; // TMDS clock
input wire i_pixclk; // Pixel clock, 10 times slower than i_tmdsclk
input wire i_reset; // Reset this module when strobed high
input wire [7:0] i_red; // Red green and blue colour values
input wire [7:0] i_grn; // for each pixel
input wire [7:0] i_blu;
output wire o_rd; // True when we can accept pixel data
output reg o_newline; // True on last pixel of each line
output reg o_newframe; // True on last pixel of each frame
output wire o_red; // Red TMDS pixel stream
output wire o_grn; // Green TMDS pixel stream
output wire o_blu; // Blue TMDS pixel stream
`ifdef VERILATOR
output wire [9:0] o_TMDS_red, o_TMDS_grn, o_TMDS_blu;
assign o_TMDS_red= TMDS_red;
assign o_TMDS_grn= TMDS_grn;
assign o_TMDS_blu= TMDS_blu;
`endif
reg [9:0] CounterX, CounterY;
reg hSync, vSync, DrawArea;
// Keep track of the current X/Y pixel position
always @(posedge i_pixclk)
if (i_reset)
CounterX <= 0;
else
CounterX <= (CounterX==799) ? 0 : CounterX+1;
always @(posedge i_pixclk)
if (i_reset)
CounterY <= 0;
else if (CounterX==799) begin
CounterY <= (CounterY==524) ? 0 : CounterY+1;
end
// Signal end of line, end of frame
always @(posedge i_pixclk) begin
o_newline <= (CounterX==639) ? 1 : 0;
o_newframe <= (CounterX==639) && (CounterY==479) ? 1 : 0;
end
// Determine when we are in a drawable area
always @(posedge i_pixclk)
DrawArea <= (CounterX<640) && (CounterY<480);
assign o_rd= ~i_reset & DrawArea;
// Generate horizontal and vertical sync pulses
always @(posedge i_pixclk)
hSync <= (CounterX>=656) && (CounterX<752);
always @(posedge i_pixclk)
vSync <= (CounterY>=490) && (CounterY<492);
// Convert the 8-bit colours into 10-bit TMDS values
wire [9:0] TMDS_red, TMDS_grn, TMDS_blu;
TMDS_encoder encode_R(.clk(i_pixclk), .VD(i_red), .CD(2'b00),
.VDE(DrawArea), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(i_pixclk), .VD(i_grn), .CD(2'b00),
.VDE(DrawArea), .TMDS(TMDS_grn));
TMDS_encoder encode_B(.clk(i_pixclk), .VD(i_blu), .CD({vSync,hSync}),
.VDE(DrawArea), .TMDS(TMDS_blu));
// Strobe the TMDS_shift_load once every 10 i_tmdsclks
// i.e. at the start of new pixel data
reg [3:0] TMDS_mod10=0;
reg TMDS_shift_load=0;
always @(posedge i_tmdsclk) begin
if (i_reset) begin
TMDS_mod10 <= 0;
TMDS_shift_load <= 0;
end else begin
TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
TMDS_shift_load <= (TMDS_mod10==4'd9);
end
end
// Latch the TMDS colour values into three shift registers
// at the start of the pixel, then shift them one bit each i_tmdsclk.
// We will then output the LSB on each i_tmdsclk.
reg [9:0] TMDS_shift_red=0, TMDS_shift_grn=0, TMDS_shift_blu=0;
always @(posedge i_tmdsclk) begin
if (i_reset) begin
TMDS_shift_red <= 0;
TMDS_shift_grn <= 0;
TMDS_shift_blu <= 0;
end else begin
TMDS_shift_red <= TMDS_shift_load ? TMDS_red: {1'b0, TMDS_shift_red[9:1]};
TMDS_shift_grn <= TMDS_shift_load ? TMDS_grn: {1'b0, TMDS_shift_grn[9:1]};
TMDS_shift_blu <= TMDS_shift_load ? TMDS_blu: {1'b0, TMDS_shift_blu[9:1]};
end
end
// Finally output the LSB of each color bitstream
assign o_red= TMDS_shift_red[0];
assign o_grn= TMDS_shift_grn[0];
assign o_blu= TMDS_shift_blu[0];
endmodule |
module ULX3S_25F (
input clk_25mhz,
output [3:0] gpdi_dp, gpdi_dn,
output wifi_gpio0);
// Tie gpio0 high, this keeps the board from rebooting
assign wifi_gpio0 = 1'b1;
wire clk_25MHz, clk_250MHz;
clock clock_instance(
.clkin_25MHz(clk_25mhz),
.clk_25MHz(clk_25MHz),
.clk_250MHz(clk_250MHz)
);
wire [7:0] red, grn, blu;
wire [23:0] pixel;
assign red= pixel[23:16];
assign grn= pixel[15:8];
assign blu= pixel[7:0];
wire o_red;
wire o_grn;
wire o_blu;
wire o_rd, o_newline, o_newframe;
// A reset line that goes low after 16 ticks
reg [2:0] reset_cnt = 0;
wire reset = ~reset_cnt[2];
always @(posedge clk_25mhz)
if (reset) reset_cnt <= reset_cnt + 1;
llhdmi llhdmi_instance(
.i_tmdsclk(clk_250MHz), .i_pixclk(clk_25MHz),
.i_reset(reset), .i_red(red), .i_grn(grn), .i_blu(blu),
.o_rd(o_rd), .o_newline(o_newline), .o_newframe(o_newframe),
.o_red(o_red), .o_grn(o_grn), .o_blu(o_blu));
vgatestsrc #(.BITS_PER_COLOR(8))
vgatestsrc_instance(
.i_pixclk(clk_25MHz), .i_reset(reset),
.i_width(640), .i_height(480),
.i_rd(o_rd), .i_newline(o_newline), .i_newframe(o_newframe),
.o_pixel(pixel));
OBUFDS OBUFDS_red(.I(o_red), .O(gpdi_dp[2]), .OB(gpdi_dn[2]));
OBUFDS OBUFDS_grn(.I(o_grn), .O(gpdi_dp[1]), .OB(gpdi_dn[1]));
OBUFDS OBUFDS_blu(.I(o_blu), .O(gpdi_dp[0]), .OB(gpdi_dn[0]));
OBUFDS OBUFDS_clock(.I(clk_25MHz), .O(gpdi_dp[3]), .OB(gpdi_dn[3]));
endmodule |
module OBUFDS(
input I, // input
output O, // positive output
output OB // negative output
);
assign O = I;
assign OB = ~I;
endmodule |
module pll(input clki,
output locked,
output clko
);
wire clkfb;
wire clkos;
wire clkop;
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.CLKOP_FPHASE(0),
.CLKOP_CPHASE(23),
.OUTDIVIDER_MUXA("DIVA"),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_DIV(48),
.CLKFB_DIV(1),
.CLKI_DIV(2),
.FEEDBK_PATH("INT_OP")
) pll_i (
.CLKI(clki),
.CLKFB(clkfb),
.CLKINTFB(clkfb),
.CLKOP(clkop),
.RST(1'b0),
.STDBY(1'b0),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b0),
.PHASESTEP(1'b0),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.LOCK(locked)
);
assign clko = clkop;
endmodule |
module top_checkered (
input wire clk_25mhz,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn
);
// checkered red green blue red green blue
wire [15:0] color = x[3] ^ y[3] ? {5'd0, x[6:1], 5'd0} : {y[5:1], 6'd0, 5'd0};
wire [6:0] x, y;
/* 0.95inch oled SSD1331, resolution 96 x 64 */
oled_video #(
.C_init_file("oled_init_16bit.mem"),
.C_init_size(44)
) oled_video_inst (
.clk(clk_25mhz),
.x(x),
.y(y),
.color(color),
.oled_csn(oled_csn),
.oled_clk(oled_clk),
.oled_mosi(oled_mosi),
.oled_dc(oled_dc),
.oled_resn(oled_resn)
);
endmodule |
module LCDC
(
input rst,
input pclk,
output LCD_DE,
output LCD_HSYNC,
output LCD_VSYNC,
output [4:0] LCD_B,
output [5:0] LCD_G,
output [4:0] LCD_R
);
reg [15:0] x;
reg [15:0] y;
localparam vbp = 16'd12;
localparam vpulse = 16'd1;
localparam vact = 16'd272;
localparam vfp = 16'd1;
localparam hbp = 16'd43;
localparam hpulse = 16'd1;
localparam hact = 16'd480;
localparam hfp = 16'd2;
/*
localparam vbp = 16'd12;
localparam vpulse = 16'd11;
localparam vact = 16'd272;
localparam vfp= 16'd8;
localparam hbp = 16'd50;
localparam hpulse = 16'd10;
localparam hact = 16'd480;
localparam hfp= 16'd8;
*/
/*
localparam vbp = 16'd0; //6
localparam vpulse = 16'd5;
localparam vact = 16'd480;
localparam vfp= 16'd45; //62
localparam hbp = 16'd182;
localparam hpulse = 16'd1;
localparam hact = 16'd800;
localparam hfp= 16'd210;
*/
localparam xmax = hact + hbp + hfp;
localparam ymax = vact + vbp + vfp;
always @( posedge pclk or negedge rst )begin
if( !rst ) begin
y <= 16'b0;
x <= 16'b0;
end
else if( x == xmax ) begin
x <= 16'b0;
y <= y + 1'b1;
end
else if( y == ymax ) begin
y <= 16'b0;
x <= 16'b0;
end
else
x <= x + 1'b1;
end
assign LCD_HSYNC = (( x >= hpulse )&&( x <= (xmax-hfp))) ? 1'b0 : 1'b1;
assign LCD_VSYNC = (( y >= vpulse )&&( y <= (ymax-0) )) ? 1'b0 : 1'b1;
assign LCD_DE = ( ( x >= hbp )&&
( x <= xmax-hfp ) &&
( y >= vbp ) &&
( y <= ymax-vfp-1 )) ? 1'b1 : 1'b0;
assign LCD_R = x<= (hbp + hpulse + 80)? 5'd16 :
(x<= (hbp + hpulse + 160)? 5'd31 : 5'd0);
assign LCD_G = (x>= (hbp + hpulse + 160) && x<= (hbp + hpulse + 240))? 6'd32 :
((x>= (hbp + hpulse + 240) && x<= (hbp + hpulse + 320))? 6'd63 : 6'd0);
assign LCD_B = (x>= (hbp + hpulse + 320) && x<= (hbp + hpulse + 400))? 5'd16 :
((x>= (hbp + hpulse + 400) && x<= (hbp + hpulse + 480))? 5'd31 : 6'd0);
/*
assign LCD_R = (x< (hbp + hpulse + 80))? 5'd0 :
(x< (hbp + hpulse + 160)? 5'd6 :
(x< (hbp + hpulse + 240)? 5'd12 :
(x< (hbp + hpulse + 320)? 5'd18 :
(x< (hbp + hpulse + 400)? 5'd24 :
(x< (hbp + hpulse + 480)? 5'd31 : 5'd0 )))));
assign LCD_G = 6'b000000;
assign LCD_B = 5'b00000;
*/
endmodule |
module maxpooling
(
input clk,
input rstn,
input ivalid, // 输入有效
input state, // 0: 24*24; 1: 8*8
input [7:0] din, // 像素数据 8bit
output ovalid, // 输出有效
output [7:0] dout // 输出结果
);
reg [7:0] data [0:23]; // 缓存一行输入数据 24 or 8
reg [6:0] ptr; // 地址指针 0 ~ 47
reg cnt; // 由于只有 1 bit，所以超过会溢出， 0：data_reg_0，1：data_reg_1
reg [7:0] data_reg_0; // 缓存寄存器0
reg [7:0] data_reg_1; // 缓存寄存器1
reg [7:0] dout_r; // 最终输出结果
// ptr 地址指针递增
always@(posedge clk)begin
if(!rstn)
ptr <= 7'b0000000;
else
case(state)
1'b0:begin
if(ptr == 7'd48-1) // 2*24 两行，从0算起，所以需要减1
ptr <= 7'd0;
else
if(!ivalid)
ptr <= ptr;
else
ptr <= ptr + 7'd1;
end
1'b1:begin
if(ptr == 7'd16-1) // 2*8 两行
ptr <= 7'd0;
else
if(!ivalid)
ptr <= ptr;
else
ptr <= ptr + 7'd1;
end
endcase
end
// cnt 计数
// 24 -> cnt=0 、25 -> cnt=1
// 26 -> cnt=0 、27 -> cnt=1
// ...
always@(posedge clk or negedge rstn)begin
if(!rstn)
cnt <= 0;
else
case(state)
1'b0:begin
if(ptr < 7'd25 - 1) //慢一拍
cnt <= 0;
else
if(ivalid)
cnt <= cnt + 1'b1;
else
cnt <= cnt;
end
1'b1:begin
if(ptr <= 7'd7)
cnt <= 0;
else
if(ivalid)
cnt <= cnt + 1'b1;
else
cnt <= cnt;
end
endcase
end
// 行数据缓存
always@(posedge clk)
begin
case(state)
1'b0:begin
if(ptr <= 7'd24 && ivalid)
data[ptr] <= din;
end
1'b1:begin
if(ptr <= 7'd8 && ivalid)
data[ptr] <= din;
end
endcase
end
// 两行对应索引数据对比，缓存较大值
always@(posedge clk)
begin
case({state,cnt}) // 这里的 cnt是触发时的值，而不是计算后的值
2'b00:begin
if(ptr >= 7'd24)
begin
if(din>data[ptr-7'd24])
data_reg_0 <= din;
else
data_reg_0 <= data[ptr-7'd24];
end
else
data_reg_0 <= 0;
end
2'b01:begin
if(ptr >= 7'd24)
begin
if(din>data[ptr-7'd24])
data_reg_1 <= din;
else
data_reg_1 <= data[ptr-7'd24];
end
else
data_reg_1 <= 0;
end
2'b10:begin
if(ptr >= 7'd9)
begin
if(din>data[ptr-7'd9])
data_reg_0 <= din;
else
data_reg_0 <= data[ptr-7'd9];
end
else
data_reg_0 <= 0;
end
2'b11:begin
if(ptr >= 7'd9)
begin
if(din>data[ptr-7'd9])
data_reg_1 <= din;
else
data_reg_1 <= data[ptr-7'd9];
end
else
data_reg_1 <= 0;
end
default:begin
data_reg_1 <= 0;
data_reg_0 <= 0;
end
endcase
end
// 打拍采沿
reg cnt_d;
always@(posedge clk)begin
if(!rstn)
cnt_d <= 0;
else
cnt_d <= cnt;
end
// cnt 为 1时，输出才是有效的，即 2*2 的kernel， cnt=1含义为第二行且为偶数位索引（从1计数）
// 筛选输出数据
assign ovalid = ~cnt && cnt_d; // 采样下降沿
assign dout = data_reg_1 > data_reg_0 ? data_reg_1 : data_reg_0;
endmodule |
module cnn_tb;
reg clk;
reg rstn;
reg start_cnn;
reg image_0_tvalid; // 图像
reg [7:0] image_0_tdata;
wire image_0_tready;
reg weight_0_tvalid; // 卷积模块权重
reg [7:0] weight_0_tdata;
wire weight_0_tready;
reg weightfc_0_tvalid; // 全连接模块权重
reg [7:0] weightfc_0_tdata;
wire weightfc_0_tready;
wire cnn_done;
wire result_0_tvalid;
wire [31:0] result_0_tdata;
wire [3:0] conv_cnt;
//========================================
//变量声明
integer i;
integer fp_w,fp_wfc,fp_i,fp_all,handle;
integer count_w,count_wfc,count_i,count_img;
reg [7:0] result [0:2];
reg [3:0] cnt_image;
reg[10:0] cnt_line_img; // 图片数据读取行数计数
reg[10:0] cnt_line_w; // 卷积模块权重读取行数计数
reg[10:0] cnt_line_fcw; // 全连接模块权重读取行数计数
CNN cnn_acc(
.clk(clk),
.rstn(rstn),
.start_cnn(start_cnn),
.image_tvalid(image_0_tvalid),
.image_tdata(image_0_tdata),
.image_tready(image_0_tready),
.weight_tvalid(weight_0_tvalid),
.weight_tdata(weight_0_tdata),
.weight_tready(weight_0_tready),
.weightfc_tvalid(weightfc_0_tvalid),
.weightfc_tdata(weightfc_0_tdata),
.weightfc_tready(weightfc_0_tready),
.cnn_done(cnn_done),
.result_tdata(result_0_tdata),
.result_tvalid(result_0_tvalid),
.conv_cnt(conv_cnt)
);
//===========================================
// 初始赋值
initial
begin
clk = 0;
rstn = 0;
start_cnn = 0;
image_0_tvalid = 0;
weight_0_tvalid = 0;
weightfc_0_tvalid = 0;
image_0_tdata = 8'hff;
weight_0_tdata = 8'hff;
weightfc_0_tdata = 8'hff;
// 读取行数计数清零
cnt_line_img = 0;
cnt_line_fcw = 0;
cnt_line_w = 0;
#40;
rstn = 1;
image_0_tvalid = 1;
weight_0_tvalid = 1;
weightfc_0_tvalid = 1;
#40000;
start_cnn = 1;
end
initial
begin
# 120000;
$finish;
end
//===================================================================
// 权重和图像数据加载
// 文件句柄
initial
begin
fp_w = $fopen("C:/Users/Administrator/Desktop/pic/cnn_test/cw.txt","r"); // 卷积模块权重
fp_wfc = $fopen("C:/Users/Administrator/Desktop/pic/cnn_test/fcw.txt","r"); // 全连接模块权重
fp_i = $fopen("C:/Users/Administrator/Desktop/pic/cnn_test/0.txt","r"); // 数字 0
//fp_all = $fopen("C:/Users/Administrator/Desktop/pic/cnn_test/images_bin.txt","r"); // 所有测试数据
end
// 读取图像数据,给滑窗模块
// 28x28x20 = 15680 ns = 15.68 ms
always@(posedge clk)
begin
if(image_0_tvalid && image_0_tready) // 当滑窗模块开始读取数据时，才输入数据，否则数据错位
begin
count_img = $fscanf(fp_i,"%b" ,image_0_tdata);
cnt_line_img <= cnt_line_img + 1;
if(cnt_line_img == 11'd784) $display("picture read over");
// $display("%d,%b",count_img,image_in);
end
end
// 加载卷积模块权重
always@(posedge clk)
begin
if(weight_0_tvalid && weight_0_tready)
begin
count_w = $fscanf(fp_w,"%d" ,weight_0_tdata);// 以十进制读取
cnt_line_w <= cnt_line_w + 1;
// if(cnt_line_w == 11'd784) $display("weight of conv module read over");
// $display("%d,%b",count_img,image_in);
end
end
// 加载全连接模块权重
always@(posedge clk)
begin
if(weightfc_0_tvalid && weightfc_0_tready)
begin
count_wfc = $fscanf(fp_wfc,"%d" ,weightfc_0_tdata);
cnt_line_fcw <= cnt_line_fcw + 1;
end
end
// 结果输出
always@(posedge clk)
begin
if(result_0_tvalid)
begin
//$fwrite(handle,"%d\n",$signed(result_tdata));
$display("%d", result_0_tdata);
end
end
/*
always@(posedge clk or negedge rstn)
begin
if(!rstn)
cnt_image <= 0;
else if(cnn_done)
begin
start_cnn <= 0;
cnt_image <= cnt_image + 1;
end
end
*/
// reg [13:0] cnt;
// reg [4:0] cnt0;
// reg cnn_done_ff_0;
// reg cnn_done_ff_1;
/*
always@(posedge clk or negedge rstn)
if(!rstn)
cnt0 <= 0;
else
if(cnt0 == 4'd12)
cnt0 <= cnt0;
else if(weight_0_tvalid)
cnt0 <= cnt0 + 1'b1;
else
cnt0 <= 0;
always@(posedge clk)
if(cnn_done)
start_cnn <= 0;
else if(cnt == 14'd10000)
start_cnn <= 0;
else
if(cnt0 == 14'd2000 || cnn_done_ff_1)
start_cnn <= 1;
*/
// always@(posedge clk or negedge rstn)
// if(!rstn)
// cnt <= 14'd0;
// else
// if(cnn_done)
// cnt <= cnt + 1'b1;
// else
// cnt <= cnt;
//
// // 打两拍
// always@(posedge clk)
// begin
// cnn_done_ff_0 <= cnn_done;
// cnn_done_ff_1 <= cnn_done_ff_0;
// end
//
// always@(posedge clk)
// begin
// if(cnt == 14'd10000)
// begin
// $fclose(handle);
// end
// end
always #10 clk = ~clk ;
endmodule |
module maxpooling_tb();
// 输入
reg clk;
reg rstn;
reg ivalid;
reg state;
reg [7:0] din;
// 输出
wire[7:0] dout;
wire ovalid;
integer STATE = 0; // 输入图像 Size 配置 0: 24x24 1:8x8
reg[10:0] cnt_line; // 读取行数计数
integer count_w,fp_i;// 文件指针
reg [7:0] pool_result_tb [0:150]; //用于缓存池化计算结果 12x12=144
reg [10:0] cnt_pool; // 缓存的卷积计算结果计数
// maxpooling module
maxpooling u_maxpooling(
.clk(clk),
.rstn(rstn),
.ivalid(ivalid),
.state(state),
.din(din),
.dout(dout),
.ovalid(ovalid)
);
// 初始信号赋值-maxpooling module
initial
begin
clk = 0;
rstn = 0; // 复位
cnt_line = 0; //行数清零
cnt_pool = 0; //计数清零
state = STATE;
ivalid = 0;
din = 0;
# 20; // 一周期后填充数据，即 ivalid = 1前数据就要准备好
rstn = 1;
ivalid = 1; // input valid
end
// 读取图片数据
initial
begin
fp_i = $fopen("C:/Users/Administrator/Desktop/pic/24/0.txt","r"); // 数字 0 (1)输入数据路径
end
// 读取图像数据，一共 576 行，即 576*20 = 11520 ns = 11.52 ms 读完一张24x24图片
// 也是池化模块的计算速度
always@(posedge clk)
begin
if(ivalid == 1)// 当输入有效标志拉高时读取数据时，数据要准备好，否则数据会错位，
begin
count_w <= $fscanf(fp_i,"%b" ,din);
cnt_line <= cnt_line + 1;
if(cnt_line == 10'd576) $display("picture read over");
// $display("%d,%b",count_w,image_in);
end
end
// 时钟信号 50MHz
always #10 clk <= ~clk;
//=======================最大池化计算结果打印=======================
integer i;
integer display_line = 0;
always@(posedge clk)// 缓存有效卷积结果
begin
if(ovalid && cnt_pool<144)
begin
//$display("cnt_pool: %d ", cnt_pool); // 先输出计数，表示缓存到该地址
// 输入:24*24 -> 输出 12x12=144
// 输入:8*8 -> 输出 4x4=16
pool_result_tb[cnt_pool] = dout;
cnt_pool = cnt_pool + 1;
end
end
// 以12x12二维矩阵形式打印卷积结果
initial
begin
# (11540+20); // 等待池化完成
$display("maxpooling complete");
if(state == 0)
begin
for(i=0;i<144;i=i+1)
begin
if(i == 0) $write("%d :", display_line);
$write("%d ", pool_result_tb[i]); // $write 不会自动换行
//$write("i:%d %d ", i,pool_result_tb[i]); // $write 不会自动换行
if((i+1)%12 == 0)// 添加行号并换行,每行 12 个数据
begin
$display(" ");
display_line = display_line + 1;
$write("%d :", display_line);
end
end
end
else if(state == 1)
begin
for(i=0;i<16;i=i+1)
begin
$display("%d", pool_result_tb[i]);
end
end
$finish; // 打印完结果后完成仿真
end
endmodule |
module window_tb();
// 输入
reg clk;
reg resetn;
reg start_window;
reg state;
reg[7:0] image_in;
// 输出
wire[39:0] taps;
// 文件指针
integer fp_i;
integer count_w;
// 读取行数计数
reg[10:0] cnt_line;
// 滑窗模块
window window_inst(
.clk (clk),
.rstn (resetn),
.start(start_window),
.state(state),
.din (image_in),
.taps (taps)
);
// 读取图片数据
initial
begin
fp_i = $fopen("C:/Users/Administrator/Desktop/pic/1/num3_0.txt","r"); // 数字 3
end
// 初始信号
initial
begin
cnt_line = 0;// 读取行数清零
clk = 0;
start_window = 0;
state = 0;
# 20;
start_window = 1;
end
// 读取图像数据，一共 784 行，即 784*20 + 20 = 15700 ns = 15.7 ms 读完一张28*28图片
always@(posedge clk)
begin
begin
count_w <= $fscanf(fp_i,"%b" ,image_in);
cnt_line <= cnt_line + 1;
if(cnt_line == 11'd784) $display("picture read over");
// $display("%d,%b",count_w,image_in);
end
end
// 时钟信号 50MHz
always #10 clk <= ~clk;
endmodule |
module fc_tb();
// 输入
reg clk;
reg rstn;
reg ivalid;
reg signed [7:0] din_0;
reg signed [7:0] din_1;
reg signed [7:0] din_2;
reg signed [7:0] din_3;
reg signed [7:0] din_4;
reg signed [7:0] din_5;
reg signed [7:0] weight;
reg weight_en;
// 输出
wire ovalid;
wire signed [31:0]dout;
reg[10:0] cnt_line; // 读取行数计数
integer count_w,fp_i;// 文件指针
integer i_fc;// 循环计数变量
reg signed[31:0] fc_result_tb ; //用于缓存全连接计算结果
reg [10:0] cnt_fc; // 缓存的全连接模块计算结果计数
// fullconnect module
fc u_fc(
.clk(clk),
.rstn(rstn),
.ivalid(ivalid),
.din_0(din_0),
.din_1(din_1),
.din_2(din_2),
.din_3(din_3),
.din_4(din_4),
.din_5(din_5),
.weight(weight),
.weight_en(weight_en),
.ovalid(ovalid),
.dout(dout)
);
// 初始信号赋值-fullconnect module
initial
begin
clk = 0;
rstn = 0; // 复位
cnt_line = 0; //行数清零
cnt_fc = 0; //计数清零
ivalid = 0;
din_0 = 0;
din_1 = 0;
din_2 = 0;
din_3 = 0;
din_4 = 0;
din_5 = 0;
weight_en = 0;
weight = 0;
# 20; // 一周期后填充权重数据，共需要192个时钟周期，192x20
rstn = 1;
weight_en = 1;
weight = 1; // 这里权重全为1
# (192*20);// 开始填充数据
// 全连接模块的输入有效信号不能一直为1
for(i_fc=0;i_fc<32;i_fc=i_fc+1)
begin
ivalid = 1; // input valid
#20;
ivalid = 0;
#20;
end
end
// 读取图片数据
initial
begin
fp_i = $fopen("C:/Users/Administrator/Desktop/pic/16x12/0.txt","r"); // 数字 0 (1)输入数据路径
end
// 读取图像数据，一共 192 行，即 (192/6)*20 = 640 ns = 0.64 ns 读完6x4x4图片
// 也是全连接模块的计算速度
always@(posedge clk)
begin
if(ivalid == 1)// 当输入有效标志拉高时读取数据时，数据要准备好，否则数据会错位，
begin
count_w <= $fscanf(fp_i,"%b" ,din_0); // 一次读取6个数据
count_w <= $fscanf(fp_i,"%b" ,din_1);
count_w <= $fscanf(fp_i,"%b" ,din_2);
count_w <= $fscanf(fp_i,"%b" ,din_3);
count_w <= $fscanf(fp_i,"%b" ,din_4);
count_w <= $fscanf(fp_i,"%b" ,din_5);
cnt_line <= cnt_line + 6;
if(cnt_line == 9'd192) $display("picture read over");
// $display("%d,%b",count_w,image_in);
end
end
// 时钟信号 50MHz
always #10 clk <= ~clk;
//=======================全连接模块计算结果打印=======================
integer i;
integer display_line = 0;
always@(posedge clk)// 缓存有效计算结果
begin
if(ovalid)
begin
$display("cnt_fc: %d ", cnt_fc); // 先输出计数，表示缓存到该地址
fc_result_tb[cnt_fc] = dout;
$display("fc_result_tb: %d ", dout);
cnt_fc = cnt_fc + 1;
end
end
// 仿真
initial
begin
# (20+192*20+32*40+5*20); // 等待全连接模块计算完成
$finish; // 打印完结果后完成仿真
end
endmodule |
module conv_tb();
// 输入
reg clk;
reg rstn;
reg start_conv;
reg weight_en;
reg [7:0] weight_c;
reg state;
reg start_window;
reg [7:0] image_in;
// 输出
wire[31:0]conv_result;
wire conv_ovalid;
wire conv_done;
wire [39:0] taps;
parameter cycle = 20; // 时钟周期
// 文件指针
integer fp_i;
integer count_w;
// 输入图像 Size 配置
integer STATE = 0; // 0: 28x28 1:12x12
// 读取行数计数
reg[10:0] cnt_line;
//用于卷积计算结果
reg [31:0] conv_result_r [0:599];
reg [10:0] cnt_conv; // 缓存的卷积计算结果计数
// 滑窗模块
window window_inst(
.clk (clk),
.rstn (rstn),
.start(start_window),
.state(state),
.din (image_in),
.taps (taps)
);
// 卷积模块
conv u_conv(
.clk(clk),
.rstn(rstn),
.start(start_conv),
.weight_en(weight_en),
.weight(weight_c),
.taps(taps),
.state(state),
.dout(conv_result),
.ovalid(conv_ovalid),
.done(conv_done)
);
// 初始信号-卷积模块
initial
begin
clk = 0;
rstn = 0; // 复位
state = STATE;
cnt_conv = 0; // 计数清零
# 20;
rstn = 1;
start_conv = 1;
weight_en = 1;
weight_c = 8'd2;
end
// 初始信号-滑窗模块
initial
begin
cnt_line = 0;// 读取行数清零
start_window = 0;
# (20 + 10*cycle);// 比 start_conv 晚10个时钟周期，用于同步权重矩阵与图像数据加载
start_window = 1;
end
// 读取图片数据
initial
begin
fp_i = $fopen("C:/Users/Administrator/Desktop/pic/1/num3_0.txt","r"); // 数字 3
end
// 读取图像数据，一共 784 行，即 784*20 + 20 = 15700 ns = 15.7 ms 读完一张28*28图片
always@(posedge clk)
begin
if(start_window == 1)// 当滑窗模块开始读取数据时，才输入数据，否则数据错位
begin
count_w <= $fscanf(fp_i,"%b" ,image_in);
cnt_line <= cnt_line + 1;
if(cnt_line == 11'd784) $display("picture read over");
// $display("%d,%b",count_w,image_in);
end
end
// 缓存卷积结果到数组（位宽32）并输出log
integer i;
integer display_line = 0;
// 缓存有效卷积结果
always@(posedge clk)
begin
if(conv_ovalid && !conv_done)
begin
//$display("cnt_conv: %d ", cnt_conv); // 先输出计数，表示缓存到该地址
// 输入:28*28 -> 输出 24x24=576
// 输入:12*12 -> 输出 8x8=64
conv_result_r[cnt_conv] = conv_result;
cnt_conv = cnt_conv + 1;
end
else
begin
if(conv_done)
begin
conv_result_r[cnt_conv] = conv_result; // 最后一个结果，conv_ovalid 和 conv_done均为 1
//$display("cnt_conv: %d ", cnt_conv);
$display("conv complete");
if(state == 0)
begin
for(i=0;i<576;i=i+1)
begin
if(i == 0) $write("%d :", display_line);
$write("%d ", conv_result_r[i]); // $write 不会自动换行
if((i+1)%24 == 0)// 添加行号并换行
begin
$display(" "); // 每行 24 个数据
display_line = display_line + 1;
$write("%d :", display_line);
end
end
end
else if(state == 1)
begin
for(i=0;i<64;i=i+1)
begin
$display("%d", conv_result_r[i]);
end
end
end
end
end
// 时钟信号 50MHz
always #10 clk <= ~clk;
//=================================================================================
//===============================输出BMP格式的图片=================================
// 这里输出 24x24
// 打开示例 bmp 图片获取文件头
integer iIndex = 0; //输出BMP数据索引 ，0-53：文件头和信息头 54之后：像素数据
integer iBmpWidth; //输入BMP 宽度 ,即24
integer iBmpHight; //输入BMP 高度，即24
integer iBmpSize; //输入BMP字节数 54+24*24*3
integer iDataStartIndex; //输入BMP 像素数据偏移量
integer iBmpFileId; //输入BMP图片
integer iCode;
integer oBmpFileId_1; // 输出BMP图片
reg [7:0] rBmpData [0:2000]; // 缓存图片数据
// 用于卷积计算之后的BMP图片数据
reg [7:0] conv_pixel_data_1 [0:2000];
// 最终写入文件的处理后的BMP图片数据
reg [7:0] conv_BmpData_1 [0:2000];
initial
begin
// 打开输入BMP图片
iBmpFileId = $fopen("C:/Users/Administrator/Desktop/pic/bmp/3.bmp","rb");
iCode = $fread(rBmpData, iBmpFileId); //将输入BMP图片加载到数组中
//根据BMP图片文件头的格式，分别计算出图片的宽度/高度/像素数据偏移量/图片字节数
iBmpWidth = {rBmpData[21], rBmpData[20], rBmpData[19], rBmpData[18]};
iBmpHight = {rBmpData[25], rBmpData[24], rBmpData[23], rBmpData[22]};
iBmpSize = {rBmpData[ 5], rBmpData[ 4], rBmpData[ 3], rBmpData[ 2]};
iDataStartIndex = {rBmpData[13], rBmpData[12], rBmpData[11], rBmpData[10]};
$fclose(iBmpFileId);
// 打开输出BMP图片
oBmpFileId_1 = $fopen("C:/Users/Administrator/Desktop/pic/sim/test.bmp","wb+");
//延迟，等待卷积计算完成
#16700;
//输出处理后的图片
for(iIndex = 0; iIndex < iBmpSize; iIndex = iIndex + 1) begin
if(iIndex < 54)
conv_BmpData_1[iIndex] = rBmpData[iIndex]; //文件头和信息头和原BMP图片保持一致，只修改像素数据对应字节
else
conv_BmpData_1[iIndex] = conv_pixel_data_1[iIndex-54]; //写入像素数据
end
//将数组中的数据写到输出BMP图片中
for (iIndex = 0; iIndex < iBmpSize; iIndex = iIndex + 1) begin
$fwrite(oBmpFileId_1, "%c" , conv_BmpData_1[iIndex]); //以ASCII写入
end
//关闭输出BMP图片
$fclose(oBmpFileId_1);
end
// 写入像素数据到缓存数组中
// Y ——》 RGB（YYY）
integer k;
always@(posedge clk)
begin
if(cnt_conv == 575) begin
for(k=0;k<576;k=k+1)
begin
//每次写一个像素数据，即3个字节，所以索引乘3
conv_pixel_data_1[k*3] <= conv_result_r[k]; //将图像算法处理后的像素数据写入到对应数组中
conv_pixel_data_1[k*3+1] <= conv_result_r[k];
conv_pixel_data_1[k*3+2] <= conv_result_r[k];
end
end
end
endmodule |
module window
(
input clk,
input rstn,
input start, // 开始标志
input state,
input [7:0] din,
output [39:0] taps // 一列数据
);
integer i;
reg [7:0] mem [0:139];
// 串行存储140（28*5）个输入数据
always@(posedge clk)begin
if(start)
begin
mem[0] <= din;
for(i=0;i<139;i=i+1)
mem[i+1] <= mem[i];
end
end
// state=0:28*28 state=1:12*12
assign taps = (!state)?{mem[139],mem[111],mem[83],mem[55],mem[27]}:{mem[59],mem[47],mem[35],mem[23],mem[11]};
endmodule |
module fc
(
input clk,
input rstn,
input ivalid,
input signed [7:0] din_0,
input signed [7:0] din_1,
input signed [7:0] din_2,
input signed [7:0] din_3,
input signed [7:0] din_4,
input signed [7:0] din_5,
input signed [7:0] weight,
input weight_en, // 权重读取使能
output ovalid,
output signed [31:0] dout
);
reg [7:0] weight_addr;
reg signed [7:0] w [0:191];
reg [4:0] cnt;
reg [4:0] cnt0;
reg sum_valid;
reg wren;
reg signed [15:0] p0,p1,p2,p3,p4,p5;
reg signed [16:0] sum00,sum01,sum02;
reg signed [17:0] sum10,sum11;
reg signed [18:0] sum;
reg signed [22:0] dout_r;
reg ivalid_ff_0,ivalid_ff_1,ivalid_ff_2,ivalid_ff_3;
//??
always@(posedge clk)
begin
if(!rstn)
dout_r <= 0;
else if(wren)
dout_r <= 0;
else if(ivalid_ff_3)
dout_r <= dout_r + sum; // 累加求最终总和
else
dout_r <= dout_r;
end
// 打拍采沿
always@(posedge clk)
begin
ivalid_ff_0 <= ivalid;
ivalid_ff_1 <= ivalid_ff_0;
ivalid_ff_2 <= ivalid_ff_1;
ivalid_ff_3 <= ivalid_ff_2;
end
always@(posedge clk)
begin
if(ivalid_ff_2 && ~ivalid_ff_1)// 采样下降沿
sum_valid <= 1; // 即读一次输入数据，计算一次
else
sum_valid <= 0;
end
always@(posedge clk or negedge rstn)
begin
if(!rstn)
cnt0 <= 0;
else
begin
if(wren || cnt0 == 5'd16)
cnt0 <= 0;
else
if(sum_valid)// 输入来一次相乘累加一次
cnt0 <= cnt0 + 1;
else
cnt0 <= cnt0;
end
end
// 输出使能，cnt到16表示计算结束
always@(posedge clk)
begin
if(cnt0 == 5'd16)
wren <= 1;
else
wren <= 0;
end
//fullconnect 计算计数，cnt:0~15
always@(posedge clk)
begin
if(!rstn)
cnt <=0;
else
if(cnt == 5'd16 || wren)
cnt <= 0;
else
if(ivalid_ff_0)
cnt <= cnt + 1;
else
cnt <= cnt;
end
// 权重地址每时钟周期递增+1
always@(posedge clk)
begin
if(!rstn)
weight_addr <= 8'd0;
else begin
if(weight_addr == 8'd192)
weight_addr <= weight_addr;
else
if(weight_en)
weight_addr <= weight_addr + 1;
else
weight_addr <= weight_addr;
end
end
// 权重读取，共192
always@(posedge clk)
begin
case(weight_addr)
8'd0:w[0]<=weight;
8'd1:w[1]<=weight;
8'd2:w[2]<=weight;
8'd3:w[3]<=weight;
8'd4:w[4]<=weight;
8'd5:w[5]<=weight;
8'd6:w[6]<=weight;
8'd7:w[7]<=weight;
8'd8:w[8]<=weight;
8'd9:w[9]<=weight;
8'd10:w[10]<=weight;
8'd11:w[11]<=weight;
8'd12:w[12]<=weight;
8'd13:w[13]<=weight;
8'd14:w[14]<=weight;
8'd15:w[15]<=weight;
8'd16:w[16]<=weight;
8'd17:w[17]<=weight;
8'd18:w[18]<=weight;
8'd19:w[19]<=weight;
8'd20:w[20]<=weight;
8'd21:w[21]<=weight;
8'd22:w[22]<=weight;
8'd23:w[23]<=weight;
8'd24:w[24]<=weight;
8'd25:w[25]<=weight;
8'd26:w[26]<=weight;
8'd27:w[27]<=weight;
8'd28:w[28]<=weight;
8'd29:w[29]<=weight;
8'd30:w[30]<=weight;
8'd31:w[31]<=weight;
8'd32:w[32]<=weight;
8'd33:w[33]<=weight;
8'd34:w[34]<=weight;
8'd35:w[35]<=weight;
8'd36:w[36]<=weight;
8'd37:w[37]<=weight;
8'd38:w[38]<=weight;
8'd39:w[39]<=weight;
8'd40:w[40]<=weight;
8'd41:w[41]<=weight;
8'd42:w[42]<=weight;
8'd43:w[43]<=weight;
8'd44:w[44]<=weight;
8'd45:w[45]<=weight;
8'd46:w[46]<=weight;
8'd47:w[47]<=weight;
8'd48:w[48]<=weight;
8'd49:w[49]<=weight;
8'd50:w[50]<=weight;
8'd51:w[51]<=weight;
8'd52:w[52]<=weight;
8'd53:w[53]<=weight;
8'd54:w[54]<=weight;
8'd55:w[55]<=weight;
8'd56:w[56]<=weight;
8'd57:w[57]<=weight;
8'd58:w[58]<=weight;
8'd59:w[59]<=weight;
8'd60:w[60]<=weight;
8'd61:w[61]<=weight;
8'd62:w[62]<=weight;
8'd63:w[63]<=weight;
8'd64:w[64]<=weight;
8'd65:w[65]<=weight;
8'd66:w[66]<=weight;
8'd67:w[67]<=weight;
8'd68:w[68]<=weight;
8'd69:w[69]<=weight;
8'd70:w[70]<=weight;
8'd71:w[71]<=weight;
8'd72:w[72]<=weight;
8'd73:w[73]<=weight;
8'd74:w[74]<=weight;
8'd75:w[75]<=weight;
8'd76:w[76]<=weight;
8'd77:w[77]<=weight;
8'd78:w[78]<=weight;
8'd79:w[79]<=weight;
8'd80:w[80]<=weight;
8'd81:w[81]<=weight;
8'd82:w[82]<=weight;
8'd83:w[83]<=weight;
8'd84:w[84]<=weight;
8'd85:w[85]<=weight;
8'd86:w[86]<=weight;
8'd87:w[87]<=weight;
8'd88:w[88]<=weight;
8'd89:w[89]<=weight;
8'd90:w[90]<=weight;
8'd91:w[91]<=weight;
8'd92:w[92]<=weight;
8'd93:w[93]<=weight;
8'd94:w[94]<=weight;
8'd95:w[95]<=weight;
8'd96:w[96]<=weight;
8'd97:w[97]<=weight;
8'd98:w[98]<=weight;
8'd99:w[99]<=weight;
8'd100:w[100]<=weight;
8'd101:w[101]<=weight;
8'd102:w[102]<=weight;
8'd103:w[103]<=weight;
8'd104:w[104]<=weight;
8'd105:w[105]<=weight;
8'd106:w[106]<=weight;
8'd107:w[107]<=weight;
8'd108:w[108]<=weight;
8'd109:w[109]<=weight;
8'd110:w[110]<=weight;
8'd111:w[111]<=weight;
8'd112:w[112]<=weight;
8'd113:w[113]<=weight;
8'd114:w[114]<=weight;
8'd115:w[115]<=weight;
8'd116:w[116]<=weight;
8'd117:w[117]<=weight;
8'd118:w[118]<=weight;
8'd119:w[119]<=weight;
8'd120:w[120]<=weight;
8'd121:w[121]<=weight;
8'd122:w[122]<=weight;
8'd123:w[123]<=weight;
8'd124:w[124]<=weight;
8'd125:w[125]<=weight;
8'd126:w[126]<=weight;
8'd127:w[127]<=weight;
8'd128:w[128]<=weight;
8'd129:w[129]<=weight;
8'd130:w[130]<=weight;
8'd131:w[131]<=weight;
8'd132:w[132]<=weight;
8'd133:w[133]<=weight;
8'd134:w[134]<=weight;
8'd135:w[135]<=weight;
8'd136:w[136]<=weight;
8'd137:w[137]<=weight;
8'd138:w[138]<=weight;
8'd139:w[139]<=weight;
8'd140:w[140]<=weight;
8'd141:w[141]<=weight;
8'd142:w[142]<=weight;
8'd143:w[143]<=weight;
8'd144:w[144]<=weight;
8'd145:w[145]<=weight;
8'd146:w[146]<=weight;
8'd147:w[147]<=weight;
8'd148:w[148]<=weight;
8'd149:w[149]<=weight;
8'd150:w[150]<=weight;
8'd151:w[151]<=weight;
8'd152:w[152]<=weight;
8'd153:w[153]<=weight;
8'd154:w[154]<=weight;
8'd155:w[155]<=weight;
8'd156:w[156]<=weight;
8'd157:w[157]<=weight;
8'd158:w[158]<=weight;
8'd159:w[159]<=weight;
8'd160:w[160]<=weight;
8'd161:w[161]<=weight;
8'd162:w[162]<=weight;
8'd163:w[163]<=weight;
8'd164:w[164]<=weight;
8'd165:w[165]<=weight;
8'd166:w[166]<=weight;
8'd167:w[167]<=weight;
8'd168:w[168]<=weight;
8'd169:w[169]<=weight;
8'd170:w[170]<=weight;
8'd171:w[171]<=weight;
8'd172:w[172]<=weight;
8'd173:w[173]<=weight;
8'd174:w[174]<=weight;
8'd175:w[175]<=weight;
8'd176:w[176]<=weight;
8'd177:w[177]<=weight;
8'd178:w[178]<=weight;
8'd179:w[179]<=weight;
8'd180:w[180]<=weight;
8'd181:w[181]<=weight;
8'd182:w[182]<=weight;
8'd183:w[183]<=weight;
8'd184:w[184]<=weight;
8'd185:w[185]<=weight;
8'd186:w[186]<=weight;
8'd187:w[187]<=weight;
8'd188:w[188]<=weight;
8'd189:w[189]<=weight;
8'd190:w[190]<=weight;
8'd191:w[191]<=weight;
default:;
endcase
end
//state: 0:0-96, 1: 97-191
reg state;
always@(posedge clk or negedge rstn)
begin
if(!rstn)
state <= 0;
else
if(wren)
state <= state + 1;
end
//???
/*
always@(posedge clk)
begin
case({state,cnt[3:0]})
5'b00000:begin
p0 <= w[0]*din_0;
p1 <= w[16]*din_1;
p2 <= w[32]*din_2;
p3 <= w[48]*din_3;
p4 <= w[64]*din_4;
p5 <= w[80]*din_5;
end
5'b00001:begin
p0 <= w[1]*din_0;
p1 <= w[17]*din_1;
p2 <= w[33]*din_2;
p3 <= w[49]*din_3;
p4 <= w[65]*din_4;
p5 <= w[81]*din_5;
end
5'b00010:begin
p0 <= w[2]*din_0;
p1 <= w[18]*din_1;
p2 <= w[34]*din_2;
p3 <= w[50]*din_3;
p4 <= w[66]*din_4;
p5 <= w[82]*din_5;
end
5'b00011:begin
p0 <= w[3]*din_0;
p1 <= w[19]*din_1;
p2 <= w[35]*din_2;
p3 <= w[51]*din_3;
p4 <= w[67]*din_4;
p5 <= w[83]*din_5;
end
5'b00100:begin
p0 <= w[4]*din_0;
p1 <= w[20]*din_1;
p2 <= w[36]*din_2;
p3 <= w[52]*din_3;
p4 <= w[68]*din_4;
p5 <= w[84]*din_5;
end
5'b00101:begin
p0 <= w[5]*din_0;
p1 <= w[21]*din_1;
p2 <= w[37]*din_2;
p3 <= w[53]*din_3;
p4 <= w[69]*din_4;
p5 <= w[85]*din_5;
end
5'b00110:begin
p0 <= w[6]*din_0;
p1 <= w[22]*din_1;
p2 <= w[38]*din_2;
p3 <= w[54]*din_3;
p4 <= w[70]*din_4;
p5 <= w[86]*din_5;
end
5'b00111:begin
p0 <= w[7]*din_0;
p1 <= w[23]*din_1;
p2 <= w[39]*din_2;
p3 <= w[55]*din_3;
p4 <= w[71]*din_4;
p5 <= w[87]*din_5;
end
5'b01000:begin
p0 <= w[8]*din_0;
p1 <= w[24]*din_1;
p2 <= w[40]*din_2;
p3 <= w[56]*din_3;
p4 <= w[72]*din_4;
p5 <= w[88]*din_5;
end
5'b01001:begin
p0 <= w[9]*din_0;
p1 <= w[25]*din_1;
p2 <= w[41]*din_2;
p3 <= w[57]*din_3;
p4 <= w[73]*din_4;
p5 <= w[89]*din_5;
end
5'b01010:begin
p0 <= w[10]*din_0;
p1 <= w[26]*din_1;
p2 <= w[42]*din_2;
p3 <= w[58]*din_3;
p4 <= w[74]*din_4;
p5 <= w[90]*din_5;
end
5'b01011:begin
p0 <= w[11]*din_0;
p1 <= w[27]*din_1;
p2 <= w[43]*din_2;
p3 <= w[59]*din_3;
p4 <= w[75]*din_4;
p5 <= w[91]*din_5;
end
5'b01100:begin
p0 <= w[12]*din_0;
p1 <= w[28]*din_1;
p2 <= w[44]*din_2;
p3 <= w[60]*din_3;
p4 <= w[76]*din_4;
p5 <= w[92]*din_5;
end
5'b01101:begin
p0 <= w[13]*din_0;
p1 <= w[29]*din_1;
p2 <= w[45]*din_2;
p3 <= w[61]*din_3;
p4 <= w[77]*din_4;
p5 <= w[93]*din_5;
end
5'b01110:begin
p0 <= w[14]*din_0;
p1 <= w[30]*din_1;
p2 <= w[46]*din_2;
p3 <= w[62]*din_3;
p4 <= w[78]*din_4;
p5 <= w[94]*din_5;
end
5'b01111:begin
p0 <= w[15]*din_0;
p1 <= w[31]*din_1;
p2 <= w[47]*din_2;
p3 <= w[63]*din_3;
p4 <= w[79]*din_4;
p5 <= w[95]*din_5;
end
5'b10000:begin
p0 <= w[96]*din_0;
p1 <= w[112]*din_1;
p2 <= w[128]*din_2;
p3 <= w[144]*din_3;
p4 <= w[160]*din_4;
p5 <= w[176]*din_5;
end
5'b10001:begin
p0 <= w[97]*din_0;
p1 <= w[113]*din_1;
p2 <= w[129]*din_2;
p3 <= w[145]*din_3;
p4 <= w[161]*din_4;
p5 <= w[177]*din_5;
end
5'b10010:begin
p0 <= w[98]*din_0;
p1 <= w[114]*din_1;
p2 <= w[130]*din_2;
p3 <= w[146]*din_3;
p4 <= w[162]*din_4;
p5 <= w[178]*din_5;
end
5'b10011:begin
p0 <= w[99]*din_0;
p1 <= w[115]*din_1;
p2 <= w[131]*din_2;
p3 <= w[147]*din_3;
p4 <= w[163]*din_4;
p5 <= w[179]*din_5;
end
5'b10100:begin
p0 <= w[100]*din_0;
p1 <= w[116]*din_1;
p2 <= w[132]*din_2;
p3 <= w[148]*din_3;
p4 <= w[164]*din_4;
p5 <= w[180]*din_5;
end
5'b10101:begin
p0 <= w[101]*din_0;
p1 <= w[117]*din_1;
p2 <= w[133]*din_2;
p3 <= w[149]*din_3;
p4 <= w[165]*din_4;
p5 <= w[181]*din_5;
end
5'b10110:begin
p0 <= w[102]*din_0;
p1 <= w[118]*din_1;
p2 <= w[134]*din_2;
p3 <= w[150]*din_3;
p4 <= w[166]*din_4;
p5 <= w[182]*din_5;
end
5'b10111:begin
p0 <= w[103]*din_0;
p1 <= w[119]*din_1;
p2 <= w[135]*din_2;
p3 <= w[151]*din_3;
p4 <= w[167]*din_4;
p5 <= w[183]*din_5;
end
5'b11000:begin
p0 <= w[104]*din_0;
p1 <= w[120]*din_1;
p2 <= w[136]*din_2;
p3 <= w[152]*din_3;
p4 <= w[168]*din_4;
p5 <= w[184]*din_5;
end
5'b11001:begin
p0 <= w[105]*din_0;
p1 <= w[121]*din_1;
p2 <= w[137]*din_2;
p3 <= w[153]*din_3;
p4 <= w[169]*din_4;
p5 <= w[185]*din_5;
end
5'b11010:begin
p0 <= w[106]*din_0;
p1 <= w[122]*din_1;
p2 <= w[138]*din_2;
p3 <= w[154]*din_3;
p4 <= w[170]*din_4;
p5 <= w[186]*din_5;
end
5'b11011:begin
p0 <= w[107]*din_0;
p1 <= w[123]*din_1;
p2 <= w[139]*din_2;
p3 <= w[155]*din_3;
p4 <= w[171]*din_4;
p5 <= w[187]*din_5;
end
5'b11100:begin
p0 <= w[108]*din_0;
p1 <= w[124]*din_1;
p2 <= w[140]*din_2;
p3 <= w[156]*din_3;
p4 <= w[172]*din_4;
p5 <= w[188]*din_5;
end
5'b11101:begin
p0 <= w[109]*din_0;
p1 <= w[125]*din_1;
p2 <= w[141]*din_2;
p3 <= w[157]*din_3;
p4 <= w[173]*din_4;
p5 <= w[189]*din_5;
end
5'b11110:begin
p0 <= w[110]*din_0;
p1 <= w[126]*din_1;
p2 <= w[142]*din_2;
p3 <= w[158]*din_3;
p4 <= w[174]*din_4;
p5 <= w[190]*din_5;
end
5'b11111:begin
p0 <= w[111]*din_0;
p1 <= w[127]*din_1;
p2 <= w[143]*din_2;
p3 <= w[159]*din_3;
p4 <= w[175]*din_4;
p5 <= w[191]*din_5;
end
default:begin
p0 <= 0;
p1 <= 0;
p2 <= 0;
p3 <= 0;
p4 <= 0;
p5 <= 0;
end
endcase
end
*/
// 输入与权重相乘
always@(posedge clk)
begin
case(cnt)
4'd0:begin
if(!state)
begin
p0 <= w[0] *din_0;
p1 <= w[16]*din_1;
p2 <= w[32]*din_2;
p3 <= w[48]*din_3;
p4 <= w[64]*din_4;
p5 <= w[80]*din_5;
end
else
begin
p0 <= w[96]*din_0;
p1 <= w[112]*din_1;
p2 <= w[128]*din_2;
p3 <= w[144]*din_3;
p4 <= w[160]*din_4;
p5 <= w[176]*din_5;
end
end
4'd1:begin
if(!state)
begin
p0 <= w[1]*din_0;
p1 <= w[17]*din_1;
p2 <= w[33]*din_2;
p3 <= w[49]*din_3;
p4 <= w[65]*din_4;
p5 <= w[81]*din_5;
end
else
begin
p0 <= w[97]*din_0;
p1 <= w[113]*din_1;
p2 <= w[129]*din_2;
p3 <= w[145]*din_3;
p4 <= w[161]*din_4;
p5 <= w[177]*din_5;
end
end
4'd2:begin
if(!state)
begin
p0 <= w[2]*din_0;
p1 <= w[18]*din_1;
p2 <= w[34]*din_2;
p3 <= w[50]*din_3;
p4 <= w[66]*din_4;
p5 <= w[82]*din_5;
end
else
begin
p0 <= w[98]*din_0;
p1 <= w[114]*din_1;
p2 <= w[130]*din_2;
p3 <= w[146]*din_3;
p4 <= w[162]*din_4;
p5 <= w[178]*din_5;
end
end
4'd3:begin
if(!state)
begin
p0 <= w[3]*din_0;
p1 <= w[19]*din_1;
p2 <= w[35]*din_2;
p3 <= w[51]*din_3;
p4 <= w[67]*din_4;
p5 <= w[83]*din_5;
end
else
begin
p0 <= w[99]*din_0;
p1 <= w[115]*din_1;
p2 <= w[131]*din_2;
p3 <= w[147]*din_3;
p4 <= w[163]*din_4;
p5 <= w[179]*din_5;
end
end
4'd4:begin
if(!state)
begin
p0 <= w[4]*din_0;
p1 <= w[20]*din_1;
p2 <= w[36]*din_2;
p3 <= w[52]*din_3;
p4 <= w[68]*din_4;
p5 <= w[84]*din_5;
end
else
begin
p0 <= w[100]*din_0;
p1 <= w[116]*din_1;
p2 <= w[132]*din_2;
p3 <= w[148]*din_3;
p4 <= w[164]*din_4;
p5 <= w[180]*din_5;
end
end
4'd5:begin
if(!state)
begin
p0 <= w[5]*din_0;
p1 <= w[21]*din_1;
p2 <= w[37]*din_2;
p3 <= w[53]*din_3;
p4 <= w[69]*din_4;
p5 <= w[85]*din_5;
end
else
begin
p0 <= w[101]*din_0;
p1 <= w[117]*din_1;
p2 <= w[133]*din_2;
p3 <= w[149]*din_3;
p4 <= w[165]*din_4;
p5 <= w[181]*din_5;
end
end
4'd6:begin
if(!state)
begin
p0 <= w[6]*din_0;
p1 <= w[22]*din_1;
p2 <= w[38]*din_2;
p3 <= w[54]*din_3;
p4 <= w[70]*din_4;
p5 <= w[86]*din_5;
end
else
begin
p0 <= w[102]*din_0;
p1 <= w[118]*din_1;
p2 <= w[134]*din_2;
p3 <= w[150]*din_3;
p4 <= w[166]*din_4;
p5 <= w[182]*din_5;
end
end
4'd7:begin
if(!state)
begin
p0 <= w[7]*din_0;
p1 <= w[23]*din_1;
p2 <= w[39]*din_2;
p3 <= w[55]*din_3;
p4 <= w[71]*din_4;
p5 <= w[87]*din_5;
end
else
begin
p0 <= w[103]*din_0;
p1 <= w[119]*din_1;
p2 <= w[135]*din_2;
p3 <= w[151]*din_3;
p4 <= w[167]*din_4;
p5 <= w[183]*din_5;
end
end
4'd8:begin
if(!state)
begin
p0 <= w[8]*din_0;
p1 <= w[24]*din_1;
p2 <= w[40]*din_2;
p3 <= w[56]*din_3;
p4 <= w[72]*din_4;
p5 <= w[88]*din_5;
end
else
begin
p0 <= w[104]*din_0;
p1 <= w[120]*din_1;
p2 <= w[136]*din_2;
p3 <= w[152]*din_3;
p4 <= w[168]*din_4;
p5 <= w[184]*din_5;
end
end
4'd9:begin
if(!state)
begin
p0 <= w[9]*din_0;
p1 <= w[25]*din_1;
p2 <= w[41]*din_2;
p3 <= w[57]*din_3;
p4 <= w[73]*din_4;
p5 <= w[89]*din_5;
end
else
begin
p0 <= w[105]*din_0;
p1 <= w[121]*din_1;
p2 <= w[137]*din_2;
p3 <= w[153]*din_3;
p4 <= w[169]*din_4;
p5 <= w[185]*din_5;
end
end
4'd10:begin
if(!state)
begin
p0 <= w[10]*din_0;
p1 <= w[26]*din_1;
p2 <= w[42]*din_2;
p3 <= w[58]*din_3;
p4 <= w[74]*din_4;
p5 <= w[90]*din_5;
end
else
begin
p0 <= w[106]*din_0;
p1 <= w[122]*din_1;
p2 <= w[138]*din_2;
p3 <= w[154]*din_3;
p4 <= w[170]*din_4;
p5 <= w[186]*din_5;
end
end
4'd11:begin
if(!state)
begin
p0 <= w[11]*din_0;
p1 <= w[27]*din_1;
p2 <= w[43]*din_2;
p3 <= w[59]*din_3;
p4 <= w[75]*din_4;
p5 <= w[91]*din_5;
end
else
begin
p0 <= w[107]*din_0;
p1 <= w[123]*din_1;
p2 <= w[139]*din_2;
p3 <= w[155]*din_3;
p4 <= w[171]*din_4;
p5 <= w[187]*din_5;
end
end
4'd12:begin
if(!state)
begin
p0 <= w[12]*din_0;
p1 <= w[28]*din_1;
p2 <= w[44]*din_2;
p3 <= w[60]*din_3;
p4 <= w[76]*din_4;
p5 <= w[92]*din_5;
end
else
begin
p0 <= w[108]*din_0;
p1 <= w[124]*din_1;
p2 <= w[140]*din_2;
p3 <= w[156]*din_3;
p4 <= w[172]*din_4;
p5 <= w[188]*din_5;
end
end
4'd13:begin
if(!state)
begin
p0 <= w[13]*din_0;
p1 <= w[29]*din_1;
p2 <= w[45]*din_2;
p3 <= w[61]*din_3;
p4 <= w[77]*din_4;
p5 <= w[93]*din_5;
end
else
begin
p0 <= w[109]*din_0;
p1 <= w[125]*din_1;
p2 <= w[141]*din_2;
p3 <= w[157]*din_3;
p4 <= w[173]*din_4;
p5 <= w[189]*din_5;
end
end
4'd14:begin
if(!state)
begin
p0 <= w[14]*din_0;
p1 <= w[30]*din_1;
p2 <= w[46]*din_2;
p3 <= w[62]*din_3;
p4 <= w[78]*din_4;
p5 <= w[94]*din_5;
end
else
begin
p0 <= w[110]*din_0;
p1 <= w[126]*din_1;
p2 <= w[142]*din_2;
p3 <= w[158]*din_3;
p4 <= w[174]*din_4;
p5 <= w[190]*din_5;
end
end
4'd15:begin
if(!state)
begin
p0 <= w[15]*din_0;
p1 <= w[31]*din_1;
p2 <= w[47]*din_2;
p3 <= w[63]*din_3;
p4 <= w[79]*din_4;
p5 <= w[95]*din_5;
end
else
begin
p0 <= w[111]*din_0;
p1 <= w[127]*din_1;
p2 <= w[143]*din_2;
p3 <= w[159]*din_3;
p4 <= w[175]*din_4;
p5 <= w[191]*din_5;
end
end
default:begin
p0 <= 0;
p1 <= 0;
p2 <= 0;
p3 <= 0;
p4 <= 0;
p5 <= 0;
end
endcase
end
//
always@(posedge clk)
begin
sum00 <= p0 + p1;
sum01 <= p2 + p3;
sum02 <= p4 + p5;
end
always@(posedge clk)
begin
sum10 <= sum00 + sum01;
sum11 <= sum02;
end
always@(posedge clk)
sum <= sum10 + sum11; // 每次并行度为6的输入与权重相乘计算结果
assign dout = dout_r;
assign ovalid = wren;
endmodule |
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