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module C_COUNTER_BINARY_V4_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q);
parameter C_AINIT_VAL = "0";
parameter C_COUNT_BY = "";
parameter C_COUNT_MODE = `c_up;
parameter C_COUNT_TO = "1111111111111111";
parameter C_ENABLE_RLOCS = 1;
parameter C_HAS_ACLR = 0;
parameter C_HAS_AINIT = 0;
parameter C_HAS_ASET = 0;
parameter C_HAS_CE = 0;
parameter C_HAS_IV = 0;
parameter C_HAS_L = 0;
parameter C_HAS_LOAD = 0;
parameter C_HAS_Q_THRESH0 = 0;
parameter C_HAS_Q_THRESH1 = 0;
parameter C_HAS_SCLR = 0;
parameter C_HAS_SINIT = 0;
parameter C_HAS_SSET = 0;
parameter C_HAS_THRESH0 = 0;
parameter C_HAS_THRESH1 = 0;
parameter C_HAS_UP = 0;
parameter C_LOAD_ENABLE = `c_no_override;
parameter C_LOAD_LOW = 0;
parameter C_PIPE_STAGES = 0;
parameter C_RESTRICT_COUNT = 0;
parameter C_SINIT_VAL = "0";
parameter C_SYNC_ENABLE = `c_override;
parameter C_SYNC_PRIORITY = `c_clear;
parameter C_THRESH0_VALUE = "1111111111111111";
parameter C_THRESH1_VALUE = "1111111111111111";
parameter C_THRESH_EARLY = 1;
parameter C_WIDTH = 16;
parameter C_OUT_TYPE = `c_signed;
parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0);
parameter iaxero = {62{"0"}};
parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE};
parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE};
parameter iazero = {64{"0"}};
parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ?
(iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ?
(iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ?
(iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ?
(iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ?
(iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ?
(iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ?
(iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ?
(iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ?
(iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ?
(iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ?
(iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ?
(iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ?
(iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ?
(iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ?
(iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ?
(iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ?
(iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ?
(iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ?
(iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ?
(iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ?
(iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ?
(iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ?
(iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ?
(iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ?
(iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ?
(iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ?
(iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ?
(iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ?
(iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ?
(iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ?
(iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0));
parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ?
(iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ?
(iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ?
(iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ?
(iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ?
(iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ?
(iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ?
(iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ?
(iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ?
(iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ?
(iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ?
(iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ?
(iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ?
(iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ?
(iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ?
(iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ?
(iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ?
(iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ?
(iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ?
(iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ?
(iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ?
(iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ?
(iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ?
(iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ?
(iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ?
(iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ?
(iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ?
(iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ?
(iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ?
(iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ?
(iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ?
(iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0))
: (C_HAS_SCLR == 1 ? 1 : 0));
input CLK;
input UP;
input CE;
input LOAD;
input [C_WIDTH-1 : 0] L;
input [C_WIDTH-1 : 0] IV;
input ACLR;
input ASET;
input AINIT;
input SCLR;
input SSET;
input SINIT;
output THRESH0;
output Q_THRESH0;
output THRESH1;
output Q_THRESH1;
output [C_WIDTH-1 : 0] Q;
// Internal values to drive signals when input is missing
wire intUP;
wire intUPbar = ~intUP;
wire intCE;
wire intLOAD;
wire [C_WIDTH-1 : 0] intL;
wire [C_WIDTH-1 : 0] intB;
wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}};
wire intSCLR;
wire intCount_to_reached;
reg intTHRESH0;
reg intTHRESH1;
wire intQ_THRESH0;
wire intQ_THRESH1;
wire [C_WIDTH-1 : 0] intFBq;
wire [C_WIDTH-1 : 0] intFBs;
wire [C_WIDTH-1 : 0] intQ = intFBq;
wire [C_WIDTH-1 : 0] intFBq_or_zero;
wire [C_WIDTH-1 : 0] intFBs_or_q;
wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY);
wire [C_WIDTH-1 : 0] intB_or_load;
wire [C_WIDTH-1 : 0] tmpintB_or_load;
wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx);
wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx);
wire [C_WIDTH-1 : 0] Q = intQ;
wire [C_WIDTH-1 : 0] intXLOADMUX;
wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL);
wire [C_WIDTH-1 : 0] intXL;
wire intXLOAD;
wire intXXLOAD;
wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD;
// Sort out default values for missing ports
assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0));
assign intCE = defval(CE, C_HAS_CE, 1);
assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}});
assign intB = (C_HAS_IV == 1 ? IV : intCount_by);
assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL);
assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD );
assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0));
assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0));
assign intSCLR = defval(SCLR, C_HAS_SCLR, 0);
assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB));
assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq);
// The addsub on which this is based...
C_ADDSUB_V4_0 #(C_COUNT_MODE,
C_AINIT_VAL,
C_OUT_TYPE,
C_WIDTH,
(((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))),
C_LOAD_LOW, // DLUNN CHANGED FROM 0,
0,
C_OUT_TYPE,
"",
C_WIDTH,
C_ENABLE_RLOCS,
C_HAS_ACLR,
C_HAS_UP,
C_HAS_AINIT,
C_HAS_ASET,
0,
C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1,
0,
0,
0,
C_HAS_CE,
1,
0,
0,
1,
0,
0,
0,
1,
adder_HAS_SCLR,
C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1),
C_HAS_SSET,
C_WIDTH-1,
1,
0,
C_WIDTH,
C_PIPE_STAGES,
C_SINIT_VAL,
C_SYNC_ENABLE,
C_SYNC_PRIORITY)
the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP),
.CE(CE), .C_IN(intUPbar), .ACLR(ACLR), .ASET(ASET),
.AINIT(AINIT), .SCLR(intSCLR_RESET), .SSET(SSET),
.SINIT(SINIT), .BYPASS(intXLOAD), .S(intFBs), .Q(intFBq));
// The Restrict Count/Sinit LOAD mux
C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
0, 0, 1, "", 0, 0, C_WIDTH)
mxRCSL(.MA(intSINITVAL), .MB(intL), .S(intLOAD), .O(intXLOADMUX));
// The feedback mux
C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
0, 0, 1, "", 0, 0, C_WIDTH)
mxfb(.MA(intFBq), .MB(all_zeros), .S(intXXLOAD), .O(intFBq_or_zero));
// The LOAD mux
C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2,
0, 0, 1, "", 0, 0, C_WIDTH)
mx1(.MA(intB), .MB(intXL), .S(intXXLOAD), .O(tmpintB_or_load));
// The Threshhold comparators
C_COMPARE_V4_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0,
0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH)
th0(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH0), .QA_EQ_B(Q_THRESH0));
C_COMPARE_V4_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1,
0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH)
th1(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH1), .QA_EQ_B(Q_THRESH1));
C_COMPARE_V4_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0,
0, 0, 0, 0, 0, 0, C_HAS_CE, 1,
0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH)
th_to(.A(intFBs), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(SCLR), .QA_EQ_B(intCount_to_reached));
initial
begin
#1;
end
function defval;
input i;
input hassig;
input val;
begin
if(hassig == 1)
defval = i;
else
defval = val;
end
endfunction
function [C_WIDTH - 1 : 0] to_bits;
input [C_WIDTH*8 : 1] instring;
integer i;
begin
for(i = C_WIDTH; i > 0; i = i - 1)
begin // Is this character a '0'? (ASCII = 48 = 00110000)
if(instring[(i*8)] == 0 &&
instring[(i*8)-1] == 0 &&
instring[(i*8)-2] == 1 &&
instring[(i*8)-3] == 1 &&
instring[(i*8)-4] == 0 &&
instring[(i*8)-5] == 0 &&
instring[(i*8)-6] == 0 &&
instring[(i*8)-7] == 0)
to_bits[i-1] = 0;
// Or is it a '1'?
else if(instring[(i*8)] == 0 &&
instring[(i*8)-1] == 0 &&
instring[(i*8)-2] == 1 &&
instring[(i*8)-3] == 1 &&
instring[(i*8)-4] == 0 &&
instring[(i*8)-5] == 0 &&
instring[(i*8)-6] == 0 &&
instring[(i*8)-7] == 1)
to_bits[i-1] = 1;
// Or is it a ' '? (a null char - in which case insert a '0')
else if(instring[(i*8)] == 0 &&
instring[(i*8)-1] == 0 &&
instring[(i*8)-2] == 0 &&
instring[(i*8)-3] == 0 &&
instring[(i*8)-4] == 0 &&
instring[(i*8)-5] == 0 &&
instring[(i*8)-6] == 0 &&
instring[(i*8)-7] == 0)
to_bits[i-1] = 0;
else
begin
$display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring);
$finish;
end
end
end
endfunction
endmodule |
module div_gen
(clk,
dividend,
divisor,
input_strobe,
output_strobe,
quotient);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, CLK_DOMAIN div_gen_clk, FREQ_HZ 200000000, INSERT_VIP 0, PHASE 0.000" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.DIVIDEND DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.DIVIDEND, LAYERED_METADATA undef" *) input [31:0]dividend;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.DIVISOR DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.DIVISOR, LAYERED_METADATA undef" *) input [23:0]divisor;
input input_strobe;
output output_strobe;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.QUOTIENT DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.QUOTIENT, LAYERED_METADATA undef" *) output [31:0]quotient;
wire clk_1;
wire [55:0]div_gen_0_m_axis_dout_tdata;
wire div_gen_0_m_axis_dout_tvalid;
wire [31:0]dividend_1;
wire [23:0]divisor_1;
wire input_strobe_1;
wire [31:0]xlslice_0_Dout;
assign clk_1 = clk;
assign dividend_1 = dividend[31:0];
assign divisor_1 = divisor[23:0];
assign input_strobe_1 = input_strobe;
assign output_strobe = div_gen_0_m_axis_dout_tvalid;
assign quotient[31:0] = xlslice_0_Dout;
div_gen_div_gen_0_0 div_gen_0
(.aclk(clk_1),
.m_axis_dout_tdata(div_gen_0_m_axis_dout_tdata),
.m_axis_dout_tvalid(div_gen_0_m_axis_dout_tvalid),
.s_axis_dividend_tdata(dividend_1),
.s_axis_dividend_tvalid(input_strobe_1),
.s_axis_divisor_tdata(divisor_1),
.s_axis_divisor_tvalid(input_strobe_1));
div_gen_xlslice_0_0 xlslice_0
(.Din(div_gen_0_m_axis_dout_tdata),
.Dout(xlslice_0_Dout));
endmodule |
module axi_master_bfm (/*AUTOARG*/
// Outputs
awid, awadr, awlen, awsize, awburst, awlock, awcache, awprot,
awvalid, wid, wrdata, wstrb, wlast, wvalid, bid, bresp, bvalid,
arid, araddr, arlen, arsize, arlock, arcache, arprot, arvalid,
rready, test_fail,
// Inputs
aclk, aresetn, awready, wready, bready, arready, rid, rdata, rresp,
rlast, rvalid
) ;
//
// Global Signals
//
input wire aclk;
input wire aresetn; //Active LOW
//
// Write Address Channel
//
output reg [3:0] awid; // Address Write ID
output reg [31:0] awadr; // Write Address
output reg [3:0] awlen; // Burst Length
output reg [2:0] awsize; // Burst Size
output reg [1:0] awburst; // Burst Type
output reg [1:0] awlock; // Lock Type
output reg [3:0] awcache; // Cache Type
output reg [2:0] awprot; // Protection Type
output reg awvalid; // Write Address Valid
input wire awready; // Write Address Ready
//
// Write Data Channel
//
output reg [3:0] wid; // Write ID
output reg [31:0] wrdata; // Write Data
output reg [3:0] wstrb; // Write Strobes
output reg wlast; // Write Last
output reg wvalid; // Write Valid
input wire wready; // Write Ready
//
// Write Response Channel
//
output reg [3:0] bid; // Response ID
output reg [1:0] bresp; // Write Response
output reg bvalid; // Write Response Valid
input wire bready; // Response Ready
//
// Read Address Channel
//
output reg [3:0] arid; // Read Address ID
output reg [31:0] araddr; // Read Address
output reg [3:0] arlen; // Burst Length
output reg [2:0] arsize; // Burst Size
output reg [1:0] arlock; // Lock Type
output reg [3:0] arcache; // Cache Type
output reg [2:0] arprot; // Protection Type
output reg arvalid; // Read Address Valid
input wire arready; // Read Address Ready
//
// Read Data Channel
//
input wire [3:0] rid; // Read ID
input wire [31:0] rdata; // Read Data
input wire [1:0] rresp; // Read Response
input wire rlast; // Read Last
input wire rvalid; // Read Valid
output reg rready; // Read Ready
//
// Test Signals
//
output reg test_fail;
//
// Set all output regs to 0
//
initial begin
awid <= 0;
awadr <= 0;
awlen <= 0;
awsize <=0;
awburst <= 0;
awlock <= 0;
awcache <= 0;
awprot <= 0;
awvalid <= 0;
wid <= 0;
wrdata <= 0;
wstrb <= 0;
wlast <= 0;
wvalid <= 0;
bid <= 0;
bresp <= 0;
bvalid <= 0;
arid <= 0;
araddr <= 0;
arlen <= 0;
arsize <= 0;
arlock <= 0;
arcache <= 0;
arprot <= 0;
arvalid <= 0;
rready <= 0;
test_fail <= 0;
end
//
// Task: Single Write Transaction
//
task write_single;
input [31:0] address;
input [31:0] data;
input [2:0] size;
input [3:0] strobe;
begin
test_fail <= 0;
//
// Operate in a synchronous manner
//
@(posedge aclk);
$display("TASK: Write Single Addr = 0x%4x Data = 0x%4x Size = 0x%x Strobe = 0x%x Time = %d",
address, data, size, strobe, $time);
//
// Address Phase
//
awid <= 0;
awadr <= address;
awvalid <= 1;
awlen <= `AXI_BURST_LENGTH_1;
awsize <= size;
awburst <= `AXI_BURST_TYPE_FIXED;
awlock <= `AXI_LOCK_NORMAL;
awcache <= 0;
awprot <= `AXI_PROTECTION_NORMAL;
@(posedge awready); //This should arrive on a clock edge!
//
// Data Phase
//
awvalid <= 0;
awadr <= 'bX;
wid <= 0;
wvalid <= 1;
wrdata <= data;
wstrb <= strobe;
wlast <= 1;
@(posedge wready);
//
// Response Phase
//
wid <= 0;
wvalid <= 0;
wrdata <= 'bX;
wstrb <= 0;
wlast <= 0;
end
endtask //
//
// Task: Single Read Transaction
//
task read_single;
input [31:0] address;
output [31:0] data;
input [2:0] size;
input [3:0] strobe;
begin
test_fail <= 0;
//
// Address Phase
//
arid <= 0;
araddr <= address;
arvalid <= 1;
arlen <= `AXI_BURST_LENGTH_1;
arsize <= size;
arlock <= `AXI_LOCK_NORMAL;
arcache <= 0;
arprot <= `AXI_PROTECTION_NORMAL;
rready <= 0;
@(posedge arready); //This should arrive on a clock edge!
//
// Data Phase
//
arvalid <= 0;
rready <= 1;
@(posedge rvalid);
rready <= 0;
data <= rdata;
@(negedge rvalid);
araddr <= 'bx;
$display("TASK: Read Single Addr Addr = 0x%4x Data = 0x%4x Size = 0x%x Strobe = 0x%x Time = %d",
address, data, size, strobe, $time);
end
endtask //
task read_single_and_check;
input [31:0] address;
input [31:0] expected_data;
input [2:0] size;
input [3:0] strobe;
reg [31:0] read_data;
begin
test_fail <= 0;
read_single(address, read_data, size, strobe);
if (read_data !== expected_data) begin
$display("TASK: Read Single and Check FAIL Read = 0x%04x Expected = 0x%04x @ %d",
read_data, expected_data, $time);
test_fail <= 1;
end
end
endtask //
endmodule // axi_master_bfm |
module testbench_axi_master_bfm (/*AUTOARG*/) ;
//
// Free running clock
//
reg aclk;
initial begin
aclk <= 0;
forever #5 aclk<=~aclk;
end
//
// Reset
//
reg aresetn;
initial begin
aresetn <= 1;
#11;
aresetn <= 0;
repeat (10) @(posedge aclk);
aresetn <= 1;
end
/*AUTOREG*/
reg test_passed;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] araddr; // From master of axi_master_bfm.v
wire [3:0] arcache; // From master of axi_master_bfm.v
wire [3:0] arid; // From master of axi_master_bfm.v
wire [3:0] arlen; // From master of axi_master_bfm.v
wire [1:0] arlock; // From master of axi_master_bfm.v
wire [2:0] arprot; // From master of axi_master_bfm.v
wire arready; // From slave of axi_slave_generic.v
wire [2:0] arsize; // From master of axi_master_bfm.v
wire arvalid; // From master of axi_master_bfm.v
wire [31:0] awadr; // From master of axi_master_bfm.v
wire [1:0] awburst; // From master of axi_master_bfm.v
wire [3:0] awcache; // From master of axi_master_bfm.v
wire [3:0] awid; // From master of axi_master_bfm.v
wire [3:0] awlen; // From master of axi_master_bfm.v
wire [1:0] awlock; // From master of axi_master_bfm.v
wire [2:0] awprot; // From master of axi_master_bfm.v
wire awready; // From slave of axi_slave_generic.v
wire [2:0] awsize; // From master of axi_master_bfm.v
wire awvalid; // From master of axi_master_bfm.v
wire [3:0] bid; // From master of axi_master_bfm.v, ...
wire [1:0] bresp; // From master of axi_master_bfm.v, ...
wire bvalid; // From master of axi_master_bfm.v, ...
wire [31:0] rdata; // From slave of axi_slave_generic.v
wire [3:0] rid; // From slave of axi_slave_generic.v
wire rlast; // From slave of axi_slave_generic.v
wire rready; // From master of axi_master_bfm.v
wire [1:0] rresp; // From slave of axi_slave_generic.v
wire rvalid; // From slave of axi_slave_generic.v
wire test_fail; // From master of axi_master_bfm.v
wire [3:0] wid; // From master of axi_master_bfm.v
wire wlast; // From master of axi_master_bfm.v
wire [31:0] wrdata; // From master of axi_master_bfm.v
wire wready; // From slave of axi_slave_generic.v
wire [3:0] wstrb; // From master of axi_master_bfm.v
wire wvalid; // From master of axi_master_bfm.v
// End of automatics
axi_master_bfm master(/*AUTOINST*/
// Outputs
.awid (awid[3:0]),
.awadr (awadr[31:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[3:0]),
.wrdata (wrdata[31:0]),
.wstrb (wstrb[3:0]),
.wlast (wlast),
.wvalid (wvalid),
.bid (bid[3:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.arid (arid[3:0]),
.araddr (araddr[31:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready),
.test_fail (test_fail),
// Inputs
.aclk (aclk),
.aresetn (aresetn),
.awready (awready),
.wready (wready),
.bready (bready),
.arready (arready),
.rid (rid[3:0]),
.rdata (rdata[31:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid));
axi_slave_generic slave (/*AUTOINST*/
// Outputs
.awready (awready),
.wready (wready),
.bid (bid[3:0]),
.bresp (bresp[1:0]),
.bvalid (bvalid),
.arready (arready),
.rid (rid[3:0]),
.rdata (rdata[31:0]),
.rresp (rresp[1:0]),
.rlast (rlast),
.rvalid (rvalid),
// Inputs
.aclk (aclk),
.aresetn (aresetn),
.awid (awid[3:0]),
.awadr (awadr[31:0]),
.awlen (awlen[3:0]),
.awsize (awsize[2:0]),
.awburst (awburst[1:0]),
.awlock (awlock[1:0]),
.awcache (awcache[3:0]),
.awprot (awprot[2:0]),
.awvalid (awvalid),
.wid (wid[3:0]),
.wrdata (wrdata[31:0]),
.wstrb (wstrb[3:0]),
.wlast (wlast),
.wvalid (wvalid),
.bready (bready),
.arid (arid[3:0]),
.araddr (araddr[31:0]),
.arlen (arlen[3:0]),
.arsize (arsize[2:0]),
.arlock (arlock[1:0]),
.arcache (arcache[3:0]),
.arprot (arprot[2:0]),
.arvalid (arvalid),
.rready (rready));
test_case test();
initial begin
@(posedge test_fail);
$display("TEST FAIL @ %d", $time);
repeat (10) @(posedge aclk);
$finish;
end
initial begin
test_passed <= 0;
@(posedge test_passed);
$display("TEST PASSED: @ %d", $time);
repeat (10) @(posedge aclk);
$finish;
end
endmodule // testbench_axi_master_bfm |
module axi_master_generic (/*AUTOARG*/
// Outputs
awid, awadr, awlen, awsize, awburst, awlock, awcache, awprot,
awvalid, wid, wrdata, wstrb, wlast, wvalid, bid, bresp, bvalid,
arid, araddr, arlen, arsize, arlock, arcache, arprot, arvalid,
rready,
// Inputs
aclk, aresetn, awready, wready, bready, arready, rid, rdata, rresp,
rlast, rvalid
) ;
//
// Global Signals
//
input wire aclk;
input wire aresetn; //Active LOW
//
// Write Address Channel
//
output reg [3:0] awid; // Address Write ID
output reg [31:0] awadr; // Write Address
output reg [3:0] awlen; // Burst Length
output reg [2:0] awsize; // Burst Size
output reg [1:0] awburst; // Burst Type
output reg [1:0] awlock; // Lock Type
output reg [3:0] awcache; // Cache Type
output reg [2:0] awprot; // Protection Type
output reg awvalid; // Write Address Valid
input wire awready; // Write Address Ready
//
// Write Data Channel
//
output reg [3:0] wid; // Write ID
output reg [31:0] wrdata; // Write Data
output reg [3:0] wstrb; // Write Strobes
output reg wlast; // Write Last
output reg wvalid; // Write Valid
input wire wready; // Write Ready
//
// Write Response CHannel
//
output reg [3:0] bid; // Response ID
output reg [1:0] bresp; // Write Response
output reg bvalid; // Write Response Valid
input wire bready; // Response Ready
//
// Read Address Channel
//
output reg [3:0] arid; // Read Address ID
output reg [31:0] araddr; // Read Address
output reg [3:0] arlen; // Burst Length
output reg [2:0] arsize; // Burst Size
output reg [1:0] arlock; // Lock Type
output reg [3:0] arcache; // Cache Type
output reg [2:0] arprot; // Protection Type
output reg arvalid; // Read Address Valid
input wire arready; // Read Address Ready
input wire [3:0] rid; // Read ID
input wire [31:0] rdata; // Read Data
input wire [1:0] rresp; // Read Response
input wire rlast; // Read Last
input wire rvalid; // Read Valid
output reg rready; // Read Ready
endmodule // axi_master_generic |
module testbench2;
reg [31:0] address, data;
reg mode, clk;
wire [31:0] out;
cache_and_ram tb(
.address(address),
.data(data),
.mode(mode),
.clk(clk),
.out(out)
);
initial
begin
clk = 1'b1;
address = 32'b00000000000000000000000000000000; // 0
data = 32'b00000000000000000011100011000000; // 14528
mode = 1'b1;
#200
address = 32'b10100111111001011111101111011100; // 2816867292 % size = 3036
data = 32'b00000000000010000000100001010101; // 526421
mode = 1'b1;
#200
address = 32'b00000000000000000000000000000000; // 0
data = 32'b00000000000000000011100011000000; // 14528
mode = 1'b0;
#200
address = 32'b10100111111001011111101111011100; // 2816867292 % size = 3036
data = 32'b00000000000010000000100001010101; // 526421
mode = 1'b0;
#200
address = 32'b00000000000011110100011111010001; // 1001425 % size = 2001
data = 32'b00000001100000110001101100010110; // 25369366
mode = 1'b1;
#200
address = 32'b00000000000011110100011111010001; // 1001425 % size = 2001
data = 32'b00000001100000110001101100010110; // 25369366
mode = 1'b0;
#200
address = 32'b10100111111001011111101111011100; // 2816867292 % size = 3036
data = 32'b00000000000000000011100011000000; // 14528
mode = 1'b1;
#200
address = 32'b00000000000011110100011111010001; // 1001425 % size = 2001
data = 32'b00000000000000000011100011000000; // 14528
mode = 1'b1;
#200
address = 32'b00000000000011110100011111010001; // 1001425 % size = 2001
data = 32'b00000000000000000000000000000000; // 0
mode = 1'b0;
#200
address = 32'b10100111111001011111101111011100; // 2816867292 % size = 3036
data = 32'b00000000000000000000000000000000; // 0
mode = 1'b0;
end
initial
$monitor("address = %d data = %d mode = %d out = %d", address % 4096, data, mode, out);
always #25 clk = ~clk;
endmodule |
module ram();
parameter size = 4096; //size of a ram in bits
reg [31:0] ram [0:size-1]; //data matrix for ram
endmodule |
module cache();
parameter size = 64; // cache size
parameter index_size = 6; // index size
reg [31:0] cache [0:size - 1]; //registers for the data in cache
reg [11 - index_size:0] tag_array [0:size - 1]; // for all tags in cache
reg valid_array [0:size - 1]; //0 - there is no data 1 - there is data
initial
begin: initialization
integer i;
for (i = 0; i < size; i = i + 1)
begin
valid_array[i] = 1'b0;
tag_array[i] = 6'b000000;
end
end
endmodule |
module serializer(
input clk,
input clk35,
input notclk35,
input [6:0] data,
input rst,
output out
);
reg [6:0] buffer [1:0]; // 14 bits buffer
reg [1:0] shiftdata = 0;
reg datacount = 0;
reg [2:0] outcount = 0;
reg DataInBuffer = 0;
reg SendOK = 0;
ODDR2 #(
.DDR_ALIGNMENT("NONE") // Sets output alignment to "NONE", "C0" or "C1"
) clock_forward_inst (
.Q(out), // 1-bit DDR output data
.C0(clk35), // 1-bit clock input
.C1(notclk35), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(shiftdata[0]), // 1-bit data input (associated with C0)
.D1(shiftdata[1]), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
always @(posedge clk or posedge rst)
begin
if(rst == 1'b1)
begin
buffer[0] <= 7'b0000000;
buffer[1] <= 7'b0000000;
datacount <= 0;
DataInBuffer <= 0;
end
else
begin
DataInBuffer <= 1;
datacount <= datacount + 1;
buffer[datacount] <= data;
//buffer[datacount] <= {data[6],data[5],data[4],data[3],data[2],data[1],data[0]};
end
end
always @(posedge clk35 or posedge rst)
begin
if(rst == 1'b1)
begin
outcount <= 0;
shiftdata <= 0;
SendOK <= 0;
end
else
begin
if(outcount == 6)
outcount <= 0;
else
outcount <= outcount + 1;
if(DataInBuffer && outcount == 6)
SendOK <= 1;
if(SendOK)
begin
case (outcount)
0: shiftdata <= { buffer[0][0], buffer[0][1] };
1: shiftdata <= { buffer[0][2], buffer[0][3] };
2: shiftdata <= { buffer[0][4], buffer[0][5] };
3: shiftdata <= { buffer[0][6], buffer[1][0] };
4: shiftdata <= { buffer[1][1], buffer[1][2] };
5: shiftdata <= { buffer[1][3], buffer[1][4] };
6: shiftdata <= { buffer[1][5], buffer[1][6] };
endcase
end
end
end
endmodule |
module maincore(
input clk,
output channel1_p,
output channel1_n,
output channel2_p,
output channel2_n,
output channel3_p,
output channel3_n,
output clock_p,
output clock_n
);
/*
parameter ScreenX = 1024;
parameter ScreenY = 768;
parameter BlankingVertical = 35;
parameter BlankingHorizontal = 280;
*/
parameter ScreenX = 1280;
parameter ScreenY = 800;
parameter BlankingVertical = 12;
parameter BlankingHorizontal = 192;
wire clo,clk4x,clk_lckd, clkdcm;
reg [5:0] Red = 0;
reg [5:0] Blue = 0;
reg [5:0] Green = 0;
reg HSync = 1, VSync = 1, DataEnable = 0;
reg [10:0] ContadorX = 0; // Contador de colunas
reg [10:0] ContadorY = 0; // Contador de linhas
reg [7:0] SendFrames = 0;
DCM_SP #(
.CLKIN_PERIOD ("62.5ns"), // 64MHz Clock from 16MHz Input
.CLKFX_MULTIPLY (4),
.CLKFX_DIVIDE (1)
)
dcm_main (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk4x),
.LOCKED (clk_lckd)
);
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
video_lvds videoencoder (
.DotClock(clk4x),
.HSync(HSync),
.VSync(VSync),
.DataEnable(DataEnable),
.Red(Red),
.Green(Green),
.Blue(Blue),
.channel1_p(channel1_p),
.channel1_n(channel1_n),
.channel2_p(channel2_p),
.channel2_n(channel2_n),
.channel3_p(channel3_p),
.channel3_n(channel3_n),
.clock_p(clock_p),
.clock_n(clock_n)
);
reg [5:0] Parallax = 0;
//Cycle Generator
always @(posedge clk4x)
begin
//Sync Generator
ContadorX <= ContadorX + 1;
if(ContadorX == ScreenX)
begin
DataEnable <= 0;
HSync <= 0;
end
if((ContadorX == 0) & (ContadorY < ScreenY))
DataEnable <= 1;
if(ContadorX == (ScreenX+BlankingHorizontal))
HSync <= 1;
if(ContadorX == (ScreenX+BlankingHorizontal))
begin
if(ContadorY == ScreenY)
begin
VSync <= 0;
DataEnable <= 0;
end
if(ContadorY == (ScreenY+BlankingVertical))
begin
VSync <= 1;
Parallax <= Parallax - 1;
ContadorY <= 0;
ContadorX <= 0;
end
else
ContadorY <= ContadorY +1;
end
if(ContadorX == (ScreenX+BlankingHorizontal))
ContadorX <= 0;
end
//Video Generator
always @(posedge clk4x)
begin
if(ContadorX == ScreenX)
begin
Blue <= 0;
Red <= 0;
Green <= 0;
end
else
begin
//Center 640x400 - Screen 640x480 -> Box: 640-320,400-240,640+320,400+240
if( (ContadorX > 320 && ContadorY > 160) && ( ContadorX < 960 && ContadorY < 640) )
begin
// ScreenBox
Blue <= 0;
Red <= 0;
Green <= 0;
end
// 3px border: (317,160),(317,640),(319,640),(319,160)
// 3px border: (317,157),(960,157),(960,160),(317,160)
else if ( (ContadorX >= 317 && ContadorY >= 160 && ContadorY <= 640 && ContadorX <= 320) ||
(ContadorX >= 317 && ContadorY >= 157 && ContadorY <= 160 && ContadorX <= 963) ||
(ContadorX >= 960 && ContadorY >= 157 && ContadorY <= 640 && ContadorX <= 963) ||
(ContadorX >= 317 && ContadorY >= 640 && ContadorY <= 643 && ContadorX <= 963) )
begin
Red <= 255;
Green <= 0;
Blue <= 0;
end
else
begin
Red <= ( ( (ContadorY[5:0]+Parallax) ^ (ContadorX[5:0]+Parallax) ) * 2 );
Blue <= ( ( (ContadorY[5:0]+Parallax) ^ (ContadorX[5:0]+Parallax) ) * 3 );
Green <= ( ( (ContadorY[5:0]+Parallax) ^ (ContadorX[5:0]+Parallax) ) * 4 );
end
end
end
endmodule |
module lvds_clockgen(
input clk,
output clk35,
output nclk35,
output rstclk,
output dataclock,
output lvdsclk
);
// Clock: 1100011
wire clk_lckd;
wire clkdcm;
wire clo;
DCM_SP #(.CLKIN_PERIOD ("15.625"),
.DESKEW_ADJUST ("0"),
.CLKFX_MULTIPLY (7),
.CLKFX_DIVIDE (2))
dcm_clk (
.CLKIN (clk),
.CLKFB (clo),
.RST (1'b0),
.CLK0 (clkdcm),
.CLKFX (clk35),
.CLKFX180 (nclk35),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (),
.PSDONE (),
.STATUS (),
.DSSEN (1'b0),
.PSINCDEC (1'b0),
.PSEN (1'b0),
.PSCLK (1'b0),
.LOCKED (clk_lckd)) ;
BUFG clk_bufg (.I(clkdcm), .O(clo) ) ;
assign not_clk_lckd = ~clk_lckd ;
FDP fd_rst_clk (.D(not_clk_lckd), .C(clo), .Q(rst_clk)) ;
// The LVDS Clock is 4:3, if you need 3:4 you can use 7'b0011100
serializer lvdsclkman (
.clk(clo),
.clk35(clk35),
.notclk35(nclk35),
.data(7'b1100011),
.rst(rst_clk),
.out(lvdsclk)
);
assign rstclk = rst_clk;
assign dataclock = clo;
endmodule |
module video_lvds(
input DotClock,
input HSync,
input VSync,
input DataEnable,
input [5:0] Red,
input [5:0] Green,
input [5:0] Blue,
output channel1_p,
output channel1_n,
output channel2_p,
output channel2_n,
output channel3_p,
output channel3_n,
output clock_p,
output clock_n
);
wire clk35, notclk35, c1,c2,c3,lvdsclk, rst_clk, DataClock;
wire [20:0] VideoData;
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel1_obuf (.I(c1), .O(channel1_p), .OB(channel1_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel2_obuf (.I(c2), .O(channel2_p), .OB(channel2_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_channel3_obuf (.I(c3), .O(channel3_p), .OB(channel3_n) );
OBUFDS #(.IOSTANDARD("LVDS_33")) lvds_clock_obuf (.I(lvdsclk), .O(clock_p), .OB(clock_n) );
lvds_clockgen clockgenerator (
.clk(DotClock),
.clk35(clk35),
.nclk35(notclk35),
.rstclk(rst_clk),
.dataclock(DataClock),
.lvdsclk(lvdsclk)
);
serializer channel1_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[6:0]),
.rst(rst_clk),
.out(c1)
);
serializer channel2_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[13:7]),
.rst(rst_clk),
.out(c2)
);
serializer channel3_ser (
.clk(DataClock),
.clk35(clk35),
.notclk35(notclk35),
.data(VideoData[20:14]),
.rst(rst_clk),
.out(c3)
);
assign VideoData[20:14] = {Blue[2],Blue[3],Blue[4],Blue[5],HSync,VSync,DataEnable};
assign VideoData[13:7] = {Green[1],Green[2],Green[3],Green[4],Green[5],Blue[0],Blue[1]};
assign VideoData[6:0] = {Red[0],Red[1],Red[2],Red[3],Red[4],Red[5],Green[0]};
endmodule |
module hbmc_dfifo #
(
parameter integer DATA_WIDTH = 32
)
(
input wire fifo_arst,
input wire fifo_wr_clk,
input wire [DATA_WIDTH - 1:0] fifo_wr_din,
input wire [DATA_WIDTH/8 - 1:0] fifo_wr_strb,
input wire fifo_wr_ena,
output wire fifo_wr_full,
input wire fifo_rd_clk,
output wire [15:0] fifo_rd_dout,
output wire [1:0] fifo_rd_strb,
input wire fifo_rd_ena,
output wire fifo_rd_empty
);
wire [17:0] dout;
assign fifo_rd_dout = dout[15:0];
assign fifo_rd_strb = dout[17:16];
generate
case (DATA_WIDTH)
16: begin : dFIFO_18b_18b_512w
wire [17:0] din = {fifo_wr_strb[1:0], fifo_wr_din[15:0]};
fifo_18b_18b_512w
fifo_18b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_data_count ( /*---NC---*/ ), // output [8 : 0] rd_data_count
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
32: begin : dFIFO_36b_18b_512w
wire [35:0] din = {
fifo_wr_strb[1:0], fifo_wr_din[15:0],
fifo_wr_strb[3:2], fifo_wr_din[31:16]
};
fifo_36b_18b_512w
fifo_36b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [35 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
64: begin : dFIFO_72b_18b_512w
wire [71:0] din = {
fifo_wr_strb[1:0], fifo_wr_din[15:0],
fifo_wr_strb[3:2], fifo_wr_din[31:16],
fifo_wr_strb[5:4], fifo_wr_din[47:32],
fifo_wr_strb[7:6], fifo_wr_din[63:48]
};
fifo_72b_18b_512w
fifo_72b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [71 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
default: begin
INVALID_PARAMETER invalid_parameter_msg();
end
endcase
endgenerate
endmodule |
module hbmc_clk_obuf #
(
parameter integer DRIVE_STRENGTH = 8,
parameter SLEW_RATE = "SLOW"
)
(
input wire cen,
input wire clk,
output wire hb_ck_p,
output wire hb_ck_n
);
wire oddr_clk_p;
wire oddr_clk_n;
/*----------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_ck_p
(
.Q ( oddr_clk_p ), // 1-bit DDR output
.C ( ~clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( cen ), // 1-bit data input (positive edge)
.D2 ( 1'b0 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
OBUF #
(
.DRIVE ( DRIVE_STRENGTH ), // Specify the output drive strength
.SLEW ( SLEW_RATE ) // Specify the output slew rate
)
OBUF_ck_p
(
.I ( oddr_clk_p ), // Buffer input
.O ( hb_ck_p ) // Buffer output (connect directly to top-level port)
);
/*----------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_ck_n
(
.Q ( oddr_clk_n ), // 1-bit DDR output
.C ( ~clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( ~cen ), // 1-bit data input (positive edge)
.D2 ( 1'b1 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
OBUF #
(
.DRIVE ( DRIVE_STRENGTH ), // Specify the output drive strength
.SLEW ( SLEW_RATE ) // Specify the output slew rate
)
OBUF_ck_n
(
.I ( oddr_clk_n ), // Buffer input
.O ( hb_ck_n ) // Buffer output (connect directly to top-level port)
);
endmodule |
module hbmc_iobuf #
(
parameter integer DRIVE_STRENGTH = 8,
parameter SLEW_RATE = "SLOW",
parameter integer USE_IDELAY_PRIMITIVE = 0,
parameter real IODELAY_REFCLK_MHZ = 200.0,
parameter IODELAY_GROUP_ID = "HBMC",
parameter [4:0] IDELAY_TAPS_VALUE = 0
)
(
input wire arst,
input wire oddr_clk,
input wire iserdes_clk,
input wire iserdes_clkdiv,
input wire idelay_clk,
inout wire buf_io,
input wire buf_t,
input wire [1:0] sdr_i,
output reg [5:0] iserdes_o,
output wire iserdes_comb_o
);
wire buf_o;
wire buf_i;
wire tristate;
wire idelay_o;
wire iserdes_d;
wire [5:0] iserdes_q;
wire iserdes_ddly;
/*----------------------------------------------------------------------------------------------------------------------------*/
IOBUF #
(
.DRIVE ( DRIVE_STRENGTH ), // Specify the output drive strength
.SLEW ( SLEW_RATE ) // Specify the output slew rate
)
IOBUF_io_buf
(
.O ( buf_o ), // Buffer output
.IO ( buf_io ), // Buffer inout port (connect directly to top-level port)
.I ( buf_i ), // Buffer input
.T ( tristate ) // 3-state enable input, high = input, low = output
);
/*----------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_i
(
.Q ( buf_i ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( sdr_i[0] ), // 1-bit data input (positive edge)
.D2 ( sdr_i[1] ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_t
(
.Q ( tristate ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( buf_t ), // 1-bit data input (positive edge)
.D2 ( buf_t ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
/*----------------------------------------------------------------------------------------------------------------------------*/
generate
if (USE_IDELAY_PRIMITIVE) begin
(* IODELAY_GROUP = IODELAY_GROUP_ID *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #
(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE ( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( (IDELAY_TAPS_VALUE > 31)? 31 : IDELAY_TAPS_VALUE ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( IODELAY_REFCLK_MHZ ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst
(
.C ( idelay_clk ), // 1-bit input: Clock input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( buf_o ), // 1-bit input: Data input from the I/O
.DATAOUT ( idelay_o ), // 1-bit output: Delayed data output
.CNTVALUEIN ( 5'b00000 ), // 5-bit input: Counter value input
.CNTVALUEOUT ( /*--NC--*/ ), // 5-bit output: Counter value output
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
assign iserdes_d = 1'b0;
assign iserdes_ddly = idelay_o;
end else begin
/* Bypassing IDELAY primitive */
assign iserdes_d = buf_o;
assign iserdes_ddly = 1'b0;
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam IOBDELAY = (USE_IDELAY_PRIMITIVE)? "BOTH" : "NONE";
ISERDESE2 #
(
.SERDES_MODE ( "MASTER" ), // MASTER, SLAVE
.INTERFACE_TYPE ( "NETWORKING" ), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.DATA_RATE ( "DDR" ), // DDR, SDR
.DATA_WIDTH ( 6 ), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN ( "FALSE" ), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN ( "FALSE" ), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
.OFB_USED ( "FALSE" ), // Select OFB path (FALSE, TRUE)
.IOBDELAY ( IOBDELAY ), // NONE, BOTH, IBUF, IFD
.NUM_CE ( 1 ), // Number of clock enables (1,2)
.INIT_Q1 ( 1'b0 ), // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q2 ( 1'b0 ),
.INIT_Q3 ( 1'b0 ),
.INIT_Q4 ( 1'b0 ),
.SRVAL_Q1 ( 1'b0 ), // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q2 ( 1'b0 ),
.SRVAL_Q3 ( 1'b0 ),
.SRVAL_Q4 ( 1'b0 )
)
ISERDESE2_inst
(
.O ( iserdes_comb_o ), // 1-bit output: Combinatorial output
.Q1 ( iserdes_q[5] ), // Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q2 ( iserdes_q[4] ),
.Q3 ( iserdes_q[3] ),
.Q4 ( iserdes_q[2] ),
.Q5 ( iserdes_q[1] ),
.Q6 ( iserdes_q[0] ),
.Q7 ( /*-----NC-----*/ ),
.Q8 ( /*-----NC-----*/ ),
.BITSLIP ( 1'b0 ), // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
.CE1 ( 1'b1 ), // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE2 ( 1'b1 ),
.CLK ( iserdes_clk ), // 1-bit input: High-speed clock
.CLKB ( ~iserdes_clk ), // 1-bit input: High-speed secondary clock
.CLKDIV ( iserdes_clkdiv ), // 1-bit input: Divided clock
.CLKDIVP ( 1'b0 ), // 1-bit input: TBD
.OCLK ( 1'b0 ), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
.OCLKB ( 1'b0 ), // 1-bit input: High speed negative edge output clock
.D ( iserdes_d ), // 1-bit input: Data input
.DDLY ( iserdes_ddly ), // 1-bit input: Serial data from IDELAYE2
.OFB ( 1'b0 ), // 1-bit input: Data feedback from OSERDESE2
.RST ( arst ), // 1-bit input: Active high asynchronous reset
.DYNCLKDIVSEL ( 1'b0 ), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL ( 1'b0 ), // 1-bit input: Dynamic CLK/CLKB inversion
.SHIFTOUT1 ( /*-----NC-----*/ ), // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT2 ( /*-----NC-----*/ ),
.SHIFTIN1 ( 1'b0 ), // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN2 ( 1'b0 )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Register ISERDESE2 output */
always @(posedge iserdes_clkdiv or posedge arst) begin
if (arst) begin
iserdes_o <= {6{1'b0}};
end else begin
iserdes_o <= iserdes_q;
end
end
endmodule |
module hbmc_bit_sync #
(
parameter integer C_SYNC_STAGES = 3,
parameter C_RESET_STATE = 1'b0
)
(
input wire arst,
input wire clk,
input wire d,
output wire q
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_SYNC_STAGES - 1:0] d_sync;
always @(posedge clk or posedge arst) begin
if (arst) begin
d_sync <= {C_SYNC_STAGES{C_RESET_STATE}};
end else begin
d_sync <= {d_sync[C_SYNC_STAGES - 2:0], d};
end
end
assign q = d_sync[C_SYNC_STAGES - 1];
endmodule |
module hbmc_elastic_buf #
(
parameter DATA_WIDTH = 8
)
(
input wire arst,
input wire clk_din,
input wire clk_dout,
input wire [DATA_WIDTH - 1:0] din,
output reg [DATA_WIDTH - 1:0] dout
);
/*----------------------------------------------------------------------------------------------------------------------------*/
wire rst_0;
wire rst_1;
hbmc_arst_sync #
(
.C_SYNC_STAGES ( 3 )
)
hbmc_arst_sync_inst_0
(
.clk ( clk_din ),
.arst ( arst ),
.rst ( rst_0 )
);
hbmc_arst_sync #
(
.C_SYNC_STAGES ( 3 )
)
hbmc_arst_sync_inst_1
(
.clk ( clk_dout ),
.arst ( arst ),
.rst ( rst_1 )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
reg [4:0] wr_addr;
reg [4:0] rd_addr;
wire [DATA_WIDTH - 1:0] dout_ram;
/* Circular buffer write pointer */
always @(posedge clk_din or posedge rst_0) begin
if (rst_0) begin
wr_addr <= 5'd2; // write to read pointer margin
end else begin
wr_addr <= wr_addr + 1'b1;
end
end
/* Circular buffer read pointer */
always @(posedge clk_dout or posedge rst_1) begin
if (rst_1) begin
rd_addr <= 5'd0;
dout <= {DATA_WIDTH{1'b0}};
end else begin
rd_addr <= rd_addr + 1'b1;
dout <= dout_ram;
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
RAM32X1D #
(
.INIT ( 32'h00000000 ) // Initial contents of RAM
)
RAM32X1D_inst
(
.WCLK ( clk_din ), // Write clock input
.WE ( 1'b1 ), // Write enable input
.A0 ( wr_addr[0] ), // RW address[0] input bit
.A1 ( wr_addr[1] ), // RW address[1] input bit
.A2 ( wr_addr[2] ), // RW address[2] input bit
.A3 ( wr_addr[3] ), // RW address[3] input bit
.A4 ( wr_addr[4] ), // RW address[4] input bit
.D ( din[i] ), // Write 1-bit data input
.SPO ( /*--NC--*/ ), // RW 1-bit data output
.DPRA0 ( rd_addr[0] ), // RO address[0] input bit
.DPRA1 ( rd_addr[1] ), // RO address[1] input bit
.DPRA2 ( rd_addr[2] ), // RO address[2] input bit
.DPRA3 ( rd_addr[3] ), // RO address[3] input bit
.DPRA4 ( rd_addr[4] ), // RO address[4] input bit
.DPO ( dout_ram[i] ) // RO 1-bit data output
);
end
endgenerate
endmodule |
module hbmc_dru
(
input wire clk,
input wire arst,
input wire [5:0] rwds_oversampled,
input wire [47:0] data_oversampled,
output wire recov_valid,
output wire [15:0] recov_data,
output reg align_error,
output reg rwds_error
);
/*----------------------------------------------------------------------------------------------------------------------------*/
reg prev_last_bit;
reg [5:0] rwds_pair_xor;
reg [47:0] data_pipeline;
always @(posedge clk or posedge arst) begin
if (arst) begin
prev_last_bit <= 1'b0;
rwds_pair_xor <= {6{1'b0}};
data_pipeline <= {48{1'b0}};
end else begin
/* Single bit pipeline delay for input data
* to compensate edge detection stage delay */
data_pipeline <= data_oversampled;
/* Saving previous sample last bit to detect
* an edge at the transition of two samples */
prev_last_bit <= rwds_oversampled[5];
/* RWDS edge detection vector */
rwds_pair_xor <= {
^ rwds_oversampled[5:4],
^ rwds_oversampled[4:3],
^ rwds_oversampled[3:2],
^ rwds_oversampled[2:1],
^ rwds_oversampled[1:0],
rwds_oversampled[0] ^ prev_last_bit
};
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
genvar i;
wire [7:0] data_mux_0;
wire [7:0] data_mux_1;
wire [7:0] data_mux_2;
wire [7:0] data_mux_3;
wire [7:0] data_mux_4;
wire [7:0] data_mux_5;
/* Data bus states at different sample positions */
generate
for (i = 0; i < 8; i = i + 1) begin : data_sample_mux
assign data_mux_0[i] = data_pipeline[6 * i + 0];
assign data_mux_1[i] = data_pipeline[6 * i + 1];
assign data_mux_2[i] = data_pipeline[6 * i + 2];
assign data_mux_3[i] = data_pipeline[6 * i + 3];
assign data_mux_4[i] = data_pipeline[6 * i + 4];
assign data_mux_5[i] = data_pipeline[6 * i + 5];
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
reg carry;
reg [7:0] data_0;
reg [7:0] data_1;
reg [7:0] data_2;
reg [1:0] data_cnt;
/* Current process performs data bytes recovery,
* based on RWDS strobe state. At every cycle
* FSM can recover and output up to 3 bytes max */
always @(posedge clk or posedge arst) begin
if (arst) begin
carry <= 1'b0;
data_0 <= {8{1'b0}};
data_1 <= {8{1'b0}};
data_2 <= {8{1'b0}};
data_cnt <= {2{1'b0}};
rwds_error <= 1'b0;
end else begin
/* This carry flag is used to indicate that
* RWDS edge was detected at the last bit of
* the previous 6-bit sample and valid data
* should be captured at the 0-bit position
* of the current data sample */
carry <= rwds_pair_xor[5];
case (rwds_pair_xor[4:0])
5'b00000: begin
data_0 <= (carry)? data_mux_0 : data_0;
data_1 <= data_1;
data_2 <= data_2;
data_cnt <= (carry)? 2'd1 : 2'd0;
end
5'b00010: begin
data_0 <= (carry)? data_mux_0 : data_mux_2;
data_1 <= (carry)? data_mux_2 : data_1;
data_2 <= data_2;
data_cnt <= (carry)? 2'd2 : 2'd1;
end
5'b00100: begin
data_0 <= (carry)? data_mux_0 : data_mux_3;
data_1 <= (carry)? data_mux_3 : data_1;
data_2 <= data_2;
data_cnt <= (carry)? 2'd2 : 2'd1;
end
5'b01000: begin
data_0 <= (carry)? data_mux_0 : data_mux_4;
data_1 <= (carry)? data_mux_4 : data_1;
data_2 <= data_2;
data_cnt <= (carry)? 2'd2 : 2'd1;
end
5'b01010: begin
data_0 <= (carry)? data_mux_0 : data_mux_2;
data_1 <= (carry)? data_mux_2 : data_mux_4;
data_2 <= (carry)? data_mux_4 : data_2;
data_cnt <= (carry)? 2'd3 : 2'd2;
end
5'b10010: begin
data_0 <= (carry)? data_mux_0 : data_mux_2;
data_1 <= (carry)? data_mux_2 : data_mux_5;
data_2 <= (carry)? data_mux_5 : data_2;
data_cnt <= (carry)? 2'd3 : 2'd2;
end
5'b10000: begin
data_0 <= (carry)? data_mux_0 : data_mux_5;
data_1 <= (carry)? data_mux_5 : data_1;
data_2 <= data_2;
data_cnt <= (carry)? 2'd2 : 2'd1;
end
5'b10100: begin
data_0 <= (carry)? data_mux_0 : data_mux_3;
data_1 <= (carry)? data_mux_3 : data_mux_5;
data_2 <= (carry)? data_mux_5 : data_2;
data_cnt <= (carry)? 2'd3 : 2'd2;
end
5'b00001: begin
data_0 <= data_mux_1;
data_1 <= data_1;
data_2 <= data_2;
data_cnt <= 2'd1;
end
5'b00101: begin
data_0 <= data_mux_1;
data_1 <= data_mux_3;
data_2 <= data_2;
data_cnt <= 2'd2;
end
5'b01001: begin
data_0 <= data_mux_1;
data_1 <= data_mux_4;
data_2 <= data_2;
data_cnt <= 2'd2;
end
5'b10001: begin
data_0 <= data_mux_1;
data_1 <= data_mux_5;
data_2 <= data_2;
data_cnt <= 2'd2;
end
default: begin
data_0 <= data_0;
data_1 <= data_1;
data_2 <= data_2;
data_cnt <= 2'd0;
rwds_error <= 1'b1;
end
endcase
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
reg [15:0] temp;
reg [15:0] data;
reg [1:0] temp_valid;
reg data_valid;
/* As data bytes recovery FSM produces unaligned
* data stream, this FSM performs data realignment
* by repacking incoming 1-3 byte width stream into
* fixed 16-bit stream with valid strobe */
always @(posedge clk or posedge arst) begin
if (arst) begin
temp <= {16{1'b0}};
data <= {16{1'b0}};
temp_valid <= 2'b00;
data_valid <= 1'b0;
align_error <= 1'b0;
end else begin
case (data_cnt)
2'd0: begin
if (temp_valid == 2'b11) begin
data <= temp;
data_valid <= 1'b1;
temp_valid <= 2'b00;
end else begin
data_valid <= 1'b0;
end
end
2'd1: begin
case (temp_valid)
2'b00: begin
data_valid <= 1'b0;
temp[7:0] <= data_0;
temp_valid <= 2'b01;
end
2'b01: begin
data <= {data_0, temp[7:0]};
data_valid <= 1'b1;
temp_valid <= 2'b00;
end
2'b11: begin
data <= temp;
data_valid <= 1'b1;
temp[7:0] <= data_0;
temp_valid <= 2'b01;
end
default: begin
align_error <= 1'b1;
end
endcase
end
2'd2: begin
case (temp_valid)
2'b00: begin
data <= {data_1, data_0};
data_valid <= 1'b1;
temp_valid <= 2'b00;
end
2'b01: begin
data <= {data_0, temp[7:0]};
data_valid <= 1'b1;
temp[7:0] <= data_1;
temp_valid <= 2'b01;
end
2'b11: begin
data <= temp;
data_valid <= 1'b1;
temp <= {data_1, data_0};
temp_valid <= 2'b11;
end
default: begin
align_error <= 1'b1;
end
endcase
end
2'd3: begin
case (temp_valid)
2'b00: begin
data <= {data_1, data_0};
data_valid <= 1'b1;
temp[7:0] <= data_2;
temp_valid <= 2'b01;
end
2'b01: begin
data <= {data_0, temp[7:0]};
data_valid <= 1'b1;
temp <= {data_2, data_1};
temp_valid <= 2'b11;
end
default: begin
align_error <= 1'b1;
end
endcase
end
endcase
end
end
assign recov_valid = data_valid;
assign recov_data = {data[7:0], data[15:8]};
endmodule |
module hbmc_ufifo #
(
parameter integer DATA_WIDTH = 32
)
(
input wire fifo_arst,
input wire fifo_wr_clk,
input wire [15:0] fifo_wr_din,
input wire fifo_wr_last,
input wire fifo_wr_ena,
output wire fifo_wr_full,
input wire fifo_rd_clk,
output wire [DATA_WIDTH - 1:0] fifo_rd_dout,
output wire [9:0] fifo_rd_free,
output wire fifo_rd_last,
input wire fifo_rd_ena,
output wire fifo_rd_empty
);
localparam FIFO_RD_DEPTH = 512;
wire [17:0] din = {1'b0, fifo_wr_last, fifo_wr_din};
wire [8:0] fifo_rd_used;
generate
case (DATA_WIDTH)
16: begin : uFIFO_18b_18b_512w
wire [17:0] dout;
assign fifo_rd_dout = dout[15:0];
assign fifo_rd_last = dout[16];
fifo_18b_18b_512w
fifo_18b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_data_count ( fifo_rd_used ), // output [8 : 0] rd_data_count
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
32: begin : uFIFO_18b_36b_512w
wire [35:0] dout;
assign fifo_rd_dout = {dout[15:0], dout[33:18]};
assign fifo_rd_last = dout[16];
fifo_18b_36b_512w
fifo_18b_36b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_data_count ( fifo_rd_used ), // output [8 : 0] rd_data_count
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [35 : 0] dout
);
end
/*--------------------------------------------------------------------*/
64: begin : uFIFO_18b_72b_512w
wire [71:0] dout;
assign fifo_rd_dout = {dout[15:0], dout[33:18], dout[51:36], dout[69:54]};
assign fifo_rd_last = dout[16];
fifo_18b_72b_512w
fifo_18b_72b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_data_count ( fifo_rd_used ), // output [8 : 0] rd_data_count
.rd_en ( fifo_rd_ena ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [71 : 0] dout
);
end
/*--------------------------------------------------------------------*/
default: begin
INVALID_PARAMETER invalid_parameter_msg();
end
endcase
endgenerate
assign fifo_rd_free = FIFO_RD_DEPTH - fifo_rd_used;
endmodule |
module hbmc_bus_sync #
(
parameter integer C_SYNC_STAGES = 3,
parameter integer C_DATA_WIDTH = 8
)
(
input wire src_clk,
input wire src_rst,
input wire [C_DATA_WIDTH - 1 : 0] src_data,
input wire src_req,
output wire src_ack,
input wire dst_clk,
input wire dst_rst,
output reg [C_DATA_WIDTH - 1 : 0] dst_data,
output reg dst_req,
input wire dst_ack
);
/*----------------------------------------------------------------------------------------------------------------------------*/
wire src_req_sync;
hbmc_bit_sync #
(
.C_SYNC_STAGES ( C_SYNC_STAGES ),
.C_RESET_STATE ( 1'b0 )
)
hbmc_bit_sync_inst_0
(
.arst ( dst_rst ),
.clk ( dst_clk ),
.d ( src_req ),
.q ( src_req_sync )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
reg src_ack_async;
hbmc_bit_sync #
(
.C_SYNC_STAGES ( C_SYNC_STAGES ),
.C_RESET_STATE ( 1'b0 )
)
hbmc_bit_sync_inst_1
(
.arst ( src_rst ),
.clk ( src_clk ),
.d ( src_ack_async ),
.q ( src_ack )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam ST_GET = 1'b0,
ST_SET = 1'b1;
reg state;
always @(posedge dst_clk or posedge dst_rst) begin
if (dst_rst) begin
src_ack_async <= 1'b0;
dst_req <= 1'b0;
dst_data <= {C_DATA_WIDTH{1'b0}};
state <= ST_GET;
end else begin
case (state)
ST_GET: begin
if (src_req_sync & ~dst_ack) begin
src_ack_async <= 1'b1;
dst_req <= 1'b1;
dst_data <= src_data;
state <= ST_SET;
end
end
ST_SET: begin
if (dst_ack) begin
dst_req <= 1'b0;
end
if (~src_req_sync) begin
src_ack_async <= 1'b0;
end
if (~dst_req & ~src_ack_async) begin
state <= ST_GET;
end
end
endcase
end
end
endmodule |
module hbmc_axi_top #
(
parameter integer C_S_AXI_ID_WIDTH = 1,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 32,
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_WUSER_WIDTH = 0,
parameter integer C_S_AXI_RUSER_WIDTH = 0,
parameter integer C_S_AXI_BUSER_WIDTH = 0,
parameter integer C_HBMC_CLOCK_HZ = 166000000,
parameter integer C_HBMC_FPGA_DRIVE_STRENGTH = 8,
parameter C_HBMC_FPGA_SLEW_RATE = "SLOW",
parameter integer C_HBMC_MEM_DRIVE_STRENGTH = 46,
parameter integer C_HBMC_CS_MAX_LOW_TIME_US = 4,
parameter C_HBMC_FIXED_LATENCY = 0,
parameter integer C_ISERDES_CLOCKING_MODE = 0,
parameter C_IDELAYCTRL_INTEGRATED = 0,
parameter C_IODELAY_GROUP_ID = "HBMC",
parameter real C_IODELAY_REFCLK_MHZ = 200.0,
parameter C_RWDS_USE_IDELAY = 0,
parameter C_DQ7_USE_IDELAY = 0,
parameter C_DQ6_USE_IDELAY = 0,
parameter C_DQ5_USE_IDELAY = 0,
parameter C_DQ4_USE_IDELAY = 0,
parameter C_DQ3_USE_IDELAY = 0,
parameter C_DQ2_USE_IDELAY = 0,
parameter C_DQ1_USE_IDELAY = 0,
parameter C_DQ0_USE_IDELAY = 0,
parameter [4:0] C_RWDS_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ7_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ6_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ5_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ4_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ3_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ2_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ1_IDELAY_TAPS_VALUE = 0,
parameter [4:0] C_DQ0_IDELAY_TAPS_VALUE = 0
)
(
input wire clk_hbmc_0,
input wire clk_hbmc_90,
input wire clk_iserdes,
input wire clk_idelay_ref,
input wire s_axi_aclk,
input wire s_axi_aresetn,
/* AXI4 Slave Interface Write Address Ports */
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, // unused
input wire s_axi_awlock, // unused
input wire [3:0] s_axi_awregion, // unused
input wire [3:0] s_axi_awcache, // unused
input wire [3:0] s_axi_awqos, // unused
input wire [2:0] s_axi_awprot, // unused
input wire s_axi_awvalid,
output reg s_axi_awready,
/* AXI4 Slave Interface Write Data Ports */
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser, // unused
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
/* AXI4 Slave Interface Write Response Ports */
output reg [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser, // unused
output wire [1:0] s_axi_bresp,
output reg s_axi_bvalid,
input wire s_axi_bready,
/* AXI4 Interface Read Address Ports */
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, // unused
input wire s_axi_arlock, // unused
input wire [3:0] s_axi_arregion, // unused
input wire [3:0] s_axi_arcache, // unused
input wire [3:0] s_axi_arqos, // unused
input wire [2:0] s_axi_arprot, // unused
input wire s_axi_arvalid,
output reg s_axi_arready,
/* AXI4 Slave Interface Read Data Ports */
output reg [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser, // unused
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
/* HyperBus Interface Port */
output wire hb_ck_p,
output wire hb_ck_n,
output wire hb_reset_n,
output wire hb_cs_n,
inout wire hb_rwds,
inout wire [7:0] hb_dq
);
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Checking input parameters */
generate
/* Supported AXI4 data bus width is 16/32/64 bit only. */
if ((C_S_AXI_DATA_WIDTH != 16) && (C_S_AXI_DATA_WIDTH != 32) && (C_S_AXI_DATA_WIDTH != 64)) begin
INVALID_PARAMETER invalid_parameter_msg();
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
function integer clog2;
input integer value;
integer temp;
begin
temp = value;
for (clog2 = 0; temp > 1; clog2 = clog2 + 1) begin
temp = temp >> 1;
end
end
endfunction
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam [C_S_AXI_ADDR_WIDTH - 1:0] AXI_ADDR_ALIGN_MASK = (C_S_AXI_DATA_WIDTH == 16)? {{C_S_AXI_ADDR_WIDTH - 1{1'b1}}, {1{1'b0}}} :
(C_S_AXI_DATA_WIDTH == 32)? {{C_S_AXI_ADDR_WIDTH - 2{1'b1}}, {2{1'b0}}} :
(C_S_AXI_DATA_WIDTH == 64)? {{C_S_AXI_ADDR_WIDTH - 3{1'b1}}, {3{1'b0}}} : {C_S_AXI_ADDR_WIDTH{1'b1}};
localparam AXI_FIXD_BURST = 2'b00,
AXI_INCR_BURST = 2'b01,
AXI_WRAP_BURST = 2'b10;
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
localparam NO_REQ = 2'b00,
WR_REQ = 2'b01,
RD_REQ = 2'b10,
WR_RD_REQ = 2'b11;
/*----------------------------------------------------------------------------------------------------------------------------*/
reg s_axi_areset;
wire idelayctrl_rdy_sync;
wire clk_idelay;
/* HBMC command interface */
reg cmd_req;
reg [31:0] cmd_mem_addr;
reg [15:0] cmd_word_cnt;
reg cmd_wr_not_rd;
reg cmd_wrap_not_incr;
wire cmd_ack;
/* Transfer state flags */
reg wr_xfer_done;
reg rd_xfer_done;
reg [11:0] wr_data_pkt_cnt;
wire rd_addr_done = s_axi_arvalid & s_axi_arready;
wire rd_data_done = s_axi_rvalid & s_axi_rready & s_axi_rlast;
wire wr_addr_done = s_axi_awvalid & s_axi_awready;
wire wr_data_done = s_axi_wvalid & s_axi_wready & s_axi_wlast;
wire wr_resp_done = s_axi_bvalid & s_axi_bready;
wire wr_data_pending = (wr_data_pkt_cnt > {12{1'b0}});
wire axi_wr_condition = s_axi_awvalid & wr_xfer_done & wr_data_pending;
wire axi_rd_condition = s_axi_arvalid & rd_xfer_done;
/* Upstream FIFO wires */
wire [15:0] ufifo_wr_data;
wire ufifo_wr_last;
wire ufifo_wr_ena;
wire [C_S_AXI_DATA_WIDTH-1:0] ufifo_rd_dout;
wire [9:0] ufifo_rd_free;
wire ufifo_rd_last;
wire ufifo_rd_ena = s_axi_rvalid & s_axi_rready;
wire ufifo_rd_empty;
/* Downstream FIFO wires */
wire [15:0] dfifo_rd_data;
wire [1:0] dfifo_rd_strb;
wire dfifo_rd_ena;
wire [C_S_AXI_DATA_WIDTH-1:0] dfifo_wr_din = s_axi_wdata;
wire [C_S_AXI_DATA_WIDTH/8-1:0] dfifo_wr_strb = s_axi_wstrb;
wire dfifo_wr_ena = s_axi_wvalid & s_axi_wready;
wire dfifo_wr_full;
wire [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr_aligned = s_axi_awaddr & AXI_ADDR_ALIGN_MASK;
wire [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr_aligned = s_axi_araddr & AXI_ADDR_ALIGN_MASK;
assign s_axi_rresp = AXI_RESP_OKAY;
assign s_axi_rdata = ufifo_rd_dout;
assign s_axi_rlast = ufifo_rd_last;
assign s_axi_rvalid = ~ufifo_rd_empty;
assign s_axi_wready = ~dfifo_wr_full;
assign s_axi_bresp = AXI_RESP_OKAY;
generate
if (C_S_AXI_BUSER_WIDTH > 0) begin
assign s_axi_buser = {C_S_AXI_BUSER_WIDTH{1'b0}};
assign s_axi_ruser = {C_S_AXI_RUSER_WIDTH{1'b0}};
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
/* AXI active low polarity reset inversion.
* Positive reset polarity removes useless
* LUT-based reset inverters, as all FPGA's
* primitives have positive reset polarity.
* This also improves timings. */
always @(posedge s_axi_aclk or negedge s_axi_aresetn) begin
if (~s_axi_aresetn) begin
s_axi_areset <= 1'b1;
end else begin
s_axi_areset <= 1'b0;
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
generate
if (C_IDELAYCTRL_INTEGRATED) begin
wire idelayctrl_rdy;
wire idelayctrl_rst;
hbmc_arst_sync #
(
/* Current module requires min
* 60ns of reset pulse width,
* 32 stage synchronizer will
* be enough for AXI clock
* frequencies < 500MHz */
.C_SYNC_STAGES ( 32 )
)
hbmc_arst_sync_idelayctrl
(
.clk ( s_axi_aclk ),
.arst ( s_axi_areset ),
.rst ( idelayctrl_rst )
);
(* IODELAY_GROUP = C_IODELAY_GROUP_ID *)
IDELAYCTRL
IDELAYCTRL_inst
(
.RST ( idelayctrl_rst ),
.REFCLK ( clk_idelay_ref ),
.RDY ( idelayctrl_rdy )
);
hbmc_bit_sync #
(
.C_SYNC_STAGES ( 3 ),
.C_RESET_STATE ( 1'b0 )
)
hbmc_bit_sync_idelayctrl_rdy
(
.arst ( s_axi_areset ),
.clk ( s_axi_aclk ),
.d ( idelayctrl_rdy ),
.q ( idelayctrl_rdy_sync )
);
assign clk_idelay = clk_idelay_ref;
end else begin
assign idelayctrl_rdy_sync = 1'b1;
assign clk_idelay = 1'b0;
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
task hbmc_config_wr_cmd;
begin
cmd_wr_not_rd <= 1'b1;
cmd_mem_addr <= (C_S_AXI_ADDR_WIDTH <= 32)? {{32 - C_S_AXI_ADDR_WIDTH + 1{1'b0}}, axi_awaddr_aligned[C_S_AXI_ADDR_WIDTH - 1:1]} :
axi_awaddr_aligned[32:1];
cmd_word_cnt <= (s_axi_awlen + 1'b1) << (clog2(C_S_AXI_DATA_WIDTH/8) - 1);
cmd_wrap_not_incr <= (s_axi_awburst == AXI_WRAP_BURST)? 1'b1 : 1'b0;
end
endtask
task hbmc_config_rd_cmd;
begin
cmd_wr_not_rd <= 1'b0;
cmd_mem_addr <= (C_S_AXI_ADDR_WIDTH <= 32)? {{32 - C_S_AXI_ADDR_WIDTH + 1{1'b0}}, axi_araddr_aligned[C_S_AXI_ADDR_WIDTH - 1:1]} :
axi_araddr_aligned[32:1];
cmd_word_cnt <= (s_axi_arlen + 1'b1) << (clog2(C_S_AXI_DATA_WIDTH/8) - 1);
cmd_wrap_not_incr <= (s_axi_arburst == AXI_WRAP_BURST)? 1'b1 : 1'b0;
end
endtask
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam ST_RST = 2'd0,
ST_XFER_SEL = 2'd1,
ST_XFER_INIT = 2'd2,
ST_XFER_RUN = 2'd3;
reg [1:0] state;
/* Main transaction processing FSM */
always @(posedge s_axi_aclk or posedge s_axi_areset) begin
if (s_axi_areset) begin
cmd_req <= 1'b0;
cmd_wr_not_rd <= 1'b0;
cmd_mem_addr <= {32{1'b0}};
cmd_word_cnt <= {16{1'b0}};
cmd_wrap_not_incr <= 1'b0;
s_axi_awready <= 1'b0;
s_axi_arready <= 1'b0;
s_axi_rid <= {C_S_AXI_ID_WIDTH{1'b0}};
s_axi_bid <= {C_S_AXI_ID_WIDTH{1'b0}};
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
cmd_req <= 1'b0;
s_axi_awready <= 1'b0;
s_axi_arready <= 1'b0;
if (idelayctrl_rdy_sync) begin
state <= ST_XFER_SEL;
end
end
ST_XFER_SEL: begin
case ({axi_rd_condition, axi_wr_condition})
/* Do nothing */
NO_REQ: begin
state <= state;
end
/* New AXI write request */
WR_REQ: begin
s_axi_awready <= 1'b1;
s_axi_bid <= s_axi_awid;
hbmc_config_wr_cmd();
state <= ST_XFER_INIT;
end
/* New AXI read request */
RD_REQ: begin
s_axi_arready <= 1'b1;
s_axi_rid <= s_axi_arid;
hbmc_config_rd_cmd();
state <= ST_XFER_INIT;
end
/* Simultaneous AXI write + read request */
WR_RD_REQ: begin
/* Simple round-robin, based
* on the previous operation */
if (cmd_wr_not_rd) begin
s_axi_arready <= 1'b1;
s_axi_rid <= s_axi_arid;
hbmc_config_rd_cmd();
end else begin
s_axi_awready <= 1'b1;
s_axi_bid <= s_axi_awid;
hbmc_config_wr_cmd();
end
state <= ST_XFER_INIT;
end
endcase
end
ST_XFER_INIT: begin
s_axi_awready <= 1'b0;
s_axi_arready <= 1'b0;
if (~cmd_ack) begin
cmd_req <= 1'b1;
state <= ST_XFER_RUN;
end
end
ST_XFER_RUN: begin
if (cmd_ack) begin
cmd_req <= 1'b0;
state <= ST_XFER_SEL;
end
end
endcase
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Checking AXI read transfer state */
always @(posedge s_axi_aclk or posedge s_axi_areset) begin
if (s_axi_areset) begin
rd_xfer_done <= 1'b1;
end else begin
if (rd_addr_done) begin
rd_xfer_done <= 1'b0;
end else begin
if (rd_data_done) begin
rd_xfer_done <= 1'b1;
end
end
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Pending AXI write data packets counter */
always @(posedge s_axi_aclk or posedge s_axi_areset) begin
if (s_axi_areset) begin
wr_data_pkt_cnt <= {12{1'b0}};
end else begin
case ({wr_resp_done, wr_data_done})
2'b00,
2'b11: wr_data_pkt_cnt <= wr_data_pkt_cnt;
2'b01: wr_data_pkt_cnt <= wr_data_pkt_cnt + 1'b1;
2'b10: wr_data_pkt_cnt <= wr_data_pkt_cnt - 1'b1;
endcase
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam ST_BRESP_IDLE = 1'b0,
ST_BRESP_SEND = 1'b1;
reg state_bresp;
/* AXI write responding FSM */
always @(posedge s_axi_aclk or posedge s_axi_areset) begin
if (s_axi_areset) begin
wr_xfer_done <= 1'b1;
s_axi_bvalid <= 1'b0;
state_bresp <= ST_BRESP_IDLE;
end else begin
case (state_bresp)
ST_BRESP_IDLE: begin
/* Start responding when AW was accepted and
* there is pending write data packet in dFIFO */
if (wr_addr_done & wr_data_pending) begin
wr_xfer_done <= 1'b0;
s_axi_bvalid <= 1'b1;
state_bresp <= ST_BRESP_SEND;
end
end
ST_BRESP_SEND: begin
if (wr_resp_done) begin
wr_xfer_done <= 1'b1;
s_axi_bvalid <= 1'b0;
state_bresp <= ST_BRESP_IDLE;
end
end
endcase
end
end
/*----------------------------------------------------------------------------------------------------------------------------*/
wire hbmc_rst_sync;
hbmc_arst_sync #
(
.C_SYNC_STAGES ( 3 )
)
hbmc_arst_sync_inst
(
.clk ( clk_hbmc_0 ),
.arst ( s_axi_areset ),
.rst ( hbmc_rst_sync )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam BUS_SYNC_WIDTH = 32 + 16 + 1 + 1;
wire cmd_req_dst;
wire cmd_ack_dst;
wire [31:0] cmd_mem_addr_dst;
wire [15:0] cmd_word_cnt_dst;
wire cmd_wr_not_rd_dst;
wire cmd_wrap_not_incr_dst;
wire [BUS_SYNC_WIDTH - 1:0] src_data;
wire [BUS_SYNC_WIDTH - 1:0] dst_data;
assign src_data = {cmd_mem_addr, cmd_word_cnt, cmd_wr_not_rd, cmd_wrap_not_incr};
assign {cmd_mem_addr_dst, cmd_word_cnt_dst, cmd_wr_not_rd_dst, cmd_wrap_not_incr_dst} = dst_data;
hbmc_bus_sync #
(
.C_SYNC_STAGES ( 3 ),
.C_DATA_WIDTH ( BUS_SYNC_WIDTH )
)
hbmc_bus_sync_inst
(
.src_clk ( s_axi_aclk ),
.src_rst ( s_axi_areset ),
.src_data ( src_data ),
.src_req ( cmd_req ),
.src_ack ( cmd_ack ),
.dst_clk ( clk_hbmc_0 ),
.dst_rst ( hbmc_rst_sync ),
.dst_data ( dst_data ),
.dst_req ( cmd_req_dst ),
.dst_ack ( cmd_ack_dst )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
hbmc_ctrl #
(
.C_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ),
.C_HBMC_CLOCK_HZ ( C_HBMC_CLOCK_HZ ),
.C_HBMC_FPGA_DRIVE_STRENGTH ( C_HBMC_FPGA_DRIVE_STRENGTH ),
.C_HBMC_FPGA_SLEW_RATE ( C_HBMC_FPGA_SLEW_RATE ),
.C_HBMC_MEM_DRIVE_STRENGTH ( C_HBMC_MEM_DRIVE_STRENGTH ),
.C_HBMC_CS_MAX_LOW_TIME_US ( C_HBMC_CS_MAX_LOW_TIME_US ),
.C_HBMC_FIXED_LATENCY ( C_HBMC_FIXED_LATENCY ),
.C_ISERDES_CLOCKING_MODE ( C_ISERDES_CLOCKING_MODE ),
.C_IODELAY_GROUP_ID ( C_IODELAY_GROUP_ID ),
.C_IODELAY_REFCLK_MHZ ( C_IODELAY_REFCLK_MHZ ),
.C_RWDS_USE_IDELAY ( C_RWDS_USE_IDELAY ),
.C_DQ7_USE_IDELAY ( C_DQ7_USE_IDELAY ),
.C_DQ6_USE_IDELAY ( C_DQ6_USE_IDELAY ),
.C_DQ5_USE_IDELAY ( C_DQ5_USE_IDELAY ),
.C_DQ4_USE_IDELAY ( C_DQ4_USE_IDELAY ),
.C_DQ3_USE_IDELAY ( C_DQ3_USE_IDELAY ),
.C_DQ2_USE_IDELAY ( C_DQ2_USE_IDELAY ),
.C_DQ1_USE_IDELAY ( C_DQ1_USE_IDELAY ),
.C_DQ0_USE_IDELAY ( C_DQ0_USE_IDELAY ),
.C_RWDS_IDELAY_TAPS_VALUE ( C_RWDS_IDELAY_TAPS_VALUE ),
.C_DQ7_IDELAY_TAPS_VALUE ( C_DQ7_IDELAY_TAPS_VALUE ),
.C_DQ6_IDELAY_TAPS_VALUE ( C_DQ6_IDELAY_TAPS_VALUE ),
.C_DQ5_IDELAY_TAPS_VALUE ( C_DQ5_IDELAY_TAPS_VALUE ),
.C_DQ4_IDELAY_TAPS_VALUE ( C_DQ4_IDELAY_TAPS_VALUE ),
.C_DQ3_IDELAY_TAPS_VALUE ( C_DQ3_IDELAY_TAPS_VALUE ),
.C_DQ2_IDELAY_TAPS_VALUE ( C_DQ2_IDELAY_TAPS_VALUE ),
.C_DQ1_IDELAY_TAPS_VALUE ( C_DQ1_IDELAY_TAPS_VALUE ),
.C_DQ0_IDELAY_TAPS_VALUE ( C_DQ0_IDELAY_TAPS_VALUE )
)
hbmc_ctrl_inst
(
.rst ( hbmc_rst_sync ),
.clk_hbmc_0 ( clk_hbmc_0 ),
.clk_hbmc_90 ( clk_hbmc_90 ),
.clk_iserdes ( clk_iserdes ),
.clk_idelay_ref ( clk_idelay ),
.cmd_valid ( cmd_req_dst ),
.cmd_ready ( cmd_ack_dst ),
.cmd_mem_addr ( cmd_mem_addr_dst ),
.cmd_word_count ( cmd_word_cnt_dst ),
.cmd_wr_not_rd ( cmd_wr_not_rd_dst ),
.cmd_wrap_not_incr ( cmd_wrap_not_incr_dst ),
.ufifo_data ( ufifo_wr_data ),
.ufifo_last ( ufifo_wr_last ),
.ufifo_we ( ufifo_wr_ena ),
.dfifo_data ( dfifo_rd_data ),
.dfifo_strb ( dfifo_rd_strb ),
.dfifo_re ( dfifo_rd_ena ),
.hb_ck_p ( hb_ck_p ),
.hb_ck_n ( hb_ck_n ),
.hb_reset_n ( hb_reset_n ),
.hb_cs_n ( hb_cs_n ),
.hb_rwds ( hb_rwds ),
.hb_dq ( hb_dq )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Upstream data FIFO */
hbmc_ufifo #
(
.DATA_WIDTH ( C_S_AXI_DATA_WIDTH )
)
hbmc_ufifo_inst
(
.fifo_arst ( s_axi_areset ),
.fifo_wr_clk ( clk_hbmc_0 ),
.fifo_wr_din ( ufifo_wr_data ),
.fifo_wr_last ( ufifo_wr_last ),
.fifo_wr_ena ( ufifo_wr_ena ),
.fifo_wr_full ( /*----NC----*/ ),
.fifo_rd_clk ( s_axi_aclk ),
.fifo_rd_dout ( ufifo_rd_dout ),
.fifo_rd_free ( /*----NC----*/ ),
.fifo_rd_last ( ufifo_rd_last ),
.fifo_rd_ena ( ufifo_rd_ena ),
.fifo_rd_empty ( ufifo_rd_empty )
);
/*----------------------------------------------------------------------------------------------------------------------------*/
/* Downstream data FIFO */
hbmc_dfifo #
(
.DATA_WIDTH ( C_S_AXI_DATA_WIDTH )
)
hbmc_dfifo_inst
(
.fifo_arst ( s_axi_areset ),
.fifo_wr_clk ( s_axi_aclk ),
.fifo_wr_din ( dfifo_wr_din ),
.fifo_wr_strb ( dfifo_wr_strb ),
.fifo_wr_ena ( dfifo_wr_ena ),
.fifo_wr_full ( dfifo_wr_full ),
.fifo_rd_clk ( clk_hbmc_0 ),
.fifo_rd_dout ( dfifo_rd_data ),
.fifo_rd_strb ( dfifo_rd_strb ),
.fifo_rd_ena ( dfifo_rd_ena ),
.fifo_rd_empty ( /*----NC----*/ )
);
endmodule |
module hbmc_arst_sync #
(
parameter integer C_SYNC_STAGES = 3
)
(
input wire clk,
input wire arst,
output wire rst
);
hbmc_bit_sync #
(
.C_SYNC_STAGES ( C_SYNC_STAGES ),
.C_RESET_STATE ( 1'b1 )
)
hbmc_bit_sync_inst
(
.arst ( arst ),
.clk ( clk ),
.d ( 1'b0 ),
.q ( rst )
);
endmodule |
module top
(
input wire clkin,
output wire hram_r0_ck_p,
output wire hram_r0_ck_n,
output wire hram_r0_reset_n,
output wire hram_r0_cs_n,
inout wire hram_r0_rwds,
inout wire [7:0] hram_r0_dq,
output wire hram_r1_ck_p,
output wire hram_r1_ck_n,
output wire hram_r1_reset_n,
output wire hram_r1_cs_n,
inout wire hram_r1_rwds,
inout wire [7:0] hram_r1_dq
);
/*----------------------------------------------------------------------------------------------------------------------------*/
localparam HYPERRAM_CLOCKING_MODE = "BUFIO"; // "BUFG"
generate
case (HYPERRAM_CLOCKING_MODE)
"BUFG": begin : bufg_mode
SoC_bufg
SoC_bufg_inst
(
.clkin ( clkin ),
.resetn ( 1'b1 ),
.HyperBus_R0_hb_ck_p ( hram_r0_ck_p ),
.HyperBus_R0_hb_ck_n ( hram_r0_ck_n ),
.HyperBus_R0_hb_cs_n ( hram_r0_cs_n ),
.HyperBus_R0_hb_dq ( hram_r0_dq ),
.HyperBus_R0_hb_reset_n ( hram_r0_reset_n ),
.HyperBus_R0_hb_rwds ( hram_r0_rwds ),
.HyperBus_R1_hb_ck_p ( hram_r1_ck_p ),
.HyperBus_R1_hb_ck_n ( hram_r1_ck_n ),
.HyperBus_R1_hb_cs_n ( hram_r1_cs_n ),
.HyperBus_R1_hb_dq ( hram_r1_dq ),
.HyperBus_R1_hb_reset_n ( hram_r1_reset_n ),
.HyperBus_R1_hb_rwds ( hram_r1_rwds )
);
end
"BUFIO": begin : bufio_mode
SoC_bufio
SoC_bufio_inst
(
.clkin ( clkin ),
.resetn ( 1'b1 ),
.HyperBus_R0_hb_ck_p ( hram_r0_ck_p ),
.HyperBus_R0_hb_ck_n ( hram_r0_ck_n ),
.HyperBus_R0_hb_cs_n ( hram_r0_cs_n ),
.HyperBus_R0_hb_dq ( hram_r0_dq ),
.HyperBus_R0_hb_reset_n ( hram_r0_reset_n ),
.HyperBus_R0_hb_rwds ( hram_r0_rwds ),
.HyperBus_R1_hb_ck_p ( hram_r1_ck_p ),
.HyperBus_R1_hb_ck_n ( hram_r1_ck_n ),
.HyperBus_R1_hb_cs_n ( hram_r1_cs_n ),
.HyperBus_R1_hb_dq ( hram_r1_dq ),
.HyperBus_R1_hb_reset_n ( hram_r1_reset_n ),
.HyperBus_R1_hb_rwds ( hram_r1_rwds )
);
end
default: begin : check_parameters
INVALID_PARAMETER invalid_parameter_msg();
end
endcase
endgenerate
endmodule |
module top
(
input wire clkin,
output wire hram_ck_p,
output wire hram_ck_n,
output wire hram_reset_n,
output wire hram_cs_n,
inout wire hram_rwds,
inout wire [7:0] hram_dq
);
/*----------------------------------------------------------------------------------------------------------------------------*/
SoC
SoC_inst
(
.clkin ( clkin ),
.resetn ( 1'b1 ),
.HyperBus_hb_ck_p ( hram_ck_p ),
.HyperBus_hb_ck_n ( hram_ck_n ),
.HyperBus_hb_cs_n ( hram_cs_n ),
.HyperBus_hb_dq ( hram_dq ),
.HyperBus_hb_reset_n ( hram_reset_n ),
.HyperBus_hb_rwds ( hram_rwds )
);
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
picorv32 #(
.BARREL_SHIFTER(1),
.ENABLE_FAST_MUL(1),
.ENABLE_DIV(1),
.PROGADDR_RESET('h10000),
.STACKADDR('h10000)
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg [7:0] memory [0:256*1024-1];
initial $readmemh("dhry.hex", memory);
always @(posedge clk) begin
mem_ready <= 1'b0;
mem_rdata[ 7: 0] <= 'bx;
mem_rdata[15: 8] <= 'bx;
mem_rdata[23:16] <= 'bx;
mem_rdata[31:24] <= 'bx;
if (mem_valid & !mem_ready) begin
if (|mem_wstrb) begin
mem_ready <= 1'b1;
case (mem_addr)
32'h1000_0000: begin
$write("%c", mem_wdata);
$fflush();
end
default: begin
if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
end
endcase
end
else begin
mem_ready <= 1'b1;
mem_rdata[ 7: 0] <= memory[mem_addr + 0];
mem_rdata[15: 8] <= memory[mem_addr + 1];
mem_rdata[23:16] <= memory[mem_addr + 2];
mem_rdata[31:24] <= memory[mem_addr + 3];
end
end
end
initial begin
$dumpfile("testbench_nola.vcd");
$dumpvars(0, testbench);
end
always @(posedge clk) begin
if (resetn && trap) begin
repeat (10) @(posedge clk);
$display("TRAP");
$finish;
end
end
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
wire mem_la_read;
wire mem_la_write;
wire [31:0] mem_la_addr;
wire [31:0] mem_la_wdata;
wire [3:0] mem_la_wstrb;
wire trace_valid;
wire [35:0] trace_data;
picorv32 #(
.BARREL_SHIFTER(1),
.ENABLE_FAST_MUL(1),
.ENABLE_DIV(1),
.PROGADDR_RESET('h10000),
.STACKADDR('h10000),
.ENABLE_TRACE(1)
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.mem_la_read (mem_la_read ),
.mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr ),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb),
.trace_valid (trace_valid),
.trace_data (trace_data )
);
reg [7:0] memory [0:256*1024-1];
initial $readmemh("dhry.hex", memory);
assign mem_ready = 1;
always @(posedge clk) begin
mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx;
mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx;
mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx;
mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx;
if (mem_la_write) begin
case (mem_la_addr)
32'h1000_0000: begin
`ifndef TIMING
$write("%c", mem_la_wdata);
$fflush();
`endif
end
default: begin
if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0];
if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8];
if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16];
if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24];
end
endcase
end
end
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
always @(posedge clk) begin
if (resetn && trap) begin
repeat (10) @(posedge clk);
$display("TRAP");
$finish;
end
end
`ifdef TIMING
initial begin
repeat (100000) @(posedge clk);
$finish;
end
always @(posedge clk) begin
if (uut.dbg_next)
$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "pcpi", uut.count_cycle);
end
`endif
endmodule |
module testbench;
reg clk;
always #5 clk = (clk === 1'b0);
localparam ser_half_period = 53;
event ser_sample;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
repeat (6) begin
repeat (50000) @(posedge clk);
$display("+50000 cycles");
end
$finish;
end
integer cycle_cnt = 0;
always @(posedge clk) begin
cycle_cnt <= cycle_cnt + 1;
end
wire [7:0] leds;
wire ser_rx;
wire ser_tx;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire flash_io2;
wire flash_io3;
always @(leds) begin
#1 $display("%b", leds);
end
hx8kdemo uut (
.clk (clk ),
.leds (leds ),
.ser_rx (ser_rx ),
.ser_tx (ser_tx ),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.flash_io2(flash_io2),
.flash_io3(flash_io3)
);
spiflash spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(flash_io2),
.io3(flash_io3)
);
reg [7:0] buffer;
always begin
@(negedge ser_tx);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // start bit
repeat (8) begin
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
buffer = {ser_tx, buffer[7:1]};
-> ser_sample; // data bit
end
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // stop bit
if (buffer < 32 || buffer >= 127)
$display("Serial data: %d", buffer);
else
$display("Serial data: '%c'", buffer);
end
endmodule |
module spiflash (
input csb,
input clk,
inout io0, // MOSI
inout io1, // MISO
inout io2,
inout io3
);
localparam verbose = 0;
localparam integer latency = 8;
reg [7:0] buffer;
integer bitcount = 0;
integer bytecount = 0;
integer dummycount = 0;
reg [7:0] spi_cmd;
reg [7:0] xip_cmd = 0;
reg [23:0] spi_addr;
reg [7:0] spi_in;
reg [7:0] spi_out;
reg spi_io_vld;
reg powered_up = 0;
localparam [3:0] mode_spi = 1;
localparam [3:0] mode_dspi_rd = 2;
localparam [3:0] mode_dspi_wr = 3;
localparam [3:0] mode_qspi_rd = 4;
localparam [3:0] mode_qspi_wr = 5;
localparam [3:0] mode_qspi_ddr_rd = 6;
localparam [3:0] mode_qspi_ddr_wr = 7;
reg [3:0] mode = 0;
reg [3:0] next_mode = 0;
reg io0_oe = 0;
reg io1_oe = 0;
reg io2_oe = 0;
reg io3_oe = 0;
reg io0_dout = 0;
reg io1_dout = 0;
reg io2_dout = 0;
reg io3_dout = 0;
assign #1 io0 = io0_oe ? io0_dout : 1'bz;
assign #1 io1 = io1_oe ? io1_dout : 1'bz;
assign #1 io2 = io2_oe ? io2_dout : 1'bz;
assign #1 io3 = io3_oe ? io3_dout : 1'bz;
wire io0_delayed;
wire io1_delayed;
wire io2_delayed;
wire io3_delayed;
assign #1 io0_delayed = io0;
assign #1 io1_delayed = io1;
assign #1 io2_delayed = io2;
assign #1 io3_delayed = io3;
// 16 MB (128Mb) Flash
reg [7:0] memory [0:16*1024*1024-1];
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware.hex";
$readmemh(firmware_file, memory);
end
task spi_action;
begin
spi_in = buffer;
if (bytecount == 1) begin
spi_cmd = buffer;
if (spi_cmd == 8'h ab)
powered_up = 1;
if (spi_cmd == 8'h b9)
powered_up = 0;
if (spi_cmd == 8'h ff)
xip_cmd = 0;
end
if (powered_up && spi_cmd == 'h 03) begin
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount >= 4) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h bb) begin
if (bytecount == 1)
mode = mode_dspi_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_dspi_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h eb) begin
if (bytecount == 1)
mode = mode_qspi_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_qspi_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
if (powered_up && spi_cmd == 'h ed) begin
if (bytecount == 1)
next_mode = mode_qspi_ddr_rd;
if (bytecount == 2)
spi_addr[23:16] = buffer;
if (bytecount == 3)
spi_addr[15:8] = buffer;
if (bytecount == 4)
spi_addr[7:0] = buffer;
if (bytecount == 5) begin
xip_cmd = (buffer == 8'h a5) ? spi_cmd : 8'h 00;
mode = mode_qspi_ddr_wr;
dummycount = latency;
end
if (bytecount >= 5) begin
buffer = memory[spi_addr];
spi_addr = spi_addr + 1;
end
end
spi_out = buffer;
spi_io_vld = 1;
if (verbose) begin
if (bytecount == 1)
$write("<SPI-START>");
$write("<SPI:%02x:%02x>", spi_in, spi_out);
end
end
endtask
task ddr_rd_edge;
begin
buffer = {buffer, io3_delayed, io2_delayed, io1_delayed, io0_delayed};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
endtask
task ddr_wr_edge;
begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
buffer = {buffer, 4'h 0};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
endtask
always @(csb) begin
if (csb) begin
if (verbose) begin
$display("");
$fflush;
end
buffer = 0;
bitcount = 0;
bytecount = 0;
mode = mode_spi;
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end else
if (xip_cmd) begin
buffer = xip_cmd;
bitcount = 0;
bytecount = 1;
spi_action;
end
end
always @(csb, clk) begin
spi_io_vld = 0;
if (!csb && !clk) begin
if (dummycount > 0) begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end else
case (mode)
mode_spi: begin
io0_oe = 0;
io1_oe = 1;
io2_oe = 0;
io3_oe = 0;
io1_dout = buffer[7];
end
mode_dspi_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_dspi_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 0;
io3_oe = 0;
io0_dout = buffer[6];
io1_dout = buffer[7];
end
mode_qspi_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_qspi_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
end
mode_qspi_ddr_rd: begin
ddr_rd_edge;
end
mode_qspi_ddr_wr: begin
ddr_wr_edge;
end
endcase
if (next_mode) begin
case (next_mode)
mode_qspi_ddr_rd: begin
io0_oe = 0;
io1_oe = 0;
io2_oe = 0;
io3_oe = 0;
end
mode_qspi_ddr_wr: begin
io0_oe = 1;
io1_oe = 1;
io2_oe = 1;
io3_oe = 1;
io0_dout = buffer[4];
io1_dout = buffer[5];
io2_dout = buffer[6];
io3_dout = buffer[7];
end
endcase
mode = next_mode;
next_mode = 0;
end
end
end
always @(posedge clk) begin
if (!csb) begin
if (dummycount > 0) begin
dummycount = dummycount - 1;
end else
case (mode)
mode_spi: begin
buffer = {buffer, io0};
bitcount = bitcount + 1;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_dspi_rd, mode_dspi_wr: begin
buffer = {buffer, io1, io0};
bitcount = bitcount + 2;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_qspi_rd, mode_qspi_wr: begin
buffer = {buffer, io3, io2, io1, io0};
bitcount = bitcount + 4;
if (bitcount == 8) begin
bitcount = 0;
bytecount = bytecount + 1;
spi_action;
end
end
mode_qspi_ddr_rd: begin
ddr_rd_edge;
end
mode_qspi_ddr_wr: begin
ddr_wr_edge;
end
endcase
end
end
endmodule |
module testbench;
reg clk;
always #5 clk = (clk === 1'b0);
localparam ser_half_period = 53;
event ser_sample;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
repeat (6) begin
repeat (50000) @(posedge clk);
$display("+50000 cycles");
end
$finish;
end
integer cycle_cnt = 0;
always @(posedge clk) begin
cycle_cnt <= cycle_cnt + 1;
end
wire led1, led2, led3, led4, led5;
wire ledr_n, ledg_n;
wire [6:0] leds = {!ledg_n, !ledr_n, led5, led4, led3, led2, led1};
wire ser_rx;
wire ser_tx;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire flash_io2;
wire flash_io3;
always @(leds) begin
#1 $display("%b", leds);
end
icebreaker #(
// We limit the amount of memory in simulation
// in order to avoid reduce simulation time
// required for intialization of RAM
.MEM_WORDS(256)
) uut (
.clk (clk ),
.led1 (led1 ),
.led2 (led2 ),
.led3 (led3 ),
.led4 (led4 ),
.led5 (led5 ),
.ledr_n (ledr_n ),
.ledg_n (ledg_n ),
.ser_rx (ser_rx ),
.ser_tx (ser_tx ),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.flash_io2(flash_io2),
.flash_io3(flash_io3)
);
spiflash spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(flash_io2),
.io3(flash_io3)
);
reg [7:0] buffer;
always begin
@(negedge ser_tx);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // start bit
repeat (8) begin
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
buffer = {ser_tx, buffer[7:1]};
-> ser_sample; // data bit
end
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // stop bit
if (buffer < 32 || buffer >= 127)
$display("Serial data: %d", buffer);
else
$display("Serial data: '%c'", buffer);
end
endmodule |
module ice40up5k_spram #(
// We current always use the whole SPRAM (128 kB)
parameter integer WORDS = 32768
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
wire cs_0, cs_1;
wire [31:0] rdata_0, rdata_1;
assign cs_0 = !addr[14];
assign cs_1 = addr[14];
assign rdata = addr[14] ? rdata_1 : rdata_0;
SB_SPRAM256KA ram00 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[15:0]),
.MASKWREN({wen[1], wen[1], wen[0], wen[0]}),
.WREN(wen[1]|wen[0]),
.CHIPSELECT(cs_0),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_0[15:0])
);
SB_SPRAM256KA ram01 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[31:16]),
.MASKWREN({wen[3], wen[3], wen[2], wen[2]}),
.WREN(wen[3]|wen[2]),
.CHIPSELECT(cs_0),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_0[31:16])
);
SB_SPRAM256KA ram10 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[15:0]),
.MASKWREN({wen[1], wen[1], wen[0], wen[0]}),
.WREN(wen[1]|wen[0]),
.CHIPSELECT(cs_1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_1[15:0])
);
SB_SPRAM256KA ram11 (
.ADDRESS(addr[13:0]),
.DATAIN(wdata[31:16]),
.MASKWREN({wen[3], wen[3], wen[2], wen[2]}),
.WREN(wen[3]|wen[2]),
.CHIPSELECT(cs_1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdata_1[31:16])
);
endmodule |
module hx8kdemo (
input clk,
output ser_tx,
input ser_rx,
output [7:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_ser_tx,
output debug_ser_rx,
output debug_flash_csb,
output debug_flash_clk,
output debug_flash_io0,
output debug_flash_io1,
output debug_flash_io2,
output debug_flash_io3
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) flash_io_buf [3:0] (
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio;
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc soc (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
assign debug_ser_tx = ser_tx;
assign debug_ser_rx = ser_rx;
assign debug_flash_csb = flash_csb;
assign debug_flash_clk = flash_clk;
assign debug_flash_io0 = flash_io0_di;
assign debug_flash_io1 = flash_io1_di;
assign debug_flash_io2 = flash_io2_di;
assign debug_flash_io3 = flash_io3_di;
endmodule |
module icebreaker (
input clk,
output ser_tx,
input ser_rx,
output led1,
output led2,
output led3,
output led4,
output led5,
output ledr_n,
output ledg_n,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3
);
parameter integer MEM_WORDS = 32768;
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire [7:0] leds;
assign led1 = leds[1];
assign led2 = leds[2];
assign led3 = leds[3];
assign led4 = leds[4];
assign led5 = leds[5];
assign ledr_n = !leds[6];
assign ledg_n = !leds[7];
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) flash_io_buf [3:0] (
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio;
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc #(
.BARREL_SHIFTER(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_FAST_MUL(1),
.MEM_WORDS(MEM_WORDS)
) soc (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule |
module top_small (
input clk, resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) picorv32 (
.clk (clk ),
.resetn (resetn ),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
endmodule |
module top_regular (
input clk, resetn,
output trap,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output [31:0] mem_la_wdata,
output [ 3:0] mem_la_wstrb
);
picorv32 picorv32 (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.mem_la_read (mem_la_read ),
.mem_la_write(mem_la_write),
.mem_la_addr (mem_la_addr ),
.mem_la_wdata(mem_la_wdata),
.mem_la_wstrb(mem_la_wstrb)
);
endmodule |
module top_large (
input clk, resetn,
output trap,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output [31:0] mem_la_wdata,
output [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output [31:0] eoi
);
picorv32 #(
.COMPRESSED_ISA(1),
.BARREL_SHIFTER(1),
.ENABLE_PCPI(1),
.ENABLE_MUL(1),
.ENABLE_IRQ(1)
) picorv32 (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.mem_la_read (mem_la_read ),
.mem_la_write (mem_la_write ),
.mem_la_addr (mem_la_addr ),
.mem_la_wdata (mem_la_wdata ),
.mem_la_wstrb (mem_la_wstrb ),
.pcpi_valid (pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready (pcpi_ready ),
.irq (irq ),
.eoi (eoi )
);
endmodule |
module system_tb;
reg clk = 1;
always #5 clk = ~clk;
reg resetn = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("system.vcd");
$dumpvars(0, system_tb);
end
repeat (100) @(posedge clk);
resetn <= 1;
end
wire trap;
wire [7:0] out_byte;
wire out_byte_en;
system uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.out_byte (out_byte ),
.out_byte_en(out_byte_en)
);
always @(posedge clk) begin
if (resetn && out_byte_en) begin
$write("%c", out_byte);
$fflush;
end
if (resetn && trap) begin
$finish;
end
end
endmodule |
module top (
input clk, io_resetn,
output io_trap,
output io_mem_axi_awvalid,
input io_mem_axi_awready,
output [31:0] io_mem_axi_awaddr,
output [ 2:0] io_mem_axi_awprot,
output io_mem_axi_wvalid,
input io_mem_axi_wready,
output [31:0] io_mem_axi_wdata,
output [ 3:0] io_mem_axi_wstrb,
input io_mem_axi_bvalid,
output io_mem_axi_bready,
output io_mem_axi_arvalid,
input io_mem_axi_arready,
output [31:0] io_mem_axi_araddr,
output [ 2:0] io_mem_axi_arprot,
input io_mem_axi_rvalid,
output io_mem_axi_rready,
input [31:0] io_mem_axi_rdata,
input [31:0] io_irq,
output [31:0] io_eoi
);
wire resetn;
wire trap;
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
wire [31:0] irq;
wire [31:0] eoi;
delay4 #( 1) delay_resetn (clk, io_resetn , resetn );
delay4 #( 1) delay_trap (clk, trap , io_trap );
delay4 #( 1) delay_mem_axi_awvalid (clk, mem_axi_awvalid, io_mem_axi_awvalid);
delay4 #( 1) delay_mem_axi_awready (clk, io_mem_axi_awready, mem_axi_awready);
delay4 #(32) delay_mem_axi_awaddr (clk, mem_axi_awaddr , io_mem_axi_awaddr );
delay4 #( 3) delay_mem_axi_awprot (clk, mem_axi_awprot , io_mem_axi_awprot );
delay4 #( 1) delay_mem_axi_wvalid (clk, mem_axi_wvalid , io_mem_axi_wvalid );
delay4 #( 1) delay_mem_axi_wready (clk, io_mem_axi_wready , mem_axi_wready );
delay4 #(32) delay_mem_axi_wdata (clk, mem_axi_wdata , io_mem_axi_wdata );
delay4 #( 4) delay_mem_axi_wstrb (clk, mem_axi_wstrb , io_mem_axi_wstrb );
delay4 #( 1) delay_mem_axi_bvalid (clk, io_mem_axi_bvalid , mem_axi_bvalid );
delay4 #( 1) delay_mem_axi_bready (clk, mem_axi_bready , io_mem_axi_bready );
delay4 #( 1) delay_mem_axi_arvalid (clk, mem_axi_arvalid, io_mem_axi_arvalid);
delay4 #( 1) delay_mem_axi_arready (clk, io_mem_axi_arready, mem_axi_arready);
delay4 #(32) delay_mem_axi_araddr (clk, mem_axi_araddr , io_mem_axi_araddr );
delay4 #( 3) delay_mem_axi_arprot (clk, mem_axi_arprot , io_mem_axi_arprot );
delay4 #( 1) delay_mem_axi_rvalid (clk, io_mem_axi_rvalid , mem_axi_rvalid );
delay4 #( 1) delay_mem_axi_rready (clk, mem_axi_rready , io_mem_axi_rready );
delay4 #(32) delay_mem_axi_rdata (clk, io_mem_axi_rdata , mem_axi_rdata );
delay4 #(32) delay_irq (clk, io_irq , irq );
delay4 #(32) delay_eoi (clk, eoi , io_eoi );
picorv32_axi #(
.TWO_CYCLE_ALU(1)
) cpu (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.irq (irq ),
.eoi (eoi )
);
endmodule |
module delay4 #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
reg [WIDTH-1:0] q1, q2, q3;
always @(posedge clk) begin
q1 <= in;
q2 <= q1;
q3 <= q2;
out <= q3;
end
endmodule |
module testbench;
reg clk = 1;
always #5 clk = ~clk;
wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;
top uut (
.clk(clk),
.LED0(LED0),
.LED1(LED1),
.LED2(LED2),
.LED3(LED3),
.LED4(LED4),
.LED5(LED5),
.LED6(LED6),
.LED7(LED7)
);
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("example.vcd");
$dumpvars(0, testbench);
end
$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
repeat (10000) @(posedge clk);
$finish;
end
endmodule |
module top (
input clk,
output reg LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7
);
// -------------------------------
// Reset Generator
reg [7:0] resetn_counter = 0;
wire resetn = &resetn_counter;
always @(posedge clk) begin
if (!resetn)
resetn_counter <= resetn_counter + 1;
end
// -------------------------------
// PicoRV32 Core
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0),
.TWO_CYCLE_ALU(1),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid(mem_valid),
.mem_ready(mem_ready),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
// -------------------------------
// Memory/IO Interface
// 128 32bit words = 512 bytes memory
localparam MEM_SIZE = 128;
reg [31:0] memory [0:MEM_SIZE-1];
initial $readmemh("firmware.hex", memory);
always @(posedge clk) begin
mem_ready <= 0;
if (resetn && mem_valid && !mem_ready) begin
(* parallel_case *)
case (1)
!mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
mem_rdata <= memory[mem_addr >> 2];
mem_ready <= 1;
end
|mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
mem_ready <= 1;
end
|mem_wstrb && mem_addr == 32'h1000_0000: begin
{LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
mem_ready <= 1;
end
endcase
end
end
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
picorv32 #(
.COMPRESSED_ISA(1)
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
localparam MEM_SIZE = 4*1024*1024;
`ifdef MEM8BIT
reg [7:0] memory [0:MEM_SIZE-1];
initial $readmemh("firmware.hex", memory);
`else
reg [31:0] memory [0:MEM_SIZE/4-1];
initial $readmemh("firmware32.hex", memory);
`endif
always @(posedge clk) begin
mem_ready <= 0;
if (mem_valid && !mem_ready) begin
mem_ready <= 1;
mem_rdata <= 'bx;
case (1)
mem_addr < MEM_SIZE: begin
`ifdef MEM8BIT
if (|mem_wstrb) begin
if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
end else begin
mem_rdata <= {memory[mem_addr+3], memory[mem_addr+2], memory[mem_addr+1], memory[mem_addr]};
end
`else
if (|mem_wstrb) begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end else begin
mem_rdata <= memory[mem_addr >> 2];
end
`endif
end
mem_addr == 32'h 1000_0000: begin
$write("%c", mem_wdata[7:0]);
end
endcase
end
if (mem_valid && mem_ready) begin
`ifdef VERBOSE_MEM
if (|mem_wstrb)
$display("WR: ADDR=%x DATA=%x MASK=%b", mem_addr, mem_wdata, mem_wstrb);
else
$display("RD: ADDR=%x DATA=%x%s", mem_addr, mem_rdata, mem_instr ? " INSN" : "");
`endif
if (^mem_addr === 1'bx ||
(mem_wstrb[0] && ^mem_wdata[ 7: 0] == 1'bx) ||
(mem_wstrb[1] && ^mem_wdata[15: 8] == 1'bx) ||
(mem_wstrb[2] && ^mem_wdata[23:16] == 1'bx) ||
(mem_wstrb[3] && ^mem_wdata[31:24] == 1'bx)) begin
$display("CRITICAL UNDEF MEM TRANSACTION");
$finish;
end
end
end
`ifdef WRITE_VCD
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
`endif
always @(posedge clk) begin
if (resetn && trap) begin
repeat (10) @(posedge clk);
$display("TRAP");
$finish;
end
end
endmodule |
module testbench;
reg clk = 1;
always #5 clk = ~clk;
reg resetn = 0;
always @(posedge clk) resetn <= 1;
wire trap;
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
picorv32 UUT (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
// 4096 32bit words = 16kB memory
localparam MEM_SIZE = 4096;
reg [31:0] memory [0:MEM_SIZE-1];
initial $readmemh("firmware.hex", memory);
always @(posedge clk) begin
mem_ready <= 0;
mem_rdata <= 'bx;
if (resetn && mem_valid && !mem_ready) begin
mem_ready <= 1;
if (mem_wstrb) begin
if (mem_addr == 32'h1000_0000) begin
$write("%c", mem_wdata[7:0]);
$fflush;
end else begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end
end else begin
mem_rdata <= memory[mem_addr >> 2];
end
end
if (resetn && trap) begin
$display("TRAP.");
$finish;
end
end
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
endmodule |
module picorv32_regs (
input [4:0] A1ADDR, A2ADDR, B1ADDR,
output reg [31:0] A1DATA, A2DATA,
input [31:0] B1DATA,
input B1EN, CLK1
);
reg [31:0] memory [0:31];
always @(posedge CLK1) begin
A1DATA <= memory[A1ADDR];
A2DATA <= memory[A2ADDR];
if (B1EN) memory[B1ADDR] <= B1DATA;
end
endmodule |
module testbench;
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
wire mem_valid;
wire mem_instr;
reg mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
picorv32 #(
.TWO_STAGE_SHIFT(`TWO_STAGE_SHIFT),
.BARREL_SHIFTER(`BARREL_SHIFTER),
.TWO_CYCLE_COMPARE(`TWO_CYCLE_COMPARE),
.TWO_CYCLE_ALU(`TWO_CYCLE_ALU)
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg [31:0] memory [0:16*1024-1];
reg [1023:0] hex_filename;
initial begin
if ($value$plusargs("hex=%s", hex_filename))
$readmemh(hex_filename, memory);
end
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
end
always @(posedge clk) begin
if (resetn && trap) begin
repeat (10) @(posedge clk);
$display("TRAP");
$stop;
end
end
always @(posedge clk) begin
mem_ready <= 0;
if (mem_valid && !mem_ready) begin
mem_ready <= 1;
if (mem_addr == 32'h 1000_0000) begin
if (mem_wdata != -32'd1) begin
$display("Failed test case: %d", mem_wdata);
$stop;
end else begin
$display("OK.");
$finish;
end
end else begin
mem_rdata <= memory[mem_addr >> 2];
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
end
end
end
endmodule |
module top (
input clk, resetn,
output mem_valid,
output mem_instr,
input mem_ready,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [ 3:0] mem_wstrb,
input [31:0] mem_rdata
);
picorv32 #(
.ENABLE_COUNTERS(0),
.LATCHED_MEM_RDATA(1),
.TWO_STAGE_SHIFT(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) picorv32 (
.clk (clk ),
.resetn (resetn ),
.mem_valid(mem_valid),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_rdata(mem_rdata)
);
endmodule |
module testbench (
`ifdef VERILATOR
input clk
`endif
);
`ifndef VERILATOR
reg clk = 1;
always #5 clk = ~clk;
`endif
reg resetn = 0;
integer resetn_cnt = 0;
wire trap;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
end
always @(posedge clk) begin
if (resetn_cnt < 100)
resetn_cnt <= resetn_cnt + 1;
else
resetn <= 1;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
reg [31:0] x32 = 314159265;
reg [31:0] next_x32;
always @(posedge clk) begin
if (resetn) begin
next_x32 = x32;
next_x32 = next_x32 ^ (next_x32 << 13);
next_x32 = next_x32 ^ (next_x32 >> 17);
next_x32 = next_x32 ^ (next_x32 << 5);
x32 <= next_x32;
end
end
picorv32 #(
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1)
) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
reg [7:0] memory [0:4*1024*1024-1];
initial $readmemh("test.hex", memory);
assign mem_ready = x32[0] && mem_valid;
assign mem_rdata[ 7: 0] = memory[mem_addr + 0];
assign mem_rdata[15: 8] = memory[mem_addr + 1];
assign mem_rdata[23:16] = memory[mem_addr + 2];
assign mem_rdata[31:24] = memory[mem_addr + 3];
always @(posedge clk) begin
if (mem_valid && mem_ready) begin
if (mem_wstrb && mem_addr == 'h10000000) begin
$write("%c", mem_wdata[ 7: 0]);
`ifndef VERILATOR
$fflush;
`endif
end else begin
if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
end
end
end
always @(posedge clk) begin
if (resetn && trap) begin
// repeat (10) @(posedge clk);
// $display("TRAP");
$finish;
end
end
endmodule |
module testbench(input clk, mem_ready_0, mem_ready_1);
// set this to 1 to test generation of counter examples
localparam ENABLE_COUNTERS = 0;
reg resetn = 0;
always @(posedge clk) resetn <= 1;
(* keep *) wire trap_0, trace_valid_0, mem_valid_0, mem_instr_0;
(* keep *) wire [3:0] mem_wstrb_0;
(* keep *) wire [31:0] mem_addr_0, mem_wdata_0, mem_rdata_0;
(* keep *) wire [35:0] trace_data_0;
(* keep *) wire trap_1, trace_valid_1, mem_valid_1, mem_instr_1;
(* keep *) wire [3:0] mem_wstrb_1;
(* keep *) wire [31:0] mem_addr_1, mem_wdata_1, mem_rdata_1;
(* keep *) wire [35:0] trace_data_1;
reg [31:0] mem_0 [0:2**30-1];
reg [31:0] mem_1 [0:2**30-1];
assign mem_rdata_0 = mem_0[mem_addr_0 >> 2];
assign mem_rdata_1 = mem_1[mem_addr_1 >> 2];
always @(posedge clk) begin
if (resetn && mem_valid_0 && mem_ready_0) begin
if (mem_wstrb_0[3]) mem_0[mem_addr_0 >> 2][31:24] <= mem_wdata_0[31:24];
if (mem_wstrb_0[2]) mem_0[mem_addr_0 >> 2][23:16] <= mem_wdata_0[23:16];
if (mem_wstrb_0[1]) mem_0[mem_addr_0 >> 2][15: 8] <= mem_wdata_0[15: 8];
if (mem_wstrb_0[0]) mem_0[mem_addr_0 >> 2][ 7: 0] <= mem_wdata_0[ 7: 0];
end
if (resetn && mem_valid_1 && mem_ready_1) begin
if (mem_wstrb_1[3]) mem_1[mem_addr_1 >> 2][31:24] <= mem_wdata_1[31:24];
if (mem_wstrb_1[2]) mem_1[mem_addr_1 >> 2][23:16] <= mem_wdata_1[23:16];
if (mem_wstrb_1[1]) mem_1[mem_addr_1 >> 2][15: 8] <= mem_wdata_1[15: 8];
if (mem_wstrb_1[0]) mem_1[mem_addr_1 >> 2][ 7: 0] <= mem_wdata_1[ 7: 0];
end
end
(* keep *) reg [7:0] trace_balance;
reg [7:0] trace_balance_q;
always @* begin
trace_balance = trace_balance_q;
if (trace_valid_0) trace_balance = trace_balance + 1;
if (trace_valid_1) trace_balance = trace_balance - 1;
end
always @(posedge clk) begin
trace_balance_q <= resetn ? trace_balance : 0;
end
picorv32 #(
// do not change this settings
.ENABLE_COUNTERS(ENABLE_COUNTERS),
.ENABLE_TRACE(1),
// change this settings as you like
.ENABLE_REGS_DUALPORT(1),
.TWO_STAGE_SHIFT(1),
.BARREL_SHIFTER(0),
.TWO_CYCLE_COMPARE(0),
.TWO_CYCLE_ALU(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0)
) cpu_0 (
.clk (clk ),
.resetn (resetn ),
.trap (trap_0 ),
.mem_valid (mem_valid_0 ),
.mem_instr (mem_instr_0 ),
.mem_ready (mem_ready_0 ),
.mem_addr (mem_addr_0 ),
.mem_wdata (mem_wdata_0 ),
.mem_wstrb (mem_wstrb_0 ),
.mem_rdata (mem_rdata_0 ),
.trace_valid (trace_valid_0),
.trace_data (trace_data_0 )
);
picorv32 #(
// do not change this settings
.ENABLE_COUNTERS(ENABLE_COUNTERS),
.ENABLE_TRACE(1),
// change this settings as you like
.ENABLE_REGS_DUALPORT(1),
.TWO_STAGE_SHIFT(1),
.BARREL_SHIFTER(0),
.TWO_CYCLE_COMPARE(0),
.TWO_CYCLE_ALU(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0)
) cpu_1 (
.clk (clk ),
.resetn (resetn ),
.trap (trap_1 ),
.mem_valid (mem_valid_1 ),
.mem_instr (mem_instr_1 ),
.mem_ready (mem_ready_1 ),
.mem_addr (mem_addr_1 ),
.mem_wdata (mem_wdata_1 ),
.mem_wstrb (mem_wstrb_1 ),
.mem_rdata (mem_rdata_1 ),
.trace_valid (trace_valid_1),
.trace_data (trace_data_1 )
);
endmodule |
module test_uart_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg m_axis_tready = 0;
reg rxd = 1;
reg [15:0] prescale = 0;
// Outputs
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire busy;
wire overrun_error;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
m_axis_tready,
rxd,
prescale);
$to_myhdl(m_axis_tdata,
m_axis_tvalid,
busy,
overrun_error,
frame_error);
// dump file
$dumpfile("test_uart_rx.lxt");
$dumpvars(0, test_uart_rx);
end
uart_rx #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.busy(busy),
.overrun_error(overrun_error),
.frame_error(frame_error),
// configuration
.prescale(prescale)
);
endmodule |
module test_uart_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 8'd0;
reg s_axis_tvalid = 1'b0;
reg [15:0] prescale = 0;
// Outputs
wire s_axis_tready;
wire txd;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
prescale);
$to_myhdl(s_axis_tready,
txd,
busy);
// dump file
$dumpfile("test_uart_tx.lxt");
$dumpvars(0, test_uart_tx);
end
uart_tx #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(busy),
// configuration
.prescale(prescale)
);
endmodule |
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire [3:0] sw,
input wire [3:0] btn,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btn,
sw}),
.out({btn_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led0_r(led0_r),
.led0_g(led0_g),
.led0_b(led0_b),
.led1_r(led1_r),
.led1_g(led1_g),
.led1_b(led1_b),
.led2_r(led2_r),
.led2_g(led2_g),
.led2_b(led2_b),
.led3_r(led3_r),
.led3_g(led3_g),
.led3_b(led3_b),
.led4(led4),
.led5(led5),
.led6(led6),
.led7(led7),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule |
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule |
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule |
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [3:0] sw,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule |
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule |
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int,uart_cts_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 9600 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule |
module fpga_core (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
assign uart_rts = 1'b1;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule |
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 9600 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule |
module fpga_core (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule |
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_dcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire dcm_rst;
wire [7:0] dcm_status;
wire dcm_locked;
wire dcm_clkfx_stopped = dcm_status[2];
assign dcm_rst = ~reset_n | (dcm_clkfx_stopped & ~dcm_locked);
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
DCM_SP #(
.CLKIN_PERIOD(10),
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_MULTIPLY(5.0),
.CLKFX_DIVIDE(4.0),
.PHASE_SHIFT(0),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.STARTUP_WAIT("FALSE"),
.CLKIN_DIVIDE_BY_2("FALSE")
)
clk_dcm_inst (
.CLKIN(clk_ibufg),
.CLKFB(1'b0),
.RST(dcm_rst),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(clk_dcm_out),
.CLKFX180(),
.STATUS(dcm_status),
.LOCKED(dcm_locked),
.PSDONE()
);
BUFG
clk_bufg_inst (
.I(clk_dcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~dcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule |
module fpga_core (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
assign phy_reset_n = ~rst;
assign phy_gtx_clk = 1'b0;
assign phy_txd = 8'd0;
assign phy_tx_en = 1'b0;
assign phy_tx_er = 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule |
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire sys_clk_p,
input wire sys_clk_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// Clock and reset
wire sys_clk_ibufg;
wire sys_clk_bufg;
wire clk_125mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_ibufgds_inst(
.I(sys_clk_p),
.IB(sys_clk_n),
.O(sys_clk_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 450 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.100),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(sys_clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
wire ledu_int;
wire ledl_int;
wire ledd_int;
wire ledr_int;
wire ledc_int;
wire [7:0] led_int;
wire uart_rxd_int;
wire uart_txd_int;
wire uart_rts_int;
wire uart_cts_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_txd,
uart_rts}),
.out({uart_txd_int,
uart_rts_int})
);
assign ledu = ledu_int;
assign ledl = ledl_int;
assign ledd = ledd_int;
assign ledr = ledr_int;
assign ledc = ledc_int;
assign led = led_int;
assign uart_rxd = uart_rxd_int;
assign uart_cts = uart_cts_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk_125mhz(clk_125mhz_int),
.rst_125mhz(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.ledu(ledu_int),
.ledl(ledl_int),
.ledd(ledd_int),
.ledr(ledr_int),
.ledc(ledc_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts_int)
);
endmodule |
module core_top
(
input wire clk,
input wire resetb,
//output wire [13:2] rom_addr,
//input wire [31:0] rom_data,
//output wire [13:2] rom_addr_2,
//input wire [31:0] rom_data_2,
output wire [7:0] io_addr,
output wire io_en,
output wire io_we,
input wire [31:0] io_data_read,
output wire [31:0] io_data_write,
input wire irq_mtimecmp
//input wire mtime_we,
//output wire [31:0] mtime_dout
);
wire dm_we;
wire [31:0] im_addr;
wire [31:0] im_do;
wire [31:0] dm_addr;
wire [31:0] dm_di;
wire [31:0] dm_do;
wire [3:0] dm_be;
wire dm_is_signed;
core CPU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .dm_is_signed(dm_is_signed),
.irq_mtimecmp(irq_mtimecmp)
);
mmu MMU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we),
.im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .is_signed(dm_is_signed),
//.im_addr_out(rom_addr), .im_data(rom_data),
//.im_addr_out_2(rom_addr_2), .im_data_2(rom_data_2),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write)
);
endmodule |
module core
(
// Top
clk, resetb,
// MMU
dm_we, im_addr, im_do, dm_addr, dm_di, dm_do, dm_be, dm_is_signed,
// IRQ
irq_mtimecmp
);
`include "core/aluop.vh"
`include "core/exception_vector.vh"
input wire clk, resetb;
// Interface to MMU
input wire [31:0] im_do/*verilator public*/, dm_do;
output dm_we, dm_is_signed;
output [31:0] im_addr, dm_addr, dm_di;
output [3:0] dm_be;
wire dm_we, dm_is_signed;
wire [31:0] dm_addr, dm_di;
reg [31:0] im_addr;
wire [3:0] dm_be;
// Timer interrupt
input wire irq_mtimecmp;
// Instruction Decode
wire [31:0] FD_imm;
wire FD_alu_is_signed;
wire [31:0] FD_aluop1_sel, FD_aluop2_sel, FD_alu_op;
wire FD_pc_update, FD_pc_mepc;
wire FD_regwrite;
wire FD_jump, FD_link, FD_jr, FD_br;
wire [3:0] FD_dm_be;
wire FD_dm_we;
wire FD_dm_is_signed;
wire FD_csr_read, FD_csr_write, FD_csr_set, FD_csr_clear, FD_csr_imm;
wire [4:0] FD_a_rs1, FD_a_rs2, FD_a_rd;
wire [2:0] FD_funct3;
/* verilator lint_off UNUSED */
wire [6:0] FD_funct7;
/* verilator lint_on UNUSED */
wire FD_exception_illegal_instruction;
wire FD_exception_ecall;
wire FD_exception_ebreak;
reg FD_exception_instruction_misaligned;
wire FD_exception_load_misaligned;
wire FD_exception_store_misaligned;
// Program Counter
wire FD_initiate_exception;
reg [31:0] FD_PC /*verilator public*/;
reg [31:0] nextPC /*verilator public*/;
// FD ALU
wire [31:0] FD_aluout;
// Internally Forwarding Register File
reg [4:0] XB_a_rd;
reg [31:0] XB_d_rd;
wire [31:0] FD_d_rs1, FD_d_rs2;
// XB Stage registers
reg [31:0] XB_d_rs1, XB_d_rs2, XB_imm;
/* verilator lint_off UNUSED */
reg [4:0] XB_a_rs1;
/* verilator lint_on UNUSED */
reg XB_regwrite;
reg XB_memtoreg;
reg XB_alu_is_signed;
reg [31:0] XB_aluop1_sel, XB_aluop2_sel, XB_alu_op;
reg XB_FD_exception_illegal_instruction;
reg XB_FD_exception_ecall;
reg XB_FD_exception_ebreak;
reg XB_FD_exception_instruction_misaligned;
reg XB_FD_exception_load_misaligned;
reg XB_FD_exception_store_misaligned;
reg [31:0] XB_PC;
wire FD_bubble;
reg FD_reset;
reg XB_bubble;
// XB ALU
reg [31:0] XB_aluop1, XB_aluop2, XB_aluout;
// CSR Register file and Exception Handling Unit
wire [31:0] XB_csr_out;
wire XB_csr_read, XB_csr_write, XB_csr_set, XB_csr_clear, XB_csr_imm;
wire [31:0] CSR_mepc, CSR_mtvec;
reg XB_csr_writeback;
assign dm_be = FD_bubble ? 4'b0 : FD_dm_be;
assign dm_we = (FD_exception_store_misaligned | FD_bubble) ?
1'b0 : FD_dm_we;
assign dm_is_signed = FD_dm_is_signed;
instruction_decoder inst_dec
(
.FD_reset(FD_reset),
.inst(im_do), .aluout_1_0(FD_aluout[1:0]),
.immediate(FD_imm),
.alu_is_signed(FD_alu_is_signed),
.aluop1_sel(FD_aluop1_sel), .aluop2_sel(FD_aluop2_sel),
.alu_op(FD_alu_op),
.pc_update(FD_pc_update), .pc_mepc(FD_pc_mepc),
.regwrite(FD_regwrite), .jump(FD_jump), .link(FD_link),
.jr(FD_jr), .br(FD_br),
.dm_be(FD_dm_be), .dm_we(FD_dm_we),
.mem_is_signed(FD_dm_is_signed),
.csr_read(FD_csr_read), .csr_write(FD_csr_write),
.csr_set(FD_csr_set), .csr_clear(FD_csr_clear), .csr_imm(FD_csr_imm),
.a_rs1(FD_a_rs1), .a_rs2(FD_a_rs2), .a_rd(FD_a_rd),
.funct3(FD_funct3), .funct7(FD_funct7),
.exception_illegal_instruction(FD_exception_illegal_instruction),
.exception_ecall(FD_exception_ecall),
.exception_ebreak(FD_exception_ebreak),
.exception_load_misaligned(FD_exception_load_misaligned),
.exception_store_misaligned(FD_exception_store_misaligned)
//.disasm_opcode(FD_disasm_opcode)
);
// Next PC for Branches
// reg [31:0] nextPC_br;
// Successful branch
reg do_branch;
always @ (*) begin : PC_UPDATE
// Successful branch: FD instruction is branch and condition
// match
do_branch = FD_br == 1'b0 ? 1'b0
:
(
(FD_funct3==3'b000&&FD_d_rs1 == FD_d_rs2)
||
(FD_funct3==3'b001&&FD_d_rs1 != FD_d_rs2)
||
(FD_funct3==3'b100&&$signed(FD_d_rs1)<$signed(FD_d_rs2))
||
(FD_funct3==3'b101&&$signed(FD_d_rs1)>=$signed(FD_d_rs2))
||
(FD_funct3==3'b110&&$unsigned(FD_d_rs1)<$unsigned(FD_d_rs2))
||
(FD_funct3==3'b111&&$unsigned(FD_d_rs1)>=$unsigned(FD_d_rs2))
)
? 1'b1 : 1'b0;
// Update PC. Priority from high to low:
//
// Illegal Instruction Exception, Misaligned Exception, MRET,
// Branch, Jump, Jump Register, Increment
nextPC = (FD_initiate_exception) ? CSR_mtvec
: (FD_pc_update & FD_pc_mepc) ? CSR_mepc
: (do_branch) ? FD_imm + FD_PC
: (FD_jump) ? FD_PC + FD_imm
: (FD_jr) ? {FD_aluout[31:1], 1'b0}
: FD_PC + 32'd4;
FD_exception_instruction_misaligned = nextPC[1:0] != 2'b00;
im_addr = nextPC;
end
// Update the Program Counter
always @ (posedge clk) begin : PROGRAM_COUNTER
if (!resetb) begin
FD_PC <= 32'hFFFFFFFC;
end
else if (clk) begin
FD_PC <= nextPC;
end // if (clk)
end
// FD stage ALU, used in PC update and MMU address
assign FD_aluout = FD_d_rs1 + FD_imm;
// Register file
regfile RF(
.clk(clk), .resetb(resetb),
.a_rs1(FD_a_rs1), .d_rs1(FD_d_rs1),
.a_rs2(FD_a_rs2), .d_rs2(FD_d_rs2),
.a_rd(XB_a_rd), .d_rd(XB_d_rd), .we_rd(XB_regwrite)
);
// Main ALU in XB stage
always @ (*) begin : XB_ALU
// Select operator 1
case (XB_aluop1_sel)
`ALUOP1_RS1: XB_aluop1 = XB_d_rs1;
`ALUOP1_PC: XB_aluop1 = XB_PC;
default: XB_aluop1 = 32'bX;
endcase // case (XB_aluop1_sel)
// Select operator 2
case (XB_aluop2_sel)
`ALUOP2_RS2: XB_aluop2 = XB_d_rs2;
`ALUOP2_IMM: XB_aluop2 = XB_imm;
default: XB_aluop2 = 32'bX;
endcase // case (XB_aluop2_sel)
// ALU operation
case (XB_alu_op)
`ALU_ADD: begin
XB_aluout = XB_aluop1 + XB_aluop2;
end
`ALU_SLT: begin
XB_aluout = (XB_alu_is_signed)
? ($signed(XB_aluop1) < $signed(XB_aluop2) ? 32'h1 : 32'h0)
: ($unsigned(XB_aluop1) < $unsigned(XB_aluop2) ? 32'h1 : 32'h0);
end
`ALU_AND: begin
XB_aluout = XB_aluop1 & XB_aluop2;
end
`ALU_OR: begin
XB_aluout = XB_aluop1 | XB_aluop2;
end
`ALU_XOR: begin
XB_aluout = XB_aluop1 ^ XB_aluop2;
end
`ALU_SLL: begin
XB_aluout = XB_aluop1 << XB_aluop2[4:0];
end
`ALU_SRL: begin
XB_aluout = XB_aluop1 >> XB_aluop2[4:0];
end
`ALU_SRA: begin
XB_aluout = $signed(XB_aluop1) >>> XB_aluop2[4:0];
end
`ALU_SUB: begin
XB_aluout = XB_aluop1 - XB_aluop2;
end
default:
XB_aluout = 32'bX;
endcase // case (XB_alu_op)
end // block: XB_ALU
// Here, the naming is confusing because the signals are actually
// in FD stage, due to the internally pipelined CSR_EHU module
assign XB_csr_read = FD_bubble ? 1'b0 : FD_csr_read;
assign XB_csr_write = FD_bubble ? 1'b0 : FD_csr_write;
assign XB_csr_set = FD_bubble ? 1'b0 : FD_csr_set;
assign XB_csr_clear = FD_bubble ? 1'b0 : FD_csr_clear;
assign XB_csr_imm = FD_csr_imm;
csr_ehu CSR_EHU0
(
.clk(clk), .resetb(resetb), .XB_bubble(XB_bubble),
.read(XB_csr_read), .write(XB_csr_write),
.set(XB_csr_set), .clear(XB_csr_clear),
.imm(XB_csr_imm), .a_rd(FD_a_rd),
.initiate_exception(FD_initiate_exception),
.XB_FD_exception_illegal_instruction(XB_FD_exception_illegal_instruction),
.XB_FD_exception_instruction_misaligned(XB_FD_exception_instruction_misaligned),
.XB_FD_exception_ecall(XB_FD_exception_ecall),
.XB_FD_exception_ebreak(XB_FD_exception_ebreak),
.XB_FD_exception_load_misaligned(XB_FD_exception_load_misaligned),
.XB_FD_exception_store_misaligned(XB_FD_exception_store_misaligned),
.irq_mtimecmp(irq_mtimecmp),
.src_dst(FD_imm[11:0]),
.d_rs1(FD_d_rs1), .uimm(FD_a_rs1), .FD_aluout(FD_aluout),
.nextPC(nextPC), .XB_pc(XB_PC[31:2]), .data_out(XB_csr_out),
.csr_mepc(CSR_mepc), .csr_mtvec(CSR_mtvec)
);
// Writeback path select
always @ (*) begin : XB_Writeback_Path
// MemToReg: Load memory to register
// csr_writeback: CSR to register
XB_d_rd = XB_memtoreg ? dm_do
: XB_csr_writeback ? XB_csr_out
: XB_aluout;
end
// MMU Interface
assign dm_addr = FD_aluout;
assign dm_di = FD_d_rs2;
// Flush instructions on exception.
assign FD_bubble = FD_initiate_exception;
// The main pipeline
always @ (posedge clk) begin : CORE_PIPELINE
if (!resetb) begin
// Initialize stage registers with side effects
XB_regwrite <= 1'b0;
XB_csr_writeback <= 1'b0;
XB_FD_exception_illegal_instruction <= 1'b0;
XB_FD_exception_ecall <= 1'b0;
XB_FD_exception_ebreak <= 1'b0;
XB_FD_exception_instruction_misaligned <= 1'b0;
XB_FD_exception_load_misaligned <= 1'b0;
XB_FD_exception_store_misaligned <= 1'b0;
XB_bubble <= 1'b1;
// Initialize stage registers
XB_PC <= 32'bX;
XB_d_rs1 <= 32'bX;
XB_d_rs2 <= 32'bX;
XB_a_rs1 <= 5'bX;
XB_a_rd <= 5'bX;
// XB_csr_imm <= 1'bX;
XB_memtoreg <= 1'bX;
XB_alu_is_signed <= 1'bX;
XB_aluop1_sel <= 32'bX;
XB_aluop2_sel <= 32'bX;
// FD Reset
FD_reset <= 1'b1;
end
else if (clk) begin
FD_reset <= 1'b0;
// XB stage
//// Operators
if (!FD_link) begin
XB_d_rs1 <= FD_d_rs1;
XB_d_rs2 <= FD_d_rs2;
end
else begin
// If Linking, the operation is PC + 4
XB_d_rs1 <= FD_PC;
XB_d_rs2 <= 32'h4;
end
XB_imm <= FD_imm;
XB_a_rs1 <= FD_a_rs1;
XB_a_rd <= FD_a_rd;
//// Pure signals
XB_memtoreg <= FD_dm_be[3] | FD_dm_be[2] | FD_dm_be[1] | FD_dm_be[0];
XB_aluop1_sel <= FD_aluop1_sel;
XB_aluop2_sel <= FD_aluop2_sel;
XB_alu_op <= FD_alu_op;
XB_alu_is_signed <= FD_alu_is_signed;
XB_PC <= FD_PC;
//// Side effect signals
XB_bubble <= FD_bubble;
if (!FD_bubble) begin
// Side effect signals propagate only if instruction is
// not a bubble
XB_csr_writeback <= XB_csr_read;
XB_regwrite <= FD_regwrite;
XB_FD_exception_illegal_instruction
<= FD_exception_illegal_instruction;
XB_FD_exception_ecall <= FD_exception_ecall;
XB_FD_exception_ebreak <= FD_exception_ebreak;
XB_FD_exception_instruction_misaligned
<= FD_exception_instruction_misaligned;
XB_FD_exception_load_misaligned
<= FD_exception_load_misaligned;
XB_FD_exception_store_misaligned
<= FD_exception_store_misaligned;
end
else begin
// A bubble has all side-effectful signals deactivated
XB_regwrite <= 1'b0;
XB_FD_exception_illegal_instruction <= 1'b0;
XB_FD_exception_instruction_misaligned <= 1'b0;
XB_FD_exception_load_misaligned <= 1'b0;
XB_FD_exception_store_misaligned <= 1'b0;
end // else: !if(!FD_bubble)
// FD stage
end
end
endmodule // core |
module timer(
input wire clk,
input wire resetb,
// No io_en signal since read has no side effect
input wire [3:2] io_addr_3_2,
input wire io_we,
input wire [31:0] io_din,
output wire [31:0] io_dout,
// mtimecmp port
// IRQ
output reg irq_mtimecmp
);
reg [63:0] mtime;
reg [63:0] mtimecmp;
always @ (posedge clk) begin : TIMER_PIPELINE
if (!resetb) begin
mtime <= 64'b0;
// mtimecmp <= 64'hFFFFFFFFFFFFFFFF;
mtimecmp <= 64'b0;
irq_mtimecmp <= 1'b0;
end
else if (clk) begin
mtime <= mtime + 1;
if (io_we) begin
case (io_addr_3_2[3:2])
2'b00: mtime[0+:32] <= io_din;
2'b01: mtime[32+:32] <= io_din;
2'b10: begin
mtimecmp[0+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
2'b11: begin
mtimecmp[32+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
endcase
end
if (mtime == mtimecmp) begin
irq_mtimecmp <= 1'b1;
end
end
end
assign io_dout =
io_addr_3_2[3]
? ( io_addr_3_2[2] ? mtimecmp[32+:32] : mtimecmp[0+:32] )
: ( io_addr_3_2[2] ? mtime[32+:32] : mtime[0+:32] );
endmodule |
module io_port
(
input wire clk,
input wire resetb,
/* verilator lint_off UNUSED */
input wire [7:0] io_addr/*verilator public*/,
input wire io_en/*verilator public*/,
/* verilator lint_on UNUSED */
input wire io_we/*verilator public*/,
input wire [31:0] io_data_write/*verilator public*/,
output wire [31:0] io_data_read,
output wire irq_mtimecmp,
output reg [7:0] gpio0
);
wire mtime_we;
wire [31:0] mtime_dout;
assign mtime_we = io_addr[7:4] == 4'b0001 ? io_we : 1'b0;
assign io_data_read = io_addr[7:4] == 4'b0001 ? mtime_dout : 32'bX;
// GPIO0 is at 0x80000000, the same address as testbench commands.
// However, it only uses the lowest byte
always @ (posedge clk) begin : GPIO0
if (!resetb) begin
gpio0 <= 8'b0;
end
else if (clk) begin
if (io_addr[7:2] == 6'b0 && io_we) begin
gpio0 <= io_data_write[7:0];
end
end
end
timer TIMER0
(
.clk(clk), .resetb(resetb),
.io_addr_3_2(io_addr[3:2]), .io_we(mtime_we), .io_din(io_data_write),
.io_dout(mtime_dout), .irq_mtimecmp(irq_mtimecmp)
);
endmodule |
module SPRAM_16Kx16
(
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output reg [15:0] dout
);
reg [15:0] RAM [16383:0] /*verilator public*/;
always @ (posedge clk) begin
if (wren) begin
if (maskwren[0]) RAM[addr][0+:4] <= din[0+:4];
if (maskwren[1]) RAM[addr][4+:4] <= din[4+:4];
if (maskwren[2]) RAM[addr][8+:4] <= din[8+:4];
if (maskwren[3]) RAM[addr][12+:4] <= din[12+:4];
end
else begin
dout <= RAM[addr];
end
end
endmodule // SB_SPRAM256KA |
module mmu_tb();
reg clk_tb, resetb_tb, dm_we_tb;
reg [31:0] im_addr_tb, dm_addr_tb, dm_di_tb;
wire [31:0] im_do_tb, dm_do_tb;
reg [3:0] dm_be_tb;
reg is_signed_tb;
wire [11:2] im_addr_out_tb;
wire [31:0] im_data_tb, io_data_read_tb, io_data_write_tb;
wire [7:0] io_addr_tb;
wire io_en_tb, io_we_tb;
reg [31:0] instruction_memory [0:4095];
reg [31:0] io_memory [0:255];
integer i;
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
// Test 1: Byte read/write
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Byte R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned bytes");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
// 1. Write process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 4*i + 0;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
dm_be_tb = 4'b0010;
dm_di_tb = 4*i + 1;
@(posedge clk_tb);
dm_be_tb = 4'b0100;
dm_di_tb = 4*i + 2;
@(posedge clk_tb);
dm_be_tb = 4'b1000;
dm_di_tb = 4*i + 3;
@(posedge clk_tb);
end // for (i = 0; i < 40; i = i + 1)
dm_we_tb = 1'b0;
// 2. Read process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0010;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1000;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask //
// Test 2: Half word read/write
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Half Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned half words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
// 1. Write process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 2*i + 0;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
dm_be_tb = 4'b1100;
dm_di_tb = 2*i + 1;
@(posedge clk_tb);
end // for (i = 0; i < 40; i = i + 1)
dm_we_tb = 1'b0;
// 2. Read process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask //
// Test 3: Word read/write
task run_test3;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 3: Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
// 1. Write process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
// 2. Read process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask //
// Test 4: Read Instruction Memory
task run_test4;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 4: Read Instruction Memory ");
$display("(TT) 1. Reads words from 0x0000000, 0x0000004, ...");
$display("(TT) 2. Pipelined. Should read 4095, 4094, ...");
$display("(TT) 3. The first read is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
// Read process
for (i = 0; i < 8; i = i + 1) begin
im_addr_tb = 32'h0 + i*4;
@(posedge clk_tb);
$display("(TT) im_addr = 0x%h, im_do(prev) = %d",
im_addr_tb, im_do_tb);
#0;
end
end
endtask //
// Test 5: IO R/W
task run_test5;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 5: IO R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x80000000, ... consecutively in unsigned words");
$display("(TT) 2. The IO port should pipeline output the written values");
$display("(TT) 3. Then IO port is read");
$display("(TT) 4. IO port should read 4096, 4097, ...");
$display("(TT) 5. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
// 1. Write process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) io_we = %b, io_addr = 0x%h, io_data_write = 0x%h",
io_we_tb, io_addr_tb, io_data_write_tb);
#0;
end
dm_we_tb = 1'b0;
// 2. Read process
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask //
assign im_data_tb = instruction_memory[im_addr_out_tb[11:2]];
assign io_data_read_tb = io_memory[io_addr_tb[7:2]];
mmu UUT(.clk(clk_tb), .resetb(resetb_tb), .dm_we(dm_we_tb),
.im_addr(im_addr_tb), .im_do(im_do_tb),
.dm_addr(dm_addr_tb), .dm_di(dm_di_tb),
.dm_do(dm_do_tb), .dm_be(dm_be_tb),
.is_signed(is_signed_tb),
.im_addr_out(im_addr_out_tb), .im_data(im_data_tb),
.io_addr(io_addr_tb), .io_en(io_en_tb), .io_we(io_we_tb),
.io_data_read(io_data_read_tb), .io_data_write(io_data_write_tb)
);
// Run the tests
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/mmu_tb.vcd");
$dumpvars(0,mmu_tb);
// Initialize the instruction memory and io memory for testing
for (i = 0; i < 4096; i = i + 1) begin
instruction_memory[i] = 4095 - i;
end
for (i = 0; i < 256; i = i + 1) begin
io_memory[i] = 4096 + i;
end
@(posedge clk_tb);
run_test1();
run_test2();
run_test3();
run_test4();
run_test5();
$finish;
end
endmodule // mmu_tb |
module board_top
(
input wire clki,
input wire resetb,
output wire [7:0] gpio0
);
wire clk;
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
.GLOBAL_BUFFER_OUTPUT(clk));
cpu_top U0(.clk(clk), .resetb(resetb), .gpio0(gpio0));
endmodule // board_top |
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
output reg [15:0] DATAOUT
);
reg [15:0] mem [0:16383];
wire off = SLEEP || !POWEROFF;
integer i;
always @(negedge POWEROFF) begin
for (i = 0; i <= 16383; i = i+1)
mem[i] = 'bx;
end
always @(posedge CLOCK, posedge off) begin
if (off) begin
DATAOUT <= 0;
end else
if (CHIPSELECT && !STANDBY && !WREN) begin
DATAOUT <= mem[ADDRESS];
end else begin
if (CHIPSELECT && !STANDBY && WREN) begin
if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
end
DATAOUT <= 'bx;
end
end
endmodule |
module mmu(
clk, resetb, dm_we,
im_addr, im_do, dm_addr, dm_di, dm_do,
dm_be, is_signed,
// To Instruction Memory
// im_addr_out, im_data,
// im_addr_out_2, im_data_2,
// TO IO
io_addr, io_en, io_we, io_data_read, io_data_write
);
parameter
WORD_DEPTH = 65536,
WORD_DEPTH_LOG = 16;
localparam
DEV_IM = 1,
DEV_DM = 2,
DEV_IO = 3,
DEV_UNKN = 4;
// Clock, reset, data memory write enable
input wire clk, resetb, dm_we;
// IM address, DM address, DM data in
/* verilator lint_off UNUSED */
input wire [31:0] im_addr, dm_addr, dm_di;
/* verilator lint_on UNUSED */
// DM data byte enable, non-encoded
input wire [3:0] dm_be;
// DM sign extend or unsigned extend
input wire is_signed;
// IM addr out to ROM
// wire [13:2] im_addr_out, im_addr_out_2;
// IM data from ROM, IO data from IO bank
//input wire [31:0] im_data, im_data_2;
input wire [31:0] io_data_read;
// IO data to IO bank, DM data output
output reg [31:0] io_data_write, dm_do;
// A temporary register for dm_do
reg [31:0] dm_do_tmp;
// IM data output
output wire [31:0] im_do;
// IO address to IO bank
output reg [7:0] io_addr;
// IO enable, IO write enable
output reg io_en, io_we;
// Shift bytes and half words to correct bank
reg [31:0] dm_di_shift;
// Address mapped to BRAM address
reg [WORD_DEPTH_LOG-1:2] ram_addr;
// BRAM write enable
reg ram_we;
// BRAM data output
wire [31:0] ram_do;
// BRAM data input
reg [31:0] ram_di;
// Selected device
/* verilator lint_off UNUSED */
integer chosen_device_tmp;
/* verilator lint_on UNUSED */
// Selected device, pipelined
reg [2:0] chosen_device_p;
// DM byte enable, pipelined
reg [3:0] dm_be_p;
// MMU signed/unsigned extend, pipelined
reg is_signed_p;
// IM port 2 pipelined
reg [31:0] im_data_2_p;
// IO Read input, IO read input pipelined, IO write output
reg [31:0] io_data_write_tmp;
// IO address
reg [7:0] io_addr_tmp;
// IO enable, IO write enable
reg io_en_tmp, io_we_tmp;
// In this implementaion, the IM ROM address is simply the 13:2 bits of IM address input
//assign im_addr_out[13:2] = im_addr[13:2];
// Second port uses DM addr
//assign im_addr_out_2[13:2] = dm_addr[13:2];
// BRAM bank in interleaved configuration
SPRAM_16Kx16 ram0 (
.clk(clk), .wren(ram_we),
.maskwren({{2{dm_be[1]}},{2{dm_be[0]}}}),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.din(ram_di[0+:16]), .dout(ram_do[0+:16])
);
SPRAM_16Kx16 ram1 (
.clk(clk), .wren(ram_we),
.maskwren({{2{dm_be[3]}},{2{dm_be[2]}}}),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.din(ram_di[16+:16]), .dout(ram_do[16+:16])
);
EBRAM_ROM rom0(
.clk(clk), .addra(im_addr[10:2]), .douta(im_do),
.addrb(dm_addr[10:2]), .doutb(im_data_2_p)
);
// The MMU pipeline
always @ (posedge clk) begin : MMU_PIPELINE
if (!resetb) begin
chosen_device_p <= 3'bX;
is_signed_p <= 1'bX;
dm_be_p <= 4'b0;
// First instruction is initialized as NOP
//im_do <= 32'b0000_0000_0000_00000_000_00000_0010011;
io_data_write <= 32'bX;
//im_data_2_p <= 32'bX;
io_en <= 1'b0;
io_we <= 1'b0;
io_addr <= 8'bX;
end
else if (clk) begin
// Notice the pipeline. The naming is a bit inconsistent
dm_be_p <= dm_be;
chosen_device_p <= chosen_device_tmp[2:0];
is_signed_p <= is_signed;
//im_do <= im_data;
//im_data_2_p <= im_data_2;
io_data_write <= io_data_write_tmp;
io_en <= io_en_tmp;
io_we <= io_we_tmp;
io_addr <= io_addr_tmp;
end
end
/* verilator lint_off UNUSED */
reg [31:0] ram_addr_temp, io_addr_temp;
/* verilator lint_on UNUSED */
// Device mapping from address
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_ADDR_MAP
ram_addr_temp = dm_addr - 32'h10000000;
io_addr_temp = dm_addr - 32'h80000000;
io_addr_tmp = io_addr_temp[7:0];;
io_en_tmp = 1'b0;
io_we_tmp = 1'b0;
io_data_write_tmp = 32'bX;
ram_we = 1'b0;
ram_addr = {(WORD_DEPTH_LOG-2){1'bX}};
ram_di = 32'bX;
chosen_device_tmp = DEV_UNKN;
if (dm_addr[31:12] == 20'b0) begin
// 0x00000000 - 0x00000FFF
chosen_device_tmp = DEV_IM;
end
else if (dm_addr[31] == 1'b0 && dm_addr[30:28] != 3'b0) begin
// 0x10000000 - 0x7FFFFFFF
ram_addr = ram_addr_temp[2+:WORD_DEPTH_LOG-2];
ram_di = dm_di_shift;
ram_we = dm_we;
chosen_device_tmp = DEV_DM;
end
else if (dm_addr[31:8] == 24'h800000) begin
// 0x80000000 - 0x800000FF
// io_addr_tmp = io_addr_temp[7:0];
io_en_tmp = 1'b1;
io_we_tmp = dm_we;
io_data_write_tmp = dm_di_shift;
chosen_device_tmp = DEV_IO;
end
end // block: DM_ADDR_MAP
// Shifting input byte/halfword to correct position
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_IN_SHIFT
dm_di_shift = 32'bX;
// Byte enable
if (dm_be == 4'b1111) begin
dm_di_shift = dm_di;
end
else if (dm_be == 4'b1100) begin
dm_di_shift[16+:16] = dm_di[0+:16];
end
else if (dm_be == 4'b0011) begin
dm_di_shift[0+:16] = dm_di[0+:16];
end
else if (dm_be == 4'b0001) begin
dm_di_shift[0+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b0010) begin
dm_di_shift[8+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b0100) begin
dm_di_shift[16+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b1000) begin
dm_di_shift[24+:8] = dm_di[0+:8];
end
end // block: DM_IN_SHIFT
// Shifting byte/halfword to correct output position
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_OUT_SHIFT
case (chosen_device_p)
DEV_IM:
dm_do_tmp = im_data_2_p;
DEV_DM:
dm_do_tmp = ram_do;
DEV_IO:
dm_do_tmp = io_data_read;
default:
dm_do_tmp = 32'bX;
endcase // case (chosen_device_reg)
// Byte enable
dm_do = 32'bX;
if (dm_be_p == 4'b1111) begin
dm_do = dm_do_tmp;
end
else if (dm_be_p == 4'b1100) begin
if (is_signed_p)
dm_do = {{16{dm_do_tmp[31]}}, dm_do_tmp[16+:16]};
else
dm_do = {16'b0, dm_do_tmp[16+:16]};
end
else if (dm_be_p == 4'b0011) begin
if (is_signed_p)
dm_do = {{16{dm_do_tmp[15]}}, dm_do_tmp[0+:16]};
else
dm_do = {16'b0, dm_do_tmp[0+:16]};
end
else if (dm_be_p == 4'b0001) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[7]}}, dm_do_tmp[0+:8]};
else
dm_do = {24'b0, dm_do_tmp[0+:8]};
end
else if (dm_be_p == 4'b0010) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[15]}}, dm_do_tmp[8+:8]};
else
dm_do = {24'b0, dm_do_tmp[8+:8]};
end
else if (dm_be_p == 4'b0100) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[23]}}, dm_do_tmp[16+:8]};
else
dm_do = {24'b0, dm_do_tmp[16+:8]};
end
else if (dm_be_p == 4'b1000) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[31]}}, dm_do_tmp[24+:8]};
else
dm_do = {24'b0, dm_do_tmp[24+:8]};
end
end
endmodule // mmu |
module BRAM_SSP(
clk, we, en, addr, din, dout
);
parameter
DEPTH = 256,
DEPTH_LOG = 8,
WIDTH = 32;
input clk, we, en;
input [DEPTH_LOG-1:0] addr;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
reg [WIDTH-1:0] RAM [DEPTH-1:0] /*verilator public*/;
reg [WIDTH-1:0] dout;
always @ (posedge clk) begin
if (en & we) begin
RAM[addr] <= din;
dout <= din;
end
else
dout <= RAM[addr];
end
endmodule // BRAM_SSP |
module EBRAM_ROM(
clk,
addra, douta, addrb, doutb
);
parameter
DEPTH = 512,
DEPTH_LOG = 9,
WIDTH = 32;
input wire clk;
input wire [DEPTH_LOG-1:0] addra, addrb;
output reg [WIDTH-1:0] douta, doutb;
reg [WIDTH-1:0] ROM [DEPTH-1:0] /*verilator public*/;
always @ (posedge clk) begin
douta <= ROM[addra];
doutb <= ROM[addrb];
end
endmodule // BRAM_SSP |
module SPRAM_16Kx16
(
input wire [13:0] addr,
input wire [15:0] din,
input wire [3:0] maskwren,
input wire wren,
input wire clk,
output wire [15:0] dout
);
SB_SPRAM256KA ram0
(
.ADDRESS(addr),
.DATAIN(din),
.MASKWREN(maskwren),
.CHIPSELECT(1'b1),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b0),
.DATAOUT(dout)
);
endmodule |
module regfile(
input wire clk, input wire resetb,
input wire [4:0] a_rs1,
output reg [31:0] d_rs1,
input wire [4:0] a_rs2,
output reg [31:0] d_rs2,
input wire [4:0] a_rd,
input wire [31:0] d_rd,
input wire we_rd
);
// 32x32 registers
reg [31:0] data [0:31] /*verilator public*/;
// Temporary variable
integer i;
always @ (posedge clk) begin : MAIN_CLK_PROCESS
if (!resetb) begin
// Registers do not initialize
for (i = 0; i < 32; i = i + 1) begin
data[i] <= 32'bX;
end
end
else if (clk) begin
// Write back
if (we_rd) begin
data[a_rd] <= d_rd;
end
end
end // block: MAIN_CLK_PROCESS
always @ (*) begin : COMBINATIONAL_PROCESS
// Forwarding rs1
if (a_rs1 == 5'b0)
d_rs1 = 32'b0;
else if (we_rd && a_rd != 5'b0 && a_rs1 == a_rd)
d_rs1 = d_rd;
else
d_rs1 = data[a_rs1];
// Forwarding rs2
if (a_rs2 == 5'b0)
d_rs2 = 32'b0;
else if (we_rd && a_rd != 5'b0 && a_rs2 == a_rd)
d_rs2 = d_rd;
else
d_rs2 = data[a_rs2];
end
endmodule // regfile |
module cpu_top
(
input wire clk,
input wire resetb,
output wire [7:0] gpio0
);
wire [7:0] io_addr;
wire io_en, io_we;
wire [31:0] io_data_read;
wire [31:0] io_data_write;
wire irq_mtimecmp;
core_top CT0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp)
);
io_port IO0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp),
.gpio0(gpio0)
);
endmodule |
module core_top
(
input wire clk,
input wire resetb,
output wire [11:2] rom_addr,
input wire [31:0] rom_data,
output wire [7:0] io_addr,
output wire io_en,
output wire io_we,
input wire [31:0] io_data_read,
output wire [31:0] io_data_write
);
wire dm_we;
wire [31:0] im_addr;
wire [31:0] im_do;
wire [31:0] dm_addr;
wire [31:0] dm_di;
wire [31:0] dm_do;
wire [3:0] dm_be;
wire dm_is_signed;
core CPU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .dm_is_signed(dm_is_signed)
);
mmu MMU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .is_signed(dm_is_signed),
.im_addr_out(rom_addr), .im_data(rom_data),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write)
);
endmodule |
module mmu(
clk, resetb, dm_we,
im_addr, im_do, dm_addr, dm_di, dm_do,
dm_be, is_signed,
// To Instruction Memory
im_addr_out, im_data,
// TO IO
io_addr, io_en, io_we, io_data_read, io_data_write
);
parameter
WORD_DEPTH = 256,
WORD_DEPTH_LOG = 8;
localparam
DEV_IM = 1,
DEV_DM = 2,
DEV_IO = 3,
DEV_UNKN = 4;
// Clock, reset, data memory write enable
input wire clk, resetb, dm_we;
// IM address, DM address, DM data in
input wire [31:0] im_addr, dm_addr, dm_di;
// DM data byte enable, non-encoded
input wire [3:0] dm_be;
// DM sign extend or unsigned extend
input wire is_signed;
// IM addr out to ROM
output wire [11:2] im_addr_out;
// IM data from ROM, IO data from IO bank
input wire [31:0] im_data, io_data_read;
// IO data to IO bank, DM data output
output reg [31:0] io_data_write, dm_do;
// A temporary register for dm_do
reg [31:0] dm_do_tmp;
// IM data output
output reg [31:0] im_do;
// IO address to IO bank
output reg [7:0] io_addr;
// IO enable, IO write enable
output reg io_en, io_we;
// Shift bytes and half words to correct bank
reg [31:0] dm_di_shift;
// Address mapped to BRAM address
reg [WORD_DEPTH_LOG-1:2] ram_addr;
// BRAM write enable
reg ram_we;
// BRAM data output
wire [31:0] ram_do;
// BRAM data input
reg [31:0] ram_di;
// Selected device
integer chosen_device_tmp;
// Selected device, pipelined
reg [2:0] chosen_device_p;
// DM byte enable, pipelined
reg [3:0] dm_be_p;
// MMU signed/unsigned extend, pipelined
reg is_signed_p;
// IO Read input, IO read input pipelined, IO write output
reg [31:0] io_data_read_tmp, io_data_read_p, io_data_write_tmp;
// IO address
reg [7:0] io_addr_tmp;
// IO enable, IO write enable
reg io_en_tmp, io_we_tmp;
// In this implementaion, the IM ROM address is simply the 11:2 bits of IM address input
assign im_addr_out[11:2] = im_addr[11:2];
// BRAM bank in interleaved configuration
BRAM_SSP #(
.DEPTH(WORD_DEPTH>>2), .DEPTH_LOG(WORD_DEPTH_LOG-2), .WIDTH(8)
) ram0 (
.clk(clk), .we(ram_we), .en(dm_be[0]),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.di(ram_di[0+:8]), .do(ram_do[0+:8])
);
BRAM_SSP
#(
.DEPTH(WORD_DEPTH>>2), .DEPTH_LOG(WORD_DEPTH_LOG-2), .WIDTH(8)
)
ram1 (
.clk(clk), .we(ram_we), .en(dm_be[1]),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.di(ram_di[8+:8]), .do(ram_do[8+:8])
);
BRAM_SSP
#(
.DEPTH(WORD_DEPTH>>2), .DEPTH_LOG(WORD_DEPTH_LOG-2), .WIDTH(8)
)
ram2 (
.clk(clk), .we(ram_we), .en(dm_be[2]),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.di(ram_di[16+:8]), .do(ram_do[16+:8])
);
BRAM_SSP
#(
.DEPTH(WORD_DEPTH>>2), .DEPTH_LOG(WORD_DEPTH_LOG-2), .WIDTH(8)
)
ram3 (
.clk(clk), .we(ram_we), .en(dm_be[3]),
.addr(ram_addr[WORD_DEPTH_LOG-1:2]),
.di(ram_di[24+:8]), .do(ram_do[24+:8])
);
// The MMU pipeline
always @ (posedge clk, negedge resetb) begin : MMU_PIPELINE
if (!resetb) begin
chosen_device_p <= 2'bX;
is_signed_p <= 1'bX;
dm_be_p <= 4'b0;
// First instruction is initialized as NOP
im_do <= 32'b0000_0000_0000_00000_000_00000_0010011;
io_data_write <= 32'bX;
io_en <= 1'b0;
io_we <= 1'b0;
io_addr <= 8'bX;
end
else if (clk) begin
// Notice the pipeline. The naming is a bit inconsistent
dm_be_p <= dm_be;
chosen_device_p <= chosen_device_tmp;
is_signed_p <= is_signed;
im_do <= im_data;
io_data_write <= io_data_write_tmp;
io_en <= io_en_tmp;
io_we <= io_we_tmp;
io_addr <= io_addr_tmp;
end
end
reg [31:0] ram_addr_temp, io_addr_temp;
// Device mapping from address
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_ADDR_MAP
ram_addr_temp = dm_addr - 32'h10000000;
io_addr_temp = dm_addr - 32'h80000000;
io_en_tmp = 1'b0;
io_we_tmp = 1'b0;
io_data_write_tmp = 32'bX;
ram_we = 1'b0;
ram_addr = {WORD_DEPTH_LOG-1{1'bX}};
ram_di = 32'bX;
chosen_device_tmp = DEV_UNKN;
if (dm_addr[31:12] == 20'b0) begin
// 0x00000000 - 0x00000FFF
chosen_device_tmp = DEV_IM;
end
else if (dm_addr[31] == 1'b0 && dm_addr[30:28] != 3'b0) begin
// 0x10000000 - 0x7FFFFFFF
ram_addr = ram_addr_temp[2+:WORD_DEPTH_LOG];
ram_di = dm_di_shift;
ram_we = dm_we;
chosen_device_tmp = DEV_DM;
end
else if (dm_addr[31:8] == 24'h800000) begin
// 0x80000000 - 0x800000FF
io_addr_tmp = io_addr_temp[7:0];
io_en_tmp = 1'b1;
io_we_tmp = dm_we;
io_data_write_tmp = dm_di_shift;
chosen_device_tmp = DEV_IO;
end
end // block: DM_ADDR_MAP
// Shifting input byte/halfword to correct position
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_IN_SHIFT
dm_di_shift = 32'bX;
// Byte enable
if (dm_be == 4'b1111) begin
dm_di_shift = dm_di;
end
else if (dm_be == 4'b1100) begin
dm_di_shift[16+:16] = dm_di[0+:16];
end
else if (dm_be == 4'b0011) begin
dm_di_shift[0+:16] = dm_di[0+:16];
end
else if (dm_be == 4'b0001) begin
dm_di_shift[0+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b0010) begin
dm_di_shift[8+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b0100) begin
dm_di_shift[16+:8] = dm_di[0+:8];
end
else if (dm_be == 4'b1000) begin
dm_di_shift[24+:8] = dm_di[0+:8];
end
end // block: DM_IN_SHIFT
// Shifting byte/halfword to correct output position
// Note: X-Optimism might be a problem. Convert to Tertiary to fix
always @ (*) begin : DM_OUT_SHIFT
case (chosen_device_p)
DEV_DM:
dm_do_tmp = ram_do;
DEV_IO:
dm_do_tmp = io_data_read;
default:
dm_do_tmp = 32'bX;
endcase // case (chosen_device_reg)
// Byte enable
dm_do = 32'bX;
if (dm_be_p == 4'b1111) begin
dm_do = dm_do_tmp;
end
else if (dm_be_p == 4'b1100) begin
if (is_signed_p)
dm_do = {{16{dm_do_tmp[31]}}, dm_do_tmp[16+:16]};
else
dm_do = {16'b0, dm_do_tmp[16+:16]};
end
else if (dm_be_p == 4'b0011) begin
if (is_signed_p)
dm_do = {{16{dm_do_tmp[15]}}, dm_do_tmp[0+:16]};
else
dm_do = {16'b0, dm_do_tmp[0+:16]};
end
else if (dm_be_p == 4'b0001) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[7]}}, dm_do_tmp[0+:8]};
else
dm_do = {24'b0, dm_do_tmp[0+:8]};
end
else if (dm_be_p == 4'b0010) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[15]}}, dm_do_tmp[8+:8]};
else
dm_do = {24'b0, dm_do_tmp[8+:8]};
end
else if (dm_be_p == 4'b0100) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[23]}}, dm_do_tmp[16+:8]};
else
dm_do = {24'b0, dm_do_tmp[16+:8]};
end
else if (dm_be_p == 4'b1000) begin
if (is_signed_p)
dm_do = {{24{dm_do_tmp[31]}}, dm_do_tmp[24+:8]};
else
dm_do = {24'b0, dm_do_tmp[24+:8]};
end
end
endmodule // mmu |
module regfile_tb();
reg clk_tb, resetb_tb, we_rd_tb;
reg [4:0] a_rs1_tb, a_rs2_tb, a_rd_tb;
wire [31:0] d_rs1_tb, d_rs2_tb;
reg [31:0] d_rd_tb;
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
// Test 1: writes 16, 15, 14, 13, 12,... to registers x0, x1, x2, x3, x4,...
// Rs1 and Rs2 reads with delay of 1 and 2 clocks, respectively
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Basic R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x31, x0, x1, ...");
$display("(TT) 3. RS2 reads x30, x31, x0, x1, ...");
$display("(TT) 4. RS1 should read X, 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
// Writeback addr
a_rd_tb = i;
// Writeback data
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
// RS1 addr
a_rs1_tb = i - 1;
// RS2 addr
a_rs2_tb = i - 2;
#0; // Wait for combinational to complete
// Then display results
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask //
// Test 2: Forwarding test
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Forwarding R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x0, x1, ...");
$display("(TT) 3. RS2 reads x31, x0, x1, ...");
$display("(TT) 4. RS1 should read 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
// Writeback addr
a_rd_tb = i;
// Writeback data
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
// RS1 addr
a_rs1_tb = i;
// RS2 addr
a_rs2_tb = i - 1;
#0; // Wait for combinational to complete
// Then display results
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask //
regfile UUT(
.clk(clk_tb), .resetb(resetb_tb),
.a_rs1(a_rs1_tb), .d_rs1(d_rs1_tb),
.a_rs2(a_rs2_tb), .d_rs2(d_rs2_tb),
.a_rd(a_rd_tb), .d_rd(d_rd_tb),
.we_rd(we_rd_tb)
);
// Run the tests
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/regfile_tb.vcd");
$dumpvars(0,regfile_tb);
@(posedge clk_tb);
// Test 1
run_test1();
// Test 2
run_test2();
$finish;
end
endmodule // regfile_tb |
module csr_ehu
(
// Stateful
clk, resetb, XB_bubble,
// Control
read, write, set, clear, imm, a_rd,
initiate_exception,
// Exception In
XB_FD_exception_illegal_instruction,
XB_FD_exception_ecall,
XB_FD_exception_ebreak,
XB_FD_exception_instruction_misaligned,
XB_FD_exception_load_misaligned,
XB_FD_exception_store_misaligned,
irq_mtimecmp,
// Data
src_dst, d_rs1, uimm, FD_aluout,
nextPC, XB_pc,
data_out, csr_mepc, csr_mtvec
);
`include "core/csrlist.vh"
input wire clk, resetb, XB_bubble;
// CSR read, write, set, clear; imm means operand is an immediate
// or from register
input wire read, write, set, clear, imm;
input wire [4:0] a_rd;
input wire [11:0] src_dst;
input wire [31:2] XB_pc;
input wire [31:0] d_rs1, FD_aluout, nextPC;
input wire [4:0] uimm;
input wire XB_FD_exception_illegal_instruction;
input wire XB_FD_exception_ecall;
input wire XB_FD_exception_ebreak;
input wire XB_FD_exception_instruction_misaligned;
input wire XB_FD_exception_load_misaligned;
input wire XB_FD_exception_store_misaligned;
input wire irq_mtimecmp;
output reg [31:0] data_out;
output reg initiate_exception;
output wire [31:0] csr_mepc;
output wire [31:0] csr_mtvec;
reg XB_exception_illegal_instruction;
reg [31:2] mepc;
reg [31:0] mscratch, mcause, mtval;
reg [31:2] mtvec;
reg mpie, mie;
reg mtie;
reg [63:0] mcycle, minstret;
reg irq_mtimecmp_p;
wire FD_exception, XB_exception;
// Output for PC update
assign csr_mepc = {mepc[31:2], 2'b0};
// Output for Machine Trap Vector Base Addr
assign csr_mtvec = {mtvec[31:2], 2'b0};
// Exception Handling Unit. XB exceptions have higher priority
// since XB instruction is senior. XB must not be a bubble
reg initiate_irq_mtimecmp,
initiate_illinst, initiate_misaligned,
initiate_ecall, initiate_ebreak;
always @ (*) begin : EXCEPTION_HANDLING_UNIT
// Timer interrupt is executed only once
initiate_irq_mtimecmp
= mtie & irq_mtimecmp & ~irq_mtimecmp_p;
initiate_ecall
= ~XB_bubble & XB_FD_exception_ecall;
initiate_ebreak
= ~XB_bubble & XB_FD_exception_ebreak;
initiate_illinst
= ~XB_bubble & (XB_exception_illegal_instruction |
XB_FD_exception_illegal_instruction);
initiate_misaligned
= ~XB_bubble & (XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned);
initiate_exception = initiate_irq_mtimecmp
| initiate_ecall | initiate_ebreak
| initiate_illinst | initiate_misaligned;
//initiate_exception = initiate_illinst | initiate_misaligned;
end
// There exists an exception from FD stage
assign FD_exception = XB_FD_exception_illegal_instruction |
XB_FD_exception_ecall |
XB_FD_exception_ebreak |
XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned;
// There exists an exception from XB stage
assign XB_exception = XB_exception_illegal_instruction | initiate_irq_mtimecmp;
// The operand to operate on target CSR
wire [31:0] operand;
assign operand = imm ? {27'b0, uimm} : d_rs1;
wire really_read, really_write, really_set, really_clear;
// If rd/uimm field is 0, then do not perform operation to prevent
// side effect
assign really_read = read && (a_rd != 5'b0);
assign really_write = write;
assign really_set = set && (uimm != 5'b0);
assign really_clear = clear && (uimm != 5'b0);
reg [31:0] badaddr_p, nextPC_p;
/* verilator lint_off BLKSEQ */
always @ (posedge clk) begin : CSR_PIPELINE
if (!resetb) begin
mcycle <= 64'b0;
minstret <= 64'b0;
mepc <= 30'bX;
data_out <= 32'bX;
mtvec[31:2] <= 30'h1; // or, 0x4
// No interrupt on reset
mpie <= 1'b0;
mie <= 1'b0;
mtie <= 1'b0;
badaddr_p <= 32'bX;
nextPC_p <= 32'bX;
irq_mtimecmp_p <= 1'b0;
end
else if (clk) begin
XB_exception_illegal_instruction = 1'b0;
mcycle <= mcycle + 64'b1;
// On trap, mpie is updated
if (initiate_exception) mpie <= mie;
irq_mtimecmp_p <= irq_mtimecmp;
if (!XB_bubble) begin
// Instruction is committed when it is not a bubble
minstret <= minstret + 64'b1;
end
// Badaddr is the address output from the FD ALU
badaddr_p <= FD_aluout;
nextPC_p <= nextPC;
// CSR register file
case (src_dst)
`CSR_MVENDORID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MARCHID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MIMPID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MHARTID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MSTATUS: begin
if (really_read)
data_out <= {19'b0,2'b11,3'b0,mpie,3'b0,mie,3'b0};
if (really_write) begin
mpie <= operand[7];
mie <= operand[3];
end
if (really_set) begin
mpie <= operand[7] ? 1 : mpie;
mie <= operand[3] ? 1 : mie;
end
if (really_clear) begin
mpie <= operand[7] ? 0 : mpie;
mie <= operand[3] ? 0 : mie;
end
end
`CSR_MISA: begin
// 32-bit, I subset. Read RISC-V Spec Vol 2
if (really_read) data_out <= 32'b0100_0000_0000_0000_0000_0001_0000_0000;
end
`CSR_MIE: begin
if (really_read) data_out <= {24'b0, mtie, 7'b0};
if (really_write) mtie <= operand[7];
if (really_set) mtie <= mtie | operand[7];
if (really_clear) mtie <= mtie & ~operand[7];
end
`CSR_MTVEC: begin
// Direct
if (really_read) data_out <= {mtvec[31:2], 2'b0};
if (really_write) mtvec[31:2] <= operand[31:2];
if (really_set) mtvec[31:2] <= mtvec[31:2] | operand[31:2];
if (really_clear) mtvec[31:2] <= mtvec[31:2] & ~operand[31:2];
end
`CSR_MSCRATCH: begin
if (really_read) data_out <= mscratch;
if (really_write) mscratch <= operand;
if (really_set) mscratch <= mscratch | operand;
if (really_clear) mscratch <= mscratch & ~operand;
end
`CSR_MEPC: begin
if (really_read) data_out <= {mepc, 2'b0};
if (really_write) mepc[31:2] <= operand[31:2];
if (really_set) mepc[31:2] <= mepc[31:2] | operand[31:2];
if (really_clear) mepc[31:2] <= mepc & ~operand[31:2];
end
`CSR_MCAUSE: begin
if (really_read) data_out <= mcause;
if (really_write) mcause <= operand;
if (really_set) mcause <= mcause | operand;
if (really_clear) mcause <= mcause & ~operand;
end
`CSR_MTVAL: begin
if (really_read) data_out <= mtval;
if (really_write) mtval <= operand;
if (really_set) mtval <= mtval | operand;
if (really_clear) mtval <= mtval & ~operand;
end
`CSR_MIP: begin
if (really_read) data_out <= {24'b0, irq_mtimecmp, 7'b0};
end
`CSR_MCYCLE: begin
if (really_read) data_out <= mcycle[0+:32];
if (really_write) mcycle[0+:32] <= operand;
if (really_set) mcycle[0+:32] <= mcycle[0+:32] | operand;
if (really_clear) mcycle[0+:32] <= mcycle[0+:32] & ~operand;
end
`CSR_MINSTRET: begin
if (really_read) data_out <= minstret[0+:32];
if (really_write) minstret[0+:32] <= operand;
if (really_set) minstret[0+:32] <= minstret[0+:32] | operand;
if (really_clear) minstret[0+:32] <= minstret[0+:32] & ~operand;
end
`CSR_MCYCLEH: begin
if (really_read) data_out <= mcycle[32+:32];
if (really_write) mcycle[32+:32] <= operand;
if (really_set) mcycle[32+:32] <= mcycle[32+:32] | operand;
if (really_clear) mcycle[32+:32] <= mcycle[32+:32] & ~operand;
end
`CSR_MINSTRETH: begin
if (really_read) data_out <= minstret[32+:32];
if (really_write) minstret[32+:32] <= operand;
if (really_set) minstret[32+:32] <= minstret[32+:32] | operand;
if (really_clear) minstret[32+:32] <= minstret[32+:32] & ~operand;
end
default: begin
// Performance monitors are hard wired to 0
if (src_dst[11:4] == 8'hB0 ||
src_dst[11:4] == 8'hB1 ||
src_dst[11:4] == 8'hB8 ||
src_dst[11:4] == 8'hB9 ||
src_dst[11:4] == 8'h32 ||
src_dst[11:4] == 8'h33
) begin : PERFORMANCE_MONITORS
data_out <= 32'b0;
end
else begin
// Unknown CSR raise exceptions
if (~XB_bubble & (read|write|set|clear))
XB_exception_illegal_instruction = 1'b1;
end // else: !if(src_dst[11:4] == 8'hB0 ||...
end // case: default
endcase // case (src_dst)
// Magic numbers are from RISC-V Spec Vol 2
if (XB_exception) begin
// NOTE: This confusing statement is caused by the
// internal pipeline of the CSR. CSR has one stage
// pipeline, so even though the exception is supposed to
// happen in XB stage, a CSR exception's PC is in FD stage
// Note that timer interrupt has higher priority
mepc <= XB_pc[31:2];
if (initiate_irq_mtimecmp) begin
mcause <= {1'b0, 31'd7};
mtval <= 32'b0;
end
else if (XB_exception_illegal_instruction) begin
mcause <= 32'd2; // Illegal Instruction
mtval <= 32'b0;
end
end
else if (FD_exception) begin
mepc <= XB_pc[31:2];
if (XB_FD_exception_instruction_misaligned) begin
mcause <= 32'd0;
mtval <= nextPC_p;
end
else if (XB_FD_exception_illegal_instruction) begin
mcause <= 32'd2;
mtval <= 32'b0;
end
else if (XB_FD_exception_ebreak) begin
mcause <= 32'd3;
end
else if (XB_FD_exception_load_misaligned) begin
mcause <= 32'd4;
mtval <= badaddr_p;
end
else if (XB_FD_exception_store_misaligned) begin
mcause <= 32'd6;
mtval <= badaddr_p;
end
else if (XB_FD_exception_ecall) begin
mcause <= 32'd11;
end
end // if (FD_exception)
end // if (clk)
end // block: CSR_PIPELINE
/* verilator lint_on BLKSEQ */
endmodule // csrrf |
module instruction_decoder
(
// Inputs
inst,
// Outputs
immediate,
alu_is_signed, aluop1_sel, aluop2_sel, alu_op,
pc_update, pc_mepc,
regwrite, jump, link, jr, br,
dm_be, dm_we, mem_is_signed,
csr_read, csr_write, csr_set, csr_clear, csr_imm,
a_rs1, a_rs2, a_rd, funct3, funct7,
// Exceptions
bug_invalid_instr_format_onehot,
exception_unsupported_category,
exception_illegal_instruction,
exception_load_misaligned,
exception_store_misaligned
);
`include "core/aluop.vh"
`include "core/opcode.vh"
// The instruction to be decoded
input wire [31:0] inst;
// Immediate value
output [31:0] immediate;
// Signed/Unsigned operation for XB ALU
output alu_is_signed;
// Select XB ALU: Operator 1, Operator 2, Operation
output [31:0] aluop1_sel, aluop2_sel, alu_op;
// Whether special PC update is needed, whether update pc with MEPC
output pc_update, pc_mepc;
// Whether a writeback is needed in XB
output regwrite;
// The instruction needs to Jump, Link, or Jump Register
output jump, link, jr;
// The instruction is Branch
output br;
// Data Memory Byte Enable
output [3:0] dm_be;
// Data Memory write enable
output dm_we;
// Treat memory item as Signed/Unsigned
output mem_is_signed;
// Control Status Register operations
output csr_read, csr_write, csr_set, csr_clear, csr_imm;
// Register address: RS1, RS2, Rd writeback
output [4:0] a_rs1, a_rs2, a_rd;
// The funct3 field
output [2:0] funct3;
// The funct7 field
output [6:0] funct7;
// This shall be refactored to assert()
output bug_invalid_instr_format_onehot;
// Exceptions to be raised
output exception_unsupported_category;
output exception_illegal_instruction;
output exception_load_misaligned;
output exception_store_misaligned;
// Opcode field
wire [6:0] opcode;
assign opcode = inst[6:0];
// One-hot encoded instruction format
reg [5:0] instr_IURJBS;
// Logic to identify immediate format using opcode
always @ (*) begin : INSTRUCTION_FORMAT
case (opcode[6:2])
// I-Types
`OP_IMM: instr_IURJBS = 6'b100000;
`JALR: instr_IURJBS = 6'b100000;
`LOAD: instr_IURJBS = 6'b100000;
`MISC_MEM: instr_IURJBS = 6'b100000;
`OP_IMM: instr_IURJBS = 6'b100000;
`SYSTEM: instr_IURJBS = 6'b100000;
// U-Types
`LUI: instr_IURJBS = 6'b010000;
`AUIPC: instr_IURJBS = 6'b010000;
// R-Types
`OP: instr_IURJBS = 6'b001000;
// J-Types
`JAL: instr_IURJBS = 6'b000100;
// B-Types
`BRANCH: instr_IURJBS = 6'b000010;
// S-Types
`STORE: instr_IURJBS = 6'b000001;
// Unsupported
default: instr_IURJBS = 6'bX;
endcase // case (opcode[6:2])
end // block: INSTRUCTION_FORMAT
// The immediate value, extended to 32-bit
reg [31:0] immediate;
// Logic to decode immediate value. Read the RISC-V spec Vol. 1 for
// details
always @ (*) begin : IMMEDIATE_DECODE
case (instr_IURJBS)
6'b100000: begin : I_TYPE
// Certain instructions use a different I-immediate format
immediate
= (opcode[6:2] == `OP_IMM
&&
(funct3 == 3'b101 || funct3 == 3'b001))
? {27'b0, inst[24:20]}
: {{21{inst[31]}}, inst[30:20]};
end
6'b010000: immediate = {inst[31:12], 12'b0};
6'b001000: immediate = 32'bX;
6'b000100: immediate = {{12{inst[31]}}, inst[19:12], inst[20], inst[30:21], 1'b0};
6'b000010: immediate = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0};
6'b000001: immediate = {{21{inst[31]}}, inst[30:25], inst[11:8], inst[7]};
default: begin
immediate = 32'bX;
end
endcase // case (instr_IURJBS)
end // block: IMMEDIATE_DECODE
wire [2:0] funct3;
wire [6:0] funct7;
assign funct3 = inst[14:12];
assign funct7 = inst[31:25];
reg alu_is_signed, pc_update, pc_mepc, regwrite, jump, link, jr;
reg br;
reg [3:0] dm_be;
reg dm_we;
reg mem_is_signed;
reg csr_read, csr_write, csr_set, csr_clear, csr_imm;
reg [4:0] a_rs1, a_rs2, a_rd;
reg exception_unsupported_category;
reg exception_illegal_instruction;
reg exception_load_misaligned;
reg exception_store_misaligned;
integer aluop1_sel, aluop2_sel, alu_op;
// Logic to generate control signals
always @ (*) begin : CONTROL_SIG_GENERATOR
// Default register fields
a_rs1 = inst[19:15];
a_rs2 = inst[24:20];
a_rd = inst[11:7];
// Default ALU selections
alu_is_signed = 1'b1;
aluop1_sel = `ALUOP1_RS1;
aluop2_sel = `ALUOP2_UNKN;
alu_op = `ALU_UNKN;
// Default write actions
regwrite = 1'b0;
pc_update = 1'b0;
pc_mepc = 1'b0;
// Default memory actions
dm_be = 4'b0;
dm_we = 1'b0;
// Default branch actions
jump = 1'b0;
jr = 1'b0;
link = 1'b0;
br = 1'b0;
// Default CSR actions
csr_read = 1'b0;
csr_write = 1'b0;
csr_set = 1'b0;
csr_clear = 1'b0;
csr_imm = 1'b0;
// Default no exception
exception_unsupported_category = 1'b0;
exception_illegal_instruction = 1'b0;
exception_load_misaligned = 1'b0;
exception_store_misaligned = 1'b0;
// Decoding opcode. Read the RISC-V Spec Vol 1.
case (opcode[6:2])
`OP_IMM: begin
// Immediate operation
regwrite = 1'b1;
aluop2_sel = `ALUOP2_IMM;
case (funct3)
3'b000: begin : ADDI
alu_op = `ALU_ADD;
end
3'b001: begin : SLLI
alu_op = `ALU_SLL;
end
3'b010: begin : SLTI
alu_op = `ALU_SLT;
end
3'b011: begin : SLTIU
alu_op = `ALU_SLT;
alu_is_signed = 1'b0;
end
3'b100: begin : XORI
alu_op = `ALU_XOR;
end
3'b101: begin : SRLI_SRAI
alu_op = inst[30] ? `ALU_SRA : `ALU_SRL;
end
3'b110: begin : ORI
alu_op = `ALU_OR;
end
3'b111: begin : ANDI
alu_op = `ALU_AND;
end
endcase // case (funct3)
end // case: OP_IMM
`LUI: begin
// LUI loads immediate into high-20 bits of register
// Operation is: imm + 0
aluop2_sel = `ALUOP2_IMM;
alu_op = `ALU_ADD;
regwrite = 1'b1;
// 0 + imm
a_rs1 = 5'd0;
end
`AUIPC: begin
// AUIPC loads upper-20 bits of PC, adds immediate, and
// saves into register
regwrite = 1'b1;
aluop1_sel = `ALUOP1_PC;
aluop2_sel = `ALUOP2_IMM;
alu_op = `ALU_ADD;
end
`OP: begin
// Register-Register integer operation
regwrite = 1'b1;
aluop2_sel = `ALUOP2_RS2;
case (funct3)
3'b000: begin : ADD_SUB
if (funct7[5]) begin : SUB
alu_op = `ALU_SUB;
end
else begin : ADD
alu_op = `ALU_ADD;
end
end
3'b001: begin : SLL
alu_op = `ALU_SLL;
end
3'b010: begin : SLT
alu_op = `ALU_SLT;
end
3'b011: begin : SLTU
alu_op = `ALU_SLT;
alu_is_signed = 1'b0;
end
3'b100: begin : XOR
alu_op = `ALU_XOR;
end
3'b101: begin : SRL_SRA
alu_op = funct7[5] ? `ALU_SRA : `ALU_SRL;
// if (funct7[5]) begin : SRA
// alu_op = `ALU_SRA;
// end
// else begin : SRL
// alu_op = `ALU_SRL;
// end
end
3'b110: begin : OR
alu_op = `ALU_OR;
end
3'b111: begin : AND
alu_op = `ALU_AND;
end
endcase // case (funct3)
end
`JAL: begin
// Jump and link. Addition is performed in XB
// stage. Operands are loaded in the Core module, so it
// does not matter here
jump = 1'b1;
link = 1'b1;
regwrite = 1'b1;
alu_op = `ALU_ADD;
aluop2_sel = `ALUOP2_RS2;
end
`JALR: begin
// Jump and link register. Addition is performed in XB
// stage. Operands are loaded in the Core module, so it
// does not matter here
jr = 1'b1;
link = 1'b1;
regwrite = 1'b1;
alu_op = `ALU_ADD;
aluop2_sel = `ALUOP2_RS2;
end
`BRANCH: begin
// Branch instructions
br = 1'b1;
case (funct3)
3'b000,3'b001,3'b100,3'b101,3'b110,3'b111: begin
// Do nothing here. Let comparator choose for itself
end
default: begin
exception_illegal_instruction = 1'b1;
end
endcase // case (funct3)
end
`LOAD: begin
// LW, LH, LB use different byte enables
regwrite = 1'b1;
case (funct3)
3'b000, 3'b100: begin : LB
mem_is_signed = (funct3 == 3'b000) ? 1'b1 : 1'b0;
case (immediate[1:0])
2'b00: begin
dm_be = 4'b0001;
end
2'b01: begin
dm_be = 4'b0010;
end
2'b10: begin
dm_be = 4'b0100;
end
2'b11: begin
dm_be = 4'b1000;
end
default:
dm_be = 4'bX;
endcase // case (immediate[1:0])
end
3'b001, 3'b101: begin : LH
mem_is_signed = (funct3 == 3'b001) ? 1'b1 : 1'b0;
exception_load_misaligned = immediate[0] ? 1'b1 : 1'b0;
dm_be = immediate[0] ? 4'b0000
: immediate[1] ? 4'b1100 : 4'b0011;
end
3'b010: begin : LW
dm_be = 4'b1111;
exception_load_misaligned
= (immediate[0] | immediate[1]) ? 1'b1 : 1'b0;
end
default: begin
exception_illegal_instruction = 1'b1;
end
endcase // case (funct3)
end
`STORE: begin
// SW, SH, SB use different byte enables
dm_we = 1'b1;
case (funct3)
3'b000: begin : SB
case (immediate[1:0])
2'b00: begin
dm_be = 4'b0001;
end
2'b01: begin
dm_be = 4'b0010;
end
2'b10: begin
dm_be = 4'b0100;
end
2'b11: begin
dm_be = 4'b1000;
end
endcase // case (immediate[1:0])
end
3'b001: begin : SH
exception_store_misaligned = immediate[0] ? 1'b1 : 1'b0;
dm_be = immediate[0] ? 4'b0
: immediate[1] ? 4'b1100 : 4'b0011;
// if (immediate[0])
// exception_store_misaligned = 1'b1;
// else begin
// if (immediate[1])
// dm_be = 4'b1100;
// else
// dm_be = 4'b0011;
// end
end
3'b010: begin : SW
dm_be = 4'b1111;
exception_store_misaligned
= (immediate[0] | immediate[1]) ? 1'b1 : 1'b0;
// if (immediate[0] | immediate[1])
// exception_store_misaligned = 1'b1;
end
default: begin
exception_illegal_instruction = 1'b1;
end
endcase // case (funct3)
end
`MISC_MEM: begin
// NOP since this core is in order commit
end
`SYSTEM: begin
// Environment instructions are implemented via software
// trap
case (funct3)
3'b000: begin : ECALL_EBREAK_RET
case (funct7)
7'b0: begin : ECALL_EBREAK_URET
// Software trap
exception_illegal_instruction = 1'b1;
end
7'b0001000: begin : SRET_WFI
// Software trap
exception_illegal_instruction = 1'b1;
end
7'b0011000: begin : MRET
// MRET jumps to MEPC
pc_update = 1'b1;
pc_mepc = 1'b1;
end
default: begin
exception_illegal_instruction = 1'b1;
end
endcase // case (funct7)
end
3'b001: begin : CSRRW
regwrite = 1'b1;
csr_read = 1'b1;
csr_write = 1'b1;
end
3'b010: begin : CSRRS
regwrite = 1'b1;
csr_read = 1'b1;
csr_set = 1'b1;
end
3'b011: begin : CSRRC
regwrite = 1'b1;
csr_read = 1'b1;
csr_clear = 1'b1;
end
3'b101: begin : CSRRWI
regwrite = 1'b1;
csr_read = 1'b1;
csr_write = 1'b1;
csr_imm = 1'b1;
end
3'b110: begin : CSRRSI
regwrite = 1'b1;
csr_read = 1'b1;
csr_set = 1'b1;
csr_imm = 1'b1;
end
3'b111: begin : CSRRCI
regwrite = 1'b1;
csr_read = 1'b1;
csr_clear = 1'b1;
csr_imm = 1'b1;
end
default: begin
exception_illegal_instruction = 1'b1;
end
endcase // case (funct3)
end
default: begin
exception_unsupported_category = 1'b1;
end
endcase // case (opcode[6:2])
if (exception_unsupported_category
| exception_illegal_instruction
| exception_load_misaligned
| exception_store_misaligned) begin
regwrite = 1'b0;
end
// Lower two bits are always 11
// exception_unsupported_category
// = (opcode[1:0] != 2'b11) ? 1'b1 : 1'b0;
// if (opcode[1:0] != 2'b11)
// exception_unsupported_category = 1'b1;
end
endmodule // instruction_decoder |
module csr_ehu
(
// Stateful
clk, resetb, XB_bubble,
// Control
read, write, set, clear, imm, a_rd,
initiate_illinst, initiate_misaligned,
// Exception In
XB_FD_exception_unsupported_category,
XB_FD_exception_illegal_instruction,
XB_FD_exception_instruction_misaligned,
XB_FD_exception_load_misaligned,
XB_FD_exception_store_misaligned,
// Data
src_dst, d_rs1, uimm, FD_pc, XB_pc, data_out, csr_mepc
);
`include "core/csrlist.vh"
input wire clk, resetb, XB_bubble;
// CSR read, write, set, clear; imm means operand is an immediate
// or from register
input wire read, write, set, clear, imm;
input wire [4:0] a_rd;
input wire [11:0] src_dst;
input wire [31:0] FD_pc, XB_pc, d_rs1;
input wire [4:0] uimm;
input wire XB_FD_exception_unsupported_category;
input wire XB_FD_exception_illegal_instruction;
input wire XB_FD_exception_instruction_misaligned;
input wire XB_FD_exception_load_misaligned;
input wire XB_FD_exception_store_misaligned;
output reg [31:0] data_out;
output reg initiate_illinst, initiate_misaligned;
output wire [31:0] csr_mepc;
reg XB_exception_illegal_instruction;
reg [31:0] mepc;
reg [31:0] mscratch, mcause, mtval;
reg [63:0] mcycle, minstret;
wire initiate_exception;
wire FD_exception, XB_exception;
// There exists an exception from FD stage
assign FD_exception = XB_FD_exception_unsupported_category |
XB_FD_exception_illegal_instruction |
XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned;
// There exists an exception from XB stage
assign XB_exception = XB_exception_illegal_instruction;
// There exists an exception
assign initiate_exception = XB_exception | FD_exception;
// Output for PC update
assign csr_mepc = mepc;
// Exception Handling Unit. XB exceptions have higher priority
// since XB instruction is senior. XB must not be a bubble
always @ (*) begin : EXCEPTION_HANDLING_UNIT
initiate_illinst
= ~XB_bubble & (XB_exception_illegal_instruction |
XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category);
initiate_misaligned
= ~XB_bubble & (XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned);
end
// The operand to operate on target CSR
wire [31:0] operand;
assign operand = imm ? {27'b0, uimm} : d_rs1;
wire really_read, really_write, really_set, really_clear;
// If rd/uimm field is 0, then do not perform operation to prevent
// side effect
assign really_read = read && (a_rd != 5'b0);
assign really_write = write && !(imm && uimm == 5'b0);
assign really_set = set && (uimm != 5'b0);
assign really_clear = clear && (uimm != 5'b0);
always @ (posedge clk, negedge resetb) begin : CSR_PIPELINE
if (!resetb) begin
mcycle <= 64'b0;
minstret <= 64'b0;
mepc <= 32'bX;
data_out <= 32'bX;
end
else if (clk) begin
XB_exception_illegal_instruction = 1'b0;
mcycle <= mcycle + 64'b1;
if (!XB_bubble) begin
// Instruction is committed when it is not a bubble
minstret <= minstret + 64'b1;
end
// CSR register file
case (src_dst)
`CSR_MVENDORID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MARCHID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MIMPID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MHARTID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MISA: begin
// 32-bit, I subset. Read RISC-V Spec Vol 2
if (really_read) data_out <= 32'b0100_0000_0000_0000_0000_0001_0000_0000;
end
`CSR_MTVEC: begin
// Direct
if (really_read) data_out <= 32'b0;
end
`CSR_MSCRATCH: begin
if (really_read) data_out <= mscratch;
if (really_write) mscratch <= operand;
if (really_set) mscratch <= mscratch | operand;
if (really_clear) mscratch <= mscratch & ~operand;
end
`CSR_MEPC: begin
if (really_read) data_out <= mepc;
if (really_write) mepc <= operand;
if (really_set) mepc <= mepc | operand;
if (really_clear) mepc <= mepc & ~operand;
end
`CSR_MCAUSE: begin
if (really_read) data_out <= mcause;
if (really_write) mcause <= operand;
if (really_set) mcause <= mcause | operand;
if (really_clear) mcause <= mcause & ~operand;
end
`CSR_MTVAL: begin
if (really_read) data_out <= mtval;
if (really_write) mtval <= operand;
if (really_set) mtval <= mtval | operand;
if (really_clear) mtval <= mtval & ~operand;
end
`CSR_MCYCLE: begin
if (really_read) data_out <= mcycle[0+:32];
if (really_write) mcycle[0+:32] <= operand;
if (really_set) mcycle[0+:32] <= mcycle[0+:32] | operand;
if (really_clear) mcycle[0+:32] <= mcycle[0+:32] & ~operand;
end
`CSR_MINSTRET: begin
if (really_read) data_out <= minstret[0+:32];
if (really_write) minstret[0+:32] <= operand;
if (really_set) minstret[0+:32] <= minstret[0+:32] | operand;
if (really_clear) minstret[0+:32] <= minstret[0+:32] & ~operand;
end
`CSR_MCYCLEH: begin
if (really_read) data_out <= mcycle[32+:32];
if (really_write) mcycle[32+:32] <= operand;
if (really_set) mcycle[32+:32] <= mcycle[32+:32] | operand;
if (really_clear) mcycle[32+:32] <= mcycle[32+:32] & ~operand;
end
`CSR_MINSTRETH: begin
if (really_read) data_out <= minstret[32+:32];
if (really_write) minstret[32+:32] <= operand;
if (really_set) minstret[32+:32] <= minstret[32+:32] | operand;
if (really_clear) minstret[32+:32] <= minstret[32+:32] & ~operand;
end
default: begin
// Performance monitors are hard wired to 0
if (src_dst[11:4] == 8'hB0 ||
src_dst[11:4] == 8'hB1 ||
src_dst[11:4] == 8'hB8 ||
src_dst[11:4] == 8'hB9 ||
src_dst[11:4] == 8'h32 ||
src_dst[11:4] == 8'h33
) begin : PERFORMANCE_MONITORS
data_out <= 32'b0;
end
else begin
// Unknown CSR raise exceptions
if (~XB_bubble & (read|write|set|clear))
XB_exception_illegal_instruction = 1'b1;
end // else: !if(src_dst[11:4] == 8'hB0 ||...
end // case: default
endcase // case (src_dst)
// Magic numbers are from RISC-V Spec Vol 2
if (XB_exception) begin
// NOTE: This confusing statement is caused by the
// internal pipeline of the CSR. CSR has one stage
// pipeline, so even though the exception is supposed to
// happen in XB stage, a CSR exception's PC is in FD stage
mepc <= FD_pc;
mcause <= 32'd2; // Illegal Instruction
end
else if (FD_exception) begin
mepc <= XB_pc;
if (XB_FD_exception_instruction_misaligned) begin
mcause <= 32'd0;
end
else if (XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category) begin
mcause <= 32'd2;
end
else if (XB_FD_exception_load_misaligned) begin
mcause <= 32'd4;
end
else if (XB_FD_exception_store_misaligned) begin
mcause <= 32'd6;
end
end
end // if (clk)
end // block: CSR_PIPELINE
endmodule // csrrf |
module iob_cache_back_end #(
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
input clk_i,
input cke_i,
input arst_i,
// write-through-buffer
input write_valid_i,
input [ FE_ADDR_W-1 : FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] write_addr_i,
input [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFFSET_W)-FE_DATA_W)-1 : 0] write_wdata_i,
input [ FE_NBYTES-1:0] write_wstrb_i,
output write_ready_o,
// cache-line replacement
input replace_valid_i,
input [FE_ADDR_W-1:BE_NBYTES_W + LINE2BE_W] replace_addr_i,
output replace_o,
output read_valid_o,
output [ LINE2BE_W -1:0] read_addr_o,
output [ BE_DATA_W -1:0] read_rdata_o,
// back-end memory interface
output be_valid_o,
output [BE_ADDR_W -1:0] be_addr_o,
output [ BE_DATA_W-1:0] be_wdata_o,
output [ BE_NBYTES-1:0] be_wstrb_o,
input [ BE_DATA_W-1:0] be_rdata_i,
input be_rvalid_i,
input be_ready_i
);
wire [BE_ADDR_W-1:0] be_addr_read, be_addr_write;
wire be_valid_read, be_valid_write;
wire be_ack;
wire be_wack;
wire be_wack_r;
assign be_addr_o = (be_valid_read) ? be_addr_read : be_addr_write;
assign be_valid_o = be_valid_read | be_valid_write;
assign be_ack = be_rvalid_i | be_wack_r;
assign be_wack = be_ready_i & be_valid_o & (| be_wstrb_o);
iob_reg_re #(
.DATA_W (1),
.RST_VAL(0)
) iob_reg_be_wack (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (1'b1),
.data_i(be_wack),
.data_o(be_wack_r)
);
iob_cache_read_channel #(
.FE_ADDR_W (FE_ADDR_W),
.FE_DATA_W (FE_DATA_W),
.BE_ADDR_W (BE_ADDR_W),
.BE_DATA_W (BE_DATA_W),
.WORD_OFFSET_W(WORD_OFFSET_W)
) read_fsm (
.clk_i (clk_i),
.reset_i (arst_i),
.replace_valid_i(replace_valid_i),
.replace_addr_i (replace_addr_i),
.replace_o (replace_o),
.read_valid_o (read_valid_o),
.read_addr_o (read_addr_o),
.read_rdata_o (read_rdata_o),
.be_addr_o (be_addr_read),
.be_valid_o (be_valid_read),
.be_ack_i (be_ack),
.be_rdata_i (be_rdata_i)
);
iob_cache_write_channel #(
.ADDR_W (FE_ADDR_W),
.DATA_W (FE_DATA_W),
.BE_ADDR_W (BE_ADDR_W),
.BE_DATA_W (BE_DATA_W),
.WRITE_POL (WRITE_POL),
.WORD_OFFSET_W(WORD_OFFSET_W)
) write_fsm (
.clk_i(clk_i),
.reset_i(arst_i),
.valid_i(write_valid_i),
.addr_i (write_addr_i),
.wstrb_i(write_wstrb_i),
.wdata_i(write_wdata_i),
.ready_o(write_ready_o),
.be_addr_o (be_addr_write),
.be_valid_o(be_valid_write),
.be_ack_i (be_ack),
.be_wdata_o(be_wdata_o),
.be_wstrb_o(be_wstrb_o)
);
endmodule |
module iob_cache_axi #(
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter NWAYS_W = `IOB_CACHE_NWAYS_W,
parameter NLINES_W = `IOB_CACHE_NLINES_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WTBUF_DEPTH_W = `IOB_CACHE_WTBUF_DEPTH_W,
parameter REP_POLICY = `IOB_CACHE_PLRU_MRU,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter USE_CTRL = `IOB_CACHE_USE_CTRL,
parameter USE_CTRL_CNT = `IOB_CACHE_USE_CTRL_CNT,
parameter AXI_ID_W = `IOB_CACHE_AXI_ID_W,
parameter [AXI_ID_W-1:0] AXI_ID = `IOB_CACHE_AXI_ID,
parameter AXI_LEN_W = `IOB_CACHE_AXI_LEN_W,
parameter AXI_ADDR_W = BE_ADDR_W,
parameter AXI_DATA_W = BE_DATA_W,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W),
parameter ADDR_W = USE_CTRL+FE_ADDR_W-FE_NBYTES_W,
parameter DATA_W = FE_DATA_W
) (
`include "clk_en_rst_s_port.vs"
// Front-end interface (IOb native slave)
`include "iob_s_port.vs"
// Cache invalidate and write-trough buffer IO chain
input [1-1:0] invalidate_i,
output [1-1:0] invalidate_o,
input [1-1:0] wtb_empty_i,
output [1-1:0] wtb_empty_o,
// AXI4 back-end interface
`include "axi_m_port.vs"
);
//Front-end & Front-end interface.
wire data_req, data_ack;
wire [FE_ADDR_W -1 : FE_NBYTES_W] data_addr;
wire [FE_DATA_W-1 : 0] data_wdata, data_rdata;
wire [ FE_NBYTES-1:0] data_wstrb;
wire [FE_ADDR_W -1 : FE_NBYTES_W] data_addr_reg;
wire [ FE_DATA_W-1 : 0] data_wdata_reg;
wire [ FE_NBYTES-1:0] data_wstrb_reg;
wire data_req_reg;
wire ctrl_req, ctrl_ack;
wire [`IOB_CACHE_SWREG_ADDR_W-1:0] ctrl_addr;
wire [ USE_CTRL*(FE_DATA_W-1):0] ctrl_rdata;
wire ctrl_invalidate;
wire wtbuf_full, wtbuf_empty;
assign invalidate_o = ctrl_invalidate | invalidate_i;
assign wtb_empty_o = wtbuf_empty & wtb_empty_i;
iob_cache_front_end #(
.ADDR_W (FE_ADDR_W - FE_NBYTES_W),
.DATA_W (FE_DATA_W),
.USE_CTRL(USE_CTRL)
) front_end (
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(arst_i),
// front-end port
`include "iob_s_s_portmap.vs"
// cache-memory input signals
.data_req_o (data_req),
.data_addr_o(data_addr),
// cache-memory output
.data_rdata_i(data_rdata),
.data_ack_i (data_ack),
// stored input signals
.data_req_reg_o (data_req_reg),
.data_addr_reg_o (data_addr_reg),
.data_wdata_reg_o(data_wdata_reg),
.data_wstrb_reg_o(data_wstrb_reg),
// cache-controller
.ctrl_req_o (ctrl_req),
.ctrl_addr_o (ctrl_addr),
.ctrl_rdata_i(ctrl_rdata),
.ctrl_ack_i (ctrl_ack)
);
//Cache memory & This block implements the cache memory.
wire write_hit, write_miss, read_hit, read_miss;
// back-end write-channel
wire write_req, write_ack;
wire [ FE_ADDR_W-1 : FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] write_addr;
wire [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFFSET_W)-FE_DATA_W)-1 : 0] write_wdata;
wire [ FE_NBYTES-1:0] write_wstrb;
// back-end read-channel
wire replace_req, replace;
wire [FE_ADDR_W -1 : BE_NBYTES_W+LINE2BE_W] replace_addr;
wire read_req;
wire [ LINE2BE_W-1:0] read_addr;
wire [ BE_DATA_W-1:0] read_rdata;
iob_cache_memory #(
.FE_ADDR_W (FE_ADDR_W),
.FE_DATA_W (FE_DATA_W),
.BE_ADDR_W (BE_ADDR_W),
.BE_DATA_W (BE_DATA_W),
.NWAYS_W (NWAYS_W),
.NLINES_W (NLINES_W),
.WORD_OFFSET_W(WORD_OFFSET_W),
.WTBUF_DEPTH_W(WTBUF_DEPTH_W),
.REP_POLICY (REP_POLICY),
.WRITE_POL (WRITE_POL),
.USE_CTRL (USE_CTRL),
.USE_CTRL_CNT (USE_CTRL_CNT)
) cache_memory (
.clk_i(clk_i),
.cke_i(cke_i),
.reset_i(arst_i),
// front-end
.req_i (data_req),
.addr_i (data_addr[FE_ADDR_W-1 : BE_NBYTES_W+LINE2BE_W]),
.rdata_o (data_rdata),
.ack_o (data_ack),
.req_reg_i (data_req_reg),
.addr_reg_i (data_addr_reg),
.wdata_reg_i(data_wdata_reg),
.wstrb_reg_i(data_wstrb_reg),
// back-end
// write-through-buffer (write-channel)
.write_req_o (write_req),
.write_addr_o (write_addr),
.write_wdata_o(write_wdata),
.write_wstrb_o(write_wstrb),
.write_ack_i (write_ack),
// cache-line replacement (read-channel)
.replace_req_o (replace_req),
.replace_addr_o(replace_addr),
.replace_i (replace),
.read_req_i (read_req),
.read_addr_i (read_addr),
.read_rdata_i (read_rdata),
// control's signals
.wtbuf_empty_o(wtbuf_empty),
.wtbuf_full_o (wtbuf_full),
.write_hit_o (write_hit),
.write_miss_o (write_miss),
.read_hit_o (read_hit),
.read_miss_o (read_miss),
.invalidate_i (invalidate_o)
);
//Back-end interface & This block interfaces with the system level or next-level cache.
iob_cache_back_end_axi #(
.FE_ADDR_W (FE_ADDR_W),
.FE_DATA_W (FE_DATA_W),
.BE_ADDR_W (BE_ADDR_W),
.BE_DATA_W (BE_DATA_W),
.WORD_OFFSET_W(WORD_OFFSET_W),
.WRITE_POL (WRITE_POL),
.AXI_ADDR_W (AXI_ADDR_W),
.AXI_DATA_W (AXI_DATA_W),
.AXI_ID_W (AXI_ID_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ID (AXI_ID)
) back_end_axi (
// write-through-buffer (write-channel)
.write_valid_i(write_req),
.write_addr_i (write_addr),
.write_wdata_i(write_wdata),
.write_wstrb_i(write_wstrb),
.write_ready_o(write_ack),
// cache-line replacement (read-channel)
.replace_valid_i(replace_req),
.replace_addr_i (replace_addr),
.replace_o (replace),
.read_valid_o (read_req),
.read_addr_o (read_addr),
.read_rdata_o (read_rdata),
//back-end AXI4 interface
`include "axi_m_m_portmap.vs"
.clk_i(clk_i),
.rst_i(arst_i)
);
//Cache control & Cache control block.
generate
if (USE_CTRL)
iob_cache_control #(
.DATA_W (FE_DATA_W),
.USE_CTRL_CNT(USE_CTRL_CNT)
) cache_control (
.clk_i(clk_i),
.reset_i(arst_i),
// control's signals
.valid_i(ctrl_req),
.addr_i (ctrl_addr),
// write data
.wtbuf_full_i (wtbuf_full),
.wtbuf_empty_i(wtbuf_empty),
.write_hit_i (write_hit),
.write_miss_i (write_miss),
.read_hit_i (read_hit),
.read_miss_i (read_miss),
.rdata_o (ctrl_rdata),
.ready_o (ctrl_ack),
.invalidate_o(ctrl_invalidate)
);
else begin : g_no_cache_ctrl
assign ctrl_rdata = 1'bx;
assign ctrl_ack = 1'bx;
assign ctrl_invalidate = 1'b0;
end
endgenerate
endmodule |
module iob_cache_write_channel_axi #(
parameter ADDR_W = `IOB_CACHE_ADDR_W,
parameter DATA_W = `IOB_CACHE_DATA_W,
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter AXI_ID_W = `IOB_CACHE_AXI_ID_W,
parameter [AXI_ID_W-1:0] AXI_ID = `IOB_CACHE_AXI_ID,
parameter AXI_LEN_W = `IOB_CACHE_AXI_LEN_W,
parameter AXI_ADDR_W = BE_ADDR_W,
parameter AXI_DATA_W = BE_DATA_W,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
input valid_i,
input [ ADDR_W-1 : FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] addr_i,
input [DATA_W + WRITE_POL*(DATA_W*(2**WORD_OFFSET_W)-DATA_W)-1 : 0] wdata_i,
input [ FE_NBYTES-1:0] wstrb_i,
output reg ready_o,
`include "axi_m_write_port.vs"
input clk_i,
input reset_i
);
reg axi_awvalid_int;
reg axi_wvalid_int;
reg axi_bready_int;
assign axi_awvalid_o = axi_awvalid_int;
assign axi_wvalid_o = axi_wvalid_int;
assign axi_bready_o = axi_bready_int;
genvar i;
generate
if (WRITE_POL == `IOB_CACHE_WRITE_THROUGH) begin : g_write_through
// Constant AXI signals
assign axi_awid_o = AXI_ID;
assign axi_awlen_o = 8'd0;
assign axi_awsize_o = BE_NBYTES_W; // verify - Writes data of the size of BE_DATA_W
assign axi_awburst_o = 2'd0;
assign axi_awlock_o = 1'b0; // 00 - Normal Access
assign axi_awcache_o = 4'b0011;
assign axi_awprot_o = 3'd0;
assign axi_awqos_o = 4'd0;
assign axi_wlast_o = axi_wvalid_o;
// AXI Buffer Output signals
assign axi_awaddr_o = {BE_ADDR_W{1'b0}} + {addr_i[ADDR_W-1 : BE_NBYTES_W], {BE_NBYTES_W{1'b0}}};
if (BE_DATA_W == DATA_W) begin : g_same_data_w
assign axi_wstrb_o = wstrb_i;
assign axi_wdata_o = wdata_i;
end else begin : g_not_same_data_w
wire [BE_NBYTES_W - FE_NBYTES_W -1 :0] word_align = addr_i[FE_NBYTES_W +: (BE_NBYTES_W - FE_NBYTES_W)];
assign axi_wstrb_o = wstrb_i << (word_align * FE_NBYTES);
for (i = 0; i < BE_DATA_W / DATA_W; i = i + 1) begin : g_wdata_block
assign axi_wdata_o[(i+1)*DATA_W-1:i*DATA_W] = wdata_i;
end
end
localparam idle = 2'd0, address = 2'd1, write = 2'd2, verif = 2'd3;
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle: begin
if (valid_i) state <= address;
else state <= idle;
end
address: begin
if (axi_awready_i) state <= write;
else state <= address;
end
write: begin
if (axi_wready_i) state <= verif;
else state <= write;
end
default: begin // verif - needs to be after the last word has been written, so this can't be optim
if (axi_bvalid_i & (axi_bresp_i == 2'b00) & ~valid_i)
state <= idle; // no more words to write
else if (axi_bvalid_i & (axi_bresp_i == 2'b00) & valid_i)
state <= address; // buffer still isn't empty
else if (axi_bvalid_i & ~(axi_bresp_i == 2'b00)) // error
state <= address; // goes back to transfer the same data.
else state <= verif;
end
endcase
end
always @* begin
ready_o = 1'b0;
axi_awvalid_int = 1'b0;
axi_wvalid_int = 1'b0;
axi_bready_int = 1'b0;
case (state)
idle: ready_o = 1'b1;
address: axi_awvalid_int = 1'b1;
write: axi_wvalid_int = 1'b1;
default: begin // verif
axi_bready_int = 1'b1;
ready_o = axi_bvalid_i & ~(|axi_bresp_i);
end
endcase
end
end else begin : g_write_back // if (WRITE_POL == `IOB_CACHE_WRITE_BACK)
if (LINE2BE_W > 0) begin : g_line2be_w
// Constant AXI signals
assign axi_awid_o = AXI_ID;
assign axi_awlock_o = 1'b0;
assign axi_awcache_o = 4'b0011;
assign axi_awprot_o = 3'd0;
assign axi_awqos_o = 4'd0;
// Burst parameters
assign axi_awlen_o = 2**LINE2BE_W - 1; // will choose the burst lenght depending on the cache's and slave's data width
assign axi_awsize_o = BE_NBYTES_W; // each word will be the width of the memory for maximum bandwidth
assign axi_awburst_o = 2'b01; // incremental burst
// memory address
assign axi_awaddr_o = {BE_ADDR_W{1'b0}} + {addr_i, {(FE_NBYTES_W+WORD_OFFSET_W){1'b0}}}; // base address for the burst, with width extension
// memory write-data
reg [LINE2BE_W-1:0] word_counter;
assign axi_wdata_o = wdata_i >> (word_counter * BE_DATA_W);
assign axi_wstrb_o = {BE_NBYTES{1'b1}};
assign axi_wlast_o = &word_counter;
localparam idle = 2'd0, address = 2'd1, write = 2'd2, verif = 2'd3;
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) begin
state <= idle;
word_counter <= 0;
end else begin
case (state)
idle:
if (valid_i) state <= address;
else state <= idle;
address:
if (axi_awready_i) state <= write;
else state <= address;
write:
if (axi_wready_i & (&word_counter)) begin // last word written
state <= verif;
word_counter <= 0;
end else if (axi_wready_i & ~(&word_counter)) begin // word still available
state <= write;
word_counter <= word_counter + 1;
end else begin // waiting for handshake
state <= write;
word_counter <= word_counter;
end
verif:
if (axi_bvalid_i & (axi_bresp_i == 2'b00))
state <= idle; // write transfer completed
else if (axi_bvalid_i & ~(axi_bresp_i == 2'b00))
state <= address; // error, requires re-transfer
else state <= verif; // still waiting for response
default: ;
endcase
end
end
always @* begin
ready_o = 1'b0;
axi_awvalid_int = 1'b0;
axi_wvalid_int = 1'b0;
axi_bready_int = 1'b0;
case (state)
idle: ready_o = ~valid_i;
address: axi_awvalid_int = 1'b1;
write: axi_wvalid_int = 1'b1;
default: begin // verif
axi_bready_int = 1'b1;
ready_o = axi_bvalid_i & ~(|axi_bresp_i);
end
endcase
end
end else begin : g_no_line2be_w
// Constant AXI signals
assign axi_awid_o = AXI_ID;
assign axi_awlock_o = 1'b0;
assign axi_awcache_o = 4'b0011;
assign axi_awprot_o = 3'd0;
assign axi_awqos_o = 4'd0;
// Burst parameters - single
assign axi_awlen_o = 8'd0; // A single burst of Memory data width word
assign axi_awsize_o = BE_NBYTES_W; // each word will be the width of the memory for maximum bandwidth
assign axi_awburst_o = 2'b00;
// memory address
assign axi_awaddr_o = {BE_ADDR_W{1'b0}} + {addr_i, {BE_NBYTES_W{1'b0}}}; // base address for the burst, with width extension
// memory write-data
assign axi_wdata_o = wdata_i;
assign axi_wstrb_o = {BE_NBYTES{1'b1}}; // uses entire bandwidth
assign axi_wlast_o = axi_wvalid_o;
localparam idle = 2'd0, address = 2'd1, write = 2'd2, verif = 2'd3;
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle:
if (valid_i) state <= address;
else state <= idle;
address:
if (axi_awready_i) state <= write;
else state <= address;
write:
if (axi_wready_i) state <= verif;
else state <= write;
default: // verif
if (axi_bvalid_i & (axi_bresp_i == 2'b00))
state <= idle; // write transfer completed
else if (axi_bvalid_i & ~(axi_bresp_i == 2'b00))
state <= address; // error, requires re-transfer
else state <= verif; // still waiting for response
endcase
end
always @* begin
ready_o = 1'b0;
axi_awvalid_int = 1'b0;
axi_wvalid_int = 1'b0;
axi_bready_int = 1'b0;
case (state)
idle: ready_o = ~valid_i;
address: axi_awvalid_int = 1'b1;
write: axi_wvalid_int = 1'b1;
default: begin // verif
axi_bready_int = 1'b1;
ready_o = axi_bvalid_i & ~(|axi_bresp_i);
end
endcase
end
end
end
endgenerate
endmodule |
module iob_cache_onehot_to_bin #(
parameter BIN_W = 2
) (
input [2**BIN_W-1:1] onehot_i,
output reg [ BIN_W-1:0] bin_o
);
reg [BIN_W-1:0] bin_cnt;
integer i;
always @(onehot_i) begin : onehot_to_binary_encoder
bin_cnt = 0;
for (i = 1; i < 2 ** BIN_W; i = i + 1) if (onehot_i[i]) bin_cnt = bin_cnt | i[BIN_W-1:0];
bin_o = bin_cnt;
end
endmodule |
module iob_cache_replacement_policy #(
parameter N_WAYS = 8,
parameter NLINES_W = 0,
parameter NWAYS_W = $clog2(N_WAYS),
parameter REP_POLICY = `IOB_CACHE_PLRU_TREE
) (
input clk_i,
input cke_i,
input reset_i,
input write_en_i,
input [ N_WAYS-1:0] way_hit_i,
input [NLINES_W-1:0] line_addr_i,
output [ N_WAYS-1:0] way_select_o,
output [ NWAYS_W-1:0] way_select_bin_o
);
genvar i, j, k;
generate
if (REP_POLICY == `IOB_CACHE_LRU) begin : g_LRU
wire [N_WAYS*NWAYS_W-1:0] mru_out, mru_in;
wire [N_WAYS*NWAYS_W-1:0] mru; // Initial MRU values of the LRU algorithm, also initialized them in case it's the first access or was invalidated
wire [N_WAYS*NWAYS_W-1:0] mru_cnt; // updates the MRU line, the way used will be the highest value, while the others are decremented
wire [NWAYS_W-1:0] mru_index, way_hit_bin;
iob_cache_onehot_to_bin #(NWAYS_W) way_hit_binary (
.onehot_i(way_hit_i[N_WAYS-1:1]),
.bin_o (way_hit_bin)
);
assign mru_index[NWAYS_W-1:0] = mru_out >> (NWAYS_W * way_hit_bin);
for (i = 0; i < N_WAYS; i = i + 1) begin : encoder_decoder
// LRU - Encoder
assign mru [i*NWAYS_W +: NWAYS_W] = (|mru_out)? mru_out [i*NWAYS_W +: NWAYS_W] : i; // verifies if the mru line has been initialized (if any bit in mru_output is HIGH), otherwise applies the priority values
assign mru_cnt [i*NWAYS_W +: NWAYS_W] = (way_hit_i[i])? {NWAYS_W{1'b1}} : (mru[i*NWAYS_W +: NWAYS_W] > mru_index) ? mru[i*NWAYS_W +: NWAYS_W] - 1 : mru[i*NWAYS_W +: NWAYS_W]; // the MRU way gets updated to the the highest value; the remaining, if their value was bigger than the MRU index previous value (mru_index), they get decremented
// LRU - Decoder (checks every index in search for the lowest (0)
assign way_select_o [i] = ~(|mru[i*NWAYS_W+:NWAYS_W]); // selects the way that has the lowest priority (mru = 0)
end
assign mru_in = (|way_hit_i)? mru_cnt : mru_out; // If an hit occured, then it updates, to avoid updating during a (write) miss (mru_cnt would decrement every way besides the lowest)
// Most Recently Used (MRU) memory
iob_regfile_sp #(
.ADDR_W(NLINES_W),
.DATA_W(N_WAYS * NWAYS_W)
) mru_memory // simply uses the same format as valid memory
(
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(reset_i),
.rst_i(1'b0),
.we_i(write_en_i),
.addr_i(line_addr_i),
.d_i(mru_in),
.d_o(mru_out)
);
iob_cache_onehot_to_bin #(NWAYS_W) onehot_bin (
.onehot_i(way_select_o[N_WAYS-1:1]),
.bin_o (way_select_bin_o)
);
end else if (REP_POLICY == `IOB_CACHE_PLRU_MRU) begin : g_PLRU_MRU
wire [N_WAYS -1:0] mru_in, mru_out;
// pseudo LRU MRU based Encoder (More Recenty-Used bits):
assign mru_in = (&(mru_out | way_hit_i))? way_hit_i : mru_out | way_hit_i; // When the cache access results in a hi, it will update the MRU signal, if all ways were used, it resets and only updated the Most Recent
// pseudo LRU MRU based Decoder:
for (i = 1; i < N_WAYS; i = i + 1) begin : g_way_select_block
assign way_select_o[i] = ~mru_out[i] & (&mru_out[i-1:0]); // verifies priority (lower index)
end
assign way_select_o[0] = ~mru_out[0];
// Most Recently Used (MRU) memory
iob_regfile_sp #(
.ADDR_W(NLINES_W),
.DATA_W(N_WAYS)
) mru_memory // simply uses the same format as valid memory
(
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(reset_i),
.rst_i(1'b0),
.we_i(write_en_i),
.addr_i(line_addr_i),
.d_i(mru_in),
.d_o(mru_out)
);
iob_cache_onehot_to_bin #(NWAYS_W) onehot_bin (
.onehot_i(way_select_o[N_WAYS-1:1]),
.bin_o (way_select_bin_o)
);
end else begin : g_PLRU_TREE
// (REP_POLICY == PLRU_TREE)
/*
i: tree level, start from 1, i <= NWAYS_W
j: tree node id @ i level, start from 0, j < (1<<(i-1))
(((1<<(i-1))+j)*2)*(1<<(NWAYS_W-i)) ==> start node id of left tree @ the lowest level node pointed to
(((1<<(i-1))+j)*2+1)*(1<<(NWAYS_W-i)) ==> start node id of right tree @ the lowest level node pointed to
way_hit_i[(((1<<(i-1))+j)*2)*(1<<(NWAYS_W-i))-N_WAYS +: (N_WAYS>>i)] ==> way hit range of left tree
way_hit_i[(((1<<(i-1))+j)*2+1)*(1<<(NWAYS_W-i))-N_WAYS +: (N_WAYS>>i)] ==> way hit range of right tree
== tree traverse ==
<--0 1--> traverse direction
[1] node id @ level1
[2] [3] node id @ level2 ==> which to traverse? from node_id[1]
[4] [5] [6] [7] node id @ level3 ==> which to traverse? from node_id[2]
[08] [09] [10] [11] [12] [13] [14] [15] node id @ level4 ==> which to traverse? from node_id[3]
(00) (01) (02) (03) (04) (05) (06) (07) way idx
node value is 0 -> left tree traverse
node value is 1 -> right tree traverse
node id mapping to way idx: node_id[NWAYS_W]-N_WAYS
*/
wire [N_WAYS -1:1] tree_in, tree_out;
wire [NWAYS_W:0] node_id[NWAYS_W:1];
assign node_id[1] = tree_out[1] ? 3 : 2; // next node id @ level2 to traverse
for (i = 2; i <= NWAYS_W; i = i + 1) begin : g_traverse_tree_level
// next node id @ level3, level4, ..., to traverse
assign node_id[i] = tree_out[node_id[i-1]] ? ((node_id[i-1]<<1)+1) : (node_id[i-1]<<1);
end
for (i = 1; i <= NWAYS_W; i = i + 1) begin : tree_level
for (j = 0; j < (1 << (i - 1)); j = j + 1) begin : tree_level_node
assign tree_in[(1<<(i-1))+j] = ~(|way_hit_i) ? tree_out[(1<<(i-1))+j] :
(|way_hit_i[((((1<<(i-1))+j)*2)*(1<<(NWAYS_W-i)))-N_WAYS +: (N_WAYS>>i)]) ||
(tree_out[(1<<(i-1))+j] && (~(|way_hit_i[((((1<<(i-1))+j)*2+1)*(1<<(NWAYS_W-i)))-N_WAYS +: (N_WAYS>>i)])));
end
end
assign way_select_bin_o = node_id[NWAYS_W] - N_WAYS;
assign way_select_o = (1 << way_select_bin_o);
// Most Recently Used (MRU) memory
iob_regfile_sp #(
.ADDR_W(NLINES_W),
.DATA_W(N_WAYS - 1)
) mru_memory // simply uses the same format as valid memory
(
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(reset_i),
.rst_i(1'b0),
.we_i(write_en_i),
.addr_i(line_addr_i),
.d_i(tree_in),
.d_o(tree_out)
);
end
endgenerate
endmodule |
module iob_cache_back_end_axi #(
parameter FE_ADDR_W = `IOB_CACHE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter AXI_ID_W = `IOB_CACHE_AXI_ID_W,
parameter [AXI_ID_W-1:0] AXI_ID = `IOB_CACHE_AXI_ID,
parameter AXI_LEN_W = `IOB_CACHE_AXI_LEN_W,
parameter AXI_ADDR_W = BE_ADDR_W,
parameter AXI_DATA_W = BE_DATA_W,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
// write-through-buffer
input write_valid_i,
input [ FE_ADDR_W-1 : FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] write_addr_i,
input [FE_DATA_W+WRITE_POL*(FE_DATA_W*(2**WORD_OFFSET_W)-FE_DATA_W)-1:0] write_wdata_i,
input [ FE_NBYTES-1:0] write_wstrb_i,
output write_ready_o,
// cache-line replacement
input replace_valid_i,
input [FE_ADDR_W-1:BE_NBYTES_W + LINE2BE_W] replace_addr_i,
output replace_o,
output read_valid_o,
output [ LINE2BE_W -1:0] read_addr_o,
output [ AXI_DATA_W -1:0] read_rdata_o,
// Back-end interface (AXI4 master)
`include "axi_m_port.vs"
input [1-1:0] clk_i, //V2TEX_IO System clock input.
input [1-1:0] rst_i //V2TEX_IO System reset, asynchronous and active high.
);
iob_cache_read_channel_axi #(
.ADDR_W (FE_ADDR_W),
.DATA_W (FE_DATA_W),
.BE_ADDR_W (AXI_ADDR_W),
.BE_DATA_W (AXI_DATA_W),
.WORD_OFFSET_W(WORD_OFFSET_W),
.AXI_ADDR_W (AXI_ADDR_W),
.AXI_DATA_W (AXI_DATA_W),
.AXI_ID_W (AXI_ID_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ID (AXI_ID)
) read_fsm (
.replace_valid_i(replace_valid_i),
.replace_addr_i (replace_addr_i),
.replace_o (replace_o),
.read_valid_o (read_valid_o),
.read_addr_o (read_addr_o),
.read_rdata_o (read_rdata_o),
`include "axi_m_m_read_portmap.vs"
.clk_i (clk_i),
.reset_i (rst_i)
);
iob_cache_write_channel_axi #(
.ADDR_W (FE_ADDR_W),
.DATA_W (FE_DATA_W),
.BE_ADDR_W (AXI_ADDR_W),
.BE_DATA_W (AXI_DATA_W),
.WRITE_POL (WRITE_POL),
.WORD_OFFSET_W(WORD_OFFSET_W),
.AXI_ADDR_W (AXI_ADDR_W),
.AXI_DATA_W (AXI_DATA_W),
.AXI_ID_W (AXI_ID_W),
.AXI_LEN_W (AXI_LEN_W),
.AXI_ID (AXI_ID)
) write_fsm (
.valid_i(write_valid_i),
.addr_i (write_addr_i),
.wstrb_i(write_wstrb_i),
.wdata_i(write_wdata_i),
.ready_o(write_ready_o),
`include "axi_m_m_write_portmap.vs"
.clk_i(clk_i),
.reset_i(rst_i)
);
endmodule |
module iob_cache_iob #(
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter NWAYS_W = `IOB_CACHE_NWAYS_W,
parameter NLINES_W = `IOB_CACHE_NLINES_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WTBUF_DEPTH_W = `IOB_CACHE_WTBUF_DEPTH_W,
parameter REP_POLICY = `IOB_CACHE_REP_POLICY,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter USE_CTRL = `IOB_CACHE_USE_CTRL,
parameter USE_CTRL_CNT = `IOB_CACHE_USE_CTRL_CNT,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W),
parameter ADDR_W = USE_CTRL+FE_ADDR_W-FE_NBYTES_W,
parameter DATA_W = FE_DATA_W) (
// Front-end interface (IOb native slave)
`include "iob_s_port.vs"
// Back-end interface
output [ 1-1:0] be_valid_o,
output [ BE_ADDR_W-1:0] be_addr_o,
output [ BE_DATA_W-1:0] be_wdata_o,
output [ BE_NBYTES-1:0] be_wstrb_o,
input [ BE_DATA_W-1:0] be_rdata_i,
input be_rvalid_i,
input be_ready_i,
// Cache invalidate and write-trough buffer IO chain
input [1-1:0] invalidate_i,
output [1-1:0] invalidate_o,
input [1-1:0] wtb_empty_i,
output [1-1:0] wtb_empty_o,
//General Interface Signals
input [1-1:0] clk_i, //V2TEX_IO System clock input.
input [1-1:0] cke_i, //V2TEX_IO System clock enable.
input [1-1:0] arst_i //V2TEX_IO System reset, asynchronous and active high.
);
//BLOCK Front-end & This NIP interface is connected to a processor or any other processing element that needs a cache buffer to improve the performance of accessing a slower but larger memory.
wire data_req, data_ack;
wire [FE_ADDR_W -1:FE_NBYTES_W] data_addr;
wire [FE_DATA_W-1 : 0] data_wdata, data_rdata;
wire [ FE_NBYTES-1:0] data_wstrb;
wire [FE_ADDR_W -1:FE_NBYTES_W] data_addr_reg;
wire [ FE_DATA_W-1 : 0] data_wdata_reg;
wire [ FE_NBYTES-1:0] data_wstrb_reg;
wire data_req_reg;
wire ctrl_req, ctrl_ack;
wire [`IOB_CACHE_SWREG_ADDR_W-1:0] ctrl_addr;
wire [ USE_CTRL*(FE_DATA_W-1):0] ctrl_rdata;
wire ctrl_invalidate;
wire wtbuf_full, wtbuf_empty;
assign invalidate_o = ctrl_invalidate | invalidate_i;
assign wtb_empty_o = wtbuf_empty & wtb_empty_i;
iob_cache_front_end #(
.ADDR_W (ADDR_W),
.DATA_W (DATA_W),
.USE_CTRL(USE_CTRL)
) front_end (
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(arst_i),
// front-end port
`include "iob_s_s_portmap.vs"
// cache-memory input signals
.data_req_o (data_req),
.data_addr_o(data_addr),
// cache-memory output
.data_rdata_i(data_rdata),
.data_ack_i (data_ack),
// stored input signals
.data_req_reg_o (data_req_reg),
.data_addr_reg_o (data_addr_reg),
.data_wdata_reg_o(data_wdata_reg),
.data_wstrb_reg_o(data_wstrb_reg),
// cache-controller
.ctrl_req_o (ctrl_req),
.ctrl_addr_o (ctrl_addr),
.ctrl_rdata_i(ctrl_rdata),
.ctrl_ack_i (ctrl_ack)
);
//BLOCK Cache memory & This block contains the tag, data storage memories and the Write Through Buffer if the correspeonding write policy is selected; these memories are implemented either with RAM if large enough, or with registers if small enough.
wire write_hit, write_miss, read_hit, read_miss;
// back-end write-channel
wire write_req, write_ack;
wire [ FE_ADDR_W-1:FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] write_addr;
wire [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFFSET_W)-FE_DATA_W)-1 : 0] write_wdata;
wire [ FE_NBYTES-1:0] write_wstrb;
// back-end read-channel
wire replace_req, replace;
wire [FE_ADDR_W -1:BE_NBYTES_W+LINE2BE_W] replace_addr;
wire read_req;
wire [ LINE2BE_W-1:0] read_addr;
wire [ BE_DATA_W-1:0] read_rdata;
iob_cache_memory #(
.FE_ADDR_W (FE_ADDR_W),
.FE_DATA_W (FE_DATA_W),
.BE_DATA_W (BE_DATA_W),
.NWAYS_W (NWAYS_W),
.NLINES_W (NLINES_W),
.WORD_OFFSET_W(WORD_OFFSET_W),
.WTBUF_DEPTH_W(WTBUF_DEPTH_W),
.REP_POLICY (REP_POLICY),
.WRITE_POL (WRITE_POL),
.USE_CTRL (USE_CTRL),
.USE_CTRL_CNT (USE_CTRL_CNT)
) cache_memory (
.clk_i(clk_i),
.cke_i(cke_i),
.reset_i(arst_i),
// front-end
.req_i (data_req),
.addr_i (data_addr[FE_ADDR_W-1 : BE_NBYTES_W+LINE2BE_W]),
.rdata_o (data_rdata),
.ack_o (data_ack),
.req_reg_i (data_req_reg),
.addr_reg_i (data_addr_reg),
.wdata_reg_i(data_wdata_reg),
.wstrb_reg_i(data_wstrb_reg),
// back-end
// write-through-buffer (write-channel)
.write_req_o (write_req),
.write_addr_o (write_addr),
.write_wdata_o(write_wdata),
.write_wstrb_o(write_wstrb),
.write_ack_i (write_ack),
// cache-line replacement (read-channel)
.replace_req_o (replace_req),
.replace_addr_o(replace_addr),
.replace_i (replace),
.read_req_i (read_req),
.read_addr_i (read_addr),
.read_rdata_i (read_rdata),
// control's signals
.wtbuf_empty_o(wtbuf_empty),
.wtbuf_full_o (wtbuf_full),
.write_hit_o (write_hit),
.write_miss_o (write_miss),
.read_hit_o (read_hit),
.read_miss_o (read_miss),
.invalidate_i (invalidate_o)
);
//BLOCK Back-end interface & Memory-side interface: if the cache is at the last level before the target memory module, the back-end interface connects to the target memory (e.g. DDR) controller; if the cache is not at the last level, the back-end interface connects to the next-level cache. This interface can be of type NPI or AXI4 as per configuration. If it is connected to the next-level IOb-Cache, the NPI type must be selected; if it is connected to a third party cache or memory controlller featuring an AXI4 interface, then the AXI4 type must be selected.
iob_cache_back_end #(
.FE_ADDR_W (FE_ADDR_W),
.FE_DATA_W (FE_DATA_W),
.BE_ADDR_W (BE_ADDR_W),
.BE_DATA_W (BE_DATA_W),
.WORD_OFFSET_W(WORD_OFFSET_W),
.WRITE_POL (WRITE_POL)
) back_end (
.clk_i(clk_i),
.cke_i(cke_i),
.arst_i(arst_i),
// write-through-buffer (write-channel)
.write_valid_i(write_req),
.write_addr_i (write_addr),
.write_wdata_i(write_wdata),
.write_wstrb_i(write_wstrb),
.write_ready_o(write_ack),
// cache-line replacement (read-channel)
.replace_valid_i(replace_req),
.replace_addr_i (replace_addr),
.replace_o (replace),
.read_valid_o (read_req),
.read_addr_o (read_addr),
.read_rdata_o (read_rdata),
// back-end native interface
.be_valid_o(be_valid_o),
.be_addr_o (be_addr_o),
.be_wdata_o (be_wdata_o),
.be_wstrb_o (be_wstrb_o),
.be_rdata_i (be_rdata_i),
.be_rvalid_i(be_rvalid_i),
.be_ready_i (be_ready_i)
);
//BLOCK Cache control & Cache controller: this block is used for invalidating the cache, monitoring the status of the Write Thorough buffer, and accessing read/write hit/miss counters.
generate
if (USE_CTRL) begin : g_ctrl
iob_cache_control #(
.DATA_W (FE_DATA_W),
.USE_CTRL_CNT(USE_CTRL_CNT)
) cache_control (
.clk_i(clk_i),
.reset_i(arst_i),
// control's signals
.valid_i(ctrl_req),
.addr_i (ctrl_addr),
// write data
.wtbuf_full_i (wtbuf_full),
.wtbuf_empty_i(wtbuf_empty),
.write_hit_i (write_hit),
.write_miss_i (write_miss),
.read_hit_i (read_hit),
.read_miss_i (read_miss),
.rdata_o (ctrl_rdata),
.ready_o (ctrl_ack),
.invalidate_o(ctrl_invalidate)
);
end
else begin : g_no_ctrl
assign ctrl_rdata = 1'bx;
assign ctrl_ack = 1'bx;
assign ctrl_invalidate = 1'b0;
end
endgenerate
endmodule |
module iob_cache_control #(
parameter DATA_W = 32,
parameter USE_CTRL_CNT = 1
) (
input clk_i,
input reset_i,
input valid_i,
input [`IOB_CACHE_SWREG_ADDR_W-1:0] addr_i,
input wtbuf_full_i,
input wtbuf_empty_i,
input write_hit_i,
input write_miss_i,
input read_hit_i,
input read_miss_i,
output reg [ DATA_W-1:0] rdata_o,
output reg ready_o,
output reg invalidate_o
);
generate
if (USE_CTRL_CNT) begin : g_ctrl_cnt
reg [DATA_W-1:0] read_hit_cnt, read_miss_cnt, write_hit_cnt, write_miss_cnt;
wire [DATA_W-1:0] hit_cnt, miss_cnt;
reg reset_counters;
assign hit_cnt = read_hit_cnt + write_hit_cnt;
assign miss_cnt = read_miss_cnt + write_miss_cnt;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) begin
read_hit_cnt <= {DATA_W{1'b0}};
read_miss_cnt <= {DATA_W{1'b0}};
write_hit_cnt <= {DATA_W{1'b0}};
write_miss_cnt <= {DATA_W{1'b0}};
end else begin
if (reset_counters) begin
read_hit_cnt <= {DATA_W{1'b0}};
read_miss_cnt <= {DATA_W{1'b0}};
write_hit_cnt <= {DATA_W{1'b0}};
write_miss_cnt <= {DATA_W{1'b0}};
end else if (read_hit_i) begin
read_hit_cnt <= read_hit_cnt + 1'b1;
end else if (write_hit_i) begin
write_hit_cnt <= write_hit_cnt + 1'b1;
end else if (read_miss_i) begin
read_miss_cnt <= read_miss_cnt + 1'b1;
read_hit_cnt <= read_hit_cnt - 1'b1;
end else if (write_miss_i) begin
write_miss_cnt <= write_miss_cnt + 1'b1;
end else begin
read_hit_cnt <= read_hit_cnt;
read_miss_cnt <= read_miss_cnt;
write_hit_cnt <= write_hit_cnt;
write_miss_cnt <= write_miss_cnt;
end
end
end
always @(posedge clk_i) begin
rdata_o <= {DATA_W{1'b0}};
invalidate_o <= 1'b0;
reset_counters <= 1'b0;
ready_o <= valid_i; // Sends acknowlege the next clock cycle after request (handshake)
if (valid_i)
if (addr_i == `IOB_CACHE_RW_HIT_ADDR>>2) rdata_o <= hit_cnt;
else if (addr_i == `IOB_CACHE_RW_MISS_ADDR>>2) rdata_o <= miss_cnt;
else if (addr_i == `IOB_CACHE_READ_HIT_ADDR>>2) rdata_o <= read_hit_cnt;
else if (addr_i == `IOB_CACHE_READ_MISS_ADDR>>2) rdata_o <= read_miss_cnt;
else if (addr_i == `IOB_CACHE_WRITE_HIT_ADDR>>2) rdata_o <= write_hit_cnt;
else if (addr_i == `IOB_CACHE_WRITE_MISS_ADDR>>2) rdata_o <= write_miss_cnt;
else if (addr_i == `IOB_CACHE_RST_CNTRS_ADDR>>2) reset_counters <= 1'b1;
end
end else begin : g_no_ctrl_cnt
always @(posedge clk_i) begin
rdata_o <= {DATA_W{1'b0}};
invalidate_o <= 1'b0;
ready_o <= valid_i; // Sends acknowlege the next clock cycle after request (handshake)
if (valid_i)
if (addr_i == `IOB_CACHE_INVALIDATE_ADDR>>2) invalidate_o <= 1'b1;
else if (addr_i == `IOB_CACHE_WTB_EMPTY_ADDR>>2) rdata_o <= wtbuf_empty_i;
else if (addr_i == `IOB_CACHE_WTB_FULL_ADDR>>2) rdata_o <= wtbuf_full_i;
else if (addr_i == `IOB_CACHE_VERSION_ADDR>>2) rdata_o <= `IOB_CACHE_VERSION;
end
end
endgenerate
endmodule |
module iob_cache_front_end #(
parameter ADDR_W = 32,
parameter DATA_W = 32,
// Derived parameters DO NOT CHANGE
parameter USE_CTRL = 0,
parameter USE_CTRL_CNT = 0
) (
// General ports
input clk_i,
input cke_i,
input arst_i,
// IOb-bus front-end
`include "iob_s_port.vs"
// internal input signals
output data_req_o,
output [ADDR_W-USE_CTRL-1:0] data_addr_o,
input [DATA_W-1:0] data_rdata_i,
input data_ack_i,
// output registered input signals
output reg data_req_reg_o,
output reg [ADDR_W-USE_CTRL-1:0] data_addr_reg_o,
output reg [DATA_W-1:0] data_wdata_reg_o,
output reg [DATA_W/8-1:0] data_wstrb_reg_o,
// cache-control
output ctrl_req_o,
output [`IOB_CACHE_SWREG_ADDR_W-1:0] ctrl_addr_o,
input [ USE_CTRL*(DATA_W-1):0] ctrl_rdata_i,
input ctrl_ack_i
);
wire ack;
wire valid_int;
wire we_r;
// select cache memory ir controller
generate
if (USE_CTRL) begin : g_ctrl
// Front-end output signals
assign ack = ctrl_ack_i | data_ack_i;
assign iob_rdata_o = (ctrl_ack_i) ? ctrl_rdata_i : data_rdata_i;
assign valid_int = ~iob_addr_i[ADDR_W-1] & iob_valid_i;
assign ctrl_req_o = iob_addr_i[ADDR_W-1] & iob_valid_i;
assign ctrl_addr_o = iob_addr_i[`IOB_CACHE_SWREG_ADDR_W-1:0];
end else begin : g_no_ctrl
// Front-end output signals
assign ack = data_ack_i;
assign iob_rdata_o = data_rdata_i;
assign valid_int = iob_valid_i;
assign ctrl_req_o = 1'bx;
assign ctrl_addr_o = `IOB_CACHE_SWREG_ADDR_W'dx;
end
endgenerate
// data output ports
assign data_addr_o = iob_addr_i[ADDR_W-1 : 0];
assign data_req_o = valid_int | data_req_reg_o;
assign iob_rvalid_o = we_r ? 1'b0 : ack;
assign iob_ready_o = data_req_reg_o ~^ ack;
// Register every input
iob_reg_re #(
.DATA_W (1),
.RST_VAL(0)
) iob_reg_valid (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (valid_int|ack),
.data_i(valid_int),
.data_o(data_req_reg_o)
);
iob_reg_re #(
.DATA_W (ADDR_W-USE_CTRL),
.RST_VAL(0)
) iob_reg_addr (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (valid_int),
.data_i(iob_addr_i[ADDR_W-USE_CTRL-1:0]),
.data_o(data_addr_reg_o)
);
iob_reg_re #(
.DATA_W (DATA_W),
.RST_VAL(0)
) iob_reg_wdata (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (valid_int),
.data_i(iob_wdata_i),
.data_o(data_wdata_reg_o)
);
iob_reg_re #(
.DATA_W (DATA_W/8),
.RST_VAL(0)
) iob_reg_wstrb (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (valid_int),
.data_i(iob_wstrb_i),
.data_o(data_wstrb_reg_o)
);
iob_reg_re #(
.DATA_W (1),
.RST_VAL(0)
) iob_reg_we (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (valid_int),
.data_i(|iob_wstrb_i),
.data_o(we_r)
);
endmodule |
module iob_cache_write_channel #(
parameter ADDR_W = `IOB_CACHE_ADDR_W,
parameter DATA_W = `IOB_CACHE_DATA_W,
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
input clk_i,
input reset_i,
input valid_i,
input [ADDR_W-1 : FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] addr_i,
input [FE_NBYTES-1:0] wstrb_i,
input [DATA_W + WRITE_POL*(DATA_W*(2**WORD_OFFSET_W)-DATA_W)-1:0] wdata_i, // try [DATA_W*((2**WORD_OFFSET_W)**WRITE_POL)-1:0] (f(x)=a*b^x)
output reg ready_o,
// Native Memory interface
output [BE_ADDR_W -1:0] be_addr_o,
output reg be_valid_o,
input be_ack_i,
output [ BE_DATA_W-1:0] be_wdata_o,
output reg [ BE_NBYTES-1:0] be_wstrb_o
);
genvar i;
generate
if (WRITE_POL == `IOB_CACHE_WRITE_THROUGH) begin : g_write_through
assign be_addr_o = {BE_ADDR_W{1'b0}} + {addr_i[ADDR_W-1 : BE_NBYTES_W], {BE_NBYTES_W{1'b0}}};
localparam idle = 1'd0, write = 1'd1;
reg [0:0] state;
if (BE_DATA_W == DATA_W) begin : g_same_data_w
assign be_wdata_o = wdata_i;
always @* begin
be_wstrb_o = 0;
case (state)
write: be_wstrb_o = wstrb_i;
default: ;
endcase
end
end else begin : g_not_same_data_w
wire [BE_NBYTES_W-FE_NBYTES_W -1 :0] word_align = addr_i[FE_NBYTES_W +: (BE_NBYTES_W - FE_NBYTES_W)];
for (i = 0; i < BE_DATA_W / DATA_W; i = i + 1) begin : g_wdata_block
assign be_wdata_o[(i+1)*DATA_W-1:i*DATA_W] = wdata_i;
end
always @* begin
be_wstrb_o = 0;
case (state)
write: be_wstrb_o = wstrb_i << word_align * FE_NBYTES;
default: ;
endcase
end
end
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle: begin
if (valid_i) state <= write;
else state <= idle;
end
default: begin // write
if (be_ack_i & ~valid_i) state <= idle;
else if (be_ack_i & valid_i) // still has data to write
state <= write;
else state <= write;
end
endcase
end
always @* begin
ready_o = 1'b0;
be_valid_o = 1'b0;
case (state)
idle: ready_o = 1'b1;
default: begin // write
be_valid_o = ~be_ack_i;
ready_o = be_ack_i;
end
endcase
end
end else begin : g_write_back
// if (WRITE_POL == WRITE_BACK)
if (LINE2BE_W > 0) begin : g_line2be_w
reg [LINE2BE_W-1:0] word_counter, word_counter_reg;
always @(posedge clk_i) word_counter_reg <= word_counter;
// memory address
assign be_addr_o = {BE_ADDR_W{1'b0}} + {addr_i[ADDR_W-1: BE_NBYTES_W + LINE2BE_W], word_counter, {BE_NBYTES_W{1'b0}}};
// memory write-data
assign be_wdata_o = wdata_i >> (BE_DATA_W * word_counter);
localparam idle = 1'd0, write = 1'd1;
reg [0:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle: begin
if (valid_i) state <= write;
else state <= idle;
end
default: begin // write
if (be_ack_i & (&word_counter_reg)) state <= idle;
else state <= write;
end
endcase
end
always @* begin
ready_o = 1'b0;
be_valid_o = 1'b0;
be_wstrb_o = 0;
word_counter = 0;
case (state)
idle: begin
ready_o = ~valid_i;
if (valid_i) be_wstrb_o = {BE_NBYTES{1'b1}};
else be_wstrb_o = 0;
end
default: begin // write
ready_o = be_ack_i & (&word_counter); // last word transfered
be_valid_o = ~(be_ack_i & (&word_counter));
be_wstrb_o = {BE_NBYTES{1'b1}};
word_counter = word_counter_reg + be_ack_i;
end
endcase
end
end else begin : g_no_line2be_w
// memory address
assign be_addr_o = {BE_ADDR_W{1'b0}} + {addr_i[ADDR_W-1:BE_NBYTES_W], {BE_NBYTES_W{1'b0}}};
// memory write-data
assign be_wdata_o = wdata_i;
localparam idle = 1'd0, write = 1'd1;
reg [0:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle: begin
if (valid_i) state <= write;
else state <= idle;
end
default: begin // write
if (be_ack_i) state <= idle;
else state <= write;
end
endcase
end
always @* begin
ready_o = 1'b0;
be_valid_o = 1'b0;
be_wstrb_o = 0;
case (state)
idle: begin
ready_o = ~valid_i;
if (valid_i) be_wstrb_o = {BE_NBYTES{1'b1}};
else be_wstrb_o = 0;
end
default: begin // write
ready_o = be_ack_i;
be_valid_o = ~be_ack_i;
be_wstrb_o = {BE_NBYTES{1'b1}};
end
endcase
end
end
end
endgenerate
endmodule |
module iob_cache_memory #(
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter NWAYS_W = `IOB_CACHE_NWAYS_W,
parameter NLINES_W = `IOB_CACHE_NLINES_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WTBUF_DEPTH_W = `IOB_CACHE_WTBUF_DEPTH_W,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
parameter REP_POLICY = `IOB_CACHE_PLRU_TREE,
parameter USE_CTRL = `IOB_CACHE_USE_CTRL,
parameter USE_CTRL_CNT = `IOB_CACHE_USE_CTRL_CNT,
//derived parameters
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
input clk_i,
input cke_i,
input reset_i,
// front-end
input req_i,
input [FE_ADDR_W-1:BE_NBYTES_W+LINE2BE_W] addr_i,
output [ FE_DATA_W-1:0] rdata_o,
output ack_o,
// stored input value
input req_reg_i,
input [FE_ADDR_W-1:FE_NBYTES_W] addr_reg_i,
input [ FE_DATA_W-1:0] wdata_reg_i,
input [ FE_NBYTES-1:0] wstrb_reg_i,
// back-end write-channel
output write_req_o,
output [ FE_ADDR_W-1:FE_NBYTES_W + WRITE_POL*WORD_OFFSET_W] write_addr_o,
output [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFFSET_W)-FE_DATA_W)-1 : 0] write_wdata_o,
// write-through[DATA_W]; write-back[DATA_W*2**WORD_OFFSET_W]
output [FE_NBYTES-1:0] write_wstrb_o,
input write_ack_i,
// back-end read-channel
output replace_req_o,
output [FE_ADDR_W-1:BE_NBYTES_W+LINE2BE_W] replace_addr_o,
input replace_i,
input read_req_i,
input [ LINE2BE_W-1:0] read_addr_i,
input [ BE_DATA_W-1:0] read_rdata_i,
// cache-control
input invalidate_i,
output wtbuf_full_o,
output wtbuf_empty_o,
output write_hit_o,
output write_miss_o,
output read_hit_o,
output read_miss_o
);
localparam TAG_W = FE_ADDR_W - (FE_NBYTES_W + WORD_OFFSET_W + NLINES_W);
localparam NWAYS = 2 ** NWAYS_W;
wire hit;
// cache-memory internal signals
wire [NWAYS-1:0] way_hit, way_select;
wire [TAG_W-1:0] tag = addr_reg_i[FE_ADDR_W-1 -: TAG_W]; // so the tag doesnt update during ack on a read-access, losing the current hit status (can take the 1 clock-cycle delay)
wire [NLINES_W-1:0] index = addr_i[FE_ADDR_W-TAG_W-1 -: NLINES_W]; // cant wait, doesnt update during a write-access
wire [NLINES_W-1:0] index_reg = addr_reg_i[FE_ADDR_W-TAG_W-1 -:NLINES_W]; // cant wait, doesnt update during a write-access
wire [WORD_OFFSET_W-1:0] offset = addr_reg_i[FE_NBYTES_W +: WORD_OFFSET_W]; // so the offset doesnt update during ack on a read-access (can take the 1 clock-cycle delay)
wire [NWAYS*(2**WORD_OFFSET_W)*FE_DATA_W-1:0] line_rdata;
wire [NWAYS*TAG_W-1:0] line_tag;
reg [NWAYS*(2**NLINES_W)-1:0] v_reg;
reg [NWAYS-1:0] v;
reg [(2**WORD_OFFSET_W)*FE_NBYTES-1:0] line_wstrb;
wire write_access = |wstrb_reg_i & req_reg_i;
wire read_access = ~|wstrb_reg_i & req_reg_i;
//signal mantains the access 1 addition clock-cycle after ack is asserted
// back-end write channel
wire buffer_empty, buffer_full;
wire [FE_NBYTES+(FE_ADDR_W-FE_NBYTES_W)+(FE_DATA_W)-1:0] buffer_dout;
// for write-back write-allocate only
reg [ NWAYS-1:0] dirty;
reg [ NWAYS*(2**NLINES_W)-1:0] dirty_reg;
generate
if (WRITE_POL == `IOB_CACHE_WRITE_THROUGH) begin : g_write_through
localparam FIFO_DATA_W = FE_ADDR_W - FE_NBYTES_W + FE_DATA_W + FE_NBYTES;
localparam FIFO_ADDR_W = WTBUF_DEPTH_W;
wire mem_clk;
wire mem_arst;
wire mem_cke;
wire mem_w_en;
wire [FIFO_ADDR_W-1:0] mem_w_addr;
wire [FIFO_DATA_W-1:0] mem_w_data;
wire mem_r_en;
wire [FIFO_ADDR_W-1:0] mem_r_addr;
wire [FIFO_DATA_W-1:0] mem_r_data;
// FIFO memory
iob_ram_2p #(
.DATA_W(FIFO_DATA_W),
.ADDR_W(FIFO_ADDR_W)
) iob_ram_2p0 (
.clk_i(clk_i),
.w_en_i (mem_w_en),
.w_addr_i(mem_w_addr),
.w_data_i(mem_w_data),
.r_en_i (mem_r_en),
.r_addr_i(mem_r_addr),
.r_data_o(mem_r_data)
);
iob_fifo_sync #(
.R_DATA_W(FIFO_DATA_W),
.W_DATA_W(FIFO_DATA_W),
.ADDR_W (FIFO_ADDR_W)
) write_throught_buffer (
.clk_i (clk_i),
.rst_i (reset_i),
.arst_i(reset_i),
.cke_i (1'b1),
.ext_mem_clk_o (mem_clk),
.ext_mem_w_en_o (mem_w_en),
.ext_mem_w_addr_o(mem_w_addr),
.ext_mem_w_data_o(mem_w_data),
.ext_mem_r_en_o (mem_r_en),
.ext_mem_r_addr_o(mem_r_addr),
.ext_mem_r_data_i(mem_r_data),
.level_o(),
.r_data_o (buffer_dout),
.r_empty_o(buffer_empty),
.r_en_i (write_ack_i),
.w_data_i({addr_reg_i, wdata_reg_i, wstrb_reg_i}),
.w_full_o(buffer_full),
.w_en_i (write_access & ack_o)
);
// buffer status
assign wtbuf_full_o = buffer_full;
assign wtbuf_empty_o = buffer_empty & write_ack_i & ~write_req_o;
// back-end write channel
assign write_req_o = ~buffer_empty;
assign write_addr_o = buffer_dout[FE_NBYTES+FE_DATA_W+:FE_ADDR_W-FE_NBYTES_W];
assign write_wdata_o = buffer_dout[FE_NBYTES+:FE_DATA_W];
assign write_wstrb_o = buffer_dout[0+:FE_NBYTES];
// back-end read channel
assign replace_req_o = (~hit & read_access & ~replace_i) & (buffer_empty & write_ack_i);
assign replace_addr_o = addr_i[FE_ADDR_W-1:BE_NBYTES_W+LINE2BE_W];
end else begin : g_write_back
// if (WRITE_POL == WRITE_BACK)
// back-end write channel
assign write_wstrb_o = {FE_NBYTES{1'bx}};
// write_req_o, write_addr_o and write_wdata_o assigns are generated bellow (dependencies)
// back-end read channel
assign replace_req_o = (~|way_hit) & (write_ack_i) & req_reg_i & ~replace_i;
assign replace_addr_o = addr_i[FE_ADDR_W-1:BE_NBYTES_W+LINE2BE_W];
end
endgenerate
//////////////////////////////////////////////////////
// Read-After-Write (RAW) Hazard (pipeline) control
//////////////////////////////////////////////////////
wire raw;
reg write_hit_prev;
reg [WORD_OFFSET_W-1:0] offset_prev;
reg [ NWAYS-1:0] way_hit_prev;
generate
if (WRITE_POL == `IOB_CACHE_WRITE_THROUGH) begin : g_write_through_on_RAW
always @(posedge clk_i) begin
write_hit_prev <= write_access & (|way_hit);
// previous write position
offset_prev <= offset;
way_hit_prev <= way_hit;
end
assign raw = write_hit_prev & (way_hit_prev == way_hit) & (offset_prev == offset);
end else begin : g_write_back_on_RAW
// if (WRITE_POL == WRITE_BACK)
always @(posedge clk_i) begin
// all writes will have the data in cache in the end
write_hit_prev <= write_access;
// previous write position
offset_prev <= offset;
way_hit_prev <= way_hit;
end
assign raw = write_hit_prev & (way_hit_prev == way_hit) & (offset_prev == offset) & read_access;
// without read_access it is an infinite replacement loop
end
endgenerate
///////////////////////////////////////////////////////////////
// Hit signal: data available and in the memory's output
///////////////////////////////////////////////////////////////
assign hit = |way_hit & ~replace_i & (~raw);
/////////////////////////////////
// front-end ACK signal
/////////////////////////////////
generate
if (WRITE_POL == `IOB_CACHE_WRITE_THROUGH)
assign ack_o = (hit & read_access) | (~buffer_full & write_access);
else // if (WRITE_POL == WRITE_BACK)
assign ack_o = hit & req_reg_i;
endgenerate
// cache-control hit-miss counters enables
generate
if (USE_CTRL & USE_CTRL_CNT) begin : g_ctrl_cnt
// cache-control hit-miss counters enables
assign write_hit_o = ack_o & (hit & write_access);
assign write_miss_o = ack_o & (~hit & write_access);
assign read_hit_o = ack_o & (hit & read_access);
assign read_miss_o = replace_req_o; //will also subtract read_hit_o
end else begin : g_no_ctrl_cnt
assign write_hit_o = 1'bx;
assign write_miss_o = 1'bx;
assign read_hit_o = 1'bx;
assign read_miss_o = 1'bx;
end
endgenerate
/////////////////////////////////////////
// Memories implementation configurations
/////////////////////////////////////////
genvar i, j, k;
generate
// Data-Memory
for (k = 0; k < NWAYS; k = k + 1) begin : g_n_ways_block
for (j = 0; j < 2 ** LINE2BE_W; j = j + 1) begin : g_line2mem_block
for (i = 0; i < BE_DATA_W / FE_DATA_W; i = i + 1) begin : g_BE_block
iob_gen_sp_ram #(
.DATA_W(FE_DATA_W),
.ADDR_W(NLINES_W)
) cache_memory (
.clk_i(clk_i),
.en_i(req_i),
.we_i ({FE_NBYTES{way_hit[k]}} & line_wstrb[(j*(BE_DATA_W/FE_DATA_W)+i)*FE_NBYTES +: FE_NBYTES]),
.addr_i((write_access & way_hit[k] & ((j*(BE_DATA_W/FE_DATA_W)+i) == offset))? index_reg[NLINES_W-1:0] : index[NLINES_W-1:0]),
.data_i((replace_i) ? read_rdata_i[i*FE_DATA_W+:FE_DATA_W] : wdata_reg_i),
.data_o(line_rdata[(k*(2**WORD_OFFSET_W)+j*(BE_DATA_W/FE_DATA_W)+i)*FE_DATA_W+:FE_DATA_W])
);
end
end
end
// Cache Line Write Strobe
if (LINE2BE_W > 0) begin : g_line2be_w
always @* begin
if (replace_i) begin
// line-replacement: read_addr_i indexes the words in cache-line
line_wstrb = {BE_NBYTES{read_req_i}} << (read_addr_i * BE_NBYTES);
end else begin
line_wstrb = (wstrb_reg_i & {FE_NBYTES{write_access}}) << (offset * FE_NBYTES);
end
end
end else begin : g_no_line2be_w
always @* begin
if (replace_i) begin
// line-replacement: mem's word replaces entire line
line_wstrb = {BE_NBYTES{read_req_i}};
end else begin
line_wstrb = (wstrb_reg_i & {FE_NBYTES{write_access}}) << (offset * FE_NBYTES);
end
end
end
// Valid-Tag memories & replacement-policy
if (NWAYS > 1) begin : g_nways
// reason for the 2 generates for single vs multiple ways
wire [NWAYS_W-1:0] way_hit_bin, way_select_bin;
// valid-memory
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) v_reg <= 0;
else if (invalidate_i) v_reg <= 0;
else if (replace_req_o)
v_reg <= v_reg | (1 << (way_select_bin * (2 ** NLINES_W) + index_reg));
else v_reg <= v_reg;
end
for (k = 0; k < NWAYS; k = k + 1) begin : g_tag_mem_block
// valid-memory output stage register - 1 c.c. read-latency (cleaner simulation during rep.)
always @(posedge clk_i)
if (invalidate_i) v[k] <= 0;
else v[k] <= v_reg[(2**NLINES_W)*k+index];
// tag-memory
iob_ram_sp #(
.DATA_W(TAG_W),
.ADDR_W(NLINES_W)
) tag_memory (
.clk_i (clk_i),
.en_i (req_i),
.we_i (way_select[k] & replace_req_o),
.addr_i(index[NLINES_W-1:0]),
.d_i (tag),
.d_o (line_tag[TAG_W*k+:TAG_W])
);
// Way hit signal - hit or replacement
assign way_hit[k] = (tag == line_tag[TAG_W*k+:TAG_W]) & v[k];
end
// Read Data Multiplexer
wire [NWAYS*(2**WORD_OFFSET_W)*FE_DATA_W-1:0] line_rdata_tmp = line_rdata >> (FE_DATA_W*(offset + (2**WORD_OFFSET_W)*way_hit_bin));
assign rdata_o[FE_DATA_W-1:0] = line_rdata_tmp[FE_DATA_W-1:0];
// replacement-policy module
iob_cache_replacement_policy #(
.N_WAYS (NWAYS),
.NLINES_W (NLINES_W),
.REP_POLICY(REP_POLICY)
) replacement_policy_algorithm (
.clk_i (clk_i),
.cke_i (cke_i),
.reset_i (reset_i | invalidate_i),
.write_en_i (ack_o),
.way_hit_i (way_hit),
.line_addr_i (index_reg[NLINES_W-1:0]),
.way_select_o (way_select),
.way_select_bin_o(way_select_bin)
);
// onehot-to-binary for way-hit
iob_cache_onehot_to_bin #(
.BIN_W(NWAYS_W)
) way_hit_encoder (
.onehot_i(way_hit[NWAYS-1:1]),
.bin_o (way_hit_bin)
);
// dirty-memory
if (WRITE_POL == `IOB_CACHE_WRITE_BACK) begin : g_write_back
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) dirty_reg <= 0;
else if (write_req_o)
dirty_reg <= dirty_reg & ~(1<<(way_select_bin*(2**NLINES_W) + index_reg)); // updates position with 0
else if (write_access & hit)
dirty_reg <= dirty_reg | (1<<(way_hit_bin*(2**NLINES_W) + index_reg)); // updates position with 1
else dirty_reg <= dirty_reg;
end
for (k = 0; k < NWAYS; k = k + 1) begin : g_dirty_block
// valid-memory output stage register - 1 c.c. read-latency (cleaner simulation during rep.)
always @(posedge clk_i) dirty[k] <= dirty_reg[(2**NLINES_W)*k+index];
end
// flush line
assign write_req_o = req_reg_i & ~(|way_hit) & dirty[way_select_bin]; //flush if there is not a hit, and the way selected is dirty
wire [TAG_W-1:0] tag_flush = line_tag >> (way_select_bin * TAG_W); //auxiliary wire
assign write_addr_o = {
tag_flush, index_reg
}; //the position of the current block in cache (not of the access)
assign write_wdata_o = line_rdata >> (way_select_bin * FE_DATA_W * (2 ** WORD_OFFSET_W));
end
end else begin : g_one_way // (NWAYS = 1)
// valid-memory
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) v_reg <= 0;
else if (invalidate_i) v_reg <= 0;
else if (replace_req_o) v_reg <= v_reg | (1 << index);
else v_reg <= v_reg;
end
// valid-memory output stage register - 1 c.c. read-latency (cleaner simulation during rep.)
always @(posedge clk_i) begin
if (invalidate_i) v <= 0;
else v <= v_reg[index];
end
// tag-memory
iob_ram_sp #(
.DATA_W(TAG_W),
.ADDR_W(NLINES_W)
) tag_memory (
.clk_i (clk_i),
.en_i (req_i),
.we_i (replace_req_o),
.addr_i(index),
.d_i (tag),
.d_o (line_tag)
);
// Cache hit signal that indicates which way has had the hit (also during replacement)
assign way_hit = (tag == line_tag) & v;
// Read Data Multiplexer
assign rdata_o[FE_DATA_W-1:0] = line_rdata >> FE_DATA_W * offset;
// dirty-memory
if (WRITE_POL == `IOB_CACHE_WRITE_BACK) begin : g_write_back
// dirty-memory
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) begin
dirty_reg <= 0;
end else if (write_req_o) begin
// updates postion with 0
dirty_reg <= dirty_reg & ~(1 << (index_reg));
end else if (write_access & hit) begin
// updates position with 1 (needs to be index_reg otherwise updates the new index if the previous access was a write)
dirty_reg <= dirty_reg | (1 << (index_reg));
end else begin
dirty_reg <= dirty_reg;
end
end
always @(posedge clk_i) dirty <= dirty_reg[index];
// flush line
// flush if there is not a hit, and is dirty
assign write_req_o = req_reg_i & ~(way_hit) & dirty;
assign write_addr_o = {
line_tag, index
}; // the position of the current block in cache (not of the access)
assign write_wdata_o = line_rdata;
end
end
endgenerate
endmodule |
module iob_cache_read_channel_axi #(
parameter ADDR_W = `IOB_CACHE_ADDR_W,
parameter DATA_W = `IOB_CACHE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter AXI_ID_W = `IOB_CACHE_AXI_ID_W,
parameter [AXI_ID_W-1:0] AXI_ID = `IOB_CACHE_AXI_ID,
parameter AXI_LEN_W = `IOB_CACHE_AXI_LEN_W,
parameter AXI_ADDR_W = BE_ADDR_W,
parameter AXI_DATA_W = BE_DATA_W,
//derived parameters
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / DATA_W)
) (
input replace_valid_i,
input [ADDR_W-1:BE_NBYTES_W+LINE2BE_W] replace_addr_i,
output reg replace_o,
output read_valid_o,
output reg [ LINE2BE_W-1:0] read_addr_o,
output [ BE_DATA_W-1:0] read_rdata_o,
`include "axi_m_read_port.vs"
input clk_i,
input reset_i
);
reg axi_arvalid_int;
reg axi_rready_int;
assign axi_arvalid_o = axi_arvalid_int;
assign axi_rready_o = axi_rready_int;
generate
if (LINE2BE_W > 0) begin : g_line2be_w
// Constant AXI signals
assign axi_arid_o = AXI_ID;
assign axi_arlock_o = 1'b0;
assign axi_arcache_o = 4'b0011;
assign axi_arprot_o = 3'd0;
assign axi_arqos_o = 4'd0;
// Burst parameters
assign axi_arlen_o = 2**LINE2BE_W - 1'b1; // will choose the burst lenght depending on the cache's and slave's data width
assign axi_arsize_o = BE_NBYTES_W; // each word will be the width of the memory for maximum bandwidth
assign axi_arburst_o = 2'b01; // incremental burst
assign axi_araddr_o = {BE_ADDR_W{1'b0}} + {replace_addr_i, {(LINE2BE_W+BE_NBYTES_W){1'b0}}}; // base address for the burst, with width extension
// Read Line values
assign read_rdata_o = axi_rdata_i;
assign read_valid_o = axi_rvalid_i;
localparam idle = 2'd0, init_process = 2'd1, load_process = 2'd2, end_process = 2'd3;
reg [1:0] state;
reg slave_error; // axi slave_error during reply (axi_rresp[1] == 1) - burst can't be interrupted, so a flag needs to be active
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) begin
state <= idle;
read_addr_o <= 0;
slave_error <= 0;
end else begin
slave_error <= slave_error;
case (state)
idle: begin
slave_error <= 0;
read_addr_o <= 0;
if (replace_valid_i) state <= init_process;
else state <= idle;
end
init_process: begin
slave_error <= 0;
read_addr_o <= 0;
if (axi_arready_i) state <= load_process;
else state <= init_process;
end
load_process: begin
if (axi_rvalid_i)
if (axi_rlast_i) begin
state <= end_process;
// to avoid writting last data in first line word
read_addr_o <= read_addr_o;
// slave_error - received at the same time as the valid - needs to wait until the end to start all over - going directly to init_process would cause a stall to this burst
if (axi_rresp_i != 2'b00) slave_error <= 1;
end else begin
read_addr_o <= read_addr_o + 1'b1;
state <= load_process;
// slave_error - received at the same time as the valid - needs to wait until the end to start all over - going directly to init_process would cause a stall to this burst
if (axi_rresp_i != 2'b00) slave_error <= 1;
end
else begin
read_addr_o <= read_addr_o;
state <= load_process;
end
end
// end_process - delay for the read_latency of the memories (if the rdata is the last word)
default: begin
if (slave_error) state <= init_process;
else state <= idle;
end
endcase
end
end
always @* begin
axi_arvalid_int = 1'b0;
axi_rready_int = 1'b0;
replace_o = 1'b1;
case (state)
idle: replace_o = 1'b0;
init_process: axi_arvalid_int = 1'b1;
default: axi_rready_int = 1'b1; // load_process
endcase
end
end else begin : g_no_line2be_w
// Constant AXI signals
assign axi_arid_o = AXI_ID;
assign axi_arlock_o = 1'b0;
assign axi_arcache_o = 4'b0011;
assign axi_arprot_o = 3'd0;
assign axi_arqos_o = 4'd0;
// Burst parameters - single
assign axi_arlen_o = 8'd0; // A single burst of Memory data width word
assign axi_arsize_o = BE_NBYTES_W; // each word will be the width of the memory for maximum bandwidth
assign axi_arburst_o = 2'b00;
assign axi_araddr_o = {BE_ADDR_W{1'b0}} + {replace_addr_i, {BE_NBYTES_W{1'b0}}}; // base address for the burst, with width extension
// Read Line values
assign read_valid_o = axi_rvalid_i;
assign read_rdata_o = axi_rdata_i;
localparam idle = 2'd0, init_process = 2'd1, load_process = 2'd2, end_process = 2'd3;
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else
case (state)
idle: begin
if (replace_valid_i) state <= init_process;
else state <= idle;
end
init_process: begin
if (axi_arready_i) state <= load_process;
else state <= init_process;
end
load_process: begin
if (axi_rvalid_i)
if (axi_rresp_i != 2'b00) // slave_error - received at the same time as valid
state <= init_process;
else state <= end_process;
else state <= load_process;
end
end_process:
state <= idle; // delay for the read_latency of the memories (if the rdata is the last word)
default: ;
endcase
end
always @* begin
axi_arvalid_int = 1'b0;
axi_rready_int = 1'b0;
replace_o = 1'b1;
case (state)
idle: begin
replace_o = 1'b0;
end
init_process: begin
axi_arvalid_int = 1'b1;
end
load_process: begin
axi_rready_int = 1'b1;
end
default: ;
endcase
end
end
endgenerate
endmodule |
module iob_cache_read_channel #(
parameter FE_ADDR_W = `IOB_CACHE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_DATA_W,
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
//derived parameters
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter LINE2BE_W = WORD_OFFSET_W - $clog2(BE_DATA_W / FE_DATA_W)
) (
input clk_i,
input reset_i,
input replace_valid_i,
input [FE_ADDR_W-1:BE_NBYTES_W+LINE2BE_W] replace_addr_i,
output reg replace_o,
output reg read_valid_o,
output reg [ LINE2BE_W-1:0] read_addr_o,
output [ BE_DATA_W-1:0] read_rdata_o,
// Native memory interface
output [BE_ADDR_W-1:0] be_addr_o,
output reg be_valid_o,
input be_ack_i,
input [BE_DATA_W-1:0] be_rdata_i
);
generate
if (LINE2BE_W > 0) begin : g_line2be_w
reg [LINE2BE_W-1:0] word_counter;
assign be_addr_o = {BE_ADDR_W{1'b0}} + {replace_addr_i[FE_ADDR_W-1 : BE_NBYTES_W+LINE2BE_W], word_counter, {BE_NBYTES_W{1'b0}}};
assign read_rdata_o = be_rdata_i;
localparam
idle = 2'd0,
handshake = 2'd1, // the process was divided in 2 handshake steps to cause a delay in the
end_handshake = 2'd2; // (always 1 or a delayed valid signal), otherwise it will fail
always @(posedge clk_i) read_addr_o <= word_counter;
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) begin
state <= idle;
end else begin
case (state)
idle: begin
if (replace_valid_i) // main_process flag
state <= handshake;
else state <= idle;
end
handshake: begin
if (be_ack_i)
if (read_addr_o == {LINE2BE_W{1'b1}}) begin
state <= end_handshake;
end else begin
state <= handshake;
end
else begin
state <= handshake;
end
end
end_handshake: begin // read-latency delay (last line word)
state <= idle;
end
default: ;
endcase
end
end
always @* begin
be_valid_o = 1'b0;
replace_o = 1'b1;
word_counter = 0;
read_valid_o = 1'b0;
case (state)
idle: begin
replace_o = 1'b0;
end
handshake: begin
be_valid_o = ~be_ack_i | ~(&read_addr_o);
word_counter = read_addr_o + be_ack_i;
read_valid_o = be_ack_i;
end
default: ;
endcase
end
end else begin : g_no_line2be_w
assign be_addr_o = {BE_ADDR_W{1'b0}} + {replace_addr_i, {BE_NBYTES_W{1'b0}}};
assign read_rdata_o = be_rdata_i;
localparam
idle = 2'd0,
handshake = 2'd1, // the process was divided in 2 handshake steps to cause a delay in the
end_handshake = 2'd2; // (always 1 or a delayed valid signal), otherwise it will fail
reg [1:0] state;
always @(posedge clk_i, posedge reset_i) begin
if (reset_i) state <= idle;
else begin
case (state)
idle: begin
if (replace_valid_i) state <= handshake;
else state <= idle;
end
handshake: begin
if (be_ack_i) state <= end_handshake;
else state <= handshake;
end
end_handshake: begin // read-latency delay (last line word)
state <= idle;
end
default: ;
endcase
end
end
always @* begin
be_valid_o = 1'b0;
replace_o = 1'b1;
read_valid_o = 1'b0;
case (state)
idle: begin
replace_o = 1'b0;
end
handshake: begin
be_valid_o = ~be_ack_i;
read_valid_o = be_ack_i;
end
default: ;
endcase
end
end
endgenerate
endmodule |
module iob_cache_sim_wrapper #(
parameter ADDR_W = `IOB_CACHE_ADDR_W,
parameter DATA_W = `IOB_CACHE_DATA_W,
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W,
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W,
parameter FE_NBYTES = FE_DATA_W / 8,
parameter FE_NBYTES_W = $clog2(FE_NBYTES),
parameter BE_ADDR_W = `IOB_CACHE_BE_ADDR_W,
parameter BE_DATA_W = `IOB_CACHE_BE_DATA_W,
parameter BE_NBYTES = BE_DATA_W / 8,
parameter BE_NBYTES_W = $clog2(BE_NBYTES),
parameter NWAYS_W = `IOB_CACHE_NWAYS_W,
parameter NLINES_W = `IOB_CACHE_NLINES_W,
parameter WORD_OFFSET_W = `IOB_CACHE_WORD_OFFSET_W,
parameter WTBUF_DEPTH_W = `IOB_CACHE_WTBUF_DEPTH_W,
parameter REP_POLICY = `IOB_CACHE_REP_POLICY,
parameter WRITE_POL = `IOB_CACHE_WRITE_THROUGH,
`ifdef IOB_CACHE_AXI
parameter AXI_ID_W = `IOB_CACHE_AXI_ID_W,
parameter [AXI_ID_W-1:0] AXI_ID = `IOB_CACHE_AXI_ID,
parameter AXI_LEN_W = `IOB_CACHE_AXI_LEN_W,
parameter AXI_ADDR_W = BE_ADDR_W,
parameter AXI_DATA_W = BE_DATA_W,
`endif
parameter USE_CTRL = `IOB_CACHE_USE_CTRL,
parameter USE_CTRL_CNT = `IOB_CACHE_USE_CTRL_CNT
) (
// Front-end interface (IOb native slave)
input [ 1-1:0] iob_valid_i,
input [USE_CTRL+FE_ADDR_W-FE_NBYTES_W-1:0] iob_addr_i,
input [ DATA_W-1:0] iob_wdata_i,
input [ FE_NBYTES-1:0] iob_wstrb_i,
output [ DATA_W-1:0] iob_rdata_o,
output [ 1-1:0] iob_rvalid_o,
output [ 1-1:0] iob_ready_o,
// Cache invalidate and write-trough buffer IO chain
input [1-1:0] invalidate_i,
output [1-1:0] invalidate_o,
input [1-1:0] wtb_empty_i,
output [1-1:0] wtb_empty_o,
//General Interface Signals
input [1-1:0] clk_i,
input [1-1:0] arst_i
);
wire cke_i;
assign cke_i = 1'b1;
`ifdef IOB_CACHE_AXI
`include "axi_wire.vs"
iob_cache_axi cache (
//front-end
`include "iob_s_s_portmap.vs"
//invalidate / wtb empty
.invalidate_i (1'b0),
.invalidate_o(invalidate_o),
.wtb_empty_i (1'b1),
.wtb_empty_o (wtb_empty_o),
`include "axi_m_portmap.vs"
`include "clk_en_rst_s_s_portmap.vs"
);
`else
wire be_valid;
wire [ BE_ADDR_W-1:0] be_addr;
wire [ BE_DATA_W-1:0] be_wdata;
wire [BE_DATA_W/8-1:0] be_wstrb;
wire [ BE_DATA_W-1:0] be_rdata;
wire be_rvalid;
wire be_ready;
iob_cache_iob cache (
//front-end
`include "iob_s_s_portmap.vs"
//invalidate / wtb empty
.invalidate_i (1'b0),
.invalidate_o(invalidate_o),
.wtb_empty_i (1'b1),
.wtb_empty_o (wtb_empty_o),
.be_valid_o(be_valid),
.be_addr_o (be_addr),
.be_wdata_o (be_wdata),
.be_wstrb_o (be_wstrb),
.be_rdata_i (be_rdata),
.be_rvalid_i(be_rvalid),
.be_ready_i (be_ready),
.clk_i (clk_i),
.cke_i (cke_i),
.arst_i (arst_i)
);
`endif
`ifdef IOB_CACHE_AXI
axi_ram #(
.ID_WIDTH (AXI_ID_W),
.LEN_WIDTH (AXI_LEN_W),
.DATA_WIDTH(BE_DATA_W),
.ADDR_WIDTH(BE_ADDR_W)
) axi_ram (
`include "axi_s_portmap.vs"
.clk_i(clk_i),
.rst_i(arst_i)
);
`else
iob_ram_sp_be #(
.DATA_W(BE_DATA_W),
.ADDR_W(BE_ADDR_W)
) native_ram (
.clk_i (clk_i),
.en_i (be_valid),
.we_i (be_wstrb),
.addr_i(be_addr),
.d_o (be_rdata),
.d_i (be_wdata)
);
assign be_ready = 1'b1;
iob_reg_re #(
.DATA_W (1),
.RST_VAL(0)
) iob_reg_rvalid (
.clk_i (clk_i),
.arst_i(arst_i),
.cke_i (cke_i),
.rst_i (1'b0),
.en_i (1'b1),
.data_i(be_valid & (~(|be_wstrb))),
.data_o(be_rvalid)
);
`endif
endmodule |
module iob_cache_tb;
//clock
parameter clk_per = 10;
reg clk = 1;
always #clk_per clk = ~clk;
parameter FE_ADDR_W = `IOB_CACHE_FE_ADDR_W;
parameter FE_DATA_W = `IOB_CACHE_FE_DATA_W;
parameter FE_NBYTES = FE_DATA_W / 8;
parameter FE_NBYTES_W = $clog2(FE_NBYTES);
parameter USE_CTRL = `IOB_CACHE_USE_CTRL;
parameter USE_CTRL_CNT = `IOB_CACHE_USE_CTRL_CNT;
parameter ADDR_W = USE_CTRL+FE_ADDR_W-FE_NBYTES_W;
parameter DATA_W = `IOB_CACHE_DATA_W;
reg rst = 1;
//frontend signals
`include "iob_m_tb_wire.vs"
reg ctrl = 0;
//iterator
integer i, fd, failed=0;
reg [DATA_W-1:0] rdata;
//test process
initial begin
`ifdef VCD
$dumpfile("uut.vcd");
$dumpvars();
`endif
repeat (5) @(posedge clk);
rst = 0;
#10;
$display("Writing data to frontend");
for (i = 0; i < 5*4; i = i + 4) begin
iob_write(i, (3*i), `IOB_CACHE_DATA_W);
end
#80 @(posedge clk);
$display("Reading data from frontend");
for (i = 0; i < 5*4; i = i + 4) begin
iob_read(i, rdata, `IOB_CACHE_DATA_W);
//Write "Test passed!" to a file named "test.log"
if (rdata !== (3*i)) begin
$display("ERROR at address %d: got 0x%0h, expected 0x%0h", i, rdata, 3*i);
failed = failed+1;
end
end
#100;
fd = $fopen("test.log", "w");
if (failed == 0) begin
$display("Test passed!");
$fwrite(fd, "Test passed!");
end else begin
$display("Test failed!");
$fwrite(fd, "Test failed!");
end
$fclose(fd);
$finish();
end
//Unit Under Test (simulation wrapper)
iob_cache_sim_wrapper uut (
//frontend
`include "iob_s_s_portmap.vs"
//invalidate / wtb empty
.invalidate_i (1'b0),
.invalidate_o(),
.wtb_empty_i (1'b1),
.wtb_empty_o (),
.clk_i(clk),
.arst_i(rst)
);
`include "iob_tasks.vs"
endmodule |
module top(
`ifdef VGA
// VGA
output out_video_clock,
output reg [`COLOR_DEPTH-1:0] out_video_r,
output reg [`COLOR_DEPTH-1:0] out_video_g,
output reg [`COLOR_DEPTH-1:0] out_video_b,
output out_video_hs,
output out_video_vs,
`endif
// basic
output [7:0] out_leds,
input clock
);
reg [2:0] ready = 3'b111;
always @(posedge clock) begin
ready <= ready >> 1;
end
wire run_main;
assign run_main = 1'b1;
M_main __main(
.clock(clock),
.reset(ready[0]),
.out_leds(out_leds),
`ifdef VGA
.out_video_clock(out_video_clock),
.out_video_r(out_video_r),
.out_video_g(out_video_g),
.out_video_b(out_video_b),
.out_video_hs(out_video_hs),
.out_video_vs(out_video_vs),
`endif
.in_run(run_main)
);
endmodule |
module M_main__mem_mem(
input [11-1:0] in_mem_addr,
output reg [32-1:0] out_mem_rdata,
input [(32)/8-1:0] in_mem_wenable,
input [32-1:0] in_mem_wdata,
input clock
);
reg [32-1:0] buffer[1536-1:0];
always @(posedge clock) begin
out_mem_rdata <= buffer[in_mem_addr];
end
integer i;
always @(posedge clock) begin
for (i = 0; i < (32)/8; i = i + 1) begin
if (in_mem_wenable[i]) begin
buffer[in_mem_addr][i*8+:8] <= in_mem_wdata[i*8+:8];
end
end
end
initial begin
buffer[0] = 32'h00002137;
buffer[1] = 32'h80010113;
buffer[2] = 32'h00000097;
buffer[3] = 32'h018080E7;
buffer[4] = 32'h00000317;
buffer[5] = 32'h00830067;
buffer[6] = 32'h00000000;
buffer[7] = 32'h00008067;
buffer[8] = 32'hFF010113;
buffer[9] = 32'h00012623;
buffer[10] = 32'h000027B7;
buffer[11] = 32'h00F00713;
buffer[12] = 32'h00E7A223;
buffer[13] = 32'h00200793;
buffer[14] = 32'h000026B7;
buffer[15] = 32'h00800713;
buffer[16] = 32'h0080006F;
buffer[17] = 32'h00100793;
buffer[18] = 32'h00F6A223;
buffer[19] = 32'h00179793;
buffer[20] = 32'hFEF74AE3;
buffer[21] = 32'hFF5FF06F;
buffer[22] = 32'h00002040;
buffer[23] = 32'h00002020;
buffer[24] = 32'h00002010;
buffer[25] = 32'h00002008;
buffer[26] = 32'h00002004;
end
endmodule |
module M_rv32i_cpu__cpu_mem_xregsA(
input [1-1:0] in_xregsA_wenable,
input signed [32-1:0] in_xregsA_wdata,
input [5-1:0] in_xregsA_addr,
output reg signed [32-1:0] out_xregsA_rdata,
input clock
);
reg signed [32-1:0] buffer[32-1:0];
always @(posedge clock) begin
if (in_xregsA_wenable) begin
buffer[in_xregsA_addr] <= in_xregsA_wdata;
end
out_xregsA_rdata <= buffer[in_xregsA_addr];
end
initial begin
buffer[0] = 0;
buffer[1] = 0;
buffer[2] = 0;
buffer[3] = 0;
buffer[4] = 0;
buffer[5] = 0;
buffer[6] = 0;
buffer[7] = 0;
buffer[8] = 0;
buffer[9] = 0;
buffer[10] = 0;
buffer[11] = 0;
buffer[12] = 0;
buffer[13] = 0;
buffer[14] = 0;
buffer[15] = 0;
buffer[16] = 0;
buffer[17] = 0;
buffer[18] = 0;
buffer[19] = 0;
buffer[20] = 0;
buffer[21] = 0;
buffer[22] = 0;
buffer[23] = 0;
buffer[24] = 0;
buffer[25] = 0;
buffer[26] = 0;
buffer[27] = 0;
buffer[28] = 0;
buffer[29] = 0;
buffer[30] = 0;
buffer[31] = 0;
end
endmodule |
module M_rv32i_cpu__cpu_mem_xregsB(
input [1-1:0] in_xregsB_wenable,
input signed [32-1:0] in_xregsB_wdata,
input [5-1:0] in_xregsB_addr,
output reg signed [32-1:0] out_xregsB_rdata,
input clock
);
reg signed [32-1:0] buffer[32-1:0];
always @(posedge clock) begin
if (in_xregsB_wenable) begin
buffer[in_xregsB_addr] <= in_xregsB_wdata;
end
out_xregsB_rdata <= buffer[in_xregsB_addr];
end
initial begin
buffer[0] = 0;
buffer[1] = 0;
buffer[2] = 0;
buffer[3] = 0;
buffer[4] = 0;
buffer[5] = 0;
buffer[6] = 0;
buffer[7] = 0;
buffer[8] = 0;
buffer[9] = 0;
buffer[10] = 0;
buffer[11] = 0;
buffer[12] = 0;
buffer[13] = 0;
buffer[14] = 0;
buffer[15] = 0;
buffer[16] = 0;
buffer[17] = 0;
buffer[18] = 0;
buffer[19] = 0;
buffer[20] = 0;
buffer[21] = 0;
buffer[22] = 0;
buffer[23] = 0;
buffer[24] = 0;
buffer[25] = 0;
buffer[26] = 0;
buffer[27] = 0;
buffer[28] = 0;
buffer[29] = 0;
buffer[30] = 0;
buffer[31] = 0;
end
endmodule |
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