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module JTAGPPC440 (
TCK,
TDIPPC,
TMS,
TDOPPC
);
output TCK;
output TDIPPC;
output TMS;
input TDOPPC;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module IBUF_LVDCI_25 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module SRLC16 (Q, Q15, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
initial
begin
assign data = INIT;
while (CLK === 1'b1 || CLK===1'bX)
#10;
deassign data;
end
always @(posedge CLK) begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule |
module AND5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
and A1 (O, I0, I1, I2, I3, I4);
endmodule |
module IBUFG_LVDCI_DV2_25 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
wire i4_inv;
not N4 (i4_inv, I4);
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);
endmodule |
module CAPTURE_SPARTAN3 (CAP, CLK);
input CAP, CLK;
parameter ONESHOT = "FALSE";
endmodule |
module IBUFG_SSTL3_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND4B3 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, I3);
endmodule |
module IBUFG_LVDCI_15 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module CLKDLL (
CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED,
CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080; // non-simulatable
localparam integer MAXPERCLKIN = 40000; // simulation parameter
localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // simulation parameter
localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // simulation parameter
parameter STARTUP_WAIT = "FALSE"; // non-simulatable
input CLKFB, CLKIN, RST;
output CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED;
reg CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV;
wire clkfb_in, clkin_in, rst_in;
wire clk0_out;
reg clk2x_out, clkdv_out, locked_out;
reg [1:0] clkfb_type;
reg [8:0] divide_type;
reg clk1x_type;
reg lock_period, lock_delay, lock_clkin, lock_clkfb;
reg [1:0] lock_out;
reg lock_fb;
reg fb_delay_found;
reg clock_stopped;
reg clkin_ps;
reg clkin_fb;
time clkin_edge;
time clkin_ps_edge;
time delay_edge;
time clkin_period [2:0];
time period;
time period_ps;
time period_orig;
time clkout_delay;
time fb_delay;
time period_dv_high, period_dv_low;
time cycle_jitter, period_jitter;
reg clkin_window, clkfb_window;
reg clkin_5050;
reg [2:0] rst_reg;
reg [23:0] i, n, d, p;
reg notifier;
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the CLKDLL, the simulator resolution must be set to 1ps or smaller.");
$finish;
end
end
initial begin
case (CLKDV_DIVIDE)
1.5 : divide_type = 'd3;
2.0 : divide_type = 'd4;
2.5 : divide_type = 'd5;
3.0 : divide_type = 'd6;
4.0 : divide_type = 'd8;
5.0 : divide_type = 'd10;
8.0 : divide_type = 'd16;
16.0 : divide_type = 'd32;
default : begin
$display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on CLKDLL instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0.", CLKDV_DIVIDE);
$finish;
end
endcase
clkfb_type = 2;
period_jitter = SIM_CLKIN_PERIOD_JITTER;
cycle_jitter = SIM_CLKIN_CYCLE_JITTER;
case (DUTY_CYCLE_CORRECTION)
"false" : clk1x_type <= 0;
"FALSE" : clk1x_type <= 0;
"true" : clk1x_type <= 1;
"TRUE" : clk1x_type <= 1;
default : begin
$display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on CLKDLL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
$finish;
end
endcase
case (STARTUP_WAIT)
"false" : ;
"FALSE" : ;
"true" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute STARTUP_WAIT on CLKDLL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
$finish;
end
endcase
end
//
// input wire delays
//
buf b_clkin (clkin_in, CLKIN);
buf b_clkfb (clkfb_in, CLKFB);
buf b_rst (rst_in, RST);
buf #100 b_locked (LOCKED, locked_out);
clkdll_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
always @(clkin_in or rst_in)
if (rst_in == 1'b0)
clkin_ps <= clkin_in;
else if (rst_in == 1'b1) begin
clkin_ps <= 1'b0;
@(negedge rst_reg[2]);
end
always @(clkin_ps or lock_fb)
clkin_fb <= #(period_ps) clkin_ps & lock_fb;
always @(posedge clkin_ps) begin
clkin_ps_edge <= $time;
if (($time - clkin_ps_edge) <= (1.5 * period_ps))
period_ps <= $time - clkin_ps_edge;
else if ((period_ps == 0) && (clkin_ps_edge != 0))
period_ps <= $time - clkin_ps_edge;
end
always @(posedge clkin_ps)
lock_fb <= lock_period;
always @(period or fb_delay)
clkout_delay <= period - fb_delay;
//
// generate master reset signal
//
always @(posedge clkin_in) begin
rst_reg[0] <= rst_in;
rst_reg[1] <= rst_reg[0] & rst_in;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in;
end
time rst_tmp1, rst_tmp2;
initial
begin
rst_tmp1 = 0;
rst_tmp2 = 0;
end
always @(posedge rst_in or negedge rst_in)
begin
if (rst_in ==1)
rst_tmp1 <= $time;
else if (rst_in==0 ) begin
rst_tmp2 = $time - rst_tmp1;
if (rst_tmp2 < 2000 && rst_tmp2 != 0)
$display("Input Error : RST on instance %m must be asserted at least for 2 ns.");
end
end
initial begin
clk2x_out = 0;
clkdv_out = 0;
clkin_5050 = 0;
clkfb_window = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_ps_edge = 0;
clkin_window = 0;
clkout_delay = 0;
clock_stopped = 1;
fb_delay = 0;
fb_delay_found = 0;
lock_clkfb = 0;
lock_clkin = 0;
lock_delay = 0;
lock_fb = 0;
lock_out = 2'b00;
lock_period = 0;
locked_out = 0;
period = 0;
period_ps = 0;
period_orig = 0;
rst_reg = 3'b000;
end
always @(rst_in) begin
clkin_5050 <= 0;
clkfb_window <= 0;
clkin_period[0] <= 0;
clkin_period[1] <= 0;
clkin_period[2] <= 0;
clkin_ps_edge <= 0;
clkin_window <= 0;
clkout_delay <= 0;
clock_stopped <= 1;
fb_delay <= 0;
fb_delay_found <= 0;
lock_clkfb <= 0;
lock_clkin <= 0;
lock_delay <= 0;
lock_fb <= 0;
lock_out <= 2'b00;
lock_period <= 0;
locked_out <= 0;
period_ps <= 0;
end
//
// determine clock period
//
always @(posedge clkin_ps) begin
clkin_edge <= $time;
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
if (clkin_edge != 0)
clkin_period[0] <= $time - clkin_edge;
end
always @(negedge clkin_ps) begin
if (lock_period == 1'b0) begin
if ((clkin_period[0] != 0) &&
(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
lock_period <= 1;
period_orig <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
period <= clkin_period[0];
end
end
else if (lock_period == 1'b1) begin
if (100000000 < (clkin_period[0] / 1000)) begin
$display("Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
clkin_period[0] = clkin_period[1];
clock_stopped = 1'b1;
end
else if ((clkin_period[0] < period_orig - period_jitter) ||
(period_orig + period_jitter < clkin_period[0])) begin
$display("Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
$display("Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else begin
period <= clkin_period[0];
clock_stopped = 1'b0;
end
end
end
//
// determine clock delay
//
always @(posedge lock_period) begin
if (lock_period && clkfb_type != 0) begin
if (clkfb_type == 1) begin
@(posedge CLK0 or rst_in)
delay_edge = $time;
end
else if (clkfb_type == 2) begin
@(posedge CLK2X or rst_in)
delay_edge = $time;
end
@(posedge clkfb_in or rst_in)
fb_delay = ($time - delay_edge) % period_orig;
end
fb_delay_found = 1;
end
//
// determine feedback lock
//
always @(posedge clkfb_in) begin
#0 clkfb_window <= 1;
#cycle_jitter clkfb_window <= 0;
end
always @(posedge clkin_fb) begin
#0 clkin_window <= 1;
#cycle_jitter clkin_window <= 0;
end
always @(posedge clkin_fb) begin
#1
if (clkfb_window && fb_delay_found)
lock_clkin <= 1;
else
lock_clkin <= 0;
end
always @(posedge clkfb_in) begin
#1
if (clkin_window && fb_delay_found)
lock_clkfb <= 1;
else
lock_clkfb <= 0;
end
always @(negedge clkin_fb)
lock_delay <= lock_clkin || lock_clkfb;
//
// generate lock signal
//
always @(posedge clkin_ps) begin
lock_out[0] <= lock_period & lock_delay & lock_fb;
lock_out[1] <= lock_out[0];
locked_out <= lock_out[1];
end
//
// generate the clk1x_out
//
always @(posedge clkin_ps) begin
clkin_5050 <= 1;
#(period / 2)
clkin_5050 <= 0;
end
assign clk0_out = (clk1x_type) ? clkin_5050 : clkin_ps;
//
// generate the clk2x_out
//
always @(posedge clkin_ps) begin
clk2x_out <= 1;
#(period / 4)
clk2x_out <= 0;
if (lock_out[0]) begin
#(period / 4)
clk2x_out <= 1;
#(period / 4)
clk2x_out <= 0;
end
else begin
#(period / 2);
end
end
//
// generate the clkdv_out
//
always @(period) begin
// period_dv_high = (period / 2) * (divide_type / 2);
// period_dv_low = (period / 2) * (divide_type / 2 + divide_type % 2);
period_dv_high = (period * divide_type) / 4;
period_dv_low = (period * divide_type) / 4;
end
always @(posedge clkin_ps) begin
if (lock_out[0]) begin
clkdv_out = 1'b1;
#(period_dv_high);
clkdv_out = 1'b0;
#(period_dv_low);
clkdv_out = 1'b1;
#(period_dv_high);
clkdv_out = 1'b0;
#(period_dv_low - period / 2);
end
end
//
// generate all output signal
//
always @(clk0_out)
CLK0 <= #(clkout_delay) clk0_out;
always @(clk0_out)
CLK90 <= #(clkout_delay + period / 4) clk0_out;
always @(clk0_out)
CLK180 <= #(clkout_delay + period / 2) clk0_out;
always @(clk0_out)
CLK270 <= #(clkout_delay + (3 * period) / 4) clk0_out;
always @(clk2x_out)
CLK2X <= #(clkout_delay) clk2x_out;
always @(clkdv_out)
CLKDV <= #(clkout_delay) clkdv_out;
endmodule |
module clkdll_maximum_period_check (clock, rst);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
clock_period <= $time - clock_edge;
if (clock_period > maximum_period && rst == 0) begin
$display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
end
end
endmodule |
module IBUFG_SSTL18_I (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module KEEPER (O);
inout O;
reg in;
always @(O)
if (O)
in <= 1;
else
in <= 0;
buf (pull1, pull0) B1 (O, in);
endmodule |
module IBUFG_SSTL3_I (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_PCIX (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR4B3 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, i2_inv, I3);
endmodule |
module IBUF_AGP (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_PCI66_3 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND3B2 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, I2);
endmodule |
module PULLDOWN (O);
output O;
wire A;
pulldown (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule |
module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE);
parameter INIT_A = 64'h0000000000000000;
parameter INIT_B = 64'h0000000000000000;
parameter INIT_C = 64'h0000000000000000;
parameter INIT_D = 64'h0000000000000000;
output [1:0] DOA;
output [1:0] DOB;
output [1:0] DOC;
output [1:0] DOD;
input [4:0] ADDRA;
input [4:0] ADDRB;
input [4:0] ADDRC;
input [4:0] ADDRD;
input [1:0] DIA;
input [1:0] DIB;
input [1:0] DIC;
input [1:0] DID;
input WCLK;
input WE;
reg [63:0] mem_a, mem_b, mem_c, mem_d;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(posedge WCLK)
if (WE) begin
mem_a[2*ADDRD] <= #100 DIA[0];
mem_a[2*ADDRD + 1] <= #100 DIA[1];
mem_b[2*ADDRD] <= #100 DIB[0];
mem_b[2*ADDRD + 1] <= #100 DIB[1];
mem_c[2*ADDRD] <= #100 DIC[0];
mem_c[2*ADDRD + 1] <= #100 DIC[1];
mem_d[2*ADDRD] <= #100 DID[0];
mem_d[2*ADDRD + 1] <= #100 DID[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD];
assign DOD[1] = mem_d[2*ADDRD + 1];
endmodule |
module MULT_AND (LO, I0, I1);
output LO;
input I0, I1;
and A1 (LO, I0, I1);
specify
(I0 *> LO) = (0, 0);
(I1 *> LO) = (0, 0);
endspecify
endmodule |
module NAND4B2 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, I2, I3);
endmodule |
module BUFT (O, I, T);
output O;
input I, T;
bufif0 T1 (O, I, T);
endmodule |
module IBUF_LVDS (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE);
parameter INIT = 16'h0000;
output DPO, SPO;
input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;
reg [15:0] mem;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign SPO = mem[adr];
assign DPO = mem[{DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUFG_HSTL_II_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module MUXCY_D (LO, O, CI, DI, S);
output LO, O;
reg O, LO;
input CI, DI, S;
always @(CI or DI or S)
if (S) begin
O = CI;
LO = CI;
end
else begin
O = DI;
LO = DI;
end
endmodule |
module IBUFG_SSTL2_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module TIMESPEC ();
endmodule |
module IBUF_GTL (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR2B2 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv);
endmodule |
module NOR3B2 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, I2);
endmodule |
module IBUF_SSTL18_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT = 16'h0000;
output O;
input A0, A1, A2, A3, D, WCLK, WE;
reg [15:0] mem;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(negedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUF_HSTL_I_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module MUXF5_D (LO, O, I0, I1, S);
output LO, O;
reg O, LO;
input I0, I1, S;
always @(I0 or I1 or S)
if (S) begin
O = I1;
LO = I1;
end
else begin
O = I0;
LO = I0;
end
endmodule |
module RAM16X2S (O0, O1, A0, A1, A2, A3, D0, D1, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
output O0, O1;
input A0, A1, A2, A3, D0, D1, WCLK, WE;
reg [15:0] mem1;
reg [15:0] mem2;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign O0 = mem1[adr];
assign O1 = mem2[adr];
initial begin
mem1 = INIT_00;
mem2 = INIT_01;
end
always @(posedge WCLK)
if (WE == 1'b1) begin
mem1[adr] <= #100 D0;
mem2[adr] <= #100 D1;
end
endmodule |
module IBUFG_PCI33_5 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_LVDS (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module CONFIG ();
endmodule |
module XOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
xor X1 (O, I0, I1, I2, I3, I4);
endmodule |
module ICAP_SPARTAN3A (BUSY, O, CE, CLK, I, WRITE);
output BUSY;
output [7:0] O;
input CE, CLK, WRITE;
input [7:0] I;
endmodule |
module NOR4B2 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, I2, I3);
endmodule |
module MULT18X18 (P, A, B);
output [35:0] P;
input [17:0] A;
input [17:0] B;
wire [35:0] a_in, b_in;
reg [35:0] p_out;
wire p0_out, p1_out, p2_out, p3_out, p4_out, p5_out, p6_out, p7_out, p8_out, p9_out, p10_out, p11_out, p12_out, p13_out, p14_out, p15_out, p16_out, p17_out, p18_out, p19_out, p20_out, p21_out, p22_out, p23_out, p24_out, p25_out, p26_out, p27_out, p28_out, p29_out, p30_out, p31_out, p32_out, p33_out, p34_out, p35_out;
buf A0 (a_in[0], A[0]);
buf A1 (a_in[1], A[1]);
buf A2 (a_in[2], A[2]);
buf A3 (a_in[3], A[3]);
buf A4 (a_in[4], A[4]);
buf A5 (a_in[5], A[5]);
buf A6 (a_in[6], A[6]);
buf A7 (a_in[7], A[7]);
buf A8 (a_in[8], A[8]);
buf A9 (a_in[9], A[9]);
buf A10 (a_in[10], A[10]);
buf A11 (a_in[11], A[11]);
buf A12 (a_in[12], A[12]);
buf A13 (a_in[13], A[13]);
buf A14 (a_in[14], A[14]);
buf A15 (a_in[15], A[15]);
buf A16 (a_in[16], A[16]);
buf A17 (a_in[17], A[17]);
buf A18 (a_in[18], A[17]);
buf A19 (a_in[19], A[17]);
buf A20 (a_in[20], A[17]);
buf A21 (a_in[21], A[17]);
buf A22 (a_in[22], A[17]);
buf A23 (a_in[23], A[17]);
buf A24 (a_in[24], A[17]);
buf A25 (a_in[25], A[17]);
buf A26 (a_in[26], A[17]);
buf A27 (a_in[27], A[17]);
buf A28 (a_in[28], A[17]);
buf A29 (a_in[29], A[17]);
buf A30 (a_in[30], A[17]);
buf A31 (a_in[31], A[17]);
buf A32 (a_in[32], A[17]);
buf A33 (a_in[33], A[17]);
buf A34 (a_in[34], A[17]);
buf A35 (a_in[35], A[17]);
buf B0 (b_in[0], B[0]);
buf B1 (b_in[1], B[1]);
buf B2 (b_in[2], B[2]);
buf B3 (b_in[3], B[3]);
buf B4 (b_in[4], B[4]);
buf B5 (b_in[5], B[5]);
buf B6 (b_in[6], B[6]);
buf B7 (b_in[7], B[7]);
buf B8 (b_in[8], B[8]);
buf B9 (b_in[9], B[9]);
buf B10 (b_in[10], B[10]);
buf B11 (b_in[11], B[11]);
buf B12 (b_in[12], B[12]);
buf B13 (b_in[13], B[13]);
buf B14 (b_in[14], B[14]);
buf B15 (b_in[15], B[15]);
buf B16 (b_in[16], B[16]);
buf B17 (b_in[17], B[17]);
buf B18 (b_in[18], B[17]);
buf B19 (b_in[19], B[17]);
buf B20 (b_in[20], B[17]);
buf B21 (b_in[21], B[17]);
buf B22 (b_in[22], B[17]);
buf B23 (b_in[23], B[17]);
buf B24 (b_in[24], B[17]);
buf B25 (b_in[25], B[17]);
buf B26 (b_in[26], B[17]);
buf B27 (b_in[27], B[17]);
buf B28 (b_in[28], B[17]);
buf B29 (b_in[29], B[17]);
buf B30 (b_in[30], B[17]);
buf B31 (b_in[31], B[17]);
buf B32 (b_in[32], B[17]);
buf B33 (b_in[33], B[17]);
buf B34 (b_in[34], B[17]);
buf B35 (b_in[35], B[17]);
buf P0 (P[0], p0_out);
buf P1 (P[1], p1_out);
buf P2 (P[2], p2_out);
buf P3 (P[3], p3_out);
buf P4 (P[4], p4_out);
buf P5 (P[5], p5_out);
buf P6 (P[6], p6_out);
buf P7 (P[7], p7_out);
buf P8 (P[8], p8_out);
buf P9 (P[9], p9_out);
buf P10 (P[10], p10_out);
buf P11 (P[11], p11_out);
buf P12 (P[12], p12_out);
buf P13 (P[13], p13_out);
buf P14 (P[14], p14_out);
buf P15 (P[15], p15_out);
buf P16 (P[16], p16_out);
buf P17 (P[17], p17_out);
buf P18 (P[18], p18_out);
buf P19 (P[19], p19_out);
buf P20 (P[20], p20_out);
buf P21 (P[21], p21_out);
buf P22 (P[22], p22_out);
buf P23 (P[23], p23_out);
buf P24 (P[24], p24_out);
buf P25 (P[25], p25_out);
buf P26 (P[26], p26_out);
buf P27 (P[27], p27_out);
buf P28 (P[28], p28_out);
buf P29 (P[29], p29_out);
buf P30 (P[30], p30_out);
buf P31 (P[31], p31_out);
buf P32 (P[32], p32_out);
buf P33 (P[33], p33_out);
buf P34 (P[34], p34_out);
buf P35 (P[35], p35_out);
assign {p35_out, p34_out, p33_out, p32_out, p31_out, p30_out, p29_out, p28_out, p27_out, p26_out, p25_out, p24_out, p23_out, p22_out, p21_out, p20_out, p19_out, p18_out, p17_out, p16_out, p15_out, p14_out, p13_out, p12_out, p11_out, p10_out, p9_out, p8_out, p7_out, p6_out, p5_out, p4_out, p3_out, p2_out, p1_out, p0_out} = a_in * b_in;
endmodule |
module NAND3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
nand A1 (O, I0, I1, I2);
endmodule |
module INV (O, I);
output O;
input I;
not N1 (O, I);
endmodule |
module MUXF6 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule |
module NOR5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
wire i4_inv;
not N4 (i4_inv, I4);
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);
endmodule |
module ROM256X1 (O, A0, A1, A2, A3, A4, A5, A6, A7);
parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6, A7;
reg [255:0] mem;
initial
mem = INIT;
assign O = mem[{A7, A6, A5, A4, A3, A2, A1, A0}];
endmodule |
module MUXF7_D (LO, O, I0, I1, S);
output LO, O;
reg O, LO;
input I0, I1, S;
always @(I0 or I1 or S)
if (S) begin
O = I1;
LO = I1;
end
else begin
O = I0;
LO = I0;
end
endmodule |
module IBUFG_LVCMOS15 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_SSTL3_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
or O1 (O, I0, I1, I2, I3);
endmodule |
module JTAGPPC (TCK, TDIPPC, TMS, TDOPPC, TDOTSPPC);
output TCK;
output TDIPPC;
output TMS;
input TDOPPC;
input TDOTSPPC;
assign TCK = 1'b1;
assign TDIPPC = 1'b1;
assign TMS = 1'b1;
endmodule |
module AND2 (O, I0, I1);
output O;
input I0, I1;
and A1 (O, I0, I1);
endmodule |
module IDELAYCTRL (RDY, REFCLK, RST);
output RDY;
input REFCLK;
input RST;
wire refclk_in;
wire rst_in;
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg lost, rdy_out = 0;
buf b_rdy (RDY, rdy_out);
buf b_refclk (refclk_in, REFCLK);
buf b_rst (rst_in, RST);
always @(rst_in, lost) begin
if ((rst_in == 1'b1) || (lost == 1))
rdy_out <= 1'b0;
else if (rst_in == 1'b0 && lost == 0)
rdy_out <= 1'b1;
end
/*
always @(posedge lost) begin
rdy_out <= 1'b0;
end
*/
initial begin
clock_edge <= 0;
clock_high <= 0;
clock_low <= 0;
lost <= 1;
period <= 0;
end
always @(posedge refclk_in) begin
if(rst_in == 1'b0) begin
clock_edge <= $time;
if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
period <= $time - clock_edge;
else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
period <= 0;
else if ((period == 0) && (clock_edge != 0))
period <= $time - clock_edge;
end
end
always @(posedge refclk_in) begin
clock_low <= 1'b0;
clock_high <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_posedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_low != 1'b1) && (clock_posedge != 1'b1))
lost <= 1;
end
always @(posedge refclk_in) begin
clock_negedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_posedge <= 1'b1;
end
always @(negedge refclk_in) begin
clock_high <= 1'b0;
clock_low <= 1'b1;
if (period != 0)
lost <= 1'b0;
clock_negedge <= 1'b0;
#((period * 9.1) / 10)
if ((clock_high != 1'b1) && (clock_negedge != 1'b1))
lost <= 1;
end
specify
(REFCLK => RDY) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDELAYCTRL |
module BUFGMUX_VIRTEX4 (O, I0, I1, S);
output O;
input I0;
input I1;
input S;
BUFGCTRL bufgctrl_inst (.O(O), .CE0(1'b1), .CE1(1'b1), .I0(I0), .I1(I1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(~S), .S1(S));
defparam bufgctrl_inst.INIT_OUT = 1'b0;
defparam bufgctrl_inst.PRESELECT_I0 = "TRUE";
defparam bufgctrl_inst.PRESELECT_I1 = "FALSE";
endmodule |
module AND2B1 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1);
endmodule |
module IBUF_LVPECL (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
endmodule |
module NOR2 (O, I0, I1);
output O;
input I0, I1;
nor O1 (O, I0, I1);
endmodule |
module DCM_CLKGEN (
CLKFX,
CLKFX180,
CLKFXDV,
LOCKED,
PROGDONE,
STATUS,
CLKIN,
FREEZEDCM,
PROGCLK,
PROGDATA,
PROGEN,
RST
);
parameter SPREAD_SPECTRUM = "NONE";
parameter STARTUP_WAIT = "FALSE";
parameter integer CLKFXDV_DIVIDE = 2;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter real CLKFX_MD_MAX = 0.0;
parameter real CLKIN_PERIOD = 0.0;
output CLKFX180;
output CLKFX;
output CLKFXDV;
output LOCKED;
output PROGDONE;
output [2:1] STATUS;
input CLKIN;
input FREEZEDCM;
input PROGCLK;
input PROGDATA;
input PROGEN;
input RST;
localparam OSC_P2 = 250;
reg clkfx_out = 0;
reg clkfx180_out = 0;
reg clkfxdv_out = 0;
wire clkfx_out1;
wire clkfx180_out1;
wire clkfxdv_out1;
reg rst_tmp1 = 0;
reg rst_tmp2 = 0;
reg [2:0] rst_reg = 3'b000;
reg rst_prog = 0;
reg locked_out = 0;
reg locked_out_out_u = 0;
reg progdone_out = 0;
reg progdone_out_u = 0;
reg lk_pd = 0;
reg lk_pd1 = 0;
reg lk_pd0 = 0;
reg clkfx_clk = 0;
reg clkin_ls_out = 0;
reg clkfx_ls_out = 0;
reg clk_osc = 0;
reg clkin_p = 0;
reg clkfx_p = 0;
reg [9:0] pg_sf_reg;
reg [7:0] pg_m_reg;
reg [7:0] pg_d_reg;
integer clkin_ls_val = 0;
integer clkfx_ls_val = 0;
integer clkin_ls_cnt = 0;
integer clkfx_ls_cnt = 0;
integer clkin_pd_init = 1000 * CLKIN_PERIOD;
integer lk_cnt = 0;
integer go_cmd = 0;
integer dcm_en_prog = 0;
integer pg_cnt = 0;
integer bit0_flag = 0;
integer first_time = 1;
integer attr_err_flag = 0;
integer period_sample = 0;
integer clkdv_cnt = 0;
integer fx_m = CLKFX_MULTIPLY;
integer fx_mt = CLKFX_MULTIPLY;
integer fx_d = CLKFX_DIVIDE;
integer fx_dt = CLKFX_DIVIDE;
real fx_n, fx_o;
real clkfx_md_ratio;
time clkin_edge = 0;
time clkin_pd = 0;
time clkin_pd1 = 0;
time lk_delay = 0;
integer spa;
integer fx_sn = 1024;
integer fx_sn1 = 512;
integer fx_sn2 = 512;
integer fx_sn11 = 256;
integer fx_sn12 = 256;
integer fx_sn21 = 256;
integer fx_sn22 = 256;
integer spju = 0, spd = 0;
real sps = 0.0;
real spst = 0.0;
real spst_tmp = 0.0;
real spst_tmp1 = 0.0;
reg spse = 0;
reg spse0 = 0;
reg spse1 = 0;
integer pd_fx = 0;
integer pd_fx_i = 0;
integer pdhf_fx = 0;
integer pdhf_fx1 = 0;
integer pdh_fx = 0;
integer pdh_fx_t = 0;
real pdh_fx_r = 0.0;
integer pdhfh_fx = 0;
integer pdhfh_fx_t = 0;
integer pdhfh_fx1 = 0;
integer rm_fx = 0;
integer rmh_fx = 0;
integer fxdv_div1;
integer fxdv_div_half;
integer rst_flag = 0;
time rst_pulse_wid = 0;
time rst_pos_edge = 0;
wire clkin_in;
wire freezedcm_in;
wire progclk_in;
wire progen_in;
wire progdata_in;
wire rst_in;
wire locked_out_out;
wire rst_ms;
wire locked_out_ms;
wire locked_out_ms1;
reg locked_out_ms2 = 0;
wire clkfx_ms_clk;
reg notifier;
wire delay_CLKIN;
wire delay_FREEZEDCM;
wire delay_PROGCLK;
wire delay_PROGDATA;
wire delay_PROGEN;
initial begin
attr_err_flag = 0;
case (CLKFXDV_DIVIDE)
2 : ;
4 : ;
8 : ;
16 : ;
32 : ;
default : begin
$display("Attribute Syntax Error : The Attribute CLKFXDV_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2, 4, 8, 16, or 32.", CLKFXDV_DIVIDE);
attr_err_flag = 1;
end
endcase
if (SPREAD_SPECTRUM == "NONE") begin
if ((CLKFX_DIVIDE < 1) || (CLKFX_DIVIDE > 256)) begin
$display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 1 ... 256.", CLKFX_DIVIDE);
attr_err_flag = 1;
end
end
else begin
if ((CLKFX_DIVIDE < 1) || (CLKFX_DIVIDE > 4)) begin
$display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 1 ... 4 in spread spectrum mode.", CLKFX_DIVIDE);
attr_err_flag = 1;
end
end
clkfx_md_ratio = CLKFX_MULTIPLY / CLKFX_DIVIDE;
if (CLKFX_MD_MAX > 0.0 && clkfx_md_ratio > CLKFX_MD_MAX) begin
$display("Attribute Syntax Error : The ratio of CLKFX_MULTIPLY / CLKFX_DIVIDE is %f on DCM_CLKGEN instance %m. It is over the value %f of attribute CLKFX_MD_MAX.", clkfx_md_ratio, CLKFX_MD_MAX);
attr_err_flag = 1;
end
if (SPREAD_SPECTRUM == "NONE") begin
if ((CLKFX_MULTIPLY < 2) || (CLKFX_MULTIPLY > 256)) begin
$display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2 ... 256.", CLKFX_MULTIPLY);
attr_err_flag = 1;
end
end
else begin
if ((CLKFX_MULTIPLY < 2) || (CLKFX_MULTIPLY > 32)) begin
$display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2 ... 32 in spread spectrum mode.", CLKFX_MULTIPLY);
attr_err_flag = 1;
end
end
case (SPREAD_SPECTRUM)
"NONE" : spa = 0;
"CENTER_HIGH_SPREAD" : spa = 1;
"CENTER_LOW_SPREAD" : spa = 2;
"VIDEO_LINK_M0" : spa = 3;
"VIDEO_LINK_M1" : spa = 4;
"VIDEO_LINK_M2" : spa = 5;
default : begin
$display("Attribute Syntax Error : The Attribute SPREAD_SPECTRUM on DCM_CLKGEN instance %m is set to %s. Legal values for this attribute are NONE, CENTER_HIGH_SPREAD, CENTER_LOW_SPREAD, VIDEO_LINK_M0, VIDEO_LINK_M1, or VIDEO_LINK_M2.", SPREAD_SPECTRUM);
end
endcase
case (STARTUP_WAIT)
"FALSE" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The Attribute STARTUP_WAIT on DCM_CLKGEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
attr_err_flag = 1;
end
endcase
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the DCM_CLKGEN, the simulator resolution must be set to 1ps.");
attr_err_flag = 1;
end
if (attr_err_flag == 1) begin
#1;
$finish;
end
end
assign STATUS[1] = clkin_ls_out;
assign STATUS[2] = clkfx_ls_out;
assign clkin_in = CLKIN;
assign freezedcm_in = FREEZEDCM;
assign progclk_in = PROGCLK;
assign progen_in = PROGEN;
assign progdata_in = PROGDATA;
assign rst_in = RST;
assign LOCKED = locked_out_out_u;
assign PROGDONE = progdone_out_u;
always @(locked_out_out)
locked_out_out_u <= #100 locked_out_out;
always @(progdone_out)
progdone_out_u <= #100 progdone_out;
assign CLKFX = clkfx_out1;
assign CLKFX180 = clkfx180_out1;
assign CLKFXDV = clkfxdv_out1;
initial begin
fxdv_div1 = CLKFXDV_DIVIDE - 1;
fxdv_div_half = CLKFXDV_DIVIDE/2;
pg_sf_reg = 10'b0;
pg_m_reg = fx_m - 1;
pg_d_reg = fx_d - 1;
end
// generate master reset signal
//
// assign rst_ms = rst_in | rst_prog;
assign rst_ms = rst_in;
always @(posedge clkin_in) begin
rst_reg[0] <= rst_in;
rst_reg[1] <= rst_reg[0] & rst_in;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in;
end
always @(rst_in) begin
if (rst_in == 1)
rst_flag <= #1 0;
rst_tmp1 = rst_in;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin
rst_flag = 1;
$display("Input Error : RST on DCM_CLKGEN instance %m at time %t must be asserted for 3 CLKIN clock cycles.", $time);
end
end
rst_tmp2 = rst_tmp1;
end
// RST less than 3 cycles, lock = x
assign locked_out_out = (rst_flag == 1) ? 1'bx : locked_out_ms1;
//
// CLKIN period calculation
//
always @(posedge clkin_in or posedge rst_in)
if (rst_in == 1) begin
clkin_pd <= clkin_pd_init;
clkin_pd1 <= clkin_pd_init;
clkin_edge <= 0;
period_sample <= 0;
end
else begin
if ( freezedcm_in == 0) begin
clkin_edge <= $time;
if (clkin_edge != 0) begin
clkin_pd1 <= clkin_pd;
clkin_pd <= $time - clkin_edge;
period_sample <= 1;
end
end
end
always @(negedge clkin_in or posedge rst_in)
if (rst_in == 1) begin
lk_cnt <= 0;
lk_pd0 <= 0;
end
else begin
if (lk_pd0 == 0) begin
if (freezedcm_in == 0) begin
lk_cnt <= lk_cnt + 1;
if (lk_cnt >= 14) begin
lk_pd0 <= 1;
end
end
else begin
if (clkin_pd == clkin_pd1 && period_sample == 1)
lk_pd0 <= 1;
end
end
end
//
// generate lock signal
//
always @(posedge lk_pd0 or posedge dcm_en_prog or posedge rst_ms)
if (rst_ms == 1) begin
locked_out <= 0;
lk_pd1 <= 0;
lk_pd <= 0;
end
else begin
locked_out <= #(lk_delay) lk_pd0;
lk_pd1 <= #1 lk_pd0;
lk_pd <= #2 lk_pd0;
end
assign locked_out_ms = locked_out;
assign locked_out_ms1 = (spa == 0 || (spa >= 3 && spa <= 5 && spse == 0)) ? locked_out : 0;
//
// generate fx clk from CLKIN period
//
always @(lk_pd0 or clkin_pd or fx_d or fx_m) begin
lk_delay = (clkin_pd / 2) - 1;
if (lk_pd0 == 1 ) begin
pd_fx = (clkin_pd * fx_d) / fx_m;
if (spse0 == 0)
pd_fx_i = pd_fx;
pdhf_fx = pd_fx / 2;
pdhf_fx1 = pdhf_fx - 1;
rm_fx = pd_fx - pdhf_fx;
clkin_ls_val = (clkin_pd * 2) / 500;
clkfx_ls_val = (pd_fx * 2) / 500;
fx_sn = (fx_m * 1024) / fx_d;
fx_sn1 = fx_sn / 2;
fx_sn2 = fx_sn - fx_sn1;
fx_sn11 = fx_sn1 /2;
fx_sn12 = fx_sn1 - fx_sn11;
fx_sn21 = fx_sn2 / 2;
fx_sn22 = fx_sn1 + fx_sn21;
if (spa == 1) begin
if (fx_d == 1)
sps = 200.0 / fx_sn;
else if (fx_d == 2)
sps = 125.0 / fx_sn;
else if (fx_d == 3)
sps = 100.0 / fx_sn;
else if (fx_d == 4)
sps = 75.0 / fx_sn;
end
else if (spa == 2) begin
if (fx_d == 1)
sps = 125.0 / fx_sn;
else if (fx_d == 2)
sps = 75.0 / fx_sn;
else if (fx_d == 3 )
sps = 65.0 / fx_sn;
else if (fx_d == 4)
sps = 60.0 / fx_sn;
end
else if (spa == 3)
sps = 5.4 / fx_m;
else if (spa == 4)
sps = 1.1 / fx_m;
else if (spa == 5)
sps = 0.3 / fx_m;
end
end
// always @(negedge clkfx_clk or rst_ms or rst_prog or lk_pd1)
always @(negedge clkfx_clk or rst_ms or lk_pd1 or lk_pd or posedge spse1 )
if (rst_ms == 1 || lk_pd1 == 0 ) begin
spju = 0;
spst = 0;
pdh_fx = pd_fx;
pdh_fx_t = pd_fx;
pdh_fx_r = pd_fx;
pdhfh_fx = pd_fx / 2;
pdhfh_fx_t = pd_fx / 2;
pdhfh_fx1 = pdhfh_fx - 1;
rmh_fx = pd_fx - pdhfh_fx;
end
else if (spse1 == 1) begin
pdh_fx = pd_fx_i;
pdh_fx_t = pd_fx_i;
pdh_fx_r = pd_fx_i;
pdhfh_fx = pd_fx_i / 2;
pdhfh_fx_t = pd_fx_i / 2;
pdhfh_fx1 = pdhfh_fx - 1;
rmh_fx = pd_fx_i - pdhfh_fx;
spst_tmp = 0.0;
spst = 0.0;
spst_tmp1 = 0.0;
end
else begin
if (lk_pd1 == 1) begin
if (spa == 1 || spa == 2) begin
if (spju >= fx_sn)
spju <= 0;
else
spju <= spju + 1;
if (spju == 0 || spju == fx_sn1) begin
spst <= 0;
pdh_fx_t = pd_fx;
end
else if ((spju > 0 && spju <= fx_sn11) || (spju > fx_sn22 && spju <= fx_sn)) begin
spst <= spst + sps;
pdh_fx_t = pd_fx + spst;
end
else if (spju > fx_sn11 && spju <= fx_sn22) begin
spst <= spst - sps;
pdh_fx_t = pd_fx + spst;
end
end
else if (spa >= 3 && spa <= 5 && spse == 1) begin
spst_tmp = spst + sps;
if (spst_tmp >= 1.0 ) begin
spst_tmp1 = $rtoi(spst_tmp);
spst <= spst_tmp - spst_tmp1;
end
else begin
spst_tmp1 = 0.0;
spst <= spst_tmp;
end
if (spd == 1)
pdh_fx_t = pdh_fx - spst_tmp1;
else
pdh_fx_t = pdh_fx + spst_tmp1;
end
if (spa != 0) begin
pdhfh_fx_t = pdh_fx_t / 2;
pdh_fx <= pdh_fx_t;
pdhfh_fx <= pdhfh_fx_t;
pdhfh_fx1 <= pdhfh_fx_t - 1;
rmh_fx <= pdh_fx_t - pdhfh_fx_t;
end
end
end
always @(clkfx_clk or posedge locked_out_ms or posedge rst_ms)
if (rst_ms == 1) begin
clkfx_clk = 0;
first_time <= 1;
end
else begin
if (locked_out_ms == 1) begin
if (first_time == 1) begin
clkfx_clk <= 1;
first_time <= 0;
end
else if (clkfx_clk == 1) begin
if (spa == 0 || (spse == 0 && spa >= 3 && spa <= 5))
clkfx_clk <= #(pdhf_fx) 0;
else
clkfx_clk <= #(pdhfh_fx) 0;
end
else if (clkfx_clk == 0) begin
if (spa == 0 || (spse == 0 && spa >= 3 && spa <= 5))
clkfx_clk <= #(rm_fx) 1;
else
clkfx_clk <= #(rmh_fx) 1;
end
end
end
always @(clk_osc or rst_ms)
if (rst_ms)
clk_osc <= 0;
else
clk_osc <= #OSC_P2 ~clk_osc;
always @(posedge clkin_in or negedge clkin_in) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge clkfx_out or negedge clkfx_out) begin
clkfx_p <= 1;
clkfx_p <= #100 0;
end
always @(posedge clk_osc or posedge rst_ms or posedge clkin_p)
if (rst_ms == 1 || clkin_p == 1) begin
clkin_ls_out <= 0;
clkin_ls_cnt <= 0;
end
else if (locked_out && freezedcm_in == 0) begin
if (clkin_ls_cnt < clkin_ls_val) begin
clkin_ls_cnt <= clkin_ls_cnt + 1;
clkin_ls_out <= 0;
end
else
clkin_ls_out <= 1;
end
always @(posedge clk_osc or posedge rst_ms or posedge clkfx_p)
if (rst_ms == 1 || clkfx_p == 1) begin
clkfx_ls_out <= 0;
clkfx_ls_cnt <= 0;
end
else if (locked_out && spa == 0) begin
if (clkfx_ls_cnt < clkfx_ls_val) begin
clkfx_ls_cnt <= clkfx_ls_cnt + 1;
clkfx_ls_out <= 0;
end
else
clkfx_ls_out <= 1;
end
//
// generate all output signal
//
assign clkfx_ms_clk = clkfx_clk;
always @(locked_out_ms)
locked_out_ms2 <= #1 locked_out_ms;
assign clkfx_out1 = (locked_out_ms2) ? clkfx_out : 0;
assign clkfx180_out1 = (locked_out_ms2) ? clkfx180_out : 0;
assign clkfxdv_out1 = (locked_out_ms2) ? clkfxdv_out : 0;
always @(posedge clkfx_ms_clk or negedge clkfx_ms_clk or posedge rst_ms)
if (rst_ms == 1) begin
clkfx_out = 0;
clkfx180_out = 0;
end
else
if (locked_out_ms == 1) begin
clkfx_out <= clkfx_ms_clk;
clkfx180_out <= !clkfx_ms_clk;
end
always @(posedge clkfx_ms_clk or posedge rst_ms)
if (rst_ms == 1) begin
clkfxdv_out = 0;
clkdv_cnt = 0;
end
else
begin
if (clkdv_cnt >= fxdv_div1)
clkdv_cnt <= 0;
else
clkdv_cnt <= clkdv_cnt + 1;
if (clkdv_cnt < fxdv_div_half )
clkfxdv_out <= 1;
else
clkfxdv_out <= 0;
end
//
//SPI for M/D dynamic change
//
always @(posedge progclk_in or posedge rst_in)
if (rst_in == 1) begin
progdone_out <= 1;
bit0_flag <= 0;
pg_cnt <= 0;
end
else begin
if (progen_in == 1) begin
if (bit0_flag == 0) begin
if (progdata_in == 0) begin
go_cmd <= 1;
end
else begin
progdone_out <= 0;
bit0_flag <= 1;
pg_cnt <= 1;
pg_sf_reg[9] <= progdata_in;
pg_sf_reg[8:0] <= 9'b0;
end
end
else begin
progdone_out <= 0;
if (pg_cnt >= 10) begin
$display("Warning : PROGDATA over 10 bit limit on X_DCMCLK_GEN on instance %m at time %t.", $time);
end
pg_sf_reg[8:0] <= pg_sf_reg[9:1];
pg_sf_reg[9] <= progdata_in;
pg_cnt <= pg_cnt + 1;
end
end
else begin
bit0_flag <= 0;
pg_cnt <= 0;
end
if (dcm_en_prog == 1)
progdone_out <= 1;
if (go_cmd ==1)
go_cmd <= 0;
end
always @(negedge progen_in)
if ( pg_sf_reg[1:0] == 2'b11)
pg_m_reg = pg_sf_reg[9:2];
else if ( pg_sf_reg[1:0] == 2'b01)
pg_d_reg = pg_sf_reg[9:2];
always @(posedge go_cmd) begin
@(negedge clkfx_out) begin
// rst_prog <= #pdhf_fx1 1;
// rst_prog <= #(pdhf_fx1 + pdhf_fx1) 0;
end
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge clkin_in);
if (spa >= 3 && spa <= 5) begin
spse0 <= 1;
end
@(posedge clkin_in) begin
fx_mt = pg_m_reg + 1;
fx_dt = pg_d_reg + 1;
fx_n = fx_mt / fx_dt;
fx_o = fx_m / fx_d;
if (fx_n > fx_o)
spd <= 1;
else if (fx_n < fx_o)
spd <= 0;
fx_m <= pg_m_reg + 1;
fx_d <= pg_d_reg + 1;
if (spa >= 3 && spa <= 5) begin
if (spse == 0) begin
spse1 <= #1 1;
spse1 <= #2 0;
spse <= #2 1;
end
end
else
spse <= 0;
end
@(posedge clkin_in);
clkfx_md_ratio = fx_m / fx_d;
if (CLKFX_MD_MAX > 0.0 && clkfx_md_ratio > CLKFX_MD_MAX) begin
$display("Error : The CLKFX MULTIPLIER and DIVIDER are programed to %d and %d on DCM_CLKGEN instance %m. The ratio of CLKFX MULTIPLIER / CLKFX DIVIDER is %f. It is over the value %f set by attribute CLKFX_MD_MAX.", fx_m, fx_d, clkfx_md_ratio, CLKFX_MD_MAX);
end
@(posedge clkin_in);
@(posedge clkin_in)
rst_prog <= 0;
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge clkin_in);
@(posedge progclk_in)
dcm_en_prog <= 1;
@(posedge progclk_in)
dcm_en_prog <= 0;
end
endmodule |
module IBUFG_HSTL_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_SSTL2_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR2B2 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv);
endmodule |
module RAM128X1S (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
reg [127:0] mem;
wire [6:0] adr;
assign adr = {A6, A5, A4, A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUFG_LVCMOS2 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module XOR2 (O, I0, I1);
output O;
input I0, I1;
xor X1 (O, I0, I1);
endmodule |
module SRLC32E (Q, Q31, A, CE, CLK, D);
parameter INIT = 32'h00000000;
output Q;
output Q31;
input [4:0] A;
input CE, CLK, D;
reg [31:0] data;
assign Q = data[A];
assign Q31 = data[31];
initial
begin
assign data = INIT;
while (CLK === 1'b1 || CLK===1'bX)
#10;
deassign data;
end
always @(posedge CLK)
if (CE == 1'b1)
data <= #100 {data[30:0], D};
endmodule |
module IBUFG_AGP (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_SSTL3_I (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_IV_DCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module LUT4_D (LO, O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
input I0, I1, I2, I3;
output O, LO;
reg O;
reg tmp;
wire LO;
assign LO = O;
always @( I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3;
if ( tmp == 0 || tmp == 1)
O = INIT[{I3, I2, I1, I0}];
else
O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}),
lut4_mux4 ( INIT[11:8], {I1, I0}),
lut4_mux4 ( INIT[7:4], {I1, I0}),
lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2});
end
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule |
module OR4B1 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
not N0 (i0_inv, I0);
or O1 (O, i0_inv, I1, I2, I3);
endmodule |
module NAND3B2 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, I2);
endmodule |
module CLKDLLE (
CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED,
CLKFB, CLKIN, RST);
parameter real CLKDV_DIVIDE = 2.0;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hC080; // non-simulatable
localparam integer MAXPERCLKIN = 40000; // simulation parameter
localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // simulation parameter
localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // simulation parameter
parameter STARTUP_WAIT = "FALSE"; // non-simulatable
input CLKFB, CLKIN, RST;
output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED;
reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV;
wire clkfb_in, clkin_in, rst_in;
wire clk0_out;
reg clk2x_out, clkdv_out, locked_out;
reg [1:0] clkfb_type;
reg [8:0] divide_type;
reg clk1x_type;
reg lock_period, lock_delay, lock_clkin, lock_clkfb;
reg [1:0] lock_out;
reg lock_fb;
reg fb_delay_found;
reg clock_stopped;
reg clkin_ps;
reg clkin_fb;
time clkin_edge;
time clkin_ps_edge;
time delay_edge;
time clkin_period [2:0];
time period;
time period_ps;
time period_orig;
time clkout_delay;
time fb_delay;
time period_dv_high, period_dv_low;
time cycle_jitter, period_jitter;
reg clkin_window, clkfb_window;
reg clkin_5050;
reg [2:0] rst_reg;
reg [23:0] i, n, d, p;
reg notifier;
initial begin
#1;
if ($realtime == 0) begin
$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
$display ("In order to simulate the CLKDLLE, the simulator resolution must be set to 1ps or smaller.");
$finish;
end
end
initial begin
case (CLKDV_DIVIDE)
1.5 : divide_type <= 'd3;
2.0 : divide_type <= 'd4;
2.5 : divide_type <= 'd5;
3.0 : divide_type <= 'd6;
3.5 : divide_type <= 'd7;
4.0 : divide_type <= 'd8;
4.5 : divide_type <= 'd9;
5.0 : divide_type <= 'd10;
5.5 : divide_type <= 'd11;
6.0 : divide_type <= 'd12;
6.5 : divide_type <= 'd13;
7.0 : divide_type <= 'd14;
7.5 : divide_type <= 'd15;
8.0 : divide_type <= 'd16;
9.0 : divide_type <= 'd18;
10.0 : divide_type <= 'd20;
11.0 : divide_type <= 'd22;
12.0 : divide_type <= 'd24;
13.0 : divide_type <= 'd26;
14.0 : divide_type <= 'd28;
15.0 : divide_type <= 'd30;
16.0 : divide_type <= 'd32;
default : begin
$display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on CLKDLLE instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE);
$finish;
end
endcase
clkfb_type <= 2;
period_jitter <= SIM_CLKIN_PERIOD_JITTER;
cycle_jitter <= SIM_CLKIN_CYCLE_JITTER;
case (DUTY_CYCLE_CORRECTION)
"false" : clk1x_type <= 0;
"FALSE" : clk1x_type <= 0;
"true" : clk1x_type <= 1;
"TRUE" : clk1x_type <= 1;
default : begin
$display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on CLKDLLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
$finish;
end
endcase
case (STARTUP_WAIT)
"false" : ;
"FALSE" : ;
"true" : ;
"TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute STARTUP_WAIT on CLKDLLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
$finish;
end
endcase
end
//
// input wire delays
//
buf b_clkin (clkin_in, CLKIN);
buf b_clkfb (clkfb_in, CLKFB);
buf b_rst (rst_in, RST);
buf #100 b_locked (LOCKED, locked_out);
clkdlle_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
always @(clkin_in or rst_in) begin
if (rst_in == 1'b0)
clkin_ps <= clkin_in;
else if (rst_in == 1'b1) begin
clkin_ps <= 1'b0;
@(negedge rst_reg[2]);
end
end
always @(clkin_ps or lock_fb) begin
clkin_fb <= #(period_ps) clkin_ps & lock_fb;
end
always @(posedge clkin_ps) begin
clkin_ps_edge <= $time;
if (($time - clkin_ps_edge) <= (1.5 * period_ps))
period_ps <= $time - clkin_ps_edge;
else if ((period_ps == 0) && (clkin_ps_edge != 0))
period_ps <= $time - clkin_ps_edge;
end
always @(posedge clkin_ps) begin
lock_fb <= lock_period;
end
always @(period or fb_delay)
clkout_delay <= period - fb_delay;
//
// generate master reset signal
//
always @(posedge clkin_in) begin
rst_reg[0] <= rst_in;
rst_reg[1] <= rst_reg[0] & rst_in;
rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in;
end
time rst_tmp1, rst_tmp2;
initial
begin
rst_tmp1 = 0;
rst_tmp2 = 0;
end
always @(posedge rst_in or negedge rst_in)
begin
if (rst_in ==1)
rst_tmp1 <= $time;
else if (rst_in==0 ) begin
rst_tmp2 = $time - rst_tmp1;
if (rst_tmp2 < 2000 && rst_tmp2 != 0)
$display("Input Error : RST on instance %m must be asserted at least for 2 ns.");
end
end
initial begin
clk2x_out <= 0;
clkdv_out <= 0;
clkin_5050 <= 0;
clkfb_window <= 0;
clkin_period[0] <= 0;
clkin_period[1] <= 0;
clkin_period[2] <= 0;
clkin_ps_edge <= 0;
clkin_window <= 0;
clkout_delay <= 0;
clock_stopped <= 1;
fb_delay <= 0;
fb_delay_found <= 0;
lock_clkfb <= 0;
lock_clkin <= 0;
lock_delay <= 0;
lock_fb <= 0;
lock_out <= 2'b00;
lock_period <= 0;
locked_out <= 0;
period <= 0;
period_ps <= 0;
period_orig <= 0;
rst_reg <= 3'b000;
end
always @(rst_in) begin
clkin_5050 <= 0;
clkfb_window <= 0;
clkin_period[0] <= 0;
clkin_period[1] <= 0;
clkin_period[2] <= 0;
clkin_ps_edge <= 0;
clkin_window <= 0;
clkout_delay <= 0;
clock_stopped <= 1;
fb_delay <= 0;
fb_delay_found <= 0;
lock_clkfb <= 0;
lock_clkin <= 0;
lock_delay <= 0;
lock_fb <= 0;
lock_out <= 2'b00;
lock_period <= 0;
locked_out <= 0;
period_ps <= 0;
end
//
// determine clock period
//
always @(posedge clkin_ps) begin
clkin_edge <= $time;
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
if (clkin_edge != 0)
clkin_period[0] <= $time - clkin_edge;
end
always @(negedge clkin_ps) begin
if (lock_period == 1'b0) begin
if ((clkin_period[0] != 0) &&
(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
lock_period <= 1;
period_orig <= (clkin_period[0] +
clkin_period[1] +
clkin_period[2]) / 3;
period <= clkin_period[0];
end
end
else if (lock_period == 1'b1) begin
if (100000000 < (clkin_period[0] / 1000)) begin
$display("Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
clkin_period[0] = clkin_period[1];
clock_stopped = 1'b1;
end
else if ((clkin_period[0] < period_orig - period_jitter) ||
(period_orig + period_jitter < clkin_period[0])) begin
$display("Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
$display("Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
lock_period <= 0;
@(negedge rst_reg[2]);
end
else begin
period <= clkin_period[0];
clock_stopped = 1'b0;
end
end
end
//
// determine clock delay
//
always @(posedge lock_period) begin
if (lock_period && clkfb_type != 0) begin
if (clkfb_type == 1) begin
@(posedge CLK0 or rst_in)
delay_edge = $time;
end
else if (clkfb_type == 2) begin
@(posedge CLK2X or rst_in)
delay_edge = $time;
end
@(posedge clkfb_in or rst_in)
fb_delay = ($time - delay_edge) % period_orig;
end
fb_delay_found = 1;
end
//
// determine feedback lock
//
always @(posedge clkfb_in) begin
#0 clkfb_window <= 1;
#cycle_jitter clkfb_window <= 0;
end
always @(posedge clkin_fb) begin
#0 clkin_window <= 1;
#cycle_jitter clkin_window <= 0;
end
always @(posedge clkin_fb) begin
#1
if (clkfb_window && fb_delay_found)
lock_clkin <= 1;
else
lock_clkin <= 0;
end
always @(posedge clkfb_in) begin
#1
if (clkin_window && fb_delay_found)
lock_clkfb <= 1;
else
lock_clkfb <= 0;
end
always @(negedge clkin_fb) begin
lock_delay <= lock_clkin || lock_clkfb;
end
//
// generate lock signal
//
always @(posedge clkin_ps) begin
lock_out[0] <= lock_period & lock_delay & lock_fb;
lock_out[1] <= lock_out[0];
locked_out <= lock_out[1];
end
//
// generate the clk1x_out
//
always @(posedge clkin_ps) begin
clkin_5050 <= 1;
#(period / 2)
clkin_5050 <= 0;
end
assign clk0_out = (clk1x_type) ? clkin_5050 : clkin_ps;
//
// generate the clk2x_out
//
always @(posedge clkin_ps) begin
clk2x_out <= 1;
#(period / 4)
clk2x_out <= 0;
if (lock_out[0]) begin
#(period / 4)
clk2x_out <= 1;
#(period / 4)
clk2x_out <= 0;
end
else begin
#(period / 2);
end
end
//
// generate the clkdv_out
//
always @(period) begin
// period_dv_high = (period / 2) * (divide_type / 2);
// period_dv_low = (period / 2) * (divide_type / 2 + divide_type % 2);
period_dv_high = (period * divide_type) / 4;
period_dv_low = (period * divide_type) / 4;
end
always @(posedge clkin_ps) begin
if (lock_out[0]) begin
clkdv_out = 1'b1;
#(period_dv_high);
clkdv_out = 1'b0;
#(period_dv_low);
clkdv_out = 1'b1;
#(period_dv_high);
clkdv_out = 1'b0;
#(period_dv_low - period / 2);
end
end
//
// generate all output signal
//
always @(clk0_out) begin
CLK0 <= #(clkout_delay) clk0_out;
end
always @(clk0_out) begin
CLK90 <= #(clkout_delay + period / 4) clk0_out;
end
always @(clk0_out) begin
CLK180 <= #(clkout_delay + period / 2) clk0_out;
end
always @(clk0_out) begin
CLK270 <= #(clkout_delay + (3 * period) / 4) clk0_out;
end
always @(clk2x_out) begin
CLK2X <= #(clkout_delay) clk2x_out;
end
always @(clk2x_out) begin
CLK2X180 <= #(clkout_delay + period / 4) clk2x_out;
end
always @(clkdv_out) begin
CLKDV <= #(clkout_delay) clkdv_out;
end
endmodule |
module VCC(P);
output P;
assign P = 1'b1;
endmodule |
module AND4B4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv);
endmodule |
module CAPTURE_FPGACORE (CAP, CLK);
input CAP, CLK;
parameter ONESHOT = "FALSE";
endmodule |
module NAND5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
endmodule |
module ROM128X1 (O, A0, A1, A2, A3, A4, A5, A6);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6;
reg [127:0] mem;
initial
mem = INIT;
assign O = mem[{A6, A5, A4, A3, A2, A1, A0}];
endmodule |
module IBUFG_HSTL_IV_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module CAPTURE_VIRTEX4 (CAP, CLK);
input CAP, CLK;
parameter ONESHOT = "TRUE";
endmodule |
module NAND5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, I2, I3, I4);
endmodule |
module NOR5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, I2, I3, I4);
endmodule |
module RAMB32_S64_ECC (
DO,
STATUS,
DI,
RDADDR,
RDCLK,
RDEN,
SSR,
WRADDR,
WRCLK,
WREN
);
parameter integer DO_REG = 0;
parameter SIM_COLLISION_CHECK = "ALL";
output [1:0] STATUS;
output [63:0] DO;
input RDCLK;
input RDEN;
input SSR;
input WRCLK;
input WREN;
input [63:0] DI;
input [8:0] RDADDR;
input [8:0] WRADDR;
reg [63:0] DO;
wire [31:0] do_ram16low;
wire [31:0] do_ram16up;
wire [3:0] dopa_ram16low;
wire [3:0] dopa_ram16up;
reg [31:0] DIB_up;
reg [31:0] DIB_low;
reg [3:0] DIPB_up;
reg [3:0] DIPB_low;
wire [31:0] DOB_low_open;
wire [3:0] DOPB_low_open;
wire CASCADEOUTA_low_open;
wire CASCADEOUTB_low_open;
wire [31:0] DOB_up_open;
wire [3:0] DOPB_up_open;
wire CASCADEOUTA_up_open;
wire CASCADEOUTB_up_open;
initial
DO <= 64'b0;
always @(posedge RDCLK )
begin
DO[13:0] <= do_ram16low[13:0];
DO[14] <= dopa_ram16low[1];
DO[15] <= dopa_ram16low[3];
DO[29:16] <= do_ram16low[29:16];
DO[30] <= dopa_ram16low[0];
DO[31] <= dopa_ram16low[2];
DO[32] <= dopa_ram16up[0];
DO[33] <= dopa_ram16up[2];
DO[47:34] <= do_ram16up[15:2];
DO[48] <= dopa_ram16up[1];
DO[49] <= dopa_ram16up[3];
DO[63:50] <= do_ram16up[31:18];
end
always @(DI)
begin
DIB_low [13:0] <= DI[13:0];
DIB_low [15:14] <= 2'b00;
DIPB_low[1] <= DI[14];
DIPB_low[3] <= DI[15];
DIB_low[29:16] <= DI[29:16];
DIB_low[31:30] <= 2'b00;
DIPB_low[0] <= DI[30];
DIPB_low[2] <= DI[31];
DIPB_up[0] <= DI[32];
DIPB_up[2] <= DI[33];
DIB_up[15:2] <= DI[47:34];
DIB_up[1:0] <= 2'b00;
DIPB_up[1] <= DI[48];
DIPB_up[3] <= DI[49];
DIB_up[17:16] <= 2'b00;
DIB_up[31:18] <= DI[63:50];
end
assign STATUS = 2'b00;
RAMB16 RAMB16_LOWER (
.ADDRA ({1'b1, RDADDR, 5'b00000}),
.ADDRB ({1'b1, WRADDR, 5'b00000}),
.DIA (32'b0),
.DIB (DIB_low),
.DIPA (4'b0),
.DIPB (DIPB_low),
.ENA (RDEN),
.ENB (WREN),
.WEA (4'b0),
.WEB (4'b1111),
.SSRA (SSR),
.SSRB (1'b0),
.CLKA (RDCLK),
.CLKB (WRCLK),
.REGCEA (1'b1),
.REGCEB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.DOA (do_ram16low),
.DOB (DOB_low_open),
.DOPA (dopa_ram16low),
.DOPB (DOPB_low_open),
.CASCADEOUTA (CASCADEOUTA_low_open),
.CASCADEOUTB (CASCADEOUTB_low_open)
);
defparam RAMB16_LOWER.READ_WIDTH_A = 36;
defparam RAMB16_LOWER.WRITE_WIDTH_A = 36;
defparam RAMB16_LOWER.READ_WIDTH_B = 36;
defparam RAMB16_LOWER.WRITE_WIDTH_B = 36;
defparam RAMB16_LOWER.WRITE_MODE_A = "READ_FIRST";
defparam RAMB16_LOWER.WRITE_MODE_B = "READ_FIRST";
defparam RAMB16_LOWER.INIT_A = 36'b0;
defparam RAMB16_LOWER.SRVAL_A = 36'b0;
defparam RAMB16_LOWER.INIT_B = 36'b0;
defparam RAMB16_LOWER.SRVAL_B = 36'b0;
defparam RAMB16_LOWER.DOA_REG = DO_REG;
defparam RAMB16_LOWER.DOB_REG = 0;
defparam RAMB16_LOWER.INVERT_CLK_DOA_REG = "FALSE";
defparam RAMB16_LOWER.INVERT_CLK_DOB_REG = "FALSE";
defparam RAMB16_LOWER.RAM_EXTENSION_A = "NONE";
defparam RAMB16_LOWER.RAM_EXTENSION_B = "NONE";
defparam RAMB16_LOWER.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK;
RAMB16 RAMB16_UPPER (
.ADDRA ({1'b1, RDADDR, 5'b00000}),
.ADDRB ({1'b1, WRADDR, 5'b00000}),
.DIA (32'b0),
.DIB (DIB_up),
.DIPA (4'b0),
.DIPB (DIPB_up),
.ENA (RDEN),
.ENB (WREN),
.WEA (4'b0),
.WEB (4'b1111),
.SSRA (SSR),
.SSRB (1'b0),
.CLKA (RDCLK),
.CLKB (WRCLK),
.REGCEA (1'b1),
.REGCEB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.DOA (do_ram16up),
.DOB (DOB_up_open),
.DOPA (dopa_ram16up),
.DOPB (DOPB_up_open),
.CASCADEOUTA (CASCADEOUTA_up_open),
.CASCADEOUTB (CASCADEOUTB_up_open)
);
defparam RAMB16_UPPER.READ_WIDTH_A = 36;
defparam RAMB16_UPPER.WRITE_WIDTH_A = 36;
defparam RAMB16_UPPER.READ_WIDTH_B = 36;
defparam RAMB16_UPPER.WRITE_WIDTH_B = 36;
defparam RAMB16_UPPER.WRITE_MODE_A = "READ_FIRST";
defparam RAMB16_UPPER.WRITE_MODE_B = "READ_FIRST";
defparam RAMB16_UPPER.INIT_A = 36'b0;
defparam RAMB16_UPPER.SRVAL_A = 36'b0;
defparam RAMB16_UPPER.INIT_B = 36'b0;
defparam RAMB16_UPPER.SRVAL_B = 36'b0;
defparam RAMB16_UPPER.DOA_REG = DO_REG;
defparam RAMB16_UPPER.DOB_REG = 0;
defparam RAMB16_UPPER.INVERT_CLK_DOA_REG = "FALSE";
defparam RAMB16_UPPER.INVERT_CLK_DOB_REG = "FALSE";
defparam RAMB16_UPPER.RAM_EXTENSION_A = "NONE";
defparam RAMB16_UPPER.RAM_EXTENSION_B = "NONE";
defparam RAMB16_UPPER.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK;
endmodule |
module IBUFG_GTLP_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module ROM16X1 (O, A0, A1, A2, A3);
parameter INIT = 16'h0000;
output O;
input A0, A1, A2, A3;
reg [15:0] mem;
initial
mem = INIT;
assign O = mem[{A3, A2, A1, A0}];
endmodule |
module IBUFG_PCIX (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module XORCY (O, CI, LI);
output O;
input CI, LI;
xor X1 (O, CI, LI);
endmodule |
module IBUF_SSTL2_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module CFGLUT5 (CDO, O5, O6, CDI, CE, CLK, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
output CDO;
output O5;
output O6;
input I4, I3, I2, I1, I0;
input CDI, CE, CLK;
reg [31:0] data;
assign O6 = data[{I4, I3, I2, I1, I0}];
assign O5 = data[{I3, I2, I1, I0}];
assign CDO = data[31];
initial
begin
assign data = INIT;
while (CLK === 1'b1 || CLK===1'bX)
#10;
deassign data;
end
always @(posedge CLK)
if (CE == 1'b1) begin
data <= #100 {data[30:0], CDI};
end
endmodule |
module IBUF_DLY_ADJ (O, I, S);
output O;
input I;
input [2:0] S;
parameter DELAY_OFFSET = "OFF";
parameter IOSTANDARD = "DEFAULT";
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the
// following parameter is changed.
localparam SIM_TAPDELAY_VALUE = 200;
localparam SPECTRUM_OFFSET_DELAY = 1600;
// xilinx_internal_parameter off
reg o_out;
wire [2:0] s_in;
integer delay_count;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7;
wire i_in;
buf buf_o (O, o_out);
buf buf_i (i_in, I);
buf buf_s[2:0] (s_in, S);
// buf buf_gsr (gsr_in, GSR);
time INITIAL_DELAY = 0;
time FINAL_DELAY = 0;
initial begin
if (DELAY_OFFSET != "ON" && DELAY_OFFSET != "OFF") begin
$display("Attribute Syntax Error : The attribute DELAY_OFFSET on IBUF_DLY_ADJ instance %m is set to %s. Legal values for this attribute are ON or OFF", DELAY_OFFSET);
$finish;
end
if(DELAY_OFFSET == "ON")
// CR 447604
// INITIAL_DELAY = SPECTRUM_OFFSET_DELAY;
INITIAL_DELAY = SPECTRUM_OFFSET_DELAY + SIM_TAPDELAY_VALUE;
else
// INITIAL_DELAY = 0;
INITIAL_DELAY = SIM_TAPDELAY_VALUE;
end // initial begin
//------------------------------------------------------------
//--------------------------- GSR ----------------------------
//------------------------------------------------------------
// always @(gsr_in)
// if (gsr_in == 1'b1)
// assign delay_count = 0;
// else if (gsr_in == 1'b0)
// deassign delay_count;
//------------------------------------------------------------
//----------------------- S input ----------------------------
//------------------------------------------------------------
always@s_in
// #FINAL_DELAY = s_in * SIM_TAP_DELAY_VALUE + INITIAL_DELAY;
delay_count = s_in;
//------------------------------------------------------------
//---------------------- delay the chain --------------------
//------------------------------------------------------------
assign #INITIAL_DELAY delay_chain_0 = i_in;
assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0;
assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1;
assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2;
assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3;
assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4;
assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5;
assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6;
//------------------------------------------------------------
//---------------------- Assign to output -------------------
//------------------------------------------------------------
always @(delay_count) begin
case (delay_count)
0: assign o_out = delay_chain_0;
1: assign o_out = delay_chain_1;
2: assign o_out = delay_chain_2;
3: assign o_out = delay_chain_3;
4: assign o_out = delay_chain_4;
5: assign o_out = delay_chain_5;
6: assign o_out = delay_chain_6;
7: assign o_out = delay_chain_7;
default:
assign o_out = delay_chain_0;
endcase
end // always @ (s_in)
endmodule // IBUF_DLY_ADJ |
module ROM32X1 (O, A0, A1, A2, A3, A4);
parameter INIT = 32'h00000000;
output O;
input A0, A1, A2, A3, A4;
reg [31:0] mem;
initial
mem = INIT;
assign O = mem[{A4, A3, A2, A1, A0}];
endmodule |
module MUXF8 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule |
module IBUFG_HSTL_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
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