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module NAND3B1 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, I1, I2);
endmodule |
module IBUFG_SSTL2_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module LUT4 (O, I0, I1, I2, I3);
parameter INIT = 16'h0000;
input I0, I1, I2, I3;
output O;
reg O;
reg tmp;
always @( I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3;
if ( tmp == 0 || tmp == 1)
O = INIT[{I3, I2, I1, I0}];
else
O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}),
lut4_mux4 ( INIT[11:8], {I1, I0}),
lut4_mux4 ( INIT[7:4], {I1, I0}),
lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2});
end
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule |
module IBUF_SSTL3_II (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND3B1 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2);
endmodule |
module LUT6 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
else
O = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}),
lut6_mux8 ( INIT[55:48], {I2, I1, I0}),
lut6_mux8 ( INIT[47:40], {I2, I1, I0}),
lut6_mux8 ( INIT[39:32], {I2, I1, I0}),
lut6_mux8 ( INIT[31:24], {I2, I1, I0}),
lut6_mux8 ( INIT[23:16], {I2, I1, I0}),
lut6_mux8 ( INIT[15:8], {I2, I1, I0}),
lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3});
end
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
endmodule |
module FRAME_ECC_VIRTEX4 (ERROR, SYNDROME, SYNDROMEVALID);
output ERROR;
output [11:0] SYNDROME;
output SYNDROMEVALID;
endmodule // FRAME_ECC_VIRTEX4 |
module AND4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
and A1 (O, I0, I1, I2, I3);
endmodule |
module NAND3B3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv);
endmodule |
module IBUFG_HSTL_III_DCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM16X1S (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT = 16'h0000;
output O;
input A0, A1, A2, A3, D, WCLK, WE;
reg [15:0] mem;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module NAND2B2 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv);
endmodule |
module IBUFG_HSTL_I (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR2B1 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
or O1 (O, i0_inv, I1);
endmodule |
module NOR3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
nor O1 (O, I0, I1, I2);
endmodule |
module IBUFG_HSTL_I_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
nor O1 (O, I0, I1, I2, I3, I4);
endmodule |
module BUFIO (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module BSCAN_SPARTAN3 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
input TDO1, TDO2;
output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;
pulldown (DRCK1);
pulldown (DRCK2);
pulldown (RESET);
pulldown (SEL1);
pulldown (SEL2);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
endmodule |
module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O5, O6;
reg [63:0] init_reg = INIT;
reg [31:0] init_l, init_h;
reg O_l, O_h, tmp;
reg O5, O6;
initial begin
init_l = init_reg[31:0];
init_h = init_reg[63:32];
end
always @(I5 or O_l or O_h) begin
O5 = O_l;
if (I5 == 1)
O6 = O_h;
else if (I5 == 0)
O6 = O_l;
else begin
if (O_h == 0 && O_l == 0)
O6 = 1'b0;
else if (O_h == 1 && O_l == 1)
O6 = 1'b1;
else
O6 = 1'bx;
end
end
always @( I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4;
if ( tmp == 0 || tmp == 1) begin
O_l = init_l[{I4, I3, I2, I1, I0}];
O_h = init_h[{I4, I3, I2, I1, I0}];
end
else begin
O_l = lut4_mux4 (
{ lut6_mux8 ( init_l[31:24], {I2, I1, I0}),
lut6_mux8 ( init_l[23:16], {I2, I1, I0}),
lut6_mux8 ( init_l[15:8], {I2, I1, I0}),
lut6_mux8 ( init_l[7:0], {I2, I1, I0}) }, { I4, I3});
O_h = lut4_mux4 (
{ lut6_mux8 ( init_h[31:24], {I2, I1, I0}),
lut6_mux8 ( init_h[23:16], {I2, I1, I0}),
lut6_mux8 ( init_h[15:8], {I2, I1, I0}),
lut6_mux8 ( init_h[7:0], {I2, I1, I0}) }, { I4, I3});
end
end
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) )
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule |
module IBUFG_LVDCI_DV2_33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_LVTTL (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module TBLOCK ();
endmodule |
module BUFH (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVDCI_DV2_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVDCI_DV2_33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR4B4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv);
endmodule |
module ROM64X1 (O, A0, A1, A2, A3, A4, A5);
parameter INIT = 64'h0000000000000000;
output O;
input A0, A1, A2, A3, A4, A5;
reg [63:0] mem;
initial
mem = INIT;
assign O = mem[{A5, A4, A3, A2, A1, A0}];
endmodule |
module OR5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, I2, I3, I4);
endmodule |
module RAM16X4S (O0, O1, O2, O3, A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
output O0, O1, O2, O3;
input A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE;
reg [15:0] mem0;
reg [15:0] mem1;
reg [15:0] mem2;
reg [15:0] mem3;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign O0 = mem0[adr];
assign O1 = mem1[adr];
assign O2 = mem2[adr];
assign O3 = mem3[adr];
initial begin
mem0 = INIT_00;
mem1 = INIT_01;
mem2 = INIT_02;
mem3 = INIT_03;
end
always @(posedge WCLK)
if (WE == 1'b1) begin
mem0[adr] <= #100 D0;
mem1[adr] <= #100 D1;
mem2[adr] <= #100 D2;
mem3[adr] <= #100 D3;
end
endmodule |
module IBUF_PCI33_5 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFDS_DLY_ADJ (O, I, IB, S);
output O;
input I, IB;
input [2:0] S;
parameter DELAY_OFFSET = "OFF";
parameter DIFF_TERM = "FALSE";
parameter IOSTANDARD = "DEFAULT";
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the
// following parameter is changed.
localparam SIM_TAPDELAY_VALUE = 200;
localparam SPECTRUM_OFFSET_DELAY = 1600;
// xilinx_internal_parameter off
reg o_out;
reg i_int;
wire [2:0] s_in;
wire i_in;
wire ib_in;
integer delay_count;
wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3,
delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7;
buf buf_o (O, o_out);
buf buf_i (i_in, I);
buf buf_ib (ib_in, IB);
buf buf_s[2:0] (s_in, S);
time INITIAL_DELAY = 0;
time FINAL_DELAY = 0;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
if (DELAY_OFFSET != "ON" && DELAY_OFFSET != "OFF") begin
$display("Attribute Syntax Error : The attribute DELAY_OFFSET on IBUFDS_DLY_ADJ instance %m is set to %s. Legal values for this attribute are ON or OFF", DELAY_OFFSET);
$finish;
end
if(DELAY_OFFSET == "ON")
// CR 447604
// INITIAL_DELAY = SPECTRUM_OFFSET_DELAY;
INITIAL_DELAY = SPECTRUM_OFFSET_DELAY + SIM_TAPDELAY_VALUE;
else
// INITIAL_DELAY = 0;
INITIAL_DELAY = SIM_TAPDELAY_VALUE;
end // initial begin
//------------------------------------------------------------
//---------------------- delay the chain --------------------
//------------------------------------------------------------
always @(i_in or ib_in) begin
if (i_in == 1'b1 && ib_in == 1'b0)
i_int <= i_in;
else if (i_in == 1'b0 && ib_in == 1'b1)
i_int <= i_in;
end
//------------------------------------------------------------
//----------------------- S input ----------------------------
//------------------------------------------------------------
always@s_in
// #FINAL_DELAY = s_in * SIM_TAP_DELAY_VALUE + INITIAL_DELAY;
delay_count = s_in;
//------------------------------------------------------------
//---------------------- delay the chain --------------------
//------------------------------------------------------------
assign #INITIAL_DELAY delay_chain_0 = i_int;
assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0;
assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1;
assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2;
assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3;
assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4;
assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5;
assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6;
//------------------------------------------------------------
//---------------------- Assign to output -------------------
//------------------------------------------------------------
always @(delay_count) begin
case (delay_count)
0: assign o_out = delay_chain_0;
1: assign o_out = delay_chain_1;
2: assign o_out = delay_chain_2;
3: assign o_out = delay_chain_3;
4: assign o_out = delay_chain_4;
5: assign o_out = delay_chain_5;
6: assign o_out = delay_chain_6;
7: assign o_out = delay_chain_7;
default:
assign o_out = delay_chain_0;
endcase
end // always @ (s_in)
endmodule // IBUFDS_DLY_ADJ |
module OFDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
output Q;
input C0, C1, CE, D0, D1, R, S;
wire q_out;
FDDRRSE F0 (.C0(C0),
.C1(C1),
.CE(CE),
.R(R),
.D0(D0),
.D1(D1),
.S(S),
.Q(q_out));
defparam F0.INIT = 1'b0;
OBUF O1 (.I(q_out),
.O(Q));
endmodule |
module NAND4B3 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv, I3);
endmodule |
module IBUF_HSTL_III (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
nor O1 (O, I0, I1, I2, I3);
endmodule |
module IBUF_HSTL_III_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_PCIX66_3 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_PCI33_3 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_GTL_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVDCI_33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM256X1S (O, A, D, WCLK, WE);
parameter INIT = 256'h0;
output O;
input [7:0] A;
input D;
input WCLK;
input WE;
reg [255:0] mem;
initial
mem = INIT;
assign O = mem[A];
always @(posedge WCLK)
if (WE == 1'b1)
mem[A] <= #100 D;
endmodule |
module MUXF5_L (LO, I0, I1, S);
output LO;
reg LO;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
LO = I1;
else
LO = I0;
endmodule |
module AND4B1 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2, I3);
endmodule |
module IBUF_LVCMOS18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_LVCMOS12 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NAND5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
nand A1 (O, I0, I1, I2, I3, I4);
endmodule |
module IBUFDS_LDT_25 (O, I, IB);
output O;
input I, IB;
reg o_out;
buf b_0 (O, o_out);
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
endmodule |
module USR_ACCESS_VIRTEX6 (
CFGCLK,
DATA,
DATAVALID
);
output CFGCLK;
output DATAVALID;
output [31:0] DATA;
endmodule |
module IBUFDS_BLVDS_25 (O, I, IB);
output O;
input I, IB;
reg o_out;
buf b_0 (O, o_out);
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
endmodule |
module IBUFG_LVCMOS25 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFGDS (O, I, IB);
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O;
input I, IB;
reg o_out;
buf b_0 (O, o_out);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz)
o_out <= 1'bx;
end
endmodule |
module RAM32X2S (O0, O1, A0, A1, A2, A3, A4, D0, D1, WCLK, WE);
parameter INIT_00 = 32'h00000000;
parameter INIT_01 = 32'h00000000;
output O0, O1;
input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
reg [31:0] mem1;
reg [31:0] mem2;
wire [4:0] adr;
assign adr = {A4, A3, A2, A1, A0};
assign O0 = mem1[adr];
assign O1 = mem2[adr];
initial begin
mem1 = INIT_00;
mem2 = INIT_01;
end
always @(posedge WCLK)
if (WE == 1'b1) begin
mem1[adr] <= #100 D0;
mem2[adr] <= #100 D1;
end
endmodule |
module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T);
output O;
input C0, C1, CE, D0, D1, R, S, T;
wire q_out;
FDDRRSE F0 (.C0(C0),
.C1(C1),
.CE(CE),
.R(R),
.D0(D0),
.D1(D1),
.S(S),
.Q(q_out));
defparam F0.INIT = 1'b0;
OBUFT O1 (.I(q_out),
.T(T),
.O(O));
endmodule |
module XNOR3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
xnor X1 (O, I0, I1, I2);
endmodule |
module IBUFG_HSTL_III (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_SSTL18_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module MUXF8_L (LO, I0, I1, S);
output LO;
reg LO;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
LO = I1;
else
LO = I0;
endmodule |
module FMAP (I1, I2, I3, I4, O);
input I1, I2, I3, I4, O;
endmodule |
module OR5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
wire i4_inv;
not N4 (i4_inv, I4);
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);
endmodule |
module NAND5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4);
endmodule |
module RAM32X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
parameter INIT = 32'h00000000;
output DPO, SPO;
input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
reg [31:0] mem;
wire [4:0] adr;
assign adr = {A4, A3, A2, A1, A0};
assign SPO = mem[adr];
assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(negedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module NOR5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, I1, I2, I3, I4);
endmodule |
module BUFGCE (O, CE, I);
output O;
input CE, I;
wire NCE;
BUFGMUX B1 (.I0(I),
.I1(1'b0),
.O(O),
.S(NCE));
INV I1 (.I(CE),
.O(NCE));
endmodule |
module IBUFG_SSTL3_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM64X1D (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output DPO, SPO;
input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
reg [63:0] mem;
wire [5:0] adr;
assign adr = {A5, A4, A3, A2, A1, A0};
assign SPO = mem[adr];
assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module OR5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
not N0 (i0_inv, I0);
or O1 (O, i0_inv, I1, I2, I3, I4);
endmodule |
module IBUFG_PCI66_3 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM32X1S_1 (O, A0, A1, A2, A3, A4, D, WCLK, WE);
parameter INIT = 32'h00000000;
output O;
input A0, A1, A2, A3, A4, D, WCLK, WE;
reg [31:0] mem;
wire [4:0] adr;
assign adr = {A4, A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(negedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUF_HSTL_I_DCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_SSTL18_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR3B1 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
not N0 (i0_inv, I0);
or O1 (O, i0_inv, I1, I2);
endmodule |
module DCM_BASE (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
CLKFB,
CLKIN,
RST
);
parameter real CLKDV_DIVIDE = 2.0;
parameter integer CLKFX_DIVIDE = 1;
parameter integer CLKFX_MULTIPLY = 4;
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
parameter real CLKIN_PERIOD = 10.0;
parameter CLKOUT_PHASE_SHIFT = "NONE";
parameter CLK_FEEDBACK = "1X";
parameter DCM_AUTOCALIBRATION = "TRUE";
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
parameter DFS_FREQUENCY_MODE = "LOW";
parameter DLL_FREQUENCY_MODE = "LOW";
parameter DUTY_CYCLE_CORRECTION = "TRUE";
parameter FACTORY_JF = 16'hF0F0;
parameter integer PHASE_SHIFT = 0;
parameter STARTUP_WAIT = "FALSE";
output CLK0;
output CLK180;
output CLK270;
output CLK2X180;
output CLK2X;
output CLK90;
output CLKDV;
output CLKFX180;
output CLKFX;
output LOCKED;
input CLKFB;
input CLKIN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire [15:0] OPEN_DO;
initial
begin
if (CLKOUT_PHASE_SHIFT != "NONE" && CLKOUT_PHASE_SHIFT != "FIXED")
begin
$display(" Attribute Syntax Error :The attribute CLKOUT_PHASE_SHIFT on DCM_BASE instance %m is set to %s. Legal values for this attribute is NONE or FIXED", CLKOUT_PHASE_SHIFT);
$finish;
end
if (CLK_FEEDBACK != "NONE" && CLK_FEEDBACK != "1X")
begin
$display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_BASE instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK);
$finish;
end
end
DCM_ADV dcm_adv_1 (
.CLK0 (CLK0),
.CLK180 (CLK180),
.CLK270 (CLK270),
.CLK2X (CLK2X),
.CLK2X180 (CLK2X180),
.CLK90 (CLK90),
.CLKDV (CLKDV),
.CLKFB (CLKFB),
.CLKFX (CLKFX),
.CLKFX180 (CLKFX180),
.CLKIN (CLKIN),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.DADDR (7'b0000000),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0000),
.DWE (1'b0),
.PSDONE (OPEN_PSDONE),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (RST)
);
defparam dcm_adv_1.CLKDV_DIVIDE = CLKDV_DIVIDE;
defparam dcm_adv_1.CLKFX_DIVIDE = CLKFX_DIVIDE;
defparam dcm_adv_1.CLKFX_MULTIPLY = CLKFX_MULTIPLY;
defparam dcm_adv_1.CLKIN_DIVIDE_BY_2 = CLKIN_DIVIDE_BY_2;
defparam dcm_adv_1.CLKIN_PERIOD = CLKIN_PERIOD;
defparam dcm_adv_1.CLKOUT_PHASE_SHIFT = CLKOUT_PHASE_SHIFT;
defparam dcm_adv_1.CLK_FEEDBACK = CLK_FEEDBACK;
defparam dcm_adv_1.DCM_AUTOCALIBRATION = DCM_AUTOCALIBRATION;
defparam dcm_adv_1.DCM_PERFORMANCE_MODE = DCM_PERFORMANCE_MODE;
defparam dcm_adv_1.DESKEW_ADJUST = DESKEW_ADJUST;
defparam dcm_adv_1.DFS_FREQUENCY_MODE = DFS_FREQUENCY_MODE;
defparam dcm_adv_1.DLL_FREQUENCY_MODE = DLL_FREQUENCY_MODE;
defparam dcm_adv_1.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION;
defparam dcm_adv_1.FACTORY_JF = FACTORY_JF;
defparam dcm_adv_1.PHASE_SHIFT = PHASE_SHIFT;
defparam dcm_adv_1.STARTUP_WAIT = STARTUP_WAIT;
endmodule |
module IBUFG_SSTL18_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVDCI_15 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND3B3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, i2_inv);
endmodule |
module BUFIO2FB (O, I);
parameter DIVIDE_BYPASS = "TRUE"; // TRUE, FALSE
output O;
input I;
reg divclk_bypass_attr;
// Other signals
reg attr_err_flag = 0;
//----------------------------------------------------------------------
//------------------------ Output Ports ------------------------------
//----------------------------------------------------------------------
buf buf_o(O, I);
initial begin
//-------------------------------------------------
//----- DIVIDE_BYPASS Check
//-------------------------------------------------
case (DIVIDE_BYPASS)
"TRUE" : divclk_bypass_attr <= 1'b1;
"FALSE" :divclk_bypass_attr <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DIVIDE_BYPASS on BUFIO2FB instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", DIVIDE_BYPASS);
attr_err_flag = 1;
end
endcase // (DIVIDE_BYPASS)
if (attr_err_flag)
begin
#1;
$finish;
end
end // initial begin
endmodule // BUFIO2FB |
module BUFGDLL (O, I);
output O;
input I;
parameter DUTY_CYCLE_CORRECTION = "TRUE";
wire clkin_int;
wire clk0_out, clk180_out, clk270_out, clk2x_out;
wire clk90_out, clkdv_out, locked_out;
CLKDLL clkdll_inst (.CLK0(clk0_out), .CLK180(clk180_out), .CLK270(clk270_out), .CLK2X(clk2x_out), .CLK90(clk90_out), .CLKDV(clkdv_out), .LOCKED(locked_out), .CLKFB(O), .CLKIN(clkin_int), .RST(1'b0));
defparam clkdll_inst.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION;
IBUFG ibufg_inst (.O(clkin_int), .I(I));
BUFG bufg_inst (.O(O), .I(clk0_out));
endmodule |
module IBUFG_LVDCI_33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_IV (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module MUXCY (O, CI, DI, S);
output O;
reg O;
input CI, DI, S;
always @(CI or DI or S)
if (S)
O = CI;
else
O = DI;
endmodule |
module POST_CRC_INTERNAL (
CRCERROR
);
output CRCERROR;
assign CRCERROR = 0;
endmodule |
module AND5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
not N0 (i0_inv, I0);
and A1 (O, i0_inv, I1, I2, I3, I4);
endmodule |
module IBUFG_GTL (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module EFUSE_USR (
EFUSEUSR
);
parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
output [31:0] EFUSEUSR;
assign EFUSEUSR = SIM_EFUSE_VALUE;
endmodule |
module IFDDRRSE (Q0, Q1, C0, C1, CE, D, R, S);
output Q0, Q1;
input C0, C1, CE, D, R, S;
wire d_in;
IBUF I1 (.I(D),
.O(d_in));
FDRSE F0 (.C(C0),
.CE(CE),
.R(R),
.D(d_in),
.S(S),
.Q(Q0));
defparam F0.INIT = 1'b0;
FDRSE F1 (.C(C1),
.CE(CE),
.R(R),
.D(d_in),
.S(S),
.Q(Q1));
defparam F1.INIT = "0";
endmodule |
module NOR4B1 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, I1, I2, I3);
endmodule |
module SRL16 (Q, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
assign Q = data[{A3, A2, A1, A0}];
initial
begin
assign data = INIT;
while (CLK === 1'b1 || CLK===1'bX)
#10;
deassign data;
end
always @(posedge CLK)
begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule |
module NAND4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
nand A1 (O, I0, I1, I2, I3);
endmodule |
module TIMEGRP ();
endmodule |
module IBUF_SSTL3_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module XORCY_L (LO, CI, LI);
output LO;
input CI, LI;
xor X1 (LO, CI, LI);
endmodule |
module OR5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
endmodule |
module XOR3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
xor X1 (O, I0, I1, I2);
endmodule |
module RAM32X4S (O0, O1, O2, O3, A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE);
parameter INIT_00 = 32'h00000000;
parameter INIT_01 = 32'h00000000;
parameter INIT_02 = 32'h00000000;
parameter INIT_03 = 32'h00000000;
output O0, O1, O2, O3;
input A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE;
reg [31:0] mem0;
reg [31:0] mem1;
reg [31:0] mem2;
reg [31:0] mem3;
wire [4:0] adr;
assign adr = {A4, A3, A2, A1, A0};
assign O0 = mem0[adr];
assign O1 = mem1[adr];
assign O2 = mem2[adr];
assign O3 = mem3[adr];
initial begin
mem0 = INIT_00;
mem1 = INIT_01;
mem2 = INIT_02;
mem3 = INIT_03;
end
always @(posedge WCLK)
if (WE == 1'b1) begin
mem0[adr] <= #100 D0;
mem1[adr] <= #100 D1;
mem2[adr] <= #100 D2;
mem3[adr] <= #100 D3;
end
endmodule |
module LUT5_L (LO, I0, I1, I2, I3, I4);
parameter INIT = 32'h00000000;
input I0, I1, I2, I3, I4;
output LO;
reg LO;
reg tmp;
always @( I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4;
if ( tmp == 0 || tmp == 1)
LO = INIT[{I4, I3, I2, I1, I0}];
else
LO = lut4_mux4 (
{ lut6_mux8 ( INIT[31:24], {I2, I1, I0}),
lut6_mux8 ( INIT[23:16], {I2, I1, I0}),
lut6_mux8 ( INIT[15:8], {I2, I1, I0}),
lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3});
end
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) )
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule |
module IBUFG_LVCMOS18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR5B3 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, i2_inv, I3, I4);
endmodule |
module IBUF_HSTL_IV_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM16X8S (O, A0, A1, A2, A3, D, WCLK, WE);
parameter INIT_00 = 16'h0000;
parameter INIT_01 = 16'h0000;
parameter INIT_02 = 16'h0000;
parameter INIT_03 = 16'h0000;
parameter INIT_04 = 16'h0000;
parameter INIT_05 = 16'h0000;
parameter INIT_06 = 16'h0000;
parameter INIT_07 = 16'h0000;
output [7:0] O;
input A0, A1, A2, A3, WCLK, WE;
input [7:0] D;
reg [7:0] mem [15:0];
integer i;
reg test;
wire [3:0] adr;
assign adr = {A3, A2, A1, A0};
assign O = mem[adr];
initial
for (i = 0; i < 16; i=i+1)
mem[i] = {INIT_07[i], INIT_06[i], INIT_05[i], INIT_04[i], INIT_03[i], INIT_02[i],
INIT_01[i], INIT_00[i]};
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
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