module
stringlengths 21
82.9k
|
|---|
module ne_tb;
reg clk;
reg [31:0] ne_a;
reg [31:0] ne_b;
wire [0:0] ne_z;
integer ne_a_file;
integer ne_b_file;
integer ne_z_file;
integer ne_a_count;
integer ne_b_count;
integer ne_z_count;
ne ne1 (clk, ne_a, ne_b, ne_z);
initial
begin
ne_z_file = $fopen("stim/ne_z");
ne_a_file = $fopen("stim/ne_a", "r");
ne_b_file = $fopen("stim/ne_b", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(ne_z_file, "%d", ne_z);
#0 ne_a_count = $fscanf(ne_a_file, "%d\n", ne_a);
#0 ne_b_count = $fscanf(ne_b_file, "%d\n", ne_b);
end
endmodule |
module double_add_tb;
reg clk;
reg [63:0] double_add_a;
reg [63:0] double_add_b;
wire [63:0] double_add_z;
integer double_add_a_file;
integer double_add_b_file;
integer double_add_z_file;
integer double_add_a_count;
integer double_add_b_count;
integer double_add_z_count;
double_add double_add1 (clk, double_add_a, double_add_b, double_add_z);
initial
begin
double_add_z_file = $fopen("stim/double_add_z");
double_add_a_file = $fopen("stim/double_add_a", "r");
double_add_b_file = $fopen("stim/double_add_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_add_z_file, "%d", double_add_z);
#0 double_add_a_count = $fscanf(double_add_a_file, "%d\n", double_add_a);
#0 double_add_b_count = $fscanf(double_add_b_file, "%d\n", double_add_b);
end
endmodule |
module lt_tb;
reg clk;
reg [31:0] lt_a;
reg [31:0] lt_b;
wire [0:0] lt_z;
integer lt_a_file;
integer lt_b_file;
integer lt_z_file;
integer lt_a_count;
integer lt_b_count;
integer lt_z_count;
lt lt1 (clk, lt_a, lt_b, lt_z);
initial
begin
lt_z_file = $fopen("stim/lt_z");
lt_a_file = $fopen("stim/lt_a", "r");
lt_b_file = $fopen("stim/lt_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(lt_z_file, "%d", lt_z);
#0 lt_a_count = $fscanf(lt_a_file, "%d\n", lt_a);
#0 lt_b_count = $fscanf(lt_b_file, "%d\n", lt_b);
end
endmodule |
module double_le_tb;
reg clk;
reg [63:0] double_le_a;
reg [63:0] double_le_b;
wire [0:0] double_le_z;
integer double_le_a_file;
integer double_le_b_file;
integer double_le_z_file;
integer double_le_a_count;
integer double_le_b_count;
integer double_le_z_count;
double_le double_le1 (clk, double_le_a, double_le_b, double_le_z);
initial
begin
double_le_z_file = $fopen("stim/double_le_z");
double_le_a_file = $fopen("stim/double_le_a", "r");
double_le_b_file = $fopen("stim/double_le_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_le_z_file, "%d", double_le_z);
#0 double_le_a_count = $fscanf(double_le_a_file, "%d\n", double_le_a);
#0 double_le_b_count = $fscanf(double_le_b_file, "%d\n", double_le_b);
end
endmodule |
module double_floor_tb;
reg clk;
reg [63:0] double_floor_a;
wire [63:0] double_floor_z;
integer double_floor_a_file;
integer double_floor_z_file;
integer double_floor_a_count;
integer double_floor_z_count;
double_floor double_floor1 (clk, double_floor_a, double_floor_z);
initial
begin
double_floor_z_file = $fopen("stim/double_floor_z");
double_floor_a_file = $fopen("stim/double_floor_a", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_floor_z_file, "%d", double_floor_z);
#0 double_floor_a_count = $fscanf(double_floor_a_file, "%d\n", double_floor_a);
end
endmodule |
module unsigned_int_to_double_tb;
reg clk;
reg [63:0] unsigned_int_to_double_a;
wire [63:0] unsigned_int_to_double_z;
integer unsigned_int_to_double_a_file;
integer unsigned_int_to_double_z_file;
integer unsigned_int_to_double_a_count;
integer unsigned_int_to_double_z_count;
unsigned_int_to_double unsigned_int_to_double1 (clk, unsigned_int_to_double_a, unsigned_int_to_double_z);
initial
begin
unsigned_int_to_double_z_file = $fopen("stim/unsigned_int_to_double_z");
unsigned_int_to_double_a_file = $fopen("stim/unsigned_int_to_double_a", "r");
end
initial
begin
#10060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(unsigned_int_to_double_z_file, "%d", unsigned_int_to_double_z);
#0 unsigned_int_to_double_a_count = $fscanf(unsigned_int_to_double_a_file, "%d\n", unsigned_int_to_double_a);
end
endmodule |
module double_ne_tb;
reg clk;
reg [63:0] double_ne_a;
reg [63:0] double_ne_b;
wire [0:0] double_ne_z;
integer double_ne_a_file;
integer double_ne_b_file;
integer double_ne_z_file;
integer double_ne_a_count;
integer double_ne_b_count;
integer double_ne_z_count;
double_ne double_ne1 (clk, double_ne_a, double_ne_b, double_ne_z);
initial
begin
double_ne_z_file = $fopen("stim/double_ne_z");
double_ne_a_file = $fopen("stim/double_ne_a", "r");
double_ne_b_file = $fopen("stim/double_ne_b", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ne_z_file, "%d", double_ne_z);
#0 double_ne_a_count = $fscanf(double_ne_a_file, "%d\n", double_ne_a);
#0 double_ne_b_count = $fscanf(double_ne_b_file, "%d\n", double_ne_b);
end
endmodule |
module double_max_tb;
reg clk;
reg [63:0] double_max_a;
reg [63:0] double_max_b;
wire [63:0] double_max_z;
integer double_max_a_file;
integer double_max_b_file;
integer double_max_z_file;
integer double_max_a_count;
integer double_max_b_count;
integer double_max_z_count;
double_max double_max1 (clk, double_max_a, double_max_b, double_max_z);
initial
begin
double_max_z_file = $fopen("stim/double_max_z");
double_max_a_file = $fopen("stim/double_max_a", "r");
double_max_b_file = $fopen("stim/double_max_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_max_z_file, "%d", double_max_z);
#0 double_max_a_count = $fscanf(double_max_a_file, "%d\n", double_max_a);
#0 double_max_b_count = $fscanf(double_max_b_file, "%d\n", double_max_b);
end
endmodule |
module double_gt_tb;
reg clk;
reg [63:0] double_gt_a;
reg [63:0] double_gt_b;
wire [0:0] double_gt_z;
integer double_gt_a_file;
integer double_gt_b_file;
integer double_gt_z_file;
integer double_gt_a_count;
integer double_gt_b_count;
integer double_gt_z_count;
double_gt double_gt1 (clk, double_gt_a, double_gt_b, double_gt_z);
initial
begin
double_gt_z_file = $fopen("stim/double_gt_z");
double_gt_a_file = $fopen("stim/double_gt_a", "r");
double_gt_b_file = $fopen("stim/double_gt_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_gt_z_file, "%d", double_gt_z);
#0 double_gt_a_count = $fscanf(double_gt_a_file, "%d\n", double_gt_a);
#0 double_gt_b_count = $fscanf(double_gt_b_file, "%d\n", double_gt_b);
end
endmodule |
module double_eq_tb;
reg clk;
reg [63:0] double_eq_a;
reg [63:0] double_eq_b;
wire [0:0] double_eq_z;
integer double_eq_a_file;
integer double_eq_b_file;
integer double_eq_z_file;
integer double_eq_a_count;
integer double_eq_b_count;
integer double_eq_z_count;
double_eq double_eq1 (clk, double_eq_a, double_eq_b, double_eq_z);
initial
begin
double_eq_z_file = $fopen("stim/double_eq_z");
double_eq_a_file = $fopen("stim/double_eq_a", "r");
double_eq_b_file = $fopen("stim/double_eq_b", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_eq_z_file, "%d", double_eq_z);
#0 double_eq_a_count = $fscanf(double_eq_a_file, "%d\n", double_eq_a);
#0 double_eq_b_count = $fscanf(double_eq_b_file, "%d\n", double_eq_b);
end
endmodule |
module int_to_single_tb;
reg clk;
reg [31:0] int_to_single_a;
wire [31:0] int_to_single_z;
integer int_to_single_a_file;
integer int_to_single_z_file;
integer int_to_single_a_count;
integer int_to_single_z_count;
int_to_single int_to_single1 (clk, int_to_single_a, int_to_single_z);
initial
begin
int_to_single_z_file = $fopen("stim/int_to_single_z");
int_to_single_a_file = $fopen("stim/int_to_single_a", "r");
end
initial
begin
#50060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(int_to_single_z_file, "%d", int_to_single_z);
#0 int_to_single_a_count = $fscanf(int_to_single_a_file, "%d\n", int_to_single_a);
end
endmodule |
module double_to_unsigned_int_tb;
reg clk;
reg [63:0] double_to_unsigned_int_a;
wire [63:0] double_to_unsigned_int_z;
integer double_to_unsigned_int_a_file;
integer double_to_unsigned_int_z_file;
integer double_to_unsigned_int_a_count;
integer double_to_unsigned_int_z_count;
double_to_unsigned_int double_to_unsigned_int1 (clk, double_to_unsigned_int_a, double_to_unsigned_int_z);
initial
begin
double_to_unsigned_int_z_file = $fopen("stim/double_to_unsigned_int_z");
double_to_unsigned_int_a_file = $fopen("stim/double_to_unsigned_int_a", "r");
end
initial
begin
#10020 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_to_unsigned_int_z_file, "%d", double_to_unsigned_int_z);
#0 double_to_unsigned_int_a_count = $fscanf(double_to_unsigned_int_a_file, "%d\n", double_to_unsigned_int_a);
end
endmodule |
module single_to_unsigned_int_tb;
reg clk;
reg [31:0] single_to_unsigned_int_a;
wire [31:0] single_to_unsigned_int_z;
integer single_to_unsigned_int_a_file;
integer single_to_unsigned_int_z_file;
integer single_to_unsigned_int_a_count;
integer single_to_unsigned_int_z_count;
single_to_unsigned_int single_to_unsigned_int1 (clk, single_to_unsigned_int_a, single_to_unsigned_int_z);
initial
begin
single_to_unsigned_int_z_file = $fopen("stim/single_to_unsigned_int_z");
single_to_unsigned_int_a_file = $fopen("stim/single_to_unsigned_int_a", "r");
end
initial
begin
#50020 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_to_unsigned_int_z_file, "%d", single_to_unsigned_int_z);
#0 single_to_unsigned_int_a_count = $fscanf(single_to_unsigned_int_a_file, "%d\n", single_to_unsigned_int_a);
end
endmodule |
module ge_tb;
reg clk;
reg [31:0] ge_a;
reg [31:0] ge_b;
wire [0:0] ge_z;
integer ge_a_file;
integer ge_b_file;
integer ge_z_file;
integer ge_a_count;
integer ge_b_count;
integer ge_z_count;
ge ge1 (clk, ge_a, ge_b, ge_z);
initial
begin
ge_z_file = $fopen("stim/ge_z");
ge_a_file = $fopen("stim/ge_a", "r");
ge_b_file = $fopen("stim/ge_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(ge_z_file, "%d", ge_z);
#0 ge_a_count = $fscanf(ge_a_file, "%d\n", ge_a);
#0 ge_b_count = $fscanf(ge_b_file, "%d\n", ge_b);
end
endmodule |
module single_to_int_tb;
reg clk;
reg [31:0] single_to_int_a;
wire [31:0] single_to_int_z;
integer single_to_int_a_file;
integer single_to_int_z_file;
integer single_to_int_a_count;
integer single_to_int_z_count;
single_to_int single_to_int1 (clk, single_to_int_a, single_to_int_z);
initial
begin
single_to_int_z_file = $fopen("stim/single_to_int_z");
single_to_int_a_file = $fopen("stim/single_to_int_a", "r");
end
initial
begin
#50030 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_to_int_z_file, "%d", single_to_int_z);
#0 single_to_int_a_count = $fscanf(single_to_int_a_file, "%d\n", single_to_int_a);
end
endmodule |
module add_tb;
reg clk;
reg [31:0] add_a;
reg [31:0] add_b;
wire [31:0] add_z;
integer add_a_file;
integer add_b_file;
integer add_z_file;
integer add_a_count;
integer add_b_count;
integer add_z_count;
add add1 (clk, add_a, add_b, add_z);
initial
begin
add_z_file = $fopen("stim/add_z");
add_a_file = $fopen("stim/add_a", "r");
add_b_file = $fopen("stim/add_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(add_z_file, "%d", add_z);
#0 add_a_count = $fscanf(add_a_file, "%d\n", add_a);
#0 add_b_count = $fscanf(add_b_file, "%d\n", add_b);
end
endmodule |
module double_ge_tb;
reg clk;
reg [63:0] double_ge_a;
reg [63:0] double_ge_b;
wire [0:0] double_ge_z;
integer double_ge_a_file;
integer double_ge_b_file;
integer double_ge_z_file;
integer double_ge_a_count;
integer double_ge_b_count;
integer double_ge_z_count;
double_ge double_ge1 (clk, double_ge_a, double_ge_b, double_ge_z);
initial
begin
double_ge_z_file = $fopen("stim/double_ge_z");
double_ge_a_file = $fopen("stim/double_ge_a", "r");
double_ge_b_file = $fopen("stim/double_ge_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ge_z_file, "%d", double_ge_z);
#0 double_ge_a_count = $fscanf(double_ge_a_file, "%d\n", double_ge_a);
#0 double_ge_b_count = $fscanf(double_ge_b_file, "%d\n", double_ge_b);
end
endmodule |
module unsigned_int_to_single_tb;
reg clk;
reg [31:0] unsigned_int_to_single_a;
wire [31:0] unsigned_int_to_single_z;
integer unsigned_int_to_single_a_file;
integer unsigned_int_to_single_z_file;
integer unsigned_int_to_single_a_count;
integer unsigned_int_to_single_z_count;
unsigned_int_to_single unsigned_int_to_single1 (clk, unsigned_int_to_single_a, unsigned_int_to_single_z);
initial
begin
unsigned_int_to_single_z_file = $fopen("stim/unsigned_int_to_single_z");
unsigned_int_to_single_a_file = $fopen("stim/unsigned_int_to_single_a", "r");
end
initial
begin
#50060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(unsigned_int_to_single_z_file, "%d", unsigned_int_to_single_z);
#0 unsigned_int_to_single_a_count = $fscanf(unsigned_int_to_single_a_file, "%d\n", unsigned_int_to_single_a);
end
endmodule |
module single_max_tb;
reg clk;
reg [31:0] single_max_a;
reg [31:0] single_max_b;
wire [31:0] single_max_z;
integer single_max_a_file;
integer single_max_b_file;
integer single_max_z_file;
integer single_max_a_count;
integer single_max_b_count;
integer single_max_z_count;
single_max single_max1 (clk, single_max_a, single_max_b, single_max_z);
initial
begin
single_max_z_file = $fopen("stim/single_max_z");
single_max_a_file = $fopen("stim/single_max_a", "r");
single_max_b_file = $fopen("stim/single_max_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_max_z_file, "%d", single_max_z);
#0 single_max_a_count = $fscanf(single_max_a_file, "%d\n", single_max_a);
#0 single_max_b_count = $fscanf(single_max_b_file, "%d\n", single_max_b);
end
endmodule |
module trunc_tb;
reg clk;
reg [31:0] trunc_a;
wire [31:0] trunc_z;
integer trunc_a_file;
integer trunc_z_file;
integer trunc_a_count;
integer trunc_z_count;
trunc trunc1 (clk, trunc_a, trunc_z);
initial
begin
trunc_z_file = $fopen("stim/trunc_z");
trunc_a_file = $fopen("stim/trunc_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(trunc_z_file, "%d", trunc_z);
#0 trunc_a_count = $fscanf(trunc_a_file, "%d\n", trunc_a);
end
endmodule |
module abs_tb;
reg clk;
reg [31:0] abs_a;
wire [31:0] abs_z;
integer abs_a_file;
integer abs_z_file;
integer abs_a_count;
integer abs_z_count;
abs abs1 (clk, abs_a, abs_z);
initial
begin
abs_z_file = $fopen("stim/abs_z");
abs_a_file = $fopen("stim/abs_a", "r");
end
initial
begin
#50010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(abs_z_file, "%d", abs_z);
#0 abs_a_count = $fscanf(abs_a_file, "%d\n", abs_a);
end
endmodule |
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule |
module to_float(clk, to_float_a, to_float_z);
input clk;
input [31:0] to_float_a;
output [31:0] to_float_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [0:0] s_3;
wire [31:0] s_4;
wire [30:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [30:0] s_9;
wire [31:0] s_10;
wire [31:0] s_11;
wire [31:0] s_12;
wire [30:0] s_13;
wire [31:0] s_14;
wire [31:0] s_15;
wire [8:0] s_16;
wire [8:0] s_17;
wire [7:0] s_18;
wire [22:0] s_19;
wire [23:0] s_20;
wire [23:0] s_21;
wire [23:0] s_22;
wire [24:0] s_23;
wire [24:0] s_24;
wire [24:0] s_25;
wire [24:0] s_26;
wire [23:0] s_27;
wire [31:0] s_28;
wire [31:0] s_29;
wire [31:0] s_30;
wire [31:0] s_31;
wire [31:0] s_32;
wire [31:0] s_33;
wire [5:0] s_34;
wire [5:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [4:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [3:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [2:0] s_44;
wire [0:0] s_45;
wire [0:0] s_46;
wire [1:0] s_47;
wire [0:0] s_48;
wire [0:0] s_49;
wire [0:0] s_50;
wire [1:0] s_51;
wire [3:0] s_52;
wire [7:0] s_53;
wire [15:0] s_54;
wire [0:0] s_55;
wire [0:0] s_56;
wire [0:0] s_57;
wire [0:0] s_58;
wire [0:0] s_59;
wire [0:0] s_60;
wire [0:0] s_61;
wire [1:0] s_62;
wire [0:0] s_63;
wire [0:0] s_64;
wire [0:0] s_65;
wire [1:0] s_66;
wire [0:0] s_67;
wire [0:0] s_68;
wire [0:0] s_69;
wire [0:0] s_70;
wire [0:0] s_71;
wire [0:0] s_72;
wire [1:0] s_73;
wire [0:0] s_74;
wire [0:0] s_75;
wire [0:0] s_76;
wire [0:0] s_77;
wire [0:0] s_78;
wire [0:0] s_79;
wire [2:0] s_80;
wire [0:0] s_81;
wire [0:0] s_82;
wire [1:0] s_83;
wire [0:0] s_84;
wire [0:0] s_85;
wire [0:0] s_86;
wire [1:0] s_87;
wire [3:0] s_88;
wire [0:0] s_89;
wire [0:0] s_90;
wire [0:0] s_91;
wire [0:0] s_92;
wire [0:0] s_93;
wire [0:0] s_94;
wire [0:0] s_95;
wire [1:0] s_96;
wire [0:0] s_97;
wire [0:0] s_98;
wire [0:0] s_99;
wire [1:0] s_100;
wire [0:0] s_101;
wire [0:0] s_102;
wire [0:0] s_103;
wire [0:0] s_104;
wire [0:0] s_105;
wire [0:0] s_106;
wire [1:0] s_107;
wire [0:0] s_108;
wire [0:0] s_109;
wire [0:0] s_110;
wire [0:0] s_111;
wire [0:0] s_112;
wire [2:0] s_113;
wire [0:0] s_114;
wire [0:0] s_115;
wire [1:0] s_116;
wire [1:0] s_117;
wire [1:0] s_118;
wire [0:0] s_119;
wire [3:0] s_120;
wire [0:0] s_121;
wire [0:0] s_122;
wire [2:0] s_123;
wire [0:0] s_124;
wire [0:0] s_125;
wire [1:0] s_126;
wire [0:0] s_127;
wire [0:0] s_128;
wire [0:0] s_129;
wire [1:0] s_130;
wire [3:0] s_131;
wire [7:0] s_132;
wire [0:0] s_133;
wire [0:0] s_134;
wire [0:0] s_135;
wire [0:0] s_136;
wire [0:0] s_137;
wire [0:0] s_138;
wire [0:0] s_139;
wire [1:0] s_140;
wire [0:0] s_141;
wire [0:0] s_142;
wire [0:0] s_143;
wire [1:0] s_144;
wire [0:0] s_145;
wire [0:0] s_146;
wire [0:0] s_147;
wire [0:0] s_148;
wire [0:0] s_149;
wire [0:0] s_150;
wire [1:0] s_151;
wire [0:0] s_152;
wire [0:0] s_153;
wire [0:0] s_154;
wire [0:0] s_155;
wire [0:0] s_156;
wire [0:0] s_157;
wire [2:0] s_158;
wire [0:0] s_159;
wire [0:0] s_160;
wire [1:0] s_161;
wire [0:0] s_162;
wire [0:0] s_163;
wire [0:0] s_164;
wire [1:0] s_165;
wire [3:0] s_166;
wire [0:0] s_167;
wire [0:0] s_168;
wire [0:0] s_169;
wire [0:0] s_170;
wire [0:0] s_171;
wire [0:0] s_172;
wire [0:0] s_173;
wire [1:0] s_174;
wire [0:0] s_175;
wire [0:0] s_176;
wire [0:0] s_177;
wire [1:0] s_178;
wire [0:0] s_179;
wire [0:0] s_180;
wire [0:0] s_181;
wire [0:0] s_182;
wire [0:0] s_183;
wire [0:0] s_184;
wire [1:0] s_185;
wire [0:0] s_186;
wire [0:0] s_187;
wire [0:0] s_188;
wire [0:0] s_189;
wire [0:0] s_190;
wire [2:0] s_191;
wire [0:0] s_192;
wire [0:0] s_193;
wire [1:0] s_194;
wire [1:0] s_195;
wire [1:0] s_196;
wire [3:0] s_197;
wire [0:0] s_198;
wire [0:0] s_199;
wire [2:0] s_200;
wire [2:0] s_201;
wire [2:0] s_202;
wire [0:0] s_203;
wire [4:0] s_204;
wire [0:0] s_205;
wire [0:0] s_206;
wire [3:0] s_207;
wire [0:0] s_208;
wire [0:0] s_209;
wire [2:0] s_210;
wire [0:0] s_211;
wire [0:0] s_212;
wire [1:0] s_213;
wire [0:0] s_214;
wire [0:0] s_215;
wire [0:0] s_216;
wire [1:0] s_217;
wire [3:0] s_218;
wire [7:0] s_219;
wire [15:0] s_220;
wire [0:0] s_221;
wire [0:0] s_222;
wire [0:0] s_223;
wire [0:0] s_224;
wire [0:0] s_225;
wire [0:0] s_226;
wire [0:0] s_227;
wire [1:0] s_228;
wire [0:0] s_229;
wire [0:0] s_230;
wire [0:0] s_231;
wire [1:0] s_232;
wire [0:0] s_233;
wire [0:0] s_234;
wire [0:0] s_235;
wire [0:0] s_236;
wire [0:0] s_237;
wire [0:0] s_238;
wire [1:0] s_239;
wire [0:0] s_240;
wire [0:0] s_241;
wire [0:0] s_242;
wire [0:0] s_243;
wire [0:0] s_244;
wire [0:0] s_245;
wire [2:0] s_246;
wire [0:0] s_247;
wire [0:0] s_248;
wire [1:0] s_249;
wire [0:0] s_250;
wire [0:0] s_251;
wire [0:0] s_252;
wire [1:0] s_253;
wire [3:0] s_254;
wire [0:0] s_255;
wire [0:0] s_256;
wire [0:0] s_257;
wire [0:0] s_258;
wire [0:0] s_259;
wire [0:0] s_260;
wire [0:0] s_261;
wire [1:0] s_262;
wire [0:0] s_263;
wire [0:0] s_264;
wire [0:0] s_265;
wire [1:0] s_266;
wire [0:0] s_267;
wire [0:0] s_268;
wire [0:0] s_269;
wire [0:0] s_270;
wire [0:0] s_271;
wire [0:0] s_272;
wire [1:0] s_273;
wire [0:0] s_274;
wire [0:0] s_275;
wire [0:0] s_276;
wire [0:0] s_277;
wire [0:0] s_278;
wire [2:0] s_279;
wire [0:0] s_280;
wire [0:0] s_281;
wire [1:0] s_282;
wire [1:0] s_283;
wire [1:0] s_284;
wire [0:0] s_285;
wire [3:0] s_286;
wire [0:0] s_287;
wire [0:0] s_288;
wire [2:0] s_289;
wire [0:0] s_290;
wire [0:0] s_291;
wire [1:0] s_292;
wire [0:0] s_293;
wire [0:0] s_294;
wire [0:0] s_295;
wire [1:0] s_296;
wire [3:0] s_297;
wire [7:0] s_298;
wire [0:0] s_299;
wire [0:0] s_300;
wire [0:0] s_301;
wire [0:0] s_302;
wire [0:0] s_303;
wire [0:0] s_304;
wire [0:0] s_305;
wire [1:0] s_306;
wire [0:0] s_307;
wire [0:0] s_308;
wire [0:0] s_309;
wire [1:0] s_310;
wire [0:0] s_311;
wire [0:0] s_312;
wire [0:0] s_313;
wire [0:0] s_314;
wire [0:0] s_315;
wire [0:0] s_316;
wire [1:0] s_317;
wire [0:0] s_318;
wire [0:0] s_319;
wire [0:0] s_320;
wire [0:0] s_321;
wire [0:0] s_322;
wire [0:0] s_323;
wire [2:0] s_324;
wire [0:0] s_325;
wire [0:0] s_326;
wire [1:0] s_327;
wire [0:0] s_328;
wire [0:0] s_329;
wire [0:0] s_330;
wire [1:0] s_331;
wire [3:0] s_332;
wire [0:0] s_333;
wire [0:0] s_334;
wire [0:0] s_335;
wire [0:0] s_336;
wire [0:0] s_337;
wire [0:0] s_338;
wire [0:0] s_339;
wire [1:0] s_340;
wire [0:0] s_341;
wire [0:0] s_342;
wire [0:0] s_343;
wire [1:0] s_344;
wire [0:0] s_345;
wire [0:0] s_346;
wire [0:0] s_347;
wire [0:0] s_348;
wire [0:0] s_349;
wire [0:0] s_350;
wire [1:0] s_351;
wire [0:0] s_352;
wire [0:0] s_353;
wire [0:0] s_354;
wire [0:0] s_355;
wire [0:0] s_356;
wire [2:0] s_357;
wire [0:0] s_358;
wire [0:0] s_359;
wire [1:0] s_360;
wire [1:0] s_361;
wire [1:0] s_362;
wire [3:0] s_363;
wire [0:0] s_364;
wire [0:0] s_365;
wire [2:0] s_366;
wire [2:0] s_367;
wire [2:0] s_368;
wire [4:0] s_369;
wire [0:0] s_370;
wire [0:0] s_371;
wire [3:0] s_372;
wire [3:0] s_373;
wire [3:0] s_374;
wire [0:0] s_375;
wire [23:0] s_376;
wire [0:0] s_377;
wire [0:0] s_378;
wire [0:0] s_379;
wire [0:0] s_380;
wire [0:0] s_381;
wire [0:0] s_382;
wire [0:0] s_383;
wire [0:0] s_384;
wire [0:0] s_385;
wire [5:0] s_386;
wire [0:0] s_387;
wire [0:0] s_388;
wire [0:0] s_389;
wire [23:0] s_390;
wire [0:0] s_391;
wire [31:0] s_392;
wire [8:0] s_393;
wire [0:0] s_394;
wire [7:0] s_395;
wire [7:0] s_396;
wire [7:0] s_397;
wire [7:0] s_398;
wire [7:0] s_399;
wire [7:0] s_400;
wire [6:0] s_401;
wire [22:0] s_402;
wire [0:0] s_403;
wire [0:0] s_404;
wire [7:0] s_405;
wire [0:0] s_406;
wire [0:0] s_407;
wire [0:0] s_408;
wire [23:0] s_409;
wire [0:0] s_410;
wire [0:0] s_411;
assign s_0 = s_411?s_1:s_6;
dq #(32, 5) dq_s_1 (clk, s_1, s_2);
assign s_2 = {s_3,s_5};
assign s_3 = s_4[31];
assign s_4 = to_float_a;
assign s_5 = 31'd2143289344;
assign s_6 = s_410?s_7:s_10;
dq #(32, 5) dq_s_7 (clk, s_7, s_8);
assign s_8 = {s_3,s_9};
assign s_9 = 31'd2139095040;
assign s_10 = s_408?s_11:s_14;
dq #(32, 5) dq_s_11 (clk, s_11, s_12);
assign s_12 = {s_3,s_13};
assign s_13 = 31'd0;
assign s_14 = s_403?s_15:s_392;
assign s_15 = {s_16,s_19};
dq #(9, 5) dq_s_16 (clk, s_16, s_17);
assign s_17 = {s_3,s_18};
assign s_18 = 8'd0;
assign s_19 = s_20[22:0];
dq #(24, 1) dq_s_20 (clk, s_20, s_21);
assign s_21 = s_391?s_22:s_390;
assign s_22 = s_23[24:1];
assign s_23 = s_377?s_24:s_376;
dq #(25, 1) dq_s_24 (clk, s_24, s_25);
assign s_25 = s_26 + s_375;
assign s_26 = s_27;
assign s_27 = s_28[31:8];
dq #(32, 1) dq_s_28 (clk, s_28, s_29);
assign s_29 = s_30 << s_34;
dq #(32, 1) dq_s_30 (clk, s_30, s_31);
dq #(32, 1) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_3?s_33:s_4;
assign s_33 = -s_4;
dq #(6, 1) dq_s_34 (clk, s_34, s_35);
assign s_35 = {s_36,s_369};
assign s_36 = s_37 & s_203;
assign s_37 = s_38[4];
assign s_38 = {s_39,s_197};
assign s_39 = s_40 & s_119;
assign s_40 = s_41[3];
assign s_41 = {s_42,s_113};
assign s_42 = s_43 & s_79;
assign s_43 = s_44[2];
assign s_44 = {s_45,s_73};
assign s_45 = s_46 & s_61;
assign s_46 = s_47[1];
assign s_47 = {s_48,s_57};
assign s_48 = s_49 & s_55;
assign s_49 = ~s_50;
assign s_50 = s_51[1];
assign s_51 = s_52[3:2];
assign s_52 = s_53[7:4];
assign s_53 = s_54[15:8];
assign s_54 = s_31[31:16];
assign s_55 = ~s_56;
assign s_56 = s_51[0];
assign s_57 = s_58 & s_60;
assign s_58 = ~s_59;
assign s_59 = s_51[1];
assign s_60 = s_51[0];
assign s_61 = s_62[1];
assign s_62 = {s_63,s_69};
assign s_63 = s_64 & s_67;
assign s_64 = ~s_65;
assign s_65 = s_66[1];
assign s_66 = s_52[1:0];
assign s_67 = ~s_68;
assign s_68 = s_66[0];
assign s_69 = s_70 & s_72;
assign s_70 = ~s_71;
assign s_71 = s_66[1];
assign s_72 = s_66[0];
assign s_73 = {s_74,s_76};
assign s_74 = s_46 & s_75;
assign s_75 = ~s_61;
assign s_76 = s_46?s_77:s_78;
assign s_77 = s_62[0:0];
assign s_78 = s_47[0:0];
assign s_79 = s_80[2];
assign s_80 = {s_81,s_107};
assign s_81 = s_82 & s_95;
assign s_82 = s_83[1];
assign s_83 = {s_84,s_91};
assign s_84 = s_85 & s_89;
assign s_85 = ~s_86;
assign s_86 = s_87[1];
assign s_87 = s_88[3:2];
assign s_88 = s_53[3:0];
assign s_89 = ~s_90;
assign s_90 = s_87[0];
assign s_91 = s_92 & s_94;
assign s_92 = ~s_93;
assign s_93 = s_87[1];
assign s_94 = s_87[0];
assign s_95 = s_96[1];
assign s_96 = {s_97,s_103};
assign s_97 = s_98 & s_101;
assign s_98 = ~s_99;
assign s_99 = s_100[1];
assign s_100 = s_88[1:0];
assign s_101 = ~s_102;
assign s_102 = s_100[0];
assign s_103 = s_104 & s_106;
assign s_104 = ~s_105;
assign s_105 = s_100[1];
assign s_106 = s_100[0];
assign s_107 = {s_108,s_110};
assign s_108 = s_82 & s_109;
assign s_109 = ~s_95;
assign s_110 = s_82?s_111:s_112;
assign s_111 = s_96[0:0];
assign s_112 = s_83[0:0];
assign s_113 = {s_114,s_116};
assign s_114 = s_43 & s_115;
assign s_115 = ~s_79;
assign s_116 = s_43?s_117:s_118;
assign s_117 = s_80[1:0];
assign s_118 = s_44[1:0];
assign s_119 = s_120[3];
assign s_120 = {s_121,s_191};
assign s_121 = s_122 & s_157;
assign s_122 = s_123[2];
assign s_123 = {s_124,s_151};
assign s_124 = s_125 & s_139;
assign s_125 = s_126[1];
assign s_126 = {s_127,s_135};
assign s_127 = s_128 & s_133;
assign s_128 = ~s_129;
assign s_129 = s_130[1];
assign s_130 = s_131[3:2];
assign s_131 = s_132[7:4];
assign s_132 = s_54[7:0];
assign s_133 = ~s_134;
assign s_134 = s_130[0];
assign s_135 = s_136 & s_138;
assign s_136 = ~s_137;
assign s_137 = s_130[1];
assign s_138 = s_130[0];
assign s_139 = s_140[1];
assign s_140 = {s_141,s_147};
assign s_141 = s_142 & s_145;
assign s_142 = ~s_143;
assign s_143 = s_144[1];
assign s_144 = s_131[1:0];
assign s_145 = ~s_146;
assign s_146 = s_144[0];
assign s_147 = s_148 & s_150;
assign s_148 = ~s_149;
assign s_149 = s_144[1];
assign s_150 = s_144[0];
assign s_151 = {s_152,s_154};
assign s_152 = s_125 & s_153;
assign s_153 = ~s_139;
assign s_154 = s_125?s_155:s_156;
assign s_155 = s_140[0:0];
assign s_156 = s_126[0:0];
assign s_157 = s_158[2];
assign s_158 = {s_159,s_185};
assign s_159 = s_160 & s_173;
assign s_160 = s_161[1];
assign s_161 = {s_162,s_169};
assign s_162 = s_163 & s_167;
assign s_163 = ~s_164;
assign s_164 = s_165[1];
assign s_165 = s_166[3:2];
assign s_166 = s_132[3:0];
assign s_167 = ~s_168;
assign s_168 = s_165[0];
assign s_169 = s_170 & s_172;
assign s_170 = ~s_171;
assign s_171 = s_165[1];
assign s_172 = s_165[0];
assign s_173 = s_174[1];
assign s_174 = {s_175,s_181};
assign s_175 = s_176 & s_179;
assign s_176 = ~s_177;
assign s_177 = s_178[1];
assign s_178 = s_166[1:0];
assign s_179 = ~s_180;
assign s_180 = s_178[0];
assign s_181 = s_182 & s_184;
assign s_182 = ~s_183;
assign s_183 = s_178[1];
assign s_184 = s_178[0];
assign s_185 = {s_186,s_188};
assign s_186 = s_160 & s_187;
assign s_187 = ~s_173;
assign s_188 = s_160?s_189:s_190;
assign s_189 = s_174[0:0];
assign s_190 = s_161[0:0];
assign s_191 = {s_192,s_194};
assign s_192 = s_122 & s_193;
assign s_193 = ~s_157;
assign s_194 = s_122?s_195:s_196;
assign s_195 = s_158[1:0];
assign s_196 = s_123[1:0];
assign s_197 = {s_198,s_200};
assign s_198 = s_40 & s_199;
assign s_199 = ~s_119;
assign s_200 = s_40?s_201:s_202;
assign s_201 = s_120[2:0];
assign s_202 = s_41[2:0];
assign s_203 = s_204[4];
assign s_204 = {s_205,s_363};
assign s_205 = s_206 & s_285;
assign s_206 = s_207[3];
assign s_207 = {s_208,s_279};
assign s_208 = s_209 & s_245;
assign s_209 = s_210[2];
assign s_210 = {s_211,s_239};
assign s_211 = s_212 & s_227;
assign s_212 = s_213[1];
assign s_213 = {s_214,s_223};
assign s_214 = s_215 & s_221;
assign s_215 = ~s_216;
assign s_216 = s_217[1];
assign s_217 = s_218[3:2];
assign s_218 = s_219[7:4];
assign s_219 = s_220[15:8];
assign s_220 = s_31[15:0];
assign s_221 = ~s_222;
assign s_222 = s_217[0];
assign s_223 = s_224 & s_226;
assign s_224 = ~s_225;
assign s_225 = s_217[1];
assign s_226 = s_217[0];
assign s_227 = s_228[1];
assign s_228 = {s_229,s_235};
assign s_229 = s_230 & s_233;
assign s_230 = ~s_231;
assign s_231 = s_232[1];
assign s_232 = s_218[1:0];
assign s_233 = ~s_234;
assign s_234 = s_232[0];
assign s_235 = s_236 & s_238;
assign s_236 = ~s_237;
assign s_237 = s_232[1];
assign s_238 = s_232[0];
assign s_239 = {s_240,s_242};
assign s_240 = s_212 & s_241;
assign s_241 = ~s_227;
assign s_242 = s_212?s_243:s_244;
assign s_243 = s_228[0:0];
assign s_244 = s_213[0:0];
assign s_245 = s_246[2];
assign s_246 = {s_247,s_273};
assign s_247 = s_248 & s_261;
assign s_248 = s_249[1];
assign s_249 = {s_250,s_257};
assign s_250 = s_251 & s_255;
assign s_251 = ~s_252;
assign s_252 = s_253[1];
assign s_253 = s_254[3:2];
assign s_254 = s_219[3:0];
assign s_255 = ~s_256;
assign s_256 = s_253[0];
assign s_257 = s_258 & s_260;
assign s_258 = ~s_259;
assign s_259 = s_253[1];
assign s_260 = s_253[0];
assign s_261 = s_262[1];
assign s_262 = {s_263,s_269};
assign s_263 = s_264 & s_267;
assign s_264 = ~s_265;
assign s_265 = s_266[1];
assign s_266 = s_254[1:0];
assign s_267 = ~s_268;
assign s_268 = s_266[0];
assign s_269 = s_270 & s_272;
assign s_270 = ~s_271;
assign s_271 = s_266[1];
assign s_272 = s_266[0];
assign s_273 = {s_274,s_276};
assign s_274 = s_248 & s_275;
assign s_275 = ~s_261;
assign s_276 = s_248?s_277:s_278;
assign s_277 = s_262[0:0];
assign s_278 = s_249[0:0];
assign s_279 = {s_280,s_282};
assign s_280 = s_209 & s_281;
assign s_281 = ~s_245;
assign s_282 = s_209?s_283:s_284;
assign s_283 = s_246[1:0];
assign s_284 = s_210[1:0];
assign s_285 = s_286[3];
assign s_286 = {s_287,s_357};
assign s_287 = s_288 & s_323;
assign s_288 = s_289[2];
assign s_289 = {s_290,s_317};
assign s_290 = s_291 & s_305;
assign s_291 = s_292[1];
assign s_292 = {s_293,s_301};
assign s_293 = s_294 & s_299;
assign s_294 = ~s_295;
assign s_295 = s_296[1];
assign s_296 = s_297[3:2];
assign s_297 = s_298[7:4];
assign s_298 = s_220[7:0];
assign s_299 = ~s_300;
assign s_300 = s_296[0];
assign s_301 = s_302 & s_304;
assign s_302 = ~s_303;
assign s_303 = s_296[1];
assign s_304 = s_296[0];
assign s_305 = s_306[1];
assign s_306 = {s_307,s_313};
assign s_307 = s_308 & s_311;
assign s_308 = ~s_309;
assign s_309 = s_310[1];
assign s_310 = s_297[1:0];
assign s_311 = ~s_312;
assign s_312 = s_310[0];
assign s_313 = s_314 & s_316;
assign s_314 = ~s_315;
assign s_315 = s_310[1];
assign s_316 = s_310[0];
assign s_317 = {s_318,s_320};
assign s_318 = s_291 & s_319;
assign s_319 = ~s_305;
assign s_320 = s_291?s_321:s_322;
assign s_321 = s_306[0:0];
assign s_322 = s_292[0:0];
assign s_323 = s_324[2];
assign s_324 = {s_325,s_351};
assign s_325 = s_326 & s_339;
assign s_326 = s_327[1];
assign s_327 = {s_328,s_335};
assign s_328 = s_329 & s_333;
assign s_329 = ~s_330;
assign s_330 = s_331[1];
assign s_331 = s_332[3:2];
assign s_332 = s_298[3:0];
assign s_333 = ~s_334;
assign s_334 = s_331[0];
assign s_335 = s_336 & s_338;
assign s_336 = ~s_337;
assign s_337 = s_331[1];
assign s_338 = s_331[0];
assign s_339 = s_340[1];
assign s_340 = {s_341,s_347};
assign s_341 = s_342 & s_345;
assign s_342 = ~s_343;
assign s_343 = s_344[1];
assign s_344 = s_332[1:0];
assign s_345 = ~s_346;
assign s_346 = s_344[0];
assign s_347 = s_348 & s_350;
assign s_348 = ~s_349;
assign s_349 = s_344[1];
assign s_350 = s_344[0];
assign s_351 = {s_352,s_354};
assign s_352 = s_326 & s_353;
assign s_353 = ~s_339;
assign s_354 = s_326?s_355:s_356;
assign s_355 = s_340[0:0];
assign s_356 = s_327[0:0];
assign s_357 = {s_358,s_360};
assign s_358 = s_288 & s_359;
assign s_359 = ~s_323;
assign s_360 = s_288?s_361:s_362;
assign s_361 = s_324[1:0];
assign s_362 = s_289[1:0];
assign s_363 = {s_364,s_366};
assign s_364 = s_206 & s_365;
assign s_365 = ~s_285;
assign s_366 = s_206?s_367:s_368;
assign s_367 = s_286[2:0];
assign s_368 = s_207[2:0];
assign s_369 = {s_370,s_372};
assign s_370 = s_37 & s_371;
assign s_371 = ~s_203;
assign s_372 = s_37?s_373:s_374;
assign s_373 = s_204[3:0];
assign s_374 = s_38[3:0];
assign s_375 = 1'd1;
dq #(24, 1) dq_s_376 (clk, s_376, s_27);
assign s_377 = s_378 & s_380;
dq #(1, 1) dq_s_378 (clk, s_378, s_379);
assign s_379 = s_28[7];
assign s_380 = s_381 | s_388;
assign s_381 = s_382 | s_384;
dq #(1, 1) dq_s_382 (clk, s_382, s_383);
assign s_383 = s_28[6];
dq #(1, 1) dq_s_384 (clk, s_384, s_385);
assign s_385 = s_386 != s_387;
assign s_386 = s_28[5:0];
assign s_387 = 1'd0;
dq #(1, 1) dq_s_388 (clk, s_388, s_389);
assign s_389 = s_27[0];
assign s_390 = s_23[23:0];
assign s_391 = s_23[24];
assign s_392 = {s_393,s_402};
assign s_393 = {s_394,s_395};
dq #(1, 5) dq_s_394 (clk, s_394, s_3);
assign s_395 = s_396 + s_401;
dq #(8, 1) dq_s_396 (clk, s_396, s_397);
assign s_397 = s_398 + s_391;
dq #(8, 2) dq_s_398 (clk, s_398, s_399);
assign s_399 = s_400 - s_34;
assign s_400 = 8'd31;
assign s_401 = 7'd127;
assign s_402 = s_20[22:0];
assign s_403 = s_404 & s_406;
assign s_404 = s_396 == s_405;
assign s_405 = -8'd126;
assign s_406 = ~s_407;
assign s_407 = s_20[23];
assign s_408 = s_20 == s_409;
assign s_409 = 24'd0;
assign s_410 = 1'd0;
assign s_411 = 1'd0;
assign to_float_z = s_0;
endmodule |
module double_trunc_tb;
reg clk;
reg [63:0] double_trunc_a;
wire [63:0] double_trunc_z;
integer double_trunc_a_file;
integer double_trunc_z_file;
integer double_trunc_a_count;
integer double_trunc_z_count;
double_trunc double_trunc1 (clk, double_trunc_a, double_trunc_z);
initial
begin
double_trunc_z_file = $fopen("stim/double_trunc_z");
double_trunc_a_file = $fopen("stim/double_trunc_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_trunc_z_file, "%d", double_trunc_z);
#0 double_trunc_a_count = $fscanf(double_trunc_a_file, "%d\n", double_trunc_a);
end
endmodule |
module double_lt_tb;
reg clk;
reg [63:0] double_lt_a;
reg [63:0] double_lt_b;
wire [0:0] double_lt_z;
integer double_lt_a_file;
integer double_lt_b_file;
integer double_lt_z_file;
integer double_lt_a_count;
integer double_lt_b_count;
integer double_lt_z_count;
double_lt double_lt1 (clk, double_lt_a, double_lt_b, double_lt_z);
initial
begin
double_lt_z_file = $fopen("stim/double_lt_z");
double_lt_a_file = $fopen("stim/double_lt_a", "r");
double_lt_b_file = $fopen("stim/double_lt_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_lt_z_file, "%d", double_lt_z);
#0 double_lt_a_count = $fscanf(double_lt_a_file, "%d\n", double_lt_a);
#0 double_lt_b_count = $fscanf(double_lt_b_file, "%d\n", double_lt_b);
end
endmodule |
module double_to_int_tb;
reg clk;
reg [63:0] double_to_int_a;
wire [63:0] double_to_int_z;
integer double_to_int_a_file;
integer double_to_int_z_file;
integer double_to_int_a_count;
integer double_to_int_z_count;
double_to_int double_to_int1 (clk, double_to_int_a, double_to_int_z);
initial
begin
double_to_int_z_file = $fopen("stim/double_to_int_z");
double_to_int_a_file = $fopen("stim/double_to_int_a", "r");
end
initial
begin
#10030 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_to_int_z_file, "%d", double_to_int_z);
#0 double_to_int_a_count = $fscanf(double_to_int_a_file, "%d\n", double_to_int_a);
end
endmodule |
module div_tb;
reg clk;
reg [31:0] div_a;
reg [31:0] div_b;
wire [31:0] div_z;
integer div_a_file;
integer div_b_file;
integer div_z_file;
integer div_a_count;
integer div_b_count;
integer div_z_count;
div div1 (clk, div_a, div_b, div_z);
initial
begin
div_z_file = $fopen("stim/div_z");
div_a_file = $fopen("stim/div_a", "r");
div_b_file = $fopen("stim/div_b", "r");
end
initial
begin
#50370 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(div_z_file, "%d", div_z);
#0 div_a_count = $fscanf(div_a_file, "%d\n", div_a);
#0 div_b_count = $fscanf(div_b_file, "%d\n", div_b);
end
endmodule |
module double_sqrt_tb;
reg clk;
reg [63:0] double_sqrt_a;
wire [63:0] double_sqrt_z;
integer double_sqrt_a_file;
integer double_sqrt_z_file;
integer double_sqrt_a_count;
integer double_sqrt_z_count;
double_sqrt double_sqrt1 (clk, double_sqrt_a, double_sqrt_z);
initial
begin
double_sqrt_z_file = $fopen("stim/double_sqrt_z");
double_sqrt_a_file = $fopen("stim/double_sqrt_a", "r");
end
initial
begin
#10110 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_sqrt_z_file, "%d", double_sqrt_z);
#0 double_sqrt_a_count = $fscanf(double_sqrt_a_file, "%d\n", double_sqrt_a);
end
endmodule |
module single_min_tb;
reg clk;
reg [31:0] single_min_a;
reg [31:0] single_min_b;
wire [31:0] single_min_z;
integer single_min_a_file;
integer single_min_b_file;
integer single_min_z_file;
integer single_min_a_count;
integer single_min_b_count;
integer single_min_z_count;
single_min single_min1 (clk, single_min_a, single_min_b, single_min_z);
initial
begin
single_min_z_file = $fopen("stim/single_min_z");
single_min_a_file = $fopen("stim/single_min_a", "r");
single_min_b_file = $fopen("stim/single_min_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(single_min_z_file, "%d", single_min_z);
#0 single_min_a_count = $fscanf(single_min_a_file, "%d\n", single_min_a);
#0 single_min_b_count = $fscanf(single_min_b_file, "%d\n", single_min_b);
end
endmodule |
module ceil_tb;
reg clk;
reg [31:0] ceil_a;
wire [31:0] ceil_z;
integer ceil_a_file;
integer ceil_z_file;
integer ceil_a_count;
integer ceil_z_count;
ceil ceil1 (clk, ceil_a, ceil_z);
initial
begin
ceil_z_file = $fopen("stim/ceil_z");
ceil_a_file = $fopen("stim/ceil_a", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(ceil_z_file, "%d", ceil_z);
#0 ceil_a_count = $fscanf(ceil_a_file, "%d\n", ceil_a);
end
endmodule |
module double_abs_tb;
reg clk;
reg [63:0] double_abs_a;
wire [63:0] double_abs_z;
integer double_abs_a_file;
integer double_abs_z_file;
integer double_abs_a_count;
integer double_abs_z_count;
double_abs double_abs1 (clk, double_abs_a, double_abs_z);
initial
begin
double_abs_z_file = $fopen("stim/double_abs_z");
double_abs_a_file = $fopen("stim/double_abs_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_abs_z_file, "%d", double_abs_z);
#0 double_abs_a_count = $fscanf(double_abs_a_file, "%d\n", double_abs_a);
end
endmodule |
module double_mul_tb;
reg clk;
reg [63:0] double_mul_a;
reg [63:0] double_mul_b;
wire [63:0] double_mul_z;
integer double_mul_a_file;
integer double_mul_b_file;
integer double_mul_z_file;
integer double_mul_a_count;
integer double_mul_b_count;
integer double_mul_z_count;
double_mul double_mul1 (clk, double_mul_a, double_mul_b, double_mul_z);
initial
begin
double_mul_z_file = $fopen("stim/double_mul_z");
double_mul_a_file = $fopen("stim/double_mul_a", "r");
double_mul_b_file = $fopen("stim/double_mul_b", "r");
end
initial
begin
#10220 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_mul_z_file, "%d", double_mul_z);
#0 double_mul_a_count = $fscanf(double_mul_a_file, "%d\n", double_mul_a);
#0 double_mul_b_count = $fscanf(double_mul_b_file, "%d\n", double_mul_b);
end
endmodule |
module int_to_double_tb;
reg clk;
reg [63:0] int_to_double_a;
wire [63:0] int_to_double_z;
integer int_to_double_a_file;
integer int_to_double_z_file;
integer int_to_double_a_count;
integer int_to_double_z_count;
int_to_double int_to_double1 (clk, int_to_double_a, int_to_double_z);
initial
begin
int_to_double_z_file = $fopen("stim/int_to_double_z");
int_to_double_a_file = $fopen("stim/int_to_double_a", "r");
end
initial
begin
#10060 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(int_to_double_z_file, "%d", int_to_double_z);
#0 int_to_double_a_count = $fscanf(int_to_double_a_file, "%d\n", int_to_double_a);
end
endmodule |
module mul_tb;
reg clk;
reg [31:0] mul_a;
reg [31:0] mul_b;
wire [31:0] mul_z;
integer mul_a_file;
integer mul_b_file;
integer mul_z_file;
integer mul_a_count;
integer mul_b_count;
integer mul_z_count;
mul mul1 (clk, mul_a, mul_b, mul_z);
initial
begin
mul_z_file = $fopen("stim/mul_z");
mul_a_file = $fopen("stim/mul_a", "r");
mul_b_file = $fopen("stim/mul_b", "r");
end
initial
begin
#50100 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(mul_z_file, "%d", mul_z);
#0 mul_a_count = $fscanf(mul_a_file, "%d\n", mul_a);
#0 mul_b_count = $fscanf(mul_b_file, "%d\n", mul_b);
end
endmodule |
module double_neg_tb;
reg clk;
reg [63:0] double_neg_a;
wire [63:0] double_neg_z;
integer double_neg_a_file;
integer double_neg_z_file;
integer double_neg_a_count;
integer double_neg_z_count;
double_neg double_neg1 (clk, double_neg_a, double_neg_z);
initial
begin
double_neg_z_file = $fopen("stim/double_neg_z");
double_neg_a_file = $fopen("stim/double_neg_a", "r");
end
initial
begin
#10010 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_neg_z_file, "%d", double_neg_z);
#0 double_neg_a_count = $fscanf(double_neg_a_file, "%d\n", double_neg_a);
end
endmodule |
module double_ceil_tb;
reg clk;
reg [63:0] double_ceil_a;
wire [63:0] double_ceil_z;
integer double_ceil_a_file;
integer double_ceil_z_file;
integer double_ceil_a_count;
integer double_ceil_z_count;
double_ceil double_ceil1 (clk, double_ceil_a, double_ceil_z);
initial
begin
double_ceil_z_file = $fopen("stim/double_ceil_z");
double_ceil_a_file = $fopen("stim/double_ceil_a", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_ceil_z_file, "%d", double_ceil_z);
#0 double_ceil_a_count = $fscanf(double_ceil_a_file, "%d\n", double_ceil_a);
end
endmodule |
module double_min_tb;
reg clk;
reg [63:0] double_min_a;
reg [63:0] double_min_b;
wire [63:0] double_min_z;
integer double_min_a_file;
integer double_min_b_file;
integer double_min_z_file;
integer double_min_a_count;
integer double_min_b_count;
integer double_min_z_count;
double_min double_min1 (clk, double_min_a, double_min_b, double_min_z);
initial
begin
double_min_z_file = $fopen("stim/double_min_z");
double_min_a_file = $fopen("stim/double_min_a", "r");
double_min_b_file = $fopen("stim/double_min_b", "r");
end
initial
begin
#10080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_min_z_file, "%d", double_min_z);
#0 double_min_a_count = $fscanf(double_min_a_file, "%d\n", double_min_a);
#0 double_min_b_count = $fscanf(double_min_b_file, "%d\n", double_min_b);
end
endmodule |
module gt_tb;
reg clk;
reg [31:0] gt_a;
reg [31:0] gt_b;
wire [0:0] gt_z;
integer gt_a_file;
integer gt_b_file;
integer gt_z_file;
integer gt_a_count;
integer gt_b_count;
integer gt_z_count;
gt gt1 (clk, gt_a, gt_b, gt_z);
initial
begin
gt_z_file = $fopen("stim/gt_z");
gt_a_file = $fopen("stim/gt_a", "r");
gt_b_file = $fopen("stim/gt_b", "r");
end
initial
begin
#50080 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(gt_z_file, "%d", gt_z);
#0 gt_a_count = $fscanf(gt_a_file, "%d\n", gt_a);
#0 gt_b_count = $fscanf(gt_b_file, "%d\n", gt_b);
end
endmodule |
module double_div_tb;
reg clk;
reg [63:0] double_div_a;
reg [63:0] double_div_b;
wire [63:0] double_div_z;
integer double_div_a_file;
integer double_div_b_file;
integer double_div_z_file;
integer double_div_a_count;
integer double_div_b_count;
integer double_div_z_count;
double_div double_div1 (clk, double_div_a, double_div_b, double_div_z);
initial
begin
double_div_z_file = $fopen("stim/double_div_z");
double_div_a_file = $fopen("stim/double_div_a", "r");
double_div_b_file = $fopen("stim/double_div_b", "r");
end
initial
begin
#10660 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(double_div_z_file, "%d", double_div_z);
#0 double_div_a_count = $fscanf(double_div_a_file, "%d\n", double_div_a);
#0 double_div_b_count = $fscanf(double_div_b_file, "%d\n", double_div_b);
end
endmodule |
module sqrt_tb;
reg clk;
reg [31:0] sqrt_a;
wire [31:0] sqrt_z;
integer sqrt_a_file;
integer sqrt_z_file;
integer sqrt_a_count;
integer sqrt_z_count;
sqrt sqrt1 (clk, sqrt_a, sqrt_z);
initial
begin
sqrt_z_file = $fopen("stim/sqrt_z");
sqrt_a_file = $fopen("stim/sqrt_a", "r");
end
initial
begin
#50110 $finish;
end
initial
begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @ (posedge clk)
begin
$fdisplay(sqrt_z_file, "%d", sqrt_z);
#0 sqrt_a_count = $fscanf(sqrt_a_file, "%d\n", sqrt_a);
end
endmodule |
module to_int(clk, to_int_a, to_int_z);
input clk;
input [31:0] to_int_a;
output [31:0] to_int_z;
wire [31:0] s_0;
wire [31:0] s_1;
wire [31:0] s_2;
wire [31:0] s_3;
wire [31:0] s_4;
wire [31:0] s_5;
wire [31:0] s_6;
wire [31:0] s_7;
wire [31:0] s_8;
wire [31:0] s_9;
wire [23:0] s_10;
wire [0:0] s_11;
wire [0:0] s_12;
wire [0:0] s_13;
wire [0:0] s_14;
wire [7:0] s_15;
wire [7:0] s_16;
wire [31:0] s_17;
wire [6:0] s_18;
wire [7:0] s_19;
wire [22:0] s_20;
wire [7:0] s_21;
wire [7:0] s_22;
wire [7:0] s_23;
wire [7:0] s_24;
wire [7:0] s_25;
wire [7:0] s_26;
wire [0:0] s_27;
wire [31:0] s_28;
wire [0:0] s_29;
wire [0:0] s_30;
wire [0:0] s_31;
wire [0:0] s_32;
wire [0:0] s_33;
wire [0:0] s_34;
wire [0:0] s_35;
wire [0:0] s_36;
wire [0:0] s_37;
wire [0:0] s_38;
wire [0:0] s_39;
wire [0:0] s_40;
wire [7:0] s_41;
wire [0:0] s_42;
wire [0:0] s_43;
wire [7:0] s_44;
wire [0:0] s_45;
wire [22:0] s_46;
wire [0:0] s_47;
wire [0:0] s_48;
wire [7:0] s_49;
wire [0:0] s_50;
wire [22:0] s_51;
assign s_0 = s_37?s_1:s_2;
assign s_1 = 32'd2147483648;
assign s_2 = s_31?s_3:s_4;
assign s_3 = 32'd0;
assign s_4 = s_29?s_5:s_28;
dq #(32, 1) dq_s_5 (clk, s_5, s_6);
assign s_6 = -s_7;
dq #(32, 1) dq_s_7 (clk, s_7, s_8);
assign s_8 = s_9 >> s_22;
assign s_9 = {s_10,s_21};
assign s_10 = {s_11,s_20};
assign s_11 = s_14?s_12:s_13;
assign s_12 = 1'd0;
assign s_13 = 1'd1;
assign s_14 = s_15 == s_19;
assign s_15 = s_16 - s_18;
assign s_16 = s_17[30:23];
assign s_17 = to_int_a;
assign s_18 = 7'd127;
assign s_19 = -8'd127;
assign s_20 = s_17[22:0];
assign s_21 = 8'd0;
assign s_22 = s_23 - s_27;
assign s_23 = s_24 - s_25;
assign s_24 = 8'd32;
assign s_25 = s_14?s_26:s_15;
assign s_26 = -8'd126;
assign s_27 = 1'd1;
dq #(32, 1) dq_s_28 (clk, s_28, s_7);
dq #(1, 2) dq_s_29 (clk, s_29, s_30);
assign s_30 = s_17[31];
dq #(1, 2) dq_s_31 (clk, s_31, s_32);
assign s_32 = s_33 | s_35;
assign s_33 = $signed(s_25) < $signed(s_34);
assign s_34 = 1'd0;
assign s_35 = s_10 == s_36;
assign s_36 = 1'd0;
dq #(1, 2) dq_s_37 (clk, s_37, s_38);
assign s_38 = s_39 | s_47;
assign s_39 = s_40 | s_42;
assign s_40 = $signed(s_25) >= $signed(s_41);
assign s_41 = 8'd31;
assign s_42 = s_43 & s_45;
assign s_43 = s_15 == s_44;
assign s_44 = 8'd128;
assign s_45 = s_20 == s_46;
assign s_46 = 23'd0;
assign s_47 = s_48 & s_50;
assign s_48 = s_15 == s_49;
assign s_49 = 8'd128;
assign s_50 = s_20 != s_51;
assign s_51 = 23'd0;
assign to_int_z = s_0;
endmodule |
module s1238(GND,VDD,CK,G0,G1,G10,G11,G12,G13,G2,G3,G4,G45,G5,G530,G532,G535,
G537,G539,
G542,G546,G547,G548,G549,G550,G551,G552,G6,G7,G8,G9);
input GND,VDD,CK,G0,G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13;
output G549,G550,G551,G552,G542,G546,G547,G548,G530,G532,G535,G537,G45,G539;
wire G29,G502,G30,G503,G31,G504,G32,G505,G33,G506,G34,G507,G35,G508,G36,G509,
G37,G510,G38,G511,G39,G512,G40,G513,G41,G514,G42,G515,G43,G516,G44,G517,
G518,G46,G519,G50,G49,G55,G54,G59,G58,G64,G63,G67,G70,G72,G71,G75,G74,G78,
G77,G87,G86,G90,G89,G98,G97,G99,G123,G122,G125,G132,G135,G134,G140,G160,
G161,G167,G168,G170,G171,G180,G181,G192,G193,G199,G200,G203,G204,G207,G208,
G212,G213,G214,G215,G221,G222,G223,G224,G231,G232,G234,G235,G272,G271,G275,
G274,G282,G281,G475,G57,G476,G477,G276,G478,G279,G479,G194,G480,G179,G481,
G129,G482,G241,G483,G182,G484,G485,G486,G68,G487,G534,G488,G172,G489,G273,
G490,G190,G491,G492,G62,G493,G544,G494,G173,G495,G496,G188,G497,G205,G498,
G195,G499,G280,G500,G501,G156,G520,G521,G522,G524,G525,G526,G527,G528,G529,
G531,G533,G536,G538,G540,G541,G543,G545,G554,G553,G81,G288,G240,G283,G219,
G289,G119,G290,G117,G157,G291,G138,G155,G303,G120,G304,G52,G158,G306,G307,
G104,G308,G151,G311,G178,G312,G315,G250,G251,G317,G159,G245,G321,G322,G105,
G196,G323,G144,G324,G183,G327,G328,G102,G329,G150,G330,G248,G249,G331,G257,
G336,G337,G270,G338,G202,G339,G209,G340,G341,G118,G342,G73,G197,G343,G147,
G344,G111,G189,G346,G82,G347,G348,G349,G108,G351,G169,G352,G164,G353,G92,
G163,G354,G357,G265,G358,G83,G359,G360,G106,G361,G362,G363,G364,G109,G365,
G137,G366,G367,G126,G371,G267,G372,G116,G373,G376,G377,G56,G378,G379,G211,
G380,G93,G382,G100,G383,G131,G385,G386,G85,G387,G388,G114,G392,G393,G127,
G396,G76,G397,G101,G398,G94,G399,G65,G400,G277,G401,G110,G402,G154,G403,
G176,G404,G218,G405,G174,G406,G410,G411,G48,G412,G413,G201,G414,G415,G146,
G142,G165,G416,G61,G417,G418,G60,G422,G80,G423,G128,G424,G177,G425,G426,
G162,G427,G95,G428,G227,G429,G51,G225,G430,G431,G432,G145,G153,G433,G91,
G434,G216,G435,G236,G436,G437,G66,G229,G438,G133,G439,G175,G440,G441,G442,
G121,G443,G47,G444,G445,G53,G446,G79,G447,G448,G139,G449,G88,G451,G187,
G452,G184,G453,G186,G457,G107,G458,G459,G198,G460,G115,G461,G462,G463,G148,
G467,G468,G124,G469,G470,G149,G471,G191,G103,G112,G472,G136,G473,G143,G474,
G242,G141,G152,G244,G261,G269,G166,G284,G285,G286,G287,G292,G293,G294,G295,
G296,G297,G298,G299,G300,G301,G302,G305,G309,G310,G313,G314,G316,G318,G319,
G320,G325,G326,G332,G238,G333,G334,G335,G345,G226,G350,G355,G356,G368,G369,
G239,G370,G374,G375,G381,G384,G389,G390,G391,G220,G394,G395,G407,G408,G409,
G419,G420,G421,G228,G450,G454,G455,G206,G456,G464,G465,G210,G466,G260,G237,
G264,G69,G233,G256,G84,G262,G96,G266,G217,G113,G268,G130,G263,G258,G259,
G252,G253,G185,G230,G243,G246,G523,G254,G255,G278,G247;
dff DFF_0(CK,G29,G502);
dff DFF_1(CK,G30,G503);
dff DFF_2(CK,G31,G504);
dff DFF_3(CK,G32,G505);
dff DFF_4(CK,G33,G506);
dff DFF_5(CK,G34,G507);
dff DFF_6(CK,G35,G508);
dff DFF_7(CK,G36,G509);
dff DFF_8(CK,G37,G510);
dff DFF_9(CK,G38,G511);
dff DFF_10(CK,G39,G512);
dff DFF_11(CK,G40,G513);
dff DFF_12(CK,G41,G514);
dff DFF_13(CK,G42,G515);
dff DFF_14(CK,G43,G516);
dff DFF_15(CK,G44,G517);
dff DFF_16(CK,G45,G518);
dff DFF_17(CK,G46,G519);
not NOT_0(G50,G49);
not NOT_1(G55,G54);
not NOT_2(G59,G58);
not NOT_3(G64,G63);
not NOT_4(G67,G44);
not NOT_5(G70,G43);
not NOT_6(G72,G71);
not NOT_7(G75,G74);
not NOT_8(G78,G77);
not NOT_9(G87,G86);
not NOT_10(G90,G89);
not NOT_11(G98,G97);
not NOT_12(G99,G29);
not NOT_13(G123,G122);
not NOT_14(G125,G40);
not NOT_15(G132,G42);
not NOT_16(G135,G134);
not NOT_17(G140,G33);
not NOT_18(G160,G161);
not NOT_19(G167,G168);
not NOT_20(G170,G171);
not NOT_21(G180,G181);
not NOT_22(G192,G193);
not NOT_23(G199,G200);
not NOT_24(G203,G204);
not NOT_25(G207,G208);
not NOT_26(G212,G213);
not NOT_27(G214,G215);
not NOT_28(G221,G222);
not NOT_29(G223,G224);
not NOT_30(G231,G232);
not NOT_31(G234,G235);
not NOT_32(G272,G271);
not NOT_33(G275,G274);
not NOT_34(G282,G281);
not NOT_35(G475,G57);
not NOT_36(G476,G30);
not NOT_37(G477,G276);
not NOT_38(G478,G279);
not NOT_39(G479,G194);
not NOT_40(G480,G179);
not NOT_41(G481,G129);
not NOT_42(G482,G241);
not NOT_43(G483,G182);
not NOT_44(G484,G30);
not NOT_45(G485,G276);
not NOT_46(G486,G68);
not NOT_47(G487,G534);
not NOT_48(G488,G172);
not NOT_49(G489,G273);
not NOT_50(G490,G190);
not NOT_51(G491,G194);
not NOT_52(G492,G62);
not NOT_53(G493,G544);
not NOT_54(G494,G173);
not NOT_55(G495,G273);
not NOT_56(G496,G188);
not NOT_57(G497,G205);
not NOT_58(G498,G195);
not NOT_59(G499,G280);
not NOT_60(G500,G173);
not NOT_61(G501,G156);
not NOT_62(G520,G0);
not NOT_63(G521,G1);
not NOT_64(G522,G2);
not NOT_65(G524,G3);
not NOT_66(G525,G526);
not NOT_67(G527,G4);
not NOT_68(G528,G5);
not NOT_69(G529,G6);
not NOT_70(G531,G7);
not NOT_71(G533,G8);
not NOT_72(G536,G9);
not NOT_73(G538,G10);
not NOT_74(G540,G11);
not NOT_75(G541,G12);
not NOT_76(G543,G13);
not NOT_77(G545,G544);
not NOT_78(G546,G41);
not NOT_79(G554,G553);
and AND2_0(G81,G288,G240);
and AND2_1(G283,G122,G219);
and AND3_0(G289,G2,G119,G156);
and AND3_1(G290,G117,G135,G157);
and AND2_2(G291,G138,G155);
and AND2_3(G303,G5,G120);
and AND2_4(G304,G52,G158);
and AND2_5(G306,G524,G78);
and AND2_6(G307,G6,G104);
and AND2_7(G308,G5,G151);
and AND3_2(G311,G0,G178,G179);
and AND2_8(G312,G180,G182);
and AND2_9(G315,G250,G251);
and AND2_10(G317,G159,G245);
and AND2_11(G321,G90,G50);
and AND3_3(G322,G522,G105,G196);
and AND2_12(G323,G2,G144);
and AND2_13(G324,G522,G183);
and AND3_4(G327,G4,G39,G157);
and AND3_5(G328,G5,G102,G155);
and AND2_14(G329,G150,G156);
and AND2_15(G330,G248,G249);
and AND2_16(G331,G213,G257);
and AND2_17(G336,G1,G188);
and AND2_18(G337,G270,G167);
and AND2_19(G338,G202,G203);
and AND3_6(G339,G533,G199,G209);
and AND2_20(G340,G8,G270);
and AND2_21(G341,G531,G118);
and AND2_22(G342,G73,G197);
and AND3_7(G343,G2,G528,G147);
and AND3_8(G344,G111,G189,G195);
and AND2_23(G346,G2,G82);
and AND2_24(G347,G135,G178);
and AND3_9(G348,G1,G97,G55);
and AND2_25(G349,G6,G108);
and AND4_0(G351,G524,G169,G221,G234);
and AND4_1(G352,G8,G135,G37,G164);
and AND3_10(G353,G11,G92,G163);
and AND2_26(G354,G0,G214);
and AND2_27(G357,G265,G232);
and AND2_28(G358,G7,G83);
and AND2_29(G359,G6,G31);
and AND2_30(G360,G8,G106);
and AND2_31(G361,G6,G202);
and AND2_32(G362,G129,G77);
and AND2_33(G363,G77,G205);
and AND2_34(G364,G2,G109);
and AND3_11(G365,G282,G137,G156);
and AND2_35(G366,G125,G155);
and AND2_36(G367,G126,G157);
and AND3_12(G371,G161,G168,G267);
and AND3_13(G372,G116,G275,G155);
and AND2_37(G373,G34,G160);
and AND2_38(G376,G533,G75);
and AND2_39(G377,G90,G56);
and AND2_40(G378,G89,G50);
and AND2_41(G379,G9,G211);
and AND2_42(G380,G6,G93);
and AND3_14(G382,G9,G100,G34);
and AND2_43(G383,G131,G155);
and AND3_15(G385,G529,G7,G49);
and AND2_44(G386,G536,G85);
and AND3_16(G387,G6,G274,G75);
and AND2_45(G388,G11,G114);
and AND2_46(G392,G132,G155);
and AND2_47(G393,G127,G34);
and AND3_17(G396,G76,G272,G155);
and AND3_18(G397,G101,G98,G157);
and AND3_19(G398,G94,G156,G158);
and AND3_20(G399,G520,G1,G65);
and AND2_48(G400,G0,G277);
and AND3_21(G401,G2,G110,G155);
and AND2_49(G402,G154,G183);
and AND2_50(G403,G11,G176);
and AND2_51(G404,G4,G218);
and AND3_22(G405,G3,G174,G189);
and AND2_52(G406,G87,G172);
and AND2_53(G410,G1,G205);
and AND2_54(G411,G48,G59);
and AND2_55(G412,G3,G207);
and AND3_23(G413,G8,G197,G201);
and AND2_56(G414,G199,G36);
and AND4_2(G415,G2,G146,G142,G165);
and AND3_24(G416,G61,G167,G169);
and AND3_25(G417,G13,G282,G70);
and AND3_26(G418,G524,G60,G172);
and AND3_27(G422,G0,G80,G155);
and AND2_57(G423,G541,G128);
and AND3_28(G424,G78,G174,G177);
and AND2_58(G425,G146,G176);
and AND3_29(G426,G37,G162,G38);
and AND3_30(G427,G541,G95,G165);
and AND2_59(G428,G212,G227);
and AND2_60(G429,G51,G225);
and AND2_61(G430,G177,G196);
and AND2_62(G431,G524,G67);
and AND2_63(G432,G145,G153);
and AND2_64(G433,G91,G154);
and AND3_31(G434,G165,G216,G231);
and AND2_65(G435,G135,G236);
and AND2_66(G436,G123,G77);
and AND2_67(G437,G66,G229);
and AND3_32(G438,G8,G146,G133);
and AND2_68(G439,G174,G175);
and AND2_69(G440,G38,G234);
and AND2_70(G441,G0,G236);
and AND2_71(G442,G541,G121);
and AND2_72(G443,G47,G162);
and AND3_33(G444,G64,G78,G211);
and AND2_73(G445,G53,G225);
and AND2_74(G446,G524,G79);
and AND2_75(G447,G11,G175);
and AND2_76(G448,G139,G153);
and AND2_77(G449,G88,G154);
and AND3_34(G451,G541,G554,G187);
and AND2_78(G452,G526,G184);
and AND2_79(G453,G545,G186);
and AND3_35(G457,G4,G107,G135);
and AND2_80(G458,G528,G209);
and AND2_81(G459,G77,G198);
and AND3_36(G460,G2,G81,G115);
and AND2_82(G461,G529,G531);
and AND2_83(G462,G192,G538);
and AND2_84(G463,G521,G148);
and AND2_85(G467,G522,G198);
and AND2_86(G468,G527,G124);
and AND2_87(G469,G163,G3);
and AND2_88(G470,G528,G149);
and AND3_37(G471,G191,G103,G112);
and AND3_38(G472,G136,G9,G190);
and AND2_89(G473,G11,G143);
and AND2_90(G474,G242,G77);
and AND2_91(G511,G163,G164);
or OR2_0(G47,G440,G441);
or OR2_1(G60,G413,G414);
or OR2_2(G61,G405,G406);
or OR2_3(G73,G339,G340);
or OR2_4(G79,G444,G445);
or OR2_5(G88,G446,G447);
or OR2_6(G91,G430,G431);
or OR2_7(G92,G351,G352);
or OR3_0(G93,G376,G377,G378);
or OR2_8(G95,G424,G425);
or OR2_9(G105,G321,G273);
or OR2_10(G106,G358,G359);
or OR2_11(G108,G346,G347);
or OR2_12(G110,G399,G400);
or OR2_13(G114,G385,G386);
or OR3_1(G115,G457,G458,G459);
or OR2_14(G118,G337,G338);
or OR2_15(G121,G438,G439);
or OR2_16(G126,G363,G364);
or OR4_0(G128,G415,G416,G417,G418);
or OR2_17(G131,G379,G380);
or OR2_18(G133,G434,G435);
or OR2_19(G137,G348,G349);
or OR2_20(G139,G442,G443);
or OR2_21(G141,G353,G354);
or OR2_22(G142,G403,G404);
or OR2_23(G145,G426,G427);
or OR2_24(G146,G336,G170);
or OR2_25(G147,G341,G342);
or OR2_26(G149,G467,G468);
or OR2_27(G150,G303,G304);
or OR3_2(G152,G306,G307,G308);
or OR2_28(G193,G6,G30);
or OR2_29(G224,G533,G31);
or OR2_30(G242,G469,G470);
or OR2_31(G244,G371,G159);
or OR2_32(G261,G283,G528);
or OR2_33(G269,G362,G529);
or OR2_34(G279,G317,G166);
or OR3_3(G284,G528,G272,G281);
or OR2_35(G285,G5,G479);
or OR2_36(G286,G9,G540);
or OR2_37(G287,G522,G81);
or OR2_38(G288,G1,G528);
or OR2_39(G292,G538,G75);
or OR2_40(G293,G7,G540);
or OR3_4(G294,G1,G117,G281);
or OR2_41(G295,G122,G491);
or OR2_42(G296,G89,G484);
or OR2_43(G297,G64,G274);
or OR2_44(G298,G5,G497);
or OR2_45(G299,G123,G77);
or OR2_46(G300,G87,G97);
or OR2_47(G301,G122,G486);
or OR2_48(G302,G4,G529);
or OR2_49(G305,G524,G55);
or OR2_50(G309,G272,G5);
or OR2_51(G310,G522,G135);
or OR2_52(G313,G521,G475);
or OR2_53(G314,G527,G57);
or OR2_54(G316,G531,G536);
or OR3_5(G318,G6,G8,G232);
or OR2_55(G319,G529,G489);
or OR2_56(G320,G76,G272);
or OR3_6(G325,G7,G536,G222);
or OR2_57(G326,G533,G232);
or OR2_58(G332,G529,G238);
or OR2_59(G333,G528,G6);
or OR2_60(G334,G3,G4);
or OR2_61(G335,G1,G78);
or OR2_62(G345,G529,G226);
or OR2_63(G350,G6,G536);
or OR2_64(G355,G11,G116);
or OR2_65(G356,G6,G476);
or OR2_66(G368,G533,G536);
or OR2_67(G369,G540,G239);
or OR2_68(G370,G538,G11);
or OR2_69(G374,G536,G538);
or OR2_70(G375,G10,G540);
or OR2_71(G381,G7,G71);
or OR2_72(G384,G529,G71);
or OR2_73(G389,G9,G274);
or OR2_74(G390,G89,G50);
or OR2_75(G391,G74,G220);
or OR2_76(G394,G5,G58);
or OR2_77(G395,G4,G134);
or OR2_78(G407,G6,G117);
or OR2_79(G408,G529,G77);
or OR2_80(G409,G528,G55);
or OR2_81(G419,G3,G5);
or OR2_82(G420,G522,G59);
or OR3_7(G421,G521,G2,G228);
or OR2_83(G450,G12,G171);
or OR3_8(G454,G481,G122,G77);
or OR2_84(G455,G78,G206);
or OR2_85(G456,G520,G78);
or OR2_86(G464,G72,G536);
or OR2_87(G465,G524,G210);
or OR2_88(G466,G538,G71);
or OR2_89(G530,G401,G402);
or OR2_90(G532,G422,G423);
or OR2_91(G535,G432,G433);
or OR2_92(G537,G448,G449);
or OR3_9(G539,G451,G452,G453);
or OR2_93(G544,G343,G344);
or OR2_94(G547,G382,G383);
or OR2_95(G548,G392,G393);
or OR4_1(G549,G396,G397,G398,G477);
or OR4_2(G550,G289,G290,G291,G485);
or OR3_10(G551,G327,G328,G329);
or OR3_11(G552,G365,G366,G367);
or OR3_12(G553,G322,G323,G324);
nand NAND3_0(G48,G407,G408,G409);
nand NAND2_0(G49,G9,G538);
nand NAND2_1(G51,G260,G237);
nand NAND3_1(G52,G298,G299,G219);
nand NAND2_2(G53,G264,G237);
nand NAND2_3(G54,G4,G6);
nand NAND2_4(G56,G374,G375);
nand NAND2_5(G57,G0,G2);
nand NAND2_6(G58,G1,G3);
nand NAND2_7(G62,G534,G32);
nand NAND2_8(G63,G75,G8);
nand NAND2_9(G65,G527,G228);
nand NAND2_10(G66,G129,G101);
nand NAND2_11(G68,G302,G528);
nand NAND3_2(G69,G419,G420,G233);
nand NAND2_12(G71,G8,G10);
nand NAND2_13(G74,G9,G11);
nand NAND2_14(G76,G0,G3);
nand NAND2_15(G77,G4,G528);
nand NAND3_3(G80,G421,G226,G256);
nand NAND2_16(G82,G334,G335);
nand NAND2_17(G83,G355,G356);
nand NAND2_18(G84,G369,G370);
nand NAND2_19(G85,G384,G239);
nand NAND2_20(G86,G55,G3);
nand NAND2_21(G89,G531,G8);
nand NAND3_4(G94,G261,G181,G262);
nand NAND2_22(G96,G313,G314);
nand NAND2_23(G97,G2,G5);
nand NAND2_24(G100,G381,G220);
nand NAND2_25(G101,G3,G4);
nand NAND3_5(G102,G320,G266,G210);
nand NAND3_6(G103,G529,G7,G30);
nand NAND3_7(G104,G122,G238,G240);
nand NAND2_26(G107,G456,G1);
nand NAND2_27(G109,G269,G219);
nand NAND2_28(G111,G213,G217);
nand NAND2_29(G112,G8,G31);
nand NAND2_30(G113,G389,G390);
nand NAND2_31(G116,G6,G9);
nand NAND2_32(G117,G2,G4);
nand NAND2_33(G119,G284,G285);
nand NAND2_34(G120,G294,G295);
nand NAND2_35(G122,G522,G3);
nand NAND2_36(G124,G0,G206);
nand NAND2_37(G127,G391,G268);
nand NAND2_38(G129,G527,G5);
nand NAND2_39(G130,G466,G9);
nand NAND2_40(G134,G3,G5);
nand NAND2_41(G136,G222,G224);
nand NAND2_42(G138,G465,G263);
nand NAND3_8(G143,G258,G193,G259);
nand NAND3_9(G144,G215,G252,G253);
nand NAND3_10(G148,G454,G455,G0);
nand NAND2_43(G151,G305,G200);
nand NAND2_44(G159,G6,G155);
nand NAND2_45(G161,G316,G72);
nand NAND2_46(G166,G7,G50);
nand NAND2_47(G168,G75,G221);
nand NAND2_48(G171,G553,G187);
nand NAND2_49(G181,G2,G78);
nand NAND2_50(G185,G525,G184);
nand NAND2_51(G200,G527,G529);
nand NAND2_52(G204,G521,G87);
nand NAND2_53(G206,G287,G524);
nand NAND2_54(G208,G68,G229);
nand NAND2_55(G210,G520,G272);
nand NAND2_56(G213,G64,G275);
nand NAND3_11(G215,G135,G55,G212);
nand NAND2_57(G217,G50,G230);
nand NAND2_58(G219,G524,G55);
nand NAND2_59(G220,G7,G71);
nand NAND2_60(G222,G533,G10);
nand NAND2_61(G226,G527,G59);
nand NAND2_62(G228,G524,G5);
nand NAND2_63(G232,G536,G164);
nand NAND2_64(G233,G522,G135);
nand NAND2_65(G235,G6,G536);
nand NAND3_12(G237,G10,G75,G201);
nand NAND2_66(G238,G2,G524);
nand NAND2_67(G239,G7,G533);
nand NAND2_68(G240,G4,G134);
nand NAND3_13(G243,G368,G275,G34);
nand NAND2_69(G245,G8,G34);
nand NAND2_70(G246,G544,G186);
nand NAND2_71(G248,G529,G36);
nand NAND3_14(G249,G11,G273,G201);
nand NAND2_72(G250,G13,G523);
nand NAND2_73(G251,G543,G32);
nand NAND4_0(G252,G3,G11,G35,G216);
nand NAND2_74(G253,G87,G218);
nand NAND2_75(G254,G1,G152);
nand NAND3_15(G255,G309,G2,G529);
nand NAND2_76(G256,G4,G69);
nand NAND2_77(G257,G538,G230);
nand NAND3_16(G258,G464,G103,G223);
nand NAND2_78(G259,G130,G225);
nand NAND3_17(G260,G528,G529,G191);
nand NAND2_79(G262,G527,G278);
nand NAND2_80(G263,G0,G99);
nand NAND2_81(G264,G227,G241);
nand NAND2_82(G265,G531,G50);
nand NAND2_83(G266,G524,G96);
nand NAND2_84(G267,G536,G84);
nand NAND2_85(G268,G11,G113);
nand NAND2_86(G270,G345,G204);
nand NAND2_87(G271,G1,G4);
nand NAND2_88(G273,G325,G326);
nand NAND2_89(G274,G7,G10);
nand NAND3_18(G276,G3,G543,G140);
nand NAND3_19(G277,G394,G395,G81);
nand NAND3_20(G278,G332,G333,G134);
nand NAND2_90(G280,G46,G247);
nand NAND2_91(G281,G523,G534);
nand NAND2_92(G503,G286,G538);
nand NAND2_93(G504,G292,G293);
nand NAND3_21(G505,G300,G301,G181);
nand NAND2_94(G508,G318,G319);
nand NAND2_95(G510,G350,G235);
nand NAND2_96(G512,G310,G233);
nand NAND3_22(G518,G450,G185,G246);
nand NAND3_23(G523,G254,G255,G208);
nand NAND3_24(G526,G1,G2,G141);
nand NAND3_25(G534,G296,G297,G166);
nand NAND3_26(G542,G243,G244,G279);
nor NOR2_0(G153,G522,G540);
nor NOR2_1(G154,G12,G488);
nor NOR2_2(G155,G13,G480);
nor NOR2_3(G156,G12,G543);
nor NOR2_4(G157,G13,G483);
nor NOR2_5(G158,G521,G281);
nor NOR3_0(G162,G533,G185,G498);
nor NOR2_6(G163,G0,G4);
nor NOR2_7(G164,G531,G10);
nor NOR2_8(G165,G524,G529);
nor NOR2_9(G169,G5,G7);
nor NOR2_10(G172,G2,G171);
nor NOR2_11(G173,G5,G495);
nor NOR2_12(G174,G1,G496);
nor NOR2_13(G175,G86,G500);
nor NOR2_14(G176,G4,G494);
nor NOR2_15(G177,G357,G533);
nor NOR2_16(G178,G521,G4);
nor NOR2_17(G179,G541,G280);
nor NOR2_18(G182,G12,G62);
nor NOR2_19(G183,G330,G3);
nor NOR3_1(G184,G541,G13,G499);
nor NOR2_20(G186,G282,G501);
nor NOR2_21(G187,G13,G492);
nor NOR3_2(G188,G543,G493,G282);
nor NOR2_22(G189,G522,G54);
nor NOR2_23(G190,G7,G11);
nor NOR2_24(G191,G9,G482);
nor NOR2_25(G194,G281,G271);
nor NOR2_26(G195,G521,G134);
nor NOR3_3(G196,G5,G540,G86);
nor NOR2_27(G197,G540,G232);
nor NOR2_28(G198,G520,G3);
nor NOR2_29(G201,G528,G54);
nor NOR2_30(G202,G10,G63);
nor NOR2_31(G205,G529,G122);
nor NOR2_32(G209,G1,G524);
nor NOR2_33(G211,G6,G274);
nor NOR2_34(G216,G4,G5);
nor NOR2_35(G218,G528,G217);
nor NOR2_36(G225,G7,G8);
nor NOR2_37(G227,G5,G200);
nor NOR2_38(G229,G1,G522);
nor NOR2_39(G230,G8,G490);
nor NOR3_4(G236,G536,G274,G54);
nor NOR2_40(G241,G10,G11);
nor NOR4_0(G247,G471,G472,G473,G474);
nor NOR2_41(G502,G436,G437);
nor NOR2_42(G506,G311,G312);
nor NOR3_5(G507,G315,G12,G487);
nor NOR2_43(G509,G331,G5);
nor NOR2_44(G513,G360,G361);
nor NOR3_6(G514,G372,G373,G478);
nor NOR2_45(G515,G387,G388);
nor NOR3_7(G516,G410,G411,G412);
nor NOR2_46(G517,G428,G429);
nor NOR4_1(G519,G460,G461,G462,G463);
endmodule |
module dff(input clk, input d, output reg q);
always@ (posedge clk)
q <= d;
endmodule |
module OPENROAD_CLKGATE (CK, E, GCK);
input CK;
input E;
output GCK;
`ifdef OPENROAD_CLKGATE
sky130_fd_sc_hd__dlclkp_1 latch (.CLK (CK), .GATE(E), .GCLK(GCK));
`else
assign GCK = CK;
`endif
endmodule |
module c499 (N1,N5,N9,N13,N17,N21,N25,N29,N33,N37,
N41,N45,N49,N53,N57,N61,N65,N69,N73,N77,
N81,N85,N89,N93,N97,N101,N105,N109,N113,N117,
N121,N125,N129,N130,N131,N132,N133,N134,N135,N136,
N137,N724,N725,N726,N727,N728,N729,N730,N731,N732,
N733,N734,N735,N736,N737,N738,N739,N740,N741,N742,
N743,N744,N745,N746,N747,N748,N749,N750,N751,N752,
N753,N754,N755);
input N1,N5,N9,N13,N17,N21,N25,N29,N33,N37,
N41,N45,N49,N53,N57,N61,N65,N69,N73,N77,
N81,N85,N89,N93,N97,N101,N105,N109,N113,N117,
N121,N125,N129,N130,N131,N132,N133,N134,N135,N136,
N137;
output N724,N725,N726,N727,N728,N729,N730,N731,N732,N733,
N734,N735,N736,N737,N738,N739,N740,N741,N742,N743,
N744,N745,N746,N747,N748,N749,N750,N751,N752,N753,
N754,N755;
wire N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,
N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,
N270,N271,N272,N273,N274,N275,N276,N277,N278,N279,
N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,
N290,N293,N296,N299,N302,N305,N308,N311,N314,N315,
N316,N317,N318,N319,N320,N321,N338,N339,N340,N341,
N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,
N352,N353,N354,N367,N380,N393,N406,N419,N432,N445,
N554,N555,N556,N557,N558,N559,N560,N561,N562,N563,
N564,N565,N566,N567,N568,N569,N570,N571,N572,N573,
N574,N575,N576,N577,N578,N579,N580,N581,N582,N583,
N584,N585,N586,N587,N588,N589,N590,N591,N592,N593,
N594,N595,N596,N597,N598,N599,N600,N601,N602,N607,
N620,N625,N630,N635,N640,N645,N650,N655,N692,N693,
N694,N695,N696,N697,N698,N699,N700,N701,N702,N703,
N704,N705,N706,N707,N708,N709,N710,N711,N712,N713,
N714,N715,N716,N717,N718,N719,N720,N721,N722,N723;
xor XOR2_1 (N250, N1, N5);
xor XOR2_2 (N251, N9, N13);
xor XOR2_3 (N252, N17, N21);
xor XOR2_4 (N253, N25, N29);
xor XOR2_5 (N254, N33, N37);
xor XOR2_6 (N255, N41, N45);
xor XOR2_7 (N256, N49, N53);
xor XOR2_8 (N257, N57, N61);
xor XOR2_9 (N258, N65, N69);
xor XOR2_10 (N259, N73, N77);
xor XOR2_11 (N260, N81, N85);
xor XOR2_12 (N261, N89, N93);
xor XOR2_13 (N262, N97, N101);
xor XOR2_14 (N263, N105, N109);
xor XOR2_15 (N264, N113, N117);
xor XOR2_16 (N265, N121, N125);
and AND2_17 (N266, N129, N137);
and AND2_18 (N267, N130, N137);
and AND2_19 (N268, N131, N137);
and AND2_20 (N269, N132, N137);
and AND2_21 (N270, N133, N137);
and AND2_22 (N271, N134, N137);
and AND2_23 (N272, N135, N137);
and AND2_24 (N273, N136, N137);
xor XOR2_25 (N274, N1, N17);
xor XOR2_26 (N275, N33, N49);
xor XOR2_27 (N276, N5, N21);
xor XOR2_28 (N277, N37, N53);
xor XOR2_29 (N278, N9, N25);
xor XOR2_30 (N279, N41, N57);
xor XOR2_31 (N280, N13, N29);
xor XOR2_32 (N281, N45, N61);
xor XOR2_33 (N282, N65, N81);
xor XOR2_34 (N283, N97, N113);
xor XOR2_35 (N284, N69, N85);
xor XOR2_36 (N285, N101, N117);
xor XOR2_37 (N286, N73, N89);
xor XOR2_38 (N287, N105, N121);
xor XOR2_39 (N288, N77, N93);
xor XOR2_40 (N289, N109, N125);
xor XOR2_41 (N290, N250, N251);
xor XOR2_42 (N293, N252, N253);
xor XOR2_43 (N296, N254, N255);
xor XOR2_44 (N299, N256, N257);
xor XOR2_45 (N302, N258, N259);
xor XOR2_46 (N305, N260, N261);
xor XOR2_47 (N308, N262, N263);
xor XOR2_48 (N311, N264, N265);
xor XOR2_49 (N314, N274, N275);
xor XOR2_50 (N315, N276, N277);
xor XOR2_51 (N316, N278, N279);
xor XOR2_52 (N317, N280, N281);
xor XOR2_53 (N318, N282, N283);
xor XOR2_54 (N319, N284, N285);
xor XOR2_55 (N320, N286, N287);
xor XOR2_56 (N321, N288, N289);
xor XOR2_57 (N338, N290, N293);
xor XOR2_58 (N339, N296, N299);
xor XOR2_59 (N340, N290, N296);
xor XOR2_60 (N341, N293, N299);
xor XOR2_61 (N342, N302, N305);
xor XOR2_62 (N343, N308, N311);
xor XOR2_63 (N344, N302, N308);
xor XOR2_64 (N345, N305, N311);
xor XOR2_65 (N346, N266, N342);
xor XOR2_66 (N347, N267, N343);
xor XOR2_67 (N348, N268, N344);
xor XOR2_68 (N349, N269, N345);
xor XOR2_69 (N350, N270, N338);
xor XOR2_70 (N351, N271, N339);
xor XOR2_71 (N352, N272, N340);
xor XOR2_72 (N353, N273, N341);
xor XOR2_73 (N354, N314, N346);
xor XOR2_74 (N367, N315, N347);
xor XOR2_75 (N380, N316, N348);
xor XOR2_76 (N393, N317, N349);
xor XOR2_77 (N406, N318, N350);
xor XOR2_78 (N419, N319, N351);
xor XOR2_79 (N432, N320, N352);
xor XOR2_80 (N445, N321, N353);
not NOT1_81 (N554, N354);
not NOT1_82 (N555, N367);
not NOT1_83 (N556, N380);
not NOT1_84 (N557, N354);
not NOT1_85 (N558, N367);
not NOT1_86 (N559, N393);
not NOT1_87 (N560, N354);
not NOT1_88 (N561, N380);
not NOT1_89 (N562, N393);
not NOT1_90 (N563, N367);
not NOT1_91 (N564, N380);
not NOT1_92 (N565, N393);
not NOT1_93 (N566, N419);
not NOT1_94 (N567, N445);
not NOT1_95 (N568, N419);
not NOT1_96 (N569, N432);
not NOT1_97 (N570, N406);
not NOT1_98 (N571, N445);
not NOT1_99 (N572, N406);
not NOT1_100 (N573, N432);
not NOT1_101 (N574, N406);
not NOT1_102 (N575, N419);
not NOT1_103 (N576, N432);
not NOT1_104 (N577, N406);
not NOT1_105 (N578, N419);
not NOT1_106 (N579, N445);
not NOT1_107 (N580, N406);
not NOT1_108 (N581, N432);
not NOT1_109 (N582, N445);
not NOT1_110 (N583, N419);
not NOT1_111 (N584, N432);
not NOT1_112 (N585, N445);
not NOT1_113 (N586, N367);
not NOT1_114 (N587, N393);
not NOT1_115 (N588, N367);
not NOT1_116 (N589, N380);
not NOT1_117 (N590, N354);
not NOT1_118 (N591, N393);
not NOT1_119 (N592, N354);
not NOT1_120 (N593, N380);
and AND4_121 (N594, N554, N555, N556, N393);
and AND4_122 (N595, N557, N558, N380, N559);
and AND4_123 (N596, N560, N367, N561, N562);
and AND4_124 (N597, N354, N563, N564, N565);
and AND4_125 (N598, N574, N575, N576, N445);
and AND4_126 (N599, N577, N578, N432, N579);
and AND4_127 (N600, N580, N419, N581, N582);
and AND4_128 (N601, N406, N583, N584, N585);
or OR4_129 (N602, N594, N595, N596, N597);
or OR4_130 (N607, N598, N599, N600, N601);
and AND5_131 (N620, N406, N566, N432, N567, N602);
and AND5_132 (N625, N406, N568, N569, N445, N602);
and AND5_133 (N630, N570, N419, N432, N571, N602);
and AND5_134 (N635, N572, N419, N573, N445, N602);
and AND5_135 (N640, N354, N586, N380, N587, N607);
and AND5_136 (N645, N354, N588, N589, N393, N607);
and AND5_137 (N650, N590, N367, N380, N591, N607);
and AND5_138 (N655, N592, N367, N593, N393, N607);
and AND2_139 (N692, N354, N620);
and AND2_140 (N693, N367, N620);
and AND2_141 (N694, N380, N620);
and AND2_142 (N695, N393, N620);
and AND2_143 (N696, N354, N625);
and AND2_144 (N697, N367, N625);
and AND2_145 (N698, N380, N625);
and AND2_146 (N699, N393, N625);
and AND2_147 (N700, N354, N630);
and AND2_148 (N701, N367, N630);
and AND2_149 (N702, N380, N630);
and AND2_150 (N703, N393, N630);
and AND2_151 (N704, N354, N635);
and AND2_152 (N705, N367, N635);
and AND2_153 (N706, N380, N635);
and AND2_154 (N707, N393, N635);
and AND2_155 (N708, N406, N640);
and AND2_156 (N709, N419, N640);
and AND2_157 (N710, N432, N640);
and AND2_158 (N711, N445, N640);
and AND2_159 (N712, N406, N645);
and AND2_160 (N713, N419, N645);
and AND2_161 (N714, N432, N645);
and AND2_162 (N715, N445, N645);
and AND2_163 (N716, N406, N650);
and AND2_164 (N717, N419, N650);
and AND2_165 (N718, N432, N650);
and AND2_166 (N719, N445, N650);
and AND2_167 (N720, N406, N655);
and AND2_168 (N721, N419, N655);
and AND2_169 (N722, N432, N655);
and AND2_170 (N723, N445, N655);
xor XOR2_171 (N724, N1, N692);
xor XOR2_172 (N725, N5, N693);
xor XOR2_173 (N726, N9, N694);
xor XOR2_174 (N727, N13, N695);
xor XOR2_175 (N728, N17, N696);
xor XOR2_176 (N729, N21, N697);
xor XOR2_177 (N730, N25, N698);
xor XOR2_178 (N731, N29, N699);
xor XOR2_179 (N732, N33, N700);
xor XOR2_180 (N733, N37, N701);
xor XOR2_181 (N734, N41, N702);
xor XOR2_182 (N735, N45, N703);
xor XOR2_183 (N736, N49, N704);
xor XOR2_184 (N737, N53, N705);
xor XOR2_185 (N738, N57, N706);
xor XOR2_186 (N739, N61, N707);
xor XOR2_187 (N740, N65, N708);
xor XOR2_188 (N741, N69, N709);
xor XOR2_189 (N742, N73, N710);
xor XOR2_190 (N743, N77, N711);
xor XOR2_191 (N744, N81, N712);
xor XOR2_192 (N745, N85, N713);
xor XOR2_193 (N746, N89, N714);
xor XOR2_194 (N747, N93, N715);
xor XOR2_195 (N748, N97, N716);
xor XOR2_196 (N749, N101, N717);
xor XOR2_197 (N750, N105, N718);
xor XOR2_198 (N751, N109, N719);
xor XOR2_199 (N752, N113, N720);
xor XOR2_200 (N753, N117, N721);
xor XOR2_201 (N754, N121, N722);
xor XOR2_202 (N755, N125, N723);
endmodule |
module c432 (N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115,N223,N329,N370,N421,
N430,N431,N432);
input N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115;
output N223,N329,N370,N421,N430,N431,N432;
wire N118,N119,N122,N123,N126,N127,N130,N131,N134,N135,
N138,N139,N142,N143,N146,N147,N150,N151,N154,N157,
N158,N159,N162,N165,N168,N171,N174,N177,N180,N183,
N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N203,N213,N224,N227,
N230,N233,N236,N239,N242,N243,N246,N247,N250,N251,
N254,N255,N256,N257,N258,N259,N260,N263,N264,N267,
N270,N273,N276,N279,N282,N285,N288,N289,N290,N291,
N292,N293,N294,N295,N296,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N319,N330,N331,N332,N333,
N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,
N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N360,N371,N372,N373,N374,N375,
N376,N377,N378,N379,N380,N381,N386,N393,N399,N404,
N407,N411,N414,N415,N416,N417,N418,N419,N420,N422,
N425,N428,N429;
not NOT1_1 (N118, N1);
not NOT1_2 (N119, N4);
not NOT1_3 (N122, N11);
not NOT1_4 (N123, N17);
not NOT1_5 (N126, N24);
not NOT1_6 (N127, N30);
not NOT1_7 (N130, N37);
not NOT1_8 (N131, N43);
not NOT1_9 (N134, N50);
not NOT1_10 (N135, N56);
not NOT1_11 (N138, N63);
not NOT1_12 (N139, N69);
not NOT1_13 (N142, N76);
not NOT1_14 (N143, N82);
not NOT1_15 (N146, N89);
not NOT1_16 (N147, N95);
not NOT1_17 (N150, N102);
not NOT1_18 (N151, N108);
nand NAND2_19 (N154, N118, N4);
nor NOR2_20 (N157, N8, N119);
nor NOR2_21 (N158, N14, N119);
nand NAND2_22 (N159, N122, N17);
nand NAND2_23 (N162, N126, N30);
nand NAND2_24 (N165, N130, N43);
nand NAND2_25 (N168, N134, N56);
nand NAND2_26 (N171, N138, N69);
nand NAND2_27 (N174, N142, N82);
nand NAND2_28 (N177, N146, N95);
nand NAND2_29 (N180, N150, N108);
nor NOR2_30 (N183, N21, N123);
nor NOR2_31 (N184, N27, N123);
nor NOR2_32 (N185, N34, N127);
nor NOR2_33 (N186, N40, N127);
nor NOR2_34 (N187, N47, N131);
nor NOR2_35 (N188, N53, N131);
nor NOR2_36 (N189, N60, N135);
nor NOR2_37 (N190, N66, N135);
nor NOR2_38 (N191, N73, N139);
nor NOR2_39 (N192, N79, N139);
nor NOR2_40 (N193, N86, N143);
nor NOR2_41 (N194, N92, N143);
nor NOR2_42 (N195, N99, N147);
nor NOR2_43 (N196, N105, N147);
nor NOR2_44 (N197, N112, N151);
nor NOR2_45 (N198, N115, N151);
and AND9_46 (N199, N154, N159, N162, N165, N168, N171, N174, N177, N180);
not NOT1_47 (N203, N199);
not NOT1_48 (N213, N199);
not NOT1_49 (N223, N199);
xor XOR2_50 (N224, N203, N154);
xor XOR2_51 (N227, N203, N159);
xor XOR2_52 (N230, N203, N162);
xor XOR2_53 (N233, N203, N165);
xor XOR2_54 (N236, N203, N168);
xor XOR2_55 (N239, N203, N171);
nand NAND2_56 (N242, N1, N213);
xor XOR2_57 (N243, N203, N174);
nand NAND2_58 (N246, N213, N11);
xor XOR2_59 (N247, N203, N177);
nand NAND2_60 (N250, N213, N24);
xor XOR2_61 (N251, N203, N180);
nand NAND2_62 (N254, N213, N37);
nand NAND2_63 (N255, N213, N50);
nand NAND2_64 (N256, N213, N63);
nand NAND2_65 (N257, N213, N76);
nand NAND2_66 (N258, N213, N89);
nand NAND2_67 (N259, N213, N102);
nand NAND2_68 (N260, N224, N157);
nand NAND2_69 (N263, N224, N158);
nand NAND2_70 (N264, N227, N183);
nand NAND2_71 (N267, N230, N185);
nand NAND2_72 (N270, N233, N187);
nand NAND2_73 (N273, N236, N189);
nand NAND2_74 (N276, N239, N191);
nand NAND2_75 (N279, N243, N193);
nand NAND2_76 (N282, N247, N195);
nand NAND2_77 (N285, N251, N197);
nand NAND2_78 (N288, N227, N184);
nand NAND2_79 (N289, N230, N186);
nand NAND2_80 (N290, N233, N188);
nand NAND2_81 (N291, N236, N190);
nand NAND2_82 (N292, N239, N192);
nand NAND2_83 (N293, N243, N194);
nand NAND2_84 (N294, N247, N196);
nand NAND2_85 (N295, N251, N198);
and AND9_86 (N296, N260, N264, N267, N270, N273, N276, N279, N282, N285);
not NOT1_87 (N300, N263);
not NOT1_88 (N301, N288);
not NOT1_89 (N302, N289);
not NOT1_90 (N303, N290);
not NOT1_91 (N304, N291);
not NOT1_92 (N305, N292);
not NOT1_93 (N306, N293);
not NOT1_94 (N307, N294);
not NOT1_95 (N308, N295);
not NOT1_96 (N309, N296);
not NOT1_97 (N319, N296);
not NOT1_98 (N329, N296);
xor XOR2_99 (N330, N309, N260);
xor XOR2_100 (N331, N309, N264);
xor XOR2_101 (N332, N309, N267);
xor XOR2_102 (N333, N309, N270);
nand NAND2_103 (N334, N8, N319);
xor XOR2_104 (N335, N309, N273);
nand NAND2_105 (N336, N319, N21);
xor XOR2_106 (N337, N309, N276);
nand NAND2_107 (N338, N319, N34);
xor XOR2_108 (N339, N309, N279);
nand NAND2_109 (N340, N319, N47);
xor XOR2_110 (N341, N309, N282);
nand NAND2_111 (N342, N319, N60);
xor XOR2_112 (N343, N309, N285);
nand NAND2_113 (N344, N319, N73);
nand NAND2_114 (N345, N319, N86);
nand NAND2_115 (N346, N319, N99);
nand NAND2_116 (N347, N319, N112);
nand NAND2_117 (N348, N330, N300);
nand NAND2_118 (N349, N331, N301);
nand NAND2_119 (N350, N332, N302);
nand NAND2_120 (N351, N333, N303);
nand NAND2_121 (N352, N335, N304);
nand NAND2_122 (N353, N337, N305);
nand NAND2_123 (N354, N339, N306);
nand NAND2_124 (N355, N341, N307);
nand NAND2_125 (N356, N343, N308);
and AND9_126 (N357, N348, N349, N350, N351, N352, N353, N354, N355, N356);
not NOT1_127 (N360, N357);
not NOT1_128 (N370, N357);
nand NAND2_129 (N371, N14, N360);
nand NAND2_130 (N372, N360, N27);
nand NAND2_131 (N373, N360, N40);
nand NAND2_132 (N374, N360, N53);
nand NAND2_133 (N375, N360, N66);
nand NAND2_134 (N376, N360, N79);
nand NAND2_135 (N377, N360, N92);
nand NAND2_136 (N378, N360, N105);
nand NAND2_137 (N379, N360, N115);
nand NAND4_138 (N380, N4, N242, N334, N371);
nand NAND4_139 (N381, N246, N336, N372, N17);
nand NAND4_140 (N386, N250, N338, N373, N30);
nand NAND4_141 (N393, N254, N340, N374, N43);
nand NAND4_142 (N399, N255, N342, N375, N56);
nand NAND4_143 (N404, N256, N344, N376, N69);
nand NAND4_144 (N407, N257, N345, N377, N82);
nand NAND4_145 (N411, N258, N346, N378, N95);
nand NAND4_146 (N414, N259, N347, N379, N108);
not NOT1_147 (N415, N380);
and AND8_148 (N416, N381, N386, N393, N399, N404, N407, N411, N414);
not NOT1_149 (N417, N393);
not NOT1_150 (N418, N404);
not NOT1_151 (N419, N407);
not NOT1_152 (N420, N411);
nor NOR2_153 (N421, N415, N416);
nand NAND2_154 (N422, N386, N417);
nand NAND4_155 (N425, N386, N393, N418, N399);
nand NAND3_156 (N428, N399, N393, N419);
nand NAND4_157 (N429, N386, N393, N407, N420);
nand NAND4_158 (N430, N381, N386, N422, N399);
nand NAND4_159 (N431, N381, N386, N425, N428);
nand NAND4_160 (N432, N381, N422, N425, N429);
endmodule |
module c1908(G1,G10,G11,G12,G13,G14,G15,G16,G17,G18,G1884,G1885,G1886,G1887,
G1888,G1889,G1890,G1891,G1892,G1893,G1894,G1895,G1896,G1897,G1898,G1899,G19,
G1900,G1901,G1902,G1903,G1904,G1905,G1906,G1907,G1908,G2,G20,G21,G22,G23,G24,
G25,G26,G27,G28,G29,G3,G30,G31,G32,G33,G4,G5,G6,G7,G8,G9);
input G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13,G14,G15,G16,G17,G18,G19,G20,
G21,G22,G23,G24,G25,G26,G27,G28,G29,G30,G31,G32,G33;
output G1884,G1885,G1886,G1887,G1888,G1889,G1890,G1891,G1892,G1893,G1894,G1895,
G1896,G1897,G1898,G1899,G1900,G1901,G1902,G1903,G1904,G1905,G1906,G1907,
G1908;
wire G112,G116,G119,G123,G128,G131,G134,G138,G142,G147,G151,G154,G157,G161,
G165,G169,G173,G174,G175,G178,G179,G182,G185,G188,G191,G194,G197,G198,G199,
G202,G205,G212,G219,G222,G225,G228,G235,G238,G241,G248,G253,G260,G265,G268,
G271,G274,G277,G280,G283,G286,G289,G292,G295,G298,G301,G304,G307,G310,G313,
G314,G315,G316,G317,G318,G319,G320,G321,G322,G323,G324,G325,G326,G327,G328,
G329,G330,G331,G332,G333,G334,G335,G338,G341,G344,G347,G350,G353,G356,G359,
G362,G365,G368,G371,G374,G377,G380,G381,G382,G387,G391,G395,G398,G401,G404,
G407,G410,G413,G416,G419,G422,G425,G428,G431,G434,G437,G440,G443,G446,G449,
G452,G455,G458,G461,G464,G467,G470,G473,G476,G479,G482,G485,G488,G491,G494,
G497,G500,G503,G506,G509,G512,G515,G518,G521,G524,G527,G530,G533,G534,G535,
G536,G537,G538,G539,G540,G541,G542,G543,G544,G545,G546,G550,G554,G557,G560,
G561,G562,G563,G564,G565,G566,G567,G568,G569,G570,G573,G582,G585,G586,G589,
G590,G593,G594,G597,G598,G601,G602,G605,G606,G609,G612,G615,G616,G619,G620,
G623,G624,G627,G628,G631,G632,G635,G636,G637,G638,G639,G640,G641,G644,G645,
G648,G649,G650,G651,G652,G653,G654,G655,G656,G657,G660,G663,G666,G669,G672,
G675,G678,G681,G684,G687,G690,G693,G696,G699,G700,G701,G702,G703,G704,G705,
G706,G707,G708,G709,G710,G711,G712,G713,G714,G715,G716,G717,G718,G719,G720,
G721,G722,G723,G724,G725,G726,G727,G728,G729,G730,G731,G734,G735,G738,G755,
G772,G773,G774,G775,G776,G777,G778,G779,G780,G781,G782,G783,G784,G785,G786,
G787,G788,G789,G790,G791,G792,G793,G794,G795,G796,G797,G798,G799,G802,G805,
G806,G807,G808,G809,G810,G813,G816,G819,G822,G825,G828,G831,G834,G835,G836,
G837,G838,G839,G840,G841,G842,G843,G844,G845,G848,G849,G850,G851,G854,G855,
G856,G857,G858,G859,G860,G861,G864,G867,G870,G873,G876,G879,G882,G885,G888,
G891,G894,G895,G896,G897,G898,G901,G904,G905,G906,G907,G908,G909,G910,G911,
G914,G917,G918,G919,G920,G921,G924,G925,G926,G927,G928,G929,G930,G931,G932,
G933,G934,G935,G936,G937,G938,G939,G940,G941,G942,G943,G944,G945,G946,G947,
G948,G951,G952,G953,G956,G959,G962,G963,G964,G965,G966,G967,G968,G969,G970,
G971,G972,G973,G974,G975,G976,G977,G980,G981,G984,G987,G988,G989,G993,G994,
G995,G996,G997,G998,G999,G1000,G1003,G1006,G1009,G1012,G1015,G1019,G1022,
G1023,G1024,G1025,G1028,G1031,G1034,G1035,G1036,G1037,G1038,G1041,G1044,
G1047,G1050,G1053,G1056,G1059,G1062,G1065,G1066,G1067,G1068,G1069,G1072,
G1075,G1078,G1081,G1084,G1087,G1090,G1091,G1092,G1093,G1094,G1095,G1096,
G1097,G1098,G1099,G1100,G1103,G1104,G1107,G1110,G1111,G1112,G1113,G1114,
G1115,G1116,G1117,G1118,G1121,G1124,G1125,G1126,G1129,G1130,G1131,G1132,
G1135,G1138,G1139,G1140,G1143,G1144,G1145,G1148,G1151,G1152,G1153,G1154,
G1155,G1156,G1157,G1158,G1159,G1160,G1163,G1166,G1167,G1168,G1169,G1170,
G1171,G1174,G1175,G1176,G1177,G1178,G1181,G1182,G1185,G1186,G1187,G1188,
G1189,G1192,G1195,G1198,G1199,G1200,G1201,G1202,G1203,G1204,G1205,G1208,
G1209,G1212,G1215,G1216,G1217,G1218,G1219,G1220,G1221,G1222,G1225,G1226,
G1227,G1230,G1233,G1236,G1239,G1240,G1243,G1244,G1245,G1246,G1247,G1250,
G1251,G1252,G1253,G1256,G1259,G1260,G1261,G1262,G1263,G1264,G1265,G1266,
G1267,G1268,G1269,G1270,G1273,G1276,G1279,G1280,G1281,G1282,G1283,G1284,
G1287,G1290,G1293,G1296,G1299,G1302,G1305,G1308,G1309,G1310,G1311,G1312,
G1313,G1316,G1317,G1320,G1321,G1322,G1323,G1324,G1325,G1326,G1327,G1328,
G1329,G1330,G1331,G1332,G1333,G1334,G1335,G1336,G1337,G1338,G1339,G1340,
G1341,G1342,G1343,G1344,G1347,G1350,G1353,G1354,G1355,G1356,G1357,G1358,
G1359,G1362,G1363,G1366,G1369,G1370,G1371,G1374,G1375,G1378,G1381,G1382,
G1383,G1386,G1389,G1392,G1395,G1410,G1420,G1434,G1439,G1442,G1445,G1448,
G1451,G1454,G1457,G1458,G1459,G1460,G1461,G1462,G1463,G1464,G1465,G1466,
G1467,G1468,G1469,G1470,G1471,G1472,G1473,G1474,G1475,G1476,G1479,G1480,
G1483,G1484,G1487,G1488,G1489,G1490,G1493,G1496,G1499,G1502,G1505,G1508,
G1511,G1522,G1538,G1549,G1563,G1576,G1584,G1598,G1607,G1608,G1609,G1624,
G1625,G1642,G1645,G1648,G1651,G1654,G1657,G1660,G1663,G1666,G1669,G1672,
G1675,G1678,G1681,G1684,G1687,G1690,G1693,G1696,G1699,G1702,G1705,G1708,
G1711,G1712,G1713,G1714,G1715,G1716,G1717,G1718,G1719,G1722,G1725,G1728,
G1731,G1734,G1737,G1740,G1743,G1746,G1747,G1748,G1749,G1750,G1751,G1752,
G1753,G1754,G1755,G1756,G1757,G1758,G1759,G1760,G1761,G1762,G1763,G1764,
G1765,G1766,G1767,G1768,G1769,G1770,G1771,G1772,G1773,G1774,G1775,G1776,
G1777,G1778,G1779,G1780,G1781,G1782,G1783,G1784,G1785,G1786,G1787,G1788,
G1791,G1794,G1795,G1796,G1797,G1798,G1799,G1800,G1801,G1802,G1803,G1806,
G1809,G1810,G1817,G1818,G1819,G1820,G1821,G1822,G1825,G1828,G1831,G1834,
G1837,G1838,G1839,G1842,G1845,G1848,G1849,G1850,G1851,G1852,G1853,G1854,
G1855,G1856,G1857,G1858,G1859,G1860,G1861,G1862,G1863,G1864,G1865,G1866,
G1867,G1868,G1869,G1870,G1871,G1872,G1873,G1874,G1875,G1876,G1877,G1880,
G1881,G1882,G1883;
not NOT_0(G112,G1);
not NOT_1(G116,G2);
not NOT_2(G119,G3);
not NOT_3(G123,G4);
not NOT_4(G128,G5);
not NOT_5(G131,G6);
not NOT_6(G134,G7);
not NOT_7(G138,G8);
not NOT_8(G142,G9);
not NOT_9(G147,G10);
not NOT_10(G151,G11);
not NOT_11(G154,G12);
not NOT_12(G157,G13);
not NOT_13(G161,G14);
not NOT_14(G165,G15);
not NOT_15(G169,G16);
nand NAND2_0(G173,G21,G29);
nand NAND2_1(G174,G22,G30);
not NOT_16(G175,G24);
not NOT_17(G178,G24);
not NOT_18(G179,G23);
not NOT_19(G182,G23);
not NOT_20(G185,G25);
not NOT_21(G188,G26);
not NOT_22(G191,G27);
not NOT_23(G194,G28);
not NOT_24(G197,G33);
not NOT_25(G198,G33);
not NOT_26(G199,G29);
not NOT_27(G202,G30);
not NOT_28(G205,G31);
not NOT_29(G212,G31);
not NOT_30(G219,G31);
not NOT_31(G222,G31);
not NOT_32(G225,G32);
not NOT_33(G228,G32);
not NOT_34(G235,G32);
not NOT_35(G238,G33);
not NOT_36(G241,G33);
not NOT_37(G248,G33);
not NOT_38(G253,G33);
not NOT_39(G260,G33);
not NOT_40(G265,G1);
not NOT_41(G268,G2);
not NOT_42(G271,G3);
not NOT_43(G274,G4);
not NOT_44(G277,G5);
not NOT_45(G280,G6);
not NOT_46(G283,G7);
not NOT_47(G286,G8);
not NOT_48(G289,G9);
not NOT_49(G292,G10);
not NOT_50(G295,G11);
not NOT_51(G298,G12);
not NOT_52(G301,G13);
not NOT_53(G304,G14);
not NOT_54(G307,G15);
not NOT_55(G310,G16);
not NOT_56(G313,G265);
not NOT_57(G314,G268);
not NOT_58(G315,G271);
not NOT_59(G316,G274);
not NOT_60(G317,G277);
not NOT_61(G318,G280);
not NOT_62(G319,G283);
not NOT_63(G320,G286);
not NOT_64(G321,G289);
not NOT_65(G322,G292);
not NOT_66(G323,G295);
not NOT_67(G324,G298);
not NOT_68(G325,G301);
not NOT_69(G326,G304);
not NOT_70(G327,G307);
not NOT_71(G328,G310);
nand NAND2_2(G329,G228,G253);
nand NAND2_3(G330,G228,G253);
nand NAND2_4(G331,G228,G253);
nand NAND2_5(G332,G228,G253);
nand NAND2_6(G333,G228,G253);
nand NAND2_7(G334,G228,G253);
not NOT_72(G335,G112);
not NOT_73(G338,G116);
not NOT_74(G341,G128);
not NOT_75(G344,G131);
not NOT_76(G347,G147);
not NOT_77(G350,G165);
and AND2_0(G353,G21,G241);
not NOT_78(G356,G142);
not NOT_79(G359,G151);
not NOT_80(G362,G154);
and AND2_1(G365,G22,G241);
not NOT_81(G368,G161);
and AND3_0(G371,G17,G175,G241);
not NOT_82(G374,G169);
not NOT_83(G377,G161);
nand NAND2_8(G380,G248,G199);
nand NAND2_9(G381,G248,G202);
nand NAND2_10(G382,G182,G24);
nand NAND2_11(G387,G182,G222);
nand NAND2_12(G391,G178,G222);
not NOT_84(G395,G123);
not NOT_85(G398,G138);
not NOT_86(G401,G142);
not NOT_87(G404,G161);
not NOT_88(G407,G112);
not NOT_89(G410,G112);
not NOT_90(G413,G116);
not NOT_91(G416,G151);
not NOT_92(G419,G119);
and AND3_1(G422,G19,G179,G241);
not NOT_93(G425,G154);
not NOT_94(G428,G123);
not NOT_95(G431,G157);
and AND3_2(G434,G20,G179,G241);
not NOT_96(G437,G185);
not NOT_97(G440,G185);
not NOT_98(G443,G188);
not NOT_99(G446,G188);
not NOT_100(G449,G191);
not NOT_101(G452,G191);
not NOT_102(G455,G194);
not NOT_103(G458,G194);
and AND2_2(G461,G173,G238);
and AND2_3(G464,G174,G238);
not NOT_104(G467,G119);
not NOT_105(G470,G119);
not NOT_106(G473,G134);
not NOT_107(G476,G134);
not NOT_108(G479,G169);
not NOT_109(G482,G169);
not NOT_110(G485,G157);
not NOT_111(G488,G157);
not NOT_112(G491,G123);
not NOT_113(G494,G123);
not NOT_114(G497,G128);
not NOT_115(G500,G138);
and AND3_3(G503,G18,G175,G241);
not NOT_116(G506,G165);
not NOT_117(G509,G142);
not NOT_118(G512,G142);
not NOT_119(G515,G131);
not NOT_120(G518,G138);
not NOT_121(G521,G147);
not NOT_122(G524,G165);
not NOT_123(G527,G134);
not NOT_124(G530,G147);
not NOT_125(G533,G461);
not NOT_126(G534,G464);
not NOT_127(G535,G395);
not NOT_128(G536,G398);
not NOT_129(G537,G401);
not NOT_130(G538,G404);
not NOT_131(G539,G410);
not NOT_132(G540,G422);
not NOT_133(G541,G428);
not NOT_134(G542,G431);
not NOT_135(G543,G434);
and AND2_4(G544,G17,G391);
and AND2_5(G545,G19,G387);
nand NAND2_13(G546,G18,G391);
nand NAND2_14(G550,G20,G387);
nand NAND2_15(G554,G17,G391);
nand NAND2_16(G557,G19,G387);
not NOT_136(G560,G440);
not NOT_137(G561,G437);
not NOT_138(G562,G446);
not NOT_139(G563,G443);
not NOT_140(G564,G452);
not NOT_141(G565,G449);
not NOT_142(G566,G458);
not NOT_143(G567,G455);
nand NAND4_0(G568,G199,G219,G248,G382);
nand NAND4_1(G569,G202,G219,G248,G382);
nand NAND3_0(G570,G225,G260,G382);
and AND3_4(G573,G225,G260,G382);
not NOT_144(G582,G335);
not NOT_145(G585,G467);
not NOT_146(G586,G335);
not NOT_147(G589,G470);
not NOT_148(G590,G341);
not NOT_149(G593,G473);
not NOT_150(G594,G341);
not NOT_151(G597,G476);
not NOT_152(G598,G347);
not NOT_153(G601,G479);
not NOT_154(G602,G347);
not NOT_155(G605,G482);
not NOT_156(G606,G353);
not NOT_157(G609,G353);
not NOT_158(G612,G359);
not NOT_159(G615,G485);
not NOT_160(G616,G359);
not NOT_161(G619,G488);
not NOT_162(G620,G365);
not NOT_163(G623,G491);
not NOT_164(G624,G365);
not NOT_165(G627,G494);
not NOT_166(G628,G371);
not NOT_167(G631,G407);
not NOT_168(G632,G371);
not NOT_169(G635,G497);
not NOT_170(G636,G500);
not NOT_171(G637,G413);
not NOT_172(G638,G503);
not NOT_173(G639,G506);
not NOT_174(G640,G416);
not NOT_175(G641,G374);
not NOT_176(G644,G509);
not NOT_177(G645,G374);
not NOT_178(G648,G512);
not NOT_179(G649,G515);
not NOT_180(G650,G518);
not NOT_181(G651,G419);
not NOT_182(G652,G521);
not NOT_183(G653,G524);
not NOT_184(G654,G425);
not NOT_185(G655,G527);
not NOT_186(G656,G530);
not NOT_187(G657,G338);
not NOT_188(G660,G338);
not NOT_189(G663,G344);
not NOT_190(G666,G344);
not NOT_191(G669,G350);
not NOT_192(G672,G350);
not NOT_193(G675,G356);
not NOT_194(G678,G356);
not NOT_195(G681,G362);
not NOT_196(G684,G362);
not NOT_197(G687,G368);
not NOT_198(G690,G368);
not NOT_199(G693,G377);
not NOT_200(G696,G377);
nand NAND2_17(G699,G398,G535);
nand NAND2_18(G700,G395,G536);
nand NAND2_19(G701,G404,G537);
nand NAND2_20(G702,G401,G538);
nand NAND2_21(G703,G434,G542);
nand NAND2_22(G704,G431,G543);
nand NAND2_23(G705,G500,G635);
nand NAND2_24(G706,G497,G636);
nand NAND2_25(G707,G506,G638);
nand NAND2_26(G708,G503,G639);
nand NAND2_27(G709,G518,G649);
nand NAND2_28(G710,G515,G650);
nand NAND2_29(G711,G524,G652);
nand NAND2_30(G712,G521,G653);
nand NAND2_31(G713,G530,G655);
nand NAND2_32(G714,G527,G656);
not NOT_201(G715,G586);
not NOT_202(G716,G582);
nand NAND2_33(G717,G699,G700);
not NOT_203(G718,G590);
not NOT_204(G719,G594);
not NOT_205(G720,G602);
not NOT_206(G721,G598);
not NOT_207(G722,G609);
not NOT_208(G723,G616);
not NOT_209(G724,G624);
nand NAND2_34(G725,G701,G702);
not NOT_210(G726,G632);
nand NAND2_35(G727,G632,G539);
not NOT_211(G728,G645);
nand NAND2_36(G729,G703,G704);
not NOT_212(G730,G546);
not NOT_213(G731,G546);
not NOT_214(G734,G550);
not NOT_215(G735,G550);
nand NAND2_37(G738,G568,G570);
nand NAND2_38(G755,G569,G570);
not NOT_216(G772,G657);
nand NAND2_39(G773,G657,G585);
not NOT_217(G774,G660);
nand NAND2_40(G775,G660,G589);
not NOT_218(G776,G663);
nand NAND2_41(G777,G663,G593);
not NOT_219(G778,G666);
nand NAND2_42(G779,G666,G597);
not NOT_220(G780,G669);
nand NAND2_43(G781,G669,G601);
not NOT_221(G782,G672);
nand NAND2_44(G783,G672,G605);
not NOT_222(G784,G675);
not NOT_223(G785,G606);
not NOT_224(G786,G678);
not NOT_225(G787,G681);
nand NAND2_45(G788,G681,G615);
not NOT_226(G789,G612);
not NOT_227(G790,G684);
nand NAND2_46(G791,G684,G619);
not NOT_228(G792,G687);
nand NAND2_47(G793,G687,G623);
not NOT_229(G794,G620);
not NOT_230(G795,G690);
nand NAND2_48(G796,G690,G627);
not NOT_231(G797,G628);
nand NAND2_49(G798,G628,G631);
nand NAND2_50(G799,G705,G706);
nand NAND2_51(G802,G707,G708);
not NOT_232(G805,G693);
nand NAND2_52(G806,G693,G644);
not NOT_233(G807,G641);
not NOT_234(G808,G696);
nand NAND2_53(G809,G696,G648);
nand NAND2_54(G810,G709,G710);
nand NAND2_55(G813,G711,G712);
nand NAND2_56(G816,G713,G714);
not NOT_235(G819,G554);
not NOT_236(G822,G554);
not NOT_237(G825,G557);
not NOT_238(G828,G557);
not NOT_239(G831,G717);
nand NAND2_57(G834,G410,G726);
nand NAND2_58(G835,G467,G772);
nand NAND2_59(G836,G470,G774);
nand NAND2_60(G837,G473,G776);
nand NAND2_61(G838,G476,G778);
nand NAND2_62(G839,G479,G780);
nand NAND2_63(G840,G482,G782);
nand NAND2_64(G841,G485,G787);
nand NAND2_65(G842,G488,G790);
nand NAND2_66(G843,G491,G792);
nand NAND2_67(G844,G494,G795);
not NOT_240(G845,G725);
nand NAND2_68(G848,G407,G797);
nand NAND2_69(G849,G509,G805);
nand NAND2_70(G850,G512,G808);
not NOT_241(G851,G729);
nand NAND2_71(G854,G834,G727);
nand NAND2_72(G855,G816,G541);
not NOT_242(G856,G816);
not NOT_243(G857,G822);
not NOT_244(G858,G819);
not NOT_245(G859,G828);
not NOT_246(G860,G825);
nand NAND2_73(G861,G835,G773);
nand NAND2_74(G864,G836,G775);
nand NAND2_75(G867,G837,G777);
nand NAND2_76(G870,G838,G779);
nand NAND2_77(G873,G839,G781);
nand NAND2_78(G876,G840,G783);
nand NAND2_79(G879,G841,G788);
nand NAND2_80(G882,G842,G791);
nand NAND2_81(G885,G843,G793);
nand NAND2_82(G888,G844,G796);
nand NAND2_83(G891,G848,G798);
not NOT_247(G894,G799);
nand NAND2_84(G895,G799,G637);
not NOT_248(G896,G802);
nand NAND2_85(G897,G802,G640);
nand NAND2_86(G898,G849,G806);
nand NAND2_87(G901,G850,G809);
not NOT_249(G904,G810);
nand NAND2_88(G905,G810,G651);
not NOT_250(G906,G813);
nand NAND2_89(G907,G813,G654);
not NOT_251(G908,G845);
nand NAND2_90(G909,G428,G856);
not NOT_252(G910,G851);
not NOT_253(G911,G831);
not NOT_254(G914,G831);
nand NAND2_91(G917,G413,G894);
nand NAND2_92(G918,G416,G896);
nand NAND2_93(G919,G419,G904);
nand NAND2_94(G920,G425,G906);
not NOT_255(G921,G854);
nand NAND2_95(G924,G864,G715);
not NOT_256(G925,G864);
nand NAND2_96(G926,G861,G716);
not NOT_257(G927,G861);
nand NAND2_97(G928,G867,G718);
not NOT_258(G929,G867);
nand NAND2_98(G930,G870,G719);
not NOT_259(G931,G870);
nand NAND2_99(G932,G876,G720);
not NOT_260(G933,G876);
nand NAND2_100(G934,G873,G721);
not NOT_261(G935,G873);
nand NAND2_101(G936,G882,G723);
not NOT_262(G937,G882);
nand NAND2_102(G938,G888,G724);
not NOT_263(G939,G888);
not NOT_264(G940,G891);
nand NAND2_103(G941,G901,G728);
not NOT_265(G942,G901);
nand NAND2_104(G943,G855,G909);
not NOT_266(G944,G879);
nand NAND2_105(G945,G879,G789);
not NOT_267(G946,G885);
nand NAND2_106(G947,G885,G794);
nand NAND2_107(G948,G895,G917);
not NOT_268(G951,G898);
nand NAND2_108(G952,G898,G807);
nand NAND2_109(G953,G897,G918);
nand NAND2_110(G956,G907,G920);
nand NAND2_111(G959,G905,G919);
nand NAND2_112(G962,G586,G925);
nand NAND2_113(G963,G582,G927);
nand NAND2_114(G964,G590,G929);
not NOT_269(G965,G914);
not NOT_270(G966,G911);
nand NAND2_115(G967,G594,G931);
nand NAND2_116(G968,G602,G933);
nand NAND2_117(G969,G598,G935);
nand NAND2_118(G970,G616,G937);
nand NAND2_119(G971,G624,G939);
nand NAND2_120(G972,G645,G942);
not NOT_271(G973,G921);
nand NAND2_121(G974,G612,G944);
nand NAND2_122(G975,G620,G946);
nand NAND2_123(G976,G641,G951);
not NOT_272(G977,G943);
nand NAND2_124(G980,G924,G962);
nand NAND2_125(G981,G926,G963);
nand NAND2_126(G984,G928,G964);
nand NAND2_127(G987,G930,G967);
nand NAND2_128(G988,G932,G968);
nand NAND2_129(G989,G934,G969);
nand NAND2_130(G993,G936,G970);
nand NAND2_131(G994,G938,G971);
not NOT_273(G995,G948);
nand NAND2_132(G996,G941,G972);
not NOT_274(G997,G953);
not NOT_275(G998,G956);
not NOT_276(G999,G959);
nand NAND2_133(G1000,G947,G975);
nand NAND2_134(G1003,G945,G974);
nand NAND2_135(G1006,G952,G976);
not NOT_277(G1009,G980);
not NOT_278(G1012,G988);
not NOT_279(G1015,G993);
not NOT_280(G1019,G987);
nand NAND2_136(G1022,G959,G998);
nand NAND2_137(G1023,G956,G999);
not NOT_281(G1024,G977);
not NOT_282(G1025,G994);
not NOT_283(G1028,G996);
not NOT_284(G1031,G989);
not NOT_285(G1034,G1000);
not NOT_286(G1035,G1003);
nand NAND2_138(G1036,G1006,G997);
not NOT_287(G1037,G1006);
nand NAND2_139(G1038,G1022,G1023);
not NOT_288(G1041,G984);
not NOT_289(G1044,G984);
not NOT_290(G1047,G989);
not NOT_291(G1050,G989);
not NOT_292(G1053,G981);
not NOT_293(G1056,G981);
not NOT_294(G1059,G1015);
not NOT_295(G1062,G1012);
not NOT_296(G1065,G1025);
nand NAND2_140(G1066,G953,G1037);
nand NAND2_141(G1067,G1028,G1024);
not NOT_297(G1068,G1028);
not NOT_298(G1069,G1019);
not NOT_299(G1072,G1019);
not NOT_300(G1075,G1009);
not NOT_301(G1078,G1009);
not NOT_302(G1081,G1012);
not NOT_303(G1084,G1015);
not NOT_304(G1087,G1015);
nand NAND2_142(G1090,G1038,G540);
not NOT_305(G1091,G1038);
not NOT_306(G1092,G1041);
not NOT_307(G1093,G1044);
nand NAND2_143(G1094,G1047,G784);
not NOT_308(G1095,G1047);
nand NAND2_144(G1096,G1050,G786);
not NOT_309(G1097,G1050);
not NOT_310(G1098,G1053);
not NOT_311(G1099,G1056);
nand NAND2_145(G1100,G1036,G1066);
nand NAND2_146(G1103,G977,G1068);
not NOT_312(G1104,G1031);
not NOT_313(G1107,G1031);
nand NAND2_147(G1110,G422,G1091);
not NOT_314(G1111,G1072);
nand NAND2_148(G1112,G1075,G1092);
not NOT_315(G1113,G1075);
nand NAND2_149(G1114,G1078,G1093);
not NOT_316(G1115,G1078);
nand NAND2_150(G1116,G675,G1095);
nand NAND2_151(G1117,G678,G1097);
not NOT_317(G1118,G1059);
not NOT_318(G1121,G1059);
nand NAND2_152(G1124,G1081,G1035);
not NOT_319(G1125,G1081);
nand NAND2_153(G1126,G1067,G1103);
not NOT_320(G1129,G1084);
not NOT_321(G1130,G1069);
not NOT_322(G1131,G1087);
not NOT_323(G1132,G1062);
not NOT_324(G1135,G1062);
nand NAND2_154(G1138,G1100,G995);
not NOT_325(G1139,G1100);
nand NAND2_155(G1140,G1090,G1110);
nand NAND2_156(G1143,G1041,G1113);
nand NAND2_157(G1144,G1044,G1115);
nand NAND2_158(G1145,G1094,G1116);
nand NAND2_159(G1148,G1096,G1117);
nand NAND2_160(G1151,G1003,G1125);
not NOT_326(G1152,G1104);
nand NAND2_161(G1153,G1104,G1129);
not NOT_327(G1154,G1107);
nand NAND2_162(G1155,G1107,G1131);
not NOT_328(G1156,G1121);
nand NAND2_163(G1157,G948,G1139);
nand NAND2_164(G1158,G1126,G910);
not NOT_329(G1159,G1126);
nand NAND2_165(G1160,G1112,G1143);
nand NAND2_166(G1163,G1114,G1144);
not NOT_330(G1166,G1132);
nand NAND2_167(G1167,G1132,G1098);
not NOT_331(G1168,G1118);
not NOT_332(G1169,G1135);
nand NAND2_168(G1170,G1135,G1099);
nand NAND2_169(G1171,G1124,G1151);
nand NAND2_170(G1174,G1084,G1152);
nand NAND2_171(G1175,G1087,G1154);
nand NAND2_172(G1176,G1148,G722);
not NOT_333(G1177,G1148);
nand NAND2_173(G1178,G1138,G1157);
nand NAND2_174(G1181,G851,G1159);
nand NAND2_175(G1182,G1140,G212);
not NOT_334(G1185,G1145);
nand NAND2_176(G1186,G1145,G785);
nand NAND2_177(G1187,G1053,G1166);
nand NAND2_178(G1188,G1056,G1169);
nand NAND2_179(G1189,G1174,G1153);
nand NAND2_180(G1192,G1175,G1155);
not NOT_335(G1195,G1140);
nand NAND2_181(G1198,G1163,G965);
not NOT_336(G1199,G1163);
nand NAND2_182(G1200,G1160,G966);
not NOT_337(G1201,G1160);
nand NAND2_183(G1202,G609,G1177);
nand NAND2_184(G1203,G1171,G908);
not NOT_338(G1204,G1171);
nand NAND2_185(G1205,G1158,G1181);
nand NAND2_186(G1208,G606,G1185);
nand NAND2_187(G1209,G1187,G1167);
nand NAND2_188(G1212,G1188,G1170);
nand NAND2_189(G1215,G914,G1199);
nand NAND2_190(G1216,G911,G1201);
nand NAND2_191(G1217,G1176,G1202);
nand NAND2_192(G1218,G845,G1204);
nand NAND2_193(G1219,G1192,G1111);
not NOT_339(G1220,G1192);
not NOT_340(G1221,G1195);
nand NAND2_194(G1222,G1178,G212);
not NOT_341(G1225,G1189);
nand NAND2_195(G1226,G1189,G1130);
not NOT_342(G1227,G1178);
not NOT_343(G1230,G1182);
not NOT_344(G1233,G1182);
nand NAND2_196(G1236,G1186,G1208);
nand NAND2_197(G1239,G1198,G1215);
nand NAND2_198(G1240,G1200,G1216);
nand NAND2_199(G1243,G1212,G1156);
not NOT_345(G1244,G1212);
nand NAND2_200(G1245,G1203,G1218);
nand NAND2_201(G1246,G1072,G1220);
nand NAND2_202(G1247,G1205,G212);
not NOT_346(G1250,G1209);
nand NAND2_203(G1251,G1209,G1168);
nand NAND2_204(G1252,G1069,G1225);
not NOT_347(G1253,G1217);
not NOT_348(G1256,G1205);
not NOT_349(G1259,G1239);
nand NAND2_205(G1260,G1121,G1244);
not NOT_350(G1261,G1245);
nand NAND2_206(G1262,G1219,G1246);
not NOT_351(G1263,G1227);
nand NAND2_207(G1264,G1233,G566);
not NOT_352(G1265,G1233);
nand NAND2_208(G1266,G1230,G567);
not NOT_353(G1267,G1230);
not NOT_354(G1268,G1236);
nand NAND2_209(G1269,G1118,G1250);
not NOT_355(G1270,G1222);
not NOT_356(G1273,G1222);
nand NAND2_210(G1276,G1226,G1252);
nand NAND2_211(G1279,G1243,G1260);
not NOT_357(G1280,G1253);
not NOT_358(G1281,G1256);
nand NAND2_212(G1282,G458,G1265);
nand NAND2_213(G1283,G455,G1267);
not NOT_359(G1284,G1240);
not NOT_360(G1287,G1262);
not NOT_361(G1290,G1247);
not NOT_362(G1293,G1247);
not NOT_363(G1296,G1240);
nand NAND2_214(G1299,G1251,G1269);
and AND2_6(G1302,G1259,G380);
and AND2_7(G1305,G381,G1261);
nand NAND2_215(G1308,G1273,G564);
not NOT_364(G1309,G1273);
nand NAND2_216(G1310,G1270,G565);
not NOT_365(G1311,G1270);
nand NAND2_217(G1312,G1264,G1282);
nand NAND2_218(G1313,G1266,G1283);
not NOT_366(G1316,G1276);
not NOT_367(G1317,G1279);
not NOT_368(G1320,G1284);
nand NAND2_219(G1321,G1284,G1280);
not NOT_369(G1322,G1287);
nand NAND2_220(G1323,G1287,G973);
nand NAND2_221(G1324,G1293,G859);
not NOT_370(G1325,G1293);
nand NAND2_222(G1326,G1290,G860);
not NOT_371(G1327,G1290);
nand NAND2_223(G1328,G452,G1309);
nand NAND2_224(G1329,G449,G1311);
not NOT_372(G1330,G1312);
not NOT_373(G1331,G1296);
nand NAND2_225(G1332,G1296,G1268);
not NOT_374(G1333,G1299);
nand NAND2_226(G1334,G1299,G1065);
not NOT_375(G1335,G1302);
not NOT_376(G1336,G1305);
nand NAND2_227(G1337,G1253,G1320);
not NOT_377(G1338,G1317);
nand NAND2_228(G1339,G1317,G1034);
nand NAND2_229(G1340,G921,G1322);
nand NAND2_230(G1341,G828,G1325);
nand NAND2_231(G1342,G825,G1327);
nand NAND2_232(G1343,G1308,G1328);
nand NAND2_233(G1344,G1310,G1329);
not NOT_378(G1347,G1313);
not NOT_379(G1350,G1313);
nand NAND2_234(G1353,G1236,G1331);
nand NAND2_235(G1354,G1025,G1333);
nand NAND2_236(G1355,G1337,G1321);
nand NAND2_237(G1356,G1000,G1338);
nand NAND2_238(G1357,G1340,G1323);
nand NAND2_239(G1358,G1324,G1341);
nand NAND2_240(G1359,G1326,G1342);
not NOT_380(G1362,G1343);
nand NAND2_241(G1363,G1353,G1332);
nand NAND2_242(G1366,G1354,G1334);
not NOT_381(G1369,G1355);
nand NAND2_243(G1370,G1356,G1339);
nand NAND2_244(G1371,G1357,G212);
not NOT_382(G1374,G1358);
not NOT_383(G1375,G1344);
not NOT_384(G1378,G1344);
not NOT_385(G1381,G1363);
not NOT_386(G1382,G1366);
nand NAND2_245(G1383,G1369,G212);
nand NAND2_246(G1386,G1370,G212);
not NOT_387(G1389,G1359);
not NOT_388(G1392,G1359);
and AND2_8(G1395,G1347,G1375);
and AND2_9(G1410,G1350,G1375);
and AND2_10(G1420,G1347,G1378);
and AND2_11(G1434,G1350,G1378);
not NOT_389(G1439,G1371);
not NOT_390(G1442,G1371);
not NOT_391(G1445,G1383);
not NOT_392(G1448,G1383);
not NOT_393(G1451,G1386);
not NOT_394(G1454,G1386);
nand NAND2_247(G1457,G1442,G562);
not NOT_395(G1458,G1442);
nand NAND2_248(G1459,G1439,G563);
not NOT_396(G1460,G1439);
nand NAND2_249(G1461,G1448,G857);
not NOT_397(G1462,G1448);
nand NAND2_250(G1463,G1445,G858);
not NOT_398(G1464,G1445);
nand NAND2_251(G1465,G1454,G560);
not NOT_399(G1466,G1454);
nand NAND2_252(G1467,G1451,G561);
not NOT_400(G1468,G1451);
nand NAND2_253(G1469,G446,G1458);
nand NAND2_254(G1470,G443,G1460);
nand NAND2_255(G1471,G822,G1462);
nand NAND2_256(G1472,G819,G1464);
nand NAND2_257(G1473,G440,G1466);
nand NAND2_258(G1474,G437,G1468);
nand NAND2_259(G1475,G1457,G1469);
nand NAND2_260(G1476,G1459,G1470);
nand NAND2_261(G1479,G1461,G1471);
nand NAND2_262(G1480,G1463,G1472);
nand NAND2_263(G1483,G1465,G1473);
nand NAND2_264(G1484,G1467,G1474);
not NOT_401(G1487,G1475);
not NOT_402(G1488,G1479);
not NOT_403(G1489,G1483);
not NOT_404(G1490,G1476);
not NOT_405(G1493,G1476);
not NOT_406(G1496,G1480);
and AND2_12(G1499,G731,G1480);
not NOT_407(G1502,G1484);
and AND2_13(G1505,G735,G1484);
nand NAND8_0(G1508,G1374,G1330,G1362,G1487,G546,G1489,G1488,G550);
not NOT_408(G1511,G1499);
not NOT_409(G1522,G1499);
not NOT_410(G1538,G1505);
not NOT_411(G1549,G1505);
and AND2_14(G1563,G1389,G1490);
and AND2_15(G1576,G1392,G1490);
and AND2_16(G1584,G1389,G1493);
and AND2_17(G1598,G1392,G1493);
and AND4_0(G1607,G260,G1508,G235,G235);
and AND2_18(G1608,G730,G1496);
and AND2_19(G1609,G731,G1496);
and AND2_20(G1624,G734,G1502);
and AND2_21(G1625,G735,G1502);
nand NAND5_0(G1642,G1511,G1538,G1584,G1395,G738);
nand NAND5_1(G1645,G1511,G1538,G1563,G1420,G738);
nand NAND5_2(G1648,G1511,G1538,G1563,G1410,G738);
nand NAND5_3(G1651,G1511,G1538,G1576,G1395,G738);
nand NAND5_4(G1654,G1522,G1538,G1598,G1410,G755);
nand NAND5_5(G1657,G1522,G1549,G1584,G1434,G755);
nand NAND5_6(G1660,G1522,G1549,G1598,G1420,G755);
and AND5_0(G1663,G1511,G1538,G1584,G1395,G738);
and AND5_1(G1666,G1511,G1538,G1563,G1420,G738);
and AND5_2(G1669,G1511,G1538,G1563,G1410,G738);
and AND5_3(G1672,G1511,G1538,G1576,G1395,G738);
and AND5_4(G1675,G1522,G1538,G1598,G1410,G755);
and AND5_5(G1678,G1522,G1549,G1584,G1434,G755);
and AND5_6(G1681,G1522,G1549,G1598,G1420,G755);
nand NAND5_7(G1684,G1511,G1625,G1584,G1420,G738);
nand NAND5_8(G1687,G1522,G1625,G1584,G1410,G738);
nand NAND5_9(G1690,G1522,G1625,G1598,G1395,G738);
nand NAND5_10(G1693,G1522,G1625,G1563,G1434,G738);
nand NAND5_11(G1696,G1522,G1625,G1576,G1420,G755);
nand NAND5_12(G1699,G1609,G1549,G1584,G1420,G755);
nand NAND5_13(G1702,G1609,G1549,G1584,G1410,G755);
nand NAND5_14(G1705,G1609,G1549,G1598,G1395,G755);
nand NAND5_15(G1708,G1609,G1549,G1576,G1420,G755);
nand NAND5_16(G1711,G1522,G1625,G1563,G1395,G573);
nand NAND5_17(G1712,G1609,G1549,G1563,G1395,G573);
nand NAND5_18(G1713,G1609,G1625,G1584,G1395,G573);
nand NAND5_19(G1714,G1609,G1625,G1563,G1420,G573);
nand NAND5_20(G1715,G1609,G1625,G1563,G1410,G573);
nand NAND5_21(G1716,G1609,G1625,G1576,G1395,G573);
nand NAND5_22(G1717,G1609,G1624,G1563,G1395,G573);
nand NAND5_23(G1718,G1608,G1625,G1563,G1395,G573);
and AND5_7(G1719,G1511,G1625,G1584,G1420,G738);
and AND5_8(G1722,G1522,G1625,G1584,G1410,G738);
and AND5_9(G1725,G1522,G1625,G1598,G1395,G738);
and AND5_10(G1728,G1522,G1625,G1563,G1434,G738);
and AND5_11(G1731,G1522,G1625,G1576,G1420,G755);
and AND5_12(G1734,G1609,G1549,G1584,G1420,G755);
and AND5_13(G1737,G1609,G1549,G1584,G1410,G755);
and AND5_14(G1740,G1609,G1549,G1598,G1395,G755);
and AND5_15(G1743,G1609,G1549,G1576,G1420,G755);
nand NAND2_265(G1746,G1663,G313);
not NOT_412(G1747,G1663);
nand NAND2_266(G1748,G1666,G314);
not NOT_413(G1749,G1666);
nand NAND2_267(G1750,G1669,G315);
not NOT_414(G1751,G1669);
nand NAND2_268(G1752,G1672,G316);
not NOT_415(G1753,G1672);
nand NAND2_269(G1754,G1675,G322);
not NOT_416(G1755,G1675);
nand NAND2_270(G1756,G1678,G327);
not NOT_417(G1757,G1678);
nand NAND2_271(G1758,G1681,G328);
not NOT_418(G1759,G1681);
and AND8_0(G1760,G1711,G1712,G1713,G1714,G1715,G1716,G1717,G1718);
nand NAND2_272(G1761,G265,G1747);
nand NAND2_273(G1762,G268,G1749);
nand NAND2_274(G1763,G271,G1751);
nand NAND2_275(G1764,G274,G1753);
nand NAND2_276(G1765,G1719,G317);
not NOT_419(G1766,G1719);
nand NAND2_277(G1767,G1722,G318);
not NOT_420(G1768,G1722);
nand NAND2_278(G1769,G1725,G319);
not NOT_421(G1770,G1725);
nand NAND2_279(G1771,G1728,G320);
not NOT_422(G1772,G1728);
nand NAND2_280(G1773,G1731,G321);
not NOT_423(G1774,G1731);
nand NAND2_281(G1775,G292,G1755);
nand NAND2_282(G1776,G1734,G323);
not NOT_424(G1777,G1734);
nand NAND2_283(G1778,G1737,G324);
not NOT_425(G1779,G1737);
nand NAND2_284(G1780,G1740,G325);
not NOT_426(G1781,G1740);
nand NAND2_285(G1782,G1743,G326);
not NOT_427(G1783,G1743);
nand NAND2_286(G1784,G307,G1757);
nand NAND2_287(G1785,G310,G1759);
nand NAND8_1(G1786,G1642,G1645,G1648,G1651,G1684,G1687,G1690,G1693);
nand NAND8_2(G1787,G1696,G1654,G1699,G1702,G1705,G1708,G1657,G1660);
and AND8_1(G1788,G1642,G1645,G1648,G1651,G1684,G1687,G1690,G1693);
and AND8_2(G1791,G1696,G1654,G1699,G1702,G1705,G1708,G1657,G1660);
nand NAND2_288(G1794,G277,G1766);
nand NAND2_289(G1795,G280,G1768);
nand NAND2_290(G1796,G283,G1770);
nand NAND2_291(G1797,G286,G1772);
nand NAND2_292(G1798,G289,G1774);
nand NAND2_293(G1799,G295,G1777);
nand NAND2_294(G1800,G298,G1779);
nand NAND2_295(G1801,G301,G1781);
nand NAND2_296(G1802,G304,G1783);
and AND2_22(G1803,G1786,G197);
and AND2_23(G1806,G1787,G198);
and AND3_5(G1809,G1788,G1791,G1760);
nand NAND2_297(G1810,G1788,G1791);
and AND4_1(G1817,G260,G1508,G32,G1809);
nand NAND2_298(G1818,G1803,G1335);
not NOT_428(G1819,G1803);
nand NAND2_299(G1820,G1806,G1336);
not NOT_429(G1821,G1806);
and AND3_6(G1822,G544,G205,G1810);
and AND3_7(G1825,G25,G205,G1810);
and AND3_8(G1828,G27,G205,G1810);
and AND3_9(G1831,G28,G205,G1810);
and AND3_10(G1834,G545,G205,G1810);
nand NAND2_300(G1837,G1302,G1819);
nand NAND2_301(G1838,G1305,G1821);
and AND3_11(G1839,G26,G205,G1810);
nand NAND2_302(G1842,G1818,G1837);
nand NAND2_303(G1845,G1820,G1838);
nand NAND2_304(G1848,G1822,G1381);
nand NAND2_305(G1849,G1825,G1382);
nand NAND2_306(G1850,G1828,G1263);
nand NAND2_307(G1851,G1831,G1221);
nand NAND2_308(G1852,G1834,G1281);
not NOT_430(G1853,G1822);
not NOT_431(G1854,G1825);
not NOT_432(G1855,G1828);
not NOT_433(G1856,G1831);
not NOT_434(G1857,G1834);
not NOT_435(G1858,G1839);
nand NAND2_309(G1859,G1839,G1316);
nand NAND2_310(G1860,G1363,G1853);
nand NAND2_311(G1861,G1366,G1854);
nand NAND2_312(G1862,G1227,G1855);
nand NAND2_313(G1863,G1195,G1856);
nand NAND2_314(G1864,G1256,G1857);
nand NAND2_315(G1865,G1842,G533);
not NOT_436(G1866,G1842);
nand NAND2_316(G1867,G1845,G534);
not NOT_437(G1868,G1845);
nand NAND2_317(G1869,G1276,G1858);
nand NAND2_318(G1870,G1860,G1848);
nand NAND2_319(G1871,G1861,G1849);
nand NAND2_320(G1872,G1862,G1850);
nand NAND2_321(G1873,G1863,G1851);
nand NAND2_322(G1874,G1864,G1852);
nand NAND2_323(G1875,G461,G1866);
nand NAND2_324(G1876,G464,G1868);
nand NAND2_325(G1877,G1869,G1859);
nand NAND2_326(G1880,G1877,G940);
not NOT_438(G1881,G1877);
nand NAND2_327(G1882,G891,G1881);
nand NAND2_328(G1883,G1880,G1882);
nand NAND2_329(G1884,G1746,G1761);
nand NAND2_330(G1885,G1748,G1762);
nand NAND2_331(G1886,G1750,G1763);
nand NAND2_332(G1887,G1752,G1764);
nand NAND2_333(G1888,G1754,G1775);
nand NAND2_334(G1889,G1756,G1784);
nand NAND2_335(G1890,G1758,G1785);
nand NAND2_336(G1891,G1765,G1794);
nand NAND2_337(G1892,G1767,G1795);
nand NAND2_338(G1893,G1769,G1796);
nand NAND2_339(G1894,G1771,G1797);
nand NAND2_340(G1895,G1773,G1798);
nand NAND2_341(G1896,G1776,G1799);
nand NAND2_342(G1897,G1778,G1800);
nand NAND2_343(G1898,G1780,G1801);
nand NAND2_344(G1899,G1782,G1802);
nor NOR2_0(G1900,G1607,G1817);
and AND2_24(G1901,G1870,G329);
and AND2_25(G1902,G330,G1871);
and AND2_26(G1903,G332,G1872);
and AND2_27(G1904,G1873,G333);
and AND2_28(G1905,G334,G1874);
nand NAND2_345(G1906,G1865,G1875);
nand NAND2_346(G1907,G1867,G1876);
and AND2_29(G1908,G1883,G331);
endmodule |
module c880 (N1,N8,N13,N17,N26,N29,N36,N42,N51,N55,
N59,N68,N72,N73,N74,N75,N80,N85,N86,N87,
N88,N89,N90,N91,N96,N101,N106,N111,N116,N121,
N126,N130,N135,N138,N143,N146,N149,N152,N153,N156,
N159,N165,N171,N177,N183,N189,N195,N201,N207,N210,
N219,N228,N237,N246,N255,N259,N260,N261,N267,N268,
N388,N389,N390,N391,N418,N419,N420,N421,N422,N423,
N446,N447,N448,N449,N450,N767,N768,N850,N863,N864,
N865,N866,N874,N878,N879,N880);
input N1,N8,N13,N17,N26,N29,N36,N42,N51,N55,
N59,N68,N72,N73,N74,N75,N80,N85,N86,N87,
N88,N89,N90,N91,N96,N101,N106,N111,N116,N121,
N126,N130,N135,N138,N143,N146,N149,N152,N153,N156,
N159,N165,N171,N177,N183,N189,N195,N201,N207,N210,
N219,N228,N237,N246,N255,N259,N260,N261,N267,N268;
output N388,N389,N390,N391,N418,N419,N420,N421,N422,N423,
N446,N447,N448,N449,N450,N767,N768,N850,N863,N864,
N865,N866,N874,N878,N879,N880;
wire N269,N270,N273,N276,N279,N280,N284,N285,N286,N287,
N290,N291,N292,N293,N294,N295,N296,N297,N298,N301,
N302,N303,N304,N305,N306,N307,N308,N309,N310,N316,
N317,N318,N319,N322,N323,N324,N325,N326,N327,N328,
N329,N330,N331,N332,N333,N334,N335,N336,N337,N338,
N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,
N349,N350,N351,N352,N353,N354,N355,N356,N357,N360,
N363,N366,N369,N375,N376,N379,N382,N385,N392,N393,
N399,N400,N401,N402,N403,N404,N405,N406,N407,N408,
N409,N410,N411,N412,N413,N414,N415,N416,N417,N424,
N425,N426,N427,N432,N437,N442,N443,N444,N445,N451,
N460,N463,N466,N475,N476,N477,N478,N479,N480,N481,
N482,N483,N488,N489,N490,N491,N492,N495,N498,N499,
N500,N501,N502,N503,N504,N505,N506,N507,N508,N509,
N510,N511,N512,N513,N514,N515,N516,N517,N518,N519,
N520,N521,N522,N523,N524,N525,N526,N527,N528,N529,
N530,N533,N536,N537,N538,N539,N540,N541,N542,N543,
N544,N547,N550,N551,N552,N553,N557,N561,N565,N569,
N573,N577,N581,N585,N586,N587,N588,N589,N590,N593,
N596,N597,N600,N605,N606,N609,N615,N616,N619,N624,
N625,N628,N631,N632,N635,N640,N641,N644,N650,N651,
N654,N659,N660,N661,N662,N665,N669,N670,N673,N677,
N678,N682,N686,N687,N692,N696,N697,N700,N704,N705,
N708,N712,N713,N717,N721,N722,N727,N731,N732,N733,
N734,N735,N736,N737,N738,N739,N740,N741,N742,N743,
N744,N745,N746,N747,N748,N749,N750,N751,N752,N753,
N754,N755,N756,N757,N758,N759,N760,N761,N762,N763,
N764,N765,N766,N769,N770,N771,N772,N773,N777,N778,
N781,N782,N785,N786,N787,N788,N789,N790,N791,N792,
N793,N794,N795,N796,N802,N803,N804,N805,N806,N807,
N808,N809,N810,N811,N812,N813,N814,N815,N819,N822,
N825,N826,N827,N828,N829,N830,N831,N832,N833,N834,
N835,N836,N837,N838,N839,N840,N841,N842,N843,N844,
N845,N846,N847,N848,N849,N851,N852,N853,N854,N855,
N856,N857,N858,N859,N860,N861,N862,N867,N868,N869,
N870,N871,N872,N873,N875,N876,N877;
nand NAND4_1 (N269, N1, N8, N13, N17);
nand NAND4_2 (N270, N1, N26, N13, N17);
and AND3_3 (N273, N29, N36, N42);
and AND3_4 (N276, N1, N26, N51);
nand NAND4_5 (N279, N1, N8, N51, N17);
nand NAND4_6 (N280, N1, N8, N13, N55);
nand NAND4_7 (N284, N59, N42, N68, N72);
nand NAND2_8 (N285, N29, N68);
nand NAND3_9 (N286, N59, N68, N74);
and AND3_10 (N287, N29, N75, N80);
and AND3_11 (N290, N29, N75, N42);
and AND3_12 (N291, N29, N36, N80);
and AND3_13 (N292, N29, N36, N42);
and AND3_14 (N293, N59, N75, N80);
and AND3_15 (N294, N59, N75, N42);
and AND3_16 (N295, N59, N36, N80);
and AND3_17 (N296, N59, N36, N42);
and AND2_18 (N297, N85, N86);
or OR2_19 (N298, N87, N88);
nand NAND2_20 (N301, N91, N96);
or OR2_21 (N302, N91, N96);
nand NAND2_22 (N303, N101, N106);
or OR2_23 (N304, N101, N106);
nand NAND2_24 (N305, N111, N116);
or OR2_25 (N306, N111, N116);
nand NAND2_26 (N307, N121, N126);
or OR2_27 (N308, N121, N126);
and AND2_28 (N309, N8, N138);
not NOT1_29 (N310, N268);
and AND2_30 (N316, N51, N138);
and AND2_31 (N317, N17, N138);
and AND2_32 (N318, N152, N138);
nand NAND2_33 (N319, N59, N156);
nor NOR2_34 (N322, N17, N42);
and AND2_35 (N323, N17, N42);
nand NAND2_36 (N324, N159, N165);
or OR2_37 (N325, N159, N165);
nand NAND2_38 (N326, N171, N177);
or OR2_39 (N327, N171, N177);
nand NAND2_40 (N328, N183, N189);
or OR2_41 (N329, N183, N189);
nand NAND2_42 (N330, N195, N201);
or OR2_43 (N331, N195, N201);
and AND2_44 (N332, N210, N91);
and AND2_45 (N333, N210, N96);
and AND2_46 (N334, N210, N101);
and AND2_47 (N335, N210, N106);
and AND2_48 (N336, N210, N111);
and AND2_49 (N337, N255, N259);
and AND2_50 (N338, N210, N116);
and AND2_51 (N339, N255, N260);
and AND2_52 (N340, N210, N121);
and AND2_53 (N341, N255, N267);
not NOT1_54 (N342, N269);
not NOT1_55 (N343, N273);
or OR2_56 (N344, N270, N273);
not NOT1_57 (N345, N276);
not NOT1_58 (N346, N276);
not NOT1_59 (N347, N279);
nor NOR2_60 (N348, N280, N284);
or OR2_61 (N349, N280, N285);
or OR2_62 (N350, N280, N286);
not NOT1_63 (N351, N293);
not NOT1_64 (N352, N294);
not NOT1_65 (N353, N295);
not NOT1_66 (N354, N296);
nand NAND2_67 (N355, N89, N298);
and AND2_68 (N356, N90, N298);
nand NAND2_69 (N357, N301, N302);
nand NAND2_70 (N360, N303, N304);
nand NAND2_71 (N363, N305, N306);
nand NAND2_72 (N366, N307, N308);
not NOT1_73 (N369, N310);
nor NOR2_74 (N375, N322, N323);
nand NAND2_75 (N376, N324, N325);
nand NAND2_76 (N379, N326, N327);
nand NAND2_77 (N382, N328, N329);
nand NAND2_78 (N385, N330, N331);
buf BUFF1_79 (N388, N290);
buf BUFF1_80 (N389, N291);
buf BUFF1_81 (N390, N292);
buf BUFF1_82 (N391, N297);
or OR2_83 (N392, N270, N343);
not NOT1_84 (N393, N345);
not NOT1_85 (N399, N346);
and AND2_86 (N400, N348, N73);
not NOT1_87 (N401, N349);
not NOT1_88 (N402, N350);
not NOT1_89 (N403, N355);
not NOT1_90 (N404, N357);
not NOT1_91 (N405, N360);
and AND2_92 (N406, N357, N360);
not NOT1_93 (N407, N363);
not NOT1_94 (N408, N366);
and AND2_95 (N409, N363, N366);
nand NAND2_96 (N410, N347, N352);
not NOT1_97 (N411, N376);
not NOT1_98 (N412, N379);
and AND2_99 (N413, N376, N379);
not NOT1_100 (N414, N382);
not NOT1_101 (N415, N385);
and AND2_102 (N416, N382, N385);
and AND2_103 (N417, N210, N369);
buf BUFF1_104 (N418, N342);
buf BUFF1_105 (N419, N344);
buf BUFF1_106 (N420, N351);
buf BUFF1_107 (N421, N353);
buf BUFF1_108 (N422, N354);
buf BUFF1_109 (N423, N356);
not NOT1_110 (N424, N400);
and AND2_111 (N425, N404, N405);
and AND2_112 (N426, N407, N408);
and AND3_113 (N427, N319, N393, N55);
and AND3_114 (N432, N393, N17, N287);
nand NAND3_115 (N437, N393, N287, N55);
nand NAND4_116 (N442, N375, N59, N156, N393);
nand NAND3_117 (N443, N393, N319, N17);
and AND2_118 (N444, N411, N412);
and AND2_119 (N445, N414, N415);
buf BUFF1_120 (N446, N392);
buf BUFF1_121 (N447, N399);
buf BUFF1_122 (N448, N401);
buf BUFF1_123 (N449, N402);
buf BUFF1_124 (N450, N403);
not NOT1_125 (N451, N424);
nor NOR2_126 (N460, N406, N425);
nor NOR2_127 (N463, N409, N426);
nand NAND2_128 (N466, N442, N410);
and AND2_129 (N475, N143, N427);
and AND2_130 (N476, N310, N432);
and AND2_131 (N477, N146, N427);
and AND2_132 (N478, N310, N432);
and AND2_133 (N479, N149, N427);
and AND2_134 (N480, N310, N432);
and AND2_135 (N481, N153, N427);
and AND2_136 (N482, N310, N432);
nand NAND2_137 (N483, N443, N1);
or OR2_138 (N488, N369, N437);
or OR2_139 (N489, N369, N437);
or OR2_140 (N490, N369, N437);
or OR2_141 (N491, N369, N437);
nor NOR2_142 (N492, N413, N444);
nor NOR2_143 (N495, N416, N445);
nand NAND2_144 (N498, N130, N460);
or OR2_145 (N499, N130, N460);
nand NAND2_146 (N500, N463, N135);
or OR2_147 (N501, N463, N135);
and AND2_148 (N502, N91, N466);
nor NOR2_149 (N503, N475, N476);
and AND2_150 (N504, N96, N466);
nor NOR2_151 (N505, N477, N478);
and AND2_152 (N506, N101, N466);
nor NOR2_153 (N507, N479, N480);
and AND2_154 (N508, N106, N466);
nor NOR2_155 (N509, N481, N482);
and AND2_156 (N510, N143, N483);
and AND2_157 (N511, N111, N466);
and AND2_158 (N512, N146, N483);
and AND2_159 (N513, N116, N466);
and AND2_160 (N514, N149, N483);
and AND2_161 (N515, N121, N466);
and AND2_162 (N516, N153, N483);
and AND2_163 (N517, N126, N466);
nand NAND2_164 (N518, N130, N492);
or OR2_165 (N519, N130, N492);
nand NAND2_166 (N520, N495, N207);
or OR2_167 (N521, N495, N207);
and AND2_168 (N522, N451, N159);
and AND2_169 (N523, N451, N165);
and AND2_170 (N524, N451, N171);
and AND2_171 (N525, N451, N177);
and AND2_172 (N526, N451, N183);
nand NAND2_173 (N527, N451, N189);
nand NAND2_174 (N528, N451, N195);
nand NAND2_175 (N529, N451, N201);
nand NAND2_176 (N530, N498, N499);
nand NAND2_177 (N533, N500, N501);
nor NOR2_178 (N536, N309, N502);
nor NOR2_179 (N537, N316, N504);
nor NOR2_180 (N538, N317, N506);
nor NOR2_181 (N539, N318, N508);
nor NOR2_182 (N540, N510, N511);
nor NOR2_183 (N541, N512, N513);
nor NOR2_184 (N542, N514, N515);
nor NOR2_185 (N543, N516, N517);
nand NAND2_186 (N544, N518, N519);
nand NAND2_187 (N547, N520, N521);
not NOT1_188 (N550, N530);
not NOT1_189 (N551, N533);
and AND2_190 (N552, N530, N533);
nand NAND2_191 (N553, N536, N503);
nand NAND2_192 (N557, N537, N505);
nand NAND2_193 (N561, N538, N507);
nand NAND2_194 (N565, N539, N509);
nand NAND2_195 (N569, N488, N540);
nand NAND2_196 (N573, N489, N541);
nand NAND2_197 (N577, N490, N542);
nand NAND2_198 (N581, N491, N543);
not NOT1_199 (N585, N544);
not NOT1_200 (N586, N547);
and AND2_201 (N587, N544, N547);
and AND2_202 (N588, N550, N551);
and AND2_203 (N589, N585, N586);
nand NAND2_204 (N590, N553, N159);
or OR2_205 (N593, N553, N159);
and AND2_206 (N596, N246, N553);
nand NAND2_207 (N597, N557, N165);
or OR2_208 (N600, N557, N165);
and AND2_209 (N605, N246, N557);
nand NAND2_210 (N606, N561, N171);
or OR2_211 (N609, N561, N171);
and AND2_212 (N615, N246, N561);
nand NAND2_213 (N616, N565, N177);
or OR2_214 (N619, N565, N177);
and AND2_215 (N624, N246, N565);
nand NAND2_216 (N625, N569, N183);
or OR2_217 (N628, N569, N183);
and AND2_218 (N631, N246, N569);
nand NAND2_219 (N632, N573, N189);
or OR2_220 (N635, N573, N189);
and AND2_221 (N640, N246, N573);
nand NAND2_222 (N641, N577, N195);
or OR2_223 (N644, N577, N195);
and AND2_224 (N650, N246, N577);
nand NAND2_225 (N651, N581, N201);
or OR2_226 (N654, N581, N201);
and AND2_227 (N659, N246, N581);
nor NOR2_228 (N660, N552, N588);
nor NOR2_229 (N661, N587, N589);
not NOT1_230 (N662, N590);
and AND2_231 (N665, N593, N590);
nor NOR2_232 (N669, N596, N522);
not NOT1_233 (N670, N597);
and AND2_234 (N673, N600, N597);
nor NOR2_235 (N677, N605, N523);
not NOT1_236 (N678, N606);
and AND2_237 (N682, N609, N606);
nor NOR2_238 (N686, N615, N524);
not NOT1_239 (N687, N616);
and AND2_240 (N692, N619, N616);
nor NOR2_241 (N696, N624, N525);
not NOT1_242 (N697, N625);
and AND2_243 (N700, N628, N625);
nor NOR2_244 (N704, N631, N526);
not NOT1_245 (N705, N632);
and AND2_246 (N708, N635, N632);
nor NOR2_247 (N712, N337, N640);
not NOT1_248 (N713, N641);
and AND2_249 (N717, N644, N641);
nor NOR2_250 (N721, N339, N650);
not NOT1_251 (N722, N651);
and AND2_252 (N727, N654, N651);
nor NOR2_253 (N731, N341, N659);
nand NAND2_254 (N732, N654, N261);
nand NAND3_255 (N733, N644, N654, N261);
nand NAND4_256 (N734, N635, N644, N654, N261);
not NOT1_257 (N735, N662);
and AND2_258 (N736, N228, N665);
and AND2_259 (N737, N237, N662);
not NOT1_260 (N738, N670);
and AND2_261 (N739, N228, N673);
and AND2_262 (N740, N237, N670);
not NOT1_263 (N741, N678);
and AND2_264 (N742, N228, N682);
and AND2_265 (N743, N237, N678);
not NOT1_266 (N744, N687);
and AND2_267 (N745, N228, N692);
and AND2_268 (N746, N237, N687);
not NOT1_269 (N747, N697);
and AND2_270 (N748, N228, N700);
and AND2_271 (N749, N237, N697);
not NOT1_272 (N750, N705);
and AND2_273 (N751, N228, N708);
and AND2_274 (N752, N237, N705);
not NOT1_275 (N753, N713);
and AND2_276 (N754, N228, N717);
and AND2_277 (N755, N237, N713);
not NOT1_278 (N756, N722);
nor NOR2_279 (N757, N727, N261);
and AND2_280 (N758, N727, N261);
and AND2_281 (N759, N228, N727);
and AND2_282 (N760, N237, N722);
nand NAND2_283 (N761, N644, N722);
nand NAND2_284 (N762, N635, N713);
nand NAND3_285 (N763, N635, N644, N722);
nand NAND2_286 (N764, N609, N687);
nand NAND2_287 (N765, N600, N678);
nand NAND3_288 (N766, N600, N609, N687);
buf BUFF1_289 (N767, N660);
buf BUFF1_290 (N768, N661);
nor NOR2_291 (N769, N736, N737);
nor NOR2_292 (N770, N739, N740);
nor NOR2_293 (N771, N742, N743);
nor NOR2_294 (N772, N745, N746);
nand NAND4_295 (N773, N750, N762, N763, N734);
nor NOR2_296 (N777, N748, N749);
nand NAND3_297 (N778, N753, N761, N733);
nor NOR2_298 (N781, N751, N752);
nand NAND2_299 (N782, N756, N732);
nor NOR2_300 (N785, N754, N755);
nor NOR2_301 (N786, N757, N758);
nor NOR2_302 (N787, N759, N760);
nor NOR2_303 (N788, N700, N773);
and AND2_304 (N789, N700, N773);
nor NOR2_305 (N790, N708, N778);
and AND2_306 (N791, N708, N778);
nor NOR2_307 (N792, N717, N782);
and AND2_308 (N793, N717, N782);
and AND2_309 (N794, N219, N786);
nand NAND2_310 (N795, N628, N773);
nand NAND2_311 (N796, N795, N747);
nor NOR2_312 (N802, N788, N789);
nor NOR2_313 (N803, N790, N791);
nor NOR2_314 (N804, N792, N793);
nor NOR2_315 (N805, N340, N794);
nor NOR2_316 (N806, N692, N796);
and AND2_317 (N807, N692, N796);
and AND2_318 (N808, N219, N802);
and AND2_319 (N809, N219, N803);
and AND2_320 (N810, N219, N804);
nand NAND4_321 (N811, N805, N787, N731, N529);
nand NAND2_322 (N812, N619, N796);
nand NAND3_323 (N813, N609, N619, N796);
nand NAND4_324 (N814, N600, N609, N619, N796);
nand NAND4_325 (N815, N738, N765, N766, N814);
nand NAND3_326 (N819, N741, N764, N813);
nand NAND2_327 (N822, N744, N812);
nor NOR2_328 (N825, N806, N807);
nor NOR2_329 (N826, N335, N808);
nor NOR2_330 (N827, N336, N809);
nor NOR2_331 (N828, N338, N810);
not NOT1_332 (N829, N811);
nor NOR2_333 (N830, N665, N815);
and AND2_334 (N831, N665, N815);
nor NOR2_335 (N832, N673, N819);
and AND2_336 (N833, N673, N819);
nor NOR2_337 (N834, N682, N822);
and AND2_338 (N835, N682, N822);
and AND2_339 (N836, N219, N825);
nand NAND3_340 (N837, N826, N777, N704);
nand NAND4_341 (N838, N827, N781, N712, N527);
nand NAND4_342 (N839, N828, N785, N721, N528);
not NOT1_343 (N840, N829);
nand NAND2_344 (N841, N815, N593);
nor NOR2_345 (N842, N830, N831);
nor NOR2_346 (N843, N832, N833);
nor NOR2_347 (N844, N834, N835);
nor NOR2_348 (N845, N334, N836);
not NOT1_349 (N846, N837);
not NOT1_350 (N847, N838);
not NOT1_351 (N848, N839);
and AND2_352 (N849, N735, N841);
buf BUFF1_353 (N850, N840);
and AND2_354 (N851, N219, N842);
and AND2_355 (N852, N219, N843);
and AND2_356 (N853, N219, N844);
nand NAND3_357 (N854, N845, N772, N696);
not NOT1_358 (N855, N846);
not NOT1_359 (N856, N847);
not NOT1_360 (N857, N848);
not NOT1_361 (N858, N849);
nor NOR2_362 (N859, N417, N851);
nor NOR2_363 (N860, N332, N852);
nor NOR2_364 (N861, N333, N853);
not NOT1_365 (N862, N854);
buf BUFF1_366 (N863, N855);
buf BUFF1_367 (N864, N856);
buf BUFF1_368 (N865, N857);
buf BUFF1_369 (N866, N858);
nand NAND3_370 (N867, N859, N769, N669);
nand NAND3_371 (N868, N860, N770, N677);
nand NAND3_372 (N869, N861, N771, N686);
not NOT1_373 (N870, N862);
not NOT1_374 (N871, N867);
not NOT1_375 (N872, N868);
not NOT1_376 (N873, N869);
buf BUFF1_377 (N874, N870);
not NOT1_378 (N875, N871);
not NOT1_379 (N876, N872);
not NOT1_380 (N877, N873);
buf BUFF1_381 (N878, N875);
buf BUFF1_382 (N879, N876);
buf BUFF1_383 (N880, N877);
endmodule |
module AND2_HPNW4 (Y, A, B);
output Y;
input A, B;
// Function
buf (Y, 1'b0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule |
module AOI21_HPNW4 (Y, A0, A1, B0);
output Y;
input A0, A1, B0;
// Function
buf (Y, 1'b0);
// Timing
specify
(A0 => Y) = 0;
(A1 => Y) = 0;
if ((A0 & ~A1))
(B0 => Y) = 0;
if ((~A0 & A1))
(B0 => Y) = 0;
if ((~A0 & ~A1))
(B0 => Y) = 0;
ifnone (B0 => Y) = 0;
endspecify
endmodule |
module DFFNQ1_HPNW4 (Q, D, CKN);
output Q;
input D, CKN;
reg notifier;
wire delayed_D, delayed_CKN;
// Missing function for pin Q
// Timing
specify
(negedge CKN => (Q:CKN)) = 0;
$setuphold (negedge CKN, posedge D, 0, 0, notifier,,, delayed_CKN, delayed_D);
$setuphold (negedge CKN, negedge D, 0, 0, notifier,,, delayed_CKN, delayed_D);
$width (posedge CKN, 0, 0, notifier);
$width (negedge CKN, 0, 0, notifier);
endspecify
endmodule |
module DFFQ1_HPNW4 (Q, D, CK);
output Q;
input D, CK;
reg notifier;
wire delayed_D, delayed_CK;
// Missing function for pin Q
// Timing
specify
(posedge CK => (Q:CK)) = 0;
$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$width (posedge CK, 0, 0, notifier);
$width (negedge CK, 0, 0, notifier);
endspecify
endmodule |
module INV1_HPNW4 (Y, A);
output Y;
input A;
// Function
buf (Y, 1'b0);
// Timing
specify
if (A)
(posedge A => (Y-:1'b0)) = 0;
if (~A)
(negedge A => (Y+:1'b1)) = 0;
ifnone (A => Y) = 0;
endspecify
endmodule |
module MUX2_HPNW4 (Y, A, B, S0);
output Y;
input A, B, S0;
// Function
buf (Y, 1'b0);
// Timing
specify
if (B)
(A => Y) = 0;
if (~B)
(A => Y) = 0;
ifnone (A => Y) = 0;
if (A)
(B => Y) = 0;
if (~A)
(B => Y) = 0;
ifnone (B => Y) = 0;
(posedge S0 => (Y:S0)) = 0;
(negedge S0 => (Y:S0)) = 0;
endspecify
endmodule |
module XNOR2_HPNW4 (Y, A, B);
output Y;
input A, B;
// Function
buf (Y, 1'b0);
// Timing
specify
(posedge A => (Y:A)) = 0;
(negedge A => (Y:A)) = 0;
(posedge B => (Y:B)) = 0;
(negedge B => (Y:B)) = 0;
endspecify
endmodule |
module XNOR3_HPNW4 (Y, A, B, C);
output Y;
input A, B, C;
// Function
buf (Y, 1'b0);
// Timing
specify
if ((B & ~C))
(A => Y) = 0;
if ((~B & C))
(A => Y) = 0;
ifnone (A => Y) = 0;
if ((B & C))
(A => Y) = 0;
if ((~B & ~C))
(A => Y) = 0;
if ((A & ~C))
(B => Y) = 0;
if ((~A & C))
(B => Y) = 0;
ifnone (B => Y) = 0;
if ((A & C))
(B => Y) = 0;
if ((~A & ~C))
(B => Y) = 0;
if ((A & ~B))
(C => Y) = 0;
if ((~A & B))
(C => Y) = 0;
ifnone (C => Y) = 0;
if ((A & B))
(C => Y) = 0;
if ((~A & ~B))
(C => Y) = 0;
endspecify
endmodule |
module mapped_register(D, Q, CLK);
input D, CLK;
output Q;
wire B;
sky130_fd_sc_hd__dfxtp_1 fflop (.CLK(CLK), .D(D), .Q(B));
sky130_fd_sc_hd__buf_8 buffer (.A(B), .X(Q));
endmodule |
module mapped_inverter(A, Y);
input A; output Y;
sky130_fd_sc_hd__inv_1 i(.A(A), .Y(Y));
endmodule |
module GPIO (
input clk,
input rst,
input [31:0] io_addr,
input io_op,
input [3:0] io_mask,
input [31:0] io_wdata,
output [31:0] io_rdata,
output [1:0] io_gpio
);
reg [1:0] out_val;
assign io_gpio = out_val;
assign rdata = {30'h0, out_val};
always @(posedge clk) begin
if (rst) begin
out_val <= 2'h0;
end
else begin
if (io_op) begin
out_val <= io_wdata[1:0];
end
end
end
endmodule |
module DataPath (
input clk,
input rst,
input io_interrupt,
input [3:0] io_hart_id,
input [31:0] io_reset_vector,
output [31:0] io_imem_addr,
input [31:0] io_imem_rdata,
output [31:0] io_dmem_addr,
input [3:0] io_dmem_mask,
output [31:0] io_dmem_wdata,
input [31:0] io_dmem_rdata,
// from control path
input io_ctl_stall,
// input dmiss,
input [`PC_SEL_WIDTH-1:0] io_ctl_pc_sel,
input [`IMM_SEL_WIDTH-1:0] io_ctl_imm_sel,
input io_ctl_op1_sel, // 0: rs1, 1: immediate
input io_ctl_op2_sel, // 0: rs2, 1: immediate
input [`ALU_SEL_WIDTH-1:0] io_ctl_alu_sel,
input io_ctl_mem_signed,
input [`WB_SEL_WIDTH-1:0] io_ctl_wb_sel,
input io_ctl_rf_wen,
// input io_ctl_csr_cmd = Output(UInt(CSR.SZ.W))
// input io_ctl_exception = Output(Bool())
// input io_ctl_exception_cause = Output(UInt(32.W))
// input io_ctl_pc_sel_no_xept = Output(UInt(PC_4.getWidth.W)) // Use only for instuction misalignment detection
// to control path
output [31:0] io_dat_inst,
// output imiss,
output io_dat_br_eq,
output io_dat_br_lt,
output io_dat_br_ltu
// output csr_eret = Output(Bool())
// output csr_interrupt = Output(Bool())
// output inst_misaligned = Output(Bool())
);
wire [31:0] pc;
wire [31:0] pc_next;
wire [31:0] pc_4;
wire [31:0] br_target;
wire [31:0] jump_target;
wire [31:0] jump_reg_target;
wire [31:0] exception_target;
// PC Register
Register_R_CE #(
.N(32),
.INIT(32'h00000000)
) pc_reg (
.clk(clk),
.rst(rst),
.ce(~io_ctl_stall),
.d(pc_next),
.q(pc)
);
assign pc_4 = pc + 32'h00000004;
// TODO: make sure we are word aligned?
assign pc_next = (
(io_ctl_pc_sel == `PC_SEL_PC4) ? pc_4 :
(io_ctl_pc_sel == `PC_SEL_BR) ? br_target :
(io_ctl_pc_sel == `PC_SEL_JAL) ? jump_target :
(io_ctl_pc_sel == `PC_SEL_JALR) ? jump_reg_target :
(io_ctl_pc_sel == `PC_SEL_EXC) ? exception_target :
pc_4
);
// Instruction memory fetching
assign io_imem_addr = pc;
wire [31:0] inst;
assign inst = io_imem_rdata;
// Decode
// extract addr fields
wire [4:0] rd_addr;
wire [4:0] rs1_addr;
wire [4:0] rs2_addr;
assign rd_addr = inst[11:7];
assign rs1_addr = inst[19:15];
assign rs2_addr = inst[24:20];
// Register File
wire [31:0] rs1_data;
wire [31:0] rs2_data;
wire signed [31:0] rs1_data_signed;
wire signed [31:0] rs2_data_signed;
wire [31:0] wb_data;
wire rd_wen;
assign rs1_data_signed = rs1_data;
assign rs2_data_signed = rs2_data;
assign rd_wen = io_ctl_rf_wen;
RegFile regfile (
.clk(clk),
.io_rd_addr(rd_addr),
.io_rd_wen(rd_wen),
.io_rd_data(wb_data),
.io_rs1_addr(rs1_addr),
.io_rs1_data(rs1_data),
.io_rs2_addr(rs2_addr),
.io_rs2_data(rs2_data)
);
wire [31:0] imm_i;
wire [31:0] imm_s;
wire [31:0] imm_b;
wire [31:0] imm_u;
wire [31:0] imm_j;
wire [31:0] imm_z;
wire [31:0] imm;
// immediate number generation
assign imm_i = {{20{inst[31]}}, inst[31:20]};
assign imm_s = {{20{inst[31]}}, inst[31:25], inst[11:7]};
assign imm_b = {{19{inst[31]}}, inst[31], inst[7], inst[30:25], inst[11:8], 1'b0};
assign imm_u = {inst[31:12], {12{1'b0}}};
assign imm_j = {{19{inst[31]}}, inst[31], inst[19:12], inst[20], inst[30:21], 1'b0};
assign imm_z = {{27{1'b0}}, inst[19:15]};
assign imm = (
(io_ctl_imm_sel == `IMM_SEL_R) ? imm_i :
(io_ctl_imm_sel == `IMM_SEL_I) ? imm_i :
(io_ctl_imm_sel == `IMM_SEL_S) ? imm_s :
(io_ctl_imm_sel == `IMM_SEL_B) ? imm_b :
(io_ctl_imm_sel == `IMM_SEL_U) ? imm_u :
(io_ctl_imm_sel == `IMM_SEL_J) ? imm_j :
(io_ctl_imm_sel == `IMM_SEL_Z) ? imm_z :
'h0
);
wire [31:0] alu_in_a;
wire [31:0] alu_in_b;
wire [31:0] alu_out;
assign alu_in_a = (
(io_ctl_op1_sel == `OP1_SEL_RS1) ? rs1_data :
(io_ctl_op1_sel == `OP1_SEL_PC) ? pc :
'h0
);
assign alu_in_b = (
(io_ctl_op2_sel == `OP2_SEL_RS2) ? rs2_data :
(io_ctl_op2_sel == `OP2_SEL_IMM) ? imm :
'h0
);
ALU alu (
.io_sel(io_ctl_alu_sel),
.io_in_a(alu_in_a),
.io_in_b(alu_in_b),
.io_out(alu_out)
);
// Branch/Jump Target Calculation
assign br_target = pc + imm_b;
assign jump_target = pc + imm_j;
assign jump_reg_target = rs1_data + imm_i;
wire [31:0] csr_rdata;
// Memory load data formatting
wire [31:0] load_data;
assign load_data = (
(io_dmem_mask == 'b1111) ? io_dmem_rdata :
(io_ctl_mem_signed && (io_dmem_mask == 'b0011)) ? {{16{io_dmem_rdata[15]}}, io_dmem_rdata[15:0]} :
(io_ctl_mem_signed && (io_dmem_mask == 'b1100)) ? {{16{io_dmem_rdata[31]}}, io_dmem_rdata[31:16]} :
(io_ctl_mem_signed && (io_dmem_mask == 'b0001)) ? {{24{io_dmem_rdata[7]}}, io_dmem_rdata[7:0]} :
(io_ctl_mem_signed && (io_dmem_mask == 'b0010)) ? {{24{io_dmem_rdata[15]}}, io_dmem_rdata[15:8]} :
(io_ctl_mem_signed && (io_dmem_mask == 'b0100)) ? {{24{io_dmem_rdata[23]}}, io_dmem_rdata[23:16]} :
(io_ctl_mem_signed && (io_dmem_mask == 'b1000)) ? {{24{io_dmem_rdata[31]}}, io_dmem_rdata[31:24]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b0011)) ? {{16'h0}, io_dmem_rdata[15:0]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b1100)) ? {{16'h0}, io_dmem_rdata[31:16]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b0001)) ? {{24'h0}, io_dmem_rdata[7:0]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b0010)) ? {{24'h0}, io_dmem_rdata[15:8]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b0100)) ? {{24'h0}, io_dmem_rdata[23:16]} :
(!io_ctl_mem_signed && (io_dmem_mask == 'b1000)) ? {{24'h0}, io_dmem_rdata[31:24]} :
'h0
);
assign io_dmem_wdata = rs2_data << (8 * io_dmem_addr[1:0]);
// WB Mux
assign wb_data = (
(io_ctl_wb_sel == `WB_SEL_ALU) ? alu_out :
(io_ctl_wb_sel == `WB_SEL_MEM) ? load_data :
(io_ctl_wb_sel == `WB_SEL_PC4) ? pc_4 :
(io_ctl_wb_sel == `WB_SEL_CSR) ? csr_rdata :
alu_out
);
// datapath to controlpath outputs
assign io_dat_inst = inst;
assign io_dat_br_eq = rs1_data == rs2_data;
assign io_dat_br_lt = rs1_data_signed < rs2_data_signed;
assign io_dat_br_ltu = rs1_data < rs2_data;
// datapath to data memory outputs
assign io_dmem_addr = alu_out;
assign io_dmem_data = rs2_data;
endmodule |
module ALU (
input [`ALU_SEL_WIDTH-1:0] io_sel,
input [31:0] io_in_a,
input [31:0] io_in_b,
output [31:0] io_out
);
wire [31:0] out_add, out_and, out_or, out_sll, out_slt,
out_sltu, out_sra, out_srl, out_sub, out_xor;
wire signed [31:0] a_signed, b_signed;
assign a_signed = io_in_a;
assign b_signed = io_in_b;
assign out_add = io_in_a + io_in_b;
assign out_sub = io_in_a - io_in_b;
assign out_sll = io_in_a << io_in_b[4:0];
assign out_slt = (a_signed < b_signed) ? 'h01 : 'h00;
assign out_sltu = (io_in_a < io_in_b) ? 'h01 : 'h00;
assign out_xor = io_in_a ^ io_in_b;
assign out_srl = io_in_a >> io_in_b[4:0];
assign out_sra = a_signed >>> io_in_b[4:0];
assign out_or = io_in_a | io_in_b;
assign out_and = io_in_a & io_in_b;
assign io_out = (
(io_sel == `ALU_SEL_ADD) ? out_add :
(io_sel == `ALU_SEL_SUB) ? out_sub :
(io_sel == `ALU_SEL_SLL) ? out_sll :
(io_sel == `ALU_SEL_SRL) ? out_srl :
(io_sel == `ALU_SEL_SRA) ? out_sra :
(io_sel == `ALU_SEL_AND) ? out_and :
(io_sel == `ALU_SEL_OR) ? out_or :
(io_sel == `ALU_SEL_XOR) ? out_xor :
(io_sel == `ALU_SEL_SLT) ? out_slt :
(io_sel == `ALU_SEL_SLTU) ? out_sltu :
(io_sel == `ALU_SEL_COPYB) ? io_in_b :
'h0);
endmodule |
module Tile (
input clk,
input rst,
output [3:0] led
);
wire clk;
wire rst;
wire io_interrupt;
wire [3:0] io_hart_id;
wire [31:0] io_reset_vector;
parameter DMEM_BASE = 32'h08000000;
parameter GPIO_BASE = 32'h10010000;
wire [31:0] imem_addr;
wire [31:0] imem_rdata;
wire [31:0] dmem_addr;
wire dmem_op;
wire [3:0] dmem_mask;
wire [31:0] dmem_wdata;
wire [31:0] dmem_rdata;
wire dmem_mem_op;
wire dmem_gpio_op;
wire [31:0] dmem_mem_addr;
wire [31:0] dmem_mem_rdata;
wire [31:0] dmem_gpio_addr;
wire [31:0] dmem_gpio_rdata;
wire gpio_selected = (dmem_addr >= GPIO_BASE) && (dmem_addr < GPIO_BASE + 'h1000);
wire dmem_selected = (dmem_addr >= DMEM_BASE) && (dmem_addr < DMEM_BASE + 'h1000);
assign dmem_rdata = gpio_selected ? dmem_gpio_rdata : dmem_mem_rdata;
assign dmem_mem_op = dmem_selected ? dmem_op : 1'b0;
assign dmem_gpio_op = gpio_selected ? dmem_op : 1'b0;
assign dmem_mem_addr = dmem_addr - DMEM_BASE;
assign dmem_gpio_addr = dmem_addr - GPIO_BASE;
Core core (
.clk(clk),
.rst(rst),
.io_interrupt(io_interrupt),
.io_hart_id(io_hart_id),
.io_reset_vector(io_reset_vector),
.io_imem_addr(imem_addr),
.io_imem_rdata(imem_rdata),
.io_dmem_addr(dmem_addr),
.io_dmem_op(dmem_op),
.io_dmem_mask(dmem_mask),
.io_dmem_wdata(dmem_wdata),
.io_dmem_rdata(dmem_rdata)
);
ROM imem (
.clk(clk),
.addr(imem_addr[15:2]),
.dout(imem_rdata)
);
RAM_Simple dmem (
.clk(clk),
.addr(dmem_mem_addr[15:2]),
.op(dmem_mem_op),
.mask(dmem_mask),
.wdata(dmem_wdata),
.rdata(dmem_mem_rdata)
);
GPIO gpio (
.clk(clk),
.rst(rst),
.io_addr(dmem_gpio_addr),
.io_op(dmem_gpio_op),
.io_mask(dmem_mask),
.io_wdata(dmem_wdata),
.io_rdata(dmem_gpio_rdata),
.io_gpio(led[1:0])
);
assign led[2] = 1'b1;
assign led[3] = 1'b0;
endmodule |
module Core (
input clk,
input rst,
input io_interrupt,
input [3:0] io_hart_id,
input [31:0] io_reset_vector,
output [31:0] io_imem_addr,
input [31:0] io_imem_rdata,
output [31:0] io_dmem_addr,
output [`MEM_OP_WIDTH-1:0] io_dmem_op,
output [3:0] io_dmem_mask,
output [31:0] io_dmem_wdata,
input [31:0] io_dmem_rdata
);
wire [1:0] dmem_addr_offset;
wire ctl_stall;
wire [`PC_SEL_WIDTH-1:0] ctl_pc_sel;
wire [`IMM_SEL_WIDTH-1:0] ctl_imm_sel;
wire ctl_op1_sel;
wire ctl_op2_sel;
wire [`ALU_SEL_WIDTH-1:0] ctl_alu_sel;
wire ctl_mem_signed;
wire [`WB_SEL_WIDTH-1:0] ctl_wb_sel;
wire ctl_rf_wen;
wire [31:0] dat_inst;
wire dat_br_eq;
wire dat_br_lt;
wire dat_br_ltu;
assign dmem_addr_offset = io_dmem_addr[1:0];
ControlPath ctrlpath (
.clk(clk),
.rst(rst),
.io_dmem_addr_offset(dmem_addr_offset),
.io_dmem_op(io_dmem_op),
.io_dmem_mask(io_dmem_mask),
.io_ctl_stall(ctl_stall),
.io_ctl_pc_sel(ctl_pc_sel),
.io_ctl_imm_sel(ctl_imm_sel),
.io_ctl_op1_sel(ctl_op1_sel),
.io_ctl_op2_sel(ctl_op2_sel),
.io_ctl_alu_sel(ctl_alu_sel),
.io_ctl_mem_signed(ctl_mem_signed),
.io_ctl_wb_sel(ctl_wb_sel),
.io_ctl_rf_wen(ctl_rf_wen),
.io_dat_inst(dat_inst),
.io_dat_br_eq(dat_br_eq),
.io_dat_br_lt(dat_br_lt),
.io_dat_br_ltu(dat_br_ltu)
);
DataPath datapath (
.clk(clk),
.rst(rst),
.io_interrupt(io_interrupt),
.io_hart_id(io_hart_id),
.io_reset_vector(io_reset_vector),
.io_imem_addr(io_imem_addr),
.io_imem_rdata(io_imem_rdata),
.io_dmem_addr(io_dmem_addr),
.io_dmem_mask(io_dmem_mask),
.io_dmem_wdata(io_dmem_wdata),
.io_dmem_rdata(io_dmem_rdata),
.io_ctl_stall(ctl_stall),
.io_ctl_pc_sel(ctl_pc_sel),
.io_ctl_imm_sel(ctl_imm_sel),
.io_ctl_op1_sel(ctl_op1_sel),
.io_ctl_op2_sel(ctl_op2_sel),
.io_ctl_alu_sel(ctl_alu_sel),
.io_ctl_mem_signed(ctl_mem_signed),
.io_ctl_wb_sel(ctl_wb_sel),
.io_ctl_rf_wen(ctl_rf_wen),
.io_dat_inst(dat_inst),
.io_dat_br_eq(dat_br_eq),
.io_dat_br_lt(dat_br_lt),
.io_dat_br_ltu(dat_br_ltu)
);
endmodule |
module RegFile (
input clk,
input [4:0] io_rd_addr,
input io_rd_wen,
input [31:0] io_rd_data,
input [4:0] io_rs1_addr,
output [31:0] io_rs1_data,
input [4:0] io_rs2_addr,
output [31:0] io_rs2_data
);
(* ram_style = "distributed" *) reg [31:0] mem[31-1:0];
always @(posedge clk) begin
if (io_rd_wen && (io_rd_addr !== 'h0)) begin
mem[io_rd_addr-1] <= io_rd_data;
end
end
assign io_rs1_data = io_rs1_addr !== 'h0 ? mem[io_rs1_addr-1] : 'h0;
assign io_rs2_data = io_rs2_addr !== 'h0 ? mem[io_rs2_addr-1] : 'h0;
endmodule |
module ControlPath (
input clk,
input rst,
input [1:0] io_dmem_addr_offset,
output [`MEM_OP_WIDTH-1:0] io_dmem_op,
output [3:0] io_dmem_mask,
// from data path
input [31:0] io_dat_inst,
// input imiss,
input io_dat_br_eq,
input io_dat_br_lt,
input io_dat_br_ltu,
// input csr_eret = Output(Bool())
// input csr_interrupt = Output(Bool())
// input inst_misaligned = Output(Bool())
// to data path
output io_ctl_stall,
// output dmiss,
output [`PC_SEL_WIDTH-1:0] io_ctl_pc_sel,
output [`IMM_SEL_WIDTH-1:0] io_ctl_imm_sel,
output io_ctl_op1_sel, // 0: rs1, 1: immediate
output io_ctl_op2_sel, // 0: rs2, 1: immediate
output [`ALU_SEL_WIDTH-1:0] io_ctl_alu_sel,
output io_ctl_mem_signed,
output [`WB_SEL_WIDTH-1:0] io_ctl_wb_sel,
output io_ctl_rf_wen
// output io_ctl_csr_cmd = Output(UInt(CSR.SZ.W))
// output io_ctl_exception = Output(Bool())
// output io_ctl_exception_cause = Output(UInt(32.W))
// output io_ctl_pc_sel_no_xept = Output(UInt(PC_4.getWidth.W)) // Use only for instuction misalignment detection
);
// extract instruction fields
wire [7:0] opcode;
wire [2:0] funct3;
wire [6:0] funct7;
wire [11:0] funct12;
assign opcode = io_dat_inst[6:0];
assign funct3 = io_dat_inst[14:12];
assign funct7 = io_dat_inst[31:25];
assign imm_i = io_dat_inst[31:20];
// instruction matching
wire opcode_is_load;
wire opcode_is_fence;
wire opcode_is_alu_i;
wire opcode_is_auipc;
wire opcode_is_alu_iw;
wire opcode_is_store;
wire opcode_is_alu_r;
wire opcode_is_lui;
wire opcode_is_alu_rw;
wire opcode_is_branch;
wire opcode_is_jalr;
wire opcode_is_jal;
wire opcode_is_sys;
wire opcode_is_type_r;
wire opcode_is_type_i;
wire opcode_is_type_s;
wire opcode_is_type_b;
wire opcode_is_type_u;
wire opcode_is_type_j;
wire opcode_is_type_z;
wire inst_is_lb;
wire inst_is_lh;
wire inst_is_lw;
// wire inst_is_ld;
wire inst_is_lbu;
wire inst_is_lhu;
// wire inst_is_lwu;
wire inst_is_fence;
wire inst_is_fence_i;
wire inst_is_addi;
wire inst_is_slli;
wire inst_is_slti;
wire inst_is_sltiu;
wire inst_is_xori;
wire inst_is_srli;
wire inst_is_srai;
wire inst_is_ori;
wire inst_is_andi;
wire inst_is_auipc;
// wire inst_is_addiw;
// wire inst_is_slliw;
// wire inst_is_srliw;
// wire inst_is_sraiw;
wire inst_is_sb;
wire inst_is_sh;
wire inst_is_sw;
// wire inst_is_sd;
wire inst_is_add;
wire inst_is_sub;
wire inst_is_sll;
wire inst_is_slt;
wire inst_is_sltu;
wire inst_is_xor;
wire inst_is_srl;
wire inst_is_sra;
wire inst_is_or;
wire inst_is_and;
wire inst_is_lui;
// wire inst_is_addw;
// wire inst_is_subw;
// wire inst_is_sllw;
// wire inst_is_srlw;
// wire inst_is_sraw;
wire inst_is_beq;
wire inst_is_bne;
wire inst_is_blt;
wire inst_is_bge;
wire inst_is_bltu;
wire inst_is_bgeu;
wire inst_is_jalr;
wire inst_is_jal;
wire inst_is_ecall;
wire inst_is_ebreak;
wire inst_is_csrrw;
wire inst_is_csrrs;
wire inst_is_csrrc;
wire inst_is_csrrwi;
wire inst_is_csrrsi;
wire inst_is_csrrci;
assign opcode_is_load = opcode === 'b0000011;
assign opcode_is_fence = opcode === 'b0001111;
assign opcode_is_alu_i = opcode === 'b0010011;
assign opcode_is_auipc = opcode === 'b0010111;
assign opcode_is_alu_iw = opcode === 'b0011011;
assign opcode_is_store = opcode === 'b0100011;
assign opcode_is_alu_r = opcode === 'b0110011;
assign opcode_is_lui = opcode === 'b0110111;
assign opcode_is_alu_rw = opcode === 'b0110011;
assign opcode_is_branch = opcode === 'b1100011;
assign opcode_is_jalr = opcode === 'b1100111;
assign opcode_is_jal = opcode === 'b1101111;
assign opcode_is_sys = opcode === 'b1110011; // csr and ecall, ebreak
assign opcode_is_type_r = opcode_is_alu_rw | opcode_is_alu_r;
assign opcode_is_type_i = opcode_is_sys | opcode_is_jalr | opcode_is_alu_iw | opcode_is_alu_i | opcode_is_fence | opcode_is_load;
assign opcode_is_type_s = opcode_is_store;
assign opcode_is_type_b = opcode_is_branch;
assign opcode_is_type_u = opcode_is_lui | opcode_is_auipc;
assign opcode_is_type_j = opcode_is_jal;
assign opcode_is_type_z = inst_is_csrrwi | inst_is_csrrsi | inst_is_csrrci;
assign inst_is_lb = opcode_is_load & (funct3 === 'b000);
assign inst_is_lh = opcode_is_load & (funct3 === 'b001);
assign inst_is_lw = opcode_is_load & (funct3 === 'b010);
// assign inst_is_ld = opcode_is_load & (funct3 === 'b011);
assign inst_is_lbu = opcode_is_load & (funct3 === 'b100);
assign inst_is_lhu = opcode_is_load & (funct3 === 'b101);
// assign inst_is_lwu = opcode_is_load & (funct3 === 'b110);
assign inst_is_fence = opcode_is_fence;
assign inst_is_fence_i= opcode_is_fence & (funct3 === 'b001);
assign inst_is_addi = opcode_is_alu_i & (funct3 === 'b000);
assign inst_is_slli = opcode_is_alu_i & (funct3 === 'b001) & (funct7 === 'b0000000);
assign inst_is_slti = opcode_is_alu_i & (funct3 === 'b010);
assign inst_is_sltiu = opcode_is_alu_i & (funct3 === 'b011);
assign inst_is_xori = opcode_is_alu_i & (funct3 === 'b100);
assign inst_is_srli = opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0000000);
assign inst_is_srai = opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0100000);
assign inst_is_ori = opcode_is_alu_i & (funct3 === 'b110);
assign inst_is_andi = opcode_is_alu_i & (funct3 === 'b111);
assign inst_is_auipc = opcode_is_auipc;
// assign inst_is_addiw = opcode_is_alu_iw & (funct3 === 'b000);
// assign inst_is_slliw = opcode_is_alu_iw & (funct3 === 'b001) & (funct7 === 'b0000000);
// assign inst_is_srliw = opcode_is_alu_iw & (funct3 === 'b101) & (funct7 === 'b0000000);
// assign inst_is_sraiw = opcode_is_alu_iw & (funct3 === 'b101) & (funct7 === 'b0100000);
assign inst_is_sb = opcode_is_store & (funct3 === 'b000);
assign inst_is_sh = opcode_is_store & (funct3 === 'b001);
assign inst_is_sw = opcode_is_store & (funct3 === 'b010);
// assign inst_is_sd = opcode_is_store & (funct3 === 'b011);
assign inst_is_add = opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0000000);
assign inst_is_sub = opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0100000);
assign inst_is_sll = opcode_is_alu_r & (funct3 === 'b001) & (funct7 === 'b0000000);
assign inst_is_slt = opcode_is_alu_r & (funct3 === 'b010) & (funct7 === 'b0000000);
assign inst_is_sltu = opcode_is_alu_r & (funct3 === 'b011) & (funct7 === 'b0000000);
assign inst_is_xor = opcode_is_alu_r & (funct3 === 'b100) & (funct7 === 'b0000000);
assign inst_is_srl = opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0000000);
assign inst_is_sra = opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0100000);
assign inst_is_or = opcode_is_alu_r & (funct3 === 'b110) & (funct7 === 'b0000000);
assign inst_is_and = opcode_is_alu_r & (funct3 === 'b111) & (funct7 === 'b0000000);
assign inst_is_lui = opcode_is_lui;
// assign inst_is_addw = opcode_is_alu_rw & (funct3 === 'b000) & (funct7 === 'b0000000);
// assign inst_is_subw = opcode_is_alu_rw & (funct3 === 'b000) & (funct7 === 'b0100000);
// assign inst_is_sllw = opcode_is_alu_rw & (funct3 === 'b001) & (funct7 === 'b0000000);
// assign inst_is_srlw = opcode_is_alu_rw & (funct3 === 'b101) & (funct7 === 'b0000000);
// assign inst_is_sraw = opcode_is_alu_rw & (funct3 === 'b101) & (funct7 === 'b0100000);
assign inst_is_beq = opcode_is_branch & (funct3 === 'b000);
assign inst_is_bne = opcode_is_branch & (funct3 === 'b001);
assign inst_is_blt = opcode_is_branch & (funct3 === 'b100);
assign inst_is_bge = opcode_is_branch & (funct3 === 'b101);
assign inst_is_bltu = opcode_is_branch & (funct3 === 'b110);
assign inst_is_bgeu = opcode_is_branch & (funct3 === 'b111);
assign inst_is_jalr = opcode_is_jalr;
assign inst_is_jal = opcode_is_jal;
assign inst_is_ecall = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000000000000);
assign inst_is_ebreak = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000000000001);
assign inst_is_uret = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000000000010);
// assign inst_is_sret = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000100000010);
// assign inst_is_hret = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b001000000010);
assign inst_is_mret = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b001100000010);
assign inst_is_sfence_vm = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000100000100);
assign inst_is_wfi = opcode_is_sys & (funct3 === 'b000) & (funct12 === 'b000100000101);
assign inst_is_csrrw = opcode_is_sys & (funct3 === 'b001) & (funct7 === 'b0000000);
assign inst_is_csrrs = opcode_is_sys & (funct3 === 'b010) & (funct7 === 'b0000000);
assign inst_is_csrrc = opcode_is_sys & (funct3 === 'b011) & (funct7 === 'b0000000);
assign inst_is_csrrwi = opcode_is_sys & (funct3 === 'b101) & (funct7 === 'b0000000);
assign inst_is_csrrsi = opcode_is_sys & (funct3 === 'b110) & (funct7 === 'b0000000);
assign inst_is_csrrci = opcode_is_sys & (funct3 === 'b111) & (funct7 === 'b0000000);
wire is_branch_hit;
assign is_branch_hit = ((inst_is_beq && io_dat_br_eq)
|| (inst_is_bne && !io_dat_br_eq)
|| (inst_is_blt && io_dat_br_lt)
|| (inst_is_bge && !io_dat_br_lt)
|| (inst_is_bltu && io_dat_br_ltu)
|| (inst_is_bgeu && !io_dat_br_ltu)
);
// control signals
// assign io_ctl_stall = io_dat_imiss || io_ctl_dmiss;
assign io_ctl_stall = 'b0;
assign io_ctl_pc_sel = (
// (io_ctl_exception || io_dat_csr_eret) ? `PC_SEL_EXC :
// io_dat_csr_interrupt ? `PC_SEL_EXC :
opcode_is_jal ? `PC_SEL_JAL :
opcode_is_jalr ? `PC_SEL_JALR :
(opcode_is_branch && is_branch_hit) ? `PC_SEL_BR :
`PC_SEL_PC4
);
assign io_ctl_imm_sel = (
opcode_is_type_r ? `IMM_SEL_R :
opcode_is_type_i ? `IMM_SEL_I :
opcode_is_type_s ? `IMM_SEL_S :
opcode_is_type_b ? `IMM_SEL_B :
opcode_is_type_u ? `IMM_SEL_U :
opcode_is_type_j ? `IMM_SEL_J :
opcode_is_type_z ? `IMM_SEL_Z :
`IMM_SEL_R
);
assign io_ctl_op1_sel = (opcode_is_auipc || opcode_is_type_j || opcode_is_type_b) ? `OP1_SEL_PC : `OP1_SEL_RS1;
assign io_ctl_op2_sel = opcode_is_type_r ? `OP2_SEL_RS2 : `OP2_SEL_IMM;
assign io_ctl_alu_sel = (
inst_is_add ? `ALU_SEL_ADD :
inst_is_sub ? `ALU_SEL_SUB :
(inst_is_sll || inst_is_slli) ? `ALU_SEL_SLL :
(inst_is_srl || inst_is_srli) ? `ALU_SEL_SRL :
(inst_is_sra || inst_is_srai) ? `ALU_SEL_SRA :
(inst_is_and || inst_is_andi) ? `ALU_SEL_AND :
(inst_is_or || inst_is_ori) ? `ALU_SEL_OR :
(inst_is_xor || inst_is_xori) ? `ALU_SEL_XOR :
(inst_is_slt || inst_is_slti) ? `ALU_SEL_SLT :
(inst_is_sltu || inst_is_sltiu) ? `ALU_SEL_SLTU :
(inst_is_lui || opcode_is_sys) ? `ALU_SEL_COPYB :
`ALU_SEL_ADD
);
assign io_dmem_op = (
opcode_is_load ? `MEM_OP_READ :
opcode_is_store ? `MEM_OP_WRITE :
`MEM_OP_READ
);
assign io_dmem_mask = (
(inst_is_sw || inst_is_lw) ? 4'b1111 :
((inst_is_sh || inst_is_lh || inst_is_lhu) && (io_dmem_addr_offset == 'b00)) ? 4'b0011 :
// ((inst_is_sh || inst_is_lh || inst_is_lhu) && (io_dmem_addr_offset == 'b01)) ? 4'b0110 :
((inst_is_sh || inst_is_lh || inst_is_lhu) && (io_dmem_addr_offset == 'b10)) ? 4'b1100 :
// ((inst_is_sh || inst_is_lh || inst_is_lhu) && (io_dmem_addr_offset == 'b11)) ? 4'b1001 :
((inst_is_sb || inst_is_lb || inst_is_lbu) && (io_dmem_addr_offset == 'b00)) ? 4'b0001 :
((inst_is_sb || inst_is_lb || inst_is_lbu) && (io_dmem_addr_offset == 'b01)) ? 4'b0010 :
((inst_is_sb || inst_is_lb || inst_is_lbu) && (io_dmem_addr_offset == 'b10)) ? 4'b0100 :
((inst_is_sb || inst_is_lb || inst_is_lbu) && (io_dmem_addr_offset == 'b11)) ? 4'b1000 :
4'b0000
);
assign io_ctl_mem_signed = inst_is_lw || inst_is_lh || inst_is_lb;
assign io_ctl_wb_sel = (
opcode_is_load ? `WB_SEL_MEM :
(opcode_is_jal || opcode_is_jalr) ? `WB_SEL_PC4 :
opcode_is_sys ? `WB_SEL_CSR :
`WB_SEL_ALU
);
assign io_ctl_rf_wen = (
opcode_is_load ? `WEN_SEL_ENABLE :
(inst_is_auipc || inst_is_lui) ? `WEN_SEL_ENABLE :
(opcode_is_alu_i || opcode_is_alu_r) ? `WEN_SEL_ENABLE :
// (opcode_is_alu_iw || opcode_is_alu_rw) ? `WEN_SEL_ENABLE :
(opcode_is_jal || opcode_is_jalr) ? `WEN_SEL_ENABLE :
(inst_is_csrrc || inst_is_csrrs || inst_is_csrrw || inst_is_csrrci || inst_is_csrrsi || inst_is_csrrwi) ? `WEN_SEL_ENABLE :
`WEN_SEL_DISABLE
);
endmodule |
module Top (
input CLK100MHZ,
input ck_rst,
output [3:0] led
);
wire clk;
wire rst;
assign rst = ~ck_rst;
clk_wiz_0 clk_wiz_0 (
.clk_out1(clk),
.reset(rst),
.clk_in1(CLK100MHZ)
);
Tile tile (
.clk(clk),
.rst(rst),
// .io_interrupt(io_interrupt),
// .io_hart_id(io_hart_id),
// .io_reset_vector(io_reset_vector),
.led(led)
);
endmodule |
module Register (q, d, clk);
parameter N = 1;
input clk;
output reg [N-1:0] q;
input [N-1:0] d;
initial q = {N{1'b0}};
always @(posedge clk)
q <= d;
endmodule // REGISTER |
module Register_CE (q, d, ce, clk);
parameter N = 1;
input clk;
output reg [N-1:0] q;
input [N-1:0] d;
input ce;
initial q = {N{1'b0}};
always @(posedge clk)
if (ce) q <= d;
endmodule // REGISTER_CE |
module Register_R (q, d, rst, clk);
parameter N = 1;
parameter INIT = {N{1'b0}};
input clk;
input rst;
output reg [N-1:0] q;
input [N-1:0] d;
initial q = INIT;
always @(posedge clk)
if (rst) q <= INIT;
else q <= d;
endmodule // REGISTER_R |
module Register_R_CE (q, d, rst, ce, clk);
parameter N = 1;
parameter INIT = {N{1'b0}};
input clk;
input rst;
output reg [N-1:0] q;
input [N-1:0] d;
input ce;
initial q = INIT;
always @(posedge clk)
if (rst) q <= INIT;
else if (ce) q <= d;
endmodule // REGISTER_R_CE |
module ROM #(
parameter DEPTH = 16384
)(
input clk,
input [11:0] addr,
output [31:0] dout
);
reg [31:0] mem [DEPTH-1:0];
assign dout = mem[addr];
initial begin
$readmemh("/scratch/vivado_projects/BAD-RISCV-CPU/BA20X-Verilog/software/firmware.mem", mem);
end
endmodule |
module RAM_Artix7 (
input clk,
input rst,
input [31:0] io_imem_addr,
output [31:0] io_imem_rdata,
input [31:0] io_dmem_addr,
input io_dmem_type,
input [31:0] io_dmem_wdata,
input [3:0] io_dmem_wmask,
output [31:0] io_dmem_rdata
);
wire [31:0] DOA;
wire [31:0] DOB;
wire [9:0] ADDRA;
wire [9:0] ADDRB;
wire CLKA;
wire CLKB;
wire [31:0] DIA;
wire [31:0] DIB;
wire ENA;
wire ENB;
wire RSTA;
wire RSTB;
wire [3:0] WEA;
wire [3:0] WEB;
assign io_imem_rdata = DOA;
assign io_dmem_rdata = DOB;
assign ADDRA = io_imem_addr[11:2];
assign ADDRB = io_dmem_addr[11:2];
assign CLKA = clk;
assign CLKB = clk;
assign DIA = 'h0;
assign DIB = io_dmem_wdata;
assign RSTA = rst;
assign RSTB = rst;
assign WEA = 'h0;
assign WEB = io_dmem_wmask;
// BRAM_TDP_MACRO: True Dual Port RAM
// Artix-7
// Xilinx HDL Language Template, version 2023.2
//////////////////////////////////////////////////////////////////////////
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
// ===============|===========|===========|===============|=============//
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
//////////////////////////////////////////////////////////////////////////
BRAM_TDP_MACRO #(
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
.DEVICE("7SERIES"), // Target device: "7SERIES"
.DOA_REG(0), // Optional port A output register (0 or 1)
.DOB_REG(0), // Optional port B output register (0 or 1)
.INIT_A(36'h0000000), // Initial values on port A output port
.INIT_B(36'h00000000), // Initial values on port B output port
.INIT_FILE("NONE"),
.READ_WIDTH_A(32), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.READ_WIDTH_B(32), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE"
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_WIDTH_A(32), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.WRITE_WIDTH_B(32), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INIT_xx are valid when configured as 36Kb
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are valid when configured as 36Kb
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) BRAM_TDP_MACRO_inst (
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
.CLKA(CLKA), // 1-bit input port-A clock
.CLKB(CLKB), // 1-bit input port-B clock
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
.ENA('b1), // 1-bit input port-A enable
.ENB('b1), // 1-bit input port-B enable
.REGCEA('b1), // 1-bit input port-A output register enable
.REGCEB('b1), // 1-bit input port-B output register enable
.RSTA(RSTA), // 1-bit input port-A reset
.RSTB(RSTB), // 1-bit input port-B reset
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
);
// End of BRAM_TDP_MACRO_inst instantiation
endmodule |
module RAM_Simple #(
parameter DEPTH = 16384
)(
input clk,
input [13:0] addr,
input op,
input [3:0] mask,
input [31:0] wdata,
output [31:0] rdata
);
// See page 133 of the Vivado Synthesis Guide for the template
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf
reg [31:0] mem [DEPTH-1:0];
assign rdata = mem[addr];
always @(posedge clk) begin
if (op == 'b1) begin
mem[addr] <= (
(mask == 'b1111) ? wdata :
(mask == 'b0011) ? {mem[addr][31:16], wdata[15:0]} :
(mask == 'b1100) ? {wdata[31:16], mem[addr][15:0]} :
(mask == 'b0001) ? {mem[addr][31:8], wdata[7:0]} :
(mask == 'b0010) ? {mem[addr][31:16], wdata[15:8], mem[addr][7:0]} :
(mask == 'b0100) ? {mem[addr][31:24], wdata[23:16], mem[addr][15:0]} :
(mask == 'b1000) ? {wdata[31:24], mem[addr][23:0]} :
mem[addr]
);
end
end
endmodule |
module ram_true_dual #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 5, parameter DISTR = 0) (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
parameter DEPTH = 2**ADDR_WIDTH;
input clka,clkb,ena,enb,wea,web;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia,dib;
output [DATA_WIDTH-1:0] doa,dob;
reg [DATA_WIDTH-1:0] doa,dob;
generate
if (DISTR) begin : distributed_ram
(* ram_style = "distributed" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb)
begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
end
else begin : block_ram
integer i;
reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
always @(posedge clka)
begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb)
begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
end
endgenerate
endmodule |
module brdg_partial_sequencer (
input clk ,
input rst_n ,
input partial_en ,
input [63:0] strobe ,
input strobe_valid ,
output reg [02:0] partial_len ,
output reg [05:0] partial_ea ,
output partial_valid ,
output reg [04:0] partial_cnt ,
output partial_done
);
reg [08:0] cstate, nstate;
reg [63:0] sub_strb;
wire part_cmd_match;
wire part_all_nil;
reg [05:0] part_cmd_cyc;
wire [63:0] partial_32B_done_mask;
wire [63:0] partial_16B_done_mask;
wire [63:0] partial_8B_done_mask;
wire [63:0] partial_4B_done_mask;
wire [63:0] partial_2B_done_mask;
wire [63:0] partial_1B_done_mask;
reg partial_valid_pre1;
reg partial_valid_pre2;
reg partial_valid_pending;
// states
parameter IDLE = 9'h001,
CHK_PART_XB = 9'h002,
WR_CMD_XB = 9'h004,
WR_VLD_XB = 9'h008,
WR_RSP_XB = 9'h010,
CYC_UPDATE = 9'h020,
DONE = 9'h040,
RETRY = 9'h080,
FAILED = 9'h100;
//-----------------------------------------------------------------------------------------------------------------
// ALL-ONES SECTION DECODE
// * Filter out all-ones in 2's power aligned sections of the strobe signal.
// * As long as the decoded signal is not all-zero, partial write/read can be done with corresponding partial length.
// e.g. if m_32B = 2'b0; m_16B = 4'b0; m_8B = 8'd7; m_4B = 16'd0; m_2B = 32'h0001_0fff; m_1B = ...., the next
// partial write/read length would be 8B.
//-----------------------------------------------------------------------------------------------------------------
wire[63:00] m_1B;
wire[31:00] m_2B;
wire[15:00] m_4B;
wire[07:00] m_8B;
wire[03:00] m_16B;
wire[01:00] m_32B;
genvar i;
generate
for(i = 0; i < 64; i = i+1)
begin : gen_all_ones
assign m_1B[i] = sub_strb[i];
if (i%2 == 0) assign m_2B[(i/2)] = &(sub_strb[i+1:i] & 2'h3) ;//: m_2B[(i/2)] ;
if (i%4 == 0) assign m_4B[(i/4)] = &(sub_strb[i+3:i] & 4'hF) ;//: m_4B[(i/4)] ;
if (i%8 == 0) assign m_8B[(i/8)] = &(sub_strb[i+7:i] & 8'hFF) ;//: m_8B[(i/8)] ;
if (i%16 == 0) assign m_16B[(i/16)] = &(sub_strb[i+15:i] & 16'hFFFF) ;//: m_16B[(i/16)] ;
if (i%32 == 0) assign m_32B[(i/32)] = &(sub_strb[i+31:i] & 32'hFFFF_FFFF) ;//: m_32B[(i/32)] ;
end
endgenerate
wire m_32B_all_1 = |m_32B;
wire m_16B_all_1 = |m_16B;
wire m_8B_all_1 = |m_8B;
wire m_4B_all_1 = |m_4B;
wire m_2B_all_1 = |m_2B;
wire m_1B_all_1 = |m_1B;
wire[5:0] strb_struct = {
m_32B_all_1,
m_16B_all_1,
m_8B_all_1 ,
m_4B_all_1 ,
m_2B_all_1 ,
m_1B_all_1
};
//-----------------------------------------------------------------------------------------------------------------
// STATEMACHINE for partial command sequencing
// * Each 2's power aligned subsection in strobe is checked.
// * An arbitrary strobe is divided into multiple partial write/read processes.
// * Command with larger width comes out first.
// 32B -> 16B -> 8B (-> 8B...) -> 4B (-> 4B...) -> 2B (-> 2B) -> 1B (-> 1B...)
//-----------------------------------------------------------------------------------------------------------------
always@(posedge clk or negedge rst_n)
if(~rst_n)
cstate <= IDLE;
else
cstate <= nstate;
always@(*)
case(cstate)
IDLE :
if(strobe_valid)
nstate = CHK_PART_XB;
else
nstate = IDLE;
// generate 32B to 1B partial command
CHK_PART_XB :
if(part_cmd_match)
nstate = WR_CMD_XB;
else
nstate = CYC_UPDATE;
WR_CMD_XB :
nstate = WR_VLD_XB;
WR_VLD_XB :
if(partial_en) // wait for enable to continue with the command sending
nstate = CHK_PART_XB;
else
nstate = WR_VLD_XB;
CYC_UPDATE :
if(part_cmd_cyc[0] || part_all_nil)
nstate = DONE;
else
nstate = CHK_PART_XB;
// finalizing
DONE :
if(partial_en) // wait for enable to continue with finishing
nstate = IDLE;
else
nstate = DONE;
default :
nstate = IDLE;
endcase
//---- cycling shift register that indicates bytes number ----
// bit5: 32B
// bit4: 16B
// bit3: 8B
// bit2: 4B
// bit1: 2B
// bit0: 1B
always@(posedge clk or negedge rst_n)
if(~rst_n)
part_cmd_cyc <= 6'b100000;
else if(cstate == IDLE)
part_cmd_cyc <= 6'b100000;
else if(cstate == CYC_UPDATE)
part_cmd_cyc <= (part_cmd_cyc >> 1);
//---- match each byte number to corresponding cycling bit ----
assign part_cmd_match = |(part_cmd_cyc & strb_struct);
//---- rest of the part is all zero ----
assign part_all_nil = ~|(sub_strb);
//-----------------------------------------------------------------------------------------------------------------
//
// SUB-STROBE UPDATE
//
// * Partial length with each command is organized in such order that data in larger section comes first; and data
// in the furthest right section comes first.
// e.g. if m_32B = 2'b0; m_16B = 4'b0; m_8B = 8'b0000_1010; m_4B = 16'd0; m_2B = 32'h0001_f0f0; m_1B = ...., the next
// partial write/read data is in the section pointed by m_8B[1], i.e. data[15:8]; and then the next one is m_8B[3].
//
// * Strobe signal is updated after each partial command issue, the last issued section in strobe is cleared out.
// Taking the above example, after section m_8B[1] is issued, strobe[15:8]=0, it turns out m_8B = 8'b0000_1000.
//
// Steps
// 1) SINGLE OUT DECODE
// Find the first all-ones section to the right and leave others zero.
// 2) EXPAND BITS
// Expand the first 2's power aligned section on the right so as to mask the current strobe section ----
// 3) MASK strobe with the expanded decode to clean up the required setion
//-----------------------------------------------------------------------------------------------------------------
//---- single out the far right bit ---------------------------------------------------------------------
// True table: (e.g. mapping m_8B to s_8B)
// m_8B s_8B
// xxxxxxx1 00000001
// xxxxxx10 00000010
// xxxxx100 00000100
// xxxx1000 00001000
// xxx10000 00010000
// xx100000 00100000
// x1000000 01000000
// 10000000 10000000
//
// Rule:
// if r=0, s_xB[r] = m_xB[r]
// else s_xB[r] = m_xB[r]&~(|m_xB[r-1:0]) // when m_xB[r] is 1, s_xB[r] is 1 only when m_xB[r-1:0]=0.
//-------------------------------------------------------------------------------------------------------
wire[63:00] so_1B;
wire[31:00] so_2B;
wire[15:00] so_4B;
wire[07:00] so_8B;
wire[03:00] so_16B;
wire[01:00] so_32B;
reg [63:00] s_1B;
reg [31:00] s_2B;
reg [15:00] s_4B;
reg [07:00] s_8B;
reg [03:00] s_16B;
reg [01:00] s_32B;
genvar j;
generate
for(j = 0; j < 64; j = j+1)
begin : gen_single_one
if(j == 0)
begin
assign so_1B[j] = m_1B[j];
assign so_2B[j] = m_2B[j];
assign so_4B[j] = m_4B[j];
assign so_8B[j] = m_8B[j];
assign so_16B[j] = m_16B[j];
assign so_32B[j] = m_32B[j];
end
else
begin
assign so_1B[j] = m_1B[j] & ~(|m_1B[j-1:0]);
if(j > 1) assign so_2B[j/2] = m_2B[j/2] & ~(|m_2B[j/2-1:0]);
if(j > 3) assign so_4B[j/4] = m_4B[j/4] & ~(|m_4B[j/4-1:0]);
if(j > 7) assign so_8B[j/8] = m_8B[j/8] & ~(|m_8B[j/8-1:0]);
if(j > 15) assign so_16B[j/16] = m_16B[j/16] & ~(|m_16B[j/16-1:0]);
if(j > 31) assign so_32B[j/32] = m_32B[j/32] & ~(|m_32B[j/32-1:0]);
end
end
endgenerate
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
s_1B <= 64'd0;
s_2B <= 32'd0;
s_4B <= 16'd0;
s_8B <= 8'd0;
s_16B <= 4'd0;
s_32B <= 2'd0;
end
else
begin
s_1B <= so_1B ;
s_2B <= so_2B ;
s_4B <= so_4B ;
s_8B <= so_8B ;
s_16B <= so_16B;
s_32B <= so_32B;
end
//---- expand the singled out decode to 64b -------------------------------------------------------------------
// e.g. s_4B : 0____0____0____0____0____0____0____0____1____0____0____0____0____0____0____0
// partial_4B_done_mask : 0000_0000_0000_0000_0000_0000_0000_0000_1111_0000_0000_0000_0000_0000_0000_0000
//-------------------------------------------------------------------------------------------------------------
assign partial_32B_done_mask = {{32{s_32B[1]}},{32{s_32B[0]}}};
assign partial_16B_done_mask = {{16{s_16B[3]}},{16{s_16B[2]}},{16{s_16B[1]}},{16{s_16B[0]}}};
assign partial_8B_done_mask = {{8{s_8B[07]}}, {8{s_8B[06]}}, {8{s_8B[05]}}, {8{s_8B[04]}}, {8{s_8B[03]}}, {8{s_8B[02]}}, {8{s_8B[01]}}, {8{s_8B[00]}}};
assign partial_4B_done_mask = {{4{s_4B[15]}}, {4{s_4B[14]}}, {4{s_4B[13]}}, {4{s_4B[12]}}, {4{s_4B[11]}}, {4{s_4B[10]}}, {4{s_4B[09]}}, {4{s_4B[08]}},
{4{s_4B[07]}}, {4{s_4B[06]}}, {4{s_4B[05]}}, {4{s_4B[04]}}, {4{s_4B[03]}}, {4{s_4B[02]}}, {4{s_4B[01]}}, {4{s_4B[00]}}};
assign partial_2B_done_mask = {{2{s_2B[31]}}, {2{s_2B[30]}}, {2{s_2B[29]}}, {2{s_2B[28]}}, {2{s_2B[27]}}, {2{s_2B[26]}}, {2{s_2B[25]}}, {2{s_2B[24]}},
{2{s_2B[23]}}, {2{s_2B[22]}}, {2{s_2B[21]}}, {2{s_2B[20]}}, {2{s_2B[19]}}, {2{s_2B[18]}}, {2{s_2B[17]}}, {2{s_2B[16]}},
{2{s_2B[15]}}, {2{s_2B[14]}}, {2{s_2B[13]}}, {2{s_2B[12]}}, {2{s_2B[11]}}, {2{s_2B[10]}}, {2{s_2B[09]}}, {2{s_2B[08]}},
{2{s_2B[07]}}, {2{s_2B[06]}}, {2{s_2B[05]}}, {2{s_2B[04]}}, {2{s_2B[03]}}, {2{s_2B[02]}}, {2{s_2B[01]}}, {2{s_2B[00]}}};
assign partial_1B_done_mask = s_1B;
//---- update strobe ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
sub_strb <= 64'd0;
else if(strobe_valid)
sub_strb <= strobe;
else if(cstate == WR_CMD_XB)
case(part_cmd_cyc)
6'b100000 : sub_strb <= sub_strb & ~partial_32B_done_mask;
6'b010000 : sub_strb <= sub_strb & ~partial_16B_done_mask;
6'b001000 : sub_strb <= sub_strb & ~partial_8B_done_mask;
6'b000100 : sub_strb <= sub_strb & ~partial_4B_done_mask;
6'b000010 : sub_strb <= sub_strb & ~partial_2B_done_mask;
6'b000001 : sub_strb <= sub_strb & ~partial_1B_done_mask;
default:;
endcase
//-----------------------------------------------------------------------------------------------------------------
//
// EFFECTIVE ADDRESS
//
// * Calculate lower 6 bits effective address that matches the setion to be issued for partial writing.
// * Use simplified gate-circuit instead of if-else for clarity.
//
// e.g. if partial length is 8B
//
// True Table:
// s_8B : b7 b6 b5 b4 b3 b2 b1 b0 partial_ea: b2 b1 b0
// 0 0 0 0 0 0 0 1 0 0 0
// 0 0 0 0 0 0 1 0 0 0 1
// 0 0 0 0 0 1 0 0 0 1 0
// 0 0 0 0 1 0 0 0 0 1 1
// 0 0 0 1 0 0 0 0 1 0 0
// 0 0 1 0 0 0 0 0 1 0 1
// 0 1 0 0 0 0 0 0 1 1 0
// 1 0 0 0 0 0 0 0 1 1 1
// Circuit:
// partial_ea[2] = s_8B[4] | s_8B[5] | s_8B[6] | s_8B[7] // |X|X|X|X|O|O|O|O|
// partial_ea[1] = s_8B[2] | s_8B[3] | s_8B[6] | s_8B[7] // |X|X|O|O|X|X|O|O|
// partial_ea[0] = s_8B[1] | s_8B[3] | s_8B[5] | s_8B[7] // |X|O|X|O|X|O|X|O|
//
//-----------------------------------------------------------------------------------------------------------------
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_ea <= 6'd0;
else if(cstate == WR_CMD_XB)
case(part_cmd_cyc)
6'b100000 : partial_ea <= {~s_32B[0], //b5
5'd0};
6'b010000 : partial_ea <= {(s_16B[3]|s_16B[2]), //b5
(s_16B[3]|s_16B[1]), //b4
4'd0};
6'b001000 : partial_ea <= {(s_8B[7]|s_8B[6]|s_8B[5]|s_8B[4]), //b5
(s_8B[7]|s_8B[6]|s_8B[3]|s_8B[2]), //b4
(s_8B[7]|s_8B[5]|s_8B[3]|s_8B[1]), //b3
3'd0};
6'b000100 : partial_ea <= {|s_4B[15:8], //b5
(|s_4B[15:12])|(|s_4B[7:4]), //b4
(s_4B[15]|s_4B[14]|s_4B[11]|s_4B[10]|s_4B[7]|s_4B[6]|s_4B[3]|s_4B[2]), //b3
(s_4B[15]|s_4B[13]|s_4B[11]|s_4B[9]|s_4B[7]|s_4B[5]|s_4B[3]|s_4B[1]), //b2
2'd0};
6'b000010 : partial_ea <= {|s_2B[31:16], //b5
(|s_2B[31:24])|(|s_2B[15:8]), //b4
(|s_2B[31:28])|(|s_2B[23:20])|(|s_2B[15:12])|(|s_2B[7:4]), //b3
(|s_2B[31:30])|(|s_2B[27:26])|(|s_2B[23:22])|(|s_2B[19:18])|
(|s_2B[15:14])|(|s_2B[11:10])|(|s_2B[7:6])|(|s_2B[3:2]), //b2
(s_2B[31]|s_2B[29]|s_2B[27]|s_2B[25]|s_2B[23]|s_2B[21]|s_2B[19]|s_2B[17]|
s_2B[15]|s_2B[13]|s_2B[11]|s_2B[9]|s_2B[7]|s_2B[5]|s_2B[3]|s_2B[1]), //b1
1'd0};
6'b000001 : partial_ea <= {|s_1B[63:32], //b5
(|s_1B[63:48])|(|s_1B[31:16]), //b4
(|s_1B[63:56])|(|s_1B[47:40])|(|s_1B[31:24])|(|s_1B[15:8]), //b3
(|s_1B[63:60])|(|s_1B[55:52])|(|s_1B[47:44])|(|s_1B[39:36])|
(|s_1B[31:28])|(|s_1B[23:20])|(|s_1B[15:12])|(|s_1B[7:4]), //b2
(|s_1B[63:62])|(|s_1B[59:58])|(|s_1B[55:54])|(|s_1B[51:50])|
(|s_1B[47:46])|(|s_1B[43:42])|(|s_1B[39:38])|(|s_1B[35:34])|
(|s_1B[31:30])|(|s_1B[27:26])|(|s_1B[23:22])|(|s_1B[19:18])|
(|s_1B[15:14])|(|s_1B[11:10])|(|s_1B[7:6])|(|s_1B[3:2]), //b1
(s_1B[63]|s_1B[61]|s_1B[59]|s_1B[57]|s_1B[55]|s_1B[53]|s_1B[51]|s_1B[49]|
s_1B[47]|s_1B[45]|s_1B[43]|s_1B[41]|s_1B[39]|s_1B[37]|s_1B[35]|s_1B[33]|
s_1B[31]|s_1B[29]|s_1B[27]|s_1B[25]|s_1B[23]|s_1B[21]|s_1B[19]|s_1B[17]|
s_1B[15]|s_1B[13]|s_1B[11]|s_1B[9]|s_1B[7]|s_1B[5]|s_1B[3]|s_1B[1])}; //b0
default:;
endcase
//---- partial length ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_len <= 3'd0;
else if(cstate == WR_CMD_XB)
case(part_cmd_cyc)
6'b100000 : partial_len <= 3'b101;
6'b010000 : partial_len <= 3'b100;
6'b001000 : partial_len <= 3'b011;
6'b000100 : partial_len <= 3'b010;
6'b000010 : partial_len <= 3'b001;
6'b000001 : partial_len <= 3'b000;
default:;
endcase
//---- partial effective address and length valid ----
// sync twice to align with partial_done if any
// make sure partial_valid align with partial_en, and deasserts when partial_en is 0
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
partial_valid_pre1 <= 1'b0;
partial_valid_pre2 <= 1'b0;
end
else
begin
partial_valid_pre1 <= (cstate == WR_VLD_XB) && partial_en;
partial_valid_pre2 <= partial_valid_pre1;
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_valid_pending <= 1'b0;
else if(partial_valid_pre1)
partial_valid_pending <= 1'b1;
else if(partial_en)
partial_valid_pending <= 1'b0;
assign partial_valid = partial_valid_pending && partial_en;
//---- counter for a single sequence of partial commands, used in afutag to distinguish individual partial command ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_cnt <= 5'd0;
else if(cstate == IDLE)
partial_cnt <= 5'd0;
else if(partial_valid)
partial_cnt <= partial_cnt + 5'd1;
//---- current partial sequencing is done, synced with partial_valid ----
assign partial_done = (cstate == CYC_UPDATE) && (part_cmd_cyc[0] || part_all_nil);
// psl default clock = (posedge clk);
//==== PSL COVERAGE ==============================================================================
// psl PARTIAL_1ST_32B : cover {strobe_valid; (m_32B_all_1)};
// psl PARTIAL_1ST_16B : cover {strobe_valid; (~m_32B_all_1 && m_16B_all_1)};
// psl PARTIAL_1ST_08B : cover {strobe_valid; (~m_32B_all_1 && ~m_16B_all_1 && m_8B_all_1)};
// psl PARTIAL_1ST_04B : cover {strobe_valid; (~m_32B_all_1 && ~m_16B_all_1 && ~m_8B_all_1 && m_4B_all_1)};
// psl PARTIAL_1ST_02B : cover {strobe_valid; (~m_32B_all_1 && ~m_16B_all_1 && ~m_8B_all_1 && ~m_4B_all_1 && m_2B_all_1)};
// psl PARTIAL_1ST_01B : cover {strobe_valid; (~m_32B_all_1 && ~m_16B_all_1 && ~m_8B_all_1 && ~m_4B_all_1 && ~m_2B_all_1 && m_1B_all_1)};
//==== PSL COVERAGE ==============================================================================
//==== PSL ASSERTION ==============================================================================
// psl PARTIAL_CNT_OVERFLOW : assert never (partial_valid && (&partial_cnt)) report "decomposed partial commands number exceeds partial counter limit!";
//==== PSL ASSERTION ==============================================================================
endmodule |
module brdg_axi_slave_cmd_fifo (
clk,
rst_n,
axi_id,
axi_addr,
axi_len,
axi_size,
axi_burst,
axi_user,
cf_id,
cf_addr,
cf_len,
cf_size,
cf_burst,
cf_user,
cf_wr_en,
cf_almost_full,
cf_full,
cf_empty,
cf_rd_en
);
input clk;
input rst_n;
input [`IDW-1:0] axi_id;
input [63:0] axi_addr;
input [7:0] axi_len;
input [2:0] axi_size;
input [1:0] axi_burst;
input [`CTXW-1:0] axi_user;
output [`IDW-1:0] cf_id;
output [63:0] cf_addr;
output [7:0] cf_len;
output [2:0] cf_size;
output [1:0] cf_burst;
output [`CTXW-1:0] cf_user;
input cf_wr_en; //There is a valid cmd
output cf_almost_full;
output cf_full;
output cf_empty;
input cf_rd_en;
wire [`IDW + 64 + 8 + 3 + 2 + `CTXW - 1:0] din;
wire [`IDW + 64 + 8 + 3 + 2 + `CTXW - 1:0] dout;
assign din = {axi_id, axi_len, axi_size, axi_burst, axi_user, axi_addr};
assign {cf_id, cf_len, cf_size, cf_burst, cf_user, cf_addr} = dout;
//`IDW=5, `CTXW=9
//5 + 64 + 8 + 3 + 2 + 9 = 91
//axicf_sync_fifo_16_91i91o axicfifo(
fifo_sync # (.DATA_WIDTH (91),
.ADDR_WIDTH (4),
.FWFT (1)
) axicfifo
(
.clk (clk ),
.rst_n (rst_n ),
.din (din ),
.wr_en (cf_wr_en ),
.rd_en (cf_rd_en ),
.dout (dout ),
.valid ( ),
.full (cf_full ),
.almost_full(cf_almost_full ),
.almost_empty ( ),
.count ( ),
.empty (cf_empty )
);
endmodule |
module brdg_data_bridge
#(
parameter MODE = 0 //0: write; 1: read
)
(
input clk ,
input rst_n ,
//---- buffer empty indicatior -------
output buf_empty ,
//---- local bus ---------------------
//--- address ---
input lcl_addr_idle ,
output reg lcl_addr_ready ,
input lcl_addr_valid ,
input [0063:0] lcl_addr_ea ,
input lcl_addr_ctx_valid ,
input [`CTXW-1:0]lcl_addr_ctx ,
input [`IDW-1:0] lcl_addr_axi_id ,
input lcl_addr_first ,
input lcl_addr_last ,
input [0127:0] lcl_addr_be ,
//--- data ---
input [1023:0] lcl_data_in ,
output [1023:0] lcl_data_out ,
output lcl_data_out_last ,
output [`CTXW-1:0]lcl_data_ctx ,
//--- response and data out ---
`ifndef ENABLE_ODMA
input lcl_resp_ready ,
`else
input [0031:0] lcl_resp_ready ,
input [0031:0] lcl_resp_ready_hint ,
`endif
output lcl_resp_valid ,
output [`IDW-1:0] lcl_resp_axi_id ,
output lcl_resp_code ,
output [`CTXW-1:0]lcl_resp_ctx ,
//---- command encoder ---------------
input dma_cmd_ready ,
output reg dma_cmd_valid ,
output reg [1023:0] dma_cmd_data ,
output reg [0127:0] dma_cmd_be ,
output reg [0063:0] dma_cmd_ea ,
output reg [`TAGW-1:0]dma_cmd_tag ,
output reg [`CTXW-1:0]dma_cmd_ctx ,
//---- response decoder --------------
input dma_resp_valid ,
input [1023:0] dma_resp_data ,
input [`TAGW-1:0]dma_resp_tag ,
input [0001:0] dma_resp_pos ,
input [0002:0] dma_resp_code ,
//---- control and status ------------
input debug_cnt_clear ,
input [0031:0] debug_axi_cmd_idle_lim,
input [0031:0] debug_axi_rsp_idle_lim,
output reg debug_axi_cmd_idle ,
output reg debug_axi_rsp_idle ,
output reg [0031:0] debug_axi_cnt_cmd ,
output reg [0031:0] debug_axi_cnt_rsp ,
output reg [0007:0] debug_buf_cnt ,
output reg [0001:0] fir_fifo_overflow
);
wire local_cmd_valid;
reg retry_tag_out_valid_sync;
reg local_cmd_valid_sync;
reg [1023:0] lcl_data_in_sync;
reg [0127:0] lcl_addr_be_sync;
reg [0063:0] lcl_addr_ea_sync;
reg [`CTXW-1:0]lcl_addr_ctx_sync;
reg [`CTXW-1:0]lcl_addr_ctx_real;
reg [`TAGW-1:0]retry_tag_out_sync;
reg [`TAGW-1:0]recycle_tag_out_sync;
wire recycle_tag_out_req;
wire [`TAGW-1:0]recycle_tag_out;
reg retry_tag_in_valid;
wire retry_tag_out_req;
wire[`TAGW-1:0] retry_tag_out;
wire retry_tag_out_valid;
reg [`TAGW-1:0] retry_tag_in;
reg [000001:0] retry_pos_in;
wire[000001:0] retry_pos_out;
wire [`TAGW+1:0]fifo_rty_tag_din;
wire [`TAGW+1:0]fifo_rty_tag_dout;
wire [`TAGW-1:0]fifo_rty_tag_count;
wire fifo_rty_tag_wr_en;
wire fifo_rty_tag_rd_en;
wire fifo_rty_tag_empty;
wire fifo_rty_tag_ovfl;
reg retry_intrpt;
reg [0003:0] powerup_cnt;
reg fifo_rcy_init;
reg [`TAGW-1:0] fifo_rcy_init_cnt;
reg fifo_rcy_tag_wr_en;
reg [`TAGW-1:0] fifo_rcy_tag_din;
wire[`TAGW-1:0] fifo_rcy_tag_count;
wire fifo_rcy_tag_rd_en;
wire[`TAGW-1:0] fifo_rcy_tag_dout;
wire fifo_rcy_tag_full;
wire fifo_rcy_tag_ovfl;
wire[`TAGW-1:0] recycle_tag_dout;
wire fifo_rcy_tag_empty;
wire fifo_rcy_tag_alempty;
reg buf_w_data_o_en;
reg buf_w_data_e_en;
reg [`TAGW-1:0] buf_w_data_addr;
reg [1023:0] buf_w_data;
reg buf_w_info_en;
reg [`TAGW-1:0] buf_w_info_addr;
reg [0200:0] buf_w_info;
wire buf_r_data_en;
wire[1023:0] buf_r_data;
wire[`TAGW-1:0] buf_r_data_addr;
wire buf_r_info_en_for_wr;
wire[`TAGW-1:0] buf_r_info_addr;
wire[0200:0] buf_r_info;
wire[0127:0] buf_r_be;
reg [0127:0] retry_be;
wire[0063:0] buf_r_ea;
wire[`CTXW:0] buf_r_ctx;
wire rsv_valid;
wire[0001:0] rsv_pos;
wire[`TAGW-1:0] rsv_tag;
wire rsv_first;
wire rsv_last;
wire[`IDW-1:0] rsv_axi_id;
wire rsp_valid;
wire[`TAGW-1:0] rsp_tag;
wire[0001:0] rsp_pos;
wire[0002:0] rsp_code;
wire rec_valid;
wire[`TAGW-1:0] rec_tag;
wire rd_valid;
wire[`TAGW-1:0] rd_tag;
wire ret_resp;
`ifndef ENABLE_ODMA
wire ret_ready;
`else
wire[0031:0] ret_ready;
wire[0031:0] ret_ready_hint;
`endif
wire ret_valid;
wire[`TAGW-1:0] ret_tag;
wire[`IDW-1:0] ret_axi_id;
wire ret_last;
wire recycle_tag_out_ready;
reg [`IDW-1:0] ret_axi_id_sync;
reg ret_valid_sync, ret_resp_sync;
parameter DMA_W = 0,
DMA_R = 1;
parameter RESP_GOOD = 3'b001,
RESP_RETRY = 3'b010,
RESP_BAD = 3'b100;
//---- signaling readiness to AXI slave ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_addr_ready <= 1'b0;
else // When:
lcl_addr_ready <= recycle_tag_out_ready && // 1) Tag available in the recycling tag FIFO
dma_cmd_ready && // 2) Enough credits for TLX command, no partial command is in process
~retry_intrpt ; // 3) No retry interuption
//~retry_intrpt && // 3) No retry interuption
//~lcl_addr_idle; // 4) Transaction in AXI is active
//---- valid AXI command indication ----
assign local_cmd_valid = (lcl_addr_valid && lcl_addr_ready);
////---- timing alignment for normal and retry data ----
// always@(posedge clk or negedge rst_n)
// if(~rst_n)
// lcl_addr_ctx_real <= {`CTXW{1'b0}};
// else if(lcl_addr_ctx_valid)
// lcl_addr_ctx_real <= lcl_addr_ctx;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
retry_tag_out_valid_sync <= 1'b0;
local_cmd_valid_sync <= 1'b0;
lcl_data_in_sync <= 1024'd0;
lcl_addr_be_sync <= 128'd0;
lcl_addr_ea_sync <= 64'd0;
lcl_addr_ctx_sync <= {`CTXW{1'b0}};
retry_tag_out_sync <= {`TAGW{1'b0}};
recycle_tag_out_sync <= {`TAGW{1'b0}};
end
else
begin
retry_tag_out_valid_sync <= retry_tag_out_valid;
local_cmd_valid_sync <= local_cmd_valid;
lcl_data_in_sync <= lcl_data_in;
lcl_addr_be_sync <= lcl_addr_be;
lcl_addr_ea_sync <= lcl_addr_ea;
lcl_addr_ctx_sync <= lcl_addr_ctx;
retry_tag_out_sync <= retry_tag_out;
recycle_tag_out_sync <= recycle_tag_out;
end
//---- direct input data and info out to command encoder ----
// When retry is enabled, select data/info from data buffer for retry
// Otherwise, AXI data/info are routed to command encoder without delay
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
dma_cmd_valid <= 1'd0;
dma_cmd_data <= 1024'd0;
dma_cmd_be <= 128'd0;
dma_cmd_ea <= 64'd0;
dma_cmd_ctx <= {`CTXW{1'b0}};
dma_cmd_tag <= {`TAGW{1'b0}};
end
else
begin
dma_cmd_valid <= (retry_tag_out_valid_sync) || local_cmd_valid_sync;
dma_cmd_data <= (retry_tag_out_valid_sync)? buf_r_data : lcl_data_in_sync;
dma_cmd_be <= (retry_tag_out_valid_sync)? buf_r_be : lcl_addr_be_sync;
dma_cmd_ea <= (retry_tag_out_valid_sync)? buf_r_ea : lcl_addr_ea_sync;
dma_cmd_ctx <= (retry_tag_out_valid_sync)? buf_r_ctx : lcl_addr_ctx_sync;
dma_cmd_tag <= (retry_tag_out_valid_sync)? retry_tag_out_sync : recycle_tag_out_sync;
end
//-------------------------------------------------------------------------------------------------------------------------------------
// RECYCLE TAG FIFO
//
// -
// dma_cmd_* <== | | ================================= lcl_data_in/lcl_addr_*
// -
// +------------------+
// rec_tag ==> | recycle tag FIFO | <--------- lcl_addr_ready && lcl_addr_valid
// +------------------+
// - ||
// dma_cmd_tag <== | | =======================> rsv_tag
// -
//-------------------------------------------------------------------------------------------------------------------------------------
//---- power up after reset ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
powerup_cnt <= 4'd0;
else if(~&powerup_cnt)
powerup_cnt <= powerup_cnt + 4'd1;
//---- initialize FIFO contents at the start ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rcy_init <= 1'b0;
else if(&powerup_cnt[3:1] && ~powerup_cnt[0])
fifo_rcy_init <= 1'b1;
else if(&fifo_rcy_init_cnt)
fifo_rcy_init <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rcy_init_cnt <= {`TAGW{1'b0}};
else if(fifo_rcy_init)
fifo_rcy_init_cnt <= fifo_rcy_init_cnt + 1'b1;
//---- tag recycling FIFO (FWFT) ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rcy_tag_wr_en <= 1'b0;
else
fifo_rcy_tag_wr_en <= fifo_rcy_init || rec_valid;
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rcy_tag_din <= {`TAGW{1'b0}};
else if(fifo_rcy_init)
fifo_rcy_tag_din <= fifo_rcy_init_cnt;
else
fifo_rcy_tag_din <= rec_tag;
//fifo_sync_64_6i6o_fwft mfifo_rcy_tag (
fifo_sync #(
.DATA_WIDTH (`TAGW),
.ADDR_WIDTH (`TAGW),
.FWFT (1)
) mfifo_rcy_tag (
.clk (clk ), // input clk
.rst_n (rst_n ), // input rst
.din (fifo_rcy_tag_din ), // input [6 : 0] din
.wr_en (fifo_rcy_tag_wr_en ), // input wr_en
.rd_en (fifo_rcy_tag_rd_en ), // input rd_en
.dout (fifo_rcy_tag_dout ), // output [6 : 0] dout
.full (fifo_rcy_tag_full ), // output full
.empty (fifo_rcy_tag_empty ), // output almost_empty
.almost_empty (fifo_rcy_tag_alempty), // output almost_empty
.overflow (fifo_rcy_tag_ovfl ), // output overflow
.count (fifo_rcy_tag_count ) // output [6:0] count
);
//---- read out recycled tag whenever AXI is ready ----
// Caution: no latency between tag out request (AXI address info valid) and valid tag out
assign fifo_rcy_tag_rd_en = local_cmd_valid;
//TODO: check with xiaodi if recycle_tag_out_req can be assigned as follow
assign recycle_tag_out_req = fifo_rcy_tag_rd_en;
assign recycle_tag_out = fifo_rcy_tag_dout;
assign recycle_tag_out_ready = ~(fifo_rcy_tag_alempty | fifo_rcy_tag_empty);
assign buf_empty = fifo_rcy_tag_full;
//-------------------------------------------------------------------------------------------------------------------------------------
// RETRY TAG FIFO
//
//
// -----o<|-----lcl_addr_idle
// |
// V
// +----------------+ +-------------+
// dma_resp_tag ==> | retry tag FIFO | ==> retry_out_tag ==> | data buffer |
// (retry) +----------------+ || +-------------+
// -- || ||
// dma_cmd_tag <== |F| ======================== ||
// -- ||
// -- ||
// dma_cmd_* <== |F| =======================================
// --
//-------------------------------------------------------------------------------------------------------------------------------------
//---- fill in retry tag when response with retry request is available ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
retry_tag_in_valid <= 1'b0;
retry_tag_in <= {`TAGW{1'b0}};
retry_pos_in <= 2'b0;
end
else
begin
retry_tag_in_valid <= dma_resp_valid && (dma_resp_code == RESP_RETRY);
retry_tag_in <= dma_resp_tag;
retry_pos_in <= dma_resp_pos;
end
//---- interrupt when FIFO's half full ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
retry_intrpt <= 1'b0;
else if(~fifo_rty_tag_empty)
retry_intrpt <= 1'b0;
else if(fifo_rty_tag_count[`TAGW-1])
retry_intrpt <= 1'b1;
//---- retry tag FIFO ----
assign fifo_rty_tag_din = {retry_pos_in, retry_tag_in};
assign fifo_rty_tag_wr_en = retry_tag_in_valid;
//fifo_sync_64_6i6o_fwft mfifo_rty_tag (
fifo_sync #(
.DATA_WIDTH (`TAGW+2),
.ADDR_WIDTH (`TAGW),
.FWFT (1)
) mfifo_rty_tag (
.clk (clk ), // input clk
.rst_n (rst_n ), // input rst
.din (fifo_rty_tag_din ), // input [8 : 0] din
.wr_en (fifo_rty_tag_wr_en ), // input wr_en
.rd_en (fifo_rty_tag_rd_en ), // input rd_en
.dout (fifo_rty_tag_dout ), // output [8 : 0] dout
.count (fifo_rty_tag_count ), // output [8 : 0] count
.empty (fifo_rty_tag_empty ), // output empty
.overflow (fifo_rty_tag_ovfl ) // output overflow
);
//---- enable retry when retry interupt is asserted or no transaction in AXI ----
// Caution: no latency between tag out request (AXI address info valid) and valid tag out
assign retry_tag_out_req = (retry_intrpt || ~local_cmd_valid) && dma_cmd_ready && (((~rd_valid) && (MODE == DMA_R)) || ((MODE == DMA_W) && ~ret_valid));
assign fifo_rty_tag_rd_en = retry_tag_out_req && (!fifo_rty_tag_empty);
assign retry_tag_out = fifo_rty_tag_dout[6:0];
assign retry_tag_out_valid = fifo_rty_tag_rd_en;
assign retry_pos_out = fifo_rty_tag_dout[8:7];
//---- extended mask for command BE, used to pick out retry high or low 64B command ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
retry_be <= 127'd0;
end
else
begin
retry_be <= {{64{retry_pos_out[1]}}, {64{retry_pos_out[0]}}};
end
//-------------------------------------------------------------------------------------------------------------------------------------
// BUFFER SET
// * data and information buffers for command data (write) or response data (read)
// * command data is buffered as preparation for retry
// * response data is buffered to reorder for AXI read response
//-------------------------------------------------------------------------------------------------------------------------------------
//---- direct input data/info into data buffer ----
//
// ------------------------------------------
// | | Write data | Write EA/BE |
// ------------------------------------------
// | DMA write | command | command |
// | DMA read | response | command |
// ------------------------------------------
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
buf_w_data_o_en <= 1'b0;
buf_w_data_e_en <= 1'b0;
buf_w_data_addr <= {`TAGW{1'b1}};
buf_w_data <= 1024'd0;
buf_w_info_en <= 1'b0;
buf_w_info_addr <= {`TAGW{1'b1}};
buf_w_info <= 201'd0;
end
else
begin
buf_w_data_o_en <= (MODE == DMA_W)? local_cmd_valid_sync : (dma_resp_valid && dma_resp_pos[1]);
buf_w_data_e_en <= (MODE == DMA_W)? local_cmd_valid_sync : (dma_resp_valid && dma_resp_pos[0]);
buf_w_data_addr <= (MODE == DMA_W)? recycle_tag_out_sync : dma_resp_tag;
buf_w_data <= (MODE == DMA_W)? lcl_data_in_sync : dma_resp_data;
buf_w_info_en <= local_cmd_valid_sync;
buf_w_info_addr <= recycle_tag_out_sync;
buf_w_info <= {lcl_addr_ctx_sync, lcl_addr_ea_sync, lcl_addr_be_sync};
end
//---- buffer for data ----
ram_simple_dual #(512,`TAGW) mbuf_data_o (
.clk (clk ),
.ena (1'b1 ),
.enb (1'b1 ),
.wea (buf_w_data_o_en ),
.addra (buf_w_data_addr ),
.dia (buf_w_data[1023:512]),
.addrb (buf_r_data_addr ),
.dob (buf_r_data[1023:512])
);
ram_simple_dual #(512,`TAGW) mbuf_data_e (
.clk (clk ),
.ena (1'b1 ),
.enb (1'b1 ),
.wea (buf_w_data_e_en ),
.addra (buf_w_data_addr ),
.dia (buf_w_data[511:0] ),
.addrb (buf_r_data_addr ),
.dob (buf_r_data[511:0] )
);
//---- buffer for information ----
ram_simple_dual #(201,`TAGW) mbuf_info (
.clk (clk ),
.ena (1'b1 ),
.enb (1'b1 ),
.wea (buf_w_info_en ),
.addra (buf_w_info_addr),
.dia (buf_w_info ),
.addrb (buf_r_info_addr),
.dob (buf_r_info )
);
//---- read buffer data and info out of buffer ----
//
// -----------------------------------------------
// | | Read data | Read EA/BE/CTX |
// -----------------------------------------------
// | DMA write | retry | retry or reclaim |
// | DMA read | reclaim | retry or reclaim |
// -----------------------------------------------
assign buf_r_data_en = (MODE == DMA_W)? retry_tag_out_valid : rd_valid;
assign buf_r_data_addr = (MODE == DMA_W)? retry_tag_out : rd_tag;
`ifdef ENABLE_ODMA
assign buf_r_info_en_for_wr = (MODE == DMA_W) && (ret_valid);
`else
assign buf_r_info_en_for_wr = (MODE == DMA_W) && ((ret_valid && ret_ready) || (ret_valid_sync && !lcl_resp_ready));
`endif
assign buf_r_info_addr = retry_tag_out_valid? retry_tag_out : (buf_r_info_en_for_wr ? ret_tag : rd_tag);
assign buf_r_be = buf_r_info[127:0] & retry_be;
assign buf_r_ea = buf_r_info[191:128];
assign buf_r_ctx = buf_r_info[200:192];
//=====================================================================================================================================
// transaction order management
//=====================================================================================================================================
//---- slot reservation ----
assign rsv_valid = recycle_tag_out_req;
assign rsv_tag = recycle_tag_out;
assign rsv_first = lcl_addr_first;
assign rsv_last = lcl_addr_last;
assign rsv_pos[0] = |lcl_addr_be[63:0];
assign rsv_pos[1] = |lcl_addr_be[127:64];
assign rsv_axi_id = lcl_addr_axi_id;
//---- response with tags ----
assign rsp_valid = dma_resp_valid && (dma_resp_code != RESP_RETRY);
assign rsp_tag = dma_resp_tag;
assign rsp_pos = dma_resp_pos;
assign rsp_code = dma_resp_code;
generate
if(MODE == 1)
begin: rd_order_mng_gen
//---- maintaining the order of AXI burst return for read channel----
brdg_rd_order_mng_array mrd_order_mng (
.clk (clk ),
.rst_n (rst_n ),
.rsv_valid (rsv_valid ),
.rsv_tag (rsv_tag ),
.rsv_pos (rsv_pos ),
.rsv_axi_id (rsv_axi_id ),
.rsv_first (rsv_first ),
.rsv_last (rsv_last ),
.rsp_valid (rsp_valid ),
.rsp_tag (rsp_tag ),
.rsp_code (rsp_code ),
.rsp_pos (rsp_pos ),
.ret_ready (ret_ready ),
`ifdef ENABLE_ODMA
.ret_ready_hint (ret_ready_hint),
`endif
.ret_valid (ret_valid ),
.ret_axi_id (ret_axi_id ),
.ret_resp (ret_resp ),
.ret_last (ret_last ),
.rd_valid (rd_valid ),
.rd_tag (rd_tag ),
.rec_valid (rec_valid ),
.rec_tag (rec_tag )
);
end
else
begin:wr_order_mng_gen
//---- maintaining the order of AXI burst return for write channel----
brdg_wr_order_mng_array mwr_order_mng (
.clk (clk ),
.rst_n (rst_n ),
.rsv_valid (rsv_valid ),
.rsv_tag (rsv_tag ),
.rsv_pos (rsv_pos ),
.rsv_axi_id(rsv_axi_id),
.rsv_first (rsv_first ),
.rsv_last (rsv_last ),
.rsp_valid (rsp_valid ),
.rsp_tag (rsp_tag ),
.rsp_code (rsp_code ),
.rsp_pos (rsp_pos ),
.ret_ready (ret_ready ),
.ret_valid (ret_valid ),
.ret_tag (ret_tag ),
.ret_axi_id(ret_axi_id),
.ret_resp (ret_resp ),
.ret_last (ret_last ),
.rec_valid (rec_valid ),
.rec_tag (rec_tag )
);
end
endgenerate
//---- return data and response back to AXI, which should be one cycle later than reclaim channel ----
`ifdef ENABLE_ODMA
//NOTE:
// In ODMA mode, lcl_resp_valid of wr channel will be a fixed value, this fixed value will only be given to
// wr_order_mng_array to decide whether a ret_valid response can be generated to ST, MM or cmpl channle.
// As lcl_resp_valid is a fixed value, once a ret_valid can be generated, it means the related
// ret_valid_sync(lcl_resp_valid) can definately be passed to the downstream modules, we do not need to care
// about lcl_resp_valid singal any more.
//TODO: if the lcl_resp_valid in ODMA mode is modified to a non-fixed value, this part should be modified accordingly.
always@(posedge clk or negedge rst_n)
if(~rst_n)
ret_valid_sync <= 1'b0;
else if(ret_valid)
ret_valid_sync <= 1'b1;
else
ret_valid_sync <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
ret_axi_id_sync <= {`IDW{1'd0}};
ret_resp_sync <= 'd0;
end
else if(ret_valid)
begin
ret_axi_id_sync <= ret_axi_id;
ret_resp_sync <= ret_resp;
end
assign ret_ready = lcl_resp_ready;
assign lcl_resp_valid = (MODE == DMA_W)? ret_valid_sync : ret_valid;
assign lcl_resp_axi_id = (MODE == DMA_W)? ret_axi_id_sync : ret_axi_id;
assign lcl_resp_code = (MODE == DMA_W)? ret_resp_sync : ret_resp;
assign lcl_resp_ctx = buf_r_ctx;
assign lcl_data_out = buf_r_data;
assign lcl_data_out_last = ret_last;
assign lcl_data_ctx = buf_r_ctx;
assign ret_ready_hint = lcl_resp_ready_hint;
`else
always@(posedge clk or negedge rst_n)
if(~rst_n)
ret_valid_sync <= 1'b0;
else if(ret_valid && ret_ready)
ret_valid_sync <= 1'b1;
else if(lcl_resp_ready)
ret_valid_sync <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
ret_axi_id_sync <= {`IDW{1'd0}};
ret_resp_sync <= 'd0;
end
else if(ret_valid && ret_ready)
begin
ret_axi_id_sync <= ret_axi_id;
ret_resp_sync <= ret_resp;
end
assign ret_ready = (MODE == DMA_W)?(!ret_valid_sync || lcl_resp_ready) : lcl_resp_ready;
assign lcl_resp_valid = (MODE == DMA_W)? ret_valid_sync : ret_valid;
assign lcl_resp_axi_id = (MODE == DMA_W)? ret_axi_id_sync : ret_axi_id;
assign lcl_resp_code = (MODE == DMA_W)? ret_resp_sync : ret_resp;
assign lcl_resp_ctx = buf_r_ctx;
assign lcl_data_out = buf_r_data;
assign lcl_data_out_last = ret_last;
assign lcl_data_ctx = buf_r_ctx;
`endif
//=================================================================================================================
// STATUS output for SNAP registers
//=================================================================================================================
reg [31:0] cmd_idle_cnt;
reg [31:0] rsp_idle_cnt;
//---- DEBUG registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
debug_axi_cmd_idle <= 1'b0;
else if(local_cmd_valid)
debug_axi_cmd_idle <= 1'b0;
else if(cmd_idle_cnt == debug_axi_cmd_idle_lim)
debug_axi_cmd_idle <= 1'b1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
cmd_idle_cnt <= 32'd0;
else if(local_cmd_valid)
cmd_idle_cnt <= 32'd0;
else
cmd_idle_cnt <= cmd_idle_cnt + 32'd1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
debug_axi_rsp_idle <= 1'b0;
else if(lcl_resp_valid)
debug_axi_rsp_idle <= 1'b0;
else if(rsp_idle_cnt == debug_axi_rsp_idle_lim)
debug_axi_rsp_idle <= 1'b1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
rsp_idle_cnt <= 32'd0;
else if(lcl_resp_valid)
rsp_idle_cnt <= 32'd0;
else
rsp_idle_cnt <= rsp_idle_cnt + 32'd1;
//---- DEBUG registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
debug_axi_cnt_cmd <= 32'd0;
else if (debug_cnt_clear)
debug_axi_cnt_cmd <= 32'd0;
else if (lcl_addr_first && lcl_addr_valid && lcl_addr_ready)
debug_axi_cnt_cmd <= debug_axi_cnt_cmd + 32'd1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
debug_axi_cnt_rsp <= 32'd0;
else if (debug_cnt_clear)
debug_axi_cnt_rsp <= 32'd0;
`ifdef ENABLE_ODMA
else if ((MODE)? (lcl_data_out_last && lcl_resp_valid) : (lcl_resp_valid))
`else
else if ((MODE)? (lcl_data_out_last && lcl_resp_ready && lcl_resp_valid) : (lcl_resp_ready && lcl_resp_valid))
`endif
debug_axi_cnt_rsp <= debug_axi_cnt_rsp + 32'd1;
//---- DEBUG register ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
debug_buf_cnt <= 8'd0;
else
debug_buf_cnt <= (buf_empty)? 8'd0 : (8'd128 - fifo_rcy_tag_count);
//---- FAULT ISOLATION REGISTER ----
reg fir_fifo_rcy_tag_overflow;
reg fir_fifo_rty_tag_overflow;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fir_fifo_rcy_tag_overflow <= 1'b0;
fir_fifo_rty_tag_overflow <= 1'b0;
fir_fifo_overflow <= 2'b0;
end
else
begin
if (fifo_rcy_tag_ovfl) fir_fifo_rcy_tag_overflow <= 1'b1;
if (fifo_rty_tag_ovfl) fir_fifo_rty_tag_overflow <= 1'b1;
fir_fifo_overflow <= { fir_fifo_rcy_tag_overflow, fir_fifo_rty_tag_overflow };
end
// psl default clock = (posedge clk);
//==== PSL ASSERTION ==============================================================================
// psl NEW_CONTEXT_CONGESTED : assert always onehot0({retry_tag_out_valid, ((MODE == DMA_R) && rd_valid), ((MODE == DMA_W) && ret_valid)}) report "information buffer read conflict! Reading the infor BUF for TLX retry command and for AXI reclaim should never happen in the same time.";
//==== PSL ASSERTION ==============================================================================
//==== PSL ASSERTION ==============================================================================
// psl DMA_COMMAND_RETRY_CONFLICT : assert never (retry_tag_out_valid_sync && local_cmd_valid_sync) report "retry and normal command conflict! It's not allowed to send both retry command from retry FIFO and normal command from AXI to command encoder simultanuously.";
// psl SURPLUS_TLX_RSP : assert never (fifo_rcy_tag_full && dma_resp_valid) report "all buffer slots have been released, response from TLX is nevertheless received.";
// psl SURPLUS_AXI_CMD : assert never (fifo_rcy_tag_empty && local_cmd_valid) report "buffer slots have been used up, command from AXI is nevertheless received.";
//==== PSL ASSERTION ==============================================================================
//==== PSL COVERAGE ==============================================================================
// psl RETRY_FIFO_ALMOST_FULL : cover {retry_intrpt};
// psl TAG_ALL_CLAIMED : cover {~fifo_rcy_tag_full; fifo_rcy_tag_full};
// psl TAG_ALL_SET_FREE : cover {~fifo_rcy_tag_empty; fifo_rcy_tag_empty};
//==== PSL COVERAGE ==============================================================================
endmodule |
module mmio (
input clk ,
input rst_n ,
//---- SNAP debug -----------------------------
output debug_cnt_clear ,
input [63:0] debug_tlx_cnt_cmd ,
input [63:0] debug_tlx_cnt_rsp ,
input [63:0] debug_tlx_cnt_retry ,
input [63:0] debug_tlx_cnt_fail ,
input [63:0] debug_tlx_cnt_xlt_pd ,
input [63:0] debug_tlx_cnt_xlt_done ,
input [63:0] debug_tlx_cnt_xlt_retry ,
input [63:0] debug_axi_cnt_cmd ,
input [63:0] debug_axi_cnt_rsp ,
input [63:0] debug_buf_cnt ,
input [63:0] debug_traffic_idle ,
output [63:0] debug_tlx_idle_lim , // higher 32b: response idle counter limit; lower 32b: command idle counter limit
output [63:0] debug_axi_idle_lim , // higher 32b: response idle counter limit; lower 32b: command idle counter limit
//---- FIR -------------------------------------
input [63:0] fir_fifo_overflow ,
input [63:0] fir_tlx_interface ,
//---- local control output -------------------
output reg soft_reset_brdg_odma , // soft reset SNAP logic
output reg soft_reset_action , // soft reset action logic
//---- MMIO side interface --------------------
input mmio_wr ,
input mmio_rd ,
input mmio_dw ,
input [31:0] mmio_addr ,
input [63:0] mmio_din ,
output reg [63:0] mmio_dout ,
output reg mmio_done ,
output reg mmio_failed ,
//---- AXI Lite interface for action ----------
output reg lcl_wr , // write enable
output reg lcl_rd , // read enable
output reg [31:0] lcl_addr , // write/read address
output reg [31:0] lcl_din , // write data
input lcl_ack , // write data acknowledgement
input lcl_rsp , // write/read response: 1: good; 0: bad
input [31:0] lcl_dout , // read data
input lcl_dv // read data valid
);
// local status
reg snap_idle ; // SNAP data buffers empty
reg snap_tlx_busy ; // SNAP TLX command all responded
reg snap_axi_busy ; // SNAP AXI command all responded
reg snap_fatal_error; // SNAP FIFO overflow or TLX command over-commit
`ifdef ENABLE_NVME
parameter NVME_ENABLED = 1'b1; // NVMe host logic enabled for connecting to NVMe Flash drives
`else
parameter NVME_ENABLED = 1'b0; // NVMe host logic disabled for connecting to NVMe Flash drives
`endif
//=================================================================================================================
// MMIO SPACE ALLOCATION
//=================================================================================================================
// +-----------------------------------------------------------------------------------------------+
// |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
// +-----------------------------------------------------------------------------------------------+
parameter GLOBAL_PP_MMIO_BIT = 31; //0: Global space; 1: PerPASID space
parameter ACTION_ACCESS_BIT = 31; //0: Snap registers 1: Action registers
//Global space is for SNAP Core registers
//PerPASID space is for Action registers
//Now they have the same meanings
//PASID: 512 (9bits)
parameter PASID_START_BIT = 30;
parameter PASID_END_BIT = 22;
//SNAP core registers are grouped
//Decided by base_address + offset
parameter SNAP_BASE_START_BIT = 21;
parameter SNAP_BASE_END_BIT = 8;
parameter SNAP_OFFSET_START_BIT = 7;
parameter SNAP_OFFSET_END_BIT = 0;
//=================================================================================================================
// SNAP REGISTERS DECLARATION
//=================================================================================================================
//------------ REG_SNAP_BASE_ADDR ---------------
reg [63:00] REG_implementation_vertion;
reg [63:00] REG_build_date ;
reg [63:00] REG_command ;
reg [63:00] REG_status ;
reg [63:00] REG_capability ;
reg [63:00] REG_freeruntime ;
reg [63:00] REG_usercode ;
reg [63:00] REG_prcode ;
//------------ REG_DEBUG_BASE_ADDR --------------
reg [63:00] REG_debug_clear ; // clear out all debug registers
reg [63:00] REG_debug_tlx_cnt_cmd ; // (higher 32b: R, lower 32b: W) number of total TLX command
reg [63:00] REG_debug_tlx_cnt_rsp ; // (higher 32b: R, lower 32b: W) number of total TLX responses
reg [63:00] REG_debug_tlx_cnt_retry ; // (higher 32b: R, lower 32b: W) number of TLX retry responses
reg [63:00] REG_debug_tlx_cnt_fail ; // (higher 32b: R, lower 32b: W) number of TLX fail responses
reg [63:00] REG_debug_tlx_cnt_xlt_pd ; // (higher 32b: R, lower 32b: W) number of TLX xlate pending responses
reg [63:00] REG_debug_tlx_cnt_xlt_done ; // (higher 32b: R, lower 32b: W) number of TLX xlate done responses
reg [63:00] REG_debug_tlx_cnt_xlt_retry; // (higher 32b: R, lower 32b: W) number of TLX xlate retry responses
reg [63:00] REG_debug_axi_cnt_cmd ; // (higher 32b: R, lower 32b: W) number of total AXI commands
reg [63:00] REG_debug_axi_cnt_rsp ; // (higher 32b: R, lower 32b: W) number of total AXI responses
reg [63:00] REG_debug_buf_cnt ; // (higher 32b: R, lower 32b: W) number of available tags
reg [63:00] REG_debug_traffic_idle ; // no activity over a period (b0: AXIwrsp; b1: AXIwcmd; b2: AXIrrsp; b3: AXIrcmd; b4: TLXrsp; b5: TLXcmd)
reg [63:00] REG_debug_tlx_idle_lim ; // length of the period during which no signal is active on TLX
reg [63:00] REG_debug_axi_idle_lim ; // length of the period during which no signal is active on AXI
//------------ REG_FIR_BASE_ADDR ----------------
reg [63:00] REG_fir_fifo_overflow ; // collection of FIFO overflow indicators
reg [63:00] REG_fir_tlx_interface ; // submit more commands than credits to TLX
//=================================================================================================================
// SNAP REGISTERS ADDRESSES
//=================================================================================================================
parameter REG_SNAP_BASE_ADDR = 13'h0000,
REG_SNAP_OFFSET_ADDR_IVR = 8'h0 , //RO
REG_SNAP_OFFSET_ADDR_BDR = 8'h8 , //RO
REG_SNAP_OFFSET_ADDR_SCR = 8'h10, //WO
REG_SNAP_OFFSET_ADDR_SSR = 8'h18, //RO
REG_SNAP_OFFSET_ADDR_CAP = 8'h30, //RO
REG_SNAP_OFFSET_ADDR_FRT = 8'h40, //RO
REG_SNAP_OFFSET_ADDR_USR = 8'h50, //RO
REG_SNAP_OFFSET_ADDR_PRC = 8'h60, //RO
REG_DEBUG_BASE_ADDR = 13'h01A0,
REG_DEBUG_OFFSET_ADDR_DBG_CLR = 8'h00, //WO, self-clear
REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD = 8'h08, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP = 8'h10, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY = 8'h18, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL = 8'h20, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP = 8'h28, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD = 8'h30, //RO
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR = 8'h38, //RO
REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD = 8'h40, //RO
REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP = 8'h48, //RO
REG_DEBUG_OFFSET_ADDR_BUF_CNT = 8'h50, //RO
REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE = 8'h58, //RO
REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM = 8'h60,
REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM = 8'h68,
REG_FIR_BASE_ADDR = 13'h01C0,
REG_SNAP_OFFSET_ADDR_FIFO_OVFL = 8'h0 , //RO
REG_SNAP_OFFSET_ADDR_TLX_INTRFC = 8'h8 ; //RO
//---- action access: 4B; SNAP access: 8B ----
wire data_width_incompatible = (mmio_rd || mmio_wr) && ((mmio_addr[ACTION_ACCESS_BIT] && mmio_dw) || (~mmio_addr[ACTION_ACCESS_BIT] && ~mmio_dw));
//---- validated action and SNAP access ----
wire action_access = mmio_addr[ACTION_ACCESS_BIT];
wire snap_access = ~mmio_addr[ACTION_ACCESS_BIT];
//---- extract base and offset addresses for SNAP register set ----
wire[SNAP_BASE_START_BIT - SNAP_BASE_END_BIT : 0] snap_base_addr;
wire[SNAP_OFFSET_START_BIT - SNAP_OFFSET_END_BIT : 0] snap_offset_addr;
assign snap_base_addr = mmio_addr[SNAP_BASE_START_BIT : SNAP_BASE_END_BIT];
assign snap_offset_addr = mmio_addr[SNAP_OFFSET_START_BIT: SNAP_OFFSET_END_BIT];
reg waddr_decode_error, raddr_decode_error;
reg snap_wr_ack, snap_rd_ack;
//---- action write/read valid pulse ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
lcl_wr <= 1'b0;
lcl_rd <= 1'b0;
end
else if(action_access)
begin
lcl_wr <= mmio_wr;
lcl_rd <= mmio_rd;
end
//---- action register address ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_addr <= 32'd0;
else
lcl_addr <= {1'b0,mmio_addr[30:0]}; //Lower 31bits are transfered to Action.
//---- action write data ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_din <= 32'd0;
else
lcl_din <= mmio_addr[2]? mmio_din[63:32] : mmio_din[31:0];
//---- return failure when... ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
mmio_failed <= 1'b0;
else
mmio_failed <= (data_width_incompatible ) || // 1. access with unwarrented data widths
((lcl_ack || lcl_dv) && (lcl_rsp == 1'b0)) || // 2. receive bad response from action
(snap_wr_ack && waddr_decode_error) || // 3. not able to locate defined SNAP register, or access illegally
(snap_rd_ack && raddr_decode_error);
//---- return done when... ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
mmio_done <= 1'b0;
else
mmio_done <= ((lcl_ack || lcl_dv) && (lcl_rsp == 1'b1)) || // 1. receive good response from action
(snap_wr_ack && ~waddr_decode_error) || // 2. done with SNAP register access
(snap_rd_ack && ~raddr_decode_error);
//---- READ ONLY registers configuration ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
// REG_SNAP_BASE_ADDR
REG_implementation_vertion <= 64'd0;
REG_build_date <= 64'd0;
REG_status <= 64'd0;
REG_capability <= 64'd0;
REG_freeruntime <= 64'd0;
REG_usercode <= 64'd0;
REG_prcode <= 64'd0;
// REG_DEBUG_BASE_ADDR
REG_debug_tlx_cnt_cmd <= 64'd0;
REG_debug_tlx_cnt_rsp <= 64'd0;
REG_debug_tlx_cnt_retry <= 64'd0;
REG_debug_tlx_cnt_fail <= 64'd0;
REG_debug_tlx_cnt_xlt_pd <= 64'd0;
REG_debug_tlx_cnt_xlt_done <= 64'd0;
REG_debug_tlx_cnt_xlt_retry <= 64'd0;
REG_debug_axi_cnt_cmd <= 64'd0;
REG_debug_axi_cnt_rsp <= 64'd0;
REG_debug_buf_cnt <= 64'd0;
REG_debug_traffic_idle <= 64'd0;
// REG_FIR_BASE_ADDR
REG_fir_fifo_overflow <= 64'd0;
REG_fir_tlx_interface <= 64'd0;
end
else
begin
// REG_SNAP_BASE_ADDR
REG_implementation_vertion <= `IMP_VERSION_DAT;
REG_build_date <= `BUILD_DATE_DAT;
REG_status <= {60'd0, snap_fatal_error, snap_axi_busy, snap_tlx_busy, snap_idle};
REG_capability [39:36] <= `DMA_XFER_SIZE;
REG_capability [35:32] <= `DMA_ALIGNMENT;
REG_capability [31:16] <= `SDRAM_SIZE;
REG_capability [8] <= NVME_ENABLED;
REG_capability [7:0] <= `CARD_TYPE;
REG_freeruntime <= REG_freeruntime+1;
REG_usercode <= `USERCODE;
REG_prcode <= `PRCODE;
// REG_DEBUG_BASE_ADDR
REG_debug_tlx_cnt_cmd <= debug_tlx_cnt_cmd ;
REG_debug_tlx_cnt_rsp <= debug_tlx_cnt_rsp ;
REG_debug_tlx_cnt_retry <= debug_tlx_cnt_retry ;
REG_debug_tlx_cnt_fail <= debug_tlx_cnt_fail ;
REG_debug_tlx_cnt_xlt_pd <= debug_tlx_cnt_xlt_pd ;
REG_debug_tlx_cnt_xlt_done <= debug_tlx_cnt_xlt_done ;
REG_debug_tlx_cnt_xlt_retry <= debug_tlx_cnt_xlt_retry;
REG_debug_axi_cnt_cmd <= debug_axi_cnt_cmd ;
REG_debug_axi_cnt_rsp <= debug_axi_cnt_rsp ;
REG_debug_buf_cnt <= debug_buf_cnt ;
REG_debug_traffic_idle <= debug_traffic_idle ;
// REG_FIR_BASE_ADDR
REG_fir_fifo_overflow <= fir_fifo_overflow ;
REG_fir_tlx_interface <= fir_tlx_interface ;
end
//---- SNAP write only/write read REGISTER writing ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
REG_command <= 64'd0;
REG_debug_clear <= 64'd0;
REG_debug_tlx_idle_lim <= 64'd0;
REG_debug_axi_idle_lim <= 64'd0;
waddr_decode_error <= 1'b0;
end
else if(snap_access && mmio_wr)
case(snap_base_addr)
REG_SNAP_BASE_ADDR :
case(snap_offset_addr)
REG_SNAP_OFFSET_ADDR_SCR : REG_command <= mmio_din;
default : waddr_decode_error <= 1'b1;
endcase
REG_DEBUG_BASE_ADDR :
case(snap_offset_addr)
REG_DEBUG_OFFSET_ADDR_DBG_CLR : REG_debug_clear <= mmio_din;
REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM : REG_debug_tlx_idle_lim <= mmio_din;
REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM : REG_debug_axi_idle_lim <= mmio_din;
default : waddr_decode_error <= 1'b1;
endcase
default : waddr_decode_error <= 1'b1;
endcase
else
begin
REG_debug_clear <= 64'd0;
REG_command <= 64'd0;
waddr_decode_error <= 1'b0;
end
always@(posedge clk)
begin
end
//---- SNAP/ACTION REGISTER reading ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
mmio_dout <= 64'd0;
raddr_decode_error <= 1'b0;
end
// read value from action registers and place it in correct half for TLX
else if(lcl_dv)
begin
mmio_dout <= mmio_addr[2]? {lcl_dout, 32'd0} : {32'd0, lcl_dout};
raddr_decode_error <= 1'b0;
end
// read from SNAP registers
else if (snap_access) begin
case(snap_base_addr)
REG_SNAP_BASE_ADDR :
case(snap_offset_addr)
REG_SNAP_OFFSET_ADDR_IVR : mmio_dout <= REG_implementation_vertion;
REG_SNAP_OFFSET_ADDR_SCR : mmio_dout <= REG_command;
REG_SNAP_OFFSET_ADDR_BDR : mmio_dout <= REG_build_date ;
REG_SNAP_OFFSET_ADDR_SSR : mmio_dout <= REG_status ;
REG_SNAP_OFFSET_ADDR_CAP : mmio_dout <= REG_capability ;
REG_SNAP_OFFSET_ADDR_FRT : mmio_dout <= REG_freeruntime ;
REG_SNAP_OFFSET_ADDR_USR : mmio_dout <= REG_usercode ;
REG_SNAP_OFFSET_ADDR_PRC : mmio_dout <= REG_prcode ;
default : raddr_decode_error <= 1'b1;
endcase
REG_DEBUG_BASE_ADDR :
case(snap_offset_addr)
REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD : mmio_dout <= REG_debug_tlx_cnt_cmd ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP : mmio_dout <= REG_debug_tlx_cnt_rsp ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY : mmio_dout <= REG_debug_tlx_cnt_retry ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL : mmio_dout <= REG_debug_tlx_cnt_fail ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP : mmio_dout <= REG_debug_tlx_cnt_xlt_pd ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD : mmio_dout <= REG_debug_tlx_cnt_xlt_done ;
REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR : mmio_dout <= REG_debug_tlx_cnt_xlt_retry;
REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD : mmio_dout <= REG_debug_axi_cnt_cmd ;
REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP : mmio_dout <= REG_debug_axi_cnt_rsp ;
REG_DEBUG_OFFSET_ADDR_BUF_CNT : mmio_dout <= REG_debug_buf_cnt ;
REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE : mmio_dout <= REG_debug_traffic_idle ;
REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM : mmio_dout <= REG_debug_tlx_idle_lim ;
REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM : mmio_dout <= REG_debug_axi_idle_lim ;
default : raddr_decode_error <= 1'b1;
endcase
REG_FIR_BASE_ADDR :
case(snap_offset_addr)
REG_SNAP_OFFSET_ADDR_FIFO_OVFL : mmio_dout <= REG_fir_fifo_overflow ;
REG_SNAP_OFFSET_ADDR_TLX_INTRFC : mmio_dout <= REG_fir_tlx_interface ;
default : raddr_decode_error <= 1'b1;
endcase
default : raddr_decode_error <= 1'b1;
endcase
end
//---- SNAP registers acknowledgement ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
snap_wr_ack <= 1'b0;
snap_rd_ack <= 1'b0;
end
else
begin
snap_wr_ack <= mmio_wr && snap_access;
snap_rd_ack <= mmio_rd && snap_access;
end
//---- local control signals output ----
reg [3:0] snap_reset_cnt;
reg [3:0] action_reset_cnt;
always@(posedge clk or negedge rst_n) // soft reset lasts 16 cycles
if(~rst_n)
soft_reset_brdg_odma <= 1'b0;
else if(&snap_reset_cnt)
soft_reset_brdg_odma <= 1'b0;
else if(REG_command[0])
soft_reset_brdg_odma <= 1'b1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
snap_reset_cnt <= 4'd0;
else if(soft_reset_brdg_odma)
snap_reset_cnt <= snap_reset_cnt + 4'd1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
soft_reset_action <= 1'b0;
else if(&action_reset_cnt)
soft_reset_action <= 1'b0;
else if(REG_command[0])
soft_reset_action <= 1'b1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
action_reset_cnt <= 4'd0;
else if(soft_reset_action)
action_reset_cnt <= action_reset_cnt + 4'd1;
assign debug_cnt_clear = REG_debug_clear[0];
assign debug_tlx_idle_lim = REG_debug_tlx_idle_lim;
assign debug_axi_idle_lim = REG_debug_axi_idle_lim;
//---- local status signals generation ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
snap_idle <= 1'b0;
snap_tlx_busy <= 1'b0;
snap_axi_busy <= 1'b0;
snap_fatal_error <= 1'b0;
end
else
begin
snap_idle <= (debug_buf_cnt == 64'd0); // SNAP considered in IDLE when both data BUF are empty
snap_tlx_busy <= (debug_tlx_cnt_cmd != debug_tlx_cnt_rsp); // only count read and write command/response pair, not viable for split responses
snap_axi_busy <= (debug_axi_cnt_cmd != debug_axi_cnt_rsp);
snap_fatal_error <= |{fir_fifo_overflow, fir_tlx_interface};
end
endmodule |
module brdg_interrupt (
input clk ,
input rst_n ,
//---- configuration --------------------------------------
input [011:0] cfg_actag_base ,
input [019:0] cfg_pasid_base ,
input [019:0] cfg_pasid_mask ,
//---- backoff time countdown time limit ------------------
input [003:0] backoff_limit ,
//---- enable interrupt when SNAP is idle -----------------
input interrupt_enable ,
//---- AXI interface --------------------------------------
output interrupt_ack ,
input interrupt ,
input [063:0] interrupt_src ,
input [008:0] interrupt_ctx ,
//---- TLX interface --------------------------------------
output reg tlx_cmd_valid ,
output reg [067:0] tlx_cmd_obj ,
output reg [015:0] tlx_cmd_afutag ,
output reg [007:0] tlx_cmd_opcode ,
output reg [0019:0] tlx_cmd_pasid ,
output reg [0011:0] tlx_cmd_actag ,
input tlx_rsp_valid ,
input [015:0] tlx_rsp_afutag ,
input [007:0] tlx_rsp_opcode ,
input [003:0] tlx_rsp_code
);
reg [07:00] cstate, nstate;
reg [23:00] cfg_short_backoff_timer;
reg [23:00] backoff_countdown;
reg [063:0] interrupt_src_sync;
wire backoff_timeup;
wire int_rsp_done;
wire int_rsp_retry;
wire int_rsp_pending;
wire int_rsp_fail;
wire int_rsp_rdy_done;
wire int_rsp_rdy_retry;
parameter IDLE = 8'h01,
NEW_INT = 8'h02,
WAIT_FOR_RSP = 8'h04,
INT_PENDING = 8'h08,
INT_BACKOFF = 8'h10,
UNEXP_RESP = 8'h20,
ACK_INT = 8'h40;
// TLX AP command encodes
localparam [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ = 8'b01011000; // -- Interrupt Request
localparam [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_S = 8'b01011001; // -- Interrupt Request
localparam [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D = 8'b01011010; // -- Interrupt Request
localparam [7:0] AFU_TLX_CMD_ENCODE_INTRP_REQ_D_S = 8'b01011011; // -- Interrupt Request
// TL CAPP response encodes
localparam [7:0] TLX_AFU_RESP_ENCODE_INTRP_RESP = 8'b00001100; // -- Interrupt Response
localparam [7:0] TLX_AFU_RESP_ENCODE_INTRP_RDY = 8'b00011010; // -- Interrupt ready (Async Notification)
// TL CAP response code encodes
localparam [3:0] TLX_AFU_RESP_CODE_DONE = 4'b0000; // -- Done
localparam [3:0] TLX_AFU_RESP_CODE_RTY_REQ = 4'b0010; // -- Retry Heavy weight (long backoff timer)
localparam [3:0] TLX_AFU_RESP_CODE_INTRP_PENDING = 4'b0100; // -- Toss, wait for intrp rdy with same AFU tag, convert to Retry
localparam [3:0] TLX_AFU_RESP_CODE_DERROR = 4'b1000; // -- Machine Check
localparam [3:0] TLX_AFU_RESP_CODE_BAD_LENGTH = 4'b1001; // -- Machine Check
localparam [3:0] TLX_AFU_RESP_CODE_BAD_HANDLE = 4'b1011; // -- Machine Check
localparam [3:0] TLX_AFU_RESP_CODE_FAILED = 4'b1110; // -- Machine Check
//store interrupt_src to interrupt_src_sync when interrupt is set, this signal is stored for reuse when retry
always@(posedge clk or negedge rst_n)
if(~rst_n)
interrupt_src_sync <= 0;
else if(interrupt)
interrupt_src_sync <= interrupt_src;
//---- TLX command ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
tlx_cmd_valid <= 1'd0;
tlx_cmd_obj <= 68'd0;
tlx_cmd_afutag <= 16'd0;
tlx_cmd_opcode <= 8'd0;
end
else
begin
tlx_cmd_valid <= ((cstate == NEW_INT) && interrupt_enable);
tlx_cmd_obj <= {4'd0, interrupt_src_sync};
tlx_cmd_afutag <= {2'b11, 14'd0};
tlx_cmd_opcode <= AFU_TLX_CMD_ENCODE_INTRP_REQ;
end
//---- interrupt pasid and actag ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
tlx_cmd_pasid <= 20'd0;
tlx_cmd_actag <= 12'd0;
end
else
begin
tlx_cmd_pasid <= ((cfg_pasid_base & cfg_pasid_mask) | ({{(20-`CTXW){1'd0}}, interrupt_ctx} & ~cfg_pasid_mask));
tlx_cmd_actag <= cfg_actag_base + {{(12-`CTXW){1'd0}}, interrupt_ctx};
end
//---- TLX response ----
assign int_rsp_done = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RESP) && (tlx_rsp_code == TLX_AFU_RESP_CODE_DONE);
assign int_rsp_retry = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RESP) && (tlx_rsp_code == TLX_AFU_RESP_CODE_RTY_REQ);
assign int_rsp_pending = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RESP) && (tlx_rsp_code == TLX_AFU_RESP_CODE_INTRP_PENDING);
assign int_rsp_fail = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RESP) && (tlx_rsp_code == TLX_AFU_RESP_CODE_FAILED);
assign int_rsp_rdy_done = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RDY) && (tlx_rsp_code == TLX_AFU_RESP_CODE_DONE);
assign int_rsp_rdy_retry = tlx_rsp_valid && (tlx_rsp_opcode == TLX_AFU_RESP_ENCODE_INTRP_RDY) && (tlx_rsp_code == TLX_AFU_RESP_CODE_RTY_REQ);
//---- interrupt acknowledgement ----
assign interrupt_ack = (cstate == ACK_INT) || (cstate == UNEXP_RESP);
//---- interrupt command sending and response receiving statemachine ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
cstate <= IDLE;
else
cstate <= nstate;
always@*
case(cstate)
IDLE :
if(interrupt)
nstate = NEW_INT;
else
nstate = IDLE;
NEW_INT :
if(interrupt_enable)
nstate = WAIT_FOR_RSP;
else
nstate = NEW_INT;
WAIT_FOR_RSP:
if(int_rsp_done)
nstate = ACK_INT;
else if(int_rsp_retry)
nstate = INT_BACKOFF;
else if(int_rsp_pending)
nstate = INT_PENDING;
else if(int_rsp_fail)
nstate = UNEXP_RESP;
else
nstate = WAIT_FOR_RSP;
INT_PENDING :
if(int_rsp_rdy_done)
nstate = NEW_INT;
else if(int_rsp_rdy_retry)
nstate = INT_BACKOFF;
else
nstate = INT_PENDING;
INT_BACKOFF :
if(backoff_timeup)
nstate = NEW_INT;
else
nstate = INT_BACKOFF;
UNEXP_RESP :
if(~interrupt)
nstate = IDLE;
else
nstate = UNEXP_RESP;
ACK_INT :
if(~interrupt)
nstate = IDLE;
else
nstate = ACK_INT;
default :
nstate = IDLE;
endcase
//---- backoff timer ----
always @*
begin
case (backoff_limit[3:0]) // -- At 200 MHz, 20 clock cycles (x14) = 100 ns
4'b0000: cfg_short_backoff_timer[23:0] = 24'h00_0014; // -- 2^0 = 1 * 100 ns
4'b0001: cfg_short_backoff_timer[23:0] = 24'h00_0028; // -- 2^1 = 2 * 100 ns
4'b0010: cfg_short_backoff_timer[23:0] = 24'h00_0050; // -- 2^2 = 4 * 100 ns
4'b0011: cfg_short_backoff_timer[23:0] = 24'h00_00A0; // -- 2^3 = 8 * 100 ns
4'b0100: cfg_short_backoff_timer[23:0] = 24'h00_0140; // -- 2^4 = 16 * 100 ns
4'b0101: cfg_short_backoff_timer[23:0] = 24'h00_0280; // -- 2^5 = 32 * 100 ns
4'b0110: cfg_short_backoff_timer[23:0] = 24'h00_0500; // -- 2^6 = 64 * 100 ns
4'b0111: cfg_short_backoff_timer[23:0] = 24'h00_0A00; // -- 2^7 = 128 * 100 ns
4'b1000: cfg_short_backoff_timer[23:0] = 24'h00_1400; // -- 2^8 = 256 * 100 ns
4'b1001: cfg_short_backoff_timer[23:0] = 24'h00_2800; // -- 2^9 = 512 * 100 ns
4'b1010: cfg_short_backoff_timer[23:0] = 24'h00_5000; // -- 2^10 = 1024 * 100 ns
4'b1011: cfg_short_backoff_timer[23:0] = 24'h00_A000; // -- 2^11 = 2048 * 100 ns
4'b1100: cfg_short_backoff_timer[23:0] = 24'h01_4000; // -- 2^12 = 4096 * 100 ns
4'b1101: cfg_short_backoff_timer[23:0] = 24'h02_8000; // -- 2^13 = 8192 * 100 ns
4'b1110: cfg_short_backoff_timer[23:0] = 24'h05_0000; // -- 2^14 = 16384 * 100 ns
4'b1111: cfg_short_backoff_timer[23:0] = 24'h0A_0000; // -- 2^15 = 32768 * 100 ns
endcase
end // -- always @ *
//---- backoff counter for retry ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
backoff_countdown <= 24'd0;
else if(cstate == INT_BACKOFF)
backoff_countdown <= backoff_countdown - 24'd1;
else
backoff_countdown <= cfg_short_backoff_timer;
assign backoff_timeup = (~|backoff_countdown);
endmodule |
module brdg_retry_queue
(
input clk ,
input rst_n ,
// backoff time countdown time limit
input [003:0] backoff_limit,
// partial command start indicator
input prt_cmd_start,
// retry busy indicator
output rty_busy ,
// retry request in
input rsp_den ,
input [001:0] rsp_pos ,
input [`TAGW-1:0]rsp_tag ,
input [004:0] rsp_typ ,
// retry request out
input rty_rdy ,
output rty_valid ,
output reg [001:0] rty_pos ,
output reg [`TAGW-1:0]rty_tag ,
// FIFO overflow
output overflow
);
reg fifo_retry_den;
reg [11:00] fifo_retry_din;
wire fifo_retry_rdrq;
wire fifo_retry_dv;
wire fifo_retry_empty;
reg rsp_is_retry_backoff;
reg [23:00] cfg_short_backoff_timer;
reg rsp_is_xlate_pending;
reg rsp_is_partial;
wire[11:00] fifo_retry_dout;
reg [23:00] backoff_countdown;
reg [04:00] xlate_pending_cnt;
wire retry_check_done;
reg [04:00] cstate, nstate;
reg ram_xlate_done_wena;
reg [`TAGW-1:00] ram_xlate_done_addra;
reg [03:00] ram_xlate_done_dina;
reg [02:00] retry_check_done_slide;
wire rsp_is_xlate_done_retry_backoff;
wire rsp_is_xlate_done_retry_immediate;
reg [`TAGW-1:00]ram_xlate_done_addrb;
wire[03:00] ram_xlate_done_doutb;
reg [`TAGW-1:00]last_rty_tag;
reg [01:00] last_rty_pos;
reg rep_retry_enable;
parameter IDLE = 5'b00001,
RETRY_RELEASE = 5'b00010,
RETRY_CHECK = 5'b00100,
RETRY_BACKOFF = 5'b01000,
RETRY_NOW = 5'b10000;
//-----------------------------------------------------------------------------------------------------------------
//
// Retry responses pushed into retry queue include: xlate_pending and rty_req
//
// Data of the retry queue are read out of the queue only if
// 1), it's not empty,
// 2), not any retry process is ongoing,
// 3), the same number of xlate_done as the xlate_pending that have been put in the queue are also received.
//
// Meanwhile, xlate_done response that follows the xlate_pending is stored in another RAM and read out
// addressed by the same AFUTAG as the response that's being read out of the retry queue.
//
// If the response read from the retry queue is rty_req, retry will be carried out after a backoff time.
// But if the response read from the retry queue is xlate_pending, retry will be carried out immediately if the
// resp_code going with the xlate_done is DONE.
//
//-----------------------------------------------------------------------------------------------------------------
//---- decode retry related responses ----
wire rsp_xlate_pending = rsp_typ[0];
wire rsp_xlate_done_retry_backoff = rsp_typ[1];
wire rsp_xlate_done_retry_immediate = rsp_typ[2];
wire rsp_retry_backoff = rsp_typ[3];
wire rsp_partial = rsp_typ[4];
//---- push retry and xlate_pending responses in queue ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fifo_retry_den <= 1'b0;
fifo_retry_din <= 12'd0;
end
else
begin
fifo_retry_den <= rsp_den && (rsp_xlate_pending || rsp_retry_backoff);
fifo_retry_din <= {rsp_partial, rsp_retry_backoff, rsp_xlate_pending, rsp_pos, rsp_tag}; //1+1+1+2+7=12
end
//---- retry FIFO ----
fifo_sync #(
.DATA_WIDTH (12),
.ADDR_WIDTH (7),
.FWFT (0)
) mfifo_rty_tag (
.clk (clk ), // input clk
.rst_n (rst_n ), // input rst
.din (fifo_retry_din ), // input [11 : 0] din
.wr_en (fifo_retry_den ), // input wr_en
.rd_en (fifo_retry_rdrq ), // input rd_en
.dout (fifo_retry_dout ), // output [11 : 0] dout
.valid (fifo_retry_dv ),
.empty (fifo_retry_empty), // output empty
.overflow (overflow )
);
//---- read FIFO once only when 1) equal number of xlate_pending and xlate_done have received; 2) FIFO is not empty
assign fifo_retry_rdrq = (cstate == RETRY_RELEASE);
//---- retrieve retry responses ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
{rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= 12'd0;
else if(fifo_retry_dv)
{rsp_is_partial, rsp_is_retry_backoff, rsp_is_xlate_pending, rty_pos, rty_tag} <= fifo_retry_dout;
//---- retry timer mapping, copied from the MCP3 example ----
always @*
begin
case (backoff_limit[3:0]) // -- At 200 MHz, 20 clock cycles (x14) = 100 ns
4'b0000: cfg_short_backoff_timer[23:0] = 24'h00_0014; // -- 2^0 = 1 * 100 ns
4'b0001: cfg_short_backoff_timer[23:0] = 24'h00_0028; // -- 2^1 = 2 * 100 ns
4'b0010: cfg_short_backoff_timer[23:0] = 24'h00_0050; // -- 2^2 = 4 * 100 ns
4'b0011: cfg_short_backoff_timer[23:0] = 24'h00_00A0; // -- 2^3 = 8 * 100 ns
4'b0100: cfg_short_backoff_timer[23:0] = 24'h00_0140; // -- 2^4 = 16 * 100 ns
4'b0101: cfg_short_backoff_timer[23:0] = 24'h00_0280; // -- 2^5 = 32 * 100 ns
4'b0110: cfg_short_backoff_timer[23:0] = 24'h00_0500; // -- 2^6 = 64 * 100 ns
4'b0111: cfg_short_backoff_timer[23:0] = 24'h00_0A00; // -- 2^7 = 128 * 100 ns
4'b1000: cfg_short_backoff_timer[23:0] = 24'h00_1400; // -- 2^8 = 256 * 100 ns
4'b1001: cfg_short_backoff_timer[23:0] = 24'h00_2800; // -- 2^9 = 512 * 100 ns
4'b1010: cfg_short_backoff_timer[23:0] = 24'h00_5000; // -- 2^10 = 1024 * 100 ns
4'b1011: cfg_short_backoff_timer[23:0] = 24'h00_A000; // -- 2^11 = 2048 * 100 ns
4'b1100: cfg_short_backoff_timer[23:0] = 24'h01_4000; // -- 2^12 = 4096 * 100 ns
4'b1101: cfg_short_backoff_timer[23:0] = 24'h02_8000; // -- 2^13 = 8192 * 100 ns
4'b1110: cfg_short_backoff_timer[23:0] = 24'h05_0000; // -- 2^14 = 16384 * 100 ns
4'b1111: cfg_short_backoff_timer[23:0] = 24'h0A_0000; // -- 2^15 = 32768 * 100 ns
endcase
end // -- always @ *
//---- backoff counter for retry ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
backoff_countdown <= 24'd0;
else if(cstate == RETRY_BACKOFF)
backoff_countdown <= backoff_countdown - 24'd1;
else
backoff_countdown <= cfg_short_backoff_timer;
//---- balance counter for xlate_pending and xlate_done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
xlate_pending_cnt <= 5'd0;
else if(rsp_den)
case(rsp_typ[3:0])
4'b0001 : xlate_pending_cnt <= xlate_pending_cnt + 5'd1; // xlate_pending
4'b0010 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1; // xlate_done
4'b0100 : xlate_pending_cnt <= xlate_pending_cnt - 5'd1; // xlate_done
default:;
endcase
//---- statemachine ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
cstate <= IDLE;
else
cstate <= nstate;
always@*
case(cstate)
IDLE :
if (~fifo_retry_empty && ~|xlate_pending_cnt)
nstate = RETRY_RELEASE;
else
nstate = IDLE;
RETRY_RELEASE :
nstate = RETRY_CHECK;
RETRY_CHECK :
if (retry_check_done)
begin
if ((rty_tag == last_rty_tag) && (rty_pos == last_rty_pos) && ~rep_retry_enable) // skip retry output with identical tag
nstate = IDLE;
else if (rsp_is_retry_backoff)
nstate = RETRY_BACKOFF;
else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_immediate)
nstate = RETRY_NOW;
else if (rsp_is_xlate_pending && rsp_is_xlate_done_retry_backoff)
nstate = RETRY_BACKOFF;
else
nstate = RETRY_CHECK;
end
else
nstate = RETRY_CHECK;
RETRY_BACKOFF :
if (~|backoff_countdown)
nstate = RETRY_NOW;
else
nstate = RETRY_BACKOFF;
RETRY_NOW :
if (rty_rdy)
nstate = IDLE;
else
nstate = RETRY_NOW;
default :
nstate = IDLE;
endcase
//---- timing adjustment for xlate_pending and xlate_done comparison ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
retry_check_done_slide <= 3'b001;
else
case(cstate)
RETRY_CHECK : retry_check_done_slide <= retry_check_done_slide << 1;
default : retry_check_done_slide <= 3'b001;
endcase
assign retry_check_done = retry_check_done_slide[2];
//---- store xlate_done response in RAM, addressed by afutag ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
ram_xlate_done_wena <= 1'b0;
ram_xlate_done_addra <= 6'd0;
ram_xlate_done_dina <= 4'd0;
end
else
begin
ram_xlate_done_wena <= rsp_den && (rsp_xlate_done_retry_backoff || rsp_xlate_done_retry_immediate);
ram_xlate_done_addra <= rsp_tag;
ram_xlate_done_dina <= {rsp_xlate_done_retry_backoff, rsp_xlate_done_retry_immediate, rsp_pos};
end
//---- RAM for xlate_done responses ----
ram_simple_dual #(4,`TAGW) mram_xlate_done (
.clk (clk ),
.ena (1'b1 ),
.enb (1'b1 ),
.wea (ram_xlate_done_wena ),
.addra (ram_xlate_done_addra),
.dia (ram_xlate_done_dina ),
.addrb (ram_xlate_done_addrb),
.dob (ram_xlate_done_doutb)
);
//---- get xlate_done response out of RAM, addressed by afutag from retry FIFO ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
ram_xlate_done_addrb <= 6'd0;
else
ram_xlate_done_addrb <= fifo_retry_dout[6:0];
assign rsp_is_xlate_done_retry_backoff = ram_xlate_done_doutb[3];
assign rsp_is_xlate_done_retry_immediate = ram_xlate_done_doutb[2];
//---- notify valid retry ----
assign rty_valid = rty_rdy && (cstate == RETRY_NOW);
//---- store the last retry tag to prevent repetitive retry on the same tag ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
last_rty_tag <= 7'd0;
last_rty_pos <= 2'd0;
end
else if(rty_valid)
begin
last_rty_tag <= rty_tag;
last_rty_pos <= rty_pos;
end
//---- allow repetitive tag retry since retry's response could be another retry ----
// 2 senarios of possible repetitive retry:
// 1) single tag, full
// 2) multiple responses with the same tag, partial
// for partial, enable retry when new partial commands start to fire; otherwise when FIFO's empty
always@(posedge clk or negedge rst_n)
if(~rst_n)
rep_retry_enable <= 1'b0;
else if(rty_valid)
rep_retry_enable <= 1'b0;
else if(prt_cmd_start || (fifo_retry_empty && ~rsp_is_partial))
rep_retry_enable <= 1'b1;
//---- indicate no retry request in queue ----
assign rty_busy = ~fifo_retry_empty;
wire cstate_h01_h02 = ((cstate == IDLE) && (nstate == RETRY_RELEASE));
wire cstate_h02_h04 = ((cstate == RETRY_RELEASE) && (nstate == RETRY_CHECK));
wire cstate_h04_h01 = ((cstate == RETRY_CHECK) && (nstate == IDLE));
wire cstate_h04_h08 = ((cstate == RETRY_CHECK) && (nstate == RETRY_BACKOFF));
wire cstate_h04_h10 = ((cstate == RETRY_CHECK) && (nstate == RETRY_NOW));
wire cstate_h10_h01 = ((cstate == RETRY_NOW) && (nstate == IDLE));
// psl default clock = (posedge clk);
//==== PSL COVERAGE ==============================================================================
// psl PRT_CSTATE_H01_H02 : cover {(cstate_h01_h02)};
// psl PRT_CSTATE_H02_H04 : cover {(cstate_h02_h04)};
// psl PRT_CSTATE_H04_H01 : cover {(cstate_h04_h01)};
// psl PRT_CSTATE_H04_H08 : cover {(cstate_h04_h08)};
// psl PRT_CSTATE_H04_H10 : cover {(cstate_h04_h10)};
// psl PRT_CSTATE_H10_H01 : cover {(cstate_h10_h01)};
//==== PSL COVERAGE ==============================================================================
endmodule |
module brdg_wr_order_mng_array
(
input clk ,
input rst_n ,
//reserve interface
input rsv_valid ,
input [0001:0] rsv_pos ,
input [`TAGW-1:0] rsv_tag ,
input rsv_last ,
input rsv_first, //TODO: used only in wr channel add rsv_first for write channel
input [`IDW-1:0] rsv_axi_id,
//response docode interface
input rsp_valid ,
input [`TAGW-1:0] rsp_tag ,
input [0002:0] rsp_code ,
input [0001:0] rsp_pos ,
//output signals for recycle tag buffer
output wire rec_valid ,
output wire [`TAGW-1:0] rec_tag ,
//interface with axi_slave module
output wire ret_valid ,
output [`TAGW-1:0] ret_tag ,
`ifndef ENABLE_ODMA
output reg [`IDW-1:0] ret_axi_id,
output reg ret_resp ,
output reg ret_last , // signal only for read
`else
output wire [`IDW-1:0] ret_axi_id,
output wire ret_resp ,
output wire ret_last , // signal only for read
`endif
`ifndef ENABLE_ODMA
input ret_ready
`else
input [0031:0] ret_ready
`endif
//interface with context update module
//output wire last_context_cleared
);
parameter IDN = 2**`IDW; // number of axi id supported
parameter ARYD = 2**`TAGW; // array depth
//--------------------------------------------------------------------------------------------------------
//-------------------------------- beat information array ------------------------------------------------
//-------------------------reserve information for all inflight beats ------------------------------------
//--------------------------------------------------------------------------------------------------------
// basic elements
reg beat_info_ev[ARYD-1:0] ; // entry valid
reg [1:0] beat_info_rv[ARYD-1:0] ; // response valid
reg beat_info_rc[ARYD-1:0] ; // response code: 0 for good response, 1 for error response
reg [`TAGW-1:0] beat_info_nxt_ptr[ARYD-1:0] ; // next tag pointer, pointer to the entry of the next beat
reg beat_info_nptr_v[ARYD-1:0] ; // indicate whether the nxt_ptr poniter is valid or not
reg [`IDW-1:0] beat_info_axi_id[ARYD-1:0] ; // axi id
reg beat_info_last[ARYD-1:0] ; // indicate this is the last beat of a burst
// related logic signals
wire [ARYD-1:0] reserve_beat_info_entry ;
wire [ARYD-1:0] clear_beat_info_entry ;
wire [ARYD-1:0] reserve_nxt_ptr ;
wire [ARYD-1:0] current_entry_rsp_rdy ;
//wire [ARYD-1:0] beat_info_valid_vector ;
//--------------------------------------------------------------------------------------------------------
//---------------------------------- previous ptr array --------------------------------------------------
//-------------------------reserve tag of the last input beat for each axi id ----------------------------
//--------------------------------------------------------------------------------------------------------
// basic elements
reg [`TAGW-1:0] pre_ptr[IDN-1:0] ; // previous tag poniter, record entry tag of the previous input beat
reg pre_ptr_valid[IDN-1:0] ; // indicate whether the pre_ptr pointer is valid or not
// related logic signals
wire [IDN-1:0] reserve_pre_ptr;
wire [IDN-1:0] clear_pre_ptr;
reg rsv_valid_latch;
reg [`TAGW-1:0] rsv_pre_ptr_latch ; // latch to buffer the previous point every time when there is a beat input
reg [`TAGW-1:0] rsv_tag_latch ; // latch to buffer the current tag of the input beat
reg [`IDW-1:0] rsv_axi_id_latch ;
reg rsv_beat_nh_latch ; // indicate the beat come in the previous cycle is not a head beat
wire [IDN-1:0] rsv_valid_latch_for_idx ;
//--------------------------------------------------------------------------------------------------------
//----------------------------------- head beat tag array ------------------------------------------------
//---------------------------reserve tag of head beat for each axi id ------------------------------------
//--------------------------------------------------------------------------------------------------------
// basic elements
reg [`TAGW-1:0] head_beat_tag[IDN-1:0] ; // head beat array, record the head beat tag of each AXI ID
reg head_beat_tag_valid[IDN-1:0]; // head beat valid
// related logic signals
wire [IDN-1:0] reserve_new_head_beat ;
wire [IDN-1:0] update_head_beat ;
wire [IDN-1:0] clear_head_beat ;
//--------------------------------------------------------------------------------------------------------
//----------------------------------- ready to response latch array --------------------------------------
//---------------------------latch information of the ready to respone beats for each axi id -------------
//--------------------------------------------------------------------------------------------------------
// basic elements
reg [IDN-1:0] rdy_to_rsp_valid ;
reg [IDN-1:0] rdy_to_rsp_rc ; // response code, 0 for good response, 1 for error response
reg [IDN-1:0] rdy_to_rsp_last ; // indicate this is the last beat of a burst
reg [`TAGW-1:0] rdy_to_rsp_tag[IDN-1:0] ; // tag of the ready to response beat
// related logic signals
wire [IDN-1:0] rdy_to_get_rsp ;
wire [IDN-1:0] store_rsp_in ;
wire [IDN-1:0] load_rsp_out ;
wire [IDN-1:0] rdy_for_next_stage ;
wire [IDN*`TAGW-1:0] rsp_tag_vector ;
wire [IDN*`TAGW-1:0] tag_mask_vector ;
wire [IDN*`IDW-1:0] rsp_axi_id_vector ;
wire [IDN*`IDW-1:0] axi_id_mask_vector ;
wire [`TAGW*IDN-1:0] tag_permute_vector ;
wire [`IDW*IDN-1:0] axi_id_permute_vector ;
wire [IDN*`IDW-1:0] rdy_to_rsp_axi_id ;
wire nretry_rsp_valid; //response valid and it is a good or bad response, not retry
wire nretry_rsp_code; //0 for good response, 1 for bad response
wire [ARYD-1:0] rsp_hi_valid;
wire [ARYD-1:0] rsp_lo_valid;
wire [ARYD-1:0] rsp_in;
wire [IDN-1:0] priority_tmp_a;
wire [IDN-1:0] priority_tmp_b;
wire rsp_latch_rdy;
reg [IDN-1:0] load_rsp_out_latch;
wire rsp_latch_valid_o;
wire [`TAGW-1:0] rsp_latch_tag_o;
wire rsp_latch_rc_o;
wire rsp_latch_last_o;
wire [`IDW-1:0] rsp_latch_axi_id_o;
wire select_a;
reg ret_valid_latch;
`ifndef ENABLE_ODMA
reg [`TAGW-1:0] ret_tag;
`else
wire [`TAGW-1:0] ret_tag;
`endif
integer p;
genvar i;
genvar j;
//############################################################################################
//#----beat info array, restore the information of a beat. each entry of this array has -----#
//#----the following fields: -----#
//#---- ------------------------------------- -----#
//#---- |ev|rv|rc|nptr_v|nxt_ptr|axi_id|last| -----#
//#---- ------------------------------------- -----#
//#---- beat_info_ev: 1 bit to indicate whether this entry is valid or not -----#
//#---- beat_info_rv: 2 bit response valid information -----#
//#---- beat_info_rc: 1 bit response code information. 0 for good and 1 for error -----#
//#---- beat_info_nptr_v: 1 bit to indicate whether the nxt_ptr in this entry is valid -----#
//#---- beat_info_nxt_ptr: `TAGW bit for tag of the next beat -----#
//#---- beat_info_axi_id: `IDW bit for axi id -----#
//#---- beat_info_last: 1 bit to indicate whether this is the last beat in a burst -----#
//############################################################################################
//----------when a beat come in: set ev and reserve axi_id, last -------------
//----------other field in this array is reserved/updated in later stage-------------
wire [ARYD-1:0] entry_valid_for_debug; //signal only for debug
generate
for(i=0; i<ARYD; i=i+1)
begin:beat_info_ev_array
assign reserve_beat_info_entry[i] = rsv_valid && (rsv_tag == i);
//assign beat_info_valid_vector[i] = beat_info_ev[i];
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_ev[i] <= 0;
else if(reserve_beat_info_entry[i])
beat_info_ev[i] <= 1;
else if(clear_beat_info_entry[i])
beat_info_ev[i] <= 0;
end
assign clear_beat_info_entry[i] = rdy_to_get_rsp[beat_info_axi_id[i]] && //rdy_to_rsp_latch ready to get rsp beat
current_entry_rsp_rdy[i] && //current entry is ready to rsp
(head_beat_tag[beat_info_axi_id[i]] == i) && //current entry is head beat
(head_beat_tag_valid[beat_info_axi_id[i]]);
assign entry_valid_for_debug[i] = beat_info_ev[i]; //signal only for debug
end
endgenerate
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
for(p=0; p<ARYD; p=p+1)
begin
beat_info_axi_id[p] <= 0;
end
else if(rsv_valid)
beat_info_axi_id[rsv_tag] <= rsv_axi_id;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
for(p=0; p<ARYD; p=p+1)
begin
beat_info_last[p] <= 0;
end
else if(rsv_valid)
beat_info_last[rsv_tag] <= rsv_last;
end
//############################################################################################
//#---- previous pointer array, restore the tag of the previous beat in the same AXI ID -----#
//#---- Every time when a beat come, do the following: -----#
//#---- 1) store the tag of the current beat to pre_ptr_array -----#
//#---- 2) read out the tag of the previous beat from pre_ptr array and -----#
//#---- sotre it to the rsv_pre_ptr_latch -----#
//#---- 3) store the tag of the current beat to rsv_tag_latch -----#
//#---- 4) use rsv_pre_ptr_latch as address, sotre rsv_tag_latch to certain entry in -----#
//#---- beat_info_nxt_ptr array -----#
//############################################################################################
//----1) sotre tag of current beat to pre_ptr_array and ---------------
//---- release the entry when response last beat to lcl ---------------
generate
for(j=0; j<IDN; j=j+1)
begin:pre_ptr_array
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
pre_ptr_valid[j] <= 0;
else if(reserve_pre_ptr[j])
pre_ptr_valid[j] <= 1;
else if(clear_pre_ptr[j])
pre_ptr_valid[j] <= 0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
pre_ptr[j] <= 0;
else if(reserve_pre_ptr[j])
pre_ptr[j] <= rsv_tag;
end
assign reserve_pre_ptr[j] = rsv_valid && (rsv_axi_id == j);
//if the pre_ptr ponit to a head beat entry that is to be cleared, this pre_ptr entry should also be cleared
assign clear_pre_ptr[j] = clear_head_beat[j] && (!rsv_valid_latch_for_idx[j]);
assign rsv_valid_latch_for_idx[j] = rsv_valid_latch && (rsv_axi_id_latch == j);
end
endgenerate
//----2) read out the tag of the previous beat from pre_ptr array and
//---- sotre it to the rsv_pre_ptr_latch
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_pre_ptr_latch <= 0;
else if(rsv_valid)
rsv_pre_ptr_latch <= pre_ptr[rsv_axi_id];
end
//----3) store the tag of the current beat to rsv_tag_latch
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_tag_latch <= 0;
else if(rsv_valid)
rsv_tag_latch <= rsv_tag;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_axi_id_latch <= 0;
else if(rsv_valid)
rsv_axi_id_latch <= rsv_axi_id;
end
//----4) use rsv_pre_ptr_latch as address, sotre rsv_tag_latch to certain
//---- entry in beat_info_nxt_ptr array
generate
for(i=0; i<ARYD; i=i+1)
begin:beat_info_nptr_array
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_nxt_ptr[i] <= 0;
else if(reserve_nxt_ptr[i])
beat_info_nxt_ptr[i] <= rsv_tag_latch;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_nptr_v[i] <= 0;
else if(clear_beat_info_entry[i])
beat_info_nptr_v[i] <= 0;
else if(reserve_nxt_ptr[i])
beat_info_nptr_v[i] <= 1;
end
assign reserve_nxt_ptr[i] = rsv_beat_nh_latch && (rsv_pre_ptr_latch == i);
end
endgenerate
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_valid_latch <= 0;
else
rsv_valid_latch <= rsv_valid;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_beat_nh_latch <= 0;
else
rsv_beat_nh_latch <= rsv_valid && pre_ptr_valid[rsv_axi_id] && (!clear_pre_ptr[rsv_axi_id]);
end
//############################################################################################
//#--------- Head beat tag array: store head beat tag for each axi id ----------#
//#--------- Can be updated in 3 conditions: ----------#
//#--------- 1) A head beat of an axi id is input and should be reserved: ----------#
//#--------- a) a beat is input and it has no pre_ptr, it should be head beat ----------#
//#--------- b) a beat is input. Its pre_ptr is head beat and will be cleared ----------#
//#--------- in this cycle. This input beat should be new head beat ----------#
//#--------- c) a beat is input and has been reserved to beat info array in ----------#
//#--------- previous cycle. It should be write as nxt_ptr of its pre_ptr ----------#
//#--------- in this cycle. But its pre_ptr is ready to response and will ----------#
//#--------- be cleared in this cycle. In this condition, this beat will ----------#
//#--------- not be reserved to nxt_ptr entry of its pre_ptr but will be ----------#
//#--------- reserved as head beat. ----------#
//#--------- 2) A head beat is responsed to lcl and its nxt_ptr should be ----------#
//#--------- updated as head beat ----------#
//#--------- 3) A head beat is responsed to lcl and it has no ----------#
//#--------- nxt_ptr, this head beat tag array entry should be cleared ----------#
//############################################################################################
generate
for(j=0; j<IDN; j=j+1)
begin:head_beat_tag_array
assign reserve_new_head_beat[j] = rsv_valid_latch_for_idx[j] && (!rsv_beat_nh_latch || clear_head_beat[j]);
assign update_head_beat[j] = store_rsp_in[j] && beat_info_nptr_v[head_beat_tag[j]];
assign clear_head_beat[j] = store_rsp_in[j] && (!beat_info_nptr_v[head_beat_tag[j]]);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
head_beat_tag_valid[j] <= 0;
else if(reserve_new_head_beat[j])
head_beat_tag_valid[j] <= 1;
else if(clear_head_beat[j])
head_beat_tag_valid[j] <= 0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
head_beat_tag[j] <= 0;
else if(reserve_new_head_beat[j])
head_beat_tag[j] <= rsv_tag_latch;
else if(update_head_beat[j])
head_beat_tag[j] <= beat_info_nxt_ptr[head_beat_tag[j]];
end
end
endgenerate
//############################################################################################
//#----beat info array, restore the information of a beat. 1 entry of this array has -----#
//#----the following fields: -----#
//#---- ------------------------------------- -----#
//#---- |ev|rv|rc|nptr_v|nxt_ptr|axi_id|last| -----#
//#---- ------------------------------------- -----#
//#---- beat_info_ev: 1 bit to indicate whether this entry is valid or not -----#
//#---- beat_info_rv: 2 bit response valid information -----#
//#---- beat_info_rc: 1 bit response code information. 0 for good and 1 for error -----#
//#---- beat_info_nptr_v: 1 bit to indicate whether the nxt_ptr in this entry is valid -----#
//#---- beat_info_nxt_ptr: `TAGW bit for tag of the next beat -----#
//#---- beat_info_axi_id: `IDW bit for axi id -----#
//#---- beat_info_last: 1 bit to indicate whether this is the last beat in a burst -----#
//############################################################################################
//----------when a response come in: set rv and rc field -------------
assign nretry_rsp_valid = rsp_valid;
assign nretry_rsp_code = rsp_code[2];
generate
for(i=0; i<ARYD; i=i+1)
begin:beat_info_rsp_array
assign rsp_in[i] = nretry_rsp_valid && (rsp_tag == i);
assign rsp_hi_valid[i] = rsp_in[i] && rsp_pos[1];
assign rsp_lo_valid[i] = rsp_in[i] && rsp_pos[0];
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_rv[i][0] <= 0;
else if(reserve_beat_info_entry[i])
beat_info_rv[i][0] <= ~rsv_pos[0];
else if(rsp_lo_valid[i])
beat_info_rv[i][0] <= 1;
else if(clear_beat_info_entry[i])
beat_info_rv[i][0] <= 0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_rv[i][1] <= 0;
else if(reserve_beat_info_entry[i])
beat_info_rv[i][1] <= ~rsv_pos[1];
else if(rsp_hi_valid[i])
beat_info_rv[i][1] <= 1;
else if(clear_beat_info_entry[i])
beat_info_rv[i][1] <= 0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
beat_info_rc[i] <= 0;
else if(rsp_in[i])
beat_info_rc[i] <= beat_info_rc[i] | nretry_rsp_code;
else if(clear_beat_info_entry[i])
beat_info_rc[i] <= 0;
end
assign current_entry_rsp_rdy[i] = beat_info_rv[i][0] && beat_info_rv[i][1];
end
endgenerate
//############################################################################################
//#---- ready to response latch array: -----#
//#---- latch information of the ready to respone beats for each axi id -----#
//#---- 1) Everytime when the head beat tag array want to update or clear a entry, -----#
//#---- store the related beat to this latch -----#
//#---- 2) For all the beat in this latch array, select one to response out, -----#
//#---- the priority is decided as below: -----#
//#---- a) For all the axi_id entry in this array, if one entry is responsed out in -----#
//#---- the previous cycle, this entry will be considered with the highest -----#
//#---- prority in this cycle -----#
//#---- b) If a) is not the case, then choose the entry with the minimum axi id as -----#
//#---- the one with highest priority -----#
//############################################################################################
// a)
`ifndef ENABLE_ODMA
assign rdy_for_next_stage = rdy_to_rsp_valid;
`else
assign rdy_for_next_stage = rdy_to_rsp_valid & ret_ready;
`endif
assign priority_tmp_a = load_rsp_out_latch;
assign select_a = |(load_rsp_out_latch & rdy_for_next_stage);
// b) The right most set bit is picked as the suitable entry to response
// The algorithm:
// 1100 = i
// 0011 = ~i
// 0100 = -i (~i + 1)
// 0100 = -i&i
assign priority_tmp_b = ( -rdy_for_next_stage) & rdy_for_next_stage;
assign load_rsp_out = select_a ? priority_tmp_a : priority_tmp_b;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
load_rsp_out_latch <= 0;
`ifndef ENABLE_ODMA
else if(rsp_latch_rdy && (|rdy_for_next_stage))
load_rsp_out_latch <= load_rsp_out;
`else
else if(|rdy_for_next_stage)
load_rsp_out_latch <= load_rsp_out;
`endif
end
generate
for(j=0; j<IDN; j=j+1)
begin:rdy_to_rsp_latch_array
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rdy_to_rsp_valid[j] <= 0;
else if(store_rsp_in[j])
rdy_to_rsp_valid[j] <= 1;
`ifndef ENABLE_ODMA
else if(load_rsp_out[j] && rsp_latch_rdy)
rdy_to_rsp_valid[j] <= 0;
`else
else if(load_rsp_out[j])
rdy_to_rsp_valid[j] <= 0;
`endif
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rdy_to_rsp_rc[j] <= 0;
rdy_to_rsp_last[j] <= 0;
rdy_to_rsp_tag[j] <= 0;
end
else if(store_rsp_in[j])
begin
rdy_to_rsp_rc[j] <= beat_info_rc[head_beat_tag[j]];
rdy_to_rsp_last[j] <= beat_info_last[head_beat_tag[j]];
rdy_to_rsp_tag[j] <= head_beat_tag[j];
end
end
assign store_rsp_in[j] = head_beat_tag_valid[j] && rdy_to_get_rsp[j] && current_entry_rsp_rdy[head_beat_tag[j]];
`ifndef ENABLE_ODMA
assign rdy_to_get_rsp[j] = !rdy_to_rsp_valid[j] || (load_rsp_out[j] && rsp_latch_rdy);
`else
assign rdy_to_get_rsp[j] = !rdy_to_rsp_valid[j] || load_rsp_out[j];
`endif
end
endgenerate
//############################################################################################
//#---- Output response signals -----#
//############################################################################################
`ifndef ENABLE_ODMA
assign rsp_latch_rdy = !ret_valid_latch || ret_ready;
`endif
assign rsp_latch_valid_o = |load_rsp_out;
assign rsp_latch_rc_o = |(load_rsp_out & rdy_to_rsp_rc);
assign rsp_latch_last_o = |(load_rsp_out & rdy_to_rsp_last);
generate
for(i=0; i<IDN; i=i+1)
begin:rsp_signal_gen
assign tag_mask_vector[(i+1)*`TAGW-1:i*`TAGW] = {`TAGW{load_rsp_out[i]}};
assign axi_id_mask_vector[(i+1)*`IDW-1:i*`IDW] = {`IDW{load_rsp_out[i]}};
assign rdy_to_rsp_axi_id[(i+1)*`IDW-1:i*`IDW] = i;
end
endgenerate
generate
for(i=0; i<IDN; i=i+1)
begin:rsp_permute_gen
for(j=0; j<`TAGW; j=j+1)
begin:tag_value_vector_gen
assign tag_permute_vector[j*IDN+i] = rdy_to_rsp_tag[i][j] & tag_mask_vector[i*`TAGW+j];
end
for(j=0; j<`IDW; j=j+1)
begin:id_value_vector_gen
assign axi_id_permute_vector[j*IDN+i] = rdy_to_rsp_axi_id[i*`IDW+j] & axi_id_mask_vector[i*`IDW+j];
end
end
endgenerate
generate
for(j=0; j<`TAGW; j=j+1)
begin:rsp_tag_gen
assign rsp_latch_tag_o[j] = |tag_permute_vector[(j+1)*IDN-1:j*IDN];
end
endgenerate
generate
for(j=0; j<`IDW; j=j+1)
begin:rsp_axi_id_gen
assign rsp_latch_axi_id_o[j] = |axi_id_permute_vector[(j+1)*IDN-1:j*IDN];
end
endgenerate
`ifndef ENABLE_ODMA
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
ret_valid_latch <= 0;
else if(rsp_latch_valid_o)
ret_valid_latch <= 1;
else if(ret_ready)
ret_valid_latch <= 0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
ret_tag <= 0;
ret_axi_id <= 0;
ret_resp <= 0;
ret_last <= 0;
end
else if(rsp_latch_valid_o && rsp_latch_rdy)
begin
ret_tag <= rsp_latch_tag_o;
ret_axi_id <= rsp_latch_axi_id_o;
ret_resp <= rsp_latch_rc_o;
ret_last <= rsp_latch_last_o;
end
end
assign rec_valid = ret_valid_latch && ret_ready;
assign rec_tag = ret_tag;
assign ret_valid = ret_valid_latch && ret_last;
`else
assign rec_valid = rsp_latch_valid_o;
assign rec_tag = rsp_latch_tag_o;
assign ret_valid = rsp_latch_valid_o && rsp_latch_last_o;
assign ret_tag = rsp_latch_tag_o;
assign ret_axi_id = rsp_latch_axi_id_o;
assign ret_resp = rsp_latch_rc_o;
assign ret_last = rsp_latch_last_o;
`endif
//==============================================================================================================
//================================ psl coverage =======================================
//==============================================================================================================
// psl default clock = (posedge clk);
wire [IDN-1:0] pre_ptr_reserve_at_clean;
wire [IDN-1:0] rsv_beat_at_clear_head;
wire [IDN-1:0] rsv_beat_at_idle_head;
wire [IDN-1:0] rsv_head_at_clear;
wire [IDN-1:0] store_rsp_at_loadout;
generate
for(j=0; j<IDN; j=j+1)
begin:id_array_cover
assign pre_ptr_reserve_at_clean[j] = reserve_pre_ptr[j] && clear_pre_ptr[j];
assign rsv_beat_at_clear_head[j] = rsv_valid_latch_for_idx[j] && clear_head_beat[j];
assign rsv_beat_at_idle_head[j] = rsv_valid_latch_for_idx[j] && (!rsv_beat_nh_latch);
assign rsv_head_at_clear[j] = reserve_new_head_beat[j] && clear_head_beat[j];
assign store_rsp_at_loadout[j] = store_rsp_in[j] && load_rsp_out[j] && rsp_latch_rdy;
//---- make sure we have checked the condition when reserve_pre_ptr and clear_pre_ptr
//---- happen in the same time and they are handled by the right priority
//---- if we can not cover this case for all 32 axi ids, at least cover it for id
// psl PRE_PTR_RESERVE_AT_CLEAN : cover {(reserve_pre_ptr[j] && clear_pre_ptr[j])};
//---- make sure we have checked the condition when reserve a new beat for idx and its
//---- head beat is beening cleared at the same time, so that the new beat should be
//---- stored to the head beat array entry for this id
//---- if we can not cover this case for all 32 axi ids, at least cover it for id
// psl RSV_BEAT_AT_CLEAR_HEAD : cover {(rsv_valid_latch_for_idx[j] && clear_head_beat[j])};
//---- make sure we have checked the condition when reserve a new beat for idx and this
//---- axi id has no head beat now, so that the new beat should be
//---- stored to the head beat array entry for this id
//---- if we can not cover this case for all 32 axi ids, at least cover it for id
// psl RSV_BEAT_AT_IDLE_HEAD : cover {(rsv_valid_latch_for_idx[j] && (!rsv_beat_nh_latch))};
//---- make sure we have checked the condition when reserve a new head beat for idx and
//---- the previous head beat for this id is been cleared at the same time and they are handled
//---- by the right priority
// psl RSV_HEAD_AT_CLEAR : cover {(reserve_new_head_beat[j] && clear_head_beat[j])};
//---- make sure we have checked the condition when store rsp in response latch array and
//---- load rsp out of this array happen at the same time and this 2 actions are handled by
//---- the right priority
// psl STORE_RSP_AT_LOADOUT_ARRAY : cover {(store_rsp_in[j] && load_rsp_out[j] && rsp_latch_rdy)};
end
endgenerate
// psl PRE_PTR_RESERVE_AT_CLEAN_SIMPLE : cover {(|pre_ptr_reserve_at_clean[IDN-1:0])};
// psl RSV_BEAT_AT_CLEAR_HEAD_SIMPLE : cover {(|rsv_beat_at_clear_head[IDN-1:0])};
// psl RSV_BEAT_AT_IDLE_HEAD_SIMPLE : cover {(|rsv_beat_at_idle_head[IDN-1:0])};
// psl RSV_HEAD_AT_CLEAR_SIMPLE : cover {(|rsv_head_at_clear[IDN-1:0])};
// psl STORE_RSP_AT_LOADOUT_SIMPLE : cover {(|store_rsp_at_loadout[IDN-1:0])};
wire [ARYD-1:0] clear_beat_at_rsv_nxtp;
generate
for(i=0; i<ARYD; i=i+1)
begin:tag_array_cover
assign clear_beat_at_rsv_nxtp[i] = clear_beat_info_entry[i] && reserve_nxt_ptr[i];
//---- make sure we have checked the condition when clear beat info entry and reserve its nxt_ptr
//---- happens at the same time and these 2 actions are handled in the right priority
// psl CLEAR_BEAT_AT_RSV_NXTP : cover {(clear_beat_info_entry[i] && reserve_nxt_ptr[i])};
end
endgenerate
// psl CLEAR_BEAT_AT_RSV_NXTP_SIMPLE : cover {(|clear_beat_at_rsv_nxtp[ARYD-1:0])};
//---- make sure we have checked the condition when reserve a new beat
//---- and its previous beat is been cleared
// psl RSV_BEAT_AT_CLEAR_PRE : cover {(rsv_valid && pre_ptr_valid[rsv_axi_id] && clear_pre_ptr[rsv_axi_id])};
//---- make sure we have checked the condition when store rsp to ret_xxx registers and load rsp out of these
//---- regsters happen at the same time and store and load are handled in right priority
// psl STORE_RSP_AT_LOADOUT_REG : cover {(rsp_latch_valid_o && ret_ready)};
`ifdef ILA_DEBUG
reg [31:0] rsv_counter ;
reg [31:0] ret_counter ;
reg [31:0] ret_idle_counter ;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
rsv_counter <= 32'b0;
else if (rsv_valid)
rsv_counter <= rsv_counter + 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
ret_counter <= 32'b0;
else if (ret_valid && ret_ready)
ret_counter <= ret_counter + 1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(rst_n)
ret_idle_counter <= 32'b0;
else if(ret_valid && ret_ready)
ret_idle_counter <= 32'b0;
else
ret_idle_counter <= ret_idle_counter + 1'b1;
end
reg [31:0] rsv_counter_sync1 ;
reg [31:0] ret_counter_sync1 ;
reg [31:0] ret_idle_counter_sync1 ;
reg rsv_valid_sync1 ;
reg [`TAGW-1:0] rsv_tag_sync1 ;
reg rsv_last_sync1 ;
reg rsv_first_sync1 ;
reg [`IDW-1:0] rsv_axi_id_sync1 ;
reg rsp_valid_sync1 ;
reg [`TAGW-1:0] rsp_tag_sync1 ;
reg ret_valid_latch_sync1 ;
reg [`IDW-1:0] ret_axi_id_sync1 ;
reg ret_last_sync1 ;
reg ret_ready_sync1 ;
reg [ARYD-1:0] entry_valid_for_debug_sync1 ;
reg [31:0] rsv_counter_sync2 ;
reg [31:0] ret_counter_sync2 ;
reg [31:0] ret_idle_counter_sync2 ;
reg rsv_valid_sync2 ;
reg [`TAGW-1:0] rsv_tag_sync2 ;
reg rsv_last_sync2 ;
reg rsv_first_sync2 ;
reg [`IDW-1:0] rsv_axi_id_sync2 ;
reg rsp_valid_sync2 ;
reg [`TAGW-1:0] rsp_tag_sync2 ;
reg ret_valid_latch_sync2 ;
reg [`IDW-1:0] ret_axi_id_sync2 ;
reg ret_last_sync2 ;
reg ret_ready_sync2 ;
reg [ARYD-1:0] entry_valid_for_debug_sync2 ;
reg [31:0] rsv_counter_sync3 ;
reg [31:0] ret_counter_sync3 ;
reg [31:0] ret_idle_counter_sync3 ;
reg rsv_valid_sync3 ;
reg [`TAGW-1:0] rsv_tag_sync3 ;
reg rsv_last_sync3 ;
reg rsv_first_sync3 ;
reg [`IDW-1:0] rsv_axi_id_sync3 ;
reg rsp_valid_sync3 ;
reg [`TAGW-1:0] rsp_tag_sync3 ;
reg ret_valid_latch_sync3 ;
reg [`IDW-1:0] ret_axi_id_sync3 ;
reg ret_last_sync3 ;
reg ret_ready_sync3 ;
reg [ARYD-1:0] entry_valid_for_debug_sync3 ;
reg [31:0] rsv_counter_sync4 ;
reg [31:0] ret_counter_sync4 ;
reg [31:0] ret_idle_counter_sync4 ;
reg rsv_valid_sync4 ;
reg [`TAGW-1:0] rsv_tag_sync4 ;
reg rsv_last_sync4 ;
reg rsv_first_sync4 ;
reg [`IDW-1:0] rsv_axi_id_sync4 ;
reg rsp_valid_sync4 ;
reg [`TAGW-1:0] rsp_tag_sync4 ;
reg ret_valid_latch_sync4 ;
reg [`IDW-1:0] ret_axi_id_sync4 ;
reg ret_last_sync4 ;
reg ret_ready_sync4 ;
reg [ARYD-1:0] entry_valid_for_debug_sync4 ;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
rsv_counter_sync1 <= 0 ;
ret_counter_sync1 <= 0 ;
ret_idle_counter_sync1 <= 0 ;
rsv_valid_sync1 <= 0;
rsv_tag_sync1 <= 0;
rsv_last_sync1 <= 0;
rsv_first_sync1 <= 0;
rsv_axi_id_sync1 <= 0;
rsp_valid_sync1 <= 0;
rsp_tag_sync1 <= 0;
ret_valid_latch_sync1 <= 0;
ret_axi_id_sync1 <= 0;
ret_last_sync1 <= 0;
ret_ready_sync1 <= 0;
entry_valid_for_debug_sync1 <= 0;
rsv_counter_sync2 <= 0 ;
ret_counter_sync2 <= 0 ;
ret_idle_counter_sync2 <= 0 ;
rsv_valid_sync2 <= 0;
rsv_tag_sync2 <= 0;
rsv_last_sync2 <= 0;
rsv_first_sync2 <= 0;
rsv_axi_id_sync2 <= 0;
rsp_valid_sync2 <= 0;
rsp_tag_sync2 <= 0;
ret_valid_latch_sync2 <= 0;
ret_axi_id_sync2 <= 0;
ret_last_sync2 <= 0;
ret_ready_sync2 <= 0;
entry_valid_for_debug_sync2 <= 0;
rsv_counter_sync3 <= 0 ;
ret_counter_sync3 <= 0 ;
ret_idle_counter_sync3 <= 0 ;
rsv_valid_sync3 <= 0;
rsv_tag_sync3 <= 0;
rsv_last_sync3 <= 0;
rsv_first_sync3 <= 0;
rsv_axi_id_sync3 <= 0;
rsp_valid_sync3 <= 0;
rsp_tag_sync3 <= 0;
ret_valid_latch_sync3 <= 0;
ret_axi_id_sync3 <= 0;
ret_last_sync3 <= 0;
ret_ready_sync3 <= 0;
entry_valid_for_debug_sync3 <= 0;
rsv_counter_sync4 <= 0 ;
ret_counter_sync4 <= 0 ;
ret_idle_counter_sync4 <= 0 ;
rsv_valid_sync4 <= 0;
rsv_tag_sync4 <= 0;
rsv_last_sync4 <= 0;
rsv_first_sync4 <= 0;
rsv_axi_id_sync4 <= 0;
rsp_valid_sync4 <= 0;
rsp_tag_sync4 <= 0;
ret_valid_latch_sync4 <= 0;
ret_axi_id_sync4 <= 0;
ret_last_sync4 <= 0;
ret_ready_sync4 <= 0;
entry_valid_for_debug_sync4 <= 0;
end
else
begin
rsv_counter_sync1 <= rsv_counter;
ret_counter_sync1 <= ret_counter;
ret_idle_counter_sync1 <= ret_idle_counter;
rsv_valid_sync1 <= rsv_valid;
rsv_tag_sync1 <= rsv_tag;
rsv_last_sync1 <= rsv_last;
rsv_first_sync1 <= rsv_first;
rsv_axi_id_sync1 <= rsv_axi_id;
rsp_valid_sync1 <= rsp_valid;
rsp_tag_sync1 <= rsp_tag;
ret_valid_latch_sync1 <= ret_valid_latch;
ret_axi_id_sync1 <= ret_axi_id;
ret_last_sync1 <= ret_last;
ret_ready_sync1 <= ret_ready;
entry_valid_for_debug_sync1 <= entry_valid_for_debug;
rsv_counter_sync2 <= rsv_counter_sync1;
ret_counter_sync2 <= ret_counter_sync1;
ret_idle_counter_sync2 <= ret_idle_counter_sync1;
rsv_valid_sync2 <= rsv_valid_sync1 ;
rsv_tag_sync2 <= rsv_tag_sync1 ;
rsv_last_sync2 <= rsv_last_sync1 ;
rsv_first_sync2 <= rsv_first_sync1 ;
rsv_axi_id_sync2 <= rsv_axi_id_sync1 ;
rsp_valid_sync2 <= rsp_valid_sync1 ;
rsp_tag_sync2 <= rsp_tag_sync1 ;
ret_valid_latch_sync2 <= ret_valid_latch_sync1 ;
ret_axi_id_sync2 <= ret_axi_id_sync1 ;
ret_last_sync2 <= ret_last_sync1 ;
ret_ready_sync2 <= ret_ready_sync1 ;
entry_valid_for_debug_sync2 <= entry_valid_for_debug_sync1;
rsv_counter_sync3 <= rsv_counter_sync2;
ret_counter_sync3 <= ret_counter_sync2;
ret_idle_counter_sync3 <= ret_idle_counter_sync2;
rsv_valid_sync3 <= rsv_valid_sync2 ;
rsv_tag_sync3 <= rsv_tag_sync2 ;
rsv_last_sync3 <= rsv_last_sync2 ;
rsv_first_sync3 <= rsv_first_sync2 ;
rsv_axi_id_sync3 <= rsv_axi_id_sync2 ;
rsp_valid_sync3 <= rsp_valid_sync2 ;
rsp_tag_sync3 <= rsp_tag_sync2 ;
ret_valid_latch_sync3 <= ret_valid_latch_sync2 ;
ret_axi_id_sync3 <= ret_axi_id_sync2 ;
ret_last_sync3 <= ret_last_sync2 ;
ret_ready_sync3 <= ret_ready_sync2 ;
entry_valid_for_debug_sync3 <= entry_valid_for_debug_sync2;
rsv_counter_sync4 <= rsv_counter_sync3;
ret_counter_sync4 <= ret_counter_sync3;
ret_idle_counter_sync4 <= ret_idle_counter_sync3;
rsv_valid_sync4 <= rsv_valid_sync3 ;
rsv_tag_sync4 <= rsv_tag_sync3 ;
rsv_last_sync4 <= rsv_last_sync3 ;
rsv_first_sync4 <= rsv_first_sync3 ;
rsv_axi_id_sync4 <= rsv_axi_id_sync3 ;
rsp_valid_sync4 <= rsp_valid_sync3 ;
rsp_tag_sync4 <= rsp_tag_sync3 ;
ret_valid_latch_sync4 <= ret_valid_latch_sync3 ;
ret_axi_id_sync4 <= ret_axi_id_sync3 ;
ret_last_sync4 <= ret_last_sync3 ;
ret_ready_sync4 <= ret_ready_sync3 ;
entry_valid_for_debug_sync4 <= entry_valid_for_debug_sync3;
end
end
ila_p190 mila_wr_mng
(
.clk(clk),
.probe0(
//1+ 1+ 6+ 1+ 1+ 5+ 1+ 6+ 1+ 5+ 1+ 1+ 64 = 94
{
rst_n ,//1+ //
rsv_counter_sync4 ,
ret_counter_sync4 ,
ret_idle_counter_sync4 ,
rsv_valid_sync4 ,//1+
rsv_tag_sync4 ,//6+
rsv_last_sync4 ,//1+
rsv_first_sync4 ,//1+
rsv_axi_id_sync4 ,//5+
rsp_valid_sync4 ,//1+
rsp_tag_sync4 ,//6+
ret_valid_latch_sync4 ,//1+
ret_axi_id_sync4 ,//5+
ret_last_sync4 ,//1+
ret_ready_sync4 ,//1+
entry_valid_for_debug_sync4 //64+
}
)
);
`endif
endmodule |
module brdg_command_encode
#(
parameter MODE = 1'b0 //0: write; 1: read
)
(
input clk ,
input rst_n ,
//---- configuration --------------------------
input [011:0] cfg_actag_base ,
input [019:0] cfg_pasid_base ,
input [019:0] cfg_pasid_mask ,
//---- communication with command decoder -----
output prt_cmd_start ,
output prt_cmd_valid ,
output prt_cmd_last ,
input prt_cmd_enable ,
//---- DMA interface ---------------------------
output dma_cmd_ready ,
input dma_cmd_valid ,
input [1023:0] dma_cmd_data ,
input [0127:0] dma_cmd_be ,
input [0063:0] dma_cmd_ea ,
input [`TAGW-1:0] dma_cmd_tag ,
input [`CTXW-1:0] dma_cmd_ctx ,
//---- TLX interface ---------------------------
// command
output reg tlx_cmd_valid ,
output reg [0007:0] tlx_cmd_opcode ,
output reg [0067:0] tlx_cmd_ea_or_obj,
output reg [0015:0] tlx_cmd_afutag ,
output reg [0001:0] tlx_cmd_dl ,
output reg [0002:0] tlx_cmd_pl ,
output [0063:0] tlx_cmd_be ,
output reg [0019:0] tlx_cmd_pasid ,
output reg [0011:0] tlx_cmd_actag ,
output reg [1023:0] tlx_cdata_bus ,
// credit availability
input tlx_cmd_rdy ,
//---- control and status ---------------------
input debug_cnt_clear ,
output reg [0031:0] debug_tlx_cnt_cmd,
output reg [0001:0] fir_fifo_overflow
);
// TLX AP command opcode
localparam [7:0] AFU_TLX_CMD_OPCODE_ASSIGN_ACTAG = 8'b0101_0000; // Assign acTag
localparam [7:0] AFU_TLX_CMD_OPCODE_RD_WNITC = 8'b0001_0000; // Read with no intent to cache
localparam [7:0] AFU_TLX_CMD_OPCODE_RD_WNITC_N = 8'b0001_0100; // Read with no intent to cache
localparam [7:0] AFU_TLX_CMD_OPCODE_PR_RD_WNITC = 8'b0001_0010; // Partial read with no intent to cache
localparam [7:0] AFU_TLX_CMD_OPCODE_PR_RD_WNITC_N = 8'b0001_0110; // Partial read with no intent to cache
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_W = 8'b0010_0000; // DMA Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_W_N = 8'b0010_0100; // DMA Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_PR_W = 8'b0011_0000; // DMA Partial Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_PR_W_N = 8'b0011_0100; // DMA Partial Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_W_BE = 8'b0010_1000; // Byte Enable DMA Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_W_BE_N = 8'b0010_1100; // Byte Enable DMA Write
localparam [7:0] AFU_TLX_CMD_OPCODE_INTRP_REQ = 8'b0101_1000; // Interrupt Request
localparam [7:0] AFU_TLX_CMD_OPCODE_INTRP_REQ_D = 8'b0101_1010; // Interrupt Request
localparam [7:0] AFU_TLX_CMD_OPCODE_XLATE_TOUCH = 8'b0111_1000; // Address translation prefetch
localparam [7:0] AFU_TLX_CMD_OPCODE_XLATE_TOUCH_N = 8'b0111_1001; // Address translation prefetch
reg fifo_prt_info_wr_en;
reg fifo_prt_data_wr_en;
reg [0202:00] fifo_prt_info_din;
reg [1023:00] fifo_prt_data_din;
wire fifo_prt_info_rd_en;
wire fifo_prt_data_rd_en;
wire [0202:00] fifo_prt_info_dout;
wire [1023:00] fifo_prt_data_dout;
wire [0004:00] fifo_prt_info_count;
reg [0202:00] fifo_prt_info_dout_sync;
reg [0511:00] fifo_prt_data_dout_h_sync;
wire fifo_prt_info_empty;
wire fifo_prt_info_dv;
reg [0063:00] strobe;
reg strobe_valid;
wire partial_l;
wire partial_h;
reg [`TAGW-1:00] partial_tag;
reg [`CTXW-1:00] partial_ctx;
wire[0004:00] partial_cnt;
reg [0056:00] partial_ea_128B;
reg partial_2nd;
reg [0511:00] partial_data;
wire partial_enable;
reg partial_next_pending;
wire [0002:00] partial_len;
wire partial_valid;
wire partial_done;
reg [0002:00] partial_status;
wire [0005:00] partial_ea_32B;
reg [0004:00] prt_cstate, prt_nstate;
wire prt_h, prt_l;
wire fifo_prt_data_ovfl;
wire fifo_prt_info_ovfl;
parameter IDLE = 5'h01,
RD_PRT_FIFO = 5'h02,
CHECK_PARTIAL = 5'h04,
PARTIAL_L64B = 5'h08,
PARTIAL_H64B = 5'h10;
//---- command type decoding ----
wire cpl_o = &dma_cmd_be[127:64]; // complete valid 64B , odd half (higher half)
wire cpl_e = &dma_cmd_be[063:00]; // complete valid 64B , even half (lower half)
wire nul_o = ~|dma_cmd_be[127:64]; // odd half all zero
wire nul_e = ~|dma_cmd_be[063:00]; // even half all zero
wire prt_o = ~cpl_o && ~nul_o; // partial valid 64B, odd half
wire prt_e = ~cpl_e && ~nul_e; // partial valid 64B, even half
//---- enable bypass mode whenever a complete 64B is available ----
wire bypass_mode = dma_cmd_valid && (cpl_o || cpl_e);
//---- partial mode is activated whenever a partial 64B is detected ----
wire partial_mode = dma_cmd_valid && (prt_o || prt_e);
//---- toggle down ready when credit is deficient or partial command transmission is taking place or partial FIFO is half full ----
assign dma_cmd_ready = tlx_cmd_rdy && (prt_cstate == IDLE) && ~fifo_prt_info_count[4];
//---- output command when 1) bypass mode for 128B/64B: immediate; 2) partial mode: until partial sequencing's ready ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
tlx_cmd_valid <= 1'b0;
else
tlx_cmd_valid <= bypass_mode || partial_valid;
//---- multiplexer for command outputs ----
// AFUTAG constitution
// __________________________________
// ||f|e|d|c b a|9|8|7 6|5 4 3 2 1 0||
// -----------------------------------
// ^ ^ \___ ___/ ^ \/ |<- tag ->|
// | | V | |
// | | | | |__ for 128B: 11; for a 64B or partial command, 01: lower 64B, 10: higher 64B
// | | | |____ partial done for a single 64B
// | | |__________ counter for partial command associated with a single 64B
// | |________________ 0: normal command, 1: partial command
// |__________________ 0: write, 1: read
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
tlx_cdata_bus <= 1024'd0;
tlx_cmd_ea_or_obj <= 68'd0;
tlx_cmd_dl <= 2'b10;
tlx_cmd_pl <= 3'b000;
tlx_cmd_opcode <= 8'd0;
tlx_cmd_afutag <= 16'd0;
end
// non-partial command: 128B or 64B
else if(bypass_mode)
case({cpl_o,cpl_e})
2'b11 : // 128B command
begin
tlx_cdata_bus <= dma_cmd_data;
tlx_cmd_ea_or_obj <= {4'd0, dma_cmd_ea};
tlx_cmd_dl <= 2'b10;
tlx_cmd_pl <= 3'b000;
tlx_cmd_opcode <= (MODE)? AFU_TLX_CMD_OPCODE_RD_WNITC : AFU_TLX_CMD_OPCODE_DMA_W;
tlx_cmd_afutag <= {MODE, 6'b0, {cpl_o,cpl_e}, dma_cmd_tag};
end
2'b01 : // low 64B command
begin
tlx_cdata_bus <= dma_cmd_data;
tlx_cmd_ea_or_obj <= {4'd0, dma_cmd_ea[63:7],1'b0,6'b0};
tlx_cmd_dl <= 2'b01;
tlx_cmd_pl <= 3'b000;
tlx_cmd_opcode <= (MODE)? AFU_TLX_CMD_OPCODE_RD_WNITC : AFU_TLX_CMD_OPCODE_DMA_W;
tlx_cmd_afutag <= {MODE, 6'b0, {cpl_o,cpl_e}, dma_cmd_tag};
end
2'b10 : // high 64B command
begin
tlx_cdata_bus <= {dma_cmd_data[511:0], dma_cmd_data[1023:512]}; // move valid data in lower 64B
tlx_cmd_ea_or_obj <= {4'd0, dma_cmd_ea[63:7],1'b1,6'b0};
tlx_cmd_dl <= 2'b01;
tlx_cmd_pl <= 3'b000;
tlx_cmd_opcode <= (MODE)? AFU_TLX_CMD_OPCODE_RD_WNITC : AFU_TLX_CMD_OPCODE_DMA_W;
tlx_cmd_afutag <= {MODE, 6'b0, {cpl_o,cpl_e}, dma_cmd_tag};
end
default:;
endcase
// partial command
else
begin
tlx_cdata_bus <= {512'd0, partial_data};
tlx_cmd_ea_or_obj <= {4'b0, partial_ea_128B, prt_h, partial_ea_32B};
tlx_cmd_dl <= 2'b01;
tlx_cmd_pl <= partial_len;
tlx_cmd_opcode <= (MODE)? AFU_TLX_CMD_OPCODE_PR_RD_WNITC : AFU_TLX_CMD_OPCODE_DMA_PR_W;
tlx_cmd_afutag <= {MODE, 1'b1, partial_cnt, {prt_h,prt_l}, partial_tag};
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
tlx_cmd_pasid <= 20'd0;
tlx_cmd_actag <= 12'd0;
end
else if(bypass_mode)
begin
tlx_cmd_pasid <= ((cfg_pasid_base & cfg_pasid_mask) | ({{(20-`CTXW){1'd0}}, dma_cmd_ctx} & ~cfg_pasid_mask));
tlx_cmd_actag <= cfg_actag_base + {{(12-`CTXW){1'd0}},dma_cmd_ctx};
end
else
begin
tlx_cmd_pasid <= ((cfg_pasid_base & cfg_pasid_mask) | ({{(20-`CTXW){1'd0}}, partial_ctx} & ~cfg_pasid_mask));
tlx_cmd_actag <= cfg_actag_base + {{(12-`CTXW){1'd0}},partial_ctx};
end
//=====================================================================================================================================
//
// Partial command handling
// Partial commands attached to a single slot take time. So partial mode information has to be buffered first to cope with the
// situation when a bunch of partial command requests flood in within a short period of time.
// ____
// tlx_cmd_* <=| M |<============================================ dma_cmd_*
// | U | ___________________ ____________ ||
// | X |<=| partial_sequencer |<=| fifo_prt_* |<==
// ---- -------------------- ------------
//
//=====================================================================================================================================
//---- fill in partial information and data in FIFO when non-all-1s be is received ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fifo_prt_info_wr_en <= 1'b0;
fifo_prt_data_wr_en <= 1'b0;
fifo_prt_info_din <= 203'd0;
fifo_prt_data_din <= 1024'd0;
end
else
begin
fifo_prt_info_wr_en <= partial_mode;
fifo_prt_data_wr_en <= partial_mode;
fifo_prt_info_din <= {dma_cmd_ctx, prt_o, prt_e, dma_cmd_tag, dma_cmd_ea[63:7], dma_cmd_be}; //9+1+1+7+57+128=203
fifo_prt_data_din <= dma_cmd_data;
end
//---- FIFO for partial info ----
fifo_sync #(
.DATA_WIDTH (203),
.ADDR_WIDTH (5),
.DISTR(1)
) mfifo_prt_info (
.clk (clk ), // input clk
.rst_n (rst_n ), // input rst
.din (fifo_prt_info_din ), // input [202 : 0] din
.wr_en (fifo_prt_info_wr_en), // input wr_en
.rd_en (fifo_prt_info_rd_en), // input rd_en
.dout (fifo_prt_info_dout ), // output [202 : 0] dout
.empty (fifo_prt_info_empty), // output empty
.count (fifo_prt_info_count), // output [4 : 0] count
.valid (fifo_prt_info_dv ), // output valid
.overflow (fifo_prt_info_ovfl ) // output overflow
);
//---- FIFO for partial data ----
fifo_sync #(
.DATA_WIDTH (1024),
.ADDR_WIDTH (5),
.DISTR(1)
) mfifo_prt_data (
.clk (clk ), // input clk
.rst_n (rst_n ), // input rst
.din (fifo_prt_data_din ), // input [1024 : 0] din
.wr_en (fifo_prt_data_wr_en), // input wr_en
.rd_en (fifo_prt_data_rd_en), // input rd_en
.dout (fifo_prt_data_dout ), // output [1024 : 0] dout
.overflow (fifo_prt_data_ovfl ) // output overflow
);
//---- read out infor and data when the last batch of partial commands have all been sent to TLX ----
assign fifo_prt_info_rd_en = (prt_cstate == RD_PRT_FIFO);
assign fifo_prt_data_rd_en = (prt_cstate == RD_PRT_FIFO);
//---- infor for partial command on higher or lower 64B ----
assign partial_l = fifo_prt_info_dout[192];
assign partial_h = fifo_prt_info_dout[193];
//---- delay FIFO out data once for the 2nd 64B partial command ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fifo_prt_info_dout_sync <= 203'd0;
fifo_prt_data_dout_h_sync <= 512'd0;
end
else if(fifo_prt_info_dv)
begin
fifo_prt_info_dout_sync <= fifo_prt_info_dout;
fifo_prt_data_dout_h_sync <= fifo_prt_data_dout[1023:512];
end
//---- latch information for partial seqencer ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
partial_tag <= {`TAGW{1'b1}};
partial_ea_128B <= 57'd0;
partial_2nd <= 1'b0;
partial_ctx <= {`CTXW{1'b0}};
end
else if(prt_cstate == CHECK_PARTIAL)
begin
partial_tag <= fifo_prt_info_dout[191:185];
partial_ea_128B <= fifo_prt_info_dout[184:128];
partial_2nd <= fifo_prt_info_dout[193];
partial_ctx <= fifo_prt_info_dout[202:194];
end
//---- adjust data position ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_data <= 512'd0;
else if(prt_cstate == CHECK_PARTIAL)
casez({partial_h, partial_l})
2'b?1 : partial_data <= fifo_prt_data_dout[0511:000];
2'b10 : partial_data <= fifo_prt_data_dout[1023:512];
endcase
else if(partial_done)
partial_data <= fifo_prt_data_dout_h_sync;
//---- input strobe to partial sequencer ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
strobe_valid <= 1'b0;
else
strobe_valid <= (prt_cstate == CHECK_PARTIAL) || ((prt_cstate == PARTIAL_L64B) && partial_next_pending && prt_cmd_enable);
always@(posedge clk or negedge rst_n)
if(~rst_n)
strobe <= 64'd0;
else if(prt_cstate == CHECK_PARTIAL)
casez({partial_h, partial_l})
2'b?1 : strobe <= fifo_prt_info_dout[063:00];
2'b10 : strobe <= fifo_prt_info_dout[127:64];
endcase
else if(partial_done)
strobe <= fifo_prt_info_dout_sync[127:64];
//---- enable partial sequencer to work when 1) command credit sufficient; 2) not full command transmission is ongoing ----
assign partial_enable = tlx_cmd_rdy && ~bypass_mode;
//---- next partial 64B pending ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
partial_next_pending <= 1'b0;
else if((prt_cstate == PARTIAL_L64B) && partial_2nd && partial_done)
partial_next_pending <= 1'b1;
else if(prt_cmd_enable)
partial_next_pending <= 1'b0;
//---- partial command sequencing submodule ----
brdg_partial_sequencer mpartial_sequencer (
.clk (clk ),
.rst_n (rst_n ),
.partial_en (partial_enable),
.strobe (strobe ),
.strobe_valid (strobe_valid ),
.partial_len (partial_len ),
.partial_ea (partial_ea_32B),
.partial_cnt (partial_cnt ),
.partial_valid (partial_valid ),
.partial_done (partial_done )
);
//---- output to response decoder ----
assign prt_cmd_valid = partial_valid;
assign prt_cmd_last = partial_done;
//---- indicator of strobe signal starting to decompose ----
assign prt_cmd_start = strobe_valid;
//---- statemachine for partial command handling ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_cstate <= IDLE;
else
prt_cstate <= prt_nstate;
always@*
case(prt_cstate)
IDLE :
if(~fifo_prt_info_empty && prt_cmd_enable)
prt_nstate = RD_PRT_FIFO;
else
prt_nstate = IDLE;
RD_PRT_FIFO :
prt_nstate = CHECK_PARTIAL;
CHECK_PARTIAL :
if(partial_l)
prt_nstate = PARTIAL_L64B;
else if(partial_h)
prt_nstate = PARTIAL_H64B;
else
prt_nstate = CHECK_PARTIAL;
PARTIAL_L64B :
if(partial_done && ~partial_2nd)
begin
if(~fifo_prt_info_empty && prt_cmd_enable)
prt_nstate = RD_PRT_FIFO;
else
prt_nstate = IDLE;
end
else if(partial_next_pending && prt_cmd_enable)
prt_nstate = PARTIAL_H64B;
else
prt_nstate = PARTIAL_L64B;
PARTIAL_H64B :
if(partial_done)
begin
if(~fifo_prt_info_empty && prt_cmd_enable)
prt_nstate = RD_PRT_FIFO;
else
prt_nstate = IDLE;
end
else
prt_nstate = PARTIAL_H64B;
default :
prt_nstate = IDLE;
endcase
//---- current 64B position for partial command ----
assign prt_h = (prt_cstate==PARTIAL_H64B);
assign prt_l = (prt_cstate==PARTIAL_L64B);
wire prt_cstate_h01_h02 = ((prt_cstate == IDLE) && (prt_nstate == RD_PRT_FIFO));
wire prt_cstate_h04_h08 = ((prt_cstate == CHECK_PARTIAL) && (prt_nstate == PARTIAL_L64B));
wire prt_cstate_h04_h10 = ((prt_cstate == CHECK_PARTIAL) && (prt_nstate == PARTIAL_H64B));
wire prt_cstate_h08_h01 = ((prt_cstate == PARTIAL_L64B) && (prt_nstate == IDLE));
wire prt_cstate_h08_h10 = ((prt_cstate == PARTIAL_L64B) && (prt_nstate == PARTIAL_H64B));
wire prt_cstate_h08_h02 = ((prt_cstate == PARTIAL_L64B) && (prt_nstate == RD_PRT_FIFO));
wire prt_cstate_h10_h01 = ((prt_cstate == PARTIAL_H64B) && (prt_nstate == IDLE));
wire prt_cstate_h10_h02 = ((prt_cstate == PARTIAL_H64B) && (prt_nstate == RD_PRT_FIFO));
//=================================================================================================================
// STATUS output for SNAP registers
//=================================================================================================================
//---- DEBUG registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
debug_tlx_cnt_cmd <= 32'd0;
end
else if (debug_cnt_clear)
begin
debug_tlx_cnt_cmd <= 32'd0;
end
else if (tlx_cmd_valid)
begin
debug_tlx_cnt_cmd <= debug_tlx_cnt_cmd + 32'd1;
end
//---- FAULT ISOLATION REGISTER ----
reg fir_fifo_prt_data_overflow;
reg fir_fifo_prt_info_overflow;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fir_fifo_prt_data_overflow <= 1'b0;
fir_fifo_prt_info_overflow <= 1'b0;
fir_fifo_overflow <= 2'b0;
end
else
begin
if (fifo_prt_data_ovfl) fir_fifo_prt_data_overflow <= 1'b1;
if (fifo_prt_info_ovfl) fir_fifo_prt_info_overflow <= 1'b1;
fir_fifo_overflow <= {fir_fifo_prt_data_overflow, fir_fifo_prt_info_overflow};
end
// psl default clock = (posedge clk);
//==== PSL ASSERTION ==============================================================================
// psl STROBE_VALID_SINGLE_PULSE : assert always (strobe_valid -> next(~strobe_valid)) report "strobe_valid not a single cycle pulse!";
// psl TLX_COMMAND_PARTIAL_FULL_CONFLICT : assert never (partial_valid && bypass_mode) report "partial and full command conflict! Each time either partial or full command is allowed to send to TLX.";
//==== PSL ASSERTION ==============================================================================
//==== PSL COVERAGE ==============================================================================
// psl DMA_CMD_HC_LC : cover {(dma_cmd_valid && (cpl_o && cpl_e))};
// psl DMA_CMD_HC_LP : cover {(dma_cmd_valid && (cpl_o && prt_e))};
// psl DMA_CMD_HP_LC : cover {(dma_cmd_valid && (prt_o && cpl_e))};
// psl DMA_CMD_HP_LP : cover {(dma_cmd_valid && (prt_o && prt_e))};
// psl DMA_CMD_HC_LN : cover {(dma_cmd_valid && (cpl_o && nul_e))};
// psl DMA_CMD_HN_LC : cover {(dma_cmd_valid && (nul_o && cpl_e))};
// psl DMA_CMD_HP_LN : cover {(dma_cmd_valid && (prt_o && nul_e))};
// psl DMA_CMD_HN_LP : cover {(dma_cmd_valid && (nul_o && prt_e))};
// psl DMA_CMD_HN_LN : cover {(dma_cmd_valid && (nul_o && nul_e))};
// psl PRT_CSTATE_H01_H02 : cover {(prt_cstate_h01_h02)};
// psl PRT_CSTATE_H04_H08 : cover {(prt_cstate_h04_h08)};
// psl PRT_CSTATE_H04_H10 : cover {(prt_cstate_h04_h10)};
// psl PRT_CSTATE_H08_H01 : cover {(prt_cstate_h08_h01)};
// psl PRT_CSTATE_H08_H10 : cover {(prt_cstate_h08_h10)};
// psl PRT_CSTATE_H08_H02 : cover {(prt_cstate_h08_h02)};
// psl PRT_CSTATE_H10_H01 : cover {(prt_cstate_h10_h01)};
// psl PRT_CSTATE_H10_H02 : cover {(prt_cstate_h10_h02)};
// psl TLX_CMD_AC : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_ASSIGN_ACTAG))};
// psl TLX_CMD_RD : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_RD_WNITC ))};
// psl TLX_CMD_RP : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_PR_RD_WNITC ))};
// psl TLX_CMD_WR : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_DMA_W ))};
// psl TLX_CMD_WP : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_DMA_PR_W ))};
// psl TLX_CMD_IN : cover {(tlx_cmd_valid && (tlx_cmd_opcode == AFU_TLX_CMD_OPCODE_INTRP_REQ ))};
// psl PRT_FIFO_ALMOST_FULL : cover {fifo_prt_info_count[4]};
//==== PSL COVERAGE ==============================================================================
endmodule |
module axi_lite_master (
input clk ,
input rst_n ,
//---- master side AXI Lite bus ----
// AXI write address channel
input m_axi_awready ,
output reg [31:0] m_axi_awaddr ,
output [02:0] m_axi_awprot , // not supported
output reg m_axi_awvalid ,
// axi write data channel
input m_axi_wready ,
output reg [31:0] m_axi_wdata ,
output [03:0] m_axi_wstrb , // not supported
output reg m_axi_wvalid ,
// AXI response channel
input [01:0] m_axi_bresp ,
input m_axi_bvalid ,
output reg m_axi_bready ,
// AXI read address channel
input m_axi_arready ,
output reg m_axi_arvalid ,
output reg [31:0] m_axi_araddr ,
output [02:0] m_axi_arprot , // not supported
// AXI read data channel
input [31:0] m_axi_rdata ,
input [01:0] m_axi_rresp ,
output reg m_axi_rready ,
input m_axi_rvalid ,
//---- local bus ----
input lcl_wr , // write enable
input lcl_rd , // read enable
input [31:0] lcl_addr , // write/read address
input [31:0] lcl_din , // write data
output reg lcl_ack , // write data acknowledgement
output reg lcl_rsp , // write/read response: 0: good; 1: bad
output reg [31:0] lcl_dout , // read data
output reg lcl_dv // read data valid
);
assign m_axi_awprot = 3'b000;
assign m_axi_wstrb = 4'b1111;
assign m_axi_arprot = 3'b000;
//=========================================================
// WRITE CHANNEL
// --------------
//
// lcl_wr __/-\______/-\___________
// lcl_din/addr --<=>------<=>-----------
// lcl_ack _______/-\__________/-\__
//=========================================================
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_awvalid <= 1'b0;
else if(lcl_wr)
m_axi_awvalid <= 1'b1;
else if(m_axi_awready)
m_axi_awvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_wvalid <= 1'b0;
else if(lcl_wr)
m_axi_wvalid <= 1'b1;
else if(m_axi_wready)
m_axi_wvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
m_axi_wdata <= 32'd0;
m_axi_awaddr <= 32'd0;
end
else if(lcl_wr)
begin
m_axi_wdata <= lcl_din;
m_axi_awaddr <= lcl_addr;
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_bready <= 1'b0;
else
m_axi_bready <= ~(m_axi_awvalid || m_axi_wvalid);
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_ack <= 1'b0;
else
lcl_ack <= (m_axi_bready && m_axi_bvalid);
//=========================================================
// READ CHANNEL
// --------------
//
// lcl_rd __/-\______/-\___________
// lcl_addr --<=>------<=>-----------
// lcl_dv _______/-\__________/-\__
// lcl_addr -------<=>----------<=>--
//=========================================================
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_arvalid <= 1'b0;
else if(lcl_rd)
m_axi_arvalid <= 1'b1;
else if(m_axi_arready)
m_axi_arvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_rready <= 1'b0;
else if(lcl_rd)
m_axi_rready <= 1'b1;
else if(m_axi_rvalid)
m_axi_rready <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
m_axi_araddr <= 32'd0;
end
else if(lcl_rd)
begin
m_axi_araddr <= lcl_addr;
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_dout <= 32'b0;
else if(m_axi_rready && m_axi_rvalid)
lcl_dout <= m_axi_rdata;
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_dv <= 1'b0;
else
lcl_dv <= (m_axi_rready && m_axi_rvalid);
//=========================================================
// common response for write and read channels
//=========================================================
always@(posedge clk or negedge rst_n)
if(~rst_n)
lcl_rsp <= 1'b0;
else if(m_axi_bready && m_axi_bvalid)
lcl_rsp <= (m_axi_bresp == 2'b00);
else
lcl_rsp <= (m_axi_rresp == 2'b00);
endmodule |
module brdg_tlx_rsp_converter (
input clk_tlx ,
input clk_afu ,
input rst_n ,
//---- TLX side interface --------------------------------
// response
input tlx_afu_resp_valid ,
input [015:0] tlx_afu_resp_afutag ,
input [007:0] tlx_afu_resp_opcode ,
input [003:0] tlx_afu_resp_code ,
input [001:0] tlx_afu_resp_dl ,
input [001:0] tlx_afu_resp_dp ,
// read data
output reg afu_tlx_resp_rd_req ,
output reg [002:0] afu_tlx_resp_rd_cnt ,
input tlx_afu_resp_data_valid ,
input [511:0] tlx_afu_resp_data_bus ,
input tlx_afu_resp_data_bdi ,
// response credit
output reg afu_tlx_resp_credit ,
output [006:0] afu_tlx_resp_initial_credit ,
//---- AFU side interface --------------------------------
// write channel
output tlx_w_rsp_valid ,
output [015:0] tlx_w_rsp_afutag ,
output [007:0] tlx_w_rsp_opcode ,
output [003:0] tlx_w_rsp_code ,
output [001:0] tlx_w_rsp_dl ,
output [001:0] tlx_w_rsp_dp ,
// read channel
output tlx_r_rsp_valid ,
output [015:0] tlx_r_rsp_afutag ,
output [007:0] tlx_r_rsp_opcode ,
output [003:0] tlx_r_rsp_code ,
output [001:0] tlx_r_rsp_dl ,
output [001:0] tlx_r_rsp_dp ,
output tlx_r_rdata_o_dv ,
output tlx_r_rdata_e_dv ,
output tlx_r_rdata_o_bdi ,
output tlx_r_rdata_e_bdi ,
output [511:0] tlx_r_rdata_o ,
output [511:0] tlx_r_rdata_e ,
// interrupt channel
output tlx_i_rsp_valid ,
output [015:0] tlx_i_rsp_afutag ,
output [007:0] tlx_i_rsp_opcode ,
output [003:0] tlx_i_rsp_code ,
//---- control and status ---------------------
input [031:0] debug_tlx_rsp_idle_lim ,
output reg debug_tlx_rsp_idle ,
output reg [005:0] fir_fifo_overflow ,
output reg fir_tlx_rsp_err
);
reg fifo_wr_rspcnv_den;
reg [031:00] fifo_wr_rspcnv_din;
reg fifo_wr_rspcnv_rdrq;
wire fifo_wr_rspcnv_dv;
wire fifo_wr_rspcnv_alempty;
wire fifo_wr_rspcnv_empty;
wire[031:00] fifo_wr_rspcnv_dout;
wire[004:00] fifo_wr_rspcnv_wrcnt;
reg fifo_rd_rspcnv_den;
reg [031:00] fifo_rd_rspcnv_din;
reg fifo_rd_rspcnv_rdrq;
wire fifo_rd_rspcnv_dv;
wire fifo_rd_rspcnv_alempty;
wire fifo_rd_rspcnv_empty;
wire[031:00] fifo_rd_rspcnv_dout;
wire[004:00] fifo_rd_rspcnv_wrcnt;
reg [004:00] rsp_credit_cnt;
reg tlx_dpdl_wr_toggle;
wire[001:00] real_dp_din_o;
wire[001:00] real_dp_din_e;
reg fifo_dpdl_o_den;
reg fifo_dpdl_e_den;
reg [003:00] fifo_dpdl_o_din;
wire[003:00] fifo_dpdl_o_dout;
reg [003:00] fifo_dpdl_e_din;
wire[003:00] fifo_dpdl_e_dout;
reg tlx_dpdl_rd_toggle;
wire fifo_dpdl_o_rdrq;
wire fifo_dpdl_e_rdrq;
wire fifo_dpdl_o_dv;
wire fifo_dpdl_e_dv;
wire[001:00] rdata_dp;
wire[001:00] rdata_dl;
reg [511:00] rdata_bus;
reg rdata_valid;
reg rdata_bdi;
reg tlx_o_dv;
reg tlx_e_dv;
reg [511:00] tlx_o_data;
reg [511:00] tlx_e_data;
reg tlx_o_bdi;
reg tlx_e_bdi;
wire fifo_datcnv_o_den;
wire[512:00] fifo_datcnv_o_din;
reg fifo_datcnv_o_rdrq;
wire fifo_datcnv_o_empty;
wire[512:00] fifo_datcnv_o_dout;
wire fifo_datcnv_o_dv;
wire[003:00] fifo_datcnv_o_wrcnt;
wire fifo_datcnv_e_den;
wire[512:00] fifo_datcnv_e_din;
reg fifo_datcnv_e_rdrq;
wire fifo_datcnv_e_empty;
wire[512:00] fifo_datcnv_e_dout;
wire fifo_datcnv_e_dv;
wire fifo_rd_rspcnv_ovfl;
wire fifo_wr_rspcnv_ovfl;
wire fifo_dpdl_o_ovfl;
wire fifo_dpdl_e_ovfl;
wire fifo_dpdl_o_udfl;
wire fifo_dpdl_e_udfl;
wire fifo_datcnv_o_ovfl;
wire fifo_datcnv_e_ovfl;
//-----------------------------------------------------------------------------------------------------------------
// CREDIT MANAGEMENT
//-----------------------------------------------------------------------------------------------------------------
//---- set response initial credit number with almost half capacity of response FIFO ----
assign afu_tlx_resp_initial_credit = 7'b0000111;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_credit_cnt <= 4'd0;
else
case({tlx_afu_resp_valid,afu_tlx_resp_credit})
2'b10 : rsp_credit_cnt <= rsp_credit_cnt + 4'd1;
2'b01 : rsp_credit_cnt <= rsp_credit_cnt - 4'd1;
endcase
//---- give response credit back when response is received, withdraw credit when response FIFO is more than half full ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
afu_tlx_resp_credit <= 1'b0;
else if(fifo_rd_rspcnv_wrcnt[4] || fifo_wr_rspcnv_wrcnt[4] || (fifo_datcnv_o_wrcnt > 4'd5))
afu_tlx_resp_credit <= 1'b0;
else
afu_tlx_resp_credit <= ((~afu_tlx_resp_credit && (rsp_credit_cnt == 4'd1)) || (rsp_credit_cnt > 4'd1));
//=====================================================================================================================================
//
// CLOCK DOMAIN CONVERTION FIFO SET: TLX -> AFU
//
// For read, care must be taken to identify even and odd data correctly.
// :
// +---+ +---------------------------------+
// tlx_afu_resp_dp/dl/afutag =============================>| |============> | write response conversion FIFO | ==> tlx_w_rsp_dp/dl/afutag
// || | M | +---------------------------------+
// || | U | :
// || | X | +---------------------------------+
// || | |============> | read response conversion FIFO | ==> tlx_r_rsp_dp/dl/afutag
// || +---+ +---------------------------------+
// || :
// ......||..........................................................................................
// || : V
// || +--+ +-----------------+ : for read only
// || | | => | dp/dl FIFO odd | ======= :
// || |M | +-----------------+ || :
// ==> |U | +--------------^--+ || :
// |X | => | dp/dl FIFO even | === || TLX clock : AFU clock
// +--+ +-----------------+ V V domain : domain
// ^ ^ +-------+ :
// dpdl_write_toggle __| | | dp dl | :
// | +-------+ :
// tlx_afu_resp_data_valid _________(dpdl_read_toggle)______| || || :
// V V :
// +----------+ +---------------------------+
// | odd | => | data conversion FIFO odd | ==> tlx_r_rsp_data_o
// tlx_afu_resp_data_bus =================================> | even | +---------------------------+
// | data | +---------------------------+
// | splitter | => | data conversion FIFO even | ==> tlx_r_rsp_data_e
// +----------+ +---------------------------+
// :
//
//=====================================================================================================================================
//----------------------------------------------------------------------------------------------------------
// READ FIFO for response info clock domain conversion
// * write in response in TLX time domain
// * read out response in AFU time domain whenever available
//----------------------------------------------------------------------------------------------------------
//---- FIFO input from TLX info ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fifo_rd_rspcnv_den <= 1'b0;
fifo_rd_rspcnv_din <= 32'd0;
end
else
begin
fifo_rd_rspcnv_den <= tlx_afu_resp_valid && tlx_afu_resp_afutag[15];
fifo_rd_rspcnv_din <= {tlx_afu_resp_dp, tlx_afu_resp_dl, tlx_afu_resp_code, tlx_afu_resp_opcode, tlx_afu_resp_afutag}; //2+2+4+8+16=32
end
//---- FIFO for response info ----
fifo_async #(
.DATA_WIDTH(32),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_rd_rspcnv (
.wr_clk (clk_tlx ),
.rd_clk (clk_afu ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_rd_rspcnv_din ),
.wr_en (fifo_rd_rspcnv_den ),
.rd_en (fifo_rd_rspcnv_rdrq ),
.valid (fifo_rd_rspcnv_dv ),
.dout (fifo_rd_rspcnv_dout ),
.overflow (fifo_rd_rspcnv_ovfl ),
.wr_data_count(fifo_rd_rspcnv_wrcnt ),
.almost_empty (fifo_rd_rspcnv_alempty),
.empty (fifo_rd_rspcnv_empty )
);
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
fifo_rd_rspcnv_rdrq <= 1'b0;
else if((fifo_rd_rspcnv_alempty && fifo_rd_rspcnv_rdrq) || fifo_rd_rspcnv_empty) // make sure no residual data in FIFO
fifo_rd_rspcnv_rdrq <= 1'b0;
else
fifo_rd_rspcnv_rdrq <= 1'b1;
//----------------------------------------------------------------------------------------------------------
// WRITE FIFO for response info clock domain conversion
// * write in response in TLX time domain
// * read out response in AFU time domain whenever available
//----------------------------------------------------------------------------------------------------------
//---- FIFO input from TLX info ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fifo_wr_rspcnv_den <= 1'b0;
fifo_wr_rspcnv_din <= 32'd0;
end
else
begin
fifo_wr_rspcnv_den <= tlx_afu_resp_valid && ~tlx_afu_resp_afutag[15];
fifo_wr_rspcnv_din <= {tlx_afu_resp_dp, tlx_afu_resp_dl, tlx_afu_resp_code, tlx_afu_resp_opcode, tlx_afu_resp_afutag}; //2+2+4+8+16=32
end
//---- FIFO for response info ----
fifo_async #(
.DATA_WIDTH(32),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_wr_rspcnv (
.wr_clk (clk_tlx ),
.rd_clk (clk_afu ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_wr_rspcnv_din ),
.wr_en (fifo_wr_rspcnv_den ),
.rd_en (fifo_wr_rspcnv_rdrq ),
.valid (fifo_wr_rspcnv_dv ),
.dout (fifo_wr_rspcnv_dout ),
.overflow (fifo_wr_rspcnv_ovfl ),
.wr_data_count(fifo_wr_rspcnv_wrcnt ),
.almost_empty (fifo_wr_rspcnv_alempty),
.empty (fifo_wr_rspcnv_empty )
);
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
fifo_wr_rspcnv_rdrq <= 1'b0;
else if((fifo_wr_rspcnv_alempty && fifo_wr_rspcnv_rdrq) || fifo_wr_rspcnv_empty) // make sure no residual data in FIFO
fifo_wr_rspcnv_rdrq <= 1'b0;
else
fifo_wr_rspcnv_rdrq <= 1'b1;
//----------------------------------------------------------------------------------------------------------
// FIFO for data length/ data position of good response
// * dual FIFOs are used to expand 128B response twice
// * write in dp and dl when read response is good
// * output of this FIFO is an indicator of response data that comes afterwards
//----------------------------------------------------------------------------------------------------------
localparam [7:0] TLX_AFU_RESP_OPCODE_READ_RESPONSE = 8'b00000100; // -- Read Response
//---- toggle write position for FIFO with 64B response ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
tlx_dpdl_wr_toggle <= 1'b0;
else if((tlx_afu_resp_valid) && (tlx_afu_resp_dl == 2'd1) && (tlx_afu_resp_opcode == TLX_AFU_RESP_OPCODE_READ_RESPONSE))
tlx_dpdl_wr_toggle <= ~tlx_dpdl_wr_toggle;
//---- for 128B response, write dl and dp in both even and odd FIFO; for 64B response, write alternately in even or odd FIFO, starting from even ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fifo_dpdl_o_den <= 1'b0;
fifo_dpdl_e_den <= 1'b0;
end
else if(tlx_afu_resp_valid && (tlx_afu_resp_opcode == TLX_AFU_RESP_OPCODE_READ_RESPONSE))
begin
fifo_dpdl_o_den <= ((tlx_afu_resp_dl == 2'd2) || ((tlx_afu_resp_dl == 2'd1) && tlx_dpdl_wr_toggle));
fifo_dpdl_e_den <= ((tlx_afu_resp_dl == 2'd2) || ((tlx_afu_resp_dl == 2'd1) && ~tlx_dpdl_wr_toggle));
end
else
begin
fifo_dpdl_o_den <= 1'b0;
fifo_dpdl_e_den <= 1'b0;
end
//---- manage real write position with 128B. this is to help the read side distinguish between the 1st 64B and 2nd 64B for an 128B response ----
// if current 64B dpdl in even FIFO, then next 128B dpdl should be in odd FIFO, so it should be 00 in odd FIFO for the 1st dp of the next 128B
// tlx_afu_resp_dl <01><10><10><01><01><01><10>
// real_dp_din_o < ><00><00><dp>< ><dp><01>
// real_dp_din_e <dp><01><01>< ><dp>< ><00>
// tlx_dpdl_wr_toggle ____/-----------\___/---\___
wire h_64B = tlx_afu_resp_afutag[8];
wire l_64B = tlx_afu_resp_afutag[7];
wire[1:0] pos_64B = ({h_64B,l_64B} == 2'b01)? 2'b00 : (({h_64B,l_64B} == 2'b10)? 2'b01 : tlx_afu_resp_dp);
assign real_dp_din_o = (tlx_afu_resp_dl == 2'd2)? {1'b0,~tlx_dpdl_wr_toggle} : pos_64B;
assign real_dp_din_e = (tlx_afu_resp_dl == 2'd2)? {1'b0, tlx_dpdl_wr_toggle} : pos_64B;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fifo_dpdl_e_din <= 4'd0;
fifo_dpdl_o_din <= 4'd0;
end
else
begin
fifo_dpdl_e_din <= {real_dp_din_e, tlx_afu_resp_dl};
fifo_dpdl_o_din <= {real_dp_din_o, tlx_afu_resp_dl};
end
//---- FIFO for response dl/dp odd ----
fifo_sync #(
.DATA_WIDTH (4),
.ADDR_WIDTH (5)
) mfifo_dpdl_o (
.clk (clk_tlx ),
.rst_n (rst_n ),
.din (fifo_dpdl_o_din ),
.wr_en (fifo_dpdl_o_den ),
.rd_en (fifo_dpdl_o_rdrq ),
.dout (fifo_dpdl_o_dout ),
.valid (fifo_dpdl_o_dv ),
.overflow (fifo_dpdl_o_ovfl ),
.underflow(fifo_dpdl_o_udfl )
);
//---- FIFO for response dl/dp even ----
fifo_sync #(
.DATA_WIDTH (4),
.ADDR_WIDTH (5)
) mfifo_dpdl_e (
.clk (clk_tlx ),
.rst_n (rst_n ),
.din (fifo_dpdl_e_din ),
.wr_en (fifo_dpdl_e_den ),
.rd_en (fifo_dpdl_e_rdrq ),
.dout (fifo_dpdl_e_dout ),
.valid (fifo_dpdl_e_dv ),
.overflow (fifo_dpdl_e_ovfl ),
.underflow(fifo_dpdl_e_udfl )
);
//---- reflect good TLX read request to accept responsed data----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
afu_tlx_resp_rd_req <= 1'b0;
afu_tlx_resp_rd_cnt <= 2'b0;
end
else
begin
afu_tlx_resp_rd_req <= tlx_afu_resp_valid && (tlx_afu_resp_opcode == TLX_AFU_RESP_OPCODE_READ_RESPONSE);
afu_tlx_resp_rd_cnt <= tlx_afu_resp_dl;
end
//---- always pop dp/dl out when response data is available, from even or odd FIFO alternatively. MUST always starts from even ----
// assuming that the dpdl FIFO can never be empty when valid data comes
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
tlx_dpdl_rd_toggle <= 1'b0;
else if(tlx_afu_resp_data_valid)
tlx_dpdl_rd_toggle <= ~tlx_dpdl_rd_toggle;
assign fifo_dpdl_o_rdrq = tlx_afu_resp_data_valid && tlx_dpdl_rd_toggle;
assign fifo_dpdl_e_rdrq = tlx_afu_resp_data_valid && ~tlx_dpdl_rd_toggle;
//---- extract dl and dp from read data ----
assign rdata_dl = (fifo_dpdl_e_dv)? fifo_dpdl_e_dout[1:0] : fifo_dpdl_o_dout[1:0];
assign rdata_dp = (fifo_dpdl_e_dv)? fifo_dpdl_e_dout[3:2] : fifo_dpdl_o_dout[3:2];
//---- delay once to sync with dp and dl output ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
rdata_valid <= 1'b0;
rdata_bus <= 512'd0;
rdata_bdi <= 1'b0;
end
else
begin
rdata_valid <= tlx_afu_resp_data_valid;
rdata_bus <= tlx_afu_resp_data_bus;
rdata_bdi <= tlx_afu_resp_data_bdi;
end
//---- split 64B TLX resp data into even and odd lanes to prepare for AFU time domain conversion ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
tlx_e_data <= 512'd0;
tlx_o_data <= 512'd0;
tlx_e_bdi <= 1'b0;
tlx_o_bdi <= 1'b0;
end
else
case(rdata_dp)
2'b01 : begin tlx_o_data <= rdata_bus; tlx_o_bdi <= rdata_bdi; tlx_e_bdi <= 1'b0; end
2'b00 : begin tlx_e_data <= rdata_bus; tlx_e_bdi <= rdata_bdi; tlx_o_bdi <= 1'b0; end
endcase
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
tlx_e_dv <= 1'b0;
tlx_o_dv <= 1'b0;
end
else
begin // write both even and odd for dl=1 (64B) regardless of dp
tlx_e_dv <= rdata_valid && (((rdata_dp == 2'b00) || (rdata_dl == 2'b01)) && (fifo_dpdl_e_dv || fifo_dpdl_o_dv));
tlx_o_dv <= rdata_valid && (((rdata_dp == 2'b01) || (rdata_dl == 2'b01)) && (fifo_dpdl_e_dv || fifo_dpdl_o_dv));
end
//----------------------------------------------------------------------------------------------------------
// FIFO for response data time domain conversion
// TLX data must be first correctly split into dual channels before going through time conversion
//----------------------------------------------------------------------------------------------------------
//---- FIFO input from TLX data ---
assign fifo_datcnv_o_den = tlx_o_dv;
assign fifo_datcnv_o_din = {tlx_o_bdi, tlx_o_data};
//---- FIFO for response data ----
fifo_async #(
.DATA_WIDTH(513),
.ADDR_WIDTH(4),
.DISTR(1)
) mfifo_datcnv_o (
.wr_clk (clk_tlx ),
.rd_clk (clk_afu ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_datcnv_o_din ),
.wr_en (fifo_datcnv_o_den ),
.rd_en (fifo_datcnv_o_rdrq ),
.dout (fifo_datcnv_o_dout ),
.valid (fifo_datcnv_o_dv ),
.overflow (fifo_datcnv_o_ovfl ),
.wr_data_count(fifo_datcnv_o_wrcnt ),
.empty (fifo_datcnv_o_empty )
);
//---- FIFO read request, making sure no residual data in FIFO ----
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
fifo_datcnv_o_rdrq <= 1'b0;
else
fifo_datcnv_o_rdrq <= ~fifo_datcnv_o_empty;
//---- FIFO input from TLX data ---
assign fifo_datcnv_e_den = tlx_e_dv;
assign fifo_datcnv_e_din = {tlx_e_bdi, tlx_e_data};
//---- FIFO for response data ----
fifo_async #(
.DATA_WIDTH(513),
.ADDR_WIDTH(4),
.DISTR(1)
) mfifo_datcnv_e (
.wr_clk (clk_tlx ),
.rd_clk (clk_afu ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_datcnv_e_din ),
.wr_en (fifo_datcnv_e_den ),
.rd_en (fifo_datcnv_e_rdrq ),
.dout (fifo_datcnv_e_dout ),
.valid (fifo_datcnv_e_dv ),
.overflow (fifo_datcnv_e_ovfl ),
.empty (fifo_datcnv_e_empty )
);
//---- FIFO read request, making sure no residual data in FIFO ----
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
fifo_datcnv_e_rdrq <= 1'b0;
else
fifo_datcnv_e_rdrq <= ~fifo_datcnv_e_empty;
//---- FIFO output to response decoder ----
// write info
assign tlx_w_rsp_valid = fifo_wr_rspcnv_dv;
assign tlx_w_rsp_afutag = fifo_wr_rspcnv_dout[15:00];
assign tlx_w_rsp_opcode = fifo_wr_rspcnv_dout[23:16];
assign tlx_w_rsp_code = fifo_wr_rspcnv_dout[27:24];
assign tlx_w_rsp_dl = fifo_wr_rspcnv_dout[29:28];
assign tlx_w_rsp_dp = fifo_wr_rspcnv_dout[31:30];
// read info
assign tlx_r_rsp_valid = fifo_rd_rspcnv_dv && (tlx_r_rsp_afutag != {2'b11, 14'd0});
assign tlx_r_rsp_afutag = fifo_rd_rspcnv_dout[15:00];
assign tlx_r_rsp_opcode = fifo_rd_rspcnv_dout[23:16];
assign tlx_r_rsp_code = fifo_rd_rspcnv_dout[27:24];
assign tlx_r_rsp_dl = fifo_rd_rspcnv_dout[29:28];
assign tlx_r_rsp_dp = fifo_rd_rspcnv_dout[31:30];
// read data
assign tlx_r_rdata_o_dv = fifo_datcnv_o_dv;
assign tlx_r_rdata_o_bdi = fifo_datcnv_o_dout[512];
assign tlx_r_rdata_o = fifo_datcnv_o_dout[511:0];
assign tlx_r_rdata_e_dv = fifo_datcnv_e_dv;
assign tlx_r_rdata_e_bdi = fifo_datcnv_e_dout[512];
assign tlx_r_rdata_e = fifo_datcnv_e_dout[511:0];
// interrupt info
assign tlx_i_rsp_valid = fifo_rd_rspcnv_dv && (tlx_r_rsp_afutag == {2'b11, 14'd0});
assign tlx_i_rsp_afutag = fifo_rd_rspcnv_dout[15:00];
assign tlx_i_rsp_opcode = fifo_rd_rspcnv_dout[23:16];
assign tlx_i_rsp_code = fifo_rd_rspcnv_dout[27:24];
//=================================================================================================================
// STATUS output for SNAP registers
//=================================================================================================================
reg [31:0] rsp_idle_cnt;
reg rsp_idle;
reg [31:0] rsp_idle_lim;
//---- DEBUG registers ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_idle <= 1'b0;
else if(tlx_afu_resp_valid)
rsp_idle <= 1'b0;
else if(rsp_idle_cnt == rsp_idle_lim)
rsp_idle <= 1'b1;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_idle_cnt <= 32'd0;
else if(tlx_afu_resp_valid)
rsp_idle_cnt <= 32'd0;
else
rsp_idle_cnt <= rsp_idle_cnt + 32'd1;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_idle_lim <= 32'd0;
else
rsp_idle_lim <= debug_tlx_rsp_idle_lim;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
debug_tlx_rsp_idle <= 1'b0;
else
debug_tlx_rsp_idle <= rsp_idle;
//---- FAULT ISOLATION REGISTER ----
reg fir_fifo_rd_rspcnv_overflow;
reg fir_fifo_wr_rspcnv_overflow;
reg fir_fifo_dpdl_o_overflow;
reg fir_fifo_dpdl_e_overflow;
reg fir_fifo_datcnv_o_overflow;
reg fir_fifo_datcnv_e_overflow;
reg fir_tlx_rsp_deficient_or_delayed;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fir_fifo_rd_rspcnv_overflow <= 1'b0;
fir_fifo_wr_rspcnv_overflow <= 1'b0;
fir_fifo_dpdl_o_overflow <= 1'b0;
fir_fifo_dpdl_e_overflow <= 1'b0;
fir_fifo_datcnv_o_overflow <= 1'b0;
fir_fifo_datcnv_e_overflow <= 1'b0;
fir_tlx_rsp_deficient_or_delayed <= 1'b0;
end
else
begin
if (fifo_rd_rspcnv_ovfl) fir_fifo_rd_rspcnv_overflow <= 1'b1;
if (fifo_wr_rspcnv_ovfl) fir_fifo_wr_rspcnv_overflow <= 1'b1;
if (fifo_dpdl_o_ovfl) fir_fifo_dpdl_o_overflow <= 1'b1;
if (fifo_dpdl_e_ovfl) fir_fifo_dpdl_e_overflow <= 1'b1;
if (fifo_datcnv_o_ovfl) fir_fifo_datcnv_o_overflow <= 1'b1;
if (fifo_datcnv_e_ovfl) fir_fifo_datcnv_e_overflow <= 1'b1;
if (rdata_valid)
begin
if (~(fifo_dpdl_e_dv || fifo_dpdl_o_dv))
fir_tlx_rsp_deficient_or_delayed <= 1'b1;
end
end
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
begin
fir_fifo_overflow <= 6'd0;
fir_tlx_rsp_err <= 1'b0;
end
else
begin
fir_fifo_overflow <= { fir_fifo_rd_rspcnv_overflow, fir_fifo_wr_rspcnv_overflow, fir_fifo_dpdl_o_overflow, fir_fifo_dpdl_e_overflow, fir_fifo_datcnv_o_overflow, fir_fifo_datcnv_e_overflow };
fir_tlx_rsp_err <= fir_tlx_rsp_deficient_or_delayed;
end
wire check_dpdl;
wire clk_check;
assign check_dpdl = fifo_dpdl_e_dv || fifo_dpdl_o_dv;
assign clk_check = clk_check && clk_tlx;
//==== PSL ASSERTION ==============================================================================
// psl DPDL_FIFO_UNDERFLOW : assert never (fifo_dpdl_o_udfl | fifo_dpdl_e_udfl) @(posedge clk_tlx) report "dpdl FIFO underflow! dpdl FIFOs are used to store response information of dp and dl, which comes earlier than response data. So when response data arrives to read dpdl FIFOs, either of them are expeced to be empty.";
// psl DL_IN_PAIR : assert always (((rdata_dl == 2'b10) && (rdata_dp == 2'b00)) -> next ((rdata_dl == 2'b10) && (rdata_dp == 2'b01))) @(posedge clk_check) report "the sequence of dp for dl=2 should always be dp=00 -> dp=01! Assertion fires under the following circumstances: 1) dl=1 -> dl=2,dp=1; 2) dl=2,dp=0 -> dl=1.";
// psl DL_IN_ERROR : assert never {(rdata_dl == 2'b01); ((rdata_dl == 2'b10) && (rdata_dp == 2'b01))} @(posedge clk_check) report "the sequence of dp for dl=2 should always be dp=00 -> dp=01! Assertion fires under the following circumstances: 1. dl=1 -> dl=2,dp=1; 2. dl=2,dp=0 -> dl=1.";
//==== PSL ASSERTION ==============================================================================
//==== PSL COVERAGE ==============================================================================
// psl RSP_FIFO_ALMOST_FULL : cover {(fifo_rd_rspcnv_wrcnt[4] || fifo_wr_rspcnv_wrcnt[4] || (fifo_datcnv_o_wrcnt > 4'd5))} @(posedge clk_tlx) ;
//==== PSL COVERAGE ==============================================================================
endmodule |
module fifo_sync
#(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 5,
parameter FWFT = 0,
parameter DISTR = 0
)
(
input clk,
input rst_n,
input wr_en,
input [DATA_WIDTH-1:0] din,
input rd_en,
output [DATA_WIDTH-1:0] dout,
output valid,
output full,
output empty,
output almost_full,
output almost_empty,
output reg overflow,
output reg underflow,
output [ADDR_WIDTH-1:0] count
);
wire [ADDR_WIDTH-1:0] ram_wa;
wire ram_wen;
wire [ADDR_WIDTH-1:0] ram_ra;
wire [DATA_WIDTH-1:0] ram_di;
wire [DATA_WIDTH-1:0] ram_do;
wire [ADDR_WIDTH-1:0] pcnt_0 = {ADDR_WIDTH{1'b0}};
wire [ADDR_WIDTH-1:0] pcnt_1 = {{ADDR_WIDTH-1{1'b0}}, 1'b1};
wire [ADDR_WIDTH:0] ecnt_0 = {ADDR_WIDTH+1{1'b0}};
wire [ADDR_WIDTH:0] ecnt_1 = {{ADDR_WIDTH{1'b0}}, 1'b1};
wire [ADDR_WIDTH:0] ecnt_max = {1'b1, {ADDR_WIDTH{1'b0}}};
wire [ADDR_WIDTH:0] ecnt_max_1 = {1'b0, {ADDR_WIDTH{1'b1}}};
wire [ADDR_WIDTH:0] ecnt_max_2 = {1'b0, {(ADDR_WIDTH-1){1'b1}},1'b0};
reg [ADDR_WIDTH-1:0] wr_pnt, rd_pnt;
reg [ADDR_WIDTH:0] valid_entry_cnt;
reg rd_en_sync;
reg wr_en_dly;
always@(posedge clk or negedge rst_n)
if(~rst_n)
wr_pnt <= pcnt_0;
else if(wr_en && ~full)
wr_pnt <= wr_pnt + pcnt_1;
always@(posedge clk or negedge rst_n)
if(~rst_n)
wr_en_dly <= 0;
else
wr_en_dly <= wr_en; // fifo cannot be read immediately after the first wr_en, data can only be valid on the port in the 2nd cycle after the first wr_en
assign ram_wen = wr_en;
assign ram_di = din;
assign ram_wa = wr_pnt;
assign dout = ram_do;
always@(posedge clk or negedge rst_n)
if(~rst_n)
rd_pnt <= pcnt_0;
else if(rd_en && ~empty)
rd_pnt <= rd_pnt + pcnt_1;
assign ram_ra = (FWFT)? (rd_en? (rd_pnt+1): rd_pnt) : rd_pnt;
always@(posedge clk or negedge rst_n)
if(~rst_n)
valid_entry_cnt <= ecnt_0;
else
casez({wr_en_dly, rd_en, full, empty})
4'b01?0 : valid_entry_cnt <= valid_entry_cnt - ecnt_1; // read
4'b100? : valid_entry_cnt <= valid_entry_cnt + ecnt_1; // write
4'b11?1 : valid_entry_cnt <= ecnt_1; // underflow
default :;
endcase
always@(posedge clk or negedge rst_n)
if(~rst_n)
rd_en_sync <= 1'b0;
else
rd_en_sync <= rd_en;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
underflow <= 1'b0;
overflow <= 1'b0;
end
else
begin
underflow <= empty && rd_en;
overflow <= full && wr_en;
end
assign full = (valid_entry_cnt == ecnt_max);
assign empty = (valid_entry_cnt == ecnt_0);
assign almost_full = ((valid_entry_cnt == ecnt_max_1) || (valid_entry_cnt == ecnt_max_2));
assign almost_empty = (valid_entry_cnt == ecnt_1);
assign count = valid_entry_cnt[ADDR_WIDTH-1:0];
assign valid = (FWFT)? ~empty : (rd_en_sync && ~underflow);
ram_simple_dual #(DATA_WIDTH,ADDR_WIDTH,DISTR) mram_simple_dual (.clk(clk),.ena(1'b1),.enb(1'b1),.wea(ram_wen),.addra(ram_wa),.addrb(ram_ra),.dia(ram_di),.dob(ram_do));
endmodule |
module brdg_tlx_cmd_converter (
input clk_tlx ,
input clk_afu ,
input rst_n ,
//---- configuration --------------------------------------
input [007:0] cfg_bdf_bus ,
input [004:0] cfg_bdf_device ,
input [002:0] cfg_bdf_function ,
//---- TLX side interface --------------------------------
// command
output afu_tlx_cmd_valid ,
output [007:0] afu_tlx_cmd_opcode ,
output [011:0] afu_tlx_cmd_actag ,
output [067:0] afu_tlx_cmd_ea_or_obj ,
output [015:0] afu_tlx_cmd_afutag ,
output [001:0] afu_tlx_cmd_dl ,
output [002:0] afu_tlx_cmd_pl ,
output [019:0] afu_tlx_cmd_pasid ,
output afu_tlx_cmd_os ,
output [063:0] afu_tlx_cmd_be ,
output [003:0] afu_tlx_cmd_flag ,
output afu_tlx_cmd_endian ,
output [015:0] afu_tlx_cmd_bdf ,
output [003:0] afu_tlx_cmd_stream_id ,
output [005:0] afu_tlx_cmd_pg_size ,
// write data
output afu_tlx_cdata_valid ,
output afu_tlx_cdata_bdi ,
output [511:0] afu_tlx_cdata_bus ,
// command and write data credit
input tlx_afu_cmd_credit ,
input tlx_afu_cmd_data_credit ,
input [003:0] tlx_afu_cmd_initial_credit ,
input [005:0] tlx_afu_cmd_data_initial_credit,
//---- AFU side interface --------------------------------
// write channel
input tlx_wr_cmd_valid ,
input [0007:0] tlx_wr_cmd_opcode ,
input [0067:0] tlx_wr_cmd_ea_or_obj ,
input [0015:0] tlx_wr_cmd_afutag ,
input [0001:0] tlx_wr_cmd_dl ,
input [0002:0] tlx_wr_cmd_pl ,
input [0063:0] tlx_wr_cmd_be ,
input [1023:0] tlx_wr_cdata_bus ,
output tlx_wr_cmd_ready ,
input [0019:0] tlx_wr_cmd_pasid ,
input [0011:0] tlx_wr_cmd_actag ,
// read channel
input tlx_rd_cmd_valid ,
input [0007:0] tlx_rd_cmd_opcode ,
input [0067:0] tlx_rd_cmd_ea_or_obj ,
input [0015:0] tlx_rd_cmd_afutag ,
input [0001:0] tlx_rd_cmd_dl ,
input [0002:0] tlx_rd_cmd_pl ,
output tlx_rd_cmd_ready ,
input [0019:0] tlx_rd_cmd_pasid ,
input [0011:0] tlx_rd_cmd_actag ,
// interrupt channel
input tlx_in_cmd_valid ,
input [0067:0] tlx_in_cmd_obj ,
input [0015:0] tlx_in_cmd_afutag ,
input [0007:0] tlx_in_cmd_opcode ,
input [0019:0] tlx_in_cmd_pasid ,
input [0011:0] tlx_in_cmd_actag ,
//---- control and status --------------------------------
input [031:0] debug_tlx_cmd_idle_lim ,
output reg debug_tlx_cmd_idle ,
output reg [0003:0] fir_fifo_overflow ,
output reg [0001:0] fir_tlx_command_credit
);
reg [003:0] cmd_credit_cnt;
reg [005:0] cmd_data_credit_cnt;
reg cmd_credit_run_out;
reg cmd_data_credit_lt_2;
wire[128:0] fifo_w_cmdcnv_din;
wire[128:0] fifo_w_cmdcnv_dout;
wire[511:0] fifo_w_datcnv_o_din;
wire[511:0] fifo_w_datcnv_o_dout;
wire[511:0] fifo_w_datcnv_e_din;
wire[511:0] fifo_w_datcnv_e_dout;
wire fifo_w_datcnv_e_dv;
wire fifo_w_cmdcnv_den;
wire fifo_w_cmdcnv_half_full;
wire[004:0] fifo_w_cmdcnv_wrcnt;
wire fifo_w_datcnv_o_den;
wire fifo_w_datcnv_e_den;
wire fifo_w_cmdcnv_rdrq;
wire fifo_w_datcnv_o_rdrq;
wire fifo_w_datcnv_o_dv;
wire fifo_w_datcnv_e_rdrq;
wire fifo_w_cmdcnv_dv;
wire[007:0] fifo_w_cmdcnv_dout_opcode;
wire[015:0] fifo_w_cmdcnv_dout_afutag;
wire[067:0] fifo_w_cmdcnv_dout_ea;
wire[001:0] fifo_w_cmdcnv_dout_dl;
wire[002:0] fifo_w_cmdcnv_dout_pl;
wire[011:0] fifo_w_cmdcnv_dout_actag;
wire[019:0] fifo_w_cmdcnv_dout_pasid;
wire[007:0] fifo_r_cmdcnv_dout_opcode;
wire[015:0] fifo_r_cmdcnv_dout_afutag;
wire[067:0] fifo_r_cmdcnv_dout_ea;
wire[001:0] fifo_r_cmdcnv_dout_dl;
wire[002:0] fifo_r_cmdcnv_dout_pl;
wire[011:0] fifo_r_cmdcnv_dout_actag;
wire[019:0] fifo_r_cmdcnv_dout_pasid;
wire[128:0] fifo_r_cmdcnv_din;
wire[128:0] fifo_r_cmdcnv_dout;
wire fifo_r_cmdcnv_den;
wire fifo_r_cmdcnv_dv;
wire fifo_r_cmdcnv_rdrq;
wire fifo_r_cmdcnv_half_full;
wire[004:0] fifo_r_cmdcnv_wrcnt;
reg cmd_crankshaft_main;
reg cmd_crankshaft_sub;
wire fifo_r_cmdcnv_ovfl;
wire fifo_w_datcnv_e_ovfl;
wire fifo_w_datcnv_o_ovfl;
wire fifo_w_cmdcnv_ovfl;
wire fifo_w_cmdcnv_empty;
wire fifo_w_cmdcnv_full;
wire fifo_r_cmdcnv_empty;
wire fifo_r_cmdcnv_full;
wire fifo_w_datcnv_o_full;
wire fifo_w_datcnv_o_empty;
wire fifo_w_datcnv_e_full;
wire fifo_w_datcnv_e_empty;
reg tlx_in_cmd_req;
reg tlx_in_cmd_ack;
reg tlx_in_cmd_rec;
reg [002:0] tlx_in_cmd_rec_pipe;
reg [002:0] tlx_in_cmd_req_pipe;
reg tlx_in_cmd_pending;
wire tlx_interrupt_valid_pre;
reg tlx_interrupt_valid;
reg [007:0] tlx_in_cmd_opcode_sync;
reg [015:0] tlx_in_cmd_afutag_sync;
reg [067:0] tlx_in_cmd_obj_sync;
reg [019:0] tlx_in_cmd_pasid_sync;
reg [011:0] tlx_in_cmd_actag_sync;
reg [007:0] tlx_interrupt_opcode;
reg [015:0] tlx_interrupt_afutag;
reg [067:0] tlx_interrupt_obj;
reg [019:0] tlx_interrupt_pasid;
reg [011:0] tlx_interrupt_actag;
wire context_input_cmd_ready ;
wire context_input_wr_en ;
reg context_input_cmd_valid ;
reg [007:0] context_input_cmd_opcode ;
reg [015:0] context_input_cmd_afutag ;
reg [067:0] context_input_cmd_ea_or_obj ;
reg [001:0] context_input_cmd_dl ;
reg [002:0] context_input_cmd_pl ;
reg [011:0] context_input_cmd_actag ;
reg [019:0] context_input_cmd_pasid ;
wire context_surveil_stage1_ready;
wire context_output_cmd_valid ;
wire [007:0] context_output_cmd_opcode ;
wire [015:0] context_output_cmd_afutag ;
wire [067:0] context_output_cmd_ea_or_obj;
wire [001:0] context_output_cmd_dl ;
wire [002:0] context_output_cmd_pl ;
wire [011:0] context_output_cmd_actag ;
wire [019:0] context_output_cmd_pasid ;
reg context_buffer_cmd_valid ;
reg [007:0] context_buffer_cmd_opcode ;
reg [015:0] context_buffer_cmd_afutag ;
reg [067:0] context_buffer_cmd_ea_or_obj;
reg [001:0] context_buffer_cmd_dl ;
reg [002:0] context_buffer_cmd_pl ;
reg [011:0] context_buffer_cmd_actag ;
reg [019:0] context_buffer_cmd_pasid ;
wire context_surveil_wdata_e_rdrq;
wire tlx_afu_cmd_ready ;
reg dl_1_dly ;
//=================================================================================================================
//
// CLOCK DOMAIN CONVERTION FIFO SET : TLX <- AFU
//
// +---+ +----------------------------+ +--------------------------------
// | |<===| write channel command FIFO |<=========== command/info =======|
// | | +----------------------------+ |
// | | ^ +----------------------------+ | command_encode
// | |<====|==| even write data FIFO |<========== even data =======| (write channel)
// | | | +----------------------------+ |
// | M | |___^ |
// | | | +----------------------------+ |
// | U |<====|==| odd write data FIFO |<========== odd data ========|
// | | | +----------------------------+ +--------------------------------
// T | X | | ^
// L <===| | | | +----------------------------+ +--------------------------------
// X | |<====|== =|=| read channel command FIFO |<=== command/info =======| command_encode (read channel)
// | | | | +----------------------------+ +--------------------------------
// | | | | ^
// +------------+_| | |
// | crankshaft |______|___|
// +------------+
//
//=================================================================================================================
//---- prevent command encoder from filling in when FIFO's almost full ----
assign fifo_w_cmdcnv_half_full = fifo_w_cmdcnv_wrcnt[4];
assign fifo_r_cmdcnv_half_full = fifo_r_cmdcnv_wrcnt[4];
assign tlx_wr_cmd_ready = ~fifo_w_cmdcnv_half_full;
assign tlx_rd_cmd_ready = ~fifo_r_cmdcnv_half_full;
//---- put write data and command in clock converter FIFO ----
assign fifo_w_cmdcnv_den = tlx_wr_cmd_valid;
assign fifo_w_cmdcnv_din = {tlx_wr_cmd_pasid, tlx_wr_cmd_actag, tlx_wr_cmd_pl, tlx_wr_cmd_dl, tlx_wr_cmd_afutag, tlx_wr_cmd_ea_or_obj, tlx_wr_cmd_opcode};//20+12+3+2+16+68+8 = 129
assign fifo_w_datcnv_o_den = tlx_wr_cmd_valid;
assign fifo_w_datcnv_o_din = tlx_wr_cdata_bus[1023:512];
assign fifo_w_datcnv_e_den = tlx_wr_cmd_valid;
assign fifo_w_datcnv_e_din = tlx_wr_cdata_bus[0511:000];
//---- FIFO for write command and info ----
fifo_async #(
.DATA_WIDTH(129),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_w_cmdcnv (
.wr_clk (clk_afu ),
.rd_clk (clk_tlx ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_w_cmdcnv_din ),
.wr_en (fifo_w_cmdcnv_den ),
.rd_en (fifo_w_cmdcnv_rdrq ),
.valid (fifo_w_cmdcnv_dv ),
.dout (fifo_w_cmdcnv_dout ),
.wr_data_count (fifo_w_cmdcnv_wrcnt ),
.overflow (fifo_w_cmdcnv_ovfl ),
.full (fifo_w_cmdcnv_full ),
.empty (fifo_w_cmdcnv_empty )
);
//---- FIFO for higher 64B write data ----
fifo_async #(
.DATA_WIDTH(512),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_w_datcnv_o (
.wr_clk (clk_afu ),
.rd_clk (clk_tlx ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_w_datcnv_o_din ),
.wr_en (fifo_w_datcnv_o_den ),
.rd_en (fifo_w_datcnv_o_rdrq ),
.valid (fifo_w_datcnv_o_dv ),
.dout (fifo_w_datcnv_o_dout ),
.overflow(fifo_w_datcnv_o_ovfl ),
.full (fifo_w_datcnv_o_full ),
.empty (fifo_w_datcnv_o_empty)
);
//---- FIFO for lower 64B write data ----
fifo_async #(
.DATA_WIDTH(512),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_w_datcnv_e (
.wr_clk (clk_afu ),
.rd_clk (clk_tlx ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_w_datcnv_e_din ),
.wr_en (fifo_w_datcnv_e_den ),
.rd_en (fifo_w_datcnv_e_rdrq ),
.valid (fifo_w_datcnv_e_dv ),
.dout (fifo_w_datcnv_e_dout ),
.overflow(fifo_w_datcnv_e_ovfl ),
.full (fifo_w_datcnv_e_full ),
.empty (fifo_w_datcnv_e_empty)
);
//---- write channel data output ----
assign fifo_w_cmdcnv_dout_opcode = fifo_w_cmdcnv_dout[007:000];
assign fifo_w_cmdcnv_dout_ea = fifo_w_cmdcnv_dout[075:008];
assign fifo_w_cmdcnv_dout_afutag = fifo_w_cmdcnv_dout[091:076];
assign fifo_w_cmdcnv_dout_dl = fifo_w_cmdcnv_dout[093:092];
assign fifo_w_cmdcnv_dout_pl = fifo_w_cmdcnv_dout[096:094];
assign fifo_w_cmdcnv_dout_actag = fifo_w_cmdcnv_dout[108:097];
assign fifo_w_cmdcnv_dout_pasid = fifo_w_cmdcnv_dout[128:109];
//---- put read command in clock converter FIFO ----
assign fifo_r_cmdcnv_din = {tlx_rd_cmd_pasid, tlx_rd_cmd_actag, tlx_rd_cmd_pl, tlx_rd_cmd_dl, tlx_rd_cmd_afutag, tlx_rd_cmd_ea_or_obj, tlx_rd_cmd_opcode};
assign fifo_r_cmdcnv_den = tlx_rd_cmd_valid;
//---- FIFO for read command and info ----
fifo_async #(
.DATA_WIDTH(129),
.ADDR_WIDTH(5),
.DISTR(1)
) mfifo_r_cmdcnv (
.wr_clk (clk_afu ),
.rd_clk (clk_tlx ),
.wr_rst (~rst_n ),
.rd_rst (~rst_n ),
.din (fifo_r_cmdcnv_din ),
.wr_en (fifo_r_cmdcnv_den ),
.rd_en (fifo_r_cmdcnv_rdrq ),
.valid (fifo_r_cmdcnv_dv ),
.dout (fifo_r_cmdcnv_dout ),
.wr_data_count (fifo_r_cmdcnv_wrcnt ),
.overflow (fifo_r_cmdcnv_ovfl ),
.full (fifo_r_cmdcnv_full ),
.empty (fifo_r_cmdcnv_empty )
);
//---- write channel data output ----
assign fifo_r_cmdcnv_dout_opcode = fifo_r_cmdcnv_dout[007:000];
assign fifo_r_cmdcnv_dout_ea = fifo_r_cmdcnv_dout[075:008];
assign fifo_r_cmdcnv_dout_afutag = fifo_r_cmdcnv_dout[091:076];
assign fifo_r_cmdcnv_dout_dl = fifo_r_cmdcnv_dout[093:092];
assign fifo_r_cmdcnv_dout_pl = fifo_r_cmdcnv_dout[096:094];
assign fifo_r_cmdcnv_dout_actag = fifo_r_cmdcnv_dout[108:097];
assign fifo_r_cmdcnv_dout_pasid = fifo_r_cmdcnv_dout[128:109];
//---- use crankshaft to ensure command data and info from read and write FIFO are popped out alternately ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_crankshaft_main <= 1'b0;
else if(context_input_cmd_ready)
cmd_crankshaft_main <= ~cmd_crankshaft_main;
//---- subordinate crankshaft used for odd data FIFO, it should always follow main crankshaft to guarantee that even data come out first ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_crankshaft_sub <= 1'b0;
else
cmd_crankshaft_sub <= context_surveil_wdata_e_rdrq;
assign fifo_w_cmdcnv_rdrq = cmd_crankshaft_main && context_input_cmd_ready && ~tlx_interrupt_valid_pre && ~fifo_w_cmdcnv_empty;
assign fifo_r_cmdcnv_rdrq = ~cmd_crankshaft_main && context_input_cmd_ready && ~tlx_interrupt_valid_pre && ~fifo_r_cmdcnv_empty;
assign fifo_w_datcnv_e_rdrq = context_surveil_wdata_e_rdrq;
assign fifo_w_datcnv_o_rdrq = cmd_crankshaft_sub;
//-----------------------------------------------------------------------------------------------------------------
// Interrupt command convertion
//
// * Handshake between TLX and AFU time domain
//
// ---- TLX ---- : --- AFU ---
// tlx_in_cmd_req
// /
// tlx_in_cmd_rec
// \
// tlx_in_cmd_ack
//-----------------------------------------------------------------------------------------------------------------
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
tlx_in_cmd_req <= 1'b0;
else if(tlx_in_cmd_ack)
tlx_in_cmd_req <= 1'b0;
else if(tlx_in_cmd_valid)
tlx_in_cmd_req <= 1'b1;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
{tlx_in_cmd_ack, tlx_in_cmd_rec_pipe} <= 4'd0;
else
{tlx_in_cmd_ack, tlx_in_cmd_rec_pipe} <= {tlx_in_cmd_rec_pipe, tlx_in_cmd_rec};
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
{tlx_in_cmd_rec, tlx_in_cmd_req_pipe} <= 4'd0;
else
{tlx_in_cmd_rec, tlx_in_cmd_req_pipe} <= {tlx_in_cmd_req_pipe, tlx_in_cmd_req};
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
tlx_in_cmd_pending <= 1'b0;
else if(~cmd_credit_run_out && tlx_in_cmd_pending)
tlx_in_cmd_pending <= 1'b0;
else if(tlx_in_cmd_req_pipe[2] && ~tlx_in_cmd_rec)
tlx_in_cmd_pending <= 1'b1;
assign tlx_interrupt_valid_pre = ~cmd_credit_run_out && tlx_in_cmd_pending;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
tlx_interrupt_valid <= 1'b0;
else
tlx_interrupt_valid <= tlx_interrupt_valid_pre;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
begin
tlx_in_cmd_opcode_sync <= 8'd0;
tlx_in_cmd_afutag_sync <= 16'd0;
tlx_in_cmd_obj_sync <= 68'd0;
tlx_in_cmd_pasid_sync <= 20'd0;
tlx_in_cmd_actag_sync <= 12'd0;
end
else if(tlx_in_cmd_valid)
begin
tlx_in_cmd_opcode_sync <= tlx_in_cmd_opcode;
tlx_in_cmd_afutag_sync <= tlx_in_cmd_afutag;
tlx_in_cmd_obj_sync <= tlx_in_cmd_obj;
tlx_in_cmd_pasid_sync <= tlx_in_cmd_pasid;
tlx_in_cmd_actag_sync <= tlx_in_cmd_actag;
end
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
tlx_interrupt_opcode <= 8'd0;
tlx_interrupt_afutag <= 16'd0;
tlx_interrupt_obj <= 68'd0;
tlx_interrupt_pasid <= 20'd0;
tlx_interrupt_actag <= 12'd0;
end
else
begin
tlx_interrupt_opcode <= tlx_in_cmd_opcode_sync;
tlx_interrupt_afutag <= tlx_in_cmd_afutag_sync;
tlx_interrupt_obj <= tlx_in_cmd_obj_sync;
tlx_interrupt_pasid <= tlx_in_cmd_pasid_sync;
tlx_interrupt_actag <= tlx_in_cmd_actag_sync;
end
always@(posedge clk_tlx or negedge rst_n)
begin
if(~rst_n)
context_buffer_cmd_valid <= 1'b0;
else if(!context_input_cmd_ready && (fifo_w_cmdcnv_dv || fifo_r_cmdcnv_dv || tlx_interrupt_valid))
context_buffer_cmd_valid <= 1'b1;
else if(context_input_cmd_ready)
context_buffer_cmd_valid <= 1'b0;
end
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
context_buffer_cmd_opcode <= 8'd0;
context_buffer_cmd_afutag <= 16'd0;
context_buffer_cmd_ea_or_obj <= 68'd0;
context_buffer_cmd_dl <= 2'd0;
context_buffer_cmd_pl <= 3'd0;
context_buffer_cmd_actag <= 12'd0;
context_buffer_cmd_pasid <= 20'd0;
end
else if(!context_input_cmd_ready && (fifo_w_cmdcnv_dv || fifo_r_cmdcnv_dv || tlx_interrupt_valid))
begin
context_buffer_cmd_opcode <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_opcode :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_opcode :
tlx_interrupt_opcode);
context_buffer_cmd_afutag <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_afutag :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_afutag :
tlx_interrupt_afutag);
context_buffer_cmd_ea_or_obj <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_ea :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_ea :
tlx_interrupt_obj);
context_buffer_cmd_dl <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_dl : fifo_r_cmdcnv_dout_dl;
context_buffer_cmd_pl <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_pl : fifo_r_cmdcnv_dout_pl;
context_buffer_cmd_actag <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_actag :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_actag :
tlx_interrupt_actag);
context_buffer_cmd_pasid <= fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_pasid :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_pasid :
tlx_interrupt_pasid);
end
assign context_input_cmd_ready = context_surveil_stage1_ready;
assign context_input_wr_en = context_buffer_cmd_valid || fifo_w_cmdcnv_dv || fifo_r_cmdcnv_dv || tlx_interrupt_valid;
always@(posedge clk_tlx or negedge rst_n)
begin
if(~rst_n)
context_input_cmd_valid <= 1'b0;
else if(context_input_wr_en && context_input_cmd_ready)
context_input_cmd_valid <= 1'b1;
else if(context_surveil_stage1_ready)
context_input_cmd_valid <= 1'b0;
end
//---- output MUX for context surveil module----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
context_input_cmd_opcode <= 8'd0;
context_input_cmd_afutag <= 16'd0;
context_input_cmd_ea_or_obj <= 68'd0;
context_input_cmd_dl <= 2'd0;
context_input_cmd_pl <= 3'd0;
context_input_cmd_actag <= 12'd0;
context_input_cmd_pasid <= 20'd0;
end
else if(context_input_wr_en && context_input_cmd_ready)
begin
context_input_cmd_opcode <= context_buffer_cmd_valid ? context_buffer_cmd_opcode :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_opcode :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_opcode :
tlx_interrupt_opcode));
context_input_cmd_afutag <= context_buffer_cmd_valid ? context_buffer_cmd_afutag :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_afutag :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_afutag :
tlx_interrupt_afutag));
context_input_cmd_ea_or_obj <= context_buffer_cmd_valid ? context_buffer_cmd_ea_or_obj :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_ea :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_ea :
tlx_interrupt_obj));
context_input_cmd_dl <= context_buffer_cmd_valid ? context_buffer_cmd_dl :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_dl : fifo_r_cmdcnv_dout_dl);
context_input_cmd_pl <= context_buffer_cmd_valid ? context_buffer_cmd_pl :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_pl : fifo_r_cmdcnv_dout_pl);
context_input_cmd_actag <= context_buffer_cmd_valid ? context_buffer_cmd_actag :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_actag :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_actag :
tlx_interrupt_actag));
context_input_cmd_pasid <= context_buffer_cmd_valid ? context_buffer_cmd_pasid :
(fifo_w_cmdcnv_dv? fifo_w_cmdcnv_dout_pasid :
(fifo_r_cmdcnv_dv? fifo_r_cmdcnv_dout_pasid :
tlx_interrupt_pasid));
end
brdg_context_surveil m_context_surveil (
.clk (clk_tlx ),
.rst_n (rst_n ),
.tlx_cmd_s1_ready (context_surveil_stage1_ready ),
.tlx_wdata_rdrq (context_surveil_wdata_e_rdrq ),
.tlx_i_cmd_valid (context_input_cmd_valid ),
.tlx_i_cmd_opcode (context_input_cmd_opcode ),
.tlx_i_cmd_afutag (context_input_cmd_afutag ),
.tlx_i_cmd_ea_or_obj (context_input_cmd_ea_or_obj ),
.tlx_i_cmd_dl (context_input_cmd_dl ),
.tlx_i_cmd_pl (context_input_cmd_pl ),
.tlx_i_cmd_actag (context_input_cmd_actag ),
.tlx_i_cmd_pasid (context_input_cmd_pasid ),
.tlx_o_cmd_valid (context_output_cmd_valid),
.tlx_o_cmd_opcode (context_output_cmd_opcode ),
.tlx_o_cmd_afutag (context_output_cmd_afutag ),
.tlx_o_cmd_ea_or_obj (context_output_cmd_ea_or_obj ),
.tlx_o_cmd_dl (context_output_cmd_dl ),
.tlx_o_cmd_pl (context_output_cmd_pl ),
.tlx_o_cmd_actag (context_output_cmd_actag ),
.tlx_o_cmd_pasid (context_output_cmd_pasid ),
.tlx_afu_cmd_ready (tlx_afu_cmd_ready )
);
//-----------------------------------------------------------------------------------------------------------------
// afu_tlx interface
//-----------------------------------------------------------------------------------------------------------------
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
dl_1_dly <= 1'b0;
else
dl_1_dly <= afu_tlx_cmd_dl[1]; // indicate whether the write command send in the previous cycle need a second data
assign afu_tlx_cmd_valid = context_output_cmd_valid ;
assign afu_tlx_cmd_opcode = context_output_cmd_opcode ;
assign afu_tlx_cmd_afutag = context_output_cmd_afutag ;
assign afu_tlx_cmd_ea_or_obj = context_output_cmd_ea_or_obj;
assign afu_tlx_cmd_dl = context_output_cmd_dl ;
assign afu_tlx_cmd_pl = context_output_cmd_pl ;
assign afu_tlx_cmd_actag = context_output_cmd_actag ;
assign afu_tlx_cmd_pasid = context_output_cmd_pasid ;
assign afu_tlx_cdata_valid = (fifo_w_datcnv_o_dv && dl_1_dly) || fifo_w_datcnv_e_dv;
assign afu_tlx_cdata_bus = fifo_w_datcnv_e_dv ? fifo_w_datcnv_e_dout : fifo_w_datcnv_o_dout;
//---- defaults ----
assign afu_tlx_cmd_stream_id = 4'd0;
assign afu_tlx_cmd_os = 1'd0;
assign afu_tlx_cmd_be = 64'd0;
assign afu_tlx_cmd_flag = 4'd0;
assign afu_tlx_cmd_endian = 1'd0;
assign afu_tlx_cmd_bdf = {cfg_bdf_bus, cfg_bdf_device, cfg_bdf_function};
assign afu_tlx_cmd_pg_size = 6'd0;
assign afu_tlx_cdata_bdi = 1'b0;
//-----------------------------------------------------------------------------------------------------------------
// CREDIT MANAGEMENT
//-----------------------------------------------------------------------------------------------------------------
assign tlx_afu_cmd_ready = !cmd_credit_run_out && (!cmd_data_credit_lt_2);
//---- command and write data credit counters ----
always@(posedge clk_tlx)
if(~rst_n)
cmd_credit_cnt <= tlx_afu_cmd_initial_credit; // this should be set through soft resetting
else
case({tlx_afu_cmd_credit, afu_tlx_cmd_valid})
2'b10 : cmd_credit_cnt <= cmd_credit_cnt + 4'd1;
2'b01 : cmd_credit_cnt <= cmd_credit_cnt - 4'd1;
default:;
endcase
always@(posedge clk_tlx)
if(~rst_n)
cmd_data_credit_cnt <= tlx_afu_cmd_data_initial_credit;
else
case({tlx_afu_cmd_data_credit, afu_tlx_cdata_valid})
2'b10 : cmd_data_credit_cnt <= cmd_data_credit_cnt + 6'd1;
2'b01 : cmd_data_credit_cnt <= cmd_data_credit_cnt - 6'd1;
default:;
endcase
//---- credit deficiency alert ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
cmd_credit_run_out <= 1'b0;
cmd_data_credit_lt_2 <= 1'b0;
end
else
begin
cmd_credit_run_out <= (cmd_credit_cnt <= 4'd3);
cmd_data_credit_lt_2 <= (cmd_data_credit_cnt < 6'd5);
end
//=================================================================================================================
// STATUS output for SNAP registers
//=================================================================================================================
reg [31:0] cmd_idle_cnt;
reg cmd_idle;
reg [31:0] cmd_idle_lim;
//---- DEBUG registers ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_idle <= 1'b0;
else if(afu_tlx_cmd_valid)
cmd_idle <= 1'b0;
else if(cmd_idle_cnt == cmd_idle_lim)
cmd_idle <= 1'b1;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_idle_cnt <= 32'd0;
else if(afu_tlx_cmd_valid)
cmd_idle_cnt <= 32'd0;
else
cmd_idle_cnt <= cmd_idle_cnt + 32'd1;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_idle_lim <= 32'd0;
else
cmd_idle_lim <= debug_tlx_cmd_idle_lim;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
debug_tlx_cmd_idle <= 1'b0;
else
debug_tlx_cmd_idle <= cmd_idle;
//---- FAULT ISOLATION REGISTER ----
reg fir_cmd_credit_breach;
reg fir_cmd_credit_data_breach;
reg fir_fifo_r_cmdcnv_overflow;
reg fir_fifo_w_datcnv_e_overflow;
reg fir_fifo_w_datcnv_o_overflow;
reg fir_fifo_w_cmdcnv_overflow;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
fir_cmd_credit_breach <= 1'b0;
fir_cmd_credit_data_breach <= 1'b0;
fir_fifo_r_cmdcnv_overflow <= 1'b0;
fir_fifo_w_datcnv_e_overflow <= 1'b0;
fir_fifo_w_datcnv_o_overflow <= 1'b0;
fir_fifo_w_cmdcnv_overflow <= 1'b0;
end
else
begin
if (afu_tlx_cmd_valid && (cmd_credit_cnt == 4'd0)) fir_cmd_credit_breach <= 1'b1;
if (afu_tlx_cdata_valid && (cmd_data_credit_cnt == 4'd0)) fir_cmd_credit_data_breach <= 1'b1;
if (fifo_r_cmdcnv_ovfl) fir_fifo_r_cmdcnv_overflow <= 1'b1;
if (fifo_w_datcnv_e_ovfl) fir_fifo_w_datcnv_e_overflow <= 1'b1;
if (fifo_w_datcnv_o_ovfl) fir_fifo_w_datcnv_o_overflow <= 1'b1;
if (fifo_w_cmdcnv_ovfl) fir_fifo_w_cmdcnv_overflow <= 1'b1;
end
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
begin
fir_fifo_overflow <= 4'd0;
fir_tlx_command_credit <= 2'd0;
end
else
begin
fir_fifo_overflow <= { fir_fifo_r_cmdcnv_overflow, fir_fifo_w_datcnv_e_overflow, fir_fifo_w_datcnv_o_overflow, fir_fifo_w_cmdcnv_overflow };
fir_tlx_command_credit <= { fir_cmd_credit_breach, fir_cmd_credit_data_breach};
end
//==== PSL ASSERTION ==============================================================================
// psl PREMATURE_INTERRUPT : assert never (tlx_in_cmd_valid && tlx_in_cmd_req) @(posedge clk_afu) report "interrupt precedes the last acknowledgement! The interrupt command should never be sent until the last interrupt ackowledgement is confirmed.";
// psl TLX_COMMAND_CHANNELS_CONFLICT : assert always onehot0({fifo_w_cmdcnv_dv, fifo_r_cmdcnv_dv, tlx_interrupt_valid}) @(posedge clk_tlx) report "TLX commands from write/read/assign_actag/interrupt have conflicts! Each time there's only one channel from write, read, assign_actag and interrupt being enabled.";
// psl TLX_COMMAND_WRITE_DATA_DEFICIENT : assert always ((fifo_w_cmdcnv_rdrq && fifo_w_datcnv_e_rdrq) -> next(fifo_w_datcnv_o_rdrq)) @(posedge clk_tlx) report "lacking command data to TLX! The odd data FIFO should always be read following the reading of even data FIFO.";
//==== PSL ASSERTION ==============================================================================
//==== PSL COVERAGE ==============================================================================
// psl SINGLE_COMMAND_I : cover {(tlx_interrupt_valid)} @(posedge clk_tlx) ;
// psl DUPLEX_COMMAND_W_R : cover {fifo_w_cmdcnv_dv; fifo_r_cmdcnv_dv} @(posedge clk_tlx) ;
// psl DUPLEX_COMMAND_R_W : cover {fifo_r_cmdcnv_dv; fifo_w_cmdcnv_dv} @(posedge clk_tlx) ;
// psl CMD_CREDIT_RUNOUT : cover {(cmd_credit_run_out)} @(posedge clk_tlx);
// psl CMD_CREDIT_LT_2 : cover {(cmd_data_credit_lt_2)} @(posedge clk_tlx);
// psl DMA_CMD_JAM : cover {(tlx_wr_cmd_ready || tlx_rd_cmd_ready)} @(posedge clk_afu);
//==== PSL COVERAGE ==============================================================================
endmodule |
module brdg_axi_slave
(
input clk,
input rst_n,
//---- local bus --------------------
// "early" means it should be 1 cycle earlier than lcl_wr_valid or lcl_rd_valid
// write address & data channel
output lcl_wr_valid, //A valid write beat to bridge
output reg [63:0] lcl_wr_ea, //Effective address
output reg [`IDW-1:0] lcl_wr_axi_id, //AXI ID of current beat
output [127:0] lcl_wr_be, //Byte enable of current beat
output lcl_wr_first, //This is the first beat in a burst
output lcl_wr_last, //This is the last beat in a burst
output [1023:0] lcl_wr_data, //Write data
output lcl_wr_idle, //Current write channel is idle,
input lcl_wr_ready, //From bridge
// write ctx channel
output reg lcl_wr_ctx_valid, //Indicate current write context is valid (one cycle)
output reg [`CTXW-1:0] lcl_wr_ctx, //AWUSER in AXI world and PASID in TLX world
// write response channel
input lcl_wr_rsp_valid, //A response valid from bridge
input [`IDW-1:0] lcl_wr_rsp_axi_id, //AXI ID of current beat in response
input lcl_wr_rsp_code, //Response code. 0: good; 1: error
output lcl_wr_rsp_ready, //axi_slave is ready to accept the response.
input [`CTXW-1:0] lcl_wr_rsp_ctx ,
// read address channel
output lcl_rd_valid, //A valid read beat command
output reg [63:0] lcl_rd_ea, //Effective address
output reg [`IDW-1:0] lcl_rd_axi_id, //AXI ID of current beat
output [127:0] lcl_rd_be, //Byte enable of current beat
output lcl_rd_first, //This is the first beat in a burst
output lcl_rd_last, //This is the last beat in a burst
output lcl_rd_idle, //Current read channel is idle,
input lcl_rd_ready, //From bridge
// read ctx channel
output reg lcl_rd_ctx_valid, //Indicate current read context is valid (one cycle)
output reg [`CTXW-1:0] lcl_rd_ctx, //ARUSER in AXI world and PASID in TLX world
// read response & data channel
input lcl_rd_data_valid, //Data valid from bridge
input [`IDW-1:0] lcl_rd_data_axi_id,//AXI ID of current beat in response
input [1023:0] lcl_rd_data, //Read data for the current beat
input [`CTXW-1:0] lcl_rd_data_ctx ,
input lcl_rd_data_last, //This the last beat in a burst
input lcl_rd_rsp_code, //Response code. 0: good; 1: error
output lcl_rd_data_ready, //To bridge: axi_slave is ready to accept the response.
//---- AXI bus ----------------------
// AXI write address channel
input [`IDW-1:0] s_axi_awid,
input [63:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [`CTXW-1:0] s_axi_awuser,
input s_axi_awvalid,
output reg s_axi_awready,
// AXI write data channel
// We suppose wuser = awuser. No wuser input.
input [1023:0] s_axi_wdata,
input [127:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// AXI write response channel
output reg [`IDW-1:0] s_axi_bid,
output reg [1:0] s_axi_bresp,
output reg [`CTXW-1:0] s_axi_buser,
output reg s_axi_bvalid,
input s_axi_bready,
// AXI read address channel
input [`IDW-1:0] s_axi_arid,
input [63:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [`CTXW-1:0] s_axi_aruser,
input s_axi_arvalid,
output reg s_axi_arready,
// AXI read data channel
output reg [`IDW-1:0] s_axi_rid,
output reg [1023:0] s_axi_rdata,
output reg [1:0] s_axi_rresp,
output reg [`CTXW-1:0]s_axi_ruser,
output reg s_axi_rlast,
output reg s_axi_rvalid,
input s_axi_rready
);
parameter AXI_FIXED=2'b00,
AXI_INCR=2'b01,
AXI_WRAP=2'b10;
parameter AXI_OKAY=2'b00,
AXI_EXOKAY=2'b01,
AXI_SLVERR=2'b10,
AXI_DECERR=2'b11;
//=============================================================================================
// Address phase
// Input: addr, len, size, burst
// Output: ea, be1_q
//
// be1_q is generated in address phase, decided by ea[6:0] and size;
// for both read and write.
//
// For write, we will still 'AND' wstrb with be1_q together in data phase
//=============================================================================================
//
//1st ea = axi_addr;
//Following ea = ea_aligned_q, step = ea_incr_q; (INCR)
// or ea_aligned_q, (FIXED)
// or ea_aligned_q, step = ea_incr_q; if hit upper_wrap_boundary, go
// to lower_wrap_boundary (WRAP) (TODO: not implement in first draft)
//
// be1_q = (byte_mask << ea[6:0]);
// For read: be = be1_q
// For write: be = be1_q & wstrb
//=============================================================================================
// All AXI commands AR* and AW* will enter axi_slave_cmd_fifo first.
//=====================================AR======================================================
parameter RD_IDLE = 4'b0001,
RD_REQ_FIRST = 4'b0010,
RD_HOLD_FIRST = 4'b0100,
RD_REQ_REMAINING = 4'b1000;
wire ar_cf_empty;
wire ar_cf_almost_full;
wire ar_cf_full;
wire ar_cf_rd_en;
wire [`IDW-1:0] ar_cf_id;
wire [63:0] ar_cf_addr;
wire [7:0] ar_cf_len;
wire [2:0] ar_cf_size;
wire [1:0] ar_cf_burst;
wire [`CTXW-1:0] ar_cf_user;
reg [3:0] rd_cstate, rd_nstate;
reg [7:0] rd_beat_counter;
reg [7:0] rd_ea_incr_q;
wire [63:0] rd_ea_next;
reg [63:0] rd_ea_aligned_q;
reg [6:0] rd_ea_low_mask;
reg [127:0] rd_byte_mask;
reg [127:0] rd_byte_mask_q;
reg [1:0] rd_burst_q;
reg [127:0] rd_be1_q;
wire rd_addr_present;
wire burst_wr_ctx_valid; //Indicate current write context is valid (one cycle) (early)
wire [`CTXW-1:0] burst_wr_ctx; //AWUSER in AXI world and PASID in TLX world
wire burst_rd_ctx_valid; //Indicate current write context is valid (one cycle) (early)
wire [`CTXW-1:0] burst_rd_ctx; //AWUSER in AXI world and PASID in TLX world
brdg_axi_slave_cmd_fifo ar_cf(
.clk (clk ),
.rst_n (rst_n ),
.axi_id (s_axi_arid ),
.axi_addr (s_axi_araddr ),
.axi_len (s_axi_arlen ),
.axi_size (s_axi_arsize ),
.axi_burst (s_axi_arburst ),
.axi_user (s_axi_aruser ),
.cf_id (ar_cf_id ),
.cf_addr (ar_cf_addr ),
.cf_len (ar_cf_len ),
.cf_size (ar_cf_size ),
.cf_burst (ar_cf_burst ),
.cf_user (ar_cf_user ),
.cf_wr_en (rd_addr_present ),
.cf_full (ar_cf_full ),
.cf_almost_full (ar_cf_almost_full),
.cf_empty (ar_cf_empty ),
.cf_rd_en (ar_cf_rd_en )
);
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_arready <= 1'b1;
else if (ar_cf_almost_full || ar_cf_full)
s_axi_arready <= 1'b0;
else
s_axi_arready <= 1'b1;
//=====================================AW======================================================
parameter WR_IDLE = 6'b000001,
WR_WAIT_ADDR = 6'b000010,
WR_REQ_FIRST = 6'b000100,
WR_HOLD_FIRST = 6'b001000,
WR_REQ_REMAINING = 6'b010000,
WR_WAIT_DATA = 6'b100000;
wire aw_cf_empty;
wire aw_cf_almost_full;
wire aw_cf_full;
wire aw_cf_rd_en;
wire [`IDW-1:0] aw_cf_id;
wire [63:0] aw_cf_addr;
wire [7:0] aw_cf_len;
wire [2:0] aw_cf_size;
wire [1:0] aw_cf_burst;
wire [`CTXW-1:0] aw_cf_user;
reg [5:0] wr_cstate, wr_nstate;
reg [7:0] wr_beat_counter;
reg [7:0] wr_ea_incr_q;
wire [63:0] wr_ea_next;
reg [63:0] wr_ea_aligned_q;
reg [6:0] wr_ea_low_mask;
reg [127:0] wr_byte_mask;
reg [127:0] wr_byte_mask_q;
reg [127:0] wr_be1_q;
reg [1:0] wr_burst_q;
wire wr_addr_present;
wire wr_data_present;
reg [1023:0] wdata_q;
reg [127:0] wstrb_q;
brdg_axi_slave_cmd_fifo aw_cf (
.clk (clk ),
.rst_n (rst_n ),
.axi_id (s_axi_awid ),
.axi_addr (s_axi_awaddr ),
.axi_len (s_axi_awlen ),
.axi_size (s_axi_awsize ),
.axi_burst (s_axi_awburst ),
.axi_user (s_axi_awuser ),
.cf_id (aw_cf_id ),
.cf_addr (aw_cf_addr ),
.cf_len (aw_cf_len ),
.cf_size (aw_cf_size ),
.cf_burst (aw_cf_burst ),
.cf_user (aw_cf_user ),
.cf_wr_en (wr_addr_present ),
.cf_full (aw_cf_full ),
.cf_almost_full (aw_cf_almost_full),
.cf_empty (aw_cf_empty ),
.cf_rd_en (aw_cf_rd_en )
);
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_awready <= 1'b1;
else if (aw_cf_almost_full || aw_cf_full)
s_axi_awready <= 1'b0;
else
s_axi_awready <= 1'b1;
//=============================================================================================
// WRITE COMMAND+DATA CHANNEL
//=============================================================================================
// Need to wait for write data, use wvalid/wready as the trigger
// Sending commands when W data comes (wr_data_present)
//
// State Machine to send lcl_wr*
assign wr_addr_present = s_axi_awvalid && s_axi_awready;
assign wr_data_present = s_axi_wvalid && s_axi_wready;
always@(posedge clk or negedge rst_n)
if(~rst_n)
wr_cstate <= WR_IDLE;
else
wr_cstate <= wr_nstate;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
wdata_q <= 1024'h0;
wstrb_q <= 128'hffffffff_ffffffff_ffffffff_ffffffff;
end
else if (wr_data_present) begin
wdata_q <= s_axi_wdata;
wstrb_q <= s_axi_wstrb;
end
always@*
if(wr_cstate == WR_IDLE) begin
if (wr_data_present) begin //I already have one valid data beat to send
if (aw_cf_empty)
wr_nstate = WR_WAIT_ADDR;
else
wr_nstate = WR_REQ_FIRST;
end
else
wr_nstate = WR_IDLE;
end
//-------------------------------------
else if (wr_cstate == WR_WAIT_ADDR) begin
if (aw_cf_empty)
wr_nstate = WR_WAIT_ADDR;
else
wr_nstate = WR_REQ_FIRST;
end
//-------------------------------------
else if (wr_cstate == WR_REQ_FIRST || wr_cstate == WR_HOLD_FIRST || wr_cstate == WR_REQ_REMAINING) begin
if (lcl_wr_ready) begin
if (wr_beat_counter == 8'd0) begin //This is the last beat
if (wr_data_present) //Deal with new burst
if (aw_cf_empty)
wr_nstate = WR_WAIT_ADDR;
else
wr_nstate = WR_REQ_FIRST;
else
wr_nstate = WR_IDLE;
end
else //Deal with next beat in this burst
if (wr_data_present)
wr_nstate = WR_REQ_REMAINING;
else
wr_nstate = WR_WAIT_DATA;
end
else begin
if(wr_cstate == WR_REQ_REMAINING)
wr_nstate = WR_REQ_REMAINING;
else
wr_nstate = WR_HOLD_FIRST;
end
end
//-------------------------------------
else if (wr_cstate == WR_WAIT_DATA) begin
if (wr_data_present)
wr_nstate = WR_REQ_REMAINING;
else
wr_nstate = WR_WAIT_DATA;
end
//-------------------------------------
else
wr_nstate = WR_IDLE;
always@(posedge clk or negedge rst_n)
if(~rst_n)
wr_beat_counter <= 8'hFF;
else if (wr_nstate == WR_IDLE)
wr_beat_counter <= 8'hFF;
else begin
if (wr_nstate == WR_REQ_FIRST) //Address information is ready
wr_beat_counter <= aw_cf_len;
else if (lcl_wr_valid && lcl_wr_ready && wr_beat_counter >= 1) //A real data has been send to bridge
wr_beat_counter = wr_beat_counter - 8'd1;
end
always@*
case (aw_cf_size)
3'h0: wr_ea_low_mask = 7'b1111111;
3'h1: wr_ea_low_mask = 7'b1111110;
3'h2: wr_ea_low_mask = 7'b1111100;
3'h3: wr_ea_low_mask = 7'b1111000;
3'h4: wr_ea_low_mask = 7'b1110000;
3'h5: wr_ea_low_mask = 7'b1100000;
3'h6: wr_ea_low_mask = 7'b1000000;
3'h7: wr_ea_low_mask = 7'b0000000;
default: wr_ea_low_mask = 7'h0;
endcase
always@*
case (aw_cf_size)
3'h0: wr_byte_mask = 128'h00000000_00000000_00000000_00000001;
3'h1: wr_byte_mask = 128'h00000000_00000000_00000000_00000003;
3'h2: wr_byte_mask = 128'h00000000_00000000_00000000_0000000f;
3'h3: wr_byte_mask = 128'h00000000_00000000_00000000_000000ff;
3'h4: wr_byte_mask = 128'h00000000_00000000_00000000_0000ffff;
3'h5: wr_byte_mask = 128'h00000000_00000000_00000000_ffffffff;
3'h6: wr_byte_mask = 128'h00000000_00000000_ffffffff_ffffffff;
3'h7: wr_byte_mask = 128'hffffffff_ffffffff_ffffffff_ffffffff;
default: wr_byte_mask = 128'hffffffff_ffffffff_ffffffff_ffffffff;
endcase
assign wr_ea_next = wr_ea_aligned_q + wr_ea_incr_q;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
lcl_wr_ea <= 64'h0;
wr_ea_incr_q <= 8'd128;
wr_ea_aligned_q <= 64'h0;
wr_be1_q <= 128'hffffffff_ffffffff_ffffffff_ffffffff;
wr_byte_mask_q <= 128'hffffffff_ffffffff_ffffffff_ffffffff;
wr_burst_q <= AXI_INCR;
end
else begin
if (wr_nstate == WR_REQ_FIRST) begin
lcl_wr_ea <= aw_cf_addr;
wr_ea_incr_q <= (8'h1 << aw_cf_size);
wr_ea_aligned_q <= {aw_cf_addr[63:7], aw_cf_addr[6:0]&wr_ea_low_mask};
wr_be1_q <= (wr_byte_mask << aw_cf_addr[6:0]);
wr_byte_mask_q <= wr_byte_mask;
wr_burst_q <= aw_cf_burst;
end
else if (wr_nstate == WR_REQ_REMAINING && lcl_wr_ready == 1) begin
if(wr_burst_q == AXI_INCR) begin
lcl_wr_ea <= wr_ea_next;
wr_ea_aligned_q <= wr_ea_next;
wr_be1_q <= (wr_byte_mask_q << wr_ea_next[6:0]);
end
//AXI_FIXED: lcl_wr_ea doesn't change.
//AXI_WRAP: Not supported.
end
end
assign lcl_wr_valid = (wr_cstate == WR_REQ_FIRST || wr_cstate == WR_HOLD_FIRST || wr_cstate == WR_REQ_REMAINING);
assign lcl_wr_data = wdata_q;
assign lcl_wr_be = wstrb_q & wr_be1_q;
assign lcl_wr_first = (wr_cstate == WR_REQ_FIRST || wr_cstate == WR_HOLD_FIRST) && lcl_wr_ready;
//assign lcl_wr_first = (wr_nstate == WR_REQ_FIRST || wr_nstate == WR_HOLD_FIRST) && lcl_wr_ready;
assign lcl_wr_idle = (wr_nstate == WR_IDLE || wr_nstate == WR_WAIT_ADDR); //One cycle earlier before lcl_wr_valid.
//assign lcl_wr_last = (wr_beat_counter == 0) && lcl_wr_ready && lcl_rd_ready; //??
assign lcl_wr_last = (wr_beat_counter == 0) && lcl_wr_ready && lcl_wr_valid;
//The state machine can deal with current aw* command in next cycle.
//So there is no need to enter the fifo
//s_axi_wready: if bridge cannot handle it (lcl_wr_ready=0), pull down;
// if command info (aw*) hasn't arrived, pull down;
assign s_axi_wready = lcl_wr_ready && ~(wr_cstate == WR_WAIT_ADDR);
assign aw_cf_rd_en = ~aw_cf_empty && (wr_nstate == WR_REQ_FIRST);
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
lcl_wr_axi_id <= 0;
end
else if (wr_nstate == WR_IDLE) begin
lcl_wr_axi_id <= 0;
end
else if (wr_nstate == WR_REQ_FIRST) begin
lcl_wr_axi_id <= aw_cf_id;
end
assign burst_wr_ctx_valid = (wr_nstate == WR_REQ_FIRST); //One cycle earlier before lcl_wr_valid.
assign burst_wr_ctx = (wr_nstate == WR_REQ_FIRST) ? aw_cf_user : 0;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
lcl_wr_ctx_valid <= 1'b0;
else
lcl_wr_ctx_valid <= burst_wr_ctx_valid;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
lcl_wr_ctx <= {`CTXW{1'b0}};
else if(burst_wr_ctx_valid)
lcl_wr_ctx <= burst_wr_ctx;
end
//=============================================================================================
// READ COMMAND CHANNEL
//=============================================================================================
// When ar_cf is not empty, we can send read requests.
// State Machine to send lcl_rd*
assign rd_addr_present = s_axi_arvalid && s_axi_arready;
//The state machine can deal with current ar* command in next cycle.
//So there is no need to enter the fifo.
always@(posedge clk or negedge rst_n)
if(~rst_n)
rd_cstate <= RD_IDLE;
else
rd_cstate <= rd_nstate;
always@*
if(rd_cstate == RD_IDLE) begin
if (~ar_cf_empty)
rd_nstate = RD_REQ_FIRST;
else
rd_nstate = RD_IDLE;
end
//-------------------------------------
else if (rd_cstate == RD_REQ_FIRST || rd_cstate == RD_HOLD_FIRST || rd_cstate == RD_REQ_REMAINING) begin
if(lcl_rd_ready) begin
if(rd_beat_counter == 8'd0) begin //This is the last beat
if (~ar_cf_empty) //There is new burst
rd_nstate = RD_REQ_FIRST;
else
rd_nstate = RD_IDLE;
end
else
rd_nstate = RD_REQ_REMAINING;
end
else begin
if (rd_cstate == RD_REQ_REMAINING)
rd_nstate = RD_REQ_REMAINING;
else
rd_nstate = RD_HOLD_FIRST;
end
end
//-------------------------------------
else
rd_nstate = RD_IDLE;
always@(posedge clk or negedge rst_n)
if(~rst_n)
rd_beat_counter <= 8'hFF;
else if (rd_nstate == RD_IDLE)
rd_beat_counter <= 8'hFF;
else begin
if (rd_nstate == RD_REQ_FIRST) //Initial value, address information is ready
rd_beat_counter <= ar_cf_len;
else if (lcl_rd_valid && lcl_rd_ready && rd_beat_counter >= 1)
rd_beat_counter = rd_beat_counter - 8'd1;
end
always@*
case (ar_cf_size)
3'h0: rd_ea_low_mask = 7'b1111111;
3'h1: rd_ea_low_mask = 7'b1111110;
3'h2: rd_ea_low_mask = 7'b1111100;
3'h3: rd_ea_low_mask = 7'b1111000;
3'h4: rd_ea_low_mask = 7'b1110000;
3'h5: rd_ea_low_mask = 7'b1100000;
3'h6: rd_ea_low_mask = 7'b1000000;
3'h7: rd_ea_low_mask = 7'b0000000;
default: rd_ea_low_mask = 7'h0;
endcase
always@*
case (ar_cf_size)
3'h0: rd_byte_mask = 128'h00000000_00000000_00000000_00000001;
3'h1: rd_byte_mask = 128'h00000000_00000000_00000000_00000003;
3'h2: rd_byte_mask = 128'h00000000_00000000_00000000_0000000f;
3'h3: rd_byte_mask = 128'h00000000_00000000_00000000_000000ff;
3'h4: rd_byte_mask = 128'h00000000_00000000_00000000_0000ffff;
3'h5: rd_byte_mask = 128'h00000000_00000000_00000000_ffffffff;
3'h6: rd_byte_mask = 128'h00000000_00000000_ffffffff_ffffffff;
3'h7: rd_byte_mask = 128'hffffffff_ffffffff_ffffffff_ffffffff;
default: rd_byte_mask = 128'hffffffff_ffffffff_ffffffff_ffffffff;
endcase
assign rd_ea_next = rd_ea_aligned_q + rd_ea_incr_q;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
lcl_rd_ea <= 64'h0;
rd_ea_incr_q <= 8'd128;
rd_ea_aligned_q <= 64'h0;
rd_be1_q <= 128'hffffffff_ffffffff_ffffffff_ffffffff;
rd_byte_mask_q <= 128'hffffffff_ffffffff_ffffffff_ffffffff;
rd_burst_q <= AXI_INCR;
end
else begin
if (rd_nstate == RD_REQ_FIRST) begin //Initial value
lcl_rd_ea <= ar_cf_addr;
rd_ea_incr_q <= (8'h1 << ar_cf_size);
rd_ea_aligned_q <= {ar_cf_addr[63:7], ar_cf_addr[6:0]&rd_ea_low_mask};
rd_be1_q <= (rd_byte_mask << ar_cf_addr[6:0]);
rd_byte_mask_q <= rd_byte_mask;
rd_burst_q <= ar_cf_burst;
end
else if (lcl_rd_valid && lcl_rd_ready) begin //Update
if(rd_burst_q == AXI_INCR) begin
lcl_rd_ea <= rd_ea_next;
rd_ea_aligned_q <= rd_ea_next;
rd_be1_q <= (rd_byte_mask_q << rd_ea_next[6:0]);
end
//AXI_FIXED: lcl_rd_ea doesn't change.
//AXI_WRAP: Not supported.
end
end
assign lcl_rd_valid = (rd_cstate != RD_IDLE);
assign lcl_rd_be = rd_be1_q;
assign lcl_rd_first = (rd_cstate == RD_REQ_FIRST || rd_cstate == RD_HOLD_FIRST) && lcl_rd_ready;
assign lcl_rd_idle = (rd_nstate == RD_IDLE); //One cycle earlier before lcl_rd_valid.
assign lcl_rd_last = (rd_beat_counter == 0) && lcl_rd_ready && lcl_rd_valid;
assign ar_cf_rd_en = ~ar_cf_empty && (rd_nstate == RD_REQ_FIRST);
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
lcl_rd_axi_id <= 0;
end
else if (rd_nstate == RD_IDLE) begin
lcl_rd_axi_id <= 0;
end
else if (rd_nstate == RD_REQ_FIRST) begin
lcl_rd_axi_id <= ar_cf_id;
end
assign burst_rd_ctx_valid = (rd_nstate == RD_REQ_FIRST); //One cycle earlier before lcl_rd_valid.
assign burst_rd_ctx = (rd_nstate == RD_REQ_FIRST) ? ar_cf_user : 0;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
lcl_rd_ctx_valid <= 1'b0;
else
lcl_rd_ctx_valid <= burst_rd_ctx_valid;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
lcl_rd_ctx <= {`CTXW{1'b0}};
else if(burst_rd_ctx_valid)
lcl_rd_ctx <= burst_rd_ctx;
end
//=============================================================================================
// WRITE RESPONSE CHANNEL
//=============================================================================================
//---- AXI write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_bvalid <= 1'b0;
else if(lcl_wr_rsp_valid && lcl_wr_rsp_ready)
s_axi_bvalid <= 1'b1;
else if(s_axi_bready)
s_axi_bvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
s_axi_bid <= 0;
s_axi_bresp <= AXI_OKAY;
s_axi_buser <= 0;
end
else if(lcl_wr_rsp_valid && lcl_wr_rsp_ready) begin
s_axi_bid <= lcl_wr_rsp_axi_id;
s_axi_bresp <= lcl_wr_rsp_code;
s_axi_buser <= lcl_wr_rsp_ctx;
end
assign lcl_wr_rsp_ready = !s_axi_bvalid && s_axi_bready;
//=============================================================================================
// READ RESPONSE CHANNEL
//=============================================================================================
//---- AXI read response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
s_axi_rvalid <= 1'b0;
else if(lcl_rd_data_valid && lcl_rd_data_ready)
s_axi_rvalid <= 1'b1;
else if(s_axi_rready)
s_axi_rvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n) begin
s_axi_rid <= 0;
s_axi_ruser <= 0;
s_axi_rresp <= AXI_OKAY;
s_axi_rdata <= 1024'h0;
s_axi_rlast <= 1'b0;
end
//RDATA must remain stable when RVALID is asserted and RREADY low
else if(lcl_rd_data_valid && lcl_rd_data_ready) begin
s_axi_rid <= lcl_rd_data_axi_id;
s_axi_ruser <= lcl_rd_data_ctx;
s_axi_rresp <= lcl_rd_rsp_code;
s_axi_rdata <= lcl_rd_data;
s_axi_rlast <= lcl_rd_data_last;
end
assign lcl_rd_data_ready = !s_axi_rvalid || s_axi_rready;
endmodule |
module mmio_wrapper (
input clk_tlx ,
input clk_afu ,
input rst_n ,
//---- configuration ------------------------------------
input [63:0] cfg_f1_mmio_bar0 ,
input [63:0] cfg_f1_mmio_bar0_mask ,
//---- local information input --------------------------
output debug_cnt_clear ,
input [63:0] debug_tlx_cnt_cmd ,
input [63:0] debug_tlx_cnt_rsp ,
input [63:0] debug_tlx_cnt_retry ,
input [63:0] debug_tlx_cnt_fail ,
input [63:0] debug_tlx_cnt_xlt_pd ,
input [63:0] debug_tlx_cnt_xlt_done ,
input [63:0] debug_tlx_cnt_xlt_retry ,
input [63:0] debug_axi_cnt_cmd ,
input [63:0] debug_axi_cnt_rsp ,
input [63:0] debug_buf_cnt ,
input [63:0] debug_traffic_idle ,
output [63:0] debug_tlx_idle_lim ,
output [63:0] debug_axi_idle_lim ,
//---- FIR ----------------------------------------------
input [63:0] fir_fifo_overflow ,
input [63:0] fir_tlx_interface ,
//---- local control output -----------------------------
output soft_reset_brdg_odma ,
output soft_reset_action ,
//---- TL CAPP command ----------------------------------
input tlx_afu_cmd_valid ,
input [7:0] tlx_afu_cmd_opcode ,
input [15:0] tlx_afu_cmd_capptag ,
input [1:0] tlx_afu_cmd_dl ,
input [2:0] tlx_afu_cmd_pl ,
input [63:0] tlx_afu_cmd_be , // not supported
input tlx_afu_cmd_end , // not supported
input [63:0] tlx_afu_cmd_pa ,
input [3:0] tlx_afu_cmd_flag , // not supported
input tlx_afu_cmd_os , // not supported
output afu_tlx_cmd_credit ,
output [6:0] afu_tlx_cmd_initial_credit ,
output afu_tlx_cmd_rd_req ,
output [2:0] afu_tlx_cmd_rd_cnt ,
input tlx_afu_cmd_data_valid ,
input tlx_afu_cmd_data_bdi ,
input [511:0] tlx_afu_cmd_data_bus ,
//---- TL CAPP response ---------------------------------
output afu_tlx_resp_valid ,
output [7:0] afu_tlx_resp_opcode ,
output [1:0] afu_tlx_resp_dl ,
output [15:0] afu_tlx_resp_capptag ,
output [1:0] afu_tlx_resp_dp ,
output [3:0] afu_tlx_resp_code ,
output afu_tlx_rdata_valid ,
output afu_tlx_rdata_bdi ,
output [511:0] afu_tlx_rdata_bus ,
input tlx_afu_resp_credit ,
input tlx_afu_resp_data_credit ,
input [3:0] tlx_afu_resp_initial_credit ,
input [5:0] tlx_afu_resp_data_initial_credit ,
//---- master side AXI Lite bus ----
// AXI write address channel
input m_axi_awready ,
output [31:0] m_axi_awaddr ,
output [02:0] m_axi_awprot , // not supported
output m_axi_awvalid ,
// axi write data channel
input m_axi_wready ,
output [31:0] m_axi_wdata ,
output [03:0] m_axi_wstrb , // not supported
output m_axi_wvalid ,
// AXI response channel
input [01:0] m_axi_bresp ,
input m_axi_bvalid ,
output m_axi_bready ,
// AXI read address channel
input m_axi_arready ,
output m_axi_arvalid ,
output [31:0] m_axi_araddr ,
output [02:0] m_axi_arprot , // not supported
// AXI read data channel
input [31:0] m_axi_rdata ,
input [01:0] m_axi_rresp ,
output m_axi_rready ,
input m_axi_rvalid
);
wire mmio_wr ;
wire mmio_rd ;
wire mmio_dw ;
wire [31:0] mmio_addr ;
wire [63:0] mmio_din ;
wire [63:0] mmio_dout ;
wire mmio_done ;
wire mmio_failed;
wire lcl_wr ;
wire lcl_rd ;
wire [31:0] lcl_addr ;
wire [31:0] lcl_din ;
wire lcl_ack ;
wire lcl_rsp ;
wire [31:0] lcl_dout ;
wire lcl_dv ;
//---- TLX and MMIO local convertion ----
tlx_mmio_converter mtlx_mmio_converter (
.clk_tlx (clk_tlx ),
.clk_afu (clk_afu ),
.rst_n (rst_n ),
.cfg_f1_mmio_bar0 (cfg_f1_mmio_bar0 ),
.cfg_f1_mmio_bar0_mask (cfg_f1_mmio_bar0_mask ),
.tlx_afu_cmd_valid (tlx_afu_cmd_valid ),
.tlx_afu_cmd_opcode (tlx_afu_cmd_opcode ),
.tlx_afu_cmd_capptag (tlx_afu_cmd_capptag ),
.tlx_afu_cmd_dl (tlx_afu_cmd_dl ),
.tlx_afu_cmd_pl (tlx_afu_cmd_pl ),
.tlx_afu_cmd_be (tlx_afu_cmd_be ), // not supported
.tlx_afu_cmd_end (tlx_afu_cmd_end ), // not supported
.tlx_afu_cmd_pa (tlx_afu_cmd_pa ),
.tlx_afu_cmd_flag (tlx_afu_cmd_flag ), // not supported
.tlx_afu_cmd_os (tlx_afu_cmd_os ), // not supported
.afu_tlx_cmd_credit (afu_tlx_cmd_credit ),
.afu_tlx_cmd_initial_credit (afu_tlx_cmd_initial_credit ),
.afu_tlx_cmd_rd_req (afu_tlx_cmd_rd_req ),
.afu_tlx_cmd_rd_cnt (afu_tlx_cmd_rd_cnt ),
.tlx_afu_cmd_data_valid (tlx_afu_cmd_data_valid ),
.tlx_afu_cmd_data_bdi (tlx_afu_cmd_data_bdi ),
.tlx_afu_cmd_data_bus (tlx_afu_cmd_data_bus ),
.afu_tlx_resp_valid (afu_tlx_resp_valid ),
.afu_tlx_resp_opcode (afu_tlx_resp_opcode ),
.afu_tlx_resp_dl (afu_tlx_resp_dl ),
.afu_tlx_resp_capptag (afu_tlx_resp_capptag ),
.afu_tlx_resp_dp (afu_tlx_resp_dp ),
.afu_tlx_resp_code (afu_tlx_resp_code ),
.afu_tlx_rdata_valid (afu_tlx_rdata_valid ),
.afu_tlx_rdata_bdi (afu_tlx_rdata_bdi ),
.afu_tlx_rdata_bus (afu_tlx_rdata_bus ),
.tlx_afu_resp_credit (tlx_afu_resp_credit ),
.tlx_afu_resp_data_credit (tlx_afu_resp_data_credit ),
.tlx_afu_resp_initial_credit (tlx_afu_resp_initial_credit ),
.tlx_afu_resp_data_initial_credit (tlx_afu_resp_data_initial_credit),
.mmio_wr (mmio_wr ),
.mmio_rd (mmio_rd ),
.mmio_dw (mmio_dw ),
.mmio_addr (mmio_addr ),
.mmio_din (mmio_din ),
.mmio_dout (mmio_dout ),
.mmio_done (mmio_done ),
.mmio_failed (mmio_failed )
);
//---- route TLX access to local SNAP registers or action register space ----
mmio mmmio (
.clk (clk_afu ),
.rst_n (rst_n ),
.debug_cnt_clear (debug_cnt_clear ),
.debug_tlx_cnt_cmd (debug_tlx_cnt_cmd ),
.debug_tlx_cnt_rsp (debug_tlx_cnt_rsp ),
.debug_tlx_cnt_retry (debug_tlx_cnt_retry ),
.debug_tlx_cnt_fail (debug_tlx_cnt_fail ),
.debug_tlx_cnt_xlt_pd (debug_tlx_cnt_xlt_pd ),
.debug_tlx_cnt_xlt_done (debug_tlx_cnt_xlt_done ),
.debug_tlx_cnt_xlt_retry (debug_tlx_cnt_xlt_retry ),
.debug_axi_cnt_cmd (debug_axi_cnt_cmd ),
.debug_axi_cnt_rsp (debug_axi_cnt_rsp ),
.debug_buf_cnt (debug_buf_cnt ),
.debug_traffic_idle (debug_traffic_idle ),
.debug_tlx_idle_lim (debug_tlx_idle_lim ),
.debug_axi_idle_lim (debug_axi_idle_lim ),
.fir_fifo_overflow (fir_fifo_overflow ),
.fir_tlx_interface (fir_tlx_interface ),
.soft_reset_brdg_odma (soft_reset_brdg_odma ),
.soft_reset_action (soft_reset_action ),
.mmio_wr (mmio_wr ),
.mmio_rd (mmio_rd ),
.mmio_dw (mmio_dw ),
.mmio_addr (mmio_addr ),
.mmio_din (mmio_din ),
.mmio_dout (mmio_dout ),
.mmio_done (mmio_done ),
.mmio_failed (mmio_failed ),
.lcl_wr (lcl_wr ),
.lcl_rd (lcl_rd ),
.lcl_addr (lcl_addr ),
.lcl_din (lcl_din ),
.lcl_ack (lcl_ack ),
.lcl_rsp (lcl_rsp ),
.lcl_dout (lcl_dout ),
.lcl_dv (lcl_dv )
);
//---- AXI lite interface to action as master ----
axi_lite_master maxi_lite_master (
.clk (clk_afu ),
.rst_n (rst_n ),
.m_axi_awready (m_axi_awready),
.m_axi_awaddr (m_axi_awaddr ),
.m_axi_awprot (m_axi_awprot ), // not supported
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wready (m_axi_wready ),
.m_axi_wdata (m_axi_wdata ),
.m_axi_wstrb (m_axi_wstrb ), // not supported
.m_axi_wvalid (m_axi_wvalid ),
.m_axi_bresp (m_axi_bresp ),
.m_axi_bvalid (m_axi_bvalid ),
.m_axi_bready (m_axi_bready ),
.m_axi_arready (m_axi_arready),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_araddr (m_axi_araddr ),
.m_axi_arprot (m_axi_arprot ), // not supported
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rready (m_axi_rready ),
.m_axi_rvalid (m_axi_rvalid ),
.lcl_wr (lcl_wr ), // write enable
.lcl_rd (lcl_rd ), // read enable
.lcl_addr (lcl_addr ), // write/read address
.lcl_din (lcl_din ), // write data
.lcl_ack (lcl_ack ), // write data acknowledgement
.lcl_rsp (lcl_rsp ), // write/read response: 0: good; 1: bad
.lcl_dout (lcl_dout ), // read data
.lcl_dv (lcl_dv ) // read data valid
);
endmodule |
module tlx_mmio_converter (
input clk_tlx ,
input clk_afu ,
input rst_n ,
//---- configuration ------------------------------------
input [63:0] cfg_f1_mmio_bar0 ,
input [63:0] cfg_f1_mmio_bar0_mask ,
//---- TL CAPP command ----------------------------------
input tlx_afu_cmd_valid ,
input [7:0] tlx_afu_cmd_opcode ,
input [15:0] tlx_afu_cmd_capptag ,
input [1:0] tlx_afu_cmd_dl ,
input [2:0] tlx_afu_cmd_pl ,
input [63:0] tlx_afu_cmd_be , // not supported
input tlx_afu_cmd_end , // not supported
input [63:0] tlx_afu_cmd_pa ,
input [3:0] tlx_afu_cmd_flag , // not supported
input tlx_afu_cmd_os , // not supported
output afu_tlx_cmd_credit ,
output [6:0] afu_tlx_cmd_initial_credit ,
output reg afu_tlx_cmd_rd_req ,
output [2:0] afu_tlx_cmd_rd_cnt ,
input tlx_afu_cmd_data_valid ,
input tlx_afu_cmd_data_bdi ,
input [511:0] tlx_afu_cmd_data_bus ,
//---- TL CAPP response ---------------------------------
output reg afu_tlx_resp_valid ,
output reg [7:0] afu_tlx_resp_opcode ,
output [1:0] afu_tlx_resp_dl ,
output [15:0] afu_tlx_resp_capptag ,
output [1:0] afu_tlx_resp_dp ,
output reg [3:0] afu_tlx_resp_code ,
output afu_tlx_rdata_valid ,
output afu_tlx_rdata_bdi ,
output reg [511:0] afu_tlx_rdata_bus ,
input tlx_afu_resp_credit ,
input tlx_afu_resp_data_credit ,
input [3:0] tlx_afu_resp_initial_credit ,
input [5:0] tlx_afu_resp_data_initial_credit ,
//---- MMIO side interface ------------------------------
output mmio_wr ,
output mmio_rd ,
output mmio_dw ,
output [31:0] mmio_addr ,
output [63:0] mmio_din ,
input [63:0] mmio_dout ,
input mmio_done ,
input mmio_failed
);
reg [07:00] cmd_opcode;
reg [15:00] cmd_capptag;
reg [01:00] cmd_dl;
reg [02:00] cmd_pl;
reg [63:00] cmd_addr;
wire cmd_wr;
wire cmd_rd;
wire cmd_dw;
reg cmd_valid;
reg cmd_data_valid;
reg [63:00] cmd_data;
reg cmd_data_bdi;
wire address_in_bar0;
wire address_aligned;
wire cmd_is_granted;
wire cmd_event;
wire cmd_incident;
reg cmd_req;
reg cmd_ack;
reg [02:00] cmd_ack_pipe;
reg cmd_done;
reg rsp_ack;
reg rsp_req;
reg [01:00] rsp_req_pipe;
reg [63:00] rsp_data;
reg rsp_pending;
wire rsp_valid;
reg rsp_failed;
reg [01:00] rsp_failed_pipe;
reg [03:00] rsp_credit_cnt;
reg [05:00] rsp_data_credit_cnt;
reg rsp_credit_run_out;
reg cmd_req_afu;
reg [01:00] cmd_req_afu_pipe;
reg cmd_wr_afu;
reg [01:00] cmd_wr_afu_pipe;
reg cmd_rd_afu;
reg [01:00] cmd_rd_afu_pipe;
reg cmd_dw_afu;
reg [01:00] cmd_dw_afu_pipe;
reg [63:00] cmd_data_afu;
reg [31:00] cmd_addr_afu;
reg cmd_ack_afu;
reg rsp_req_afu;
reg rsp_failed_afu;
reg rsp_ack_afu;
reg [02:00] rsp_ack_afu_pipe;
reg [63:00] rsp_data_afu;
// TL CAPP command opcode
localparam [7:0] TLX_AFU_CMD_OPCODE_RETURN_ADR_TAG = 8'b00011001; // Return Address Tag
localparam [7:0] TLX_AFU_CMD_OPCODE_RD_MEM = 8'b00100000; // Read Memory
localparam [7:0] TLX_AFU_CMD_OPCODE_PR_RD_MEM = 8'b00101000; // Partial Memory Read
localparam [7:0] TLX_AFU_CMD_OPCODE_AMO_RD = 8'b00110000; // Atomic Memory Operation - Read
localparam [7:0] TLX_AFU_CMD_OPCODE_AMO_RW = 8'b00111000; // Atomic Memory Operation - Read Write
localparam [7:0] TLX_AFU_CMD_OPCODE_AMO_W = 8'b01000000; // Atomic Memory Operation - Write
localparam [7:0] TLX_AFU_CMD_OPCODE_WRITE_MEM = 8'b10000001; // Write Memory
localparam [7:0] TLX_AFU_CMD_OPCODE_WRITE_MEM_BE = 8'b10000010; // Byte Enable Memory Write
localparam [7:0] TLX_AFU_CMD_OPCODE_PR_WR_MEM = 8'b10000110; // Partial Cache Line Memory Write
localparam [7:0] TLX_AFU_CMD_OPCODE_FORCE_EVICT = 8'b11010000; // Force Eviction
localparam [7:0] TLX_AFU_CMD_OPCODE_WAKE_AFU_THREAD = 8'b11011111; // Wake AFU Thread
localparam [7:0] TLX_AFU_CMD_OPCODE_CONFIG_READ = 8'b11100000; // Configuration Read
localparam [7:0] TLX_AFU_CMD_OPCODE_CONFIG_WRITE = 8'b11100001; // Configuration Write
// TLX AP response opcode
localparam [7:0] AFU_TLX_RESP_OPCODE_NOP = 8'b00000000; // Nop
localparam [7:0] AFU_TLX_RESP_OPCODE_MEM_RD_RESPONSE = 8'b00000001; // Memory Read Response
localparam [7:0] AFU_TLX_RESP_OPCODE_MEM_RD_FAIL = 8'b00000010; // Memory Read Failure
localparam [7:0] AFU_TLX_RESP_OPCODE_MEM_WR_RESPONSE = 8'b00000100; // Memory Write Response
localparam [7:0] AFU_TLX_RESP_OPCODE_MEM_WR_FAIL = 8'b00000101; // Memory Write Failure
localparam [7:0] AFU_TLX_RESP_OPCODE_RETURN_TL_CREDITS = 8'b00001000; // Return TL Credits
localparam [7:0] AFU_TLX_RESP_OPCODE_WAKE_AFU_RESP = 8'b00001010; // Wake AFU Thread Response
// TLX AP response code
localparam [3:0] AFU_TLX_RESP_CODE_NULL = 4'b0000; // Nop
localparam [3:0] AFU_TLX_RESP_CODE_RTY_REQ = 4'b0010; // Retry request
localparam [3:0] AFU_TLX_RESP_CODE_DERROR = 4'b1000; // Data error
localparam [3:0] AFU_TLX_RESP_CODE_UOL = 4'b1001; // Unsupported operand length
localparam [3:0] AFU_TLX_RESP_CODE_BAD_ADDR = 4'b1011; // Bad address specification
localparam [3:0] AFU_TLX_RESP_CODE_FAILED = 4'b1110; // The operation has failed and cannot be recovered
//=================================================================================================================
// TLX TIME DOMAIN
// Command
//=================================================================================================================
//---- latch command info at the start ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
cmd_opcode <= 8'd0;
cmd_capptag <= 16'd0;
cmd_dl <= 2'd0;
cmd_pl <= 3'd0;
cmd_addr <= 64'd0;
end
else if(tlx_afu_cmd_valid)
begin
cmd_opcode <= tlx_afu_cmd_opcode;
cmd_capptag <= tlx_afu_cmd_capptag;
cmd_dl <= tlx_afu_cmd_dl;
cmd_pl <= tlx_afu_cmd_pl;
cmd_addr <= tlx_afu_cmd_pa;
end
assign cmd_wr = (cmd_opcode == TLX_AFU_CMD_OPCODE_PR_WR_MEM);
assign cmd_rd = (cmd_opcode == TLX_AFU_CMD_OPCODE_PR_RD_MEM);
assign cmd_dw = (cmd_pl == 3'b011);
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
cmd_valid <= 1'b0;
cmd_data_valid <= 1'b0;
end
else
begin
cmd_valid <= tlx_afu_cmd_valid;
cmd_data_valid <= tlx_afu_cmd_data_valid;
end
//---- latch command data at the start ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
cmd_data <= 64'd0;
cmd_data_bdi <= 1'b0;
end
else if(tlx_afu_cmd_data_valid)
begin
case(cmd_addr[5:3])
3'b111 : cmd_data <= tlx_afu_cmd_data_bus[511:448];
3'b110 : cmd_data <= tlx_afu_cmd_data_bus[447:384];
3'b101 : cmd_data <= tlx_afu_cmd_data_bus[383:320];
3'b100 : cmd_data <= tlx_afu_cmd_data_bus[319:256];
3'b011 : cmd_data <= tlx_afu_cmd_data_bus[255:192];
3'b010 : cmd_data <= tlx_afu_cmd_data_bus[191:128];
3'b001 : cmd_data <= tlx_afu_cmd_data_bus[127:064];
3'b000 : cmd_data <= tlx_afu_cmd_data_bus[063:000];
endcase
cmd_data_bdi <= tlx_afu_cmd_data_bdi;
end
//---- command address shall match BAR0 ----
assign address_in_bar0 = ((cmd_addr & cfg_f1_mmio_bar0_mask) == cfg_f1_mmio_bar0);
//---- command address shall be 4B or 8B aligned ----
assign address_aligned = (((cmd_pl == 3'b010) && (cmd_addr [1:0] == 2'b00)) || //4B aligned
((cmd_pl == 3'b011) && (cmd_addr [2:0] == 3'b000))); //8B aligned
//---- commmand is permitted for MMIO access when 1. BAR0 matched; 2. address aligned with 4B or 8B ----
assign cmd_is_granted = address_in_bar0 && address_aligned;
//---- generate command event to trigger MMIO access when 1. command is granted; 2. command data is not corrupted (write only) ----
assign cmd_event = ((cmd_data_valid && ~cmd_data_bdi) || (cmd_valid && cmd_rd)) && cmd_is_granted;
//---- indicate invalid command incident when 1. command is not granted; 2. command data is corrupted even if command is granted (write only) ----
assign cmd_incident = (cmd_data_valid && cmd_data_bdi && cmd_is_granted) || (cmd_valid && ~cmd_is_granted);
//------------------------------------------------------------------------------
// command event time domain crossing handshake
// _
// cmd_event _/ \__________ :
// ______________:_ TLX domain
// cmd_req ___/ : \__
// ............................................................
// _______:__________ AFU
// cmd_req_afu ________/ : \__ domain
// __:_________________ dual-FF
// cmd_ack_afu _____________/ : \__ sync
// _____
// mmio_wr/rd __________________/ \________ MMIO access
// ............................................................
// :_
// cmd_ack __________________/ \__________ TLX domain dual-FF sync
//
//------------------------------------------------------------------------------
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_req <= 1'b0;
else if(cmd_event)
cmd_req <= 1'b1;
else if(cmd_ack)
cmd_req <= 1'b0;
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
{ cmd_ack_pipe } <= 3'd0;
end
else
begin
{ cmd_ack_pipe } <= { cmd_ack_pipe , cmd_ack_afu };
end
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_ack <= 1'b0;
else
cmd_ack <= (~cmd_ack_pipe[2] && cmd_ack_pipe[1]);
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
cmd_done <= 1'b0;
else
cmd_done <= cmd_req && cmd_ack;
//---- request command data immediately after command valid, one 64B each time ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
afu_tlx_cmd_rd_req <= 1'b0;
else
afu_tlx_cmd_rd_req <= tlx_afu_cmd_valid && (tlx_afu_cmd_opcode == TLX_AFU_CMD_OPCODE_PR_WR_MEM);
assign afu_tlx_cmd_rd_cnt[2:0] = 3'b001; // Supports 4B or 8B only from partial write (Request 64B for partial)
//---- command credit ----
assign afu_tlx_cmd_initial_credit = 7'd1;
assign afu_tlx_cmd_credit = afu_tlx_resp_valid;
//=================================================================================================================
// TLX TIME DOMAIN
// Response
//=================================================================================================================
assign afu_tlx_resp_dl = 2'b01; // forced 64B for partial commands
assign afu_tlx_resp_dp = 2'b00; // forced for partial commands
assign afu_tlx_resp_capptag = cmd_capptag; // reflect command tag
assign afu_tlx_rdata_valid = afu_tlx_resp_valid && cmd_rd && (afu_tlx_resp_opcode == AFU_TLX_RESP_OPCODE_MEM_RD_RESPONSE);
assign afu_tlx_rdata_bdi = 1'b0;
//---- response request pipeline, acknowledge and data ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
{ rsp_ack, rsp_req , rsp_req_pipe } <= 4'd0;
{ rsp_failed , rsp_failed_pipe } <= 3'd0;
rsp_data <= 64'd0;
end
else
begin
{ rsp_ack, rsp_req , rsp_req_pipe } <= { rsp_req, rsp_req_pipe , rsp_req_afu };
{ rsp_failed , rsp_failed_pipe } <= { rsp_failed_pipe , rsp_failed_afu };
rsp_data <= rsp_data_afu;
end
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_pending <= 1'b0;
else if(~rsp_ack && rsp_req)
rsp_pending <= 1'b1;
else if(~rsp_credit_run_out)
rsp_pending <= 1'b0;
assign rsp_valid = rsp_pending && ~rsp_credit_run_out;
//---- assert response valid when command not viable or response returned from MMIO ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
afu_tlx_resp_valid <= 1'b0;
else
afu_tlx_resp_valid <= cmd_incident || rsp_valid;
//---- return response opcode and code ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
begin
afu_tlx_resp_opcode <= AFU_TLX_RESP_OPCODE_NOP;
afu_tlx_resp_code <= AFU_TLX_RESP_CODE_NULL;
end
else if(~cmd_is_granted) // when command information not viable for MMIO access
begin
afu_tlx_resp_opcode <= (cmd_wr)? AFU_TLX_RESP_OPCODE_MEM_WR_FAIL : AFU_TLX_RESP_OPCODE_MEM_RD_FAIL;
afu_tlx_resp_code <= AFU_TLX_RESP_CODE_BAD_ADDR;
end
else if(cmd_data_bdi) // when command data corrupted
begin
afu_tlx_resp_opcode <= AFU_TLX_RESP_OPCODE_MEM_WR_FAIL;
afu_tlx_resp_code <= AFU_TLX_RESP_CODE_DERROR;
end
else if(rsp_failed) // when MMIO read/write failed
begin
afu_tlx_resp_opcode <= (cmd_wr)? AFU_TLX_RESP_OPCODE_MEM_WR_FAIL : AFU_TLX_RESP_OPCODE_MEM_RD_FAIL;
afu_tlx_resp_code <= AFU_TLX_RESP_CODE_FAILED;
end
else // otherwise MMIO read/write done
begin
afu_tlx_resp_opcode <= (cmd_wr)? AFU_TLX_RESP_OPCODE_MEM_WR_RESPONSE : AFU_TLX_RESP_OPCODE_MEM_RD_RESPONSE;
afu_tlx_resp_code <= AFU_TLX_RESP_CODE_NULL;
end
//---- response data ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
afu_tlx_rdata_bus <= 512'd0;
else
case(cmd_addr[5:3])
3'b000: afu_tlx_rdata_bus <= {448'h0, rsp_data_afu[63:0]};
3'b001: afu_tlx_rdata_bus <= {384'h0, rsp_data_afu[63:0], 64'h0};
3'b010: afu_tlx_rdata_bus <= {320'h0, rsp_data_afu[63:0], 128'h0};
3'b011: afu_tlx_rdata_bus <= {256'h0, rsp_data_afu[63:0], 192'h0};
3'b100: afu_tlx_rdata_bus <= {192'h0, rsp_data_afu[63:0], 256'h0};
3'b101: afu_tlx_rdata_bus <= {128'h0, rsp_data_afu[63:0], 320'h0};
3'b110: afu_tlx_rdata_bus <= {064'h0, rsp_data_afu[63:0], 384'h0};
3'b111: afu_tlx_rdata_bus <= {rsp_data_afu[63:0], 448'h0};
endcase
//---- credit management ----
always@(posedge clk_tlx)
if(~rst_n)
rsp_credit_cnt <= tlx_afu_resp_initial_credit; // this should be set through soft resetting
else
case({tlx_afu_resp_credit, afu_tlx_resp_valid})
2'b10 : rsp_credit_cnt <= rsp_credit_cnt + 4'd1;
2'b01 : rsp_credit_cnt <= rsp_credit_cnt - 4'd1;
default:;
endcase
always@(posedge clk_tlx)
if(~rst_n)
rsp_data_credit_cnt <= tlx_afu_resp_data_initial_credit;
else
case({tlx_afu_resp_data_credit, afu_tlx_rdata_valid})
2'b10 : rsp_data_credit_cnt <= rsp_data_credit_cnt + 6'd1;
2'b01 : rsp_data_credit_cnt <= rsp_data_credit_cnt - 6'd1;
default:;
endcase
//---- credit deficiency alert ----
always@(posedge clk_tlx or negedge rst_n)
if(~rst_n)
rsp_credit_run_out <= 1'b0;
else
rsp_credit_run_out <= (rsp_credit_cnt == 4'd0) || (rsp_data_credit_cnt == 6'd0);
//=================================================================================================================
// AFU TIME DOMAIN
// Command
//=================================================================================================================
//---- command request pipeline, acknowledge, data and address ----
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
begin
{ cmd_req_afu , cmd_req_afu_pipe } <= 3'd0;
{ cmd_wr_afu , cmd_wr_afu_pipe } <= 3'd0;
{ cmd_rd_afu , cmd_rd_afu_pipe } <= 3'd0;
{ cmd_dw_afu , cmd_dw_afu_pipe } <= 3'd0;
cmd_data_afu <= 64'd0;
cmd_addr_afu <= 32'd0;
cmd_ack_afu <= 1'd0;
end
else
begin
{ cmd_req_afu , cmd_req_afu_pipe } <= { cmd_req_afu_pipe , cmd_req };
{ cmd_wr_afu , cmd_wr_afu_pipe } <= { cmd_wr_afu_pipe , cmd_wr };
{ cmd_rd_afu , cmd_rd_afu_pipe } <= { cmd_rd_afu_pipe , cmd_rd };
{ cmd_dw_afu , cmd_dw_afu_pipe } <= { cmd_dw_afu_pipe , cmd_dw };
cmd_data_afu <= cmd_data;
cmd_addr_afu <= cmd_addr;
cmd_ack_afu <= cmd_req_afu;
end
//---- MMIO access event generation ----
assign mmio_wr = ~cmd_ack_afu && cmd_req_afu && cmd_wr_afu;
assign mmio_rd = ~cmd_ack_afu && cmd_req_afu && cmd_rd_afu;
assign mmio_dw = ~cmd_ack_afu && cmd_req_afu && cmd_dw_afu;
assign mmio_din = cmd_data_afu;
assign mmio_addr = cmd_addr_afu;
//=================================================================================================================
// AFU TIME DOMAIN
// Response
//=================================================================================================================
//------------------------------------------------------------------------------
// response event time domain crossing handshake
// ____
// mmio_done/failed _/ \__________ : AFU domain
// ___________:____
// rsp_req_afu ___/ : \__
// .....................................:......................
// ________:__________ TLX
// rsp_req ______/ : \__ domain
// _______:____________ dual-FF
// rsp_ack _____________/ : \__ sync
// _ :
// rsp_valid __/ \___ :
// .....................................:......................
// :_____________________
// rsp_ack_afu __________________/ \_ AFU domain
//
//------------------------------------------------------------------------------
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
rsp_req_afu <= 1'b0;
else if(rsp_ack_afu)
rsp_req_afu <= 1'b0;
else if(mmio_done || mmio_failed)
rsp_req_afu <= 1'b1;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
rsp_failed_afu <= 1'b0;
else if(rsp_ack_afu)
rsp_failed_afu <= 1'b0;
else if(mmio_failed)
rsp_failed_afu <= 1'b1;
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
{ rsp_ack_afu_pipe } <= 3'd0;
else
{ rsp_ack_afu_pipe } <= { rsp_ack_afu_pipe , rsp_ack };
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
rsp_ack_afu <= 1'b0;
else
rsp_ack_afu <= (~rsp_ack_afu_pipe[2] && rsp_ack_afu_pipe[1]);
always@(posedge clk_afu or negedge rst_n)
if(~rst_n)
rsp_data_afu <= 64'd0;
else if(mmio_done)
rsp_data_afu <= mmio_dout;
endmodule |
module brdg_response_decode
#(
parameter MODE = 1'b1 //0: write; 1: read
)
(
input clk ,
input rst_n ,
//---- configuration --------------------------
input [0003:0] cfg_backoff_timer ,
//---- communication with command decoder -----
input prt_cmd_valid ,
input prt_cmd_last ,
output reg prt_cmd_enable ,
input prt_cmd_start ,
//---- DMA interface --------------------------
output reg dma_resp_valid ,
output reg [1023:0] dma_resp_data ,
output reg [`TAGW-1:0]dma_resp_tag ,
output reg [0001:0] dma_resp_pos ,
output reg [0002:0] dma_resp_code ,
//---- TLX interface --------------------------
input tlx_rsp_valid ,
input [0015:0] tlx_rsp_afutag ,
input [0007:0] tlx_rsp_opcode ,
input [0003:0] tlx_rsp_code ,
input [0001:0] tlx_rsp_dl ,
input [0001:0] tlx_rsp_dp ,
input tlx_rdata_o_dv ,
input tlx_rdata_e_dv ,
input tlx_rdata_o_bdi ,
input tlx_rdata_e_bdi ,
input [0511:0] tlx_rdata_o ,
input [0511:0] tlx_rdata_e ,
//---- control and status ---------------------
input debug_cnt_clear ,
output reg [0031:0] debug_tlx_cnt_rsp ,
output reg [0031:0] debug_tlx_cnt_retry ,
output reg [0031:0] debug_tlx_cnt_fail ,
output reg [0031:0] debug_tlx_cnt_xlt_pd ,
output reg [0031:0] debug_tlx_cnt_xlt_done ,
output reg [0031:0] debug_tlx_cnt_xlt_retry ,
output reg [0004:0] fir_fifo_overflow ,
output reg fir_tlx_response_unsupport
);
reg rsp_valid;
reg [0015:00] rsp_afutag;
reg [0007:00] rsp_opcode;
reg [0004:00] rsp_code;
reg [0001:00] rsp_dl;
reg [0001:00] rsp_dp;
wire[0017:00] rsp_type;
wire[0001:00] rsp_pos;
wire[`TAGW-1:00]rsp_tag;
wire response_wr_done;
wire response_wr_failed;
wire response_wr_xlate_pending;
wire response_wr_xlate_done;
wire response_wr_xlate_retry;
wire response_wr_retry;
wire response_rd_xlate_pending;
wire response_rd_done;
wire response_rd_failed;
wire response_rd_retry;
wire response_rd_xlate_done;
wire response_rd_xlate_retry;
wire response_write;
wire response_read;
wire response_done;
wire response_failed;
wire response_retry;
wire response_xlate_done;
wire response_xlate_pending;
wire response_xlate_retry;
wire response_partial;
wire response_partial_done;
wire response_partial_retry;
wire response_partial_failed;
wire response_partial_xlate_pending;
wire rsp_rd_partial;
wire rsp_good_valid;
wire rsp_good_full_valid;
wire rsp_bad_full_valid;
wire fifo_rsp_good_partial_dv;
wire fifo_rsp_good_full_dv;
wire fifo_rsp_bad_full_dv;
reg all_fifos_emptied;
reg [0511:00] tmp_partial_rd_data_o;
reg [0511:00] tmp_partial_rd_data_e;
wire[0004:00] rsp_rty_typ;
wire rty_rdy;
wire rty_valid;
wire[0001:00] rty_pos;
wire[`TAGW-1:00]rty_tag;
reg [0004:00] prt_inflight_cnt;
reg [0004:00] prt_data_cnt;
reg prt_commands_allout;
reg prt_responses_allin;
wire prt_rsp_empty_window;
wire prt_rsp_available;
wire prt_rsp_last;
wire prt_rsp_last_no_data;
wire prt_rsp_last_all_data;
wire prt_rsp_end;
reg [0007:00] prt_rsp_end_shift;
reg prt_rsp_pending;
reg prt_rsp_retry;
reg prt_rsp_done;
reg prt_rsp_failed;
reg rty_in_progress;
wire prt_valid;
wire end_of_partial_batch;
wire rty_busy;
reg [0003:00] prt_rsp_code;
reg [0001:00] prt_pos;
reg [0006:00] prt_tag;
wire[0009:00] fifo_rsp_good_din;
wire fifo_rsp_good_den;
wire fifo_rsp_good_rdrq;
wire fifo_rsp_good_dv;
wire[0009:00] fifo_rsp_good_dout;
wire fifo_rsp_good_empty;
wire fifo_rsp_good_ovfl;
reg [0512:00] fifo_rspdat_o_din;
reg fifo_rspdat_o_den;
wire fifo_rspdat_o_rdrq;
wire[0512:00] fifo_rspdat_o_dout;
wire fifo_rspdat_o_empty;
reg [0512:00] fifo_rspdat_e_din;
reg fifo_rspdat_e_den;
wire fifo_rspdat_e_rdrq;
wire[0512:00] fifo_rspdat_e_dout;
wire fifo_rspdat_e_empty;
wire fifo_rspdat_o_ovfl;
wire fifo_rspdat_e_ovfl;
wire[0008:00] fifo_rsp_bad_din;
wire fifo_rsp_bad_den;
wire fifo_rsp_bad_rdrq;
wire fifo_rsp_bad_dv;
wire fifo_rsp_bad_empty;
wire fifo_rsp_bad_ovfl;
wire[0008:00] fifo_rsp_bad_dout;
// TL CAPP response opcode
localparam [7:0] TLX_AFU_RESP_OPCODE_NOP = 8'b00000000; // -- Nop
localparam [7:0] TLX_AFU_RESP_OPCODE_RETURN_TLX_CREDITS = 8'b00000001; // -- Return TLX Credits
localparam [7:0] TLX_AFU_RESP_OPCODE_TOUCH_RESP = 8'b00000010; // -- Touch Response
localparam [7:0] TLX_AFU_RESP_OPCODE_READ_RESPONSE = 8'b00000100; // -- Read Response
localparam [7:0] TLX_AFU_RESP_OPCODE_UPGRADE_RESP = 8'b00000111; // -- Upgrade Response
localparam [7:0] TLX_AFU_RESP_OPCODE_READ_FAILED = 8'b00000101; // -- Read Failed
localparam [7:0] TLX_AFU_RESP_OPCODE_CL_RD_RESP = 8'b00000110; // -- Cachable Read Response
localparam [7:0] TLX_AFU_RESP_OPCODE_WRITE_RESPONSE = 8'b00001000; // -- Write Response
localparam [7:0] TLX_AFU_RESP_OPCODE_WRITE_FAILED = 8'b00001001; // -- Write Failed
localparam [7:0] TLX_AFU_RESP_OPCODE_MEM_FLUSH_DONE = 8'b00001010; // -- Memory Flush Done
localparam [7:0] TLX_AFU_RESP_OPCODE_INTRP_RESP = 8'b00001100; // -- Interrupt Response
localparam [7:0] TLX_AFU_RESP_OPCODE_WAKE_HOST_RESP = 8'b00010000; // -- Wake Host Thread Response
localparam [7:0] TLX_AFU_RESP_OPCODE_XLATE_DONE = 8'b00011000; // -- Address Translation Completed (Async Notification)
localparam [7:0] TLX_AFU_RESP_OPCODE_INTRP_RDY = 8'b00011010; // -- Interrupt ready (Async Notification)
// TL CAPP response code
localparam [3:0] TLX_AFU_RESP_CODE_DONE = 4'b0000;
localparam [3:0] TLX_AFU_RESP_CODE_RTY_HWT = 4'b0001;
localparam [3:0] TLX_AFU_RESP_CODE_RTY_REQ = 4'b0010;
localparam [3:0] TLX_AFU_RESP_CODE_XLATE_PENDING = 4'b0100;
localparam [3:0] TLX_AFU_RESP_CODE_INTRP_PENDING = 4'b0100;
localparam [3:0] TLX_AFU_RESP_CODE_DERROR = 4'b1000;
localparam [3:0] TLX_AFU_RESP_CODE_BAD_LENGTH = 4'b1001;
localparam [3:0] TLX_AFU_RESP_CODE_BAD_ADDR = 4'b1011;
localparam [3:0] TLX_AFU_RESP_CODE_FAILED = 4'b1110;
localparam [3:0] TLX_AFU_RESP_CODE_ADR_ERROR = 4'b1111;
// response code
parameter RESP_GOOD = 3'b001,
RESP_RETRY = 3'b010,
RESP_BAD = 3'b100;
//=================================================================================================================
//
// RESPONSE INFORMATION DECODE
//
// * response type : 16 bits
// bit16~8: read/write failures
// bit7: write retry request
// bit6: read retry request
// bit5: write xlate pending
// bit4: read xlate pending
// bit3: xlate and retry backoff request
// bit2: xlate and retry immediate request
// bit1: write done
// bit0: read done
//
// * response tag : 6 bits
// slot address
//
// * response pos : 2 bits
// bit1: higher 64B in slot
// bit0: lower 64B in slot
//
//=================================================================================================================
//---- latch signals once ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
rsp_valid <= 1'd0;
else
rsp_valid <= tlx_rsp_valid;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
rsp_afutag <= 16'd0;
rsp_opcode <= 8'd0;
rsp_code <= 4'd0;
rsp_dl <= 2'd0;
rsp_dp <= 2'd0;
end
else if(tlx_rsp_valid)
begin
rsp_afutag <= tlx_rsp_afutag;
rsp_opcode <= tlx_rsp_opcode;
rsp_code <= tlx_rsp_code;
rsp_dl <= tlx_rsp_dl;
rsp_dp <= tlx_rsp_dp;
end
// response type
assign rsp_type = {
/*bit17*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_BAD_LENGTH),
/*bit16*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_BAD_LENGTH),
/*bit15*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_ADR_ERROR),
/*bit14*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_ADR_ERROR),
/*bit13*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_DERROR),
/*bit12*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_DERROR),
/*bit11*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_BAD_ADDR),
/*bit10*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_BAD_ADDR),
/*bit09*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_FAILED),
/*bit08*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_FAILED),
/*bit07*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_RTY_REQ),
/*bit06*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_RTY_REQ),
/*bit05*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_XLATE_PENDING),
/*bit04*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_FAILED) && (rsp_code == TLX_AFU_RESP_CODE_XLATE_PENDING),
/*bit03*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_XLATE_DONE) && (rsp_code == TLX_AFU_RESP_CODE_RTY_REQ),
/*bit02*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_XLATE_DONE) && (rsp_code == TLX_AFU_RESP_CODE_DONE),
/*bit01*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_WRITE_RESPONSE),
/*bit00*/ (rsp_opcode == TLX_AFU_RESP_OPCODE_READ_RESPONSE)
};
// response data length and position:
// * full resp for 128B : 2'b11;
// * split resp for 128B: 2'b10 (dp=01) or 2'b01 (dp=00);
// * resp for 64B: afutag[7:6]
assign rsp_pos = (rsp_dl == 2'd2)? 2'b11 : ((rsp_afutag[8:7] == 2'b11)? ((rsp_dp[0])? 2'b10 : 2'b01) : (rsp_afutag[8:7]));
// tag
assign rsp_tag = rsp_afutag[6:0];
// decode responses
assign response_wr_done = rsp_type[1];
assign response_wr_failed = rsp_type[9] || rsp_type[11] || rsp_type[13] || rsp_type[15] || rsp_type[17];
assign response_wr_xlate_pending = rsp_type[5];
assign response_wr_xlate_done = rsp_type[2] && response_write;
assign response_wr_xlate_retry = rsp_type[3] && response_write;
assign response_wr_retry = rsp_type[7];
assign response_rd_xlate_pending = rsp_type[4];
assign response_rd_done = rsp_type[0];
assign response_rd_failed = rsp_type[8] || rsp_type[10] || rsp_type[12] || rsp_type[14] || rsp_type[16];
assign response_rd_retry = rsp_type[6];
assign response_rd_xlate_done = rsp_type[2] && response_read;
assign response_rd_xlate_retry = rsp_type[3] && response_read;
// distinguish read, write and partial write
assign response_write = ~rsp_afutag[15];
assign response_read = rsp_afutag[15];
// check mode
assign response_done = (MODE)? response_rd_done : response_wr_done;
assign response_failed = (MODE)? response_rd_failed : response_wr_failed;
assign response_retry = (MODE)? response_rd_retry : response_wr_retry;
assign response_xlate_done = (MODE)? response_rd_xlate_done : response_wr_xlate_done;
assign response_xlate_pending = (MODE)? response_rd_xlate_pending : response_wr_xlate_pending;
assign response_xlate_retry = (MODE)? response_rd_xlate_retry : response_wr_xlate_retry;
// partial
assign response_partial = rsp_afutag[14];
assign response_partial_done = response_partial && response_done;
assign response_partial_retry = response_partial && response_retry;
assign response_partial_xlate_pending = response_partial && response_xlate_pending;
assign response_partial_failed = response_partial && response_failed;
assign rsp_rd_partial = response_read && response_partial;
// response valid for good and bad responses
assign rsp_bad_full_valid = rsp_valid && ~response_partial && response_failed;
assign rsp_good_full_valid = rsp_valid && ~response_partial && response_done;
assign rsp_good_valid = rsp_valid && response_done;
//=================================================================================================================
//
// NORMAL RESPONSE FIFO SET (RO)
//
// read/write mode------------|
// V
// +--------+ +------------------------+ +--+
// | | ====> | FIFO for good rsp (RO) |====> |M |
// | | || +------------------------+ |U | +--+
// | | || +------------------------+ |X |===> |M |
// | | ====> | FIFO for bad rsp (RO) |====> | | |U | ==> data
// ==> | decode | || +------------------------+ | | |X | ==> tag
// | | ||=================================> | | | | ==> pos
// | | (bypass route, WO) +--+ | | ==> code (good/bad/retry)
// | | | |
// | | +-------------------+ | |
// | | ======> | retry queue |================> | |
// +--------+ +-------------------+ +--+
//
// * designed for alignment of good response and its corresponding read data.
// * good response FIFO (highest priority, read only, data driven out by valid read data)
// * bad response FIFO (2nd priority, read only)
// * retry queue (lowest priority for read)
//
//=================================================================================================================
generate
if (MODE) begin : ReadModeOnly
//---- FIFO to buffer information of good response ----
assign fifo_rsp_good_din = {rsp_rd_partial, rsp_pos, rsp_tag};
assign fifo_rsp_good_den = rsp_good_valid && (MODE);
fifo_sync #(
.DATA_WIDTH (10),
.ADDR_WIDTH (4),
.FWFT(0),
.DISTR(1)
) mfifo_rsp_good (
.clk (clk ),
.rst_n (rst_n ),
.din (fifo_rsp_good_din ),
.wr_en (fifo_rsp_good_den ),
.rd_en (fifo_rsp_good_rdrq ),
.valid (fifo_rsp_good_dv ),
.dout (fifo_rsp_good_dout ),
.overflow(fifo_rsp_good_ovfl ),
.empty (fifo_rsp_good_empty)
);
//---- FIFO to buffer data of good response ----
// ODD data and bdi
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fifo_rspdat_o_din <= 1024'd0;
fifo_rspdat_o_den <= 1'b0;
end
else
begin
fifo_rspdat_o_din <= {tlx_rdata_o_bdi,tlx_rdata_o};
fifo_rspdat_o_den <= tlx_rdata_o_dv;
end
fifo_sync #(
.DATA_WIDTH (513),
.ADDR_WIDTH (4),
.FWFT(0),
.DISTR(1)
) mfifo_rspdat_o (
.clk (clk ),
.rst_n (rst_n ),
.din (fifo_rspdat_o_din ),
.wr_en (fifo_rspdat_o_den ),
.rd_en (fifo_rspdat_o_rdrq ),
.dout (fifo_rspdat_o_dout ),
.overflow(fifo_rspdat_o_ovfl ),
.empty (fifo_rspdat_o_empty)
);
// EVEN data and bdi
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fifo_rspdat_e_din <= 1024'd0;
fifo_rspdat_e_den <= 1'b0;
end
else
begin
fifo_rspdat_e_din <= {tlx_rdata_e_bdi,tlx_rdata_e};
fifo_rspdat_e_den <= tlx_rdata_e_dv;
end
fifo_sync #(
.DATA_WIDTH (513),
.ADDR_WIDTH (4),
.FWFT(0),
.DISTR(1)
) mfifo_rspdat_e (
.clk (clk ),
.rst_n (rst_n ),
.din (fifo_rspdat_e_din ),
.wr_en (fifo_rspdat_e_den ),
.rd_en (fifo_rspdat_e_rdrq ),
.dout (fifo_rspdat_e_dout ),
.overflow(fifo_rspdat_e_ovfl ),
.empty (fifo_rspdat_e_empty)
);
//---- sync response info and even/odd data ----
wire fifo_tri_rsp_good_empty = fifo_rsp_good_empty || fifo_rspdat_o_empty || fifo_rspdat_e_empty;
reg fifo_rsp_good_rdrq_orig;
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rsp_good_rdrq_orig <= 1'b0;
else
fifo_rsp_good_rdrq_orig <= ~fifo_tri_rsp_good_empty;
assign fifo_rsp_good_rdrq = fifo_rsp_good_rdrq_orig && ~fifo_tri_rsp_good_empty;
assign fifo_rspdat_o_rdrq = fifo_rsp_good_rdrq_orig && ~fifo_tri_rsp_good_empty;
assign fifo_rspdat_e_rdrq = fifo_rsp_good_rdrq_orig && ~fifo_tri_rsp_good_empty;
//---- classify data FIFO output based on partial info ----
assign fifo_rsp_good_full_dv = (fifo_rsp_good_dv && ~fifo_rsp_good_dout[9]);
assign fifo_rsp_good_partial_dv = (fifo_rsp_good_dv && fifo_rsp_good_dout[9]);
//---- tmporary register for partial read data combination ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
tmp_partial_rd_data_o <= 512'd0;
else if(prt_rsp_available)
tmp_partial_rd_data_o <= 512'd0;
else if(fifo_rsp_good_partial_dv && ~fifo_rsp_good_dout[7])
tmp_partial_rd_data_o <= (tmp_partial_rd_data_o | fifo_rspdat_o_dout[511:0]);
always@(posedge clk or negedge rst_n)
if(~rst_n)
tmp_partial_rd_data_e <= 512'd0;
else if(prt_rsp_available)
tmp_partial_rd_data_e <= 512'd0;
else if(fifo_rsp_good_partial_dv && fifo_rsp_good_dout[7])
tmp_partial_rd_data_e <= (tmp_partial_rd_data_e | fifo_rspdat_e_dout[511:0]);
//---- FIFO to buffer information of bad response ----
assign fifo_rsp_bad_din = {rsp_pos, rsp_tag};
assign fifo_rsp_bad_den = rsp_bad_full_valid && (MODE);
fifo_sync #(
.DATA_WIDTH (9),
.ADDR_WIDTH (4),
.DISTR(1)
) mfifo_rsp_bad (
.clk (clk ),
.rst_n (rst_n ),
.din (fifo_rsp_bad_din ),
.wr_en (fifo_rsp_bad_den ),
.rd_en (fifo_rsp_bad_rdrq ),
.valid (fifo_rsp_bad_dv ),
.dout (fifo_rsp_bad_dout ),
.overflow(fifo_rsp_bad_ovfl ),
.empty (fifo_rsp_bad_empty)
);
assign fifo_rsp_bad_rdrq = ~fifo_rsp_bad_empty && ~fifo_rsp_good_rdrq;
assign fifo_rsp_bad_full_dv = fifo_rsp_bad_dv;
reg fifo_rsp_good_den_sync;
always@(posedge clk or negedge rst_n)
if(~rst_n)
fifo_rsp_good_den_sync <= 1'b0;
else
fifo_rsp_good_den_sync <= fifo_rsp_good_den;
always@(posedge clk or negedge rst_n)
if(~rst_n)
all_fifos_emptied <= 1'b1;
else if(fifo_rsp_good_den_sync)
all_fifos_emptied <= 1'b0;
else if(fifo_rsp_good_empty)
all_fifos_emptied <= 1'b1;
end
endgenerate
//=================================================================================================================
//
// RETRY QUEUE
//
// * manages responses of rty_req, xlate_pending and xlate_done, send out retry request in apt time
// * read out available retry data only when no other responses are in process.
//
//=================================================================================================================
//---- push xlate_pending, xlate_done and retry response into retry queue -----
assign rsp_rty_typ = {response_partial, response_retry, response_xlate_done, response_xlate_retry, response_xlate_pending};
wire rsp_valid_rty = rsp_valid;
wire fifo_retry_ovfl;
//---- retry queue that handles backoff countdown and xlate_pending/xlate_done matching ----
brdg_retry_queue mretry_queue (
.clk (clk ),
.rst_n (rst_n ),
.backoff_limit(cfg_backoff_timer),
.prt_cmd_start(prt_cmd_start ),
.rty_busy (rty_busy ),
.rsp_den (rsp_valid_rty ),
.rsp_pos (rsp_pos ),
.rsp_tag (rsp_tag ),
.rsp_typ (rsp_rty_typ ),
.rty_rdy (rty_rdy ),
.rty_valid (rty_valid ),
.rty_pos (rty_pos ),
.rty_tag (rty_tag ),
.overflow (fifo_retry_ovfl )
);
//---- let good or bad responsed processed first ----
assign rty_rdy = (MODE)? (~fifo_rsp_good_full_dv && ~fifo_rsp_bad_full_dv) : (~rsp_good_full_valid && ~rsp_bad_full_valid);
//=================================================================================================================
//
// Partial bookkeeper
//
// * increment counter when one partial command is sent.
// * decrement counter when one partial command is received.
// * partial commands pertinent to the same 64B are processed individually
// * acknowledge when all partial commands pertinent to the same 64B are responded.
// __
// prt_cmd_start __/ |_________________________________________________________________
// _____ ___________
// prt_cmd_enable |_____________________________________________________/
// __ __ __ __ __
// prt_cmd_valid ______/ |_______/ |_______/ |___/ |____/ |________________________
// __
// prt_cmd_last ___________________________________________/ |________________________
// __ __ __ __ __
// rsp_valid _____________/ |_______/ |_______/ |_________/ |____/ |___________
// __
// rsp_last ________________________________________________________/ |___________
// ________
// prt_rsp_pending __________________________________________________________/ |__
// __
// prt_rsp_available _____________________________________________________________/ |__
//
//=================================================================================================================
//---- inflight partial command counter ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_inflight_cnt <= 5'd0;
else
case({prt_cmd_valid, (response_partial && ~response_xlate_pending && rsp_valid)})
2'b10 : prt_inflight_cnt <= prt_inflight_cnt + 5'd1;
2'b01 : prt_inflight_cnt <= prt_inflight_cnt - 5'd1;
default:;
endcase
//---- valid partial response data counter, incrementing when valid response of partial is received, decrementing when valid data is popped ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_data_cnt <= 5'd0;
else if(MODE)
case({(response_partial_done && rsp_valid), fifo_rsp_good_partial_dv})
2'b10 : prt_data_cnt <= prt_data_cnt + 5'd1;
2'b01 : prt_data_cnt <= prt_data_cnt - 5'd1;
default:;
endcase
//---- indicate partial commands have all been sent ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_commands_allout <= 1'b0;
else if(prt_cmd_enable)
prt_commands_allout <= 1'b0;
else if(prt_cmd_last)
prt_commands_allout <= 1'b1;
//---- indicate all partial responses but not all data have all been received, for read mode only ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_responses_allin <= 1'b0;
else if(prt_rsp_end)
prt_responses_allin <= 1'b0;
else if(prt_rsp_last)
prt_responses_allin <= 1'b1;
//---- when no other non-partial responses or retry responses are committed to upstream interface ----
assign prt_rsp_empty_window = rty_rdy && ~rty_valid;
//---- all responses for partial commands have been back ----
assign prt_rsp_available = prt_rsp_pending && prt_rsp_empty_window;
//---- the last response pertaining to the partial commands batch ----
assign prt_rsp_last = response_partial && (prt_inflight_cnt == 5'd1) && prt_commands_allout && ~response_xlate_pending && rsp_valid;
//---- there's no valid data returned ----
assign prt_rsp_last_no_data = prt_rsp_last && ~prt_rsp_done && ~response_partial_done;
//---- the last response data for read mode ----
assign prt_rsp_last_all_data = (prt_data_cnt == 5'd0) && prt_rsp_done && prt_responses_allin;
//---- indicate the end of all partial responses for an individual batch ----
assign prt_rsp_end = (MODE)? (prt_rsp_last_no_data || prt_rsp_last_all_data) : prt_rsp_last;
//---- delay partial commands enabling to make safe distance between 2 partial batches ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_end_shift <= 8'd0;
else
prt_rsp_end_shift <= {prt_rsp_end_shift[6:0], prt_rsp_end};
//---- pending to acknowledge the last batch of partial commands ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_pending <= 1'b0;
else if(prt_rsp_end)
prt_rsp_pending <= 1'b1;
else if(prt_rsp_empty_window)
prt_rsp_pending <= 1'b0;
//---- indicate that at least one out of all responses is retry ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_retry <= 1'b0;
else if(prt_rsp_available)
prt_rsp_retry <= 1'b0;
else if((response_partial_retry || response_partial_xlate_pending) && rsp_valid)
prt_rsp_retry <= 1'b1;
//---- indicate that at least one out of all responses is done ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_done <= 1'b0;
else if(prt_rsp_available)
prt_rsp_done <= 1'b0;
else if(response_partial_done && rsp_valid)
prt_rsp_done <= 1'b1;
//---- indicate that at least one out of all responses is failed ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_failed <= 1'b0;
else if(prt_rsp_available)
prt_rsp_failed <= 1'b0;
else if(response_partial_failed && rsp_valid)
prt_rsp_failed <= 1'b1;
//---- partial response valid signal to upstream interface except for retry ----
// for write or read with bad resp, asserts partial valid to demonstrate the end of a partial commands batch, except when there's retry in it;
// for read with all good resp, asserts partial valid when the last response data is read out of FIFO
assign prt_valid = prt_rsp_available && ~prt_rsp_retry;
//---- just in case when there's still retry in FIFO which might be re-sent ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
rty_in_progress <= 1'b0;
else if(prt_rsp_end_shift[7])
rty_in_progress <= 1'b1;
else if(~rty_busy)
rty_in_progress <= 1'b0;
assign end_of_partial_batch = rty_in_progress && ~rty_busy;
//---- asserts to notify partial sequencer that all responses have been received ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_cmd_enable <= 1'b1;
else if(prt_cmd_start)
prt_cmd_enable <= 1'b0;
else if(end_of_partial_batch)
prt_cmd_enable <= 1'b1;
//---- overall partial commands response, being good only when all responses are good ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
prt_rsp_code <= RESP_GOOD;
else if(prt_rsp_available)
begin
if(prt_rsp_failed)
prt_rsp_code <= RESP_BAD;
else
prt_rsp_code <= RESP_GOOD;
end
//---- position and tag information for partial response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
prt_pos <= 2'd0;
prt_tag <= 7'd0;
end
else if(rsp_valid && response_partial)
begin
prt_pos <= rsp_pos;
prt_tag <= rsp_tag;
end
//=================================================================================================================
//
// MULTIPLEXER FOR RESPONSE OUT
//
// * read mode: good response > bad response > retry. good response is entitled with the highest priority because
// it's brought out by incoming response data, which is not buffered.
// * write mode: good/bad response is not buffered, and overrides retry response.
//
//=================================================================================================================
//---- read data, tag and pos ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
dma_resp_valid <= 1'b0;
dma_resp_data <= 1024'd0;
dma_resp_tag <= {`TAGW{1'b1}};
dma_resp_pos <= 2'd0;
end
else if(MODE)
begin
dma_resp_valid <= fifo_rsp_good_full_dv || fifo_rsp_bad_full_dv || rty_valid || prt_valid;
dma_resp_data <= (fifo_rsp_good_full_dv)?
{fifo_rspdat_o_dout[511:0], fifo_rspdat_e_dout[511:0]} :
{tmp_partial_rd_data_o, tmp_partial_rd_data_e};
dma_resp_tag <= (fifo_rsp_good_full_dv)?
fifo_rsp_good_dout[6:0] :
((fifo_rsp_bad_full_dv)? fifo_rsp_bad_dout[6:0] : (rty_valid? rty_tag : prt_tag));
dma_resp_pos <= (fifo_rsp_good_full_dv)?
fifo_rsp_good_dout[8:7] :
((fifo_rsp_bad_full_dv)? fifo_rsp_bad_dout[8:7] : (rty_valid? rty_pos : prt_pos));
end
else
begin
dma_resp_valid <= rsp_good_full_valid || rsp_bad_full_valid || rty_valid || prt_valid;
dma_resp_tag <= ((rsp_good_full_valid) || (rsp_bad_full_valid))? rsp_tag : (rty_valid? rty_tag : prt_tag);
dma_resp_pos <= ((rsp_good_full_valid) || (rsp_bad_full_valid))? rsp_pos : (rty_valid? rty_pos : prt_pos);
end
//---- reponse type: 3'b001: good; 3'b010: bad; 3'b100: retry ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
dma_resp_code <= 3'd0;
else if(MODE)
case({fifo_rsp_good_full_dv,fifo_rsp_bad_full_dv,rty_valid,prt_valid})
4'b1000 : dma_resp_code <= (fifo_rspdat_o_dout[512] || fifo_rspdat_e_dout[512])? RESP_BAD : RESP_GOOD;
4'b0100 : dma_resp_code <= RESP_BAD;
4'b0010 : dma_resp_code <= RESP_RETRY;
4'b0001 : dma_resp_code <= prt_rsp_code;
default:;
endcase
else
case({rsp_good_full_valid,rsp_bad_full_valid,rty_valid,prt_valid})
4'b1000 : dma_resp_code <= RESP_GOOD;
4'b0100 : dma_resp_code <= RESP_BAD;
4'b0010 : dma_resp_code <= RESP_RETRY;
4'b0001 : dma_resp_code <= prt_rsp_code;
default:;
endcase
//=================================================================================================================
// STATUS output for SNAP registers
//=================================================================================================================
//---- DEBUG registers ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
debug_tlx_cnt_rsp <= 32'b0;
debug_tlx_cnt_retry <= 32'b0;
debug_tlx_cnt_fail <= 32'b0;
debug_tlx_cnt_xlt_pd <= 32'b0;
debug_tlx_cnt_xlt_done <= 32'b0;
debug_tlx_cnt_xlt_retry <= 32'b0;
end
else if(debug_cnt_clear)
begin
debug_tlx_cnt_rsp <= 32'b0;
debug_tlx_cnt_retry <= 32'b0;
debug_tlx_cnt_fail <= 32'b0;
debug_tlx_cnt_xlt_pd <= 32'b0;
debug_tlx_cnt_xlt_done <= 32'b0;
debug_tlx_cnt_xlt_retry <= 32'b0;
end
else if(rsp_valid)
begin
if(~response_xlate_pending)
debug_tlx_cnt_rsp <= debug_tlx_cnt_rsp + 32'b1; // xlate pending doesn't count
if(response_retry)
debug_tlx_cnt_retry <= debug_tlx_cnt_retry + 32'b1;
if(response_failed)
debug_tlx_cnt_fail <= debug_tlx_cnt_fail + 32'b1;
if(response_xlate_pending)
debug_tlx_cnt_xlt_pd <= debug_tlx_cnt_xlt_pd + 32'b1;
if(response_xlate_done)
debug_tlx_cnt_xlt_done <= debug_tlx_cnt_xlt_done + 32'b1;
if(response_xlate_retry)
debug_tlx_cnt_xlt_retry <= debug_tlx_cnt_xlt_retry + 32'b1;
end
//---- FAULT ISOLATION REGISTER ----
reg [0003:0] fir_fifo_rsp_good_overflow;
reg fir_fifo_rsp_bad_overflow ;
reg fir_fifo_rspdat_o_overflow;
reg fir_fifo_rspdat_e_overflow;
reg fir_fifo_retry_overflow;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
fir_fifo_rsp_good_overflow <= 1'b0;
fir_fifo_rsp_bad_overflow <= 1'b0;
fir_fifo_rspdat_o_overflow <= 1'b0;
fir_fifo_rspdat_e_overflow <= 1'b0;
fir_fifo_retry_overflow <= 1'b0;
fir_tlx_response_unsupport <= 1'b0;
fir_fifo_overflow <= 5'd0;
end
else
begin
if (fifo_rsp_good_ovfl) fir_fifo_rsp_good_overflow <= 1'b1;
if (fifo_rsp_bad_ovfl) fir_fifo_rsp_bad_overflow <= 1'b1;
if (fifo_rspdat_o_ovfl) fir_fifo_rspdat_o_overflow <= 1'b1;
if (fifo_rspdat_e_ovfl) fir_fifo_rspdat_e_overflow <= 1'b1;
if (fifo_retry_ovfl) fir_fifo_retry_overflow <= 1'b1;
if (rsp_valid && (rsp_type == 16'd0)) fir_tlx_response_unsupport <= 1'b1;
fir_fifo_overflow <= { fir_fifo_rsp_good_overflow, fir_fifo_rsp_bad_overflow, fir_fifo_rspdat_o_overflow, fir_fifo_rspdat_e_overflow, fir_fifo_retry_overflow };
end
// psl default clock = (posedge clk);
//==== PSL ASSERTION ==============================================================================
//// psl TLX_RESPONSE_DATA_SYNC : assert always ((MODE)? (all_fifos_emptied ? (fifo_rsp_good_empty && fifo_rspdat_o_empty && fifo_rspdat_e_empty) : 1'b1) : 1'b1) report "TLX response and data not synced! Response info and data FIFO should always be in the same status because good TLX response info and response data are expected to come in pairs.";
// psl DATA_BRIDGE_RESPONSE_CONFLICT : assert always ((MODE)? onehot0({fifo_rsp_good_full_dv, fifo_rsp_bad_full_dv, rty_valid, prt_valid}) : onehot0({rsp_good_full_valid, rsp_bad_full_valid, rty_valid, prt_valid})) report "there should be only one response among good, bad, retry and partial responses committed to data bridge each time!";
//==== PSL ASSERTION ==============================================================================
//==== PSL COVERAGE ==============================================================================
// psl TLX_RSP_17_DL1_DP0 : cover {(rsp_valid && (rsp_type[17]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_16_DL1_DP0 : cover {(rsp_valid && (rsp_type[16]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_15_DL1_DP0 : cover {(rsp_valid && (rsp_type[15]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_14_DL1_DP0 : cover {(rsp_valid && (rsp_type[14]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_13_DL1_DP0 : cover {(rsp_valid && (rsp_type[13]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_12_DL1_DP0 : cover {(rsp_valid && (rsp_type[12]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_11_DL1_DP0 : cover {(rsp_valid && (rsp_type[11]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_10_DL1_DP0 : cover {(rsp_valid && (rsp_type[10]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_09_DL1_DP0 : cover {(rsp_valid && (rsp_type[09]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_08_DL1_DP0 : cover {(rsp_valid && (rsp_type[08]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_07_DL1_DP0 : cover {(rsp_valid && (rsp_type[07]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_06_DL1_DP0 : cover {(rsp_valid && (rsp_type[06]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_05_DL1_DP0 : cover {(rsp_valid && (rsp_type[05]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_04_DL1_DP0 : cover {(rsp_valid && (rsp_type[04]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_03_DL1_DP0 : cover {(rsp_valid && (rsp_type[03]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_02_DL1_DP0 : cover {(rsp_valid && (rsp_type[02]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_01_DL1_DP0 : cover {(rsp_valid && (rsp_type[01]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_00_DL1_DP0 : cover {(rsp_valid && (rsp_type[00]) && (rsp_dl==2'd1) && (rsp_dp==2'd0))};
// psl TLX_RSP_17_DL1_DP1 : cover {(rsp_valid && (rsp_type[17]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_16_DL1_DP1 : cover {(rsp_valid && (rsp_type[16]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_15_DL1_DP1 : cover {(rsp_valid && (rsp_type[15]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_14_DL1_DP1 : cover {(rsp_valid && (rsp_type[14]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_13_DL1_DP1 : cover {(rsp_valid && (rsp_type[13]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_12_DL1_DP1 : cover {(rsp_valid && (rsp_type[12]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_11_DL1_DP1 : cover {(rsp_valid && (rsp_type[11]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_10_DL1_DP1 : cover {(rsp_valid && (rsp_type[10]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_09_DL1_DP1 : cover {(rsp_valid && (rsp_type[09]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_08_DL1_DP1 : cover {(rsp_valid && (rsp_type[08]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_07_DL1_DP1 : cover {(rsp_valid && (rsp_type[07]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_06_DL1_DP1 : cover {(rsp_valid && (rsp_type[06]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_05_DL1_DP1 : cover {(rsp_valid && (rsp_type[05]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_04_DL1_DP1 : cover {(rsp_valid && (rsp_type[04]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_03_DL1_DP1 : cover {(rsp_valid && (rsp_type[03]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_02_DL1_DP1 : cover {(rsp_valid && (rsp_type[02]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_01_DL1_DP1 : cover {(rsp_valid && (rsp_type[01]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_00_DL1_DP1 : cover {(rsp_valid && (rsp_type[00]) && (rsp_dl==2'd1) && (rsp_dp==2'd1))};
// psl TLX_RSP_17_DL2 : cover {(rsp_valid && (rsp_type[17]) && (rsp_dl==2'd2))};
// psl TLX_RSP_16_DL2 : cover {(rsp_valid && (rsp_type[16]) && (rsp_dl==2'd2))};
// psl TLX_RSP_15_DL2 : cover {(rsp_valid && (rsp_type[15]) && (rsp_dl==2'd2))};
// psl TLX_RSP_14_DL2 : cover {(rsp_valid && (rsp_type[14]) && (rsp_dl==2'd2))};
// psl TLX_RSP_13_DL2 : cover {(rsp_valid && (rsp_type[13]) && (rsp_dl==2'd2))};
// psl TLX_RSP_12_DL2 : cover {(rsp_valid && (rsp_type[12]) && (rsp_dl==2'd2))};
// psl TLX_RSP_11_DL2 : cover {(rsp_valid && (rsp_type[11]) && (rsp_dl==2'd2))};
// psl TLX_RSP_10_DL2 : cover {(rsp_valid && (rsp_type[10]) && (rsp_dl==2'd2))};
// psl TLX_RSP_09_DL2 : cover {(rsp_valid && (rsp_type[09]) && (rsp_dl==2'd2))};
// psl TLX_RSP_08_DL2 : cover {(rsp_valid && (rsp_type[08]) && (rsp_dl==2'd2))};
// psl TLX_RSP_07_DL2 : cover {(rsp_valid && (rsp_type[07]) && (rsp_dl==2'd2))};
// psl TLX_RSP_06_DL2 : cover {(rsp_valid && (rsp_type[06]) && (rsp_dl==2'd2))};
// psl TLX_RSP_05_DL2 : cover {(rsp_valid && (rsp_type[05]) && (rsp_dl==2'd2))};
// psl TLX_RSP_04_DL2 : cover {(rsp_valid && (rsp_type[04]) && (rsp_dl==2'd2))};
// psl TLX_RSP_03_DL2 : cover {(rsp_valid && (rsp_type[03]) && (rsp_dl==2'd2))};
// psl TLX_RSP_02_DL2 : cover {(rsp_valid && (rsp_type[02]) && (rsp_dl==2'd2))};
// psl TLX_RSP_01_DL2 : cover {(rsp_valid && (rsp_type[01]) && (rsp_dl==2'd2))};
// psl TLX_RSP_00_DL2 : cover {(rsp_valid && (rsp_type[00]) && (rsp_dl==2'd2))};
// psl TLX_RSP_PRT_NO_DATA : cover {prt_rsp_last_no_data};
// psl TLX_RSP_PRT_ALL_DATA : cover {prt_rsp_last_all_data};
// psl TLX_RSP_PRT_ANY_RTY : cover {prt_rsp_retry};
// psl TLX_RSP_PRT_ANY_DONE : cover {prt_rsp_done};
// psl TLX_RSP_PRT_ANY_FAIL : cover {prt_rsp_failed};
//==== PSL CONVERAGE ==============================================================================
endmodule |
module fifo_async
#(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 5,
parameter DISTR = 0
)
(
input wr_clk,
input wr_rst,
input wr_en,
input [DATA_WIDTH-1:0] din,
input rd_clk,
input rd_rst,
input rd_en,
output [DATA_WIDTH-1:0] dout,
output valid,
output reg [ADDR_WIDTH-1:0] rd_data_count,
output reg [ADDR_WIDTH-1:0] wr_data_count,
output reg full,
output reg empty,
output reg overflow,
output reg underflow,
output reg almost_full,
output reg almost_empty
);
wire [ADDR_WIDTH:0] wr_pnt_nxt;
reg [ADDR_WIDTH:0] wr_pnt;
wire [ADDR_WIDTH:0] wr_gray_nxt;
reg [ADDR_WIDTH:0] wr_gray;
reg [ADDR_WIDTH:0] r2w_gray_sync1, r2w_gray_sync2;
wire [ADDR_WIDTH:0] r2w_bin;
wire [ADDR_WIDTH:0] rd_pnt_nxt;
reg [ADDR_WIDTH:0] rd_pnt;
wire [ADDR_WIDTH:0] rd_gray_nxt;
reg [ADDR_WIDTH:0] rd_gray;
reg [ADDR_WIDTH:0] w2r_gray_sync1, w2r_gray_sync2;
wire [ADDR_WIDTH:0] w2r_bin;
wire ram_clka;
wire ram_clkb;
wire ram_ena;
wire ram_enb;
wire ram_wea;
wire ram_web;
wire [ADDR_WIDTH-1:0] ram_addra;
wire [ADDR_WIDTH-1:0] ram_addrb;
wire [DATA_WIDTH-1:0] ram_dia;
wire [DATA_WIDTH-1:0] ram_dib;
wire [DATA_WIDTH-1:0] ram_doa;
wire [DATA_WIDTH-1:0] ram_dob;
wire [DATA_WIDTH-1:0] dcnt_0 = {DATA_WIDTH{1'b0}};
wire [ADDR_WIDTH:0] pcnt_0 = {ADDR_WIDTH+1{1'b0}};
wire [ADDR_WIDTH:0] pcnt_1 = {{ADDR_WIDTH{1'b0}}, 1'b1};
wire [ADDR_WIDTH:0] pcnt_2 = {{ADDR_WIDTH-2{1'b0}}, 2'b10};
wire [ADDR_WIDTH-1:0] pcnt_max_2 = {{ADDR_WIDTH-1{1'b1}}, 1'b0};
reg rd_en_sync;
wire wr_rst_n = ~wr_rst;
wire rd_rst_n = ~rd_rst;
parameter DEPTH = 2**ADDR_WIDTH;
assign wr_pnt_nxt = wr_pnt + pcnt_1;
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
wr_pnt <= pcnt_0;
else if(wr_en && ~full)
wr_pnt <= wr_pnt_nxt;
assign wr_gray_nxt = (wr_pnt_nxt>>1) ^ wr_pnt_nxt;
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
wr_gray <= pcnt_0;
else if(wr_en && ~full)
wr_gray <= wr_gray_nxt;
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
{r2w_gray_sync2, r2w_gray_sync1} <= {pcnt_0, pcnt_0};
else
{r2w_gray_sync2, r2w_gray_sync1} <= {r2w_gray_sync1, rd_gray};
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
full <= 1'b0;
else if((wr_gray_nxt == {~r2w_gray_sync2[ADDR_WIDTH:ADDR_WIDTH-1], r2w_gray_sync2[ADDR_WIDTH-2:0]}) && wr_en)
full <= 1'b1;
else if(wr_gray != {~r2w_gray_sync2[ADDR_WIDTH:ADDR_WIDTH-1], r2w_gray_sync2[ADDR_WIDTH-2:0]})
full <= 1'b0;
genvar i;
generate
for(i = ADDR_WIDTH; i >= 0; i = i-1)
begin
if(i == ADDR_WIDTH)
assign r2w_bin[i] = r2w_gray_sync2[i];
else
assign r2w_bin[i] = r2w_bin[i+1] ^ r2w_gray_sync2[i];
end
endgenerate
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
almost_full <= 1'b0;
else if((((r2w_bin[ADDR_WIDTH] != wr_pnt_nxt[ADDR_WIDTH]) && (r2w_bin[ADDR_WIDTH-1:0] - wr_pnt_nxt[ADDR_WIDTH-1:0] <= pcnt_2)) ||
((r2w_bin[ADDR_WIDTH] == wr_pnt_nxt[ADDR_WIDTH]) && (wr_pnt_nxt[ADDR_WIDTH-1:0] - r2w_bin[ADDR_WIDTH-1:0] >= pcnt_max_2))))
almost_full <= 1'b1;
else if(((r2w_bin[ADDR_WIDTH] != wr_pnt_nxt[ADDR_WIDTH]) && (r2w_bin[ADDR_WIDTH-1:0] - wr_pnt_nxt[ADDR_WIDTH-1:0] > pcnt_2)) ||
((r2w_bin[ADDR_WIDTH] == wr_pnt_nxt[ADDR_WIDTH]) && (wr_pnt_nxt[ADDR_WIDTH-1:0] - r2w_bin[ADDR_WIDTH-1:0] < pcnt_max_2)))
almost_full <= 1'b0;
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
wr_data_count <= pcnt_0[ADDR_WIDTH-1:0];
else
wr_data_count <= (r2w_bin[ADDR_WIDTH] == wr_pnt[ADDR_WIDTH])? (wr_pnt[ADDR_WIDTH-1:0] - r2w_bin[ADDR_WIDTH-1:0]) :
(DEPTH - (r2w_bin[ADDR_WIDTH-1:0] - wr_pnt[ADDR_WIDTH-1:0]));
always@(posedge wr_clk or negedge wr_rst_n)
if(~wr_rst_n)
overflow <= 1'b0;
else
overflow <= full && wr_en;
assign rd_pnt_nxt = rd_pnt + pcnt_1;
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
rd_pnt <= pcnt_0;
else if(rd_en && ~empty)
rd_pnt <= rd_pnt_nxt;
assign rd_gray_nxt = (rd_pnt_nxt>>1) ^ rd_pnt_nxt;
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
rd_gray <= pcnt_0;
else if(rd_en && ~empty)
rd_gray <= rd_gray_nxt;
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
{w2r_gray_sync2, w2r_gray_sync1} <= {pcnt_0, pcnt_0};
else
{w2r_gray_sync2, w2r_gray_sync1} <= {w2r_gray_sync1, wr_gray};
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
empty <= 1'b1;
else if((rd_gray_nxt == w2r_gray_sync2) && rd_en)
empty <= 1'b1;
else if(rd_gray != w2r_gray_sync2)
empty <= 1'b0;
genvar j;
generate
for(j = ADDR_WIDTH; j >= 0; j = j-1)
begin
if(j == ADDR_WIDTH)
assign w2r_bin[j] = w2r_gray_sync2[j];
else
assign w2r_bin[j] = w2r_bin[j+1] ^ w2r_gray_sync2[j];
end
endgenerate
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
almost_empty <= 1'b1;
else if((((w2r_bin[ADDR_WIDTH] == rd_pnt_nxt[ADDR_WIDTH]) && (w2r_bin[ADDR_WIDTH-1:0] - rd_pnt_nxt[ADDR_WIDTH-1:0] <= pcnt_2)) ||
((w2r_bin[ADDR_WIDTH] != rd_pnt_nxt[ADDR_WIDTH]) && (rd_pnt_nxt[ADDR_WIDTH-1:0] - w2r_bin[ADDR_WIDTH-1:0] >= pcnt_max_2))))
almost_empty <= 1'b1;
else if (((w2r_bin[ADDR_WIDTH] == rd_pnt_nxt[ADDR_WIDTH]) && (w2r_bin[ADDR_WIDTH-1:0] - rd_pnt_nxt[ADDR_WIDTH-1:0] > pcnt_2)) ||
((w2r_bin[ADDR_WIDTH] != rd_pnt_nxt[ADDR_WIDTH]) && (rd_pnt_nxt[ADDR_WIDTH-1:0] - w2r_bin[ADDR_WIDTH-1:0] < pcnt_max_2)))
almost_empty <= 1'b0;
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
rd_data_count <= pcnt_0[ADDR_WIDTH-1:0];
else
rd_data_count <= (w2r_bin[ADDR_WIDTH] == rd_pnt[ADDR_WIDTH])? (w2r_bin[ADDR_WIDTH-1:0] - rd_pnt[ADDR_WIDTH-1:0]) :
(DEPTH - (rd_pnt[ADDR_WIDTH-1:0] - w2r_bin[ADDR_WIDTH-1:0]));
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
rd_en_sync <= 1'b0;
else
rd_en_sync <= rd_en;
always@(posedge rd_clk or negedge rd_rst_n)
if(~rd_rst_n)
underflow <= 1'b0;
else
underflow <= empty && rd_en;
assign ram_clka = wr_clk;
assign ram_clkb = rd_clk;
assign ram_ena = 1'b1;
assign ram_enb = 1'b1;
assign ram_wea = wr_en;
assign ram_web = 1'b0;
assign ram_addra = wr_pnt[ADDR_WIDTH-1:0];
assign ram_addrb = rd_pnt[ADDR_WIDTH-1:0];
assign ram_dia = din;
assign ram_dib = dcnt_0;
assign dout = ram_dob;
assign valid = rd_en_sync && ~underflow;
ram_true_dual #(DATA_WIDTH,ADDR_WIDTH,DISTR) mram_true_dual (.clka(ram_clka),.clkb(ram_clkb),.ena(ram_ena),.enb(ram_enb),.wea(ram_wea),.web(ram_web),.addra(ram_addra),.addrb(ram_addrb),.dia(ram_dia),.dib(ram_dib),.doa(ram_doa),.dob(ram_dob));
endmodule |
module ram_simple_dual #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 5, parameter DISTR = 0) (clk,ena,enb,wea,addra,addrb,dia,dob);
parameter DEPTH = 2**ADDR_WIDTH;
input clk,ena,enb,wea;
input [ADDR_WIDTH-1:0] addra,addrb;
input [DATA_WIDTH-1:0] dia;
output [DATA_WIDTH-1:0] dob;
reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
reg [DATA_WIDTH-1:0] dob;
generate
if (DISTR) begin : distributed_ram
(* ram_style = "distributed" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
always @(posedge clk) begin
if (ena) begin
if (wea)
ram[addra] <= dia;
end end
always @(posedge clk) begin
if (enb)
dob <= ram[addrb];
end
end
else begin : block_ram
reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];
integer i;
initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;
always @(posedge clk) begin
if (ena) begin
if (wea)
ram[addra] <= dia;
end end
always @(posedge clk) begin
if (enb)
dob <= ram[addrb];
end
end
endgenerate
endmodule |
module brdg_context_surveil
#(
parameter DISTR = 0
)
(
input clk ,
input rst_n ,
//---- configuration --------------------------------------
input [011:0] cfg_actag_base ,
input [019:0] cfg_pasid_base ,
input [019:0] cfg_pasid_mask ,
output tlx_cmd_s1_ready ,
output tlx_wdata_rdrq ,
input tlx_i_cmd_valid ,
input [007:0] tlx_i_cmd_opcode ,
input [015:0] tlx_i_cmd_afutag ,
input [067:0] tlx_i_cmd_ea_or_obj ,
input [001:0] tlx_i_cmd_dl ,
input [002:0] tlx_i_cmd_pl ,
input [011:0] tlx_i_cmd_actag ,
input [019:0] tlx_i_cmd_pasid ,
output tlx_o_cmd_valid ,
output [007:0] tlx_o_cmd_opcode ,
output [015:0] tlx_o_cmd_afutag ,
output [067:0] tlx_o_cmd_ea_or_obj ,
output [001:0] tlx_o_cmd_dl ,
output [002:0] tlx_o_cmd_pl ,
output [011:0] tlx_o_cmd_actag ,
output [019:0] tlx_o_cmd_pasid ,
input tlx_afu_cmd_ready
);
localparam [7:0] AFU_TLX_CMD_OPCODE_ASSIGN_ACTAG = 8'b0101_0000; // Assign acTag
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_W = 8'b0010_0000; // DMA Write
localparam [7:0] AFU_TLX_CMD_OPCODE_DMA_PR_W = 8'b0011_0000; // DMA Partial Write
reg s1_cmd_valid ;
reg [007:0] s1_cmd_opcode ;
reg [011:0] s1_cmd_actag ;
reg [067:0] s1_cmd_ea_or_obj ;
reg [015:0] s1_cmd_afutag ;
reg [001:0] s1_cmd_dl ;
reg [002:0] s1_cmd_pl ;
reg [019:0] s1_cmd_pasid ;
wire s1_ready ;
reg s2_cmd_valid ;
reg [007:0] s2_cmd_opcode ;
reg [011:0] s2_cmd_actag ;
reg [067:0] s2_cmd_ea_or_obj ;
reg [015:0] s2_cmd_afutag ;
reg [001:0] s2_cmd_dl ;
reg [002:0] s2_cmd_pl ;
reg [019:0] s2_cmd_pasid ;
wire s2_ready ;
wire ram_wr_en ;
wire [005:0] ram_wr_addr ;
wire [005:0] ram_rd_addr ;
wire [`CTXW-6:0] ram_data_i ;
wire [`CTXW-6:0] ram_data_o ;
wire entry_valid ;
wire [`CTXW-7:0] pasid_stored_in_entry;
wire send_assign_actag ;
reg send_assign_actag_dly;
reg [019:0] cmd_pasid_aligned ;
reg [011:0] cmd_actag ;
parameter DEPTH = 2**6 ; // ADDR_WIDTH used here is 6
reg [DEPTH-1:0] bit0 ;
//-----------------------------------------------------------------------------------------------------------
// stage 0: read pasid<->actag mapping ram, use input pasid[5:0](actag) as address
//-----------------------------------------------------------------------------------------------------------
assign tlx_cmd_s1_ready = s1_ready;
// pasid<->actag mapping ram.
// as actag should be less than 64 but pasid should be less than 512, use this ram to mapping the 6bit actag with 9bit pasid
// the mapping is handled in this way: actag is equal to pasid[5:0] and is used as rd/wr addr for this ram while pasid[8:6] is
// store in this ram.
// in each entry of this ram, there is an extra valid bit to indicate whether actag<->pasid mapping relationship has been setup
// in this entry
ram_simple_dual #(`CTXW-5,6,DISTR) mram_simple_dual (
.clk (clk ),
.ena (1'b1 ),
.enb (1'b1 ),
.wea (ram_wr_en ),
.addra (ram_wr_addr),
.addrb (ram_rd_addr),
.dia (ram_data_i ),
.dob (ram_data_o ));
assign ram_rd_addr = tlx_i_cmd_actag[5:0];
// manage separately bit 0 to be able to reset it
always @(posedge clk) begin
if (~rst_n)
bit0 <= 0;
else begin
if (ram_wr_en) begin
if (ram_data_i[0:0])
bit0 <= bit0 | (1'b1 << ram_wr_addr); //set 1 to the ram_wr_addr position
else
bit0 <= bit0 & ~(1'b1 << ram_wr_addr); //set 0 to the ram_wr_addr position
end
else
bit0 <= bit0;
end
end
//-----------------------------------------------------------------------------------------------------------
// stage 1: check if pasid<->actag mapping ram need to be updated. if need update, update this ram and
// send assign_actag cmd to stage 2 at the same time, else pass tlx_cmd in stage 1 to stage 2 directly
//-----------------------------------------------------------------------------------------------------------
assign s1_ready = (s2_ready && (!send_assign_actag));
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
s1_cmd_valid <= 1'b0;
else if(tlx_i_cmd_valid && s1_ready)
s1_cmd_valid <= 1'b1;
else if(s2_ready && (!send_assign_actag))
s1_cmd_valid <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
s1_cmd_opcode <= 0;
s1_cmd_actag <= 0;
s1_cmd_ea_or_obj <= 0;
s1_cmd_afutag <= 0;
s1_cmd_dl <= 0;
s1_cmd_pl <= 0;
s1_cmd_pasid <= 0;
end
else if(s1_ready && tlx_i_cmd_valid)
begin
s1_cmd_opcode <= tlx_i_cmd_opcode ;
s1_cmd_actag <= tlx_i_cmd_actag ;
s1_cmd_ea_or_obj <= tlx_i_cmd_ea_or_obj;
s1_cmd_afutag <= tlx_i_cmd_afutag ;
s1_cmd_dl <= tlx_i_cmd_dl ;
s1_cmd_pl <= tlx_i_cmd_pl ;
s1_cmd_pasid <= tlx_i_cmd_pasid ;
end
end
assign entry_valid = bit0[ram_rd_addr]; //ram_data_o[0];
assign pasid_stored_in_entry = ram_data_o[`CTXW-6:1];
assign send_assign_actag = s1_cmd_valid && s2_ready && !(send_assign_actag_dly) && (!entry_valid || (pasid_stored_in_entry != s1_cmd_pasid[`CTXW-1:6]));
assign ram_wr_en = send_assign_actag;
assign ram_wr_addr = s1_cmd_actag[5:0];
assign ram_data_i = {s1_cmd_pasid[`CTXW-1:6], 1'b1};
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
send_assign_actag_dly <= 1'b0;
else
send_assign_actag_dly <= send_assign_actag;
end
//-----------------------------------------------------------------------------------------------------------
// stage 2: send command to afu_tlx interface
//-----------------------------------------------------------------------------------------------------------
assign s2_ready = tlx_afu_cmd_ready;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
s2_cmd_valid <= 1'b0;
else
s2_cmd_valid <= s1_cmd_valid && s2_ready;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
s2_cmd_opcode <= 0;
else if(s1_cmd_valid && s2_ready)
s2_cmd_opcode <= send_assign_actag ? AFU_TLX_CMD_OPCODE_ASSIGN_ACTAG : s1_cmd_opcode;
end
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
s2_cmd_actag <= 0;
s2_cmd_ea_or_obj <= 0;
s2_cmd_afutag <= 0;
s2_cmd_dl <= 0;
s2_cmd_pl <= 0;
s2_cmd_pasid <= 0;
end
else if(s1_cmd_valid && s2_ready)
begin
s2_cmd_actag <= s1_cmd_actag ;
s2_cmd_ea_or_obj <= s1_cmd_ea_or_obj;
s2_cmd_afutag <= s1_cmd_afutag ;
s2_cmd_dl <= s1_cmd_dl ;
s2_cmd_pl <= s1_cmd_pl ;
s2_cmd_pasid <= s1_cmd_pasid ;
end
//----ouptut signals----
assign tlx_wdata_rdrq = s1_cmd_valid && s2_ready && (!send_assign_actag) && ((s1_cmd_opcode == AFU_TLX_CMD_OPCODE_DMA_W) || (s1_cmd_opcode == AFU_TLX_CMD_OPCODE_DMA_PR_W));
assign tlx_o_cmd_valid = s2_cmd_valid ;
assign tlx_o_cmd_opcode = s2_cmd_opcode ;
assign tlx_o_cmd_afutag = s2_cmd_afutag ;
assign tlx_o_cmd_ea_or_obj = s2_cmd_ea_or_obj;
assign tlx_o_cmd_dl = s2_cmd_dl ;
assign tlx_o_cmd_pl = s2_cmd_pl ;
assign tlx_o_cmd_actag = {6'b0,s2_cmd_actag[5:0]};
assign tlx_o_cmd_pasid = s2_cmd_pasid ;
endmodule |
module odma_h2a_st_engine #(
parameter AXIS_ID_WIDTH = 5,
parameter AXIS_DATA_WIDTH = 1024,
parameter AXIS_USER_WIDTH = 8
)
(
input clk ,
input rst_n ,
//---------- Descriptor Interface ---------------------------//
output dsc_ready ,
input dsc_valid ,
input [0255:0] dsc_data ,
//---------- Completion Interface ---------------------------//
output reg cmp_valid_0 ,
output reg [0511:0] cmp_data_0 ,
input cmp_resp_0 ,
output reg cmp_valid_1 ,
output reg [0511:0] cmp_data_1 ,
input cmp_resp_1 ,
output reg cmp_valid_2 ,
output reg [0511:0] cmp_data_2 ,
input cmp_resp_2 ,
output reg cmp_valid_3 ,
output reg [0511:0] cmp_data_3 ,
input cmp_resp_3 ,
//---------- LCL Read Interface -----------------------------//
//---------- Read Addr/Req Channel --------------------------//
output lcl_rd_valid ,
output [0063:0] lcl_rd_ea ,
output [AXIS_ID_WIDTH - 1:0] lcl_rd_axi_id ,
output lcl_rd_first ,
output lcl_rd_last ,
output [0127:0] lcl_rd_be ,
output [0008:0] lcl_rd_ctx ,
output lcl_rd_ctx_valid ,
input lcl_rd_ready ,
//---------- Read Data/Resp Channel -------------------------//
input lcl_rd_data_valid ,
input [1023:0] lcl_rd_data ,
input [AXIS_ID_WIDTH - 1:0] lcl_rd_data_axi_id,
input lcl_rd_data_last ,
input lcl_rd_rsp_code ,
output [0003:0] lcl_rd_rsp_ready ,
output [0003:0] lcl_rd_rsp_ready_hint,
//---------- AXI4-ST Write Interface -----------------------//
output m_axis_tvalid ,
input m_axis_tready ,
output [AXIS_DATA_WIDTH - 1:0] m_axis_tdata ,
output [AXIS_DATA_WIDTH/8 - 1:0] m_axis_tkeep ,
output m_axis_tlast ,
output [AXIS_ID_WIDTH - 1:0] m_axis_tid ,
output [AXIS_USER_WIDTH - 1:0] m_axis_tuser
);
reg [0255:0] dsc_data_0;
reg [0255:0] dsc_data_1;
reg [0001:0] dsc_data_status;
reg [0021:0] lcl_rd_req_cnt;
reg [0021:0] lcl_rd_req_number;
reg parser_ready;
reg [0005:0] rd_axi_id_reg;
reg [0063:0] lcl_src_addr;
wire [0063:0] src_addr;
wire lcl_rd_issue;
wire [0002:0] engine_id;
reg [0255:0] descriptor;
wire is_dsc_valid;
wire interrupt_req;
wire [0001:0] channel_id;
wire [0029:0] dsc_id;
wire [0027:0] dsc_len;
wire [0020:0] lcl_req_len;
wire [0020:0] axis_wdata_len;
wire st_eop;
// Descriptor signals
reg dsc_onflight;
reg dsc_interrupt_req;
reg [0001:0] dsc_channel_id;
reg [0029:0] dsc_id_reg;
reg dsc_st_eop;
`ifdef ACTION_DATA_WIDTH_512
reg [0021:0] dsc_axis_data_number;
reg [0021:0] dsc_axis_data_cnt;
`else
reg [0020:0] dsc_axis_data_number;
reg [0020:0] dsc_axis_data_cnt;
`endif
wire dsc_axis_data_first_beat;
wire dsc_axis_data_last_beat;
reg dsc_lcl_rd_error;
reg [0063:0] dsc_lcl_src_addr;
reg [0063:0] dsc_error_src_addr;
wire dsc_axis_data_complete;
// LCL Read Data FIFO signals
reg [1023:0] rdata_fifo_din;
reg rdata_fifo_wen;
wire rdata_fifo_ren;
wire rdata_fifo_valid;
wire [1023:0] rdata_fifo_dout;
wire rdata_fifo_full;
wire rdata_fifo_almost_full;
wire [0005:0] rdata_fifo_cnt;
wire rdata_fifo_empty;
wire rdata_fifo_almost_empty;
wire dsc_sts_error;
wire [0511:0] dsc_cmp_data;
reg dsc_cmp;
wire axis_data_issue;
wire lcl_rd_data_receive;
/////////////////////////////////////////////////////////////////////////////
//
// dsc_buffer
// +------------+ descriptor
// +---------+ dsc_data | dsc_data_0 | ------------> +------------+
// | dsc_eng | ---------> -------------- | dsc_parser |
// +---------+ <--------- | dsc_data_1 | <------------ +------------+
// dsc_ready +------------+ parser_ready
//
//
// dsc_data_status: bit0 - Data is pushed into dsc_data_0;
// bit1 - Data is pushed into dsc_data_1.
//
// When dsc_valid is 1, the dsc_buffer will receive the dsc_data and push
// into the dsc_buffer.
// When parser_ready is 1, the dsc_buffer will send the descriptor to the
// dsc_parser.
// There are 2 cylces for dsc_data transfer from dsc_eng to dsc_parser.
//
/////////////////////////////////////////////////////////////////////////////
always@(posedge clk)
casex ({dsc_valid, parser_ready, dsc_data_status})
4'b1x00: dsc_data_0 <= dsc_data;
4'b1110: dsc_data_0 <= dsc_data;
4'b0101: dsc_data_0 <= 256'b0;
4'b1101: dsc_data_0 <= dsc_data;
4'bx010: dsc_data_0 <= dsc_data_1;
4'b0111: dsc_data_0 <= dsc_data_1;
default: dsc_data_0 <= dsc_data_0;
endcase
always@(posedge clk)
casex ({dsc_valid, parser_ready, dsc_data_status})
4'b1001: dsc_data_1 <= dsc_data;
4'b1101: dsc_data_1 <= 256'b0;
4'b1010: dsc_data_1 <= dsc_data;
4'b0x10: dsc_data_1 <= 256'b0;
4'b1110: dsc_data_1 <= 256'b0;
4'b0111: dsc_data_1 <= 256'b0;
default: dsc_data_1 <= dsc_data_1;
endcase
always@(posedge clk or negedge rst_n)
if (!rst_n)
dsc_data_status <= 2'b00;
else
casex ({dsc_data_status[1:0], dsc_valid, parser_ready})
4'b001x: dsc_data_status <= 2'b01; // dsc_data will be pushed into the data_buffer first
4'b0101: dsc_data_status <= 2'b00;
4'b0110: dsc_data_status <= 2'b11;
4'b1000: dsc_data_status <= 2'b01;
4'b1001: dsc_data_status <= 2'b00;
4'b1010: dsc_data_status <= 2'b11;
4'b1011: dsc_data_status <= 2'b01;
4'b1101: dsc_data_status <= 2'b01;
default: dsc_data_status <= dsc_data_status;
endcase
assign dsc_ready = ~(dsc_data_status[0] & dsc_data_status[1]);
//*****************************************************//
// //
// When parser_ready is high and there is valid data //
// in the descriptor buffer, the buffer will send one //
// descriptor to the dsc_parser. //
// //
//*****************************************************//
always @(*) begin
casex ({parser_ready, dsc_data_status[1:0]})
3'b1x1: descriptor = dsc_data_0;
3'b110: descriptor = dsc_data_1;
default: descriptor = 256'b0;
endcase
end
assign is_dsc_valid = (descriptor[31:16] == 16'had4b);
assign dsc_len = descriptor[59:32];
assign src_addr = descriptor[127:64];
assign dst_addr = descriptor[191:128];
assign channel_id = descriptor[223:222];
assign dsc_id = descriptor[221:192];
assign engine_id = `H2AST_ENGINE_ID;
assign interrupt_req = descriptor[1];
assign st_eop = descriptor[4];
assign lcl_req_len = (dsc_len >> 7);
assign axis_wdata_len = (dsc_len >> 7);
// For Stream mode, ODMA only supports 128B aligned data transfer
// One descriptor will transfer within one data packet for AXI4-Stream interface
////////////////////////////////////////////////////////////////////////////////////////////
//
// +----------------+ +-----------------------+
// +------------+ descriptor | | ----------> | |
// | dsc_buffer | <------------> | dsc_parser | | lcl_rd_req dispatcher |
// +------------+ parser_ready | | <---------- | |
// +----------------+ +-----------------------+
//
// parser_ready: 1) For an idle scenario, the parser_ready is always pulled up.
// 2) From a specific dscriptor is valid at the dsc_parser to the last beat
// of LCL Read Request is sent out, we call the dsc_parser is busy.
// parser_ready will be pulled down when the dsc_parser is busy.
//
////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
if(!rst_n)
rd_axi_id_reg <= 5'b0;
else if (is_dsc_valid)
rd_axi_id_reg <= {channel_id, engine_id};
else
rd_axi_id_reg <= rd_axi_id_reg;
// lcl_rd_req_cnt for lcl read request beat counter
// is_dsc_valid and lcl_rd_valid can not be pulled up at the same cycle
always @(posedge clk or negedge rst_n)
if (!rst_n)
lcl_rd_req_cnt <= 0;
else
case ({is_dsc_valid, lcl_rd_issue})
2'b10: lcl_rd_req_cnt <= lcl_req_len;
2'b01: lcl_rd_req_cnt <= lcl_rd_req_cnt - 1;
default: lcl_rd_req_cnt <= lcl_rd_req_cnt;
endcase
always @(posedge clk or negedge rst_n)
if (!rst_n)
lcl_rd_req_number <= 22'd0;
else if (is_dsc_valid)
lcl_rd_req_number <= lcl_req_len;
else
lcl_rd_req_number <= lcl_rd_req_number;
always @(posedge clk or negedge rst_n)
if (!rst_n)
lcl_src_addr <= 64'b0;
else if (is_dsc_valid)
lcl_src_addr <= src_addr;
else if (lcl_rd_issue && (~lcl_rd_last))
lcl_src_addr <= lcl_src_addr + 64'd128;
else
lcl_src_addr <= lcl_src_addr;
assign lcl_rd_issue = lcl_rd_valid & lcl_rd_ready;
// LCL Read Requst Interface signals
assign lcl_rd_valid = (lcl_rd_req_cnt != 0);
assign lcl_rd_axi_id = rd_axi_id_reg;
assign lcl_rd_first = (lcl_rd_req_cnt != 0) & (lcl_rd_req_cnt == lcl_rd_req_number);
assign lcl_rd_last = (lcl_rd_req_cnt != 0) & (lcl_rd_req_cnt == 21'd1);
assign lcl_rd_ea = lcl_src_addr;
assign lcl_rd_ctx = 9'b0;
assign lcl_rd_ctx_valid = 0;
assign lcl_rd_be = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
// parser_ready signal back to dsc_buffer
always @(posedge clk or negedge rst_n)
if (!rst_n)
parser_ready <= 1;
else if (is_dsc_valid)
parser_ready <= 0;
else if (dsc_cmp)
parser_ready <= 1;
else
parser_ready <= parser_ready;
///////////////////////////////////////////////////////////////////////////////////////////////
//
//
// Descriptor Registers
//
//
///////////////////////////////////////////////////////////////////////////////////////////////
// for dsc_onflight
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_onflight <= 1'b0;
else if (is_dsc_valid)
dsc_onflight <= 1'b1;
else if (dsc_cmp)
dsc_onflight <= 1'b0;
else
dsc_onflight <= dsc_onflight;
// for dsc_interrupt_req
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_interrupt_req <= 1'b0;
else if (is_dsc_valid)
dsc_interrupt_req <= interrupt_req;
else if (dsc_cmp)
dsc_interrupt_req <= 1'b0;
else
dsc_interrupt_req <= dsc_interrupt_req;
// for dsc_channel_id
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_channel_id <= 2'b00;
else if (is_dsc_valid)
dsc_channel_id <= channel_id;
else if (dsc_cmp)
dsc_channel_id <= 2'b00;
else
dsc_channel_id <= dsc_channel_id;
// for dsc_id_reg
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_id_reg <= 30'b0;
else if (is_dsc_valid)
dsc_id_reg <= dsc_id;
else if (dsc_cmp)
dsc_id_reg <= 30'b0;
else
dsc_id_reg <= dsc_id_reg;
// for dsc_st_eop
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_st_eop <= 1'b0;
else if (is_dsc_valid)
dsc_st_eop <= st_eop;
else if (dsc_cmp)
dsc_st_eop <= 1'b0;
else
dsc_st_eop <= dsc_st_eop;
`ifdef ACTION_DATA_WIDTH_512
// for dsc_axis_data_number
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_axis_data_number <= 22'd0;
else if (is_dsc_valid)
dsc_axis_data_number <= (axis_wdata_len << 1);
else if (dsc_cmp)
dsc_axis_data_number <= 21'd0;
else
dsc_axis_data_number <= dsc_axis_data_number;
// for dsc_axis_data_cnt
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_axis_data_cnt <= 22'd0;
else if (is_dsc_valid)
dsc_axis_data_cnt <= (axis_wdata_len << 1);
else if (axis_data_issue)
dsc_axis_data_cnt <= dsc_axis_data_cnt - 1;
else
dsc_axis_data_cnt <= dsc_axis_data_cnt;
`else
// for dsc_axis_data_number
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_axis_data_number <= 21'd0;
else if (is_dsc_valid)
dsc_axis_data_number <= axis_wdata_len;
else if (dsc_cmp)
dsc_axis_data_number <= 21'd0;
else
dsc_axis_data_number <= dsc_axis_data_number;
// for dsc_axis_data_cnt
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_axis_data_cnt <= 21'd0;
else if (is_dsc_valid)
dsc_axis_data_cnt <= axis_wdata_len;
else if (axis_data_issue)
dsc_axis_data_cnt <= dsc_axis_data_cnt - 1;
else
dsc_axis_data_cnt <= dsc_axis_data_cnt;
`endif
assign dsc_axis_data_first_beat = (dsc_axis_data_cnt == dsc_axis_data_number) && dsc_onflight;
assign dsc_axis_data_last_beat = (dsc_axis_data_cnt == 21'd1) && dsc_onflight;
// for dsc_lcl_rd_error
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_lcl_rd_error <= 1'b0;
else if (dsc_lcl_rd_error)
dsc_lcl_rd_error <= 1'b1;
else if (lcl_rd_data_valid)
dsc_lcl_rd_error <= lcl_rd_rsp_code;
else
dsc_lcl_rd_error <= 1'b0;
// for dsc_lcl_src_addr
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_lcl_src_addr <= 64'h0;
else if (is_dsc_valid)
dsc_lcl_src_addr <= src_addr;
else if (lcl_rd_data_receive)
dsc_lcl_src_addr <= dsc_lcl_src_addr + 64'd128;
else if (dsc_cmp)
dsc_lcl_src_addr <= 64'h0;
else
dsc_lcl_src_addr <= dsc_lcl_src_addr;
// for dsc_error_src_addr
always @(posedge clk or negedge rst_n)
if (!rst_n)
dsc_error_src_addr <= 64'h0;
else if (dsc_lcl_rd_error)
dsc_error_src_addr <= dsc_error_src_addr;
else if (lcl_rd_data_valid)
dsc_error_src_addr <= dsc_lcl_src_addr;
else
dsc_error_src_addr <= 64'h0;
assign dsc_axis_data_complete = (dsc_axis_data_cnt == 21'd0) && dsc_onflight;
////////////////////////////////////////////////////////////////////////////////////////////////
//
//
// +----------------+ +------------------+
// | | ----------> | |
// | lcl_rd_data | | rdata_fifo |
// | | ----------> | |
// +----------------+ +------------------+
//
////////////////////////////////////////////////////////////////////////////////////////////////
assign lcl_rd_data_receive = lcl_rd_data_valid && lcl_rd_rsp_ready;
always @(*) begin
if (lcl_rd_data_valid) begin
rdata_fifo_din = lcl_rd_data;
rdata_fifo_wen = 1'b1;
end
else begin
rdata_fifo_din = 1024'b0;
rdata_fifo_wen = 1'b0;
end
end
assign lcl_rd_rsp_ready = ~(rdata_fifo_full);
assign lcl_rd_rsp_ready_hint = ~(rdata_fifo_almost_full);
// rdata_fifo* FIFOs are in FWFT mode
// Xilinx Standard FIFO IP
fifo_sync_32_1024i1024o rdata_fifo (
.clk ( clk ),
.srst ( ~rst_n ),
.din ( rdata_fifo_din ),
.wr_en ( rdata_fifo_wen ),
.rd_en ( rdata_fifo_ren ),
.valid ( rdata_fifo_valid ),
.dout ( rdata_fifo_dout ),
.full ( rdata_fifo_full ),
.almost_full ( rdata_fifo_almost_full ),
.data_count ( rdata_fifo_cnt ),
.empty ( ),
.almost_empty ( rdata_fifo_almost_empty )
);
assign rdata_fifo_empty = (rdata_fifo_cnt == 6'd0);
////////////////////////////////////////////////////////////////////////////////////////////////
//
//
// +----------------+ +------------------+
// | | ----------> | |
// | rdata_fifo | | AXI4-ST IF |
// | | ----------> | |
// +----------------+ +------------------+
//
////////////////////////////////////////////////////////////////////////////////////////////////
assign m_axis_tid = {3'b000, dsc_channel_id};
assign m_axis_tlast = dsc_st_eop & dsc_axis_data_last_beat;
assign m_axis_tuser = 8'b0;
`ifdef ACTION_DATA_WIDTH_512
// TODO
// dsc_axis_data_number is an even number
// 128B
// |
// -------
// | |
// 64B | 64B
// even | odd | even | odd | even | odd
//
wire m_axis_tvalid_128B;
reg m_axis_tvalid_64B_odd;
wire [1023:0] m_axis_tdata_128B;
reg [0511:0] m_axis_tdata_64B_odd;
wire m_axis_wbeat_even;
assign rdata_fifo_ren = (~rdata_fifo_empty) && m_axis_tvalid && m_axis_tready && (~m_axis_wbeat_even);
//always @(posedge clk or negedge rst_n)
// if (!rst_n)
// m_axis_tvalid_128B <= 1'b0;
// else
// m_axis_tvalid_128B <= (dsc_axis_data_cnt != 22'd0) && rdata_fifo_valid;
assign m_axis_tvalid_128B = (dsc_axis_data_cnt != 22'd0) && rdata_fifo_valid;
always @(posedge clk or negedge rst_n)
if (!rst_n)
m_axis_tvalid_64B_odd <= 1'b0;
else if (m_axis_wbeat_even)
m_axis_tvalid_64B_odd <= m_axis_tvalid_128B;
else
m_axis_tvalid_64B_odd <= m_axis_tvalid_64B_odd;
//always @(posedge clk)
// m_axis_tdata_128B <= rdata_fifo_dout;
assign m_axis_tdata_128B = rdata_fifo_dout;
always @(posedge clk)
if (m_axis_wbeat_even)
m_axis_tdata_64B_odd <= m_axis_tdata_128B[1023:512];
else
m_axis_tdata_64B_odd <= m_axis_tdata_64B_odd;
assign m_axis_wbeat_even = (dsc_axis_data_cnt[0] == 1'b0) && dsc_onflight;
assign m_axis_tvalid = (m_axis_wbeat_even)? m_axis_tvalid_128B : m_axis_tvalid_64B_odd;
assign m_axis_tdata = (m_axis_wbeat_even)? m_axis_tdata_128B[511:0] : m_axis_tdata_64B_odd;
assign m_axis_tkeep = 64'hFFFF_FFFF_FFFF_FFFF;
`else
assign rdata_fifo_ren = (~rdata_fifo_empty) && m_axis_tvalid && m_axis_tready;
assign m_axis_tvalid = rdata_fifo_valid;
assign m_axis_tdata = rdata_fifo_dout;
assign m_axis_tkeep = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
`endif
assign axis_data_issue = m_axis_tvalid && m_axis_tready;
////////////////////////////////////////////////////////////////////////////////////////////////
//
// Completion Logic
//
////////////////////////////////////////////////////////////////////////////////////////////////
assign dsc_sts_error = dsc_lcl_rd_error;
assign dsc_cmp_data = {190'b0,
2'b0,
64'b0,
62'b0,
1'b0, dsc_lcl_rd_error,
dsc_error_src_addr,
93'b0,
dsc_interrupt_req,
dsc_channel_id,
dsc_id_reg,
dsc_axis_data_complete,
dsc_sts_error};
always @(posedge clk or negedge rst_n)
if (!rst_n)
cmp_valid_0 <= 1'b0;
else if (cmp_valid_0)
cmp_valid_0 <= (cmp_resp_0)? 1'b0 : cmp_valid_0;
else if (dsc_axis_data_complete && (dsc_channel_id == 2'b00))
cmp_valid_0 <= 1'b1;
else
cmp_valid_0 <= cmp_valid_0;
always @(posedge clk)
if ( dsc_axis_data_complete && (dsc_channel_id == 2'b00))
cmp_data_0 <= dsc_cmp_data;
else
cmp_data_0 <= 512'b0;
always @(posedge clk or negedge rst_n)
if (!rst_n)
cmp_valid_1 <= 1'b0;
else if (cmp_valid_1)
cmp_valid_1 <= (cmp_resp_1)? 1'b0 : cmp_valid_1;
else if (dsc_axis_data_complete && (dsc_channel_id == 2'b01))
cmp_valid_1 <= 1'b1;
else
cmp_valid_1 <= cmp_valid_1;
always @(posedge clk)
if ( dsc_axis_data_complete && (dsc_channel_id == 2'b01))
cmp_data_1 <= dsc_cmp_data;
else
cmp_data_1 <= 512'b0;
always @(posedge clk or negedge rst_n)
if (!rst_n)
cmp_valid_2 <= 1'b0;
else if (cmp_valid_2)
cmp_valid_2 <= (cmp_resp_2)? 1'b0 : cmp_valid_2;
else if (dsc_axis_data_complete && (dsc_channel_id == 2'b10))
cmp_valid_2 <= 1'b1;
else
cmp_valid_2 <= cmp_valid_2;
always @(posedge clk)
if ( dsc_axis_data_complete && (dsc_channel_id == 2'b10))
cmp_data_2 <= dsc_cmp_data;
else
cmp_data_2 <= 512'b0;
always @(posedge clk or negedge rst_n)
if (!rst_n)
cmp_valid_3 <= 1'b0;
else if (cmp_valid_3)
cmp_valid_3 <= (cmp_resp_3)? 1'b0 : cmp_valid_3;
else if (dsc_axis_data_complete && (dsc_channel_id == 2'b11))
cmp_valid_3 <= 1'b1;
else
cmp_valid_3 <= cmp_valid_3;
always @(posedge clk)
if ( dsc_axis_data_complete && (dsc_channel_id == 2'b11))
cmp_data_3 <= dsc_cmp_data;
else
cmp_data_3 <= 512'b0;
always @(*) begin
case (dsc_channel_id)
2'b00: dsc_cmp = cmp_valid_0 & cmp_resp_0;
2'b01: dsc_cmp = cmp_valid_1 & cmp_resp_1;
2'b10: dsc_cmp = cmp_valid_2 & cmp_resp_2;
2'b11: dsc_cmp = cmp_valid_3 & cmp_resp_3;
endcase
end
endmodule |
module odma_lcl_wr_arbiter #(
parameter AXI_ID_WIDTH = 5
)
(
input clk ,
input rst_n ,
//--------------- LCL Write Interface -----------------//
//-------------- Write Addr/Data Channel --------------//
output reg lcl_wr_valid ,
output reg [0063:0] lcl_wr_ea ,
output reg [AXI_ID_WIDTH - 1:0] lcl_wr_axi_id ,
output reg [0127:0] lcl_wr_be ,
output reg lcl_wr_first ,
output reg lcl_wr_last ,
output reg [1023:0] lcl_wr_data ,
output reg [0008:0] lcl_wr_ctx ,
output reg lcl_wr_ctx_valid ,
input lcl_wr_ready ,
//-------------- Write Response Channel ---------------//
input lcl_wr_rsp_valid ,
input [AXI_ID_WIDTH - 1:0] lcl_wr_rsp_axi_id ,
input lcl_wr_rsp_code ,
output [0031:0] lcl_wr_rsp_ready ,
//--------------- CMP Engine LCL Wr IF ----------------//
//-------------- Write Addr/Data Channel --------------//
input cmp_lcl_wr_valid ,
input [0063:0] cmp_lcl_wr_ea ,
input [AXI_ID_WIDTH - 1:0] cmp_lcl_wr_axi_id ,
input [0127:0] cmp_lcl_wr_be ,
input cmp_lcl_wr_first ,
input cmp_lcl_wr_last ,
input [1023:0] cmp_lcl_wr_data ,
input [0008:0] cmp_lcl_wr_ctx ,
input cmp_lcl_wr_ctx_valid ,
output cmp_lcl_wr_ready ,
//-------------- Write Response Channel ---------------//
output reg cmp_lcl_wr_rsp_valid ,
output reg [AXI_ID_WIDTH - 1:0] cmp_lcl_wr_rsp_axi_id,
output reg cmp_lcl_wr_rsp_code ,
input [0031:0] cmp_lcl_wr_rsp_ready ,
//-------------- A2H MM Engine LCL Wr IF --------------//
//-------------- Write Addr/Data Channel --------------//
input mm_lcl_wr_valid ,
input [0063:0] mm_lcl_wr_ea ,
input [AXI_ID_WIDTH - 1:0] mm_lcl_wr_axi_id ,
input [0127:0] mm_lcl_wr_be ,
input mm_lcl_wr_first ,
input mm_lcl_wr_last ,
input [1023:0] mm_lcl_wr_data ,
input [0008:0] mm_lcl_wr_ctx ,
input mm_lcl_wr_ctx_valid ,
output mm_lcl_wr_ready ,
//-------------- Write Response Channel ---------------//
output reg mm_lcl_wr_rsp_valid ,
output reg [AXI_ID_WIDTH - 1:0] mm_lcl_wr_rsp_axi_id ,
output reg mm_lcl_wr_rsp_code ,
input mm_lcl_wr_rsp_ready ,
//-------------- A2H ST Engine LCL Wr IF --------------//
//-------------- Write Addr/Data Channel --------------//
input st_lcl_wr_valid ,
input [0063:0] st_lcl_wr_ea ,
input [AXI_ID_WIDTH - 1:0] st_lcl_wr_axi_id ,
input [0127:0] st_lcl_wr_be ,
input st_lcl_wr_first ,
input st_lcl_wr_last ,
input [1023:0] st_lcl_wr_data ,
input [0008:0] st_lcl_wr_ctx ,
input st_lcl_wr_ctx_valid ,
output st_lcl_wr_ready ,
//-------------- Write Response Channel ---------------//
output reg st_lcl_wr_rsp_valid ,
output reg [AXI_ID_WIDTH - 1:0] st_lcl_wr_rsp_axi_id ,
output reg st_lcl_wr_rsp_code ,
input [0031:0] st_lcl_wr_rsp_ready
);
reg wr_req_cmp_grant;
reg wr_req_mm_grant;
reg wr_req_st_grant;
reg wr_req_arb_en;
reg wr_req_arb_en_extend;
reg no_arb;
wire no_valid;
// Writer Request (Addr/Data) Channel
// wr_req_arbiter
// for wr_req_cmp_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
wr_req_cmp_grant <= 1'b0;
else if (wr_req_arb_en)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: wr_req_cmp_grant <= (cmp_lcl_wr_valid)? 1'b1 : 1'b0;
3'b100: wr_req_cmp_grant <= (mm_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b0 : 1'b1);
3'b010: wr_req_cmp_grant <= (cmp_lcl_wr_valid)? 1'b1 : 1'b0;
3'b001: wr_req_cmp_grant <= (cmp_lcl_wr_valid)? 1'b1: 1'b0;
default:;
endcase
else if (wr_req_arb_en_extend)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b100: wr_req_cmp_grant <= (cmp_lcl_wr_valid)? 1'b1 : 1'b0;
3'b010: wr_req_cmp_grant <= (mm_lcl_wr_valid)? 1'b0 : ((cmp_lcl_wr_valid)? 1'b1 : 1'b0);
3'b001: wr_req_cmp_grant <= (st_lcl_wr_valid)? 1'b0 : ((cmp_lcl_wr_valid)? 1'b1 : 1'b0);
default:;
endcase
else
wr_req_cmp_grant <= wr_req_cmp_grant;
// for wr_req_mm_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
wr_req_mm_grant <= 1'b0;
else if (wr_req_arb_en)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: wr_req_mm_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b1 : 1'b0);
3'b100: wr_req_mm_grant <= (mm_lcl_wr_valid)? 1'b1 : 1'b0;
3'b010: wr_req_mm_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b0 : 1'b1);
3'b001: wr_req_mm_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b1 : 1'b0);
default:;
endcase
else if (wr_req_arb_en_extend)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b100: wr_req_mm_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b1 : 1'b0);
3'b010: wr_req_mm_grant <= (mm_lcl_wr_valid)? 1'b1 : 1'b0;
3'b001: wr_req_mm_grant <= (st_lcl_wr_valid)? 1'b0 : ((cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b1 : 1'b0));
default:;
endcase
else
wr_req_mm_grant <= wr_req_mm_grant;
// for wr_req_st_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
wr_req_st_grant <= 1'b0;
else if (wr_req_arb_en)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: wr_req_st_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b1 : 1'b0));
3'b100: wr_req_st_grant <= (mm_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b1 : 1'b0);
3'b010: wr_req_st_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b1 : 1'b0);
3'b001: wr_req_st_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b0 : 1'b1);
default:;
endcase
else if (wr_req_arb_en_extend)
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b100: wr_req_st_grant <= (cmp_lcl_wr_valid)? 1'b0 : ((mm_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b1 : 1'b0));
3'b010: wr_req_st_grant <= (mm_lcl_wr_valid)? 1'b0 : ((cmp_lcl_wr_valid)? 1'b0 : ((st_lcl_wr_valid)? 1'b1 : 1'b0));
3'b001: wr_req_st_grant <= (st_lcl_wr_valid)? 1'b1 : 1'b0;
default:;
endcase
else
wr_req_st_grant <= wr_req_st_grant;
always @(*) begin
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: no_arb = (~(cmp_lcl_wr_valid || mm_lcl_wr_valid || st_lcl_wr_valid)) && wr_req_arb_en;
3'b100: no_arb = ((cmp_lcl_wr_valid && cmp_lcl_wr_last && (~mm_lcl_wr_valid) && (~st_lcl_wr_valid))) && wr_req_arb_en;
3'b010: no_arb = ((mm_lcl_wr_valid && mm_lcl_wr_last && (~cmp_lcl_wr_valid) && (~st_lcl_wr_valid))) && wr_req_arb_en;
3'b001: no_arb = ((st_lcl_wr_valid && st_lcl_wr_last && (~cmp_lcl_wr_valid) && (~mm_lcl_wr_valid))) && wr_req_arb_en;
default: no_arb = 1'b0;
endcase
end
assign no_valid = ~(cmp_lcl_wr_valid || mm_lcl_wr_valid || st_lcl_wr_valid);
always @(*) begin
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: wr_req_arb_en = 1'b1;
3'b100: wr_req_arb_en = (cmp_lcl_wr_valid) && (cmp_lcl_wr_last) && lcl_wr_ready;
3'b010: wr_req_arb_en = (mm_lcl_wr_valid) && (mm_lcl_wr_last) && lcl_wr_ready;
3'b001: wr_req_arb_en = (st_lcl_wr_valid) && (st_lcl_wr_last) && lcl_wr_ready;
default: wr_req_arb_en = 1'b0;
endcase
end
always @(posedge clk or negedge rst_n)
if (!rst_n)
wr_req_arb_en_extend <= 1'b0;
else if (wr_req_arb_en && no_arb)
wr_req_arb_en_extend <= 1'b1;
else if (wr_req_arb_en_extend && (~no_valid))
wr_req_arb_en_extend <= 1'b0;
else
wr_req_arb_en_extend <= wr_req_arb_en_extend;
// Write Request(Addr/Data) Channel Data path
// LCL_Wr_IF -> Arbiter -> Engines
assign cmp_lcl_wr_ready = lcl_wr_ready && wr_req_cmp_grant;
assign mm_lcl_wr_ready = lcl_wr_ready && wr_req_mm_grant;
assign st_lcl_wr_ready = lcl_wr_ready && wr_req_st_grant;
// Engines -> Arbiter -> LCL_Wr_IF
always @(*) begin
case ({wr_req_cmp_grant, wr_req_mm_grant, wr_req_st_grant})
3'b000: begin
lcl_wr_valid = 1'b0;
lcl_wr_ea = 64'b0;
lcl_wr_axi_id = 5'b0;
lcl_wr_be = 128'b0;
lcl_wr_first = 1'b0;
lcl_wr_last = 1'b0;
lcl_wr_data = 1024'b0;
lcl_wr_ctx = 9'b0;
lcl_wr_ctx_valid = 1'b0;
end
3'b100: begin
lcl_wr_valid = cmp_lcl_wr_valid;
lcl_wr_ea = cmp_lcl_wr_ea;
lcl_wr_axi_id = cmp_lcl_wr_axi_id;
lcl_wr_be = cmp_lcl_wr_be;
lcl_wr_first = cmp_lcl_wr_first;
lcl_wr_last = cmp_lcl_wr_last;
lcl_wr_data = cmp_lcl_wr_data;
lcl_wr_ctx = cmp_lcl_wr_ctx;
lcl_wr_ctx_valid = cmp_lcl_wr_ctx_valid;
end
3'b010: begin
lcl_wr_valid = mm_lcl_wr_valid;
lcl_wr_ea = mm_lcl_wr_ea;
lcl_wr_axi_id = mm_lcl_wr_axi_id;
lcl_wr_be = mm_lcl_wr_be;
lcl_wr_first = mm_lcl_wr_first;
lcl_wr_last = mm_lcl_wr_last;
lcl_wr_data = mm_lcl_wr_data;
lcl_wr_ctx = mm_lcl_wr_ctx;
lcl_wr_ctx_valid = mm_lcl_wr_ctx_valid;
end
3'b001: begin
lcl_wr_valid = st_lcl_wr_valid;
lcl_wr_ea = st_lcl_wr_ea;
lcl_wr_axi_id = st_lcl_wr_axi_id;
lcl_wr_be = st_lcl_wr_be;
lcl_wr_first = st_lcl_wr_first;
lcl_wr_last = st_lcl_wr_last;
lcl_wr_data = st_lcl_wr_data;
lcl_wr_ctx = st_lcl_wr_ctx;
lcl_wr_ctx_valid = st_lcl_wr_ctx_valid;
end
default:;
endcase
end
// Write Response Channel
// wr_resp_dispatcher
// The dispatcher will dispatch the LCL Wr IF Response to the three engines accodring to the axi_id
// Engines -> Arbiter -> LCL Wr IF
assign lcl_wr_rsp_ready[5] = cmp_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[13] = cmp_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[21] = cmp_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[29] = cmp_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[0] = mm_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[8] = mm_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[16] = mm_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[24] = mm_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[1] = st_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[9] = st_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[17] = st_lcl_wr_rsp_ready;
assign lcl_wr_rsp_ready[25] = st_lcl_wr_rsp_ready;
assign {lcl_wr_rsp_ready[31:30], lcl_wr_rsp_ready[28:26], lcl_wr_rsp_ready[23:22], lcl_wr_rsp_ready[20:18], lcl_wr_rsp_ready[15:14], lcl_wr_rsp_ready[12:10], lcl_wr_rsp_ready[7:6], lcl_wr_rsp_ready[4:2]} = 20'b0;
//TODO:split the *_lcl_wr_rsp_ready into 4 signals which represent for 4 channels according to the channel_id width
// LCL_Wr_IF -> Arbiter -> Engines
always @(*) begin
case (lcl_wr_rsp_axi_id[2:0])
`CMP_ENGINE_ID: begin
cmp_lcl_wr_rsp_valid = lcl_wr_rsp_valid;
cmp_lcl_wr_rsp_axi_id = lcl_wr_rsp_axi_id;
cmp_lcl_wr_rsp_code = lcl_wr_rsp_code;
mm_lcl_wr_rsp_valid = 1'b0;
mm_lcl_wr_rsp_axi_id = 5'b0;
mm_lcl_wr_rsp_code = 1'b0;
st_lcl_wr_rsp_valid = 1'b0;
st_lcl_wr_rsp_axi_id = 5'b0;
st_lcl_wr_rsp_code = 1'b0;
end
`A2HMM_ENGINE_ID: begin
cmp_lcl_wr_rsp_valid = 1'b0;
cmp_lcl_wr_rsp_axi_id = 5'b0;
cmp_lcl_wr_rsp_code = 1'b0;
mm_lcl_wr_rsp_valid = lcl_wr_rsp_valid;
mm_lcl_wr_rsp_axi_id = lcl_wr_rsp_axi_id;
mm_lcl_wr_rsp_code = lcl_wr_rsp_code;
st_lcl_wr_rsp_valid = 1'b0;
st_lcl_wr_rsp_axi_id = 5'b0;
st_lcl_wr_rsp_code = 1'b0;
end
`A2HST_ENGINE_ID: begin
cmp_lcl_wr_rsp_valid = 1'b0;
cmp_lcl_wr_rsp_axi_id = 5'b0;
cmp_lcl_wr_rsp_code = 1'b0;
mm_lcl_wr_rsp_valid = 1'b0;
mm_lcl_wr_rsp_axi_id = 5'b0;
mm_lcl_wr_rsp_code = 1'b0;
st_lcl_wr_rsp_valid = lcl_wr_rsp_valid;
st_lcl_wr_rsp_axi_id = lcl_wr_rsp_axi_id;
st_lcl_wr_rsp_code = lcl_wr_rsp_code;
end
default: begin
cmp_lcl_wr_rsp_valid = 1'b0;
cmp_lcl_wr_rsp_axi_id = 5'b0;
cmp_lcl_wr_rsp_code = 1'b0;
mm_lcl_wr_rsp_valid = 1'b0;
mm_lcl_wr_rsp_axi_id = 5'b0;
mm_lcl_wr_rsp_code = 1'b0;
st_lcl_wr_rsp_valid = 1'b0;
st_lcl_wr_rsp_axi_id = 5'b0;
st_lcl_wr_rsp_code = 1'b0;
end
endcase
end
endmodule |
module odma_a2h_st_engine #(
parameter AXIS_ID_WIDTH = 5,
parameter AXIS_DATA_WIDTH = 1024,
parameter AXIS_USER_WIDTH = 8
)
(
input clk,
input rst_n,
//----- dsc engine interface -----
input dsc_valid, //descriptor valid
input [255 : 0] dsc_data, //descriptor data
output dsc_ready, //descriptor ready
//----- AXI4 read data interface -----
input axis_tvalid, //AXI stream valid
output axis_tready, //AXI stream ready
input [AXIS_DATA_WIDTH-1 : 0 ] axis_tdata, //AXI stream data
input [AXIS_DATA_WIDTH/8-1 : 0 ] axis_tkeep, //AXI stream keep
input axis_tlast, //AXI stream last
input [AXIS_ID_WIDTH-1 : 0 ] axis_tid, //AXI stream ID
input [AXIS_USER_WIDTH-1 : 0 ] axis_tuser, //AXI stream user
//----- local write interface -----
output lcl_wr_valid, //local write valid
output [63 : 0] lcl_wr_ea, //local write address
output [AXIS_ID_WIDTH-1 : 0] lcl_wr_axi_id, //local write AXI ID
output [127 : 0] lcl_wr_be, //local write byte enable
output lcl_wr_first, //local write first beat
output lcl_wr_last, //local write last beat
output [1023 : 0] lcl_wr_data, //local write data
input lcl_wr_ready, //local write ready
//----- local write context interface -----
output lcl_wr_ctx_valid, //local context write valid
output [8 : 0] lcl_wr_ctx, //local context write data
//----- local write rsp interface -----
input lcl_wr_rsp_valid, //local write response valid
input [AXIS_ID_WIDTH-1 : 0] lcl_wr_rsp_axi_id, //local write response AXI id
input lcl_wr_rsp_code, //local write response code
output lcl_wr_rsp_ready, //local write response ready
//----- cmp engine interface -----
output dsc_ch0_cmp_valid, //channel0 descriptor complete valid
output [511 : 0] dsc_ch0_cmp_data, //channel0 descriptor complete data
input dsc_ch0_cmp_ready, //channel0 descriptor complete ready
output dsc_ch1_cmp_valid, //channel1 descriptor complete valid
output [511 : 0] dsc_ch1_cmp_data, //channel1 descriptor complete data
input dsc_ch1_cmp_ready, //channel1 descriptor complete ready
output dsc_ch2_cmp_valid, //channel2 descriptor complete valid
output [511 : 0] dsc_ch2_cmp_data, //channel2 descriptor complete data
input dsc_ch2_cmp_ready, //channel2 descriptor complete ready
output dsc_ch3_cmp_valid, //channel3 descriptor complete valid
output [511 : 0] dsc_ch3_cmp_data, //channel3 descriptor complete data
input dsc_ch3_cmp_ready //channel3 descriptor complete ready
);
//------------------------------------------------------------------------------
// Internal signals
//------------------------------------------------------------------------------
//--- Descriptor FIFO ---
wire [255 : 0] dsc_fifo_din; //descriptor FIFO data in
wire dsc_fifo_wr_en; //descriptor FIFO write enable
wire dsc_fifo_rd_en; //descriptor FIFO read enable
wire dsc_fifo_valid; //descriptor FIFO data out valid
wire [255 : 0] dsc_fifo_dout; //descriptor FIFO data out
wire dsc_fifo_full; //descriptor FIFO full
wire dsc_fifo_empty; //descriptor FIFO empty
wire dsc_intr; //descriptor interrupt flag
wire [63 : 0] dsc_dst_addr; //descriptor destination address
wire [27 : 0] dsc_length; //descriptor dma transfer length
wire [ 1 : 0] dsc_channel_id; //descriptor channel ID
wire [29 : 0] dsc_descriptor_id; //descriptor ID
wire [122: 0] dsc_info_data; //descriptor information
//--- Channel Descriptor Read FIFO ---
wire [122 : 0] dsc_ch0_rd_fifo_din; //channel 0 descriptor read FIFO data in
wire dsc_ch0_rd_fifo_wr_en; //channel 0 descriptor read FIFO write enable
wire dsc_ch0_rd_fifo_rd_en; //channel 0 descriptor read FIFO read enable
wire dsc_ch0_rd_fifo_valid; //channel 0 descriptor read FIFO data out valid
wire [122 : 0] dsc_ch0_rd_fifo_dout; //channel 0 descriptor read FIFO data out
wire dsc_ch0_rd_fifo_full; //channel 0 descriptor read FIFO full
wire dsc_ch0_rd_fifo_empty; //channel 0 descriptor read FIFO empty
wire [122 : 0] dsc_ch1_rd_fifo_din; //channel 1 descriptor read FIFO data in
wire dsc_ch1_rd_fifo_wr_en; //channel 1 descriptor read FIFO write enable
wire dsc_ch1_rd_fifo_rd_en; //channel 1 descriptor read FIFO read enable
wire dsc_ch1_rd_fifo_valid; //channel 1 descriptor read FIFO data out valid
wire [122 : 0] dsc_ch1_rd_fifo_dout; //channel 1 descriptor read FIFO data out
wire dsc_ch1_rd_fifo_full; //channel 1 descriptor read FIFO full
wire dsc_ch1_rd_fifo_empty; //channel 1 descriptor read FIFO empty
wire [122 : 0] dsc_ch2_rd_fifo_din; //channel 2 descriptor read FIFO data in
wire dsc_ch2_rd_fifo_wr_en; //channel 2 descriptor read FIFO write enable
wire dsc_ch2_rd_fifo_rd_en; //channel 2 descriptor read FIFO read enable
wire dsc_ch2_rd_fifo_valid; //channel 2 descriptor read FIFO data out valid
wire [122 : 0] dsc_ch2_rd_fifo_dout; //channel 2 descriptor read FIFO data out
wire dsc_ch2_rd_fifo_full; //channel 2 descriptor read FIFO full
wire dsc_ch2_rd_fifo_empty; //channel 2 descriptor read FIFO empty
wire [122 : 0] dsc_ch3_rd_fifo_din; //channel 3 descriptor read FIFO data in
wire dsc_ch3_rd_fifo_wr_en; //channel 3 descriptor read FIFO write enable
wire dsc_ch3_rd_fifo_rd_en; //channel 3 descriptor read FIFO read enable
wire dsc_ch3_rd_fifo_valid; //channel 3 descriptor read FIFO data out valid
wire [122 : 0] dsc_ch3_rd_fifo_dout; //channel 3 descriptor read FIFO data out
wire dsc_ch3_rd_fifo_full; //channel 3 descriptor read FIFO full
wire dsc_ch3_rd_fifo_empty; //channel 3 descriptor read FIFO empty
//--- AXI stream data ---
wire [AXIS_DATA_WIDTH-1 : 0] rdata_fifo_din; //AXI stream data FIFO in
wire rdata_fifo_wr_en; //AXI stream data FIFO write enable
wire rdata_fifo_rd_en; //AXI stream data FIFO read enable
wire rdata_fifo_valid; //AXI stream data FIFO out valid
wire [AXIS_DATA_WIDTH-1 : 0] rdata_fifo_dout; //AXI stream data FIFO out
wire rdata_fifo_full; //AXI stream data FIFO full
wire rdata_fifo_empty; //AXI stream data FIFO empty
wire [AXIS_ID_WIDTH + AXIS_DATA_WIDTH/8 : 0] rtag_fifo_din; //AXI stream data tag FIFO in
wire [AXIS_ID_WIDTH + AXIS_DATA_WIDTH/8 : 0] rtag_fifo_dout; //AXI stream data tag FIFO out
wire [AXIS_ID_WIDTH-1 : 0 ] rtag_fifo_tid; //AXI stream data tag FIFO out tid
wire [AXIS_DATA_WIDTH/8-1 :0 ] rtag_fifo_tkeep; //AXI stream data tag FIFO out tkeep
wire rtag_fifo_tlast; //AXI stream data tag FIFO out tlast
//--- Local write data ---
wire lcl_wr_done; //local write done
wire lcl_wr_data_ch0_valid; //channel 0 local write data valid
wire lcl_wr_data_ch1_valid; //channel 1 local write data valid
wire lcl_wr_data_ch2_valid; //channel 2 local write data valid
wire lcl_wr_data_ch3_valid; //channel 3 local write data valid
wire [ 3 : 0] lcl_wr_ctrl; //lcl write control
reg [27 : 0] sel_dsc_length; //Selected descriptor length
reg [63 : 0] sel_dsc_addr; //Selected descriptor addr
reg dsc_wr_first; //Descriptor lcl write first beat
reg [27 : 0] dsc_length_left; //Descriptor length left
reg [31 : 0] dsc_length_sum; //Descriptor write length sum
wire [31 : 0] dsc_length_sum_nxt; //Descriptor write length sum next
reg [63 : 0] dsc_cur_addr; //Descriptor lcl write addr
//--- Channel Descriptor Write FIFO ---
wire [127 : 0] dsc_ch0_wr_fifo_din; //channel 0 descriptor write FIFO data in
wire dsc_ch0_wr_fifo_wr_en; //channel 0 descriptor write FIFO write enable
wire dsc_ch0_wr_fifo_rd_en; //channel 0 descriptor write FIFO read enable
wire dsc_ch0_wr_fifo_valid; //channel 0 descriptor write FIFO data out valid
wire [127 : 0] dsc_ch0_wr_fifo_dout; //channel 0 descriptor write FIFO data out
wire dsc_ch0_wr_fifo_full; //channel 0 descriptor write FIFO full
wire dsc_ch0_wr_fifo_empty; //channel 0 descriptor write FIFO empty
wire [127 : 0] dsc_ch1_wr_fifo_din; //channel 1 descriptor write FIFO data in
wire dsc_ch1_wr_fifo_wr_en; //channel 1 descriptor write FIFO write enable
wire dsc_ch1_wr_fifo_rd_en; //channel 1 descriptor write FIFO read enable
wire dsc_ch1_wr_fifo_valid; //channel 1 descriptor write FIFO data out valid
wire [127 : 0] dsc_ch1_wr_fifo_dout; //channel 1 descriptor write FIFO data out
wire dsc_ch1_wr_fifo_full; //channel 1 descriptor write FIFO full
wire dsc_ch1_wr_fifo_empty; //channel 1 descriptor write FIFO empty
wire [127 : 0] dsc_ch2_wr_fifo_din; //channel 2 descriptor write FIFO data in
wire dsc_ch2_wr_fifo_wr_en; //channel 2 descriptor write FIFO write enable
wire dsc_ch2_wr_fifo_rd_en; //channel 2 descriptor write FIFO read enable
wire dsc_ch2_wr_fifo_valid; //channel 2 descriptor write FIFO data out valid
wire [127 : 0] dsc_ch2_wr_fifo_dout; //channel 2 descriptor write FIFO data out
wire dsc_ch2_wr_fifo_full; //channel 2 descriptor write FIFO full
wire dsc_ch2_wr_fifo_empty; //channel 2 descriptor write FIFO empty
wire [127 : 0] dsc_ch3_wr_fifo_din; //channel 3 descriptor write FIFO data in
wire dsc_ch3_wr_fifo_wr_en; //channel 3 descriptor write FIFO write enable
wire dsc_ch3_wr_fifo_rd_en; //channel 3 descriptor write FIFO read enable
wire dsc_ch3_wr_fifo_valid; //channel 3 descriptor write FIFO data out valid
wire [127 : 0] dsc_ch3_wr_fifo_dout; //channel 3 descriptor write FIFO data out
wire dsc_ch3_wr_fifo_full; //channel 3 descriptor write FIFO full
wire dsc_ch3_wr_fifo_empty; //channel 3 descriptor write FIFO empty
//--- Channel Write Resp Registers ---
wire dsc_ch0_rsp_fifo_din; //channel 0 descriptor write rsp FIFO data in
wire dsc_ch0_rsp_fifo_wr_en; //channel 0 descriptor write rsp FIFO write enable
wire dsc_ch0_rsp_fifo_rd_en; //channel 0 descriptor write rsp FIFO read enable
wire dsc_ch0_rsp_fifo_valid; //channel 0 descriptor write rsp FIFO data out valid
wire dsc_ch0_rsp_fifo_dout; //channel 0 descriptor write rsp FIFO data out
wire dsc_ch0_rsp_fifo_full; //channel 0 descriptor write rsp FIFO full
wire dsc_ch0_rsp_fifo_empty; //channel 0 descriptor write rsp FIFO empty
wire dsc_ch1_rsp_fifo_din; //channel 1 descriptor write rsp FIFO data in
wire dsc_ch1_rsp_fifo_wr_en; //channel 1 descriptor write rsp FIFO write enable
wire dsc_ch1_rsp_fifo_rd_en; //channel 1 descriptor write rsp FIFO read enable
wire dsc_ch1_rsp_fifo_valid; //channel 1 descriptor write rsp FIFO data out valid
wire dsc_ch1_rsp_fifo_dout; //channel 1 descriptor write rsp FIFO data out
wire dsc_ch1_rsp_fifo_full; //channel 1 descriptor write rsp FIFO full
wire dsc_ch1_rsp_fifo_empty; //channel 1 descriptor write rsp FIFO empty
wire dsc_ch2_rsp_fifo_din; //channel 2 descriptor write rsp FIFO data in
wire dsc_ch2_rsp_fifo_wr_en; //channel 2 descriptor write rsp FIFO write enable
wire dsc_ch2_rsp_fifo_rd_en; //channel 2 descriptor write rsp FIFO read enable
wire dsc_ch2_rsp_fifo_valid; //channel 2 descriptor write rsp FIFO data out valid
wire dsc_ch2_rsp_fifo_dout; //channel 2 descriptor write rsp FIFO data out
wire dsc_ch2_rsp_fifo_full; //channel 2 descriptor write rsp FIFO full
wire dsc_ch2_rsp_fifo_empty; //channel 2 descriptor write rsp FIFO empty
wire dsc_ch3_rsp_fifo_din; //channel 3 descriptor write rsp FIFO data in
wire dsc_ch3_rsp_fifo_wr_en; //channel 3 descriptor write rsp FIFO write enable
wire dsc_ch3_rsp_fifo_rd_en; //channel 3 descriptor write rsp FIFO read enable
wire dsc_ch3_rsp_fifo_valid; //channel 3 descriptor write rsp FIFO data out valid
wire dsc_ch3_rsp_fifo_dout; //channel 3 descriptor write rsp FIFO data out
wire dsc_ch3_rsp_fifo_full; //channel 3 descriptor write rsp FIFO full
wire dsc_ch3_rsp_fifo_empty; //channel 3 descriptor write rsp FIFO empty
//------------------------------------------------------------------------------
// Descriptor FIFO
//------------------------------------------------------------------------------
//---Descriptor FIFO(256b width x 8 depth)
// Xilinx IP: FWFT fifo
fifo_sync_256x8 dsc_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_fifo_din ),
.wr_en (dsc_fifo_wr_en),
.rd_en (dsc_fifo_rd_en),
.valid (dsc_fifo_valid),
.dout (dsc_fifo_dout ),
.full (dsc_fifo_full ),
.empty (dsc_fifo_empty)
);
// FIFO write
// write fifo when dsc valid
assign dsc_fifo_wr_en = dsc_valid;
assign dsc_fifo_din = dsc_data;
assign dsc_ready = ~dsc_fifo_full;
// decode dsc based on channel id, write into channel fifos
assign dsc_channel_id = dsc_fifo_valid ? dsc_fifo_dout[223:222] : 2'b0;
assign dsc_descriptor_id = dsc_fifo_valid ? dsc_fifo_dout[221:192] : 30'b0;
assign dsc_dst_addr = dsc_fifo_valid ? dsc_fifo_dout[191:128] : 64'b0;
assign dsc_length = dsc_fifo_valid ? dsc_fifo_dout[ 59: 32] : 28'b0;
assign dsc_intr = dsc_fifo_valid ? dsc_fifo_dout[1] : 1'b0;
assign dsc_info_data = {dsc_length, dsc_intr, dsc_descriptor_id, dsc_dst_addr};
assign dsc_ch0_rd_fifo_wr_en = dsc_fifo_valid & (dsc_channel_id==2'b00) & ~dsc_ch0_rd_fifo_full;
assign dsc_ch1_rd_fifo_wr_en = dsc_fifo_valid & (dsc_channel_id==2'b01) & ~dsc_ch1_rd_fifo_full;
assign dsc_ch2_rd_fifo_wr_en = dsc_fifo_valid & (dsc_channel_id==2'b10) & ~dsc_ch2_rd_fifo_full;
assign dsc_ch3_rd_fifo_wr_en = dsc_fifo_valid & (dsc_channel_id==2'b11) & ~dsc_ch3_rd_fifo_full;
assign dsc_ch0_rd_fifo_din = dsc_info_data;
assign dsc_ch1_rd_fifo_din = dsc_info_data;
assign dsc_ch2_rd_fifo_din = dsc_info_data;
assign dsc_ch3_rd_fifo_din = dsc_info_data;
assign dsc_fifo_rd_en = ~dsc_fifo_empty & (dsc_ch0_rd_fifo_wr_en | dsc_ch1_rd_fifo_wr_en | dsc_ch2_rd_fifo_wr_en | dsc_ch3_rd_fifo_wr_en);
//---Channel 0 receive stream data descriptor FIFO(123b width x 4 depth)
// 28b length + 1b intr + 30b id + 64b addr
// Xilinx IP: FWFT fifo
fifo_sync_123x4 dsc_ch0_rd_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch0_rd_fifo_din ),
.wr_en (dsc_ch0_rd_fifo_wr_en),
.rd_en (dsc_ch0_rd_fifo_rd_en),
.valid (dsc_ch0_rd_fifo_valid),
.dout (dsc_ch0_rd_fifo_dout ),
.full (dsc_ch0_rd_fifo_full ),
.empty (dsc_ch0_rd_fifo_empty)
);
//---Channel 1 receive stream data descriptor FIFO(123b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_123x4 dsc_ch1_rd_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch1_rd_fifo_din ),
.wr_en (dsc_ch1_rd_fifo_wr_en),
.rd_en (dsc_ch1_rd_fifo_rd_en),
.valid (dsc_ch1_rd_fifo_valid),
.dout (dsc_ch1_rd_fifo_dout ),
.full (dsc_ch1_rd_fifo_full ),
.empty (dsc_ch1_rd_fifo_empty)
);
//---Channel 2 receive stream data descriptor FIFO(123b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_123x4 dsc_ch2_rd_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch2_rd_fifo_din ),
.wr_en (dsc_ch2_rd_fifo_wr_en),
.rd_en (dsc_ch2_rd_fifo_rd_en),
.valid (dsc_ch2_rd_fifo_valid),
.dout (dsc_ch2_rd_fifo_dout ),
.full (dsc_ch2_rd_fifo_full ),
.empty (dsc_ch2_rd_fifo_empty)
);
//---Channel 3 receive stream data descriptor FIFO(123b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_123x4 dsc_ch3_rd_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch3_rd_fifo_din ),
.wr_en (dsc_ch3_rd_fifo_wr_en),
.rd_en (dsc_ch3_rd_fifo_rd_en),
.valid (dsc_ch3_rd_fifo_valid),
.dout (dsc_ch3_rd_fifo_dout ),
.full (dsc_ch3_rd_fifo_full ),
.empty (dsc_ch3_rd_fifo_empty)
);
//------------------------------------------------------------------------------
// AXI-Stream data
//------------------------------------------------------------------------------
// Stream data write into FIFO
assign rdata_fifo_wr_en = axis_tvalid & ~rdata_fifo_full;
assign rdata_fifo_din = axis_tdata;
assign rtag_fifo_din = {axis_tkeep, axis_tid, axis_tlast};
assign axis_tready = ~rdata_fifo_full;
assign rtag_fifo_tkeep = rtag_fifo_dout[AXIS_ID_WIDTH + AXIS_DATA_WIDTH/8 : AXIS_ID_WIDTH + 1];
assign rtag_fifo_tid = rtag_fifo_dout[AXIS_ID_WIDTH : 1];
assign rtag_fifo_tlast = rtag_fifo_dout[0];
`ifdef ACTION_DATA_WIDTH_512
// *****************************
// begin 512 bit AXI data width
// *****************************
reg [AXIS_DATA_WIDTH-1 : 0 ] axi_rdata_ch0_data; //channel 0 first beat AXI read data
reg axi_rdata_ch0_valid; //channel 0 first beat AXI read data valid
wire axi_rdata_ch0_wr; //channel 0 first beat AXI read data update
reg [AXIS_DATA_WIDTH-1 : 0 ] axi_rdata_ch1_data; //channel 1 first beat AXI read data
reg axi_rdata_ch1_valid; //channel 1 first beat AXI read data valid
wire axi_rdata_ch1_wr; //channel 1 first beat AXI read data update
reg [AXIS_DATA_WIDTH-1 : 0 ] axi_rdata_ch2_data; //channel 2 first beat AXI read data
reg axi_rdata_ch2_valid; //channel 2 first beat AXI read data valid
wire axi_rdata_ch2_wr; //channel 2 first beat AXI read data update
reg [AXIS_DATA_WIDTH-1 : 0 ] axi_rdata_ch3_data; //channel 3 first beat AXI read data
reg axi_rdata_ch3_valid; //channel 3 first beat AXI read data valid
wire axi_rdata_ch3_wr; //channel 3 first beat AXI read data update
wire axi_rdata_wr; //any channel first beat AXI read data update
wire axi_rdata_fifo_ch0_valid; //AXI read data fifo head data is channel 0
wire axi_rdata_fifo_ch1_valid; //AXI read data fifo head data is channel 1
wire axi_rdata_fifo_ch2_valid; //AXI read data fifo head data is channel 2
wire axi_rdata_fifo_ch3_valid; //AXI read data fifo head data is channel 3
wire lcl_ch0_wr_done; //channel 0 local write done
wire lcl_ch1_wr_done; //channel 1 local write done
wire lcl_ch2_wr_done; //channel 2 local write done
wire lcl_ch3_wr_done; //channel 3 local write done
wire lcl_wr_ch0_dsc_lower_half; //channel 0 last write beat data is first 512b on lcl write data bus
wire lcl_wr_ch1_dsc_lower_half; //channel 1 last write beat data is first 512b on lcl write data bus
wire lcl_wr_ch2_dsc_lower_half; //channel 2 last write beat data is first 512b on lcl write data bus
wire lcl_wr_ch3_dsc_lower_half; //channel 3 last write beat data is first 512b on lcl write data bus
wire lcl_wr_dsc_lower_half; //any channel last write beat data is first 512b on lcl write data bus
// first 512-bit AXI data (not rlast data) write into register
// rlast data will send to local bus if it is the first beat
// clear register when second 512-bit AXI data write done on
// local bus with the first 512-bit data
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
axi_rdata_ch0_valid <= 1'b0;
axi_rdata_ch0_data <= 512'b0;
end
else if(axi_rdata_ch0_wr) begin
axi_rdata_ch0_valid <= 1'b1;
axi_rdata_ch0_data <= rdata_fifo_dout;
end
else if(axi_rdata_ch0_valid & lcl_ch0_wr_done) begin
axi_rdata_ch0_valid <= 1'b0;
axi_rdata_ch0_data <= 512'b0;
end
else begin
axi_rdata_ch0_valid <= axi_rdata_ch0_valid;
axi_rdata_ch0_data <= axi_rdata_ch0_data;
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
axi_rdata_ch1_valid <= 1'b0;
axi_rdata_ch1_data <= 512'b0;
end
else if(axi_rdata_ch1_wr) begin
axi_rdata_ch1_valid <= 1'b1;
axi_rdata_ch1_data <= rdata_fifo_dout;
end
else if(axi_rdata_ch1_valid & lcl_ch1_wr_done) begin
axi_rdata_ch1_valid <= 1'b0;
axi_rdata_ch1_data <= 512'b0;
end
else begin
axi_rdata_ch1_valid <= axi_rdata_ch1_valid;
axi_rdata_ch1_data <= axi_rdata_ch1_data;
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
axi_rdata_ch2_valid <= 1'b0;
axi_rdata_ch2_data <= 512'b0;
end
else if(axi_rdata_ch2_wr) begin
axi_rdata_ch2_valid <= 1'b1;
axi_rdata_ch2_data <= rdata_fifo_dout;
end
else if(axi_rdata_ch2_valid & lcl_ch2_wr_done) begin
axi_rdata_ch2_valid <= 1'b0;
axi_rdata_ch2_data <= 512'b0;
end
else begin
axi_rdata_ch2_valid <= axi_rdata_ch2_valid;
axi_rdata_ch2_data <= axi_rdata_ch2_data;
end
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
axi_rdata_ch3_valid <= 1'b0;
axi_rdata_ch3_data <= 512'b0;
end
else if(axi_rdata_ch3_wr) begin
axi_rdata_ch3_valid <= 1'b1;
axi_rdata_ch3_data <= rdata_fifo_dout;
end
else if(axi_rdata_ch3_valid & lcl_ch3_wr_done) begin
axi_rdata_ch3_valid <= 1'b0;
axi_rdata_ch3_data <= 512'b0;
end
else begin
axi_rdata_ch3_valid <= axi_rdata_ch3_valid;
axi_rdata_ch3_data <= axi_rdata_ch3_data;
end
end
assign axi_rdata_fifo_ch0_valid = rdata_fifo_valid & (rtag_fifo_tid==5'd0);
assign axi_rdata_fifo_ch1_valid = rdata_fifo_valid & (rtag_fifo_tid==5'd1);
assign axi_rdata_fifo_ch2_valid = rdata_fifo_valid & (rtag_fifo_tid==5'd2);
assign axi_rdata_fifo_ch3_valid = rdata_fifo_valid & (rtag_fifo_tid==5'd3);
assign axi_rdata_ch0_wr = axi_rdata_fifo_ch0_valid & ~rtag_fifo_tlast & ~axi_rdata_ch0_valid;
assign axi_rdata_ch1_wr = axi_rdata_fifo_ch1_valid & ~rtag_fifo_tlast & ~axi_rdata_ch1_valid;
assign axi_rdata_ch2_wr = axi_rdata_fifo_ch2_valid & ~rtag_fifo_tlast & ~axi_rdata_ch2_valid;
assign axi_rdata_ch3_wr = axi_rdata_fifo_ch3_valid & ~rtag_fifo_tlast & ~axi_rdata_ch3_valid;
assign axi_rdata_wr = axi_rdata_ch0_wr | axi_rdata_ch1_wr | axi_rdata_ch2_wr | axi_rdata_ch3_wr;
// read fifo when first beat data write into register or second beat data
// write done on local bus
assign rdata_fifo_rd_en = ~rdata_fifo_empty & (axi_rdata_wr | lcl_wr_done);
//---AXI stream data FIFO(512b width x 8 depth)
// Xilinx IP: FWFT fifo
fifo_sync_512x8 rdata_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (rdata_fifo_din ),
.wr_en (rdata_fifo_wr_en),
.rd_en (rdata_fifo_rd_en),
.valid (rdata_fifo_valid),
.dout (rdata_fifo_dout ),
.full (rdata_fifo_full ),
.empty (rdata_fifo_empty)
);
//---AXI stream data tag FIFO(70b width x 8 depth)
// 64b tkeep + 5b tid + 1b tlast
// Xilinx IP: FWFT fifo
fifo_sync_70x8 rtag_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (rtag_fifo_din ),
.wr_en (rdata_fifo_wr_en),
.rd_en (rdata_fifo_rd_en),
.valid ( ),
.dout (rtag_fifo_dout ),
.full ( ),
.empty ( )
);
//--------------------------
// Local write command
//--------------------------
// ready to issue write cmd when two beat data for the same id are valid or end of packet
assign lcl_wr_data_ch0_valid = axi_rdata_fifo_ch0_valid & (axi_rdata_ch0_valid | rtag_fifo_tlast) & dsc_ch0_rd_fifo_valid;
assign lcl_wr_data_ch1_valid = axi_rdata_fifo_ch1_valid & (axi_rdata_ch1_valid | rtag_fifo_tlast) & dsc_ch1_rd_fifo_valid;
assign lcl_wr_data_ch2_valid = axi_rdata_fifo_ch2_valid & (axi_rdata_ch2_valid | rtag_fifo_tlast) & dsc_ch2_rd_fifo_valid;
assign lcl_wr_data_ch3_valid = axi_rdata_fifo_ch3_valid & (axi_rdata_ch3_valid | rtag_fifo_tlast) & dsc_ch3_rd_fifo_valid;
assign lcl_ch0_wr_done = lcl_wr_data_ch0_valid & lcl_wr_done;
assign lcl_ch1_wr_done = lcl_wr_data_ch1_valid & lcl_wr_done;
assign lcl_ch2_wr_done = lcl_wr_data_ch2_valid & lcl_wr_done;
assign lcl_ch3_wr_done = lcl_wr_data_ch3_valid & lcl_wr_done;
// check last beat data is the lower 512b half
assign lcl_wr_ch0_dsc_lower_half = axi_rdata_fifo_ch0_valid & rtag_fifo_tlast & ~axi_rdata_ch0_valid;
assign lcl_wr_ch1_dsc_lower_half = axi_rdata_fifo_ch1_valid & rtag_fifo_tlast & ~axi_rdata_ch1_valid;
assign lcl_wr_ch2_dsc_lower_half = axi_rdata_fifo_ch2_valid & rtag_fifo_tlast & ~axi_rdata_ch2_valid;
assign lcl_wr_ch3_dsc_lower_half = axi_rdata_fifo_ch3_valid & rtag_fifo_tlast & ~axi_rdata_ch3_valid;
assign lcl_wr_dsc_lower_half = lcl_wr_ch0_dsc_lower_half | lcl_wr_ch1_dsc_lower_half | lcl_wr_ch2_dsc_lower_half | lcl_wr_ch3_dsc_lower_half;
// generate lcl write data and be
assign lcl_wr_data = lcl_wr_dsc_lower_half ? {512'b0, rdata_fifo_dout}
: (lcl_wr_data_ch0_valid ? {rdata_fifo_dout, axi_rdata_ch0_data}
: (lcl_wr_data_ch1_valid ? {rdata_fifo_dout, axi_rdata_ch1_data}
: (lcl_wr_data_ch2_valid ? {rdata_fifo_dout, axi_rdata_ch2_data}
: (lcl_wr_data_ch3_valid ? {rdata_fifo_dout, axi_rdata_ch3_data} : 1024'b0))));
assign lcl_wr_be = lcl_wr_dsc_lower_half ? {64'b0, rtag_fifo_tkeep} : {64'hFFFFFFFF_FFFFFFFF, rtag_fifo_tkeep};
// *****************************
// end 512 bit AXI data width
// *****************************
`else
// *****************************
// begin 1024 bit AXI data width
// *****************************
//---AXI stream data FIFO(1024b width x 8 depth)
// Xilinx IP: FWFT fifo(FIFO IP max data width is 1024)
fifo_sync_1024x8 rdata_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (rdata_fifo_din ),
.wr_en (rdata_fifo_wr_en),
.rd_en (rdata_fifo_rd_en),
.valid (rdata_fifo_valid),
.dout (rdata_fifo_dout ),
.full (rdata_fifo_full ),
.empty (rdata_fifo_empty)
);
//---AXI stream data tag FIFO(134b width x 8 depth)
// 128b tkeep + 5b tid + 1b tlast
// Xilinx IP: FWFT fifo
fifo_sync_134x8 rtag_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (rtag_fifo_din ),
.wr_en (rdata_fifo_wr_en),
.rd_en (rdata_fifo_rd_en),
.valid ( ),
.dout (rtag_fifo_dout ),
.full ( ),
.empty ( )
);
assign rdata_fifo_rd_en = ~rdata_fifo_empty & lcl_wr_done;
//--------------------------
// Local write command
//--------------------------
assign lcl_wr_data_ch0_valid = rdata_fifo_valid & (rtag_fifo_tid == 5'd0) & dsc_ch0_rd_fifo_valid;
assign lcl_wr_data_ch1_valid = rdata_fifo_valid & (rtag_fifo_tid == 5'd1) & dsc_ch1_rd_fifo_valid;
assign lcl_wr_data_ch2_valid = rdata_fifo_valid & (rtag_fifo_tid == 5'd2) & dsc_ch2_rd_fifo_valid;
assign lcl_wr_data_ch3_valid = rdata_fifo_valid & (rtag_fifo_tid == 5'd3) & dsc_ch3_rd_fifo_valid;
assign lcl_wr_data = rdata_fifo_dout;
assign lcl_wr_be = rtag_fifo_tkeep;
// *****************************
// end 1024 bit AXI data width
// *****************************
`endif
// select different channel dsc length and addr
assign lcl_wr_ctrl = {lcl_wr_data_ch3_valid, lcl_wr_data_ch2_valid, lcl_wr_data_ch1_valid, lcl_wr_data_ch0_valid};
always@(*) begin
case(lcl_wr_ctrl)
4'b0001: begin
sel_dsc_length = dsc_ch0_rd_fifo_dout[122:95];
sel_dsc_addr = dsc_ch0_rd_fifo_dout[63:0];
end
4'b0010: begin
sel_dsc_length = dsc_ch1_rd_fifo_dout[122:95];
sel_dsc_addr = dsc_ch1_rd_fifo_dout[63:0];
end
4'b0100: begin
sel_dsc_length = dsc_ch2_rd_fifo_dout[122:95];
sel_dsc_addr = dsc_ch2_rd_fifo_dout[63:0];
end
4'b1000: begin
sel_dsc_length = dsc_ch3_rd_fifo_dout[122:95];
sel_dsc_addr = dsc_ch3_rd_fifo_dout[63:0];
end
default: begin
sel_dsc_length = 28'b0;
sel_dsc_addr = 64'b0;
end
endcase
end
// generate dsc lcl write first beat flag
always@(posedge clk or negedge rst_n) begin
if(~rst_n)
dsc_wr_first <= 1'b1;
else if(lcl_wr_last & lcl_wr_done)
dsc_wr_first <= 1'b1;
else if(dsc_wr_first & lcl_wr_done)
dsc_wr_first <= 1'b0;
else
dsc_wr_first <= dsc_wr_first;
end
always@(posedge clk or negedge rst_n) begin
if(~rst_n) begin
dsc_cur_addr <= 64'b0;
dsc_length_left <= 28'b0;
dsc_length_sum <= 32'b0;
end
else if(dsc_wr_first & lcl_wr_done) begin
dsc_cur_addr <= sel_dsc_addr + 8'd128;
dsc_length_left <= sel_dsc_length - 8'd128;
dsc_length_sum <= 32'd128;
end
else if(lcl_wr_done) begin
dsc_cur_addr <= dsc_cur_addr + 8'd128;
dsc_length_left <= dsc_length_left - 8'd128;
dsc_length_sum <= dsc_length_sum_nxt;
end
else begin
dsc_cur_addr <= dsc_cur_addr;
dsc_length_left <= dsc_length_left;
dsc_length_sum <= dsc_length_sum;
end
end
assign dsc_length_sum_nxt = dsc_length_sum + 8'd128;
// Generate local write signals
// Last beat when a descriptor is filled completely or closed due to an end of packet on the interface
assign lcl_wr_valid = (lcl_wr_data_ch0_valid & ~dsc_ch0_wr_fifo_full) | (lcl_wr_data_ch1_valid & ~dsc_ch1_wr_fifo_full)
| (lcl_wr_data_ch2_valid & ~dsc_ch2_wr_fifo_full) | (lcl_wr_data_ch3_valid & ~dsc_ch3_wr_fifo_full);
assign lcl_wr_ea = dsc_wr_first ? sel_dsc_addr : dsc_cur_addr;
assign lcl_wr_axi_id = {rtag_fifo_tid[1:0], `A2HST_ENGINE_ID};
assign lcl_wr_first = lcl_wr_valid & dsc_wr_first;
assign lcl_wr_last = lcl_wr_valid & (rtag_fifo_tlast | (dsc_wr_first & (sel_dsc_length == 28'd128)) | dsc_length_left == 28'd128);
// lcl ctx write cmd (not used for now)
assign lcl_wr_ctx_valid = 1'b0;
assign lcl_wr_ctx = 9'b0;
// read dsc read fifo, write into dsc write fifo when last beat write done
assign dsc_ch0_rd_fifo_rd_en = lcl_wr_data_ch0_valid & lcl_wr_last & lcl_wr_ready;
assign dsc_ch1_rd_fifo_rd_en = lcl_wr_data_ch1_valid & lcl_wr_last & lcl_wr_ready;
assign dsc_ch2_rd_fifo_rd_en = lcl_wr_data_ch2_valid & lcl_wr_last & lcl_wr_ready;
assign dsc_ch3_rd_fifo_rd_en = lcl_wr_data_ch3_valid & lcl_wr_last & lcl_wr_ready;
assign dsc_ch0_wr_fifo_wr_en = dsc_ch0_rd_fifo_rd_en;
assign dsc_ch1_wr_fifo_wr_en = dsc_ch1_rd_fifo_rd_en;
assign dsc_ch2_wr_fifo_wr_en = dsc_ch2_rd_fifo_rd_en;
assign dsc_ch3_wr_fifo_wr_en = dsc_ch3_rd_fifo_rd_en;
assign dsc_ch0_wr_fifo_din = {rtag_fifo_tlast, dsc_length_sum_nxt, dsc_ch0_rd_fifo_dout[94:0]};
assign dsc_ch1_wr_fifo_din = {rtag_fifo_tlast, dsc_length_sum_nxt, dsc_ch1_rd_fifo_dout[94:0]};
assign dsc_ch2_wr_fifo_din = {rtag_fifo_tlast, dsc_length_sum_nxt, dsc_ch2_rd_fifo_dout[94:0]};
assign dsc_ch3_wr_fifo_din = {rtag_fifo_tlast, dsc_length_sum_nxt, dsc_ch3_rd_fifo_dout[94:0]};
assign lcl_wr_done = lcl_wr_valid & lcl_wr_ready;
//---Channel 0 lcl write data done descriptor FIFO(128b width x 4 depth)
// 1b eop + 32b length + 1b intr + 30b id + 64b addr
// Xilinx IP: FWFT fifo
fifo_sync_128x4 dsc_ch0_wr_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch0_wr_fifo_din ),
.wr_en (dsc_ch0_wr_fifo_wr_en),
.rd_en (dsc_ch0_wr_fifo_rd_en),
.valid (dsc_ch0_wr_fifo_valid),
.dout (dsc_ch0_wr_fifo_dout ),
.full (dsc_ch0_wr_fifo_full ),
.empty (dsc_ch0_wr_fifo_empty)
);
//---Channel 1 lcl write data done descriptor FIFO(128b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_128x4 dsc_ch1_wr_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch1_wr_fifo_din ),
.wr_en (dsc_ch1_wr_fifo_wr_en),
.rd_en (dsc_ch1_wr_fifo_rd_en),
.valid (dsc_ch1_wr_fifo_valid),
.dout (dsc_ch1_wr_fifo_dout ),
.full (dsc_ch1_wr_fifo_full ),
.empty (dsc_ch1_wr_fifo_empty)
);
//---Channel 2 lcl write data done descriptor FIFO(128b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_128x4 dsc_ch2_wr_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch2_wr_fifo_din ),
.wr_en (dsc_ch2_wr_fifo_wr_en),
.rd_en (dsc_ch2_wr_fifo_rd_en),
.valid (dsc_ch2_wr_fifo_valid),
.dout (dsc_ch2_wr_fifo_dout ),
.full (dsc_ch2_wr_fifo_full ),
.empty (dsc_ch2_wr_fifo_empty)
);
//---Channel 3 lcl write data done descriptor FIFO(128b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_128x4 dsc_ch3_wr_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch3_wr_fifo_din ),
.wr_en (dsc_ch3_wr_fifo_wr_en),
.rd_en (dsc_ch3_wr_fifo_rd_en),
.valid (dsc_ch3_wr_fifo_valid),
.dout (dsc_ch3_wr_fifo_dout ),
.full (dsc_ch3_wr_fifo_full ),
.empty (dsc_ch3_wr_fifo_empty)
);
//------------------------------------------------------------------------------
// Local write response
//------------------------------------------------------------------------------
// always ready to receive write resp for now
assign lcl_wr_rsp_ready = 1'b1;
//---Channel 0 lcl write rsp descriptor FIFO(1b width x 4 depth)
// 1b rsp error
// Xilinx IP: FWFT fifo
fifo_sync_1x4 dsc_ch0_rsp_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch0_rsp_fifo_din ),
.wr_en (dsc_ch0_rsp_fifo_wr_en),
.rd_en (dsc_ch0_rsp_fifo_rd_en),
.valid (dsc_ch0_rsp_fifo_valid),
.dout (dsc_ch0_rsp_fifo_dout ),
.full (dsc_ch0_rsp_fifo_full ),
.empty (dsc_ch0_rsp_fifo_empty)
);
//---Channel 1 lcl write rsp descriptor FIFO(1b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_1x4 dsc_ch1_rsp_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch1_rsp_fifo_din ),
.wr_en (dsc_ch1_rsp_fifo_wr_en),
.rd_en (dsc_ch1_rsp_fifo_rd_en),
.valid (dsc_ch1_rsp_fifo_valid),
.dout (dsc_ch1_rsp_fifo_dout ),
.full (dsc_ch1_rsp_fifo_full ),
.empty (dsc_ch1_rsp_fifo_empty)
);
//---Channel 2 lcl write rsp descriptor FIFO(1b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_1x4 dsc_ch2_rsp_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch2_rsp_fifo_din ),
.wr_en (dsc_ch2_rsp_fifo_wr_en),
.rd_en (dsc_ch2_rsp_fifo_rd_en),
.valid (dsc_ch2_rsp_fifo_valid),
.dout (dsc_ch2_rsp_fifo_dout ),
.full (dsc_ch2_rsp_fifo_full ),
.empty (dsc_ch2_rsp_fifo_empty)
);
//---Channel 3 lcl write rsp descriptor FIFO(1b width x 4 depth)
// Xilinx IP: FWFT fifo
fifo_sync_1x4 dsc_ch3_rsp_fifo (
.clk (clk ),
.srst (~rst_n ),
.din (dsc_ch3_rsp_fifo_din ),
.wr_en (dsc_ch3_rsp_fifo_wr_en),
.rd_en (dsc_ch3_rsp_fifo_rd_en),
.valid (dsc_ch3_rsp_fifo_valid),
.dout (dsc_ch3_rsp_fifo_dout ),
.full (dsc_ch3_rsp_fifo_full ),
.empty (dsc_ch3_rsp_fifo_empty)
);
assign dsc_ch0_rsp_fifo_wr_en = lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id[4:3] == 2'b00) & ~dsc_ch0_rsp_fifo_full;
assign dsc_ch1_rsp_fifo_wr_en = lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id[4:3] == 2'b01) & ~dsc_ch0_rsp_fifo_full;
assign dsc_ch2_rsp_fifo_wr_en = lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id[4:3] == 2'b10) & ~dsc_ch0_rsp_fifo_full;
assign dsc_ch3_rsp_fifo_wr_en = lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id[4:3] == 2'b11) & ~dsc_ch0_rsp_fifo_full;
assign dsc_ch0_rsp_fifo_din = lcl_wr_rsp_code;
assign dsc_ch1_rsp_fifo_din = lcl_wr_rsp_code;
assign dsc_ch2_rsp_fifo_din = lcl_wr_rsp_code;
assign dsc_ch3_rsp_fifo_din = lcl_wr_rsp_code;
//------------------------------------------------------------------------------
// Commit to complete engine
//------------------------------------------------------------------------------
// commit when dsc wr and rsp fifo valid
assign dsc_ch0_cmp_valid = dsc_ch0_wr_fifo_valid & dsc_ch0_rsp_fifo_valid;
assign dsc_ch1_cmp_valid = dsc_ch1_wr_fifo_valid & dsc_ch1_rsp_fifo_valid;
assign dsc_ch2_cmp_valid = dsc_ch2_wr_fifo_valid & dsc_ch2_rsp_fifo_valid;
assign dsc_ch3_cmp_valid = dsc_ch3_wr_fifo_valid & dsc_ch3_rsp_fifo_valid;
assign dsc_ch0_cmp_data = {dsc_ch0_wr_fifo_dout[126:95],
16'h52b4, 15'b0, dsc_ch0_wr_fifo_dout[127],
126'b0,
1'b0, dsc_ch0_rsp_fifo_dout,
dsc_ch0_wr_fifo_dout[63:0],
221'b0,
dsc_ch0_wr_fifo_dout[94],
2'b00,
dsc_ch0_wr_fifo_dout[93:64],
1'b1,
dsc_ch0_rsp_fifo_dout};
assign dsc_ch1_cmp_data = {dsc_ch1_wr_fifo_dout[126:95],
16'h52b4, 15'b0, dsc_ch1_wr_fifo_dout[127],
126'b0,
1'b0, dsc_ch1_rsp_fifo_dout,
dsc_ch1_wr_fifo_dout[63:0],
221'b0,
dsc_ch1_wr_fifo_dout[94],
2'b00,
dsc_ch1_wr_fifo_dout[93:64],
1'b1,
dsc_ch1_rsp_fifo_dout};
assign dsc_ch2_cmp_data = {dsc_ch2_wr_fifo_dout[126:95],
16'h52b4, 15'b0, dsc_ch2_wr_fifo_dout[127],
126'b0,
1'b0, dsc_ch2_rsp_fifo_dout,
dsc_ch2_wr_fifo_dout[63:0],
221'b0,
dsc_ch2_wr_fifo_dout[94],
2'b00,
dsc_ch2_wr_fifo_dout[93:64],
1'b1,
dsc_ch2_rsp_fifo_dout};
assign dsc_ch3_cmp_data = {dsc_ch3_wr_fifo_dout[126:95],
16'h52b4, 15'b0, dsc_ch3_wr_fifo_dout[127],
126'b0,
1'b0, dsc_ch3_rsp_fifo_dout,
dsc_ch3_wr_fifo_dout[63:0],
221'b0,
dsc_ch3_wr_fifo_dout[94],
2'b00,
dsc_ch3_wr_fifo_dout[93:64],
1'b1,
dsc_ch3_rsp_fifo_dout};
// read dsc wr and rsp fifo when commit done
assign dsc_ch0_wr_fifo_rd_en = dsc_ch0_cmp_valid & dsc_ch0_cmp_ready;
assign dsc_ch1_wr_fifo_rd_en = dsc_ch1_cmp_valid & dsc_ch1_cmp_ready;
assign dsc_ch2_wr_fifo_rd_en = dsc_ch2_cmp_valid & dsc_ch2_cmp_ready;
assign dsc_ch3_wr_fifo_rd_en = dsc_ch3_cmp_valid & dsc_ch3_cmp_ready;
assign dsc_ch0_rsp_fifo_rd_en = dsc_ch0_cmp_valid & dsc_ch0_cmp_ready;
assign dsc_ch1_rsp_fifo_rd_en = dsc_ch1_cmp_valid & dsc_ch1_cmp_ready;
assign dsc_ch2_rsp_fifo_rd_en = dsc_ch2_cmp_valid & dsc_ch2_cmp_ready;
assign dsc_ch3_rsp_fifo_rd_en = dsc_ch3_cmp_valid & dsc_ch3_cmp_ready;
endmodule |
module odma_completion_manager (
input clk ,
input rst_n ,
//interrupt
input action_interrupt ,
input [8:0] action_interrupt_ctx,
input [63:0] action_interrupt_src,
output action_interrupt_ack,
output reg odma_interrupt ,
output [8:0] odma_interrupt_ctx ,
output reg [63:0] odma_interrupt_src ,
input odma_interrupt_ack ,
//configuration
input [63:0] completion_addr0,
input [31:0] completion_size0,
input [63:0] completion_addr1,
input [31:0] completion_size1,
input [63:0] completion_addr2,
input [31:0] completion_size2,
input [63:0] completion_addr3,
input [31:0] completion_size3,
output [63:0] completion_error,
output [3:0] completion_done ,
input [63:0] cmp_ch0_obj_handle,
input [63:0] cmp_ch1_obj_handle,
input [63:0] cmp_ch2_obj_handle,
input [63:0] cmp_ch3_obj_handle,
//engine
input [15:0] eng_cmp_done ,
output [15:0] eng_cmp_okay ,
input [511:0] eng_cmp_data00 ,
input [511:0] eng_cmp_data01 ,
input [511:0] eng_cmp_data02 ,
input [511:0] eng_cmp_data03 ,
input [511:0] eng_cmp_data10 ,
input [511:0] eng_cmp_data11 ,
input [511:0] eng_cmp_data12 ,
input [511:0] eng_cmp_data13 ,
input [511:0] eng_cmp_data20 ,
input [511:0] eng_cmp_data21 ,
input [511:0] eng_cmp_data22 ,
input [511:0] eng_cmp_data23 ,
input [511:0] eng_cmp_data30 ,
input [511:0] eng_cmp_data31 ,
input [511:0] eng_cmp_data32 ,
input [511:0] eng_cmp_data33 ,
//write
output lcl_wr_valid ,
output [63:0] lcl_wr_ea ,
output [4:0] lcl_wr_axi_id ,
output [127:0] lcl_wr_be ,
output lcl_wr_first ,
output lcl_wr_last ,
output [1023:0] lcl_wr_data ,
output lcl_wr_ctx_valid,
output [8:0] lcl_wr_ctx ,
input lcl_wr_ready ,
input lcl_wr_rsp_valid,
input [4:0] lcl_wr_rsp_axi_id,
input lcl_wr_rsp_code ,
output lcl_wr_rsp_ready,
//descriptor
input [3:0] channel_done ,
input [29:0] channel_id0 ,
input [29:0] channel_id1 ,
input [29:0] channel_id2 ,
input [29:0] channel_id3 ,
input [3:0] manager_start_w
);
reg write_start;
reg [63:0] write_address;
reg [1023:0] write_data;
reg [1:0] write_channel;
reg [3:0] channel_done_r;
reg [1:0] write_request0;
reg in_write0;
reg [31:0] waddr_offside0;
reg [511:0] channel0_buf;
reg [29:0] channel_cnt0;
reg [1:0] write_request1;
reg in_write1;
reg [31:0] waddr_offside1;
reg [511:0] channel1_buf;
reg [29:0] channel_cnt1;
reg [1:0] write_request2;
reg in_write2;
reg [31:0] waddr_offside2;
reg [511:0] channel2_buf;
reg [29:0] channel_cnt2;
reg [1:0] write_request3;
reg in_write3;
reg [31:0] waddr_offside3;
reg [511:0] channel3_buf;
reg [29:0] channel_cnt3;
reg interrupt_source; //0:odma 1:action
reg interrupt0_req;
reg interrupt1_req;
reg interrupt2_req;
reg interrupt3_req;
reg interrupt_req;
wire interrupt_ack;
reg [1:0] interrupt_channel;
//interrupt related
assign interrupt_ack = odma_interrupt_ack & !interrupt_source;
assign action_interrupt_ack = odma_interrupt_ack & interrupt_source;
assign odma_interrupt_ctx = interrupt_source ? action_interrupt_ctx : 9'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
odma_interrupt <= 1'b0;
else if(odma_interrupt_ack)
odma_interrupt <= 1'b0;
else if(interrupt_req | action_interrupt)
odma_interrupt <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt_source <= 1'b0;
else if(odma_interrupt_ack)
interrupt_source <= 1'b0;
else if(action_interrupt & !interrupt_req)
interrupt_source <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt0_req <= 1'b0;
else if(interrupt_ack & (interrupt_channel == 2'b00))
interrupt0_req <= 1'b0;
else if(channel0_buf[34])
interrupt0_req <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt1_req <= 1'b0;
else if(interrupt_ack & (interrupt_channel == 2'b01))
interrupt1_req <= 1'b0;
else if(channel1_buf[34])
interrupt1_req <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt2_req <= 1'b0;
else if(interrupt_ack & (interrupt_channel == 2'b10))
interrupt2_req <= 1'b0;
else if(channel2_buf[34])
interrupt2_req <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt3_req <= 1'b0;
else if(interrupt_ack & (interrupt_channel == 2'b11))
interrupt3_req <= 1'b0;
else if(channel3_buf[34])
interrupt3_req <= 1'b1;
always@(*)
if(!interrupt_source)
case(interrupt_channel)
2'b00: odma_interrupt_src = cmp_ch0_obj_handle;
2'b01: odma_interrupt_src = cmp_ch1_obj_handle;
2'b10: odma_interrupt_src = cmp_ch2_obj_handle;
2'b11: odma_interrupt_src = cmp_ch3_obj_handle;
endcase
else
odma_interrupt_src = action_interrupt_src;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt_channel <= 2'b00;
else if(interrupt_req)
interrupt_channel <= interrupt_channel;
else if(interrupt0_req)
interrupt_channel <= 2'b00;
else if(interrupt1_req)
interrupt_channel <= 2'b01;
else if(interrupt2_req)
interrupt_channel <= 2'b10;
else if(interrupt3_req)
interrupt_channel <= 2'b11;
always@(posedge clk or negedge rst_n)
if(!rst_n)
interrupt_req <= 1'b0;
else if(interrupt_ack)
interrupt_req <= 1'b0;
else if(interrupt0_req | interrupt1_req | interrupt2_req | interrupt3_req)
interrupt_req <= 1'b1;
//lcl write
assign lcl_wr_first = lcl_wr_valid;
assign lcl_wr_last = lcl_wr_valid;
assign lcl_wr_valid = write_start;
assign lcl_wr_be = 128'hffffffffffffffffffffffffffffffff;
assign lcl_wr_ea = write_address;
assign lcl_wr_data = write_data;
assign lcl_wr_axi_id = {write_channel,3'b101};
assign lcl_wr_ctx_valid = 1'b0;
assign lcl_wr_ctx = 9'b0;
assign lcl_wr_rsp_ready = 1'b1;
assign completion_error = 64'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_done_r[3] <= 1'b0;
else if(manager_start_w[3])
channel_done_r[3] <= 1'b0;
else if(channel_done[3])
channel_done_r[3] <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_done_r[2] <= 1'b0;
else if(manager_start_w[2])
channel_done_r[2] <= 1'b0;
else if(channel_done[2])
channel_done_r[2] <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_done_r[1] <= 1'b0;
else if(manager_start_w[1])
channel_done_r[1] <= 1'b0;
else if(channel_done[1])
channel_done_r[1] <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_done_r[0] <= 1'b0;
else if(manager_start_w[0])
channel_done_r[0] <= 1'b0;
else if(channel_done[0])
channel_done_r[0] <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_start <= 1'b0;
else if(lcl_wr_valid & lcl_wr_ready)
write_start <= 1'b0;
else if(write_request0 || write_request1 || write_request2 || write_request3)
write_start <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_channel <= 2'b00;
else if(write_start)
write_channel <= write_channel;
else if(write_request0 != 2'b00)
write_channel <= 2'b00;
else if(write_request1 != 2'b00)
write_channel <= 2'b01;
else if(write_request2 != 2'b00)
write_channel <= 2'b10;
else if(write_request3 != 2'b00)
write_channel <= 2'b11;
always@(*)
if(!rst_n)
write_address = 64'd0;
else case(write_channel)
2'b00: write_address = completion_addr0;// + waddr_offside0;
2'b01: write_address = completion_addr1;// + waddr_offside1;
2'b10: write_address = completion_addr2;// + waddr_offside2;
2'b11: write_address = completion_addr3;// + waddr_offside3;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_data = 1024'd0;
else case(write_channel)
2'b00: write_data = {channel0_buf,482'b0,channel_cnt0};
2'b01: write_data = {channel1_buf,482'b0,channel_cnt1};
2'b10: write_data = {channel2_buf,482'b0,channel_cnt2};
2'b11: write_data = {channel3_buf,482'b0,channel_cnt3};
endcase
//channel 0
assign completion_done[0] = (channel_cnt0 > channel_id0) & channel_done_r[0];
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_request0 <= 2'b0;
else if ((eng_cmp_okay[0] | eng_cmp_okay[4] | eng_cmp_okay[8] | eng_cmp_okay[12]) & (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b00)))
write_request0 <= write_request0;
else if (eng_cmp_okay[0] | eng_cmp_okay[4] | eng_cmp_okay[8] | eng_cmp_okay[12])
write_request0 <= write_request0 + 1'b1;
else if (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b00))
write_request0 <= write_request0 - 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
waddr_offside0 <= 'd0;
else if (lcl_wr_rsp_valid & !lcl_wr_rsp_code & (lcl_wr_rsp_axi_id == 5'b00101))
waddr_offside0 <= waddr_offside0 + 'd128;
else if(waddr_offside0 == completion_size0)
waddr_offside0 <= 'd0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_write0 <= 1'b0;
else if(write_start & (write_channel == 2'b00))
in_write0 <= 1'b1;
else if(lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id == 5'b00101))
in_write0 <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel0_buf <= 512'b0;
else if(eng_cmp_okay[0])
channel0_buf <= eng_cmp_data00;
else if(eng_cmp_okay[4])
channel0_buf <= eng_cmp_data10;
else if(eng_cmp_okay[8])
channel0_buf <= eng_cmp_data20;
else if(eng_cmp_okay[12])
channel0_buf <= eng_cmp_data30;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_cnt0 <= 'd0;
else if(manager_start_w[0])
channel_cnt0 <= 'd1;
else if(lcl_wr_valid & (lcl_wr_axi_id == 5'b00101) & lcl_wr_ready)
channel_cnt0 <= channel_cnt0 + 1'b1;
//channel 1
assign completion_done[1] = (channel_cnt1 > channel_id1) & channel_done_r[1];
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_request1 <= 2'b00;
else if ((eng_cmp_okay[1] | eng_cmp_okay[5] | eng_cmp_okay[9] | eng_cmp_okay[13]) & (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b01)))
write_request1 <= write_request1;
else if (eng_cmp_okay[1] | eng_cmp_okay[5] | eng_cmp_okay[9] | eng_cmp_okay[13])
write_request1 <= write_request1 + 1'b1;
else if (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b01))
write_request1 <= write_request1 - 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
waddr_offside1 <= 'd0;
else if (lcl_wr_rsp_valid & !lcl_wr_rsp_code & (lcl_wr_rsp_axi_id == 5'b01101))
waddr_offside1 <= waddr_offside1 + 'd128;
else if(waddr_offside1 == completion_size1)
waddr_offside1 <= 'd0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel1_buf <= 512'b0;
else if(eng_cmp_okay[1])
channel1_buf <= eng_cmp_data01;
else if(eng_cmp_okay[5])
channel1_buf <= eng_cmp_data11;
else if(eng_cmp_okay[9])
channel1_buf <= eng_cmp_data21;
else if(eng_cmp_okay[13])
channel1_buf <= eng_cmp_data31;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_cnt1 <= 'd0;
else if(manager_start_w[1])
channel_cnt1 <= 'd1;
else if(lcl_wr_valid & (lcl_wr_axi_id == 5'b01101) & lcl_wr_ready)
channel_cnt1 <= channel_cnt1 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_write1 <= 1'b0;
else if(write_start & (write_channel == 2'b01))
in_write1 <= 1'b1;
else if(lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id == 5'b01101))
in_write1 <= 1'b0;
//channel 2
assign completion_done[2] = (channel_cnt2 > channel_id2) & channel_done_r[2];
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_request2 <= 2'b00;
else if ((eng_cmp_okay[2] | eng_cmp_okay[6] | eng_cmp_okay[10] | eng_cmp_okay[14]) & (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b10)))
write_request2 <= write_request2;
else if (eng_cmp_okay[2] | eng_cmp_okay[6] | eng_cmp_okay[10] | eng_cmp_okay[14])
write_request2 <= write_request2 + 1'b1;
else if (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b10))
write_request2 <= write_request2 - 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
waddr_offside2 <= 'd0;
else if (lcl_wr_rsp_valid & !lcl_wr_rsp_code & (lcl_wr_rsp_axi_id == 5'b10101))
waddr_offside2 <= waddr_offside2 + 'd128;
else if(waddr_offside2 == completion_size2)
waddr_offside2 <= 'd0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel2_buf <= 512'b0;
else if(eng_cmp_okay[2])
channel2_buf <= eng_cmp_data02;
else if(eng_cmp_okay[6])
channel2_buf <= eng_cmp_data12;
else if(eng_cmp_okay[10])
channel2_buf <= eng_cmp_data22;
else if(eng_cmp_okay[14])
channel2_buf <= eng_cmp_data32;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_cnt2 <= 'd0;
else if(manager_start_w[2])
channel_cnt2 <= 'd1;
else if(lcl_wr_valid & (lcl_wr_axi_id == 5'b10101) & lcl_wr_ready)
channel_cnt2 <= channel_cnt2 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_write2 <= 1'b0;
else if(write_start & (write_channel == 2'b10))
in_write2 <= 1'b1;
else if(lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id == 5'b10101))
in_write2 <= 1'b0;
//channel 3
assign completion_done[3] = (channel_cnt3 > channel_id3) & channel_done_r[3];
always@(posedge clk or negedge rst_n)
if(!rst_n)
waddr_offside3 <= 'd0;
else if (lcl_wr_rsp_valid & !lcl_wr_rsp_code & (lcl_wr_rsp_axi_id == 5'b11101))
waddr_offside3 <= waddr_offside3 + 'd128;
else if(waddr_offside3 == completion_size3)
waddr_offside3 <= 'd0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel3_buf <= 512'b0;
else if(eng_cmp_okay[3])
channel3_buf <= eng_cmp_data03;
else if(eng_cmp_okay[7])
channel3_buf <= eng_cmp_data13;
else if(eng_cmp_okay[11])
channel3_buf <= eng_cmp_data23;
else if(eng_cmp_okay[15])
channel3_buf <= eng_cmp_data33;
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_cnt3 <= 'd0;
else if(manager_start_w[3])
channel_cnt3 <= 'd1;
else if(lcl_wr_valid & (lcl_wr_axi_id == 5'b11101) & lcl_wr_ready)
channel_cnt3 <= channel_cnt3 + 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
write_request3 <= 2'b00;
else if ((eng_cmp_okay[3] | eng_cmp_okay[7] | eng_cmp_okay[11] | eng_cmp_okay[15]) & (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b11)))
write_request3 <= write_request3;
else if (eng_cmp_okay[3] | eng_cmp_okay[7] | eng_cmp_okay[11] | eng_cmp_okay[15])
write_request3 <= write_request3 + 1'b1;
else if (lcl_wr_valid & lcl_wr_ready & (write_channel == 2'b11))
write_request3 <= write_request3 - 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_write3 <= 1'b0;
else if(write_start & (write_channel == 2'b11))
in_write3 <= 1'b1;
else if(lcl_wr_rsp_valid & (lcl_wr_rsp_axi_id == 5'b11101))
in_write3 <= 1'b0;
//engine
assign eng_cmp_okay[0] = eng_cmp_done[0] & !write_request0;
assign eng_cmp_okay[1] = eng_cmp_done[1] & !write_request1;
assign eng_cmp_okay[2] = eng_cmp_done[2] & !write_request2;
assign eng_cmp_okay[3] = eng_cmp_done[3] & !write_request3;
assign eng_cmp_okay[4] = eng_cmp_done[4] & !write_request0;
assign eng_cmp_okay[5] = eng_cmp_done[5] & !write_request1;
assign eng_cmp_okay[6] = eng_cmp_done[6] & !write_request2;
assign eng_cmp_okay[7] = eng_cmp_done[7] & !write_request3;
assign eng_cmp_okay[8] = eng_cmp_done[8] & !write_request0;
assign eng_cmp_okay[9] = eng_cmp_done[9] & !write_request1;
assign eng_cmp_okay[10] = eng_cmp_done[10] & !write_request2;
assign eng_cmp_okay[11] = eng_cmp_done[11] & !write_request3;
assign eng_cmp_okay[12] = eng_cmp_done[12] & !write_request0;
assign eng_cmp_okay[13] = eng_cmp_done[13] & !write_request1;
assign eng_cmp_okay[14] = eng_cmp_done[14] & !write_request2;
assign eng_cmp_okay[15] = eng_cmp_done[15] & !write_request3;
endmodule |
module odma_lcl_rd_arbiter #(
parameter AXI_ID_WIDTH = 5
)
(
input clk ,
input rst_n ,
//--------------- LCL Read Interface ------------------//
//-------------- Read Addr/Req Channel ----------------//
output reg lcl_rd_valid ,
output reg [0063:0] lcl_rd_ea ,
output reg [AXI_ID_WIDTH - 1:0] lcl_rd_axi_id ,
output reg lcl_rd_first ,
output reg lcl_rd_last ,
output reg [0127:0] lcl_rd_be ,
output reg [0008:0] lcl_rd_ctx ,
output reg lcl_rd_ctx_valid ,
input lcl_rd_ready ,
//-------------- Read Data/Resp Channel-----------------//
input lcl_rd_data_valid ,
input [1023:0] lcl_rd_data ,
input [AXI_ID_WIDTH - 1:0] lcl_rd_data_axi_id ,
input lcl_rd_data_last ,
input lcl_rd_rsp_code ,
output [0031:0] lcl_rd_rsp_ready ,
output [0031:0] lcl_rd_rsp_ready_hint ,
//-------------- DSC Engine LCL Rd IF ------------------//
//-------------- Read Addr/Req Channel -----------------//
input dsc_lcl_rd_valid ,
input [0063:0] dsc_lcl_rd_ea ,
input [AXI_ID_WIDTH - 1:0] dsc_lcl_rd_axi_id ,
input dsc_lcl_rd_first ,
input dsc_lcl_rd_last ,
input [0127:0] dsc_lcl_rd_be ,
input [0008:0] dsc_lcl_rd_ctx ,
input dsc_lcl_rd_ctx_valid ,
output dsc_lcl_rd_ready ,
//-------------- Read Data/Resp Channel-----------------//
output reg dsc_lcl_rd_data_valid ,
output reg [1023:0] dsc_lcl_rd_data ,
output reg [AXI_ID_WIDTH - 1:0] dsc_lcl_rd_data_axi_id ,
output reg dsc_lcl_rd_data_last ,
output reg dsc_lcl_rd_rsp_code ,
input dsc_lcl_rd_rsp_ready ,
input dsc_lcl_rd_rsp_ready_hint,
//------------ H2A MM Engine LCL Rd IF -----------------//
//-------------- Read Addr/Req Channel -----------------//
input mm_lcl_rd_valid ,
input [0063:0] mm_lcl_rd_ea ,
input [AXI_ID_WIDTH - 1:0] mm_lcl_rd_axi_id ,
input mm_lcl_rd_first ,
input mm_lcl_rd_last ,
input [0127:0] mm_lcl_rd_be ,
input [0008:0] mm_lcl_rd_ctx ,
input mm_lcl_rd_ctx_valid ,
output mm_lcl_rd_ready ,
//-------------- Read Data/Resp Channel-----------------//
output reg mm_lcl_rd_data_valid ,
output reg [1023:0] mm_lcl_rd_data ,
output reg [AXI_ID_WIDTH - 1:0] mm_lcl_rd_data_axi_id ,
output reg mm_lcl_rd_data_last ,
output reg mm_lcl_rd_rsp_code ,
input [0003:0] mm_lcl_rd_rsp_ready ,
input [0003:0] mm_lcl_rd_rsp_ready_hint,
//------------ H2A ST Engine LCL Rd IF -----------------//
//-------------- Read Addr/Req Channel -----------------//
input st_lcl_rd_valid ,
input [0063:0] st_lcl_rd_ea ,
input [AXI_ID_WIDTH - 1:0] st_lcl_rd_axi_id ,
input st_lcl_rd_first ,
input st_lcl_rd_last ,
input [0127:0] st_lcl_rd_be ,
input [0008:0] st_lcl_rd_ctx ,
input st_lcl_rd_ctx_valid ,
output st_lcl_rd_ready ,
//-------------- Read Data/Resp Channel-----------------//
output reg st_lcl_rd_data_valid ,
output reg [1023:0] st_lcl_rd_data ,
output reg [AXI_ID_WIDTH - 1:0] st_lcl_rd_data_axi_id ,
output reg st_lcl_rd_data_last ,
output reg st_lcl_rd_rsp_code ,
input st_lcl_rd_rsp_ready ,
input st_lcl_rd_rsp_ready_hint
);
/////////////////////////////
//
// For debug
//
/////////////////////////////
reg [27:0] lcl_rd_cnt;
reg [27:0] lcl_rd_data_cnt;
always @(posedge clk or negedge rst_n)
if (!rst_n)
lcl_rd_cnt <= 28'd0;
else if (lcl_rd_valid && lcl_rd_ready && (lcl_rd_axi_id == 5'b11010))
lcl_rd_cnt <= (lcl_rd_last)? 28'd0 : lcl_rd_cnt + 1;
else
lcl_rd_cnt <= lcl_rd_cnt;
always @(posedge clk or negedge rst_n)
if (!rst_n)
lcl_rd_data_cnt <= 28'd0;
else if (lcl_rd_data_valid && lcl_rd_rsp_ready && (lcl_rd_data_axi_id == 5'b11010))
lcl_rd_data_cnt <= (lcl_rd_data_last)? 28'd0 : lcl_rd_data_cnt + 1;
else
lcl_rd_data_cnt <= lcl_rd_data_cnt;
reg rd_req_dsc_grant;
reg rd_req_mm_grant;
reg rd_req_st_grant;
reg rd_req_arb_en;
reg rd_req_arb_en_extend;
reg no_arb;
wire no_valid;
// Read Requester Channel
// rd_req_arbiter
// if the rd_req_arb_en is high, the arbiter will follow the priority that DSC Engine > MM Engine > ST Engine
// if the rd_req_arb_en_extend is high, the arbiter will give the highest priority to current engine
// When both rd_req_arb_en and no_arb are high, the rd_req_arb_en_extend will be pulled up
// no_arb: 1) value 1'b1 means that the granter does not change when rd_req_arb_en is high.
// 2) value 1'b0 means that the granter changes whne rd_req_arb_en is high.
// for rd_req_dsc_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
rd_req_dsc_grant <= 1'b0;
else if (rd_req_arb_en)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: rd_req_dsc_grant <= (dsc_lcl_rd_valid)? 1'b1 : 1'b0;
3'b100: rd_req_dsc_grant <= (mm_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b0 : 1'b1);
3'b010: rd_req_dsc_grant <= (dsc_lcl_rd_valid)? 1'b1 : 1'b0;
3'b001: rd_req_dsc_grant <= (dsc_lcl_rd_valid)? 1'b1 : 1'b0;
default:;
endcase
else if (rd_req_arb_en_extend)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
//3'b000: rd_req_dsc_grant <= (dsc_lcl_rd_valid)? 1'b1 : 1'b0;
3'b100: rd_req_dsc_grant <= (dsc_lcl_rd_valid)? 1'b1 : 1'b0;
3'b010: rd_req_dsc_grant <= (mm_lcl_rd_valid)? 1'b0 : ((dsc_lcl_rd_valid)? 1'b1 : 1'b0);
3'b001: rd_req_dsc_grant <= (st_lcl_rd_valid)? 1'b0 : ((dsc_lcl_rd_valid)? 1'b1 : 1'b0);
default:;
endcase
else
rd_req_dsc_grant <= rd_req_dsc_grant;
// for rd_req_mm_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
rd_req_mm_grant <= 1'b0;
else if (rd_req_arb_en)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: rd_req_mm_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b1 : 1'b0);
3'b100: rd_req_mm_grant <= (mm_lcl_rd_valid)? 1'b1 : 1'b0;
3'b010: rd_req_mm_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b0 : 1'b1);
3'b001: rd_req_mm_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b1 : 1'b0);
default:;
endcase
else if (rd_req_arb_en_extend)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
//3'b000: rd_req_mm_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b1 : 1'b0);
3'b100: rd_req_mm_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b1 : 1'b0);
3'b010: rd_req_mm_grant <= (mm_lcl_rd_valid)? 1'b1 : 1'b0;
3'b001: rd_req_mm_grant <= (st_lcl_rd_valid)? 1'b0 : ((dsc_lcl_rd_valid)? 1'b0 : (mm_lcl_rd_valid)? 1'b1 : 1'b0);
default:;
endcase
else
rd_req_mm_grant <= rd_req_mm_grant;
// for rd_req_st_grant
always @(posedge clk or negedge rst_n)
if (!rst_n)
rd_req_st_grant <= 1'b0;
else if (rd_req_arb_en)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: rd_req_st_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0));
3'b100: rd_req_st_grant <= (mm_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0);
3'b010: rd_req_st_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0);
3'b001: rd_req_st_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b0 : 1'b1);
default:;
endcase
else if (rd_req_arb_en_extend)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
// 3'b000: rd_req_st_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0));
3'b100: rd_req_st_grant <= (dsc_lcl_rd_valid)? 1'b0 : ((mm_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0));
3'b010: rd_req_st_grant <= (mm_lcl_rd_valid)? 1'b0 : ((dsc_lcl_rd_valid)? 1'b0 : ((st_lcl_rd_valid)? 1'b1 : 1'b0));
3'b001: rd_req_st_grant <= (st_lcl_rd_valid)? 1'b1 : 1'b0;
default:;
endcase
else
rd_req_st_grant <= rd_req_st_grant;
always @(*)
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: no_arb = (~(dsc_lcl_rd_valid || mm_lcl_rd_valid || st_lcl_rd_valid)) && rd_req_arb_en;
3'b100: no_arb = ((dsc_lcl_rd_valid && dsc_lcl_rd_last && (~mm_lcl_rd_valid) && (~st_lcl_rd_valid))) && rd_req_arb_en;
3'b010: no_arb = ((mm_lcl_rd_valid && mm_lcl_rd_last && (~dsc_lcl_rd_valid) && (~st_lcl_rd_valid))) && rd_req_arb_en;
3'b001: no_arb = ((st_lcl_rd_valid && st_lcl_rd_last && (~dsc_lcl_rd_valid) && (~mm_lcl_rd_valid))) && rd_req_arb_en;
default: no_arb = 1'b0;
endcase
assign no_valid = ~(dsc_lcl_rd_valid || mm_lcl_rd_valid || st_lcl_rd_valid);
always @(*) begin
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: rd_req_arb_en = 1'b1;
3'b100: rd_req_arb_en = (dsc_lcl_rd_valid) && (dsc_lcl_rd_last) && lcl_rd_ready;
3'b010: rd_req_arb_en = (mm_lcl_rd_valid) && (mm_lcl_rd_last) && lcl_rd_ready;
3'b001: rd_req_arb_en = (st_lcl_rd_valid) && (st_lcl_rd_last) && lcl_rd_ready;
default: rd_req_arb_en = 1'b0;
endcase
end
always @(posedge clk or negedge rst_n)
if (!rst_n)
rd_req_arb_en_extend <= 1'b0;
else if (rd_req_arb_en && no_arb)
rd_req_arb_en_extend <= 1'b1;
else if (rd_req_arb_en_extend && (~no_valid))
rd_req_arb_en_extend <= 1'b0;
else
rd_req_arb_en_extend <= rd_req_arb_en_extend;
// Read request channel Data path
// LCL_Rd_IF -> Arbiter -> Engines
assign dsc_lcl_rd_ready = lcl_rd_ready && rd_req_dsc_grant;
assign mm_lcl_rd_ready = lcl_rd_ready && rd_req_mm_grant;
assign st_lcl_rd_ready = lcl_rd_ready && rd_req_st_grant;
// Engines -> Arbiter -> LCL_Rd_IF
always @(*) begin
case ({rd_req_dsc_grant, rd_req_mm_grant, rd_req_st_grant})
3'b000: begin
lcl_rd_valid = 1'b0;
lcl_rd_ea = 64'b0;
lcl_rd_axi_id = 5'b0;
lcl_rd_first = 1'b0;
lcl_rd_last = 1'b0;
lcl_rd_be = 128'b0;
lcl_rd_ctx = 9'b0;
lcl_rd_ctx_valid = 1'b0;
end
3'b100: begin
lcl_rd_valid = dsc_lcl_rd_valid;
lcl_rd_ea = dsc_lcl_rd_ea;
lcl_rd_axi_id = dsc_lcl_rd_axi_id;
lcl_rd_first = dsc_lcl_rd_first;
lcl_rd_last = dsc_lcl_rd_last;
lcl_rd_be = dsc_lcl_rd_be;
lcl_rd_ctx = dsc_lcl_rd_ctx;
lcl_rd_ctx_valid = dsc_lcl_rd_ctx_valid;
end
3'b010: begin
lcl_rd_valid = mm_lcl_rd_valid;
lcl_rd_ea = mm_lcl_rd_ea;
lcl_rd_axi_id = mm_lcl_rd_axi_id;
lcl_rd_first = mm_lcl_rd_first;
lcl_rd_last = mm_lcl_rd_last;
lcl_rd_be = mm_lcl_rd_be;
lcl_rd_ctx = mm_lcl_rd_ctx;
lcl_rd_ctx_valid = mm_lcl_rd_ctx_valid;
end
3'b001: begin
lcl_rd_valid = st_lcl_rd_valid;
lcl_rd_ea = st_lcl_rd_ea;
lcl_rd_axi_id = st_lcl_rd_axi_id;
lcl_rd_first = st_lcl_rd_first;
lcl_rd_last = st_lcl_rd_last;
lcl_rd_be = st_lcl_rd_be;
lcl_rd_ctx = st_lcl_rd_ctx;
lcl_rd_ctx_valid = st_lcl_rd_ctx_valid;
end
default:;
endcase
end
// Read Response/Data Channel
// rd_resp_dispatcher
// The dispatcher will dispatch the LCL Rd IF Response/Data to the three engines according to the axi_id
//
// Engines -> Arbiter -> LCL Rd IF
assign lcl_rd_rsp_ready[4] = dsc_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[12] = dsc_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[20] = dsc_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[28] = dsc_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready_hint[4] = dsc_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[12] = dsc_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[20] = dsc_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[28] = dsc_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready[2] = mm_lcl_rd_rsp_ready[0];
assign lcl_rd_rsp_ready[10] = mm_lcl_rd_rsp_ready[1];
assign lcl_rd_rsp_ready[18] = mm_lcl_rd_rsp_ready[2];
assign lcl_rd_rsp_ready[26] = mm_lcl_rd_rsp_ready[3];
assign lcl_rd_rsp_ready_hint[2] = mm_lcl_rd_rsp_ready_hint[0];
assign lcl_rd_rsp_ready_hint[10] = mm_lcl_rd_rsp_ready_hint[1];
assign lcl_rd_rsp_ready_hint[18] = mm_lcl_rd_rsp_ready_hint[2];
assign lcl_rd_rsp_ready_hint[26] = mm_lcl_rd_rsp_ready_hint[3];
assign lcl_rd_rsp_ready[3] = st_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[11] = st_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[19] = st_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready[27] = st_lcl_rd_rsp_ready;
assign lcl_rd_rsp_ready_hint[3] = st_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[11] = st_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[19] = st_lcl_rd_rsp_ready_hint;
assign lcl_rd_rsp_ready_hint[27] = st_lcl_rd_rsp_ready_hint;
assign {lcl_rd_rsp_ready[31:29],
lcl_rd_rsp_ready[25:21],
lcl_rd_rsp_ready[17:13],
lcl_rd_rsp_ready[9:5],
lcl_rd_rsp_ready[1:0] } = 20'b0;
assign {lcl_rd_rsp_ready_hint[31:29],
lcl_rd_rsp_ready_hint[25:21],
lcl_rd_rsp_ready_hint[17:13],
lcl_rd_rsp_ready_hint[9:5],
lcl_rd_rsp_ready_hint[1:0] } = 20'b0;
//TODO: spilt the *_lcl_rd_rsp_ready signal into 4 ready signals which is for an individual channel
// LCL Rd IF -> Arbiter -> Engines
always @(*) begin
case (lcl_rd_data_axi_id[2:0])
`DSC_ENGINE_ID: begin
dsc_lcl_rd_data_valid = lcl_rd_data_valid;
dsc_lcl_rd_data_axi_id = lcl_rd_data_axi_id;
dsc_lcl_rd_data = lcl_rd_data;
dsc_lcl_rd_data_last = lcl_rd_data_last;
dsc_lcl_rd_rsp_code = lcl_rd_rsp_code;
mm_lcl_rd_data_valid = 1'b0;
mm_lcl_rd_data_axi_id = 5'b0;
mm_lcl_rd_data = 1024'b0;
mm_lcl_rd_data_last = 1'b0;
mm_lcl_rd_rsp_code = 1'b0;
st_lcl_rd_data_valid = 1'b0;
st_lcl_rd_data_axi_id = 5'b0;
st_lcl_rd_data = 1024'b0;
st_lcl_rd_data_last = 1'b0;
st_lcl_rd_rsp_code = 1'b0;
end
`H2AMM_ENGINE_ID: begin
mm_lcl_rd_data_valid = lcl_rd_data_valid;
mm_lcl_rd_data_axi_id = lcl_rd_data_axi_id;
mm_lcl_rd_data = lcl_rd_data;
mm_lcl_rd_data_last = lcl_rd_data_last;
mm_lcl_rd_rsp_code = lcl_rd_rsp_code;
dsc_lcl_rd_data_valid = 1'b0;
dsc_lcl_rd_data_axi_id = 5'b0;
dsc_lcl_rd_data = 1024'b0;
dsc_lcl_rd_data_last = 1'b0;
dsc_lcl_rd_rsp_code = 1'b0;
st_lcl_rd_data_valid = 1'b0;
st_lcl_rd_data_axi_id = 5'b0;
st_lcl_rd_data = 1024'b0;
st_lcl_rd_data_last = 1'b0;
st_lcl_rd_rsp_code = 1'b0;
end
`H2AST_ENGINE_ID: begin
st_lcl_rd_data_valid = lcl_rd_data_valid;
st_lcl_rd_data_axi_id = lcl_rd_data_axi_id;
st_lcl_rd_data = lcl_rd_data;
st_lcl_rd_data_last = lcl_rd_data_last;
st_lcl_rd_rsp_code = lcl_rd_rsp_code;
dsc_lcl_rd_data_valid = 1'b0;
dsc_lcl_rd_data_axi_id = 5'b0;
dsc_lcl_rd_data = 1024'b0;
dsc_lcl_rd_data_last = 1'b0;
dsc_lcl_rd_rsp_code = 1'b0;
mm_lcl_rd_data_valid = 1'b0;
mm_lcl_rd_data_axi_id = 5'b0;
mm_lcl_rd_data = 1024'b0;
mm_lcl_rd_data_last = 1'b0;
mm_lcl_rd_rsp_code = 1'b0;
end
default: begin
dsc_lcl_rd_data_valid = 1'b0;
dsc_lcl_rd_data_axi_id = 5'b0;
dsc_lcl_rd_data = 1024'b0;
dsc_lcl_rd_data_last = 1'b0;
dsc_lcl_rd_rsp_code = 1'b0;
mm_lcl_rd_data_valid = 1'b0;
mm_lcl_rd_data_axi_id = 5'b0;
mm_lcl_rd_data = 1024'b0;
mm_lcl_rd_data_last = 1'b0;
mm_lcl_rd_rsp_code = 1'b0;
st_lcl_rd_data_valid = 1'b0;
st_lcl_rd_data_axi_id = 5'b0;
st_lcl_rd_data = 1024'b0;
st_lcl_rd_data_last = 1'b0;
st_lcl_rd_rsp_code = 1'b0;
end
endcase
end
endmodule |
module odma_descriptor_manager (
input clk ,
input rst_n ,
//configure
input [063:0] init_addr0 ,
input [063:0] init_addr1 ,
input [063:0] init_addr2 ,
input [063:0] init_addr3 ,
input [005:0] init_size0 ,
input [005:0] init_size1 ,
input [005:0] init_size2 ,
input [005:0] init_size3 ,
input dsc_ch0_h2a , //0:a2h 1:h2a
input dsc_ch1_h2a ,
input dsc_ch2_h2a ,
input dsc_ch3_h2a ,
input dsc_ch0_axi_st , //0:mm 1:st
input dsc_ch1_axi_st ,
input dsc_ch2_axi_st ,
input dsc_ch3_axi_st ,
output [063:0] manager_error ,
input [3:0] manager_start ,
//Read
output lcl_rd_valid ,
output [63:0] lcl_rd_ea ,
output [4:0] lcl_rd_axi_id ,
output lcl_rd_last ,
output lcl_rd_first ,
output [127:0] lcl_rd_be ,
output lcl_rd_ctx_valid,
output [8:0] lcl_rd_ctx ,
input lcl_rd_ready ,
input lcl_rd_data_valid,
input [4:0] lcl_rd_data_axi_id,
input [1023:0] lcl_rd_data ,
input lcl_rd_data_last,
input lcl_rd_rsp_code ,
output lcl_rd_rsp_ready,
//completion
output [3:0] channel_done ,
output reg [29:0] channel_id0 ,
output reg [29:0] channel_id1 ,
output reg [29:0] channel_id2 ,
output reg [29:0] channel_id3 ,
output [3:0] manager_start_w ,
//engine
input [3:0] eng_buf_full ,
output [3:0] eng_buf_write ,
output reg [255:0] eng_dsc_data0 ,
output reg [255:0] eng_dsc_data1 ,
output reg [255:0] eng_dsc_data2 ,
output reg [255:0] eng_dsc_data3
);
//lcl
reg [1:0] read_channel;
reg [3:0] beat_cnt;
reg read_start;
reg [5:0] total_num;
reg [127:0] read_byte_enable;
reg [63:0] next_addr;
reg [3:0] manager_start_r;
//channel
wire manager_start0;
reg channel0_done;
reg [63:0] next_addr0;
reg [5:0] ajacent_cnt0;
reg in_read0;
wire read_request0;
wire [1023:0] fifo_in0;
reg [1023:0] fifo_in0_r;
wire fifo_push0;
wire [6:0] fifo_cnt0;
wire fifo_empty0;
wire fifo_full0;
wire fifo_pull0;
wire [1023:0] fifo_out0;
reg [255:0] current_out0;
reg [1:0] current_valid0;
wire unvalid_dsc0;
wire next_dsc0;
wire manager_start1;
reg channel1_done;
reg [63:0] next_addr1;
reg [5:0] ajacent_cnt1;
reg in_read1;
wire read_request1;
wire [1023:0] fifo_in1;
reg [1023:0] fifo_in1_r;
wire fifo_push1;
wire [6:0] fifo_cnt1;
wire fifo_empty1;
wire fifo_full1;
wire fifo_pull1;
wire [1023:0] fifo_out1;
reg [255:0] current_out1;
reg [1:0] current_valid1;
wire unvalid_dsc1;
wire next_dsc1;
wire manager_start2;
reg channel2_done;
reg [63:0] next_addr2;
reg [5:0] ajacent_cnt2;
reg in_read2;
wire read_request2;
wire [1023:0] fifo_in2;
reg [1023:0] fifo_in2_r;
wire fifo_push2;
wire [6:0] fifo_cnt2;
wire fifo_empty2;
wire fifo_full2;
wire fifo_pull2;
wire [1023:0] fifo_out2;
reg [255:0] current_out2;
reg [1:0] current_valid2;
wire unvalid_dsc2;
wire next_dsc2;
wire manager_start3;
reg channel3_done;
reg [63:0] next_addr3;
reg [5:0] ajacent_cnt3;
reg in_read3;
wire read_request3;
wire [1023:0] fifo_in3;
reg [1023:0] fifo_in3_r;
wire fifo_push3;
wire [6:0] fifo_cnt3;
wire fifo_empty3;
wire fifo_full3;
wire fifo_pull3;
wire [1023:0] fifo_out3;
reg [255:0] current_out3;
reg [1:0] current_valid3;
wire unvalid_dsc3;
wire next_dsc3;
//engine
reg engine0_ready;
reg [1:0] engine0_channel;
reg engine1_ready;
reg [1:0] engine1_channel;
reg engine2_ready;
reg [1:0] engine2_channel;
reg engine3_ready;
reg [1:0] engine3_channel;
//channel arbiter
assign lcl_rd_valid = read_start;
assign lcl_rd_ea = next_addr + 'd128 * beat_cnt;
assign lcl_rd_axi_id = {read_channel,3'b100};
assign lcl_rd_last = (beat_cnt == total_num[5:2]) & read_start;
assign lcl_rd_first = (beat_cnt == 'b0) & lcl_rd_valid;
assign lcl_rd_be = read_byte_enable;
assign lcl_rd_ctx = 9'b0;
assign lcl_rd_ctx_valid = 0;
assign lcl_rd_rsp_ready = 1'b1;
assign manager_error = 64'b0;
assign manager_start_w = {manager_start3,manager_start2,manager_start1,manager_start0};
always@(posedge clk or negedge rst_n)
if(!rst_n)
manager_start_r <= 4'b0;
else
manager_start_r <= manager_start;
always@(*)
if(!rst_n)
total_num = 'd0;
else case(read_channel)
2'b00: total_num = ajacent_cnt0;
2'b01: total_num = ajacent_cnt1;
2'b10: total_num = ajacent_cnt2;
2'b11: total_num = ajacent_cnt3;
endcase
always@(*)
if(!rst_n)
next_addr = 'd0;
else case(read_channel)
2'b00: next_addr = next_addr0;
2'b01: next_addr = next_addr1;
2'b10: next_addr = next_addr2;
2'b11: next_addr = next_addr3;
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
read_start <= 1'b0;
else if(lcl_rd_last & lcl_rd_valid & lcl_rd_ready)
read_start <= 1'b0;
else if(read_request0 | read_request1 | read_request2 | read_request3)
read_start <= 1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
read_channel <= 2'b00;
else if(read_start)
read_channel <= read_channel;
else if(read_request0)
read_channel <= 2'b00;
else if(read_request1)
read_channel <= 2'b01;
else if(read_request2)
read_channel <= 2'b10;
else if(read_request3)
read_channel <= 2'b11;
always@(*)
if(!rst_n)
read_byte_enable = 128'b0;
else if(lcl_rd_last)
case(total_num[1:0])
2'b00: read_byte_enable = 128'h000000000000000000000000ffffffff;
2'b01: read_byte_enable = 128'h0000000000000000ffffffffffffffff;
2'b10: read_byte_enable = 128'h00000000ffffffffffffffffffffffff;
2'b11: read_byte_enable = 128'hffffffffffffffffffffffffffffffff;
endcase
else
read_byte_enable = 128'hffffffffffffffffffffffffffffffff;
always@(posedge clk or negedge rst_n)
if(!rst_n)
beat_cnt <= 4'b0;
else if(lcl_rd_ready&lcl_rd_valid&lcl_rd_last)
beat_cnt <= 4'b0;
else if(lcl_rd_ready&lcl_rd_valid)
beat_cnt <= beat_cnt + 1'b1;
//channel0
assign read_request0 = !in_read0 & ((fifo_cnt0[4:0] + ajacent_cnt0[5:2] < 'd16) | fifo_empty0) & manager_start_r[0] & !channel0_done;
assign manager_start0 = manager_start[0] & !manager_start_r[0];
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel0_done <= 1'b0;
else if(manager_start0)
channel0_done <= 1'b0;
else if((lcl_rd_data_axi_id == 5'b00100) & lcl_rd_data_valid & !lcl_rd_rsp_code)
case(ajacent_cnt0[1:0])
2'b00: channel0_done <= lcl_rd_data[0];
2'b01: channel0_done <= lcl_rd_data[256];
2'b10: channel0_done <= lcl_rd_data[512];
2'b11: channel0_done <= lcl_rd_data[768];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_read0 <= 1'b0;
else if(read_start & (read_channel == 2'b00))
in_read0 <= 1'b1;
else if(in_read0 & lcl_rd_data_last & lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id[4:0] == 5'b00100))
in_read0 <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
ajacent_cnt0 <= 6'h3f;
else if(manager_start0)
ajacent_cnt0 <= init_size0;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b00100) & lcl_rd_data_last)
case(ajacent_cnt0[1:0])
2'b11: ajacent_cnt0 <= lcl_rd_data[781:776];
2'b10: ajacent_cnt0 <= lcl_rd_data[525:520];
2'b01: ajacent_cnt0 <= lcl_rd_data[269:264];
2'b00: ajacent_cnt0 <= lcl_rd_data[13:8];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
next_addr0 <= 'd0;
else if(manager_start0)
next_addr0 <= init_addr0;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b00100) & lcl_rd_data_last)
case(ajacent_cnt0[1:0])
2'b00: next_addr0 <= lcl_rd_data[255:192];
2'b01: next_addr0 <= lcl_rd_data[511:448];
2'b10: next_addr0 <= lcl_rd_data[767:704];
2'b11: next_addr0 <= lcl_rd_data[1023:960];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_id0 <= 30'b0;
else if (manager_start0)
channel_id0 <= 30'b0;
else if(next_dsc0)
channel_id0 <= channel_id0 + 1'b1;
assign fifo_push0 = lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b00100);
assign fifo_pull0 = ((next_dsc0 & (current_valid0 == 'd3)) | unvalid_dsc0) & !fifo_empty0;
assign unvalid_dsc0 = (current_out0[31:16] != 16'had4b);
assign channel_done[0] = next_dsc0 & current_out0[0];
assign next_dsc0 = (eng_buf_write[0]&(engine0_channel==2'b00))|(eng_buf_write[1]&(engine1_channel==2'b00))|(eng_buf_write[2]&(engine2_channel==2'b00))|(eng_buf_write[3]&(engine3_channel==2'b00));
assign fifo_in0 = fifo_in0_r;
always@(*) begin
fifo_in0_r = lcl_rd_data;
if(lcl_rd_data_last & lcl_rd_data_valid & (lcl_rd_data_axi_id == 5'b00100))
case(ajacent_cnt0[1:0])
2'b00: fifo_in0_r[287] = 1'b0;
2'b01: fifo_in0_r[543] = 1'b0;
2'b10: fifo_in0_r[799] = 1'b0;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
current_valid0 <= 2'b00;
else if(manager_start0 | unvalid_dsc0)
current_valid0 <= 2'b00;
else if(next_dsc0)
current_valid0 <= current_valid0 + 1'b1;
always@(*)
if(!rst_n)
current_out0 = 256'b0;
else case(current_valid0)
2'b00: current_out0 = fifo_out0[255:0];
2'b01: current_out0 = fifo_out0[511:256];
2'b10: current_out0 = fifo_out0[767:512];
2'b11: current_out0 = fifo_out0[1023:768];
endcase
channel_fifo channel_fifo0 ( //256x64
.clk (clk ),
.srst (manager_start0 ),
.din (fifo_in0_r ),
.wr_en (fifo_push0 ),
.rd_en (fifo_pull0 ),
.dout (fifo_out0 ),
.full (fifo_full0 ),
.data_count (fifo_cnt0 ),
.empty (fifo_empty0 )
);
//channel1
assign read_request1 = !in_read1 & ((fifo_cnt1[4:0] + ajacent_cnt1[5:2] < 'd16) | fifo_empty1) & manager_start_r[1] & !channel1_done;
assign manager_start1 = manager_start[1] & !manager_start_r[1];
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel1_done <= 1'b0;
else if(manager_start1)
channel1_done <= 1'b0;
else if((lcl_rd_data_axi_id == 5'b01100) & lcl_rd_data_valid & !lcl_rd_rsp_code)
case(ajacent_cnt1[1:0])
2'b00: channel1_done <= lcl_rd_data[0];
2'b01: channel1_done <= lcl_rd_data[256];
2'b10: channel1_done <= lcl_rd_data[512];
2'b11: channel1_done <= lcl_rd_data[768];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_read1 <= 1'b0;
else if(read_start & (read_channel == 2'b01))
in_read1 <= 1'b1;
else if(in_read1 & lcl_rd_data_last & lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id[4:0] == 5'b01100))
in_read1 <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
ajacent_cnt1 <= 6'h3f;
else if(manager_start1)
ajacent_cnt1 <= init_size1;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b01100) & lcl_rd_data_last)
case(ajacent_cnt1[1:0])
2'b11: ajacent_cnt1 <= lcl_rd_data[781:776];
2'b10: ajacent_cnt1 <= lcl_rd_data[525:520];
2'b01: ajacent_cnt1 <= lcl_rd_data[269:264];
2'b00: ajacent_cnt1 <= lcl_rd_data[13:8];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
next_addr1 <= 'd0;
else if(manager_start1)
next_addr1 <= init_addr1;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b01100) & lcl_rd_data_last)
case(ajacent_cnt1[1:0])
2'b00: next_addr1 <= lcl_rd_data[255:192];
2'b01: next_addr1 <= lcl_rd_data[511:448];
2'b10: next_addr1 <= lcl_rd_data[767:704];
2'b11: next_addr1 <= lcl_rd_data[1023:960];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_id1 <= 30'b0;
else if (manager_start1)
channel_id1 <= 30'b0;
else if(next_dsc1)
channel_id1 <= channel_id1 + 1'b1;
assign fifo_push1 = lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b01100);
assign fifo_pull1 = ((next_dsc1 & (current_valid1 == 'd3)) | unvalid_dsc1) & !fifo_empty1;
assign unvalid_dsc1 = (current_out1[31:16] != 16'had4b);
assign channel_done[1] = next_dsc1 & current_out1[0];
assign next_dsc1 = (eng_buf_write[0]&(engine0_channel==2'b01))|(eng_buf_write[1]&(engine1_channel==2'b01))|(eng_buf_write[2]&(engine2_channel==2'b01))|(eng_buf_write[3]&(engine3_channel==2'b01));
assign fifo_in1 = fifo_in1_r;
always@(*) begin
fifo_in1_r = lcl_rd_data;
if(lcl_rd_data_last & lcl_rd_data_valid & (lcl_rd_data_axi_id == 5'b01100))
case(ajacent_cnt1[1:0])
2'b00: fifo_in1_r[287] = 1'b0;
2'b01: fifo_in1_r[543] = 1'b0;
2'b10: fifo_in1_r[799] = 1'b0;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
current_valid1 <= 2'b00;
else if(manager_start1 | unvalid_dsc1)
current_valid1 <= 2'b00;
else if(next_dsc1)
current_valid1 <= current_valid1 + 1'b1;
always@(*)
if(!rst_n)
current_out1 = 256'b0;
else case(current_valid1)
2'b00: current_out1 = fifo_out1[255:0];
2'b01: current_out1 = fifo_out1[511:256];
2'b10: current_out1 = fifo_out1[767:512];
2'b11: current_out1 = fifo_out1[1023:768];
endcase
channel_fifo channel_fifo1 ( //256x64
.clk (clk ),
.srst (manager_start1 ),
.din (fifo_in1 ),
.wr_en (fifo_push1 ),
.rd_en (fifo_pull1 ),
.dout (fifo_out1 ),
.full (fifo_full1 ),
.data_count (fifo_cnt1 ),
.empty (fifo_empty1 )
);
//channel2
assign read_request2 = !in_read2 & ((fifo_cnt2[4:0] + ajacent_cnt2[5:2] < 'd16) | fifo_empty2) & manager_start_r[2] & !channel2_done;
assign manager_start2 = manager_start[2] & !manager_start_r[2];
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel2_done <= 1'b0;
else if(manager_start2)
channel2_done <= 1'b0;
else if((lcl_rd_data_axi_id == 5'b10100) & lcl_rd_data_valid & !lcl_rd_rsp_code)
case(ajacent_cnt2[1:0])
2'b00: channel2_done <= lcl_rd_data[0];
2'b01: channel2_done <= lcl_rd_data[256];
2'b10: channel2_done <= lcl_rd_data[512];
2'b11: channel2_done <= lcl_rd_data[768];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_read2 <= 1'b0;
else if(read_start & (read_channel == 2'b10))
in_read2 <= 1'b1;
else if(in_read2 & lcl_rd_data_last & lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id[4:0] == 5'b10100))
in_read2 <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
ajacent_cnt2 <= 6'h3f;
else if(manager_start2)
ajacent_cnt2 <= init_size2;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b10100) & lcl_rd_data_last)
case(ajacent_cnt2[1:0])
2'b11: ajacent_cnt2 <= lcl_rd_data[781:776];
2'b10: ajacent_cnt2 <= lcl_rd_data[525:520];
2'b01: ajacent_cnt2 <= lcl_rd_data[269:264];
2'b00: ajacent_cnt2 <= lcl_rd_data[13:8];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
next_addr2 <= 'd0;
else if(manager_start2)
next_addr2 <= init_addr2;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b10100) & lcl_rd_data_last)
case(ajacent_cnt2[1:0])
2'b00: next_addr2 <= lcl_rd_data[255:192];
2'b01: next_addr2 <= lcl_rd_data[511:448];
2'b10: next_addr2 <= lcl_rd_data[767:704];
2'b11: next_addr2 <= lcl_rd_data[1023:960];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_id2 <= 30'b0;
else if (manager_start2)
channel_id2 <= 30'b0;
else if(next_dsc2)
channel_id2 <= channel_id2 + 1'b1;
assign fifo_push2 = lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b10100);
assign fifo_pull2 = ((next_dsc2 & (current_valid2 == 'd3)) | unvalid_dsc2) & !fifo_empty2;
assign unvalid_dsc2 = (current_out2[31:16] != 16'had4b);
assign channel_done[2] = next_dsc2 & current_out2[0];
assign next_dsc2 = (eng_buf_write[0]&(engine0_channel==2'b10))|(eng_buf_write[1]&(engine1_channel==2'b10))|(eng_buf_write[2]&(engine2_channel==2'b10))|(eng_buf_write[3]&(engine3_channel==2'b10));
assign fifo_in2 = fifo_in2_r;
always@(*) begin
fifo_in2_r = lcl_rd_data;
if(lcl_rd_data_last & lcl_rd_data_valid & (lcl_rd_data_axi_id == 5'b10100))
case(ajacent_cnt2[1:0])
2'b00: fifo_in2_r[287] = 1'b0;
2'b01: fifo_in2_r[543] = 1'b0;
2'b10: fifo_in2_r[799] = 1'b0;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
current_valid2 <= 2'b00;
else if(manager_start2 | unvalid_dsc2)
current_valid2 <= 2'b00;
else if(next_dsc2)
current_valid2 <= current_valid2 + 1'b1;
always@(*)
if(!rst_n)
current_out2 = 256'b0;
else case(current_valid2)
2'b00: current_out2 = fifo_out2[255:0];
2'b01: current_out2 = fifo_out2[511:256];
2'b10: current_out2 = fifo_out2[767:512];
2'b11: current_out2 = fifo_out2[1023:768];
endcase
channel_fifo channel_fifo2 ( //256x64
.clk (clk ),
.srst (manager_start2 ),
.din (fifo_in2 ),
.wr_en (fifo_push2 ),
.rd_en (fifo_pull2 ),
.dout (fifo_out2 ),
.full (fifo_full2 ),
.data_count (fifo_cnt2 ),
.empty (fifo_empty2 )
);
//channel3
assign read_request3 = !in_read3 & ((fifo_cnt3[4:0] + ajacent_cnt3[5:2] < 'd16) | fifo_empty3) & manager_start_r[3] & !channel3_done;
assign manager_start3 = manager_start[3] & !manager_start_r[3];
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel3_done <= 1'b0;
else if(manager_start3)
channel3_done <= 1'b0;
else if((lcl_rd_data_axi_id == 5'b11100) & lcl_rd_data_valid & !lcl_rd_rsp_code)
case(ajacent_cnt3[1:0])
2'b00: channel3_done <= lcl_rd_data[0];
2'b01: channel3_done <= lcl_rd_data[256];
2'b10: channel3_done <= lcl_rd_data[512];
2'b11: channel3_done <= lcl_rd_data[768];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
in_read3 <= 1'b0;
else if(read_start & (read_channel == 2'b11))
in_read3 <= 1'b1;
else if(in_read3 & lcl_rd_data_last & lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id[4:0] == 5'b11100))
in_read3 <= 1'b0;
always@(posedge clk or negedge rst_n)
if(!rst_n)
ajacent_cnt3 <= 6'h3f;
else if(manager_start3)
ajacent_cnt3 <= init_size3;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b11100) & lcl_rd_data_last)
case(ajacent_cnt3[1:0])
2'b11: ajacent_cnt3 <= lcl_rd_data[781:776];
2'b10: ajacent_cnt3 <= lcl_rd_data[525:520];
2'b01: ajacent_cnt3 <= lcl_rd_data[269:264];
2'b00: ajacent_cnt3 <= lcl_rd_data[13:8];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
next_addr3 <= 'd0;
else if(manager_start3)
next_addr3 <= init_addr3;
else if(lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b11100) & lcl_rd_data_last)
case(ajacent_cnt3[1:0])
2'b00: next_addr3 <= lcl_rd_data[255:192];
2'b01: next_addr3 <= lcl_rd_data[511:448];
2'b10: next_addr3 <= lcl_rd_data[767:704];
2'b11: next_addr3 <= lcl_rd_data[1023:960];
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
channel_id3 <= 30'b0;
else if (manager_start3)
channel_id3 <= 30'b0;
else if(next_dsc3)
channel_id3 <= channel_id3 + 1'b1;
assign fifo_push3 = lcl_rd_data_valid & !lcl_rd_rsp_code & (lcl_rd_data_axi_id == 5'b11100);
assign fifo_pull3 = ((next_dsc3 & (current_valid3 == 'd3)) | unvalid_dsc3) & !fifo_empty3;
assign unvalid_dsc3 = (current_out3[31:16] != 16'had4b);
assign channel_done[3] = next_dsc3 & current_out3[0];
assign next_dsc3 = (eng_buf_write[0]&(engine0_channel==2'b11))|(eng_buf_write[1]&(engine1_channel==2'b11))|(eng_buf_write[2]&(engine2_channel==2'b11))|(eng_buf_write[3]&(engine3_channel==2'b11));
assign fifo_in3 = fifo_in3_r;
always@(*) begin
fifo_in3_r = lcl_rd_data;
if(lcl_rd_data_last & lcl_rd_data_valid & (lcl_rd_data_axi_id == 5'b11100))
case(ajacent_cnt3[1:0])
2'b00: fifo_in3_r[287] = 1'b0;
2'b01: fifo_in3_r[543] = 1'b0;
2'b10: fifo_in3_r[799] = 1'b0;
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
current_valid3 <= 2'b00;
else if(manager_start3 | unvalid_dsc3)
current_valid3 <= 2'b00;
else if(next_dsc3)
current_valid3 <= current_valid3 + 1'b1;
always@(*)
if(!rst_n)
current_out3 = 256'b0;
else case(current_valid3)
2'b00: current_out3 = fifo_out3[255:0];
2'b01: current_out3 = fifo_out3[511:256];
2'b10: current_out3 = fifo_out3[767:512];
2'b11: current_out3 = fifo_out3[1023:768];
endcase
channel_fifo channel_fifo3 ( //256x64
.clk (clk ),
.srst (manager_start3 ),
.din (fifo_in3 ),
.wr_en (fifo_push3 ),
.rd_en (fifo_pull3 ),
.dout (fifo_out3 ),
.full (fifo_full3 ),
.data_count (fifo_cnt3 ),
.empty (fifo_empty3 )
);
//engine 0
assign eng_buf_write[0] = engine0_ready&!eng_buf_full[0];
always@(*)
if(!rst_n)
eng_dsc_data0 = 256'b0;
else
case(engine0_channel)
2'b00:eng_dsc_data0 = {34'h0,channel_id0,current_out0[191:0]};
2'b01:eng_dsc_data0 = {34'h1,channel_id1,current_out1[191:0]};
2'b10:eng_dsc_data0 = {34'h2,channel_id2,current_out2[191:0]};
2'b11:eng_dsc_data0 = {34'h3,channel_id3,current_out3[191:0]};
endcase
always@(*)
if(!rst_n)
engine0_ready = 1'b0;
else
case(engine0_channel)
2'b00:engine0_ready = !fifo_empty0 & !dsc_ch0_h2a & !dsc_ch0_axi_st & (current_out0[31:16] == 16'had4b);
2'b01:engine0_ready = !fifo_empty1 & !dsc_ch1_h2a & !dsc_ch1_axi_st & (current_out1[31:16] == 16'had4b);
2'b10:engine0_ready = !fifo_empty2 & !dsc_ch2_h2a & !dsc_ch2_axi_st & (current_out2[31:16] == 16'had4b);
2'b11:engine0_ready = !fifo_empty3 & !dsc_ch3_h2a & !dsc_ch3_axi_st & (current_out3[31:16] == 16'had4b);
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine0_channel <= 2'b00;
else if(!eng_buf_full[0])
engine0_channel <= engine0_channel + 1'b1;
//engine 1
assign eng_buf_write[1] = engine1_ready&!eng_buf_full[1];
always@(*)
if(!rst_n)
eng_dsc_data1 = 1'b0;
else
case(engine1_channel)
2'b00:eng_dsc_data1 = {34'h0,channel_id0,current_out0[191:0]};
2'b01:eng_dsc_data1 = {34'h1,channel_id1,current_out1[191:0]};
2'b10:eng_dsc_data1 = {34'h2,channel_id2,current_out2[191:0]};
2'b11:eng_dsc_data1 = {34'h3,channel_id3,current_out3[191:0]};
endcase
always@(*)
if(!rst_n)
engine1_ready = 1'b0;
else
case(engine1_channel)
2'b00:engine1_ready = !fifo_empty0 & !dsc_ch0_h2a & dsc_ch0_axi_st & (current_out0[31:16] == 16'had4b);
2'b01:engine1_ready = !fifo_empty1 & !dsc_ch1_h2a & dsc_ch1_axi_st & (current_out1[31:16] == 16'had4b);
2'b10:engine1_ready = !fifo_empty2 & !dsc_ch2_h2a & dsc_ch2_axi_st & (current_out2[31:16] == 16'had4b);
2'b11:engine1_ready = !fifo_empty3 & !dsc_ch3_h2a & dsc_ch3_axi_st & (current_out3[31:16] == 16'had4b);
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine1_channel <= 2'b00;
else if(!eng_buf_full[1])
engine1_channel <= engine1_channel + 1'b1;
//engine 2
assign eng_buf_write[2] = engine2_ready&!eng_buf_full[2];
always@(*)
if(!rst_n)
eng_dsc_data2 = 1'b0;
else
case(engine2_channel)
2'b00:eng_dsc_data2 = {34'h0,channel_id0,current_out0[191:0]};
2'b01:eng_dsc_data2 = {34'h1,channel_id1,current_out1[191:0]};
2'b10:eng_dsc_data2 = {34'h2,channel_id2,current_out2[191:0]};
2'b11:eng_dsc_data2 = {34'h3,channel_id3,current_out3[191:0]};
endcase
always@(*)
if(!rst_n)
engine2_ready = 1'b0;
else
case(engine2_channel)
2'b00:engine2_ready = !fifo_empty0 & dsc_ch0_h2a & !dsc_ch0_axi_st & (current_out0[31:16] == 16'had4b);
2'b01:engine2_ready = !fifo_empty1 & dsc_ch1_h2a & !dsc_ch1_axi_st & (current_out1[31:16] == 16'had4b);
2'b10:engine2_ready = !fifo_empty2 & dsc_ch2_h2a & !dsc_ch2_axi_st & (current_out2[31:16] == 16'had4b);
2'b11:engine2_ready = !fifo_empty3 & dsc_ch3_h2a & !dsc_ch3_axi_st & (current_out3[31:16] == 16'had4b);
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine2_channel <= 2'b00;
else if(!eng_buf_full[2])
engine2_channel <= engine2_channel + 1'b1;
//engine 3
assign eng_buf_write[3] = engine3_ready&!eng_buf_full[3];
always@(*)
if(!rst_n)
eng_dsc_data3 = 1'b0;
else
case(engine3_channel)
2'b00:eng_dsc_data3 = {34'h0,channel_id0,current_out0[191:0]};
2'b01:eng_dsc_data3 = {34'h1,channel_id1,current_out1[191:0]};
2'b10:eng_dsc_data3 = {34'h2,channel_id2,current_out2[191:0]};
2'b11:eng_dsc_data3 = {34'h3,channel_id3,current_out3[191:0]};
endcase
always@(*)
if(!rst_n)
engine3_ready = 1'b0;
else
case(engine3_channel)
2'b00:engine3_ready = !fifo_empty0 & dsc_ch0_h2a & dsc_ch0_axi_st & (current_out0[31:16] == 16'had4b);
2'b01:engine3_ready = !fifo_empty1 & dsc_ch1_h2a & dsc_ch1_axi_st & (current_out1[31:16] == 16'had4b);
2'b10:engine3_ready = !fifo_empty2 & dsc_ch2_h2a & dsc_ch2_axi_st & (current_out2[31:16] == 16'had4b);
2'b11:engine3_ready = !fifo_empty3 & dsc_ch3_h2a & dsc_ch3_axi_st & (current_out3[31:16] == 16'had4b);
endcase
always@(posedge clk or negedge rst_n)
if(!rst_n)
engine3_channel <= 2'b00;
else if(!eng_buf_full[3])
engine3_channel <= engine3_channel + 1'b1;
endmodule |
module nvme_host_wrap
(
input wire axi_aclk,
input wire axi_aresetn,
// Action/MMIO to NMVE Host Slave AXI Lite IF
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_awaddr,
input wire host_s_axi_awvalid,
output wire host_s_axi_awready,
input wire [31:0] host_s_axi_wdata,
input wire [3:0] host_s_axi_wstrb,
input wire host_s_axi_wvalid,
output wire host_s_axi_wready,
output wire [1:0] host_s_axi_bresp,
output wire host_s_axi_bvalid,
input wire host_s_axi_bready,
input wire [`HOST_ADDR_BITS - 1:0] host_s_axi_araddr,
input wire host_s_axi_arvalid,
output wire host_s_axi_arready,
output wire [31:0] host_s_axi_rdata,
output wire [1:0] host_s_axi_rresp,
output wire host_s_axi_rvalid,
input wire host_s_axi_rready,
// NVMe Host to PCIE Master AXI Lite IF
output wire [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_awaddr,
output wire [2:0] pcie_m_axi_awprot,
output wire pcie_m_axi_awvalid,
input wire pcie_m_axi_awready,
output wire [31:0] pcie_m_axi_wdata,
output wire [3:0] pcie_m_axi_wstrb,
output wire pcie_m_axi_wvalid,
input wire pcie_m_axi_wready,
input wire [1:0] pcie_m_axi_bresp,
input wire pcie_m_axi_bvalid,
output wire pcie_m_axi_bready,
output wire [`PCIE_M_ADDR_BITS-1:0] pcie_m_axi_araddr,
output wire [2:0] pcie_m_axi_arprot,
output wire pcie_m_axi_arvalid,
input wire pcie_m_axi_arready,
input wire [31:0] pcie_m_axi_rdata,
input wire [1:0] pcie_m_axi_rresp,
input wire pcie_m_axi_rvalid,
output wire pcie_m_axi_rready,
// NVMe Host to PCIE Slave AXI MM IF
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_awid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_awaddr,
input wire [7:0] pcie_s_axi_awlen,
input wire [2:0] pcie_s_axi_awsize,
input wire [1:0] pcie_s_axi_awburst,
input wire pcie_s_axi_awvalid,
output wire pcie_s_axi_awready,
input wire [127:0] pcie_s_axi_wdata,
input wire [15:0] pcie_s_axi_wstrb,
input wire pcie_s_axi_wlast,
input wire pcie_s_axi_wvalid,
output wire pcie_s_axi_wready,
output wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_bid,
output wire [1:0] pcie_s_axi_bresp,
output wire pcie_s_axi_bvalid,
input wire pcie_s_axi_bready,
input wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_arid,
input wire [`PCIE_S_ADDR_BITS-1:0] pcie_s_axi_araddr,
input wire [7:0] pcie_s_axi_arlen,
input wire [2:0] pcie_s_axi_arsize,
input wire [1:0] pcie_s_axi_arburst,
input wire pcie_s_axi_arvalid,
output wire pcie_s_axi_arready,
output wire [`PCIE_S_ID_BITS-1:0] pcie_s_axi_rid,
output wire [127:0] pcie_s_axi_rdata,
output wire [1:0] pcie_s_axi_rresp,
output wire pcie_s_axi_rlast,
output wire pcie_s_axi_rvalid,
input wire pcie_s_axi_rready
);
nvme_host nvme_host_i (
.axi_aclk (axi_aclk),
.axi_aresetn (axi_aresetn),
.host_s_axi_awaddr (host_s_axi_awaddr ),
.host_s_axi_awvalid (host_s_axi_awvalid ),
.host_s_axi_awready (host_s_axi_awready ),
.host_s_axi_wdata (host_s_axi_wdata ),
.host_s_axi_wstrb (host_s_axi_wstrb ),
.host_s_axi_wvalid (host_s_axi_wvalid ),
.host_s_axi_wready (host_s_axi_wready ),
.host_s_axi_bresp (host_s_axi_bresp ),
.host_s_axi_bvalid (host_s_axi_bvalid ),
.host_s_axi_bready (host_s_axi_bready ),
.host_s_axi_araddr (host_s_axi_araddr ),
.host_s_axi_arvalid (host_s_axi_arvalid ),
.host_s_axi_arready (host_s_axi_arready ),
.host_s_axi_rdata (host_s_axi_rdata ),
.host_s_axi_rresp (host_s_axi_rresp ),
.host_s_axi_rvalid (host_s_axi_rvalid ),
.host_s_axi_rready (host_s_axi_rready ),
.pcie_m_axi_awaddr (pcie_m_axi_awaddr ),
.pcie_m_axi_awprot (pcie_m_axi_awprot ),
.pcie_m_axi_awvalid (pcie_m_axi_awvalid ),
.pcie_m_axi_awready (pcie_m_axi_awready ),
.pcie_m_axi_wdata (pcie_m_axi_wdata ),
.pcie_m_axi_wstrb (pcie_m_axi_wstrb ),
.pcie_m_axi_wvalid (pcie_m_axi_wvalid ),
.pcie_m_axi_wready (pcie_m_axi_wready ),
.pcie_m_axi_bresp (pcie_m_axi_bresp ),
.pcie_m_axi_bvalid (pcie_m_axi_bvalid ),
.pcie_m_axi_bready (pcie_m_axi_bready ),
.pcie_m_axi_araddr (pcie_m_axi_araddr ),
.pcie_m_axi_arprot (pcie_m_axi_arprot ),
.pcie_m_axi_arvalid (pcie_m_axi_arvalid ),
.pcie_m_axi_arready (pcie_m_axi_arready ),
.pcie_m_axi_rdata (pcie_m_axi_rdata ),
.pcie_m_axi_rresp (pcie_m_axi_rresp ),
.pcie_m_axi_rvalid (pcie_m_axi_rvalid ),
.pcie_m_axi_rready (pcie_m_axi_rready ),
.pcie_s_axi_awid (pcie_s_axi_awid ),
.pcie_s_axi_awaddr (pcie_s_axi_awaddr ),
.pcie_s_axi_awlen (pcie_s_axi_awlen ),
.pcie_s_axi_awsize (pcie_s_axi_awsize ),
.pcie_s_axi_awburst (pcie_s_axi_awburst ),
.pcie_s_axi_awvalid (pcie_s_axi_awvalid ),
.pcie_s_axi_awready (pcie_s_axi_awready ),
.pcie_s_axi_wdata (pcie_s_axi_wdata ),
.pcie_s_axi_wstrb (pcie_s_axi_wstrb ),
.pcie_s_axi_wlast (pcie_s_axi_wlast ),
.pcie_s_axi_wvalid (pcie_s_axi_wvalid ),
.pcie_s_axi_wready (pcie_s_axi_wready ),
.pcie_s_axi_bid (pcie_s_axi_bid ),
.pcie_s_axi_bresp (pcie_s_axi_bresp ),
.pcie_s_axi_bvalid (pcie_s_axi_bvalid ),
.pcie_s_axi_bready (pcie_s_axi_bready ),
.pcie_s_axi_arid (pcie_s_axi_arid ),
.pcie_s_axi_araddr (pcie_s_axi_araddr ),
.pcie_s_axi_arlen (pcie_s_axi_arlen ),
.pcie_s_axi_arsize (pcie_s_axi_arsize ),
.pcie_s_axi_arburst (pcie_s_axi_arburst ),
.pcie_s_axi_arvalid (pcie_s_axi_arvalid ),
.pcie_s_axi_arready (pcie_s_axi_arready ),
.pcie_s_axi_rid (pcie_s_axi_rid ),
.pcie_s_axi_rdata (pcie_s_axi_rdata ),
.pcie_s_axi_rresp (pcie_s_axi_rresp ),
.pcie_s_axi_rlast (pcie_s_axi_rlast ),
.pcie_s_axi_rvalid (pcie_s_axi_rvalid ),
.pcie_s_axi_rready (pcie_s_axi_rready )
);
endmodule |
Subsets and Splits