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module WaveformGenerator (
input clk,
input wgen, // waveform generator enable signal
input rstn,
output [7:0] DACdata,
output WRn,
output CSn,
output DACsel
);
reg [7:0] addr_reg;
wire [7:0] addr_next;
assign addr_next = (addr_reg == 8'd200) ? 8'd0 : addr_reg + 1;
always @ (posedge clk) begin
if (~rstn) begin
addr_reg <= 8'b0;
end
else begin
addr_reg <= addr_next;
end
end
wire [7:0] addr;
assign addr = addr_reg;
wire [7:0] rom_data;
WaveformROM #(
.ADDR_WIDTH (8)
) sinROM (
.clka (clk),
.addra (addr),
.douta (rom_data)
);
assign DACdata = (wgen)?rom_data:8'b0;
assign {WRn, CSn, DACsel} = 3'b000;
endmodule |
module WaveformROM #(
parameter ADDR_WIDTH = 8)(
input clka,
input [ADDR_WIDTH-1:0] addra,
output reg [7:0] douta
);
(* ramstyle = "AUTO" *) reg [7:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("C:/Users/range/Desktop/CortexM0_SoC/Task4/source/sin_Xilinx.hex", mem);
end
always@(posedge clka) begin
douta <= mem[addra];
end
endmodule |
module seg_led_decoder(
input [3:0] data_disp,
output reg [7:0] seg_led
);
always@(data_disp)begin
case(data_disp)
4'h0 : seg_led = 8'h3f;
4'h1 : seg_led = 8'h06;
4'h2 : seg_led = 8'h5b;
4'h3 : seg_led = 8'h4f;
4'h4 : seg_led = 8'h66;
4'h5 : seg_led = 8'h6d;
4'h6 : seg_led = 8'h7d;
4'h7 : seg_led = 8'h07;
4'h8 : seg_led = 8'h7f;
4'h9 : seg_led = 8'h6f;
4'ha : seg_led = 8'h77;
4'hb : seg_led = 8'h7c;
4'hc : seg_led = 8'h39;
4'hd : seg_led = 8'h5e;
4'he : seg_led = 8'h79;
4'hf : seg_led = 8'h71;
default :seg_led = 8'h00;
endcase
end
endmodule |
module seg_sel_decoder(
input [2:0] bit_disp,
output reg [5:0] seg_sel
);
always@(bit_disp)begin
case(bit_disp)
3'b000 : seg_sel = 6'b011111;
3'b001 : seg_sel = 6'b101111;
3'b010 : seg_sel = 6'b110111;
3'b011 : seg_sel = 6'b111011;
3'b100 : seg_sel = 6'b111101;
3'b101 : seg_sel = 6'b111110;
default : seg_sel = 6'b111111;
endcase
end
endmodule |
module clk_division #(
parameter DIVCLK_CNTMAX = 24999
)(
input clk_in,
input rstn,
output divclk
);
reg [31:0] cnt;
reg divclk_reg;
always@(posedge clk_in, negedge rstn) begin
if (!rstn) begin
cnt <= 0;
divclk_reg <= 0;
end else begin
if(cnt == DIVCLK_CNTMAX) begin
cnt <= 0;
divclk_reg <= ~divclk_reg;
end
else begin
cnt <= cnt + 1;
end
end
end
assign divclk = divclk_reg;
endmodule |
module keyboard_reg (
input clk,
input rstn,
input key_clear,//高有效
input [15:0] key_pulse,
output reg [15:0] key_reg
);
wire clear;
assign clear = rstn && (!key_clear) ;
always @(posedge clk or negedge clear) begin
if (!clear) begin
key_reg <= 1'b0;
end else begin
if(key_pulse[15]) key_reg[15] <= 1'b1;
if(key_pulse[14]) key_reg[14] <= 1'b1;
if(key_pulse[13]) key_reg[13] <= 1'b1;
if(key_pulse[12]) key_reg[12] <= 1'b1;
if(key_pulse[11]) key_reg[11] <= 1'b1;
if(key_pulse[10]) key_reg[10] <= 1'b1;
if(key_pulse[9]) key_reg[9] <= 1'b1;
if(key_pulse[8]) key_reg[8] <= 1'b1;
if(key_pulse[7]) key_reg[7] <= 1'b1;
if(key_pulse[6]) key_reg[6] <= 1'b1;
if(key_pulse[5]) key_reg[5] <= 1'b1;
if(key_pulse[4]) key_reg[4] <= 1'b1;
if(key_pulse[3]) key_reg[3] <= 1'b1;
if(key_pulse[2]) key_reg[2] <= 1'b1;
if(key_pulse[1]) key_reg[1] <= 1'b1;
if(key_pulse[0]) key_reg[0] <= 1'b1;
end
end
endmodule |
module AHBlite_Segdisp(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output wire [4:0] disp_data
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
assign disp_data = wr_en_reg ? HWDATA[4:0] : 5'd0;
assign HRDATA = {28'd0,disp_data[3:0]};
endmodule |
module counter(
input clk,
input rstn,
output reg [2:0] cnt
);
always@(posedge clk, negedge rstn) begin
if (!rstn) begin
cnt <= 0;
end else begin
if (cnt == 3'b101) begin
cnt <= 0;
end else begin
cnt <= cnt + 1'b1;
end
end
end
endmodule |
module Keyboard(
input clk,
input rstn,
input key_clear,
input [3 :0] col,
output [3 :0] row,
output key_interrupt,
output [15:0] key_data
);
wire [15:0] key;
keyboard_scan keyboard_scan(
.clk(clk)
,.rstn(rstn)
,.col(col)
,.row(row)
,.key(key)
);
wire [15:0] key_pulse;
keyboard_filter keyboard_filter(
.clk(clk)
,.rstn(rstn)
,.key_in(key)
,.key_pulse(key_pulse)
);
assign key_interrupt = |key_pulse ;
keyboard_reg keyboard_reg(
.rstn(rstn)
,.key_clear(key_clear)
,.key_pulse(key_pulse)
,.key_reg(key_data)
);
endmodule |
module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] douta
);
(* ram_style="block" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("C:/Users/73474/Desktop/M0/Keyboard/keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
douta <= mem[addra];
end
endmodule |
module AHBlite_Block_RAM #(
parameter ADDR_WIDTH = 14)(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [1:0] HRESP,
output wire [ADDR_WIDTH-1:0] BRAM_ADDR,
input wire [31:0] BRAM_RDATA,
output wire [31:0] BRAM_WDATA,
output wire [3:0] BRAM_WRITE
);
assign HRESP = 2'b0;
assign HRDATA = BRAM_RDATA;
wire trans_en;
assign trans_en = HSEL & HTRANS[1];
wire write_en;
assign write_en = trans_en & HWRITE;
wire read_en;
assign read_en = trans_en & (~HWRITE);
wire [3:0] size_dec;
assign size_dec = (HSIZE == 3'b000) ? 4'h1 : (
(HSIZE == 3'b001) ? 4'h3 : (
(HSIZE == 3'b010) ? 4'hf : 4'h0));
reg [3:0] size_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) size_reg <= 0;
else if(write_en & HREADY) size_reg <= size_dec;
end
reg [13:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 0;
else if(trans_en & HREADY) addr_reg <= HADDR[(ADDR_WIDTH+1):2];
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(HREADY) wr_en_reg <= write_en;
else wr_en_reg <= 1'b0;
end
assign BRAM_ADDR = (~read_en) ? addr_reg :
(wr_en_reg ? addr_reg : HADDR[(ADDR_WIDTH+1):2]);
assign HREADYOUT = ~(wr_en_reg & read_en);
assign BRAM_WRITE = wr_en_reg ? size_reg : 4'h0;
assign BRAM_WDATA = HWDATA;
endmodule |
module keyboard_scan(
input clk,
input rstn,
input [3 :0] col,
output reg [3 :0] row = 4'b1110,
output reg [15:0] key
);
reg [31:0] cnt;
reg scan_clk;
always@(posedge clk) begin
if (!rstn) begin
cnt <= 0;
scan_clk <= 1'b0;
end else begin
if(cnt == 2499) begin
cnt <= 0;
scan_clk <= ~scan_clk;
end else begin
cnt <= cnt + 1;
end
end
end
always@(posedge scan_clk) begin
row <= {row[2:0],row[3]};
end
always@(negedge scan_clk) begin
case(row)
4'b1110 : key[3:0] <= col;
4'b1101 : key[7:4] <= col;
4'b1011 : key[11:8] <= col;
4'b0111 : key[15:12] <= col;
default : key <= 0;
endcase
end
endmodule |
module keyboard_filter(
input clk,
input rstn,
input [15: 0] key_in,
output [15: 0] key_pulse // if key pushed, output 1
);
wire [15: 0] key;
assign key = ~key_in;
reg [19 : 0] treg0;
reg [19 : 0] treg1;
reg [19 : 0] treg2;
reg [19 : 0] treg3;
reg [19 : 0] treg4;
reg [19 : 0] treg5;
reg [19 : 0] treg6;
reg [19 : 0] treg7;
reg [19 : 0] treg8;
reg [19 : 0] treg9;
reg [19 : 0] treg10;
reg [19 : 0] treg11;
reg [19 : 0] treg12;
reg [19 : 0] treg13;
reg [19 : 0] treg14;
reg [19 : 0] treg15;
wire [19 : 0] treg0_nxt = treg0 + 1'b1;
wire [19 : 0] treg1_nxt = treg1 + 1'b1;
wire [19 : 0] treg2_nxt = treg2 + 1'b1;
wire [19 : 0] treg3_nxt = treg3 + 1'b1;
wire [19 : 0] treg4_nxt = treg4 + 1'b1;
wire [19 : 0] treg5_nxt = treg5 + 1'b1;
wire [19 : 0] treg6_nxt = treg6 + 1'b1;
wire [19 : 0] treg7_nxt = treg7 + 1'b1;
wire [19 : 0] treg8_nxt = treg8 + 1'b1;
wire [19 : 0] treg9_nxt = treg9 + 1'b1;
wire [19 : 0] treg10_nxt = treg10 + 1'b1;
wire [19 : 0] treg11_nxt = treg11 + 1'b1;
wire [19 : 0] treg12_nxt = treg12 + 1'b1;
wire [19 : 0] treg13_nxt = treg13 + 1'b1;
wire [19 : 0] treg14_nxt = treg14 + 1'b1;
wire [19 : 0] treg15_nxt = treg15 + 1'b1;
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
treg0 <= 20'b0;
treg1 <= 20'b0;
treg2 <= 20'b0;
treg3 <= 20'b0;
treg4 <= 20'b0;
treg5 <= 20'b0;
treg6 <= 20'b0;
treg7 <= 20'b0;
treg8 <= 20'b0;
treg9 <= 20'b0;
treg10 <= 20'b0;
treg11 <= 20'b0;
treg12 <= 20'b0;
treg13 <= 20'b0;
treg14 <= 20'b0;
treg15 <= 20'b0;
end
else begin
if (key[0]) begin
if (treg0 != 20'hfffff)
treg0 <= treg0_nxt;
end
else begin
treg0 <= 20'b0;
end
if (key[1]) begin
if (treg1 != 20'hfffff)
treg1 <= treg1_nxt;
end
else begin
treg1 <= 20'b0;
end
if (key[2]) begin
if (treg2 != 20'hfffff)
treg2 <= treg2_nxt;
end
else begin
treg2 <= 20'b0;
end
if (key[3]) begin
if (treg3 != 20'hfffff)
treg3 <= treg3_nxt;
end
else begin
treg3 <= 20'b0;
end
if (key[4]) begin
if (treg4 != 20'hfffff)
treg4 <= treg4_nxt;
end
else begin
treg4 <= 20'b0;
end
if (key[5]) begin
if (treg5 != 20'hfffff)
treg5 <= treg5_nxt;
end
else begin
treg5 <= 20'b0;
end
if (key[6]) begin
if (treg6 != 20'hfffff)
treg6 <= treg6_nxt;
end
else begin
treg6 <= 20'b0;
end
if (key[7]) begin
if (treg7 != 20'hfffff)
treg7 <= treg7_nxt;
end
else begin
treg7 <= 20'b0;
end
if (key[8]) begin
if (treg8 != 20'hfffff)
treg8 <= treg8_nxt;
end
else begin
treg8 <= 20'b0;
end
if (key[9]) begin
if (treg9 != 20'hfffff)
treg9 <= treg9_nxt;
end
else begin
treg9 <= 20'b0;
end
if (key[10]) begin
if (treg10 != 20'hfffff)
treg10 <= treg10_nxt;
end
else begin
treg10 <= 20'b0;
end
if (key[11]) begin
if (treg11 != 20'hfffff)
treg11 <= treg11_nxt;
end
else begin
treg11 <= 20'b0;
end
if (key[12]) begin
if (treg12 != 20'hfffff)
treg12 <= treg12_nxt;
end
else begin
treg12 <= 20'b0;
end
if (key[13]) begin
if (treg13 != 20'hfffff)
treg13 <= treg13_nxt;
end
else begin
treg13 <= 20'b0;
end
if (key[14]) begin
if (treg14 != 20'hfffff)
treg14 <= treg14_nxt;
end
else begin
treg14 <= 20'b0;
end
if (key[15]) begin
if (treg15 != 20'hfffff)
treg15 <= treg15_nxt;
end
else begin
treg15 <= 20'b0;
end
end
end
assign key_pulse[15] = (treg15 != 20'hfffff) & (treg15_nxt == 20'hfffff);
assign key_pulse[14] = (treg14 != 20'hfffff) & (treg14_nxt == 20'hfffff);
assign key_pulse[13] = (treg13 != 20'hfffff) & (treg13_nxt == 20'hfffff);
assign key_pulse[12] = (treg12 != 20'hfffff) & (treg12_nxt == 20'hfffff);
assign key_pulse[11] = (treg11 != 20'hfffff) & (treg11_nxt == 20'hfffff);
assign key_pulse[10] = (treg10 != 20'hfffff) & (treg10_nxt == 20'hfffff);
assign key_pulse[9] = (treg9 != 20'hfffff) & (treg9_nxt == 20'hfffff);
assign key_pulse[8] = (treg8 != 20'hfffff) & (treg8_nxt == 20'hfffff);
assign key_pulse[7] = (treg7 != 20'hfffff) & (treg7_nxt == 20'hfffff);
assign key_pulse[6] = (treg6 != 20'hfffff) & (treg6_nxt == 20'hfffff);
assign key_pulse[5] = (treg5 != 20'hfffff) & (treg5_nxt == 20'hfffff);
assign key_pulse[4] = (treg4 != 20'hfffff) & (treg4_nxt == 20'hfffff);
assign key_pulse[3] = (treg3 != 20'hfffff) & (treg3_nxt == 20'hfffff);
assign key_pulse[2] = (treg2 != 20'hfffff) & (treg2_nxt == 20'hfffff);
assign key_pulse[1] = (treg1 != 20'hfffff) & (treg1_nxt == 20'hfffff);
assign key_pulse[0] = (treg0 != 20'hfffff) & (treg0_nxt == 20'hfffff);
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port1_en = 1,
/************************/
/*Keyboard enable parameter*/
parameter Port2_en = 1,
/************************/
/*Segdisp enable parameter*/
parameter Port3_en = 1
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*Keyboard OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 key_data/key_clear
/*Insert Keyboard decoder code there*/
assign P2_HSEL = (HADDR[31:4] == 28'h4000000) ? Port2_en : 1'b0;
/***********************************/
//0X40000010 disp_data
/*Insert DISP decoder code there*/
assign P3_HSEL = (HADDR[31:4] == 28'h4000001) ? Port3_en : 1'b0;
/***********************************/
endmodule |
module Segdisp(
input clk,
input rstn,
input [4:0] data_in,
output [5:0] seg_sel,
output [7:0] seg_led
);
wire clk_1ms;
clk_division #(
.DIVCLK_CNTMAX(24_999)
)
sel_clk_division (
.clk_in(clk)
,.rstn(rstn)
,.divclk(clk_1ms)
);
wire [2:0] bit_disp;
counter sel_counter(
.clk(clk_1ms)
,.rstn(rstn)
,.cnt(bit_disp)
);
wire [23:0] data_nxt;
wire en;
reg [23:0] data;
assign data_nxt = {data[19:0],data_in[3:0]};
assign en = data_in[4];
always @(posedge clk) begin
if (!rstn) begin
data <= 24'b0;
end else begin
if (en) begin
data <= data_nxt;
end
end
end
wire [3:0] data_disp;
Mux Mux(
.sel(bit_disp)
,.dina(data[3:0])
,.dinb(data[7:4])
,.dinc(data[11:8])
,.dind(data[15:12])
,.dine(data[19:16])
,.dinf(data[23:20])
,.data_out(data_disp)
);
seg_sel_decoder seg_sel_decoder(
.bit_disp(bit_disp),
.seg_sel(seg_sel)
);
seg_led_decoder seg_led_decoder(
.data_disp(data_disp),
.seg_led(seg_led)
);
endmodule |
module AHBlite_Keyboard(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
input wire [15:0] key_data,
output wire key_clear
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
assign key_clear = wr_en_reg ? HWDATA[0] : 1'b0;
assign HRDATA = {16'h0,key_data};
endmodule |
module Mux(
input [2:0] sel,
input [3:0] dina,
input [3:0] dinb,
input [3:0] dinc,
input [3:0] dind,
input [3:0] dine,
input [3:0] dinf,
output reg [3:0] data_out
);
always@(*)begin
case (sel)
3'b000 : data_out = dina;
3'b001 : data_out = dinb;
3'b010 : data_out = dinc;
3'b011 : data_out = dind;
3'b100 : data_out = dine;
3'b101 : data_out = dinf;
default: data_out = 0;
endcase
end
endmodule |
module AHBlite_LCD(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output wire LCD_CS,
output wire LCD_RS,
output wire LCD_WR,
output wire LCD_RD,
output wire LCD_RST,
output wire [15:0] LCD_DATA,
output wire LCD_BL_CTR
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire read_en;
assign read_en=HSEL&HTRANS[1]&(~HWRITE)&HREADY;
wire write_en;
assign write_en=HSEL&HTRANS[1]&(HWRITE)&HREADY;
reg [5:0] addr;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr <= 6'b0;
else if(read_en || write_en) addr <= HADDR[7:2];
end
reg write_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) write_en_reg <= 1'b0;
else if(write_en) write_en_reg <= 1'b1;
else write_en_reg <= 1'b0;
end
wire LCD_CS_en;
wire LCD_RS_en;
wire LCD_WR_en;
wire LCD_RD_en;
wire LCD_RST_en;
wire LCD_BL_CTR_en;
wire [15:0] LCD_DATA_en;
assign LCD_CS_en = addr == 6'h00 & write_en_reg;
assign LCD_RS_en = addr == 6'h01 & write_en_reg;
assign LCD_WR_en = addr == 6'h02 & write_en_reg;
assign LCD_RD_en = addr == 6'h03 & write_en_reg;
assign LCD_RST_en = addr == 6'h04 & write_en_reg;
assign LCD_BL_CTR_en = addr == 6'h05 & write_en_reg;
assign LCD_DATA_en[0] = addr == 6'h06 & write_en_reg;
assign LCD_DATA_en[1] = addr == 6'h07 & write_en_reg;
assign LCD_DATA_en[2] = addr == 6'h08 & write_en_reg;
assign LCD_DATA_en[3] = addr == 6'h09 & write_en_reg;
assign LCD_DATA_en[4] = addr == 6'h0A & write_en_reg;
assign LCD_DATA_en[5] = addr == 6'h0B & write_en_reg;
assign LCD_DATA_en[6] = addr == 6'h0C & write_en_reg;
assign LCD_DATA_en[7] = addr == 6'h0D & write_en_reg;
assign LCD_DATA_en[8] = addr == 6'h0E & write_en_reg;
assign LCD_DATA_en[9] = addr == 6'h0F & write_en_reg;
assign LCD_DATA_en[10] = addr == 6'h10 & write_en_reg;
assign LCD_DATA_en[11] = addr == 6'h11 & write_en_reg;
assign LCD_DATA_en[12] = addr == 6'h12 & write_en_reg;
assign LCD_DATA_en[13] = addr == 6'h13 & write_en_reg;
assign LCD_DATA_en[14] = addr == 6'h14 & write_en_reg;
assign LCD_DATA_en[15] = addr == 6'h15 & write_en_reg;
reg LCD_CS_reg;
reg LCD_RS_reg;
reg LCD_WR_reg;
reg LCD_RD_reg;
reg LCD_RST_reg;
reg LCD_BL_CTR_reg;
reg [15:0] LCD_DATA_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
LCD_CS_reg <= 1'b0;
LCD_RS_reg <= 1'b0;
LCD_WR_reg <= 1'b0;
LCD_RD_reg <= 1'b0;
LCD_RST_reg <= 1'b0;
LCD_BL_CTR_reg <= 1'b0;
end
else begin
if (LCD_CS_en) begin
LCD_CS_reg <= HWDATA[0];
end
if (LCD_RS_en) begin
LCD_RS_reg <= HWDATA[0];
end
if (LCD_WR_en) begin
LCD_WR_reg <= HWDATA[0];
end
if (LCD_RD_en) begin
LCD_RD_reg <= HWDATA[0];
end
if (LCD_RST_en) begin
LCD_RST_reg <= HWDATA[0];
end
if (LCD_BL_CTR_en) begin
LCD_BL_CTR_reg <= HWDATA[0];
end
//-----------------------------------------------
// DATA
//-----------------------------------------------
if (LCD_DATA_en[0]) begin
LCD_DATA_reg[0] <= HWDATA[0];
end
if (LCD_DATA_en[1]) begin
LCD_DATA_reg[1] <= HWDATA[0];
end
if (LCD_DATA_en[2]) begin
LCD_DATA_reg[2] <= HWDATA[0];
end
if (LCD_DATA_en[3]) begin
LCD_DATA_reg[3] <= HWDATA[0];
end
if (LCD_DATA_en[4]) begin
LCD_DATA_reg[4] <= HWDATA[0];
end
if (LCD_DATA_en[5]) begin
LCD_DATA_reg[5] <= HWDATA[0];
end
if (LCD_DATA_en[6]) begin
LCD_DATA_reg[6] <= HWDATA[0];
end
if (LCD_DATA_en[7]) begin
LCD_DATA_reg[7] <= HWDATA[0];
end
if (LCD_DATA_en[8]) begin
LCD_DATA_reg[8] <= HWDATA[0];
end
if (LCD_DATA_en[9]) begin
LCD_DATA_reg[9] <= HWDATA[0];
end
if (LCD_DATA_en[10]) begin
LCD_DATA_reg[10] <= HWDATA[0];
end
if (LCD_DATA_en[11]) begin
LCD_DATA_reg[11] <= HWDATA[0];
end
if (LCD_DATA_en[12]) begin
LCD_DATA_reg[12] <= HWDATA[0];
end
if (LCD_DATA_en[13]) begin
LCD_DATA_reg[13] <= HWDATA[0];
end
if (LCD_DATA_en[14]) begin
LCD_DATA_reg[14] <= HWDATA[0];
end
if (LCD_DATA_en[15]) begin
LCD_DATA_reg[15] <= HWDATA[0];
end
end
end
//-------------------------------------------------------------------
// HRDATA DECODER
//-------------------------------------------------------------------
assign HRDATA[0] = ( addr == 6'h00 ) ? LCD_CS_reg : (
( addr == 6'h01 ) ? LCD_RS_reg : (
( addr == 6'h02 ) ? LCD_WR_reg : (
( addr == 6'h03 ) ? LCD_RD_reg : (
( addr == 6'h04 ) ? LCD_RST_reg : (
( addr == 6'h05 ) ? LCD_BL_CTR_reg : (
( addr == 6'h06 ) ? LCD_DATA_reg[0] : (
( addr == 6'h07 ) ? LCD_DATA_reg[1] : (
( addr == 6'h08 ) ? LCD_DATA_reg[2] : (
( addr == 6'h09 ) ? LCD_DATA_reg[3] : (
( addr == 6'h0A ) ? LCD_DATA_reg[4] : (
( addr == 6'h0B ) ? LCD_DATA_reg[5] : (
( addr == 6'h0C ) ? LCD_DATA_reg[6] : (
( addr == 6'h0D ) ? LCD_DATA_reg[7] : (
( addr == 6'h0E ) ? LCD_DATA_reg[8] : (
( addr == 6'h0F ) ? LCD_DATA_reg[9] : (
( addr == 6'h10 ) ? LCD_DATA_reg[10] : (
( addr == 6'h11 ) ? LCD_DATA_reg[11] : (
( addr == 6'h12 ) ? LCD_DATA_reg[12] : (
( addr == 6'h13 ) ? LCD_DATA_reg[13] : (
( addr == 6'h14 ) ? LCD_DATA_reg[14] : (
( addr == 6'h15 ) ? LCD_DATA_reg[15] : 1'b0)))))))))))))))))))));
assign HRDATA[31 : 1] = 31'b0;
assign LCD_CS = LCD_CS_reg;
assign LCD_RS = LCD_RS_reg;
assign LCD_WR = LCD_WR_reg;
assign LCD_RD = LCD_RD_reg;
assign LCD_RST = LCD_RST_reg;
assign LCD_BL_CTR = LCD_BL_CTR_reg;
assign LCD_DATA = LCD_DATA_reg;
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port1_en = 1,
/************************/
/*WaterLight enable parameter*/
parameter Port2_en = 0,
/************************/
/*UART enable parameter*/
parameter Port3_en = 1,
/************************/
/*LCD enable parameter*/
parameter Port4_en = 0
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL,
/*LCD OUTPUT SELECTION SIGNAL*/
output wire P4_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0x40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = (HADDR[31:4] == 28'h4000000) ? Port2_en : 1'b0;
/***********************************/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = (HADDR[31:4] == 28'h4000010) ? Port3_en : 1'b0;
/***********************************/
//0X40050000 LCD
/*Insert LCD decoder code there*/
/***********************************/
endmodule |
module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
// LCD
// insert LCD ports
output wire TXD,
input wire RXD
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
wire [31:0] IRQ;
wire interrupt_UART;
/*Connect the IRQ with UART*/
assign IRQ = {31'b0,interrupt_UART};
/***************************/
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b1),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
wire HSEL_P4;
wire [31:0] HADDR_P4;
wire [2:0] HBURST_P4;
wire HMASTLOCK_P4;
wire [3:0] HPROT_P4;
wire [2:0] HSIZE_P4;
wire [1:0] HTRANS_P4;
wire [31:0] HWDATA_P4;
wire HWRITE_P4;
wire HREADY_P4;
wire HREADYOUT_P4;
wire [31:0] HRDATA_P4;
wire HRESP_P4;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3),
// P4
.HSEL_P4 (HSEL_P4),
.HADDR_P4 (HADDR_P4),
.HBURST_P4 (HBURST_P4),
.HMASTLOCK_P4 (HMASTLOCK_P4),
.HPROT_P4 (HPROT_P4),
.HSIZE_P4 (HSIZE_P4),
.HTRANS_P4 (HTRANS_P4),
.HWDATA_P4 (HWDATA_P4),
.HWRITE_P4 (HWRITE_P4),
.HREADY_P4 (HREADY_P4),
.HREADYOUT_P4 (HREADYOUT_P4),
.HRDATA_P4 (HRDATA_P4),
.HRESP_P4 (HRESP_P4)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
// //------------------------------------------------------------------------------
// // AHB WaterLight
// //------------------------------------------------------------------------------
// wire [7:0] WaterLight_mode;
// wire [31:0] WaterLight_speed;
// AHBlite_WaterLight WaterLight_Interface(
// /* Connect to Interconnect Port 2 */
// .HCLK (clk),
// .HRESETn (cpuresetn),
// .HSEL (HSEL_P2),
// .HADDR (HADDR_P2),
// .HPROT (HPROT_P2),
// .HSIZE (HSIZE_P2),
// .HTRANS (HTRANS_P2),
// .HWDATA (HWDATA_P2),
// .HWRITE (HWRITE_P2),
// .HRDATA (HRDATA_P2),
// .HREADY (HREADY_P2),
// .HREADYOUT (HREADYOUT_P2),
// .HRESP (HRESP_P2),
// .WaterLight_mode (WaterLight_mode),
// .WaterLight_speed (WaterLight_speed)
// /**********************************/
// );
//------------------------------------------------------------------------------
// AHB LCD
//------------------------------------------------------------------------------
AHBlite_LCD LCD_Interface(
/* Connect to Interconnect Port 4 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (/*Port 4*/),
.HADDR (/*Port 4*/),
.HPROT (/*Port 4*/),
.HSIZE (/*Port 4*/),
.HTRANS (/*Port 4*/),
.HWDATA (/*Port 4*/),
.HWRITE (/*Port 4*/),
.HRDATA (/*Port 4*/),
.HREADY (/*Port 4*/),
.HREADYOUT (/*Port 4*/),
.HRESP (/*Port 4*/),
.LCD_CS (LCD_CS),
.LCD_RS (LCD_RS),
.LCD_WR (LCD_WR),
.LCD_RD (LCD_RD),
.LCD_RST (LCD_RST),
.LCD_DATA (LCD_DATA),
.LCD_BL_CTR (LCD_BL_CTR)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P1),
.HADDR (HADDR_P1),
.HPROT (HPROT_P1),
.HSIZE (HSIZE_P1),
.HTRANS (HTRANS_P1),
.HWDATA (HWDATA_P1),
.HWRITE (HWRITE_P1),
.HRDATA (HRDATA_P1),
.HREADY (HREADY_P1),
.HREADYOUT (HREADYOUT_P1),
.HRESP (HRESP_P1),
.BRAM_WRADDR (RAMDATA_WADDR),
.BRAM_RDADDR (RAMDATA_RADDR),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB UART
//------------------------------------------------------------------------------
wire state;
wire [7:0] UART_RX_data;
wire [7:0] UART_TX_data;
wire tx_en;
AHBlite_UART UART_Interface(
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P3),
.HADDR (HADDR_P3),
.HPROT (HPROT_P3),
.HSIZE (HSIZE_P3),
.HTRANS (HTRANS_P3),
.HWDATA (HWDATA_P3),
.HWRITE (HWRITE_P3),
.HRDATA (HRDATA_P3),
.HREADY (HREADY_P3),
.HREADYOUT (HREADYOUT_P3),
.HRESP (HRESP_P3),
.UART_RX (UART_RX_data),
.state (state),
.tx_en (tx_en),
.UART_TX (UART_TX_data)
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
// //------------------------------------------------------------------------------
// // WaterLight
// //------------------------------------------------------------------------------
// WaterLight WaterLight(
// .WaterLight_mode(WaterLight_mode),
// .WaterLight_speed(WaterLight_speed),
// .clk(clk),
// .RSTn(cpuresetn),
// .LED(LED),
// .LEDclk(LEDclk)
// );
//------------------------------------------------------------------------------
// UART
//------------------------------------------------------------------------------
wire clk_uart;
wire bps_en;
wire bps_en_rx,bps_en_tx;
assign bps_en = bps_en_rx | bps_en_tx;
clkuart_pwm clkuart_pwm(
.clk(clk),
.RSTn(cpuresetn),
.clk_uart(clk_uart),
.bps_en(bps_en)
);
UART_RX UART_RX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.RXD(RXD),
.data(UART_RX_data),
.interrupt(interrupt_UART),
.bps_en(bps_en_rx)
);
UART_TX UART_TX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.data(UART_TX_data),
.tx_en(tx_en),
.TXD(TXD),
.state(state),
.bps_en(bps_en_tx)
);
endmodule |
module top(
input wire clk,
output wire [7:0] pmod1,
output wire [7:0] pmod2,
output wire [7:0] pmod3,
output wire [7:0] pmod4,
output wire [7:0] pmod5,
output wire [7:0] pmod6,
output wire gp6, gp12, gp13, gp14, gp15, gp16, ce1,
output wire led1, led2,
// output wire spi_clk, // Can't do this - see below for spi clock pin control.
output wire spi_cs,
output wire [3:0] spi_sdio,
input wire button1, button2
);
localparam CLK_SPEED = 240_000;
localparam CLK_W = $clog2(CLK_SPEED);
reg [CLK_W-1:0] counter = 0;
reg blink = 0;
reg [47:0] shift = 48'b1;
always @(posedge clk) begin
counter <= counter + 1;
if(counter == CLK_SPEED - 1) begin
counter <= 0;
blink <= !blink;
shift <= {shift[0], shift[47:1]};
end
end
// flash all the pmods in sequence
assign pmod1 = shift[7:0];
assign pmod2 = shift[15:8];
assign pmod3 = shift[23:16];
assign pmod4 = shift[31:24];
assign pmod5 = shift[39:32];
assign pmod6 = shift[47:40];
// blink all the gpios
assign gp6 = blink;
assign gp12 = blink;
assign gp13 = blink;
assign gp14 = blink;
assign gp15 = blink;
assign gp16 = blink;
assign ce1 = blink;
assign led1 = button1;
assign led2 = button2;
// https://github.com/ironsteel/nes_ecp5/blob/master/top.v#L70
// the spi clock pin is not available in the lpf file, have to use the USRMCLK primitive
wire spi_clk = blink;
wire tristate = 1'b0;
USRMCLK u1 (.USRMCLKI(spi_clk), .USRMCLKTS(tristate));
assign spi_sdio = blink ? 4'b1111 : 4'b0000;
assign spi_cs = blink;
endmodule |
module systolic#(
parameter ARRAY_SIZE = 8,
parameter SRAM_DATA_WIDTH = 32,
parameter DATA_WIDTH = 8
)
(
input clk,
input srstn,
input alu_start, //enable signal, can start do mul and add plus shift
input [8:0] cycle_num,
//input pos_table [0:ARRAY_SIZE-1] [0:ARRAY_SIZE-1],
input [SRAM_DATA_WIDTH-1:0] sram_rdata_w0, //32 weight queue
input [SRAM_DATA_WIDTH-1:0] sram_rdata_w1,
input [SRAM_DATA_WIDTH-1:0] sram_rdata_d0, //32 data queue
input [SRAM_DATA_WIDTH-1:0] sram_rdata_d1,
input [5:0] matrix_index,
output reg signed [(ARRAY_SIZE*(DATA_WIDTH+DATA_WIDTH+5))-1:0] mul_outcome
);
localparam FIRST_OUT = ARRAY_SIZE+1;
localparam PARALLEL_START = ARRAY_SIZE+ARRAY_SIZE+1;
localparam OUTCOME_WIDTH = DATA_WIDTH+DATA_WIDTH+5;
reg signed [OUTCOME_WIDTH-1:0] matrix_mul_2D [0:ARRAY_SIZE-1] [0:ARRAY_SIZE-1];
reg signed [OUTCOME_WIDTH-1:0] matrix_mul_2D_nx [0:ARRAY_SIZE-1] [0:ARRAY_SIZE-1];
reg signed [DATA_WIDTH-1:0] data_queue [0:ARRAY_SIZE-1] [0:ARRAY_SIZE-1];
reg signed [DATA_WIDTH-1:0] weight_queue [0:ARRAY_SIZE-1] [0:ARRAY_SIZE-1];
reg signed [DATA_WIDTH+DATA_WIDTH-1:0] mul_result;
reg [5:0] upper_bound;
reg [5:0] lower_bound;
integer i,j;
//------data, weight------
always@(posedge clk) begin
if(~srstn) begin
for(i=0; i<ARRAY_SIZE; i=i+1) begin
for(j=0; j<ARRAY_SIZE; j=j+1) begin
weight_queue[i][j] <= 0;
data_queue[i][j] <= 0;
end
end
end
else begin
if(alu_start) begin
//weight shifting(a0)
for(i=0; i<4; i=i+1) begin
weight_queue[0][i] <= sram_rdata_w0[31-8*i-:8];
weight_queue[0][i+4] <= sram_rdata_w1[31-8*i-:8];
end
for(i=1; i<ARRAY_SIZE; i=i+1)
for(j=0; j<ARRAY_SIZE; j=j+1)
weight_queue[i][j] <= weight_queue[i-1][j];
//data shifting(b0)
for(i=0; i<4; i=i+1) begin
data_queue[i][0] <= sram_rdata_d0[31-8*i-:8];
data_queue[i+4][0] <= sram_rdata_d1[31-8*i-:8];
end
for(i=0; i<ARRAY_SIZE; i=i+1)
for(j=1; j<ARRAY_SIZE; j=j+1)
data_queue[i][j] <= data_queue[i][j-1];
end
end
end
//-------multiplication unit------------
always@(posedge clk) begin
if(~srstn) begin
for(i=0; i<ARRAY_SIZE; i=i+1)
for(j=0; j<ARRAY_SIZE; j=j+1)
matrix_mul_2D[i][j] <= 0;
end
else begin
for(i=0; i<ARRAY_SIZE; i=i+1)
for(j=0; j<ARRAY_SIZE; j=j+1)
matrix_mul_2D[i][j] <= matrix_mul_2D_nx[i][j];
end
end
always@(*) begin
if(alu_start) begin //based on the mul_row_num, decode how many row operations need to do
for(i=0; i<ARRAY_SIZE; i=i+1) begin
for(j=0; j<ARRAY_SIZE; j=j+1) begin
//multiplication and adding
if( (cycle_num>=FIRST_OUT && (i+j)==(cycle_num-FIRST_OUT)%16) || (cycle_num >=PARALLEL_START && (i+j)==(cycle_num-PARALLEL_START)%16) ) begin
mul_result = weight_queue[i][j] * data_queue[i][j];
matrix_mul_2D_nx[i][j] = { {5{mul_result[15]}} , mul_result };
end
else if( cycle_num>=1 && i+j<=(cycle_num-1) ) begin
mul_result = weight_queue[i][j] * data_queue[i][j];
matrix_mul_2D_nx[i][j] = matrix_mul_2D[i][j] + { {5{mul_result[15]}} , mul_result };
end
else begin
mul_result = 0;
matrix_mul_2D_nx[i][j] = matrix_mul_2D[i][j];
end
end
end
end
else begin
mul_result = 0;
for(i=0; i<ARRAY_SIZE; i=i+1)
for(j=0; j<ARRAY_SIZE; j=j+1)
matrix_mul_2D_nx[i][j] = matrix_mul_2D[i][j];
end
end
//------output data: mul_outcome(indexed by matrix_index)------
always@(*) begin
if(matrix_index < ARRAY_SIZE) begin
upper_bound = matrix_index;
lower_bound = matrix_index + ARRAY_SIZE;
end
else begin
upper_bound = matrix_index - ARRAY_SIZE;
lower_bound = matrix_index;
end
//initialization
for(i=0; i<ARRAY_SIZE*OUTCOME_WIDTH; i=i+1)
mul_outcome[i] = 0;
//fetch data
for(i=0; i<ARRAY_SIZE; i=i+1) begin
for(j=0; j<ARRAY_SIZE-i; j=j+1) begin
if(i+j == upper_bound)
mul_outcome[i*OUTCOME_WIDTH+:OUTCOME_WIDTH] = matrix_mul_2D[i][j];
end
end
for(i=1; i<ARRAY_SIZE; i=i+1) begin
for(j=ARRAY_SIZE-i; j<ARRAY_SIZE; j=j+1) begin
if(i+j == lower_bound)
mul_outcome[i*OUTCOME_WIDTH+:OUTCOME_WIDTH] = matrix_mul_2D[i][j];
end
end
end
endmodule |
module write_out#(
parameter ARRAY_SIZE = 8,
parameter OUTPUT_DATA_WIDTH = 16
)
(
input clk,
input srstn,
input sram_write_enable,
input [1:0] data_set,
input [5:0] matrix_index,
input signed [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] quantized_data,
output reg sram_write_enable_a0,
output reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_a,
output reg [5:0] sram_waddr_a,
output reg sram_write_enable_b0,
output reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_b,
output reg [5:0] sram_waddr_b,
output reg sram_write_enable_c0,
output reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_c,
output reg [5:0] sram_waddr_c
);
integer i;
localparam MAX_INDEX = ARRAY_SIZE - 1;
//output flip-flop
reg sram_write_enable_a0_nx;
reg sram_write_enable_b0_nx;
reg sram_write_enable_c0_nx;
reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_a_nx;
reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_b_nx;
reg [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_c_nx;
reg [5:0] sram_waddr_a_nx;
reg [5:0] sram_waddr_b_nx;
reg [5:0] sram_waddr_c_nx;
//---sequential logic-----
always@(posedge clk) begin
if(~srstn) begin
sram_write_enable_a0 <= 1;
sram_write_enable_b0 <= 1;
sram_write_enable_c0 <= 1;
sram_wdata_a <= 0;
sram_wdata_b <= 0;
sram_wdata_c <= 0;
sram_waddr_a <= 0;
sram_waddr_b <= 0;
sram_waddr_c <= 0;
end
else begin
sram_write_enable_a0 <= sram_write_enable_a0_nx;
sram_write_enable_b0 <= sram_write_enable_b0_nx;
sram_write_enable_c0 <= sram_write_enable_c0_nx;
sram_wdata_a <= sram_wdata_a_nx;
sram_wdata_b <= sram_wdata_b_nx;
sram_wdata_c <= sram_wdata_c_nx;
sram_waddr_a <= sram_waddr_a_nx;
sram_waddr_b <= sram_waddr_b_nx;
sram_waddr_c <= sram_waddr_c_nx;
end
end
//for a0, write_enable_X0 = 0 means write
always@(*) begin
if(sram_write_enable) begin
case(data_set)
0: begin
if(matrix_index < ARRAY_SIZE) begin
sram_write_enable_a0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i<=matrix_index)
sram_wdata_a_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_a_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_a_nx = matrix_index;
end
else begin //mix type
sram_write_enable_a0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i < 15-matrix_index)
sram_wdata_a_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[(i+1+(matrix_index-ARRAY_SIZE))*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_a_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_a_nx = matrix_index;
end
end
default: begin
sram_write_enable_a0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_a_nx[i] = 0;
sram_waddr_a_nx = 0;
end
endcase
end
else begin
sram_write_enable_a0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_a_nx[i] = 0;
sram_waddr_a_nx = 0;
end
end
//for b0, write_enable_X0 = 0 means write
always@(*) begin
if(sram_write_enable) begin
case(data_set)
0: begin
if(matrix_index < ARRAY_SIZE) begin //all occupied by a
sram_write_enable_b0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_b_nx[i] = 0;
sram_waddr_b_nx = 0;
end
else begin //mix type
sram_write_enable_b0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i <= matrix_index-ARRAY_SIZE)
sram_wdata_b_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_b_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_b_nx = matrix_index - ARRAY_SIZE;
end
end
1: begin
if(matrix_index < ARRAY_SIZE) begin
sram_write_enable_b0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i < ARRAY_SIZE-matrix_index-1)
sram_wdata_b_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[(i+1+matrix_index)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_b_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_b_nx = matrix_index + ARRAY_SIZE;
end
else begin
sram_write_enable_b0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_b_nx[i] = 0;
sram_waddr_b_nx = 0;
end
end
default: begin
sram_write_enable_b0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_b_nx[i] = 0;
sram_waddr_b_nx = 0;
end
endcase
end
else begin
sram_write_enable_b0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_b_nx[i] = 0;
sram_waddr_b_nx = 0;
end
end
//for c0, write_enable_X0 = 0 means write
always@(*) begin
if(sram_write_enable) begin
case(data_set)
1: begin
if(matrix_index < ARRAY_SIZE) begin //all occupied by a
sram_write_enable_c0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i<=matrix_index)
sram_wdata_c_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_c_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_c_nx = matrix_index;
end
else begin //mix type
sram_write_enable_c0_nx = 0;
for(i=0; i<ARRAY_SIZE; i=i+1) begin
if(i < 15-matrix_index)
sram_wdata_c_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = quantized_data[(i+1+(matrix_index-ARRAY_SIZE))*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH];
else
sram_wdata_c_nx[(MAX_INDEX-i)*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = 0;
end
sram_waddr_c_nx = matrix_index;
end
end
default: begin
sram_write_enable_c0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_c_nx[i] = 0;
sram_waddr_c_nx = 0;
end
endcase
end
else begin
sram_write_enable_c0_nx = 1;
for(i=0; i<ARRAY_SIZE*OUTPUT_DATA_WIDTH; i=i+1)
sram_wdata_c_nx[i] = 0;
sram_waddr_c_nx = 0;
end
end
endmodule |
module systolic_controll#(
parameter ARRAY_SIZE = 8
)
(
input clk,
input srstn,
input tpu_start, //total enable signal
output reg sram_write_enable,
//addr_sel
output reg [6:0] addr_serial_num,
//systolic array
output reg alu_start, //shift & multiplcation start
output reg [8:0] cycle_num, //for systolic.v
output reg [5:0] matrix_index, //index for write-out SRAM data
output reg [1:0] data_set,
output reg tpu_done //done signal
);
localparam IDLE = 3'd0, LOAD_DATA = 3'd1, WAIT1 = 3'd2, ROLLING = 3'd3;
//----general variable----
reg [2:0] state;
reg [2:0] state_nx;
reg [1:0] data_set_nx;
reg tpu_done_nx;
//----addr_sel----
reg [6:0] addr_serial_num_nx;
//----systolic array----
reg [8:0] cycle_num_nx;
reg [5:0] matrix_index_nx;
//----initialization----
always@(posedge clk) begin
if(~srstn) begin
state <= IDLE;
data_set <= 0;
cycle_num <= 0;
matrix_index <= 0;
addr_serial_num <= 0;
tpu_done <= 0;
end
else begin
state <= state_nx;
data_set <= data_set_nx;
cycle_num <= cycle_num_nx;
matrix_index <= matrix_index_nx;
addr_serial_num <= addr_serial_num_nx;
tpu_done <= tpu_done_nx;
end
end
//----state transition, tpu_done signal----
always@(*) begin
case(state)
IDLE: begin
if(tpu_start)
state_nx = LOAD_DATA;
else
state_nx = IDLE;
tpu_done_nx = 0;
end
LOAD_DATA: begin
state_nx = WAIT1;
tpu_done_nx = 0;
end
WAIT1: begin
state_nx = ROLLING;
tpu_done_nx = 0;
end
ROLLING: begin
if(matrix_index==15 && data_set == 1) begin
state_nx = IDLE;
tpu_done_nx = 1;
end
else begin
state_nx = ROLLING;
tpu_done_nx = 0;
end
end
default: begin
state_nx = IDLE;
tpu_done_nx = 0;
end
endcase
end
//-----addr_sel: addr_serial_num-----
always@(*) begin
case(state)
IDLE: begin
if(tpu_start)
addr_serial_num_nx = 0;
else
addr_serial_num_nx = addr_serial_num;
end
LOAD_DATA:
addr_serial_num_nx = 1;
WAIT1:
addr_serial_num_nx = 2;
ROLLING: begin
if(addr_serial_num == 127)
addr_serial_num_nx = addr_serial_num;
else
addr_serial_num_nx = addr_serial_num + 1;
end
default:
addr_serial_num_nx = 0;
endcase
end
//------systolic: alu_start, cycle_num, matrix_index, data_set,
//sram_write_enable------
always@(*) begin
case(state)
IDLE: begin
alu_start = 0;
cycle_num_nx = 0;
matrix_index_nx = 0;
data_set_nx = 0;
sram_write_enable = 0;
end
LOAD_DATA: begin
alu_start = 0;
cycle_num_nx = 0;
matrix_index_nx = 0;
data_set_nx = 0;
sram_write_enable = 0;
end
WAIT1: begin
alu_start = 0;
cycle_num_nx = 0;
matrix_index_nx = 0;
data_set_nx = 0;
sram_write_enable = 0;
end
ROLLING: begin
alu_start = 1;
cycle_num_nx = cycle_num + 1;
if(cycle_num >= ARRAY_SIZE+1) begin
if(matrix_index == 15) begin
matrix_index_nx = 0;
data_set_nx = data_set + 1;
end
else begin
matrix_index_nx = matrix_index + 1;
data_set_nx = data_set;
end
sram_write_enable = 1;
end
else begin
matrix_index_nx = 0;
data_set_nx = data_set;
sram_write_enable = 0;
end
end
default: begin
alu_start = 0;
cycle_num_nx = 0;
matrix_index_nx = 0;
data_set_nx = 0;
sram_write_enable = 0;
end
endcase
end
endmodule |
module quantize#(
parameter ARRAY_SIZE = 8,
parameter SRAM_DATA_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter OUTPUT_DATA_WIDTH = 16
)
(
input signed [ARRAY_SIZE*(DATA_WIDTH+DATA_WIDTH+5)-1:0] ori_data,
output reg signed [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] quantized_data
);
localparam max_val = 32767,min_val = -32768;
localparam ORI_WIDTH = DATA_WIDTH+DATA_WIDTH+5;
reg signed [ORI_WIDTH-1:0] ori_shifted_data;
integer i;
//quantize the data from 32 bit(16: integer, 8: precision) to 16 bit(8: integer, 8: precision)
always@* begin
for(i=0; i<ARRAY_SIZE; i=i+1) begin
ori_shifted_data = ori_data[i*ORI_WIDTH +: ORI_WIDTH];
if(ori_shifted_data >= max_val) quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = max_val;
else if(ori_shifted_data <= min_val) quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = min_val;
else quantized_data[i*OUTPUT_DATA_WIDTH +: OUTPUT_DATA_WIDTH] = ori_shifted_data[OUTPUT_DATA_WIDTH-1:0];
end
end
endmodule |
module tpu_top#(
parameter ARRAY_SIZE = 8,
parameter SRAM_DATA_WIDTH = 32,
parameter DATA_WIDTH = 8,
parameter OUTPUT_DATA_WIDTH = 16
)
(
input clk,
input srstn,
input tpu_start,
//input data for (data, weight) from eight SRAM
input [SRAM_DATA_WIDTH-1:0] sram_rdata_w0,
input [SRAM_DATA_WIDTH-1:0] sram_rdata_w1,
input [SRAM_DATA_WIDTH-1:0] sram_rdata_d0,
input [SRAM_DATA_WIDTH-1:0] sram_rdata_d1,
//output addr for (data, weight) from eight SRAM
output [9:0] sram_raddr_w0,
output [9:0] sram_raddr_w1,
output [9:0] sram_raddr_d0,
output [9:0] sram_raddr_d1,
//write to three SRAN for comparison
output sram_write_enable_a0,
output [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_a,
output [5:0] sram_waddr_a,
output sram_write_enable_b0,
output [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_b,
output [5:0] sram_waddr_b,
output sram_write_enable_c0,
output [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] sram_wdata_c,
output [5:0] sram_waddr_c,
output tpu_done
);
localparam ORI_WIDTH = DATA_WIDTH+DATA_WIDTH+5;
//----addr_sel parameter----
wire [6:0] addr_serial_num;
//----quantized parameter----
wire signed [ARRAY_SIZE*ORI_WIDTH-1:0] ori_data;
wire signed [ARRAY_SIZE*OUTPUT_DATA_WIDTH-1:0] quantized_data;
//-----systolic parameter----
wire alu_start;
wire [8:0] cycle_num;
wire [5:0] matrix_index;
//----ststolic_controll parameter---
wire sram_write_enable;
wire [1:0] data_set;
//----write_out parameter----
// nothing XD
//----addr_sel module----
addr_sel addr_sel
(
//input
.clk(clk),
.addr_serial_num(addr_serial_num),
//output
.sram_raddr_w0(sram_raddr_w0),
.sram_raddr_w1(sram_raddr_w1),
.sram_raddr_d0(sram_raddr_d0),
.sram_raddr_d1(sram_raddr_d1)
);
//----quantize module----
quantize #(
.ARRAY_SIZE(ARRAY_SIZE),
.SRAM_DATA_WIDTH(SRAM_DATA_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH)
) quantize
(
//input
.ori_data(ori_data),
//output
.quantized_data(quantized_data)
);
//----systolic module----
systolic #(
.ARRAY_SIZE(ARRAY_SIZE),
.SRAM_DATA_WIDTH(SRAM_DATA_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) systolic
(
//input
.clk(clk),
.srstn(srstn),
.alu_start(alu_start),
.cycle_num(cycle_num),
.sram_rdata_w0(sram_rdata_w0),
.sram_rdata_w1(sram_rdata_w1),
.sram_rdata_d0(sram_rdata_d0),
.sram_rdata_d1(sram_rdata_d1),
.matrix_index(matrix_index),
//output
.mul_outcome(ori_data)
);
//----systolic_controller module----
systolic_controll #(
.ARRAY_SIZE(ARRAY_SIZE)
) systolic_controll
(
//input
.clk(clk),
.srstn(srstn),
.tpu_start(tpu_start),
//output
.sram_write_enable(sram_write_enable),
.addr_serial_num(addr_serial_num),
.alu_start(alu_start),
.cycle_num(cycle_num),
.matrix_index(matrix_index),
.data_set(data_set),
.tpu_done(tpu_done)
);
//----write_out module----
write_out #(
.ARRAY_SIZE(ARRAY_SIZE),
.OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH)
) write_out
(
//input
.clk(clk),
.srstn(srstn),
.sram_write_enable(sram_write_enable),
.data_set(data_set),
.matrix_index(matrix_index),
.quantized_data(quantized_data),
//output
.sram_write_enable_a0(sram_write_enable_a0),
.sram_wdata_a(sram_wdata_a),
.sram_waddr_a(sram_waddr_a),
.sram_write_enable_b0(sram_write_enable_b0),
.sram_wdata_b(sram_wdata_b),
.sram_waddr_b(sram_waddr_b),
.sram_write_enable_c0(sram_write_enable_c0),
.sram_wdata_c(sram_wdata_c),
.sram_waddr_c(sram_waddr_c)
);
endmodule |
module addr_sel
(
input clk,
input [6:0] addr_serial_num, //max = 126, setting all of the addr127 = 0
//sel for w0~w7
output reg [9:0] sram_raddr_w0, //queue 0~3
output reg [9:0] sram_raddr_w1, //queue 4~7
//sel for d0~d7
output reg [9:0] sram_raddr_d0,
output reg [9:0] sram_raddr_d1
);
wire [9:0] sram_raddr_w0_nx; //queue 0~3
wire [9:0] sram_raddr_w1_nx; //queue 4~7
//sel for d0~d7
wire [9:0] sram_raddr_d0_nx;
wire [9:0] sram_raddr_d1_nx;
always@(posedge clk) begin //fit in output flip-flop
sram_raddr_w0 <= sram_raddr_w0_nx;
sram_raddr_w1 <= sram_raddr_w1_nx;
sram_raddr_d0 <= sram_raddr_d0_nx;
sram_raddr_d1 <= sram_raddr_d1_nx;
end
assign sram_raddr_w0_nx = (addr_serial_num<=98)? { {3{1'd0}} , addr_serial_num} : 127;
assign sram_raddr_w1_nx = (addr_serial_num>=4 && addr_serial_num<=102)? { {3{1'd0}} , addr_serial_num-7'd4} : 127;
assign sram_raddr_d0_nx = (addr_serial_num<=98)? { {3{1'd0}} , addr_serial_num} : 127;
assign sram_raddr_d1_nx = (addr_serial_num>=4 && addr_serial_num<=102)? { {3{1'd0}} , addr_serial_num-7'd4} : 127;
endmodule |
module lab1(
//////////////////////////////////////////////////////////////////////////////////////
// FPGA Pins
//////////////////////////////////////////////////////////////////////////////////////
// Clock pins
CLOCK_50,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// Pushbuttons
KEY,
// LEDs
LEDR,
// Slider Switches
SW,
//////////////////////////////////////////////////////////////////////////////////////
// HPS Pins
//////////////////////////////////////////////////////////////////////////////////////
// DDR3 SRAM
HPS_DDR3_A,
HPS_DDR3_BA,
HPS_DDR3_CAS_n,
HPS_DDR3_CKE,
HPS_DDR3_CK_n,
HPS_DDR3_CK_p,
HPS_DDR3_CS_n,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_n,
HPS_DDR3_DQS_p,
HPS_DDR3_ODT,
HPS_DDR3_RAS_n,
HPS_DDR3_RESET_n,
HPS_DDR3_WE_n,
HPS_DDR3_RZQ
);
//========================================================================================
// PORT Declarations
//========================================================================================
//////////////////////////////////////////////////////////////////////////////////////////
// FPGA Pins
//////////////////////////////////////////////////////////////////////////////////////////
input CLOCK_50;
input [3:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
//////////////////////////////////////////////////////////////////////////////////////////
// HPS Pins
//////////////////////////////////////////////////////////////////////////////////////////
// DDR3 SRAM
output [14:0] HPS_DDR3_A;
output [2:0] HPS_DDR3_BA;
output HPS_DDR3_CAS_n;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_n;
output HPS_DDR3_CK_p;
output HPS_DDR3_CS_n;
output [3:0] HPS_DDR3_DM;
inout [31:0] HPS_DDR3_DQ;
inout [3:0] HPS_DDR3_DQS_n;
inout [3:0] HPS_DDR3_DQS_p;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_n;
output HPS_DDR3_RESET_n;
output HPS_DDR3_WE_n;
input HPS_DDR3_RZQ;
//========================================================================================
// REG/WIRE declarations
//========================================================================================
wire [31:0] hex3_hex0;
wire [15:0] hex5_hex4;
assign HEX0 = ~hex3_hex0[6:0];
assign HEX1 = ~hex3_hex0[14:8];
assign HEX2 = ~hex3_hex0[22:16];
assign HEX3 = ~hex3_hex0[30:24];
assign HEX4 = ~hex5_hex4[6:0];
assign HEX5 = ~hex5_hex4[14:8];
//========================================================================================
// Structural Coding
//========================================================================================
mysystem u0 (
.clk_clk (CLOCK_50), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
.memory_mem_a (HPS_DDR3_A), // memory.mem_a
.memory_mem_ba (HPS_DDR3_BA), // .mem_ba
.memory_mem_cas_n (HPS_DDR3_CAS_n), // .mem_cas_n
.memory_mem_cke (HPS_DDR3_CKE), // .mem_cke
.memory_mem_ck_n (HPS_DDR3_CK_n), // .mem_ck_n
.memory_mem_ck (HPS_DDR3_CK_p), // .mem_ck
.memory_mem_cs_n (HPS_DDR3_CS_n), // .mem_cs_n
.memory_mem_dm (HPS_DDR3_DM), // .mem_dm
.memory_mem_dq (HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs_n (HPS_DDR3_DQS_n), // .mem_dqs_n
.memory_mem_dqs (HPS_DDR3_DQS_p), // .mem_dqs
.memory_mem_odt (HPS_DDR3_ODT), // .mem_odt
.memory_mem_ras_n (HPS_DDR3_RAS_n), // .mem_ras_n
.memory_mem_reset_n (HPS_DDR3_RESET_n), // .mem_reset_n
.memory_mem_we_n (HPS_DDR3_WE_n), // .mem_we_n
.memory_oct_rzqin (HPS_DDR3_RZQ), // .oct_rzqin
.pushbuttons_export (~KEY[3:0]), // pushbuttons.export
.hex3_hex0_export (hex3_hex0), // hex3_hex0.export
.hex5_hex4_export (hex5_hex4), // hex5_hex4.export
.rled_export (LEDR), // rled.export
.switches_export (SW) // switches.export
);
endmodule // lab1 |
module matrixMultiplier (
clk,
reset,
slave_address,
slave_read,
slave_write,
slave_readdata,
slave_writedata,
slave_byteenable
);
// BE SURE TO USE FULL AVALON (not lightweight) BUS IN QSYS
parameter DATA_WIDTH = 64;
parameter WIDTH_HEIGHT = 16;
parameter TPU_DATA_WIDTH = WIDTH_HEIGHT * 8;
input clk;
input reset;
input [9:0] slave_address;
input slave_read;
input slave_write;
input [DATA_WIDTH-1:0] slave_writedata;
input [(DATA_WIDTH/8)-1:0] slave_byteenable;
output reg [DATA_WIDTH-1:0] slave_readdata;
/* TODO:
*
* - inputMem_wr_en & weightMem_wr_en />
* - outputMem_rd_en />
* - inputMem_wr_addr & weightMem_wr_addr />
* - outputMem_rd_addr />
* - inputMem_wr_data & weightMem_wr_data />
* - outputMem_rd_data />
* - Control Signals (Write) />
* + reset />
* + active />
* - inputMem_rd_addr_base />
* - outputMem_wr_addr_base />
* + fill_fifo />
* - weightMem_rd_addr_base />
* + drain_fifo />
* - Control Signals (Read) />
* + mem_to_fifo_done />
* + fifo_to_arr_done />
* + output_done />
* - slave_readdata />
*/
// ========================================
// --------- wr/rd enables ----------------
// ========================================
wire [WIDTH_HEIGHT - 1:0] inputMem_wr_en;
wire [WIDTH_HEIGHT - 1:0] weightMem_wr_en;
wire [WIDTH_HEIGHT - 1:0] outputMem_rd_en;
assign inputMem_wr_en = {16{slave_write & (slave_address[9:8] == `INPUT_OFFSET)}};
assign weightMem_wr_en = {16{slave_write & (slave_address[9:8] == `WEIGHT_OFFSET)}};
assign outputMem_rd_en = {16{slave_read & (slave_address[9:8] == `OUTPUT_OFFSET)}};
// ========================================
// ------------ wr/rd addresses -----------
// ========================================
wire [TPU_DATA_WIDTH - 1:0] inputMem_wr_addr;
wire [TPU_DATA_WIDTH - 1:0] weightMem_wr_addr;
wire [TPU_DATA_WIDTH - 1:0] outputMem_rd_addr;
assign inputMem_wr_addr = {16{slave_address[7:0]}};
assign weightMem_wr_addr = {16{slave_address[7:0]}};
assign outputMem_rd_addr = {16{slave_address[7:0]}};
// ========================================
// ------------ wr/rd data ----------------
// ========================================
wire [TPU_DATA_WIDTH - 1:0] inputMem_wr_data;
wire [TPU_DATA_WIDTH - 1:0] weightMem_wr_data;
// Driven below by TPU output, then assigned to slave_readdata
wire [TPU_DATA_WIDTH - 1:0] outputMem_rd_data;
assign inputMem_wr_data = {2{slave_writedata}};
assign weightMem_wr_data = {2{slave_writedata}};
// ========================================
// ----------- Control (inputs) -----------
// ========================================
reg [TPU_DATA_WIDTH - 1:0] inputMem_rd_addr_base;
reg [TPU_DATA_WIDTH - 1:0] weightMem_rd_addr_base;
reg [TPU_DATA_WIDTH - 1:0] outputMem_wr_addr_base;
reg reset_tpu;
reg fill_fifo;
reg drain_fifo;
reg multiply;
always @(posedge clk) begin
if ((slave_write == 1) && (slave_address[9:8] == `CONTROL_OFFSET)) begin
case (slave_writedata[3:0])
`RESET: begin
reset_tpu <= 1'b1;
fill_fifo <= 1'b0;
drain_fifo <= 1'b0;
multiply <= 1'b0;
weightMem_rd_addr_base <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
inputMem_rd_addr_base <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
outputMem_wr_addr_base <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
end
`FILL_FIFO: begin
reset_tpu <= 1'b0;
fill_fifo <= 1'b1;
drain_fifo <= 1'b0;
multiply <= 1'b0;
weightMem_rd_addr_base <= {16{slave_writedata[11:4]}};
end
`DRAIN_FIFO: begin
reset_tpu <= 1'b0;
fill_fifo <= 1'b0;
drain_fifo <= 1'b1;
multiply <= 1'b0;
end
`MULTIPLY: begin
reset_tpu <= 1'b0;
fill_fifo <= 1'b0;
drain_fifo <= 1'b0;
multiply <= 1'b1;
inputMem_rd_addr_base <= {16{slave_writedata[11:4]}};
outputMem_wr_addr_base <= {16{slave_writedata[19:12]}};
end
endcase // slave_writedata[3:0]
end // if ((slave_write == 1) && (slave_address[9:8] == `CONTROL_OFFSET))
end // always @(posedge clk)
// ========================================
// --------- Bus Read Side ----------------
// ========================================
wire mem_to_fifo_done;
wire fifo_to_arr_done;
wire output_done;
always @(*) begin
slave_readdata = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
case(slave_address[9:8])
`CONTROL_OFFSET: slave_readdata = { 61'd0, output_done, fifo_to_arr_done, mem_to_fifo_done};
`OUTPUT_OFFSET: slave_readdata = outputMem_rd_data[63:0];
default: slave_readdata = 64'h0000_0000_0000_0000_0000_0000_0000_0000;
endcase
end // alwasy @(*)
// ========================================
// ------------ TPU Instantiation ---------
// ========================================
top TPU (
.clk (clk),
.reset (reset_tpu),
.active (multiply),
.inputMem_wr_en (inputMem_wr_en),
.inputMem_wr_addr (inputMem_wr_addr),
.inputMem_wr_data (inputMem_wr_data),
.inputMem_rd_addr_base (inputMem_rd_addr_base),
.outputMem_rd_en (outputMem_rd_en),
.outputMem_rd_addr (outputMem_rd_addr),
.outputMem_rd_data (outputMem_rd_data),
.outputMem_wr_addr_base(outputMem_wr_addr_base),
.weightMem_wr_en (weightMem_wr_en),
.weightMem_wr_addr (weightMem_wr_addr),
.weightMem_wr_data (weightMem_wr_data),
.weightMem_rd_addr_base(weightMem_rd_addr_base),
.fill_fifo (fill_fifo),
.drain_fifo (drain_fifo),
.mem_to_fifo_done (mem_to_fifo_done),
.fifo_to_arr_done (fifo_to_arr_done),
.output_done (output_done)
);
endmodule |
module top (
clk,
reset,
start,
done,
opcode,
dim_1,
dim_2,
dim_3,
addr_1,
accum_table_submat_row_in,
accum_table_submat_col_in,
fifo_ready,
inputMem_wr_data,
weightMem_wr_data,
outputMem_rd_data
);
// ========================================
// ---------- Parameters ------------------
// ========================================
parameter WIDTH_HEIGHT = 16;
parameter DATA_WIDTH = 8;
parameter MAX_MAT_WH = 128;
// ========================================
// ------------ Inputs --------------------
// ========================================
input clk;
input reset;
input start;
input [2:0] opcode;
input [$clog2(WIDTH_HEIGHT)-1:0] dim_1;
input [$clog2(WIDTH_HEIGHT)-1:0] dim_2;
input [$clog2(WIDTH_HEIGHT)-1:0] dim_3;
input [7:0] addr_1;
input [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] accum_table_submat_row_in;
input [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] accum_table_submat_col_in;
input [WIDTH_HEIGHT*DATA_WIDTH-1:0] inputMem_wr_data;
input [WIDTH_HEIGHT*DATA_WIDTH-1:0] weightMem_wr_data;
// ========================================
// ------------ Outputs -------------------
// ========================================
output done;
output fifo_ready;
output [WIDTH_HEIGHT*DATA_WIDTH*2-1:0] outputMem_rd_data;
// ========================================
// ------- Local Wires and Regs -----------
// ========================================
wire [(WIDTH_HEIGHT*DATA_WIDTH)-1:0] inputMem_to_sysArr;
wire [WIDTH_HEIGHT-1:0] inputMem_rd_en;
wire [(WIDTH_HEIGHT*DATA_WIDTH)-1:0] inputMem_rd_addr;
wire [(WIDTH_HEIGHT*DATA_WIDTH)-1:0] weightMem_rd_data;
wire [(WIDTH_HEIGHT*DATA_WIDTH)-1:0] weightFifo_to_sysArr;
wire [WIDTH_HEIGHT-1:0] outputMem_wr_en;
wire [WIDTH_HEIGHT-1:0] mmu_col_valid_out;
wire [2*DATA_WIDTH*WIDTH_HEIGHT-1:0] accumTable_wr_data;
wire [$clog2(MAX_MAT_WH*(MAX_MAT_WH/WIDTH_HEIGHT))*WIDTH_HEIGHT-1:0] accumTable_wr_addr;
wire [WIDTH_HEIGHT-1:0] accumTable_wr_en_in;
wire [$clog2(MAX_MAT_WH*(MAX_MAT_WH/WIDTH_HEIGHT))*WIDTH_HEIGHT-1:0] accumTable_rd_addr;
wire [2*DATA_WIDTH*WIDTH_HEIGHT-1:0] accumTable_data_out_to_relu;
wire [(WIDTH_HEIGHT*16)-1:0] outputMem_wr_data;
wire [WIDTH_HEIGHT-1:0] mem_to_fifo_en;
wire [WIDTH_HEIGHT-1:0] fifo_to_arr_en;
wire [(WIDTH_HEIGHT*DATA_WIDTH)-1:0] weightMem_rd_addr;
wire [WIDTH_HEIGHT-1:0] weightMem_rd_en;
wire weight_write;
// set sys_arr_active 2 cycles after we start reading memory
wire sys_arr_active;
reg sys_arr_active1;
reg sys_arr_active2;
reg data_mem_calc_done; // high if MMU is done multiplying
wire accum_clear;
wire [DATA_WIDTH-1:0] mem_addr_bus_data;
wire [$clog2(WIDTH_HEIGHT)-1:0] wr_accumTable_mat_row;
wire [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] wr_accumTable_submat_row;
wire [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] wr_accumTable_submat_col;
wire [$clog2(WIDTH_HEIGHT)-1:0] rd_accumTable_mat_row;
wire [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] rd_accumTable_submat_row;
wire [$clog2(MAX_MAT_WH/WIDTH_HEIGHT)-1:0] rd_accumTable_submat_col;
wire [7:0] outputMem_wr_addr;
// ========================================
// ---------------- Logic -----------------
// ========================================
// sys_arr_active 2 cycles after we start reading memory
assign sys_arr_active = inputMem_rd_en[0];
// ========================================
// ------------ Master Control ------------
// ========================================
master_control master_control(
.clk (clk),
.reset (reset),
.reset_out (reset_global),
.start (start),
.done (done),
.opcode (opcode),
.dim_1 (dim_1),
.dim_2 (dim_2),
.dim_3 (dim_3),
.addr_1 (addr_1),
.accum_table_submat_row_in(accum_table_submat_row_in),
.accum_table_submat_col_in(accum_table_submat_col_in),
.weight_fifo_arr_done (fifo_to_arr_done),
.data_mem_calc_done (data_mem_calc_done),
.fifo_ready (fifo_ready),
.bus_to_mem_addr (mem_addr_bus_data),
.in_mem_wr_en (inputMem_wr_en),
.weight_mem_out_rd_addr (weightMem_rd_addr),
.weight_mem_out_rd_en (weightMem_rd_en),
.weight_mem_wr_en (weightMem_wr_en),
.out_mem_out_wr_addr (outputMem_wr_addr),
.out_mem_out_wr_en (outputMem_wr_en),
.out_mem_rd_en (outputMem_rd_en),
.in_fifo_active (in_fifo_active),
.out_fifo_active (out_fifo_active),
.data_mem_calc_en (data_mem_calc_en),
.wr_submat_row_out (wr_accumTable_submat_row),
.wr_submat_col_out (wr_accumTable_submat_col),
.wr_row_num (wr_accumTable_mat_row),
.rd_submat_row_out (rd_accumTable_submat_row),
.rd_submat_col_out (rd_accumTable_submat_col),
.rd_row_num (rd_accumTable_mat_row),
.accum_clear (accum_clear),
.relu_en (relu_en)
);
defparam master_control.SYS_ARR_COLS = WIDTH_HEIGHT;
defparam master_control.SYS_ARR_ROWS = WIDTH_HEIGHT;
defparam master_control.MAX_OUT_ROWS = MAX_MAT_WH;
defparam master_control.MAX_OUT_COLS = MAX_MAT_WH;
defparam master_control.ADDR_WIDTH = 8;
// ========================================
// ------------ Systolic Array ------------
// ========================================
sysArr sysArr(
.clk (clk),
.active (sys_arr_active2), // from control or software
.datain (inputMem_to_sysArr), // from inputMem
.win (weightFifo_to_sysArr), // from weightFifo
.sumin (256'd0), // can be used for biases
.wwrite ({16{weight_write}}), // from fifo_arr
.maccout (accumTable_wr_data), // to accumTable
.wout (), // Not used
.wwriteout(), // Not used
.activeout(mmu_col_valid_out), // en for accumTable_wr_control
.dataout () // Not used
);
defparam sysArr.width_height = WIDTH_HEIGHT;
// =========================================
// --------- Input Side of Array -----------
// =========================================
memArr inputMem(
.clk (clk),
.rd_en (inputMem_rd_en), // from inputMemControl
.wr_en ({WIDTH_HEIGHT{inputMem_wr_en}}), // from master_control
.wr_data(inputMem_wr_data), // from interconnect (INPUT)
.rd_addr(inputMem_rd_addr), // from inputMemControl
.wr_addr({WIDTH_HEIGHT{mem_addr_bus_data}}), // from master_control
.rd_data(inputMem_to_sysArr) // to sysArr
);
defparam inputMem.width_height = WIDTH_HEIGHT;
rd_control inputMemControl (
.clk (clk),
.reset (reset_global), // from master_control
.active (data_mem_calc_en), // from master_control
.rd_en (inputMem_rd_en), // to inputMem
.rd_addr (inputMem_rd_addr), // to inputMem
.wr_active() // NOTE: not sure if needed
);
defparam inputMemControl.width_height = WIDTH_HEIGHT;
// ========================================
// --------- Weight side of Array ---------
// ========================================
memArr weightMem(
.clk (clk),
.rd_en (weightMem_rd_en), // from master_control
.wr_en ({WIDTH_HEIGHT{weightMem_wr_en}}), // from master_control
.wr_data(weightMem_wr_data), // from interconnect (INPUT)
.rd_addr(weightMem_rd_addr), // from master_control
.wr_addr({WIDTH_HEIGHT{mem_addr_bus_data}}), // from master_control
.rd_data(weightMem_rd_data) // to weightFifo
);
defparam weightMem.width_height = WIDTH_HEIGHT;
fifo_control mem_fifo (
.clk (clk),
.reset (reset_global), // from master_control
.active (in_fifo_active), // from master_control
.stagger_load(1'b0), // never stagger when filling
.fifo_en (mem_to_fifo_en), // to weightFifo
.done (), // NOTE: not sure if signal needed
.weight_write() // not used
);
defparam mem_fifo.fifo_width = WIDTH_HEIGHT;
fifo_control fifo_arr (
.clk (clk),
.reset (reset_global), // from master_control
.active (out_fifo_active), // from master_control
.stagger_load(1'b0), // fucntionality not implemented
.fifo_en (fifo_to_arr_en), // to weightFifo
.done (fifo_to_arr_done), // to master_control
.weight_write(weight_write) // to sysArr
);
defparam fifo_arr.fifo_width = WIDTH_HEIGHT;
weightFifo weightFifo (
.clk (clk),
.reset (reset_global), // from master_control
.en (mem_to_fifo_en | fifo_to_arr_en), // from mem_fifo & fifo_arr
.weightIn (weightMem_rd_data), // from weightMem
.weightOut(weightFifo_to_sysArr) // to sysArr
);
defparam weightFifo.DATA_WIDTH = DATA_WIDTH;
defparam weightFifo.FIFO_INPUTS = WIDTH_HEIGHT;
defparam weightFifo.FIFO_DEPTH = WIDTH_HEIGHT;
// =========================================
// --------- Output side of array ----------
// =========================================
accumTable accumTable (
.clk (clk),
.clear ({WIDTH_HEIGHT{reset_global}} | {WIDTH_HEIGHT{accum_clear}}),
.rd_en ({WIDTH_HEIGHT{1'b1}}), // FIXME: figure out where this signal should come from
.wr_en (accumTable_wr_en_in), // from accumTableWr_control
.rd_addr(accumTable_rd_addr), // from accumTableRd_control
.wr_addr(accumTable_wr_addr), // from accumTableWr_control
.rd_data(accumTable_data_out_to_relu), // to reluArr
.wr_data(accumTable_wr_data) // from sysArr
);
defparam accumTable.SYS_ARR_ROWS = WIDTH_HEIGHT;
defparam accumTable.SYS_ARR_COLS = WIDTH_HEIGHT;
defparam accumTable.DATA_WIDTH = 2*DATA_WIDTH;
defparam accumTable.MAX_OUT_ROWS = MAX_MAT_WH;
defparam accumTable.MAX_OUT_COLS = MAX_MAT_WH;
accumTableWr_control accumTableWr_control (
.clk (clk),
.reset (reset_global), // from master_control
.wr_en_in (mmu_col_valid_out[0]), // from sysArr
.sub_row (wr_accumTable_mat_row), // from master_control
.submat_m (wr_accumTable_submat_row), // from master_control
.submat_n (wr_accumTable_submat_col), // from master_control
.wr_en_out (accumTable_wr_en_in), // to accumTable
.wr_addr_out(accumTable_wr_addr) // to accumTable
);
defparam accumTableWr_control.SYS_ARR_ROWS = WIDTH_HEIGHT;
defparam accumTableWr_control.SYS_ARR_COLS = WIDTH_HEIGHT;
defparam accumTableWr_control.MAX_OUT_ROWS = MAX_MAT_WH;
defparam accumTableWr_control.MAX_OUT_COLS = MAX_MAT_WH;
accumTableRd_control accumTableRd_control (
.sub_row (rd_accumTable_mat_row), // from master_control
.submat_m (rd_accumTable_submat_row), // from master_control
.submat_n (rd_accumTable_submat_col), // from master_control
.rd_addr_out(accumTable_rd_addr) // to accumTable
);
defparam accumTableRd_control.SYS_ARR_ROWS = WIDTH_HEIGHT;
defparam accumTableRd_control.SYS_ARR_COLS = WIDTH_HEIGHT;
defparam accumTableRd_control.MAX_OUT_ROWS = MAX_MAT_WH;
defparam accumTableRd_control.MAX_OUT_COLS = MAX_MAT_WH;
reluArr reluArr (
.en (relu_en), // from master_control
.in (accumTable_data_out_to_relu), // from accumTable
.out(outputMem_wr_data) // to outputMem
);
defparam reluArr.DATA_WIDTH = 2*DATA_WIDTH;
defparam reluArr.ARR_INPUTS = WIDTH_HEIGHT;
outputArr outputMem (
.clk (clk),
.rd_en ({WIDTH_HEIGHT{outputMem_rd_en}}), // from master_control
.wr_en (outputMem_wr_en), // from master_control
.wr_data(outputMem_wr_data), // from reluArr
.rd_addr({WIDTH_HEIGHT{mem_addr_bus_data}}), // from master_control
.wr_addr({WIDTH_HEIGHT{outputMem_wr_addr}}), // from master_control
.rd_data(outputMem_rd_data) // to interconect (OUTPUT)
);
defparam outputMem.width_height = WIDTH_HEIGHT;
/* FIXME: determine if this module is needed (don't think it is)
wr_control outputMemControl (
.clk (clk),
.reset (reset_global), // from master_control
.active (rd_to_wr_start), // from inputMemControl NOTE: why?
.wr_en (outputMem_wr_en), // to outputMem
.wr_addr(outputMem_wr_addr_offset), // to outputMem
.done (output_done),
.sys_arr_active(sys_arr_active)
);
defparam outputMemControl.width_height = WIDTH_HEIGHT;
*/
// ======================================
// ----------- Flip flops ---------------
// ======================================
integer i;
always @(*) begin
data_mem_calc_done = 0;
for (i = 0; i < WIDTH_HEIGHT; i=i+1) begin
// OR MMU column done signals to tell when entire MMU is done
data_mem_calc_done = data_mem_calc_done | mmu_col_valid_out[i];
end // for (i = 0; i < WIDTH_HEIGHT; i++)
end
always @(posedge clk) begin
// set sys_arr_active 2 cycles after we read memory
sys_arr_active1 <= sys_arr_active;
sys_arr_active2 <= sys_arr_active1;
end // always
endmodule // top |
module dff8(clk, reset, en, d, q);
parameter DATA_WIDTH = 8;
input clk;
input reset;
input en;
input signed [DATA_WIDTH-1:0] d;
output reg signed [DATA_WIDTH-1:0] q;
always @(posedge clk) begin
if (reset) begin
q <= 0;
end // if (reset == 1'b1)
else if (en) begin
q <= d;
end // else if (en)
else begin // expecting this to get synthesized away (remove otherwise)
q <= q;
end // else
end // always @(posedge clk)
endmodule // dff8 |
module weightFifo(clk, reset, en, weightIn, weightOut);
parameter DATA_WIDTH = 8; // must be same as DATA_WIDTH in dff8.v
parameter FIFO_INPUTS = 4;
localparam FIFO_WIDTH = DATA_WIDTH*FIFO_INPUTS; // number of output weights
parameter FIFO_DEPTH = 4; // number of stage weights
input clk;
input reset;
input [FIFO_INPUTS-1:0] en; // MSB is leftmost column in the array
input [FIFO_WIDTH-1:0] weightIn; // MSB is leftmost column in the array
output wire [FIFO_WIDTH-1:0] weightOut; // LSB is leftmost column in the array
wire [FIFO_INPUTS*FIFO_DEPTH-1:0] colEn; // enable signals to be sent to each element in a respective column
wire [FIFO_WIDTH*FIFO_DEPTH-1:0] dffIn; // inputs to each element of dff array
wire [FIFO_WIDTH*FIFO_DEPTH-1:0] dffOut; // ouputs of each element of dff array
dff8 dffArray[FIFO_INPUTS*FIFO_DEPTH-1:0] ( // array of elements in row-major order
.clk(clk),
.reset(reset),
.en(colEn),
.d(dffIn),
.q(dffOut)
);
assign dffIn[FIFO_WIDTH-1:0] = weightIn; // assign beginning of array to input
assign weightOut = dffOut[FIFO_WIDTH*FIFO_DEPTH-1:FIFO_WIDTH*(FIFO_DEPTH-1)]; // assign end of array to output
generate
genvar i;
for (i=1; i<FIFO_DEPTH; i=i+1) begin : assignConn // use for-loop to dynamically make connections between FFs
assign dffIn[FIFO_WIDTH*(i+1)-1:FIFO_WIDTH*i] = dffOut[FIFO_WIDTH*i-1:FIFO_WIDTH*(i-1)];
end // for (i=0; i<FIFO_DEPTH; i=i+1)
endgenerate
generate
genvar j;
for (i=0; i<FIFO_INPUTS; i=i+1) begin : widthIndex // use for-loop to dynamically make enable connections to each column
for (j=0; j<FIFO_DEPTH; j=j+1) begin : depthIndex
assign colEn[j*FIFO_DEPTH+i] = en[i]; // assign all dff8's in each column to the same enable signal
end // for (j=0; j<FIFO_DEPTH; j=j+1)
end // for (i=0; i<FIFO_WIDTH; i=i+1)
endgenerate
endmodule // weightFifo |
module keyboard (
input clk,
input [10:0] ps2_key,
input key_was_processed,
output reg kbd_read_strobe,
output reg console_switch_strobe,
output reg [10:0] console_switches,
output reg [6:0] kbd_char_out,
/* selected_ptr_* points to cursor coordinates (used for flipping main console switches) */
output reg [5:0] selected_ptr_x,
output reg [4:0] selected_ptr_y,
output reg [1:0] current_output_device,
output reg [7:0] joystick_emu
);
reg pressed, current_key_state, old_state;
reg current_case;
wire next_case;
reg [1:0] current_shift_pressed;
wire [1:0] shift_pressed;
assign shift_pressed[0] = ps2_key[7:0] == 8'h12 ? pressed : current_shift_pressed[0];
assign shift_pressed[1] = ps2_key[7:0] == 8'h59 ? pressed : current_shift_pressed[1];
assign next_case = |shift_pressed;
reg [6:0] keyboard_buffer[7:0];
reg [2:0] kbdbuf_read_ptr = 3'b0;
reg [2:0] kbdbuf_write_ptr = 3'b0;
reg [0:0] old_key_was_processed;
reg [1:0] active_switches;
`define key_assign(code) keyboard_buffer[kbdbuf_write_ptr] <= { current_case, code }
`include "definitions.v"
always @(posedge clk) begin
pressed <= ps2_key[9];
current_key_state <= ps2_key[10];
kbd_char_out <= keyboard_buffer[kbdbuf_read_ptr];
old_state <= current_key_state;
old_key_was_processed <= key_was_processed;
if (old_state != current_key_state) begin
if (pressed && (current_output_device == `output_teletype)) // Write to write ptr buffer only if outputting to tty
kbdbuf_write_ptr <= kbdbuf_write_ptr + 1'b1;
if (~pressed) // Changed, was if(~pressed), TEST!
kbd_read_strobe <= 1'b0;
/* Keys for typewriter emulation and console */
case (ps2_key[7:0])
8'h0D: keyboard_buffer[kbdbuf_write_ptr] <= 6'o36; // TAB (ps2 = 0x0d, fiodec = o36)
8'h29: keyboard_buffer[kbdbuf_write_ptr] <= 6'o00; // Space
8'h5A: begin
keyboard_buffer[kbdbuf_write_ptr] <= 6'o77; // Carriage Return
console_switch_strobe <= pressed;
end
8'h05: `power_switch <= pressed ^ `power_switch; // F1 -> Power switch toggle
8'h06: begin
active_switches <= active_switches + pressed; // F2 -> Toggle active switch row
case (active_switches + pressed)
2'b00: {selected_ptr_x, selected_ptr_y} <= { 6'd3, 5'd21 }; // Test word cursor set
2'b01: {selected_ptr_x, selected_ptr_y} <= { 6'd5, 5'd19 }; // Test address cursor set
2'b10: {selected_ptr_x, selected_ptr_y} <= { 6'd31, 5'd14 }; // Sense switches cursor set
2'b11: {selected_ptr_x, selected_ptr_y} <= { 11'b0 }; // Clear selection
endcase
end
8'h04: `single_inst_switch <= pressed ^ `single_inst_switch; // F3 -> Single Instruction switch toggle
8'h0C: current_output_device <= current_output_device + pressed + ¤t_output_device; // F4 -> Cycle output, skip fourth case because we have only three
8'h03: `start_button <= pressed; // F5 -> Start
8'h0B: `stop_button <= pressed; // F6 -> Stop
8'h83: `continue_button <= pressed; // F7 -> Continue
8'h0A: `examine_button <= pressed; // F8 -> Examine
8'h01: `deposit_button <= pressed; // F9 -> Deposit
8'h09: `readin_button <= pressed; // F10 -> Read in mode pressed
8'h78: `tapefeed_button <= pressed; // F11 -> Tape Feed
8'h70: `power_switch <= pressed ^ `power_switch; // Insert -> Power
8'h69: `single_step_switch <= pressed ^ `single_step_switch; // Num Lock-> Single Step
8'h71: `single_inst_switch <= pressed ^ `single_inst_switch; // Delete -> Single Instruction
/* PS2 code FIO-DEC code Key */
8'h66: `key_assign(6'o75); // Backspace
8'h41,
8'h55: `key_assign(6'o33); // , = (comma, equal)
8'h4A: `key_assign(6'o21); // / ? (slash, question mark)
8'h54: `key_assign(6'o57); // ( [ (left brackets)
8'h5B: `key_assign(6'o55); // ) ] (right brackets)
8'h49: `key_assign(6'o73); // . x (period, multiply)
8'h4E: `key_assign(6'o54); // - + (minus, plus)
8'h7C: `key_assign(6'o40); // . _ (middle dot, underline)
8'h5D: `key_assign(6'o56); // non-spacing overstrike and vertical
8'h58: `key_assign(6'o36); // caps lock -> captab
8'h45: `key_assign(6'o020); /* 0 */ 8'h1C: `key_assign(6'o061); /* a */
8'h16: `key_assign(6'o001); /* 1 */ 8'h32: `key_assign(6'o062); /* b */
8'h1E: `key_assign(6'o002); /* 2 */ 8'h21: `key_assign(6'o063); /* c */
8'h26: `key_assign(6'o003); /* 3 */ 8'h23: `key_assign(6'o064); /* d */
8'h25: `key_assign(6'o004); /* 4 */ 8'h24: `key_assign(6'o065); /* e */
8'h2E: `key_assign(6'o005); /* 5 */ 8'h2B: `key_assign(6'o066); /* f */
8'h36: `key_assign(6'o006); /* 6 */ 8'h34: `key_assign(6'o067); /* g */
8'h3D: `key_assign(6'o007); /* 7 */ 8'h33: `key_assign(6'o070); /* h */
8'h3E: `key_assign(6'o010); /* 8 */ 8'h43: `key_assign(6'o071); /* i */
8'h46: `key_assign(6'o011); /* 9 */ 8'h3B: `key_assign(6'o041); /* j */
8'h42: `key_assign(6'o042); /* k */ 8'h1B: `key_assign(6'o022); /* s */
8'h4B: `key_assign(6'o043); /* l */ 8'h2C: `key_assign(6'o023); /* t */
8'h3A: `key_assign(6'o044); /* m */ 8'h3C: `key_assign(6'o024); /* u */
8'h31: `key_assign(6'o045); /* n */ 8'h2A: `key_assign(6'o025); /* v */
8'h44: `key_assign(6'o046); /* o */ 8'h1D: `key_assign(6'o026); /* w */
8'h4D: `key_assign(6'o047); /* p */ 8'h22: `key_assign(6'o027); /* x */
8'h15: `key_assign(6'o050); /* q */ 8'h35: `key_assign(6'o030); /* y */
8'h2D: `key_assign(6'o051); /* r */ 8'h1A: `key_assign(6'o031); /* z */
/* Controls for navigating cursor through console switches */
8'h74: selected_ptr_x <= selected_ptr_x + pressed;
8'h6B: selected_ptr_x <= selected_ptr_x - pressed;
8'h12, /* Left shift / right shift */
8'h59:
begin
if (current_case != next_case) begin
keyboard_buffer[kbdbuf_write_ptr] <= next_case ? 6'o74 : 6'o72;
kbdbuf_write_ptr <= kbdbuf_write_ptr + 1'b1;
end else kbdbuf_write_ptr <= kbdbuf_write_ptr;
current_case <= next_case;
current_shift_pressed <= shift_pressed;
end
/* If key not recognized, don't increment write pointer */
default:
kbdbuf_write_ptr <= kbdbuf_write_ptr;
endcase
end
if (kbdbuf_write_ptr != kbdbuf_read_ptr)
kbd_read_strobe <= 1'b1;
if (~old_key_was_processed && key_was_processed)
begin
kbdbuf_read_ptr <= kbdbuf_read_ptr + 1'b1;
kbd_read_strobe <= 1'b0;
end
end
/* Enable using the keyboard as controller for spacewar */
always @(posedge clk) begin
if(old_state != current_key_state) begin
casex(ps2_key[8:0])
8'h1D: joystick_emu[0] <= pressed; // w, fire
8'h1C: joystick_emu[1] <= pressed; // a, left
8'h1B: joystick_emu[2] <= pressed; // s, thrust
8'h23: joystick_emu[3] <= pressed; // d, right
8'h43: joystick_emu[4] <= pressed; // i, fire
8'h3B: joystick_emu[5] <= pressed; // j, left
8'h42: joystick_emu[6] <= pressed; // k, thrust
8'h4B: joystick_emu[7] <= pressed; // l, right
endcase
end
end
endmodule |
module pdp1_terminal_charset (
address,
clock,
q);
input [11:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "fiodec_charset.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule |
module pdp1_vga_rowbuffer (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [12:0] rdaddress;
input [12:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module line_shift_register (
clock,
shiftin,
shiftout,
taps);
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps;
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] shiftout = sub_wire0[7:0];
wire [7:0] taps = sub_wire1[7:0];
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.shiftin (shiftin),
.shiftout (sub_wire0),
.taps (sub_wire1)
// synopsys translate_off
,
.aclr (),
.clken (),
.sclr ()
// synopsys translate_on
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone V",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 1,
/* Not 1688 (the number of clock cycles in 1280 x 1024 @ 60 Hz row)
because 3 explicitly defined registers are used in the chain as well,
adding up to 1685 + 3 = 1688 */
ALTSHIFT_TAPS_component.tap_distance = 1685,
ALTSHIFT_TAPS_component.width = 8;
endmodule |
module pixel_ring_buffer (
clock,
shiftin,
shiftout,
taps);
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [255:0] taps;
wire [31:0] sub_wire0;
wire [255:0] sub_wire1;
wire [31:0] shiftout = sub_wire0[31:0];
wire [255:0] taps = sub_wire1[255:0];
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.shiftin (shiftin),
.shiftout (sub_wire0),
.taps (sub_wire1)
// synopsys translate_off
,
.aclr (),
.clken (),
.sclr ()
// synopsys translate_on
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone V",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 8,
ALTSHIFT_TAPS_component.tap_distance = 1024,
ALTSHIFT_TAPS_component.width = 32;
endmodule |
module pdp1_terminal_fb (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2000,
altsyncram_component.numwords_b = 2000,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module console_bg_image (
address,
clock,
q);
input [15:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "console_bg.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 45056,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module pdp1_main_ram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.init_file = "spacewar.mif",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule |
module spdif
(
input clk_i,
input rst_i,
// SPDIF bit output enable
// Single cycle pulse synchronous to clk_i which drives
// the output bit rate.
// For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
// For 48KHz, 48000×32×2×2 = 6,144,000Hz
input bit_out_en_i,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [31:0] sample_i,
output reg sample_req_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [15:0] audio_sample_q;
reg [8:0] subframe_count_q;
reg load_subframe_q;
reg [7:0] preamble_q;
wire [31:0] subframe_w;
reg [5:0] bit_count_q;
reg bit_toggle_q;
reg spdif_out_q;
reg [5:0] parity_count_q;
//-----------------------------------------------------------------
// Subframe Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
subframe_count_q <= 9'd0;
else if (load_subframe_q)
begin
// 192 frames (384 subframes) in an audio block
if (subframe_count_q == 9'd383)
subframe_count_q <= 9'd0;
else
subframe_count_q <= subframe_count_q + 9'd1;
end
end
//-----------------------------------------------------------------
// Sample capture
//-----------------------------------------------------------------
reg [15:0] sample_buf_q;
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
audio_sample_q <= 16'h0000;
sample_buf_q <= 16'h0000;
sample_req_o <= 1'b0;
end
else if (load_subframe_q)
begin
// Start of frame (first subframe)?
if (subframe_count_q[0] == 1'b0)
begin
// Use left sample
audio_sample_q <= sample_i[15:0];
// Store right sample
sample_buf_q <= sample_i[31:16];
// Request next sample
sample_req_o <= 1'b1;
end
else
begin
// Use right sample
audio_sample_q <= sample_buf_q;
sample_req_o <= 1'b0;
end
end
else
sample_req_o <= 1'b0;
end
// Timeslots 3 - 0 = Preamble
assign subframe_w[3:0] = 4'b0000;
// Timeslots 7 - 4 = 24-bit audio LSB
assign subframe_w[7:4] = 4'b0000;
// Timeslots 11 - 8 = 20-bit audio LSB
assign subframe_w[11:8] = 4'b0000;
// Timeslots 27 - 12 = 16-bit audio
assign subframe_w[27:12] = audio_sample_q;
// Timeslots 28 = Validity
assign subframe_w[28] = 1'b0; // Valid
// Timeslots 29 = User bit
assign subframe_w[29] = 1'b0;
// Timeslots 30 = Channel status bit
assign subframe_w[30] = 1'b0;
// Timeslots 31 = Even Parity bit (31:4)
assign subframe_w[31] = 1'b0;
//-----------------------------------------------------------------
// Preamble
//-----------------------------------------------------------------
localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;
reg [7:0] preamble_r;
always @ *
begin
// Start of audio block?
// Z(B) - Left channel
if (subframe_count_q == 9'd0)
preamble_r = PREAMBLE_Z; // Z(B)
// Right Channel?
else if (subframe_count_q[0] == 1'b1)
preamble_r = PREAMBLE_Y; // Y(W)
// Left Channel (but not start of block)?
else
preamble_r = PREAMBLE_X; // X(M)
end
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
preamble_q <= 8'h00;
else if (load_subframe_q)
preamble_q <= preamble_r;
//-----------------------------------------------------------------
// Parity Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if (rst_i == 1'b1)
begin
parity_count_q <= 6'd0;
end
// Time to output a bit?
else if (bit_out_en_i)
begin
// Preamble bits?
if (bit_count_q < 6'd8)
begin
parity_count_q <= 6'd0;
end
// Normal timeslots
else if (bit_count_q < 6'd62)
begin
// On first pass through this timeslot, count number of high bits
if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
parity_count_q <= parity_count_q + 6'd1;
end
end
end
//-----------------------------------------------------------------
// Bit Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
begin
if (rst_i == 1'b1)
begin
bit_count_q <= 6'b0;
load_subframe_q <= 1'b1;
end
// Time to output a bit?
else if (bit_out_en_i)
begin
// 32 timeslots (x2 for double frequency)
if (bit_count_q == 6'd63)
begin
bit_count_q <= 6'd0;
load_subframe_q <= 1'b1;
end
else
begin
bit_count_q <= bit_count_q + 6'd1;
load_subframe_q <= 1'b0;
end
end
else
load_subframe_q <= 1'b0;
end
//-----------------------------------------------------------------
// Bit half toggle
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
if (rst_i == 1'b1)
bit_toggle_q <= 1'b0;
// Time to output a bit?
else if (bit_out_en_i)
bit_toggle_q <= ~bit_toggle_q;
//-----------------------------------------------------------------
// Output bit (BMC encoded)
//-----------------------------------------------------------------
reg bit_r;
always @ *
begin
bit_r = spdif_out_q;
// Time to output a bit?
if (bit_out_en_i)
begin
// Preamble bits?
if (bit_count_q < 6'd8)
begin
bit_r = preamble_q[bit_count_q[2:0]];
end
// Normal timeslots
else if (bit_count_q < 6'd62)
begin
if (subframe_w[bit_count_q / 2] == 1'b0)
begin
if (bit_toggle_q == 1'b0)
bit_r = ~spdif_out_q;
else
bit_r = spdif_out_q;
end
else
bit_r = ~spdif_out_q;
end
// Parity timeslot
else
begin
// Even number of high bits, make odd
if (parity_count_q[0] == 1'b0)
begin
if (bit_toggle_q == 1'b0)
bit_r = ~spdif_out_q;
else
bit_r = spdif_out_q;
end
else
bit_r = ~spdif_out_q;
end
end
end
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
spdif_out_q <= 1'b0;
else
spdif_out_q <= bit_r;
assign spdif_o = spdif_out_q;
endmodule |
module vga_frame_generator(
input reset_n,
input clk,
output vga_hs,
output vga_vs,
output reg [11:0] vga_rgb,
output reg [10:0] rd_address,
input [15:0] rd_data,
output reg g_req,
input g_ack,
output reg g_cache_row,
output reg [9:0] g_sdram_row,
input interlaced,
input field_no
);
// List of VGA timings: http://tinyvga.com/vga-timing
// 1280x800p@60Hz
localparam H_SYNC = 11'd136;
localparam H_BACK = 11'd200;
localparam H_VISIBLE = 11'd1280;
localparam H_FRONT = 11'd64;
localparam H_TOTAL = 11'd1680;
localparam V_SYNC = 11'd3;
localparam V_BACK = 11'd24;
localparam V_VISIBLE = 11'd800;
localparam V_FRONT = 11'd1;
localparam V_TOTAL = 11'd828;
localparam X_START = 11'd600;
localparam Y_START = 11'd139;
localparam BOX_WIDTH = 11'd752;
localparam BOX_HEIGHT = 11'd576;
reg [10:0] h_cnt = 11'd0;
reg [10:0] v_cnt = 11'd0;
assign vga_hs = h_cnt >= H_SYNC;
assign vga_vs = v_cnt >= V_SYNC;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
h_cnt <= 11'd0;
v_cnt <= 11'd0;
end
else
begin
if (h_cnt == H_TOTAL - 11'd1)
begin
h_cnt <= 11'd0;
if (v_cnt == V_TOTAL - 11'd1)
v_cnt <= 11'd0;
else
v_cnt <= v_cnt + 11'd1;
end
else
h_cnt <= h_cnt + 11'd1;
end
end
wire [10:0] y_pos = v_cnt - Y_START;
wire [10:0] addr_x_pos = h_cnt - (X_START - 11'd3);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
rd_address <= 11'd0;
else
begin
if (addr_x_pos < BOX_WIDTH && y_pos < BOX_HEIGHT)
rd_address <= {y_pos[0], addr_x_pos[9:0]};
else
rd_address <= 11'd0;
end
end
wire [10:0] col_x_pos = h_cnt - (X_START - 11'd1);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
vga_rgb <= 12'h000;
end
else
begin
if (col_x_pos < BOX_WIDTH && y_pos < BOX_HEIGHT)
vga_rgb <= rd_data[11:0];
/*
else if (v_cnt >= (V_SYNC + V_BACK) && v_cnt < (V_TOTAL - V_FRONT) && h_cnt >= (H_SYNC + H_BACK) && h_cnt < (H_TOTAL - H_FRONT))
begin
if (h_cnt[0])
vga_rgb <= 12'h223;
else
vga_rgb <= 12'h333;
end*/
else
vga_rgb <= 12'h000;
end
end
wire [10:0] fetch_y_pos = v_cnt - (Y_START - 11'd1);
always @(posedge clk)
begin
if (h_cnt == 0 && fetch_y_pos < BOX_HEIGHT)
begin
g_req <= !g_ack;
g_cache_row <= fetch_y_pos[0];
if (interlaced)
g_sdram_row <= fetch_y_pos[9:0];
else
g_sdram_row <= {fetch_y_pos[9:1], field_no};
end
end
endmodule |
module flickerfixer(
input MAX10_CLK1_50,
output DRAM_CLK,
output DRAM_CKE,
output DRAM_CS_N,
output DRAM_RAS_N,
output DRAM_CAS_N,
output DRAM_WE_N,
output [1:0] DRAM_BA,
output [12:0] DRAM_ADDR,
output DRAM_LDQM,
output DRAM_UDQM,
inout [15:0] DRAM_DQ,
input AM_7M,
input AM_CDAC,
input AM_PIXELSW,
input AM_CSYNC_n,
input [11:0] AM_RGB,
output VGA_HS,
output VGA_VS,
output [11:0] VGA_RGB,
input [1:0] KEY,
input [9:0] SW,
output [9:0] LEDR,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5
);
wire amiga_pix_clk;
wire vga_pix_clk;
wire sdram_clk;
wire pll_locked;
wire vga_pll_locked;
pll pll_inst(
.inclk0(AM_7M),
.c0(amiga_pix_clk),
.c1(sdram_clk),
.locked(pll_locked)
);
vga_pll vga_pll_inst(
.inclk0(MAX10_CLK1_50),
.c0(vga_pix_clk),
.locked(vga_pll_locked)
);
wire reset_n = KEY[0] && pll_locked && vga_pll_locked;
wire [10:0] sc_wr_address;
wire [15:0] sc_wr_data;
wire sc_wr_en;
wire [10:0] sc_rd_address;
wire [15:0] sc_rd_data;
scanline_cache sampler_cache(
.wrclock(amiga_pix_clk),
.wraddress(sc_wr_address),
.wren(sc_wr_en),
.data(sc_wr_data),
.rdclock(sdram_clk),
.rdaddress(sc_rd_address),
.q(sc_rd_data)
);
wire [10:0] gc_wr_address;
wire [15:0] gc_wr_data;
wire gc_wr_en;
wire [10:0] gc_rd_address;
wire [15:0] gc_rd_data;
scanline_cache generator_cache(
.wrclock(sdram_clk),
.wraddress(gc_wr_address),
.wren(gc_wr_en),
.data(gc_wr_data),
.rdclock(vga_pix_clk),
.rdaddress(gc_rd_address),
.q(gc_rd_data)
);
wire interlaced;
wire field_no;
wire s_req;
wire s_ack;
wire s_cache_row;
wire [9:0] s_sdram_row;
amiga_frame_sampler sampler(
.reset_n(reset_n),
.clk(amiga_pix_clk),
.csync_n(AM_CSYNC_n),
.am_rgb(AM_RGB),
.wr_address(sc_wr_address),
.wr_data(sc_wr_data),
.wr_en(sc_wr_en),
.s_req(s_req),
.s_ack(s_ack),
.s_cache_row(s_cache_row),
.s_sdram_row(s_sdram_row),
.interlaced(interlaced),
.field_no(field_no)
);
wire g_req;
wire g_ack;
wire g_cache_row;
wire [9:0] g_sdram_row;
vga_frame_generator generator(
.reset_n(reset_n),
.clk(vga_pix_clk),
.vga_hs(VGA_HS),
.vga_vs(VGA_VS),
.vga_rgb(VGA_RGB),
.rd_address(gc_rd_address),
.rd_data(gc_rd_data),
.g_req(g_req),
.g_ack(g_ack),
.g_cache_row(g_cache_row),
.g_sdram_row(g_sdram_row),
.interlaced(interlaced),
.field_no(field_no)
);
sdram_controller sdram_controller(
.reset_n(reset_n),
.clk(sdram_clk),
.DRAM_CLK(DRAM_CLK),
.DRAM_CKE(DRAM_CKE),
.DRAM_CS_N(DRAM_CS_N),
.DRAM_RAS_N(DRAM_RAS_N),
.DRAM_CAS_N(DRAM_CAS_N),
.DRAM_WE_N(DRAM_WE_N),
.DRAM_BA(DRAM_BA),
.DRAM_ADDR(DRAM_ADDR),
.DRAM_LDQM(DRAM_LDQM),
.DRAM_UDQM(DRAM_UDQM),
.DRAM_DQ(DRAM_DQ),
.sc_rd_address(sc_rd_address),
.sc_rd_data(sc_rd_data),
.gc_wr_address(gc_wr_address),
.gc_wr_data(gc_wr_data),
.gc_wr_en(gc_wr_en),
.s_req(s_req),
.s_ack(s_ack),
.s_cache_row(s_cache_row),
.s_sdram_row(s_sdram_row),
.g_req(g_req),
.g_ack(g_ack),
.g_cache_row(g_cache_row),
.g_sdram_row(g_sdram_row)
);
// Debug.
assign LEDR[0] = interlaced;
assign LEDR[1] = field_no;
assign LEDR[9:2] = 8'b11111111;
wire [23:0] seg_values = {4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0};
seg7_lut_6 u0(
.hex0(HEX0),
.hex1(HEX1),
.hex2(HEX2),
.hex3(HEX3),
.hex4(HEX4),
.hex5(HEX5),
.values(seg_values)
);
endmodule |
module scanline_cache (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [10:0] rdaddress;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule |
module vga_pll (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
endmodule |
module sdram_controller(
input reset_n,
input clk,
output DRAM_CLK,
output DRAM_CKE,
output DRAM_LDQM,
output DRAM_UDQM,
output DRAM_CS_N,
output DRAM_RAS_N,
output DRAM_CAS_N,
output DRAM_WE_N,
output reg [1:0] DRAM_BA,
output reg [12:0] DRAM_ADDR,
inout [15:0] DRAM_DQ,
output [10:0] sc_rd_address,
input [15:0] sc_rd_data,
output reg [10:0] gc_wr_address,
output reg gc_wr_en,
output reg [15:0] gc_wr_data,
input s_req,
output reg s_ack,
input s_cache_row,
input [9:0] s_sdram_row,
input g_req,
output reg g_ack,
input g_cache_row,
input [9:0] g_sdram_row
);
localparam CMD_NOP = 3'b111;
localparam CMD_ACTIVE = 3'b011;
localparam CMD_READ = 3'b101;
localparam CMD_WRITE = 3'b100;
localparam CMD_BURST_TERM = 3'b110;
localparam CMD_PRECHARGE = 3'b010;
localparam CMD_AUTO_REFRESH = 3'b001;
localparam CMD_LOAD_MODE = 3'b000;
reg s_request;
reg g_request;
always @(negedge clk)
begin
s_request <= s_req != s_ack;
g_request <= g_req != g_ack;
end
assign DRAM_CLK = clk;
assign DRAM_CKE = 1'b1;
reg oe_n = 1'b1;
assign DRAM_LDQM = oe_n;
assign DRAM_UDQM = oe_n;
assign DRAM_CS_N = 1'b0;
reg [2:0] dram_command = CMD_NOP;
assign DRAM_RAS_N = dram_command[2];
assign DRAM_CAS_N = dram_command[1];
assign DRAM_WE_N = dram_command[0];
reg dram_drive_data = 1'b0;
assign DRAM_DQ = dram_drive_data ? {4'd0, sc_rd_data[11:0]} : 16'bz;
assign sc_rd_address = {s_cache_row, counter[9:0]};
reg [3:0] state = 4'd0;
reg [15:0] counter = 16'd0;
localparam STATE_INIT_WAIT_200US = 4'd0;
localparam STATE_INIT_WAIT_PRECHARGE = 4'd1;
localparam STATE_INIT_WAIT_REFRESH = 4'd2;
localparam STATE_PRE_MAIN_WAIT = 4'd3;
localparam STATE_MAIN_WAIT = 4'd4;
localparam STATE_MAIN_WAIT_REFRESH = 4'd5;
localparam STATE_ACTIVATE_READ = 4'd6;
localparam STATE_READ = 4'd7;
localparam STATE_ACTIVATE_WRITE = 4'd8;
localparam STATE_WRITE = 4'd9;
always @(negedge clk or negedge reset_n)
begin
if (!reset_n)
begin
state <= STATE_INIT_WAIT_200US;
counter <= 16'd0;
end
else
begin
case (state)
STATE_INIT_WAIT_200US:
begin
if (!counter[15])
begin
dram_command <= CMD_NOP;
oe_n = 1'b1;
DRAM_ADDR <= 13'd0;
dram_drive_data <= 1'b0;
gc_wr_en <= 1'b0;
counter <= counter + 16'd1;
end
else
begin
dram_command <= CMD_PRECHARGE;
DRAM_ADDR[10] <= 1'b1;
counter <= 16'd0;
state <= STATE_INIT_WAIT_PRECHARGE;
end
end
STATE_INIT_WAIT_PRECHARGE:
begin
dram_command <= CMD_NOP;
if (!counter[2])
counter <= counter + 16'd1;
else
begin
counter <= 16'd0;
state <= STATE_INIT_WAIT_REFRESH;
end
end
STATE_INIT_WAIT_REFRESH:
begin
if (!counter[7])
begin
if (counter[3:0] == 4'd0)
dram_command <= CMD_AUTO_REFRESH;
else
dram_command <= CMD_NOP;
counter <= counter + 16'd1;
end
else
begin
dram_command <= CMD_LOAD_MODE;
DRAM_ADDR <= 13'b0000000110011;
DRAM_BA <= 2'd0;
counter <= 16'd0;
state <= STATE_PRE_MAIN_WAIT;
end
end
STATE_PRE_MAIN_WAIT:
begin
dram_command <= CMD_NOP;
if (!counter[3])
counter <= counter + 16'd1;
else
begin
counter <= 16'd0;
state <= STATE_MAIN_WAIT;
end
end
STATE_MAIN_WAIT:
begin
counter <= 16'd0;
if (g_request)
begin
g_ack <= g_req;
dram_command <= CMD_ACTIVE;
DRAM_ADDR <= {3'd0, g_sdram_row};
DRAM_BA <= 2'd0;
state <= STATE_ACTIVATE_READ;
end
else if (s_request)
begin
s_ack <= s_req;
dram_command <= CMD_ACTIVE;
DRAM_ADDR <= {3'd0, s_sdram_row};
DRAM_BA <= 2'd0;
state <= STATE_ACTIVATE_WRITE;
end
else
dram_command <= CMD_NOP;
end
STATE_MAIN_WAIT_REFRESH:
begin
dram_command <= CMD_NOP;
if (!counter[3])
counter <= counter + 16'd1;
else
begin
counter <= 16'd0;
state <= STATE_MAIN_WAIT;
end
end
STATE_ACTIVATE_READ:
begin
dram_command <= CMD_NOP;
if (!counter[1])
counter <= counter + 16'd1;
else
begin
counter <= 16'd0;
state <= STATE_READ;
end
end
STATE_READ:
begin
if (counter[9:0] < 10'd752)
begin
if (counter[2:0] == 3'd0)
begin
dram_command <= CMD_READ;
DRAM_ADDR <= {2'd0, counter[7:3] == 5'd31 || (counter[9:8] == 2'd2 && counter[7:3] == 5'd29), 2'd0, counter[7:0]};
DRAM_BA <= counter[9:8];
end
else if (counter[7:3] == 5'd31 && counter[2:0] == 3'd2)
begin
dram_command <= CMD_ACTIVE;
DRAM_ADDR <= {3'd0, g_sdram_row};
DRAM_BA <= counter[9:8] + 2'd1;
end
else
dram_command <= CMD_NOP;
end
else
dram_command <= CMD_NOP;
if (counter[9:0] < 10'd756)
begin
oe_n <= 1'b0;
if (counter[9:0] < 10'd4)
gc_wr_en <= 1'b0;
else
begin
gc_wr_en <= 1'b1;
gc_wr_address <= {g_cache_row, counter[9:0] - 10'd4};
gc_wr_data <= {4'd0, DRAM_DQ[11:0]};
end
counter <= counter + 16'd1;
end
else
begin
oe_n <= 1'b1;
gc_wr_en <= 1'b0;
counter <= 16'd0;
state <= STATE_MAIN_WAIT;
end
end
STATE_ACTIVATE_WRITE:
begin
dram_command <= CMD_NOP;
if (!counter[1])
counter <= counter + 16'd1;
else
begin
counter <= 16'd0;
state <= STATE_WRITE;
dram_drive_data <= 1'b1;
end
end
STATE_WRITE:
begin
if (counter[9:0] < 10'd752)
begin
oe_n <= 1'b0;
dram_drive_data <= 1'b1;
if (counter[2:0] == 3'd0)
begin
dram_command <= CMD_WRITE;
DRAM_ADDR <= {2'd0, counter[7:3] == 5'd31 || (counter[9:8] == 2'd2 && counter[7:3] == 5'd29), 2'd0, counter[7:0]};
DRAM_BA <= counter[9:8];
end
else if (counter[7:3] == 5'd31 && counter[2:0] == 3'd2)
begin
dram_command <= CMD_ACTIVE;
DRAM_ADDR <= {3'd0, s_sdram_row};
DRAM_BA <= counter[9:8] + 2'd1;
end
else
dram_command <= CMD_NOP;
counter <= counter + 16'd1;
end
else
begin
dram_command <= CMD_NOP;
dram_drive_data <= 1'b0;
oe_n <= 1'b1;
counter <= 16'd0;
state <= STATE_MAIN_WAIT;
end
end
default:
begin
counter <= 16'd0;
state <= STATE_INIT_WAIT_200US;
end
endcase
end
end
endmodule |
module amiga_frame_sampler(
input reset_n,
input clk,
input csync_n,
input [11:0] am_rgb,
output reg [10:0] wr_address,
output reg wr_en,
output reg [15:0] wr_data,
output reg s_req,
input s_ack,
output reg s_cache_row,
output reg [9:0] s_sdram_row,
output reg interlaced,
output reg field_no
);
localparam FULL_ROW_LENGTH = 10'd908;
localparam LEFT_HALF_ROW_LENGTH = 10'd456;
localparam RIGHT_HALF_ROW_LENGTH = 10'd452;
localparam NORMAL_PULSE_LENGTH = 10'd68;
localparam SHORT_PULSE_LENGTH = 10'd32;
localparam LONG_LEFT_PULSE_LENGTH = 10'd388;
localparam LONG_RIGHT_PULSE_LENGTH = 10'd384;
localparam X_START = 10'd147;
localparam Y_START = 10'd22;
localparam BOX_WIDTH = 10'd752;
localparam BOX_HEIGHT = 10'd288;
reg prev_ne_csync_n = 1'b1;
reg csync_rising = 1'b0;
always @(negedge clk)
begin
prev_ne_csync_n <= csync_n;
csync_rising <= !prev_ne_csync_n && csync_n;
end
reg prev_pe_csync_n;
always @(posedge clk)
prev_pe_csync_n <= csync_n;
wire csync_falling = prev_pe_csync_n && !csync_n;
reg x_cnt_started = 1'b0;
reg y_cnt_started = 1'b0;
reg [9:0] x_cnt;
reg [9:0] y_cnt;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
x_cnt_started <= 1'b0;
else if (csync_falling)
x_cnt_started <= 1'b1;
end
always @(posedge clk)
begin
if (csync_falling)
x_cnt <= 10'd0;
else
x_cnt <= x_cnt + 10'd1;
end
reg half_row_short = 1'b0;
reg prev_half_row_short = 1'b0;
reg lhr_first = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
y_cnt_started <= 1'b0;
half_row_short <= 1'b0;
prev_half_row_short <= 1'b0;
lhr_first <= 1'b0;
end
else
begin
if (x_cnt_started)
begin
if (csync_falling)
begin
if (x_cnt == FULL_ROW_LENGTH - 10'd1)
y_cnt <= y_cnt + 10'd1;
else if (x_cnt == LEFT_HALF_ROW_LENGTH - 10'd1)
lhr_first <= !half_row_short && prev_half_row_short;
else // if (x_cnt == RIGHT_HALF_ROW_LENGTH - 10'd1)
begin
if (lhr_first || (!half_row_short && prev_half_row_short && y_cnt_started))
begin
if (lhr_first)
begin
y_cnt <= 10'd1;
interlaced <= field_no == 1'b1;
end
else
begin
y_cnt <= 10'd0;
interlaced <= field_no == 1'b0;
end
field_no <= !lhr_first;
y_cnt_started <= 1'b1;
end
else
y_cnt <= y_cnt + 10'd1;
end
prev_half_row_short <= half_row_short;
end
if (csync_rising)
half_row_short <= (x_cnt < 10'd64);
end
end
end
wire [9:0] y_pos = y_cnt - (Y_START - 10'd1);
wire [9:0] x_pos = x_cnt - (X_START - 10'd1);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
wr_en <= 1'b0;
else
begin
if (x_cnt_started && y_cnt_started && x_pos < BOX_WIDTH && y_pos < BOX_HEIGHT)
begin
wr_address <= {y_pos[0], x_pos};
wr_en <= 1'b1;
wr_data <= {4'd0, am_rgb};
end
else
wr_en <= 1'b0;
end
end
always @(posedge clk)
begin
if (x_cnt_started && y_cnt_started && x_pos == BOX_WIDTH && y_pos < BOX_HEIGHT)
begin
s_req <= !s_ack;
s_cache_row <= y_pos[0];
s_sdram_row <= {y_pos[8:0], field_no};
end
end
endmodule |
module seg7_lut_6(
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3,
output [6:0] hex4,
output [6:0] hex5,
input [23:0] values
);
seg7_lut u0(hex0, values[3:0]);
seg7_lut u1(hex1, values[7:4]);
seg7_lut u2(hex2, values[11:8]);
seg7_lut u3(hex3, values[15:12]);
seg7_lut u4(hex4, values[19:16]);
seg7_lut u5(hex5, values[23:20]);
endmodule |
module scanline_cache (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [10:0] rdaddress;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module pll (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
endmodule |
module vga_frame_generator(
input reset_n,
input clk,
output vga_hs,
output vga_vs,
output reg [11:0] vga_rgb,
output reg [10:0] rd_address,
input [15:0] rd_data,
output reg g_req,
input g_ack,
output reg g_cache_row,
output reg [9:0] g_sdram_row,
input interlaced,
input field_no
);
// List of VGA timings: http://tinyvga.com/vga-timing
// 1280x1024p@60Hz
localparam H_SYNC = 11'd112;
localparam H_BACK = 11'd248;
localparam H_VISIBLE = 11'd1280;
localparam H_FRONT = 11'd48;
localparam H_TOTAL = 11'd1688;
localparam V_SYNC = 11'd3;
localparam V_BACK = 11'd38;
localparam V_VISIBLE = 11'd1024;
localparam V_FRONT = 11'd1;
localparam V_TOTAL = 11'd1066;
localparam X_START = H_SYNC + H_BACK;
localparam Y_START = V_SYNC + V_BACK;
localparam BOX_WIDTH = H_VISIBLE;
localparam BOX_HEIGHT = V_VISIBLE;
reg [10:0] h_cnt = 11'd0;
reg [10:0] v_cnt = 11'd0;
assign vga_hs = h_cnt >= H_SYNC;
assign vga_vs = v_cnt >= V_SYNC;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
h_cnt <= 11'd0;
v_cnt <= 11'd0;
end
else
begin
if (h_cnt == H_TOTAL - 11'd1)
begin
h_cnt <= 11'd0;
if (v_cnt == V_TOTAL - 11'd1)
v_cnt <= 11'd0;
else
v_cnt <= v_cnt + 11'd1;
end
else
h_cnt <= h_cnt + 11'd1;
end
end
wire [10:0] y_pos = v_cnt - Y_START;
wire [10:0] addr_x_pos = h_cnt - (X_START - 11'd3);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
rd_address <= 11'd0;
else
begin
if (addr_x_pos < BOX_WIDTH && y_pos < BOX_HEIGHT)
rd_address <= {y_pos[0], addr_x_pos[10:1]};
else
rd_address <= 11'd0;
end
end
wire [10:0] col_x_pos = h_cnt - (X_START - 11'd1);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
vga_rgb <= 12'h000;
end
else
begin
if (col_x_pos < BOX_WIDTH && y_pos < BOX_HEIGHT)
vga_rgb <= rd_data[11:0];
/*
else if (v_cnt >= (V_SYNC + V_BACK) && v_cnt < (V_TOTAL - V_FRONT) && h_cnt >= (H_SYNC + H_BACK) && h_cnt < (H_TOTAL - H_FRONT))
begin
if (h_cnt[0])
vga_rgb <= 12'h223;
else
vga_rgb <= 12'h333;
end*/
else
vga_rgb <= 12'h000;
end
end
wire [10:0] fetch_y_pos = v_cnt - (Y_START - 11'd1);
always @(posedge clk)
begin
if (h_cnt == 0 && fetch_y_pos < BOX_HEIGHT)
begin
g_req <= !g_ack;
g_cache_row <= fetch_y_pos[0];
if (interlaced)
g_sdram_row <= fetch_y_pos[10:1];
else
g_sdram_row <= {fetch_y_pos[10:2], field_no};
end
end
endmodule |
module id_resp_fifo #(
parameter AXI_ID_WIDTH = 8
)(
input wclk,
input rclk,
input resetn,
input [AXI_ID_WIDTH+2-1:0] data_in,
input write_en,
input read_en,
output [AXI_ID_WIDTH+2-1:0] data_out,
output full,
output empty
);
reg [AXI_ID_WIDTH+2-1:0] ram[127:0];
reg [7:0] write_addr_wclk;
reg [7:0] read_addr_rclk;
wire [7:0] write_addr_gray_wclk;
reg [7:0] write_addr_gray_rclk0;
reg [7:0] write_addr_gray_rclk1;
wire [7:0] read_addr_gray_rclk;
reg [7:0] read_addr_gray_wclk0;
reg [7:0] read_addr_gray_wclk1;
always@(posedge wclk or negedge resetn)//write addr wclk operation
if(!resetn)
write_addr_wclk <= 8'b0;
else if(write_en == 1'b1 && full != 1'b1)
write_addr_wclk <= write_addr_wclk + 1'b1;
else
write_addr_wclk <= write_addr_wclk;
always@(posedge rclk or negedge resetn)//read addr read operation
if(!resetn)
read_addr_rclk <= 8'b0;
else if(read_en == 1'b1 && empty != 1'b1)
read_addr_rclk <= read_addr_rclk + 1'b1;
else
read_addr_rclk <= read_addr_rclk;
always@(posedge wclk or negedge resetn)//sync
if(!resetn)begin
read_addr_gray_wclk0 <= 8'b0;
read_addr_gray_wclk1 <= 8'b0;
end
else begin
read_addr_gray_wclk0 <= read_addr_gray_rclk;
read_addr_gray_wclk1 <= read_addr_gray_wclk0;
end
always@(posedge rclk or negedge resetn)//sync
if(!resetn)begin
write_addr_gray_rclk0 <= 8'b0;
write_addr_gray_rclk1 <= 8'b0;
end
else begin
write_addr_gray_rclk0 <= write_addr_gray_wclk;
write_addr_gray_rclk1 <= write_addr_gray_rclk0;
end
always@(posedge wclk or negedge resetn)//data out
if(!resetn)begin
ram[0] <= 'b0;
ram[1] <= 'b0;
ram[2] <= 'b0;
ram[3] <= 'b0;
ram[4] <= 'b0;
ram[5] <= 'b0;
ram[6] <= 'b0;
ram[7] <= 'b0;
ram[8] <= 'b0;
ram[9] <= 'b0;
ram[10] <= 'b0;
ram[11] <= 'b0;
ram[12] <= 'b0;
ram[13] <= 'b0;
ram[14] <= 'b0;
ram[15] <= 'b0;
ram[16] <= 'b0;
ram[17] <= 'b0;
ram[18] <= 'b0;
ram[19] <= 'b0;
ram[20] <= 'b0;
ram[21] <= 'b0;
ram[22] <= 'b0;
ram[23] <= 'b0;
ram[24] <= 'b0;
ram[25] <= 'b0;
ram[26] <= 'b0;
ram[27] <= 'b0;
ram[28] <= 'b0;
ram[29] <= 'b0;
ram[30] <= 'b0;
ram[31] <= 'b0;
ram[32] <= 'b0;
ram[33] <= 'b0;
ram[34] <= 'b0;
ram[35] <= 'b0;
ram[36] <= 'b0;
ram[37] <= 'b0;
ram[38] <= 'b0;
ram[39] <= 'b0;
ram[40] <= 'b0;
ram[41] <= 'b0;
ram[42] <= 'b0;
ram[43] <= 'b0;
ram[44] <= 'b0;
ram[45] <= 'b0;
ram[46] <= 'b0;
ram[47] <= 'b0;
ram[48] <= 'b0;
ram[49] <= 'b0;
ram[50] <= 'b0;
ram[51] <= 'b0;
ram[52] <= 'b0;
ram[53] <= 'b0;
ram[54] <= 'b0;
ram[55] <= 'b0;
ram[56] <= 'b0;
ram[57] <= 'b0;
ram[58] <= 'b0;
ram[59] <= 'b0;
ram[60] <= 'b0;
ram[61] <= 'b0;
ram[62] <= 'b0;
ram[63] <= 'b0;
ram[64] <= 'b0;
ram[65] <= 'b0;
ram[66] <= 'b0;
ram[67] <= 'b0;
ram[68] <= 'b0;
ram[69] <= 'b0;
ram[70] <= 'b0;
ram[71] <= 'b0;
ram[72] <= 'b0;
ram[73] <= 'b0;
ram[74] <= 'b0;
ram[75] <= 'b0;
ram[76] <= 'b0;
ram[77] <= 'b0;
ram[78] <= 'b0;
ram[79] <= 'b0;
ram[80] <= 'b0;
ram[81] <= 'b0;
ram[82] <= 'b0;
ram[83] <= 'b0;
ram[84] <= 'b0;
ram[85] <= 'b0;
ram[86] <= 'b0;
ram[87] <= 'b0;
ram[88] <= 'b0;
ram[89] <= 'b0;
ram[90] <= 'b0;
ram[91] <= 'b0;
ram[92] <= 'b0;
ram[93] <= 'b0;
ram[94] <= 'b0;
ram[95] <= 'b0;
ram[96] <= 'b0;
ram[97] <= 'b0;
ram[98] <= 'b0;
ram[99] <= 'b0;
ram[100] <= 'b0;
ram[101] <= 'b0;
ram[102] <= 'b0;
ram[103] <= 'b0;
ram[104] <= 'b0;
ram[105] <= 'b0;
ram[106] <= 'b0;
ram[107] <= 'b0;
ram[108] <= 'b0;
ram[109] <= 'b0;
ram[110] <= 'b0;
ram[111] <= 'b0;
ram[112] <= 'b0;
ram[113] <= 'b0;
ram[114] <= 'b0;
ram[115] <= 'b0;
ram[116] <= 'b0;
ram[117] <= 'b0;
ram[118] <= 'b0;
ram[119] <= 'b0;
ram[120] <= 'b0;
ram[121] <= 'b0;
ram[122] <= 'b0;
ram[123] <= 'b0;
ram[124] <= 'b0;
ram[125] <= 'b0;
ram[126] <= 'b0;
ram[127] <= 'b0;
end
else if(full == 1'b0 && write_en == 1'b1)
ram[write_addr_wclk[6:0]] <= data_in;
assign full = (write_addr_gray_wclk[7] != read_addr_gray_wclk1[7])?
(write_addr_gray_wclk[6] != read_addr_gray_wclk1[6])?
(write_addr_gray_wclk[5:0] == read_addr_gray_wclk1[5:0])?1'b1:1'b0:1'b0:1'b0;
assign empty = (write_addr_gray_rclk1 == read_addr_gray_rclk)?1'b1:1'b0;
assign data_out = ((read_en == 1'b1) && (empty != 1'b1))?ram[read_addr_rclk[6:0]]:'b0;
assign write_addr_gray_wclk = (write_addr_wclk>>1)^write_addr_wclk;
assign read_addr_gray_rclk = (read_addr_rclk>>1)^read_addr_rclk;
endmodule |
module ahb_controller(
input hclk,
input hresetn,
//ahb output
output reg [31:0] haddr,
output reg [1:0] htrans,
output reg hwrite,
output reg [2:0] hsize,
output reg [2:0] hburst,
output reg [63:0] hwdata,
output reg hbusreq,
output reg hlock,
//ahb input
input [63:0] hrdata,
input hready,
input [1:0] hresp,
input hgrant,
input [3:0] hmaster,
//addr_fifo in
output addr_r_en,
input [31:0] ahb_addr,
input addr_fifo_empty,
//data_fifo in
output data_r_en,
input [63:0] ahb_data,
input data_fifo_empty,
// write or read state fifo (1 write 0 read) in
output state_r_en,
input ahb_write,
input state_fifo_empty,
//id_send_fifo in
output id_send_r_en,
input [8:0] ahb_id,
input id_send_fifo_empty,
//size_fifo in
output size_r_en,
input [2:0] ahb_size,
input size_fifo_empty,
//rdata_fifo out
output rdata_w_en,
output reg [63:0] ahb_rdata,
input rdata_fifo_full,
//resp_fifo out
output resp_w_en,
output reg [1:0] ahb_resp,
input resp_fifo_full,
//id_resp out
output id_resp_w_en,
output reg [9:0] ahb_id_resp,
input id_resp_fifo_full
);
parameter
IDLE = 5'b00001,
START = 5'b00010,
ADDR_PHASE = 5'b00100,
DATA_PHASE = 5'b01000,
END_PHASE = 5'b10000;
reg read_lock;
wire ahb_access;
assign ahb_access = (hgrant == 1'b1 && hmaster == 4'b0)?1'b1:1'b0;
wire fifo_r_control_access,fifo_r_data_access,fifo_w_access;
assign fifo_r_control_access = (read_lock == 1'b1)?1'b1:(addr_fifo_empty|state_fifo_empty|id_send_fifo_empty|size_fifo_empty);
assign fifo_r_data_access = data_fifo_empty;
assign fifo_w_access = rdata_fifo_full|resp_fifo_full|id_resp_fifo_full;
reg [4:0] cstate,nstate;
reg [8:0] id_reg;
//addr_fifo in
reg addr_r_en_reg;
assign addr_r_en = addr_r_en_reg&hready;
//data_fifo in
reg data_r_en_reg;
assign data_r_en = data_r_en_reg&hready;
// write or read state fifo (1 write 0 read) in
reg state_r_en_reg;
assign state_r_en = state_r_en_reg&hready;
//id_send_fifo in
reg id_send_r_en_reg;
assign id_send_r_en = id_send_r_en_reg&hready;
//size_fifo in
reg size_r_en_reg;
assign size_r_en = size_r_en_reg&hready;
//rdata_fifo out
reg rdata_w_en_reg;
assign rdata_w_en = rdata_w_en_reg&hready;
//resp_fifo out
reg resp_w_en_reg;
assign resp_w_en = resp_w_en_reg&hready;
//id_resp out
reg id_resp_w_en_reg;
assign id_resp_w_en = id_resp_w_en_reg&hready;
always@(posedge hclk or negedge hresetn)
if(!hresetn)begin
hbusreq <= 1'b0;
hlock <= 1'b0;
end
else if(hgrant == 1'b0)
hbusreq <= 1'b1;
else
hbusreq <= 1'b0;
always@(posedge hclk or negedge hresetn)
if(!hresetn)
cstate <= IDLE;
else
cstate <= nstate;
always@(*)
case(cstate)
IDLE:begin
if(ahb_access == 1'b0)
nstate = IDLE;
else if(fifo_r_control_access == 1'b0)
nstate = START;
else
nstate = IDLE;
end
START:begin
if(hready == 1'b0)
nstate = START;
else
nstate = ADDR_PHASE;
end
ADDR_PHASE:begin
if(hready == 1'b1)
nstate = DATA_PHASE;
else
nstate = ADDR_PHASE;
end
DATA_PHASE:begin
if(hready == 1'b1 && (fifo_r_data_access == 1'b1 || (fifo_r_data_access == 1'b0 && read_lock == 1'b1)))
nstate = END_PHASE;
else
nstate = DATA_PHASE;
end
END_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)
nstate = START;
else
nstate = IDLE;
end
endcase
always@(posedge hclk or negedge hresetn)
if(!hresetn)begin
//ahb output
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 9'b0;
//addr_fifo in
addr_r_en_reg <= 1'b0;
//data_fifo in
data_r_en_reg <= 1'b0;
// write or read state fifo (1 write 0 read) in
state_r_en_reg <= 1'b0;
//id_send_fifo in
id_send_r_en_reg <= 1'b0;
//size_fifo in
size_r_en_reg <= 1'b0;
//rdata_fifo out
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
//resp_fifo out
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
//id_resp out
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
read_lock <= 1'b0;
end
else
case(cstate)
IDLE:begin
if(ahb_access == 1'b1 && hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 9'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
read_lock <= 1'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 9'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
read_lock <= 1'b0;
end
end
START:begin
if(hready == 1'b1)begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= ahb_id;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
read_lock <= 1'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 9'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
read_lock <= 1'b0;
end
end
ADDR_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= ahb_id;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= 9'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
read_lock <= 1'b1;
end
else begin
haddr <= haddr;
htrans <= htrans;
hwrite <= hwrite;
hsize <= hsize;
hburst <= hburst;
hwdata <= hwdata;
id_reg <= id_reg;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
end
end
DATA_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= ahb_id;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1 && fifo_r_data_access == 1'b0 && read_lock == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= 9'b0;
read_lock <= 1'b1;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1 && (fifo_r_data_access == 1'b1 || (fifo_r_data_access == 1'b0 && read_lock == 1'b1)))begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 9'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
end
else if(hready == 1'b0)begin
haddr <= haddr;
htrans <= htrans;
hwrite <= hwrite;
hsize <= hsize;
hburst <= hburst;
hwdata <= hwdata;
id_reg <= id_reg;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
if(fifo_r_control_access == 1'b0)begin
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else begin
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
end
end
end
END_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 10'b0;
end
end
endcase
endmodule |
module write_fifo(
input wclk,
input rclk,
input resetn,
input data_in,
input write_en,
input read_en,
output data_out,
output full,
output empty
);
reg [127:0] ram;
reg [7:0] write_addr_wclk;
reg [7:0] read_addr_rclk;
wire [7:0] write_addr_gray_wclk;
reg [7:0] write_addr_gray_rclk0;
reg [7:0] write_addr_gray_rclk1;
wire [7:0] read_addr_gray_rclk;
reg [7:0] read_addr_gray_wclk0;
reg [7:0] read_addr_gray_wclk1;
always@(posedge wclk or negedge resetn)//write addr wclk operation
if(!resetn)
write_addr_wclk <= 8'b0;
else if(write_en == 1'b1 && full != 1'b1)
write_addr_wclk <= write_addr_wclk + 1'b1;
else
write_addr_wclk <= write_addr_wclk;
always@(posedge rclk or negedge resetn)//read addr read operation
if(!resetn)
read_addr_rclk <= 8'b0;
else if(read_en == 1'b1 && empty != 1'b1)
read_addr_rclk <= read_addr_rclk + 1'b1;
else
read_addr_rclk <= read_addr_rclk;
always@(posedge wclk or negedge resetn)//sync
if(!resetn)begin
read_addr_gray_wclk0 <= 8'b0;
read_addr_gray_wclk1 <= 8'b0;
end
else begin
read_addr_gray_wclk0 <= read_addr_gray_rclk;
read_addr_gray_wclk1 <= read_addr_gray_wclk0;
end
always@(posedge rclk or negedge resetn)//sync
if(!resetn)begin
write_addr_gray_rclk0 <= 8'b0;
write_addr_gray_rclk1 <= 8'b0;
end
else begin
write_addr_gray_rclk0 <= write_addr_gray_wclk;
write_addr_gray_rclk1 <= write_addr_gray_rclk0;
end
always@(posedge wclk or negedge resetn)//data out
if(!resetn)
ram <= 128'b0;
else if(full == 1'b0 && write_en == 1'b1)
ram[write_addr_wclk[6:0]] <= data_in;
assign full = (write_addr_gray_wclk[7] != read_addr_gray_wclk1[7])?
(write_addr_gray_wclk[6] != read_addr_gray_wclk1[6])?
(write_addr_gray_wclk[5:0] == read_addr_gray_wclk1[5:0])?1'b1:1'b0:1'b0:1'b0;
assign empty = (write_addr_gray_rclk1 == read_addr_gray_rclk)?1'b1:1'b0;
assign data_out = ((read_en == 1'b1) && (empty != 1'b1))?ram[read_addr_rclk[6:0]]:31'b0;
assign write_addr_gray_wclk = (write_addr_wclk>>1)^write_addr_wclk;
assign read_addr_gray_rclk = (read_addr_rclk>>1)^read_addr_rclk;
endmodule |
module fifo2axi #(
parameter AXI_ID_WIDTH = 8
)(
input aclk,
input aresetn,
//rdata_fifo
output rdata_r_en,
input [63:0] axi_rdata,
input rdata_fifo_empty,
//resp_fifo
output resp_r_en,
input [1:0] axi_resp,
input resp_fifo_empty,
//id_resp
output id_resp_r_en,
input [AXI_ID_WIDTH+2-1:0] axi_id_resp,
input id_resp_fifo_empty,
//b response
output reg [AXI_ID_WIDTH-1:0] bid,
output reg [1:0] bresp,
output reg bvalid,
input bready,
//r response
output reg [AXI_ID_WIDTH-1:0] rid,
output reg [63:0] rdata,
output reg [1:0] rresp,
output reg rlast,
output reg rvalid,
input rready
);//read directly
wire ready;
assign ready = bready&rready;
wire fifo_empty;
assign fifo_empty = rdata_fifo_empty|resp_fifo_empty|id_resp_fifo_empty;
wire read_en;
wire ready_for_read;
//assign read_en = (!rdata_fifo_empty)&(!resp_fifo_empty)&(!id_resp_fifo_empty)&ready;
//assign read_en = (!rdata_fifo_empty)&(!resp_fifo_empty)&(!id_resp_fifo_empty);
assign ready_for_read = (~rvalid & ~bvalid) | (rvalid & rready) | (bvalid & bready);
assign read_en = (!rdata_fifo_empty)&(!resp_fifo_empty)&(!id_resp_fifo_empty)&ready_for_read;
assign rdata_r_en = read_en;
assign resp_r_en = read_en;
assign id_resp_r_en = read_en;
//reg ready_for_read;
//always@(posedge aclk or negedge aresetn) begin
// if(!aresetn)begin
// ready_for_read <= 'b1;
// end
// else if(rvalid == 1'b1)begin
// if(rready == 1'b1) begin
// ready_for_read <= 'b1;
// end
// else begin
// ready_for_read <= 'b0;
// end
// end
// else if(bvalid == 1'b1)begin
// if(bready == 1'b1) begin
// ready_for_read <= 'b1;
// end
// else begin
// ready_for_read <= 'b0;
// end
// end
// else begin
// ready_for_read <= 'b1;
// end
//end
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
bid <= 'b0;
bresp <= 2'b0;
bvalid <= 1'b0;
rid <= 'b0;
rdata <= 64'b0;
rresp <= 2'b0;
rlast <= 1'b0;
rvalid <= 1'b0;
end
else if(read_en == 1'b1)begin
if(axi_id_resp[AXI_ID_WIDTH+1] == 1'b1)begin
bid <= axi_id_resp[AXI_ID_WIDTH-1:0];
bresp <= axi_resp;
bvalid <= axi_id_resp[AXI_ID_WIDTH];
rid <= 'b0;
rdata <= 64'b0;
rresp <= 2'b0;
rlast <= 1'b0;
rvalid <= 1'b0;
end
else begin
bid <= 'b0;
bresp <= 2'b0;
bvalid <= 1'b0;
rid <= axi_id_resp[AXI_ID_WIDTH-1:0];
rdata <= axi_rdata;
rresp <= axi_resp;
rlast <= axi_id_resp[AXI_ID_WIDTH];
rvalid <= 1'b1;
end
end
else if(rvalid == 1'b1 && rready == 1'b0)begin
bid <= 'b0;
bresp <= 2'b0;
bvalid <= 1'b0;
rid <= rid;
rdata <= rdata;
rresp <= rresp;
rlast <= rlast;
rvalid <= 1'b1;
end
else if(bvalid == 1'b1 && bready == 1'b0)begin
bid <= bid;
bresp <= bresp;
bvalid <= 1'b1;
rid <= 'b0;
rdata <= 64'b0;
rresp <= 2'b0;
rlast <= 1'b0;
rvalid <= 1'b0;
end
else if(fifo_empty == 1'b1)begin
bid <= 'b0;
bresp <= 2'b0;
bvalid <= 1'b0;
rid <= 'b0;
rdata <= 64'b0;
rresp <= 2'b0;
rlast <= 1'b0;
rvalid <= 1'b0;
end
endmodule |
module ahb_controller #(
parameter AXI_ID_WIDTH = 8
)(
input hclk,
input hresetn,
//ahb output
output reg [31:0] haddr,
output reg [1:0] htrans,
output reg hwrite,
output reg [2:0] hsize,
output reg [2:0] hburst,
output reg [63:0] hwdata,
output reg hbusreq,
output reg hlock,
//ahb input
input [63:0] hrdata,
input hready,
input [1:0] hresp,
input hgrant,
input [3:0] hmaster,
//addr_fifo in
output addr_r_en,
input [31:0] ahb_addr,
input addr_fifo_empty,
//data_fifo in
output data_r_en,
input [63:0] ahb_data,
input data_fifo_empty,
// write or read state fifo (1 write 0 read) in
output state_r_en,
input ahb_write,
input state_fifo_empty,
//id_send_fifo in
output id_send_r_en,
input [AXI_ID_WIDTH+1-1:0] ahb_id,
input id_send_fifo_empty,
//size_fifo in
output size_r_en,
input [2:0] ahb_size,
input size_fifo_empty,
//rdata_fifo out
output rdata_w_en,
output reg [63:0] ahb_rdata,
input rdata_fifo_full,
input rdata_fifo_empty,
//resp_fifo out
output resp_w_en,
output reg [1:0] ahb_resp,
input resp_fifo_full,
//id_resp out
output id_resp_w_en,
output reg [AXI_ID_WIDTH+2-1:0] ahb_id_resp,
input id_resp_fifo_full
);
parameter
IDLE = 5'b00001,
START = 5'b00010,
ADDR_PHASE = 5'b00100,
DATA_PHASE = 5'b01000,
END_PHASE = 5'b10000;
reg read_lock;
wire ahb_access;
assign ahb_access = (hgrant == 1'b1 && hmaster == 4'b0)?1'b1:1'b0;
wire fifo_r_control_access,fifo_r_data_access,fifo_w_access;
assign fifo_r_control_access = (read_lock == 1'b1)?1'b1:(addr_fifo_empty|state_fifo_empty|id_send_fifo_empty|size_fifo_empty);
assign fifo_r_data_access = data_fifo_empty;
assign fifo_w_access = rdata_fifo_full|resp_fifo_full|id_resp_fifo_full;
reg [4:0] cstate,nstate;
reg [AXI_ID_WIDTH+1-1:0] id_reg;
wire ready_for_read;
assign ready_for_read = ~((cstate == DATA_PHASE) & id_resp_w_en & ((ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01) | (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b11)) & (nstate!=cstate));
//addr_fifo in
reg addr_r_en_reg;
assign addr_r_en = addr_r_en_reg&hready&ready_for_read/* & (~((nstate==END_PHASE)&(~addr_fifo_empty)))*/;
//data_fifo in
reg data_r_en_reg;
assign data_r_en = data_r_en_reg&hready&ready_for_read/* & (~((nstate==END_PHASE)&(~data_fifo_empty)))*/;
// write or read state fifo (1 write 0 read) in
reg state_r_en_reg;
assign state_r_en = state_r_en_reg&hready&ready_for_read/* & (~((nstate==END_PHASE)&(~state_fifo_empty)))*/;
//id_send_fifo in
reg id_send_r_en_reg;
assign id_send_r_en = id_send_r_en_reg&hready&ready_for_read/* & (~((nstate==END_PHASE)&(~id_send_fifo_empty)))*/;
//size_fifo in
reg size_r_en_reg;
assign size_r_en = size_r_en_reg&hready&ready_for_read/* & (~((nstate==END_PHASE)&(~size_fifo_empty)))*/;
//rdata_fifo out
reg rdata_w_en_reg;
assign rdata_w_en = rdata_w_en_reg&hready;
//resp_fifo out
reg resp_w_en_reg;
assign resp_w_en = resp_w_en_reg&hready;
//id_resp out
reg id_resp_w_en_reg;
assign id_resp_w_en = id_resp_w_en_reg&hready;
//added by yjl
///////////////////////////////////////////////////////////////////////////
wire reading;
wire writing;
reg ahb_reading;
reg read_done;
reg ahb_writing;
reg write_done;
always@(posedge hclk or negedge hresetn) begin
if(!hresetn)begin
ahb_reading <= 1'b0;
end
else if(hwrite == 1'b0) begin
ahb_reading <= 1'b1;
end
else if(id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01)) begin
ahb_reading <= 1'b0;
end
end
assign reading = (hwrite==1'b0) | ahb_reading;
always@(posedge hclk or negedge hresetn) begin
if(!hresetn)begin
read_done <= 1'b0;
end
else begin
read_done <= id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01);
end
end
always@(posedge hclk or negedge hresetn) begin
if(!hresetn)begin
ahb_writing <= 1'b0;
end
else if(hwrite == 1'b1 && htrans!=2'd0) begin
ahb_writing <= 1'b1;
end
else if(id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b11)) begin
ahb_writing <= 1'b0;
end
end
assign writing = ((hwrite==1'b1) && (htrans!=2'd0)) | ahb_writing;
always@(posedge hclk or negedge hresetn) begin
if(!hresetn)begin
write_done <= 1'b0;
end
else begin
write_done <= id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b11);
end
end
//wire read_done;
//reg rdata_fifo_empty_reg;
//always@(posedge hclk or negedge hresetn) begin
// if(!hresetn)begin
// rdata_fifo_empty_reg <= 1'b0;
// end
// else begin
// rdata_fifo_empty_reg <= rdata_fifo_empty;
// end
//end
//assign read_done = ~rdata_fifo_empty_reg & rdata_fifo_empty;
///////////////////////////////////////////////////////////////////////////
always@(posedge hclk or negedge hresetn)
if(!hresetn)begin
hbusreq <= 1'b0;
hlock <= 1'b0;
end
else if(hgrant == 1'b0)
hbusreq <= 1'b1;
else
hbusreq <= 1'b0;
always@(posedge hclk or negedge hresetn)
if(!hresetn)
cstate <= IDLE;
else
cstate <= nstate;
always@(*)
case(cstate)
IDLE:begin
if(ahb_access == 1'b0)
nstate = IDLE;
else if(fifo_r_control_access == 1'b0)
nstate = START;
else
nstate = IDLE;
end
START:begin
if(hready == 1'b0)
nstate = START;
else
nstate = ADDR_PHASE;
end
ADDR_PHASE:begin
if(hready == 1'b1)
nstate = DATA_PHASE;
else
nstate = ADDR_PHASE;
end
DATA_PHASE:begin
if(reading) begin
if(id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01)) begin
if(hwrite==1'b0) begin
nstate = DATA_PHASE;
end
else if(hwrite == 1'b1 && htrans!=2'd0) begin
nstate = DATA_PHASE;
end
/////////////////////////////////////////////
//else if(state_r_en & ~state_fifo_empty) begin
// //nstate = DATA_PHASE;
// nstate = START;
//end
/////////////////////////////////////////////
else begin
nstate = END_PHASE;
end
end
else begin
nstate = DATA_PHASE;
end
end
else if(writing) begin
if(id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b11)) begin
if(hwrite == 1'b1 && htrans!=2'd0) begin
nstate = DATA_PHASE;
end
else if(hwrite==1'b0) begin
nstate = DATA_PHASE;
end
/////////////////////////////////////////////
//else if(state_r_en & ~state_fifo_empty) begin
// nstate = DATA_PHASE;
//end
///////////////////////////////////////////////
else begin
nstate = END_PHASE;
end
end
else begin
nstate = DATA_PHASE;
end
end
else if(hready == 1'b1 && (fifo_r_data_access == 1'b1 || (fifo_r_data_access == 1'b0 && read_lock == 1'b1)))
nstate = END_PHASE;
else
nstate = DATA_PHASE;
end
END_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)
nstate = START;
else
nstate = IDLE;
end
endcase
always@(posedge hclk or negedge hresetn)
if(!hresetn)begin
//ahb output
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
//addr_fifo in
addr_r_en_reg <= 1'b0;
//data_fifo in
data_r_en_reg <= 1'b0;
// write or read state fifo (1 write 0 read) in
state_r_en_reg <= 1'b0;
//id_send_fifo in
id_send_r_en_reg <= 1'b0;
//size_fifo in
size_r_en_reg <= 1'b0;
//rdata_fifo out
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
//resp_fifo out
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
//id_resp out
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
read_lock <= 1'b0;
end
else
case(cstate)
IDLE:begin
if(ahb_access == 1'b1 && hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
read_lock <= 1'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
read_lock <= 1'b0;
end
end
START:begin
if(hready == 1'b1)begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= ahb_id;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
read_lock <= 1'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
read_lock <= 1'b0;
end
end
ADDR_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= ahb_id;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= 'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
read_lock <= 1'b1;
end
else begin
haddr <= haddr;
htrans <= htrans;
hwrite <= hwrite;
hsize <= hsize;
hburst <= hburst;
hwdata <= hwdata;
id_reg <= id_reg;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
end
DATA_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
//haddr <= ahb_addr;
//htrans <= 2'd2;
//hwrite <= ahb_write;
//hsize <= ahb_size;
//hburst <= 3'b0;
//hwdata <= ahb_data;
//id_reg <= ahb_id;
if(nstate==DATA_PHASE) begin
haddr <= ahb_addr;
htrans <= 2'd2;
hwrite <= ahb_write;
hsize <= ahb_size;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= ahb_id;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
end
//addr_r_en_reg <= 1'b1;
//data_r_en_reg <= 1'b1;
//state_r_en_reg <= 1'b1;
//id_send_r_en_reg <= 1'b1;
//size_r_en_reg <= 1'b1;
if(nstate==DATA_PHASE) begin
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
end
else begin
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
end
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
//id_resp_w_en_reg <= 1'b1;
//ahb_id_resp <= {hwrite,id_reg};
//
//if((/*(reading==1'b0) |*/ ((reading==1'b1) & id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01))) & hwrite) begin
// id_resp_w_en_reg <= 1'b0;
// ahb_id_resp <= 'b0;
//end
//else begin
// id_resp_w_en_reg <= 1'b1;
// ahb_id_resp <= {hwrite,id_reg};
//end
//
if(nstate==DATA_PHASE) begin
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else begin
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1 && fifo_r_data_access == 1'b0 && read_lock == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= ahb_data;
id_reg <= 'b0;
read_lock <= 1'b1;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
else if(hready == 1'b1 && fifo_r_control_access == 1'b1 && (fifo_r_data_access == 1'b1 || (fifo_r_data_access == 1'b0 && read_lock == 1'b1)))begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
id_reg <= 'b0;
//if(state_r_en & ~state_fifo_empty) begin
// haddr <= ahb_addr;
// htrans <= 2'd2;
// hwrite <= ahb_write;
// hsize <= ahb_size;
// hburst <= 3'b0;
// hwdata <= ahb_data;
// id_reg <= ahb_id;
//end
//else begin
// haddr <= 32'b0;
// htrans <= 2'b0;
// hwrite <= 1'b1;
// hsize <= 3'b0;
// hburst <= 3'b0;
// hwdata <= 64'b0;
// id_reg <= 'b0;
//end
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
//if(state_r_en & ~state_fifo_empty) begin
// addr_r_en_reg <= 1'b1;
// data_r_en_reg <= 1'b1;
// state_r_en_reg <= 1'b1;
// id_send_r_en_reg <= 1'b1;
// size_r_en_reg <= 1'b1;
//end
//else begin
// addr_r_en_reg <= 1'b0;
// data_r_en_reg <= 1'b0;
// state_r_en_reg <= 1'b0;
// id_send_r_en_reg <= 1'b0;
// size_r_en_reg <= 1'b0;
//end
rdata_w_en_reg <= 1'b1;
ahb_rdata <= hrdata;
resp_w_en_reg <= 1'b1;
ahb_resp <= hresp;
//if(read_done & writing) begin
// rdata_w_en_reg <= 1'b0;
// ahb_rdata <= 64'd0;
// resp_w_en_reg <= 1'b0;
// ahb_resp <= 2'd0;
//end
//else if(write_done & reading) begin
// rdata_w_en_reg <= 1'b0;
// ahb_rdata <= 64'd0;
// resp_w_en_reg <= 1'b0;
// ahb_resp <= 2'd0;
//end
//else if(read_done & reading) begin
// rdata_w_en_reg <= 1'b0;
// ahb_rdata <= 64'd0;
// resp_w_en_reg <= 1'b0;
// ahb_resp <= 2'd0;
//end
//else if(write_done & writing) begin
// rdata_w_en_reg <= 1'b0;
// ahb_rdata <= 64'd0;
// resp_w_en_reg <= 1'b0;
// ahb_resp <= 2'd0;
//end
//else begin
// rdata_w_en_reg <= 1'b1;
// ahb_rdata <= hrdata;
// resp_w_en_reg <= 1'b1;
// ahb_resp <= hresp;
//end
if(/*(reading==1'b0) |*/ ((reading==1'b1) & id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b01))) begin
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
else if(((writing==1'b1) & id_resp_w_en & (ahb_id_resp[AXI_ID_WIDTH+1:AXI_ID_WIDTH]==2'b11))) begin
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
else begin
id_resp_w_en_reg <= 1'b1;
ahb_id_resp <= {hwrite,id_reg};
end
end
else if(hready == 1'b0)begin
haddr <= haddr;
htrans <= htrans;
hwrite <= hwrite;
hsize <= hsize;
hburst <= hburst;
hwdata <= hwdata;
id_reg <= id_reg;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b1;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
//if(fifo_r_control_access == 1'b0)begin
// addr_r_en_reg <= 1'b1;
// state_r_en_reg <= 1'b1;
// id_send_r_en_reg <= 1'b1;
// size_r_en_reg <= 1'b1;
//end
//else begin
// addr_r_en_reg <= 1'b0;
// state_r_en_reg <= 1'b0;
// id_send_r_en_reg <= 1'b0;
// size_r_en_reg <= 1'b0;
//end
//if(fifo_r_data_access == 1'b0)begin
// data_r_en_reg <= 1'b1;
//end
//else begin
// data_r_en_reg <= 1'b0;
//end
if(fifo_r_control_access == 1'b0)begin
rdata_w_en_reg <= rdata_w_en_reg;
ahb_rdata <= ahb_rdata;
resp_w_en_reg <= resp_w_en_reg;
ahb_resp <= ahb_resp;
id_resp_w_en_reg <= id_resp_w_en_reg;
ahb_id_resp <= ahb_id_resp;
end
else begin
rdata_w_en_reg <= rdata_w_en_reg;
ahb_rdata <= ahb_rdata;
resp_w_en_reg <= resp_w_en_reg;
ahb_resp <= ahb_resp;
id_resp_w_en_reg <= id_resp_w_en_reg;
ahb_id_resp <= ahb_id_resp;
end
end
end
END_PHASE:begin
if(hready == 1'b1 && fifo_r_control_access == 1'b0)begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
addr_r_en_reg <= 1'b1;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b1;
id_send_r_en_reg <= 1'b1;
size_r_en_reg <= 1'b1;
//if(nstate == START) begin
// rdata_w_en_reg <= 1'b1;
// ahb_rdata <= hrdata;
// resp_w_en_reg <= 1'b1;
// ahb_resp <= hresp;
//end
//else begin
// rdata_w_en_reg <= 1'b0;
// ahb_rdata <= 64'b0;
// resp_w_en_reg <= 1'b0;
// ahb_resp <= 2'b0;
//end
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
else begin
haddr <= 32'b0;
htrans <= 2'b0;
hwrite <= 1'b1;
hsize <= 3'b0;
hburst <= 3'b0;
hwdata <= 64'b0;
addr_r_en_reg <= 1'b0;
data_r_en_reg <= 1'b0;
state_r_en_reg <= 1'b0;
id_send_r_en_reg <= 1'b0;
size_r_en_reg <= 1'b0;
rdata_w_en_reg <= 1'b0;
ahb_rdata <= 64'b0;
resp_w_en_reg <= 1'b0;
ahb_resp <= 2'b0;
id_resp_w_en_reg <= 1'b0;
ahb_id_resp <= 'b0;
end
end
endcase
endmodule |
module axi_controller #(
parameter AXI_ID_WIDTH = 8
)(
input aclk,
input aresetn,
//axi2fifo
//aw channel
input [AXI_ID_WIDTH-1:0] awid,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input awvalid,
output awready,
//w channel
input [63:0] wdata,
input [7:0] wstrb,
input wlast,
input wvalid,
output wready,
//ar channel
input [AXI_ID_WIDTH-1:0] arid,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input arvalid,
output arready,
//addr fifo in
output [31:0] axi_addr,
output addr_w_en,
input addr_fifo_full,
//data fifo in
output [63:0] axi_data,
output data_w_en,
input data_fifo_full,
//write fifo in
output axi_write,
output state_w_en,
input state_fifo_full,
//id_send fifo in
output [AXI_ID_WIDTH+1-1:0] axi_id,
output id_send_w_en,
input id_send_fifo_full,
//size fifo
output [2:0] axi_size,
output size_w_en,
input size_fifo_full,
//fifo2axi
//rdata_fifo
output rdata_r_en,
input [63:0] axi_rdata,
input rdata_fifo_empty,
//resp_fifo
output resp_r_en,
input [1:0] axi_resp,
input resp_fifo_empty,
//id_resp
output id_resp_r_en,
input [AXI_ID_WIDTH+2-1:0] axi_id_resp,
input id_resp_fifo_empty,
//b response
output [AXI_ID_WIDTH-1:0] bid,
output [1:0] bresp,
output bvalid,
input bready,
//r response
output [AXI_ID_WIDTH-1:0] rid,
output [63:0] rdata,
output [1:0] rresp,
output rlast,
output rvalid,
input rready
);
axi2fifo
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) u0
(
.aclk(aclk),
.aresetn(aresetn),
.awid(awid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awvalid(awvalid),
.awready(awready),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.arid(arid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arvalid(arvalid),
.arready(arready),
.axi_addr(axi_addr),
.addr_w_en(addr_w_en),
.addr_fifo_full(addr_fifo_full),
.axi_data(axi_data),
.data_w_en(data_w_en),
.data_fifo_full(data_fifo_full),
.axi_write(axi_write),
.state_w_en(state_w_en),
.state_fifo_full(state_fifo_full),
.axi_id(axi_id),
.id_send_w_en(id_send_w_en),
.id_send_fifo_full(id_send_fifo_full),
.axi_size(axi_size),
.size_w_en(size_w_en),
.size_fifo_full(size_fifo_full)
);//rlast state set at highest bit of id fifo
fifo2axi
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) u1
(
.aclk(aclk),
.aresetn(aresetn),
.rdata_r_en(rdata_r_en),
.axi_rdata(axi_rdata),
.rdata_fifo_empty(rdata_fifo_empty),
.resp_r_en(resp_r_en),
.axi_resp(axi_resp),
.resp_fifo_empty(resp_fifo_empty),
.id_resp_r_en(id_resp_r_en),
.axi_id_resp(axi_id_resp),
.id_resp_fifo_empty(id_resp_fifo_empty),
.bid(bid),
.bresp(bresp),
.bvalid(bvalid),
.bready(bready),
.rid(rid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast),
.rvalid(rvalid),
.rready(rready)
);//read directly
endmodule |
module fifo_wrapper #(
parameter AXI_ID_WIDTH = 8
)(
input aclk,
input aresetn,
input hclk,
input hresetn,
//addr_fifo
input [31:0] axi_addr,
input addr_w_en,
input addr_r_en,
output [31:0] ahb_addr,
output addr_fifo_full,
output addr_fifo_empty,
//data_fifo
input [63:0] axi_data,
input data_w_en,
input data_r_en,
output [63:0] ahb_data,
output data_fifo_full,
output data_fifo_empty,
// write or read state fifo (1 write 0 read)
input axi_write,
input state_w_en,
input state_r_en,
output ahb_write,
output state_fifo_full,
output state_fifo_empty,
//id_send_fifo
input [AXI_ID_WIDTH+1-1:0] axi_id,
input id_send_w_en,
input id_send_r_en,
output [AXI_ID_WIDTH+1-1:0] ahb_id,
output id_send_fifo_full,
output id_send_fifo_empty,
//size_fifo
input [2:0] axi_size,
input size_w_en,
input size_r_en,
output [2:0] ahb_size,
output size_fifo_full,
output size_fifo_empty,
//rdata_fifo
input [63:0] ahb_rdata,
input rdata_w_en,
input rdata_r_en,
output [63:0] axi_rdata,
output rdata_fifo_full,
output rdata_fifo_empty,
//resp_fifo
input [1:0] ahb_resp,
input resp_w_en,
input resp_r_en,
output [1:0] axi_resp,
output resp_fifo_full,
output resp_fifo_empty,
//id_resp
input [AXI_ID_WIDTH+2-1:0] ahb_id_resp,
input id_resp_w_en,
input id_resp_r_en,
output [AXI_ID_WIDTH+2-1:0] axi_id_resp,
output id_resp_fifo_full,
output id_resp_fifo_empty
);
//ahb to axi
id_resp_fifo
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) id_resp_fifo
(
.wclk(hclk),
.rclk(aclk),
.resetn(aresetn),
.data_in(ahb_id_resp),
.write_en(id_resp_w_en),
.read_en(id_resp_r_en),
.data_out(axi_id_resp),
.full(id_resp_fifo_full),
.empty(id_resp_fifo_empty)
);
resp_fifo resp_fifo_mod(
.wclk(hclk),
.rclk(aclk),
.resetn(aresetn),
.data_in(ahb_resp),
.write_en(resp_w_en),
.read_en(resp_r_en),
.data_out(axi_resp),
.full(resp_fifo_full),
.empty(resp_fifo_empty)
);
rdata_fifo rdata_fifo_mod(
.wclk(hclk),
.rclk(aclk),
.resetn(aresetn),
.data_in(ahb_rdata),
.write_en(rdata_w_en),
.read_en(rdata_r_en),
.data_out(axi_rdata),
.full(rdata_fifo_full),
.empty(rdata_fifo_empty)
);
//axi to ahb
size_fifo size_fifo_mod(
.wclk(aclk),
.rclk(hclk),
.resetn(aresetn),
.data_in(axi_size),
.write_en(size_w_en),
.read_en(size_r_en),
.data_out(ahb_size),
.full(size_fifo_full),
.empty(size_fifo_empty)
);
id_send_fifo
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) id_send_fifo_mod
(
.wclk(aclk),
.rclk(hclk),
.resetn(aresetn),
.data_in(axi_id),
.write_en(id_send_w_en),
.read_en(id_send_r_en),
.data_out(ahb_id),
.full(id_send_fifo_full),
.empty(id_send_fifo_empty)
);
write_fifo write_fifo_mod(
.wclk(aclk),
.rclk(hclk),
.resetn(aresetn),
.data_in(axi_write),
.write_en(state_w_en),
.read_en(state_r_en),
.data_out(ahb_write),
.full(state_fifo_full),
.empty(state_fifo_empty)
);
data_fifo data_fifo_mod(
.wclk(aclk),
.rclk(hclk),
.resetn(aresetn),
.data_in(axi_data),
.write_en(data_w_en),
.read_en(data_r_en),
.data_out(ahb_data),
.full(data_fifo_full),
.empty(data_fifo_empty)
);
addr_fifo addr_fifo_mod(
.wclk(aclk),
.rclk(hclk),
.resetn(aresetn),
.data_in(axi_addr),
.write_en(addr_w_en),
.read_en(addr_r_en),
.data_out(ahb_addr),
.full(addr_fifo_full),
.empty(addr_fifo_empty)
);
endmodule |
module axi2fifo #(
parameter AXI_ID_WIDTH = 8
)(
input aclk,
input aresetn,
//aw channel
input [AXI_ID_WIDTH-1:0] awid,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input awvalid,
output awready,
//w channel
input [63:0] wdata,
input [7:0] wstrb,
input wlast,
input wvalid,
output wready,
//ar channel
input [AXI_ID_WIDTH-1:0] arid,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input arvalid,
output arready,
//addr fifo in
output reg [31:0] axi_addr,
output reg addr_w_en,
input addr_fifo_full,
//data fifo in
output reg [63:0] axi_data,
output reg data_w_en,
input data_fifo_full,
//write fifo in
output reg axi_write,
output reg state_w_en,
input state_fifo_full,
//id_send fifo in
output reg [AXI_ID_WIDTH+1-1:0] axi_id,
output reg id_send_w_en,
input id_send_fifo_full,
//size fifo
output reg [2:0] axi_size,
output reg size_w_en,
input size_fifo_full
);//rlast state set at highest bit of id fifo
parameter
IDLE = 6'b000001,
WRITE = 6'b000010,
WRITE_WRAP = 6'b000100,
READ = 6'b001000,
READ_INCR = 6'b010000,
READ_WRAP = 6'b100000;
//aw channel
reg [AXI_ID_WIDTH-1:0] awid_reg;
reg [31:0] awaddr_reg;
reg [7:0] awlen_reg;
reg [2:0] awsize_reg;
reg [1:0] awburst_reg;
reg awvalid_reg;
//ar channel
reg [AXI_ID_WIDTH-1:0] arid_reg;
reg [31:0] araddr_reg;
reg [7:0] arlen_reg;
reg [2:0] arsize_reg;
reg [1:0] arburst_reg;
reg arvalid_reg;
reg write_finished,read_finished;
reg [7:0] awlen_temp;
reg [7:0] arlen_temp;
reg [31:0] waddr_upper_bound,waddr_lower_bound,raddr_upper_bound,raddr_lower_bound;
reg lower_bound_shift;
reg [5:0] cstate,nstate;
reg single_write_flag;
wire [63:0] data_mask;
wire fifo_access;
assign fifo_access = addr_fifo_full|data_fifo_full|id_send_fifo_full|state_fifo_full|size_fifo_full;
assign data_mask[7:0] = wstrb[0]?8'b1111_1111:8'b0000_0000;
assign data_mask[15:8] = wstrb[1]?8'b1111_1111:8'b0000_0000;
assign data_mask[23:16] = wstrb[2]?8'b1111_1111:8'b0000_0000;
assign data_mask[31:24] = wstrb[3]?8'b1111_1111:8'b0000_0000;
assign data_mask[39:32] = wstrb[4]?8'b1111_1111:8'b0000_0000;
assign data_mask[47:40] = wstrb[5]?8'b1111_1111:8'b0000_0000;
assign data_mask[55:48] = wstrb[6]?8'b1111_1111:8'b0000_0000;
assign data_mask[63:56] = wstrb[7]?8'b1111_1111:8'b0000_0000;
//write control
always@(posedge aclk or negedge aresetn)
if(!aresetn)
write_finished <= 1'b1;
else if(wlast == 1'b1 && fifo_access == 1'b0)
write_finished <= 1'b1;
else if(wvalid == 1'b1)
write_finished <= 1'b0;
else
write_finished <= write_finished;
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
awid_reg <= 'b0;
awaddr_reg <= 32'b0;
awlen_reg <= 8'b0;
awsize_reg <= 3'b0;
awburst_reg <= 2'b0;
end
else if(write_finished == 1'b1)begin
awid_reg <= awid;
awaddr_reg <= awaddr;
awlen_reg <= awlen;
awsize_reg <= awsize;
awburst_reg <= awburst;
end
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
waddr_upper_bound <= 32'b0;
waddr_lower_bound <= 32'b0;
end
else if(awburst == 2'b10 && write_finished == 1'b1)begin
waddr_lower_bound <= (awaddr/((8'd1<<awsize)*(awlen+1'b1)))*(8'd1<<awsize)*(awlen+1'b1);
waddr_upper_bound <= (awaddr/((8'd1<<awsize)*(awlen+1'b1)))*(8'd1<<awsize)*(awlen+1'b1) + (8'd1<<awsize)*(awlen+1'b1);
end
else if(lower_bound_shift == 1'b1 || (write_finished == 1'b0 && (awaddr_reg + awlen_temp*(8'b1<<awsize_reg) >= waddr_upper_bound)))
waddr_lower_bound <= waddr_lower_bound + (8'b1<<awsize_reg);
always@(posedge aclk or negedge aresetn)
if(!aresetn)
awlen_temp <= 8'b0;
else if(wlast == 1'b1 && fifo_access == 1'b0)
awlen_temp <= 8'b0;
//else if(wvalid == 1'b1 && fifo_access == 1'b0)
else if(wvalid && wready && fifo_access == 1'b0)
awlen_temp <= awlen_temp + 1'b1;
else
awlen_temp <= awlen_temp;
assign awready = ~fifo_access && read_finished;
assign wready = ~fifo_access && read_finished;
//read control
always@(posedge aclk or negedge aresetn)
if(!aresetn)
read_finished <= 1'b1;
else if((nstate == READ_INCR || nstate == READ_WRAP) && read_finished == 1'b1 && arlen != 8'b0)
read_finished <= 1'b0;
else if(arlen_reg == arlen_temp && fifo_access == 1'b0)
read_finished <= 1'b1;
else
read_finished <= read_finished;
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
arid_reg <= 'b0;
araddr_reg <= 32'b0;
arlen_reg <= 8'b0;
arsize_reg <= 3'b0;
arburst_reg <= 2'b0;
end
else if(read_finished == 1'b1)begin
arid_reg <= arid;
araddr_reg <= araddr;
arlen_reg <= arlen;
arsize_reg <= arsize;
arburst_reg <= arburst;
end
always@(posedge aclk or negedge aresetn)
if(!aresetn)
arlen_temp <= 8'b0;
else if(/*cstate==WRITE || cstate==WRITE_WRAP || */nstate==WRITE || nstate==WRITE_WRAP)
arlen_temp <= 8'b0;
else if(arlen_reg == arlen_temp && read_finished == 1'b0 && fifo_access == 1'b0)
arlen_temp <= 8'b0;
else if(arvalid == 1'b1 && arlen != arlen_temp && fifo_access == 1'b0 && read_finished == 1'b1)
//else if(arvalid && arready && arlen != arlen_temp && fifo_access == 1'b0 && read_finished == 1'b1)
arlen_temp <= arlen_temp + 1'b1;
else if(arlen_reg != arlen_temp && fifo_access == 1'b0 && read_finished == 1'b0)
arlen_temp <= arlen_temp + 1'b1;
else
arlen_temp <= arlen_temp;
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
raddr_upper_bound <= 32'b0;
raddr_lower_bound <= 32'b0;
end
else if(arburst == 2'b10 && read_finished == 1'b1)begin
raddr_lower_bound <= (araddr/((8'd1<<arsize)*(arlen+1'b1)))*(8'd1<<arsize)*(arlen+1'b1);
raddr_upper_bound <= (araddr/((8'd1<<arsize)*(arlen+1'b1)))*(8'd1<<arsize)*(arlen+1'b1) + (8'd1<<arsize)*(arlen+1'b1);
end
else if(lower_bound_shift == 1'b1 || (read_finished == 1'b0 && (araddr_reg + arlen_temp*(8'b1<<arsize_reg) >= raddr_upper_bound)))
raddr_lower_bound <= raddr_lower_bound + (1'b1<<arsize_reg);
assign arready = (write_finished==1'b0 || read_finished == 1'b0 || fifo_access == 1'b1 || (awvalid&awready) || (nstate==WRITE) || (nstate==WRITE_WRAP)) ? 1'b0 : 1'b1;
//state machine
always@(posedge aclk or negedge aresetn)
if(!aresetn)
cstate <= IDLE;
else
cstate <= nstate;
always@(*)
case(cstate)
IDLE:begin
if(awvalid == 1'b1 && (awburst == 2'b0 || awburst == 2'b1))
nstate = WRITE;
else if(awvalid == 1'b1 && awburst == 2'b10)
nstate = WRITE_WRAP;
else if(arvalid == 1'b1 && arburst == 2'b0)
nstate = READ;
else if(arvalid == 1'b1 && arburst == 2'b1)
nstate = READ_INCR;
else if(arvalid == 1'b1 && arburst == 2'b10)
nstate = READ_WRAP;
else
nstate = IDLE;
end
WRITE:begin
if(arvalid == 1'b0 && awvalid == 1'b0 && write_finished == 1'b1 && single_write_flag == 1'b1)
nstate = IDLE;
else if(awvalid == 1'b1 && awburst == 2'b10 && write_finished == 1'b1 && single_write_flag == 1'b1)
nstate = WRITE_WRAP;
else if(arvalid == 1'b1 && arburst == 2'b0 && write_finished == 1'b1 && single_write_flag == 1'b1)
nstate = READ;
else if(arvalid == 1'b1 && arburst == 2'b1 && write_finished == 1'b1 && single_write_flag == 1'b1)
nstate = READ_INCR;
else if(arvalid == 1'b1 && arburst == 2'b10 && write_finished == 1'b1 && single_write_flag == 1'b1)
nstate = READ_WRAP;
else
nstate = WRITE;
end
WRITE_WRAP:begin
if(arvalid == 1'b0 && awvalid == 1'b0 && write_finished == 1'b1)
nstate = IDLE;
else if(awvalid == 1'b1 && (awburst == 2'b0 || awburst == 2'b1) && write_finished == 1'b1)
nstate = WRITE;
else if(arvalid == 1'b1 && arburst == 2'b0 && write_finished == 1'b1)
nstate = READ;
else if(arvalid == 1'b1 && arburst == 2'b1 && write_finished == 1'b1)
nstate = READ_INCR;
else if(arvalid == 1'b1 && arburst == 2'b10 && write_finished == 1'b1)
nstate = READ_WRAP;
else
nstate = WRITE_WRAP;
end
READ:begin
if(arvalid == 1'b0 && awvalid == 1'b0 && read_finished == 1'b1)
nstate = IDLE;
else if(awvalid == 1'b1 && (awburst == 2'b0 || awburst == 2'b1) && read_finished == 1'b1)
nstate = WRITE;
else if(awvalid == 1'b1 && awburst == 2'b10 && read_finished == 1'b1)
nstate = WRITE_WRAP;
else if(arvalid == 1'b1 && arburst == 2'b1 && read_finished == 1'b1)
nstate = READ_INCR;
else if(arvalid == 1'b1 && arburst == 2'b10 && read_finished == 1'b1)
nstate = READ_WRAP;
else
nstate = READ;
end
READ_INCR:begin
if(arvalid == 1'b0 && awvalid == 1'b0 && read_finished == 1'b1)
nstate = IDLE;
else if(awvalid == 1'b1 && (awburst == 2'b0 || awburst == 2'b1) && read_finished == 1'b1)
nstate = WRITE;
else if(awvalid == 1'b1 && awburst == 2'b10 && read_finished == 1'b1)
nstate = WRITE_WRAP;
else if(arvalid == 1'b1 && arburst == 2'b0 && read_finished == 1'b1)
nstate = READ;
else if(arvalid == 1'b1 && arburst == 2'b10 && read_finished == 1'b1)
nstate = READ_WRAP;
else
nstate = READ_INCR;
end
READ_WRAP:begin
if(arvalid == 1'b0 && awvalid == 1'b0 && read_finished == 1'b1)
nstate = IDLE;
else if(awvalid == 1'b1 && (awburst == 2'b0 || awburst == 2'b1) && read_finished == 1'b1)
nstate = WRITE;
else if(awvalid == 1'b1 && awburst == 2'b10 && read_finished == 1'b1)
nstate = WRITE_WRAP;
else if(arvalid == 1'b1 && arburst == 2'b0 && read_finished == 1'b1)
nstate = READ;
else if(arvalid == 1'b1 && arburst == 2'b1 && read_finished == 1'b1)
nstate = READ_INCR;
else
nstate = READ_WRAP;
end
endcase
always@(posedge aclk or negedge aresetn)
if(!aresetn)begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b1;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
lower_bound_shift <= 1'b0;
single_write_flag <= 1'b0;
end
else
case(nstate)
IDLE:begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b1;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
lower_bound_shift <= 1'b0;
single_write_flag <= 1'b0;
end
WRITE:begin
lower_bound_shift <= 1'b0;
if(wvalid == 1'b1 && fifo_access == 1'b0 && write_finished == 1'b1)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= awaddr + awlen_temp*(8'b1<<awsize);
axi_data <= wdata&data_mask;
axi_write <= 1'b1;
axi_size <= awsize;
single_write_flag <= 1'b1;
if(wlast == 1'b1)
axi_id <= {1'b1,awid};
else
axi_id <= {1'b0,awid};
end
else if(wvalid == 1'b1 && fifo_access == 1'b0 && write_finished == 1'b0)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= awaddr_reg + awlen_temp*(8'b1<<awsize_reg);
axi_data <= wdata&data_mask;
axi_write <= 1'b1;
axi_size <= awsize_reg;
single_write_flag <= 1'b1;
if(wlast == 1'b1)
axi_id <= {1'b1,awid_reg};
else
axi_id <= {1'b0,awid_reg};
end
else begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b1;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
end
end
WRITE_WRAP:begin
single_write_flag <= 1'b0;
if(write_finished == 1'b1 && (awaddr + (8'b1<<awsize) >= ((awaddr/((8'b1<<awsize)*(awlen+1'b1)))*(8'b1<<awsize)*(awlen+1'b1) + (8'b1<<awsize)*(awlen+1'b1))))
lower_bound_shift <= 1'b1;
else if(write_finished == 1'b0 && (awaddr_reg + awlen_temp*(8'b1<<awsize_reg) >= waddr_upper_bound))
lower_bound_shift <= 1'b1;
else
lower_bound_shift <= 1'b0;
if(wvalid == 1'b1 && fifo_access == 1'b0 && write_finished == 1'b1)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= awaddr + awlen_temp*(8'b1<<awsize);
axi_data <= wdata&data_mask;
axi_write <= 1'b1;
axi_size <= awsize;
if(wlast == 1'b1)
axi_id <= {1'b1,awid};
else
axi_id <= {1'b0,awid};
end
else if(wvalid == 1'b1 && fifo_access == 1'b0 && write_finished == 1'b0 && (awaddr_reg + awlen_temp*(8'b1<<awsize_reg) < waddr_upper_bound))begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= awaddr_reg + awlen_temp*(8'b1<<awsize_reg);
axi_data <= wdata&data_mask;
axi_write <= 1'b1;
axi_size <= awsize_reg;
if(wlast == 1'b1)
axi_id <= {1'b1,awid_reg};
else
axi_id <= {1'b0,awid_reg};
end
else if(wvalid == 1'b1 && fifo_access == 1'b0 && write_finished == 1'b0 && (awaddr_reg + awlen_temp*(8'b1<<awsize_reg) >= waddr_upper_bound))begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= waddr_lower_bound;
axi_data <= wdata&data_mask;
axi_write <= 1'b1;
axi_size <= awsize_reg;
if(wlast == 1'b1)
axi_id <= {1'b1,awid_reg};
else
axi_id <= {1'b0,awid_reg};
end
else begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b1;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
end
end
READ:begin
single_write_flag <= 1'b0;
lower_bound_shift <= 1'b0;
if(arvalid == 1'b1 && fifo_access == 1'b0)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= araddr;
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize;
axi_id <= {1'b1,arid};
end
else begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
end
end
READ_INCR:begin
single_write_flag <= 1'b0;
lower_bound_shift <= 1'b0;
if(arvalid == 1'b1 && fifo_access == 1'b0 && read_finished == 1'b1)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= araddr + arlen_temp*(8'b1<<arsize);
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize;
if(arlen == 8'b0)
axi_id <= {1'b1,arid};
else
axi_id <= {1'b0,arid};
end
else if(fifo_access == 1'b0 && read_finished == 1'b0)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= araddr_reg + arlen_temp*(8'b1<<arsize_reg);
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize_reg;
if(arlen_temp == arlen_reg)
axi_id <= {1'b1,arid_reg};
else
axi_id <= {1'b0,arid_reg};
end
else begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
end
end
READ_WRAP:begin
single_write_flag <= 1'b0;
if(read_finished == 1'b1 && (araddr + (8'b1<<arsize) >= ((araddr/((8'b1<<arsize)*(arlen+1'b1)))*(8'b1<<arsize)*(arlen+1'b1) + (8'b1<<arsize)*(arlen+1'b1))))
lower_bound_shift <= 1'b1;
else if(read_finished == 1'b0 && (araddr_reg + arlen_temp*(8'b1<<arsize_reg) >= raddr_upper_bound))
lower_bound_shift <= 1'b1;
else
lower_bound_shift <= 1'b0;
if(arvalid == 1'b1 && fifo_access == 1'b0 && read_finished == 1'b1)begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= araddr + arlen_temp*(8'b1<<arsize);
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize;
axi_id <= {1'b0,arid};
end
else if(fifo_access == 1'b0 && read_finished == 1'b0 && (araddr_reg + arlen_temp*(8'b1<<arsize_reg) < raddr_upper_bound))begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= araddr_reg + arlen_temp*(8'b1<<arsize_reg);
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize_reg;
if(arlen_temp == arlen_reg)
axi_id <= {1'b1,arid_reg};
else
axi_id <= {1'b0,arid_reg};
end
else if(fifo_access == 1'b0 && read_finished == 1'b0 && (araddr_reg + arlen_temp*(8'b1<<arsize_reg) >= raddr_upper_bound))begin
addr_w_en <= 1'b1;
data_w_en <= 1'b1;
state_w_en <= 1'b1;
id_send_w_en <= 1'b1;
size_w_en <= 1'b1;
axi_addr <= raddr_lower_bound;
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_size <= arsize_reg;
if(arlen_temp == arlen_reg)
axi_id <= {1'b1,arid_reg};
else
axi_id <= {1'b0,arid_reg};
end
else begin
axi_addr <= 31'b0;
axi_data <= 64'b0;
axi_write <= 1'b0;
axi_id <= 'b0;
axi_size <= 3'b0;
addr_w_en <= 1'b0;
data_w_en <= 1'b0;
state_w_en <= 1'b0;
id_send_w_en <= 1'b0;
size_w_en <= 1'b0;
end
end
endcase
endmodule |
module axi2ahb_bridge_top #(
parameter AXI_ID_WIDTH = 8
)(
input aclk,
input aresetn,
input hclk,
input hresetn,
//axi side
//aw channel
input [AXI_ID_WIDTH-1:0] awid,
input [31:0] awaddr,
input [7:0] awlen,
input [2:0] awsize,
input [1:0] awburst,
input awvalid,
output awready,
//w channel
input [63:0] wdata,
input [7:0] wstrb,
input wlast,
input wvalid,
output wready,
//ar channel
input [AXI_ID_WIDTH-1:0] arid,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input arvalid,
output arready,
//b response
output [AXI_ID_WIDTH-1:0] bid,
output [1:0] bresp,
output bvalid,
input bready,
//r response
output [AXI_ID_WIDTH-1:0] rid,
output [63:0] rdata,
output [1:0] rresp,
output rlast,
output rvalid,
input rready,
//ahb_side
//ahb output
output [31:0] haddr,
output [1:0] htrans,
output hwrite,
output [2:0] hsize,
output [2:0] hburst,
output [63:0] hwdata,
output hbusreq,
output hlock,
//ahb input
input [63:0] hrdata,
input hready,
input [1:0] hresp,
input hgrant,
input [3:0] hmaster
);
wire [31:0] axi_addr;
wire addr_w_en;
wire addr_r_en;
wire [31:0] ahb_addr;
wire addr_fifo_full;
wire addr_fifo_empty;
//data_fifo
wire [63:0] axi_data;
wire data_w_en;
wire data_r_en;
wire [63:0] ahb_data;
wire data_fifo_full;
wire data_fifo_empty;
// write or read state fifo (1 write 0 read)
wire axi_write;
wire state_w_en;
wire state_r_en;
wire ahb_write;
wire state_fifo_full;
wire state_fifo_empty;
//id_send_fifo
wire [AXI_ID_WIDTH+1-1:0] axi_id;
wire id_send_w_en;
wire id_send_r_en;
wire [AXI_ID_WIDTH+1-1:0] ahb_id;
wire id_send_fifo_full;
wire id_send_fifo_empty;
//size_fifo
wire [2:0] axi_size;
wire size_w_en;
wire size_r_en;
wire [2:0] ahb_size;
wire size_fifo_full;
wire size_fifo_empty;
//rdata_fifo
wire [63:0] ahb_rdata;
wire rdata_w_en;
wire rdata_r_en;
wire [63:0] axi_rdata;
wire rdata_fifo_full;
wire rdata_fifo_empty;
//resp_fifo
wire [1:0] ahb_resp;
wire resp_w_en;
wire resp_r_en;
wire [1:0] axi_resp;
wire resp_fifo_full;
wire resp_fifo_empty;
//id_resp
wire [AXI_ID_WIDTH+2-1:0] ahb_id_resp;
wire id_resp_w_en;
wire id_resp_r_en;
wire [AXI_ID_WIDTH+2-1:0] axi_id_resp;
wire id_resp_fifo_full;
wire id_resp_fifo_empty;
axi_controller
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) axi_mod
(
.aclk(aclk),
.aresetn(aresetn),
.awid(awid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awvalid(awvalid),
.awready(awready),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.wvalid(wvalid),
.wready(wready),
.arid(arid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arvalid(arvalid),
.arready(arready),
.axi_addr(axi_addr),
.addr_w_en(addr_w_en),
.addr_fifo_full(addr_fifo_full),
.axi_data(axi_data),
.data_w_en(data_w_en),
.data_fifo_full(data_fifo_full),
.axi_write(axi_write),
.state_w_en(state_w_en),
.state_fifo_full(state_fifo_full),
.axi_id(axi_id),
.id_send_w_en(id_send_w_en),
.id_send_fifo_full(id_send_fifo_full),
.axi_size(axi_size),
.size_w_en(size_w_en),
.size_fifo_full(size_fifo_full),
.rdata_r_en(rdata_r_en),
.axi_rdata(axi_rdata),
.rdata_fifo_empty(rdata_fifo_empty),
.resp_r_en(resp_r_en),
.axi_resp(axi_resp),
.resp_fifo_empty(resp_fifo_empty),
.id_resp_r_en(id_resp_r_en),
.axi_id_resp(axi_id_resp),
.id_resp_fifo_empty(id_resp_fifo_empty),
.bid(bid),
.bresp(bresp),
.bvalid(bvalid),
.bready(bready),
.rid(rid),
.rdata(rdata),
.rresp(rresp),
.rlast(rlast),
.rvalid(rvalid),
.rready(rready)
);
fifo_wrapper
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) fifo_mod
(
.aclk(aclk),
.aresetn(aresetn),
.hclk(hclk),
.hresetn(hresetn),
.axi_addr(axi_addr),
.addr_w_en(addr_w_en),
.addr_r_en(addr_r_en),
.ahb_addr(ahb_addr),
.addr_fifo_full(addr_fifo_full),
.addr_fifo_empty(addr_fifo_empty),
.axi_data(axi_data),
.data_w_en(data_w_en),
.data_r_en(data_r_en),
.ahb_data(ahb_data),
.data_fifo_full(data_fifo_full),
.data_fifo_empty(data_fifo_empty),
.axi_write(axi_write),
.state_w_en(state_w_en),
.state_r_en(state_r_en),
.ahb_write(ahb_write),
.state_fifo_full(state_fifo_full),
.state_fifo_empty(state_fifo_empty),
.axi_id(axi_id),
.id_send_w_en(id_send_w_en),
.id_send_r_en(id_send_r_en),
.ahb_id(ahb_id),
.id_send_fifo_full(id_send_fifo_full),
.id_send_fifo_empty(id_send_fifo_empty),
.axi_size(axi_size),
.size_w_en(size_w_en),
.size_r_en(size_r_en),
.ahb_size(ahb_size),
.size_fifo_full(size_fifo_full),
.size_fifo_empty(size_fifo_empty),
.ahb_rdata(ahb_rdata),
.rdata_w_en(rdata_w_en),
.rdata_r_en(rdata_r_en),
.axi_rdata(axi_rdata),
.rdata_fifo_full(rdata_fifo_full),
.rdata_fifo_empty(rdata_fifo_empty),
.ahb_resp(ahb_resp),
.resp_w_en(resp_w_en),
.resp_r_en(resp_r_en),
.axi_resp(axi_resp),
.resp_fifo_full(resp_fifo_full),
.resp_fifo_empty(resp_fifo_empty),
.ahb_id_resp(ahb_id_resp),
.id_resp_w_en(id_resp_w_en),
.id_resp_r_en(id_resp_r_en),
.axi_id_resp(axi_id_resp),
.id_resp_fifo_full(id_resp_fifo_full),
.id_resp_fifo_empty(id_resp_fifo_empty)
);
ahb_controller
#(
.AXI_ID_WIDTH(AXI_ID_WIDTH)
) ahb_mod
(
.hclk(hclk),
.hresetn(hresetn),
.haddr(haddr),
.htrans(htrans),
.hwrite(hwrite),
.hsize(hsize),
.hburst(hburst),
.hwdata(hwdata),
.hbusreq(hbusreq),
.hlock(hlock),
.hrdata(hrdata),
.hready(hready),
.hresp(hresp),
.hgrant(hgrant),
.hmaster(hmaster),
.addr_r_en(addr_r_en),
.ahb_addr(ahb_addr),
.addr_fifo_empty(addr_fifo_empty),
.data_r_en(data_r_en),
.ahb_data(ahb_data),
.data_fifo_empty(data_fifo_empty),
.state_r_en(state_r_en),
.ahb_write(ahb_write),
.state_fifo_empty(state_fifo_empty),
.id_send_r_en(id_send_r_en),
.ahb_id(ahb_id),
.id_send_fifo_empty(id_send_fifo_empty),
.size_r_en(size_r_en),
.ahb_size(ahb_size),
.size_fifo_empty(size_fifo_empty),
.rdata_w_en(rdata_w_en),
.ahb_rdata(ahb_rdata),
.rdata_fifo_full(rdata_fifo_full),
.rdata_fifo_empty(rdata_fifo_empty),
.resp_w_en(resp_w_en),
.ahb_resp(ahb_resp),
.resp_fifo_full(resp_fifo_full),
.id_resp_w_en(id_resp_w_en),
.ahb_id_resp(ahb_id_resp),
.id_resp_fifo_full(id_resp_fifo_full)
);
endmodule |
module NV_NVDLA_CMAC_CORE_rt_out (
nvdla_core_clk
,nvdla_wg_clk
,nvdla_core_rstn
,cfg_is_wg
,cfg_reg_en
//: for(my $i=0; $i<32/2; $i++){
//: print qq(
//: ,out_data${i} )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,out_data0
,out_data1
,out_data2
,out_data3
,out_data4
,out_data5
,out_data6
,out_data7
,out_data8
,out_data9
,out_data10
,out_data11
,out_data12
,out_data13
,out_data14
,out_data15
//| eperl: generated_end (DO NOT EDIT ABOVE)
,out_mask
,out_pd
,out_pvld
,dp2reg_done
//: for(my $i=0; $i<32/2; $i++){
//: print qq(
//: ,mac2accu_data${i} )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac2accu_data0
,mac2accu_data1
,mac2accu_data2
,mac2accu_data3
,mac2accu_data4
,mac2accu_data5
,mac2accu_data6
,mac2accu_data7
,mac2accu_data8
,mac2accu_data9
,mac2accu_data10
,mac2accu_data11
,mac2accu_data12
,mac2accu_data13
,mac2accu_data14
,mac2accu_data15
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac2accu_mask
,mac2accu_pd
,mac2accu_pvld
);
input nvdla_core_clk;
input nvdla_wg_clk;
input nvdla_core_rstn;
input cfg_is_wg;
input cfg_reg_en;
//: for(my $i=0; $i<32/2; $i++){
//: print qq(
//: input[22 -1:0] out_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input[22 -1:0] out_data0;
input[22 -1:0] out_data1;
input[22 -1:0] out_data2;
input[22 -1:0] out_data3;
input[22 -1:0] out_data4;
input[22 -1:0] out_data5;
input[22 -1:0] out_data6;
input[22 -1:0] out_data7;
input[22 -1:0] out_data8;
input[22 -1:0] out_data9;
input[22 -1:0] out_data10;
input[22 -1:0] out_data11;
input[22 -1:0] out_data12;
input[22 -1:0] out_data13;
input[22 -1:0] out_data14;
input[22 -1:0] out_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [32/2 -1:0] out_mask;
input [8:0] out_pd;
input out_pvld;
output dp2reg_done;
//: for(my $i=0; $i<32/2; $i++){
//: print qq(
//: output[22 -1:0] mac2accu_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
output[22 -1:0] mac2accu_data0;
output[22 -1:0] mac2accu_data1;
output[22 -1:0] mac2accu_data2;
output[22 -1:0] mac2accu_data3;
output[22 -1:0] mac2accu_data4;
output[22 -1:0] mac2accu_data5;
output[22 -1:0] mac2accu_data6;
output[22 -1:0] mac2accu_data7;
output[22 -1:0] mac2accu_data8;
output[22 -1:0] mac2accu_data9;
output[22 -1:0] mac2accu_data10;
output[22 -1:0] mac2accu_data11;
output[22 -1:0] mac2accu_data12;
output[22 -1:0] mac2accu_data13;
output[22 -1:0] mac2accu_data14;
output[22 -1:0] mac2accu_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output [32/2 -1:0] mac2accu_mask;
output [8:0] mac2accu_pd;
output mac2accu_pvld;
wire [32/2 -1:0] mac2accu_mask;
wire [8:0] mac2accu_pd;
wire mac2accu_pvld;
wire out_layer_done;
wire out_rt_done_d0;
//==========================================================
// Config logic
//==========================================================
//: &eperl::flop(" -q \"cfg_reg_en_d1\" -d \"cfg_reg_en\" -clk nvdla_core_clk -rst nvdla_core_rstn ");
//: &eperl::flop(" -q \"cfg_is_wg_d1\" -en \"cfg_reg_en\" -d \"cfg_is_wg\" -clk nvdla_core_clk -rst nvdla_core_rstn ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
reg cfg_reg_en_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cfg_reg_en_d1 <= 'b0;
end else begin
cfg_reg_en_d1 <= cfg_reg_en;
end
end
reg cfg_is_wg_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cfg_is_wg_d1 <= 'b0;
end else begin
if ((cfg_reg_en) == 1'b1) begin
cfg_is_wg_d1 <= cfg_is_wg;
// VCS coverage off
end else if ((cfg_reg_en) == 1'b0) begin
// VCS coverage on
end
end
end
//| eperl: generated_end (DO NOT EDIT ABOVE)
//==========================================================
// Output retiming
//==========================================================
assign out_layer_done = out_pd[8] &
out_pd[6] &
out_pvld;
//: my $kk = 32/2;
//: my $jj = 22;
//: print "wire out_rt_pvld_d0 = out_pvld;\n";
//: print "wire [$kk-1:0] out_rt_mask_d0 = out_mask;\n";
//: print "wire [8:0] out_rt_pd_d0 = out_pd;\n";
//: for(my $k = 0; $k < $kk; $k ++) {
//: print "wire [${jj}-1:0] out_rt_data${k}_d0 = out_data${k};\n";
//: }
//: my $latency = 2;
//: my $kk = 32/2;
//: my $res_width = 22;
//: for(my $i = 0; $i < $latency; $i ++) {
//: my $j = $i + 1;
//: &eperl::flop(" -q out_rt_pvld_d${j} -d \"out_rt_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn ");
//: &eperl::flop(" -q out_rt_mask_d${j} -d \"out_rt_mask_d${i}\" -wid $kk -clk nvdla_core_clk -rst nvdla_core_rstn ");
//: &eperl::flop("-wid 9 -q out_rt_pd_d${j} -en \"out_rt_pvld_d${i}\" -d \"out_rt_pd_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn");
//: for(my $k = 0; $k < $kk; $k ++) {
//: &eperl::flop("-norst -wid $res_width -q out_rt_data${k}_d${j} -en \"out_rt_mask_d${i}[${k}]\" -d \"out_rt_data${k}_d${i}\" -clk nvdla_core_clk");
//: }
//: }
//:
//: my $i = $latency;
//: print "assign mac2accu_pvld = out_rt_pvld_d${i};\n";
//: print "assign mac2accu_mask = out_rt_mask_d${i};\n";
//: print "assign mac2accu_pd = out_rt_pd_d${i};\n";
//: my $kk = 32/2;
//: for(my $k = 0; $k < $kk; $k ++) {
//: print "assign mac2accu_data${k} = out_rt_data${k}_d${i};\n";
//: }
//:
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire out_rt_pvld_d0 = out_pvld;
wire [16-1:0] out_rt_mask_d0 = out_mask;
wire [8:0] out_rt_pd_d0 = out_pd;
wire [22-1:0] out_rt_data0_d0 = out_data0;
wire [22-1:0] out_rt_data1_d0 = out_data1;
wire [22-1:0] out_rt_data2_d0 = out_data2;
wire [22-1:0] out_rt_data3_d0 = out_data3;
wire [22-1:0] out_rt_data4_d0 = out_data4;
wire [22-1:0] out_rt_data5_d0 = out_data5;
wire [22-1:0] out_rt_data6_d0 = out_data6;
wire [22-1:0] out_rt_data7_d0 = out_data7;
wire [22-1:0] out_rt_data8_d0 = out_data8;
wire [22-1:0] out_rt_data9_d0 = out_data9;
wire [22-1:0] out_rt_data10_d0 = out_data10;
wire [22-1:0] out_rt_data11_d0 = out_data11;
wire [22-1:0] out_rt_data12_d0 = out_data12;
wire [22-1:0] out_rt_data13_d0 = out_data13;
wire [22-1:0] out_rt_data14_d0 = out_data14;
wire [22-1:0] out_rt_data15_d0 = out_data15;
reg out_rt_pvld_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_pvld_d1 <= 'b0;
end else begin
out_rt_pvld_d1 <= out_rt_pvld_d0;
end
end
reg [15:0] out_rt_mask_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_mask_d1 <= 'b0;
end else begin
out_rt_mask_d1 <= out_rt_mask_d0;
end
end
reg [8:0] out_rt_pd_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_pd_d1 <= 'b0;
end else begin
if ((out_rt_pvld_d0) == 1'b1) begin
out_rt_pd_d1 <= out_rt_pd_d0;
// VCS coverage off
end else if ((out_rt_pvld_d0) == 1'b0) begin
// VCS coverage on
end
end
end
reg [21:0] out_rt_data0_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[0]) == 1'b1) begin
out_rt_data0_d1 <= out_rt_data0_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[0]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data1_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[1]) == 1'b1) begin
out_rt_data1_d1 <= out_rt_data1_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[1]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data2_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[2]) == 1'b1) begin
out_rt_data2_d1 <= out_rt_data2_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[2]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data3_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[3]) == 1'b1) begin
out_rt_data3_d1 <= out_rt_data3_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[3]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data4_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[4]) == 1'b1) begin
out_rt_data4_d1 <= out_rt_data4_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[4]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data5_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[5]) == 1'b1) begin
out_rt_data5_d1 <= out_rt_data5_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[5]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data6_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[6]) == 1'b1) begin
out_rt_data6_d1 <= out_rt_data6_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[6]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data7_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[7]) == 1'b1) begin
out_rt_data7_d1 <= out_rt_data7_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[7]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data8_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[8]) == 1'b1) begin
out_rt_data8_d1 <= out_rt_data8_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[8]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data9_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[9]) == 1'b1) begin
out_rt_data9_d1 <= out_rt_data9_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[9]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data10_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[10]) == 1'b1) begin
out_rt_data10_d1 <= out_rt_data10_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[10]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data11_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[11]) == 1'b1) begin
out_rt_data11_d1 <= out_rt_data11_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[11]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data12_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[12]) == 1'b1) begin
out_rt_data12_d1 <= out_rt_data12_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[12]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data13_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[13]) == 1'b1) begin
out_rt_data13_d1 <= out_rt_data13_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[13]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data14_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[14]) == 1'b1) begin
out_rt_data14_d1 <= out_rt_data14_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[14]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data15_d1;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d0[15]) == 1'b1) begin
out_rt_data15_d1 <= out_rt_data15_d0;
// VCS coverage off
end else if ((out_rt_mask_d0[15]) == 1'b0) begin
// VCS coverage on
end
end
reg out_rt_pvld_d2;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_pvld_d2 <= 'b0;
end else begin
out_rt_pvld_d2 <= out_rt_pvld_d1;
end
end
reg [15:0] out_rt_mask_d2;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_mask_d2 <= 'b0;
end else begin
out_rt_mask_d2 <= out_rt_mask_d1;
end
end
reg [8:0] out_rt_pd_d2;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_pd_d2 <= 'b0;
end else begin
if ((out_rt_pvld_d1) == 1'b1) begin
out_rt_pd_d2 <= out_rt_pd_d1;
// VCS coverage off
end else if ((out_rt_pvld_d1) == 1'b0) begin
// VCS coverage on
end
end
end
reg [21:0] out_rt_data0_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[0]) == 1'b1) begin
out_rt_data0_d2 <= out_rt_data0_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[0]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data1_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[1]) == 1'b1) begin
out_rt_data1_d2 <= out_rt_data1_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[1]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data2_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[2]) == 1'b1) begin
out_rt_data2_d2 <= out_rt_data2_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[2]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data3_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[3]) == 1'b1) begin
out_rt_data3_d2 <= out_rt_data3_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[3]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data4_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[4]) == 1'b1) begin
out_rt_data4_d2 <= out_rt_data4_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[4]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data5_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[5]) == 1'b1) begin
out_rt_data5_d2 <= out_rt_data5_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[5]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data6_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[6]) == 1'b1) begin
out_rt_data6_d2 <= out_rt_data6_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[6]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data7_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[7]) == 1'b1) begin
out_rt_data7_d2 <= out_rt_data7_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[7]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data8_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[8]) == 1'b1) begin
out_rt_data8_d2 <= out_rt_data8_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[8]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data9_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[9]) == 1'b1) begin
out_rt_data9_d2 <= out_rt_data9_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[9]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data10_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[10]) == 1'b1) begin
out_rt_data10_d2 <= out_rt_data10_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[10]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data11_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[11]) == 1'b1) begin
out_rt_data11_d2 <= out_rt_data11_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[11]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data12_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[12]) == 1'b1) begin
out_rt_data12_d2 <= out_rt_data12_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[12]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data13_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[13]) == 1'b1) begin
out_rt_data13_d2 <= out_rt_data13_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[13]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data14_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[14]) == 1'b1) begin
out_rt_data14_d2 <= out_rt_data14_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[14]) == 1'b0) begin
// VCS coverage on
end
end
reg [21:0] out_rt_data15_d2;
always @(posedge nvdla_core_clk) begin
if ((out_rt_mask_d1[15]) == 1'b1) begin
out_rt_data15_d2 <= out_rt_data15_d1;
// VCS coverage off
end else if ((out_rt_mask_d1[15]) == 1'b0) begin
// VCS coverage on
end
end
assign mac2accu_pvld = out_rt_pvld_d2;
assign mac2accu_mask = out_rt_mask_d2;
assign mac2accu_pd = out_rt_pd_d2;
assign mac2accu_data0 = out_rt_data0_d2;
assign mac2accu_data1 = out_rt_data1_d2;
assign mac2accu_data2 = out_rt_data2_d2;
assign mac2accu_data3 = out_rt_data3_d2;
assign mac2accu_data4 = out_rt_data4_d2;
assign mac2accu_data5 = out_rt_data5_d2;
assign mac2accu_data6 = out_rt_data6_d2;
assign mac2accu_data7 = out_rt_data7_d2;
assign mac2accu_data8 = out_rt_data8_d2;
assign mac2accu_data9 = out_rt_data9_d2;
assign mac2accu_data10 = out_rt_data10_d2;
assign mac2accu_data11 = out_rt_data11_d2;
assign mac2accu_data12 = out_rt_data12_d2;
assign mac2accu_data13 = out_rt_data13_d2;
assign mac2accu_data14 = out_rt_data14_d2;
assign mac2accu_data15 = out_rt_data15_d2;
//| eperl: generated_end (DO NOT EDIT ABOVE)
// get layer done signal
assign out_rt_done_d0 = out_layer_done;
//: my $latency = 2 + 1;
//: for(my $i = 0; $i < $latency; $i ++) {
//: my $j = $i + 1;
//: &eperl::flop(" -q out_rt_done_d${j} -d \"out_rt_done_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn ");
//: };
//: my $h = $latency;
//: print "assign dp2reg_done = out_rt_done_d${h};\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
reg out_rt_done_d1;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_done_d1 <= 'b0;
end else begin
out_rt_done_d1 <= out_rt_done_d0;
end
end
reg out_rt_done_d2;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_done_d2 <= 'b0;
end else begin
out_rt_done_d2 <= out_rt_done_d1;
end
end
reg out_rt_done_d3;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_rt_done_d3 <= 'b0;
end else begin
out_rt_done_d3 <= out_rt_done_d2;
end
end
assign dp2reg_done = out_rt_done_d3;
//| eperl: generated_end (DO NOT EDIT ABOVE)
endmodule |
module NV_NVDLA_SDP_nrdma (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,nrdma_disable //|< i
,nrdma_slcg_op_en //|< i
,sdp_n2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2cvif_rd_req_pd //|> o
,sdp_n2cvif_rd_req_valid //|> o
,sdp_n2cvif_rd_req_ready //|< i
,cvif2sdp_n_rd_rsp_pd //|< i
,cvif2sdp_n_rd_rsp_valid //|< i
,cvif2sdp_n_rd_rsp_ready //|> o
,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2mcif_rd_req_pd //|> o
,sdp_n2mcif_rd_req_valid //|> o
,sdp_n2mcif_rd_req_ready //|< i
,mcif2sdp_n_rd_rsp_pd //|< i
,mcif2sdp_n_rd_rsp_valid //|< i
,mcif2sdp_n_rd_rsp_ready //|> o
,reg2dp_bn_base_addr_high //|< i
,reg2dp_bn_base_addr_low //|< i
,reg2dp_bn_line_stride //|< i
,reg2dp_bn_surface_stride //|< i
,reg2dp_nrdma_data_mode //|< i
,reg2dp_nrdma_data_size //|< i
,reg2dp_nrdma_data_use //|< i
,reg2dp_nrdma_ram_type //|< i
,reg2dp_batch_number //|< i
,reg2dp_channel //|< i
,reg2dp_height //|< i
,reg2dp_width //|< i
,reg2dp_op_en //|< i
,reg2dp_out_precision //|< i
,reg2dp_perf_dma_en //|< i
,reg2dp_proc_precision //|< i
,reg2dp_winograd //|< i
,dp2reg_nrdma_stall //|> o
,dp2reg_done //|> o
,sdp_nrdma2dp_alu_ready //|< i
,sdp_nrdma2dp_mul_ready //|< i
,sdp_nrdma2dp_alu_pd //|> o
,sdp_nrdma2dp_alu_valid //|> o
,sdp_nrdma2dp_mul_pd //|> o
,sdp_nrdma2dp_mul_valid //|> o
);
//
// NV_NVDLA_SDP_nrdma_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
output sdp_n2cvif_rd_req_valid;
input sdp_n2cvif_rd_req_ready;
output [79 -1:0] sdp_n2cvif_rd_req_pd;
input cvif2sdp_n_rd_rsp_valid;
output cvif2sdp_n_rd_rsp_ready;
input [257 -1:0] cvif2sdp_n_rd_rsp_pd;
output sdp_n2cvif_rd_cdt_lat_fifo_pop;
output sdp_n2mcif_rd_req_valid;
input sdp_n2mcif_rd_req_ready;
output [79 -1:0] sdp_n2mcif_rd_req_pd;
input mcif2sdp_n_rd_rsp_valid;
output mcif2sdp_n_rd_rsp_ready;
input [257 -1:0] mcif2sdp_n_rd_rsp_pd;
output sdp_n2mcif_rd_cdt_lat_fifo_pop;
output sdp_nrdma2dp_alu_valid;
input sdp_nrdma2dp_alu_ready;
output [32*16:0] sdp_nrdma2dp_alu_pd;
output sdp_nrdma2dp_mul_valid;
input sdp_nrdma2dp_mul_ready;
output [32*16:0] sdp_nrdma2dp_mul_pd;
input reg2dp_nrdma_data_mode;
input reg2dp_nrdma_data_size;
input [1:0] reg2dp_nrdma_data_use;
input reg2dp_nrdma_ram_type;
input [31:0] reg2dp_bn_base_addr_high;
input [31-5:0] reg2dp_bn_base_addr_low;
input [31-5:0] reg2dp_bn_line_stride;
input [31-5:0] reg2dp_bn_surface_stride;
input [4:0] reg2dp_batch_number;
input [12:0] reg2dp_channel;
input [12:0] reg2dp_height;
input reg2dp_op_en;
input [1:0] reg2dp_out_precision;
input reg2dp_perf_dma_en;
input [1:0] reg2dp_proc_precision;
input [12:0] reg2dp_width;
input reg2dp_winograd;
output [31:0] dp2reg_nrdma_stall;
output dp2reg_done;
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
input nrdma_slcg_op_en;
input nrdma_disable;
wire nvdla_gated_clk;
wire op_load;
wire eg_done;
reg layer_process;
wire [15:0] ig2cq_pd;
wire ig2cq_prdy;
wire ig2cq_pvld;
wire [15:0] cq2eg_pd;
wire cq2eg_prdy;
wire cq2eg_pvld;
wire dma_rd_cdt_lat_fifo_pop;
wire [79 -1:0] dma_rd_req_pd;
wire dma_rd_req_rdy;
wire dma_rd_req_vld;
wire [257 -1:0] dma_rd_rsp_pd;
wire dma_rd_rsp_rdy;
wire dma_rd_rsp_vld;
wire [257 -1:0] lat_fifo_rd_pd;
wire lat_fifo_rd_pvld;
wire lat_fifo_rd_prdy;
// Layer Switch
assign op_load = reg2dp_op_en & !layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
layer_process <= 1'b0;
end else begin
if (op_load) begin
layer_process <= 1'b1;
end else if (eg_done) begin
layer_process <= 1'b0;
end
end
end
assign dp2reg_done = eg_done;
//=======================================
NV_NVDLA_SDP_NRDMA_gate u_gate (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.nrdma_disable (nrdma_disable) //|< i
,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_gated_clk (nvdla_gated_clk) //|> w
);
NV_NVDLA_SDP_RDMA_ig u_ig (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.op_load (op_load) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|> w
,.ig2cq_prdy (ig2cq_prdy) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|> w
,.dma_rd_req_vld (dma_rd_req_vld) //|> w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w
,.reg2dp_op_en (reg2dp_op_en) //|< i
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i
,.reg2dp_winograd (reg2dp_winograd) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i
,.reg2dp_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< i
,.reg2dp_base_addr_low (reg2dp_bn_base_addr_low[31-5:0]) //|< i
,.reg2dp_line_stride (reg2dp_bn_line_stride[31-5:0]) //|< i
,.reg2dp_surface_stride (reg2dp_bn_surface_stride[31-5:0]) //|< i
,.dp2reg_rdma_stall (dp2reg_nrdma_stall[31:0]) //|> o
);
//: my $depth = 256;
//: my $width = 16;
//: print "NV_NVDLA_SDP_NRDMA_cq_${depth}x${width} u_cq ( \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_NRDMA_cq_256x16 u_cq (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.ig2cq_prdy (ig2cq_prdy) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|> w
);
NV_NVDLA_SDP_RDMA_eg u_eg (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.op_load (op_load) //|< w
,.eg_done (eg_done) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|> w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w
,.lat_fifo_rd_pd (lat_fifo_rd_pd[257 -1:0]) //|< w
,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w
,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w
,.sdp_rdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i
,.sdp_rdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i
,.sdp_rdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_rdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o
,.sdp_rdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[32*16:0]) //|> o
,.sdp_rdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i
);
//: my $depth = 256;
//: my $width = 257;
//: print "NV_NVDLA_SDP_NRDMA_lat_fifo_${depth}x${width} u_lat_fifo (\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_NRDMA_lat_fifo_256x257 u_lat_fifo (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
,.lat_wr_prdy (dma_rd_rsp_rdy)
,.lat_wr_pvld (dma_rd_rsp_vld)
,.lat_wr_pd (dma_rd_rsp_pd[257 -1:0])
,.lat_rd_prdy (lat_fifo_rd_prdy)
,.lat_rd_pvld (lat_fifo_rd_pvld)
,.lat_rd_pd (lat_fifo_rd_pd[257 -1:0])
);
NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif (
.nvdla_core_clk (nvdla_gated_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2cvif_rd_req_pd (sdp_n2cvif_rd_req_pd[79 -1:0]) //|> o
,.sdp2cvif_rd_req_valid (sdp_n2cvif_rd_req_valid) //|> o
,.sdp2cvif_rd_req_ready (sdp_n2cvif_rd_req_ready) //|< i
,.cvif2sdp_rd_rsp_pd (cvif2sdp_n_rd_rsp_pd[257 -1:0]) //|< i
,.cvif2sdp_rd_rsp_valid (cvif2sdp_n_rd_rsp_valid) //|< i
,.cvif2sdp_rd_rsp_ready (cvif2sdp_n_rd_rsp_ready) //|> o
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[79 -1:0]) //|> o
,.sdp2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o
,.sdp2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i
,.mcif2sdp_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[257 -1:0]) //|< i
,.mcif2sdp_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i
,.mcif2sdp_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o
,.dma_rd_req_ram_type (reg2dp_nrdma_ram_type) //|< w
,.dma_rd_rsp_ram_type (reg2dp_nrdma_ram_type) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|< w
,.dma_rd_req_vld (dma_rd_req_vld) //|< w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w
,.dma_rd_rsp_pd (dma_rd_rsp_pd[257 -1:0]) //|> w
,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w
,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w
);
endmodule // NV_NVDLA_SDP_nrdma |
module NV_NVDLA_SDP_HLS_Y_cvt_top (
cfg_cvt_bypass //|< i
,cfg_cvt_offset //|< i
,cfg_cvt_scale //|< i
,cfg_cvt_truncate //|< i
,cvt_data_in //|< i
,cvt_in_pvld //|< i
,cvt_out_prdy //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,cvt_data_out //|> o
,cvt_in_prdy //|> o
,cvt_out_pvld //|> o
);
input cfg_cvt_bypass;
input [31:0] cfg_cvt_offset;
input [15:0] cfg_cvt_scale;
input [5:0] cfg_cvt_truncate;
input [16*4 -1:0] cvt_data_in;
input cvt_in_pvld;
input cvt_out_prdy;
output [32*4 -1:0] cvt_data_out;
output cvt_in_prdy;
output cvt_out_pvld;
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $k=4;
//: foreach my $i (0..${k}-1) {
//: print qq(
//: wire [15:0] cvt_data_in_${i};
//: wire [31:0] cvt_data_out_${i};
//: wire cvt_in_prdy_${i};
//: wire cvt_out_pvld_${i};
//: );
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_data_in_${i} = cvt_data_in[16*${i}+15:16*${i}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_data_out[32*${i}+31:32*${i}] = cvt_data_out_${i}; \n";
//: }
//:
//: foreach my $i (0..${k}-1) {
//: print qq(
//: NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_${i} (
//: .cfg_cvt_bypass (cfg_cvt_bypass) //|< i
//: ,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i
//: ,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i
//: ,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i
//: ,.cvt_data_in (cvt_data_in_${i}[15:0]) //|< w
//: ,.cvt_in_pvld (cvt_in_pvld) //|< i
//: ,.cvt_out_prdy (cvt_out_prdy) //|< i
//: ,.nvdla_core_clk (nvdla_core_clk) //|< i
//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: ,.cvt_data_out (cvt_data_out_${i}[31:0]) //|> w
//: ,.cvt_in_prdy (cvt_in_prdy_${i}) //|> w
//: ,.cvt_out_pvld (cvt_out_pvld_${i}) //|> w
//: );
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [15:0] cvt_data_in_0;
wire [31:0] cvt_data_out_0;
wire cvt_in_prdy_0;
wire cvt_out_pvld_0;
wire [15:0] cvt_data_in_1;
wire [31:0] cvt_data_out_1;
wire cvt_in_prdy_1;
wire cvt_out_pvld_1;
wire [15:0] cvt_data_in_2;
wire [31:0] cvt_data_out_2;
wire cvt_in_prdy_2;
wire cvt_out_pvld_2;
wire [15:0] cvt_data_in_3;
wire [31:0] cvt_data_out_3;
wire cvt_in_prdy_3;
wire cvt_out_pvld_3;
assign cvt_data_in_0 = cvt_data_in[16*0+15:16*0];
assign cvt_data_in_1 = cvt_data_in[16*1+15:16*1];
assign cvt_data_in_2 = cvt_data_in[16*2+15:16*2];
assign cvt_data_in_3 = cvt_data_in[16*3+15:16*3];
assign cvt_data_out[32*0+31:32*0] = cvt_data_out_0;
assign cvt_data_out[32*1+31:32*1] = cvt_data_out_1;
assign cvt_data_out[32*2+31:32*2] = cvt_data_out_2;
assign cvt_data_out[32*3+31:32*3] = cvt_data_out_3;
NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_0 (
.cfg_cvt_bypass (cfg_cvt_bypass) //|< i
,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i
,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i
,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i
,.cvt_data_in (cvt_data_in_0[15:0]) //|< w
,.cvt_in_pvld (cvt_in_pvld) //|< i
,.cvt_out_prdy (cvt_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cvt_data_out (cvt_data_out_0[31:0]) //|> w
,.cvt_in_prdy (cvt_in_prdy_0) //|> w
,.cvt_out_pvld (cvt_out_pvld_0) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_1 (
.cfg_cvt_bypass (cfg_cvt_bypass) //|< i
,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i
,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i
,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i
,.cvt_data_in (cvt_data_in_1[15:0]) //|< w
,.cvt_in_pvld (cvt_in_pvld) //|< i
,.cvt_out_prdy (cvt_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cvt_data_out (cvt_data_out_1[31:0]) //|> w
,.cvt_in_prdy (cvt_in_prdy_1) //|> w
,.cvt_out_pvld (cvt_out_pvld_1) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_2 (
.cfg_cvt_bypass (cfg_cvt_bypass) //|< i
,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i
,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i
,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i
,.cvt_data_in (cvt_data_in_2[15:0]) //|< w
,.cvt_in_pvld (cvt_in_pvld) //|< i
,.cvt_out_prdy (cvt_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cvt_data_out (cvt_data_out_2[31:0]) //|> w
,.cvt_in_prdy (cvt_in_prdy_2) //|> w
,.cvt_out_pvld (cvt_out_pvld_2) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_3 (
.cfg_cvt_bypass (cfg_cvt_bypass) //|< i
,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i
,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i
,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i
,.cvt_data_in (cvt_data_in_3[15:0]) //|< w
,.cvt_in_pvld (cvt_in_pvld) //|< i
,.cvt_out_prdy (cvt_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cvt_data_out (cvt_data_out_3[31:0]) //|> w
,.cvt_in_prdy (cvt_in_prdy_3) //|> w
,.cvt_out_pvld (cvt_out_pvld_3) //|> w
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign cvt_in_prdy = cvt_in_prdy_0;
assign cvt_out_pvld = cvt_out_pvld_0;
endmodule // NV_NVDLA_SDP_HLS_Y_cvt_top |
module NV_NVDLA_CDMA_dma_mux (
nvdla_core_clk
,nvdla_core_rstn
,dc_dat2mcif_rd_req_valid
,dc_dat2mcif_rd_req_ready
,dc_dat2mcif_rd_req_pd
,dc_dat2cvif_rd_req_valid
,dc_dat2cvif_rd_req_ready
,dc_dat2cvif_rd_req_pd
,img_dat2cvif_rd_req_valid
,img_dat2cvif_rd_req_ready
,img_dat2cvif_rd_req_pd
,cdma_dat2cvif_rd_req_valid
,cdma_dat2cvif_rd_req_ready
,cdma_dat2cvif_rd_req_pd
,cvif2cdma_dat_rd_rsp_valid
,cvif2cdma_dat_rd_rsp_ready
,cvif2cdma_dat_rd_rsp_pd
,cvif2dc_dat_rd_rsp_valid
,cvif2dc_dat_rd_rsp_ready
,cvif2dc_dat_rd_rsp_pd
,cvif2img_dat_rd_rsp_valid
,cvif2img_dat_rd_rsp_ready
,cvif2img_dat_rd_rsp_pd
,img_dat2mcif_rd_req_valid
,img_dat2mcif_rd_req_ready
,img_dat2mcif_rd_req_pd
,cdma_dat2mcif_rd_req_valid
,cdma_dat2mcif_rd_req_ready
,cdma_dat2mcif_rd_req_pd
,mcif2cdma_dat_rd_rsp_valid
,mcif2cdma_dat_rd_rsp_ready
,mcif2cdma_dat_rd_rsp_pd
,mcif2dc_dat_rd_rsp_valid
,mcif2dc_dat_rd_rsp_ready
,mcif2dc_dat_rd_rsp_pd
,mcif2img_dat_rd_rsp_valid
,mcif2img_dat_rd_rsp_ready
,mcif2img_dat_rd_rsp_pd
);
////////////////////////////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
input dc_dat2cvif_rd_req_valid; /* data valid */
output dc_dat2cvif_rd_req_ready; /* data return handshake */
input [( 64 + 15 )-1:0] dc_dat2cvif_rd_req_pd;
output cvif2dc_dat_rd_rsp_valid; /* data valid */
input cvif2dc_dat_rd_rsp_ready; /* data return handshake */
output [( 256 + (256/8/32) )-1:0] cvif2dc_dat_rd_rsp_pd;
input img_dat2cvif_rd_req_valid; /* data valid */
output img_dat2cvif_rd_req_ready; /* data return handshake */
input [( 64 + 15 )-1:0] img_dat2cvif_rd_req_pd;
output cvif2img_dat_rd_rsp_valid; /* data valid */
input cvif2img_dat_rd_rsp_ready; /* data return handshake */
output [( 256 + (256/8/32) )-1:0] cvif2img_dat_rd_rsp_pd;
output cdma_dat2cvif_rd_req_valid; /* data valid */
input cdma_dat2cvif_rd_req_ready; /* data return handshake */
output [( 64 + 15 )-1:0] cdma_dat2cvif_rd_req_pd;
input cvif2cdma_dat_rd_rsp_valid; /* data valid */
output cvif2cdma_dat_rd_rsp_ready; /* data return handshake */
input [( 256 + (256/8/32) )-1:0] cvif2cdma_dat_rd_rsp_pd;
input dc_dat2mcif_rd_req_valid; /* data valid */
output dc_dat2mcif_rd_req_ready; /* data return handshake */
input [( 64 + 15 )-1:0] dc_dat2mcif_rd_req_pd;
output mcif2dc_dat_rd_rsp_valid; /* data valid */
input mcif2dc_dat_rd_rsp_ready; /* data return handshake */
output [( 256 + (256/8/32) )-1:0] mcif2dc_dat_rd_rsp_pd;
input img_dat2mcif_rd_req_valid; /* data valid */
output img_dat2mcif_rd_req_ready; /* data return handshake */
input [( 64 + 15 )-1:0] img_dat2mcif_rd_req_pd;
output mcif2img_dat_rd_rsp_valid; /* data valid */
input mcif2img_dat_rd_rsp_ready; /* data return handshake */
output [( 256 + (256/8/32) )-1:0] mcif2img_dat_rd_rsp_pd;
output cdma_dat2mcif_rd_req_valid; /* data valid */
input cdma_dat2mcif_rd_req_ready; /* data return handshake */
output [( 64 + 15 )-1:0] cdma_dat2mcif_rd_req_pd;
input mcif2cdma_dat_rd_rsp_valid; /* data valid */
output mcif2cdma_dat_rd_rsp_ready; /* data return handshake */
input [( 256 + (256/8/32) )-1:0] mcif2cdma_dat_rd_rsp_pd;
////////////////////////////////////////////////////////////////////
wire [( 64 + 15 )-1:0] cdma_dat2cvif_rd_req_pd;
wire cdma_dat2cvif_rd_req_valid;
wire cv_sel_dc_w;
wire cv_sel_img_w;
wire cvif2cdma_dat_rd_rsp_ready;
wire [( 256 + (256/8/32) )-1:0] cvif2dc_dat_rd_rsp_pd;
wire cvif2dc_dat_rd_rsp_valid;
wire [( 256 + (256/8/32) )-1:0] cvif2img_dat_rd_rsp_pd;
wire cvif2img_dat_rd_rsp_valid;
wire dc_dat2cvif_rd_req_ready;
wire img_dat2cvif_rd_req_ready;
wire [( 64 + 15 )-1:0] req_cv_in_pd;
wire req_cv_in_pvld;
wire req_cv_out_prdy;
wire [( 256 + (256/8/32) )-1:0] rsp_cv_in_pd;
wire rsp_cv_in_pvld;
wire rsp_cv_out_prdy;
reg cv_sel_dc;
reg cv_sel_img;
wire [( 64 + 15 )-1:0] cdma_dat2mcif_rd_req_pd;
wire cdma_dat2mcif_rd_req_valid;
wire dc_dat2mcif_rd_req_ready;
wire img_dat2mcif_rd_req_ready;
wire mc_sel_dc_w;
wire mc_sel_img_w;
wire mcif2cdma_dat_rd_rsp_ready;
wire [( 256 + (256/8/32) )-1:0] mcif2dc_dat_rd_rsp_pd;
wire mcif2dc_dat_rd_rsp_valid;
wire [( 256 + (256/8/32) )-1:0] mcif2img_dat_rd_rsp_pd;
wire mcif2img_dat_rd_rsp_valid;
wire [( 64 + 15 )-1:0] req_mc_in_pd;
wire req_mc_in_pvld;
wire req_mc_out_prdy;
wire [( 256 + (256/8/32) )-1:0] rsp_mc_in_pd;
wire rsp_mc_in_pvld;
wire rsp_mc_out_prdy;
reg mc_sel_dc;
reg mc_sel_img;
////////////////////////////////////////////////////////////////////////
// Data request channel //
////////////////////////////////////////////////////////////////////////
//////////////// MCIF interface ////////////////
assign mc_sel_dc_w = dc_dat2mcif_rd_req_valid;
assign mc_sel_img_w = img_dat2mcif_rd_req_valid;
assign req_mc_in_pvld = dc_dat2mcif_rd_req_valid |
img_dat2mcif_rd_req_valid;
assign req_mc_in_pd = ({( 64 + 15 ) {mc_sel_dc_w}} & dc_dat2mcif_rd_req_pd) |
({( 64 + 15 ) {mc_sel_img_w}} & img_dat2mcif_rd_req_pd);
//: my $k = ( 64 + 15 );
//: &eperl::pipe("-is -wid ${k} -do req_mc_out_pd -vo req_mc_out_pvld -ri req_mc_out_prdy -di req_mc_in_pd -vi req_mc_in_pvld -ro req_mc_in_prdy");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg req_mc_in_prdy;
reg skid_flop_req_mc_in_prdy;
reg skid_flop_req_mc_in_pvld;
reg [79-1:0] skid_flop_req_mc_in_pd;
reg pipe_skid_req_mc_in_pvld;
reg [79-1:0] pipe_skid_req_mc_in_pd;
// Wire
wire skid_req_mc_in_pvld;
wire [79-1:0] skid_req_mc_in_pd;
wire skid_req_mc_in_prdy;
wire pipe_skid_req_mc_in_prdy;
wire req_mc_out_pvld;
wire [79-1:0] req_mc_out_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
req_mc_in_prdy <= 1'b1;
skid_flop_req_mc_in_prdy <= 1'b1;
end else begin
req_mc_in_prdy <= skid_req_mc_in_prdy;
skid_flop_req_mc_in_prdy <= skid_req_mc_in_prdy;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_req_mc_in_pvld <= 1'b0;
end else begin
if (skid_flop_req_mc_in_prdy) begin
skid_flop_req_mc_in_pvld <= req_mc_in_pvld;
end
end
end
assign skid_req_mc_in_pvld = (skid_flop_req_mc_in_prdy) ? req_mc_in_pvld : skid_flop_req_mc_in_pvld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_req_mc_in_prdy & req_mc_in_pvld) begin
skid_flop_req_mc_in_pd[79-1:0] <= req_mc_in_pd[79-1:0];
end
end
assign skid_req_mc_in_pd[79-1:0] = (skid_flop_req_mc_in_prdy) ? req_mc_in_pd[79-1:0] : skid_flop_req_mc_in_pd[79-1:0];
// PIPE READY
assign skid_req_mc_in_prdy = pipe_skid_req_mc_in_prdy || !pipe_skid_req_mc_in_pvld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_req_mc_in_pvld <= 1'b0;
end else begin
if (skid_req_mc_in_prdy) begin
pipe_skid_req_mc_in_pvld <= skid_req_mc_in_pvld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_req_mc_in_prdy && skid_req_mc_in_pvld) begin
pipe_skid_req_mc_in_pd[79-1:0] <= skid_req_mc_in_pd[79-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_req_mc_in_prdy = req_mc_out_prdy;
assign req_mc_out_pvld = pipe_skid_req_mc_in_pvld;
assign req_mc_out_pd = pipe_skid_req_mc_in_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign dc_dat2mcif_rd_req_ready = req_mc_in_prdy & dc_dat2mcif_rd_req_valid;
assign img_dat2mcif_rd_req_ready = req_mc_in_prdy & img_dat2mcif_rd_req_valid;
assign cdma_dat2mcif_rd_req_valid = req_mc_out_pvld;
assign cdma_dat2mcif_rd_req_pd = req_mc_out_pd;
assign req_mc_out_prdy = cdma_dat2mcif_rd_req_ready;
//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_dc_w\" -q mc_sel_dc");
//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_img_w\" -q mc_sel_img");
//| eperl: generated_beg (DO NOT EDIT BELOW)
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_sel_dc <= 1'b0;
end else begin
if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b1) begin
mc_sel_dc <= mc_sel_dc_w;
// VCS coverage off
end else if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b0) begin
// VCS coverage on
end
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_sel_img <= 1'b0;
end else begin
if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b1) begin
mc_sel_img <= mc_sel_img_w;
// VCS coverage off
end else if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b0) begin
// VCS coverage on
end
end
end
//| eperl: generated_end (DO NOT EDIT ABOVE)
//////////////// CVIF interface ////////////////
assign cv_sel_dc_w = dc_dat2cvif_rd_req_valid;
assign cv_sel_img_w = img_dat2cvif_rd_req_valid;
assign req_cv_in_pvld = dc_dat2cvif_rd_req_valid |
img_dat2cvif_rd_req_valid;
assign req_cv_in_pd = ({( 64 + 15 ) {cv_sel_dc_w}} & dc_dat2cvif_rd_req_pd) |
({( 64 + 15 ) {cv_sel_img_w}} & img_dat2cvif_rd_req_pd);
//: my $k = ( 64 + 15 );
//: &eperl::pipe("-is -wid $k -do req_cv_out_pd -vo req_cv_out_pvld -ri req_cv_out_prdy -di req_cv_in_pd -vi req_cv_in_pvld -ro req_cv_in_prdy");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg req_cv_in_prdy;
reg skid_flop_req_cv_in_prdy;
reg skid_flop_req_cv_in_pvld;
reg [79-1:0] skid_flop_req_cv_in_pd;
reg pipe_skid_req_cv_in_pvld;
reg [79-1:0] pipe_skid_req_cv_in_pd;
// Wire
wire skid_req_cv_in_pvld;
wire [79-1:0] skid_req_cv_in_pd;
wire skid_req_cv_in_prdy;
wire pipe_skid_req_cv_in_prdy;
wire req_cv_out_pvld;
wire [79-1:0] req_cv_out_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
req_cv_in_prdy <= 1'b1;
skid_flop_req_cv_in_prdy <= 1'b1;
end else begin
req_cv_in_prdy <= skid_req_cv_in_prdy;
skid_flop_req_cv_in_prdy <= skid_req_cv_in_prdy;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_req_cv_in_pvld <= 1'b0;
end else begin
if (skid_flop_req_cv_in_prdy) begin
skid_flop_req_cv_in_pvld <= req_cv_in_pvld;
end
end
end
assign skid_req_cv_in_pvld = (skid_flop_req_cv_in_prdy) ? req_cv_in_pvld : skid_flop_req_cv_in_pvld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_req_cv_in_prdy & req_cv_in_pvld) begin
skid_flop_req_cv_in_pd[79-1:0] <= req_cv_in_pd[79-1:0];
end
end
assign skid_req_cv_in_pd[79-1:0] = (skid_flop_req_cv_in_prdy) ? req_cv_in_pd[79-1:0] : skid_flop_req_cv_in_pd[79-1:0];
// PIPE READY
assign skid_req_cv_in_prdy = pipe_skid_req_cv_in_prdy || !pipe_skid_req_cv_in_pvld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_req_cv_in_pvld <= 1'b0;
end else begin
if (skid_req_cv_in_prdy) begin
pipe_skid_req_cv_in_pvld <= skid_req_cv_in_pvld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_req_cv_in_prdy && skid_req_cv_in_pvld) begin
pipe_skid_req_cv_in_pd[79-1:0] <= skid_req_cv_in_pd[79-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_req_cv_in_prdy = req_cv_out_prdy;
assign req_cv_out_pvld = pipe_skid_req_cv_in_pvld;
assign req_cv_out_pd = pipe_skid_req_cv_in_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign dc_dat2cvif_rd_req_ready = req_cv_in_prdy & dc_dat2cvif_rd_req_valid;
assign img_dat2cvif_rd_req_ready = req_cv_in_prdy & img_dat2cvif_rd_req_valid;
assign cdma_dat2cvif_rd_req_valid = req_cv_out_pvld;
assign cdma_dat2cvif_rd_req_pd = req_cv_out_pd;
assign req_cv_out_prdy = cdma_dat2cvif_rd_req_ready;
//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_cv_in_pvld & req_cv_in_prdy\" -d \"cv_sel_dc_w\" -q cv_sel_dc");
//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_cv_in_pvld & req_cv_in_prdy\" -d \"cv_sel_img_w\" -q cv_sel_img");
//| eperl: generated_beg (DO NOT EDIT BELOW)
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_sel_dc <= 1'b0;
end else begin
if ((req_cv_in_pvld & req_cv_in_prdy) == 1'b1) begin
cv_sel_dc <= cv_sel_dc_w;
// VCS coverage off
end else if ((req_cv_in_pvld & req_cv_in_prdy) == 1'b0) begin
// VCS coverage on
end
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_sel_img <= 1'b0;
end else begin
if ((req_cv_in_pvld & req_cv_in_prdy) == 1'b1) begin
cv_sel_img <= cv_sel_img_w;
// VCS coverage off
end else if ((req_cv_in_pvld & req_cv_in_prdy) == 1'b0) begin
// VCS coverage on
end
end
end
//| eperl: generated_end (DO NOT EDIT ABOVE)
//////////////// assertion ////////////////
////////////////////////////////////////////////////////////////////////
// Data response channel //
////////////////////////////////////////////////////////////////////////
//////////////// MCIF interface ////////////////
assign rsp_mc_in_pvld = mcif2cdma_dat_rd_rsp_valid;
assign rsp_mc_in_pd = mcif2cdma_dat_rd_rsp_pd;
//: my $k = ( 256 + (256/8/32) );
//: &eperl::pipe("-is -wid $k -do rsp_mc_out_pd -vo rsp_mc_out_pvld -ri rsp_mc_out_prdy -di rsp_mc_in_pd -vi rsp_mc_in_pvld -ro rsp_mc_in_prdy");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg rsp_mc_in_prdy;
reg skid_flop_rsp_mc_in_prdy;
reg skid_flop_rsp_mc_in_pvld;
reg [257-1:0] skid_flop_rsp_mc_in_pd;
reg pipe_skid_rsp_mc_in_pvld;
reg [257-1:0] pipe_skid_rsp_mc_in_pd;
// Wire
wire skid_rsp_mc_in_pvld;
wire [257-1:0] skid_rsp_mc_in_pd;
wire skid_rsp_mc_in_prdy;
wire pipe_skid_rsp_mc_in_prdy;
wire rsp_mc_out_pvld;
wire [257-1:0] rsp_mc_out_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
rsp_mc_in_prdy <= 1'b1;
skid_flop_rsp_mc_in_prdy <= 1'b1;
end else begin
rsp_mc_in_prdy <= skid_rsp_mc_in_prdy;
skid_flop_rsp_mc_in_prdy <= skid_rsp_mc_in_prdy;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_rsp_mc_in_pvld <= 1'b0;
end else begin
if (skid_flop_rsp_mc_in_prdy) begin
skid_flop_rsp_mc_in_pvld <= rsp_mc_in_pvld;
end
end
end
assign skid_rsp_mc_in_pvld = (skid_flop_rsp_mc_in_prdy) ? rsp_mc_in_pvld : skid_flop_rsp_mc_in_pvld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_rsp_mc_in_prdy & rsp_mc_in_pvld) begin
skid_flop_rsp_mc_in_pd[257-1:0] <= rsp_mc_in_pd[257-1:0];
end
end
assign skid_rsp_mc_in_pd[257-1:0] = (skid_flop_rsp_mc_in_prdy) ? rsp_mc_in_pd[257-1:0] : skid_flop_rsp_mc_in_pd[257-1:0];
// PIPE READY
assign skid_rsp_mc_in_prdy = pipe_skid_rsp_mc_in_prdy || !pipe_skid_rsp_mc_in_pvld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_rsp_mc_in_pvld <= 1'b0;
end else begin
if (skid_rsp_mc_in_prdy) begin
pipe_skid_rsp_mc_in_pvld <= skid_rsp_mc_in_pvld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_rsp_mc_in_prdy && skid_rsp_mc_in_pvld) begin
pipe_skid_rsp_mc_in_pd[257-1:0] <= skid_rsp_mc_in_pd[257-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_rsp_mc_in_prdy = rsp_mc_out_prdy;
assign rsp_mc_out_pvld = pipe_skid_rsp_mc_in_pvld;
assign rsp_mc_out_pd = pipe_skid_rsp_mc_in_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign mcif2cdma_dat_rd_rsp_ready = rsp_mc_in_prdy;
assign mcif2dc_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_dc;
assign mcif2img_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_img;
assign mcif2dc_dat_rd_rsp_pd = {( 256 + (256/8/32) ) {mc_sel_dc}} & rsp_mc_out_pd;
assign mcif2img_dat_rd_rsp_pd = {( 256 + (256/8/32) ) {mc_sel_img}} & rsp_mc_out_pd;
assign rsp_mc_out_prdy = (mc_sel_dc & mcif2dc_dat_rd_rsp_ready) |
(mc_sel_img & mcif2img_dat_rd_rsp_ready);
//////////////// CVIF interface ////////////////
//: my $k = ( 256 + (256/8/32) );
//: &eperl::pipe("-is -wid $k -do rsp_cv_out_pd -vo rsp_cv_out_pvld -ri rsp_cv_out_prdy -di rsp_cv_in_pd -vi rsp_cv_in_pvld -ro rsp_cv_in_prdy");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg rsp_cv_in_prdy;
reg skid_flop_rsp_cv_in_prdy;
reg skid_flop_rsp_cv_in_pvld;
reg [257-1:0] skid_flop_rsp_cv_in_pd;
reg pipe_skid_rsp_cv_in_pvld;
reg [257-1:0] pipe_skid_rsp_cv_in_pd;
// Wire
wire skid_rsp_cv_in_pvld;
wire [257-1:0] skid_rsp_cv_in_pd;
wire skid_rsp_cv_in_prdy;
wire pipe_skid_rsp_cv_in_prdy;
wire rsp_cv_out_pvld;
wire [257-1:0] rsp_cv_out_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
rsp_cv_in_prdy <= 1'b1;
skid_flop_rsp_cv_in_prdy <= 1'b1;
end else begin
rsp_cv_in_prdy <= skid_rsp_cv_in_prdy;
skid_flop_rsp_cv_in_prdy <= skid_rsp_cv_in_prdy;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_rsp_cv_in_pvld <= 1'b0;
end else begin
if (skid_flop_rsp_cv_in_prdy) begin
skid_flop_rsp_cv_in_pvld <= rsp_cv_in_pvld;
end
end
end
assign skid_rsp_cv_in_pvld = (skid_flop_rsp_cv_in_prdy) ? rsp_cv_in_pvld : skid_flop_rsp_cv_in_pvld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_rsp_cv_in_prdy & rsp_cv_in_pvld) begin
skid_flop_rsp_cv_in_pd[257-1:0] <= rsp_cv_in_pd[257-1:0];
end
end
assign skid_rsp_cv_in_pd[257-1:0] = (skid_flop_rsp_cv_in_prdy) ? rsp_cv_in_pd[257-1:0] : skid_flop_rsp_cv_in_pd[257-1:0];
// PIPE READY
assign skid_rsp_cv_in_prdy = pipe_skid_rsp_cv_in_prdy || !pipe_skid_rsp_cv_in_pvld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_rsp_cv_in_pvld <= 1'b0;
end else begin
if (skid_rsp_cv_in_prdy) begin
pipe_skid_rsp_cv_in_pvld <= skid_rsp_cv_in_pvld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_rsp_cv_in_prdy && skid_rsp_cv_in_pvld) begin
pipe_skid_rsp_cv_in_pd[257-1:0] <= skid_rsp_cv_in_pd[257-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_rsp_cv_in_prdy = rsp_cv_out_prdy;
assign rsp_cv_out_pvld = pipe_skid_rsp_cv_in_pvld;
assign rsp_cv_out_pd = pipe_skid_rsp_cv_in_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign rsp_cv_in_pvld = cvif2cdma_dat_rd_rsp_valid;
assign rsp_cv_in_pd = cvif2cdma_dat_rd_rsp_pd;
assign cvif2cdma_dat_rd_rsp_ready = rsp_cv_in_prdy;
assign cvif2dc_dat_rd_rsp_valid = rsp_cv_out_pvld & cv_sel_dc;
assign cvif2img_dat_rd_rsp_valid = rsp_cv_out_pvld & cv_sel_img;
assign cvif2dc_dat_rd_rsp_pd = {( 256 + (256/8/32) ) {cv_sel_dc}} & rsp_cv_out_pd;
assign cvif2img_dat_rd_rsp_pd = {( 256 + (256/8/32) ) {cv_sel_img}} & rsp_cv_out_pd;
assign rsp_cv_out_prdy = (cv_sel_dc & cvif2dc_dat_rd_rsp_ready) |
(cv_sel_img & cvif2img_dat_rd_rsp_ready);
////////////////////////////////////////////////////////////////////////
// Assertion //
////////////////////////////////////////////////////////////////////////
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass disable_block NoWidthInBasedNum-ML
// spyglass disable_block STARC-2.10.3.2a
// spyglass disable_block STARC05-2.1.3.1
// spyglass disable_block STARC-2.1.4.6
// spyglass disable_block W116
// spyglass disable_block W154
// spyglass disable_block W239
// spyglass disable_block W362
// spyglass disable_block WRN_58
// spyglass disable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif // ASSERT_OFF_RESET_IS_X
`endif // SYNTHESIS
`endif // FV_ASSERT_ON
`ifndef SYNTHESIS
// VCS coverage off
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_mc_out_pvld^req_mc_out_prdy^req_mc_in_pvld^req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_cv_out_pvld^req_cv_out_prdy^req_cv_in_pvld^req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_mc_out_pvld^rsp_mc_out_prdy^rsp_mc_in_pvld^rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_cv_out_pvld^rsp_cv_out_prdy^rsp_cv_in_pvld^rsp_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (req_mc_in_pvld && !req_mc_in_prdy), (req_mc_in_pvld), (req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_7x (nvdla_core_clk, `ASSERT_RESET, (req_cv_in_pvld && !req_cv_in_prdy), (req_cv_in_pvld), (req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_19x (nvdla_core_clk, `ASSERT_RESET, (rsp_mc_in_pvld && !rsp_mc_in_prdy), (rsp_mc_in_pvld), (rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_zero_one_hot #(0,2,0,"Error! DMA resp conflict!") zzz_assert_zero_one_hot_22x (nvdla_core_clk, `ASSERT_RESET, {mcif2cdma_dat_rd_rsp_valid, cvif2cdma_dat_rd_rsp_valid}); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_zero_one_hot #(0,2,0,"Error! CVIF req conflict!") zzz_assert_zero_one_hot_12x (nvdla_core_clk, `ASSERT_RESET, {dc_dat2cvif_rd_req_valid, img_dat2cvif_rd_req_valid}); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_zero_one_hot #(0,2,0,"Error! CVIF sel conflict!") zzz_assert_zero_one_hot_17x (nvdla_core_clk, `ASSERT_RESET, {cv_sel_dc, cv_sel_img}); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_never #(0,0,"Error! Change cvif source!") zzz_assert_never_26x (nvdla_core_clk, `ASSERT_RESET, (cvif2cdma_dat_rd_rsp_valid & (|{mc_sel_dc_w, mc_sel_img_w}) & ({cv_sel_dc_w, cv_sel_img_w} != {cv_sel_dc, cv_sel_img}))); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_zero_one_hot #(0,2,0,"Error! DC req conflict!") zzz_assert_zero_one_hot_13x (nvdla_core_clk, `ASSERT_RESET, {dc_dat2mcif_rd_req_valid, dc_dat2cvif_rd_req_valid}); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_zero_one_hot #(0,2,0,"Error! IMG req conflict!") zzz_assert_zero_one_hot_15x (nvdla_core_clk, `ASSERT_RESET, {img_dat2mcif_rd_req_valid, img_dat2cvif_rd_req_valid}); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_21x (nvdla_core_clk, `ASSERT_RESET, (rsp_cv_in_pvld && !rsp_cv_in_prdy), (rsp_cv_in_pvld), (rsp_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_never #(0,0,"Error! Change dma from mcif to cvif!") zzz_assert_never_23x (nvdla_core_clk, `ASSERT_RESET, (cdma_dat2cvif_rd_req_valid & mcif2cdma_dat_rd_rsp_valid)); // spyglass disable W504 SelfDeterminedExpr-ML
nv_assert_never #(0,0,"Error! Change dma from cvif to mcif!") zzz_assert_never_24x (nvdla_core_clk, `ASSERT_RESET, (cdma_dat2mcif_rd_req_valid & cvif2cdma_dat_rd_rsp_valid)); // spyglass disable W504 SelfDeterminedExpr-ML
// VCS coverage on
`endif
`undef ASSERT_RESET
`endif // ASSERT_ON
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass enable_block NoWidthInBasedNum-ML
// spyglass enable_block STARC-2.10.3.2a
// spyglass enable_block STARC05-2.1.3.1
// spyglass enable_block STARC-2.1.4.6
// spyglass enable_block W116
// spyglass enable_block W154
// spyglass enable_block W239
// spyglass enable_block W362
// spyglass enable_block WRN_58
// spyglass enable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
endmodule // NV_NVDLA_CDMA_dma_mux |
module NV_NVDLA_partition_m (
csb2cmac_a_req_pd //|< i
,csb2cmac_a_req_pvld //|< i
,direct_reset_ //|< i
,dla_reset_rstn //|< i
,global_clk_ovr_on //|< i
,nvdla_clk_ovr_on //|< i
,nvdla_core_clk //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,sc2mac_dat_data${i} //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,sc2mac_dat_data0 //|< i
,sc2mac_dat_data1 //|< i
,sc2mac_dat_data2 //|< i
,sc2mac_dat_data3 //|< i
,sc2mac_dat_data4 //|< i
,sc2mac_dat_data5 //|< i
,sc2mac_dat_data6 //|< i
,sc2mac_dat_data7 //|< i
,sc2mac_dat_data8 //|< i
,sc2mac_dat_data9 //|< i
,sc2mac_dat_data10 //|< i
,sc2mac_dat_data11 //|< i
,sc2mac_dat_data12 //|< i
,sc2mac_dat_data13 //|< i
,sc2mac_dat_data14 //|< i
,sc2mac_dat_data15 //|< i
,sc2mac_dat_data16 //|< i
,sc2mac_dat_data17 //|< i
,sc2mac_dat_data18 //|< i
,sc2mac_dat_data19 //|< i
,sc2mac_dat_data20 //|< i
,sc2mac_dat_data21 //|< i
,sc2mac_dat_data22 //|< i
,sc2mac_dat_data23 //|< i
,sc2mac_dat_data24 //|< i
,sc2mac_dat_data25 //|< i
,sc2mac_dat_data26 //|< i
,sc2mac_dat_data27 //|< i
,sc2mac_dat_data28 //|< i
,sc2mac_dat_data29 //|< i
,sc2mac_dat_data30 //|< i
,sc2mac_dat_data31 //|< i
,sc2mac_dat_data32 //|< i
,sc2mac_dat_data33 //|< i
,sc2mac_dat_data34 //|< i
,sc2mac_dat_data35 //|< i
,sc2mac_dat_data36 //|< i
,sc2mac_dat_data37 //|< i
,sc2mac_dat_data38 //|< i
,sc2mac_dat_data39 //|< i
,sc2mac_dat_data40 //|< i
,sc2mac_dat_data41 //|< i
,sc2mac_dat_data42 //|< i
,sc2mac_dat_data43 //|< i
,sc2mac_dat_data44 //|< i
,sc2mac_dat_data45 //|< i
,sc2mac_dat_data46 //|< i
,sc2mac_dat_data47 //|< i
,sc2mac_dat_data48 //|< i
,sc2mac_dat_data49 //|< i
,sc2mac_dat_data50 //|< i
,sc2mac_dat_data51 //|< i
,sc2mac_dat_data52 //|< i
,sc2mac_dat_data53 //|< i
,sc2mac_dat_data54 //|< i
,sc2mac_dat_data55 //|< i
,sc2mac_dat_data56 //|< i
,sc2mac_dat_data57 //|< i
,sc2mac_dat_data58 //|< i
,sc2mac_dat_data59 //|< i
,sc2mac_dat_data60 //|< i
,sc2mac_dat_data61 //|< i
,sc2mac_dat_data62 //|< i
,sc2mac_dat_data63 //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,sc2mac_dat_mask //|< i
,sc2mac_dat_pd //|< i
,sc2mac_dat_pvld //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,sc2mac_wt_data${i} //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,sc2mac_wt_data0 //|< i
,sc2mac_wt_data1 //|< i
,sc2mac_wt_data2 //|< i
,sc2mac_wt_data3 //|< i
,sc2mac_wt_data4 //|< i
,sc2mac_wt_data5 //|< i
,sc2mac_wt_data6 //|< i
,sc2mac_wt_data7 //|< i
,sc2mac_wt_data8 //|< i
,sc2mac_wt_data9 //|< i
,sc2mac_wt_data10 //|< i
,sc2mac_wt_data11 //|< i
,sc2mac_wt_data12 //|< i
,sc2mac_wt_data13 //|< i
,sc2mac_wt_data14 //|< i
,sc2mac_wt_data15 //|< i
,sc2mac_wt_data16 //|< i
,sc2mac_wt_data17 //|< i
,sc2mac_wt_data18 //|< i
,sc2mac_wt_data19 //|< i
,sc2mac_wt_data20 //|< i
,sc2mac_wt_data21 //|< i
,sc2mac_wt_data22 //|< i
,sc2mac_wt_data23 //|< i
,sc2mac_wt_data24 //|< i
,sc2mac_wt_data25 //|< i
,sc2mac_wt_data26 //|< i
,sc2mac_wt_data27 //|< i
,sc2mac_wt_data28 //|< i
,sc2mac_wt_data29 //|< i
,sc2mac_wt_data30 //|< i
,sc2mac_wt_data31 //|< i
,sc2mac_wt_data32 //|< i
,sc2mac_wt_data33 //|< i
,sc2mac_wt_data34 //|< i
,sc2mac_wt_data35 //|< i
,sc2mac_wt_data36 //|< i
,sc2mac_wt_data37 //|< i
,sc2mac_wt_data38 //|< i
,sc2mac_wt_data39 //|< i
,sc2mac_wt_data40 //|< i
,sc2mac_wt_data41 //|< i
,sc2mac_wt_data42 //|< i
,sc2mac_wt_data43 //|< i
,sc2mac_wt_data44 //|< i
,sc2mac_wt_data45 //|< i
,sc2mac_wt_data46 //|< i
,sc2mac_wt_data47 //|< i
,sc2mac_wt_data48 //|< i
,sc2mac_wt_data49 //|< i
,sc2mac_wt_data50 //|< i
,sc2mac_wt_data51 //|< i
,sc2mac_wt_data52 //|< i
,sc2mac_wt_data53 //|< i
,sc2mac_wt_data54 //|< i
,sc2mac_wt_data55 //|< i
,sc2mac_wt_data56 //|< i
,sc2mac_wt_data57 //|< i
,sc2mac_wt_data58 //|< i
,sc2mac_wt_data59 //|< i
,sc2mac_wt_data60 //|< i
,sc2mac_wt_data61 //|< i
,sc2mac_wt_data62 //|< i
,sc2mac_wt_data63 //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,sc2mac_wt_mask //|< i
,sc2mac_wt_pvld //|< i
,sc2mac_wt_sel //|< i
,test_mode //|< i
,tmc2slcg_disable_clock_gating //|< i
,cmac_a2csb_resp_pd //|> o
,cmac_a2csb_resp_valid //|> o
,csb2cmac_a_req_prdy //|> o
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,mac2accu_data${i} //|> o )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac2accu_data0 //|> o
,mac2accu_data1 //|> o
,mac2accu_data2 //|> o
,mac2accu_data3 //|> o
,mac2accu_data4 //|> o
,mac2accu_data5 //|> o
,mac2accu_data6 //|> o
,mac2accu_data7 //|> o
,mac2accu_data8 //|> o
,mac2accu_data9 //|> o
,mac2accu_data10 //|> o
,mac2accu_data11 //|> o
,mac2accu_data12 //|> o
,mac2accu_data13 //|> o
,mac2accu_data14 //|> o
,mac2accu_data15 //|> o
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac2accu_mask //|> o
,mac2accu_mode //|> o
,mac2accu_pd //|> o
,mac2accu_pvld //|> o
);
//
// NV_NVDLA_partition_m_io.v
//
input test_mode;
input direct_reset_;
input csb2cmac_a_req_pvld;
output csb2cmac_a_req_prdy;
input [62:0] csb2cmac_a_req_pd;
output cmac_a2csb_resp_valid;
output [33:0] cmac_a2csb_resp_pd;
input sc2mac_wt_pvld; /* data valid */
input [64 -1:0] sc2mac_wt_mask;
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: input [8 -1:0] sc2mac_wt_data${i}; //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [8 -1:0] sc2mac_wt_data0; //|< i
input [8 -1:0] sc2mac_wt_data1; //|< i
input [8 -1:0] sc2mac_wt_data2; //|< i
input [8 -1:0] sc2mac_wt_data3; //|< i
input [8 -1:0] sc2mac_wt_data4; //|< i
input [8 -1:0] sc2mac_wt_data5; //|< i
input [8 -1:0] sc2mac_wt_data6; //|< i
input [8 -1:0] sc2mac_wt_data7; //|< i
input [8 -1:0] sc2mac_wt_data8; //|< i
input [8 -1:0] sc2mac_wt_data9; //|< i
input [8 -1:0] sc2mac_wt_data10; //|< i
input [8 -1:0] sc2mac_wt_data11; //|< i
input [8 -1:0] sc2mac_wt_data12; //|< i
input [8 -1:0] sc2mac_wt_data13; //|< i
input [8 -1:0] sc2mac_wt_data14; //|< i
input [8 -1:0] sc2mac_wt_data15; //|< i
input [8 -1:0] sc2mac_wt_data16; //|< i
input [8 -1:0] sc2mac_wt_data17; //|< i
input [8 -1:0] sc2mac_wt_data18; //|< i
input [8 -1:0] sc2mac_wt_data19; //|< i
input [8 -1:0] sc2mac_wt_data20; //|< i
input [8 -1:0] sc2mac_wt_data21; //|< i
input [8 -1:0] sc2mac_wt_data22; //|< i
input [8 -1:0] sc2mac_wt_data23; //|< i
input [8 -1:0] sc2mac_wt_data24; //|< i
input [8 -1:0] sc2mac_wt_data25; //|< i
input [8 -1:0] sc2mac_wt_data26; //|< i
input [8 -1:0] sc2mac_wt_data27; //|< i
input [8 -1:0] sc2mac_wt_data28; //|< i
input [8 -1:0] sc2mac_wt_data29; //|< i
input [8 -1:0] sc2mac_wt_data30; //|< i
input [8 -1:0] sc2mac_wt_data31; //|< i
input [8 -1:0] sc2mac_wt_data32; //|< i
input [8 -1:0] sc2mac_wt_data33; //|< i
input [8 -1:0] sc2mac_wt_data34; //|< i
input [8 -1:0] sc2mac_wt_data35; //|< i
input [8 -1:0] sc2mac_wt_data36; //|< i
input [8 -1:0] sc2mac_wt_data37; //|< i
input [8 -1:0] sc2mac_wt_data38; //|< i
input [8 -1:0] sc2mac_wt_data39; //|< i
input [8 -1:0] sc2mac_wt_data40; //|< i
input [8 -1:0] sc2mac_wt_data41; //|< i
input [8 -1:0] sc2mac_wt_data42; //|< i
input [8 -1:0] sc2mac_wt_data43; //|< i
input [8 -1:0] sc2mac_wt_data44; //|< i
input [8 -1:0] sc2mac_wt_data45; //|< i
input [8 -1:0] sc2mac_wt_data46; //|< i
input [8 -1:0] sc2mac_wt_data47; //|< i
input [8 -1:0] sc2mac_wt_data48; //|< i
input [8 -1:0] sc2mac_wt_data49; //|< i
input [8 -1:0] sc2mac_wt_data50; //|< i
input [8 -1:0] sc2mac_wt_data51; //|< i
input [8 -1:0] sc2mac_wt_data52; //|< i
input [8 -1:0] sc2mac_wt_data53; //|< i
input [8 -1:0] sc2mac_wt_data54; //|< i
input [8 -1:0] sc2mac_wt_data55; //|< i
input [8 -1:0] sc2mac_wt_data56; //|< i
input [8 -1:0] sc2mac_wt_data57; //|< i
input [8 -1:0] sc2mac_wt_data58; //|< i
input [8 -1:0] sc2mac_wt_data59; //|< i
input [8 -1:0] sc2mac_wt_data60; //|< i
input [8 -1:0] sc2mac_wt_data61; //|< i
input [8 -1:0] sc2mac_wt_data62; //|< i
input [8 -1:0] sc2mac_wt_data63; //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [32/2 -1:0] sc2mac_wt_sel;
input sc2mac_dat_pvld; /* data valid */
input [64 -1:0] sc2mac_dat_mask;
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: input [8 -1:0] sc2mac_dat_data${i}; //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [8 -1:0] sc2mac_dat_data0; //|< i
input [8 -1:0] sc2mac_dat_data1; //|< i
input [8 -1:0] sc2mac_dat_data2; //|< i
input [8 -1:0] sc2mac_dat_data3; //|< i
input [8 -1:0] sc2mac_dat_data4; //|< i
input [8 -1:0] sc2mac_dat_data5; //|< i
input [8 -1:0] sc2mac_dat_data6; //|< i
input [8 -1:0] sc2mac_dat_data7; //|< i
input [8 -1:0] sc2mac_dat_data8; //|< i
input [8 -1:0] sc2mac_dat_data9; //|< i
input [8 -1:0] sc2mac_dat_data10; //|< i
input [8 -1:0] sc2mac_dat_data11; //|< i
input [8 -1:0] sc2mac_dat_data12; //|< i
input [8 -1:0] sc2mac_dat_data13; //|< i
input [8 -1:0] sc2mac_dat_data14; //|< i
input [8 -1:0] sc2mac_dat_data15; //|< i
input [8 -1:0] sc2mac_dat_data16; //|< i
input [8 -1:0] sc2mac_dat_data17; //|< i
input [8 -1:0] sc2mac_dat_data18; //|< i
input [8 -1:0] sc2mac_dat_data19; //|< i
input [8 -1:0] sc2mac_dat_data20; //|< i
input [8 -1:0] sc2mac_dat_data21; //|< i
input [8 -1:0] sc2mac_dat_data22; //|< i
input [8 -1:0] sc2mac_dat_data23; //|< i
input [8 -1:0] sc2mac_dat_data24; //|< i
input [8 -1:0] sc2mac_dat_data25; //|< i
input [8 -1:0] sc2mac_dat_data26; //|< i
input [8 -1:0] sc2mac_dat_data27; //|< i
input [8 -1:0] sc2mac_dat_data28; //|< i
input [8 -1:0] sc2mac_dat_data29; //|< i
input [8 -1:0] sc2mac_dat_data30; //|< i
input [8 -1:0] sc2mac_dat_data31; //|< i
input [8 -1:0] sc2mac_dat_data32; //|< i
input [8 -1:0] sc2mac_dat_data33; //|< i
input [8 -1:0] sc2mac_dat_data34; //|< i
input [8 -1:0] sc2mac_dat_data35; //|< i
input [8 -1:0] sc2mac_dat_data36; //|< i
input [8 -1:0] sc2mac_dat_data37; //|< i
input [8 -1:0] sc2mac_dat_data38; //|< i
input [8 -1:0] sc2mac_dat_data39; //|< i
input [8 -1:0] sc2mac_dat_data40; //|< i
input [8 -1:0] sc2mac_dat_data41; //|< i
input [8 -1:0] sc2mac_dat_data42; //|< i
input [8 -1:0] sc2mac_dat_data43; //|< i
input [8 -1:0] sc2mac_dat_data44; //|< i
input [8 -1:0] sc2mac_dat_data45; //|< i
input [8 -1:0] sc2mac_dat_data46; //|< i
input [8 -1:0] sc2mac_dat_data47; //|< i
input [8 -1:0] sc2mac_dat_data48; //|< i
input [8 -1:0] sc2mac_dat_data49; //|< i
input [8 -1:0] sc2mac_dat_data50; //|< i
input [8 -1:0] sc2mac_dat_data51; //|< i
input [8 -1:0] sc2mac_dat_data52; //|< i
input [8 -1:0] sc2mac_dat_data53; //|< i
input [8 -1:0] sc2mac_dat_data54; //|< i
input [8 -1:0] sc2mac_dat_data55; //|< i
input [8 -1:0] sc2mac_dat_data56; //|< i
input [8 -1:0] sc2mac_dat_data57; //|< i
input [8 -1:0] sc2mac_dat_data58; //|< i
input [8 -1:0] sc2mac_dat_data59; //|< i
input [8 -1:0] sc2mac_dat_data60; //|< i
input [8 -1:0] sc2mac_dat_data61; //|< i
input [8 -1:0] sc2mac_dat_data62; //|< i
input [8 -1:0] sc2mac_dat_data63; //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [8:0] sc2mac_dat_pd;
output mac2accu_pvld; /* data valid */
output [32/2 -1:0] mac2accu_mask;
output mac2accu_mode;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: output [22 -1:0] mac2accu_data${i}; )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
output [22 -1:0] mac2accu_data0;
output [22 -1:0] mac2accu_data1;
output [22 -1:0] mac2accu_data2;
output [22 -1:0] mac2accu_data3;
output [22 -1:0] mac2accu_data4;
output [22 -1:0] mac2accu_data5;
output [22 -1:0] mac2accu_data6;
output [22 -1:0] mac2accu_data7;
output [22 -1:0] mac2accu_data8;
output [22 -1:0] mac2accu_data9;
output [22 -1:0] mac2accu_data10;
output [22 -1:0] mac2accu_data11;
output [22 -1:0] mac2accu_data12;
output [22 -1:0] mac2accu_data13;
output [22 -1:0] mac2accu_data14;
output [22 -1:0] mac2accu_data15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output [8:0] mac2accu_pd;
input global_clk_ovr_on;
input tmc2slcg_disable_clock_gating;
wire dla_clk_ovr_on_sync;
wire global_clk_ovr_on_sync;
wire nvdla_core_rstn;
input nvdla_core_clk;
input dla_reset_rstn;
input nvdla_clk_ovr_on;
////////////////////////////////////////////////////////////////////////
// NVDLA Partition M: Reset Syncer //
////////////////////////////////////////////////////////////////////////
NV_NVDLA_reset u_partition_m_reset (
.dla_reset_rstn (dla_reset_rstn)
,.direct_reset_ (direct_reset_)
,.test_mode (test_mode)
,.synced_rstn (nvdla_core_rstn)
,.nvdla_clk (nvdla_core_clk)
);
////////////////////////////////////////////////////////////////////////
// SLCG override
////////////////////////////////////////////////////////////////////////
NV_NVDLA_sync3d u_dla_clk_ovr_on_sync (
.clk (nvdla_core_clk)
,.sync_i (nvdla_clk_ovr_on)
,.sync_o (dla_clk_ovr_on_sync)
);
NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (
.clk (nvdla_core_clk)
,.prst (nvdla_core_rstn)
,.sync_i (global_clk_ovr_on)
,.sync_o (global_clk_ovr_on_sync)
);
////////////////////////////////////////////////////////////////////////
// NVDLA Partition M: Convolution MAC Array //
////////////////////////////////////////////////////////////////////////
NV_NVDLA_cmac u_NV_NVDLA_cmac (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< w
,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o
,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o
,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i
,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o
,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i
,.mac2accu_pvld (mac2accu_pvld) //|> o
,.mac2accu_mask (mac2accu_mask) //|> o
,.mac2accu_mode (mac2accu_mode) //|> o
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac2accu_data0 (mac2accu_data0) //|> o
,.mac2accu_data1 (mac2accu_data1) //|> o
,.mac2accu_data2 (mac2accu_data2) //|> o
,.mac2accu_data3 (mac2accu_data3) //|> o
,.mac2accu_data4 (mac2accu_data4) //|> o
,.mac2accu_data5 (mac2accu_data5) //|> o
,.mac2accu_data6 (mac2accu_data6) //|> o
,.mac2accu_data7 (mac2accu_data7) //|> o
,.mac2accu_data8 (mac2accu_data8) //|> o
,.mac2accu_data9 (mac2accu_data9) //|> o
,.mac2accu_data10 (mac2accu_data10) //|> o
,.mac2accu_data11 (mac2accu_data11) //|> o
,.mac2accu_data12 (mac2accu_data12) //|> o
,.mac2accu_data13 (mac2accu_data13) //|> o
,.mac2accu_data14 (mac2accu_data14) //|> o
,.mac2accu_data15 (mac2accu_data15) //|> o
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac2accu_pd (mac2accu_pd) //|> o
,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i
,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.sc2mac_dat_data0 (sc2mac_dat_data0) //|< i
,.sc2mac_dat_data1 (sc2mac_dat_data1) //|< i
,.sc2mac_dat_data2 (sc2mac_dat_data2) //|< i
,.sc2mac_dat_data3 (sc2mac_dat_data3) //|< i
,.sc2mac_dat_data4 (sc2mac_dat_data4) //|< i
,.sc2mac_dat_data5 (sc2mac_dat_data5) //|< i
,.sc2mac_dat_data6 (sc2mac_dat_data6) //|< i
,.sc2mac_dat_data7 (sc2mac_dat_data7) //|< i
,.sc2mac_dat_data8 (sc2mac_dat_data8) //|< i
,.sc2mac_dat_data9 (sc2mac_dat_data9) //|< i
,.sc2mac_dat_data10 (sc2mac_dat_data10) //|< i
,.sc2mac_dat_data11 (sc2mac_dat_data11) //|< i
,.sc2mac_dat_data12 (sc2mac_dat_data12) //|< i
,.sc2mac_dat_data13 (sc2mac_dat_data13) //|< i
,.sc2mac_dat_data14 (sc2mac_dat_data14) //|< i
,.sc2mac_dat_data15 (sc2mac_dat_data15) //|< i
,.sc2mac_dat_data16 (sc2mac_dat_data16) //|< i
,.sc2mac_dat_data17 (sc2mac_dat_data17) //|< i
,.sc2mac_dat_data18 (sc2mac_dat_data18) //|< i
,.sc2mac_dat_data19 (sc2mac_dat_data19) //|< i
,.sc2mac_dat_data20 (sc2mac_dat_data20) //|< i
,.sc2mac_dat_data21 (sc2mac_dat_data21) //|< i
,.sc2mac_dat_data22 (sc2mac_dat_data22) //|< i
,.sc2mac_dat_data23 (sc2mac_dat_data23) //|< i
,.sc2mac_dat_data24 (sc2mac_dat_data24) //|< i
,.sc2mac_dat_data25 (sc2mac_dat_data25) //|< i
,.sc2mac_dat_data26 (sc2mac_dat_data26) //|< i
,.sc2mac_dat_data27 (sc2mac_dat_data27) //|< i
,.sc2mac_dat_data28 (sc2mac_dat_data28) //|< i
,.sc2mac_dat_data29 (sc2mac_dat_data29) //|< i
,.sc2mac_dat_data30 (sc2mac_dat_data30) //|< i
,.sc2mac_dat_data31 (sc2mac_dat_data31) //|< i
,.sc2mac_dat_data32 (sc2mac_dat_data32) //|< i
,.sc2mac_dat_data33 (sc2mac_dat_data33) //|< i
,.sc2mac_dat_data34 (sc2mac_dat_data34) //|< i
,.sc2mac_dat_data35 (sc2mac_dat_data35) //|< i
,.sc2mac_dat_data36 (sc2mac_dat_data36) //|< i
,.sc2mac_dat_data37 (sc2mac_dat_data37) //|< i
,.sc2mac_dat_data38 (sc2mac_dat_data38) //|< i
,.sc2mac_dat_data39 (sc2mac_dat_data39) //|< i
,.sc2mac_dat_data40 (sc2mac_dat_data40) //|< i
,.sc2mac_dat_data41 (sc2mac_dat_data41) //|< i
,.sc2mac_dat_data42 (sc2mac_dat_data42) //|< i
,.sc2mac_dat_data43 (sc2mac_dat_data43) //|< i
,.sc2mac_dat_data44 (sc2mac_dat_data44) //|< i
,.sc2mac_dat_data45 (sc2mac_dat_data45) //|< i
,.sc2mac_dat_data46 (sc2mac_dat_data46) //|< i
,.sc2mac_dat_data47 (sc2mac_dat_data47) //|< i
,.sc2mac_dat_data48 (sc2mac_dat_data48) //|< i
,.sc2mac_dat_data49 (sc2mac_dat_data49) //|< i
,.sc2mac_dat_data50 (sc2mac_dat_data50) //|< i
,.sc2mac_dat_data51 (sc2mac_dat_data51) //|< i
,.sc2mac_dat_data52 (sc2mac_dat_data52) //|< i
,.sc2mac_dat_data53 (sc2mac_dat_data53) //|< i
,.sc2mac_dat_data54 (sc2mac_dat_data54) //|< i
,.sc2mac_dat_data55 (sc2mac_dat_data55) //|< i
,.sc2mac_dat_data56 (sc2mac_dat_data56) //|< i
,.sc2mac_dat_data57 (sc2mac_dat_data57) //|< i
,.sc2mac_dat_data58 (sc2mac_dat_data58) //|< i
,.sc2mac_dat_data59 (sc2mac_dat_data59) //|< i
,.sc2mac_dat_data60 (sc2mac_dat_data60) //|< i
,.sc2mac_dat_data61 (sc2mac_dat_data61) //|< i
,.sc2mac_dat_data62 (sc2mac_dat_data62) //|< i
,.sc2mac_dat_data63 (sc2mac_dat_data63) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i
,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i
,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.sc2mac_wt_data0 (sc2mac_wt_data0) //|< i
,.sc2mac_wt_data1 (sc2mac_wt_data1) //|< i
,.sc2mac_wt_data2 (sc2mac_wt_data2) //|< i
,.sc2mac_wt_data3 (sc2mac_wt_data3) //|< i
,.sc2mac_wt_data4 (sc2mac_wt_data4) //|< i
,.sc2mac_wt_data5 (sc2mac_wt_data5) //|< i
,.sc2mac_wt_data6 (sc2mac_wt_data6) //|< i
,.sc2mac_wt_data7 (sc2mac_wt_data7) //|< i
,.sc2mac_wt_data8 (sc2mac_wt_data8) //|< i
,.sc2mac_wt_data9 (sc2mac_wt_data9) //|< i
,.sc2mac_wt_data10 (sc2mac_wt_data10) //|< i
,.sc2mac_wt_data11 (sc2mac_wt_data11) //|< i
,.sc2mac_wt_data12 (sc2mac_wt_data12) //|< i
,.sc2mac_wt_data13 (sc2mac_wt_data13) //|< i
,.sc2mac_wt_data14 (sc2mac_wt_data14) //|< i
,.sc2mac_wt_data15 (sc2mac_wt_data15) //|< i
,.sc2mac_wt_data16 (sc2mac_wt_data16) //|< i
,.sc2mac_wt_data17 (sc2mac_wt_data17) //|< i
,.sc2mac_wt_data18 (sc2mac_wt_data18) //|< i
,.sc2mac_wt_data19 (sc2mac_wt_data19) //|< i
,.sc2mac_wt_data20 (sc2mac_wt_data20) //|< i
,.sc2mac_wt_data21 (sc2mac_wt_data21) //|< i
,.sc2mac_wt_data22 (sc2mac_wt_data22) //|< i
,.sc2mac_wt_data23 (sc2mac_wt_data23) //|< i
,.sc2mac_wt_data24 (sc2mac_wt_data24) //|< i
,.sc2mac_wt_data25 (sc2mac_wt_data25) //|< i
,.sc2mac_wt_data26 (sc2mac_wt_data26) //|< i
,.sc2mac_wt_data27 (sc2mac_wt_data27) //|< i
,.sc2mac_wt_data28 (sc2mac_wt_data28) //|< i
,.sc2mac_wt_data29 (sc2mac_wt_data29) //|< i
,.sc2mac_wt_data30 (sc2mac_wt_data30) //|< i
,.sc2mac_wt_data31 (sc2mac_wt_data31) //|< i
,.sc2mac_wt_data32 (sc2mac_wt_data32) //|< i
,.sc2mac_wt_data33 (sc2mac_wt_data33) //|< i
,.sc2mac_wt_data34 (sc2mac_wt_data34) //|< i
,.sc2mac_wt_data35 (sc2mac_wt_data35) //|< i
,.sc2mac_wt_data36 (sc2mac_wt_data36) //|< i
,.sc2mac_wt_data37 (sc2mac_wt_data37) //|< i
,.sc2mac_wt_data38 (sc2mac_wt_data38) //|< i
,.sc2mac_wt_data39 (sc2mac_wt_data39) //|< i
,.sc2mac_wt_data40 (sc2mac_wt_data40) //|< i
,.sc2mac_wt_data41 (sc2mac_wt_data41) //|< i
,.sc2mac_wt_data42 (sc2mac_wt_data42) //|< i
,.sc2mac_wt_data43 (sc2mac_wt_data43) //|< i
,.sc2mac_wt_data44 (sc2mac_wt_data44) //|< i
,.sc2mac_wt_data45 (sc2mac_wt_data45) //|< i
,.sc2mac_wt_data46 (sc2mac_wt_data46) //|< i
,.sc2mac_wt_data47 (sc2mac_wt_data47) //|< i
,.sc2mac_wt_data48 (sc2mac_wt_data48) //|< i
,.sc2mac_wt_data49 (sc2mac_wt_data49) //|< i
,.sc2mac_wt_data50 (sc2mac_wt_data50) //|< i
,.sc2mac_wt_data51 (sc2mac_wt_data51) //|< i
,.sc2mac_wt_data52 (sc2mac_wt_data52) //|< i
,.sc2mac_wt_data53 (sc2mac_wt_data53) //|< i
,.sc2mac_wt_data54 (sc2mac_wt_data54) //|< i
,.sc2mac_wt_data55 (sc2mac_wt_data55) //|< i
,.sc2mac_wt_data56 (sc2mac_wt_data56) //|< i
,.sc2mac_wt_data57 (sc2mac_wt_data57) //|< i
,.sc2mac_wt_data58 (sc2mac_wt_data58) //|< i
,.sc2mac_wt_data59 (sc2mac_wt_data59) //|< i
,.sc2mac_wt_data60 (sc2mac_wt_data60) //|< i
,.sc2mac_wt_data61 (sc2mac_wt_data61) //|< i
,.sc2mac_wt_data62 (sc2mac_wt_data62) //|< i
,.sc2mac_wt_data63 (sc2mac_wt_data63) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
);
endmodule // NV_NVDLA_partition_m |
module NV_NVDLA_CDP_DP_sum (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,normalz_buf_data //|< i
,normalz_buf_data_pvld //|< i
,reg2dp_normalz_len //|< i
,sum2itp_prdy //|< i
,normalz_buf_data_prdy //|> o
,sum2itp_pd //|> o
,sum2itp_pvld //|> o
);
/////////////////////////////////////////////////////
// parameter pINT8_BW = 9;
/////////////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $k = ${icvto}*(${tp}+8)+17;
//: print qq(
//: input [${k}-1:0] normalz_buf_data;
//: output [${tp}*(${icvto}*2+3)-1:0] sum2itp_pd;
//: );
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [161-1:0] normalz_buf_data;
output [8*(9*2+3)-1:0] sum2itp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input normalz_buf_data_pvld;
input [1:0] reg2dp_normalz_len;
input sum2itp_prdy;
output normalz_buf_data_prdy;
output sum2itp_pvld;
/////////////////////////////////////////////////////
reg buf2sum_2d_vld;
reg buf2sum_3d_vld;
reg buf2sum_d_vld;
wire buf2sum_2d_rdy;
wire buf2sum_3d_rdy;
wire buf2sum_d_rdy;
wire buf2sum_din_prdy;
wire buf2sum_rdy_f;
wire cdp_buf2sum_ready;
//: my $icvto=(8 +1);
//: my $tp=8 +8;
//: foreach my $i (0..${tp}-1) {
//: print qq(
//: wire [${icvto}-1:0] buf2sum_int8_$i;
//: wire [${icvto}-1:0] inv_${i};
//: wire [${icvto}-1:0] int8_abs_${i};
//: reg [${icvto}*2-2:0] int8_sq_${i};
//: reg mon_int8_sq_${i};
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [9-1:0] buf2sum_int8_0;
wire [9-1:0] inv_0;
wire [9-1:0] int8_abs_0;
reg [9*2-2:0] int8_sq_0;
reg mon_int8_sq_0;
wire [9-1:0] buf2sum_int8_1;
wire [9-1:0] inv_1;
wire [9-1:0] int8_abs_1;
reg [9*2-2:0] int8_sq_1;
reg mon_int8_sq_1;
wire [9-1:0] buf2sum_int8_2;
wire [9-1:0] inv_2;
wire [9-1:0] int8_abs_2;
reg [9*2-2:0] int8_sq_2;
reg mon_int8_sq_2;
wire [9-1:0] buf2sum_int8_3;
wire [9-1:0] inv_3;
wire [9-1:0] int8_abs_3;
reg [9*2-2:0] int8_sq_3;
reg mon_int8_sq_3;
wire [9-1:0] buf2sum_int8_4;
wire [9-1:0] inv_4;
wire [9-1:0] int8_abs_4;
reg [9*2-2:0] int8_sq_4;
reg mon_int8_sq_4;
wire [9-1:0] buf2sum_int8_5;
wire [9-1:0] inv_5;
wire [9-1:0] int8_abs_5;
reg [9*2-2:0] int8_sq_5;
reg mon_int8_sq_5;
wire [9-1:0] buf2sum_int8_6;
wire [9-1:0] inv_6;
wire [9-1:0] int8_abs_6;
reg [9*2-2:0] int8_sq_6;
reg mon_int8_sq_6;
wire [9-1:0] buf2sum_int8_7;
wire [9-1:0] inv_7;
wire [9-1:0] int8_abs_7;
reg [9*2-2:0] int8_sq_7;
reg mon_int8_sq_7;
wire [9-1:0] buf2sum_int8_8;
wire [9-1:0] inv_8;
wire [9-1:0] int8_abs_8;
reg [9*2-2:0] int8_sq_8;
reg mon_int8_sq_8;
wire [9-1:0] buf2sum_int8_9;
wire [9-1:0] inv_9;
wire [9-1:0] int8_abs_9;
reg [9*2-2:0] int8_sq_9;
reg mon_int8_sq_9;
wire [9-1:0] buf2sum_int8_10;
wire [9-1:0] inv_10;
wire [9-1:0] int8_abs_10;
reg [9*2-2:0] int8_sq_10;
reg mon_int8_sq_10;
wire [9-1:0] buf2sum_int8_11;
wire [9-1:0] inv_11;
wire [9-1:0] int8_abs_11;
reg [9*2-2:0] int8_sq_11;
reg mon_int8_sq_11;
wire [9-1:0] buf2sum_int8_12;
wire [9-1:0] inv_12;
wire [9-1:0] int8_abs_12;
reg [9*2-2:0] int8_sq_12;
reg mon_int8_sq_12;
wire [9-1:0] buf2sum_int8_13;
wire [9-1:0] inv_13;
wire [9-1:0] int8_abs_13;
reg [9*2-2:0] int8_sq_13;
reg mon_int8_sq_13;
wire [9-1:0] buf2sum_int8_14;
wire [9-1:0] inv_14;
wire [9-1:0] int8_abs_14;
reg [9*2-2:0] int8_sq_14;
reg mon_int8_sq_14;
wire [9-1:0] buf2sum_int8_15;
wire [9-1:0] inv_15;
wire [9-1:0] int8_abs_15;
reg [9*2-2:0] int8_sq_15;
reg mon_int8_sq_15;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [7:0] int8_inv_2;
wire [7:0] int8_inv_3;
wire [7:0] int8_inv_4;
wire [7:0] int8_inv_5;
wire [7:0] int8_inv_6;
wire [7:0] int8_inv_7;
wire [7:0] int8_inv_8;
wire [7:0] int8_inv_9;
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $k = ${tp}*(${icvto}*2+3);
//: print qq(
//: wire [${k}-1:0] sum_out_pd;
//: wire [${k}-1:0] sum2itp_data;
//: );
//: foreach my $i (0..$tp-1){
//: print qq(
//: wire [${icvto}*2-1+4-1:0] int8_sum_$i;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [168-1:0] sum_out_pd;
wire [168-1:0] sum2itp_data;
wire [9*2-1+4-1:0] int8_sum_0;
wire [9*2-1+4-1:0] int8_sum_1;
wire [9*2-1+4-1:0] int8_sum_2;
wire [9*2-1+4-1:0] int8_sum_3;
wire [9*2-1+4-1:0] int8_sum_4;
wire [9*2-1+4-1:0] int8_sum_5;
wire [9*2-1+4-1:0] int8_sum_6;
wire [9*2-1+4-1:0] int8_sum_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [41:0] int8_sum_1st;
wire [41:0] int8_sum_2nd;
wire [41:0] int8_sum_3rd;
wire [41:0] int8_sum_4th;
wire [15:0] int_ivt_2;
wire [15:0] int_ivt_3;
wire [15:0] int_ivt_4;
wire [15:0] int_ivt_5;
wire [15:0] int_ivt_6;
wire [15:0] int_ivt_7;
wire [15:0] int_ivt_8;
wire [15:0] int_ivt_9;
wire [16:0] int_sq_datin_2;
wire [16:0] int_sq_datin_3;
wire [16:0] int_sq_datin_4;
wire [16:0] int_sq_datin_5;
wire [16:0] int_sq_datin_6;
wire [16:0] int_sq_datin_7;
wire [16:0] int_sq_datin_8;
wire [16:0] int_sq_datin_9;
wire [16:0] int_sq_datin_abs_2;
wire [16:0] int_sq_datin_abs_3;
wire [16:0] int_sq_datin_abs_4;
wire [16:0] int_sq_datin_abs_5;
wire [16:0] int_sq_datin_abs_6;
wire [16:0] int_sq_datin_abs_7;
wire [16:0] int_sq_datin_abs_8;
wire [16:0] int_sq_datin_abs_9;
wire len3;
wire len5;
wire len7;
wire len9;
wire load_din;
wire load_din_2d;
wire load_din_d;
wire sum2itp_valid;
wire sum_out_prdy;
wire sum_out_pvld;
///////////////////////////////////////////
//==========================================
//----------------------------------------
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $k = ${icvto}*(${tp}+8)+17;
//: &eperl::pipe(" -wid $k -do cdp_buf2sum_pd -vo cdp_buf2sum_valid -ri cdp_buf2sum_ready -di normalz_buf_data -vi normalz_buf_data_pvld -ro normalz_buf_data_prdy ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg pipe_normalz_buf_data_pvld;
reg [161-1:0] pipe_normalz_buf_data;
// Wire
wire normalz_buf_data_prdy;
wire pipe_normalz_buf_data_prdy;
wire cdp_buf2sum_valid;
wire [161-1:0] cdp_buf2sum_pd;
// Code
// PIPE READY
assign normalz_buf_data_prdy = pipe_normalz_buf_data_prdy || !pipe_normalz_buf_data_pvld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_normalz_buf_data_pvld <= 1'b0;
end else begin
if (normalz_buf_data_prdy) begin
pipe_normalz_buf_data_pvld <= normalz_buf_data_pvld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (normalz_buf_data_prdy && normalz_buf_data_pvld) begin
pipe_normalz_buf_data[161-1:0] <= normalz_buf_data[161-1:0];
end
end
// PIPE OUTPUT
assign pipe_normalz_buf_data_prdy = cdp_buf2sum_ready;
assign cdp_buf2sum_valid = pipe_normalz_buf_data_pvld;
assign cdp_buf2sum_pd = pipe_normalz_buf_data;
//| eperl: generated_end (DO NOT EDIT ABOVE)
/////////////////////////////////////////////
assign load_din = (cdp_buf2sum_valid & buf2sum_rdy_f);
assign cdp_buf2sum_ready = buf2sum_rdy_f;
assign buf2sum_rdy_f = buf2sum_din_prdy;
//==========================================
//: my $icvto=(8 +1);
//: my $tp=8 +8;
//: foreach my $i (0..${tp}-1) {
//: print qq(
//: assign buf2sum_int8_$i = cdp_buf2sum_pd[${icvto}*${i}+${icvto}-1:${icvto}*${i}];
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign buf2sum_int8_0 = cdp_buf2sum_pd[9*0+9-1:9*0];
assign buf2sum_int8_1 = cdp_buf2sum_pd[9*1+9-1:9*1];
assign buf2sum_int8_2 = cdp_buf2sum_pd[9*2+9-1:9*2];
assign buf2sum_int8_3 = cdp_buf2sum_pd[9*3+9-1:9*3];
assign buf2sum_int8_4 = cdp_buf2sum_pd[9*4+9-1:9*4];
assign buf2sum_int8_5 = cdp_buf2sum_pd[9*5+9-1:9*5];
assign buf2sum_int8_6 = cdp_buf2sum_pd[9*6+9-1:9*6];
assign buf2sum_int8_7 = cdp_buf2sum_pd[9*7+9-1:9*7];
assign buf2sum_int8_8 = cdp_buf2sum_pd[9*8+9-1:9*8];
assign buf2sum_int8_9 = cdp_buf2sum_pd[9*9+9-1:9*9];
assign buf2sum_int8_10 = cdp_buf2sum_pd[9*10+9-1:9*10];
assign buf2sum_int8_11 = cdp_buf2sum_pd[9*11+9-1:9*11];
assign buf2sum_int8_12 = cdp_buf2sum_pd[9*12+9-1:9*12];
assign buf2sum_int8_13 = cdp_buf2sum_pd[9*13+9-1:9*13];
assign buf2sum_int8_14 = cdp_buf2sum_pd[9*14+9-1:9*14];
assign buf2sum_int8_15 = cdp_buf2sum_pd[9*15+9-1:9*15];
//| eperl: generated_end (DO NOT EDIT ABOVE)
//========================================================
//int mode
//--------------------------------------------------------
//: my $tp=8;
//: my $icvto=(8 +1);
//: foreach my $i (0..${tp}+8-1) {
//: print qq(
//: assign inv_${i} = buf2sum_int8_${i}[${icvto}-1] ? (~buf2sum_int8_${i}[${icvto}-2:0]) : {(${icvto}-1){1'b0}};
//: assign int8_abs_${i} = buf2sum_int8_${i}[${icvto}-1] ? (inv_${i}[${icvto}-2:0] + {{(${icvto}-2){1'b0}},1'b1}) : buf2sum_int8_${i};
//: );
//: }
//:
//: print qq(
//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
//: if (!nvdla_core_rstn) begin
//: );
//: foreach my $i (0..${tp}+8-1) {
//: print qq(
//: {mon_int8_sq_${i},int8_sq_${i}} <= {(${icvto}*2-1){1'b0}};
//: );
//: }
//: print qq(
//: end else if(load_din) begin
//: {mon_int8_sq_0,int8_sq_0} <= len9 ? (int8_abs_0 * int8_abs_0) : {(${icvto}*2){1'b0}};
//: {mon_int8_sq_1,int8_sq_1} <= ( len7|len9)? (int8_abs_1 * int8_abs_1) : {(${icvto}*2){1'b0}};
//: {mon_int8_sq_2,int8_sq_2} <= (len5|len7|len9)? (int8_abs_2 * int8_abs_2) : {(${icvto}*2){1'b0}};
//: {mon_int8_sq_3,int8_sq_3} <= (int8_abs_3 * int8_abs_3);
//: );
//: foreach my $i (0..${tp}-1) {
//: my $j = 4 + $i;
//: print "{mon_int8_sq_${j},int8_sq_${j}} <= (int8_abs_${j} * int8_abs_${j}); \n";
//: }
//: my $b0 = ${tp}+4+0;
//: my $b1 = ${tp}+4+1;
//: my $b2 = ${tp}+4+2;
//: my $b3 = ${tp}+4+3;
//: print qq(
//: {mon_int8_sq_${b0},int8_sq_${b0}} <= (int8_abs_${b0} * int8_abs_${b0});
//: {mon_int8_sq_${b1},int8_sq_${b1}} <= (len5|len7|len9)? (int8_abs_${b1} * int8_abs_${b1}) : {(${icvto}*2){1'b0}};
//: {mon_int8_sq_${b2},int8_sq_${b2}} <= ( len7|len9)? (int8_abs_${b2} * int8_abs_${b2}) : {(${icvto}*2){1'b0}};
//: {mon_int8_sq_${b3},int8_sq_${b3}} <= len9 ? (int8_abs_${b3} * int8_abs_${b3}) : {(${icvto}*2){1'b0}};
//: end
//: end
//: );
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign inv_0 = buf2sum_int8_0[9-1] ? (~buf2sum_int8_0[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_0 = buf2sum_int8_0[9-1] ? (inv_0[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_0;
assign inv_1 = buf2sum_int8_1[9-1] ? (~buf2sum_int8_1[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_1 = buf2sum_int8_1[9-1] ? (inv_1[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_1;
assign inv_2 = buf2sum_int8_2[9-1] ? (~buf2sum_int8_2[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_2 = buf2sum_int8_2[9-1] ? (inv_2[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_2;
assign inv_3 = buf2sum_int8_3[9-1] ? (~buf2sum_int8_3[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_3 = buf2sum_int8_3[9-1] ? (inv_3[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_3;
assign inv_4 = buf2sum_int8_4[9-1] ? (~buf2sum_int8_4[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_4 = buf2sum_int8_4[9-1] ? (inv_4[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_4;
assign inv_5 = buf2sum_int8_5[9-1] ? (~buf2sum_int8_5[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_5 = buf2sum_int8_5[9-1] ? (inv_5[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_5;
assign inv_6 = buf2sum_int8_6[9-1] ? (~buf2sum_int8_6[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_6 = buf2sum_int8_6[9-1] ? (inv_6[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_6;
assign inv_7 = buf2sum_int8_7[9-1] ? (~buf2sum_int8_7[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_7 = buf2sum_int8_7[9-1] ? (inv_7[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_7;
assign inv_8 = buf2sum_int8_8[9-1] ? (~buf2sum_int8_8[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_8 = buf2sum_int8_8[9-1] ? (inv_8[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_8;
assign inv_9 = buf2sum_int8_9[9-1] ? (~buf2sum_int8_9[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_9 = buf2sum_int8_9[9-1] ? (inv_9[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_9;
assign inv_10 = buf2sum_int8_10[9-1] ? (~buf2sum_int8_10[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_10 = buf2sum_int8_10[9-1] ? (inv_10[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_10;
assign inv_11 = buf2sum_int8_11[9-1] ? (~buf2sum_int8_11[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_11 = buf2sum_int8_11[9-1] ? (inv_11[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_11;
assign inv_12 = buf2sum_int8_12[9-1] ? (~buf2sum_int8_12[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_12 = buf2sum_int8_12[9-1] ? (inv_12[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_12;
assign inv_13 = buf2sum_int8_13[9-1] ? (~buf2sum_int8_13[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_13 = buf2sum_int8_13[9-1] ? (inv_13[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_13;
assign inv_14 = buf2sum_int8_14[9-1] ? (~buf2sum_int8_14[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_14 = buf2sum_int8_14[9-1] ? (inv_14[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_14;
assign inv_15 = buf2sum_int8_15[9-1] ? (~buf2sum_int8_15[9-2:0]) : {(9-1){1'b0}};
assign int8_abs_15 = buf2sum_int8_15[9-1] ? (inv_15[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_15;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
{mon_int8_sq_0,int8_sq_0} <= {(9*2-1){1'b0}};
{mon_int8_sq_1,int8_sq_1} <= {(9*2-1){1'b0}};
{mon_int8_sq_2,int8_sq_2} <= {(9*2-1){1'b0}};
{mon_int8_sq_3,int8_sq_3} <= {(9*2-1){1'b0}};
{mon_int8_sq_4,int8_sq_4} <= {(9*2-1){1'b0}};
{mon_int8_sq_5,int8_sq_5} <= {(9*2-1){1'b0}};
{mon_int8_sq_6,int8_sq_6} <= {(9*2-1){1'b0}};
{mon_int8_sq_7,int8_sq_7} <= {(9*2-1){1'b0}};
{mon_int8_sq_8,int8_sq_8} <= {(9*2-1){1'b0}};
{mon_int8_sq_9,int8_sq_9} <= {(9*2-1){1'b0}};
{mon_int8_sq_10,int8_sq_10} <= {(9*2-1){1'b0}};
{mon_int8_sq_11,int8_sq_11} <= {(9*2-1){1'b0}};
{mon_int8_sq_12,int8_sq_12} <= {(9*2-1){1'b0}};
{mon_int8_sq_13,int8_sq_13} <= {(9*2-1){1'b0}};
{mon_int8_sq_14,int8_sq_14} <= {(9*2-1){1'b0}};
{mon_int8_sq_15,int8_sq_15} <= {(9*2-1){1'b0}};
end else if(load_din) begin
{mon_int8_sq_0,int8_sq_0} <= len9 ? (int8_abs_0 * int8_abs_0) : {(9*2){1'b0}};
{mon_int8_sq_1,int8_sq_1} <= ( len7|len9)? (int8_abs_1 * int8_abs_1) : {(9*2){1'b0}};
{mon_int8_sq_2,int8_sq_2} <= (len5|len7|len9)? (int8_abs_2 * int8_abs_2) : {(9*2){1'b0}};
{mon_int8_sq_3,int8_sq_3} <= (int8_abs_3 * int8_abs_3);
{mon_int8_sq_4,int8_sq_4} <= (int8_abs_4 * int8_abs_4);
{mon_int8_sq_5,int8_sq_5} <= (int8_abs_5 * int8_abs_5);
{mon_int8_sq_6,int8_sq_6} <= (int8_abs_6 * int8_abs_6);
{mon_int8_sq_7,int8_sq_7} <= (int8_abs_7 * int8_abs_7);
{mon_int8_sq_8,int8_sq_8} <= (int8_abs_8 * int8_abs_8);
{mon_int8_sq_9,int8_sq_9} <= (int8_abs_9 * int8_abs_9);
{mon_int8_sq_10,int8_sq_10} <= (int8_abs_10 * int8_abs_10);
{mon_int8_sq_11,int8_sq_11} <= (int8_abs_11 * int8_abs_11);
{mon_int8_sq_12,int8_sq_12} <= (int8_abs_12 * int8_abs_12);
{mon_int8_sq_13,int8_sq_13} <= (len5|len7|len9)? (int8_abs_13 * int8_abs_13) : {(9*2){1'b0}};
{mon_int8_sq_14,int8_sq_14} <= ( len7|len9)? (int8_abs_14 * int8_abs_14) : {(9*2){1'b0}};
{mon_int8_sq_15,int8_sq_15} <= len9 ? (int8_abs_15 * int8_abs_15) : {(9*2){1'b0}};
end
end
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign buf2sum_din_prdy = ~buf2sum_d_vld | buf2sum_d_rdy;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
buf2sum_d_vld <= 1'b0;
end else begin
if(cdp_buf2sum_valid)
buf2sum_d_vld <= 1'b1;
else if(buf2sum_d_rdy)
buf2sum_d_vld <= 1'b0;
end
end
assign buf2sum_d_rdy = ~buf2sum_2d_vld | buf2sum_2d_rdy;
//===========
//sum process
//-----------
assign len3 = (reg2dp_normalz_len[1:0] == 2'h0 );
assign len5 = (reg2dp_normalz_len[1:0] == 2'h1 );
assign len7 = (reg2dp_normalz_len[1:0] == 2'h2 );
assign len9 = (reg2dp_normalz_len[1:0] == 2'h3 );
assign load_din_d = buf2sum_d_vld & buf2sum_d_rdy;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
buf2sum_2d_vld <= 1'b0;
end else begin
if(buf2sum_d_vld)
buf2sum_2d_vld <= 1'b1;
else if(buf2sum_2d_rdy)
buf2sum_2d_vld <= 1'b0;
end
end
assign buf2sum_2d_rdy = ~buf2sum_3d_vld | buf2sum_3d_rdy ;
assign load_din_2d = buf2sum_2d_vld & buf2sum_2d_rdy;
//: my $tp=8;
//: my $icvto=(8 +1);
//: foreach my $i (0..${tp}-1) {
//: print "int_sum_block_tp1 u_sum_block_$i ( \n";
//: print qq(
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.len5 (len5)
//: ,.len7 (len7)
//: ,.len9 (len9)
//: ,.load_din_2d (load_din_2d)
//: ,.load_din_d (load_din_d)
//: ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
//: );
//:
//: foreach my $k (0..8) {
//: my $j = $k + $i;
//: print " ,.sq_pd_int8_${k} (int8_sq_${j}) \n";
//: }
//: print qq(
//: ,.int8_sum (int8_sum_${i})
//: );
//: print " ); \n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
int_sum_block_tp1 u_sum_block_0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_0)
,.sq_pd_int8_1 (int8_sq_1)
,.sq_pd_int8_2 (int8_sq_2)
,.sq_pd_int8_3 (int8_sq_3)
,.sq_pd_int8_4 (int8_sq_4)
,.sq_pd_int8_5 (int8_sq_5)
,.sq_pd_int8_6 (int8_sq_6)
,.sq_pd_int8_7 (int8_sq_7)
,.sq_pd_int8_8 (int8_sq_8)
,.int8_sum (int8_sum_0)
);
int_sum_block_tp1 u_sum_block_1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_1)
,.sq_pd_int8_1 (int8_sq_2)
,.sq_pd_int8_2 (int8_sq_3)
,.sq_pd_int8_3 (int8_sq_4)
,.sq_pd_int8_4 (int8_sq_5)
,.sq_pd_int8_5 (int8_sq_6)
,.sq_pd_int8_6 (int8_sq_7)
,.sq_pd_int8_7 (int8_sq_8)
,.sq_pd_int8_8 (int8_sq_9)
,.int8_sum (int8_sum_1)
);
int_sum_block_tp1 u_sum_block_2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_2)
,.sq_pd_int8_1 (int8_sq_3)
,.sq_pd_int8_2 (int8_sq_4)
,.sq_pd_int8_3 (int8_sq_5)
,.sq_pd_int8_4 (int8_sq_6)
,.sq_pd_int8_5 (int8_sq_7)
,.sq_pd_int8_6 (int8_sq_8)
,.sq_pd_int8_7 (int8_sq_9)
,.sq_pd_int8_8 (int8_sq_10)
,.int8_sum (int8_sum_2)
);
int_sum_block_tp1 u_sum_block_3 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_3)
,.sq_pd_int8_1 (int8_sq_4)
,.sq_pd_int8_2 (int8_sq_5)
,.sq_pd_int8_3 (int8_sq_6)
,.sq_pd_int8_4 (int8_sq_7)
,.sq_pd_int8_5 (int8_sq_8)
,.sq_pd_int8_6 (int8_sq_9)
,.sq_pd_int8_7 (int8_sq_10)
,.sq_pd_int8_8 (int8_sq_11)
,.int8_sum (int8_sum_3)
);
int_sum_block_tp1 u_sum_block_4 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_4)
,.sq_pd_int8_1 (int8_sq_5)
,.sq_pd_int8_2 (int8_sq_6)
,.sq_pd_int8_3 (int8_sq_7)
,.sq_pd_int8_4 (int8_sq_8)
,.sq_pd_int8_5 (int8_sq_9)
,.sq_pd_int8_6 (int8_sq_10)
,.sq_pd_int8_7 (int8_sq_11)
,.sq_pd_int8_8 (int8_sq_12)
,.int8_sum (int8_sum_4)
);
int_sum_block_tp1 u_sum_block_5 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_5)
,.sq_pd_int8_1 (int8_sq_6)
,.sq_pd_int8_2 (int8_sq_7)
,.sq_pd_int8_3 (int8_sq_8)
,.sq_pd_int8_4 (int8_sq_9)
,.sq_pd_int8_5 (int8_sq_10)
,.sq_pd_int8_6 (int8_sq_11)
,.sq_pd_int8_7 (int8_sq_12)
,.sq_pd_int8_8 (int8_sq_13)
,.int8_sum (int8_sum_5)
);
int_sum_block_tp1 u_sum_block_6 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_6)
,.sq_pd_int8_1 (int8_sq_7)
,.sq_pd_int8_2 (int8_sq_8)
,.sq_pd_int8_3 (int8_sq_9)
,.sq_pd_int8_4 (int8_sq_10)
,.sq_pd_int8_5 (int8_sq_11)
,.sq_pd_int8_6 (int8_sq_12)
,.sq_pd_int8_7 (int8_sq_13)
,.sq_pd_int8_8 (int8_sq_14)
,.int8_sum (int8_sum_6)
);
int_sum_block_tp1 u_sum_block_7 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.len5 (len5)
,.len7 (len7)
,.len9 (len9)
,.load_din_2d (load_din_2d)
,.load_din_d (load_din_d)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sq_pd_int8_0 (int8_sq_7)
,.sq_pd_int8_1 (int8_sq_8)
,.sq_pd_int8_2 (int8_sq_9)
,.sq_pd_int8_3 (int8_sq_10)
,.sq_pd_int8_4 (int8_sq_11)
,.sq_pd_int8_5 (int8_sq_12)
,.sq_pd_int8_6 (int8_sq_13)
,.sq_pd_int8_7 (int8_sq_14)
,.sq_pd_int8_8 (int8_sq_15)
,.int8_sum (int8_sum_7)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
buf2sum_3d_vld <= 1'b0;
end else begin
if(buf2sum_2d_vld)
buf2sum_3d_vld <= 1'b1;
else if(buf2sum_3d_rdy)
buf2sum_3d_vld <= 1'b0;
end
end
assign buf2sum_3d_rdy = sum_out_prdy;
//=======================================================
//data output select
//-------------------------------------------------------
assign sum_out_pd = {
//: my $tp=8;
//: if($tp > 1){
//: foreach my $i (0..${tp}-2) {
//: my $j = ${tp} - $i -1;
//: print "int8_sum_${j}, ";
//: }
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
int8_sum_7, int8_sum_6, int8_sum_5, int8_sum_4, int8_sum_3, int8_sum_2, int8_sum_1,
//| eperl: generated_end (DO NOT EDIT ABOVE)
int8_sum_0};
assign sum_out_pvld = buf2sum_3d_vld;
////////////////////////////////////
//assign sum_out_prdy = sum2itp_ready;
////////////////////////////////////
assign sum2itp_valid = sum_out_pvld;
assign sum2itp_data = sum_out_pd;
//=======================================================
////////::pipe -bc -is sum2itp_pd (sum2itp_pvld,sum2itp_prdy) <= sum2itp_data (sum2itp_valid,sum2itp_ready);
//: my $k = 8*21;
//: &eperl::pipe("-wid $k -is -do sum2itp_pd -vo sum2itp_pvld -ri sum2itp_prdy -di sum2itp_data -vi sum2itp_valid -ro sum2itp_ready ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg sum2itp_ready;
reg skid_flop_sum2itp_ready;
reg skid_flop_sum2itp_valid;
reg [168-1:0] skid_flop_sum2itp_data;
reg pipe_skid_sum2itp_valid;
reg [168-1:0] pipe_skid_sum2itp_data;
// Wire
wire skid_sum2itp_valid;
wire [168-1:0] skid_sum2itp_data;
wire skid_sum2itp_ready;
wire pipe_skid_sum2itp_ready;
wire sum2itp_pvld;
wire [168-1:0] sum2itp_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
sum2itp_ready <= 1'b1;
skid_flop_sum2itp_ready <= 1'b1;
end else begin
sum2itp_ready <= skid_sum2itp_ready;
skid_flop_sum2itp_ready <= skid_sum2itp_ready;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_sum2itp_valid <= 1'b0;
end else begin
if (skid_flop_sum2itp_ready) begin
skid_flop_sum2itp_valid <= sum2itp_valid;
end
end
end
assign skid_sum2itp_valid = (skid_flop_sum2itp_ready) ? sum2itp_valid : skid_flop_sum2itp_valid;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_sum2itp_ready & sum2itp_valid) begin
skid_flop_sum2itp_data[168-1:0] <= sum2itp_data[168-1:0];
end
end
assign skid_sum2itp_data[168-1:0] = (skid_flop_sum2itp_ready) ? sum2itp_data[168-1:0] : skid_flop_sum2itp_data[168-1:0];
// PIPE READY
assign skid_sum2itp_ready = pipe_skid_sum2itp_ready || !pipe_skid_sum2itp_valid;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_sum2itp_valid <= 1'b0;
end else begin
if (skid_sum2itp_ready) begin
pipe_skid_sum2itp_valid <= skid_sum2itp_valid;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_sum2itp_ready && skid_sum2itp_valid) begin
pipe_skid_sum2itp_data[168-1:0] <= skid_sum2itp_data[168-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_sum2itp_ready = sum2itp_prdy;
assign sum2itp_pvld = pipe_skid_sum2itp_valid;
assign sum2itp_pd = pipe_skid_sum2itp_data;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign sum_out_prdy = sum2itp_ready;
/////////////////////////////////////////////////////////
endmodule // NV_NVDLA_CDP_DP_sum |
module NV_NVDLA_MCIF_READ_IG_arb (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
//: for (my $i=0;$i<9;$i++) {
//: print(" ,reg2dp_rd_weight${i}\n");
//: }
//: for (my $i=0;$i<9;$i++) {
//: print(" ,bpt2arb_req${i}_valid\n");
//: print(" ,bpt2arb_req${i}_ready\n");
//: print(" ,bpt2arb_req${i}_pd\n");
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,reg2dp_rd_weight0
,reg2dp_rd_weight1
,reg2dp_rd_weight2
,reg2dp_rd_weight3
,reg2dp_rd_weight4
,reg2dp_rd_weight5
,reg2dp_rd_weight6
,reg2dp_rd_weight7
,reg2dp_rd_weight8
,bpt2arb_req0_valid
,bpt2arb_req0_ready
,bpt2arb_req0_pd
,bpt2arb_req1_valid
,bpt2arb_req1_ready
,bpt2arb_req1_pd
,bpt2arb_req2_valid
,bpt2arb_req2_ready
,bpt2arb_req2_pd
,bpt2arb_req3_valid
,bpt2arb_req3_ready
,bpt2arb_req3_pd
,bpt2arb_req4_valid
,bpt2arb_req4_ready
,bpt2arb_req4_pd
,bpt2arb_req5_valid
,bpt2arb_req5_ready
,bpt2arb_req5_pd
,bpt2arb_req6_valid
,bpt2arb_req6_ready
,bpt2arb_req6_pd
,bpt2arb_req7_valid
,bpt2arb_req7_ready
,bpt2arb_req7_pd
,bpt2arb_req8_valid
,bpt2arb_req8_ready
,bpt2arb_req8_pd
//| eperl: generated_end (DO NOT EDIT ABOVE)
,arb2spt_req_pd //|> o
,arb2spt_req_valid //|> o
,arb2spt_req_ready //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
//: for (my $i=0;$i<9;$i++) {
//: print "input [7:0] reg2dp_rd_weight${i};\n";
//: }
//: for (my $i=0;$i<9;$i++) {
//: print qq(
//: input bpt2arb_req${i}_valid;
//: output bpt2arb_req${i}_ready;
//: input [64 +11 -1:0] bpt2arb_req${i}_pd;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [7:0] reg2dp_rd_weight0;
input [7:0] reg2dp_rd_weight1;
input [7:0] reg2dp_rd_weight2;
input [7:0] reg2dp_rd_weight3;
input [7:0] reg2dp_rd_weight4;
input [7:0] reg2dp_rd_weight5;
input [7:0] reg2dp_rd_weight6;
input [7:0] reg2dp_rd_weight7;
input [7:0] reg2dp_rd_weight8;
input bpt2arb_req0_valid;
output bpt2arb_req0_ready;
input [64 +11 -1:0] bpt2arb_req0_pd;
input bpt2arb_req1_valid;
output bpt2arb_req1_ready;
input [64 +11 -1:0] bpt2arb_req1_pd;
input bpt2arb_req2_valid;
output bpt2arb_req2_ready;
input [64 +11 -1:0] bpt2arb_req2_pd;
input bpt2arb_req3_valid;
output bpt2arb_req3_ready;
input [64 +11 -1:0] bpt2arb_req3_pd;
input bpt2arb_req4_valid;
output bpt2arb_req4_ready;
input [64 +11 -1:0] bpt2arb_req4_pd;
input bpt2arb_req5_valid;
output bpt2arb_req5_ready;
input [64 +11 -1:0] bpt2arb_req5_pd;
input bpt2arb_req6_valid;
output bpt2arb_req6_ready;
input [64 +11 -1:0] bpt2arb_req6_pd;
input bpt2arb_req7_valid;
output bpt2arb_req7_ready;
input [64 +11 -1:0] bpt2arb_req7_pd;
input bpt2arb_req8_valid;
output bpt2arb_req8_ready;
input [64 +11 -1:0] bpt2arb_req8_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output arb2spt_req_valid;
input arb2spt_req_ready;
output [64 +11 -1:0] arb2spt_req_pd;
//: for (my $i=0;$i<9;$i++) {
//: print qq(
//: wire [64 +11 -1:0] arb_src${i}_pd;
//: wire arb_src${i}_rdy;
//: wire arb_src${i}_vld;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [64 +11 -1:0] arb_src0_pd;
wire arb_src0_rdy;
wire arb_src0_vld;
wire [64 +11 -1:0] arb_src1_pd;
wire arb_src1_rdy;
wire arb_src1_vld;
wire [64 +11 -1:0] arb_src2_pd;
wire arb_src2_rdy;
wire arb_src2_vld;
wire [64 +11 -1:0] arb_src3_pd;
wire arb_src3_rdy;
wire arb_src3_vld;
wire [64 +11 -1:0] arb_src4_pd;
wire arb_src4_rdy;
wire arb_src4_vld;
wire [64 +11 -1:0] arb_src5_pd;
wire arb_src5_rdy;
wire arb_src5_vld;
wire [64 +11 -1:0] arb_src6_pd;
wire arb_src6_rdy;
wire arb_src6_vld;
wire [64 +11 -1:0] arb_src7_pd;
wire arb_src7_rdy;
wire arb_src7_vld;
wire [64 +11 -1:0] arb_src8_pd;
wire arb_src8_rdy;
wire arb_src8_vld;
//| eperl: generated_end (DO NOT EDIT ABOVE)
reg [64 +11 -1:0] arb_pd;
wire [64 +11 -1:0] arb_out_pd;
wire arb_out_vld;
wire arb_out_rdy;
wire [9:0] arb_gnt;
wire gnt_busy;
wire src0_gnt;
wire src0_req;
wire src1_gnt;
wire src1_req;
wire src2_gnt;
wire src2_req;
wire src3_gnt;
wire src3_req;
wire src4_gnt;
wire src4_req;
wire src5_gnt;
wire src5_req;
wire src6_gnt;
wire src6_req;
wire src7_gnt;
wire src7_req;
wire src8_gnt;
wire src8_req;
wire src9_gnt;
wire src9_req;
wire [7:0] wt0;
wire [7:0] wt1;
wire [7:0] wt2;
wire [7:0] wt3;
wire [7:0] wt4;
wire [7:0] wt5;
wire [7:0] wt6;
wire [7:0] wt7;
wire [7:0] wt8;
wire [7:0] wt9;
//: for (my $i=0;$i<9;$i++) {
//: print qq(
//: NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p${i} (
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.bpt2arb_req_pd (bpt2arb_req${i}_pd)
//: ,.bpt2arb_req_valid (bpt2arb_req${i}_valid)
//: ,.bpt2arb_req_ready (bpt2arb_req${i}_ready)
//: ,.arb_src_pd (arb_src${i}_pd)
//: ,.arb_src_vld (arb_src${i}_vld)
//: ,.arb_src_rdy (arb_src${i}_rdy)
//: );
//: assign src${i}_req = arb_src${i}_vld;
//: assign arb_src${i}_rdy = src${i}_gnt;
//: );
//: }
//: print "\n";
//: for (my $i=9;$i<10;$i++) {
//: print "assign src${i}_req = 1'b0;\n";
//: }
//: for (my $i=0;$i<9;$i++) {
//: print "assign wt${i} = reg2dp_rd_weight${i};\n";
//: }
//: for (my $i=9;$i<10;$i++) {
//: print "assign wt${i} = 8'h0;\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req0_pd)
,.bpt2arb_req_valid (bpt2arb_req0_valid)
,.bpt2arb_req_ready (bpt2arb_req0_ready)
,.arb_src_pd (arb_src0_pd)
,.arb_src_vld (arb_src0_vld)
,.arb_src_rdy (arb_src0_rdy)
);
assign src0_req = arb_src0_vld;
assign arb_src0_rdy = src0_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req1_pd)
,.bpt2arb_req_valid (bpt2arb_req1_valid)
,.bpt2arb_req_ready (bpt2arb_req1_ready)
,.arb_src_pd (arb_src1_pd)
,.arb_src_vld (arb_src1_vld)
,.arb_src_rdy (arb_src1_rdy)
);
assign src1_req = arb_src1_vld;
assign arb_src1_rdy = src1_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req2_pd)
,.bpt2arb_req_valid (bpt2arb_req2_valid)
,.bpt2arb_req_ready (bpt2arb_req2_ready)
,.arb_src_pd (arb_src2_pd)
,.arb_src_vld (arb_src2_vld)
,.arb_src_rdy (arb_src2_rdy)
);
assign src2_req = arb_src2_vld;
assign arb_src2_rdy = src2_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p3 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req3_pd)
,.bpt2arb_req_valid (bpt2arb_req3_valid)
,.bpt2arb_req_ready (bpt2arb_req3_ready)
,.arb_src_pd (arb_src3_pd)
,.arb_src_vld (arb_src3_vld)
,.arb_src_rdy (arb_src3_rdy)
);
assign src3_req = arb_src3_vld;
assign arb_src3_rdy = src3_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p4 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req4_pd)
,.bpt2arb_req_valid (bpt2arb_req4_valid)
,.bpt2arb_req_ready (bpt2arb_req4_ready)
,.arb_src_pd (arb_src4_pd)
,.arb_src_vld (arb_src4_vld)
,.arb_src_rdy (arb_src4_rdy)
);
assign src4_req = arb_src4_vld;
assign arb_src4_rdy = src4_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p5 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req5_pd)
,.bpt2arb_req_valid (bpt2arb_req5_valid)
,.bpt2arb_req_ready (bpt2arb_req5_ready)
,.arb_src_pd (arb_src5_pd)
,.arb_src_vld (arb_src5_vld)
,.arb_src_rdy (arb_src5_rdy)
);
assign src5_req = arb_src5_vld;
assign arb_src5_rdy = src5_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p6 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req6_pd)
,.bpt2arb_req_valid (bpt2arb_req6_valid)
,.bpt2arb_req_ready (bpt2arb_req6_ready)
,.arb_src_pd (arb_src6_pd)
,.arb_src_vld (arb_src6_vld)
,.arb_src_rdy (arb_src6_rdy)
);
assign src6_req = arb_src6_vld;
assign arb_src6_rdy = src6_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p7 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req7_pd)
,.bpt2arb_req_valid (bpt2arb_req7_valid)
,.bpt2arb_req_ready (bpt2arb_req7_ready)
,.arb_src_pd (arb_src7_pd)
,.arb_src_vld (arb_src7_vld)
,.arb_src_rdy (arb_src7_rdy)
);
assign src7_req = arb_src7_vld;
assign arb_src7_rdy = src7_gnt;
NV_NVDLA_MCIF_READ_IG_ARB_pipe pipe_p8 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.bpt2arb_req_pd (bpt2arb_req8_pd)
,.bpt2arb_req_valid (bpt2arb_req8_valid)
,.bpt2arb_req_ready (bpt2arb_req8_ready)
,.arb_src_pd (arb_src8_pd)
,.arb_src_vld (arb_src8_vld)
,.arb_src_rdy (arb_src8_rdy)
);
assign src8_req = arb_src8_vld;
assign arb_src8_rdy = src8_gnt;
assign src9_req = 1'b0;
assign wt0 = reg2dp_rd_weight0;
assign wt1 = reg2dp_rd_weight1;
assign wt2 = reg2dp_rd_weight2;
assign wt3 = reg2dp_rd_weight3;
assign wt4 = reg2dp_rd_weight4;
assign wt5 = reg2dp_rd_weight5;
assign wt6 = reg2dp_rd_weight6;
assign wt7 = reg2dp_rd_weight7;
assign wt8 = reg2dp_rd_weight8;
assign wt9 = 8'h0;
//| eperl: generated_end (DO NOT EDIT ABOVE)
read_ig_arb u_read_ig_arb (
.req0 (src0_req) //|< w
,.req1 (src1_req) //|< w
,.req2 (src2_req) //|< w
,.req3 (src3_req) //|< w
,.req4 (src4_req) //|< w
,.req5 (src5_req) //|< w
,.req6 (src6_req) //|< w
,.req7 (src7_req) //|< w
,.req8 (src8_req) //|< w
,.req9 (src9_req) //|< w
,.wt0 (wt0[7:0]) //|< w
,.wt1 (wt1[7:0]) //|< w
,.wt2 (wt2[7:0]) //|< w
,.wt3 (wt3[7:0]) //|< w
,.wt4 (wt4[7:0]) //|< w
,.wt5 (wt5[7:0]) //|< w
,.wt6 (wt6[7:0]) //|< w
,.wt7 (wt7[7:0]) //|< w
,.wt8 (wt8[7:0]) //|< w
,.wt9 (wt9[7:0]) //|< w
,.gnt_busy (gnt_busy) //|< w
,.clk (nvdla_core_clk) //|< i
,.reset_ (nvdla_core_rstn) //|< i
,.gnt0 (src0_gnt) //|> w
,.gnt1 (src1_gnt) //|> w
,.gnt2 (src2_gnt) //|> w
,.gnt3 (src3_gnt) //|> w
,.gnt4 (src4_gnt) //|> w
,.gnt5 (src5_gnt) //|> w
,.gnt6 (src6_gnt) //|> w
,.gnt7 (src7_gnt) //|> w
,.gnt8 (src8_gnt) //|> w
,.gnt9 (src9_gnt) //|> w
);
// MUX OUT
always @(
src0_gnt
or arb_src0_pd
//: for (my $i=1;$i<9;$i++) {
//: print " or src${i}_gnt \n";
//: print " or arb_src${i}_pd\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
or src1_gnt
or arb_src1_pd
or src2_gnt
or arb_src2_pd
or src3_gnt
or arb_src3_pd
or src4_gnt
or arb_src4_pd
or src5_gnt
or arb_src5_pd
or src6_gnt
or arb_src6_pd
or src7_gnt
or arb_src7_pd
or src8_gnt
or arb_src8_pd
//| eperl: generated_end (DO NOT EDIT ABOVE)
) begin
//spyglass disable_block W171 W226
case (1'b1 )
src0_gnt: arb_pd = arb_src0_pd;
//: for (my $i=1;$i<9;$i++) {
//: print" src${i}_gnt: arb_pd = arb_src${i}_pd;\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
src1_gnt: arb_pd = arb_src1_pd;
src2_gnt: arb_pd = arb_src2_pd;
src3_gnt: arb_pd = arb_src3_pd;
src4_gnt: arb_pd = arb_src4_pd;
src5_gnt: arb_pd = arb_src5_pd;
src6_gnt: arb_pd = arb_src6_pd;
src7_gnt: arb_pd = arb_src7_pd;
src8_gnt: arb_pd = arb_src8_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
default : begin
arb_pd[64 +11 -1:0] = {64 +11{`x_or_0}};
end
endcase
//spyglass enable_block W171 W226
end
assign arb_gnt = {src9_gnt, src8_gnt, src7_gnt, src6_gnt, src5_gnt, src4_gnt, src3_gnt, src2_gnt, src1_gnt, src0_gnt};
assign arb_out_vld = |arb_gnt;
assign gnt_busy = !arb_out_rdy;
assign arb_out_pd = arb_pd;
NV_NVDLA_MCIF_READ_IG_ARB_pipe_out pipe_out (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.arb_out_pd (arb_out_pd)
,.arb_out_vld (arb_out_vld)
,.arb_out_rdy (arb_out_rdy)
,.arb2spt_req_pd (arb2spt_req_pd)
,.arb2spt_req_valid (arb2spt_req_valid)
,.arb2spt_req_ready (arb2spt_req_ready)
);
endmodule // NV_NVDLA_MCIF_READ_IG_arb |
module NV_NVDLA_partition_p (
cacc2sdp_pd //|< i
,cacc2sdp_valid //|< i
,csb2sdp_rdma_req_pd //|< i
,csb2sdp_rdma_req_pvld //|< i
,csb2sdp_req_pd //|< i
,csb2sdp_req_pvld //|< i
,direct_reset_ //|< i
,dla_reset_rstn //|< i
,global_clk_ovr_on //|< i
,nvdla_clk_ovr_on //|< i
,nvdla_core_clk //|< i
,pwrbus_ram_pd //|< i
,sdp_b2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2cvif_rd_req_pd //|> o
,sdp_b2cvif_rd_req_valid //|> o
,sdp_b2cvif_rd_req_ready //|< i
,cvif2sdp_b_rd_rsp_pd //|< i
,cvif2sdp_b_rd_rsp_valid //|< i
,cvif2sdp_b_rd_rsp_ready //|> o
,sdp_e2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2cvif_rd_req_pd //|> o
,sdp_e2cvif_rd_req_valid //|> o
,sdp_e2cvif_rd_req_ready //|< i
,cvif2sdp_e_rd_rsp_pd //|< i
,cvif2sdp_e_rd_rsp_valid //|< i
,cvif2sdp_e_rd_rsp_ready //|> o
,sdp_n2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2cvif_rd_req_pd //|> o
,sdp_n2cvif_rd_req_valid //|> o
,sdp_n2cvif_rd_req_ready //|< i
,cvif2sdp_n_rd_rsp_pd //|< i
,cvif2sdp_n_rd_rsp_valid //|< i
,cvif2sdp_n_rd_rsp_ready //|> o
,cvif2sdp_rd_rsp_pd //|< i
,cvif2sdp_rd_rsp_valid //|< i
,cvif2sdp_rd_rsp_ready //|> o
,sdp2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp2cvif_rd_req_pd //|> o
,sdp2cvif_rd_req_valid //|> o
,sdp2cvif_rd_req_ready //|< i
,sdp2cvif_wr_req_pd //|> o
,sdp2cvif_wr_req_valid //|> o
,sdp2cvif_wr_req_ready //|< i
,cvif2sdp_wr_rsp_complete //|< i
,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2mcif_rd_req_pd //|> o
,sdp_b2mcif_rd_req_valid //|> o
,sdp_b2mcif_rd_req_ready //|< i
,mcif2sdp_b_rd_rsp_pd //|< i
,mcif2sdp_b_rd_rsp_valid //|< i
,mcif2sdp_b_rd_rsp_ready //|> o
,sdp_e2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2mcif_rd_req_pd //|> o
,sdp_e2mcif_rd_req_valid //|> o
,sdp_e2mcif_rd_req_ready //|< i
,mcif2sdp_e_rd_rsp_pd //|< i
,mcif2sdp_e_rd_rsp_valid //|< i
,mcif2sdp_e_rd_rsp_ready //|> o
,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2mcif_rd_req_pd //|> o
,sdp_n2mcif_rd_req_valid //|> o
,sdp_n2mcif_rd_req_ready //|< i
,mcif2sdp_n_rd_rsp_pd //|< i
,mcif2sdp_n_rd_rsp_valid //|< i
,mcif2sdp_n_rd_rsp_ready //|> o
,mcif2sdp_rd_rsp_pd //|< i
,mcif2sdp_rd_rsp_valid //|< i
,mcif2sdp_wr_rsp_complete //|< i
,sdp2mcif_rd_req_ready //|< i
,sdp2mcif_wr_req_ready //|< i
,mcif2sdp_rd_rsp_ready //|> o
,sdp2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp2mcif_rd_req_pd //|> o
,sdp2mcif_rd_req_valid //|> o
,sdp2mcif_wr_req_pd //|> o
,sdp2mcif_wr_req_valid //|> o
,sdp2pdp_ready //|< i
,test_mode //|< i
,tmc2slcg_disable_clock_gating //|< i
,cacc2sdp_ready //|> o
,csb2sdp_rdma_req_prdy //|> o
,csb2sdp_req_prdy //|> o
,sdp2csb_resp_pd //|> o
,sdp2csb_resp_valid //|> o
,sdp2glb_done_intr_pd //|> o
,sdp2pdp_pd //|> o
,sdp2pdp_valid //|> o
,sdp_rdma2csb_resp_pd //|> o
,sdp_rdma2csb_resp_valid //|> o
,cacc2sdp_adpt_valid
,cacc2sdp_adpt_ready
,cacc2sdp_adpt_pd
,sdp_dp2wdma_valid
,sdp_dp2wdma_ready
,sdp_dp2wdma_pd
);
//
// NV_NVDLA_partition_p_io.v
//
input test_mode;
input direct_reset_;
input global_clk_ovr_on;
input tmc2slcg_disable_clock_gating;
input cacc2sdp_valid; /* data valid */
output cacc2sdp_ready; /* data return handshake */
input [16*32+2-1:0] cacc2sdp_pd;
input csb2sdp_rdma_req_pvld; /* data valid */
output csb2sdp_rdma_req_prdy; /* data return handshake */
input [62:0] csb2sdp_rdma_req_pd;
input csb2sdp_req_pvld; /* data valid */
output csb2sdp_req_prdy; /* data return handshake */
input [62:0] csb2sdp_req_pd;
input [31:0] pwrbus_ram_pd;
output sdp2csb_resp_valid; /* data valid */
output [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
output sdp_b2cvif_rd_cdt_lat_fifo_pop;
output sdp_b2cvif_rd_req_valid; /* data valid */
input sdp_b2cvif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_b2cvif_rd_req_pd;
input cvif2sdp_b_rd_rsp_valid; /* data valid */
output cvif2sdp_b_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] cvif2sdp_b_rd_rsp_pd;
output sdp_e2cvif_rd_cdt_lat_fifo_pop;
output sdp_e2cvif_rd_req_valid; /* data valid */
input sdp_e2cvif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_e2cvif_rd_req_pd;
input cvif2sdp_e_rd_rsp_valid; /* data valid */
output cvif2sdp_e_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] cvif2sdp_e_rd_rsp_pd;
output sdp_n2cvif_rd_cdt_lat_fifo_pop;
output sdp_n2cvif_rd_req_valid; /* data valid */
input sdp_n2cvif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_n2cvif_rd_req_pd;
input cvif2sdp_n_rd_rsp_valid; /* data valid */
output cvif2sdp_n_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] cvif2sdp_n_rd_rsp_pd;
input cvif2sdp_rd_rsp_valid; /* data valid */
output cvif2sdp_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] cvif2sdp_rd_rsp_pd;
output sdp2cvif_rd_cdt_lat_fifo_pop;
output sdp2cvif_rd_req_valid; /* data valid */
input sdp2cvif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp2cvif_rd_req_pd;
output sdp2cvif_wr_req_valid; /* data valid */
input sdp2cvif_wr_req_ready; /* data return handshake */
output [256 +(256/8/32):0] sdp2cvif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */
input cvif2sdp_wr_rsp_complete;
output [1:0] sdp2glb_done_intr_pd;
output sdp_b2mcif_rd_cdt_lat_fifo_pop;
output sdp_b2mcif_rd_req_valid; /* data valid */
input sdp_b2mcif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_b2mcif_rd_req_pd;
input mcif2sdp_b_rd_rsp_valid; /* data valid */
output mcif2sdp_b_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] mcif2sdp_b_rd_rsp_pd;
output sdp_e2mcif_rd_cdt_lat_fifo_pop;
output sdp_e2mcif_rd_req_valid; /* data valid */
input sdp_e2mcif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_e2mcif_rd_req_pd;
input mcif2sdp_e_rd_rsp_valid; /* data valid */
output mcif2sdp_e_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] mcif2sdp_e_rd_rsp_pd;
output sdp_n2mcif_rd_cdt_lat_fifo_pop;
output sdp_n2mcif_rd_req_valid; /* data valid */
input sdp_n2mcif_rd_req_ready; /* data return handshake */
output [64 +14:0] sdp_n2mcif_rd_req_pd;
input mcif2sdp_n_rd_rsp_valid; /* data valid */
output mcif2sdp_n_rd_rsp_ready; /* data return handshake */
input [256 +(256/8/32)-1:0] mcif2sdp_n_rd_rsp_pd;
output sdp2mcif_rd_cdt_lat_fifo_pop;
input mcif2sdp_rd_rsp_valid;
output mcif2sdp_rd_rsp_ready;
input [256 +(256/8/32)-1:0] mcif2sdp_rd_rsp_pd;
output sdp2mcif_rd_req_valid;
input sdp2mcif_rd_req_ready;
output [64 +14:0] sdp2mcif_rd_req_pd;
output sdp2mcif_wr_req_valid;
input sdp2mcif_wr_req_ready;
output [256 +(256/8/32):0] sdp2mcif_wr_req_pd;
input mcif2sdp_wr_rsp_complete;
output sdp2pdp_valid;
input sdp2pdp_ready;
output [16*8 -1:0] sdp2pdp_pd;
output sdp_rdma2csb_resp_valid;
output [33:0] sdp_rdma2csb_resp_pd;
//input la_r_clk;
//input larstn;
input nvdla_core_clk;
input dla_reset_rstn;
input nvdla_clk_ovr_on;
//for debug
/////////////////////////////////////////////
output cacc2sdp_adpt_valid;
output cacc2sdp_adpt_ready;
output [32*16 +1:0] cacc2sdp_adpt_pd;
output sdp_dp2wdma_valid;
output sdp_dp2wdma_ready;
output [32*8 -1:0] sdp_dp2wdma_pd;
/////////////////////////////////////////////
wire dla_clk_ovr_on_sync;
wire global_clk_ovr_on_sync;
wire nvdla_core_rstn;
////////////////////////////////////////////////////////////////////////
// NVDLA Partition P: Reset Syncer //
////////////////////////////////////////////////////////////////////////
NV_NVDLA_reset u_partition_p_reset (
.dla_reset_rstn (dla_reset_rstn)
,.direct_reset_ (direct_reset_)
,.test_mode (test_mode)
,.synced_rstn (nvdla_core_rstn)
,.nvdla_clk (nvdla_core_clk)
);
////////////////////////////////////////////////////////////////////////
// Sync for SLCG
////////////////////////////////////////////////////////////////////////
NV_NVDLA_sync3d u_dla_clk_ovr_on_sync (
.clk (nvdla_core_clk)
,.sync_i (nvdla_clk_ovr_on)
,.sync_o (dla_clk_ovr_on_sync)
);
NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (
.clk (nvdla_core_clk)
,.prst (nvdla_core_rstn)
,.sync_i (global_clk_ovr_on)
,.sync_o (global_clk_ovr_on_sync)
);
////////////////////////////////////////////////////////////////////////
// NVDLA Partition P: Single Data Processor //
////////////////////////////////////////////////////////////////////////
NV_NVDLA_sdp u_NV_NVDLA_sdp (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cacc2sdp_valid (cacc2sdp_valid)
,.cacc2sdp_ready (cacc2sdp_ready)
,.cacc2sdp_pd (cacc2sdp_pd)
,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld)
,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy)
,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd)
,.csb2sdp_req_pvld (csb2sdp_req_pvld)
,.csb2sdp_req_prdy (csb2sdp_req_prdy)
,.csb2sdp_req_pd (csb2sdp_req_pd)
,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop)
,.sdp_b2cvif_rd_req_valid (sdp_b2cvif_rd_req_valid)
,.sdp_b2cvif_rd_req_ready (sdp_b2cvif_rd_req_ready)
,.sdp_b2cvif_rd_req_pd (sdp_b2cvif_rd_req_pd )
,.cvif2sdp_b_rd_rsp_valid (cvif2sdp_b_rd_rsp_valid)
,.cvif2sdp_b_rd_rsp_ready (cvif2sdp_b_rd_rsp_ready)
,.cvif2sdp_b_rd_rsp_pd (cvif2sdp_b_rd_rsp_pd )
,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
,.sdp_e2cvif_rd_req_valid (sdp_e2cvif_rd_req_valid)
,.sdp_e2cvif_rd_req_ready (sdp_e2cvif_rd_req_ready)
,.sdp_e2cvif_rd_req_pd (sdp_e2cvif_rd_req_pd )
,.cvif2sdp_e_rd_rsp_valid (cvif2sdp_e_rd_rsp_valid)
,.cvif2sdp_e_rd_rsp_ready (cvif2sdp_e_rd_rsp_ready)
,.cvif2sdp_e_rd_rsp_pd (cvif2sdp_e_rd_rsp_pd )
,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop)
,.sdp_n2cvif_rd_req_valid (sdp_n2cvif_rd_req_valid)
,.sdp_n2cvif_rd_req_ready (sdp_n2cvif_rd_req_ready)
,.sdp_n2cvif_rd_req_pd (sdp_n2cvif_rd_req_pd )
,.cvif2sdp_n_rd_rsp_valid (cvif2sdp_n_rd_rsp_valid)
,.cvif2sdp_n_rd_rsp_ready (cvif2sdp_n_rd_rsp_ready)
,.cvif2sdp_n_rd_rsp_pd (cvif2sdp_n_rd_rsp_pd )
,.cvif2sdp_rd_rsp_valid (cvif2sdp_rd_rsp_valid)
,.cvif2sdp_rd_rsp_ready (cvif2sdp_rd_rsp_ready)
,.cvif2sdp_rd_rsp_pd (cvif2sdp_rd_rsp_pd )
,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp2cvif_rd_cdt_lat_fifo_pop)
,.sdp2cvif_rd_req_valid (sdp2cvif_rd_req_valid)
,.sdp2cvif_rd_req_ready (sdp2cvif_rd_req_ready)
,.sdp2cvif_rd_req_pd (sdp2cvif_rd_req_pd )
,.sdp2cvif_wr_req_valid (sdp2cvif_wr_req_valid)
,.sdp2cvif_wr_req_ready (sdp2cvif_wr_req_ready)
,.sdp2cvif_wr_req_pd (sdp2cvif_wr_req_pd )
,.cvif2sdp_wr_rsp_complete (cvif2sdp_wr_rsp_complete)
,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid)
,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready)
,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd)
,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid)
,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready)
,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd)
,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid)
,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready)
,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd)
,.mcif2sdp_e_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid)
,.mcif2sdp_e_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready)
,.mcif2sdp_e_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd)
,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid)
,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready)
,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd)
,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid)
,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready)
,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd)
,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid)
,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready)
,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd)
,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.sdp2csb_resp_valid (sdp2csb_resp_valid)
,.sdp2csb_resp_pd (sdp2csb_resp_pd)
,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd)
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid)
,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready)
,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd)
,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid)
,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready)
,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd)
,.sdp2pdp_valid (sdp2pdp_valid)
,.sdp2pdp_ready (sdp2pdp_ready)
,.sdp2pdp_pd (sdp2pdp_pd)
,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid)
,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd)
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
,.cacc2sdp_adpt_valid(cacc2sdp_adpt_valid)
,.cacc2sdp_adpt_ready(cacc2sdp_adpt_ready)
,.cacc2sdp_adpt_pd (cacc2sdp_adpt_pd)
,.sdp_dp2wdma_ready (sdp_dp2wdma_ready)
,.sdp_dp2wdma_valid (sdp_dp2wdma_valid)
,.sdp_dp2wdma_pd (sdp_dp2wdma_pd)
);
////////////////////////////////////////////////////////////////////////
// Dangles/Contenders report //
////////////////////////////////////////////////////////////////////////
endmodule // NV_NVDLA_partition_p |
module NV_NVDLA_SDP_brdma (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,brdma_disable //|< i
,brdma_slcg_op_en //|< i
,sdp_b2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2cvif_rd_req_pd //|> o
,sdp_b2cvif_rd_req_valid //|> o
,sdp_b2cvif_rd_req_ready //|< i
,cvif2sdp_b_rd_rsp_pd //|< i
,cvif2sdp_b_rd_rsp_valid //|< i
,cvif2sdp_b_rd_rsp_ready //|> o
,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2mcif_rd_req_pd //|> o
,sdp_b2mcif_rd_req_valid //|> o
,sdp_b2mcif_rd_req_ready //|< i
,mcif2sdp_b_rd_rsp_pd //|< i
,mcif2sdp_b_rd_rsp_valid //|< i
,mcif2sdp_b_rd_rsp_ready //|> o
,reg2dp_brdma_data_mode //|< i
,reg2dp_brdma_data_size //|< i
,reg2dp_brdma_data_use //|< i
,reg2dp_brdma_ram_type //|< i
,reg2dp_bs_base_addr_high //|< i
,reg2dp_bs_base_addr_low //|< i
,reg2dp_bs_line_stride //|< i
,reg2dp_bs_surface_stride //|< i
,reg2dp_batch_number //|< i
,reg2dp_channel //|< i
,reg2dp_height //|< i
,reg2dp_width //|< i
,reg2dp_op_en //|< i
,reg2dp_out_precision //|< i
,reg2dp_perf_dma_en //|< i
,reg2dp_proc_precision //|< i
,reg2dp_winograd //|< i
,dp2reg_brdma_stall //|> o
,dp2reg_done //|> o
,sdp_brdma2dp_alu_ready //|< i
,sdp_brdma2dp_mul_ready //|< i
,sdp_brdma2dp_alu_pd //|> o
,sdp_brdma2dp_alu_valid //|> o
,sdp_brdma2dp_mul_pd //|> o
,sdp_brdma2dp_mul_valid //|> o
);
//
// NV_NVDLA_SDP_brdma_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
output sdp_b2cvif_rd_req_valid;
input sdp_b2cvif_rd_req_ready;
output [79 -1:0] sdp_b2cvif_rd_req_pd;
input cvif2sdp_b_rd_rsp_valid;
output cvif2sdp_b_rd_rsp_ready;
input [257 -1:0] cvif2sdp_b_rd_rsp_pd;
output sdp_b2cvif_rd_cdt_lat_fifo_pop;
output sdp_b2mcif_rd_req_valid;
input sdp_b2mcif_rd_req_ready;
output [79 -1:0] sdp_b2mcif_rd_req_pd;
input mcif2sdp_b_rd_rsp_valid;
output mcif2sdp_b_rd_rsp_ready;
input [257 -1:0] mcif2sdp_b_rd_rsp_pd;
output sdp_b2mcif_rd_cdt_lat_fifo_pop;
output sdp_brdma2dp_alu_valid;
input sdp_brdma2dp_alu_ready;
output [32*16:0] sdp_brdma2dp_alu_pd;
output sdp_brdma2dp_mul_valid;
input sdp_brdma2dp_mul_ready;
output [32*16:0] sdp_brdma2dp_mul_pd;
input reg2dp_brdma_data_mode;
input reg2dp_brdma_data_size;
input [1:0] reg2dp_brdma_data_use;
input reg2dp_brdma_ram_type;
input [31:0] reg2dp_bs_base_addr_high;
input [31-5:0] reg2dp_bs_base_addr_low;
input [31-5:0] reg2dp_bs_line_stride;
input [31-5:0] reg2dp_bs_surface_stride;
input [4:0] reg2dp_batch_number;
input [12:0] reg2dp_channel;
input [12:0] reg2dp_height;
input reg2dp_op_en;
input [1:0] reg2dp_out_precision;
input reg2dp_perf_dma_en;
input [1:0] reg2dp_proc_precision;
input [12:0] reg2dp_width;
input reg2dp_winograd;
output [31:0] dp2reg_brdma_stall;
output dp2reg_done;
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
input brdma_slcg_op_en;
input brdma_disable;
wire nvdla_gated_clk;
wire op_load;
wire eg_done;
reg layer_process;
wire [15:0] ig2cq_pd;
wire ig2cq_prdy;
wire ig2cq_pvld;
wire [15:0] cq2eg_pd;
wire cq2eg_prdy;
wire cq2eg_pvld;
wire dma_rd_cdt_lat_fifo_pop;
wire [79 -1:0] dma_rd_req_pd;
wire dma_rd_req_rdy;
wire dma_rd_req_vld;
wire [257 -1:0] dma_rd_rsp_pd;
wire dma_rd_rsp_rdy;
wire dma_rd_rsp_vld;
wire [257 -1:0] lat_fifo_rd_pd;
wire lat_fifo_rd_pvld;
wire lat_fifo_rd_prdy;
// Layer Switch
assign op_load = reg2dp_op_en & !layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
layer_process <= 1'b0;
end else begin
if (op_load) begin
layer_process <= 1'b1;
end else if (eg_done) begin
layer_process <= 1'b0;
end
end
end
assign dp2reg_done = eg_done;
//=======================================
NV_NVDLA_SDP_BRDMA_gate u_gate (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.brdma_disable (brdma_disable) //|< i
,.brdma_slcg_op_en (brdma_slcg_op_en) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_gated_clk (nvdla_gated_clk) //|> w
);
NV_NVDLA_SDP_RDMA_ig u_ig (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.op_load (op_load) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|> w
,.ig2cq_prdy (ig2cq_prdy) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|> w
,.dma_rd_req_vld (dma_rd_req_vld) //|> w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w
,.reg2dp_op_en (reg2dp_op_en) //|< i
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i
,.reg2dp_winograd (reg2dp_winograd) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i
,.reg2dp_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< i
,.reg2dp_base_addr_low (reg2dp_bs_base_addr_low[31-5:0]) //|< i
,.reg2dp_line_stride (reg2dp_bs_line_stride[31-5:0]) //|< i
,.reg2dp_surface_stride (reg2dp_bs_surface_stride[31-5:0]) //|< i
,.dp2reg_rdma_stall (dp2reg_brdma_stall[31:0]) //|> o
);
//: my $depth = 256;
//: my $width = 16;
//: print "NV_NVDLA_SDP_BRDMA_cq_${depth}x${width} u_cq ( \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_BRDMA_cq_256x16 u_cq (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.ig2cq_prdy (ig2cq_prdy) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|> w
);
NV_NVDLA_SDP_RDMA_eg u_eg (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.op_load (op_load) //|< w
,.eg_done (eg_done) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|> w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w
,.lat_fifo_rd_pd (lat_fifo_rd_pd[257 -1:0]) //|< w
,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w
,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w
,.sdp_rdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i
,.sdp_rdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i
,.sdp_rdma2dp_alu_pd (sdp_brdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_rdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o
,.sdp_rdma2dp_mul_pd (sdp_brdma2dp_mul_pd[32*16:0]) //|> o
,.sdp_rdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i
);
//: my $depth = 256;
//: my $width = 257;
//: print "NV_NVDLA_SDP_BRDMA_lat_fifo_${depth}x${width} u_lat_fifo (\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_BRDMA_lat_fifo_256x257 u_lat_fifo (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
,.lat_wr_prdy (dma_rd_rsp_rdy)
,.lat_wr_pvld (dma_rd_rsp_vld)
,.lat_wr_pd (dma_rd_rsp_pd[257 -1:0])
,.lat_rd_prdy (lat_fifo_rd_prdy)
,.lat_rd_pvld (lat_fifo_rd_pvld)
,.lat_rd_pd (lat_fifo_rd_pd[257 -1:0])
);
NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif (
.nvdla_core_clk (nvdla_gated_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2cvif_rd_req_pd (sdp_b2cvif_rd_req_pd[79 -1:0]) //|> o
,.sdp2cvif_rd_req_valid (sdp_b2cvif_rd_req_valid) //|> o
,.sdp2cvif_rd_req_ready (sdp_b2cvif_rd_req_ready) //|< i
,.cvif2sdp_rd_rsp_pd (cvif2sdp_b_rd_rsp_pd[257 -1:0]) //|< i
,.cvif2sdp_rd_rsp_valid (cvif2sdp_b_rd_rsp_valid) //|< i
,.cvif2sdp_rd_rsp_ready (cvif2sdp_b_rd_rsp_ready) //|> o
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[79 -1:0]) //|> o
,.sdp2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o
,.sdp2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i
,.mcif2sdp_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[257 -1:0]) //|< i
,.mcif2sdp_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i
,.mcif2sdp_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o
,.dma_rd_req_ram_type (reg2dp_brdma_ram_type) //|< w
,.dma_rd_rsp_ram_type (reg2dp_brdma_ram_type) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|< w
,.dma_rd_req_vld (dma_rd_req_vld) //|< w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w
,.dma_rd_rsp_pd (dma_rd_rsp_pd[257 -1:0]) //|> w
,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w
,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w
);
endmodule // NV_NVDLA_SDP_brdma |
module NV_NVDLA_MCIF_READ_IG_bpt (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,dma2bpt_cdt_lat_fifo_pop //|< i
,dma2bpt_req_pd //|< i
,dma2bpt_req_valid //|< i
,dma2bpt_req_ready //|> o
,bpt2arb_req_pd //|> o
,bpt2arb_req_valid //|> o
,bpt2arb_req_ready //|< i
,tieoff_axid //|< i
,tieoff_lat_fifo_depth //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
input dma2bpt_req_valid;
output dma2bpt_req_ready;
input [79 -1:0] dma2bpt_req_pd;
input dma2bpt_cdt_lat_fifo_pop;
output bpt2arb_req_valid;
input bpt2arb_req_ready;
output [64 +11 -1:0] bpt2arb_req_pd;
input [3:0] tieoff_axid;
input [8:0] tieoff_lat_fifo_depth;
reg [15 -1:0] count_req;
reg [15 -1:0] req_num;
wire lat_fifo_stall_enable;
reg lat_adv;
reg [10:0] lat_cnt_ext;
reg [10:0] lat_cnt_mod;
reg [10:0] lat_cnt_new;
reg [10:0] lat_cnt_nxt;
reg [8:0] lat_cnt_cur;
reg [8:0] lat_count_cnt;
reg [0:0] lat_count_dec;
wire [3:0] lat_count_inc;
wire [8:0] lat_fifo_free_slot;
wire mon_lat_fifo_free_slot_c;
reg [64 -1:0] out_addr;
wire [2:0] out_size;
reg [2:0] out_size_tmp;
wire [1:0] beat_size;
wire bpt2arb_accept;
wire [64 -1:0] bpt2arb_addr;
wire [3:0] bpt2arb_axid;
wire bpt2arb_ftran;
wire bpt2arb_ltran;
wire bpt2arb_odd;
wire [2:0] bpt2arb_size;
wire bpt2arb_swizzle;
wire [3 -1:0] stt_offset;
wire [3 -1:0] end_offset;
wire [3 -1:0] size_offset;
wire [3 -1:0] ftran_size_tmp;
wire [3 -1:0] ltran_size_tmp;
wire mon_end_offset_c;
wire [2:0] ftran_size;
wire [2:0] ltran_size;
wire [15 -1:0] mtran_num;
wire [64 -1:0] in_addr;
wire [79 -1:0] in_pd;
wire [79 -1:0] in_pd_p;
wire in_rdy;
wire in_rdy_p;
wire [15 -1:0] in_size;
wire in_vld;
wire in_vld_p;
wire [79 -1:0] in_vld_pd;
wire is_ftran;
wire is_ltran;
wire is_mtran;
wire is_single_tran;
wire mon_out_beats_c;
wire out_inc;
wire out_odd;
wire out_swizzle;
wire req_enable;
wire req_rdy;
wire req_vld;
NV_NVDLA_MCIF_READ_IG_BPT_pipe_p1 pipe_p1 (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.dma2bpt_req_pd (dma2bpt_req_pd) //|< i
,.dma2bpt_req_valid (dma2bpt_req_valid) //|< i
,.dma2bpt_req_ready (dma2bpt_req_ready) //|> o
,.in_pd_p (in_pd_p) //|> w
,.in_vld_p (in_vld_p) //|> w
,.in_rdy_p (in_rdy_p) //|< w
);
NV_NVDLA_MCIF_READ_IG_BPT_pipe_p2 pipe_p2 (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.in_pd_p (in_pd_p) //|< w
,.in_vld_p (in_vld_p) //|< w
,.in_rdy_p (in_rdy_p) //|> w
,.in_pd (in_pd) //|> w
,.in_vld (in_vld) //|> w
,.in_rdy (in_rdy) //|< w
);
assign in_rdy = req_rdy & is_ltran;
assign in_vld_pd = {79{in_vld}} & in_pd;
assign in_addr[64 -1:0] = in_vld_pd[64 -1:0];
assign in_size[15 -1:0] = in_vld_pd[79 -1:64];
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass disable_block NoWidthInBasedNum-ML
// spyglass disable_block STARC-2.10.3.2a
// spyglass disable_block STARC05-2.1.3.1
// spyglass disable_block STARC-2.1.4.6
// spyglass disable_block W116
// spyglass disable_block W154
// spyglass disable_block W239
// spyglass disable_block W362
// spyglass disable_block WRN_58
// spyglass disable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif // ASSERT_OFF_RESET_IS_X
`endif // SYNTHESIS
`endif // FV_ASSERT_ON
// VCS coverage off
wire cond_zzz_assert_always_1x = (in_addr[5 -1:0] == 0);
nv_assert_always #(0,0,"lower LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML
// VCS coverage on
`undef ASSERT_RESET
`endif // ASSERT_ON
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass enable_block NoWidthInBasedNum-ML
// spyglass enable_block STARC-2.10.3.2a
// spyglass enable_block STARC05-2.1.3.1
// spyglass enable_block STARC-2.1.4.6
// spyglass enable_block W116
// spyglass enable_block W154
// spyglass enable_block W239
// spyglass enable_block W362
// spyglass enable_block WRN_58
// spyglass enable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
assign stt_offset[3 -1:0] = in_addr[5 +3 -1:5];
assign size_offset[3 -1:0] = in_size[3 -1:0];
assign {mon_end_offset_c, end_offset[3 -1:0]} = stt_offset + size_offset;
assign is_single_tran = (stt_offset + in_size) < 8;
assign ftran_size_tmp[3 -1:0] = is_single_tran ? size_offset : 8 -1 - stt_offset;
assign ltran_size_tmp[3 -1:0] = is_single_tran ? 0 : end_offset;
assign ftran_size[2:0] = {{(3-3){1'b0}},ftran_size_tmp};
assign ltran_size[2:0] = {{(3-3){1'b0}},ltran_size_tmp};
assign mtran_num = in_size - ftran_size - ltran_size - 1;
//================
// check the empty entry of lat.fifo
//================
reg [3:0] slot_needed;
always @(
out_size
//or is_single_tran
or is_ltran
//or out_swizzle
or is_ftran
) begin
//if (is_single_tran) begin
// slot_needed = (out_size>>(1 -1)) + 1; //fixme
//end else if (is_ltran) begin
// slot_needed = ((out_size+out_swizzle)>>(1 -1)) + 1; //fixme
//end else if (is_ftran) begin
// slot_needed = (out_size+1)>>(1 -1);
if (is_ftran | is_ltran) begin
slot_needed = out_size+1;
end else begin
slot_needed = 4'd8;
end
end
assign lat_fifo_stall_enable = (tieoff_lat_fifo_depth!=0);
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
lat_count_dec <= 1'b0;
end else begin
lat_count_dec <= dma2bpt_cdt_lat_fifo_pop;
end
end
assign lat_count_inc = (bpt2arb_accept && lat_fifo_stall_enable ) ? slot_needed : 4'd0;
always @(
lat_count_inc
or lat_count_dec
) begin
lat_adv = lat_count_inc[3:0] != {{3{1'b0}}, lat_count_dec[0:0]};
end
// lat cnt logic
always @(
lat_cnt_cur
or lat_count_inc
or lat_count_dec
or lat_adv
) begin
// VCS sop_coverage_off start
lat_cnt_ext[10:0] = {1'b0, 1'b0, lat_cnt_cur};
lat_cnt_mod[10:0] = lat_cnt_cur + lat_count_inc[3:0] - lat_count_dec[0:0]; // spyglass disable W164b
lat_cnt_new[10:0] = (lat_adv)? lat_cnt_mod[10:0] : lat_cnt_ext[10:0];
lat_cnt_nxt[10:0] = lat_cnt_new[10:0];
// VCS sop_coverage_off end
//| &End;
end
// lat flops
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
lat_cnt_cur[8:0] <= 0;
end else begin
lat_cnt_cur[8:0] <= lat_cnt_nxt[8:0];
end
end
// lat output logic
always @(
lat_cnt_cur
) begin
lat_count_cnt[8:0] = lat_cnt_cur[8:0];
end
// lat asserts
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass disable_block NoWidthInBasedNum-ML
// spyglass disable_block STARC-2.10.3.2a
// spyglass disable_block STARC05-2.1.3.1
// spyglass disable_block STARC-2.1.4.6
// spyglass disable_block W116
// spyglass disable_block W154
// spyglass disable_block W239
// spyglass disable_block W362
// spyglass disable_block WRN_58
// spyglass disable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif // ASSERT_OFF_RESET_IS_X
`endif // SYNTHESIS
`endif // FV_ASSERT_ON
// VCS coverage off
nv_assert_never #(0,0,"never: counter underflow below <und_cnt>") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (lat_cnt_nxt < 0)); // spyglass disable W504 SelfDeterminedExpr-ML
// VCS coverage on
`undef ASSERT_RESET
`endif // ASSERT_ON
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass enable_block NoWidthInBasedNum-ML
// spyglass enable_block STARC-2.10.3.2a
// spyglass enable_block STARC05-2.1.3.1
// spyglass enable_block STARC-2.1.4.6
// spyglass enable_block W116
// spyglass enable_block W154
// spyglass enable_block W239
// spyglass enable_block W362
// spyglass enable_block WRN_58
// spyglass enable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
assign {mon_lat_fifo_free_slot_c,lat_fifo_free_slot[8:0]} = tieoff_lat_fifo_depth - lat_count_cnt;
assign req_enable = (!lat_fifo_stall_enable) || ({{5{1'b0}}, slot_needed} <= lat_fifo_free_slot);
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass disable_block NoWidthInBasedNum-ML
// spyglass disable_block STARC-2.10.3.2a
// spyglass disable_block STARC05-2.1.3.1
// spyglass disable_block STARC-2.1.4.6
// spyglass disable_block W116
// spyglass disable_block W154
// spyglass disable_block W239
// spyglass disable_block W362
// spyglass disable_block WRN_58
// spyglass disable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif // ASSERT_OFF_RESET_IS_X
`endif // SYNTHESIS
`endif // FV_ASSERT_ON
// VCS coverage off
nv_assert_never #(0,0,"should not over flow") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_lat_fifo_free_slot_c); // spyglass disable W504 SelfDeterminedExpr-ML
// VCS coverage on
`undef ASSERT_RESET
`endif // ASSERT_ON
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass enable_block NoWidthInBasedNum-ML
// spyglass enable_block STARC-2.10.3.2a
// spyglass enable_block STARC05-2.1.3.1
// spyglass enable_block STARC-2.1.4.6
// spyglass enable_block W116
// spyglass enable_block W154
// spyglass enable_block W239
// spyglass enable_block W362
// spyglass enable_block WRN_58
// spyglass enable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
//================
// bsp out: swizzle
//================
assign out_swizzle = 1'b0;
assign out_odd = 1'b0;
//================
// bsp out: size
//================
always @(
is_ftran
or ftran_size
or is_mtran
or is_ltran
or ltran_size
) begin
out_size_tmp = {3{`tick_x_or_0}};
if (is_ftran) begin
out_size_tmp = ftran_size;
end else if (is_mtran) begin
out_size_tmp = 8 -1;
end else if (is_ltran) begin
out_size_tmp = ltran_size;
end
end
assign out_size = out_size_tmp;
//================
// bpt2arb: addr
//================
always @(posedge nvdla_core_clk) begin
if (bpt2arb_accept) begin
if (is_ftran) begin
out_addr <= in_addr + ((ftran_size+1) <<5);
end else begin
out_addr <= out_addr + (8<<5);
end
end
end
//================
// tran count
//================
always @(
is_single_tran
or mtran_num
) begin
if (is_single_tran) begin
req_num = 0;
end else begin
req_num = 1 + mtran_num[14:3];
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
count_req <= {15{1'b0}};
end else begin
if (bpt2arb_accept) begin
if (is_ltran) begin
count_req <= 0;
end else begin
count_req <= count_req + 1;
end
end
end
end
assign is_ftran = (count_req==0);
assign is_mtran = (count_req>0 && count_req<req_num);
assign is_ltran = (count_req==req_num);
assign bpt2arb_addr = (is_ftran) ? in_addr : out_addr;
assign bpt2arb_size = out_size;
assign bpt2arb_swizzle = out_swizzle;
assign bpt2arb_odd = out_odd;
assign bpt2arb_ltran = is_ltran;
assign bpt2arb_ftran = is_ftran;
assign bpt2arb_axid = tieoff_axid[3:0];
assign req_rdy = req_enable & bpt2arb_req_ready;
assign req_vld = req_enable & in_vld;
assign bpt2arb_req_valid = req_vld;
assign bpt2arb_accept = bpt2arb_req_valid & req_rdy;
assign bpt2arb_req_pd[3:0] = bpt2arb_axid[3:0];
assign bpt2arb_req_pd[64 +3:4] = bpt2arb_addr[64 -1:0];
assign bpt2arb_req_pd[64 +6:64 +4] = bpt2arb_size[2:0];
assign bpt2arb_req_pd[64 +7] = bpt2arb_swizzle ;
assign bpt2arb_req_pd[64 +8] = bpt2arb_odd ;
assign bpt2arb_req_pd[64 +9] = bpt2arb_ltran ;
assign bpt2arb_req_pd[64 +10] = bpt2arb_ftran ;
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
reg funcpoint_cover_off;
initial begin
if ( $test$plusargs( "cover_off" ) ) begin
funcpoint_cover_off = 1'b1;
end else begin
funcpoint_cover_off = 1'b0;
end
end
property mcif_bpt__is_first_trans__0_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
((req_vld) && nvdla_core_rstn) |-> (is_ftran);
endproperty
// Cover 0 : "is_ftran"
FUNCPOINT_mcif_bpt__is_first_trans__0_COV : cover property (mcif_bpt__is_first_trans__0_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property mcif_bpt__is_middle_trans__1_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
((req_vld) && nvdla_core_rstn) |-> (is_mtran);
endproperty
// Cover 1 : "is_mtran"
FUNCPOINT_mcif_bpt__is_middle_trans__1_COV : cover property (mcif_bpt__is_middle_trans__1_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property mcif_bpt__is_last_trans__2_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
((req_vld) && nvdla_core_rstn) |-> (is_ltran);
endproperty
// Cover 2 : "is_ltran"
FUNCPOINT_mcif_bpt__is_last_trans__2_COV : cover property (mcif_bpt__is_last_trans__2_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property mcif_bpt__is_odd_not_swizzle__4_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
((req_vld) && nvdla_core_rstn) |-> (out_odd & !out_swizzle);
endproperty
// Cover 4 : "out_odd & !out_swizzle"
FUNCPOINT_mcif_bpt__is_odd_not_swizzle__4_COV : cover property (mcif_bpt__is_odd_not_swizzle__4_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property mcif_bpt__count_inc_and_dec__5_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
lat_count_inc & lat_count_dec;
endproperty
// Cover 5 : "lat_count_inc & lat_count_dec"
FUNCPOINT_mcif_bpt__count_inc_and_dec__5_COV : cover property (mcif_bpt__count_inc_and_dec__5_cov);
`endif
`endif
//VCS coverage on
endmodule // NV_NVDLA_MCIF_READ_IG_bpt |
module NV_NVDLA_DMAIF_rdreq (
nvdla_core_clk
,nvdla_core_rstn
,reg2dp_src_ram_type
,cvif_rd_req_pd
,cvif_rd_req_valid
,cvif_rd_req_ready
,mcif_rd_req_pd
,mcif_rd_req_valid
,mcif_rd_req_ready
,dmaif_rd_req_pd
,dmaif_rd_req_vld
,dmaif_rd_req_rdy
);
//////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
input reg2dp_src_ram_type;
output [64 +14:0] cvif_rd_req_pd;
output cvif_rd_req_valid;
input cvif_rd_req_ready;
output [64 +14:0] mcif_rd_req_pd;
output mcif_rd_req_valid;
input mcif_rd_req_ready;
input [64 +14:0] dmaif_rd_req_pd;
input dmaif_rd_req_vld;
output dmaif_rd_req_rdy;
//////////////////////////////////////////////
wire mc_dma_rd_req_vld;
wire mc_dma_rd_req_rdy;
wire mc_rd_req_rdyi;
wire dma_rd_req_ram_type;
wire rd_req_rdyi;
//////////////////////////////////////////////
assign dma_rd_req_ram_type = reg2dp_src_ram_type;
assign mc_dma_rd_req_vld = dmaif_rd_req_vld & (dma_rd_req_ram_type == 1'b1);
assign mc_rd_req_rdyi = mc_dma_rd_req_rdy & (dma_rd_req_ram_type == 1'b1);
assign dmaif_rd_req_rdy= rd_req_rdyi;
//: my $dmabw = ( 64 + 15 );
//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_req_pd -vo mcif_rd_req_valid -ri mcif_rd_req_ready -di dmaif_rd_req_pd -vi mc_dma_rd_req_vld -ro mc_dma_rd_req_rdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg mc_dma_rd_req_rdy_f;
reg skid_flop_mc_dma_rd_req_rdy_f;
reg skid_flop_mc_dma_rd_req_vld;
reg [79-1:0] skid_flop_dmaif_rd_req_pd;
reg pipe_skid_mc_dma_rd_req_vld;
reg [79-1:0] pipe_skid_dmaif_rd_req_pd;
// Wire
wire skid_mc_dma_rd_req_vld;
wire [79-1:0] skid_dmaif_rd_req_pd;
wire skid_mc_dma_rd_req_rdy_f;
wire pipe_skid_mc_dma_rd_req_rdy_f;
wire mcif_rd_req_valid;
wire [79-1:0] mcif_rd_req_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_dma_rd_req_rdy_f <= 1'b1;
skid_flop_mc_dma_rd_req_rdy_f <= 1'b1;
end else begin
mc_dma_rd_req_rdy_f <= skid_mc_dma_rd_req_rdy_f;
skid_flop_mc_dma_rd_req_rdy_f <= skid_mc_dma_rd_req_rdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_mc_dma_rd_req_vld <= 1'b0;
end else begin
if (skid_flop_mc_dma_rd_req_rdy_f) begin
skid_flop_mc_dma_rd_req_vld <= mc_dma_rd_req_vld;
end
end
end
assign skid_mc_dma_rd_req_vld = (skid_flop_mc_dma_rd_req_rdy_f) ? mc_dma_rd_req_vld : skid_flop_mc_dma_rd_req_vld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_mc_dma_rd_req_rdy_f & mc_dma_rd_req_vld) begin
skid_flop_dmaif_rd_req_pd[79-1:0] <= dmaif_rd_req_pd[79-1:0];
end
end
assign skid_dmaif_rd_req_pd[79-1:0] = (skid_flop_mc_dma_rd_req_rdy_f) ? dmaif_rd_req_pd[79-1:0] : skid_flop_dmaif_rd_req_pd[79-1:0];
// PIPE READY
assign skid_mc_dma_rd_req_rdy_f = pipe_skid_mc_dma_rd_req_rdy_f || !pipe_skid_mc_dma_rd_req_vld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_mc_dma_rd_req_vld <= 1'b0;
end else begin
if (skid_mc_dma_rd_req_rdy_f) begin
pipe_skid_mc_dma_rd_req_vld <= skid_mc_dma_rd_req_vld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_mc_dma_rd_req_rdy_f && skid_mc_dma_rd_req_vld) begin
pipe_skid_dmaif_rd_req_pd[79-1:0] <= skid_dmaif_rd_req_pd[79-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_mc_dma_rd_req_rdy_f = mcif_rd_req_ready;
assign mcif_rd_req_valid = pipe_skid_mc_dma_rd_req_vld;
assign mcif_rd_req_pd = pipe_skid_dmaif_rd_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign mc_dma_rd_req_rdy = mc_dma_rd_req_rdy_f;
wire cv_dma_rd_req_vld;
wire cv_rd_req_rdyi;
wire cv_dma_rd_req_rdy;
assign cv_dma_rd_req_vld = dmaif_rd_req_vld & (dma_rd_req_ram_type == 1'b0);
assign cv_rd_req_rdyi = cv_dma_rd_req_rdy & (dma_rd_req_ram_type == 1'b0);
assign rd_req_rdyi = mc_rd_req_rdyi | cv_rd_req_rdyi;
//: my $dmabw = ( 64 + 15 );
//: print "wire [${dmabw}-1:0] cv_dma_rd_req_pd; \n";
//: print "assign cv_dma_rd_req_pd = dmaif_rd_req_pd; \n";
//: &eperl::pipe(" -wid $dmabw -is -do cvif_rd_req_pd -vo cvif_rd_req_valid -ri cvif_rd_req_ready -di cv_dma_rd_req_pd -vi cv_dma_rd_req_vld -ro cv_dma_rd_req_rdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [79-1:0] cv_dma_rd_req_pd;
assign cv_dma_rd_req_pd = dmaif_rd_req_pd;
// Reg
reg cv_dma_rd_req_rdy_f;
reg skid_flop_cv_dma_rd_req_rdy_f;
reg skid_flop_cv_dma_rd_req_vld;
reg [79-1:0] skid_flop_cv_dma_rd_req_pd;
reg pipe_skid_cv_dma_rd_req_vld;
reg [79-1:0] pipe_skid_cv_dma_rd_req_pd;
// Wire
wire skid_cv_dma_rd_req_vld;
wire [79-1:0] skid_cv_dma_rd_req_pd;
wire skid_cv_dma_rd_req_rdy_f;
wire pipe_skid_cv_dma_rd_req_rdy_f;
wire cvif_rd_req_valid;
wire [79-1:0] cvif_rd_req_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_dma_rd_req_rdy_f <= 1'b1;
skid_flop_cv_dma_rd_req_rdy_f <= 1'b1;
end else begin
cv_dma_rd_req_rdy_f <= skid_cv_dma_rd_req_rdy_f;
skid_flop_cv_dma_rd_req_rdy_f <= skid_cv_dma_rd_req_rdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_cv_dma_rd_req_vld <= 1'b0;
end else begin
if (skid_flop_cv_dma_rd_req_rdy_f) begin
skid_flop_cv_dma_rd_req_vld <= cv_dma_rd_req_vld;
end
end
end
assign skid_cv_dma_rd_req_vld = (skid_flop_cv_dma_rd_req_rdy_f) ? cv_dma_rd_req_vld : skid_flop_cv_dma_rd_req_vld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_cv_dma_rd_req_rdy_f & cv_dma_rd_req_vld) begin
skid_flop_cv_dma_rd_req_pd[79-1:0] <= cv_dma_rd_req_pd[79-1:0];
end
end
assign skid_cv_dma_rd_req_pd[79-1:0] = (skid_flop_cv_dma_rd_req_rdy_f) ? cv_dma_rd_req_pd[79-1:0] : skid_flop_cv_dma_rd_req_pd[79-1:0];
// PIPE READY
assign skid_cv_dma_rd_req_rdy_f = pipe_skid_cv_dma_rd_req_rdy_f || !pipe_skid_cv_dma_rd_req_vld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_cv_dma_rd_req_vld <= 1'b0;
end else begin
if (skid_cv_dma_rd_req_rdy_f) begin
pipe_skid_cv_dma_rd_req_vld <= skid_cv_dma_rd_req_vld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_cv_dma_rd_req_rdy_f && skid_cv_dma_rd_req_vld) begin
pipe_skid_cv_dma_rd_req_pd[79-1:0] <= skid_cv_dma_rd_req_pd[79-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_cv_dma_rd_req_rdy_f = cvif_rd_req_ready;
assign cvif_rd_req_valid = pipe_skid_cv_dma_rd_req_vld;
assign cvif_rd_req_pd = pipe_skid_cv_dma_rd_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign cv_dma_rd_req_rdy = cv_dma_rd_req_rdy_f;
endmodule |
module nv_ram_rwsp_8x257 (
clk,
ra,
re,
ore,
dout,
wa,
we,
di,
pwrbus_ram_pd
);
parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
// port list
input clk;
input [2:0] ra;
input re;
input ore;
output [256:0] dout;
input [2:0] wa;
input we;
input [256:0] di;
input [31:0] pwrbus_ram_pd;
//reg and wire list
reg [2:0] ra_d;
wire [256:0] dout;
reg [256:0] M [7:0];
always @( posedge clk ) begin
if (we)
M[wa] <= di;
end
always @( posedge clk ) begin
if (re)
ra_d <= ra;
end
wire [256:0] dout_ram = M[ra_d];
reg [256:0] dout_r;
always @( posedge clk ) begin
if (ore)
dout_r <= dout_ram;
end
assign dout = dout_r;
endmodule |
module NV_NVDLA_pdp (
dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,csb2pdp_rdma_req_pvld //|< i
,csb2pdp_rdma_req_prdy //|> o
,csb2pdp_rdma_req_pd //|< i
,csb2pdp_req_pvld //|< i
,csb2pdp_req_prdy //|> o
,csb2pdp_req_pd //|< i
,cvif2pdp_rd_rsp_valid //|< i
,cvif2pdp_rd_rsp_ready //|> o
,cvif2pdp_rd_rsp_pd //|< i
,cvif2pdp_wr_rsp_complete //|< i
,pdp2cvif_rd_cdt_lat_fifo_pop //|> o
,pdp2cvif_rd_req_valid //|> o
,pdp2cvif_rd_req_ready //|< i
,pdp2cvif_rd_req_pd //|> o
,pdp2cvif_wr_req_valid //|> o
,pdp2cvif_wr_req_ready //|< i
,pdp2cvif_wr_req_pd //|> o
,mcif2pdp_rd_rsp_valid //|< i
,mcif2pdp_rd_rsp_ready //|> o
,mcif2pdp_rd_rsp_pd //|< i
,mcif2pdp_wr_rsp_complete //|< i
,pdp2csb_resp_valid //|> o
,pdp2csb_resp_pd //|> o
,pdp2glb_done_intr_pd //|> o
,pdp2mcif_rd_cdt_lat_fifo_pop //|> o
,pdp2mcif_rd_req_valid //|> o
,pdp2mcif_rd_req_ready //|< i
,pdp2mcif_rd_req_pd //|> o
,pdp2mcif_wr_req_valid //|> o
,pdp2mcif_wr_req_ready //|< i
,pdp2mcif_wr_req_pd //|> o
,pdp_rdma2csb_resp_valid //|> o
,pdp_rdma2csb_resp_pd //|> o
,pwrbus_ram_pd //|< i
,sdp2pdp_valid //|< i
,sdp2pdp_ready //|> o
,sdp2pdp_pd //|< i
);
///////////////////////////////////////////////////////////////////////
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
input nvdla_core_clk;
input nvdla_core_rstn;
input csb2pdp_rdma_req_pvld;
output csb2pdp_rdma_req_prdy;
input [62:0] csb2pdp_rdma_req_pd;
input csb2pdp_req_pvld;
output csb2pdp_req_prdy;
input [62:0] csb2pdp_req_pd;
input cvif2pdp_rd_rsp_valid;
output cvif2pdp_rd_rsp_ready;
input [( 256 + (256/8/32) )-1:0] cvif2pdp_rd_rsp_pd;
input cvif2pdp_wr_rsp_complete;
output pdp2cvif_rd_cdt_lat_fifo_pop;
output pdp2cvif_rd_req_valid;
input pdp2cvif_rd_req_ready;
output [64 +14:0] pdp2cvif_rd_req_pd;
output pdp2cvif_wr_req_valid;
input pdp2cvif_wr_req_ready;
output [( 256 + (256/8/32) + 1 )-1:0] pdp2cvif_wr_req_pd;
input mcif2pdp_rd_rsp_valid;
output mcif2pdp_rd_rsp_ready;
input [( 256 + (256/8/32) )-1:0] mcif2pdp_rd_rsp_pd;
input mcif2pdp_wr_rsp_complete;
output pdp2csb_resp_valid;
output [33:0] pdp2csb_resp_pd;
output [1:0] pdp2glb_done_intr_pd;
output pdp2mcif_rd_cdt_lat_fifo_pop;
output pdp2mcif_rd_req_valid;
input pdp2mcif_rd_req_ready;
output [64 +14:0] pdp2mcif_rd_req_pd;
output pdp2mcif_wr_req_valid;
input pdp2mcif_wr_req_ready;
output [( 256 + (256/8/32) + 1 )-1:0] pdp2mcif_wr_req_pd;
output pdp_rdma2csb_resp_valid;
output [33:0] pdp_rdma2csb_resp_pd;
input [31:0] pwrbus_ram_pd;
input sdp2pdp_valid;
output sdp2pdp_ready;
input [8*16 -1:0] sdp2pdp_pd;
//
///////////////////////////////////////////////////////////////////////
assign csb2pdp_req_prdy = 1'b1;
assign pdp2csb_resp_valid = 1'b0;
assign pdp2csb_resp_pd = 34'd0;
assign csb2pdp_rdma_req_prdy = 1'b1;
assign pdp_rdma2csb_resp_valid = 1'b0;
assign pdp_rdma2csb_resp_pd = 34'd0;
assign sdp2pdp_ready = 1'b1;
assign cvif2pdp_rd_rsp_ready = 1'b1;
assign pdp2cvif_rd_cdt_lat_fifo_pop = 1'b0;
assign pdp2cvif_rd_req_valid = 1'b0;
assign pdp2cvif_rd_req_pd = 79'd0;
assign pdp2cvif_wr_req_valid = 1'b0;
assign pdp2cvif_wr_req_pd = 258'd0;
assign mcif2pdp_rd_rsp_ready = 1'b1;
assign pdp2mcif_rd_cdt_lat_fifo_pop = 1'b0;
assign pdp2mcif_rd_req_valid = 1'b0;
assign pdp2mcif_rd_req_pd = 79'd0;
assign pdp2mcif_wr_req_valid = 1'b0;
assign pdp2mcif_wr_req_pd = 258'd0;
assign pdp2glb_done_intr_pd = 2'd0;
///////////////////////////////////////////////////////////////////////
//
endmodule // NV_NVDLA_pdp |
module NV_NVDLA_mcif (
nvdla_core_clk
,nvdla_core_rstn
,pwrbus_ram_pd
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print " ,${client}2mcif_rd_cdt_lat_fifo_pop\n";
//: print " ,${client}2mcif_rd_req_valid\n";
//: print " ,${client}2mcif_rd_req_ready\n";
//: print " ,${client}2mcif_rd_req_pd\n";
//: print " ,mcif2${client}_rd_rsp_valid\n";
//: print " ,mcif2${client}_rd_rsp_ready\n";
//: print " ,mcif2${client}_rd_rsp_pd\n";
//: }
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print " ,${client}2mcif_wr_req_valid\n";
//: print " ,${client}2mcif_wr_req_ready\n";
//: print " ,${client}2mcif_wr_req_pd\n";
//: print " ,mcif2${client}_wr_rsp_complete\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,cdma_dat2mcif_rd_cdt_lat_fifo_pop
,cdma_dat2mcif_rd_req_valid
,cdma_dat2mcif_rd_req_ready
,cdma_dat2mcif_rd_req_pd
,mcif2cdma_dat_rd_rsp_valid
,mcif2cdma_dat_rd_rsp_ready
,mcif2cdma_dat_rd_rsp_pd
,cdma_wt2mcif_rd_cdt_lat_fifo_pop
,cdma_wt2mcif_rd_req_valid
,cdma_wt2mcif_rd_req_ready
,cdma_wt2mcif_rd_req_pd
,mcif2cdma_wt_rd_rsp_valid
,mcif2cdma_wt_rd_rsp_ready
,mcif2cdma_wt_rd_rsp_pd
,sdp2mcif_rd_cdt_lat_fifo_pop
,sdp2mcif_rd_req_valid
,sdp2mcif_rd_req_ready
,sdp2mcif_rd_req_pd
,mcif2sdp_rd_rsp_valid
,mcif2sdp_rd_rsp_ready
,mcif2sdp_rd_rsp_pd
,sdp_b2mcif_rd_cdt_lat_fifo_pop
,sdp_b2mcif_rd_req_valid
,sdp_b2mcif_rd_req_ready
,sdp_b2mcif_rd_req_pd
,mcif2sdp_b_rd_rsp_valid
,mcif2sdp_b_rd_rsp_ready
,mcif2sdp_b_rd_rsp_pd
,sdp_n2mcif_rd_cdt_lat_fifo_pop
,sdp_n2mcif_rd_req_valid
,sdp_n2mcif_rd_req_ready
,sdp_n2mcif_rd_req_pd
,mcif2sdp_n_rd_rsp_valid
,mcif2sdp_n_rd_rsp_ready
,mcif2sdp_n_rd_rsp_pd
,sdp_e2mcif_rd_cdt_lat_fifo_pop
,sdp_e2mcif_rd_req_valid
,sdp_e2mcif_rd_req_ready
,sdp_e2mcif_rd_req_pd
,mcif2sdp_e_rd_rsp_valid
,mcif2sdp_e_rd_rsp_ready
,mcif2sdp_e_rd_rsp_pd
,pdp2mcif_rd_cdt_lat_fifo_pop
,pdp2mcif_rd_req_valid
,pdp2mcif_rd_req_ready
,pdp2mcif_rd_req_pd
,mcif2pdp_rd_rsp_valid
,mcif2pdp_rd_rsp_ready
,mcif2pdp_rd_rsp_pd
,cdp2mcif_rd_cdt_lat_fifo_pop
,cdp2mcif_rd_req_valid
,cdp2mcif_rd_req_ready
,cdp2mcif_rd_req_pd
,mcif2cdp_rd_rsp_valid
,mcif2cdp_rd_rsp_ready
,mcif2cdp_rd_rsp_pd
,bdma2mcif_rd_cdt_lat_fifo_pop
,bdma2mcif_rd_req_valid
,bdma2mcif_rd_req_ready
,bdma2mcif_rd_req_pd
,mcif2bdma_rd_rsp_valid
,mcif2bdma_rd_rsp_ready
,mcif2bdma_rd_rsp_pd
,sdp2mcif_wr_req_valid
,sdp2mcif_wr_req_ready
,sdp2mcif_wr_req_pd
,mcif2sdp_wr_rsp_complete
,pdp2mcif_wr_req_valid
,pdp2mcif_wr_req_ready
,pdp2mcif_wr_req_pd
,mcif2pdp_wr_rsp_complete
,cdp2mcif_wr_req_valid
,cdp2mcif_wr_req_ready
,cdp2mcif_wr_req_pd
,mcif2cdp_wr_rsp_complete
,bdma2mcif_wr_req_valid
,bdma2mcif_wr_req_ready
,bdma2mcif_wr_req_pd
,mcif2bdma_wr_rsp_complete
//| eperl: generated_end (DO NOT EDIT ABOVE)
,csb2mcif_req_pd //|< i
,csb2mcif_req_pvld //|< i
,csb2mcif_req_prdy //|> o
,mcif2csb_resp_pd //|> o
,mcif2csb_resp_valid //|> o
,noc2mcif_axi_b_bid //|< i
,noc2mcif_axi_b_bvalid //|< i
,noc2mcif_axi_b_bready //|> o
,noc2mcif_axi_r_rdata //|< i
,noc2mcif_axi_r_rid //|< i
,noc2mcif_axi_r_rlast //|< i
,noc2mcif_axi_r_rvalid //|< i
,noc2mcif_axi_r_rready //|> o
,mcif2noc_axi_ar_araddr //|> o
,mcif2noc_axi_ar_arid //|> o
,mcif2noc_axi_ar_arlen //|> o
,mcif2noc_axi_ar_arvalid //|> o
,mcif2noc_axi_ar_arready //|< i
,mcif2noc_axi_aw_awaddr //|> o
,mcif2noc_axi_aw_awid //|> o
,mcif2noc_axi_aw_awlen //|> o
,mcif2noc_axi_aw_awvalid //|> o
,mcif2noc_axi_aw_awready //|< i
,mcif2noc_axi_w_wdata //|> o
,mcif2noc_axi_w_wlast //|> o
,mcif2noc_axi_w_wstrb //|> o
,mcif2noc_axi_w_wvalid //|> o
,mcif2noc_axi_w_wready //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input csb2mcif_req_pvld;
output csb2mcif_req_prdy;
input [62:0] csb2mcif_req_pd;
output mcif2csb_resp_valid;
output [33:0] mcif2csb_resp_pd;
output mcif2noc_axi_ar_arvalid;
input mcif2noc_axi_ar_arready;
output [7:0] mcif2noc_axi_ar_arid;
output [3:0] mcif2noc_axi_ar_arlen;
output [64 -1:0] mcif2noc_axi_ar_araddr;
output mcif2noc_axi_aw_awvalid;
input mcif2noc_axi_aw_awready;
output [7:0] mcif2noc_axi_aw_awid;
output [3:0] mcif2noc_axi_aw_awlen;
output [64 -1:0] mcif2noc_axi_aw_awaddr;
output mcif2noc_axi_w_wvalid;
input mcif2noc_axi_w_wready;
output [256 -1:0] mcif2noc_axi_w_wdata;
output [32 -1:0] mcif2noc_axi_w_wstrb;
output mcif2noc_axi_w_wlast;
input noc2mcif_axi_b_bvalid;
output noc2mcif_axi_b_bready;
input [7:0] noc2mcif_axi_b_bid;
input noc2mcif_axi_r_rvalid;
output noc2mcif_axi_r_rready;
input [7:0] noc2mcif_axi_r_rid;
input noc2mcif_axi_r_rlast;
input [256 -1:0] noc2mcif_axi_r_rdata;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print ("input ${client}2mcif_rd_cdt_lat_fifo_pop;\n");
//: print ("input ${client}2mcif_rd_req_valid;\n");
//: print ("output ${client}2mcif_rd_req_ready;\n");
//: print qq(input [79 -1:0] ${client}2mcif_rd_req_pd;\n);
//: print ("output mcif2${client}_rd_rsp_valid;\n");
//: print ("input mcif2${client}_rd_rsp_ready;\n");
//: print qq(output [257 -1:0] mcif2${client}_rd_rsp_pd;\n);
//: }
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print ("input ${client}2mcif_wr_req_valid;\n");
//: print ("output ${client}2mcif_wr_req_ready;\n");
//: print qq(input [258 -1:0] ${client}2mcif_wr_req_pd;\n);
//: print ("output mcif2${client}_wr_rsp_complete;\n");
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input cdma_dat2mcif_rd_cdt_lat_fifo_pop;
input cdma_dat2mcif_rd_req_valid;
output cdma_dat2mcif_rd_req_ready;
input [79 -1:0] cdma_dat2mcif_rd_req_pd;
output mcif2cdma_dat_rd_rsp_valid;
input mcif2cdma_dat_rd_rsp_ready;
output [257 -1:0] mcif2cdma_dat_rd_rsp_pd;
input cdma_wt2mcif_rd_cdt_lat_fifo_pop;
input cdma_wt2mcif_rd_req_valid;
output cdma_wt2mcif_rd_req_ready;
input [79 -1:0] cdma_wt2mcif_rd_req_pd;
output mcif2cdma_wt_rd_rsp_valid;
input mcif2cdma_wt_rd_rsp_ready;
output [257 -1:0] mcif2cdma_wt_rd_rsp_pd;
input sdp2mcif_rd_cdt_lat_fifo_pop;
input sdp2mcif_rd_req_valid;
output sdp2mcif_rd_req_ready;
input [79 -1:0] sdp2mcif_rd_req_pd;
output mcif2sdp_rd_rsp_valid;
input mcif2sdp_rd_rsp_ready;
output [257 -1:0] mcif2sdp_rd_rsp_pd;
input sdp_b2mcif_rd_cdt_lat_fifo_pop;
input sdp_b2mcif_rd_req_valid;
output sdp_b2mcif_rd_req_ready;
input [79 -1:0] sdp_b2mcif_rd_req_pd;
output mcif2sdp_b_rd_rsp_valid;
input mcif2sdp_b_rd_rsp_ready;
output [257 -1:0] mcif2sdp_b_rd_rsp_pd;
input sdp_n2mcif_rd_cdt_lat_fifo_pop;
input sdp_n2mcif_rd_req_valid;
output sdp_n2mcif_rd_req_ready;
input [79 -1:0] sdp_n2mcif_rd_req_pd;
output mcif2sdp_n_rd_rsp_valid;
input mcif2sdp_n_rd_rsp_ready;
output [257 -1:0] mcif2sdp_n_rd_rsp_pd;
input sdp_e2mcif_rd_cdt_lat_fifo_pop;
input sdp_e2mcif_rd_req_valid;
output sdp_e2mcif_rd_req_ready;
input [79 -1:0] sdp_e2mcif_rd_req_pd;
output mcif2sdp_e_rd_rsp_valid;
input mcif2sdp_e_rd_rsp_ready;
output [257 -1:0] mcif2sdp_e_rd_rsp_pd;
input pdp2mcif_rd_cdt_lat_fifo_pop;
input pdp2mcif_rd_req_valid;
output pdp2mcif_rd_req_ready;
input [79 -1:0] pdp2mcif_rd_req_pd;
output mcif2pdp_rd_rsp_valid;
input mcif2pdp_rd_rsp_ready;
output [257 -1:0] mcif2pdp_rd_rsp_pd;
input cdp2mcif_rd_cdt_lat_fifo_pop;
input cdp2mcif_rd_req_valid;
output cdp2mcif_rd_req_ready;
input [79 -1:0] cdp2mcif_rd_req_pd;
output mcif2cdp_rd_rsp_valid;
input mcif2cdp_rd_rsp_ready;
output [257 -1:0] mcif2cdp_rd_rsp_pd;
input bdma2mcif_rd_cdt_lat_fifo_pop;
input bdma2mcif_rd_req_valid;
output bdma2mcif_rd_req_ready;
input [79 -1:0] bdma2mcif_rd_req_pd;
output mcif2bdma_rd_rsp_valid;
input mcif2bdma_rd_rsp_ready;
output [257 -1:0] mcif2bdma_rd_rsp_pd;
input sdp2mcif_wr_req_valid;
output sdp2mcif_wr_req_ready;
input [258 -1:0] sdp2mcif_wr_req_pd;
output mcif2sdp_wr_rsp_complete;
input pdp2mcif_wr_req_valid;
output pdp2mcif_wr_req_ready;
input [258 -1:0] pdp2mcif_wr_req_pd;
output mcif2pdp_wr_rsp_complete;
input cdp2mcif_wr_req_valid;
output cdp2mcif_wr_req_ready;
input [258 -1:0] cdp2mcif_wr_req_pd;
output mcif2cdp_wr_rsp_complete;
input bdma2mcif_wr_req_valid;
output bdma2mcif_wr_req_ready;
input [258 -1:0] bdma2mcif_wr_req_pd;
output mcif2bdma_wr_rsp_complete;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [7:0] reg2dp_rd_os_cnt;
wire [7:0] reg2dp_wr_os_cnt;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print "wire [7:0] reg2dp_rd_weight_${client};\n";
//: }
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print "wire [7:0] reg2dp_wr_weight_${client};\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [7:0] reg2dp_rd_weight_cdma_dat;
wire [7:0] reg2dp_rd_weight_cdma_wt;
wire [7:0] reg2dp_rd_weight_sdp;
wire [7:0] reg2dp_rd_weight_sdp_b;
wire [7:0] reg2dp_rd_weight_sdp_n;
wire [7:0] reg2dp_rd_weight_sdp_e;
wire [7:0] reg2dp_rd_weight_pdp;
wire [7:0] reg2dp_rd_weight_cdp;
wire [7:0] reg2dp_rd_weight_bdma;
wire [7:0] reg2dp_wr_weight_sdp;
wire [7:0] reg2dp_wr_weight_pdp;
wire [7:0] reg2dp_wr_weight_cdp;
wire [7:0] reg2dp_wr_weight_bdma;
//| eperl: generated_end (DO NOT EDIT ABOVE)
NV_NVDLA_MCIF_csb u_csb (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< i
,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> o
,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< i
,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> o
,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> o
,.dp2reg_idle ({1{1'b1}}) //|< ?
,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|> w
,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|> w
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print" ,.reg2dp_rd_weight_${client} (reg2dp_rd_weight_${client}[7:0])\n";
//: }
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print" ,.reg2dp_wr_weight_${client} (reg2dp_wr_weight_${client}[7:0])\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0])
,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0])
,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp[7:0])
,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0])
,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0])
,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0])
,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp[7:0])
,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp[7:0])
,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma[7:0])
,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp[7:0])
,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp[7:0])
,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp[7:0])
,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma[7:0])
,.reg2dp_rd_weight_rbk () //|> ?
,.reg2dp_wr_weight_rbk () //|> ?
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.reg2dp_rd_weight_rsv_0 () //|> ?
,.reg2dp_rd_weight_rsv_1 () //|> ?
,.reg2dp_wr_weight_rsv_0 () //|> ?
,.reg2dp_wr_weight_rsv_1 () //|> ?
,.reg2dp_wr_weight_rsv_2 () //|> ?
);
NV_NVDLA_MCIF_read u_read (
.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd)
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,.reg2dp_rd_weight_${client} (reg2dp_rd_weight_${client})\n"),
//: }
//: foreach my $client (@rdma_name) {
//: print(" ,.${client}2mcif_rd_cdt_lat_fifo_pop (${client}2mcif_rd_cdt_lat_fifo_pop)\n");
//: print(" ,.${client}2mcif_rd_req_valid (${client}2mcif_rd_req_valid)\n");
//: print(" ,.${client}2mcif_rd_req_ready (${client}2mcif_rd_req_ready)\n");
//: print(" ,.${client}2mcif_rd_req_pd (${client}2mcif_rd_req_pd)\n");
//: print(" ,.mcif2${client}_rd_rsp_valid (mcif2${client}_rd_rsp_valid)\n");
//: print(" ,.mcif2${client}_rd_rsp_ready (mcif2${client}_rd_rsp_ready)\n");
//: print(" ,.mcif2${client}_rd_rsp_pd (mcif2${client}_rd_rsp_pd)\n"),
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat)
,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt)
,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp)
,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b)
,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n)
,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e)
,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp)
,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp)
,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma)
,.cdma_dat2mcif_rd_cdt_lat_fifo_pop (cdma_dat2mcif_rd_cdt_lat_fifo_pop)
,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid)
,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready)
,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd)
,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid)
,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready)
,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd)
,.cdma_wt2mcif_rd_cdt_lat_fifo_pop (cdma_wt2mcif_rd_cdt_lat_fifo_pop)
,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid)
,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready)
,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd)
,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid)
,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready)
,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd)
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid)
,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready)
,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd)
,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid)
,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready)
,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd)
,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid)
,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready)
,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd)
,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid)
,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready)
,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd)
,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid)
,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready)
,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd)
,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid)
,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready)
,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd)
,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid)
,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready)
,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd)
,.mcif2sdp_e_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid)
,.mcif2sdp_e_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready)
,.mcif2sdp_e_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd)
,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop)
,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid)
,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready)
,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd)
,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid)
,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready)
,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd)
,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop)
,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid)
,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready)
,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd)
,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid)
,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready)
,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd)
,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid)
,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready)
,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd)
,.mcif2bdma_rd_rsp_valid (mcif2bdma_rd_rsp_valid)
,.mcif2bdma_rd_rsp_ready (mcif2bdma_rd_rsp_ready)
,.mcif2bdma_rd_rsp_pd (mcif2bdma_rd_rsp_pd)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid)
,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready)
,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid)
,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen)
,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr)
,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid)
,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready)
,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid)
,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast)
,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata)
);
NV_NVDLA_MCIF_write u_write (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt)
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print(" ,.reg2dp_wr_weight_${client} (reg2dp_wr_weight_${client})\n"),
//: }
//: foreach my $client (@wdma_name) {
//: print(" ,.${client}2mcif_wr_req_valid (${client}2mcif_wr_req_valid)\n");
//: print(" ,.${client}2mcif_wr_req_ready (${client}2mcif_wr_req_ready)\n");
//: print(" ,.${client}2mcif_wr_req_pd (${client}2mcif_wr_req_pd)\n");
//: print(" ,.mcif2${client}_wr_rsp_complete (mcif2${client}_wr_rsp_complete)\n");
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp)
,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp)
,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp)
,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma)
,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid)
,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready)
,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd)
,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete)
,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid)
,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready)
,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd)
,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete)
,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid)
,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready)
,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd)
,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete)
,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid)
,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready)
,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd)
,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid)
,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready)
,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid)
,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen)
,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr)
,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid)
,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready)
,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata)
,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb)
,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast)
,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid)
,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready)
,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid)
);
endmodule |
module NV_nvdla_top (
dla_core_clk,
dla_csb_clk,
dla_reset_rstn,
nvdla_core2dbb_aw_awid,
nvdla_core2dbb_aw_awaddr,
nvdla_core2dbb_aw_awlen,
nvdla_core2dbb_aw_awsize,
nvdla_core2dbb_aw_awburst,
nvdla_core2dbb_aw_awlock,
nvdla_core2dbb_aw_awcache,
nvdla_core2dbb_aw_awprot,
nvdla_core2dbb_aw_awqos,
nvdla_core2dbb_aw_awregion,
nvdla_core2dbb_aw_awuser,
nvdla_core2dbb_aw_awvalid,
nvdla_core2dbb_aw_awready,
nvdla_core2dbb_w_wid,
nvdla_core2dbb_w_wdata,
nvdla_core2dbb_w_wstrb,
nvdla_core2dbb_w_wlast,
nvdla_core2dbb_w_wuser,
nvdla_core2dbb_w_wvalid,
nvdla_core2dbb_w_wready,
nvdla_core2dbb_b_bid,
nvdla_core2dbb_b_bresp,
nvdla_core2dbb_b_buser,
nvdla_core2dbb_b_bvalid,
nvdla_core2dbb_b_bready,
nvdla_core2dbb_ar_arid,
nvdla_core2dbb_ar_araddr,
nvdla_core2dbb_ar_arlen,
nvdla_core2dbb_ar_arsize,
nvdla_core2dbb_ar_arburst,
nvdla_core2dbb_ar_arlock,
nvdla_core2dbb_ar_arcache,
nvdla_core2dbb_ar_arprot,
nvdla_core2dbb_ar_arqos,
nvdla_core2dbb_ar_arregion,
nvdla_core2dbb_ar_aruser,
nvdla_core2dbb_ar_arvalid,
nvdla_core2dbb_ar_arready,
nvdla_core2dbb_r_rid,
nvdla_core2dbb_r_rdata,
nvdla_core2dbb_r_rresp,
nvdla_core2dbb_r_rlast,
nvdla_core2dbb_r_ruser,
nvdla_core2dbb_r_rvalid,
nvdla_core2dbb_r_rready,
nvdla_core2cvsram_aw_awid,
nvdla_core2cvsram_aw_awaddr,
nvdla_core2cvsram_aw_awlen,
nvdla_core2cvsram_aw_awsize,
nvdla_core2cvsram_aw_awburst,
nvdla_core2cvsram_aw_awlock,
nvdla_core2cvsram_aw_awcache,
nvdla_core2cvsram_aw_awprot,
nvdla_core2cvsram_aw_awqos,
nvdla_core2cvsram_aw_awregion,
nvdla_core2cvsram_aw_awuser,
nvdla_core2cvsram_aw_awvalid,
nvdla_core2cvsram_aw_awready,
nvdla_core2cvsram_w_wid,
nvdla_core2cvsram_w_wdata,
nvdla_core2cvsram_w_wstrb,
nvdla_core2cvsram_w_wlast,
nvdla_core2cvsram_w_wuser,
nvdla_core2cvsram_w_wvalid,
nvdla_core2cvsram_w_wready,
nvdla_core2cvsram_b_bid,
nvdla_core2cvsram_b_bresp,
nvdla_core2cvsram_b_buser,
nvdla_core2cvsram_b_bvalid,
nvdla_core2cvsram_b_bready,
nvdla_core2cvsram_ar_arid,
nvdla_core2cvsram_ar_araddr,
nvdla_core2cvsram_ar_arlen,
nvdla_core2cvsram_ar_arsize,
nvdla_core2cvsram_ar_arburst,
nvdla_core2cvsram_ar_arlock,
nvdla_core2cvsram_ar_arcache,
nvdla_core2cvsram_ar_arprot,
nvdla_core2cvsram_ar_arqos,
nvdla_core2cvsram_ar_arregion,
nvdla_core2cvsram_ar_aruser,
nvdla_core2cvsram_ar_arvalid,
nvdla_core2cvsram_ar_arready,
nvdla_core2cvsram_r_rid,
nvdla_core2cvsram_r_rdata,
nvdla_core2cvsram_r_rresp,
nvdla_core2cvsram_r_rlast,
nvdla_core2cvsram_r_ruser,
nvdla_core2cvsram_r_rvalid,
nvdla_core2cvsram_r_rready,
nvdla_intr,
psel,
penable,
pwrite,
pprot,
paddr,
pwdata,
pstrb,
prdata,
pready,
pslverr
//cdma_wt_done_status0,
//cdma_wt_done_status1,
//cdma_dat_done_status0,
//cdma_dat_done_status1,
//cacc_done_status0,
//cacc_done_status1,
//sdp_done_status0,
//sdp_done_status1,
//pdp_done_status0,
//pdp_done_status1,
//cdp_done_status0,
//cdp_done_status1,
//bdma_done_status0,
//bdma_done_status1,
//cdma_wt_done_0_counter,
//cdma_wt_done_1_counter,
//cdma_dat_done_0_counter,
//cdma_dat_done_1_counter,
//cacc_done_0_counter,
//cacc_done_1_counter,
//sdp_done_0_counter,
//sdp_done_1_counter,
//pdp_done_0_counter,
//pdp_done_1_counter,
//cdp_done_0_counter,
//cdp_done_1_counter,
//bdma_done_0_counter,
//bdma_done_1_counter,
//cdma_img_status,
//cdma_dc_status,
//cdma_wt_status,
//upper_limit_w,
//lower_limit_w,
//sc2mac_wt_a_pvld,
//sc2mac_wt_a_sel,
//sc2mac_wt_a_mask,
//sc2mac_wt_a_data0,
//sc2mac_dat_a_pvld,
//sc2mac_dat_a_mask,
//sc2mac_dat_a_data0,
//mac_a2accu_pvld,
//mac_a2accu_mask,
//mac_a2accu_data0,
//sc2mac_wt_b_pvld,
//sc2mac_wt_b_sel,
//sc2mac_wt_b_mask,
//sc2mac_wt_b_data0,
//sc2mac_dat_b_pvld,
//sc2mac_dat_b_mask,
//sc2mac_dat_b_data0,
//mac_b2accu_pvld,
//mac_b2accu_mask,
//mac_b2accu_data0,
//cacc2sdp_valid,
//cacc2sdp_ready,
//cacc2sdp_pd,
//cacc2sdp_adpt_valid,
//cacc2sdp_adpt_ready,
//cacc2sdp_adpt_pd,
//sdp_dp2wdma_valid,
//sdp_dp2wdma_ready,
//sdp_dp2wdma_pd,
//sdp2pdp_valid,
//sdp2pdp_ready,
//sdp2pdp_pd
);
//input & output ports declaration
////////////////////////////////////////////////////////////////////////
//sys signals
input dla_core_clk;
input dla_csb_clk;
input dla_reset_rstn;
//DBBIF
/*********************************************************************/
//AXI4-AW channel
//output [7:0] nvdla_core2dbb_aw_awid;
output [3:0] nvdla_core2dbb_aw_awid;
(* mark_debug = "TRUE" *)output [64 -1:0] nvdla_core2dbb_aw_awaddr;
//output [3:0] nvdla_core2dbb_aw_awlen;
output [7:0] nvdla_core2dbb_aw_awlen;
output [2:0] nvdla_core2dbb_aw_awsize;//new added
output [1:0] nvdla_core2dbb_aw_awburst;//new added
output nvdla_core2dbb_aw_awlock;//new added
output [3:0] nvdla_core2dbb_aw_awcache;//new added
output [2:0] nvdla_core2dbb_aw_awprot;//new added
output [3:0] nvdla_core2dbb_aw_awqos;//new added
output [3:0] nvdla_core2dbb_aw_awregion;//new added
output [31:0] nvdla_core2dbb_aw_awuser;//new added, not sure about width
(* mark_debug = "TRUE" *)output nvdla_core2dbb_aw_awvalid;
(* mark_debug = "TRUE" *)input nvdla_core2dbb_aw_awready;
//AXI4-W channel
output [7:0] nvdla_core2dbb_w_wid;
(* mark_debug = "TRUE" *)output [256-1:0] nvdla_core2dbb_w_wdata;
(* mark_debug = "TRUE" *)output [256/8-1:0] nvdla_core2dbb_w_wstrb;
(* mark_debug = "TRUE" *)output nvdla_core2dbb_w_wlast;
output [31:0] nvdla_core2dbb_w_wuser;//new added, not sure about width
(* mark_debug = "TRUE" *)output nvdla_core2dbb_w_wvalid;
(* mark_debug = "TRUE" *)input nvdla_core2dbb_w_wready;
//AXI4-B channel
//input [7:0] nvdla_core2dbb_b_bid;
input [5:0] nvdla_core2dbb_b_bid;
input [1:0] nvdla_core2dbb_b_bresp;//new added
input [31:0] nvdla_core2dbb_b_buser;//new added, not sure about signal width
(* mark_debug = "TRUE" *)input nvdla_core2dbb_b_bvalid;
(* mark_debug = "TRUE" *)output nvdla_core2dbb_b_bready;
//AXI4-AR channel
//output [7:0] nvdla_core2dbb_ar_arid;
output [3:0] nvdla_core2dbb_ar_arid;
(* mark_debug = "TRUE" *)output [64 -1:0] nvdla_core2dbb_ar_araddr;
//output [3:0] nvdla_core2dbb_ar_arlen;
output [7:0] nvdla_core2dbb_ar_arlen;
output [2:0] nvdla_core2dbb_ar_arsize;//new added
output [1:0] nvdla_core2dbb_ar_arburst;//new added
output nvdla_core2dbb_ar_arlock;//new added
output [3:0] nvdla_core2dbb_ar_arcache;//new added
output [2:0] nvdla_core2dbb_ar_arprot;//new added
output [3:0] nvdla_core2dbb_ar_arqos;//new added
output [3:0] nvdla_core2dbb_ar_arregion;//new added
output [31:0] nvdla_core2dbb_ar_aruser;//new added, not sure about signal width
(* mark_debug = "TRUE" *)output nvdla_core2dbb_ar_arvalid;
(* mark_debug = "TRUE" *)input nvdla_core2dbb_ar_arready;
//AXI4-R channel
//input [7:0] nvdla_core2dbb_r_rid;
input [5:0] nvdla_core2dbb_r_rid;
(* mark_debug = "TRUE" *)input [256-1:0] nvdla_core2dbb_r_rdata;
input [1:0] nvdla_core2dbb_r_rresp;//new added
(* mark_debug = "TRUE" *)input nvdla_core2dbb_r_rlast;
input [31:0] nvdla_core2dbb_r_ruser;//new added, not sure sbout signal width
(* mark_debug = "TRUE" *)input nvdla_core2dbb_r_rvalid;
(* mark_debug = "TRUE" *)output nvdla_core2dbb_r_rready;
/*********************************************************************/
//SRAMIF
/*********************************************************************/
//AXI4-AW channel
//output [7:0] nvdla_core2cvsram_aw_awid;
output [3:0] nvdla_core2cvsram_aw_awid;
(* mark_debug = "TRUE" *)output [63:0] nvdla_core2cvsram_aw_awaddr;
//output [3:0] nvdla_core2cvsram_aw_awlen;
output [7:0] nvdla_core2cvsram_aw_awlen;
output [2:0] nvdla_core2cvsram_aw_awsize;//new added
output [1:0] nvdla_core2cvsram_aw_awburst;//new added
output nvdla_core2cvsram_aw_awlock;//new added
output [3:0] nvdla_core2cvsram_aw_awcache;//new added
output [2:0] nvdla_core2cvsram_aw_awprot;//new added
output [3:0] nvdla_core2cvsram_aw_awqos;//new added
output [3:0] nvdla_core2cvsram_aw_awregion;//new added
output [31:0] nvdla_core2cvsram_aw_awuser;//new added, not sure about width
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_aw_awvalid; /* data valid */
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_aw_awready; /* data return handshake */
//AXI4-W channel
output [7:0] nvdla_core2cvsram_w_wid;
(* mark_debug = "TRUE" *)output [255:0] nvdla_core2cvsram_w_wdata;
(* mark_debug = "TRUE" *)output [31:0] nvdla_core2cvsram_w_wstrb;
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_w_wlast;
output [31:0] nvdla_core2cvsram_w_wuser;//new added, not sure about width
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_w_wvalid; /* data valid */
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_w_wready; /* data return handshake */
//AXI4-B channel
//input [7:0] nvdla_core2cvsram_b_bid;
input [5:0] nvdla_core2cvsram_b_bid;
input [1:0] nvdla_core2cvsram_b_bresp;//new added
input [31:0] nvdla_core2cvsram_b_buser;//new added, not sure about signal width
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_b_bvalid; /* data valid */
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_b_bready; /* data return handshake */
//AXI4-AR channel
//output [7:0] nvdla_core2cvsram_ar_arid;
output [3:0] nvdla_core2cvsram_ar_arid;
(* mark_debug = "TRUE" *)output [63:0] nvdla_core2cvsram_ar_araddr;
//output [3:0] nvdla_core2cvsram_ar_arlen;
output [7:0] nvdla_core2cvsram_ar_arlen;
output [2:0] nvdla_core2cvsram_ar_arsize;//new added
output [1:0] nvdla_core2cvsram_ar_arburst;//new added
output nvdla_core2cvsram_ar_arlock;//new added
output [3:0] nvdla_core2cvsram_ar_arcache;//new added
output [2:0] nvdla_core2cvsram_ar_arprot;//new added
output [3:0] nvdla_core2cvsram_ar_arqos;//new added
output [3:0] nvdla_core2cvsram_ar_arregion;//new added
output [31:0] nvdla_core2cvsram_ar_aruser;//new added, not sure about signal width
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_ar_arvalid; /* data valid */
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_ar_arready; /* data return handshake */
//AXI4-R channel
//input [7:0] nvdla_core2cvsram_r_rid;
input [5:0] nvdla_core2cvsram_r_rid;
(* mark_debug = "TRUE" *)input [255:0] nvdla_core2cvsram_r_rdata;
input [1:0] nvdla_core2cvsram_r_rresp;//new added
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_r_rlast;
input [31:0] nvdla_core2cvsram_r_ruser;//new added, not sure sbout signal width
(* mark_debug = "TRUE" *)input nvdla_core2cvsram_r_rvalid; /* data valid */
(* mark_debug = "TRUE" *)output nvdla_core2cvsram_r_rready; /* data return handshake */
/*********************************************************************/
//NVDLA interrupt
(* mark_debug = "TRUE" *)output nvdla_intr;
//power contrl signals, tied to 0 when connected to NVDLA
//input [31:0] nvdla_pwrbus_ram_c_pd;
//input [31:0] nvdla_pwrbus_ram_ma_pd;
//input [31:0] nvdla_pwrbus_ram_mb_pd;
//input [31:0] nvdla_pwrbus_ram_p_pd;
//input [31:0] nvdla_pwrbus_ram_o_pd;
//input [31:0] nvdla_pwrbus_ram_a_pd;
//APB interface, apb2csb integrated
//input pclk;
//input prstn;
(* mark_debug = "TRUE" *)input psel;
(* mark_debug = "TRUE" *)input penable;
(* mark_debug = "TRUE" *)input pwrite;
(* mark_debug = "TRUE" *)input pprot;
(* mark_debug = "TRUE" *)input [31:0] paddr;
(* mark_debug = "TRUE" *)input [31:0] pwdata;
(* mark_debug = "TRUE" *)input [3:0] pstrb;
(* mark_debug = "TRUE" *)output [31:0] prdata;
(* mark_debug = "TRUE" *)output pready;
(* mark_debug = "TRUE" *)output pslverr;
////////////////////////////////////////////////////////////////////////
//
//for debug
////////////////////////////////////////////////////////////////////////
wire cdma_wt_done_status0;
wire cdma_wt_done_status1;
wire cdma_dat_done_status0;
wire cdma_dat_done_status1;
wire cacc_done_status0;
wire cacc_done_status1;
wire sdp_done_status0;
wire sdp_done_status1;
wire pdp_done_status0;
wire pdp_done_status1;
wire cdp_done_status0;
wire cdp_done_status1;
wire bdma_done_status0;
wire bdma_done_status1;
(* mark_debug = "TRUE" *)wire [31:0] cdma_wt_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] cdma_wt_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] cdma_dat_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] cdma_dat_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] cacc_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] cacc_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] sdp_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] sdp_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] pdp_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] pdp_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] cdp_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] cdp_done_1_counter;
(* mark_debug = "TRUE" *)wire [31:0] bdma_done_0_counter;
(* mark_debug = "TRUE" *)wire [31:0] bdma_done_1_counter;
wire [1:0] cdma_img_status;
wire [1:0] cdma_dc_status;
wire [1:0] cdma_wt_status;
wire [6:0] upper_limit_w;
wire [6:0] lower_limit_w;
wire sc2mac_wt_a_pvld;
wire [32/2-1:0] sc2mac_wt_a_sel;
wire [64 -1:0] sc2mac_wt_a_mask;
wire [8 -1:0] sc2mac_wt_a_data0;
wire sc2mac_dat_a_pvld;
wire [64 -1:0] sc2mac_dat_a_mask;
wire [8 -1:0] sc2mac_dat_a_data0;
wire mac_a2accu_pvld;
wire [32/2-1:0] mac_a2accu_mask;
wire [22 -1:0] mac_a2accu_data0;
wire sc2mac_wt_b_pvld;
wire [32/2-1:0] sc2mac_wt_b_sel;
wire [64 -1:0] sc2mac_wt_b_mask;
wire [8 -1:0] sc2mac_wt_b_data0;
wire sc2mac_dat_b_pvld;
wire [64 -1:0] sc2mac_dat_b_mask;
wire [8 -1:0] sc2mac_dat_b_data0;
wire mac_b2accu_pvld;
wire [32/2-1:0] mac_b2accu_mask;
wire [22 -1:0] mac_b2accu_data0;
wire cacc2sdp_valid;
wire cacc2sdp_ready;
wire [32*16+2-1:0] cacc2sdp_pd;
wire cacc2sdp_adpt_valid;
wire cacc2sdp_adpt_ready;
wire [32*16 +1:0] cacc2sdp_adpt_pd;
wire sdp_dp2wdma_valid;
wire sdp_dp2wdma_ready;
wire [32*8 -1:0] sdp_dp2wdma_pd;
wire sdp2pdp_valid;
wire sdp2pdp_ready;
wire [16*8 -1:0] sdp2pdp_pd;
////////////////////////////////////////////////////////////////////////
//wire declarations
////////////////////////////////////////////////////////////////////////
wire csb2nvdla_valid;
wire csb2nvdla_ready;
wire [15:0] csb2nvdla_addr;
wire [31:0] csb2nvdla_wdat;
wire csb2nvdla_write;
wire csb2nvdla_nposted;
wire nvdla2csb_valid;
wire [31:0] nvdla2csb_data;
wire [7:0] nvdla_core2dbb_aw_awid_t;
wire [3:0] nvdla_core2dbb_aw_awlen_t;
wire [7:0] nvdla_core2dbb_ar_arid_t;
wire [3:0] nvdla_core2dbb_ar_arlen_t;
wire [7:0] nvdla_core2cvsram_aw_awid_t;
wire [3:0] nvdla_core2cvsram_aw_awlen_t;
wire [7:0] nvdla_core2cvsram_ar_arid_t;
wire [3:0] nvdla_core2cvsram_ar_arlen_t;
////////////////////////////////////////////////////////////////////////
//sub-module instantiation
////////////////////////////////////////////////////////////////////////
//
NV_NVDLA_apb2csb U_NVDLA_APB2CSB (
.pclk (dla_csb_clk )
,.prstn (dla_reset_rstn )
,.psel (psel )
,.penable (penable )
,.pwrite (pwrite )
,.paddr (paddr )
,.pwdata (pwdata )
,.prdata (prdata )
,.pready (pready )
,.csb2nvdla_valid (csb2nvdla_valid )
,.csb2nvdla_ready (csb2nvdla_ready )
,.csb2nvdla_addr (csb2nvdla_addr )
,.csb2nvdla_wdat (csb2nvdla_wdat )
,.csb2nvdla_write (csb2nvdla_write )
,.csb2nvdla_nposted (csb2nvdla_nposted )
,.nvdla2csb_valid (nvdla2csb_valid )
,.nvdla2csb_data (nvdla2csb_data )
);
//
NV_nvdla U_NVDLA_CORE (
//sys signals
.dla_core_clk (dla_core_clk ) //|< i
,.dla_csb_clk (dla_csb_clk ) //|< i
,.global_clk_ovr_on (1'b0 ) //|< i
,.tmc2slcg_disable_clock_gating(1'b0 ) //|< i
,.dla_reset_rstn (dla_reset_rstn ) //|< i
,.direct_reset_ (1'b0 ) //|< i
,.test_mode (1'b0 ) //|< i
//csb interface
,.csb2nvdla_valid (csb2nvdla_valid )//|< i
,.csb2nvdla_ready (csb2nvdla_ready )//|> o
,.csb2nvdla_addr (csb2nvdla_addr )//|< i
,.csb2nvdla_wdat (csb2nvdla_wdat )//|< i
,.csb2nvdla_write (csb2nvdla_write )//|< i
,.csb2nvdla_nposted (csb2nvdla_nposted )//|< i
,.nvdla2csb_valid (nvdla2csb_valid )//|> o
,.nvdla2csb_data (nvdla2csb_data )//|> o
,.nvdla2csb_wr_complete ( )//|> o
//DBBIF --- AXI4 interface
,.nvdla_core2dbb_aw_awvalid (nvdla_core2dbb_aw_awvalid )//|> o
,.nvdla_core2dbb_aw_awready (nvdla_core2dbb_aw_awready )//|< i
,.nvdla_core2dbb_aw_awid (nvdla_core2dbb_aw_awid_t )//|> o
,.nvdla_core2dbb_aw_awlen (nvdla_core2dbb_aw_awlen_t )//|> o
,.nvdla_core2dbb_aw_awaddr (nvdla_core2dbb_aw_awaddr )//|> o
,.nvdla_core2dbb_w_wvalid (nvdla_core2dbb_w_wvalid )//|> o
,.nvdla_core2dbb_w_wready (nvdla_core2dbb_w_wready )//|< i
,.nvdla_core2dbb_w_wdata (nvdla_core2dbb_w_wdata )//|> o
,.nvdla_core2dbb_w_wstrb (nvdla_core2dbb_w_wstrb )//|> o
,.nvdla_core2dbb_w_wlast (nvdla_core2dbb_w_wlast )//|> o
,.nvdla_core2dbb_b_bvalid (nvdla_core2dbb_b_bvalid )//|< i
,.nvdla_core2dbb_b_bready (nvdla_core2dbb_b_bready )//|> o
,.nvdla_core2dbb_b_bid ({2'b00,nvdla_core2dbb_b_bid} )//|< i
,.nvdla_core2dbb_ar_arvalid (nvdla_core2dbb_ar_arvalid )//|> o
,.nvdla_core2dbb_ar_arready (nvdla_core2dbb_ar_arready )//|< i
,.nvdla_core2dbb_ar_arid (nvdla_core2dbb_ar_arid_t )//|> o
,.nvdla_core2dbb_ar_arlen (nvdla_core2dbb_ar_arlen_t )//|> o
,.nvdla_core2dbb_ar_araddr (nvdla_core2dbb_ar_araddr )//|> o
,.nvdla_core2dbb_r_rvalid (nvdla_core2dbb_r_rvalid )//|< i
,.nvdla_core2dbb_r_rready (nvdla_core2dbb_r_rready )//|> o
,.nvdla_core2dbb_r_rid ({2'b00,nvdla_core2dbb_r_rid} )//|< i
,.nvdla_core2dbb_r_rlast (nvdla_core2dbb_r_rlast )//|< i
,.nvdla_core2dbb_r_rdata (nvdla_core2dbb_r_rdata )//|< i
//SRAMIF --- AXI4 interface
,.nvdla_core2cvsram_aw_awvalid (nvdla_core2cvsram_aw_awvalid )//|> o
,.nvdla_core2cvsram_aw_awready (nvdla_core2cvsram_aw_awready )//|< i
,.nvdla_core2cvsram_aw_awid (nvdla_core2cvsram_aw_awid_t )//|> o
,.nvdla_core2cvsram_aw_awlen (nvdla_core2cvsram_aw_awlen_t )//|> o
,.nvdla_core2cvsram_aw_awaddr (nvdla_core2cvsram_aw_awaddr )//|> o
,.nvdla_core2cvsram_w_wvalid (nvdla_core2cvsram_w_wvalid )//|> o
,.nvdla_core2cvsram_w_wready (nvdla_core2cvsram_w_wready )//|< i
,.nvdla_core2cvsram_w_wdata (nvdla_core2cvsram_w_wdata )//|> o
,.nvdla_core2cvsram_w_wstrb (nvdla_core2cvsram_w_wstrb )//|> o
,.nvdla_core2cvsram_w_wlast (nvdla_core2cvsram_w_wlast )//|> o
,.nvdla_core2cvsram_b_bvalid (nvdla_core2cvsram_b_bvalid )//|< i
,.nvdla_core2cvsram_b_bready (nvdla_core2cvsram_b_bready )//|> o
,.nvdla_core2cvsram_b_bid ({2'b00,nvdla_core2cvsram_b_bid} )//|< i
,.nvdla_core2cvsram_ar_arvalid (nvdla_core2cvsram_ar_arvalid )//|> o
,.nvdla_core2cvsram_ar_arready (nvdla_core2cvsram_ar_arready )//|< i
,.nvdla_core2cvsram_ar_arid (nvdla_core2cvsram_ar_arid_t )//|> o
,.nvdla_core2cvsram_ar_arlen (nvdla_core2cvsram_ar_arlen_t )//|> o
,.nvdla_core2cvsram_ar_araddr (nvdla_core2cvsram_ar_araddr )//|> o
,.nvdla_core2cvsram_r_rvalid (nvdla_core2cvsram_r_rvalid )//|< i
,.nvdla_core2cvsram_r_rready (nvdla_core2cvsram_r_rready )//|> o
,.nvdla_core2cvsram_r_rid ({2'b00,nvdla_core2cvsram_r_rid} )//|< i
,.nvdla_core2cvsram_r_rlast (nvdla_core2cvsram_r_rlast )//|< i
,.nvdla_core2cvsram_r_rdata (nvdla_core2cvsram_r_rdata )//|< i
//NVDLA interrupt
,.dla_intr (nvdla_intr )//|> o
//power control signals
,.nvdla_pwrbus_ram_c_pd (32'd0 )//|< i
,.nvdla_pwrbus_ram_ma_pd (32'd0 )//|< i *
,.nvdla_pwrbus_ram_mb_pd (32'd0 )//|< i *
,.nvdla_pwrbus_ram_p_pd (32'd0 )//|< i
,.nvdla_pwrbus_ram_o_pd (32'd0 )//|< i
,.nvdla_pwrbus_ram_a_pd (32'd0 )//|< i
//for debug
,.cdma_wt_done_status0 (cdma_wt_done_status0 )
,.cdma_wt_done_status1 (cdma_wt_done_status1 )
,.cdma_dat_done_status0 (cdma_dat_done_status0 )
,.cdma_dat_done_status1 (cdma_dat_done_status1 )
,.cacc_done_status0 (cacc_done_status0 )
,.cacc_done_status1 (cacc_done_status1 )
,.sdp_done_status0 (sdp_done_status0 )
,.sdp_done_status1 (sdp_done_status1 )
,.pdp_done_status0 (pdp_done_status0 )
,.pdp_done_status1 (pdp_done_status1 )
,.cdp_done_status0 (cdp_done_status0 )
,.cdp_done_status1 (cdp_done_status1 )
,.bdma_done_status0 (bdma_done_status0 )
,.bdma_done_status1 (bdma_done_status1 )
,.cdma_wt_done_0_counter (cdma_wt_done_0_counter )
,.cdma_wt_done_1_counter (cdma_wt_done_1_counter )
,.cdma_dat_done_0_counter (cdma_dat_done_0_counter )
,.cdma_dat_done_1_counter (cdma_dat_done_1_counter )
,.cacc_done_0_counter (cacc_done_0_counter )
,.cacc_done_1_counter (cacc_done_1_counter )
,.sdp_done_0_counter (sdp_done_0_counter )
,.sdp_done_1_counter (sdp_done_1_counter )
,.pdp_done_0_counter (pdp_done_0_counter )
,.pdp_done_1_counter (pdp_done_1_counter )
,.cdp_done_0_counter (cdp_done_0_counter )
,.cdp_done_1_counter (cdp_done_1_counter )
,.bdma_done_0_counter (bdma_done_0_counter )
,.bdma_done_1_counter (bdma_done_1_counter )
,.cdma_img_status (cdma_img_status )
,.cdma_dc_status (cdma_dc_status )
,.cdma_wt_status (cdma_wt_status )
,.upper_limit_w (upper_limit_w )
,.lower_limit_w (lower_limit_w )
,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld )
,.sc2mac_wt_a_sel (sc2mac_wt_a_sel )
,.sc2mac_wt_a_mask (sc2mac_wt_a_mask )
,.sc2mac_wt_a_data0 (sc2mac_wt_a_data0 )
,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld )
,.sc2mac_dat_a_mask (sc2mac_dat_a_mask )
,.sc2mac_dat_a_data0 (sc2mac_dat_a_data0 )
,.mac_a2accu_pvld (mac_a2accu_pvld )
,.mac_a2accu_mask (mac_a2accu_mask )
,.mac_a2accu_data0 (mac_a2accu_data0 )
,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld )
,.sc2mac_wt_b_sel (sc2mac_wt_b_sel )
,.sc2mac_wt_b_mask (sc2mac_wt_b_mask )
,.sc2mac_wt_b_data0 (sc2mac_wt_b_data0 )
,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld )
,.sc2mac_dat_b_mask (sc2mac_dat_b_mask )
,.sc2mac_dat_b_data0 (sc2mac_dat_b_data0 )
,.mac_b2accu_pvld (mac_b2accu_pvld )
,.mac_b2accu_mask (mac_b2accu_mask )
,.mac_b2accu_data0 (mac_b2accu_data0 )
,.cacc2sdp_valid (cacc2sdp_valid )
,.cacc2sdp_ready (cacc2sdp_ready )
,.cacc2sdp_pd (cacc2sdp_pd )
,.cacc2sdp_adpt_valid (cacc2sdp_adpt_valid )
,.cacc2sdp_adpt_ready (cacc2sdp_adpt_ready )
,.cacc2sdp_adpt_pd (cacc2sdp_adpt_pd )
,.sdp_dp2wdma_ready (sdp_dp2wdma_ready )
,.sdp_dp2wdma_valid (sdp_dp2wdma_valid )
,.sdp_dp2wdma_pd (sdp_dp2wdma_pd )
,.sdp2pdp_valid (sdp2pdp_valid )
,.sdp2pdp_ready (sdp2pdp_ready )
,.sdp2pdp_pd (sdp2pdp_pd )
);
////////////////////////////////////////////////////////////////////////
//
//output assignment
////////////////////////////////////////////////////////////////////////
assign nvdla_core2dbb_aw_awid = nvdla_core2dbb_aw_awid_t[3:0];
assign nvdla_core2dbb_aw_awlen = {4'd0,nvdla_core2dbb_aw_awlen_t};
assign nvdla_core2dbb_aw_awsize = 3'b101 ;//64 bit, needed to be verified
assign nvdla_core2dbb_aw_awburst = 2'b01 ;//INCR burst type
assign nvdla_core2dbb_aw_awlock = 1'b0 ;//normal access
assign nvdla_core2dbb_aw_awcache = 4'b0000;//non-bufferable
assign nvdla_core2dbb_aw_awprot = 3'b000 ;//unprivileged & secure & data access
assign nvdla_core2dbb_aw_awqos = 4'b0000;//no QOS scheme
assign nvdla_core2dbb_aw_awregion = 4'b0000;//default value
assign nvdla_core2dbb_aw_awuser = 32'd0 ;//not sure about width
assign nvdla_core2dbb_w_wid = 8'd0 ;//not needed for AXI4
assign nvdla_core2dbb_w_wuser = 32'd0 ;//not sure about width
assign nvdla_core2dbb_ar_arid = nvdla_core2dbb_ar_arid_t[3:0];
assign nvdla_core2dbb_ar_arlen = {4'd0,nvdla_core2dbb_ar_arlen_t};
assign nvdla_core2dbb_ar_arsize = 3'b101 ;//64 bit
assign nvdla_core2dbb_ar_arburst = 2'b01 ;//INCE burst type
assign nvdla_core2dbb_ar_arlock = 1'b0 ;//normal access
assign nvdla_core2dbb_ar_arcache = 4'b0000;//non-bufferable
assign nvdla_core2dbb_ar_arprot = 3'b000 ;//unprivileged & secure & data access
assign nvdla_core2dbb_ar_arqos = 4'b0000;//no QOS scheme
assign nvdla_core2dbb_ar_arregion = 4'b0000;//default value
assign nvdla_core2dbb_ar_aruser = 32'd0 ;//not sure about signal width
assign nvdla_core2cvsram_aw_awid = nvdla_core2cvsram_aw_awid_t[3:0];
assign nvdla_core2cvsram_aw_awlen = {4'd0,nvdla_core2cvsram_aw_awlen_t};
assign nvdla_core2cvsram_aw_awsize = 3'b101 ;//64 bit, needed to be verified
assign nvdla_core2cvsram_aw_awburst = 2'b01 ;//INCR burst type
assign nvdla_core2cvsram_aw_awlock = 1'b0 ;//normal access
assign nvdla_core2cvsram_aw_awcache = 4'b0000;//non-bufferable
assign nvdla_core2cvsram_aw_awprot = 3'b000 ;//unprivileged & secure & data access
assign nvdla_core2cvsram_aw_awqos = 4'b0000;//no QOS scheme
assign nvdla_core2cvsram_aw_awregion = 4'b0000;//default value
assign nvdla_core2cvsram_aw_awuser = 32'd0 ;//not sure about width
assign nvdla_core2cvsram_w_wid = 8'd0 ;//not needed for AXI4
assign nvdla_core2cvsram_w_wuser = 32'd0 ;//not sure about width
assign nvdla_core2cvsram_ar_arid = nvdla_core2cvsram_ar_arid_t[3:0];
assign nvdla_core2cvsram_ar_arlen = {4'd0,nvdla_core2cvsram_ar_arlen_t};
assign nvdla_core2cvsram_ar_arsize = 3'b101 ;//64 bit
assign nvdla_core2cvsram_ar_arburst = 2'b01 ;//INCE burst type
assign nvdla_core2cvsram_ar_arlock = 1'b0 ;//normal access
assign nvdla_core2cvsram_ar_arcache = 4'b0000;//non-bufferable
assign nvdla_core2cvsram_ar_arprot = 3'b000 ;//unprivileged & secure & data access
assign nvdla_core2cvsram_ar_arqos = 4'b0000;//no QOS scheme
assign nvdla_core2cvsram_ar_arregion = 4'b0000;//default value
assign nvdla_core2cvsram_ar_aruser = 32'd0 ;//not sure about signal width
assign pslverr = 1'b0 ;
////////////////////////////////////////////////////////////////////////
//
endmodule // NV_nvdla_top |
module NV_NVDLA_SDP_erdma (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,erdma_disable //|< i
,erdma_slcg_op_en //|< i
,sdp_e2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2cvif_rd_req_pd //|> o
,sdp_e2cvif_rd_req_valid //|> o
,sdp_e2cvif_rd_req_ready //|< i
,cvif2sdp_e_rd_rsp_pd //|< i
,cvif2sdp_e_rd_rsp_valid //|< i
,cvif2sdp_e_rd_rsp_ready //|> o
,sdp_e2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2mcif_rd_req_pd //|> o
,sdp_e2mcif_rd_req_valid //|> o
,sdp_e2mcif_rd_req_ready //|< i
,mcif2sdp_e_rd_rsp_pd //|< i
,mcif2sdp_e_rd_rsp_valid //|< i
,mcif2sdp_e_rd_rsp_ready //|> o
,reg2dp_erdma_data_mode //|< i
,reg2dp_erdma_data_size //|< i
,reg2dp_erdma_data_use //|< i
,reg2dp_erdma_ram_type //|< i
,reg2dp_ew_base_addr_high //|< i
,reg2dp_ew_base_addr_low //|< i
,reg2dp_ew_line_stride //|< i
,reg2dp_ew_surface_stride //|< i
,reg2dp_batch_number //|< i
,reg2dp_channel //|< i
,reg2dp_height //|< i
,reg2dp_width //|< i
,reg2dp_op_en //|< i
,reg2dp_out_precision //|< i
,reg2dp_perf_dma_en //|< i
,reg2dp_proc_precision //|< i
,reg2dp_winograd //|< i
,dp2reg_erdma_stall //|> o
,dp2reg_done //|> o
,sdp_erdma2dp_alu_ready //|< i
,sdp_erdma2dp_mul_ready //|< i
,sdp_erdma2dp_alu_pd //|> o
,sdp_erdma2dp_alu_valid //|> o
,sdp_erdma2dp_mul_pd //|> o
,sdp_erdma2dp_mul_valid //|> o
);
//
// NV_NVDLA_SDP_erdma_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
output sdp_e2cvif_rd_req_valid;
input sdp_e2cvif_rd_req_ready;
output [79 -1:0] sdp_e2cvif_rd_req_pd;
input cvif2sdp_e_rd_rsp_valid;
output cvif2sdp_e_rd_rsp_ready;
input [257 -1:0] cvif2sdp_e_rd_rsp_pd;
output sdp_e2cvif_rd_cdt_lat_fifo_pop;
output sdp_e2mcif_rd_req_valid;
input sdp_e2mcif_rd_req_ready;
output [79 -1:0] sdp_e2mcif_rd_req_pd;
input mcif2sdp_e_rd_rsp_valid;
output mcif2sdp_e_rd_rsp_ready;
input [257 -1:0] mcif2sdp_e_rd_rsp_pd;
output sdp_e2mcif_rd_cdt_lat_fifo_pop;
output sdp_erdma2dp_alu_valid;
input sdp_erdma2dp_alu_ready;
output [32*16:0] sdp_erdma2dp_alu_pd;
output sdp_erdma2dp_mul_valid;
input sdp_erdma2dp_mul_ready;
output [32*16:0] sdp_erdma2dp_mul_pd;
input reg2dp_erdma_data_mode;
input reg2dp_erdma_data_size;
input [1:0] reg2dp_erdma_data_use;
input reg2dp_erdma_ram_type;
input [31:0] reg2dp_ew_base_addr_high;
input [31-5:0] reg2dp_ew_base_addr_low;
input [31-5:0] reg2dp_ew_line_stride;
input [31-5:0] reg2dp_ew_surface_stride;
input [4:0] reg2dp_batch_number;
input [12:0] reg2dp_channel;
input [12:0] reg2dp_height;
input reg2dp_op_en;
input [1:0] reg2dp_out_precision;
input reg2dp_perf_dma_en;
input [1:0] reg2dp_proc_precision;
input [12:0] reg2dp_width;
input reg2dp_winograd;
output [31:0] dp2reg_erdma_stall;
output dp2reg_done;
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
input erdma_slcg_op_en;
input erdma_disable;
wire nvdla_gated_clk;
wire op_load;
wire eg_done;
reg layer_process;
wire [15:0] ig2cq_pd;
wire ig2cq_prdy;
wire ig2cq_pvld;
wire [15:0] cq2eg_pd;
wire cq2eg_prdy;
wire cq2eg_pvld;
wire dma_rd_cdt_lat_fifo_pop;
wire [79 -1:0] dma_rd_req_pd;
wire dma_rd_req_rdy;
wire dma_rd_req_vld;
wire [257 -1:0] dma_rd_rsp_pd;
wire dma_rd_rsp_rdy;
wire dma_rd_rsp_vld;
wire [257 -1:0] lat_fifo_rd_pd;
wire lat_fifo_rd_pvld;
wire lat_fifo_rd_prdy;
// Layer Switch
assign op_load = reg2dp_op_en & !layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
layer_process <= 1'b0;
end else begin
if (op_load) begin
layer_process <= 1'b1;
end else if (eg_done) begin
layer_process <= 1'b0;
end
end
end
assign dp2reg_done = eg_done;
//=======================================
NV_NVDLA_SDP_ERDMA_gate u_gate (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.erdma_disable (erdma_disable) //|< i
,.erdma_slcg_op_en (erdma_slcg_op_en) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_gated_clk (nvdla_gated_clk) //|> w
);
NV_NVDLA_SDP_RDMA_ig u_ig (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.op_load (op_load) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|> w
,.ig2cq_prdy (ig2cq_prdy) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|> w
,.dma_rd_req_vld (dma_rd_req_vld) //|> w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w
,.reg2dp_op_en (reg2dp_op_en) //|< i
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i
,.reg2dp_winograd (reg2dp_winograd) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i
,.reg2dp_base_addr_high (reg2dp_ew_base_addr_high[31:0]) //|< i
,.reg2dp_base_addr_low (reg2dp_ew_base_addr_low[31-5:0]) //|< i
,.reg2dp_line_stride (reg2dp_ew_line_stride[31-5:0]) //|< i
,.reg2dp_surface_stride (reg2dp_ew_surface_stride[31-5:0]) //|< i
,.dp2reg_rdma_stall (dp2reg_erdma_stall[31:0]) //|> o
);
//: my $depth = 256;
//: my $width = 16;
//: print "NV_NVDLA_SDP_ERDMA_cq_${depth}x${width} u_cq ( \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_ERDMA_cq_256x16 u_cq (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.ig2cq_prdy (ig2cq_prdy) //|> w
,.ig2cq_pvld (ig2cq_pvld) //|< w
,.ig2cq_pd (ig2cq_pd[15:0]) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|> w
);
NV_NVDLA_SDP_RDMA_eg u_eg (
.nvdla_core_clk (nvdla_gated_clk) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.op_load (op_load) //|< w
,.eg_done (eg_done) //|> w
,.cq2eg_pd (cq2eg_pd[15:0]) //|< w
,.cq2eg_pvld (cq2eg_pvld) //|< w
,.cq2eg_prdy (cq2eg_prdy) //|> w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w
,.lat_fifo_rd_pd (lat_fifo_rd_pd[257 -1:0]) //|< w
,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w
,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w
,.sdp_rdma2dp_alu_ready (sdp_erdma2dp_alu_ready) //|< i
,.sdp_rdma2dp_mul_ready (sdp_erdma2dp_mul_ready) //|< i
,.sdp_rdma2dp_alu_pd (sdp_erdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_rdma2dp_alu_valid (sdp_erdma2dp_alu_valid) //|> o
,.sdp_rdma2dp_mul_pd (sdp_erdma2dp_mul_pd[32*16:0]) //|> o
,.sdp_rdma2dp_mul_valid (sdp_erdma2dp_mul_valid) //|> o
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i
,.reg2dp_channel (reg2dp_channel[12:0]) //|< i
,.reg2dp_height (reg2dp_height[12:0]) //|< i
,.reg2dp_width (reg2dp_width[12:0]) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i
,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i
,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i
,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i
);
//: my $depth = 256;
//: my $width = 257;
//: print "NV_NVDLA_SDP_ERDMA_lat_fifo_${depth}x${width} u_lat_fifo (\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_SDP_ERDMA_lat_fifo_256x257 u_lat_fifo (
//| eperl: generated_end (DO NOT EDIT ABOVE)
.nvdla_core_clk (nvdla_gated_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
,.lat_wr_prdy (dma_rd_rsp_rdy)
,.lat_wr_pvld (dma_rd_rsp_vld)
,.lat_wr_pd (dma_rd_rsp_pd[257 -1:0])
,.lat_rd_prdy (lat_fifo_rd_prdy)
,.lat_rd_pvld (lat_fifo_rd_pvld)
,.lat_rd_pd (lat_fifo_rd_pd[257 -1:0])
);
NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif (
.nvdla_core_clk (nvdla_gated_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2cvif_rd_req_pd (sdp_e2cvif_rd_req_pd[79 -1:0]) //|> o
,.sdp2cvif_rd_req_valid (sdp_e2cvif_rd_req_valid) //|> o
,.sdp2cvif_rd_req_ready (sdp_e2cvif_rd_req_ready) //|< i
,.cvif2sdp_rd_rsp_pd (cvif2sdp_e_rd_rsp_pd[257 -1:0]) //|< i
,.cvif2sdp_rd_rsp_valid (cvif2sdp_e_rd_rsp_valid) //|< i
,.cvif2sdp_rd_rsp_ready (cvif2sdp_e_rd_rsp_ready) //|> o
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[79 -1:0]) //|> o
,.sdp2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid) //|> o
,.sdp2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready) //|< i
,.mcif2sdp_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[257 -1:0]) //|< i
,.mcif2sdp_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid) //|< i
,.mcif2sdp_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready) //|> o
,.dma_rd_req_ram_type (reg2dp_erdma_ram_type) //|< w
,.dma_rd_rsp_ram_type (reg2dp_erdma_ram_type) //|< w
,.dma_rd_req_pd (dma_rd_req_pd[79 -1:0]) //|< w
,.dma_rd_req_vld (dma_rd_req_vld) //|< w
,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w
,.dma_rd_rsp_pd (dma_rd_rsp_pd[257 -1:0]) //|> w
,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w
,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w
,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w
);
endmodule // NV_NVDLA_SDP_erdma |
module NV_nvdla_top (
dla_core_clk,
dla_csb_clk,
dla_reset_rstn,
nvdla_core2dbb_aw_awid,
nvdla_core2dbb_aw_awaddr,
nvdla_core2dbb_aw_awlen,
nvdla_core2dbb_aw_awsize,
nvdla_core2dbb_aw_awburst,
nvdla_core2dbb_aw_awlock,
nvdla_core2dbb_aw_awcache,
nvdla_core2dbb_aw_awprot,
nvdla_core2dbb_aw_awqos,
nvdla_core2dbb_aw_awregion,
nvdla_core2dbb_aw_awuser,
nvdla_core2dbb_aw_awvalid,
nvdla_core2dbb_aw_awready,
nvdla_core2dbb_w_wid,
nvdla_core2dbb_w_wdata,
nvdla_core2dbb_w_wstrb,
nvdla_core2dbb_w_wlast,
nvdla_core2dbb_w_wuser,
nvdla_core2dbb_w_wvalid,
nvdla_core2dbb_w_wready,
nvdla_core2dbb_b_bid,
nvdla_core2dbb_b_bresp,
nvdla_core2dbb_b_buser,
nvdla_core2dbb_b_bvalid,
nvdla_core2dbb_b_bready,
nvdla_core2dbb_ar_arid,
nvdla_core2dbb_ar_araddr,
nvdla_core2dbb_ar_arlen,
nvdla_core2dbb_ar_arsize,
nvdla_core2dbb_ar_arburst,
nvdla_core2dbb_ar_arlock,
nvdla_core2dbb_ar_arcache,
nvdla_core2dbb_ar_arprot,
nvdla_core2dbb_ar_arqos,
nvdla_core2dbb_ar_arregion,
nvdla_core2dbb_ar_aruser,
nvdla_core2dbb_ar_arvalid,
nvdla_core2dbb_ar_arready,
nvdla_core2dbb_r_rid,
nvdla_core2dbb_r_rdata,
nvdla_core2dbb_r_rresp,
nvdla_core2dbb_r_rlast,
nvdla_core2dbb_r_ruser,
nvdla_core2dbb_r_rvalid,
nvdla_core2dbb_r_rready,
nvdla_core2cvsram_aw_awid,
nvdla_core2cvsram_aw_awaddr,
nvdla_core2cvsram_aw_awlen,
nvdla_core2cvsram_aw_awsize,
nvdla_core2cvsram_aw_awburst,
nvdla_core2cvsram_aw_awlock,
nvdla_core2cvsram_aw_awcache,
nvdla_core2cvsram_aw_awprot,
nvdla_core2cvsram_aw_awqos,
nvdla_core2cvsram_aw_awregion,
nvdla_core2cvsram_aw_awuser,
nvdla_core2cvsram_aw_awvalid,
nvdla_core2cvsram_aw_awready,
nvdla_core2cvsram_w_wid,
nvdla_core2cvsram_w_wdata,
nvdla_core2cvsram_w_wstrb,
nvdla_core2cvsram_w_wlast,
nvdla_core2cvsram_w_wuser,
nvdla_core2cvsram_w_wvalid,
nvdla_core2cvsram_w_wready,
nvdla_core2cvsram_b_bid,
nvdla_core2cvsram_b_bresp,
nvdla_core2cvsram_b_buser,
nvdla_core2cvsram_b_bvalid,
nvdla_core2cvsram_b_bready,
nvdla_core2cvsram_ar_arid,
nvdla_core2cvsram_ar_araddr,
nvdla_core2cvsram_ar_arlen,
nvdla_core2cvsram_ar_arsize,
nvdla_core2cvsram_ar_arburst,
nvdla_core2cvsram_ar_arlock,
nvdla_core2cvsram_ar_arcache,
nvdla_core2cvsram_ar_arprot,
nvdla_core2cvsram_ar_arqos,
nvdla_core2cvsram_ar_arregion,
nvdla_core2cvsram_ar_aruser,
nvdla_core2cvsram_ar_arvalid,
nvdla_core2cvsram_ar_arready,
nvdla_core2cvsram_r_rid,
nvdla_core2cvsram_r_rdata,
nvdla_core2cvsram_r_rresp,
nvdla_core2cvsram_r_rlast,
nvdla_core2cvsram_r_ruser,
nvdla_core2cvsram_r_rvalid,
nvdla_core2cvsram_r_rready,
nvdla_intr,
psel,
penable,
pwrite,
pprot,
paddr,
pwdata,
pstrb,
prdata,
pready,
pslverr
//cdma_wt_done_status0,
//cdma_wt_done_status1,
//cdma_dat_done_status0,
//cdma_dat_done_status1,
//cacc_done_status0,
//cacc_done_status1,
//sdp_done_status0,
//sdp_done_status1,
//pdp_done_status0,
//pdp_done_status1,
//cdp_done_status0,
//cdp_done_status1,
//bdma_done_status0,
//bdma_done_status1,
//cdma_wt_done_0_counter,
//cdma_wt_done_1_counter,
//cdma_dat_done_0_counter,
//cdma_dat_done_1_counter,
//cacc_done_0_counter,
//cacc_done_1_counter,
//sdp_done_0_counter,
//sdp_done_1_counter,
//pdp_done_0_counter,
//pdp_done_1_counter,
//cdp_done_0_counter,
//cdp_done_1_counter,
//bdma_done_0_counter,
//bdma_done_1_counter,
//cdma_img_status,
//cdma_dc_status,
//cdma_wt_status,
//upper_limit_w,
//lower_limit_w,
//sc2mac_wt_a_pvld,
//sc2mac_wt_a_sel,
//sc2mac_wt_a_mask,
//sc2mac_wt_a_data0,
//sc2mac_dat_a_pvld,
//sc2mac_dat_a_mask,
//sc2mac_dat_a_data0,
//mac_a2accu_pvld,
//mac_a2accu_mask,
//mac_a2accu_data0,
//sc2mac_wt_b_pvld,
//sc2mac_wt_b_sel,
//sc2mac_wt_b_mask,
//sc2mac_wt_b_data0,
//sc2mac_dat_b_pvld,
//sc2mac_dat_b_mask,
//sc2mac_dat_b_data0,
//mac_b2accu_pvld,
//mac_b2accu_mask,
//mac_b2accu_data0,
//cacc2sdp_valid,
//cacc2sdp_ready,
//cacc2sdp_pd,
//cacc2sdp_adpt_valid,
//cacc2sdp_adpt_ready,
//cacc2sdp_adpt_pd,
//sdp_dp2wdma_valid,
//sdp_dp2wdma_ready,
//sdp_dp2wdma_pd,
//sdp2pdp_valid,
//sdp2pdp_ready,
//sdp2pdp_pd
);
//input & output ports declaration
////////////////////////////////////////////////////////////////////////
//sys signals
input dla_core_clk;
input dla_csb_clk;
input dla_reset_rstn;
//DBBIF
/*********************************************************************/
//AXI4-AW channel
//output [7:0] nvdla_core2dbb_aw_awid;
output [3:0] nvdla_core2dbb_aw_awid;
output [64 -1:0] nvdla_core2dbb_aw_awaddr;
//output [3:0] nvdla_core2dbb_aw_awlen;
output [7:0] nvdla_core2dbb_aw_awlen;
output [2:0] nvdla_core2dbb_aw_awsize;//new added
output [1:0] nvdla_core2dbb_aw_awburst;//new added
output nvdla_core2dbb_aw_awlock;//new added
output [3:0] nvdla_core2dbb_aw_awcache;//new added
output [2:0] nvdla_core2dbb_aw_awprot;//new added
output [3:0] nvdla_core2dbb_aw_awqos;//new added
output [3:0] nvdla_core2dbb_aw_awregion;//new added
output [31:0] nvdla_core2dbb_aw_awuser;//new added, not sure about width
output nvdla_core2dbb_aw_awvalid;
input nvdla_core2dbb_aw_awready;
//AXI4-W channel
output [7:0] nvdla_core2dbb_w_wid;
output [256-1:0] nvdla_core2dbb_w_wdata;
output [256/8-1:0] nvdla_core2dbb_w_wstrb;
output nvdla_core2dbb_w_wlast;
output [31:0] nvdla_core2dbb_w_wuser;//new added, not sure about width
output nvdla_core2dbb_w_wvalid;
input nvdla_core2dbb_w_wready;
//AXI4-B channel
//input [7:0] nvdla_core2dbb_b_bid;
input [5:0] nvdla_core2dbb_b_bid;
input [1:0] nvdla_core2dbb_b_bresp;//new added
input [31:0] nvdla_core2dbb_b_buser;//new added, not sure about signal width
input nvdla_core2dbb_b_bvalid;
output nvdla_core2dbb_b_bready;
//AXI4-AR channel
//output [7:0] nvdla_core2dbb_ar_arid;
output [3:0] nvdla_core2dbb_ar_arid;
output [64 -1:0] nvdla_core2dbb_ar_araddr;
//output [3:0] nvdla_core2dbb_ar_arlen;
output [7:0] nvdla_core2dbb_ar_arlen;
output [2:0] nvdla_core2dbb_ar_arsize;//new added
output [1:0] nvdla_core2dbb_ar_arburst;//new added
output nvdla_core2dbb_ar_arlock;//new added
output [3:0] nvdla_core2dbb_ar_arcache;//new added
output [2:0] nvdla_core2dbb_ar_arprot;//new added
output [3:0] nvdla_core2dbb_ar_arqos;//new added
output [3:0] nvdla_core2dbb_ar_arregion;//new added
output [31:0] nvdla_core2dbb_ar_aruser;//new added, not sure about signal width
output nvdla_core2dbb_ar_arvalid;
input nvdla_core2dbb_ar_arready;
//AXI4-R channel
//input [7:0] nvdla_core2dbb_r_rid;
input [5:0] nvdla_core2dbb_r_rid;
input [256-1:0] nvdla_core2dbb_r_rdata;
input [1:0] nvdla_core2dbb_r_rresp;//new added
input nvdla_core2dbb_r_rlast;
input [31:0] nvdla_core2dbb_r_ruser;//new added, not sure sbout signal width
input nvdla_core2dbb_r_rvalid;
output nvdla_core2dbb_r_rready;
/*********************************************************************/
//SRAMIF
/*********************************************************************/
//AXI4-AW channel
//output [7:0] nvdla_core2cvsram_aw_awid;
output [3:0] nvdla_core2cvsram_aw_awid;
output [63:0] nvdla_core2cvsram_aw_awaddr;
//output [3:0] nvdla_core2cvsram_aw_awlen;
output [7:0] nvdla_core2cvsram_aw_awlen;
output [2:0] nvdla_core2cvsram_aw_awsize;//new added
output [1:0] nvdla_core2cvsram_aw_awburst;//new added
output nvdla_core2cvsram_aw_awlock;//new added
output [3:0] nvdla_core2cvsram_aw_awcache;//new added
output [2:0] nvdla_core2cvsram_aw_awprot;//new added
output [3:0] nvdla_core2cvsram_aw_awqos;//new added
output [3:0] nvdla_core2cvsram_aw_awregion;//new added
output [31:0] nvdla_core2cvsram_aw_awuser;//new added, not sure about width
output nvdla_core2cvsram_aw_awvalid; /* data valid */
input nvdla_core2cvsram_aw_awready; /* data return handshake */
//AXI4-W channel
output [7:0] nvdla_core2cvsram_w_wid;
output [255:0] nvdla_core2cvsram_w_wdata;
output [31:0] nvdla_core2cvsram_w_wstrb;
output nvdla_core2cvsram_w_wlast;
output [31:0] nvdla_core2cvsram_w_wuser;//new added, not sure about width
output nvdla_core2cvsram_w_wvalid; /* data valid */
input nvdla_core2cvsram_w_wready; /* data return handshake */
//AXI4-B channel
//input [7:0] nvdla_core2cvsram_b_bid;
input [5:0] nvdla_core2cvsram_b_bid;
input [1:0] nvdla_core2cvsram_b_bresp;//new added
input [31:0] nvdla_core2cvsram_b_buser;//new added, not sure about signal width
input nvdla_core2cvsram_b_bvalid; /* data valid */
output nvdla_core2cvsram_b_bready; /* data return handshake */
//AXI4-AR channel
//output [7:0] nvdla_core2cvsram_ar_arid;
output [3:0] nvdla_core2cvsram_ar_arid;
output [63:0] nvdla_core2cvsram_ar_araddr;
//output [3:0] nvdla_core2cvsram_ar_arlen;
output [7:0] nvdla_core2cvsram_ar_arlen;
output [2:0] nvdla_core2cvsram_ar_arsize;//new added
output [1:0] nvdla_core2cvsram_ar_arburst;//new added
output nvdla_core2cvsram_ar_arlock;//new added
output [3:0] nvdla_core2cvsram_ar_arcache;//new added
output [2:0] nvdla_core2cvsram_ar_arprot;//new added
output [3:0] nvdla_core2cvsram_ar_arqos;//new added
output [3:0] nvdla_core2cvsram_ar_arregion;//new added
output [31:0] nvdla_core2cvsram_ar_aruser;//new added, not sure about signal width
output nvdla_core2cvsram_ar_arvalid; /* data valid */
input nvdla_core2cvsram_ar_arready; /* data return handshake */
//AXI4-R channel
//input [7:0] nvdla_core2cvsram_r_rid;
input [5:0] nvdla_core2cvsram_r_rid;
input [255:0] nvdla_core2cvsram_r_rdata;
input [1:0] nvdla_core2cvsram_r_rresp;//new added
input nvdla_core2cvsram_r_rlast;
input [31:0] nvdla_core2cvsram_r_ruser;//new added, not sure sbout signal width
input nvdla_core2cvsram_r_rvalid; /* data valid */
output nvdla_core2cvsram_r_rready; /* data return handshake */
/*********************************************************************/
//NVDLA interrupt
output nvdla_intr;
//power contrl signals, tied to 0 when connected to NVDLA
//input [31:0] nvdla_pwrbus_ram_c_pd;
//input [31:0] nvdla_pwrbus_ram_ma_pd;
//input [31:0] nvdla_pwrbus_ram_mb_pd;
//input [31:0] nvdla_pwrbus_ram_p_pd;
//input [31:0] nvdla_pwrbus_ram_o_pd;
//input [31:0] nvdla_pwrbus_ram_a_pd;
//APB interface, apb2csb integrated
//input pclk;
//input prstn;
input psel;
input penable;
input pwrite;
input pprot;
input [31:0] paddr;
input [31:0] pwdata;
input [3:0] pstrb;
output [31:0] prdata;
output pready;
output pslverr;
////////////////////////////////////////////////////////////////////////
//
//for debug
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//output assignment
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
assign pready =1'b1;
assign nvdla_core2dbb_b_bready =1'b1;
assign nvdla_core2dbb_r_rready =1'b1;
assign nvdla_core2cvsram_b_bready =1'b1;
assign nvdla_core2cvsram_r_rready =1'b1;
assign nvdla_core2dbb_aw_awid = 'd0 ;
assign nvdla_core2dbb_aw_awaddr = 'd0 ;
assign nvdla_core2dbb_aw_awlen = 'd0 ;
assign nvdla_core2dbb_aw_awsize = 'd0 ;
assign nvdla_core2dbb_aw_awburst = 'd0 ;
assign nvdla_core2dbb_aw_awlock = 'd0 ;
assign nvdla_core2dbb_aw_awcache = 'd0 ;
assign nvdla_core2dbb_aw_awprot = 'd0 ;
assign nvdla_core2dbb_aw_awvalid = 'd0 ;
assign nvdla_core2dbb_w_wdata = 'd0 ;
assign nvdla_core2dbb_w_wstrb = 'd0 ;
assign nvdla_core2dbb_w_wlast = 'd0 ;
assign nvdla_core2dbb_w_wvalid = 'd0 ;
assign nvdla_core2dbb_ar_arid = 'd0 ;
assign nvdla_core2dbb_ar_araddr = 'd0 ;
assign nvdla_core2dbb_ar_arlen = 'd0 ;
assign nvdla_core2dbb_ar_arsize = 'd0 ;
assign nvdla_core2dbb_ar_arburst = 'd0 ;
assign nvdla_core2dbb_ar_arlock = 'd0 ;
assign nvdla_core2dbb_ar_arcache = 'd0 ;
assign nvdla_core2dbb_ar_arprot = 'd0 ;
assign nvdla_core2dbb_ar_arvalid = 'd0 ;
assign nvdla_core2cvsram_aw_awid = 'd0 ;
assign nvdla_core2cvsram_aw_awaddr = 'd0 ;
assign nvdla_core2cvsram_aw_awlen = 'd0 ;
assign nvdla_core2cvsram_aw_awsize = 'd0 ;
assign nvdla_core2cvsram_aw_awburst = 'd0 ;
assign nvdla_core2cvsram_aw_awlock = 'd0 ;
assign nvdla_core2cvsram_aw_awcache = 'd0 ;
assign nvdla_core2cvsram_aw_awprot = 'd0 ;
assign nvdla_core2cvsram_aw_awvalid = 'd0 ;
assign nvdla_core2cvsram_w_wdata = 'd0 ;
assign nvdla_core2cvsram_w_wstrb = 'd0 ;
assign nvdla_core2cvsram_w_wlast = 'd0 ;
assign nvdla_core2cvsram_w_wvalid = 'd0 ;
assign nvdla_core2cvsram_ar_arid = 'd0 ;
assign nvdla_core2cvsram_ar_araddr = 'd0 ;
assign nvdla_core2cvsram_ar_arlen = 'd0 ;
assign nvdla_core2cvsram_ar_arsize = 'd0 ;
assign nvdla_core2cvsram_ar_arburst = 'd0 ;
assign nvdla_core2cvsram_ar_arlock = 'd0 ;
assign nvdla_core2cvsram_ar_arcache = 'd0 ;
assign nvdla_core2cvsram_ar_arprot = 'd0 ;
assign nvdla_core2cvsram_ar_arvalid = 'd0 ;
assign nvdla_intr = 'd0 ;
assign prdata = 'd0 ;
assign pslverr = 'd0 ;
//
endmodule // NV_nvdla_top |
module NV_NVDLA_MCIF_WRITE_ig (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd
,reg2dp_wr_os_cnt
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print" ,reg2dp_wr_weight_${client}\n";
//: }
//: foreach my $client (@wdma_name) {
//: print" ,${client}2mcif_wr_req_pd\n";
//: print" ,${client}2mcif_wr_req_valid\n";
//: print" ,${client}2mcif_wr_req_ready\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,reg2dp_wr_weight_sdp
,reg2dp_wr_weight_pdp
,reg2dp_wr_weight_cdp
,reg2dp_wr_weight_bdma
,sdp2mcif_wr_req_pd
,sdp2mcif_wr_req_valid
,sdp2mcif_wr_req_ready
,pdp2mcif_wr_req_pd
,pdp2mcif_wr_req_valid
,pdp2mcif_wr_req_ready
,cdp2mcif_wr_req_pd
,cdp2mcif_wr_req_valid
,cdp2mcif_wr_req_ready
,bdma2mcif_wr_req_pd
,bdma2mcif_wr_req_valid
,bdma2mcif_wr_req_ready
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mcif2noc_axi_aw_awvalid
,mcif2noc_axi_aw_awready
,mcif2noc_axi_aw_awid
,mcif2noc_axi_aw_awlen
,mcif2noc_axi_aw_awaddr
,mcif2noc_axi_w_wvalid
,mcif2noc_axi_w_wready
,mcif2noc_axi_w_wdata
,mcif2noc_axi_w_wstrb
,mcif2noc_axi_w_wlast
,cq_wr_pvld
,cq_wr_prdy
,cq_wr_pd
,cq_wr_thread_id
,eg2ig_axi_len
,eg2ig_axi_vld
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input [7:0] reg2dp_wr_os_cnt;
input [2:0] eg2ig_axi_len;
input eg2ig_axi_vld;
output cq_wr_pvld;
input cq_wr_prdy;
output [2:0] cq_wr_thread_id;
output [3:0] cq_wr_pd;
output mcif2noc_axi_aw_awvalid;
input mcif2noc_axi_aw_awready;
output [7:0] mcif2noc_axi_aw_awid;
output [3:0] mcif2noc_axi_aw_awlen;
output [64 -1:0] mcif2noc_axi_aw_awaddr;
output mcif2noc_axi_w_wvalid;
input mcif2noc_axi_w_wready;
output [256 -1:0] mcif2noc_axi_w_wdata;
output [32 -1:0] mcif2noc_axi_w_wstrb;
output mcif2noc_axi_w_wlast;
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print qq(
//: input ${client}2mcif_wr_req_valid;
//: output ${client}2mcif_wr_req_ready;
//: input [258 -1:0] ${client}2mcif_wr_req_pd;
//: );
//: }
//: foreach my $client (@wdma_name) {
//: print "input [7:0] reg2dp_wr_weight_${client};\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input sdp2mcif_wr_req_valid;
output sdp2mcif_wr_req_ready;
input [258 -1:0] sdp2mcif_wr_req_pd;
input pdp2mcif_wr_req_valid;
output pdp2mcif_wr_req_ready;
input [258 -1:0] pdp2mcif_wr_req_pd;
input cdp2mcif_wr_req_valid;
output cdp2mcif_wr_req_ready;
input [258 -1:0] cdp2mcif_wr_req_pd;
input bdma2mcif_wr_req_valid;
output bdma2mcif_wr_req_ready;
input [258 -1:0] bdma2mcif_wr_req_pd;
input [7:0] reg2dp_wr_weight_sdp;
input [7:0] reg2dp_wr_weight_pdp;
input [7:0] reg2dp_wr_weight_cdp;
input [7:0] reg2dp_wr_weight_bdma;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire arb2spt_cmd_ready;
wire arb2spt_cmd_valid;
wire [64 +13 -1:0] arb2spt_cmd_pd;
wire arb2spt_dat_ready;
wire arb2spt_dat_valid;
wire [258 -2:0] arb2spt_dat_pd;
/*
wire spt2cvt_cmd_ready;
wire spt2cvt_cmd_valid;
wire [NVDLA_MEM_ADDRESS_WIDTH+12:0] spt2cvt_cmd_pd;
wire spt2cvt_dat_ready;
wire spt2cvt_dat_valid;
wire [NVDLA_MEMIF_WIDTH+1:0] spt2cvt_dat_pd;
*/
//: for (my $i=0;$i<4;$i++) {
//: print qq(
//: wire bpt2arb_cmd${i}_valid;
//: wire bpt2arb_cmd${i}_ready;
//: wire [64 +13 -1:0] bpt2arb_cmd${i}_pd;
//: wire bpt2arb_dat${i}_valid;
//: wire bpt2arb_dat${i}_ready;
//: wire [258 -2:0] bpt2arb_dat${i}_pd;
//: );
//: }
//: my $i = 0;
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print "NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt${i} ( \n";
//: print " .nvdla_core_clk (nvdla_core_clk)\n";
//: print " ,.nvdla_core_rstn (nvdla_core_rstn)\n";
//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd)\n";
//: print " ,.dma2bpt_req_valid (${client}2mcif_wr_req_valid)\n";
//: print " ,.dma2bpt_req_ready (${client}2mcif_wr_req_ready)\n";
//: print " ,.dma2bpt_req_pd (${client}2mcif_wr_req_pd)\n";
//: print " ,.bpt2arb_cmd_valid (bpt2arb_cmd${i}_valid)\n";
//: print " ,.bpt2arb_cmd_ready (bpt2arb_cmd${i}_ready)\n";
//: print " ,.bpt2arb_cmd_pd (bpt2arb_cmd${i}_pd)\n";
//: print " ,.bpt2arb_dat_valid (bpt2arb_dat${i}_valid)\n";
//: print " ,.bpt2arb_dat_ready (bpt2arb_dat${i}_ready)\n";
//: print " ,.bpt2arb_dat_pd (bpt2arb_dat${i}_pd)\n";
//: print " ,.axid (`tieoff_axid_${client})\n";
//: print ");\n";
//: $i++;
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire bpt2arb_cmd0_valid;
wire bpt2arb_cmd0_ready;
wire [64 +13 -1:0] bpt2arb_cmd0_pd;
wire bpt2arb_dat0_valid;
wire bpt2arb_dat0_ready;
wire [258 -2:0] bpt2arb_dat0_pd;
wire bpt2arb_cmd1_valid;
wire bpt2arb_cmd1_ready;
wire [64 +13 -1:0] bpt2arb_cmd1_pd;
wire bpt2arb_dat1_valid;
wire bpt2arb_dat1_ready;
wire [258 -2:0] bpt2arb_dat1_pd;
wire bpt2arb_cmd2_valid;
wire bpt2arb_cmd2_ready;
wire [64 +13 -1:0] bpt2arb_cmd2_pd;
wire bpt2arb_dat2_valid;
wire bpt2arb_dat2_ready;
wire [258 -2:0] bpt2arb_dat2_pd;
wire bpt2arb_cmd3_valid;
wire bpt2arb_cmd3_ready;
wire [64 +13 -1:0] bpt2arb_cmd3_pd;
wire bpt2arb_dat3_valid;
wire bpt2arb_dat3_ready;
wire [258 -2:0] bpt2arb_dat3_pd;
NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (sdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (sdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (sdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd0_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd0_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd0_pd)
,.bpt2arb_dat_valid (bpt2arb_dat0_valid)
,.bpt2arb_dat_ready (bpt2arb_dat0_ready)
,.bpt2arb_dat_pd (bpt2arb_dat0_pd)
,.axid (`tieoff_axid_sdp)
);
NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (pdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (pdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (pdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd1_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd1_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd1_pd)
,.bpt2arb_dat_valid (bpt2arb_dat1_valid)
,.bpt2arb_dat_ready (bpt2arb_dat1_ready)
,.bpt2arb_dat_pd (bpt2arb_dat1_pd)
,.axid (`tieoff_axid_pdp)
);
NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (cdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (cdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (cdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd2_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd2_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd2_pd)
,.bpt2arb_dat_valid (bpt2arb_dat2_valid)
,.bpt2arb_dat_ready (bpt2arb_dat2_ready)
,.bpt2arb_dat_pd (bpt2arb_dat2_pd)
,.axid (`tieoff_axid_cdp)
);
NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt3 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (bdma2mcif_wr_req_valid)
,.dma2bpt_req_ready (bdma2mcif_wr_req_ready)
,.dma2bpt_req_pd (bdma2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd3_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd3_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd3_pd)
,.bpt2arb_dat_valid (bpt2arb_dat3_valid)
,.bpt2arb_dat_ready (bpt2arb_dat3_ready)
,.bpt2arb_dat_pd (bpt2arb_dat3_pd)
,.axid (`tieoff_axid_bdma)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
NV_NVDLA_MCIF_WRITE_IG_arb u_arb (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|<
//: for (my $i=0;$i<4;$i++) {
//: print " ,.bpt2arb_cmd${i}_valid (bpt2arb_cmd${i}_valid)\n";
//: print " ,.bpt2arb_cmd${i}_ready (bpt2arb_cmd${i}_ready)\n";
//: print " ,.bpt2arb_cmd${i}_pd (bpt2arb_cmd${i}_pd)\n";
//: print " ,.bpt2arb_dat${i}_valid (bpt2arb_dat${i}_valid)\n";
//: print " ,.bpt2arb_dat${i}_ready (bpt2arb_dat${i}_ready)\n";
//: print " ,.bpt2arb_dat${i}_pd (bpt2arb_dat${i}_pd)\n";
//: }
//: my $i=0;
//: my @wdma_name = ("sdp", "pdp","cdp","bdma");
//: foreach my $client (@wdma_name) {
//: print " ,.reg2dp_wr_weight${i} (reg2dp_wr_weight_${client}[7:0])\n";
//: $i++;
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.bpt2arb_cmd0_valid (bpt2arb_cmd0_valid)
,.bpt2arb_cmd0_ready (bpt2arb_cmd0_ready)
,.bpt2arb_cmd0_pd (bpt2arb_cmd0_pd)
,.bpt2arb_dat0_valid (bpt2arb_dat0_valid)
,.bpt2arb_dat0_ready (bpt2arb_dat0_ready)
,.bpt2arb_dat0_pd (bpt2arb_dat0_pd)
,.bpt2arb_cmd1_valid (bpt2arb_cmd1_valid)
,.bpt2arb_cmd1_ready (bpt2arb_cmd1_ready)
,.bpt2arb_cmd1_pd (bpt2arb_cmd1_pd)
,.bpt2arb_dat1_valid (bpt2arb_dat1_valid)
,.bpt2arb_dat1_ready (bpt2arb_dat1_ready)
,.bpt2arb_dat1_pd (bpt2arb_dat1_pd)
,.bpt2arb_cmd2_valid (bpt2arb_cmd2_valid)
,.bpt2arb_cmd2_ready (bpt2arb_cmd2_ready)
,.bpt2arb_cmd2_pd (bpt2arb_cmd2_pd)
,.bpt2arb_dat2_valid (bpt2arb_dat2_valid)
,.bpt2arb_dat2_ready (bpt2arb_dat2_ready)
,.bpt2arb_dat2_pd (bpt2arb_dat2_pd)
,.bpt2arb_cmd3_valid (bpt2arb_cmd3_valid)
,.bpt2arb_cmd3_ready (bpt2arb_cmd3_ready)
,.bpt2arb_cmd3_pd (bpt2arb_cmd3_pd)
,.bpt2arb_dat3_valid (bpt2arb_dat3_valid)
,.bpt2arb_dat3_ready (bpt2arb_dat3_ready)
,.bpt2arb_dat3_pd (bpt2arb_dat3_pd)
,.reg2dp_wr_weight0 (reg2dp_wr_weight_sdp[7:0])
,.reg2dp_wr_weight1 (reg2dp_wr_weight_pdp[7:0])
,.reg2dp_wr_weight2 (reg2dp_wr_weight_cdp[7:0])
,.reg2dp_wr_weight3 (reg2dp_wr_weight_bdma[7:0])
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|> w
,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|< w
,.arb2spt_cmd_pd (arb2spt_cmd_pd)
,.arb2spt_dat_valid (arb2spt_dat_valid) //|> w
,.arb2spt_dat_ready (arb2spt_dat_ready) //|< w
,.arb2spt_dat_pd (arb2spt_dat_pd)
);
/*
NV_NVDLA_MCIF_WRITE_IG_spt u_spt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< w
,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> w
,.arb2spt_cmd_pd (arb2spt_cmd_pd)
,.arb2spt_dat_valid (arb2spt_dat_valid) //|< w
,.arb2spt_dat_ready (arb2spt_dat_ready) //|> w
,.arb2spt_dat_pd (arb2spt_dat_pd)
,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|> w
,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|< w
,.spt2cvt_cmd_pd (spt2cvt_cmd_pd)
,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|> w
,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|< w
,.spt2cvt_dat_pd (spt2cvt_dat_pd)
);
*/
NV_NVDLA_MCIF_WRITE_IG_cvt u_cvt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|< i
,.cq_wr_pvld (cq_wr_pvld) //|> o
,.cq_wr_prdy (cq_wr_prdy) //|< i
,.cq_wr_pd (cq_wr_pd[3:0]) //|> o
,.cq_wr_thread_id (cq_wr_thread_id[2:0]) //|> o
,.eg2ig_axi_len (eg2ig_axi_len[2:0]) //|< i
,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i
,.spt2cvt_cmd_valid (arb2spt_cmd_valid) //|< w
,.spt2cvt_cmd_ready (arb2spt_cmd_ready) //|> w
,.spt2cvt_cmd_pd (arb2spt_cmd_pd)
,.spt2cvt_dat_valid (arb2spt_dat_valid) //|< w
,.spt2cvt_dat_ready (arb2spt_dat_ready) //|> w
,.spt2cvt_dat_pd (arb2spt_dat_pd)
,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o
,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i
,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o
,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o
,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr)
,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o
,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i
,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata)
,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb)
,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o
);
endmodule |
module NV_NVDLA_CDP_DP_mul (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,intp2mul_pd_$m
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,intp2mul_pd_0
,intp2mul_pd_1
,intp2mul_pd_2
,intp2mul_pd_3
,intp2mul_pd_4
,intp2mul_pd_5
,intp2mul_pd_6
,intp2mul_pd_7
//| eperl: generated_end (DO NOT EDIT ABOVE)
,intp2mul_pvld //|< i
,mul2ocvt_prdy //|< i
,reg2dp_mul_bypass //|< i
,sync2mul_pd //|< i
,sync2mul_pvld //|< i
,intp2mul_prdy //|> o
,mul2ocvt_pd //|> o
,mul2ocvt_pvld //|> o
,sync2mul_prdy //|> o
);
//////////////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $k = 8;
//: my $icvto=(8 +1);
//: foreach my $m (0..$k-1) {
//: print qq(
//: input [16:0] intp2mul_pd_$m;
//: );
//: }
//: print qq(
//: input [${k}*${icvto}-1:0] sync2mul_pd;
//: output [${k}*(${icvto}+16)-1:0] mul2ocvt_pd;
//: );
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [16:0] intp2mul_pd_0;
input [16:0] intp2mul_pd_1;
input [16:0] intp2mul_pd_2;
input [16:0] intp2mul_pd_3;
input [16:0] intp2mul_pd_4;
input [16:0] intp2mul_pd_5;
input [16:0] intp2mul_pd_6;
input [16:0] intp2mul_pd_7;
input [8*9-1:0] sync2mul_pd;
output [8*(9+16)-1:0] mul2ocvt_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input intp2mul_pvld;
input mul2ocvt_prdy;
input reg2dp_mul_bypass;
input sync2mul_pvld;
output intp2mul_prdy;
output mul2ocvt_pvld;
output sync2mul_prdy;
//////////////////////////////////////////////////////
reg mul_bypass_en;
wire [8*((8 +1)+16)-1:0] intp_out_ext;
wire [8*((8 +1)+16)-1:0] mul2ocvt_pd_f;
wire mul2ocvt_pvld_f;
wire mul_in_rdy;
wire mul_in_vld;
//: my $k = 8;
//: my $icvto=(8 +1);
//: foreach my $m (0..$k-1) {
//: print qq(
//: wire [(${icvto}+16)-1:0] mul_unit_pd_$m;
//: wire [${icvto}-1:0] mul_ina_pd_$m;
//: wire [15:0] mul_inb_pd_$m;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [(9+16)-1:0] mul_unit_pd_0;
wire [9-1:0] mul_ina_pd_0;
wire [15:0] mul_inb_pd_0;
wire [(9+16)-1:0] mul_unit_pd_1;
wire [9-1:0] mul_ina_pd_1;
wire [15:0] mul_inb_pd_1;
wire [(9+16)-1:0] mul_unit_pd_2;
wire [9-1:0] mul_ina_pd_2;
wire [15:0] mul_inb_pd_2;
wire [(9+16)-1:0] mul_unit_pd_3;
wire [9-1:0] mul_ina_pd_3;
wire [15:0] mul_inb_pd_3;
wire [(9+16)-1:0] mul_unit_pd_4;
wire [9-1:0] mul_ina_pd_4;
wire [15:0] mul_inb_pd_4;
wire [(9+16)-1:0] mul_unit_pd_5;
wire [9-1:0] mul_ina_pd_5;
wire [15:0] mul_inb_pd_5;
wire [(9+16)-1:0] mul_unit_pd_6;
wire [9-1:0] mul_ina_pd_6;
wire [15:0] mul_inb_pd_6;
wire [(9+16)-1:0] mul_unit_pd_7;
wire [9-1:0] mul_ina_pd_7;
wire [15:0] mul_inb_pd_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [8 -1:0] mul_unit_rdy;
wire [8 -1:0] mul_unit_vld;
wire [8 -1:0] mul_vld;
wire [8 -1:0] mul_rdy;
///////////////////////////////////////////
//: my $k = 8*((8 +1)+16);
//: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg mul2ocvt_prdy_f;
reg skid_flop_mul2ocvt_prdy_f;
reg skid_flop_mul2ocvt_pvld_f;
reg [200-1:0] skid_flop_mul2ocvt_pd_f;
reg pipe_skid_mul2ocvt_pvld_f;
reg [200-1:0] pipe_skid_mul2ocvt_pd_f;
// Wire
wire skid_mul2ocvt_pvld_f;
wire [200-1:0] skid_mul2ocvt_pd_f;
wire skid_mul2ocvt_prdy_f;
wire pipe_skid_mul2ocvt_prdy_f;
wire mul2ocvt_pvld;
wire [200-1:0] mul2ocvt_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mul2ocvt_prdy_f <= 1'b1;
skid_flop_mul2ocvt_prdy_f <= 1'b1;
end else begin
mul2ocvt_prdy_f <= skid_mul2ocvt_prdy_f;
skid_flop_mul2ocvt_prdy_f <= skid_mul2ocvt_prdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_mul2ocvt_pvld_f <= 1'b0;
end else begin
if (skid_flop_mul2ocvt_prdy_f) begin
skid_flop_mul2ocvt_pvld_f <= mul2ocvt_pvld_f;
end
end
end
assign skid_mul2ocvt_pvld_f = (skid_flop_mul2ocvt_prdy_f) ? mul2ocvt_pvld_f : skid_flop_mul2ocvt_pvld_f;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_mul2ocvt_prdy_f & mul2ocvt_pvld_f) begin
skid_flop_mul2ocvt_pd_f[200-1:0] <= mul2ocvt_pd_f[200-1:0];
end
end
assign skid_mul2ocvt_pd_f[200-1:0] = (skid_flop_mul2ocvt_prdy_f) ? mul2ocvt_pd_f[200-1:0] : skid_flop_mul2ocvt_pd_f[200-1:0];
// PIPE READY
assign skid_mul2ocvt_prdy_f = pipe_skid_mul2ocvt_prdy_f || !pipe_skid_mul2ocvt_pvld_f;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_mul2ocvt_pvld_f <= 1'b0;
end else begin
if (skid_mul2ocvt_prdy_f) begin
pipe_skid_mul2ocvt_pvld_f <= skid_mul2ocvt_pvld_f;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_mul2ocvt_prdy_f && skid_mul2ocvt_pvld_f) begin
pipe_skid_mul2ocvt_pd_f[200-1:0] <= skid_mul2ocvt_pd_f[200-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_mul2ocvt_prdy_f = mul2ocvt_prdy;
assign mul2ocvt_pvld = pipe_skid_mul2ocvt_pvld_f;
assign mul2ocvt_pd = pipe_skid_mul2ocvt_pd_f;
//| eperl: generated_end (DO NOT EDIT ABOVE)
///////////////////////////////////////////////////////////////////
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mul_bypass_en <= 1'b0;
end else begin
mul_bypass_en <= reg2dp_mul_bypass == 1'h1;
end
end
//interlock two path data
assign intp2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & sync2mul_pvld;
assign sync2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & intp2mul_pvld;
assign mul_in_vld = mul_bypass_en ? 1'b0 : (sync2mul_pvld & intp2mul_pvld);
assign mul_in_rdy = &mul_rdy;
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: assign mul_vld[$m] = mul_in_vld
//: );
//: foreach my $i (0..$k-1) {
//: print qq(
//: & mul_rdy[$i]
//: );
//: }
//: print qq(
//: ;
//: );
//: }
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: assign mul_inb_pd_$m = intp2mul_pd_${m}[15:0];
//: );
//: }
//: my $k = 8;
//: my $icvto=(8 +1);
//: foreach my $m (0..$k-1) {
//: print qq(
//: assign mul_ina_pd_$m = sync2mul_pd[$m*${icvto}+${icvto}-1:$m*${icvto}];
//: NV_NVDLA_CDP_DP_MUL_unit u_mul_unit$m (
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.mul_vld (mul_vld[$m])
//: ,.mul_rdy (mul_rdy[$m])
//: ,.mul_ina_pd (mul_ina_pd_$m)
//: ,.mul_inb_pd (mul_inb_pd_$m)
//: ,.mul_unit_vld (mul_unit_vld[$m])
//: ,.mul_unit_rdy (mul_unit_rdy[$m])
//: ,.mul_unit_pd (mul_unit_pd_$m)
//: );
//: );
//: }
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: assign mul_unit_rdy[$m] = mul2ocvt_prdy_f
//: );
//: foreach my $i (0..$k-1) {
//: print qq(
//: & mul_unit_vld[$i]
//: );
//: }
//: print qq(
//: ;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign mul_vld[0] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[1] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[2] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[3] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[4] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[5] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[6] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_vld[7] = mul_in_vld
& mul_rdy[0]
& mul_rdy[1]
& mul_rdy[2]
& mul_rdy[3]
& mul_rdy[4]
& mul_rdy[5]
& mul_rdy[6]
& mul_rdy[7]
;
assign mul_inb_pd_0 = intp2mul_pd_0[15:0];
assign mul_inb_pd_1 = intp2mul_pd_1[15:0];
assign mul_inb_pd_2 = intp2mul_pd_2[15:0];
assign mul_inb_pd_3 = intp2mul_pd_3[15:0];
assign mul_inb_pd_4 = intp2mul_pd_4[15:0];
assign mul_inb_pd_5 = intp2mul_pd_5[15:0];
assign mul_inb_pd_6 = intp2mul_pd_6[15:0];
assign mul_inb_pd_7 = intp2mul_pd_7[15:0];
assign mul_ina_pd_0 = sync2mul_pd[0*9+9-1:0*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[0])
,.mul_rdy (mul_rdy[0])
,.mul_ina_pd (mul_ina_pd_0)
,.mul_inb_pd (mul_inb_pd_0)
,.mul_unit_vld (mul_unit_vld[0])
,.mul_unit_rdy (mul_unit_rdy[0])
,.mul_unit_pd (mul_unit_pd_0)
);
assign mul_ina_pd_1 = sync2mul_pd[1*9+9-1:1*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[1])
,.mul_rdy (mul_rdy[1])
,.mul_ina_pd (mul_ina_pd_1)
,.mul_inb_pd (mul_inb_pd_1)
,.mul_unit_vld (mul_unit_vld[1])
,.mul_unit_rdy (mul_unit_rdy[1])
,.mul_unit_pd (mul_unit_pd_1)
);
assign mul_ina_pd_2 = sync2mul_pd[2*9+9-1:2*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[2])
,.mul_rdy (mul_rdy[2])
,.mul_ina_pd (mul_ina_pd_2)
,.mul_inb_pd (mul_inb_pd_2)
,.mul_unit_vld (mul_unit_vld[2])
,.mul_unit_rdy (mul_unit_rdy[2])
,.mul_unit_pd (mul_unit_pd_2)
);
assign mul_ina_pd_3 = sync2mul_pd[3*9+9-1:3*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit3 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[3])
,.mul_rdy (mul_rdy[3])
,.mul_ina_pd (mul_ina_pd_3)
,.mul_inb_pd (mul_inb_pd_3)
,.mul_unit_vld (mul_unit_vld[3])
,.mul_unit_rdy (mul_unit_rdy[3])
,.mul_unit_pd (mul_unit_pd_3)
);
assign mul_ina_pd_4 = sync2mul_pd[4*9+9-1:4*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit4 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[4])
,.mul_rdy (mul_rdy[4])
,.mul_ina_pd (mul_ina_pd_4)
,.mul_inb_pd (mul_inb_pd_4)
,.mul_unit_vld (mul_unit_vld[4])
,.mul_unit_rdy (mul_unit_rdy[4])
,.mul_unit_pd (mul_unit_pd_4)
);
assign mul_ina_pd_5 = sync2mul_pd[5*9+9-1:5*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit5 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[5])
,.mul_rdy (mul_rdy[5])
,.mul_ina_pd (mul_ina_pd_5)
,.mul_inb_pd (mul_inb_pd_5)
,.mul_unit_vld (mul_unit_vld[5])
,.mul_unit_rdy (mul_unit_rdy[5])
,.mul_unit_pd (mul_unit_pd_5)
);
assign mul_ina_pd_6 = sync2mul_pd[6*9+9-1:6*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit6 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[6])
,.mul_rdy (mul_rdy[6])
,.mul_ina_pd (mul_ina_pd_6)
,.mul_inb_pd (mul_inb_pd_6)
,.mul_unit_vld (mul_unit_vld[6])
,.mul_unit_rdy (mul_unit_rdy[6])
,.mul_unit_pd (mul_unit_pd_6)
);
assign mul_ina_pd_7 = sync2mul_pd[7*9+9-1:7*9];
NV_NVDLA_CDP_DP_MUL_unit u_mul_unit7 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.mul_vld (mul_vld[7])
,.mul_rdy (mul_rdy[7])
,.mul_ina_pd (mul_ina_pd_7)
,.mul_inb_pd (mul_inb_pd_7)
,.mul_unit_vld (mul_unit_vld[7])
,.mul_unit_rdy (mul_unit_rdy[7])
,.mul_unit_pd (mul_unit_pd_7)
);
assign mul_unit_rdy[0] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[1] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[2] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[3] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[4] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[5] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[6] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
assign mul_unit_rdy[7] = mul2ocvt_prdy_f
& mul_unit_vld[0]
& mul_unit_vld[1]
& mul_unit_vld[2]
& mul_unit_vld[3]
& mul_unit_vld[4]
& mul_unit_vld[5]
& mul_unit_vld[6]
& mul_unit_vld[7]
;
//| eperl: generated_end (DO NOT EDIT ABOVE)
///////////////////
//NaN propagation for mul_bypass condition
///////////////////
assign intp_out_ext = {
//: my $icvto=(8 +1);
//: my $k = 8;
//: if($k > 1) {
//: foreach my $m (0..$k-2) {
//: my $i = $k -$m -1;
//: print "{{(${icvto}+16-17){intp2mul_pd_${i}[16]}}, intp2mul_pd_${i}[16:0]},";
//: }
//: }
//: print "{{(${icvto}+16-17){intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}}; \n";
//:
//: print "assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : { ";
//: if($k > 1) {
//: foreach my $m (0..$k-2) {
//: my $i = $k -$m -1;
//: print "mul_unit_pd_$i,";
//: }
//: }
//: print " mul_unit_pd_0}; \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
{{(9+16-17){intp2mul_pd_7[16]}}, intp2mul_pd_7[16:0]},{{(9+16-17){intp2mul_pd_6[16]}}, intp2mul_pd_6[16:0]},{{(9+16-17){intp2mul_pd_5[16]}}, intp2mul_pd_5[16:0]},{{(9+16-17){intp2mul_pd_4[16]}}, intp2mul_pd_4[16:0]},{{(9+16-17){intp2mul_pd_3[16]}}, intp2mul_pd_3[16:0]},{{(9+16-17){intp2mul_pd_2[16]}}, intp2mul_pd_2[16:0]},{{(9+16-17){intp2mul_pd_1[16]}}, intp2mul_pd_1[16:0]},{{(9+16-17){intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}};
assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : { mul_unit_pd_7,mul_unit_pd_6,mul_unit_pd_5,mul_unit_pd_4,mul_unit_pd_3,mul_unit_pd_2,mul_unit_pd_1, mul_unit_pd_0};
//| eperl: generated_end (DO NOT EDIT ABOVE)
//output select
assign mul2ocvt_pvld_f = mul_bypass_en ? (sync2mul_pvld & intp2mul_pvld) : (&mul_unit_vld);
// ///////////////////////////////////////////
//
// //: my $k = NVDLA_CDP_THROUGHPUT*(NVDLA_CDP_ICVTO_BWPE+16);
// //: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f ");
//
///////////////////////////////////////////
endmodule // NV_NVDLA_CDP_DP_mul |
module NV_NVDLA_glb (
cacc2glb_done_intr_pd //|< i
,bdma2glb_done_intr_pd //|< i
,cdma_dat2glb_done_intr_pd //|< i
,cdma_wt2glb_done_intr_pd //|< i
,cdp2glb_done_intr_pd //|< i
,csb2glb_req_pd //|< i
,csb2glb_req_pvld //|< i
,direct_reset_ //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,nvdla_falcon_clk //|< i
,nvdla_falcon_rstn //|< i
,pdp2glb_done_intr_pd //|< i
,sdp2glb_done_intr_pd //|< i
,test_mode //|< i
,core_intr //|> o
,csb2glb_req_prdy //|> o
,glb2csb_resp_pd //|> o
,glb2csb_resp_valid //|> o
,csb2nvdla_write //|< i used for performance counter
,cdma_wt_done_status0
,cdma_wt_done_status1
,cdma_dat_done_status0
,cdma_dat_done_status1
,cacc_done_status0
,cacc_done_status1
,sdp_done_status0
,sdp_done_status1
,pdp_done_status0
,pdp_done_status1
,cdp_done_status0
,cdp_done_status1
,bdma_done_status0
,bdma_done_status1
,cdma_op_en
);
//
// NV_NVDLA_glb_io.v
//
input csb2glb_req_pvld; /* data valid */
output csb2glb_req_prdy; /* data return handshake */
input [62:0] csb2glb_req_pd;
output glb2csb_resp_valid; /* data valid */
output [33:0] glb2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
output core_intr;
input [1:0] sdp2glb_done_intr_pd;
input [1:0] cdp2glb_done_intr_pd;
input [1:0] pdp2glb_done_intr_pd;
input [1:0] bdma2glb_done_intr_pd;
input [1:0] cdma_wt2glb_done_intr_pd;
input [1:0] cdma_dat2glb_done_intr_pd;
input [1:0] cacc2glb_done_intr_pd;
input nvdla_core_clk;
input nvdla_falcon_clk;
input nvdla_core_rstn;
input nvdla_falcon_rstn;
input test_mode;
input direct_reset_;
input csb2nvdla_write;
wire bdma_done_mask0;
wire bdma_done_mask1;
output bdma_done_status0;
output bdma_done_status1;
wire cacc_done_mask0;
wire cacc_done_mask1;
output cacc_done_status0;
output cacc_done_status1;
wire cdma_dat_done_mask0;
wire cdma_dat_done_mask1;
output cdma_dat_done_status0;
output cdma_dat_done_status1;
wire cdma_wt_done_mask0;
wire cdma_wt_done_mask1;
output cdma_wt_done_status0;
output cdma_wt_done_status1;
wire cdp_done_mask0;
wire cdp_done_mask1;
output cdp_done_status0;
output cdp_done_status1;
wire pdp_done_mask0;
wire pdp_done_mask1;
output pdp_done_status0;
output pdp_done_status1;
wire sdp_done_mask0;
wire sdp_done_mask1;
wire sdp_done_set0_trigger;
output sdp_done_status0;
output sdp_done_status1;
wire sdp_done_status0_trigger;
wire [31:0] req_wdat;
input cdma_op_en;//modified by jiazhaorong
////////////////////////////////////////////////////////
// csb interface
////////////////////////////////////////////////////////
NV_NVDLA_GLB_csb u_csb (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.bdma_done_status0 (bdma_done_status0) //|< w
,.bdma_done_status1 (bdma_done_status1) //|< w
,.cacc_done_status0 (cacc_done_status0) //|< w
,.cacc_done_status1 (cacc_done_status1) //|< w
,.cdma_dat_done_status0 (cdma_dat_done_status0) //|< w
,.cdma_dat_done_status1 (cdma_dat_done_status1) //|< w
,.cdma_wt_done_status0 (cdma_wt_done_status0) //|< w
,.cdma_wt_done_status1 (cdma_wt_done_status1) //|< w
,.cdp_done_status0 (cdp_done_status0) //|< w
,.cdp_done_status1 (cdp_done_status1) //|< w
,.csb2glb_req_pd (csb2glb_req_pd[62:0]) //|< i
,.csb2glb_req_pvld (csb2glb_req_pvld) //|< i
,.pdp_done_status0 (pdp_done_status0) //|< w
,.pdp_done_status1 (pdp_done_status1) //|< w
,.sdp_done_status0 (sdp_done_status0) //|< w
,.sdp_done_status1 (sdp_done_status1) //|< w
,.bdma_done_mask0 (bdma_done_mask0) //|> w
,.bdma_done_mask1 (bdma_done_mask1) //|> w
,.cacc_done_mask0 (cacc_done_mask0) //|> w
,.cacc_done_mask1 (cacc_done_mask1) //|> w
,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|> w
,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|> w
,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|> w
,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|> w
,.cdp_done_mask0 (cdp_done_mask0) //|> w
,.cdp_done_mask1 (cdp_done_mask1) //|> w
,.csb2glb_req_prdy (csb2glb_req_prdy) //|> o
,.glb2csb_resp_pd (glb2csb_resp_pd[33:0]) //|> o
,.glb2csb_resp_valid (glb2csb_resp_valid) //|> o
,.pdp_done_mask0 (pdp_done_mask0) //|> w
,.pdp_done_mask1 (pdp_done_mask1) //|> w
,.sdp_done_mask0 (sdp_done_mask0) //|> w
,.sdp_done_mask1 (sdp_done_mask1) //|> w
,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|> w
,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|> w
,.req_wdat (req_wdat[31:0]) //|> w
,.csb2nvdla_write(csb2nvdla_write) //|<i
,.cdma_op_en(cdma_op_en)//modified by jiazhaorong
);
////////////////////////////////////////////////////////
// interrupt controller
////////////////////////////////////////////////////////
NV_NVDLA_GLB_ic u_ic (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.bdma2glb_done_intr_pd (bdma2glb_done_intr_pd[1:0]) //|< i
,.bdma_done_mask0 (bdma_done_mask0) //|< w
,.bdma_done_mask1 (bdma_done_mask1) //|< w
,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) //|< i
,.cacc_done_mask0 (cacc_done_mask0) //|< w
,.cacc_done_mask1 (cacc_done_mask1) //|< w
,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) //|< i
,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|< w
,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|< w
,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) //|< i
,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|< w
,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|< w
,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|< i
,.cdp_done_mask0 (cdp_done_mask0) //|< w
,.cdp_done_mask1 (cdp_done_mask1) //|< w
,.nvdla_falcon_clk (nvdla_falcon_clk) //|< i
,.nvdla_falcon_rstn (nvdla_falcon_rstn) //|< i
,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|< i
,.pdp_done_mask0 (pdp_done_mask0) //|< w
,.pdp_done_mask1 (pdp_done_mask1) //|< w
,.req_wdat (req_wdat[21:0]) //|< w
,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) //|< i
,.sdp_done_mask0 (sdp_done_mask0) //|< w
,.sdp_done_mask1 (sdp_done_mask1) //|< w
,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|< w
,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|< w
,.bdma_done_status0 (bdma_done_status0) //|> w
,.bdma_done_status1 (bdma_done_status1) //|> w
,.cacc_done_status0 (cacc_done_status0) //|> w
,.cacc_done_status1 (cacc_done_status1) //|> w
,.cdma_dat_done_status0 (cdma_dat_done_status0) //|> w
,.cdma_dat_done_status1 (cdma_dat_done_status1) //|> w
,.cdma_wt_done_status0 (cdma_wt_done_status0) //|> w
,.cdma_wt_done_status1 (cdma_wt_done_status1) //|> w
,.cdp_done_status0 (cdp_done_status0) //|> w
,.cdp_done_status1 (cdp_done_status1) //|> w
,.pdp_done_status0 (pdp_done_status0) //|> w
,.pdp_done_status1 (pdp_done_status1) //|> w
,.sdp_done_status0 (sdp_done_status0) //|> w
,.sdp_done_status1 (sdp_done_status1) //|> w
,.core_intr (core_intr) //|> o
);
//////////////////////////////////////////////////////////
//// Dangles/Contenders report
//////////////////////////////////////////////////////////
endmodule // NV_NVDLA_glb |
module NV_NVDLA_SDP_rdma (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,sdp_b2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2cvif_rd_req_pd //|> o
,sdp_b2cvif_rd_req_valid //|> o
,sdp_b2cvif_rd_req_ready //|< i
,cvif2sdp_b_rd_rsp_pd //|< i
,cvif2sdp_b_rd_rsp_valid //|< i
,cvif2sdp_b_rd_rsp_ready //|> o
,sdp_e2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2cvif_rd_req_pd //|> o
,sdp_e2cvif_rd_req_valid //|> o
,sdp_e2cvif_rd_req_ready //|< i
,cvif2sdp_e_rd_rsp_pd //|< i
,cvif2sdp_e_rd_rsp_valid //|< i
,cvif2sdp_e_rd_rsp_ready //|> o
,sdp_n2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2cvif_rd_req_pd //|> o
,sdp_n2cvif_rd_req_valid //|> o
,sdp_n2cvif_rd_req_ready //|< i
,cvif2sdp_n_rd_rsp_pd //|< i
,cvif2sdp_n_rd_rsp_valid //|< i
,cvif2sdp_n_rd_rsp_ready //|> o
,sdp2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp2cvif_rd_req_pd //|> o
,sdp2cvif_rd_req_valid //|> o
,sdp2cvif_rd_req_ready //|< i
,cvif2sdp_rd_rsp_pd //|< i
,cvif2sdp_rd_rsp_valid //|< i
,cvif2sdp_rd_rsp_ready //|> o
,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_b2mcif_rd_req_pd //|> o
,sdp_b2mcif_rd_req_valid //|> o
,sdp_b2mcif_rd_req_ready //|< i
,mcif2sdp_b_rd_rsp_pd //|< i
,mcif2sdp_b_rd_rsp_valid //|< i
,mcif2sdp_b_rd_rsp_ready //|> o
,sdp_e2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_e2mcif_rd_req_pd //|> o
,sdp_e2mcif_rd_req_valid //|> o
,sdp_e2mcif_rd_req_ready //|< i
,mcif2sdp_e_rd_rsp_pd //|< i
,mcif2sdp_e_rd_rsp_valid //|< i
,mcif2sdp_e_rd_rsp_ready //|> o
,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp_n2mcif_rd_req_pd //|> o
,sdp_n2mcif_rd_req_valid //|> o
,sdp_n2mcif_rd_req_ready //|< i
,mcif2sdp_n_rd_rsp_pd //|< i
,mcif2sdp_n_rd_rsp_valid //|< i
,mcif2sdp_n_rd_rsp_ready //|> o
,sdp2mcif_rd_cdt_lat_fifo_pop //|> o
,sdp2mcif_rd_req_pd //|> o
,sdp2mcif_rd_req_valid //|> o
,sdp2mcif_rd_req_ready //|< i
,mcif2sdp_rd_rsp_pd //|< i
,mcif2sdp_rd_rsp_valid //|< i
,mcif2sdp_rd_rsp_ready //|> o
,sdp_brdma2dp_alu_ready //|< i
,sdp_brdma2dp_mul_ready //|< i
,sdp_brdma2dp_alu_pd //|> o
,sdp_brdma2dp_alu_valid //|> o
,sdp_brdma2dp_mul_pd //|> o
,sdp_brdma2dp_mul_valid //|> o
,sdp_erdma2dp_alu_ready //|< i
,sdp_erdma2dp_mul_ready //|< i
,sdp_erdma2dp_alu_pd //|> o
,sdp_erdma2dp_alu_valid //|> o
,sdp_erdma2dp_mul_pd //|> o
,sdp_erdma2dp_mul_valid //|> o
,sdp_nrdma2dp_alu_ready //|< i
,sdp_nrdma2dp_mul_ready //|< i
,sdp_nrdma2dp_alu_pd //|> o
,sdp_nrdma2dp_alu_valid //|> o
,sdp_nrdma2dp_mul_pd //|> o
,sdp_nrdma2dp_mul_valid //|> o
,sdp_mrdma2cmux_ready //|< i
,sdp_mrdma2cmux_pd //|> o
,sdp_mrdma2cmux_valid //|> o
,csb2sdp_rdma_req_pd //|< i
,csb2sdp_rdma_req_pvld //|< i
,csb2sdp_rdma_req_prdy //|> o
,sdp_rdma2csb_resp_pd //|> o
,sdp_rdma2csb_resp_valid //|> o
);
//
// NV_NVDLA_SDP_rdma_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
input csb2sdp_rdma_req_pvld;
output csb2sdp_rdma_req_prdy;
input [62:0] csb2sdp_rdma_req_pd;
output sdp_rdma2csb_resp_valid;
output [33:0] sdp_rdma2csb_resp_pd;
output sdp_b2cvif_rd_cdt_lat_fifo_pop;
output sdp_b2cvif_rd_req_valid;
input sdp_b2cvif_rd_req_ready;
output [79 -1:0] sdp_b2cvif_rd_req_pd;
input cvif2sdp_b_rd_rsp_valid;
output cvif2sdp_b_rd_rsp_ready;
input [257 -1:0] cvif2sdp_b_rd_rsp_pd;
output sdp_e2cvif_rd_cdt_lat_fifo_pop;
output sdp_e2cvif_rd_req_valid;
input sdp_e2cvif_rd_req_ready;
output [79 -1:0] sdp_e2cvif_rd_req_pd;
input cvif2sdp_e_rd_rsp_valid;
output cvif2sdp_e_rd_rsp_ready;
input [257 -1:0] cvif2sdp_e_rd_rsp_pd;
output sdp_n2cvif_rd_cdt_lat_fifo_pop;
output sdp_n2cvif_rd_req_valid;
input sdp_n2cvif_rd_req_ready;
output [79 -1:0] sdp_n2cvif_rd_req_pd;
input cvif2sdp_n_rd_rsp_valid;
output cvif2sdp_n_rd_rsp_ready;
input [257 -1:0] cvif2sdp_n_rd_rsp_pd;
output sdp2cvif_rd_cdt_lat_fifo_pop;
output sdp2cvif_rd_req_valid;
input sdp2cvif_rd_req_ready;
output [79 -1:0] sdp2cvif_rd_req_pd;
input cvif2sdp_rd_rsp_valid;
output cvif2sdp_rd_rsp_ready;
input [257 -1:0] cvif2sdp_rd_rsp_pd;
output sdp2mcif_rd_cdt_lat_fifo_pop;
output sdp2mcif_rd_req_valid;
input sdp2mcif_rd_req_ready;
output [79 -1:0] sdp2mcif_rd_req_pd;
input mcif2sdp_rd_rsp_valid;
output mcif2sdp_rd_rsp_ready;
input [257 -1:0] mcif2sdp_rd_rsp_pd;
output sdp_b2mcif_rd_cdt_lat_fifo_pop;
output sdp_b2mcif_rd_req_valid;
input sdp_b2mcif_rd_req_ready;
output [79 -1:0] sdp_b2mcif_rd_req_pd;
input mcif2sdp_b_rd_rsp_valid;
output mcif2sdp_b_rd_rsp_ready;
input [257 -1:0] mcif2sdp_b_rd_rsp_pd;
output sdp_brdma2dp_alu_valid;
input sdp_brdma2dp_alu_ready;
output [32*16:0] sdp_brdma2dp_alu_pd;
output sdp_brdma2dp_mul_valid;
input sdp_brdma2dp_mul_ready;
output [32*16:0] sdp_brdma2dp_mul_pd;
output sdp_e2mcif_rd_cdt_lat_fifo_pop;
output sdp_e2mcif_rd_req_valid;
input sdp_e2mcif_rd_req_ready;
output [79 -1:0] sdp_e2mcif_rd_req_pd;
input mcif2sdp_e_rd_rsp_valid;
output mcif2sdp_e_rd_rsp_ready;
input [257 -1:0] mcif2sdp_e_rd_rsp_pd;
output sdp_erdma2dp_alu_valid;
input sdp_erdma2dp_alu_ready;
output [32*16:0] sdp_erdma2dp_alu_pd;
output sdp_erdma2dp_mul_valid;
input sdp_erdma2dp_mul_ready;
output [32*16:0] sdp_erdma2dp_mul_pd;
output sdp_n2mcif_rd_cdt_lat_fifo_pop;
output sdp_n2mcif_rd_req_valid;
input sdp_n2mcif_rd_req_ready;
output [79 -1:0] sdp_n2mcif_rd_req_pd;
input mcif2sdp_n_rd_rsp_valid;
output mcif2sdp_n_rd_rsp_ready;
input [257 -1:0] mcif2sdp_n_rd_rsp_pd;
output sdp_nrdma2dp_alu_valid;
input sdp_nrdma2dp_alu_ready;
output [32*16:0] sdp_nrdma2dp_alu_pd;
output sdp_nrdma2dp_mul_valid;
input sdp_nrdma2dp_mul_ready;
output [32*16:0] sdp_nrdma2dp_mul_pd;
output sdp_mrdma2cmux_valid;
input sdp_mrdma2cmux_ready;
output [32*32 +1:0] sdp_mrdma2cmux_pd;
reg mrdma_done_pending;
wire dp2reg_done;
wire [31:0] dp2reg_mrdma_stall;
wire [31:0] dp2reg_status_inf_input_num;
wire [31:0] dp2reg_status_nan_input_num;
wire mrdma_disable;
wire nrdma_disable;
wire brdma_disable;
wire erdma_disable;
wire mrdma_done;
wire nrdma_done;
wire brdma_done;
wire erdma_done;
wire mrdma_op_en;
wire mrdma_slcg_op_en;
wire nrdma_slcg_op_en;
wire brdma_slcg_op_en;
wire erdma_slcg_op_en;
wire [4:0] reg2dp_batch_number;
wire nrdma_op_en;
wire reg2dp_nrdma_data_mode;
wire reg2dp_nrdma_data_size;
wire [1:0] reg2dp_nrdma_data_use;
wire reg2dp_nrdma_disable;
wire reg2dp_nrdma_ram_type;
wire [31:0] reg2dp_bn_base_addr_high;
wire [31:0] reg2dp_bn_base_addr_low;
wire [31:0] reg2dp_bn_batch_stride;
wire [31:0] reg2dp_bn_line_stride;
wire [31:0] reg2dp_bn_surface_stride;
wire [31:0] dp2reg_nrdma_stall;
wire brdma_op_en;
wire reg2dp_brdma_data_mode;
wire reg2dp_brdma_data_size;
wire [1:0] reg2dp_brdma_data_use;
wire reg2dp_brdma_disable;
wire reg2dp_brdma_ram_type;
wire [31:0] reg2dp_bs_base_addr_high;
wire [31:0] reg2dp_bs_base_addr_low;
wire [31:0] reg2dp_bs_batch_stride;
wire [31:0] reg2dp_bs_line_stride;
wire [31:0] reg2dp_bs_surface_stride;
wire [31:0] dp2reg_brdma_stall;
wire erdma_op_en;
wire reg2dp_erdma_data_mode;
wire reg2dp_erdma_data_size;
wire [1:0] reg2dp_erdma_data_use;
wire reg2dp_erdma_disable;
wire reg2dp_erdma_ram_type;
wire [31:0] reg2dp_ew_base_addr_high;
wire [31:0] reg2dp_ew_base_addr_low;
wire [31:0] reg2dp_ew_batch_stride;
wire [31:0] reg2dp_ew_line_stride;
wire [31:0] reg2dp_ew_surface_stride;
wire [31:0] dp2reg_erdma_stall;
wire reg2dp_op_en;
wire reg2dp_flying_mode;
wire reg2dp_src_ram_type;
wire [1:0] reg2dp_in_precision;
wire [1:0] reg2dp_out_precision;
wire reg2dp_perf_dma_en;
wire reg2dp_perf_nan_inf_count_en;
wire [1:0] reg2dp_proc_precision;
wire [31:0] reg2dp_src_base_addr_high;
wire [31:0] reg2dp_src_base_addr_low;
wire [31:0] reg2dp_src_line_stride;
wire [31:0] reg2dp_src_surface_stride;
wire [12:0] reg2dp_width;
wire [12:0] reg2dp_height;
wire [12:0] reg2dp_channel;
wire reg2dp_winograd;
wire [3:0] slcg_op_en;
//=======================================
// M-RDMA
NV_NVDLA_SDP_mrdma u_mrdma (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.mrdma_slcg_op_en (mrdma_slcg_op_en) //|< w
,.mrdma_disable (mrdma_disable) //|< w
,.cvif2sdp_rd_rsp_valid (cvif2sdp_rd_rsp_valid) //|< i
,.cvif2sdp_rd_rsp_ready (cvif2sdp_rd_rsp_ready) //|> o
,.cvif2sdp_rd_rsp_pd (cvif2sdp_rd_rsp_pd[257 -1:0]) //|< i
,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2cvif_rd_req_valid (sdp2cvif_rd_req_valid) //|> o
,.sdp2cvif_rd_req_ready (sdp2cvif_rd_req_ready) //|< i
,.sdp2cvif_rd_req_pd (sdp2cvif_rd_req_pd[79 -1:0]) //|> o
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) //|> o
,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) //|< i
,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[79 -1:0]) //|> o
,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|< i
,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|> o
,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) //|> o
,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) //|< i
,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*32 +1:0]) //|> o
,.reg2dp_op_en (mrdma_op_en) //|< w
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w
,.reg2dp_channel (reg2dp_channel[12:0]) //|< w
,.reg2dp_height (reg2dp_height[12:0]) //|< w
,.reg2dp_width (reg2dp_width[12:0]) //|< w
,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w
,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< w
,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w
,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:5]) //|< w
,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:5]) //|< w
,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:5]) //|< w
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w
,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|< w
,.dp2reg_done (mrdma_done) //|> w
,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|> w
,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|> w
,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|> w
);
NV_NVDLA_SDP_brdma u_brdma (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.brdma_slcg_op_en (brdma_slcg_op_en) //|< w
,.brdma_disable (brdma_disable) //|< w
,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_b2cvif_rd_req_valid (sdp_b2cvif_rd_req_valid) //|> o
,.sdp_b2cvif_rd_req_ready (sdp_b2cvif_rd_req_ready) //|< i
,.sdp_b2cvif_rd_req_pd (sdp_b2cvif_rd_req_pd[79 -1:0]) //|> o
,.cvif2sdp_b_rd_rsp_valid (cvif2sdp_b_rd_rsp_valid) //|< i
,.cvif2sdp_b_rd_rsp_ready (cvif2sdp_b_rd_rsp_ready) //|> o
,.cvif2sdp_b_rd_rsp_pd (cvif2sdp_b_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o
,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i
,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[79 -1:0]) //|> o
,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i
,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o
,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o
,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i
,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o
,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i
,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[32*16:0]) //|> o
,.reg2dp_op_en (brdma_op_en) //|< w
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w
,.reg2dp_winograd (reg2dp_winograd) //|< w
,.reg2dp_channel (reg2dp_channel[12:0]) //|< w
,.reg2dp_height (reg2dp_height[12:0]) //|< w
,.reg2dp_width (reg2dp_width[12:0]) //|< w
,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|< w
,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|< w
,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|< w
,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|< w
,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< w
,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:5]) //|< w
,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:5]) //|< w
,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:5]) //|< w
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w
,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|> w
,.dp2reg_done (brdma_done) //|> w
);
NV_NVDLA_SDP_nrdma u_nrdma (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< w
,.nrdma_disable (nrdma_disable) //|< w
,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_n2cvif_rd_req_valid (sdp_n2cvif_rd_req_valid) //|> o
,.sdp_n2cvif_rd_req_ready (sdp_n2cvif_rd_req_ready) //|< i
,.sdp_n2cvif_rd_req_pd (sdp_n2cvif_rd_req_pd[79 -1:0]) //|> o
,.cvif2sdp_n_rd_rsp_valid (cvif2sdp_n_rd_rsp_valid) //|< i
,.cvif2sdp_n_rd_rsp_ready (cvif2sdp_n_rd_rsp_ready) //|> o
,.cvif2sdp_n_rd_rsp_pd (cvif2sdp_n_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o
,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i
,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[79 -1:0]) //|> o
,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i
,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o
,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o
,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i
,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o
,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i
,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[32*16:0]) //|> o
,.reg2dp_op_en (nrdma_op_en) //|< w
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w
,.reg2dp_winograd (reg2dp_winograd) //|< w
,.reg2dp_channel (reg2dp_channel[12:0]) //|< w
,.reg2dp_height (reg2dp_height[12:0]) //|< w
,.reg2dp_width (reg2dp_width[12:0]) //|< w
,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|< w
,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|< w
,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< w
,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|< w
,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< w
,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:5]) //|< w
,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:5]) //|< w
,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:5]) //|< w
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w
,.dp2reg_done (nrdma_done) //|> w
,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|> w
);
NV_NVDLA_SDP_erdma u_erdma (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.erdma_slcg_op_en (erdma_slcg_op_en) //|< w
,.erdma_disable (erdma_disable) //|< w
,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_e2cvif_rd_req_valid (sdp_e2cvif_rd_req_valid) //|> o
,.sdp_e2cvif_rd_req_ready (sdp_e2cvif_rd_req_ready) //|< i
,.sdp_e2cvif_rd_req_pd (sdp_e2cvif_rd_req_pd[79 -1:0]) //|> o
,.cvif2sdp_e_rd_rsp_valid (cvif2sdp_e_rd_rsp_valid) //|< i
,.cvif2sdp_e_rd_rsp_ready (cvif2sdp_e_rd_rsp_ready) //|> o
,.cvif2sdp_e_rd_rsp_pd (cvif2sdp_e_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop) //|> o
,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid) //|> o
,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready) //|< i
,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[79 -1:0]) //|> o
,.mcif2sdp_e_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid) //|< i
,.mcif2sdp_e_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready) //|> o
,.mcif2sdp_e_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[257 -1:0]) //|< i
,.sdp_erdma2dp_alu_valid (sdp_erdma2dp_alu_valid) //|> o
,.sdp_erdma2dp_alu_ready (sdp_erdma2dp_alu_ready) //|< i
,.sdp_erdma2dp_alu_pd (sdp_erdma2dp_alu_pd[32*16:0]) //|> o
,.sdp_erdma2dp_mul_valid (sdp_erdma2dp_mul_valid) //|> o
,.sdp_erdma2dp_mul_ready (sdp_erdma2dp_mul_ready) //|< i
,.sdp_erdma2dp_mul_pd (sdp_erdma2dp_mul_pd[32*16:0]) //|> o
,.reg2dp_op_en (erdma_op_en) //|< w
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w
,.reg2dp_winograd (reg2dp_winograd) //|< w
,.reg2dp_channel (reg2dp_channel[12:0]) //|< w
,.reg2dp_height (reg2dp_height[12:0]) //|< w
,.reg2dp_width (reg2dp_width[12:0]) //|< w
,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode) //|< w
,.reg2dp_erdma_data_size (reg2dp_erdma_data_size) //|< w
,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0]) //|< w
,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type) //|< w
,.reg2dp_ew_base_addr_high (reg2dp_ew_base_addr_high[31:0]) //|< w
,.reg2dp_ew_base_addr_low (reg2dp_ew_base_addr_low[31:5]) //|< w
,.reg2dp_ew_line_stride (reg2dp_ew_line_stride[31:5]) //|< w
,.reg2dp_ew_surface_stride (reg2dp_ew_surface_stride[31:5]) //|< w
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w
,.dp2reg_done (erdma_done) //|> w
,.dp2reg_erdma_stall (dp2reg_erdma_stall[31:0]) //|> w
);
//=======================================
// Configuration Register File
assign mrdma_slcg_op_en = slcg_op_en[0];
assign brdma_slcg_op_en = slcg_op_en[1];
assign nrdma_slcg_op_en = slcg_op_en[2];
assign erdma_slcg_op_en = slcg_op_en[3];
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mrdma_done_pending <= 1'b0;
end else begin
if (dp2reg_done) begin
mrdma_done_pending <= 1'b0;
end else if (mrdma_done) begin
mrdma_done_pending <= 1'b1;
end
end
end
assign mrdma_op_en = reg2dp_op_en & ~mrdma_done_pending & ~mrdma_disable;
reg brdma_done_pending;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
brdma_done_pending <= 1'b0;
end else begin
if (dp2reg_done) begin
brdma_done_pending <= 1'b0;
end else if (brdma_done) begin
brdma_done_pending <= 1'b1;
end
end
end
assign brdma_op_en = reg2dp_op_en & ~brdma_done_pending & ~brdma_disable;
reg nrdma_done_pending;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
nrdma_done_pending <= 1'b0;
end else begin
if (dp2reg_done) begin
nrdma_done_pending <= 1'b0;
end else if (nrdma_done) begin
nrdma_done_pending <= 1'b1;
end
end
end
assign nrdma_op_en = reg2dp_op_en & ~nrdma_done_pending & ~nrdma_disable;
reg erdma_done_pending;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
erdma_done_pending <= 1'b0;
end else begin
if (dp2reg_done) begin
erdma_done_pending <= 1'b0;
end else if (erdma_done) begin
erdma_done_pending <= 1'b1;
end
end
end
assign erdma_op_en = reg2dp_op_en & ~erdma_done_pending & ~erdma_disable;
assign dp2reg_done = reg2dp_op_en & ((mrdma_done_pending || mrdma_done || mrdma_disable)&(brdma_done_pending || brdma_done || brdma_disable)&(nrdma_done_pending || nrdma_done || nrdma_disable)&(erdma_done_pending || erdma_done || erdma_disable));
assign mrdma_disable = reg2dp_flying_mode == 1'h1 ;
assign brdma_disable = reg2dp_brdma_disable == 1'h1 ;
assign nrdma_disable = reg2dp_nrdma_disable == 1'h1 ;
assign erdma_disable = reg2dp_erdma_disable == 1'h1 ;
NV_NVDLA_SDP_RDMA_reg u_reg (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) //|< i
,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) //|< i
,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) //|> o
,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) //|> o
,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) //|> o
,.slcg_op_en (slcg_op_en[3:0]) //|> w
,.dp2reg_done (dp2reg_done) //|< w
,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|< w
,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|< w
,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|< w
,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|> w
,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|> w
,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|> w
,.reg2dp_nrdma_disable (reg2dp_nrdma_disable) //|> w
,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|> w
,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|> w
,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:0]) //|> w
,.reg2dp_bn_batch_stride (reg2dp_bn_batch_stride[31:0]) //|> w
,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:0]) //|> w
,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:0]) //|> w
,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|< w
,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|> w
,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|> w
,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|> w
,.reg2dp_brdma_disable (reg2dp_brdma_disable) //|> w
,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|> w
,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|> w
,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:0]) //|> w
,.reg2dp_bs_batch_stride (reg2dp_bs_batch_stride[31:0]) //|> w
,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:0]) //|> w
,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:0]) //|> w
,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|< w
,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode) //|> w
,.reg2dp_erdma_data_size (reg2dp_erdma_data_size) //|> w
,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0]) //|> w
,.reg2dp_erdma_disable (reg2dp_erdma_disable) //|> w
,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type) //|> w
,.reg2dp_ew_base_addr_high (reg2dp_ew_base_addr_high[31:0]) //|> w
,.reg2dp_ew_base_addr_low (reg2dp_ew_base_addr_low[31:0]) //|> w
,.reg2dp_ew_batch_stride (reg2dp_ew_batch_stride[31:0]) //|> w
,.reg2dp_ew_line_stride (reg2dp_ew_line_stride[31:0]) //|> w
,.reg2dp_ew_surface_stride (reg2dp_ew_surface_stride[31:0]) //|> w
,.dp2reg_erdma_stall (dp2reg_erdma_stall[31:0]) //|< w
,.reg2dp_op_en (reg2dp_op_en) //|> w
,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|> w
,.reg2dp_winograd (reg2dp_winograd) //|> w
,.reg2dp_flying_mode (reg2dp_flying_mode) //|> w
,.reg2dp_channel (reg2dp_channel[12:0]) //|> w
,.reg2dp_height (reg2dp_height[12:0]) //|> w
,.reg2dp_width (reg2dp_width[12:0]) //|> w
,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|> w
,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|> w
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|> w
,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|> w
,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|> w
,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) //|> w
,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) //|> w
,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) //|> w
,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|> w
,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|> w
);
endmodule // NV_NVDLA_SDP_rdma |
module NV_NVDLA_cmac (
csb2cmac_a_req_pd //|< i
,csb2cmac_a_req_pvld //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,sc2mac_dat_data${i} //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,sc2mac_dat_data0 //|< i
,sc2mac_dat_data1 //|< i
,sc2mac_dat_data2 //|< i
,sc2mac_dat_data3 //|< i
,sc2mac_dat_data4 //|< i
,sc2mac_dat_data5 //|< i
,sc2mac_dat_data6 //|< i
,sc2mac_dat_data7 //|< i
,sc2mac_dat_data8 //|< i
,sc2mac_dat_data9 //|< i
,sc2mac_dat_data10 //|< i
,sc2mac_dat_data11 //|< i
,sc2mac_dat_data12 //|< i
,sc2mac_dat_data13 //|< i
,sc2mac_dat_data14 //|< i
,sc2mac_dat_data15 //|< i
,sc2mac_dat_data16 //|< i
,sc2mac_dat_data17 //|< i
,sc2mac_dat_data18 //|< i
,sc2mac_dat_data19 //|< i
,sc2mac_dat_data20 //|< i
,sc2mac_dat_data21 //|< i
,sc2mac_dat_data22 //|< i
,sc2mac_dat_data23 //|< i
,sc2mac_dat_data24 //|< i
,sc2mac_dat_data25 //|< i
,sc2mac_dat_data26 //|< i
,sc2mac_dat_data27 //|< i
,sc2mac_dat_data28 //|< i
,sc2mac_dat_data29 //|< i
,sc2mac_dat_data30 //|< i
,sc2mac_dat_data31 //|< i
,sc2mac_dat_data32 //|< i
,sc2mac_dat_data33 //|< i
,sc2mac_dat_data34 //|< i
,sc2mac_dat_data35 //|< i
,sc2mac_dat_data36 //|< i
,sc2mac_dat_data37 //|< i
,sc2mac_dat_data38 //|< i
,sc2mac_dat_data39 //|< i
,sc2mac_dat_data40 //|< i
,sc2mac_dat_data41 //|< i
,sc2mac_dat_data42 //|< i
,sc2mac_dat_data43 //|< i
,sc2mac_dat_data44 //|< i
,sc2mac_dat_data45 //|< i
,sc2mac_dat_data46 //|< i
,sc2mac_dat_data47 //|< i
,sc2mac_dat_data48 //|< i
,sc2mac_dat_data49 //|< i
,sc2mac_dat_data50 //|< i
,sc2mac_dat_data51 //|< i
,sc2mac_dat_data52 //|< i
,sc2mac_dat_data53 //|< i
,sc2mac_dat_data54 //|< i
,sc2mac_dat_data55 //|< i
,sc2mac_dat_data56 //|< i
,sc2mac_dat_data57 //|< i
,sc2mac_dat_data58 //|< i
,sc2mac_dat_data59 //|< i
,sc2mac_dat_data60 //|< i
,sc2mac_dat_data61 //|< i
,sc2mac_dat_data62 //|< i
,sc2mac_dat_data63 //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,sc2mac_dat_mask //|< i
,sc2mac_dat_pd //|< i
,sc2mac_dat_pvld //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,sc2mac_wt_data${i} //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,sc2mac_wt_data0 //|< i
,sc2mac_wt_data1 //|< i
,sc2mac_wt_data2 //|< i
,sc2mac_wt_data3 //|< i
,sc2mac_wt_data4 //|< i
,sc2mac_wt_data5 //|< i
,sc2mac_wt_data6 //|< i
,sc2mac_wt_data7 //|< i
,sc2mac_wt_data8 //|< i
,sc2mac_wt_data9 //|< i
,sc2mac_wt_data10 //|< i
,sc2mac_wt_data11 //|< i
,sc2mac_wt_data12 //|< i
,sc2mac_wt_data13 //|< i
,sc2mac_wt_data14 //|< i
,sc2mac_wt_data15 //|< i
,sc2mac_wt_data16 //|< i
,sc2mac_wt_data17 //|< i
,sc2mac_wt_data18 //|< i
,sc2mac_wt_data19 //|< i
,sc2mac_wt_data20 //|< i
,sc2mac_wt_data21 //|< i
,sc2mac_wt_data22 //|< i
,sc2mac_wt_data23 //|< i
,sc2mac_wt_data24 //|< i
,sc2mac_wt_data25 //|< i
,sc2mac_wt_data26 //|< i
,sc2mac_wt_data27 //|< i
,sc2mac_wt_data28 //|< i
,sc2mac_wt_data29 //|< i
,sc2mac_wt_data30 //|< i
,sc2mac_wt_data31 //|< i
,sc2mac_wt_data32 //|< i
,sc2mac_wt_data33 //|< i
,sc2mac_wt_data34 //|< i
,sc2mac_wt_data35 //|< i
,sc2mac_wt_data36 //|< i
,sc2mac_wt_data37 //|< i
,sc2mac_wt_data38 //|< i
,sc2mac_wt_data39 //|< i
,sc2mac_wt_data40 //|< i
,sc2mac_wt_data41 //|< i
,sc2mac_wt_data42 //|< i
,sc2mac_wt_data43 //|< i
,sc2mac_wt_data44 //|< i
,sc2mac_wt_data45 //|< i
,sc2mac_wt_data46 //|< i
,sc2mac_wt_data47 //|< i
,sc2mac_wt_data48 //|< i
,sc2mac_wt_data49 //|< i
,sc2mac_wt_data50 //|< i
,sc2mac_wt_data51 //|< i
,sc2mac_wt_data52 //|< i
,sc2mac_wt_data53 //|< i
,sc2mac_wt_data54 //|< i
,sc2mac_wt_data55 //|< i
,sc2mac_wt_data56 //|< i
,sc2mac_wt_data57 //|< i
,sc2mac_wt_data58 //|< i
,sc2mac_wt_data59 //|< i
,sc2mac_wt_data60 //|< i
,sc2mac_wt_data61 //|< i
,sc2mac_wt_data62 //|< i
,sc2mac_wt_data63 //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,sc2mac_wt_mask //|< i
,sc2mac_wt_pvld //|< i
,sc2mac_wt_sel //|< i
,tmc2slcg_disable_clock_gating //|< i
,cmac_a2csb_resp_pd //|> o
,cmac_a2csb_resp_valid //|> o
,csb2cmac_a_req_prdy //|> o
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,mac2accu_data${i} //|> o )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac2accu_data0 //|> o
,mac2accu_data1 //|> o
,mac2accu_data2 //|> o
,mac2accu_data3 //|> o
,mac2accu_data4 //|> o
,mac2accu_data5 //|> o
,mac2accu_data6 //|> o
,mac2accu_data7 //|> o
,mac2accu_data8 //|> o
,mac2accu_data9 //|> o
,mac2accu_data10 //|> o
,mac2accu_data11 //|> o
,mac2accu_data12 //|> o
,mac2accu_data13 //|> o
,mac2accu_data14 //|> o
,mac2accu_data15 //|> o
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac2accu_mask //|> o
,mac2accu_mode //|> o
,mac2accu_pd //|> o
,mac2accu_pvld //|> o
);
//
// NV_NVDLA_cmac_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
output cmac_a2csb_resp_valid; /* data valid */
output [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
input csb2cmac_a_req_pvld; /* data valid */
output csb2cmac_a_req_prdy; /* data return handshake */
input [62:0] csb2cmac_a_req_pd;
output mac2accu_pvld; /* data valid */
output [32/2 -1:0] mac2accu_mask;
output mac2accu_mode;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: output [22 -1:0] mac2accu_data${i}; //|> o )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
output [22 -1:0] mac2accu_data0; //|> o
output [22 -1:0] mac2accu_data1; //|> o
output [22 -1:0] mac2accu_data2; //|> o
output [22 -1:0] mac2accu_data3; //|> o
output [22 -1:0] mac2accu_data4; //|> o
output [22 -1:0] mac2accu_data5; //|> o
output [22 -1:0] mac2accu_data6; //|> o
output [22 -1:0] mac2accu_data7; //|> o
output [22 -1:0] mac2accu_data8; //|> o
output [22 -1:0] mac2accu_data9; //|> o
output [22 -1:0] mac2accu_data10; //|> o
output [22 -1:0] mac2accu_data11; //|> o
output [22 -1:0] mac2accu_data12; //|> o
output [22 -1:0] mac2accu_data13; //|> o
output [22 -1:0] mac2accu_data14; //|> o
output [22 -1:0] mac2accu_data15; //|> o
//| eperl: generated_end (DO NOT EDIT ABOVE)
output [8:0] mac2accu_pd;
input sc2mac_dat_pvld; /* data valid */
input [64 -1:0] sc2mac_dat_mask;
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: input [8 -1:0] sc2mac_dat_data${i}; //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [8 -1:0] sc2mac_dat_data0; //|< i
input [8 -1:0] sc2mac_dat_data1; //|< i
input [8 -1:0] sc2mac_dat_data2; //|< i
input [8 -1:0] sc2mac_dat_data3; //|< i
input [8 -1:0] sc2mac_dat_data4; //|< i
input [8 -1:0] sc2mac_dat_data5; //|< i
input [8 -1:0] sc2mac_dat_data6; //|< i
input [8 -1:0] sc2mac_dat_data7; //|< i
input [8 -1:0] sc2mac_dat_data8; //|< i
input [8 -1:0] sc2mac_dat_data9; //|< i
input [8 -1:0] sc2mac_dat_data10; //|< i
input [8 -1:0] sc2mac_dat_data11; //|< i
input [8 -1:0] sc2mac_dat_data12; //|< i
input [8 -1:0] sc2mac_dat_data13; //|< i
input [8 -1:0] sc2mac_dat_data14; //|< i
input [8 -1:0] sc2mac_dat_data15; //|< i
input [8 -1:0] sc2mac_dat_data16; //|< i
input [8 -1:0] sc2mac_dat_data17; //|< i
input [8 -1:0] sc2mac_dat_data18; //|< i
input [8 -1:0] sc2mac_dat_data19; //|< i
input [8 -1:0] sc2mac_dat_data20; //|< i
input [8 -1:0] sc2mac_dat_data21; //|< i
input [8 -1:0] sc2mac_dat_data22; //|< i
input [8 -1:0] sc2mac_dat_data23; //|< i
input [8 -1:0] sc2mac_dat_data24; //|< i
input [8 -1:0] sc2mac_dat_data25; //|< i
input [8 -1:0] sc2mac_dat_data26; //|< i
input [8 -1:0] sc2mac_dat_data27; //|< i
input [8 -1:0] sc2mac_dat_data28; //|< i
input [8 -1:0] sc2mac_dat_data29; //|< i
input [8 -1:0] sc2mac_dat_data30; //|< i
input [8 -1:0] sc2mac_dat_data31; //|< i
input [8 -1:0] sc2mac_dat_data32; //|< i
input [8 -1:0] sc2mac_dat_data33; //|< i
input [8 -1:0] sc2mac_dat_data34; //|< i
input [8 -1:0] sc2mac_dat_data35; //|< i
input [8 -1:0] sc2mac_dat_data36; //|< i
input [8 -1:0] sc2mac_dat_data37; //|< i
input [8 -1:0] sc2mac_dat_data38; //|< i
input [8 -1:0] sc2mac_dat_data39; //|< i
input [8 -1:0] sc2mac_dat_data40; //|< i
input [8 -1:0] sc2mac_dat_data41; //|< i
input [8 -1:0] sc2mac_dat_data42; //|< i
input [8 -1:0] sc2mac_dat_data43; //|< i
input [8 -1:0] sc2mac_dat_data44; //|< i
input [8 -1:0] sc2mac_dat_data45; //|< i
input [8 -1:0] sc2mac_dat_data46; //|< i
input [8 -1:0] sc2mac_dat_data47; //|< i
input [8 -1:0] sc2mac_dat_data48; //|< i
input [8 -1:0] sc2mac_dat_data49; //|< i
input [8 -1:0] sc2mac_dat_data50; //|< i
input [8 -1:0] sc2mac_dat_data51; //|< i
input [8 -1:0] sc2mac_dat_data52; //|< i
input [8 -1:0] sc2mac_dat_data53; //|< i
input [8 -1:0] sc2mac_dat_data54; //|< i
input [8 -1:0] sc2mac_dat_data55; //|< i
input [8 -1:0] sc2mac_dat_data56; //|< i
input [8 -1:0] sc2mac_dat_data57; //|< i
input [8 -1:0] sc2mac_dat_data58; //|< i
input [8 -1:0] sc2mac_dat_data59; //|< i
input [8 -1:0] sc2mac_dat_data60; //|< i
input [8 -1:0] sc2mac_dat_data61; //|< i
input [8 -1:0] sc2mac_dat_data62; //|< i
input [8 -1:0] sc2mac_dat_data63; //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [8:0] sc2mac_dat_pd;
input sc2mac_wt_pvld; /* data valid */
input [64 -1:0] sc2mac_wt_mask;
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: input [8 -1:0] sc2mac_wt_data${i}; //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [8 -1:0] sc2mac_wt_data0; //|< i
input [8 -1:0] sc2mac_wt_data1; //|< i
input [8 -1:0] sc2mac_wt_data2; //|< i
input [8 -1:0] sc2mac_wt_data3; //|< i
input [8 -1:0] sc2mac_wt_data4; //|< i
input [8 -1:0] sc2mac_wt_data5; //|< i
input [8 -1:0] sc2mac_wt_data6; //|< i
input [8 -1:0] sc2mac_wt_data7; //|< i
input [8 -1:0] sc2mac_wt_data8; //|< i
input [8 -1:0] sc2mac_wt_data9; //|< i
input [8 -1:0] sc2mac_wt_data10; //|< i
input [8 -1:0] sc2mac_wt_data11; //|< i
input [8 -1:0] sc2mac_wt_data12; //|< i
input [8 -1:0] sc2mac_wt_data13; //|< i
input [8 -1:0] sc2mac_wt_data14; //|< i
input [8 -1:0] sc2mac_wt_data15; //|< i
input [8 -1:0] sc2mac_wt_data16; //|< i
input [8 -1:0] sc2mac_wt_data17; //|< i
input [8 -1:0] sc2mac_wt_data18; //|< i
input [8 -1:0] sc2mac_wt_data19; //|< i
input [8 -1:0] sc2mac_wt_data20; //|< i
input [8 -1:0] sc2mac_wt_data21; //|< i
input [8 -1:0] sc2mac_wt_data22; //|< i
input [8 -1:0] sc2mac_wt_data23; //|< i
input [8 -1:0] sc2mac_wt_data24; //|< i
input [8 -1:0] sc2mac_wt_data25; //|< i
input [8 -1:0] sc2mac_wt_data26; //|< i
input [8 -1:0] sc2mac_wt_data27; //|< i
input [8 -1:0] sc2mac_wt_data28; //|< i
input [8 -1:0] sc2mac_wt_data29; //|< i
input [8 -1:0] sc2mac_wt_data30; //|< i
input [8 -1:0] sc2mac_wt_data31; //|< i
input [8 -1:0] sc2mac_wt_data32; //|< i
input [8 -1:0] sc2mac_wt_data33; //|< i
input [8 -1:0] sc2mac_wt_data34; //|< i
input [8 -1:0] sc2mac_wt_data35; //|< i
input [8 -1:0] sc2mac_wt_data36; //|< i
input [8 -1:0] sc2mac_wt_data37; //|< i
input [8 -1:0] sc2mac_wt_data38; //|< i
input [8 -1:0] sc2mac_wt_data39; //|< i
input [8 -1:0] sc2mac_wt_data40; //|< i
input [8 -1:0] sc2mac_wt_data41; //|< i
input [8 -1:0] sc2mac_wt_data42; //|< i
input [8 -1:0] sc2mac_wt_data43; //|< i
input [8 -1:0] sc2mac_wt_data44; //|< i
input [8 -1:0] sc2mac_wt_data45; //|< i
input [8 -1:0] sc2mac_wt_data46; //|< i
input [8 -1:0] sc2mac_wt_data47; //|< i
input [8 -1:0] sc2mac_wt_data48; //|< i
input [8 -1:0] sc2mac_wt_data49; //|< i
input [8 -1:0] sc2mac_wt_data50; //|< i
input [8 -1:0] sc2mac_wt_data51; //|< i
input [8 -1:0] sc2mac_wt_data52; //|< i
input [8 -1:0] sc2mac_wt_data53; //|< i
input [8 -1:0] sc2mac_wt_data54; //|< i
input [8 -1:0] sc2mac_wt_data55; //|< i
input [8 -1:0] sc2mac_wt_data56; //|< i
input [8 -1:0] sc2mac_wt_data57; //|< i
input [8 -1:0] sc2mac_wt_data58; //|< i
input [8 -1:0] sc2mac_wt_data59; //|< i
input [8 -1:0] sc2mac_wt_data60; //|< i
input [8 -1:0] sc2mac_wt_data61; //|< i
input [8 -1:0] sc2mac_wt_data62; //|< i
input [8 -1:0] sc2mac_wt_data63; //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [32/2 -1:0] sc2mac_wt_sel;
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
wire dp2reg_done;
wire [0:0] reg2dp_conv_mode;
wire [0:0] reg2dp_op_en;
wire [1:0] reg2dp_proc_precision=2'b0;
wire [3+32/2 -1:0] slcg_op_en;
//==========================================================
// core
//==========================================================
NV_NVDLA_CMAC_core u_core (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i
,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.sc2mac_dat_data0 (sc2mac_dat_data0) //|< i
,.sc2mac_dat_data1 (sc2mac_dat_data1) //|< i
,.sc2mac_dat_data2 (sc2mac_dat_data2) //|< i
,.sc2mac_dat_data3 (sc2mac_dat_data3) //|< i
,.sc2mac_dat_data4 (sc2mac_dat_data4) //|< i
,.sc2mac_dat_data5 (sc2mac_dat_data5) //|< i
,.sc2mac_dat_data6 (sc2mac_dat_data6) //|< i
,.sc2mac_dat_data7 (sc2mac_dat_data7) //|< i
,.sc2mac_dat_data8 (sc2mac_dat_data8) //|< i
,.sc2mac_dat_data9 (sc2mac_dat_data9) //|< i
,.sc2mac_dat_data10 (sc2mac_dat_data10) //|< i
,.sc2mac_dat_data11 (sc2mac_dat_data11) //|< i
,.sc2mac_dat_data12 (sc2mac_dat_data12) //|< i
,.sc2mac_dat_data13 (sc2mac_dat_data13) //|< i
,.sc2mac_dat_data14 (sc2mac_dat_data14) //|< i
,.sc2mac_dat_data15 (sc2mac_dat_data15) //|< i
,.sc2mac_dat_data16 (sc2mac_dat_data16) //|< i
,.sc2mac_dat_data17 (sc2mac_dat_data17) //|< i
,.sc2mac_dat_data18 (sc2mac_dat_data18) //|< i
,.sc2mac_dat_data19 (sc2mac_dat_data19) //|< i
,.sc2mac_dat_data20 (sc2mac_dat_data20) //|< i
,.sc2mac_dat_data21 (sc2mac_dat_data21) //|< i
,.sc2mac_dat_data22 (sc2mac_dat_data22) //|< i
,.sc2mac_dat_data23 (sc2mac_dat_data23) //|< i
,.sc2mac_dat_data24 (sc2mac_dat_data24) //|< i
,.sc2mac_dat_data25 (sc2mac_dat_data25) //|< i
,.sc2mac_dat_data26 (sc2mac_dat_data26) //|< i
,.sc2mac_dat_data27 (sc2mac_dat_data27) //|< i
,.sc2mac_dat_data28 (sc2mac_dat_data28) //|< i
,.sc2mac_dat_data29 (sc2mac_dat_data29) //|< i
,.sc2mac_dat_data30 (sc2mac_dat_data30) //|< i
,.sc2mac_dat_data31 (sc2mac_dat_data31) //|< i
,.sc2mac_dat_data32 (sc2mac_dat_data32) //|< i
,.sc2mac_dat_data33 (sc2mac_dat_data33) //|< i
,.sc2mac_dat_data34 (sc2mac_dat_data34) //|< i
,.sc2mac_dat_data35 (sc2mac_dat_data35) //|< i
,.sc2mac_dat_data36 (sc2mac_dat_data36) //|< i
,.sc2mac_dat_data37 (sc2mac_dat_data37) //|< i
,.sc2mac_dat_data38 (sc2mac_dat_data38) //|< i
,.sc2mac_dat_data39 (sc2mac_dat_data39) //|< i
,.sc2mac_dat_data40 (sc2mac_dat_data40) //|< i
,.sc2mac_dat_data41 (sc2mac_dat_data41) //|< i
,.sc2mac_dat_data42 (sc2mac_dat_data42) //|< i
,.sc2mac_dat_data43 (sc2mac_dat_data43) //|< i
,.sc2mac_dat_data44 (sc2mac_dat_data44) //|< i
,.sc2mac_dat_data45 (sc2mac_dat_data45) //|< i
,.sc2mac_dat_data46 (sc2mac_dat_data46) //|< i
,.sc2mac_dat_data47 (sc2mac_dat_data47) //|< i
,.sc2mac_dat_data48 (sc2mac_dat_data48) //|< i
,.sc2mac_dat_data49 (sc2mac_dat_data49) //|< i
,.sc2mac_dat_data50 (sc2mac_dat_data50) //|< i
,.sc2mac_dat_data51 (sc2mac_dat_data51) //|< i
,.sc2mac_dat_data52 (sc2mac_dat_data52) //|< i
,.sc2mac_dat_data53 (sc2mac_dat_data53) //|< i
,.sc2mac_dat_data54 (sc2mac_dat_data54) //|< i
,.sc2mac_dat_data55 (sc2mac_dat_data55) //|< i
,.sc2mac_dat_data56 (sc2mac_dat_data56) //|< i
,.sc2mac_dat_data57 (sc2mac_dat_data57) //|< i
,.sc2mac_dat_data58 (sc2mac_dat_data58) //|< i
,.sc2mac_dat_data59 (sc2mac_dat_data59) //|< i
,.sc2mac_dat_data60 (sc2mac_dat_data60) //|< i
,.sc2mac_dat_data61 (sc2mac_dat_data61) //|< i
,.sc2mac_dat_data62 (sc2mac_dat_data62) //|< i
,.sc2mac_dat_data63 (sc2mac_dat_data63) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i
,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i
,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i
//: for(my $i=0; $i<64 ; $i++){
//: print qq(
//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.sc2mac_wt_data0 (sc2mac_wt_data0) //|< i
,.sc2mac_wt_data1 (sc2mac_wt_data1) //|< i
,.sc2mac_wt_data2 (sc2mac_wt_data2) //|< i
,.sc2mac_wt_data3 (sc2mac_wt_data3) //|< i
,.sc2mac_wt_data4 (sc2mac_wt_data4) //|< i
,.sc2mac_wt_data5 (sc2mac_wt_data5) //|< i
,.sc2mac_wt_data6 (sc2mac_wt_data6) //|< i
,.sc2mac_wt_data7 (sc2mac_wt_data7) //|< i
,.sc2mac_wt_data8 (sc2mac_wt_data8) //|< i
,.sc2mac_wt_data9 (sc2mac_wt_data9) //|< i
,.sc2mac_wt_data10 (sc2mac_wt_data10) //|< i
,.sc2mac_wt_data11 (sc2mac_wt_data11) //|< i
,.sc2mac_wt_data12 (sc2mac_wt_data12) //|< i
,.sc2mac_wt_data13 (sc2mac_wt_data13) //|< i
,.sc2mac_wt_data14 (sc2mac_wt_data14) //|< i
,.sc2mac_wt_data15 (sc2mac_wt_data15) //|< i
,.sc2mac_wt_data16 (sc2mac_wt_data16) //|< i
,.sc2mac_wt_data17 (sc2mac_wt_data17) //|< i
,.sc2mac_wt_data18 (sc2mac_wt_data18) //|< i
,.sc2mac_wt_data19 (sc2mac_wt_data19) //|< i
,.sc2mac_wt_data20 (sc2mac_wt_data20) //|< i
,.sc2mac_wt_data21 (sc2mac_wt_data21) //|< i
,.sc2mac_wt_data22 (sc2mac_wt_data22) //|< i
,.sc2mac_wt_data23 (sc2mac_wt_data23) //|< i
,.sc2mac_wt_data24 (sc2mac_wt_data24) //|< i
,.sc2mac_wt_data25 (sc2mac_wt_data25) //|< i
,.sc2mac_wt_data26 (sc2mac_wt_data26) //|< i
,.sc2mac_wt_data27 (sc2mac_wt_data27) //|< i
,.sc2mac_wt_data28 (sc2mac_wt_data28) //|< i
,.sc2mac_wt_data29 (sc2mac_wt_data29) //|< i
,.sc2mac_wt_data30 (sc2mac_wt_data30) //|< i
,.sc2mac_wt_data31 (sc2mac_wt_data31) //|< i
,.sc2mac_wt_data32 (sc2mac_wt_data32) //|< i
,.sc2mac_wt_data33 (sc2mac_wt_data33) //|< i
,.sc2mac_wt_data34 (sc2mac_wt_data34) //|< i
,.sc2mac_wt_data35 (sc2mac_wt_data35) //|< i
,.sc2mac_wt_data36 (sc2mac_wt_data36) //|< i
,.sc2mac_wt_data37 (sc2mac_wt_data37) //|< i
,.sc2mac_wt_data38 (sc2mac_wt_data38) //|< i
,.sc2mac_wt_data39 (sc2mac_wt_data39) //|< i
,.sc2mac_wt_data40 (sc2mac_wt_data40) //|< i
,.sc2mac_wt_data41 (sc2mac_wt_data41) //|< i
,.sc2mac_wt_data42 (sc2mac_wt_data42) //|< i
,.sc2mac_wt_data43 (sc2mac_wt_data43) //|< i
,.sc2mac_wt_data44 (sc2mac_wt_data44) //|< i
,.sc2mac_wt_data45 (sc2mac_wt_data45) //|< i
,.sc2mac_wt_data46 (sc2mac_wt_data46) //|< i
,.sc2mac_wt_data47 (sc2mac_wt_data47) //|< i
,.sc2mac_wt_data48 (sc2mac_wt_data48) //|< i
,.sc2mac_wt_data49 (sc2mac_wt_data49) //|< i
,.sc2mac_wt_data50 (sc2mac_wt_data50) //|< i
,.sc2mac_wt_data51 (sc2mac_wt_data51) //|< i
,.sc2mac_wt_data52 (sc2mac_wt_data52) //|< i
,.sc2mac_wt_data53 (sc2mac_wt_data53) //|< i
,.sc2mac_wt_data54 (sc2mac_wt_data54) //|< i
,.sc2mac_wt_data55 (sc2mac_wt_data55) //|< i
,.sc2mac_wt_data56 (sc2mac_wt_data56) //|< i
,.sc2mac_wt_data57 (sc2mac_wt_data57) //|< i
,.sc2mac_wt_data58 (sc2mac_wt_data58) //|< i
,.sc2mac_wt_data59 (sc2mac_wt_data59) //|< i
,.sc2mac_wt_data60 (sc2mac_wt_data60) //|< i
,.sc2mac_wt_data61 (sc2mac_wt_data61) //|< i
,.sc2mac_wt_data62 (sc2mac_wt_data62) //|< i
,.sc2mac_wt_data63 (sc2mac_wt_data63) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i
,.mac2accu_pvld (mac2accu_pvld) //|> o
,.mac2accu_mask (mac2accu_mask) //|> o
,.mac2accu_mode (mac2accu_mode) //|> o
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac2accu_data0 (mac2accu_data0) //|> o
,.mac2accu_data1 (mac2accu_data1) //|> o
,.mac2accu_data2 (mac2accu_data2) //|> o
,.mac2accu_data3 (mac2accu_data3) //|> o
,.mac2accu_data4 (mac2accu_data4) //|> o
,.mac2accu_data5 (mac2accu_data5) //|> o
,.mac2accu_data6 (mac2accu_data6) //|> o
,.mac2accu_data7 (mac2accu_data7) //|> o
,.mac2accu_data8 (mac2accu_data8) //|> o
,.mac2accu_data9 (mac2accu_data9) //|> o
,.mac2accu_data10 (mac2accu_data10) //|> o
,.mac2accu_data11 (mac2accu_data11) //|> o
,.mac2accu_data12 (mac2accu_data12) //|> o
,.mac2accu_data13 (mac2accu_data13) //|> o
,.mac2accu_data14 (mac2accu_data14) //|> o
,.mac2accu_data15 (mac2accu_data15) //|> o
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac2accu_pd (mac2accu_pd) //|> o
,.reg2dp_op_en (reg2dp_op_en) //|< w
,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w
,.dp2reg_done (dp2reg_done) //|> w
,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.slcg_op_en (slcg_op_en) //|< w
);
//==========================================================
// reg
//==========================================================
wire [1:0] reg2dp_proc_precision_NC;
NV_NVDLA_CMAC_reg u_reg (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i
,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i
,.dp2reg_done (dp2reg_done) //|< w
,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o
,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o
,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o
,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w
,.reg2dp_op_en (reg2dp_op_en) //|> w
,.reg2dp_proc_precision (reg2dp_proc_precision_NC) //|> w //dangle
,.slcg_op_en (slcg_op_en) //|> w
);
endmodule // NV_NVDLA_cmac |
module NV_NVDLA_MCIF_read (
nvdla_core_clk
,nvdla_core_rstn
,pwrbus_ram_pd
,reg2dp_rd_os_cnt
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,reg2dp_rd_weight_${client}\n"),
//: }
//: foreach my $client (@rdma_name) {
//: print(" ,${client}2mcif_rd_cdt_lat_fifo_pop\n");
//: print(" ,${client}2mcif_rd_req_valid\n");
//: print(" ,${client}2mcif_rd_req_ready\n");
//: print(" ,${client}2mcif_rd_req_pd\n");
//: print(" ,mcif2${client}_rd_rsp_valid\n");
//: print(" ,mcif2${client}_rd_rsp_ready\n");
//: print(" ,mcif2${client}_rd_rsp_pd\n"),
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,reg2dp_rd_weight_cdma_dat
,reg2dp_rd_weight_cdma_wt
,reg2dp_rd_weight_sdp
,reg2dp_rd_weight_sdp_b
,reg2dp_rd_weight_sdp_n
,reg2dp_rd_weight_sdp_e
,reg2dp_rd_weight_pdp
,reg2dp_rd_weight_cdp
,reg2dp_rd_weight_bdma
,cdma_dat2mcif_rd_cdt_lat_fifo_pop
,cdma_dat2mcif_rd_req_valid
,cdma_dat2mcif_rd_req_ready
,cdma_dat2mcif_rd_req_pd
,mcif2cdma_dat_rd_rsp_valid
,mcif2cdma_dat_rd_rsp_ready
,mcif2cdma_dat_rd_rsp_pd
,cdma_wt2mcif_rd_cdt_lat_fifo_pop
,cdma_wt2mcif_rd_req_valid
,cdma_wt2mcif_rd_req_ready
,cdma_wt2mcif_rd_req_pd
,mcif2cdma_wt_rd_rsp_valid
,mcif2cdma_wt_rd_rsp_ready
,mcif2cdma_wt_rd_rsp_pd
,sdp2mcif_rd_cdt_lat_fifo_pop
,sdp2mcif_rd_req_valid
,sdp2mcif_rd_req_ready
,sdp2mcif_rd_req_pd
,mcif2sdp_rd_rsp_valid
,mcif2sdp_rd_rsp_ready
,mcif2sdp_rd_rsp_pd
,sdp_b2mcif_rd_cdt_lat_fifo_pop
,sdp_b2mcif_rd_req_valid
,sdp_b2mcif_rd_req_ready
,sdp_b2mcif_rd_req_pd
,mcif2sdp_b_rd_rsp_valid
,mcif2sdp_b_rd_rsp_ready
,mcif2sdp_b_rd_rsp_pd
,sdp_n2mcif_rd_cdt_lat_fifo_pop
,sdp_n2mcif_rd_req_valid
,sdp_n2mcif_rd_req_ready
,sdp_n2mcif_rd_req_pd
,mcif2sdp_n_rd_rsp_valid
,mcif2sdp_n_rd_rsp_ready
,mcif2sdp_n_rd_rsp_pd
,sdp_e2mcif_rd_cdt_lat_fifo_pop
,sdp_e2mcif_rd_req_valid
,sdp_e2mcif_rd_req_ready
,sdp_e2mcif_rd_req_pd
,mcif2sdp_e_rd_rsp_valid
,mcif2sdp_e_rd_rsp_ready
,mcif2sdp_e_rd_rsp_pd
,pdp2mcif_rd_cdt_lat_fifo_pop
,pdp2mcif_rd_req_valid
,pdp2mcif_rd_req_ready
,pdp2mcif_rd_req_pd
,mcif2pdp_rd_rsp_valid
,mcif2pdp_rd_rsp_ready
,mcif2pdp_rd_rsp_pd
,cdp2mcif_rd_cdt_lat_fifo_pop
,cdp2mcif_rd_req_valid
,cdp2mcif_rd_req_ready
,cdp2mcif_rd_req_pd
,mcif2cdp_rd_rsp_valid
,mcif2cdp_rd_rsp_ready
,mcif2cdp_rd_rsp_pd
,bdma2mcif_rd_cdt_lat_fifo_pop
,bdma2mcif_rd_req_valid
,bdma2mcif_rd_req_ready
,bdma2mcif_rd_req_pd
,mcif2bdma_rd_rsp_valid
,mcif2bdma_rd_rsp_ready
,mcif2bdma_rd_rsp_pd
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mcif2noc_axi_ar_arvalid
,mcif2noc_axi_ar_arready
,mcif2noc_axi_ar_arid
,mcif2noc_axi_ar_arlen
,mcif2noc_axi_ar_araddr
,noc2mcif_axi_r_rvalid
,noc2mcif_axi_r_rready
,noc2mcif_axi_r_rid
,noc2mcif_axi_r_rlast
,noc2mcif_axi_r_rdata
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input [7:0] reg2dp_rd_os_cnt;
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print "input [7:0] reg2dp_rd_weight_${client};\n";
//: }
//: foreach my $client (@rdma_name) {
//: print("input ${client}2mcif_rd_cdt_lat_fifo_pop;\n");
//: print("input ${client}2mcif_rd_req_valid;\n");
//: print("output ${client}2mcif_rd_req_ready;\n");
//: print qq(input [79 -1:0] ${client}2mcif_rd_req_pd;\n);
//: print("output mcif2${client}_rd_rsp_valid;\n");
//: print("input mcif2${client}_rd_rsp_ready;\n");
//: print qq(output [257 -1:0] mcif2${client}_rd_rsp_pd;\n);
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_n;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_bdma;
input cdma_dat2mcif_rd_cdt_lat_fifo_pop;
input cdma_dat2mcif_rd_req_valid;
output cdma_dat2mcif_rd_req_ready;
input [79 -1:0] cdma_dat2mcif_rd_req_pd;
output mcif2cdma_dat_rd_rsp_valid;
input mcif2cdma_dat_rd_rsp_ready;
output [257 -1:0] mcif2cdma_dat_rd_rsp_pd;
input cdma_wt2mcif_rd_cdt_lat_fifo_pop;
input cdma_wt2mcif_rd_req_valid;
output cdma_wt2mcif_rd_req_ready;
input [79 -1:0] cdma_wt2mcif_rd_req_pd;
output mcif2cdma_wt_rd_rsp_valid;
input mcif2cdma_wt_rd_rsp_ready;
output [257 -1:0] mcif2cdma_wt_rd_rsp_pd;
input sdp2mcif_rd_cdt_lat_fifo_pop;
input sdp2mcif_rd_req_valid;
output sdp2mcif_rd_req_ready;
input [79 -1:0] sdp2mcif_rd_req_pd;
output mcif2sdp_rd_rsp_valid;
input mcif2sdp_rd_rsp_ready;
output [257 -1:0] mcif2sdp_rd_rsp_pd;
input sdp_b2mcif_rd_cdt_lat_fifo_pop;
input sdp_b2mcif_rd_req_valid;
output sdp_b2mcif_rd_req_ready;
input [79 -1:0] sdp_b2mcif_rd_req_pd;
output mcif2sdp_b_rd_rsp_valid;
input mcif2sdp_b_rd_rsp_ready;
output [257 -1:0] mcif2sdp_b_rd_rsp_pd;
input sdp_n2mcif_rd_cdt_lat_fifo_pop;
input sdp_n2mcif_rd_req_valid;
output sdp_n2mcif_rd_req_ready;
input [79 -1:0] sdp_n2mcif_rd_req_pd;
output mcif2sdp_n_rd_rsp_valid;
input mcif2sdp_n_rd_rsp_ready;
output [257 -1:0] mcif2sdp_n_rd_rsp_pd;
input sdp_e2mcif_rd_cdt_lat_fifo_pop;
input sdp_e2mcif_rd_req_valid;
output sdp_e2mcif_rd_req_ready;
input [79 -1:0] sdp_e2mcif_rd_req_pd;
output mcif2sdp_e_rd_rsp_valid;
input mcif2sdp_e_rd_rsp_ready;
output [257 -1:0] mcif2sdp_e_rd_rsp_pd;
input pdp2mcif_rd_cdt_lat_fifo_pop;
input pdp2mcif_rd_req_valid;
output pdp2mcif_rd_req_ready;
input [79 -1:0] pdp2mcif_rd_req_pd;
output mcif2pdp_rd_rsp_valid;
input mcif2pdp_rd_rsp_ready;
output [257 -1:0] mcif2pdp_rd_rsp_pd;
input cdp2mcif_rd_cdt_lat_fifo_pop;
input cdp2mcif_rd_req_valid;
output cdp2mcif_rd_req_ready;
input [79 -1:0] cdp2mcif_rd_req_pd;
output mcif2cdp_rd_rsp_valid;
input mcif2cdp_rd_rsp_ready;
output [257 -1:0] mcif2cdp_rd_rsp_pd;
input bdma2mcif_rd_cdt_lat_fifo_pop;
input bdma2mcif_rd_req_valid;
output bdma2mcif_rd_req_ready;
input [79 -1:0] bdma2mcif_rd_req_pd;
output mcif2bdma_rd_rsp_valid;
input mcif2bdma_rd_rsp_ready;
output [257 -1:0] mcif2bdma_rd_rsp_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input noc2mcif_axi_r_rvalid;
output noc2mcif_axi_r_rready;
input [7:0] noc2mcif_axi_r_rid;
input noc2mcif_axi_r_rlast;
input [256 -1:0] noc2mcif_axi_r_rdata;
output mcif2noc_axi_ar_arvalid;
input mcif2noc_axi_ar_arready;
output [7:0] mcif2noc_axi_ar_arid;
output [3:0] mcif2noc_axi_ar_arlen;
output [64 -1:0] mcif2noc_axi_ar_araddr;
wire eg2ig_axi_vld;
NV_NVDLA_MCIF_READ_ig u_ig (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt)
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,.reg2dp_rd_weight_${client} (reg2dp_rd_weight_${client})\n");
//: }
//: foreach my $client (@rdma_name) {
//: print (" ,.${client}2mcif_rd_cdt_lat_fifo_pop (${client}2mcif_rd_cdt_lat_fifo_pop)\n");
//: print (" ,.${client}2mcif_rd_req_valid (${client}2mcif_rd_req_valid)\n");
//: print (" ,.${client}2mcif_rd_req_ready (${client}2mcif_rd_req_ready)\n");
//: print (" ,.${client}2mcif_rd_req_pd (${client}2mcif_rd_req_pd)\n");
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat)
,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt)
,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp)
,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b)
,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n)
,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e)
,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp)
,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp)
,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma)
,.cdma_dat2mcif_rd_cdt_lat_fifo_pop (cdma_dat2mcif_rd_cdt_lat_fifo_pop)
,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid)
,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready)
,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd)
,.cdma_wt2mcif_rd_cdt_lat_fifo_pop (cdma_wt2mcif_rd_cdt_lat_fifo_pop)
,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid)
,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready)
,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd)
,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid)
,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready)
,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd)
,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid)
,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready)
,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd)
,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid)
,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready)
,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd)
,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid)
,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready)
,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd)
,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop)
,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid)
,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready)
,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd)
,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop)
,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid)
,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready)
,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd)
,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid)
,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready)
,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o
,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i
,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o
,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o
,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr) //|> o
,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w
);
NV_NVDLA_MCIF_READ_eg u_eg (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w
//: my @rdma_name = ("cdma_dat","cdma_wt","sdp", "sdp_b","sdp_n","sdp_e","pdp","cdp","bdma");
//: foreach my $client (@rdma_name) {
//: print(" ,.mcif2${client}_rd_rsp_valid(mcif2${client}_rd_rsp_valid)\n");
//: print(" ,.mcif2${client}_rd_rsp_ready(mcif2${client}_rd_rsp_ready)\n");
//: print(" ,.mcif2${client}_rd_rsp_pd(mcif2${client}_rd_rsp_pd)\n");
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mcif2cdma_dat_rd_rsp_valid(mcif2cdma_dat_rd_rsp_valid)
,.mcif2cdma_dat_rd_rsp_ready(mcif2cdma_dat_rd_rsp_ready)
,.mcif2cdma_dat_rd_rsp_pd(mcif2cdma_dat_rd_rsp_pd)
,.mcif2cdma_wt_rd_rsp_valid(mcif2cdma_wt_rd_rsp_valid)
,.mcif2cdma_wt_rd_rsp_ready(mcif2cdma_wt_rd_rsp_ready)
,.mcif2cdma_wt_rd_rsp_pd(mcif2cdma_wt_rd_rsp_pd)
,.mcif2sdp_rd_rsp_valid(mcif2sdp_rd_rsp_valid)
,.mcif2sdp_rd_rsp_ready(mcif2sdp_rd_rsp_ready)
,.mcif2sdp_rd_rsp_pd(mcif2sdp_rd_rsp_pd)
,.mcif2sdp_b_rd_rsp_valid(mcif2sdp_b_rd_rsp_valid)
,.mcif2sdp_b_rd_rsp_ready(mcif2sdp_b_rd_rsp_ready)
,.mcif2sdp_b_rd_rsp_pd(mcif2sdp_b_rd_rsp_pd)
,.mcif2sdp_n_rd_rsp_valid(mcif2sdp_n_rd_rsp_valid)
,.mcif2sdp_n_rd_rsp_ready(mcif2sdp_n_rd_rsp_ready)
,.mcif2sdp_n_rd_rsp_pd(mcif2sdp_n_rd_rsp_pd)
,.mcif2sdp_e_rd_rsp_valid(mcif2sdp_e_rd_rsp_valid)
,.mcif2sdp_e_rd_rsp_ready(mcif2sdp_e_rd_rsp_ready)
,.mcif2sdp_e_rd_rsp_pd(mcif2sdp_e_rd_rsp_pd)
,.mcif2pdp_rd_rsp_valid(mcif2pdp_rd_rsp_valid)
,.mcif2pdp_rd_rsp_ready(mcif2pdp_rd_rsp_ready)
,.mcif2pdp_rd_rsp_pd(mcif2pdp_rd_rsp_pd)
,.mcif2cdp_rd_rsp_valid(mcif2cdp_rd_rsp_valid)
,.mcif2cdp_rd_rsp_ready(mcif2cdp_rd_rsp_ready)
,.mcif2cdp_rd_rsp_pd(mcif2cdp_rd_rsp_pd)
,.mcif2bdma_rd_rsp_valid(mcif2bdma_rd_rsp_valid)
,.mcif2bdma_rd_rsp_ready(mcif2bdma_rd_rsp_ready)
,.mcif2bdma_rd_rsp_pd(mcif2bdma_rd_rsp_pd)
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i
,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o
,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid[7:0]) //|< i
,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i
,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata) //|< i
);
endmodule |
module NV_NVDLA_CVIF_WRITE_ig (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd
,reg2dp_wr_os_cnt
//: my @wdma_name = ("sdp", "pdp","cdp","rbk","bdma");
//: foreach my $client (@wdma_name) {
//: print" ,reg2dp_wr_weight_${client}\n";
//: }
//: foreach my $client (@wdma_name) {
//: print" ,${client}2mcif_wr_req_pd\n";
//: print" ,${client}2mcif_wr_req_valid\n";
//: print" ,${client}2mcif_wr_req_ready\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,reg2dp_wr_weight_sdp
,reg2dp_wr_weight_pdp
,reg2dp_wr_weight_cdp
,reg2dp_wr_weight_rbk
,reg2dp_wr_weight_bdma
,sdp2mcif_wr_req_pd
,sdp2mcif_wr_req_valid
,sdp2mcif_wr_req_ready
,pdp2mcif_wr_req_pd
,pdp2mcif_wr_req_valid
,pdp2mcif_wr_req_ready
,cdp2mcif_wr_req_pd
,cdp2mcif_wr_req_valid
,cdp2mcif_wr_req_ready
,bdma2mcif_wr_req_pd
,bdma2mcif_wr_req_valid
,bdma2mcif_wr_req_ready
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mcif2noc_axi_aw_awvalid
,mcif2noc_axi_aw_awready
,mcif2noc_axi_aw_awid
,mcif2noc_axi_aw_awlen
,mcif2noc_axi_aw_awaddr
,mcif2noc_axi_w_wvalid
,mcif2noc_axi_w_wready
,mcif2noc_axi_w_wdata
,mcif2noc_axi_w_wstrb
,mcif2noc_axi_w_wlast
,cq_wr_pvld
,cq_wr_prdy
,cq_wr_pd
,cq_wr_thread_id
,eg2ig_axi_len
,eg2ig_axi_vld
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input [7:0] reg2dp_wr_os_cnt;
input [2:0] eg2ig_axi_len;
input eg2ig_axi_vld;
output cq_wr_pvld;
input cq_wr_prdy;
output [2:0] cq_wr_thread_id;
output [3:0] cq_wr_pd;
output mcif2noc_axi_aw_awvalid;
input mcif2noc_axi_aw_awready;
output [7:0] mcif2noc_axi_aw_awid;
output [3:0] mcif2noc_axi_aw_awlen;
output [64 -1:0] mcif2noc_axi_aw_awaddr;
output mcif2noc_axi_w_wvalid;
input mcif2noc_axi_w_wready;
output [256 -1:0] mcif2noc_axi_w_wdata;
output [32 -1:0] mcif2noc_axi_w_wstrb;
output mcif2noc_axi_w_wlast;
//: my @wdma_name = ("sdp", "pdp","cdp","rbk","bdma");
//: foreach my $client (@wdma_name) {
//: print qq(
//: input ${client}2mcif_wr_req_valid;
//: output ${client}2mcif_wr_req_ready;
//: input [258 -1:0] ${client}2mcif_wr_req_pd;
//: );
//: }
//: foreach my $client (@wdma_name) {
//: print "input [7:0] reg2dp_wr_weight_${client};\n";
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input sdp2mcif_wr_req_valid;
output sdp2mcif_wr_req_ready;
input [258 -1:0] sdp2mcif_wr_req_pd;
input pdp2mcif_wr_req_valid;
output pdp2mcif_wr_req_ready;
input [258 -1:0] pdp2mcif_wr_req_pd;
input cdp2mcif_wr_req_valid;
output cdp2mcif_wr_req_ready;
input [258 -1:0] cdp2mcif_wr_req_pd;
input bdma2mcif_wr_req_valid;
output bdma2mcif_wr_req_ready;
input [258 -1:0] bdma2mcif_wr_req_pd;
input [7:0] reg2dp_wr_weight_sdp;
input [7:0] reg2dp_wr_weight_pdp;
input [7:0] reg2dp_wr_weight_cdp;
input [7:0] reg2dp_wr_weight_rbk;
input [7:0] reg2dp_wr_weight_bdma;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire arb2spt_cmd_ready;
wire arb2spt_cmd_valid;
wire [64 +13 -1:0] arb2spt_cmd_pd;
wire arb2spt_dat_ready;
wire arb2spt_dat_valid;
wire [258 -2:0] arb2spt_dat_pd;
wire spt2cvt_cmd_ready;
wire spt2cvt_cmd_valid;
wire [76:0] spt2cvt_cmd_pd;
wire spt2cvt_dat_ready;
wire spt2cvt_dat_valid;
wire [256:0] spt2cvt_dat_pd;
//: for (my $i=0;$i<5;$i++) {
//: print qq(
//: wire bpt2arb_cmd${i}_valid;
//: wire bpt2arb_cmd${i}_ready;
//: wire [64 +13 -1:0] bpt2arb_cmd${i}_pd;
//: wire bpt2arb_dat${i}_valid;
//: wire bpt2arb_dat${i}_ready;
//: wire [258 -2:0] bpt2arb_dat${i}_pd;
//: );
//: }
//: my $i = 0;
//: my @wdma_name = ("sdp", "pdp","cdp","rbk","bdma");
//: foreach my $client (@wdma_name) {
//: print "NV_NVDLA_MCIF_WRITE_IG_bpt u_bpt${i} ( \n";
//: print " .nvdla_core_clk (nvdla_core_clk)\n";
//: print " ,.nvdla_core_rstn (nvdla_core_rstn)\n";
//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd)\n";
//: print " ,.dma2bpt_req_valid (${client}2mcif_wr_req_valid)\n";
//: print " ,.dma2bpt_req_ready (${client}2mcif_wr_req_ready)\n";
//: print " ,.dma2bpt_req_pd (${client}2mcif_wr_req_pd)\n";
//: print " ,.bpt2arb_cmd_valid (bpt2arb_cmd${i}_valid)\n";
//: print " ,.bpt2arb_cmd_ready (bpt2arb_cmd${i}_ready)\n";
//: print " ,.bpt2arb_cmd_pd (bpt2arb_cmd${i}_pd)\n";
//: print " ,.bpt2arb_dat_valid (bpt2arb_dat${i}_valid)\n";
//: print " ,.bpt2arb_dat_ready (bpt2arb_dat${i}_ready)\n";
//: print " ,.bpt2arb_dat_pd (bpt2arb_dat${i}_pd)\n";
//: print " ,.axid (`tieoff_axid_${client})\n";
//: print ");\n";
//: $i++;
//:}
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire bpt2arb_cmd0_valid;
wire bpt2arb_cmd0_ready;
wire [64 +13 -1:0] bpt2arb_cmd0_pd;
wire bpt2arb_dat0_valid;
wire bpt2arb_dat0_ready;
wire [258 -2:0] bpt2arb_dat0_pd;
wire bpt2arb_cmd1_valid;
wire bpt2arb_cmd1_ready;
wire [64 +13 -1:0] bpt2arb_cmd1_pd;
wire bpt2arb_dat1_valid;
wire bpt2arb_dat1_ready;
wire [258 -2:0] bpt2arb_dat1_pd;
wire bpt2arb_cmd2_valid;
wire bpt2arb_cmd2_ready;
wire [64 +13 -1:0] bpt2arb_cmd2_pd;
wire bpt2arb_dat2_valid;
wire bpt2arb_dat2_ready;
wire [258 -2:0] bpt2arb_dat2_pd;
wire bpt2arb_cmd4_valid;
wire bpt2arb_cmd4_ready;
wire [64 +13 -1:0] bpt2arb_cmd4_pd;
wire bpt2arb_dat4_valid;
wire bpt2arb_dat4_ready;
wire [258 -2:0] bpt2arb_dat4_pd;
NV_NVDLA_CVIF_WRITE_IG_bpt u_bpt0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (sdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (sdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (sdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd0_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd0_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd0_pd)
,.bpt2arb_dat_valid (bpt2arb_dat0_valid)
,.bpt2arb_dat_ready (bpt2arb_dat0_ready)
,.bpt2arb_dat_pd (bpt2arb_dat0_pd)
,.axid (`tieoff_axid_sdp)
);
NV_NVDLA_CVIF_WRITE_IG_bpt u_bpt1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (pdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (pdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (pdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd1_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd1_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd1_pd)
,.bpt2arb_dat_valid (bpt2arb_dat1_valid)
,.bpt2arb_dat_ready (bpt2arb_dat1_ready)
,.bpt2arb_dat_pd (bpt2arb_dat1_pd)
,.axid (`tieoff_axid_pdp)
);
NV_NVDLA_CVIF_WRITE_IG_bpt u_bpt2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (cdp2mcif_wr_req_valid)
,.dma2bpt_req_ready (cdp2mcif_wr_req_ready)
,.dma2bpt_req_pd (cdp2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd2_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd2_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd2_pd)
,.bpt2arb_dat_valid (bpt2arb_dat2_valid)
,.bpt2arb_dat_ready (bpt2arb_dat2_ready)
,.bpt2arb_dat_pd (bpt2arb_dat2_pd)
,.axid (`tieoff_axid_cdp)
);
NV_NVDLA_CVIF_WRITE_IG_bpt u_bpt4 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.dma2bpt_req_valid (bdma2mcif_wr_req_valid)
,.dma2bpt_req_ready (bdma2mcif_wr_req_ready)
,.dma2bpt_req_pd (bdma2mcif_wr_req_pd)
,.bpt2arb_cmd_valid (bpt2arb_cmd4_valid)
,.bpt2arb_cmd_ready (bpt2arb_cmd4_ready)
,.bpt2arb_cmd_pd (bpt2arb_cmd4_pd)
,.bpt2arb_dat_valid (bpt2arb_dat4_valid)
,.bpt2arb_dat_ready (bpt2arb_dat4_ready)
,.bpt2arb_dat_pd (bpt2arb_dat4_pd)
,.axid (`tieoff_axid_bdma)
);
NV_NVDLA_CVIF_WRITE_IG_arb u_arb (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|<
//: for (my $i=0;$i<5;$i++) {
//: print " ,.bpt2arb_cmd${i}_valid (bpt2arb_cmd${i}_valid)\n";
//: print " ,.bpt2arb_cmd${i}_ready (bpt2arb_cmd${i}_ready)\n";
//: print " ,.bpt2arb_cmd${i}_pd (bpt2arb_cmd${i}_pd)\n";
//: print " ,.bpt2arb_dat${i}_valid (bpt2arb_dat${i}_valid)\n";
//: print " ,.bpt2arb_dat${i}_ready (bpt2arb_dat${i}_ready)\n";
//: print " ,.bpt2arb_dat${i}_pd (bpt2arb_dat${i}_pd)\n";
//: }
//: my $i=0;
//: my @wdma_name = ("sdp", "pdp","cdp","rbk","bdma");
//: foreach my $client (@wdma_name) {
//: print " ,.reg2dp_wr_weight${i} (reg2dp_wr_weight_${client}[7:0])\n";
//: $i++;
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.bpt2arb_cmd0_valid (bpt2arb_cmd0_valid)
,.bpt2arb_cmd0_ready (bpt2arb_cmd0_ready)
,.bpt2arb_cmd0_pd (bpt2arb_cmd0_pd)
,.bpt2arb_dat0_valid (bpt2arb_dat0_valid)
,.bpt2arb_dat0_ready (bpt2arb_dat0_ready)
,.bpt2arb_dat0_pd (bpt2arb_dat0_pd)
,.bpt2arb_cmd1_valid (bpt2arb_cmd1_valid)
,.bpt2arb_cmd1_ready (bpt2arb_cmd1_ready)
,.bpt2arb_cmd1_pd (bpt2arb_cmd1_pd)
,.bpt2arb_dat1_valid (bpt2arb_dat1_valid)
,.bpt2arb_dat1_ready (bpt2arb_dat1_ready)
,.bpt2arb_dat1_pd (bpt2arb_dat1_pd)
,.bpt2arb_cmd2_valid (bpt2arb_cmd2_valid)
,.bpt2arb_cmd2_ready (bpt2arb_cmd2_ready)
,.bpt2arb_cmd2_pd (bpt2arb_cmd2_pd)
,.bpt2arb_dat2_valid (bpt2arb_dat2_valid)
,.bpt2arb_dat2_ready (bpt2arb_dat2_ready)
,.bpt2arb_dat2_pd (bpt2arb_dat2_pd)
,.bpt2arb_cmd4_valid (bpt2arb_cmd4_valid)
,.bpt2arb_cmd4_ready (bpt2arb_cmd4_ready)
,.bpt2arb_cmd4_pd (bpt2arb_cmd4_pd)
,.bpt2arb_dat4_valid (bpt2arb_dat4_valid)
,.bpt2arb_dat4_ready (bpt2arb_dat4_ready)
,.bpt2arb_dat4_pd (bpt2arb_dat4_pd)
,.reg2dp_wr_weight0 (reg2dp_wr_weight_sdp[7:0])
,.reg2dp_wr_weight1 (reg2dp_wr_weight_pdp[7:0])
,.reg2dp_wr_weight2 (reg2dp_wr_weight_cdp[7:0])
,.reg2dp_wr_weight4 (reg2dp_wr_weight_bdma[7:0])
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|> w
,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|< w
,.arb2spt_cmd_pd (arb2spt_cmd_pd)
,.arb2spt_dat_valid (arb2spt_dat_valid) //|> w
,.arb2spt_dat_ready (arb2spt_dat_ready) //|< w
,.arb2spt_dat_pd (arb2spt_dat_pd)
);
NV_NVDLA_CVIF_WRITE_IG_spt u_spt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< w
,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> w
,.arb2spt_cmd_pd (arb2spt_cmd_pd)
,.arb2spt_dat_valid (arb2spt_dat_valid) //|< w
,.arb2spt_dat_ready (arb2spt_dat_ready) //|> w
,.arb2spt_dat_pd (arb2spt_dat_pd)
,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|> w
,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|< w
,.spt2cvt_cmd_pd (spt2cvt_cmd_pd)
,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|> w
,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|< w
,.spt2cvt_dat_pd (spt2cvt_dat_pd)
);
NV_NVDLA_CVIF_WRITE_IG_cvt u_cvt (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|< i
,.cq_wr_pvld (cq_wr_pvld) //|> o
,.cq_wr_prdy (cq_wr_prdy) //|< i
,.cq_wr_pd (cq_wr_pd[3:0]) //|> o
,.cq_wr_thread_id (cq_wr_thread_id[2:0]) //|> o
,.eg2ig_axi_len (eg2ig_axi_len[2:0]) //|< i
,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i
,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|< w
,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|> w
,.spt2cvt_cmd_pd (spt2cvt_cmd_pd)
,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|< w
,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|> w
,.spt2cvt_dat_pd (spt2cvt_dat_pd)
,.cvif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o
,.cvif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i
,.cvif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o
,.cvif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o
,.cvif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr)
,.cvif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o
,.cvif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i
,.cvif2noc_axi_w_wdata (mcif2noc_axi_w_wdata)
,.cvif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb)
,.cvif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o
);
endmodule // NV_NVDLA_CVIF_WRITE_ig |
module NV_NVDLA_SDP_RDMA_eg (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,op_load //|< i
,eg_done //|> o
,cq2eg_pd //|< i
,cq2eg_pvld //|< i
,cq2eg_prdy //|> o
,lat_fifo_rd_pd //|< i
,lat_fifo_rd_pvld //|< i
,lat_fifo_rd_prdy //|> o
,dma_rd_cdt_lat_fifo_pop //|> o
,sdp_rdma2dp_alu_pd //|> o
,sdp_rdma2dp_alu_valid //|> o
,sdp_rdma2dp_alu_ready //|< i
,sdp_rdma2dp_mul_pd //|> o
,sdp_rdma2dp_mul_valid //|> o
,sdp_rdma2dp_mul_ready //|< i
,reg2dp_batch_number //|< i
,reg2dp_channel //|< i
,reg2dp_height //|< i
,reg2dp_width //|< i
,reg2dp_proc_precision //|< i
,reg2dp_out_precision //|< i
,reg2dp_rdma_data_mode //|< i
,reg2dp_rdma_data_size //|< i
,reg2dp_rdma_data_use //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input op_load;
output eg_done;
input [15:0] cq2eg_pd;
input cq2eg_pvld;
output cq2eg_prdy;
input [257 -1:0] lat_fifo_rd_pd;
input lat_fifo_rd_pvld;
output lat_fifo_rd_prdy;
output dma_rd_cdt_lat_fifo_pop;
output [32*16:0] sdp_rdma2dp_alu_pd;
output sdp_rdma2dp_alu_valid;
input sdp_rdma2dp_alu_ready;
output [32*16:0] sdp_rdma2dp_mul_pd;
output sdp_rdma2dp_mul_valid;
input sdp_rdma2dp_mul_ready;
input [4:0] reg2dp_batch_number;
input [12:0] reg2dp_channel;
input [12:0] reg2dp_height;
input [12:0] reg2dp_width;
input [1:0] reg2dp_proc_precision;
input [1:0] reg2dp_out_precision;
input reg2dp_rdma_data_mode;
input reg2dp_rdma_data_size;
input [1:0] reg2dp_rdma_data_use;
wire cfg_alu_en;
wire cfg_mul_en;
wire cfg_do_8;
wire cfg_dp_8;
wire cfg_data_size_1byte;
wire cfg_data_size_2byte;
wire cfg_mode_1bytex1;
wire cfg_mode_1bytex2;
wire cfg_mode_2bytex1;
wire cfg_mode_2bytex2;
wire cfg_mode_alu_only;
wire cfg_mode_both;
wire cfg_mode_mul_only;
wire cfg_mode_per_element;
wire cfg_mode_single;
reg cq2eg_prdy_hold;
wire ig2eg_cube_end;
wire [14:0] ig2eg_size;
wire [15:0] beat_size;
reg [14:0] beat_count;
wire [15:0] beat_count_nxt;
reg mon_beat_count;
wire is_last_beat;
wire is_beat_end;
wire layer_done;
wire mul_layer_end;
wire mul_roc_rdy;
wire mul_roc_vld;
wire mul_rod_rdy;
wire mul_rod_vld;
reg alu_layer_done;
reg alu_roc_en;
reg eg_done;
reg mul_layer_done;
reg mul_roc_en;
wire alu_layer_end;
wire alu_roc_rdy;
wire alu_roc_vld;
wire alu_rod_rdy;
wire alu_rod_vld;
wire [4*32*8 +3:0] unpack_out_pd;
wire unpack_out_pvld;
wire unpack_out_prdy;
wire [32*8 -1:0] mode_1bytex2_alu_rod0_pd;
wire [32*8 -1:0] mode_1bytex2_alu_rod1_pd;
wire [32*8 -1:0] mode_2bytex2_alu_rod0_pd;
wire [32*8 -1:0] mode_2bytex2_alu_rod1_pd;
wire [32*8 -1:0] mode_1bytex2_mul_rod0_pd;
wire [32*8 -1:0] mode_1bytex2_mul_rod1_pd;
wire [32*8 -1:0] mode_2bytex2_mul_rod0_pd;
wire [32*8 -1:0] mode_2bytex2_mul_rod1_pd;
//==============
// CFG REG
//==============
assign cfg_data_size_1byte = reg2dp_rdma_data_size == 1'h0 ;
assign cfg_data_size_2byte = reg2dp_rdma_data_size == 1'h1 ;
assign cfg_mode_mul_only = reg2dp_rdma_data_use == 2'h0 ;
assign cfg_mode_alu_only = reg2dp_rdma_data_use == 2'h1 ;
assign cfg_mode_both = reg2dp_rdma_data_use == 2'h2 ;
assign cfg_mode_per_element = reg2dp_rdma_data_mode == 1'h1 ;
assign cfg_mode_single = cfg_mode_mul_only || cfg_mode_alu_only;
assign cfg_mode_1bytex1 = cfg_data_size_1byte & cfg_mode_single;
assign cfg_mode_2bytex1 = cfg_data_size_2byte & cfg_mode_single;
assign cfg_mode_1bytex2 = cfg_data_size_1byte & cfg_mode_both;
assign cfg_mode_2bytex2 = cfg_data_size_2byte & cfg_mode_both;
wire cfg_mode_multi_batch = reg2dp_batch_number!=0;
assign cfg_dp_8 = reg2dp_proc_precision== 0 ;
assign cfg_do_8 = reg2dp_out_precision== 0 ;
assign cfg_alu_en = cfg_mode_alu_only || cfg_mode_both;
assign cfg_mul_en = cfg_mode_mul_only || cfg_mode_both;
//==============
// DMA Interface
//==============
assign dma_rd_cdt_lat_fifo_pop = lat_fifo_rd_pvld & lat_fifo_rd_prdy;
//==============
// Latency FIFO to buffer return DATA
//==============
wire [3:0] lat_fifo_rd_mask = {{(4-1){1'b0}},lat_fifo_rd_pd[257 -1:256]};
wire [2:0] lat_fifo_rd_size = lat_fifo_rd_mask[3]+lat_fifo_rd_mask[2]+lat_fifo_rd_mask[1]+lat_fifo_rd_mask[0];
//==================================================================
// Context Queue: read
//==================================================================
assign cq2eg_prdy = is_beat_end;
assign ig2eg_size[14:0] = cq2eg_pd[14:0];
assign ig2eg_cube_end = cq2eg_pd[15];
assign beat_size = ig2eg_size+1;
assign beat_count_nxt = beat_count+lat_fifo_rd_size;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
{mon_beat_count,beat_count} <= 16'h0;
end else begin
if (lat_fifo_rd_pvld & lat_fifo_rd_prdy) begin
if (is_last_beat) begin
{mon_beat_count,beat_count} <= 16'h0;
end else begin
{mon_beat_count,beat_count} <= beat_count_nxt;
end
end
end
end
assign is_last_beat = (beat_count_nxt == beat_size);
assign is_beat_end = is_last_beat & lat_fifo_rd_pvld & lat_fifo_rd_prdy;
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass disable_block NoWidthInBasedNum-ML
// spyglass disable_block STARC-2.10.3.2a
// spyglass disable_block STARC05-2.1.3.1
// spyglass disable_block STARC-2.1.4.6
// spyglass disable_block W116
// spyglass disable_block W154
// spyglass disable_block W239
// spyglass disable_block W362
// spyglass disable_block WRN_58
// spyglass disable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif // ASSERT_OFF_RESET_IS_X
`endif // SYNTHESIS
`endif // FV_ASSERT_ON
// VCS coverage off
nv_assert_never #(0,0,"info in CQ there be there when return data come") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (!cq2eg_pvld) & lat_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML
// VCS coverage on
`undef ASSERT_RESET
`endif // ASSERT_ON
`ifdef SPYGLASS_ASSERT_ON
`else
// spyglass enable_block NoWidthInBasedNum-ML
// spyglass enable_block STARC-2.10.3.2a
// spyglass enable_block STARC05-2.1.3.1
// spyglass enable_block STARC-2.1.4.6
// spyglass enable_block W116
// spyglass enable_block W154
// spyglass enable_block W239
// spyglass enable_block W362
// spyglass enable_block WRN_58
// spyglass enable_block WRN_61
`endif // SPYGLASS_ASSERT_ON
/////////combine lat fifo pd to 4*atomic_m*bpe//////
wire lat_fifo_rd_beat_end = is_last_beat;
NV_NVDLA_SDP_RDMA_unpack u_rdma_unpack (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.inp_data (lat_fifo_rd_pd[257 -1:0])
,.inp_pvld (lat_fifo_rd_pvld)
,.inp_prdy (lat_fifo_rd_prdy)
,.inp_end (lat_fifo_rd_beat_end)
,.out_data (unpack_out_pd[4*32*8 +3:0])
,.out_pvld (unpack_out_pvld)
,.out_prdy (unpack_out_prdy)
);
wire [3:0] unpack_out_mask = unpack_out_pd[4*32*8 +3:4*32*8];
assign unpack_out_prdy = cfg_mode_both ? alu_rod_rdy & mul_rod_rdy : cfg_mode_alu_only ? alu_rod_rdy : mul_rod_rdy;
//============================================================
// Re-Order FIFO to send data to SDP-core
//============================================================
// |----------------------------------------------------|
// | 16B | 16B | 16B | 16B |
// MODE |----------------------------------------------------|
// | 0 1 2 3 |
// 1Bx1 | ALU or MUL | ALU or MUL | ALU or MUL or ALU or MUL |
// |----------------------------------------------------|
// | 0 | 1 |
// 2Bx1 | ALU or MUL | ALU or MUL |
// |====================================================|
// | 0 | 1 |
// 1Bx2 | ALU | MUL | ALU | MUL |
// |----------------------------------------------------|
// | 0 | 1 |
// 2Bx2 | ALU | MUL |
// |----------------------------------------------------|
//============================================================
//: my $k = 32;
//: foreach my $i (0..${k}-1) {
//: my $j = ${i}*2;
//: print "assign mode_1bytex2_alu_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: my $jj = ${i}*2+$k*2;
//: print "assign mode_1bytex2_alu_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}/2-1) {
//: my $j = ${i}*2;
//: print "assign mode_2bytex2_alu_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}/2-1) {
//: my $jj = ${i}*2+$k;
//: print "assign mode_2bytex2_alu_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: my $j = ${i}*2+1;
//: print "assign mode_1bytex2_mul_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: my $jj = ${i}*2+1+$k*2;
//: print "assign mode_1bytex2_mul_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}/2-1) {
//: my $j = ${i}*2+1;
//: print "assign mode_2bytex2_mul_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}/2-1) {
//: my $jj = ${i}*2+1+$k;
//: print "assign mode_2bytex2_mul_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n";
//: }
//: print "\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign mode_1bytex2_alu_rod0_pd[8*0+7:8*0] = unpack_out_pd[8*0+7: 8*0];
assign mode_1bytex2_alu_rod0_pd[8*1+7:8*1] = unpack_out_pd[8*2+7: 8*2];
assign mode_1bytex2_alu_rod0_pd[8*2+7:8*2] = unpack_out_pd[8*4+7: 8*4];
assign mode_1bytex2_alu_rod0_pd[8*3+7:8*3] = unpack_out_pd[8*6+7: 8*6];
assign mode_1bytex2_alu_rod0_pd[8*4+7:8*4] = unpack_out_pd[8*8+7: 8*8];
assign mode_1bytex2_alu_rod0_pd[8*5+7:8*5] = unpack_out_pd[8*10+7: 8*10];
assign mode_1bytex2_alu_rod0_pd[8*6+7:8*6] = unpack_out_pd[8*12+7: 8*12];
assign mode_1bytex2_alu_rod0_pd[8*7+7:8*7] = unpack_out_pd[8*14+7: 8*14];
assign mode_1bytex2_alu_rod0_pd[8*8+7:8*8] = unpack_out_pd[8*16+7: 8*16];
assign mode_1bytex2_alu_rod0_pd[8*9+7:8*9] = unpack_out_pd[8*18+7: 8*18];
assign mode_1bytex2_alu_rod0_pd[8*10+7:8*10] = unpack_out_pd[8*20+7: 8*20];
assign mode_1bytex2_alu_rod0_pd[8*11+7:8*11] = unpack_out_pd[8*22+7: 8*22];
assign mode_1bytex2_alu_rod0_pd[8*12+7:8*12] = unpack_out_pd[8*24+7: 8*24];
assign mode_1bytex2_alu_rod0_pd[8*13+7:8*13] = unpack_out_pd[8*26+7: 8*26];
assign mode_1bytex2_alu_rod0_pd[8*14+7:8*14] = unpack_out_pd[8*28+7: 8*28];
assign mode_1bytex2_alu_rod0_pd[8*15+7:8*15] = unpack_out_pd[8*30+7: 8*30];
assign mode_1bytex2_alu_rod0_pd[8*16+7:8*16] = unpack_out_pd[8*32+7: 8*32];
assign mode_1bytex2_alu_rod0_pd[8*17+7:8*17] = unpack_out_pd[8*34+7: 8*34];
assign mode_1bytex2_alu_rod0_pd[8*18+7:8*18] = unpack_out_pd[8*36+7: 8*36];
assign mode_1bytex2_alu_rod0_pd[8*19+7:8*19] = unpack_out_pd[8*38+7: 8*38];
assign mode_1bytex2_alu_rod0_pd[8*20+7:8*20] = unpack_out_pd[8*40+7: 8*40];
assign mode_1bytex2_alu_rod0_pd[8*21+7:8*21] = unpack_out_pd[8*42+7: 8*42];
assign mode_1bytex2_alu_rod0_pd[8*22+7:8*22] = unpack_out_pd[8*44+7: 8*44];
assign mode_1bytex2_alu_rod0_pd[8*23+7:8*23] = unpack_out_pd[8*46+7: 8*46];
assign mode_1bytex2_alu_rod0_pd[8*24+7:8*24] = unpack_out_pd[8*48+7: 8*48];
assign mode_1bytex2_alu_rod0_pd[8*25+7:8*25] = unpack_out_pd[8*50+7: 8*50];
assign mode_1bytex2_alu_rod0_pd[8*26+7:8*26] = unpack_out_pd[8*52+7: 8*52];
assign mode_1bytex2_alu_rod0_pd[8*27+7:8*27] = unpack_out_pd[8*54+7: 8*54];
assign mode_1bytex2_alu_rod0_pd[8*28+7:8*28] = unpack_out_pd[8*56+7: 8*56];
assign mode_1bytex2_alu_rod0_pd[8*29+7:8*29] = unpack_out_pd[8*58+7: 8*58];
assign mode_1bytex2_alu_rod0_pd[8*30+7:8*30] = unpack_out_pd[8*60+7: 8*60];
assign mode_1bytex2_alu_rod0_pd[8*31+7:8*31] = unpack_out_pd[8*62+7: 8*62];
assign mode_1bytex2_alu_rod1_pd[8*0+7:8*0] = unpack_out_pd[8*64+7: 8*64];
assign mode_1bytex2_alu_rod1_pd[8*1+7:8*1] = unpack_out_pd[8*66+7: 8*66];
assign mode_1bytex2_alu_rod1_pd[8*2+7:8*2] = unpack_out_pd[8*68+7: 8*68];
assign mode_1bytex2_alu_rod1_pd[8*3+7:8*3] = unpack_out_pd[8*70+7: 8*70];
assign mode_1bytex2_alu_rod1_pd[8*4+7:8*4] = unpack_out_pd[8*72+7: 8*72];
assign mode_1bytex2_alu_rod1_pd[8*5+7:8*5] = unpack_out_pd[8*74+7: 8*74];
assign mode_1bytex2_alu_rod1_pd[8*6+7:8*6] = unpack_out_pd[8*76+7: 8*76];
assign mode_1bytex2_alu_rod1_pd[8*7+7:8*7] = unpack_out_pd[8*78+7: 8*78];
assign mode_1bytex2_alu_rod1_pd[8*8+7:8*8] = unpack_out_pd[8*80+7: 8*80];
assign mode_1bytex2_alu_rod1_pd[8*9+7:8*9] = unpack_out_pd[8*82+7: 8*82];
assign mode_1bytex2_alu_rod1_pd[8*10+7:8*10] = unpack_out_pd[8*84+7: 8*84];
assign mode_1bytex2_alu_rod1_pd[8*11+7:8*11] = unpack_out_pd[8*86+7: 8*86];
assign mode_1bytex2_alu_rod1_pd[8*12+7:8*12] = unpack_out_pd[8*88+7: 8*88];
assign mode_1bytex2_alu_rod1_pd[8*13+7:8*13] = unpack_out_pd[8*90+7: 8*90];
assign mode_1bytex2_alu_rod1_pd[8*14+7:8*14] = unpack_out_pd[8*92+7: 8*92];
assign mode_1bytex2_alu_rod1_pd[8*15+7:8*15] = unpack_out_pd[8*94+7: 8*94];
assign mode_1bytex2_alu_rod1_pd[8*16+7:8*16] = unpack_out_pd[8*96+7: 8*96];
assign mode_1bytex2_alu_rod1_pd[8*17+7:8*17] = unpack_out_pd[8*98+7: 8*98];
assign mode_1bytex2_alu_rod1_pd[8*18+7:8*18] = unpack_out_pd[8*100+7: 8*100];
assign mode_1bytex2_alu_rod1_pd[8*19+7:8*19] = unpack_out_pd[8*102+7: 8*102];
assign mode_1bytex2_alu_rod1_pd[8*20+7:8*20] = unpack_out_pd[8*104+7: 8*104];
assign mode_1bytex2_alu_rod1_pd[8*21+7:8*21] = unpack_out_pd[8*106+7: 8*106];
assign mode_1bytex2_alu_rod1_pd[8*22+7:8*22] = unpack_out_pd[8*108+7: 8*108];
assign mode_1bytex2_alu_rod1_pd[8*23+7:8*23] = unpack_out_pd[8*110+7: 8*110];
assign mode_1bytex2_alu_rod1_pd[8*24+7:8*24] = unpack_out_pd[8*112+7: 8*112];
assign mode_1bytex2_alu_rod1_pd[8*25+7:8*25] = unpack_out_pd[8*114+7: 8*114];
assign mode_1bytex2_alu_rod1_pd[8*26+7:8*26] = unpack_out_pd[8*116+7: 8*116];
assign mode_1bytex2_alu_rod1_pd[8*27+7:8*27] = unpack_out_pd[8*118+7: 8*118];
assign mode_1bytex2_alu_rod1_pd[8*28+7:8*28] = unpack_out_pd[8*120+7: 8*120];
assign mode_1bytex2_alu_rod1_pd[8*29+7:8*29] = unpack_out_pd[8*122+7: 8*122];
assign mode_1bytex2_alu_rod1_pd[8*30+7:8*30] = unpack_out_pd[8*124+7: 8*124];
assign mode_1bytex2_alu_rod1_pd[8*31+7:8*31] = unpack_out_pd[8*126+7: 8*126];
assign mode_2bytex2_alu_rod0_pd[16*0+15:16*0] = unpack_out_pd[16*0+15: 16*0];
assign mode_2bytex2_alu_rod0_pd[16*1+15:16*1] = unpack_out_pd[16*2+15: 16*2];
assign mode_2bytex2_alu_rod0_pd[16*2+15:16*2] = unpack_out_pd[16*4+15: 16*4];
assign mode_2bytex2_alu_rod0_pd[16*3+15:16*3] = unpack_out_pd[16*6+15: 16*6];
assign mode_2bytex2_alu_rod0_pd[16*4+15:16*4] = unpack_out_pd[16*8+15: 16*8];
assign mode_2bytex2_alu_rod0_pd[16*5+15:16*5] = unpack_out_pd[16*10+15: 16*10];
assign mode_2bytex2_alu_rod0_pd[16*6+15:16*6] = unpack_out_pd[16*12+15: 16*12];
assign mode_2bytex2_alu_rod0_pd[16*7+15:16*7] = unpack_out_pd[16*14+15: 16*14];
assign mode_2bytex2_alu_rod0_pd[16*8+15:16*8] = unpack_out_pd[16*16+15: 16*16];
assign mode_2bytex2_alu_rod0_pd[16*9+15:16*9] = unpack_out_pd[16*18+15: 16*18];
assign mode_2bytex2_alu_rod0_pd[16*10+15:16*10] = unpack_out_pd[16*20+15: 16*20];
assign mode_2bytex2_alu_rod0_pd[16*11+15:16*11] = unpack_out_pd[16*22+15: 16*22];
assign mode_2bytex2_alu_rod0_pd[16*12+15:16*12] = unpack_out_pd[16*24+15: 16*24];
assign mode_2bytex2_alu_rod0_pd[16*13+15:16*13] = unpack_out_pd[16*26+15: 16*26];
assign mode_2bytex2_alu_rod0_pd[16*14+15:16*14] = unpack_out_pd[16*28+15: 16*28];
assign mode_2bytex2_alu_rod0_pd[16*15+15:16*15] = unpack_out_pd[16*30+15: 16*30];
assign mode_2bytex2_alu_rod1_pd[16*0+15:16*0] = unpack_out_pd[16*32+15: 16*32];
assign mode_2bytex2_alu_rod1_pd[16*1+15:16*1] = unpack_out_pd[16*34+15: 16*34];
assign mode_2bytex2_alu_rod1_pd[16*2+15:16*2] = unpack_out_pd[16*36+15: 16*36];
assign mode_2bytex2_alu_rod1_pd[16*3+15:16*3] = unpack_out_pd[16*38+15: 16*38];
assign mode_2bytex2_alu_rod1_pd[16*4+15:16*4] = unpack_out_pd[16*40+15: 16*40];
assign mode_2bytex2_alu_rod1_pd[16*5+15:16*5] = unpack_out_pd[16*42+15: 16*42];
assign mode_2bytex2_alu_rod1_pd[16*6+15:16*6] = unpack_out_pd[16*44+15: 16*44];
assign mode_2bytex2_alu_rod1_pd[16*7+15:16*7] = unpack_out_pd[16*46+15: 16*46];
assign mode_2bytex2_alu_rod1_pd[16*8+15:16*8] = unpack_out_pd[16*48+15: 16*48];
assign mode_2bytex2_alu_rod1_pd[16*9+15:16*9] = unpack_out_pd[16*50+15: 16*50];
assign mode_2bytex2_alu_rod1_pd[16*10+15:16*10] = unpack_out_pd[16*52+15: 16*52];
assign mode_2bytex2_alu_rod1_pd[16*11+15:16*11] = unpack_out_pd[16*54+15: 16*54];
assign mode_2bytex2_alu_rod1_pd[16*12+15:16*12] = unpack_out_pd[16*56+15: 16*56];
assign mode_2bytex2_alu_rod1_pd[16*13+15:16*13] = unpack_out_pd[16*58+15: 16*58];
assign mode_2bytex2_alu_rod1_pd[16*14+15:16*14] = unpack_out_pd[16*60+15: 16*60];
assign mode_2bytex2_alu_rod1_pd[16*15+15:16*15] = unpack_out_pd[16*62+15: 16*62];
assign mode_1bytex2_mul_rod0_pd[8*0+7:8*0] = unpack_out_pd[8*1+7: 8*1];
assign mode_1bytex2_mul_rod0_pd[8*1+7:8*1] = unpack_out_pd[8*3+7: 8*3];
assign mode_1bytex2_mul_rod0_pd[8*2+7:8*2] = unpack_out_pd[8*5+7: 8*5];
assign mode_1bytex2_mul_rod0_pd[8*3+7:8*3] = unpack_out_pd[8*7+7: 8*7];
assign mode_1bytex2_mul_rod0_pd[8*4+7:8*4] = unpack_out_pd[8*9+7: 8*9];
assign mode_1bytex2_mul_rod0_pd[8*5+7:8*5] = unpack_out_pd[8*11+7: 8*11];
assign mode_1bytex2_mul_rod0_pd[8*6+7:8*6] = unpack_out_pd[8*13+7: 8*13];
assign mode_1bytex2_mul_rod0_pd[8*7+7:8*7] = unpack_out_pd[8*15+7: 8*15];
assign mode_1bytex2_mul_rod0_pd[8*8+7:8*8] = unpack_out_pd[8*17+7: 8*17];
assign mode_1bytex2_mul_rod0_pd[8*9+7:8*9] = unpack_out_pd[8*19+7: 8*19];
assign mode_1bytex2_mul_rod0_pd[8*10+7:8*10] = unpack_out_pd[8*21+7: 8*21];
assign mode_1bytex2_mul_rod0_pd[8*11+7:8*11] = unpack_out_pd[8*23+7: 8*23];
assign mode_1bytex2_mul_rod0_pd[8*12+7:8*12] = unpack_out_pd[8*25+7: 8*25];
assign mode_1bytex2_mul_rod0_pd[8*13+7:8*13] = unpack_out_pd[8*27+7: 8*27];
assign mode_1bytex2_mul_rod0_pd[8*14+7:8*14] = unpack_out_pd[8*29+7: 8*29];
assign mode_1bytex2_mul_rod0_pd[8*15+7:8*15] = unpack_out_pd[8*31+7: 8*31];
assign mode_1bytex2_mul_rod0_pd[8*16+7:8*16] = unpack_out_pd[8*33+7: 8*33];
assign mode_1bytex2_mul_rod0_pd[8*17+7:8*17] = unpack_out_pd[8*35+7: 8*35];
assign mode_1bytex2_mul_rod0_pd[8*18+7:8*18] = unpack_out_pd[8*37+7: 8*37];
assign mode_1bytex2_mul_rod0_pd[8*19+7:8*19] = unpack_out_pd[8*39+7: 8*39];
assign mode_1bytex2_mul_rod0_pd[8*20+7:8*20] = unpack_out_pd[8*41+7: 8*41];
assign mode_1bytex2_mul_rod0_pd[8*21+7:8*21] = unpack_out_pd[8*43+7: 8*43];
assign mode_1bytex2_mul_rod0_pd[8*22+7:8*22] = unpack_out_pd[8*45+7: 8*45];
assign mode_1bytex2_mul_rod0_pd[8*23+7:8*23] = unpack_out_pd[8*47+7: 8*47];
assign mode_1bytex2_mul_rod0_pd[8*24+7:8*24] = unpack_out_pd[8*49+7: 8*49];
assign mode_1bytex2_mul_rod0_pd[8*25+7:8*25] = unpack_out_pd[8*51+7: 8*51];
assign mode_1bytex2_mul_rod0_pd[8*26+7:8*26] = unpack_out_pd[8*53+7: 8*53];
assign mode_1bytex2_mul_rod0_pd[8*27+7:8*27] = unpack_out_pd[8*55+7: 8*55];
assign mode_1bytex2_mul_rod0_pd[8*28+7:8*28] = unpack_out_pd[8*57+7: 8*57];
assign mode_1bytex2_mul_rod0_pd[8*29+7:8*29] = unpack_out_pd[8*59+7: 8*59];
assign mode_1bytex2_mul_rod0_pd[8*30+7:8*30] = unpack_out_pd[8*61+7: 8*61];
assign mode_1bytex2_mul_rod0_pd[8*31+7:8*31] = unpack_out_pd[8*63+7: 8*63];
assign mode_1bytex2_mul_rod1_pd[8*0+7:8*0] = unpack_out_pd[8*65+7: 8*65];
assign mode_1bytex2_mul_rod1_pd[8*1+7:8*1] = unpack_out_pd[8*67+7: 8*67];
assign mode_1bytex2_mul_rod1_pd[8*2+7:8*2] = unpack_out_pd[8*69+7: 8*69];
assign mode_1bytex2_mul_rod1_pd[8*3+7:8*3] = unpack_out_pd[8*71+7: 8*71];
assign mode_1bytex2_mul_rod1_pd[8*4+7:8*4] = unpack_out_pd[8*73+7: 8*73];
assign mode_1bytex2_mul_rod1_pd[8*5+7:8*5] = unpack_out_pd[8*75+7: 8*75];
assign mode_1bytex2_mul_rod1_pd[8*6+7:8*6] = unpack_out_pd[8*77+7: 8*77];
assign mode_1bytex2_mul_rod1_pd[8*7+7:8*7] = unpack_out_pd[8*79+7: 8*79];
assign mode_1bytex2_mul_rod1_pd[8*8+7:8*8] = unpack_out_pd[8*81+7: 8*81];
assign mode_1bytex2_mul_rod1_pd[8*9+7:8*9] = unpack_out_pd[8*83+7: 8*83];
assign mode_1bytex2_mul_rod1_pd[8*10+7:8*10] = unpack_out_pd[8*85+7: 8*85];
assign mode_1bytex2_mul_rod1_pd[8*11+7:8*11] = unpack_out_pd[8*87+7: 8*87];
assign mode_1bytex2_mul_rod1_pd[8*12+7:8*12] = unpack_out_pd[8*89+7: 8*89];
assign mode_1bytex2_mul_rod1_pd[8*13+7:8*13] = unpack_out_pd[8*91+7: 8*91];
assign mode_1bytex2_mul_rod1_pd[8*14+7:8*14] = unpack_out_pd[8*93+7: 8*93];
assign mode_1bytex2_mul_rod1_pd[8*15+7:8*15] = unpack_out_pd[8*95+7: 8*95];
assign mode_1bytex2_mul_rod1_pd[8*16+7:8*16] = unpack_out_pd[8*97+7: 8*97];
assign mode_1bytex2_mul_rod1_pd[8*17+7:8*17] = unpack_out_pd[8*99+7: 8*99];
assign mode_1bytex2_mul_rod1_pd[8*18+7:8*18] = unpack_out_pd[8*101+7: 8*101];
assign mode_1bytex2_mul_rod1_pd[8*19+7:8*19] = unpack_out_pd[8*103+7: 8*103];
assign mode_1bytex2_mul_rod1_pd[8*20+7:8*20] = unpack_out_pd[8*105+7: 8*105];
assign mode_1bytex2_mul_rod1_pd[8*21+7:8*21] = unpack_out_pd[8*107+7: 8*107];
assign mode_1bytex2_mul_rod1_pd[8*22+7:8*22] = unpack_out_pd[8*109+7: 8*109];
assign mode_1bytex2_mul_rod1_pd[8*23+7:8*23] = unpack_out_pd[8*111+7: 8*111];
assign mode_1bytex2_mul_rod1_pd[8*24+7:8*24] = unpack_out_pd[8*113+7: 8*113];
assign mode_1bytex2_mul_rod1_pd[8*25+7:8*25] = unpack_out_pd[8*115+7: 8*115];
assign mode_1bytex2_mul_rod1_pd[8*26+7:8*26] = unpack_out_pd[8*117+7: 8*117];
assign mode_1bytex2_mul_rod1_pd[8*27+7:8*27] = unpack_out_pd[8*119+7: 8*119];
assign mode_1bytex2_mul_rod1_pd[8*28+7:8*28] = unpack_out_pd[8*121+7: 8*121];
assign mode_1bytex2_mul_rod1_pd[8*29+7:8*29] = unpack_out_pd[8*123+7: 8*123];
assign mode_1bytex2_mul_rod1_pd[8*30+7:8*30] = unpack_out_pd[8*125+7: 8*125];
assign mode_1bytex2_mul_rod1_pd[8*31+7:8*31] = unpack_out_pd[8*127+7: 8*127];
assign mode_2bytex2_mul_rod0_pd[16*0+15:16*0] = unpack_out_pd[16*1+15: 16*1];
assign mode_2bytex2_mul_rod0_pd[16*1+15:16*1] = unpack_out_pd[16*3+15: 16*3];
assign mode_2bytex2_mul_rod0_pd[16*2+15:16*2] = unpack_out_pd[16*5+15: 16*5];
assign mode_2bytex2_mul_rod0_pd[16*3+15:16*3] = unpack_out_pd[16*7+15: 16*7];
assign mode_2bytex2_mul_rod0_pd[16*4+15:16*4] = unpack_out_pd[16*9+15: 16*9];
assign mode_2bytex2_mul_rod0_pd[16*5+15:16*5] = unpack_out_pd[16*11+15: 16*11];
assign mode_2bytex2_mul_rod0_pd[16*6+15:16*6] = unpack_out_pd[16*13+15: 16*13];
assign mode_2bytex2_mul_rod0_pd[16*7+15:16*7] = unpack_out_pd[16*15+15: 16*15];
assign mode_2bytex2_mul_rod0_pd[16*8+15:16*8] = unpack_out_pd[16*17+15: 16*17];
assign mode_2bytex2_mul_rod0_pd[16*9+15:16*9] = unpack_out_pd[16*19+15: 16*19];
assign mode_2bytex2_mul_rod0_pd[16*10+15:16*10] = unpack_out_pd[16*21+15: 16*21];
assign mode_2bytex2_mul_rod0_pd[16*11+15:16*11] = unpack_out_pd[16*23+15: 16*23];
assign mode_2bytex2_mul_rod0_pd[16*12+15:16*12] = unpack_out_pd[16*25+15: 16*25];
assign mode_2bytex2_mul_rod0_pd[16*13+15:16*13] = unpack_out_pd[16*27+15: 16*27];
assign mode_2bytex2_mul_rod0_pd[16*14+15:16*14] = unpack_out_pd[16*29+15: 16*29];
assign mode_2bytex2_mul_rod0_pd[16*15+15:16*15] = unpack_out_pd[16*31+15: 16*31];
assign mode_2bytex2_mul_rod1_pd[16*0+15:16*0] = unpack_out_pd[16*33+15: 16*33];
assign mode_2bytex2_mul_rod1_pd[16*1+15:16*1] = unpack_out_pd[16*35+15: 16*35];
assign mode_2bytex2_mul_rod1_pd[16*2+15:16*2] = unpack_out_pd[16*37+15: 16*37];
assign mode_2bytex2_mul_rod1_pd[16*3+15:16*3] = unpack_out_pd[16*39+15: 16*39];
assign mode_2bytex2_mul_rod1_pd[16*4+15:16*4] = unpack_out_pd[16*41+15: 16*41];
assign mode_2bytex2_mul_rod1_pd[16*5+15:16*5] = unpack_out_pd[16*43+15: 16*43];
assign mode_2bytex2_mul_rod1_pd[16*6+15:16*6] = unpack_out_pd[16*45+15: 16*45];
assign mode_2bytex2_mul_rod1_pd[16*7+15:16*7] = unpack_out_pd[16*47+15: 16*47];
assign mode_2bytex2_mul_rod1_pd[16*8+15:16*8] = unpack_out_pd[16*49+15: 16*49];
assign mode_2bytex2_mul_rod1_pd[16*9+15:16*9] = unpack_out_pd[16*51+15: 16*51];
assign mode_2bytex2_mul_rod1_pd[16*10+15:16*10] = unpack_out_pd[16*53+15: 16*53];
assign mode_2bytex2_mul_rod1_pd[16*11+15:16*11] = unpack_out_pd[16*55+15: 16*55];
assign mode_2bytex2_mul_rod1_pd[16*12+15:16*12] = unpack_out_pd[16*57+15: 16*57];
assign mode_2bytex2_mul_rod1_pd[16*13+15:16*13] = unpack_out_pd[16*59+15: 16*59];
assign mode_2bytex2_mul_rod1_pd[16*14+15:16*14] = unpack_out_pd[16*61+15: 16*61];
assign mode_2bytex2_mul_rod1_pd[16*15+15:16*15] = unpack_out_pd[16*63+15: 16*63];
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [32*8 -1:0] alu_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod0_pd : unpack_out_pd[(32*8*0+32*8 -1):32*8*0];
wire [32*8 -1:0] alu_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod1_pd : unpack_out_pd[(32*8*1+32*8 -1):32*8*1];
wire [32*8 -1:0] alu_rod2_pd = unpack_out_pd[(32*8*2+32*8 -1):32*8*2];
wire [32*8 -1:0] alu_rod3_pd = unpack_out_pd[(32*8*3+32*8 -1):32*8*3];
wire [32*8 -1:0] mul_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod0_pd : unpack_out_pd[(32*8*0+32*8 -1):32*8*0];
wire [32*8 -1:0] mul_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod1_pd : unpack_out_pd[(32*8*1+32*8 -1):32*8*1];
wire [32*8 -1:0] mul_rod2_pd = unpack_out_pd[(32*8*2+32*8 -1):32*8*2];
wire [32*8 -1:0] mul_rod3_pd = unpack_out_pd[(32*8*3+32*8 -1):32*8*3];
wire [3:0] alu_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0];
wire [3:0] mul_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0];
wire [2:0] alu_roc_size = alu_rod_mask[3] + alu_rod_mask[2] + alu_rod_mask[1] + alu_rod_mask[0];
wire [2:0] mul_roc_size = mul_rod_mask[3] + mul_rod_mask[2] + mul_rod_mask[1] + mul_rod_mask[0];
assign alu_rod_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_rod_rdy : 1'b1);
assign mul_rod_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_rod_rdy : 1'b1);
assign alu_roc_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_roc_rdy & mul_rod_rdy & alu_rod_rdy : alu_rod_rdy);
assign mul_roc_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_roc_rdy & mul_rod_rdy & alu_rod_rdy : mul_rod_rdy);
wire [1:0] alu_roc_pd,mul_roc_pd;
wire mon_alu_roc_c,mon_mul_roc_c;
assign {mon_alu_roc_c,alu_roc_pd} = alu_roc_size -1;
assign {mon_mul_roc_c,mul_roc_pd} = mul_roc_size -1;
//assert: alu_rod_vld & !alu_roc_rdy
////////////////split unpack pd to 4 atomic_m alu or mul data /////////////////////
NV_NVDLA_SDP_RDMA_EG_ro u_alu (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.sdp_rdma2dp_valid (sdp_rdma2dp_alu_valid)
,.sdp_rdma2dp_ready (sdp_rdma2dp_alu_ready)
,.sdp_rdma2dp_pd (sdp_rdma2dp_alu_pd[32*16:0])
,.rod0_wr_pd (alu_rod0_pd[32*8 -1:0])
,.rod1_wr_pd (alu_rod1_pd[32*8 -1:0])
,.rod2_wr_pd (alu_rod2_pd[32*8 -1:0])
,.rod3_wr_pd (alu_rod3_pd[32*8 -1:0])
,.rod_wr_mask (alu_rod_mask[3:0])
,.rod_wr_vld (alu_rod_vld)
,.rod_wr_rdy (alu_rod_rdy)
,.roc_wr_pd (alu_roc_pd[1:0])
,.roc_wr_vld (alu_roc_vld)
,.roc_wr_rdy (alu_roc_rdy)
,.cfg_dp_8 (cfg_dp_8)
,.cfg_dp_size_1byte (cfg_data_size_1byte)
,.cfg_mode_per_element (cfg_mode_per_element)
,.cfg_mode_multi_batch (cfg_mode_multi_batch)
,.reg2dp_batch_number (reg2dp_batch_number[4:0])
,.reg2dp_channel (reg2dp_channel[12:0])
,.reg2dp_height (reg2dp_height[12:0])
,.reg2dp_width (reg2dp_width[12:0])
,.layer_end (alu_layer_end)
);
NV_NVDLA_SDP_RDMA_EG_ro u_mul (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.pwrbus_ram_pd (pwrbus_ram_pd)
,.sdp_rdma2dp_valid (sdp_rdma2dp_mul_valid)
,.sdp_rdma2dp_ready (sdp_rdma2dp_mul_ready)
,.sdp_rdma2dp_pd (sdp_rdma2dp_mul_pd[32*16:0])
,.rod0_wr_pd (mul_rod0_pd[32*8 -1:0])
,.rod1_wr_pd (mul_rod1_pd[32*8 -1:0])
,.rod2_wr_pd (mul_rod2_pd[32*8 -1:0])
,.rod3_wr_pd (mul_rod3_pd[32*8 -1:0])
,.rod_wr_mask (mul_rod_mask[3:0])
,.rod_wr_vld (mul_rod_vld)
,.rod_wr_rdy (mul_rod_rdy)
,.roc_wr_pd (mul_roc_pd[1:0])
,.roc_wr_vld (mul_roc_vld)
,.roc_wr_rdy (mul_roc_rdy)
,.cfg_dp_8 (cfg_dp_8)
,.cfg_dp_size_1byte (cfg_data_size_1byte)
,.cfg_mode_per_element (cfg_mode_per_element)
,.cfg_mode_multi_batch (cfg_mode_multi_batch)
,.reg2dp_batch_number (reg2dp_batch_number[4:0])
,.reg2dp_channel (reg2dp_channel[12:0])
,.reg2dp_height (reg2dp_height[12:0])
,.reg2dp_width (reg2dp_width[12:0])
,.layer_end (mul_layer_end)
);
//==========================================================
// Layer Done
//==========================================================
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
alu_layer_done <= 1'b0;
end else begin
if (op_load) begin
if (cfg_alu_en) begin
alu_layer_done <= 1'b0;
end else begin
alu_layer_done <= 1'b1;
end
end else if (alu_layer_end) begin
alu_layer_done <= 1'b1;
end else if (layer_done) begin
alu_layer_done <= 1'b0;
end
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mul_layer_done <= 1'b0;
end else begin
if (op_load) begin
if (cfg_mul_en) begin
mul_layer_done <= 1'b0;
end else begin
mul_layer_done <= 1'b1;
end
end else if (mul_layer_end) begin
mul_layer_done <= 1'b1;
end else if (layer_done) begin
mul_layer_done <= 1'b0;
end
end
end
assign layer_done = alu_layer_done & mul_layer_done;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
eg_done <= 1'b0;
end else begin
eg_done <= layer_done;
end
end
endmodule // NV_NVDLA_SDP_RDMA_eg |
module NV_DW_lsd (a, dec, enc);
parameter a_width = 8;
parameter b_width = a_width-1;
localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1)));
input [a_width-1:0] a;
output [a_width-1:0] dec;
output [enc_width-1:0] enc;
//get the encoded output: the number of sign bits.
function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A);
reg [enc_width-1:0] temp_enc;
reg [enc_width-1:0] i;
reg done;
begin
done =0;
temp_enc = a_width-1;
for (i=a_width-2; done==0; i=i-1) begin
if (A[i+1] != A[i]) begin
temp_enc = a_width - i -2;
done =1;
end
else if(i==0) begin
temp_enc = a_width-1;
done =1;
end
end
DWF_lsd_enc = temp_enc;
end
endfunction
//get the sign bit position of input.
function [a_width-1:0] DWF_lsd (input [a_width-1:0] A);
reg [enc_width-1:0] temp_enc;
reg [a_width-1:0] temp_dec;
reg [enc_width-1:0] temp;
begin
temp_enc = DWF_lsd_enc (A);
temp_dec = {a_width{1'b0}};
temp = b_width - temp_enc;
temp_dec[temp] = 1'b1;
DWF_lsd = temp_dec;
end
endfunction
assign enc = DWF_lsd_enc (a);
assign dec = DWF_lsd (a);
endmodule |
module NV_NVDLA_CDP_dp (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,cdp_dp2wdma_ready //|< i
,cdp_rdma2dp_pd //|< i
,cdp_rdma2dp_valid //|< i
,dp2reg_done //|< i
,nvdla_core_clk_orig //|< i
,pwrbus_ram_pd //|< i
,reg2dp_datin_offset //|< i
,reg2dp_datin_scale //|< i
,reg2dp_datin_shifter //|< i
,reg2dp_datout_offset //|< i
,reg2dp_datout_scale //|< i
,reg2dp_datout_shifter //|< i
,reg2dp_lut_access_type //|< i
,reg2dp_lut_addr //|< i
,reg2dp_lut_data //|< i
,reg2dp_lut_data_trigger //|< i
,reg2dp_lut_hybrid_priority //|< i
,reg2dp_lut_le_end_high //|< i
,reg2dp_lut_le_end_low //|< i
,reg2dp_lut_le_function //|< i
,reg2dp_lut_le_index_offset //|< i
,reg2dp_lut_le_index_select //|< i
,reg2dp_lut_le_slope_oflow_scale //|< i
,reg2dp_lut_le_slope_oflow_shift //|< i
,reg2dp_lut_le_slope_uflow_scale //|< i
,reg2dp_lut_le_slope_uflow_shift //|< i
,reg2dp_lut_le_start_high //|< i
,reg2dp_lut_le_start_low //|< i
,reg2dp_lut_lo_end_high //|< i
,reg2dp_lut_lo_end_low //|< i
,reg2dp_lut_lo_index_select //|< i
,reg2dp_lut_lo_slope_oflow_scale //|< i
,reg2dp_lut_lo_slope_oflow_shift //|< i
,reg2dp_lut_lo_slope_uflow_scale //|< i
,reg2dp_lut_lo_slope_uflow_shift //|< i
,reg2dp_lut_lo_start_high //|< i
,reg2dp_lut_lo_start_low //|< i
,reg2dp_lut_oflow_priority //|< i
,reg2dp_lut_table_id //|< i
,reg2dp_lut_uflow_priority //|< i
,reg2dp_mul_bypass //|< i
,reg2dp_normalz_len //|< i
,reg2dp_sqsum_bypass //|< i
,cdp_dp2wdma_pd //|> o
,cdp_dp2wdma_valid //|> o
,cdp_rdma2dp_ready //|> o
,dp2reg_d0_out_saturation //|> o
,dp2reg_d0_perf_lut_hybrid //|> o
,dp2reg_d0_perf_lut_le_hit //|> o
,dp2reg_d0_perf_lut_lo_hit //|> o
,dp2reg_d0_perf_lut_oflow //|> o
,dp2reg_d0_perf_lut_uflow //|> o
,dp2reg_d1_out_saturation //|> o
,dp2reg_d1_perf_lut_hybrid //|> o
,dp2reg_d1_perf_lut_le_hit //|> o
,dp2reg_d1_perf_lut_lo_hit //|> o
,dp2reg_d1_perf_lut_oflow //|> o
,dp2reg_d1_perf_lut_uflow //|> o
,dp2reg_lut_data //|> o
);
///////////////////////////////////////////////////////
///////////////////////////////////////////////////////
//&Clock nvdla_core_clk;
//&Reset nvdla_core_rstn;
input [31:0] pwrbus_ram_pd;
input dp2reg_done;
input [15:0] reg2dp_datin_offset;
input [15:0] reg2dp_datin_scale;
input [4:0] reg2dp_datin_shifter;
input [31:0] reg2dp_datout_offset;
input [15:0] reg2dp_datout_scale;
input [5:0] reg2dp_datout_shifter;
input reg2dp_lut_access_type;
input [9:0] reg2dp_lut_addr;
input [15:0] reg2dp_lut_data;
input reg2dp_lut_data_trigger;
input reg2dp_lut_hybrid_priority;
input [5:0] reg2dp_lut_le_end_high;
input [31:0] reg2dp_lut_le_end_low;
input reg2dp_lut_le_function;
input [7:0] reg2dp_lut_le_index_offset;
input [7:0] reg2dp_lut_le_index_select;
input [15:0] reg2dp_lut_le_slope_oflow_scale;
input [4:0] reg2dp_lut_le_slope_oflow_shift;
input [15:0] reg2dp_lut_le_slope_uflow_scale;
input [4:0] reg2dp_lut_le_slope_uflow_shift;
input [5:0] reg2dp_lut_le_start_high;
input [31:0] reg2dp_lut_le_start_low;
input [5:0] reg2dp_lut_lo_end_high;
input [31:0] reg2dp_lut_lo_end_low;
input [7:0] reg2dp_lut_lo_index_select;
input [15:0] reg2dp_lut_lo_slope_oflow_scale;
input [4:0] reg2dp_lut_lo_slope_oflow_shift;
input [15:0] reg2dp_lut_lo_slope_uflow_scale;
input [4:0] reg2dp_lut_lo_slope_uflow_shift;
input [5:0] reg2dp_lut_lo_start_high;
input [31:0] reg2dp_lut_lo_start_low;
input reg2dp_lut_oflow_priority;
input reg2dp_lut_table_id;
input reg2dp_lut_uflow_priority;
input reg2dp_mul_bypass;
input [1:0] reg2dp_normalz_len;
input reg2dp_sqsum_bypass;
output [31:0] dp2reg_d0_out_saturation;
output [31:0] dp2reg_d0_perf_lut_hybrid;
output [31:0] dp2reg_d0_perf_lut_le_hit;
output [31:0] dp2reg_d0_perf_lut_lo_hit;
output [31:0] dp2reg_d0_perf_lut_oflow;
output [31:0] dp2reg_d0_perf_lut_uflow;
output [31:0] dp2reg_d1_out_saturation;
output [31:0] dp2reg_d1_perf_lut_hybrid;
output [31:0] dp2reg_d1_perf_lut_le_hit;
output [31:0] dp2reg_d1_perf_lut_lo_hit;
output [31:0] dp2reg_d1_perf_lut_oflow;
output [31:0] dp2reg_d1_perf_lut_uflow;
output [15:0] dp2reg_lut_data;
//
// NV_NVDLA_CDP_core_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
input cdp_rdma2dp_valid; /* data valid */
output cdp_rdma2dp_ready; /* data return handshake */
input [8*8 +24:0] cdp_rdma2dp_pd;
output cdp_dp2wdma_valid; /* data valid */
input cdp_dp2wdma_ready; /* data return handshake */
output [8*8 +16:0] cdp_dp2wdma_pd;
input nvdla_core_clk_orig;
///////////////////////////////////////////////////////////////////
reg sqsum_bypass_en;
//: my $icvto = (8 +1);
//: my $k = 8;
//: print qq(
//: wire [${k}*${icvto}+16:0] bufin_pd;
//: wire [${k}*${icvto}+16:0] cvt2buf_pd;
//: wire [${k}*${icvto}+16:0] cvt2sync_pd;
//: wire [${k}*(${icvto}*2+3)-1:0] cvtin_out_int8_ext;
//: wire [${k}*(${icvto}*2+3)-1:0] lutctrl_in_pd;
//: wire [${k}*(${icvto}+16)-1:0] mul2ocvt_pd;
//: wire [${k}*(${icvto}*2+3)-1:0] sum2itp_pd;
//: wire [${k}*(${icvto}*2+3)-1:0] sum2sync_pd;
//: wire [${k}*(${icvto}*2+3)-1:0] sync2itp_pd;
//: wire [${k}*${icvto}-1:0] sync2mul_pd;
//: );
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [8*9+16:0] bufin_pd;
wire [8*9+16:0] cvt2buf_pd;
wire [8*9+16:0] cvt2sync_pd;
wire [8*(9*2+3)-1:0] cvtin_out_int8_ext;
wire [8*(9*2+3)-1:0] lutctrl_in_pd;
wire [8*(9+16)-1:0] mul2ocvt_pd;
wire [8*(9*2+3)-1:0] sum2itp_pd;
wire [8*(9*2+3)-1:0] sum2sync_pd;
wire [8*(9*2+3)-1:0] sync2itp_pd;
wire [8*9-1:0] sync2mul_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire bufin_prdy;
wire bufin_pvld;
wire cvt2buf_prdy;
wire cvt2buf_pvld;
wire cvt2sync_prdy;
wire cvt2sync_pvld;
//: my $k = 8;
//: my $icvto = (8 +1);
//: foreach my $m (0..$k-1) {
//: print qq(
//: wire [${icvto}-1:0] cvtin_out_int8_$m;
//: wire [9:0] dp2lut_X_entry_${m} ;
//: wire [17:0] dp2lut_Xinfo_${m} ;
//: wire [9:0] dp2lut_Y_entry_${m} ;
//: wire [17:0] dp2lut_Yinfo_${m} ;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [9-1:0] cvtin_out_int8_0;
wire [9:0] dp2lut_X_entry_0 ;
wire [17:0] dp2lut_Xinfo_0 ;
wire [9:0] dp2lut_Y_entry_0 ;
wire [17:0] dp2lut_Yinfo_0 ;
wire [9-1:0] cvtin_out_int8_1;
wire [9:0] dp2lut_X_entry_1 ;
wire [17:0] dp2lut_Xinfo_1 ;
wire [9:0] dp2lut_Y_entry_1 ;
wire [17:0] dp2lut_Yinfo_1 ;
wire [9-1:0] cvtin_out_int8_2;
wire [9:0] dp2lut_X_entry_2 ;
wire [17:0] dp2lut_Xinfo_2 ;
wire [9:0] dp2lut_Y_entry_2 ;
wire [17:0] dp2lut_Yinfo_2 ;
wire [9-1:0] cvtin_out_int8_3;
wire [9:0] dp2lut_X_entry_3 ;
wire [17:0] dp2lut_Xinfo_3 ;
wire [9:0] dp2lut_Y_entry_3 ;
wire [17:0] dp2lut_Yinfo_3 ;
wire [9-1:0] cvtin_out_int8_4;
wire [9:0] dp2lut_X_entry_4 ;
wire [17:0] dp2lut_Xinfo_4 ;
wire [9:0] dp2lut_Y_entry_4 ;
wire [17:0] dp2lut_Yinfo_4 ;
wire [9-1:0] cvtin_out_int8_5;
wire [9:0] dp2lut_X_entry_5 ;
wire [17:0] dp2lut_Xinfo_5 ;
wire [9:0] dp2lut_Y_entry_5 ;
wire [17:0] dp2lut_Yinfo_5 ;
wire [9-1:0] cvtin_out_int8_6;
wire [9:0] dp2lut_X_entry_6 ;
wire [17:0] dp2lut_Xinfo_6 ;
wire [9:0] dp2lut_Y_entry_6 ;
wire [17:0] dp2lut_Yinfo_6 ;
wire [9-1:0] cvtin_out_int8_7;
wire [9:0] dp2lut_X_entry_7 ;
wire [17:0] dp2lut_Xinfo_7 ;
wire [9:0] dp2lut_Y_entry_7 ;
wire [17:0] dp2lut_Yinfo_7 ;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire dp2lut_prdy;
wire dp2lut_pvld;
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: wire [16:0] intp2mul_pd_$m;
//: wire [31:0] lut2intp_X_data_${m}0;
//: wire [16:0] lut2intp_X_data_${m}0_17b;
//: wire [31:0] lut2intp_X_data_${m}1;
//: wire [19:0] lut2intp_X_info_${m};
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [16:0] intp2mul_pd_0;
wire [31:0] lut2intp_X_data_00;
wire [16:0] lut2intp_X_data_00_17b;
wire [31:0] lut2intp_X_data_01;
wire [19:0] lut2intp_X_info_0;
wire [16:0] intp2mul_pd_1;
wire [31:0] lut2intp_X_data_10;
wire [16:0] lut2intp_X_data_10_17b;
wire [31:0] lut2intp_X_data_11;
wire [19:0] lut2intp_X_info_1;
wire [16:0] intp2mul_pd_2;
wire [31:0] lut2intp_X_data_20;
wire [16:0] lut2intp_X_data_20_17b;
wire [31:0] lut2intp_X_data_21;
wire [19:0] lut2intp_X_info_2;
wire [16:0] intp2mul_pd_3;
wire [31:0] lut2intp_X_data_30;
wire [16:0] lut2intp_X_data_30_17b;
wire [31:0] lut2intp_X_data_31;
wire [19:0] lut2intp_X_info_3;
wire [16:0] intp2mul_pd_4;
wire [31:0] lut2intp_X_data_40;
wire [16:0] lut2intp_X_data_40_17b;
wire [31:0] lut2intp_X_data_41;
wire [19:0] lut2intp_X_info_4;
wire [16:0] intp2mul_pd_5;
wire [31:0] lut2intp_X_data_50;
wire [16:0] lut2intp_X_data_50_17b;
wire [31:0] lut2intp_X_data_51;
wire [19:0] lut2intp_X_info_5;
wire [16:0] intp2mul_pd_6;
wire [31:0] lut2intp_X_data_60;
wire [16:0] lut2intp_X_data_60_17b;
wire [31:0] lut2intp_X_data_61;
wire [19:0] lut2intp_X_info_6;
wire [16:0] intp2mul_pd_7;
wire [31:0] lut2intp_X_data_70;
wire [16:0] lut2intp_X_data_70_17b;
wire [31:0] lut2intp_X_data_71;
wire [19:0] lut2intp_X_info_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire intp2mul_prdy;
wire intp2mul_pvld;
wire [8 -1:0] lut2intp_X_sel;
wire [8 -1:0] lut2intp_Y_sel;
wire lut2intp_prdy;
wire lut2intp_pvld;
wire lutctrl_in_pvld;
wire mul2ocvt_prdy;
wire mul2ocvt_pvld;
//: my $icvto = (8 +1);
//: my $tp = 8;
//: my $k = (${tp}+8)*${icvto}+17;
//: print "wire [${k}-1:0] normalz_buf_data; \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [161-1:0] normalz_buf_data;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire normalz_buf_data_prdy;
wire normalz_buf_data_pvld;
wire sum2itp_prdy;
wire sum2itp_pvld;
wire sum2sync_prdy;
wire sum2sync_pvld;
wire sync2itp_prdy;
wire sync2itp_pvld;
wire sync2mul_prdy;
wire sync2mul_pvld;
wire [16:0] sync2ocvt_pd;
wire sync2ocvt_prdy;
wire sync2ocvt_pvld;
///////////////////////////////////////////////////////
assign dp2reg_d0_out_saturation = 32'd0;//for spyglass
assign dp2reg_d1_out_saturation = 32'd0;//for spyglass
/////////////////////////////
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
sqsum_bypass_en <= 1'b0;
end else begin
sqsum_bypass_en <= reg2dp_sqsum_bypass == 1'h1;
end
end
//===== convertor_in Instance========
assign cvt2buf_prdy = sqsum_bypass_en ? sum2itp_prdy : bufin_prdy;
NV_NVDLA_CDP_DP_cvtin u_NV_NVDLA_CDP_DP_cvtin (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cdp_rdma2dp_pd (cdp_rdma2dp_pd)
,.cdp_rdma2dp_valid (cdp_rdma2dp_valid)
,.cvt2buf_prdy (cvt2buf_prdy)
,.cvt2sync_prdy (cvt2sync_prdy)
,.reg2dp_datin_offset (reg2dp_datin_offset[15:0])
,.reg2dp_datin_scale (reg2dp_datin_scale[15:0])
,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0])
,.cdp_rdma2dp_ready (cdp_rdma2dp_ready)
,.cvt2buf_pd (cvt2buf_pd)
,.cvt2buf_pvld (cvt2buf_pvld)
,.cvt2sync_pd (cvt2sync_pd)
,.cvt2sync_pvld (cvt2sync_pvld)
);
//===== sync fifo Instance========
NV_NVDLA_CDP_DP_syncfifo u_NV_NVDLA_CDP_DP_syncfifo (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt2sync_pd (cvt2sync_pd)
,.cvt2sync_pvld (cvt2sync_pvld)
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
,.sum2sync_pd (sum2sync_pd)
,.sum2sync_pvld (sum2sync_pvld)
,.sync2itp_prdy (sync2itp_prdy)
,.sync2mul_prdy (sync2mul_prdy)
,.sync2ocvt_prdy (sync2ocvt_prdy)
,.cvt2sync_prdy (cvt2sync_prdy)
,.sum2sync_prdy (sum2sync_prdy)
,.sync2itp_pd (sync2itp_pd)
,.sync2itp_pvld (sync2itp_pvld)
,.sync2mul_pd (sync2mul_pd)
,.sync2mul_pvld (sync2mul_pvld)
,.sync2ocvt_pd (sync2ocvt_pd[16:0])
,.sync2ocvt_pvld (sync2ocvt_pvld)
);
//===== Buffer_in Instance========
assign bufin_pd = sqsum_bypass_en ? 0 : cvt2buf_pd;
assign bufin_pvld = sqsum_bypass_en ? 0 : cvt2buf_pvld;
//: if(8 >= 4) {
//: print qq(
//: NV_NVDLA_CDP_DP_bufferin u_NV_NVDLA_CDP_DP_bufferin (
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.cdp_rdma2dp_pd (bufin_pd)
//: ,.cdp_rdma2dp_valid (bufin_pvld)
//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy)
//: ,.cdp_rdma2dp_ready (bufin_prdy)
//: ,.normalz_buf_data (normalz_buf_data)
//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld)
//: );
//: );
//: } elsif(8 < 4) {
//: print qq(
//: NV_NVDLA_CDP_DP_bufferin_tp1 u_NV_NVDLA_CDP_DP_bufferin (
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.cdp_rdma2dp_pd (bufin_pd)
//: ,.cdp_rdma2dp_valid (bufin_pvld)
//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy)
//: ,.cdp_rdma2dp_ready (bufin_prdy)
//: ,.normalz_buf_data (normalz_buf_data)
//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld)
//: );
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
NV_NVDLA_CDP_DP_bufferin u_NV_NVDLA_CDP_DP_bufferin (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cdp_rdma2dp_pd (bufin_pd)
,.cdp_rdma2dp_valid (bufin_pvld)
,.normalz_buf_data_prdy (normalz_buf_data_prdy)
,.cdp_rdma2dp_ready (bufin_prdy)
,.normalz_buf_data (normalz_buf_data)
,.normalz_buf_data_pvld (normalz_buf_data_pvld)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
//===== sigma squre Instance========
NV_NVDLA_CDP_DP_sum u_NV_NVDLA_CDP_DP_sum (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.normalz_buf_data (normalz_buf_data)
,.normalz_buf_data_pvld (normalz_buf_data_pvld)
,.reg2dp_normalz_len (reg2dp_normalz_len[1:0])
,.sum2itp_prdy (sum2itp_prdy)
,.normalz_buf_data_prdy (normalz_buf_data_prdy)
,.sum2itp_pd (sum2itp_pd)
,.sum2itp_pvld (sum2itp_pvld)
);
//===== LUT controller Instance========
//: my $icvto = (8 +1);
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: assign cvtin_out_int8_$m = cvt2buf_pd[${m}*${icvto}+${icvto}-1:${m}*${icvto}];
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign cvtin_out_int8_0 = cvt2buf_pd[0*9+9-1:0*9];
assign cvtin_out_int8_1 = cvt2buf_pd[1*9+9-1:1*9];
assign cvtin_out_int8_2 = cvt2buf_pd[2*9+9-1:2*9];
assign cvtin_out_int8_3 = cvt2buf_pd[3*9+9-1:3*9];
assign cvtin_out_int8_4 = cvt2buf_pd[4*9+9-1:4*9];
assign cvtin_out_int8_5 = cvt2buf_pd[5*9+9-1:5*9];
assign cvtin_out_int8_6 = cvt2buf_pd[6*9+9-1:6*9];
assign cvtin_out_int8_7 = cvt2buf_pd[7*9+9-1:7*9];
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign cvtin_out_int8_ext = {
//: my $k = 8;
//: my $icvto = (8 +1);
//: if($k > 1) {
//: foreach my $m (0..$k-2) {
//: my $ss = $k -$m -1;
//: print qq(
//: {{(${icvto}+3){cvtin_out_int8_${ss}[${icvto}-1]}}, cvtin_out_int8_${ss}},
//: );
//: }
//: }
//: print "{{(${icvto}+3){cvtin_out_int8_0[${icvto}-1]}}, cvtin_out_int8_0}}; \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
{{(9+3){cvtin_out_int8_7[9-1]}}, cvtin_out_int8_7},
{{(9+3){cvtin_out_int8_6[9-1]}}, cvtin_out_int8_6},
{{(9+3){cvtin_out_int8_5[9-1]}}, cvtin_out_int8_5},
{{(9+3){cvtin_out_int8_4[9-1]}}, cvtin_out_int8_4},
{{(9+3){cvtin_out_int8_3[9-1]}}, cvtin_out_int8_3},
{{(9+3){cvtin_out_int8_2[9-1]}}, cvtin_out_int8_2},
{{(9+3){cvtin_out_int8_1[9-1]}}, cvtin_out_int8_1},
{{(9+3){cvtin_out_int8_0[9-1]}}, cvtin_out_int8_0}};
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign lutctrl_in_pd = sqsum_bypass_en ? cvtin_out_int8_ext : sum2itp_pd;
assign lutctrl_in_pvld = sqsum_bypass_en ? cvt2buf_pvld : sum2itp_pvld;
NV_NVDLA_CDP_DP_LUT_ctrl u_NV_NVDLA_CDP_DP_LUT_ctrl (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.dp2lut_prdy (dp2lut_prdy) //|< w
,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|< i
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|< i
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i
,.sum2itp_pd (lutctrl_in_pd) //|< w
,.sum2itp_pvld (lutctrl_in_pvld) //|< w
,.sum2sync_prdy (sum2sync_prdy) //|< w
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} )
//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} )
//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} )
//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} )
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.dp2lut_X_entry_0 (dp2lut_X_entry_0 )
,.dp2lut_Xinfo_0 (dp2lut_Xinfo_0 )
,.dp2lut_Y_entry_0 (dp2lut_Y_entry_0 )
,.dp2lut_Yinfo_0 (dp2lut_Yinfo_0 )
,.dp2lut_X_entry_1 (dp2lut_X_entry_1 )
,.dp2lut_Xinfo_1 (dp2lut_Xinfo_1 )
,.dp2lut_Y_entry_1 (dp2lut_Y_entry_1 )
,.dp2lut_Yinfo_1 (dp2lut_Yinfo_1 )
,.dp2lut_X_entry_2 (dp2lut_X_entry_2 )
,.dp2lut_Xinfo_2 (dp2lut_Xinfo_2 )
,.dp2lut_Y_entry_2 (dp2lut_Y_entry_2 )
,.dp2lut_Yinfo_2 (dp2lut_Yinfo_2 )
,.dp2lut_X_entry_3 (dp2lut_X_entry_3 )
,.dp2lut_Xinfo_3 (dp2lut_Xinfo_3 )
,.dp2lut_Y_entry_3 (dp2lut_Y_entry_3 )
,.dp2lut_Yinfo_3 (dp2lut_Yinfo_3 )
,.dp2lut_X_entry_4 (dp2lut_X_entry_4 )
,.dp2lut_Xinfo_4 (dp2lut_Xinfo_4 )
,.dp2lut_Y_entry_4 (dp2lut_Y_entry_4 )
,.dp2lut_Yinfo_4 (dp2lut_Yinfo_4 )
,.dp2lut_X_entry_5 (dp2lut_X_entry_5 )
,.dp2lut_Xinfo_5 (dp2lut_Xinfo_5 )
,.dp2lut_Y_entry_5 (dp2lut_Y_entry_5 )
,.dp2lut_Yinfo_5 (dp2lut_Yinfo_5 )
,.dp2lut_X_entry_6 (dp2lut_X_entry_6 )
,.dp2lut_Xinfo_6 (dp2lut_Xinfo_6 )
,.dp2lut_Y_entry_6 (dp2lut_Y_entry_6 )
,.dp2lut_Yinfo_6 (dp2lut_Yinfo_6 )
,.dp2lut_X_entry_7 (dp2lut_X_entry_7 )
,.dp2lut_Xinfo_7 (dp2lut_Xinfo_7 )
,.dp2lut_Y_entry_7 (dp2lut_Y_entry_7 )
,.dp2lut_Yinfo_7 (dp2lut_Yinfo_7 )
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.dp2lut_pvld (dp2lut_pvld) //|> w
,.sum2itp_prdy (sum2itp_prdy) //|> w
,.sum2sync_pd (sum2sync_pd) //|> w
,.sum2sync_pvld (sum2sync_pvld) //|> w
);
//===== LUT Instance========
NV_NVDLA_CDP_DP_lut u_NV_NVDLA_CDP_DP_lut (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_clk_orig (nvdla_core_clk_orig) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} )
//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} )
//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} )
//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} )
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.dp2lut_X_entry_0 (dp2lut_X_entry_0 )
,.dp2lut_Xinfo_0 (dp2lut_Xinfo_0 )
,.dp2lut_Y_entry_0 (dp2lut_Y_entry_0 )
,.dp2lut_Yinfo_0 (dp2lut_Yinfo_0 )
,.dp2lut_X_entry_1 (dp2lut_X_entry_1 )
,.dp2lut_Xinfo_1 (dp2lut_Xinfo_1 )
,.dp2lut_Y_entry_1 (dp2lut_Y_entry_1 )
,.dp2lut_Yinfo_1 (dp2lut_Yinfo_1 )
,.dp2lut_X_entry_2 (dp2lut_X_entry_2 )
,.dp2lut_Xinfo_2 (dp2lut_Xinfo_2 )
,.dp2lut_Y_entry_2 (dp2lut_Y_entry_2 )
,.dp2lut_Yinfo_2 (dp2lut_Yinfo_2 )
,.dp2lut_X_entry_3 (dp2lut_X_entry_3 )
,.dp2lut_Xinfo_3 (dp2lut_Xinfo_3 )
,.dp2lut_Y_entry_3 (dp2lut_Y_entry_3 )
,.dp2lut_Yinfo_3 (dp2lut_Yinfo_3 )
,.dp2lut_X_entry_4 (dp2lut_X_entry_4 )
,.dp2lut_Xinfo_4 (dp2lut_Xinfo_4 )
,.dp2lut_Y_entry_4 (dp2lut_Y_entry_4 )
,.dp2lut_Yinfo_4 (dp2lut_Yinfo_4 )
,.dp2lut_X_entry_5 (dp2lut_X_entry_5 )
,.dp2lut_Xinfo_5 (dp2lut_Xinfo_5 )
,.dp2lut_Y_entry_5 (dp2lut_Y_entry_5 )
,.dp2lut_Yinfo_5 (dp2lut_Yinfo_5 )
,.dp2lut_X_entry_6 (dp2lut_X_entry_6 )
,.dp2lut_Xinfo_6 (dp2lut_Xinfo_6 )
,.dp2lut_Y_entry_6 (dp2lut_Y_entry_6 )
,.dp2lut_Yinfo_6 (dp2lut_Yinfo_6 )
,.dp2lut_X_entry_7 (dp2lut_X_entry_7 )
,.dp2lut_Xinfo_7 (dp2lut_Xinfo_7 )
,.dp2lut_Y_entry_7 (dp2lut_Y_entry_7 )
,.dp2lut_Yinfo_7 (dp2lut_Yinfo_7 )
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.dp2lut_pvld (dp2lut_pvld) //|< w
,.lut2intp_prdy (lut2intp_prdy) //|< w
,.reg2dp_lut_access_type (reg2dp_lut_access_type) //|< i
,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) //|< i
,.reg2dp_lut_data (reg2dp_lut_data[15:0]) //|< i
,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) //|< i
,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|< i
,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) //|< i
,.reg2dp_lut_table_id (reg2dp_lut_table_id) //|< i
,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) //|< i
,.dp2lut_prdy (dp2lut_prdy) //|> w
,.dp2reg_lut_data (dp2reg_lut_data[15:0]) //|> o
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 )
//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b )
//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 )
//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} )
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.lut2intp_X_data_00 (lut2intp_X_data_00 )
,.lut2intp_X_data_00_17b (lut2intp_X_data_00_17b )
,.lut2intp_X_data_01 (lut2intp_X_data_01 )
,.lut2intp_X_info_0 (lut2intp_X_info_0 )
,.lut2intp_X_data_10 (lut2intp_X_data_10 )
,.lut2intp_X_data_10_17b (lut2intp_X_data_10_17b )
,.lut2intp_X_data_11 (lut2intp_X_data_11 )
,.lut2intp_X_info_1 (lut2intp_X_info_1 )
,.lut2intp_X_data_20 (lut2intp_X_data_20 )
,.lut2intp_X_data_20_17b (lut2intp_X_data_20_17b )
,.lut2intp_X_data_21 (lut2intp_X_data_21 )
,.lut2intp_X_info_2 (lut2intp_X_info_2 )
,.lut2intp_X_data_30 (lut2intp_X_data_30 )
,.lut2intp_X_data_30_17b (lut2intp_X_data_30_17b )
,.lut2intp_X_data_31 (lut2intp_X_data_31 )
,.lut2intp_X_info_3 (lut2intp_X_info_3 )
,.lut2intp_X_data_40 (lut2intp_X_data_40 )
,.lut2intp_X_data_40_17b (lut2intp_X_data_40_17b )
,.lut2intp_X_data_41 (lut2intp_X_data_41 )
,.lut2intp_X_info_4 (lut2intp_X_info_4 )
,.lut2intp_X_data_50 (lut2intp_X_data_50 )
,.lut2intp_X_data_50_17b (lut2intp_X_data_50_17b )
,.lut2intp_X_data_51 (lut2intp_X_data_51 )
,.lut2intp_X_info_5 (lut2intp_X_info_5 )
,.lut2intp_X_data_60 (lut2intp_X_data_60 )
,.lut2intp_X_data_60_17b (lut2intp_X_data_60_17b )
,.lut2intp_X_data_61 (lut2intp_X_data_61 )
,.lut2intp_X_info_6 (lut2intp_X_info_6 )
,.lut2intp_X_data_70 (lut2intp_X_data_70 )
,.lut2intp_X_data_70_17b (lut2intp_X_data_70_17b )
,.lut2intp_X_data_71 (lut2intp_X_data_71 )
,.lut2intp_X_info_7 (lut2intp_X_info_7 )
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.lut2intp_X_sel (lut2intp_X_sel) //|> w
,.lut2intp_Y_sel (lut2intp_Y_sel) //|> w
,.lut2intp_pvld (lut2intp_pvld) //|> w
);
//===== interpolator Instance========
NV_NVDLA_CDP_DP_intp u_NV_NVDLA_CDP_DP_intp (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.dp2reg_done (dp2reg_done) //|< i
,.intp2mul_prdy (intp2mul_prdy) //|< w
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 )
//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b )
//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 )
//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} )
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.lut2intp_X_data_00 (lut2intp_X_data_00 )
,.lut2intp_X_data_00_17b (lut2intp_X_data_00_17b )
,.lut2intp_X_data_01 (lut2intp_X_data_01 )
,.lut2intp_X_info_0 (lut2intp_X_info_0 )
,.lut2intp_X_data_10 (lut2intp_X_data_10 )
,.lut2intp_X_data_10_17b (lut2intp_X_data_10_17b )
,.lut2intp_X_data_11 (lut2intp_X_data_11 )
,.lut2intp_X_info_1 (lut2intp_X_info_1 )
,.lut2intp_X_data_20 (lut2intp_X_data_20 )
,.lut2intp_X_data_20_17b (lut2intp_X_data_20_17b )
,.lut2intp_X_data_21 (lut2intp_X_data_21 )
,.lut2intp_X_info_2 (lut2intp_X_info_2 )
,.lut2intp_X_data_30 (lut2intp_X_data_30 )
,.lut2intp_X_data_30_17b (lut2intp_X_data_30_17b )
,.lut2intp_X_data_31 (lut2intp_X_data_31 )
,.lut2intp_X_info_3 (lut2intp_X_info_3 )
,.lut2intp_X_data_40 (lut2intp_X_data_40 )
,.lut2intp_X_data_40_17b (lut2intp_X_data_40_17b )
,.lut2intp_X_data_41 (lut2intp_X_data_41 )
,.lut2intp_X_info_4 (lut2intp_X_info_4 )
,.lut2intp_X_data_50 (lut2intp_X_data_50 )
,.lut2intp_X_data_50_17b (lut2intp_X_data_50_17b )
,.lut2intp_X_data_51 (lut2intp_X_data_51 )
,.lut2intp_X_info_5 (lut2intp_X_info_5 )
,.lut2intp_X_data_60 (lut2intp_X_data_60 )
,.lut2intp_X_data_60_17b (lut2intp_X_data_60_17b )
,.lut2intp_X_data_61 (lut2intp_X_data_61 )
,.lut2intp_X_info_6 (lut2intp_X_info_6 )
,.lut2intp_X_data_70 (lut2intp_X_data_70 )
,.lut2intp_X_data_70_17b (lut2intp_X_data_70_17b )
,.lut2intp_X_data_71 (lut2intp_X_data_71 )
,.lut2intp_X_info_7 (lut2intp_X_info_7 )
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.lut2intp_X_sel (lut2intp_X_sel) //|< w
,.lut2intp_Y_sel (lut2intp_Y_sel) //|< w
,.lut2intp_pvld (lut2intp_pvld) //|< w
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) //|< i
,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) //|< i
,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i
,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|< i
,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|< i
,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|< i
,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|< i
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i
,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) //|< i
,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) //|< i
,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|< i
,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|< i
,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|< i
,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|< i
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i
,.sync2itp_pd (sync2itp_pd ) //|< w
,.sync2itp_pvld (sync2itp_pvld) //|< w
,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) //|> o
,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) //|> o
,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) //|> o
,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) //|> o
,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) //|> o
,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) //|> o
,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) //|> o
,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) //|> o
,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) //|> o
,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) //|> o
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.intp2mul_pd_0 (intp2mul_pd_0[16:0]) //|> w
,.intp2mul_pd_1 (intp2mul_pd_1[16:0]) //|> w
,.intp2mul_pd_2 (intp2mul_pd_2[16:0]) //|> w
,.intp2mul_pd_3 (intp2mul_pd_3[16:0]) //|> w
,.intp2mul_pd_4 (intp2mul_pd_4[16:0]) //|> w
,.intp2mul_pd_5 (intp2mul_pd_5[16:0]) //|> w
,.intp2mul_pd_6 (intp2mul_pd_6[16:0]) //|> w
,.intp2mul_pd_7 (intp2mul_pd_7[16:0]) //|> w
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.intp2mul_pvld (intp2mul_pvld) //|> w
,.lut2intp_prdy (lut2intp_prdy) //|> w
,.sync2itp_prdy (sync2itp_prdy) //|> w
);
//===== DP multiple Instance========
NV_NVDLA_CDP_DP_mul u_NV_NVDLA_CDP_DP_mul (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.intp2mul_pd_0 (intp2mul_pd_0[16:0]) //|> w
,.intp2mul_pd_1 (intp2mul_pd_1[16:0]) //|> w
,.intp2mul_pd_2 (intp2mul_pd_2[16:0]) //|> w
,.intp2mul_pd_3 (intp2mul_pd_3[16:0]) //|> w
,.intp2mul_pd_4 (intp2mul_pd_4[16:0]) //|> w
,.intp2mul_pd_5 (intp2mul_pd_5[16:0]) //|> w
,.intp2mul_pd_6 (intp2mul_pd_6[16:0]) //|> w
,.intp2mul_pd_7 (intp2mul_pd_7[16:0]) //|> w
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.intp2mul_pvld (intp2mul_pvld) //|< w
,.mul2ocvt_prdy (mul2ocvt_prdy) //|< w
,.reg2dp_mul_bypass (reg2dp_mul_bypass) //|< i
,.sync2mul_pd (sync2mul_pd) //|< w
,.sync2mul_pvld (sync2mul_pvld) //|< w
,.intp2mul_prdy (intp2mul_prdy) //|> w
,.mul2ocvt_pd (mul2ocvt_pd) //|> w
,.mul2ocvt_pvld (mul2ocvt_pvld) //|> w
,.sync2mul_prdy (sync2mul_prdy) //|> w
);
//===== convertor_out Instance========
NV_NVDLA_CDP_DP_cvtout u_NV_NVDLA_CDP_DP_cvtout (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cvtout_prdy (cdp_dp2wdma_ready) //|< i
,.mul2ocvt_pd (mul2ocvt_pd) //|< w
,.mul2ocvt_pvld (mul2ocvt_pvld) //|< w
,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) //|< i
,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) //|< i
,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) //|< i
,.sync2ocvt_pd (sync2ocvt_pd[16:0]) //|< w
,.sync2ocvt_pvld (sync2ocvt_pvld) //|< w
,.cvtout_pd (cdp_dp2wdma_pd) //|> o
,.cvtout_pvld (cdp_dp2wdma_valid) //|> o
,.mul2ocvt_prdy (mul2ocvt_prdy) //|> w
,.sync2ocvt_prdy (sync2ocvt_prdy) //|> w
);
////==============
////OBS signals
////==============
//assign obs_bus_cdp_rdma2dp_vld = cdp_rdma2dp_valid;
//assign obs_bus_cdp_rdma2dp_rdy = cdp_rdma2dp_ready;
//assign obs_bus_cdp_icvt_vld = cvt2buf_pvld;
//assign obs_bus_cdp_icvt_rdy = cvt2buf_prdy;
//assign obs_bus_cdp_buf_vld = normalz_buf_data_pvld;
//assign obs_bus_cdp_buf_rdy = normalz_buf_data_prdy;
//assign obs_bus_cdp_sum_vld = sum2itp_pvld;
//assign obs_bus_cdp_sum_rdy = sum2itp_prdy;
//assign obs_bus_cdp_lutctrl_vld = dp2lut_pvld;
//assign obs_bus_cdp_lutctrl_rdy = dp2lut_prdy;
//assign obs_bus_cdp_intp_vld = intp2mul_pvld;
//assign obs_bus_cdp_intp_rdy = intp2mul_prdy;
//assign obs_bus_cdp_ocvt_vld = cdp_dp2wdma_valid;
//assign obs_bus_cdp_ocvt_rdy = cdp_dp2wdma_ready;
endmodule // NV_NVDLA_CDP_dp |
module NV_NVDLA_SDP_RDMA_dmaif (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,sdp2cvif_rd_req_pd //|> o
,sdp2cvif_rd_req_valid //|> o
,sdp2cvif_rd_req_ready //|< i
,cvif2sdp_rd_rsp_pd //|< i
,cvif2sdp_rd_rsp_valid //|< i
,cvif2sdp_rd_rsp_ready //|> o
,sdp2cvif_rd_cdt_lat_fifo_pop //|> o
,sdp2mcif_rd_req_pd //|> o
,sdp2mcif_rd_req_valid //|> o
,sdp2mcif_rd_req_ready //|< i
,mcif2sdp_rd_rsp_pd //|< i
,mcif2sdp_rd_rsp_valid //|< i
,mcif2sdp_rd_rsp_ready //|> o
,sdp2mcif_rd_cdt_lat_fifo_pop //|> o
,dma_rd_req_ram_type //|< i
,dma_rd_req_pd //|< i
,dma_rd_req_vld //|< i
,dma_rd_req_rdy //|> o
,dma_rd_rsp_ram_type //|< i
,dma_rd_rsp_pd //|> o
,dma_rd_rsp_vld //|> o
,dma_rd_rsp_rdy //|< i
,dma_rd_cdt_lat_fifo_pop //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
output sdp2cvif_rd_cdt_lat_fifo_pop;
output [79 -1:0] sdp2cvif_rd_req_pd;
output sdp2cvif_rd_req_valid;
input sdp2cvif_rd_req_ready;
input [257 -1:0] cvif2sdp_rd_rsp_pd;
input cvif2sdp_rd_rsp_valid;
output cvif2sdp_rd_rsp_ready;
output [79 -1:0] sdp2mcif_rd_req_pd;
output sdp2mcif_rd_req_valid;
input sdp2mcif_rd_req_ready;
input [257 -1:0] mcif2sdp_rd_rsp_pd;
input mcif2sdp_rd_rsp_valid;
output mcif2sdp_rd_rsp_ready;
output sdp2mcif_rd_cdt_lat_fifo_pop;
input dma_rd_req_ram_type;
input dma_rd_req_vld;
output dma_rd_req_rdy;
input [79 -1:0] dma_rd_req_pd;
input dma_rd_rsp_ram_type;
output [257 -1:0] dma_rd_rsp_pd;
output dma_rd_rsp_vld;
input dma_rd_rsp_rdy;
input dma_rd_cdt_lat_fifo_pop;
reg sdp2mcif_rd_cdt_lat_fifo_pop;
reg sdp2cvif_rd_cdt_lat_fifo_pop;
NV_NVDLA_DMAIF_rdreq NV_NVDLA_SDP_RDMA_rdreq(
.nvdla_core_clk (nvdla_core_clk )
,.nvdla_core_rstn (nvdla_core_rstn )
,.reg2dp_src_ram_type (dma_rd_req_ram_type)
,.cvif_rd_req_pd (sdp2cvif_rd_req_pd )
,.cvif_rd_req_valid (sdp2cvif_rd_req_valid)
,.cvif_rd_req_ready (sdp2cvif_rd_req_ready)
,.mcif_rd_req_pd (sdp2mcif_rd_req_pd )
,.mcif_rd_req_valid (sdp2mcif_rd_req_valid)
,.mcif_rd_req_ready (sdp2mcif_rd_req_ready)
,.dmaif_rd_req_pd (dma_rd_req_pd )
,.dmaif_rd_req_vld (dma_rd_req_vld )
,.dmaif_rd_req_rdy (dma_rd_req_rdy )
);
NV_NVDLA_DMAIF_rdrsp NV_NVDLA_SDP_RDMA_rdrsp(
.nvdla_core_clk (nvdla_core_clk )
,.nvdla_core_rstn (nvdla_core_rstn )
,.cvif_rd_rsp_pd (cvif2sdp_rd_rsp_pd )
,.cvif_rd_rsp_valid (cvif2sdp_rd_rsp_valid )
,.cvif_rd_rsp_ready (cvif2sdp_rd_rsp_ready )
,.mcif_rd_rsp_pd (mcif2sdp_rd_rsp_pd )
,.mcif_rd_rsp_valid (mcif2sdp_rd_rsp_valid )
,.mcif_rd_rsp_ready (mcif2sdp_rd_rsp_ready )
,.dmaif_rd_rsp_pd (dma_rd_rsp_pd )
,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld )
,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy )
);
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
sdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0;
end else begin
sdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1);
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
sdp2cvif_rd_cdt_lat_fifo_pop <= 1'b0;
end else begin
sdp2cvif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b0);
end
end
endmodule |
module NV_NVDLA_SDP_HLS_Y_idx_top (
cfg_lut_hybrid_priority //|< i
,cfg_lut_le_function //|< i
,cfg_lut_le_index_offset //|< i
,cfg_lut_le_index_select //|< i
,cfg_lut_le_start //|< i
,cfg_lut_lo_index_select //|< i
,cfg_lut_lo_start //|< i
,cfg_lut_oflow_priority //|< i
,cfg_lut_uflow_priority //|< i
,chn_lut_in_pd //|< i
,chn_lut_in_pvld //|< i
,chn_lut_out_prdy //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,chn_lut_in_prdy //|> o
,chn_lut_out_pd //|> o
,chn_lut_out_pvld //|> o
);
input cfg_lut_hybrid_priority;
input cfg_lut_le_function;
input [7:0] cfg_lut_le_index_offset;
input [7:0] cfg_lut_le_index_select;
input [31:0] cfg_lut_le_start;
input [7:0] cfg_lut_lo_index_select;
input [31:0] cfg_lut_lo_start;
input cfg_lut_oflow_priority;
input cfg_lut_uflow_priority;
input [32*4 -1:0] chn_lut_in_pd;
input chn_lut_in_pvld;
input chn_lut_out_prdy;
output chn_lut_in_prdy;
output [81*4 -1:0] chn_lut_out_pd;
output chn_lut_out_pvld;
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $k=4;
//: my $bx =4*35;
//: my $bof=4*(35+32);
//: my $buf=4*(35+32+1);
//: my $bsl=4*(35+32+2);
//: my $ba =4*(35+32+3);
//: my $beh=4*(35+32+12);
//: my $boh=4*(35+32+13);
//: foreach my $i (0..${k}-1) {
//: print qq(
//: wire chn_lut_in_prdy$i;
//: wire chn_lut_out_pvld$i;
//: wire [31:0] lut_data_in$i;
//: wire [8:0] lut_out_addr$i;
//: wire [34:0] lut_out_fraction$i;
//: wire lut_out_le_hit$i;
//: wire lut_out_lo_hit$i;
//: wire lut_out_oflow$i;
//: wire lut_out_sel$i;
//: wire lut_out_uflow$i;
//: wire [31:0] lut_out_x$i;
//: );
//: }
//:
//:
//: foreach my $i (0..${k}-1) {
//: print "assign lut_data_in${i} = chn_lut_in_pd[32*${i}+31:32*${i}]; \n";
//: }
//:
//: foreach my $i (0..${k}-1) {
//: print qq(
//: NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_$i (
//: .cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i
//: ,.cfg_lut_le_function (cfg_lut_le_function) //|< i
//: ,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i
//: ,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i
//: ,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i
//: ,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i
//: ,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i
//: ,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i
//: ,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i
//: ,.lut_data_in (lut_data_in${i}[31:0]) //|< w
//: ,.lut_in_pvld (chn_lut_in_pvld) //|< i
//: ,.lut_out_prdy (chn_lut_out_prdy) //|< i
//: ,.nvdla_core_clk (nvdla_core_clk) //|< i
//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: ,.lut_in_prdy (chn_lut_in_prdy${i}) //|> w
//: ,.lut_out_frac (lut_out_fraction${i}[34:0]) //|> w
//: ,.lut_out_le_hit (lut_out_le_hit${i}) //|> w
//: ,.lut_out_lo_hit (lut_out_lo_hit${i}) //|> w
//: ,.lut_out_oflow (lut_out_oflow${i}) //|> w
//: ,.lut_out_pvld (chn_lut_out_pvld${i}) //|> w
//: ,.lut_out_ram_addr (lut_out_addr${i}[8:0]) //|> w
//: ,.lut_out_ram_sel (lut_out_sel${i}) //|> w
//: ,.lut_out_uflow (lut_out_uflow${i}) //|> w
//: ,.lut_out_x (lut_out_x${i}[31:0]) //|> w
//: );
//: );
//: }
//:
//:
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[35*${i}+34:35*${i}] = lut_out_fraction${i}[34:0]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[32*${i}+31+${bx}:32*${i}+${bx}] = lut_out_x${i}[31:0]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[${i}+${bof}] = lut_out_oflow${i} ; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[${i}+${buf}] = lut_out_uflow${i} ; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[${i}+${bsl}] = lut_out_sel${i} ; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[9*${i}+8+${ba}:9*${i}+${ba}] = lut_out_addr${i}[8:0]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[${i}+${beh}] = lut_out_le_hit${i} ; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign chn_lut_out_pd[${i}+${boh}] = lut_out_lo_hit${i} ; \n";
//: }
//:
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire chn_lut_in_prdy0;
wire chn_lut_out_pvld0;
wire [31:0] lut_data_in0;
wire [8:0] lut_out_addr0;
wire [34:0] lut_out_fraction0;
wire lut_out_le_hit0;
wire lut_out_lo_hit0;
wire lut_out_oflow0;
wire lut_out_sel0;
wire lut_out_uflow0;
wire [31:0] lut_out_x0;
wire chn_lut_in_prdy1;
wire chn_lut_out_pvld1;
wire [31:0] lut_data_in1;
wire [8:0] lut_out_addr1;
wire [34:0] lut_out_fraction1;
wire lut_out_le_hit1;
wire lut_out_lo_hit1;
wire lut_out_oflow1;
wire lut_out_sel1;
wire lut_out_uflow1;
wire [31:0] lut_out_x1;
wire chn_lut_in_prdy2;
wire chn_lut_out_pvld2;
wire [31:0] lut_data_in2;
wire [8:0] lut_out_addr2;
wire [34:0] lut_out_fraction2;
wire lut_out_le_hit2;
wire lut_out_lo_hit2;
wire lut_out_oflow2;
wire lut_out_sel2;
wire lut_out_uflow2;
wire [31:0] lut_out_x2;
wire chn_lut_in_prdy3;
wire chn_lut_out_pvld3;
wire [31:0] lut_data_in3;
wire [8:0] lut_out_addr3;
wire [34:0] lut_out_fraction3;
wire lut_out_le_hit3;
wire lut_out_lo_hit3;
wire lut_out_oflow3;
wire lut_out_sel3;
wire lut_out_uflow3;
wire [31:0] lut_out_x3;
assign lut_data_in0 = chn_lut_in_pd[32*0+31:32*0];
assign lut_data_in1 = chn_lut_in_pd[32*1+31:32*1];
assign lut_data_in2 = chn_lut_in_pd[32*2+31:32*2];
assign lut_data_in3 = chn_lut_in_pd[32*3+31:32*3];
NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_0 (
.cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i
,.cfg_lut_le_function (cfg_lut_le_function) //|< i
,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i
,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i
,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i
,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i
,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i
,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i
,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i
,.lut_data_in (lut_data_in0[31:0]) //|< w
,.lut_in_pvld (chn_lut_in_pvld) //|< i
,.lut_out_prdy (chn_lut_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.lut_in_prdy (chn_lut_in_prdy0) //|> w
,.lut_out_frac (lut_out_fraction0[34:0]) //|> w
,.lut_out_le_hit (lut_out_le_hit0) //|> w
,.lut_out_lo_hit (lut_out_lo_hit0) //|> w
,.lut_out_oflow (lut_out_oflow0) //|> w
,.lut_out_pvld (chn_lut_out_pvld0) //|> w
,.lut_out_ram_addr (lut_out_addr0[8:0]) //|> w
,.lut_out_ram_sel (lut_out_sel0) //|> w
,.lut_out_uflow (lut_out_uflow0) //|> w
,.lut_out_x (lut_out_x0[31:0]) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_1 (
.cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i
,.cfg_lut_le_function (cfg_lut_le_function) //|< i
,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i
,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i
,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i
,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i
,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i
,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i
,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i
,.lut_data_in (lut_data_in1[31:0]) //|< w
,.lut_in_pvld (chn_lut_in_pvld) //|< i
,.lut_out_prdy (chn_lut_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.lut_in_prdy (chn_lut_in_prdy1) //|> w
,.lut_out_frac (lut_out_fraction1[34:0]) //|> w
,.lut_out_le_hit (lut_out_le_hit1) //|> w
,.lut_out_lo_hit (lut_out_lo_hit1) //|> w
,.lut_out_oflow (lut_out_oflow1) //|> w
,.lut_out_pvld (chn_lut_out_pvld1) //|> w
,.lut_out_ram_addr (lut_out_addr1[8:0]) //|> w
,.lut_out_ram_sel (lut_out_sel1) //|> w
,.lut_out_uflow (lut_out_uflow1) //|> w
,.lut_out_x (lut_out_x1[31:0]) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_2 (
.cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i
,.cfg_lut_le_function (cfg_lut_le_function) //|< i
,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i
,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i
,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i
,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i
,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i
,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i
,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i
,.lut_data_in (lut_data_in2[31:0]) //|< w
,.lut_in_pvld (chn_lut_in_pvld) //|< i
,.lut_out_prdy (chn_lut_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.lut_in_prdy (chn_lut_in_prdy2) //|> w
,.lut_out_frac (lut_out_fraction2[34:0]) //|> w
,.lut_out_le_hit (lut_out_le_hit2) //|> w
,.lut_out_lo_hit (lut_out_lo_hit2) //|> w
,.lut_out_oflow (lut_out_oflow2) //|> w
,.lut_out_pvld (chn_lut_out_pvld2) //|> w
,.lut_out_ram_addr (lut_out_addr2[8:0]) //|> w
,.lut_out_ram_sel (lut_out_sel2) //|> w
,.lut_out_uflow (lut_out_uflow2) //|> w
,.lut_out_x (lut_out_x2[31:0]) //|> w
);
NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_3 (
.cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i
,.cfg_lut_le_function (cfg_lut_le_function) //|< i
,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i
,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i
,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i
,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i
,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i
,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i
,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i
,.lut_data_in (lut_data_in3[31:0]) //|< w
,.lut_in_pvld (chn_lut_in_pvld) //|< i
,.lut_out_prdy (chn_lut_out_prdy) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.lut_in_prdy (chn_lut_in_prdy3) //|> w
,.lut_out_frac (lut_out_fraction3[34:0]) //|> w
,.lut_out_le_hit (lut_out_le_hit3) //|> w
,.lut_out_lo_hit (lut_out_lo_hit3) //|> w
,.lut_out_oflow (lut_out_oflow3) //|> w
,.lut_out_pvld (chn_lut_out_pvld3) //|> w
,.lut_out_ram_addr (lut_out_addr3[8:0]) //|> w
,.lut_out_ram_sel (lut_out_sel3) //|> w
,.lut_out_uflow (lut_out_uflow3) //|> w
,.lut_out_x (lut_out_x3[31:0]) //|> w
);
assign chn_lut_out_pd[35*0+34:35*0] = lut_out_fraction0[34:0];
assign chn_lut_out_pd[35*1+34:35*1] = lut_out_fraction1[34:0];
assign chn_lut_out_pd[35*2+34:35*2] = lut_out_fraction2[34:0];
assign chn_lut_out_pd[35*3+34:35*3] = lut_out_fraction3[34:0];
assign chn_lut_out_pd[32*0+31+140:32*0+140] = lut_out_x0[31:0];
assign chn_lut_out_pd[32*1+31+140:32*1+140] = lut_out_x1[31:0];
assign chn_lut_out_pd[32*2+31+140:32*2+140] = lut_out_x2[31:0];
assign chn_lut_out_pd[32*3+31+140:32*3+140] = lut_out_x3[31:0];
assign chn_lut_out_pd[0+268] = lut_out_oflow0 ;
assign chn_lut_out_pd[1+268] = lut_out_oflow1 ;
assign chn_lut_out_pd[2+268] = lut_out_oflow2 ;
assign chn_lut_out_pd[3+268] = lut_out_oflow3 ;
assign chn_lut_out_pd[0+272] = lut_out_uflow0 ;
assign chn_lut_out_pd[1+272] = lut_out_uflow1 ;
assign chn_lut_out_pd[2+272] = lut_out_uflow2 ;
assign chn_lut_out_pd[3+272] = lut_out_uflow3 ;
assign chn_lut_out_pd[0+276] = lut_out_sel0 ;
assign chn_lut_out_pd[1+276] = lut_out_sel1 ;
assign chn_lut_out_pd[2+276] = lut_out_sel2 ;
assign chn_lut_out_pd[3+276] = lut_out_sel3 ;
assign chn_lut_out_pd[9*0+8+280:9*0+280] = lut_out_addr0[8:0];
assign chn_lut_out_pd[9*1+8+280:9*1+280] = lut_out_addr1[8:0];
assign chn_lut_out_pd[9*2+8+280:9*2+280] = lut_out_addr2[8:0];
assign chn_lut_out_pd[9*3+8+280:9*3+280] = lut_out_addr3[8:0];
assign chn_lut_out_pd[0+316] = lut_out_le_hit0 ;
assign chn_lut_out_pd[1+316] = lut_out_le_hit1 ;
assign chn_lut_out_pd[2+316] = lut_out_le_hit2 ;
assign chn_lut_out_pd[3+316] = lut_out_le_hit3 ;
assign chn_lut_out_pd[0+320] = lut_out_lo_hit0 ;
assign chn_lut_out_pd[1+320] = lut_out_lo_hit1 ;
assign chn_lut_out_pd[2+320] = lut_out_lo_hit2 ;
assign chn_lut_out_pd[3+320] = lut_out_lo_hit3 ;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign chn_lut_in_prdy = chn_lut_in_prdy0;
assign chn_lut_out_pvld = chn_lut_out_pvld0;
endmodule // NV_NVDLA_SDP_HLS_Y_idx_top |
module NV_BLKBOX_SINK (
A,B
);
input A ;
output B;
assign B = 1'b0;
endmodule |
module NV_NVDLA_GLB_CSB_reg (
reg_rd_data
,reg_offset
// verilint 498 off
// leda UNUSED_DEC off
,reg_wr_data
// verilint 498 on
// leda UNUSED_DEC on
,reg_wr_en
,nvdla_core_clk
,nvdla_core_rstn
,bdma_done_mask0
,bdma_done_mask1
,cacc_done_mask0
,cacc_done_mask1
,cdma_dat_done_mask0
,cdma_dat_done_mask1
,cdma_wt_done_mask0
,cdma_wt_done_mask1
,cdp_done_mask0
,cdp_done_mask1
,pdp_done_mask0
,pdp_done_mask1
,rubik_done_mask0
,rubik_done_mask1
,sdp_done_mask0
,sdp_done_mask1
,sdp_done_set0_trigger
,sdp_done_status0_trigger
,bdma_done_set0
,bdma_done_set1
,cacc_done_set0
,cacc_done_set1
,cdma_dat_done_set0
,cdma_dat_done_set1
,cdma_wt_done_set0
,cdma_wt_done_set1
,cdp_done_set0
,cdp_done_set1
,pdp_done_set0
,pdp_done_set1
,rubik_done_set0
,rubik_done_set1
,sdp_done_set0
,sdp_done_set1
,bdma_done_status0
,bdma_done_status1
,cacc_done_status0
,cacc_done_status1
,cdma_dat_done_status0
,cdma_dat_done_status1
,cdma_wt_done_status0
,cdma_wt_done_status1
,cdp_done_status0
,cdp_done_status1
,pdp_done_status0
,pdp_done_status1
,rubik_done_status0
,rubik_done_status1
,sdp_done_status0
,sdp_done_status1
,csb2nvdla_write
,cdma_op_en // modified by jiazhaorong
);
wire [7:0] major;
wire [15:0] minor;
wire [31:0] nvdla_glb_s_intr_mask_0_out;
wire [31:0] nvdla_glb_s_intr_set_0_out;
wire [31:0] nvdla_glb_s_intr_status_0_out;
wire [31:0] nvdla_glb_s_sdp_per_counter_0_out ;
wire [31:0] nvdla_glb_s_cdp_per_counter_0_out ;
wire [31:0] nvdla_glb_s_pdp_per_counter_0_out ;
wire [31:0] nvdla_glb_s_cdma_dat_counter_0_out ;
wire [31:0] nvdla_glb_s_cdma_op_en_counter_0_out ;
wire [31:0] nvdla_glb_s_cdma_wt_counter_0_out ;
wire [31:0] nvdla_glb_s_cacc_per_counter_0_out ;
wire [31:0] nvdla_glb_s_csb_per_counter_0_out ;
wire [31:0] nvdla_glb_s_bdma_per_counter_0_out ;
wire [31:0] nvdla_glb_s_nvdla_hw_version_0_out;
wire [11:0] reg_offset_rd_int;
wire [31:0] reg_offset_wr;
// Register control interface
output [31:0] reg_rd_data;
input [11:0] reg_offset;
input [31:0] reg_wr_data; //(UNUSED_DEC)
input reg_wr_en;
input nvdla_core_clk;
input nvdla_core_rstn;
// Writable register flop/trigger outputs
output bdma_done_mask0;
output bdma_done_mask1;
output cacc_done_mask0;
output cacc_done_mask1;
output cdma_dat_done_mask0;
output cdma_dat_done_mask1;
output cdma_wt_done_mask0;
output cdma_wt_done_mask1;
output cdp_done_mask0;
output cdp_done_mask1;
output pdp_done_mask0;
output pdp_done_mask1;
output rubik_done_mask0;
output rubik_done_mask1;
output sdp_done_mask0;
output sdp_done_mask1;
output sdp_done_set0_trigger;
output sdp_done_status0_trigger;
// Read-only register inputs
input bdma_done_set0;
input bdma_done_set1;
input cacc_done_set0;
input cacc_done_set1;
input cdma_dat_done_set0;
input cdma_dat_done_set1;
input cdma_wt_done_set0;
input cdma_wt_done_set1;
input cdp_done_set0;
input cdp_done_set1;
input pdp_done_set0;
input pdp_done_set1;
input rubik_done_set0;
input rubik_done_set1;
input sdp_done_set0;
input sdp_done_set1;
input bdma_done_status0;
input bdma_done_status1;
input cacc_done_status0;
input cacc_done_status1;
input cdma_dat_done_status0;
input cdma_dat_done_status1;
input cdma_wt_done_status0;
input cdma_wt_done_status1;
input cdp_done_status0;
input cdp_done_status1;
input pdp_done_status0;
input pdp_done_status1;
input rubik_done_status0;
input rubik_done_status1;
input sdp_done_status0;
input sdp_done_status1;
input csb2nvdla_write;
input cdma_op_en; //modified by jiazhaorong
// wr_mask register inputs
// rstn register inputs
// leda FM_2_23 off
reg arreggen_abort_on_invalid_wr;
reg arreggen_abort_on_rowr;
reg arreggen_dump;
// leda FM_2_23 on
reg bdma_done_mask0;
reg bdma_done_mask1;
reg cacc_done_mask0;
reg cacc_done_mask1;
reg cdma_dat_done_mask0;
reg cdma_dat_done_mask1;
reg cdma_wt_done_mask0;
reg cdma_wt_done_mask1;
reg cdp_done_mask0;
reg cdp_done_mask1;
reg pdp_done_mask0;
reg pdp_done_mask1;
reg [31:0] reg_rd_data;
reg rubik_done_mask0;
reg rubik_done_mask1;
reg sdp_done_mask0;
reg sdp_done_mask1;
reg [31:0] sdp_per_counter ;
reg [31:0] cdp_per_counter ;
reg [31:0] pdp_per_counter ;
reg [31:0] cdma_dat_counter ;
reg [31:0] cdma_wt_counter ;
reg [31:0] cacc_per_counter ;
reg [31:0] csb_per_counter, csb_per_counter_temp;
reg [31:0] bdma_per_counter ;
reg [31:0] cdma_op_en_counter;// used for test cdma_op_en start time
reg cdma_op_en_temp;
assign reg_offset_wr = {20'b0 , reg_offset};
wire core_intr_w;
// SCR signals
// Address decode
wire nvdla_glb_s_intr_mask_0_wren = (reg_offset_wr == (32'h4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_intr_set_0_wren = (reg_offset_wr == (32'h8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_intr_status_0_wren = (reg_offset_wr == (32'hc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_sdp_per_counter_0_wren = (reg_offset_wr == (32'h10 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_cdp_per_counter_0_wren = (reg_offset_wr == (32'h14 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_pdp_per_counter_0_wren = (reg_offset_wr == (32'h18 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_cdma_dat_counter_0_wren = (reg_offset_wr == (32'h1c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_cdma_wt_counter_0_wren = (reg_offset_wr == (32'h20 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_cacc_per_counter_0_wren = (reg_offset_wr == (32'h24 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_csb_per_counter_0_wren = (reg_offset_wr == (32'h28 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_bdma_per_counter_0_wren = (reg_offset_wr == (32'h2c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
wire nvdla_glb_s_nvdla_hw_version_0_wren = (reg_offset_wr == (32'h0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528)
assign major = 8'h31;
assign minor = 16'h3030;
assign nvdla_glb_s_intr_mask_0_out[31:0] = { 10'b0, cacc_done_mask1, cacc_done_mask0, cdma_wt_done_mask1, cdma_wt_done_mask0, cdma_dat_done_mask1, cdma_dat_done_mask0, 6'b0, rubik_done_mask1, rubik_done_mask0, bdma_done_mask1, bdma_done_mask0, pdp_done_mask1, pdp_done_mask0, cdp_done_mask1, cdp_done_mask0, sdp_done_mask1, sdp_done_mask0 };
assign nvdla_glb_s_intr_set_0_out[31:0] = { 10'b0, cacc_done_set1, cacc_done_set0, cdma_wt_done_set1, cdma_wt_done_set0, cdma_dat_done_set1, cdma_dat_done_set0, 6'b0, rubik_done_set1, rubik_done_set0, bdma_done_set1, bdma_done_set0, pdp_done_set1, pdp_done_set0, cdp_done_set1, cdp_done_set0, sdp_done_set1, sdp_done_set0 };
assign nvdla_glb_s_intr_status_0_out[31:0] = { 10'b0, cacc_done_status1, cacc_done_status0, cdma_wt_done_status1, cdma_wt_done_status0, cdma_dat_done_status1, cdma_dat_done_status0, 6'b0, rubik_done_status1, rubik_done_status0, bdma_done_status1, bdma_done_status0, pdp_done_status1, pdp_done_status0, cdp_done_status1, cdp_done_status0, sdp_done_status1, sdp_done_status0 };
assign nvdla_glb_s_sdp_per_counter_0_out = {sdp_per_counter };
assign nvdla_glb_s_cdp_per_counter_0_out = {cdp_per_counter };
assign nvdla_glb_s_pdp_per_counter_0_out = {pdp_per_counter };
assign nvdla_glb_s_cdma_dat_counter_0_out = {cdma_dat_counter};
assign nvdla_glb_s_cdma_wt_counter_0_out = {cdma_wt_counter };
assign nvdla_glb_s_cdma_op_en_counter_0_out = {cdma_op_en_counter };
assign nvdla_glb_s_cacc_per_counter_0_out = {cacc_per_counter};
assign nvdla_glb_s_csb_per_counter_0_out = {csb_per_counter };
assign nvdla_glb_s_bdma_per_counter_0_out = {bdma_per_counter };
assign nvdla_glb_s_nvdla_hw_version_0_out[31:0] = { 8'b0, minor, major };
assign sdp_done_set0_trigger = nvdla_glb_s_intr_set_0_wren; //(W563)
assign sdp_done_status0_trigger = nvdla_glb_s_intr_status_0_wren; //(W563)
assign reg_offset_rd_int = reg_offset;
// Output mux
//spyglass disable_block W338, W263
always @(
reg_offset_rd_int
or nvdla_glb_s_intr_mask_0_out
or nvdla_glb_s_intr_set_0_out
or nvdla_glb_s_intr_status_0_out
or nvdla_glb_s_nvdla_hw_version_0_out
or nvdla_glb_s_sdp_per_counter_0_out
or nvdla_glb_s_cdp_per_counter_0_out
or nvdla_glb_s_pdp_per_counter_0_out
or nvdla_glb_s_cdma_dat_counter_0_out
or nvdla_glb_s_cdma_wt_counter_0_out
or nvdla_glb_s_cacc_per_counter_0_out
or nvdla_glb_s_csb_per_counter_0_out
or nvdla_glb_s_bdma_per_counter_0_out
or nvdla_glb_s_cdma_op_en_counter_0_out
) begin
case (reg_offset_rd_int)
(32'h4 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_intr_mask_0_out ;
end
(32'h8 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_intr_set_0_out ;
end
(32'hc & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_intr_status_0_out ;
end
(32'h10 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_sdp_per_counter_0_out ;
end
(32'h14 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_cdp_per_counter_0_out ;
end
(32'h18 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_pdp_per_counter_0_out ;
end
(32'h1c & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_cdma_dat_counter_0_out ;
end
(32'h20 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_cdma_wt_counter_0_out ;
end
(32'h24 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_cacc_per_counter_0_out ;
end
(32'h28 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_csb_per_counter_0_out ;
end
(32'h2c & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_bdma_per_counter_0_out ;
end
(32'h30 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_cdma_op_en_counter_0_out ;
end
(32'h0 & 32'h00000fff): begin
reg_rd_data = nvdla_glb_s_nvdla_hw_version_0_out ;
end
default: reg_rd_data = {32{1'b0}};
endcase
end
//spyglass enable_block W338, W263
// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443
// Register flop declarations
assign core_intr_w = (~sdp_done_mask0 & sdp_done_status0) |
(~sdp_done_mask1 & sdp_done_status1) |
(~cdp_done_mask0 & cdp_done_status0) |
(~cdp_done_mask1 & cdp_done_status1) |
(~pdp_done_mask0 & pdp_done_status0) |
(~pdp_done_mask1 & pdp_done_status1) ;
// (~cdma_dat_done_mask0 & cdma_dat_done_status0) |
// (~cdma_dat_done_mask1 & cdma_dat_done_status1) |
// (~cdma_wt_done_mask0 & cdma_wt_done_status0) |
// (~cdma_wt_done_mask1 & cdma_wt_done_status1) |
// (~bdma_done_mask0 & bdma_done_status0) |
// (~bdma_done_mask1 & bdma_done_status1) |
// (~cacc_done_mask0 & cacc_done_status0) |
// (~cacc_done_mask1 & cacc_done_status1)
//;
reg csb2nvdla_write_temp;
reg [7:0] us_timer;
reg timer_en, timer_en_temp;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
csb2nvdla_write_temp <= 1'b0;
us_timer <= 8'b0;
timer_en <= 1'b0;
timer_en_temp <= 1'b0;
end else begin
csb2nvdla_write_temp <= csb2nvdla_write;
timer_en_temp <= timer_en;
if(csb2nvdla_write &(~csb2nvdla_write_temp))
timer_en <= 1'b1;
else if(core_intr_w)
timer_en <= 1'b0;
if((us_timer >= 8'b0110_0011) || (timer_en == 1'b0))
us_timer <= 8'b0;
else
us_timer <= us_timer + 1'b1;
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
sdp_per_counter <= 32'b0;
cdp_per_counter <= 32'b0;
pdp_per_counter <= 32'b0;
cdma_dat_counter <= 32'b0;
cdma_wt_counter <= 32'b0;
cacc_per_counter <= 32'b0;
bdma_per_counter <= 32'b0;
csb_per_counter <= 32'b0;
csb_per_counter_temp <= 32'b0;
cdma_op_en_counter <= 32'b0;
cdma_op_en_temp <= 1'b0;
end else begin
cdma_op_en_temp <= cdma_op_en;
if((~timer_en_temp ) & timer_en) begin
sdp_per_counter <= 32'b0;
cdp_per_counter <= 32'b0;
pdp_per_counter <= 32'b0;
cdma_dat_counter <= 32'b0;
cdma_wt_counter <= 32'b0;
cacc_per_counter <= 32'b0;
bdma_per_counter <= 32'b0;
csb_per_counter <= 32'b0;
csb_per_counter_temp <= 32'b0;
cdma_op_en_counter <= 32'b0;
end else if((timer_en == 1'b1) && (us_timer >= 8'b0110_0011))begin
csb_per_counter_temp <= csb_per_counter_temp + 1'b1;
if((!sdp_done_status0) & (!sdp_done_status1))
sdp_per_counter[30:0] <= sdp_per_counter[30:0]+ 1'b1;
if((!cdp_done_status0) & (!cdp_done_status1))
cdp_per_counter[30:0] <= cdp_per_counter[30:0]+ 1'b1;
if((!pdp_done_status0) & (!pdp_done_status1))
pdp_per_counter[30:0] <= pdp_per_counter[30:0]+ 1'b1;
if((!cdma_dat_done_status0) & (!cdma_dat_done_status1))
cdma_dat_counter[30:0]<= cdma_dat_counter[30:0]+ 1'b1;
if((!cdma_wt_done_status0) & (!cdma_wt_done_status1))
cdma_wt_counter[30:0] <= cdma_wt_counter[30:0]+ 1'b1;
if((!cacc_done_status0) & (!cacc_done_status1))
cacc_per_counter[30:0]<= cacc_per_counter[30:0]+ 1'b1;
if((!bdma_done_status0) & (!bdma_done_status1))
bdma_per_counter[30:0]<= bdma_per_counter[30:0]+ 1'b1;
end
if(csb2nvdla_write_temp &(~csb2nvdla_write))begin
csb_per_counter <= csb_per_counter_temp;
end
if(cdma_op_en & (~cdma_op_en_temp)) begin
cdma_op_en_counter <= csb_per_counter_temp;
end
if(core_intr_w) begin
if(sdp_done_status0 | sdp_done_status1)
sdp_per_counter[31:31] <= 1'b1;
else
sdp_per_counter[31:31] <= 1'b0;
if(cdp_done_status0 | cdp_done_status1)
cdp_per_counter[31:31] <= 1'b1;
else
cdp_per_counter[31:31] <= 1'b0;
if(pdp_done_status0 | pdp_done_status1)
pdp_per_counter[31:31] <= 1'b1;
else
pdp_per_counter[31:31] <= 1'b0;
if(cdma_dat_done_status0 | cdma_dat_done_status1)
cdma_dat_counter[31:31] <= 1'b1;
else
cdma_dat_counter[31:31] <= 1'b0;
if(cdma_wt_done_status0 | cdma_wt_done_status1)
cdma_wt_counter[31:31] <= 1'b1;
else
cdma_wt_counter[31:31] <= 1'b0;
if(cacc_done_status0 | cacc_done_status1)
cacc_per_counter[31:31] <= 1'b1;
else
cacc_per_counter[31:31] <= 1'b0;
if(bdma_done_status0 | bdma_done_status1)
bdma_per_counter[31:31] <= 1'b1;
else
bdma_per_counter[31:31] <= 1'b0;
end
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
bdma_done_mask0 <= 1'b0;
bdma_done_mask1 <= 1'b0;
cacc_done_mask0 <= 1'b0;
cacc_done_mask1 <= 1'b0;
cdma_dat_done_mask0 <= 1'b0;
cdma_dat_done_mask1 <= 1'b0;
cdma_wt_done_mask0 <= 1'b0;
cdma_wt_done_mask1 <= 1'b0;
cdp_done_mask0 <= 1'b0;
cdp_done_mask1 <= 1'b0;
pdp_done_mask0 <= 1'b0;
pdp_done_mask1 <= 1'b0;
rubik_done_mask0 <= 1'b0;
rubik_done_mask1 <= 1'b0;
sdp_done_mask0 <= 1'b0;
sdp_done_mask1 <= 1'b0;
end else begin
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: bdma_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
bdma_done_mask0 <= reg_wr_data[6];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: bdma_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
bdma_done_mask1 <= reg_wr_data[7];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
cacc_done_mask0 <= reg_wr_data[20];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
cacc_done_mask1 <= reg_wr_data[21];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
cdma_dat_done_mask0 <= reg_wr_data[16];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
cdma_dat_done_mask1 <= reg_wr_data[17];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
cdma_wt_done_mask0 <= reg_wr_data[18];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
cdma_wt_done_mask1 <= reg_wr_data[19];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
cdp_done_mask0 <= reg_wr_data[2];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
cdp_done_mask1 <= reg_wr_data[3];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
pdp_done_mask0 <= reg_wr_data[4];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
pdp_done_mask1 <= reg_wr_data[5];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: rubik_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
rubik_done_mask0 <= reg_wr_data[8];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: rubik_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
rubik_done_mask1 <= reg_wr_data[9];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask0
if (nvdla_glb_s_intr_mask_0_wren) begin
sdp_done_mask0 <= reg_wr_data[0];
end
// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask1
if (nvdla_glb_s_intr_mask_0_wren) begin
sdp_done_mask1 <= reg_wr_data[1];
end
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status1 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status0 (to be implemented outside)
// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status1 (to be implemented outside)
// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::major
// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::minor
end
end
// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443
// synopsys translate_off
// VCS coverage off
initial begin
arreggen_dump = $test$plusargs("arreggen_dump_wr");
arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr");
arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr");
`ifdef VERILATOR
`else
$timeformat(-9, 2, "ns", 15);
`endif
end
always @(posedge nvdla_core_clk) begin
if (reg_wr_en) begin
case(reg_offset)
(32'h4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_MASK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_mask_0_out, nvdla_glb_s_intr_mask_0_out);
(32'h8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_SET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_set_0_out, nvdla_glb_s_intr_set_0_out);
(32'hc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_STATUS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_status_0_out, nvdla_glb_s_intr_status_0_out);
(32'h0 & 32'h00000fff): begin
if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_GLB_S_NVDLA_HW_VERSION_0 = 0x%h", $time, reg_wr_data);
if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end
end
default: begin
if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data);
if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end
end
endcase
end
end
// VCS coverage on
// synopsys translate_on
endmodule // NV_NVDLA_GLB_CSB_reg |
module NV_NVDLA_cdp (
dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
,tmc2slcg_disable_clock_gating //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,cdp2csb_resp_valid //|> o
,cdp2csb_resp_pd //|> o
,cdp2cvif_rd_cdt_lat_fifo_pop //|> o
,cdp2cvif_rd_req_valid //|> o
,cdp2cvif_rd_req_ready //|< i
,cdp2cvif_rd_req_pd //|> o
,cdp2cvif_wr_req_valid //|> o
,cdp2cvif_wr_req_ready //|< i
,cdp2cvif_wr_req_pd //|> o
,cdp2glb_done_intr_pd //|> o
,cdp2mcif_rd_cdt_lat_fifo_pop //|> o
,cdp2mcif_rd_req_valid //|> o
,cdp2mcif_rd_req_ready //|< i
,cdp2mcif_rd_req_pd //|> o
,cdp2mcif_wr_req_valid //|> o
,cdp2mcif_wr_req_ready //|< i
,cdp2mcif_wr_req_pd //|> o
,cdp_rdma2csb_resp_valid //|> o
,cdp_rdma2csb_resp_pd //|> o
,csb2cdp_rdma_req_pvld //|< i
,csb2cdp_rdma_req_prdy //|> o
,csb2cdp_rdma_req_pd //|< i
,csb2cdp_req_pvld //|< i
,csb2cdp_req_prdy //|> o
,csb2cdp_req_pd //|< i
,cvif2cdp_rd_rsp_valid //|< i
,cvif2cdp_rd_rsp_ready //|> o
,cvif2cdp_rd_rsp_pd //|< i
,cvif2cdp_wr_rsp_complete //|< i
,mcif2cdp_rd_rsp_valid //|< i
,mcif2cdp_rd_rsp_ready //|> o
,mcif2cdp_rd_rsp_pd //|< i
,mcif2cdp_wr_rsp_complete //|< i
,pwrbus_ram_pd //|< i
);
//////////////////////////////////////////////////////////////////
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
//
// NV_NVDLA_cdp_ports.v
//
input nvdla_core_clk;
input nvdla_core_rstn;
output cdp2csb_resp_valid; /* data valid */
output [33:0] cdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
output cdp2cvif_rd_cdt_lat_fifo_pop;
output cdp2cvif_rd_req_valid; /* data valid */
input cdp2cvif_rd_req_ready; /* data return handshake */
output [79 -1:0] cdp2cvif_rd_req_pd;
output cdp2cvif_wr_req_valid; /* data valid */
input cdp2cvif_wr_req_ready; /* data return handshake */
output [258 -1:0] cdp2cvif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */
output [1:0] cdp2glb_done_intr_pd;
output cdp2mcif_rd_cdt_lat_fifo_pop;
output cdp2mcif_rd_req_valid; /* data valid */
input cdp2mcif_rd_req_ready; /* data return handshake */
output [79 -1:0] cdp2mcif_rd_req_pd;
output cdp2mcif_wr_req_valid; /* data valid */
input cdp2mcif_wr_req_ready; /* data return handshake */
output [258 -1:0] cdp2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */
output cdp_rdma2csb_resp_valid; /* data valid */
output [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
input csb2cdp_rdma_req_pvld; /* data valid */
output csb2cdp_rdma_req_prdy; /* data return handshake */
input [62:0] csb2cdp_rdma_req_pd;
input csb2cdp_req_pvld; /* data valid */
output csb2cdp_req_prdy; /* data return handshake */
input [62:0] csb2cdp_req_pd;
input cvif2cdp_rd_rsp_valid; /* data valid */
output cvif2cdp_rd_rsp_ready; /* data return handshake */
input [257 -1:0] cvif2cdp_rd_rsp_pd;
input cvif2cdp_wr_rsp_complete;
input mcif2cdp_rd_rsp_valid; /* data valid */
output mcif2cdp_rd_rsp_ready; /* data return handshake */
input [257 -1:0] mcif2cdp_rd_rsp_pd;
input mcif2cdp_wr_rsp_complete;
input [31:0] pwrbus_ram_pd;
//
//
//////////////////////////////////////////////////////////////////
assign csb2cdp_req_prdy = 1'b1; /* data return handshake */
assign cdp2csb_resp_valid = 1'b0; /* data valid */
assign cdp2csb_resp_pd = 34'd0; /* pkt_id_width=1 pkt_widths=33,33 */
assign csb2cdp_rdma_req_prdy = 1'b1; /* data return handshake */
assign cdp_rdma2csb_resp_valid = 1'd0; /* data valid */
assign cdp_rdma2csb_resp_pd = 34'd0; /* pkt_id_width=1 pkt_widths=33,33 */
assign cvif2cdp_rd_rsp_ready = 1'b1; /* data return handshake */
assign cdp2cvif_rd_cdt_lat_fifo_pop = 1'b0;
assign cdp2cvif_rd_req_valid = 1'b0; /* data valid */
assign cdp2cvif_rd_req_pd = 79'd0;
assign cdp2cvif_wr_req_valid = 1'd0; /* data valid */
assign cdp2cvif_wr_req_pd = 258'd0; /* pkt_id_width=1 pkt_widths=78,514 */
assign cdp2glb_done_intr_pd = 2'd0;
assign mcif2cdp_rd_rsp_ready = 1'b1; /* data return handshake */
assign cdp2mcif_rd_cdt_lat_fifo_pop = 1'b0;
assign cdp2mcif_rd_req_valid = 1'd0; /* data valid */
assign cdp2mcif_rd_req_pd = 79'd0;
assign cdp2mcif_wr_req_valid = 1'd0; /* data valid */
assign cdp2mcif_wr_req_pd = 258'd0; /* pkt_id_width=1 pkt_widths=78,514 */
//////////////////////////////////////////////////////////////////
//
//
endmodule // NV_NVDLA_cdp |
module NV_NVDLA_CACC_CALC_int8 (
nvdla_core_clk
,nvdla_core_rstn
,cfg_truncate
,in_data
,in_op
,in_op_valid
,in_sel
,in_valid
,out_final_data
,out_final_sat
,out_final_valid
,out_partial_data
,out_partial_valid
);
input [4:0] cfg_truncate;
input [21:0] in_data;
input [33:0] in_op;
input in_op_valid;
input in_sel;
input in_valid;
output [31:0] out_final_data;
output out_final_sat;
output out_final_valid;
output [33:0] out_partial_data;
output out_partial_valid;
input nvdla_core_clk;
input nvdla_core_rstn;
reg [32:0] i_sat_bits;
reg i_sat_sel;
reg i_sat_vld;
reg [34:0] i_sum_pd;
reg [31:0] out_final_data;
reg out_final_sat;
reg out_final_valid;
reg [33:0] out_partial_data;
reg out_partial_valid;
wire [21:0] di_pd;
wire [31:0] i_final_result;
wire i_final_vld;
wire i_guide;
wire [33:0] i_partial_result;
wire i_partial_vld;
wire i_point5;
wire [31:0] i_pos_pd;
wire [33:0] i_pre_sft_pd;
wire [33:0] i_sat_pd;
wire i_sat_sign;
wire i_sel;
wire [31:0] i_sft_max;
wire i_sft_need_sat;
wire [33:0] i_sft_pd;
wire [14:0] i_stick;
wire i_sum_msb;
wire [34:0] i_sum_pd_nxt;
wire i_sum_sign;
wire [31:0] i_tru_pd;
wire i_vld;
wire [33:0] in_mask_op;
wire mon_pos_pd_c;
wire [33:0] oi_pd;
assign i_sel = in_sel;
assign i_vld = in_valid;
assign in_mask_op = in_op_valid ? in_op[33:0] : 34'b0;
assign di_pd = in_data[21:0];
assign oi_pd = in_mask_op[33:0];
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
i_sat_vld <= 1'b0;
end else begin
i_sat_vld <= i_vld;
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
i_sat_sel <= 1'b0;
end else begin
if ((i_vld) == 1'b1) begin
i_sat_sel <= i_sel;
// VCS coverage off
end else if ((i_vld) == 1'b0) begin
// VCS coverage on
end
end
end
//====================
// Addition
//====================
assign i_sum_pd_nxt[34:0] = $signed(di_pd) + $signed(oi_pd);
always @(posedge nvdla_core_clk) begin
if ((i_vld) == 1'b1) begin
i_sum_pd <= i_sum_pd_nxt;
// VCS coverage off
end else if ((i_vld) == 1'b0) begin
// VCS coverage on
end
end
//====================
// narrow down to 34bit, and need satuation only
//====================
assign i_sum_sign = i_sum_pd[34 +1 -1];
assign i_sum_msb = i_sum_pd[34 +1 -2];
assign i_sat_sign = i_sum_sign;
always @(
i_sum_sign
or i_sum_msb
or i_sum_pd
) begin
if (i_sum_sign ^ i_sum_msb) begin // overflow, need satuation
i_sat_bits = {33{~i_sum_sign}};
end else begin
i_sat_bits = i_sum_pd[32:0];
end
end
assign i_sat_pd = {i_sat_sign,i_sat_bits};
assign i_partial_result = i_sat_pd;
//====================
// narrow down to 32bit, and need rounding and satuation
//====================
assign i_pre_sft_pd = i_sat_sel ? i_sat_pd[33:0] : {34{1'b0}};
assign {i_sft_pd[33:0], i_guide, i_stick[14:0]} = ($signed({i_pre_sft_pd, 16'b0}) >>> cfg_truncate);
assign i_sft_need_sat = (i_sat_sign & ~(&i_sft_pd[32:31])) |
(~i_sat_sign & (|i_sft_pd[32:31])) |
(~i_sat_sign & (&{i_sft_pd[30:0], i_point5}));
assign i_sft_max = i_sat_sign ? {1'b1, 31'b0} : ~{1'b1, 31'b0};
assign i_point5 = i_sat_sel & i_guide & (~i_sat_sign | (|i_stick));
assign {mon_pos_pd_c, i_pos_pd[31:0]} = i_sft_pd[31:0] + i_point5;
assign i_tru_pd = i_pos_pd;
assign i_final_result = i_sft_need_sat ? i_sft_max : i_tru_pd;
assign i_partial_vld = i_sat_vld & ~i_sat_sel;
assign i_final_vld = i_sat_vld & i_sat_sel;
//====================
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_partial_valid <= 1'b0;
end else begin
out_partial_valid <= i_partial_vld;
end
end
// spyglass disable_block STARC05-3.3.1.4b
always @(posedge nvdla_core_clk) begin
if ((i_partial_vld) == 1'b1) begin
out_partial_data <= i_partial_result;
// VCS coverage off
end else if ((i_partial_vld) == 1'b0) begin
// VCS coverage on
end
end
// spyglass enable_block STARC05-3.3.1.4b
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_final_valid <= 1'b0;
end else begin
out_final_valid <= i_final_vld;
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
out_final_sat <= 1'b0;
end else begin
out_final_sat <= i_final_vld & i_sft_need_sat;
end
end
// spyglass disable_block STARC05-3.3.1.4b
always @(posedge nvdla_core_clk) begin
if ((i_final_vld) == 1'b1) begin
out_final_data <= i_final_result;
// VCS coverage off
end else if ((i_final_vld) == 1'b0) begin
// VCS coverage on
end
end
// spyglass enable_block STARC05-3.3.1.4b
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
reg funcpoint_cover_off;
initial begin
if ( $test$plusargs( "cover_off" ) ) begin
funcpoint_cover_off = 1'b1;
end else begin
funcpoint_cover_off = 1'b0;
end
end
property cacc_calc_int8__partial_sum_need_sat__0_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
i_sum_sign ^ i_sum_msb;
endproperty
// Cover 0 : "i_sum_sign ^ i_sum_msb"
FUNCPOINT_cacc_calc_int8__partial_sum_need_sat__0_COV : cover property (cacc_calc_int8__partial_sum_need_sat__0_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property cacc_calc_int8__out32_need_sat_pos__1_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
i_sft_need_sat & ~i_sat_sign & ~i_point5;
endproperty
// Cover 1 : "i_sft_need_sat & ~i_sat_sign & ~i_point5"
FUNCPOINT_cacc_calc_int8__out32_need_sat_pos__1_COV : cover property (cacc_calc_int8__out32_need_sat_pos__1_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property cacc_calc_int8__out32_round_need_sat_pos__2_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
i_sft_need_sat & ~i_sat_sign & i_point5;
endproperty
// Cover 2 : "i_sft_need_sat & ~i_sat_sign & i_point5"
FUNCPOINT_cacc_calc_int8__out32_round_need_sat_pos__2_COV : cover property (cacc_calc_int8__out32_round_need_sat_pos__2_cov);
`endif
`endif
//VCS coverage on
//VCS coverage off
`ifndef DISABLE_FUNCPOINT
`ifdef ENABLE_FUNCPOINT
property cacc_calc_int8__out32_round_need_sat_neg__3_cov;
disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
@(posedge nvdla_core_clk)
i_sft_need_sat & i_sat_sign;
endproperty
// Cover 3 : "i_sft_need_sat & i_sat_sign"
FUNCPOINT_cacc_calc_int8__out32_round_need_sat_neg__3_COV : cover property (cacc_calc_int8__out32_round_need_sat_neg__3_cov);
`endif
`endif
//VCS coverage on
endmodule // NV_NVDLA_CACC_CALC_int8 |
module NV_NVDLA_SDP_HLS_c (
cfg_mode_eql
,cfg_offset
,cfg_out_precision
,cfg_scale
,cfg_truncate
,cvt_in_pvld
,cvt_out_prdy
,cvt_pd_in
,nvdla_core_clk
,nvdla_core_rstn
,cvt_in_prdy
,cvt_out_pvld
,cvt_pd_out
);
input cfg_mode_eql;
input [31:0] cfg_offset;
input [1:0] cfg_out_precision;
input [15:0] cfg_scale;
input [5:0] cfg_truncate;
input cvt_in_pvld;
input cvt_out_prdy;
input [32*16 -1:0] cvt_pd_in;
output cvt_in_prdy;
output cvt_out_pvld;
output [16*16 +16 -1:0] cvt_pd_out;
input nvdla_core_clk;
input nvdla_core_rstn;
wire [8*16 -1:0] cvt_pd_out8;
wire [16*16 -1:0] cvt_pd_out16;
//: my $b = 8;
//: my $dw = 16*16;
//: my $k=16;
//: foreach my $i (0..${k}-1) {
//: print qq(
//: wire [31:0] cvt_data_in_$i;
//: wire [15:0] cvt_data_out_$i;
//: wire cvt_in_prdy_$i;
//: wire cvt_out_pvld_$i;
//: wire cvt_sat_out_$i;
//: );
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_data_in_${i} = cvt_pd_in[32*${i}+31:32*${i}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_pd_out8[8*${i}+7:8*${i}] = cvt_data_out_${i}[7:0]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_pd_out16[16*${i}+15:16*${i}] = cvt_data_out_${i}; \n";
//: }
//: print "\n";
//: print "assign cvt_pd_out[${dw}-1:0] = cfg_out_precision[1:0]==2'b0 ? {{(8*$k){1'b0}},cvt_pd_out8[8*${k}-1:0]} : cvt_pd_out16[16*${k}-1:0]; \n";
//: foreach my $i (0..${k}-1) {
//: print "assign cvt_pd_out[${dw}+${i}] = cvt_sat_out_${i}; \n";
//: }
//: print "\n";
//: foreach my $i (0..${k}-1) {
//: print qq(
//: NV_NVDLA_SDP_HLS_C_int c_int_${i} (
//: .cfg_mode_eql (cfg_mode_eql)
//: ,.cfg_offset (cfg_offset[31:0])
//: ,.cfg_out_precision (cfg_out_precision[1:0])
//: ,.cfg_scale (cfg_scale[15:0])
//: ,.cfg_truncate (cfg_truncate[5:0])
//: ,.cvt_data_in (cvt_data_in_${i}[31:0])
//: ,.cvt_in_pvld (cvt_in_pvld)
//: ,.cvt_out_prdy (cvt_out_prdy)
//: ,.nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.cvt_data_out (cvt_data_out_${i}[15:0])
//: ,.cvt_in_prdy (cvt_in_prdy_${i})
//: ,.cvt_out_pvld (cvt_out_pvld_${i})
//: ,.cvt_sat_out (cvt_sat_out_${i})
//: );
//:
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [31:0] cvt_data_in_0;
wire [15:0] cvt_data_out_0;
wire cvt_in_prdy_0;
wire cvt_out_pvld_0;
wire cvt_sat_out_0;
wire [31:0] cvt_data_in_1;
wire [15:0] cvt_data_out_1;
wire cvt_in_prdy_1;
wire cvt_out_pvld_1;
wire cvt_sat_out_1;
wire [31:0] cvt_data_in_2;
wire [15:0] cvt_data_out_2;
wire cvt_in_prdy_2;
wire cvt_out_pvld_2;
wire cvt_sat_out_2;
wire [31:0] cvt_data_in_3;
wire [15:0] cvt_data_out_3;
wire cvt_in_prdy_3;
wire cvt_out_pvld_3;
wire cvt_sat_out_3;
wire [31:0] cvt_data_in_4;
wire [15:0] cvt_data_out_4;
wire cvt_in_prdy_4;
wire cvt_out_pvld_4;
wire cvt_sat_out_4;
wire [31:0] cvt_data_in_5;
wire [15:0] cvt_data_out_5;
wire cvt_in_prdy_5;
wire cvt_out_pvld_5;
wire cvt_sat_out_5;
wire [31:0] cvt_data_in_6;
wire [15:0] cvt_data_out_6;
wire cvt_in_prdy_6;
wire cvt_out_pvld_6;
wire cvt_sat_out_6;
wire [31:0] cvt_data_in_7;
wire [15:0] cvt_data_out_7;
wire cvt_in_prdy_7;
wire cvt_out_pvld_7;
wire cvt_sat_out_7;
wire [31:0] cvt_data_in_8;
wire [15:0] cvt_data_out_8;
wire cvt_in_prdy_8;
wire cvt_out_pvld_8;
wire cvt_sat_out_8;
wire [31:0] cvt_data_in_9;
wire [15:0] cvt_data_out_9;
wire cvt_in_prdy_9;
wire cvt_out_pvld_9;
wire cvt_sat_out_9;
wire [31:0] cvt_data_in_10;
wire [15:0] cvt_data_out_10;
wire cvt_in_prdy_10;
wire cvt_out_pvld_10;
wire cvt_sat_out_10;
wire [31:0] cvt_data_in_11;
wire [15:0] cvt_data_out_11;
wire cvt_in_prdy_11;
wire cvt_out_pvld_11;
wire cvt_sat_out_11;
wire [31:0] cvt_data_in_12;
wire [15:0] cvt_data_out_12;
wire cvt_in_prdy_12;
wire cvt_out_pvld_12;
wire cvt_sat_out_12;
wire [31:0] cvt_data_in_13;
wire [15:0] cvt_data_out_13;
wire cvt_in_prdy_13;
wire cvt_out_pvld_13;
wire cvt_sat_out_13;
wire [31:0] cvt_data_in_14;
wire [15:0] cvt_data_out_14;
wire cvt_in_prdy_14;
wire cvt_out_pvld_14;
wire cvt_sat_out_14;
wire [31:0] cvt_data_in_15;
wire [15:0] cvt_data_out_15;
wire cvt_in_prdy_15;
wire cvt_out_pvld_15;
wire cvt_sat_out_15;
assign cvt_data_in_0 = cvt_pd_in[32*0+31:32*0];
assign cvt_data_in_1 = cvt_pd_in[32*1+31:32*1];
assign cvt_data_in_2 = cvt_pd_in[32*2+31:32*2];
assign cvt_data_in_3 = cvt_pd_in[32*3+31:32*3];
assign cvt_data_in_4 = cvt_pd_in[32*4+31:32*4];
assign cvt_data_in_5 = cvt_pd_in[32*5+31:32*5];
assign cvt_data_in_6 = cvt_pd_in[32*6+31:32*6];
assign cvt_data_in_7 = cvt_pd_in[32*7+31:32*7];
assign cvt_data_in_8 = cvt_pd_in[32*8+31:32*8];
assign cvt_data_in_9 = cvt_pd_in[32*9+31:32*9];
assign cvt_data_in_10 = cvt_pd_in[32*10+31:32*10];
assign cvt_data_in_11 = cvt_pd_in[32*11+31:32*11];
assign cvt_data_in_12 = cvt_pd_in[32*12+31:32*12];
assign cvt_data_in_13 = cvt_pd_in[32*13+31:32*13];
assign cvt_data_in_14 = cvt_pd_in[32*14+31:32*14];
assign cvt_data_in_15 = cvt_pd_in[32*15+31:32*15];
assign cvt_pd_out8[8*0+7:8*0] = cvt_data_out_0[7:0];
assign cvt_pd_out8[8*1+7:8*1] = cvt_data_out_1[7:0];
assign cvt_pd_out8[8*2+7:8*2] = cvt_data_out_2[7:0];
assign cvt_pd_out8[8*3+7:8*3] = cvt_data_out_3[7:0];
assign cvt_pd_out8[8*4+7:8*4] = cvt_data_out_4[7:0];
assign cvt_pd_out8[8*5+7:8*5] = cvt_data_out_5[7:0];
assign cvt_pd_out8[8*6+7:8*6] = cvt_data_out_6[7:0];
assign cvt_pd_out8[8*7+7:8*7] = cvt_data_out_7[7:0];
assign cvt_pd_out8[8*8+7:8*8] = cvt_data_out_8[7:0];
assign cvt_pd_out8[8*9+7:8*9] = cvt_data_out_9[7:0];
assign cvt_pd_out8[8*10+7:8*10] = cvt_data_out_10[7:0];
assign cvt_pd_out8[8*11+7:8*11] = cvt_data_out_11[7:0];
assign cvt_pd_out8[8*12+7:8*12] = cvt_data_out_12[7:0];
assign cvt_pd_out8[8*13+7:8*13] = cvt_data_out_13[7:0];
assign cvt_pd_out8[8*14+7:8*14] = cvt_data_out_14[7:0];
assign cvt_pd_out8[8*15+7:8*15] = cvt_data_out_15[7:0];
assign cvt_pd_out16[16*0+15:16*0] = cvt_data_out_0;
assign cvt_pd_out16[16*1+15:16*1] = cvt_data_out_1;
assign cvt_pd_out16[16*2+15:16*2] = cvt_data_out_2;
assign cvt_pd_out16[16*3+15:16*3] = cvt_data_out_3;
assign cvt_pd_out16[16*4+15:16*4] = cvt_data_out_4;
assign cvt_pd_out16[16*5+15:16*5] = cvt_data_out_5;
assign cvt_pd_out16[16*6+15:16*6] = cvt_data_out_6;
assign cvt_pd_out16[16*7+15:16*7] = cvt_data_out_7;
assign cvt_pd_out16[16*8+15:16*8] = cvt_data_out_8;
assign cvt_pd_out16[16*9+15:16*9] = cvt_data_out_9;
assign cvt_pd_out16[16*10+15:16*10] = cvt_data_out_10;
assign cvt_pd_out16[16*11+15:16*11] = cvt_data_out_11;
assign cvt_pd_out16[16*12+15:16*12] = cvt_data_out_12;
assign cvt_pd_out16[16*13+15:16*13] = cvt_data_out_13;
assign cvt_pd_out16[16*14+15:16*14] = cvt_data_out_14;
assign cvt_pd_out16[16*15+15:16*15] = cvt_data_out_15;
assign cvt_pd_out[256-1:0] = cfg_out_precision[1:0]==2'b0 ? {{(8*16){1'b0}},cvt_pd_out8[8*16-1:0]} : cvt_pd_out16[16*16-1:0];
assign cvt_pd_out[256+0] = cvt_sat_out_0;
assign cvt_pd_out[256+1] = cvt_sat_out_1;
assign cvt_pd_out[256+2] = cvt_sat_out_2;
assign cvt_pd_out[256+3] = cvt_sat_out_3;
assign cvt_pd_out[256+4] = cvt_sat_out_4;
assign cvt_pd_out[256+5] = cvt_sat_out_5;
assign cvt_pd_out[256+6] = cvt_sat_out_6;
assign cvt_pd_out[256+7] = cvt_sat_out_7;
assign cvt_pd_out[256+8] = cvt_sat_out_8;
assign cvt_pd_out[256+9] = cvt_sat_out_9;
assign cvt_pd_out[256+10] = cvt_sat_out_10;
assign cvt_pd_out[256+11] = cvt_sat_out_11;
assign cvt_pd_out[256+12] = cvt_sat_out_12;
assign cvt_pd_out[256+13] = cvt_sat_out_13;
assign cvt_pd_out[256+14] = cvt_sat_out_14;
assign cvt_pd_out[256+15] = cvt_sat_out_15;
NV_NVDLA_SDP_HLS_C_int c_int_0 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_0[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_0[15:0])
,.cvt_in_prdy (cvt_in_prdy_0)
,.cvt_out_pvld (cvt_out_pvld_0)
,.cvt_sat_out (cvt_sat_out_0)
);
NV_NVDLA_SDP_HLS_C_int c_int_1 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_1[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_1[15:0])
,.cvt_in_prdy (cvt_in_prdy_1)
,.cvt_out_pvld (cvt_out_pvld_1)
,.cvt_sat_out (cvt_sat_out_1)
);
NV_NVDLA_SDP_HLS_C_int c_int_2 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_2[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_2[15:0])
,.cvt_in_prdy (cvt_in_prdy_2)
,.cvt_out_pvld (cvt_out_pvld_2)
,.cvt_sat_out (cvt_sat_out_2)
);
NV_NVDLA_SDP_HLS_C_int c_int_3 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_3[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_3[15:0])
,.cvt_in_prdy (cvt_in_prdy_3)
,.cvt_out_pvld (cvt_out_pvld_3)
,.cvt_sat_out (cvt_sat_out_3)
);
NV_NVDLA_SDP_HLS_C_int c_int_4 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_4[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_4[15:0])
,.cvt_in_prdy (cvt_in_prdy_4)
,.cvt_out_pvld (cvt_out_pvld_4)
,.cvt_sat_out (cvt_sat_out_4)
);
NV_NVDLA_SDP_HLS_C_int c_int_5 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_5[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_5[15:0])
,.cvt_in_prdy (cvt_in_prdy_5)
,.cvt_out_pvld (cvt_out_pvld_5)
,.cvt_sat_out (cvt_sat_out_5)
);
NV_NVDLA_SDP_HLS_C_int c_int_6 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_6[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_6[15:0])
,.cvt_in_prdy (cvt_in_prdy_6)
,.cvt_out_pvld (cvt_out_pvld_6)
,.cvt_sat_out (cvt_sat_out_6)
);
NV_NVDLA_SDP_HLS_C_int c_int_7 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_7[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_7[15:0])
,.cvt_in_prdy (cvt_in_prdy_7)
,.cvt_out_pvld (cvt_out_pvld_7)
,.cvt_sat_out (cvt_sat_out_7)
);
NV_NVDLA_SDP_HLS_C_int c_int_8 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_8[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_8[15:0])
,.cvt_in_prdy (cvt_in_prdy_8)
,.cvt_out_pvld (cvt_out_pvld_8)
,.cvt_sat_out (cvt_sat_out_8)
);
NV_NVDLA_SDP_HLS_C_int c_int_9 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_9[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_9[15:0])
,.cvt_in_prdy (cvt_in_prdy_9)
,.cvt_out_pvld (cvt_out_pvld_9)
,.cvt_sat_out (cvt_sat_out_9)
);
NV_NVDLA_SDP_HLS_C_int c_int_10 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_10[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_10[15:0])
,.cvt_in_prdy (cvt_in_prdy_10)
,.cvt_out_pvld (cvt_out_pvld_10)
,.cvt_sat_out (cvt_sat_out_10)
);
NV_NVDLA_SDP_HLS_C_int c_int_11 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_11[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_11[15:0])
,.cvt_in_prdy (cvt_in_prdy_11)
,.cvt_out_pvld (cvt_out_pvld_11)
,.cvt_sat_out (cvt_sat_out_11)
);
NV_NVDLA_SDP_HLS_C_int c_int_12 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_12[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_12[15:0])
,.cvt_in_prdy (cvt_in_prdy_12)
,.cvt_out_pvld (cvt_out_pvld_12)
,.cvt_sat_out (cvt_sat_out_12)
);
NV_NVDLA_SDP_HLS_C_int c_int_13 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_13[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_13[15:0])
,.cvt_in_prdy (cvt_in_prdy_13)
,.cvt_out_pvld (cvt_out_pvld_13)
,.cvt_sat_out (cvt_sat_out_13)
);
NV_NVDLA_SDP_HLS_C_int c_int_14 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_14[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_14[15:0])
,.cvt_in_prdy (cvt_in_prdy_14)
,.cvt_out_pvld (cvt_out_pvld_14)
,.cvt_sat_out (cvt_sat_out_14)
);
NV_NVDLA_SDP_HLS_C_int c_int_15 (
.cfg_mode_eql (cfg_mode_eql)
,.cfg_offset (cfg_offset[31:0])
,.cfg_out_precision (cfg_out_precision[1:0])
,.cfg_scale (cfg_scale[15:0])
,.cfg_truncate (cfg_truncate[5:0])
,.cvt_data_in (cvt_data_in_15[31:0])
,.cvt_in_pvld (cvt_in_pvld)
,.cvt_out_prdy (cvt_out_prdy)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.cvt_data_out (cvt_data_out_15[15:0])
,.cvt_in_prdy (cvt_in_prdy_15)
,.cvt_out_pvld (cvt_out_pvld_15)
,.cvt_sat_out (cvt_sat_out_15)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign cvt_in_prdy = cvt_in_prdy_0;
assign cvt_out_pvld = cvt_out_pvld_0;
endmodule // NV_NVDLA_SDP_HLS_c |
module NV_NVDLA_DMAIF_wr (
nvdla_core_clk
,nvdla_core_rstn
,reg2dp_dst_ram_type
,cvif_wr_req_pd
,cvif_wr_req_valid
,cvif_wr_req_ready
,cvif_wr_rsp_complete
,mcif_wr_req_pd
,mcif_wr_req_valid
,mcif_wr_req_ready
,mcif_wr_rsp_complete
,dmaif_wr_req_pd
,dmaif_wr_req_pvld
,dmaif_wr_req_prdy
,dmaif_wr_rsp_complete
);
//////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
input reg2dp_dst_ram_type;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask );
//: print qq( output [${dmabw}:0] cvif_wr_req_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
output [257:0] cvif_wr_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output cvif_wr_req_valid;
input cvif_wr_req_ready;
input cvif_wr_rsp_complete;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask );
//: print qq( output [${dmabw}:0] mcif_wr_req_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
output [257:0] mcif_wr_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output mcif_wr_req_valid;
input mcif_wr_req_ready;
input mcif_wr_rsp_complete;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask );
//: print qq( input [${dmabw}:0] dmaif_wr_req_pd; \n);
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [257:0] dmaif_wr_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input dmaif_wr_req_pvld;
output dmaif_wr_req_prdy;
output dmaif_wr_rsp_complete;
//////////////////////////////////////////////
reg dmaif_wr_rsp_complete;
wire dma_wr_req_type;
wire mc_dma_wr_req_vld;
wire mc_dma_wr_req_rdy;
wire mc_wr_req_rdyi;
wire wr_req_rdyi;
wire cv_dma_wr_req_vld;
wire cv_dma_wr_req_rdy;
wire cv_wr_req_rdyi;
//==============
// DMA Interface
//==============
assign dma_wr_req_type = reg2dp_dst_ram_type;
// wr Channel: Request
assign cv_dma_wr_req_vld = dmaif_wr_req_pvld & (dma_wr_req_type == 1'b0);
assign cv_wr_req_rdyi = cv_dma_wr_req_rdy & (dma_wr_req_type == 1'b0);
assign wr_req_rdyi = mc_wr_req_rdyi | cv_wr_req_rdyi;
assign mc_dma_wr_req_vld = dmaif_wr_req_pvld & (dma_wr_req_type == 1'b1);
assign mc_wr_req_rdyi = mc_dma_wr_req_rdy & (dma_wr_req_type == 1'b1);
assign dmaif_wr_req_prdy= wr_req_rdyi;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask + 1 );
//: &eperl::pipe(" -wid $dmabw -is -do mcif_wr_req_pd -vo mcif_wr_req_valid -ri mcif_wr_req_ready -di dmaif_wr_req_pd -vi mc_dma_wr_req_vld -ro mc_dma_wr_req_rdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
// Reg
reg mc_dma_wr_req_rdy_f;
reg skid_flop_mc_dma_wr_req_rdy_f;
reg skid_flop_mc_dma_wr_req_vld;
reg [258-1:0] skid_flop_dmaif_wr_req_pd;
reg pipe_skid_mc_dma_wr_req_vld;
reg [258-1:0] pipe_skid_dmaif_wr_req_pd;
// Wire
wire skid_mc_dma_wr_req_vld;
wire [258-1:0] skid_dmaif_wr_req_pd;
wire skid_mc_dma_wr_req_rdy_f;
wire pipe_skid_mc_dma_wr_req_rdy_f;
wire mcif_wr_req_valid;
wire [258-1:0] mcif_wr_req_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_dma_wr_req_rdy_f <= 1'b1;
skid_flop_mc_dma_wr_req_rdy_f <= 1'b1;
end else begin
mc_dma_wr_req_rdy_f <= skid_mc_dma_wr_req_rdy_f;
skid_flop_mc_dma_wr_req_rdy_f <= skid_mc_dma_wr_req_rdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_mc_dma_wr_req_vld <= 1'b0;
end else begin
if (skid_flop_mc_dma_wr_req_rdy_f) begin
skid_flop_mc_dma_wr_req_vld <= mc_dma_wr_req_vld;
end
end
end
assign skid_mc_dma_wr_req_vld = (skid_flop_mc_dma_wr_req_rdy_f) ? mc_dma_wr_req_vld : skid_flop_mc_dma_wr_req_vld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_mc_dma_wr_req_rdy_f & mc_dma_wr_req_vld) begin
skid_flop_dmaif_wr_req_pd[258-1:0] <= dmaif_wr_req_pd[258-1:0];
end
end
assign skid_dmaif_wr_req_pd[258-1:0] = (skid_flop_mc_dma_wr_req_rdy_f) ? dmaif_wr_req_pd[258-1:0] : skid_flop_dmaif_wr_req_pd[258-1:0];
// PIPE READY
assign skid_mc_dma_wr_req_rdy_f = pipe_skid_mc_dma_wr_req_rdy_f || !pipe_skid_mc_dma_wr_req_vld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_mc_dma_wr_req_vld <= 1'b0;
end else begin
if (skid_mc_dma_wr_req_rdy_f) begin
pipe_skid_mc_dma_wr_req_vld <= skid_mc_dma_wr_req_vld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_mc_dma_wr_req_rdy_f && skid_mc_dma_wr_req_vld) begin
pipe_skid_dmaif_wr_req_pd[258-1:0] <= skid_dmaif_wr_req_pd[258-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_mc_dma_wr_req_rdy_f = mcif_wr_req_ready;
assign mcif_wr_req_valid = pipe_skid_mc_dma_wr_req_vld;
assign mcif_wr_req_pd = pipe_skid_dmaif_wr_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign mc_dma_wr_req_rdy = mc_dma_wr_req_rdy_f;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask + 1 );
//: print " wire [${dmabw}-1:0] cv_dma_wr_req_pd ; \n";
//: print " assign cv_dma_wr_req_pd = dmaif_wr_req_pd; \n";
//: &eperl::pipe(" -wid $dmabw -is -do cvif_wr_req_pd -vo cvif_wr_req_valid -ri cvif_wr_req_ready -di cv_dma_wr_req_pd -vi cv_dma_wr_req_vld -ro cv_dma_wr_req_rdy_f ");
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [258-1:0] cv_dma_wr_req_pd ;
assign cv_dma_wr_req_pd = dmaif_wr_req_pd;
// Reg
reg cv_dma_wr_req_rdy_f;
reg skid_flop_cv_dma_wr_req_rdy_f;
reg skid_flop_cv_dma_wr_req_vld;
reg [258-1:0] skid_flop_cv_dma_wr_req_pd;
reg pipe_skid_cv_dma_wr_req_vld;
reg [258-1:0] pipe_skid_cv_dma_wr_req_pd;
// Wire
wire skid_cv_dma_wr_req_vld;
wire [258-1:0] skid_cv_dma_wr_req_pd;
wire skid_cv_dma_wr_req_rdy_f;
wire pipe_skid_cv_dma_wr_req_rdy_f;
wire cvif_wr_req_valid;
wire [258-1:0] cvif_wr_req_pd;
// Code
// SKID READY
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_dma_wr_req_rdy_f <= 1'b1;
skid_flop_cv_dma_wr_req_rdy_f <= 1'b1;
end else begin
cv_dma_wr_req_rdy_f <= skid_cv_dma_wr_req_rdy_f;
skid_flop_cv_dma_wr_req_rdy_f <= skid_cv_dma_wr_req_rdy_f;
end
end
// SKID VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
skid_flop_cv_dma_wr_req_vld <= 1'b0;
end else begin
if (skid_flop_cv_dma_wr_req_rdy_f) begin
skid_flop_cv_dma_wr_req_vld <= cv_dma_wr_req_vld;
end
end
end
assign skid_cv_dma_wr_req_vld = (skid_flop_cv_dma_wr_req_rdy_f) ? cv_dma_wr_req_vld : skid_flop_cv_dma_wr_req_vld;
// SKID DATA
always @(posedge nvdla_core_clk) begin
if (skid_flop_cv_dma_wr_req_rdy_f & cv_dma_wr_req_vld) begin
skid_flop_cv_dma_wr_req_pd[258-1:0] <= cv_dma_wr_req_pd[258-1:0];
end
end
assign skid_cv_dma_wr_req_pd[258-1:0] = (skid_flop_cv_dma_wr_req_rdy_f) ? cv_dma_wr_req_pd[258-1:0] : skid_flop_cv_dma_wr_req_pd[258-1:0];
// PIPE READY
assign skid_cv_dma_wr_req_rdy_f = pipe_skid_cv_dma_wr_req_rdy_f || !pipe_skid_cv_dma_wr_req_vld;
// PIPE VALID
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
pipe_skid_cv_dma_wr_req_vld <= 1'b0;
end else begin
if (skid_cv_dma_wr_req_rdy_f) begin
pipe_skid_cv_dma_wr_req_vld <= skid_cv_dma_wr_req_vld;
end
end
end
// PIPE DATA
always @(posedge nvdla_core_clk) begin
if (skid_cv_dma_wr_req_rdy_f && skid_cv_dma_wr_req_vld) begin
pipe_skid_cv_dma_wr_req_pd[258-1:0] <= skid_cv_dma_wr_req_pd[258-1:0];
end
end
// PIPE OUTPUT
assign pipe_skid_cv_dma_wr_req_rdy_f = cvif_wr_req_ready;
assign cvif_wr_req_valid = pipe_skid_cv_dma_wr_req_vld;
assign cvif_wr_req_pd = pipe_skid_cv_dma_wr_req_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign cv_dma_wr_req_rdy = cv_dma_wr_req_rdy_f;
// wr Channel: Response
wire ack_top_rdy;
wire releasing;
reg ack_top_vld ;
reg ack_top_id ;
wire ack_bot_rdy;
reg ack_bot_vld ;
reg ack_bot_id ;
wire ack_raw_rdy;
wire ack_raw_id;
wire ack_raw_vld;
wire require_ack;
wire mc_int_wr_rsp_complete;
assign mc_int_wr_rsp_complete = mcif_wr_rsp_complete;
wire cv_int_wr_rsp_complete;
assign cv_int_wr_rsp_complete = cvif_wr_rsp_complete;
//: my $dmaif = 256;
//: my $mask = int($dmaif/32/8);
//: my $dmabw = ( $dmaif + $mask + 1 );
//: if($dmaif > 64) {
//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77]==1); \n);
//: } else {
//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[45]==1); \n);
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign require_ack = (dmaif_wr_req_pd[258-1]==0) & (dmaif_wr_req_pd[77]==1);
//| eperl: generated_end (DO NOT EDIT ABOVE)
// assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77:77]==1);
assign ack_raw_vld = dmaif_wr_req_pvld & wr_req_rdyi & require_ack;
assign ack_raw_id = dma_wr_req_type;
// stage1: bot
assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld;
always @(posedge nvdla_core_clk) begin
if (ack_raw_vld & ack_raw_rdy)
ack_bot_id <= ack_raw_id;
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
ack_bot_vld <= 1'b0;
end else if (ack_raw_rdy) begin
ack_bot_vld <= ack_raw_vld;
end
end
////: &eperl::assert(" -type never -desc `dmaif bot never push back` -expr `ack_raw_vld & !ack_raw_rdy` ");
// stage2: top
assign ack_bot_rdy = ack_top_rdy || !ack_top_vld;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
ack_top_id <= 1'b0;
end else if (ack_bot_vld & ack_bot_rdy) begin
ack_top_id <= ack_bot_id;
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
ack_top_vld <= 1'b0;
end else if (ack_bot_rdy) begin
ack_top_vld <= ack_bot_vld;
end
end
assign ack_top_rdy = releasing;
reg mc_dma_wr_rsp_complete;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_dma_wr_rsp_complete <= 1'b0;
end else begin
mc_dma_wr_rsp_complete <= mc_int_wr_rsp_complete;
end
end
reg cv_dma_wr_rsp_complete;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_dma_wr_rsp_complete <= 1'b0;
end else begin
cv_dma_wr_rsp_complete <= cv_int_wr_rsp_complete;
end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
dmaif_wr_rsp_complete <= 1'b0;
end else begin
dmaif_wr_rsp_complete <= releasing;
end
end
reg mc_pending;
wire mc_releasing;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
mc_pending <= 1'b0;
end else begin
if (ack_top_id==0) begin
if (mc_dma_wr_rsp_complete) begin
mc_pending <= 1'b1;
end
end else if (ack_top_id==1) begin
if (mc_pending) begin
mc_pending <= 1'b0;
end
end
end
end
assign mc_releasing = ack_top_id==1'b1 & (mc_dma_wr_rsp_complete | mc_pending);
reg cv_pending;
wire cv_releasing;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cv_pending <= 1'b0;
end else begin
if (ack_top_id==1) begin
if (cv_dma_wr_rsp_complete) begin
cv_pending <= 1'b1;
end
end else if (ack_top_id==0) begin
if (cv_pending) begin
cv_pending <= 1'b0;
end
end
end
end
assign cv_releasing = ack_top_id==1'b0 & (cv_dma_wr_rsp_complete | cv_pending);
assign releasing = mc_releasing | cv_releasing;
// //: &eperl::assert(" -type never -desc 'no release both together' -expr 'mc_releasing & cv_releasing' );
// //: &eperl::assert(" -type never -desc 'no cv resp back and pending together' -expr 'cv_pending & cv_dma_wr_rsp_complete' );
// //: &eperl::assert(" -type never -desc 'no ack_top_vld when resp from cv' -expr '(cv_pending | cv_dma_wr_rsp_complete) & !ack_top_vld' );
////: &eperl::assert(" -type never -desc 'no mc resp back and pending together' -expr 'mc_pending & mc_dma_wr_rsp_complete' );
////: &eperl::assert(" -type never -desc 'no ack_top_vld when resp from mc' -expr '(mc_pending | mc_dma_wr_rsp_complete) & !ack_top_vld' );
//////////////////////////
endmodule |
module NV_NVDLA_SDP_HLS_Y_int_core (
cfg_alu_algo //|< i
,cfg_alu_bypass //|< i
,cfg_alu_op //|< i
,cfg_alu_src //|< i
,cfg_mul_bypass //|< i
,cfg_mul_op //|< i
,cfg_mul_prelu //|< i
,cfg_mul_src //|< i
,cfg_mul_truncate //|< i
,chn_alu_op //|< i
,chn_alu_op_pvld //|< i
,chn_data_in //|< i
,chn_in_pvld //|< i
,chn_mul_op //|< i
,chn_mul_op_pvld //|< i
,chn_out_prdy //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,chn_alu_op_prdy //|> o
,chn_data_out //|> o
,chn_in_prdy //|> o
,chn_mul_op_prdy //|> o
,chn_out_pvld //|> o
);
input [1:0] cfg_alu_algo;
input cfg_alu_bypass;
input [31:0] cfg_alu_op;
input cfg_alu_src;
input cfg_mul_bypass;
input [31:0] cfg_mul_op;
input cfg_mul_prelu;
input cfg_mul_src;
input [9:0] cfg_mul_truncate;
input [32*4 -1:0] chn_alu_op;
input chn_alu_op_pvld;
input [32*4 -1:0] chn_data_in;
input chn_in_pvld;
input [32*4 -1:0] chn_mul_op;
input chn_mul_op_pvld;
input chn_out_prdy;
output chn_alu_op_prdy;
output [32*4 -1:0] chn_data_out;
output chn_in_prdy;
output chn_mul_op_prdy;
output chn_out_pvld;
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $k=4;
//: foreach my $i (0..${k}-1) {
//: print qq(
//: wire [31:0] chn_alu_op_${i};
//: wire chn_alu_op_prdy_${i};
//: wire [31:0] chn_data_in_${i};
//: wire [31:0] chn_data_out_${i};
//: wire chn_in_prdy_${i};
//: wire [31:0] chn_mul_op_${i};
//: wire chn_mul_op_prdy_${i};
//: wire chn_out_pvld_${i};
//: wire [31:0] mul_data_out_${i};
//: wire mul_out_prdy_${i};
//: wire mul_out_pvld_${i};
//:
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [31:0] chn_alu_op_0;
wire chn_alu_op_prdy_0;
wire [31:0] chn_data_in_0;
wire [31:0] chn_data_out_0;
wire chn_in_prdy_0;
wire [31:0] chn_mul_op_0;
wire chn_mul_op_prdy_0;
wire chn_out_pvld_0;
wire [31:0] mul_data_out_0;
wire mul_out_prdy_0;
wire mul_out_pvld_0;
wire [31:0] chn_alu_op_1;
wire chn_alu_op_prdy_1;
wire [31:0] chn_data_in_1;
wire [31:0] chn_data_out_1;
wire chn_in_prdy_1;
wire [31:0] chn_mul_op_1;
wire chn_mul_op_prdy_1;
wire chn_out_pvld_1;
wire [31:0] mul_data_out_1;
wire mul_out_prdy_1;
wire mul_out_pvld_1;
wire [31:0] chn_alu_op_2;
wire chn_alu_op_prdy_2;
wire [31:0] chn_data_in_2;
wire [31:0] chn_data_out_2;
wire chn_in_prdy_2;
wire [31:0] chn_mul_op_2;
wire chn_mul_op_prdy_2;
wire chn_out_pvld_2;
wire [31:0] mul_data_out_2;
wire mul_out_prdy_2;
wire mul_out_pvld_2;
wire [31:0] chn_alu_op_3;
wire chn_alu_op_prdy_3;
wire [31:0] chn_data_in_3;
wire [31:0] chn_data_out_3;
wire chn_in_prdy_3;
wire [31:0] chn_mul_op_3;
wire chn_mul_op_prdy_3;
wire chn_out_pvld_3;
wire [31:0] mul_data_out_3;
wire mul_out_prdy_3;
wire mul_out_pvld_3;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign chn_in_prdy = chn_in_prdy_0;
assign chn_alu_op_prdy = chn_alu_op_prdy_0;
assign chn_mul_op_prdy = chn_mul_op_prdy_0;
assign chn_out_pvld = chn_out_pvld_0;
//: my $k=4;
//: foreach my $i (0..${k}-1) {
//: print qq(
//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}];
//: assign chn_alu_op_${i} = chn_alu_op[32*${i}+31:32*${i}];
//: assign chn_mul_op_${i} = chn_mul_op[32*${i}+31:32*${i}];
//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i};
//:
//: NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_${i} (
//: .cfg_mul_bypass (cfg_mul_bypass)
//: ,.cfg_mul_op (cfg_mul_op[31:0])
//: ,.cfg_mul_prelu (cfg_mul_prelu)
//: ,.cfg_mul_src (cfg_mul_src)
//: ,.cfg_mul_truncate (cfg_mul_truncate[9:0])
//: ,.chn_in_pvld (chn_in_pvld)
//: ,.chn_mul_in (chn_data_in_${i}[31:0])
//: ,.chn_mul_op (chn_mul_op_${i}[31:0])
//: ,.chn_mul_op_pvld (chn_mul_op_pvld)
//: ,.mul_out_prdy (mul_out_prdy_${i})
//: ,.nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.chn_in_prdy (chn_in_prdy_${i})
//: ,.chn_mul_op_prdy (chn_mul_op_prdy_${i})
//: ,.mul_data_out (mul_data_out_${i}[31:0])
//: ,.mul_out_pvld (mul_out_pvld_${i})
//: );
//:
//: NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_${i} (
//: .alu_data_in (mul_data_out_${i}[31:0])
//: ,.alu_in_pvld (mul_out_pvld_${i})
//: ,.alu_out_prdy (chn_out_prdy)
//: ,.cfg_alu_algo (cfg_alu_algo[1:0])
//: ,.cfg_alu_bypass (cfg_alu_bypass)
//: ,.cfg_alu_op (cfg_alu_op[31:0])
//: ,.cfg_alu_src (cfg_alu_src)
//: ,.chn_alu_op (chn_alu_op_${i}[31:0])
//: ,.chn_alu_op_pvld (chn_alu_op_pvld)
//: ,.nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.alu_data_out (chn_data_out_${i}[31:0])
//: ,.alu_in_prdy (mul_out_prdy_${i})
//: ,.alu_out_pvld (chn_out_pvld_${i})
//: ,.chn_alu_op_prdy (chn_alu_op_prdy_${i})
//: );
//:
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign chn_data_in_0= chn_data_in[32*0+31:32*0];
assign chn_alu_op_0 = chn_alu_op[32*0+31:32*0];
assign chn_mul_op_0 = chn_mul_op[32*0+31:32*0];
assign chn_data_out[32*0+31:32*0] = chn_data_out_0;
NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_0 (
.cfg_mul_bypass (cfg_mul_bypass)
,.cfg_mul_op (cfg_mul_op[31:0])
,.cfg_mul_prelu (cfg_mul_prelu)
,.cfg_mul_src (cfg_mul_src)
,.cfg_mul_truncate (cfg_mul_truncate[9:0])
,.chn_in_pvld (chn_in_pvld)
,.chn_mul_in (chn_data_in_0[31:0])
,.chn_mul_op (chn_mul_op_0[31:0])
,.chn_mul_op_pvld (chn_mul_op_pvld)
,.mul_out_prdy (mul_out_prdy_0)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.chn_in_prdy (chn_in_prdy_0)
,.chn_mul_op_prdy (chn_mul_op_prdy_0)
,.mul_data_out (mul_data_out_0[31:0])
,.mul_out_pvld (mul_out_pvld_0)
);
NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_0 (
.alu_data_in (mul_data_out_0[31:0])
,.alu_in_pvld (mul_out_pvld_0)
,.alu_out_prdy (chn_out_prdy)
,.cfg_alu_algo (cfg_alu_algo[1:0])
,.cfg_alu_bypass (cfg_alu_bypass)
,.cfg_alu_op (cfg_alu_op[31:0])
,.cfg_alu_src (cfg_alu_src)
,.chn_alu_op (chn_alu_op_0[31:0])
,.chn_alu_op_pvld (chn_alu_op_pvld)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.alu_data_out (chn_data_out_0[31:0])
,.alu_in_prdy (mul_out_prdy_0)
,.alu_out_pvld (chn_out_pvld_0)
,.chn_alu_op_prdy (chn_alu_op_prdy_0)
);
assign chn_data_in_1= chn_data_in[32*1+31:32*1];
assign chn_alu_op_1 = chn_alu_op[32*1+31:32*1];
assign chn_mul_op_1 = chn_mul_op[32*1+31:32*1];
assign chn_data_out[32*1+31:32*1] = chn_data_out_1;
NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_1 (
.cfg_mul_bypass (cfg_mul_bypass)
,.cfg_mul_op (cfg_mul_op[31:0])
,.cfg_mul_prelu (cfg_mul_prelu)
,.cfg_mul_src (cfg_mul_src)
,.cfg_mul_truncate (cfg_mul_truncate[9:0])
,.chn_in_pvld (chn_in_pvld)
,.chn_mul_in (chn_data_in_1[31:0])
,.chn_mul_op (chn_mul_op_1[31:0])
,.chn_mul_op_pvld (chn_mul_op_pvld)
,.mul_out_prdy (mul_out_prdy_1)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.chn_in_prdy (chn_in_prdy_1)
,.chn_mul_op_prdy (chn_mul_op_prdy_1)
,.mul_data_out (mul_data_out_1[31:0])
,.mul_out_pvld (mul_out_pvld_1)
);
NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_1 (
.alu_data_in (mul_data_out_1[31:0])
,.alu_in_pvld (mul_out_pvld_1)
,.alu_out_prdy (chn_out_prdy)
,.cfg_alu_algo (cfg_alu_algo[1:0])
,.cfg_alu_bypass (cfg_alu_bypass)
,.cfg_alu_op (cfg_alu_op[31:0])
,.cfg_alu_src (cfg_alu_src)
,.chn_alu_op (chn_alu_op_1[31:0])
,.chn_alu_op_pvld (chn_alu_op_pvld)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.alu_data_out (chn_data_out_1[31:0])
,.alu_in_prdy (mul_out_prdy_1)
,.alu_out_pvld (chn_out_pvld_1)
,.chn_alu_op_prdy (chn_alu_op_prdy_1)
);
assign chn_data_in_2= chn_data_in[32*2+31:32*2];
assign chn_alu_op_2 = chn_alu_op[32*2+31:32*2];
assign chn_mul_op_2 = chn_mul_op[32*2+31:32*2];
assign chn_data_out[32*2+31:32*2] = chn_data_out_2;
NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_2 (
.cfg_mul_bypass (cfg_mul_bypass)
,.cfg_mul_op (cfg_mul_op[31:0])
,.cfg_mul_prelu (cfg_mul_prelu)
,.cfg_mul_src (cfg_mul_src)
,.cfg_mul_truncate (cfg_mul_truncate[9:0])
,.chn_in_pvld (chn_in_pvld)
,.chn_mul_in (chn_data_in_2[31:0])
,.chn_mul_op (chn_mul_op_2[31:0])
,.chn_mul_op_pvld (chn_mul_op_pvld)
,.mul_out_prdy (mul_out_prdy_2)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.chn_in_prdy (chn_in_prdy_2)
,.chn_mul_op_prdy (chn_mul_op_prdy_2)
,.mul_data_out (mul_data_out_2[31:0])
,.mul_out_pvld (mul_out_pvld_2)
);
NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_2 (
.alu_data_in (mul_data_out_2[31:0])
,.alu_in_pvld (mul_out_pvld_2)
,.alu_out_prdy (chn_out_prdy)
,.cfg_alu_algo (cfg_alu_algo[1:0])
,.cfg_alu_bypass (cfg_alu_bypass)
,.cfg_alu_op (cfg_alu_op[31:0])
,.cfg_alu_src (cfg_alu_src)
,.chn_alu_op (chn_alu_op_2[31:0])
,.chn_alu_op_pvld (chn_alu_op_pvld)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.alu_data_out (chn_data_out_2[31:0])
,.alu_in_prdy (mul_out_prdy_2)
,.alu_out_pvld (chn_out_pvld_2)
,.chn_alu_op_prdy (chn_alu_op_prdy_2)
);
assign chn_data_in_3= chn_data_in[32*3+31:32*3];
assign chn_alu_op_3 = chn_alu_op[32*3+31:32*3];
assign chn_mul_op_3 = chn_mul_op[32*3+31:32*3];
assign chn_data_out[32*3+31:32*3] = chn_data_out_3;
NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_3 (
.cfg_mul_bypass (cfg_mul_bypass)
,.cfg_mul_op (cfg_mul_op[31:0])
,.cfg_mul_prelu (cfg_mul_prelu)
,.cfg_mul_src (cfg_mul_src)
,.cfg_mul_truncate (cfg_mul_truncate[9:0])
,.chn_in_pvld (chn_in_pvld)
,.chn_mul_in (chn_data_in_3[31:0])
,.chn_mul_op (chn_mul_op_3[31:0])
,.chn_mul_op_pvld (chn_mul_op_pvld)
,.mul_out_prdy (mul_out_prdy_3)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.chn_in_prdy (chn_in_prdy_3)
,.chn_mul_op_prdy (chn_mul_op_prdy_3)
,.mul_data_out (mul_data_out_3[31:0])
,.mul_out_pvld (mul_out_pvld_3)
);
NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_3 (
.alu_data_in (mul_data_out_3[31:0])
,.alu_in_pvld (mul_out_pvld_3)
,.alu_out_prdy (chn_out_prdy)
,.cfg_alu_algo (cfg_alu_algo[1:0])
,.cfg_alu_bypass (cfg_alu_bypass)
,.cfg_alu_op (cfg_alu_op[31:0])
,.cfg_alu_src (cfg_alu_src)
,.chn_alu_op (chn_alu_op_3[31:0])
,.chn_alu_op_pvld (chn_alu_op_pvld)
,.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.alu_data_out (chn_data_out_3[31:0])
,.alu_in_prdy (mul_out_prdy_3)
,.alu_out_pvld (chn_out_pvld_3)
,.chn_alu_op_prdy (chn_alu_op_prdy_3)
);
//| eperl: generated_end (DO NOT EDIT ABOVE)
endmodule // NV_NVDLA_SDP_HLS_Y_int_core |
module NV_NVDLA_cacc (
cacc2sdp_ready //|< i
,csb2cacc_req_pd //|< i
,csb2cacc_req_pvld //|< i
,dla_clk_ovr_on_sync //|< i
,global_clk_ovr_on_sync //|< i
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,mac_a2accu_data${i} //|< i
//: ,mac_b2accu_data${i} //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,mac_a2accu_data0 //|< i
,mac_b2accu_data0 //|< i
,mac_a2accu_data1 //|< i
,mac_b2accu_data1 //|< i
,mac_a2accu_data2 //|< i
,mac_b2accu_data2 //|< i
,mac_a2accu_data3 //|< i
,mac_b2accu_data3 //|< i
,mac_a2accu_data4 //|< i
,mac_b2accu_data4 //|< i
,mac_a2accu_data5 //|< i
,mac_b2accu_data5 //|< i
,mac_a2accu_data6 //|< i
,mac_b2accu_data6 //|< i
,mac_a2accu_data7 //|< i
,mac_b2accu_data7 //|< i
,mac_a2accu_data8 //|< i
,mac_b2accu_data8 //|< i
,mac_a2accu_data9 //|< i
,mac_b2accu_data9 //|< i
,mac_a2accu_data10 //|< i
,mac_b2accu_data10 //|< i
,mac_a2accu_data11 //|< i
,mac_b2accu_data11 //|< i
,mac_a2accu_data12 //|< i
,mac_b2accu_data12 //|< i
,mac_a2accu_data13 //|< i
,mac_b2accu_data13 //|< i
,mac_a2accu_data14 //|< i
,mac_b2accu_data14 //|< i
,mac_a2accu_data15 //|< i
,mac_b2accu_data15 //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,mac_a2accu_mask //|< i
,mac_a2accu_mode //|< i
,mac_a2accu_pd //|< i
,mac_a2accu_pvld //|< i
,mac_b2accu_mask //|< i
,mac_b2accu_mode //|< i
,mac_b2accu_pd //|< i
,mac_b2accu_pvld //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,pwrbus_ram_pd //|< i
,tmc2slcg_disable_clock_gating //|< i
,accu2sc_credit_size //|> o
,accu2sc_credit_vld //|> o
,cacc2csb_resp_pd //|> o
,cacc2csb_resp_valid //|> o
,cacc2glb_done_intr_pd //|> o
,cacc2sdp_pd //|> o
,cacc2sdp_valid //|> o
,csb2cacc_req_prdy //|> o
);
//
// NV_NVDLA_cacc_ports.v
//
input nvdla_core_clk; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */
input nvdla_core_rstn; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */
input [31:0] pwrbus_ram_pd;
input csb2cacc_req_pvld; /* data valid */
output csb2cacc_req_prdy; /* data return handshake */
input [62:0] csb2cacc_req_pd;
output cacc2csb_resp_valid; /* data valid */
output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */
input mac_a2accu_pvld; /* data valid */
input [32/2-1:0] mac_a2accu_mask;
input mac_a2accu_mode;
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: input [22 -1:0] mac_a2accu_data${i}; //|< i
//: input [22 -1:0] mac_b2accu_data${i}; //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [22 -1:0] mac_a2accu_data0; //|< i
input [22 -1:0] mac_b2accu_data0; //|< i
input [22 -1:0] mac_a2accu_data1; //|< i
input [22 -1:0] mac_b2accu_data1; //|< i
input [22 -1:0] mac_a2accu_data2; //|< i
input [22 -1:0] mac_b2accu_data2; //|< i
input [22 -1:0] mac_a2accu_data3; //|< i
input [22 -1:0] mac_b2accu_data3; //|< i
input [22 -1:0] mac_a2accu_data4; //|< i
input [22 -1:0] mac_b2accu_data4; //|< i
input [22 -1:0] mac_a2accu_data5; //|< i
input [22 -1:0] mac_b2accu_data5; //|< i
input [22 -1:0] mac_a2accu_data6; //|< i
input [22 -1:0] mac_b2accu_data6; //|< i
input [22 -1:0] mac_a2accu_data7; //|< i
input [22 -1:0] mac_b2accu_data7; //|< i
input [22 -1:0] mac_a2accu_data8; //|< i
input [22 -1:0] mac_b2accu_data8; //|< i
input [22 -1:0] mac_a2accu_data9; //|< i
input [22 -1:0] mac_b2accu_data9; //|< i
input [22 -1:0] mac_a2accu_data10; //|< i
input [22 -1:0] mac_b2accu_data10; //|< i
input [22 -1:0] mac_a2accu_data11; //|< i
input [22 -1:0] mac_b2accu_data11; //|< i
input [22 -1:0] mac_a2accu_data12; //|< i
input [22 -1:0] mac_b2accu_data12; //|< i
input [22 -1:0] mac_a2accu_data13; //|< i
input [22 -1:0] mac_b2accu_data13; //|< i
input [22 -1:0] mac_a2accu_data14; //|< i
input [22 -1:0] mac_b2accu_data14; //|< i
input [22 -1:0] mac_a2accu_data15; //|< i
input [22 -1:0] mac_b2accu_data15; //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
input [8:0] mac_a2accu_pd;
input mac_b2accu_pvld; /* data valid */
input [32/2-1:0] mac_b2accu_mask;
input mac_b2accu_mode;
input [8:0] mac_b2accu_pd;
output cacc2sdp_valid; /* data valid */
input cacc2sdp_ready; /* data return handshake */
output [32*16 +2 -1:0] cacc2sdp_pd;
output accu2sc_credit_vld; /* data valid */
output [2:0] accu2sc_credit_size;
output [1:0] cacc2glb_done_intr_pd;
//Port for SLCG
input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
wire [5 +1 -1:0] abuf_rd_addr;
wire [34*32 -1:0] abuf_rd_data;
wire abuf_rd_en;
wire [5 +1 -1:0] abuf_wr_addr;
wire [34*32 -1:0] abuf_wr_data;
wire abuf_wr_en;
//wire [12:0] accu_ctrl_pd;
wire [13:0] accu_ctrl_pd;
wire accu_ctrl_ram_valid;
wire accu_ctrl_valid;
wire cfg_in_en_mask;
wire cfg_is_wg;
wire [4:0] cfg_truncate;
wire [5 +1 -1:0] dbuf_rd_addr;
wire dbuf_rd_en;
wire dbuf_rd_layer_end;
wire dbuf_rd_ready;
wire [5 +1 -1:0] dbuf_wr_addr;
wire [32*32 -1:0] dbuf_wr_data;
wire dbuf_wr_en;
wire [32*32 -1:0] dlv_data;
wire dlv_mask;
wire [1:0] dlv_pd;
wire dlv_valid;
wire dp2reg_done;
wire [31:0] dp2reg_sat_count;
wire nvdla_cell_gated_clk;
wire nvdla_op_gated_clk_0;
wire nvdla_op_gated_clk_1;
wire nvdla_op_gated_clk_2;
wire [4:0] reg2dp_batches;
wire [4:0] reg2dp_clip_truncate;
wire [0:0] reg2dp_conv_mode;
wire [31:0] reg2dp_cya;
wire [31:0] reg2dp_dataout_addr;
wire [12:0] reg2dp_dataout_channel;
wire [12:0] reg2dp_dataout_height;
wire [12:0] reg2dp_dataout_width;
wire [0:0] reg2dp_line_packed;
wire [23:0] reg2dp_line_stride;
wire [0:0] reg2dp_op_en;
wire [1:0] reg2dp_proc_precision;
wire [0:0] reg2dp_surf_packed;
wire [23:0] reg2dp_surf_stride;
wire slcg_cell_en;
wire [6:0] slcg_op_en;
wire wait_for_op_en;
//==========================================================
// Regfile
//==========================================================
NV_NVDLA_CACC_regfile u_regfile (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.csb2cacc_req_pd (csb2cacc_req_pd) //|< i
,.csb2cacc_req_pvld (csb2cacc_req_pvld) //|< i
,.dp2reg_done (dp2reg_done) //|< w
,.dp2reg_sat_count (dp2reg_sat_count) //|< w
,.cacc2csb_resp_pd (cacc2csb_resp_pd) //|> o
,.cacc2csb_resp_valid (cacc2csb_resp_valid) //|> o
,.csb2cacc_req_prdy (csb2cacc_req_prdy) //|> o
,.reg2dp_batches (reg2dp_batches) //|> w
,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|> w
,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w
,.reg2dp_cya (reg2dp_cya) //|> w *
,.reg2dp_dataout_addr (reg2dp_dataout_addr) //|> w
,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|> w
,.reg2dp_dataout_height (reg2dp_dataout_height) //|> w
,.reg2dp_dataout_width (reg2dp_dataout_width) //|> w
,.reg2dp_line_packed (reg2dp_line_packed) //|> w
,.reg2dp_line_stride (reg2dp_line_stride) //|> w
,.reg2dp_op_en (reg2dp_op_en) //|> w
,.reg2dp_proc_precision (reg2dp_proc_precision) //|> w
,.reg2dp_surf_packed (reg2dp_surf_packed) //|> w
,.reg2dp_surf_stride (reg2dp_surf_stride) //|> w
,.slcg_op_en (slcg_op_en) //|> w
);
//==========================================================
// Assembly controller
//==========================================================
NV_NVDLA_CACC_assembly_ctrl u_assembly_ctrl (
.reg2dp_op_en (reg2dp_op_en) //|< w
,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w
,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|< w
,.nvdla_core_clk (nvdla_op_gated_clk_0) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.dp2reg_done (dp2reg_done) //|< w
,.mac_a2accu_pd (mac_a2accu_pd) //|< i
,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i
,.mac_b2accu_pd (mac_b2accu_pd) //|< i
,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i
,.abuf_rd_addr (abuf_rd_addr) //|> w
,.abuf_rd_en (abuf_rd_en) //|> w
,.accu_ctrl_pd (accu_ctrl_pd) //|> w
,.accu_ctrl_ram_valid ( accu_ctrl_ram_valid) //|> w
,.accu_ctrl_valid (accu_ctrl_valid) //|> w
,.cfg_in_en_mask (cfg_in_en_mask) //|> w
,.cfg_is_wg (cfg_is_wg) //|> w
,.cfg_truncate (cfg_truncate) //|> w
,.slcg_cell_en (slcg_cell_en) //|> w
,.wait_for_op_en (wait_for_op_en) //|> w
);
//==========================================================
// Assembly buffer
//==========================================================
NV_NVDLA_CACC_assembly_buffer u_assembly_buffer (
.nvdla_core_clk (nvdla_op_gated_clk_1) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.abuf_rd_addr (abuf_rd_addr) //|< w
,.abuf_rd_en (abuf_rd_en) //|< w
,.abuf_wr_addr (abuf_wr_addr) //|< w
,.abuf_wr_data (abuf_wr_data) //|< w
,.abuf_wr_en (abuf_wr_en) //|< w
,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i
,.abuf_rd_data (abuf_rd_data) //|> w
);
//==========================================================
// CACC calculator
//==========================================================
NV_NVDLA_CACC_calculator u_calculator (
.nvdla_cell_clk (nvdla_cell_gated_clk) //|< w
,.nvdla_core_clk (nvdla_op_gated_clk_2) //|< w
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.abuf_rd_data (abuf_rd_data) //|< w
,.accu_ctrl_pd (accu_ctrl_pd) //|< w
,.accu_ctrl_ram_valid (accu_ctrl_ram_valid) //|< w
,.accu_ctrl_valid (accu_ctrl_valid) //|< w
,.cfg_in_en_mask (cfg_in_en_mask) //|< w
,.cfg_is_wg (cfg_is_wg) //|< w
,.cfg_truncate (cfg_truncate) //|< w
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,.mac_a2accu_data${i} (mac_a2accu_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac_a2accu_data0 (mac_a2accu_data0) //|< i
,.mac_a2accu_data1 (mac_a2accu_data1) //|< i
,.mac_a2accu_data2 (mac_a2accu_data2) //|< i
,.mac_a2accu_data3 (mac_a2accu_data3) //|< i
,.mac_a2accu_data4 (mac_a2accu_data4) //|< i
,.mac_a2accu_data5 (mac_a2accu_data5) //|< i
,.mac_a2accu_data6 (mac_a2accu_data6) //|< i
,.mac_a2accu_data7 (mac_a2accu_data7) //|< i
,.mac_a2accu_data8 (mac_a2accu_data8) //|< i
,.mac_a2accu_data9 (mac_a2accu_data9) //|< i
,.mac_a2accu_data10 (mac_a2accu_data10) //|< i
,.mac_a2accu_data11 (mac_a2accu_data11) //|< i
,.mac_a2accu_data12 (mac_a2accu_data12) //|< i
,.mac_a2accu_data13 (mac_a2accu_data13) //|< i
,.mac_a2accu_data14 (mac_a2accu_data14) //|< i
,.mac_a2accu_data15 (mac_a2accu_data15) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac_a2accu_mask (mac_a2accu_mask) //|< i
,.mac_a2accu_mode (mac_a2accu_mode) //|< i
,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i
//: for(my $i=0; $i<32/2 ; $i++){
//: print qq(
//: ,.mac_b2accu_data${i} (mac_b2accu_data${i}) //|< i )
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,.mac_b2accu_data0 (mac_b2accu_data0) //|< i
,.mac_b2accu_data1 (mac_b2accu_data1) //|< i
,.mac_b2accu_data2 (mac_b2accu_data2) //|< i
,.mac_b2accu_data3 (mac_b2accu_data3) //|< i
,.mac_b2accu_data4 (mac_b2accu_data4) //|< i
,.mac_b2accu_data5 (mac_b2accu_data5) //|< i
,.mac_b2accu_data6 (mac_b2accu_data6) //|< i
,.mac_b2accu_data7 (mac_b2accu_data7) //|< i
,.mac_b2accu_data8 (mac_b2accu_data8) //|< i
,.mac_b2accu_data9 (mac_b2accu_data9) //|< i
,.mac_b2accu_data10 (mac_b2accu_data10) //|< i
,.mac_b2accu_data11 (mac_b2accu_data11) //|< i
,.mac_b2accu_data12 (mac_b2accu_data12) //|< i
,.mac_b2accu_data13 (mac_b2accu_data13) //|< i
,.mac_b2accu_data14 (mac_b2accu_data14) //|< i
,.mac_b2accu_data15 (mac_b2accu_data15) //|< i
//| eperl: generated_end (DO NOT EDIT ABOVE)
,.mac_b2accu_mask (mac_b2accu_mask) //|< i
,.mac_b2accu_mode (mac_b2accu_mode) //|< i
,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i
,.abuf_wr_addr (abuf_wr_addr) //|> w
,.abuf_wr_data (abuf_wr_data) //|> w
,.abuf_wr_en (abuf_wr_en) //|> w
,.dlv_data (dlv_data) //|> w
,.dlv_mask (dlv_mask) //|> w
,.dlv_pd (dlv_pd) //|> w
,.dlv_valid (dlv_valid) //|> w
,.dp2reg_sat_count (dp2reg_sat_count) //|> w
);
//==========================================================
// Delivery controller
//==========================================================
NV_NVDLA_CACC_delivery_ctrl u_delivery_ctrl (
.reg2dp_op_en (reg2dp_op_en) //|< w
,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w
,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w
,.reg2dp_dataout_width (reg2dp_dataout_width) //|< w
,.reg2dp_dataout_height (reg2dp_dataout_height) //|< w
,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|< w
,.reg2dp_dataout_addr (reg2dp_dataout_addr[31:5]) //|< w
,.reg2dp_line_packed (reg2dp_line_packed) //|< w
,.reg2dp_surf_packed (reg2dp_surf_packed) //|< w
,.reg2dp_batches (reg2dp_batches[4:0]) //|< w
,.reg2dp_line_stride (reg2dp_line_stride) //|< w
,.reg2dp_surf_stride (reg2dp_surf_stride) //|< w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cacc2sdp_ready (cacc2sdp_ready) //|< i
,.cacc2sdp_valid (cacc2sdp_valid) //|< o
,.dbuf_rd_ready (dbuf_rd_ready) //|< w
,.dlv_data (dlv_data) //|< w
,.dlv_mask (dlv_mask) //|< w
,.dlv_pd (dlv_pd) //|< w
,.dlv_valid (dlv_valid) //|< w
,.wait_for_op_en (wait_for_op_en) //|< w
,.dbuf_rd_addr (dbuf_rd_addr) //|> w
,.dbuf_rd_en (dbuf_rd_en) //|> w
,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|> w
,.dbuf_wr_addr (dbuf_wr_addr) //|> w
,.dbuf_wr_data (dbuf_wr_data) //|> w
,.dbuf_wr_en (dbuf_wr_en) //|> w
,.dp2reg_done (dp2reg_done) //|> w
);
//==========================================================
// Delivery buffer
//==========================================================
NV_NVDLA_CACC_delivery_buffer u_delivery_buffer (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.cacc2sdp_ready (cacc2sdp_ready) //|< i
,.dbuf_rd_addr (dbuf_rd_addr) //|< w
,.dbuf_rd_en (dbuf_rd_en) //|< w
,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|< w
,.dbuf_wr_addr (dbuf_wr_addr) //|< w
,.dbuf_wr_data (dbuf_wr_data) //|< w
,.dbuf_wr_en (dbuf_wr_en) //|< w
,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i
,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd) //|> o
,.cacc2sdp_pd (cacc2sdp_pd) //|> o
,.cacc2sdp_valid (cacc2sdp_valid) //|> o
,.dbuf_rd_ready (dbuf_rd_ready) //|> w
,.accu2sc_credit_size (accu2sc_credit_size) //|> o
,.accu2sc_credit_vld (accu2sc_credit_vld) //|> o
);
//==========================================================
// SLCG groups
//==========================================================
NV_NVDLA_CACC_slcg u_slcg_op_0 (
.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.slcg_en_src_0 (slcg_op_en[0]) //|< w
,.slcg_en_src_1 (1'b1) //|< ?
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w
);
NV_NVDLA_CACC_slcg u_slcg_op_1 (
.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.slcg_en_src_0 (slcg_op_en[1]) //|< w
,.slcg_en_src_1 (1'b1) //|< ?
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w
);
NV_NVDLA_CACC_slcg u_slcg_op_2 (
.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.slcg_en_src_0 (slcg_op_en[2]) //|< w
,.slcg_en_src_1 (1'b1) //|< ?
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w
);
NV_NVDLA_CACC_slcg u_slcg_cell_0 (
.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i
,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.slcg_en_src_0 (slcg_op_en[3]) //|< w
,.slcg_en_src_1 (slcg_cell_en) //|< w
,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i
,.nvdla_core_gated_clk (nvdla_cell_gated_clk) //|> w
);
endmodule // NV_NVDLA_cacc |
module NV_NVDLA_SDP_CORE_y (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,op_en_load //|< i
,pwrbus_ram_pd //|< i
,ew_alu_in_rdy //|> o
,ew_alu_in_data //|< i
,ew_alu_in_vld //|< i
,ew_mul_in_data //|< i
,ew_mul_in_vld //|< i
,ew_mul_in_rdy //|> o
,ew_data_in_pd //|< i
,ew_data_in_pvld //|< i
,ew_data_in_prdy //|> o
,reg2dp_nan_to_zero //|< i
,reg2dp_perf_lut_en //|< i
,reg2dp_proc_precision //|< i
,reg2dp_ew_alu_algo //|< i
,reg2dp_ew_alu_bypass //|< i
,reg2dp_ew_alu_cvt_bypass //|< i
,reg2dp_ew_alu_cvt_offset //|< i
,reg2dp_ew_alu_cvt_scale //|< i
,reg2dp_ew_alu_cvt_truncate //|< i
,reg2dp_ew_alu_operand //|< i
,reg2dp_ew_alu_src //|< i
,reg2dp_ew_lut_bypass //|< i
,reg2dp_ew_mul_bypass //|< i
,reg2dp_ew_mul_cvt_bypass //|< i
,reg2dp_ew_mul_cvt_offset //|< i
,reg2dp_ew_mul_cvt_scale //|< i
,reg2dp_ew_mul_cvt_truncate //|< i
,reg2dp_ew_mul_operand //|< i
,reg2dp_ew_mul_prelu //|< i
,reg2dp_ew_mul_src //|< i
,reg2dp_ew_truncate //|< i
,reg2dp_lut_hybrid_priority //|< i
,reg2dp_lut_int_access_type //|< i
,reg2dp_lut_int_addr //|< i
,reg2dp_lut_int_data //|< i
,reg2dp_lut_int_data_wr //|< i
,reg2dp_lut_int_table_id //|< i
,reg2dp_lut_le_end //|< i
,reg2dp_lut_le_function //|< i
,reg2dp_lut_le_index_offset //|< i
,reg2dp_lut_le_index_select //|< i
,reg2dp_lut_le_slope_oflow_scale //|< i
,reg2dp_lut_le_slope_oflow_shift //|< i
,reg2dp_lut_le_slope_uflow_scale //|< i
,reg2dp_lut_le_slope_uflow_shift //|< i
,reg2dp_lut_le_start //|< i
,reg2dp_lut_lo_end //|< i
,reg2dp_lut_lo_index_select //|< i
,reg2dp_lut_lo_slope_oflow_scale //|< i
,reg2dp_lut_lo_slope_oflow_shift //|< i
,reg2dp_lut_lo_slope_uflow_scale //|< i
,reg2dp_lut_lo_slope_uflow_shift //|< i
,reg2dp_lut_lo_start //|< i
,reg2dp_lut_oflow_priority //|< i
,reg2dp_lut_uflow_priority //|< i
,dp2reg_lut_hybrid //|> o
,dp2reg_lut_int_data //|> o
,dp2reg_lut_le_hit //|> o
,dp2reg_lut_lo_hit //|> o
,dp2reg_lut_oflow //|> o
,dp2reg_lut_uflow //|> o
,ew_data_out_pd //|> o
,ew_data_out_pvld //|> o
,ew_data_out_prdy //|< i
);
input nvdla_core_clk;
input nvdla_core_rstn;
input [16*4 -1:0] ew_alu_in_data;
input ew_alu_in_vld;
output ew_alu_in_rdy;
input [32*4 -1:0] ew_data_in_pd;
input ew_data_in_pvld;
output ew_data_in_prdy;
input [16*4 -1:0] ew_mul_in_data;
input ew_mul_in_vld;
output ew_mul_in_rdy;
output [32*4 -1:0] ew_data_out_pd;
output ew_data_out_pvld;
input ew_data_out_prdy;
input [1:0] reg2dp_ew_alu_algo;
input reg2dp_ew_alu_bypass;
input reg2dp_ew_alu_cvt_bypass;
input [31:0] reg2dp_ew_alu_cvt_offset;
input [15:0] reg2dp_ew_alu_cvt_scale;
input [5:0] reg2dp_ew_alu_cvt_truncate;
input [31:0] reg2dp_ew_alu_operand;
input reg2dp_ew_alu_src;
input reg2dp_ew_lut_bypass;
input reg2dp_ew_mul_bypass;
input reg2dp_ew_mul_cvt_bypass;
input [31:0] reg2dp_ew_mul_cvt_offset;
input [15:0] reg2dp_ew_mul_cvt_scale;
input [5:0] reg2dp_ew_mul_cvt_truncate;
input [31:0] reg2dp_ew_mul_operand;
input reg2dp_ew_mul_prelu;
input reg2dp_ew_mul_src;
input [9:0] reg2dp_ew_truncate;
input reg2dp_lut_hybrid_priority;
input reg2dp_lut_int_access_type;
input [9:0] reg2dp_lut_int_addr;
input [15:0] reg2dp_lut_int_data;
input reg2dp_lut_int_data_wr;
input reg2dp_lut_int_table_id;
input [31:0] reg2dp_lut_le_end;
input reg2dp_lut_le_function;
input [7:0] reg2dp_lut_le_index_offset;
input [7:0] reg2dp_lut_le_index_select;
input [15:0] reg2dp_lut_le_slope_oflow_scale;
input [4:0] reg2dp_lut_le_slope_oflow_shift;
input [15:0] reg2dp_lut_le_slope_uflow_scale;
input [4:0] reg2dp_lut_le_slope_uflow_shift;
input [31:0] reg2dp_lut_le_start;
input [31:0] reg2dp_lut_lo_end;
input [7:0] reg2dp_lut_lo_index_select;
input [15:0] reg2dp_lut_lo_slope_oflow_scale;
input [4:0] reg2dp_lut_lo_slope_oflow_shift;
input [15:0] reg2dp_lut_lo_slope_uflow_scale;
input [4:0] reg2dp_lut_lo_slope_uflow_shift;
input [31:0] reg2dp_lut_lo_start;
input reg2dp_lut_oflow_priority;
input reg2dp_lut_uflow_priority;
output [31:0] dp2reg_lut_hybrid;
output [15:0] dp2reg_lut_int_data;
output [31:0] dp2reg_lut_le_hit;
output [31:0] dp2reg_lut_lo_hit;
output [31:0] dp2reg_lut_oflow;
output [31:0] dp2reg_lut_uflow;
input reg2dp_nan_to_zero;
input reg2dp_perf_lut_en;
input [1:0] reg2dp_proc_precision;
//&Ports /^cfg/;
input [31:0] pwrbus_ram_pd;
input op_en_load;
reg [1:0] cfg_ew_alu_algo;
reg cfg_ew_alu_bypass;
reg cfg_ew_alu_cvt_bypass;
reg [31:0] cfg_ew_alu_cvt_offset;
reg [15:0] cfg_ew_alu_cvt_scale;
reg [5:0] cfg_ew_alu_cvt_truncate;
reg [31:0] cfg_ew_alu_operand;
reg cfg_ew_alu_src;
reg cfg_ew_lut_bypass;
reg cfg_ew_mul_bypass;
reg cfg_ew_mul_cvt_bypass;
reg [31:0] cfg_ew_mul_cvt_offset;
reg [15:0] cfg_ew_mul_cvt_scale;
reg [5:0] cfg_ew_mul_cvt_truncate;
reg [31:0] cfg_ew_mul_operand;
reg cfg_ew_mul_prelu;
reg cfg_ew_mul_src;
reg [9:0] cfg_ew_truncate;
reg cfg_lut_hybrid_priority;
reg [31:0] cfg_lut_le_end;
reg cfg_lut_le_function;
reg [7:0] cfg_lut_le_index_offset;
reg [7:0] cfg_lut_le_index_select;
reg [15:0] cfg_lut_le_slope_oflow_scale;
reg [4:0] cfg_lut_le_slope_oflow_shift;
reg [15:0] cfg_lut_le_slope_uflow_scale;
reg [4:0] cfg_lut_le_slope_uflow_shift;
reg [31:0] cfg_lut_le_start;
reg [31:0] cfg_lut_lo_end;
reg [7:0] cfg_lut_lo_index_select;
reg [15:0] cfg_lut_lo_slope_oflow_scale;
reg [4:0] cfg_lut_lo_slope_oflow_shift;
reg [15:0] cfg_lut_lo_slope_uflow_scale;
reg [4:0] cfg_lut_lo_slope_uflow_shift;
reg [31:0] cfg_lut_lo_start;
reg cfg_lut_oflow_priority;
reg cfg_lut_uflow_priority;
reg cfg_nan_to_zero;
reg [1:0] cfg_proc_precision;
wire [32*4 -1:0] alu_cvt_out_pd;
wire alu_cvt_out_prdy;
wire alu_cvt_out_pvld;
wire [32*4 -1:0] mul_cvt_out_pd;
wire mul_cvt_out_prdy;
wire mul_cvt_out_pvld;
wire [32*4 -1:0] core_out_pd;
wire core_out_prdy;
wire core_out_pvld;
wire [81*4 -1:0] idx2lut_pd;
wire idx2lut_prdy;
wire idx2lut_pvld;
wire [32*4 -1:0] idx_in_pd;
wire idx_in_prdy;
wire idx_in_pvld;
wire [32*4 -1:0] inp_out_pd;
wire inp_out_prdy;
wire inp_out_pvld;
wire [185*4 -1:0] lut2inp_pd;
wire lut2inp_prdy;
wire lut2inp_pvld;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
if (!nvdla_core_rstn) begin
cfg_proc_precision <= {2{1'b0}};
cfg_nan_to_zero <= 1'b0;
cfg_ew_alu_operand <= {32{1'b0}};
cfg_ew_alu_bypass <= 1'b0;
cfg_ew_alu_algo <= {2{1'b0}};
cfg_ew_alu_src <= 1'b0;
cfg_ew_alu_cvt_bypass <= 1'b0;
cfg_ew_alu_cvt_offset <= {32{1'b0}};
cfg_ew_alu_cvt_scale <= {16{1'b0}};
cfg_ew_alu_cvt_truncate <= {6{1'b0}};
cfg_ew_mul_operand <= {32{1'b0}};
cfg_ew_mul_bypass <= 1'b0;
cfg_ew_mul_src <= 1'b0;
cfg_ew_mul_cvt_bypass <= 1'b0;
cfg_ew_mul_cvt_offset <= {32{1'b0}};
cfg_ew_mul_cvt_scale <= {16{1'b0}};
cfg_ew_mul_cvt_truncate <= {6{1'b0}};
cfg_ew_truncate <= {10{1'b0}};
cfg_ew_mul_prelu <= 1'b0;
cfg_ew_lut_bypass <= 1'b0;
cfg_lut_le_start <= {32{1'b0}};
cfg_lut_le_end <= {32{1'b0}};
cfg_lut_lo_start <= {32{1'b0}};
cfg_lut_lo_end <= {32{1'b0}};
cfg_lut_le_index_offset <= {8{1'b0}};
cfg_lut_le_index_select <= {8{1'b0}};
cfg_lut_lo_index_select <= {8{1'b0}};
cfg_lut_le_function <= 1'b0;
cfg_lut_uflow_priority <= 1'b0;
cfg_lut_oflow_priority <= 1'b0;
cfg_lut_hybrid_priority <= 1'b0;
cfg_lut_le_slope_oflow_scale <= {16{1'b0}};
cfg_lut_le_slope_oflow_shift <= {5{1'b0}};
cfg_lut_le_slope_uflow_scale <= {16{1'b0}};
cfg_lut_le_slope_uflow_shift <= {5{1'b0}};
cfg_lut_lo_slope_oflow_scale <= {16{1'b0}};
cfg_lut_lo_slope_oflow_shift <= {5{1'b0}};
cfg_lut_lo_slope_uflow_scale <= {16{1'b0}};
cfg_lut_lo_slope_uflow_shift <= {5{1'b0}};
end else begin
if (op_en_load) begin
cfg_proc_precision <= reg2dp_proc_precision ;
cfg_nan_to_zero <= reg2dp_nan_to_zero ;
cfg_ew_alu_operand <= reg2dp_ew_alu_operand ;
cfg_ew_alu_bypass <= reg2dp_ew_alu_bypass ;
cfg_ew_alu_algo <= reg2dp_ew_alu_algo ;
cfg_ew_alu_src <= reg2dp_ew_alu_src ;
cfg_ew_alu_cvt_bypass <= reg2dp_ew_alu_cvt_bypass ;
cfg_ew_alu_cvt_offset <= reg2dp_ew_alu_cvt_offset ;
cfg_ew_alu_cvt_scale <= reg2dp_ew_alu_cvt_scale ;
cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate;
cfg_ew_mul_operand <= reg2dp_ew_mul_operand ;
cfg_ew_mul_bypass <= reg2dp_ew_mul_bypass ;
cfg_ew_mul_src <= reg2dp_ew_mul_src ;
cfg_ew_mul_cvt_bypass <= reg2dp_ew_mul_cvt_bypass ;
cfg_ew_mul_cvt_offset <= reg2dp_ew_mul_cvt_offset ;
cfg_ew_mul_cvt_scale <= reg2dp_ew_mul_cvt_scale ;
cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate;
cfg_ew_truncate <= reg2dp_ew_truncate ;
cfg_ew_mul_prelu <= reg2dp_ew_mul_prelu ;
cfg_ew_lut_bypass <= reg2dp_ew_lut_bypass ;
cfg_lut_le_start <= reg2dp_lut_le_start ;
cfg_lut_le_end <= reg2dp_lut_le_end ;
cfg_lut_lo_start <= reg2dp_lut_lo_start ;
cfg_lut_lo_end <= reg2dp_lut_lo_end ;
cfg_lut_le_index_offset <= reg2dp_lut_le_index_offset;
cfg_lut_le_index_select <= reg2dp_lut_le_index_select;
cfg_lut_lo_index_select <= reg2dp_lut_lo_index_select;
cfg_lut_le_function <= reg2dp_lut_le_function ;
cfg_lut_uflow_priority <= reg2dp_lut_uflow_priority ;
cfg_lut_oflow_priority <= reg2dp_lut_oflow_priority ;
cfg_lut_hybrid_priority <= reg2dp_lut_hybrid_priority;
cfg_lut_le_slope_oflow_scale <= reg2dp_lut_le_slope_oflow_scale;
cfg_lut_le_slope_oflow_shift <= reg2dp_lut_le_slope_oflow_shift;
cfg_lut_le_slope_uflow_scale <= reg2dp_lut_le_slope_uflow_scale;
cfg_lut_le_slope_uflow_shift <= reg2dp_lut_le_slope_uflow_shift;
cfg_lut_lo_slope_oflow_scale <= reg2dp_lut_lo_slope_oflow_scale;
cfg_lut_lo_slope_oflow_shift <= reg2dp_lut_lo_slope_oflow_shift;
cfg_lut_lo_slope_uflow_scale <= reg2dp_lut_lo_slope_uflow_scale;
cfg_lut_lo_slope_uflow_shift <= reg2dp_lut_lo_slope_uflow_shift;
end
end
end
//===========================================
// y input pipe
//===========================================
//=================================================
NV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt (
.cfg_cvt_bypass (cfg_ew_alu_cvt_bypass) //|< r
,.cfg_cvt_offset (cfg_ew_alu_cvt_offset[31:0]) //|< r
,.cfg_cvt_scale (cfg_ew_alu_cvt_scale[15:0]) //|< r
,.cfg_cvt_truncate (cfg_ew_alu_cvt_truncate[5:0]) //|< r
,.cvt_data_in (ew_alu_in_data[16*4 -1:0]) //|< w
,.cvt_in_pvld (ew_alu_in_vld) //|< w
,.cvt_in_prdy (ew_alu_in_rdy) //|> w
,.cvt_out_prdy (alu_cvt_out_prdy) //|< w
,.cvt_data_out (alu_cvt_out_pd[32*4 -1:0]) //|> w
,.cvt_out_pvld (alu_cvt_out_pvld) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt (
.cfg_cvt_bypass (cfg_ew_mul_cvt_bypass) //|< r
,.cfg_cvt_offset (cfg_ew_mul_cvt_offset[31:0]) //|< r
,.cfg_cvt_scale (cfg_ew_mul_cvt_scale[15:0]) //|< r
,.cfg_cvt_truncate (cfg_ew_mul_cvt_truncate[5:0]) //|< r
,.cvt_data_in (ew_mul_in_data[16*4 -1:0]) //|< w
,.cvt_in_pvld (ew_mul_in_vld) //|< w
,.cvt_in_prdy (ew_mul_in_rdy) //|> w
,.cvt_out_prdy (mul_cvt_out_prdy) //|< w
,.cvt_data_out (mul_cvt_out_pd[32*4 -1:0]) //|> w
,.cvt_out_pvld (mul_cvt_out_pvld) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_HLS_Y_int_core u_core (
.cfg_alu_algo (cfg_ew_alu_algo[1:0]) //|< r
,.cfg_alu_bypass (cfg_ew_alu_bypass) //|< r
,.cfg_alu_op (cfg_ew_alu_operand[31:0]) //|< r
,.cfg_alu_src (cfg_ew_alu_src) //|< r
,.cfg_mul_bypass (cfg_ew_mul_bypass) //|< r
,.cfg_mul_op (cfg_ew_mul_operand[31:0]) //|< r
,.cfg_mul_prelu (cfg_ew_mul_prelu) //|< r
,.cfg_mul_src (cfg_ew_mul_src) //|< r
,.cfg_mul_truncate (cfg_ew_truncate[9:0]) //|< r
,.chn_alu_op (alu_cvt_out_pd[32*4 -1:0]) //|< w
,.chn_alu_op_pvld (alu_cvt_out_pvld) //|< w
,.chn_data_in (ew_data_in_pd[32*4 -1:0]) //|< w
,.chn_in_pvld (ew_data_in_pvld) //|< w
,.chn_in_prdy (ew_data_in_prdy) //|> w
,.chn_mul_op (mul_cvt_out_pd[32*4 -1:0]) //|< w
,.chn_mul_op_pvld (mul_cvt_out_pvld) //|< w
,.chn_alu_op_prdy (alu_cvt_out_prdy) //|> w
,.chn_mul_op_prdy (mul_cvt_out_prdy) //|> w
,.chn_data_out (core_out_pd[32*4 -1:0]) //|> w
,.chn_out_pvld (core_out_pvld) //|> w
,.chn_out_prdy (core_out_prdy) //|< w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
assign core_out_prdy = cfg_ew_lut_bypass ? ew_data_out_prdy : idx_in_prdy;
assign idx_in_pvld = cfg_ew_lut_bypass ? 1'b0 : core_out_pvld;
assign idx_in_pd = {32*4{idx_in_pvld}} & core_out_pd;
NV_NVDLA_SDP_HLS_Y_idx_top u_idx (
.cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< r
,.cfg_lut_le_function (cfg_lut_le_function) //|< r
,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< r
,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< r
,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< r
,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< r
,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< r
,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< r
,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< r
,.chn_lut_in_pd (idx_in_pd[32*4 -1:0]) //|< w
,.chn_lut_in_pvld (idx_in_pvld) //|< w
,.chn_lut_out_prdy (idx2lut_prdy) //|< w
,.chn_lut_in_prdy (idx_in_prdy) //|> w
,.chn_lut_out_pd (idx2lut_pd[81*4 -1:0]) //|> w
,.chn_lut_out_pvld (idx2lut_pvld) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_CORE_Y_lut u_lut (
.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
,.lut2inp_pvld (lut2inp_pvld) //|> w
,.lut2inp_prdy (lut2inp_prdy) //|< w
,.lut2inp_pd (lut2inp_pd[185*4 -1:0]) //|> w
,.idx2lut_pvld (idx2lut_pvld) //|< w
,.idx2lut_prdy (idx2lut_prdy) //|> w
,.idx2lut_pd (idx2lut_pd[81*4 -1:0]) //|< w
,.reg2dp_lut_int_access_type (reg2dp_lut_int_access_type) //|< i
,.reg2dp_lut_int_addr (reg2dp_lut_int_addr[9:0]) //|< i
,.reg2dp_lut_int_data (reg2dp_lut_int_data[15:0]) //|< i
,.reg2dp_lut_int_data_wr (reg2dp_lut_int_data_wr) //|< i
,.reg2dp_lut_int_table_id (reg2dp_lut_int_table_id) //|< i
,.reg2dp_lut_le_end (cfg_lut_le_end[31:0]) //|< r
,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i
,.reg2dp_lut_le_slope_oflow_scale (cfg_lut_le_slope_oflow_scale[15:0]) //|< r
,.reg2dp_lut_le_slope_oflow_shift (cfg_lut_le_slope_oflow_shift[4:0]) //|< r
,.reg2dp_lut_le_slope_uflow_scale (cfg_lut_le_slope_uflow_scale[15:0]) //|< r
,.reg2dp_lut_le_slope_uflow_shift (cfg_lut_le_slope_uflow_shift[4:0]) //|< r
,.reg2dp_lut_le_start (cfg_lut_le_start[31:0]) //|< r
,.reg2dp_lut_lo_end (cfg_lut_lo_end[31:0]) //|< r
,.reg2dp_lut_lo_slope_oflow_scale (cfg_lut_lo_slope_oflow_scale[15:0]) //|< r
,.reg2dp_lut_lo_slope_oflow_shift (cfg_lut_lo_slope_oflow_shift[4:0]) //|< r
,.reg2dp_lut_lo_slope_uflow_scale (cfg_lut_lo_slope_uflow_scale[15:0]) //|< r
,.reg2dp_lut_lo_slope_uflow_shift (cfg_lut_lo_slope_uflow_shift[4:0]) //|< r
,.reg2dp_lut_lo_start (cfg_lut_lo_start[31:0]) //|< r
,.reg2dp_perf_lut_en (reg2dp_perf_lut_en) //|< i
,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i
,.dp2reg_lut_hybrid (dp2reg_lut_hybrid[31:0]) //|> o
,.dp2reg_lut_int_data (dp2reg_lut_int_data[15:0]) //|> o
,.dp2reg_lut_le_hit (dp2reg_lut_le_hit[31:0]) //|> o
,.dp2reg_lut_lo_hit (dp2reg_lut_lo_hit[31:0]) //|> o
,.dp2reg_lut_oflow (dp2reg_lut_oflow[31:0]) //|> o
,.dp2reg_lut_uflow (dp2reg_lut_uflow[31:0]) //|> o
,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i
,.op_en_load (op_en_load) //|< i
);
NV_NVDLA_SDP_HLS_Y_inp_top u_inp (
.chn_inp_in_pd (lut2inp_pd[185*4 -1:0]) //|< w
,.chn_inp_in_pvld (lut2inp_pvld) //|< w
,.chn_inp_out_prdy (inp_out_prdy) //|< w
,.chn_inp_in_prdy (lut2inp_prdy) //|> w
,.chn_inp_out_pd (inp_out_pd[32*4 -1:0]) //|> w
,.chn_inp_out_pvld (inp_out_pvld) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
assign ew_data_out_pvld = cfg_ew_lut_bypass ? core_out_pvld : inp_out_pvld;
assign ew_data_out_pd = cfg_ew_lut_bypass ? core_out_pd : inp_out_pd;
assign inp_out_prdy = cfg_ew_lut_bypass ? 1'b0 : ew_data_out_prdy;
endmodule // NV_NVDLA_SDP_CORE_y |
module NV_NVDLA_SDP_HLS_Y_inp_top (
chn_inp_in_pd //|< i
,chn_inp_in_pvld //|< i
,chn_inp_out_prdy //|< i
,nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,chn_inp_in_prdy //|> o
,chn_inp_out_pd //|> o
,chn_inp_out_pvld //|> o
);
input [185*4 -1:0] chn_inp_in_pd;
input chn_inp_in_pvld;
input chn_inp_out_prdy;
output chn_inp_in_prdy;
output [32*4 -1:0] chn_inp_out_pd;
output chn_inp_out_pvld;
input nvdla_core_clk;
input nvdla_core_rstn;
//: my $k=4;
//: my $bf =4*32;
//: my $by0=4*(32+35);
//: my $by1=4*(32+35+16);
//: my $bsc=4*(32+35+32);
//: my $bsf=4*(32+35+48);
//: my $bof=4*(32+35+48+5);
//: my $bbs=4*(32+35+85);
//: my $bfw=4*(32+35+85+32);
//: foreach my $i (0..${k}-1) {
//: print qq(
//: wire chn_inp_in_prdy${i};
//: wire [31:0] chn_inp_out_data${i};
//: wire chn_inp_out_pvld${i};
//: wire [31:0] inp_in_bias${i};
//: wire inp_in_flow${i};
//: wire [34:0] inp_in_fraction${i};
//: wire [31:0] inp_in_offset${i};
//: wire [15:0] inp_in_scale${i};
//: wire [4:0] inp_in_shift${i};
//: wire [31:0] inp_in_x${i};
//: wire [15:0] inp_in_y0_${i};
//: wire [15:0] inp_in_y1_${i};
//: );
//: }
//: print "\n";
//:
//: foreach my $i (0..${k}-1) {
//: print "assign chn_inp_out_pd[32*${i}+31:32*${i}] = chn_inp_out_data${i}; \n";
//: }
//: print "\n";
//:
//: foreach my $i (0..${k}-1) {
//: print qq(
//: NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_${i} (
//: .inp_bias_in (inp_in_bias${i}[31:0]) //|< w
//: ,.inp_flow_in (inp_in_flow${i}) //|< w
//: ,.inp_frac_in (inp_in_fraction${i}[34:0]) //|< w
//: ,.inp_in_pvld (chn_inp_in_pvld) //|< i
//: ,.inp_offset_in (inp_in_offset${i}[31:0]) //|< w
//: ,.inp_out_prdy (chn_inp_out_prdy) //|< i
//: ,.inp_scale_in (inp_in_scale${i}[15:0]) //|< w
//: ,.inp_shift_in (inp_in_shift${i}[4:0]) //|< w
//: ,.inp_x_in (inp_in_x${i}[31:0]) //|< w
//: ,.inp_y0_in (inp_in_y0_${i}[15:0]) //|< w
//: ,.inp_y1_in (inp_in_y1_${i}[15:0]) //|< w
//: ,.inp_data_out (chn_inp_out_data${i}[31:0]) //|> w
//: ,.inp_in_prdy (chn_inp_in_prdy${i}) //|> w
//: ,.inp_out_pvld (chn_inp_out_pvld${i}) //|> w
//: ,.nvdla_core_clk (nvdla_core_clk) //|< i
//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i
//: );
//: );
//: }
//: print "\n";
//:
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_x${i}[31:0] = chn_inp_in_pd[32*${i}+31:32*${i}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_fraction${i}[34:0] = chn_inp_in_pd[35*${i}+${bf}+34:35*${i}+${bf}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_y0_${i}[15:0] = chn_inp_in_pd[16*${i}+${by0}+15:16*${i}+${by0}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_y1_${i}[15:0] = chn_inp_in_pd[16*${i}+${by1}+15:16*${i}+${by1}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_scale${i}[15:0] = chn_inp_in_pd[16*${i}+${bsc}+15:16*${i}+${bsc}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_shift${i}[4:0] = chn_inp_in_pd[5*${i}+${bsf}+4:5*${i}+${bsf}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_offset${i}[31:0] = chn_inp_in_pd[32*${i}+${bof}+31:32*${i}+${bof}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_bias${i}[31:0] = chn_inp_in_pd[32*${i}+${bbs}+31:32*${i}+${bbs}]; \n";
//: }
//: foreach my $i (0..${k}-1) {
//: print "assign inp_in_flow${i} = chn_inp_in_pd[${i}+${bfw}]; \n";
//: }
//: print "\n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire chn_inp_in_prdy0;
wire [31:0] chn_inp_out_data0;
wire chn_inp_out_pvld0;
wire [31:0] inp_in_bias0;
wire inp_in_flow0;
wire [34:0] inp_in_fraction0;
wire [31:0] inp_in_offset0;
wire [15:0] inp_in_scale0;
wire [4:0] inp_in_shift0;
wire [31:0] inp_in_x0;
wire [15:0] inp_in_y0_0;
wire [15:0] inp_in_y1_0;
wire chn_inp_in_prdy1;
wire [31:0] chn_inp_out_data1;
wire chn_inp_out_pvld1;
wire [31:0] inp_in_bias1;
wire inp_in_flow1;
wire [34:0] inp_in_fraction1;
wire [31:0] inp_in_offset1;
wire [15:0] inp_in_scale1;
wire [4:0] inp_in_shift1;
wire [31:0] inp_in_x1;
wire [15:0] inp_in_y0_1;
wire [15:0] inp_in_y1_1;
wire chn_inp_in_prdy2;
wire [31:0] chn_inp_out_data2;
wire chn_inp_out_pvld2;
wire [31:0] inp_in_bias2;
wire inp_in_flow2;
wire [34:0] inp_in_fraction2;
wire [31:0] inp_in_offset2;
wire [15:0] inp_in_scale2;
wire [4:0] inp_in_shift2;
wire [31:0] inp_in_x2;
wire [15:0] inp_in_y0_2;
wire [15:0] inp_in_y1_2;
wire chn_inp_in_prdy3;
wire [31:0] chn_inp_out_data3;
wire chn_inp_out_pvld3;
wire [31:0] inp_in_bias3;
wire inp_in_flow3;
wire [34:0] inp_in_fraction3;
wire [31:0] inp_in_offset3;
wire [15:0] inp_in_scale3;
wire [4:0] inp_in_shift3;
wire [31:0] inp_in_x3;
wire [15:0] inp_in_y0_3;
wire [15:0] inp_in_y1_3;
assign chn_inp_out_pd[32*0+31:32*0] = chn_inp_out_data0;
assign chn_inp_out_pd[32*1+31:32*1] = chn_inp_out_data1;
assign chn_inp_out_pd[32*2+31:32*2] = chn_inp_out_data2;
assign chn_inp_out_pd[32*3+31:32*3] = chn_inp_out_data3;
NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_0 (
.inp_bias_in (inp_in_bias0[31:0]) //|< w
,.inp_flow_in (inp_in_flow0) //|< w
,.inp_frac_in (inp_in_fraction0[34:0]) //|< w
,.inp_in_pvld (chn_inp_in_pvld) //|< i
,.inp_offset_in (inp_in_offset0[31:0]) //|< w
,.inp_out_prdy (chn_inp_out_prdy) //|< i
,.inp_scale_in (inp_in_scale0[15:0]) //|< w
,.inp_shift_in (inp_in_shift0[4:0]) //|< w
,.inp_x_in (inp_in_x0[31:0]) //|< w
,.inp_y0_in (inp_in_y0_0[15:0]) //|< w
,.inp_y1_in (inp_in_y1_0[15:0]) //|< w
,.inp_data_out (chn_inp_out_data0[31:0]) //|> w
,.inp_in_prdy (chn_inp_in_prdy0) //|> w
,.inp_out_pvld (chn_inp_out_pvld0) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_1 (
.inp_bias_in (inp_in_bias1[31:0]) //|< w
,.inp_flow_in (inp_in_flow1) //|< w
,.inp_frac_in (inp_in_fraction1[34:0]) //|< w
,.inp_in_pvld (chn_inp_in_pvld) //|< i
,.inp_offset_in (inp_in_offset1[31:0]) //|< w
,.inp_out_prdy (chn_inp_out_prdy) //|< i
,.inp_scale_in (inp_in_scale1[15:0]) //|< w
,.inp_shift_in (inp_in_shift1[4:0]) //|< w
,.inp_x_in (inp_in_x1[31:0]) //|< w
,.inp_y0_in (inp_in_y0_1[15:0]) //|< w
,.inp_y1_in (inp_in_y1_1[15:0]) //|< w
,.inp_data_out (chn_inp_out_data1[31:0]) //|> w
,.inp_in_prdy (chn_inp_in_prdy1) //|> w
,.inp_out_pvld (chn_inp_out_pvld1) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_2 (
.inp_bias_in (inp_in_bias2[31:0]) //|< w
,.inp_flow_in (inp_in_flow2) //|< w
,.inp_frac_in (inp_in_fraction2[34:0]) //|< w
,.inp_in_pvld (chn_inp_in_pvld) //|< i
,.inp_offset_in (inp_in_offset2[31:0]) //|< w
,.inp_out_prdy (chn_inp_out_prdy) //|< i
,.inp_scale_in (inp_in_scale2[15:0]) //|< w
,.inp_shift_in (inp_in_shift2[4:0]) //|< w
,.inp_x_in (inp_in_x2[31:0]) //|< w
,.inp_y0_in (inp_in_y0_2[15:0]) //|< w
,.inp_y1_in (inp_in_y1_2[15:0]) //|< w
,.inp_data_out (chn_inp_out_data2[31:0]) //|> w
,.inp_in_prdy (chn_inp_in_prdy2) //|> w
,.inp_out_pvld (chn_inp_out_pvld2) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_3 (
.inp_bias_in (inp_in_bias3[31:0]) //|< w
,.inp_flow_in (inp_in_flow3) //|< w
,.inp_frac_in (inp_in_fraction3[34:0]) //|< w
,.inp_in_pvld (chn_inp_in_pvld) //|< i
,.inp_offset_in (inp_in_offset3[31:0]) //|< w
,.inp_out_prdy (chn_inp_out_prdy) //|< i
,.inp_scale_in (inp_in_scale3[15:0]) //|< w
,.inp_shift_in (inp_in_shift3[4:0]) //|< w
,.inp_x_in (inp_in_x3[31:0]) //|< w
,.inp_y0_in (inp_in_y0_3[15:0]) //|< w
,.inp_y1_in (inp_in_y1_3[15:0]) //|< w
,.inp_data_out (chn_inp_out_data3[31:0]) //|> w
,.inp_in_prdy (chn_inp_in_prdy3) //|> w
,.inp_out_pvld (chn_inp_out_pvld3) //|> w
,.nvdla_core_clk (nvdla_core_clk) //|< i
,.nvdla_core_rstn (nvdla_core_rstn) //|< i
);
assign inp_in_x0[31:0] = chn_inp_in_pd[32*0+31:32*0];
assign inp_in_x1[31:0] = chn_inp_in_pd[32*1+31:32*1];
assign inp_in_x2[31:0] = chn_inp_in_pd[32*2+31:32*2];
assign inp_in_x3[31:0] = chn_inp_in_pd[32*3+31:32*3];
assign inp_in_fraction0[34:0] = chn_inp_in_pd[35*0+128+34:35*0+128];
assign inp_in_fraction1[34:0] = chn_inp_in_pd[35*1+128+34:35*1+128];
assign inp_in_fraction2[34:0] = chn_inp_in_pd[35*2+128+34:35*2+128];
assign inp_in_fraction3[34:0] = chn_inp_in_pd[35*3+128+34:35*3+128];
assign inp_in_y0_0[15:0] = chn_inp_in_pd[16*0+268+15:16*0+268];
assign inp_in_y0_1[15:0] = chn_inp_in_pd[16*1+268+15:16*1+268];
assign inp_in_y0_2[15:0] = chn_inp_in_pd[16*2+268+15:16*2+268];
assign inp_in_y0_3[15:0] = chn_inp_in_pd[16*3+268+15:16*3+268];
assign inp_in_y1_0[15:0] = chn_inp_in_pd[16*0+332+15:16*0+332];
assign inp_in_y1_1[15:0] = chn_inp_in_pd[16*1+332+15:16*1+332];
assign inp_in_y1_2[15:0] = chn_inp_in_pd[16*2+332+15:16*2+332];
assign inp_in_y1_3[15:0] = chn_inp_in_pd[16*3+332+15:16*3+332];
assign inp_in_scale0[15:0] = chn_inp_in_pd[16*0+396+15:16*0+396];
assign inp_in_scale1[15:0] = chn_inp_in_pd[16*1+396+15:16*1+396];
assign inp_in_scale2[15:0] = chn_inp_in_pd[16*2+396+15:16*2+396];
assign inp_in_scale3[15:0] = chn_inp_in_pd[16*3+396+15:16*3+396];
assign inp_in_shift0[4:0] = chn_inp_in_pd[5*0+460+4:5*0+460];
assign inp_in_shift1[4:0] = chn_inp_in_pd[5*1+460+4:5*1+460];
assign inp_in_shift2[4:0] = chn_inp_in_pd[5*2+460+4:5*2+460];
assign inp_in_shift3[4:0] = chn_inp_in_pd[5*3+460+4:5*3+460];
assign inp_in_offset0[31:0] = chn_inp_in_pd[32*0+480+31:32*0+480];
assign inp_in_offset1[31:0] = chn_inp_in_pd[32*1+480+31:32*1+480];
assign inp_in_offset2[31:0] = chn_inp_in_pd[32*2+480+31:32*2+480];
assign inp_in_offset3[31:0] = chn_inp_in_pd[32*3+480+31:32*3+480];
assign inp_in_bias0[31:0] = chn_inp_in_pd[32*0+608+31:32*0+608];
assign inp_in_bias1[31:0] = chn_inp_in_pd[32*1+608+31:32*1+608];
assign inp_in_bias2[31:0] = chn_inp_in_pd[32*2+608+31:32*2+608];
assign inp_in_bias3[31:0] = chn_inp_in_pd[32*3+608+31:32*3+608];
assign inp_in_flow0 = chn_inp_in_pd[0+736];
assign inp_in_flow1 = chn_inp_in_pd[1+736];
assign inp_in_flow2 = chn_inp_in_pd[2+736];
assign inp_in_flow3 = chn_inp_in_pd[3+736];
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign chn_inp_in_prdy = chn_inp_in_prdy0;
assign chn_inp_out_pvld = chn_inp_out_pvld0;
endmodule // NV_NVDLA_SDP_HLS_Y_inp_top |
module NV_NVDLA_CDP_DP_LUT_ctrl (
nvdla_core_clk //|< i
,nvdla_core_rstn //|< i
,dp2lut_prdy //|< i
,reg2dp_lut_le_function //|< i
,reg2dp_lut_le_index_offset //|< i
,reg2dp_lut_le_index_select //|< i
,reg2dp_lut_le_start_high //|< i
,reg2dp_lut_le_start_low //|< i
,reg2dp_lut_lo_index_select //|< i
,reg2dp_lut_lo_start_high //|< i
,reg2dp_lut_lo_start_low //|< i
,reg2dp_sqsum_bypass //|< i
,sum2itp_pd //|< i
,sum2itp_pvld //|< i
,sum2sync_prdy //|< i
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: ,dp2lut_X_entry_${m}
//: ,dp2lut_Xinfo_${m}
//: ,dp2lut_Y_entry_${m}
//: ,dp2lut_Yinfo_${m}
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
,dp2lut_X_entry_0
,dp2lut_Xinfo_0
,dp2lut_Y_entry_0
,dp2lut_Yinfo_0
,dp2lut_X_entry_1
,dp2lut_Xinfo_1
,dp2lut_Y_entry_1
,dp2lut_Yinfo_1
,dp2lut_X_entry_2
,dp2lut_Xinfo_2
,dp2lut_Y_entry_2
,dp2lut_Yinfo_2
,dp2lut_X_entry_3
,dp2lut_Xinfo_3
,dp2lut_Y_entry_3
,dp2lut_Yinfo_3
,dp2lut_X_entry_4
,dp2lut_Xinfo_4
,dp2lut_Y_entry_4
,dp2lut_Yinfo_4
,dp2lut_X_entry_5
,dp2lut_Xinfo_5
,dp2lut_Y_entry_5
,dp2lut_Yinfo_5
,dp2lut_X_entry_6
,dp2lut_Xinfo_6
,dp2lut_Y_entry_6
,dp2lut_Yinfo_6
,dp2lut_X_entry_7
,dp2lut_Xinfo_7
,dp2lut_Y_entry_7
,dp2lut_Yinfo_7
//| eperl: generated_end (DO NOT EDIT ABOVE)
,dp2lut_pvld //|> o
,sum2itp_prdy //|> o
,sum2sync_pd //|> o
,sum2sync_pvld //|> o
);
////////////////////////////////////////////////////////////////////////////////////////
//parameter pINT8_BW = 9;//int8 bitwidth after icvt
//parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4;
////////////////////////////////////////////////////////////////////////////////////////
input nvdla_core_clk;
input nvdla_core_rstn;
input reg2dp_lut_le_function;
input [7:0] reg2dp_lut_le_index_offset;
input [7:0] reg2dp_lut_le_index_select;
input [5:0] reg2dp_lut_le_start_high;
input [31:0] reg2dp_lut_le_start_low;
input [7:0] reg2dp_lut_lo_index_select;
input [5:0] reg2dp_lut_lo_start_high;
input [31:0] reg2dp_lut_lo_start_low;
input reg2dp_sqsum_bypass;
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $sqsumo = $icvto *2 -1+4; ##(${tp}*2) -1 is for x^2, +4 is after 9 lrn
//: print "input [${tp}*${sqsumo}-1:0] sum2itp_pd; \n";
//: print "output [${tp}*${sqsumo}-1:0] sum2sync_pd; \n";
//| eperl: generated_beg (DO NOT EDIT BELOW)
input [8*21-1:0] sum2itp_pd;
output [8*21-1:0] sum2sync_pd;
//| eperl: generated_end (DO NOT EDIT ABOVE)
input sum2itp_pvld;
output sum2itp_prdy;
//: my $k = 8;
//: foreach my $m (0..$k-1) {
//: print qq(
//: output [9:0] dp2lut_X_entry_${m};
//: output [17:0] dp2lut_Xinfo_${m};
//: output [9:0] dp2lut_Y_entry_${m};
//: output [17:0] dp2lut_Yinfo_${m};
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
output [9:0] dp2lut_X_entry_0;
output [17:0] dp2lut_Xinfo_0;
output [9:0] dp2lut_Y_entry_0;
output [17:0] dp2lut_Yinfo_0;
output [9:0] dp2lut_X_entry_1;
output [17:0] dp2lut_Xinfo_1;
output [9:0] dp2lut_Y_entry_1;
output [17:0] dp2lut_Yinfo_1;
output [9:0] dp2lut_X_entry_2;
output [17:0] dp2lut_Xinfo_2;
output [9:0] dp2lut_Y_entry_2;
output [17:0] dp2lut_Yinfo_2;
output [9:0] dp2lut_X_entry_3;
output [17:0] dp2lut_Xinfo_3;
output [9:0] dp2lut_Y_entry_3;
output [17:0] dp2lut_Yinfo_3;
output [9:0] dp2lut_X_entry_4;
output [17:0] dp2lut_Xinfo_4;
output [9:0] dp2lut_Y_entry_4;
output [17:0] dp2lut_Yinfo_4;
output [9:0] dp2lut_X_entry_5;
output [17:0] dp2lut_Xinfo_5;
output [9:0] dp2lut_Y_entry_5;
output [17:0] dp2lut_Yinfo_5;
output [9:0] dp2lut_X_entry_6;
output [17:0] dp2lut_Xinfo_6;
output [9:0] dp2lut_Y_entry_6;
output [17:0] dp2lut_Yinfo_6;
output [9:0] dp2lut_X_entry_7;
output [17:0] dp2lut_Xinfo_7;
output [9:0] dp2lut_Y_entry_7;
output [17:0] dp2lut_Yinfo_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
output dp2lut_pvld;
input dp2lut_prdy;
output sum2sync_pvld;
input sum2sync_prdy;
////////////////////////////////////////////////////////////////////////////////////////
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $sqsumo = $icvto *2 -1+4;
//: foreach my $m (0..${tp}-1) {
//: print qq(
//: wire [17:0] dp2lut_X_info_$m;
//: wire [9:0] dp2lut_X_pd_$m;
//: wire [17:0] dp2lut_Y_info_$m;
//: wire [9:0] dp2lut_Y_pd_$m;
//: wire [${sqsumo}-1:0] sum2itp_pd_$m;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
wire [17:0] dp2lut_X_info_0;
wire [9:0] dp2lut_X_pd_0;
wire [17:0] dp2lut_Y_info_0;
wire [9:0] dp2lut_Y_pd_0;
wire [21-1:0] sum2itp_pd_0;
wire [17:0] dp2lut_X_info_1;
wire [9:0] dp2lut_X_pd_1;
wire [17:0] dp2lut_Y_info_1;
wire [9:0] dp2lut_Y_pd_1;
wire [21-1:0] sum2itp_pd_1;
wire [17:0] dp2lut_X_info_2;
wire [9:0] dp2lut_X_pd_2;
wire [17:0] dp2lut_Y_info_2;
wire [9:0] dp2lut_Y_pd_2;
wire [21-1:0] sum2itp_pd_2;
wire [17:0] dp2lut_X_info_3;
wire [9:0] dp2lut_X_pd_3;
wire [17:0] dp2lut_Y_info_3;
wire [9:0] dp2lut_Y_pd_3;
wire [21-1:0] sum2itp_pd_3;
wire [17:0] dp2lut_X_info_4;
wire [9:0] dp2lut_X_pd_4;
wire [17:0] dp2lut_Y_info_4;
wire [9:0] dp2lut_Y_pd_4;
wire [21-1:0] sum2itp_pd_4;
wire [17:0] dp2lut_X_info_5;
wire [9:0] dp2lut_X_pd_5;
wire [17:0] dp2lut_Y_info_5;
wire [9:0] dp2lut_Y_pd_5;
wire [21-1:0] sum2itp_pd_5;
wire [17:0] dp2lut_X_info_6;
wire [9:0] dp2lut_X_pd_6;
wire [17:0] dp2lut_Y_info_6;
wire [9:0] dp2lut_Y_pd_6;
wire [21-1:0] sum2itp_pd_6;
wire [17:0] dp2lut_X_info_7;
wire [9:0] dp2lut_X_pd_7;
wire [17:0] dp2lut_Y_info_7;
wire [9:0] dp2lut_Y_pd_7;
wire [21-1:0] sum2itp_pd_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
wire [8 -1:0] dp2lut_rdy;
wire [8 -1:0] dp2lut_vld;
wire [8 -1:0] sum2itp_rdy;
wire [8 -1:0] sum2itp_vld;
////////////////////////////////////////////////////////////////////////////////////////
assign sum2itp_prdy = (&sum2itp_rdy) & sum2sync_prdy;
//////////////////////////////////////////////////////////////////////
//from intp_ctrl input port to sync fifo for interpolation
assign sum2sync_pvld = sum2itp_pvld & (&sum2itp_rdy);
assign sum2sync_pd = sum2itp_pd;
///////////////////////////////////////////
//: my $tp=8;
//: my $icvto=(8 +1);
//: my $sqsumo = $icvto *2 -1+4;
//: foreach my $m (0..${tp} -1) {
//: print qq(
//: assign sum2itp_vld[$m] = sum2itp_pvld & sum2sync_prdy
//: );
//: foreach my $j (0..${tp} -1) {
//: if(${j} != ${m}) {
//: print qq(
//: & sum2itp_rdy[$j]
//: );
//: }
//: }
//: print qq(
//: ;
//: );
//: print qq(
//: assign sum2itp_pd_${m} = sum2itp_pd[${sqsumo}*${m}+${sqsumo}-1:${sqsumo}*${m}];
//: NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit$m (
//: .nvdla_core_clk (nvdla_core_clk)
//: ,.nvdla_core_rstn (nvdla_core_rstn)
//: ,.sum2itp_pd (sum2itp_pd_${m})
//: ,.sum2itp_pvld (sum2itp_vld[${m}])
//: ,.sum2itp_prdy (sum2itp_rdy[${m}])
//: ,.reg2dp_lut_le_function (reg2dp_lut_le_function)
//: ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
//: ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
//: ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
//: ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
//: ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
//: ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
//: ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
//: ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
//: ,.dp2lut_X_info (dp2lut_X_info_${m})
//: ,.dp2lut_X_pd (dp2lut_X_pd_${m})
//: ,.dp2lut_Y_info (dp2lut_Y_info_${m})
//: ,.dp2lut_Y_pd (dp2lut_Y_pd_${m})
//: ,.dp2lut_pvld (dp2lut_vld[${m}])
//: ,.dp2lut_prdy (dp2lut_rdy[${m}])
//: );
//: );
//: }
//: my $k = 8;
//: foreach my $m (0..$k -1) {
//: print qq(
//: assign dp2lut_X_entry_$m = dp2lut_X_pd_$m;
//: assign dp2lut_Y_entry_$m = dp2lut_Y_pd_$m;
//: assign dp2lut_Xinfo_$m = dp2lut_X_info_$m;
//: assign dp2lut_Yinfo_$m = dp2lut_Y_info_$m;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign sum2itp_vld[0] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_0 = sum2itp_pd[21*0+21-1:21*0];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit0 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_0)
,.sum2itp_pvld (sum2itp_vld[0])
,.sum2itp_prdy (sum2itp_rdy[0])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_0)
,.dp2lut_X_pd (dp2lut_X_pd_0)
,.dp2lut_Y_info (dp2lut_Y_info_0)
,.dp2lut_Y_pd (dp2lut_Y_pd_0)
,.dp2lut_pvld (dp2lut_vld[0])
,.dp2lut_prdy (dp2lut_rdy[0])
);
assign sum2itp_vld[1] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_1 = sum2itp_pd[21*1+21-1:21*1];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit1 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_1)
,.sum2itp_pvld (sum2itp_vld[1])
,.sum2itp_prdy (sum2itp_rdy[1])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_1)
,.dp2lut_X_pd (dp2lut_X_pd_1)
,.dp2lut_Y_info (dp2lut_Y_info_1)
,.dp2lut_Y_pd (dp2lut_Y_pd_1)
,.dp2lut_pvld (dp2lut_vld[1])
,.dp2lut_prdy (dp2lut_rdy[1])
);
assign sum2itp_vld[2] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_2 = sum2itp_pd[21*2+21-1:21*2];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit2 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_2)
,.sum2itp_pvld (sum2itp_vld[2])
,.sum2itp_prdy (sum2itp_rdy[2])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_2)
,.dp2lut_X_pd (dp2lut_X_pd_2)
,.dp2lut_Y_info (dp2lut_Y_info_2)
,.dp2lut_Y_pd (dp2lut_Y_pd_2)
,.dp2lut_pvld (dp2lut_vld[2])
,.dp2lut_prdy (dp2lut_rdy[2])
);
assign sum2itp_vld[3] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_3 = sum2itp_pd[21*3+21-1:21*3];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit3 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_3)
,.sum2itp_pvld (sum2itp_vld[3])
,.sum2itp_prdy (sum2itp_rdy[3])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_3)
,.dp2lut_X_pd (dp2lut_X_pd_3)
,.dp2lut_Y_info (dp2lut_Y_info_3)
,.dp2lut_Y_pd (dp2lut_Y_pd_3)
,.dp2lut_pvld (dp2lut_vld[3])
,.dp2lut_prdy (dp2lut_rdy[3])
);
assign sum2itp_vld[4] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_4 = sum2itp_pd[21*4+21-1:21*4];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit4 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_4)
,.sum2itp_pvld (sum2itp_vld[4])
,.sum2itp_prdy (sum2itp_rdy[4])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_4)
,.dp2lut_X_pd (dp2lut_X_pd_4)
,.dp2lut_Y_info (dp2lut_Y_info_4)
,.dp2lut_Y_pd (dp2lut_Y_pd_4)
,.dp2lut_pvld (dp2lut_vld[4])
,.dp2lut_prdy (dp2lut_rdy[4])
);
assign sum2itp_vld[5] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[6]
& sum2itp_rdy[7]
;
assign sum2itp_pd_5 = sum2itp_pd[21*5+21-1:21*5];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit5 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_5)
,.sum2itp_pvld (sum2itp_vld[5])
,.sum2itp_prdy (sum2itp_rdy[5])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_5)
,.dp2lut_X_pd (dp2lut_X_pd_5)
,.dp2lut_Y_info (dp2lut_Y_info_5)
,.dp2lut_Y_pd (dp2lut_Y_pd_5)
,.dp2lut_pvld (dp2lut_vld[5])
,.dp2lut_prdy (dp2lut_rdy[5])
);
assign sum2itp_vld[6] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[7]
;
assign sum2itp_pd_6 = sum2itp_pd[21*6+21-1:21*6];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit6 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_6)
,.sum2itp_pvld (sum2itp_vld[6])
,.sum2itp_prdy (sum2itp_rdy[6])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_6)
,.dp2lut_X_pd (dp2lut_X_pd_6)
,.dp2lut_Y_info (dp2lut_Y_info_6)
,.dp2lut_Y_pd (dp2lut_Y_pd_6)
,.dp2lut_pvld (dp2lut_vld[6])
,.dp2lut_prdy (dp2lut_rdy[6])
);
assign sum2itp_vld[7] = sum2itp_pvld & sum2sync_prdy
& sum2itp_rdy[0]
& sum2itp_rdy[1]
& sum2itp_rdy[2]
& sum2itp_rdy[3]
& sum2itp_rdy[4]
& sum2itp_rdy[5]
& sum2itp_rdy[6]
;
assign sum2itp_pd_7 = sum2itp_pd[21*7+21-1:21*7];
NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit7 (
.nvdla_core_clk (nvdla_core_clk)
,.nvdla_core_rstn (nvdla_core_rstn)
,.sum2itp_pd (sum2itp_pd_7)
,.sum2itp_pvld (sum2itp_vld[7])
,.sum2itp_prdy (sum2itp_rdy[7])
,.reg2dp_lut_le_function (reg2dp_lut_le_function)
,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0])
,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0])
,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0])
,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0])
,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0])
,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0])
,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0])
,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass)
,.dp2lut_X_info (dp2lut_X_info_7)
,.dp2lut_X_pd (dp2lut_X_pd_7)
,.dp2lut_Y_info (dp2lut_Y_info_7)
,.dp2lut_Y_pd (dp2lut_Y_pd_7)
,.dp2lut_pvld (dp2lut_vld[7])
,.dp2lut_prdy (dp2lut_rdy[7])
);
assign dp2lut_X_entry_0 = dp2lut_X_pd_0;
assign dp2lut_Y_entry_0 = dp2lut_Y_pd_0;
assign dp2lut_Xinfo_0 = dp2lut_X_info_0;
assign dp2lut_Yinfo_0 = dp2lut_Y_info_0;
assign dp2lut_X_entry_1 = dp2lut_X_pd_1;
assign dp2lut_Y_entry_1 = dp2lut_Y_pd_1;
assign dp2lut_Xinfo_1 = dp2lut_X_info_1;
assign dp2lut_Yinfo_1 = dp2lut_Y_info_1;
assign dp2lut_X_entry_2 = dp2lut_X_pd_2;
assign dp2lut_Y_entry_2 = dp2lut_Y_pd_2;
assign dp2lut_Xinfo_2 = dp2lut_X_info_2;
assign dp2lut_Yinfo_2 = dp2lut_Y_info_2;
assign dp2lut_X_entry_3 = dp2lut_X_pd_3;
assign dp2lut_Y_entry_3 = dp2lut_Y_pd_3;
assign dp2lut_Xinfo_3 = dp2lut_X_info_3;
assign dp2lut_Yinfo_3 = dp2lut_Y_info_3;
assign dp2lut_X_entry_4 = dp2lut_X_pd_4;
assign dp2lut_Y_entry_4 = dp2lut_Y_pd_4;
assign dp2lut_Xinfo_4 = dp2lut_X_info_4;
assign dp2lut_Yinfo_4 = dp2lut_Y_info_4;
assign dp2lut_X_entry_5 = dp2lut_X_pd_5;
assign dp2lut_Y_entry_5 = dp2lut_Y_pd_5;
assign dp2lut_Xinfo_5 = dp2lut_X_info_5;
assign dp2lut_Yinfo_5 = dp2lut_Y_info_5;
assign dp2lut_X_entry_6 = dp2lut_X_pd_6;
assign dp2lut_Y_entry_6 = dp2lut_Y_pd_6;
assign dp2lut_Xinfo_6 = dp2lut_X_info_6;
assign dp2lut_Yinfo_6 = dp2lut_Y_info_6;
assign dp2lut_X_entry_7 = dp2lut_X_pd_7;
assign dp2lut_Y_entry_7 = dp2lut_Y_pd_7;
assign dp2lut_Xinfo_7 = dp2lut_X_info_7;
assign dp2lut_Yinfo_7 = dp2lut_Y_info_7;
//| eperl: generated_end (DO NOT EDIT ABOVE)
assign dp2lut_pvld = &dp2lut_vld;
//: my $k = 8;
//: foreach my $m (0..$k -1) {
//: print qq(
//: assign dp2lut_rdy[${m}] = dp2lut_prdy
//: );
//: foreach my $j (0..$k -1) {
//: if(${j} != ${m}) {
//: print qq(
//: & dp2lut_vld[$j]
//: );
//: }
//: }
//: print qq(
//: ;
//: );
//: }
//| eperl: generated_beg (DO NOT EDIT BELOW)
assign dp2lut_rdy[0] = dp2lut_prdy
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[1] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[2] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[3] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[4] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[5]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[5] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[6]
& dp2lut_vld[7]
;
assign dp2lut_rdy[6] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[7]
;
assign dp2lut_rdy[7] = dp2lut_prdy
& dp2lut_vld[0]
& dp2lut_vld[1]
& dp2lut_vld[2]
& dp2lut_vld[3]
& dp2lut_vld[4]
& dp2lut_vld[5]
& dp2lut_vld[6]
;
//| eperl: generated_end (DO NOT EDIT ABOVE)
///////////////////////////////////////////
endmodule // NV_NVDLA_CDP_DP_LUT_ctrl |
Subsets and Splits