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module MUX(in_0,in_1,in_2,in_3,out,key_0,key_1);
input in_0,in_1,in_2,in_3;
input key_0,key_1;
output out;
wire in_0,in_1,in_2,in_3;
wire key_0,key_1,k_b_0,k_b_1;
wire n_0,n_1,n_2,n_3;
wire s_0,s_1,s_2,s_3;
wire out;
or OR (out, n_0, n_1, n_2, n_3);
and AND0 (n_0, in_0, s_0);
and AND1 (n_1, in_1, s_1);
and AND2 (n_2, in_2, s_2);
and AND3 (n_3, in_3, s_3);
not NOT0 (k_b_0, key_0);
not NOT1 (k_b_1, key_1);
and sAND0 (s_0, k_b_1, k_b_0);
and sAND1 (s_1, k_b_1, key_0);
and sAND2 (s_2, key_1, k_b_0);
and sAND3 (s_3, key_1, key_0);
endmodule |
module test_blackbox_io(clk, i0, o0);
input clk, i0;
output o0;
ff ff0(.D(i0), .CK(clk), .Q(o0));
endmodule |
module test_blackbox_io(clk, i0, i1, o0);
input clk, i0, i1;
output o0;
wire w0, w1;
xor xor0(w0, i0, i1);
ff ff0(.D(w0), .CK(clk), .Q(w1));
not not0(o0, w1);
endmodule |
module do_not_parse_0(G2, G3);
input G2;
output G3;
assign G2 = ~G3;
endmodule |
module test_correct_io(G1,G2,G3,G4,G5_0,G5_1,G17,G18,G19,G20,G21,G22_0,G22_1);
// Comments Inside Module
input G1,G2,G3,G4;
/* Comments Inside Module */
input G5_0,G5_1;
output G17, G18,G19,G20,G21;
output G22_0,
G22_1;
wire G8_0,G8_1;
nand NAND2_0 (G8_0,G1,G3);
nor NOR2_0( G17,G8_1,1'b1);
and AND2_0(G18, G2,G5_0);
xor XOR2_0(G22_0,G5_1 ,G4);
assign G8_1 = 1'b1;
assign G19 = G1 & G2 & (G3 ^ G4);
assign G20 = G17 ^ (G8_0 & G5_0);
assign G22_1 = G1 & (~G2 | 1'b1);
assign G21 = 1'b0;
endmodule |
module do_not_parse_1(G2, G3);
input G2;
output G3;
assign G2 = ~G3;
endmodule |
module test_module_bb(clk, G0, G1, G2_0, G2_1, G18_0, G18_1);
input clk, G0, G1;
input G2_0,G2_1;
output G18_0,G18_1;
wire G3, G4, G5;
ff DFF_0(.CK (clk), .D (G3), .Q (G4));
and AND2_0(G3, G0, G1);
and AND2_1(G18_1, G5, G2_1);
ff DFF_1(.CK (clk), .D(G2_0), .Q(G5));
ff DFF_2(.CK (clk), .D(G5), .Q(G18_0));
endmodule |
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
parameter W = 2**LEVELS;
// pad input to even power of two
wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
wire [W/2-1:0] stage_valid[LEVELS-1:0];
wire [W/2-1:0] stage_enc[LEVELS-1:0];
generate
genvar l, n;
// process input bits; generate valid bit and encoded bit for each pair
for (n = 0; n < W/2; n = n + 1) begin : loop_in
assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
if (LSB_PRIORITY == "LOW") begin
assign stage_enc[0][n] = input_padded[n*2+1];
end else begin
assign stage_enc[0][n] = !input_padded[n*2+0];
end
end
// compress down to single valid bit and encoded bus
for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
if (LSB_PRIORITY == "LOW") begin
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
end else begin
assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
end
end
end
endgenerate
assign output_valid = stage_valid[LEVELS-1];
assign output_encoded = stage_enc[LEVELS-1];
assign output_unencoded = 1 << output_encoded;
endmodule |
module PSUM_BUFF #(
parameter data_width = 25,
parameter addr_width = 8,
parameter depth = 61
) (
input clk,
input rst_n,
input p_valid_data,
input p_write_zero,
input p_init,
input odd_cnt,
input signed [data_width-1:0] pe0_data,
input signed [data_width-1:0] pe1_data,
input signed [data_width-1:0] pe2_data,
input signed [data_width-1:0] pe3_data,
output [data_width-1:0] fifo_out,
output valid_fifo_out
);
// wire [data_width-1:0] fifo_head;
// reg [data_width-1:0] fifo_head_reg;
reg [data_width-1:0] fifo_in0;
reg [data_width-1:0] fifo_in1;
wire signed [data_width-1:0] adder_out;
wire empty0, full0;
wire empty1, full1;
reg fifo_rd_en0;
reg fifo_wr_en0;
reg fifo_rd_en1;
reg fifo_wr_en1;
/// delayed odd_cnt
reg d_odd_cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
d_odd_cnt <= 0;
else
d_odd_cnt <= odd_cnt;
end
/// Shifter register, there are four pipeline stages
reg [3-1:0] p_valid;
reg [3-1:0] p_write_zero_reg;
reg [data_width-1:0] fifo_out_i;
reg [data_width-1:0] fifo_out_a;
wire [data_width-1:0] fifo_out_i0;
wire [data_width-1:0] fifo_out_i1;
always @(*) begin
if (!rst_n) begin
fifo_out_i = 0;
fifo_out_a = 0;
end else if (~d_odd_cnt) begin
fifo_out_i = fifo_out_i1;
fifo_out_a = fifo_out_i0;
end else begin
fifo_out_i = fifo_out_i0;
fifo_out_a = fifo_out_i1;
end
end
/// Whether the output of current fifo output is valid
assign valid_fifo_out = p_write_zero_reg;
/// Relu Operation
assign fifo_out = fifo_out_i[data_width-1] ? 0 : fifo_out_i;
/// Fifo read and write
/// When to write fifo
/// Data that will be written to fifo
wire write_zero;
assign write_zero = p_write_zero || p_write_zero_reg;
always @(*) begin
if (!rst_n) begin
fifo_rd_en0 = 0;
fifo_wr_en0 = 0;
fifo_rd_en1 = 0;
fifo_wr_en1 = 0;
fifo_in0 = 0;
fifo_in1 = 0;
end else if (p_init) begin
fifo_rd_en0 = 0;
fifo_wr_en0 = 1;
fifo_rd_en1 = 0;
fifo_wr_en1 = 1;
fifo_in0 = 0;
fifo_in1 = 0;
end else if (write_zero & d_odd_cnt) begin
fifo_rd_en0 = p_write_zero;
fifo_wr_en0 = p_write_zero_reg;
fifo_rd_en1 = p_valid[0];
fifo_wr_en1 = p_valid[2];
fifo_in0 = 0;
fifo_in1 = adder_out;
end else if (write_zero & ~d_odd_cnt) begin
fifo_rd_en1 = p_write_zero;
fifo_wr_en1 = p_write_zero_reg;
fifo_rd_en0 = p_valid[0];
fifo_wr_en0 = p_valid[2];
fifo_in1 = 0;
fifo_in0 = adder_out;
end else if (~d_odd_cnt & ~write_zero) begin
fifo_rd_en1 = 0;
fifo_wr_en1 = 0;
fifo_rd_en0 = p_valid[0];
fifo_wr_en0 = p_valid[2];
fifo_in1 = 0;
fifo_in0 = adder_out;
end else if (d_odd_cnt & ~write_zero) begin
fifo_rd_en0 = 0;
fifo_wr_en0 = 0;
fifo_rd_en1 = p_valid[0];
fifo_wr_en1 = p_valid[2];
fifo_in0 = 0;
fifo_in1 = adder_out;
end else begin
fifo_rd_en0 = 0;
fifo_wr_en0 = 0;
fifo_rd_en1 = 0;
fifo_wr_en1 = 0;
fifo_in0 = 0;
fifo_in1 = 0;
end
end
/// Whether the current input is valid data
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_valid <= 3'b0;
else
p_valid <= {p_valid[1:0], p_valid_data};
end
/// Whether the current write zero is valid data
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_write_zero_reg <= 1'b0;
else
p_write_zero_reg <= p_write_zero;
end
/// Adder tree
PSUM_ADD #(.data_width(data_width)) adder_tree (
.clk(clk),
.rst_n(rst_n),
.pe0_data(pe0_data),
.pe1_data(pe1_data),
.pe2_data(pe2_data),
.pe3_data(pe3_data),
.fifo_data(fifo_out_a),
.out(adder_out)
);
/// Synchronous fifo
SYNCH_FIFO #(
.data_width(data_width),
.addr_width(addr_width),
.depth(depth)
) synch_fifo0 (
.clk(clk),
.rd_en(fifo_rd_en0),
.wr_en(fifo_wr_en0),
.rst_n(rst_n),
.empty(empty0),
.full(full0),
.data_out(fifo_out_i0),
.data_in(fifo_in0)
);
/// Synchronous fifo
SYNCH_FIFO #(
.data_width(data_width),
.addr_width(addr_width),
.depth(depth)
) synch_fifo1 (
.clk(clk),
.rd_en(fifo_rd_en1),
.wr_en(fifo_wr_en1),
.rst_n(rst_n),
.empty(empty1),
.full(full1),
.data_out(fifo_out_i1),
.data_in(fifo_in1)
);
endmodule |
module WGT_BUF (clk, rst_n, wgt_input, wgt_read, wgt_buf0, wgt_buf1, wgt_buf2, wgt_buf3);
input clk;
input rst_n;
input signed [7:0] wgt_input;
input wgt_read;
output signed [7:0] wgt_buf0;
output signed [7:0] wgt_buf1;
output signed [7:0] wgt_buf2;
output signed [7:0] wgt_buf3;
reg signed [7:0] wgt_buf [3:0];
integer i;
always @(posedge clk or negedge rst_n)
if (~rst_n)
begin
for(i = 0; i < 4; i = i + 1)
begin
wgt_buf[i] <= 0;
end
end
else
begin
if(wgt_read)
begin
wgt_buf[3] <= wgt_buf[2];
wgt_buf[2] <= wgt_buf[1];
wgt_buf[1] <= wgt_buf[0];
wgt_buf[0] <= wgt_input;
end
else
begin
wgt_buf[3] <= wgt_buf[3];
wgt_buf[2] <= wgt_buf[2];
wgt_buf[1] <= wgt_buf[1];
wgt_buf[0] <= wgt_buf[0];
end
end
assign wgt_buf0 = wgt_buf[0];
assign wgt_buf1 = wgt_buf[1];
assign wgt_buf2 = wgt_buf[2];
assign wgt_buf3 = wgt_buf[3];
endmodule |
module SYNCH_FIFO #(
parameter data_width = 25,
parameter addr_width = 8,
parameter depth = 61
) (
/// Control signal
input clk,
input rd_en,
input wr_en,
input rst_n,
/// status signal
output empty,
output full,
/// data signal
output reg [data_width-1:0] data_out,
input [data_width-1:0] data_in
);
reg [addr_width:0] cnt;
reg [data_width-1:0] fifo_mem [0:depth-1];
reg [addr_width-1:0] rd_ptr;
reg [addr_width-1:0] wr_ptr;
/// Status generation
assign empty = (cnt == 0);
assign full = (cnt == depth);
/// Updata read pointer && Read operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
rd_ptr <= 0;
else if (rd_en && !empty) begin
if (rd_ptr == depth-1)
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end else
rd_ptr <= rd_ptr;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
data_out <= 0;
else if (rd_en && !empty)
data_out <= fifo_mem[rd_ptr];
end
/// Update write pointer && write operation
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
wr_ptr <= 0;
else if (wr_en && !full) begin
if (wr_ptr == depth-1)
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end else
wr_ptr <= wr_ptr;
end
always @(posedge clk) begin
if (wr_en & ~full)
fifo_mem[wr_ptr] = data_in;
end
/// Update the counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else begin
case ({wr_en, rd_en})
2'b00: cnt <= cnt;
2'b01: cnt <= !empty ? cnt-1 : cnt;
2'b10: cnt <= !full ? cnt+1 : cnt;
2'b11: cnt <= cnt;
endcase
end
end
endmodule |
module PE (clk, rst_n, ifm_input0, ifm_input1, ifm_input2, ifm_input3,
wgt_input0, wgt_input1, wgt_input2, wgt_input3, p_sum);
input clk;
input rst_n;
input signed [7:0] ifm_input0;
input signed [7:0] ifm_input1;
input signed [7:0] ifm_input2;
input signed [7:0] ifm_input3;
input signed [7:0] wgt_input0;
input signed [7:0] wgt_input1;
input signed [7:0] wgt_input2;
input signed [7:0] wgt_input3;
output signed [24:0] p_sum;
reg signed [15:0] product [3:0];
reg signed [16:0] pp_sum [1:0];
reg signed [24:0] p_sum;
integer i;
integer j;
always @(posedge clk or negedge rst_n)
if (~rst_n)
begin
for(i = 0; i < 4; i = i + 1)
begin
product[i] <= 0;
end
for(i = 0; i < 2; i = i + 1)
begin
pp_sum[i] <= 0;
end
p_sum <= 0;
end
else
begin
product[0] <= ifm_input0 * wgt_input0;
product[1] <= ifm_input1 * wgt_input1;
product[2] <= ifm_input2 * wgt_input2;
product[3] <= ifm_input3 * wgt_input3;
pp_sum[0] <= product[0] + product[1];
pp_sum[1] <= product[2] + product[3];
p_sum <= pp_sum[0] + pp_sum[1];
end
endmodule //PE |
module WRITE_BACK #(
parameter data_width = 25,
parameter depth = 61
) (
input clk,
input rst_n,
input start_init,
input p_filter_end,
input [data_width-1:0] row0,
input row0_valid,
input [data_width-1:0] row1,
input row1_valid,
input [data_width-1:0] row2,
input row2_valid,
input [data_width-1:0] row3,
input row3_valid,
input [data_width-1:0] row4,
input row4_valid,
output p_write_zero0,
output p_write_zero1,
output p_write_zero2,
output p_write_zero3,
output p_write_zero4,
output p_init,
output [data_width-1:0] out_port0,
output [data_width-1:0] out_port1,
output port0_valid,
output port1_valid,
output start_conv,
output odd_cnt
);
/// machine state encode
localparam IDLE = 4'd0;
localparam INIT_BUFF = 4'd1;
localparam START_CONV = 4'd2;
localparam WAIT_ADD = 4'd3;
localparam WAIT_WRITE0 = 4'd4;
localparam ROW_0_1 = 4'd5;
localparam CLEAR_0_1 = 4'd6;
localparam ROW_2_3 = 4'd7;
localparam CLEAR_2_3 = 4'd8;
localparam ROW_5 = 4'd9;
localparam CLEAR_START_CONV = 4'd10;
localparam CLEAR_CNT = 4'd11;
// localparam DONE = 4'b1001;
/// machine state
reg [3:0] st_next;
reg [3:0] st_cur;
reg [7:0] cnt;
/// State transfer
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
st_cur <= IDLE;
else
st_cur <= st_next;
end
/// Next state logic
always @(*) begin
st_next = st_cur;
case(st_cur)
IDLE:
if (start_init)
st_next = INIT_BUFF;
else
st_next = IDLE;
INIT_BUFF:
if (cnt == depth-1)
st_next = START_CONV;
else
st_next = INIT_BUFF;
START_CONV:
if (cnt >= depth+2)
st_next = CLEAR_START_CONV;
else
st_next = START_CONV;
CLEAR_START_CONV:
if (p_filter_end)
st_next = WAIT_ADD;
else
st_next = CLEAR_START_CONV;
WAIT_ADD:
if (cnt == depth-1)
st_next = WAIT_WRITE0;
else
st_next = WAIT_ADD;
WAIT_WRITE0:
st_next = CLEAR_CNT;
CLEAR_CNT:
st_next = ROW_0_1;
ROW_0_1:
if (cnt == depth-1)
st_next = CLEAR_0_1;
else
st_next = ROW_0_1;
CLEAR_0_1:
st_next = ROW_2_3;
ROW_2_3:
if (cnt == depth-1)
st_next = CLEAR_2_3;
else
st_next = ROW_2_3;
CLEAR_2_3:
st_next = ROW_5;
ROW_5:
if (cnt == depth-1)
st_next = CLEAR_START_CONV;
else
st_next = ROW_5;
// DONE:
// st_next = START_CONV;
default:
st_next = IDLE;
endcase
end
/// Output logic
reg p_write_zero0_r;
reg p_write_zero1_r;
reg p_write_zero2_r;
reg p_write_zero3_r;
reg p_write_zero4_r;
reg p_init_r;
reg [data_width-1:0] out_port0_r;
reg [data_width-1:0] out_port1_r;
reg port0_valid_r;
reg port1_valid_r;
reg start_conv_r;
/// Output start conv signal
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
start_conv_r <= 0;
else if (st_cur == START_CONV || st_cur == CLEAR_CNT)
start_conv_r <= 1;
else
start_conv_r <= 0;
end
assign start_conv = start_conv_r;
/// PingPong buffer controller signal
reg odd_cnt_r;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
odd_cnt_r <= 0;
else if (st_cur == CLEAR_CNT)
odd_cnt_r <= ~odd_cnt;
else
odd_cnt_r <= odd_cnt;
end
assign odd_cnt = odd_cnt_r;
/// Output zero flag signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero0_r <= 0;
p_write_zero1_r <= 0;
end else if (st_cur == ROW_0_1) begin
p_write_zero0_r <= 1;
p_write_zero1_r <= 1;
end else begin
p_write_zero0_r <= 0;
p_write_zero1_r <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero2_r <= 0;
p_write_zero3_r <= 0;
end else if (st_cur == ROW_2_3) begin
p_write_zero2_r <= 1;
p_write_zero3_r <= 1;
end else begin
p_write_zero2_r <= 0;
p_write_zero3_r <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero4_r <= 0;
end else if (st_cur == ROW_5) begin
p_write_zero4_r <= 1;
end else begin
p_write_zero4_r <= 0;
end
end
assign p_write_zero0 = p_write_zero0_r;
assign p_write_zero1 = p_write_zero1_r;
assign p_write_zero2 = p_write_zero2_r;
assign p_write_zero3 = p_write_zero3_r;
assign p_write_zero4 = p_write_zero4_r;
/// Init buffer signal, why this signal? since, at the beginning, the buffer is empty, we only need to
/// push zero to buffer without read from it, this behaviour is difference from p_write_zerox signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_init_r <= 0;
else if (st_cur == INIT_BUFF)
p_init_r <= 1;
else
p_init_r <= 0;
end
assign p_init = p_init_r;
/// Update the cnt
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else if (st_cur == IDLE || st_cur == CLEAR_0_1 || st_cur == CLEAR_START_CONV
|| st_cur == CLEAR_2_3 || st_cur == CLEAR_CNT)
cnt <= 0;
else
cnt <= cnt + 1;
end
/// Final result, a big mux
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_port0_r <= 0;
out_port1_r <= 0;
port0_valid_r <= 0;
port1_valid_r <= 0;
end else begin
case({row0_valid, row1_valid, row2_valid, row3_valid, row4_valid})
5'b11000 : begin
out_port0_r <= row0;
out_port1_r <= row1;
port0_valid_r <= row0_valid;
port1_valid_r <= row1_valid;
end
5'b00110 : begin
out_port0_r <= row2;
out_port1_r <= row3;
port0_valid_r <= row2_valid;
port1_valid_r <= row3_valid;
end
5'b00001 : begin
out_port0_r <= row4;
out_port1_r <= 0;
port0_valid_r <= row4_valid;
port1_valid_r <= 0;
end
default : begin
out_port0_r <= 0;
out_port1_r <= 0;
port0_valid_r <= 0;
port1_valid_r <= 0;
end
endcase
end
end
assign out_port0 = out_port0_r;
assign out_port1 = out_port1_r;
assign port0_valid = port0_valid_r;
assign port1_valid = port1_valid_r;
endmodule |
module CONV_ACC #(
parameter out_data_width = 25,
parameter buf_addr_width = 5,
parameter buf_depth = 16
) (
input clk,
input rst_n,
input start_conv,
input [1:0] cfg_ci,
input [1:0] cfg_co,
input [63:0] ifm,
input [31:0] weight,
output [24:0] ofm_port0,
output [24:0] ofm_port1,
output ofm_port0_v,
output ofm_port1_v,
output ifm_read,
output wgt_read,
output end_conv
);
/// Assign ifm to each pes
reg [7:0] rows [0:7];
always @(*) begin
rows[0] = ifm[7:0];
rows[1] = ifm[15:8];
rows[2] = ifm[23:16];
rows[3] = ifm[31:24];
rows[4] = ifm[39:32];
rows[5] = ifm[47:40];
rows[6] = ifm[55:48];
rows[7] = ifm[63:56];
// {rows[0], rows[1], rows[2], rows[3], rows[4], rows[5], rows[6], rows[7]} =
// {ifm[7:0], ifm[15:8], ifm[23:16], ifm[31:24], ifm[39:32], ifm[47:40], ifm[55:48], ifm[63:56]};
end
/// Assign weight to each pes
reg [7:0] wgts [0:3];
always @(*) begin
wgts[0] = weight[7:0];
wgts[1] = weight[15:8];
wgts[2] = weight[23:16];
wgts[3] = weight[31:24];
// {wgts[0], wgts[1], wgts[2], wgts[3]} = {weight[7:0], weight[15:8], weight[23:16], weight[31:24]};
end
///==-------------------------------------------------------------------------------------==
/// Connect between PE and PE_FSM
wire ifm_read_en;
wire wgt_read_en;
assign ifm_read = ifm_read_en;
assign wgt_read = wgt_read_en;
/// Connection between PEs+PE_FSM and WRITEBACK+BUFF
wire [out_data_width-1:0] pe00_data, pe10_data, pe20_data, pe30_data;
wire [out_data_width-1:0] pe01_data, pe11_data, pe21_data, pe31_data;
wire [out_data_width-1:0] pe02_data, pe12_data, pe22_data, pe32_data;
wire [out_data_width-1:0] pe03_data, pe13_data, pe23_data, pe33_data;
wire [out_data_width-1:0] pe04_data, pe14_data, pe24_data, pe34_data;
wire p_filter_end, p_valid_data, start_again;
/// PE FSM
PE_FSM pe_fsm ( .clk(clk), .rst_n(rst_n), .start_conv(start_conv), .start_again(start_again), .cfg_ci(cfg_ci), .cfg_co(cfg_co),
.ifm_read(ifm_read_en), .wgt_read(wgt_read_en), .p_valid_output(p_valid_data),
.last_chanel_output(p_filter_end), .end_conv(end_conv) );
/// PE Array
/// wgt0 row0 pe00 pe01 pe02 pe03 pe04
/// wgt1 row1 pe10 pe11 pe12 pe13 pe14
/// wgt2 row2 pe20 pe21 pe22 pe23 pe24
/// wgt3 pe30 pe31 pe32 pe33 pe34
/// row3 row4 row5 row6 row7
/// First row
wire [7:0] ifm_buf00, ifm_buf01, ifm_buf02, ifm_buf03;
wire [7:0] ifm_buf10, ifm_buf11, ifm_buf12, ifm_buf13;
wire [7:0] ifm_buf20, ifm_buf21, ifm_buf22, ifm_buf23;
wire [7:0] ifm_buf30, ifm_buf31, ifm_buf32, ifm_buf33;
wire [7:0] ifm_buf40, ifm_buf41, ifm_buf42, ifm_buf43;
wire [7:0] ifm_buf50, ifm_buf51, ifm_buf52, ifm_buf53;
wire [7:0] ifm_buf60, ifm_buf61, ifm_buf62, ifm_buf63;
wire [7:0] ifm_buf70, ifm_buf71, ifm_buf72, ifm_buf73;
wire [7:0] wgt_buf00, wgt_buf01, wgt_buf02, wgt_buf03;
wire [7:0] wgt_buf10, wgt_buf11, wgt_buf12, wgt_buf13;
wire [7:0] wgt_buf20, wgt_buf21, wgt_buf22, wgt_buf23;
wire [7:0] wgt_buf30, wgt_buf31, wgt_buf32, wgt_buf33;
IFM_BUF ifm_buf0( .clk(clk), .rst_n(rst_n), .ifm_input(rows[0]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf00), .ifm_buf1(ifm_buf01), .ifm_buf2(ifm_buf02), .ifm_buf3(ifm_buf03));
IFM_BUF ifm_buf1( .clk(clk), .rst_n(rst_n), .ifm_input(rows[1]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf10), .ifm_buf1(ifm_buf11), .ifm_buf2(ifm_buf12), .ifm_buf3(ifm_buf13));
IFM_BUF ifm_buf2( .clk(clk), .rst_n(rst_n), .ifm_input(rows[2]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf20), .ifm_buf1(ifm_buf21), .ifm_buf2(ifm_buf22), .ifm_buf3(ifm_buf23));
IFM_BUF ifm_buf3( .clk(clk), .rst_n(rst_n), .ifm_input(rows[3]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf30), .ifm_buf1(ifm_buf31), .ifm_buf2(ifm_buf32), .ifm_buf3(ifm_buf33));
IFM_BUF ifm_buf4( .clk(clk), .rst_n(rst_n), .ifm_input(rows[4]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf40), .ifm_buf1(ifm_buf41), .ifm_buf2(ifm_buf42), .ifm_buf3(ifm_buf43));
IFM_BUF ifm_buf5( .clk(clk), .rst_n(rst_n), .ifm_input(rows[5]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf50), .ifm_buf1(ifm_buf51), .ifm_buf2(ifm_buf52), .ifm_buf3(ifm_buf53));
IFM_BUF ifm_buf6( .clk(clk), .rst_n(rst_n), .ifm_input(rows[6]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf60), .ifm_buf1(ifm_buf61), .ifm_buf2(ifm_buf62), .ifm_buf3(ifm_buf63));
IFM_BUF ifm_buf7( .clk(clk), .rst_n(rst_n), .ifm_input(rows[7]), .ifm_read(ifm_read_en),
.ifm_buf0(ifm_buf70), .ifm_buf1(ifm_buf71), .ifm_buf2(ifm_buf72), .ifm_buf3(ifm_buf73));
WGT_BUF wgt_buf0( .clk(clk), .rst_n(rst_n), .wgt_input(wgts[0]), .wgt_read(wgt_read_en),
.wgt_buf0(wgt_buf00), .wgt_buf1(wgt_buf01), .wgt_buf2(wgt_buf02), .wgt_buf3(wgt_buf03));
WGT_BUF wgt_buf1( .clk(clk), .rst_n(rst_n), .wgt_input(wgts[1]), .wgt_read(wgt_read_en),
.wgt_buf0(wgt_buf10), .wgt_buf1(wgt_buf11), .wgt_buf2(wgt_buf12), .wgt_buf3(wgt_buf13));
WGT_BUF wgt_buf2( .clk(clk), .rst_n(rst_n), .wgt_input(wgts[2]), .wgt_read(wgt_read_en),
.wgt_buf0(wgt_buf20), .wgt_buf1(wgt_buf21), .wgt_buf2(wgt_buf22), .wgt_buf3(wgt_buf23));
WGT_BUF wgt_buf3( .clk(clk), .rst_n(rst_n), .wgt_input(wgts[3]), .wgt_read(wgt_read_en),
.wgt_buf0(wgt_buf30), .wgt_buf1(wgt_buf31), .wgt_buf2(wgt_buf32), .wgt_buf3(wgt_buf33));
PE pe00( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf00), .ifm_input1(ifm_buf01), .ifm_input2(ifm_buf02), .ifm_input3(ifm_buf03),
.wgt_input0(wgt_buf00), .wgt_input1(wgt_buf01), .wgt_input2(wgt_buf02), .wgt_input3(wgt_buf03), .p_sum(pe00_data) );
PE pe01( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf10), .ifm_input1(ifm_buf11), .ifm_input2(ifm_buf12), .ifm_input3(ifm_buf13),
.wgt_input0(wgt_buf00), .wgt_input1(wgt_buf01), .wgt_input2(wgt_buf02), .wgt_input3(wgt_buf03), .p_sum(pe01_data) );
PE pe02( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf20), .ifm_input1(ifm_buf21), .ifm_input2(ifm_buf22), .ifm_input3(ifm_buf23),
.wgt_input0(wgt_buf00), .wgt_input1(wgt_buf01), .wgt_input2(wgt_buf02), .wgt_input3(wgt_buf03), .p_sum(pe02_data) );
PE pe03( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf30), .ifm_input1(ifm_buf31), .ifm_input2(ifm_buf32), .ifm_input3(ifm_buf33),
.wgt_input0(wgt_buf00), .wgt_input1(wgt_buf01), .wgt_input2(wgt_buf02), .wgt_input3(wgt_buf03), .p_sum(pe03_data) );
PE pe04( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf40), .ifm_input1(ifm_buf41), .ifm_input2(ifm_buf42), .ifm_input3(ifm_buf43),
.wgt_input0(wgt_buf00), .wgt_input1(wgt_buf01), .wgt_input2(wgt_buf02), .wgt_input3(wgt_buf03), .p_sum(pe04_data) );
PE pe10( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf10), .ifm_input1(ifm_buf11), .ifm_input2(ifm_buf12), .ifm_input3(ifm_buf13),
.wgt_input0(wgt_buf10), .wgt_input1(wgt_buf11), .wgt_input2(wgt_buf12), .wgt_input3(wgt_buf13), .p_sum(pe10_data) );
PE pe11( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf20), .ifm_input1(ifm_buf21), .ifm_input2(ifm_buf22), .ifm_input3(ifm_buf23),
.wgt_input0(wgt_buf10), .wgt_input1(wgt_buf11), .wgt_input2(wgt_buf12), .wgt_input3(wgt_buf13), .p_sum(pe11_data) );
PE pe12( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf30), .ifm_input1(ifm_buf31), .ifm_input2(ifm_buf32), .ifm_input3(ifm_buf33),
.wgt_input0(wgt_buf10), .wgt_input1(wgt_buf11), .wgt_input2(wgt_buf12), .wgt_input3(wgt_buf13), .p_sum(pe12_data) );
PE pe13( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf40), .ifm_input1(ifm_buf41), .ifm_input2(ifm_buf42), .ifm_input3(ifm_buf43),
.wgt_input0(wgt_buf10), .wgt_input1(wgt_buf11), .wgt_input2(wgt_buf12), .wgt_input3(wgt_buf13), .p_sum(pe13_data) );
PE pe14( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf50), .ifm_input1(ifm_buf51), .ifm_input2(ifm_buf52), .ifm_input3(ifm_buf53),
.wgt_input0(wgt_buf10), .wgt_input1(wgt_buf11), .wgt_input2(wgt_buf12), .wgt_input3(wgt_buf13), .p_sum(pe14_data) );
PE pe20( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf20), .ifm_input1(ifm_buf21), .ifm_input2(ifm_buf22), .ifm_input3(ifm_buf23),
.wgt_input0(wgt_buf20), .wgt_input1(wgt_buf21), .wgt_input2(wgt_buf22), .wgt_input3(wgt_buf23), .p_sum(pe20_data) );
PE pe21( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf30), .ifm_input1(ifm_buf31), .ifm_input2(ifm_buf32), .ifm_input3(ifm_buf33),
.wgt_input0(wgt_buf20), .wgt_input1(wgt_buf21), .wgt_input2(wgt_buf22), .wgt_input3(wgt_buf23), .p_sum(pe21_data) );
PE pe22( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf40), .ifm_input1(ifm_buf41), .ifm_input2(ifm_buf42), .ifm_input3(ifm_buf43),
.wgt_input0(wgt_buf20), .wgt_input1(wgt_buf21), .wgt_input2(wgt_buf22), .wgt_input3(wgt_buf23), .p_sum(pe22_data) );
PE pe23( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf50), .ifm_input1(ifm_buf51), .ifm_input2(ifm_buf52), .ifm_input3(ifm_buf53),
.wgt_input0(wgt_buf20), .wgt_input1(wgt_buf21), .wgt_input2(wgt_buf22), .wgt_input3(wgt_buf23), .p_sum(pe23_data) );
PE pe24( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf60), .ifm_input1(ifm_buf61), .ifm_input2(ifm_buf62), .ifm_input3(ifm_buf63),
.wgt_input0(wgt_buf20), .wgt_input1(wgt_buf21), .wgt_input2(wgt_buf22), .wgt_input3(wgt_buf23), .p_sum(pe24_data) );
PE pe30( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf30), .ifm_input1(ifm_buf31), .ifm_input2(ifm_buf32), .ifm_input3(ifm_buf33),
.wgt_input0(wgt_buf30), .wgt_input1(wgt_buf31), .wgt_input2(wgt_buf32), .wgt_input3(wgt_buf33), .p_sum(pe30_data) );
PE pe31( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf40), .ifm_input1(ifm_buf41), .ifm_input2(ifm_buf42), .ifm_input3(ifm_buf43),
.wgt_input0(wgt_buf30), .wgt_input1(wgt_buf31), .wgt_input2(wgt_buf32), .wgt_input3(wgt_buf33), .p_sum(pe31_data) );
PE pe32( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf50), .ifm_input1(ifm_buf51), .ifm_input2(ifm_buf52), .ifm_input3(ifm_buf53),
.wgt_input0(wgt_buf30), .wgt_input1(wgt_buf31), .wgt_input2(wgt_buf32), .wgt_input3(wgt_buf33), .p_sum(pe32_data) );
PE pe33( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf60), .ifm_input1(ifm_buf61), .ifm_input2(ifm_buf62), .ifm_input3(ifm_buf63),
.wgt_input0(wgt_buf30), .wgt_input1(wgt_buf31), .wgt_input2(wgt_buf32), .wgt_input3(wgt_buf33), .p_sum(pe33_data) );
PE pe34( .clk(clk), .rst_n(rst_n), .ifm_input0(ifm_buf70), .ifm_input1(ifm_buf71), .ifm_input2(ifm_buf72), .ifm_input3(ifm_buf73),
.wgt_input0(wgt_buf30), .wgt_input1(wgt_buf31), .wgt_input2(wgt_buf32), .wgt_input3(wgt_buf33), .p_sum(pe34_data) );
///==-------------------------------------------------------------------------------------==
/// Connection between the buffer and write back controllers
wire [out_data_width-1:0] fifo_out[0:4];
wire valid_fifo_out[0:4];
wire p_write_zero[0:4];
wire p_init;
wire odd_cnt;
/// Write back controller
WRITE_BACK #(
.data_width(out_data_width),
.depth(buf_depth)
) writeback_control (
.clk(clk),
.rst_n(rst_n),
.start_init(start_conv),
.p_filter_end(p_filter_end),
.row0(fifo_out[0]),
.row0_valid(valid_fifo_out[0]),
.row1(fifo_out[1]),
.row1_valid(valid_fifo_out[1]),
.row2(fifo_out[2]),
.row2_valid(valid_fifo_out[2]),
.row3(fifo_out[3]),
.row3_valid(valid_fifo_out[3]),
.row4(fifo_out[4]),
.row4_valid(valid_fifo_out[4]),
.p_write_zero0(p_write_zero[0]),
.p_write_zero1(p_write_zero[1]),
.p_write_zero2(p_write_zero[2]),
.p_write_zero3(p_write_zero[3]),
.p_write_zero4(p_write_zero[4]),
.p_init(p_init),
.out_port0(ofm_port0),
.out_port1(ofm_port1),
.port0_valid(ofm_port0_v),
.port1_valid(ofm_port1_v),
.start_conv(start_again),
.odd_cnt(odd_cnt)
);
/// Buffer
PSUM_BUFF #(
.data_width(out_data_width),
.addr_width(buf_addr_width),
.depth(buf_depth)
) psum_buff0 (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero[0]),
.p_init(p_init),
.odd_cnt(odd_cnt),
.pe0_data(pe00_data),
.pe1_data(pe10_data),
.pe2_data(pe20_data),
.pe3_data(pe30_data),
.fifo_out(fifo_out[0]),
.valid_fifo_out(valid_fifo_out[0])
);
PSUM_BUFF #(
.data_width(out_data_width),
.addr_width(buf_addr_width),
.depth(buf_depth)
) psum_buff1 (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero[1]),
.p_init(p_init),
.odd_cnt(odd_cnt),
.pe0_data(pe01_data),
.pe1_data(pe11_data),
.pe2_data(pe21_data),
.pe3_data(pe31_data),
.fifo_out(fifo_out[1]),
.valid_fifo_out(valid_fifo_out[1])
);
PSUM_BUFF #(
.data_width(out_data_width),
.addr_width(buf_addr_width),
.depth(buf_depth)
) psum_buff2 (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero[2]),
.p_init(p_init),
.odd_cnt(odd_cnt),
.pe0_data(pe02_data),
.pe1_data(pe12_data),
.pe2_data(pe22_data),
.pe3_data(pe32_data),
.fifo_out(fifo_out[2]),
.valid_fifo_out(valid_fifo_out[2])
);
PSUM_BUFF #(
.data_width(out_data_width),
.addr_width(buf_addr_width),
.depth(buf_depth)
) psum_buff3 (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero[3]),
.p_init(p_init),
.odd_cnt(odd_cnt),
.pe0_data(pe03_data),
.pe1_data(pe13_data),
.pe2_data(pe23_data),
.pe3_data(pe33_data),
.fifo_out(fifo_out[3]),
.valid_fifo_out(valid_fifo_out[3])
);
PSUM_BUFF #(
.data_width(out_data_width),
.addr_width(buf_addr_width),
.depth(buf_depth)
) psum_buff4 (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero[4]),
.p_init(p_init),
.odd_cnt(odd_cnt),
.pe0_data(pe04_data),
.pe1_data(pe14_data),
.pe2_data(pe24_data),
.pe3_data(pe34_data),
.fifo_out(fifo_out[4]),
.valid_fifo_out(valid_fifo_out[4])
);
endmodule //CONV_ACC |
module IFM_BUF (clk, rst_n, ifm_input, ifm_read, ifm_buf0, ifm_buf1, ifm_buf2, ifm_buf3);
input clk;
input rst_n;
input signed [7:0] ifm_input;
input ifm_read;
output signed [7:0] ifm_buf0;
output signed [7:0] ifm_buf1;
output signed [7:0] ifm_buf2;
output signed [7:0] ifm_buf3;
reg signed [7:0] ifm_buf [3:0];
integer i;
always @(posedge clk or negedge rst_n)
if (~rst_n)
begin
for(i = 0; i < 4; i = i + 1)
begin
ifm_buf[i] <= 0;
end
end
else
begin
if(ifm_read)
begin
ifm_buf[3] <= ifm_buf[2];
ifm_buf[2] <= ifm_buf[1];
ifm_buf[1] <= ifm_buf[0];
ifm_buf[0] <= ifm_input;
end
else
begin
ifm_buf[3] <= ifm_buf[3];
ifm_buf[2] <= ifm_buf[2];
ifm_buf[1] <= ifm_buf[1];
ifm_buf[0] <= ifm_buf[0];
end
end
assign ifm_buf0 = ifm_buf[0];
assign ifm_buf1 = ifm_buf[1];
assign ifm_buf2 = ifm_buf[2];
assign ifm_buf3 = ifm_buf[3];
endmodule |
module PSUM_ADD #(
parameter data_width = 25
) (
input clk,
input rst_n,
input signed [data_width-1:0] pe0_data,
input signed [data_width-1:0] pe1_data,
input signed [data_width-1:0] pe2_data,
input signed [data_width-1:0] pe3_data,
input signed [data_width-1:0] fifo_data,
output signed [data_width-1:0] out
);
reg signed [data_width-1:0] psum0;
reg signed [data_width-1:0] psum1;
reg signed [data_width-1:0] psum2;
reg signed [data_width-1:0] out_r;
assign out = out_r;
/// Adder tree
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
psum0 <= 0;
psum1 <= 0;
psum2 <= 0;
out_r <= 0;
end else begin
psum0 <= pe0_data + pe1_data;
psum1 <= pe2_data + pe3_data;
psum2 <= psum0 + psum1;
out_r <= fifo_data + psum2;
end
end
endmodule |
module PE_FSM (clk, rst_n, start_conv, start_again, cfg_ci, cfg_co,
ifm_read, wgt_read, p_valid_output, last_chanel_output, end_conv
);
input clk;
input rst_n;
input start_conv;
input start_again;
input [1:0] cfg_ci;
input [1:0] cfg_co;
output ifm_read;
output wgt_read;
output p_valid_output;
output last_chanel_output;
output end_conv;
reg [5:0] ci;
reg [5:0] co;
reg [5:0] cnt1;
reg [8:0] cnt2;
reg [4:0] cnt3;
reg [2:0] current_state;
reg [2:0] next_state;
reg ifm_read;
reg wgt_read;
reg p_valid;
reg last_chanel;
reg end_conv;
parameter [2:0]
IDLE = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
FINISH = 3'b100;
parameter[6:0] tile_length = 16;
always @ (posedge clk or negedge rst_n)
if(!rst_n)
current_state <= IDLE;
else
current_state <= next_state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ci <= 0;
co <= 0;
end else if(start_conv) begin
ci <= ((cfg_ci + 6'b000001) << 3);
co <= ((cfg_co + 6'b000001) << 3);
end
end
always @ (current_state or start_conv or start_again or cnt1 or cnt2)
begin
next_state = 3'bx;
case(current_state)
IDLE:
if(start_again)
next_state = S1;
else if(start_again && cnt2 == 0 && cnt3 == 0)
next_state = FINISH;
else
next_state = IDLE;
S1:
next_state = (cnt1 == 4) ? S2 : S1;
S2:
if(cnt2 == 0 && cnt1 == 0)
next_state = IDLE;
else if(cnt1 == 0)
next_state = S1;
// else if(cnt1 == 0)
// next_state = S1;
else
next_state = S2;
default:
next_state = IDLE;
endcase
end
always @ (posedge clk or negedge rst_n)
if(!rst_n)
{ifm_read, wgt_read, p_valid, last_chanel, end_conv} <= 5'b00000;
else
begin
{ifm_read, wgt_read, p_valid, last_chanel, end_conv} <= 5'b00000;
case(next_state)
IDLE:
{ifm_read, wgt_read, p_valid, last_chanel, end_conv} <= 5'b00000;
S1:
begin
{ifm_read, wgt_read, end_conv} <= 3'b110;
p_valid <= (cnt1 < 3) ? 0 : 1;
last_chanel <= (cnt1 == 3 && cnt2 == 0) ? 1 : 0;
end
S2:
begin
{ifm_read, wgt_read, p_valid, end_conv} <= 4'b1010;
last_chanel <= (cnt2 == 0) ? 1 : 0;
end
FINISH:
{ifm_read, wgt_read, p_valid, last_chanel, end_conv} <= 5'b00001;
default:
{ifm_read, wgt_read, p_valid, last_chanel, end_conv} <= 5'b00000;
endcase
end
always @ (posedge clk or negedge rst_n)
if(!rst_n)
begin
cnt1 <= 0;
cnt2 <= 0;
cnt3 <= 0;
end
else
begin
if(next_state == IDLE)
cnt1 <= 0;
else
begin
if (cnt1 == tile_length + 2)
cnt1 <= 0;
else
cnt1 <= cnt1 + 1;
if(cnt1 == 0)
begin
if(cnt2 == ci-1)
cnt2 <= 0;
else
cnt2 <= cnt2 + 1;
if(cnt2 == 0)
if(cnt3 == co*15-1)
cnt3 <= 0;
else
cnt3 <= cnt3 + 1;
else
cnt3 <= cnt3;
end
else
cnt2 <= cnt2;
end
end
reg [2:0] p_valid_i;
reg [2:0] last_chanel_i;
reg p_valid_output;
reg last_chanel_output;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
p_valid_output <= 0;
p_valid_i[2] <= 0;
p_valid_i[1] <= 0;
p_valid_i[0] <= 0;
last_chanel_output <= 0;
last_chanel_i[2] <= 0;
last_chanel_i[1] <= 0;
last_chanel_i[0] <= 0;
end else begin
p_valid_output <= p_valid_i[2];
p_valid_i[2] <= p_valid_i[1];
p_valid_i[1] <= p_valid_i[0];
p_valid_i[0] <= p_valid;
last_chanel_output <= last_chanel_i[2];
last_chanel_i[2] <= last_chanel_i[1];
last_chanel_i[1] <= last_chanel_i[0];
last_chanel_i[0] <= last_chanel;
end
endmodule //PE |
module PSUM_BUFF #(
parameter data_width = 25,
parameter addr_width = 8,
parameter depth = 61
) (
input clk,
input rst_n,
input p_valid_data,
input p_write_zero,
input p_init,
input signed [data_width-1:0] pe0_data,
input signed [data_width-1:0] pe1_data,
input signed [data_width-1:0] pe2_data,
input signed [data_width-1:0] pe3_data,
output [data_width-1:0] fifo_out,
output valid_fifo_out
);
// wire [data_width-1:0] fifo_head;
// reg [data_width-1:0] fifo_head_reg;
reg [data_width-1:0] fifo_in;
wire signed [data_width-1:0] adder_out;
wire empty, full;
reg fifo_rd_en;
reg fifo_wr_en;
/// Shifter register, there are four pipeline stages
reg [3-1:0] p_valid;
reg [3-1:0] p_write_zero_reg;
/// Whether the output of current fifo output is valid
assign valid_fifo_out = p_write_zero_reg;
/// Fifo read and write
/// When to write fifo
/// Data that will be written to fifo
always @(*) begin
if (!rst_n) begin
fifo_wr_en = 0;
fifo_rd_en = 0;
fifo_in = 0;
end else if (p_init) begin
fifo_wr_en = 1;
fifo_rd_en = 0;
fifo_in = 0;
end else if (p_write_zero || p_write_zero_reg) begin
fifo_wr_en = p_write_zero_reg;
fifo_rd_en = p_write_zero;
fifo_in = 0;
end else begin
fifo_wr_en = p_valid[2];
fifo_rd_en = p_valid[0];
fifo_in = adder_out;
end
end
/// Whether the current input is valid data
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_valid <= 3'b0;
else
p_valid <= {p_valid[1:0], p_valid_data};
end
/// Whether the current write zero is valid data
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_write_zero_reg <= 1'b0;
else
p_write_zero_reg <= p_write_zero;
end
/// Adder tree
PSUM_ADD #(.data_width(data_width)) adder_tree (
.clk(clk),
.rst_n(rst_n),
.pe0_data(pe0_data),
.pe1_data(pe1_data),
.pe2_data(pe2_data),
.pe3_data(pe3_data),
.fifo_data(fifo_out),
.out(adder_out)
);
/// Synchronous fifo
SYNCH_FIFO #(
.data_width(data_width),
.addr_width(addr_width),
.depth(depth)
) synch_fifo (
.clk(clk),
.rd_en(fifo_rd_en),
.wr_en(fifo_wr_en),
.rst_n(rst_n),
.empty(empty),
.full(full),
.data_out(fifo_out),
.data_in(fifo_in)
);
endmodule |
module WRITE_BACK #(
parameter data_width = 25,
parameter depth = 61
) (
input clk,
input rst_n,
input start_init,
input p_filter_end,
input [data_width-1:0] row0,
input row0_valid,
input [data_width-1:0] row1,
input row1_valid,
input [data_width-1:0] row2,
input row2_valid,
input [data_width-1:0] row3,
input row3_valid,
input [data_width-1:0] row4,
input row4_valid,
output p_write_zero0,
output p_write_zero1,
output p_write_zero2,
output p_write_zero3,
output p_write_zero4,
output p_init,
output [data_width-1:0] out_port0,
output [data_width-1:0] out_port1,
output port0_valid,
output port1_valid,
output start_conv
);
/// machine state encode
localparam IDLE = 4'b0000;
localparam INIT_BUFF = 4'b0001;
localparam START_CONV = 4'b0010;
localparam WAIT_ADD = 4'b0011;
localparam ROW_0_1 = 4'b0100;
localparam CLEAR_0_1 = 4'b0101;
localparam ROW_2_3 = 4'b0110;
localparam CLEAR_2_3 = 4'b0111;
localparam ROW_5 = 4'b1000;
localparam CLEAR_START_CONV = 4'b1001;
localparam CLEAR_CNT = 4'b1010;
// localparam DONE = 4'b1001;
/// machine state
reg [3:0] st_next;
reg [3:0] st_cur;
reg [7:0] cnt;
/// State transfer
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
st_cur <= IDLE;
else
st_cur <= st_next;
end
/// Next state logic
always @(*) begin
st_next = st_cur;
case(st_cur)
IDLE:
if (start_init)
st_next = INIT_BUFF;
else
st_next = IDLE;
INIT_BUFF:
if (cnt == depth-1)
st_next = START_CONV;
else
st_next = INIT_BUFF;
START_CONV:
if (cnt >= depth+2)
st_next = CLEAR_START_CONV;
else
st_next = START_CONV;
CLEAR_START_CONV:
if (p_filter_end)
st_next = WAIT_ADD;
else
st_next = CLEAR_START_CONV;
WAIT_ADD:
if (cnt == depth-1)
st_next = CLEAR_CNT;
else
st_next = WAIT_ADD;
CLEAR_CNT:
st_next = ROW_0_1;
ROW_0_1:
if (cnt == depth-1)
st_next = CLEAR_0_1;
else
st_next = ROW_0_1;
CLEAR_0_1:
st_next = ROW_2_3;
ROW_2_3:
if (cnt == depth-1)
st_next = CLEAR_2_3;
else
st_next = ROW_2_3;
CLEAR_2_3:
st_next = ROW_5;
ROW_5:
if (cnt == depth-1)
st_next = START_CONV;
else
st_next = ROW_5;
// DONE:
// st_next = START_CONV;
default:
st_next = IDLE;
endcase
end
/// Output logic
reg p_write_zero0_r;
reg p_write_zero1_r;
reg p_write_zero2_r;
reg p_write_zero3_r;
reg p_write_zero4_r;
reg p_init_r;
reg [data_width-1:0] out_port0_r;
reg [data_width-1:0] out_port1_r;
reg port0_valid_r;
reg port1_valid_r;
reg start_conv_r;
/// Output start conv signal
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
start_conv_r <= 0;
else if (st_cur == START_CONV)
start_conv_r <= 1;
else
start_conv_r <= 0;
end
assign start_conv = start_conv_r;
/// Output zero flag signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero0_r <= 0;
p_write_zero1_r <= 0;
end else if (st_cur == ROW_0_1) begin
p_write_zero0_r <= 1;
p_write_zero1_r <= 1;
end else begin
p_write_zero0_r <= 0;
p_write_zero1_r <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero2_r <= 0;
p_write_zero3_r <= 0;
end else if (st_cur == ROW_2_3) begin
p_write_zero2_r <= 1;
p_write_zero3_r <= 1;
end else begin
p_write_zero2_r <= 0;
p_write_zero3_r <= 0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
p_write_zero4_r <= 0;
end else if (st_cur == ROW_5) begin
p_write_zero4_r <= 1;
end else begin
p_write_zero4_r <= 0;
end
end
assign p_write_zero0 = p_write_zero0_r;
assign p_write_zero1 = p_write_zero1_r;
assign p_write_zero2 = p_write_zero2_r;
assign p_write_zero3 = p_write_zero3_r;
assign p_write_zero4 = p_write_zero4_r;
/// Init buffer signal, why this signal? since, at the beginning, the buffer is empty, we only need to
/// push zero to buffer without read from it, this behaviour is difference from p_write_zerox signals
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
p_init_r <= 0;
else if (st_cur == INIT_BUFF)
p_init_r <= 1;
else
p_init_r <= 0;
end
assign p_init = p_init_r;
/// Update the cnt
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cnt <= 0;
else if (st_cur == IDLE || st_cur == CLEAR_0_1 || st_cur == CLEAR_START_CONV
|| st_cur == CLEAR_2_3 || st_cur == CLEAR_CNT)
cnt <= 0;
else
cnt <= cnt + 1;
end
/// Final result, a big mux
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_port0_r <= 0;
out_port1_r <= 0;
port0_valid_r <= 0;
port1_valid_r <= 0;
end else begin
case({row0_valid, row1_valid, row2_valid, row3_valid, row4_valid})
5'b11000 : begin
out_port0_r <= row0;
out_port1_r <= row1;
port0_valid_r <= row0_valid;
port1_valid_r <= row1_valid;
end
5'b00110 : begin
out_port0_r <= row2;
out_port1_r <= row3;
port0_valid_r <= row2_valid;
port1_valid_r <= row3_valid;
end
5'b00001 : begin
out_port0_r <= row4;
out_port1_r <= 0;
port0_valid_r <= row4_valid;
port1_valid_r <= 0;
end
default : begin
out_port0_r <= 0;
out_port1_r <= 0;
port0_valid_r <= 0;
port1_valid_r <= 0;
end
endcase
end
end
assign out_port0 = out_port0_r;
assign out_port1 = out_port1_r;
assign port0_valid = port0_valid_r;
assign port1_valid = port1_valid_r;
endmodule |
module TEST_PSUM_BUFF();
reg clk;
reg rst_n, p_valid_data, p_write_zero, p_init;
reg signed [`BUF_DATA_WIDTH-1:0] pe0_data;
reg signed [`BUF_DATA_WIDTH-1:0] pe1_data;
reg signed [`BUF_DATA_WIDTH-1:0] pe2_data;
reg signed [`BUF_DATA_WIDTH-1:0] pe3_data;
wire signed [`BUF_DATA_WIDTH-1:0] fifo_out;
reg signed [`BUF_DATA_WIDTH-1:0] temp;
wire valid_fifo_out;
PSUM_BUFF #(
.data_width(`BUF_DATA_WIDTH),
.addr_width(`BUF_ADDR_WIDTH),
.depth(`BUF_DEPTH)
) psum_buff (
.clk(clk),
.rst_n(rst_n),
.p_valid_data(p_valid_data),
.p_write_zero(p_write_zero),
.p_init(p_init),
.pe0_data(pe0_data),
.pe1_data(pe1_data),
.pe2_data(pe2_data),
.pe3_data(pe3_data),
.fifo_out(fifo_out),
.valid_fifo_out(valid_fifo_out)
);
// generate clock
initial begin
#5 clk = 1'b1;
forever #5 clk = ~clk;
end
/// Write zero task
task write_zero;
output signed [`BUF_DATA_WIDTH-1:0] out;
begin
p_init = 1;
@(posedge clk);
out = fifo_out;
$display("Current fifo head: ", out);
#1 p_init = 0;
end
endtask
/// Write zero task
task write_zero_filter;
output signed [`BUF_DATA_WIDTH-1:0] out;
begin
p_write_zero = 1;
@(posedge clk);
out = fifo_out;
$display("Current fifo head: ", out);
#1 p_write_zero = 0;
end
endtask
/// push data task
task push_data;
input signed [`BUF_DATA_WIDTH-1:0] data0;
input signed [`BUF_DATA_WIDTH-1:0] data1;
input signed [`BUF_DATA_WIDTH-1:0] data2;
input signed [`BUF_DATA_WIDTH-1:0] data3;
begin
$display("Push data: ", data0, data1, data2, data3);
pe0_data = data0;
pe1_data = data1;
pe2_data = data2;
pe3_data = data3;
p_valid_data = 1;
@(posedge clk);
#1 p_valid_data = 0;
end
endtask
integer i;
integer j;
initial begin
rst_n = 1;
p_valid_data = 0;
p_write_zero = 0;
p_init = 0;
pe0_data = 0;
pe1_data = 0;
pe2_data = 0;
pe3_data = 0;
#5 rst_n = 0;
#10 rst_n = 1;
write_zero(temp);
write_zero(temp);
write_zero(temp);
write_zero(temp);
write_zero(temp);
write_zero(temp);
write_zero(temp);
write_zero(temp);
push_data(1,1,1,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,2,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,3,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,4,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,5,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,6,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,7,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,8,2,2);
$display("Current fifo head is: ", fifo_out);
#30 p_valid_data = 0;
push_data(1,1,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,2,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,3,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,4,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,5,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,6,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,7,2,2);
$display("Current fifo head is: ", fifo_out);
push_data(1,8,2,2);
$display("Current fifo head is: ", fifo_out);
#30 p_valid_data = 0;
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
write_zero_filter(temp);
end
endmodule |
module Counter(
input enable,
output [3:0] counter_out,
input clk,
input rst_n
);
reg [3:0] cnt_R;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt_R <= 'd0;
else if(enable)
cnt_R <= cnt_R + 1'b1;
end
assign counter_out = cnt_R;
endmodule |
module tb_counter();
reg clk;
reg rst_n;
reg enable;
wire [3:0] counter_tb;
Counter dut(.enable(enable), .counter_out(counter_tb), .clk(clk), .rst_n(rst_n));
// generate clock
initial begin
#5 clk = 1'b1;
forever #5 clk = ~clk;
end
task check_count;
begin
@(negedge clk);
$display("Checking counter %0d at %0t", counter_tb, $time);
end
endtask
initial begin
#1 rst_n = 1'b1;
enable = 0;
#22 $display("Begin to reset the counter @%0t", $time);
rst_n = 1'b0;
@(posedge clk);
@(negedge clk);
$display("Checking the counter after reset @%0t", $time);
$display("Counter suppose is 0 and we get %0d from dut", counter_tb);
repeat(5) @(posedge clk);
#0 rst_n = 1'b1;
$display("Disable reset @%0t", $time);
repeat(5) @(posedge clk);
#0 enable = 1'b1;
$display("Setting the enable signal @%0t", $time);
$display("checking the counter for 20 cycle:");
repeat(20) check_count;
@(negedge clk);
#0 enable = 1'b0;
$display("Disable the enable signal @%0t", $time);
$display("checking the counter for 10 cycle:");
repeat(10) check_count;
#20 $finish;
end
endmodule |
module TEST_FIFO ();
reg clk, rst_n, wr_en, rd_en;
reg [`BUF_DATA_WIDTH-1:0] data_in;
reg [`BUF_DATA_WIDTH-1:0] temp;
wire [`BUF_DATA_WIDTH-1:0] data_out;
wire empty;
wire full;
SYNCH_FIFO #(
.data_width(`BUF_DATA_WIDTH),
.addr_width(`BUF_ADDR_WIDTH),
.depth(`BUF_DEPTH)
) synch_fifo (
.clk(clk),
.rd_en(rd_en),
.wr_en(wr_en),
.rst_n(rst_n),
.empty(empty),
.full(full),
.data_out(data_out),
.data_in(data_in)
);
/// Push task
task push;
input [`BUF_DATA_WIDTH-1:0] data;
if (full)
$display("Opps! Buffer already full, pop then push");
else begin
$display("Pushed: ", data);
data_in = data;
wr_en = 1;
@(posedge clk);
#1 wr_en = 0;
end
endtask
/// Pop task
task pop;
output [`BUF_DATA_WIDTH-1:0] data;
if (empty)
$display("Opps! Buffer is empty nothing to pop");
else begin
rd_en = 1;
@(posedge clk);
#1 rd_en = 0;
data = data_out;
$display("Poped: ", data);
end
endtask
/// clock generation
always #5 clk = ~clk;
/// Run simulation
initial begin
clk = 0;
rst_n = 1;
rd_en = 0;
wr_en = 0;
temp = 0;
data_in = 0;
#5 rst_n = 0;
#10 rst_n = 1;
push(1);
fork
push(2);
pop(temp);
join
push(10);
push(20);
push(30);
push(40);
push(50);
push(60);
push(70);
push(80);
push(90);
push(100);
push(110);
push(120);
push(130);
pop(temp);
push(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
push(140);
pop(temp);
push(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
pop(temp);
push(5);
pop(temp);
end
endmodule |
module clkgen (
input wire clk,
output wire [2:0] cnt
);
// Connect to system clock (with buffering)
wire clko;
SB_GB clk_gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(clk),
.GLOBAL_BUFFER_OUTPUT(clko)
);
// Use counter logic to divide system clock. The clock is 48 MHz,
// so we divide it down by 2^28.
reg [28:0] counter = 0;
always @(posedge clko) begin
counter <= counter + 1;
end
assign cnt = counter[25:23];
endmodule |
module RF(
input write,
input clk,
input reset_n,
input [1:0] addr1,
input [1:0] addr2,
input [1:0] addr3,
output [15:0] data1,
output [15:0] data2,
input [15:0] data3
);
reg [63:0] register;
/*
register[63:48] == register[16*3+: 16] (addr is 2'b11)
register[47:32] == register[16*2+: 16] (addr is 2'b10)
register[31:16] == register[16*1+: 16] (addr is 2'b01)
register[15: 0] == register[16*0+: 16] (addr is 2'b00)
*/
always @(posedge clk) begin
// Synchronous active low reset
if (!reset_n) register <= 64'b0;
// Synchronous data write
else if (write) register[16*addr3+: 16] <= data3;
end
// Asynchronous data read
assign data1 = register[16*addr1+: 16];
assign data2 = register[16*addr2+: 16];
endmodule |
module ALU(
input signed [15:0] A,
input signed [15:0] B,
input [3:0] OP,
output reg signed [15:0] C,
output branch_cond
);
always @(*) begin
case (OP)
0: C = A + B; // ADD, ADI, LWD, SWD
1: C = A - B; // SUB
2: C = A & B; // AND
3: C = A | B; // ORR, ORI
4: C = ~A; // NOT
5: C = ~A + 1'b1; // TCP
6: C = A << 1; // SHL
7: C = A >>> 1; // SHR
8: C = {B[7:0], 8'b0}; // LHI
9: C = A - B; // BNE
10: C = A - B; // BEQ
11: C = A; // BGZ
12: C = A; // BLZ
default: C = 16'bz;
endcase
end
// Using assign, C and bcond change at the same time.
// The timing would have been different if they were inside a single always block.
assign branch_cond = OP==9 ? (C!=0) : // BNE
OP==10 ? (C==0) : // BEQ
OP==11 ? (C>0) : // BGZ
OP==12 ? (C<0) : 0; // BLZ
endmodule |
module Control(
input clk,
input reset_n,
input [3:0] opcode,
input [5:0] func,
output PCWriteCond,
output PCWrite,
output IorD,
output ReadM,
output WriteM,
output [1:0] RegSrc,
output IRWrite,
output RegWrite,
output [1:0] RegDst,
output [1:0] PCSrc,
output ALUSrcA,
output [1:0] ALUSrcB,
output Halt,
output OpenPort,
output reg [3:0] ALUOp,
output increment_num_inst
);
/*
Implementation of a micro-code controller using a ROM.
Receives opcode and function code of an instruction, and generates control signals.
Only those that are different from the lecture slide are explained here.
RegSrc[2] : Data being written to the RF. B(00) or MDR(01) or PC(10)
RegDst[2] : Adress of register to write to. Inst[9:8](00) or Inst[7:6](01) or 2(10)
PCSrc[2] : Source of next PC. ALU result right now(00) or ALU result last cycle(01) or jump target(10) or A(11)
ALUSrcB[2] : Second input to ALU. B(00) or 1(01) or sign-extended immediate(10)
increment_num_inst : signal that the next state is IF. CPU should increment num_inst for test.
*/
reg [4:0] state, next_state; // State code, as well as register transfer code, are defined in the design document. You can find this in my report.
reg [3:0] one, two; // Input to ROM. Code of (at most) two register transfers that occur this cycle.
wire [`NUM_CTRL-1:0] CTRL; // Output from ROM. (Almost) all control signals.
// Unpack CTRL from ROM.
assign {PCWriteCond, PCWrite, IorD, ReadM, WriteM, RegSrc, IRWrite, RegWrite, RegDst, PCSrc, ALUSrcA, ALUSrcB} = CTRL;
// Halt and OpenPort
assign Halt = (opcode==`OPCODE_R & func==`FUNC_HLT & state==2);
assign OpenPort = (opcode==`OPCODE_R & func==`FUNC_WWD & state==2);
assign increment_num_inst = (next_state == 0);
// State transition
always @(posedge clk) begin
if (!reset_n) state <= 0;
else state <= next_state;
end
// Set next_state
always @(*) begin
case (state)
0: begin
if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD) next_state = 1;
else if ((opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) | opcode==`OPCODE_SWD) next_state = 2;
else if (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ) next_state = 3;
else if (opcode==`OPCODE_JMP) next_state = 4;
else if (opcode==`OPCODE_JAL) next_state = 5;
else if (opcode==`OPCODE_R & func==`FUNC_JPR) next_state = 6;
else if (opcode==`OPCODE_R & func==`FUNC_JRL) next_state = 7;
end
1: begin
if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI) next_state = 8;
else if (opcode==`OPCODE_LWD) next_state = 10;
end
2: begin
if (opcode==`OPCODE_R & (func==`FUNC_WWD | func==`FUNC_HLT)) next_state = 0;
else if (opcode==`OPCODE_R & func!=`FUNC_JPR & func!=`FUNC_JRL) next_state = 9;
else if (opcode==`OPCODE_SWD) next_state = 10;
end
3: next_state = 11;
4: next_state = 0;
5: next_state = 0;
6: next_state = 0;
7: next_state = 0;
8: next_state = 12;
9: next_state = 13;
10: begin
if (opcode==`OPCODE_LWD) next_state = 14;
else if (opcode==`OPCODE_SWD) next_state = 15;
end
11: next_state = 0;
12: next_state = 0;
13: next_state = 0;
14: next_state = 16;
15: next_state = 0;
16: next_state = 0;
endcase
end
// Set 'one'
always @(*) begin
case (state)
0: one = 0;
1: one = `NUM_RT;
2: one = `NUM_RT;
3: one = 2;
4: one = 3;
5: one = 3;
6: one = 5;
7: one = 4;
8: one = 6;
9: one = 7;
10: one = 6;
11: one = 7;
12: one = 9;
13: one = 10;
14: one = 11;
15: one = 12;
16: one = 13;
default: one = 0;
endcase
end
// Set 'two'
always @(*) begin
if (state==0) two = 1;
else if (state==5) two = 4;
else if (state==7) two = 5;
else if (state==11) two = 8;
else two = `NUM_RT;
end
// Set ALUOp
always @(*) begin
if (state==0 | state==3 | state==10) begin
ALUOp = 0;
end else if (state==8) begin
if (opcode==`OPCODE_ADI) ALUOp = 0;
else if (opcode==`OPCODE_ORI) ALUOp = 3;
else if (opcode==`OPCODE_LHI) ALUOp = 8;
else ALUOp = 15;
end else if (state==9) begin
if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
else ALUOp = 15;
end else if (state==11) begin
if (opcode==`OPCODE_BNE) ALUOp = 9;
else if (opcode==`OPCODE_BEQ) ALUOp = 10;
else if (opcode==`OPCODE_BGZ) ALUOp = 11;
else if (opcode==`OPCODE_BLZ) ALUOp = 12;
else ALUOp = 15;
end else begin
ALUOp = 15;
end
end
// Instantiate ROM
ROM rom (.one(one),
.two(two),
.CTRL(CTRL));
endmodule |
module cpu (
output reg readM, // read from memory
output reg writeM, // write to memory
output reg [`WORD_SIZE-1:0] address, // current address for data
inout [`WORD_SIZE-1:0] data, // data being input or output
input inputReady, // indicates that data is ready from the input port
input reset_n, // active-low RESET signal
input clk, // clock signal
// for debuging/testing purpose
output reg [`WORD_SIZE-1:0] num_inst, // number of instruction during execution
output [`WORD_SIZE-1:0] output_port, // this will be used for a "WWD" instruction
output is_halted // 1 if the cpu is halted
);
///////////////////////////// Declarations and Instantiations /////////////////////////////
// Testbench purposes
reg [`WORD_SIZE-1:0] internal_num_inst; // only show num_inst value for exactly one cycle in each instruction
// Registers in the CPU
reg [`WORD_SIZE-1:0] PC, nextPC;
reg [`WORD_SIZE-1:0] IR, MDR;
reg [`WORD_SIZE-1:0] A, B;
reg [`WORD_SIZE-1:0] ALUOut;
// Control module
wire PCWriteCond, PCWrite, IorD, control_read, control_write, IRWrite, RegWrite, ALUSrcA, OpenPort, increment_num_inst;
wire [1:0] RegSrc, RegDst, PCSrc, ALUSrcB;
wire [3:0] ALUOp;
Control control (clk, reset_n, IR[15:12], IR[5:0], PCWriteCond, PCWrite, IorD, control_read, control_write, RegSrc,
IRWrite, RegWrite, RegDst, PCSrc, ALUSrcA, ALUSrcB, is_halted, OpenPort, ALUOp, increment_num_inst);
// RF
reg [`WORD_SIZE-1:0] WriteAddress, WriteData;
wire [`WORD_SIZE-1:0] ReadData1, ReadData2;
RF rf (RegWrite, clk, reset_n, IR[11:10], IR[9:8], WriteAddress, ReadData1, ReadData2, WriteData);
// ALU
reg [`WORD_SIZE-1:0] ALUin1, ALUin2;
wire [`WORD_SIZE-1:0] ALUResult;
wire branch_cond;
ALU alu (ALUin1, ALUin2, ALUOp, ALUResult, branch_cond);
///////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////// CPU reset ////////////////////////////////////////
always @(posedge clk) begin
if (!reset_n) begin // Synchronous active-low reset
PC <= 0;
internal_num_inst <= 1;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Outward Signals /////////////////////////////////////
// Only open output_port when control signal OpenPort is asserted,
assign output_port = OpenPort ? ReadData1 : `WORD_SIZE'bz;
// increment_num_inst is asserted when the current stage is the last stage of this instruction.
always @(posedge increment_num_inst) begin
internal_num_inst <= internal_num_inst + 1;
end
always @(increment_num_inst) begin
if (increment_num_inst) num_inst = internal_num_inst;
else num_inst = 0;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Memory Access //////////////////////////////////////
// Read
always @(posedge control_read) begin
if (IorD) address <= ALUOut;
else address <= PC;
readM <= 1;
end
always @(posedge inputReady) begin
if (IRWrite) IR <= data; // instruction fetch mode
else MDR <= data; // data fetch mode
readM <= 0;
end
// Write
assign data = control_write ? B : `WORD_SIZE'bz;
always @(posedge control_write) begin
address <= ALUOut;
writeM <= 1;
end
always @(negedge clk) begin // Kill writeM before posedge.
writeM <= 0;
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////// Updating PC ///////////////////////////////////////
// Determine nextPC
always @(*) begin
case (PCSrc)
0: nextPC = ALUResult;
1: nextPC = ALUOut;
2: nextPC = { PC[15:12], IR[11:0] };
3: nextPC = ReadData1;
default: begin end
endcase
end
// Update PC at clock posedge
always @(posedge clk) begin
if (reset_n)
if (PCWrite | (PCWriteCond & branch_cond)) PC <= nextPC;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Register File //////////////////////////////////////
always @(*) begin
case (RegDst)
0: WriteAddress = IR[9:8];
1: WriteAddress = IR[7:6];
2: WriteAddress = 2'b10;
default: begin end
endcase
case (RegSrc)
0: WriteData = ALUOut;
1: WriteData = MDR;
2: WriteData = PC;
default: begin end
endcase
end
// Register transfer every clock
always @(posedge clk) begin
if(reset_n) begin
A <= ReadData1;
B <= ReadData2;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// ALU ///////////////////////////////////////////
always @(*) begin
case (ALUSrcA)
0: ALUin1 = PC;
1: ALUin1 = A;
default: begin end
endcase
case (ALUSrcB)
0: ALUin2 = B;
1: ALUin2 = 16'b1;
2: ALUin2 = { {8{IR[7]}}, IR[7:0] };
default: begin end
endcase
end
// Register transfer every clock
always @(posedge clk) begin
if (reset_n) ALUOut <= ALUResult;
end
///////////////////////////////////////////////////////////////////////////////////////////
endmodule |
module ROM(
input [3:0] one,
input [3:0] two,
output [`NUM_CTRL-1:0] CTRL
);
/*
Input:
There are at maximum two register transfers in a single state (cycle). 'one' and 'two' represent each of their RT codes.
For states with only one RT, 'one' is 13.
Output:
CTRL = elementwise-OR( control_signal of 'one', control_signal of 'two' )
Output CTRL signal bits correspond to:
PCWriteCond, PCWrite, IorD, ReadM, WriteM, RegSrc[2], IRWrite, RegWrite, RegDst[2], PCSrc[2], ALUSrcA, ALUSrcB[2]
*/
parameter [`NUM_CTRL*(`NUM_RT+1)-1:0] memory = {
`NUM_CTRL'b0_0_0_0_0_00_0_0_00_00_0_00, // 14: All zero. Does nothing when performed OR with something else.
`NUM_CTRL'b0_0_0_0_0_01_0_1_00_00_0_00, // 13
`NUM_CTRL'b0_0_1_0_1_00_0_0_00_00_0_00, // 12
`NUM_CTRL'b0_0_1_1_0_00_0_0_00_00_0_00, // 11
`NUM_CTRL'b0_0_0_0_0_00_0_1_01_00_0_00, // 10
`NUM_CTRL'b0_0_0_0_0_00_0_1_00_00_0_00, // 9
`NUM_CTRL'b1_0_0_0_0_00_0_0_00_01_1_00, // 8
`NUM_CTRL'b0_0_0_0_0_00_0_0_00_00_1_00, // 7
`NUM_CTRL'b0_0_0_0_0_00_0_0_00_00_1_10, // 6
`NUM_CTRL'b0_1_0_0_0_00_0_0_00_11_0_00, // 5
`NUM_CTRL'b0_0_0_0_0_10_0_1_10_00_0_00, // 4
`NUM_CTRL'b0_1_0_0_0_00_0_0_00_10_0_00, // 3
`NUM_CTRL'b0_0_0_0_0_00_0_0_00_00_0_10, // 2
`NUM_CTRL'b0_1_0_0_0_00_0_0_00_00_0_01, // 1
`NUM_CTRL'b0_0_0_1_0_00_1_0_00_00_0_00 // 0
};
assign CTRL = memory[`NUM_CTRL*one+:`NUM_CTRL] | memory[`NUM_CTRL*two+:`NUM_CTRL];
endmodule |
module external_device(
input wire [`DEVICE_BIT_LEN - 1 :0] offset,
output reg interrupt,
output reg [4 * `WORD_SIZE - 1 : 0] data);
reg [4 * `WORD_SIZE - 1 : 0] storage [`DATA_SIZE - 1 : 0];
initial begin
/* Randomized storage initialization.
* You may want to change these for the
* debugging */
storage[0] <= $random;
storage[1] <= $random;
storage[2] <= $random;
interrupt <= 0;
/* Fire interrupt. You may want to change */
#(`FIRE_TIME);
interrupt <= 1;
/* Interrupt duration. You may want to change */
#(`INTTERRUPT_DURATION);
interrupt <= 0;
/* Randomized storage initialization.
* You may want to change these for the
* debugging */
storage[0] <= $random;
storage[1] <= $random;
storage[2] <= $random;
/* Another interrupt. You may want to change */
#(`FIRE_TIME);
interrupt <= 1;
/* Interrupt duration. You may want to change */
#(`INTTERRUPT_DURATION);
interrupt <= 0;
//$finish;
end
/* Data to be send */
always @(offset) begin
if (offset < 3) data <= storage[offset];
else data <= 16'hzzzz;
end
endmodule |
module Control(
input [3:0] opcode,
input [5:0] func,
input BranchMisprediction, JumpMisprediction, DataHazard, InstCacheBusy, DataCacheBusy,
output PCWrite, IFIDWrite, IFIDFlush, IDEXWrite, IDEXFlush, EXMEMWrite, MEMWBWrite,
output reg IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, ALUSrcA, RegSrc, Halt, OpenPort,
output reg [1:0] RegDst, ALUSrcB,
output reg [3:0] ALUOp
);
/*
[CPU control module]
Functionality:
By looking at the opcode and func field of an instruction, this module outputs appropriate control signals.
Also, when notified of branch/jump misprediction or pipeline stall, this module outputs control signals that
flush or stall part of the pipeline.
Inputs:
opcode and function code of the current instruction
BranchMisprediction, JumpMisprediction, are asserted when its name is detected at the CPU module.
Stall is asserted when the pipeline needs to stall due to data hazards.
Outputs: only those that are different from the lecture slide are explained here.
JumpType : Which type of jump destination? JumpAddress(0) or Rs(1)
RegSrc : Data being written to the RF. ALUResult(0) or MDR(1)
RegDst[2] : Adress of register to write to. Rt(00) or Rd(01) or 2(10)
ALUSrcA : First input to ALU. RFRead1(0) or PC(1)
ALUSrcB[2] : Second input to ALU. RFRead2(0) or sign-extended immediate(1) or 1(2)
IFIDWrite : Write enable bit for IF/ID pipeline register
IFIDFlush : Flush IFID pipeline register if enabled
IDEXWrite : Write enable bit for ID/EX pipeline register
*/
// Determine PC and pipeline register transfer control signals
assign PCWrite = ((!InstCacheBusy && !DataHazard) || (InstCacheBusy && (JumpMisprediction || BranchMisprediction))) && !DataCacheBusy;
assign IFIDWrite = (!InstCacheBusy && !DataCacheBusy && !DataHazard && !BranchMisprediction && !JumpMisprediction);
assign IFIDFlush = (!IFIDWrite && !DataHazard && !DataCacheBusy);
assign IDEXWrite = (!BranchMisprediction && !DataHazard && !DataCacheBusy);
assign IDEXFlush = (BranchMisprediction || DataHazard) && !DataCacheBusy;
assign EXMEMWrite = (!DataCacheBusy);
assign MEMWBWrite = (!DataCacheBusy);
// Determine usual control signals
always @(*) begin
JumpType = (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL));
DataMemRead = !DataHazard & (opcode==`OPCODE_LWD);
DataMemWrite = !DataHazard & (opcode==`OPCODE_SWD);
RegWrite = !DataHazard & ((opcode==`OPCODE_R & (func==`FUNC_ADD | func==`FUNC_SUB | func==`FUNC_AND | func==`FUNC_ORR | func==`FUNC_NOT | func==`FUNC_TCP | func==`FUNC_SHL | func==`FUNC_SHR | func==`FUNC_JRL)) | opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_JAL);
IsBranch = (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ);
IsJump = (opcode==`OPCODE_JMP | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL)));
ALUSrcA = (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL));
RegSrc = (opcode==`OPCODE_LWD);
Halt = (opcode==`OPCODE_R & func==`FUNC_HLT);
OpenPort = !BranchMisprediction & !JumpMisprediction & !DataHazard & (opcode==`OPCODE_R & func==`FUNC_WWD);
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUSrcB = 2;
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD) ALUSrcB = 1;
else ALUSrcB = 0;
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) RegDst = 2;
else if (opcode==`OPCODE_R) RegDst = 1;
else RegDst = 0;
end
// Determine usual ALU operation
always @(*) begin
if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUOp = 0;
else if (opcode==`OPCODE_ORI) ALUOp = 3;
else if (opcode==`OPCODE_LHI) ALUOp = 8;
else if (opcode==`OPCODE_BNE) ALUOp = 9;
else if (opcode==`OPCODE_BEQ) ALUOp = 10;
else if (opcode==`OPCODE_BGZ) ALUOp = 11;
else if (opcode==`OPCODE_BLZ) ALUOp = 12;
else ALUOp = 15; // undefined operation
end
endmodule |
module DCache(
input clk,
input reset_n,
// communication with CPU
input d_readC, d_writeC,
input [15:0] d_address,
inout [15:0] d_data,
output DataCacheBusy,
// communication with Memory
output reg d_readM, d_writeM,
output [13:0] d_address_mem,
inout [63:0] d_data_mem,
// DMA support
input BR,
output reg BG
);
/*
Latency:
Read/write hit: 1 cycle
Read/write miss, no evict: 6 cycles (1 for cache search, 4 for memory read, 1 for cache search)
Read/write miss, yes evict: 10 cycles (1 for cache search, 4 for cache line eviction, 4 for memory read, 1 for cache search)
Output:
DataCacheBusy: asserted when the cache is fetching the requested data.
deasserted right before the cycle data is provided, so that the CPU can detect fetch finish at posedge clk.
Hence, (the number of cycles DataCacheBusy==1) + 1 is the cache's latency.
*/
reg [11:0] TagBank [3:0];
reg Valid [3:0];
reg Dirty [3:0];
reg [63:0] DataBank [3:0];
wire [11:0] tag;
wire [1:0] idx;
wire [1:0] block;
wire hit, evict;
reg [2:0] DataCacheCounter;
assign tag = d_address[15:4];
assign idx = d_address[3:2];
assign block = d_address[1:0];
assign hit = (TagBank[idx]==tag) && Valid[idx];
assign evict = (Dirty[idx]);
// Read hit is handled combinationally
assign d_data = (d_readC && hit) ? DataBank[idx][16*block+:16] : 16'hz;
assign d_address_mem = (BG || (BR && !d_readM && !d_writeM)) ? 14'bz : { tag, idx };
assign d_data_mem = (d_writeM && evict && !(BG || (BR && !d_readM && !d_writeM))) ? DataBank[idx] : 64'hz;
// Becomes zero when data is fetched into the cache, since hit becomes 1.
assign DataCacheBusy = (d_readC || d_writeC) && !hit;
// Cache reset
always @(posedge clk) begin
if (!reset_n) begin
{ TagBank[3], TagBank[2], TagBank[1], TagBank[0] } <= 0;
{ Valid[3], Valid[2], Valid[1], Valid[0] } <= 0;
{ Dirty[3], Dirty[2], Dirty[1], Dirty[0] } <= 0;
{ DataBank[3], DataBank[2], DataBank[1], DataBank[0] } <= 0;
d_readM <= 0;
d_writeM <= 0;
DataCacheCounter <= 0;
BG <= 0;
end
end
// Immediately remove bus grant when bus request is deasserted
always @(negedge BR) begin
BG <= 0;
end
// Data read/write miss
always @(posedge clk) begin
if (reset_n) begin
//Bus is requested by the DMA, and data memory is not being accessed => start DMA!
if (BG || (BR && !d_readM && !d_writeM)) begin
if (BR) begin
BG <= 1;
d_writeM <= 1'bz;
end else begin
BG <= 0;
end
// Data memory access
end else if ((d_readC || d_writeC) && !hit) begin
if (evict) begin // evict cache line to memory. actual evicting logic is located at the next always statement.
if (DataCacheCounter == 0) begin
d_writeM <= 1;
DataCacheCounter <= `LATENCY;
end else begin
DataCacheCounter <= DataCacheCounter - 1;
end
end else begin // fetch cache line from memory
if (DataCacheCounter == 0) begin
d_readM <= 1;
DataCacheCounter <= `LATENCY;
end else if (DataCacheCounter == 1) begin
TagBank[idx] <= tag;
Valid[idx] <= 1;
Dirty[idx] <= 0;
DataBank[idx] <= d_data_mem;
d_readM <= 0;
end else begin
DataCacheCounter <= DataCacheCounter - 1;
end
end
// Data cache idle
end else begin
d_readM <= 0;
d_writeM <= 0;
DataCacheCounter <= 0;
end
end
end
// Cache line eviction
always @(negedge clk) begin
if (reset_n && !hit && evict && DataCacheCounter == 1) begin
Dirty[idx] <= 0; // Dirty bit cleared. Now the evict signal will drop.
Valid[idx] <= 0;
d_writeM <= 0;
DataCacheCounter <= 0;
end
end
// Data write hit: latch to cache at next posedge
always @(posedge clk) begin
if (reset_n) begin
if (d_writeC && hit) begin
DataBank[idx][16*block+:16] <= d_data;
Dirty[idx] <= 1;
end
end
end
// For measuring hit ratio
integer data_hit_instructions, data_total_instructions;
always @(posedge clk) begin
if (!reset_n) begin
data_hit_instructions <= 0;
data_total_instructions <= 0;
end
end
always @(negedge clk) begin
if ((d_readC || d_writeC) && hit) data_total_instructions <= data_total_instructions + 1;
if ((d_readC || d_writeC) && hit && DataCacheCounter==0) data_hit_instructions <= data_hit_instructions + 1;
end
endmodule |
module cpu (
input Clk,
input Reset_N,
// Instruction memory interface
output i_readM,
output i_writeM,
output [13:0] i_address,
inout [63:0] i_data,
// Data memory interface
output d_readM,
output d_writeM,
output [13:0] d_address,
inout [63:0] d_data,
// TB purpose
output [`WORD_SIZE-1:0] num_inst,
output [`WORD_SIZE-1:0] output_port,
output is_halted, // 1 if the cpu is halted
// DMA
input dma_start_int, dma_end_int, BR,
output BG,
output reg cmd
);
///////////////////////////// Declarations and Instantiations /////////////////////////////
// Register and wire declarations
// Testbench purposes
reg LastCycleFetch; // asserted when an instruction was latched into the ID stage last cycle.
reg [`WORD_SIZE-1:0] internal_num_inst; // only show num_inst value for exactly one cycle in each instruction
// Program Counter related
reg [`WORD_SIZE-1:0] PC, nextPC;
// IF/ID pipeline registers. no control signals
reg [`WORD_SIZE-1:0] IF_ID_Inst, IF_ID_PC, IF_ID_nextPC;
// ID/EX pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] ID_EX_RFRead1, ID_EX_RFRead2, ID_EX_SignExtendedImm, ID_EX_PC, ID_EX_nextPC;
reg [1:0] ID_EX_RFWriteAddress;
// control signals
reg ID_EX_IsBranch, ID_EX_ALUSrcA, ID_EX_DataMemRead, ID_EX_DataMemWrite, ID_EX_RegWrite, ID_EX_Halt, ID_EX_RegSrc;
reg [1:0] ID_EX_RegDst, ID_EX_ALUSrcB;
reg [3:0] ID_EX_ALUOp;
// EX/MEM pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] EX_MEM_RFRead2, EX_MEM_PC, EX_MEM_ALUResult;
reg [1:0] EX_MEM_RFWriteAddress;
// control signals
reg EX_MEM_DataMemRead, EX_MEM_DataMemWrite, EX_MEM_RegWrite, EX_MEM_RegSrc;
// MEM/WB pipeline registers
//non - control signals
reg [`WORD_SIZE-1:0] MEM_WB_RFRead2, MEM_WB_MemData, MEM_WB_ALUResult;
reg [1:0] MEM_WB_RFWriteAddress;
// control signals
reg MEM_WB_RegWrite, MEM_WB_RegSrc;
// Control signals
wire IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, PCWrite, IFIDWrite, IFIDFlush, IDEXWrite, IDEXFlush, EXMEMWrite, MEMWBWrite, ALUSrcA, RegSrc, Halt, OpenPort;
wire [1:0] RegDst, ALUSrcB;
wire [3:0] ALUOp;
// Cache access
wire i_readC, d_readC, d_writeC;
wire InstCacheBusy, DataCacheBusy;
reg [`WORD_SIZE-1:0] IR, DR; // temporary instruction register, data register
reg [`WORD_SIZE-1:0] FetchCompletePC, MemCompleteAddr; // Latches the most recent fetch address (PC or memory address)
wire [`WORD_SIZE-1:0] i_address_cache, d_address_cache;
wire [`WORD_SIZE-1:0] i_data_cache, d_data_cache;
// Hazard detection
wire BranchMisprediction, JumpMisprediction, DataHazard;
// RF
reg [`WORD_SIZE-1:0] WriteData;
wire [`WORD_SIZE-1:0] RFRead1, RFRead2;
// ALU
reg [`WORD_SIZE-1:0] ALUin1, ALUin2;
wire [`WORD_SIZE-1:0] ALUResult;
wire BranchTaken;
// Module instantiations
// Control module is located at the ID stage.
Control control (.opcode(IF_ID_Inst[15:12]),
.func(IF_ID_Inst[5:0]),
.BranchMisprediction(BranchMisprediction),
.JumpMisprediction(JumpMisprediction),
.DataHazard(DataHazard),
.InstCacheBusy(InstCacheBusy),
.DataCacheBusy(DataCacheBusy),
.PCWrite(PCWrite),
.IFIDWrite(IFIDWrite),
.IFIDFlush(IFIDFlush),
.IDEXWrite(IDEXWrite),
.IDEXFlush(IDEXFlush),
.EXMEMWrite(EXMEMWrite),
.MEMWBWrite(MEMWBWrite),
.IsBranch(IsBranch),
.IsJump(IsJump),
.JumpType(JumpType),
.DataMemRead(DataMemRead),
.DataMemWrite(DataMemWrite),
.RegWrite(RegWrite),
.RegSrc(RegSrc),
.ALUSrcA(ALUSrcA),
.Halt(Halt),
.OpenPort(OpenPort),
.RegDst(RegDst),
.ALUSrcB(ALUSrcB),
.ALUOp(ALUOp));
ICache icache(.clk(Clk),
.reset_n(Reset_N),
.i_readC(i_readC),
.i_address(i_address_cache),
.i_data(i_data_cache),
.InstCacheBusy(InstCacheBusy),
.i_readM(i_readM),
.i_address_mem(i_address),
.i_data_mem(i_data));
DCache dcache(.clk(Clk),
.reset_n(Reset_N),
.d_readC(d_readC),
.d_writeC(d_writeC),
.d_address(d_address_cache),
.d_data(d_data_cache),
.DataCacheBusy(DataCacheBusy),
.d_readM(d_readM),
.d_writeM(d_writeM),
.d_address_mem(d_address),
.d_data_mem(d_data),
.BR(BR),
.BG(BG));
// Hazard Detector module is located at the ID stage.
HazardDetector hazard_detector (.inst(IF_ID_Inst),
.ID_EX_RFWriteAddress(ID_EX_RFWriteAddress),
.EX_MEM_RFWriteAddress(EX_MEM_RFWriteAddress),
.MEM_WB_RFWriteAddress(MEM_WB_RFWriteAddress),
.ID_EX_RegWrite(ID_EX_RegWrite),
.EX_MEM_RegWrite(EX_MEM_RegWrite),
.MEM_WB_RegWrite(MEM_WB_RegWrite),
.DataHazard(DataHazard));
RF rf (.write(MEM_WB_RegWrite),
.clk(Clk),
.reset_n(Reset_N),
.addr1(IF_ID_Inst[11:10]),
.addr2(IF_ID_Inst[9:8]),
.addr3(MEM_WB_RFWriteAddress),
.data1(RFRead1),
.data2(RFRead2),
.data3(WriteData));
ALU alu (.A(ALUin1),
.B(ALUin2),
.OP(ID_EX_ALUOp),
.C(ALUResult),
.branch_cond(BranchTaken));
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// CPU reset ///////////////////////////////////////
always @(posedge Clk) begin
if (!Reset_N) begin // Synchronous active-low reset
PC <= 0;
internal_num_inst <= 0;
LastCycleFetch <= 0;
MemCompleteAddr <= `WORD_SIZE'hffff;
FetchCompletePC <= `WORD_SIZE'hffff;
cmd <= 0;
IF_ID_Inst <= `WORD_SIZE'hffff;
IF_ID_PC <= 0;
IF_ID_nextPC <= 0;
ID_EX_RFWriteAddress <= 0;
ID_EX_PC <= 0;
ID_EX_nextPC <= 0;
ID_EX_IsBranch <= 0;
ID_EX_DataMemRead <= 0;
ID_EX_DataMemWrite <= 0;
ID_EX_RegWrite <= 0;
ID_EX_Halt <= 0;
EX_MEM_RFRead2 <= 0;
EX_MEM_PC <= 0;
EX_MEM_ALUResult <= 0;
EX_MEM_RFWriteAddress <= 0;
EX_MEM_DataMemRead <= 0;
EX_MEM_DataMemWrite <= 0;
EX_MEM_RegWrite <= 0;
EX_MEM_RegSrc <= 0;
MEM_WB_MemData <= 0;
MEM_WB_RFRead2 <= 0;
MEM_WB_RFWriteAddress <= 0;
MEM_WB_RegWrite <= 0;
MEM_WB_RegSrc <= 0;
MEM_WB_ALUResult <= 0;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Pipeline register transfers ///////////////////////////////
always @(posedge Clk) begin
if (Reset_N) begin // Synchronous active-low reset
// IF/ID registers
if (IFIDWrite) begin
IF_ID_Inst <= IR;
IF_ID_PC <= PC;
IF_ID_nextPC <= nextPC;
end else if (IFIDFlush) begin
IF_ID_Inst <= `WORD_SIZE'hffff;
IF_ID_PC <= 0;
IF_ID_nextPC <= 0;
end
// ID/EX registers
if (IDEXWrite) begin
case (RegDst)
2'b00: ID_EX_RFWriteAddress <= IF_ID_Inst[9:8];
2'b01: ID_EX_RFWriteAddress <= IF_ID_Inst[7:6];
2'b10: ID_EX_RFWriteAddress <= 2'b10;
default: begin end
endcase
ID_EX_SignExtendedImm <= {{8{IF_ID_Inst[7]}}, IF_ID_Inst[7:0]};
ID_EX_RFRead1 <= RFRead1;
ID_EX_RFRead2 <= RFRead2;
ID_EX_PC <= IF_ID_PC;
ID_EX_nextPC <= IF_ID_nextPC;
ID_EX_IsBranch <= IsBranch;
ID_EX_ALUSrcA <= ALUSrcA;
ID_EX_ALUSrcB <= ALUSrcB;
ID_EX_DataMemRead <= DataMemRead;
ID_EX_DataMemWrite <= DataMemWrite;
ID_EX_RegWrite <= RegWrite;
ID_EX_RegSrc <= RegSrc;
ID_EX_RegDst <= RegDst;
ID_EX_ALUOp <= ALUOp;
ID_EX_Halt <= Halt;
end else if (IDEXFlush) begin
ID_EX_RFWriteAddress <= 0;
ID_EX_PC <= 0;
ID_EX_nextPC <= 0;
ID_EX_IsBranch <= 0;
ID_EX_DataMemRead <= 0;
ID_EX_DataMemWrite <= 0;
ID_EX_RegWrite <= 0;
ID_EX_Halt <= 0;
end
// EX/MEM registers
if (EXMEMWrite) begin
EX_MEM_RFRead2 <= ID_EX_RFRead2;
EX_MEM_PC <= ID_EX_PC;
EX_MEM_ALUResult <= ALUResult;
EX_MEM_RFWriteAddress <= ID_EX_RFWriteAddress;
EX_MEM_DataMemRead <= ID_EX_DataMemRead;
EX_MEM_DataMemWrite <= ID_EX_DataMemWrite;
EX_MEM_RegWrite <= ID_EX_RegWrite;
EX_MEM_RegSrc <= ID_EX_RegSrc;
end
// MEM/WB registers
if (MEMWBWrite) begin
MEM_WB_MemData <= DR;
MEM_WB_RFRead2 <= EX_MEM_RFRead2;
MEM_WB_RFWriteAddress <= EX_MEM_RFWriteAddress;
MEM_WB_RegWrite <= EX_MEM_RegWrite;
MEM_WB_RegSrc <= EX_MEM_RegSrc;
MEM_WB_ALUResult <= EX_MEM_ALUResult;
end else begin
MEM_WB_MemData <= 0;
MEM_WB_RFRead2 <= 0;
MEM_WB_RFWriteAddress <= 0;
MEM_WB_RegWrite <= 0;
MEM_WB_RegSrc <= 0;
MEM_WB_ALUResult <= 0;
end
end
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Outward Signals /////////////////////////////////////
// Only open output_port when control signal OpenPort is asserted,
assign output_port = OpenPort ? RFRead1 : `WORD_SIZE'bz;
// HLT should be serviced when it is guaranteed not to be flushed.
assign is_halted = ID_EX_Halt;
// num_inst counts the unique number of instructions that enter the ID stage.
assign num_inst = OpenPort ? internal_num_inst : `WORD_SIZE'bz;
always @(posedge Clk) begin
if (IFIDWrite) begin
internal_num_inst <= internal_num_inst + 1;
LastCycleFetch <= 1;
end else begin
LastCycleFetch <= 0;
end
end
always @(negedge Clk) begin
if (LastCycleFetch && BranchMisprediction) internal_num_inst <= internal_num_inst - 1;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Memory Access //////////////////////////////////////
// Instruction memory access
assign i_address_cache = PC;
assign i_readC = (!DataHazard && !BranchMisprediction && !JumpMisprediction && FetchCompletePC!=PC) || (internal_num_inst==0);
// i_data is immediately latched into RR at negedge clk.
// On the next posedge clk, the content of IR is latched into IF_ID_Inst if IF/ID write is enabled.
// This is because IF may stall due to data memory stall. If we don't save the fetched instruction, we will lose it.
always @(negedge Clk) begin
if (i_readC && !InstCacheBusy) begin
IR <= i_data_cache;
FetchCompletePC <= i_address_cache;
end
end
// Data memory access
assign d_readC = (EX_MEM_DataMemRead && MemCompleteAddr!=EX_MEM_ALUResult);
assign d_writeC = EX_MEM_DataMemWrite;
assign d_data_cache = (EX_MEM_DataMemWrite) ? EX_MEM_RFRead2 : `WORD_SIZE'bz;
assign d_address_cache = (EX_MEM_DataMemRead || EX_MEM_DataMemWrite) ? EX_MEM_ALUResult : `WORD_SIZE'bz;
// d_data is immediately latched into DR at negedge clk.
// On the next posedge clk, the content of DR is latched into MEM_WB_MemData if MEM/WB write is enabled.
always @(negedge Clk) begin
if (d_readC && !DataCacheBusy) begin
DR <= d_data_cache;
MemCompleteAddr <= d_address_cache;
end
end
// After a write, need to flush MemCompleteAddr since data at that very data may have been changed
// (which was indeed the case during Test #20)
always @(posedge d_writeC)
MemCompleteAddr <= `WORD_SIZE'hffff;
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// DMA /// ///////////////////////////////////////
always @(posedge dma_start_int) begin
cmd <= 1;
end
always @(posedge dma_end_int) begin
cmd <= 0;
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////// Updating PC ///////////////////////////////////////
// Branch mispredictions have higher priority
// since it is detected at the EX stage, whereas jump mispredictions are detected at the ID stage, hence being older.
always @(*) begin
if (ID_EX_IsBranch & BranchMisprediction) begin
if (BranchTaken) nextPC = ID_EX_PC + 1 + ID_EX_SignExtendedImm; // Branch should have been taken
else nextPC = ID_EX_PC + 1; // Branch shouldn't have been taken
end else if (IsJump & JumpMisprediction) begin
if (JumpType) nextPC = RFRead1; // JPR, JRL
else nextPC = {IF_ID_PC[15:12], IF_ID_Inst[11:0]}; // JMP, JAL
end else begin
nextPC = PC+1; // by the branch_predictor. Always PC+1 in the baseline model.
end
end
// Update PC at clock posedge
always @(posedge Clk) begin
if (Reset_N)
if (PCWrite) PC <= nextPC;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Register File //////////////////////////////////////
always @(*) begin
case (MEM_WB_RegSrc)
0: WriteData = MEM_WB_ALUResult;
1: WriteData = MEM_WB_MemData;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// ALU ///////////////////////////////////////////
always @(*) begin
case (ID_EX_ALUSrcA)
0: ALUin1 = ID_EX_RFRead1;
1: ALUin1 = ID_EX_PC;
endcase
end
always @(*) begin
case (ID_EX_ALUSrcB)
0: ALUin2 = ID_EX_RFRead2;
1: ALUin2 = ID_EX_SignExtendedImm;
2: ALUin2 = 1;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Control Hazard Detection ////////////////////////////////
assign BranchMisprediction = ID_EX_IsBranch && ((BranchTaken && ID_EX_nextPC!=ALUResult) || (!BranchTaken && ID_EX_nextPC!=ID_EX_PC+1));
assign JumpMisprediction = IsJump && ((JumpType && RFRead1!=IF_ID_nextPC) || (!JumpType && {IF_ID_PC[15:12], IF_ID_Inst[11:0]}!=IF_ID_nextPC));
///////////////////////////////////////////////////////////////////////////////////////////
endmodule |
module DMA (
input CLK, BG,
input [4 * `WORD_SIZE - 1 : 0] edata,
input cmd,
output reg BR, WR,
output reg [`WORD_SIZE - 3 : 0] addr, // block address is used
output reg [4 * `WORD_SIZE - 1 : 0] data,
output [1:0] offset,
output reg interrupt);
reg [1:0] block; // data is written to block address (0x1F4>>2 + block)
reg [2:0] counter; // counts cycles left until data write to memory completes
assign offset = BG ? block : 2'bz;
always @(posedge CLK) begin
// Received DMA request. Send out bus request.
if (cmd && !interrupt) BR <= 1;
else BR <= 0;
// Bus granted. Execute writes.
if (BG && !interrupt) begin
addr <= 14'h7d + block;
data <= edata;
if (counter == 0) begin
counter <= `LATENCY;
WR <= 1;
end else begin
counter <= counter - 1;
end
end else begin
addr <= 14'bz;
data <= 64'bz;
WR <= 1'bz;
interrupt <= 0;
block <= 0;
counter <= 0;
end
end
// Writes are done at clock negative edge.
always @(negedge CLK) begin
if (BG && !interrupt && counter==1) begin
counter <= 0;
if (block == 2) begin
block <= 0;
interrupt <= 1;
BR <= 0;
WR <= 0;
end else begin
block <= block + 1;
end
end
end
endmodule |
module ICache(
input clk,
input reset_n,
// communication with CPU
input i_readC,
input [15:0] i_address,
output [15:0] i_data,
output InstCacheBusy,
// communication with Memory
output reg i_readM,
output [13:0] i_address_mem,
input [63:0] i_data_mem
);
/*
Latency:
Read hit: 1 cycle
Read miss: 6 cycles (1 for cache search, 4 for memory read, 1 for cache search)
Read miss, during right prefetch: 2~5 cycles (cache was already prefetching the correct block)
Read miss, during wrong prefetch: 7 cycles (1 for cache search, 1 for prefetch cancel, 4 for memory read, 1 for cache search)
Output:
InstCacheBusy: asserted when the cache is fetching the requested data.
deasserted right before the cycle data is provided, so that the CPU can detect fetch finish at posedge clk.
Hence, (the number of cycles InstCacheBusy==1) + 1 is the cache's latency.
*/
reg [11:0] TagBank [3:0];
reg Valid [3:0];
reg [63:0] DataBank [3:0];
wire [11:0] tag;
wire [1:0] idx;
wire [1:0] block;
wire hit;
// internal counter that counts the memory latency
reg [2:0] InstCacheCounter;
// for prefetching
reg prefetching;
reg [2:0] PrefetchCounter;
reg [13:0] fetched_block, prefetched_block;
assign tag = i_address[15:4];
assign idx = i_address[3:2];
assign block = i_address[1:0];
assign hit = (TagBank[idx]==tag) && Valid[idx];
assign i_data = (i_readC && hit) ? DataBank[idx][16*block+:16] : 16'hz;
assign i_address_mem = prefetching ? (fetched_block + 1) : { tag, idx };
// Becomes zero when data is fetched into the cache, since hit becomes 1.
assign InstCacheBusy = i_readC && !hit;
// Cache reset
always @(posedge clk) begin
if (!reset_n) begin
{ TagBank[3], TagBank[2], TagBank[1], TagBank[0] } <= 0;
{ Valid[3], Valid[2], Valid[1], Valid[0] } <= 0;
{ DataBank[3], DataBank[2], DataBank[1], DataBank[0] } <= 0;
i_readM <= 0;
InstCacheCounter <= 0;
PrefetchCounter <= 0;
prefetching <= 0;
prefetched_block <= 0;
end
end
always @(posedge clk) begin
if (reset_n) begin
if (i_readC && !hit) begin // fetch missed PC from memory
if (prefetching) begin // cache was during prefetch!
if (i_address_mem == {tag, idx}) begin // cache was actually prefetching the correct block. continue!
if (PrefetchCounter == 1) begin
TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
Valid[(fetched_block[1:0]+1)%4] <= 1;
DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
i_readM <= 0;
fetched_block <= i_address_mem;
end else begin
InstCacheCounter <= PrefetchCounter - 1;
end
end else begin // cache was prefetching the wrong block. cancel, and restart next cycle.
i_readM <= 0;
end
PrefetchCounter <= 0;
prefetching <= 0;
// instruction is serviced from the memory when InstCacheCounter value is 1.
end else if (InstCacheCounter == 0) begin
i_readM <= 1;
InstCacheCounter <= `LATENCY;
end else if (InstCacheCounter == 1) begin
TagBank[idx] <= tag;
Valid[idx] <= 1;
DataBank[idx] <= i_data_mem;
i_readM <= 0;
fetched_block <= i_address_mem;
end else begin
InstCacheCounter <= InstCacheCounter - 1;
end
end else begin // prefetch next block undercover when there are no requests
if (prefetched_block != fetched_block + 1) begin // check if the next block was already prefetched
if (PrefetchCounter == 0) begin
prefetching <= 1; // internal cache-busy-because-of-prefetch signal. not exposed outside.
i_readM <= 1;
PrefetchCounter <= `LATENCY;
end else if (PrefetchCounter == 1) begin
TagBank[(fetched_block[1:0]+1)%4] <= i_address_mem[13:2];
Valid[(fetched_block[1:0]+1)%4] <= 1;
DataBank[(fetched_block[1:0]+1)%4] <= i_data_mem;
i_readM <= 0;
prefetched_block <= fetched_block + 1;
prefetching <= 0;
PrefetchCounter <= 0;
end else begin
PrefetchCounter <= PrefetchCounter - 1;
end
end else begin // next block was already prefetched.
i_readM <= 0;
end
InstCacheCounter <= 0;
end
end
end
// For measuring hit ratio
integer inst_hit_instructions, inst_total_instructions;
always @(posedge clk) begin
if (!reset_n) begin
inst_total_instructions <= 0;
inst_hit_instructions <= 0;
end
end
always @(negedge clk) begin
if (i_readC && hit) inst_total_instructions <= inst_total_instructions + 1;
if (i_readC && hit && InstCacheCounter==0) inst_hit_instructions <= inst_hit_instructions + 1;
end
endmodule |
module HazardDetector(
input [15:0] inst,
input [1:0] ID_EX_RFWriteAddress, EX_MEM_RFWriteAddress, MEM_WB_RFWriteAddress,
input ID_EX_RegWrite, EX_MEM_RegWrite, MEM_WB_RegWrite,
output reg DataHazard
);
/*
[Hazard Detector module]
Purpose:
Detect data hazards in the CPU, and send out the 'Stall' signal indicating whether to stall the pipeline.
Inputs:
The instruction currently in the ID stage
Register write enable and write address of EX, MEM, and WB stage.
Output:
DataHazard: asserted when data hazard is detected in ID stage
*/
always @(*) begin
// for instructions that require both rs and rt
// first if statement checks instruction type
// second if statement checks data dependency
if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_ADD || inst[5:0]==`FUNC_SUB || inst[5:0]==`FUNC_AND || inst[5:0]==`FUNC_ORR)) || inst[15:12]==`OPCODE_SWD || inst[15:12]==`OPCODE_BNE || inst[15:12]==`OPCODE_BEQ) begin
if (((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) || ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) || ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite)
|| ((ID_EX_RFWriteAddress ==inst[9:8]) && ID_EX_RegWrite) || ((EX_MEM_RFWriteAddress==inst[9:8]) && EX_MEM_RegWrite) || ((MEM_WB_RFWriteAddress==inst[9:8]) && MEM_WB_RegWrite)) begin
DataHazard = 1;
end // of if statement that checks data dependency of rs and rt
else begin
DataHazard = 0;
end
end // of if statement that checks if both rs and rt are required
// for instructions that require only rs
// first if statement checks instruction type
// second if statement checks data dependency
else if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_NOT || inst[5:0]==`FUNC_TCP || inst[5:0]==`FUNC_SHL || inst[5:0]==`FUNC_SHR || inst[5:0]==`FUNC_WWD || inst[5:0]==`FUNC_JPR || inst[5:0]==`FUNC_JRL))
|| inst[15:12]==`OPCODE_ADI || inst[15:12]==`OPCODE_ORI || inst[15:12]==`OPCODE_LWD || inst[15:12]==`OPCODE_BGZ || inst[15:12]==`OPCODE_BLZ) begin
if (((ID_EX_RFWriteAddress==inst[11:10]) && ID_EX_RegWrite) || ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) || ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite)) begin
DataHazard = 1;
end // of if statement that checks data dependency of rs
else begin
DataHazard = 0;
end
end // of if statement that checks if rs is required
else begin
DataHazard = 0;
end
end // of always @(*)
endmodule |
module AlwaysNTPredictor (
input [`WORD_SIZE-1:0] PC,
input Correct,
input [`WORD_SIZE-1:0] ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Always not-taken branch predictor module]
Purpose:
A placeholder(or framework) for future possibility of implementing a better branch predictor.
Always predicts PC+1 for any jump or branch instruction.
*/
assign Prediction = PC + 1;
endmodule |
module Control(
input [3:0] opcode,
input [5:0] func,
input BranchMisprediction, JumpMisprediction, Stall,
output reg IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, PCWrite, IFIDWrite, IFFlush, IDEXWrite, ALUSrcA, RegSrc, Halt, OpenPort,
output reg [1:0] RegDst, ALUSrcB,
output reg [3:0] ALUOp
);
/*
[CPU control module]
Inputs:
opcode and function code of the current instruction
BranchMisprediction, JumpMisprediction, and Stall are asserted when its name is detected at the CPU module.
Outputs: only those that are different from the lecture slide are explained here.
JumpType : Which type of jump destination? JumpAddress(0) or Rs(1)
RegSrc : Data being written to the RF. ALUResult(0) or MDR(1)
RegDst[2] : Adress of register to write to. Rt(00) or Rd(01) or 2(10)
ALUSrcA : First input to ALU. RFRead1(0) or PC(1)
ALUSrcB[2] : Second input to ALU. RFRead2(0) or sign-extended immediate(1) or 1(2)
IFIDWrite : Write enable bit for IF/ID pipeline register
IFFlush : Flush IF stage if enabled
IDEXWrite : Write enable bit for ID/EX pipeline register
*/
// Determine PCWrite, IFIDWrite, IFFlush, IDEXWrite separately according to state priority
always @(*) begin
if (BranchMisprediction) begin
PCWrite = 1;
IFIDWrite = 0;
IFFlush = 1;
IDEXWrite = 0;
end else if (Stall) begin
PCWrite = 0;
IFIDWrite = 0;
IFFlush = 0;
IDEXWrite = 0;
end else if (JumpMisprediction) begin
PCWrite = 1;
IFIDWrite = 0;
IFFlush = 1;
IDEXWrite = 1;
end else begin
PCWrite = 1;
IFIDWrite = 1;
IFFlush = 0;
IDEXWrite = 1;
end
end
// Determine usual control signals
always @(*) begin
JumpType = (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL));
DataMemRead = !Stall & (opcode==`OPCODE_LWD);
DataMemWrite = !Stall & (opcode==`OPCODE_SWD);
RegWrite = !Stall & ((opcode==`OPCODE_R & (func==`FUNC_ADD | func==`FUNC_SUB | func==`FUNC_AND | func==`FUNC_ORR | func==`FUNC_NOT | func==`FUNC_TCP | func==`FUNC_SHL | func==`FUNC_SHR | func==`FUNC_JRL)) | opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_JAL);
IsBranch = (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ);
IsJump = (opcode==`OPCODE_JMP | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL)));
ALUSrcA = (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL));
RegSrc = (opcode==`OPCODE_LWD);
Halt = (opcode==`OPCODE_R & func==`FUNC_HLT);
OpenPort = !BranchMisprediction & !JumpMisprediction & !Stall & (opcode==`OPCODE_R & func==`FUNC_WWD);
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUSrcB = 2;
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD) ALUSrcB = 1;
else ALUSrcB = 0;
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) RegDst = 2;
else if (opcode==`OPCODE_R) RegDst = 1;
else RegDst = 0;
end
// Determine ALU operation
always @(*) begin
if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUOp = 0;
else if (opcode==`OPCODE_ORI) ALUOp = 3;
else if (opcode==`OPCODE_LHI) ALUOp = 8;
else if (opcode==`OPCODE_BNE) ALUOp = 9;
else if (opcode==`OPCODE_BEQ) ALUOp = 10;
else if (opcode==`OPCODE_BGZ) ALUOp = 11;
else if (opcode==`OPCODE_BLZ) ALUOp = 12;
else ALUOp = 15; // undefined operation
end
endmodule |
module cpu (
input Clk,
input Reset_N,
// Instruction memory interface
output i_readM,
output reg i_writeM,
output [`WORD_SIZE-1:0] i_address,
inout [`WORD_SIZE-1:0] i_data,
// Data memory interface
output d_readM,
output d_writeM,
output [`WORD_SIZE-1:0] d_address,
inout [`WORD_SIZE-1:0] d_data,
output [`WORD_SIZE-1:0] num_inst,
output [`WORD_SIZE-1:0] output_port,
output is_halted // 1 if the cpu is halted
);
///////////////////////////// Declarations and Instantiations /////////////////////////////
// Register and wire declarations
// Testbench purposes
reg [`WORD_SIZE-1:0] internal_num_inst; // only show num_inst value for exactly one cycle in each instruction
reg [`WORD_SIZE-1:0] jump_mispredict_penalty, branch_mispredict_penalty, stall_penalty;
// Program Counter related
reg [`WORD_SIZE-1:0] PC, nextPC;
// IF/ID pipeline registers. no control signals
reg [`WORD_SIZE-1:0] IF_ID_Inst, IF_ID_PC, IF_ID_nextPC;
// ID/EX pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] ID_EX_RFRead1, ID_EX_RFRead2, ID_EX_SignExtendedImm, ID_EX_PC, ID_EX_nextPC;
reg [1:0] ID_EX_RFWriteAddress;
// control signals
reg ID_EX_IsBranch, ID_EX_ALUSrcA, ID_EX_DataMemRead, ID_EX_DataMemWrite, ID_EX_RegWrite, ID_EX_Halt, ID_EX_RegSrc;
reg [1:0] ID_EX_RegDst, ID_EX_ALUSrcB;
reg [3:0] ID_EX_ALUOp;
// EX/MEM pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] EX_MEM_RFRead2, EX_MEM_PC, EX_MEM_ALUResult;
reg [1:0] EX_MEM_RFWriteAddress;
// control signals
reg EX_MEM_DataMemRead, EX_MEM_DataMemWrite, EX_MEM_RegWrite, EX_MEM_RegSrc;
// MEM/WB pipeline registers
//non - control signals
reg [`WORD_SIZE-1:0] MEM_WB_RFRead2, MEM_WB_MemData, MEM_WB_ALUResult;
reg [1:0] MEM_WB_RFWriteAddress;
// control signals
reg MEM_WB_RegWrite, MEM_WB_RegSrc;
// Control signals
wire IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, PCWrite, IFIDWrite, IFFlush, IDEXWrite, ALUSrcA, RegSrc, Halt, OpenPort;
wire [1:0] RegDst, ALUSrcB;
wire [3:0] ALUOp;
// Data hazard detection
wire BranchMisprediction, JumpMisprediction, Stall;
wire [1:0] Forward_Rs, Forward_Rt;
// Branch Prediction
wire [`WORD_SIZE-1:0] ActualBranchTarget, Prediction;
wire Correct;
// RF
reg [`WORD_SIZE-1:0] WriteData;
wire [`WORD_SIZE-1:0] RFRead1, RFRead2;
reg [`WORD_SIZE-1:0] Forwarded_Rs, Forwarded_Rt;
// ALU
reg [`WORD_SIZE-1:0] ALUin1, ALUin2;
wire [`WORD_SIZE-1:0] ALUResult;
wire BranchTaken;
// Module instantiations
// Control module is located at the ID stage.
Control control (.opcode(IF_ID_Inst[15:12]),
.func(IF_ID_Inst[5:0]),
.BranchMisprediction(BranchMisprediction),
.JumpMisprediction(JumpMisprediction),
.Stall(Stall),
.IsBranch(IsBranch),
.IsJump(IsJump),
.JumpType(JumpType),
.DataMemRead(DataMemRead),
.DataMemWrite(DataMemWrite),
.RegWrite(RegWrite),
.PCWrite(PCWrite),
.IFIDWrite(IFIDWrite),
.IFFlush(IFFlush),
.IDEXWrite(IDEXWrite),
.RegSrc(RegSrc),
.ALUSrcA(ALUSrcA),
.Halt(Halt),
.OpenPort(OpenPort),
.RegDst(RegDst),
.ALUSrcB(ALUSrcB),
.ALUOp(ALUOp));
// Hazard Detector module is located at the ID stage.
HazardDetector hazard_detector (.inst(IF_ID_Inst),
.ID_EX_RFWriteAddress(ID_EX_RFWriteAddress),
.EX_MEM_RFWriteAddress(EX_MEM_RFWriteAddress),
.MEM_WB_RFWriteAddress(MEM_WB_RFWriteAddress),
.ID_EX_RegWrite(ID_EX_RegWrite),
.EX_MEM_RegWrite(EX_MEM_RegWrite),
.MEM_WB_RegWrite(MEM_WB_RegWrite),
.ID_EX_IsLWD(ID_EX_DataMemRead),
.Stall(Stall),
.Forward_Rs(Forward_Rs),
.Forward_Rt(Forward_Rt));
// Branch Predictor module is located at the IF stage.
AlwaysNTPredictor branch_predictor (.PC(PC),
.Correct(Correct),
.ActualBranchTarget(ActualBranchTarget),
.Prediction(Prediction));
RF rf (.write(MEM_WB_RegWrite),
.clk(Clk),
.reset_n(Reset_N),
.addr1(IF_ID_Inst[11:10]),
.addr2(IF_ID_Inst[9:8]),
.addr3(MEM_WB_RFWriteAddress),
.data1(RFRead1),
.data2(RFRead2),
.data3(WriteData));
ALU alu (.A(ALUin1),
.B(ALUin2),
.OP(ID_EX_ALUOp),
.C(ALUResult),
.branch_cond(BranchTaken));
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// CPU reset ///////////////////////////////////////
always @(posedge Clk) begin
if (!Reset_N) begin // Synchronous active-low reset
PC <= 0;
internal_num_inst <= 0;
jump_mispredict_penalty <= 0;
branch_mispredict_penalty <= 0;
stall_penalty <= 0;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Pipeline register transfers ///////////////////////////////
always @(posedge Clk) begin
if (Reset_N) begin // Synchronous active-low reset
// IF/ID registers
if (IFIDWrite | internal_num_inst==0) begin
IF_ID_PC <= PC;
IF_ID_nextPC <= nextPC;
end else if (IFFlush) begin
IF_ID_Inst <= `WORD_SIZE'hffff;
IF_ID_PC <= 0;
IF_ID_nextPC <= 0;
end
// ID/EX registers
if (IDEXWrite) begin
case (RegDst)
2'b00: ID_EX_RFWriteAddress <= IF_ID_Inst[9:8];
2'b01: ID_EX_RFWriteAddress <= IF_ID_Inst[7:6];
2'b10: ID_EX_RFWriteAddress <= 2'b10;
default: begin end
endcase
ID_EX_SignExtendedImm <= {{8{IF_ID_Inst[7]}}, IF_ID_Inst[7:0]};
ID_EX_RFRead1 <= Forwarded_Rs;
ID_EX_RFRead2 <= Forwarded_Rt;
ID_EX_PC <= IF_ID_PC;
ID_EX_nextPC <= IF_ID_nextPC;
ID_EX_IsBranch <= IsBranch;
ID_EX_ALUSrcA <= ALUSrcA;
ID_EX_ALUSrcB <= ALUSrcB;
ID_EX_DataMemRead <= DataMemRead;
ID_EX_DataMemWrite <= DataMemWrite;
ID_EX_RegWrite <= RegWrite;
ID_EX_RegSrc <= RegSrc;
ID_EX_RegDst <= RegDst;
ID_EX_ALUOp <= ALUOp;
ID_EX_Halt <= Halt;
end else begin
ID_EX_RFWriteAddress <= 0;
ID_EX_PC <= 0;
ID_EX_nextPC <= 0;
ID_EX_IsBranch <= 0;
ID_EX_DataMemRead <= 0;
ID_EX_DataMemWrite <= 0;
ID_EX_RegWrite <= 0;
ID_EX_Halt <= 0;
end
// EX/MEM registers
EX_MEM_RFRead2 <= ID_EX_RFRead2;
EX_MEM_PC <= ID_EX_PC;
EX_MEM_ALUResult <= ALUResult;
EX_MEM_RFWriteAddress <= ID_EX_RFWriteAddress;
EX_MEM_DataMemRead <= ID_EX_DataMemRead;
EX_MEM_DataMemWrite <= ID_EX_DataMemWrite;
EX_MEM_RegWrite <= ID_EX_RegWrite;
EX_MEM_RegSrc <= ID_EX_RegSrc;
// MEM/WB registers
MEM_WB_RFRead2 <= EX_MEM_RFRead2;
MEM_WB_RFWriteAddress <= EX_MEM_RFWriteAddress;
MEM_WB_RegWrite <= EX_MEM_RegWrite;
MEM_WB_RegSrc <= EX_MEM_RegSrc;
MEM_WB_ALUResult <= EX_MEM_ALUResult;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Outward Signals /////////////////////////////////////
// Only open output_port when control signal OpenPort is asserted,
assign output_port = OpenPort ? Forwarded_Rs : `WORD_SIZE'bz;
// HLT should be serviced when it is guaranteed not to be flushed.
assign is_halted = ID_EX_Halt;
/*
num_inst is output when OpenPort is asserted, which means the current instruction is WWD.
internal_num_inst : assumes CPI = 1. increments every cycle
branch_mispredict_penalty: 2 cycle penalty
jump_mispredict_penalty : 1 cycle penalty
stall_penalty : As long as the stall
Thus internal_num_inst - branch_mispredict_penalty - stall_penalty - jump_mispredict_penalty is the number of instructions processed (including the current one)
*/
assign num_inst = OpenPort ? (internal_num_inst - branch_mispredict_penalty - stall_penalty - jump_mispredict_penalty) : `WORD_SIZE'b0;
always @(posedge Clk) begin
if (Reset_N) internal_num_inst <= internal_num_inst + 1;
end
always @(negedge Clk) begin // Used negedge because of glitches in the signals at transition yielded random increments
if (BranchMisprediction) branch_mispredict_penalty <= branch_mispredict_penalty + 2;
else if (Stall) stall_penalty <= stall_penalty + 1;
else if (JumpMisprediction) jump_mispredict_penalty <= jump_mispredict_penalty + 1;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Memory Access //////////////////////////////////////
// Fetch instruction every cycle
assign i_address = (IFIDWrite | internal_num_inst==0) ? PC : `WORD_SIZE'bz;
assign i_readM = (IFIDWrite | internal_num_inst==0) ? 1 : 0;
// When the IF stage needs to be flushed, discard the fetched instruction.
// Else, fetch instruction directly into the pipeline register.
always @(posedge Clk) begin
if (IFFlush) IF_ID_Inst <= `WORD_SIZE'hffff;
// No control signals during the IF stage of the first instruction. Manually enable IF/ID pipeline register write,
else if (IFIDWrite | internal_num_inst==0) IF_ID_Inst <= i_data;
end
// Data memory access
assign d_data = (EX_MEM_DataMemWrite) ? EX_MEM_RFRead2 : `WORD_SIZE'bz;
assign d_readM = EX_MEM_DataMemRead;
assign d_writeM = EX_MEM_DataMemWrite;
assign d_address = (EX_MEM_DataMemRead || EX_MEM_DataMemWrite) ? EX_MEM_ALUResult : `WORD_SIZE'bz;
// Fetch data directly into the pipeline register.
always @(posedge Clk) begin
if (EX_MEM_DataMemRead) MEM_WB_MemData <= d_data;
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////// Updating PC ///////////////////////////////////////
// Branch mispredictions have higher priority
// since it is detected at the EX stage, whereas jump mispredictions are detected at the ID stage, hence being older.
always @(*) begin
if (ID_EX_IsBranch & BranchMisprediction) begin
if (BranchTaken) nextPC = ID_EX_PC + 1 + ID_EX_SignExtendedImm; // Branch should have been taken
else nextPC = ID_EX_PC + 1; // Branch shouldn't have been taken
end else if (IsJump & JumpMisprediction) begin
if (JumpType) nextPC = Forwarded_Rs; // JPR, JRL
else nextPC = {IF_ID_PC[15:12], IF_ID_Inst[11:0]}; // JMP, JAL
end else begin
nextPC = Prediction; // by the branch_predictor. Always PC+1 in the baseline model.
end
end
// Update PC at clock posedge
always @(posedge Clk) begin
if (Reset_N)
// No control signals before the ID stage of the first instruction. Manually enable PCwrite,
if (PCWrite | internal_num_inst==0) PC <= nextPC;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Register File //////////////////////////////////////
always @(*) begin
case (Forward_Rs)
2'b00: Forwarded_Rs = RFRead1; // no forwarding
2'b01: Forwarded_Rs = ALUResult; // from EX
2'b10: Forwarded_Rs = EX_MEM_DataMemRead ? d_data : EX_MEM_ALUResult; // from MEM
2'b11: Forwarded_Rs = WriteData; // from WB
endcase
case (Forward_Rt)
2'b00: Forwarded_Rt = RFRead2; // no forwarding
2'b01: Forwarded_Rt = ALUResult; // from EX
2'b10: Forwarded_Rt = EX_MEM_DataMemRead ? d_data : EX_MEM_ALUResult; // from MEM
2'b11: Forwarded_Rt = WriteData; // from WB
endcase
end
always @(*) begin
case (MEM_WB_RegSrc)
0: WriteData = MEM_WB_ALUResult;
1: WriteData = MEM_WB_MemData;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// ALU ///////////////////////////////////////////
always @(*) begin
case (ID_EX_ALUSrcA)
0: ALUin1 = ID_EX_RFRead1;
1: ALUin1 = ID_EX_PC;
endcase
end
always @(*) begin
case (ID_EX_ALUSrcB)
0: ALUin2 = ID_EX_RFRead2;
1: ALUin2 = ID_EX_SignExtendedImm;
2: ALUin2 = 1;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Control Hazard Detection ////////////////////////////////
assign BranchMisprediction = ID_EX_IsBranch && ((BranchTaken && ID_EX_nextPC!=ALUResult) || (!BranchTaken && ID_EX_nextPC!=ID_EX_PC+1));
assign JumpMisprediction = IsJump && ((JumpType && Forwarded_Rs!=IF_ID_nextPC) || (!JumpType && {IF_ID_PC[15:12], IF_ID_Inst[11:0]}!=IF_ID_nextPC));
///////////////////////////////////////////////////////////////////////////////////////////
endmodule |
module HazardDetector(
input [15:0] inst,
input [1:0] ID_EX_RFWriteAddress, EX_MEM_RFWriteAddress, MEM_WB_RFWriteAddress,
input ID_EX_RegWrite, EX_MEM_RegWrite, MEM_WB_RegWrite,
input ID_EX_IsLWD,
output reg Stall,
output reg [1:0] Forward_Rs, Forward_Rt
);
/*
[Hazard Detector module]
Purpose:
Detects data hazards in the CPU, and indicates whether the CPU should stall the pipeline or forward data.
Inputs:
The instruction currently in the ID stage
Register write enable and write address of EX, MEM, and WB stage.
Whether the instruction in the EX stage is LWD
Output:
Stall: stall pipeline(1) or proceed without stalling(0)
Forward_Rx: no forwarding(00), from EX(01), from MEM(10), from WB(11)
*/
always @(*) begin
// for instructions that require both rs and rt
if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_ADD || inst[5:0]==`FUNC_SUB || inst[5:0]==`FUNC_AND || inst[5:0]==`FUNC_ORR)) || inst[15:12]==`OPCODE_SWD || inst[15:12]==`OPCODE_BNE || inst[15:12]==`OPCODE_BEQ) begin
// Check if Rs can be forwarded
if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin // instruction in EX writes to Rs
if (ID_EX_IsLWD) begin // LWD produces data in MEM stage. Data in EX stage shouldn't be forwarded.
Stall = 1;
Forward_Rs = 0;
end else begin
Stall = 0;
Forward_Rs = 1;
end
end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin // instruction in MEM writes to Rs
Stall = 0;
Forward_Rs = 2;
end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin // instruction in WB writes to Rs
Stall = 0;
Forward_Rs = 3;
end else begin
Stall = 0;
Forward_Rs = 0;
end // of Rs forward check
// Check if Rt can be forwarded
if ((ID_EX_RFWriteAddress ==inst[9:8]) && ID_EX_RegWrite) begin // instruction in EX writes to Rt
if (ID_EX_IsLWD) begin // LWD produces data in MEM stage. Data in EX stage shouldn't be forwarded.
Stall = 1;
Forward_Rt = 0;
end else begin
Stall = 0;
Forward_Rt = 1;
end
end else if ((EX_MEM_RFWriteAddress==inst[9:8]) && EX_MEM_RegWrite) begin // instruction in MEM writes to Rt
Stall = 0;
Forward_Rt = 2;
end else if ((MEM_WB_RFWriteAddress==inst[9:8]) && MEM_WB_RegWrite) begin // instruction in WB writes to Rt
Stall = 0;
Forward_Rt = 3;
end else begin
Stall = 0;
Forward_Rt = 0;
end // of Rt forward check
end // of if statement for instructions that require both rs and rt
// for instructions that require only rs\
else if ((inst[15:12]==`OPCODE_R && (inst[5:0]==`FUNC_NOT || inst[5:0]==`FUNC_TCP || inst[5:0]==`FUNC_SHL || inst[5:0]==`FUNC_SHR || inst[5:0]==`FUNC_WWD || inst[5:0]==`FUNC_JPR || inst[5:0]==`FUNC_JRL))
|| inst[15:12]==`OPCODE_ADI || inst[15:12]==`OPCODE_ORI || inst[15:12]==`OPCODE_LWD || inst[15:12]==`OPCODE_BGZ || inst[15:12]==`OPCODE_BLZ) begin
// Check if Rs can be forwarded
if ((ID_EX_RFWriteAddress ==inst[11:10]) && ID_EX_RegWrite) begin // instruction in EX writes to Rs
if (ID_EX_IsLWD) begin // LWD produces data in MEM stage. Data in EX stage shouldn't be forwarded.
Stall = 1;
Forward_Rs = 0;
end else begin
Stall = 0;
Forward_Rs = 1;
end
end else if ((EX_MEM_RFWriteAddress==inst[11:10]) && EX_MEM_RegWrite) begin // instruction in MEM writes to Rs
Stall = 0;
Forward_Rs = 2;
end else if ((MEM_WB_RFWriteAddress==inst[11:10]) && MEM_WB_RegWrite) begin // instruction in WB writes to Rs
Stall = 0;
Forward_Rs = 3;
end else begin
Stall = 0;
Forward_Rs = 0;
end // of Rs forward check
end // of if statement for instructions that require only rs
// No dependency, no stall, and no forwarding
else begin
Stall = 0;
Forward_Rs = 0;
Forward_Rt = 0;
end
end // of always @(*)
endmodule |
module TournamentPredictor (
input clk,
input reset_n,
input IsControl,
input [`WORD_SIZE-1:0] PC,
input JumpResolved, BranchResolved, BranchTaken,
input [`WORD_SIZE-1:0] ResolvedJumpPC, ResolvedBranchPC,
input [`WORD_SIZE-1:0] ActualJumpTarget, ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Tournament branch predictor module]
Functionality:
8 bit tag
8 bit BTB index
PC[7:0] -> 256 x 8 Local History Table -> 256 x 2 Local Predictor (saturation counter)
12 bit Global History Shift Register: Caches the prediction/outcome results of ten most recent branch/jump instructions
GHSR[9:0] -> 1024 x 2 Global Predictor (saturation counter)
GHSR[9:0] -> 1024 x 2 Choice Predictor (saturation counter)
Inputs:
IsControl : Whether the currnet instruction is a jump or branch instruction. (Predecode)
PC : Address of the current instruction. We should predict its outcome.
BranchTaken : Whether the resolved branch was taken
ResolvedJumpPC : address of the jump instruction resolved this cycle (ID stage)
ResolvedBranchPC : address of the branch instruction resolved this cycle (EX stage)
ActualJumpTarget : The actual destination of the jump instruction resolved this cycle.
ActualBranchTarget: The actual destination of the branch instruction resolved this cycle.
Outputs:
Prediction : Predicted nextPC of the current instruction.
*/
// For initialization for loop
integer i, j;
// BTB and Tag Table
reg [`WORD_SIZE-1:0] BTB [255:0];
reg [7:0] TagTable [255:0];
// SAg Local Predictor
reg [7:0] LHT [255:0];
reg [1:0] LP [255:0];
// Global History Shift Register
reg [11:0] GHSR;
// GAg Global Predictor
reg [1:0] GP [1023:0];
// GAg Choice Predictor
reg [1:0] CP [1023:0];
// Asserted when predict taken
wire GlobalPredictTaken, LocalPredictTaken, ChosenPredictTaken, PredictTaken;
// Internal book keeping. Used to update the predictor when the actual outcome of control instructions are determined.
reg [1:0] LocalPredictionHistory, ChoicePredictionHistory;
always @(posedge clk) begin
if (!reset_n) begin // Synchronous active-low reset
for (i=0; i<256; i=i+1) begin
BTB[i] <= 0;
TagTable[i] <= 8'hff;
LHT[i] <= 0;
LP[i] <= 1; // 2 bit saturations counters are initialized to 1, i.e. not taken.
end
for (j=0; j<1024; j=j+1) begin
GP[j] <= 1;
CP[j] <= 1;
end
GHSR <= 0;
LocalPredictionHistory <= 0;
ChoicePredictionHistory <= 0;
end else begin
if (IsControl) GHSR <= {GHSR[10:0], PredictTaken};
LocalPredictionHistory <= {LocalPredictionHistory[0], LocalPredictTaken};
ChoicePredictionHistory <= {ChoicePredictionHistory[0], ChosenPredictTaken};
end
end
// Branch prediction logic
assign GlobalPredictTaken = (GP[GHSR[9:0]] >= 2);
assign LocalPredictTaken = (LP[LHT[PC[7:0]]] >= 2);
assign ChosenPredictTaken = (CP[GHSR[9:0]] >= 2 ? GlobalPredictTaken : LocalPredictTaken);
assign PredictTaken = (TagTable[PC[7:0]] == PC[15:8]) && ChosenPredictTaken;
assign Prediction = PredictTaken ? BTB[PC[7:0]] : PC+1;
// Updating predictor based on the actual outcome of control instructions
always @(negedge clk) begin
if (BranchResolved && JumpResolved) begin // GHSR[1] = Branch Prediction, GHSR[0] = Jump Prediction
if (BranchTaken) begin // Branch taken
// Update local predictor counter
if (LP[LHT[ResolvedBranchPC[7:0]]] != 3) begin
LP[LHT[ResolvedBranchPC[7:0]]] <= LP[LHT[ResolvedBranchPC[7:0]]] + 1;
end
// Update global predictor counter
if (GP[GHSR[11:2]] != 3) begin
GP[GHSR[11:2]] <= GP[GHSR[11:2]] + 1;
end
end else begin // Branch not taken
// Update local predictor counter
if (LP[LHT[ResolvedBranchPC[7:0]]] != 0) begin
LP[LHT[ResolvedBranchPC[7:0]]] <= LP[LHT[ResolvedBranchPC[7:0]]] - 1;
end
// Update global predictor counter
if (GP[GHSR[11:2]] != 0) begin
GP[GHSR[11:2]] <= GP[GHSR[11:2]] - 1;
end
end
// Update choice predictor counter
if (ChoicePredictionHistory[1] == GHSR[1]) begin // Global predictor was chosen
if (GHSR[1] != BranchTaken && LocalPredictionHistory[1] == BranchTaken) begin // Global was wrong, local was right
if (CP[GHSR[11:2]] != 0) CP[GHSR[11:2]] <= CP[GHSR[11:2]] - 1; // Decrement choice predictor counter
end
end else if (ChoicePredictionHistory[1] == LocalPredictionHistory[1]) begin // Local predictor was chosen
if (LocalPredictionHistory[1] != BranchTaken && GHSR[1] == BranchTaken) begin // Local was wrong, global was right
if (CP[GHSR[11:2]] != 3) CP[GHSR[11:2]] <= CP[GHSR[11:2]] + 1; // Increment choice predictor counter
end
end
// Update local history table
LHT[ResolvedBranchPC[7:0]] <= { LHT[ResolvedBranchPC[7:0]][6:0], BranchTaken};
// Update Tag Table and BTB
TagTable[ResolvedBranchPC[7:0]] <= ResolvedBranchPC[15:8];
BTB[ResolvedBranchPC[7:0]] <= ActualBranchTarget;
// Update Global History Shift Register
GHSR[1] <= BranchTaken;
if (BranchTaken == GHSR[1]) begin // Update predictors with jump resolution information only if branch prediction was right,
// Update local predictor counter
if (LP[LHT[ResolvedJumpPC[7:0]]] != 3) begin
LP[LHT[ResolvedJumpPC[7:0]]] <= LP[LHT[ResolvedJumpPC[7:0]]] + 1;
end
// Update global predictor counter
if (GP[GHSR[10:1]] != 3) begin
GP[GHSR[10:1]] <= GP[GHSR[10:1]] + 1;
end
// Update choice predictor counter
if (CP[GHSR[10:1]] != 3) begin
CP[GHSR[10:1]] <= CP[GHSR[10:1]] + 1;
end
// Update choice predictor counter
if (ChoicePredictionHistory[0] == GHSR[0]) begin // Global predictor was chosen
if (GHSR[0] != BranchTaken && LocalPredictionHistory[0] == BranchTaken) begin // Global was wrong, local was right
if (CP[GHSR[10:1]] != 0) CP[GHSR[10:1]] <= CP[GHSR[10:1]] - 1; // Decrement choice predictor counter
end
end else if (ChoicePredictionHistory[0] == LocalPredictionHistory[0]) begin // Local predictor was chosen
if (LocalPredictionHistory[0] != BranchTaken && GHSR[0] == BranchTaken) begin // Local was wrong, global was right
if (CP[GHSR[10:1]] != 3) CP[GHSR[10:1]] <= CP[GHSR[10:1]] + 1; // Increment choice predictor counter
end
end
// Update local history table
LHT[ResolvedJumpPC[7:0]] <= { LHT[ResolvedJumpPC[7:0]][6:0], 1'b1};
// Update Tag Table and BTB
TagTable[ResolvedJumpPC[7:0]] <= ResolvedJumpPC[15:8];
BTB[ResolvedJumpPC[7:0]] <= ActualJumpTarget;
// Update Global History Shift Register
GHSR[0] <= 1'b1;
end // of if (Branch prediction was right)
end // of if (BranchResolved && JumpResolved)
else if (BranchResolved && !JumpResolved) begin // This branch was the most recently predicted control instruction. Thus GHSR[0] = Branch Prediction.
if (BranchTaken) begin // Branch taken
// Update local predictor counter
if (LP[LHT[ResolvedBranchPC[7:0]]] != 3) begin
LP[LHT[ResolvedBranchPC[7:0]]] <= LP[LHT[ResolvedBranchPC[7:0]]] + 1;
end
// Update global predictor counter
if (GP[GHSR[10:1]] != 3) begin
GP[GHSR[10:1]] <= GP[GHSR[10:1]] + 1;
end
end else begin // Branch not taken
// Update local predictor counter
if (LP[LHT[ResolvedBranchPC[7:0]]] != 0) begin
LP[LHT[ResolvedBranchPC[7:0]]] <= LP[LHT[ResolvedBranchPC[7:0]]] - 1;
end
// Update global predictor counter
if (GP[GHSR[10:1]] != 0) begin
GP[GHSR[10:1]] <= GP[GHSR[10:1]] - 1;
end
end
// Update choice predictor counter
if (ChoicePredictionHistory[1] == GHSR[1]) begin // Global predictor was chosen
if (GHSR[1] != BranchTaken && LocalPredictionHistory[1] == BranchTaken) begin // Global was wrong, local was right
if (CP[GHSR[11:2]] != 0) CP[GHSR[11:2]] <= CP[GHSR[11:2]] - 1; // Decrement choice predictor counter
end
end else if (ChoicePredictionHistory[1] == LocalPredictionHistory[1]) begin // Local predictor was chosen
if (LocalPredictionHistory[1] != BranchTaken && GHSR[1] == BranchTaken) begin // Local was wrong, global was right
if (CP[GHSR[11:2]] != 3) CP[GHSR[11:2]] <= CP[GHSR[11:2]] + 1; // Increment choice predictor counter
end
end
// Update local history table
LHT[ResolvedBranchPC[7:0]] <= { LHT[ResolvedBranchPC[7:0]][6:0], BranchTaken};
// Update Tag Table and BTB
TagTable[ResolvedBranchPC[7:0]] <= ResolvedBranchPC[15:8];
BTB[ResolvedBranchPC[7:0]] <= ActualBranchTarget;
// Update Global History Shift Register
GHSR[1] <= BranchTaken;
end // of if (BranchResolved)
else if (JumpResolved && !BranchResolved) begin // This jump was the most recently predicted control instruction. Thus GHSR[0] = Jump Prediction.
// Update local predictor counter
if (LP[LHT[ResolvedJumpPC[7:0]]] != 3) begin
LP[LHT[ResolvedJumpPC[7:0]]] <= LP[LHT[ResolvedJumpPC[7:0]]] + 1;
end
// Update global predictor counter
if (GP[GHSR[10:1]] != 3) begin
GP[GHSR[10:1]] <= GP[GHSR[10:1]] + 1;
end
// Update choice predictor counter
if (CP[GHSR[10:1]] != 3) begin
CP[GHSR[10:1]] <= CP[GHSR[10:1]] + 1;
end
// Update choice predictor counter
if (ChoicePredictionHistory[0] == GHSR[0]) begin // Global predictor was chosen
if (GHSR[0] != BranchTaken && LocalPredictionHistory[0] == BranchTaken) begin // Global was wrong, local was right
if (CP[GHSR[10:1]] != 0) CP[GHSR[10:1]] <= CP[GHSR[10:1]] - 1; // Decrement choice predictor counter
end
end else if (ChoicePredictionHistory[0] == LocalPredictionHistory[0]) begin // Local predictor was chosen
if (LocalPredictionHistory[0] != BranchTaken && GHSR[0] == BranchTaken) begin // Local was wrong, global was right
if (CP[GHSR[10:1]] != 3) CP[GHSR[10:1]] <= CP[GHSR[10:1]] + 1; // Increment choice predictor counter
end
end
// Update local history table
LHT[ResolvedJumpPC[7:0]] <= { LHT[ResolvedJumpPC[7:0]][6:0], 1'b1};
// Update Tag Table and BTB
TagTable[ResolvedJumpPC[7:0]] <= ResolvedJumpPC[15:8];
BTB[ResolvedJumpPC[7:0]] <= ActualJumpTarget;
// Update Global History Shift Register
GHSR[0] <= 1'b1;
end // of if (JumpResolved)
end
endmodule |
module TwoBitSaturationPredictor (
input clk,
input reset_n,
input [`WORD_SIZE-1:0] PC,
input JumpResolved, BranchResolved, BranchTaken,
input [`WORD_SIZE-1:0] ResolvedJumpPC, ResolvedBranchPC,
input [`WORD_SIZE-1:0] ActualJumpTarget, ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Two Bit Saturation branch predictor module]
Functionality:
8 bit tag
8 bit BTB index
2 bit BHT saturation counter
Only branch and jump instructions are stored in the BTB.
Inputs:
PC : Address of the current instruction. We should predict its outcome.
BranchTaken : Whether the resolved branch was taken
ResolvedJumpPC : address of the jump instruction resolved this cycle (ID stage)
ResolvedBranchPC : address of the branch instruction resolved this cycle (EX stage)
ActualJumpTarget : The actual destination of the jump instruction resolved this cycle.
ActualBranchTarget: The actual destination of the branch instruction resolved this cycle.
Outputs:
Prediction : Predicted nextPC of the current instruction.
*/
integer i;
reg [`WORD_SIZE-1:0] BTB [`BTB_SIZE-1:0];
reg [7:0] TagTable [`BTB_SIZE-1:0];
reg [1:0] Counter [`BTB_SIZE-1:0];
wire PredictTaken;
// Store the last two prediction history
reg [1:0] PredictionHistory;
always @(posedge clk) begin
if (!reset_n) begin // Synchronous active-low reset
for (i=0; i<`BTB_SIZE; i=i+1) begin
BTB[i] <= 0;
TagTable[i] <= 8'hff;
Counter[i] <= 1;
end
PredictionHistory <= 2'b00;
end else begin // Prediction history shift register
PredictionHistory <= { PredictionHistory[1], PredictTaken };
end
end
// Branch prediction logic
assign PredictTaken = (TagTable[PC[`IDX_SIZE-1:0]] == PC[`WORD_SIZE-1:`IDX_SIZE]) && (Counter[PC[`IDX_SIZE-1:0]] >= 2);
assign Prediction = PredictTaken ? BTB[PC[`IDX_SIZE-1:0]] : PC+1;
// Updating predictor based on the actual outcome of control instructions
always @(negedge clk) begin
if (BranchResolved) begin // In EX stage
if (BranchTaken) begin // Branch taken
if (Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] != 3) begin
Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] <= Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] + 1;
end
end else begin // Branch not taken
if (Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] != 0) begin
Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] <= Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] - 1;
end
end
TagTable[ResolvedBranchPC[`IDX_SIZE-1:0]] <= ResolvedBranchPC[`WORD_SIZE-1:`IDX_SIZE];
BTB[ResolvedBranchPC[`IDX_SIZE-1:0]] <= ActualBranchTarget;
end
if (JumpResolved) begin
// If there was a branch resolution in the EX stage, its prediction should have been correct to ensure the execution of the jump in the ID stage.
// Or else, no branch resolution in the EX stage.
if ((BranchResolved && (BranchTaken == PredictionHistory[1])) || !BranchResolved) begin
if (Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] != 3) begin
Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] <= Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] + 1;
end
TagTable[ResolvedJumpPC[`IDX_SIZE-1:0]] <= ResolvedJumpPC[`WORD_SIZE-1:`IDX_SIZE];
BTB[ResolvedJumpPC[`IDX_SIZE-1:0]] <= ActualJumpTarget;
end
end
end
endmodule |
module DMA (
input CLK, BG,
input [4 * `WORD_SIZE - 1 : 0] edata,
input cmd,
output reg BR, WR,
output reg [`WORD_SIZE - 3 : 0] addr, // block address is used
output reg [4 * `WORD_SIZE - 1 : 0] data,
output [1:0] offset,
output reg interrupt);
reg cycle_stolen; // DMA not done yet, but cycle stolen by CPU.
reg [1:0] block; // data is written to block address (0x1F4>>2 + block)
reg [2:0] counter; // counts cycles left until data write to memory completes
assign offset = BG ? block : 2'bz;
always @(posedge CLK) begin
// Received DMA request. Send out bus request.
if (cmd && !interrupt) BR <= 1;
else BR <= 0;
// Bus granted. Execute writes.
if (BG && !interrupt) begin
addr <= 14'h7d + block;
data <= edata;
if (counter == 0) begin
counter <= `LATENCY;
WR <= 1;
end else begin
counter <= counter - 1;
end
end else begin
addr <= 14'bz;
data <= 64'bz;
WR <= 1'bz;
interrupt <= 0;
counter <= 0;
// While DMA cycle is stolen, do not reset block number.
if (cycle_stolen==0 || cycle_stolen===1'bx) begin
block <= 0;
end
end
end
// Writes are done at clock negative edge.
always @(negedge CLK) begin
if (BG && !interrupt && counter==1) begin
counter <= 0;
BR <= 0;
WR <= 0;
if (block == 2) begin
cycle_stolen <= 0;
block <= 0;
interrupt <= 1;
end else begin
cycle_stolen <= 1;
block <= block + 1;
end
end
end
endmodule |
module RF(
input write,
input clk,
input reset_n,
input [1:0] addr1,
input [1:0] addr2,
input [1:0] addr3,
output [15:0] data1,
output [15:0] data2,
input [15:0] data3
);
reg [63:0] register;
/*
register[63:48] == register[16*3+: 16] (addr is 2'b11)
register[47:32] == register[16*2+: 16] (addr is 2'b10)
register[31:16] == register[16*1+: 16] (addr is 2'b01)
register[15: 0] == register[16*0+: 16] (addr is 2'b00)
*/
always @(posedge clk, negedge reset_n) begin
// Asynchronous active low reset -> This used to be Synchronous reset; modified to asynchronous for Project 4.
if (!reset_n) register <= 64'b0;
// Synchronous data write
else if (write) register[16*addr3+: 16] <= data3;
end
// Asynchronous data read
assign data1 = register[16*addr1+: 16];
assign data2 = register[16*addr2+: 16];
endmodule |
module cpu (
output reg readM, // read from memory
output reg [`WORD_SIZE-1:0] address, // current address for data
inout [`WORD_SIZE-1:0] data, // data being input or output
input inputReady, // indicates that data is ready from the input port
input reset_n, // active-low RESET signal
input clk, // clock signal
// for debuging/testing purpose
output reg [`WORD_SIZE-1:0] num_inst, // number of instruction during execution
output [`WORD_SIZE-1:0] output_port // this will be used for a "WWD" instruction
);
// General CPU declarations
reg reading_instruction; // Whether the current data access is for instruction or memory
reg [`WORD_SIZE-1:0] PC, nextPC; // Update PC to nextPC at every posedge clk
reg [`WORD_SIZE-1:0] instruction, dataReg; // Because data is only available for a short time, we need to save it.
// Control signals from control module
wire RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, OpenPort;
wire [3:0] ALUOp;
// RF related declarations
wire [`WORD_SIZE-1:0] ReadData1, ReadData2;
// ALU related declarations
wire bcond;
wire [`WORD_SIZE-1:0] ALUResult;
// Actual modul declarations
Control control(.opcode(instruction[15:12]),
.func(instruction[5:0]),
.RegDst(RegDst),
.Jump(Jump),
.Branch(Branch),
.MemRead(MemRead),
.MemtoReg(MemtoReg),
.ALUOp(ALUOp),
.MemWrite(MemWrite),
.ALUSrc(ALUSrc),
.RegWrite(RegWrite),
.OpenPort(OpenPort));
RF rf(.write(RegWrite),
.clk(clk),
.reset_n(reset_n),
.addr1(instruction[11:10]),
.addr2(instruction[9:8]),
.addr3(RegDst ? instruction[7:6] : instruction[9:8]), // Write address either rt or rd
.data1(ReadData1),
.data2(ReadData2),
.data3(MemtoReg ? dataReg : ALUResult));
ALU alu(.A(ReadData1),
.B(ALUSrc ? {{8{instruction[7]}}, instruction[7:0]} : ReadData2), // Either sign-extended immediate or second register read from RF.
.OP(ALUOp),
.C(ALUResult),
.bcond(bcond));
always @(*) begin
if (Jump) nextPC = {PC[15:12], instruction[11:0]}; // Jumping to target (12 bit), concatenated with the upper 4 bits of PC.
else if (Branch & bcond) nextPC = PC + {{8{instruction[7]}}, instruction[7:0]}; // Branching to PC + sign-extend(immediate)
else nextPC = PC + 1; // Next instruction
end
// Only open when OpenPort is asserted by the control module
assign output_port = OpenPort ? ReadData1 : `WORD_SIZE'bz;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin // Asynchronous active low reset
PC <= 0;
nextPC <= 0;
num_inst <= 1;
end else begin
PC <= nextPC;
num_inst <= num_inst + 1;
end
end
// When PC updates, assert readM for instruction fetch
always @(PC) begin
address = PC;
readM = 1;
reading_instruction = 1;
end
// When inputReady changes from 0 to 1
always @(posedge inputReady) begin
if (reading_instruction) begin // instruction fetch mode
instruction <= data;
readM <= 0;
reading_instruction <= 0; // deassert since instruction fetch is done
end else begin // data fetch mode
dataReg <= data;
readM <= 0;
end
end
endmodule |
module Control(
input [3:0] opcode,
input [5:0] func,
output RegDst,
output Jump,
output Branch,
output MemRead,
output MemtoReg,
output reg [3:0] ALUOp,
output MemWrite,
output ALUSrc,
output RegWrite,
output OpenPort
);
/*
Receives opcode and function code of an instruction, and generates control signals.
RegDst : Chooses RF write address (rt or rd)
Jump : Whether this instruction is a jump
Branch : Whether this instruction is a branch
MemRead : Whether we should read data memory
MemtoReg: Chooses what to write to RF (ALU result or data read from memory)
ALUOp : Controls ALU operation. Directly connected to the input OP of the ALU. (There is no ALU control module in this CPU)
MemWrite: Whether we should write data to memory
ALUSrc : Chooses ALU second input (Second RF read data or sign-extended immediate)
RegWrite: Whether we should write data to RF
OpenPort: Wheter to open output_port of CPU
*/
assign RegDst = (opcode==`OPCODE_R);
assign Jump = (opcode==`OPCODE_JMP || opcode==`OPCODE_JAL);
assign Branch = (opcode==`OPCODE_BEQ || opcode==`OPCODE_BNE || opcode==`OPCODE_BGZ || opcode==`OPCODE_BLZ);
assign MemRead = (opcode==`OPCODE_LWD || opcode==`OPCODE_SWD);
assign MemtoReg = (opcode==`OPCODE_LWD);
assign MemWrite = (opcode==`OPCODE_SWD);
assign ALUSrc = !(opcode==`OPCODE_R || opcode==`OPCODE_BEQ || opcode==`OPCODE_BNE);
assign RegWrite = !(opcode==`OPCODE_SWD || opcode==`OPCODE_BEQ || opcode==`OPCODE_BNE || opcode==`OPCODE_BGZ || opcode==`OPCODE_BLZ || opcode==`OPCODE_JMP || func==`FUNC_WWD);
assign OpenPort = (opcode==`OPCODE_R & func==`FUNC_WWD);
always @(*) begin
if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
else if (opcode==`OPCODE_ADI || opcode==`OPCODE_LWD || opcode==`OPCODE_SWD) ALUOp = 0;
else if (opcode==`OPCODE_ORI) ALUOp = 3;
else if (opcode==`OPCODE_LHI) ALUOp = 8;
else if (opcode==`OPCODE_BNE) ALUOp = 9;
else if (opcode==`OPCODE_BEQ) ALUOp = 10;
else if (opcode==`OPCODE_BGZ) ALUOp = 11;
else if (opcode==`OPCODE_BLZ) ALUOp = 12;
else ALUOp = 15;
end
endmodule |
module Control(
input [3:0] opcode,
input [5:0] func,
input BranchMisprediction, JumpMisprediction, Stall,
output reg IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, PCWrite, IFIDWrite, IFFlush, IDEXWrite, ALUSrcA, RegSrc, Halt, OpenPort,
output reg [1:0] RegDst, ALUSrcB,
output reg [3:0] ALUOp
);
/*
[CPU control module]
Functionality:
By looking at the opcode and func field of an instruction, this module outputs appropriate control signals.
Also, when notified of branch/jump misprediction or pipeline stall, this module outputs control signals that
flush or stall part of the pipeline.
Inputs:
opcode and function code of the current instruction
BranchMisprediction, JumpMisprediction, are asserted when its name is detected at the CPU module.
Stall is asserted when the pipeline needs to stall due to data hazards.
Outputs: only those that are different from the lecture slide are explained here.
JumpType : Which type of jump destination? JumpAddress(0) or Rs(1)
RegSrc : Data being written to the RF. ALUResult(0) or MDR(1)
RegDst[2] : Adress of register to write to. Rt(00) or Rd(01) or 2(10)
ALUSrcA : First input to ALU. RFRead1(0) or PC(1)
ALUSrcB[2] : Second input to ALU. RFRead2(0) or sign-extended immediate(1) or 1(2)
IFIDWrite : Write enable bit for IF/ID pipeline register
IFFlush : Flush IF stage if enabled
IDEXWrite : Write enable bit for ID/EX pipeline register
*/
// Determine PCWrite, IFIDWrite, IFFlush, IDEXWrite separately according to state priority
always @(*) begin
if (BranchMisprediction) begin
PCWrite = 1;
IFIDWrite = 0;
IFFlush = 1;
IDEXWrite = 0;
end else if (Stall) begin
PCWrite = 0;
IFIDWrite = 0;
IFFlush = 0;
IDEXWrite = 0;
end else if (JumpMisprediction) begin
PCWrite = 1;
IFIDWrite = 0;
IFFlush = 1;
IDEXWrite = 1;
end else begin
PCWrite = 1;
IFIDWrite = 1;
IFFlush = 0;
IDEXWrite = 1;
end
end
// Determine usual control signals
always @(*) begin
JumpType = (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL));
DataMemRead = !Stall & (opcode==`OPCODE_LWD);
DataMemWrite = !Stall & (opcode==`OPCODE_SWD);
RegWrite = !Stall & ((opcode==`OPCODE_R & (func==`FUNC_ADD | func==`FUNC_SUB | func==`FUNC_AND | func==`FUNC_ORR | func==`FUNC_NOT | func==`FUNC_TCP | func==`FUNC_SHL | func==`FUNC_SHR | func==`FUNC_JRL)) | opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_JAL);
IsBranch = (opcode==`OPCODE_BEQ | opcode==`OPCODE_BNE | opcode==`OPCODE_BGZ | opcode==`OPCODE_BLZ);
IsJump = (opcode==`OPCODE_JMP | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & (func==`FUNC_JPR | func==`FUNC_JRL)));
ALUSrcA = (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL));
RegSrc = (opcode==`OPCODE_LWD);
Halt = (opcode==`OPCODE_R & func==`FUNC_HLT);
OpenPort = !BranchMisprediction & !JumpMisprediction & !Stall & (opcode==`OPCODE_R & func==`FUNC_WWD);
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUSrcB = 2;
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_ORI | opcode==`OPCODE_LHI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD) ALUSrcB = 1;
else ALUSrcB = 0;
if (opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) RegDst = 2;
else if (opcode==`OPCODE_R) RegDst = 1;
else RegDst = 0;
end
// Determine usual ALU operation
always @(*) begin
if (opcode==`OPCODE_R & func<8) ALUOp = func[3:0];
else if (opcode==`OPCODE_ADI | opcode==`OPCODE_LWD | opcode==`OPCODE_SWD | opcode==`OPCODE_JAL | (opcode==`OPCODE_R & func==`FUNC_JRL)) ALUOp = 0;
else if (opcode==`OPCODE_ORI) ALUOp = 3;
else if (opcode==`OPCODE_LHI) ALUOp = 8;
else if (opcode==`OPCODE_BNE) ALUOp = 9;
else if (opcode==`OPCODE_BEQ) ALUOp = 10;
else if (opcode==`OPCODE_BGZ) ALUOp = 11;
else if (opcode==`OPCODE_BLZ) ALUOp = 12;
else ALUOp = 15; // undefined operation
end
endmodule |
module cpu (
input Clk,
input Reset_N,
// Instruction memory interface
output i_readM,
output reg i_writeM,
output [`WORD_SIZE-1:0] i_address,
inout [`WORD_SIZE-1:0] i_data,
// Data memory interface
output d_readM,
output d_writeM,
output [`WORD_SIZE-1:0] d_address,
inout [`WORD_SIZE-1:0] d_data,
output [`WORD_SIZE-1:0] num_inst,
output [`WORD_SIZE-1:0] output_port,
output is_halted // 1 if the cpu is halted
);
///////////////////////////// Declarations and Instantiations /////////////////////////////
// Register and wire declarations
// Testbench purposes
reg [`WORD_SIZE-1:0] internal_num_inst; // only show num_inst value for exactly one cycle in each instruction
reg [`WORD_SIZE-1:0] jump_mispredict_penalty, branch_mispredict_penalty, stall_penalty;
// Program Counter related
reg [`WORD_SIZE-1:0] PC, nextPC;
// IF/ID pipeline registers. no control signals
reg [`WORD_SIZE-1:0] IF_ID_Inst, IF_ID_PC, IF_ID_nextPC;
// ID/EX pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] ID_EX_RFRead1, ID_EX_RFRead2, ID_EX_SignExtendedImm, ID_EX_PC, ID_EX_nextPC;
reg [1:0] ID_EX_RFWriteAddress;
// control signals
reg ID_EX_IsBranch, ID_EX_ALUSrcA, ID_EX_DataMemRead, ID_EX_DataMemWrite, ID_EX_RegWrite, ID_EX_Halt, ID_EX_RegSrc;
reg [1:0] ID_EX_RegDst, ID_EX_ALUSrcB;
reg [3:0] ID_EX_ALUOp;
// EX/MEM pipeline registers
// non - control signals
reg [`WORD_SIZE-1:0] EX_MEM_RFRead2, EX_MEM_PC, EX_MEM_ALUResult;
reg [1:0] EX_MEM_RFWriteAddress;
// control signals
reg EX_MEM_DataMemRead, EX_MEM_DataMemWrite, EX_MEM_RegWrite, EX_MEM_RegSrc;
// MEM/WB pipeline registers
//non - control signals
reg [`WORD_SIZE-1:0] MEM_WB_RFRead2, MEM_WB_MemData, MEM_WB_ALUResult;
reg [1:0] MEM_WB_RFWriteAddress;
// control signals
reg MEM_WB_RegWrite, MEM_WB_RegSrc;
// Control signals
wire IsBranch, IsJump, JumpType, DataMemRead, DataMemWrite, RegWrite, PCWrite, IFIDWrite, IFFlush, IDEXWrite, IDEXFlush, EXMEMWrite, MEMWBWrite, ALUSrcA, RegSrc, Halt, OpenPort;
wire [1:0] RegDst, ALUSrcB;
wire [3:0] ALUOp;
// Memory access
wire InstMemBusy, DataMemBusy;
reg InstMemCounter, DataMemCounter;
reg [`WORD_SIZE-1:0] IR, DR; // temporary instruction register, data register
reg [`WORD_SIZE-1:0] FetchCompletePC, MemCompleteAddr; // Latches the most recent fetch address (PC or memory address)
// Hazard detection
wire BranchMisprediction, JumpMisprediction, DataHazard;
// RF
reg [`WORD_SIZE-1:0] WriteData;
wire [`WORD_SIZE-1:0] RFRead1, RFRead2;
// ALU
reg [`WORD_SIZE-1:0] ALUin1, ALUin2;
wire [`WORD_SIZE-1:0] ALUResult;
wire BranchTaken;
// Module instantiations
// Control module is located at the ID stage.
Control control (.opcode(IF_ID_Inst[15:12]),
.func(IF_ID_Inst[5:0]),
.BranchMisprediction(BranchMisprediction),
.JumpMisprediction(JumpMisprediction),
.DataHazard(DataHazard),
.InstMemBusy(InstMemBusy),
.DataMemBusy(DataMemBusy),
.PCWrite(PCWrite),
.IFIDWrite(IFIDWrite),
.IFFlush(IFFlush),
.IDEXWrite(IDEXWrite),
.IDEXFlush(IDEXFlush),
.EXMEMWrite(EXMEMWrite),
.MEMWBWrite(MEMWBWrite),
.IsBranch(IsBranch),
.IsJump(IsJump),
.JumpType(JumpType),
.DataMemRead(DataMemRead),
.DataMemWrite(DataMemWrite),
.RegWrite(RegWrite),
.RegSrc(RegSrc),
.ALUSrcA(ALUSrcA),
.Halt(Halt),
.OpenPort(OpenPort),
.RegDst(RegDst),
.ALUSrcB(ALUSrcB),
.ALUOp(ALUOp));
// Hazard Detector module is located at the ID stage.
HazardDetector hazard_detector (.inst(IF_ID_Inst),
.ID_EX_RFWriteAddress(ID_EX_RFWriteAddress),
.EX_MEM_RFWriteAddress(EX_MEM_RFWriteAddress),
.MEM_WB_RFWriteAddress(MEM_WB_RFWriteAddress),
.ID_EX_RegWrite(ID_EX_RegWrite),
.EX_MEM_RegWrite(EX_MEM_RegWrite),
.MEM_WB_RegWrite(MEM_WB_RegWrite),
.DataHazard(DataHazard));
RF rf (.write(MEM_WB_RegWrite),
.clk(Clk),
.reset_n(Reset_N),
.addr1(IF_ID_Inst[11:10]),
.addr2(IF_ID_Inst[9:8]),
.addr3(MEM_WB_RFWriteAddress),
.data1(RFRead1),
.data2(RFRead2),
.data3(WriteData));
ALU alu (.A(ALUin1),
.B(ALUin2),
.OP(ID_EX_ALUOp),
.C(ALUResult),
.branch_cond(BranchTaken));
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////// CPU reset ///////////////////////////////////////
always @(posedge Clk) begin
if (!Reset_N) begin // Synchronous active-low reset
PC <= 0;
internal_num_inst <= 0;
InstMemCounter <= `LATENCY - 1;
DataMemCounter <= 0;
FetchCompletePC <= `WORD_SIZE'hffff;
MemCompleteAddr <= `WORD_SIZE'hffff;
IF_ID_Inst <= `WORD_SIZE'hffff;
IF_ID_PC <= 0;
IF_ID_nextPC <= 0;
ID_EX_RFWriteAddress <= 0;
ID_EX_PC <= 0;
ID_EX_nextPC <= 0;
ID_EX_IsBranch <= 0;
ID_EX_DataMemRead <= 0;
ID_EX_DataMemWrite <= 0;
ID_EX_RegWrite <= 0;
ID_EX_Halt <= 0;
EX_MEM_RFRead2 <= 0;
EX_MEM_PC <= 0;
EX_MEM_ALUResult <= 0;
EX_MEM_RFWriteAddress <= 0;
EX_MEM_DataMemRead <= 0;
EX_MEM_DataMemWrite <= 0;
EX_MEM_RegWrite <= 0;
EX_MEM_RegSrc <= 0;
MEM_WB_MemData <= 0;
MEM_WB_RFRead2 <= 0;
MEM_WB_RFWriteAddress <= 0;
MEM_WB_RegWrite <= 0;
MEM_WB_RegSrc <= 0;
MEM_WB_ALUResult <= 0;
end
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Pipeline register transfers ///////////////////////////////
always @(posedge Clk) begin
if (Reset_N) begin // Synchronous active-low reset
// IF/ID registers
if (IFIDWrite) begin
IF_ID_Inst <= IR;
IF_ID_PC <= PC;
IF_ID_nextPC <= nextPC;
end else if (IFFlush) begin
IF_ID_Inst <= `WORD_SIZE'hffff;
IF_ID_PC <= 0;
IF_ID_nextPC <= 0;
end
// ID/EX registers
if (IDEXWrite) begin
case (RegDst)
2'b00: ID_EX_RFWriteAddress <= IF_ID_Inst[9:8];
2'b01: ID_EX_RFWriteAddress <= IF_ID_Inst[7:6];
2'b10: ID_EX_RFWriteAddress <= 2'b10;
default: begin end
endcase
ID_EX_SignExtendedImm <= {{8{IF_ID_Inst[7]}}, IF_ID_Inst[7:0]};
ID_EX_RFRead1 <= RFRead1;
ID_EX_RFRead2 <= RFRead2;
ID_EX_PC <= IF_ID_PC;
ID_EX_nextPC <= IF_ID_nextPC;
ID_EX_IsBranch <= IsBranch;
ID_EX_ALUSrcA <= ALUSrcA;
ID_EX_ALUSrcB <= ALUSrcB;
ID_EX_DataMemRead <= DataMemRead;
ID_EX_DataMemWrite <= DataMemWrite;
ID_EX_RegWrite <= RegWrite;
ID_EX_RegSrc <= RegSrc;
ID_EX_RegDst <= RegDst;
ID_EX_ALUOp <= ALUOp;
ID_EX_Halt <= Halt;
end else if (IDEXFlush) begin
ID_EX_RFWriteAddress <= 0;
ID_EX_PC <= 0;
ID_EX_nextPC <= 0;
ID_EX_IsBranch <= 0;
ID_EX_DataMemRead <= 0;
ID_EX_DataMemWrite <= 0;
ID_EX_RegWrite <= 0;
ID_EX_Halt <= 0;
end
// EX/MEM registers
if (EXMEMWrite) begin
EX_MEM_RFRead2 <= ID_EX_RFRead2;
EX_MEM_PC <= ID_EX_PC;
EX_MEM_ALUResult <= ALUResult;
EX_MEM_RFWriteAddress <= ID_EX_RFWriteAddress;
EX_MEM_DataMemRead <= ID_EX_DataMemRead;
EX_MEM_DataMemWrite <= ID_EX_DataMemWrite;
EX_MEM_RegWrite <= ID_EX_RegWrite;
EX_MEM_RegSrc <= ID_EX_RegSrc;
end
// MEM/WB registers
if (MEMWBWrite) begin
MEM_WB_MemData <= DR;
MEM_WB_RFRead2 <= EX_MEM_RFRead2;
MEM_WB_RFWriteAddress <= EX_MEM_RFWriteAddress;
MEM_WB_RegWrite <= EX_MEM_RegWrite;
MEM_WB_RegSrc <= EX_MEM_RegSrc;
MEM_WB_ALUResult <= EX_MEM_ALUResult;
end else begin
MEM_WB_MemData <= 0;
MEM_WB_RFRead2 <= 0;
MEM_WB_RFWriteAddress <= 0;
MEM_WB_RegWrite <= 0;
MEM_WB_RegSrc <= 0;
MEM_WB_ALUResult <= 0;
end
end
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////// Outward Signals /////////////////////////////////////
// Only open output_port when control signal OpenPort is asserted,
assign output_port = OpenPort ? RFRead1 : `WORD_SIZE'bz;
// HLT should be serviced when it is guaranteed not to be flushed.
assign is_halted = ID_EX_Halt;
// num_inst counts the unique number of instructions that enter the ID stage.
assign num_inst = OpenPort ? internal_num_inst : `WORD_SIZE'bz;
always @(posedge Clk) begin
if (IFIDWrite) internal_num_inst <= internal_num_inst + 1;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Memory Access //////////////////////////////////////
assign i_address = PC;
assign i_readM = (!DataHazard && !BranchMisprediction && !JumpMisprediction && FetchCompletePC!=PC) || (internal_num_inst==0);
assign InstMemBusy = (InstMemCounter > 0);
// Simulating InstMemBusy of an actual instruction memory.
// Logic is elaborated on the design document.
always @(posedge Clk) begin
if (Reset_N) begin
if (BranchMisprediction || JumpMisprediction) begin
InstMemCounter <= `LATENCY - 1;
end else if (DataHazard) begin
InstMemCounter <= 0;
end else begin
if (InstMemCounter > 0)
InstMemCounter <= InstMemCounter - 1;
else
InstMemCounter <= `LATENCY - 1;
end
end
end
always @(posedge DataHazard)
InstMemCounter <= 0;
always @(negedge DataHazard)
InstMemCounter <= `LATENCY - 1;
// i_data is immediately latched into RR at negedge clk.
// On the next posedge clk, the content of IR is latched into IF_ID_Inst if IF/ID write is enabled.
// This is because IF may stall due to data memory stall. If we don't save the fetched instruction, we will lose it.
always @(i_data) begin
if (Clk==0 && i_readM && FetchCompletePC!=PC) begin
IR = i_data;
FetchCompletePC = PC;
end
end
// Data memory access
assign d_readM = (EX_MEM_DataMemRead && MemCompleteAddr!=EX_MEM_ALUResult);
assign d_writeM = EX_MEM_DataMemWrite;
assign d_data = (EX_MEM_DataMemWrite) ? EX_MEM_RFRead2 : `WORD_SIZE'bz;
assign d_address = (EX_MEM_DataMemRead || EX_MEM_DataMemWrite) ? EX_MEM_ALUResult : `WORD_SIZE'bz;
assign DataMemBusy = (DataMemCounter > 0);
// Simulating DataMemBusy of an actual data memory.
// Logic is elaborated on the design document.
always @(posedge Clk) begin
if (DataMemCounter > 0) begin
DataMemCounter <= DataMemCounter - 1;
end else if (ID_EX_DataMemRead || ID_EX_DataMemWrite) begin
DataMemCounter <= `LATENCY - 1;
end
end
// d_data is immediately latched into DR at negedge clk.
// On the next posedge clk, the content of DR is latched into MEM_WB_MemData if MEM/WB write is enabled.
always @(d_data) begin
if (Clk==0 && d_readM && MemCompleteAddr!=EX_MEM_ALUResult) begin
DR = d_data;
MemCompleteAddr = EX_MEM_ALUResult;
end
end
// After a write, need to flush MemCompleteAddr since data at that very data may have been changed
// (which was indeed the case during Test #20)
always @(posedge d_writeM) begin
MemCompleteAddr <= `WORD_SIZE'hffff;
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////// Updating PC ///////////////////////////////////////
// Branch mispredictions have higher priority
// since it is detected at the EX stage, whereas jump mispredictions are detected at the ID stage, hence being older.
always @(*) begin
if (ID_EX_IsBranch & BranchMisprediction) begin
if (BranchTaken) nextPC = ID_EX_PC + 1 + ID_EX_SignExtendedImm; // Branch should have been taken
else nextPC = ID_EX_PC + 1; // Branch shouldn't have been taken
end else if (IsJump & JumpMisprediction) begin
if (JumpType) nextPC = RFRead1; // JPR, JRL
else nextPC = {IF_ID_PC[15:12], IF_ID_Inst[11:0]}; // JMP, JAL
end else begin
nextPC = PC+1; // by the branch_predictor. Always PC+1 in the baseline model.
end
end
// Update PC at clock posedge
always @(posedge Clk) begin
if (Reset_N)
// No control signals before the ID stage of the first instruction. Manually enable PCwrite,
if (PCWrite) PC <= nextPC;
end
///////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////// Register File //////////////////////////////////////
always @(*) begin
case (MEM_WB_RegSrc)
0: WriteData = MEM_WB_ALUResult;
1: WriteData = MEM_WB_MemData;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////// ALU ///////////////////////////////////////////
always @(*) begin
case (ID_EX_ALUSrcA)
0: ALUin1 = ID_EX_RFRead1;
1: ALUin1 = ID_EX_PC;
endcase
end
always @(*) begin
case (ID_EX_ALUSrcB)
0: ALUin2 = ID_EX_RFRead2;
1: ALUin2 = ID_EX_SignExtendedImm;
2: ALUin2 = 1;
default: begin end
endcase
end
///////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Control Hazard Detection ////////////////////////////////
assign BranchMisprediction = ID_EX_IsBranch && ((BranchTaken && ID_EX_nextPC!=ALUResult) || (!BranchTaken && ID_EX_nextPC!=ID_EX_PC+1));
assign JumpMisprediction = IsJump && ((JumpType && RFRead1!=IF_ID_nextPC) || (!JumpType && {IF_ID_PC[15:12], IF_ID_Inst[11:0]}!=IF_ID_nextPC));
///////////////////////////////////////////////////////////////////////////////////////////
endmodule |
module PipelineCPU(
input wire sysclk,
input wire reset,
output wire [7:0] leds,
output wire [7:0] bcd7,
output wire [3:0] an
);
wire clk;
//CLK CLKController(sysclk, reset, clk);
assign clk = sysclk;
wire [31:0] Instruction;
wire [31:0] PC_now; // PC_IF
wire [31:0] PC_new;
// IF
InstructionMemory InstMemory(PC_now, Instruction);
// ID
wire [5:0] OpCode_ID;
wire [4:0] rs_ID;
wire [4:0] rt_ID;
wire [4:0] rd_ID;
wire [4:0] Shamt_ID;
wire [5:0] Funct_ID;
wire [31:0] PC_ID;
wire flush_IFID;
wire hold_IFID;
wire Load_EX;
IF_ID IFIDReg(clk, reset, flush_IFID, hold_IFID, Load_EX, Instruction, PC_now, OpCode_ID, rs_ID, rt_ID, rd_ID, Shamt_ID, Funct_ID, PC_ID);
wire [1:0] PCSrc_ID;
wire Branch_ID;
wire RegWrite_ID;
wire [1:0] RegDst_ID;
wire MemRead_ID;
wire MemWrite_ID;
wire [1:0] MemtoReg_ID;
wire ALUSrcA_ID;
wire ALUSrcB_ID;
wire ExtOp_ID;
wire LuOp_ID;
wire JOp_ID;
wire LoadByte_ID;
Control ControlDecoder(OpCode_ID, Funct_ID, PCSrc_ID, Branch_ID, RegWrite_ID, RegDst_ID, MemRead_ID, MemWrite_ID, MemtoReg_ID, ALUSrcA_ID, ALUSrcB_ID, ExtOp_ID, LuOp_ID, JOp_ID, LoadByte_ID);
wire [4:0] ALUCtrl_ID;
wire Sign_ID;
ALUControl ALUController(OpCode_ID, Funct_ID, ALUCtrl_ID, Sign_ID);
assign flush_IFID = Branch_ID || JOp_ID;
wire [31:0] WriteData_WB;
wire [4:0] Rw_WB;
wire RegWrite_WB;
wire [31:0] dataA_ID;
wire [31:0] dataB_ID;
RegisterFile RF(clk, reset, RegWrite_WB, rs_ID, rt_ID, Rw_WB, WriteData_WB, dataA_ID, dataB_ID);
wire [31:0] ImmExtOut_ID;
wire [31:0] ImmExtShift_ID;
ImmProcess Imm1(ExtOp_ID, LuOp_ID, {rd_ID, Shamt_ID, Funct_ID}, ImmExtOut_ID, ImmExtShift_ID);
wire Zero;
wire [1:0] BrForwardingA;
wire [1:0] BrForwardingB;
wire [31:0] BrJuderA;
wire [31:0] BrJuderB;
wire [4:0] Rw_MEM;
wire RegWrite_MEM;
wire [31:0] ALUOut_MEM;
wire Load_ID;
wire Load_WB;
assign Load_ID = OpCode_ID == 6'h23 || OpCode_ID == 6'h20;
BranchForwarding BrForwarding(rs_ID, rt_ID, Rw_MEM, RegWrite_MEM, Load_WB, Rw_WB, BrForwardingA, BrForwardingB);
assign BrJuderA = BrForwardingA == 1 ? ALUOut_MEM :
BrForwardingA == 2 ? WriteData_WB : dataA_ID;
assign BrJuderB = BrForwardingB == 1 ? ALUOut_MEM :
BrForwardingB == 2 ? WriteData_WB : dataB_ID;
BranchJudge BranchJudger(OpCode_ID, BrJuderA, BrJuderB, Branch_ID, Zero);
wire [31:0] PC_Branch;
assign PC_Branch = Branch_ID && Zero ? PC_ID + 4 + ImmExtShift_ID : PC_ID + 4;
// EX
wire flush_IDEX;
wire [4:0] Rw_EX;
//wire hold_IDEX;
wire RegWrite_EX;
wire Branch_EX;
wire MemRead_EX;
wire MemWrite_EX;
wire [1:0] MemtoReg_EX;
wire ALUSrcA_EX;
wire ALUSrcB_EX;
wire [4:0] ALUCtrl_EX;
wire [1:0] RegDst_EX;
wire [31:0] dataA_EX;
wire [31:0] dataB_EX;
wire [31:0] ImmExtOut_EX;
wire [4:0] Shamt_EX;
wire [4:0] rs_EX;
wire [4:0] rt_EX;
wire [4:0] rd_EX;
wire Sign_EX;
wire LoadByte_EX;
wire [31:0] PC_EX;
//wire Load_EX;
ID_EX IDEXReg(
clk, reset, flush_IDEX, RegWrite_ID, Branch_ID, MemRead_ID, MemWrite_ID,
MemtoReg_ID, ALUSrcA_ID, ALUSrcB_ID, ALUCtrl_ID, RegDst_ID, dataA_ID, dataB_ID,
ImmExtOut_ID, Shamt_ID, rs_ID, rt_ID, rd_ID, Sign_ID, LoadByte_ID, PC_ID, Load_ID,
RegWrite_EX, Branch_EX, MemRead_EX, MemWrite_EX,
MemtoReg_EX, ALUSrcA_EX, ALUSrcB_EX, ALUCtrl_EX, RegDst_EX, dataA_EX, dataB_EX,
ImmExtOut_EX, Shamt_EX, rs_EX, rt_EX, rd_EX, Sign_EX, LoadByte_EX, PC_EX, Load_EX
);
assign Rw_EX = RegDst_EX == 2'b00 ? rt_EX : RegDst_EX == 2'b01 ? rd_EX : 31; // 0: rt; 1: rd; 2: ra
assign hold_IFID = ((RegWrite_EX && Branch_ID && (Rw_EX == rs_ID || Rw_EX == rt_ID)) && Load_EX == 0) ||
(MemRead_EX && (rt_EX == rs_ID || rt_EX == rt_ID) && Load_EX); // next inst is branch && !Load, stall || load use hazard
assign flush_IDEX = (RegWrite_EX && Branch_ID && (Rw_EX == rs_ID || Rw_EX == rt_ID)) ||
(MemRead_EX && (rt_EX == rs_ID || rt_EX == rt_ID) && Load_EX);
wire [1:0] ALUChooseA;
wire [1:0] ALUChooseB;
ALUForwarding ALUForward(rs_EX, rt_EX, Rw_MEM, Rw_WB, RegWrite_MEM, RegWrite_WB, ALUSrcA_EX, ALUSrcB_EX, ALUChooseA, ALUChooseB);
wire [31:0] ALUinA;
wire [31:0] ALUinB;
assign ALUinA = ALUChooseA == 1 ? {27'h0000000, Shamt_EX} :
ALUChooseA == 2 ? ALUOut_MEM :
ALUChooseA == 3 ? WriteData_WB: dataA_EX;
assign ALUinB = ALUChooseB == 1 ? ImmExtOut_EX :
ALUChooseB == 2 ? ALUOut_MEM :
ALUChooseB == 3 ? WriteData_WB: dataB_EX;
wire [31:0] ALUOut_EX;
ALU ALUCalculate(ALUCtrl_EX, Sign_EX, ALUinA, ALUinB, ALUOut_EX);
// MEM
wire MemRead_MEM;
wire MemWrite_MEM;
//wire [31:0] ALUOut_MEM;
//wire [4:0] Rw_MEM;
wire [1:0] MemtoReg_MEM;
//wire RegWrite_MEM;
wire [31:0] dataB_MEM;
wire LoadByte_MEM;
wire [31:0] PC_MEM;
wire Load_MEM;
EX_MEM EXMEMReg(
clk, reset, MemRead_EX, MemWrite_EX, ALUOut_EX, Rw_EX, MemtoReg_EX, RegWrite_EX, dataB_EX, LoadByte_EX, PC_EX, Load_EX,
MemRead_MEM, MemWrite_MEM, ALUOut_MEM, Rw_MEM, MemtoReg_MEM, RegWrite_MEM, dataB_MEM, LoadByte_MEM, PC_MEM, Load_MEM
);
wire [31:0] ReadData_Temp;
DataMemory DataMem(clk, reset, ALUOut_MEM, dataB_MEM, ReadData_Temp, MemRead_MEM, MemWrite_MEM, leds, bcd7, an);
wire [31:0] ReadData_MEM;
assign ReadData_MEM = LoadByte_MEM == 0 ? ReadData_Temp :
ALUOut_MEM[1:0] == 2'b00 ? {{24{ReadData_Temp[7]}}, ReadData_Temp[7:0]} :
ALUOut_MEM[1:0] == 2'b01 ? {{24{ReadData_Temp[15]}}, ReadData_Temp[15:8]} :
ALUOut_MEM[1:0] == 2'b10 ? {{24{ReadData_Temp[23]}}, ReadData_Temp[23:16]} :
{{24{ReadData_Temp[31]}}, ReadData_Temp[31:24]};
// WB
//wire RegWrite_WB;
wire [1:0] MemtoReg_WB;
//wire [4:0] Rw_WB;
wire [31:0] ReadData_WB;
wire [31:0] ALUOut_WB;
wire [31:0] PC_WB;
//wire Load_WB;
MEM_WB MEMWBReg(
clk, reset, RegWrite_MEM, MemtoReg_MEM, Rw_MEM, ReadData_MEM, ALUOut_MEM, PC_MEM, Load_MEM,
RegWrite_WB, MemtoReg_WB, Rw_WB, ReadData_WB, ALUOut_WB, PC_WB, Load_WB
);
//wire [31:0] WriteData_WB;
assign WriteData_WB = MemtoReg_WB == 1 ? ReadData_WB :
MemtoReg_WB == 2 ? PC_WB : ALUOut_WB;
// PC
assign PC_new = (RegWrite_EX && Branch_ID && (Rw_EX == rs_ID || Rw_EX == rt_ID) && Load_EX) ? PC_now - 4 :
hold_IFID ? PC_now :
PCSrc_ID == 1 ? {PC_ID[31:28], rs_ID, rt_ID, rd_ID, Shamt_ID, Funct_ID, 2'b00} :
PCSrc_ID == 2 ? dataA_ID + 4:
// (Branch_ID && Zero) ? PC_now + ImmExtShift_ID : // ID stage Judge: PC_now has plused 4
// Branch_ID ? PC_now :
Branch_ID ? PC_Branch :
PC_now + 4;
PC PCConctroller(clk, reset, PC_new, PC_now);
endmodule |
module ALU (
ALUCtrl,
Sign,
in1,
in2,
out
);
parameter ADD = 0;
parameter SUB = 1;
parameter AND = 2;
parameter OR = 3;
parameter XOR = 4;
parameter NOR = 5;
parameter SLL = 6;
parameter SRL = 7;
parameter SRA = 8;
parameter SLT = 9;
input [4:0] ALUCtrl;
input Sign;
input [31:0] in1;
input [31:0] in2;
output [31:0] out;
reg [31:0] out;
wire lt_low31;
wire lt_sign;
assign lt_low31 = (in1[30:0] < in2[30:0]);
assign lt_sign = (
(in1[31] ^ in2[31]) ?
(in1[31] > in2[31] ? 1 : 0)
: lt_low31
);
always @(*) begin
case(ALUCtrl)
ADD: out <= in1 + in2;
SUB: out <= in1 - in2;
AND: out <= in1 & in2;
OR: out <= in1 | in2;
XOR: out <= in1 ^ in2;
NOR: out <= ~(in1 | in2);
SLL: out <= in2 << in1[4:0];
SRL: out <= in2 >> in1[4:0];
SRA: out <= {{32{in2[31]}}, in2} >> in1[4:0];
SLT: out <= {31'h00000000, Sign ? lt_sign : in1 < in2};
default: out <= 0;
endcase
end
endmodule |
module EX_MEM(
input wire clk,
input wire reset,
input wire MemRead_EX,
input wire MemWrite_EX,
input wire [31:0] ALUOut_EX,
input wire [4:0] Rw_EX,
input wire [1:0] MemtoReg_EX,
input wire RegWrite_EX,
input wire [31:0] rt_EX,
input wire LoadByte_EX,
input wire [31:0] PC_EX,
input wire Load_EX,
output reg MemRead_MEM,
output reg MemWrite_MEM,
output reg [31:0] ALUOut_MEM,
output reg [4:0] Rw_MEM,
output reg [1:0] MemtoReg_MEM,
output reg RegWrite_MEM,
output reg [31:0] rt_MEM,
output reg LoadByte_MEM,
output reg [31:0] PC_MEM,
output reg Load_MEM
);
initial begin
MemRead_MEM <= 0;
MemWrite_MEM <= 0;
ALUOut_MEM <= 0;
Rw_MEM <= 0;
MemtoReg_MEM <= 0;
RegWrite_MEM <= 0;
rt_MEM <= 0;
LoadByte_MEM <= 0;
PC_MEM <= 0;
Load_MEM <= 0;
end
always@(posedge clk or posedge reset) begin
if(reset) begin
MemRead_MEM <= 0;
MemWrite_MEM <= 0;
ALUOut_MEM <= 0;
Rw_MEM <= 0;
MemtoReg_MEM <= 0;
RegWrite_MEM <= 0;
rt_MEM <= 0;
LoadByte_MEM <= 0;
PC_MEM <= 0;
Load_MEM <= 0;
end
else begin
MemRead_MEM <= MemRead_EX;
MemWrite_MEM <= MemWrite_EX;
ALUOut_MEM <= ALUOut_EX;
Rw_MEM <= Rw_EX;
MemtoReg_MEM <= MemtoReg_EX;
RegWrite_MEM <= RegWrite_EX;
rt_MEM <= rt_EX;
LoadByte_MEM <= LoadByte_EX;
PC_MEM <= PC_EX;
Load_MEM <= Load_EX;
end
end
endmodule |
module ALUControl (
OpCode,
Funct,
ALUCtrl,
Sign
);
parameter ADD = 0;
parameter SUB = 1;
parameter AND = 2;
parameter OR = 3;
parameter XOR = 4;
parameter NOR = 5;
parameter SLL = 6;
parameter SRL = 7;
parameter SRA = 8;
parameter SLT = 9;
input [5:0] OpCode;
input [5:0] Funct;
output [4:0] ALUCtrl;
output Sign;
reg [4:0] ALUCtrl;
reg Sign;
always @(OpCode, Funct) begin
case(OpCode)
6'h23: ALUCtrl <= ADD; // lw
6'h20: ALUCtrl <= ADD; // lb
6'h2b: ALUCtrl <= ADD; // sw
6'h0f: ALUCtrl <= ADD; // lui
6'h08: begin
ALUCtrl <= ADD;
Sign <= 1;
end
6'h09: begin
ALUCtrl <= ADD;
Sign <= 0;
end
6'h0c: ALUCtrl <= AND;
6'h0a: begin
ALUCtrl <= SLT;
Sign <= 1;
end
6'h0b: begin
ALUCtrl <= SLT;
Sign <= 0;
end
6'h04: ALUCtrl <= SUB; // beq
default: begin // Opcode = 0
case(Funct)
6'h20: begin
ALUCtrl <= ADD;
Sign <= 1;
end
6'h21: begin
ALUCtrl <= ADD;
Sign <= 0;
end
6'h22: begin
ALUCtrl <= SUB;
Sign <= 1;
end
6'h23: begin
ALUCtrl <= SUB;
Sign <= 0;
end
6'h24: ALUCtrl <= AND;
6'h25: ALUCtrl <= OR;
6'h26: ALUCtrl <= XOR;
6'h27: ALUCtrl <= NOR;
6'h00: ALUCtrl <= SLL;
6'h02: begin
ALUCtrl <= SRL;
Sign <= 0;
end
6'h03: begin
ALUCtrl <= SRA;
Sign <= 1;
end
6'h2a: begin
ALUCtrl <= SLT;
Sign <= 1;
end
6'h2b: begin
ALUCtrl <= SLT;
Sign <= 0;
end
6'h08: ALUCtrl <= ADD; // jr
6'h09: ALUCtrl <= ADD; // jalr
default: ALUCtrl <= ALUCtrl;
endcase
end
endcase
end
endmodule |
module ALUForwarding(
input wire [4:0] rs_EX,
input wire [4:0] rt_EX,
input wire [4:0] Rw_MEM,
input wire [4:0] Rw_WB,
input wire RegWrite_MEM,
input wire RegWrite_WB,
input wire ALUSrcA_EX,
input wire ALUSrcB_EX,
output wire [1:0] ALUChooseA, // A: 0-dataA 1-Shamt 2-WriteData_MEM 3-WriteData_WB
output wire [1:0] ALUChooseB // B: 0-dataB 1-Imm 2-WriteData_MEM 3-WriteData_WB
);
assign ALUChooseA = ALUSrcA_EX == 1 ? 1 :
(RegWrite_MEM && (Rw_MEM == rs_EX) && (Rw_MEM != 0)) ? 2 : // 优先判断MEM阶段，即前一条指令
(RegWrite_WB && (Rw_WB == rs_EX) && (Rw_WB != 0)) ? 3 : 0;
assign ALUChooseB = ALUSrcB_EX == 1 ? 1 :
(RegWrite_MEM && (Rw_MEM == rt_EX) && (Rw_MEM != 0)) ? 2 : // 优先判断MEM阶段，即前一条指令
(RegWrite_WB && (Rw_WB == rt_EX) && (Rw_WB != 0)) ? 3 : 0;
endmodule |
module Control(OpCode, Funct,
PCSrc, Branch, RegWrite, RegDst,
MemRead, MemWrite, MemtoReg,
ALUSrc1, ALUSrc2, ExtOp, LuOp, JOp, LoadByte
);
input wire [5:0] OpCode;
input wire [5:0] Funct;
output wire [1:0] PCSrc;
output wire Branch;
output wire RegWrite;
output wire [1:0] RegDst;
output wire MemRead;
output wire MemWrite;
output wire [1:0] MemtoReg;
output wire ALUSrc1;
output wire ALUSrc2;
output wire ExtOp;
output wire LuOp;
output wire JOp;
output wire LoadByte;
// Your code below
assign PCSrc = (OpCode == 6'h02 || OpCode == 6'h03) ? 1 : // j,jal: 1 -- jr,jalr: 2 -- 0
(OpCode == 0 && (Funct == 6'h08 || Funct == 6'h09)) ? 2 : 0;
assign Branch = OpCode == 6'h04 || OpCode == 6'h05 || OpCode == 6'h06 || OpCode == 6'h07 || OpCode == 6'h01;
assign RegWrite = (OpCode == 6'h2b || OpCode == 6'h04 || OpCode == 6'h05 || OpCode == 6'h06 || OpCode == 6'h07 || OpCode == 6'h01 ||
OpCode == 6'h02 || (OpCode == 6'h00 && Funct == 6'h08)) ? 0 : 1;
assign RegDst = (OpCode == 6'h23 || OpCode == 6'h20 || OpCode == 6'h0f || OpCode == 6'h08 || OpCode == 6'h09 ||
OpCode == 6'h0c || OpCode == 6'h0a || OpCode == 6'h0b) ? 0 :
OpCode == 6'h03 ? 2 : 1; // 0: rt; 1: rd; 2: ra
assign MemRead = OpCode == 6'h23 || OpCode == 6'h20;
assign MemWrite = OpCode == 6'h2b;
assign MemtoReg = OpCode == 6'h23 || OpCode == 6'h20 ? 1 :
(OpCode == 6'h03 || (OpCode == 6'h00 && Funct == 6'h09)) ? 2 : 0;
assign ALUSrc1 = (OpCode == 6'h00 && (Funct == 6'h00 || Funct == 6'h02 || Funct == 6'h03)) ? 1 : 0;
assign ALUSrc2 = (OpCode == 6'h23 || OpCode == 6'h20 || OpCode == 6'h2b || OpCode == 6'h0f ||
OpCode == 6'h08 || OpCode == 6'h09 || OpCode == 6'h0c ||
OpCode == 6'h0a || OpCode == 6'h0b) ? 1 : 0;
assign ExtOp = OpCode == 6'h0c ? 0 : 1;
assign LuOp = OpCode == 6'h0f;
assign JOp = OpCode == 6'h02 || OpCode == 6'h03 || (OpCode == 6'h00 && (Funct == 6'h08 || Funct == 6'h09));
assign LoadByte = OpCode == 6'h20;
// Your code above
endmodule |
module ImmProcess(ExtOp, LuiOp, Immediate, ImmExtOut, ImmExtShift);
//Input Control Signals
input ExtOp; //'0'-zero extension, '1'-signed extension
input LuiOp; //for lui instruction
//Input
input [15:0] Immediate;
//Output
output [31:0] ImmExtOut;
output [31:0] ImmExtShift;
wire [31:0] ImmExt;
assign ImmExt = {ExtOp? {16{Immediate[15]}}: 16'h0000, Immediate};
assign ImmExtShift = ImmExt << 2;
assign ImmExtOut = LuiOp? {Immediate, 16'h0000}: ImmExt;
endmodule |
module IF_ID(
input wire clk,
input wire reset,
input wire flush_IFID,
input wire hold,
input wire Load_EX, // if Load, flush is more important than hold
input wire [31:0] Instruction,
input wire [31:0] PC_IF,
output reg [5:0] OpCode,
output reg [4:0] rs,
output reg [4:0] rt,
output reg [4:0] rd,
output reg [4:0] Shamt,
output reg [5:0] Funct,
output reg [31:0] PC_ID
);
initial begin
OpCode <= 0;
rs <= 0;
rt <= 0;
rd <= 0;
Shamt <= 0;
Funct <= 0;
PC_ID <= 0;
end
always @(posedge clk or posedge reset) begin
if(reset || (flush_IFID && Load_EX)) begin // || flush_IFID
OpCode <= 0;
rs <= 0;
rt <= 0;
rd <= 0;
Shamt <= 0;
Funct <= 0;
PC_ID <= 0;
end
else if (hold) begin
OpCode <= OpCode;
rs <= rs;
rt <= rt;
rd <= rd;
Shamt <= Shamt;
Funct <= Funct;
PC_ID <= PC_ID;
end
else if (flush_IFID) begin
OpCode <= 0;
rs <= 0;
rt <= 0;
rd <= 0;
Shamt <= 0;
Funct <= 0;
PC_ID <= 0;
end
else begin
OpCode <= Instruction[31:26];
rs <= Instruction[25:21];
rt <= Instruction[20:16];
rd <= Instruction[15:11];
Shamt <= Instruction[10:6];
Funct <= Instruction[5:0];
PC_ID <= PC_IF;
end
// else if(!hold) begin
// if(flush_IFID) begin
// OpCode <= 0;
// rs <= 0;
// rt <= 0;
// rd <= 0;
// Shamt <= 0;
// Funct <= 0;
// PC_ID <= 0;
// end
// else begin
// OpCode <= Instruction[31:26];
// rs <= Instruction[25:21];
// rt <= Instruction[20:16];
// rd <= Instruction[15:11];
// Shamt <= Instruction[10:6];
// Funct <= Instruction[5:0];
// PC_ID <= PC_IF;
// end
// end
// else begin
// OpCode <= OpCode;
// rs <= rs;
// rt <= rt;
// rd <= rd;
// Shamt <= Shamt;
// Funct <= Funct;
// PC_ID <= PC_ID;
// end
end
endmodule |
module test_pipeline();
reg reset;
reg sysclk;
wire [7:0] leds;
wire [7:0] bcd7;
wire [3:0] an;
PipelineCPU pipelineCpu(sysclk, reset, leds, bcd7, an);
initial begin
reset = 1;
sysclk = 1;
#10 reset = 0;
end
always #5 sysclk = ~sysclk;
endmodule |
module CLK(
input wire sysclk,
input wire reset,
output reg clk
);
reg [31:0] count;
initial begin
count <= 0;
end
always@(posedge sysclk or posedge reset) begin
if(reset) begin
count <= 0;
clk <= 0;
end
else if(count >= 2) begin
clk <= ~clk;
count <= 0;
end
else begin
count <= count + 1;
end
end
endmodule |
module ID_EX(
input wire clk,
input wire reset,
input wire flush_IDEX,
//input wire hold_IDEX,
input wire RegWrite_ID,
input wire Branch_ID,
input wire MemRead_ID,
input wire MemWrite_ID,
input wire [1:0] MemtoReg_ID,
input wire ALUSrcA_ID,
input wire ALUSrcB_ID,
input wire [4:0] ALUCtrl_ID,
input wire [1:0] RegDst_ID,
input wire [31:0] dataA_ID,
input wire [31:0] dataB_ID,
input wire [31:0] ImmExtOut_ID,
input wire [4:0] Shamt_ID,
input wire [4:0] rs_ID,
input wire [4:0] rt_ID,
input wire [4:0] rd_ID,
input wire Sign_ID,
input wire LoadByte_ID,
input wire [31:0] PC_ID,
input wire Load_ID,
output reg RegWrite_EX,
output reg Branch_EX,
output reg MemRead_EX,
output reg MemWrite_EX,
output reg [1:0] MemtoReg_EX,
output reg ALUSrcA_EX,
output reg ALUSrcB_EX,
output reg [4:0] ALUCtrl_EX,
output reg [1:0] RegDst_EX,
output reg [31:0] dataA_EX,
output reg [31:0] dataB_EX,
output reg [31:0] ImmExtOut_EX,
output reg [4:0] Shamt_EX,
output reg [4:0] rs_EX,
output reg [4:0] rt_EX,
output reg [4:0] rd_EX,
output reg Sign_EX,
output reg LoadByte_EX,
output reg [31:0] PC_EX,
output reg Load_EX
);
initial begin
RegWrite_EX <= 0;
Branch_EX <= 0;
MemRead_EX <= 0;
MemWrite_EX <= 0;
MemtoReg_EX <= 0;
ALUSrcA_EX <= 0;
ALUSrcB_EX <= 0;
ALUCtrl_EX <= 0;
RegDst_EX <= 0;
dataA_EX <= 0;
dataB_EX <= 0;
ImmExtOut_EX <= 0;
Shamt_EX <= 0;
rs_EX <= 0;
rt_EX <= 0;
rd_EX <= 0;
Sign_EX <= 0;
LoadByte_EX <= 0;
PC_EX <= 0;
Load_EX <= 0;
end
always@(posedge clk or posedge reset) begin
if(reset || flush_IDEX) begin
RegWrite_EX <= 0;
Branch_EX <= 0;
MemRead_EX <= 0;
MemWrite_EX <= 0;
MemtoReg_EX <= 0;
ALUSrcA_EX <= 0;
ALUSrcB_EX <= 0;
ALUCtrl_EX <= 0;
RegDst_EX <= 0;
dataA_EX <= 0;
dataB_EX <= 0;
ImmExtOut_EX <= 0;
Shamt_EX <= 0;
rs_EX <= 0;
rt_EX <= 0;
rd_EX <= 0;
Sign_EX <= 0;
LoadByte_EX <= 0;
PC_EX <= 0;
Load_EX <= 0;
end
else begin
RegWrite_EX <= RegWrite_ID;
Branch_EX <= Branch_ID;
MemRead_EX <= MemRead_ID;
MemWrite_EX <= MemWrite_ID;
MemtoReg_EX <= MemtoReg_ID;
ALUSrcA_EX <= ALUSrcA_ID;
ALUSrcB_EX <= ALUSrcB_ID;
ALUCtrl_EX <= ALUCtrl_ID;
RegDst_EX <= RegDst_ID;
dataA_EX <= dataA_ID;
dataB_EX <= dataB_ID;
ImmExtOut_EX <= ImmExtOut_ID;
Shamt_EX <= Shamt_ID;
rs_EX <= rs_ID;
rt_EX <= rt_ID;
rd_EX <= rd_ID;
Sign_EX <= Sign_ID;
LoadByte_EX <= LoadByte_ID;
PC_EX <= PC_ID;
Load_EX <= Load_ID;
end
// else begin
// RegWrite_EX <= RegWrite_EX;
// Branch_EX <= Branch_EX;
// MemRead_EX <= MemRead_EX;
// MemWrite_EX <= MemWrite_EX;
// MemtoReg_EX <= MemtoReg_EX;
// ALUSrcA_EX <= ALUSrcA_EX;
// ALUSrcB_EX <= ALUSrcB_EX;
// ALUCtrl_EX <= ALUCtrl_EX;
// RegDst_EX <= RegDst_EX;
// dataA_EX <= dataA_EX;
// dataB_EX <= dataB_EX;
// ImmExtOut_EX <= ImmExtOut_EX;
// Shamt_EX <= Shamt_EX;
// rt_EX <= rt_EX;
// rd_EX <= rd_EX;
// Sign_EX <= Sign_EX;
// LoadByte_EX <= LoadByte_EX;
// end
end
endmodule |
module MEM_WB(
input wire clk,
input wire reset,
input wire RegWrite_MEM,
input wire [1:0] MemtoReg_MEM,
input wire [4:0] Rw_MEM,
input wire [31:0] ReadData_MEM,
input wire [31:0] ALUOut_MEM,
input wire [31:0] PC_MEM,
input wire Load_MEM,
output reg RegWrite_WB,
output reg [1:0] MemtoReg_WB,
output reg [4:0] Rw_WB,
output reg [31:0] ReadData_WB,
output reg [31:0] ALUOut_WB,
output reg [31:0] PC_WB,
output reg Load_WB
);
initial begin
RegWrite_WB <= 0;
MemtoReg_WB <= 0;
Rw_WB <= 0;
ReadData_WB <= 0;
ALUOut_WB <= 0;
PC_WB <= 0;
Load_WB <= 0;
end
always @(posedge clk or posedge reset) begin
if(reset) begin
RegWrite_WB <= 0;
MemtoReg_WB <= 0;
Rw_WB <= 0;
ReadData_WB <= 0;
ALUOut_WB <= 0;
PC_WB <= 0;
Load_WB <= 0;
end
else begin
RegWrite_WB <= RegWrite_MEM;
MemtoReg_WB <= MemtoReg_MEM;
Rw_WB <= Rw_MEM;
ReadData_WB <= ReadData_MEM;
ALUOut_WB <= ALUOut_MEM;
PC_WB <= PC_MEM;
Load_WB <= Load_MEM;
end
end
endmodule |
module BranchJudge(
input wire [5:0] OpCode,
input wire [31:0] data1_ID,
input wire [31:0] data2_ID,
input wire Branch,
output reg Zero
);
always@(*) begin
if(Branch) begin
if(OpCode == 6'h04) begin // beq
Zero <= data1_ID == data2_ID;
end
else if(OpCode == 6'h05) begin // bne
Zero <= data1_ID != data2_ID;
end
else if(OpCode == 6'h06) begin // blez
Zero <= (data1_ID <= data2_ID);
end
else if(OpCode == 6'h07) begin // bgtz
Zero <= (data1_ID > data2_ID);
end
else if(OpCode == 6'h01) begin // bltz
Zero <= (data1_ID < data2_ID);
end
else begin
Zero <= Zero;
end
end
else begin
Zero <= 0;
end
end
endmodule |
module RegisterFile(clk, reset, RegWrite, Read_register1, Read_register2, Write_register, Write_data, Read_data1, Read_data2);
input reset, clk;
input RegWrite;
input [4:0] Read_register1, Read_register2, Write_register;
input [31:0] Write_data;
output [31:0] Read_data1, Read_data2;
reg [31:0] RF_data[31:0];
wire Writable;
assign Writable = RegWrite && (Write_register != 5'b00000);
assign Read_data1 = (Write_register == Read_register1 && Writable) ? Write_data :
(Read_register1 == 5'b00000)? 32'h00000000: RF_data[Read_register1];
assign Read_data2 = (Write_register == Read_register2 && Writable) ? Write_data :
(Read_register2 == 5'b00000)? 32'h00000000: RF_data[Read_register2];
integer i;
always @(posedge reset or posedge clk)
if (reset)
for (i = 1; i < 32; i = i + 1)
RF_data[i] <= 32'h00000000;
else if (Writable)
RF_data[Write_register] <= Write_data;
endmodule |
module DataMemory(clk, reset, Address, Write_data, Read_data, MemRead, MemWrite, LEDData, BCDData, an);
input clk, reset;
input [31:0] Address, Write_data;
input MemRead, MemWrite;
output [31:0] Read_data;
output reg [7:0] LEDData;
output wire [7:0] BCDData;
output wire [3:0] an;
reg [11:0] ANBCDData;
parameter RAM_SIZE = 512;
parameter RAM_SIZE_BIT = 9;
reg [31:0] RAM_data[RAM_SIZE - 1: 0];
assign Read_data = MemRead ? RAM_data[Address[RAM_SIZE_BIT + 1:2]]: 32'h00000000;
assign BCDData = ANBCDData[7:0];
assign an = ANBCDData[11:8];
integer j;
initial begin
LEDData <= 0;
ANBCDData <= 0;
// for(i = 0; i < RAM_SIZE; i = i + 1) begin
// case(i)
// 0: RAM_data[0] <= 32'h756e696c;
// 1: RAM_data[1] <= 32'h6e736978;
// 2: RAM_data[2] <= 32'h6e75746f;
// 3: RAM_data[3] <= 32'h73697869;
// 4: RAM_data[4] <= 32'h75746f6e;
// 5: RAM_data[5] <= 32'h6978696e;
// 6: RAM_data[6] <= 32'h746f6e73;
// 7: RAM_data[7] <= 32'h78696e75;
// 100: RAM_data[100] <= 32'h78696e75;
// default: RAM_data[i] <= 32'h0;
// endcase
// end
for(i = 0; i < RAM_SIZE; i = i + 1) begin
case(i)
0: RAM_data[0] <= 32'h64636261;
1: RAM_data[1] <= 32'h63626178;
2: RAM_data[2] <= 32'h65737364;
3: RAM_data[3] <= 32'h64636261;
4: RAM_data[4] <= 32'h61786373;
5: RAM_data[5] <= 32'h66646362;
6: RAM_data[6] <= 32'h63626173;
7: RAM_data[7] <= 32'h62617664;
8: RAM_data[8] <= 32'h61616463;
9: RAM_data[9] <= 32'h62616463;
10: RAM_data[10] <= 32'h61636463;
11: RAM_data[11] <= 32'h61706362;
12: RAM_data[12] <= 32'h6e646362;
13: RAM_data[13] <= 32'h64636261;
14: RAM_data[14] <= 32'h72657771;
15: RAM_data[15] <= 32'h64636261;
16: RAM_data[16] <= 32'h6362616c;
17: RAM_data[17] <= 32'h61676764;
18: RAM_data[18] <= 32'h67646362;
19: RAM_data[19] <= 32'h64636261;
20: RAM_data[20] <= 32'h63626167;
21: RAM_data[21] <= 32'h65636564;
22: RAM_data[22] <= 32'h6d656161;
23: RAM_data[23] <= 32'h64636261;
24: RAM_data[24] <= 32'h72646b6c;
25: RAM_data[25] <= 32'h64636261;
26: RAM_data[26] <= 32'h62616262;
27: RAM_data[27] <= 32'h63636463;
28: RAM_data[28] <= 32'h64636261;
100: RAM_data[100] <= 32'h64636261;
default: RAM_data[i] <= 32'h00000000;
endcase
end
end
integer i;
always @(posedge reset or posedge clk)
if (reset) begin
LEDData <= 0;
ANBCDData <= 0;
// for(i = 0; i < RAM_SIZE; i = i + 1) begin
// case(i)
// 0: RAM_data[0] <= 32'h756e696c;
// 1: RAM_data[1] <= 32'h6e736978;
// 2: RAM_data[2] <= 32'h6e75746f;
// 3: RAM_data[3] <= 32'h73697869;
// 4: RAM_data[4] <= 32'h75746f6e;
// 5: RAM_data[5] <= 32'h6978696e;
// 6: RAM_data[6] <= 32'h746f6e73;
// 7: RAM_data[7] <= 32'h78696e75;
// 100: RAM_data[100] <= 32'h78696e75;
// default: RAM_data[i] <= 32'h0;
// endcase
// end
for(i = 0; i < RAM_SIZE; i = i + 1) begin
case(i)
0: RAM_data[0] <= 32'h64636261;
1: RAM_data[1] <= 32'h63626178;
2: RAM_data[2] <= 32'h65737364;
3: RAM_data[3] <= 32'h64636261;
4: RAM_data[4] <= 32'h61786373;
5: RAM_data[5] <= 32'h66646362;
6: RAM_data[6] <= 32'h63626173;
7: RAM_data[7] <= 32'h62617664;
8: RAM_data[8] <= 32'h61616463;
9: RAM_data[9] <= 32'h62616463;
10: RAM_data[10] <= 32'h61636463;
11: RAM_data[11] <= 32'h61706362;
12: RAM_data[12] <= 32'h6e646362;
13: RAM_data[13] <= 32'h64636261;
14: RAM_data[14] <= 32'h72657771;
15: RAM_data[15] <= 32'h64636261;
16: RAM_data[16] <= 32'h6362616c;
17: RAM_data[17] <= 32'h61676764;
18: RAM_data[18] <= 32'h67646362;
19: RAM_data[19] <= 32'h64636261;
20: RAM_data[20] <= 32'h63626167;
21: RAM_data[21] <= 32'h65636564;
22: RAM_data[22] <= 32'h6d656161;
23: RAM_data[23] <= 32'h64636261;
24: RAM_data[24] <= 32'h72646b6c;
25: RAM_data[25] <= 32'h64636261;
26: RAM_data[26] <= 32'h62616262;
27: RAM_data[27] <= 32'h63636463;
28: RAM_data[28] <= 32'h64636261;
100: RAM_data[100] <= 32'h64636261;
default: RAM_data[i] <= 32'h00000000;
endcase
end
end
else if (MemWrite) begin
if(Address == 32'h4000000C) begin
LEDData <= Write_data[7:0];
end
else if(Address == 32'h40000010) begin
ANBCDData <= Write_data[11:0];
end
else begin
RAM_data[Address[RAM_SIZE_BIT + 1:2]] <= Write_data;
end
end
else begin
ANBCDData <= ANBCDData;
LEDData <= LEDData;
end
endmodule |
module InstructionMemory(Address, Instruction);
input wire [31:0] Address;
output wire [31:0] Instruction;
parameter MEM_SIZE = 512;
reg [31:0] data [MEM_SIZE - 1:0];
assign Instruction = data[Address[10:2]];
integer i;
initial begin
//data[9'd0] <= 32'h20040020;
data[9'd0] <= 32'h20040074;
data[9'd1] <= 32'h20050000;
data[9'd2] <= 32'h20060004;
data[9'd3] <= 32'h20070190;
data[9'd4] <= 32'h00865022;
data[9'd5] <= 32'h20080000;
data[9'd6] <= 32'h20020000;
data[9'd7] <= 32'h0148582a;
data[9'd8] <= 32'h1560000f;
data[9'd9] <= 32'h20090000;
data[9'd10] <= 32'h0126582a;
data[9'd11] <= 32'h11600008;
data[9'd12] <= 32'h01096020;
data[9'd13] <= 32'h01856820;
data[9'd14] <= 32'h81ae0000;
data[9'd15] <= 32'h01276820;
data[9'd16] <= 32'h81af0000;
data[9'd17] <= 32'h15cf0002;
data[9'd18] <= 32'h21290001;
data[9'd19] <= 32'h0810000a;
data[9'd20] <= 32'h15260001;
data[9'd21] <= 32'h20420001;
data[9'd22] <= 32'h21080001;
data[9'd23] <= 32'h08100007;
data[9'd24] <= 32'h200c4000;
data[9'd25] <= 32'h000c6400;
data[9'd26] <= 32'h218c000c;
data[9'd27] <= 32'had820000;
data[9'd28] <= 32'h20100000;
data[9'd29] <= 32'h00104302;
data[9'd30] <= 32'h31080003;
data[9'd31] <= 32'h20090000;
data[9'd32] <= 32'h11090006;
data[9'd33] <= 32'h21290001;
data[9'd34] <= 32'h11090007;
data[9'd35] <= 32'h21290001;
data[9'd36] <= 32'h11090009;
data[9'd37] <= 32'h21290001;
data[9'd38] <= 32'h1109000b;
data[9'd39] <= 32'h20110100;
data[9'd40] <= 32'h304a000f;
data[9'd41] <= 32'h08100035;
data[9'd42] <= 32'h20110200;
data[9'd43] <= 32'h304a00f0;
data[9'd44] <= 32'h000a5102;
data[9'd45] <= 32'h08100035;
data[9'd46] <= 32'h20110400;
data[9'd47] <= 32'h304a0f00;
data[9'd48] <= 32'h000a5202;
data[9'd49] <= 32'h08100035;
data[9'd50] <= 32'h20110800;
data[9'd51] <= 32'h304af000;
data[9'd52] <= 32'h000a5042;
data[9'd53] <= 32'h20090000;
data[9'd54] <= 32'h1149001e;
data[9'd55] <= 32'h20090001;
data[9'd56] <= 32'h1149001e;
data[9'd57] <= 32'h20090002;
data[9'd58] <= 32'h1149001e;
data[9'd59] <= 32'h20090003;
data[9'd60] <= 32'h1149001e;
data[9'd61] <= 32'h20090004;
data[9'd62] <= 32'h1149001e;
data[9'd63] <= 32'h20090005;
data[9'd64] <= 32'h1149001e;
data[9'd65] <= 32'h20090006;
data[9'd66] <= 32'h1149001e;
data[9'd67] <= 32'h20090007;
data[9'd68] <= 32'h1149001e;
data[9'd69] <= 32'h20090008;
data[9'd70] <= 32'h1149001e;
data[9'd71] <= 32'h20090009;
data[9'd72] <= 32'h1149001e;
data[9'd73] <= 32'h2009000a;
data[9'd74] <= 32'h1149001e;
data[9'd75] <= 32'h2009000b;
data[9'd76] <= 32'h1149001e;
data[9'd77] <= 32'h2009000c;
data[9'd78] <= 32'h1149001e;
data[9'd79] <= 32'h2009000d;
data[9'd80] <= 32'h1149001e;
data[9'd81] <= 32'h2009000e;
data[9'd82] <= 32'h1149001e;
data[9'd83] <= 32'h2009000f;
data[9'd84] <= 32'h1149001e;
data[9'd85] <= 32'h200b003f;
data[9'd86] <= 32'h08100074;
data[9'd87] <= 32'h200b0006;
data[9'd88] <= 32'h08100074;
data[9'd89] <= 32'h200b005b;
data[9'd90] <= 32'h08100074;
data[9'd91] <= 32'h200b004f;
data[9'd92] <= 32'h08100074;
data[9'd93] <= 32'h200b0066;
data[9'd94] <= 32'h08100074;
data[9'd95] <= 32'h200b006d;
data[9'd96] <= 32'h08100074;
data[9'd97] <= 32'h200b007d;
data[9'd98] <= 32'h08100074;
data[9'd99] <= 32'h200b0007;
data[9'd100] <= 32'h08100074;
data[9'd101] <= 32'h200b007f;
data[9'd102] <= 32'h08100074;
data[9'd103] <= 32'h200b006f;
data[9'd104] <= 32'h08100074;
data[9'd105] <= 32'h200b0077;
data[9'd106] <= 32'h08100074;
data[9'd107] <= 32'h200b007c;
data[9'd108] <= 32'h08100074;
data[9'd109] <= 32'h200b0039;
data[9'd110] <= 32'h08100074;
data[9'd111] <= 32'h200b005e;
data[9'd112] <= 32'h08100074;
data[9'd113] <= 32'h200b0079;
data[9'd114] <= 32'h08100074;
data[9'd115] <= 32'h200b0071;
data[9'd116] <= 32'h022b9020;
data[9'd117] <= 32'h200c4000;
data[9'd118] <= 32'h000c6400;
data[9'd119] <= 32'h218c0010;
data[9'd120] <= 32'had920000;
data[9'd121] <= 32'h22100001;
data[9'd122] <= 32'h0810001d;
for (i = 9'd123; i < MEM_SIZE; i = i + 1) begin
data[i] <= 0;
end
end
endmodule |
module BranchForwarding(
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] Rw_MEM,
input wire RegWrite_MEM,
input wire Load_WB,
input wire [4:0] Rw_WB,
output wire [1:0] BrForwardingA,
output wire [1:0] BrForwardingB
);
assign BrForwardingA = rs == Rw_WB && Load_WB ? 2 :
rs == Rw_MEM && RegWrite_MEM ? 1 : 0;
assign BrForwardingB = rt == Rw_WB && Load_WB ? 2 :
rt == Rw_MEM && RegWrite_MEM ? 1 : 0;
endmodule |
module PC(clk, reset, PC_i, PC_o);
//Input Clock Signals
input reset;
input clk;
//Input PC
input [31:0] PC_i;
//Output PC
output reg [31:0] PC_o;
initial begin
PC_o <= 0;
end
always@(posedge reset or posedge clk)
begin
if(reset) begin
PC_o <= 0;
end else begin
PC_o <= PC_i;
end
end
endmodule |
module tb_vga;
reg clk_4x, clk_2x, clk;
reg reset;
reg sel_ram;
reg sel_ctl;
reg we;
reg [12:0] addr;
reg [7:0] din;
wire [7:0] ram_dout;
wire [7:0] ctl_dout;
wire [1:0] vga_r, vga_g, vga_b;
wire vga_vs, vga_hs;
// 40 MHz clock source
always
#12.5 clk_4x = ~clk_4x;
// generate 2x, 1x clocks from 4x clk
always @(posedge clk_4x)
{clk,clk_2x} <= {clk,clk_2x} + 2'b01;
// reset
initial
begin
`ifdef icarus
$dumpfile("tb_vga.vcd");
$dumpvars;
`endif
// init regs
clk_4x = 1'b0;
clk_2x = 1'b0;
clk = 1'b0;
reset = 1'b1;
sel_ram = 1'b0;
sel_ctl = 1'b0;
we = 1'b0;
addr = 13'h0000;
din = 8'h00;
// release reset
#60
@(posedge clk)
reset = 1'b0;
`ifdef icarus
// stop after 1 sec
//#40000000 $finish; // full frame
#1000000 $finish; //quicker for testing
`endif
end
// Unit under test
vga uut
(
.clk(clk),
.clk_4x(clk_4x),
.reset(reset),
.sel_ram(sel_ram),
.sel_ctl(sel_ctl),
.we(we),
.addr(addr),
.din(din),
.ram_dout(ram_dout),
.ctl_dout(ctl_dout),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.vga_vs(vga_vs),
.vga_hs(vga_hs)
);
endmodule |
module vga(
input clk, // 10MHz cpu clock
input clk_4x, // 40MHz pixel clock
input reset, // active high system reset
input sel_ram, // decoded video RAM address
input sel_ctl, // decoded video control address
input we, // write enable
input [12:0] addr, // address (8k range)
input [7:0] din, // write data
output reg [7:0] ram_dout, // RAM read data
output reg [7:0] ctl_dout, // control read data
output reg [1:0] vga_r, // 2-bit red data
vga_g, // 2-bit green data
vga_b, // 2-bit blue data
output reg vga_vs, // vertical sync
vga_hs // horizontal sync
);
// set up timing parameters for 16MHz clock rate
localparam MAX_H = 1055; // 1056 clocks/line
localparam HFP_WID = 40; // 40 clocks H Front Porch
localparam HS_WID = 128; // 128 clocks H sync pulse
localparam HBP_WID = 88; // 88 clocks H Back Porch
localparam HA_WID = 800; // 800 clocks horizontal active
localparam MAX_V = 627; // 628 lines/frame
localparam VFP_WID = 1; // 1 line V Front Porch
localparam VS_WID = 4; // 3 lines V sync pulse
localparam VBP_WID = 23; // 41 lines V Back Porch
localparam VA_WID = 600; // 600 lines vertical active
// control register and color LUT
reg [5:0] color_lut[15:0];
reg [7:0] ctrl, hires;
// write
always @(posedge clk)
if(reset)
begin
// clear control reg
ctrl <= 8'h00;
// hires color mapping
hires <= 8'hF3;
// 3-bits luma, 3-bits chroma phase, 2-bits chroma gain
color_lut[0] <= 6'b00_00_00; // black
color_lut[1] <= 6'b11_00_00; // red
color_lut[2] <= 6'b00_11_00; // green
color_lut[3] <= 6'b00_00_11; // blue
color_lut[4] <= 6'b00_11_11; // cyan
color_lut[5] <= 6'b11_00_11; // magenta
color_lut[6] <= 6'b11_11_00; // yellow
color_lut[7] <= 6'b01_01_01; // dk gray
color_lut[8] <= 6'b10_10_10; // lt gray
color_lut[9] <= 6'b11_10_11; // pink
color_lut[10] <= 6'b11_10_00; // lt org
color_lut[11] <= 6'b11_11_10; // lt yellow
color_lut[12] <= 6'b00_11_10; // lt green
color_lut[13] <= 6'b00_10_11; // lt blue
color_lut[14] <= 6'b11_01_11; // lt purple
color_lut[15] <= 6'b11_11_11; // white
end
else if((we == 1'b1) && (sel_ctl == 1'b1))
begin
if(addr[4]==1'b0)
case(addr[3:0])
4'h0: ctrl <= din;
4'h1: hires <= din;
endcase
else
color_lut[addr[3:0]] <= din[5:0];
end
// read
always @(posedge clk)
if((we == 1'b0) && (sel_ctl == 1'b1))
if(addr[4]==1'b0)
case(addr[3:0])
4'h0: ctl_dout <= ctrl;
4'h1: ctl_dout <= hires;
default: ctl_dout <= 8'h00;
endcase
else
ctl_dout <= {2'b00,color_lut[addr[3:0]]};
// break out bank select for glyph / color addressing
wire gc = ctrl[0];
wire bank = ctrl[1];
wire [1:0] mode = ctrl[3:2];
// video timing - separate H and V counters
reg [10:0] hcnt;
reg [9:0] vcnt;
reg hs, vs, ha, va;
always @(posedge clk_4x)
begin
if(reset)
begin
hcnt <= 11'd0;
vcnt <= 10'd0;
hs <= 1'b0;
vs <= 1'b0;
ha <= 1'b0;
va <= 1'b0;
end
else
begin
// counters
if(hcnt == MAX_H)
begin
// horizontal counter
hcnt <= 11'd0;
if(vcnt == MAX_V)
vcnt <= 10'd0;
else
vcnt <= vcnt + 10'd1;
// vertical sync
if(vcnt == VFP_WID)
vs <= 1'b1;
else if(vcnt == (VFP_WID + VS_WID))
vs <= 1'b0;
// vertical active
if(vcnt >= (VFP_WID + VS_WID + VBP_WID))
va <= 1'b1;
else
va <= 1'b0;
end
else
hcnt <= hcnt + 1;
// horizontal sync
if(hcnt == HFP_WID)
hs <= 1'b1;
else if(hcnt == (HFP_WID + HS_WID))
hs <= 1'b0;
// horizontal active
if(hcnt >= (HFP_WID + HS_WID + HBP_WID))
ha <= 1'b1;
else
ha <= 1'b0;
end
end
// character generator
localparam ASTART = HFP_WID + HS_WID + HBP_WID; // start of active area
localparam BK_TOP = VFP_WID + VS_WID + VBP_WID; // vertical top
// extract video character data address & ROM line
reg active; // active video
reg [2:0] pcnt; // pixel/char count
reg vload; // load video shift reg
reg hrena; // hi-res shift enable at 1/2 pixel rate
reg mrena; // med-res shift enable at 1/4 pixel rate
reg [6:0] haddr; // horizontal component of vram addr
reg [2:0] cline; // character line index
reg [6:0] vaddr; // vertical component of vram addr
always @(posedge clk_4x)
begin
if(reset)
begin
active <= 1'b0;
pcnt <= 3'b000;
vload <= 1'b0;
hrena <= 1'b0;
mrena <= 1'b0;
haddr <= 7'd0;
cline <= 3'b000;
vaddr <= 7'd0;
end
else
begin
// wait for start of active
if(active == 1'b0)
begin
if((hcnt == ASTART) && (vcnt >= BK_TOP))
begin
// reset horizontal stuff at hcnt == ASTART
active <= 1'b1; // active video
pcnt <= 3'b000;
vload <= 1'b1; // start with load
hrena <= 1'b1; // enable on 1st
mrena <= 1'b1; // enable on 1st
haddr <= 7'd0;
end
// reset vertical stuff at vcnt == 0;
if(vcnt == 0)
begin
cline <= 3'b000;
vaddr <= 7'd0;
end
end
else
begin
if(pcnt == 3'b111)
begin
// generate vload
vload <= 1'b1;
// end of line?
if(haddr == 7'd99)
begin
// shut off counting & loading
active <= 1'b0;
vload <= 1'b0;
// time to update vertical address?
if(cline == 3'b111)
vaddr <= vaddr + 7'd1;
// update character line index
cline <= cline + 3'b001;
end
// update horizontal address
haddr <= haddr + 7'd1;
end
else
vload <= 1'b0;
// always increment pixel count
pcnt <= pcnt + 3'b001;
// hrena runs at 1/2 rate
hrena <= pcnt[0];
// mrena runs at 1/4 rate
mrena <= &pcnt[1:0];
end
end
end
// pipeline control signals
reg [2:0] vload_pipe;
reg [2:0] hrena_pipe;
reg [2:0] mrena_pipe;
reg [4:0] active_pipe, hs_pipe, vs_pipe;
reg [2:0] cline_dly0, cline_dly1;
always @(posedge clk_4x)
begin
vload_pipe <= {vload_pipe[1:0],vload};
hrena_pipe <= {hrena_pipe[1:0],hrena};
mrena_pipe <= {mrena_pipe[1:0],mrena};
active_pipe <= {active_pipe[3:0],active};
hs_pipe <= {hs_pipe[3:0],hs};
vs_pipe <= {vs_pipe[3:0],vs};
cline_dly0 <= cline;
cline_dly1 <= cline_dly0;
end
wire vload_dly = vload_pipe[2];
wire hrena_dly = hrena_pipe[2];
wire mrena_dly = mrena_pipe[2];
wire active_dly = active_pipe[4];
wire hs_dly = hs_pipe[4];
wire vs_dly = vs_pipe[4];
wire [2:0] cline_dly = cline_dly1;
// one pipe delay
// mult/add horizontal and vertical addresses to make vram address
reg [12:0] char_addr;
always @(posedge clk_4x)
char_addr <= vaddr*100 + haddr;
// shift up for glyph + color
wire [13:0] vid_addr = {char_addr, 1'b0};
// sync 1/4 rate to vload for cpu access
reg [1:0] scnt;
reg cpu_mux, cpu_mux_d1;
always @(posedge clk_4x)
if(reset)
begin
scnt <= 2'b10;
cpu_mux <= 1'b0;
cpu_mux_d1 <= 1'b0;
end
else
begin
if(vload)
scnt <= 2'b00;
else
scnt <= scnt + 2'b01;
// mux timed to allow CPU access ~1/2 way thru low rate cycle
cpu_mux <= (scnt == 2'b00) ? 1'b1 : 1'b0;
cpu_mux_d1 <= cpu_mux;
end
// invert msb of cpu addr due to decoding on D/E range
wire [13:0] cpu_addr = {~addr[12],addr[11:0],gc};
// address mux selects video only for now
wire [13:0] mem_addr = cpu_mux ? cpu_addr: vid_addr;
// cpu writes to video memory only on 2nd half of CPU clock cycle
wire mem_we = sel_ram & we & cpu_mux;
// instantiated video memory
wire [7:0] raw_ram_dout;
wire [15:0] raw_ram_word;
vram_32kb uram(
.clk(clk_4x),
.we(mem_we),
.addr({bank,mem_addr}),
.din(din),
.dout_byte(raw_ram_dout),
.dout_word(raw_ram_word)
);
// hold data for full cycle for CPU
always @(posedge clk_4x)
if(cpu_mux_d1)
ram_dout <= raw_ram_dout;
// two pipe delay
// Character Generator ROM
wire [10:0] cg_addr = {raw_ram_word[7:0],cline_dly};
wire [7:0] cg_dout;
rom_cg_2kB ucgr(
.clk(clk_4x),
.addr(cg_addr),
.dout(cg_dout)
);
// pipeline character color data
reg [7:0] color_idx;
always @(posedge clk_4x)
color_idx <= raw_ram_word[15:8];
// hires 2-color graphics mode nybble select
reg [3:0] hr_dout;
always @(posedge clk_4x)
case(cline_dly[2:1])
2'b00: hr_dout <= raw_ram_word[3:0];
2'b01: hr_dout <= raw_ram_word[7:4];
2'b10: hr_dout <= raw_ram_word[11:8];
2'b11: hr_dout <= raw_ram_word[15:12];
endcase
// medres 16-color select
reg [7:0] mr_dout;
always @(posedge clk_4x)
mr_dout <= cline_dly[2] ? raw_ram_word[15:8] : raw_ram_word[7:0];
// three pipes delay
// Video Shift Register for character mode
reg [7:0] vid_shf_reg;
reg [3:0] fore, back;
always @(posedge clk_4x)
if(vload_dly)
begin
vid_shf_reg <= cg_dout;
fore <= color_idx[7:4];
back <= color_idx[3:0];
end
else
vid_shf_reg <= {vid_shf_reg[6:0],1'b0};
// Video Shift Register for hires mode runs at 1/2 pixel rate
reg [3:0] hr_shf_reg;
always @(posedge clk_4x)
if(hrena_dly)
begin
if(vload_dly)
hr_shf_reg <= hr_dout;
else
hr_shf_reg <= {hr_shf_reg[2:0],1'b0};
end
// Selector for medres mode
reg [3:0] mr_sel_reg;
always @(posedge clk_4x)
if(mrena_dly)
if(vload_dly)
mr_sel_reg <= mr_dout[3:0];
else
mr_sel_reg <= mr_dout[7:4];
// four pipes delay
// color LUT addr
reg [3:0] color_addr;
always @(*)
case(mode)
2'b00: color_addr = vid_shf_reg[7] ? fore : back;
2'b01: color_addr = hr_shf_reg[3] ? hires[7:4] : hires[3:0];
2'b10: color_addr = mr_sel_reg;
2'b11: color_addr = mr_sel_reg;
endcase
// Get color
reg [1:0] r, g, b;
always @(posedge clk_4x)
{r, g, b} <= color_lut[color_addr];
// reclock outputs
always @(posedge clk_4x)
begin
vga_r <= active_dly ? r : 2'd0;
vga_g <= active_dly ? g : 2'd0;
vga_b <= active_dly ? b : 2'd0;
vga_hs <= hs_dly;
vga_vs <= vs_dly;
end
endmodule |
module vga_6502(
input clk, // 10MHz CPU clock
input clk_4x, // 40MHz pixel clock
input reset, // high-true reset
output [1:0] vga_r, // 2-bit red data
vga_g, // 2-bit green data
vga_b, // 2-bit blue data
output vga_vs, // vertical sync
vga_hs, // horizontal sync
output reg [7:0] gpio_o, // GPIO port
input [7:0] gpio_i,
input RX, // serial RX
output TX, // serial TX
output snd_l, // left 1-bit audio output
output snd_r, // right 1-bit audio output
output snd_nmute, // audio /mute output
inout spi0_mosi, // SPI core 0
spi0_miso,
spi0_sclk,
spi0_cs0,
inout ps2_clk, // PS/2 Keyboard port
ps2_dat,
output rgb0, // LED drivers
rgb1,
rgb2,
output [3:0] tst // diagnostic
);
// The 6502
wire [15:0] CPU_AB;
reg [7:0] CPU_DI;
wire [7:0] CPU_DO;
wire CPU_WE, CPU_IRQ, CPU_RDY;
cpu_65c02 ucpu(
.clk(clk),
.reset(reset),
.AB(CPU_AB),
.DI(CPU_DI),
.DO(CPU_DO),
.WE(CPU_WE),
.IRQ(CPU_IRQ),
.NMI(1'b0),
.RDY(CPU_RDY)
);
// address decode
wire ram0_sel = (CPU_AB[15] == 1'b0) ? 1 : 0;
wire ram1_sel = ((CPU_AB[15:12] >= 4'h8)&&(CPU_AB[15:12] <= 4'hC)) ? 1 : 0;
wire video_sel = ((CPU_AB[15:12] == 4'hd)||(CPU_AB[15:12] == 4'he)) ? 1 : 0;
wire acia_sel = (CPU_AB[15:8] == 8'hf0) ? 1 : 0;
wire wb_sel = (CPU_AB[15:8] == 8'hf1) ? 1 : 0;
wire gpio_sel = (CPU_AB[15:8] == 8'hf2) ? 1 : 0;
wire led_sel = (CPU_AB[15:8] == 8'hf3) ? 1 : 0;
wire ps2_sel = (CPU_AB[15:8] == 8'hf4) ? 1 : 0;
wire snd_sel = (CPU_AB[15:8] == 8'hf5) ? 1 : 0;
wire vctl_sel = (CPU_AB[15:8] == 8'hf6) ? 1 : 0;
wire rom_sel = (CPU_AB[15:11] == 5'h1f) ? 1 : 0;
// system control and write protect bytes
reg [7:0] sysctl, ram0_wp, ram1_wp;
// 32kB RAM @ 0000-7FFF
wire [7:0] ram0_do;
ram_32kb uram0(
.clk(clk),
.sel(ram0_sel),
.we(CPU_WE),
.wp(ram0_wp),
.addr(CPU_AB[14:0]),
.din(CPU_DO),
.dout(ram0_do)
);
// 20kB RAM @ 8000-CFFF
wire [7:0] ram1_do;
ram_32kb uram1(
.clk(clk),
.sel(ram1_sel),
.we(CPU_WE),
.wp(ram1_wp),
.addr(CPU_AB[14:0]),
.din(CPU_DO),
.dout(ram1_do)
);
// 8kB Video RAM @ D000-EFFF, video control @ F600-F6FF
wire [7:0] video_do, vctl_do;
vga uvid(
.clk(clk), // system clock
.clk_4x(clk_4x), // pixel clock
.reset(reset), // system reset
.sel_ram(video_sel), // video RAM select
.sel_ctl(vctl_sel), // video control select
.we(CPU_WE), // write enable
.addr(CPU_AB[12:0]), // address
.din(CPU_DO), // data bus input
.ram_dout(video_do), // ram data bus output
.ctl_dout(vctl_do), // ctl data bus output
.vga_r(vga_r), // 2-bit red data
.vga_g(vga_g), // 2-bit green data
.vga_b(vga_b), // 2-bit blue data
.vga_vs(vga_vs), // vertical sync
.vga_hs(vga_hs) // horizontal sync
);
// 256B ACIA @ F000-F0FF
wire [7:0] acia_do;
wire acia_irq;
acia uacia(
.clk(clk), // system clock
.rst(reset), // system reset
.cs(acia_sel), // chip select
.we(CPU_WE), // write enable
.rs(CPU_AB[0]), // address
.rx(RX), // serial receive
.din(CPU_DO), // data bus input
.dout(acia_do), // data bus output
.tx(TX), // serial transmit
.irq(acia_irq) // interrupt request
);
// 256B Wishbone bus master and SB IP cores @ F100-F1FF
wire [7:0] wb_do;
wire wb_irq, wb_rdy;
system_bus usysbus(
.clk(clk), // system clock
.rst(reset), // system reset
.cs(wb_sel), // chip select
.we(CPU_WE), // write enable
.addr(CPU_AB[7:0]), // address
.din(CPU_DO), // data bus input
.dout(wb_do), // data bus output
.rdy(wb_rdy), // processor stall
.irq(wb_irq), // interrupt request
.spi0_mosi(spi0_mosi), // spi core 0 mosi
.spi0_miso(spi0_miso), // spi core 0 miso
.spi0_sclk(spi0_sclk), // spi core 0 sclk
.spi0_cs0(spi0_cs0) // spi core 0 cs
);
// combine IRQs
assign CPU_IRQ = acia_irq | wb_irq;
// combine RDYs
assign CPU_RDY = wb_rdy;
// 256B GPIO & sysctl @ F200-F2FF
reg [7:0] gpio_do;
// write
always @(posedge clk)
if(reset)
begin
gpio_o <= 8'h00;
sysctl <= 8'h00;
ram0_wp <= 8'h00;
ram1_wp <= 8'h00;
end
else if((CPU_WE == 1'b1) && (gpio_sel == 1'b1))
begin
case(CPU_AB[1:0])
2'b00: gpio_o <= CPU_DO;
2'b01: sysctl <= CPU_DO;
2'b10: ram0_wp <= CPU_DO;
2'b11: ram1_wp <= CPU_DO;
endcase
end
// read
always @(posedge clk)
if((CPU_WE == 1'b0) && (gpio_sel == 1'b1))
case(CPU_AB[1:0])
2'b00: gpio_do <= gpio_i;
2'b01: gpio_do <= sysctl;
2'b10: gpio_do <= ram0_wp;
2'b11: gpio_do <= ram1_wp;
endcase
// LED PWM controller @ F300-F3FF
wire [7:0] led_do;
led_pwm uledpwm(
.clk(clk), // system clock
.rst(reset), // system reset
.cs(led_sel), // chip select
.we(CPU_WE), // write enable
.addr(CPU_AB[3:0]), // address
.din(CPU_DO), // data bus input
.dout(led_do), // data bus output
.rgb0(rgb0), // rgb0 pin
.rgb1(rgb1), // rgb1 pin
.rgb2(rgb2) // rgb2 pin
);
// PS/2 Keyboard port @ F400 - F4FF
wire [7:0] ps2_do;
wire [3:0] ps2_diag;
ps2 ups2(
.clk(clk), // system clock
.rst(reset), // system reset
.cs(ps2_sel), // chip select
.we(CPU_WE), // write enable
.addr(CPU_AB[1:0]), // address
.din(CPU_DO), // data bus input
.dout(ps2_do), // data bus output
.diag(ps2_diag), // diagnostics
.ps2_clk(ps2_clk), // ps2 clock i/o
.ps2_dat(ps2_dat) // ps2 data i/o
);
// sound generator @ F500 - F5FF
wire [7:0] snd_do;
snd usnd(
.clk(clk), // system clock
.rst(reset), // system reset
.cs(snd_sel), // chip select
.we(CPU_WE), // write enable
.addr(CPU_AB[3:0]), // address
.din(CPU_DO), // data bus input
.dout(snd_do), // data bus output
.snd_l(snd_l), // left 1-bit DAC output
.snd_r(snd_r), // right 1-bit DAC output
.snd_nmute(snd_nmute) // audio /mute output
);
// 2kB ROM @ f800-ffff
reg [7:0] rom_mem[2047:0];
reg [7:0] rom_do;
initial
$readmemh("rom.hex",rom_mem);
always @(posedge clk)
rom_do <= rom_mem[CPU_AB[10:0]];
// data mux only updates select lines when CPU_RDY asserted
reg [9:0] mux_sel;
always @(posedge clk)
if(CPU_RDY)
mux_sel <= {rom_sel,vctl_sel,snd_sel,ps2_sel,led_sel,gpio_sel,
wb_sel,acia_sel,video_sel,ram1_sel,ram0_sel};
always @(*)
casez(mux_sel)
11'b00000000001: CPU_DI = ram0_do;
11'b0000000001z: CPU_DI = ram1_do;
11'b000000001zz: CPU_DI = video_do;
11'b00000001zzz: CPU_DI = acia_do;
11'b0000001zzzz: CPU_DI = wb_do;
11'b000001zzzzz: CPU_DI = gpio_do;
11'b00001zzzzzz: CPU_DI = led_do;
11'b0001zzzzzzz: CPU_DI = ps2_do;
11'b001zzzzzzzz: CPU_DI = snd_do;
11'b01zzzzzzzzz: CPU_DI = vctl_do;
11'b1zzzzzzzzzz: CPU_DI = rom_do;
default: CPU_DI = rom_do;
endcase
// hook up diagnostics
//assign tst[0] = clk;
//assign tst[1] = wb_sel;
//assign tst[2] = CPU_RDY;
//assign tst[3] = 1'b0;
assign tst = ps2_diag;
endmodule |
module Keyboard(
input HCLK,
input HRESETn,
input [3:0] col,
output wire [3:0] key_interrupt
);
reg [11:0] sreg0;
wire [11:0] sreg0_nxt;
reg [11:0] sreg1;
wire [11:0] sreg1_nxt;
reg [11:0] sreg2;
wire [11:0] sreg2_nxt;
reg [11:0] sreg3;
wire [11:0] sreg3_nxt;
assign sreg0_nxt = sreg0 + 1'b1;
assign sreg1_nxt = sreg1 + 1'b1;
assign sreg2_nxt = sreg2 + 1'b1;
assign sreg3_nxt = sreg3 + 1'b1;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
sreg0 <= 12'b0;
end else if(col[0]) begin
if(sreg0 != 12'hfff)
sreg0 <= sreg0_nxt;
end else
sreg0 <= 12'b0;
end
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
sreg1 <= 12'b0;
end else if(col[1]) begin
if(sreg1 != 16'hfff)
sreg1 <= sreg1_nxt;
end else
sreg1 <= 12'b0;
end
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
sreg2 <= 12'b0;
end else if(col[2]) begin
if(sreg2 != 12'hfff)
sreg2 <= sreg2_nxt;
end else
sreg2 <= 12'b0;
end
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
sreg3 <= 12'b0;
end else if(col[3]) begin
if(sreg3 != 12'hfff)
sreg3 <= sreg3_nxt;
end else
sreg3 <= 12'b0;
end
reg [3:0] key_reg;
assign key_interrupt[0] = (sreg0 != 12'hfff) & (sreg0_nxt == 12'hfff);
assign key_interrupt[1] = (sreg1 != 12'hfff) & (sreg1_nxt == 12'hfff);
assign key_interrupt[2] = (sreg2 != 12'hfff) & (sreg2_nxt == 12'hfff);
assign key_interrupt[3] = (sreg3 != 12'hfff) & (sreg3_nxt == 12'hfff);
endmodule |
module CortexM0_SoC_vlg_tst();
reg clk;
reg RSTn;
CortexM0_SoC i1 (
.clk(clk),
.RSTn(RSTn)
);
initial begin
clk = 0;
RSTn=0;
#100
RSTn=1;
end
always begin
#10 clk = ~clk;
end
endmodule |
module GPIO (
input outEn,
input clk,
input RSTn,
input [7:0] oData,
output[7:0] iData,
inout[7:0] ioPin
);
reg [7:0] tmp;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) tmp <= 8'd0;
else tmp <= ioPin;
end
assign iData = tmp;
assign ioPin = outEn ? oData : 8'bzzzzzzzz;
endmodule |
module AHBlite_Interconnect(
// CLK & RST
input wire HCLK,
input wire HRESETn,
// CORE SIDE
input wire [31:0] HADDR,
input wire [2:0] HBURST,
input wire HMASTLOCK,
input wire [3:0] HPROT,
input wire [2:0] HSIZE,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
output wire HREADY,
output wire [31:0] HRDATA,
output wire HRESP,
// Peripheral 0
output wire HSEL_P0,
output wire [31:0] HADDR_P0,
output wire [2:0] HBURST_P0,
output wire HMASTLOCK_P0,
output wire [3:0] HPROT_P0,
output wire [2:0] HSIZE_P0,
output wire [1:0] HTRANS_P0,
output wire [31:0] HWDATA_P0,
output wire HWRITE_P0,
output wire HREADY_P0,
input wire HREADYOUT_P0,
input wire [31:0] HRDATA_P0,
input wire HRESP_P0,
// Peripheral 1
output wire HSEL_P1,
output wire [31:0] HADDR_P1,
output wire [2:0] HBURST_P1,
output wire HMASTLOCK_P1,
output wire [3:0] HPROT_P1,
output wire [2:0] HSIZE_P1,
output wire [1:0] HTRANS_P1,
output wire [31:0] HWDATA_P1,
output wire HWRITE_P1,
output wire HREADY_P1,
input wire HREADYOUT_P1,
input wire [31:0] HRDATA_P1,
input wire HRESP_P1,
// Peripheral 2
output wire HSEL_P2,
output wire [31:0] HADDR_P2,
output wire [2:0] HBURST_P2,
output wire HMASTLOCK_P2,
output wire [3:0] HPROT_P2,
output wire [2:0] HSIZE_P2,
output wire [1:0] HTRANS_P2,
output wire [31:0] HWDATA_P2,
output wire HWRITE_P2,
output wire HREADY_P2,
input wire HREADYOUT_P2,
input wire [31:0] HRDATA_P2,
input wire HRESP_P2,
// Peripheral 3
output wire HSEL_P3,
output wire [31:0] HADDR_P3,
output wire [2:0] HBURST_P3,
output wire HMASTLOCK_P3,
output wire [3:0] HPROT_P3,
output wire [2:0] HSIZE_P3,
output wire [1:0] HTRANS_P3,
output wire [31:0] HWDATA_P3,
output wire HWRITE_P3,
output wire HREADY_P3,
input wire HREADYOUT_P3,
input wire [31:0] HRDATA_P3,
input wire HRESP_P3,
// Peripheral 4
output wire HSEL_P4,
output wire [31:0] HADDR_P4,
output wire [2:0] HBURST_P4,
output wire HMASTLOCK_P4,
output wire [3:0] HPROT_P4,
output wire [2:0] HSIZE_P4,
output wire [1:0] HTRANS_P4,
output wire [31:0] HWDATA_P4,
output wire HWRITE_P4,
output wire HREADY_P4,
input wire HREADYOUT_P4,
input wire [31:0] HRDATA_P4,
input wire HRESP_P4
);
// Public signals--------------------------------
//-----------------------------------------------
// HADDR
assign HADDR_P0 = HADDR;
assign HADDR_P1 = HADDR;
assign HADDR_P2 = HADDR;
assign HADDR_P3 = HADDR;
assign HADDR_P4 = HADDR;
// HBURST
assign HBURST_P0 = HBURST;
assign HBURST_P1 = HBURST;
assign HBURST_P2 = HBURST;
assign HBURST_P3 = HBURST;
assign HBURST_P4 = HBURST;
// HMASTLOCK
assign HMASTLOCK_P0 = HMASTLOCK;
assign HMASTLOCK_P1 = HMASTLOCK;
assign HMASTLOCK_P2 = HMASTLOCK;
assign HMASTLOCK_P3 = HMASTLOCK;
assign HMASTLOCK_P4 = HMASTLOCK;
// HPROT
assign HPROT_P0 = HPROT;
assign HPROT_P1 = HPROT;
assign HPROT_P2 = HPROT;
assign HPROT_P3 = HPROT;
assign HPROT_P4 = HPROT;
// HSIZE
assign HSIZE_P0 = HSIZE;
assign HSIZE_P1 = HSIZE;
assign HSIZE_P2 = HSIZE;
assign HSIZE_P3 = HSIZE;
assign HSIZE_P4 = HSIZE;
// HTRANS
assign HTRANS_P0 = HTRANS;
assign HTRANS_P1 = HTRANS;
assign HTRANS_P2 = HTRANS;
assign HTRANS_P3 = HTRANS;
assign HTRANS_P4 = HTRANS;
// HWDATA
assign HWDATA_P0 = HWDATA;
assign HWDATA_P1 = HWDATA;
assign HWDATA_P2 = HWDATA;
assign HWDATA_P3 = HWDATA;
assign HWDATA_P4 = HWDATA;
// HWRITE
assign HWRITE_P0 = HWRITE;
assign HWRITE_P1 = HWRITE;
assign HWRITE_P2 = HWRITE;
assign HWRITE_P3 = HWRITE;
assign HWRITE_P4 = HWRITE;
// HREADY
assign HREADY_P0 = HREADY;
assign HREADY_P1 = HREADY;
assign HREADY_P2 = HREADY;
assign HREADY_P3 = HREADY;
assign HREADY_P4 = HREADY;
// Decoder---------------------------------------
//-----------------------------------------------
AHBlite_Decoder Decoder(
.HADDR (HADDR),
.P0_HSEL (HSEL_P0),
.P1_HSEL (HSEL_P1),
.P2_HSEL (HSEL_P2),
.P3_HSEL (HSEL_P3),
.P4_HSEL (HSEL_P4)
);
// Slave MUX-------------------------------------
//-----------------------------------------------
AHBlite_SlaveMUX SlaveMUX(
// CLOCK & RST
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
//P0
.P0_HSEL (HSEL_P0),
.P0_HREADYOUT (HREADYOUT_P0),
.P0_HRESP (HRESP_P0),
.P0_HRDATA (HRDATA_P0),
//P1
.P1_HSEL (HSEL_P1),
.P1_HREADYOUT (HREADYOUT_P1),
.P1_HRESP (HRESP_P1),
.P1_HRDATA (HRDATA_P1),
//P2
.P2_HSEL (HSEL_P2),
.P2_HREADYOUT (HREADYOUT_P2),
.P2_HRESP (HRESP_P2),
.P2_HRDATA (HRDATA_P2),
//P3
.P3_HSEL (HSEL_P3),
.P3_HREADYOUT (HREADYOUT_P3),
.P3_HRESP (HRESP_P3),
.P3_HRDATA (HRDATA_P3),
//P4
.P4_HSEL (HSEL_P4),
.P4_HREADYOUT (HREADYOUT_P4),
.P4_HRESP (HRESP_P4),
.P4_HRDATA (HRDATA_P4),
.HREADYOUT (HREADY),
.HRESP (HRESP),
.HRDATA (HRDATA)
);
endmodule |
module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] doutb
);
(* ram_style="block" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("G:/workspace-windows/M0_task/Task1/keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
doutb <= mem[addrb];
end
endmodule |
module AHBlite_SlaveMUX (
input HCLK,
input HRESETn,
input HREADY,
//port 0
input P0_HSEL,
input P0_HREADYOUT,
input P0_HRESP,
input [31:0] P0_HRDATA,
//port 1
input P1_HSEL,
input P1_HREADYOUT,
input P1_HRESP,
input [31:0] P1_HRDATA,
//port 2
input P2_HSEL,
input P2_HREADYOUT,
input P2_HRESP,
input [31:0] P2_HRDATA,
//port 3
input P3_HSEL,
input P3_HREADYOUT,
input P3_HRESP,
input [31:0] P3_HRDATA,
//port 4
input P4_HSEL,
input P4_HREADYOUT,
input P4_HRESP,
input [31:0] P4_HRDATA,
//output
output wire HREADYOUT,
output wire HRESP,
output wire [31:0] HRDATA
);
//reg the hsel
reg [4:0] hsel_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) hsel_reg <= 5'b00000;
else if(HREADY) hsel_reg <= {P0_HSEL,P1_HSEL,P2_HSEL,P3_HSEL,P4_HSEL};
end
//hready mux
reg hready_mux;
always@(*) begin
case(hsel_reg)
5'b00001 : begin hready_mux = P4_HREADYOUT;end
5'b00010 : begin hready_mux = P3_HREADYOUT;end
5'b00100 : begin hready_mux = P2_HREADYOUT;end
5'b01000 : begin hready_mux = P1_HREADYOUT;end
5'b10000 : begin hready_mux = P0_HREADYOUT;end
default : begin hready_mux = 1'b1;end
endcase
end
assign HREADYOUT = hready_mux;
//hresp mux
reg hresp_mux;
always@(*) begin
case(hsel_reg)
5'b00001 : begin hresp_mux = P4_HRESP;end
5'b00010 : begin hresp_mux = P3_HRESP;end
5'b00100 : begin hresp_mux = P2_HRESP;end
5'b01000 : begin hresp_mux = P1_HRESP;end
5'b10000 : begin hresp_mux = P0_HRESP;end
default : begin hresp_mux = 1'b0;end
endcase
end
assign HRESP = hresp_mux;
//hrdata mux
reg [31:0] hrdata_mux;
always@(*) begin
case(hsel_reg)
5'b00001 : begin hrdata_mux = P4_HRDATA;end
5'b00010 : begin hrdata_mux = P3_HRDATA;end
5'b00100 : begin hrdata_mux = P2_HRDATA;end
5'b01000 : begin hrdata_mux = P1_HRDATA;end
5'b10000 : begin hrdata_mux = P0_HRDATA;end
default : begin hrdata_mux = 32'b0;end
endcase
end
assign HRDATA = hrdata_mux;
endmodule |
module AHBlite_Block_RAM #(
parameter ADDR_WIDTH = 14)(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [1:0] HRESP,
output wire [ADDR_WIDTH-1:0] BRAM_RDADDR,
output wire [ADDR_WIDTH-1:0] BRAM_WRADDR,
input wire [31:0] BRAM_RDATA,
output wire [31:0] BRAM_WDATA,
output wire [3:0] BRAM_WRITE
);
assign HRESP = 2'b0;
assign HRDATA = BRAM_RDATA;
wire trans_en;
assign trans_en = HSEL & HTRANS[1];
wire write_en;
assign write_en = trans_en & HWRITE;
wire read_en;
assign read_en = trans_en & (~HWRITE);
reg [3:0] size_dec;
always@(*) begin
case({HADDR[1:0],HSIZE[1:0]})
4'h0 : size_dec = 4'h1;
4'h1 : size_dec = 4'h3;
4'h2 : size_dec = 4'hf;
4'h4 : size_dec = 4'h2;
4'h8 : size_dec = 4'h4;
4'h9 : size_dec = 4'hc;
4'hc : size_dec = 4'h8;
default : size_dec = 4'h0;
endcase
end
reg [3:0] size_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) size_reg <= 0;
else if(write_en & HREADY) size_reg <= size_dec;
end
reg [ADDR_WIDTH-1:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 0;
else if(trans_en & HREADY) addr_reg <= HADDR[(ADDR_WIDTH+1):2];
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(HREADY) wr_en_reg <= write_en;
else wr_en_reg <= 1'b0;
end
assign BRAM_RDADDR = HADDR[(ADDR_WIDTH+1):2];
assign BRAM_WRADDR = addr_reg;
assign HREADYOUT = 1'b1;
assign BRAM_WRITE = wr_en_reg ? size_reg : 4'h0;
assign BRAM_WDATA = HWDATA;
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port1_en = 0,
/************************/
/*WaterLight enable parameter*/
parameter Port2_en = 0,
/************************/
/*UART enable parameter*/
parameter Port3_en=0,
/************************/
/*GPIO enable parameter*/
parameter Port4_en=0
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P4_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'd0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = 1'd0;
/***********************************/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = 1'b0;
/***********************************/
//0x40000028 OUT ENABLE
//0X40000024 IN DATA
//0X40000020 OUT DATA
/*Insert GPIO decoder code there*/
assign P4_HSEL = 1'd0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = 1'b0;
/***********************************/
endmodule |
module AHBlite_GPIO(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output wire outEn,
output wire [7:0] oData,
input wire [7:0] iData
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
wire read_en;
assign read_en=HSEL&HTRANS[1]&(~HWRITE)&HREADY;
reg [3:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 4'h0;
else if(read_en || write_en) addr_reg <= HADDR[3:0];
end
reg rd_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) rd_en_reg <= 1'b0;
else if(read_en) rd_en_reg <= 1'b1;
else rd_en_reg <= 1'b0;
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
// always@(*) begin
// if(rd_en_reg) begin
// if(addr_reg == 4'h4) HRDATA <= {24'b0,iData};
// else HRDATA <= 32'd0;
// end
// else HRDATA <= 32'd0;
// end]
assign HRDATA = (rd_en_reg & (addr_reg == 4'h4)) ? {24'd0,iData} : 32'd0;
reg [7:0] oData_reg;
reg outEn_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) begin
oData_reg <= 8'd0;
outEn_reg <= 1'd0;
end
else if(wr_en_reg & addr_reg == 4'h0) oData_reg <= HWDATA[7:0];
else if(wr_en_reg & addr_reg == 4'h8) outEn_reg <= HWDATA[0];
end
assign oData = oData_reg;
assign outEn = outEn_reg;
endmodule |
module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
// output wire [7:0] LED,
// output wire LEDclk,
inout wire [7:0] ioPin
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
wire [31:0] IRQ;
wire interrupt_UART;
assign IRQ = 32'b0;
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b0),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
wire HSEL_P4;
wire [31:0] HADDR_P4;
wire [2:0] HBURST_P4;
wire HMASTLOCK_P4;
wire [3:0] HPROT_P4;
wire [2:0] HSIZE_P4;
wire [1:0] HTRANS_P4;
wire [31:0] HWDATA_P4;
wire HWRITE_P4;
wire HREADY_P4;
wire HREADYOUT_P4;
wire [31:0] HRDATA_P4;
wire HRESP_P4;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3),
// P4
.HSEL_P4 (HSEL_P4),
.HADDR_P4 (HADDR_P4),
.HBURST_P4 (HBURST_P4),
.HMASTLOCK_P4 (HMASTLOCK_P4),
.HPROT_P4 (HPROT_P4),
.HSIZE_P4 (HSIZE_P4),
.HTRANS_P4 (HTRANS_P4),
.HWDATA_P4 (HWDATA_P4),
.HWRITE_P4 (HWRITE_P4),
.HREADY_P4 (HREADY_P4),
.HREADYOUT_P4 (HREADYOUT_P4),
.HRDATA_P4 (HRDATA_P4),
.HRESP_P4 (HRESP_P4)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
//---------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (/*Port 1*/),
.HADDR (/*Port 1*/),
.HPROT (/*Port 1*/),
.HSIZE (/*Port 1*/),
.HTRANS (/*Port 1*/),
.HWDATA (/*Port 1*/),
.HWRITE (/*Port 1*/),
.HRDATA (/*Port 1*/),
.HREADY (/*Port 1*/),
.HREADYOUT (/*Port 1*/),
.HRESP (/*Port 1*/),
.BRAM_ADDR (RAMDATA_ADDR),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB GPIO
//------------------------------------------------------------------------------
wire [7:0] oData;
wire [7:0] iData;
wire outEn;
AHBlite_GPIO GPIO_Interface(
/* Connect to Interconnect Port 4 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (/*Port 4*/),
.HADDR (/*Port 4*/),
.HPROT (/*Port 4*/),
.HSIZE (/*Port 4*/),
.HTRANS (/*Port 4*/),
.HWDATA (/*Port 4*/),
.HWRITE (/*Port 4*/),
.HRDATA (/*Port 4*/),
.HREADY (/*Port 4*/),
.HREADYOUT (/*Port 4*/),
.HRESP (/*Port 4*/),
.outEn (outEn),
.oData (oData),
.iData (iData)
/**********************************/
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
//------------------------------------------------------------------------------
// WaterLight
//------------------------------------------------------------------------------
// WaterLight WaterLight(
// .WaterLight_mode(WaterLight_mode),
// .WaterLight_speed(WaterLight_speed),
// .clk(clk),
// .RSTn(cpuresetn),
// .LED(LED),
// .LEDclk(LEDclk)
// );
//------------------------------------------------------------------------------
// GPIO
//------------------------------------------------------------------------------
GPIO GPIO(
.outEn(outEn),
.oData(oData),
.iData(iData),
.clk(clk),
.RSTn(cpuresetn),
.ioPin(ioPin)
);
endmodule |
module WaterLight(
input [7:0] WaterLight_mode,
input [31:0] WaterLight_speed,
input clk,
input RSTn,
output reg [7:0] LED,
output wire LEDclk
);
//------------------------------------------------------
// PWM
//------------------------------------------------------
reg [31:0] pwm_cnt;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) pwm_cnt <= 32'b0;
else if(pwm_cnt == WaterLight_speed) pwm_cnt <= 32'b0;
else pwm_cnt <= pwm_cnt + 1'b1;
end
reg light_clk;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) light_clk <= 1'b0;
else if(pwm_cnt == WaterLight_speed) light_clk <= ~light_clk;
end
assign LEDclk = light_clk;
//------------------------------------------------------
// LEFT MODE
//------------------------------------------------------
reg [7:0] mode1;
always@(posedge light_clk or negedge RSTn) begin
if(~RSTn) mode1 <= 8'h01;
else begin
case(mode1)
8'h01 : mode1 <= 8'h02;
8'h02 : mode1 <= 8'h04;
8'h04 : mode1 <= 8'h08;
8'h08 : mode1 <= 8'h10;
8'h10 : mode1 <= 8'h20;
8'h20 : mode1 <= 8'h40;
8'h40 : mode1 <= 8'h80;
default : mode1 <= 8'h01;
endcase
end
end
//------------------------------------------------------
// RIGHT MODE
//------------------------------------------------------
reg [7:0] mode2;
always@(posedge light_clk or negedge RSTn) begin
if(~RSTn) mode2 <= 8'h80;
else begin
case(mode2)
8'h80 : mode2 <= 8'h40;
8'h40 : mode2 <= 8'h20;
8'h20 : mode2 <= 8'h10;
8'h10 : mode2 <= 8'h08;
8'h08 : mode2 <= 8'h04;
8'h04 : mode2 <= 8'h02;
8'h02 : mode2 <= 8'h01;
default : mode2 <= 8'h80;
endcase
end
end
//------------------------------------------------------
// FLASH MODE
//------------------------------------------------------
wire [7:0] mode3;
assign mode3 = (light_clk == 1'b0) ? 8'h00 : 8'hff;
//------------------------------------------------------
// OUTPUT MUX
//------------------------------------------------------
endmodule |
module AHBlite_WaterLight(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output reg [7:0] WaterLight_mode,
output reg [31:0] WaterLight_speed
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 1'b0;
else if(HSEL & HREADY & HTRANS[1]) addr_reg <= HADDR[2];
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always@(posedge HCLK) begin
if(~HRESETn) begin
WaterLight_mode <= 8'h00;
WaterLight_speed <= 32'h00000000;
end else if(wr_en_reg && HREADY) begin
if(~addr_reg)
WaterLight_mode <= HWDATA[7:0];
else
WaterLight_speed <= HWDATA;
end
end
assign HRDATA = (addr_reg) ? WaterLight_speed : {24'b0,WaterLight_mode};
endmodule |
module AHBlite_Interconnect(
// CLK & RST
input wire HCLK,
input wire HRESETn,
// CORE SIDE
input wire [31:0] HADDR,
input wire [2:0] HBURST,
input wire HMASTLOCK,
input wire [3:0] HPROT,
input wire [2:0] HSIZE,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
output wire HREADY,
output wire [31:0] HRDATA,
output wire HRESP,
// Peripheral 0
output wire HSEL_P0,
output wire [31:0] HADDR_P0,
output wire [2:0] HBURST_P0,
output wire HMASTLOCK_P0,
output wire [3:0] HPROT_P0,
output wire [2:0] HSIZE_P0,
output wire [1:0] HTRANS_P0,
output wire [31:0] HWDATA_P0,
output wire HWRITE_P0,
output wire HREADY_P0,
input wire HREADYOUT_P0,
input wire [31:0] HRDATA_P0,
input wire HRESP_P0,
// Peripheral 1
output wire HSEL_P1,
output wire [31:0] HADDR_P1,
output wire [2:0] HBURST_P1,
output wire HMASTLOCK_P1,
output wire [3:0] HPROT_P1,
output wire [2:0] HSIZE_P1,
output wire [1:0] HTRANS_P1,
output wire [31:0] HWDATA_P1,
output wire HWRITE_P1,
output wire HREADY_P1,
input wire HREADYOUT_P1,
input wire [31:0] HRDATA_P1,
input wire HRESP_P1,
// Peripheral 2
output wire HSEL_P2,
output wire [31:0] HADDR_P2,
output wire [2:0] HBURST_P2,
output wire HMASTLOCK_P2,
output wire [3:0] HPROT_P2,
output wire [2:0] HSIZE_P2,
output wire [1:0] HTRANS_P2,
output wire [31:0] HWDATA_P2,
output wire HWRITE_P2,
output wire HREADY_P2,
input wire HREADYOUT_P2,
input wire [31:0] HRDATA_P2,
input wire HRESP_P2,
// Peripheral 3
output wire HSEL_P3,
output wire [31:0] HADDR_P3,
output wire [2:0] HBURST_P3,
output wire HMASTLOCK_P3,
output wire [3:0] HPROT_P3,
output wire [2:0] HSIZE_P3,
output wire [1:0] HTRANS_P3,
output wire [31:0] HWDATA_P3,
output wire HWRITE_P3,
output wire HREADY_P3,
input wire HREADYOUT_P3,
input wire [31:0] HRDATA_P3,
input wire HRESP_P3
);
// Public signals--------------------------------
//-----------------------------------------------
// HADDR
assign HADDR_P0 = HADDR;
assign HADDR_P1 = HADDR;
assign HADDR_P2 = HADDR;
assign HADDR_P3 = HADDR;
// HBURST
assign HBURST_P0 = HBURST;
assign HBURST_P1 = HBURST;
assign HBURST_P2 = HBURST;
assign HBURST_P3 = HBURST;
// HMASTLOCK
assign HMASTLOCK_P0 = HMASTLOCK;
assign HMASTLOCK_P1 = HMASTLOCK;
assign HMASTLOCK_P2 = HMASTLOCK;
assign HMASTLOCK_P3 = HMASTLOCK;
// HPROT
assign HPROT_P0 = HPROT;
assign HPROT_P1 = HPROT;
assign HPROT_P2 = HPROT;
assign HPROT_P3 = HPROT;
// HSIZE
assign HSIZE_P0 = HSIZE;
assign HSIZE_P1 = HSIZE;
assign HSIZE_P2 = HSIZE;
assign HSIZE_P3 = HSIZE;
// HTRANS
assign HTRANS_P0 = HTRANS;
assign HTRANS_P1 = HTRANS;
assign HTRANS_P2 = HTRANS;
assign HTRANS_P3 = HTRANS;
// HWDATA
assign HWDATA_P0 = HWDATA;
assign HWDATA_P1 = HWDATA;
assign HWDATA_P2 = HWDATA;
assign HWDATA_P3 = HWDATA;
// HWRITE
assign HWRITE_P0 = HWRITE;
assign HWRITE_P1 = HWRITE;
assign HWRITE_P2 = HWRITE;
assign HWRITE_P3 = HWRITE;
// HREADY
assign HREADY_P0 = HREADY;
assign HREADY_P1 = HREADY;
assign HREADY_P2 = HREADY;
assign HREADY_P3 = HREADY;
// Decoder---------------------------------------
//-----------------------------------------------
AHBlite_Decoder Decoder(
.HADDR (HADDR),
.P0_HSEL (HSEL_P0),
.P1_HSEL (HSEL_P1),
.P2_HSEL (HSEL_P2),
.P3_HSEL (HSEL_P3)
);
// Slave MUX-------------------------------------
//-----------------------------------------------
AHBlite_SlaveMUX SlaveMUX(
// CLOCK & RST
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
//P0
.P0_HSEL (HSEL_P0),
.P0_HREADYOUT (HREADYOUT_P0),
.P0_HRESP (HRESP_P0),
.P0_HRDATA (HRDATA_P0),
//P1
.P1_HSEL (HSEL_P1),
.P1_HREADYOUT (HREADYOUT_P1),
.P1_HRESP (HRESP_P1),
.P1_HRDATA (HRDATA_P1),
//P2
.P2_HSEL (HSEL_P2),
.P2_HREADYOUT (HREADYOUT_P2),
.P2_HRESP (HRESP_P2),
.P2_HRDATA (HRDATA_P2),
//P3
.P3_HSEL (HSEL_P3),
.P3_HREADYOUT (HREADYOUT_P3),
.P3_HRESP (HRESP_P3),
.P3_HRDATA (HRDATA_P3),
.HREADYOUT (HREADY),
.HRESP (HRESP),
.HRDATA (HRDATA)
);
endmodule |
module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] doutb
);
(* ram_style="block" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("C:/Users/range/Desktop/CortexM0_SoC_cd/Task2/keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
doutb <= mem[addrb];
end
endmodule |
module AHBlite_SlaveMUX (
input HCLK,
input HRESETn,
input HREADY,
//port 0
input P0_HSEL,
input P0_HREADYOUT,
input P0_HRESP,
input [31:0] P0_HRDATA,
//port 1
input P1_HSEL,
input P1_HREADYOUT,
input P1_HRESP,
input [31:0] P1_HRDATA,
//port 2
input P2_HSEL,
input P2_HREADYOUT,
input P2_HRESP,
input [31:0] P2_HRDATA,
//port 3
input P3_HSEL,
input P3_HREADYOUT,
input P3_HRESP,
input [31:0] P3_HRDATA,
//output
output wire HREADYOUT,
output wire HRESP,
output wire [31:0] HRDATA
);
//reg the hsel
reg [3:0] hsel_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) hsel_reg <= 4'b0000;
else if(HREADY) hsel_reg <= {P0_HSEL,P1_HSEL,P2_HSEL,P3_HSEL};
end
//hready mux
reg hready_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hready_mux = P3_HREADYOUT;end
4'b0010 : begin hready_mux = P2_HREADYOUT;end
4'b0100 : begin hready_mux = P1_HREADYOUT;end
4'b1000 : begin hready_mux = P0_HREADYOUT;end
default : begin hready_mux = 1'b1;end
endcase
end
assign HREADYOUT = hready_mux;
//hresp mux
reg hresp_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hresp_mux = P3_HRESP;end
4'b0010 : begin hresp_mux = P2_HRESP;end
4'b0100 : begin hresp_mux = P1_HRESP;end
4'b1000 : begin hresp_mux = P0_HRESP;end
default : begin hresp_mux = 1'b0;end
endcase
end
assign HRESP = hresp_mux;
//hrdata mux
reg [31:0] hrdata_mux;
always@(*) begin
case(hsel_reg)
4'b0001 : begin hrdata_mux = P3_HRDATA;end
4'b0010 : begin hrdata_mux = P2_HRDATA;end
4'b0100 : begin hrdata_mux = P1_HRDATA;end
4'b1000 : begin hrdata_mux = P0_HRDATA;end
default : begin hrdata_mux = 32'b0;end
endcase
end
assign HRDATA = hrdata_mux;
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*WaterLight enable parameter*/
parameter Port1_en = 0,
/************************/
/*RAMDATA enable parameter*/
parameter Port2_en = 0,
/************************/
/*UART enable parameter*/
parameter Port3_en=0
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = 1'b0;
/***********************************/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = 1'b0;
/***********************************/
endmodule |
module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
output wire [7:0] LED,
output wire LEDclk
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
wire [31:0] IRQ;
wire interrupt_UART;
assign IRQ = 32'b0;
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b0),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB WaterLight
//------------------------------------------------------------------------------
wire [7:0] WaterLight_mode;
wire [31:0] WaterLight_speed;
AHBlite_WaterLight WaterLight_Interface(
/* Connect to Interconnect Port 2 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (/*Port 2*/),
.HADDR (/*Port 2*/),
.HPROT (/*Port 2*/),
.HSIZE (/*Port 2*/),
.HTRANS (/*Port 2*/),
.HWDATA (/*Port 2*/),
.HWRITE (/*Port 2*/),
.HRDATA (/*Port 2*/),
.HREADY (/*Port 2*/),
.HREADYOUT (/*Port 2*/),
.HRESP (/*Port 2*/),
.WaterLight_mode (WaterLight_mode),
.WaterLight_speed (WaterLight_speed)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (/*Port 1*/),
.HADDR (/*Port 1*/),
.HPROT (/*Port 1*/),
.HSIZE (/*Port 1*/),
.HTRANS (/*Port 1*/),
.HWDATA (/*Port 1*/),
.HWRITE (/*Port 1*/),
.HRDATA (/*Port 1*/),
.HREADY (/*Port 1*/),
.HREADYOUT (/*Port 1*/),
.HRESP (/*Port 1*/),
.BRAM_WRADDR (RAMDATA_WADDR),
.BRAM_RDADDR (RAMDATA_RADDR),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
//------------------------------------------------------------------------------
// WaterLight
//------------------------------------------------------------------------------
WaterLight WaterLight(
.WaterLight_mode(WaterLight_mode),
.WaterLight_speed(WaterLight_speed),
.clk(clk),
.RSTn(cpuresetn),
.LED(LED),
.LEDclk(LEDclk)
);
endmodule |
module CortexM0_SoC_vlg_tst();
reg clk;
reg RSTn;
reg[3:0] col;
CortexM0_SoC i1 (
.clk(clk),
.RSTn(RSTn),
.col(col)
);
initial begin
clk = 0;
RSTn=0;
#100
RSTn=1;
#100
col = 4'b0001;
#100000
col = 4'b0000;
end
always begin
#5 clk = ~clk;
end
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port1_en = 1,
/************************/
/*WaterLight enable parameter*/
parameter Port2_en = 1,
/************************/
/*UART enable parameter*/
parameter Port3_en=0,
/************************/
/*GPIO enable parameter*/
parameter Port4_en=0
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P4_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'd0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = (HADDR[31:4] == 28'h4000000) ? Port2_en : 1'd0;
/***********************************/
//0X40000010 UART RX DATA
//0X40000014 UART TX STATE
//0X40000018 UART TX DATA
/*Insert UART decoder code there*/
assign P3_HSEL = 1'b0;
/***********************************/
//0x40000028 OUT ENABLE
//0X40000024 IN DATA
//0X40000020 OUT DATA
/*Insert GPIO decoder code there*/
assign P4_HSEL = 1'd0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
endmodule |
module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
output wire [7:0] LED,
output wire LEDclk,
input wire [3:0] col,
output wire [3:0] row
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
assign row = 4'b1110;
wire [3:0] key_interrupt;
Keyboard kb(
.HCLK(clk),
.HRESETn(RSTn),
.col(col),
.key_interrupt(key_interrupt)
);
wire [31:0] IRQ;
/*Connect the IRQ with keyboard*/
assign IRQ = 32'b0;
/***************************/
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b0),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB WaterLight
//------------------------------------------------------------------------------
wire [7:0] WaterLight_mode;
wire [31:0] WaterLight_speed;
AHBlite_WaterLight WaterLight_Interface(
/* Connect to Interconnect Port 2 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P2),
.HADDR (HADDR_P2),
.HPROT (HPROT_P2),
.HSIZE (HSIZE_P2),
.HTRANS (HTRANS_P2),
.HWDATA (HWDATA_P2),
.HWRITE (HWRITE_P2),
.HRDATA (HRDATA_P2),
.HREADY (HREADY_P2),
.HREADYOUT (HREADYOUT_P2),
.HRESP (HRESP_P2),
.WaterLight_mode (WaterLight_mode),
.WaterLight_speed (WaterLight_speed)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P1),
.HADDR (HADDR_P1),
.HPROT (HPROT_P1),
.HSIZE (HSIZE_P1),
.HTRANS (HTRANS_P1),
.HWDATA (HWDATA_P1),
.HWRITE (HWRITE_P1),
.HRDATA (HRDATA_P1),
.HREADY (HREADY_P1),
.HREADYOUT (HREADYOUT_P1),
.HRESP (HRESP_P1),
.BRAM_WRADDR (RAMDATA_WADDR),
.BRAM_RDADDR (RAMDATA_RADDR),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
//------------------------------------------------------------------------------
// WaterLight
//------------------------------------------------------------------------------
WaterLight WaterLight(
.WaterLight_mode(WaterLight_mode),
.WaterLight_speed(WaterLight_speed),
.clk(clk),
.RSTn(cpuresetn),
.LED(LED),
.LEDclk(LEDclk)
);
endmodule |
module UART_RX(
input clk,
input clk_uart,
input RSTn,
input RXD,
output reg [7:0] data,
output wire interrupt,
output wire bps_en
);
//shift register
reg [7:0] shift_reg;
always@(posedge clk) begin
if(~RSTn) shift_reg <= 8'hff;
else shift_reg <= {RXD,shift_reg[7:1]};
end
wire re_start;
assign re_start = (shift_reg == 8'h0f) ? 1'b1 : 1'b0;
// recive counter
reg counter_en;
reg [3:0] counter;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter_en <= 1'b0;
else if(re_start&&(~counter_en)) counter_en <= 1'b1;
else if(counter == 4'h9) counter_en <= 1'b0;
end
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter <= 4'h0;
else if(counter_en) begin
if(clk_uart) counter <= counter + 1'b1;
else if(counter == 4'h9) counter <= 4'h0;
end
end
assign bps_en = counter_en;
// RXD re
always@(posedge clk or negedge RSTn) begin
if(~RSTn) data <= 8'h00;
else if(counter_en) begin
if(clk_uart && (counter <= 4'h8)) data[counter-1] <= RXD;
end
end
//interrupt
assign interrupt = (counter == 4'h9) ? 1'b1 : 1'b0;
endmodule |
module clkuart_pwm
#( parameter BPS_PARA = 434 )
(
input bps_en,
input clk,
input RSTn,
output reg clk_uart
);
reg [12:0] cnt = 0;
always @ (posedge clk or negedge RSTn) begin
if(~RSTn) cnt <= 13'b0;
else if((cnt >= BPS_PARA-1)||(!bps_en)) cnt <= 13'b0;
else cnt <= cnt + 1'b1;
end
always @ (posedge clk or negedge RSTn) begin
if(~RSTn) clk_uart <= 1'b0;
else if(cnt == (BPS_PARA>>1)) clk_uart <= 1'b1;
else clk_uart <= 1'b0;
end
endmodule |
module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] doutb
);
(* ram_style="block" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("C:/Users/tianj/Desktop/CortexM0_SoC_Task/Task3/keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
doutb <= mem[addrb];
end
endmodule |
module AHBlite_UART(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output reg [31:0] HRDATA,
output wire HRESP,
input wire [7:0] UART_RX,
input wire state,
output wire tx_en,
output wire [7:0] UART_TX
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire read_en;
assign read_en=HSEL&HTRANS[1]&(~HWRITE)&HREADY;
wire write_en;
assign write_en=HSEL&HTRANS[1]&(HWRITE)&HREADY;
reg [3:0] addr_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) addr_reg <= 4'h0;
else if(read_en || write_en) addr_reg <= HADDR[3:0];
end
reg rd_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) rd_en_reg <= 1'b0;
else if(read_en) rd_en_reg <= 1'b1;
else rd_en_reg <= 1'b0;
end
reg wr_en_reg;
always@(posedge HCLK or negedge HRESETn) begin
if(~HRESETn) wr_en_reg <= 1'b0;
else if(write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always@(*) begin
if(rd_en_reg) begin
if(addr_reg == 4'h0) HRDATA <= {24'b0,UART_RX};
else if(addr_reg == 4'h4) HRDATA <= {31'b0,state};
else HRDATA <= 32'b0;
end else
HRDATA <= 32'b0;
end
assign tx_en = wr_en_reg ? 1'b1 : 1'b0;
assign UART_TX = wr_en_reg ? HWDATA[7:0] : 8'b0;
endmodule |
module buzzer(
input wire clk,
input wire RSTn,
input wire [7:0] mode,
output wire buzzer_o
);
reg clk0,clk1,clk2;
reg [25:0] cnt;
wire [25:0]cnt_nxt;
wire cnt_done;
assign cnt_done = cnt == 26'd50000000;
assign cnt_nxt = cnt_done ? 26'b0 : cnt + 1'b1;
always@(posedge clk or negedge RSTn) begin
if(~RSTn) cnt <= 26'b0;
else cnt <= cnt_nxt;
end
always@(posedge clk or negedge RSTn) begin
if(~RSTn) clk0 <= 1'b0;
else if(cnt_done) clk0 <= ~clk0;
end
always@(posedge clk0 or negedge RSTn) begin
if(~RSTn) clk1 <= 1'b0;
else clk1 <= ~clk1;
end
always@(posedge clk1 or negedge RSTn) begin
if(~RSTn) clk2 <= 1'b0;
else clk2 <= ~clk2;
end
assign buzzer_o = (mode[1:0] == 2'b00) ? 1'b0 : (
(mode[1:0] == 2'b01) ? clk0 : (
(mode[1:0] == 2'b10) ? clk1 : clk2));
endmodule |
module CortexM0_SoC (
input wire clk,
input wire RSTn,
inout wire SWDIO,
input wire SWCLK,
output wire [7:0] LED,
output wire LEDclk,
output wire TXD,
input wire RXD
);
//------------------------------------------------------------------------------
// DEBUG IOBUF
//------------------------------------------------------------------------------
wire SWDO;
wire SWDOEN;
wire SWDI;
assign SWDI = SWDIO;
assign SWDIO = (SWDOEN) ? SWDO : 1'bz;
//------------------------------------------------------------------------------
// Interrupt
//------------------------------------------------------------------------------
wire [31:0] IRQ;
wire interrupt_UART;
/*Connect the IRQ with UART*/
assign IRQ = 32'b0;
/***************************/
wire RXEV;
assign RXEV = 1'b0;
//------------------------------------------------------------------------------
// AHB
//------------------------------------------------------------------------------
wire [31:0] HADDR;
wire [ 2:0] HBURST;
wire HMASTLOCK;
wire [ 3:0] HPROT;
wire [ 2:0] HSIZE;
wire [ 1:0] HTRANS;
wire [31:0] HWDATA;
wire HWRITE;
wire [31:0] HRDATA;
wire HRESP;
wire HMASTER;
wire HREADY;
//------------------------------------------------------------------------------
// RESET AND DEBUG
//------------------------------------------------------------------------------
wire SYSRESETREQ;
reg cpuresetn;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) cpuresetn <= 1'b0;
else if (SYSRESETREQ) cpuresetn <= 1'b0;
else cpuresetn <= 1'b1;
end
wire CDBGPWRUPREQ;
reg CDBGPWRUPACK;
always @(posedge clk or negedge RSTn)begin
if (~RSTn) CDBGPWRUPACK <= 1'b0;
else CDBGPWRUPACK <= CDBGPWRUPREQ;
end
//------------------------------------------------------------------------------
// Instantiate Cortex-M0 processor logic level
//------------------------------------------------------------------------------
cortexm0ds_logic u_logic (
// System inputs
.FCLK (clk), //FREE running clock
.SCLK (clk), //system clock
.HCLK (clk), //AHB clock
.DCLK (clk), //Debug clock
.PORESETn (RSTn), //Power on reset
.HRESETn (cpuresetn), //AHB and System reset
.DBGRESETn (RSTn), //Debug Reset
.RSTBYPASS (1'b0), //Reset bypass
.SE (1'b0), // dummy scan enable port for synthesis
// Power management inputs
.SLEEPHOLDREQn (1'b1), // Sleep extension request from PMU
.WICENREQ (1'b0), // WIC enable request from PMU
.CDBGPWRUPACK (CDBGPWRUPACK), // Debug Power Up ACK from PMU
// Power management outputs
.CDBGPWRUPREQ (CDBGPWRUPREQ),
.SYSRESETREQ (SYSRESETREQ),
// System bus
.HADDR (HADDR[31:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HBURST (HBURST[2:0]),
.HPROT (HPROT[3:0]),
.HMASTER (HMASTER),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HRDATA (HRDATA[31:0]),
.HREADY (HREADY),
.HRESP (HRESP),
// Interrupts
.IRQ (IRQ), //Interrupt
.NMI (1'b0), //Watch dog interrupt
.IRQLATENCY (8'h0),
.ECOREVNUM (28'h0),
// Systick
.STCLKEN (1'b0),
.STCALIB (26'h0),
// Debug - JTAG or Serial wire
// Inputs
.nTRST (1'b1),
.SWDITMS (SWDI),
.SWCLKTCK (SWCLK),
.TDI (1'b0),
// Outputs
.SWDO (SWDO),
.SWDOEN (SWDOEN),
.DBGRESTART (1'b0),
// Event communication
.RXEV (RXEV), // Generate event when a DMA operation completed.
.EDBGRQ (1'b0) // multi-core synchronous halt request
);
//------------------------------------------------------------------------------
// AHBlite Interconncet
//------------------------------------------------------------------------------
wire HSEL_P0;
wire [31:0] HADDR_P0;
wire [2:0] HBURST_P0;
wire HMASTLOCK_P0;
wire [3:0] HPROT_P0;
wire [2:0] HSIZE_P0;
wire [1:0] HTRANS_P0;
wire [31:0] HWDATA_P0;
wire HWRITE_P0;
wire HREADY_P0;
wire HREADYOUT_P0;
wire [31:0] HRDATA_P0;
wire HRESP_P0;
wire HSEL_P1;
wire [31:0] HADDR_P1;
wire [2:0] HBURST_P1;
wire HMASTLOCK_P1;
wire [3:0] HPROT_P1;
wire [2:0] HSIZE_P1;
wire [1:0] HTRANS_P1;
wire [31:0] HWDATA_P1;
wire HWRITE_P1;
wire HREADY_P1;
wire HREADYOUT_P1;
wire [31:0] HRDATA_P1;
wire HRESP_P1;
wire HSEL_P2;
wire [31:0] HADDR_P2;
wire [2:0] HBURST_P2;
wire HMASTLOCK_P2;
wire [3:0] HPROT_P2;
wire [2:0] HSIZE_P2;
wire [1:0] HTRANS_P2;
wire [31:0] HWDATA_P2;
wire HWRITE_P2;
wire HREADY_P2;
wire HREADYOUT_P2;
wire [31:0] HRDATA_P2;
wire HRESP_P2;
wire HSEL_P3;
wire [31:0] HADDR_P3;
wire [2:0] HBURST_P3;
wire HMASTLOCK_P3;
wire [3:0] HPROT_P3;
wire [2:0] HSIZE_P3;
wire [1:0] HTRANS_P3;
wire [31:0] HWDATA_P3;
wire HWRITE_P3;
wire HREADY_P3;
wire HREADYOUT_P3;
wire [31:0] HRDATA_P3;
wire HRESP_P3;
AHBlite_Interconnect Interconncet(
.HCLK (clk),
.HRESETn (cpuresetn),
// CORE SIDE
.HADDR (HADDR),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HBURST (HBURST),
.HPROT (HPROT),
.HMASTLOCK (HMASTLOCK),
.HWRITE (HWRITE),
.HWDATA (HWDATA),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
// P0
.HSEL_P0 (HSEL_P0),
.HADDR_P0 (HADDR_P0),
.HBURST_P0 (HBURST_P0),
.HMASTLOCK_P0 (HMASTLOCK_P0),
.HPROT_P0 (HPROT_P0),
.HSIZE_P0 (HSIZE_P0),
.HTRANS_P0 (HTRANS_P0),
.HWDATA_P0 (HWDATA_P0),
.HWRITE_P0 (HWRITE_P0),
.HREADY_P0 (HREADY_P0),
.HREADYOUT_P0 (HREADYOUT_P0),
.HRDATA_P0 (HRDATA_P0),
.HRESP_P0 (HRESP_P0),
// P1
.HSEL_P1 (HSEL_P1),
.HADDR_P1 (HADDR_P1),
.HBURST_P1 (HBURST_P1),
.HMASTLOCK_P1 (HMASTLOCK_P1),
.HPROT_P1 (HPROT_P1),
.HSIZE_P1 (HSIZE_P1),
.HTRANS_P1 (HTRANS_P1),
.HWDATA_P1 (HWDATA_P1),
.HWRITE_P1 (HWRITE_P1),
.HREADY_P1 (HREADY_P1),
.HREADYOUT_P1 (HREADYOUT_P1),
.HRDATA_P1 (HRDATA_P1),
.HRESP_P1 (HRESP_P1),
// P2
.HSEL_P2 (HSEL_P2),
.HADDR_P2 (HADDR_P2),
.HBURST_P2 (HBURST_P2),
.HMASTLOCK_P2 (HMASTLOCK_P2),
.HPROT_P2 (HPROT_P2),
.HSIZE_P2 (HSIZE_P2),
.HTRANS_P2 (HTRANS_P2),
.HWDATA_P2 (HWDATA_P2),
.HWRITE_P2 (HWRITE_P2),
.HREADY_P2 (HREADY_P2),
.HREADYOUT_P2 (HREADYOUT_P2),
.HRDATA_P2 (HRDATA_P2),
.HRESP_P2 (HRESP_P2),
// P3
.HSEL_P3 (HSEL_P3),
.HADDR_P3 (HADDR_P3),
.HBURST_P3 (HBURST_P3),
.HMASTLOCK_P3 (HMASTLOCK_P3),
.HPROT_P3 (HPROT_P3),
.HSIZE_P3 (HSIZE_P3),
.HTRANS_P3 (HTRANS_P3),
.HWDATA_P3 (HWDATA_P3),
.HWRITE_P3 (HWRITE_P3),
.HREADY_P3 (HREADY_P3),
.HREADYOUT_P3 (HREADYOUT_P3),
.HRDATA_P3 (HRDATA_P3),
.HRESP_P3 (HRESP_P3)
);
//------------------------------------------------------------------------------
// AHB RAMCODE
//------------------------------------------------------------------------------
wire [31:0] RAMCODE_RDATA,RAMCODE_WDATA;
wire [13:0] RAMCODE_WADDR;
wire [13:0] RAMCODE_RADDR;
wire [3:0] RAMCODE_WRITE;
AHBlite_Block_RAM RAMCODE_Interface(
/* Connect to Interconnect Port 0 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P0),
.HADDR (HADDR_P0),
.HPROT (HPROT_P0),
.HSIZE (HSIZE_P0),
.HTRANS (HTRANS_P0),
.HWDATA (HWDATA_P0),
.HWRITE (HWRITE_P0),
.HRDATA (HRDATA_P0),
.HREADY (HREADY_P0),
.HREADYOUT (HREADYOUT_P0),
.HRESP (HRESP_P0),
.BRAM_WRADDR (RAMCODE_WADDR),
.BRAM_RDADDR (RAMCODE_RADDR),
.BRAM_RDATA (RAMCODE_RDATA),
.BRAM_WDATA (RAMCODE_WDATA),
.BRAM_WRITE (RAMCODE_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB WaterLight
//------------------------------------------------------------------------------
wire [7:0] WaterLight_mode;
wire [31:0] WaterLight_speed;
AHBlite_WaterLight WaterLight_Interface(
/* Connect to Interconnect Port 2 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P2),
.HADDR (HADDR_P2),
.HPROT (HPROT_P2),
.HSIZE (HSIZE_P2),
.HTRANS (HTRANS_P2),
.HWDATA (HWDATA_P2),
.HWRITE (HWRITE_P2),
.HRDATA (HRDATA_P2),
.HREADY (HREADY_P2),
.HREADYOUT (HREADYOUT_P2),
.HRESP (HRESP_P2),
.WaterLight_mode (WaterLight_mode),
.WaterLight_speed (WaterLight_speed)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB RAMDATA
//------------------------------------------------------------------------------
wire [31:0] RAMDATA_RDATA;
wire [31:0] RAMDATA_WDATA;
wire [13:0] RAMDATA_WADDR;
wire [13:0] RAMDATA_RADDR;
wire [3:0] RAMDATA_WRITE;
AHBlite_Block_RAM RAMDATA_Interface(
/* Connect to Interconnect Port 1 */
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P1),
.HADDR (HADDR_P1),
.HPROT (HPROT_P1),
.HSIZE (HSIZE_P1),
.HTRANS (HTRANS_P1),
.HWDATA (HWDATA_P1),
.HWRITE (HWRITE_P1),
.HRDATA (HRDATA_P1),
.HREADY (HREADY_P1),
.HREADYOUT (HREADYOUT_P1),
.HRESP (HRESP_P1),
.BRAM_WRADDR (RAMDATA_WADDR),
.BRAM_RDADDR (RAMDATA_RADDR),
.BRAM_WDATA (RAMDATA_WDATA),
.BRAM_RDATA (RAMDATA_RDATA),
.BRAM_WRITE (RAMDATA_WRITE)
/**********************************/
);
//------------------------------------------------------------------------------
// AHB UART
//------------------------------------------------------------------------------
wire state;
wire [7:0] UART_RX_data;
wire [7:0] UART_TX_data;
wire tx_en;
AHBlite_UART UART_Interface(
.HCLK (clk),
.HRESETn (cpuresetn),
.HSEL (HSEL_P3),
.HADDR (HADDR_P3),
.HPROT (HPROT_P3),
.HSIZE (HSIZE_P3),
.HTRANS (HTRANS_P3),
.HWDATA (HWDATA_P3),
.HWRITE (HWRITE_P3),
.HRDATA (HRDATA_P3),
.HREADY (HREADY_P3),
.HREADYOUT (HREADYOUT_P3),
.HRESP (HRESP_P3),
.UART_RX (UART_RX_data),
.state (state),
.tx_en (tx_en),
.UART_TX (UART_TX_data)
);
//------------------------------------------------------------------------------
// RAM
//------------------------------------------------------------------------------
Block_RAM RAM_CODE(
.clka (clk),
.addra (RAMCODE_WADDR),
.addrb (RAMCODE_RADDR),
.dina (RAMCODE_WDATA),
.doutb (RAMCODE_RDATA),
.wea (RAMCODE_WRITE)
);
Block_RAM RAM_DATA(
.clka (clk),
.addra (RAMDATA_WADDR),
.addrb (RAMDATA_RADDR),
.dina (RAMDATA_WDATA),
.doutb (RAMDATA_RDATA),
.wea (RAMDATA_WRITE)
);
//------------------------------------------------------------------------------
// WaterLight
//------------------------------------------------------------------------------
WaterLight WaterLight(
.WaterLight_mode(WaterLight_mode),
.WaterLight_speed(WaterLight_speed),
.clk(clk),
.RSTn(cpuresetn),
.LED(LED),
.LEDclk(LEDclk)
);
//------------------------------------------------------------------------------
// UART
//------------------------------------------------------------------------------
wire clk_uart;
wire bps_en;
wire bps_en_rx,bps_en_tx;
assign bps_en = bps_en_rx | bps_en_tx;
clkuart_pwm clkuart_pwm(
.clk(clk),
.RSTn(cpuresetn),
.clk_uart(clk_uart),
.bps_en(bps_en)
);
UART_RX UART_RX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.RXD(RXD),
.data(UART_RX_data),
.interrupt(interrupt_UART),
.bps_en(bps_en_rx)
);
UART_TX UART_TX(
.clk(clk),
.clk_uart(clk_uart),
.RSTn(cpuresetn),
.data(UART_TX_data),
.tx_en(tx_en),
.TXD(TXD),
.state(state),
.bps_en(bps_en_tx)
);
endmodule |
module UART_TX(
input clk,
input clk_uart,
input RSTn,
input [7:0] data,
input tx_en,
output reg TXD,
output wire state,
output wire bps_en
);
//FIFO 8bit-16depth
wire FIFOrd_en;
wire FIFOwr_en;
wire [7:0] FIFOdata;
wire FIFOempty;
wire FIFOfull;
FIFO FIFO(
.clock(clk),
.sclr(RSTn),
.rdreq(FIFOrd_en),
.wrreq(FIFOwr_en),
.full(FIFOfull),
.empty(FIFOempty),
.data(data),
.q(FIFOdata)
);
//FIFO write control
assign FIFOwr_en = (~FIFOfull) & tx_en;
assign state = FIFOfull;
//UART TX
reg counter_en;
reg [3:0] counter;
wire trans_finish;
assign trans_finish = (counter == 4'hb);
wire trans_start;
assign trans_start = (~FIFOempty) & (~counter_en);
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter_en <= 1'b0;
else if(trans_start) counter_en <= 1'b1;
else if(trans_finish) counter_en <= 1'b0;
end
always@(posedge clk or negedge RSTn) begin
if(~RSTn) counter <= 4'h0;
else if(counter_en) begin
if(clk_uart) counter <= counter + 1'b1;
else if(trans_finish) counter <= 4'h0;
end
end
assign bps_en = counter_en;
wire [9:0] data_formed;
assign data_formed = {1'b1,FIFOdata,1'b0};
always@(posedge clk or negedge RSTn) begin
if(~RSTn) TXD <= 1'b1;
else if(counter_en) begin
if(clk_uart && (counter <= 4'h9)) TXD <= data_formed[counter];
end else TXD <= 1'b1;
end
//FIFO read control
assign FIFOrd_en = (~FIFOempty) & trans_finish;
endmodule |
module FIFO(
input clock,
input sclr,
input rdreq, wrreq,
output reg full, empty,
input [7 : 0] data,
output [7 : 0] q
);
reg [7 : 0] mem [15 : 0];
reg [3 : 0] wp, rp;
reg w_flag, r_flag;
initial
begin
wp=0;
w_flag=0;
rp=0;
r_flag=0;
end
always @(posedge clock) begin
if (~sclr) begin
wp <= 0;
w_flag <= 0;
end else if(!full && wrreq) begin
wp<= (wp==16-1) ? 0 : wp+1;
w_flag <= (wp==16-1) ? ~w_flag : w_flag;
end
end
always @(posedge clock) begin
if(wrreq && !full)begin
mem[wp] <= data;
end
end
always @(posedge clock) begin
if (~sclr) begin
rp<=0;
r_flag <= 0;
end else if(!empty && rdreq) begin
rp<= (rp==16-1) ? 0 : rp+1;
r_flag <= (rp==16-1) ? ~r_flag : r_flag;
end
end
assign q = mem[rp];
always @(*) begin
if(wp==rp)begin
if(r_flag==w_flag)begin
full <= 0;
empty <= 1;
end else begin
full <= 1;
empty <= 0;
end
end else begin
full <= 0;
empty <= 0;
end
end
endmodule |
module Block_RAM #(
parameter ADDR_WIDTH = 14
) (
input clka,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [31:0] dina,
input [3:0] wea,
output reg [31:0] doutb
);
(* ram_style="block" *)reg [31:0] mem [(2**ADDR_WIDTH-1):0];
initial begin
$readmemh("C:/Users/range/Desktop/CortexM0_SoC/Task1/keil/code.hex",mem);
end
always@(posedge clka) begin
if(wea[0]) mem[addra][7:0] <= dina[7:0];
end
always@(posedge clka) begin
if(wea[1]) mem[addra][15:8] <= dina[15:8];
end
always@(posedge clka) begin
if(wea[2]) mem[addra][23:16] <= dina[23:16];
end
always@(posedge clka) begin
if(wea[3]) mem[addra][31:24] <= dina[31:24];
end
always@(posedge clka) begin
doutb <= mem[addrb];
end
endmodule |
module AHBlite_WaveformGenerator(
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire [31:0] HWDATA,
input wire HREADY,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
output reg wgen
);
assign HRESP = 1'b0;
assign HREADYOUT = 1'b1;
wire write_en;
assign write_en = HSEL & HTRANS[1] & HWRITE & HREADY;
reg wr_en_reg;
always @ (posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wr_en_reg <= 1'b0;
else if (write_en) wr_en_reg <= 1'b1;
else wr_en_reg <= 1'b0;
end
always @ (posedge HCLK or negedge HRESETn) begin
if (~HRESETn) wgen <= 1'b0;
else if (wr_en_reg && HREADY) wgen <= HWDATA[0];
end
assign HRDATA = {31'b0, wgen};
endmodule |
module AHBlite_Decoder
#(
/*RAMCODE enable parameter*/
parameter Port0_en = 1,
/************************/
/*WaterLight enable parameter*/
parameter Port1_en = 1,
/************************/
/*RAMDATA enable parameter*/
parameter Port2_en = 1,
/************************/
/*UART enable parameter*/
parameter Port3_en = 1
/************************/
)(
input [31:0] HADDR,
/*RAMCODE OUTPUT SELECTION SIGNAL*/
output wire P0_HSEL,
/*WaterLight OUTPUT SELECTION SIGNAL*/
output wire P1_HSEL,
/*RAMDATA OUTPUT SELECTION SIGNAL*/
output wire P2_HSEL,
/*UART OUTPUT SELECTION SIGNAL*/
output wire P3_HSEL
);
//RAMCODE-----------------------------------
//0x00000000-0x0000ffff
/*Insert RAMCODE decoder code there*/
assign P0_HSEL = (HADDR[31:16] == 16'h0000) ? Port0_en : 1'b0;
/***********************************/
//PERIPHRAL-----------------------------
//0X40000000 WaterLight MODE
//0x40000004 WaterLight SPEED
/*Insert WaterLight decoder code there*/
assign P2_HSEL = (HADDR[31:4] == 28'h4000000) ? Port2_en : 1'b0;
/***********************************/
//0X40000010 WaveformGenerator enable signal
/*Insert WaveformGenerator decoder code there*/
assign P3_HSEL = (HADDR[31:4] == 28'h4000001) ? Port3_en : 1'b0;
/***********************************/
//RAMDATA-----------------------------
//0X20000000-0X2000FFFF
/*Insert RAMDATA decoder code there*/
assign P1_HSEL = (HADDR[31:16] == 16'h2000) ? Port1_en : 1'b0;
/***********************************/
endmodule |
Subsets and Splits