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module ct_had_dbg_info(
cp0_had_debug_info,
cpuclk,
cpurst_b,
ctrl_dbgfifo_ren,
ctrl_pipefifo_ren,
ctrl_pipefifo_wen,
dbgfifo_regs_data,
had_idu_debug_id_inst_en,
had_lsu_dbg_info_en,
had_rtu_debug_retire_info_en,
idu_had_debug_info,
idu_had_id_inst0_info,
idu_had_id_inst0_vld,
idu_had_id_inst1_info,
idu_had_id_inst1_vld,
idu_had_id_inst2_info,
idu_had_id_inst2_vld,
ifu_had_debug_info,
ir_xx_pipesel_reg_sel,
ir_xx_wdata,
iu_had_debug_info,
lsu_had_debug_info,
lsu_had_st_addr,
lsu_had_st_data,
lsu_had_st_req,
mmu_had_debug_info,
pipefifo_regs_data,
pipesel_regs_data,
rtu_had_dbg_ack_info,
rtu_had_debug_info,
rtu_had_retire_inst0_info,
rtu_had_retire_inst0_vld,
rtu_had_retire_inst1_info,
rtu_had_retire_inst1_vld,
rtu_had_retire_inst2_info,
rtu_had_retire_inst2_vld,
x_dbg_ack_pc,
x_sm_xx_update_dr_en
);
// &Ports; @24
input [3 :0] cp0_had_debug_info;
input cpuclk;
input cpurst_b;
input ctrl_dbgfifo_ren;
input ctrl_pipefifo_ren;
input ctrl_pipefifo_wen;
input [49 :0] idu_had_debug_info;
input [39 :0] idu_had_id_inst0_info;
input idu_had_id_inst0_vld;
input [39 :0] idu_had_id_inst1_info;
input idu_had_id_inst1_vld;
input [39 :0] idu_had_id_inst2_info;
input idu_had_id_inst2_vld;
input [82 :0] ifu_had_debug_info;
input ir_xx_pipesel_reg_sel;
input [63 :0] ir_xx_wdata;
input [9 :0] iu_had_debug_info;
input [183:0] lsu_had_debug_info;
input [39 :0] lsu_had_st_addr;
input [63 :0] lsu_had_st_data;
input lsu_had_st_req;
input [33 :0] mmu_had_debug_info;
input rtu_had_dbg_ack_info;
input [42 :0] rtu_had_debug_info;
input [63 :0] rtu_had_retire_inst0_info;
input rtu_had_retire_inst0_vld;
input [63 :0] rtu_had_retire_inst1_info;
input rtu_had_retire_inst1_vld;
input [63 :0] rtu_had_retire_inst2_info;
input rtu_had_retire_inst2_vld;
input x_sm_xx_update_dr_en;
output [63 :0] dbgfifo_regs_data;
output had_idu_debug_id_inst_en;
output had_lsu_dbg_info_en;
output had_rtu_debug_retire_info_en;
output [63 :0] pipefifo_regs_data;
output [31 :0] pipesel_regs_data;
output x_dbg_ack_pc;
// &Regs; @25
reg dbg_ack_pc_f;
reg [2 :0] dbg_read_ptr;
reg [63 :0] dbginfo_dout;
reg [63 :0] pipefifo_din_0;
reg [63 :0] pipefifo_din_1;
reg [63 :0] pipefifo_din_2;
reg [63 :0] pipefifo_dout;
reg [2 :0] pipefifo_sel;
reg [1 :0] pipesel;
reg [4 :0] rptr;
reg [4 :0] wptr;
reg [407:0] xx_dbg_info_reg;
// &Wires; @26
wire [3 :0] cp0_had_debug_info;
wire cpuclk;
wire cpurst_b;
wire create_one;
wire create_thr;
wire create_two;
wire create_vld;
wire ctrl_dbgfifo_ren;
wire ctrl_pipefifo_ren;
wire ctrl_pipefifo_wen;
wire dbg_rptr_done;
wire [63 :0] dbgfifo_regs_data;
wire had_idu_debug_id_inst_en;
wire had_lsu_dbg_info_en;
wire had_rtu_debug_retire_info_en;
wire [49 :0] idu_had_debug_info;
wire [39 :0] idu_had_id_inst0_info;
wire idu_had_id_inst0_vld;
wire [39 :0] idu_had_id_inst1_info;
wire idu_had_id_inst1_vld;
wire [39 :0] idu_had_id_inst2_info;
wire idu_had_id_inst2_vld;
wire [2 :0] idu_pipe_vld;
wire [82 :0] ifu_had_debug_info;
wire ir_xx_pipesel_reg_sel;
wire [63 :0] ir_xx_wdata;
wire [9 :0] iu_had_debug_info;
wire [183:0] lsu_had_debug_info;
wire [39 :0] lsu_had_st_addr;
wire [63 :0] lsu_had_st_data;
wire lsu_had_st_req;
wire [2 :0] lsu_pipe_vld;
wire [33 :0] mmu_had_debug_info;
wire one_entry_left;
wire pipefifo_empty;
wire pipefifo_full;
wire [63 :0] pipefifo_regs_data;
wire [2 :0] pipefifo_wen;
wire [31 :0] pipesel_regs_data;
wire [4 :0] rptr_inc;
wire rptr_inc_1;
wire rptr_inc_2;
wire rptr_inc_3;
wire rtu_had_dbg_ack_info;
wire [42 :0] rtu_had_debug_info;
wire [63 :0] rtu_had_retire_inst0_info;
wire rtu_had_retire_inst0_vld;
wire [63 :0] rtu_had_retire_inst1_info;
wire rtu_had_retire_inst1_vld;
wire [63 :0] rtu_had_retire_inst2_info;
wire rtu_had_retire_inst2_vld;
wire [2 :0] rtu_pipe_vld;
wire two_entry_left;
wire [4 :0] wptr_0;
wire [4 :0] wptr_1;
wire [4 :0] wptr_2;
wire [4 :0] wptr_inc;
wire [15 :0] wptr_sel_0;
wire [15 :0] wptr_sel_1;
wire [15 :0] wptr_sel_2;
wire x_dbg_ack_pc;
wire x_sm_xx_update_dr_en;
wire [407:0] xx_dgb_info;
// &Force("nonport","pipefifo_din_0"); @28
// &Force("nonport","pipefifo_din_1"); @29
// &Force("nonport","pipefifo_din_2"); @30
// &Force("nonport","wptr_sel_0"); @31
// &Force("nonport","wptr_sel_1"); @32
// &Force("nonport","wptr_sel_2"); @33
// &Force("nonport","xx_dbg_info_reg"); @34
//==============================================================================
// PIPESEL REG
//==============================================================================
// &Force("bus","ir_xx_wdata",63,0); @39
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
pipesel[1:0] <= 2'b0;
else if (x_sm_xx_update_dr_en && ir_xx_pipesel_reg_sel)
pipesel[1:0] <= ir_xx_wdata[1:0];
end
assign pipesel_regs_data[31:0] = {30'b0, pipesel[1:0]};
assign had_idu_debug_id_inst_en = (pipesel[1:0] == 2'b01) && ctrl_pipefifo_wen;
assign had_rtu_debug_retire_info_en = (pipesel[1:0] == 2'b10) && ctrl_pipefifo_wen;
assign had_lsu_dbg_info_en = (pipesel[1:0] == 2'b11) && ctrl_pipefifo_wen;
//==============================================================================
// PIPEFIFO REG
//==============================================================================
parameter PTR_WIDTH = 5;
parameter WIDTH = 64;
parameter DEPTH = 16;
assign idu_pipe_vld[2:0] = {idu_had_id_inst2_vld,idu_had_id_inst1_vld,idu_had_id_inst0_vld};
assign rtu_pipe_vld[2:0] = {rtu_had_retire_inst2_vld,rtu_had_retire_inst1_vld,rtu_had_retire_inst0_vld};
assign lsu_pipe_vld[2:0] = {1'b0,{2{lsu_had_st_req}}};
// &CombBeg; @65
always @( lsu_pipe_vld[2:0]
or lsu_had_st_data[63:0]
or rtu_had_retire_inst2_info[63:0]
or rtu_had_retire_inst1_info[63:0]
or rtu_had_retire_inst0_info[63:0]
or idu_had_id_inst1_info[39:0]
or rtu_pipe_vld[2:0]
or pipesel[1:0]
or idu_pipe_vld[2:0]
or idu_had_id_inst0_info[39:0]
or idu_had_id_inst2_info[39:0]
or lsu_had_st_addr[39:0])
begin
case(pipesel[1:0])
2'b01: begin pipefifo_sel[2:0] = idu_pipe_vld[2:0]; pipefifo_din_0[WIDTH-1:0] = {24'b0,idu_had_id_inst0_info[39:0]};
pipefifo_din_1[WIDTH-1:0] = {24'b0,idu_had_id_inst1_info[39:0]};
pipefifo_din_2[WIDTH-1:0] = {24'b0,idu_had_id_inst2_info[39:0]};
end
2'b10: begin pipefifo_sel[2:0] = rtu_pipe_vld[2:0]; pipefifo_din_0[WIDTH-1:0] = rtu_had_retire_inst0_info[63:0];
pipefifo_din_1[WIDTH-1:0] = rtu_had_retire_inst1_info[63:0];
pipefifo_din_2[WIDTH-1:0] = rtu_had_retire_inst2_info[63:0];
end
2'b11: begin pipefifo_sel[2:0] = lsu_pipe_vld[2:0]; pipefifo_din_0[WIDTH-1:0] = lsu_had_st_data[63:0];
pipefifo_din_1[WIDTH-1:0] = {24'b0,lsu_had_st_addr[39:0]};
pipefifo_din_2[WIDTH-1:0] = {WIDTH{1'b0}};
end
default:begin pipefifo_sel[2:0] = 3'b0; pipefifo_din_0[WIDTH-1:0] = {WIDTH{1'b0}};
pipefifo_din_1[WIDTH-1:0] = {WIDTH{1'b0}};
pipefifo_din_2[WIDTH-1:0] = {WIDTH{1'b0}};
end
endcase
// &CombEnd; @84
end
assign pipefifo_wen[2:0] = pipefifo_sel[2:0] & {3{ctrl_pipefifo_wen}};
assign create_vld = |pipefifo_wen[2:0];
assign create_one = pipefifo_wen[2:0] == 3'b001;
assign create_two = pipefifo_wen[2:0] == 3'b011;
assign create_thr = pipefifo_wen[2:0] == 3'b111;
assign wptr_sel_0[DEPTH-1:0] = {{(DEPTH-1){1'b0}},1'b1} << wptr_0[PTR_WIDTH-2:0];
assign wptr_sel_1[DEPTH-1:0] = {{(DEPTH-1){1'b0}},1'b1} << wptr_1[PTR_WIDTH-2:0];
assign wptr_sel_2[DEPTH-1:0] = {{(DEPTH-1){1'b0}},1'b1} << wptr_2[PTR_WIDTH-2:0];
//csky vperl_off
reg [WIDTH-1:0] pipefifo_reg[DEPTH-1:0];
genvar i;
generate
for(i=0; i<DEPTH; i=i+1) begin: PCFIFO_GEN
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
pipefifo_reg[i][WIDTH-1:0] <= {WIDTH{1'b0}};
else if (pipefifo_wen[0] && wptr_sel_0[i])
pipefifo_reg[i][WIDTH-1:0] <= pipefifo_din_0[WIDTH-1:0];
else if (pipefifo_wen[1] && wptr_sel_1[i])
pipefifo_reg[i][WIDTH-1:0] <= pipefifo_din_1[WIDTH-1:0];
else if (pipefifo_wen[2] && wptr_sel_2[i])
pipefifo_reg[i][WIDTH-1:0] <= pipefifo_din_2[WIDTH-1:0];
else
pipefifo_reg[i][WIDTH-1:0] <= pipefifo_reg[i][WIDTH-1:0];
end
end
endgenerate
//csky vperl_on
//==========================================================
// PIPEFIFO read
//==========================================================
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
pipefifo_dout[WIDTH-1:0] <= {WIDTH{1'b0}};
//csky vperl_off
else if (ctrl_pipefifo_ren)
pipefifo_dout[WIDTH-1:0] <= pipefifo_reg[rptr[PTR_WIDTH-2:0]][WIDTH-1:0];
//csky vperl_on
else
pipefifo_dout[WIDTH-1:0] <= pipefifo_dout[WIDTH-1:0];
end
assign pipefifo_regs_data[WIDTH-1:0] = pipefifo_dout[WIDTH-1:0];
//==========================================================
// Read pointer maintenance
//==========================================================
assign pipefifo_empty = (wptr[PTR_WIDTH-2:0] == rptr[PTR_WIDTH-2:0]) &&
(wptr[PTR_WIDTH-1] ~^ rptr[PTR_WIDTH-1]);
assign pipefifo_full = (wptr[PTR_WIDTH-2:0] == rptr[PTR_WIDTH-2:0]) &&
(wptr[PTR_WIDTH-1] ^ rptr[PTR_WIDTH-1]);
assign two_entry_left = (wptr_2[PTR_WIDTH-2:0] == rptr[PTR_WIDTH-2:0]) &&
(wptr_2[PTR_WIDTH-1] ^ rptr[PTR_WIDTH-1]);
assign one_entry_left = (wptr_1[PTR_WIDTH-2:0] == rptr[PTR_WIDTH-2:0]) &&
(wptr_1[PTR_WIDTH-1] ^ rptr[PTR_WIDTH-1]);
assign rptr_inc_3 = create_vld && pipefifo_full && create_thr;
assign rptr_inc_2 = create_vld && (one_entry_left && create_thr ||
pipefifo_full && create_two);
assign rptr_inc_1 = create_vld && (two_entry_left && create_thr ||
one_entry_left && create_two ||
pipefifo_full && create_one)
|| ctrl_pipefifo_ren;
assign rptr_inc[PTR_WIDTH-1:0] = rptr_inc_3
? {{(PTR_WIDTH-2){1'b0}},2'b11}
: rptr_inc_2 ? {{(PTR_WIDTH-2){1'b0}},2'b10}
: rptr_inc_1 ? {{(PTR_WIDTH-2){1'b0}},2'b01}
: {PTR_WIDTH{1'b0}};
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
rptr[PTR_WIDTH-1:0] <= {PTR_WIDTH{1'b0}};
else if (ctrl_pipefifo_ren || create_vld)
rptr[PTR_WIDTH-1:0] <= rptr[PTR_WIDTH-1:0] + rptr_inc[PTR_WIDTH-1:0];
else
rptr[PTR_WIDTH-1:0] <= rptr[PTR_WIDTH-1:0];
end
//==========================================================
// Write pointer maintenance
//==========================================================
assign wptr_inc[PTR_WIDTH-1:0] = create_thr
? {{(PTR_WIDTH-2){1'b0}},2'b11}
: create_two ? {{(PTR_WIDTH-2){1'b0}},2'b10}
: {{(PTR_WIDTH-2){1'b0}},2'b01};
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
wptr[PTR_WIDTH-1:0] <= {PTR_WIDTH{1'b0}};
else if (create_vld)
wptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0] + wptr_inc[PTR_WIDTH-1:0];
else if (ctrl_pipefifo_ren && pipefifo_empty)
wptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0] + {{(PTR_WIDTH-1){1'b0}},1'b1};
else
wptr[PTR_WIDTH-1:0] <= wptr[PTR_WIDTH-1:0];
end
assign wptr_0[PTR_WIDTH-1:0] = wptr[PTR_WIDTH-1:0];
assign wptr_1[PTR_WIDTH-1:0] = wptr[PTR_WIDTH-1:0] + {{(PTR_WIDTH-1){1'b0}},1'b1};
assign wptr_2[PTR_WIDTH-1:0] = wptr[PTR_WIDTH-1:0] + {{(PTR_WIDTH-2){1'b0}},2'b10};
//==============================================================================
// DBGINFO FIFO read
//==============================================================================
parameter DBG_WIDTH = 64;
parameter DBG_RPTR = 3;
parameter DBG_DPETH = 7;
//csky vperl_off
wire [DBG_WIDTH-1:0] dbginfo_reg[DBG_DPETH-1:0];
assign dbginfo_reg[0][63:0] = xx_dbg_info_reg[63:0];
assign dbginfo_reg[1][63:0] = xx_dbg_info_reg[127:64];
assign dbginfo_reg[2][63:0] = xx_dbg_info_reg[191:128];
assign dbginfo_reg[3][63:0] = xx_dbg_info_reg[255:192];
assign dbginfo_reg[4][63:0] = xx_dbg_info_reg[319:256];
assign dbginfo_reg[5][63:0] = xx_dbg_info_reg[383:320];
assign dbginfo_reg[6][63:0] = {40'b0, xx_dbg_info_reg[407:384]};
//csky vperl_on
// &Force("input","ctrl_dbgfifo_ren"); @221
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
dbginfo_dout[DBG_WIDTH-1:0] <= {DBG_WIDTH{1'b0}};
//csky vperl_off
else if (ctrl_dbgfifo_ren)
dbginfo_dout[DBG_WIDTH-1:0] <= dbginfo_reg[dbg_read_ptr[DBG_RPTR-1:0]][DBG_WIDTH-1:0];
//csky vperl_on
else
dbginfo_dout[DBG_WIDTH-1:0] <= dbginfo_dout[DBG_WIDTH-1:0];
end
assign dbgfifo_regs_data[DBG_WIDTH-1:0] = dbginfo_dout[DBG_WIDTH-1:0];
//==========================================================
// DBGINFO FIFO write
//==========================================================
assign xx_dgb_info[407:0] = {mmu_had_debug_info[33:0],
rtu_had_debug_info[42:0],
cp0_had_debug_info[3:0],
iu_had_debug_info[9:0],
idu_had_debug_info[49:0],
lsu_had_debug_info[183:0],
ifu_had_debug_info[82:0]};
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)begin
dbg_ack_pc_f <= 1'b0;
end
else begin
dbg_ack_pc_f <= rtu_had_dbg_ack_info;
end
end
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
xx_dbg_info_reg[407:0] <= 408'b0;
else if (dbg_ack_pc_f)
xx_dbg_info_reg[407:0] <= xx_dgb_info[407:0];
end
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
dbg_read_ptr[DBG_RPTR-1:0] <= {DBG_RPTR{1'b0}};
else if (ctrl_dbgfifo_ren)
dbg_read_ptr[DBG_RPTR-1:0] <= dbg_read_ptr[DBG_RPTR-1:0] + 4'b1;
else if (dbg_rptr_done)
dbg_read_ptr[DBG_RPTR-1:0] <= {DBG_RPTR{1'b0}};
else
dbg_read_ptr[DBG_RPTR-1:0] <= dbg_read_ptr[DBG_RPTR-1:0];
end
assign dbg_rptr_done = dbg_read_ptr[DBG_RPTR-1:0] == DBG_DPETH;
// &Force("input", "x_dbg_ack_pc_ack"); @288
// &Force("input", "forever_coreclk"); @289
// &Force("nonport", "x_dbg_ack_pc_ack_sync"); @290
assign x_dbg_ack_pc = dbg_ack_pc_f;
// &ModuleEnd; @305
endmodule |
module ct_had_bkpt(
bkpt_ctrl_data_req,
bkpt_ctrl_data_req_raw,
bkpt_ctrl_inst_req,
bkpt_ctrl_inst_req_raw,
bkpt_ctrl_xx_ack,
bkpt_regs_mbc,
cp0_yy_priv_mode,
cpuclk,
cpurst_b,
ctrl_bkpt_en,
ctrl_bkpt_en_raw,
inst_bkpt_dbgreq,
ir_xx_mbc_reg_sel,
ir_xx_wdata,
regs_xx_bc,
regs_xx_nirven,
rtu_had_bkpt_data_st,
rtu_had_data_bkpt_vld,
rtu_had_inst_bkpt_inst_vld,
rtu_had_inst_bkpt_vld,
rtu_had_inst_split,
rtu_had_xx_mbkpt_chgflow,
rtu_had_xx_mbkpt_data_ack,
rtu_had_xx_mbkpt_inst_ack,
rtu_had_xx_split_inst,
rtu_yy_xx_dbgon,
rtu_yy_xx_flush,
rtu_yy_xx_retire0_normal,
x_sm_xx_update_dr_en
);
// &Ports; @24
input [1 :0] cp0_yy_priv_mode;
input cpuclk;
input cpurst_b;
input ctrl_bkpt_en;
input ctrl_bkpt_en_raw;
input inst_bkpt_dbgreq;
input ir_xx_mbc_reg_sel;
input [63:0] ir_xx_wdata;
input [4 :0] regs_xx_bc;
input regs_xx_nirven;
input rtu_had_bkpt_data_st;
input rtu_had_data_bkpt_vld;
input rtu_had_inst_bkpt_inst_vld;
input rtu_had_inst_bkpt_vld;
input rtu_had_inst_split;
input rtu_had_xx_mbkpt_chgflow;
input rtu_had_xx_mbkpt_data_ack;
input rtu_had_xx_mbkpt_inst_ack;
input rtu_had_xx_split_inst;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_flush;
input rtu_yy_xx_retire0_normal;
input x_sm_xx_update_dr_en;
output bkpt_ctrl_data_req;
output bkpt_ctrl_data_req_raw;
output bkpt_ctrl_inst_req;
output bkpt_ctrl_inst_req_raw;
output bkpt_ctrl_xx_ack;
output [7 :0] bkpt_regs_mbc;
// &Regs; @25
reg [7 :0] bkpt_counter;
reg changeflow_inst_bkpt_ff;
reg data_bkpt_pending;
reg data_bkpt_vld_f;
reg inst_bkpt_inst_vld_f;
reg inst_bkpt_vld_f;
reg load_data_bkpt_ff;
reg normal_data_bkpt_ff;
reg normal_inst_bkpt_ff;
reg st_data_bkpt_ff;
// &Wires; @26
wire bkpt_counter_dec_1;
wire bkpt_counter_eq_0;
wire bkpt_counter_eq_0_raw;
wire bkpt_counter_eq_1;
wire bkpt_ctrl_data_req;
wire bkpt_ctrl_data_req_raw;
wire bkpt_ctrl_inst_req;
wire bkpt_ctrl_inst_req_raw;
wire bkpt_ctrl_xx_ack;
wire [7 :0] bkpt_regs_mbc;
wire changeflow_inst_bkpt;
wire [1 :0] cp0_yy_priv_mode;
wire cpuclk;
wire cpurst_b;
wire ctrl_bkpt_en;
wire ctrl_bkpt_en_raw;
wire data_bkpt_occur;
wire data_bkpt_req_raw;
wire data_bkpt_vld;
wire inst_bkpt_dbgreq;
wire inst_bkpt_occur;
wire inst_bkpt_req_raw;
wire inst_bkpt_vld;
wire ir_xx_mbc_reg_sel;
wire [63:0] ir_xx_wdata;
wire load_data_bkpt;
wire normal_data_bkpt;
wire normal_inst_bkpt;
wire priv_mode;
wire [4 :0] regs_xx_bc;
wire regs_xx_nirven;
wire rtu_had_bkpt_data_st;
wire rtu_had_data_bkpt_vld;
wire rtu_had_inst_bkpt_inst_vld;
wire rtu_had_inst_bkpt_vld;
wire rtu_had_inst_split;
wire rtu_had_xx_mbkpt_chgflow;
wire rtu_had_xx_mbkpt_data_ack;
wire rtu_had_xx_mbkpt_inst_ack;
wire rtu_had_xx_split_inst;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_flush;
wire rtu_yy_xx_retire0_normal;
wire st_data_bkpt;
wire user_mode;
wire x_sm_xx_update_dr_en;
//==============================================================================
// memory bkpt debug contains four levels:
// level one: memory bkpt conditions meet: (determined by RTU and LSU)
// 1. address trap (addr equal & rc clear or addr not equal & rc set)
// 2. bkpt_en
// 3. retire normal
// 4. not spilt inst for inst bkpt(except the last one)
// level two: memory bkpt type meets various conditions indicated by
// control bits of HCR
// level three: memory bkpt request
// 1. memory bkpt vld
// 2. bkpt_counter equal zero or one (corner case)
// 3. not in debug mode
// level four: memory bkpt debug request: (implemented in ctrl module)
// 1. current memory bkpt request meet SQC condition
//
// In naming methodology, the names for every levels are
// level one -- inst_bkpt_occur, data_bkpt_occur
// level two -- inst_bkpt_vld, data_bkpt_vld
// level three -- bkpt_ctrl_req
// level four -- mem_bkpt_debug_req
//==============================================================================
//==============================================================================
// level one
//==============================================================================
assign inst_bkpt_occur = rtu_had_inst_bkpt_vld && !regs_xx_nirven;
assign data_bkpt_occur = rtu_had_data_bkpt_vld && !regs_xx_nirven;
//==============================================================================
// level two
//==============================================================================
assign user_mode = cp0_yy_priv_mode[1:0] == 2'b00;
assign priv_mode = !user_mode;
assign changeflow_inst_bkpt =!regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&&!regs_xx_bc[0]
|| regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&&!regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&&!regs_xx_bc[0]&& priv_mode;
assign normal_inst_bkpt =!regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]
||!regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]
|| regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&& priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]&& priv_mode;
assign normal_data_bkpt =!regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]
||!regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&& regs_xx_bc[0]
|| regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&&!regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&& regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&&!regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&& priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&&!regs_xx_bc[2]&& regs_xx_bc[1]&& regs_xx_bc[0]&& priv_mode;
assign st_data_bkpt =!regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]
|| regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&& regs_xx_bc[2]&&!regs_xx_bc[1]&& regs_xx_bc[0]&& priv_mode;
assign load_data_bkpt =!regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]
|| regs_xx_bc[4]&&!regs_xx_bc[3]&& regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]&&!priv_mode
|| regs_xx_bc[4]&& regs_xx_bc[3]&& regs_xx_bc[2]&& regs_xx_bc[1]&&!regs_xx_bc[0]&& priv_mode;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
changeflow_inst_bkpt_ff <= 1'b0;
normal_inst_bkpt_ff <= 1'b0;
normal_data_bkpt_ff <= 1'b0;
st_data_bkpt_ff <= 1'b0;
load_data_bkpt_ff <= 1'b0;
end
else
begin
changeflow_inst_bkpt_ff <= changeflow_inst_bkpt;
normal_inst_bkpt_ff <= normal_inst_bkpt;
normal_data_bkpt_ff <= normal_data_bkpt;
st_data_bkpt_ff <= st_data_bkpt;
load_data_bkpt_ff <= load_data_bkpt;
end
end
assign inst_bkpt_vld = inst_bkpt_occur && rtu_had_xx_mbkpt_chgflow && changeflow_inst_bkpt_ff
|| inst_bkpt_occur && normal_inst_bkpt_ff;
assign data_bkpt_vld = data_bkpt_occur && normal_data_bkpt_ff
|| data_bkpt_occur && rtu_had_bkpt_data_st && st_data_bkpt_ff
|| data_bkpt_occur &&!rtu_had_bkpt_data_st && load_data_bkpt_ff;
//==============================================================================
// level three
//==============================================================================
//==========================================================
// memory bkpt counter decrease 1 condition(AND):
// 1. only one of inst_bkpt or data_bkpt is valid;
// 2. bkpt counter doesn't equal to zero;
// 3. not in debug mode.
// memory bkpt counter decrease 2 condition(AND):
// 1. both inst_bkpt and data_bkpt are valid;
// 2. bkpt counter doesn't equal to zero or one;
// 3. not in debug mode.
// 4. highest level or in untrusted world while medium level
//==========================================================
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b) begin
inst_bkpt_vld_f <= 1'b0;
data_bkpt_vld_f <= 1'b0;
end
else if (rtu_had_inst_bkpt_inst_vld) begin
inst_bkpt_vld_f <= inst_bkpt_vld;
data_bkpt_vld_f <= data_bkpt_vld;
end
end
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
inst_bkpt_inst_vld_f <= 1'b0;
else
inst_bkpt_inst_vld_f <= rtu_had_inst_bkpt_inst_vld;
end
assign bkpt_counter_dec_1 = (inst_bkpt_vld_f && !rtu_had_xx_split_inst ||
data_bkpt_vld_f) &&
ctrl_bkpt_en &&
rtu_yy_xx_retire0_normal &&
!bkpt_counter_eq_0 &&
!inst_bkpt_dbgreq &&
// !rtu_had_xx_split_inst &&
!rtu_yy_xx_dbgon;
// memory bkpt counter
// &Force("bus", "ir_xx_wdata", 63, 0); @158
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
bkpt_counter[7:0] <= 8'b0;
else if (x_sm_xx_update_dr_en && ir_xx_mbc_reg_sel)
bkpt_counter[7:0] <= ir_xx_wdata[7:0];
else if (bkpt_counter_dec_1)
bkpt_counter[7:0] <= bkpt_counter[7:0] - 8'b1;
else
bkpt_counter[7:0] <= bkpt_counter[7:0];
end
assign bkpt_counter_eq_0 = bkpt_counter[7:0] == 8'b0;
assign bkpt_counter_eq_1 = bkpt_counter[7:0] == 8'b1;
assign bkpt_regs_mbc[7:0] = bkpt_counter[7:0];
assign bkpt_counter_eq_0_raw = bkpt_counter_dec_1 ? bkpt_counter_eq_1 : bkpt_counter_eq_0;
//=========================================================
// memory bkpt request condition(AND):
// 1. bkpt counter equals to zero;
// 2. inst_bkpt_vld or data_bkpt_vld or both vld;
// OR
// 1. bkpt counter equals to one;
// 2. inst_bkpt_vld and data_bkpt_vld both vld;
//==========================================================
assign bkpt_ctrl_xx_ack = rtu_had_xx_mbkpt_inst_ack && bkpt_counter_eq_0 && ctrl_bkpt_en ||
rtu_had_xx_mbkpt_data_ack && bkpt_counter_eq_0 && ctrl_bkpt_en;
assign bkpt_ctrl_inst_req = bkpt_counter_eq_0 && inst_bkpt_vld_f && !rtu_yy_xx_dbgon && ctrl_bkpt_en && inst_bkpt_inst_vld_f;
assign bkpt_ctrl_data_req = bkpt_counter_eq_0 && data_bkpt_vld_f && !rtu_yy_xx_dbgon && ctrl_bkpt_en && rtu_yy_xx_retire0_normal;
assign inst_bkpt_req_raw = bkpt_counter_eq_0_raw && inst_bkpt_vld && !rtu_yy_xx_dbgon && ctrl_bkpt_en_raw && rtu_had_inst_bkpt_inst_vld;
assign data_bkpt_req_raw = bkpt_counter_eq_0_raw && data_bkpt_vld && !rtu_yy_xx_dbgon && ctrl_bkpt_en_raw && rtu_had_inst_bkpt_inst_vld;
assign bkpt_ctrl_inst_req_raw = inst_bkpt_req_raw;
assign bkpt_ctrl_data_req_raw = data_bkpt_req_raw && !rtu_had_inst_split ||
data_bkpt_pending && !rtu_had_inst_split && rtu_had_inst_bkpt_inst_vld;
always @(posedge cpuclk or negedge cpurst_b)
begin
if (!cpurst_b)
data_bkpt_pending <= 1'b0;
else if (rtu_yy_xx_flush)
data_bkpt_pending <= 1'b0;
else if (data_bkpt_req_raw && rtu_had_inst_split)
data_bkpt_pending <= 1'b1;
else if (rtu_yy_xx_dbgon)
data_bkpt_pending <= 1'b0;
end
// &ModuleEnd; @211
endmodule |
module ct_had_common_top(
apbif_had_pctrace_inv,
ciu_had_dbg_info,
core0_dbg_ack_pc,
core0_enter_dbg_req_i,
core0_enter_dbg_req_o,
core0_exit_dbg_req_i,
core0_exit_dbg_req_o,
core0_had_dbg_mask,
core0_regs_serial_data,
core0_rst_b,
core1_dbg_ack_pc,
core1_enter_dbg_req_i,
core1_enter_dbg_req_o,
core1_exit_dbg_req_i,
core1_exit_dbg_req_o,
core1_had_dbg_mask,
core1_regs_serial_data,
core1_rst_b,
cpurst_b,
forever_cpuclk,
had_pad_jtg_tdo,
had_pad_jtg_tdo_en,
ir_corex_wdata,
l2c_had_dbg_info,
pad_had_jtg_tdi,
pad_had_jtg_tms,
pad_yy_icg_scan_en,
perr_had,
prdata_had,
pready_had,
psel_had,
sm_update_dr,
sm_update_ir,
sysio_had_dbg_mask,
tclk,
trst_b
);
// &Ports; @24
input apbif_had_pctrace_inv;
input [292:0] ciu_had_dbg_info;
input core0_dbg_ack_pc;
input core0_enter_dbg_req_o;
input core0_exit_dbg_req_o;
input [63 :0] core0_regs_serial_data;
input core0_rst_b;
input core1_dbg_ack_pc;
input core1_enter_dbg_req_o;
input core1_exit_dbg_req_o;
input [63 :0] core1_regs_serial_data;
input core1_rst_b;
input cpurst_b;
input forever_cpuclk;
input [43 :0] l2c_had_dbg_info;
input pad_had_jtg_tdi;
input pad_had_jtg_tms;
input pad_yy_icg_scan_en;
input psel_had;
input [3 :0] sysio_had_dbg_mask;
input tclk;
input trst_b;
output core0_enter_dbg_req_i;
output core0_exit_dbg_req_i;
output core0_had_dbg_mask;
output core1_enter_dbg_req_i;
output core1_exit_dbg_req_i;
output core1_had_dbg_mask;
output had_pad_jtg_tdo;
output had_pad_jtg_tdo_en;
output [63 :0] ir_corex_wdata;
output perr_had;
output [31 :0] prdata_had;
output pready_had;
output sm_update_dr;
output sm_update_ir;
// &Regs; @25
// &Wires; @26
wire [292:0] ciu_had_dbg_info;
wire [63 :0] common_regs_data;
wire core0_dbg_ack_pc;
wire core0_enter_dbg_req_i;
wire core0_enter_dbg_req_o;
wire core0_exit_dbg_req_i;
wire core0_exit_dbg_req_o;
wire core0_had_dbg_mask;
wire [63 :0] core0_regs_serial_data;
wire core0_rst_b;
wire core1_dbg_ack_pc;
wire core1_enter_dbg_req_i;
wire core1_enter_dbg_req_o;
wire core1_exit_dbg_req_i;
wire core1_exit_dbg_req_o;
wire core1_had_dbg_mask;
wire [63 :0] core1_regs_serial_data;
wire core1_rst_b;
wire cpurst_b;
wire [63 :0] dbgfifo2_data;
wire dbgfifo2_read_ren;
wire forever_cpuclk;
wire had_pad_jtg_tdo;
wire had_pad_jtg_tdo_en;
wire io_serial_tdi;
wire io_sm_tap_en;
wire [63 :0] ir_corex_wdata;
wire ir_sm_hacr_rw;
wire ir_xx_baba_reg_sel;
wire ir_xx_babb_reg_sel;
wire ir_xx_bama_reg_sel;
wire ir_xx_bamb_reg_sel;
wire ir_xx_core0_sel;
wire ir_xx_core1_sel;
wire ir_xx_core2_sel;
wire ir_xx_core3_sel;
wire ir_xx_csr_reg_sel;
wire ir_xx_daddr_reg_sel;
wire ir_xx_dbgfifo2_reg_sel;
wire ir_xx_dbgfifo_reg_sel;
wire ir_xx_ddata_reg_sel;
wire ir_xx_dms_reg_sel;
wire ir_xx_id_reg_sel;
wire ir_xx_mbca_reg_sel;
wire ir_xx_mbcb_reg_sel;
wire ir_xx_otc_reg_sel;
wire ir_xx_pc_reg_sel;
wire ir_xx_pcfifo_reg_sel;
wire ir_xx_pipefifo_reg_sel;
wire ir_xx_rsr_reg_sel;
wire ir_xx_wbbr_reg_sel;
wire [43 :0] l2c_had_dbg_info;
wire pad_had_jtg_tdi;
wire pad_had_jtg_tms;
wire pad_yy_icg_scan_en;
wire perr_had;
wire [31 :0] prdata_had;
wire pready_had;
wire [63 :0] regs_serial_data;
wire serial_io_tdo;
wire [63 :0] serial_xx_data;
wire sm_io_tdo_en;
wire sm_ir_update_hacr;
wire sm_serial_capture_dr;
wire sm_serial_shift_dr;
wire sm_serial_shift_ir;
wire sm_update_dr;
wire sm_update_ir;
wire sm_xx_write_en;
wire [3 :0] sysio_had_dbg_mask;
wire tclk;
wire trst_b;
// &Instance("ct_had_sm"); @28
ct_had_sm x_ct_had_sm (
.cpurst_b (cpurst_b ),
.dbgfifo2_read_ren (dbgfifo2_read_ren ),
.forever_cpuclk (forever_cpuclk ),
.io_sm_tap_en (io_sm_tap_en ),
.ir_sm_hacr_rw (ir_sm_hacr_rw ),
.ir_xx_dbgfifo2_reg_sel (ir_xx_dbgfifo2_reg_sel),
.pad_had_jtg_tms (pad_had_jtg_tms ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.sm_io_tdo_en (sm_io_tdo_en ),
.sm_ir_update_hacr (sm_ir_update_hacr ),
.sm_serial_capture_dr (sm_serial_capture_dr ),
.sm_serial_shift_dr (sm_serial_shift_dr ),
.sm_serial_shift_ir (sm_serial_shift_ir ),
.sm_update_dr (sm_update_dr ),
.sm_update_ir (sm_update_ir ),
.sm_xx_write_en (sm_xx_write_en ),
.tclk (tclk ),
.trst_b (trst_b )
);
// &Instance("ct_had_io"); @29
ct_had_io x_ct_had_io (
.had_pad_jtg_tdo (had_pad_jtg_tdo ),
.had_pad_jtg_tdo_en (had_pad_jtg_tdo_en),
.io_serial_tdi (io_serial_tdi ),
.io_sm_tap_en (io_sm_tap_en ),
.pad_had_jtg_tdi (pad_had_jtg_tdi ),
.serial_io_tdo (serial_io_tdo ),
.sm_io_tdo_en (sm_io_tdo_en )
);
// &Instance("ct_had_serial"); @30
ct_had_serial x_ct_had_serial (
.io_serial_tdi (io_serial_tdi ),
.ir_xx_baba_reg_sel (ir_xx_baba_reg_sel ),
.ir_xx_babb_reg_sel (ir_xx_babb_reg_sel ),
.ir_xx_bama_reg_sel (ir_xx_bama_reg_sel ),
.ir_xx_bamb_reg_sel (ir_xx_bamb_reg_sel ),
.ir_xx_csr_reg_sel (ir_xx_csr_reg_sel ),
.ir_xx_daddr_reg_sel (ir_xx_daddr_reg_sel ),
.ir_xx_dbgfifo2_reg_sel (ir_xx_dbgfifo2_reg_sel),
.ir_xx_dbgfifo_reg_sel (ir_xx_dbgfifo_reg_sel ),
.ir_xx_ddata_reg_sel (ir_xx_ddata_reg_sel ),
.ir_xx_mbca_reg_sel (ir_xx_mbca_reg_sel ),
.ir_xx_mbcb_reg_sel (ir_xx_mbcb_reg_sel ),
.ir_xx_otc_reg_sel (ir_xx_otc_reg_sel ),
.ir_xx_pc_reg_sel (ir_xx_pc_reg_sel ),
.ir_xx_pcfifo_reg_sel (ir_xx_pcfifo_reg_sel ),
.ir_xx_pipefifo_reg_sel (ir_xx_pipefifo_reg_sel),
.ir_xx_wbbr_reg_sel (ir_xx_wbbr_reg_sel ),
.regs_serial_data (regs_serial_data ),
.serial_io_tdo (serial_io_tdo ),
.serial_xx_data (serial_xx_data ),
.sm_serial_capture_dr (sm_serial_capture_dr ),
.sm_serial_shift_dr (sm_serial_shift_dr ),
.sm_serial_shift_ir (sm_serial_shift_ir ),
.sm_xx_write_en (sm_xx_write_en ),
.tclk (tclk ),
.trst_b (trst_b )
);
// &Instance("ct_had_ir"); @31
ct_had_ir x_ct_had_ir (
.common_regs_data (common_regs_data ),
.core0_regs_serial_data (core0_regs_serial_data),
.core1_regs_serial_data (core1_regs_serial_data),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.ir_corex_wdata (ir_corex_wdata ),
.ir_sm_hacr_rw (ir_sm_hacr_rw ),
.ir_xx_baba_reg_sel (ir_xx_baba_reg_sel ),
.ir_xx_babb_reg_sel (ir_xx_babb_reg_sel ),
.ir_xx_bama_reg_sel (ir_xx_bama_reg_sel ),
.ir_xx_bamb_reg_sel (ir_xx_bamb_reg_sel ),
.ir_xx_core0_sel (ir_xx_core0_sel ),
.ir_xx_core1_sel (ir_xx_core1_sel ),
.ir_xx_core2_sel (ir_xx_core2_sel ),
.ir_xx_core3_sel (ir_xx_core3_sel ),
.ir_xx_csr_reg_sel (ir_xx_csr_reg_sel ),
.ir_xx_daddr_reg_sel (ir_xx_daddr_reg_sel ),
.ir_xx_dbgfifo2_reg_sel (ir_xx_dbgfifo2_reg_sel),
.ir_xx_dbgfifo_reg_sel (ir_xx_dbgfifo_reg_sel ),
.ir_xx_ddata_reg_sel (ir_xx_ddata_reg_sel ),
.ir_xx_dms_reg_sel (ir_xx_dms_reg_sel ),
.ir_xx_id_reg_sel (ir_xx_id_reg_sel ),
.ir_xx_mbca_reg_sel (ir_xx_mbca_reg_sel ),
.ir_xx_mbcb_reg_sel (ir_xx_mbcb_reg_sel ),
.ir_xx_otc_reg_sel (ir_xx_otc_reg_sel ),
.ir_xx_pc_reg_sel (ir_xx_pc_reg_sel ),
.ir_xx_pcfifo_reg_sel (ir_xx_pcfifo_reg_sel ),
.ir_xx_pipefifo_reg_sel (ir_xx_pipefifo_reg_sel),
.ir_xx_rsr_reg_sel (ir_xx_rsr_reg_sel ),
.ir_xx_wbbr_reg_sel (ir_xx_wbbr_reg_sel ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.regs_serial_data (regs_serial_data ),
.serial_xx_data (serial_xx_data ),
.sm_ir_update_hacr (sm_ir_update_hacr ),
.sysio_had_dbg_mask (sysio_had_dbg_mask )
);
// &Instance("ct_had_etm"); @32
ct_had_etm x_ct_had_etm (
.core0_enter_dbg_req_i (core0_enter_dbg_req_i),
.core0_enter_dbg_req_o (core0_enter_dbg_req_o),
.core0_exit_dbg_req_i (core0_exit_dbg_req_i ),
.core0_exit_dbg_req_o (core0_exit_dbg_req_o ),
.core1_enter_dbg_req_i (core1_enter_dbg_req_i),
.core1_enter_dbg_req_o (core1_enter_dbg_req_o),
.core1_exit_dbg_req_i (core1_exit_dbg_req_i ),
.core1_exit_dbg_req_o (core1_exit_dbg_req_o ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_had_common_regs"); @34
ct_had_common_regs x_ct_had_common_regs (
.common_regs_data (common_regs_data ),
.core0_had_dbg_mask (core0_had_dbg_mask ),
.core0_rst_b (core0_rst_b ),
.core1_had_dbg_mask (core1_had_dbg_mask ),
.core1_rst_b (core1_rst_b ),
.dbgfifo2_data (dbgfifo2_data ),
.forever_cpuclk (forever_cpuclk ),
.ir_xx_core0_sel (ir_xx_core0_sel ),
.ir_xx_core1_sel (ir_xx_core1_sel ),
.ir_xx_core2_sel (ir_xx_core2_sel ),
.ir_xx_core3_sel (ir_xx_core3_sel ),
.ir_xx_dbgfifo2_reg_sel (ir_xx_dbgfifo2_reg_sel),
.ir_xx_dms_reg_sel (ir_xx_dms_reg_sel ),
.ir_xx_id_reg_sel (ir_xx_id_reg_sel ),
.ir_xx_rsr_reg_sel (ir_xx_rsr_reg_sel ),
.sysio_had_dbg_mask (sysio_had_dbg_mask )
);
// &Instance("ct_had_common_dbg_info") @35
ct_had_common_dbg_info x_ct_had_common_dbg_info (
.ciu_had_dbg_info (ciu_had_dbg_info ),
.core0_dbg_ack_pc (core0_dbg_ack_pc ),
.core1_dbg_ack_pc (core1_dbg_ack_pc ),
.cpurst_b (cpurst_b ),
.dbgfifo2_data (dbgfifo2_data ),
.dbgfifo2_read_ren (dbgfifo2_read_ren ),
.forever_cpuclk (forever_cpuclk ),
.l2c_had_dbg_info (l2c_had_dbg_info ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Instance("ct_had_pctrace_busif"); @38
// &Connect(.pclk (apb_clk ), @39
// .perr (perr_had ), @40
// .prdata (prdata_had), @41
// .pready (pready_had), @42
// .prst_b (cpurst_b ), @43
// .psel (psel_had )); @44
// had apb
// &Force("input", "psel_had"); @47
assign pready_had = 1'b1;
assign perr_had = 1'b0;
assign prdata_had[31:0] = 32'b0;
// &Force("input", "apbif_had_pctrace_inv"); @51
// &ModuleEnd; @71
endmodule |
module ct_vfmau_lza_simd_half(
addend,
lza_result,
lza_result_zero,
sub_vld,
summand
);
// &Ports; @24
input [23:0] addend;
input sub_vld;
input [23:0] summand;
output [4 :0] lza_result;
output lza_result_zero;
// &Regs; @25
reg [4 :0] lza_result;
// &Wires; @26
wire [23:0] addend;
wire [23:0] carry_d;
wire [23:0] carry_g;
wire [23:0] carry_p;
wire [23:0] lza_precod;
wire lza_result_zero;
wire sub_vld;
wire [23:0] summand;
//==========================================================
// Signal Pre-encode
//==========================================================
//----------------------------------------------------------
// Signal preparation
//----------------------------------------------------------
// carry_p: carry propagete
// carry_g: carry generate
// carry_d: carry delete
assign carry_p[23:0] = summand[23:0] ^ addend[23:0];
assign carry_g[23:0] = summand[23:0] & addend[23:0];
assign carry_d[23:0] = ~(summand[23:0] | addend[23:0]);
//----------------------------------------------------------
// Signal decode
//----------------------------------------------------------
//pre-predecode for leading zero anticipation
assign lza_precod[0] =
carry_p[1] && (carry_g[0] && sub_vld || carry_d[0])
|| !carry_p[1] && (carry_d[0] && sub_vld || carry_g[0]);
assign lza_precod[23] =
sub_vld && (carry_g[23] && !carry_d[22] || carry_d[23] && !carry_g[22])
|| !sub_vld && (carry_d[23] && !carry_d[22] || !carry_d[23]);
assign lza_precod[22:1] =
carry_p[23:2] & (carry_g[22:1] & ~carry_d[21:0] | carry_d[22:1] & ~carry_g[21:0])
| ~carry_p[23:2] & (carry_g[22:1] & ~carry_g[21:0] | carry_d[22:1] & ~carry_d[21:0]);
//==========================================================
// LZA coding
//==========================================================
// &CombBeg; @59
always @( lza_precod[23:0])
begin
casez(lza_precod[23:0])
24'b1???????????????????????:lza_result[4:0] = 5'd0;
24'b01??????????????????????:lza_result[4:0] = 5'd1;
24'b001?????????????????????:lza_result[4:0] = 5'd2;
24'b0001????????????????????:lza_result[4:0] = 5'd3;
24'b00001???????????????????:lza_result[4:0] = 5'd4;
24'b000001??????????????????:lza_result[4:0] = 5'd5;
24'b0000001?????????????????:lza_result[4:0] = 5'd6;
24'b00000001????????????????:lza_result[4:0] = 5'd7;
24'b000000001???????????????:lza_result[4:0] = 5'd8;
24'b0000000001??????????????:lza_result[4:0] = 5'd9;
24'b00000000001?????????????:lza_result[4:0] = 5'd10;
24'b000000000001????????????:lza_result[4:0] = 5'd11;
24'b0000000000001???????????:lza_result[4:0] = 5'd12;
24'b00000000000001??????????:lza_result[4:0] = 5'd13;
24'b000000000000001?????????:lza_result[4:0] = 5'd14;
24'b0000000000000001????????:lza_result[4:0] = 5'd15;
24'b00000000000000001???????:lza_result[4:0] = 5'd16;
24'b000000000000000001??????:lza_result[4:0] = 5'd17;
24'b0000000000000000001?????:lza_result[4:0] = 5'd18;
24'b00000000000000000001????:lza_result[4:0] = 5'd19;
24'b000000000000000000001???:lza_result[4:0] = 5'd20;
24'b0000000000000000000001??:lza_result[4:0] = 5'd21;
24'b00000000000000000000001?:lza_result[4:0] = 5'd22;
24'b000000000000000000000001:lza_result[4:0] = 5'd23;
default :lza_result[4:0] = 5'd24;
endcase
// &CombEnd; @87
end
assign lza_result_zero = ~|lza_precod[23:0];
// &ModuleEnd; @91
endmodule |
module ct_vfmau_top(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfmau_ex1_pipex_dst_vreg,
dp_vfmau_ex1_pipex_imm0,
dp_vfmau_ex1_pipex_sel,
dp_vfmau_pipe6_mla_srcv2_vld,
dp_vfmau_pipe6_mla_srcv2_vreg,
dp_vfmau_pipe6_mla_type,
dp_vfmau_pipe7_mla_srcv2_vld,
dp_vfmau_pipe7_mla_srcv2_vreg,
dp_vfmau_pipe7_mla_type,
dp_vfmau_pipex_inst_type,
dp_vfmau_pipex_sel,
dp_vfmau_pipex_vfmau_sel,
dp_vfmau_rf_pipex_sel,
forever_cpuclk,
idu_vfpu_rf_pipex_func,
idu_vfpu_rf_pipex_gateclk_sel,
idu_vfpu_rf_pipex_srcv0_fr,
idu_vfpu_rf_pipex_srcv1_fr,
idu_vfpu_rf_pipex_srcv2_fr,
pad_yy_icg_scan_en,
pipe6_pipex_ex4_fmla_fwd_vld,
pipe6_pipex_ex5_ex1_fmla_fwd_vld,
pipe6_pipex_ex5_ex2_fmla_fwd_vld,
pipe6_vfmau_ex4_fmla_slice0_half0_data,
pipe6_vfmau_ex5_fmla_slice0_data,
pipe7_pipex_ex4_fmla_fwd_vld,
pipe7_pipex_ex5_ex1_fmla_fwd_vld,
pipe7_pipex_ex5_ex2_fmla_fwd_vld,
pipe7_vfmau_ex4_fmla_slice0_half0_data,
pipe7_vfmau_ex5_fmla_slice0_data,
pipex_dp_ex1_mult_id,
pipex_dp_ex3_vfmau_ereg_data,
pipex_dp_ex3_vfmau_freg_data,
pipex_dp_ex4_vfmau_ereg_data,
pipex_dp_ex4_vfmau_freg_data,
pipex_pipe6_ex4_fmla_fwd_vld,
pipex_pipe6_ex5_ex1_fmla_fwd_vld,
pipex_pipe6_ex5_ex2_fmla_fwd_vld,
pipex_pipe7_ex4_fmla_fwd_vld,
pipex_pipe7_ex5_ex1_fmla_fwd_vld,
pipex_pipe7_ex5_ex2_fmla_fwd_vld,
pipex_rbus_ex1_fmla_data_vld,
pipex_rbus_ex1_fmla_data_vld_dup0,
pipex_rbus_ex1_fmla_data_vld_dup1,
pipex_rbus_ex1_fmla_data_vld_dup2,
pipex_rbus_ex2_fmla_data_vld,
pipex_rbus_ex2_fmla_data_vld_dup0,
pipex_rbus_ex2_fmla_data_vld_dup1,
pipex_rbus_ex2_fmla_data_vld_dup2,
pipex_rbus_pipe6_fmla_no_fwd,
pipex_rbus_pipe7_fmla_no_fwd,
pipex_rbus_vfmau_ereg_wb_data,
pipex_rbus_vfmau_ereg_wb_vld,
pipex_rbus_vfmau_freg_wb_data,
pipex_rbus_vfmau_vreg_wb_vld,
pipex_vfmau_ex4_fmla_slice0_half0_data,
pipex_vfmau_ex5_fmla_slice0_data,
rtu_yy_xx_flush,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [6 :0] dp_vfmau_ex1_pipex_dst_vreg;
input [2 :0] dp_vfmau_ex1_pipex_imm0;
input dp_vfmau_ex1_pipex_sel;
input dp_vfmau_pipe6_mla_srcv2_vld;
input [6 :0] dp_vfmau_pipe6_mla_srcv2_vreg;
input [2 :0] dp_vfmau_pipe6_mla_type;
input dp_vfmau_pipe7_mla_srcv2_vld;
input [6 :0] dp_vfmau_pipe7_mla_srcv2_vreg;
input [2 :0] dp_vfmau_pipe7_mla_type;
input [5 :0] dp_vfmau_pipex_inst_type;
input dp_vfmau_pipex_sel;
input dp_vfmau_pipex_vfmau_sel;
input dp_vfmau_rf_pipex_sel;
input forever_cpuclk;
input [19:0] idu_vfpu_rf_pipex_func;
input idu_vfpu_rf_pipex_gateclk_sel;
input [63:0] idu_vfpu_rf_pipex_srcv0_fr;
input [63:0] idu_vfpu_rf_pipex_srcv1_fr;
input [63:0] idu_vfpu_rf_pipex_srcv2_fr;
input pad_yy_icg_scan_en;
input pipe6_pipex_ex4_fmla_fwd_vld;
input pipe6_pipex_ex5_ex1_fmla_fwd_vld;
input pipe6_pipex_ex5_ex2_fmla_fwd_vld;
input [15:0] pipe6_vfmau_ex4_fmla_slice0_half0_data;
input [67:0] pipe6_vfmau_ex5_fmla_slice0_data;
input pipe7_pipex_ex4_fmla_fwd_vld;
input pipe7_pipex_ex5_ex1_fmla_fwd_vld;
input pipe7_pipex_ex5_ex2_fmla_fwd_vld;
input [15:0] pipe7_vfmau_ex4_fmla_slice0_half0_data;
input [67:0] pipe7_vfmau_ex5_fmla_slice0_data;
input rtu_yy_xx_flush;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output pipex_dp_ex1_mult_id;
output [4 :0] pipex_dp_ex3_vfmau_ereg_data;
output [63:0] pipex_dp_ex3_vfmau_freg_data;
output [4 :0] pipex_dp_ex4_vfmau_ereg_data;
output [63:0] pipex_dp_ex4_vfmau_freg_data;
output pipex_pipe6_ex4_fmla_fwd_vld;
output pipex_pipe6_ex5_ex1_fmla_fwd_vld;
output pipex_pipe6_ex5_ex2_fmla_fwd_vld;
output pipex_pipe7_ex4_fmla_fwd_vld;
output pipex_pipe7_ex5_ex1_fmla_fwd_vld;
output pipex_pipe7_ex5_ex2_fmla_fwd_vld;
output pipex_rbus_ex1_fmla_data_vld;
output pipex_rbus_ex1_fmla_data_vld_dup0;
output pipex_rbus_ex1_fmla_data_vld_dup1;
output pipex_rbus_ex1_fmla_data_vld_dup2;
output pipex_rbus_ex2_fmla_data_vld;
output pipex_rbus_ex2_fmla_data_vld_dup0;
output pipex_rbus_ex2_fmla_data_vld_dup1;
output pipex_rbus_ex2_fmla_data_vld_dup2;
output pipex_rbus_pipe6_fmla_no_fwd;
output pipex_rbus_pipe7_fmla_no_fwd;
output [4 :0] pipex_rbus_vfmau_ereg_wb_data;
output pipex_rbus_vfmau_ereg_wb_vld;
output [63:0] pipex_rbus_vfmau_freg_wb_data;
output pipex_rbus_vfmau_vreg_wb_vld;
output [15:0] pipex_vfmau_ex4_fmla_slice0_half0_data;
output [67:0] pipex_vfmau_ex5_fmla_slice0_data;
// &Regs; @25
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_dp_ex5_fma_wb_vld;
wire ctrl_ex1_ex2_en;
wire ctrl_ex1_inst_vld;
wire ctrl_ex2_inst_vld;
wire ctrl_ex3_inst_vld;
wire ctrl_ex4_inst_vld;
wire ctrl_ex5_inst_vld;
wire [63:0] dp_mult1_ex1_op0_slice0;
wire [31:0] dp_mult1_ex1_op0_slice0_high;
wire [63:0] dp_mult1_ex1_op1_slice0;
wire [31:0] dp_mult1_ex1_op1_slice0_high;
wire [63:0] dp_mult1_ex1_op2_slice0;
wire [31:0] dp_mult1_ex1_op2_slice0_high;
wire dp_mult1_op2_slice0_vl_mask;
wire dp_mult1_op2_slice0_vm_mask;
wire [15:0] dp_mult_ex1_op0_slice0_half0;
wire [47:0] dp_mult_ex1_op0_slice0_half0_high;
wire [15:0] dp_mult_ex1_op1_slice0_half0;
wire [47:0] dp_mult_ex1_op1_slice0_half0_high;
wire [31:0] dp_mult_ex1_op2_slice0_half0;
wire [47:0] dp_mult_ex1_op2_slice0_half0_high;
wire dp_mult_op2_slice0_vl_half0_mask;
wire dp_mult_op2_slice0_vm_half0_mask;
wire [6 :0] dp_vfmau_ex1_pipex_dst_vreg;
wire [2 :0] dp_vfmau_ex1_pipex_imm0;
wire dp_vfmau_ex1_pipex_sel;
wire dp_vfmau_pipe6_mla_srcv2_vld;
wire [6 :0] dp_vfmau_pipe6_mla_srcv2_vreg;
wire [2 :0] dp_vfmau_pipe6_mla_type;
wire dp_vfmau_pipe7_mla_srcv2_vld;
wire [6 :0] dp_vfmau_pipe7_mla_srcv2_vreg;
wire [2 :0] dp_vfmau_pipe7_mla_type;
wire [5 :0] dp_vfmau_pipex_inst_type;
wire dp_vfmau_pipex_sel;
wire dp_vfmau_pipex_vfmau_sel;
wire dp_vfmau_rf_pipex_sel;
wire dp_xx_ex1_double;
wire dp_xx_ex1_fma;
wire dp_xx_ex1_half;
wire dp_xx_ex1_neg;
wire [51:0] dp_xx_ex1_op0_frac;
wire [51:0] dp_xx_ex1_op1_frac;
wire [2 :0] dp_xx_ex1_rm;
wire dp_xx_ex1_simd;
wire dp_xx_ex1_single;
wire dp_xx_ex1_sub;
wire dp_xx_ex1_widen;
wire dp_xx_ex2_double;
wire dp_xx_ex2_fma;
wire dp_xx_ex2_half;
wire dp_xx_ex2_mult_id;
wire dp_xx_ex2_neg;
wire [2 :0] dp_xx_ex2_rm;
wire dp_xx_ex2_simd;
wire dp_xx_ex2_sub;
wire dp_xx_ex2_widen;
wire dp_xx_ex3_double;
wire dp_xx_ex3_fma;
wire dp_xx_ex3_half;
wire dp_xx_ex3_mult_id;
wire [2 :0] dp_xx_ex3_rm;
wire dp_xx_ex3_simd;
wire dp_xx_ex3_widen;
wire dp_xx_ex4_double;
wire dp_xx_ex4_fma;
wire dp_xx_ex4_half;
wire dp_xx_ex4_mult_id;
wire [2 :0] dp_xx_ex4_rm;
wire forever_cpuclk;
wire [19:0] idu_vfpu_rf_pipex_func;
wire idu_vfpu_rf_pipex_gateclk_sel;
wire [63:0] idu_vfpu_rf_pipex_srcv0_fr;
wire [63:0] idu_vfpu_rf_pipex_srcv1_fr;
wire [63:0] idu_vfpu_rf_pipex_srcv2_fr;
wire mult1_ex1_ex2_pipedown;
wire mult1_ex2_ex3_pipedown;
wire mult1_ex3_ex4_pipedown;
wire mult1_ex4_ex5_pipedown;
wire mult_ex1_ex2_half_pipedown;
wire mult_ex2_ex3_half_pipedown;
wire mult_ex3_ex4_half_pipedown;
wire mult_ex4_ex5_half_pipedown;
wire pad_yy_icg_scan_en;
wire pipe6_pipex_ex4_fmla_fwd_vld;
wire pipe6_pipex_ex5_ex1_fmla_fwd_vld;
wire pipe6_pipex_ex5_ex2_fmla_fwd_vld;
wire [15:0] pipe6_vfmau_ex4_fmla_slice0_half0_data;
wire [67:0] pipe6_vfmau_ex5_fmla_slice0_data;
wire pipe7_pipex_ex4_fmla_fwd_vld;
wire pipe7_pipex_ex5_ex1_fmla_fwd_vld;
wire pipe7_pipex_ex5_ex2_fmla_fwd_vld;
wire [15:0] pipe7_vfmau_ex4_fmla_slice0_half0_data;
wire [67:0] pipe7_vfmau_ex5_fmla_slice0_data;
wire pipex_dp_ex1_mult_id;
wire [4 :0] pipex_dp_ex3_vfmau_ereg_data;
wire [63:0] pipex_dp_ex3_vfmau_freg_data;
wire [4 :0] pipex_dp_ex4_vfmau_ereg_data;
wire [63:0] pipex_dp_ex4_vfmau_freg_data;
wire pipex_pipe6_ex4_fmla_fwd_vld;
wire pipex_pipe6_ex5_ex1_fmla_fwd_vld;
wire pipex_pipe6_ex5_ex2_fmla_fwd_vld;
wire pipex_pipe7_ex4_fmla_fwd_vld;
wire pipex_pipe7_ex5_ex1_fmla_fwd_vld;
wire pipex_pipe7_ex5_ex2_fmla_fwd_vld;
wire pipex_rbus_ex1_fmla_data_vld;
wire pipex_rbus_ex1_fmla_data_vld_dup0;
wire pipex_rbus_ex1_fmla_data_vld_dup1;
wire pipex_rbus_ex1_fmla_data_vld_dup2;
wire pipex_rbus_ex2_fmla_data_vld;
wire pipex_rbus_ex2_fmla_data_vld_dup0;
wire pipex_rbus_ex2_fmla_data_vld_dup1;
wire pipex_rbus_ex2_fmla_data_vld_dup2;
wire pipex_rbus_pipe6_fmla_no_fwd;
wire pipex_rbus_pipe7_fmla_no_fwd;
wire [4 :0] pipex_rbus_vfmau_ereg_wb_data;
wire pipex_rbus_vfmau_ereg_wb_vld;
wire [63:0] pipex_rbus_vfmau_freg_wb_data;
wire pipex_rbus_vfmau_vreg_wb_vld;
wire [15:0] pipex_vfmau_ex4_fmla_slice0_half0_data;
wire [67:0] pipex_vfmau_ex5_fmla_slice0_data;
wire rtu_yy_xx_flush;
wire slice0_dp_half0_mult_id;
wire slice0_dp_mult1_mult_id;
wire [4 :0] slice0_mult1_dp_ex3_mult_expt;
wire [63:0] slice0_mult1_dp_ex3_mult_result;
wire [4 :0] slice0_mult1_dp_ex4_expt;
wire [15:0] slice0_mult1_dp_ex4_half_fma_result;
wire [63:0] slice0_mult1_dp_ex4_mult_result;
wire [4 :0] slice0_mult1_dp_ex5_fma_expt;
wire [63:0] slice0_mult1_dp_ex5_fma_result;
wire [67:0] slice0_mult1_dp_ex5_fwd_data;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Depend("cpu_cfig.h"); @28
// &Instance("ct_vfmau_ctrl","x_ct_vfmau_ctrl"); @30
ct_vfmau_ctrl x_ct_vfmau_ctrl (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_dp_ex5_fma_wb_vld (ctrl_dp_ex5_fma_wb_vld ),
.ctrl_ex1_ex2_en (ctrl_ex1_ex2_en ),
.ctrl_ex1_inst_vld (ctrl_ex1_inst_vld ),
.ctrl_ex2_inst_vld (ctrl_ex2_inst_vld ),
.ctrl_ex3_inst_vld (ctrl_ex3_inst_vld ),
.ctrl_ex4_inst_vld (ctrl_ex4_inst_vld ),
.ctrl_ex5_inst_vld (ctrl_ex5_inst_vld ),
.dp_vfmau_ex1_pipex_sel (dp_vfmau_ex1_pipex_sel ),
.dp_xx_ex1_half (dp_xx_ex1_half ),
.dp_xx_ex2_half (dp_xx_ex2_half ),
.dp_xx_ex3_fma (dp_xx_ex3_fma ),
.dp_xx_ex3_half (dp_xx_ex3_half ),
.dp_xx_ex4_fma (dp_xx_ex4_fma ),
.dp_xx_ex4_half (dp_xx_ex4_half ),
.dp_xx_ex4_mult_id (dp_xx_ex4_mult_id ),
.forever_cpuclk (forever_cpuclk ),
.mult1_ex1_ex2_pipedown (mult1_ex1_ex2_pipedown ),
.mult1_ex2_ex3_pipedown (mult1_ex2_ex3_pipedown ),
.mult1_ex3_ex4_pipedown (mult1_ex3_ex4_pipedown ),
.mult1_ex4_ex5_pipedown (mult1_ex4_ex5_pipedown ),
.mult_ex1_ex2_half_pipedown (mult_ex1_ex2_half_pipedown),
.mult_ex2_ex3_half_pipedown (mult_ex2_ex3_half_pipedown),
.mult_ex3_ex4_half_pipedown (mult_ex3_ex4_half_pipedown),
.mult_ex4_ex5_half_pipedown (mult_ex4_ex5_half_pipedown),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.rtu_yy_xx_flush (rtu_yy_xx_flush )
);
// &Instance("ct_vfmau_dp","x_ct_vfmau_dp"); @31
ct_vfmau_dp x_ct_vfmau_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ctrl_dp_ex5_fma_wb_vld (ctrl_dp_ex5_fma_wb_vld ),
.ctrl_ex1_ex2_en (ctrl_ex1_ex2_en ),
.ctrl_ex1_inst_vld (ctrl_ex1_inst_vld ),
.ctrl_ex2_inst_vld (ctrl_ex2_inst_vld ),
.ctrl_ex3_inst_vld (ctrl_ex3_inst_vld ),
.ctrl_ex4_inst_vld (ctrl_ex4_inst_vld ),
.ctrl_ex5_inst_vld (ctrl_ex5_inst_vld ),
.dp_mult1_ex1_op0_slice0 (dp_mult1_ex1_op0_slice0 ),
.dp_mult1_ex1_op0_slice0_high (dp_mult1_ex1_op0_slice0_high ),
.dp_mult1_ex1_op1_slice0 (dp_mult1_ex1_op1_slice0 ),
.dp_mult1_ex1_op1_slice0_high (dp_mult1_ex1_op1_slice0_high ),
.dp_mult1_ex1_op2_slice0 (dp_mult1_ex1_op2_slice0 ),
.dp_mult1_ex1_op2_slice0_high (dp_mult1_ex1_op2_slice0_high ),
.dp_mult1_op2_slice0_vl_mask (dp_mult1_op2_slice0_vl_mask ),
.dp_mult1_op2_slice0_vm_mask (dp_mult1_op2_slice0_vm_mask ),
.dp_mult_ex1_op0_slice0_half0 (dp_mult_ex1_op0_slice0_half0 ),
.dp_mult_ex1_op0_slice0_half0_high (dp_mult_ex1_op0_slice0_half0_high ),
.dp_mult_ex1_op1_slice0_half0 (dp_mult_ex1_op1_slice0_half0 ),
.dp_mult_ex1_op1_slice0_half0_high (dp_mult_ex1_op1_slice0_half0_high ),
.dp_mult_ex1_op2_slice0_half0 (dp_mult_ex1_op2_slice0_half0 ),
.dp_mult_ex1_op2_slice0_half0_high (dp_mult_ex1_op2_slice0_half0_high ),
.dp_mult_op2_slice0_vl_half0_mask (dp_mult_op2_slice0_vl_half0_mask ),
.dp_mult_op2_slice0_vm_half0_mask (dp_mult_op2_slice0_vm_half0_mask ),
.dp_vfmau_ex1_pipex_dst_vreg (dp_vfmau_ex1_pipex_dst_vreg ),
.dp_vfmau_ex1_pipex_imm0 (dp_vfmau_ex1_pipex_imm0 ),
.dp_vfmau_pipe6_mla_srcv2_vld (dp_vfmau_pipe6_mla_srcv2_vld ),
.dp_vfmau_pipe6_mla_srcv2_vreg (dp_vfmau_pipe6_mla_srcv2_vreg ),
.dp_vfmau_pipe6_mla_type (dp_vfmau_pipe6_mla_type ),
.dp_vfmau_pipe7_mla_srcv2_vld (dp_vfmau_pipe7_mla_srcv2_vld ),
.dp_vfmau_pipe7_mla_srcv2_vreg (dp_vfmau_pipe7_mla_srcv2_vreg ),
.dp_vfmau_pipe7_mla_type (dp_vfmau_pipe7_mla_type ),
.dp_vfmau_pipex_inst_type (dp_vfmau_pipex_inst_type ),
.dp_vfmau_pipex_sel (dp_vfmau_pipex_sel ),
.dp_vfmau_pipex_vfmau_sel (dp_vfmau_pipex_vfmau_sel ),
.dp_vfmau_rf_pipex_sel (dp_vfmau_rf_pipex_sel ),
.dp_xx_ex1_double (dp_xx_ex1_double ),
.dp_xx_ex1_fma (dp_xx_ex1_fma ),
.dp_xx_ex1_half (dp_xx_ex1_half ),
.dp_xx_ex1_neg (dp_xx_ex1_neg ),
.dp_xx_ex1_op0_frac (dp_xx_ex1_op0_frac ),
.dp_xx_ex1_op1_frac (dp_xx_ex1_op1_frac ),
.dp_xx_ex1_rm (dp_xx_ex1_rm ),
.dp_xx_ex1_simd (dp_xx_ex1_simd ),
.dp_xx_ex1_single (dp_xx_ex1_single ),
.dp_xx_ex1_sub (dp_xx_ex1_sub ),
.dp_xx_ex1_widen (dp_xx_ex1_widen ),
.dp_xx_ex2_double (dp_xx_ex2_double ),
.dp_xx_ex2_fma (dp_xx_ex2_fma ),
.dp_xx_ex2_half (dp_xx_ex2_half ),
.dp_xx_ex2_mult_id (dp_xx_ex2_mult_id ),
.dp_xx_ex2_neg (dp_xx_ex2_neg ),
.dp_xx_ex2_rm (dp_xx_ex2_rm ),
.dp_xx_ex2_simd (dp_xx_ex2_simd ),
.dp_xx_ex2_sub (dp_xx_ex2_sub ),
.dp_xx_ex2_widen (dp_xx_ex2_widen ),
.dp_xx_ex3_double (dp_xx_ex3_double ),
.dp_xx_ex3_fma (dp_xx_ex3_fma ),
.dp_xx_ex3_half (dp_xx_ex3_half ),
.dp_xx_ex3_mult_id (dp_xx_ex3_mult_id ),
.dp_xx_ex3_rm (dp_xx_ex3_rm ),
.dp_xx_ex3_simd (dp_xx_ex3_simd ),
.dp_xx_ex3_widen (dp_xx_ex3_widen ),
.dp_xx_ex4_double (dp_xx_ex4_double ),
.dp_xx_ex4_fma (dp_xx_ex4_fma ),
.dp_xx_ex4_half (dp_xx_ex4_half ),
.dp_xx_ex4_mult_id (dp_xx_ex4_mult_id ),
.dp_xx_ex4_rm (dp_xx_ex4_rm ),
.forever_cpuclk (forever_cpuclk ),
.idu_vfpu_rf_pipex_func (idu_vfpu_rf_pipex_func ),
.idu_vfpu_rf_pipex_gateclk_sel (idu_vfpu_rf_pipex_gateclk_sel ),
.idu_vfpu_rf_pipex_srcv0_fr (idu_vfpu_rf_pipex_srcv0_fr ),
.idu_vfpu_rf_pipex_srcv1_fr (idu_vfpu_rf_pipex_srcv1_fr ),
.idu_vfpu_rf_pipex_srcv2_fr (idu_vfpu_rf_pipex_srcv2_fr ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pipex_dp_ex1_mult_id (pipex_dp_ex1_mult_id ),
.pipex_dp_ex3_vfmau_ereg_data (pipex_dp_ex3_vfmau_ereg_data ),
.pipex_dp_ex3_vfmau_freg_data (pipex_dp_ex3_vfmau_freg_data ),
.pipex_dp_ex4_vfmau_ereg_data (pipex_dp_ex4_vfmau_ereg_data ),
.pipex_dp_ex4_vfmau_freg_data (pipex_dp_ex4_vfmau_freg_data ),
.pipex_pipe6_ex4_fmla_fwd_vld (pipex_pipe6_ex4_fmla_fwd_vld ),
.pipex_pipe6_ex5_ex1_fmla_fwd_vld (pipex_pipe6_ex5_ex1_fmla_fwd_vld ),
.pipex_pipe6_ex5_ex2_fmla_fwd_vld (pipex_pipe6_ex5_ex2_fmla_fwd_vld ),
.pipex_pipe7_ex4_fmla_fwd_vld (pipex_pipe7_ex4_fmla_fwd_vld ),
.pipex_pipe7_ex5_ex1_fmla_fwd_vld (pipex_pipe7_ex5_ex1_fmla_fwd_vld ),
.pipex_pipe7_ex5_ex2_fmla_fwd_vld (pipex_pipe7_ex5_ex2_fmla_fwd_vld ),
.pipex_rbus_ex1_fmla_data_vld (pipex_rbus_ex1_fmla_data_vld ),
.pipex_rbus_ex1_fmla_data_vld_dup0 (pipex_rbus_ex1_fmla_data_vld_dup0 ),
.pipex_rbus_ex1_fmla_data_vld_dup1 (pipex_rbus_ex1_fmla_data_vld_dup1 ),
.pipex_rbus_ex1_fmla_data_vld_dup2 (pipex_rbus_ex1_fmla_data_vld_dup2 ),
.pipex_rbus_ex2_fmla_data_vld (pipex_rbus_ex2_fmla_data_vld ),
.pipex_rbus_ex2_fmla_data_vld_dup0 (pipex_rbus_ex2_fmla_data_vld_dup0 ),
.pipex_rbus_ex2_fmla_data_vld_dup1 (pipex_rbus_ex2_fmla_data_vld_dup1 ),
.pipex_rbus_ex2_fmla_data_vld_dup2 (pipex_rbus_ex2_fmla_data_vld_dup2 ),
.pipex_rbus_pipe6_fmla_no_fwd (pipex_rbus_pipe6_fmla_no_fwd ),
.pipex_rbus_pipe7_fmla_no_fwd (pipex_rbus_pipe7_fmla_no_fwd ),
.pipex_rbus_vfmau_ereg_wb_data (pipex_rbus_vfmau_ereg_wb_data ),
.pipex_rbus_vfmau_ereg_wb_vld (pipex_rbus_vfmau_ereg_wb_vld ),
.pipex_rbus_vfmau_freg_wb_data (pipex_rbus_vfmau_freg_wb_data ),
.pipex_rbus_vfmau_vreg_wb_vld (pipex_rbus_vfmau_vreg_wb_vld ),
.pipex_vfmau_ex4_fmla_slice0_half0_data (pipex_vfmau_ex4_fmla_slice0_half0_data),
.pipex_vfmau_ex5_fmla_slice0_data (pipex_vfmau_ex5_fmla_slice0_data ),
.rtu_yy_xx_flush (rtu_yy_xx_flush ),
.slice0_dp_half0_mult_id (slice0_dp_half0_mult_id ),
.slice0_dp_mult1_mult_id (slice0_dp_mult1_mult_id ),
.slice0_mult1_dp_ex3_mult_expt (slice0_mult1_dp_ex3_mult_expt ),
.slice0_mult1_dp_ex3_mult_result (slice0_mult1_dp_ex3_mult_result ),
.slice0_mult1_dp_ex4_expt (slice0_mult1_dp_ex4_expt ),
.slice0_mult1_dp_ex4_half_fma_result (slice0_mult1_dp_ex4_half_fma_result ),
.slice0_mult1_dp_ex4_mult_result (slice0_mult1_dp_ex4_mult_result ),
.slice0_mult1_dp_ex5_fma_expt (slice0_mult1_dp_ex5_fma_expt ),
.slice0_mult1_dp_ex5_fma_result (slice0_mult1_dp_ex5_fma_result ),
.slice0_mult1_dp_ex5_fwd_data (slice0_mult1_dp_ex5_fwd_data ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &ConnRule(s/slicex/slice0/); @33
// &Instance("ct_vfmau_mult1","x_ct_vfmau_mult1_slice0"); @34
// &Connect(.dp_mult1_slicem (1'b1), @35
// .dp_mult1_slicen (1'b0), @36
// .dp_mult1_ex1_clk_en (1'b1), @37
// .dp_mult1_ex2_clk_en (1'b1), @38
// .dp_mult1_ex3_clk_en (1'b1), @39
// .dp_mult1_ex4_clk_en (1'b1) @40
// ); @41
// &ConnRule(s/slicex/slice1/); @43
// &Instance("ct_vfmau_mult1","x_ct_vfmau_mult1_slice1"); @44
// &Connect(.dp_mult1_slicem (1'b0), @45
// .dp_mult1_slicen (1'b1) @46
// .dp_mult1_ex1_clk_en (dp_xx_ex1_simd), @47
// .dp_mult1_ex2_clk_en (dp_xx_ex2_simd), @48
// .dp_mult1_ex3_clk_en (dp_xx_ex3_simd), @49
// .dp_mult1_ex4_clk_en (dp_xx_ex4_simd) @50
// ); @51
// &ConnRule(s/slicex/slice0/); @53
// &Instance("ct_vfmau_mult1","x_ct_vfmau_mult1_slice0"); @54
ct_vfmau_mult1 x_ct_vfmau_mult1_slice0 (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_mult1_ex1_clk_en (1'b1 ),
.dp_mult1_ex1_op0_slicex (dp_mult1_ex1_op0_slice0 ),
.dp_mult1_ex1_op0_slicex_high (dp_mult1_ex1_op0_slice0_high ),
.dp_mult1_ex1_op1_slicex (dp_mult1_ex1_op1_slice0 ),
.dp_mult1_ex1_op1_slicex_high (dp_mult1_ex1_op1_slice0_high ),
.dp_mult1_ex1_op2_slicex (dp_mult1_ex1_op2_slice0 ),
.dp_mult1_ex1_op2_slicex_high (dp_mult1_ex1_op2_slice0_high ),
.dp_mult1_ex2_clk_en (1'b1 ),
.dp_mult1_ex3_clk_en (1'b1 ),
.dp_mult1_ex4_clk_en (1'b1 ),
.dp_mult1_op2_slicex_vl_mask (dp_mult1_op2_slice0_vl_mask ),
.dp_mult1_op2_slicex_vm_mask (dp_mult1_op2_slice0_vm_mask ),
.dp_mult_ex1_op0_slicex_half0 (dp_mult_ex1_op0_slice0_half0 ),
.dp_mult_ex1_op0_slicex_half0_high (dp_mult_ex1_op0_slice0_half0_high ),
.dp_mult_ex1_op1_slicex_half0 (dp_mult_ex1_op1_slice0_half0 ),
.dp_mult_ex1_op1_slicex_half0_high (dp_mult_ex1_op1_slice0_half0_high ),
.dp_mult_ex1_op2_slicex_half0 (dp_mult_ex1_op2_slice0_half0 ),
.dp_mult_ex1_op2_slicex_half0_high (dp_mult_ex1_op2_slice0_half0_high ),
.dp_mult_op2_slicex_vl_half0_mask (dp_mult_op2_slice0_vl_half0_mask ),
.dp_mult_op2_slicex_vm_half0_mask (dp_mult_op2_slice0_vm_half0_mask ),
.dp_xx_ex1_double (dp_xx_ex1_double ),
.dp_xx_ex1_fma (dp_xx_ex1_fma ),
.dp_xx_ex1_half (dp_xx_ex1_half ),
.dp_xx_ex1_neg (dp_xx_ex1_neg ),
.dp_xx_ex1_op0_frac (dp_xx_ex1_op0_frac ),
.dp_xx_ex1_op1_frac (dp_xx_ex1_op1_frac ),
.dp_xx_ex1_rm (dp_xx_ex1_rm ),
.dp_xx_ex1_simd (dp_xx_ex1_simd ),
.dp_xx_ex1_single (dp_xx_ex1_single ),
.dp_xx_ex1_sub (dp_xx_ex1_sub ),
.dp_xx_ex1_widen (dp_xx_ex1_widen ),
.dp_xx_ex2_double (dp_xx_ex2_double ),
.dp_xx_ex2_fma (dp_xx_ex2_fma ),
.dp_xx_ex2_half (dp_xx_ex2_half ),
.dp_xx_ex2_mult_id (dp_xx_ex2_mult_id ),
.dp_xx_ex2_neg (dp_xx_ex2_neg ),
.dp_xx_ex2_rm (dp_xx_ex2_rm ),
.dp_xx_ex2_simd (dp_xx_ex2_simd ),
.dp_xx_ex2_sub (dp_xx_ex2_sub ),
.dp_xx_ex2_widen (dp_xx_ex2_widen ),
.dp_xx_ex3_double (dp_xx_ex3_double ),
.dp_xx_ex3_fma (dp_xx_ex3_fma ),
.dp_xx_ex3_half (dp_xx_ex3_half ),
.dp_xx_ex3_mult_id (dp_xx_ex3_mult_id ),
.dp_xx_ex3_rm (dp_xx_ex3_rm ),
.dp_xx_ex3_simd (dp_xx_ex3_simd ),
.dp_xx_ex3_widen (dp_xx_ex3_widen ),
.dp_xx_ex4_double (dp_xx_ex4_double ),
.dp_xx_ex4_half (dp_xx_ex4_half ),
.dp_xx_ex4_rm (dp_xx_ex4_rm ),
.forever_cpuclk (forever_cpuclk ),
.mult1_ex1_ex2_pipedown (mult1_ex1_ex2_pipedown ),
.mult1_ex2_ex3_pipedown (mult1_ex2_ex3_pipedown ),
.mult1_ex3_ex4_pipedown (mult1_ex3_ex4_pipedown ),
.mult1_ex4_ex5_pipedown (mult1_ex4_ex5_pipedown ),
.mult_ex1_ex2_half_pipedown (mult_ex1_ex2_half_pipedown ),
.mult_ex2_ex3_half_pipedown (mult_ex2_ex3_half_pipedown ),
.mult_ex3_ex4_half_pipedown (mult_ex3_ex4_half_pipedown ),
.mult_ex4_ex5_half_pipedown (mult_ex4_ex5_half_pipedown ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pipe6_pipex_ex4_fmla_fwd_vld (pipe6_pipex_ex4_fmla_fwd_vld ),
.pipe6_pipex_ex5_ex1_fmla_fwd_vld (pipe6_pipex_ex5_ex1_fmla_fwd_vld ),
.pipe6_pipex_ex5_ex2_fmla_fwd_vld (pipe6_pipex_ex5_ex2_fmla_fwd_vld ),
.pipe6_vfmau_ex4_fmla_slicex_half0_data (pipe6_vfmau_ex4_fmla_slice0_half0_data),
.pipe6_vfmau_ex5_fmla_slicex_data (pipe6_vfmau_ex5_fmla_slice0_data ),
.pipe7_pipex_ex4_fmla_fwd_vld (pipe7_pipex_ex4_fmla_fwd_vld ),
.pipe7_pipex_ex5_ex1_fmla_fwd_vld (pipe7_pipex_ex5_ex1_fmla_fwd_vld ),
.pipe7_pipex_ex5_ex2_fmla_fwd_vld (pipe7_pipex_ex5_ex2_fmla_fwd_vld ),
.pipe7_vfmau_ex4_fmla_slicex_half0_data (pipe7_vfmau_ex4_fmla_slice0_half0_data),
.pipe7_vfmau_ex5_fmla_slicex_data (pipe7_vfmau_ex5_fmla_slice0_data ),
.slicex_dp_half0_mult_id (slice0_dp_half0_mult_id ),
.slicex_dp_mult1_mult_id (slice0_dp_mult1_mult_id ),
.slicex_mult1_dp_ex3_mult_expt (slice0_mult1_dp_ex3_mult_expt ),
.slicex_mult1_dp_ex3_mult_result (slice0_mult1_dp_ex3_mult_result ),
.slicex_mult1_dp_ex4_expt (slice0_mult1_dp_ex4_expt ),
.slicex_mult1_dp_ex4_half_fma_result (slice0_mult1_dp_ex4_half_fma_result ),
.slicex_mult1_dp_ex4_mult_result (slice0_mult1_dp_ex4_mult_result ),
.slicex_mult1_dp_ex5_fma_expt (slice0_mult1_dp_ex5_fma_expt ),
.slicex_mult1_dp_ex5_fma_result (slice0_mult1_dp_ex5_fma_result ),
.slicex_mult1_dp_ex5_fwd_data (slice0_mult1_dp_ex5_fwd_data ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan )
);
// &Connect(.dp_mult1_ex1_clk_en (1'b1), @55
// .dp_mult1_ex2_clk_en (1'b1), @56
// .dp_mult1_ex3_clk_en (1'b1), @57
// .dp_mult1_ex4_clk_en (1'b1) @58
// ); @59
// &ModuleEnd; @62
endmodule |
module ct_vfmau_lza_42(
lza_p0,
lza_p1,
lza_precod,
lza_vld
);
// &Ports; @24
input [3:0] lza_precod;
output lza_p0;
output lza_p1;
output lza_vld;
// &Regs; @25
// &Wires; @26
wire lza_p0;
wire lza_p1;
wire [3:0] lza_precod;
wire lza_vld;
assign lza_vld = |lza_precod[3:0];
assign lza_p0 = !lza_precod[3] && (lza_precod[2] || !lza_precod[1]);
assign lza_p1 = !(lza_precod[2] || lza_precod[3]);
// &ModuleEnd; @32
endmodule |
module ct_vfmau_lza(
addend,
lza_result,
sub_vld,
summand
);
// &Ports; @24
input [107:0] addend;
input sub_vld;
input [107:0] summand;
output [6 :0] lza_result;
// &Regs; @25
reg [3 :0] high_l2_set0_encod;
reg [3 :0] high_l2_set1_encod;
reg [3 :0] high_l2_set2_encod;
reg [3 :0] high_l2_set3_encod;
reg [5 :0] high_l3_set0_encod;
reg [3 :0] low_l2_set0_encod;
reg [3 :0] low_l2_set1_encod;
reg [3 :0] low_l2_set2_encod;
reg [5 :0] low_l3_set0_encod;
// &Wires; @26
wire [107:0] addend;
wire [107:0] carry_d;
wire [107:0] carry_g;
wire [107:0] carry_p;
wire [31 :0] high_l1_encod;
wire [15 :0] high_l1_vld;
wire [7 :0] high_l2_encod;
wire [3 :0] high_l2_vld;
wire [1 :0] high_l3_encod;
wire high_l3_vld;
wire [21 :0] low_l1_encod;
wire [10 :0] low_l1_vld;
wire [5 :0] low_l2_encod;
wire [2 :0] low_l2_vld;
wire [1 :0] low_l3_encod;
wire low_l3_vld;
wire [6 :0] lza_l4_encod;
wire [107:0] lza_precod;
wire [6 :0] lza_result;
wire lza_result_vld;
wire sub_vld;
wire [107:0] summand;
//==========================================================
// Signal Pre-encode
//==========================================================
//----------------------------------------------------------
// Signal preparation
//----------------------------------------------------------
// carry_p: carry propagete
// carry_g: carry generate
// carry_d: carry delete
assign carry_p[107:0] = summand[107:0] ^ addend[107:0];
assign carry_g[107:0] = summand[107:0] & addend[107:0];
assign carry_d[107:0] = ~(summand[107:0] | addend[107:0]);
//----------------------------------------------------------
// Signal decode
//----------------------------------------------------------
//pre-predecode for leading zero anticipation
assign lza_precod[0] =
carry_p[1] && (carry_g[0] && sub_vld || carry_d[0])
|| !carry_p[1] && (carry_d[0] && sub_vld || carry_g[0]);
assign lza_precod[107] =
sub_vld && (carry_g[107] && !carry_d[106] || carry_d[107] && !carry_g[106])
|| !sub_vld && (carry_d[107] && !carry_d[106] || !carry_d[107]);
assign lza_precod[106:1] =
carry_p[107:2] & (carry_g[106:1] & ~carry_d[105:0] | carry_d[106:1] & ~carry_g[105:0])
| ~carry_p[107:2] & (carry_g[106:1] & ~carry_g[105:0] | carry_d[106:1] & ~carry_d[105:0]);
//==========================================================
// LZA coding
//==========================================================
//----------------------------------------------------------
// high 64-bit lza encoder
//----------------------------------------------------------
//first level : 64:16 compressor , 16 4:2 lza_compressor
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_0"); @64
ct_vfmau_lza_42 x_ct_vfmau_lza_42_0 (
.lza_p0 (high_l1_encod[0] ),
.lza_p1 (high_l1_encod[1] ),
.lza_precod (lza_precod[107:104]),
.lza_vld (high_l1_vld[15] )
);
// &Connect(.lza_precod (lza_precod[107:104] ), @65
// .lza_vld (high_l1_vld[15] ), @66
// .lza_p0 (high_l1_encod[0] ), @67
// .lza_p1 (high_l1_encod[1] )); @68
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_1"); @70
ct_vfmau_lza_42 x_ct_vfmau_lza_42_1 (
.lza_p0 (high_l1_encod[2] ),
.lza_p1 (high_l1_encod[3] ),
.lza_precod (lza_precod[103:100]),
.lza_vld (high_l1_vld[14] )
);
// &Connect(.lza_precod (lza_precod[103:100] ), @71
// .lza_vld (high_l1_vld[14] ), @72
// .lza_p0 (high_l1_encod[2] ), @73
// .lza_p1 (high_l1_encod[3] )); @74
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_2"); @76
ct_vfmau_lza_42 x_ct_vfmau_lza_42_2 (
.lza_p0 (high_l1_encod[4] ),
.lza_p1 (high_l1_encod[5] ),
.lza_precod (lza_precod[99:96]),
.lza_vld (high_l1_vld[13] )
);
// &Connect(.lza_precod (lza_precod[99:96] ), @77
// .lza_vld (high_l1_vld[13] ), @78
// .lza_p0 (high_l1_encod[4] ), @79
// .lza_p1 (high_l1_encod[5] )); @80
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_3"); @82
ct_vfmau_lza_42 x_ct_vfmau_lza_42_3 (
.lza_p0 (high_l1_encod[6] ),
.lza_p1 (high_l1_encod[7] ),
.lza_precod (lza_precod[95:92]),
.lza_vld (high_l1_vld[12] )
);
// &Connect(.lza_precod (lza_precod[95:92] ), @83
// .lza_vld (high_l1_vld[12] ), @84
// .lza_p0 (high_l1_encod[6] ), @85
// .lza_p1 (high_l1_encod[7] )); @86
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_4"); @88
ct_vfmau_lza_42 x_ct_vfmau_lza_42_4 (
.lza_p0 (high_l1_encod[8] ),
.lza_p1 (high_l1_encod[9] ),
.lza_precod (lza_precod[91:88]),
.lza_vld (high_l1_vld[11] )
);
// &Connect(.lza_precod (lza_precod[91:88] ), @89
// .lza_vld (high_l1_vld[11] ), @90
// .lza_p0 (high_l1_encod[8] ), @91
// .lza_p1 (high_l1_encod[9] )); @92
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_5"); @94
ct_vfmau_lza_42 x_ct_vfmau_lza_42_5 (
.lza_p0 (high_l1_encod[10]),
.lza_p1 (high_l1_encod[11]),
.lza_precod (lza_precod[87:84]),
.lza_vld (high_l1_vld[10] )
);
// &Connect(.lza_precod (lza_precod[87:84] ), @95
// .lza_vld (high_l1_vld[10] ), @96
// .lza_p0 (high_l1_encod[10] ), @97
// .lza_p1 (high_l1_encod[11] )); @98
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_6"); @100
ct_vfmau_lza_42 x_ct_vfmau_lza_42_6 (
.lza_p0 (high_l1_encod[12]),
.lza_p1 (high_l1_encod[13]),
.lza_precod (lza_precod[83:80]),
.lza_vld (high_l1_vld[9] )
);
// &Connect(.lza_precod (lza_precod[83:80] ), @101
// .lza_vld (high_l1_vld[9] ), @102
// .lza_p0 (high_l1_encod[12] ), @103
// .lza_p1 (high_l1_encod[13] )); @104
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_7"); @106
ct_vfmau_lza_42 x_ct_vfmau_lza_42_7 (
.lza_p0 (high_l1_encod[14]),
.lza_p1 (high_l1_encod[15]),
.lza_precod (lza_precod[79:76]),
.lza_vld (high_l1_vld[8] )
);
// &Connect(.lza_precod (lza_precod[79:76] ), @107
// .lza_vld (high_l1_vld[8] ), @108
// .lza_p0 (high_l1_encod[14] ), @109
// .lza_p1 (high_l1_encod[15] )); @110
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_8"); @112
ct_vfmau_lza_42 x_ct_vfmau_lza_42_8 (
.lza_p0 (high_l1_encod[16]),
.lza_p1 (high_l1_encod[17]),
.lza_precod (lza_precod[75:72]),
.lza_vld (high_l1_vld[7] )
);
// &Connect(.lza_precod (lza_precod[75:72] ), @113
// .lza_vld (high_l1_vld[7] ), @114
// .lza_p0 (high_l1_encod[16] ), @115
// .lza_p1 (high_l1_encod[17] )); @116
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_9"); @118
ct_vfmau_lza_42 x_ct_vfmau_lza_42_9 (
.lza_p0 (high_l1_encod[18]),
.lza_p1 (high_l1_encod[19]),
.lza_precod (lza_precod[71:68]),
.lza_vld (high_l1_vld[6] )
);
// &Connect(.lza_precod (lza_precod[71:68] ), @119
// .lza_vld (high_l1_vld[6] ), @120
// .lza_p0 (high_l1_encod[18] ), @121
// .lza_p1 (high_l1_encod[19] )); @122
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_10"); @124
ct_vfmau_lza_42 x_ct_vfmau_lza_42_10 (
.lza_p0 (high_l1_encod[20]),
.lza_p1 (high_l1_encod[21]),
.lza_precod (lza_precod[67:64]),
.lza_vld (high_l1_vld[5] )
);
// &Connect(.lza_precod (lza_precod[67:64] ), @125
// .lza_vld (high_l1_vld[5] ), @126
// .lza_p0 (high_l1_encod[20] ), @127
// .lza_p1 (high_l1_encod[21] )); @128
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_11"); @130
ct_vfmau_lza_42 x_ct_vfmau_lza_42_11 (
.lza_p0 (high_l1_encod[22]),
.lza_p1 (high_l1_encod[23]),
.lza_precod (lza_precod[63:60]),
.lza_vld (high_l1_vld[4] )
);
// &Connect(.lza_precod (lza_precod[63:60] ), @131
// .lza_vld (high_l1_vld[4] ), @132
// .lza_p0 (high_l1_encod[22] ), @133
// .lza_p1 (high_l1_encod[23] )); @134
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_12"); @136
ct_vfmau_lza_42 x_ct_vfmau_lza_42_12 (
.lza_p0 (high_l1_encod[24]),
.lza_p1 (high_l1_encod[25]),
.lza_precod (lza_precod[59:56]),
.lza_vld (high_l1_vld[3] )
);
// &Connect(.lza_precod (lza_precod[59:56] ), @137
// .lza_vld (high_l1_vld[3] ), @138
// .lza_p0 (high_l1_encod[24] ), @139
// .lza_p1 (high_l1_encod[25] )); @140
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_13"); @142
ct_vfmau_lza_42 x_ct_vfmau_lza_42_13 (
.lza_p0 (high_l1_encod[26]),
.lza_p1 (high_l1_encod[27]),
.lza_precod (lza_precod[55:52]),
.lza_vld (high_l1_vld[2] )
);
// &Connect(.lza_precod (lza_precod[55:52] ), @143
// .lza_vld (high_l1_vld[2] ), @144
// .lza_p0 (high_l1_encod[26] ), @145
// .lza_p1 (high_l1_encod[27] )); @146
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_14"); @148
ct_vfmau_lza_42 x_ct_vfmau_lza_42_14 (
.lza_p0 (high_l1_encod[28]),
.lza_p1 (high_l1_encod[29]),
.lza_precod (lza_precod[51:48]),
.lza_vld (high_l1_vld[1] )
);
// &Connect(.lza_precod (lza_precod[51:48] ), @149
// .lza_vld (high_l1_vld[1] ), @150
// .lza_p0 (high_l1_encod[28] ), @151
// .lza_p1 (high_l1_encod[29] )); @152
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_15"); @154
ct_vfmau_lza_42 x_ct_vfmau_lza_42_15 (
.lza_p0 (high_l1_encod[30]),
.lza_p1 (high_l1_encod[31]),
.lza_precod (lza_precod[47:44]),
.lza_vld (high_l1_vld[0] )
);
// &Connect(.lza_precod (lza_precod[47:44] ), @155
// .lza_vld (high_l1_vld[0] ), @156
// .lza_p0 (high_l1_encod[30] ), @157
// .lza_p1 (high_l1_encod[31] )); @158
//second level : 16:4 compressor , 4 4:2 lza_compressor
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_16"); @161
ct_vfmau_lza_42 x_ct_vfmau_lza_42_16 (
.lza_p0 (high_l2_encod[0] ),
.lza_p1 (high_l2_encod[1] ),
.lza_precod (high_l1_vld[15:12]),
.lza_vld (high_l2_vld[3] )
);
// &Connect(.lza_precod (high_l1_vld[15:12] ), @162
// .lza_vld (high_l2_vld[3] ), @163
// .lza_p0 (high_l2_encod[0] ), @164
// .lza_p1 (high_l2_encod[1] )); @165
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_17"); @167
ct_vfmau_lza_42 x_ct_vfmau_lza_42_17 (
.lza_p0 (high_l2_encod[2] ),
.lza_p1 (high_l2_encod[3] ),
.lza_precod (high_l1_vld[11:8]),
.lza_vld (high_l2_vld[2] )
);
// &Connect(.lza_precod (high_l1_vld[11:8] ), @168
// .lza_vld (high_l2_vld[2] ), @169
// .lza_p0 (high_l2_encod[2] ), @170
// .lza_p1 (high_l2_encod[3] )); @171
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_18"); @173
ct_vfmau_lza_42 x_ct_vfmau_lza_42_18 (
.lza_p0 (high_l2_encod[4]),
.lza_p1 (high_l2_encod[5]),
.lza_precod (high_l1_vld[7:4]),
.lza_vld (high_l2_vld[1] )
);
// &Connect(.lza_precod (high_l1_vld[7:4] ), @174
// .lza_vld (high_l2_vld[1] ), @175
// .lza_p0 (high_l2_encod[4] ), @176
// .lza_p1 (high_l2_encod[5] )); @177
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_19"); @179
ct_vfmau_lza_42 x_ct_vfmau_lza_42_19 (
.lza_p0 (high_l2_encod[6]),
.lza_p1 (high_l2_encod[7]),
.lza_precod (high_l1_vld[3:0]),
.lza_vld (high_l2_vld[0] )
);
// &Connect(.lza_precod (high_l1_vld[3:0]), @180
// .lza_vld (high_l2_vld[0] ), @181
// .lza_p0 (high_l2_encod[6] ), @182
// .lza_p1 (high_l2_encod[7] )); @183
// &CombBeg; @186
always @( high_l1_encod[3:0]
or high_l2_encod[1:0]
or high_l1_encod[7:4])
begin
case(high_l2_encod[1:0])
2'b00 : high_l2_set0_encod[3:0] = {2'b00,high_l1_encod[1:0]};
2'b01 : high_l2_set0_encod[3:0] = {2'b01,high_l1_encod[3:2]};
2'b10 : high_l2_set0_encod[3:0] = {2'b10,high_l1_encod[5:4]};
2'b11 : high_l2_set0_encod[3:0] = {2'b11,high_l1_encod[7:6]};
default : high_l2_set0_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @194
end
// &CombBeg; @196
always @( high_l2_encod[3:2]
or high_l1_encod[15:8])
begin
case(high_l2_encod[3:2])
2'b00 : high_l2_set1_encod[3:0] = {2'b00,high_l1_encod[9:8]};
2'b01 : high_l2_set1_encod[3:0] = {2'b01,high_l1_encod[11:10]};
2'b10 : high_l2_set1_encod[3:0] = {2'b10,high_l1_encod[13:12]};
2'b11 : high_l2_set1_encod[3:0] = {2'b11,high_l1_encod[15:14]};
default : high_l2_set1_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @204
end
// &CombBeg; @206
always @( high_l1_encod[23:18]
or high_l1_encod[17:16]
or high_l2_encod[5:4])
begin
case(high_l2_encod[5:4])
2'b00 : high_l2_set2_encod[3:0] = {2'b00,high_l1_encod[17:16]};
2'b01 : high_l2_set2_encod[3:0] = {2'b01,high_l1_encod[19:18]};
2'b10 : high_l2_set2_encod[3:0] = {2'b10,high_l1_encod[21:20]};
2'b11 : high_l2_set2_encod[3:0] = {2'b11,high_l1_encod[23:22]};
default : high_l2_set2_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @214
end
// &CombBeg; @216
always @( high_l1_encod[31:26]
or high_l1_encod[25:24]
or high_l2_encod[7:6])
begin
case(high_l2_encod[7:6])
2'b00 : high_l2_set3_encod[3:0] = {2'b00,high_l1_encod[25:24]};
2'b01 : high_l2_set3_encod[3:0] = {2'b01,high_l1_encod[27:26]};
2'b10 : high_l2_set3_encod[3:0] = {2'b10,high_l1_encod[29:28]};
2'b11 : high_l2_set3_encod[3:0] = {2'b11,high_l1_encod[31:30]};
default : high_l2_set3_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @224
end
//third level : :4:1 compressor , 1 4:2 lza_compressor
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_20"); @227
ct_vfmau_lza_42 x_ct_vfmau_lza_42_20 (
.lza_p0 (high_l3_encod[0]),
.lza_p1 (high_l3_encod[1]),
.lza_precod (high_l2_vld[3:0]),
.lza_vld (high_l3_vld )
);
// &Connect(.lza_precod (high_l2_vld[3:0]), @228
// .lza_vld (high_l3_vld ), @229
// .lza_p0 (high_l3_encod[0] ), @230
// .lza_p1 (high_l3_encod[1] )); @231
// &CombBeg; @233
always @( high_l2_set2_encod[3:0]
or high_l3_encod[1:0]
or high_l2_set3_encod[3:0]
or high_l2_set1_encod[3:0]
or high_l2_set0_encod[3:0])
begin
case(high_l3_encod[1:0])
2'b00 : high_l3_set0_encod[5:0] = {2'b00,high_l2_set0_encod[3:0]};
2'b01 : high_l3_set0_encod[5:0] = {2'b01,high_l2_set1_encod[3:0]};
2'b10 : high_l3_set0_encod[5:0] = {2'b10,high_l2_set2_encod[3:0]};
2'b11 : high_l3_set0_encod[5:0] = {2'b11,high_l2_set3_encod[3:0]};
default : high_l3_set0_encod[5:0] = {6{1'bx}};
endcase
// &CombEnd; @241
end
//----------------------------------------------------------
// low 44-bit lza encoder
//----------------------------------------------------------
//first level : 44:11 compressor , 11 4:2 lza_compressor
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_21"); @248
ct_vfmau_lza_42 x_ct_vfmau_lza_42_21 (
.lza_p0 (low_l1_encod[0] ),
.lza_p1 (low_l1_encod[1] ),
.lza_precod (lza_precod[43:40]),
.lza_vld (low_l1_vld[10] )
);
// &Connect(.lza_precod (lza_precod[43:40] ), @249
// .lza_vld (low_l1_vld[10] ), @250
// .lza_p0 (low_l1_encod[0] ), @251
// .lza_p1 (low_l1_encod[1] )); @252
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_22"); @254
ct_vfmau_lza_42 x_ct_vfmau_lza_42_22 (
.lza_p0 (low_l1_encod[2] ),
.lza_p1 (low_l1_encod[3] ),
.lza_precod (lza_precod[39:36]),
.lza_vld (low_l1_vld[9] )
);
// &Connect(.lza_precod (lza_precod[39:36] ), @255
// .lza_vld (low_l1_vld[9] ), @256
// .lza_p0 (low_l1_encod[2] ), @257
// .lza_p1 (low_l1_encod[3] )); @258
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_23"); @260
ct_vfmau_lza_42 x_ct_vfmau_lza_42_23 (
.lza_p0 (low_l1_encod[4] ),
.lza_p1 (low_l1_encod[5] ),
.lza_precod (lza_precod[35:32]),
.lza_vld (low_l1_vld[8] )
);
// &Connect(.lza_precod (lza_precod[35:32] ), @261
// .lza_vld (low_l1_vld[8] ), @262
// .lza_p0 (low_l1_encod[4] ), @263
// .lza_p1 (low_l1_encod[5] )); @264
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_24"); @266
ct_vfmau_lza_42 x_ct_vfmau_lza_42_24 (
.lza_p0 (low_l1_encod[6] ),
.lza_p1 (low_l1_encod[7] ),
.lza_precod (lza_precod[31:28]),
.lza_vld (low_l1_vld[7] )
);
// &Connect(.lza_precod (lza_precod[31:28] ), @267
// .lza_vld (low_l1_vld[7] ), @268
// .lza_p0 (low_l1_encod[6] ), @269
// .lza_p1 (low_l1_encod[7] )); @270
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_25"); @272
ct_vfmau_lza_42 x_ct_vfmau_lza_42_25 (
.lza_p0 (low_l1_encod[8] ),
.lza_p1 (low_l1_encod[9] ),
.lza_precod (lza_precod[27:24]),
.lza_vld (low_l1_vld[6] )
);
// &Connect(.lza_precod (lza_precod[27:24] ), @273
// .lza_vld (low_l1_vld[6] ), @274
// .lza_p0 (low_l1_encod[8] ), @275
// .lza_p1 (low_l1_encod[9] )); @276
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_26"); @278
ct_vfmau_lza_42 x_ct_vfmau_lza_42_26 (
.lza_p0 (low_l1_encod[10] ),
.lza_p1 (low_l1_encod[11] ),
.lza_precod (lza_precod[23:20]),
.lza_vld (low_l1_vld[5] )
);
// &Connect(.lza_precod (lza_precod[23:20] ), @279
// .lza_vld (low_l1_vld[5] ), @280
// .lza_p0 (low_l1_encod[10] ), @281
// .lza_p1 (low_l1_encod[11] )); @282
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_27"); @284
ct_vfmau_lza_42 x_ct_vfmau_lza_42_27 (
.lza_p0 (low_l1_encod[12] ),
.lza_p1 (low_l1_encod[13] ),
.lza_precod (lza_precod[19:16]),
.lza_vld (low_l1_vld[4] )
);
// &Connect(.lza_precod (lza_precod[19:16] ), @285
// .lza_vld (low_l1_vld[4] ), @286
// .lza_p0 (low_l1_encod[12] ), @287
// .lza_p1 (low_l1_encod[13] )); @288
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_28"); @290
ct_vfmau_lza_42 x_ct_vfmau_lza_42_28 (
.lza_p0 (low_l1_encod[14] ),
.lza_p1 (low_l1_encod[15] ),
.lza_precod (lza_precod[15:12]),
.lza_vld (low_l1_vld[3] )
);
// &Connect(.lza_precod (lza_precod[15:12] ), @291
// .lza_vld (low_l1_vld[3] ), @292
// .lza_p0 (low_l1_encod[14] ), @293
// .lza_p1 (low_l1_encod[15] )); @294
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_29"); @296
ct_vfmau_lza_42 x_ct_vfmau_lza_42_29 (
.lza_p0 (low_l1_encod[16]),
.lza_p1 (low_l1_encod[17]),
.lza_precod (lza_precod[11:8]),
.lza_vld (low_l1_vld[2] )
);
// &Connect(.lza_precod (lza_precod[11:8] ), @297
// .lza_vld (low_l1_vld[2] ), @298
// .lza_p0 (low_l1_encod[16] ), @299
// .lza_p1 (low_l1_encod[17] )); @300
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_30"); @302
ct_vfmau_lza_42 x_ct_vfmau_lza_42_30 (
.lza_p0 (low_l1_encod[18]),
.lza_p1 (low_l1_encod[19]),
.lza_precod (lza_precod[7:4] ),
.lza_vld (low_l1_vld[1] )
);
// &Connect(.lza_precod (lza_precod[7:4]), @303
// .lza_vld (low_l1_vld[1] ), @304
// .lza_p0 (low_l1_encod[18] ), @305
// .lza_p1 (low_l1_encod[19] )); @306
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_31"); @308
ct_vfmau_lza_42 x_ct_vfmau_lza_42_31 (
.lza_p0 (low_l1_encod[20]),
.lza_p1 (low_l1_encod[21]),
.lza_precod (lza_precod[3:0] ),
.lza_vld (low_l1_vld[0] )
);
// &Connect(.lza_precod (lza_precod[3:0]), @309
// .lza_vld (low_l1_vld[0] ), @310
// .lza_p0 (low_l1_encod[20] ), @311
// .lza_p1 (low_l1_encod[21] )); @312
//second level : 11:3 compressor , 2 4:2 lza_compressor,1 3:2 lza_compressor
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_32"); @316
ct_vfmau_lza_42 x_ct_vfmau_lza_42_32 (
.lza_p0 (low_l2_encod[0] ),
.lza_p1 (low_l2_encod[1] ),
.lza_precod (low_l1_vld[10:7]),
.lza_vld (low_l2_vld[2] )
);
// &Connect(.lza_precod (low_l1_vld[10:7] ), @317
// .lza_vld (low_l2_vld[2] ), @318
// .lza_p0 (low_l2_encod[0] ), @319
// .lza_p1 (low_l2_encod[1] )); @320
// &Instance("ct_vfmau_lza_42","x_ct_vfmau_lza_42_33"); @322
ct_vfmau_lza_42 x_ct_vfmau_lza_42_33 (
.lza_p0 (low_l2_encod[2]),
.lza_p1 (low_l2_encod[3]),
.lza_precod (low_l1_vld[6:3]),
.lza_vld (low_l2_vld[1] )
);
// &Connect(.lza_precod (low_l1_vld[6:3] ), @323
// .lza_vld (low_l2_vld[1] ), @324
// .lza_p0 (low_l2_encod[2] ), @325
// .lza_p1 (low_l2_encod[3] )); @326
// &Instance("ct_vfmau_lza_32","x_ct_vfmau_lza_32_0"); @328
ct_vfmau_lza_32 x_ct_vfmau_lza_32_0 (
.lza_p0 (low_l2_encod[4]),
.lza_p1 (low_l2_encod[5]),
.lza_precod (low_l1_vld[2:0]),
.lza_vld (low_l2_vld[0] )
);
// &Connect(.lza_precod (low_l1_vld[2:0] ), @329
// .lza_vld (low_l2_vld[0] ), @330
// .lza_p0 (low_l2_encod[4] ), @331
// .lza_p1 (low_l2_encod[5] )); @332
// &CombBeg; @334
always @( low_l1_encod[1:0]
or low_l2_encod[1:0]
or low_l1_encod[7:2])
begin
case(low_l2_encod[1:0])
2'b00 : low_l2_set0_encod[3:0] = {2'b00,low_l1_encod[1:0]};
2'b01 : low_l2_set0_encod[3:0] = {2'b01,low_l1_encod[3:2]};
2'b10 : low_l2_set0_encod[3:0] = {2'b10,low_l1_encod[5:4]};
2'b11 : low_l2_set0_encod[3:0] = {2'b11,low_l1_encod[7:6]};
default : low_l2_set0_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @342
end
// &CombBeg; @344
always @( low_l2_encod[3:2]
or low_l1_encod[15:8])
begin
case(low_l2_encod[3:2])
2'b00 : low_l2_set1_encod[3:0] = {2'b00,low_l1_encod[9:8]};
2'b01 : low_l2_set1_encod[3:0] = {2'b01,low_l1_encod[11:10]};
2'b10 : low_l2_set1_encod[3:0] = {2'b10,low_l1_encod[13:12]};
2'b11 : low_l2_set1_encod[3:0] = {2'b11,low_l1_encod[15:14]};
default : low_l2_set1_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @352
end
// &CombBeg; @354
always @( low_l2_encod[5:4]
or low_l1_encod[21:16])
begin
case(low_l2_encod[5:4])
2'b00 : low_l2_set2_encod[3:0] = {2'b00,low_l1_encod[17:16]};
2'b01 : low_l2_set2_encod[3:0] = {2'b01,low_l1_encod[19:18]};
2'b10 : low_l2_set2_encod[3:0] = {2'b10,low_l1_encod[21:20]};
default : low_l2_set2_encod[3:0] = {4{1'bx}};
endcase
// &CombEnd; @361
end
//third level : 3:1 compressor , 1 3:2 lza_compressor
// &Instance("ct_vfmau_lza_32","x_ct_vfmau_lza_32_1"); @364
ct_vfmau_lza_32 x_ct_vfmau_lza_32_1 (
.lza_p0 (low_l3_encod[0]),
.lza_p1 (low_l3_encod[1]),
.lza_precod (low_l2_vld[2:0]),
.lza_vld (low_l3_vld )
);
// &Connect(.lza_precod (low_l2_vld[2:0]), @365
// .lza_vld (low_l3_vld ), @366
// .lza_p0 (low_l3_encod[0] ), @367
// .lza_p1 (low_l3_encod[1] )); @368
// &CombBeg; @370
always @( low_l3_encod[1:0]
or low_l2_set2_encod[3:0]
or low_l2_set1_encod[3:0]
or low_l2_set0_encod[3:0])
begin
case(low_l3_encod[1:0])
2'b00 : low_l3_set0_encod[5:0] = {2'b00,low_l2_set0_encod[3:0]};
2'b01 : low_l3_set0_encod[5:0] = {2'b01,low_l2_set1_encod[3:0]};
2'b10 : low_l3_set0_encod[5:0] = {2'b10,low_l2_set2_encod[3:0]};
default : low_l3_set0_encod[5:0] = 6'b0;
endcase
// &CombEnd; @377
end
//----------------------------------------------------------
// 108-bit lza encoder result
//----------------------------------------------------------
assign lza_l4_encod[6:0] = (high_l3_vld)
? {1'b0,high_l3_set0_encod[5:0]}
: {1'b1,low_l3_set0_encod[5:0]};
assign lza_result_vld = high_l3_vld || low_l3_vld;
assign lza_result[6:0] = (lza_result_vld)
? lza_l4_encod[6:0]
: 7'd108;
// &ModuleEnd; @390
endmodule |
module ct_vfmau_lza_32(
lza_p0,
lza_p1,
lza_precod,
lza_vld
);
// &Ports; @24
input [2:0] lza_precod;
output lza_p0;
output lza_p1;
output lza_vld;
// &Regs; @25
// &Wires; @26
wire lza_p0;
wire lza_p1;
wire [2:0] lza_precod;
wire lza_vld;
assign lza_vld = |lza_precod[2:0];
assign lza_p0 = !lza_precod[2] && lza_precod[1];
assign lza_p1 = !lza_precod[2] && !lza_precod[1];
// &ModuleEnd; @32
endmodule |
module ct_vfmau_ff1_10bit(
ff1_data,
ff1_result
);
// &Ports; @24
input [9:0] ff1_data;
output [3:0] ff1_result;
// &Regs; @25
reg [3:0] ff1_result;
// &Wires; @26
wire [9:0] ff1_data;
// &CombBeg; @28
always @( ff1_data[9:0])
begin
casez(ff1_data[9:0])
10'b1?????????: ff1_result[3:0] = 4'd1;
10'b01????????: ff1_result[3:0] = 4'd2;
10'b001???????: ff1_result[3:0] = 4'd3;
10'b0001??????: ff1_result[3:0] = 4'd4;
10'b00001?????: ff1_result[3:0] = 4'd5;
10'b000001????: ff1_result[3:0] = 4'd6;
10'b0000001???: ff1_result[3:0] = 4'd7;
10'b00000001??: ff1_result[3:0] = 4'd8;
10'b000000001?: ff1_result[3:0] = 4'd9;
10'b0000000001: ff1_result[3:0] = 4'd10;
default : ff1_result[3:0] = {4{1'bx}};
endcase
// &CombEnd; @42
end
// &ModuleEnd; @44
endmodule |
module ct_vfmau_ctrl(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
ctrl_dp_ex5_fma_wb_vld,
ctrl_ex1_ex2_en,
ctrl_ex1_inst_vld,
ctrl_ex2_inst_vld,
ctrl_ex3_inst_vld,
ctrl_ex4_inst_vld,
ctrl_ex5_inst_vld,
dp_vfmau_ex1_pipex_sel,
dp_xx_ex1_half,
dp_xx_ex2_half,
dp_xx_ex3_fma,
dp_xx_ex3_half,
dp_xx_ex4_fma,
dp_xx_ex4_half,
dp_xx_ex4_mult_id,
forever_cpuclk,
mult1_ex1_ex2_pipedown,
mult1_ex2_ex3_pipedown,
mult1_ex3_ex4_pipedown,
mult1_ex4_ex5_pipedown,
mult_ex1_ex2_half_pipedown,
mult_ex2_ex3_half_pipedown,
mult_ex3_ex4_half_pipedown,
mult_ex4_ex5_half_pipedown,
pad_yy_icg_scan_en,
rtu_yy_xx_flush
);
// &Ports; @15
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dp_vfmau_ex1_pipex_sel;
input dp_xx_ex1_half;
input dp_xx_ex2_half;
input dp_xx_ex3_fma;
input dp_xx_ex3_half;
input dp_xx_ex4_fma;
input dp_xx_ex4_half;
input dp_xx_ex4_mult_id;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
output ctrl_dp_ex5_fma_wb_vld;
output ctrl_ex1_ex2_en;
output ctrl_ex1_inst_vld;
output ctrl_ex2_inst_vld;
output ctrl_ex3_inst_vld;
output ctrl_ex4_inst_vld;
output ctrl_ex5_inst_vld;
output mult1_ex1_ex2_pipedown;
output mult1_ex2_ex3_pipedown;
output mult1_ex3_ex4_pipedown;
output mult1_ex4_ex5_pipedown;
output mult_ex1_ex2_half_pipedown;
output mult_ex2_ex3_half_pipedown;
output mult_ex3_ex4_half_pipedown;
output mult_ex4_ex5_half_pipedown;
// &Regs; @16
reg ctrl_ex2_inst_vld;
reg ctrl_ex3_inst_vld;
reg ctrl_ex4_inst_vld;
reg ctrl_ex5_fma_wb_vld;
reg ctrl_ex5_inst_vld;
// &Wires; @17
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ctrl_dp_ex5_fma_wb_vld;
wire ctrl_ex1_ex2_clk;
wire ctrl_ex1_ex2_en;
wire ctrl_ex1_inst_vld;
wire ctrl_ex2_ex3_clk;
wire ctrl_ex2_ex3_en;
wire ctrl_ex3_en;
wire ctrl_ex3_ex4_clk;
wire ctrl_ex4_en;
wire ctrl_ex4_ex5_clk;
wire ctrl_ex4_fma_wb_vld;
wire dp_vfmau_ex1_pipex_sel;
wire dp_xx_ex1_half;
wire dp_xx_ex2_half;
wire dp_xx_ex3_fma;
wire dp_xx_ex3_half;
wire dp_xx_ex4_fma;
wire dp_xx_ex4_half;
wire dp_xx_ex4_mult_id;
wire forever_cpuclk;
wire mult1_ex1_ex2_pipedown;
wire mult1_ex2_ex3_pipedown;
wire mult1_ex3_ex4_pipedown;
wire mult1_ex4_ex5_pipedown;
wire mult_ex1_ex2_half_pipedown;
wire mult_ex2_ex3_half_pipedown;
wire mult_ex3_ex4_half_pipedown;
wire mult_ex4_ex5_half_pipedown;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
// &Depend("cpu_cfig.h"); @19
// &Force("bus","dp_xx_ex1_oper_size",2,0); @21
// &Force("bus","dp_xx_ex2_oper_size",2,0); @22
// &Force("bus","dp_xx_ex3_oper_size",2,0); @23
// &Force("bus","dp_xx_ex4_oper_size",2,0); @24
//==========================================================
// EX1 EX2 Gated CLK
//==========================================================
assign mult1_ex1_ex2_pipedown = dp_vfmau_ex1_pipex_sel && !dp_xx_ex1_half;
assign mult_ex1_ex2_half_pipedown = dp_vfmau_ex1_pipex_sel && dp_xx_ex1_half;
assign ctrl_ex1_inst_vld = dp_vfmau_ex1_pipex_sel;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ctrl_ex1_ex2_en = dp_vfmau_ex1_pipex_sel
||ctrl_ex2_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex1_ex2_gated_clk"); @43
gated_clk_cell x_ctrl_ex1_ex2_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ctrl_ex1_ex2_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ctrl_ex1_ex2_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @44
// .external_en (1'b0 ), @45
// .global_en (cp0_yy_clk_en ), @46
// .module_en (cp0_vfpu_icg_en ), @47
// .local_en (ctrl_ex1_ex2_en ), @48
// .clk_out (ctrl_ex1_ex2_clk)); @49
//----------------------------------------------------------
// EX2 Instrcution Valid
//----------------------------------------------------------
always @(posedge ctrl_ex1_ex2_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_ex2_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
ctrl_ex2_inst_vld <= 1'b0;
else
ctrl_ex2_inst_vld <= dp_vfmau_ex1_pipex_sel;
end
// &Force("output","ctrl_ex2_inst_vld"); @64
// &Force("output","ctrl_ex1_ex2_en"); @65
//==========================================================
// EX2 EX3 Gated CLK
//==========================================================
assign mult1_ex2_ex3_pipedown = ctrl_ex2_inst_vld && !dp_xx_ex2_half;
assign mult_ex2_ex3_half_pipedown = ctrl_ex2_inst_vld && dp_xx_ex2_half;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ctrl_ex2_ex3_en = ctrl_ex2_inst_vld
||ctrl_ex3_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex2_ex3_gated_clk"); @84
gated_clk_cell x_ctrl_ex2_ex3_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ctrl_ex2_ex3_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ctrl_ex2_ex3_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @85
// .external_en (1'b0 ), @86
// .global_en (cp0_yy_clk_en ), @87
// .module_en (cp0_vfpu_icg_en ), @88
// .local_en (ctrl_ex2_ex3_en ), @89
// .clk_out (ctrl_ex2_ex3_clk)); @90
//----------------------------------------------------------
// EX3 Instrcution Valid
//----------------------------------------------------------
always @(posedge ctrl_ex2_ex3_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_ex3_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
ctrl_ex3_inst_vld <= 1'b0;
else
ctrl_ex3_inst_vld <= ctrl_ex2_inst_vld;
end
// &Force("output","ctrl_ex3_inst_vld"); @104
//==========================================================
// EX3 EX4 Gated CLK
//==========================================================
assign mult1_ex3_ex4_pipedown = ctrl_ex3_inst_vld && !dp_xx_ex3_half;
assign mult_ex3_ex4_half_pipedown = ctrl_ex3_inst_vld && dp_xx_ex3_half && dp_xx_ex3_fma;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ctrl_ex3_en = ctrl_ex3_inst_vld
||ctrl_ex4_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex3_ex4_gated_clk"); @124
gated_clk_cell x_ctrl_ex3_ex4_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ctrl_ex3_ex4_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ctrl_ex3_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @125
// .external_en (1'b0 ), @126
// .global_en (cp0_yy_clk_en ), @127
// .module_en (cp0_vfpu_icg_en ), @128
// .local_en (ctrl_ex3_en ), @129
// .clk_out (ctrl_ex3_ex4_clk)); @130
//----------------------------------------------------------
// EX4 Instrcution Valid
//----------------------------------------------------------
always @(posedge ctrl_ex3_ex4_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_ex4_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
ctrl_ex4_inst_vld <= 1'b0;
else
ctrl_ex4_inst_vld <= ctrl_ex3_inst_vld;
end
// &Force("output","ctrl_ex4_inst_vld"); @144
//==========================================================
// EX4 EX5 Gated CLK
//==========================================================
assign mult1_ex4_ex5_pipedown = ctrl_ex4_inst_vld
&& !dp_xx_ex4_half
&& (dp_xx_ex4_fma
|| dp_xx_ex4_mult_id);
assign mult_ex4_ex5_half_pipedown = ctrl_ex4_inst_vld
&& dp_xx_ex4_fma
&& dp_xx_ex4_half;
//assign mult1_ex4_ex5_pipedown = ctrl_ex4_inst_vld && dp_xx_ex4_fma && !dp_xx_ex4_half;
//assign mult_ex4_ex5_half_pipedown = ctrl_ex4_inst_vld && dp_xx_ex4_fma && dp_xx_ex4_half;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ctrl_ex4_en = ctrl_ex4_inst_vld
||ctrl_ex5_inst_vld;
// &Instance("gated_clk_cell", "x_ctrl_ex4_ex5_gated_clk"); @188
gated_clk_cell x_ctrl_ex4_ex5_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ctrl_ex4_ex5_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ctrl_ex4_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @189
// .external_en (1'b0 ), @190
// .global_en (cp0_yy_clk_en ), @191
// .module_en (cp0_vfpu_icg_en ), @192
// .local_en (ctrl_ex4_en ), @193
// .clk_out (ctrl_ex4_ex5_clk)); @194
//----------------------------------------------------------
// EX5 Instrcution Valid
//----------------------------------------------------------
always @(posedge ctrl_ex4_ex5_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_ex5_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
ctrl_ex5_inst_vld <= 1'b0;
else
ctrl_ex5_inst_vld <= ctrl_ex4_inst_vld;
end
// &Force("output","ctrl_ex5_inst_vld"); @209
//----------------------------------------------------------
// EX5 FMA Write Back Valid
//----------------------------------------------------------
assign ctrl_ex4_fma_wb_vld = dp_xx_ex4_fma
&& ctrl_ex4_inst_vld
&& !dp_xx_ex4_half
|| dp_xx_ex4_mult_id
&& ctrl_ex4_inst_vld
&& !dp_xx_ex4_half;
//assign ctrl_ex4_fma_wb_vld = dp_xx_ex4_fma
// && ctrl_ex4_inst_vld
// && !dp_xx_ex4_half;
always @(posedge ctrl_ex4_ex5_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ctrl_ex5_fma_wb_vld <= 1'b0;
else if(rtu_yy_xx_flush)
ctrl_ex5_fma_wb_vld <= 1'b0;
else
ctrl_ex5_fma_wb_vld <= ctrl_ex4_fma_wb_vld;
end
assign ctrl_dp_ex5_fma_wb_vld = ctrl_ex5_fma_wb_vld;
// &ModuleEnd; @251
endmodule |
module apb(
b_pad_gpio_porta,
biu_pad_haddr,
biu_pad_hprot,
biu_pad_lpmd_b,
clk_en,
haddr_s2,
hburst_s2,
hmastlock,
hprot_s2,
hrdata_s2,
hready_s2,
hresp_s2,
hsel_s2,
hsize_s2,
htrans_s2,
hwdata_s2,
hwrite_s2,
i_pad_clk,
pad_biu_clkratio,
pad_cpu_rst_b,
per_clk,
cpu_clk,
`ifdef PMU_LP_MODE_TEST
pmu_cpu_pwr_on ,
pmu_cpu_iso_in ,
pmu_cpu_iso_out,
pmu_cpu_save ,
pmu_cpu_restore,
`endif
uart0_sin,
uart0_sout,
xx_intc_vld
);
input [39 :0] biu_pad_haddr;
input [3 :0] biu_pad_hprot;
input [1 :0] biu_pad_lpmd_b;
input [39 :0] haddr_s2;
input [2 :0] hburst_s2;
input hmastlock;
input [3 :0] hprot_s2;
input hsel_s2;
input [2 :0] hsize_s2;
input [1 :0] htrans_s2;
input [127:0] hwdata_s2;
input hwrite_s2;
input i_pad_clk;
input uart0_sin;
output clk_en;
output [127:0] hrdata_s2;
output hready_s2;
output [1 :0] hresp_s2;
output [2 :0] pad_biu_clkratio;
input pad_cpu_rst_b;
output per_clk;
output cpu_clk;
`ifdef PMU_LP_MODE_TEST
output pmu_cpu_pwr_on ;
output pmu_cpu_iso_in ;
output pmu_cpu_iso_out;
output pmu_cpu_save ;
output pmu_cpu_restore;
`endif
output uart0_sout;
output [39 :0] xx_intc_vld;
inout [7 :0] b_pad_gpio_porta;
wire apb_clkgen_psel;
wire apb_gpio_psel;
wire [39 :0] apb_haddr;
wire [2 :0] apb_hburst;
wire [31 :0] apb_hrdata;
wire apb_hready;
wire [1 :0] apb_hresp;
wire apb_hsel;
wire [2 :0] apb_hsize;
wire [1 :0] apb_htrans;
wire [31 :0] apb_hwdata;
wire apb_hwrite;
wire apb_intc_psel;
wire apb_stim_psel;
wire apb_tim_psel;
wire apb_uart_psel;
wire apb_pmu_psel;
wire [39 :0] apb_xx_paddr;
wire apb_xx_penable;
wire [31 :0] apb_xx_pwdata;
wire apb_xx_pwrite;
wire [7 :0] b_pad_gpio_porta;
wire [39 :0] biu_pad_haddr;
wire [3 :0] biu_pad_hprot;
wire [1 :0] biu_pad_lpmd_b;
wire clk_en;
wire [31 :0] clkgen_apb_prdata;
wire [31 :0] gpio_apb_prdata;
wire [7 :0] gpio_intc_int;
wire [39 :0] haddr_s2;
wire [2 :0] hburst_s2;
wire hmastlock;
wire [3 :0] hprot_s2;
wire [127:0] hrdata_s2;
wire hready_s2;
wire [1 :0] hresp_s2;
wire hsel_s2;
wire [2 :0] hsize_s2;
wire [1 :0] htrans_s2;
wire [127:0] hwdata_s2;
wire hwrite_s2;
wire i_pad_clk;
wire [2 :0] pad_biu_clkratio;
wire pad_cpu_rst_b;
wire per_clk;
wire [31 :0] stim_apb_prdata;
wire [3 :0] stim_intc_int;
wire [31 :0] tim_apb_prdata;
wire [3 :0] tim_intc_int;
wire uart0_intc_int;
wire uart0_sin;
wire uart0_sout;
wire [31 :0] uart_apb_prdata;
wire [39 :0] xx_intc_vld;
wire gate_en0;
wire gate_en1;
wire pmu_cpu_pwr_on ;
wire pmu_cpu_iso_in ;
wire pmu_cpu_iso_out;
wire pmu_cpu_save ;
wire pmu_cpu_restore;
wire merged_int_vld;
wire [31:0 ] pmu_apb_prdata;
ahb2apb x_ahb2apb (
.apb_haddr (apb_haddr ),
.apb_hburst (apb_hburst ),
.apb_hrdata (apb_hrdata ),
.apb_hready (apb_hready ),
.apb_hresp (apb_hresp ),
.apb_hsel (apb_hsel ),
.apb_hsize (apb_hsize ),
.apb_htrans (apb_htrans ),
.apb_hwdata (apb_hwdata ),
.apb_hwrite (apb_hwrite ),
.haddr_s2 (haddr_s2 ),
.hburst_s2 (hburst_s2 ),
.hmastlock (hmastlock ),
.hprot_s2 (hprot_s2 ),
.hrdata_s2 (hrdata_s2 ),
.hready_s2 (hready_s2 ),
.hresp_s2 (hresp_s2 ),
.hsel_s2 (hsel_s2 ),
.hsize_s2 (hsize_s2 ),
.htrans_s2 (htrans_s2 ),
.hwdata_s2 (hwdata_s2 ),
.hwrite_s2 (hwrite_s2 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk )
);
apb_bridge x_apb_bridge (
.apb_harb_hrdata (apb_hrdata ),
.apb_harb_hready (apb_hready ),
.apb_harb_hresp (apb_hresp ),
.apb_xx_paddr (apb_xx_paddr ),
.apb_xx_penable (apb_xx_penable ),
.apb_xx_pwdata (apb_xx_pwdata ),
.apb_xx_pwrite (apb_xx_pwrite ),
.harb_apb_hsel (apb_hsel ),
.harb_xx_haddr (apb_haddr ),
.harb_xx_hwdata (apb_hwdata ),
.harb_xx_hwrite (apb_hwrite ),
.hclk (per_clk ),
.hrst_b (pad_cpu_rst_b ),
.prdata_s1 (uart_apb_prdata ),
.prdata_s2 (tim_apb_prdata ),
.prdata_s3 (pmu_apb_prdata ),
.prdata_s4 (32'h0 ),
.prdata_s5 (gpio_apb_prdata ),
.prdata_s6 (clkgen_apb_prdata),
.prdata_s7 (stim_apb_prdata ),
.psel_s1 (apb_uart_psel ),
.psel_s2 (apb_tim_psel ),
.psel_s3 (apb_pmu_psel ),
.psel_s4 (apb_intc_psel ),
.psel_s5 (apb_gpio_psel ),
.psel_s6 (apb_clkgen_psel ),
.psel_s7 (apb_stim_psel )
);
uart x_uart (
.apb_uart_paddr (apb_xx_paddr ),
.apb_uart_penable (apb_xx_penable ),
.apb_uart_psel (apb_uart_psel ),
.apb_uart_pwdata (apb_xx_pwdata ),
.apb_uart_pwrite (apb_xx_pwrite ),
.rst_b (pad_cpu_rst_b ),
.s_in (uart0_sin ),
.s_out (uart0_sout ),
.sys_clk (per_clk ),
.uart_apb_prdata (uart_apb_prdata ),
.uart_vic_int (uart0_intc_int )
);
timer x_timer (
.paddr (apb_xx_paddr[15:0]),
.pclk (per_clk ),
.penable (apb_xx_penable ),
.prdata (tim_apb_prdata ),
.presetn (pad_cpu_rst_b ),
.psel (apb_tim_psel ),
.pwdata (apb_xx_pwdata ),
.pwrite (apb_xx_pwrite ),
.timer_int (tim_intc_int )
);
gpio x_gpio (
.b_pad_gpio_porta (b_pad_gpio_porta ),
.gpio_intr (gpio_intc_int ),
.paddr (apb_xx_paddr[6:2]),
.pclk (per_clk ),
.pclk_intr (per_clk ),
.penable (apb_xx_penable ),
.prdata (gpio_apb_prdata ),
.presetn (pad_cpu_rst_b ),
.psel (apb_gpio_psel ),
.pwdata (apb_xx_pwdata ),
.pwrite (apb_xx_pwrite )
);
timer x_stimer (
.paddr (apb_xx_paddr[15:0]),
.pclk (per_clk ),
.penable (apb_xx_penable ),
.prdata (stim_apb_prdata ),
.presetn (pad_cpu_rst_b ),
.psel (apb_stim_psel ),
.pwdata (apb_xx_pwdata ),
.pwrite (apb_xx_pwrite ),
.timer_int (stim_intc_int[3:0])
);
clk_gen x_clk_gen (
.clk_en (clk_en ),
.clkrst_b (pad_cpu_rst_b ),
.i_pad_clk (i_pad_clk ),
.gate_en0 (gate_en0 ),
.gate_en1 (gate_en1 ),
.pad_biu_clkratio (pad_biu_clkratio ),
.penable (apb_xx_penable ),
.per_clk (per_clk ),
.cpu_clk (cpu_clk ),
.prdata (clkgen_apb_prdata ),
.psel (apb_clkgen_psel ),
.pwdata (apb_xx_pwdata[2:0]),
.pwrite (apb_xx_pwrite )
);
pmu x_pmu (
.apb_pmu_paddr (apb_xx_paddr[11:0] ),
.apb_pmu_penable (apb_xx_penable ),
.apb_pmu_psel (apb_pmu_psel ),
.apb_pmu_pwdata (apb_xx_pwdata ),
.apb_pmu_pwrite (apb_xx_pwrite ),
.biu_pad_lpmd_b (biu_pad_lpmd_b ),
.corec_pmu_sleep_out (),
.cpu_clk (cpu_clk ), // Sample lpmd from CPU
.gate_en0 (gate_en0 ),
.gate_en1 (gate_en1 ),
.had_pad_wakeup_req_b (1'b1 ),
.i_pad_cpu_jtg_rst_b (1'b1 ),
.i_pad_jtg_tclk (1'b1 ),
.intraw_vld (merged_int_vld ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_had_jdb_req_b ( ),
.pad_had_jtg_tap_en (1'b0 ),
.pad_had_jtg_tms (1'b0 ),
.pad_had_jtg_trst_b ( ),
.pad_had_jtg_trst_b_pre (1'b1 ),
.pg_reset_b ( ), // output from pmu
.pmu_apb_prdata (pmu_apb_prdata ),
.pmu_clk (per_clk ),
.pmu_cpu_pwr_on (pmu_cpu_pwr_on ),
.pmu_cpu_iso_in (pmu_cpu_iso_in ),
.pmu_cpu_iso_out (pmu_cpu_iso_out ),
.pmu_cpu_save (pmu_cpu_save ),
.pmu_cpu_restore (pmu_cpu_restore )
);
assign merged_int_vld = | xx_intc_vld[39:0];
assign xx_intc_vld[39:0] = {21'b0,stim_intc_int[3:0],gpio_intc_int[7:0],1'b0,tim_intc_int[3:0],1'b0,uart0_intc_int};
//clk_aligner x_clk_aligner (
// .clk_div_1 (sclk_div_1 ),
// .clk_div_2 (sclk_div_2 ),
// .clk_div_3 (sclk_div_3 ),
// .clk_div_4 (sclk_div_4 ),
// .clk_div_5 (sclk_div_5 ),
// .clk_div_6 (sclk_div_6 ),
// .clk_div_7 (sclk_div_7 ),
// .clk_div_8 (sclk_div_8 ),
// .clk_en (sclk_en ),
// .clk_en_1 (sclk_en_1 ),
// .clk_en_2 (sclk_en_2 ),
// .clk_en_3 (sclk_en_3 ),
// .clk_en_4 (sclk_en_4 ),
// .clk_en_5 (sclk_en_5 ),
// .clk_en_6 (sclk_en_6 ),
// .clk_en_7 (sclk_en_7 ),
// .clk_en_8 (sclk_en_8 ),
// .clkgen_ahbclk (sclkgen_ahbclk ),
// .clkgen_apbclk (sclkgen_apbclk ),
// .clkgen_cpuclk (sclkgen_cpuclk ),
// .forever_cpuclk (top_osc_clk ),
// .pad_biu_clkratio (top_cpu_sclkratio)
//);
//
//clk_divider x_clk_divider (
// .clk_div_1 (sclk_div_1 ),
// .clk_div_2 (sclk_div_2 ),
// .clk_div_3 (sclk_div_3 ),
// .clk_div_4 (sclk_div_4 ),
// .clk_div_5 (sclk_div_5 ),
// .clk_div_6 (sclk_div_6 ),
// .clk_div_7 (sclk_div_7 ),
// .clk_div_8 (sclk_div_8 ),
// .clk_en_1 (sclk_en_1 ),
// .clk_en_2 (sclk_en_2 ),
// .clk_en_3 (sclk_en_3 ),
// .clk_en_4 (sclk_en_4 ),
// .clk_en_5 (sclk_en_5 ),
// .clk_en_6 (sclk_en_6 ),
// .clk_en_7 (sclk_en_7 ),
// .clk_en_8 (sclk_en_8 ),
// .osc_clk (i_pad_clk )
//)
//
//
//
endmodule |
module apb_bridge(
apb_harb_hrdata,
apb_harb_hready,
apb_harb_hresp,
apb_xx_paddr,
apb_xx_penable,
apb_xx_pwdata,
apb_xx_pwrite,
harb_apb_hsel,
harb_xx_haddr,
harb_xx_hwdata,
harb_xx_hwrite,
hclk,
hrst_b,
prdata_s1,
prdata_s2,
prdata_s3,
prdata_s4,
prdata_s5,
prdata_s6,
prdata_s7,
psel_s1,
psel_s2,
psel_s3,
psel_s4,
psel_s5,
psel_s6,
psel_s7
);
input harb_apb_hsel;
input [39:0] harb_xx_haddr;
input [31:0] harb_xx_hwdata;
input harb_xx_hwrite;
input hclk;
input hrst_b;
input [31:0] prdata_s1;
input [31:0] prdata_s2;
input [31:0] prdata_s3;
input [31:0] prdata_s4;
input [31:0] prdata_s5;
input [31:0] prdata_s6;
input [31:0] prdata_s7;
output [31:0] apb_harb_hrdata;
output apb_harb_hready;
output [1 :0] apb_harb_hresp;
output [39:0] apb_xx_paddr;
output apb_xx_penable;
output [31:0] apb_xx_pwdata;
output apb_xx_pwrite;
output psel_s1;
output psel_s2;
output psel_s3;
output psel_s4;
output psel_s5;
output psel_s6;
output psel_s7;
reg [31:0] apb_harb_hrdata;
reg apb_harb_hready;
reg [39:0] apb_xx_paddr;
reg apb_xx_penable;
reg apb_xx_psel;
reg [31:0] apb_xx_pwdata;
reg apb_xx_pwrite;
reg [2 :0] cur_state;
reg [39:0] haddr_latch;
reg hwrite_latch;
reg [2 :0] nxt_state;
wire [1 :0] apb_harb_hresp;
wire busy_s1;
wire busy_s2;
wire busy_s3;
wire busy_s4;
wire busy_s5;
wire busy_s6;
wire busy_s7;
wire busy_s8;
wire enable_latch;
wire enable_r_select;
wire harb_apb_hsel;
wire [39:0] harb_xx_haddr;
wire [31:0] harb_xx_hwdata;
wire harb_xx_hwrite;
wire hclk;
wire hrst_b;
wire idle_latch;
wire idle_r_select;
wire [31:0] prdata_s1;
wire [31:0] prdata_s2;
wire [31:0] prdata_s3;
wire [31:0] prdata_s4;
wire [31:0] prdata_s5;
wire [31:0] prdata_s6;
wire [31:0] prdata_s7;
wire psel_s1;
wire psel_s2;
wire psel_s3;
wire psel_s4;
wire psel_s5;
wire psel_s6;
wire psel_s7;
wire psel_s8;
assign apb_harb_hresp[1:0] = 2'b0;
parameter IDLE = 3'b000;
parameter LATCH = 3'b001;
parameter W_SELECT = 3'b010;
parameter R_SELECT = 3'b011;
parameter ENABLE = 3'b100;
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
cur_state[2:0] <= IDLE;
end
else
begin
cur_state[2:0] <= nxt_state[2:0];
end
end
assign idle_latch = harb_apb_hsel && harb_xx_hwrite;
assign idle_r_select = harb_apb_hsel && !harb_xx_hwrite;
assign enable_latch = harb_apb_hsel && harb_xx_hwrite;
assign enable_r_select = harb_apb_hsel && !harb_xx_hwrite;
always @( enable_r_select
or idle_latch
or idle_r_select
or enable_latch
or cur_state[2:0])
begin
nxt_state[2:0] = IDLE;
case(cur_state[2:0])
IDLE:
begin
if(idle_latch)
begin
nxt_state[2:0] = LATCH;
end
else if(idle_r_select)
begin
nxt_state[2:0] = R_SELECT;
end
else
begin
nxt_state[2:0] = IDLE;
end
end
LATCH:
begin
nxt_state[2:0] = W_SELECT;
end
W_SELECT:
begin
nxt_state[2:0] = ENABLE;
end
R_SELECT:
begin
nxt_state[2:0] = ENABLE;
end
ENABLE:
begin
if(enable_latch)
begin
nxt_state[2:0] = LATCH;
end
else if(enable_r_select)
begin
nxt_state[2:0] = R_SELECT;
end
else
begin
nxt_state[2:0] = IDLE;
end
end
endcase
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
haddr_latch[39:0] <= 40'b0;
hwrite_latch <= 1'b0;
end
else if(nxt_state[2:0]==LATCH)
begin
haddr_latch[39:0] <= harb_xx_haddr[39:0];
hwrite_latch <= harb_xx_hwrite;
end
else
begin
haddr_latch[39:0] <= haddr_latch[39:0];
hwrite_latch <= hwrite_latch;
end
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
apb_xx_paddr[39:0] <= 40'b0;
apb_xx_pwrite <= 1'b0;
end
else if(nxt_state[2:0]==W_SELECT)
begin
apb_xx_paddr[39:0] <= haddr_latch[39:0];
apb_xx_pwrite <= hwrite_latch;
end
else if(nxt_state[2:0]==R_SELECT)
begin
apb_xx_paddr[39:0] <= harb_xx_haddr[39:0];
apb_xx_pwrite <= harb_xx_hwrite;
end
else
begin
apb_xx_paddr[39:0] <= apb_xx_paddr[39:0];
apb_xx_pwrite <= apb_xx_pwrite;
end
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
apb_xx_pwdata[31:0] <= 32'b0;
end
else if(nxt_state[2:0]==W_SELECT)
begin
apb_xx_pwdata[31:0] <= harb_xx_hwdata[31:0];
end
else
begin
apb_xx_pwdata[31:0] <= apb_xx_pwdata[31:0];
end
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
apb_xx_psel <= 1'b0;
end
else if(nxt_state[2:0]==W_SELECT)
begin
apb_xx_psel <= 1'b1;
end
else if(nxt_state[2:0]==R_SELECT)
begin
apb_xx_psel <= 1'b1;
end
else if(nxt_state[2:0]==ENABLE)
begin
apb_xx_psel <= 1'b1;
end
else
begin
apb_xx_psel <= 1'b0;
end
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
apb_xx_penable <= 1'b0;
end
else if(nxt_state[2:0]==ENABLE)
begin
apb_xx_penable <= 1'b1;
end
else
begin
apb_xx_penable <= 1'b0;
end
end
always @(posedge hclk or negedge hrst_b)
begin
if(!hrst_b)
begin
apb_harb_hready <= 1'b1;
end
else if(nxt_state[2:0]==LATCH)
begin
apb_harb_hready <= 1'b0;
end
else if(nxt_state[2:0]==W_SELECT)
begin
apb_harb_hready <= 1'b0;
end
else if(nxt_state[2:0]==R_SELECT)
begin
apb_harb_hready <= 1'b0;
end
else
begin
apb_harb_hready <= 1'b1;
end
end
assign psel_s1 = apb_xx_psel && (apb_xx_paddr>=`PS1_BASE_START) && (apb_xx_paddr<=`PS1_BASE_END);
assign psel_s2 = apb_xx_psel && (apb_xx_paddr>=`PS2_BASE_START) && (apb_xx_paddr<=`PS2_BASE_END);
assign psel_s3 = apb_xx_psel && (apb_xx_paddr>=`PS3_BASE_START) && (apb_xx_paddr<=`PS3_BASE_END);
assign psel_s4 = apb_xx_psel && (apb_xx_paddr>=`PS4_BASE_START) && (apb_xx_paddr<=`PS4_BASE_END);
assign psel_s5 = apb_xx_psel && (apb_xx_paddr>=`PS5_BASE_START) && (apb_xx_paddr<=`PS5_BASE_END);
assign psel_s6 = apb_xx_psel && (apb_xx_paddr>=`PS6_BASE_START) && (apb_xx_paddr<=`PS6_BASE_END);
assign psel_s7 = apb_xx_psel && (apb_xx_paddr>=`PS7_BASE_START) && (apb_xx_paddr<=`PS7_BASE_END);
assign psel_s8 = apb_xx_psel && (apb_xx_paddr>=`PS8_BASE_START) && (apb_xx_paddr<=`PS8_BASE_END);
assign busy_s1 = apb_xx_penable && psel_s1;
assign busy_s2 = apb_xx_penable && psel_s2;
assign busy_s3 = apb_xx_penable && psel_s3;
assign busy_s4 = apb_xx_penable && psel_s4;
assign busy_s5 = apb_xx_penable && psel_s5;
assign busy_s6 = apb_xx_penable && psel_s6;
assign busy_s7 = apb_xx_penable && psel_s7;
assign busy_s8 = apb_xx_penable && psel_s8;
always @( busy_s3
or busy_s4
or busy_s7
or busy_s2
or prdata_s5[31:0]
or busy_s6
or prdata_s6[31:0]
or busy_s5
or busy_s1
or prdata_s1[31:0]
or busy_s8
or prdata_s4[31:0]
or prdata_s2[31:0]
or prdata_s3[31:0]
or prdata_s7[31:0])
begin
case({busy_s1,busy_s2,busy_s3,busy_s4,busy_s5,busy_s6,busy_s7,busy_s8})
8'b10000000:
begin
apb_harb_hrdata[31:0] = prdata_s1[31:0] ;
end
8'b01000000:
begin
apb_harb_hrdata[31:0] = prdata_s2[31:0] ;
end
8'b00100000:
begin
apb_harb_hrdata[31:0] = prdata_s3[31:0] ;
end
8'b00010000:
begin
apb_harb_hrdata[31:0] = prdata_s4[31:0] ;
end
8'b00001000:
begin
apb_harb_hrdata[31:0] = prdata_s5[31:0] ;
end
8'b00000100:
begin
apb_harb_hrdata[31:0] = prdata_s6[31:0];
end
8'b00000010:
begin
apb_harb_hrdata[31:0] = prdata_s7[31:0] ;
end
8'b00000001:
begin
apb_harb_hrdata[31:0] = 32'h0 ;
end
default:
begin
apb_harb_hrdata[31:0] = 32'b0;
end
endcase
end
endmodule |
module soc(
b_pad_gpio_porta,
i_pad_clk,
i_pad_jtg_tclk,
i_pad_jtg_tdi,
i_pad_jtg_tms,
i_pad_jtg_trst_b,
i_pad_rst_b,
i_pad_uart0_sin,
o_pad_jtg_tdo,
o_pad_uart0_sout
);
input i_pad_clk;
input i_pad_jtg_tclk;
input i_pad_jtg_tdi;
input i_pad_jtg_tms;
input i_pad_jtg_trst_b;
input i_pad_rst_b;
input i_pad_uart0_sin;
output o_pad_jtg_tdo;
output o_pad_uart0_sout;
inout [7 :0] b_pad_gpio_porta;
wire arready_s0;
wire arready_s1;
wire arready_s2;
wire arready_s3;
wire arvalid_s0;
wire arvalid_s1;
wire arvalid_s2;
wire arvalid_s3;
wire awready_s0;
wire awready_s1;
wire awready_s2;
wire awready_s3;
wire awvalid_s0;
wire awvalid_s1;
wire awvalid_s2;
wire awvalid_s3;
wire [7 :0] b_pad_gpio_porta;
wire [7 :0] bid_s0;
wire [7 :0] bid_s1;
wire [7 :0] bid_s2;
wire [7 :0] bid_s3;
wire [39 :0] biu_pad_araddr;
wire [1 :0] biu_pad_arburst;
wire [3 :0] biu_pad_arcache;
wire [7 :0] biu_pad_arid;
wire [7 :0] biu_pad_arlen;
wire biu_pad_arlock;
wire [2 :0] biu_pad_arprot;
wire [2 :0] biu_pad_arsize;
wire biu_pad_arvalid;
wire [39 :0] biu_pad_awaddr;
wire [1 :0] biu_pad_awburst;
wire [3 :0] biu_pad_awcache;
wire [7 :0] biu_pad_awid;
wire [7 :0] biu_pad_awlen;
wire biu_pad_awlock;
wire [2 :0] biu_pad_awprot;
wire [2 :0] biu_pad_awsize;
wire biu_pad_awvalid;
wire biu_pad_bready;
wire [39 :0] biu_pad_haddr;
wire [2 :0] biu_pad_hburst;
wire biu_pad_hbusreq;
wire biu_pad_hlock;
wire [3 :0] biu_pad_hprot;
wire [2 :0] biu_pad_hsize;
wire [1 :0] biu_pad_htrans;
wire [1 :0] biu_pad_htrans_dly;
wire [127:0] biu_pad_hwdata;
wire biu_pad_hwrite;
wire biu_pad_hwrite_dly;
wire [1 :0] biu_pad_lpmd_b;
// wire biu_pad_retire_0;
// wire biu_pad_retire_1;
// wire biu_pad_retire_2;
// wire [39 :0] biu_pad_retire_pc_0;
// wire [39 :0] biu_pad_retire_pc_1;
// wire [39 :0] biu_pad_retire_pc_2;
wire biu_pad_rready;
// wire [63 :0] biu_pad_wb_gpr_data_0;
// wire [63 :0] biu_pad_wb_gpr_data_1;
// wire [63 :0] biu_pad_wb_gpr_data_2;
// wire biu_pad_wb_gpr_en_0;
// wire biu_pad_wb_gpr_en_1;
// wire biu_pad_wb_gpr_en_2;
wire [127:0] biu_pad_wdata;
wire [7 :0] biu_pad_wid;
wire biu_pad_wlast;
wire [15 :0] biu_pad_wstrb;
wire biu_pad_wvalid;
wire bready_s0;
wire bready_s1;
wire bready_s2;
wire bready_s3;
wire [1 :0] bresp_s0;
wire [1 :0] bresp_s1;
wire [1 :0] bresp_s2;
wire [1 :0] bresp_s3;
wire bvalid_s0;
wire bvalid_s1;
wire bvalid_s2;
wire bvalid_s3;
wire axim_clk_en;
wire fifo_biu_arready;
wire [39 :0] fifo_pad_araddr;
wire [1 :0] fifo_pad_arburst;
wire [3 :0] fifo_pad_arcache;
wire [7 :0] fifo_pad_arid;
wire [7 :0] fifo_pad_arlen;
wire fifo_pad_arlock;
wire [2 :0] fifo_pad_arprot;
wire [2 :0] fifo_pad_arsize;
wire fifo_pad_artrust;
wire fifo_pad_arvalid;
wire had_pad_jtg_tdo;
wire had_pad_jtg_tdo_en;
wire [39 :0] haddr_dly;
wire [39 :0] haddr_s1;
wire [39 :0] haddr_s2;
wire [39 :0] haddr_s3;
wire [2 :0] hburst_s1;
wire [2 :0] hburst_s2;
wire [2 :0] hburst_s3;
wire hmastlock;
wire [3 :0] hprot_s1;
wire [3 :0] hprot_s2;
wire [3 :0] hprot_s3;
wire [127:0] hrdata_s1;
wire [127:0] hrdata_s2;
wire [127:0] hrdata_s3;
wire hready_s1;
wire hready_s2;
wire hready_s3;
wire [1 :0] hresp_s1;
wire [1 :0] hresp_s2;
wire [1 :0] hresp_s3;
wire hsel_s1;
wire hsel_s2;
wire hsel_s3;
wire [2 :0] hsize_s1;
wire [2 :0] hsize_s2;
wire [2 :0] hsize_s3;
wire [1 :0] htrans_s1;
wire [1 :0] htrans_s2;
wire [1 :0] htrans_s3;
wire [127:0] hwdata_s1;
wire [127:0] hwdata_s2;
wire [127:0] hwdata_s3;
wire hwrite_s1;
wire hwrite_s2;
wire hwrite_s3;
wire i_pad_clk;
wire cpu_clk;
wire i_pad_jtg_tclk;
wire i_pad_jtg_tdi;
wire i_pad_jtg_tms;
wire i_pad_jtg_trst_b;
wire i_pad_rst_b;
wire i_pad_uart0_sin;
wire o_pad_jtg_tdo;
wire o_pad_uart0_sout;
wire pad_biu_arready;
wire pad_biu_awready;
wire [7 :0] pad_biu_bid;
wire [1 :0] pad_biu_bresp;
wire pad_biu_bvalid;
wire pad_biu_hgrant;
wire [127:0] pad_biu_hrdata;
wire pad_biu_hready;
wire [1 :0] pad_biu_hresp;
wire [127:0] pad_biu_rdata;
wire [7 :0] pad_biu_rid;
wire pad_biu_rlast;
wire [1 :0] pad_biu_rresp;
wire pad_biu_rvalid;
wire pad_biu_wready;
wire pad_cpu_rst_b;
wire pad_had_jtg_tclk;
wire pad_had_jtg_tdi;
wire pad_had_jtg_trst_b;
wire per_clk;
wire pll_cpu_clk;
wire [127:0] rdata_s0;
wire [127:0] rdata_s1;
wire [127:0] rdata_s2;
wire [127:0] rdata_s3;
wire [7 :0] rid_s0;
wire [7 :0] rid_s1;
wire [7 :0] rid_s2;
wire [7 :0] rid_s3;
wire rlast_s0;
wire rlast_s1;
wire rlast_s2;
wire rlast_s3;
wire rready_s0;
wire rready_s1;
wire rready_s2;
wire rready_s3;
wire [1 :0] rresp_s0;
wire [1 :0] rresp_s1;
wire [1 :0] rresp_s2;
wire [1 :0] rresp_s3;
wire rvalid_s0;
wire rvalid_s1;
wire rvalid_s2;
wire rvalid_s3;
wire uart0_sin;
wire uart0_sout;
wire wready_s0;
wire wready_s1;
wire wready_s2;
wire wready_s3;
wire wvalid_s0;
wire wvalid_s1;
wire wvalid_s2;
wire wvalid_s3;
wire [39 :0] xx_intc_vld;
`ifdef PMU_LP_MODE_TEST
wire pmu_cpu_pwr_on ;
wire pmu_cpu_iso_in ;
wire pmu_cpu_iso_out;
wire pmu_cpu_save ;
wire pmu_cpu_restore;
`endif
cpu_sub_system_axi x_cpu_sub_system_axi (
.biu_pad_araddr (biu_pad_araddr ),
.biu_pad_arburst (biu_pad_arburst ),
.biu_pad_arcache (biu_pad_arcache ),
.biu_pad_arid (biu_pad_arid ),
.biu_pad_arlen (biu_pad_arlen ),
.biu_pad_arlock (biu_pad_arlock ),
.biu_pad_arprot (biu_pad_arprot ),
.biu_pad_arsize (biu_pad_arsize ),
.biu_pad_arvalid (biu_pad_arvalid ),
.biu_pad_awaddr (biu_pad_awaddr ),
.biu_pad_awburst (biu_pad_awburst ),
.biu_pad_awcache (biu_pad_awcache ),
.biu_pad_awid (biu_pad_awid ),
.biu_pad_awlen (biu_pad_awlen ),
.biu_pad_awlock (biu_pad_awlock ),
.biu_pad_awprot (biu_pad_awprot ),
.biu_pad_awsize (biu_pad_awsize ),
.biu_pad_awvalid (biu_pad_awvalid ),
.biu_pad_bready (biu_pad_bready ),
.biu_pad_lpmd_b (biu_pad_lpmd_b ),
.biu_pad_rready (biu_pad_rready ),
.biu_pad_wdata (biu_pad_wdata ),
.biu_pad_wid (biu_pad_wid ),
.biu_pad_wlast (biu_pad_wlast ),
.biu_pad_wstrb (biu_pad_wstrb ),
.biu_pad_wvalid (biu_pad_wvalid ),
.axim_clk_en (axim_clk_en ),
.had_pad_jtg_tdo (had_pad_jtg_tdo ),
.had_pad_jtg_tdo_en (had_pad_jtg_tdo_en ),
.i_pad_jtg_tms (i_pad_jtg_tms ),
.pad_biu_arready (fifo_biu_arready ),
.pad_biu_awready (pad_biu_awready ),
.pad_biu_bid (pad_biu_bid ),
.pad_biu_bresp (pad_biu_bresp ),
.pad_biu_bvalid (pad_biu_bvalid ),
.pad_biu_rdata (pad_biu_rdata ),
.pad_biu_rid (pad_biu_rid ),
.pad_biu_rlast (pad_biu_rlast ),
.pad_biu_rresp ({2'b0,pad_biu_rresp} ),
.pad_biu_rvalid (pad_biu_rvalid ),
.pad_biu_wready (pad_biu_wready ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_yy_dft_clk_rst_b (pad_cpu_rst_b ),
.pad_had_jtg_tclk (pad_had_jtg_tclk ),
.pad_had_jtg_tdi (pad_had_jtg_tdi ),
.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
`ifdef PMU_LP_MODE_TEST
.pmu_cpu_pwr_on (pmu_cpu_pwr_on ),
.pmu_cpu_iso_in (pmu_cpu_iso_in ),
.pmu_cpu_iso_out (pmu_cpu_iso_out ),
.pmu_cpu_save (pmu_cpu_save ),
.pmu_cpu_restore (pmu_cpu_restore ),
`endif
.per_clk (per_clk ),
.pll_cpu_clk (pll_cpu_clk ),
.xx_intc_vld (xx_intc_vld )
);
assign pad_cpu_rst_b = i_pad_rst_b;
assign pll_cpu_clk = cpu_clk;
assign pad_had_jtg_tclk = i_pad_jtg_tclk;
assign pad_had_jtg_tdi = i_pad_jtg_tdi;
assign pad_had_jtg_trst_b = i_pad_jtg_trst_b;
assign uart0_sin = i_pad_uart0_sin;
assign o_pad_jtg_tdo = had_pad_jtg_tdo;
assign o_pad_uart0_sout = uart0_sout;
axi_interconnect128 x_axi_interconnect (
.aclk (per_clk ),
.araddr (fifo_pad_araddr ),
.aresetn (pad_cpu_rst_b ),
.arready (pad_biu_arready ),
.arready_s0 (arready_s0 ),
.arready_s1 (arready_s1 ),
.arready_s2 (arready_s2 ),
.arready_s3 (arready_s3 ),
.arvalid (fifo_pad_arvalid),
.arvalid_s0 (arvalid_s0 ),
.arvalid_s1 (arvalid_s1 ),
.arvalid_s2 (arvalid_s2 ),
.arvalid_s3 (arvalid_s3 ),
.awaddr (biu_pad_awaddr ),
.awid (biu_pad_awid ),
.awready (pad_biu_awready ),
.awready_s0 (awready_s0 ),
.awready_s1 (awready_s1 ),
.awready_s2 (awready_s2 ),
.awready_s3 (awready_s3 ),
.awvalid (biu_pad_awvalid ),
.awvalid_s0 (awvalid_s0 ),
.awvalid_s1 (awvalid_s1 ),
.awvalid_s2 (awvalid_s2 ),
.awvalid_s3 (awvalid_s3 ),
.bid (pad_biu_bid ),
.bid_s0 (bid_s0 ),
.bid_s1 (bid_s1 ),
.bid_s2 (bid_s2 ),
.bid_s3 (bid_s3 ),
.bready (biu_pad_bready ),
.bready_s0 (bready_s0 ),
.bready_s1 (bready_s1 ),
.bready_s2 (bready_s2 ),
.bready_s3 (bready_s3 ),
.bresp (pad_biu_bresp ),
.bresp_s0 (bresp_s0 ),
.bresp_s1 (bresp_s1 ),
.bresp_s2 (bresp_s2 ),
.bresp_s3 (bresp_s3 ),
.bvalid (pad_biu_bvalid ),
.bvalid_s0 (bvalid_s0 ),
.bvalid_s1 (bvalid_s1 ),
.bvalid_s2 (bvalid_s2 ),
.bvalid_s3 (bvalid_s3 ),
.rdata (pad_biu_rdata ),
.rdata_s0 (rdata_s0 ),
.rdata_s1 (rdata_s1 ),
.rdata_s2 (rdata_s2 ),
.rdata_s3 (rdata_s3 ),
.rid (pad_biu_rid ),
.rid_s0 (rid_s0 ),
.rid_s1 (rid_s1 ),
.rid_s2 (rid_s2 ),
.rid_s3 (rid_s3 ),
.rlast (pad_biu_rlast ),
.rlast_s0 (rlast_s0 ),
.rlast_s1 (rlast_s1 ),
.rlast_s2 (rlast_s2 ),
.rlast_s3 (rlast_s3 ),
.rready (biu_pad_rready ),
.rready_s0 (rready_s0 ),
.rready_s1 (rready_s1 ),
.rready_s2 (rready_s2 ),
.rready_s3 (rready_s3 ),
.rresp (pad_biu_rresp ),
.rresp_s0 (rresp_s0 ),
.rresp_s1 (rresp_s1 ),
.rresp_s2 (rresp_s2 ),
.rresp_s3 (rresp_s3 ),
.rvalid (pad_biu_rvalid ),
.rvalid_s0 (rvalid_s0 ),
.rvalid_s1 (rvalid_s1 ),
.rvalid_s2 (rvalid_s2 ),
.rvalid_s3 (rvalid_s3 ),
.wid (biu_pad_wid ),
.wlast (biu_pad_wlast ),
.wready (pad_biu_wready ),
.wready_s0 (wready_s0 ),
.wready_s1 (wready_s1 ),
.wready_s2 (wready_s2 ),
.wready_s3 (wready_s3 ),
.wvalid (biu_pad_wvalid ),
.wvalid_s0 (wvalid_s0 ),
.wvalid_s1 (wvalid_s1 ),
.wvalid_s2 (wvalid_s2 ),
.wvalid_s3 (wvalid_s3 )
);
axi_fifo x_axi_fifo (
.biu_pad_araddr (biu_pad_araddr ),
.biu_pad_arburst (biu_pad_arburst ),
.biu_pad_arcache (biu_pad_arcache ),
.biu_pad_arid (biu_pad_arid ),
.biu_pad_arlen (biu_pad_arlen ),
.biu_pad_arlock (biu_pad_arlock ),
.biu_pad_arprot (biu_pad_arprot ),
.biu_pad_arsize (biu_pad_arsize ),
.biu_pad_arvalid (biu_pad_arvalid ),
.counter_num0 (32'd0 ),
.counter_num1 (32'd0 ),
.counter_num2 (32'd0 ),
.counter_num3 (32'd0 ),
.counter_num4 (32'd0 ),
.counter_num5 (32'd0 ),
.counter_num6 (32'd0 ),
.counter_num7 (32'd0 ),
.cpu_clk (per_clk ),
.cpu_rst_b (pad_cpu_rst_b ),
.fifo_biu_arready (fifo_biu_arready),
.fifo_pad_araddr (fifo_pad_araddr ),
.fifo_pad_arburst (fifo_pad_arburst),
.fifo_pad_arcache (fifo_pad_arcache),
.fifo_pad_arid (fifo_pad_arid ),
.fifo_pad_arlen (fifo_pad_arlen ),
.fifo_pad_arlock (fifo_pad_arlock ),
.fifo_pad_arprot (fifo_pad_arprot ),
.fifo_pad_arsize (fifo_pad_arsize ),
.fifo_pad_artrust (fifo_pad_artrust),
.fifo_pad_arvalid (fifo_pad_arvalid),
.pad_biu_arready (pad_biu_arready )
);
axi_slave128 x_axi_slave128 (
.araddr_s0 (fifo_pad_araddr ),
.arburst_s0 (fifo_pad_arburst),
.arcache_s0 (fifo_pad_arcache),
.arid_s0 (fifo_pad_arid ),
.arlen_s0 (fifo_pad_arlen ),
.arprot_s0 (fifo_pad_arprot ),
.arready_s0 (arready_s0 ),
.arsize_s0 (fifo_pad_arsize ),
.arvalid_s0 (arvalid_s0 ),
.awaddr_s0 (biu_pad_awaddr ),
.awburst_s0 (biu_pad_awburst ),
.awcache_s0 (biu_pad_awcache ),
.awid_s0 (biu_pad_awid ),
.awlen_s0 (biu_pad_awlen ),
.awprot_s0 (biu_pad_awprot ),
.awready_s0 (awready_s0 ),
.awsize_s0 (biu_pad_awsize ),
.awvalid_s0 (awvalid_s0 ),
.bid_s0 (bid_s0 ),
.bready_s0 (bready_s0 ),
.bresp_s0 (bresp_s0 ),
.bvalid_s0 (bvalid_s0 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk ),
.rdata_s0 (rdata_s0 ),
.rid_s0 (rid_s0 ),
.rlast_s0 (rlast_s0 ),
.rready_s0 (rready_s0 ),
.rresp_s0 (rresp_s0 ),
.rvalid_s0 (rvalid_s0 ),
.wdata_s0 (biu_pad_wdata ),
.wid_s0 (biu_pad_wid ),
.wlast_s0 (biu_pad_wlast ),
.wready_s0 (wready_s0 ),
.wstrb_s0 (biu_pad_wstrb ),
.wvalid_s0 (wvalid_s0 )
);
axi_err128 x_axi_err (
.araddr_s1 (fifo_pad_araddr ),
.arburst_s1 (fifo_pad_arburst),
.arcache_s1 (fifo_pad_arcache),
.arid_s1 (fifo_pad_arid ),
.arlen_s1 (fifo_pad_arlen ),
.arprot_s1 (fifo_pad_arprot ),
.arready_s1 (arready_s1 ),
.arsize_s1 (fifo_pad_arsize ),
.arvalid_s1 (arvalid_s1 ),
.awaddr_s1 (biu_pad_awaddr ),
.awburst_s1 (biu_pad_awburst ),
.awcache_s1 (biu_pad_awcache ),
.awid_s1 (biu_pad_awid ),
.awlen_s1 (biu_pad_awlen ),
.awprot_s1 (biu_pad_awprot ),
.awready_s1 (awready_s1 ),
.awsize_s1 (biu_pad_awsize ),
.awvalid_s1 (awvalid_s1 ),
.bid_s1 (bid_s1 ),
.bready_s1 (bready_s1 ),
.bresp_s1 (bresp_s1 ),
.bvalid_s1 (bvalid_s1 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk ),
.rdata_s1 (rdata_s1 ),
.rid_s1 (rid_s1 ),
.rlast_s1 (rlast_s1 ),
.rready_s1 (rready_s1 ),
.rresp_s1 (rresp_s1 ),
.rvalid_s1 (rvalid_s1 ),
.wdata_s1 (biu_pad_wdata ),
.wid_s1 (biu_pad_wid ),
.wlast_s1 (biu_pad_wlast ),
.wready_s1 (wready_s1 ),
.wstrb_s1 (biu_pad_wstrb ),
.wvalid_s1 (wvalid_s1 )
);
axi2ahb x_axi2ahb (
.biu_pad_araddr (fifo_pad_araddr ),
.biu_pad_arburst (fifo_pad_arburst),
.biu_pad_arcache (fifo_pad_arcache),
.biu_pad_arid (fifo_pad_arid ),
.biu_pad_arlen (fifo_pad_arlen ),
.biu_pad_arlock (fifo_pad_arlock ),
.biu_pad_arprot (fifo_pad_arprot ),
.biu_pad_arsize (fifo_pad_arsize ),
.biu_pad_artrust (fifo_pad_artrust),
.biu_pad_arvalid (arvalid_s2 ),
.biu_pad_awaddr (biu_pad_awaddr ),
.biu_pad_awburst (biu_pad_awburst ),
.biu_pad_awcache (biu_pad_awcache ),
.biu_pad_awid (biu_pad_awid ),
.biu_pad_awlen (biu_pad_awlen ),
.biu_pad_awlock (biu_pad_awlock ),
.biu_pad_awprot (biu_pad_awprot ),
.biu_pad_awsize (biu_pad_awsize ),
.biu_pad_awvalid (awvalid_s2 ),
.biu_pad_bready (bready_s2 ),
.biu_pad_haddr (biu_pad_haddr ),
.biu_pad_hburst (biu_pad_hburst ),
.biu_pad_hbusreq (biu_pad_hbusreq ),
.biu_pad_hlock (biu_pad_hlock ),
.biu_pad_hprot (biu_pad_hprot ),
.biu_pad_hsize (biu_pad_hsize ),
.biu_pad_htrans (biu_pad_htrans ),
.biu_pad_hwdata (biu_pad_hwdata ),
.biu_pad_hwrite (biu_pad_hwrite ),
.biu_pad_rready (rready_s2 ),
.biu_pad_wdata (biu_pad_wdata ),
.biu_pad_wid (biu_pad_wid ),
.biu_pad_wlast (biu_pad_wlast ),
.biu_pad_wstrb (biu_pad_wstrb ),
.biu_pad_wvalid (wvalid_s2 ),
.pad_biu_arready (arready_s2 ),
.pad_biu_awready (awready_s2 ),
.pad_biu_bid (bid_s2 ),
.pad_biu_bresp (bresp_s2 ),
.pad_biu_bvalid (bvalid_s2 ),
.pad_biu_hgrant (pad_biu_hgrant ),
.pad_biu_hrdata (pad_biu_hrdata ),
.pad_biu_hready (pad_biu_hready ),
.pad_biu_hresp (pad_biu_hresp ),
.pad_biu_rdata (rdata_s2 ),
.pad_biu_rid (rid_s2 ),
.pad_biu_rlast (rlast_s2 ),
.pad_biu_rresp (rresp_s2 ),
.pad_biu_rvalid (rvalid_s2 ),
.pad_biu_wready (wready_s2 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk )
);
axi_err128 x_axi_err1 (
.araddr_s1 (fifo_pad_araddr ),
.arburst_s1 (fifo_pad_arburst),
.arcache_s1 (fifo_pad_arcache),
.arid_s1 (fifo_pad_arid ),
.arlen_s1 (fifo_pad_arlen ),
.arprot_s1 (fifo_pad_arprot ),
.arready_s1 (arready_s3 ),
.arsize_s1 (fifo_pad_arsize ),
.arvalid_s1 (arvalid_s3 ),
.awaddr_s1 (biu_pad_awaddr ),
.awburst_s1 (biu_pad_awburst ),
.awcache_s1 (biu_pad_awcache ),
.awid_s1 (biu_pad_awid ),
.awlen_s1 (biu_pad_awlen ),
.awprot_s1 (biu_pad_awprot ),
.awready_s1 (awready_s3 ),
.awsize_s1 (biu_pad_awsize ),
.awvalid_s1 (awvalid_s3 ),
.bid_s1 (bid_s3 ),
.bready_s1 (bready_s3 ),
.bresp_s1 (bresp_s3 ),
.bvalid_s1 (bvalid_s3 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk ),
.rdata_s1 (rdata_s3 ),
.rid_s1 (rid_s3 ),
.rlast_s1 (rlast_s3 ),
.rready_s1 (rready_s3 ),
.rresp_s1 (rresp_s3 ),
.rvalid_s1 (rvalid_s3 ),
.wdata_s1 (biu_pad_wdata ),
.wid_s1 (biu_pad_wid ),
.wlast_s1 (biu_pad_wlast ),
.wready_s1 (wready_s3 ),
.wstrb_s1 (biu_pad_wstrb ),
.wvalid_s1 (wvalid_s3 )
);
assign #1 biu_pad_htrans_dly[1:0] = biu_pad_htrans[1:0];
assign #1 haddr_dly[39:0] = biu_pad_haddr[39:0];
assign #1 biu_pad_hwrite_dly = biu_pad_hwrite;
ahb x_ahb (
.biu_pad_haddr (haddr_dly ),
.biu_pad_hburst (biu_pad_hburst ),
.biu_pad_hbusreq (biu_pad_hbusreq ),
.biu_pad_hlock (biu_pad_hlock ),
.biu_pad_hprot (biu_pad_hprot ),
.biu_pad_hsize (biu_pad_hsize ),
.biu_pad_htrans (biu_pad_htrans_dly),
.biu_pad_hwdata (biu_pad_hwdata ),
.biu_pad_hwrite (biu_pad_hwrite_dly),
.haddr_s1 (haddr_s1 ),
.haddr_s2 (haddr_s2 ),
.haddr_s3 (haddr_s3 ),
.hburst_s1 (hburst_s1 ),
.hburst_s2 (hburst_s2 ),
.hburst_s3 (hburst_s3 ),
.hmastlock (hmastlock ),
.hprot_s1 (hprot_s1 ),
.hprot_s2 (hprot_s2 ),
.hprot_s3 (hprot_s3 ),
.hrdata_s1 (hrdata_s1 ),
.hrdata_s2 (hrdata_s2 ),
.hrdata_s3 (hrdata_s3 ),
.hready_s1 (hready_s1 ),
.hready_s2 (hready_s2 ),
.hready_s3 (hready_s3 ),
.hresp_s1 (hresp_s1 ),
.hresp_s2 (hresp_s2 ),
.hresp_s3 (hresp_s3 ),
.hsel_s1 (hsel_s1 ),
.hsel_s2 (hsel_s2 ),
.hsel_s3 (hsel_s3 ),
.hsize_s1 (hsize_s1 ),
.hsize_s2 (hsize_s2 ),
.hsize_s3 (hsize_s3 ),
.htrans_s1 (htrans_s1 ),
.htrans_s2 (htrans_s2 ),
.htrans_s3 (htrans_s3 ),
.hwdata_s1 (hwdata_s1 ),
.hwdata_s2 (hwdata_s2 ),
.hwdata_s3 (hwdata_s3 ),
.hwrite_s1 (hwrite_s1 ),
.hwrite_s2 (hwrite_s2 ),
.hwrite_s3 (hwrite_s3 ),
.pad_biu_hgrant (pad_biu_hgrant ),
.pad_biu_hrdata (pad_biu_hrdata ),
.pad_biu_hready (pad_biu_hready ),
.pad_biu_hresp (pad_biu_hresp ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk )
);
mem_ctrl x_mem_ctrl (
.haddr_s1 (haddr_s1 ),
.hburst_s1 (hburst_s1 ),
.hprot_s1 (hprot_s1 ),
.hrdata_s1 (hrdata_s1 ),
.hready_s1 (hready_s1 ),
.hresp_s1 (hresp_s1 ),
.hsel_s1 (hsel_s1 ),
.hsize_s1 (hsize_s1 ),
.htrans_s1 (htrans_s1 ),
.hwdata_s1 (hwdata_s1 ),
.hwrite_s1 (hwrite_s1 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk )
);
apb x_apb (
.b_pad_gpio_porta (b_pad_gpio_porta),
.biu_pad_haddr (haddr_dly ),
.biu_pad_hprot (biu_pad_hprot ),
.biu_pad_lpmd_b (biu_pad_lpmd_b ),
.clk_en (axim_clk_en ),
.haddr_s2 (haddr_s2 ),
.hburst_s2 (hburst_s2 ),
.hmastlock (hmastlock ),
.hprot_s2 (hprot_s2 ),
.hrdata_s2 (hrdata_s2 ),
.hready_s2 (hready_s2 ),
.hresp_s2 (hresp_s2 ),
.hsel_s2 (hsel_s2 ),
.hsize_s2 (hsize_s2 ),
.htrans_s2 (htrans_s2 ),
.hwdata_s2 (hwdata_s2 ),
.hwrite_s2 (hwrite_s2 ),
.i_pad_clk (i_pad_clk ),
.pad_biu_clkratio ( ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.cpu_clk (cpu_clk ),
`ifdef PMU_LP_MODE_TEST
.pmu_cpu_pwr_on (pmu_cpu_pwr_on ),
.pmu_cpu_iso_in (pmu_cpu_iso_in ),
.pmu_cpu_iso_out (pmu_cpu_iso_out ),
.pmu_cpu_save (pmu_cpu_save ),
.pmu_cpu_restore (pmu_cpu_restore ),
`endif
.uart0_sin (uart0_sin ),
.uart0_sout (uart0_sout ),
.xx_intc_vld (xx_intc_vld )
);
err_gen x_err_gen (
.hburst_s3 (hburst_s3 ),
.hmastlock (hmastlock ),
.hprot_s3 (hprot_s3 ),
.hrdata_s3 (hrdata_s3 ),
.hready_s3 (hready_s3 ),
.hresp_s3 (hresp_s3 ),
.hsel_s3 (hsel_s3 ),
.hsize_s3 (hsize_s3 ),
.htrans_s3 (htrans_s3 ),
.hwdata_s3 (hwdata_s3 ),
.hwrite_s3 (hwrite_s3 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pll_core_cpuclk (per_clk )
);
endmodule |
module rv_integration_platform
///////////////////////////////////////////////////
// Ports Declarations
///////////////////////////////////////////////////
(
axim_clk_en ,
pad_biu_arready ,
pad_biu_awready ,
pad_biu_bid ,
pad_biu_bresp ,
pad_biu_bvalid ,
pad_biu_csysreq ,
pad_biu_rdata ,
pad_biu_rid ,
pad_biu_rlast ,
pad_biu_rresp ,
pad_biu_rvalid ,
pad_biu_wready ,
pad_core0_dbg_mask ,
pad_core0_dbgrq_b ,
pad_core0_rst_b ,
pad_core0_hartid ,
pad_cpu_apb_base ,
pad_cpu_l2cache_flush_req ,
pad_cpu_rst_b ,
pad_core0_rvba ,
pad_cpu_sys_cnt ,
pad_had_jtg_tclk ,
pad_had_jtg_tdi ,
pad_had_jtg_tms ,
pad_had_jtg_trst_b ,
pad_l2c_data_mbist_clk_ratio ,
pad_l2c_tag_mbist_clk_ratio ,
pad_plic_int_cfg ,
pad_plic_int_vld ,
pad_yy_dft_clk_rst_b ,
pad_yy_icg_scan_en ,
pad_yy_mbist_mode ,
pad_yy_scan_enable ,
pad_yy_scan_mode ,
pad_yy_scan_rst_b ,
pll_cpu_clk ,
biu_pad_araddr ,
biu_pad_arburst ,
biu_pad_arcache ,
biu_pad_arid ,
biu_pad_arlen ,
biu_pad_arlock ,
biu_pad_arprot ,
biu_pad_arsize ,
biu_pad_arvalid ,
biu_pad_awaddr ,
biu_pad_awburst ,
biu_pad_awcache ,
biu_pad_awid ,
biu_pad_awlen ,
biu_pad_awlock ,
biu_pad_awprot ,
biu_pad_awsize ,
biu_pad_awvalid ,
biu_pad_bready ,
biu_pad_cactive ,
biu_pad_csysack ,
biu_pad_rready ,
biu_pad_wdata ,
biu_pad_wlast ,
biu_pad_wstrb ,
biu_pad_wvalid ,
core0_pad_jdb_pm ,
core0_pad_lpmd_b ,
core0_pad_mstatus ,
core0_pad_retire0 ,
core0_pad_retire0_pc ,
core0_pad_retire1 ,
core0_pad_retire1_pc ,
core0_pad_retire2 ,
core0_pad_retire2_pc ,
cpu_debug_port ,
//----- Core 1 -----
pad_core1_dbg_mask ,
pad_core1_dbgrq_b ,
pad_core1_rst_b ,
pad_core1_hartid ,
pad_core1_rvba ,
core1_pad_jdb_pm ,
core1_pad_lpmd_b ,
core1_pad_mstatus ,
core1_pad_retire0 ,
core1_pad_retire0_pc ,
core1_pad_retire1 ,
core1_pad_retire1_pc ,
core1_pad_retire2 ,
core1_pad_retire2_pc ,
cpu_pad_l2cache_flush_done ,
cpu_pad_no_op ,
had_pad_jtg_tdo ,
had_pad_jtg_tdo_en
);
///////////////////////////////////////////////////
// Input/Output Declarations
///////////////////////////////////////////////////
input axim_clk_en ;
input pad_biu_arready ;
input pad_biu_awready ;
input [7 : 0] pad_biu_bid ;
input [1 : 0] pad_biu_bresp ;
input pad_biu_bvalid ;
input pad_biu_csysreq ;
input [127 : 0] pad_biu_rdata ;
input [7 : 0] pad_biu_rid ;
input pad_biu_rlast ;
input [3 : 0] pad_biu_rresp ;
input pad_biu_rvalid ;
input pad_biu_wready ;
input pad_core0_dbg_mask ;
input pad_core0_dbgrq_b ;
input pad_core0_rst_b ;
input [2 : 0] pad_core0_hartid ;
input [39 : 0] pad_cpu_apb_base ;
input pad_cpu_l2cache_flush_req ;
input pad_cpu_rst_b ;
input [39 : 0] pad_core0_rvba ;
input [63 : 0] pad_cpu_sys_cnt ;
input pad_had_jtg_tclk ;
input pad_had_jtg_tdi ;
input pad_had_jtg_tms ;
input pad_had_jtg_trst_b ;
input [2 : 0] pad_l2c_data_mbist_clk_ratio ;
input [2 : 0] pad_l2c_tag_mbist_clk_ratio ;
input [144 - 1 : 0] pad_plic_int_cfg ;
input [144 - 1 : 0] pad_plic_int_vld ;
input pad_yy_dft_clk_rst_b ;
input pad_yy_icg_scan_en ;
input pad_yy_mbist_mode ;
input pad_yy_scan_enable ;
input pad_yy_scan_mode ;
input pad_yy_scan_rst_b ;
input pll_cpu_clk ;
output [39 : 0] biu_pad_araddr ;
output [1 : 0] biu_pad_arburst ;
output [3 : 0] biu_pad_arcache ;
output [7 : 0] biu_pad_arid ;
output [7 : 0] biu_pad_arlen ;
output biu_pad_arlock ;
output [2 : 0] biu_pad_arprot ;
output [2 : 0] biu_pad_arsize ;
output biu_pad_arvalid ;
output [39 : 0] biu_pad_awaddr ;
output [1 : 0] biu_pad_awburst ;
output [3 : 0] biu_pad_awcache ;
output [7 : 0] biu_pad_awid ;
output [7 : 0] biu_pad_awlen ;
output biu_pad_awlock ;
output [2 : 0] biu_pad_awprot ;
output [2 : 0] biu_pad_awsize ;
output biu_pad_awvalid ;
output biu_pad_bready ;
output biu_pad_cactive ;
output biu_pad_csysack ;
output biu_pad_rready ;
output [127 : 0] biu_pad_wdata ;
output biu_pad_wlast ;
output [15 : 0] biu_pad_wstrb ;
output biu_pad_wvalid ;
output [1 : 0] core0_pad_jdb_pm ;
output [1 : 0] core0_pad_lpmd_b ;
output [63 : 0] core0_pad_mstatus ;
output core0_pad_retire0 ;
output [39 : 0] core0_pad_retire0_pc ;
output core0_pad_retire1 ;
output [39 : 0] core0_pad_retire1_pc ;
output core0_pad_retire2 ;
output [39 : 0] core0_pad_retire2_pc ;
output cpu_pad_l2cache_flush_done ;
output cpu_pad_no_op ;
output had_pad_jtg_tdo ;
output had_pad_jtg_tdo_en ;
output cpu_debug_port ;
//----- Core 1 -----
input pad_core1_dbg_mask ;
input pad_core1_dbgrq_b ;
input pad_core1_rst_b ;
input [2 : 0] pad_core1_hartid ;
input [39 : 0] pad_core1_rvba ;
output [1 : 0] core1_pad_jdb_pm ;
output [1 : 0] core1_pad_lpmd_b ;
output [63 : 0] core1_pad_mstatus ;
output core1_pad_retire0 ;
output [39 : 0] core1_pad_retire0_pc ;
output core1_pad_retire1 ;
output [39 : 0] core1_pad_retire1_pc ;
output core1_pad_retire2 ;
output [39 : 0] core1_pad_retire2_pc ;
///////////////////////////////////////////////////
// Wire Declarations
///////////////////////////////////////////////////
wire axim_clk_en ;
wire pad_biu_arready ;
wire pad_biu_awready ;
wire [7 : 0] pad_biu_bid ;
wire [1 : 0] pad_biu_bresp ;
wire pad_biu_bvalid ;
wire pad_biu_csysreq ;
wire [127 : 0] pad_biu_rdata ;
wire [7 : 0] pad_biu_rid ;
wire pad_biu_rlast ;
wire [3 : 0] pad_biu_rresp ;
wire pad_biu_rvalid ;
wire pad_biu_wready ;
wire pad_core0_dbg_mask ;
wire pad_core0_dbgrq_b ;
wire pad_core0_rst_b ;
wire [2 : 0] pad_core0_hartid ;
wire [39 : 0] pad_cpu_apb_base ;
wire pad_cpu_l2cache_flush_req ;
wire pad_cpu_rst_b ;
wire [39 : 0] pad_core0_rvba ;
wire [63 : 0] pad_cpu_sys_cnt ;
wire pad_had_jtg_tclk ;
wire pad_had_jtg_tdi ;
wire pad_had_jtg_tms ;
wire pad_had_jtg_trst_b ;
wire [2 : 0] pad_l2c_data_mbist_clk_ratio ;
wire [2 : 0] pad_l2c_tag_mbist_clk_ratio ;
wire [144 - 1 : 0] pad_plic_int_cfg ;
wire [144 - 1 : 0] pad_plic_int_vld ;
wire pad_yy_dft_clk_rst_b ;
wire pad_yy_icg_scan_en ;
wire pad_yy_mbist_mode ;
wire pad_yy_scan_enable ;
wire pad_yy_scan_mode ;
wire pad_yy_scan_rst_b ;
wire pll_cpu_clk ;
wire [39 : 0] biu_pad_araddr ;
wire [1 : 0] biu_pad_arburst ;
wire [3 : 0] biu_pad_arcache ;
wire [7 : 0] biu_pad_arid ;
wire [7 : 0] biu_pad_arlen ;
wire biu_pad_arlock ;
wire [2 : 0] biu_pad_arprot ;
wire [2 : 0] biu_pad_arsize ;
wire biu_pad_arvalid ;
wire [39 : 0] biu_pad_awaddr ;
wire [1 : 0] biu_pad_awburst ;
wire [3 : 0] biu_pad_awcache ;
wire [7 : 0] biu_pad_awid ;
wire [7 : 0] biu_pad_awlen ;
wire biu_pad_awlock ;
wire [2 : 0] biu_pad_awprot ;
wire [2 : 0] biu_pad_awsize ;
wire biu_pad_awvalid ;
wire biu_pad_bready ;
wire biu_pad_cactive ;
wire biu_pad_csysack ;
wire biu_pad_rready ;
wire [127 : 0] biu_pad_wdata ;
wire biu_pad_wlast ;
wire [15 : 0] biu_pad_wstrb ;
wire biu_pad_wvalid ;
wire [1 : 0] core0_pad_jdb_pm ;
wire [1 : 0] core0_pad_lpmd_b ;
wire [63 : 0] core0_pad_mstatus ;
wire core0_pad_retire0 ;
wire [39 : 0] core0_pad_retire0_pc ;
wire core0_pad_retire1 ;
wire [39 : 0] core0_pad_retire1_pc ;
wire core0_pad_retire2 ;
wire [39 : 0] core0_pad_retire2_pc ;
wire cpu_pad_l2cache_flush_done ;
wire cpu_pad_no_op ;
wire had_pad_jtg_tdo ;
wire had_pad_jtg_tdo_en ;
wire cpu_debug_port ;
//----- Core 1 -----
wire pad_core1_dbg_mask ;
wire pad_core1_dbgrq_b ;
wire pad_core1_rst_b ;
wire [2 : 0] pad_core1_hartid ;
wire [39 : 0] pad_core1_rvba ;
wire [1 : 0] core1_pad_jdb_pm ;
wire [1 : 0] core1_pad_lpmd_b ;
wire [63 : 0] core1_pad_mstatus ;
wire core1_pad_retire0 ;
wire [39 : 0] core1_pad_retire0_pc ;
wire core1_pad_retire1 ;
wire [39 : 0] core1_pad_retire1_pc ;
wire core1_pad_retire2 ;
wire [39 : 0] core1_pad_retire2_pc ;
///////////////////////////////////////////////////
// Module Instantiation
///////////////////////////////////////////////////
openC910 x_cpu_top(
.axim_clk_en (axim_clk_en ),
.pad_biu_arready (pad_biu_arready ),
.pad_biu_awready (pad_biu_awready ),
.pad_biu_bid (pad_biu_bid ),
.pad_biu_bresp (pad_biu_bresp ),
.pad_biu_bvalid (pad_biu_bvalid ),
.pad_biu_csysreq (pad_biu_csysreq ),
.pad_biu_rdata (pad_biu_rdata ),
.pad_biu_rid (pad_biu_rid ),
.pad_biu_rlast (pad_biu_rlast ),
.pad_biu_rresp (pad_biu_rresp[1:0] ),
.pad_biu_rvalid (pad_biu_rvalid ),
.pad_biu_wready (pad_biu_wready ),
.pad_core0_dbg_mask (pad_core0_dbg_mask ),
.pad_core0_dbgrq_b (pad_core0_dbgrq_b ),
.pad_core0_rst_b (pad_core0_rst_b ),
.pad_core0_hartid (pad_core0_hartid ),
.pad_cpu_apb_base (pad_cpu_apb_base ),
.pad_cpu_l2cache_flush_req (pad_cpu_l2cache_flush_req ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_core0_rvba (pad_core0_rvba ),
.pad_cpu_sys_cnt (pad_cpu_sys_cnt ),
.pad_had_jtg_tclk (pad_had_jtg_tclk ),
.pad_had_jtg_tdi (pad_had_jtg_tdi ),
.pad_had_jtg_tms (pad_had_jtg_tms ),
.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
.pad_l2c_data_mbist_clk_ratio (pad_l2c_data_mbist_clk_ratio ),
.pad_l2c_tag_mbist_clk_ratio (pad_l2c_tag_mbist_clk_ratio ),
.pad_plic_int_cfg (pad_plic_int_cfg ),
.pad_plic_int_vld (pad_plic_int_vld ),
.pad_yy_dft_clk_rst_b (pad_yy_dft_clk_rst_b ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.pad_yy_mbist_mode (pad_yy_mbist_mode ),
.pad_yy_scan_enable (pad_yy_scan_enable ),
.pad_yy_scan_mode (pad_yy_scan_mode ),
.pad_yy_scan_rst_b (pad_yy_scan_rst_b ),
.pll_cpu_clk (pll_cpu_clk ),
.biu_pad_araddr (biu_pad_araddr ),
.biu_pad_arburst (biu_pad_arburst ),
.biu_pad_arcache (biu_pad_arcache ),
.biu_pad_arid (biu_pad_arid ),
.biu_pad_arlen (biu_pad_arlen ),
.biu_pad_arlock (biu_pad_arlock ),
.biu_pad_arprot (biu_pad_arprot ),
.biu_pad_arsize (biu_pad_arsize ),
.biu_pad_arvalid (biu_pad_arvalid ),
.biu_pad_awaddr (biu_pad_awaddr ),
.biu_pad_awburst (biu_pad_awburst ),
.biu_pad_awcache (biu_pad_awcache ),
.biu_pad_awid (biu_pad_awid ),
.biu_pad_awlen (biu_pad_awlen ),
.biu_pad_awlock (biu_pad_awlock ),
.biu_pad_awprot (biu_pad_awprot ),
.biu_pad_awsize (biu_pad_awsize ),
.biu_pad_awvalid (biu_pad_awvalid ),
.biu_pad_bready (biu_pad_bready ),
.biu_pad_cactive (biu_pad_cactive ),
.biu_pad_csysack (biu_pad_csysack ),
.biu_pad_rready (biu_pad_rready ),
.biu_pad_wdata (biu_pad_wdata ),
.biu_pad_wlast (biu_pad_wlast ),
.biu_pad_wstrb (biu_pad_wstrb ),
.biu_pad_wvalid (biu_pad_wvalid ),
.core0_pad_jdb_pm (core0_pad_jdb_pm ),
.core0_pad_lpmd_b (core0_pad_lpmd_b ),
.core0_pad_mstatus (core0_pad_mstatus ),
.core0_pad_retire0 (core0_pad_retire0 ),
.core0_pad_retire0_pc (core0_pad_retire0_pc ),
.core0_pad_retire1 (core0_pad_retire1 ),
.core0_pad_retire1_pc (core0_pad_retire1_pc ),
.core0_pad_retire2 (core0_pad_retire2 ),
.core0_pad_retire2_pc (core0_pad_retire2_pc ),
.cpu_debug_port (cpu_debug_port ),
//----- Core 1 -----
.pad_core1_dbg_mask (pad_core1_dbg_mask ),
.pad_core1_dbgrq_b (pad_core1_dbgrq_b ),
.pad_core1_rst_b (pad_core1_rst_b ),
.pad_core1_hartid (pad_core1_hartid ),
.pad_core1_rvba (pad_core1_rvba ),
.core1_pad_jdb_pm (core1_pad_jdb_pm ),
.core1_pad_lpmd_b (core1_pad_lpmd_b ),
.core1_pad_mstatus (core1_pad_mstatus ),
.core1_pad_retire0 (core1_pad_retire0 ),
.core1_pad_retire0_pc (core1_pad_retire0_pc ),
.core1_pad_retire1 (core1_pad_retire1 ),
.core1_pad_retire1_pc (core1_pad_retire1_pc ),
.core1_pad_retire2 (core1_pad_retire2 ),
.core1_pad_retire2_pc (core1_pad_retire2_pc ),
.cpu_pad_l2cache_flush_done (cpu_pad_l2cache_flush_done ),
.cpu_pad_no_op (cpu_pad_no_op ),
.had_pad_jtg_tdo (had_pad_jtg_tdo ),
.had_pad_jtg_tdo_en (had_pad_jtg_tdo_en )
);
endmodule |
module clk_gen(
clkrst_b,
i_pad_clk,
clk_en,
psel,
penable,
prdata,
pwdata,
pwrite,
gate_en0,
gate_en1,
pad_biu_clkratio,
per_clk,
cpu_clk
);
input clkrst_b;
input i_pad_clk;
input penable;
input psel;
input [2 :0] pwdata;
input pwrite;
input gate_en0;
input gate_en1;
output clk_en;
output [2 :0] pad_biu_clkratio;
output per_clk;
output cpu_clk;
output [31:0] prdata;
wire [31:0] prdata;
wire clk_en;
wire clkrst_b;
wire i_pad_clk;
wire [2 :0] pad_biu_clkratio;
wire penable;
wire per_clk;
wire cpu_clk;
wire psel;
wire [2 :0] pwdata;
wire pwrite;
// configure parameter for system clock dividor
// 0 not support
//
// default 1:1. all case can run in this configuration
// 1 = 1:1
//
// some case may run fail
// 2 = 2:1
// 3 = 3:1
// 4 = 4:1
// 5 = 5:1
//........
// 7 = 7:1
parameter CLK_RATIO = 3'd1;
reg [2:0] cnt;
reg cnt_zero;
wire sys_clk;
always @(posedge i_pad_clk or negedge clkrst_b)
begin
if(!clkrst_b)
cnt[2:0] <= 3'b0;
else if(cnt == (CLK_RATIO - 1))
cnt[2:0] <= 3'b0;
else
cnt[2:0] <= cnt[2:0] + 3'd1;
end
always @(posedge i_pad_clk or negedge clkrst_b)
begin
if(!clkrst_b)
cnt_zero <= 1'b1;
else if(cnt == (CLK_RATIO - 1))
cnt_zero <= 1'b1;
else
cnt_zero <= 1'b0;
end
assign sys_clk = (CLK_RATIO == 1) ? i_pad_clk
: cnt_zero;
assign clk_en = (CLK_RATIO == 1) ? 1'b1
: (CLK_RATIO == 2) ? cnt_zero
: (cnt == CLK_RATIO - 2);
assign prdata[31:0] = {29'b0,CLK_RATIO};
assign pad_biu_clkratio[2:0] = CLK_RATIO;
reg [3:0] div_cnt;
reg slow_clk;
always @(posedge i_pad_clk or negedge clkrst_b) begin
if (!clkrst_b) begin
div_cnt <= 4'hf;
slow_clk <= 1'b0;
end
else begin
if(div_cnt != 4'h0) begin
div_cnt <= div_cnt - 1;
slow_clk <= slow_clk;
end
else begin
div_cnt <= 4'hf;
slow_clk <= ~slow_clk;
end
end
end
assign per_clk = sys_clk;
assign cpu_clk = gate_en0 ? slow_clk : (gate_en1 ? 1'b0 : i_pad_clk);
// assign cpu_clk = i_pad_clk;
endmodule |
module BUFGCE(
I,
CE,
O
);
input I;
input CE;
output O;
wire clk_in;
wire external_en;
assign clk_in = I;
assign external_en = CE;
reg clk_en_af_latch;
always @(clk_in or external_en)
begin
if(!clk_in)
clk_en_af_latch <= external_en;
end
reg clk_en ;
always @ (clk_en_af_latch )
begin
clk_en <= clk_en_af_latch;
end
assign O = clk_in && clk_en ;
endmodule |
module wid_for_axi4(
biu_pad_awid,
biu_pad_awvalid,
pad_biu_awready,
biu_pad_wvalid,
biu_pad_wlast,
pad_biu_wready,
pad_cpu_rst_b,
biu_pad_wid,
per_clk
);
input [7:0] biu_pad_awid;
input pad_cpu_rst_b;
input per_clk;
input biu_pad_awvalid;
input pad_biu_awready;
input biu_pad_wvalid;
input biu_pad_wlast;
input pad_biu_wready;
output [7:0] biu_pad_wid;
reg [4 :0] wid_fifo_create;
reg [4 :0] wid_fifo_pop;
reg [7 :0] wid_m1_8;
wire [7 :0] wid_0;
wire [7 :0] wid_1;
wire [7 :0] wid_10;
wire [7 :0] wid_11;
wire [7 :0] wid_12;
wire [7 :0] wid_13;
wire [7 :0] wid_14;
wire [7 :0] wid_15;
wire [7 :0] wid_16;
wire [7 :0] wid_17;
wire [7 :0] wid_18;
wire [7 :0] wid_19;
wire [7 :0] wid_2;
wire [7 :0] wid_20;
wire [7 :0] wid_21;
wire [7 :0] wid_22;
wire [7 :0] wid_23;
wire [7 :0] wid_24;
wire [7 :0] wid_25;
wire [7 :0] wid_26;
wire [7 :0] wid_27;
wire [7 :0] wid_28;
wire [7 :0] wid_29;
wire [7 :0] wid_3;
wire [7 :0] wid_30;
wire [7 :0] wid_31;
wire [7 :0] wid_4;
wire [7 :0] wid_5;
wire [7 :0] wid_6;
wire [7 :0] wid_7;
wire [7 :0] wid_8;
wire [7 :0] wid_9;
wire [31 :0] wid_entry_push;
assign create_en = biu_pad_awvalid && pad_biu_awready;
always@(posedge per_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
wid_fifo_create[4:0] <= 5'b0;
else if (create_en)
wid_fifo_create[4:0] <= wid_fifo_create[4:0] + 5'b1;
end
assign wid_entry_push[31:0] = {32{create_en}} & (32'b1<<wid_fifo_create[4:0]);
always@(posedge per_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
wid_fifo_pop[4:0] <= 5'b0;
else if (biu_pad_wvalid && biu_pad_wlast&& pad_biu_wready)
wid_fifo_pop[4:0] <= wid_fifo_pop[4:0] + 5'b1;
end
always @( wid_17[7:0]
or wid_27[7:0]
or wid_25[7:0]
or wid_15[7:0]
or wid_11[7:0]
or wid_12[7:0]
or wid_8[7:0]
or wid_14[7:0]
or wid_2[7:0]
or wid_16[7:0]
or wid_31[7:0]
or wid_9[7:0]
or wid_4[7:0]
or wid_20[7:0]
or wid_22[7:0]
or wid_28[7:0]
or wid_5[7:0]
or wid_29[7:0]
or wid_7[7:0]
or wid_3[7:0]
or wid_10[7:0]
or wid_1[7:0]
or wid_24[7:0]
or wid_19[7:0]
or wid_13[7:0]
or wid_0[7:0]
or wid_23[7:0]
or wid_6[7:0]
or wid_21[7:0]
or wid_26[7:0]
or wid_18[7:0]
or wid_30[7:0]
or wid_fifo_pop[4:0])
begin
wid_m1_8[7:0] = 5'b0;
case(wid_fifo_pop[4:0])
5'b00000: wid_m1_8[7:0] = wid_0[7:0];
5'b00001: wid_m1_8[7:0] = wid_1[7:0];
5'b00010: wid_m1_8[7:0] = wid_2[7:0];
5'b00011: wid_m1_8[7:0] = wid_3[7:0];
5'b00100: wid_m1_8[7:0] = wid_4[7:0];
5'b00101: wid_m1_8[7:0] = wid_5[7:0];
5'b00110: wid_m1_8[7:0] = wid_6[7:0];
5'b00111: wid_m1_8[7:0] = wid_7[7:0];
5'b01000: wid_m1_8[7:0] = wid_8[7:0];
5'b01001: wid_m1_8[7:0] = wid_9[7:0];
5'b01010: wid_m1_8[7:0] = wid_10[7:0];
5'b01011: wid_m1_8[7:0] = wid_11[7:0];
5'b01100: wid_m1_8[7:0] = wid_12[7:0];
5'b01101: wid_m1_8[7:0] = wid_13[7:0];
5'b01110: wid_m1_8[7:0] = wid_14[7:0];
5'b01111: wid_m1_8[7:0] = wid_15[7:0];
5'b10000: wid_m1_8[7:0] = wid_16[7:0];
5'b10001: wid_m1_8[7:0] = wid_17[7:0];
5'b10010: wid_m1_8[7:0] = wid_18[7:0];
5'b10011: wid_m1_8[7:0] = wid_19[7:0];
5'b10100: wid_m1_8[7:0] = wid_20[7:0];
5'b10101: wid_m1_8[7:0] = wid_21[7:0];
5'b10110: wid_m1_8[7:0] = wid_22[7:0];
5'b10111: wid_m1_8[7:0] = wid_23[7:0];
5'b11000: wid_m1_8[7:0] = wid_24[7:0];
5'b11001: wid_m1_8[7:0] = wid_25[7:0];
5'b11010: wid_m1_8[7:0] = wid_26[7:0];
5'b11011: wid_m1_8[7:0] = wid_27[7:0];
5'b11100: wid_m1_8[7:0] = wid_28[7:0];
5'b11101: wid_m1_8[7:0] = wid_29[7:0];
5'b11110: wid_m1_8[7:0] = wid_30[7:0];
5'b11111: wid_m1_8[7:0] = wid_31[7:0];
default: wid_m1_8[7:0] = 8'b0;
endcase
end
wid_entry x_wid_entry_31 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_31 ),
.wid_entry_push (wid_entry_push[31])
);
wid_entry x_wid_entry_30 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_30 ),
.wid_entry_push (wid_entry_push[30])
);
wid_entry x_wid_entry_29 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_29 ),
.wid_entry_push (wid_entry_push[29])
);
wid_entry x_wid_entry_28 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_28 ),
.wid_entry_push (wid_entry_push[28])
);
wid_entry x_wid_entry_27 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_27 ),
.wid_entry_push (wid_entry_push[27])
);
wid_entry x_wid_entry_26 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_26 ),
.wid_entry_push (wid_entry_push[26])
);
wid_entry x_wid_entry_25 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_25 ),
.wid_entry_push (wid_entry_push[25])
);
wid_entry x_wid_entry_24 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_24 ),
.wid_entry_push (wid_entry_push[24])
);
wid_entry x_wid_entry_23 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_23 ),
.wid_entry_push (wid_entry_push[23])
);
wid_entry x_wid_entry_22 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_22 ),
.wid_entry_push (wid_entry_push[22])
);
wid_entry x_wid_entry_21 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_21 ),
.wid_entry_push (wid_entry_push[21])
);
wid_entry x_wid_entry_20 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_20 ),
.wid_entry_push (wid_entry_push[20])
);
wid_entry x_wid_entry_19 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_19 ),
.wid_entry_push (wid_entry_push[19])
);
wid_entry x_wid_entry_18 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_18 ),
.wid_entry_push (wid_entry_push[18])
);
wid_entry x_wid_entry_17 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_17 ),
.wid_entry_push (wid_entry_push[17])
);
wid_entry x_wid_entry_16 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_16 ),
.wid_entry_push (wid_entry_push[16])
);
wid_entry x_wid_entry_15 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_15 ),
.wid_entry_push (wid_entry_push[15])
);
wid_entry x_wid_entry_14 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_14 ),
.wid_entry_push (wid_entry_push[14])
);
wid_entry x_wid_entry_13 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_13 ),
.wid_entry_push (wid_entry_push[13])
);
wid_entry x_wid_entry_12 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_12 ),
.wid_entry_push (wid_entry_push[12])
);
wid_entry x_wid_entry_11 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_11 ),
.wid_entry_push (wid_entry_push[11])
);
wid_entry x_wid_entry_10 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_10 ),
.wid_entry_push (wid_entry_push[10])
);
wid_entry x_wid_entry_9 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_9 ),
.wid_entry_push (wid_entry_push[9])
);
wid_entry x_wid_entry_8 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_8 ),
.wid_entry_push (wid_entry_push[8])
);
wid_entry x_wid_entry_7 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_7 ),
.wid_entry_push (wid_entry_push[7])
);
wid_entry x_wid_entry_6 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_6 ),
.wid_entry_push (wid_entry_push[6])
);
wid_entry x_wid_entry_5 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_5 ),
.wid_entry_push (wid_entry_push[5])
);
wid_entry x_wid_entry_4 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_4 ),
.wid_entry_push (wid_entry_push[4])
);
wid_entry x_wid_entry_3 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_3 ),
.wid_entry_push (wid_entry_push[3])
);
wid_entry x_wid_entry_2 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_2 ),
.wid_entry_push (wid_entry_push[2])
);
wid_entry x_wid_entry_1 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_1 ),
.wid_entry_push (wid_entry_push[1])
);
wid_entry x_wid_entry_0 (
.biu_pad_awid (biu_pad_awid ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.per_clk (per_clk ),
.wid (wid_0 ),
.wid_entry_push (wid_entry_push[0])
);
assign biu_pad_wid[7:0] = wid_m1_8[7:0];
endmodule |
module cpu_sub_system_axi
///////////////////////////////////////////////////
// Ports Declarations
///////////////////////////////////////////////////
(
axim_clk_en ,
pad_biu_arready ,
pad_biu_awready ,
pad_biu_bid ,
pad_biu_bresp ,
pad_biu_bvalid ,
pad_biu_rdata ,
pad_biu_rid ,
pad_biu_rlast ,
pad_biu_rresp ,
pad_biu_rvalid ,
pad_biu_wready ,
pad_cpu_rst_b ,
pad_had_jtg_tclk ,
pad_had_jtg_tdi ,
pad_had_jtg_trst_b ,
pad_yy_dft_clk_rst_b ,
pll_cpu_clk ,
biu_pad_araddr ,
biu_pad_arburst ,
biu_pad_arcache ,
biu_pad_arid ,
biu_pad_arlen ,
biu_pad_arlock ,
biu_pad_arprot ,
biu_pad_arsize ,
biu_pad_arvalid ,
biu_pad_awaddr ,
biu_pad_awburst ,
biu_pad_awcache ,
biu_pad_awid ,
biu_pad_awlen ,
biu_pad_awlock ,
biu_pad_awprot ,
biu_pad_awsize ,
biu_pad_awvalid ,
biu_pad_bready ,
biu_pad_rready ,
biu_pad_wdata ,
biu_pad_wlast ,
biu_pad_wstrb ,
biu_pad_wvalid ,
had_pad_jtg_tdo ,
had_pad_jtg_tdo_en ,
//-------------------
`ifdef PMU_LP_MODE_TEST
pmu_cpu_pwr_on ,
pmu_cpu_iso_in ,
pmu_cpu_iso_out,
pmu_cpu_save ,
pmu_cpu_restore,
`endif
xx_intc_vld ,
per_clk ,
i_pad_jtg_tms ,
biu_pad_wid ,
biu_pad_lpmd_b
);
///////////////////////////////////////////////////
// Input/Output Declarations
///////////////////////////////////////////////////
input axim_clk_en ;
input pad_biu_arready ;
input pad_biu_awready ;
input [7 : 0] pad_biu_bid ;
input [1 : 0] pad_biu_bresp ;
input pad_biu_bvalid ;
input [127 : 0] pad_biu_rdata ;
input [7 : 0] pad_biu_rid ;
input pad_biu_rlast ;
input [3 : 0] pad_biu_rresp ;
input pad_biu_rvalid ;
input pad_biu_wready ;
input pad_cpu_rst_b ;
input pad_had_jtg_tclk ;
input pad_had_jtg_tdi ;
input pad_had_jtg_trst_b ;
input pad_yy_dft_clk_rst_b ;
input pll_cpu_clk ;
output [39 : 0] biu_pad_araddr ;
output [1 : 0] biu_pad_arburst ;
output [3 : 0] biu_pad_arcache ;
output [7 : 0] biu_pad_arid ;
output [7 : 0] biu_pad_arlen ;
output biu_pad_arlock ;
output [2 : 0] biu_pad_arprot ;
output [2 : 0] biu_pad_arsize ;
output biu_pad_arvalid ;
output [39 : 0] biu_pad_awaddr ;
output [1 : 0] biu_pad_awburst ;
output [3 : 0] biu_pad_awcache ;
output [7 : 0] biu_pad_awid ;
output [7 : 0] biu_pad_awlen ;
output biu_pad_awlock ;
output [2 : 0] biu_pad_awprot ;
output [2 : 0] biu_pad_awsize ;
output biu_pad_awvalid ;
output biu_pad_bready ;
output biu_pad_rready ;
output [127 : 0] biu_pad_wdata ;
output biu_pad_wlast ;
output [15 : 0] biu_pad_wstrb ;
output biu_pad_wvalid ;
output had_pad_jtg_tdo ;
output had_pad_jtg_tdo_en ;
//----------------------------------------------------------------------
`ifdef PMU_LP_MODE_TEST
input pmu_cpu_pwr_on ;
input pmu_cpu_iso_in ;
input pmu_cpu_iso_out;
input pmu_cpu_save ;
input pmu_cpu_restore;
`endif
input per_clk;
input [39 :0] xx_intc_vld;
input i_pad_jtg_tms;
output [7 :0] biu_pad_wid;
output [1 :0] biu_pad_lpmd_b;
///////////////////////////////////////////////////
// Wire Declarations
///////////////////////////////////////////////////
wire axim_clk_en ;
wire pad_biu_arready ;
wire pad_biu_awready ;
wire [7 : 0] pad_biu_bid ;
wire [1 : 0] pad_biu_bresp ;
wire pad_biu_bvalid ;
wire [127 : 0] pad_biu_rdata ;
wire [7 : 0] pad_biu_rid ;
wire pad_biu_rlast ;
wire [3 : 0] pad_biu_rresp ;
wire pad_biu_rvalid ;
wire pad_biu_wready ;
wire pad_cpu_rst_b ;
wire pad_had_jtg_tclk ;
wire pad_had_jtg_tdi ;
wire pad_had_jtg_tms ;
wire pad_had_jtg_trst_b ;
wire [144 - 1 : 0] pad_plic_int_cfg ;
wire [144 - 1 : 0] pad_plic_int_vld ;
wire pad_yy_dft_clk_rst_b ;
wire pll_cpu_clk ;
wire [39 : 0] biu_pad_araddr ;
wire [1 : 0] biu_pad_arburst ;
wire [3 : 0] biu_pad_arcache ;
wire [7 : 0] biu_pad_arid ;
wire [7 : 0] biu_pad_arlen ;
wire biu_pad_arlock ;
wire [2 : 0] biu_pad_arprot ;
wire [2 : 0] biu_pad_arsize ;
wire biu_pad_arvalid ;
wire [39 : 0] biu_pad_awaddr ;
wire [1 : 0] biu_pad_awburst ;
wire [3 : 0] biu_pad_awcache ;
wire [7 : 0] biu_pad_awid ;
wire [7 : 0] biu_pad_awlen ;
wire biu_pad_awlock ;
wire [2 : 0] biu_pad_awprot ;
wire [2 : 0] biu_pad_awsize ;
wire biu_pad_awvalid ;
wire biu_pad_bready ;
wire biu_pad_rready ;
wire [127 : 0] biu_pad_wdata ;
wire biu_pad_wlast ;
wire [15 : 0] biu_pad_wstrb ;
wire biu_pad_wvalid ;
wire [1 : 0] core0_pad_lpmd_b ;
wire had_pad_jtg_tdo ;
wire had_pad_jtg_tdo_en ;
//----------------------------------------------------------------------
wire [7 : 0] biu_pad_wid;
wire [63 : 0] xx_intc_int;
wire [39 : 0] xx_intc_vld;
reg [63 : 0] pad_cpu_sys_cnt;
///////////////////////////////////////////////////
// Module Instantiation
///////////////////////////////////////////////////
rv_integration_platform x_rv_integration_platform (
.axim_clk_en (axim_clk_en ),
.pad_biu_arready (pad_biu_arready ),
.pad_biu_awready (pad_biu_awready ),
.pad_biu_bid (pad_biu_bid ),
.pad_biu_bresp (pad_biu_bresp ),
.pad_biu_bvalid (pad_biu_bvalid ),
.pad_biu_csysreq (1'b0 ),
.pad_biu_rdata (pad_biu_rdata ),
.pad_biu_rid (pad_biu_rid ),
.pad_biu_rlast (pad_biu_rlast ),
.pad_biu_rresp (pad_biu_rresp ),
.pad_biu_rvalid (pad_biu_rvalid ),
.pad_biu_wready (pad_biu_wready ),
.pad_core0_dbg_mask (1'b0 ),
.pad_core0_dbgrq_b (1'b1 ),
.pad_core0_rst_b (pad_cpu_rst_b ),
.pad_core0_hartid (3'h0 ),
.pad_cpu_apb_base (`APB_BASE_ADDR ),
.pad_cpu_l2cache_flush_req (1'b0 ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_core0_rvba (40'b0 ),
.pad_cpu_sys_cnt (pad_cpu_sys_cnt ),
.pad_had_jtg_tclk (pad_had_jtg_tclk ),
.pad_had_jtg_tdi (pad_had_jtg_tdi ),
.pad_had_jtg_tms (pad_had_jtg_tms ),
.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
.pad_l2c_data_mbist_clk_ratio (3'b0 ),
.pad_l2c_tag_mbist_clk_ratio (3'b0 ),
.pad_plic_int_cfg (pad_plic_int_cfg ),
.pad_plic_int_vld (pad_plic_int_vld ),
.pad_yy_dft_clk_rst_b (pad_yy_dft_clk_rst_b ),
.pad_yy_icg_scan_en (1'b0 ),
.pad_yy_mbist_mode (1'b0 ),
.pad_yy_scan_enable (1'b0 ),
.pad_yy_scan_mode (1'b0 ),
.pad_yy_scan_rst_b (1'b1 ),
.pll_cpu_clk (pll_cpu_clk ),
.biu_pad_araddr (biu_pad_araddr ),
.biu_pad_arburst (biu_pad_arburst ),
.biu_pad_arcache (biu_pad_arcache ),
.biu_pad_arid (biu_pad_arid ),
.biu_pad_arlen (biu_pad_arlen ),
.biu_pad_arlock (biu_pad_arlock ),
.biu_pad_arprot (biu_pad_arprot ),
.biu_pad_arsize (biu_pad_arsize ),
.biu_pad_arvalid (biu_pad_arvalid ),
.biu_pad_awaddr (biu_pad_awaddr ),
.biu_pad_awburst (biu_pad_awburst ),
.biu_pad_awcache (biu_pad_awcache ),
.biu_pad_awid (biu_pad_awid ),
.biu_pad_awlen (biu_pad_awlen ),
.biu_pad_awlock (biu_pad_awlock ),
.biu_pad_awprot (biu_pad_awprot ),
.biu_pad_awsize (biu_pad_awsize ),
.biu_pad_awvalid (biu_pad_awvalid ),
.biu_pad_bready (biu_pad_bready ),
.biu_pad_cactive ( ),
.biu_pad_csysack ( ),
.biu_pad_rready (biu_pad_rready ),
.biu_pad_wdata (biu_pad_wdata ),
.biu_pad_wlast (biu_pad_wlast ),
.biu_pad_wstrb (biu_pad_wstrb ),
.biu_pad_wvalid (biu_pad_wvalid ),
// .core0_pad_dispatch0_info ( ),
// .core0_pad_dispatch1_info ( ),
// .core0_pad_dispatch2_info ( ),
// .core0_pad_dispatch3_info ( ),
// .core0_pad_dispatch_info ( ),
// .core0_pad_flush ( ),
.core0_pad_jdb_pm ( ),
.core0_pad_lpmd_b (core0_pad_lpmd_b ),
.core0_pad_mstatus ( ),
.core0_pad_retire0 ( ),
// .core0_pad_retire0_iid ( ),
.core0_pad_retire0_pc ( ),
.core0_pad_retire1 ( ),
// .core0_pad_retire1_iid ( ),
.core0_pad_retire1_pc ( ),
.core0_pad_retire2 ( ),
// .core0_pad_retire2_iid ( ),
.core0_pad_retire2_pc ( ),
// .core0_pad_wb0_data ( ),
// .core0_pad_wb0_edata ( ),
// .core0_pad_wb0_ereg ( ),
// .core0_pad_wb0_ereg_vld ( ),
// .core0_pad_wb0_fdata ( ),
// .core0_pad_wb0_freg ( ),
// .core0_pad_wb0_freg_vld ( ),
// .core0_pad_wb0_preg ( ),
// .core0_pad_wb0_vdata ( ),
// .core0_pad_wb0_vld ( ),
// .core0_pad_wb0_vreg ( ),
// .core0_pad_wb0_vreg_vld ( ),
// .core0_pad_wb1_data ( ),
// .core0_pad_wb1_edata ( ),
// .core0_pad_wb1_ereg ( ),
// .core0_pad_wb1_ereg_vld ( ),
// .core0_pad_wb1_fdata ( ),
// .core0_pad_wb1_freg ( ),
// .core0_pad_wb1_freg_vld ( ),
// .core0_pad_wb1_preg ( ),
// .core0_pad_wb1_vdata ( ),
// .core0_pad_wb1_vld ( ),
// .core0_pad_wb1_vreg ( ),
// .core0_pad_wb1_vreg_vld ( ),
// .core0_pad_wb2_data ( ),
// .core0_pad_wb2_fdata ( ),
// .core0_pad_wb2_freg ( ),
// .core0_pad_wb2_freg_vld ( ),
// .core0_pad_wb2_preg ( ),
// .core0_pad_wb2_vdata ( ),
// .core0_pad_wb2_vld ( ),
// .core0_pad_wb2_vreg ( ),
// .core0_pad_wb2_vreg_vld ( ),
.cpu_debug_port ( ),
//----- Core 1 -----
.pad_core1_dbg_mask (1'b0 ),
.pad_core1_dbgrq_b (1'b1 ),
.pad_core1_rst_b (1'b0 ),
.pad_core1_hartid (3'h1 ),
.pad_core1_rvba (40'h0 ),
.core1_pad_jdb_pm ( ),
.core1_pad_lpmd_b ( ),
.core1_pad_mstatus ( ),
.core1_pad_retire0 ( ),
.core1_pad_retire0_pc ( ),
.core1_pad_retire1 ( ),
.core1_pad_retire1_pc ( ),
.core1_pad_retire2 ( ),
.core1_pad_retire2_pc ( ),
.cpu_pad_l2cache_flush_done ( ),
.cpu_pad_no_op ( ),
.had_pad_jtg_tdo (had_pad_jtg_tdo ),
.had_pad_jtg_tdo_en (had_pad_jtg_tdo_en )
);
assign pad_had_jtg_tms = i_pad_jtg_tms;
assign biu_pad_lpmd_b[1:0] = core0_pad_lpmd_b;
// system timer simple model
always@(posedge pll_cpu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
pad_cpu_sys_cnt <= 64'b0;
else
pad_cpu_sys_cnt <= pad_cpu_sys_cnt + 1'b1;
end
// External Interrupts
// assign xx_intc_int[63:0] = {24'b0,xx_intc_vld[39:0]};
// assign pad_plic_int_vld = {{ 144 - 40{1'b0}}, xx_intc_vld[39:0]};
assign pad_plic_int_vld[ 39 : 0] = xx_intc_vld[ 39 : 0];
assign pad_plic_int_vld[144 - 1 : 32] = 'h0;
assign pad_plic_int_cfg = 'b0;
// for fiting AXI3 system bus
wire [7 :0] tmp_biu_pad_awid ;
wire tmp_biu_pad_awvalid ;
wire tmp_biu_pad_wvalid ;
wire tmp_biu_pad_wlast ;
wire tmp_pad_biu_awready ;
wire tmp_pad_biu_wready ;
assign # 0.1 tmp_biu_pad_awid = biu_pad_awid;
assign # 0.1 tmp_biu_pad_awvalid = biu_pad_awvalid;
assign # 0.1 tmp_biu_pad_wvalid = biu_pad_wvalid;
assign # 0.1 tmp_biu_pad_wlast = biu_pad_wlast;
assign # 0.1 tmp_pad_biu_awready = pad_biu_awready;
assign # 0.1 tmp_pad_biu_wready = pad_biu_wready;
wid_for_axi4 wid_for_axi4 (
.biu_pad_awid (tmp_biu_pad_awid),
.biu_pad_awvalid (tmp_biu_pad_awvalid),
.biu_pad_wvalid (tmp_biu_pad_wvalid),
.biu_pad_wlast (tmp_biu_pad_wlast),
.pad_biu_awready (tmp_pad_biu_awready),
.pad_biu_wready (tmp_pad_biu_wready),
.pad_cpu_rst_b (pad_cpu_rst_b),
.biu_pad_wid (biu_pad_wid),
.per_clk (per_clk)
);
endmodule |
module int_mnt();
endmodule |
module pmu(
apb_pmu_paddr,
apb_pmu_penable,
apb_pmu_psel,
apb_pmu_pwdata,
apb_pmu_pwrite,
biu_pad_lpmd_b,
corec_pmu_sleep_out,
cpu_clk,
gate_en0,
gate_en1,
had_pad_wakeup_req_b,
i_pad_cpu_jtg_rst_b,
i_pad_jtg_tclk,
intraw_vld,
pad_cpu_rst_b,
pad_had_jdb_req_b,
pad_had_jtg_tap_en,
pad_had_jtg_tms,
pad_had_jtg_trst_b,
pad_had_jtg_trst_b_pre,
pg_reset_b,
pmu_apb_prdata,
pmu_clk,
// pmu_corec_isolation,
// pmu_corec_sleep_in,
pmu_cpu_pwr_on,
pmu_cpu_iso_in,
pmu_cpu_iso_out,
pmu_cpu_save,
pmu_cpu_restore
);
// &Ports; @25
input [11:0] apb_pmu_paddr;
input apb_pmu_penable;
input apb_pmu_psel;
input [31:0] apb_pmu_pwdata;
input apb_pmu_pwrite;
input [1 :0] biu_pad_lpmd_b;
input corec_pmu_sleep_out;
input cpu_clk;
input had_pad_wakeup_req_b;
input i_pad_cpu_jtg_rst_b;
input i_pad_jtg_tclk;
input intraw_vld;
input pad_cpu_rst_b;
input pad_had_jtg_tap_en;
input pad_had_jtg_tms;
input pad_had_jtg_trst_b_pre;
input pmu_clk;
output gate_en0;
output gate_en1;
output pad_had_jdb_req_b;
output pad_had_jtg_trst_b;
output pg_reset_b;
output [31:0] pmu_apb_prdata;
// output pmu_corec_isolation;
// output pmu_corec_sleep_in;
output pmu_cpu_pwr_on;
output pmu_cpu_iso_in;
output pmu_cpu_iso_out;
output pmu_cpu_save;
output pmu_cpu_restore;
// &Regs; @26
reg [31:0] counter;
reg counter_en_ff;
reg [31:0] counter_load;
reg [31:0] ctrl_reg;
reg [2 :0] cur_state;
reg debug_pending;
reg event_ff;
reg event_pending;
reg [2 :0] next_state;
reg [2 :0] pg_next_state;
reg [2 :0] pg_state;
reg [31:0] pmu_apb_prdata;
// Supporting various low power strategies
reg [31:0] pmu_lp_mode_sel;
// &Wires; @27
wire [11:0] apb_pmu_paddr;
wire apb_pmu_penable;
wire apb_pmu_psel;
wire [31:0] apb_pmu_pwdata;
wire apb_pmu_pwrite;
wire [1 :0] biu_pad_lpmd_b;
wire corec_pmu_sleep_out;
wire counter_en;
wire cpu_clk;
wire debug_ctl_en;
wire debug_vld;
wire debug_vld_pre;
wire debug_wake_vld;
wire doze_mode;
wire event_ctl_en;
wire event_vld;
wire gate_en0;
wire gate_en1;
wire had_pad_wakeup_req_b;
wire i_pad_cpu_jtg_rst_b;
wire i_pad_jtg_tclk;
wire intraw_vld;
wire load_cnt_en;
wire low_power_dis;
wire low_power_dis_pre;
wire lpmd_en;
wire lpmd_en_ff;
wire pad_cpu_rst_b;
wire pad_had_jdb_req_b;
wire pad_had_jtg_tap_en;
wire pad_had_jtg_tms;
wire pad_had_jtg_trst_b;
wire pad_had_jtg_trst_b_pre;
wire pad_vic_event_vld;
wire pg_reset_b;
wire pmu_clk;
// wire pmu_corec_isolation;
// wire pmu_corec_sleep_in;
reg pmu_cpu_pwr_on;
reg pmu_cpu_iso_in;
reg pmu_cpu_iso_out;
reg pmu_cpu_save;
reg pmu_cpu_restore;
wire pmu_debug_wakeup;
wire pmu_event_wakeup;
wire pmu_wakeup;
wire pmu_wic_wakeup;
wire stop_mode;
wire wait_mode;
wire wic_ctl_en;
// Supporting various low power strategies
wire pmu_lp_mode_normal;
wire pmu_lp_mode_clk_slow;
wire pmu_lp_mode_clk_off;
wire pmu_lp_mode_ret_pwr_off;
wire pmu_lp_mode_pwr_off;
parameter NORMAL_MODE = 3'b000; // 0x0
parameter LIGHT_SLP_MODE = 3'b001; // 0x1
parameter LSLP_TO_NORMAL = 3'b010; // 0x2
parameter DEEP_SLP_MODE = 3'b011; // 0x3
parameter DSLP_TO_NORMAL = 3'b100; // 0x4
parameter PG_IDLE = 3'b000;
parameter PG_RESET_ON = 3'b001;
parameter PG_ISO_ON = 3'b010;
parameter PG_POWER_OFF_REQ = 3'b011;
parameter PG_POWER_OFF = 3'b100;
parameter PG_POWER_ON = 3'b101;
parameter PG_ISO_OFF = 3'b110;
parameter PG_RESET_OFF = 3'b111;
assign low_power_dis_pre = (biu_pad_lpmd_b[1:0] == 2'b11);
assign lpmd_en = (biu_pad_lpmd_b[1:0] != 2'b11) ;
////////////sync /////////////////////
// &Instance("sync", "x_cpu2pmu_sync1"); @58
sync x_cpu2pmu_sync1 (
.fast_clk (cpu_clk ),
.in (lpmd_en ),
.out (lpmd_en_ff ),
.pad_cpu_rst_b (pad_cpu_rst_b),
.slow_clk (pmu_clk )
);
// &Connect( .in ( lpmd_en ), @59
// .out ( lpmd_en_ff ), @60
// .fast_clk ( cpu_clk ), @61
// .slow_clk ( pmu_clk ) @62
// ); @63
// &Instance("sync", "x_cpu2pmu_sync2"); @69
sync x_cpu2pmu_sync2 (
.fast_clk (cpu_clk ),
.in (low_power_dis_pre),
.out (low_power_dis ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.slow_clk (pmu_clk )
);
// &Connect( .in ( low_power_dis_pre ), @70
// .out ( low_power_dis ), @71
// .fast_clk ( cpu_clk ), @72
// .slow_clk ( pmu_clk ) @73
// ); @74
//------------------------------------------------
//WRITE CTRL REG
//------------------------------------------------
always @ (posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
begin
ctrl_reg[31:0] <= 32'b0;
pmu_lp_mode_sel[31:0] <= 32'b0;
end
else if (apb_pmu_psel && apb_pmu_pwrite && apb_pmu_penable)
begin
if (!apb_pmu_paddr[11:0] )
ctrl_reg[31:0] <= apb_pmu_pwdata[31:0];
else if (apb_pmu_paddr[11:0] == 12'h4 )
counter_load[31:0] <= apb_pmu_pwdata[31:0];
else if (apb_pmu_paddr[11:0] == 12'h8 )
pmu_lp_mode_sel[31:0] <= cur_state[2:0] == NORMAL_MODE ? apb_pmu_pwdata[31:0] : pmu_lp_mode_sel[31:0];
end
end
//------------------------------------------------
//READ CTRL REG
//------------------------------------------------
// &CombBeg; @99
always @( apb_pmu_paddr[11:0]
or ctrl_reg[3:0]
or apb_pmu_psel
or apb_pmu_pwrite
or counter[31:0])
begin
if (apb_pmu_psel && !apb_pmu_pwrite)
begin
if(!apb_pmu_paddr[11:0] )
pmu_apb_prdata[31:0] = {28'b0,ctrl_reg[3:0]};
else if (apb_pmu_paddr[11:0] == 12'h4 )
pmu_apb_prdata[31:0] = counter[31:0];
else if (apb_pmu_paddr[11:0] == 12'h8 )
pmu_apb_prdata[31:0] = pmu_lp_mode_sel[31:0];
else
pmu_apb_prdata[31:0] = 32'b0;
end
// &CombEnd; @109
end
assign wic_ctl_en = ctrl_reg[0];
assign event_ctl_en = ctrl_reg[1];
assign debug_ctl_en = ctrl_reg[2];
assign counter_en = ctrl_reg[3];
//event counter
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
begin
counter_en_ff <=0;
end
else
begin
counter_en_ff <=counter_en ;
end
end
assign load_cnt_en= (counter_en && !counter_en_ff)
|| !(|counter[31:0]);
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
begin
counter[31:0] <= 32'h0;
end
else if (load_cnt_en)
begin
counter[31:0] <= counter_load[31:0];
end
else if (counter_en)
counter[31:0] <= counter[31:0] -1'b1;
else
counter[31:0] <= counter[31:0];
end
assign pad_vic_event_vld = (counter[31:0] == 32'b0) && counter_en;
assign pmu_wic_wakeup = intraw_vld && wic_ctl_en && lpmd_en_ff ;
// event_wakeup
assign event_vld = pad_vic_event_vld && !event_ff && lpmd_en_ff ;
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
event_ff <= 1'b0;
else
event_ff <= pad_vic_event_vld;
end
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
event_pending <= 1'b0;
else if (event_vld)
event_pending <= 1'b1;
else if (low_power_dis)
event_pending <= 1'b0;
end
assign pmu_event_wakeup = event_pending && event_ctl_en ;
//debug wake up
// &Instance("tap2_sm", "x_tap2_sm"); @180
tap2_sm x_tap2_sm (
.debug_wake_vld (debug_wake_vld ),
.pad_had_jtg_tap_en (pad_had_jtg_tap_en ),
.tclk (i_pad_jtg_tclk ),
.tms_i (pad_had_jtg_tms ),
.trst_b (i_pad_cpu_jtg_rst_b)
);
assign debug_vld_pre = (debug_wake_vld || !had_pad_wakeup_req_b) && lpmd_en_ff;
// &Instance("px_had_sync", "x_jtag2pmu_sync"); @193
px_had_sync x_jtag2pmu_sync (
.clk1 (i_pad_jtg_tclk ),
.clk2 (pmu_clk ),
.rst1_b (pad_had_jtg_trst_b_pre),
.rst2_b (pad_cpu_rst_b ),
.sync_in (debug_vld_pre ),
.sync_out (debug_vld )
);
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
debug_pending <= 1'b0;
else if (debug_vld)
debug_pending <= 1'b1;
else if (low_power_dis)
debug_pending <= 1'b0;
end
assign pad_had_jdb_req_b = !debug_pending;
assign pmu_debug_wakeup = debug_pending && debug_ctl_en ;
/////
assign pmu_wakeup = pmu_event_wakeup || pmu_wic_wakeup || pmu_debug_wakeup ;
// Supporting various low power strategies
assign pmu_lp_mode_pwr_off = pmu_lp_mode_sel[4]; // Deep
assign pmu_lp_mode_ret_pwr_off = pmu_lp_mode_sel[3]; // Deep
assign pmu_lp_mode_clk_off = pmu_lp_mode_sel[2]; // Light
assign pmu_lp_mode_clk_slow = pmu_lp_mode_sel[1]; // Light
assign pmu_lp_mode_normal = pmu_lp_mode_sel[0]; // Normal
//-----------------------------------------
// PMU FSM
//-----------------------------------------
wire normal_req;
// wire light_slp_req;
// wire deep_slp_req;
wire cpu_slp_req;
assign normal_req = biu_pad_lpmd_b[1:0] == 2'b11;
// assign light_slp_req = biu_pad_lpmd_b[1:0] == 2'b01;
// assign deep_slp_req = biu_pad_lpmd_b[1:0] == 2'b00;
assign cpu_slp_req = biu_pad_lpmd_b[1:0] != 2'b11;
reg dslp_in_sequence_req;
reg dslp_in_sequence_done;
reg dslp_out_sequence_req;
reg dslp_out_sequence_done;
reg [15:0] dslp_sequence_counter;
reg dslp_sequence_counter_enable;
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b)
cur_state[2:0] <= NORMAL_MODE;
else
cur_state[2:0] <= next_state[2:0];
end
always @(*) begin
case(cur_state)
NORMAL_MODE:
begin
if(pmu_lp_mode_normal)
next_state = NORMAL_MODE;
else if(pmu_lp_mode_clk_slow || pmu_lp_mode_clk_off)
if(cpu_slp_req)
next_state = LIGHT_SLP_MODE;
else
next_state = NORMAL_MODE;
else if(pmu_lp_mode_ret_pwr_off || pmu_lp_mode_pwr_off)
if(cpu_slp_req)
next_state = DEEP_SLP_MODE;
else
next_state = NORMAL_MODE;
else
next_state = NORMAL_MODE;
end
LIGHT_SLP_MODE:
begin
if(pmu_wakeup)
next_state = LSLP_TO_NORMAL;
else
next_state = LIGHT_SLP_MODE;
end
LSLP_TO_NORMAL:
begin
if(normal_req)
next_state = NORMAL_MODE;
else
next_state = LSLP_TO_NORMAL;
end
DEEP_SLP_MODE:
begin
if(pmu_wakeup && dslp_in_sequence_done)
next_state = DSLP_TO_NORMAL;
else
next_state = DEEP_SLP_MODE;
end
DSLP_TO_NORMAL:
begin
if(normal_req && dslp_out_sequence_done)
next_state = NORMAL_MODE;
else
next_state = DSLP_TO_NORMAL;
end
endcase
end
// gate_en0/1 (connected to fpga_clk_gen), reused as:
// gate_en0:
// 0: clock normal
// 1: clock slow
// gate_en1:
// 0: clock normal
// 1: clock off
assign gate_en0 = (cur_state[2:0] == LIGHT_SLP_MODE) && pmu_lp_mode_clk_slow ? 1 : 0;
assign gate_en1 = (cur_state[2:0] == LIGHT_SLP_MODE && pmu_lp_mode_clk_off) ||
(cur_state[2:0] == DEEP_SLP_MODE && pmu_lp_mode_ret_pwr_off)
? 1 : 0;
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if (!pad_cpu_rst_b) begin
dslp_in_sequence_req <= 1'b0;
dslp_out_sequence_req <= 1'b0;
end
else if (cur_state[2:0] == NORMAL_MODE && next_state[2:0] == DEEP_SLP_MODE) begin
dslp_in_sequence_req <= 1'b1;
dslp_out_sequence_req <= 1'b0;
end
else if (cur_state[2:0] == DEEP_SLP_MODE && next_state[2:0] == DSLP_TO_NORMAL) begin
dslp_in_sequence_req <= 1'b0;
dslp_out_sequence_req <= 1'b1;
end
else begin
dslp_in_sequence_req <= 1'b0;
dslp_out_sequence_req <= 1'b0;
end
end
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
dslp_sequence_counter_enable <= 1'b0;
else if (dslp_in_sequence_req || dslp_out_sequence_req)
dslp_sequence_counter_enable <= 1'b1;
else if (dslp_in_sequence_done || dslp_out_sequence_done)
dslp_sequence_counter_enable <= 1'b0;
else
dslp_sequence_counter_enable <= dslp_sequence_counter_enable;
end
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
dslp_sequence_counter[15:0] <= 16'h0;
else if (dslp_sequence_counter_enable)
dslp_sequence_counter[15:0] <= dslp_sequence_counter[15:0] + 1'b1;
else
dslp_sequence_counter[15:0] <= 16'h0;
end
always @(posedge pmu_clk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b0;
pmu_cpu_iso_out <= 1'b0;
pmu_cpu_save <= 1'b0;
pmu_cpu_restore <= 1'b0;
dslp_in_sequence_done <= 1'b0;
dslp_out_sequence_done <= 1'b0;
end
else if (cur_state[2:0] == DEEP_SLP_MODE)
begin
pmu_cpu_restore <= 1'b0;
dslp_out_sequence_done <= 1'b0;
case(dslp_sequence_counter[15:0])
16'h1:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b0;
pmu_cpu_iso_out <= 1'b0;
pmu_cpu_save <= 1'b0;
end
16'h20:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_save <= 1'b0;
end
16'h40:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_save <= 1'b1;
end
16'h41:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_save <= 1'b0;
end
16'h60:
begin
pmu_cpu_pwr_on <= 1'b0;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_save <= 1'b0;
dslp_in_sequence_done <= 1'b1;
end
default:
begin
pmu_cpu_pwr_on <= pmu_cpu_pwr_on ;
pmu_cpu_iso_in <= pmu_cpu_iso_in ;
pmu_cpu_iso_out <= pmu_cpu_iso_out;
pmu_cpu_save <= pmu_cpu_save ;
dslp_in_sequence_done <= dslp_in_sequence_done;
end
endcase
end
else if (cur_state[2:0] == DSLP_TO_NORMAL)
begin
pmu_cpu_save <= 1'b0;
dslp_in_sequence_done <= 1'b0;
case(dslp_sequence_counter[15:0])
16'h1:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_restore <= 1'b0;
dslp_out_sequence_done <= 1'b0;
end
16'h20:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_restore <= 1'b1;
dslp_out_sequence_done <= 1'b0;
end
16'h21:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b1;
pmu_cpu_iso_out <= 1'b1;
pmu_cpu_restore <= 1'b0;
dslp_out_sequence_done <= 1'b0;
end
16'h40:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b0;
pmu_cpu_iso_out <= 1'b0;
pmu_cpu_restore <= 1'b0;
dslp_out_sequence_done <= 1'b0;
end
16'h60:
begin
pmu_cpu_pwr_on <= 1'b1;
pmu_cpu_iso_in <= 1'b0;
pmu_cpu_iso_out <= 1'b0;
pmu_cpu_restore <= 1'b0;
dslp_out_sequence_done <= 1'b1;
end
default:
begin
pmu_cpu_pwr_on <= pmu_cpu_pwr_on ;
pmu_cpu_iso_in <= pmu_cpu_iso_in ;
pmu_cpu_iso_out <= pmu_cpu_iso_out;
pmu_cpu_restore <= pmu_cpu_restore ;
dslp_out_sequence_done <= dslp_out_sequence_done;
end
endcase
end
else
begin
pmu_cpu_pwr_on <= pmu_cpu_pwr_on ;
pmu_cpu_iso_in <= pmu_cpu_iso_in ;
pmu_cpu_iso_out <= pmu_cpu_iso_out;
pmu_cpu_save <= pmu_cpu_save ;
pmu_cpu_restore <= pmu_cpu_restore;
dslp_in_sequence_done <= dslp_in_sequence_done;
dslp_out_sequence_done <= dslp_out_sequence_done;
end
end
// assign pg_reset_b = pad_cpu_rst_b && tdt_dm_pad_ndmreset_n;
assign pg_reset_b = pad_cpu_rst_b;
assign pad_had_jtg_trst_b = pad_had_jtg_trst_b_pre;
// &ModuleEnd; @389
endmodule |
module debug_stim();
endmodule |
module debug_stim(
);
reg[15:0] hsr_data_out;
reg[63:0] wbbr_data_out;
reg[63:0] rand_data;
initial
begin
hsr_data_out = 0;
wbbr_data_out = 0;
rand_data = 0;
#10000;
jtag_rst(32'h10);
open_event;
//===============================================
//Main Program: 1. Set DR enter debug mode and then clear DR bit.
//===============================================
write_hadreg_corea(`hcr,32'h8000); //set DR
wait_debug_mode_corea;
write_hadreg_corea(`hcr,32'h0); //clear DR
write_hadreg_corea(`event_outen,32'h0);
//-----------------------------------------------
//1. initial base register
//2. use ld inst access address stored in base register
//-----------------------------------------------
write_hadreg_corea(`csr,16'h100); //set FFY=1
rand_data = 64'h0;
$display("Write X6 = 0x%h",rand_data);
write_hadreg_corea(`wbbr,rand_data);
write_hadreg_corea(`ir_go_nex,`MV_X6_X6); //write X6
write_hadreg_corea(`csr,16'h0); //set FFY=0
//Set FFY=0 Read Memory
write_hadreg_corea(`csr,16'h0);
write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
hsr_data_out[12] = 0;
while(!hsr_data_out[12])
read_hadreg_corea(`hsr,hsr_data_out);
read_hadreg_corea(`wbbr,wbbr_data_out);
$display("read address 0 = 0x%h",wbbr_data_out);
//-----------------------------------------------
//Set FFY=1 Write Memory
write_hadreg_corea(`csr,16'h100);
// initial base register
write_hadreg_corea(`wbbr,64'h0);
write_hadreg_corea(`ir_go_nex,`MV_X6_X6);
write_hadreg_corea(`wbbr,64'h1111111111111111);
$display("write address 0 = 0x%h",64'h1111111111111111);
write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
write_hadreg_corea(`ir_go_nex,`SD_X7_0_X6);
write_hadreg_corea(`wbbr,64'h2222222222222222);
$display("write address 8 = 0x%h",64'h2222222222222222);
write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
write_hadreg_corea(`ir_go_nex,`SD_X7_8_X6);
write_hadreg_corea(`wbbr,64'h3333333333333333);
$display("write address 16 = 0x%h",64'h3333333333333333);
write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
write_hadreg_corea(`ir_go_nex,`SD_X7_16_X6);
write_hadreg_corea(`wbbr,64'h4444444444444444);
$display("write address 24 = 0x%h",64'h4444444444444444);
write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
write_hadreg_corea(`ir_go_nex,`SD_X7_24_X6);
//Set FFY=0 Read Memory
write_hadreg_corea(`csr,16'h0);
write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
hsr_data_out[12] = 0;
while(!hsr_data_out[12])
read_hadreg_corea(`hsr,hsr_data_out);
read_hadreg_corea(`wbbr,wbbr_data_out);
if(wbbr_data_out == 64'h1111111111111111)
$display("Success!Addr at X6+0 mem is 0x%h!",wbbr_data_out);
else begin
$display("Fail!Addr at X6+0 mem is 0x%h!",wbbr_data_out);
// write_hadreg_corea(`pc_go_ex,`TEST_FAIL);
$finish;
end
write_hadreg_corea(`ir_go_nex,`LD_X7_8_X6 );
wbbr_data_out = 64'h0;
hsr_data_out[12] = 0;
while(!hsr_data_out[12])
read_hadreg_corea(`hsr,hsr_data_out);
read_hadreg_corea(`wbbr,wbbr_data_out);
if(wbbr_data_out == 64'h2222222222222222)
$display("Success!Addr at X6+8 mem is 0x%h!",wbbr_data_out);
else begin
$display("Fail!Addr at X6+8 mem is 0x%h!",wbbr_data_out);
// write_hadreg_corea(`pc_go_ex,`TEST_FAIL);
$finish;
end
write_hadreg_corea(`ir_go_nex,`LD_X7_16_X6 );
wbbr_data_out = 64'h0;
hsr_data_out[12] = 0;
while(!hsr_data_out[12])
read_hadreg_corea(`hsr,hsr_data_out);
read_hadreg_corea(`wbbr,wbbr_data_out);
if(wbbr_data_out == 64'h3333333333333333)
$display("Success!Addr at X6+16 mem is 0x%h!",wbbr_data_out);
else begin
$display("Fail!Addr at X6+16 mem is 0x%h!",wbbr_data_out);
// write_hadreg_corea(`pc_go_ex,`TEST_FAIL);
$finish;
end
write_hadreg_corea(`ir_go_nex,`LD_X7_24_X6 );
wbbr_data_out = 64'h0;
hsr_data_out[12] = 0;
while(!hsr_data_out[12])
read_hadreg_corea(`hsr,hsr_data_out);
read_hadreg_corea(`wbbr,wbbr_data_out);
if(wbbr_data_out == 64'h4444444444444444)
$display("Success!Addr at X6+24 mem is 0x%h!",wbbr_data_out);
else begin
$display("Fail!Addr at X6+24 mem is 0x%h!",wbbr_data_out);
// write_hadreg_corea(`pc_go_ex,`TEST_FAIL);
$finish;
end
$display("#####################################################");
$display("XXXXX Congratulations!!!!!! Simulation PASS!!! XXXXX");
$display("#####################################################");
$finish;
end
endmodule |
module cpu_bht_mem_test_tb(
bht_mem_passed
);
output bht_mem_passed;
reg bht_mem_passed;
//data array parameter
//branch history table parameter
parameter LOCAL_DATA_ADDR_WIDTH = 10;
//==========================================================
// Parameter Definition
//==========================================================
parameter LOCAL_DATA_DATA_WIDTH = 64;
parameter LOCAL_DATA_WE_WIDTH = 64;
//data array signal
reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH -1 : 0 ] temp_data_wen_internal ;
reg temp_data_cen_internal ;
reg temp_data_CLK ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff ;
//gated cell clk
reg temp_forever_cpuclk ;
reg temp_external_en ;
reg temp_pad_yy_test_mode ;
wire temp_xor_clk ;
integer i;
initial
begin
bht_mem_passed =1'b0;
////memory test
temp_data_CLK = 1'b0;
temp_data_cen_internal = 1'b0;
temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
temp_data_din_internal = {LOCAL_DATA_DATA_WIDTH{1'b0}};
golden_data = {LOCAL_DATA_DATA_WIDTH{1'b0}};
data_mask = {LOCAL_DATA_DATA_WIDTH{1'b0}};
#20
@(posedge temp_data_CLK)
//write
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=1;i<10;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
end
//read
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=1;i<10;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$$$ data array memory cen test cen ==1 test passed $\n");
//$display("$$$$$$$$$$ data array memory cen test cen ==0 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b1;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal === golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//wen test
//$display("$$$$$$$$$ data array memory cen test cen ==0 test passed $");
//$display("$$$$$$$$$ data array memory wen test....... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=0;i<LOCAL_DATA_WE_WIDTH/2 ;i=i+1)
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
temp_data_wen_internal <= {{LOCAL_DATA_WE_WIDTH-2{1'b1}},2'b0} <<2*i ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
@(posedge temp_data_CLK)
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
data_mask_ff <= data_mask;
@(posedge temp_data_CLK)
#0.1
// $display("$ address = %h temp_data_q_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q_internal,(golden_data &(~data_mask)),temp_data_wen_internal);
if(temp_data_q_internal !== (golden_data &(~data_mask_ff)) )
begin
// $display("$ Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \n",temp_data_q_internal,golden_data,temp_data_wen_internal);
$finish;
end
end
//write test
//$display("$$$$$$$$$ data array memory wen test passed $");
//$display("$$$$$$$$$ data array memory write test...... $");
@(posedge temp_data_CLK) //write address 0
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ data array memory read test passed $");
//$display("$$$$$$$$ data array memory address width test...... $");
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
//read data in 1/2max address
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//read data in address 0
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory address width test passed $");
//$display("$$$$$$$$ data array memory data width test...... $");
//read data check
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$$$$$$$$ bht Congratuations PASS!!!!!!!!! $");
#10
bht_mem_passed = 1'b1;
end
//Dumping Control
//initial
//begin
// $fsdbDumpfile("bht_mem.fsdb");
// $fsdbDumpon;
// $fsdbDumpvars();
// //$dumpfile("test.vcd");
// //$dumpvars;
//end
always
#(`CLK_PERIOD/2) temp_data_CLK = ~temp_data_CLK;
//always
//#(`CLK_PERIOD/2) temp_tag_CLK = ~temp_tag_CLK;
//always
//#(`CLK_PERIOD/2) temp_dirty_CLK = ~temp_dirty_CLK;
always
#(`CLK_PERIOD/2) temp_forever_cpuclk = ~temp_forever_cpuclk;
always @(posedge temp_data_CLK)
begin
//data array mask
data_mask <= { {temp_data_wen_internal[63:0]} };
end
ct_ifu_bht_pre_array x_way0_smbist_wrap (
.bht_pred_array_index ( temp_data_addr_internal ),
.bht_pred_array_cen_b ( temp_data_cen_internal ),
.forever_cpuclk ( temp_data_CLK ),
.bht_pred_array_din ( temp_data_din_internal ),
.bht_pre_data_out ( temp_data_q_internal ),
.bht_pred_bwen ( temp_data_wen_internal ),
.bht_pred_array_gwen ( &temp_data_wen_internal ),
// .pad_yy_gate_clk_en_b ( 1'b0 ),
.pad_yy_icg_scan_en ( 1'b0 ),
.cp0_ifu_icg_en ( 1'b0 ),
.cp0_yy_clk_en ( 1'b1 ),
.bht_pre_array_clk_en ( 1'b1 )
);
endmodule |
module cpu_imem_test_tb(
imem_passed
);
output imem_passed;
reg imem_passed;
//data array parameter
//==========================================================
// Parameter Definition
//==========================================================
//data array
`ifdef ICACHE_256K
parameter WIDTH = 15;
`endif
`ifdef ICACHE_128K
parameter WIDTH = 14;
`endif
`ifdef ICACHE_64K
parameter WIDTH = 13;
`endif
`ifdef ICACHE_32K
parameter WIDTH = 12;
`endif
// tag array
// `ifdef ICACHE_32K
// parameter LOCAL_DATA_ADDR_WIDTH = 31;
// parameter LOCAL_TAG_ADDR_WIDTH = 31;
// `endif
//
// `ifdef ICACHE_64K
// parameter LOCAL_DATA_ADDR_WIDTH = 14;
// parameter LOCAL_TAG_ADDR_WIDTH = 14;
// `endif
parameter LOCAL_DATA_ADDR_WIDTH = 16;
parameter LOCAL_TAG_ADDR_WIDTH = 16;
`ifdef L1_CACHE_ECC
//data
parameter LOCAL_DATA_DATA_WIDTH = 132;
//tag
parameter LOCAL_TAG_DATA_WIDTH = 61;
`else
//data
parameter LOCAL_DATA_DATA_WIDTH = 128;
//tag
parameter LOCAL_TAG_DATA_WIDTH = 59;
`endif
parameter LOCAL_DATA_WE_WIDTH = 1;
parameter LOCAL_TAG_WE_WIDTH = 3;
//data array signal
reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH -1 : 0 ] temp_data_wen_internal ;
reg temp_data_cen_internal_0 ;
reg temp_data_cen_internal_1 ;
reg temp_data_cen_internal_2 ;
reg temp_data_cen_internal_3 ;
reg temp_tag_cen_internal ;
reg temp_data_CLK ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff ;
//tag array signal
reg [ LOCAL_TAG_ADDR_WIDTH-1 : 0 ] temp_tag_addr_internal;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0 ] temp_tag_din_internal ;
reg [ LOCAL_TAG_WE_WIDTH -1 : 0 ] temp_tag_wen_internal ;
reg temp_tag_CLK ;
wire [ LOCAL_TAG_DATA_WIDTH-1 : 0] temp_tag_q_internal ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] golden_tag ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] tag_mask ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] tag_mask_ff ;
//gated cell clk
reg temp_forever_cpuclk ;
reg temp_external_en ;
reg temp_pad_yy_test_mode ;
wire temp_xor_clk ;
wire [151:0] temp_cmp ;
integer i;
initial
begin
imem_passed =1'b0;
//memory test
temp_data_CLK = 1'b0;
temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
temp_data_din_internal = {LOCAL_DATA_DATA_WIDTH{1'b0}};
golden_data = {LOCAL_DATA_DATA_WIDTH{1'b0}};
data_mask = {LOCAL_DATA_DATA_WIDTH{1'b0}};
#20
@(posedge temp_data_CLK)
//cen==1 test
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b0 ;
temp_data_cen_internal_1 = 1'b0 ;
temp_data_cen_internal_2 = 1'b0 ;
temp_data_cen_internal_3 = 1'b0 ;
for(i=1;i<10;i=i+1) //set address 1~9
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
// golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$$$ data array memory cen test cen ==1 test passed $\n");
//$display("$$$$$$$$$$ data array memory cen test cen ==0 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b1;
temp_data_cen_internal_1 = 1'b1;
temp_data_cen_internal_2 = 1'b1;
temp_data_cen_internal_3 = 1'b1;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal === golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//wen test
//$display("$$$$$$$$$ data array memory cen test cen ==0 test passed $");
//$display("$$$$$$$$$ data array memory wen test....... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
for(i=0;i<LOCAL_DATA_WE_WIDTH ;i=i+1)
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;
//golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
data_mask_ff <= data_mask;
@(posedge temp_data_CLK)
#0.3
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q_internal,(golden_data &(~data_mask)),temp_data_wen_internal);
if(temp_data_q_internal !== (golden_data & data_mask_ff))
begin
//$display("$ Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \n",temp_data_q_internal,golden_data,temp_data_wen_internal);
$finish;
end
end
//write test
//$display("$$$$$$$$$ data array memory wen test passed $");
//$display("$$$$$$$$$ data array memory write test...... $");
@(posedge temp_data_CLK) //write address 0
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i<<3;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ data array memory read test passed $");
//$display("$$$$$$$$ data array memory address width test...... $");
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= { {7'b1},{(LOCAL_DATA_ADDR_WIDTH-7){1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
//read data in 1/2max address
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= { {20'b1},{LOCAL_DATA_ADDR_WIDTH-7{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//read data in address 0
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory address width test passed $");
//$display("$$$$$$$$ data array memory data width test...... $");
//read data check
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal_0 = 1'b0;
temp_data_cen_internal_1 = 1'b0;
temp_data_cen_internal_2 = 1'b0;
temp_data_cen_internal_3 = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
temp_tag_CLK = 1'b0;
temp_tag_cen_internal = 1'b0;
temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal = {LOCAL_TAG_ADDR_WIDTH{1'b0}};
temp_tag_din_internal = {LOCAL_TAG_DATA_WIDTH{1'b0}};
golden_tag = {LOCAL_TAG_DATA_WIDTH{1'b0}};
tag_mask = {LOCAL_TAG_DATA_WIDTH{1'b0}};
#20
@(posedge temp_tag_CLK)
//cen==1 test
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$$$$$$$ tag array memory cen test cen ==1 test... $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b0 ;
for(i=1;i<10;i=i+1) //set address 1~9
begin
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b0 ;
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.1
//$display("$address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$ tag array memory cen test cen ==1 test passed $");
//$display("$$$$$$$$ tag array memory cen test cen ==0 test... $");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b1 ;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal === golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//wen testA
//$display("$$$$$$$ tag array memory cen test cen ==0 test passed $");
//$display("$$$$$$$ tag array memory wen test....... $");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b0 ;
for(i=0;i<LOCAL_TAG_WE_WIDTH + 1;i=i+1)
begin
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_wen_internal <= {{LOCAL_TAG_WE_WIDTH-1{1'b1}},1'b0} <<i ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b1}};
@(posedge temp_tag_CLK)
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
golden_tag <= temp_tag_din_internal;
tag_mask_ff <= tag_mask;
@(posedge temp_tag_CLK)
#0.3
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h,wen=%h \n",temp_tag_addr_internal,temp_tag_q_internal,(golden_tag &(~tag_mask)),temp_tag_wen_internal);
if(temp_tag_q_internal !== (golden_tag &(~tag_mask_ff)) )
begin
// $display("$ temp_tag_q_internal = %h , golden_tag =%h, wen=%h \n",temp_tag_q_internal,golden_tag,temp_tag_wen_internal);
$finish;
end
end
//write test
//$display("$$$$$$$$$ tag array memory wen test passed $");
//$display("$$$$$$$$$ tag array memory write test...... $");
@(posedge temp_tag_CLK) //write address 0
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b0 ;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b0 ;
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i<<5;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
// golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.3
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ tag array memory read test passed $");
//$display("$$$$$$$$ tag array memory address width test...... $");
@(posedge temp_tag_CLK) //write address
#0.1 temp_tag_cen_internal = 1'b0 ;
//write address 0
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
//write address 1/2 max address
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal <= {{7'b1}, {LOCAL_TAG_ADDR_WIDTH-7{1'b0}} } ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
//read address 1/2 max address
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal <= {{7'b1}, {LOCAL_TAG_ADDR_WIDTH-7{1'b0}} } ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hff;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_tag_CLK)
#0.1
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//read address 0
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hff;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_tag_CLK)
#0.1
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//$display("$$$$$$$ tag array memory address width test passed $");
//$display("$$$$$$$ tag array memory data width test...... $");
//read data check
@(posedge temp_tag_CLK) //write address
#0.1 temp_tag_cen_internal = 1'b0 ;
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b1}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//$display("$$$$$$$ tag array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$$$$$$$$ icache Congratuations PASS!!!!!!!!! $");
#10
imem_passed = 1'b1;
end
//Dumping Control
//initial
//begin
// //$display("######time:%d, Dump start######",$time);
// $fsdbDumpfile("imem_test.fsdb");
// $fsdbDumpon;
// $fsdbDumpvars();
//// $dumpfile("test.vcd");
//// $dumpvars;
//end
always
#(`CLK_PERIOD/2) temp_data_CLK = ~temp_data_CLK;
always
#(`CLK_PERIOD/2) temp_tag_CLK = ~temp_tag_CLK;
//always
//#(`CLK_PERIOD/2) temp_dirty_CLK = ~temp_dirty_CLK;
always
#(`CLK_PERIOD/2) temp_forever_cpuclk = ~temp_forever_cpuclk;
always @(posedge temp_data_CLK)
begin
//data array mask
// data_mask <= {{128{!temp_data_wen_internal[0]}} };
data_mask <= {LOCAL_DATA_DATA_WIDTH{!temp_data_wen_internal[0]}};
//tag array mask
`ifdef L1_CACHE_ECC
tag_mask <= {{1{temp_tag_wen_internal[2]}},{30{temp_tag_wen_internal[1]}},{30{temp_tag_wen_internal[0]}}};
`else
tag_mask <= {{1{temp_tag_wen_internal[2]}},{29{temp_tag_wen_internal[1]}},{29{temp_tag_wen_internal[0]}}};
`endif
//dirty array mask
//dirty_mask <={temp_dirty_wen_internal[1:0]};
end
ct_ifu_icache_data_array0 x_way0_smbist_wrap (
.ifu_icache_index ( temp_data_addr_internal ),
.ifu_icache_data_array0_bank0_cen_b ( temp_data_cen_internal_0 ),
.ifu_icache_data_array0_bank1_cen_b ( temp_data_cen_internal_1 ),
.ifu_icache_data_array0_bank2_cen_b ( temp_data_cen_internal_2 ),
.ifu_icache_data_array0_bank3_cen_b ( temp_data_cen_internal_3 ),
.ifu_icache_data_array0_bank0_clk_en ( 1'b1 ),
.ifu_icache_data_array0_bank1_clk_en ( 1'b1 ),
.ifu_icache_data_array0_bank2_clk_en ( 1'b1 ),
.ifu_icache_data_array0_bank3_clk_en ( 1'b1 ),
.forever_cpuclk ( temp_data_CLK ),
.ifu_icache_data_array0_din ( temp_data_din_internal ),
.icache_ifu_data_array0_dout ( temp_data_q_internal ),
.ifu_icache_data_array0_wen_b ( temp_data_wen_internal ),
.cp0_ifu_icg_en ( 1'b0 ),
.cp0_yy_clk_en ( 1'b1 ),
.pad_yy_icg_scan_en ( 1'b0 )
);
ct_ifu_icache_tag_array x_tag_array (
.ifu_icache_index ( temp_tag_addr_internal ),
.ifu_icache_tag_cen_b ( temp_tag_cen_internal ),
.ifu_icache_tag_clk_en ( 1'b1 ),
.forever_cpuclk ( temp_tag_CLK ),
.ifu_icache_tag_din ( temp_tag_din_internal ),
.icache_ifu_tag_dout ( temp_tag_q_internal ),
.ifu_icache_tag_wen ( temp_tag_wen_internal ),
.cp0_ifu_icg_en ( 1'b0 ),
.pad_yy_icg_scan_en ( 1'b0 )
);
endmodule |
module mem_icg_check_top();
endmodule |
module cpu_mem_icg_check_top();
wire bht_mem_passed;
wire btb_mem_passed;
wire dmem_passed;
wire imem_passed;
wire icg_passed;
wire mmu_mem_passed;
wire l2_mem_passed;
wire ifupred_mem_passed;
initial
begin
#10000
if(ifupred_mem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ifupred mem test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ ifupred_mem_test passed = %h",ifupred_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: ifupred mem test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ ifupred_mem_test passed = %h",ifupred_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
initial
begin
#10000
if(bht_mem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ bht mem test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ bht_mem_test passed = %h",bht_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: bht mem test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ bht_mem_test passed = %h",bht_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
initial
begin
#10000
`ifdef BTB
if(btb_mem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ btb mem test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ btb_mem_test passed = %h",btb_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: btb mem test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ btb_mem_test passed = %h",btb_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
`else
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ BTB not define ");
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
`endif
//#100
//$finish;
end
initial
begin
#10000
if(dmem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ dmem test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ dmem_test passed = %h",dmem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: dmem test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ dmem_test passed = %h",dmem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
initial
begin
#10000
if(imem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ imem test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ imem_test passed = %h",imem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: imem test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ imem_test passed = %h",imem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
#100
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ Congratuaion all mem & icg test PASSED!!!!!!!!!! $");
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
#100
$finish;
end
initial
begin
#10000
if(mmu_mem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ mmu_mem_test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ mmu_mem_test passed = %h",mmu_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: mmu_mem_test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ mmu_mem_test passed = %h",mmu_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
initial
begin
#100000
if(l2_mem_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ l2_mem_test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ l2_mem_test passed = %h",l2_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: l2_mem_test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ l2_mem_test passed = %h",l2_mem_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
initial
begin
#10000
if( icg_passed ===1'b1 )
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ icg_test passed!!!!!!!!!!!!!!!!!!!! $");
$display("$ icg_test passed = %h",icg_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
else
begin
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ ERROR:: icg_test failed!!!!!!!!!!!!!!!!!!!! $");
$display("$ icg_test passed = %h",icg_passed);
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$finish;
end
//#100
//$finish;
end
cpu_ifupred_mem_test_tb a(.ifupred_mem_passed(ifupred_mem_passed));
cpu_imem_test_tb b(.imem_passed (imem_passed));
cpu_icg_test_tb c(.icg_passed (icg_passed));
cpu_dmem_test_tb d(.dmem_passed (dmem_passed));
cpu_bht_mem_test_tb bht(.bht_mem_passed (bht_mem_passed));
`ifdef BTB
cpu_btb_mem_test_tb f(.btb_mem_passed (btb_mem_passed));
`endif
cpu_mmu_mem_test_tb g(.mmu_mem_passed (mmu_mem_passed));
cpu_l2_mem_test_tb h(.l2_mem_passed (l2_mem_passed));
endmodule |
module cpu_icg_test_tb(
icg_passed
);
output icg_passed;
reg icg_passed;
//data array parameter
//gated cell clk
reg temp_forever_cpuclk ;
reg temp_external_en ;
reg temp_pad_yy_test_mode ;
wire temp_xor_clk ;
always
#(`CLK_PERIOD/2) temp_forever_cpuclk = ~temp_forever_cpuclk;
`ifdef GATED_CELL
gated_clk_cell x_gated_clk_cell_xor (
.clk_in (temp_forever_cpuclk ),
.clk_out (temp_xor_clk ),
.external_en (temp_external_en ),
.global_en (1'b0 ),
.local_en (1'b0 ),
.module_en (1'b0 ),
// .pad_yy_gate_clk_en_b (temp_pad_yy_test_mode )
.pad_yy_icg_scan_en ( 1'b0 )
);
//initial
//begin
// $fsdbDumpfile("icg.fsdb");
// $fsdbDumpon;
// $fsdbDumpvars();
// //$dumpfile("test.vcd");
// // //$dumpvars;
// // end
//end
`endif
integer i;
`ifdef GATED_CELL
initial
begin
//gated cell test
#20
temp_forever_cpuclk = 1'b0;
temp_external_en = 1'b0;
temp_pad_yy_test_mode = 1'b0;
icg_passed = 1'b0;
#100
//gated celll type test
$display("$$$$$$$$$ gated clk type aftre gated,clkout should be 0 test...... $");
@(posedge temp_forever_cpuclk)
#0.1
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, aftre gated clock out is %h, gated clk check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ gated clk check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ gated clk check fail ! @_@ $",temp_xor_clk);
$finish;
end
//loacal enable enable test,clkout next cycle valid
$display("$$$$$$$$$ gated clk local en enable test...... $");
@(posedge temp_forever_cpuclk)
#0.1
temp_external_en = 1'b1;
temp_pad_yy_test_mode = 1'b0;
#0.1
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, aftre gated clock out is %h, gated clk check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ gated clk check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b1)
begin
$display("$ gated loacl en check fail ! @_@ $",temp_xor_clk);
$finish;
end
//loacal en disable test,clkout next cycle invalid
$display("$$$$$$$$$ gated clk local en disable test...... $");
@(posedge temp_forever_cpuclk)
#0.1
temp_external_en = 1'b0;
temp_pad_yy_test_mode = 1'b0;
#0.1
if(temp_xor_clk !== 1'b1)
begin
$display("$ Sorry, loacel en gated disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, loacel en gated disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, loacel en gated disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
//test en enable test,clkout current cycle vaild
$display("$$$$$$$$$ gated clk test en enable test...... $");
@(posedge temp_forever_cpuclk)
#0.1
// temp_external_en = 1'b0;
// temp_pad_yy_test_mode = 1'b1;
// #0.1
// if(temp_xor_clk !== 1'b1)
// begin
// $display("$ Sorry, test en enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b0)
// begin
// $display("$ Sorry, test en enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b1)
// begin
// $display("$ Sorry, test en enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
//
////test en disable test,clkout cycle cycle invalid
// $display("$$$$$$$$$ gated clk test en disable test...... $");
// @(posedge temp_forever_cpuclk)
// #0.1
temp_external_en = 1'b0;
temp_pad_yy_test_mode = 1'b0;
#0.1
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, test en disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, test en disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
#(`CLK_PERIOD/2)
if(temp_xor_clk !== 1'b0)
begin
$display("$ Sorry, test en disable check fail ! @_@ $",temp_xor_clk);
$finish;
end
//test en and loacal en both enabke test,clkout valid current cycle
$display("$$$$$$$$$ gated clk test en local en both enable test...... $");
@(posedge temp_forever_cpuclk)
#0.1
// temp_external_en = 1'b1;
// temp_pad_yy_test_mode = 1'b1;
// #0.1
// if(temp_xor_clk !== 1'b1)
// begin
// $display("$ Sorry, gated enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b0)
// begin
// $display("$ Sorry, gated enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b1)
// begin
// $display("$ Sorry, gated enable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
//
////test en and loacal en both disable test,clkout disable next cycle
// $display("$$$$$$$$$ gated clk test en local en both disable test...... $");
// @(posedge temp_forever_cpuclk)
// #0.1
// temp_external_en = 1'b0;
// temp_pad_yy_test_mode = 1'b0;
// #0.1
// if(temp_xor_clk !== 1'b1)
// begin
// $display("$ Sorry, gated disable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b0)
// begin
// $display("$ Sorry, gated disable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
// #(`CLK_PERIOD/2)
// if(temp_xor_clk !== 1'b0)
// begin
// $display("$ Sorry, gated disable check fail ! @_@ $",temp_xor_clk);
// $finish;
// end
icg_passed = 1'b1;
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$ gated clk test PASS!!!!!!!!!!!!!!!!!!!! $");
$display("$ gated clk test PASS!!!!!!!!!!!!!!!!!!!! $");
$display("$ gated clk test PASS!!!!!!!!!!!!!!!!!!!! $");
$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
end
`else
initial
begin
icg_passed = 1'b1;
end
`endif
endmodule |
module cpu_mmu_mem_test_tb(
mmu_mem_passed
);
output mmu_mem_passed;
reg mmu_mem_passed;
//data array parameter
//==========================================================
// Parameter Definition
//==========================================================
//---------------------------------------------------------
// MMU Configuration
//---------------------------------------------------------
`define JTLB_ENTRY_1024
//`define JTLB_ENTRY_2048
`ifdef JTLB_ENTRY_1024
`define JTLB_ADDR_WIDTH 8
`endif
`ifdef JTLB_ENTRY_2048
`define JTLB_ADDR_WIDTH 9
`endif
`ifdef L1_CACHE_ECC
parameter LOCAL_DATA_DATA_WIDTH = 88;
parameter LOCAL_TAG_DATA_WIDTH = 204;
`else
parameter LOCAL_DATA_DATA_WIDTH = 84;
parameter LOCAL_TAG_DATA_WIDTH = 196;
`endif
//data
parameter LOCAL_DATA_ADDR_WIDTH = `JTLB_ADDR_WIDTH;
parameter LOCAL_DATA_WE_WIDTH = 4;
//tag
parameter LOCAL_TAG_ADDR_WIDTH = `JTLB_ADDR_WIDTH;
parameter LOCAL_TAG_WE_WIDTH = 5;
//data array signal
reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH -1 : 0 ] temp_data_wen_internal ;
reg temp_data_cen0_internal ;
reg temp_data_cen1_internal ;
reg temp_data_CLK ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q0_internal ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q1_internal ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data0_mask ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data0_mask_ff ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data1_mask ;
//tag array signal
reg [ LOCAL_TAG_ADDR_WIDTH-1 : 0 ] temp_tag_addr_internal;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0 ] temp_tag_din_internal ;
reg [ LOCAL_TAG_WE_WIDTH -1 : 0 ] temp_tag_wen_internal ;
reg temp_tag_cen_internal ;
reg temp_tag_CLK ;
wire [ LOCAL_TAG_DATA_WIDTH-1 : 0] temp_tag_q_internal ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] golden_tag ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] tag_mask ;
reg [ LOCAL_TAG_DATA_WIDTH-1 : 0] tag_mask_ff ;
//gated cell clk
reg temp_forever_cpuclk ;
reg temp_external_en ;
reg temp_pad_yy_test_mode ;
wire temp_xor_clk ;
integer i;
initial
begin
mmu_mem_passed = 1'b0;
//memory test
temp_data_CLK = 1'b0;
temp_data_cen0_internal = 1'b1;
temp_data_cen1_internal = 1'b0;
temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
temp_data_din_internal = {LOCAL_DATA_DATA_WIDTH{1'b0}};
golden_data = {LOCAL_DATA_DATA_WIDTH{1'b0}};
data0_mask = {LOCAL_DATA_DATA_WIDTH{1'b0}};
#20
@(posedge temp_data_CLK)
//cen==1 test
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen0_internal = 1'b1;
for(i=1;i<10;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
end
@(posedge temp_data_CLK)
//cen==1 test
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen0_internal = 1'b1;
for(i=1;i<10;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q0_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$$$ data array memory cen test cen ==1 test passed $\n");
//$display("$$$$$$$$$$ data array memory cen test cen ==0 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen0_internal = 1'b0;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q0_internal === golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==1 test
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen1_internal = 1'b1;
for(i=1;i<15;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
end
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen1_internal = 1'b1;
for(i=1;i<15;i=i+1) //set address 1~9
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q1_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$$$ data array memory cen test cen ==1 test passed $\n");
//$display("$$$$$$$$$$ data array memory cen test cen ==0 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen1_internal = 1'b1;
#0.1 temp_data_cen0_internal = 1'b0;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q1_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
#0.1 temp_data_cen1_internal = 1'b0;
//wen test
//$display("$$$$$$$$$ data array memory cen test cen ==0 test passed $");
//$display("$$$$$$$$$ data array memory wen test....... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen0_internal = 1'b1;
for(i=0;i<LOCAL_DATA_WE_WIDTH/2;i=i+1)
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}} <<i ;
temp_data_din_internal <= {20{1'b1}}<<56*i;
golden_data <= {20{1'b1}}<<56*i;
@(posedge temp_data_CLK)
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
golden_data <= temp_data_din_internal ;
data0_mask_ff <= data0_mask;
@(posedge temp_data_CLK)
#0.1
// $display("$ address = %h temp_data_q0_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q0_internal,(golden_data &(~data0_mask)),temp_data_wen_internal);
if((temp_data_q0_internal & data0_mask_ff) !== (golden_data &(data0_mask_ff)) )
begin
// $display("$ Sorry, temp_data_q0_internal = %h , golden_data =%h, wen=%h \n",temp_data_q0_internal,golden_data,temp_data_wen_internal);
$finish;
end
end
//write test
//$display("$$$$$$$$$ data array memory wen test passed $");
//$display("$$$$$$$$$ data array memory write test...... $");
@(posedge temp_data_CLK) //write address 0
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen0_internal = 1'b1;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
#0.1 temp_data_cen0_internal = 1'b1;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q0_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ data array memory read test passed $");
//$display("$$$$$$$$ data array memory address width test...... $");
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen0_internal = 1'b1;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
//read data in 1/2max address
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q0_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//read data in address 0
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q0_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory address width test passed $");
//$display("$$$$$$$$ data array memory data width test...... $");
//read data check
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen0_internal = 1'b1;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
//golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q0_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q0_internal,golden_data);
if(temp_data_q0_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
temp_tag_CLK = 1'b0;
temp_tag_cen_internal = 1'b0;
temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal = {LOCAL_TAG_ADDR_WIDTH{1'b0}};
temp_tag_din_internal = {LOCAL_TAG_DATA_WIDTH{1'b0}};
golden_tag = {LOCAL_TAG_DATA_WIDTH{1'b0}};
tag_mask = {LOCAL_TAG_DATA_WIDTH{1'b0}};
#20
@(posedge temp_tag_CLK)
//cen==1 test
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$$$$$$$ tag array memory cen test cen ==1 test... $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
#0.1 temp_tag_cen_internal = 1'b1;
for(i=1;i<10;i=i+1) //set address 1~9
begin
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
#0.1 temp_tag_cen_internal = 1'b1;
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
// golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.1
//$display("$address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$ tag array memory cen test cen ==1 test passed $");
//$display("$$$$$$$$ tag array memory cen test cen ==0 test... $");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
#0.1 temp_tag_cen_internal = 1'b1;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal === golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//wen test
//$display("$$$$$$$ tag array memory cen test cen ==0 test passed $");
//$display("$$$$$$$ tag array memory wen test....... $");
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
#0.1 temp_tag_cen_internal = 1'b1;
for(i=0;i<LOCAL_TAG_WE_WIDTH + 1;i=i+1)
begin
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}} >>i ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
// golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
@(posedge temp_tag_CLK)
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
golden_tag <= temp_tag_din_internal;
tag_mask_ff <= tag_mask;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h,wen=%h \n",temp_tag_addr_internal,temp_tag_q_internal,(golden_tag &(tag_mask)),temp_tag_wen_internal);
if((temp_tag_q_internal&tag_mask_ff) !== (golden_tag &(tag_mask_ff)) )
begin
// $display("$ temp_tag_q_internal = %h , golden_tag =%h, wen=%h (golden_tag &(~tag_mask)) =%h\n",temp_tag_q_internal,golden_tag,temp_tag_wen_internal, (golden_tag &(tag_mask)));
$finish;
end
end
//write test
//$display("$$$$$$$$$ tag array memory wen test passed $");
//$display("$$$$$$$$$ tag array memory write test...... $");
@(posedge temp_tag_CLK) //write address 0
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
#0.1 temp_tag_cen_internal = 1'b1;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b1}};
#0.1 temp_tag_cen_internal = 1'b1;
@(posedge temp_tag_CLK)
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} + i;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + i;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ tag array memory read test passed $");
//$display("$$$$$$$$ tag array memory address width test...... $");
@(posedge temp_tag_CLK) //write address
#0.1 temp_tag_cen_internal = 1'b1;
//write address 0
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
//write address 1/2 max address
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal <= {{1'b1}, {LOCAL_TAG_ADDR_WIDTH-1{1'b0}} } ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
//read address 1/2 max address
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal <= {{1'b1}, {LOCAL_TAG_ADDR_WIDTH-1{1'b0}} } ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hff;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_tag_CLK)
#0.1
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//read address 0
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b0}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b0}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hff;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_tag_CLK)
#0.1
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//$display("$$$$$$$ tag array memory address width test passed $");
//$display("$$$$$$$ tag array memory data width test...... $");
//read data check
@(posedge temp_tag_CLK) //write address
#0.1 temp_tag_cen_internal = 1'b1;
@(posedge temp_tag_CLK)
temp_tag_wen_internal <= {LOCAL_TAG_WE_WIDTH{1'b1}};
temp_tag_addr_internal <= {LOCAL_TAG_ADDR_WIDTH{1'b1}} ;
temp_tag_din_internal <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
golden_tag <= {LOCAL_TAG_DATA_WIDTH{1'b1}} ;
@(posedge temp_tag_CLK)
#0.1 temp_tag_wen_internal = {LOCAL_TAG_WE_WIDTH{1'b0}};
golden_tag <= temp_tag_din_internal;
@(posedge temp_tag_CLK)
#0.1
//$display("$ address = %h temp_tag_q_internal = %h , golden_tag =%h \n",temp_tag_addr_internal,temp_tag_q_internal,golden_tag);
if(temp_tag_q_internal !== golden_tag)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_tag_addr_internal);
$finish;
end
//$display("$$$$$$$ tag array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$ tag array test passed!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
#10
mmu_mem_passed =1'b1;
end
////Dumping Control
//initial
//begin
// $fsdbDumpfile("mmu_mem.fsdb");
// $fsdbDumpon;
// $fsdbDumpvars();
// //$dumpfile("test.vcd");
// //$dumpvars;
//end
always
#(`CLK_PERIOD/2) temp_data_CLK = ~temp_data_CLK;
always
#(`CLK_PERIOD/2) temp_tag_CLK = ~temp_tag_CLK;
//always
//#(`CLK_PERIOD/2) temp_dirty_CLK = ~temp_dirty_CLK;
always
#(`CLK_PERIOD/2) temp_forever_cpuclk = ~temp_forever_cpuclk;
always @(posedge temp_data_CLK)
begin
//data array mask
data0_mask <= { {42{temp_data_wen_internal[1]}},{42{temp_data_wen_internal[0]}} };
data1_mask <= { {42{temp_data_wen_internal[3]}},{42{temp_data_wen_internal[2]}} };
//tag array mask
tag_mask <= { {4{temp_tag_wen_internal[4]}} , {48{temp_tag_wen_internal[3]}},{48{temp_tag_wen_internal[2]}},{48{temp_tag_wen_internal[1]}} ,{48{temp_tag_wen_internal[0]}}};
end
ct_mmu_jtlb_data_array x_px_mmu_da_smbist_wrap (
.jtlb_data_idx ( temp_data_addr_internal ),
.jtlb_data_cen0 ( temp_data_cen0_internal ),
.jtlb_data_cen1 ( temp_data_cen1_internal ),
.forever_cpuclk ( temp_data_CLK ),
.jtlb_data_din ( temp_data_din_internal ),
.jtlb_data_dout0 ( temp_data_q0_internal ),
.jtlb_data_dout1 ( temp_data_q1_internal ),
.jtlb_data_wen ( temp_data_wen_internal ),
// .pad_yy_gate_clk_en_b ( 1'b0 ),
.pad_yy_icg_scan_en ( 1'b1 ),
.cp0_mmu_icg_en ( 1'b1 )
);
ct_mmu_jtlb_tag_array x_px_mmu_tag_smbist_wrap (
.jtlb_tag_idx (temp_tag_addr_internal),
.jtlb_tag_cen (temp_tag_cen_internal ),
.forever_cpuclk (temp_tag_CLK ),
.jtlb_tag_din (temp_tag_din_internal ),
.jtlb_tag_dout (temp_tag_q_internal ),
.jtlb_tag_wen (temp_tag_wen_internal ),
// .pad_yy_gate_clk_en_b (1'b0 ),
.pad_yy_icg_scan_en ( 1'b1 ),
.cp0_mmu_icg_en (1'b1 )
);
endmodule |
module cpu_ifupred_mem_test_tb(
ifupred_mem_passed
);
output ifupred_mem_passed;
reg ifupred_mem_passed;
//data array parameter
//==========================================================
// Parameter Definition
//==========================================================
parameter LOCAL_DATA_ADDR_WIDTH = 16;
// `ifdef ICACHE_256K
// parameter LOCAL_DATA_ADDR_WIDTH = 15 - 3;
// `endif
// `ifdef ICACHE_128K
// parameter LOCAL_DATA_ADDR_WIDTH = 14 - 3;
// `endif
// `ifdef ICACHE_64K
// parameter LOCAL_DATA_ADDR_WIDTH = 13 - 3;
// `endif
// `ifdef ICACHE_32K
// parameter LOCAL_DATA_ADDR_WIDTH = 12 - 3;
// `endif
//data
`ifdef L1_CACHE_ECC
parameter LOCAL_DATA_DATA_WIDTH = 33;
`else
parameter LOCAL_DATA_DATA_WIDTH = 32;
`endif
parameter LOCAL_DATA_WE_WIDTH = 1;
//data array signal
reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH -1 : 0 ] temp_data_wen_internal ;
reg temp_data_CLK ;
reg temp_data_cen_internal ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask ;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff ;
//gated cell clk
reg temp_forever_cpuclk ;
reg temp_external_en ;
reg temp_pad_yy_test_mode ;
wire temp_xor_clk ;
wire [151:0] temp_cmp ;
integer i;
initial
begin
ifupred_mem_passed =1'b0;
//memory test
temp_data_CLK = 1'b0;
temp_data_cen_internal = 1'b0;
temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
temp_data_din_internal = {LOCAL_DATA_DATA_WIDTH{1'b0}};
golden_data = {LOCAL_DATA_DATA_WIDTH{1'b0}};
data_mask = {LOCAL_DATA_DATA_WIDTH{1'b0}};
#20
@(posedge temp_data_CLK)
//cen==1 test
//$display("$$$$$$$$ data array memory cen test cen ==1 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0 ;
for(i=1;i<10;i=i+1) //set address 1~9
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
// golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//cen==0 test
//$display("$$$$$$$$$$ data array memory cen test cen ==1 test passed $\n");
//$display("$$$$$$$$$$ data array memory cen test cen ==0 test... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b1;
for(i=10;i<15;i=i+1) //set address 10 ~15
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal === golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//wen test
//$display("$$$$$$$$$ data array memory cen test cen ==0 test passed $");
//$display("$$$$$$$$$ data array memory wen test....... $");
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=0;i<LOCAL_DATA_WE_WIDTH ;i=i+1)
begin
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;
//golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
data_mask_ff <= data_mask;
@(posedge temp_data_CLK)
#0.3
$display("$ address = %h temp_data_q_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q_internal,(golden_data &(~data_mask)),temp_data_wen_internal);
if(temp_data_q_internal !== (golden_data & data_mask_ff))
begin
$display("$ Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \n",temp_data_q_internal,golden_data,temp_data_wen_internal);
$finish;
end
end
//write test
//$display("$$$$$$$$$ data array memory wen test passed $");
//$display("$$$$$$$$$ data array memory write test...... $");
@(posedge temp_data_CLK) //write address 0
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
for(i=10;i<15;i = i+1) //set address 10 ~15
begin
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b0}};
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i<<3;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory write check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
end
//address width check
//$display("$$$$$$$$ data array memory read test passed $");
//$display("$$$$$$$$ data array memory address width test...... $");
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= { {7'b1},{(LOCAL_DATA_ADDR_WIDTH-7){1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
//read data in 1/2max address
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= { {20'b1},{LOCAL_DATA_ADDR_WIDTH-7{1'b0}} } ; // 1/2 max address
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//read data in address 0
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b1}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ; // 0 address write bb
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
@(posedge temp_data_CLK)
#0.1
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory address width test passed $");
//$display("$$$$$$$$ data array memory data width test...... $");
//read data check
@(posedge temp_data_CLK) //write address
#0.1 temp_data_cen_internal = 1'b0;
@(posedge temp_data_CLK)
temp_data_wen_internal <= {LOCAL_DATA_WE_WIDTH{1'b0}};
temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
temp_data_din_internal <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
golden_data <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
@(posedge temp_data_CLK)
#0.1 temp_data_wen_internal = {LOCAL_DATA_WE_WIDTH{1'b1}};
golden_data <= temp_data_din_internal ;
@(posedge temp_data_CLK)
#0.1
//$display("$ address = %h temp_data_q_internal = %h , golden_data =%h \n",temp_data_addr_internal,temp_data_q_internal,golden_data);
if(temp_data_q_internal !== golden_data)
begin
//$display("$ Sorry, address %h memory read check fail ! @_@ $",temp_data_addr_internal);
$finish;
end
//$display("$$$$$$$$ data array memory data width test passed $");
//read data check
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$ data array test PASS!!!!!!!!!!!!!!!!!!!! $");
//$display("$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$");
$display("$$$$$$$$ icache predecd mem Congratuations PASS!!!!!!!!! $");
#10
ifupred_mem_passed = 1'b1;
end
////Dumping Control
//initial
//begin
// //$display("######time:%d, Dump start######",$time);
// $fsdbDumpfile("ifupred_mem.fsdb");
// $fsdbDumpon;
// $fsdbDumpvars();
//// $dumpfile("test.vcd");
//// $dumpvars;
//end
//
always
#(`CLK_PERIOD/2) temp_data_CLK = ~temp_data_CLK;
//always
//#(`CLK_PERIOD/2) temp_dirty_CLK = ~temp_dirty_CLK;
always
#(`CLK_PERIOD/2) temp_forever_cpuclk = ~temp_forever_cpuclk;
always @(posedge temp_data_CLK)
begin
//data array mask
// data_mask <= {{32{!temp_data_wen_internal[0]}} };
data_mask <= {LOCAL_DATA_DATA_WIDTH{!temp_data_wen_internal[0]}};
//dirty array mask
//dirty_mask <={temp_dirty_wen_internal[1:0]};
end
ct_ifu_icache_predecd_array0 x_way0_smbist_wrap (
.ifu_icache_index ( temp_data_addr_internal ),
.ifu_icache_predecd_array0_cen_b ( temp_data_cen_internal ),
.ifu_icache_predecd_array0_clk_en ( 1'b1),
.forever_cpuclk ( temp_data_CLK ),
.ifu_icache_data_array0_wen_b ( temp_data_wen_internal),
.ifu_icache_predecd_array0_din ( temp_data_din_internal ),
.icache_ifu_predecd_array0_dout ( temp_data_q_internal ),
.ifu_icache_predecd_array0_wen_b ( temp_data_wen_internal ),
.cp0_ifu_icg_en ( 1'b0 ),
// .pad_yy_gate_clk_en_b ( 1'b0 ),
.pad_yy_icg_scan_en ( 1'b0 ),
.cp0_yy_clk_en (1'b1)
);
endmodule |
module RCOSC_1MHZ (
CLKOUT );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
output CLKOUT;
endmodule |
module RCOSC_25_50MHZ (
CLKOUT );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
output CLKOUT;
parameter FREQUENCY = 50.0;
endmodule |
module XTLOSC (
CLKOUT,
XTL );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
/* synthesis black_box_pad_pin ="XTL" */
output CLKOUT;
input XTL;
parameter MODE = 'h3;
parameter FREQUENCY = 20.0;
endmodule |
module RCOSC_1MHZ_FAB (
CLKOUT,
A );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
output CLKOUT;
input A;
endmodule |
module RCOSC_25_50MHZ_FAB (
CLKOUT,
A );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
output CLKOUT;
input A;
endmodule |
module XTLOSC_FAB (
CLKOUT,
A );
/* synthesis syn_black_box */
/* synthesis syn_noprune=1 */
output CLKOUT;
input A;
endmodule |
module RCOSC_1MHZ (
CLKOUT );
/* synthesis black_box */
output CLKOUT;
endmodule |
module RCOSC_25_50MHZ (
CLKOUT );
/* synthesis black_box */
output CLKOUT;
parameter FREQUENCY = 50.0;
endmodule |
module XTLOSC (
CLKOUT,
XTL );
/* synthesis black_box */
/* synthesis black_box black_box_pad ="XTL" */
output CLKOUT;
input XTL;
parameter MODE = 'h3;
parameter FREQUENCY = 20.0;
endmodule |
module RCOSC_1MHZ_FAB (
CLKOUT,
A );
/* synthesis black_box */
output CLKOUT;
input A;
endmodule |
module RCOSC_25_50MHZ_FAB (
CLKOUT,
A );
/* synthesis black_box */
output CLKOUT;
input A;
endmodule |
module XTLOSC_FAB (
CLKOUT,
A );
/* synthesis black_box */
output CLKOUT;
input A;
endmodule |
module coreresetp_pcie_hotreset (
input CLK_BASE,
input CLK_LTSSM,
input psel,
input pwrite,
input [31:0] prdata,
input sdif_core_reset_n_0,
output reg sdif_core_reset_n
);
// Parameters for state machine states
parameter IDLE = 2'b00;
parameter HOTRESET_DETECT = 2'b01;
parameter DETECT_QUIET = 2'b10;
parameter RESET_ASSERT = 2'b11;
// LTSSM state values (on prdata[30:26])
parameter LTSSM_STATE_HotReset = 5'b10100;
parameter LTSSM_STATE_DetectQuiet = 5'b00000;
parameter LTSSM_STATE_Disabled = 5'b10000;
reg no_apb_read;
reg [1:0] state;
reg hot_reset_n;
reg [6:0] count;
reg core_areset_n;
reg LTSSM_HotReset;
reg LTSSM_DetectQuiet;
reg LTSSM_Disabled;
reg LTSSM_HotReset_q;
reg LTSSM_DetectQuiet_q;
reg LTSSM_Disabled_q;
reg LTSSM_HotReset_entry_p;
reg LTSSM_DetectQuiet_entry_p;
reg LTSSM_Disabled_entry_p;
reg reset_n_q1;
reg reset_n_clk_ltssm;
reg [4:0] ltssm_q1;
reg [4:0] ltssm_q2;
reg psel_q1;
reg psel_q2;
reg pwrite_q1;
reg pwrite_q2;
reg sdif_core_reset_n_q1;
// Synchronize reset to CLK_LTSSM domain
always @(posedge CLK_LTSSM or negedge sdif_core_reset_n_0)
begin
if (!sdif_core_reset_n_0)
begin
reset_n_q1 <= 1'b0;
reset_n_clk_ltssm <= 1'b0;
end
else
begin
reset_n_q1 <= 1'b1;
reset_n_clk_ltssm <= reset_n_q1;
end
end
// Synchronize APB signals to CLK_LTSSM domain
always @(posedge CLK_LTSSM or negedge reset_n_clk_ltssm)
begin
if (!reset_n_clk_ltssm)
begin
ltssm_q1 <= 5'b0;
ltssm_q2 <= 5'b0;
psel_q1 <= 1'b0;
psel_q2 <= 1'b0;
pwrite_q1 <= 1'b0;
pwrite_q2 <= 1'b0;
end
else
begin
ltssm_q1 <= prdata[30:26];
ltssm_q2 <= ltssm_q1;
psel_q1 <= psel;
psel_q2 <= psel_q1;
pwrite_q1 <= pwrite;
pwrite_q2 <= pwrite_q1;
end
end
always @(*)
begin
if ( (psel_q2 == 1'b0) || (pwrite_q2 == 1'b1) )
begin
no_apb_read = 1'b1;
end
else
begin
no_apb_read = 1'b0;
end
end
// Create pulse signals to indicate LTSSM state transitions.
always @(posedge CLK_LTSSM or negedge reset_n_clk_ltssm)
begin
if (!reset_n_clk_ltssm)
begin
LTSSM_HotReset <= 1'b0;
LTSSM_Disabled <= 1'b0;
LTSSM_DetectQuiet <= 1'b0;
LTSSM_HotReset_q <= 1'b0;
LTSSM_Disabled_q <= 1'b0;
LTSSM_DetectQuiet_q <= 1'b0;
LTSSM_HotReset_entry_p <= 1'b0;
LTSSM_Disabled_entry_p <= 1'b0;
LTSSM_DetectQuiet_entry_p <= 1'b0;
end
else
begin
if (no_apb_read)
begin
if (ltssm_q2 == LTSSM_STATE_HotReset ) LTSSM_HotReset <= 1'b1; else LTSSM_HotReset <= 1'b0;
if (ltssm_q2 == LTSSM_STATE_Disabled ) LTSSM_Disabled <= 1'b1; else LTSSM_Disabled <= 1'b0;
if (ltssm_q2 == LTSSM_STATE_DetectQuiet) LTSSM_DetectQuiet <= 1'b1; else LTSSM_DetectQuiet <= 1'b0;
end
else
begin
LTSSM_HotReset <= 1'b0;
LTSSM_Disabled <= 1'b0;
LTSSM_DetectQuiet <= 1'b0;
end
LTSSM_HotReset_q <= LTSSM_HotReset;
LTSSM_Disabled_q <= LTSSM_Disabled;
LTSSM_DetectQuiet_q <= LTSSM_DetectQuiet;
LTSSM_HotReset_entry_p <= !LTSSM_HotReset_q & LTSSM_HotReset;
LTSSM_Disabled_entry_p <= !LTSSM_Disabled_q & LTSSM_Disabled;
LTSSM_DetectQuiet_entry_p <= !LTSSM_DetectQuiet_q & LTSSM_DetectQuiet;
end
end
//---------------------------------------------------------------------
// State machine to control SDIF hot reset.
// Tracks LTSSM in SDIF and can cause assertion of core reset to SDIF.
//---------------------------------------------------------------------
always @(posedge CLK_LTSSM or negedge reset_n_clk_ltssm)
begin
if (!reset_n_clk_ltssm)
begin
state <= IDLE;
hot_reset_n <= 1'b1;
end
else
begin
case (state)
IDLE:
begin
if (LTSSM_HotReset_entry_p | LTSSM_Disabled_entry_p)
begin
state <= HOTRESET_DETECT;
end
end
HOTRESET_DETECT:
begin
if (LTSSM_DetectQuiet_entry_p)
begin
state <= DETECT_QUIET;
hot_reset_n <= 1'b0;
end
end
DETECT_QUIET:
begin
state <= RESET_ASSERT;
end
RESET_ASSERT:
begin
if (count == 7'b1100011)
begin
state <= IDLE;
hot_reset_n <= 1'b1;
end
end
default:
begin
state <= IDLE;
hot_reset_n <= 1'b1;
end
endcase
end
end
// Counter used to ensure that the hot_reset_n signal is asserted for
// a sufficient amount of time.
always @(posedge CLK_LTSSM or negedge reset_n_clk_ltssm)
begin
if (!reset_n_clk_ltssm)
begin
count <= 7'b0000000;
end
else
begin
if (state == DETECT_QUIET)
begin
count <= 7'b0000000;
end
else
begin
if (state == RESET_ASSERT)
begin
count <= count + 1'b1;
end
end
end
end
// Async core reset signal
always @(*)
begin
core_areset_n = hot_reset_n && sdif_core_reset_n_0;
end
// Create reset signal to SDIF core.
// (Synchronize core_areset_n signal to CLK_BASE domain.)
always @(posedge CLK_BASE or negedge core_areset_n)
begin
if (!core_areset_n)
begin
sdif_core_reset_n_q1 <= 1'b0;
sdif_core_reset_n <= 1'b0;
end
else
begin
sdif_core_reset_n_q1 <= 1'b1;
sdif_core_reset_n <= sdif_core_reset_n_q1;
end
end
endmodule |
module ccc1(
// Inputs
RCOSC_25_50MHZ,
// Outputs
GL0,
LOCK
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input RCOSC_25_50MHZ;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output GL0;
output LOCK;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire GL0_net_0;
wire LOCK_net_0;
wire RCOSC_25_50MHZ;
wire GL0_net_1;
wire LOCK_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [7:2]PADDR_const_net_0;
wire [7:0]PWDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign PADDR_const_net_0 = 6'h00;
assign PWDATA_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign GL0_net_1 = GL0_net_0;
assign GL0 = GL0_net_1;
assign LOCK_net_1 = LOCK_net_0;
assign LOCK = LOCK_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------ccc1_ccc1_0_FCCC - Actel:SgCore:FCCC:2.0.201
ccc1_ccc1_0_FCCC ccc1_0(
// Inputs
.RCOSC_25_50MHZ ( RCOSC_25_50MHZ ),
// Outputs
.GL0 ( GL0_net_0 ),
.LOCK ( LOCK_net_0 )
);
endmodule |
module osc1(
// Outputs
RCOSC_25_50MHZ_CCC
);
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output RCOSC_25_50MHZ_CCC;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
wire RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0 = RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
assign RCOSC_25_50MHZ_CCC = RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------osc1_osc1_0_OSC - Actel:SgCore:OSC:2.0.101
osc1_osc1_0_OSC osc1_0(
// Inputs
.XTL ( GND_net ), // tied to 1'b0 from definition
// Outputs
.RCOSC_25_50MHZ_CCC ( RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
.RCOSC_25_50MHZ_O2F ( ),
.RCOSC_1MHZ_CCC ( ),
.RCOSC_1MHZ_O2F ( ),
.XTLOSC_CCC ( ),
.XTLOSC_O2F ( )
);
endmodule |
module ccc1_ccc1_0_FCCC(
RCOSC_25_50MHZ,
LOCK,
GL0
);
input RCOSC_25_50MHZ;
output LOCK;
output GL0;
wire gnd_net, vcc_net, GL0_net;
VCC vcc_inst (.Y(vcc_net));
GND gnd_inst (.Y(gnd_net));
CLKINT GL0_INST (.A(GL0_net), .Y(GL0));
CCC #( .INIT(210'h0000407F90000044D74000718C6318C2318C1DEC0404040403818)
, .VCOFREQUENCY(912.000) ) CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(
), .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
LOCK), .BUSY(), .CLK0(vcc_net), .CLK1(vcc_net), .CLK2(vcc_net),
.CLK3(vcc_net), .NGMUX0_SEL(gnd_net), .NGMUX1_SEL(gnd_net),
.NGMUX2_SEL(gnd_net), .NGMUX3_SEL(gnd_net), .NGMUX0_HOLD_N(
vcc_net), .NGMUX1_HOLD_N(vcc_net), .NGMUX2_HOLD_N(vcc_net),
.NGMUX3_HOLD_N(vcc_net), .NGMUX0_ARST_N(vcc_net),
.NGMUX1_ARST_N(vcc_net), .NGMUX2_ARST_N(vcc_net),
.NGMUX3_ARST_N(vcc_net), .PLL_BYPASS_N(vcc_net), .PLL_ARST_N(
vcc_net), .PLL_POWERDOWN_N(vcc_net), .GPD0_ARST_N(vcc_net),
.GPD1_ARST_N(vcc_net), .GPD2_ARST_N(vcc_net), .GPD3_ARST_N(
vcc_net), .PRESET_N(gnd_net), .PCLK(vcc_net), .PSEL(vcc_net),
.PENABLE(vcc_net), .PWRITE(vcc_net), .PADDR({vcc_net, vcc_net,
vcc_net, vcc_net, vcc_net, vcc_net}), .PWDATA({vcc_net,
vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net, vcc_net})
, .CLK0_PAD(gnd_net), .CLK1_PAD(gnd_net), .CLK2_PAD(gnd_net),
.CLK3_PAD(gnd_net), .GL0(GL0_net), .GL1(), .GL2(), .GL3(),
.RCOSC_25_50MHZ(RCOSC_25_50MHZ), .RCOSC_1MHZ(gnd_net), .XTLOSC(
gnd_net));
endmodule |
module osc1_osc1_0_OSC(
XTL,
RCOSC_25_50MHZ_CCC,
RCOSC_25_50MHZ_O2F,
RCOSC_1MHZ_CCC,
RCOSC_1MHZ_O2F,
XTLOSC_CCC,
XTLOSC_O2F
);
input XTL;
output RCOSC_25_50MHZ_CCC;
output RCOSC_25_50MHZ_O2F;
output RCOSC_1MHZ_CCC;
output RCOSC_1MHZ_O2F;
output XTLOSC_CCC;
output XTLOSC_O2F;
RCOSC_25_50MHZ #( .FREQUENCY(50.0) ) I_RCOSC_25_50MHZ (.CLKOUT(
RCOSC_25_50MHZ_CCC));
endmodule |
module corescore_ebaz4205
(
input wire i_clk,
output wire o_uart_tx);
wire clk;
wire rst;
ebaz4205_clock_gen clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_vu19p
(
input wire CLK_100MHZ_P,
input wire CLK_100MHZ_N,
output wire UART_TXD);
wire i_clk;
wire clk;
wire rst;
IBUFGDS ibufds(
.I (CLK_100MHZ_P),
.IB(CLK_100MHZ_N),
.O (i_clk));
corescore_vu19p_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (UART_TXD));
endmodule |
module axis2wb
(
input wire i_clk,
input wire i_rst,
input wire [0:0] i_wb_sel,
input wire i_wb_stb,
output wire [9:0] o_wb_rdt,
output reg o_wb_ack,
input wire [7:0] i_tdata,
input wire i_tlast,
input wire i_tvalid,
output wire o_tready);
always @(posedge i_clk) begin
o_wb_ack <= i_wb_stb & !o_wb_ack;
if (i_rst)
o_wb_ack <= 1'b0;
end
assign o_tready = i_wb_sel[0] & o_wb_ack;
assign o_wb_rdt = {i_tvalid, i_tlast, i_tdata};
endmodule |
module de5_net_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output wire o_rst
);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk) begin
if (locked)
r <= {r[8:0], 1'b0};
else
r <= 10'b1111111111;
end
wire clk;
assign o_clk = clk;
altera_pll #(
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.output_clock_frequency0("16.000000 MHz")
) altera_pll_i (
.rst(i_rst),
.outclk({clk}),
.locked(locked),
.fboutclk(),
.fbclk(1'b0),
.refclk(i_clk)
);
endmodule |
module corescore_genesys2
(
input wire i_clk_p,
input wire i_clk_n,
output wire o_uart_tx);
wire i_clk;
wire clk;
wire rst;
IBUFDS ibufds
(.I (i_clk_p),
.IB (i_clk_n),
.O (i_clk));
genesys2_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_alhambra_II
(
input i_clk,
output wire locked_led,
output wire o_uart_tx);
wire clk;
wire locked;
//Mirror locked PLL to LED
assign locked_led = locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll48
(.clock_in (i_clk),
.clock_out (clk),
.locked (locked));
reg rst = 1'b1;
always @(posedge clk)
rst <= !locked;
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_deca
(
input wire i_clk,
input wire i_rst_n,
output wire q,
output wire uart_txd);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = uart_txd;
de0_nano_clock_gen clock_gen
(.i_clk (i_clk),
.i_rst (!i_rst_n),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (uart_txd));
endmodule |
module arty_a7_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE"))
PLLE2_BASE_inst
(.CLKOUT0(o_clk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_ulx3s
(input wire i_clk,
input wire btn0,
output wire wifi_gpio0,
output wire o_uart_tx,
output wire q);
wire clk;
wire rst;
assign q = o_uart_tx;
assign wifi_gpio0 = btn0;
corescore_ulx3s_clock_gen clock_gen
(.i_clk (i_clk),
.i_rst (!btn0),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_generic
(
input wire i_clk,
input wire i_rst,
output wire o_uart_tx);
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (i_clk),
.i_rst (i_rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (i_clk),
.i_rst (i_rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module emitter_mux
(
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_cpu_adr,
input wire [31:0] i_wb_cpu_dat,
input wire [3:0] i_wb_cpu_sel,
input wire i_wb_cpu_we,
input wire i_wb_cpu_cyc,
output wire [31:0] o_wb_cpu_rdt,
output wire o_wb_cpu_ack,
//RW
output wire [31:0] o_wb_mem_adr,
output wire [31:0] o_wb_mem_dat,
output wire [3:0] o_wb_mem_sel,
output wire o_wb_mem_we,
output wire o_wb_mem_cyc,
input wire [31:0] i_wb_mem_rdt,
//W
output wire o_wb_gpio_dat,
output wire o_wb_gpio_cyc,
//RW
output wire [31:0] o_wb_timer_dat,
output wire o_wb_timer_we,
output wire o_wb_timer_cyc,
input wire [31:0] i_wb_timer_rdt,
//R
output wire [0:0] o_wb_fifo_sel,
output wire o_wb_fifo_stb,
input wire [9:0] i_wb_fifo_rdt,
input wire i_wb_fifo_ack);
parameter sim = 0;
reg ack;
wire [1:0] s = i_wb_cpu_adr[31:30];
assign o_wb_cpu_rdt = !s[1] ? i_wb_mem_rdt :
s[0] ? {22'd0, i_wb_fifo_rdt} :
i_wb_timer_rdt;
assign o_wb_cpu_ack = (s == 2'b11) ? i_wb_fifo_ack : ack;
always @(posedge i_clk) begin
ack <= 1'b0;
if (i_wb_cpu_cyc & (s != 2'b11) & !ack)
ack <= 1'b1;
if (i_rst)
ack <= 1'b0;
end
assign o_wb_mem_adr = i_wb_cpu_adr;
assign o_wb_mem_dat = i_wb_cpu_dat;
assign o_wb_mem_sel = i_wb_cpu_sel;
assign o_wb_mem_we = i_wb_cpu_we;
assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
assign o_wb_gpio_dat = i_wb_cpu_dat[0];
assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
assign o_wb_timer_dat = i_wb_cpu_dat;
assign o_wb_timer_we = i_wb_cpu_we;
assign o_wb_timer_cyc = i_wb_cpu_cyc & (s == 2'b10);
assign o_wb_fifo_sel = i_wb_cpu_sel[0];
assign o_wb_fifo_stb = i_wb_cpu_cyc & (s == 2'b11);
generate
if (sim) begin
wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
always @(posedge i_clk)
if(halt_en) begin
$display("Finito");
$finish;
end
end
endgenerate
endmodule |
module corescore_haps_dx7_clock_gen
(input wire i_clk,
output wire o_clk,
output wire o_rst);
wire clkfb;
wire locked;
reg locked_r;
reg rst = 1'b1;
assign o_rst = rst;
MMCME2_ADV
#(.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (30.000),
.CLKOUT0_DIVIDE_F (50.0),
.CLKIN1_PERIOD (7.5001875), //133.33 MHz
.STARTUP_WAIT ("FALSE"))
mmcm
(.CLKFBOUT (clkfb),
.CLKFBOUTB (),
.CLKOUT0 (o_clk),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKIN1 (i_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (1'b0),
.CLKFBIN (clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
if (locked_r) begin
rst <= 1'b0;
end else begin
rst <= rst;
end
end
endmodule |
module emitter_uart
#(parameter clk_freq_hz = 16_000_000,
parameter baud_rate = 57600)
(input wire i_clk,
input wire i_rst,
input wire [7:0] i_tdata,
input wire i_tvalid,
output reg o_tready,
output wire o_uart_tx);
localparam START_VALUE = clk_freq_hz/baud_rate;
localparam WIDTH = $clog2(START_VALUE);
reg [WIDTH:0] cnt;
reg [9:0] data;
assign o_uart_tx = data[0] | !(|data);
always @(posedge i_clk) begin
if (cnt[WIDTH] & !(|data))
o_tready <= 1'b1;
else if (i_tvalid & o_tready)
o_tready <= 1'b0;
if (o_tready | cnt[WIDTH])
cnt <= {1'b0,START_VALUE[WIDTH-1:0]};
else
cnt <= cnt-1;
if (cnt[WIDTH])
data <= {1'b0, data[9:1]};
else if (i_tvalid & o_tready)
data <= {1'b1, i_tdata, 1'b0};
end
endmodule |
module wb2axis
(
input wire i_clk,
input wire i_rst,
input wire [8:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_stb,
output reg o_wb_ack,
output wire [7:0] o_tdata,
output wire o_tlast,
output wire o_tvalid,
input wire i_tready);
always @(posedge i_clk) begin
o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack;
if (i_rst)
o_wb_ack <= 1'b0;
end
assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack;
assign o_tdata = i_wb_dat[7:0];
assign o_tlast = i_wb_dat[8];
endmodule |
module corescore_icesugar
(
output wire g,
output wire b,
output wire r,
output wire o_uart_tx);
wire clk48;
wire clk;
wire locked;
SB_HFOSC inthosc
(
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF(clk48));
SB_PLL40_CORE
#(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0010),
.DIVF(7'b0111111),
.DIVQ(3'b110),
.FILTER_RANGE(3'b001))
pll
(.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clk48),
.PLLOUTCORE(clk));
SB_RGBA_DRV
#(
.CURRENT_MODE ("0b1"),
.RGB0_CURRENT ("0b000111"),
.RGB1_CURRENT ("0b000111"),
.RGB2_CURRENT ("0b000111"))
RGBA_DRIVER
(
.CURREN(1'b1),
.RGBLEDEN(1'b1),
.RGB0PWM(o_uart_tx),
.RGB1PWM(o_uart_tx),
.RGB2PWM(o_uart_tx),
.RGB0(g),
.RGB1(b),
.RGB2(r));
reg rst = 1'b1;
always @(posedge clk)
rst <= !locked;
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_max1000
(
input wire CLK12M,
output wire q,
output wire o_uart_tx);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
max1000_clock_gen clock_gen
(.i_clk (CLK12M),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_ep2c5t144_devboard
(
input wire clk50,
output wire led0,
output wire uart_txd);
wire clk;
wire rst;
//Mirror UART output to LED
assign led0 = uart_txd;
ep2c5t144_clock_gen clock_gen
(.i_clk (clk50),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (uart_txd));
endmodule |
module corescore_intel_a10gx_devkit
(
input wire rstn,
input wire clk50
);
wire clk;
wire rst;
wire [7:0] tdata;
wire tlast;
wire tvalid;
reg tready;
reg [7:0] r_dat;
wire r_ena;
// ================================================================
// Generate 16MHz from 50MHz board Clock
// ================================================================
intel_a10gx_devkit_clock_gen clock_gen
(
.i_rst (~rstn),
.i_clk (clk50),
.o_clk (clk),
.o_rst (rst)
);
// ================================================================
// CPU Magic Inside
// ================================================================
corescorecore corescorecore
(
.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready)
);
// ================================================================
// Pipeline response as UART expects 1 clk delay after r_ena goes active
// before you can push characters into it.
// ================================================================
always @(posedge clk) begin
if (tvalid & r_ena) begin
tready <= 1'b1;
r_dat <= tdata;
end else begin
tready <= 1'b0;
end
end
// ================================================================
// Instantiate the internal JTAG-UART interface as the GX Devkit has no UART pins.
//
// NOTE - UART will stall indefinety when its tx-fifo is full,
// so you must run nios-terminal.exe to allow things to flow
// ================================================================
alt_jtag_atlantic #(
.INSTANCE_ID(0),
.LOG2_RXFIFO_DEPTH(6),
.LOG2_TXFIFO_DEPTH(6),
.SLD_AUTO_INSTANCE_INDEX("YES")
) i_uart (
.clk (clk),
.rst_n (~rst),
.r_dat (r_dat),
.r_ena (r_ena),
.r_val (tready),
// Not interested in RX
.t_dat (),
.t_dav (1'b1),
.t_ena (),
.t_pause()
);
endmodule |
module corescore_de5_net (
input wire i_clk,
input wire i_rst_n,
output wire o_led_n,
output wire o_hex0_dp_n,
output wire o_hex1_dp_n,
output wire o_uart_txd,
output wire o_rs422_de,
output wire o_rs422_re_n,
output wire o_rs422_te
);
wire clk;
wire rst;
// Mirror UART output to LED and decimal point on 7-seg
assign o_led_n = ~o_uart_txd;
assign o_hex0_dp_n = o_uart_txd;
assign o_hex1_dp_n = ~o_uart_txd;
de5_net_clock_gen clock_gen
(.i_clk (i_clk),
.i_rst (!i_rst_n),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_txd));
assign o_rs422_de = 1'b1; // Driver enable
assign o_rs422_re_n = 1'b1; // Receiver disabled
assign o_rs422_te = 1'b0; // Disable RS-485 termination
endmodule |
module corescore_cisco_hwic_3g_cdma
(
input wire clk25,
output wire led0,
output wire uart_txd,
output wire uart_drv_ena_,
output wire uart_drv_sd_);
wire clk;
wire rst;
//Mirror UART output to LED
assign led0 = uart_txd;
assign uart_drv_ena_ = 1'b0; // ADM3222 EN_: Set 0 to enable RX
assign uart_drv_sd_ = 1'b1; // ADM3222 SD_: Set 1 to enabel TX
cisco_hwic_3g_cdma_clock_gen clock_gen
(.i_clk (clk25),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (uart_txd));
endmodule |
module genesys2_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(4),
.CLKIN1_PERIOD(5.0), //200MHz
.CLKOUT0_DIVIDE(50),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE"))
PLLE2_BASE_inst
(.CLKOUT0(o_clk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_tinyfpga_bx
(input wire i_clk,
inout wire pin_usb_p,
inout wire pin_usb_n,
output wire pin_pu);
wire clk;
wire clk_locked;
// USB Host Detect Pull Up
assign pin_pu = 1'b1;
pll pll48
(.clock_in (i_clk),
.clock_out (clk),
.locked (clk_locked));
// Generate reset signal
reg [5:0] reset_cnt = 0;
wire reset = ~reset_cnt[5];
always @(posedge clk)
if ( clk_locked )
reset_cnt <= reset_cnt + reset;
reg rst;
reg rst_r;
always @(posedge i_clk) begin
rst_r <= reset;
rst <= rst_r;
end
wire [7:0] tdata;
wire tvalid;
wire tready;
wire [7:0] usb_tdata;
wire usb_tvalid;
wire usb_tready;
corescorecore corescorecore
(.i_clk (i_clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (),
.o_tvalid (tvalid),
.i_tready (tready));
axis_async_fifo
#(
.DEPTH(4),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.KEEP_WIDTH(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.ID_WIDTH(0),
.DEST_ENABLE(0),
.DEST_WIDTH(0),
.USER_ENABLE(0),
.USER_WIDTH(0),
.FRAME_FIFO(0),
.USER_BAD_FRAME_VALUE(0),
.USER_BAD_FRAME_MASK(0),
.DROP_BAD_FRAME(0),
.DROP_WHEN_FULL(0))
UUT
(// Common reset
.async_rst (rst),
// AXI input
.s_clk(i_clk),
.s_axis_tdata(tdata),
.s_axis_tkeep(),
.s_axis_tvalid(tvalid),
.s_axis_tready(tready),
.s_axis_tlast(),
.s_axis_tid(),
.s_axis_tdest(),
.s_axis_tuser(),
// AXI output
.m_clk(clk),
.m_axis_tdata (usb_tdata),
.m_axis_tkeep (),
.m_axis_tvalid (usb_tvalid),
.m_axis_tready (usb_tready),
.m_axis_tlast (),
.m_axis_tid (),
.m_axis_tdest (),
.m_axis_tuser (),
// Status
.s_status_overflow (),
.s_status_bad_frame (),
.s_status_good_frame (),
.m_status_overflow (),
.m_status_bad_frame (),
.m_status_good_frame ());
wire usb_p_tx;
wire usb_n_tx;
wire usb_p_rx;
wire usb_n_rx;
wire usb_tx_en;
usb_uart_core uart
(
.clk_48mhz (clk),
.reset (reset),
// pins - these must be connected properly to the outside world. See below.
.usb_p_tx (usb_p_tx),
.usb_n_tx (usb_n_tx),
.usb_p_rx (usb_p_rx),
.usb_n_rx (usb_n_rx),
.usb_tx_en (usb_tx_en),
// uart pipeline in
.uart_in_data (usb_tdata),
.uart_in_valid (usb_tvalid),
.uart_in_ready (usb_tready),
// uart pipeline out
.uart_out_data (),
.uart_out_valid (/*tvalid*/),
.uart_out_ready (tready),
.debug ());
wire usb_p_in;
wire usb_n_in;
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_in;
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_in;
SB_IO
#(.PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT
.PULLUP(1'b 0))
iobuf_usbp
(.PACKAGE_PIN (pin_usb_p),
.OUTPUT_ENABLE (usb_tx_en),
.D_OUT_0 (usb_p_tx),
.D_IN_0 (usb_p_in));
SB_IO #(
.PIN_TYPE(6'b 1010_01), // PIN_OUTPUT_TRISTATE - PIN_INPUT
.PULLUP(1'b 0)
) iobuf_usbn (
.PACKAGE_PIN(pin_usb_n),
.OUTPUT_ENABLE(usb_tx_en),
.D_OUT_0(usb_n_tx),
.D_IN_0(usb_n_in)
);
endmodule |
module corescore_hx8k
(
input i_clk,
output wire o_uart_tx);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll12
(.clock_in (i_clk),
.clock_out (clk),
.locked (locked));
reg rst = 1'b1;
always @(posedge clk)
rst <= !locked;
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_haps_dx7
(
input wire i_clk_in,
output wire o_clk_en,
output wire q,
output wire o_uart_tx);
wire i_clk;
wire clk;
wire rst;
//Enable clock input
assign o_clk_en = 1'b1;
//Mirror UART output to LED
assign q = o_uart_tx;
IBUF ibuf
(.I (i_clk_in),
.O (i_clk));
corescore_haps_dx7_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_marble (
input wire i_clk_p,
input wire i_clk_n,
output wire o_uart_tx,
output wire o_uart_tx2,
input wire i_uart_rx
);
assign o_uart_tx2 = o_uart_tx;
wire main_crg_clkin, main_crg_clkout0;
IBUFDS IBUFDS(
.I(i_clk_p),
.IB(i_clk_n),
.O(main_crg_clkin)
);
// Create a 100 MHz clock using MMCME
// baudrate = 57600 * 100 / 16 = 360000 baud / s
wire builder_mmcm_fb;
wire locked;
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(11),
.CLKIN1_PERIOD(8.0),
.CLKOUT0_DIVIDE_F(13.75),
.CLKOUT0_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01)
) MMCME2_ADV (
.CLKFBIN(builder_mmcm_fb),
.CLKIN1(main_crg_clkin),
.PWRDWN(0),
.RST(),
.CLKFBOUT(builder_mmcm_fb),
.CLKOUT0(main_crg_clkout0),
.LOCKED(locked)
);
wire clk;
reg rst = 1;
reg locked_r = 0;
BUFG BUFG(
.I(main_crg_clkout0),
.O(clk)
);
always @(posedge clk) begin
locked_r <= locked;
rst <= !locked_r;
end
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module ep2c5t144_clock_gen
(input wire i_clk,
output wire o_clk,
output wire o_rst);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked)
r <= {r[8:0],1'b0};
else
r <= 10'b1111111111;
altpll altpll_component (
.inclk (i_clk),
.clk (o_clk),
.locked (locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 50,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule |
module corescore_kc705_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(8),
.CLKIN1_PERIOD(5.0), //200MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE"))
PLLE2_BASE_inst
(.CLKOUT0(o_clk), // 16MHz
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_polarfire
(
input wire i_clk,
input wire resetbtn,
output wire q,
output reg h,
output wire o_uart_tx);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
assign rst = ~resetbtn;
PF_CCC_C0_PF_CCC_C0_0_PF_CCC clock_gen
(.REF_CLK_0 (i_clk),
.OUT0_FABCLK_0 (clk));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
// Heartbeat led
reg [$clog2(16000000)-1:0] count = 0;
always @(posedge clk) begin
if (rst) begin
count <= 0;
h <= 0;
end else
count <= count + 1;
if (count == 16000000-1) begin
h <= !h;
count <= 0;
end
end
endmodule |
module corescore_vu19p_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
MMCME4_ADV
#(.DIVCLK_DIVIDE (4),
.CLKFBOUT_MULT_F (32.000),
.CLKOUT0_DIVIDE_F (50.0),
.CLKIN1_PERIOD (10.0), //100MHz
.STARTUP_WAIT ("FALSE"))
mmcm
(.CLKFBOUT (clkfb),
.CLKFBOUTB (),
.CLKOUT0 (o_clk), // 16MHz
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN1 (i_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (1'b0),
.CLKFBIN (clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_icebreaker
(
input i_clk,
output wire o_uart_tx);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
SB_PLL40_PAD
#(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000),
.DIVF(7'b1010100),
.DIVQ(3'b110),
.FILTER_RANGE(3'b001))
pll
(.LOCK(locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.PACKAGEPIN(i_clk),
.PLLOUTCORE(clk));
reg rst = 1'b1;
always @(posedge clk)
rst <= !locked;
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_nexys_video
(
input wire i_clk,
output wire o_uart_tx);
wire clk;
wire rst;
nexys_video_clock_gen clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module intel_a10gx_devkit_clock_gen
(
input wire i_rst,
input wire i_clk,
output wire o_clk,
output wire o_rst);
wire locked;
wire [7:0] unused_wires;
assign o_rst = ~locked;
altera_iopll #(
.c_cnt_bypass_en0("false"),
.c_cnt_bypass_en1("true"),
.c_cnt_bypass_en2("true"),
.c_cnt_bypass_en3("true"),
.c_cnt_bypass_en4("true"),
.c_cnt_bypass_en5("true"),
.c_cnt_bypass_en6("true"),
.c_cnt_bypass_en7("true"),
.c_cnt_bypass_en8("true"),
.c_cnt_hi_div0(25),
.c_cnt_hi_div1(256),
.c_cnt_hi_div2(256),
.c_cnt_hi_div3(256),
.c_cnt_hi_div4(256),
.c_cnt_hi_div5(256),
.c_cnt_hi_div6(256),
.c_cnt_hi_div7(256),
.c_cnt_hi_div8(256),
.c_cnt_in_src0("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src1("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src2("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src3("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src4("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src5("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src6("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src7("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_in_src8("c_m_cnt_in_src_ph_mux_clk"),
.c_cnt_lo_div0(25),
.c_cnt_lo_div1(256),
.c_cnt_lo_div2(256),
.c_cnt_lo_div3(256),
.c_cnt_lo_div4(256),
.c_cnt_lo_div5(256),
.c_cnt_lo_div6(256),
.c_cnt_lo_div7(256),
.c_cnt_lo_div8(256),
.c_cnt_odd_div_duty_en0("false"),
.c_cnt_odd_div_duty_en1("false"),
.c_cnt_odd_div_duty_en2("false"),
.c_cnt_odd_div_duty_en3("false"),
.c_cnt_odd_div_duty_en4("false"),
.c_cnt_odd_div_duty_en5("false"),
.c_cnt_odd_div_duty_en6("false"),
.c_cnt_odd_div_duty_en7("false"),
.c_cnt_odd_div_duty_en8("false"),
.c_cnt_ph_mux_prst0(0),
.c_cnt_ph_mux_prst1(0),
.c_cnt_ph_mux_prst2(0),
.c_cnt_ph_mux_prst3(0),
.c_cnt_ph_mux_prst4(0),
.c_cnt_ph_mux_prst5(0),
.c_cnt_ph_mux_prst6(0),
.c_cnt_ph_mux_prst7(0),
.c_cnt_ph_mux_prst8(0),
.c_cnt_prst0(1),
.c_cnt_prst1(1),
.c_cnt_prst2(1),
.c_cnt_prst3(1),
.c_cnt_prst4(1),
.c_cnt_prst5(1),
.c_cnt_prst6(1),
.c_cnt_prst7(1),
.c_cnt_prst8(1),
.clock_name_0("outclk0"),
.clock_name_1(""),
.clock_name_2(""),
.clock_name_3(""),
.clock_name_4(""),
.clock_name_5(""),
.clock_name_6(""),
.clock_name_7(""),
.clock_name_8(""),
.clock_name_global_0("false"),
.clock_name_global_1("false"),
.clock_name_global_2("false"),
.clock_name_global_3("false"),
.clock_name_global_4("false"),
.clock_name_global_5("false"),
.clock_name_global_6("false"),
.clock_name_global_7("false"),
.clock_name_global_8("false"),
.duty_cycle0(50),
.duty_cycle1(50),
.duty_cycle2(50),
.duty_cycle3(50),
.duty_cycle4(50),
.duty_cycle5(50),
.duty_cycle6(50),
.duty_cycle7(50),
.duty_cycle8(50),
.m_cnt_bypass_en("false"),
.m_cnt_hi_div(8),
.m_cnt_lo_div(8),
.m_cnt_odd_div_duty_en("false"),
.n_cnt_bypass_en("true"),
.n_cnt_hi_div(256),
.n_cnt_lo_div(256),
.n_cnt_odd_div_duty_en("false"),
.number_of_clocks(1),
.operation_mode("direct"),
.output_clock_frequency0("16.0 MHz"),
.output_clock_frequency1("0 ps"),
.output_clock_frequency2("0 ps"),
.output_clock_frequency3("0 ps"),
.output_clock_frequency4("0 ps"),
.output_clock_frequency5("0 ps"),
.output_clock_frequency6("0 ps"),
.output_clock_frequency7("0 ps"),
.output_clock_frequency8("0 ps"),
.phase_shift0("0 ps"),
.phase_shift1("0 ps"),
.phase_shift2("0 ps"),
.phase_shift3("0 ps"),
.phase_shift4("0 ps"),
.phase_shift5("0 ps"),
.phase_shift6("0 ps"),
.phase_shift7("0 ps"),
.phase_shift8("0 ps"),
.pll_bw_sel("Low"),
.pll_bwctrl("pll_bw_res_setting3"),
.pll_cp_current("pll_cp_setting10"),
.pll_extclk_0_cnt_src("pll_extclk_cnt_src_vss"),
.pll_extclk_1_cnt_src("pll_extclk_cnt_src_vss"),
.pll_fbclk_mux_1("pll_fbclk_mux_1_glb"),
.pll_fbclk_mux_2("pll_fbclk_mux_2_m_cnt"),
.pll_m_cnt_in_src("c_m_cnt_in_src_ph_mux_clk"),
.pll_output_clk_frequency("800.0 MHz"),
.pll_slf_rst("true"),
.pll_subtype("General"),
.pll_type("Arria 10"),
.prot_mode("BASIC"),
.reference_clock_frequency("50.0 MHz")
) altera_iopll_i (
.refclk1 (1'b0),
.rst (i_rst),
.fbclk (1'b0),
.fboutclk ( ),
.zdbfbclk ( ),
.locked (locked),
.loaden ( ),
.phase_done ( ),
.reconfig_to_pll (64'b0),
.refclk (i_clk),
.scanclk (1'b0),
.phout ( ),
.num_phase_shifts (3'b0),
.cntsel (5'b0),
.clkbad ( ),
.extclk_out ( ),
.lvds_clk ( ),
.outclk ({o_clk}),
.phase_en (1'b0),
.extswitch (1'b0),
.cascade_out ( ),
.activeclk ( ),
.adjpllin (1'b0),
.updn (1'b0),
.reconfig_from_pll ( )
);
endmodule |
module corescore_icestick
(
input i_clk,
output wire o_uart_tx);
wire clk;
wire locked;
//Create a 16MHz clock from 12MHz using PLL
pll pll12
(.clock_in (i_clk),
.clock_out (clk),
.locked (locked));
reg rst = 1'b1;
always @(posedge clk)
rst <= !locked;
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter_uart emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_nexys_a7
(
input wire i_clk,
output wire o_uart_tx);
wire clk;
wire rst;
nexys_a7_clock_gen clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_zcu106
(
input wire i_clk_p,
input wire i_clk_n,
output wire q,
output wire o_uart_tx);
wire i_clk;
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
IBUFDS ibufds
(.I (i_clk_p),
.IB (i_clk_n),
.O (i_clk));
corescore_zcu106_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_vcu118
(
input wire i_clk_p,
input wire i_clk_n,
output wire q,
output wire o_uart_tx);
wire i_clk;
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
IBUFDS ibufds
(.I (i_clk_p),
.IB (i_clk_n),
.O (i_clk));
corescore_vcu118_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module hpc_k7_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKOUT0_DIVIDE(12.5),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE"))
PLLE2_BASE_inst
(.CLKOUT0(o_clk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_hpc_ku
(
input wire i_clk,
output wire o_uart_tx);
wire clk;
wire rst;
hpc_ku_clock_gen clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module storeypeak_clock_gen
(input wire i_clk,
output wire o_clk,
output wire o_rst);
wire clk_fb;
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked)
r <= {r[8:0],1'b0};
else
r <= 10'b1111111111;
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("125.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("16.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (1'b0),
.outclk ({o_clk}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (i_clk)
);
endmodule |
module ebaz4205_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE
#(.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(48),
.CLKIN1_PERIOD(30.000300003), // 33.333 MHz
.CLKOUT0_DIVIDE(100),
.DIVCLK_DIVIDE(1),
.STARTUP_WAIT("FALSE"))
PLLE2_BASE_inst
(.CLKOUT0(o_clk),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(clkfb),
.LOCKED(locked),
.CLKIN1(i_clk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clkfb));
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module corescore_arty_a7
(
input wire i_clk,
output wire q,
output wire o_uart_tx);
wire clk;
wire rst;
//Mirror UART output to LED
assign q = o_uart_tx;
arty_a7_clock_gen clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter_uart emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_vcu128
(
input wire QDR4_CLK_100MHZ_P,
input wire QDR4_CLK_100MHZ_N,
output wire GPIO_LED_0_LS,
output wire UART1_TXD);
wire i_clk;
wire clk;
wire rst;
//Mirror UART output to LED
assign GPIO_LED_0_LS = UART1_TXD;
IBUFGDS ibufds(
.I (QDR4_CLK_100MHZ_P),
.IB(QDR4_CLK_100MHZ_N),
.O (i_clk));
corescore_vcu128_clock_gen
clock_gen
(.i_clk (i_clk),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (UART1_TXD));
endmodule |
module corescore_xyloni
(
input wire i_clk,
input wire i_pll_locked,
output wire q,
output wire o_uart_tx);
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
reg pll_locked_r;
reg rst;
assign q = o_uart_tx;
always @(posedge i_clk) begin
pll_locked_r <= i_pll_locked;
rst <= ~pll_locked_r;
end
corescorecore corescorecore
(.i_clk (i_clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter_uart emitter
(.i_clk (i_clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (o_uart_tx));
endmodule |
module corescore_fpc_iii_clock_gen( input i_clk, output o_clk, output o_rst );
wire locked;
reg[ 1:0 ] rst_reg;
always @( posedge o_clk )
rst_reg <= { !locked, rst_reg[ 1 ] };
assign o_rst = rst_reg[ 0 ];
pll pll( .clki( i_clk ), .clko( o_clk ), .locked( locked ) );
endmodule |
module corescore_intel_cyc10lp_devkit
(
input wire clk50,
output wire uart_txd);
wire clk;
wire rst;
intel_cyc10lp_devkit_clock_gen clock_gen
(.i_clk (clk50),
.o_clk (clk),
.o_rst (rst));
parameter memfile_emitter = "emitter.hex";
wire [7:0] tdata;
wire tlast;
wire tvalid;
wire tready;
corescorecore corescorecore
(.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready));
emitter #(.memfile (memfile_emitter)) emitter
(.i_clk (clk),
.i_rst (rst),
.i_tdata (tdata),
.i_tlast (tlast),
.i_tvalid (tvalid),
.o_tready (tready),
.o_uart_tx (uart_txd));
endmodule |
module corescore_intel_agilex7
(
// input wire rstn,
input wire i_clk,
input wire i_rstn
);
wire clk;
wire rst;
wire [7:0] tdata;
wire tlast;
wire tvalid;
reg tready;
reg [7:0] r_dat;
wire r_ena;
wire ninit_done;
wire locked;
reg rst_reg1;
reg rst_reg2;
assign rst = rst_reg2;
// ================================================================
// CPU Magic Inside
// ================================================================
corescorecore corescorecore
(
.i_clk (clk),
.i_rst (rst),
.o_tdata (tdata),
.o_tlast (tlast),
.o_tvalid (tvalid),
.i_tready (tready)
);
// ================================================================
// Synchronize Reset
// ================================================================
always @(posedge clk) begin
if (!locked || !i_rstn) begin
rst_reg1 <= 1'b1;
rst_reg2 <= 1'b1;
end else begin
rst_reg1 <= 1'b0;
rst_reg2 <= rst_reg1;
end
end
// ================================================================
// Agilex Reset Release
// ================================================================
altera_agilex_config_reset_release_endpoint config_reset_release_endpoint(
.conf_reset(ninit_done)
);
// ================================================================
// Basic Intel Parameterizable Macro for IOPLL
// ================================================================
ipm_iopll_basic #(
.REFERENCE_CLOCK_FREQUENCY ("100.0 MHz"),
.N_CNT (1),
.M_CNT (8),
.C0_CNT (50),
.C1_CNT (1),
.C2_CNT (1),
.C3_CNT (1),
.C4_CNT (1),
.C5_CNT (1),
.C6_CNT (1)
) core_pll (
.refclk (i_clk), //input, width = 1
.reset (ninit_done), //input, width = 1
.outclk0 (clk), //output, width = 1
.outclk1 (), //output, width = 1
.outclk2 (), //output, width = 1
.outclk3 (), //output, width = 1
.outclk4 (), //output, width = 1
.outclk5 (), //output, width = 1
.outclk6 (), //output, width = 1
.locked (locked) //output, width = 1
);
// ================================================================
// Pipeline response as UART expects 1 clk delay after r_ena goes active
// before you can push characters into it.
// ================================================================
always @(posedge clk) begin
if (tvalid & r_ena) begin
tready <= 1'b1;
r_dat <= tdata;
end else begin
tready <= 1'b0;
end
end
// ================================================================
// Instantiate the internal JTAG-UART interface as the GX Devkit has no UART pins.
//
// NOTE - UART will stall indefinety when its tx-fifo is full,
// so you must run nios-terminal.exe to allow things to flow
// ================================================================
alt_jtag_atlantic #(
.INSTANCE_ID(0),
.LOG2_RXFIFO_DEPTH(6),
.LOG2_TXFIFO_DEPTH(6),
.SLD_AUTO_INSTANCE_INDEX("YES")
) i_uart (
.clk (clk),
.rst_n (~rst),
.r_dat (r_dat),
.r_ena (r_ena),
.r_val (tready),
// Not interested in RX
.t_dat (),
.t_dav (1'b1),
.t_ena (),
.t_pause()
);
endmodule |
module emitter
(input wire i_clk,
input wire i_rst,
input wire [7:0] i_tdata,
input wire i_tlast,
input wire i_tvalid,
output wire o_tready,
output wire o_uart_tx);
parameter memfile = "";
parameter memsize = 256;
parameter sim = 0;
wire [31:0] wb_ibus_adr;
wire wb_ibus_cyc;
wire [31:0] wb_ibus_rdt;
wire wb_ibus_ack;
wire [31:0] wb_dbus_adr;
wire [31:0] wb_dbus_dat;
wire [3:0] wb_dbus_sel;
wire wb_dbus_we;
wire wb_dbus_cyc;
wire [31:0] wb_dbus_rdt;
wire wb_dbus_ack;
wire [31:0] wb_dmem_adr;
wire [31:0] wb_dmem_dat;
wire [3:0] wb_dmem_sel;
wire wb_dmem_we;
wire wb_dmem_cyc;
wire [31:0] wb_dmem_rdt;
wire wb_dmem_ack;
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
wire wb_mem_we;
wire wb_mem_cyc;
wire [31:0] wb_mem_rdt;
wire wb_mem_ack;
wire wb_gpio_dat;
wire wb_gpio_cyc;
// wire wb_gpio_rdt;
wire [0:0] wb_fifo_sel;
wire wb_fifo_stb;
wire [9:0] wb_fifo_rdt;
wire wb_fifo_ack;
servant_arbiter arbiter
(.i_wb_cpu_dbus_adr (wb_dmem_adr),
.i_wb_cpu_dbus_dat (wb_dmem_dat),
.i_wb_cpu_dbus_sel (wb_dmem_sel),
.i_wb_cpu_dbus_we (wb_dmem_we ),
.i_wb_cpu_dbus_cyc (wb_dmem_cyc),
.o_wb_cpu_dbus_rdt (wb_dmem_rdt),
.o_wb_cpu_dbus_ack (wb_dmem_ack),
.i_wb_cpu_ibus_adr (wb_ibus_adr),
.i_wb_cpu_ibus_cyc (wb_ibus_cyc),
.o_wb_cpu_ibus_rdt (wb_ibus_rdt),
.o_wb_cpu_ibus_ack (wb_ibus_ack),
.o_wb_cpu_adr (wb_mem_adr),
.o_wb_cpu_dat (wb_mem_dat),
.o_wb_cpu_sel (wb_mem_sel),
.o_wb_cpu_we (wb_mem_we ),
.o_wb_cpu_cyc (wb_mem_cyc),
.i_wb_cpu_rdt (wb_mem_rdt),
.i_wb_cpu_ack (wb_mem_ack));
emitter_mux #(sim) dmux
(
.i_clk (i_clk),
.i_rst (i_rst),
.i_wb_cpu_adr (wb_dbus_adr),
.i_wb_cpu_dat (wb_dbus_dat),
.i_wb_cpu_sel (wb_dbus_sel),
.i_wb_cpu_we (wb_dbus_we),
.i_wb_cpu_cyc (wb_dbus_cyc),
.o_wb_cpu_rdt (wb_dbus_rdt),
.o_wb_cpu_ack (wb_dbus_ack),
.o_wb_mem_adr (wb_dmem_adr),
.o_wb_mem_dat (wb_dmem_dat),
.o_wb_mem_sel (wb_dmem_sel),
.o_wb_mem_we (wb_dmem_we),
.o_wb_mem_cyc (wb_dmem_cyc),
.i_wb_mem_rdt (wb_dmem_rdt),
.o_wb_gpio_dat (wb_gpio_dat),
.o_wb_gpio_cyc (wb_gpio_cyc),
// .i_wb_gpio_rdt (wb_gpio_rdt),
.o_wb_timer_dat (),
.o_wb_timer_we (),
.o_wb_timer_cyc (),
.i_wb_timer_rdt (32'd0),
.o_wb_fifo_sel (wb_fifo_sel),
.o_wb_fifo_stb (wb_fifo_stb),
.i_wb_fifo_rdt (wb_fifo_rdt),
.i_wb_fifo_ack (wb_fifo_ack));
servant_ram
#(.memfile (memfile),
.RESET_STRATEGY ("MINI"),
.depth (memsize))
ram
(// Wishbone interface
.i_wb_clk (i_clk),
.i_wb_rst (i_rst),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
.i_wb_cyc (wb_mem_cyc),
.i_wb_we (wb_mem_we) ,
.i_wb_sel (wb_mem_sel),
.i_wb_dat (wb_mem_dat),
.o_wb_rdt (wb_mem_rdt),
.o_wb_ack (wb_mem_ack));
servant_gpio gpio
(.i_wb_clk (i_clk),
.i_wb_dat (wb_gpio_dat),
.i_wb_we (1'b1),
.i_wb_cyc (wb_gpio_cyc),
.o_wb_rdt (),
.o_gpio (o_uart_tx));
axis2wb s2w
(.i_clk (i_clk),
.i_rst (i_rst),
.i_wb_sel (wb_fifo_sel),
.i_wb_stb (wb_fifo_stb),
.o_wb_rdt (wb_fifo_rdt),
.o_wb_ack (wb_fifo_ack),
.i_tdata (i_tdata),
.i_tlast (i_tlast),
.i_tvalid (i_tvalid),
.o_tready (o_tready));
serv_rf_top
#(.RESET_PC (32'h0000_0000),
.WITH_CSR (0))
cpu
(
.clk (i_clk),
.i_rst (i_rst),
.i_timer_irq (1'b0),
`ifdef RISCV_FORMAL
.rvfi_valid (),
.rvfi_order (),
.rvfi_insn (),
.rvfi_trap (),
.rvfi_halt (),
.rvfi_intr (),
.rvfi_mode (),
.rvfi_ixl (),
.rvfi_rs1_addr (),
.rvfi_rs2_addr (),
.rvfi_rs1_rdata (),
.rvfi_rs2_rdata (),
.rvfi_rd_addr (),
.rvfi_rd_wdata (),
.rvfi_pc_rdata (),
.rvfi_pc_wdata (),
.rvfi_mem_addr (),
.rvfi_mem_rmask (),
.rvfi_mem_wmask (),
.rvfi_mem_rdata (),
.rvfi_mem_wdata (),
`endif
.o_ibus_adr (wb_ibus_adr),
.o_ibus_cyc (wb_ibus_cyc),
.i_ibus_rdt (wb_ibus_rdt),
.i_ibus_ack (wb_ibus_ack),
.o_dbus_adr (wb_dbus_adr),
.o_dbus_dat (wb_dbus_dat),
.o_dbus_sel (wb_dbus_sel),
.o_dbus_we (wb_dbus_we),
.o_dbus_cyc (wb_dbus_cyc),
.i_dbus_rdt (wb_dbus_rdt),
.i_dbus_ack (wb_dbus_ack));
endmodule |
module base
(input wire i_clk,
input wire i_rst,
output wire [7:0] o_tdata,
output wire o_tlast,
output wire o_tvalid,
input wire i_tready);
parameter memfile = "";
parameter memsize = 8192;
wire [31:0] wb_dat;
wire wb_we;
wire wb_stb;
wire wb_ack;
wb2axis w2s
(.i_clk (i_clk),
.i_rst (i_rst),
.i_wb_dat (wb_dat[8:0]),
.i_wb_we (wb_we),
.i_wb_stb (wb_stb),
.o_wb_ack (wb_ack),
.o_tdata (o_tdata),
.o_tlast (o_tlast),
.o_tvalid (o_tvalid),
.i_tready (i_tready));
serving
#(.memfile (memfile),
.memsize (memsize),
.WITH_CSR (0))
serving
(.i_clk (i_clk),
.i_rst (i_rst),
.i_timer_irq (1'b0),
.o_wb_adr (),
.o_wb_dat (wb_dat),
.o_wb_sel (),
.o_wb_we (wb_we),
.o_wb_stb (wb_stb),
.i_wb_rdt (32'd0),
.i_wb_ack (wb_ack));
endmodule |
module cmod_a7_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);
wire clkfb;
wire locked;
reg locked_r;
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(64),
.CLKIN1_PERIOD(83.33), // 12 MHz (not possible with PLLE2_BASE)
.CLKOUT0_DIVIDE_F(48),
.CLKOUT0_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01)
) MMCME2_ADV (
.CLKFBIN(clkfb),
.CLKIN1(i_clk),
.PWRDWN(0),
.RST(1'b0),
.CLKFBOUT(clkfb),
.CLKOUT0(o_clk),
.LOCKED(locked)
);
always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end
endmodule |
module CV_96 (
output q,
output uart_txd
);
wire clk;
HPS u0(
.h2f_user0_clk( clk) //hps_0_h2f_user0_clock.clk
);
corescore_chameleon96 u1 (
.i_clk ( clk ),
.i_rst_n ( 1'b1),
.q ( q ),
.uart_txd( uart_txd )
);
endmodule |
module mux_2(in_0,in_1,out,sel);
input in_0,in_1;
input sel;
output out;
wire in_0,in_1;
wire sel,sel_b;
wire n_0,n_1;
wire out;
or OR (out, n_0, n_1);
and AND0 (n_0, in_0, sel_b);
and AND1 (n_1, in_1, sel);
not NOT0 (sel_b, sel);
endmodule |
module s27_unrolled_4 (G1_3, G2_4, DFF_1_Q_reg_Q_0, G1_4, G2_2, G3_1, G1_2, G3_0, G0_4, G0_3, G1_0, G3_3, G1_1, G0_2, DFF_2_Q_reg_Q_0, G0_1, G3_4, G3_2, DFF_0_Q_reg_Q_0, G2_0, G2_1, G2_3, G0_0, G17_3, G17_2, DFF_0_Q_reg_D_4, G17_0, DFF_2_Q_reg_D_4, DFF_1_Q_reg_D_4, G17_1, G17_4);
input G1_3;
input G2_4;
input DFF_1_Q_reg_Q_0;
input G1_4;
input G2_2;
input G3_1;
input G1_2;
input G3_0;
input G0_4;
input G0_3;
input G1_0;
input G3_3;
input G1_1;
input G0_2;
input DFF_2_Q_reg_Q_0;
input G0_1;
input G3_4;
input G3_2;
input DFF_0_Q_reg_Q_0;
input G2_0;
input G2_1;
input G2_3;
input G0_0;
output G17_3;
output G17_2;
output DFF_0_Q_reg_D_4;
output G17_0;
output DFF_2_Q_reg_D_4;
output DFF_1_Q_reg_D_4;
output G17_1;
output G17_4;
wire G17_3;
wire unrolled_4_n_8;
wire unrolled_4_DFF_2_Q_reg_Q;
wire unrolled_3_DFF_2_Q_reg_D;
wire unrolled_0_n_12;
wire DFF_2_Q_reg_D_2;
wire DFF_1_Q_reg_Q_2;
wire unrolled_4_G7;
wire unrolled_3_G6;
wire unrolled_0_G1;
wire unrolled_4_n_4;
wire DFF_0_Q_reg_D_1;
wire unrolled_3_n_0;
wire unrolled_4_n_10;
wire unrolled_0_n_9;
wire unrolled_4_n_6;
wire unrolled_1_n_4;
wire unrolled_4_DFF_0_Q_reg_Q;
wire unrolled_1_DFF_2_Q_reg_Q;
wire unrolled_0_DFF_0_Q_reg_D;
wire unrolled_1_n_5;
wire unrolled_1_G7;
wire unrolled_1_n_10;
wire unrolled_1_DFF_1_Q_reg_Q;
wire unrolled_0_n_1;
wire unrolled_0_n_3;
wire unrolled_0_n_0;
wire unrolled_0_n_4;
wire unrolled_3_G7;
wire unrolled_3_n_2;
wire unrolled_0_n_6;
wire unrolled_3_n_6;
wire DFF_1_Q_reg_D_1;
wire unrolled_2_n_21;
wire DFF_0_Q_reg_Q_3;
wire unrolled_4_G0;
wire unrolled_0_DFF_2_Q_reg_D;
wire unrolled_2_G17_driver;
wire unrolled_4_n_9;
wire unrolled_4_n_1;
wire unrolled_0_n_11;
wire unrolled_4_n_12;
wire unrolled_1_G2;
wire unrolled_2_n_6;
wire unrolled_2_n_5;
wire unrolled_3_G17_driver;
wire unrolled_3_G2;
wire unrolled_2_n_7;
wire unrolled_4_G5;
wire unrolled_4_n_2;
wire unrolled_1_DFF_0_Q_reg_Q;
wire unrolled_1_n_8;
wire DFF_2_Q_reg_Q_4;
wire G17_4;
wire unrolled_1_n_2;
wire unrolled_3_DFF_1_Q_reg_D;
wire DFF_2_Q_reg_D_1;
wire unrolled_1_n_3;
wire unrolled_3_DFF_0_Q_reg_D;
wire unrolled_1_G17_driver;
wire unrolled_1_G1;
wire DFF_2_Q_reg_Q_1;
wire unrolled_1_G3;
wire DFF_1_Q_reg_D_2;
wire unrolled_3_G5;
wire unrolled_4_G17_driver;
wire unrolled_2_n_0;
wire unrolled_2_DFF_2_Q_reg_Q;
wire unrolled_3_n_5;
wire unrolled_4_n_5;
wire unrolled_1_n_0;
wire unrolled_2_G5;
wire unrolled_3_n_20;
wire unrolled_2_DFF_2_Q_reg_D;
wire DFF_2_Q_reg_D_4;
wire DFF_0_Q_reg_D_0;
wire DFF_1_Q_reg_D_0;
wire unrolled_1_DFF_0_Q_reg_D;
wire DFF_0_Q_reg_D_3;
wire unrolled_3_n_4;
wire DFF_2_Q_reg_Q_2;
wire DFF_1_Q_reg_Q_1;
wire unrolled_3_DFF_1_Q_reg_Q;
wire unrolled_0_n_7;
wire unrolled_2_n_3;
wire unrolled_2_n_8;
wire unrolled_0_G7;
wire unrolled_4_G3;
wire unrolled_2_n_1;
wire unrolled_2_DFF_1_Q_reg_Q;
wire unrolled_2_G2;
wire unrolled_1_n_20;
wire unrolled_1_G0;
wire unrolled_4_n_0;
wire unrolled_0_n_5;
wire unrolled_4_G6;
wire unrolled_0_n_10;
wire unrolled_1_n_12;
wire unrolled_3_n_21;
wire unrolled_1_n_11;
wire unrolled_3_n_12;
wire unrolled_0_G17_driver;
wire unrolled_2_G0;
wire unrolled_2_G1;
wire unrolled_4_G1;
wire DFF_1_Q_reg_D_4;
wire G17_1;
wire DFF_1_Q_reg_Q_4;
wire unrolled_2_n_2;
wire unrolled_2_n_12;
wire unrolled_1_n_7;
wire DFF_2_Q_reg_D_0;
wire unrolled_2_G7;
wire unrolled_2_G3;
wire unrolled_4_n_7;
wire unrolled_0_G3;
wire unrolled_2_n_10;
wire unrolled_0_DFF_0_Q_reg_Q;
wire unrolled_1_G6;
wire unrolled_0_DFF_2_Q_reg_Q;
wire DFF_0_Q_reg_D_4;
wire G17_0;
wire DFF_0_Q_reg_D_2;
wire unrolled_2_n_9;
wire unrolled_4_n_3;
wire unrolled_0_G5;
wire DFF_0_Q_reg_Q_1;
wire unrolled_1_n_6;
wire unrolled_0_DFF_1_Q_reg_D;
wire unrolled_0_G2;
wire unrolled_0_DFF_1_Q_reg_Q;
wire unrolled_2_n_20;
wire unrolled_3_G0;
wire unrolled_1_DFF_2_Q_reg_D;
wire DFF_0_Q_reg_Q_2;
wire unrolled_1_n_1;
wire unrolled_4_n_20;
wire DFF_1_Q_reg_D_3;
wire unrolled_3_n_7;
wire unrolled_3_n_3;
wire unrolled_0_G0;
wire unrolled_4_n_11;
wire DFF_2_Q_reg_D_3;
wire unrolled_3_DFF_0_Q_reg_Q;
wire unrolled_0_n_21;
wire unrolled_2_n_11;
wire unrolled_3_n_1;
wire unrolled_4_DFF_1_Q_reg_Q;
wire unrolled_3_n_11;
wire unrolled_0_n_20;
wire unrolled_2_DFF_0_Q_reg_D;
wire DFF_0_Q_reg_Q_4;
wire DFF_1_Q_reg_Q_3;
wire unrolled_3_n_9;
wire unrolled_3_DFF_2_Q_reg_Q;
wire unrolled_3_n_10;
wire unrolled_2_DFF_1_Q_reg_D;
wire unrolled_2_DFF_0_Q_reg_Q;
wire unrolled_1_DFF_1_Q_reg_D;
wire unrolled_0_n_2;
wire DFF_2_Q_reg_Q_3;
wire unrolled_0_n_8;
wire unrolled_3_G1;
wire unrolled_4_G2;
wire unrolled_2_n_4;
wire unrolled_3_G3;
wire G17_2;
wire unrolled_3_n_8;
wire unrolled_1_G5;
wire unrolled_4_n_21;
wire unrolled_1_n_21;
wire unrolled_2_G6;
wire unrolled_0_G6;
wire unrolled_1_n_9;
buf g_0 (G17_3, unrolled_3_G17_driver);
nor g_1 (unrolled_4_n_8, unrolled_4_n_4, unrolled_4_G7);
buf g_2 (unrolled_4_DFF_2_Q_reg_Q, DFF_2_Q_reg_Q_4);
buf g_3 (unrolled_3_DFF_2_Q_reg_D, unrolled_3_n_6);
not g_4 (unrolled_0_n_12, unrolled_0_n_11);
buf g_5 (DFF_2_Q_reg_D_2, unrolled_2_DFF_2_Q_reg_D);
buf g_6 (DFF_1_Q_reg_Q_2, DFF_1_Q_reg_D_1);
buf g_7 (unrolled_4_G7, unrolled_4_DFF_2_Q_reg_Q);
buf g_8 (unrolled_3_G6, unrolled_3_DFF_1_Q_reg_Q);
buf g_9 (unrolled_0_G1, G1_0);
nand g_10 (unrolled_4_n_4, unrolled_4_G3, unrolled_4_n_0);
buf g_11 (DFF_0_Q_reg_D_1, unrolled_1_DFF_0_Q_reg_D);
not g_12 (unrolled_3_n_0, unrolled_3_G1);
nor g_13 (unrolled_4_n_10, unrolled_4_n_7, unrolled_4_n_8);
nand g_14 (unrolled_0_n_9, unrolled_0_n_1, unrolled_0_n_8);
nor g_15 (unrolled_4_n_6, unrolled_4_G2, unrolled_4_n_3);
nand g_16 (unrolled_1_n_4, unrolled_1_n_0, unrolled_1_G3);
buf g_17 (unrolled_4_DFF_0_Q_reg_Q, DFF_0_Q_reg_Q_4);
buf g_18 (unrolled_1_DFF_2_Q_reg_Q, DFF_2_Q_reg_Q_1);
buf g_19 (unrolled_0_DFF_0_Q_reg_D, unrolled_0_n_12);
nand g_20 (unrolled_1_n_5, unrolled_1_n_2, unrolled_1_G6);
buf g_21 (unrolled_1_G7, unrolled_1_DFF_2_Q_reg_Q);
nor g_22 (unrolled_1_n_10, unrolled_1_n_7, unrolled_1_n_8);
buf g_23 (unrolled_1_DFF_1_Q_reg_Q, DFF_1_Q_reg_Q_1);
not g_24 (unrolled_0_n_1, unrolled_0_G5);
nor g_25 (unrolled_0_n_3, unrolled_0_G1, unrolled_0_G7);
not g_26 (unrolled_0_n_0, unrolled_0_G1);
nand g_27 (unrolled_0_n_4, unrolled_0_n_0, unrolled_0_G3);
buf g_28 (unrolled_3_G7, unrolled_3_DFF_2_Q_reg_Q);
not g_29 (unrolled_3_n_2, unrolled_3_G0);
nor g_30 (unrolled_0_n_6, unrolled_0_n_3, unrolled_0_G2);
nor g_31 (unrolled_3_n_6, unrolled_3_G2, unrolled_3_n_3);
buf g_32 (DFF_1_Q_reg_D_1, unrolled_1_DFF_1_Q_reg_D);
nor g_33 (unrolled_2_n_21, unrolled_2_G5, unrolled_2_n_10);
buf g_34 (DFF_0_Q_reg_Q_3, DFF_0_Q_reg_D_2);
buf g_35 (unrolled_4_G0, G0_4);
buf g_36 (unrolled_0_DFF_2_Q_reg_D, unrolled_0_n_6);
not g_37 (unrolled_2_G17_driver, unrolled_2_n_20);
nand g_38 (unrolled_4_n_9, unrolled_4_n_1, unrolled_4_n_8);
not g_39 (unrolled_4_n_1, unrolled_4_G5);
nand g_40 (unrolled_0_n_11, unrolled_0_n_9, unrolled_0_G0);
not g_41 (unrolled_4_n_12, unrolled_4_n_11);
buf g_42 (unrolled_1_G2, G2_1);
nor g_43 (unrolled_2_n_6, unrolled_2_G2, unrolled_2_n_3);
nand g_44 (unrolled_2_n_5, unrolled_2_G6, unrolled_2_n_2);
not g_45 (unrolled_3_G17_driver, unrolled_3_n_20);
buf g_46 (unrolled_3_G2, G2_3);
not g_47 (unrolled_2_n_7, unrolled_2_n_5);
buf g_48 (unrolled_4_G5, unrolled_4_DFF_0_Q_reg_Q);
not g_49 (unrolled_4_n_2, unrolled_4_G0);
buf g_50 (unrolled_1_DFF_0_Q_reg_Q, DFF_0_Q_reg_Q_1);
nor g_51 (unrolled_1_n_8, unrolled_1_G7, unrolled_1_n_4);
buf g_52 (DFF_2_Q_reg_Q_4, DFF_2_Q_reg_D_3);
buf g_53 (G17_4, unrolled_4_G17_driver);
not g_54 (unrolled_1_n_2, unrolled_1_G0);
buf g_55 (unrolled_3_DFF_1_Q_reg_D, unrolled_3_n_21);
buf g_56 (DFF_2_Q_reg_D_1, unrolled_1_DFF_2_Q_reg_D);
nor g_57 (unrolled_1_n_3, unrolled_1_G7, unrolled_1_G1);
buf g_58 (unrolled_3_DFF_0_Q_reg_D, unrolled_3_n_12);
not g_59 (unrolled_1_G17_driver, unrolled_1_n_20);
buf g_60 (unrolled_1_G1, G1_1);
buf g_61 (DFF_2_Q_reg_Q_1, DFF_2_Q_reg_D_0);
buf g_62 (unrolled_1_G3, G3_1);
buf g_63 (DFF_1_Q_reg_D_2, unrolled_2_DFF_1_Q_reg_D);
buf g_64 (unrolled_3_G5, unrolled_3_DFF_0_Q_reg_Q);
not g_65 (unrolled_4_G17_driver, unrolled_4_n_20);
not g_66 (unrolled_2_n_0, unrolled_2_G1);
buf g_67 (unrolled_2_DFF_2_Q_reg_Q, DFF_2_Q_reg_Q_2);
nand g_68 (unrolled_3_n_5, unrolled_3_G6, unrolled_3_n_2);
nand g_69 (unrolled_4_n_5, unrolled_4_G6, unrolled_4_n_2);
not g_70 (unrolled_1_n_0, unrolled_1_G1);
buf g_71 (unrolled_2_G5, unrolled_2_DFF_0_Q_reg_Q);
nor g_72 (unrolled_3_n_20, unrolled_3_G5, unrolled_3_n_10);
buf g_73 (unrolled_2_DFF_2_Q_reg_D, unrolled_2_n_6);
buf g_74 (DFF_2_Q_reg_D_4, unrolled_4_n_6);
buf g_75 (DFF_0_Q_reg_D_0, unrolled_0_DFF_0_Q_reg_D);
buf g_76 (DFF_1_Q_reg_D_0, unrolled_0_DFF_1_Q_reg_D);
buf g_77 (unrolled_1_DFF_0_Q_reg_D, unrolled_1_n_12);
buf g_78 (DFF_0_Q_reg_D_3, unrolled_3_DFF_0_Q_reg_D);
nand g_79 (unrolled_3_n_4, unrolled_3_n_0, unrolled_3_G3);
buf g_80 (DFF_2_Q_reg_Q_2, DFF_2_Q_reg_D_1);
buf g_81 (DFF_1_Q_reg_Q_1, DFF_1_Q_reg_D_0);
buf g_82 (unrolled_3_DFF_1_Q_reg_Q, DFF_1_Q_reg_Q_3);
not g_83 (unrolled_0_n_7, unrolled_0_n_5);
nor g_84 (unrolled_2_n_3, unrolled_2_G7, unrolled_2_G1);
nor g_85 (unrolled_2_n_8, unrolled_2_n_4, unrolled_2_G7);
buf g_86 (unrolled_0_G7, unrolled_0_DFF_2_Q_reg_Q);
buf g_87 (unrolled_4_G3, G3_4);
not g_88 (unrolled_2_n_1, unrolled_2_G5);
buf g_89 (unrolled_2_DFF_1_Q_reg_Q, DFF_1_Q_reg_Q_2);
buf g_90 (unrolled_2_G2, G2_2);
nor g_91 (unrolled_1_n_20, unrolled_1_n_10, unrolled_1_G5);
buf g_92 (unrolled_1_G0, G0_1);
not g_93 (unrolled_4_n_0, unrolled_4_G1);
nand g_94 (unrolled_0_n_5, unrolled_0_n_2, unrolled_0_G6);
buf g_95 (unrolled_4_G6, unrolled_4_DFF_1_Q_reg_Q);
nor g_96 (unrolled_0_n_10, unrolled_0_n_7, unrolled_0_n_8);
not g_97 (unrolled_1_n_12, unrolled_1_n_11);
nor g_98 (unrolled_3_n_21, unrolled_3_G5, unrolled_3_n_10);
nand g_99 (unrolled_1_n_11, unrolled_1_G0, unrolled_1_n_9);
not g_100 (unrolled_3_n_12, unrolled_3_n_11);
not g_101 (unrolled_0_G17_driver, unrolled_0_n_20);
buf g_102 (unrolled_2_G0, G0_2);
buf g_103 (unrolled_2_G1, G1_2);
buf g_104 (unrolled_4_G1, G1_4);
buf g_105 (DFF_1_Q_reg_D_4, unrolled_4_n_21);
buf g_106 (G17_1, unrolled_1_G17_driver);
buf g_107 (DFF_1_Q_reg_Q_4, DFF_1_Q_reg_D_3);
not g_108 (unrolled_2_n_2, unrolled_2_G0);
not g_109 (unrolled_2_n_12, unrolled_2_n_11);
not g_110 (unrolled_1_n_7, unrolled_1_n_5);
buf g_111 (DFF_2_Q_reg_D_0, unrolled_0_DFF_2_Q_reg_D);
buf g_112 (unrolled_2_G7, unrolled_2_DFF_2_Q_reg_Q);
buf g_113 (unrolled_2_G3, G3_2);
not g_114 (unrolled_4_n_7, unrolled_4_n_5);
buf g_115 (unrolled_0_G3, G3_0);
nor g_116 (unrolled_2_n_10, unrolled_2_n_7, unrolled_2_n_8);
buf g_117 (unrolled_0_DFF_0_Q_reg_Q, DFF_0_Q_reg_Q_0);
buf g_118 (unrolled_1_G6, unrolled_1_DFF_1_Q_reg_Q);
buf g_119 (unrolled_0_DFF_2_Q_reg_Q, DFF_2_Q_reg_Q_0);
buf g_120 (DFF_0_Q_reg_D_4, unrolled_4_n_12);
buf g_121 (G17_0, unrolled_0_G17_driver);
buf g_122 (DFF_0_Q_reg_D_2, unrolled_2_DFF_0_Q_reg_D);
nand g_123 (unrolled_2_n_9, unrolled_2_n_1, unrolled_2_n_8);
nor g_124 (unrolled_4_n_3, unrolled_4_G7, unrolled_4_G1);
buf g_125 (unrolled_0_G5, unrolled_0_DFF_0_Q_reg_Q);
buf g_126 (DFF_0_Q_reg_Q_1, DFF_0_Q_reg_D_0);
nor g_127 (unrolled_1_n_6, unrolled_1_n_3, unrolled_1_G2);
buf g_128 (unrolled_0_DFF_1_Q_reg_D, unrolled_0_n_21);
buf g_129 (unrolled_0_G2, G2_0);
buf g_130 (unrolled_0_DFF_1_Q_reg_Q, DFF_1_Q_reg_Q_0);
nor g_131 (unrolled_2_n_20, unrolled_2_G5, unrolled_2_n_10);
buf g_132 (unrolled_3_G0, G0_3);
buf g_133 (unrolled_1_DFF_2_Q_reg_D, unrolled_1_n_6);
buf g_134 (DFF_0_Q_reg_Q_2, DFF_0_Q_reg_D_1);
not g_135 (unrolled_1_n_1, unrolled_1_G5);
nor g_136 (unrolled_4_n_20, unrolled_4_G5, unrolled_4_n_10);
buf g_137 (DFF_1_Q_reg_D_3, unrolled_3_DFF_1_Q_reg_D);
not g_138 (unrolled_3_n_7, unrolled_3_n_5);
nor g_139 (unrolled_3_n_3, unrolled_3_G1, unrolled_3_G7);
buf g_140 (unrolled_0_G0, G0_0);
nand g_141 (unrolled_4_n_11, unrolled_4_G0, unrolled_4_n_9);
buf g_142 (DFF_2_Q_reg_D_3, unrolled_3_DFF_2_Q_reg_D);
buf g_143 (unrolled_3_DFF_0_Q_reg_Q, DFF_0_Q_reg_Q_3);
nor g_144 (unrolled_0_n_21, unrolled_0_G5, unrolled_0_n_10);
nand g_145 (unrolled_2_n_11, unrolled_2_n_9, unrolled_2_G0);
not g_146 (unrolled_3_n_1, unrolled_3_G5);
buf g_147 (unrolled_4_DFF_1_Q_reg_Q, DFF_1_Q_reg_Q_4);
nand g_148 (unrolled_3_n_11, unrolled_3_G0, unrolled_3_n_9);
nor g_149 (unrolled_0_n_20, unrolled_0_G5, unrolled_0_n_10);
buf g_150 (unrolled_2_DFF_0_Q_reg_D, unrolled_2_n_12);
buf g_151 (DFF_0_Q_reg_Q_4, DFF_0_Q_reg_D_3);
buf g_152 (DFF_1_Q_reg_Q_3, DFF_1_Q_reg_D_2);
nand g_153 (unrolled_3_n_9, unrolled_3_n_1, unrolled_3_n_8);
buf g_154 (unrolled_3_DFF_2_Q_reg_Q, DFF_2_Q_reg_Q_3);
nor g_155 (unrolled_3_n_10, unrolled_3_n_7, unrolled_3_n_8);
buf g_156 (unrolled_2_DFF_1_Q_reg_D, unrolled_2_n_21);
buf g_157 (unrolled_2_DFF_0_Q_reg_Q, DFF_0_Q_reg_Q_2);
buf g_158 (unrolled_1_DFF_1_Q_reg_D, unrolled_1_n_21);
not g_159 (unrolled_0_n_2, unrolled_0_G0);
buf g_160 (DFF_2_Q_reg_Q_3, DFF_2_Q_reg_D_2);
nor g_161 (unrolled_0_n_8, unrolled_0_n_4, unrolled_0_G7);
buf g_162 (unrolled_3_G1, G1_3);
buf g_163 (unrolled_4_G2, G2_4);
nand g_164 (unrolled_2_n_4, unrolled_2_n_0, unrolled_2_G3);
buf g_165 (unrolled_3_G3, G3_3);
buf g_166 (G17_2, unrolled_2_G17_driver);
nor g_167 (unrolled_3_n_8, unrolled_3_G7, unrolled_3_n_4);
buf g_168 (unrolled_1_G5, unrolled_1_DFF_0_Q_reg_Q);
nor g_169 (unrolled_4_n_21, unrolled_4_G5, unrolled_4_n_10);
nor g_170 (unrolled_1_n_21, unrolled_1_n_10, unrolled_1_G5);
buf g_171 (unrolled_2_G6, unrolled_2_DFF_1_Q_reg_Q);
buf g_172 (unrolled_0_G6, unrolled_0_DFF_1_Q_reg_Q);
nand g_173 (unrolled_1_n_9, unrolled_1_n_1, unrolled_1_n_8);
endmodule |
module switch(in_0,in_1,out_0,out_1,key);
input in_0,in_1;
input key;
output out_0,out_1;
wire in_0,in_1;
wire key;
wire out_0,out_1;
wire k_b,n_0,n_1,n_2,n_3;
not NOT (k_b, key);
or OR_0 (out_0, n_0, n_1);
and AND0_0 (n_0, in_0, k_b);
and AND1_0 (n_1, in_1, key);
or OR_1 (out_1, n_2, n_3);
and AND0_1 (n_2, in_0, key);
and AND1_1 (n_3, in_1, k_b);
endmodule |
module c17_assign (
G1, G2, G3, G6, G7,
G22, G23 );
input G1, G2, G3, G6, G7;
output G22, G23;
wire G10, G11, G16, G19;
assign G10 = ~G1 | ~G3;
assign G11 = ~G3 | ~G6;
assign G16 = ~G2 | ~G11;
assign G19 = ~G11 | ~G7;
assign G22 = ~G10 | ~G16;
assign G23 = ~G16 | ~G19;
endmodule |
Subsets and Splits