module
stringlengths 21
82.9k
|
|---|
module RV2T_data_access (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// interface from controller
//=====================================================================
input wire data_access_enable,
//=====================================================================
// interface for the execution unit
//=====================================================================
input wire ctl_CSR,
input wire ctl_CSR_write,
input wire [`XLEN - 1 : 0] csr_new_value,
input wire [`XLEN - 1 : 0] csr_old_value,
input wire [`CSR_BITS - 1 : 0] csr_addr,
input wire ctl_save_to_rd,
input wire [`REG_ADDR_BITS - 1 : 0] rd_addr_in,
input wire [`XLEN - 1 : 0] rd_data_in,
input wire load_active,
input wire store_active,
input wire [2 : 0] width_load_store,
input wire [`XLEN - 1 : 0] data_to_store,
input wire [`XLEN - 1 : 0] mem_access_addr,
input wire mem_access_unaligned,
input wire mul_div_done,
//=====================================================================
// interface to write to the register file
//=====================================================================
output wire ctl_reg_we,
output wire [`XLEN - 1 : 0] ctl_reg_data_to_write,
output wire [`REG_ADDR_BITS - 1 : 0] ctl_reg_addr,
//=====================================================================
// interface for CSR
//=====================================================================
output wire ctl_csr_we,
output wire [`CSR_ADDR_BITS - 1 : 0] ctl_csr_write_addr,
output wire [`XLEN - 1 : 0] ctl_csr_write_data,
//=====================================================================
// interface for memory
//=====================================================================
input wire mem_enable_in,
input wire [`XLEN - 1 : 0] mem_data_in,
input wire mm_reg_enable_in,
input wire [`XLEN - 1 : 0] mm_reg_data_in,
output wire mem_re,
output reg [`XLEN_BYTES - 1 : 0] mem_we,
output reg [`XLEN - 1 : 0] mem_data_to_write,
output reg [`XLEN - 1 : 0] mem_addr_rw_out,
output reg store_done,
output wire load_done,
output wire exception_alignment,
output reg mm_reg_re,
output reg mm_reg_we,
output reg [`XLEN - 1 : 0] mm_reg_data_to_write,
output reg [`MM_REG_ADDR_BITS - 1 : 0] mm_reg_addr_rw_out
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg ctl_mem_we;
reg ctl_mem_re;
reg ctl_mem_we_d1;
reg ctl_load_exception;
reg ctl_store_exception;
reg ctl_load_exception_d1;
reg ctl_store_done;
reg ctl_load_done;
reg ctl_load_shift;
reg ctl_load_mask;
reg ctl_load_reg_write;
reg [2 : 0] width_reg;
reg [3 : 0] width_mask;
reg [`XLEN - 1 : 0] mem_data_in_reg;
reg [`XLEN - 1 : 0] load_masked_data;
reg [1 : 0] mem_addr_rw_out_tail_reg;
wire [`XLEN - 1 : 0] mem_data_in_mux;
reg [`XLEN - 1 : 0] mem_access_addr_d1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------------
// register write back
//---------------------------------------------------------------------
assign ctl_reg_we = (data_access_enable & ctl_save_to_rd) | ctl_load_reg_write | mul_div_done;
assign ctl_reg_data_to_write = ctl_CSR ? csr_old_value : (ctl_load_reg_write ? load_masked_data : rd_data_in);
assign ctl_reg_addr = rd_addr_in;
//---------------------------------------------------------------------
// CSR write back
//---------------------------------------------------------------------
assign ctl_csr_we = data_access_enable & ctl_CSR_write;
assign ctl_csr_write_addr = csr_addr;
assign ctl_csr_write_data = csr_new_value;
//---------------------------------------------------------------------
// memory read / write
//---------------------------------------------------------------------
/* always @(*) begin
case (mem_access_addr[1 : 0]) // synthesis parallel_case
2'b01 : begin
mem_data_to_write = {data_to_store[23 : 0], 8'd0};
end
2'b10 : begin
mem_data_to_write = {data_to_store[15 : 0], 16'd0};
end
2'b11 : begin
mem_data_to_write = {data_to_store[7 : 0], 24'd0};
end
default : begin
mem_data_to_write = data_to_store;
end
endcase
end
*/
always @(*) begin
if (width_load_store [1 : 0] == 2'b00) begin
width_mask = 4'b0001 << (mem_access_addr[1 : 0]);
end else if (width_load_store [1 : 0] == 2'b01) begin
width_mask = 4'b0011 << (mem_access_addr[1 : 0]);
end else begin
width_mask = 4'b1111;
end
end
// assign mem_we ={ctl_mem_we, ctl_mem_we, ctl_mem_we, ctl_mem_we} & width_mask;
assign mem_re = ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];
always @(*) begin
if (ctl_mem_we_d1) begin
mem_addr_rw_out = mem_access_addr_d1;
end else begin
mem_addr_rw_out = mem_access_addr;
end
end
assign mem_data_in_mux = mem_enable_in ? mem_data_in : mm_reg_data_in;
always @(*) begin
case (mem_addr_rw_out_tail_reg) // synthesis parallel_case
2'b01 : begin
mem_data_in_reg = {8'd0, mem_data_in_mux[`XLEN - 1 : 8]};
end
2'b10 : begin
mem_data_in_reg = {16'd0, mem_data_in_mux[`XLEN - 1 : 16]};
end
2'b11 : begin
mem_data_in_reg = {24'd0, mem_data_in_mux[`XLEN - 1 : 24]};
end
default : begin
mem_data_in_reg = mem_data_in_mux;
end
endcase
end
always @(*) begin
case (width_reg)
3'b000 : begin // LB
load_masked_data = {{24{mem_data_in_reg[7]}}, mem_data_in_reg[7 : 0]};
end
3'b001 : begin // LH
load_masked_data = {{16{mem_data_in_reg[15]}}, mem_data_in_reg[15 : 0]};
end
3'b100 : begin // LBU
load_masked_data = {24'd0, mem_data_in_reg[7 : 0]};
end
3'b101 : begin // LHU
load_masked_data = {16'd0, mem_data_in_reg[15 : 0]};
end
default : begin
load_masked_data = mem_data_in_reg;
end
endcase
end
assign load_done = ctl_load_done;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
// mem_re <= 0;
mem_we <= 0;
mm_reg_re <= 0;
mm_reg_we <= 0;
mem_data_to_write <= 0;
// mem_addr_rw_out <= 0;
width_reg <= 0;
// width_mask <= 0;
// mem_data_in_reg <= 0;
ctl_mem_we_d1 <= 0;
store_done <= 0;
// load_done <= 0;
// load_masked_data <= 0;
mm_reg_data_to_write <= 0;
mm_reg_addr_rw_out <= 0;
mem_addr_rw_out_tail_reg <= 0;
mem_access_addr_d1 <= 0;
ctl_load_exception_d1 <= 0;
end else begin
mem_access_addr_d1 <= mem_access_addr;
ctl_load_exception_d1 <= ctl_load_exception;
mm_reg_we <= ctl_mem_we & mem_access_addr [`REG_SPACE_BIT];
mm_reg_re <= ctl_mem_re & mem_access_addr [`REG_SPACE_BIT];
mm_reg_data_to_write <= data_to_store;
mm_reg_addr_rw_out <= ctl_mem_we ? mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2] : mem_access_addr [`MM_REG_ADDR_BITS + 1 : 2];
//ctl_mem_we_d1 <= ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT];
ctl_mem_we_d1 <= ctl_mem_we;
store_done <= ctl_store_done;
//load_done <= ctl_load_done;
// mem_we <={ctl_mem_we_d1, ctl_mem_we_d1, ctl_mem_we_d1, ctl_mem_we_d1} & width_mask;
mem_we <= {4{ctl_mem_we & mem_access_addr [`MEM_SPACE_BIT]}} & width_mask;
/* if (mem_enable_in) begin
mem_data_in_reg <= mem_data_in;
end else if (mm_reg_enable_in) begin
mem_data_in_reg <= mm_reg_data_in;
end else if (ctl_load_shift) begin
case (mem_addr_rw_out [1 : 0]) // synthesis parallel_case
2'b01 : begin
mem_data_in_reg <= mem_data_in_reg >> 8;
end
2'b10 : begin
mem_data_in_reg <= mem_data_in_reg >> 16;
end
2'b11 : begin
mem_data_in_reg <= mem_data_in_reg >> 24;
end
default : begin
end
endcase
end
*/
/*
if (ctl_mem_we) begin
case (mem_access_addr[1 : 0]) // synthesis parallel_case
2'b01 : begin
mem_data_to_write <= {data_to_store[23 : 0], 8'd0};
end
2'b10 : begin
mem_data_to_write <= {data_to_store[15 : 0], 16'd0};
end
2'b11 : begin
mem_data_to_write <= {data_to_store[7 : 0], 24'd0};
end
default : begin
mem_data_to_write <= data_to_store;
end
endcase
mem_addr_rw_out <= mem_access_addr;
end else if (ctl_mem_re) begin
mem_addr_rw_out <= mem_access_addr;
end
*/
case (mem_access_addr[1 : 0]) // synthesis parallel_case
2'b01 : begin
mem_data_to_write <= {data_to_store[23 : 0], 8'd0};
end
2'b10 : begin
mem_data_to_write <= {data_to_store[15 : 0], 16'd0};
end
2'b11 : begin
mem_data_to_write <= {data_to_store[7 : 0], 24'd0};
end
default : begin
mem_data_to_write <= data_to_store;
end
endcase
// mem_re <= ctl_mem_re & mem_access_addr [`MEM_SPACE_BIT];
if (data_access_enable) begin
width_reg <= width_load_store;
mem_addr_rw_out_tail_reg <= mem_addr_rw_out [1 : 0];
/*
if (width_load_store [1 : 0] == 2'b00) begin
width_mask <= 4'b0001 << (mem_access_addr[1 : 0]);
end else if (width_load_store [1 : 0] == 2'b01) begin
width_mask <= 4'b0011 << (mem_access_addr[1 : 0]);
end else begin
width_mask <= 4'b1111;
end
*/
end
/* if (ctl_load_mask) begin
case (width_reg)
3'b000 : begin // LB
load_masked_data <= {{24{mem_data_in_reg[7]}}, mem_data_in_reg[7 : 0]};
end
3'b001 : begin // LH
load_masked_data <= {{16{mem_data_in_reg[15]}}, mem_data_in_reg[15 : 0]};
end
3'b100 : begin // LBU
load_masked_data <= {24'd0, mem_data_in_reg[7 : 0]};
end
3'b101 : begin // LHU
load_masked_data <= {16'd0, mem_data_in_reg[15 : 0]};
end
default : begin
load_masked_data <= mem_data_in_reg;
end
endcase
end
*/
end
end
//---------------------------------------------------------------------
// exception
//---------------------------------------------------------------------
/* always @(posedge clk, negedge reset_n) begin : exception_proc
if (!reset_n) begin
exception_alignment <= 0;
end else begin
exception_alignment <= ctl_load_store_exception;
end
end
*/
assign exception_alignment = ctl_store_exception | ctl_load_exception_d1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_EXCEPTION = 1, S_LOAD = 2;
reg [2 : 0] current_state, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else if (sync_reset) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_mem_we = 0;
ctl_mem_re = 0;
ctl_load_exception = 0;
ctl_store_exception = 0;
ctl_store_done = 0;
ctl_load_done = 0;
ctl_load_shift = 0;
ctl_load_mask = 0;
ctl_load_reg_write = 0;
case (1'b1) // synthesis parallel_case
current_state[S_IDLE]: begin
if (data_access_enable) begin
if (store_active) begin
if (mem_access_unaligned) begin
ctl_store_exception = 1'b1;
next_state [S_EXCEPTION] = 1'b1;
end else begin
ctl_mem_we = 1'b1;
//next_state [S_STORE] = 1'b1;
next_state [S_IDLE] = 1'b1;
end
end else if (load_active) begin
if (mem_access_unaligned) begin
ctl_load_exception = 1'b1;
next_state [S_EXCEPTION] = 1'b1;
end else begin
ctl_mem_re = 1'b1;
next_state [S_LOAD] = 1'b1;
end
end else begin
next_state [S_IDLE] = 1'b1;
end
end else begin
next_state [S_IDLE] = 1'b1;
end
end
current_state [S_EXCEPTION] : begin
next_state [S_IDLE] = 1'b1;
end
current_state [S_LOAD] : begin
if (mem_enable_in | mm_reg_enable_in) begin
//==next_state [S_LOAD_SHIFT_IN] = 1'b1;
ctl_load_reg_write = 1'b1;
ctl_load_done = 1'b1;
next_state [S_IDLE] = 1'b1;
end else begin
next_state [S_LOAD] = 1'b1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module RV2T_fetch_instruction (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// interface for the scheduler
//=====================================================================
input wire fetch_init,
input wire [`PC_BITWIDTH - 1 : 0] start_addr,
input wire fetch_next,
output reg fetch_enable_out,
output reg [`XLEN - 1 : 0] IR_out,
output reg [`PC_BITWIDTH - 1 : 0] PC_out,
//=====================================================================
// interface to memory controller
//=====================================================================
input wire mem_read_done,
input wire [`XLEN - 1 : 0] mem_data,
output reg read_mem_enable,
output reg [`PC_BITWIDTH - 1 : 0] read_mem_addr
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg ctl_load_start_addr;
reg ctl_inc_read_addr;
reg ctl_read_mem_enable;
reg read_mem_enable_d1;
reg [`PC_BITWIDTH - 1 : 0] PC_out_i;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------------
// read memory
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : read_mem_proc
if (!reset_n) begin
read_mem_enable <= 0;
read_mem_addr <= 0;
read_mem_enable_d1 <= 0;
end else begin
read_mem_enable <= ctl_read_mem_enable;
read_mem_enable_d1 <= read_mem_enable;
if (ctl_load_start_addr) begin
read_mem_addr <= start_addr;
end else if (ctl_inc_read_addr) begin
read_mem_addr <= read_mem_addr + 4;
end
end
end
//---------------------------------------------------------------------
// output
//---------------------------------------------------------------------
always @(posedge clk, negedge reset_n) begin : PC_proc
if (!reset_n) begin
PC_out <= 0;
IR_out <= `RV32I_NOP;
fetch_enable_out <= 0;
PC_out_i <= 0;
end else begin
fetch_enable_out <= mem_read_done;
PC_out <= PC_out_i;
if (read_mem_enable) begin
PC_out_i <= read_mem_addr;
end
if (mem_read_done & read_mem_enable_d1) begin
IR_out <= mem_data;
end
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_FETCH = 1;
reg [1 : 0] current_state, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else if (sync_reset) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_load_start_addr = 0;
ctl_read_mem_enable = 0;
ctl_inc_read_addr = 0;
case (1'b1) // synthesis parallel_case
current_state[S_IDLE]: begin
if (fetch_init) begin
ctl_load_start_addr = 1'b1;
ctl_read_mem_enable = 1'b1;
next_state [S_FETCH] = 1'b1;
end else begin
next_state [S_IDLE] = 1'b1;
end
end
current_state [S_FETCH] : begin
next_state [S_FETCH] = 1'b1;
ctl_read_mem_enable = fetch_init | fetch_next;
if (fetch_init) begin
ctl_load_start_addr = 1'b1;
end else if (fetch_next) begin
ctl_inc_read_addr = 1'b1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module PulseRain_RV2T_core (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
input wire sync_reset,
//=====================================================================
// Interface Onchip Debugger
//=====================================================================
//== input wire run1_pause0,
input wire ocd_read_enable,
input wire ocd_write_enable,
input wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr,
input wire [`XLEN - 1 : 0] ocd_write_word,
output wire ocd_mem_enable_out,
output wire [`XLEN - 1 : 0] ocd_mem_word_out,
input wire [`REG_ADDR_BITS - 1 : 0] ocd_reg_read_addr,
input wire ocd_reg_we,
input wire [`REG_ADDR_BITS - 1 : 0] ocd_reg_write_addr,
input wire [`XLEN - 1 : 0] ocd_reg_write_data,
//=====================================================================
// UARAT
//=====================================================================
output wire start_TX,
output wire [7 : 0] tx_data,
input wire tx_active,
//=====================================================================
// Interface for init/start
//=====================================================================
input wire start,
input wire [`PC_BITWIDTH - 1 : 0] start_address,
output wire [31 : 0] peek_pc,
output wire [31 : 0] peek_ir,
output wire [`MEM_ADDR_BITS - 1 : 0] mem_addr,
output wire [`XLEN_BYTES - 1 : 0] mem_write_en,
output wire [`XLEN - 1 : 0] mem_write_data,
input wire [`XLEN - 1 : 0] mem_read_data,
output wire processor_paused
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire csr_read_en_out;
wire [`XLEN - 1 : 0] csr_read_data_out;
wire mem_enable_out;
wire [`XLEN - 1 : 0] mem_word_out;
wire [`REG_ADDR_BITS - 1 : 0] reg_file_read_rs1_addr;
wire [`REG_ADDR_BITS - 1 : 0] reg_file_read_rs2_addr;
wire [`XLEN - 1 : 0] reg_file_read_rs1_data_out;
wire [`XLEN - 1 : 0] reg_file_read_rs2_data_out;
wire reg_file_write_enable;
wire [`REG_ADDR_BITS - 1 : 0] reg_file_write_addr;
wire [`XLEN - 1 : 0] reg_file_write_data;
wire fetch_init;
wire [`PC_BITWIDTH - 1 : 0] fetch_init_addr;
wire fetch_next;
wire fetch_enable_out;
wire [`XLEN - 1 : 0] fetch_IR_out;
wire [`PC_BITWIDTH - 1 : 0] fetch_PC_out;
wire fetch_read_mem_enable;
wire [`PC_BITWIDTH - 1 : 0] fetch_read_mem_addr;
wire decode_enable;
wire [`REG_ADDR_BITS - 1 : 0] rs1;
wire [`REG_ADDR_BITS - 1 : 0] rs2;
wire [`XLEN - 1 : 2] decode_IR_out ;
wire [`PC_BITWIDTH - 1 : 0] decode_PC_out ;
wire [`CSR_BITS - 1 : 0] decode_csr;
wire decode_csr_enable;
wire decode_ctl_load_X_from_rs1;
wire decode_ctl_load_Y_from_rs2;
wire decode_ctl_load_Y_from_imm_12;
wire decode_ctl_load_Y_from_store_offset_12;
wire decode_ctl_save_to_rd;
wire decode_ctl_ALU_FUNCT3;
wire decode_ctl_MUL_DIV_FUNCT3;
wire decode_ctl_LUI;
wire decode_ctl_AUIPC;
wire decode_ctl_JAL;
wire decode_ctl_JALR;
wire decode_ctl_BRANCH;
wire decode_ctl_LOAD;
wire decode_ctl_STORE;
wire decode_ctl_SYSTEM;
wire decode_ctl_CSR;
wire decode_ctl_CSR_write;
wire decode_ctl_MISC_MEM;
wire decode_ctl_MRET;
wire decode_ctl_WFI;
wire exe_ctl_save_to_rd;
wire exe_ctl_LOAD;
wire exe_ctl_STORE;
wire [`REG_ADDR_BITS - 1 : 0] exe_rd_addr_out;
wire [`XLEN - 1 : 0] exe_data_out;
wire exe_enable ;
wire data_access_enable;
wire data_access_reg_we;
wire [`XLEN - 1 : 0] data_access_reg_data_to_write;
wire [`REG_ADDR_BITS - 1 : 0] data_access_reg_addr;
wire exe_branch_active;
wire [`PC_BITWIDTH - 1 : 0] exe_branch_addr;
wire exe_jalr_active;
wire [`PC_BITWIDTH - 1 : 0] exe_jalr_addr;
wire exe_jal_active;
wire [`PC_BITWIDTH - 1 : 0] exe_jal_addr;
wire exe_load_active;
wire exe_store_active;
wire [`XLEN - 1 : 0] exe_data_to_store;
wire [`XLEN - 1 : 0] exe_mem_access_addr;
wire exe_mem_access_unaligned;
wire exe_unaligned_read;
wire [2 : 0] exe_width_load_store;
wire exe_reg_ctl_CSR;
wire exe_reg_ctl_CSR_write;
wire [`CSR_BITS - 1 : 0] exe_csr_addr;
wire [`XLEN - 1 : 2] exe_IR_out;
wire [`PC_BITWIDTH - 1 : 0] exe_PC_out;
wire data_access_mem_re;
wire [`XLEN_BYTES - 1 : 0] data_access_mem_we;
wire [`XLEN - 1 : 0] data_access_mem_data_to_write;
wire [`XLEN - 1 : 0] data_access_mem_addr_rw;
wire data_access_ctl_csr_we;
wire [`CSR_ADDR_BITS - 1 : 0] data_access_ctl_csr_write_addr;
wire [`XLEN - 1 : 0] data_access_ctl_csr_write_data;
wire store_done;
wire load_done;
wire [`XLEN - 1 : 0] csr_new_value;
wire [`XLEN - 1 : 0] csr_old_value;
wire exception_ecall;
wire exception_ebreak;
wire exception_alignment;
wire decode_exception_illegal_instruction;
wire csr_exception_illegal_instruction;
wire activate_exception;
wire [`EXCEPTION_CODE_BITS - 1 : 0] exception_code;
wire [`XLEN - 1 : 0] mtvec_value;
wire [`XLEN - 1 : 0] mepc_value;
wire [`PC_BITWIDTH - 1 : 0] exception_PC;
wire [`PC_BITWIDTH - 1 : 0] exception_addr;
wire mret_active;
wire mul_div_active;
wire mul_div_done;
wire paused;
wire run1_pause0;
wire mm_reg_re;
wire mm_reg_we;
wire [`XLEN - 1 : 0] mm_reg_data_to_write;
wire [`MM_REG_ADDR_BITS - 1 : 0] mm_reg_addr_rw;
wire mm_reg_enable_out;
wire [`XLEN - 1 : 0] mm_reg_word_out;
wire timer_triggered;
wire mtie_out;
wire mie_out;
wire mtip_out;
wire is_interrupt;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Data Path
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//---------------------------------------------------------------------
// memory mapped registers
//---------------------------------------------------------------------
RV2T_mm_reg RV2T_mm_reg_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.data_read_enable (mm_reg_re),
.data_write_enable (mm_reg_we),
.data_rw_addr (mm_reg_addr_rw),
.data_write_word (mm_reg_data_to_write),
.enable_out (mm_reg_enable_out),
.word_out (mm_reg_word_out),
.start_TX (start_TX),
.tx_data (tx_data),
.tx_active (tx_active),
.timer_triggered (timer_triggered));
//---------------------------------------------------------------------
// memory
//---------------------------------------------------------------------
RV2T_memory RV2T_memory_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.code_read_enable (fetch_read_mem_enable),
.code_read_addr (fetch_read_mem_addr [`MEM_ADDR_BITS + 1 : 2]),
.data_read_enable (data_access_mem_re),
.data_write_enable (data_access_mem_we),
.data_rw_addr (data_access_mem_addr_rw [`MEM_ADDR_BITS + 1 : 2]),
.data_write_word (data_access_mem_data_to_write),
.enable_out (mem_enable_out),
.word_out (mem_word_out),
.mem_addr (mem_addr),
.mem_write_en (mem_write_en),
.mem_write_data (mem_write_data),
.mem_read_data (mem_read_data));
assign ocd_mem_enable_out = mem_enable_out;
assign ocd_mem_word_out = mem_word_out;
//---------------------------------------------------------------------
// register file
//---------------------------------------------------------------------
assign processor_paused = paused;
assign run1_pause0 = ~paused;
assign reg_file_read_rs1_addr = rs1;
assign reg_file_read_rs2_addr = run1_pause0 ? rs2 : ocd_reg_read_addr;
assign reg_file_write_enable = run1_pause0 ? data_access_reg_we : ocd_reg_we;
assign reg_file_write_addr = run1_pause0 ? data_access_reg_addr : ocd_reg_write_addr;
assign reg_file_write_data = run1_pause0 ? data_access_reg_data_to_write : ocd_reg_write_data;
RV2T_reg_file RV2T_reg_file_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.read_enable (fetch_enable_out),
.read_rs1_addr (reg_file_read_rs1_addr),
.read_rs2_addr (reg_file_read_rs2_addr),
.read_en_out(),
.read_rs1_data_out (reg_file_read_rs1_data_out),
.read_rs2_data_out (reg_file_read_rs2_data_out),
.write_enable (reg_file_write_enable),
.write_addr (reg_file_write_addr),
.write_data_in (reg_file_write_data));
//---------------------------------------------------------------------
// Control and Status Registers
//---------------------------------------------------------------------
RV2T_CSR RV2T_CSR_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.exe_enable (exe_enable),
.read_enable (decode_csr_enable & exe_enable),
.read_addr (decode_csr),
.read_en_out (csr_read_en_out),
.read_data_out (csr_read_data_out),
.write_enable (data_access_ctl_csr_we),
.write_addr (data_access_ctl_csr_write_addr),
.write_data_in (data_access_ctl_csr_write_data),
.timer_triggered (timer_triggered),
.activate_exception (activate_exception),
.is_interrupt (is_interrupt),
.exception_code (exception_code),
.exception_PC (exception_PC),
.exception_addr (exception_addr),
.exception_illegal_instruction (csr_exception_illegal_instruction),
.mtvec_out (mtvec_value),
.mepc_out (mepc_value),
.mtie_out (mtie_out),
.mie_out (mie_out),
.mtip_out (mtip_out));
//---------------------------------------------------------------------
// fetch instruction
//---------------------------------------------------------------------
RV2T_fetch_instruction RV2T_fetch_instruction_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.fetch_init (fetch_init),
.start_addr (fetch_init_addr),
.fetch_next (fetch_next),
.fetch_enable_out (fetch_enable_out),
.IR_out (fetch_IR_out),
.PC_out (fetch_PC_out),
.mem_read_done (mem_enable_out),
.mem_data (mem_word_out),
.read_mem_enable (fetch_read_mem_enable),
.read_mem_addr (fetch_read_mem_addr));
//---------------------------------------------------------------------
// instruction decode
//---------------------------------------------------------------------
RV2T_instruction_decode RV2T_instruction_decode_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.decode_enable (decode_enable),
.enable_in (fetch_enable_out),
.IR_in (fetch_IR_out),
.PC_in (fetch_PC_out),
.rs1 (rs1),
.rs2 (rs2),
.csr (decode_csr),
.csr_read_enable (decode_csr_enable),
.IR_out (decode_IR_out),
.PC_out (decode_PC_out),
.ctl_load_X_from_rs1 (decode_ctl_load_X_from_rs1),
.ctl_load_Y_from_rs2 (decode_ctl_load_Y_from_rs2),
.ctl_load_Y_from_imm_12 (decode_ctl_load_Y_from_imm_12),
.ctl_load_Y_from_store_offset_12 (decode_ctl_load_Y_from_store_offset_12),
.ctl_save_to_rd (decode_ctl_save_to_rd),
.ctl_ALU_FUNCT3 (decode_ctl_ALU_FUNCT3),
.ctl_MUL_DIV_FUNCT3 (decode_ctl_MUL_DIV_FUNCT3),
.ctl_LUI (decode_ctl_LUI),
.ctl_AUIPC (decode_ctl_AUIPC),
.ctl_JAL (decode_ctl_JAL),
.ctl_JALR (decode_ctl_JALR),
.ctl_BRANCH (decode_ctl_BRANCH),
.ctl_LOAD (decode_ctl_LOAD),
.ctl_STORE (decode_ctl_STORE),
.ctl_SYSTEM (decode_ctl_SYSTEM),
.ctl_CSR (decode_ctl_CSR),
.ctl_CSR_write (decode_ctl_CSR_write),
.ctl_MISC_MEM (decode_ctl_MISC_MEM),
.ctl_MRET (decode_ctl_MRET),
.ctl_WFI (decode_ctl_WFI),
.exception_illegal_instruction (decode_exception_illegal_instruction));
//---------------------------------------------------------------------
// execution unit
//---------------------------------------------------------------------
RV2T_execution_unit RV2T_execution_unit_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.exe_enable (exe_enable),
.enable_in (1'b0),
.IR_in (decode_IR_out),
.PC_in (decode_PC_out),
.csr_addr_in (decode_csr),
.ctl_load_Y_from_imm_12 (decode_ctl_load_Y_from_imm_12),
.ctl_save_to_rd (decode_ctl_save_to_rd),
.ctl_LUI (decode_ctl_LUI),
.ctl_AUIPC (decode_ctl_AUIPC),
.ctl_JAL (decode_ctl_JAL),
.ctl_JALR (decode_ctl_JALR),
.ctl_BRANCH (decode_ctl_BRANCH),
.ctl_LOAD (decode_ctl_LOAD),
.ctl_STORE (decode_ctl_STORE),
.ctl_SYSTEM (decode_ctl_SYSTEM),
.ctl_CSR (decode_ctl_CSR),
.ctl_CSR_write (decode_ctl_CSR_write),
.ctl_MISC_MEM (decode_ctl_MISC_MEM),
.ctl_MRET (decode_ctl_MRET),
.ctl_MUL_DIV_FUNCT3 (decode_ctl_MUL_DIV_FUNCT3),
.rs1_in (reg_file_read_rs1_data_out),
.rs2_in (reg_file_read_rs2_data_out),
.csr_in (csr_read_data_out),
.enable_out (),
.rd_addr_out (exe_rd_addr_out),
.IR_out (exe_IR_out),
.PC_out (exe_PC_out),
.branch_active (exe_branch_active),
.branch_addr (exe_branch_addr),
.csr_new_value (csr_new_value),
.csr_old_value (csr_old_value),
.reg_ctl_save_to_rd (exe_ctl_save_to_rd),
.data_out (exe_data_out),
.load_active (exe_load_active),
.store_active (exe_store_active),
.width_load_store (exe_width_load_store),
.data_to_store (exe_data_to_store),
.mem_access_addr (exe_mem_access_addr),
.mem_access_unaligned (exe_mem_access_unaligned),
.reg_ctl_CSR (exe_reg_ctl_CSR),
.reg_ctl_CSR_write (exe_reg_ctl_CSR_write),
.csr_addr_out (exe_csr_addr),
.ecall_active (exception_ecall),
.ebreak_active (exception_ebreak),
.mret_active (mret_active),
.mul_div_active (mul_div_active),
.mul_div_done (mul_div_done)
);
//---------------------------------------------------------------------
// data access
//---------------------------------------------------------------------
RV2T_data_access RV2T_data_access_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.data_access_enable (data_access_enable),
.ctl_CSR (exe_reg_ctl_CSR),
.ctl_CSR_write (exe_reg_ctl_CSR_write),
.csr_new_value (csr_new_value),
.csr_old_value (csr_old_value),
.csr_addr (exe_csr_addr),
.ctl_save_to_rd (exe_ctl_save_to_rd),
.rd_addr_in (exe_rd_addr_out),
.rd_data_in (exe_data_out),
.load_active (exe_load_active),
.store_active (exe_store_active),
.width_load_store (exe_width_load_store),
.data_to_store (exe_data_to_store),
.mem_access_addr (exe_mem_access_addr),
.mem_access_unaligned (exe_mem_access_unaligned),
.mul_div_done (mul_div_done),
.ctl_reg_we (data_access_reg_we),
.ctl_reg_data_to_write (data_access_reg_data_to_write),
.ctl_reg_addr (data_access_reg_addr),
.ctl_csr_we (data_access_ctl_csr_we),
.ctl_csr_write_addr (data_access_ctl_csr_write_addr),
.ctl_csr_write_data (data_access_ctl_csr_write_data),
.mem_enable_in (mem_enable_out),
.mem_data_in (mem_word_out),
.mm_reg_enable_in (mm_reg_enable_out),
.mm_reg_data_in (mm_reg_word_out),
.mem_re (data_access_mem_re),
.mem_we (data_access_mem_we),
.mem_data_to_write (data_access_mem_data_to_write),
.mem_addr_rw_out (data_access_mem_addr_rw),
.store_done (store_done),
.load_done (load_done),
.exception_alignment (exception_alignment),
.mm_reg_re (mm_reg_re),
.mm_reg_we (mm_reg_we),
.mm_reg_data_to_write (mm_reg_data_to_write),
.mm_reg_addr_rw_out (mm_reg_addr_rw));
//---------------------------------------------------------------------
// pipeline controller
//---------------------------------------------------------------------
RV2T_controller RV2T_controller_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (sync_reset),
.start (start),
.start_addr (start_address),
.fetch_init (fetch_init),
.fetch_start_addr (fetch_init_addr),
.fetch_next (fetch_next),
.mul_div_active (mul_div_active),
.mul_div_done (mul_div_done),
.decode_ctl_LOAD (decode_ctl_LOAD),
.decode_ctl_STORE (decode_ctl_STORE),
.decode_ctl_MISC_MEM (decode_ctl_MISC_MEM),
.decode_ctl_MUL_DIV_FUNCT3 (decode_ctl_MUL_DIV_FUNCT3),
.decode_ctl_WFI (decode_ctl_WFI),
.branch_active (exe_branch_active),
.branch_addr (exe_branch_addr),
.load_active (exe_load_active),
.data_to_store (exe_data_to_store),
.mem_access_addr (exe_mem_access_addr),
.unaligned_write (exe_mem_access_unaligned),
.store_done (store_done),
.load_done (load_done),
.mret_active (mret_active),
.exe_enable (exe_enable),
.data_access_enable (data_access_enable),
.PC_in (exe_PC_out),
.mtvec_in (mtvec_value),
.mepc_in (mepc_value),
.exception_storage_page_fault (1'b0),
.exception_ecall (exception_ecall),
.exception_ebreak (exception_ebreak),
.exception_alignment (exception_alignment),
.timer_triggered (mtip_out & mtie_out & mie_out),
.is_interrupt (is_interrupt),
.exception_code (exception_code),
.activate_exception (activate_exception),
.exception_PC (exception_PC),
.exception_addr (exception_addr),
.exception_illegal_instruction (decode_exception_illegal_instruction | csr_exception_illegal_instruction),
.paused (paused)
);
//----------------------------------------------------------------------------
// DEBUG
//----------------------------------------------------------------------------
assign peek_pc = exe_PC_out;
assign peek_ir = { exe_IR_out, 2'b11 };
endmodule |
module long_slow_div_denom_reg
#(parameter DATA_WIDTH = 32)(
//======= clock and reset ======
input wire clk,
input wire reset_n,
//========== INPUT ==========
input wire enable_in,
input wire [DATA_WIDTH - 1 : 0] numerator,
input wire [DATA_WIDTH - 1 : 0] denominator,
//========== OUTPUT ==========
output wire enable_out,
output wire [DATA_WIDTH - 1 : 0] quotient,
output reg [DATA_WIDTH - 1 : 0] remainder,
output reg div_by_zero,
output reg error
);
reg [DATA_WIDTH * 2 : 0] L_num;
wire [DATA_WIDTH : 0] L_num_high;
wire [DATA_WIDTH : 0] L_den;
wire [DATA_WIDTH : 0] difference;
reg [DATA_WIDTH - 1 : 0] denominator_reg;
reg [$clog2(DATA_WIDTH) : 0] iteration;
reg ctl_set_div_by_zero;
reg ctl_division_init, ctl_division_enable, ctl_set_enable_out;
reg [DATA_WIDTH : 0] quotient_i;
always @(posedge clk) begin
if (enable_in) begin
denominator_reg <= denominator;
end
end
assign L_num_high = L_num [DATA_WIDTH * 2 : DATA_WIDTH];
assign difference = L_num_high - L_den;
assign L_den = {1'b0, denominator_reg};
always @(posedge clk) begin
if (ctl_division_init) begin
L_num <= { {(DATA_WIDTH){1'b0}}, numerator, 1'b0};
end else if (ctl_division_enable) begin
if (L_num_high >= L_den) begin
L_num <= {difference [DATA_WIDTH - 1 : 0], L_num [DATA_WIDTH - 1 : 0], 1'b0};
end else begin
L_num <= L_num << 1;
end
end
end
always @(posedge clk) begin
if (ctl_division_init) begin
iteration <= 0;
remainder <= 0;
end else if (ctl_division_enable) begin
iteration <= iteration + 1;
remainder <= L_num_high[32 : 1];
end
end
always @(posedge clk) begin : div_by_zero_proc
if (enable_in) begin
div_by_zero <= 0;
end else begin
div_by_zero <= ctl_set_div_by_zero;
end
end
always @(posedge clk) begin : error_proc
if (enable_in) begin
error <= 0;
end else if (ctl_set_div_by_zero) begin
error <= 1;
end
end
always @(posedge clk) begin : quotient_proc
if (ctl_division_init) begin
quotient_i <= 0;
end else if (ctl_division_enable) begin
if (L_num_high >= L_den) begin
quotient_i <= {quotient_i [DATA_WIDTH - 1 : 0], 1'b1};
end else begin
quotient_i <= {quotient_i [DATA_WIDTH - 1 : 0], 1'b0};
end
end
end
assign quotient = quotient_i [DATA_WIDTH : 1];
assign enable_out = ctl_set_enable_out;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_CHECK = 1, S_DIVISION = 2, S_OUTPUT = 3;
reg [3 : 0] current_state, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_set_div_by_zero = 0;
ctl_division_init = 0;
ctl_division_enable = 0;
ctl_set_enable_out = 0;
case (1'b1)
current_state[S_IDLE]: begin
if (!enable_in) begin
next_state[S_IDLE] = 1;
end else begin
next_state[S_CHECK] = 1;
end
end
current_state[S_CHECK] : begin
next_state[S_DIVISION] = 1;
ctl_division_init = 1;
if (denominator_reg == 0) begin
ctl_set_div_by_zero = 1;
end
end
current_state[S_DIVISION] : begin
if (iteration == (DATA_WIDTH + 1)) begin
next_state[S_OUTPUT] = 1;
end else begin
ctl_division_enable = 1;
next_state[S_DIVISION] = 1;
end
end
current_state[S_OUTPUT] : begin
ctl_set_enable_out = 1;
next_state[S_IDLE] = 1;
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module absolute_value #(parameter DATA_WIDTH=32)(
//========== INPUT ==========
input wire signed [DATA_WIDTH - 1 : 0] data_in,
//========== OUTPUT ==========
output wire signed [DATA_WIDTH - 1 : 0] data_out
//========== IN/OUT ==========
);
wire signed [DATA_WIDTH - 1 : 0] data_sign_ext, data_tmp;
wire signed [DATA_WIDTH - 1 : 0] abs_value;
assign data_sign_ext = {(DATA_WIDTH){data_in[DATA_WIDTH - 1]}};
assign data_tmp = data_in ^ data_sign_ext;
assign abs_value = data_tmp - data_sign_ext;
assign data_out = abs_value;
endmodule |
module mul_div_32(
//======= clock and reset ======
input wire clk,
input wire reset_n,
//========== INPUT ==========
input wire enable_in,
input wire signed [31 : 0] x,
input wire signed [31 : 0] y,
input wire mul0_div1,
input wire x_signed0_unsigned1,
input wire y_signed0_unsigned1,
//========== OUTPUT ==========
output wire enable_out,
output wire [63 : 0] z,
output wire ov
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire signed [31 : 0] x_abs;
wire signed [31 : 0] y_abs;
reg unsigned [31 : 0] x_mul;
reg unsigned [31 : 0] y_mul;
wire x_max_neg_flag;
reg enable_in_d1;
reg enable_in_d2;
reg enable_in_d3;
reg mul0_div1_reg;
reg z_pos0_neg1;
reg x_pos0_neg1;
wire div_enable_out;
reg [63 : 0] z_i;
wire [31 : 0] q_i;
wire [31 : 0] r_i;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// mul
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign x_max_neg_flag = x[31] & (~(|x[30 : 0]));
absolute_value #(.DATA_WIDTH (32)) abs_x_i (
.data_in (x),
.data_out (x_abs));
absolute_value #(.DATA_WIDTH (32)) abs_y_i (
.data_in (y),
.data_out (y_abs));
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
x_mul <= 0;
y_mul <= 0;
z_i <= 0;
mul0_div1_reg <= 0;
enable_in_d1 <= 0;
enable_in_d2 <= 0;
enable_in_d3 <= 0;
end else begin
enable_in_d1 <= enable_in;
enable_in_d2 <= enable_in_d1;
enable_in_d3 <= enable_in_d2;
if (enable_in) begin
if (!x_signed0_unsigned1) begin
x_mul <= x_abs;
end else begin
x_mul <= x;
end
if (!y_signed0_unsigned1) begin
y_mul <= y_abs;
end else begin
y_mul <= y;
end
mul0_div1_reg <= mul0_div1;
z_pos0_neg1 <= (~x_signed0_unsigned1 & x[31]) ^ (~y_signed0_unsigned1 & y[31]);
x_pos0_neg1 <= ~x_signed0_unsigned1 & x[31];
end
z_i <= x_mul * y_mul;
end
end
assign enable_out = mul0_div1_reg ? div_enable_out : enable_in_d3;
assign z = mul0_div1_reg ?
{z_pos0_neg1 ? -q_i : q_i, x_pos0_neg1 ? -r_i : r_i} :
(z_pos0_neg1 ? -z_i : z_i);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// div
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
long_slow_div_denom_reg #(.DATA_WIDTH (32)) long_slow_div_denom_reg_i (
.clk (clk),
.reset_n (reset_n),
.enable_in (enable_in_d1 & mul0_div1_reg),
.numerator (x_mul),
.denominator (y_mul),
.enable_out (div_enable_out),
.quotient (q_i),
.remainder (r_i),
.div_by_zero (),
.error (ov)
);
endmodule |
module debug_reply (
input wire clk, // clock input
input wire reset_n, // reset, active low
input wire reply_enable_in,
input wire [`DBG_NUM_OF_OPERATIONS - 1 : 0] reply_debug_cmd,
input wire [`DEBUG_ACK_PAYLOAD_BITS - 1 : 0] reply_payload,
input wire uart_tx_done,
output reg ctl_start_uart_tx,
output wire [`DEBUG_DATA_WIDTH - 1 : 0] uart_data_out,
output reg reply_done
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [(`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * `DEBUG_DATA_WIDTH - 1 : 0] data_out_sr;
reg [$clog2(`DEBUG_FRAME_LENGTH + 1) - 1 : 0] data_counter;
reg ctl_reset_data_counter;
reg ctl_inc_data_counter;
reg ctl_crc_sync_reset;
wire [`DEBUG_DATA_WIDTH * 2 - 1 : 0] crc_out;
reg ctl_data_out_sr_shift;
reg ctl_crc_enable_in;
reg ctl_load_crc;
reg ctl_reply_done;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data_out_sr
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : data_out_sr_proc
if (!reset_n) begin
data_out_sr <= 0;
end else begin
if (reply_enable_in) begin
data_out_sr <= {`DEBUG_REPLY_SYNC, reply_payload};
end else if (ctl_load_crc) begin
data_out_sr [(`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * (`DEBUG_DATA_WIDTH) - 1: (`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * (`DEBUG_DATA_WIDTH) - 1 - 15] <= crc_out;
end else if (ctl_data_out_sr_shift) begin
data_out_sr <= {data_out_sr [(`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * (`DEBUG_DATA_WIDTH) - 1 - `DEBUG_DATA_WIDTH : 0], 8'd170};
end
end
end
assign uart_data_out = data_out_sr [(`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * `DEBUG_DATA_WIDTH - 1 : (`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN) * `DEBUG_DATA_WIDTH - 1 - `DEBUG_DATA_WIDTH + 1];
always @(posedge clk, negedge reset_n) begin : data_counter_proc
if (!reset_n) begin
data_counter <= 0;
end else if (ctl_reset_data_counter) begin
data_counter <= 0;
end else if (ctl_inc_data_counter) begin
data_counter <= data_counter + 1;
end
end
always @(posedge clk, negedge reset_n) begin : reply_done_proc
if (!reset_n) begin
reply_done <= 0;
end else begin
reply_done <= ctl_reply_done;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// CRC
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
crc16_CCITT crc16_CCITT_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (ctl_crc_sync_reset),
.crc_en (ctl_crc_enable_in),
.data_in (uart_data_out),
.crc_out (crc_out)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_TX_WITHOUT_CRC = 1, S_TX_WITHOUT_CRC_WAIT_DONE = 2, S_TX_CRC = 3, S_TX_CRC_DONE = 4;
reg [4:0] current_state = 0, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_reset_data_counter = 0;
ctl_inc_data_counter = 0;
ctl_start_uart_tx = 0;
ctl_data_out_sr_shift = 0;
ctl_crc_enable_in = 0;
ctl_crc_sync_reset = 0;
ctl_load_crc = 0;
ctl_reply_done = 0;
case (1'b1) // synthesis parallel_case
current_state [S_IDLE]: begin
if (reply_enable_in) begin
ctl_reset_data_counter = 1'b1;
next_state [S_TX_WITHOUT_CRC] = 1;
end else begin
ctl_crc_sync_reset = 1'b1;
next_state [S_IDLE] = 1;
end
end
current_state [S_TX_WITHOUT_CRC] : begin
if (data_counter == (`DEBUG_FRAME_LENGTH - `DEBUG_CRC_LEN)) begin
ctl_reset_data_counter = 1'b1;
ctl_load_crc = 1'b1;
next_state [S_TX_CRC] = 1;
end else begin
ctl_start_uart_tx = 1'b1;
ctl_crc_enable_in = 1'b1;
next_state [S_TX_WITHOUT_CRC_WAIT_DONE] = 1;
end
end
current_state [S_TX_WITHOUT_CRC_WAIT_DONE] : begin
if (uart_tx_done) begin
ctl_inc_data_counter = 1'b1;
ctl_data_out_sr_shift = 1'b1;
next_state [S_TX_WITHOUT_CRC] = 1;
end else begin
next_state [S_TX_WITHOUT_CRC_WAIT_DONE] = 1;
end
end
current_state [S_TX_CRC] : begin
if (data_counter == 2) begin
ctl_reply_done = 1'b1;
next_state [S_IDLE] = 1;
end else begin
ctl_start_uart_tx = 1'b1;
next_state [S_TX_CRC_DONE] = 1;
end
end
current_state [S_TX_CRC_DONE] : begin
if (uart_tx_done) begin
ctl_inc_data_counter = 1'b1;
ctl_data_out_sr_shift = 1'b1;
next_state [S_TX_CRC] = 1;
end else begin
next_state [S_TX_CRC_DONE] = 1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module crc16_CCITT #(parameter INIT_VALUE = 16'hFFFF) (
input wire clk,
input wire reset_n,
input wire sync_reset,
input wire crc_en,
input wire [7:0] data_in,
output wire [15:0] crc_out
);
reg [15:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[8] ^ lfsr_q[12] ^ data_in[0] ^ data_in[4];
lfsr_c[1] = lfsr_q[9] ^ lfsr_q[13] ^ data_in[1] ^ data_in[5];
lfsr_c[2] = lfsr_q[10] ^ lfsr_q[14] ^ data_in[2] ^ data_in[6];
lfsr_c[3] = lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];
lfsr_c[4] = lfsr_q[12] ^ data_in[4];
lfsr_c[5] = lfsr_q[8] ^ lfsr_q[12] ^ lfsr_q[13] ^ data_in[0] ^ data_in[4] ^ data_in[5];
lfsr_c[6] = lfsr_q[9] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[1] ^ data_in[5] ^ data_in[6];
lfsr_c[7] = lfsr_q[10] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[2] ^ data_in[6] ^ data_in[7];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[12] ^ data_in[4];
lfsr_c[10] = lfsr_q[2] ^ lfsr_q[13] ^ data_in[5];
lfsr_c[11] = lfsr_q[3] ^ lfsr_q[14] ^ data_in[6];
lfsr_c[12] = lfsr_q[4] ^ lfsr_q[8] ^ lfsr_q[12] ^ lfsr_q[15] ^ data_in[0] ^ data_in[4] ^ data_in[7];
lfsr_c[13] = lfsr_q[5] ^ lfsr_q[9] ^ lfsr_q[13] ^ data_in[1] ^ data_in[5];
lfsr_c[14] = lfsr_q[6] ^ lfsr_q[10] ^ lfsr_q[14] ^ data_in[2] ^ data_in[6];
lfsr_c[15] = lfsr_q[7] ^ lfsr_q[11] ^ lfsr_q[15] ^ data_in[3] ^ data_in[7];
end // always
always @(posedge clk, negedge reset_n) begin
if(!reset_n) begin
lfsr_q <= INIT_VALUE;
end else if (sync_reset) begin
lfsr_q <= INIT_VALUE;
end else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc16_CCITT |
module debug_coprocessor (
input wire clk, // clock input
input wire reset_n, // reset, active low
input wire enable_in,
input wire [`DEBUG_DATA_WIDTH - 1 : 0] debug_data_in,
output reg reply_enable_out,
output reg [`DBG_NUM_OF_OPERATIONS - 1 : 0] reply_debug_cmd,
output reg [`DEBUG_ACK_PAYLOAD_BITS - 1 : 0] reply_payload,
input wire reply_done,
input wire pram_read_enable_in,
input wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] pram_read_data_in,
output reg pram_read_enable_out,
output reg [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_read_addr_out,
output reg pram_write_enable_out,
output reg [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr_out,
output reg [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] pram_write_data_out,
output reg cpu_reset,
output reg cpu_start,
output reg [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr,
output reg debug_uart_tx_sel_ocd1_cpu0
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [1 : 0] enable_in_sr;
reg [`DEBUG_FRAME_LENGTH * `DEBUG_DATA_WIDTH - 1 : 0] data_in_sr;
wire [`DEBUG_DATA_WIDTH - 1 : 0] new_data_in;
reg [$clog2(`DEBUG_EXT_FRAME_LENGTH + 1) - 1 : 0] input_counter;
reg ctl_reset_input_counter;
reg ctl_crc_sync_reset;
wire [15 : 0] crc_out;
reg ctl_pram_write_enable;
reg ctl_pram_read_enable;
wire [`DEBUG_PRAM_ADDR_WIDTH - 1 : 0] pram_addr;
wire [`DEBUG_FRAME_DATA_LEN * `DEBUG_DATA_WIDTH - 1 : 0] pram_data;
wire [`DEBUG_DATA_WIDTH - 2 : 0] frame_type;
wire toggle_bit;
wire uart_sel_ocd1_cpu0;
reg ctl_reply_wr_ack;
reg ctl_reply_pram_read_back;
reg ctl_reply_data_mem_read_back;
reg ctl_cpu_reset;
reg [`DEBUG_CPU_RESET_LENGTH - 1 : 0] cpu_reset_sr;
reg ctl_run_pulse;
reg ctl_cpu_status_ack;
reg ctl_uart_sel;
reg [`DEBUG_PRAM_ADDR_WIDTH - 1 : 0] pram_addr_ext;
reg ctl_load_pram_addr_ext;
reg ctl_inc_pram_addr_ext;
reg wr_ext_enable;
reg ctl_wr_ext_disable;
reg ctl_wr_ext_enable;
reg ctl_config_start;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// shift registers
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : enable_in_sr_proc
if (!reset_n) begin
enable_in_sr <= 0;
data_in_sr <= 0;
end else if (enable_in) begin
enable_in_sr <= {enable_in_sr [0 : 0] , 1'b1};
data_in_sr <= {data_in_sr[`DEBUG_FRAME_LENGTH * `DEBUG_DATA_WIDTH - 1 - `DEBUG_DATA_WIDTH : 0], debug_data_in};
end else begin
enable_in_sr <= {enable_in_sr [0 : 0] , 1'b0};
end
end
assign new_data_in = data_in_sr [`DEBUG_DATA_WIDTH - 1 : 0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// CRC
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
crc16_CCITT crc16_CCITT_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (ctl_crc_sync_reset),
.crc_en (enable_in_sr[0]),
.data_in (new_data_in),
.crc_out (crc_out)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// start address
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : start_addr_proc
if (!reset_n) begin
cpu_start <= 0;
cpu_start_addr <= 0;
end else if (ctl_config_start) begin
cpu_start <= 1'b1;
cpu_start_addr <= pram_data;
end else begin
cpu_start <= 0;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// input_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : input_counter_proc
if (!reset_n) begin
input_counter <= 0;
end else if (ctl_reset_input_counter) begin
input_counter <= 0;
end else if (enable_in_sr[0]) begin
input_counter <= input_counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// CPU reset
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : cpu_reset_proc
if (!reset_n) begin
cpu_reset <= 0;
cpu_reset_sr <= 0;
end else begin
cpu_reset_sr <= {cpu_reset_sr [`DEBUG_CPU_RESET_LENGTH - 2 : 0], ctl_cpu_reset};
cpu_reset <= |cpu_reset_sr;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// debug_pram_write
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign pram_addr = data_in_sr [(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN + `DEBUG_FRAME_ADDR_LEN) * `DEBUG_DATA_WIDTH - 1 :
(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN) * `DEBUG_DATA_WIDTH];
assign pram_data = data_in_sr [(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN) * `DEBUG_DATA_WIDTH - 1 :
`DEBUG_CRC_LEN * `DEBUG_DATA_WIDTH];
assign uart_sel_ocd1_cpu0 = pram_data [1];
assign frame_type = data_in_sr [(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN + `DEBUG_FRAME_ADDR_LEN + `DEBUG_FRAME_TYPE_LEN) * `DEBUG_DATA_WIDTH - 1 :
(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN + `DEBUG_FRAME_ADDR_LEN ) * `DEBUG_DATA_WIDTH + 1];
assign toggle_bit = data_in_sr [(`DEBUG_FRAME_DATA_LEN + `DEBUG_CRC_LEN + `DEBUG_FRAME_ADDR_LEN ) * `DEBUG_DATA_WIDTH];
always @(posedge clk, negedge reset_n) begin : pram_write_proc
if (!reset_n) begin
pram_write_enable_out <= 0;
pram_write_addr_out <= 0;
pram_write_data_out <= 0;
end else begin
pram_write_enable_out <= ctl_pram_write_enable;
if (wr_ext_enable) begin
pram_write_addr_out <= pram_addr_ext [`DEBUG_PRAM_ADDR_WIDTH - 1 : 2];
end else begin
pram_write_addr_out <= pram_addr [`DEBUG_PRAM_ADDR_WIDTH - 1 : 2];
end
pram_write_data_out <= pram_data;
end
end
always @(posedge clk, negedge reset_n) begin : pram_read_proc
if (!reset_n) begin
pram_read_enable_out <= 0;
pram_read_addr_out <= 0;
end else begin
pram_read_enable_out <= ctl_pram_read_enable;
pram_read_addr_out <= pram_addr [`DEBUG_PRAM_ADDR_WIDTH - 1 : 2];
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// uart selection
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
debug_uart_tx_sel_ocd1_cpu0 <= 0;
end else if (ctl_uart_sel) begin
debug_uart_tx_sel_ocd1_cpu0 <= uart_sel_ocd1_cpu0;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Reply Acknowledge
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : reply_ack_proc
if (!reset_n) begin
reply_enable_out <= 0;
reply_debug_cmd <= 0;
reply_payload <= 0;
end else begin
reply_enable_out <= ctl_reply_wr_ack | ctl_reply_pram_read_back | ctl_cpu_status_ack | ctl_reply_data_mem_read_back;
case (1'b1) // synthesis parallel_case
ctl_reply_wr_ack : begin
reply_debug_cmd <= (1 << (`OP_DBG_ACK));
reply_payload <= {frame_type, toggle_bit, pram_addr, 32'hAAABACAD};
end
ctl_reply_pram_read_back : begin
reply_debug_cmd <= (1 << (`OP_READ_BACK_4_BYTES));
reply_payload <= {frame_type, toggle_bit, pram_addr, pram_read_data_in};
end
ctl_cpu_status_ack : begin
reply_debug_cmd <= (1 << `OP_CPU_STATUS_ACK);
reply_payload <= {frame_type, toggle_bit, 8'h0, 7'd59, 1'b0, 16'hBEEF, 16'hDEAD};
end
ctl_reply_data_mem_read_back : begin
reply_debug_cmd <= (1 << (`OP_DATA_MEM_READ));
reply_payload <= {frame_type, toggle_bit, 16'h999D, 24'hAABBCC, 8'hDC};
end
default : begin
reply_payload <= 0;
end
endcase
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// debug RAM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
pram_addr_ext <= 0;
end else if (ctl_load_pram_addr_ext) begin
pram_addr_ext <= pram_addr + 4;
end else if (ctl_inc_pram_addr_ext) begin
pram_addr_ext <= pram_addr_ext + 4;
end
end
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
wr_ext_enable <= 0;
end else if (ctl_wr_ext_disable) begin
wr_ext_enable <= 0;
end else if (ctl_wr_ext_enable) begin
wr_ext_enable <= 1'b1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_SYNC_1 = 1, S_SYNC_0 = 2, S_INPUT_WAIT = 3, S_FRAME_TYPE = 4, S_CRC = 5,
S_WR_ACK = 6, S_PRAM_READ_WAIT = 7, S_CPU_STATUS_ACK = 8,
S_WAIT_DONE = 9, S_WR_EXT = 10, S_EXT_CRC = 11;
reg [11 : 0] current_state = 0, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_reset_input_counter = 0;
ctl_crc_sync_reset = 0;
ctl_pram_write_enable = 0;
ctl_pram_read_enable = 0;
ctl_reply_wr_ack = 0;
ctl_reply_pram_read_back = 0;
ctl_cpu_reset = 0;
ctl_cpu_status_ack = 0;
ctl_reply_data_mem_read_back = 0;
ctl_uart_sel= 0;
ctl_load_pram_addr_ext = 0;
ctl_inc_pram_addr_ext = 0;
ctl_wr_ext_disable = 0;
ctl_wr_ext_enable = 0;
ctl_config_start = 0;
case (1'b1) // synthesis parallel_case
current_state[S_IDLE]: begin
ctl_wr_ext_disable = 1'b1;
if (enable_in_sr[0] && (new_data_in == `DEBUG_SYNC_2)) begin
next_state [S_SYNC_1] = 1;
end else begin
ctl_crc_sync_reset = 1'b1;
next_state [S_IDLE] = 1;
end
end
current_state [S_SYNC_1] : begin
if (enable_in_sr[0]) begin
if (new_data_in == `DEBUG_SYNC_1) begin
next_state [S_SYNC_0] = 1;
end else begin
next_state [S_IDLE] = 1;
end
end else begin
next_state [S_SYNC_1] = 1;
end
end
current_state [S_SYNC_0] : begin
ctl_reset_input_counter = 1;
if (enable_in_sr[0]) begin
if (new_data_in == `DEBUG_SYNC_0) begin
next_state [S_INPUT_WAIT] = 1;
end else begin
next_state [S_IDLE] = 1;
end
end else begin
next_state [S_SYNC_0] = 1;
end
end
current_state [S_INPUT_WAIT] : begin
if (input_counter == (`DEBUG_FRAME_LENGTH - `DEBUG_SYNC_LENGTH - 1)) begin
next_state [S_FRAME_TYPE] = 1;
end else begin
next_state [S_INPUT_WAIT] = 1;
end
end
current_state [S_FRAME_TYPE] : begin
ctl_reset_input_counter = 1'b1;
if (enable_in_sr[0]) begin
next_state [S_CRC] = 1;
end else begin
next_state [S_FRAME_TYPE] = 1;
end
end
current_state [S_CRC] : begin
ctl_load_pram_addr_ext = 1'b1;
if (!crc_out) begin
case (frame_type) // synthesis parallel_case
`DEBUG_TYPE_PRAM_WRITE_128_BYTES_WITH_ACK : begin
ctl_pram_write_enable = 1'b1;
ctl_crc_sync_reset = 1'b1;
next_state [S_WR_EXT] = 1;
end
`DEBUG_TYPE_PRAM_WRITE_4_BYTES_WITHOUT_ACK : begin
ctl_pram_write_enable = 1'b1;
next_state [S_IDLE] = 1;
end
`DEBUG_TYPE_PRAM_WRITE_4_BYTES_WITH_ACK : begin
ctl_pram_write_enable = 1'b1;
next_state [S_WR_ACK] = 1;
end
`DEBUG_TYPE_PRAM_READ_4_BYTES : begin
ctl_pram_read_enable = 1'b1;
next_state [S_PRAM_READ_WAIT] = 1;
end
`DEBUG_TYPE_CPU_RESET_WITH_ACK : begin
ctl_cpu_reset = 1'b1;
next_state [S_WR_ACK] = 1;
end
`DEBUG_TYPE_RUN_PULSE_WITH_ACK : begin
next_state [S_WR_ACK] = 1;
end
`DEBUG_TYPE_READ_CPU_STATUS : begin
next_state [S_CPU_STATUS_ACK] = 1;
end
`DEBUG_TYPE_COUNTER_CONFIG : begin
ctl_config_start = 1'b1;
next_state [S_WR_ACK] = 1;
end
`DEBUG_TYPE_UART_SEL : begin
ctl_uart_sel = 1'b1;
next_state [S_IDLE] = 1;
end
default : begin
next_state [S_IDLE] = 1;
end
endcase
end else begin
next_state [S_IDLE] = 1;
end
end
current_state [S_WR_ACK] : begin
ctl_crc_sync_reset = 1'b1;
ctl_reply_wr_ack = 1'b1;
next_state [S_WAIT_DONE] = 1;
end
current_state [S_CPU_STATUS_ACK] : begin
ctl_crc_sync_reset = 1'b1;
ctl_cpu_status_ack = 1'b1;
next_state [S_WAIT_DONE] = 1;
end
current_state [S_PRAM_READ_WAIT] : begin
ctl_crc_sync_reset = 1'b1;
if (!pram_read_enable_in) begin
next_state [S_PRAM_READ_WAIT] = 1;
end else begin
ctl_reply_pram_read_back = 1'b1;
next_state [S_WAIT_DONE] = 1;
end
end
current_state [S_WAIT_DONE] :begin
if (reply_done) begin
next_state [S_IDLE] = 1;
end else begin
next_state [S_WAIT_DONE] = 1;
end
end
current_state [S_WR_EXT] : begin
ctl_wr_ext_enable = 1'b1;
if (input_counter == (`DEBUG_EXT_FRAME_LENGTH - `DEBUG_FRAME_LENGTH)) begin
next_state [S_EXT_CRC] = 1;
end else begin
next_state [S_WR_EXT] = 1;
end
if (enable_in_sr[0] && (|input_counter[$clog2(`DEBUG_EXT_FRAME_LENGTH + 1) - 1 : 2]) && (input_counter [1:0] == 2'b01)) begin
ctl_pram_write_enable = 1'b1;
ctl_inc_pram_addr_ext = 1'b1;
end
end
current_state [S_EXT_CRC] : begin
if (!crc_out) begin
next_state [S_WR_ACK] = 1;
end else begin
next_state [S_IDLE] = 1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module debug_coprocessor_wrapper #(parameter BAUD_PERIOD=208) (
input wire clk,
input wire reset_n,
input wire RXD,
output wire TXD,
input wire pram_read_enable_in,
input wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] pram_read_data_in,
output wire pram_read_enable_out,
output wire [`DEBUG_PRAM_ADDR_WIDTH - 1 : 0] pram_read_addr_out,
output wire pram_write_enable_out,
output wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr_out,
output wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] pram_write_data_out,
output wire cpu_reset,
output wire cpu_start,
output wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr,
output wire debug_uart_tx_sel_ocd1_cpu0
);
wire [7 : 0] SBUF_out;
wire TI, RI;
wire reply_enable;
wire [`DBG_NUM_OF_OPERATIONS - 1 : 0] reply_debug_cmd;
wire [`DEBUG_ACK_PAYLOAD_BITS - 1 : 0] reply_payload;
wire TX_done_pulse;
wire ctl_start_uart_tx;
wire [7 : 0] SBUF_in;
wire reply_done;
debug_UART #(.BAUD_PERIOD (BAUD_PERIOD)) debug_UART_i (
.clk (clk),
.reset_n (reset_n),
.sync_reset (1'b0),
.UART_enable (1'b1),
.TX_enable_in (ctl_start_uart_tx),
.RXD (RXD),
.SBUF_in (SBUF_in),
.REN (1'b1),
.TXD (TXD),
.SBUF_out (SBUF_out),
.TX_done_pulse (TX_done_pulse),
.TI (TI),
.RI (RI));
debug_reply debug_reply_i (
.clk (clk),
.reset_n (reset_n),
.reply_enable_in (reply_enable),
.reply_debug_cmd (reply_debug_cmd),
.reply_payload (reply_payload),
.uart_tx_done (TX_done_pulse),
.ctl_start_uart_tx (ctl_start_uart_tx),
.uart_data_out (SBUF_in),
.reply_done (reply_done));
debug_coprocessor debug_coprocessor_i (
.clk (clk),
.reset_n (reset_n),
.enable_in (RI),
.debug_data_in (SBUF_out),
.reply_enable_out (reply_enable),
.reply_debug_cmd (reply_debug_cmd),
.reply_payload (reply_payload),
.reply_done (reply_done),
.pram_read_enable_in (pram_read_enable_in),
.pram_read_data_in (pram_read_data_in),
.pram_read_enable_out (pram_read_enable_out),
.pram_read_addr_out (pram_read_addr_out),
.pram_write_enable_out (pram_write_enable_out),
.pram_write_addr_out (pram_write_addr_out),
.pram_write_data_out (pram_write_data_out),
.cpu_reset (cpu_reset),
.cpu_start (cpu_start),
.cpu_start_addr (cpu_start_addr),
.debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0)
);
endmodule |
module Serial_RS232 #(parameter STABLE_TIME = `UART_STABLE_COUNT, MAX_BAUD_PERIOD = `UART_TX_BAUD_PERIOD) (
//=======================================================================
// clock / reset
//=======================================================================
input wire clk,
input wire reset_n,
//=======================================================================
// host interface
//=======================================================================
input wire start_TX,
input wire start_RX,
input wire class_8051_unit_pulse,
input wire timer_trigger,
input wire [7 : 0] SBUF_in,
input wire [2 : 0] SM,
input wire REN,
output reg [7 : 0] SBUF_out,
output reg TI, // TX interrupt
output reg RI, // RX interrupt
//=======================================================================
// device interface
//=======================================================================
input wire RXD,
output wire TXD
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg sync_reset;
reg [2 : 0] SM_d1;
reg [2 : 0] rxd_sr;
reg [$clog2(STABLE_TIME + 1) - 1 : 0] stable_counter;
reg baud_rate_pulse;
reg [$clog2(MAX_BAUD_PERIOD) - 1 : 0] counter, counter_save;
reg ctl_reset_stable_counter;
reg ctl_save_counter;
reg [$clog2 (8 + 4) - 1 : 0] data_counter;
reg ctl_reset_data_counter;
reg ctl_inc_data_counter;
reg [10 : 0] tx_data;
reg ctl_load_tx_data;
reg ctl_shift_tx_data;
reg ctl_set_TI;
reg ctl_set_RI;
reg ctl_shift_rx_data;
reg ctl_counter_reset;
reg tx_start_flag;
reg ctl_set_tx_start_flag;
reg ctl_clear_tx_start_flag;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// sync reset
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : sync_reset_proc
if (!reset_n) begin
SM_d1 <= 0;
sync_reset <= 0;
end else begin
SM_d1 <= SM;
if (SM_d1 != SM) begin
sync_reset <= 1'b1;
end else begin
sync_reset <= 0;
end
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// TI / RI
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : TI_proc
if (!reset_n) begin
TI <= 0;
end else if (ctl_set_TI) begin
TI <= 1'b1;
end else if (start_TX) begin
TI <= 0;
end
end
always @(posedge clk, negedge reset_n) begin : RI_proc
if (!reset_n) begin
RI <= 0;
end else if (ctl_set_RI) begin
RI <= 1'b1;
end else if (start_RX) begin
RI <= 0;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// baud_rate_pulse
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : baud_rate_pulse_proc
if (!reset_n) begin
baud_rate_pulse <= 0;
end else if (sync_reset) begin
baud_rate_pulse <= 0;
end else begin
baud_rate_pulse <= timer_trigger;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// tx_data
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : tx_data_proc
if (!reset_n) begin
tx_data <= 0;
end else if (ctl_load_tx_data) begin
tx_data <= {1'b1, SBUF_in, 2'b01};
end else if (ctl_shift_tx_data) begin
tx_data <= {1'b1, tx_data [10 : 1]};
end
end
assign TXD = tx_data [0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// rx_data
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : SBUF_out_proc
if (!reset_n) begin
SBUF_out <= 0;
end else if (ctl_shift_rx_data) begin
SBUF_out <= {rxd_sr[2], SBUF_out [7 : 1]};
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// rxd_sr
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : rxd_sr_proc
if (!reset_n) begin
rxd_sr <= 0;
end else begin
rxd_sr <= {rxd_sr [2 - 1 : 0] , RXD};
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : counter_proc
if (!reset_n) begin
counter <= 0;
end else if (sync_reset | ctl_counter_reset) begin
counter <= 0;
end else if (baud_rate_pulse) begin
counter <= 0;
end else begin
counter <= counter + 1;
end
end
always @(posedge clk, negedge reset_n) begin : counter_save_proc
if (!reset_n) begin
counter_save <= 0;
end else if (sync_reset | ctl_counter_reset) begin
counter_save <= 0;
end else if (ctl_save_counter) begin
counter_save <= counter;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// data_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : data_counter_proc
if (!reset_n) begin
data_counter <= 0;
end else if (ctl_reset_data_counter) begin
data_counter <= 0;
end else if (ctl_inc_data_counter) begin
data_counter <= data_counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// stable_counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : stable_counter_proc
if (!reset_n) begin
stable_counter <= 0;
end else if (ctl_reset_stable_counter) begin
stable_counter <= 0;
end else begin
stable_counter <= stable_counter + 1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// tx_start_flag
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : tx_start_flag_proc
if (!reset_n) begin
tx_start_flag <= 0;
end else if (ctl_clear_tx_start_flag) begin
tx_start_flag <= 0;
end else if (ctl_set_tx_start_flag) begin
tx_start_flag <= 1'b1;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_IDLE = 0, S_RX_START = 1, S_TX_START = 2, S_RX_START_BIT = 3, S_RX_DATA = 4,
S_TX_DATA = 5, S_RX_STOP_BIT = 6, S_TX_WAIT = 7, S_TX_WAIT2 = 8;
reg [8:0] current_state = 0, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else if (sync_reset) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_reset_stable_counter = 0;
ctl_save_counter = 0;
ctl_reset_data_counter = 0;
ctl_inc_data_counter = 0;
ctl_load_tx_data = 0;
ctl_shift_tx_data = 0;
ctl_shift_rx_data = 0;
ctl_set_TI = 0;
ctl_set_RI = 0;
ctl_counter_reset = 0;
ctl_set_tx_start_flag = 0;
ctl_clear_tx_start_flag = 0;
case (1'b1) // synthesis parallel_case
current_state[S_IDLE]: begin
ctl_load_tx_data = 1'b1;
ctl_reset_data_counter = 1'b1;
ctl_counter_reset = 1'b1;
ctl_clear_tx_start_flag = 1'b1;
if (REN) begin
if (start_RX) begin
next_state [S_RX_START] = 1'b1;
end else begin
next_state [S_IDLE] = 1'b1;
end
end else if (start_TX) begin
next_state [S_TX_START] = 1'b1;
end else begin
next_state [S_IDLE] = 1'b1;
end
end
current_state [S_TX_START] : begin
ctl_reset_data_counter = 1'b1;
if (REN) begin
next_state [S_RX_START] = 1'b1;
end else if (baud_rate_pulse) begin
if (tx_start_flag) begin
ctl_shift_tx_data = 1'b1;
next_state [S_TX_DATA] = 1'b1;
end else begin
ctl_set_tx_start_flag = 1'b1;
ctl_load_tx_data = 1'b1;
next_state [S_TX_START] = 1'b1;
end
end else begin
ctl_load_tx_data = 1'b1;
next_state [S_TX_START] = 1'b1;
end
end
current_state [S_TX_DATA] : begin
if (data_counter == (8 + 3)) begin
ctl_set_TI = 1'b1;
next_state [S_IDLE] = 1;
//ctl_load_tx_data = 1'b1;
//next_state [S_TX_WAIT] = 1;
end else if (baud_rate_pulse) begin
ctl_shift_tx_data = 1'b1;
ctl_inc_data_counter = 1'b1;
next_state [S_TX_DATA] = 1;
end else begin
next_state [S_TX_DATA] = 1;
end
end
current_state [S_TX_WAIT] : begin
ctl_load_tx_data = 1'b1;
if (baud_rate_pulse) begin
next_state [S_TX_WAIT2] = 1;
end else begin
next_state [S_TX_WAIT] = 1;
end
end
current_state [S_TX_WAIT2] : begin
if (baud_rate_pulse) begin
ctl_set_TI = 1'b1;
next_state [S_IDLE] = 1;
end else begin
ctl_load_tx_data = 1'b1;
next_state [S_TX_WAIT2] = 1;
end
end
current_state [S_RX_START] : begin
ctl_reset_stable_counter = 1'b1;
ctl_clear_tx_start_flag = 1'b1;
if (!REN) begin
next_state [S_TX_START] = 1'b1;
end else if (rxd_sr[2] & (~rxd_sr[1])) begin
next_state [S_RX_START_BIT] = 1'b1;
end else begin
next_state [S_RX_START] = 1'b1;
end
end
current_state [S_RX_START_BIT] : begin
if (!rxd_sr[2]) begin
if (stable_counter == STABLE_TIME) begin
ctl_save_counter = 1'b1;
ctl_reset_data_counter = 0;
next_state [S_RX_DATA] = 1;
end else begin
next_state [S_RX_START_BIT] = 1;
end
end else begin
next_state [S_RX_START] = 1'b1;
end
end
current_state [S_RX_DATA] : begin
if (counter == counter_save) begin
ctl_inc_data_counter = 1'b1;
ctl_shift_rx_data = 1'b1;
end
if (data_counter == 8) begin
next_state [S_RX_STOP_BIT] = 1'b1;
end else begin
next_state [S_RX_DATA] = 1;
end
end
current_state [S_RX_STOP_BIT] : begin
if (counter == counter_save) begin
ctl_set_RI = 1'b1;
next_state [S_IDLE] = 1;
end else begin
next_state [S_RX_STOP_BIT] = 1;
end
end
default: begin
next_state[S_IDLE] = 1'b1;
end
endcase
end
endmodule |
module debug_UART #(parameter BAUD_PERIOD = `UART_TX_BAUD_PERIOD) (
input wire clk,
input wire reset_n,
input wire sync_reset,
input wire UART_enable,
input wire TX_enable_in,
input wire RXD,
input wire [`DEBUG_DATA_WIDTH - 1 : 0] SBUF_in,
input wire REN,
output wire TXD,
output wire [`DEBUG_DATA_WIDTH - 1 : 0] SBUF_out,
output reg TX_done_pulse,
output wire TI,
output wire RI
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
reg [$clog2(BAUD_PERIOD + 1) - 1 : 0] baud_counter;
wire baud_pulse;
reg ctl_uart_rx_enable;
reg ctl_uart_tx_start;
reg ctl_tx_done;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// baud counter
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : baud_counter_proc
if (!reset_n) begin
baud_counter <= 0;
end else if (sync_reset) begin
baud_counter <= 0;
end else if (UART_enable) begin
if (baud_counter == (BAUD_PERIOD - 1)) begin
baud_counter <= 0;
end else begin
baud_counter <= baud_counter + 1;
end
end
end
assign baud_pulse = (baud_counter == (BAUD_PERIOD - 1)) ? 1'b1 : 1'b0;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// UART
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Serial_RS232 #(.STABLE_TIME (100),
.MAX_BAUD_PERIOD (10000))
UART_i (
.clk (clk),
.reset_n (reset_n),
.start_TX (ctl_uart_tx_start),
.start_RX (ctl_uart_rx_enable),
.class_8051_unit_pulse (1'b0),
.timer_trigger (baud_pulse),
.RXD (RXD),
.SBUF_in (SBUF_in),
.SM (3'b011),
.REN (REN & ctl_uart_rx_enable),
.TXD (TXD),
.TI (TI),
.RI (RI),
.SBUF_out (SBUF_out));
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// TX Done
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk, negedge reset_n) begin : TX_done_pulse_proc
if (!reset_n) begin
TX_done_pulse <= 0;
end else begin
TX_done_pulse <= ctl_tx_done;
end
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam S_RX = 0, S_TX = 1;
reg [1:0] current_state = 0, next_state;
// Declare states
always @(posedge clk, negedge reset_n) begin : state_machine_reg
if (!reset_n) begin
current_state <= 0;
end else begin
current_state <= next_state;
end
end
// FSM main body
always @(*) begin : state_machine_comb
next_state = 0;
ctl_uart_rx_enable = 0;
ctl_uart_tx_start = 0;
ctl_tx_done = 0;
case (1'b1) // synthesis parallel_case
current_state[S_RX]: begin
if (TX_enable_in) begin
ctl_uart_tx_start = 1'b1;
next_state [S_TX] = 1;
end else begin
ctl_uart_rx_enable = 1'b1;
next_state [S_RX] = 1;
end
end
current_state [S_TX] : begin
if (TI) begin
ctl_tx_done = 1'b1;
next_state [S_RX] = 1;
end else begin
next_state [S_TX] = 1;
end
end
default: begin
next_state[S_RX] = 1'b1;
end
endcase
end
endmodule |
module creative(
// Inputs
RXD,
osc_in,
// Outputs
LED_GREEN,
LED_RED,
TXD
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input RXD;
input osc_in;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output LED_GREEN;
output LED_RED;
output TXD;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire FCCC_0_GL0;
wire FCCC_0_LOCK;
wire LED_GREEN_net_0;
wire LED_RED_net_0;
wire osc_in;
wire RXD;
wire TXD_net_0;
wire LED_GREEN_net_1;
wire LED_RED_net_1;
wire TXD_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [7:2]PADDR_const_net_0;
wire [7:0]PWDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign PADDR_const_net_0 = 6'h00;
assign PWDATA_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign LED_GREEN_net_1 = LED_GREEN_net_0;
assign LED_GREEN = LED_GREEN_net_1;
assign LED_RED_net_1 = LED_RED_net_0;
assign LED_RED = LED_RED_net_1;
assign TXD_net_1 = TXD_net_0;
assign TXD = TXD_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------creative_FCCC_0_FCCC - Actel:SgCore:FCCC:2.0.201
creative_FCCC_0_FCCC FCCC_0(
// Inputs
.CLK0_PAD ( osc_in ),
// Outputs
.GL0 ( FCCC_0_GL0 ),
.LOCK ( FCCC_0_LOCK )
);
//--------Reindeer
Reindeer Reindeer_0(
// Inputs
.clk ( FCCC_0_GL0 ),
.reset_n ( FCCC_0_LOCK ),
.RXD ( RXD ),
// Outputs
.TXD ( TXD_net_0 ),
.processor_active ( LED_GREEN_net_0 ),
.processor_paused ( LED_RED_net_0 )
);
endmodule |
module Reindeer (
//=====================================================================
// clock and reset
//=====================================================================
input wire clk,
input wire reset_n,
//=====================================================================
// UART
//=====================================================================
output reg TXD,
input wire RXD,
//=====================================================================
// status
//=====================================================================
output wire processor_active,
output wire processor_paused
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire debug_uart_tx_sel_ocd1_cpu0;
wire cpu_reset;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_read_addr;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr;
wire ocd_read_enable;
wire ocd_write_enable;
wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr;
wire [`XLEN - 1 : 0] ocd_write_word;
wire ocd_mem_enable_out;
wire [`XLEN - 1 : 0] ocd_mem_word_out;
wire cpu_start;
wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr;
wire uart_tx_cpu;
wire uart_tx_ocd;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// MCU
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
.clk (clk),
.reset_n ((~cpu_reset) & reset_n),
.sync_reset (1'b0),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.ocd_mem_enable_out (ocd_mem_enable_out),
.ocd_mem_word_out (ocd_mem_word_out),
.ocd_reg_read_addr (5'd2),
.ocd_reg_we (1'b0),
.ocd_reg_write_addr (5'd2),
.ocd_reg_write_data (32'h80007F00),
.TXD (uart_tx_cpu),
.start (cpu_start),
.start_address (cpu_start_addr),
.processor_paused (processor_paused),
.peek_pc (),
.peek_ir () );
assign processor_active = ~processor_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// OCD
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
.clk (clk),
.reset_n (reset_n),
.RXD (RXD),
.TXD (uart_tx_ocd),
.pram_read_enable_in (ocd_mem_enable_out),
.pram_read_data_in (ocd_mem_word_out),
.pram_read_enable_out (ocd_read_enable),
.pram_read_addr_out (pram_read_addr),
.pram_write_enable_out (ocd_write_enable),
.pram_write_addr_out (pram_write_addr),
.pram_write_data_out (ocd_write_word),
.cpu_reset (cpu_reset),
.cpu_start (cpu_start),
.cpu_start_addr (cpu_start_addr),
.debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
always @(posedge clk, negedge reset_n) begin : uart_proc
if (!reset_n) begin
TXD <= 0;
end else if (!debug_uart_tx_sel_ocd1_cpu0) begin
TXD <= uart_tx_cpu;
end else begin
TXD <= uart_tx_ocd;
end
end
endmodule |
module Reindeer (
//=====================================================================
// clock and reset
//=====================================================================
input wire osc_in,
input wire reset_btn,
//=====================================================================
// UART
//=====================================================================
output reg TXD,
input wire RXD,
//=====================================================================
// status
//=====================================================================
output wire REDn, // Red
output wire BLUn, // Blue
output wire GRNn // Green
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire clk;
wire pll_locked;
wire processor_paused;
wire processor_active;
wire debug_uart_tx_sel_ocd1_cpu0;
wire cpu_reset;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_read_addr;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr;
wire ocd_read_enable;
wire ocd_write_enable;
wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr;
wire [`XLEN - 1 : 0] ocd_write_word;
wire ocd_mem_enable_out;
wire [`XLEN - 1 : 0] ocd_mem_word_out;
wire cpu_start;
wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr;
wire uart_tx_cpu;
wire uart_tx_ocd;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// PLL and clock control block
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PLL PLL_i (
.CLKI (osc_in),
.RST (reset_btn),
.CLKOP (clk),
.LOCK (pll_locked));
assign REDn = processor_paused;
assign BLUn = processor_active;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// UART
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// MCU
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
.clk (clk),
.reset_n ((~cpu_reset) & pll_locked),
.sync_reset (1'b0),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.ocd_mem_enable_out (ocd_mem_enable_out),
.ocd_mem_word_out (ocd_mem_word_out),
.ocd_reg_read_addr (5'd2),
.ocd_reg_we (cpu_start),
.ocd_reg_write_addr (5'd2),
.ocd_reg_write_data (`DEFAULT_STACK_ADDR),
.TXD (uart_tx_cpu),
.start (cpu_start),
.start_address (cpu_start_addr),
.processor_paused (processor_paused),
.peek_pc (),
.peek_ir (),
.peek_mem_write_en (),
.peek_mem_write_data (),
.peek_mem_addr ()
);
assign processor_active = ~processor_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// OCD
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
.clk (clk),
.reset_n (pll_locked),
.RXD (RXD),
.TXD (uart_tx_ocd),
.pram_read_enable_in (ocd_mem_enable_out),
.pram_read_data_in (ocd_mem_word_out),
.pram_read_enable_out (ocd_read_enable),
.pram_read_addr_out (pram_read_addr),
.pram_write_enable_out (ocd_write_enable),
.pram_write_addr_out (pram_write_addr),
.pram_write_data_out (ocd_write_word),
.cpu_reset (cpu_reset),
.cpu_start (cpu_start),
.cpu_start_addr (cpu_start_addr),
.debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
always @(posedge clk, negedge pll_locked) begin : uart_proc
if (!pll_locked) begin
TXD <= 0;
end else if (!debug_uart_tx_sel_ocd1_cpu0) begin
TXD <= uart_tx_cpu;
end else begin
TXD <= uart_tx_ocd;
end
end
endmodule |
module Reindeer (
//=====================================================================
// clock and reset
//=====================================================================
//=====================================================================
// UART
//=====================================================================
output wire spi_ss,
output reg TXD,
input wire RXD,
//=====================================================================
// status
//=====================================================================
output wire REDn, // Red
output wire BLUn, // Blue
output wire GRNn // Green
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire clk;
wire processor_paused;
wire processor_active;
wire debug_uart_tx_sel_ocd1_cpu0;
wire cpu_reset;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_read_addr;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr;
wire ocd_read_enable;
wire ocd_write_enable;
wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr;
wire [`XLEN - 1 : 0] ocd_write_word;
wire ocd_mem_enable_out;
wire [`XLEN - 1 : 0] ocd_mem_word_out;
wire cpu_start;
wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr;
wire uart_tx_cpu;
wire uart_tx_ocd;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// CLOCK
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
HSOSC #(
.CLKHF_DIV ("0b10")
) osc_i (
.CLKHFPU (1'b1),
.CLKHFEN (1'b1),
.CLKHF (clk)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// LED
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
RGB #(
.RGB0_CURRENT ("0b000001"),
.RGB1_CURRENT ("0b000001"),
.RGB2_CURRENT ("0b000001") )
rbg_i (
.CURREN (1'b1),
.RGBLEDEN (1'b1),
.RGB0PWM (processor_active),
.RGB1PWM (1'b0),
.RGB2PWM (processor_paused),
.RGB0 (GRNn),
.RGB1 (BLUn),
.RGB2 (REDn)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// UART
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
assign spi_ss = 1'b1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// MCU
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
.clk (clk),
.reset_n (~cpu_reset),
.sync_reset (1'b0),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.ocd_mem_enable_out (ocd_mem_enable_out),
.ocd_mem_word_out (ocd_mem_word_out),
.ocd_reg_read_addr (5'd2),
.ocd_reg_we (cpu_start),
.ocd_reg_write_addr (5'd2),
.ocd_reg_write_data (`DEFAULT_STACK_ADDR),
.TXD (uart_tx_cpu),
.start (cpu_start),
.start_address (cpu_start_addr),
.processor_paused (processor_paused),
.peek_pc (),
.peek_ir (),
.peek_mem_write_en (),
.peek_mem_write_data (),
.peek_mem_addr ()
);
assign processor_active = ~processor_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// OCD
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
.clk (clk),
.reset_n (1'b1),
.RXD (RXD),
.TXD (uart_tx_ocd),
.pram_read_enable_in (ocd_mem_enable_out),
.pram_read_data_in (ocd_mem_word_out),
.pram_read_enable_out (ocd_read_enable),
.pram_read_addr_out (pram_read_addr),
.pram_write_enable_out (ocd_write_enable),
.pram_write_addr_out (pram_write_addr),
.pram_write_data_out (ocd_write_word),
.cpu_reset (cpu_reset),
.cpu_start (cpu_start),
.cpu_start_addr (cpu_start_addr),
.debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
always @(posedge clk) begin : uart_proc
if (!debug_uart_tx_sel_ocd1_cpu0) begin
TXD <= uart_tx_cpu;
end else begin
TXD <= uart_tx_ocd;
end
end
endmodule |
module Reindeer (
//=====================================================================
// clock and reset
//=====================================================================
input wire osc_in,
input wire reset_button,
//=====================================================================
// UART
//=====================================================================
output reg TXD,
input wire RXD,
//=====================================================================
// status
//=====================================================================
output wire processor_active
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signal
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire debug_uart_tx_sel_ocd1_cpu0;
wire cpu_reset;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_read_addr;
wire [`DEBUG_PRAM_ADDR_WIDTH - 3 : 0] pram_write_addr;
wire ocd_read_enable;
wire ocd_write_enable;
wire [`MEM_ADDR_BITS - 1 : 0] ocd_rw_addr;
wire [`XLEN - 1 : 0] ocd_write_word;
wire ocd_mem_enable_out;
wire [`XLEN - 1 : 0] ocd_mem_word_out;
wire cpu_start;
wire [`DEBUG_DATA_WIDTH * `DEBUG_FRAME_DATA_LEN - 1 : 0] cpu_start_addr;
wire uart_tx_cpu;
wire uart_tx_ocd;
wire clk_24MHz;
wire clk_2MHz;
wire clk;
wire pll_locked;
wire processor_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// PLL and clock control block
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PLL PLL_i (
.areset (1'b0),
.inclk0 (osc_in),
.c0 (clk),
.c1 (clk_24MHz),
.c2 (clk_2MHz),
.locked (pll_locked));
/* PLL Pll_lattice_i (
.ref_clk_i (osc_in),
.rst_n_i (reset_button),
.lock_o (pll_locked),
.outcore_o (),
.outglobal_o (clk));
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// MCU
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
PulseRain_RV2T_MCU PulseRain_RV2T_MCU_i (
.clk (clk),
.reset_n ((~cpu_reset) & pll_locked),
.sync_reset (1'b0),
.ocd_read_enable (ocd_read_enable),
.ocd_write_enable (ocd_write_enable),
.ocd_rw_addr (ocd_rw_addr),
.ocd_write_word (ocd_write_word),
.ocd_mem_enable_out (ocd_mem_enable_out),
.ocd_mem_word_out (ocd_mem_word_out),
.ocd_reg_read_addr (5'd2),
.ocd_reg_we (1'b0),
.ocd_reg_write_addr (5'd2),
.ocd_reg_write_data (`DEFAULT_STACK_ADDR),
.TXD (uart_tx_cpu),
.start (cpu_start),
.start_address (cpu_start_addr),
.processor_paused (processor_paused),
.peek_pc (),
.peek_ir () );
assign processor_active = ~processor_paused;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// OCD
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate
if (`DISABLE_OCD == 0) begin
debug_coprocessor_wrapper #(.BAUD_PERIOD (`UART_TX_BAUD_PERIOD)) ocd_i (
.clk (clk),
.reset_n (pll_locked),
.RXD (RXD),
.TXD (uart_tx_ocd),
.pram_read_enable_in (ocd_mem_enable_out),
.pram_read_data_in (ocd_mem_word_out),
.pram_read_enable_out (ocd_read_enable),
.pram_read_addr_out (pram_read_addr),
.pram_write_enable_out (ocd_write_enable),
.pram_write_addr_out (pram_write_addr),
.pram_write_data_out (ocd_write_word),
.cpu_reset (cpu_reset),
.cpu_start (cpu_start),
.cpu_start_addr (cpu_start_addr),
.debug_uart_tx_sel_ocd1_cpu0 (debug_uart_tx_sel_ocd1_cpu0));
assign ocd_rw_addr = ocd_read_enable ? pram_read_addr : pram_write_addr;
end
endgenerate
always @(posedge clk, negedge pll_locked) begin : uart_proc
if (!pll_locked) begin
TXD <= 0;
end else if (!debug_uart_tx_sel_ocd1_cpu0) begin
TXD <= uart_tx_cpu;
end else begin
TXD <= uart_tx_ocd;
end
end
wire [127 : 0] acq_data_in;
assign acq_data_in [0] = debug_uart_tx_sel_ocd1_cpu0;
assign acq_data_in [1] = cpu_reset;
assign acq_data_in [2] = cpu_start;
assign acq_data_in [3] = pll_locked;
assign acq_data_in [35 : 4] = cpu_start_addr;
assign acq_data_in [36] = ocd_write_enable;
assign acq_data_in [37] = ocd_read_enable;
assign acq_data_in [51 : 38] = pram_write_addr;
assign acq_data_in [83 : 52] = ocd_write_word;
assign acq_data_in [97 : 84] = pram_read_addr;
assign acq_data_in [127 : 98] = ocd_mem_word_out [29 : 0];
/*
ocd_sigtap ocd_sigtap_i (
.acq_clk (clk),
.acq_data_in (acq_data_in),
.acq_trigger_in ({ocd_write_enable, cpu_start, cpu_reset, debug_uart_tx_sel_ocd1_cpu0})
);
*/
endmodule |
module ct_clint_top(
apb_clk_en,
ciu_clint_icg_en,
clint_core0_ms_int,
clint_core0_mt_int,
clint_core0_ss_int,
clint_core0_st_int,
clint_core1_ms_int,
clint_core1_mt_int,
clint_core1_ss_int,
clint_core1_st_int,
cpurst_b,
forever_apbclk,
forever_cpuclk,
pad_yy_icg_scan_en,
paddr,
penable,
perr_clint,
pprot,
prdata_clint,
pready_clint,
psel_clint,
pwdata,
pwrite,
sysio_clint_mtime
);
// &Ports; @25
input apb_clk_en;
input ciu_clint_icg_en;
input cpurst_b;
input forever_apbclk;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [31:0] paddr;
input penable;
input [1 :0] pprot;
input psel_clint;
input [31:0] pwdata;
input pwrite;
input [63:0] sysio_clint_mtime;
output clint_core0_ms_int;
output clint_core0_mt_int;
output clint_core0_ss_int;
output clint_core0_st_int;
output clint_core1_ms_int;
output clint_core1_mt_int;
output clint_core1_ss_int;
output clint_core1_st_int;
output perr_clint;
output [31:0] prdata_clint;
output pready_clint;
// &Regs; @26
// &Wires; @27
wire apb_clk_en;
wire ciu_clint_icg_en;
wire clint_core0_ms_int;
wire clint_core0_mt_int;
wire clint_core0_ss_int;
wire clint_core0_st_int;
wire clint_core1_ms_int;
wire clint_core1_mt_int;
wire clint_core1_ss_int;
wire clint_core1_st_int;
wire cpurst_b;
wire forever_apbclk;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire [31:0] paddr;
wire penable;
wire perr_clint;
wire [1 :0] pprot;
wire [31:0] prdata_clint;
wire pready_clint;
wire psel_clint;
wire [31:0] pwdata;
wire pwrite;
wire [63:0] sysio_clint_mtime;
//==========================================================
// Instance clint func
//==========================================================
// &Instance("ct_clint_func"); @32
ct_clint_func x_ct_clint_func (
.apb_clk_en (apb_clk_en ),
.ciu_clint_icg_en (ciu_clint_icg_en ),
.clint_core0_ms_int (clint_core0_ms_int),
.clint_core0_mt_int (clint_core0_mt_int),
.clint_core0_ss_int (clint_core0_ss_int),
.clint_core0_st_int (clint_core0_st_int),
.clint_core1_ms_int (clint_core1_ms_int),
.clint_core1_mt_int (clint_core1_mt_int),
.clint_core1_ss_int (clint_core1_ss_int),
.clint_core1_st_int (clint_core1_st_int),
.cpurst_b (cpurst_b ),
.forever_apbclk (forever_apbclk ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en),
.paddr (paddr ),
.penable (penable ),
.perr_clint (perr_clint ),
.pprot (pprot ),
.prdata_clint (prdata_clint ),
.pready_clint (pready_clint ),
.psel_clint (psel_clint ),
.pwdata (pwdata ),
.pwrite (pwrite ),
.sysio_clint_mtime (sysio_clint_mtime )
);
// &ModuleEnd; @35
endmodule |
module ct_l2c_sub_bank(
ciu_l2c_addr_vld_x,
ciu_l2c_addr_x,
ciu_l2c_clr_cp_x,
ciu_l2c_ctcq_req_x,
ciu_l2c_data_acc_cycle,
ciu_l2c_data_setup,
ciu_l2c_data_vld_x,
ciu_l2c_dca_addr_x,
ciu_l2c_dca_req_x,
ciu_l2c_hpcp_bus_x,
ciu_l2c_icc_mid_x,
ciu_l2c_icc_type_x,
ciu_l2c_mid_x,
ciu_l2c_rdl_ready_x,
ciu_l2c_rst_req,
ciu_l2c_set_cp_x,
ciu_l2c_sid_x,
ciu_l2c_snpl2_ready_x,
ciu_l2c_src_x,
ciu_l2c_tag_acc_cycle,
ciu_l2c_tag_setup,
ciu_l2c_type_x,
ciu_l2c_wdata_x,
cmp_pref_addr_x,
cmp_pref_cache_miss_x,
cmp_pref_ifu_req_x,
cmp_pref_read_x,
cmp_pref_tlb_req_x,
cmp_pref_vld_x,
cpurst_b,
forever_cpuclk,
l2c_ciu_addr_ready_x,
l2c_ciu_cmplt_x,
l2c_ciu_cp_x,
l2c_ciu_ctcq_cmplt_x,
l2c_ciu_ctcq_ready_x,
l2c_ciu_data_ready_gate_x,
l2c_ciu_data_ready_x,
l2c_ciu_data_x,
l2c_ciu_dca_cmplt_x,
l2c_ciu_dca_data_x,
l2c_ciu_dca_ready_x,
l2c_ciu_hpcp_acc_inc_x,
l2c_ciu_hpcp_mid_x,
l2c_ciu_hpcp_miss_inc_x,
l2c_ciu_rdl_addr_x,
l2c_ciu_rdl_dvld_x,
l2c_ciu_rdl_mid_x,
l2c_ciu_rdl_prot_x,
l2c_ciu_rdl_rvld_x,
l2c_ciu_resp_x,
l2c_ciu_sid_x,
l2c_ciu_snpl2_addr_x,
l2c_ciu_snpl2_ini_sid_x,
l2c_ciu_snpl2_vld_x,
l2c_data_clk_x,
l2c_data_ram_clk_en_x,
l2c_dbg_info_x,
l2c_flush_done_x,
l2c_flush_req_x,
l2c_icg_en,
l2c_no_op_x,
l2c_tag_clk_x,
l2c_tag_ram_clk_en_x,
pad_yy_icg_scan_en
);
// &Ports; @23
input ciu_l2c_addr_vld_x;
input [32 :0] ciu_l2c_addr_x;
input [3 :0] ciu_l2c_clr_cp_x;
input ciu_l2c_ctcq_req_x;
input [3 :0] ciu_l2c_data_acc_cycle;
input ciu_l2c_data_setup;
input ciu_l2c_data_vld_x;
input [32 :0] ciu_l2c_dca_addr_x;
input ciu_l2c_dca_req_x;
input [2 :0] ciu_l2c_hpcp_bus_x;
input [2 :0] ciu_l2c_icc_mid_x;
input [1 :0] ciu_l2c_icc_type_x;
input [2 :0] ciu_l2c_mid_x;
input ciu_l2c_rdl_ready_x;
input ciu_l2c_rst_req;
input [3 :0] ciu_l2c_set_cp_x;
input [4 :0] ciu_l2c_sid_x;
input ciu_l2c_snpl2_ready_x;
input [1 :0] ciu_l2c_src_x;
input [2 :0] ciu_l2c_tag_acc_cycle;
input ciu_l2c_tag_setup;
input [12 :0] ciu_l2c_type_x;
input [511:0] ciu_l2c_wdata_x;
input cpurst_b;
input forever_cpuclk;
input l2c_data_clk_x;
input l2c_flush_req_x;
input l2c_icg_en;
input l2c_tag_clk_x;
input pad_yy_icg_scan_en;
output [32 :0] cmp_pref_addr_x;
output cmp_pref_cache_miss_x;
output cmp_pref_ifu_req_x;
output cmp_pref_read_x;
output cmp_pref_tlb_req_x;
output cmp_pref_vld_x;
output l2c_ciu_addr_ready_x;
output l2c_ciu_cmplt_x;
output [3 :0] l2c_ciu_cp_x;
output l2c_ciu_ctcq_cmplt_x;
output l2c_ciu_ctcq_ready_x;
output l2c_ciu_data_ready_gate_x;
output l2c_ciu_data_ready_x;
output [511:0] l2c_ciu_data_x;
output l2c_ciu_dca_cmplt_x;
output [127:0] l2c_ciu_dca_data_x;
output l2c_ciu_dca_ready_x;
output [1 :0] l2c_ciu_hpcp_acc_inc_x;
output [2 :0] l2c_ciu_hpcp_mid_x;
output [1 :0] l2c_ciu_hpcp_miss_inc_x;
output [32 :0] l2c_ciu_rdl_addr_x;
output l2c_ciu_rdl_dvld_x;
output [2 :0] l2c_ciu_rdl_mid_x;
output [2 :0] l2c_ciu_rdl_prot_x;
output l2c_ciu_rdl_rvld_x;
output [4 :0] l2c_ciu_resp_x;
output [4 :0] l2c_ciu_sid_x;
output [32 :0] l2c_ciu_snpl2_addr_x;
output [4 :0] l2c_ciu_snpl2_ini_sid_x;
output l2c_ciu_snpl2_vld_x;
output l2c_data_ram_clk_en_x;
output [21 :0] l2c_dbg_info_x;
output l2c_flush_done_x;
output l2c_no_op_x;
output l2c_tag_ram_clk_en_x;
// &Regs; @24
// &Wires; @25
wire ciu_l2c_addr_vld_x;
wire [32 :0] ciu_l2c_addr_x;
wire [3 :0] ciu_l2c_clr_cp_x;
wire ciu_l2c_ctcq_req_x;
wire [3 :0] ciu_l2c_data_acc_cycle;
wire ciu_l2c_data_setup;
wire ciu_l2c_data_vld_x;
wire [32 :0] ciu_l2c_dca_addr_x;
wire ciu_l2c_dca_req_x;
wire [2 :0] ciu_l2c_hpcp_bus_x;
wire [2 :0] ciu_l2c_icc_mid_x;
wire [1 :0] ciu_l2c_icc_type_x;
wire [2 :0] ciu_l2c_mid_x;
wire ciu_l2c_rdl_ready_x;
wire ciu_l2c_rst_req;
wire [3 :0] ciu_l2c_set_cp_x;
wire [4 :0] ciu_l2c_sid_x;
wire ciu_l2c_snpl2_ready_x;
wire [1 :0] ciu_l2c_src_x;
wire [2 :0] ciu_l2c_tag_acc_cycle;
wire ciu_l2c_tag_setup;
wire [12 :0] ciu_l2c_type_x;
wire [511:0] ciu_l2c_wdata_x;
wire [511:0] cmp_data_din;
wire [12 :0] cmp_data_index;
wire cmp_data_req;
wire cmp_data_req_gate;
wire cmp_data_vld;
wire cmp_data_wen;
wire cmp_dirty_cen;
wire [143:0] cmp_dirty_din;
wire cmp_dirty_gwen;
wire [15 :0] cmp_dirty_way;
wire [8 :0] cmp_dirty_wen;
wire [32 :0] cmp_pref_addr_x;
wire cmp_pref_cache_miss_x;
wire cmp_pref_ifu_req_x;
wire cmp_pref_read_x;
wire cmp_pref_tlb_req_x;
wire cmp_pref_vld_x;
wire [15 :0] cmp_refill_ptr;
wire cmp_req_vld;
wire [3 :0] cmp_rfifo_cp;
wire cmp_rfifo_create;
wire [4 :0] cmp_rfifo_resp;
wire [4 :0] cmp_rfifo_sid;
wire [32 :0] cmp_stage_addr;
wire [3 :0] cmp_stage_cp;
wire [4 :0] cmp_stage_resp;
wire [4 :0] cmp_stage_sid;
wire [1 :0] cmp_stage_src;
wire cmp_stage_stall;
wire cmp_stage_vld;
wire cmp_stage_write;
wire cmp_stall_by_data;
wire cmp_tag_cen;
wire cmp_tag_gwen;
wire [8 :0] cmp_tag_index;
wire [15 :0] cmp_tag_wen;
wire [15 :0] cmp_way_v_hit;
wire [15 :0] cmp_way_vd_hit;
wire [15 :0] cmp_way_vs_hit;
wire [15 :0] cmp_way_vu_hit;
wire cmp_yy_wdata_pop;
wire cmp_yy_wdata_pop_gate;
wire cpurst_b;
wire data_ecc_ram_cen;
wire data_ecc_wen;
wire data_icc_grant;
wire [3 :0] data_stage_cp;
wire [6 :0] data_stage_index;
wire [4 :0] data_stage_resp;
wire [4 :0] data_stage_sid;
wire data_stage_vld;
wire data_xx_idle;
wire data_yy_flop_vld;
wire data_yy_ram_idle;
wire forever_cpuclk;
wire [4 :0] icc_data_cen;
wire icc_data_flop;
wire [12 :0] icc_data_index;
wire icc_data_req;
wire [7 :0] icc_dca_dirty_f;
wire [23 :0] icc_dca_tag_f;
wire [15 :0] icc_dca_way_sel;
wire icc_dirty_cen;
wire icc_dirty_gwen;
wire [8 :0] icc_dirty_wen;
wire icc_idle;
wire icc_tag_cen;
wire icc_tag_flop;
wire icc_tag_gwen;
wire [8 :0] icc_tag_index;
wire icc_tag_req;
wire l2c_busy;
wire l2c_ciu_addr_ready_x;
wire l2c_ciu_cmplt_x;
wire [3 :0] l2c_ciu_cp_x;
wire l2c_ciu_ctcq_cmplt_x;
wire l2c_ciu_ctcq_ready_x;
wire l2c_ciu_data_ready_gate_x;
wire l2c_ciu_data_ready_x;
wire [511:0] l2c_ciu_data_x;
wire l2c_ciu_dca_cmplt_x;
wire [127:0] l2c_ciu_dca_data_x;
wire l2c_ciu_dca_ready_x;
wire [1 :0] l2c_ciu_hpcp_acc_inc_x;
wire [2 :0] l2c_ciu_hpcp_mid_x;
wire [1 :0] l2c_ciu_hpcp_miss_inc_x;
wire [32 :0] l2c_ciu_rdl_addr_x;
wire l2c_ciu_rdl_dvld_x;
wire [2 :0] l2c_ciu_rdl_mid_x;
wire [2 :0] l2c_ciu_rdl_prot_x;
wire l2c_ciu_rdl_rvld_x;
wire [4 :0] l2c_ciu_resp_x;
wire [4 :0] l2c_ciu_sid_x;
wire [32 :0] l2c_ciu_snpl2_addr_x;
wire [4 :0] l2c_ciu_snpl2_ini_sid_x;
wire l2c_ciu_snpl2_vld_x;
wire l2c_clk;
wire l2c_clk_en;
wire l2c_data_clk_x;
wire [511:0] l2c_data_din;
wire [511:0] l2c_data_dout;
wire [511:0] l2c_data_dout_flop;
wire [12 :0] l2c_data_index0;
wire [12 :0] l2c_data_index1;
wire [12 :0] l2c_data_index2;
wire [12 :0] l2c_data_index3;
wire [3 :0] l2c_data_ram_cen;
wire l2c_data_ram_clk_en_x;
wire [3 :0] l2c_data_wen;
wire [21 :0] l2c_dbg_info_x;
wire [143:0] l2c_dirty_din;
wire [143:0] l2c_dirty_dout;
wire l2c_dirty_gwen;
wire l2c_dirty_ram_cen;
wire [143:0] l2c_dirty_wen;
wire l2c_flush_done_x;
wire l2c_flush_req_x;
wire l2c_icg_en;
wire l2c_no_op_x;
wire l2c_pipeline_rdy;
wire l2c_tag_clk_x;
wire [383:0] l2c_tag_din;
wire [15 :0] l2c_tag_dirty_fatal_err;
wire [383:0] l2c_tag_dout;
wire l2c_tag_gwen;
wire [8 :0] l2c_tag_index;
wire l2c_tag_ram_cen;
wire l2c_tag_ram_clk_en_x;
wire [383:0] l2c_tag_wen;
wire [3 :0] l2c_way0_cp_dout;
wire [7 :0] l2c_way0_dirty_dout;
wire [23 :0] l2c_way0_tag_dout;
wire [3 :0] l2c_way10_cp_dout;
wire [7 :0] l2c_way10_dirty_dout;
wire [23 :0] l2c_way10_tag_dout;
wire [3 :0] l2c_way11_cp_dout;
wire [7 :0] l2c_way11_dirty_dout;
wire [23 :0] l2c_way11_tag_dout;
wire [3 :0] l2c_way12_cp_dout;
wire [7 :0] l2c_way12_dirty_dout;
wire [23 :0] l2c_way12_tag_dout;
wire [3 :0] l2c_way13_cp_dout;
wire [7 :0] l2c_way13_dirty_dout;
wire [23 :0] l2c_way13_tag_dout;
wire [3 :0] l2c_way14_cp_dout;
wire [7 :0] l2c_way14_dirty_dout;
wire [23 :0] l2c_way14_tag_dout;
wire [3 :0] l2c_way15_cp_dout;
wire [7 :0] l2c_way15_dirty_dout;
wire [23 :0] l2c_way15_tag_dout;
wire [3 :0] l2c_way1_cp_dout;
wire [7 :0] l2c_way1_dirty_dout;
wire [23 :0] l2c_way1_tag_dout;
wire [3 :0] l2c_way2_cp_dout;
wire [7 :0] l2c_way2_dirty_dout;
wire [23 :0] l2c_way2_tag_dout;
wire [3 :0] l2c_way3_cp_dout;
wire [7 :0] l2c_way3_dirty_dout;
wire [23 :0] l2c_way3_tag_dout;
wire [3 :0] l2c_way4_cp_dout;
wire [7 :0] l2c_way4_dirty_dout;
wire [23 :0] l2c_way4_tag_dout;
wire [3 :0] l2c_way5_cp_dout;
wire [7 :0] l2c_way5_dirty_dout;
wire [23 :0] l2c_way5_tag_dout;
wire [3 :0] l2c_way6_cp_dout;
wire [7 :0] l2c_way6_dirty_dout;
wire [23 :0] l2c_way6_tag_dout;
wire [3 :0] l2c_way7_cp_dout;
wire [7 :0] l2c_way7_dirty_dout;
wire [23 :0] l2c_way7_tag_dout;
wire [3 :0] l2c_way8_cp_dout;
wire [7 :0] l2c_way8_dirty_dout;
wire [23 :0] l2c_way8_tag_dout;
wire [3 :0] l2c_way9_cp_dout;
wire [7 :0] l2c_way9_dirty_dout;
wire [23 :0] l2c_way9_tag_dout;
wire [15 :0] l2c_way_dirty;
wire [15 :0] l2c_way_fifo;
wire [15 :0] l2c_way_vld;
wire pad_yy_icg_scan_en;
wire rfifo_empty;
wire tag_acc_cnt_zero;
wire tag_icc_grant;
wire tag_stage_vld;
wire tag_xx_idle;
wire tag_yy_ram_idle;
wire ttecc_flop_vld;
wire [32 :0] ttecc_stage_addr;
wire [3 :0] ttecc_stage_clrcp;
wire ttecc_stage_fatal_err;
wire [2 :0] ttecc_stage_hpcp_bus;
wire [2 :0] ttecc_stage_mid;
wire [3 :0] ttecc_stage_setcp;
wire [4 :0] ttecc_stage_sid;
wire [1 :0] ttecc_stage_src;
wire [12 :0] ttecc_stage_type;
wire ttecc_stage_write_raw;
wire wb_dirty_cen;
wire wb_dirty_gwen;
wire [15 :0] wb_dirty_way;
wire [8 :0] wb_dirty_wen;
wire wb_ecc_rfifo_empty;
wire wb_stage_fatal_err;
wire wb_stage_vld;
wire wb_tag_cen;
wire wb_tag_gwen;
wire [8 :0] wb_tag_index;
wire wb_tag_req;
assign l2c_busy = tag_stage_vld | cmp_stage_vld | data_stage_vld | wb_stage_vld |
!tag_xx_idle | !data_xx_idle |
!rfifo_empty | !icc_idle;
assign l2c_dbg_info_x[21:0] = {ciu_l2c_type_x[12:0],ciu_l2c_addr_vld_x,
tag_stage_vld,cmp_stage_vld,
data_stage_vld,1'b0,
wb_stage_vld,rfifo_empty,
1'b0,icc_idle};
assign l2c_clk_en = ciu_l2c_data_vld_x | l2c_busy;
assign l2c_no_op_x = !l2c_busy;
// &Instance("gated_clk_cell", "x_l2c_gated_clk"); @53
gated_clk_cell x_l2c_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2c_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2c_clk_en ),
.module_en (l2c_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @54
// .external_en (1'b0 ), @55
// .global_en (1'b1 ), @56
// .module_en (l2c_icg_en ), @57
// .local_en (l2c_clk_en ), @58
// .clk_out (l2c_clk ) @59
// ); @60
// &Instance("ct_l2c_tag","x_ct_l2c_tag"); @62
ct_l2c_tag x_ct_l2c_tag (
.ciu_l2c_addr_vld_x (ciu_l2c_addr_vld_x ),
.ciu_l2c_addr_x (ciu_l2c_addr_x ),
.ciu_l2c_clr_cp_x (ciu_l2c_clr_cp_x ),
.ciu_l2c_hpcp_bus_x (ciu_l2c_hpcp_bus_x ),
.ciu_l2c_mid_x (ciu_l2c_mid_x ),
.ciu_l2c_set_cp_x (ciu_l2c_set_cp_x ),
.ciu_l2c_sid_x (ciu_l2c_sid_x ),
.ciu_l2c_src_x (ciu_l2c_src_x ),
.ciu_l2c_tag_acc_cycle (ciu_l2c_tag_acc_cycle ),
.ciu_l2c_tag_setup (ciu_l2c_tag_setup ),
.ciu_l2c_type_x (ciu_l2c_type_x ),
.cmp_dirty_cen (cmp_dirty_cen ),
.cmp_dirty_din (cmp_dirty_din ),
.cmp_dirty_gwen (cmp_dirty_gwen ),
.cmp_dirty_way (cmp_dirty_way ),
.cmp_dirty_wen (cmp_dirty_wen ),
.cmp_refill_ptr (cmp_refill_ptr ),
.cmp_req_vld (cmp_req_vld ),
.cmp_stage_addr (cmp_stage_addr ),
.cmp_stage_stall (cmp_stage_stall ),
.cmp_stage_vld (cmp_stage_vld ),
.cmp_stall_by_data (cmp_stall_by_data ),
.cmp_tag_cen (cmp_tag_cen ),
.cmp_tag_gwen (cmp_tag_gwen ),
.cmp_tag_index (cmp_tag_index ),
.cmp_tag_wen (cmp_tag_wen ),
.cmp_way_v_hit (cmp_way_v_hit ),
.cmp_way_vd_hit (cmp_way_vd_hit ),
.cmp_way_vs_hit (cmp_way_vs_hit ),
.cmp_way_vu_hit (cmp_way_vu_hit ),
.cpurst_b (cpurst_b ),
.data_stage_index (data_stage_index ),
.data_stage_vld (data_stage_vld ),
.forever_cpuclk (forever_cpuclk ),
.icc_dca_dirty_f (icc_dca_dirty_f ),
.icc_dca_tag_f (icc_dca_tag_f ),
.icc_dca_way_sel (icc_dca_way_sel ),
.icc_dirty_cen (icc_dirty_cen ),
.icc_dirty_gwen (icc_dirty_gwen ),
.icc_dirty_wen (icc_dirty_wen ),
.icc_idle (icc_idle ),
.icc_tag_cen (icc_tag_cen ),
.icc_tag_flop (icc_tag_flop ),
.icc_tag_gwen (icc_tag_gwen ),
.icc_tag_index (icc_tag_index ),
.icc_tag_req (icc_tag_req ),
.l2c_ciu_addr_ready_x (l2c_ciu_addr_ready_x ),
.l2c_dirty_din (l2c_dirty_din ),
.l2c_dirty_dout (l2c_dirty_dout ),
.l2c_dirty_gwen (l2c_dirty_gwen ),
.l2c_dirty_ram_cen (l2c_dirty_ram_cen ),
.l2c_dirty_wen (l2c_dirty_wen ),
.l2c_icg_en (l2c_icg_en ),
.l2c_tag_din (l2c_tag_din ),
.l2c_tag_dirty_fatal_err (l2c_tag_dirty_fatal_err),
.l2c_tag_dout (l2c_tag_dout ),
.l2c_tag_gwen (l2c_tag_gwen ),
.l2c_tag_index (l2c_tag_index ),
.l2c_tag_ram_cen (l2c_tag_ram_cen ),
.l2c_tag_ram_clk_en_x (l2c_tag_ram_clk_en_x ),
.l2c_tag_wen (l2c_tag_wen ),
.l2c_way0_cp_dout (l2c_way0_cp_dout ),
.l2c_way0_dirty_dout (l2c_way0_dirty_dout ),
.l2c_way0_tag_dout (l2c_way0_tag_dout ),
.l2c_way10_cp_dout (l2c_way10_cp_dout ),
.l2c_way10_dirty_dout (l2c_way10_dirty_dout ),
.l2c_way10_tag_dout (l2c_way10_tag_dout ),
.l2c_way11_cp_dout (l2c_way11_cp_dout ),
.l2c_way11_dirty_dout (l2c_way11_dirty_dout ),
.l2c_way11_tag_dout (l2c_way11_tag_dout ),
.l2c_way12_cp_dout (l2c_way12_cp_dout ),
.l2c_way12_dirty_dout (l2c_way12_dirty_dout ),
.l2c_way12_tag_dout (l2c_way12_tag_dout ),
.l2c_way13_cp_dout (l2c_way13_cp_dout ),
.l2c_way13_dirty_dout (l2c_way13_dirty_dout ),
.l2c_way13_tag_dout (l2c_way13_tag_dout ),
.l2c_way14_cp_dout (l2c_way14_cp_dout ),
.l2c_way14_dirty_dout (l2c_way14_dirty_dout ),
.l2c_way14_tag_dout (l2c_way14_tag_dout ),
.l2c_way15_cp_dout (l2c_way15_cp_dout ),
.l2c_way15_dirty_dout (l2c_way15_dirty_dout ),
.l2c_way15_tag_dout (l2c_way15_tag_dout ),
.l2c_way1_cp_dout (l2c_way1_cp_dout ),
.l2c_way1_dirty_dout (l2c_way1_dirty_dout ),
.l2c_way1_tag_dout (l2c_way1_tag_dout ),
.l2c_way2_cp_dout (l2c_way2_cp_dout ),
.l2c_way2_dirty_dout (l2c_way2_dirty_dout ),
.l2c_way2_tag_dout (l2c_way2_tag_dout ),
.l2c_way3_cp_dout (l2c_way3_cp_dout ),
.l2c_way3_dirty_dout (l2c_way3_dirty_dout ),
.l2c_way3_tag_dout (l2c_way3_tag_dout ),
.l2c_way4_cp_dout (l2c_way4_cp_dout ),
.l2c_way4_dirty_dout (l2c_way4_dirty_dout ),
.l2c_way4_tag_dout (l2c_way4_tag_dout ),
.l2c_way5_cp_dout (l2c_way5_cp_dout ),
.l2c_way5_dirty_dout (l2c_way5_dirty_dout ),
.l2c_way5_tag_dout (l2c_way5_tag_dout ),
.l2c_way6_cp_dout (l2c_way6_cp_dout ),
.l2c_way6_dirty_dout (l2c_way6_dirty_dout ),
.l2c_way6_tag_dout (l2c_way6_tag_dout ),
.l2c_way7_cp_dout (l2c_way7_cp_dout ),
.l2c_way7_dirty_dout (l2c_way7_dirty_dout ),
.l2c_way7_tag_dout (l2c_way7_tag_dout ),
.l2c_way8_cp_dout (l2c_way8_cp_dout ),
.l2c_way8_dirty_dout (l2c_way8_dirty_dout ),
.l2c_way8_tag_dout (l2c_way8_tag_dout ),
.l2c_way9_cp_dout (l2c_way9_cp_dout ),
.l2c_way9_dirty_dout (l2c_way9_dirty_dout ),
.l2c_way9_tag_dout (l2c_way9_tag_dout ),
.l2c_way_dirty (l2c_way_dirty ),
.l2c_way_fifo (l2c_way_fifo ),
.l2c_way_vld (l2c_way_vld ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.tag_acc_cnt_zero (tag_acc_cnt_zero ),
.tag_icc_grant (tag_icc_grant ),
.tag_stage_vld (tag_stage_vld ),
.tag_xx_idle (tag_xx_idle ),
.tag_yy_ram_idle (tag_yy_ram_idle ),
.ttecc_flop_vld (ttecc_flop_vld ),
.ttecc_stage_addr (ttecc_stage_addr ),
.ttecc_stage_clrcp (ttecc_stage_clrcp ),
.ttecc_stage_fatal_err (ttecc_stage_fatal_err ),
.ttecc_stage_hpcp_bus (ttecc_stage_hpcp_bus ),
.ttecc_stage_mid (ttecc_stage_mid ),
.ttecc_stage_setcp (ttecc_stage_setcp ),
.ttecc_stage_sid (ttecc_stage_sid ),
.ttecc_stage_src (ttecc_stage_src ),
.ttecc_stage_type (ttecc_stage_type ),
.ttecc_stage_write_raw (ttecc_stage_write_raw ),
.wb_dirty_cen (wb_dirty_cen ),
.wb_dirty_gwen (wb_dirty_gwen ),
.wb_dirty_way (wb_dirty_way ),
.wb_dirty_wen (wb_dirty_wen ),
.wb_ecc_rfifo_empty (wb_ecc_rfifo_empty ),
.wb_tag_cen (wb_tag_cen ),
.wb_tag_gwen (wb_tag_gwen ),
.wb_tag_index (wb_tag_index ),
.wb_tag_req (wb_tag_req )
);
// &Instance("ct_l2c_cmp","x_ct_l2c_cmp"); @63
ct_l2c_cmp x_ct_l2c_cmp (
.ciu_l2c_snpl2_ready_x (ciu_l2c_snpl2_ready_x ),
.cmp_data_index (cmp_data_index ),
.cmp_data_req (cmp_data_req ),
.cmp_data_req_gate (cmp_data_req_gate ),
.cmp_data_vld (cmp_data_vld ),
.cmp_data_wen (cmp_data_wen ),
.cmp_dirty_cen (cmp_dirty_cen ),
.cmp_dirty_din (cmp_dirty_din ),
.cmp_dirty_gwen (cmp_dirty_gwen ),
.cmp_dirty_way (cmp_dirty_way ),
.cmp_dirty_wen (cmp_dirty_wen ),
.cmp_pref_addr_x (cmp_pref_addr_x ),
.cmp_pref_cache_miss_x (cmp_pref_cache_miss_x ),
.cmp_pref_ifu_req_x (cmp_pref_ifu_req_x ),
.cmp_pref_read_x (cmp_pref_read_x ),
.cmp_pref_tlb_req_x (cmp_pref_tlb_req_x ),
.cmp_pref_vld_x (cmp_pref_vld_x ),
.cmp_refill_ptr (cmp_refill_ptr ),
.cmp_req_vld (cmp_req_vld ),
.cmp_rfifo_cp (cmp_rfifo_cp ),
.cmp_rfifo_create (cmp_rfifo_create ),
.cmp_rfifo_resp (cmp_rfifo_resp ),
.cmp_rfifo_sid (cmp_rfifo_sid ),
.cmp_stage_addr (cmp_stage_addr ),
.cmp_stage_cp (cmp_stage_cp ),
.cmp_stage_resp (cmp_stage_resp ),
.cmp_stage_sid (cmp_stage_sid ),
.cmp_stage_src (cmp_stage_src ),
.cmp_stage_stall (cmp_stage_stall ),
.cmp_stage_vld (cmp_stage_vld ),
.cmp_stage_write (cmp_stage_write ),
.cmp_stall_by_data (cmp_stall_by_data ),
.cmp_tag_cen (cmp_tag_cen ),
.cmp_tag_gwen (cmp_tag_gwen ),
.cmp_tag_index (cmp_tag_index ),
.cmp_tag_wen (cmp_tag_wen ),
.cmp_way_v_hit (cmp_way_v_hit ),
.cmp_way_vd_hit (cmp_way_vd_hit ),
.cmp_way_vs_hit (cmp_way_vs_hit ),
.cmp_way_vu_hit (cmp_way_vu_hit ),
.cmp_yy_wdata_pop (cmp_yy_wdata_pop ),
.cmp_yy_wdata_pop_gate (cmp_yy_wdata_pop_gate ),
.cpurst_b (cpurst_b ),
.data_yy_ram_idle (data_yy_ram_idle ),
.forever_cpuclk (forever_cpuclk ),
.l2c_ciu_hpcp_acc_inc_x (l2c_ciu_hpcp_acc_inc_x ),
.l2c_ciu_hpcp_mid_x (l2c_ciu_hpcp_mid_x ),
.l2c_ciu_hpcp_miss_inc_x (l2c_ciu_hpcp_miss_inc_x),
.l2c_ciu_snpl2_addr_x (l2c_ciu_snpl2_addr_x ),
.l2c_ciu_snpl2_ini_sid_x (l2c_ciu_snpl2_ini_sid_x),
.l2c_ciu_snpl2_vld_x (l2c_ciu_snpl2_vld_x ),
.l2c_clk (l2c_clk ),
.l2c_icg_en (l2c_icg_en ),
.l2c_way0_cp_dout (l2c_way0_cp_dout ),
.l2c_way0_dirty_dout (l2c_way0_dirty_dout ),
.l2c_way0_tag_dout (l2c_way0_tag_dout ),
.l2c_way10_cp_dout (l2c_way10_cp_dout ),
.l2c_way10_dirty_dout (l2c_way10_dirty_dout ),
.l2c_way10_tag_dout (l2c_way10_tag_dout ),
.l2c_way11_cp_dout (l2c_way11_cp_dout ),
.l2c_way11_dirty_dout (l2c_way11_dirty_dout ),
.l2c_way11_tag_dout (l2c_way11_tag_dout ),
.l2c_way12_cp_dout (l2c_way12_cp_dout ),
.l2c_way12_dirty_dout (l2c_way12_dirty_dout ),
.l2c_way12_tag_dout (l2c_way12_tag_dout ),
.l2c_way13_cp_dout (l2c_way13_cp_dout ),
.l2c_way13_dirty_dout (l2c_way13_dirty_dout ),
.l2c_way13_tag_dout (l2c_way13_tag_dout ),
.l2c_way14_cp_dout (l2c_way14_cp_dout ),
.l2c_way14_dirty_dout (l2c_way14_dirty_dout ),
.l2c_way14_tag_dout (l2c_way14_tag_dout ),
.l2c_way15_cp_dout (l2c_way15_cp_dout ),
.l2c_way15_dirty_dout (l2c_way15_dirty_dout ),
.l2c_way15_tag_dout (l2c_way15_tag_dout ),
.l2c_way1_cp_dout (l2c_way1_cp_dout ),
.l2c_way1_dirty_dout (l2c_way1_dirty_dout ),
.l2c_way1_tag_dout (l2c_way1_tag_dout ),
.l2c_way2_cp_dout (l2c_way2_cp_dout ),
.l2c_way2_dirty_dout (l2c_way2_dirty_dout ),
.l2c_way2_tag_dout (l2c_way2_tag_dout ),
.l2c_way3_cp_dout (l2c_way3_cp_dout ),
.l2c_way3_dirty_dout (l2c_way3_dirty_dout ),
.l2c_way3_tag_dout (l2c_way3_tag_dout ),
.l2c_way4_cp_dout (l2c_way4_cp_dout ),
.l2c_way4_dirty_dout (l2c_way4_dirty_dout ),
.l2c_way4_tag_dout (l2c_way4_tag_dout ),
.l2c_way5_cp_dout (l2c_way5_cp_dout ),
.l2c_way5_dirty_dout (l2c_way5_dirty_dout ),
.l2c_way5_tag_dout (l2c_way5_tag_dout ),
.l2c_way6_cp_dout (l2c_way6_cp_dout ),
.l2c_way6_dirty_dout (l2c_way6_dirty_dout ),
.l2c_way6_tag_dout (l2c_way6_tag_dout ),
.l2c_way7_cp_dout (l2c_way7_cp_dout ),
.l2c_way7_dirty_dout (l2c_way7_dirty_dout ),
.l2c_way7_tag_dout (l2c_way7_tag_dout ),
.l2c_way8_cp_dout (l2c_way8_cp_dout ),
.l2c_way8_dirty_dout (l2c_way8_dirty_dout ),
.l2c_way8_tag_dout (l2c_way8_tag_dout ),
.l2c_way9_cp_dout (l2c_way9_cp_dout ),
.l2c_way9_dirty_dout (l2c_way9_dirty_dout ),
.l2c_way9_tag_dout (l2c_way9_tag_dout ),
.l2c_way_fifo (l2c_way_fifo ),
.l2c_way_vld (l2c_way_vld ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.tag_yy_ram_idle (tag_yy_ram_idle ),
.ttecc_flop_vld (ttecc_flop_vld ),
.ttecc_stage_addr (ttecc_stage_addr ),
.ttecc_stage_clrcp (ttecc_stage_clrcp ),
.ttecc_stage_fatal_err (ttecc_stage_fatal_err ),
.ttecc_stage_hpcp_bus (ttecc_stage_hpcp_bus ),
.ttecc_stage_mid (ttecc_stage_mid ),
.ttecc_stage_setcp (ttecc_stage_setcp ),
.ttecc_stage_sid (ttecc_stage_sid ),
.ttecc_stage_src (ttecc_stage_src ),
.ttecc_stage_type (ttecc_stage_type ),
.ttecc_stage_write_raw (ttecc_stage_write_raw )
);
// &Instance("ct_l2c_data","x_ct_l2c_data"); @64
ct_l2c_data x_ct_l2c_data (
.ciu_l2c_data_acc_cycle (ciu_l2c_data_acc_cycle),
.ciu_l2c_data_setup (ciu_l2c_data_setup ),
.cmp_data_din (cmp_data_din ),
.cmp_data_index (cmp_data_index ),
.cmp_data_req (cmp_data_req ),
.cmp_data_req_gate (cmp_data_req_gate ),
.cmp_data_wen (cmp_data_wen ),
.cmp_stage_addr (cmp_stage_addr ),
.cmp_stage_cp (cmp_stage_cp ),
.cmp_stage_resp (cmp_stage_resp ),
.cmp_stage_sid (cmp_stage_sid ),
.cmp_stage_src (cmp_stage_src ),
.cmp_stage_write (cmp_stage_write ),
.cpurst_b (cpurst_b ),
.data_ecc_ram_cen (data_ecc_ram_cen ),
.data_ecc_wen (data_ecc_wen ),
.data_icc_grant (data_icc_grant ),
.data_stage_cp (data_stage_cp ),
.data_stage_index (data_stage_index ),
.data_stage_resp (data_stage_resp ),
.data_stage_sid (data_stage_sid ),
.data_stage_vld (data_stage_vld ),
.data_xx_idle (data_xx_idle ),
.data_yy_flop_vld (data_yy_flop_vld ),
.data_yy_ram_idle (data_yy_ram_idle ),
.forever_cpuclk (forever_cpuclk ),
.icc_data_cen (icc_data_cen ),
.icc_data_flop (icc_data_flop ),
.icc_data_index (icc_data_index ),
.icc_data_req (icc_data_req ),
.l2c_clk (l2c_clk ),
.l2c_data_din (l2c_data_din ),
.l2c_data_dout (l2c_data_dout ),
.l2c_data_dout_flop (l2c_data_dout_flop ),
.l2c_data_index0 (l2c_data_index0 ),
.l2c_data_index1 (l2c_data_index1 ),
.l2c_data_index2 (l2c_data_index2 ),
.l2c_data_index3 (l2c_data_index3 ),
.l2c_data_ram_cen (l2c_data_ram_cen ),
.l2c_data_ram_clk_en_x (l2c_data_ram_clk_en_x ),
.l2c_data_wen (l2c_data_wen ),
.l2c_icg_en (l2c_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_l2c_wb","x_ct_l2c_wb"); @65
ct_l2c_wb x_ct_l2c_wb (
.cmp_rfifo_cp (cmp_rfifo_cp ),
.cmp_rfifo_create (cmp_rfifo_create ),
.cmp_rfifo_resp (cmp_rfifo_resp ),
.cmp_rfifo_sid (cmp_rfifo_sid ),
.cmp_stage_vld (cmp_stage_vld ),
.cpurst_b (cpurst_b ),
.data_stage_cp (data_stage_cp ),
.data_stage_resp (data_stage_resp ),
.data_stage_sid (data_stage_sid ),
.data_stage_vld (data_stage_vld ),
.data_yy_flop_vld (data_yy_flop_vld ),
.forever_cpuclk (forever_cpuclk ),
.l2c_ciu_cmplt_x (l2c_ciu_cmplt_x ),
.l2c_ciu_cp_x (l2c_ciu_cp_x ),
.l2c_ciu_data_x (l2c_ciu_data_x ),
.l2c_ciu_resp_x (l2c_ciu_resp_x ),
.l2c_ciu_sid_x (l2c_ciu_sid_x ),
.l2c_clk (l2c_clk ),
.l2c_data_dout_flop (l2c_data_dout_flop),
.l2c_icg_en (l2c_icg_en ),
.l2c_pipeline_rdy (l2c_pipeline_rdy ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en),
.rfifo_empty (rfifo_empty ),
.tag_stage_vld (tag_stage_vld ),
.wb_dirty_cen (wb_dirty_cen ),
.wb_dirty_gwen (wb_dirty_gwen ),
.wb_dirty_way (wb_dirty_way ),
.wb_dirty_wen (wb_dirty_wen ),
.wb_ecc_rfifo_empty (wb_ecc_rfifo_empty),
.wb_stage_fatal_err (wb_stage_fatal_err),
.wb_stage_vld (wb_stage_vld ),
.wb_tag_cen (wb_tag_cen ),
.wb_tag_gwen (wb_tag_gwen ),
.wb_tag_index (wb_tag_index ),
.wb_tag_req (wb_tag_req )
);
// &Instance("ct_l2c_icc","x_ct_l2c_icc"); @66
ct_l2c_icc x_ct_l2c_icc (
.ciu_l2c_ctcq_req_x (ciu_l2c_ctcq_req_x ),
.ciu_l2c_dca_addr_x (ciu_l2c_dca_addr_x ),
.ciu_l2c_dca_req_x (ciu_l2c_dca_req_x ),
.ciu_l2c_icc_mid_x (ciu_l2c_icc_mid_x ),
.ciu_l2c_icc_type_x (ciu_l2c_icc_type_x ),
.ciu_l2c_rdl_ready_x (ciu_l2c_rdl_ready_x ),
.ciu_l2c_rst_req (ciu_l2c_rst_req ),
.cpurst_b (cpurst_b ),
.data_icc_grant (data_icc_grant ),
.forever_cpuclk (forever_cpuclk ),
.icc_data_cen (icc_data_cen ),
.icc_data_flop (icc_data_flop ),
.icc_data_index (icc_data_index ),
.icc_data_req (icc_data_req ),
.icc_dca_dirty_f (icc_dca_dirty_f ),
.icc_dca_tag_f (icc_dca_tag_f ),
.icc_dca_way_sel (icc_dca_way_sel ),
.icc_dirty_cen (icc_dirty_cen ),
.icc_dirty_gwen (icc_dirty_gwen ),
.icc_dirty_wen (icc_dirty_wen ),
.icc_idle (icc_idle ),
.icc_tag_cen (icc_tag_cen ),
.icc_tag_flop (icc_tag_flop ),
.icc_tag_gwen (icc_tag_gwen ),
.icc_tag_index (icc_tag_index ),
.icc_tag_req (icc_tag_req ),
.l2c_ciu_ctcq_cmplt_x (l2c_ciu_ctcq_cmplt_x ),
.l2c_ciu_ctcq_ready_x (l2c_ciu_ctcq_ready_x ),
.l2c_ciu_dca_cmplt_x (l2c_ciu_dca_cmplt_x ),
.l2c_ciu_dca_data_x (l2c_ciu_dca_data_x ),
.l2c_ciu_dca_ready_x (l2c_ciu_dca_ready_x ),
.l2c_ciu_rdl_addr_x (l2c_ciu_rdl_addr_x ),
.l2c_ciu_rdl_dvld_x (l2c_ciu_rdl_dvld_x ),
.l2c_ciu_rdl_mid_x (l2c_ciu_rdl_mid_x ),
.l2c_ciu_rdl_prot_x (l2c_ciu_rdl_prot_x ),
.l2c_ciu_rdl_rvld_x (l2c_ciu_rdl_rvld_x ),
.l2c_data_dout_flop (l2c_data_dout_flop ),
.l2c_flush_done_x (l2c_flush_done_x ),
.l2c_flush_req_x (l2c_flush_req_x ),
.l2c_icg_en (l2c_icg_en ),
.l2c_pipeline_rdy (l2c_pipeline_rdy ),
.l2c_tag_dirty_fatal_err (l2c_tag_dirty_fatal_err),
.l2c_way0_tag_dout (l2c_way0_tag_dout ),
.l2c_way10_tag_dout (l2c_way10_tag_dout ),
.l2c_way11_tag_dout (l2c_way11_tag_dout ),
.l2c_way12_tag_dout (l2c_way12_tag_dout ),
.l2c_way13_tag_dout (l2c_way13_tag_dout ),
.l2c_way14_tag_dout (l2c_way14_tag_dout ),
.l2c_way15_tag_dout (l2c_way15_tag_dout ),
.l2c_way1_tag_dout (l2c_way1_tag_dout ),
.l2c_way2_tag_dout (l2c_way2_tag_dout ),
.l2c_way3_tag_dout (l2c_way3_tag_dout ),
.l2c_way4_tag_dout (l2c_way4_tag_dout ),
.l2c_way5_tag_dout (l2c_way5_tag_dout ),
.l2c_way6_tag_dout (l2c_way6_tag_dout ),
.l2c_way7_tag_dout (l2c_way7_tag_dout ),
.l2c_way8_tag_dout (l2c_way8_tag_dout ),
.l2c_way9_tag_dout (l2c_way9_tag_dout ),
.l2c_way_dirty (l2c_way_dirty ),
.l2c_way_vld (l2c_way_vld ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.tag_acc_cnt_zero (tag_acc_cnt_zero ),
.tag_icc_grant (tag_icc_grant ),
.wb_stage_fatal_err (wb_stage_fatal_err )
);
// &Instance("ct_l2c_ecc","x_ct_l2c_ecc"); @69
// &Force("nonport","data_ecc_ram_cen"); @71
// &Force("nonport","data_ecc_wen"); @72
assign l2c_ciu_data_ready_x = cmp_yy_wdata_pop;
assign l2c_ciu_data_ready_gate_x = cmp_yy_wdata_pop_gate;
assign cmp_data_vld = ciu_l2c_data_vld_x;
assign cmp_data_din[511:0] = ciu_l2c_wdata_x[511:0];
// &Instance("ct_l2cache_top","x_ct_l2cache_top"); @79
ct_l2cache_top x_ct_l2cache_top (
.l2c_data_clk_x (l2c_data_clk_x ),
.l2c_data_din (l2c_data_din ),
.l2c_data_dout (l2c_data_dout ),
.l2c_data_index0 (l2c_data_index0 ),
.l2c_data_index1 (l2c_data_index1 ),
.l2c_data_index2 (l2c_data_index2 ),
.l2c_data_index3 (l2c_data_index3 ),
.l2c_data_ram_cen (l2c_data_ram_cen ),
.l2c_data_wen (l2c_data_wen ),
.l2c_dirty_din (l2c_dirty_din ),
.l2c_dirty_dout (l2c_dirty_dout ),
.l2c_dirty_gwen (l2c_dirty_gwen ),
.l2c_dirty_ram_cen (l2c_dirty_ram_cen ),
.l2c_dirty_wen (l2c_dirty_wen ),
.l2c_tag_clk_x (l2c_tag_clk_x ),
.l2c_tag_din (l2c_tag_din ),
.l2c_tag_dout (l2c_tag_dout ),
.l2c_tag_gwen (l2c_tag_gwen ),
.l2c_tag_index (l2c_tag_index ),
.l2c_tag_ram_cen (l2c_tag_ram_cen ),
.l2c_tag_wen (l2c_tag_wen ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &ModuleEnd; @81
endmodule |
module ct_l2c_top(
ciu_l2c_addr_bank_0,
ciu_l2c_addr_bank_1,
ciu_l2c_addr_vld_bank_0,
ciu_l2c_addr_vld_bank_1,
ciu_l2c_clr_cp_bank_0,
ciu_l2c_clr_cp_bank_1,
ciu_l2c_ctcq_req_bank_0,
ciu_l2c_ctcq_req_bank_1,
ciu_l2c_data_latency,
ciu_l2c_data_setup,
ciu_l2c_data_vld_bank_0,
ciu_l2c_data_vld_bank_1,
ciu_l2c_dca_addr_bank_0,
ciu_l2c_dca_addr_bank_1,
ciu_l2c_dca_req_bank_0,
ciu_l2c_dca_req_bank_1,
ciu_l2c_hpcp_bus_bank_0,
ciu_l2c_hpcp_bus_bank_1,
ciu_l2c_icc_mid_bank_0,
ciu_l2c_icc_mid_bank_1,
ciu_l2c_icc_type_bank_0,
ciu_l2c_icc_type_bank_1,
ciu_l2c_iprf,
ciu_l2c_mid_bank_0,
ciu_l2c_mid_bank_1,
ciu_l2c_prf_ready,
ciu_l2c_rdl_ready_bank_0,
ciu_l2c_rdl_ready_bank_1,
ciu_l2c_rst_req,
ciu_l2c_set_cp_bank_0,
ciu_l2c_set_cp_bank_1,
ciu_l2c_sid_bank_0,
ciu_l2c_sid_bank_1,
ciu_l2c_snpl2_ready_bank_0,
ciu_l2c_snpl2_ready_bank_1,
ciu_l2c_src_bank_0,
ciu_l2c_src_bank_1,
ciu_l2c_tag_latency,
ciu_l2c_tag_setup,
ciu_l2c_tprf,
ciu_l2c_type_bank_0,
ciu_l2c_type_bank_1,
ciu_l2c_wdata_bank_0,
ciu_l2c_wdata_bank_1,
ciu_top_clk,
ciu_xx_no_op,
cpurst_b,
forever_cpuclk,
l2c_ciu_addr_ready_bank_0,
l2c_ciu_addr_ready_bank_1,
l2c_ciu_cmplt_bank_0,
l2c_ciu_cmplt_bank_1,
l2c_ciu_cp_bank_0,
l2c_ciu_cp_bank_1,
l2c_ciu_ctcq_cmplt_bank_0,
l2c_ciu_ctcq_cmplt_bank_1,
l2c_ciu_ctcq_ready_bank_0,
l2c_ciu_ctcq_ready_bank_1,
l2c_ciu_data_bank_0,
l2c_ciu_data_bank_1,
l2c_ciu_data_ready_bank_0,
l2c_ciu_data_ready_bank_1,
l2c_ciu_data_ready_gate_bank_0,
l2c_ciu_data_ready_gate_bank_1,
l2c_ciu_dbg_info,
l2c_ciu_dca_cmplt_bank_0,
l2c_ciu_dca_cmplt_bank_1,
l2c_ciu_dca_data_bank_0,
l2c_ciu_dca_data_bank_1,
l2c_ciu_dca_ready_bank_0,
l2c_ciu_dca_ready_bank_1,
l2c_ciu_hpcp_acc_inc_bank_0,
l2c_ciu_hpcp_acc_inc_bank_1,
l2c_ciu_hpcp_mid_bank_0,
l2c_ciu_hpcp_mid_bank_1,
l2c_ciu_hpcp_miss_inc_bank_0,
l2c_ciu_hpcp_miss_inc_bank_1,
l2c_ciu_prf_addr,
l2c_ciu_prf_prot,
l2c_ciu_prf_vld,
l2c_ciu_rdl_addr_bank_0,
l2c_ciu_rdl_addr_bank_1,
l2c_ciu_rdl_dvld_bank_0,
l2c_ciu_rdl_dvld_bank_1,
l2c_ciu_rdl_mid_bank_0,
l2c_ciu_rdl_mid_bank_1,
l2c_ciu_rdl_prot_bank_0,
l2c_ciu_rdl_prot_bank_1,
l2c_ciu_rdl_rvld_bank_0,
l2c_ciu_rdl_rvld_bank_1,
l2c_ciu_resp_bank_0,
l2c_ciu_resp_bank_1,
l2c_ciu_sid_bank_0,
l2c_ciu_sid_bank_1,
l2c_ciu_snpl2_addr_bank_0,
l2c_ciu_snpl2_addr_bank_1,
l2c_ciu_snpl2_ini_sid_bank_0,
l2c_ciu_snpl2_ini_sid_bank_1,
l2c_ciu_snpl2_vld_bank_0,
l2c_ciu_snpl2_vld_bank_1,
l2c_data_clk_bank_0,
l2c_data_clk_bank_1,
l2c_data_ram_clk_en_bank_0,
l2c_data_ram_clk_en_bank_1,
l2c_icg_en,
l2c_sysio_flush_done,
l2c_sysio_flush_idle,
l2c_tag_clk_bank_0,
l2c_tag_clk_bank_1,
l2c_tag_ram_clk_en_bank_0,
l2c_tag_ram_clk_en_bank_1,
l2c_xx_no_op,
pad_yy_icg_scan_en,
sysio_l2c_flush_req
);
// &Ports @24
input [32 :0] ciu_l2c_addr_bank_0;
input [32 :0] ciu_l2c_addr_bank_1;
input ciu_l2c_addr_vld_bank_0;
input ciu_l2c_addr_vld_bank_1;
input [3 :0] ciu_l2c_clr_cp_bank_0;
input [3 :0] ciu_l2c_clr_cp_bank_1;
input ciu_l2c_ctcq_req_bank_0;
input ciu_l2c_ctcq_req_bank_1;
input [2 :0] ciu_l2c_data_latency;
input ciu_l2c_data_setup;
input ciu_l2c_data_vld_bank_0;
input ciu_l2c_data_vld_bank_1;
input [32 :0] ciu_l2c_dca_addr_bank_0;
input [32 :0] ciu_l2c_dca_addr_bank_1;
input ciu_l2c_dca_req_bank_0;
input ciu_l2c_dca_req_bank_1;
input [2 :0] ciu_l2c_hpcp_bus_bank_0;
input [2 :0] ciu_l2c_hpcp_bus_bank_1;
input [2 :0] ciu_l2c_icc_mid_bank_0;
input [2 :0] ciu_l2c_icc_mid_bank_1;
input [1 :0] ciu_l2c_icc_type_bank_0;
input [1 :0] ciu_l2c_icc_type_bank_1;
input [1 :0] ciu_l2c_iprf;
input [2 :0] ciu_l2c_mid_bank_0;
input [2 :0] ciu_l2c_mid_bank_1;
input ciu_l2c_prf_ready;
input ciu_l2c_rdl_ready_bank_0;
input ciu_l2c_rdl_ready_bank_1;
input ciu_l2c_rst_req;
input [3 :0] ciu_l2c_set_cp_bank_0;
input [3 :0] ciu_l2c_set_cp_bank_1;
input [4 :0] ciu_l2c_sid_bank_0;
input [4 :0] ciu_l2c_sid_bank_1;
input ciu_l2c_snpl2_ready_bank_0;
input ciu_l2c_snpl2_ready_bank_1;
input [1 :0] ciu_l2c_src_bank_0;
input [1 :0] ciu_l2c_src_bank_1;
input [2 :0] ciu_l2c_tag_latency;
input ciu_l2c_tag_setup;
input ciu_l2c_tprf;
input [12 :0] ciu_l2c_type_bank_0;
input [12 :0] ciu_l2c_type_bank_1;
input [511:0] ciu_l2c_wdata_bank_0;
input [511:0] ciu_l2c_wdata_bank_1;
input ciu_top_clk;
input ciu_xx_no_op;
input cpurst_b;
input forever_cpuclk;
input l2c_data_clk_bank_0;
input l2c_data_clk_bank_1;
input l2c_icg_en;
input l2c_tag_clk_bank_0;
input l2c_tag_clk_bank_1;
input pad_yy_icg_scan_en;
input sysio_l2c_flush_req;
output l2c_ciu_addr_ready_bank_0;
output l2c_ciu_addr_ready_bank_1;
output l2c_ciu_cmplt_bank_0;
output l2c_ciu_cmplt_bank_1;
output [3 :0] l2c_ciu_cp_bank_0;
output [3 :0] l2c_ciu_cp_bank_1;
output l2c_ciu_ctcq_cmplt_bank_0;
output l2c_ciu_ctcq_cmplt_bank_1;
output l2c_ciu_ctcq_ready_bank_0;
output l2c_ciu_ctcq_ready_bank_1;
output [511:0] l2c_ciu_data_bank_0;
output [511:0] l2c_ciu_data_bank_1;
output l2c_ciu_data_ready_bank_0;
output l2c_ciu_data_ready_bank_1;
output l2c_ciu_data_ready_gate_bank_0;
output l2c_ciu_data_ready_gate_bank_1;
output [43 :0] l2c_ciu_dbg_info;
output l2c_ciu_dca_cmplt_bank_0;
output l2c_ciu_dca_cmplt_bank_1;
output [127:0] l2c_ciu_dca_data_bank_0;
output [127:0] l2c_ciu_dca_data_bank_1;
output l2c_ciu_dca_ready_bank_0;
output l2c_ciu_dca_ready_bank_1;
output [1 :0] l2c_ciu_hpcp_acc_inc_bank_0;
output [1 :0] l2c_ciu_hpcp_acc_inc_bank_1;
output [2 :0] l2c_ciu_hpcp_mid_bank_0;
output [2 :0] l2c_ciu_hpcp_mid_bank_1;
output [1 :0] l2c_ciu_hpcp_miss_inc_bank_0;
output [1 :0] l2c_ciu_hpcp_miss_inc_bank_1;
output [33 :0] l2c_ciu_prf_addr;
output [2 :0] l2c_ciu_prf_prot;
output l2c_ciu_prf_vld;
output [32 :0] l2c_ciu_rdl_addr_bank_0;
output [32 :0] l2c_ciu_rdl_addr_bank_1;
output l2c_ciu_rdl_dvld_bank_0;
output l2c_ciu_rdl_dvld_bank_1;
output [2 :0] l2c_ciu_rdl_mid_bank_0;
output [2 :0] l2c_ciu_rdl_mid_bank_1;
output [2 :0] l2c_ciu_rdl_prot_bank_0;
output [2 :0] l2c_ciu_rdl_prot_bank_1;
output l2c_ciu_rdl_rvld_bank_0;
output l2c_ciu_rdl_rvld_bank_1;
output [4 :0] l2c_ciu_resp_bank_0;
output [4 :0] l2c_ciu_resp_bank_1;
output [4 :0] l2c_ciu_sid_bank_0;
output [4 :0] l2c_ciu_sid_bank_1;
output [32 :0] l2c_ciu_snpl2_addr_bank_0;
output [32 :0] l2c_ciu_snpl2_addr_bank_1;
output [4 :0] l2c_ciu_snpl2_ini_sid_bank_0;
output [4 :0] l2c_ciu_snpl2_ini_sid_bank_1;
output l2c_ciu_snpl2_vld_bank_0;
output l2c_ciu_snpl2_vld_bank_1;
output l2c_data_ram_clk_en_bank_0;
output l2c_data_ram_clk_en_bank_1;
output l2c_sysio_flush_done;
output l2c_sysio_flush_idle;
output l2c_tag_ram_clk_en_bank_0;
output l2c_tag_ram_clk_en_bank_1;
output l2c_xx_no_op;
// &Regs; @25
reg [3 :0] ciu_l2c_data_acc_cycle;
reg [2 :0] ciu_l2c_tag_acc_cycle;
reg [2 :0] flush_cur_state;
reg [2 :0] flush_next_state;
// &Wires; @26
wire [32 :0] ciu_l2c_addr_bank_0;
wire [32 :0] ciu_l2c_addr_bank_1;
wire ciu_l2c_addr_vld_bank_0;
wire ciu_l2c_addr_vld_bank_1;
wire [3 :0] ciu_l2c_clr_cp_bank_0;
wire [3 :0] ciu_l2c_clr_cp_bank_1;
wire ciu_l2c_ctcq_req_bank_0;
wire ciu_l2c_ctcq_req_bank_1;
wire [2 :0] ciu_l2c_data_latency;
wire ciu_l2c_data_setup;
wire ciu_l2c_data_vld_bank_0;
wire ciu_l2c_data_vld_bank_1;
wire [32 :0] ciu_l2c_dca_addr_bank_0;
wire [32 :0] ciu_l2c_dca_addr_bank_1;
wire ciu_l2c_dca_req_bank_0;
wire ciu_l2c_dca_req_bank_1;
wire [2 :0] ciu_l2c_hpcp_bus_bank_0;
wire [2 :0] ciu_l2c_hpcp_bus_bank_1;
wire [2 :0] ciu_l2c_icc_mid_bank_0;
wire [2 :0] ciu_l2c_icc_mid_bank_1;
wire [1 :0] ciu_l2c_icc_type_bank_0;
wire [1 :0] ciu_l2c_icc_type_bank_1;
wire [1 :0] ciu_l2c_iprf;
wire [2 :0] ciu_l2c_mid_bank_0;
wire [2 :0] ciu_l2c_mid_bank_1;
wire ciu_l2c_prf_ready;
wire ciu_l2c_rdl_ready_bank_0;
wire ciu_l2c_rdl_ready_bank_1;
wire ciu_l2c_rst_req;
wire [3 :0] ciu_l2c_set_cp_bank_0;
wire [3 :0] ciu_l2c_set_cp_bank_1;
wire [4 :0] ciu_l2c_sid_bank_0;
wire [4 :0] ciu_l2c_sid_bank_1;
wire ciu_l2c_snpl2_ready_bank_0;
wire ciu_l2c_snpl2_ready_bank_1;
wire [1 :0] ciu_l2c_src_bank_0;
wire [1 :0] ciu_l2c_src_bank_1;
wire [2 :0] ciu_l2c_tag_latency;
wire ciu_l2c_tag_setup;
wire ciu_l2c_tprf;
wire [12 :0] ciu_l2c_type_bank_0;
wire [12 :0] ciu_l2c_type_bank_1;
wire [511:0] ciu_l2c_wdata_bank_0;
wire [511:0] ciu_l2c_wdata_bank_1;
wire ciu_top_clk;
wire ciu_xx_no_op;
wire [32 :0] cmp_pref_addr_bank_0;
wire [32 :0] cmp_pref_addr_bank_1;
wire cmp_pref_cache_miss_bank_0;
wire cmp_pref_cache_miss_bank_1;
wire cmp_pref_ifu_req_bank_0;
wire cmp_pref_ifu_req_bank_1;
wire cmp_pref_read_bank_0;
wire cmp_pref_read_bank_1;
wire cmp_pref_tlb_req_bank_0;
wire cmp_pref_tlb_req_bank_1;
wire cmp_pref_vld_bank_0;
wire cmp_pref_vld_bank_1;
wire cpurst_b;
wire [3 :0] data_acc_cycle;
wire forever_cpuclk;
wire l2c_ciu_addr_ready_bank_0;
wire l2c_ciu_addr_ready_bank_1;
wire l2c_ciu_cmplt_bank_0;
wire l2c_ciu_cmplt_bank_1;
wire [3 :0] l2c_ciu_cp_bank_0;
wire [3 :0] l2c_ciu_cp_bank_1;
wire l2c_ciu_ctcq_cmplt_bank_0;
wire l2c_ciu_ctcq_cmplt_bank_1;
wire l2c_ciu_ctcq_ready_bank_0;
wire l2c_ciu_ctcq_ready_bank_1;
wire [511:0] l2c_ciu_data_bank_0;
wire [511:0] l2c_ciu_data_bank_1;
wire l2c_ciu_data_ready_bank_0;
wire l2c_ciu_data_ready_bank_1;
wire l2c_ciu_data_ready_gate_bank_0;
wire l2c_ciu_data_ready_gate_bank_1;
wire [43 :0] l2c_ciu_dbg_info;
wire l2c_ciu_dca_cmplt_bank_0;
wire l2c_ciu_dca_cmplt_bank_1;
wire [127:0] l2c_ciu_dca_data_bank_0;
wire [127:0] l2c_ciu_dca_data_bank_1;
wire l2c_ciu_dca_ready_bank_0;
wire l2c_ciu_dca_ready_bank_1;
wire [1 :0] l2c_ciu_hpcp_acc_inc_bank_0;
wire [1 :0] l2c_ciu_hpcp_acc_inc_bank_1;
wire [2 :0] l2c_ciu_hpcp_mid_bank_0;
wire [2 :0] l2c_ciu_hpcp_mid_bank_1;
wire [1 :0] l2c_ciu_hpcp_miss_inc_bank_0;
wire [1 :0] l2c_ciu_hpcp_miss_inc_bank_1;
wire [33 :0] l2c_ciu_prf_addr;
wire [2 :0] l2c_ciu_prf_prot;
wire l2c_ciu_prf_vld;
wire [32 :0] l2c_ciu_rdl_addr_bank_0;
wire [32 :0] l2c_ciu_rdl_addr_bank_1;
wire l2c_ciu_rdl_dvld_bank_0;
wire l2c_ciu_rdl_dvld_bank_1;
wire [2 :0] l2c_ciu_rdl_mid_bank_0;
wire [2 :0] l2c_ciu_rdl_mid_bank_1;
wire [2 :0] l2c_ciu_rdl_prot_bank_0;
wire [2 :0] l2c_ciu_rdl_prot_bank_1;
wire l2c_ciu_rdl_rvld_bank_0;
wire l2c_ciu_rdl_rvld_bank_1;
wire [4 :0] l2c_ciu_resp_bank_0;
wire [4 :0] l2c_ciu_resp_bank_1;
wire [4 :0] l2c_ciu_sid_bank_0;
wire [4 :0] l2c_ciu_sid_bank_1;
wire [32 :0] l2c_ciu_snpl2_addr_bank_0;
wire [32 :0] l2c_ciu_snpl2_addr_bank_1;
wire [4 :0] l2c_ciu_snpl2_ini_sid_bank_0;
wire [4 :0] l2c_ciu_snpl2_ini_sid_bank_1;
wire l2c_ciu_snpl2_vld_bank_0;
wire l2c_ciu_snpl2_vld_bank_1;
wire l2c_data_clk_bank_0;
wire l2c_data_clk_bank_1;
wire l2c_data_ram_clk_en_bank_0;
wire l2c_data_ram_clk_en_bank_1;
wire [21 :0] l2c_dbg_info_bank_0;
wire [21 :0] l2c_dbg_info_bank_1;
wire l2c_flush_done_bank_0;
wire l2c_flush_done_bank_1;
wire l2c_flush_req_bank_0;
wire l2c_flush_req_bank_1;
wire l2c_icg_en;
wire l2c_no_op_bank_0;
wire l2c_no_op_bank_1;
wire l2c_sysio_flush_done;
wire l2c_sysio_flush_idle;
wire l2c_tag_clk_bank_0;
wire l2c_tag_clk_bank_1;
wire l2c_tag_ram_clk_en_bank_0;
wire l2c_tag_ram_clk_en_bank_1;
wire l2c_xx_no_op;
wire pad_yy_icg_scan_en;
wire prf_idle;
wire sysio_l2c_flush_req;
wire [3 :0] tag_acc_cycle;
assign tag_acc_cycle[3:0] = {3'b0,ciu_l2c_tag_setup } + {1'b0,ciu_l2c_tag_latency[2:0] };
assign data_acc_cycle[3:0] = {3'b0,ciu_l2c_data_setup} + {1'b0,ciu_l2c_data_latency[2:0]};
// &CombBeg; @43
always @( tag_acc_cycle[3:0])
begin
case(tag_acc_cycle[3:0])
4'b0000:
ciu_l2c_tag_acc_cycle[2:0] = 3'b000;
4'b0001:
ciu_l2c_tag_acc_cycle[2:0] = 3'b001;
4'b0010:
ciu_l2c_tag_acc_cycle[2:0] = 3'b010;
4'b0011:
ciu_l2c_tag_acc_cycle[2:0] = 3'b011;
4'b0100:
ciu_l2c_tag_acc_cycle[2:0] = 3'b100;
default:
ciu_l2c_tag_acc_cycle[2:0] = 3'b100;
endcase
// &CombEnd; @58
end
// &CombBeg; @60
always @( data_acc_cycle[3:0])
begin
case(data_acc_cycle[3:0])
4'b0000:
ciu_l2c_data_acc_cycle[3:0] = 4'b000;
4'b0001:
ciu_l2c_data_acc_cycle[3:0] = 4'b001;
4'b0010:
ciu_l2c_data_acc_cycle[3:0] = 4'b010;
4'b0011:
ciu_l2c_data_acc_cycle[3:0] = 4'b011;
4'b0100:
ciu_l2c_data_acc_cycle[3:0] = 4'b100;
4'b0101:
ciu_l2c_data_acc_cycle[3:0] = 4'b101;
4'b0110:
ciu_l2c_data_acc_cycle[3:0] = 4'b110;
4'b0111:
ciu_l2c_data_acc_cycle[3:0] = 4'b111;
4'b1000:
ciu_l2c_data_acc_cycle[3:0] = 4'b1000;
default:
ciu_l2c_data_acc_cycle[3:0] = 4'b1000;
endcase
// &CombEnd; @83
end
assign l2c_xx_no_op = prf_idle && l2c_no_op_bank_0 && l2c_no_op_bank_1;
//==========================================================
// l2c_flush from soc
//==========================================================
parameter IDLE = 3'b000;
parameter REQ = 3'b001;
parameter WAIT_1 = 3'b010;
parameter WAIT_0 = 3'b011;
parameter DONE = 3'b100;
always@(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
flush_cur_state[2:0] <= IDLE;
else
flush_cur_state[2:0] <= flush_next_state[2:0];
end
// &CombBeg; @104
always @( l2c_flush_done_bank_1
or sysio_l2c_flush_req
or l2c_flush_done_bank_0
or flush_cur_state
or ciu_xx_no_op)
begin
case(flush_cur_state)
IDLE: begin
if (sysio_l2c_flush_req & ciu_xx_no_op)
flush_next_state = REQ;
else
flush_next_state = IDLE;
end
REQ: begin
if (l2c_flush_done_bank_0 & l2c_flush_done_bank_1)
flush_next_state = DONE;
else if (l2c_flush_done_bank_0)
flush_next_state = WAIT_1;
else if (l2c_flush_done_bank_1)
flush_next_state = WAIT_0;
else
flush_next_state = REQ;
end
WAIT_1: begin
if (l2c_flush_done_bank_1)
flush_next_state = DONE;
else
flush_next_state = WAIT_1;
end
WAIT_0: begin
if (l2c_flush_done_bank_0)
flush_next_state = DONE;
else
flush_next_state = WAIT_0;
end
DONE: begin
if (!sysio_l2c_flush_req)
flush_next_state = IDLE;
else
flush_next_state = DONE;
end
default: flush_next_state = IDLE;
endcase
// &CombEnd; @142
end
assign l2c_sysio_flush_done = flush_cur_state == DONE;
assign l2c_sysio_flush_idle = flush_cur_state == IDLE;
assign l2c_flush_req_bank_0 = flush_cur_state == REQ;
assign l2c_flush_req_bank_1 = flush_cur_state == REQ;
//==========================================================
// module instance
//==========================================================
// &ConnRule(s/_x$/_bank_0/); @152
// &Instance("ct_l2c_sub_bank","x_ct_l2c_sub_bank_0"); @153
ct_l2c_sub_bank x_ct_l2c_sub_bank_0 (
.ciu_l2c_addr_vld_x (ciu_l2c_addr_vld_bank_0 ),
.ciu_l2c_addr_x (ciu_l2c_addr_bank_0 ),
.ciu_l2c_clr_cp_x (ciu_l2c_clr_cp_bank_0 ),
.ciu_l2c_ctcq_req_x (ciu_l2c_ctcq_req_bank_0 ),
.ciu_l2c_data_acc_cycle (ciu_l2c_data_acc_cycle ),
.ciu_l2c_data_setup (ciu_l2c_data_setup ),
.ciu_l2c_data_vld_x (ciu_l2c_data_vld_bank_0 ),
.ciu_l2c_dca_addr_x (ciu_l2c_dca_addr_bank_0 ),
.ciu_l2c_dca_req_x (ciu_l2c_dca_req_bank_0 ),
.ciu_l2c_hpcp_bus_x (ciu_l2c_hpcp_bus_bank_0 ),
.ciu_l2c_icc_mid_x (ciu_l2c_icc_mid_bank_0 ),
.ciu_l2c_icc_type_x (ciu_l2c_icc_type_bank_0 ),
.ciu_l2c_mid_x (ciu_l2c_mid_bank_0 ),
.ciu_l2c_rdl_ready_x (ciu_l2c_rdl_ready_bank_0 ),
.ciu_l2c_rst_req (ciu_l2c_rst_req ),
.ciu_l2c_set_cp_x (ciu_l2c_set_cp_bank_0 ),
.ciu_l2c_sid_x (ciu_l2c_sid_bank_0 ),
.ciu_l2c_snpl2_ready_x (ciu_l2c_snpl2_ready_bank_0 ),
.ciu_l2c_src_x (ciu_l2c_src_bank_0 ),
.ciu_l2c_tag_acc_cycle (ciu_l2c_tag_acc_cycle ),
.ciu_l2c_tag_setup (ciu_l2c_tag_setup ),
.ciu_l2c_type_x (ciu_l2c_type_bank_0 ),
.ciu_l2c_wdata_x (ciu_l2c_wdata_bank_0 ),
.cmp_pref_addr_x (cmp_pref_addr_bank_0 ),
.cmp_pref_cache_miss_x (cmp_pref_cache_miss_bank_0 ),
.cmp_pref_ifu_req_x (cmp_pref_ifu_req_bank_0 ),
.cmp_pref_read_x (cmp_pref_read_bank_0 ),
.cmp_pref_tlb_req_x (cmp_pref_tlb_req_bank_0 ),
.cmp_pref_vld_x (cmp_pref_vld_bank_0 ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (ciu_top_clk ),
.l2c_ciu_addr_ready_x (l2c_ciu_addr_ready_bank_0 ),
.l2c_ciu_cmplt_x (l2c_ciu_cmplt_bank_0 ),
.l2c_ciu_cp_x (l2c_ciu_cp_bank_0 ),
.l2c_ciu_ctcq_cmplt_x (l2c_ciu_ctcq_cmplt_bank_0 ),
.l2c_ciu_ctcq_ready_x (l2c_ciu_ctcq_ready_bank_0 ),
.l2c_ciu_data_ready_gate_x (l2c_ciu_data_ready_gate_bank_0),
.l2c_ciu_data_ready_x (l2c_ciu_data_ready_bank_0 ),
.l2c_ciu_data_x (l2c_ciu_data_bank_0 ),
.l2c_ciu_dca_cmplt_x (l2c_ciu_dca_cmplt_bank_0 ),
.l2c_ciu_dca_data_x (l2c_ciu_dca_data_bank_0 ),
.l2c_ciu_dca_ready_x (l2c_ciu_dca_ready_bank_0 ),
.l2c_ciu_hpcp_acc_inc_x (l2c_ciu_hpcp_acc_inc_bank_0 ),
.l2c_ciu_hpcp_mid_x (l2c_ciu_hpcp_mid_bank_0 ),
.l2c_ciu_hpcp_miss_inc_x (l2c_ciu_hpcp_miss_inc_bank_0 ),
.l2c_ciu_rdl_addr_x (l2c_ciu_rdl_addr_bank_0 ),
.l2c_ciu_rdl_dvld_x (l2c_ciu_rdl_dvld_bank_0 ),
.l2c_ciu_rdl_mid_x (l2c_ciu_rdl_mid_bank_0 ),
.l2c_ciu_rdl_prot_x (l2c_ciu_rdl_prot_bank_0 ),
.l2c_ciu_rdl_rvld_x (l2c_ciu_rdl_rvld_bank_0 ),
.l2c_ciu_resp_x (l2c_ciu_resp_bank_0 ),
.l2c_ciu_sid_x (l2c_ciu_sid_bank_0 ),
.l2c_ciu_snpl2_addr_x (l2c_ciu_snpl2_addr_bank_0 ),
.l2c_ciu_snpl2_ini_sid_x (l2c_ciu_snpl2_ini_sid_bank_0 ),
.l2c_ciu_snpl2_vld_x (l2c_ciu_snpl2_vld_bank_0 ),
.l2c_data_clk_x (l2c_data_clk_bank_0 ),
.l2c_data_ram_clk_en_x (l2c_data_ram_clk_en_bank_0 ),
.l2c_dbg_info_x (l2c_dbg_info_bank_0 ),
.l2c_flush_done_x (l2c_flush_done_bank_0 ),
.l2c_flush_req_x (l2c_flush_req_bank_0 ),
.l2c_icg_en (l2c_icg_en ),
.l2c_no_op_x (l2c_no_op_bank_0 ),
.l2c_tag_clk_x (l2c_tag_clk_bank_0 ),
.l2c_tag_ram_clk_en_x (l2c_tag_ram_clk_en_bank_0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @154
// .forever_cpuclk (ciu_top_clk ) @155
// ); @156
// &ConnRule(s/_x$/_bank_1/); @158
// &Instance("ct_l2c_sub_bank","x_ct_l2c_sub_bank_1"); @159
ct_l2c_sub_bank x_ct_l2c_sub_bank_1 (
.ciu_l2c_addr_vld_x (ciu_l2c_addr_vld_bank_1 ),
.ciu_l2c_addr_x (ciu_l2c_addr_bank_1 ),
.ciu_l2c_clr_cp_x (ciu_l2c_clr_cp_bank_1 ),
.ciu_l2c_ctcq_req_x (ciu_l2c_ctcq_req_bank_1 ),
.ciu_l2c_data_acc_cycle (ciu_l2c_data_acc_cycle ),
.ciu_l2c_data_setup (ciu_l2c_data_setup ),
.ciu_l2c_data_vld_x (ciu_l2c_data_vld_bank_1 ),
.ciu_l2c_dca_addr_x (ciu_l2c_dca_addr_bank_1 ),
.ciu_l2c_dca_req_x (ciu_l2c_dca_req_bank_1 ),
.ciu_l2c_hpcp_bus_x (ciu_l2c_hpcp_bus_bank_1 ),
.ciu_l2c_icc_mid_x (ciu_l2c_icc_mid_bank_1 ),
.ciu_l2c_icc_type_x (ciu_l2c_icc_type_bank_1 ),
.ciu_l2c_mid_x (ciu_l2c_mid_bank_1 ),
.ciu_l2c_rdl_ready_x (ciu_l2c_rdl_ready_bank_1 ),
.ciu_l2c_rst_req (ciu_l2c_rst_req ),
.ciu_l2c_set_cp_x (ciu_l2c_set_cp_bank_1 ),
.ciu_l2c_sid_x (ciu_l2c_sid_bank_1 ),
.ciu_l2c_snpl2_ready_x (ciu_l2c_snpl2_ready_bank_1 ),
.ciu_l2c_src_x (ciu_l2c_src_bank_1 ),
.ciu_l2c_tag_acc_cycle (ciu_l2c_tag_acc_cycle ),
.ciu_l2c_tag_setup (ciu_l2c_tag_setup ),
.ciu_l2c_type_x (ciu_l2c_type_bank_1 ),
.ciu_l2c_wdata_x (ciu_l2c_wdata_bank_1 ),
.cmp_pref_addr_x (cmp_pref_addr_bank_1 ),
.cmp_pref_cache_miss_x (cmp_pref_cache_miss_bank_1 ),
.cmp_pref_ifu_req_x (cmp_pref_ifu_req_bank_1 ),
.cmp_pref_read_x (cmp_pref_read_bank_1 ),
.cmp_pref_tlb_req_x (cmp_pref_tlb_req_bank_1 ),
.cmp_pref_vld_x (cmp_pref_vld_bank_1 ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (ciu_top_clk ),
.l2c_ciu_addr_ready_x (l2c_ciu_addr_ready_bank_1 ),
.l2c_ciu_cmplt_x (l2c_ciu_cmplt_bank_1 ),
.l2c_ciu_cp_x (l2c_ciu_cp_bank_1 ),
.l2c_ciu_ctcq_cmplt_x (l2c_ciu_ctcq_cmplt_bank_1 ),
.l2c_ciu_ctcq_ready_x (l2c_ciu_ctcq_ready_bank_1 ),
.l2c_ciu_data_ready_gate_x (l2c_ciu_data_ready_gate_bank_1),
.l2c_ciu_data_ready_x (l2c_ciu_data_ready_bank_1 ),
.l2c_ciu_data_x (l2c_ciu_data_bank_1 ),
.l2c_ciu_dca_cmplt_x (l2c_ciu_dca_cmplt_bank_1 ),
.l2c_ciu_dca_data_x (l2c_ciu_dca_data_bank_1 ),
.l2c_ciu_dca_ready_x (l2c_ciu_dca_ready_bank_1 ),
.l2c_ciu_hpcp_acc_inc_x (l2c_ciu_hpcp_acc_inc_bank_1 ),
.l2c_ciu_hpcp_mid_x (l2c_ciu_hpcp_mid_bank_1 ),
.l2c_ciu_hpcp_miss_inc_x (l2c_ciu_hpcp_miss_inc_bank_1 ),
.l2c_ciu_rdl_addr_x (l2c_ciu_rdl_addr_bank_1 ),
.l2c_ciu_rdl_dvld_x (l2c_ciu_rdl_dvld_bank_1 ),
.l2c_ciu_rdl_mid_x (l2c_ciu_rdl_mid_bank_1 ),
.l2c_ciu_rdl_prot_x (l2c_ciu_rdl_prot_bank_1 ),
.l2c_ciu_rdl_rvld_x (l2c_ciu_rdl_rvld_bank_1 ),
.l2c_ciu_resp_x (l2c_ciu_resp_bank_1 ),
.l2c_ciu_sid_x (l2c_ciu_sid_bank_1 ),
.l2c_ciu_snpl2_addr_x (l2c_ciu_snpl2_addr_bank_1 ),
.l2c_ciu_snpl2_ini_sid_x (l2c_ciu_snpl2_ini_sid_bank_1 ),
.l2c_ciu_snpl2_vld_x (l2c_ciu_snpl2_vld_bank_1 ),
.l2c_data_clk_x (l2c_data_clk_bank_1 ),
.l2c_data_ram_clk_en_x (l2c_data_ram_clk_en_bank_1 ),
.l2c_dbg_info_x (l2c_dbg_info_bank_1 ),
.l2c_flush_done_x (l2c_flush_done_bank_1 ),
.l2c_flush_req_x (l2c_flush_req_bank_1 ),
.l2c_icg_en (l2c_icg_en ),
.l2c_no_op_x (l2c_no_op_bank_1 ),
.l2c_tag_clk_x (l2c_tag_clk_bank_1 ),
.l2c_tag_ram_clk_en_x (l2c_tag_ram_clk_en_bank_1 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @160
// .forever_cpuclk (ciu_top_clk ) @161
// ); @162
// &Instance("ct_l2c_prefetch","x_ct_l2c_prefetch"); @164
ct_l2c_prefetch x_ct_l2c_prefetch (
.ciu_l2c_iprf (ciu_l2c_iprf ),
.ciu_l2c_prf_ready (ciu_l2c_prf_ready ),
.ciu_l2c_tprf (ciu_l2c_tprf ),
.cmp_pref_addr_bank_0 (cmp_pref_addr_bank_0 ),
.cmp_pref_addr_bank_1 (cmp_pref_addr_bank_1 ),
.cmp_pref_cache_miss_bank_0 (cmp_pref_cache_miss_bank_0),
.cmp_pref_cache_miss_bank_1 (cmp_pref_cache_miss_bank_1),
.cmp_pref_ifu_req_bank_0 (cmp_pref_ifu_req_bank_0 ),
.cmp_pref_ifu_req_bank_1 (cmp_pref_ifu_req_bank_1 ),
.cmp_pref_read_bank_0 (cmp_pref_read_bank_0 ),
.cmp_pref_read_bank_1 (cmp_pref_read_bank_1 ),
.cmp_pref_tlb_req_bank_0 (cmp_pref_tlb_req_bank_0 ),
.cmp_pref_tlb_req_bank_1 (cmp_pref_tlb_req_bank_1 ),
.cmp_pref_vld_bank_0 (cmp_pref_vld_bank_0 ),
.cmp_pref_vld_bank_1 (cmp_pref_vld_bank_1 ),
.cpurst_b (cpurst_b ),
.forever_cpuclk (ciu_top_clk ),
.l2c_ciu_prf_addr (l2c_ciu_prf_addr ),
.l2c_ciu_prf_prot (l2c_ciu_prf_prot ),
.l2c_ciu_prf_vld (l2c_ciu_prf_vld ),
.l2c_icg_en (l2c_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.prf_idle (prf_idle )
);
// &Connect( @165
// .forever_cpuclk (ciu_top_clk ) @166
// ); @167
//==========================================================
//debug information
//==========================================================
assign l2c_ciu_dbg_info[43:0] = {l2c_dbg_info_bank_1[21:0],l2c_dbg_info_bank_0[21:0]};
// &ModuleEnd; @196
endmodule |
module ct_l2c_prefetch(
ciu_l2c_iprf,
ciu_l2c_prf_ready,
ciu_l2c_tprf,
cmp_pref_addr_bank_0,
cmp_pref_addr_bank_1,
cmp_pref_cache_miss_bank_0,
cmp_pref_cache_miss_bank_1,
cmp_pref_ifu_req_bank_0,
cmp_pref_ifu_req_bank_1,
cmp_pref_read_bank_0,
cmp_pref_read_bank_1,
cmp_pref_tlb_req_bank_0,
cmp_pref_tlb_req_bank_1,
cmp_pref_vld_bank_0,
cmp_pref_vld_bank_1,
cpurst_b,
forever_cpuclk,
l2c_ciu_prf_addr,
l2c_ciu_prf_prot,
l2c_ciu_prf_vld,
l2c_icg_en,
pad_yy_icg_scan_en,
prf_idle
);
// &Ports; @23
input [1 :0] ciu_l2c_iprf;
input ciu_l2c_prf_ready;
input ciu_l2c_tprf;
input [32:0] cmp_pref_addr_bank_0;
input [32:0] cmp_pref_addr_bank_1;
input cmp_pref_cache_miss_bank_0;
input cmp_pref_cache_miss_bank_1;
input cmp_pref_ifu_req_bank_0;
input cmp_pref_ifu_req_bank_1;
input cmp_pref_read_bank_0;
input cmp_pref_read_bank_1;
input cmp_pref_tlb_req_bank_0;
input cmp_pref_tlb_req_bank_1;
input cmp_pref_vld_bank_0;
input cmp_pref_vld_bank_1;
input cpurst_b;
input forever_cpuclk;
input l2c_icg_en;
input pad_yy_icg_scan_en;
output [33:0] l2c_ciu_prf_addr;
output [2 :0] l2c_ciu_prf_prot;
output l2c_ciu_prf_vld;
output prf_idle;
// &Regs; @24
reg [33:0] pref_addr;
reg [1 :0] pref_cnt;
reg pref_next_state;
reg pref_state;
reg pref_tlb;
// &Wires; @25
wire bank1_sel;
wire ciu_accepted;
wire ciu_ipref_en;
wire [1 :0] ciu_l2c_iprf;
wire ciu_l2c_prf_ready;
wire ciu_l2c_tprf;
wire ciu_tpref_en;
wire [33:0] cmp_pref_addr;
wire [32:0] cmp_pref_addr_bank_0;
wire [32:0] cmp_pref_addr_bank_1;
wire cmp_pref_addr_cross_page;
wire cmp_pref_cache_miss_bank_0;
wire cmp_pref_cache_miss_bank_1;
wire cmp_pref_ifu_req_bank_0;
wire cmp_pref_ifu_req_bank_1;
wire cmp_pref_read_bank_0;
wire cmp_pref_read_bank_1;
wire cmp_pref_tlb_req_bank_0;
wire cmp_pref_tlb_req_bank_1;
wire cmp_pref_vld_bank_0;
wire cmp_pref_vld_bank_1;
wire cpurst_b;
wire cross_page;
wire forever_cpuclk;
wire [1 :0] iprf_cnt;
wire [33:0] l2c_ciu_prf_addr;
wire [2 :0] l2c_ciu_prf_prot;
wire l2c_ciu_prf_vld;
wire l2c_icg_en;
wire l2c_pref_clk;
wire l2c_pref_clk_en;
wire pad_yy_icg_scan_en;
wire [33:0] pref_addr_bank0;
wire [33:0] pref_addr_bank1;
wire pref_addr_update;
wire pref_en;
wire pref_en_0;
wire pref_en_1;
wire pref_last;
wire [33:0] pref_next_addr;
wire [33:0] pref_updt_addr;
wire pref_updt_tlb_req;
wire prf_idle;
parameter IDLE = 1'b0;
parameter PREF = 1'b1;
assign l2c_ciu_prf_vld = (pref_state == PREF);
assign l2c_ciu_prf_addr[33:0] = pref_addr[33:0] ;
assign l2c_ciu_prf_prot[2 :0] = {!pref_tlb,2'b11} ;
assign l2c_pref_clk_en = pref_addr_update || ciu_accepted;
// &Instance("gated_clk_cell", "x_l2c_pref_gated_clk"); @35
gated_clk_cell x_l2c_pref_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (l2c_pref_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2c_pref_clk_en ),
.module_en (l2c_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk ), @36
// .external_en (1'b0 ), @37
// .global_en (1'b1 ), @38
// .module_en (l2c_icg_en ), @39
// .local_en (l2c_pref_clk_en ), @40
// .clk_out (l2c_pref_clk ) @41
// ); @42
always@(posedge l2c_pref_clk or negedge cpurst_b)
begin
if(!cpurst_b)
pref_state <= IDLE;
else
pref_state <= pref_next_state;
end
assign ciu_ipref_en = (ciu_l2c_iprf[1:0] != 2'b00);
assign ciu_tpref_en = (ciu_l2c_tprf != 1'b0 );
assign pref_en_0 = cmp_pref_vld_bank_0 &&
cmp_pref_read_bank_0 &&
(cmp_pref_ifu_req_bank_0 && ciu_ipref_en ||
cmp_pref_tlb_req_bank_0 && ciu_tpref_en) &&
cmp_pref_cache_miss_bank_0;
assign pref_en_1 = cmp_pref_vld_bank_1 &&
cmp_pref_read_bank_1 &&
(cmp_pref_ifu_req_bank_1 && ciu_ipref_en ||
cmp_pref_tlb_req_bank_1 && ciu_tpref_en) &&
cmp_pref_cache_miss_bank_1;
assign pref_en = (pref_en_0 || pref_en_1) && !cmp_pref_addr_cross_page;
// &CombBeg; @69
always @( cross_page
or pref_state
or pref_en
or ciu_accepted
or pref_last)
begin
case(pref_state)
IDLE:
begin
if(pref_en)
pref_next_state = PREF;
else
pref_next_state = IDLE;
end
PREF:
begin
if(ciu_accepted && (pref_last || cross_page))
pref_next_state = IDLE;
else
pref_next_state = PREF;
end
default:
pref_next_state = IDLE;
endcase
// &CombEnd; @88
end
assign pref_addr_update = pref_en && (pref_state == IDLE);
assign ciu_accepted = ciu_l2c_prf_ready;
assign pref_last = pref_cnt[1:0] == 2'b00;
//===============================================
// prefetch buffer
//===============================================
assign bank1_sel = cmp_pref_cache_miss_bank_1 &&
(cmp_pref_ifu_req_bank_1 || cmp_pref_tlb_req_bank_1) &&
cmp_pref_vld_bank_1;
assign pref_addr_bank1[33:0] = {cmp_pref_addr_bank_1[32:0],1'b1};
assign pref_addr_bank0[33:0] = {cmp_pref_addr_bank_0[32:0],1'b0};
assign cmp_pref_addr[33:0] = bank1_sel ? pref_addr_bank1[33:0] : pref_addr_bank0[33:0];
assign pref_updt_tlb_req = bank1_sel ? cmp_pref_tlb_req_bank_1 : cmp_pref_tlb_req_bank_0;
assign cmp_pref_addr_cross_page = cmp_pref_addr[6] ^ pref_updt_addr[6];
assign pref_updt_addr[33:0] = cmp_pref_addr[33:0] + 34'b1;
assign pref_next_addr[33:0] = pref_addr[33:0] + 34'b1;
assign iprf_cnt[1:0] = ciu_l2c_iprf[1:0] - 2'b1;
always@(posedge l2c_pref_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pref_addr[33:0] <= 34'b0;
pref_tlb <= 1'b0 ;
pref_cnt[1:0] <= 2'b0;
end
else if(pref_addr_update)
begin
pref_addr[33:0] <= pref_updt_addr[33:0];
pref_tlb <= pref_updt_tlb_req ;
pref_cnt[1:0] <= pref_updt_tlb_req ? 2'b00 : iprf_cnt[1:0];
end
else if(ciu_accepted)
begin
pref_addr[33:0] <= pref_next_addr[33:0];
pref_tlb <= pref_tlb ;
pref_cnt[1:0] <= pref_cnt[1:0] - 2'b1;
end
else
begin
pref_addr[33:0] <= pref_addr[33:0] ;
pref_tlb <= pref_tlb ;
pref_cnt[1:0] <= pref_cnt[1:0];
end
end
assign cross_page = (pref_addr[6] ^ pref_next_addr[6]);
assign prf_idle = pref_state == IDLE;
// &ModuleEnd; @148
endmodule |
module ct_l2cache_top(
l2c_data_clk_x,
l2c_data_din,
l2c_data_dout,
l2c_data_index0,
l2c_data_index1,
l2c_data_index2,
l2c_data_index3,
l2c_data_ram_cen,
l2c_data_wen,
l2c_dirty_din,
l2c_dirty_dout,
l2c_dirty_gwen,
l2c_dirty_ram_cen,
l2c_dirty_wen,
l2c_tag_clk_x,
l2c_tag_din,
l2c_tag_dout,
l2c_tag_gwen,
l2c_tag_index,
l2c_tag_ram_cen,
l2c_tag_wen,
pad_yy_icg_scan_en
);
// &Ports; @26
input l2c_data_clk_x;
input [511:0] l2c_data_din;
input [12 :0] l2c_data_index0;
input [12 :0] l2c_data_index1;
input [12 :0] l2c_data_index2;
input [12 :0] l2c_data_index3;
input [3 :0] l2c_data_ram_cen;
input [3 :0] l2c_data_wen;
input [143:0] l2c_dirty_din;
input l2c_dirty_gwen;
input l2c_dirty_ram_cen;
input [143:0] l2c_dirty_wen;
input l2c_tag_clk_x;
input [383:0] l2c_tag_din;
input l2c_tag_gwen;
input [8 :0] l2c_tag_index;
input l2c_tag_ram_cen;
input [383:0] l2c_tag_wen;
input pad_yy_icg_scan_en;
output [511:0] l2c_data_dout;
output [143:0] l2c_dirty_dout;
output [383:0] l2c_tag_dout;
// &Regs; @27
// &Wires; @28
wire l2c_data_clk;
wire l2c_data_clk_x;
wire [511:0] l2c_data_din;
wire [511:0] l2c_data_dout;
wire [3 :0] l2c_data_gwen;
wire [12 :0] l2c_data_index0;
wire [12 :0] l2c_data_index1;
wire [12 :0] l2c_data_index2;
wire [12 :0] l2c_data_index3;
wire [3 :0] l2c_data_ram_cen;
wire [3 :0] l2c_data_wen;
wire [127:0] l2c_data_wen0;
wire [127:0] l2c_data_wen1;
wire [127:0] l2c_data_wen2;
wire [127:0] l2c_data_wen3;
wire [143:0] l2c_dirty_din;
wire [143:0] l2c_dirty_dout;
wire l2c_dirty_gwen;
wire l2c_dirty_ram_cen;
wire [143:0] l2c_dirty_wen;
wire l2c_tag_clk;
wire l2c_tag_clk_x;
wire [383:0] l2c_tag_din;
wire [383:0] l2c_tag_dout;
wire l2c_tag_gwen;
wire [8 :0] l2c_tag_index;
wire l2c_tag_ram_cen;
wire [383:0] l2c_tag_wen;
wire pad_yy_icg_scan_en;
assign l2c_tag_clk = l2c_tag_clk_x;
assign l2c_data_clk = l2c_data_clk_x;
//==========================================================
// Instance l2c cache array
//==========================================================
//---------------------tag and dirty------------------------
// &Instance("ct_l2cache_tag_array_8way", "x_ct_l2cache_tag_array"); @38
// &Instance("ct_l2cache_tag_array_16way", "x_ct_l2cache_tag_array"); @41
ct_l2cache_tag_array_16way x_ct_l2cache_tag_array (
.tag_cen (l2c_tag_ram_cen),
.tag_clk (l2c_tag_clk ),
.tag_din (l2c_tag_din ),
.tag_dout (l2c_tag_dout ),
.tag_gwen (l2c_tag_gwen ),
.tag_idx (l2c_tag_index ),
.tag_wen (l2c_tag_wen )
);
// &Connect( @43
// .tag_clk (l2c_tag_clk ), @44
// .tag_cen (l2c_tag_ram_cen ), @45
// .tag_wen (l2c_tag_wen ), @46
// .tag_din (l2c_tag_din ), @47
// .tag_idx (l2c_tag_index ), @48
// .tag_gwen (l2c_tag_gwen ), @49
// .tag_dout (l2c_tag_dout )); @50
// &Instance("ct_l2cache_dirty_array_8way", "x_ct_l2cache_dirty_array"); @53
// &Instance("ct_l2cache_dirty_array_16way", "x_ct_l2cache_dirty_array"); @56
ct_l2cache_dirty_array_16way x_ct_l2cache_dirty_array (
.dirty_cen (l2c_dirty_ram_cen),
.dirty_clk (l2c_tag_clk ),
.dirty_din (l2c_dirty_din ),
.dirty_dout (l2c_dirty_dout ),
.dirty_gwen (l2c_dirty_gwen ),
.dirty_idx (l2c_tag_index ),
.dirty_wen (l2c_dirty_wen )
);
// &Connect( @58
// .dirty_clk (l2c_tag_clk ), @59
// .dirty_cen (l2c_dirty_ram_cen ), @60
// .dirty_idx (l2c_tag_index ), @61
// .dirty_wen (l2c_dirty_wen ), @62
// .dirty_din (l2c_dirty_din ), @63
// .dirty_gwen (l2c_dirty_gwen ), @64
// .dirty_dout (l2c_dirty_dout )); @65
//-------------------------data-----------------------------
assign l2c_data_gwen[3:0] = l2c_data_wen[3:0];
assign l2c_data_wen0[127:0] = {128{l2c_data_wen[0]}};
assign l2c_data_wen1[127:0] = {128{l2c_data_wen[1]}};
assign l2c_data_wen2[127:0] = {128{l2c_data_wen[2]}};
assign l2c_data_wen3[127:0] = {128{l2c_data_wen[3]}};
// &Instance("ct_l2cache_data_array", "x_ct_l2cache_data_array_bank0"); @74
ct_l2cache_data_array x_ct_l2cache_data_array_bank0 (
.data_cen (l2c_data_ram_cen[0] ),
.data_clk (l2c_data_clk ),
.data_din (l2c_data_din[127:0] ),
.data_dout (l2c_data_dout[127:0]),
.data_gwen (l2c_data_gwen[0] ),
.data_idx (l2c_data_index0 ),
.data_wen (l2c_data_wen0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @75
// .data_clk (l2c_data_clk ), @76
// .data_cen (l2c_data_ram_cen[0] ), @77
// .data_wen (l2c_data_wen0 ), @78
// .data_din (l2c_data_din[127:0] ), @79
// .data_idx (l2c_data_index0 ), @80
// .data_gwen (l2c_data_gwen[0] ), @81
// .data_dout (l2c_data_dout[127:0] )); @82
// &Instance("ct_l2cache_data_array", "x_ct_l2cache_data_array_bank1"); @85
ct_l2cache_data_array x_ct_l2cache_data_array_bank1 (
.data_cen (l2c_data_ram_cen[1] ),
.data_clk (l2c_data_clk ),
.data_din (l2c_data_din[255:128] ),
.data_dout (l2c_data_dout[255:128]),
.data_gwen (l2c_data_gwen[1] ),
.data_idx (l2c_data_index1 ),
.data_wen (l2c_data_wen1 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @86
// .data_clk (l2c_data_clk ), @87
// .data_cen (l2c_data_ram_cen[1] ), @88
// .data_wen (l2c_data_wen1 ), @89
// .data_din (l2c_data_din[255:128] ), @90
// .data_idx (l2c_data_index1 ), @91
// .data_gwen (l2c_data_gwen[1] ), @92
// .data_dout (l2c_data_dout[255:128] )); @93
// &Instance("ct_l2cache_data_array", "x_ct_l2cache_data_array_bank2"); @95
ct_l2cache_data_array x_ct_l2cache_data_array_bank2 (
.data_cen (l2c_data_ram_cen[2] ),
.data_clk (l2c_data_clk ),
.data_din (l2c_data_din[383:256] ),
.data_dout (l2c_data_dout[383:256]),
.data_gwen (l2c_data_gwen[2] ),
.data_idx (l2c_data_index2 ),
.data_wen (l2c_data_wen2 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @96
// .data_clk (l2c_data_clk ), @97
// .data_cen (l2c_data_ram_cen[2] ), @98
// .data_wen (l2c_data_wen2 ), @99
// .data_din (l2c_data_din[383:256] ), @100
// .data_idx (l2c_data_index2 ), @101
// .data_gwen (l2c_data_gwen[2] ), @102
// .data_dout (l2c_data_dout[383:256] )); @103
// &Instance("ct_l2cache_data_array", "x_ct_l2cache_data_array_bank3"); @105
ct_l2cache_data_array x_ct_l2cache_data_array_bank3 (
.data_cen (l2c_data_ram_cen[3] ),
.data_clk (l2c_data_clk ),
.data_din (l2c_data_din[511:384] ),
.data_dout (l2c_data_dout[511:384]),
.data_gwen (l2c_data_gwen[3] ),
.data_idx (l2c_data_index3 ),
.data_wen (l2c_data_wen3 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( @106
// .data_clk (l2c_data_clk ), @107
// .data_cen (l2c_data_ram_cen[3] ), @108
// .data_wen (l2c_data_wen3 ), @109
// .data_din (l2c_data_din[511:384] ), @110
// .data_idx (l2c_data_index3 ), @111
// .data_gwen (l2c_data_gwen[3] ), @112
// .data_dout (l2c_data_dout[511:384] )); @113
// &Instance("ct_l2cache_tag_ecc_array_8way", "x_ct_l2cache_tag_ecc_array"); @117
// &Instance("ct_l2cache_tag_ecc_array_16way", "x_ct_l2cache_tag_ecc_array"); @120
// &Connect( @122
// .ecc_clk (l2c_tag_clk ), @123
// .ecc_cen (l2c_tag_ram_cen ), @124
// .ecc_gwen (l2c_tag_gwen ), @125
// .ecc_idx (l2c_tag_index ), @126
// .ecc_wen (l2c_tag_ecc_wen ), @127
// .ecc_din (l2c_tag_ecc_din ), @128
// .ecc_dout (l2c_tag_ecc_dout )); @129
// &Instance("ct_l2cache_dirty_ecc_array_8way", "x_ct_l2cache_dirty_ecc_array"); @132
// &Instance("ct_l2cache_dirty_ecc_array_16way", "x_ct_l2cache_dirty_ecc_array"); @135
// &Connect( @137
// .ecc_clk (l2c_tag_clk ), @138
// .ecc_cen (l2c_dirty_ram_cen ), @139
// .ecc_idx (l2c_tag_index ), @140
// .ecc_gwen (l2c_dirty_gwen ), @141
// .ecc_wen (l2c_dirty_ecc_wen ), @142
// .ecc_din (l2c_dirty_ecc_din ), @143
// .ecc_dout (l2c_dirty_ecc_dout )); @144
// &Instance("ct_l2cache_data_ecc_array", "x_ct_l2cache_data_ecc_array"); @149
// &Connect( @150
// .ecc_clk (l2c_data_clk ), @151
// .ecc_cen (l2c_ecc_ram_cen ), @152
// .ecc_wen (l2c_ecc_wen_extend ), @153
// .ecc_din (l2c_ecc_din ), @154
// .ecc_idx (l2c_ecc_index ), @155
// .ecc_gwen (l2c_ecc_gwen ), @156
// .ecc_dout (l2c_ecc_dout )); @157
// &Force("nonport","l2c_tag_setup_violation"); @176
// &Force("nonport","l2c_tag_latency_violation"); @190
// &Force("nonport","l2c_dirty_setup_violation"); @222
// &Force("nonport","l2c_dirty_latency_violation"); @236
// &Force("nonport","l2c_data0_setup_violation"); @268
// &Force("nonport","l2c_data0_latency_violation"); @282
// &Force("nonport","l2c_data1_setup_violation"); @314
// &Force("nonport","l2c_data1_latency_violation"); @328
// &Force("nonport","l2c_data2_setup_violation"); @360
// &Force("nonport","l2c_data2_latency_violation"); @374
// &Force("nonport","l2c_data3_setup_violation"); @406
// &Force("nonport","l2c_data3_latency_violation"); @420
// &ModuleEnd; @440
endmodule |
module ct_rtu_expand_8(
x_num,
x_num_expand
);
// &Ports; @25
input [2:0] x_num;
output [7:0] x_num_expand;
// &Regs; @26
// &Wires; @27
wire [2:0] x_num;
wire [7:0] x_num_expand;
//==========================================================
// expand 3 bits number to 8 bits one-hot number
//==========================================================
assign x_num_expand[0] = (x_num[2:0] == 3'd0);
assign x_num_expand[1] = (x_num[2:0] == 3'd1);
assign x_num_expand[2] = (x_num[2:0] == 3'd2);
assign x_num_expand[3] = (x_num[2:0] == 3'd3);
assign x_num_expand[4] = (x_num[2:0] == 3'd4);
assign x_num_expand[5] = (x_num[2:0] == 3'd5);
assign x_num_expand[6] = (x_num[2:0] == 3'd6);
assign x_num_expand[7] = (x_num[2:0] == 3'd7);
// &ModuleEnd; @41
endmodule |
module ct_rtu_pst_vreg_entry(
cp0_rtu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dealloc_vld_for_gateclk,
idu_rtu_pst_dis_inst0_dstv_reg,
idu_rtu_pst_dis_inst0_rel_vreg,
idu_rtu_pst_dis_inst0_vreg_iid,
idu_rtu_pst_dis_inst1_dstv_reg,
idu_rtu_pst_dis_inst1_rel_vreg,
idu_rtu_pst_dis_inst1_vreg_iid,
idu_rtu_pst_dis_inst2_dstv_reg,
idu_rtu_pst_dis_inst2_rel_vreg,
idu_rtu_pst_dis_inst2_vreg_iid,
idu_rtu_pst_dis_inst3_dstv_reg,
idu_rtu_pst_dis_inst3_rel_vreg,
idu_rtu_pst_dis_inst3_vreg_iid,
ifu_xx_sync_reset,
pad_yy_icg_scan_en,
retire_pst_async_flush,
retire_pst_wb_retire_inst0_vreg_vld,
retire_pst_wb_retire_inst1_vreg_vld,
retire_pst_wb_retire_inst2_vreg_vld,
rob_pst_retire_inst0_gateclk_vld,
rob_pst_retire_inst0_iid_updt_val,
rob_pst_retire_inst1_gateclk_vld,
rob_pst_retire_inst1_iid_updt_val,
rob_pst_retire_inst2_gateclk_vld,
rob_pst_retire_inst2_iid_updt_val,
rtu_yy_xx_flush,
vreg_top_clk,
x_create_vld,
x_cur_state_alloc_release,
x_cur_state_dealloc,
x_dealloc_mask,
x_dealloc_vld,
x_dreg,
x_rel_vreg_expand,
x_release_vld,
x_reset_dstv_reg,
x_reset_mapped,
x_retired_released_wb,
x_wb_vld
);
// &Ports; @28
input cp0_rtu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dealloc_vld_for_gateclk;
input [4 :0] idu_rtu_pst_dis_inst0_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst0_rel_vreg;
input [6 :0] idu_rtu_pst_dis_inst0_vreg_iid;
input [4 :0] idu_rtu_pst_dis_inst1_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst1_rel_vreg;
input [6 :0] idu_rtu_pst_dis_inst1_vreg_iid;
input [4 :0] idu_rtu_pst_dis_inst2_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst2_rel_vreg;
input [6 :0] idu_rtu_pst_dis_inst2_vreg_iid;
input [4 :0] idu_rtu_pst_dis_inst3_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst3_rel_vreg;
input [6 :0] idu_rtu_pst_dis_inst3_vreg_iid;
input ifu_xx_sync_reset;
input pad_yy_icg_scan_en;
input retire_pst_async_flush;
input retire_pst_wb_retire_inst0_vreg_vld;
input retire_pst_wb_retire_inst1_vreg_vld;
input retire_pst_wb_retire_inst2_vreg_vld;
input rob_pst_retire_inst0_gateclk_vld;
input [6 :0] rob_pst_retire_inst0_iid_updt_val;
input rob_pst_retire_inst1_gateclk_vld;
input [6 :0] rob_pst_retire_inst1_iid_updt_val;
input rob_pst_retire_inst2_gateclk_vld;
input [6 :0] rob_pst_retire_inst2_iid_updt_val;
input rtu_yy_xx_flush;
input vreg_top_clk;
input [3 :0] x_create_vld;
input x_dealloc_mask;
input x_dealloc_vld;
input x_release_vld;
input [4 :0] x_reset_dstv_reg;
input x_reset_mapped;
input x_wb_vld;
output x_cur_state_alloc_release;
output x_cur_state_dealloc;
output [31:0] x_dreg;
output [63:0] x_rel_vreg_expand;
output x_retired_released_wb;
// &Regs; @29
reg [4 :0] create_dstv_reg;
reg [6 :0] create_iid;
reg [5 :0] create_rel_vreg;
reg [4 :0] dstv_reg;
reg [6 :0] iid;
reg [4 :0] lifecycle_cur_state;
reg [4 :0] lifecycle_next_state;
reg [5 :0] rel_vreg;
reg retire_inst0_iid_match;
reg retire_inst1_iid_match;
reg retire_inst2_iid_match;
reg wb_cur_state;
reg wb_next_state;
// &Wires; @30
wire alloc_clk;
wire alloc_clk_en;
wire cp0_rtu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_vld;
wire dealloc_vld_for_gateclk;
wire [31:0] dstv_reg_expand;
wire [4 :0] idu_rtu_pst_dis_inst0_dstv_reg;
wire [5 :0] idu_rtu_pst_dis_inst0_rel_vreg;
wire [6 :0] idu_rtu_pst_dis_inst0_vreg_iid;
wire [4 :0] idu_rtu_pst_dis_inst1_dstv_reg;
wire [5 :0] idu_rtu_pst_dis_inst1_rel_vreg;
wire [6 :0] idu_rtu_pst_dis_inst1_vreg_iid;
wire [4 :0] idu_rtu_pst_dis_inst2_dstv_reg;
wire [5 :0] idu_rtu_pst_dis_inst2_rel_vreg;
wire [6 :0] idu_rtu_pst_dis_inst2_vreg_iid;
wire [4 :0] idu_rtu_pst_dis_inst3_dstv_reg;
wire [5 :0] idu_rtu_pst_dis_inst3_rel_vreg;
wire [6 :0] idu_rtu_pst_dis_inst3_vreg_iid;
wire ifu_xx_sync_reset;
wire lifecycle_cur_state_alloc;
wire lifecycle_cur_state_dealloc;
wire lifecycle_cur_state_release;
wire lifecycle_cur_state_retire;
wire pad_yy_icg_scan_en;
wire rel_retire_vld;
wire [63:0] rel_vreg_expand;
wire [4 :0] reset_lifecycle_state;
wire reset_wb_state;
wire retire_gateclk_vld;
wire retire_inst0_iid_match_updt_val;
wire retire_inst1_iid_match_updt_val;
wire retire_inst2_iid_match_updt_val;
wire retire_inst_iid_match_gateclk_en;
wire retire_pst_async_flush;
wire retire_pst_wb_retire_inst0_vreg_vld;
wire retire_pst_wb_retire_inst1_vreg_vld;
wire retire_pst_wb_retire_inst2_vreg_vld;
wire retire_vld;
wire rob_pst_retire_inst0_gateclk_vld;
wire [6 :0] rob_pst_retire_inst0_iid_updt_val;
wire rob_pst_retire_inst1_gateclk_vld;
wire [6 :0] rob_pst_retire_inst1_iid_updt_val;
wire rob_pst_retire_inst2_gateclk_vld;
wire [6 :0] rob_pst_retire_inst2_iid_updt_val;
wire rtu_yy_xx_flush;
wire sm_clk;
wire sm_clk_en;
wire vreg_top_clk;
wire wb_cur_state_wb;
wire wb_cur_state_wb_masked;
wire [3 :0] x_create_vld;
wire x_cur_state_alloc_release;
wire x_cur_state_dealloc;
wire x_dealloc_mask;
wire x_dealloc_vld;
wire [31:0] x_dreg;
wire [63:0] x_rel_vreg_expand;
wire x_release_vld;
wire [4 :0] x_reset_dstv_reg;
wire x_reset_mapped;
wire x_retired_released_wb;
wire x_wb_vld;
parameter DEALLOC = 5'b00001;
parameter WF_ALLOC = 5'b00010;
parameter ALLOC = 5'b00100;
parameter RETIRE = 5'b01000;
parameter RELEASE = 5'b10000;
parameter IDLE = 1'b0;
parameter WB = 1'b1;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign sm_clk_en = rtu_yy_xx_flush
|| retire_pst_async_flush
|| ifu_xx_sync_reset
|| dealloc_vld_for_gateclk
&& lifecycle_cur_state_dealloc
|| (lifecycle_cur_state[4:0] == RETIRE)
&& retire_gateclk_vld
// && x_release_vld
|| x_wb_vld
|| (lifecycle_cur_state[4:0] == WF_ALLOC)
&& create_vld
|| lifecycle_cur_state_alloc
&& (retire_vld || retire_inst_iid_match_gateclk_en)
|| lifecycle_cur_state_release
&& wb_cur_state_wb
|| lifecycle_cur_state_dealloc
&& wb_cur_state_wb;
// &Instance("gated_clk_cell", "x_sm_gated_clk"); @61
gated_clk_cell x_sm_gated_clk (
.clk_in (vreg_top_clk ),
.clk_out (sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sm_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (vreg_top_clk), @62
// .external_en (1'b0), @63
// .global_en (cp0_yy_clk_en), @64
// .module_en (cp0_rtu_icg_en), @65
// .local_en (sm_clk_en), @66
// .clk_out (sm_clk)); @67
assign alloc_clk_en = ifu_xx_sync_reset
|| create_vld;
// &Instance("gated_clk_cell", "x_alloc_gated_clk"); @71
gated_clk_cell x_alloc_gated_clk (
.clk_in (vreg_top_clk ),
.clk_out (alloc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (alloc_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (vreg_top_clk), @72
// .external_en (1'b0), @73
// .global_en (cp0_yy_clk_en), @74
// .module_en (cp0_rtu_icg_en), @75
// .local_en (alloc_clk_en), @76
// .clk_out (alloc_clk)); @77
//==========================================================
// Vreg Lifecycle State Machine
//==========================================================
assign reset_lifecycle_state[4:0] = (x_reset_mapped) ? RETIRE : DEALLOC;
//----------------------------------------------------------
// FSM of Vreg liftcycle
//----------------------------------------------------------
// State Description:
// DEALLOC : vreg is released and written back, could
// allocate to new producer
// WF_ALLOC : vreg is in allocate vreg register
// ALLOC : vreg is allocated to producer
// RETIRE : producer is retired but vreg is not released
// RELEASE : vreg is released
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lifecycle_cur_state[4:0] <= DEALLOC;
else if(ifu_xx_sync_reset)
lifecycle_cur_state[4:0] <= reset_lifecycle_state[4:0];
else
lifecycle_cur_state[4:0] <= lifecycle_next_state[4:0];
end
// &CombBeg; @105
always @( retire_vld
or wb_cur_state_wb_masked
or x_dealloc_vld
or rtu_yy_xx_flush
or x_release_vld
or lifecycle_cur_state[4:0]
or create_vld)
begin
case(lifecycle_cur_state[4:0])
DEALLOC : if(x_dealloc_vld && !rtu_yy_xx_flush)
lifecycle_next_state[4:0] = WF_ALLOC;
else
lifecycle_next_state[4:0] = DEALLOC;
WF_ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(create_vld)
lifecycle_next_state[4:0] = ALLOC;
else
lifecycle_next_state[4:0] = WF_ALLOC;
ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld && wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else if(retire_vld)
lifecycle_next_state[4:0] = RETIRE;
else
lifecycle_next_state[4:0] = ALLOC;
RETIRE : if(x_release_vld && wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else
lifecycle_next_state[4:0] = RETIRE;
RELEASE : if(wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else
lifecycle_next_state[4:0] = RELEASE;
default : lifecycle_next_state[4:0] = DEALLOC;
endcase
// &CombEnd; @139
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign lifecycle_cur_state_dealloc = lifecycle_cur_state[0];
assign lifecycle_cur_state_alloc = lifecycle_cur_state[2];
assign lifecycle_cur_state_retire = lifecycle_cur_state[3];
assign lifecycle_cur_state_release = lifecycle_cur_state[4];
assign x_cur_state_dealloc = lifecycle_cur_state_dealloc;
assign x_cur_state_alloc_release = lifecycle_cur_state_alloc
|| lifecycle_cur_state_release;
//==========================================================
// Vreg Write Back State Machine
//==========================================================
assign reset_wb_state = (x_reset_mapped) ? WB : IDLE;
//----------------------------------------------------------
// FSM of Vreg write back
//----------------------------------------------------------
// State Description:
// IDLE : vreg is not written back
// WB : vreg is written back
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb_cur_state <= IDLE;
else if(retire_pst_async_flush)
wb_cur_state <= WB;
else if(ifu_xx_sync_reset)
wb_cur_state <= reset_wb_state;
else if(create_vld)
wb_cur_state <= IDLE;
else
wb_cur_state <= wb_next_state;
end
// &CombBeg; @179
always @( lifecycle_cur_state_dealloc
or x_wb_vld
or wb_cur_state)
begin
case(wb_cur_state)
IDLE : if(x_wb_vld)
wb_next_state = WB;
else
wb_next_state = IDLE;
WB : if(lifecycle_cur_state_dealloc)
wb_next_state = IDLE;
else
wb_next_state = WB;
default : wb_next_state = IDLE;
endcase
// &CombEnd; @191
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign wb_cur_state_wb = (wb_cur_state == WB);
assign wb_cur_state_wb_masked = (wb_cur_state == WB) && !x_dealloc_mask;
//==========================================================
// Vreg information
//==========================================================
//----------------------------------------------------------
// Prepare allocate create data
//----------------------------------------------------------
assign create_vld = |x_create_vld[3:0];
// &CombBeg; @206
always @( idu_rtu_pst_dis_inst2_dstv_reg[4:0]
or idu_rtu_pst_dis_inst0_dstv_reg[4:0]
or idu_rtu_pst_dis_inst1_vreg_iid[6:0]
or idu_rtu_pst_dis_inst0_vreg_iid[6:0]
or idu_rtu_pst_dis_inst3_dstv_reg[4:0]
or idu_rtu_pst_dis_inst0_rel_vreg[5:0]
or idu_rtu_pst_dis_inst2_vreg_iid[6:0]
or idu_rtu_pst_dis_inst2_rel_vreg[5:0]
or idu_rtu_pst_dis_inst3_vreg_iid[6:0]
or x_create_vld[3:0]
or idu_rtu_pst_dis_inst1_dstv_reg[4:0]
or idu_rtu_pst_dis_inst3_rel_vreg[5:0]
or idu_rtu_pst_dis_inst1_rel_vreg[5:0])
begin
case (x_create_vld[3:0])
4'h1 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst0_vreg_iid[6:0];
create_dstv_reg[4:0] = idu_rtu_pst_dis_inst0_dstv_reg[4:0];
create_rel_vreg[5:0] = idu_rtu_pst_dis_inst0_rel_vreg[5:0];
end
4'h2 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst1_vreg_iid[6:0];
create_dstv_reg[4:0] = idu_rtu_pst_dis_inst1_dstv_reg[4:0];
create_rel_vreg[5:0] = idu_rtu_pst_dis_inst1_rel_vreg[5:0];
end
4'h4 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst2_vreg_iid[6:0];
create_dstv_reg[4:0] = idu_rtu_pst_dis_inst2_dstv_reg[4:0];
create_rel_vreg[5:0] = idu_rtu_pst_dis_inst2_rel_vreg[5:0];
end
4'h8 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst3_vreg_iid[6:0];
create_dstv_reg[4:0] = idu_rtu_pst_dis_inst3_dstv_reg[4:0];
create_rel_vreg[5:0] = idu_rtu_pst_dis_inst3_rel_vreg[5:0];
end
default: begin
create_iid[6:0] = {7{1'bx}};
create_dstv_reg[4:0] = {5{1'bx}};
create_rel_vreg[5:0] = {6{1'bx}};
end
endcase
// &CombEnd; @234
end
//----------------------------------------------------------
// Information Register
//----------------------------------------------------------
always @(posedge alloc_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
iid[6:0] <= 7'd0;
dstv_reg[4:0] <= 5'd0;
rel_vreg[5:0] <= 6'd0;
end
else if(ifu_xx_sync_reset) begin
iid[6:0] <= 7'd0;
dstv_reg[4:0] <= x_reset_dstv_reg[4:0];
rel_vreg[5:0] <= 6'd0;
end
else if(create_vld) begin
iid[6:0] <= create_iid[6:0];
dstv_reg[4:0] <= create_dstv_reg[4:0];
rel_vreg[5:0] <= create_rel_vreg[5:0];
end
else begin
iid[6:0] <= iid[6:0];
dstv_reg[4:0] <= dstv_reg[4:0];
rel_vreg[5:0] <= rel_vreg[5:0];
end
end
//----------------------------------------------------------
// Retire IID Match Register
//----------------------------------------------------------
//timing optimization: compare retire inst iid before retire
assign retire_inst0_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst0_iid_updt_val[6:0]);
assign retire_inst1_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst1_iid_updt_val[6:0]);
assign retire_inst2_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst2_iid_updt_val[6:0]);
assign retire_inst_iid_match_gateclk_en =
rob_pst_retire_inst0_gateclk_vld
|| rob_pst_retire_inst1_gateclk_vld
|| rob_pst_retire_inst2_gateclk_vld;
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst0_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst0_iid_match <= 1'b0;
else if(rob_pst_retire_inst0_gateclk_vld)
retire_inst0_iid_match <= retire_inst0_iid_match_updt_val;
else
retire_inst0_iid_match <= retire_inst0_iid_match;
end
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst1_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst1_iid_match <= 1'b0;
else if(rob_pst_retire_inst1_gateclk_vld)
retire_inst1_iid_match <= retire_inst1_iid_match_updt_val;
else
retire_inst1_iid_match <= retire_inst1_iid_match;
end
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst2_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst2_iid_match <= 1'b0;
else if(rob_pst_retire_inst2_gateclk_vld)
retire_inst2_iid_match <= retire_inst2_iid_match_updt_val;
else
retire_inst2_iid_match <= retire_inst2_iid_match;
end
//==========================================================
// Retire signal
//==========================================================
assign retire_vld = retire_pst_wb_retire_inst0_vreg_vld
&& retire_inst0_iid_match
|| retire_pst_wb_retire_inst1_vreg_vld
&& retire_inst1_iid_match
|| retire_pst_wb_retire_inst2_vreg_vld
&& retire_inst2_iid_match;
assign retire_gateclk_vld = retire_pst_wb_retire_inst0_vreg_vld
|| retire_pst_wb_retire_inst1_vreg_vld
|| retire_pst_wb_retire_inst2_vreg_vld;
//==========================================================
// Release signal
//==========================================================
// &ConnRule(s/^x_num/rel_vreg/); @334
// &Instance("ct_rtu_expand_64","x_ct_rtu_expand_64_rel_vreg"); @335
ct_rtu_expand_64 x_ct_rtu_expand_64_rel_vreg (
.x_num (rel_vreg ),
.x_num_expand (rel_vreg_expand)
);
//iid match is already AND with cur state alloc
assign rel_retire_vld = lifecycle_cur_state_alloc && retire_vld;
assign x_rel_vreg_expand[63:0] =
{64{rel_retire_vld}} & rel_vreg_expand[63:0];
//==========================================================
// Rename Table Recovery signal
//==========================================================
// &ConnRule(s/^x_num/dstv_reg/); @345
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dstv_reg"); @346
ct_rtu_expand_32 x_ct_rtu_expand_32_dstv_reg (
.x_num (dstv_reg ),
.x_num_expand (dstv_reg_expand)
);
assign x_dreg[31:0] = {32{lifecycle_cur_state_retire}}
& dstv_reg_expand[31:0];
//==========================================================
// Fast Retired Instruction Write Back
//==========================================================
//this signal will be used at retiring cycle by FLUSH state machine
//should consider the retiring insts
assign x_retired_released_wb = (lifecycle_cur_state_alloc
&& retire_vld
|| lifecycle_cur_state_retire
|| lifecycle_cur_state_release)
? wb_cur_state_wb : 1'b1;
// &ModuleEnd; @374
endmodule |
module ct_rtu_pst_ereg_entry(
cp0_rtu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dealloc_vld_for_gateclk,
ereg_top_clk,
idu_rtu_pst_dis_inst0_ereg_iid,
idu_rtu_pst_dis_inst0_rel_ereg,
idu_rtu_pst_dis_inst1_ereg_iid,
idu_rtu_pst_dis_inst1_rel_ereg,
idu_rtu_pst_dis_inst2_ereg_iid,
idu_rtu_pst_dis_inst2_rel_ereg,
idu_rtu_pst_dis_inst3_ereg_iid,
idu_rtu_pst_dis_inst3_rel_ereg,
ifu_xx_sync_reset,
pad_yy_icg_scan_en,
retire_pst_async_flush,
retire_pst_wb_retire_inst0_ereg_vld,
retire_pst_wb_retire_inst1_ereg_vld,
retire_pst_wb_retire_inst2_ereg_vld,
rob_pst_retire_inst0_iid,
rob_pst_retire_inst1_iid,
rob_pst_retire_inst2_iid,
rtu_yy_xx_flush,
x_create_vld,
x_cur_state_alloc_release,
x_cur_state_dealloc,
x_cur_state_retire,
x_dealloc_vld,
x_rel_ereg_expand,
x_release_vld,
x_reset_mapped,
x_retired_released_wb,
x_retired_released_wb_for_acc,
x_wb_vld
);
// &Ports; @28
input cp0_rtu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dealloc_vld_for_gateclk;
input ereg_top_clk;
input [6 :0] idu_rtu_pst_dis_inst0_ereg_iid;
input [4 :0] idu_rtu_pst_dis_inst0_rel_ereg;
input [6 :0] idu_rtu_pst_dis_inst1_ereg_iid;
input [4 :0] idu_rtu_pst_dis_inst1_rel_ereg;
input [6 :0] idu_rtu_pst_dis_inst2_ereg_iid;
input [4 :0] idu_rtu_pst_dis_inst2_rel_ereg;
input [6 :0] idu_rtu_pst_dis_inst3_ereg_iid;
input [4 :0] idu_rtu_pst_dis_inst3_rel_ereg;
input ifu_xx_sync_reset;
input pad_yy_icg_scan_en;
input retire_pst_async_flush;
input retire_pst_wb_retire_inst0_ereg_vld;
input retire_pst_wb_retire_inst1_ereg_vld;
input retire_pst_wb_retire_inst2_ereg_vld;
input [6 :0] rob_pst_retire_inst0_iid;
input [6 :0] rob_pst_retire_inst1_iid;
input [6 :0] rob_pst_retire_inst2_iid;
input rtu_yy_xx_flush;
input [3 :0] x_create_vld;
input x_dealloc_vld;
input x_release_vld;
input x_reset_mapped;
input x_wb_vld;
output x_cur_state_alloc_release;
output x_cur_state_dealloc;
output x_cur_state_retire;
output [31:0] x_rel_ereg_expand;
output x_retired_released_wb;
output x_retired_released_wb_for_acc;
// &Regs; @29
reg [6 :0] create_iid;
reg [4 :0] create_rel_ereg;
reg [6 :0] iid;
reg [4 :0] lifecycle_cur_state;
reg [4 :0] lifecycle_next_state;
reg [4 :0] rel_ereg;
reg wb_cur_state;
reg wb_next_state;
// &Wires; @30
wire alloc_clk;
wire alloc_clk_en;
wire cp0_rtu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_vld;
wire dealloc_vld_for_gateclk;
wire ereg_top_clk;
wire [6 :0] idu_rtu_pst_dis_inst0_ereg_iid;
wire [4 :0] idu_rtu_pst_dis_inst0_rel_ereg;
wire [6 :0] idu_rtu_pst_dis_inst1_ereg_iid;
wire [4 :0] idu_rtu_pst_dis_inst1_rel_ereg;
wire [6 :0] idu_rtu_pst_dis_inst2_ereg_iid;
wire [4 :0] idu_rtu_pst_dis_inst2_rel_ereg;
wire [6 :0] idu_rtu_pst_dis_inst3_ereg_iid;
wire [4 :0] idu_rtu_pst_dis_inst3_rel_ereg;
wire ifu_xx_sync_reset;
wire lifecycle_cur_state_alloc;
wire lifecycle_cur_state_dealloc;
wire lifecycle_cur_state_release;
wire lifecycle_cur_state_retire;
wire pad_yy_icg_scan_en;
wire [31:0] rel_ereg_expand;
wire rel_retire_vld;
wire [4 :0] reset_lifecycle_state;
wire reset_wb_state;
wire retire_pst_async_flush;
wire retire_pst_wb_retire_inst0_ereg_vld;
wire retire_pst_wb_retire_inst1_ereg_vld;
wire retire_pst_wb_retire_inst2_ereg_vld;
wire retire_vld;
wire [6 :0] rob_pst_retire_inst0_iid;
wire [6 :0] rob_pst_retire_inst1_iid;
wire [6 :0] rob_pst_retire_inst2_iid;
wire rtu_yy_xx_flush;
wire sm_clk;
wire sm_clk_en;
wire wb_cur_state_wb;
wire [3 :0] x_create_vld;
wire x_cur_state_alloc_release;
wire x_cur_state_dealloc;
wire x_cur_state_retire;
wire x_dealloc_vld;
wire [31:0] x_rel_ereg_expand;
wire x_release_vld;
wire x_reset_mapped;
wire x_retired_released_wb;
wire x_retired_released_wb_for_acc;
wire x_wb_vld;
parameter DEALLOC = 5'b00001;
parameter WF_ALLOC = 5'b00010;
parameter ALLOC = 5'b00100;
parameter RETIRE = 5'b01000;
parameter RELEASE = 5'b10000;
parameter IDLE = 1'b0;
parameter WB = 1'b1;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign sm_clk_en = rtu_yy_xx_flush
|| retire_pst_async_flush
|| ifu_xx_sync_reset
|| dealloc_vld_for_gateclk
&& lifecycle_cur_state_dealloc
|| (lifecycle_cur_state[4:0] == RETIRE)
// && retire_gateclk_vld
&& x_release_vld
|| x_wb_vld
|| (lifecycle_cur_state[4:0] == WF_ALLOC)
&& create_vld
|| lifecycle_cur_state_alloc
&& retire_vld
|| lifecycle_cur_state_release
&& wb_cur_state_wb
|| lifecycle_cur_state_dealloc
&& wb_cur_state_wb;
// &Instance("gated_clk_cell", "x_sm_gated_clk"); @61
gated_clk_cell x_sm_gated_clk (
.clk_in (ereg_top_clk ),
.clk_out (sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sm_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (ereg_top_clk), @62
// .external_en (1'b0), @63
// .global_en (cp0_yy_clk_en), @64
// .module_en (cp0_rtu_icg_en), @65
// .local_en (sm_clk_en), @66
// .clk_out (sm_clk)); @67
assign alloc_clk_en = ifu_xx_sync_reset
|| create_vld;
// &Instance("gated_clk_cell", "x_alloc_gated_clk"); @71
gated_clk_cell x_alloc_gated_clk (
.clk_in (ereg_top_clk ),
.clk_out (alloc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (alloc_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (ereg_top_clk), @72
// .external_en (1'b0), @73
// .global_en (cp0_yy_clk_en), @74
// .module_en (cp0_rtu_icg_en), @75
// .local_en (alloc_clk_en), @76
// .clk_out (alloc_clk)); @77
//==========================================================
// Creg Lifecycle State Machine
//==========================================================
assign reset_lifecycle_state[4:0] = (x_reset_mapped) ? RETIRE : DEALLOC;
//----------------------------------------------------------
// FSM of Creg liftcycle
//----------------------------------------------------------
// State Description:
// DEALLOC : ereg is released and written back, could
// allocate to new producer
// WF_ALLOC : ereg is in allocate ereg register
// ALLOC : ereg is allocated to producer
// RETIRE : producer is retired but ereg is not released
// RELEASE : ereg is released
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lifecycle_cur_state[4:0] <= DEALLOC;
else if(ifu_xx_sync_reset)
lifecycle_cur_state[4:0] <= reset_lifecycle_state[4:0];
else
lifecycle_cur_state[4:0] <= lifecycle_next_state[4:0];
end
// &CombBeg; @105
always @( retire_vld
or x_dealloc_vld
or rtu_yy_xx_flush
or x_release_vld
or wb_cur_state_wb
or lifecycle_cur_state[4:0]
or create_vld)
begin
case(lifecycle_cur_state[4:0])
DEALLOC : if(x_dealloc_vld && !rtu_yy_xx_flush)
lifecycle_next_state[4:0] = WF_ALLOC;
else
lifecycle_next_state[4:0] = DEALLOC;
WF_ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(create_vld)
lifecycle_next_state[4:0] = ALLOC;
else
lifecycle_next_state[4:0] = WF_ALLOC;
ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld && wb_cur_state_wb)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else if(retire_vld)
lifecycle_next_state[4:0] = RETIRE;
else
lifecycle_next_state[4:0] = ALLOC;
RETIRE : if(x_release_vld && wb_cur_state_wb)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else
lifecycle_next_state[4:0] = RETIRE;
RELEASE : if(wb_cur_state_wb)
lifecycle_next_state[4:0] = DEALLOC;
else
lifecycle_next_state[4:0] = RELEASE;
default : lifecycle_next_state[4:0] = DEALLOC;
endcase
// &CombEnd; @139
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign lifecycle_cur_state_dealloc = lifecycle_cur_state[0];
assign lifecycle_cur_state_alloc = lifecycle_cur_state[2];
assign lifecycle_cur_state_retire = lifecycle_cur_state[3];
assign lifecycle_cur_state_release = lifecycle_cur_state[4];
assign x_cur_state_dealloc = lifecycle_cur_state_dealloc;
assign x_cur_state_alloc_release = lifecycle_cur_state_alloc
|| lifecycle_cur_state_release;
//==========================================================
// Creg Write Back State Machine
//==========================================================
assign reset_wb_state = (x_reset_mapped) ? WB : IDLE;
//----------------------------------------------------------
// FSM of Creg write back
//----------------------------------------------------------
// State Description:
// IDLE : ereg is not written back
// WB : ereg is written back
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb_cur_state <= IDLE;
else if(retire_pst_async_flush)
wb_cur_state <= WB;
else if(ifu_xx_sync_reset)
wb_cur_state <= reset_wb_state;
else if(create_vld)
wb_cur_state <= IDLE;
else
wb_cur_state <= wb_next_state;
end
// &CombBeg; @179
always @( lifecycle_cur_state_dealloc
or x_wb_vld
or wb_cur_state)
begin
case(wb_cur_state)
IDLE : if(x_wb_vld)
wb_next_state = WB;
else
wb_next_state = IDLE;
WB : if(lifecycle_cur_state_dealloc)
wb_next_state = IDLE;
else
wb_next_state = WB;
default : wb_next_state = IDLE;
endcase
// &CombEnd; @191
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign wb_cur_state_wb = (wb_cur_state == WB);
//==========================================================
// Creg information
//==========================================================
//----------------------------------------------------------
// Prepare allocate create data
//----------------------------------------------------------
assign create_vld = |x_create_vld[3:0];
// &CombBeg; @205
always @( idu_rtu_pst_dis_inst0_rel_ereg[4:0]
or idu_rtu_pst_dis_inst1_ereg_iid[6:0]
or idu_rtu_pst_dis_inst0_ereg_iid[6:0]
or idu_rtu_pst_dis_inst2_ereg_iid[6:0]
or idu_rtu_pst_dis_inst1_rel_ereg[4:0]
or idu_rtu_pst_dis_inst3_ereg_iid[6:0]
or idu_rtu_pst_dis_inst2_rel_ereg[4:0]
or x_create_vld[3:0]
or idu_rtu_pst_dis_inst3_rel_ereg[4:0])
begin
case (x_create_vld[3:0])
4'h1 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst0_ereg_iid[6:0];
create_rel_ereg[4:0] = idu_rtu_pst_dis_inst0_rel_ereg[4:0];
end
4'h2 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst1_ereg_iid[6:0];
create_rel_ereg[4:0] = idu_rtu_pst_dis_inst1_rel_ereg[4:0];
end
4'h4 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst2_ereg_iid[6:0];
create_rel_ereg[4:0] = idu_rtu_pst_dis_inst2_rel_ereg[4:0];
end
4'h8 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst3_ereg_iid[6:0];
create_rel_ereg[4:0] = idu_rtu_pst_dis_inst3_rel_ereg[4:0];
end
default: begin
create_iid[6:0] = {7{1'bx}};
create_rel_ereg[4:0] = {5{1'bx}};
end
endcase
// &CombEnd; @228
end
//----------------------------------------------------------
// Information Register
//----------------------------------------------------------
always @(posedge alloc_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
iid[6:0] <= 7'd0;
rel_ereg[4:0] <= 5'd0;
end
else if(ifu_xx_sync_reset) begin
iid[6:0] <= 7'd0;
rel_ereg[4:0] <= 5'd0;
end
else if(create_vld) begin
iid[6:0] <= create_iid[6:0];
rel_ereg[4:0] <= create_rel_ereg[4:0];
end
else begin
iid[6:0] <= iid[6:0];
rel_ereg[4:0] <= rel_ereg[4:0];
end
end
////----------------------------------------------------------
//// Retire IID Match Register
////----------------------------------------------------------
////timing optimization: compare retire inst iid before retire
//assign retire_inst0_iid_match_updt_val =
// lifecycle_cur_state_alloc
// && (iid[6:0] == rob_pst_retire_inst0_iid_updt_val[6:0]);
//assign retire_inst1_iid_match_updt_val =
// lifecycle_cur_state_alloc
// && (iid[6:0] == rob_pst_retire_inst1_iid_updt_val[6:0]);
//assign retire_inst2_iid_match_updt_val =
// lifecycle_cur_state_alloc
// && (iid[6:0] == rob_pst_retire_inst2_iid_updt_val[6:0]);
//
//always @(posedge sm_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// retire_inst0_iid_match <= 1'b0;
// else if(ifu_xx_sync_reset)
// retire_inst0_iid_match <= 1'b0;
// else if(rob_pst_retire_inst0_gateclk_vld)
// retire_inst0_iid_match <= retire_inst0_iid_match_updt_val;
// else
// retire_inst0_iid_match <= retire_inst0_iid_match;
//end
//
//always @(posedge sm_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// retire_inst1_iid_match <= 1'b0;
// else if(ifu_xx_sync_reset)
// retire_inst1_iid_match <= 1'b0;
// else if(rob_pst_retire_inst1_gateclk_vld)
// retire_inst1_iid_match <= retire_inst1_iid_match_updt_val;
// else
// retire_inst1_iid_match <= retire_inst1_iid_match;
//end
//
//always @(posedge sm_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// retire_inst2_iid_match <= 1'b0;
// else if(ifu_xx_sync_reset)
// retire_inst2_iid_match <= 1'b0;
// else if(rob_pst_retire_inst2_gateclk_vld)
// retire_inst2_iid_match <= retire_inst2_iid_match_updt_val;
// else
// retire_inst2_iid_match <= retire_inst2_iid_match;
//end
//==========================================================
// Retire signal
//==========================================================
//assign retire_vld = retire_pst_wb_retire_inst0_ereg_vld
// && retire_inst0_iid_match
// || retire_pst_wb_retire_inst1_ereg_vld
// && retire_inst1_iid_match
// || retire_pst_wb_retire_inst2_ereg_vld
// && retire_inst2_iid_match;
assign retire_vld = retire_pst_wb_retire_inst0_ereg_vld
&& (iid[6:0] == rob_pst_retire_inst0_iid[6:0])
|| retire_pst_wb_retire_inst1_ereg_vld
&& (iid[6:0] == rob_pst_retire_inst1_iid[6:0])
|| retire_pst_wb_retire_inst2_ereg_vld
&& (iid[6:0] == rob_pst_retire_inst2_iid[6:0]);
//assign retire_gateclk_vld = retire_pst_wb_retire_inst0_ereg_vld
// || retire_pst_wb_retire_inst1_ereg_vld
// || retire_pst_wb_retire_inst2_ereg_vld;
//==========================================================
// Release signal
//==========================================================
// &ConnRule(s/^x_num/rel_ereg/); @325
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_rel_ereg"); @326
ct_rtu_expand_32 x_ct_rtu_expand_32_rel_ereg (
.x_num (rel_ereg ),
.x_num_expand (rel_ereg_expand)
);
//iid match is already AND with cur state alloc
assign rel_retire_vld = lifecycle_cur_state_alloc && retire_vld;
assign x_rel_ereg_expand[31:0] =
{32{rel_retire_vld}} & rel_ereg_expand[31:0];
//==========================================================
// Rename Table Recovery signal
//==========================================================
assign x_cur_state_retire = lifecycle_cur_state_retire;
//==========================================================
// Fast Retired Instruction Write Back
//==========================================================
//this signal will be used at retiring cycle by FLUSH state machine
//should consider the retiring insts
assign x_retired_released_wb = (lifecycle_cur_state_alloc
&& retire_vld
|| lifecycle_cur_state_retire
|| lifecycle_cur_state_release)
? wb_cur_state_wb : 1'b1;
//retire release wb for fesr acc update: alloc inst should not update
//acc bits, so should be treated as 1'b0
assign x_retired_released_wb_for_acc =
lifecycle_cur_state_alloc && retire_vld
&& (wb_cur_state_wb || x_wb_vld)
|| (lifecycle_cur_state_retire || lifecycle_cur_state_release)
&& x_wb_vld;
// &ModuleEnd; @356
endmodule |
module ct_rtu_encode_96(
x_num,
x_num_expand
);
// &Ports; @25
input [95:0] x_num_expand;
output [6 :0] x_num;
// &Regs; @26
// &Wires; @27
wire [6 :0] x_num;
wire [95:0] x_num_expand;
//==========================================================
// encode 96 bits one-hot number to 7 bits binary number
//==========================================================
assign x_num[6:0] =
{7{x_num_expand[0]}} & 7'd0
| {7{x_num_expand[1]}} & 7'd1
| {7{x_num_expand[2]}} & 7'd2
| {7{x_num_expand[3]}} & 7'd3
| {7{x_num_expand[4]}} & 7'd4
| {7{x_num_expand[5]}} & 7'd5
| {7{x_num_expand[6]}} & 7'd6
| {7{x_num_expand[7]}} & 7'd7
| {7{x_num_expand[8]}} & 7'd8
| {7{x_num_expand[9]}} & 7'd9
| {7{x_num_expand[10]}} & 7'd10
| {7{x_num_expand[11]}} & 7'd11
| {7{x_num_expand[12]}} & 7'd12
| {7{x_num_expand[13]}} & 7'd13
| {7{x_num_expand[14]}} & 7'd14
| {7{x_num_expand[15]}} & 7'd15
| {7{x_num_expand[16]}} & 7'd16
| {7{x_num_expand[17]}} & 7'd17
| {7{x_num_expand[18]}} & 7'd18
| {7{x_num_expand[19]}} & 7'd19
| {7{x_num_expand[20]}} & 7'd20
| {7{x_num_expand[21]}} & 7'd21
| {7{x_num_expand[22]}} & 7'd22
| {7{x_num_expand[23]}} & 7'd23
| {7{x_num_expand[24]}} & 7'd24
| {7{x_num_expand[25]}} & 7'd25
| {7{x_num_expand[26]}} & 7'd26
| {7{x_num_expand[27]}} & 7'd27
| {7{x_num_expand[28]}} & 7'd28
| {7{x_num_expand[29]}} & 7'd29
| {7{x_num_expand[30]}} & 7'd30
| {7{x_num_expand[31]}} & 7'd31
| {7{x_num_expand[32]}} & 7'd32
| {7{x_num_expand[33]}} & 7'd33
| {7{x_num_expand[34]}} & 7'd34
| {7{x_num_expand[35]}} & 7'd35
| {7{x_num_expand[36]}} & 7'd36
| {7{x_num_expand[37]}} & 7'd37
| {7{x_num_expand[38]}} & 7'd38
| {7{x_num_expand[39]}} & 7'd39
| {7{x_num_expand[40]}} & 7'd40
| {7{x_num_expand[41]}} & 7'd41
| {7{x_num_expand[42]}} & 7'd42
| {7{x_num_expand[43]}} & 7'd43
| {7{x_num_expand[44]}} & 7'd44
| {7{x_num_expand[45]}} & 7'd45
| {7{x_num_expand[46]}} & 7'd46
| {7{x_num_expand[47]}} & 7'd47
| {7{x_num_expand[48]}} & 7'd48
| {7{x_num_expand[49]}} & 7'd49
| {7{x_num_expand[50]}} & 7'd50
| {7{x_num_expand[51]}} & 7'd51
| {7{x_num_expand[52]}} & 7'd52
| {7{x_num_expand[53]}} & 7'd53
| {7{x_num_expand[54]}} & 7'd54
| {7{x_num_expand[55]}} & 7'd55
| {7{x_num_expand[56]}} & 7'd56
| {7{x_num_expand[57]}} & 7'd57
| {7{x_num_expand[58]}} & 7'd58
| {7{x_num_expand[59]}} & 7'd59
| {7{x_num_expand[60]}} & 7'd60
| {7{x_num_expand[61]}} & 7'd61
| {7{x_num_expand[62]}} & 7'd62
| {7{x_num_expand[63]}} & 7'd63
| {7{x_num_expand[64]}} & 7'd64
| {7{x_num_expand[65]}} & 7'd65
| {7{x_num_expand[66]}} & 7'd66
| {7{x_num_expand[67]}} & 7'd67
| {7{x_num_expand[68]}} & 7'd68
| {7{x_num_expand[69]}} & 7'd69
| {7{x_num_expand[70]}} & 7'd70
| {7{x_num_expand[71]}} & 7'd71
| {7{x_num_expand[72]}} & 7'd72
| {7{x_num_expand[73]}} & 7'd73
| {7{x_num_expand[74]}} & 7'd74
| {7{x_num_expand[75]}} & 7'd75
| {7{x_num_expand[76]}} & 7'd76
| {7{x_num_expand[77]}} & 7'd77
| {7{x_num_expand[78]}} & 7'd78
| {7{x_num_expand[79]}} & 7'd79
| {7{x_num_expand[80]}} & 7'd80
| {7{x_num_expand[81]}} & 7'd81
| {7{x_num_expand[82]}} & 7'd82
| {7{x_num_expand[83]}} & 7'd83
| {7{x_num_expand[84]}} & 7'd84
| {7{x_num_expand[85]}} & 7'd85
| {7{x_num_expand[86]}} & 7'd86
| {7{x_num_expand[87]}} & 7'd87
| {7{x_num_expand[88]}} & 7'd88
| {7{x_num_expand[89]}} & 7'd89
| {7{x_num_expand[90]}} & 7'd90
| {7{x_num_expand[91]}} & 7'd91
| {7{x_num_expand[92]}} & 7'd92
| {7{x_num_expand[93]}} & 7'd93
| {7{x_num_expand[94]}} & 7'd94
| {7{x_num_expand[95]}} & 7'd95;
// &ModuleEnd; @130
endmodule |
module ct_rtu_pst_vreg_dummy(
idu_rtu_ir_xreg0_alloc_vld,
idu_rtu_ir_xreg1_alloc_vld,
idu_rtu_ir_xreg2_alloc_vld,
idu_rtu_ir_xreg3_alloc_vld,
idu_rtu_ir_xreg_alloc_gateclk_vld,
idu_rtu_pst_dis_inst0_dstv_reg,
idu_rtu_pst_dis_inst0_rel_vreg,
idu_rtu_pst_dis_inst0_vreg,
idu_rtu_pst_dis_inst0_vreg_iid,
idu_rtu_pst_dis_inst0_xreg_vld,
idu_rtu_pst_dis_inst1_dstv_reg,
idu_rtu_pst_dis_inst1_rel_vreg,
idu_rtu_pst_dis_inst1_vreg,
idu_rtu_pst_dis_inst1_vreg_iid,
idu_rtu_pst_dis_inst1_xreg_vld,
idu_rtu_pst_dis_inst2_dstv_reg,
idu_rtu_pst_dis_inst2_rel_vreg,
idu_rtu_pst_dis_inst2_vreg,
idu_rtu_pst_dis_inst2_vreg_iid,
idu_rtu_pst_dis_inst2_xreg_vld,
idu_rtu_pst_dis_inst3_dstv_reg,
idu_rtu_pst_dis_inst3_rel_vreg,
idu_rtu_pst_dis_inst3_vreg,
idu_rtu_pst_dis_inst3_vreg_iid,
idu_rtu_pst_dis_inst3_xreg_vld,
idu_rtu_pst_xreg_dealloc_mask,
lsu_rtu_wb_pipe3_wb_vreg_expand,
lsu_rtu_wb_pipe3_wb_vreg_vld,
pst_retired_xreg_wb,
rtu_idu_alloc_xreg0,
rtu_idu_alloc_xreg0_vld,
rtu_idu_alloc_xreg1,
rtu_idu_alloc_xreg1_vld,
rtu_idu_alloc_xreg2,
rtu_idu_alloc_xreg2_vld,
rtu_idu_alloc_xreg3,
rtu_idu_alloc_xreg3_vld,
rtu_idu_rt_recover_xreg,
vfpu_rtu_ex5_pipe6_wb_vreg_expand,
vfpu_rtu_ex5_pipe6_wb_vreg_vld,
vfpu_rtu_ex5_pipe7_wb_vreg_expand,
vfpu_rtu_ex5_pipe7_wb_vreg_vld
);
// &Ports; @24
input idu_rtu_ir_xreg0_alloc_vld;
input idu_rtu_ir_xreg1_alloc_vld;
input idu_rtu_ir_xreg2_alloc_vld;
input idu_rtu_ir_xreg3_alloc_vld;
input idu_rtu_ir_xreg_alloc_gateclk_vld;
input [4 :0] idu_rtu_pst_dis_inst0_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst0_rel_vreg;
input [5 :0] idu_rtu_pst_dis_inst0_vreg;
input [6 :0] idu_rtu_pst_dis_inst0_vreg_iid;
input idu_rtu_pst_dis_inst0_xreg_vld;
input [4 :0] idu_rtu_pst_dis_inst1_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst1_rel_vreg;
input [5 :0] idu_rtu_pst_dis_inst1_vreg;
input [6 :0] idu_rtu_pst_dis_inst1_vreg_iid;
input idu_rtu_pst_dis_inst1_xreg_vld;
input [4 :0] idu_rtu_pst_dis_inst2_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst2_rel_vreg;
input [5 :0] idu_rtu_pst_dis_inst2_vreg;
input [6 :0] idu_rtu_pst_dis_inst2_vreg_iid;
input idu_rtu_pst_dis_inst2_xreg_vld;
input [4 :0] idu_rtu_pst_dis_inst3_dstv_reg;
input [5 :0] idu_rtu_pst_dis_inst3_rel_vreg;
input [5 :0] idu_rtu_pst_dis_inst3_vreg;
input [6 :0] idu_rtu_pst_dis_inst3_vreg_iid;
input idu_rtu_pst_dis_inst3_xreg_vld;
input [63 :0] idu_rtu_pst_xreg_dealloc_mask;
input [63 :0] lsu_rtu_wb_pipe3_wb_vreg_expand;
input lsu_rtu_wb_pipe3_wb_vreg_vld;
input [63 :0] vfpu_rtu_ex5_pipe6_wb_vreg_expand;
input vfpu_rtu_ex5_pipe6_wb_vreg_vld;
input [63 :0] vfpu_rtu_ex5_pipe7_wb_vreg_expand;
input vfpu_rtu_ex5_pipe7_wb_vreg_vld;
output pst_retired_xreg_wb;
output [5 :0] rtu_idu_alloc_xreg0;
output rtu_idu_alloc_xreg0_vld;
output [5 :0] rtu_idu_alloc_xreg1;
output rtu_idu_alloc_xreg1_vld;
output [5 :0] rtu_idu_alloc_xreg2;
output rtu_idu_alloc_xreg2_vld;
output [5 :0] rtu_idu_alloc_xreg3;
output rtu_idu_alloc_xreg3_vld;
output [191:0] rtu_idu_rt_recover_xreg;
// &Regs; @25
// &Wires; @26
wire pst_retired_xreg_wb;
wire [5 :0] rtu_idu_alloc_xreg0;
wire rtu_idu_alloc_xreg0_vld;
wire [5 :0] rtu_idu_alloc_xreg1;
wire rtu_idu_alloc_xreg1_vld;
wire [5 :0] rtu_idu_alloc_xreg2;
wire rtu_idu_alloc_xreg2_vld;
wire [5 :0] rtu_idu_alloc_xreg3;
wire rtu_idu_alloc_xreg3_vld;
wire [191:0] rtu_idu_rt_recover_xreg;
// &Force("bus","idu_rtu_pst_dis_inst0_dstv_reg",4,0); @30
// &Force("bus","idu_rtu_pst_dis_inst0_rel_vreg",5,0); @31
// &Force("bus","idu_rtu_pst_dis_inst0_vreg",5,0); @32
// &Force("bus","idu_rtu_pst_dis_inst0_vreg_iid",6,0); @33
// &Force("bus","idu_rtu_pst_dis_inst1_dstv_reg",4,0); @34
// &Force("bus","idu_rtu_pst_dis_inst1_rel_vreg",5,0); @35
// &Force("bus","idu_rtu_pst_dis_inst1_vreg",5,0); @36
// &Force("bus","idu_rtu_pst_dis_inst1_vreg_iid",6,0); @37
// &Force("bus","idu_rtu_pst_dis_inst2_dstv_reg",4,0); @38
// &Force("bus","idu_rtu_pst_dis_inst2_rel_vreg",5,0); @39
// &Force("bus","idu_rtu_pst_dis_inst2_vreg",5,0); @40
// &Force("bus","idu_rtu_pst_dis_inst2_vreg_iid",6,0); @41
// &Force("bus","idu_rtu_pst_dis_inst3_dstv_reg",4,0); @42
// &Force("bus","idu_rtu_pst_dis_inst3_rel_vreg",5,0); @43
// &Force("bus","idu_rtu_pst_dis_inst3_vreg",5,0); @44
// &Force("bus","idu_rtu_pst_dis_inst3_vreg_iid",6,0); @45
// &Force("bus","idu_rtu_pst_xreg_dealloc_mask",63,0); @46
// &Force("bus","lsu_rtu_wb_pipe3_wb_vreg_expand",63,0); @47
// &Force("bus","rob_pst_retire_inst0_iid_updt_val",6,0); @48
// &Force("bus","rob_pst_retire_inst1_iid_updt_val",6,0); @49
// &Force("bus","rob_pst_retire_inst2_iid_updt_val",6,0); @50
// &Force("bus","vfpu_rtu_ex5_pipe6_wb_vreg_expand",63,0); @51
// &Force("bus","vfpu_rtu_ex5_pipe7_wb_vreg_expand",63,0); @52
// &Force("input","idu_rtu_ir_xreg0_alloc_vld"); @54
// &Force("input","idu_rtu_ir_xreg1_alloc_vld"); @55
// &Force("input","idu_rtu_ir_xreg2_alloc_vld"); @56
// &Force("input","idu_rtu_ir_xreg3_alloc_vld"); @57
// &Force("input","idu_rtu_ir_xreg_alloc_gateclk_vld"); @58
// &Force("input","idu_rtu_pst_dis_inst0_dstv_reg"); @59
// &Force("input","idu_rtu_pst_dis_inst0_rel_vreg"); @60
// &Force("input","idu_rtu_pst_dis_inst0_vreg"); @61
// &Force("input","idu_rtu_pst_dis_inst0_vreg_iid"); @62
// &Force("input","idu_rtu_pst_dis_inst0_xreg_vld"); @63
// &Force("input","idu_rtu_pst_dis_inst1_dstv_reg"); @64
// &Force("input","idu_rtu_pst_dis_inst1_rel_vreg"); @65
// &Force("input","idu_rtu_pst_dis_inst1_vreg"); @66
// &Force("input","idu_rtu_pst_dis_inst1_vreg_iid"); @67
// &Force("input","idu_rtu_pst_dis_inst1_xreg_vld"); @68
// &Force("input","idu_rtu_pst_dis_inst2_dstv_reg"); @69
// &Force("input","idu_rtu_pst_dis_inst2_rel_vreg"); @70
// &Force("input","idu_rtu_pst_dis_inst2_vreg"); @71
// &Force("input","idu_rtu_pst_dis_inst2_vreg_iid"); @72
// &Force("input","idu_rtu_pst_dis_inst2_xreg_vld"); @73
// &Force("input","idu_rtu_pst_dis_inst3_dstv_reg"); @74
// &Force("input","idu_rtu_pst_dis_inst3_rel_vreg"); @75
// &Force("input","idu_rtu_pst_dis_inst3_vreg"); @76
// &Force("input","idu_rtu_pst_dis_inst3_vreg_iid"); @77
// &Force("input","idu_rtu_pst_dis_inst3_xreg_vld"); @78
// &Force("input","idu_rtu_pst_xreg_dealloc_mask"); @79
// &Force("input","lsu_rtu_wb_pipe3_wb_vreg_vld"); @80
// &Force("input","lsu_rtu_wb_pipe3_wb_vreg_expand"); @81
// &Force("input","vfpu_rtu_ex5_pipe6_wb_vreg_vld"); @82
// &Force("input","vfpu_rtu_ex5_pipe6_wb_vreg_expand"); @83
// &Force("input","vfpu_rtu_ex5_pipe7_wb_vreg_vld"); @84
// &Force("input","vfpu_rtu_ex5_pipe7_wb_vreg_expand"); @85
assign pst_retired_xreg_wb = 1'b1;
assign rtu_idu_alloc_xreg0[5:0] = 6'b0;
assign rtu_idu_alloc_xreg0_vld = 1'b0;
assign rtu_idu_alloc_xreg1[5:0] = 6'b0;
assign rtu_idu_alloc_xreg1_vld = 1'b0;
assign rtu_idu_alloc_xreg2[5:0] = 6'b0;
assign rtu_idu_alloc_xreg2_vld = 1'b0;
assign rtu_idu_alloc_xreg3[5:0] = 6'b0;
assign rtu_idu_alloc_xreg3_vld = 1'b0;
assign rtu_idu_rt_recover_xreg[191:0] = 192'b0;
// &ModuleEnd; @98
endmodule |
module ct_rtu_rob_expt(
cp0_rtu_icg_en,
cp0_yy_clk_en,
cpurst_b,
expt_entry_expt_vld_updt_val,
expt_entry_iid,
expt_entry_vld,
forever_cpuclk,
iu_rtu_pipe0_abnormal,
iu_rtu_pipe0_bkpt,
iu_rtu_pipe0_cmplt,
iu_rtu_pipe0_efpc_vld,
iu_rtu_pipe0_expt_vec,
iu_rtu_pipe0_expt_vld,
iu_rtu_pipe0_flush,
iu_rtu_pipe0_high_hw_expt,
iu_rtu_pipe0_iid,
iu_rtu_pipe0_immu_expt,
iu_rtu_pipe0_mtval,
iu_rtu_pipe0_vsetvl,
iu_rtu_pipe0_vstart,
iu_rtu_pipe0_vstart_vld,
iu_rtu_pipe2_abnormal,
iu_rtu_pipe2_bht_mispred,
iu_rtu_pipe2_cmplt,
iu_rtu_pipe2_iid,
iu_rtu_pipe2_jmp_mispred,
lsu_rtu_da_pipe3_split_spec_fail_iid,
lsu_rtu_da_pipe3_split_spec_fail_vld,
lsu_rtu_da_pipe4_split_spec_fail_iid,
lsu_rtu_da_pipe4_split_spec_fail_vld,
lsu_rtu_wb_pipe3_abnormal,
lsu_rtu_wb_pipe3_cmplt,
lsu_rtu_wb_pipe3_expt_vec,
lsu_rtu_wb_pipe3_expt_vld,
lsu_rtu_wb_pipe3_flush,
lsu_rtu_wb_pipe3_iid,
lsu_rtu_wb_pipe3_mtval,
lsu_rtu_wb_pipe3_spec_fail,
lsu_rtu_wb_pipe3_vsetvl,
lsu_rtu_wb_pipe3_vstart,
lsu_rtu_wb_pipe3_vstart_vld,
lsu_rtu_wb_pipe4_abnormal,
lsu_rtu_wb_pipe4_cmplt,
lsu_rtu_wb_pipe4_expt_vec,
lsu_rtu_wb_pipe4_expt_vld,
lsu_rtu_wb_pipe4_flush,
lsu_rtu_wb_pipe4_iid,
lsu_rtu_wb_pipe4_mtval,
lsu_rtu_wb_pipe4_spec_fail,
lsu_rtu_wb_pipe4_vstart,
lsu_rtu_wb_pipe4_vstart_vld,
pad_yy_icg_scan_en,
retire_expt_inst0_abnormal,
retire_expt_inst0_vld,
retire_rob_flush,
rob_expt_inst0_iid,
rob_retire_inst0_bht_mispred,
rob_retire_inst0_bkpt,
rob_retire_inst0_efpc_vld,
rob_retire_inst0_expt_vec,
rob_retire_inst0_expt_vld,
rob_retire_inst0_high_hw_expt,
rob_retire_inst0_immu_expt,
rob_retire_inst0_inst_flush,
rob_retire_inst0_jmp_mispred,
rob_retire_inst0_mtval,
rob_retire_inst0_spec_fail,
rob_retire_inst0_spec_fail_no_ssf,
rob_retire_inst0_spec_fail_ssf,
rob_retire_inst0_split,
rob_retire_inst0_vsetvl,
rob_retire_inst0_vstart,
rob_retire_inst0_vstart_vld,
rob_retire_split_spec_fail_srt,
rob_retire_ssf_iid,
rob_top_ssf_cur_state,
rtu_yy_xx_flush
);
// &Ports; @28
input cp0_rtu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input iu_rtu_pipe0_abnormal;
input iu_rtu_pipe0_bkpt;
input iu_rtu_pipe0_cmplt;
input iu_rtu_pipe0_efpc_vld;
input [4 :0] iu_rtu_pipe0_expt_vec;
input iu_rtu_pipe0_expt_vld;
input iu_rtu_pipe0_flush;
input iu_rtu_pipe0_high_hw_expt;
input [6 :0] iu_rtu_pipe0_iid;
input iu_rtu_pipe0_immu_expt;
input [31:0] iu_rtu_pipe0_mtval;
input iu_rtu_pipe0_vsetvl;
input [6 :0] iu_rtu_pipe0_vstart;
input iu_rtu_pipe0_vstart_vld;
input iu_rtu_pipe2_abnormal;
input iu_rtu_pipe2_bht_mispred;
input iu_rtu_pipe2_cmplt;
input [6 :0] iu_rtu_pipe2_iid;
input iu_rtu_pipe2_jmp_mispred;
input [6 :0] lsu_rtu_da_pipe3_split_spec_fail_iid;
input lsu_rtu_da_pipe3_split_spec_fail_vld;
input [6 :0] lsu_rtu_da_pipe4_split_spec_fail_iid;
input lsu_rtu_da_pipe4_split_spec_fail_vld;
input lsu_rtu_wb_pipe3_abnormal;
input lsu_rtu_wb_pipe3_cmplt;
input [4 :0] lsu_rtu_wb_pipe3_expt_vec;
input lsu_rtu_wb_pipe3_expt_vld;
input lsu_rtu_wb_pipe3_flush;
input [6 :0] lsu_rtu_wb_pipe3_iid;
input [39:0] lsu_rtu_wb_pipe3_mtval;
input lsu_rtu_wb_pipe3_spec_fail;
input lsu_rtu_wb_pipe3_vsetvl;
input [6 :0] lsu_rtu_wb_pipe3_vstart;
input lsu_rtu_wb_pipe3_vstart_vld;
input lsu_rtu_wb_pipe4_abnormal;
input lsu_rtu_wb_pipe4_cmplt;
input [4 :0] lsu_rtu_wb_pipe4_expt_vec;
input lsu_rtu_wb_pipe4_expt_vld;
input lsu_rtu_wb_pipe4_flush;
input [6 :0] lsu_rtu_wb_pipe4_iid;
input [39:0] lsu_rtu_wb_pipe4_mtval;
input lsu_rtu_wb_pipe4_spec_fail;
input [6 :0] lsu_rtu_wb_pipe4_vstart;
input lsu_rtu_wb_pipe4_vstart_vld;
input pad_yy_icg_scan_en;
input retire_expt_inst0_abnormal;
input retire_expt_inst0_vld;
input retire_rob_flush;
input [6 :0] rob_expt_inst0_iid;
input rob_retire_inst0_split;
input rtu_yy_xx_flush;
output expt_entry_expt_vld_updt_val;
output [6 :0] expt_entry_iid;
output expt_entry_vld;
output rob_retire_inst0_bht_mispred;
output rob_retire_inst0_bkpt;
output rob_retire_inst0_efpc_vld;
output [3 :0] rob_retire_inst0_expt_vec;
output rob_retire_inst0_expt_vld;
output rob_retire_inst0_high_hw_expt;
output rob_retire_inst0_immu_expt;
output rob_retire_inst0_inst_flush;
output rob_retire_inst0_jmp_mispred;
output [39:0] rob_retire_inst0_mtval;
output rob_retire_inst0_spec_fail;
output rob_retire_inst0_spec_fail_no_ssf;
output rob_retire_inst0_spec_fail_ssf;
output rob_retire_inst0_vsetvl;
output [6 :0] rob_retire_inst0_vstart;
output rob_retire_inst0_vstart_vld;
output rob_retire_split_spec_fail_srt;
output [6 :0] rob_retire_ssf_iid;
output [1 :0] rob_top_ssf_cur_state;
// &Regs; @29
reg [69:0] expt_entry_data;
reg [69:0] expt_entry_updt_data;
reg expt_entry_vld;
reg [1 :0] ssf_cur_state;
reg [6 :0] ssf_iid;
reg [1 :0] ssf_next_state;
// &Wires; @30
wire cp0_rtu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_clk;
wire entry_clk_en;
wire expt_cmplt;
wire expt_entry_bht_mispred;
wire expt_entry_bkpt;
wire expt_entry_efpc_vld;
wire [3 :0] expt_entry_expt_vec;
wire expt_entry_expt_vld;
wire expt_entry_expt_vld_updt_val;
wire expt_entry_flush;
wire expt_entry_high_hw_expt;
wire [6 :0] expt_entry_iid;
wire expt_entry_immu_expt;
wire expt_entry_jmp_mispred;
wire [39:0] expt_entry_mtval;
wire expt_entry_spec_fail;
wire expt_entry_vsetvl;
wire [6 :0] expt_entry_vstart;
wire expt_entry_vstart_vld;
wire [4 :0] expt_entry_write_sel;
wire forever_cpuclk;
wire iu_rtu_pipe0_abnormal;
wire iu_rtu_pipe0_bkpt;
wire iu_rtu_pipe0_cmplt;
wire iu_rtu_pipe0_efpc_vld;
wire [4 :0] iu_rtu_pipe0_expt_vec;
wire iu_rtu_pipe0_expt_vld;
wire iu_rtu_pipe0_flush;
wire iu_rtu_pipe0_high_hw_expt;
wire [6 :0] iu_rtu_pipe0_iid;
wire iu_rtu_pipe0_immu_expt;
wire [31:0] iu_rtu_pipe0_mtval;
wire iu_rtu_pipe0_vsetvl;
wire [6 :0] iu_rtu_pipe0_vstart;
wire iu_rtu_pipe0_vstart_vld;
wire iu_rtu_pipe2_abnormal;
wire iu_rtu_pipe2_bht_mispred;
wire iu_rtu_pipe2_cmplt;
wire [6 :0] iu_rtu_pipe2_iid;
wire iu_rtu_pipe2_jmp_mispred;
wire [6 :0] lsu_rtu_da_pipe3_split_spec_fail_iid;
wire lsu_rtu_da_pipe3_split_spec_fail_vld;
wire [6 :0] lsu_rtu_da_pipe4_split_spec_fail_iid;
wire lsu_rtu_da_pipe4_split_spec_fail_vld;
wire lsu_rtu_wb_pipe3_abnormal;
wire lsu_rtu_wb_pipe3_cmplt;
wire [4 :0] lsu_rtu_wb_pipe3_expt_vec;
wire lsu_rtu_wb_pipe3_expt_vld;
wire lsu_rtu_wb_pipe3_flush;
wire [6 :0] lsu_rtu_wb_pipe3_iid;
wire [39:0] lsu_rtu_wb_pipe3_mtval;
wire lsu_rtu_wb_pipe3_spec_fail;
wire lsu_rtu_wb_pipe3_vsetvl;
wire [6 :0] lsu_rtu_wb_pipe3_vstart;
wire lsu_rtu_wb_pipe3_vstart_vld;
wire lsu_rtu_wb_pipe4_abnormal;
wire lsu_rtu_wb_pipe4_cmplt;
wire [4 :0] lsu_rtu_wb_pipe4_expt_vec;
wire lsu_rtu_wb_pipe4_expt_vld;
wire lsu_rtu_wb_pipe4_flush;
wire [6 :0] lsu_rtu_wb_pipe4_iid;
wire [39:0] lsu_rtu_wb_pipe4_mtval;
wire lsu_rtu_wb_pipe4_spec_fail;
wire [6 :0] lsu_rtu_wb_pipe4_vstart;
wire lsu_rtu_wb_pipe4_vstart_vld;
wire pad_yy_icg_scan_en;
wire pipe0_expt_cmplt;
wire [69:0] pipe0_expt_cmplt_data;
wire pipe0_older_e;
wire pipe2_expt_cmplt;
wire [69:0] pipe2_expt_cmplt_data;
wire pipe2_older_0;
wire pipe2_older_e;
wire pipe3_expt_cmplt;
wire [69:0] pipe3_expt_cmplt_data;
wire pipe3_older_0;
wire pipe3_older_2;
wire pipe3_older_e;
wire pipe4_expt_cmplt;
wire [69:0] pipe4_expt_cmplt_data;
wire pipe4_older_0;
wire pipe4_older_2;
wire pipe4_older_3;
wire pipe4_older_e;
wire retire_expt_inst0_abnormal;
wire retire_expt_inst0_vld;
wire retire_rob_flush;
wire [6 :0] rob_expt_inst0_iid;
wire rob_retire_inst0_bht_mispred;
wire rob_retire_inst0_bkpt;
wire rob_retire_inst0_efpc_vld;
wire [3 :0] rob_retire_inst0_expt_vec;
wire rob_retire_inst0_expt_vld;
wire rob_retire_inst0_high_hw_expt;
wire rob_retire_inst0_immu_expt;
wire rob_retire_inst0_inst_flush;
wire rob_retire_inst0_jmp_mispred;
wire [39:0] rob_retire_inst0_mtval;
wire rob_retire_inst0_spec_fail;
wire rob_retire_inst0_spec_fail_no_ssf;
wire rob_retire_inst0_spec_fail_ssf;
wire rob_retire_inst0_split;
wire rob_retire_inst0_vsetvl;
wire [6 :0] rob_retire_inst0_vstart;
wire rob_retire_inst0_vstart_vld;
wire rob_retire_split_spec_fail_srt;
wire [6 :0] rob_retire_ssf_iid;
wire [1 :0] rob_top_ssf_cur_state;
wire rtu_yy_xx_flush;
wire ssf_clk;
wire ssf_clk_en;
wire [6 :0] ssf_iid_updt_val;
wire ssf_inst_retire_no_split;
wire ssf_pipe3_iid_updt_vld;
wire ssf_pipe3_older_sm;
wire ssf_pipe4_iid_updt_vld;
wire ssf_pipe4_older_3;
wire ssf_pipe4_older_sm;
wire ssf_sm_iid_updt_vld;
wire ssf_sm_start;
wire ssf_split_spec_fail_flush;
wire ssf_split_spec_fail_retire;
parameter EXPT_WIDTH = 70;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = expt_cmplt || expt_entry_vld;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @39
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @40
// .external_en (1'b0), @41
// .global_en (cp0_yy_clk_en), @42
// .module_en (cp0_rtu_icg_en), @43
// .local_en (entry_clk_en), @44
// .clk_out (entry_clk)); @45
//==========================================================
// Exception Cmplt Order
//==========================================================
//----------------------------------------------------------
// Order Compare
//----------------------------------------------------------
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe4_older_3"); @53
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe4_older_3 (
.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]),
.x_iid0_older (pipe4_older_3 ),
.x_iid1 (lsu_rtu_wb_pipe3_iid[6:0])
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]), @54
// .x_iid1 (lsu_rtu_wb_pipe3_iid[6:0]), @55
// .x_iid0_older (pipe4_older_3 )); @56
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe4_older_2"); @57
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe4_older_2 (
.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]),
.x_iid0_older (pipe4_older_2 ),
.x_iid1 (iu_rtu_pipe2_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]), @58
// .x_iid1 (iu_rtu_pipe2_iid[6:0]), @59
// .x_iid0_older (pipe4_older_2 )); @60
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe4_older_0"); @61
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe4_older_0 (
.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]),
.x_iid0_older (pipe4_older_0 ),
.x_iid1 (iu_rtu_pipe0_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]), @62
// .x_iid1 (iu_rtu_pipe0_iid[6:0]), @63
// .x_iid0_older (pipe4_older_0 )); @64
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe4_older_e"); @65
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe4_older_e (
.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]),
.x_iid0_older (pipe4_older_e ),
.x_iid1 (expt_entry_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe4_iid[6:0]), @66
// .x_iid1 (expt_entry_iid[6:0] ), @67
// .x_iid0_older (pipe4_older_e )); @68
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe3_older_2"); @69
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe3_older_2 (
.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]),
.x_iid0_older (pipe3_older_2 ),
.x_iid1 (iu_rtu_pipe2_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]), @70
// .x_iid1 (iu_rtu_pipe2_iid[6:0]), @71
// .x_iid0_older (pipe3_older_2 )); @72
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe3_older_0"); @73
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe3_older_0 (
.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]),
.x_iid0_older (pipe3_older_0 ),
.x_iid1 (iu_rtu_pipe0_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]), @74
// .x_iid1 (iu_rtu_pipe0_iid[6:0]), @75
// .x_iid0_older (pipe3_older_0 )); @76
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe3_older_e"); @77
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe3_older_e (
.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]),
.x_iid0_older (pipe3_older_e ),
.x_iid1 (expt_entry_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_wb_pipe3_iid[6:0]), @78
// .x_iid1 (expt_entry_iid[6:0] ), @79
// .x_iid0_older (pipe3_older_e )); @80
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe2_older_0"); @81
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe2_older_0 (
.x_iid0 (iu_rtu_pipe2_iid[6:0]),
.x_iid0_older (pipe2_older_0 ),
.x_iid1 (iu_rtu_pipe0_iid[6:0])
);
// &Connect(.x_iid0 (iu_rtu_pipe2_iid[6:0]), @82
// .x_iid1 (iu_rtu_pipe0_iid[6:0]), @83
// .x_iid0_older (pipe2_older_0 )); @84
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe2_older_e"); @85
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe2_older_e (
.x_iid0 (iu_rtu_pipe2_iid[6:0]),
.x_iid0_older (pipe2_older_e ),
.x_iid1 (expt_entry_iid[6:0] )
);
// &Connect(.x_iid0 (iu_rtu_pipe2_iid[6:0]), @86
// .x_iid1 (expt_entry_iid[6:0] ), @87
// .x_iid0_older (pipe2_older_e )); @88
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_pipe0_older_e"); @89
ct_rtu_compare_iid x_ct_rtu_compare_iid_pipe0_older_e (
.x_iid0 (iu_rtu_pipe0_iid[6:0]),
.x_iid0_older (pipe0_older_e ),
.x_iid1 (expt_entry_iid[6:0] )
);
// &Connect(.x_iid0 (iu_rtu_pipe0_iid[6:0]), @90
// .x_iid1 (expt_entry_iid[6:0] ), @91
// .x_iid0_older (pipe0_older_e )); @92
//----------------------------------------------------------
// Expt cmplt select signals
//----------------------------------------------------------
assign pipe4_expt_cmplt = lsu_rtu_wb_pipe4_cmplt && lsu_rtu_wb_pipe4_abnormal;
assign pipe3_expt_cmplt = lsu_rtu_wb_pipe3_cmplt && lsu_rtu_wb_pipe3_abnormal;
assign pipe2_expt_cmplt = iu_rtu_pipe2_cmplt && iu_rtu_pipe2_abnormal;
assign pipe0_expt_cmplt = iu_rtu_pipe0_cmplt && iu_rtu_pipe0_abnormal;
assign expt_entry_write_sel[4] = pipe4_expt_cmplt
&& (!pipe3_expt_cmplt || pipe4_older_3)
&& (!pipe2_expt_cmplt || pipe4_older_2)
&& (!pipe0_expt_cmplt || pipe4_older_0)
&& (!expt_entry_vld || pipe4_older_e);
assign expt_entry_write_sel[3] = pipe3_expt_cmplt
&& (!pipe4_expt_cmplt || !pipe4_older_3)
&& (!pipe2_expt_cmplt || pipe3_older_2)
&& (!pipe0_expt_cmplt || pipe3_older_0)
&& (!expt_entry_vld || pipe3_older_e);
assign expt_entry_write_sel[2] = pipe2_expt_cmplt
&& (!pipe4_expt_cmplt || !pipe4_older_2)
&& (!pipe3_expt_cmplt || !pipe3_older_2)
&& (!pipe0_expt_cmplt || pipe2_older_0)
&& (!expt_entry_vld || pipe2_older_e);
assign expt_entry_write_sel[1] = pipe0_expt_cmplt
&& (!pipe4_expt_cmplt || !pipe4_older_0)
&& (!pipe3_expt_cmplt || !pipe3_older_0)
&& (!pipe2_expt_cmplt || !pipe2_older_0)
&& (!expt_entry_vld || pipe0_older_e);
assign expt_entry_write_sel[0] = expt_entry_vld
&& (!pipe4_expt_cmplt || !pipe4_older_e)
&& (!pipe3_expt_cmplt || !pipe3_older_e)
&& (!pipe2_expt_cmplt || !pipe2_older_e)
&& (!pipe0_expt_cmplt || !pipe0_older_e);
assign pipe4_expt_cmplt_data[69:63] = lsu_rtu_wb_pipe4_vstart[6:0];
assign pipe4_expt_cmplt_data[62] = lsu_rtu_wb_pipe4_vstart_vld;
assign pipe4_expt_cmplt_data[61] = 1'b0;
assign pipe4_expt_cmplt_data[60] = 1'b0;
assign pipe4_expt_cmplt_data[59] = lsu_rtu_wb_pipe4_spec_fail;
assign pipe4_expt_cmplt_data[58] = 1'b0;
assign pipe4_expt_cmplt_data[57] = lsu_rtu_wb_pipe4_flush;
assign pipe4_expt_cmplt_data[56] = 1'b0;
assign pipe4_expt_cmplt_data[55] = 1'b0;
assign pipe4_expt_cmplt_data[54:15] = lsu_rtu_wb_pipe4_mtval[39:0];
assign pipe4_expt_cmplt_data[14] = 1'b0;
assign pipe4_expt_cmplt_data[13] = 1'b0;
assign pipe4_expt_cmplt_data[12:8] = lsu_rtu_wb_pipe4_expt_vec[4:0];
assign pipe4_expt_cmplt_data[7] = lsu_rtu_wb_pipe4_expt_vld;
assign pipe4_expt_cmplt_data[6:0] = lsu_rtu_wb_pipe4_iid[6:0];
assign pipe3_expt_cmplt_data[69:63] = lsu_rtu_wb_pipe3_vstart[6:0];
assign pipe3_expt_cmplt_data[62] = lsu_rtu_wb_pipe3_vstart_vld;
assign pipe3_expt_cmplt_data[61] = lsu_rtu_wb_pipe3_vsetvl;
assign pipe3_expt_cmplt_data[60] = 1'b0;
assign pipe3_expt_cmplt_data[59] = lsu_rtu_wb_pipe3_spec_fail;
assign pipe3_expt_cmplt_data[58] = 1'b0;
assign pipe3_expt_cmplt_data[57] = lsu_rtu_wb_pipe3_flush;
assign pipe3_expt_cmplt_data[56] = 1'b0;
assign pipe3_expt_cmplt_data[55] = 1'b0;
assign pipe3_expt_cmplt_data[54:15] = lsu_rtu_wb_pipe3_mtval[39:0];
assign pipe3_expt_cmplt_data[14] = 1'b0;
assign pipe3_expt_cmplt_data[13] = 1'b0;
assign pipe3_expt_cmplt_data[12:8] = lsu_rtu_wb_pipe3_expt_vec[4:0];
assign pipe3_expt_cmplt_data[7] = lsu_rtu_wb_pipe3_expt_vld;
assign pipe3_expt_cmplt_data[6:0] = lsu_rtu_wb_pipe3_iid[6:0];
assign pipe2_expt_cmplt_data[69:63] = 7'b0;
assign pipe2_expt_cmplt_data[62] = 1'b0;
assign pipe2_expt_cmplt_data[61] = 1'b0;
assign pipe2_expt_cmplt_data[60] = 1'b0;
assign pipe2_expt_cmplt_data[59] = 1'b0;
assign pipe2_expt_cmplt_data[58] = 1'b0;
assign pipe2_expt_cmplt_data[57] = 1'b0;
assign pipe2_expt_cmplt_data[56] = iu_rtu_pipe2_jmp_mispred;
assign pipe2_expt_cmplt_data[55] = iu_rtu_pipe2_bht_mispred;
assign pipe2_expt_cmplt_data[54:15] = 40'b0;
assign pipe2_expt_cmplt_data[14] = 1'b0;
assign pipe2_expt_cmplt_data[13] = 1'b0;
assign pipe2_expt_cmplt_data[12:8] = 5'b0;
assign pipe2_expt_cmplt_data[7] = 1'b0;
assign pipe2_expt_cmplt_data[6:0] = iu_rtu_pipe2_iid[6:0];
assign pipe0_expt_cmplt_data[69:63] = iu_rtu_pipe0_vstart[6:0];
assign pipe0_expt_cmplt_data[62] = iu_rtu_pipe0_vstart_vld;
assign pipe0_expt_cmplt_data[61] = iu_rtu_pipe0_vsetvl;
assign pipe0_expt_cmplt_data[60] = iu_rtu_pipe0_efpc_vld;
assign pipe0_expt_cmplt_data[59] = 1'b0;
assign pipe0_expt_cmplt_data[58] = iu_rtu_pipe0_bkpt;
assign pipe0_expt_cmplt_data[57] = iu_rtu_pipe0_flush;
assign pipe0_expt_cmplt_data[56] = 1'b0;
assign pipe0_expt_cmplt_data[55] = 1'b0;
assign pipe0_expt_cmplt_data[54:15] = {8'b0, iu_rtu_pipe0_mtval[31:0]};
assign pipe0_expt_cmplt_data[14] = iu_rtu_pipe0_immu_expt;
assign pipe0_expt_cmplt_data[13] = iu_rtu_pipe0_high_hw_expt;
assign pipe0_expt_cmplt_data[12:8] = iu_rtu_pipe0_expt_vec[4:0];
assign pipe0_expt_cmplt_data[7] = iu_rtu_pipe0_expt_vld;
assign pipe0_expt_cmplt_data[6:0] = iu_rtu_pipe0_iid[6:0];
// &CombBeg; @192
always @( expt_entry_write_sel[4:0]
or pipe4_expt_cmplt_data[69:0]
or pipe2_expt_cmplt_data[69:0]
or pipe0_expt_cmplt_data[69:0]
or expt_entry_data[69:0]
or pipe3_expt_cmplt_data[69:0])
begin
case (expt_entry_write_sel[4:0])
5'h01 : expt_entry_updt_data[EXPT_WIDTH-1:0] = expt_entry_data[EXPT_WIDTH-1:0];
5'h02 : expt_entry_updt_data[EXPT_WIDTH-1:0] = pipe0_expt_cmplt_data[EXPT_WIDTH-1:0];
5'h04 : expt_entry_updt_data[EXPT_WIDTH-1:0] = pipe2_expt_cmplt_data[EXPT_WIDTH-1:0];
5'h08 : expt_entry_updt_data[EXPT_WIDTH-1:0] = pipe3_expt_cmplt_data[EXPT_WIDTH-1:0];
5'h10 : expt_entry_updt_data[EXPT_WIDTH-1:0] = pipe4_expt_cmplt_data[EXPT_WIDTH-1:0];
default: expt_entry_updt_data[EXPT_WIDTH-1:0] = {EXPT_WIDTH{1'bx}};
endcase
// &CombEnd; @201
end
//==========================================================
// Exception Entry Valid
//==========================================================
// &Force("output","expt_entry_vld"); @206
assign expt_cmplt = pipe4_expt_cmplt
|| pipe3_expt_cmplt
|| pipe2_expt_cmplt
|| pipe0_expt_cmplt;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
expt_entry_vld <= 1'b0;
//flush with rob, if spec inst on wrong path set expt, flush again
//when flush be
else if(retire_rob_flush || rtu_yy_xx_flush)
expt_entry_vld <= 1'b0;
else if(expt_cmplt)
expt_entry_vld <= 1'b1;
else if(retire_expt_inst0_vld && retire_expt_inst0_abnormal)
expt_entry_vld <= 1'b0;
else
expt_entry_vld <= expt_entry_vld;
end
//==========================================================
// Expt Cmplt Info
//==========================================================
assign expt_entry_expt_vld_updt_val = (expt_cmplt) ? expt_entry_updt_data[7]
: expt_entry_data[7];
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
expt_entry_data[EXPT_WIDTH-1:0] <= {EXPT_WIDTH{1'b0}};
else if(expt_cmplt)
expt_entry_data[EXPT_WIDTH-1:0] <= expt_entry_updt_data[EXPT_WIDTH-1:0];
else
expt_entry_data[EXPT_WIDTH-1:0] <= expt_entry_data[EXPT_WIDTH-1:0];
end
// &Force("output","expt_entry_iid"); @243
assign expt_entry_vstart[6:0] = expt_entry_data[69:63];
assign expt_entry_vstart_vld = expt_entry_data[62];
assign expt_entry_vsetvl = expt_entry_data[61];
assign expt_entry_efpc_vld = expt_entry_data[60];
assign expt_entry_spec_fail = expt_entry_data[59];
assign expt_entry_bkpt = expt_entry_data[58];
assign expt_entry_flush = expt_entry_data[57];
assign expt_entry_jmp_mispred = expt_entry_data[56];
assign expt_entry_bht_mispred = expt_entry_data[55];
assign expt_entry_mtval[39:0] = expt_entry_data[54:15];
assign expt_entry_immu_expt = expt_entry_data[14];
assign expt_entry_high_hw_expt = expt_entry_data[13];
//assign expt_entry_expt_vec[4] = expt_entry_data[12];
assign expt_entry_expt_vec[3:0] = expt_entry_data[11:8];
assign expt_entry_expt_vld = expt_entry_data[7];
assign expt_entry_iid[6:0] = expt_entry_data[6:0];
//----------------------------------------------------------
// Rename for output
//----------------------------------------------------------
// &Force("output","rob_retire_inst0_spec_fail_ssf"); @264
// &Force("output","rob_retire_inst0_spec_fail_no_ssf"); @265
assign rob_retire_inst0_expt_vld = retire_expt_inst0_abnormal
&& expt_entry_expt_vld;
assign rob_retire_inst0_expt_vec[3:0] = expt_entry_expt_vec[3:0];
assign rob_retire_inst0_immu_expt = expt_entry_immu_expt;
assign rob_retire_inst0_high_hw_expt = expt_entry_high_hw_expt;
assign rob_retire_inst0_inst_flush = retire_expt_inst0_abnormal
&& !expt_entry_expt_vld
&& expt_entry_flush
|| !retire_expt_inst0_abnormal
&& ssf_split_spec_fail_flush;
assign rob_retire_inst0_jmp_mispred = retire_expt_inst0_abnormal
&& expt_entry_jmp_mispred;
assign rob_retire_inst0_bht_mispred = retire_expt_inst0_abnormal
&& expt_entry_bht_mispred;
assign rob_retire_inst0_mtval[39:0] = expt_entry_mtval[39:0];
assign rob_retire_inst0_bkpt = retire_expt_inst0_abnormal
&& expt_entry_bkpt;
assign rob_retire_inst0_spec_fail_no_ssf = retire_expt_inst0_abnormal
&& expt_entry_spec_fail;
assign rob_retire_inst0_spec_fail_ssf = !retire_expt_inst0_abnormal
&& ssf_split_spec_fail_flush;
assign rob_retire_inst0_spec_fail = rob_retire_inst0_spec_fail_no_ssf
|| rob_retire_inst0_spec_fail_ssf;
assign rob_retire_inst0_efpc_vld = retire_expt_inst0_abnormal
&& expt_entry_efpc_vld;
assign rob_retire_inst0_vsetvl = retire_expt_inst0_abnormal
&& expt_entry_vsetvl;
assign rob_retire_inst0_vstart_vld = retire_expt_inst0_abnormal
&& expt_entry_vstart_vld;
assign rob_retire_inst0_vstart[6:0] = expt_entry_vstart[6:0];
//==========================================================
// Split instruction spec fail
//==========================================================
parameter IDLE = 2'b00;
parameter WF_RETIRE = 2'b10;
parameter RETIRING = 2'b11;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ssf_clk_en = ssf_sm_start
|| (ssf_cur_state[1:0] != IDLE);
// &Instance("gated_clk_cell", "x_ssf_gated_clk"); @309
gated_clk_cell x_ssf_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ssf_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ssf_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @310
// .external_en (1'b0), @311
// .global_en (cp0_yy_clk_en), @312
// .module_en (cp0_rtu_icg_en), @313
// .local_en (ssf_clk_en), @314
// .clk_out (ssf_clk)); @315
//----------------------------------------------------------
// control signal for ssf FSM
//----------------------------------------------------------
assign ssf_sm_start = lsu_rtu_da_pipe4_split_spec_fail_vld
|| lsu_rtu_da_pipe3_split_spec_fail_vld;
assign ssf_split_spec_fail_retire = retire_expt_inst0_vld
&& (rob_expt_inst0_iid[6:0] == ssf_iid[6:0]);
assign ssf_inst_retire_no_split = retire_expt_inst0_vld
&& !rob_retire_inst0_split;
//----------------------------------------------------------
// FSM of inst ssf ctrl logic
//----------------------------------------------------------
// State Description:
// IDLE : no split instruction speculation failed
// WF_RETIRE : wait for split spec fail inst retire
// RETIRING : split spec fail inst is retring
always @(posedge ssf_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ssf_cur_state[1:0] <= IDLE;
else if(retire_rob_flush || rtu_yy_xx_flush)
ssf_cur_state[1:0] <= IDLE;
else
ssf_cur_state[1:0] <= ssf_next_state[1:0];
end
// &CombBeg; @346
always @( ssf_split_spec_fail_retire
or ssf_cur_state[1:0]
or ssf_sm_start
or ssf_inst_retire_no_split)
begin
case(ssf_cur_state[1:0])
IDLE : if(ssf_sm_start)
ssf_next_state[1:0] = WF_RETIRE;
else
ssf_next_state[1:0] = IDLE;
WF_RETIRE : if(ssf_split_spec_fail_retire)
ssf_next_state[1:0] = RETIRING;
else
ssf_next_state[1:0] = WF_RETIRE;
RETIRING : if(ssf_inst_retire_no_split)
ssf_next_state[1:0] = IDLE;
else
ssf_next_state[1:0] = RETIRING;
default : ssf_next_state[1:0] = IDLE;
endcase
// &CombEnd; @362
end
//----------------------------------------------------------
// control signals
//----------------------------------------------------------
//if there is split inst spec fail, to simplify the design, enable srt
//wait for split inst retire
assign rob_retire_split_spec_fail_srt = ssf_cur_state[1];
//if in RETIRING state, wait for next no split inst and generate
//spec fail flush if it is not abnormal
assign ssf_split_spec_fail_flush = ssf_cur_state[0]
&& ssf_inst_retire_no_split;
assign rob_top_ssf_cur_state[1:0] = ssf_cur_state[1:0];
//----------------------------------------------------------
// Split Spec fail Age
//----------------------------------------------------------
//compare lsu pipe3/4/ssf split spec fail inst age
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_ssf_pipe4_older_3"); @380
ct_rtu_compare_iid x_ct_rtu_compare_iid_ssf_pipe4_older_3 (
.x_iid0 (lsu_rtu_da_pipe4_split_spec_fail_iid[6:0]),
.x_iid0_older (ssf_pipe4_older_3 ),
.x_iid1 (lsu_rtu_da_pipe3_split_spec_fail_iid[6:0])
);
// &Connect(.x_iid0 (lsu_rtu_da_pipe4_split_spec_fail_iid[6:0]), @381
// .x_iid1 (lsu_rtu_da_pipe3_split_spec_fail_iid[6:0]), @382
// .x_iid0_older (ssf_pipe4_older_3 )); @383
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_ssf_pipe4_older_sm"); @384
ct_rtu_compare_iid x_ct_rtu_compare_iid_ssf_pipe4_older_sm (
.x_iid0 (lsu_rtu_da_pipe4_split_spec_fail_iid[6:0]),
.x_iid0_older (ssf_pipe4_older_sm ),
.x_iid1 (ssf_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_da_pipe4_split_spec_fail_iid[6:0]), @385
// .x_iid1 (ssf_iid[6:0]), @386
// .x_iid0_older (ssf_pipe4_older_sm )); @387
// &Instance("ct_rtu_compare_iid","x_ct_rtu_compare_iid_ssf_pipe3_older_sm"); @388
ct_rtu_compare_iid x_ct_rtu_compare_iid_ssf_pipe3_older_sm (
.x_iid0 (lsu_rtu_da_pipe3_split_spec_fail_iid[6:0]),
.x_iid0_older (ssf_pipe3_older_sm ),
.x_iid1 (ssf_iid[6:0] )
);
// &Connect(.x_iid0 (lsu_rtu_da_pipe3_split_spec_fail_iid[6:0]), @389
// .x_iid1 (ssf_iid[6:0]), @390
// .x_iid0_older (ssf_pipe3_older_sm )); @391
//if older split spec fail occurs, update ssf_iid with older iid
//and hold ssf sm state if it is not idle
//because lsu should signal split spec fail before cmplt
assign ssf_pipe4_iid_updt_vld =
lsu_rtu_da_pipe4_split_spec_fail_vld
&& (!lsu_rtu_da_pipe3_split_spec_fail_vld || ssf_pipe4_older_3)
&& ((ssf_cur_state[1:0] == IDLE) || ssf_pipe4_older_sm);
assign ssf_pipe3_iid_updt_vld =
lsu_rtu_da_pipe3_split_spec_fail_vld
&& (!lsu_rtu_da_pipe4_split_spec_fail_vld || !ssf_pipe4_older_3)
&& ((ssf_cur_state[1:0] == IDLE) || ssf_pipe3_older_sm);
assign ssf_sm_iid_updt_vld =
(ssf_cur_state[1:0] != IDLE)
&& (!lsu_rtu_da_pipe4_split_spec_fail_vld || !ssf_pipe4_older_sm)
&& (!lsu_rtu_da_pipe3_split_spec_fail_vld || !ssf_pipe3_older_sm);
//----------------------------------------------------------
// Split spec fail inst iid
//----------------------------------------------------------
assign ssf_iid_updt_val[6:0] =
{7{ssf_pipe4_iid_updt_vld}} & lsu_rtu_da_pipe4_split_spec_fail_iid[6:0]
| {7{ssf_pipe3_iid_updt_vld}} & lsu_rtu_da_pipe3_split_spec_fail_iid[6:0]
| {7{ssf_sm_iid_updt_vld}} & ssf_iid[6:0];
always @(posedge ssf_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ssf_iid[6:0] <= 7'b0;
else
ssf_iid[6:0] <= ssf_iid_updt_val[6:0];
end
assign rob_retire_ssf_iid[6:0] = ssf_iid[6:0];
// &ModuleEnd @427
endmodule |
module ct_rtu_rob_entry(
cp0_rtu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idu_rtu_rob_create0_data,
idu_rtu_rob_create1_data,
idu_rtu_rob_create2_data,
idu_rtu_rob_create3_data,
lsu_misc_cmplt_gateclk_en,
lsu_rtu_wb_pipe3_bkpta_data,
lsu_rtu_wb_pipe3_bkptb_data,
lsu_rtu_wb_pipe3_no_spec_hit,
lsu_rtu_wb_pipe3_no_spec_mispred,
lsu_rtu_wb_pipe3_no_spec_miss,
lsu_rtu_wb_pipe4_bkpta_data,
lsu_rtu_wb_pipe4_bkptb_data,
lsu_rtu_wb_pipe4_no_spec_hit,
lsu_rtu_wb_pipe4_no_spec_mispred,
lsu_rtu_wb_pipe4_no_spec_miss,
pad_yy_icg_scan_en,
retire_rob_flush,
retire_rob_flush_gateclk,
x_cmplt_gateclk_vld,
x_cmplt_vld,
x_create_dp_en,
x_create_en,
x_create_gateclk_en,
x_create_sel,
x_pop_en,
x_read_data
);
// &Ports; @28
input cp0_rtu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input [39:0] idu_rtu_rob_create0_data;
input [39:0] idu_rtu_rob_create1_data;
input [39:0] idu_rtu_rob_create2_data;
input [39:0] idu_rtu_rob_create3_data;
input lsu_misc_cmplt_gateclk_en;
input lsu_rtu_wb_pipe3_bkpta_data;
input lsu_rtu_wb_pipe3_bkptb_data;
input lsu_rtu_wb_pipe3_no_spec_hit;
input lsu_rtu_wb_pipe3_no_spec_mispred;
input lsu_rtu_wb_pipe3_no_spec_miss;
input lsu_rtu_wb_pipe4_bkpta_data;
input lsu_rtu_wb_pipe4_bkptb_data;
input lsu_rtu_wb_pipe4_no_spec_hit;
input lsu_rtu_wb_pipe4_no_spec_mispred;
input lsu_rtu_wb_pipe4_no_spec_miss;
input pad_yy_icg_scan_en;
input retire_rob_flush;
input retire_rob_flush_gateclk;
input x_cmplt_gateclk_vld;
input [6 :0] x_cmplt_vld;
input x_create_dp_en;
input x_create_en;
input x_create_gateclk_en;
input [3 :0] x_create_sel;
input x_pop_en;
output [39:0] x_read_data;
// &Regs; @29
reg bju;
reg bkpta_data;
reg bkpta_inst;
reg bkptb_data;
reg bkptb_inst;
reg cmplt;
reg [1 :0] cmplt_cnt;
reg fp_dirty;
reg [1 :0] inst_num;
reg intmask;
reg load;
reg no_spec_hit;
reg no_spec_mispred;
reg no_spec_miss;
reg [2 :0] pc_offset;
reg pcfifo;
reg ras;
reg split;
reg store;
reg vec_dirty;
reg [7 :0] vl;
reg vl_pred;
reg vld;
reg [1 :0] vlmul;
reg vsetvli;
reg [2 :0] vsew;
reg [39:0] x_create_data;
// &Wires; @30
wire bkpta_data_updt_val;
wire bkptb_data_updt_val;
wire cmplt_1_fold_inst;
wire cmplt_2_fold_inst;
wire cmplt_3_fold_inst;
wire [1 :0] cmplt_cnt_cmplt_exist;
wire [1 :0] cmplt_cnt_with_create;
wire cmplt_updt_val;
wire cp0_rtu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_clk;
wire create_clk_en;
wire entry_clk;
wire entry_clk_en;
wire forever_cpuclk;
wire [39:0] idu_rtu_rob_create0_data;
wire [39:0] idu_rtu_rob_create1_data;
wire [39:0] idu_rtu_rob_create2_data;
wire [39:0] idu_rtu_rob_create3_data;
wire lsu_cmplt_clk;
wire lsu_cmplt_clk_en;
wire lsu_misc_cmplt_gateclk_en;
wire lsu_rtu_wb_pipe3_bkpta_data;
wire lsu_rtu_wb_pipe3_bkptb_data;
wire lsu_rtu_wb_pipe3_no_spec_hit;
wire lsu_rtu_wb_pipe3_no_spec_mispred;
wire lsu_rtu_wb_pipe3_no_spec_miss;
wire lsu_rtu_wb_pipe4_bkpta_data;
wire lsu_rtu_wb_pipe4_bkptb_data;
wire lsu_rtu_wb_pipe4_no_spec_hit;
wire lsu_rtu_wb_pipe4_no_spec_mispred;
wire lsu_rtu_wb_pipe4_no_spec_miss;
wire no_spec_hit_updt_val;
wire no_spec_mispred_updt_val;
wire no_spec_miss_updt_val;
wire pad_yy_icg_scan_en;
wire retire_rob_flush;
wire retire_rob_flush_gateclk;
wire x_cmplt_gateclk_vld;
wire [6 :0] x_cmplt_vld;
wire x_create_dp_en;
wire x_create_en;
wire x_create_gateclk_en;
wire [3 :0] x_create_sel;
wire x_pop_en;
wire [39:0] x_read_data;
//==========================================================
// Parameters
//==========================================================
//----------------------------------------------------------
// ROB Parameters
//----------------------------------------------------------
parameter ROB_WIDTH = 40;
parameter ROB_VL_PRED = 39;
parameter ROB_VL = 38;
parameter ROB_VEC_DIRTY = 30;
parameter ROB_VSETVLI = 29;
parameter ROB_VSEW = 28;
parameter ROB_VLMUL = 25;
parameter ROB_NO_SPEC_MISPRED = 23;
parameter ROB_NO_SPEC_MISS = 22;
parameter ROB_NO_SPEC_HIT = 21;
parameter ROB_LOAD = 20;
parameter ROB_FP_DIRTY = 19;
parameter ROB_INST_NUM = 18;
parameter ROB_BKPTB_INST = 16;
parameter ROB_BKPTA_INST = 15;
parameter ROB_BKPTB_DATA = 14;
parameter ROB_BKPTA_DATA = 13;
parameter ROB_STORE = 12;
parameter ROB_RAS = 11;
parameter ROB_PCFIFO = 10;
parameter ROB_BJU = 9;
parameter ROB_INTMASK = 8;
parameter ROB_SPLIT = 7;
parameter ROB_PC_OFFSET = 6;
parameter ROB_CMPLT_CNT = 3;
parameter ROB_CMPLT = 1;
parameter ROB_VLD = 0;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = retire_rob_flush_gateclk
|| x_create_gateclk_en
|| x_cmplt_gateclk_vld
|| x_pop_en;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @76
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @77
// .external_en (1'b0), @78
// .global_en (cp0_yy_clk_en), @79
// .module_en (cp0_rtu_icg_en), @80
// .local_en (entry_clk_en), @81
// .clk_out (entry_clk)); @82
assign create_clk_en = x_create_gateclk_en;
// &Instance("gated_clk_cell", "x_create_data_gated_clk"); @85
gated_clk_cell x_create_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (create_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (create_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @86
// .external_en (1'b0), @87
// .global_en (cp0_yy_clk_en), @88
// .module_en (cp0_rtu_icg_en), @89
// .local_en (create_clk_en), @90
// .clk_out (create_clk)); @91
assign lsu_cmplt_clk_en = x_create_gateclk_en
|| lsu_misc_cmplt_gateclk_en;
// &Instance("gated_clk_cell", "x_lsu_cmplt_gated_clk"); @95
gated_clk_cell x_lsu_cmplt_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (lsu_cmplt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lsu_cmplt_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @96
// .external_en (1'b0), @97
// .global_en (cp0_yy_clk_en), @98
// .module_en (cp0_rtu_icg_en), @99
// .local_en (lsu_cmplt_clk_en), @100
// .clk_out (lsu_cmplt_clk)); @101
//==========================================================
// Create Port
//==========================================================
// &CombBeg; @106
always @( idu_rtu_rob_create1_data[39:0]
or idu_rtu_rob_create3_data[39:0]
or x_create_sel[3:0]
or idu_rtu_rob_create0_data[39:0]
or idu_rtu_rob_create2_data[39:0])
begin
case (x_create_sel[3:0])
4'h1 : x_create_data[ROB_WIDTH-1:0] = idu_rtu_rob_create0_data[ROB_WIDTH-1:0];
4'h2 : x_create_data[ROB_WIDTH-1:0] = idu_rtu_rob_create1_data[ROB_WIDTH-1:0];
4'h4 : x_create_data[ROB_WIDTH-1:0] = idu_rtu_rob_create2_data[ROB_WIDTH-1:0];
4'h8 : x_create_data[ROB_WIDTH-1:0] = idu_rtu_rob_create3_data[ROB_WIDTH-1:0];
default: x_create_data[ROB_WIDTH-1:0] = {ROB_WIDTH{1'bx}};
endcase
// &CombEnd; @114
end
//==========================================================
// Entry Valid
//==========================================================
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vld <= 1'b0;
else if(retire_rob_flush)
vld <= 1'b0;
else if(x_create_en)
vld <= x_create_data[ROB_VLD];
else if(x_pop_en)
vld <= 1'b0;
else
vld <= vld;
end
assign x_read_data[ROB_VLD] = vld;
//==========================================================
// Cmplt counter and Cmplt bit
//==========================================================
//----------------------------------------------------------
// Prepare cmplt cnt create and cmplt value
//----------------------------------------------------------
assign cmplt_1_fold_inst =
x_cmplt_vld[0] && !x_cmplt_vld[1] && !x_cmplt_vld[5] && !x_cmplt_vld[6]
|| !x_cmplt_vld[0] && x_cmplt_vld[1] && !x_cmplt_vld[5] && !x_cmplt_vld[6]
|| !x_cmplt_vld[0] && !x_cmplt_vld[1] && x_cmplt_vld[5] && !x_cmplt_vld[6]
|| !x_cmplt_vld[0] && !x_cmplt_vld[1] && !x_cmplt_vld[5] && x_cmplt_vld[6];
assign cmplt_2_fold_inst =
x_cmplt_vld[0] && x_cmplt_vld[1] && !x_cmplt_vld[5] && !x_cmplt_vld[6]
|| x_cmplt_vld[0] && !x_cmplt_vld[1] && x_cmplt_vld[5] && !x_cmplt_vld[6]
|| x_cmplt_vld[0] && !x_cmplt_vld[1] && !x_cmplt_vld[5] && x_cmplt_vld[6]
|| !x_cmplt_vld[0] && x_cmplt_vld[1] && x_cmplt_vld[5] && !x_cmplt_vld[6]
|| !x_cmplt_vld[0] && x_cmplt_vld[1] && !x_cmplt_vld[5] && x_cmplt_vld[6]
|| !x_cmplt_vld[0] && !x_cmplt_vld[1] && x_cmplt_vld[5] && x_cmplt_vld[6];
assign cmplt_3_fold_inst =
x_cmplt_vld[0] && x_cmplt_vld[1] && x_cmplt_vld[5] && !x_cmplt_vld[6]
|| x_cmplt_vld[0] && x_cmplt_vld[1] && !x_cmplt_vld[5] && x_cmplt_vld[6]
|| x_cmplt_vld[0] && !x_cmplt_vld[1] && x_cmplt_vld[5] && x_cmplt_vld[6]
|| !x_cmplt_vld[0] && x_cmplt_vld[1] && x_cmplt_vld[5] && x_cmplt_vld[6];
assign cmplt_cnt_cmplt_exist[1:0] =
// 2.1 0 inst cmplt
{2{!(|x_cmplt_vld[6:0])}} & cmplt_cnt_with_create[1:0]
// 2.2 1 fold inst cmplt
| {2{cmplt_1_fold_inst}} & (cmplt_cnt_with_create[1:0] - 2'd1)
// 2.3 2 fold inst cmplt
| {2{cmplt_2_fold_inst}} & (cmplt_cnt_with_create[1:0] - 2'd2)
// 2.4 3 fold inst cmplt
| {2{cmplt_3_fold_inst}} & 2'd0
// 2.5 other inst cmplt
| {2{(|x_cmplt_vld[6:2])}} & 2'd0;
//----------------------------------------------------------
// cmplt cnt
//----------------------------------------------------------
assign cmplt_cnt_with_create[1:0] = x_create_en
? x_create_data[ROB_CMPLT_CNT:ROB_CMPLT_CNT-1]
: cmplt_cnt[1:0];
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cmplt_cnt[1:0] <= 2'b0;
else if(|x_cmplt_vld[6:0])
cmplt_cnt[1:0] <= cmplt_cnt_cmplt_exist[1:0];
else if(x_create_en)
cmplt_cnt[1:0] <= x_create_data[ROB_CMPLT_CNT:ROB_CMPLT_CNT-1];
else
cmplt_cnt[1:0] <= cmplt_cnt[1:0];
end
assign x_read_data[ROB_CMPLT_CNT:ROB_CMPLT_CNT-1] = cmplt_cnt[1:0];
//----------------------------------------------------------
// Prepare cmplt create and cmplt value
//----------------------------------------------------------
//1.if create to new or exist entry, cmplt will be 0
//2.if no create in and inst cmplt, cmplt will be 1 if
assign cmplt_updt_val =
// 2.1 1 fold inst cmplt and cmplt cnt is 1
(cmplt_1_fold_inst) && (cmplt_cnt_with_create[1:0] == 2'd1)
// 2.2 2 fold inst cmplt and cmplt cnt is 2
|| (cmplt_2_fold_inst) && (cmplt_cnt_with_create[1:0] == 2'd2)
// 2.3 3 fold inst cmplt and (cmplt cnt is/must be 3)
|| (cmplt_3_fold_inst)
// 2.4 other inst cmplt no matter cmplt cnt
|| (|x_cmplt_vld[4:2]);
//----------------------------------------------------------
// cmplt
//----------------------------------------------------------
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cmplt <= 1'b0;
else if(|x_cmplt_vld[6:0])
cmplt <= cmplt_updt_val;
else if(x_create_en)
cmplt <= x_create_data[ROB_CMPLT];
else
cmplt <= cmplt;
end
assign x_read_data[ROB_CMPLT] = cmplt;
//==========================================================
// Instruction Complete Information
//==========================================================
//bkpta_data and bkptb_data can only from pipe3/4
assign bkpta_data_updt_val = x_cmplt_vld[3] && lsu_rtu_wb_pipe3_bkpta_data
|| x_cmplt_vld[4] && lsu_rtu_wb_pipe4_bkpta_data;
assign bkptb_data_updt_val = x_cmplt_vld[3] && lsu_rtu_wb_pipe3_bkptb_data
|| x_cmplt_vld[4] && lsu_rtu_wb_pipe4_bkptb_data;
assign no_spec_hit_updt_val = x_cmplt_vld[3] && lsu_rtu_wb_pipe3_no_spec_hit
|| x_cmplt_vld[4] && lsu_rtu_wb_pipe4_no_spec_hit;
assign no_spec_miss_updt_val = x_cmplt_vld[3] && lsu_rtu_wb_pipe3_no_spec_miss
|| x_cmplt_vld[4] && lsu_rtu_wb_pipe4_no_spec_miss;
assign no_spec_mispred_updt_val = x_cmplt_vld[3] && lsu_rtu_wb_pipe3_no_spec_mispred
|| x_cmplt_vld[4] && lsu_rtu_wb_pipe4_no_spec_mispred;
always @(posedge lsu_cmplt_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
bkpta_data <= 1'b0;
bkptb_data <= 1'b0;
no_spec_hit <= 1'b0;
no_spec_miss <= 1'b0;
no_spec_mispred <= 1'b0;
end
else if(|x_cmplt_vld[4:3]) begin
bkpta_data <= bkpta_data_updt_val;
bkptb_data <= bkptb_data_updt_val;
no_spec_hit <= no_spec_hit_updt_val;
no_spec_miss <= no_spec_miss_updt_val;
no_spec_mispred <= no_spec_mispred_updt_val;
end
else if(x_create_dp_en) begin
bkpta_data <= x_create_data[ROB_BKPTA_DATA];
bkptb_data <= x_create_data[ROB_BKPTB_DATA];
no_spec_hit <= x_create_data[ROB_NO_SPEC_HIT];
no_spec_miss <= x_create_data[ROB_NO_SPEC_MISS];
no_spec_mispred <= x_create_data[ROB_NO_SPEC_MISPRED];
end
else begin
bkpta_data <= bkpta_data;
bkptb_data <= bkptb_data;
no_spec_hit <= no_spec_hit;
no_spec_miss <= no_spec_miss;
no_spec_mispred <= no_spec_mispred;
end
end
//rename for read output
assign x_read_data[ROB_BKPTA_DATA] = bkpta_data;
assign x_read_data[ROB_BKPTB_DATA] = bkptb_data;
assign x_read_data[ROB_NO_SPEC_HIT] = no_spec_hit;
assign x_read_data[ROB_NO_SPEC_MISS] = no_spec_miss;
assign x_read_data[ROB_NO_SPEC_MISPRED] = no_spec_mispred;
//==========================================================
// Instruction Create Information
//==========================================================
always @(posedge create_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
pc_offset[2:0] <= 3'b0;
split <= 1'b0;
intmask <= 1'b0;
bju <= 1'b0;
pcfifo <= 1'b0;
ras <= 1'b0;
store <= 1'b0;
bkpta_inst <= 1'b0;
bkptb_inst <= 1'b0;
inst_num[1:0] <= 2'b0;
fp_dirty <= 1'b0;
load <= 1'b0;
vlmul[1:0] <= 2'b0;
vsew[2:0] <= 3'b0;
vsetvli <= 1'b0;
vec_dirty <= 1'b0;
vl[7:0] <= 8'b0;
vl_pred <= 1'b0;
end
else if(x_create_dp_en) begin
pc_offset[2:0] <= x_create_data[ROB_PC_OFFSET:ROB_PC_OFFSET-2];
split <= x_create_data[ROB_SPLIT];
intmask <= x_create_data[ROB_INTMASK];
bju <= x_create_data[ROB_BJU];
pcfifo <= x_create_data[ROB_PCFIFO];
ras <= x_create_data[ROB_RAS];
store <= x_create_data[ROB_STORE];
bkpta_inst <= x_create_data[ROB_BKPTA_INST];
bkptb_inst <= x_create_data[ROB_BKPTB_INST];
inst_num[1:0] <= x_create_data[ROB_INST_NUM:ROB_INST_NUM-1];
fp_dirty <= x_create_data[ROB_FP_DIRTY];
load <= x_create_data[ROB_LOAD];
vlmul[1:0] <= x_create_data[ROB_VLMUL:ROB_VLMUL-1];
vsew[2:0] <= x_create_data[ROB_VSEW:ROB_VSEW-2];
vsetvli <= x_create_data[ROB_VSETVLI];
vec_dirty <= x_create_data[ROB_VEC_DIRTY];
vl[7:0] <= x_create_data[ROB_VL:ROB_VL-7];
vl_pred <= x_create_data[ROB_VL_PRED];
end
else begin
pc_offset[2:0] <= pc_offset[2:0];
split <= split;
intmask <= intmask;
bju <= bju;
pcfifo <= pcfifo;
ras <= ras;
store <= store;
bkpta_inst <= bkpta_inst;
bkptb_inst <= bkptb_inst;
inst_num[1:0] <= inst_num[1:0];
fp_dirty <= fp_dirty;
load <= load;
vlmul[1:0] <= vlmul[1:0];
vsew[2:0] <= vsew[2:0];
vsetvli <= vsetvli;
vec_dirty <= vec_dirty;
vl[7:0] <= vl[7:0];
vl_pred <= vl_pred;
end
end
//rename for read output
assign x_read_data[ROB_PC_OFFSET:ROB_PC_OFFSET-2] = pc_offset[2:0];
assign x_read_data[ROB_SPLIT] = split;
assign x_read_data[ROB_INTMASK] = intmask;
assign x_read_data[ROB_BJU] = bju;
assign x_read_data[ROB_PCFIFO] = pcfifo;
assign x_read_data[ROB_RAS] = ras;
assign x_read_data[ROB_STORE] = store;
assign x_read_data[ROB_BKPTA_INST] = bkpta_inst;
assign x_read_data[ROB_BKPTB_INST] = bkptb_inst;
assign x_read_data[ROB_INST_NUM:ROB_INST_NUM-1] = inst_num[1:0];
assign x_read_data[ROB_FP_DIRTY] = fp_dirty;
assign x_read_data[ROB_LOAD] = load;
assign x_read_data[ROB_VLMUL:ROB_VLMUL-1] = vlmul[1:0];
assign x_read_data[ROB_VSEW:ROB_VSEW-2] = vsew[2:0];
assign x_read_data[ROB_VSETVLI] = vsetvli;
assign x_read_data[ROB_VEC_DIRTY] = vec_dirty;
assign x_read_data[ROB_VL:ROB_VL-7] = vl[7:0];
assign x_read_data[ROB_VL_PRED] = vl_pred;
// &ModuleEnd; @366
endmodule |
module ct_rtu_compare_iid(
x_iid0,
x_iid0_older,
x_iid1
);
// &Ports; @25
input [6:0] x_iid0;
input [6:0] x_iid1;
output x_iid0_older;
// &Regs; @26
// &Wires; @27
wire iid0_5_0_larger;
wire [5:0] iid0_larger;
wire iid1_5_0_larger;
wire [5:0] iid1_larger;
wire iid_msb_mismatch;
wire [6:0] x_iid0;
wire x_iid0_older;
wire [6:0] x_iid1;
//==========================================================
// Compare order of two 7 bits IIDs
//==========================================================
assign iid_msb_mismatch = x_iid0[6] ^ x_iid1[6];
assign iid0_larger[5] = x_iid0[5] && !x_iid1[5];
assign iid0_larger[4] = x_iid0[4] && !x_iid1[4];
assign iid0_larger[3] = x_iid0[3] && !x_iid1[3];
assign iid0_larger[2] = x_iid0[2] && !x_iid1[2];
assign iid0_larger[1] = x_iid0[1] && !x_iid1[1];
assign iid0_larger[0] = x_iid0[0] && !x_iid1[0];
assign iid1_larger[5] = !x_iid0[5] && x_iid1[5];
assign iid1_larger[4] = !x_iid0[4] && x_iid1[4];
assign iid1_larger[3] = !x_iid0[3] && x_iid1[3];
assign iid1_larger[2] = !x_iid0[2] && x_iid1[2];
assign iid1_larger[1] = !x_iid0[1] && x_iid1[1];
assign iid1_larger[0] = !x_iid0[0] && x_iid1[0];
assign iid0_5_0_larger =
iid0_larger[5]
|| iid0_larger[4] && !iid1_larger[5]
|| iid0_larger[3] && !(|iid1_larger[5:4])
|| iid0_larger[2] && !(|iid1_larger[5:3])
|| iid0_larger[1] && !(|iid1_larger[5:2])
|| iid0_larger[0] && !(|iid1_larger[5:1]);
assign iid1_5_0_larger =
iid1_larger[5]
|| iid1_larger[4] && !iid0_larger[5]
|| iid1_larger[3] && !(|iid0_larger[5:4])
|| iid1_larger[2] && !(|iid0_larger[5:3])
|| iid1_larger[1] && !(|iid0_larger[5:2])
|| iid1_larger[0] && !(|iid0_larger[5:1]);
assign x_iid0_older = !iid_msb_mismatch && iid1_5_0_larger
|| iid_msb_mismatch && iid0_5_0_larger;
// &ModuleEnd; @67
endmodule |
module ct_rtu_pst_preg_entry(
cp0_rtu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dealloc_vld_for_gateclk,
forever_cpuclk,
idu_rtu_pst_dis_inst0_dst_reg,
idu_rtu_pst_dis_inst0_preg_iid,
idu_rtu_pst_dis_inst0_rel_preg,
idu_rtu_pst_dis_inst1_dst_reg,
idu_rtu_pst_dis_inst1_preg_iid,
idu_rtu_pst_dis_inst1_rel_preg,
idu_rtu_pst_dis_inst2_dst_reg,
idu_rtu_pst_dis_inst2_preg_iid,
idu_rtu_pst_dis_inst2_rel_preg,
idu_rtu_pst_dis_inst3_dst_reg,
idu_rtu_pst_dis_inst3_preg_iid,
idu_rtu_pst_dis_inst3_rel_preg,
ifu_xx_sync_reset,
pad_yy_icg_scan_en,
retire_pst_async_flush,
retire_pst_wb_retire_inst0_preg_vld,
retire_pst_wb_retire_inst1_preg_vld,
retire_pst_wb_retire_inst2_preg_vld,
rob_pst_retire_inst0_gateclk_vld,
rob_pst_retire_inst0_iid_updt_val,
rob_pst_retire_inst1_gateclk_vld,
rob_pst_retire_inst1_iid_updt_val,
rob_pst_retire_inst2_gateclk_vld,
rob_pst_retire_inst2_iid_updt_val,
rtu_yy_xx_flush,
x_create_vld,
x_cur_state_dealloc,
x_dealloc_mask,
x_dealloc_vld,
x_dreg,
x_rel_preg_expand,
x_release_vld,
x_reset_dst_reg,
x_reset_mapped,
x_retired_released_wb,
x_wb_vld
);
// &Ports; @28
input cp0_rtu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input dealloc_vld_for_gateclk;
input forever_cpuclk;
input [4 :0] idu_rtu_pst_dis_inst0_dst_reg;
input [6 :0] idu_rtu_pst_dis_inst0_preg_iid;
input [6 :0] idu_rtu_pst_dis_inst0_rel_preg;
input [4 :0] idu_rtu_pst_dis_inst1_dst_reg;
input [6 :0] idu_rtu_pst_dis_inst1_preg_iid;
input [6 :0] idu_rtu_pst_dis_inst1_rel_preg;
input [4 :0] idu_rtu_pst_dis_inst2_dst_reg;
input [6 :0] idu_rtu_pst_dis_inst2_preg_iid;
input [6 :0] idu_rtu_pst_dis_inst2_rel_preg;
input [4 :0] idu_rtu_pst_dis_inst3_dst_reg;
input [6 :0] idu_rtu_pst_dis_inst3_preg_iid;
input [6 :0] idu_rtu_pst_dis_inst3_rel_preg;
input ifu_xx_sync_reset;
input pad_yy_icg_scan_en;
input retire_pst_async_flush;
input retire_pst_wb_retire_inst0_preg_vld;
input retire_pst_wb_retire_inst1_preg_vld;
input retire_pst_wb_retire_inst2_preg_vld;
input rob_pst_retire_inst0_gateclk_vld;
input [6 :0] rob_pst_retire_inst0_iid_updt_val;
input rob_pst_retire_inst1_gateclk_vld;
input [6 :0] rob_pst_retire_inst1_iid_updt_val;
input rob_pst_retire_inst2_gateclk_vld;
input [6 :0] rob_pst_retire_inst2_iid_updt_val;
input rtu_yy_xx_flush;
input [3 :0] x_create_vld;
input x_dealloc_mask;
input x_dealloc_vld;
input x_release_vld;
input [4 :0] x_reset_dst_reg;
input x_reset_mapped;
input x_wb_vld;
output x_cur_state_dealloc;
output [31:0] x_dreg;
output [95:0] x_rel_preg_expand;
output x_retired_released_wb;
// &Regs; @29
reg [4 :0] create_dst_reg;
reg [6 :0] create_iid;
reg [6 :0] create_rel_preg;
reg [4 :0] dst_reg;
reg [6 :0] iid;
reg [4 :0] lifecycle_cur_state;
reg [4 :0] lifecycle_next_state;
reg [6 :0] rel_preg;
reg retire_inst0_iid_match;
reg retire_inst1_iid_match;
reg retire_inst2_iid_match;
reg wb_cur_state;
reg wb_next_state;
// &Wires; @30
wire alloc_clk;
wire alloc_clk_en;
wire cp0_rtu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_vld;
wire dealloc_vld_for_gateclk;
wire [31:0] dst_reg_expand;
wire forever_cpuclk;
wire [4 :0] idu_rtu_pst_dis_inst0_dst_reg;
wire [6 :0] idu_rtu_pst_dis_inst0_preg_iid;
wire [6 :0] idu_rtu_pst_dis_inst0_rel_preg;
wire [4 :0] idu_rtu_pst_dis_inst1_dst_reg;
wire [6 :0] idu_rtu_pst_dis_inst1_preg_iid;
wire [6 :0] idu_rtu_pst_dis_inst1_rel_preg;
wire [4 :0] idu_rtu_pst_dis_inst2_dst_reg;
wire [6 :0] idu_rtu_pst_dis_inst2_preg_iid;
wire [6 :0] idu_rtu_pst_dis_inst2_rel_preg;
wire [4 :0] idu_rtu_pst_dis_inst3_dst_reg;
wire [6 :0] idu_rtu_pst_dis_inst3_preg_iid;
wire [6 :0] idu_rtu_pst_dis_inst3_rel_preg;
wire ifu_xx_sync_reset;
wire lifecycle_cur_state_alloc;
wire lifecycle_cur_state_dealloc;
wire lifecycle_cur_state_release;
wire lifecycle_cur_state_retire;
wire pad_yy_icg_scan_en;
wire [95:0] rel_preg_expand;
wire rel_retire_vld;
wire [4 :0] reset_lifecycle_state;
wire reset_wb_state;
wire retire_gateclk_vld;
wire retire_inst0_iid_match_updt_val;
wire retire_inst1_iid_match_updt_val;
wire retire_inst2_iid_match_updt_val;
wire retire_inst_iid_match_gateclk_en;
wire retire_pst_async_flush;
wire retire_pst_wb_retire_inst0_preg_vld;
wire retire_pst_wb_retire_inst1_preg_vld;
wire retire_pst_wb_retire_inst2_preg_vld;
wire retire_vld;
wire rob_pst_retire_inst0_gateclk_vld;
wire [6 :0] rob_pst_retire_inst0_iid_updt_val;
wire rob_pst_retire_inst1_gateclk_vld;
wire [6 :0] rob_pst_retire_inst1_iid_updt_val;
wire rob_pst_retire_inst2_gateclk_vld;
wire [6 :0] rob_pst_retire_inst2_iid_updt_val;
wire rtu_yy_xx_flush;
wire sm_clk;
wire sm_clk_en;
wire wb_cur_state_wb;
wire wb_cur_state_wb_masked;
wire [3 :0] x_create_vld;
wire x_cur_state_dealloc;
wire x_dealloc_mask;
wire x_dealloc_vld;
wire [31:0] x_dreg;
wire [95:0] x_rel_preg_expand;
wire x_release_vld;
wire [4 :0] x_reset_dst_reg;
wire x_reset_mapped;
wire x_retired_released_wb;
wire x_wb_vld;
parameter DEALLOC = 5'b00001;
parameter WF_ALLOC = 5'b00010;
parameter ALLOC = 5'b00100;
parameter RETIRE = 5'b01000;
parameter RELEASE = 5'b10000;
parameter IDLE = 1'b0;
parameter WB = 1'b1;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign sm_clk_en = rtu_yy_xx_flush
|| retire_pst_async_flush
|| ifu_xx_sync_reset
|| dealloc_vld_for_gateclk
&& lifecycle_cur_state_dealloc
|| (lifecycle_cur_state[4:0] == RETIRE)
&& retire_gateclk_vld
// && x_release_vld
|| x_wb_vld
|| (lifecycle_cur_state[4:0] == WF_ALLOC)
&& create_vld
|| lifecycle_cur_state_alloc
&& (retire_vld || retire_inst_iid_match_gateclk_en)
|| lifecycle_cur_state_release
&& wb_cur_state_wb
|| lifecycle_cur_state_dealloc
&& wb_cur_state_wb;
// &Instance("gated_clk_cell", "x_sm_gated_clk"); @61
gated_clk_cell x_sm_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (sm_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (sm_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @62
// .external_en (1'b0), @63
// .global_en (cp0_yy_clk_en), @64
// .module_en (cp0_rtu_icg_en), @65
// .local_en (sm_clk_en), @66
// .clk_out (sm_clk)); @67
assign alloc_clk_en = ifu_xx_sync_reset
|| create_vld;
// &Instance("gated_clk_cell", "x_alloc_gated_clk"); @71
gated_clk_cell x_alloc_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (alloc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (alloc_clk_en ),
.module_en (cp0_rtu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @72
// .external_en (1'b0), @73
// .global_en (cp0_yy_clk_en), @74
// .module_en (cp0_rtu_icg_en), @75
// .local_en (alloc_clk_en), @76
// .clk_out (alloc_clk)); @77
//==========================================================
// Preg Lifecycle State Machine
//==========================================================
assign reset_lifecycle_state[4:0] = (x_reset_mapped) ? RETIRE : DEALLOC;
//----------------------------------------------------------
// FSM of Preg liftcycle
//----------------------------------------------------------
// State Description:
// DEALLOC : preg is released and written back, could
// allocate to new producer
// WF_ALLOC : preg is in allocate preg register
// ALLOC : preg is allocated to producer
// RETIRE : producer is retired but preg is not released
// RELEASE : preg is released
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
lifecycle_cur_state[4:0] <= DEALLOC;
else if(ifu_xx_sync_reset)
lifecycle_cur_state[4:0] <= reset_lifecycle_state[4:0];
else
lifecycle_cur_state[4:0] <= lifecycle_next_state[4:0];
end
// &CombBeg; @105
always @( retire_vld
or wb_cur_state_wb_masked
or x_dealloc_vld
or rtu_yy_xx_flush
or x_release_vld
or lifecycle_cur_state[4:0]
or create_vld)
begin
case(lifecycle_cur_state[4:0])
DEALLOC : if(x_dealloc_vld && !rtu_yy_xx_flush)
lifecycle_next_state[4:0] = WF_ALLOC;
else
lifecycle_next_state[4:0] = DEALLOC;
WF_ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(create_vld)
lifecycle_next_state[4:0] = ALLOC;
else
lifecycle_next_state[4:0] = WF_ALLOC;
ALLOC : if(rtu_yy_xx_flush)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld && wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else if(retire_vld)
lifecycle_next_state[4:0] = RETIRE;
else
lifecycle_next_state[4:0] = ALLOC;
RETIRE : if(x_release_vld && wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else if(x_release_vld)
lifecycle_next_state[4:0] = RELEASE;
else
lifecycle_next_state[4:0] = RETIRE;
RELEASE : if(wb_cur_state_wb_masked)
lifecycle_next_state[4:0] = DEALLOC;
else
lifecycle_next_state[4:0] = RELEASE;
default : lifecycle_next_state[4:0] = DEALLOC;
endcase
// &CombEnd; @139
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign lifecycle_cur_state_dealloc = lifecycle_cur_state[0];
assign lifecycle_cur_state_alloc = lifecycle_cur_state[2];
assign lifecycle_cur_state_retire = lifecycle_cur_state[3];
assign lifecycle_cur_state_release = lifecycle_cur_state[4];
assign x_cur_state_dealloc = lifecycle_cur_state_dealloc;
//==========================================================
// Preg Write Back State Machine
//==========================================================
assign reset_wb_state = (x_reset_mapped) ? WB : IDLE;
//----------------------------------------------------------
// FSM of Preg write back
//----------------------------------------------------------
// State Description:
// IDLE : preg is not written back
// WB : preg is written back
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
wb_cur_state <= IDLE;
else if(retire_pst_async_flush)
wb_cur_state <= WB;
else if(ifu_xx_sync_reset)
wb_cur_state <= reset_wb_state;
else if(create_vld)
wb_cur_state <= IDLE;
else
wb_cur_state <= wb_next_state;
end
// &CombBeg; @177
always @( lifecycle_cur_state_dealloc
or x_wb_vld
or wb_cur_state)
begin
case(wb_cur_state)
IDLE : if(x_wb_vld)
wb_next_state = WB;
else
wb_next_state = IDLE;
WB : if(lifecycle_cur_state_dealloc)
wb_next_state = IDLE;
else
wb_next_state = WB;
default : wb_next_state = IDLE;
endcase
// &CombEnd; @189
end
//----------------------------------------------------------
// Control Siganls
//----------------------------------------------------------
assign wb_cur_state_wb = (wb_cur_state == WB);
assign wb_cur_state_wb_masked = (wb_cur_state == WB) && !x_dealloc_mask;
//==========================================================
// Preg information
//==========================================================
//----------------------------------------------------------
// Prepare allocate create data
//----------------------------------------------------------
assign create_vld = |x_create_vld[3:0];
// &CombBeg; @204
always @( idu_rtu_pst_dis_inst3_preg_iid[6:0]
or idu_rtu_pst_dis_inst3_dst_reg[4:0]
or idu_rtu_pst_dis_inst0_rel_preg[6:0]
or idu_rtu_pst_dis_inst3_rel_preg[6:0]
or idu_rtu_pst_dis_inst1_preg_iid[6:0]
or idu_rtu_pst_dis_inst2_rel_preg[6:0]
or idu_rtu_pst_dis_inst1_rel_preg[6:0]
or idu_rtu_pst_dis_inst1_dst_reg[4:0]
or x_create_vld[3:0]
or idu_rtu_pst_dis_inst0_preg_iid[6:0]
or idu_rtu_pst_dis_inst2_preg_iid[6:0]
or idu_rtu_pst_dis_inst0_dst_reg[4:0]
or idu_rtu_pst_dis_inst2_dst_reg[4:0])
begin
case (x_create_vld[3:0])
4'h1 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst0_preg_iid[6:0];
create_dst_reg[4:0] = idu_rtu_pst_dis_inst0_dst_reg[4:0];
create_rel_preg[6:0] = idu_rtu_pst_dis_inst0_rel_preg[6:0];
end
4'h2 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst1_preg_iid[6:0];
create_dst_reg[4:0] = idu_rtu_pst_dis_inst1_dst_reg[4:0];
create_rel_preg[6:0] = idu_rtu_pst_dis_inst1_rel_preg[6:0];
end
4'h4 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst2_preg_iid[6:0];
create_dst_reg[4:0] = idu_rtu_pst_dis_inst2_dst_reg[4:0];
create_rel_preg[6:0] = idu_rtu_pst_dis_inst2_rel_preg[6:0];
end
4'h8 : begin
create_iid[6:0] = idu_rtu_pst_dis_inst3_preg_iid[6:0];
create_dst_reg[4:0] = idu_rtu_pst_dis_inst3_dst_reg[4:0];
create_rel_preg[6:0] = idu_rtu_pst_dis_inst3_rel_preg[6:0];
end
default: begin
create_iid[6:0] = {7{1'bx}};
create_dst_reg[4:0] = {5{1'bx}};
create_rel_preg[6:0] = {7{1'bx}};
end
endcase
// &CombEnd; @232
end
//----------------------------------------------------------
// Information Register
//----------------------------------------------------------
always @(posedge alloc_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
iid[6:0] <= 7'd0;
dst_reg[4:0] <= 5'd0;
rel_preg[6:0] <= 7'd0;
end
else if(ifu_xx_sync_reset) begin
iid[6:0] <= 7'd0;
dst_reg[4:0] <= x_reset_dst_reg[4:0];
rel_preg[6:0] <= 7'd0;
end
else if(create_vld) begin
iid[6:0] <= create_iid[6:0];
dst_reg[4:0] <= create_dst_reg[4:0];
rel_preg[6:0] <= create_rel_preg[6:0];
end
else begin
iid[6:0] <= iid[6:0];
dst_reg[4:0] <= dst_reg[4:0];
rel_preg[6:0] <= rel_preg[6:0];
end
end
//----------------------------------------------------------
// Retire IID Match Register
//----------------------------------------------------------
//timing optimization: compare retire inst iid before retire
assign retire_inst0_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst0_iid_updt_val[6:0]);
assign retire_inst1_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst1_iid_updt_val[6:0]);
assign retire_inst2_iid_match_updt_val =
lifecycle_cur_state_alloc
&& (iid[6:0] == rob_pst_retire_inst2_iid_updt_val[6:0]);
assign retire_inst_iid_match_gateclk_en =
rob_pst_retire_inst0_gateclk_vld
|| rob_pst_retire_inst1_gateclk_vld
|| rob_pst_retire_inst2_gateclk_vld;
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst0_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst0_iid_match <= 1'b0;
else if(rob_pst_retire_inst0_gateclk_vld)
retire_inst0_iid_match <= retire_inst0_iid_match_updt_val;
else
retire_inst0_iid_match <= retire_inst0_iid_match;
end
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst1_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst1_iid_match <= 1'b0;
else if(rob_pst_retire_inst1_gateclk_vld)
retire_inst1_iid_match <= retire_inst1_iid_match_updt_val;
else
retire_inst1_iid_match <= retire_inst1_iid_match;
end
always @(posedge sm_clk or negedge cpurst_b)
begin
if(!cpurst_b)
retire_inst2_iid_match <= 1'b0;
else if(ifu_xx_sync_reset)
retire_inst2_iid_match <= 1'b0;
else if(rob_pst_retire_inst2_gateclk_vld)
retire_inst2_iid_match <= retire_inst2_iid_match_updt_val;
else
retire_inst2_iid_match <= retire_inst2_iid_match;
end
//==========================================================
// Retire signal
//==========================================================
assign retire_vld = retire_pst_wb_retire_inst0_preg_vld
&& retire_inst0_iid_match
|| retire_pst_wb_retire_inst1_preg_vld
&& retire_inst1_iid_match
|| retire_pst_wb_retire_inst2_preg_vld
&& retire_inst2_iid_match;
assign retire_gateclk_vld = retire_pst_wb_retire_inst0_preg_vld
|| retire_pst_wb_retire_inst1_preg_vld
|| retire_pst_wb_retire_inst2_preg_vld;
//==========================================================
// Release signal
//==========================================================
// &ConnRule(s/^x_num/rel_preg/); @333
// &Instance("ct_rtu_expand_96","x_ct_rtu_expand_96_rel_preg"); @334
ct_rtu_expand_96 x_ct_rtu_expand_96_rel_preg (
.x_num (rel_preg ),
.x_num_expand (rel_preg_expand)
);
//iid match is already AND with cur state alloc
assign rel_retire_vld = lifecycle_cur_state_alloc && retire_vld;
assign x_rel_preg_expand[95:0] =
{96{rel_retire_vld}} & rel_preg_expand[95:0];
//==========================================================
// Rename Table Recovery signal
//==========================================================
// &ConnRule(s/^x_num/dst_reg/); @344
// &Instance("ct_rtu_expand_32","x_ct_rtu_expand_32_dst_reg"); @345
ct_rtu_expand_32 x_ct_rtu_expand_32_dst_reg (
.x_num (dst_reg ),
.x_num_expand (dst_reg_expand)
);
assign x_dreg[31:0] = {32{lifecycle_cur_state_retire}}
& dst_reg_expand[31:0];
//==========================================================
// Fast Retired Instruction Write Back
//==========================================================
//this signal will be used at retiring cycle by FLUSH state machine
//should consider the retiring insts
assign x_retired_released_wb = (lifecycle_cur_state_alloc
&& retire_vld
|| lifecycle_cur_state_retire
|| lifecycle_cur_state_release)
? wb_cur_state_wb : 1'b1;
// &ModuleEnd; @373
endmodule |
module ct_rtu_encode_64(
x_num,
x_num_expand
);
// &Ports; @25
input [63:0] x_num_expand;
output [5 :0] x_num;
// &Regs; @26
// &Wires; @27
wire [5 :0] x_num;
wire [63:0] x_num_expand;
//==========================================================
// encode 64 bits one-hot number to 6 bits binary number
//==========================================================
assign x_num[5:0] =
{6{x_num_expand[0]}} & 6'd0
| {6{x_num_expand[1]}} & 6'd1
| {6{x_num_expand[2]}} & 6'd2
| {6{x_num_expand[3]}} & 6'd3
| {6{x_num_expand[4]}} & 6'd4
| {6{x_num_expand[5]}} & 6'd5
| {6{x_num_expand[6]}} & 6'd6
| {6{x_num_expand[7]}} & 6'd7
| {6{x_num_expand[8]}} & 6'd8
| {6{x_num_expand[9]}} & 6'd9
| {6{x_num_expand[10]}} & 6'd10
| {6{x_num_expand[11]}} & 6'd11
| {6{x_num_expand[12]}} & 6'd12
| {6{x_num_expand[13]}} & 6'd13
| {6{x_num_expand[14]}} & 6'd14
| {6{x_num_expand[15]}} & 6'd15
| {6{x_num_expand[16]}} & 6'd16
| {6{x_num_expand[17]}} & 6'd17
| {6{x_num_expand[18]}} & 6'd18
| {6{x_num_expand[19]}} & 6'd19
| {6{x_num_expand[20]}} & 6'd20
| {6{x_num_expand[21]}} & 6'd21
| {6{x_num_expand[22]}} & 6'd22
| {6{x_num_expand[23]}} & 6'd23
| {6{x_num_expand[24]}} & 6'd24
| {6{x_num_expand[25]}} & 6'd25
| {6{x_num_expand[26]}} & 6'd26
| {6{x_num_expand[27]}} & 6'd27
| {6{x_num_expand[28]}} & 6'd28
| {6{x_num_expand[29]}} & 6'd29
| {6{x_num_expand[30]}} & 6'd30
| {6{x_num_expand[31]}} & 6'd31
| {6{x_num_expand[32]}} & 6'd32
| {6{x_num_expand[33]}} & 6'd33
| {6{x_num_expand[34]}} & 6'd34
| {6{x_num_expand[35]}} & 6'd35
| {6{x_num_expand[36]}} & 6'd36
| {6{x_num_expand[37]}} & 6'd37
| {6{x_num_expand[38]}} & 6'd38
| {6{x_num_expand[39]}} & 6'd39
| {6{x_num_expand[40]}} & 6'd40
| {6{x_num_expand[41]}} & 6'd41
| {6{x_num_expand[42]}} & 6'd42
| {6{x_num_expand[43]}} & 6'd43
| {6{x_num_expand[44]}} & 6'd44
| {6{x_num_expand[45]}} & 6'd45
| {6{x_num_expand[46]}} & 6'd46
| {6{x_num_expand[47]}} & 6'd47
| {6{x_num_expand[48]}} & 6'd48
| {6{x_num_expand[49]}} & 6'd49
| {6{x_num_expand[50]}} & 6'd50
| {6{x_num_expand[51]}} & 6'd51
| {6{x_num_expand[52]}} & 6'd52
| {6{x_num_expand[53]}} & 6'd53
| {6{x_num_expand[54]}} & 6'd54
| {6{x_num_expand[55]}} & 6'd55
| {6{x_num_expand[56]}} & 6'd56
| {6{x_num_expand[57]}} & 6'd57
| {6{x_num_expand[58]}} & 6'd58
| {6{x_num_expand[59]}} & 6'd59
| {6{x_num_expand[60]}} & 6'd60
| {6{x_num_expand[61]}} & 6'd61
| {6{x_num_expand[62]}} & 6'd62
| {6{x_num_expand[63]}} & 6'd63;
// &ModuleEnd; @98
endmodule |
module ct_rtu_encode_8(
x_num,
x_num_expand
);
// &Ports; @25
input [7:0] x_num_expand;
output [2:0] x_num;
// &Regs; @26
// &Wires; @27
wire [2:0] x_num;
wire [7:0] x_num_expand;
//==========================================================
// encode 8 bits one-hot number to 3 bits binary number
//==========================================================
assign x_num[2:0] =
{3{x_num_expand[0]}} & 3'd0
| {3{x_num_expand[1]}} & 3'd1
| {3{x_num_expand[2]}} & 3'd2
| {3{x_num_expand[3]}} & 3'd3
| {3{x_num_expand[4]}} & 3'd4
| {3{x_num_expand[5]}} & 3'd5
| {3{x_num_expand[6]}} & 3'd6
| {3{x_num_expand[7]}} & 3'd7;
// &ModuleEnd; @42
endmodule |
module ct_cp0_lpmd(
biu_yy_xx_no_op,
cp0_biu_lpmd_b,
cp0_had_lpmd_b,
cp0_ifu_no_op_req,
cp0_lsu_no_op_req,
cp0_mmu_no_op_req,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
had_cp0_xx_dbg,
ifu_yy_xx_no_op,
inst_lpmd_ex1_ex2,
lpmd_cmplt,
lpmd_top_cur_state,
lsu_yy_xx_no_op,
mmu_yy_xx_no_op,
pad_yy_icg_scan_en,
regs_lpmd_int_vld,
regs_xx_icg_en,
rtu_yy_xx_dbgon,
rtu_yy_xx_flush
);
// &Ports; @25
input biu_yy_xx_no_op;
input cpurst_b;
input forever_cpuclk;
input had_cp0_xx_dbg;
input ifu_yy_xx_no_op;
input inst_lpmd_ex1_ex2;
input lsu_yy_xx_no_op;
input mmu_yy_xx_no_op;
input pad_yy_icg_scan_en;
input regs_lpmd_int_vld;
input regs_xx_icg_en;
input rtu_yy_xx_dbgon;
input rtu_yy_xx_flush;
output [1:0] cp0_biu_lpmd_b;
output [1:0] cp0_had_lpmd_b;
output cp0_ifu_no_op_req;
output cp0_lsu_no_op_req;
output cp0_mmu_no_op_req;
output cp0_yy_clk_en;
output lpmd_cmplt;
output [1:0] lpmd_top_cur_state;
// &Regs; @26
reg [1:0] cur_state;
reg [1:0] lpmd_b;
reg [1:0] next_state;
// &Wires; @27
wire biu_yy_xx_no_op;
wire [1:0] cp0_biu_lpmd_b;
wire [1:0] cp0_had_lpmd_b;
wire cp0_ifu_no_op_req;
wire cp0_lsu_no_op_req;
wire cp0_mmu_no_op_req;
wire cp0_yy_clk_en;
wire cpu_in_lpmd;
wire cpuclk;
wire cpurst_b;
wire forever_cpuclk;
wire had_cp0_xx_dbg;
wire ifu_yy_xx_no_op;
wire inst_lpmd_ex1_ex2;
wire lpmd_ack;
wire lpmd_clk_en;
wire lpmd_cmplt;
wire lpmd_in_wait_state;
wire [1:0] lpmd_top_cur_state;
wire lsu_yy_xx_no_op;
wire mmu_yy_xx_no_op;
wire pad_yy_icg_scan_en;
wire regs_lpmd_int_vld;
wire regs_xx_icg_en;
wire rtu_yy_xx_dbgon;
wire rtu_yy_xx_flush;
//==========================================================
// Instance of Gated Cell
//==========================================================
// &Instance("gated_clk_cell", "x_lpmd_gated_clk"); @32
gated_clk_cell x_lpmd_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (cpuclk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (lpmd_clk_en ),
.module_en (regs_xx_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @33
// .external_en (1'b0), @34
// .global_en (cp0_yy_clk_en), @35
// .module_en (regs_xx_icg_en), @36
// .local_en (lpmd_clk_en), @37
// .clk_out (cpuclk)); @38
//----------------------------------------------------------
// Handling the low power operating modes
//----------------------------------------------------------
// Request the BIU to enter low power mode and do
// not accept any more transaction from IFU or LSU
//-------------------FSM of lpmd req logic------------------
// State Description:
// IDLE : no lpmd instruction (wfi)
// WAIT : request biu and wait for biu ack
// the lpmd request
// LPMD : wait for wake up and then cmplt lpmd inst
//----------------------------------------------------------
parameter IDLE = 2'b00;
parameter WAIT = 2'b01;
parameter LPMD = 2'b10;
assign lpmd_clk_en = inst_lpmd_ex1_ex2 || cur_state[1:0] != IDLE;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
cur_state[1:0] <= IDLE;
else if(rtu_yy_xx_flush)
cur_state[1:0] <= IDLE;
else
cur_state[1:0] <= next_state[1:0];
end
// &CombBeg; @68
always @( cur_state[1:0]
or lpmd_ack
or inst_lpmd_ex1_ex2
or cpu_in_lpmd)
begin
case(cur_state[1:0])
IDLE : if(inst_lpmd_ex1_ex2)
next_state[1:0] = WAIT;
else
next_state[1:0] = IDLE;
WAIT : if(lpmd_ack)
next_state[1:0] = LPMD;
else
next_state[1:0] = WAIT;
LPMD : if(!cpu_in_lpmd)
next_state[1:0] = IDLE;
else
next_state[1:0] = LPMD;
default : next_state[1:0] = IDLE;
endcase
// &CombEnd; @84
end
assign lpmd_in_wait_state = cur_state[0];
assign lpmd_top_cur_state[1:0] = cur_state[1:0];
//----------------conctol signal by lpmd FSM----------------
//req if entering into WAIT state
assign cp0_ifu_no_op_req = lpmd_in_wait_state;
assign cp0_lsu_no_op_req = lpmd_in_wait_state;
assign cp0_mmu_no_op_req = lpmd_in_wait_state;
//----------------------------------------------------------
// lpmd request ack
//----------------------------------------------------------
assign lpmd_ack = lpmd_in_wait_state
&& ifu_yy_xx_no_op
&& lsu_yy_xx_no_op
&& biu_yy_xx_no_op
&& mmu_yy_xx_no_op;
assign lpmd_cmplt = (cur_state[1:0] == LPMD) && !cpu_in_lpmd;
//----------------------------------------------------------
// Send lpmd bits to BIU and HAD, when
// cp0 can enter low power mode (get biu_cp0_no_op)
//----------------------------------------------------------
// &Force("output","cp0_biu_lpmd_b"); @111
always @(posedge forever_cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
lpmd_b[1:0] <= 2'b11;
else if((had_cp0_xx_dbg || regs_lpmd_int_vld)
&& cpu_in_lpmd || rtu_yy_xx_dbgon)
lpmd_b[1:0] <= 2'b11;
else if(lpmd_ack && !cpu_in_lpmd)
begin
if(inst_lpmd_ex1_ex2)
lpmd_b[1:0] <= 2'b00;
else
lpmd_b[1:0] <= 2'b11;
end
else
lpmd_b[1:0] <= lpmd_b[1:0];
end
assign cp0_had_lpmd_b[1:0] = lpmd_b[1:0];
assign cp0_biu_lpmd_b[1:0] = lpmd_b[1:0];
//cpu ack in debug mode
assign cpu_in_lpmd = !(lpmd_b[1] & lpmd_b[0]);
//======================================================
//Generate clock enable signal to clock module
//Disable the clock when low power mode is entered
//======================================================
// &Force("output","cp0_yy_clk_en"); @141
assign cp0_yy_clk_en = lpmd_b[1] & lpmd_b[0];
// &ModuleEnd; @144
endmodule |
module ct_mmu_iutlb_fst_entry(
cp0_mmu_icg_en,
cpurst_b,
lsu_mmu_tlb_va,
pad_yy_icg_scan_en,
regs_utlb_clr,
tlboper_utlb_clr,
tlboper_utlb_inv_va_req,
utlb_clk,
utlb_entry_flg,
utlb_entry_hit,
utlb_entry_pgs,
utlb_entry_ppn,
utlb_entry_swp,
utlb_entry_swp_on,
utlb_entry_upd,
utlb_entry_vld,
utlb_entry_vpn,
utlb_fst_swp_flg,
utlb_fst_swp_pgs,
utlb_fst_swp_ppn,
utlb_fst_swp_vpn,
utlb_req_vpn,
utlb_upd_flg,
utlb_upd_pgs,
utlb_upd_ppn,
utlb_upd_vpn
);
// &Ports; @25
input cp0_mmu_icg_en;
input cpurst_b;
input [26:0] lsu_mmu_tlb_va;
input pad_yy_icg_scan_en;
input regs_utlb_clr;
input tlboper_utlb_clr;
input tlboper_utlb_inv_va_req;
input utlb_clk;
input utlb_entry_swp;
input utlb_entry_swp_on;
input utlb_entry_upd;
input [13:0] utlb_fst_swp_flg;
input [2 :0] utlb_fst_swp_pgs;
input [27:0] utlb_fst_swp_ppn;
input [26:0] utlb_fst_swp_vpn;
input [26:0] utlb_req_vpn;
input [13:0] utlb_upd_flg;
input [2 :0] utlb_upd_pgs;
input [27:0] utlb_upd_ppn;
input [26:0] utlb_upd_vpn;
output [13:0] utlb_entry_flg;
output utlb_entry_hit;
output [2 :0] utlb_entry_pgs;
output [27:0] utlb_entry_ppn;
output utlb_entry_vld;
output [26:0] utlb_entry_vpn;
// &Regs; @26
reg [13:0] utlb_flg;
reg [2 :0] utlb_pgs;
reg [27:0] utlb_ppn;
reg utlb_vld;
reg [26:0] utlb_vpn;
// &Wires; @27
wire cp0_mmu_icg_en;
wire cpurst_b;
wire ctc_inv_va_hit_clr;
wire entry_clk_en;
wire [26:0] lsu_mmu_tlb_va;
wire pad_yy_icg_scan_en;
wire regs_utlb_clr;
wire tlboper_utlb_clr;
wire tlboper_utlb_inv_va_req;
wire utlb_clk;
wire utlb_entry_clk;
wire utlb_entry_clr;
wire [13:0] utlb_entry_flg;
wire utlb_entry_gating_clr;
wire utlb_entry_hit;
wire [2 :0] utlb_entry_pgs;
wire [27:0] utlb_entry_ppn;
wire utlb_entry_swp;
wire utlb_entry_swp_on;
wire utlb_entry_upd;
wire utlb_entry_vld;
wire [26:0] utlb_entry_vpn;
wire [13:0] utlb_fst_swp_flg;
wire [2 :0] utlb_fst_swp_pgs;
wire [27:0] utlb_fst_swp_ppn;
wire [26:0] utlb_fst_swp_vpn;
wire utlb_hit;
wire [26:0] utlb_req_vpn;
wire [13:0] utlb_upd_flg;
wire [2 :0] utlb_upd_pgs;
wire [27:0] utlb_upd_ppn;
wire [26:0] utlb_upd_vpn;
wire vpn0_hit;
wire vpn1_hit;
wire vpn2_hit;
// &Force("bus","lsu_mmu_tlb_va",26,0); @28
parameter VPN_WIDTH = 39-12; // VPN
parameter PPN_WIDTH = 40-12; // PPN
parameter FLG_WIDTH = 14; // Flags
parameter PGS_WIDTH = 3; // Page Size
parameter PTE_LEVEL = 3; // Page Table Label
//============================================================
// MicroTLB Entry
//============================================================
//------------------------------------------------------------
// 1. ASID field are not included in uTLB entry
// 2. Each Data uTLB entry always matches the ASID in the SATP
// register
// 3. The micro tlb entry layout is figured as following:
// =========================================
// | |72 46|45 43|42 15|14 0|
// |-------+-------+----------+-----+------+
// | Valid | VPN | PageSize | PFN | Flag |
// =========================================
//------------------------------------------------------------
// Gated Cell for utlb entry
assign entry_clk_en = utlb_entry_gating_clr
|| utlb_entry_upd
|| utlb_entry_swp;
// &Instance("gated_clk_cell", "x_iutlb_entry_gateclk"); @55
gated_clk_cell x_iutlb_entry_gateclk (
.clk_in (utlb_clk ),
.clk_out (utlb_entry_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (entry_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (utlb_clk ), @56
// .external_en(1'b0 ), @57
// .global_en (1'b1 ), @58
// .module_en (cp0_mmu_icg_en), @59
// .local_en (entry_clk_en ), @60
// .clk_out (utlb_entry_clk) @61
// ); @62
//------------------------------------------------------------
// Valid bit generating
//------------------------------------------------------------
assign utlb_entry_clr = regs_utlb_clr
|| tlboper_utlb_clr
|| ctc_inv_va_hit_clr;
assign utlb_entry_gating_clr = regs_utlb_clr
|| tlboper_utlb_clr
|| tlboper_utlb_inv_va_req;
assign ctc_inv_va_hit_clr = tlboper_utlb_inv_va_req
&& (lsu_mmu_tlb_va[7:0] == utlb_vpn[7:0]);
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
utlb_vld <= 1'b0;
else if(utlb_entry_clr)
utlb_vld <= 1'b0;
else if(utlb_entry_upd)
utlb_vld <= 1'b1;
else if(utlb_entry_swp)
utlb_vld <= utlb_entry_swp_on;
end
//------------------------------------------------------------
// VPN Information
//------------------------------------------------------------
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
utlb_vpn[VPN_WIDTH-1:0] <= {VPN_WIDTH{1'b0}};
else if(utlb_entry_upd)
utlb_vpn[VPN_WIDTH-1:0] <= utlb_upd_vpn[VPN_WIDTH-1:0];
else if(utlb_entry_swp)
utlb_vpn[VPN_WIDTH-1:0] <= utlb_fst_swp_vpn[VPN_WIDTH-1:0];
end
//------------------------------------------------------------
// PFN and Flag information
//------------------------------------------------------------
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
utlb_pgs[PGS_WIDTH-1:0] <= {PGS_WIDTH{1'b0}};
utlb_ppn[PPN_WIDTH-1:0] <= {PPN_WIDTH{1'b0}};
utlb_flg[FLG_WIDTH-1:0] <= {FLG_WIDTH{1'b0}};
end
else if(utlb_entry_upd)
begin
utlb_pgs[PGS_WIDTH-1:0] <= utlb_upd_pgs[PGS_WIDTH-1:0];
utlb_ppn[PPN_WIDTH-1:0] <= utlb_upd_ppn[PPN_WIDTH-1:0];
utlb_flg[FLG_WIDTH-1:0] <= utlb_upd_flg[FLG_WIDTH-1:0];
end
else if(utlb_entry_swp)
begin
utlb_pgs[PGS_WIDTH-1:0] <= utlb_fst_swp_pgs[PGS_WIDTH-1:0];
utlb_ppn[PPN_WIDTH-1:0] <= utlb_fst_swp_ppn[PPN_WIDTH-1:0];
utlb_flg[FLG_WIDTH-1:0] <= utlb_fst_swp_flg[FLG_WIDTH-1:0];
end
end
//------------------------------------------------------------
// Entry Hit
//------------------------------------------------------------
assign vpn2_hit = utlb_req_vpn[VPN_WIDTH-1:VPN_WIDTH-9]
== utlb_vpn[VPN_WIDTH-1:VPN_WIDTH-9];
assign vpn1_hit = utlb_req_vpn[VPN_WIDTH-1-9:VPN_WIDTH-2*9]
== utlb_vpn[VPN_WIDTH-1-9:VPN_WIDTH-2*9];
assign vpn0_hit = utlb_req_vpn[VPN_WIDTH-1-2*9:0]
== utlb_vpn[VPN_WIDTH-1-2*9:0];
assign utlb_hit = utlb_pgs[0] && vpn2_hit && vpn1_hit && vpn0_hit
|| utlb_pgs[1] && vpn2_hit && vpn1_hit
|| utlb_pgs[2] && vpn2_hit;
//------------------------------------------------------------
// Output
//------------------------------------------------------------
assign utlb_entry_vld = utlb_vld;
assign utlb_entry_hit = utlb_hit;
assign utlb_entry_vpn[VPN_WIDTH-1:0] = utlb_vpn[VPN_WIDTH-1:0];
assign utlb_entry_pgs[PGS_WIDTH-1:0] = utlb_pgs[PGS_WIDTH-1:0];
assign utlb_entry_ppn[PPN_WIDTH-1:0] = utlb_ppn[PPN_WIDTH-1:0];
assign utlb_entry_flg[FLG_WIDTH-1:0] = utlb_flg[FLG_WIDTH-1:0];
// &ModuleEnd; @156
endmodule |
module ct_mmu_jtlb_tag_array(
cp0_mmu_icg_en,
forever_cpuclk,
jtlb_tag_cen,
jtlb_tag_din,
jtlb_tag_dout,
jtlb_tag_idx,
jtlb_tag_wen,
pad_yy_icg_scan_en
);
// &Ports; @24
input cp0_mmu_icg_en;
input forever_cpuclk;
input jtlb_tag_cen;
input [195:0] jtlb_tag_din;
input [7 :0] jtlb_tag_idx;
input [4 :0] jtlb_tag_wen;
input pad_yy_icg_scan_en;
output [195:0] jtlb_tag_dout;
// &Regs; @25
// &Wires; @26
wire cp0_mmu_icg_en;
wire forever_cpuclk;
wire [195:0] jtlb_tag_bwen;
wire [195:0] jtlb_tag_bwen_b;
wire jtlb_tag_cen;
wire jtlb_tag_cen_b;
wire jtlb_tag_clk;
wire jtlb_tag_clk_en;
wire [195:0] jtlb_tag_din;
wire [195:0] jtlb_tag_dout;
wire jtlb_tag_gwen;
wire jtlb_tag_gwen_b;
wire [7 :0] jtlb_tag_idx;
wire [4 :0] jtlb_tag_wen;
wire pad_yy_icg_scan_en;
//==========================================================
// Gate Cell
//==========================================================
assign jtlb_tag_clk_en = jtlb_tag_cen;
// &Instance("gated_clk_cell", "x_jtlb_tag_gateclk"); @33
gated_clk_cell x_jtlb_tag_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (jtlb_tag_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (jtlb_tag_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @34
// .external_en(1'b0 ), @35
// .global_en (1'b1 ), @36
// .module_en (cp0_mmu_icg_en ), @37
// .local_en (jtlb_tag_clk_en ), @38
// .clk_out (jtlb_tag_clk ) @39
// ); @40
assign jtlb_tag_gwen = |jtlb_tag_wen[4:0];
assign jtlb_tag_bwen[195:0] = {
{4 {jtlb_tag_wen[4]}}, //fifo
{48{jtlb_tag_wen[3]}}, //way3
{48{jtlb_tag_wen[2]}}, //way2
{48{jtlb_tag_wen[1]}}, //way1
{48{jtlb_tag_wen[0]}} //way0
};
assign jtlb_tag_cen_b = !jtlb_tag_cen;
assign jtlb_tag_gwen_b = !jtlb_tag_gwen;
assign jtlb_tag_bwen_b[195:0] = ~jtlb_tag_bwen[195:0];
// &Instance("ct_spsram_256x204","x_ct_spsram_256x204"); @66
// &Connect( @67
// .CLK (jtlb_tag_clk ), @68
// .CEN (jtlb_tag_cen_b ), @69
// .GWEN (jtlb_tag_gwen_b ), @70
// .WEN (jtlb_tag_bwen_b ), @71
// .A (jtlb_tag_idx[7:0]), @72
// .D (jtlb_tag_din ), @73
// .Q (jtlb_tag_dout ) @74
// ); @75
// &Instance("ct_spsram_512x204","x_ct_spsram_512x204"); @79
// &Connect( @80
// .CLK (jtlb_tag_clk ), @81
// .CEN (jtlb_tag_cen_b ), @82
// .GWEN (jtlb_tag_gwen_b ), @83
// .WEN (jtlb_tag_bwen_b ), @84
// .A (jtlb_tag_idx[8:0]), @85
// .D (jtlb_tag_din ), @86
// .Q (jtlb_tag_dout ) @87
// ); @88
// &Instance("ct_spsram_256x196","x_ct_spsram_256x196"); @94
ct_spsram_256x196 x_ct_spsram_256x196 (
.A (jtlb_tag_idx[7:0]),
.CEN (jtlb_tag_cen_b ),
.CLK (jtlb_tag_clk ),
.D (jtlb_tag_din ),
.GWEN (jtlb_tag_gwen_b ),
.Q (jtlb_tag_dout ),
.WEN (jtlb_tag_bwen_b )
);
// &Connect( @95
// .CLK (jtlb_tag_clk ), @96
// .CEN (jtlb_tag_cen_b ), @97
// .GWEN (jtlb_tag_gwen_b ), @98
// .WEN (jtlb_tag_bwen_b ), @99
// .A (jtlb_tag_idx[7:0]), @100
// .D (jtlb_tag_din ), @101
// .Q (jtlb_tag_dout ) @102
// ); @103
// &Instance("ct_spsram_512x196","x_ct_spsram_512x196"); @107
// &Connect( @108
// .CLK (jtlb_tag_clk ), @109
// .CEN (jtlb_tag_cen_b ), @110
// .GWEN (jtlb_tag_gwen_b ), @111
// .WEN (jtlb_tag_bwen_b ), @112
// .A (jtlb_tag_idx[8:0]), @113
// .D (jtlb_tag_din ), @114
// .Q (jtlb_tag_dout ) @115
// ); @116
// &ModuleEnd; @121
endmodule |
module ct_mmu_regs(
cp0_mmu_cskyee,
cp0_mmu_icg_en,
cp0_mmu_mpp,
cp0_mmu_mprv,
cp0_mmu_reg_num,
cp0_mmu_satp_sel,
cp0_mmu_wdata,
cp0_mmu_wreg,
cp0_yy_priv_mode,
cpurst_b,
forever_cpuclk,
jtlb_regs_hit,
jtlb_regs_hit_mult,
jtlb_regs_tlbp_hit_index,
jtlb_tlbr_asid,
jtlb_tlbr_flg,
jtlb_tlbr_g,
jtlb_tlbr_pgs,
jtlb_tlbr_ppn,
jtlb_tlbr_vpn,
mmu_cp0_cmplt,
mmu_cp0_data,
mmu_cp0_satp_data,
mmu_lsu_mmu_en,
mmu_xx_mmu_en,
pad_yy_icg_scan_en,
regs_jtlb_cur_asid,
regs_jtlb_cur_flg,
regs_jtlb_cur_g,
regs_jtlb_cur_ppn,
regs_mmu_en,
regs_ptw_cur_asid,
regs_ptw_satp_ppn,
regs_tlboper_cur_asid,
regs_tlboper_cur_pgs,
regs_tlboper_cur_vpn,
regs_tlboper_inv_asid,
regs_tlboper_invall,
regs_tlboper_invasid,
regs_tlboper_mir,
regs_tlboper_tlbp,
regs_tlboper_tlbr,
regs_tlboper_tlbwi,
regs_tlboper_tlbwr,
regs_utlb_clr,
rtu_mmu_bad_vpn,
rtu_mmu_expt_vld,
tlboper_regs_cmplt,
tlboper_regs_tlbp_cmplt,
tlboper_regs_tlbr_cmplt
);
// &Ports; @24
input cp0_mmu_cskyee;
input cp0_mmu_icg_en;
input [1 :0] cp0_mmu_mpp;
input cp0_mmu_mprv;
input [1 :0] cp0_mmu_reg_num;
input cp0_mmu_satp_sel;
input [63:0] cp0_mmu_wdata;
input cp0_mmu_wreg;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input forever_cpuclk;
input jtlb_regs_hit;
input jtlb_regs_hit_mult;
input [10:0] jtlb_regs_tlbp_hit_index;
input [15:0] jtlb_tlbr_asid;
input [13:0] jtlb_tlbr_flg;
input jtlb_tlbr_g;
input [2 :0] jtlb_tlbr_pgs;
input [27:0] jtlb_tlbr_ppn;
input [26:0] jtlb_tlbr_vpn;
input pad_yy_icg_scan_en;
input [26:0] rtu_mmu_bad_vpn;
input rtu_mmu_expt_vld;
input tlboper_regs_cmplt;
input tlboper_regs_tlbp_cmplt;
input tlboper_regs_tlbr_cmplt;
output mmu_cp0_cmplt;
output [63:0] mmu_cp0_data;
output [63:0] mmu_cp0_satp_data;
output mmu_lsu_mmu_en;
output mmu_xx_mmu_en;
output [15:0] regs_jtlb_cur_asid;
output [13:0] regs_jtlb_cur_flg;
output regs_jtlb_cur_g;
output [27:0] regs_jtlb_cur_ppn;
output regs_mmu_en;
output [15:0] regs_ptw_cur_asid;
output [27:0] regs_ptw_satp_ppn;
output [15:0] regs_tlboper_cur_asid;
output [2 :0] regs_tlboper_cur_pgs;
output [26:0] regs_tlboper_cur_vpn;
output [15:0] regs_tlboper_inv_asid;
output regs_tlboper_invall;
output regs_tlboper_invasid;
output [11:0] regs_tlboper_mir;
output regs_tlboper_tlbp;
output regs_tlboper_tlbr;
output regs_tlboper_tlbwi;
output regs_tlboper_tlbwr;
output regs_utlb_clr;
// &Regs; @25
reg [15:0] mcir_asid;
reg mcir_invall;
reg mcir_invasid;
reg mcir_no_op;
reg mcir_tlbp;
reg mcir_tlbr;
reg mcir_tlbwi;
reg mcir_tlbwr;
reg [15:0] meh_asid;
reg [2 :0] meh_pgs;
reg [26:0] meh_vpn;
reg mel_access;
reg mel_b;
reg mel_c;
reg mel_dirty;
reg mel_exe;
reg mel_global;
reg [27:0] mel_ppn;
reg mel_read;
reg [1 :0] mel_rsw;
reg mel_sec;
reg mel_sh;
reg mel_so;
reg mel_user;
reg mel_vld;
reg mel_write;
reg [11:0] mir_index;
reg mir_probe;
reg mir_tlbp_tfatal;
reg [63:0] mmu_cp0_data;
reg [15:0] satp_asid;
reg [3 :0] satp_mode;
reg [27:0] satp_ppn;
// &Wires; @26
wire cp0_mmu_cskyee;
wire cp0_mmu_icg_en;
wire [1 :0] cp0_mmu_mpp;
wire cp0_mmu_mprv;
wire [1 :0] cp0_mmu_reg_num;
wire cp0_mmu_satp_sel;
wire [63:0] cp0_mmu_wdata;
wire cp0_mmu_wreg;
wire [1 :0] cp0_priv_mode;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire forever_cpuclk;
wire jtlb_regs_hit;
wire jtlb_regs_hit_mult;
wire [10:0] jtlb_regs_tlbp_hit_index;
wire [15:0] jtlb_tlbr_asid;
wire [13:0] jtlb_tlbr_flg;
wire jtlb_tlbr_g;
wire [2 :0] jtlb_tlbr_pgs;
wire [27:0] jtlb_tlbr_ppn;
wire [26:0] jtlb_tlbr_vpn;
wire [63:0] mcir_data;
wire mcir_data_no_op;
wire mcir_write_en;
wire [63:0] meh_data;
wire meh_write_en;
wire [63:0] mel_data;
wire mel_write_en;
wire [63:0] mir_data;
wire mir_write_en;
wire mmu_cp0_cmplt;
wire [63:0] mmu_cp0_satp_data;
wire mmu_lsu_mmu_en;
wire mmu_regs_clk;
wire mmu_regs_clk_en;
wire mmu_xx_mmu_en;
wire pad_yy_icg_scan_en;
wire [15:0] regs_jtlb_cur_asid;
wire [13:0] regs_jtlb_cur_flg;
wire regs_jtlb_cur_g;
wire [27:0] regs_jtlb_cur_ppn;
wire regs_mmu_en;
wire [15:0] regs_ptw_cur_asid;
wire [27:0] regs_ptw_satp_ppn;
wire [15:0] regs_tlboper_cur_asid;
wire [2 :0] regs_tlboper_cur_pgs;
wire [26:0] regs_tlboper_cur_vpn;
wire [15:0] regs_tlboper_inv_asid;
wire regs_tlboper_invall;
wire regs_tlboper_invasid;
wire [11:0] regs_tlboper_mir;
wire regs_tlboper_tlbp;
wire regs_tlboper_tlbr;
wire regs_tlboper_tlbwi;
wire regs_tlboper_tlbwr;
wire regs_utlb_clr;
wire [26:0] rtu_mmu_bad_vpn;
wire rtu_mmu_expt_vld;
wire [63:0] satp_data;
wire satp_write_en;
wire tlboper_regs_cmplt;
wire tlboper_regs_tlbp_cmplt;
wire tlboper_regs_tlbr_cmplt;
wire wdata_invall;
wire wdata_invasid;
wire wdata_tlbp;
wire wdata_tlbr;
wire wdata_tlbwi;
wire wdata_tlbwr;
parameter VPN_WIDTH = 39-12; // VPN
parameter PPN_WIDTH = 40-12; // PPN
parameter FLG_WIDTH = 14; // Flags
parameter PGS_WIDTH = 3; // Page Size
parameter ASID_WIDTH = 16; // Flags
//==============================================================================
// Flush uTLB when CR oper
//==============================================================================
assign regs_utlb_clr = satp_write_en;
//==============================================================================
// Gate Cell
//==============================================================================
assign mmu_regs_clk_en = cp0_mmu_wreg
|| satp_write_en
|| rtu_mmu_expt_vld
|| tlboper_regs_cmplt
|| mcir_no_op;
// &Instance("gated_clk_cell", "x_mmu_regs_gateclk"); @47
gated_clk_cell x_mmu_regs_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (mmu_regs_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (mmu_regs_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @48
// .external_en(1'b0 ), @49
// .global_en (1'b1 ), @50
// .module_en (cp0_mmu_icg_en ), @51
// .local_en (mmu_regs_clk_en ), @52
// .clk_out (mmu_regs_clk ) @53
// ); @54
//==============================================================================
// MMU Regs Definition
//==============================================================================
parameter MIR_NUM = 2'd0;
parameter MEL_NUM = 2'd1;
parameter MEH_NUM = 2'd2;
parameter MCIR_NUM = 2'd3;
//----------------------------------------------------------
// Generate Write Enable
//----------------------------------------------------------
assign mir_write_en = (cp0_mmu_reg_num[1:0] == MIR_NUM) && cp0_mmu_wreg;
assign mel_write_en = (cp0_mmu_reg_num[1:0] == MEL_NUM) && cp0_mmu_wreg;
assign meh_write_en = (cp0_mmu_reg_num[1:0] == MEH_NUM) && cp0_mmu_wreg;
assign mcir_write_en = (cp0_mmu_reg_num[1:0] == MCIR_NUM) && cp0_mmu_wreg;
assign satp_write_en = cp0_mmu_satp_sel;
//==============================================================================
// Implement MMU Registers
//==============================================================================
//==========================================================
// MIR register
//==========================================================
// the definiton for MIR register is listed as follows
// ========================================================
// | 63 32 |
// +------------------------------------------------------+
// | Reserved |
// ========================================================
// ========================================================
// | 31 | 30 |29 12|11 0|
// +------+-------------+-----------------+---------------+
// | P | tlbp_tfatal | Reserved | Index |
// ========================================================
// P --> tlbp match flag
// 1'b0: match success
// 1'b1: match failure
//
// tlbp_tfatal --> 1'b0: none tlb probe tfatal exception
// --> 1'b1: tlb probe tfatal exception occurs
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
mir_probe <= 1'b0;
mir_tlbp_tfatal <= 1'b0;
end
else if(tlboper_regs_tlbp_cmplt)
begin
mir_probe <= !jtlb_regs_hit;
mir_tlbp_tfatal <= jtlb_regs_hit_mult;
end
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
mir_index[11:0] <= 12'b0;
end
else if(mir_write_en)
begin
mir_index[11:0] <= cp0_mmu_wdata[11:0];
end
else if(tlboper_regs_tlbp_cmplt && jtlb_regs_hit)
begin
mir_index[11:0] <= {1'b0, jtlb_regs_tlbp_hit_index[10:0]}; // TLBP probe is successful
end
end
assign mir_data[63:0] = {32'b0, mir_probe, mir_tlbp_tfatal, 18'b0, mir_index[11:0]};
//==========================================================
// MEL register
//==========================================================
// the definiton for MEL register is listed as follows
// =======================================================
// | 63 |62 |61 | 60 |59 | 58 38 |37 32|
// +----+---+---+----+---+----------------------+--------+
// | So | C | B | Sh |Sec| Reserved | PPN |
// =======================================================
// =======================================================
// |31 10|9 8| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
// +---------------------------------+---+---+---+---+---+
// | PPN | RSW | D | A | G | U | X | W | R | V |
// =======================================================
//
// PFN --> the physical frame page numeber mapped to VPN
// So --> 1'b1: the current page is strong order
// 1'b0: the current page is not strong order
// C --> 1'b1: the current page is cacheable
// 1'b0: the current page is uncacheable
// B --> 1'b1: the current page is bufferable
// 1'b0: the current page is unbufferable
// SH --> 1'b1: the current page is shareable
// 1'b0: the current page is non-shareable
// Sec --> 1'b1: the current page is security sensitive
// 1'b0: the current page is not security sensitive
// D --> 1'b1: the current page is writable
// 1'b0: the current page cannot be written to
// A --> 1'b1: the current page is accessable
// 1'b0: the current page cannot be accessed to
// G --> 1'b1: all process share Mem
// 1'b0: ASID will be compared in generating jtlb entry hit singal
// U --> 1'b1: the current page can be accessed by user mode
// 1'b0: the current page cannot be accessed by user mode
// X --> 1'b1: the current page is executable
// 1'b0: the current page is not executable
// W --> 1'b1: the current page is writeable
// 1'b0: the current page is not writeable
// R --> 1'b1: the current page is readable
// 1'b0: the current page is not readable
// V --> 1'b1: the current page is valid
// 1'b0: the current page is invalid
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
mel_ppn[PPN_WIDTH-1:0] <= {PPN_WIDTH{1'b0}};
mel_so <= 1'b0;
mel_c <= 1'b0;
mel_b <= 1'b0;
mel_sh <= 1'b0;
mel_sec <= 1'b0;
mel_rsw[1:0] <= 2'b0;
mel_dirty <= 1'b0;
mel_access <= 1'b0;
mel_global <= 1'b0;
mel_user <= 1'b0;
mel_exe <= 1'b0;
mel_write <= 1'b0;
mel_read <= 1'b0;
mel_vld <= 1'b0;
end
else if(mel_write_en)
begin
mel_ppn[PPN_WIDTH-1:0] <= cp0_mmu_wdata[PPN_WIDTH+9:10];
mel_so <= cp0_mmu_wdata[63];
mel_c <= cp0_mmu_wdata[62];
mel_b <= cp0_mmu_wdata[61];
mel_sh <= cp0_mmu_wdata[60];
mel_sec <= cp0_mmu_wdata[59];
mel_rsw[1:0] <= cp0_mmu_wdata[9:8];
mel_dirty <= cp0_mmu_wdata[7];
mel_access <= cp0_mmu_wdata[6];
mel_global <= cp0_mmu_wdata[5];
mel_user <= cp0_mmu_wdata[4];
mel_exe <= cp0_mmu_wdata[3];
mel_write <= cp0_mmu_wdata[2];
mel_read <= cp0_mmu_wdata[1];
mel_vld <= cp0_mmu_wdata[0];
end
else if(tlboper_regs_tlbr_cmplt)
begin
mel_ppn[PPN_WIDTH-1:0] <= jtlb_tlbr_ppn[PPN_WIDTH-1:0];
mel_so <= jtlb_tlbr_flg[13];
mel_c <= jtlb_tlbr_flg[12];
mel_b <= jtlb_tlbr_flg[11];
mel_sh <= jtlb_tlbr_flg[10];
mel_sec <= jtlb_tlbr_flg[9];
mel_rsw[1:0] <= jtlb_tlbr_flg[8:7];
mel_dirty <= jtlb_tlbr_flg[6];
mel_access <= jtlb_tlbr_flg[5];
mel_global <= jtlb_tlbr_g;
mel_user <= jtlb_tlbr_flg[4];
mel_exe <= jtlb_tlbr_flg[3];
mel_write <= jtlb_tlbr_flg[2];
mel_read <= jtlb_tlbr_flg[1];
mel_vld <= jtlb_tlbr_flg[0];
end
end
assign mel_data[63:0] = {mel_so,mel_c,mel_b,mel_sh,mel_sec,21'b0,
mel_ppn[PPN_WIDTH-1:0],mel_rsw[1:0],mel_dirty,
mel_access,mel_global,mel_user,mel_exe,mel_write,
mel_read,mel_vld};
//==========================================================
// MEH register
//==========================================================
// the definiton for MEH register is listed as follows
// =======================================================
// |63 46|45 19|18 16|15 0|
// +------------------------+--------+-------------------+
// | Reserved | VPN |PageSize| ASID |
// =======================================================
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
meh_vpn[VPN_WIDTH-1:0] <= {VPN_WIDTH{1'b0}};
meh_pgs[PGS_WIDTH-1:0] <= {PGS_WIDTH{1'b0}};
meh_asid[ASID_WIDTH-1:0] <= {ASID_WIDTH{1'b0}};
end
else if(meh_write_en)
begin
meh_vpn[VPN_WIDTH-1:0] <= cp0_mmu_wdata[45:19];
meh_pgs[PGS_WIDTH-1:0] <= cp0_mmu_wdata[18:16];
meh_asid[ASID_WIDTH-1:0] <= cp0_mmu_wdata[ASID_WIDTH-1:0];
end
else if(rtu_mmu_expt_vld) // if TLB miss/inv/mod expt occurs, record bad VPN
begin
meh_vpn[VPN_WIDTH-1:0] <= rtu_mmu_bad_vpn[VPN_WIDTH-1:0];
meh_pgs[PGS_WIDTH-1:0] <= meh_pgs[PGS_WIDTH-1:0];
meh_asid[ASID_WIDTH-1:0] <= meh_asid[ASID_WIDTH-1:0];
end
else if(tlboper_regs_tlbr_cmplt)
begin
meh_vpn[VPN_WIDTH-1:0] <= jtlb_tlbr_vpn[VPN_WIDTH-1:0];
meh_pgs[PGS_WIDTH-1:0] <= jtlb_tlbr_pgs[PGS_WIDTH-1:0];
meh_asid[ASID_WIDTH-1:0] <= jtlb_tlbr_asid[ASID_WIDTH-1:0];
end
end
assign meh_data[63:0] = {18'b0, meh_vpn[VPN_WIDTH-1:0], meh_pgs[PGS_WIDTH-1:0],
meh_asid[ASID_WIDTH-1:0]};
//==========================================================
// MCIR register
//==========================================================
// the definiton for MCIR register is listed as follows
// ========================================================
// | 63 32 |
// +------------------------------------------------------+
// | Reserved |
// ========================================================
// ===================================================================
// | 31 | 30 | 29 | 28 | 27 | 26 |25 12|15 0 |
// +------+------+-------+-------+----------+--------+--------+------+
// | tlbp | tlbr | tlbwi | tlbwr | inv asid | invall |reserved| ASID |
// ===================================================================
assign wdata_invall = cp0_mmu_wdata[26] && cp0_mmu_cskyee;
assign wdata_invasid = !cp0_mmu_wdata[26] && cp0_mmu_wdata[27] && cp0_mmu_cskyee;
assign wdata_tlbp = !cp0_mmu_wdata[26] && !cp0_mmu_wdata[27] && cp0_mmu_cskyee
&& cp0_mmu_wdata[31];
assign wdata_tlbwi = !cp0_mmu_wdata[26] && !cp0_mmu_wdata[27] && cp0_mmu_cskyee
&&!cp0_mmu_wdata[31] && cp0_mmu_wdata[29];
assign wdata_tlbwr = !cp0_mmu_wdata[26] && !cp0_mmu_wdata[27] && cp0_mmu_cskyee
&&!cp0_mmu_wdata[31] && !cp0_mmu_wdata[29]
&& cp0_mmu_wdata[28];
assign wdata_tlbr = !cp0_mmu_wdata[26] && !cp0_mmu_wdata[27] && cp0_mmu_cskyee
&&!cp0_mmu_wdata[31] && !cp0_mmu_wdata[29]
&&!cp0_mmu_wdata[28] && cp0_mmu_wdata[30];
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_invall <= 1'b0;
else if(mcir_write_en && wdata_invall)
mcir_invall <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_invall <= 1'b0;
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_invasid <= 1'b0;
else if(mcir_write_en && wdata_invasid)
mcir_invasid <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_invasid <= 1'b0;
end
//always @(posedge mmu_regs_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// mcir_invidx <= 1'b0;
// else if(mcir_write_en && cp0_mmu_wdata[25])
// mcir_invidx <= 1'b1;
// else if(tlboper_regs_cmplt)
// mcir_invidx <= 1'b0;
//end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_tlbp <= 1'b0;
else if(mcir_write_en && wdata_tlbp)
mcir_tlbp <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_tlbp <= 1'b0;
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_tlbwi <= 1'b0;
else if(mcir_write_en && wdata_tlbwi)
mcir_tlbwi <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_tlbwi <= 1'b0;
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_tlbwr <= 1'b0;
else if(mcir_write_en && wdata_tlbwr)
mcir_tlbwr <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_tlbwr <= 1'b0;
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_tlbr <= 1'b0;
else if(mcir_write_en && wdata_tlbr)
mcir_tlbr <= 1'b1;
else if(tlboper_regs_cmplt)
mcir_tlbr <= 1'b0;
end
// The recycled ASID field is updated for TLBINV instruction
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
mcir_asid[ASID_WIDTH-1:0] <= {ASID_WIDTH{1'b0}};
end
else if(mcir_write_en)
begin
mcir_asid[ASID_WIDTH-1:0] <= cp0_mmu_wdata[ASID_WIDTH-1:0];
end
end
assign mcir_data[63:0] = {32'b0, mcir_tlbp, mcir_tlbr, mcir_tlbwi,
mcir_tlbwr, mcir_invasid, mcir_invall,
10'b0, mcir_asid[ASID_WIDTH-1:0]};
assign mcir_data_no_op = (cp0_mmu_wdata[31:26] == 6'b0);
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mcir_no_op <= 1'b0;
else if(mcir_write_en && mcir_data_no_op)
mcir_no_op <= 1'b1;
else if(mcir_no_op)
mcir_no_op <= 1'b0;
end
//==========================================================
// STAP register
//==========================================================
// the definiton for STAP register is listed as follows
// =======================================================
// |63 60|59 44|43 28|27 0|
// +------+------------+---------------------------------+
// | Mode | ASID | Reserved | PPN |
// =======================================================
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
satp_mode[3:0] <= {4{1'b0}};
else if(satp_write_en && cp0_mmu_wdata[62:60] == 3'b0)
satp_mode[3:0] <= {cp0_mmu_wdata[63],3'b0};
end
always @(posedge mmu_regs_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
satp_asid[ASID_WIDTH-1:0] <= {ASID_WIDTH{1'b0}};
satp_ppn[PPN_WIDTH-1:0] <= {PPN_WIDTH{1'b0}};
end
else if(satp_write_en)
begin
satp_asid[ASID_WIDTH-1:0] <= cp0_mmu_wdata[59:44];
satp_ppn[PPN_WIDTH-1:0] <= cp0_mmu_wdata[PPN_WIDTH-1:0];
end
end
assign satp_data[63:0] = {satp_mode[3:0],satp_asid[ASID_WIDTH-1:0],
16'b0,satp_ppn[PPN_WIDTH-1:0]};
//==========================================================
// CP0 interface
//==========================================================
assign mmu_cp0_cmplt = tlboper_regs_cmplt || mcir_no_op;
//--------------------------------------
// Provide MMU register read data bus to CP15 module
//--------------------------------------
// &CombBeg; @453
always @( mcir_data[63:0]
or mel_data[63:0]
or meh_data[63:0]
or mir_data[63:0]
or cp0_mmu_reg_num[1:0])
begin
case(cp0_mmu_reg_num[1:0])
MIR_NUM : mmu_cp0_data[63:0] = mir_data[63:0];
MEL_NUM : mmu_cp0_data[63:0] = mel_data[63:0];
MEH_NUM : mmu_cp0_data[63:0] = meh_data[63:0];
MCIR_NUM : mmu_cp0_data[63:0] = mcir_data[63:0];
default : mmu_cp0_data[63:0] = 64'b0;
endcase
// &CombEnd; @461
end
assign mmu_cp0_satp_data[63:0] = satp_data[63:0];
//==============================================================================
// CP0 request to TLBoper
//==============================================================================
//assign regs_tlboper_invidx = mcir_invidx;
assign regs_tlboper_invall = mcir_invall;
assign regs_tlboper_invasid = mcir_invasid;
assign regs_tlboper_tlbwr = mcir_tlbwr;
assign regs_tlboper_tlbwi = mcir_tlbwi;
assign regs_tlboper_tlbr = mcir_tlbr;
assign regs_tlboper_tlbp = mcir_tlbp;
assign regs_tlboper_inv_asid[ASID_WIDTH-1:0] = mcir_asid[ASID_WIDTH-1:0];
assign regs_tlboper_mir[11:0] = mir_index[11:0];
assign regs_tlboper_cur_vpn[VPN_WIDTH-1:0] = meh_vpn[VPN_WIDTH-1:0];
assign regs_tlboper_cur_pgs[PGS_WIDTH-1:0] = meh_pgs[PGS_WIDTH-1:0];
assign regs_tlboper_cur_asid[ASID_WIDTH-1:0] = meh_asid[ASID_WIDTH-1:0];
assign regs_mmu_en = satp_mode[3:0] == 4'b1000;
assign cp0_priv_mode[1:0] = cp0_mmu_mprv ? cp0_mmu_mpp[1:0]
: cp0_yy_priv_mode[1:0];
assign mmu_lsu_mmu_en = satp_mode[3:0] == 4'b1000
&& cp0_priv_mode[1:0] != 2'b11;
assign mmu_xx_mmu_en = satp_mode[3:0] == 4'b1000
&& cp0_yy_priv_mode[1:0] != 2'b11;
assign regs_ptw_satp_ppn[PPN_WIDTH-1:0] = satp_ppn[PPN_WIDTH-1:0];
assign regs_ptw_cur_asid[ASID_WIDTH-1:0] = satp_asid[ASID_WIDTH-1:0];
// for asid hit judgement
assign regs_jtlb_cur_asid[ASID_WIDTH-1:0] = satp_asid[ASID_WIDTH-1:0];
//used for jtlb data array wen
assign regs_jtlb_cur_ppn[PPN_WIDTH-1:0] = mel_ppn[PPN_WIDTH-1:0];
assign regs_jtlb_cur_flg[FLG_WIDTH-1:0] = {mel_data[63:59], mel_data[9:6], mel_data[4:0]};
assign regs_jtlb_cur_g = mel_global;
// &ModuleEnd; @503
endmodule |
module ct_mmu_jtlb_data_array(
cp0_mmu_icg_en,
forever_cpuclk,
jtlb_data_cen0,
jtlb_data_cen1,
jtlb_data_din,
jtlb_data_dout0,
jtlb_data_dout1,
jtlb_data_idx,
jtlb_data_wen,
pad_yy_icg_scan_en
);
// &Ports; @24
input cp0_mmu_icg_en;
input forever_cpuclk;
input jtlb_data_cen0;
input jtlb_data_cen1;
input [83:0] jtlb_data_din;
input [7 :0] jtlb_data_idx;
input [3 :0] jtlb_data_wen;
input pad_yy_icg_scan_en;
output [83:0] jtlb_data_dout0;
output [83:0] jtlb_data_dout1;
// &Regs; @25
// &Wires; @26
wire cp0_mmu_icg_en;
wire forever_cpuclk;
wire [83:0] jtlb_data_bwen0;
wire [83:0] jtlb_data_bwen0_b;
wire [83:0] jtlb_data_bwen1;
wire [83:0] jtlb_data_bwen1_b;
wire jtlb_data_cen0;
wire jtlb_data_cen0_b;
wire jtlb_data_cen1;
wire jtlb_data_cen1_b;
wire jtlb_data_clk;
wire jtlb_data_clk_en;
wire [83:0] jtlb_data_din;
wire [83:0] jtlb_data_dout0;
wire [83:0] jtlb_data_dout1;
wire jtlb_data_gwen0;
wire jtlb_data_gwen0_b;
wire jtlb_data_gwen1;
wire jtlb_data_gwen1_b;
wire [7 :0] jtlb_data_idx;
wire [3 :0] jtlb_data_wen;
wire pad_yy_icg_scan_en;
//==========================================================
// Gate Cell
//==========================================================
assign jtlb_data_clk_en = jtlb_data_cen1 || jtlb_data_cen0;
// &Instance("gated_clk_cell", "x_jtlb_data_gateclk"); @33
gated_clk_cell x_jtlb_data_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (jtlb_data_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (jtlb_data_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @34
// .external_en(1'b0 ), @35
// .global_en (1'b1 ), @36
// .module_en (cp0_mmu_icg_en ), @37
// .local_en (jtlb_data_clk_en), @38
// .clk_out (jtlb_data_clk ) @39
// ); @40
assign jtlb_data_gwen1 = |jtlb_data_wen[3:2];
assign jtlb_data_bwen1[83:0] = {
{42{jtlb_data_wen[3]}},
{42{jtlb_data_wen[2]}}
};
assign jtlb_data_gwen0 = |jtlb_data_wen[1:0];
assign jtlb_data_bwen0[83:0] = {
{42{jtlb_data_wen[1]}},
{42{jtlb_data_wen[0]}}
};
assign jtlb_data_cen1_b = !jtlb_data_cen1;
assign jtlb_data_cen0_b = !jtlb_data_cen0;
assign jtlb_data_gwen1_b = !jtlb_data_gwen1;
assign jtlb_data_gwen0_b = !jtlb_data_gwen0;
assign jtlb_data_bwen1_b[83:0] = ~jtlb_data_bwen1[83:0];
assign jtlb_data_bwen0_b[83:0] = ~jtlb_data_bwen0[83:0];
// &Instance("ct_spsram_256x88","x_ct_spsram_256x88_bank1"); @80
// &Connect( @81
// .CLK (jtlb_data_clk ), @82
// .CEN (jtlb_data_cen1_b ), @83
// .GWEN (jtlb_data_gwen1_b ), @84
// .WEN (jtlb_data_bwen1_b ), @85
// .A (jtlb_data_idx[7:0]), @86
// .D (jtlb_data_din ), @87
// .Q (jtlb_data_dout1 ) @88
// ); @89
// &Instance("ct_spsram_256x88","x_ct_spsram_256x88_bank0"); @91
// &Connect( @92
// .CLK (jtlb_data_clk ), @93
// .CEN (jtlb_data_cen0_b ), @94
// .GWEN (jtlb_data_gwen0_b ), @95
// .WEN (jtlb_data_bwen0_b ), @96
// .A (jtlb_data_idx[7:0]), @97
// .D (jtlb_data_din ), @98
// .Q (jtlb_data_dout0 ) @99
// ); @100
// &Instance("ct_spsram_512x88","x_ct_spsram_512x88_bank1"); @105
// &Connect( @106
// .CLK (jtlb_data_clk ), @107
// .CEN (jtlb_data_cen1_b ), @108
// .GWEN (jtlb_data_gwen1_b ), @109
// .WEN (jtlb_data_bwen1_b ), @110
// .A (jtlb_data_idx[8:0]), @111
// .D (jtlb_data_din ), @112
// .Q (jtlb_data_dout1 ) @113
// ); @114
// &Instance("ct_spsram_512x88","x_ct_spsram_512x88_bank0"); @116
// &Connect( @117
// .CLK (jtlb_data_clk ), @118
// .CEN (jtlb_data_cen0_b ), @119
// .GWEN (jtlb_data_gwen0_b ), @120
// .WEN (jtlb_data_bwen0_b ), @121
// .A (jtlb_data_idx[8:0]), @122
// .D (jtlb_data_din ), @123
// .Q (jtlb_data_dout0 ) @124
// ); @125
// &Instance("ct_spsram_256x84","x_ct_spsram_256x84_bank1"); @131
ct_spsram_256x84 x_ct_spsram_256x84_bank1 (
.A (jtlb_data_idx[7:0]),
.CEN (jtlb_data_cen1_b ),
.CLK (jtlb_data_clk ),
.D (jtlb_data_din ),
.GWEN (jtlb_data_gwen1_b ),
.Q (jtlb_data_dout1 ),
.WEN (jtlb_data_bwen1_b )
);
// &Connect( @132
// .CLK (jtlb_data_clk ), @133
// .CEN (jtlb_data_cen1_b ), @134
// .GWEN (jtlb_data_gwen1_b ), @135
// .WEN (jtlb_data_bwen1_b ), @136
// .A (jtlb_data_idx[7:0]), @137
// .D (jtlb_data_din ), @138
// .Q (jtlb_data_dout1 ) @139
// ); @140
// &Instance("ct_spsram_256x84","x_ct_spsram_256x84_bank0"); @142
ct_spsram_256x84 x_ct_spsram_256x84_bank0 (
.A (jtlb_data_idx[7:0]),
.CEN (jtlb_data_cen0_b ),
.CLK (jtlb_data_clk ),
.D (jtlb_data_din ),
.GWEN (jtlb_data_gwen0_b ),
.Q (jtlb_data_dout0 ),
.WEN (jtlb_data_bwen0_b )
);
// &Connect( @143
// .CLK (jtlb_data_clk ), @144
// .CEN (jtlb_data_cen0_b ), @145
// .GWEN (jtlb_data_gwen0_b ), @146
// .WEN (jtlb_data_bwen0_b ), @147
// .A (jtlb_data_idx[7:0]), @148
// .D (jtlb_data_din ), @149
// .Q (jtlb_data_dout0 ) @150
// ); @151
// &Instance("ct_spsram_512x84","x_ct_spsram_512x84_bank1"); @155
// &Connect( @156
// .CLK (jtlb_data_clk ), @157
// .CEN (jtlb_data_cen1_b ), @158
// .GWEN (jtlb_data_gwen1_b ), @159
// .WEN (jtlb_data_bwen1_b ), @160
// .A (jtlb_data_idx[8:0]), @161
// .D (jtlb_data_din ), @162
// .Q (jtlb_data_dout1 ) @163
// ); @164
// &Instance("ct_spsram_512x84","x_ct_spsram_512x84_bank0"); @166
// &Connect( @167
// .CLK (jtlb_data_clk ), @168
// .CEN (jtlb_data_cen0_b ), @169
// .GWEN (jtlb_data_gwen0_b ), @170
// .WEN (jtlb_data_bwen0_b ), @171
// .A (jtlb_data_idx[8:0]), @172
// .D (jtlb_data_din ), @173
// .Q (jtlb_data_dout0 ) @174
// ); @175
// &ModuleEnd; @180
endmodule |
module ct_mmu_dplru(
cp0_mmu_icg_en,
cpurst_b,
entry0_vld,
entry10_vld,
entry11_vld,
entry12_vld,
entry13_vld,
entry14_vld,
entry15_vld,
entry1_vld,
entry2_vld,
entry3_vld,
entry4_vld,
entry5_vld,
entry6_vld,
entry7_vld,
entry8_vld,
entry9_vld,
forever_cpuclk,
pad_yy_icg_scan_en,
plru_dutlb_ref_num,
utlb_plru_read_hit0,
utlb_plru_read_hit1,
utlb_plru_read_hit_vld0,
utlb_plru_read_hit_vld1,
utlb_plru_refill_on,
utlb_plru_refill_vld
);
// &Ports; @24
input cp0_mmu_icg_en;
input cpurst_b;
input entry0_vld;
input entry10_vld;
input entry11_vld;
input entry12_vld;
input entry13_vld;
input entry14_vld;
input entry15_vld;
input entry1_vld;
input entry2_vld;
input entry3_vld;
input entry4_vld;
input entry5_vld;
input entry6_vld;
input entry7_vld;
input entry8_vld;
input entry9_vld;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [15:0] utlb_plru_read_hit0;
input [15:0] utlb_plru_read_hit1;
input utlb_plru_read_hit_vld0;
input utlb_plru_read_hit_vld1;
input utlb_plru_refill_on;
input utlb_plru_refill_vld;
output [15:0] plru_dutlb_ref_num;
// &Regs; @25
reg [3 :0] hit_num_flop0;
reg [3 :0] hit_num_flop1;
reg [3 :0] hit_num_index0;
reg [3 :0] hit_num_index1;
reg p00;
reg p10;
reg p11;
reg p20;
reg p21;
reg p22;
reg p23;
reg p30;
reg p31;
reg p32;
reg p33;
reg p34;
reg p35;
reg p36;
reg p37;
reg [3 :0] refill_num_index;
reg [15:0] refill_num_onehot;
reg [3 :0] write_num;
// &Wires; @26
wire cp0_mmu_icg_en;
wire cpurst_b;
wire entry0_vld;
wire entry10_vld;
wire entry11_vld;
wire entry12_vld;
wire entry13_vld;
wire entry14_vld;
wire entry15_vld;
wire entry1_vld;
wire entry2_vld;
wire entry3_vld;
wire entry4_vld;
wire entry5_vld;
wire entry6_vld;
wire entry7_vld;
wire entry8_vld;
wire entry9_vld;
wire forever_cpuclk;
wire [15:0] hit_num_onehot0;
wire [15:0] hit_num_onehot1;
wire lru_clk;
wire lru_clk_en;
wire p00_read_updt;
wire p00_read_updt_val;
wire p00_write_updt;
wire p00_write_updt_val;
wire p10_rdupdt_by_va0;
wire p10_rdupdt_by_va01;
wire p10_rdupdt_by_va1;
wire p10_read_updt0;
wire p10_read_updt1;
wire p10_read_updt_val0;
wire p10_read_updt_val1;
wire p10_write_updt;
wire p10_write_updt_val;
wire p11_rdupdt_by_va0;
wire p11_rdupdt_by_va01;
wire p11_rdupdt_by_va1;
wire p11_read_updt0;
wire p11_read_updt1;
wire p11_read_updt_val0;
wire p11_read_updt_val1;
wire p11_write_updt;
wire p11_write_updt_val;
wire p20_rdupdt_by_va0;
wire p20_rdupdt_by_va01;
wire p20_rdupdt_by_va1;
wire p20_read_updt0;
wire p20_read_updt1;
wire p20_read_updt_val0;
wire p20_read_updt_val1;
wire p20_write_updt;
wire p20_write_updt_val;
wire p21_rdupdt_by_va0;
wire p21_rdupdt_by_va01;
wire p21_rdupdt_by_va1;
wire p21_read_updt0;
wire p21_read_updt1;
wire p21_read_updt_val0;
wire p21_read_updt_val1;
wire p21_write_updt;
wire p21_write_updt_val;
wire p22_rdupdt_by_va0;
wire p22_rdupdt_by_va01;
wire p22_rdupdt_by_va1;
wire p22_read_updt0;
wire p22_read_updt1;
wire p22_read_updt_val0;
wire p22_read_updt_val1;
wire p22_write_updt;
wire p22_write_updt_val;
wire p23_rdupdt_by_va0;
wire p23_rdupdt_by_va01;
wire p23_rdupdt_by_va1;
wire p23_read_updt0;
wire p23_read_updt1;
wire p23_read_updt_val0;
wire p23_read_updt_val1;
wire p23_write_updt;
wire p23_write_updt_val;
wire p30_rdupdt_by_va0;
wire p30_rdupdt_by_va01;
wire p30_rdupdt_by_va1;
wire p30_read_updt0;
wire p30_read_updt1;
wire p30_read_updt_val0;
wire p30_read_updt_val1;
wire p30_write_updt;
wire p30_write_updt_val;
wire p31_rdupdt_by_va0;
wire p31_rdupdt_by_va01;
wire p31_rdupdt_by_va1;
wire p31_read_updt0;
wire p31_read_updt1;
wire p31_read_updt_val0;
wire p31_read_updt_val1;
wire p31_write_updt;
wire p31_write_updt_val;
wire p32_rdupdt_by_va0;
wire p32_rdupdt_by_va01;
wire p32_rdupdt_by_va1;
wire p32_read_updt0;
wire p32_read_updt1;
wire p32_read_updt_val0;
wire p32_read_updt_val1;
wire p32_write_updt;
wire p32_write_updt_val;
wire p33_rdupdt_by_va0;
wire p33_rdupdt_by_va01;
wire p33_rdupdt_by_va1;
wire p33_read_updt0;
wire p33_read_updt1;
wire p33_read_updt_val0;
wire p33_read_updt_val1;
wire p33_write_updt;
wire p33_write_updt_val;
wire p34_rdupdt_by_va0;
wire p34_rdupdt_by_va01;
wire p34_rdupdt_by_va1;
wire p34_read_updt0;
wire p34_read_updt1;
wire p34_read_updt_val0;
wire p34_read_updt_val1;
wire p34_write_updt;
wire p34_write_updt_val;
wire p35_rdupdt_by_va0;
wire p35_rdupdt_by_va01;
wire p35_rdupdt_by_va1;
wire p35_read_updt0;
wire p35_read_updt1;
wire p35_read_updt_val0;
wire p35_read_updt_val1;
wire p35_write_updt;
wire p35_write_updt_val;
wire p36_rdupdt_by_va0;
wire p36_rdupdt_by_va01;
wire p36_rdupdt_by_va1;
wire p36_read_updt0;
wire p36_read_updt1;
wire p36_read_updt_val0;
wire p36_read_updt_val1;
wire p36_write_updt;
wire p36_write_updt_val;
wire p37_rdupdt_by_va0;
wire p37_rdupdt_by_va01;
wire p37_rdupdt_by_va1;
wire p37_read_updt0;
wire p37_read_updt1;
wire p37_read_updt_val0;
wire p37_read_updt_val1;
wire p37_write_updt;
wire p37_write_updt_val;
wire pad_yy_icg_scan_en;
wire [15:0] plru_dutlb_ref_num;
wire [3 :0] plru_num;
wire plru_read_updt;
wire plru_read_updt0;
wire plru_read_updt1;
wire plru_write_updt;
wire [15:0] utlb_plru_read_hit0;
wire [15:0] utlb_plru_read_hit1;
wire utlb_plru_read_hit_vld0;
wire utlb_plru_read_hit_vld1;
wire utlb_plru_refill_on;
wire utlb_plru_refill_vld;
wire [15:0] vld_entry_num;
//==========================================================
// Gate Cell
//==========================================================
assign lru_clk_en = utlb_plru_refill_on
|| plru_read_updt0
|| plru_read_updt1;
// &Instance("gated_clk_cell", "x_dplru_gateclk"); @35
gated_clk_cell x_dplru_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (lru_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (lru_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @36
// .external_en(1'b0 ), @37
// .global_en (1'b1 ), @38
// .module_en (cp0_mmu_icg_en), @39
// .local_en (lru_clk_en ), @40
// .clk_out (lru_clk ) @41
// ); @42
//==========================================================
// Entry sel for Refill
//==========================================================
assign vld_entry_num[15:0] = {entry15_vld, entry14_vld, entry13_vld, entry12_vld,
entry11_vld, entry10_vld, entry9_vld, entry8_vld,
entry7_vld, entry6_vld, entry5_vld, entry4_vld,
entry3_vld, entry2_vld, entry1_vld, entry0_vld};
// &CombBeg; @53
always @( plru_num[3:0]
or vld_entry_num[15:0])
begin
casez(vld_entry_num[15:0])
16'b???????????????0: write_num[3:0] = 4'b0000;
16'b??????????????01: write_num[3:0] = 4'b0001;
16'b?????????????011: write_num[3:0] = 4'b0010;
16'b????????????0111: write_num[3:0] = 4'b0011;
16'b???????????01111: write_num[3:0] = 4'b0100;
16'b??????????011111: write_num[3:0] = 4'b0101;
16'b?????????0111111: write_num[3:0] = 4'b0110;
16'b????????01111111: write_num[3:0] = 4'b0111;
16'b???????011111111: write_num[3:0] = 4'b1000;
16'b??????0111111111: write_num[3:0] = 4'b1001;
16'b?????01111111111: write_num[3:0] = 4'b1010;
16'b????011111111111: write_num[3:0] = 4'b1011;
16'b???0111111111111: write_num[3:0] = 4'b1100;
16'b??01111111111111: write_num[3:0] = 4'b1101;
16'b?011111111111111: write_num[3:0] = 4'b1110;
16'b0111111111111111: write_num[3:0] = 4'b1111;
16'b1111111111111111: write_num[3:0] = plru_num[3:0];
endcase
// &CombEnd; @73
end
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
refill_num_index[3:0] <= 4'b0;
else if(utlb_plru_refill_on)
refill_num_index[3:0] <= write_num[3:0];
end
// &CombBeg; @85
always @( refill_num_index[3:0])
begin
case(refill_num_index[3:0])
4'b0000: refill_num_onehot[15:0] = 16'b0000000000000001;
4'b0001: refill_num_onehot[15:0] = 16'b0000000000000010;
4'b0010: refill_num_onehot[15:0] = 16'b0000000000000100;
4'b0011: refill_num_onehot[15:0] = 16'b0000000000001000;
4'b0100: refill_num_onehot[15:0] = 16'b0000000000010000;
4'b0101: refill_num_onehot[15:0] = 16'b0000000000100000;
4'b0110: refill_num_onehot[15:0] = 16'b0000000001000000;
4'b0111: refill_num_onehot[15:0] = 16'b0000000010000000;
4'b1000: refill_num_onehot[15:0] = 16'b0000000100000000;
4'b1001: refill_num_onehot[15:0] = 16'b0000001000000000;
4'b1010: refill_num_onehot[15:0] = 16'b0000010000000000;
4'b1011: refill_num_onehot[15:0] = 16'b0000100000000000;
4'b1100: refill_num_onehot[15:0] = 16'b0001000000000000;
4'b1101: refill_num_onehot[15:0] = 16'b0010000000000000;
4'b1110: refill_num_onehot[15:0] = 16'b0100000000000000;
4'b1111: refill_num_onehot[15:0] = 16'b1000000000000000;
endcase
// &CombEnd; @104
end
//----------------------------------------------------------
// Final Refill Sel to uTLB
//----------------------------------------------------------
assign plru_dutlb_ref_num[15:0] = refill_num_onehot[15:0];
//==========================================================
// Read Update
//==========================================================
// When utlb hit with different entry, updata PLRU path flop
assign hit_num_onehot0[15:0] = utlb_plru_read_hit0[15:0];
// &CombBeg; @120
always @( hit_num_onehot0[15:0])
begin
case(hit_num_onehot0[15:0])
16'b0000000000000001: hit_num_index0[3:0] = 4'b0000;
16'b0000000000000010: hit_num_index0[3:0] = 4'b0001;
16'b0000000000000100: hit_num_index0[3:0] = 4'b0010;
16'b0000000000001000: hit_num_index0[3:0] = 4'b0011;
16'b0000000000010000: hit_num_index0[3:0] = 4'b0100;
16'b0000000000100000: hit_num_index0[3:0] = 4'b0101;
16'b0000000001000000: hit_num_index0[3:0] = 4'b0110;
16'b0000000010000000: hit_num_index0[3:0] = 4'b0111;
16'b0000000100000000: hit_num_index0[3:0] = 4'b1000;
16'b0000001000000000: hit_num_index0[3:0] = 4'b1001;
16'b0000010000000000: hit_num_index0[3:0] = 4'b1010;
16'b0000100000000000: hit_num_index0[3:0] = 4'b1011;
16'b0001000000000000: hit_num_index0[3:0] = 4'b1100;
16'b0010000000000000: hit_num_index0[3:0] = 4'b1101;
16'b0100000000000000: hit_num_index0[3:0] = 4'b1110;
16'b1000000000000000: hit_num_index0[3:0] = 4'b1111;
default : hit_num_index0[3:0] = 4'b0000;
endcase
// &CombEnd; @140
end
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
hit_num_flop0[3:0] <= 4'b0;
else if(utlb_plru_read_hit_vld0)
hit_num_flop0[3:0] <= hit_num_index0[3:0];
end
assign hit_num_onehot1[15:0] = utlb_plru_read_hit1[15:0];
// &CombBeg; @153
always @( hit_num_onehot1[15:0])
begin
case(hit_num_onehot1[15:0])
16'b0000000000000001: hit_num_index1[3:0] = 4'b0000;
16'b0000000000000010: hit_num_index1[3:0] = 4'b0001;
16'b0000000000000100: hit_num_index1[3:0] = 4'b0010;
16'b0000000000001000: hit_num_index1[3:0] = 4'b0011;
16'b0000000000010000: hit_num_index1[3:0] = 4'b0100;
16'b0000000000100000: hit_num_index1[3:0] = 4'b0101;
16'b0000000001000000: hit_num_index1[3:0] = 4'b0110;
16'b0000000010000000: hit_num_index1[3:0] = 4'b0111;
16'b0000000100000000: hit_num_index1[3:0] = 4'b1000;
16'b0000001000000000: hit_num_index1[3:0] = 4'b1001;
16'b0000010000000000: hit_num_index1[3:0] = 4'b1010;
16'b0000100000000000: hit_num_index1[3:0] = 4'b1011;
16'b0001000000000000: hit_num_index1[3:0] = 4'b1100;
16'b0010000000000000: hit_num_index1[3:0] = 4'b1101;
16'b0100000000000000: hit_num_index1[3:0] = 4'b1110;
16'b1000000000000000: hit_num_index1[3:0] = 4'b1111;
default : hit_num_index1[3:0] = 4'b0000;
endcase
// &CombEnd; @173
end
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
hit_num_flop1[3:0] <= 4'b0;
else if(utlb_plru_read_hit_vld1)
hit_num_flop1[3:0] <= hit_num_index1[3:0];
end
//==========================================================
// PLRU Path Flop
//==========================================================
// P00
// /\
// / \
// / \
// 0/ \1
// / \
// P10 P11
// /\ /\
// 0/ \1 0/ \1
// / \ / \
// P20 P21 P22 P23
// /\ /\ /\ /\
// 0/ \1 0/ \1 0/ \1 0/ \1
// P30 P31 P32 P33 P34 P35 P36 P37
assign plru_write_updt = utlb_plru_refill_vld;
assign plru_read_updt0 = utlb_plru_read_hit_vld0
&& (hit_num_flop0[3:0] != hit_num_index0[3:0]);
assign plru_read_updt1 = utlb_plru_read_hit_vld1
&& (hit_num_flop1[3:0] != hit_num_index1[3:0]);
assign plru_read_updt = plru_read_updt0 || plru_read_updt1;
//----------------------------------------------------------
// Level 0 Path
//----------------------------------------------------------
// Path 0
assign p00_write_updt = plru_write_updt;
assign p00_read_updt = plru_read_updt
&& (hit_num_index0[3] == hit_num_index1[3]);
assign p00_write_updt_val = !refill_num_index[3];
assign p00_read_updt_val = !hit_num_index0[3];
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p00 <= 1'b0;
else if(p00_write_updt)
p00 <= p00_write_updt_val;
else if(p00_read_updt)
p00 <= p00_read_updt_val;
end
//----------------------------------------------------------
// Level 1 Path
//----------------------------------------------------------
// Path 10
assign p10_write_updt = plru_write_updt && !refill_num_index[3];
assign p10_read_updt0 = plru_read_updt0 && !hit_num_index0[3];
assign p10_read_updt1 = plru_read_updt1 && !hit_num_index1[3];
assign p10_write_updt_val = (refill_num_index[3:2] == 2'b00);
assign p10_read_updt_val0 = (hit_num_index0[3:2] == 2'b00);
assign p10_read_updt_val1 = (hit_num_index1[3:2] == 2'b00);
assign p10_rdupdt_by_va0 = p10_read_updt0 && !p10_read_updt1;
assign p10_rdupdt_by_va1 = !p10_read_updt0 && p10_read_updt1;
assign p10_rdupdt_by_va01 = (p10_read_updt0 && p10_read_updt1)
&& (p10_read_updt_val0 ^~ p10_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p10 <= 1'b0;
else if(p10_write_updt)
p10 <= p10_write_updt_val;
else if(p10_rdupdt_by_va0 || p10_rdupdt_by_va01)
p10 <= p10_read_updt_val0;
else if(p10_rdupdt_by_va1)
p10 <= p10_read_updt_val1;
end
// Path 11
assign p11_write_updt = plru_write_updt && refill_num_index[3];
assign p11_read_updt0 = plru_read_updt0 && hit_num_index0[3];
assign p11_read_updt1 = plru_read_updt1 && hit_num_index1[3];
assign p11_write_updt_val = (refill_num_index[3:2] == 2'b10);
assign p11_read_updt_val0 = (hit_num_index0[3:2] == 2'b10);
assign p11_read_updt_val1 = (hit_num_index1[3:2] == 2'b10);
assign p11_rdupdt_by_va0 = p11_read_updt0 && !p11_read_updt1;
assign p11_rdupdt_by_va1 = !p11_read_updt0 && p11_read_updt1;
assign p11_rdupdt_by_va01 = (p11_read_updt0 && p11_read_updt1)
&& (p11_read_updt_val0 ^~ p11_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p11 <= 1'b0;
else if(p11_write_updt)
p11 <= p11_write_updt_val;
else if(p11_rdupdt_by_va0 || p11_rdupdt_by_va01)
p11 <= p11_read_updt_val0;
else if(p11_rdupdt_by_va1)
p11 <= p11_read_updt_val1;
end
//----------------------------------------------------------
// Level 2 Path
//----------------------------------------------------------
// Path 20
assign p20_write_updt = plru_write_updt
&& (refill_num_index[3:2] == 2'b00);
assign p20_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:2] == 2'b00);
assign p20_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:2] == 2'b00);
assign p20_write_updt_val = (refill_num_index[3:1] == 3'b000);
assign p20_read_updt_val0 = (hit_num_index0[3:1] == 3'b000);
assign p20_read_updt_val1 = (hit_num_index1[3:1] == 3'b000);
assign p20_rdupdt_by_va0 = p20_read_updt0 && !p20_read_updt1;
assign p20_rdupdt_by_va1 = !p20_read_updt0 && p20_read_updt1;
assign p20_rdupdt_by_va01 = (p20_read_updt0 && p20_read_updt1)
&& (p20_read_updt_val0 ^~ p20_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p20 <= 1'b0;
else if(p20_write_updt)
p20 <= p20_write_updt_val;
else if(p20_rdupdt_by_va0 || p20_rdupdt_by_va01)
p20 <= p20_read_updt_val0;
else if(p20_rdupdt_by_va1)
p20 <= p20_read_updt_val1;
end
// Path 21
assign p21_write_updt = plru_write_updt
&& (refill_num_index[3:2] == 2'b01);
assign p21_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:2] == 2'b01);
assign p21_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:2] == 2'b01);
assign p21_write_updt_val = (refill_num_index[3:1] == 3'b010);
assign p21_read_updt_val0 = (hit_num_index0[3:1] == 3'b010);
assign p21_read_updt_val1 = (hit_num_index1[3:1] == 3'b010);
assign p21_rdupdt_by_va0 = p21_read_updt0 && !p21_read_updt1;
assign p21_rdupdt_by_va1 = !p21_read_updt0 && p21_read_updt1;
assign p21_rdupdt_by_va01 = (p21_read_updt0 && p21_read_updt1)
&& (p21_read_updt_val0 ^~ p21_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p21 <= 1'b0;
else if(p21_write_updt)
p21 <= p21_write_updt_val;
else if(p21_rdupdt_by_va0 || p21_rdupdt_by_va01)
p21 <= p21_read_updt_val0;
else if(p21_rdupdt_by_va1)
p21 <= p21_read_updt_val1;
end
// Path 22
assign p22_write_updt = plru_write_updt
&& (refill_num_index[3:2] == 2'b10);
assign p22_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:2] == 2'b10);
assign p22_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:2] == 2'b10);
assign p22_write_updt_val = (refill_num_index[3:1] == 3'b100);
assign p22_read_updt_val0 = (hit_num_index0[3:1] == 3'b100);
assign p22_read_updt_val1 = (hit_num_index1[3:1] == 3'b100);
assign p22_rdupdt_by_va0 = p22_read_updt0 && !p22_read_updt1;
assign p22_rdupdt_by_va1 = !p22_read_updt0 && p22_read_updt1;
assign p22_rdupdt_by_va01 = (p22_read_updt0 && p22_read_updt1)
&& (p22_read_updt_val0 ^~ p22_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p22 <= 1'b0;
else if(p22_write_updt)
p22 <= p22_write_updt_val;
else if(p22_rdupdt_by_va0 || p22_rdupdt_by_va01)
p22 <= p22_read_updt_val0;
else if(p22_rdupdt_by_va1)
p22 <= p22_read_updt_val1;
end
// Path 23
assign p23_write_updt = plru_write_updt
&& (refill_num_index[3:2] == 2'b11);
assign p23_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:2] == 2'b11);
assign p23_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:2] == 2'b11);
assign p23_write_updt_val = (refill_num_index[3:1] == 3'b110);
assign p23_read_updt_val0 = (hit_num_index0[3:1] == 3'b110);
assign p23_read_updt_val1 = (hit_num_index1[3:1] == 3'b110);
assign p23_rdupdt_by_va0 = p23_read_updt0 && !p23_read_updt1;
assign p23_rdupdt_by_va1 = !p23_read_updt0 && p23_read_updt1;
assign p23_rdupdt_by_va01 = (p23_read_updt0 && p23_read_updt1)
&& (p23_read_updt_val0 ^~ p23_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p23 <= 1'b0;
else if(p23_write_updt)
p23 <= p23_write_updt_val;
else if(p23_rdupdt_by_va0 || p23_rdupdt_by_va01)
p23 <= p23_read_updt_val0;
else if(p23_rdupdt_by_va1)
p23 <= p23_read_updt_val1;
end
//----------------------------------------------------------
// Level 3 Path
//----------------------------------------------------------
//Path 30
assign p30_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b000);
assign p30_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b000);
assign p30_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b000);
assign p30_write_updt_val = (refill_num_index[3:0] == 4'b0000);
assign p30_read_updt_val0 = (hit_num_index0[3:0] == 4'b0000);
assign p30_read_updt_val1 = (hit_num_index1[3:0] == 4'b0000);
assign p30_rdupdt_by_va0 = p30_read_updt0 && !p30_read_updt1;
assign p30_rdupdt_by_va1 = !p30_read_updt0 && p30_read_updt1;
assign p30_rdupdt_by_va01 = (p30_read_updt0 && p30_read_updt1)
&& (p30_read_updt_val0 ^~ p30_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p30 <= 1'b0;
else if(p30_write_updt)
p30 <= p30_write_updt_val;
else if(p30_rdupdt_by_va0 || p30_rdupdt_by_va01)
p30 <= p30_read_updt_val0;
else if(p30_rdupdt_by_va1)
p30 <= p30_read_updt_val1;
end
//Path 31
assign p31_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b001);
assign p31_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b001);
assign p31_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b001);
assign p31_write_updt_val = (refill_num_index[3:0] == 4'b0010);
assign p31_read_updt_val0 = (hit_num_index0[3:0] == 4'b0010);
assign p31_read_updt_val1 = (hit_num_index1[3:0] == 4'b0010);
assign p31_rdupdt_by_va0 = p31_read_updt0 && !p31_read_updt1;
assign p31_rdupdt_by_va1 = !p31_read_updt0 && p31_read_updt1;
assign p31_rdupdt_by_va01 = (p31_read_updt0 && p31_read_updt1)
&& (p31_read_updt_val0 ^~ p31_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p31 <= 1'b0;
else if(p31_write_updt)
p31 <= p31_write_updt_val;
else if(p31_rdupdt_by_va0 || p31_rdupdt_by_va01)
p31 <= p31_read_updt_val0;
else if(p31_rdupdt_by_va1)
p31 <= p31_read_updt_val1;
end
//Path 32
assign p32_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b010);
assign p32_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b010);
assign p32_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b010);
assign p32_write_updt_val = (refill_num_index[3:0] == 4'b0100);
assign p32_read_updt_val0 = (hit_num_index0[3:0] == 4'b0100);
assign p32_read_updt_val1 = (hit_num_index1[3:0] == 4'b0100);
assign p32_rdupdt_by_va0 = p32_read_updt0 && !p32_read_updt1;
assign p32_rdupdt_by_va1 = !p32_read_updt0 && p32_read_updt1;
assign p32_rdupdt_by_va01 = (p32_read_updt0 && p32_read_updt1)
&& (p32_read_updt_val0 ^~ p32_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p32 <= 1'b0;
else if(p32_write_updt)
p32 <= p32_write_updt_val;
else if(p32_rdupdt_by_va0 || p32_rdupdt_by_va01)
p32 <= p32_read_updt_val0;
else if(p32_rdupdt_by_va1)
p32 <= p32_read_updt_val1;
end
//Path 33
assign p33_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b011);
assign p33_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b011);
assign p33_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b011);
assign p33_write_updt_val = (refill_num_index[3:0] == 4'b0110);
assign p33_read_updt_val0 = (hit_num_index0[3:0] == 4'b0110);
assign p33_read_updt_val1 = (hit_num_index1[3:0] == 4'b0110);
assign p33_rdupdt_by_va0 = p33_read_updt0 && !p33_read_updt1;
assign p33_rdupdt_by_va1 = !p33_read_updt0 && p33_read_updt1;
assign p33_rdupdt_by_va01 = (p33_read_updt0 && p33_read_updt1)
&& (p33_read_updt_val0 ^~ p33_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p33 <= 1'b0;
else if(p33_write_updt)
p33 <= p33_write_updt_val;
else if(p33_rdupdt_by_va0 || p33_rdupdt_by_va01)
p33 <= p33_read_updt_val0;
else if(p33_rdupdt_by_va1)
p33 <= p33_read_updt_val1;
end
//Path 34
assign p34_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b100);
assign p34_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b100);
assign p34_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b100);
assign p34_write_updt_val = (refill_num_index[3:0] == 4'b1000);
assign p34_read_updt_val0 = (hit_num_index0[3:0] == 4'b1000);
assign p34_read_updt_val1 = (hit_num_index1[3:0] == 4'b1000);
assign p34_rdupdt_by_va0 = p34_read_updt0 && !p34_read_updt1;
assign p34_rdupdt_by_va1 = !p34_read_updt0 && p34_read_updt1;
assign p34_rdupdt_by_va01 = (p34_read_updt0 && p34_read_updt1)
&& (p34_read_updt_val0 ^~ p34_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p34 <= 1'b0;
else if(p34_write_updt)
p34 <= p34_write_updt_val;
else if(p34_rdupdt_by_va0 || p34_rdupdt_by_va01)
p34 <= p34_read_updt_val0;
else if(p34_rdupdt_by_va1)
p34 <= p34_read_updt_val1;
end
//Path 35
assign p35_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b101);
assign p35_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b101);
assign p35_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b101);
assign p35_write_updt_val = (refill_num_index[3:0] == 4'b1010);
assign p35_read_updt_val0 = (hit_num_index0[3:0] == 4'b1010);
assign p35_read_updt_val1 = (hit_num_index1[3:0] == 4'b1010);
assign p35_rdupdt_by_va0 = p35_read_updt0 && !p35_read_updt1;
assign p35_rdupdt_by_va1 = !p35_read_updt0 && p35_read_updt1;
assign p35_rdupdt_by_va01 = (p35_read_updt0 && p35_read_updt1)
&& (p35_read_updt_val0 ^~ p35_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p35 <= 1'b0;
else if(p35_write_updt)
p35 <= p35_write_updt_val;
else if(p35_rdupdt_by_va0 || p35_rdupdt_by_va01)
p35 <= p35_read_updt_val0;
else if(p35_rdupdt_by_va1)
p35 <= p35_rdupdt_by_va1;
end
//Path 36
assign p36_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b110);
assign p36_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b110);
assign p36_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b110);
assign p36_write_updt_val = (refill_num_index[3:0] == 4'b1100);
assign p36_read_updt_val0 = (hit_num_index0[3:0] == 4'b1100);
assign p36_read_updt_val1 = (hit_num_index1[3:0] == 4'b1100);
assign p36_rdupdt_by_va0 = p36_read_updt0 && !p36_read_updt1;
assign p36_rdupdt_by_va1 = !p36_read_updt0 && p36_read_updt1;
assign p36_rdupdt_by_va01 = (p36_read_updt0 && p36_read_updt1)
&& (p36_read_updt_val0 ^~ p36_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p36 <= 1'b0;
else if(p36_write_updt)
p36 <= p36_write_updt_val;
else if(p36_rdupdt_by_va0 || p36_rdupdt_by_va01)
p36 <= p36_read_updt_val0;
else if(p36_rdupdt_by_va1)
p36 <= p36_read_updt_val1;
end
//Path 37
assign p37_write_updt = plru_write_updt
&& (refill_num_index[3:1] == 3'b111);
assign p37_read_updt0 = plru_read_updt0
&& (hit_num_index0[3:1] == 3'b111);
assign p37_read_updt1 = plru_read_updt1
&& (hit_num_index1[3:1] == 3'b111);
assign p37_write_updt_val = (refill_num_index[3:0] == 4'b1110);
assign p37_read_updt_val0 = (hit_num_index0[3:0] == 4'b1110);
assign p37_read_updt_val1 = (hit_num_index1[3:0] == 4'b1110);
assign p37_rdupdt_by_va0 = p37_read_updt0 && !p37_read_updt1;
assign p37_rdupdt_by_va1 = !p37_read_updt0 && p37_read_updt1;
assign p37_rdupdt_by_va01 = (p37_read_updt0 && p37_read_updt1)
&& (p37_read_updt_val0 ^~ p37_read_updt_val1);
always @(posedge lru_clk or negedge cpurst_b)
begin
if(!cpurst_b)
p37 <= 1'b0;
else if(p37_write_updt)
p37 <= p37_write_updt_val;
else if(p37_rdupdt_by_va0 || p37_rdupdt_by_va01)
p37 <= p37_read_updt_val0;
else if(p37_rdupdt_by_va1)
p37 <= p37_read_updt_val1;
end
//----------------------------------------------------------
// uTLB Replacement Algorithm
//----------------------------------------------------------
assign plru_num[3] = p00;
assign plru_num[2] = !p00 && p10
|| p00 && p11;
assign plru_num[1] = !p00 && !p10 && p20
||!p00 && p10 && p21
|| p00 && !p11 && p22
|| p00 && p11 && p23;
assign plru_num[0] = !p00 && !p10 && !p20 && p30
||!p00 && !p10 && p20 && p31
||!p00 && p10 && !p21 && p32
||!p00 && p10 && p21 && p33
|| p00 && !p11 && !p22 && p34
|| p00 && !p11 && p22 && p35
|| p00 && p11 && !p23 && p36
|| p00 && p11 && p23 && p37;
// &ModuleEnd; @671
endmodule |
module ct_mmu_dutlb_huge_entry(
cp0_mmu_icg_en,
cpurst_b,
lsu_mmu_tlb_va,
pad_yy_icg_scan_en,
regs_utlb_clr,
tlboper_utlb_clr,
tlboper_utlb_inv_va_req,
utlb_clk,
utlb_entry_flg,
utlb_entry_hit0,
utlb_entry_hit1,
utlb_entry_ppn,
utlb_entry_upd,
utlb_entry_vld,
utlb_req_vpn0,
utlb_req_vpn1,
utlb_upd_flg,
utlb_upd_ppn,
utlb_upd_vpn
);
// &Ports; @25
input cp0_mmu_icg_en;
input cpurst_b;
input [26:0] lsu_mmu_tlb_va;
input pad_yy_icg_scan_en;
input regs_utlb_clr;
input tlboper_utlb_clr;
input tlboper_utlb_inv_va_req;
input utlb_clk;
input utlb_entry_upd;
input [26:0] utlb_req_vpn0;
input [26:0] utlb_req_vpn1;
input [13:0] utlb_upd_flg;
input [27:0] utlb_upd_ppn;
input [26:0] utlb_upd_vpn;
output [13:0] utlb_entry_flg;
output utlb_entry_hit0;
output utlb_entry_hit1;
output [27:0] utlb_entry_ppn;
output utlb_entry_vld;
// &Regs; @26
reg [13:0] utlb_flg;
reg [27:0] utlb_ppn;
reg utlb_vld;
reg [26:0] utlb_vpn;
// &Wires; @27
wire cp0_mmu_icg_en;
wire cpurst_b;
wire ctc_inv_va_hit_clr;
wire entry_clk_en;
wire [26:0] lsu_mmu_tlb_va;
wire pad_yy_icg_scan_en;
wire regs_utlb_clr;
wire tlboper_utlb_clr;
wire tlboper_utlb_inv_va_req;
wire utlb_clk;
wire utlb_entry_clk;
wire utlb_entry_clr;
wire [13:0] utlb_entry_flg;
wire utlb_entry_gating_clr;
wire utlb_entry_hit0;
wire utlb_entry_hit1;
wire [27:0] utlb_entry_ppn;
wire utlb_entry_upd;
wire utlb_entry_vld;
wire utlb_hit0;
wire utlb_hit1;
wire [26:0] utlb_req_vpn0;
wire [26:0] utlb_req_vpn1;
wire [13:0] utlb_upd_flg;
wire [27:0] utlb_upd_ppn;
wire [26:0] utlb_upd_vpn;
// &Force("bus","lsu_mmu_tlb_va",26,0); @28
parameter VPN_WIDTH = 39-12; // VPN
parameter PPN_WIDTH = 40-12; // PPN
parameter FLG_WIDTH = 14; // Flags
parameter PGS_WIDTH = 3; // Page Size
parameter PTE_LEVEL = 3; // Page Table Label
parameter LVL_WIDTH = 9;
//============================================================
// MicroTLB Entry
//============================================================
//------------------------------------------------------------
// 1. ASID field are not included in uTLB entry
// 2. Each Data uTLB entry always matches the ASID in the SATP
// register
// 3. The micro tlb entry layout is figured as following:
// =========================================
// | |72 46|45 43|42 15|14 0|
// |-------+-------+----------+-----+------+
// | Valid | VPN | PageSize | PFN | Flag |
// =========================================
//------------------------------------------------------------
// Gated Cell for utlb entry
assign entry_clk_en = utlb_entry_gating_clr
|| utlb_entry_upd;
// &Instance("gated_clk_cell", "x_dutlb_entry_gateclk"); @55
gated_clk_cell x_dutlb_entry_gateclk (
.clk_in (utlb_clk ),
.clk_out (utlb_entry_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (entry_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (utlb_clk ), @56
// .external_en(1'b0 ), @57
// .global_en (1'b1 ), @58
// .module_en (cp0_mmu_icg_en), @59
// .local_en (entry_clk_en ), @60
// .clk_out (utlb_entry_clk) @61
// ); @62
//------------------------------------------------------------
// Valid bit generating
//------------------------------------------------------------
assign utlb_entry_clr = regs_utlb_clr
|| tlboper_utlb_clr
|| ctc_inv_va_hit_clr;
assign utlb_entry_gating_clr = regs_utlb_clr
|| tlboper_utlb_clr
|| tlboper_utlb_inv_va_req;
assign ctc_inv_va_hit_clr = tlboper_utlb_inv_va_req
&& (lsu_mmu_tlb_va[7:0] == utlb_vpn[7:0]);
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
utlb_vld <= 1'b0;
else if(utlb_entry_clr)
utlb_vld <= 1'b0;
else if(utlb_entry_upd)
utlb_vld <= 1'b1;
end
//------------------------------------------------------------
// VPN Information
//------------------------------------------------------------
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
utlb_vpn[VPN_WIDTH-1:0] <= {VPN_WIDTH{1'b0}};
else if(utlb_entry_upd)
utlb_vpn[VPN_WIDTH-1:0] <= utlb_upd_vpn[VPN_WIDTH-1:0];
end
//------------------------------------------------------------
// PFN and Flag information
//------------------------------------------------------------
always @(posedge utlb_entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
utlb_ppn[PPN_WIDTH-1:0] <= {PPN_WIDTH{1'b0}};
utlb_flg[FLG_WIDTH-1:0] <= {FLG_WIDTH{1'b0}};
end
else if(utlb_entry_upd)
begin
utlb_ppn[PPN_WIDTH-1:0] <= utlb_upd_ppn[PPN_WIDTH-1:0];
utlb_flg[FLG_WIDTH-1:0] <= utlb_upd_flg[FLG_WIDTH-1:0];
end
end
//------------------------------------------------------------
// Entry Hit
//------------------------------------------------------------
// &Force("bus", "utlb_req_vpn0", 26, 0); @117
// &Force("bus", "utlb_req_vpn1", 26, 0); @118
assign utlb_hit0 = utlb_req_vpn0[VPN_WIDTH-1:VPN_WIDTH-LVL_WIDTH]
== utlb_vpn[VPN_WIDTH-1:VPN_WIDTH-LVL_WIDTH];
assign utlb_hit1 = utlb_req_vpn1[VPN_WIDTH-1:VPN_WIDTH-LVL_WIDTH]
== utlb_vpn[VPN_WIDTH-1:VPN_WIDTH-LVL_WIDTH];
//------------------------------------------------------------
// Output
//------------------------------------------------------------
assign utlb_entry_vld = utlb_vld;
assign utlb_entry_hit0 = utlb_hit0;
assign utlb_entry_hit1 = utlb_hit1;
//assign utlb_entry_vpn[VPN_WIDTH-1:0] = utlb_vpn[VPN_WIDTH-1:0];
assign utlb_entry_ppn[PPN_WIDTH-1:0] = utlb_ppn[PPN_WIDTH-1:0];
assign utlb_entry_flg[FLG_WIDTH-1:0] = utlb_flg[FLG_WIDTH-1:0];
// &ModuleEnd; @138
endmodule |
module ct_mmu_ptw(
arb_ptw_grant,
arb_ptw_mask,
cp0_mmu_icg_en,
cp0_mmu_maee,
cp0_mmu_mpp,
cp0_mmu_mprv,
cp0_mmu_mxr,
cp0_mmu_sum,
cp0_yy_priv_mode,
cpurst_b,
dutlb_ptw_wfc,
forever_cpuclk,
hpcp_mmu_cnt_en,
iutlb_ptw_wfc,
jtlb_ptw_req,
jtlb_ptw_type,
jtlb_ptw_vpn,
jtlb_xx_fifo,
lsu_mmu_bus_error,
lsu_mmu_data,
lsu_mmu_data_vld,
mmu_hpcp_jtlb_miss,
mmu_lsu_data_req,
mmu_lsu_data_req_addr,
mmu_lsu_data_req_size,
mmu_pmp_fetch3,
mmu_pmp_pa3,
mmu_sysmap_pa3,
pad_yy_icg_scan_en,
pmp_mmu_flg3,
ptw_arb_bank_sel,
ptw_arb_data_din,
ptw_arb_fifo_din,
ptw_arb_pgs,
ptw_arb_req,
ptw_arb_tag_din,
ptw_arb_vpn,
ptw_jtlb_dmiss,
ptw_jtlb_imiss,
ptw_jtlb_pmiss,
ptw_jtlb_ref_acc_err,
ptw_jtlb_ref_cmplt,
ptw_jtlb_ref_data_vld,
ptw_jtlb_ref_flg,
ptw_jtlb_ref_pgflt,
ptw_jtlb_ref_pgs,
ptw_jtlb_ref_ppn,
ptw_top_cur_st,
ptw_top_imiss,
regs_ptw_cur_asid,
regs_ptw_satp_ppn,
sysmap_mmu_flg3,
sysmap_mmu_hit3,
tlboper_ptw_abort
);
// &Ports; @24
input arb_ptw_grant;
input arb_ptw_mask;
input cp0_mmu_icg_en;
input cp0_mmu_maee;
input [1 :0] cp0_mmu_mpp;
input cp0_mmu_mprv;
input cp0_mmu_mxr;
input cp0_mmu_sum;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input dutlb_ptw_wfc;
input forever_cpuclk;
input hpcp_mmu_cnt_en;
input iutlb_ptw_wfc;
input jtlb_ptw_req;
input [2 :0] jtlb_ptw_type;
input [26:0] jtlb_ptw_vpn;
input [11:0] jtlb_xx_fifo;
input lsu_mmu_bus_error;
input [63:0] lsu_mmu_data;
input lsu_mmu_data_vld;
input pad_yy_icg_scan_en;
input [3 :0] pmp_mmu_flg3;
input [15:0] regs_ptw_cur_asid;
input [27:0] regs_ptw_satp_ppn;
input [4 :0] sysmap_mmu_flg3;
input [7 :0] sysmap_mmu_hit3;
input tlboper_ptw_abort;
output mmu_hpcp_jtlb_miss;
output mmu_lsu_data_req;
output [39:0] mmu_lsu_data_req_addr;
output mmu_lsu_data_req_size;
output mmu_pmp_fetch3;
output [27:0] mmu_pmp_pa3;
output [27:0] mmu_sysmap_pa3;
output [3 :0] ptw_arb_bank_sel;
output [41:0] ptw_arb_data_din;
output [3 :0] ptw_arb_fifo_din;
output [2 :0] ptw_arb_pgs;
output ptw_arb_req;
output [47:0] ptw_arb_tag_din;
output [26:0] ptw_arb_vpn;
output ptw_jtlb_dmiss;
output ptw_jtlb_imiss;
output ptw_jtlb_pmiss;
output ptw_jtlb_ref_acc_err;
output ptw_jtlb_ref_cmplt;
output ptw_jtlb_ref_data_vld;
output [13:0] ptw_jtlb_ref_flg;
output ptw_jtlb_ref_pgflt;
output [2 :0] ptw_jtlb_ref_pgs;
output [27:0] ptw_jtlb_ref_ppn;
output [3 :0] ptw_top_cur_st;
output ptw_top_imiss;
// &Regs; @25
reg jtlb_miss;
reg [63:0] lsu_data_flop;
reg [4 :0] ptw_cur_st;
reg [11:0] ptw_fifo;
reg [7 :0] ptw_hit_num;
reg [4 :0] ptw_nxt_abt_st;
reg [4 :0] ptw_nxt_st;
reg [39:0] ptw_req_addr;
reg [2 :0] ptw_type;
reg [26:0] ptw_vpn;
reg [2 :0] ref_pgs;
// &Wires; @26
wire arb_ptw_grant;
wire arb_ptw_mask;
wire cp0_mach_mode;
wire cp0_mmu_icg_en;
wire cp0_mmu_maee;
wire [1 :0] cp0_mmu_mpp;
wire cp0_mmu_mprv;
wire cp0_mmu_mxr;
wire cp0_mmu_sum;
wire [1 :0] cp0_priv_mode;
wire cp0_supv_mode;
wire cp0_user_mode;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire dutlb_ptw_wfc;
wire forever_cpuclk;
wire hpcp_mmu_cnt_en;
wire iutlb_ptw_wfc;
wire jtlb_miss_cnt;
wire jtlb_ptw_req;
wire [2 :0] jtlb_ptw_type;
wire [26:0] jtlb_ptw_vpn;
wire [11:0] jtlb_xx_fifo;
wire lsu_mmu_bus_error;
wire [63:0] lsu_mmu_data;
wire lsu_mmu_data_vld;
wire mmu_hpcp_jtlb_miss;
wire mmu_lsu_data_req;
wire [39:0] mmu_lsu_data_req_addr;
wire mmu_lsu_data_req_size;
wire mmu_pmp_fetch3;
wire [27:0] mmu_pmp_pa3;
wire [27:0] mmu_sysmap_pa3;
wire pad_yy_icg_scan_en;
wire [3 :0] pmp_mmu_flg3;
wire ptw_addr_fst;
wire ptw_addr_scd;
wire ptw_addr_thd;
wire [3 :0] ptw_arb_bank_sel;
wire [41:0] ptw_arb_data_din;
wire [3 :0] ptw_arb_fifo_din;
wire [2 :0] ptw_arb_pgs;
wire ptw_arb_req;
wire [47:0] ptw_arb_tag_din;
wire [26:0] ptw_arb_vpn;
wire ptw_chk_cross;
wire ptw_chk_fst;
wire ptw_chk_scd;
wire ptw_chk_thd;
wire ptw_clk;
wire ptw_clk_en;
wire ptw_crs1_1g;
wire ptw_crs1_2m;
wire ptw_crs2_1g;
wire ptw_crs2_2m;
wire ptw_crs2_chk;
wire ptw_data_abt;
wire ptw_data_fst;
wire ptw_data_req;
wire ptw_data_scd;
wire ptw_data_thd;
wire ptw_fetch_type;
wire [8 :0] ptw_flg;
wire [39:0] ptw_fst_addr;
wire ptw_hit_1g;
wire ptw_hit_2m;
wire ptw_jtlb_dmiss;
wire ptw_jtlb_imiss;
wire ptw_jtlb_pmiss;
wire ptw_jtlb_ref_acc_err;
wire ptw_jtlb_ref_cmplt;
wire ptw_jtlb_ref_data_vld;
wire [13:0] ptw_jtlb_ref_flg;
wire ptw_jtlb_ref_pgflt;
wire [2 :0] ptw_jtlb_ref_pgs;
wire [27:0] ptw_jtlb_ref_ppn;
wire ptw_leaf_vld;
wire ptw_load_type;
wire ptw_page_flt;
wire ptw_pmp_deny;
wire ptw_pref_type;
wire ptw_ref_acc_err;
wire ptw_ref_cmplt;
wire ptw_ref_data_vld;
wire [3 :0] ptw_ref_fifo;
wire [13:0] ptw_ref_flg;
wire ptw_ref_g;
wire ptw_ref_pgflt;
wire [2 :0] ptw_ref_pgs;
wire [4 :0] ptw_ref_pma;
wire [27:0] ptw_ref_ppn;
wire [26:0] ptw_ref_vpn;
wire ptw_refill_on;
wire [39:0] ptw_req_addr_pre;
wire [39:0] ptw_scd_addr;
wire ptw_store_type;
wire [39:0] ptw_thd_addr;
wire [3 :0] ptw_top_cur_st;
wire ptw_top_imiss;
wire [15:0] regs_ptw_cur_asid;
wire [27:0] regs_ptw_satp_ppn;
wire [4 :0] sysmap_mmu_flg3;
wire [7 :0] sysmap_mmu_hit3;
wire tlboper_ptw_abort;
parameter VADDR_WIDTH = 39; // VADDR
parameter PADDR_WIDTH = 40; // PADDR
parameter VPN_WIDTH = VADDR_WIDTH-12; // VPN
parameter PPN_WIDTH = PADDR_WIDTH-12; // PPN
parameter FLG_WIDTH = 14; // PPN
parameter ASID_WIDTH = 16; // PPN
parameter PGS_WIDTH = 3; // Page Size
parameter PTE_LEVEL = 3; // Page Table Label
// VPN width per level
parameter VPN_PERLEL = VPN_WIDTH/PTE_LEVEL;
// Valid + VPN + ASID + PageSize + Global
parameter TAG_WIDTH = 1+VPN_WIDTH+ASID_WIDTH+PGS_WIDTH+1;
parameter DATA_WIDTH = PPN_WIDTH+FLG_WIDTH;
// current privlidged mode
assign cp0_priv_mode[1:0] = cp0_mmu_mprv ? cp0_mmu_mpp[1:0]
: cp0_yy_priv_mode[1:0];
assign cp0_user_mode = ptw_fetch_type ? cp0_yy_priv_mode[1:0] == 2'b00
: cp0_priv_mode[1:0] == 2'b00;
assign cp0_supv_mode = ptw_fetch_type ? cp0_yy_priv_mode[1:0] == 2'b01
: cp0_priv_mode[1:0] == 2'b01;
assign cp0_mach_mode = ptw_fetch_type ? cp0_yy_priv_mode[1:0] == 2'b11
: cp0_priv_mode[1:0] == 2'b11;
//==========================================================
// Gate Cell
//==========================================================
assign ptw_clk_en = jtlb_ptw_req || ptw_refill_on || jtlb_miss;
// &Instance("gated_clk_cell", "x_ptw_gateclk"); @59
gated_clk_cell x_ptw_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (ptw_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (ptw_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @60
// .external_en(1'b0 ), @61
// .global_en (1'b1 ), @62
// .module_en (cp0_mmu_icg_en ), @63
// .local_en (ptw_clk_en ), @64
// .clk_out (ptw_clk ) @65
// ); @66
//==============================================================================
// Control Path
//==============================================================================
//==========================================================
// PTW FSM
//==========================================================
parameter PTW_IDLE = 5'b00000,
PTW_FST_PMP = 5'b00001,
PTW_FST_DATA = 5'b00010,
PTW_FST_CHK = 5'b00011,
PTW_SCD_PMP = 5'b00100,
PTW_SCD_DATA = 5'b00101,
PTW_SCD_CHK = 5'b00110,
PTW_THD_PMP = 5'b00111,
PTW_THD_DATA = 5'b01000,
PTW_THD_CHK = 5'b01001,
PTW_ACC_FLT = 5'b01010,
PTW_PGE_FLT = 5'b01011,
PTW_DATA_VLD = 5'b01100,
PTW_ABT_DATA = 5'b01101,
PTW_ABT = 5'b01110,
PTW_MACH_PMP = 5'b01111,
PTW_1G_CRS1 = 5'b10000,
PTW_1G_CRS2 = 5'b10001,
PTW_2M_CRS1 = 5'b10010,
PTW_2M_CRS2 = 5'b10011;
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ptw_cur_st[4:0] <= PTW_IDLE;
else if(tlboper_ptw_abort)
ptw_cur_st[4:0] <= ptw_nxt_abt_st[4:0];
else
ptw_cur_st[4:0] <= ptw_nxt_st[4:0];
end
// &CombBeg; @106
always @( ptw_nxt_st[4:0]
or ptw_cur_st
or lsu_mmu_bus_error
or lsu_mmu_data_vld)
begin
case (ptw_cur_st)
PTW_IDLE,
PTW_FST_PMP,
PTW_ACC_FLT,
PTW_PGE_FLT,
PTW_ABT,
PTW_ABT_DATA:
begin
ptw_nxt_abt_st[4:0] = ptw_nxt_st[4:0];
end
PTW_FST_DATA,
PTW_SCD_DATA,
PTW_THD_DATA:
begin
if(lsu_mmu_bus_error || lsu_mmu_data_vld)
ptw_nxt_abt_st[4:0] = PTW_ABT;
else
ptw_nxt_abt_st[4:0] = PTW_ABT_DATA;
end
default:
begin
ptw_nxt_abt_st[4:0] = PTW_ABT;
end
endcase
// &CombEnd; @131
end
// &CombBeg; @133
always @( cp0_mmu_maee
or ptw_hit_2m
or jtlb_ptw_req
or arb_ptw_grant
or ptw_pmp_deny
or ptw_cur_st
or lsu_mmu_bus_error
or lsu_mmu_data_vld
or ptw_hit_1g
or ptw_page_flt
or ptw_chk_cross)
begin
case (ptw_cur_st)
PTW_IDLE:
begin
if(jtlb_ptw_req)
ptw_nxt_st[4:0] = PTW_FST_PMP;
else
ptw_nxt_st[4:0] = PTW_IDLE;
end
PTW_FST_PMP:
begin
if(ptw_pmp_deny)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else
ptw_nxt_st[4:0] = PTW_FST_DATA;
end
PTW_FST_DATA:
begin
if(lsu_mmu_bus_error)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else if(lsu_mmu_data_vld)
ptw_nxt_st[4:0] = PTW_FST_CHK;
else
ptw_nxt_st[4:0] = PTW_FST_DATA;
end
PTW_FST_CHK:
begin
if(ptw_page_flt)
ptw_nxt_st[4:0] = PTW_PGE_FLT;
else
if(ptw_hit_1g)
if(cp0_mmu_maee)
ptw_nxt_st[4:0] = PTW_DATA_VLD;
else
ptw_nxt_st[4:0] = PTW_1G_CRS1;
else
ptw_nxt_st[4:0] = PTW_SCD_PMP;
end
PTW_SCD_PMP:
begin
if(ptw_pmp_deny)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else
ptw_nxt_st[4:0] = PTW_SCD_DATA;
end
PTW_SCD_DATA:
begin
if(lsu_mmu_bus_error)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else if(lsu_mmu_data_vld)
ptw_nxt_st[4:0] = PTW_SCD_CHK;
else
ptw_nxt_st[4:0] = PTW_SCD_DATA;
end
PTW_SCD_CHK:
begin
if(ptw_page_flt)
ptw_nxt_st[4:0] = PTW_PGE_FLT;
else
if(ptw_hit_2m)
if(cp0_mmu_maee)
ptw_nxt_st[4:0] = PTW_DATA_VLD;
else
ptw_nxt_st[4:0] = PTW_2M_CRS1;
else
ptw_nxt_st[4:0] = PTW_THD_PMP;
end
PTW_THD_PMP:
begin
if(ptw_pmp_deny)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else
ptw_nxt_st[4:0] = PTW_THD_DATA;
end
PTW_THD_DATA:
begin
if(lsu_mmu_bus_error)
ptw_nxt_st[4:0] = PTW_ACC_FLT;
else if(lsu_mmu_data_vld)
ptw_nxt_st[4:0] = PTW_THD_CHK;
else
ptw_nxt_st[4:0] = PTW_THD_DATA;
end
PTW_THD_CHK:
begin
if(ptw_page_flt)
ptw_nxt_st[4:0] = PTW_PGE_FLT;
else
ptw_nxt_st[4:0] = PTW_DATA_VLD;
end
PTW_ACC_FLT:
begin
ptw_nxt_st[4:0] = PTW_IDLE;
end
PTW_PGE_FLT:
begin
ptw_nxt_st[4:0] = PTW_IDLE;
end
PTW_MACH_PMP:
begin
ptw_nxt_st[4:0] = PTW_IDLE;
end
PTW_DATA_VLD:
begin
if(arb_ptw_grant)
ptw_nxt_st[4:0] = PTW_IDLE;
else
ptw_nxt_st[4:0] = PTW_DATA_VLD;
end
PTW_ABT_DATA:
begin
if(lsu_mmu_bus_error)
ptw_nxt_st[4:0] = PTW_FST_DATA;
else if(lsu_mmu_data_vld)
ptw_nxt_st[4:0] = PTW_FST_DATA;
else
ptw_nxt_st[4:0] = PTW_ABT_DATA;
end
PTW_ABT:
begin
ptw_nxt_st[4:0] = PTW_FST_DATA;
end
PTW_1G_CRS1:
begin
ptw_nxt_st[4:0] = PTW_1G_CRS2;
end
PTW_1G_CRS2:
begin
if(ptw_chk_cross)
ptw_nxt_st[4:0] = PTW_2M_CRS1;
else
ptw_nxt_st[4:0] = PTW_DATA_VLD;
end
PTW_2M_CRS1:
begin
ptw_nxt_st[4:0] = PTW_2M_CRS2;
end
PTW_2M_CRS2:
begin
ptw_nxt_st[4:0] = PTW_DATA_VLD;
end
default:
begin
ptw_nxt_st[4:0] = PTW_IDLE;
end
endcase
// &CombEnd; @279
end
assign ptw_data_fst = (ptw_cur_st[4:0] == PTW_FST_DATA);
assign ptw_data_scd = (ptw_cur_st[4:0] == PTW_SCD_DATA);
assign ptw_data_thd = (ptw_cur_st[4:0] == PTW_THD_DATA);
assign ptw_data_abt = (ptw_cur_st[4:0] == PTW_ABT_DATA);
assign ptw_chk_fst = (ptw_cur_st[4:0] == PTW_FST_CHK);
assign ptw_chk_scd = (ptw_cur_st[4:0] == PTW_SCD_CHK);
assign ptw_chk_thd = (ptw_cur_st[4:0] == PTW_THD_CHK);
assign ptw_crs1_1g = (ptw_cur_st[4:0] == PTW_1G_CRS1);
assign ptw_crs2_1g = (ptw_cur_st[4:0] == PTW_1G_CRS2);
assign ptw_crs1_2m = (ptw_cur_st[4:0] == PTW_2M_CRS1);
assign ptw_crs2_2m = (ptw_cur_st[4:0] == PTW_2M_CRS2);
assign ptw_crs2_chk = ptw_crs2_1g || ptw_crs2_2m;
assign ptw_refill_on = (ptw_cur_st[4:0] != PTW_IDLE);
assign ptw_data_req = ptw_data_fst || ptw_data_scd || ptw_data_thd || ptw_data_abt;
assign ptw_addr_fst = ptw_cur_st[4:0] == PTW_IDLE && jtlb_ptw_req
|| ptw_cur_st[4:0] == PTW_ABT_DATA && lsu_mmu_data_vld
|| ptw_cur_st[4:0] == PTW_ABT;
assign ptw_addr_scd = ptw_cur_st[4:0] == PTW_FST_DATA && lsu_mmu_data_vld;
assign ptw_addr_thd = ptw_cur_st[4:0] == PTW_SCD_DATA && lsu_mmu_data_vld;
// flop vpn and fifo bit
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
begin
ptw_vpn[VPN_WIDTH-1:0] <= {VPN_WIDTH{1'b0}};
ptw_fifo[11:0] <= 12'b0;
ptw_type[2:0] <= 3'b0;
end
else if(jtlb_ptw_req)
begin
ptw_vpn[VPN_WIDTH-1:0] <= jtlb_ptw_vpn[VPN_WIDTH-1:0];
ptw_fifo[11:0] <= jtlb_xx_fifo[11:0];
ptw_type[2:0] <= jtlb_ptw_type[2:0];
end
end
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lsu_data_flop[58:0] <= 59'b0;
else if(lsu_mmu_data_vld)
lsu_data_flop[58:0] <= lsu_mmu_data[58:0];
else if(ptw_crs2_1g && ptw_chk_cross)
lsu_data_flop[58:0] <= {lsu_data_flop[58:PPN_WIDTH], ptw_vpn[17:9], lsu_data_flop[18:0]};
else if(ptw_crs2_2m && ptw_chk_cross)
lsu_data_flop[58:0] <= {lsu_data_flop[58:PPN_WIDTH-9], ptw_vpn[8:0], lsu_data_flop[9:0]};
end
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
lsu_data_flop[63:59] <= 5'b0;
else if(lsu_mmu_data_vld)
lsu_data_flop[63:59] <= lsu_mmu_data[63:59];
end
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ptw_req_addr[PADDR_WIDTH-1:0] <= {PADDR_WIDTH{1'b0}};
else if(ptw_addr_fst || lsu_mmu_data_vld)
ptw_req_addr[PADDR_WIDTH-1:0] <= ptw_req_addr_pre[PADDR_WIDTH-1:0];
else if(ptw_leaf_vld)
ptw_req_addr[PADDR_WIDTH-1:0] <= {lsu_data_flop[PPN_WIDTH+9:10], 12'b0};
else if(ptw_crs1_1g)
ptw_req_addr[PADDR_WIDTH-1:0] <= {lsu_data_flop[PPN_WIDTH+9:PPN_WIDTH], 18'h3ffff, 12'b0};
else if(ptw_crs2_1g && ptw_chk_cross)
ptw_req_addr[PADDR_WIDTH-1:0] <= {lsu_data_flop[PPN_WIDTH+9:PPN_WIDTH], ptw_vpn[17:9], 21'b0};
else if(ptw_crs1_2m)
ptw_req_addr[PADDR_WIDTH-1:0] <= {lsu_data_flop[PPN_WIDTH+9:PPN_WIDTH-9], 9'h1ff, 12'b0};
else if(ptw_crs2_2m && ptw_chk_cross)
ptw_req_addr[PADDR_WIDTH-1:0] <= {lsu_data_flop[PPN_WIDTH+9:PPN_WIDTH-9], ptw_vpn[8:0], 12'b0};
end
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ref_pgs[PGS_WIDTH-1:0] <= {PGS_WIDTH{1'b0}};
else if(ptw_leaf_vld)
ref_pgs[PGS_WIDTH-1:0] <= {ptw_hit_1g, ptw_hit_2m, ptw_chk_thd};
else if(ptw_crs2_1g && ptw_chk_cross)
ref_pgs[PGS_WIDTH-1:0] <= 3'b010;
else if(ptw_crs2_2m && ptw_chk_cross)
ref_pgs[PGS_WIDTH-1:0] <= 3'b001;
end
assign ptw_fst_addr[PADDR_WIDTH-1:0] = {regs_ptw_satp_ppn[PPN_WIDTH-1:0],
ptw_refill_on ? ptw_vpn[VPN_WIDTH-1:VPN_PERLEL*2] :
jtlb_ptw_vpn[VPN_WIDTH-1:VPN_PERLEL*2], 3'b0};
assign ptw_scd_addr[PADDR_WIDTH-1:0] = {lsu_mmu_data[PPN_WIDTH+9:10],
ptw_vpn[VPN_PERLEL*2-1:VPN_PERLEL*1], 3'b0};
assign ptw_thd_addr[PADDR_WIDTH-1:0] = {lsu_mmu_data[PPN_WIDTH+9:10],
ptw_vpn[VPN_PERLEL*1-1:VPN_PERLEL*0], 3'b0};
assign ptw_req_addr_pre[PADDR_WIDTH-1:0] =
{PADDR_WIDTH{ptw_addr_fst}} & ptw_fst_addr[PADDR_WIDTH-1:0]
| {PADDR_WIDTH{ptw_addr_scd}} & ptw_scd_addr[PADDR_WIDTH-1:0]
| {PADDR_WIDTH{ptw_addr_thd}} & ptw_thd_addr[PADDR_WIDTH-1:0];
// ptw flag
assign ptw_flg[8:0] = {lsu_data_flop[9:6], lsu_data_flop[4:0]};
// judge if hit huge page
assign ptw_hit_1g = ptw_chk_fst && ptw_flg[0] && (ptw_flg[1] || ptw_flg[3]);
assign ptw_hit_2m = ptw_chk_scd && ptw_flg[0] && (ptw_flg[1] || ptw_flg[3]);
// judge if access fault
// access error when lsu bus error
// access error when pmp check deny
// &Force("bus", "pmp_mmu_flg3", 3, 0) @396
assign ptw_pmp_deny = (ptw_fetch_type && !pmp_mmu_flg3[2]
|| ptw_load_type && !pmp_mmu_flg3[0]
|| ptw_store_type && !pmp_mmu_flg3[1]
|| ptw_pref_type && !pmp_mmu_flg3[0])
// L-bit for M-Mode
&& !(cp0_mach_mode && !pmp_mmu_flg3[3]);
assign ptw_leaf_vld = (ptw_hit_1g || ptw_hit_2m || ptw_chk_thd);
// judge if page fault
// page fault when PTE not valid
// page fault when PTE write only
// page fault when not match R/W/X
// page fault when supv access user region and vise versa
// page fault when A/D bit violation
// page fault when fetch meets strong order
// page fault when third request no R/X
// page fault when huge page misalign
assign ptw_fetch_type = ptw_type[2:0] == 3'b011;
assign ptw_load_type = ptw_type[2:0] == 3'b010;
assign ptw_store_type = ptw_type[2:0] == 3'b110;
assign ptw_pref_type = ptw_type[2:0] == 3'b100;
assign ptw_page_flt = ((!ptw_flg[0] // not valid
|| !(ptw_flg[1] || cp0_mmu_mxr && ptw_flg[3])
&& ptw_flg[2] // write only
|| (!ptw_flg[1] && ptw_load_type // match R
&& !(cp0_mmu_mxr && ptw_flg[3])
|| !ptw_flg[2] && ptw_store_type // match W
|| !ptw_flg[3] && ptw_fetch_type // match X
|| ptw_flg[4] && cp0_supv_mode && !cp0_mmu_sum // S->U
|| !ptw_flg[4] && cp0_user_mode // U->S
|| !ptw_flg[5] // A bit volation
|| !ptw_flg[6] && ptw_store_type // D bit volation
// || ptw_flg[13] && ptw_fetch_type // fetch so
|| ptw_hit_1g && lsu_data_flop[27:10] != 18'b0 // 1g align
|| ptw_hit_2m && lsu_data_flop[18:10] != 9'b0 // 2m align
) && ptw_leaf_vld)
|| !ptw_flg[1] && !ptw_flg[3] // thd req no R/X
&& ptw_chk_thd);
// access cross when:
// sysmap check 2 and hit num not match
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
ptw_hit_num[7:0] <= 8'b0;
else if(ptw_crs1_1g || ptw_crs1_2m)
ptw_hit_num[7:0] <= sysmap_mmu_hit3[7:0];
end
assign ptw_chk_cross = ptw_crs2_chk && ptw_hit_num[7:0] != sysmap_mmu_hit3[7:0];
// response to jtlb refill
assign ptw_ref_cmplt = (ptw_cur_st[4:0] == PTW_ACC_FLT)
|| (ptw_cur_st[4:0] == PTW_PGE_FLT)
|| (ptw_cur_st[4:0] == PTW_DATA_VLD) && arb_ptw_grant;
assign ptw_ref_data_vld = (ptw_cur_st[4:0] == PTW_DATA_VLD) && !tlboper_ptw_abort;
assign ptw_ref_acc_err = (ptw_cur_st[4:0] == PTW_ACC_FLT);
assign ptw_ref_pgflt = (ptw_cur_st[4:0] == PTW_PGE_FLT);
assign ptw_ref_pma[4:0] = cp0_mmu_maee ? lsu_data_flop[63:59]
: sysmap_mmu_flg3[4:0];
assign ptw_ref_vpn[VPN_WIDTH-1:0] =
{VPN_WIDTH{ref_pgs[2]}} & {ptw_vpn[26:18], 18'b0}
| {VPN_WIDTH{ref_pgs[1]}} & {ptw_vpn[26:9], 9'b0}
| {VPN_WIDTH{ref_pgs[0]}} & ptw_vpn[26:0];
assign ptw_ref_ppn[PPN_WIDTH-1:0] = lsu_data_flop[PPN_WIDTH+9:10];
assign ptw_ref_flg[FLG_WIDTH-1:0] = {ptw_ref_pma[4:0], lsu_data_flop[9:6],
lsu_data_flop[4:0]};
assign ptw_ref_pgs[PGS_WIDTH-1:0] = ref_pgs[PGS_WIDTH-1:0];
assign ptw_ref_g = lsu_data_flop[5];
assign ptw_ref_fifo[3:0] = {4{ref_pgs[0]}} & ptw_fifo[3:0]
| {4{ref_pgs[1]}} & ptw_fifo[7:4]
| {4{ref_pgs[2]}} & ptw_fifo[11:8];
// for hpcp
//assign jtlb_miss_cnt = (ptw_cur_st[3:0] == PTW_IDLE) && (ptw_nxt_st[3:0] != PTW_IDLE)
// && hpcp_mmu_cnt_en;
//assign jtlb_miss_cnt = ptw_ref_cmplt && hpcp_mmu_cnt_en;
assign jtlb_miss_cnt = ((ptw_load_type || ptw_store_type) && dutlb_ptw_wfc
|| ptw_fetch_type && iutlb_ptw_wfc)
&& ptw_ref_data_vld && hpcp_mmu_cnt_en;
always @(posedge ptw_clk or negedge cpurst_b)
begin
if (!cpurst_b)
jtlb_miss <= 1'b0;
else if(jtlb_miss_cnt)
jtlb_miss <= 1'b1;
else if(jtlb_miss)
jtlb_miss <= 1'b0;
end
assign mmu_hpcp_jtlb_miss = jtlb_miss;
//==========================================================
// Interface to SysMap
//==========================================================
assign mmu_sysmap_pa3[PPN_WIDTH-1:0] = ptw_req_addr[PPN_WIDTH+11:12];
//==========================================================
// Interface to PMP
//==========================================================
assign mmu_pmp_pa3[PPN_WIDTH-1:0] = ptw_req_addr[PPN_WIDTH+11:12];
assign mmu_pmp_fetch3 = ptw_fetch_type;
//==========================================================
// Interface to LSU
//==========================================================
assign mmu_lsu_data_req = ptw_data_req;
assign mmu_lsu_data_req_addr[PADDR_WIDTH-1:0] = ptw_req_addr[PADDR_WIDTH-1:0];
assign mmu_lsu_data_req_size = 1'b1;
//==========================================================
// Interface to jTLB
//==========================================================
assign ptw_jtlb_ref_cmplt = ptw_ref_cmplt;
assign ptw_jtlb_imiss = ptw_fetch_type;
assign ptw_jtlb_dmiss = ptw_load_type || ptw_store_type;
assign ptw_jtlb_pmiss = ptw_pref_type;
assign ptw_jtlb_ref_data_vld = ptw_ref_data_vld && arb_ptw_grant;
assign ptw_jtlb_ref_acc_err = ptw_ref_acc_err;
assign ptw_jtlb_ref_pgflt = ptw_ref_pgflt;
assign ptw_jtlb_ref_ppn[PPN_WIDTH-1:0] = ptw_ref_ppn[PPN_WIDTH-1:0];
assign ptw_jtlb_ref_pgs[PGS_WIDTH-1:0] = ptw_ref_pgs[PGS_WIDTH-1:0];
assign ptw_jtlb_ref_flg[FLG_WIDTH-1:0] = ptw_ref_flg[FLG_WIDTH-1:0];
//==========================================================
// Interface to arb
//==========================================================
assign ptw_arb_req = ptw_ref_data_vld && !arb_ptw_mask;
assign ptw_arb_bank_sel[3:0] = ptw_ref_fifo[3:0];
assign ptw_arb_vpn[VPN_WIDTH-1:0] = ptw_ref_vpn[VPN_WIDTH-1:0];
assign ptw_arb_pgs[PGS_WIDTH-1:0] = ptw_ref_pgs[PGS_WIDTH-1:0];
assign ptw_arb_fifo_din[3:0] = {ptw_ref_fifo[2:0], ptw_ref_fifo[3]};
assign ptw_arb_tag_din[TAG_WIDTH-1:0] = {1'b1, ptw_ref_vpn[VPN_WIDTH-1:0],
regs_ptw_cur_asid[ASID_WIDTH-1:0],
ptw_ref_pgs[PGS_WIDTH-1:0], ptw_ref_g};
assign ptw_arb_data_din[DATA_WIDTH-1:0] = {ptw_ref_ppn[PPN_WIDTH-1:0],
ptw_ref_flg[FLG_WIDTH-1:0]};
// for dbg
assign ptw_top_cur_st[3:0] = ptw_cur_st[3:0];
assign ptw_top_imiss = ptw_fetch_type;
// &ModuleEnd; @554
endmodule |
module ct_mmu_dutlb_read(
biu_mmu_smp_disable,
cp0_mach_mode,
cp0_mmu_icg_en,
cp0_mmu_mxr,
cp0_mmu_sum,
cp0_supv_mode,
cp0_user_mode,
cpurst_b,
dplru_clk,
dutlb_acc_flt_x,
dutlb_clk,
dutlb_expt_for_taken,
dutlb_inst_id_match_x,
dutlb_inst_id_older_x,
dutlb_miss_vld_short_x,
dutlb_miss_vld_x,
dutlb_off_hit,
dutlb_ori_read_x,
dutlb_plru_read_hit_vld_x,
dutlb_plru_read_hit_x,
dutlb_read_type_x,
dutlb_ref_acflt,
dutlb_ref_pgflt,
dutlb_refill_on_x,
dutlb_va_chg_x,
entry0_flg,
entry0_hit_x,
entry0_ppn,
entry0_vld,
entry10_flg,
entry10_hit_x,
entry10_ppn,
entry10_vld,
entry11_flg,
entry11_hit_x,
entry11_ppn,
entry11_vld,
entry12_flg,
entry12_hit_x,
entry12_ppn,
entry12_vld,
entry13_flg,
entry13_hit_x,
entry13_ppn,
entry13_vld,
entry14_flg,
entry14_hit_x,
entry14_ppn,
entry14_vld,
entry15_flg,
entry15_hit_x,
entry15_ppn,
entry15_vld,
entry16_flg,
entry16_hit_x,
entry16_ppn,
entry16_vld,
entry1_flg,
entry1_hit_x,
entry1_ppn,
entry1_vld,
entry2_flg,
entry2_hit_x,
entry2_ppn,
entry2_vld,
entry3_flg,
entry3_hit_x,
entry3_ppn,
entry3_vld,
entry4_flg,
entry4_hit_x,
entry4_ppn,
entry4_vld,
entry5_flg,
entry5_hit_x,
entry5_ppn,
entry5_vld,
entry6_flg,
entry6_hit_x,
entry6_ppn,
entry6_vld,
entry7_flg,
entry7_hit_x,
entry7_ppn,
entry7_vld,
entry8_flg,
entry8_hit_x,
entry8_ppn,
entry8_vld,
entry9_flg,
entry9_hit_x,
entry9_ppn,
entry9_vld,
forever_cpuclk,
lsu_mmu_abort_x,
lsu_mmu_id_x,
lsu_mmu_stamo_pa_x,
lsu_mmu_stamo_vld_x,
lsu_mmu_va_vld_x,
lsu_mmu_va_x,
lsu_mmu_vabuf_x,
mmu_lsu_access_fault_x,
mmu_lsu_buf_x,
mmu_lsu_ca_x,
mmu_lsu_pa_vld_x,
mmu_lsu_pa_x,
mmu_lsu_page_fault_x,
mmu_lsu_sec_x,
mmu_lsu_sh_x,
mmu_lsu_so_x,
mmu_lsu_stall_x,
mmu_pmp_pa_x,
mmu_sysmap_pa_x,
pad_yy_icg_scan_en,
pmp_mmu_flg_x,
refill_id_flop,
sysmap_mmu_flg_x,
utlb_req_vpn_x
);
// &Ports; @24
input biu_mmu_smp_disable;
input cp0_mach_mode;
input cp0_mmu_icg_en;
input cp0_mmu_mxr;
input cp0_mmu_sum;
input cp0_supv_mode;
input cp0_user_mode;
input cpurst_b;
input dplru_clk;
input dutlb_clk;
input dutlb_expt_for_taken;
input dutlb_off_hit;
input dutlb_ori_read_x;
input dutlb_read_type_x;
input dutlb_ref_acflt;
input dutlb_ref_pgflt;
input dutlb_refill_on_x;
input [13:0] entry0_flg;
input entry0_hit_x;
input [27:0] entry0_ppn;
input entry0_vld;
input [13:0] entry10_flg;
input entry10_hit_x;
input [27:0] entry10_ppn;
input entry10_vld;
input [13:0] entry11_flg;
input entry11_hit_x;
input [27:0] entry11_ppn;
input entry11_vld;
input [13:0] entry12_flg;
input entry12_hit_x;
input [27:0] entry12_ppn;
input entry12_vld;
input [13:0] entry13_flg;
input entry13_hit_x;
input [27:0] entry13_ppn;
input entry13_vld;
input [13:0] entry14_flg;
input entry14_hit_x;
input [27:0] entry14_ppn;
input entry14_vld;
input [13:0] entry15_flg;
input entry15_hit_x;
input [27:0] entry15_ppn;
input entry15_vld;
input [13:0] entry16_flg;
input entry16_hit_x;
input [27:0] entry16_ppn;
input entry16_vld;
input [13:0] entry1_flg;
input entry1_hit_x;
input [27:0] entry1_ppn;
input entry1_vld;
input [13:0] entry2_flg;
input entry2_hit_x;
input [27:0] entry2_ppn;
input entry2_vld;
input [13:0] entry3_flg;
input entry3_hit_x;
input [27:0] entry3_ppn;
input entry3_vld;
input [13:0] entry4_flg;
input entry4_hit_x;
input [27:0] entry4_ppn;
input entry4_vld;
input [13:0] entry5_flg;
input entry5_hit_x;
input [27:0] entry5_ppn;
input entry5_vld;
input [13:0] entry6_flg;
input entry6_hit_x;
input [27:0] entry6_ppn;
input entry6_vld;
input [13:0] entry7_flg;
input entry7_hit_x;
input [27:0] entry7_ppn;
input entry7_vld;
input [13:0] entry8_flg;
input entry8_hit_x;
input [27:0] entry8_ppn;
input entry8_vld;
input [13:0] entry9_flg;
input entry9_hit_x;
input [27:0] entry9_ppn;
input entry9_vld;
input forever_cpuclk;
input lsu_mmu_abort_x;
input [6 :0] lsu_mmu_id_x;
input [27:0] lsu_mmu_stamo_pa_x;
input lsu_mmu_stamo_vld_x;
input lsu_mmu_va_vld_x;
input [63:0] lsu_mmu_va_x;
input [27:0] lsu_mmu_vabuf_x;
input pad_yy_icg_scan_en;
input [3 :0] pmp_mmu_flg_x;
input [6 :0] refill_id_flop;
input [4 :0] sysmap_mmu_flg_x;
output dutlb_acc_flt_x;
output dutlb_inst_id_match_x;
output dutlb_inst_id_older_x;
output dutlb_miss_vld_short_x;
output dutlb_miss_vld_x;
output dutlb_plru_read_hit_vld_x;
output [15:0] dutlb_plru_read_hit_x;
output dutlb_va_chg_x;
output mmu_lsu_access_fault_x;
output mmu_lsu_buf_x;
output mmu_lsu_ca_x;
output mmu_lsu_pa_vld_x;
output [27:0] mmu_lsu_pa_x;
output mmu_lsu_page_fault_x;
output mmu_lsu_sec_x;
output mmu_lsu_sh_x;
output mmu_lsu_so_x;
output mmu_lsu_stall_x;
output [27:0] mmu_pmp_pa_x;
output [27:0] mmu_sysmap_pa_x;
output [26:0] utlb_req_vpn_x;
// &Regs; @25
reg [13:0] dutlb_entry_flg;
reg [27:0] dutlb_entry_pa;
reg [27:0] dutlb_pa_buf;
reg [15:0] dutlb_plru_read_hit_x;
reg jtlb_acc_fault_flop;
reg pmp_flg_vld;
reg pmp_read_type;
// &Wires; @26
wire biu_mmu_smp_disable;
wire cp0_mach_mode;
wire cp0_mmu_icg_en;
wire cp0_mmu_mxr;
wire cp0_mmu_sum;
wire cp0_supv_mode;
wire cp0_user_mode;
wire cpurst_b;
wire dplru_clk;
wire dutlb_acc_flt_x;
wire dutlb_addr_hit;
wire dutlb_clk;
wire dutlb_disable_vld;
wire [16:0] dutlb_entry_hit;
wire dutlb_entry_hit_vld;
wire dutlb_expt_for_taken;
wire dutlb_expt_match;
wire [13:0] dutlb_fin_flg;
wire [27:0] dutlb_fin_pa;
wire [2 :0] dutlb_fin_pgs;
wire dutlb_hit_vld;
wire dutlb_inst_id_hit;
wire dutlb_inst_id_match_x;
wire dutlb_inst_id_older_x;
wire dutlb_miss_vld_short_x;
wire dutlb_miss_vld_x;
wire [13:0] dutlb_off_flg;
wire dutlb_off_hit;
wire [27:0] dutlb_off_pa;
wire [2 :0] dutlb_off_pgs;
wire dutlb_ori_read_x;
wire dutlb_page_fault;
wire dutlb_plru_read_hit_vld_x;
wire dutlb_pmp_chk_vld;
wire [13:0] dutlb_pre_flg;
wire [27:0] dutlb_pre_pa;
wire [2 :0] dutlb_pre_pgs;
wire dutlb_pre_sel;
wire dutlb_read_type_x;
wire dutlb_ref_acflt;
wire dutlb_ref_pgflt;
wire dutlb_refill_on_x;
wire dutlb_req_id_older;
wire dutlb_va_chg_x;
wire dutlb_va_illegal;
wire [13:0] entry0_flg;
wire entry0_hit_x;
wire [27:0] entry0_ppn;
wire entry0_vld;
wire [13:0] entry10_flg;
wire entry10_hit_x;
wire [27:0] entry10_ppn;
wire entry10_vld;
wire [13:0] entry11_flg;
wire entry11_hit_x;
wire [27:0] entry11_ppn;
wire entry11_vld;
wire [13:0] entry12_flg;
wire entry12_hit_x;
wire [27:0] entry12_ppn;
wire entry12_vld;
wire [13:0] entry13_flg;
wire entry13_hit_x;
wire [27:0] entry13_ppn;
wire entry13_vld;
wire [13:0] entry14_flg;
wire entry14_hit_x;
wire [27:0] entry14_ppn;
wire entry14_vld;
wire [13:0] entry15_flg;
wire entry15_hit_x;
wire [27:0] entry15_ppn;
wire entry15_vld;
wire [13:0] entry16_flg;
wire entry16_hit_x;
wire [27:0] entry16_ppn;
wire entry16_vld;
wire [13:0] entry1_flg;
wire entry1_hit_x;
wire [27:0] entry1_ppn;
wire entry1_vld;
wire [13:0] entry2_flg;
wire entry2_hit_x;
wire [27:0] entry2_ppn;
wire entry2_vld;
wire [13:0] entry3_flg;
wire entry3_hit_x;
wire [27:0] entry3_ppn;
wire entry3_vld;
wire [13:0] entry4_flg;
wire entry4_hit_x;
wire [27:0] entry4_ppn;
wire entry4_vld;
wire [13:0] entry5_flg;
wire entry5_hit_x;
wire [27:0] entry5_ppn;
wire entry5_vld;
wire [13:0] entry6_flg;
wire entry6_hit_x;
wire [27:0] entry6_ppn;
wire entry6_vld;
wire [13:0] entry7_flg;
wire entry7_hit_x;
wire [27:0] entry7_ppn;
wire entry7_vld;
wire [13:0] entry8_flg;
wire entry8_hit_x;
wire [27:0] entry8_ppn;
wire entry8_vld;
wire [13:0] entry9_flg;
wire entry9_hit_x;
wire [27:0] entry9_ppn;
wire entry9_vld;
wire forever_cpuclk;
wire jtlb_acc_fault;
wire lsu_mmu_abort_x;
wire [6 :0] lsu_mmu_id_x;
wire [27:0] lsu_mmu_stamo_pa_x;
wire lsu_mmu_stamo_vld_x;
wire lsu_mmu_va_vld_x;
wire [63:0] lsu_mmu_va_x;
wire lsu_va_chg;
wire mmu_lsu_access_fault_x;
wire mmu_lsu_buf_x;
wire mmu_lsu_ca_x;
wire mmu_lsu_pa_vld_x;
wire [27:0] mmu_lsu_pa_x;
wire mmu_lsu_page_fault_x;
wire [2 :0] mmu_lsu_page_size_x;
wire mmu_lsu_sec_x;
wire mmu_lsu_sh_x;
wire mmu_lsu_so_x;
wire mmu_lsu_stall_x;
wire [27:0] mmu_pmp_pa_x;
wire [27:0] mmu_sysmap_pa_x;
wire [17:0] pa_offset;
wire pabuf_clk;
wire pabuf_clk_en;
wire pad_yy_icg_scan_en;
wire [3 :0] pmp_mmu_flg_x;
wire [6 :0] refill_id_flop;
wire [4 :0] sysmap_mmu_flg_x;
wire [26:0] utlb_req_vpn_x;
wire [16:0] vpn_hit;
wire [16:0] vpn_vld;
parameter VPN_WIDTH = 39-12; // VPN
parameter PPN_WIDTH = 40-12; // PPN
parameter FLG_WIDTH = 14; // Flags
parameter PGS_WIDTH = 3; // Page Size
parameter VPN_PERLEL = 9;
//==========================================================
// Tranlation Related Signal
//==========================================================
//----------------------------------------------------------
// Addr Translation Cmplt
//----------------------------------------------------------
// 1. when utlb hit, return pvald to LSU
// 2. later utlb hit can bypass the previous utlb miss, but
// later utlb miss must be blocking
assign dutlb_hit_vld = lsu_mmu_va_vld_x && dutlb_addr_hit;
// D-uTLB trans cmplt without addr match in utlb:
// 1. when mmu is not enabled
// 2. when cpu is in machine mode
assign dutlb_disable_vld = lsu_mmu_va_vld_x && dutlb_off_hit;
//----------------------------------------------------------
// Interface to LSU
//----------------------------------------------------------
// Paddr is valid when:
// 1. utlb hit
// 2. mmu is disabled
// 4. expt happened when utlb refill and inst id match
assign mmu_lsu_pa_vld_x = dutlb_hit_vld
|| dutlb_disable_vld
|| dutlb_va_illegal
|| dutlb_expt_match;
assign mmu_lsu_stall_x = 1'b0;
assign mmu_lsu_pa_x[PPN_WIDTH-1:0] = dutlb_fin_pa[PPN_WIDTH-1:0];
// &Force("nonport", "mmu_lsu_page_size_x"); @64
assign mmu_lsu_page_size_x[PGS_WIDTH-1:0] = dutlb_fin_pgs[PGS_WIDTH-1:0];
// flags judgement
// pmas to lsu: bufferable, security, cacheable
assign mmu_lsu_sh_x = dutlb_fin_flg[10] && !biu_mmu_smp_disable;
assign mmu_lsu_buf_x = dutlb_fin_flg[11]
|| !dutlb_fin_flg[13]; //when !so, always buf
assign mmu_lsu_so_x = dutlb_fin_flg[13];
assign mmu_lsu_sec_x = dutlb_fin_flg[9];
assign mmu_lsu_ca_x = dutlb_fin_flg[12] && !dutlb_fin_flg[13];
// R W X judgement, R and W are not used in I-uTLB
// page fault when not valid
// page fault when writeable but not readable
// page fault when load/store not match R/W
// page fault when supv access user region and vise versa
// page fault when A/D bit violation
// page fault when tfatal and tmiss from jTLB
// page fault when virtual address not legal
// &Force("bus", "lsu_mmu_va_x", 63, 0); @84
assign dutlb_va_illegal = (lsu_mmu_va_x[VPN_WIDTH+11] && !(&lsu_mmu_va_x[63:VPN_WIDTH+12])
|| !lsu_mmu_va_x[VPN_WIDTH+11] && (|lsu_mmu_va_x[63:VPN_WIDTH+12]))
&& !dutlb_off_hit && lsu_mmu_va_vld_x;
assign dutlb_page_fault = (!dutlb_fin_flg[0]
|| !dutlb_fin_flg[1] && dutlb_fin_flg[2]
|| !dutlb_fin_flg[1] && dutlb_read_type_x
&& !(cp0_mmu_mxr && dutlb_fin_flg[3])
|| !dutlb_fin_flg[2] && !dutlb_read_type_x
|| dutlb_fin_flg[4] && cp0_supv_mode && !cp0_mmu_sum
|| !dutlb_fin_flg[4] && cp0_user_mode
|| !dutlb_fin_flg[5]
|| !dutlb_fin_flg[6] && !dutlb_read_type_x)
&& dutlb_addr_hit
|| dutlb_ref_pgflt && dutlb_refill_on_x
&& dutlb_inst_id_hit
|| dutlb_va_illegal;
assign mmu_lsu_page_fault_x = dutlb_page_fault && !dutlb_off_hit;
// &Force("bus", "pmp_mmu_flg_x", 3, 0); @103
assign mmu_lsu_access_fault_x = jtlb_acc_fault_flop
|| !pmp_mmu_flg_x[0] && (pmp_read_type || dutlb_ori_read_x)
&& !(cp0_mach_mode && !pmp_mmu_flg_x[3]) // L-bit for M-Mode
&& pmp_flg_vld
|| !pmp_mmu_flg_x[1] && !pmp_read_type
&& !(cp0_mach_mode && !pmp_mmu_flg_x[3]) // L-bit for M-Mode
&& pmp_flg_vld;
//assign mmu_lsu_access_fault_short_x = jtlb_acc_fault_flop || !pmp_mmu_flg_x[0]
// || !pmp_mmu_flg_x[1];
assign dutlb_acc_flt_x = jtlb_acc_fault_flop;
always @(posedge dplru_clk or negedge cpurst_b)
begin
if (!cpurst_b)
dutlb_plru_read_hit_x[15:0] <= 16'b0;
else if(lsu_mmu_va_vld_x)
dutlb_plru_read_hit_x[15:0] <= dutlb_entry_hit[15:0];
end
// &Force("output", "dutlb_plru_read_hit_x"); @124
assign dutlb_plru_read_hit_vld_x = |dutlb_plru_read_hit_x[15:0];
assign dutlb_miss_vld_x = lsu_mmu_va_vld_x
&& !dutlb_entry_hit_vld
&& !dutlb_va_illegal
&& !lsu_mmu_abort_x
&& !dutlb_off_hit;
assign dutlb_miss_vld_short_x = lsu_mmu_va_vld_x
&& !dutlb_entry_hit_vld
&& !dutlb_va_illegal
&& !dutlb_off_hit;
// &Force("output", "dutlb_inst_id_match_x"); @137
assign dutlb_inst_id_hit = (refill_id_flop[6:0] == lsu_mmu_id_x[6:0])
&& lsu_mmu_va_vld_x;
assign dutlb_inst_id_match_x = dutlb_inst_id_hit && !lsu_mmu_abort_x;
// &Instance("ct_rtu_compare_iid","x_mmu_dutlb_read_compare_req_iid"); @142
ct_rtu_compare_iid x_mmu_dutlb_read_compare_req_iid (
.x_iid0 (lsu_mmu_id_x[6:0] ),
.x_iid0_older (dutlb_req_id_older ),
.x_iid1 (refill_id_flop[6:0])
);
// &Connect( .x_iid0 (lsu_mmu_id_x[6:0]), @143
// .x_iid1 (refill_id_flop[6:0]), @144
// .x_iid0_older (dutlb_req_id_older)); @145
assign dutlb_inst_id_older_x = dutlb_req_id_older && lsu_mmu_va_vld_x
&& !lsu_mmu_abort_x;
assign dutlb_expt_match = dutlb_expt_for_taken && dutlb_inst_id_hit;
//==============================================================================
// Data Path
//==============================================================================
//==========================================================
// VA Matching
//==========================================================
//----------------------------------------------------------
// uTLB Entry Matching
//----------------------------------------------------------
assign vpn_vld[16:0] = {entry16_vld,
entry15_vld, entry14_vld, entry13_vld, entry12_vld,
entry11_vld, entry10_vld, entry9_vld, entry8_vld,
entry7_vld, entry6_vld, entry5_vld, entry4_vld,
entry3_vld, entry2_vld, entry1_vld, entry0_vld};
assign vpn_hit[16:0] ={entry16_hit_x, entry15_hit_x, entry14_hit_x, entry13_hit_x, entry12_hit_x,
entry11_hit_x, entry10_hit_x, entry9_hit_x, entry8_hit_x,
entry7_hit_x, entry6_hit_x, entry5_hit_x, entry4_hit_x,
entry3_hit_x, entry2_hit_x, entry1_hit_x, entry0_hit_x};
assign dutlb_entry_hit[16:0] = vpn_vld[16:0] & vpn_hit[16:0];
assign dutlb_entry_hit_vld = |dutlb_entry_hit[16:0];
assign dutlb_addr_hit = |dutlb_entry_hit[16:0];
//assign dutlb_entry_hit_x[15:0] = dutlb_entry_hit[15:0];
//==========================================================
// VA Matching
//==========================================================
//----------------------------------------------------------
// Selecting Info from uTLB
//----------------------------------------------------------
// &CombBeg; @185
always @( entry4_ppn[27:0]
or entry1_ppn[27:0]
or entry8_ppn[27:0]
or dutlb_entry_hit[15:0]
or entry13_ppn[27:0]
or entry7_ppn[27:0]
or entry10_ppn[27:0]
or entry11_ppn[27:0]
or entry0_ppn[27:0]
or entry2_ppn[27:0]
or entry3_ppn[27:0]
or entry6_ppn[27:0]
or entry5_ppn[27:0]
or entry14_ppn[27:0]
or entry15_ppn[27:0]
or entry9_ppn[27:0]
or entry12_ppn[27:0])
begin
case(dutlb_entry_hit[15:0])
16'b0000000000000001: dutlb_entry_pa[PPN_WIDTH-1:0] = entry0_ppn[PPN_WIDTH-1:0];
16'b0000000000000010: dutlb_entry_pa[PPN_WIDTH-1:0] = entry1_ppn[PPN_WIDTH-1:0];
16'b0000000000000100: dutlb_entry_pa[PPN_WIDTH-1:0] = entry2_ppn[PPN_WIDTH-1:0];
16'b0000000000001000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry3_ppn[PPN_WIDTH-1:0];
16'b0000000000010000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry4_ppn[PPN_WIDTH-1:0];
16'b0000000000100000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry5_ppn[PPN_WIDTH-1:0];
16'b0000000001000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry6_ppn[PPN_WIDTH-1:0];
16'b0000000010000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry7_ppn[PPN_WIDTH-1:0];
16'b0000000100000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry8_ppn[PPN_WIDTH-1:0];
16'b0000001000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry9_ppn[PPN_WIDTH-1:0];
16'b0000010000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry10_ppn[PPN_WIDTH-1:0];
16'b0000100000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry11_ppn[PPN_WIDTH-1:0];
16'b0001000000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry12_ppn[PPN_WIDTH-1:0];
16'b0010000000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry13_ppn[PPN_WIDTH-1:0];
16'b0100000000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry14_ppn[PPN_WIDTH-1:0];
16'b1000000000000000: dutlb_entry_pa[PPN_WIDTH-1:0] = entry15_ppn[PPN_WIDTH-1:0];
default: dutlb_entry_pa[PPN_WIDTH-1:0] = {PPN_WIDTH{1'b0}};
endcase
// &CombEnd; @205
end
// &CombBeg; @206
always @( entry5_flg[13:0]
or entry2_flg[13:0]
or dutlb_entry_hit[15:0]
or entry9_flg[13:0]
or entry14_flg[13:0]
or entry12_flg[13:0]
or entry13_flg[13:0]
or entry6_flg[13:0]
or entry1_flg[13:0]
or entry10_flg[13:0]
or entry11_flg[13:0]
or entry7_flg[13:0]
or entry15_flg[13:0]
or entry0_flg[13:0]
or entry4_flg[13:0]
or entry3_flg[13:0]
or entry8_flg[13:0])
begin
case(dutlb_entry_hit[15:0])
16'b0000000000000001: dutlb_entry_flg[FLG_WIDTH-1:0] = entry0_flg[FLG_WIDTH-1:0];
16'b0000000000000010: dutlb_entry_flg[FLG_WIDTH-1:0] = entry1_flg[FLG_WIDTH-1:0];
16'b0000000000000100: dutlb_entry_flg[FLG_WIDTH-1:0] = entry2_flg[FLG_WIDTH-1:0];
16'b0000000000001000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry3_flg[FLG_WIDTH-1:0];
16'b0000000000010000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry4_flg[FLG_WIDTH-1:0];
16'b0000000000100000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry5_flg[FLG_WIDTH-1:0];
16'b0000000001000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry6_flg[FLG_WIDTH-1:0];
16'b0000000010000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry7_flg[FLG_WIDTH-1:0];
16'b0000000100000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry8_flg[FLG_WIDTH-1:0];
16'b0000001000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry9_flg[FLG_WIDTH-1:0];
16'b0000010000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry10_flg[FLG_WIDTH-1:0];
16'b0000100000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry11_flg[FLG_WIDTH-1:0];
16'b0001000000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry12_flg[FLG_WIDTH-1:0];
16'b0010000000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry13_flg[FLG_WIDTH-1:0];
16'b0100000000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry14_flg[FLG_WIDTH-1:0];
16'b1000000000000000: dutlb_entry_flg[FLG_WIDTH-1:0] = entry15_flg[FLG_WIDTH-1:0];
default: dutlb_entry_flg[FLG_WIDTH-1:0] = {FLG_WIDTH{1'bx}};
endcase
// &CombEnd; @226
end
// &Force("bus", "entry16_ppn", 27, 0); @228
assign pa_offset[VPN_PERLEL*2-1:0] = lsu_mmu_va_x[VPN_PERLEL*2+11:12];
assign dutlb_pre_pa[PPN_WIDTH-1:0] = lsu_mmu_stamo_vld_x ? lsu_mmu_stamo_pa_x[PPN_WIDTH-1:0]
: dutlb_off_hit || !lsu_mmu_va_vld_x
? dutlb_off_pa[PPN_WIDTH-1:0]
: {entry16_ppn[PPN_WIDTH-1:VPN_PERLEL*2], pa_offset[VPN_PERLEL*2-1:0]};
assign dutlb_pre_flg[FLG_WIDTH-1:0] = dutlb_off_hit || !lsu_mmu_va_vld_x
? dutlb_off_flg[FLG_WIDTH-1:0]
: entry16_flg[FLG_WIDTH-1:0];
assign dutlb_pre_pgs[PGS_WIDTH-1:0] = dutlb_off_hit || !lsu_mmu_va_vld_x
? dutlb_off_pgs[PGS_WIDTH-1:0]
: 3'b100;
// off sel
assign dutlb_pre_sel = dutlb_off_hit || !lsu_mmu_va_vld_x || dutlb_entry_hit[16]
|| dutlb_va_illegal || dutlb_expt_match || lsu_mmu_stamo_vld_x;
// pa and flag when mmu is off
assign dutlb_off_pa[PPN_WIDTH-1:0] = lsu_mmu_va_x[VPN_WIDTH+12:12];
// Sysmap PMA Flags, RSW-zero, Dirty, Access, Non-User, X, W, R, Valid
assign dutlb_off_flg[FLG_WIDTH-1:0] = {sysmap_mmu_flg_x[4:0], 5'b00110, 3'b111, 1'b1};
// page size 4K when mmu is off
assign dutlb_off_pgs[PGS_WIDTH-1:0] = 3'b0;
// off sel
//assign dutlb_hit_sel = dutlb_addr_hit && lsu_mmu_va_vld_x;
assign dutlb_fin_pa[PPN_WIDTH-1:0] =
dutlb_pre_sel ? dutlb_pre_pa[PPN_WIDTH-1:0]
: dutlb_entry_pa[PPN_WIDTH-1:0];
assign dutlb_fin_flg[FLG_WIDTH-1:0] =
dutlb_pre_sel ? dutlb_pre_flg[FLG_WIDTH-1:0]
: dutlb_entry_flg[FLG_WIDTH-1:0];
assign dutlb_fin_pgs[PGS_WIDTH-1:0] =
dutlb_pre_sel ? dutlb_pre_pgs[PGS_WIDTH-1:0]
: 3'b001;
//----------------------------------------------------------
// JTLB Access Fault
//----------------------------------------------------------
// to cut off the timing from dutlb abort to access fault
assign jtlb_acc_fault = dutlb_ref_acflt && dutlb_refill_on_x && dutlb_inst_id_match_x;
always @(posedge dutlb_clk or negedge cpurst_b)
begin
if(!cpurst_b)
jtlb_acc_fault_flop <= 1'b0;
else if(jtlb_acc_fault)
jtlb_acc_fault_flop <= 1'b1;
else
jtlb_acc_fault_flop <= 1'b0;
end
//----------------------------------------------------------
// PMP Check
//----------------------------------------------------------
// to cut off the timing from final-pa to pmp check
// pa buffer clock
// va change signal
// &Force("input", "lsu_mmu_vabuf_x"); @285
// &Force("bus", "lsu_mmu_vabuf_x", 27,0); @286
assign lsu_va_chg = lsu_mmu_va_vld_x;
// && (lsu_mmu_va_x[PPN_WIDTH+11:12] != lsu_mmu_vabuf_x[PPN_WIDTH-1:0]);
assign pabuf_clk_en = lsu_va_chg
|| lsu_mmu_va_vld_x // && (pmp_read_type ^ dutlb_read_type_x)
|| pmp_flg_vld ^ lsu_mmu_va_vld_x;
// &Instance("gated_clk_cell", "x_dutlb_pabuf_gateclk"); @292
gated_clk_cell x_dutlb_pabuf_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (pabuf_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (pabuf_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @293
// .external_en(1'b0 ), @294
// .global_en (1'b1 ), @295
// .module_en (cp0_mmu_icg_en), @296
// .local_en (pabuf_clk_en ), @297
// .clk_out (pabuf_clk ) @298
// ); @299
assign dutlb_pmp_chk_vld = (dutlb_hit_vld || dutlb_disable_vld)
&& !dutlb_page_fault;
always @(posedge pabuf_clk or negedge cpurst_b)
begin
if(!cpurst_b)
pmp_flg_vld <= 1'b0;
else if(dutlb_pmp_chk_vld)
pmp_flg_vld <= 1'b1;
else
pmp_flg_vld <= 1'b0;
end
//assign pmp_flg_vld = 1'b1;
always @(posedge pabuf_clk or negedge cpurst_b)
begin
if(!cpurst_b)
pmp_read_type <= 1'b0;
else if(dutlb_pmp_chk_vld)
pmp_read_type <= dutlb_read_type_x;
end
always @(posedge pabuf_clk)
begin
if(dutlb_pmp_chk_vld)
dutlb_pa_buf[PPN_WIDTH-1:0] <= dutlb_fin_pa[PPN_WIDTH-1:0];
end
assign dutlb_va_chg_x = lsu_va_chg;
assign mmu_pmp_pa_x[PPN_WIDTH-1:0] = dutlb_pa_buf[PPN_WIDTH-1:0];
assign utlb_req_vpn_x[VPN_WIDTH-1:0] = lsu_mmu_va_x[VPN_WIDTH+11:12];
assign mmu_sysmap_pa_x[PPN_WIDTH-1:0] = lsu_mmu_va_x[VPN_WIDTH+12:12];
// &ModuleEnd; @337
endmodule |
module ct_mmu_arb(
arb_dutlb_grant,
arb_iutlb_grant,
arb_jtlb_acc_type,
arb_jtlb_bank_sel,
arb_jtlb_cmp_with_va,
arb_jtlb_data_din,
arb_jtlb_fifo_din,
arb_jtlb_fifo_write,
arb_jtlb_idx,
arb_jtlb_req,
arb_jtlb_tag_din,
arb_jtlb_vpn,
arb_jtlb_write,
arb_ptw_grant,
arb_ptw_mask,
arb_tlboper_grant,
arb_top_cur_st,
arb_top_tlboper_on,
cp0_mmu_icg_en,
cp0_mmu_no_op_req,
cpurst_b,
dutlb_arb_cmplt,
dutlb_arb_load,
dutlb_arb_req,
dutlb_arb_vpn,
dutlb_xx_mmu_off,
forever_cpuclk,
iutlb_arb_cmplt,
iutlb_arb_req,
iutlb_arb_vpn,
jtlb_arb_cmp_va,
jtlb_arb_par_clr,
jtlb_arb_pfu_cmplt,
jtlb_arb_pfu_vpn,
jtlb_arb_sel_1g,
jtlb_arb_sel_2m,
jtlb_arb_sel_4k,
jtlb_arb_tc_miss,
jtlb_arb_type,
jtlb_arb_vpn,
lsu_mmu_va2_vld,
mmu_yy_xx_no_op,
pad_yy_icg_scan_en,
ptw_arb_bank_sel,
ptw_arb_data_din,
ptw_arb_fifo_din,
ptw_arb_pgs,
ptw_arb_req,
ptw_arb_tag_din,
ptw_arb_vpn,
tlboper_arb_bank_sel,
tlboper_arb_cmp_va,
tlboper_arb_data_din,
tlboper_arb_fifo_din,
tlboper_arb_fifo_write,
tlboper_arb_idx,
tlboper_arb_idx_not_va,
tlboper_arb_req,
tlboper_arb_tag_din,
tlboper_arb_vpn,
tlboper_arb_write,
tlboper_xx_cmplt,
tlboper_xx_pgs,
tlboper_xx_pgs_en
);
// &Ports; @29
input cp0_mmu_icg_en;
input cp0_mmu_no_op_req;
input cpurst_b;
input dutlb_arb_cmplt;
input dutlb_arb_load;
input dutlb_arb_req;
input [26:0] dutlb_arb_vpn;
input dutlb_xx_mmu_off;
input forever_cpuclk;
input iutlb_arb_cmplt;
input iutlb_arb_req;
input [26:0] iutlb_arb_vpn;
input jtlb_arb_cmp_va;
input jtlb_arb_par_clr;
input jtlb_arb_pfu_cmplt;
input [26:0] jtlb_arb_pfu_vpn;
input jtlb_arb_sel_1g;
input jtlb_arb_sel_2m;
input jtlb_arb_sel_4k;
input jtlb_arb_tc_miss;
input [2 :0] jtlb_arb_type;
input [26:0] jtlb_arb_vpn;
input lsu_mmu_va2_vld;
input pad_yy_icg_scan_en;
input [3 :0] ptw_arb_bank_sel;
input [41:0] ptw_arb_data_din;
input [3 :0] ptw_arb_fifo_din;
input [2 :0] ptw_arb_pgs;
input ptw_arb_req;
input [47:0] ptw_arb_tag_din;
input [26:0] ptw_arb_vpn;
input [3 :0] tlboper_arb_bank_sel;
input tlboper_arb_cmp_va;
input [41:0] tlboper_arb_data_din;
input [3 :0] tlboper_arb_fifo_din;
input tlboper_arb_fifo_write;
input [8 :0] tlboper_arb_idx;
input tlboper_arb_idx_not_va;
input tlboper_arb_req;
input [47:0] tlboper_arb_tag_din;
input [26:0] tlboper_arb_vpn;
input tlboper_arb_write;
input tlboper_xx_cmplt;
input [2 :0] tlboper_xx_pgs;
input tlboper_xx_pgs_en;
output arb_dutlb_grant;
output arb_iutlb_grant;
output [2 :0] arb_jtlb_acc_type;
output [3 :0] arb_jtlb_bank_sel;
output arb_jtlb_cmp_with_va;
output [41:0] arb_jtlb_data_din;
output [3 :0] arb_jtlb_fifo_din;
output arb_jtlb_fifo_write;
output [8 :0] arb_jtlb_idx;
output arb_jtlb_req;
output [47:0] arb_jtlb_tag_din;
output [26:0] arb_jtlb_vpn;
output arb_jtlb_write;
output arb_ptw_grant;
output arb_ptw_mask;
output arb_tlboper_grant;
output [1 :0] arb_top_cur_st;
output arb_top_tlboper_on;
output mmu_yy_xx_no_op;
// &Regs; @30
reg [1 :0] arb_cur_st;
reg [1 :0] arb_nxt_st;
reg tlboper_on;
// &Wires; @31
wire arb_clk;
wire arb_clk_en;
wire arb_dutlb_grant;
wire arb_idx_sel_1g;
wire arb_idx_sel_2m;
wire arb_idx_sel_4k;
wire arb_iutlb_grant;
wire [2 :0] arb_jtlb_acc_type;
wire [3 :0] arb_jtlb_bank_sel;
wire arb_jtlb_cmp_with_va;
wire [41:0] arb_jtlb_data_din;
wire [3 :0] arb_jtlb_fifo_din;
wire arb_jtlb_fifo_write;
wire [8 :0] arb_jtlb_idx;
wire arb_jtlb_req;
wire [47:0] arb_jtlb_tag_din;
wire [26:0] arb_jtlb_vpn;
wire arb_jtlb_write;
wire arb_load_grant;
wire arb_par_clr;
wire arb_pfu_grant;
wire arb_ptw_grant;
wire arb_ptw_mask;
wire arb_read_huge;
wire arb_store_grant;
wire arb_tlboper_grant;
wire [1 :0] arb_top_cur_st;
wire arb_top_tlboper_on;
wire [8 :0] arb_va_index;
wire [26:0] arb_vpn;
wire cp0_mmu_icg_en;
wire cp0_mmu_no_op_req;
wire cpurst_b;
wire dutlb_arb_cmplt;
wire dutlb_arb_load;
wire dutlb_arb_req;
wire [26:0] dutlb_arb_vpn;
wire dutlb_xx_mmu_off;
wire forever_cpuclk;
wire iutlb_arb_cmplt;
wire iutlb_arb_req;
wire [26:0] iutlb_arb_vpn;
wire jtlb_arb_cmp_va;
wire jtlb_arb_par_clr;
wire jtlb_arb_pfu_cmplt;
wire [26:0] jtlb_arb_pfu_vpn;
wire jtlb_arb_sel_1g;
wire jtlb_arb_sel_2m;
wire jtlb_arb_sel_4k;
wire jtlb_arb_tc_miss;
wire [2 :0] jtlb_arb_type;
wire [26:0] jtlb_arb_vpn;
wire lsu_mmu_va2_vld;
wire mmu_yy_xx_no_op;
wire pad_yy_icg_scan_en;
wire [3 :0] ptw_arb_bank_sel;
wire [41:0] ptw_arb_data_din;
wire [3 :0] ptw_arb_fifo_din;
wire [2 :0] ptw_arb_pgs;
wire ptw_arb_req;
wire [47:0] ptw_arb_tag_din;
wire [26:0] ptw_arb_vpn;
wire [3 :0] tlboper_arb_bank_sel;
wire tlboper_arb_cmp_va;
wire [41:0] tlboper_arb_data_din;
wire [3 :0] tlboper_arb_fifo_din;
wire tlboper_arb_fifo_write;
wire [8 :0] tlboper_arb_idx;
wire tlboper_arb_idx_not_va;
wire tlboper_arb_req;
wire [47:0] tlboper_arb_tag_din;
wire [26:0] tlboper_arb_vpn;
wire tlboper_arb_write;
wire tlboper_fifo_wen;
wire tlboper_idx_not_va_sel;
wire tlboper_wen;
wire tlboper_xx_cmplt;
wire [2 :0] tlboper_xx_pgs;
wire tlboper_xx_pgs_en;
wire utlb_mask;
wire utlb_refill_on;
parameter VPN_WIDTH = 39-12; // VPN
parameter PPN_WIDTH = 40-12; // PPN
parameter FLG_WIDTH = 14; // Flags
parameter PGS_WIDTH = 3; // Page Size
parameter ASID_WIDTH = 16; // Flags
// Valid + VPN + ASID + PageSize + Global
parameter TAG_WIDTH = 1+VPN_WIDTH+ASID_WIDTH+PGS_WIDTH+1;
parameter DATA_WIDTH = PPN_WIDTH+FLG_WIDTH;
//==========================================================
// Gate Cell
//==========================================================
assign arb_clk_en = iutlb_arb_req
|| dutlb_arb_req
|| tlboper_arb_req
|| lsu_mmu_va2_vld
|| utlb_mask;
// &Instance("gated_clk_cell", "x_jtlb_arb_gateclk"); @51
gated_clk_cell x_jtlb_arb_gateclk (
.clk_in (forever_cpuclk ),
.clk_out (arb_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (arb_clk_en ),
.module_en (cp0_mmu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk ), @52
// .external_en(1'b0 ), @53
// .global_en (1'b1 ), @54
// .module_en (cp0_mmu_icg_en ), @55
// .local_en (arb_clk_en ), @56
// .clk_out (arb_clk ) @57
// ); @58
//==============================================================================
// Control Path
//==============================================================================
//==========================================================
// Grant Siangl
//==========================================================
// &Force("output","arb_iutlb_grant"); @67
// &Force("output","arb_dutlb_grant"); @68
// &Force("output","arb_tlboper_grant"); @69
// &Force("output","arb_ptw_grant"); @70
assign arb_pfu_grant = lsu_mmu_va2_vld
&& !dutlb_xx_mmu_off // only valid when mmu is enabled
&& !iutlb_arb_req
&& !dutlb_arb_req
&& !tlboper_arb_req
&& !ptw_arb_req
&& !utlb_mask;
assign arb_iutlb_grant = iutlb_arb_req
&& !dutlb_arb_req
&& !tlboper_arb_req
&& !ptw_arb_req
&& !utlb_mask;
assign arb_dutlb_grant = dutlb_arb_req
&& !tlboper_arb_req
&& !ptw_arb_req
&& !utlb_mask;
assign arb_tlboper_grant = tlboper_arb_req
&& !ptw_arb_req
&& jtlb_arb_sel_4k;
assign arb_ptw_grant = ptw_arb_req;
assign arb_jtlb_req = arb_iutlb_grant
|| arb_pfu_grant
|| arb_dutlb_grant
|| arb_tlboper_grant
|| arb_ptw_grant
|| arb_read_huge
|| arb_par_clr;
//==========================================================
// Req Mask FSM
//==========================================================
parameter ARB_IDLE = 2'b00,
ARB_IUTLB = 2'b01,
ARB_DUTLB = 2'b10,
ARB_PFU = 2'b11;
always @(posedge arb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
arb_cur_st[1:0] <= ARB_IDLE;
else
arb_cur_st[1:0] <= arb_nxt_st[1:0];
end
// &CombBeg; @121
always @( arb_cur_st
or dutlb_arb_cmplt
or arb_iutlb_grant
or iutlb_arb_cmplt
or jtlb_arb_pfu_cmplt
or arb_pfu_grant
or arb_dutlb_grant)
begin
case (arb_cur_st)
ARB_IDLE:
begin
if(arb_pfu_grant)
arb_nxt_st[1:0] = ARB_PFU;
else if(arb_iutlb_grant)
arb_nxt_st[1:0] = ARB_IUTLB;
else if(arb_dutlb_grant)
arb_nxt_st[1:0] = ARB_DUTLB;
else
arb_nxt_st[1:0] = ARB_IDLE;
end
ARB_IUTLB:
begin
if(iutlb_arb_cmplt)
arb_nxt_st[1:0] = ARB_IDLE;
else
arb_nxt_st[1:0] = ARB_IUTLB;
end
ARB_DUTLB:
begin
if(dutlb_arb_cmplt)
arb_nxt_st[1:0] = ARB_IDLE;
else
arb_nxt_st[1:0] = ARB_DUTLB;
end
ARB_PFU:
begin
if(jtlb_arb_pfu_cmplt)
arb_nxt_st[1:0] = ARB_IDLE;
else
arb_nxt_st[1:0] = ARB_PFU;
end
default:
begin
arb_nxt_st[1:0] = ARB_IDLE;
end
endcase
// &CombEnd; @160
end
// 1. tlboper(including ctc oper) req only masked by ptw refill req
// 2. when tlboper started, it will stall all other req
always @(posedge arb_clk or negedge cpurst_b)
begin
if (!cpurst_b)
tlboper_on <= 1'b0;
else if(tlboper_on && tlboper_xx_cmplt)
tlboper_on <= 1'b0;
else if(arb_tlboper_grant)
tlboper_on <= 1'b1;
end
assign utlb_mask = (arb_cur_st[1:0] != ARB_IDLE)
|| tlboper_on;
assign utlb_refill_on = (arb_cur_st[1:0] != ARB_IDLE);
assign arb_ptw_mask = tlboper_on;
assign mmu_yy_xx_no_op = cp0_mmu_no_op_req
&& !utlb_refill_on;
assign arb_read_huge = (jtlb_arb_sel_2m || jtlb_arb_sel_1g) && jtlb_arb_tc_miss;
assign arb_idx_sel_4k = tlboper_xx_pgs_en ? tlboper_xx_pgs[0] :
arb_ptw_grant ? ptw_arb_pgs[0] :
arb_par_clr ? jtlb_arb_sel_2m : jtlb_arb_sel_4k ;
assign arb_idx_sel_2m = tlboper_xx_pgs_en ? tlboper_xx_pgs[1] :
arb_ptw_grant ? ptw_arb_pgs[1] :
arb_par_clr ? jtlb_arb_sel_1g : jtlb_arb_sel_2m ;
assign arb_idx_sel_1g = tlboper_xx_pgs_en ? tlboper_xx_pgs[2] :
arb_ptw_grant ? ptw_arb_pgs[2] :
arb_par_clr ? !jtlb_arb_sel_1g && !jtlb_arb_sel_2m : jtlb_arb_sel_1g ;
// parity check fail invalid request
assign arb_par_clr = jtlb_arb_par_clr;
//==============================================================================
// Data Path
//==============================================================================
//==========================================================
// jTLB Index & VPN(tag for cmp)
//==========================================================
assign arb_vpn[VPN_WIDTH-1:0] =
{VPN_WIDTH{arb_pfu_grant}} & jtlb_arb_pfu_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_iutlb_grant}} & iutlb_arb_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_read_huge}} & jtlb_arb_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_par_clr}} & jtlb_arb_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_dutlb_grant}} & dutlb_arb_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_tlboper_grant}} & tlboper_arb_vpn[VPN_WIDTH-1:0]
| {VPN_WIDTH{arb_ptw_grant}} & ptw_arb_vpn[VPN_WIDTH-1:0];
assign arb_jtlb_vpn[VPN_WIDTH-1:0] = arb_vpn[VPN_WIDTH-1:0];
assign arb_va_index[8:0] = {9{arb_idx_sel_4k}} & arb_vpn[8:0]
| {9{arb_idx_sel_2m}} & arb_vpn[17:9]
| {9{arb_idx_sel_1g}} & arb_vpn[26:18];
assign tlboper_idx_not_va_sel = arb_tlboper_grant && tlboper_arb_idx_not_va;
assign arb_jtlb_idx[8:0] = tlboper_idx_not_va_sel ? tlboper_arb_idx[8:0]
: arb_va_index[8:0];
assign arb_jtlb_bank_sel[3:0] = {4{arb_pfu_grant}} & 4'b1111
| {4{arb_iutlb_grant}} & 4'b1111
| {4{arb_read_huge}} & 4'b1111
| {4{arb_par_clr}} & 4'b1111
| {4{arb_dutlb_grant}} & 4'b1111
| {4{arb_tlboper_grant}} & tlboper_arb_bank_sel[3:0]
| {4{arb_ptw_grant}} & ptw_arb_bank_sel[3:0];
assign arb_jtlb_write = arb_tlboper_grant && tlboper_arb_write
|| arb_ptw_grant && 1'b1
|| arb_par_clr;
assign arb_jtlb_fifo_write = arb_tlboper_grant && tlboper_arb_fifo_write
|| arb_ptw_grant && 1'b1
|| arb_par_clr;
assign arb_jtlb_cmp_with_va = arb_pfu_grant
|| arb_iutlb_grant
|| arb_dutlb_grant
|| arb_read_huge && jtlb_arb_cmp_va
//|| arb_par_clr && jtlb_arb_cmp_va
|| arb_tlboper_grant && tlboper_arb_cmp_va;
assign arb_load_grant = arb_dutlb_grant && dutlb_arb_load;
assign arb_store_grant = arb_dutlb_grant && !dutlb_arb_load;
assign arb_jtlb_acc_type[2:0] = {3{arb_pfu_grant}} & 3'b100
| {3{arb_iutlb_grant}} & 3'b011
| {3{arb_read_huge}} & jtlb_arb_type[2:0]
| {3{arb_load_grant}} & 3'b010
| {3{arb_store_grant}} & 3'b110
| {3{arb_tlboper_grant}} & 3'b001
| {3{arb_par_clr}} & 3'b000
| {3{arb_ptw_grant}} & 3'b000;
//==========================================================
// jTLB Tag & Data Input
//==========================================================
assign tlboper_fifo_wen = arb_tlboper_grant && tlboper_arb_fifo_write;
assign arb_jtlb_fifo_din[3:0] =
{4{tlboper_fifo_wen}} & tlboper_arb_fifo_din[3:0]
| {4{arb_ptw_grant}} & ptw_arb_fifo_din[3:0];
assign tlboper_wen = arb_tlboper_grant && tlboper_arb_write;
assign arb_jtlb_tag_din[TAG_WIDTH-1:0] =
{TAG_WIDTH{tlboper_wen}} & tlboper_arb_tag_din[TAG_WIDTH-1:0]
| {TAG_WIDTH{arb_ptw_grant}} & ptw_arb_tag_din[TAG_WIDTH-1:0];
assign arb_jtlb_data_din[DATA_WIDTH-1:0] =
{DATA_WIDTH{tlboper_wen}} & tlboper_arb_data_din[DATA_WIDTH-1:0]
| {DATA_WIDTH{arb_ptw_grant}} & ptw_arb_data_din[DATA_WIDTH-1:0];
// for dbg
assign arb_top_cur_st[1:0] = arb_cur_st[1:0];
assign arb_top_tlboper_on = tlboper_on;
// &ModuleEnd; @278
endmodule |
module ct_mp_clk_top(
apb_clk,
apb_clk_en,
axim_clk_en,
axim_clk_en_f,
forever_core0_clk,
forever_core1_clk,
forever_cpuclk,
forever_jtgclk,
l2c_data_clk_bank_0,
l2c_data_clk_bank_1,
l2c_data_ram_clk_en_bank_0,
l2c_data_ram_clk_en_bank_1,
l2c_tag_clk_bank_0,
l2c_tag_clk_bank_1,
l2c_tag_ram_clk_en_bank_0,
l2c_tag_ram_clk_en_bank_1,
pad_had_jtg_tclk,
pad_l2c_data_mbist_clk_ratio,
pad_l2c_tag_mbist_clk_ratio,
pad_yy_dft_clk_rst_b,
pad_yy_icg_scan_en,
pad_yy_mbist_mode,
pad_yy_scan_mode,
phl_rst_b,
pll_cpu_clk
);
// &Ports; @23
input axim_clk_en;
input l2c_data_ram_clk_en_bank_0;
input l2c_data_ram_clk_en_bank_1;
input l2c_tag_ram_clk_en_bank_0;
input l2c_tag_ram_clk_en_bank_1;
input pad_had_jtg_tclk;
input [2:0] pad_l2c_data_mbist_clk_ratio;
input [2:0] pad_l2c_tag_mbist_clk_ratio;
input pad_yy_dft_clk_rst_b;
input pad_yy_icg_scan_en;
input pad_yy_mbist_mode;
input pad_yy_scan_mode;
input phl_rst_b;
input pll_cpu_clk;
output apb_clk;
output apb_clk_en;
output axim_clk_en_f;
output forever_core0_clk;
output forever_core1_clk;
output forever_cpuclk;
output forever_jtgclk;
output l2c_data_clk_bank_0;
output l2c_data_clk_bank_1;
output l2c_tag_clk_bank_0;
output l2c_tag_clk_bank_1;
// &Regs; @24
reg apb_clk_en_f;
reg axim_clk_en_f;
reg [2:0] l2c_data_ram_bist_clk_ratio;
reg [2:0] l2c_tag_ram_bist_clk_ratio;
reg peripheral_clk_en;
// &Wires; @25
wire apb_clk_en;
wire axim_clk_en;
wire bist_clk;
wire bist_clk_en;
wire data_ram_bist_cnt_idle;
wire data_ram_clk_en_bank_0;
wire data_ram_clk_en_bank_1;
wire forever_core0_clk;
wire forever_core1_clk;
wire forever_cpuclk;
wire forever_jtgclk;
wire l2c_data_clk_bank_0;
wire l2c_data_clk_bank_0_before_occ;
wire l2c_data_clk_bank_1;
wire l2c_data_clk_bank_1_before_occ;
wire l2c_data_ram_clk_en_bank_0;
wire l2c_data_ram_clk_en_bank_1;
wire l2c_tag_clk_bank_0;
wire l2c_tag_clk_bank_0_before_occ;
wire l2c_tag_clk_bank_1;
wire l2c_tag_clk_bank_1_before_occ;
wire l2c_tag_ram_clk_en_bank_0;
wire l2c_tag_ram_clk_en_bank_1;
wire pad_had_jtg_tclk;
wire [2:0] pad_l2c_data_mbist_clk_ratio;
wire [2:0] pad_l2c_tag_mbist_clk_ratio;
wire pad_yy_dft_clk_rst_b;
wire pad_yy_icg_scan_en;
wire pad_yy_mbist_mode;
wire pad_yy_scan_mode;
wire phl_rst_b;
wire pll_cpu_clk;
wire tag_ram_bist_cnt_idle;
wire tag_ram_clk_en_bank_0;
wire tag_ram_clk_en_bank_1;
// //&Depend("BUFGCE.v"); @27
//================================================
// CPU_CLOCK
//================================================
// &Force("output", "forever_cpuclk"); @31
assign forever_cpuclk = pll_cpu_clk;
// &Instance("clk_buf_cell", "x_ct_mp_top_clk_buf"); @35
// &Connect(.buf_in (pll_cpu_clk), @36
// .buf_out (forever_cpuclk)); @37
assign forever_core0_clk = forever_cpuclk;
assign forever_core1_clk = forever_cpuclk;
//================================================
// JTAG_CLOCK
//================================================
assign forever_jtgclk = pad_had_jtg_tclk;
//================================================
// APB CLOCK
//================================================
// &Force("output", "apb_clk_en"); @81
// &Force("input", "phl_rst_b"); @82
always@(posedge pll_cpu_clk or negedge phl_rst_b)
begin
if (!phl_rst_b)
peripheral_clk_en <= 1'b0;
else
peripheral_clk_en <= ~peripheral_clk_en;
end
always@(posedge pll_cpu_clk)
begin
apb_clk_en_f <= peripheral_clk_en;
end
assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;
// &Force("output","apb_clk"); @104
BUFGCE apb_clk_buf
(.O (apb_clk),
.I (pll_cpu_clk),
.CE (apb_clk_en_f)
);
// &Instance("gated_clk_cell", "x_apb_gated_clk"); @116
// &Connect(.clk_in (pll_cpu_clk ), @117
// .external_en (1'b0 ), @118
// .global_en (1'b1 ), @119
// .module_en (1'b0 ), @120
// .local_en (apb_clk_en_f ), @121
// .clk_out (apb_clk_before_occ) @122
// .pad_yy_icg_scan_en (1'b0) @123
// ); @124
// &Instance("clk_buf_cell", "x_apb_clk_buf"); @125
// &Connect(.buf_in (apb_clk_before_occ), @126
// .buf_out (apb_clk)); @127
//================================================
// SLVIF CLK_EN
//================================================
// &Force("output", "slvif_clk_en_f"); @134
//================================================
// AXIM CLK_EN
//================================================
// &Force("output", "axim_clk_en_f"); @145
always@(posedge forever_cpuclk)
begin
axim_clk_en_f <= axim_clk_en;
end
//================================================
// L2C DATA CLOCK
//================================================
assign bist_clk_en = pad_yy_mbist_mode | pad_yy_scan_mode;
// &Instance("gated_clk_cell", "x_data_bist_gated_clk"); @157
gated_clk_cell x_data_bist_gated_clk (
.clk_in (pll_cpu_clk ),
.clk_out (bist_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (bist_clk_en ),
.module_en (1'b0 ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (pll_cpu_clk ), @158
// .external_en (1'b0 ), @159
// .global_en (1'b1 ), @160
// .module_en (1'b0 ), @161
// .local_en (bist_clk_en ), @162
// .clk_out (bist_clk ) @163
// ); @164
always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b)
begin
if (!pad_yy_dft_clk_rst_b)
l2c_data_ram_bist_clk_ratio[2:0] <= 3'b0;
else if (bist_clk_en) begin
if (data_ram_bist_cnt_idle)
l2c_data_ram_bist_clk_ratio[2:0] <= pad_l2c_data_mbist_clk_ratio[2:0];
else
l2c_data_ram_bist_clk_ratio[2:0] <= l2c_data_ram_bist_clk_ratio[2:0] - 3'b001;
end
end
assign data_ram_bist_cnt_idle = l2c_data_ram_bist_clk_ratio[2:0] == 3'b000;
assign data_ram_clk_en_bank_0 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_0;
assign data_ram_clk_en_bank_1 = bist_clk_en ? data_ram_bist_cnt_idle : l2c_data_ram_clk_en_bank_1;
// &Force("nonport","l2c_data_clk_bank_0_before_occ"); @184
// &Force("nonport","l2c_data_clk_bank_1_before_occ"); @185
// &Force("nonport","data_ram_clk_en_bank_0"); @186
// &Force("nonport","data_ram_clk_en_bank_1"); @187
BUFGCE data_bank0_clk_buf
(.O (l2c_data_clk_bank_0_before_occ),
.I (pll_cpu_clk),
.CE (data_ram_clk_en_bank_0)
);
BUFGCE data_bank1_clk_buf
(.O (l2c_data_clk_bank_1_before_occ),
.I (pll_cpu_clk),
.CE (data_ram_clk_en_bank_1)
);
// &Instance("gated_clk_cell", "x_l2cache_data_ram_gated_clk_0"); @201
// &Connect( @202
// .clk_in (pll_cpu_clk ), @203
// .external_en (1'b0 ), @204
// .global_en (1'b1 ), @205
// .module_en (1'b0 ), @206
// .local_en (data_ram_clk_en_bank_0), @207
// .clk_out (l2c_data_clk_bank_0_before_occ), @208
// .pad_yy_icg_scan_en (1'b0 ) @209
// ); @210
// &Instance("gated_clk_cell", "x_l2cache_data_ram_gated_clk_1"); @212
// &Connect( @213
// .clk_in (pll_cpu_clk ), @214
// .external_en (1'b0 ), @215
// .global_en (1'b1 ), @216
// .module_en (1'b0 ), @217
// .local_en (data_ram_clk_en_bank_1), @218
// .clk_out (l2c_data_clk_bank_1_before_occ), @219
// .pad_yy_icg_scan_en (1'b0 ) @220
// ); @221
assign l2c_data_clk_bank_0 = l2c_data_clk_bank_0_before_occ;
assign l2c_data_clk_bank_1 = l2c_data_clk_bank_1_before_occ;
// &Instance("clk_buf_cell", "x_l2c_data_bank0_clk_buf"); @228
// &Connect(.buf_in (l2c_data_clk_bank_0_before_occ), @229
// .buf_out (l2c_data_clk_bank_0)); @230
// &Instance("clk_buf_cell", "x_l2c_data_bank1_clk_buf"); @232
// &Connect(.buf_in (l2c_data_clk_bank_1_before_occ), @233
// .buf_out (l2c_data_clk_bank_1)); @234
//================================================
// L2C TAG CLOCK
//================================================
always@(posedge bist_clk or negedge pad_yy_dft_clk_rst_b)
begin
if (!pad_yy_dft_clk_rst_b)
l2c_tag_ram_bist_clk_ratio[2:0] <= 3'b0;
else if (bist_clk_en) begin
if (tag_ram_bist_cnt_idle)
l2c_tag_ram_bist_clk_ratio[2:0] <= pad_l2c_tag_mbist_clk_ratio[2:0];
else
l2c_tag_ram_bist_clk_ratio[2:0] <= l2c_tag_ram_bist_clk_ratio[2:0] - 3'b001;
end
end
assign tag_ram_bist_cnt_idle = l2c_tag_ram_bist_clk_ratio[2:0] == 3'b000;
assign tag_ram_clk_en_bank_0 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_0;
assign tag_ram_clk_en_bank_1 = bist_clk_en ? tag_ram_bist_cnt_idle : l2c_tag_ram_clk_en_bank_1;
// &Force("nonport","l2c_tag_clk_bank_0_before_occ"); @258
// &Force("nonport","l2c_tag_clk_bank_1_before_occ"); @259
// &Force("nonport","tag_ram_clk_en_bank_0"); @260
// &Force("nonport","tag_ram_clk_en_bank_1"); @261
BUFGCE tag_bank0_clk_buf
(.O (l2c_tag_clk_bank_0_before_occ),
.I (pll_cpu_clk),
.CE (tag_ram_clk_en_bank_0)
);
BUFGCE tag_bank1_clk_buf
(.O (l2c_tag_clk_bank_1_before_occ),
.I (pll_cpu_clk),
.CE (tag_ram_clk_en_bank_1)
);
// &Instance("gated_clk_cell", "x_l2cache_tag_ram_gated_clk_0"); @274
// &Connect( @275
// .clk_in (pll_cpu_clk ), @276
// .external_en (1'b0 ), @277
// .global_en (1'b1 ), @278
// .module_en (1'b0 ), @279
// .local_en (tag_ram_clk_en_bank_0), @280
// .clk_out (l2c_tag_clk_bank_0_before_occ), @281
// .pad_yy_icg_scan_en (1'b0 ) @282
// ); @283
// &Instance("gated_clk_cell", "x_l2cache_tag_ram_gated_clk_1"); @285
// &Connect( @286
// .clk_in (pll_cpu_clk ), @287
// .external_en (1'b0 ), @288
// .global_en (1'b1 ), @289
// .module_en (1'b0 ), @290
// .local_en (tag_ram_clk_en_bank_1), @291
// .clk_out (l2c_tag_clk_bank_1_before_occ), @292
// .pad_yy_icg_scan_en (1'b0 ) @293
// ); @294
assign l2c_tag_clk_bank_0 = l2c_tag_clk_bank_0_before_occ;
assign l2c_tag_clk_bank_1 = l2c_tag_clk_bank_1_before_occ;
// &Instance("clk_buf_cell", "x_l2c_tag_bank0_clk_buf"); @301
// &Connect(.buf_in (l2c_tag_clk_bank_0_before_occ), @302
// .buf_out (l2c_tag_clk_bank_0)); @303
// &Instance("clk_buf_cell", "x_l2c_tag_bank1_clk_buf"); @305
// &Connect(.buf_in (l2c_tag_clk_bank_1_before_occ), @306
// .buf_out (l2c_tag_clk_bank_1)); @307
// &ModuleEnd; @310
endmodule |
module ct_clk_top(
biu_xx_dbg_wakeup,
biu_xx_int_wakeup,
biu_xx_normal_work,
biu_xx_pmp_sel,
biu_xx_snoop_vld,
coreclk,
cp0_xx_core_icg_en,
forever_coreclk,
had_xx_clk_en,
pll_core_clk
);
// &Ports; @23
input biu_xx_dbg_wakeup;
input biu_xx_int_wakeup;
input biu_xx_normal_work;
input biu_xx_pmp_sel;
input biu_xx_snoop_vld;
input cp0_xx_core_icg_en;
input had_xx_clk_en;
input pll_core_clk;
output coreclk;
output forever_coreclk;
// &Regs; @24
// &Wires; @25
wire biu_xx_dbg_wakeup;
wire biu_xx_int_wakeup;
wire biu_xx_normal_work;
wire biu_xx_pmp_sel;
wire biu_xx_snoop_vld;
wire core_clk_en;
wire cp0_xx_core_icg_en;
wire forever_coreclk;
wire had_xx_clk_en;
wire pll_core_clk;
// &Force("output", "forever_coreclk"); @27
assign forever_coreclk = pll_core_clk;
//==============================================================================
// global ICG for core
//==============================================================================
assign core_clk_en = biu_xx_normal_work |
biu_xx_int_wakeup |
biu_xx_dbg_wakeup |
biu_xx_snoop_vld |
had_xx_clk_en |
biu_xx_pmp_sel |
cp0_xx_core_icg_en ;
// &Force("nonport","core_clk_en"); @41
// &Force("output","coreclk"); @42
BUFGCE core_clk_buf
(.O (coreclk),
.I (forever_coreclk),
.CE (core_clk_en)
);
// &Instance("gated_clk_cell", "x_core_gated_clk"); @49
// &Connect(.clk_in (forever_coreclk ), @50
// .external_en (1'b0 ), @51
// .global_en (1'b1 ), @52
// .module_en (1'b0 ), @53
// .local_en (core_clk_en ), @54
// .clk_out (coreclk )); @55
// &ModuleEnd; @58
endmodule |
module ct_biu_other_io_sync(
biu_cp0_apb_base,
biu_cp0_coreid,
biu_cp0_me_int,
biu_cp0_ms_int,
biu_cp0_mt_int,
biu_cp0_rvba,
biu_cp0_se_int,
biu_cp0_ss_int,
biu_cp0_st_int,
biu_csr_cmplt,
biu_csr_op,
biu_csr_rdata,
biu_csr_sel,
biu_csr_wdata,
biu_had_coreid,
biu_had_sdb_req_b,
biu_hpcp_l2of_int,
biu_hpcp_time,
biu_mmu_smp_disable,
biu_pad_cnt_en,
biu_pad_csr_sel,
biu_pad_csr_wdata,
biu_pad_jdb_pm,
biu_pad_lpmd_b,
biu_xx_dbg_wakeup,
biu_xx_int_wakeup,
biu_xx_normal_work,
biu_xx_pmp_sel,
coreclk,
cp0_biu_icg_en,
cp0_biu_lpmd_b,
cpurst_b,
forever_coreclk,
had_biu_jdb_pm,
hpcp_biu_cnt_en,
pad_biu_csr_cmplt,
pad_biu_csr_rdata,
pad_biu_dbgrq_b,
pad_biu_hpcp_l2of_int,
pad_biu_me_int,
pad_biu_ms_int,
pad_biu_mt_int,
pad_biu_se_int,
pad_biu_ss_int,
pad_biu_st_int,
pad_core_hartid,
pad_core_rvba,
pad_xx_apb_base,
pad_xx_time,
pad_yy_icg_scan_en
);
// &Ports; @23
input [15 :0] biu_csr_op;
input biu_csr_sel;
input [63 :0] biu_csr_wdata;
input coreclk;
input cp0_biu_icg_en;
input [1 :0] cp0_biu_lpmd_b;
input cpurst_b;
input forever_coreclk;
input [1 :0] had_biu_jdb_pm;
input [3 :0] hpcp_biu_cnt_en;
input pad_biu_csr_cmplt;
input [127:0] pad_biu_csr_rdata;
input pad_biu_dbgrq_b;
input [3 :0] pad_biu_hpcp_l2of_int;
input pad_biu_me_int;
input pad_biu_ms_int;
input pad_biu_mt_int;
input pad_biu_se_int;
input pad_biu_ss_int;
input pad_biu_st_int;
input [2 :0] pad_core_hartid;
input [39 :0] pad_core_rvba;
input [39 :0] pad_xx_apb_base;
input [63 :0] pad_xx_time;
input pad_yy_icg_scan_en;
output [39 :0] biu_cp0_apb_base;
output [2 :0] biu_cp0_coreid;
output biu_cp0_me_int;
output biu_cp0_ms_int;
output biu_cp0_mt_int;
output [39 :0] biu_cp0_rvba;
output biu_cp0_se_int;
output biu_cp0_ss_int;
output biu_cp0_st_int;
output biu_csr_cmplt;
output [127:0] biu_csr_rdata;
output [1 :0] biu_had_coreid;
output biu_had_sdb_req_b;
output [3 :0] biu_hpcp_l2of_int;
output [63 :0] biu_hpcp_time;
output biu_mmu_smp_disable;
output [3 :0] biu_pad_cnt_en;
output biu_pad_csr_sel;
output [79 :0] biu_pad_csr_wdata;
output biu_pad_jdb_pm;
output biu_pad_lpmd_b;
output biu_xx_dbg_wakeup;
output biu_xx_int_wakeup;
output biu_xx_normal_work;
output biu_xx_pmp_sel;
// &Regs; @24
reg [39 :0] biu_cp0_apb_base;
reg [39 :0] biu_cp0_rvba;
reg biu_csr_cmplt;
reg [127:0] biu_csr_rdata;
reg biu_csr_sel_ff;
reg [3 :0] biu_hpcp_l2of_int;
reg [63 :0] biu_hpcp_time;
reg [3 :0] biu_pad_cnt_en;
reg biu_pad_csr_sel;
reg [79 :0] biu_pad_csr_wdata;
reg biu_pad_jdb_pm;
reg biu_pad_lpmd_b;
reg cp0_me_int_ff1;
reg cp0_me_int_ff2;
reg cp0_ms_int_ff1;
reg cp0_ms_int_ff2;
reg cp0_mt_int_ff1;
reg cp0_mt_int_ff2;
reg cp0_se_int_ff1;
reg cp0_se_int_ff2;
reg cp0_ss_int_ff1;
reg cp0_ss_int_ff2;
reg cp0_st_int_ff1;
reg cp0_st_int_ff2;
reg had_sdb_req_b_ff1;
reg had_sdb_req_b_ff2;
// &Wires; @25
wire [2 :0] biu_cp0_coreid;
wire biu_cp0_me_int;
wire biu_cp0_ms_int;
wire biu_cp0_mt_int;
wire biu_cp0_se_int;
wire biu_cp0_ss_int;
wire biu_cp0_st_int;
wire [15 :0] biu_csr_op;
wire [79 :0] biu_csr_req_data;
wire biu_csr_sel;
wire [63 :0] biu_csr_wdata;
wire [1 :0] biu_had_coreid;
wire biu_had_sdb_req_b;
wire biu_mmu_smp_disable;
wire biu_xx_dbg_wakeup;
wire biu_xx_int_wakeup;
wire biu_xx_normal_work;
wire biu_xx_pmp_sel;
wire coreclk;
wire cp0_biu_icg_en;
wire [1 :0] cp0_biu_lpmd_b;
wire cpurst_b;
wire csr_sel_pulse;
wire forever_coreclk;
wire [1 :0] had_biu_jdb_pm;
wire [3 :0] hpcp_biu_cnt_en;
wire l2reg_iclk;
wire l2reg_iclk_en;
wire l2reg_oclk;
wire l2reg_oclk_en;
wire pad_biu_csr_cmplt;
wire [127:0] pad_biu_csr_rdata;
wire pad_biu_dbgrq_b;
wire [3 :0] pad_biu_hpcp_l2of_int;
wire pad_biu_me_int;
wire pad_biu_ms_int;
wire pad_biu_mt_int;
wire pad_biu_se_int;
wire pad_biu_ss_int;
wire pad_biu_st_int;
wire [2 :0] pad_core_hartid;
wire [39 :0] pad_core_rvba;
wire [39 :0] pad_xx_apb_base;
wire [63 :0] pad_xx_time;
wire pad_yy_icg_scan_en;
//=========================================
// CIU ID
//=========================================
assign biu_cp0_coreid[2:0] = pad_core_hartid[2:0];
assign biu_had_coreid[1:0] = pad_core_hartid[1:0];
//=========================================
// RVBA: reset vector base address
//=========================================
always@(posedge coreclk)
begin
biu_cp0_rvba[39:0] <= pad_core_rvba[39:0];
end
//=========================================
// apb base address
//=========================================
always@(posedge coreclk)
begin
biu_cp0_apb_base[39:0] <= pad_xx_apb_base[39:0];
end
// &Force("output", "biu_pmp_psel"); @77
// &Force("output", "biu_pad_pready"); @78
// &Instance("gated_clk_cell", "x_ct_apbif_in_gated_clk"); @81
// &Connect(.clk_in (forever_coreclk), @82
// .external_en (1'b0), @83
// .global_en (1'b1), @84
// .module_en (cp0_biu_icg_en), @85
// .local_en (apbif_iclk_en), @86
// .clk_out (apbif_iclk)); @87
// &Instance("gated_clk_cell", "x_ct_apbif_out_gated_clk"); @90
// &Connect(.clk_in (forever_coreclk), @91
// .external_en (1'b0), @92
// .global_en (1'b1), @93
// .module_en (cp0_biu_icg_en), @94
// .local_en (apbif_oclk_en), @95
// .clk_out (apbif_oclk)); @96
assign biu_xx_pmp_sel = 1'b0;
//==============================================================================
// L2C CSR and RAM REQ/ACK signals
//==============================================================================
assign l2reg_oclk_en = biu_csr_sel | biu_csr_sel_ff;
// &Instance("gated_clk_cell", "x_ct_l2reg_out_gated_clk"); @143
gated_clk_cell x_ct_l2reg_out_gated_clk (
.clk_in (coreclk ),
.clk_out (l2reg_oclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2reg_oclk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (coreclk), @144
// .external_en (1'b0), @145
// .global_en (1'b1), @146
// .module_en (cp0_biu_icg_en), @147
// .local_en (l2reg_oclk_en), @148
// .clk_out (l2reg_oclk)); @149
assign l2reg_iclk_en = pad_biu_csr_cmplt | biu_csr_cmplt;
// &Instance("gated_clk_cell", "x_ct_l2reg_in_gated_clk"); @152
gated_clk_cell x_ct_l2reg_in_gated_clk (
.clk_in (coreclk ),
.clk_out (l2reg_iclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (l2reg_iclk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (coreclk), @153
// .external_en (1'b0), @154
// .global_en (1'b1), @155
// .module_en (cp0_biu_icg_en), @156
// .local_en (l2reg_iclk_en), @157
// .clk_out (l2reg_iclk)); @158
always@(posedge l2reg_oclk or negedge cpurst_b)
begin
if (!cpurst_b)
biu_csr_sel_ff <= 1'b0;
else
biu_csr_sel_ff <= biu_csr_sel;
end
assign csr_sel_pulse = biu_csr_sel & !biu_csr_sel_ff;
always@(posedge l2reg_oclk or negedge cpurst_b)
begin
if (!cpurst_b)
biu_pad_csr_sel <= 1'b0;
else
biu_pad_csr_sel <= csr_sel_pulse;
end
assign biu_csr_req_data[79:0] = {biu_csr_op[15:0],biu_csr_wdata[63:0]};
always@(posedge l2reg_oclk)
begin
if (csr_sel_pulse) begin
biu_pad_csr_wdata[79:0] <= biu_csr_req_data[79:0];
end
end
always@(posedge l2reg_iclk or negedge cpurst_b)
begin
if (!cpurst_b)
biu_csr_cmplt <= 1'b0;
else
biu_csr_cmplt <= pad_biu_csr_cmplt;
end
// &Force("output","biu_csr_cmplt"); @195
always@(posedge l2reg_iclk)
begin
if (pad_biu_csr_cmplt)
biu_csr_rdata[127:0] <= pad_biu_csr_rdata[127:0];
end
//==============================================================================
// single bit level signals
//==============================================================================
//=========================================
// intput: interrupt requests
//=========================================
always @(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b) begin
cp0_me_int_ff1 <= 1'b0;
cp0_mt_int_ff1 <= 1'b0;
cp0_ms_int_ff1 <= 1'b0;
cp0_se_int_ff1 <= 1'b0;
cp0_st_int_ff1 <= 1'b0;
cp0_ss_int_ff1 <= 1'b0;
cp0_me_int_ff2 <= 1'b0;
cp0_mt_int_ff2 <= 1'b0;
cp0_ms_int_ff2 <= 1'b0;
cp0_se_int_ff2 <= 1'b0;
cp0_st_int_ff2 <= 1'b0;
cp0_ss_int_ff2 <= 1'b0;
end
else begin
cp0_me_int_ff1 <= pad_biu_me_int;
cp0_mt_int_ff1 <= pad_biu_mt_int;
cp0_ms_int_ff1 <= pad_biu_ms_int;
cp0_se_int_ff1 <= pad_biu_se_int;
cp0_st_int_ff1 <= pad_biu_st_int;
cp0_ss_int_ff1 <= pad_biu_ss_int;
cp0_me_int_ff2 <= cp0_me_int_ff1;
cp0_mt_int_ff2 <= cp0_mt_int_ff1;
cp0_ms_int_ff2 <= cp0_ms_int_ff1;
cp0_se_int_ff2 <= cp0_se_int_ff1;
cp0_st_int_ff2 <= cp0_st_int_ff1;
cp0_ss_int_ff2 <= cp0_ss_int_ff1;
end
end
assign biu_cp0_me_int = cp0_me_int_ff2;
assign biu_cp0_mt_int = cp0_mt_int_ff2;
assign biu_cp0_ms_int = cp0_ms_int_ff2;
assign biu_cp0_se_int = cp0_se_int_ff2;
assign biu_cp0_st_int = cp0_st_int_ff2;
assign biu_cp0_ss_int = cp0_ss_int_ff2;
assign biu_xx_int_wakeup = cp0_me_int_ff2 | cp0_mt_int_ff2 | cp0_ms_int_ff2 |
cp0_se_int_ff2 | cp0_st_int_ff2 | cp0_ss_int_ff2;
//=========================================
// input: debug request
//=========================================
always@(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b) begin
had_sdb_req_b_ff1 <= 1'b1;
had_sdb_req_b_ff2 <= 1'b1;
end
else begin
had_sdb_req_b_ff1 <= pad_biu_dbgrq_b;
had_sdb_req_b_ff2 <= had_sdb_req_b_ff1;
end
end
assign biu_had_sdb_req_b = had_sdb_req_b_ff2;
assign biu_xx_dbg_wakeup = !had_sdb_req_b_ff2;
//=========================================
// hpcp_timer
//=========================================
always@(posedge coreclk)
begin
biu_hpcp_time[63:0] <= pad_xx_time[63:0];
end
//==============================================================================
// output port
//==============================================================================
//=========================================
// lpmd
//=========================================
// &Force("bus", "cp0_biu_lpmd_b",1,0); @285
// &Force("bus", "had_biu_jdb_pm",1,0); @286
// &Force("output", "biu_pad_lpmd_b"); @287
always@(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b) begin
biu_pad_lpmd_b <= 1'b1;
biu_pad_jdb_pm <= 1'b0;
end
else begin
biu_pad_lpmd_b <= cp0_biu_lpmd_b[0];
biu_pad_jdb_pm <= had_biu_jdb_pm[1];
end
end
assign biu_xx_normal_work = biu_pad_lpmd_b;
//=========================================
// hpcp_cnt_en for L2C
//=========================================
//output
always@(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b)
biu_pad_cnt_en[3:0] <= 4'b0;
else
biu_pad_cnt_en[3:0] <= hpcp_biu_cnt_en[3:0];
end
//input
always@(posedge forever_coreclk or negedge cpurst_b)
begin
if (!cpurst_b)
biu_hpcp_l2of_int[3:0] <= 4'b0;
else
biu_hpcp_l2of_int[3:0] <= pad_biu_hpcp_l2of_int[3:0];
end
assign biu_mmu_smp_disable = 1'b0;
// &ModuleEnd; @353
endmodule |
module ct_biu_lowpower(
accpuclk,
arcpuclk,
bcpuclk,
biu_yy_xx_no_op,
bus_arb_w_fifo_clk,
bus_arb_w_fifo_clk_en,
cdcpuclk,
coreclk,
cp0_biu_icg_en,
crcpuclk,
forever_coreclk,
pad_yy_icg_scan_en,
rcpuclk,
read_ar_clk_en,
read_busy,
read_r_clk_en,
round_w_clk_en,
round_wcpuclk,
snoop_ac_clk_en,
snoop_cd_clk_en,
snoop_cr_clk_en,
st_aw_clk_en,
st_awcpuclk,
st_w_clk_en,
st_wcpuclk,
vict_aw_clk_en,
vict_awcpuclk,
vict_w_clk_en,
vict_wcpuclk,
write_b_clk_en,
write_busy
);
// &Ports; @24
input bus_arb_w_fifo_clk_en;
input coreclk;
input cp0_biu_icg_en;
input forever_coreclk;
input pad_yy_icg_scan_en;
input read_ar_clk_en;
input read_busy;
input read_r_clk_en;
input round_w_clk_en;
input snoop_ac_clk_en;
input snoop_cd_clk_en;
input snoop_cr_clk_en;
input st_aw_clk_en;
input st_w_clk_en;
input vict_aw_clk_en;
input vict_w_clk_en;
input write_b_clk_en;
input write_busy;
output accpuclk;
output arcpuclk;
output bcpuclk;
output biu_yy_xx_no_op;
output bus_arb_w_fifo_clk;
output cdcpuclk;
output crcpuclk;
output rcpuclk;
output round_wcpuclk;
output st_awcpuclk;
output st_wcpuclk;
output vict_awcpuclk;
output vict_wcpuclk;
// &Regs; @25
// &Wires; @26
wire accpuclk;
wire arcpuclk;
wire bcpuclk;
wire biu_yy_xx_no_op;
wire bus_arb_w_fifo_clk;
wire bus_arb_w_fifo_clk_en;
wire cdcpuclk;
wire coreclk;
wire cp0_biu_icg_en;
wire crcpuclk;
wire forever_coreclk;
wire pad_yy_icg_scan_en;
wire rcpuclk;
wire read_ar_clk_en;
wire read_busy;
wire read_r_clk_en;
wire round_w_clk_en;
wire round_wcpuclk;
wire snoop_ac_clk_en;
wire snoop_cd_clk_en;
wire snoop_cr_clk_en;
wire st_aw_clk_en;
wire st_awcpuclk;
wire st_w_clk_en;
wire st_wcpuclk;
wire vict_aw_clk_en;
wire vict_awcpuclk;
wire vict_w_clk_en;
wire vict_wcpuclk;
wire write_b_clk_en;
wire write_busy;
//==========================================================
// low power gated clock for read channel
//==========================================================
// &Instance("gated_clk_cell","x_read_channel_ar_gated_cell"); @31
gated_clk_cell x_read_channel_ar_gated_cell (
.clk_in (coreclk ),
.clk_out (arcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (read_ar_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @32
// .clk_out (arcpuclk ), @33
// .external_en (1'b0 ), @34
// .global_en (1'b1 ), @35
// .local_en (read_ar_clk_en ), @36
// .module_en (cp0_biu_icg_en) @37
// ); @38
// &Instance("gated_clk_cell","x_read_channel_r_gated_cell"); @40
gated_clk_cell x_read_channel_r_gated_cell (
.clk_in (coreclk ),
.clk_out (rcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (read_r_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @41
// .clk_out (rcpuclk ), @42
// .external_en (1'b0 ), @43
// .global_en (1'b1 ), @44
// .local_en (read_r_clk_en ), @45
// .module_en (cp0_biu_icg_en) @46
// ); @47
//==========================================================
// low power gated clock for write channel
//==========================================================
// &Instance("gated_clk_cell","x_write_channel_vict_aw_gated_cell"); @51
gated_clk_cell x_write_channel_vict_aw_gated_cell (
.clk_in (coreclk ),
.clk_out (vict_awcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vict_aw_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @52
// .clk_out (vict_awcpuclk ), @53
// .external_en (1'b0 ), @54
// .global_en (1'b1 ), @55
// .local_en (vict_aw_clk_en ), @56
// .module_en (cp0_biu_icg_en) @57
// ); @58
// &Instance("gated_clk_cell","x_write_channel_st_aw_gated_cell"); @60
gated_clk_cell x_write_channel_st_aw_gated_cell (
.clk_in (coreclk ),
.clk_out (st_awcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (st_aw_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @61
// .clk_out (st_awcpuclk ), @62
// .external_en (1'b0 ), @63
// .global_en (1'b1 ), @64
// .local_en (st_aw_clk_en ), @65
// .module_en (cp0_biu_icg_en) @66
// ); @67
// &Instance("gated_clk_cell","x_write_channel_vict_w_gated_cell"); @69
gated_clk_cell x_write_channel_vict_w_gated_cell (
.clk_in (coreclk ),
.clk_out (vict_wcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (vict_w_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @70
// .clk_out (vict_wcpuclk ), @71
// .external_en (1'b0 ), @72
// .global_en (1'b1 ), @73
// .local_en (vict_w_clk_en ), @74
// .module_en (cp0_biu_icg_en) @75
// ); @76
// &Instance("gated_clk_cell","x_write_channel_st_w_gated_cell"); @78
gated_clk_cell x_write_channel_st_w_gated_cell (
.clk_in (coreclk ),
.clk_out (st_wcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (st_w_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @79
// .clk_out (st_wcpuclk ), @80
// .external_en (1'b0 ), @81
// .global_en (1'b1 ), @82
// .local_en (st_w_clk_en ), @83
// .module_en (cp0_biu_icg_en) @84
// ); @85
// &Instance("gated_clk_cell","x_write_channel_round_w_gated_cell"); @87
gated_clk_cell x_write_channel_round_w_gated_cell (
.clk_in (coreclk ),
.clk_out (round_wcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (round_w_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @88
// .clk_out (round_wcpuclk ), @89
// .external_en (1'b0 ), @90
// .global_en (1'b1 ), @91
// .local_en (round_w_clk_en ), @92
// .module_en (cp0_biu_icg_en) @93
// ); @94
// &Instance("gated_clk_cell", "x_lsu_bus_arb_w_fifo_gated_clk"); @96
gated_clk_cell x_lsu_bus_arb_w_fifo_gated_clk (
.clk_in (coreclk ),
.clk_out (bus_arb_w_fifo_clk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (bus_arb_w_fifo_clk_en),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (coreclk ), @97
// .external_en (1'b0 ), @98
// .global_en (1'b1 ), @99
// .module_en (cp0_biu_icg_en ), @100
// .local_en (bus_arb_w_fifo_clk_en), @101
// .clk_out (bus_arb_w_fifo_clk )); @102
// &Instance("gated_clk_cell","x_write_channel_b_gated_cell"); @104
gated_clk_cell x_write_channel_b_gated_cell (
.clk_in (coreclk ),
.clk_out (bcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (write_b_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @105
// .clk_out (bcpuclk ), @106
// .external_en (1'b0 ), @107
// .global_en (1'b1 ), @108
// .local_en (write_b_clk_en ), @109
// .module_en (cp0_biu_icg_en) @110
// ); @111
//==========================================================
// low power gated clock for snoop channel
//==========================================================
// &Instance("gated_clk_cell","x_snoop_channel_ac_gated_cell"); @115
gated_clk_cell x_snoop_channel_ac_gated_cell (
.clk_in (forever_coreclk ),
.clk_out (accpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (snoop_ac_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_coreclk ), @116
// .clk_out (accpuclk ), @117
// .external_en (1'b0 ), @118
// .global_en (1'b1 ), @119
// .local_en (snoop_ac_clk_en ), @120
// .module_en (cp0_biu_icg_en) @121
// ); @122
// &Instance("gated_clk_cell","x_snoop_channel_cr_gated_cell"); @124
gated_clk_cell x_snoop_channel_cr_gated_cell (
.clk_in (coreclk ),
.clk_out (crcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (snoop_cr_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @125
// .clk_out (crcpuclk ), @126
// .external_en (1'b0 ), @127
// .global_en (1'b1 ), @128
// .local_en (snoop_cr_clk_en ), @129
// .module_en (cp0_biu_icg_en) @130
// ); @131
// &Instance("gated_clk_cell","x_snoop_channel_cd_gated_cell"); @133
gated_clk_cell x_snoop_channel_cd_gated_cell (
.clk_in (coreclk ),
.clk_out (cdcpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (snoop_cd_clk_en ),
.module_en (cp0_biu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (coreclk ), @134
// .clk_out (cdcpuclk ), @135
// .external_en (1'b0 ), @136
// .global_en (1'b1 ), @137
// .local_en (snoop_cd_clk_en ), @138
// .module_en (cp0_biu_icg_en) @139
// ); @140
//for low power mode
assign biu_yy_xx_no_op = !read_busy && !write_busy;
// &ModuleEnd; @145
endmodule |
module ct_biu_csr_req_arbiter(
biu_cp0_cmplt,
biu_cp0_rdata,
biu_csr_cmplt,
biu_csr_op,
biu_csr_rdata,
biu_csr_sel,
biu_csr_wdata,
biu_hpcp_cmplt,
biu_hpcp_rdata,
cp0_biu_op,
cp0_biu_sel,
cp0_biu_wdata,
hpcp_biu_op,
hpcp_biu_sel,
hpcp_biu_wdata
);
// &Ports; @23
input biu_csr_cmplt;
input [127:0] biu_csr_rdata;
input [15 :0] cp0_biu_op;
input cp0_biu_sel;
input [63 :0] cp0_biu_wdata;
input [15 :0] hpcp_biu_op;
input hpcp_biu_sel;
input [63 :0] hpcp_biu_wdata;
output biu_cp0_cmplt;
output [127:0] biu_cp0_rdata;
output [15 :0] biu_csr_op;
output biu_csr_sel;
output [63 :0] biu_csr_wdata;
output biu_hpcp_cmplt;
output [127:0] biu_hpcp_rdata;
// &Regs; @24
reg [15 :0] biu_csr_op;
reg biu_csr_sel;
reg [63 :0] biu_csr_wdata;
// &Wires; @25
wire biu_cp0_cmplt;
wire [127:0] biu_cp0_rdata;
wire biu_csr_cmplt;
wire [127:0] biu_csr_rdata;
wire biu_hpcp_cmplt;
wire [127:0] biu_hpcp_rdata;
wire [15 :0] cp0_biu_op;
wire cp0_biu_sel;
wire [63 :0] cp0_biu_wdata;
wire [15 :0] hpcp_biu_op;
wire hpcp_biu_sel;
wire [63 :0] hpcp_biu_wdata;
// &CombBeg; @27
always @( hpcp_biu_op[15:0]
or hpcp_biu_wdata[63:0]
or cp0_biu_wdata[63:0]
or cp0_biu_op[15:0]
or cp0_biu_sel
or hpcp_biu_sel)
begin
if(cp0_biu_sel)
begin
biu_csr_sel = 1'b1;
biu_csr_op[15:0] = cp0_biu_op[15:0];
biu_csr_wdata[63:0] = cp0_biu_wdata[63:0];
end
else
begin
biu_csr_sel = hpcp_biu_sel;
biu_csr_op[15:0] = hpcp_biu_op[15:0];
biu_csr_wdata[63:0] = hpcp_biu_wdata[63:0];
end
// &CombEnd; @40
end
assign biu_cp0_cmplt = biu_csr_cmplt && cp0_biu_sel;
assign biu_cp0_rdata[127:0] = biu_csr_rdata[127:0];
assign biu_hpcp_cmplt = biu_csr_cmplt;
assign biu_hpcp_rdata[127:0] = biu_csr_rdata[127:0];
// &ModuleEnd; @47
endmodule |
module ct_pmp_regs(
cp0_pmp_wdata,
cpuclk,
cpurst_b,
pmp_cp0_data,
pmp_csr_sel,
pmp_csr_wen,
pmpaddr0_value,
pmpaddr1_value,
pmpaddr2_value,
pmpaddr3_value,
pmpaddr4_value,
pmpaddr5_value,
pmpaddr6_value,
pmpaddr7_value,
pmpcfg0_value,
pmpcfg2_value
);
// &Ports; @24
input [63:0] cp0_pmp_wdata;
input cpuclk;
input cpurst_b;
input [17:0] pmp_csr_sel;
input [17:0] pmp_csr_wen;
output [63:0] pmp_cp0_data;
output [28:0] pmpaddr0_value;
output [28:0] pmpaddr1_value;
output [28:0] pmpaddr2_value;
output [28:0] pmpaddr3_value;
output [28:0] pmpaddr4_value;
output [28:0] pmpaddr5_value;
output [28:0] pmpaddr6_value;
output [28:0] pmpaddr7_value;
output [63:0] pmpcfg0_value;
output [63:0] pmpcfg2_value;
// &Regs; @25
reg [1 :0] pmp0cfg_addr_mode;
reg pmp0cfg_executeable;
reg pmp0cfg_lock;
reg pmp0cfg_readable;
reg pmp0cfg_writable;
reg [1 :0] pmp1cfg_addr_mode;
reg pmp1cfg_executeable;
reg pmp1cfg_lock;
reg pmp1cfg_readable;
reg pmp1cfg_writable;
reg [1 :0] pmp2cfg_addr_mode;
reg pmp2cfg_executeable;
reg pmp2cfg_lock;
reg pmp2cfg_readable;
reg pmp2cfg_writable;
reg [1 :0] pmp3cfg_addr_mode;
reg pmp3cfg_executeable;
reg pmp3cfg_lock;
reg pmp3cfg_readable;
reg pmp3cfg_writable;
reg [1 :0] pmp4cfg_addr_mode;
reg pmp4cfg_executeable;
reg pmp4cfg_lock;
reg pmp4cfg_readable;
reg pmp4cfg_writable;
reg [1 :0] pmp5cfg_addr_mode;
reg pmp5cfg_executeable;
reg pmp5cfg_lock;
reg pmp5cfg_readable;
reg pmp5cfg_writable;
reg [1 :0] pmp6cfg_addr_mode;
reg pmp6cfg_executeable;
reg pmp6cfg_lock;
reg pmp6cfg_readable;
reg pmp6cfg_writable;
reg [1 :0] pmp7cfg_addr_mode;
reg pmp7cfg_executeable;
reg pmp7cfg_lock;
reg pmp7cfg_readable;
reg pmp7cfg_writable;
reg [28:0] pmpaddr0_value;
reg [28:0] pmpaddr1_value;
reg [28:0] pmpaddr2_value;
reg [28:0] pmpaddr3_value;
reg [28:0] pmpaddr4_value;
reg [28:0] pmpaddr5_value;
reg [28:0] pmpaddr6_value;
reg [28:0] pmpaddr7_value;
// &Wires; @26
wire [63:0] cp0_pmp_wdata;
wire cpuclk;
wire cpurst_b;
wire [63:0] pmp_cp0_data;
wire [17:0] pmp_csr_sel;
wire [17:0] pmp_csr_wen;
wire pmp_updt_pmp0cfg;
wire pmp_updt_pmp1cfg;
wire pmp_updt_pmp2cfg;
wire pmp_updt_pmp3cfg;
wire pmp_updt_pmp4cfg;
wire pmp_updt_pmp5cfg;
wire pmp_updt_pmp6cfg;
wire pmp_updt_pmp7cfg;
wire pmp_updt_pmpaddr0;
wire pmp_updt_pmpaddr1;
wire pmp_updt_pmpaddr2;
wire pmp_updt_pmpaddr3;
wire pmp_updt_pmpaddr4;
wire pmp_updt_pmpaddr5;
wire pmp_updt_pmpaddr6;
wire pmp_updt_pmpaddr7;
wire [28:0] pmpaddr10_value;
wire [28:0] pmpaddr11_value;
wire [28:0] pmpaddr12_value;
wire [28:0] pmpaddr13_value;
wire [28:0] pmpaddr14_value;
wire [28:0] pmpaddr15_value;
wire [28:0] pmpaddr8_value;
wire [28:0] pmpaddr9_value;
wire [63:0] pmpcfg0_value;
wire [63:0] pmpcfg2_value;
parameter ADDR_WIDTH = 28+1;
// &Force("bus", "pmp_csr_wen", 17, 0); @30
//==========================================================
// PMP Entry Configuration Register
//==========================================================
//------------------------------------------------
//pmpcfg0 register
//------------------------------------------------
assign pmp_updt_pmp0cfg = pmp_csr_wen[0] && !pmp0cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp0cfg_readable <= 1'b0;
pmp0cfg_writable <= 1'b0;
pmp0cfg_executeable <= 1'b0;
pmp0cfg_addr_mode[1:0] <= 2'b0;
pmp0cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp0cfg)
begin
pmp0cfg_readable <= cp0_pmp_wdata[0];
pmp0cfg_writable <= cp0_pmp_wdata[1];
pmp0cfg_executeable <= cp0_pmp_wdata[2];
pmp0cfg_addr_mode[1:0] <= cp0_pmp_wdata[4:3];
pmp0cfg_lock <= cp0_pmp_wdata[7];
end
else
begin
pmp0cfg_readable <= pmp0cfg_readable;
pmp0cfg_writable <= pmp0cfg_writable;
pmp0cfg_executeable <= pmp0cfg_executeable;
pmp0cfg_addr_mode[1:0] <= pmp0cfg_addr_mode[1:0];
pmp0cfg_lock <= pmp0cfg_lock;
end
end
assign pmp_updt_pmp1cfg = pmp_csr_wen[0] && !pmp1cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp1cfg_readable <= 1'b0;
pmp1cfg_writable <= 1'b0;
pmp1cfg_executeable <= 1'b0;
pmp1cfg_addr_mode[1:0] <= 2'b0;
pmp1cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp1cfg)
begin
pmp1cfg_readable <= cp0_pmp_wdata[8];
pmp1cfg_writable <= cp0_pmp_wdata[9];
pmp1cfg_executeable <= cp0_pmp_wdata[10];
pmp1cfg_addr_mode[1:0] <= cp0_pmp_wdata[12:11];
pmp1cfg_lock <= cp0_pmp_wdata[15];
end
else
begin
pmp1cfg_readable <= pmp1cfg_readable;
pmp1cfg_writable <= pmp1cfg_writable;
pmp1cfg_executeable <= pmp1cfg_executeable;
pmp1cfg_addr_mode[1:0] <= pmp1cfg_addr_mode[1:0];
pmp1cfg_lock <= pmp1cfg_lock;
end
end
assign pmp_updt_pmp2cfg = pmp_csr_wen[0] && !pmp2cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp2cfg_readable <= 1'b0;
pmp2cfg_writable <= 1'b0;
pmp2cfg_executeable <= 1'b0;
pmp2cfg_addr_mode[1:0] <= 2'b0;
pmp2cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp2cfg)
begin
pmp2cfg_readable <= cp0_pmp_wdata[16];
pmp2cfg_writable <= cp0_pmp_wdata[17];
pmp2cfg_executeable <= cp0_pmp_wdata[18];
pmp2cfg_addr_mode[1:0] <= cp0_pmp_wdata[20:19];
pmp2cfg_lock <= cp0_pmp_wdata[23];
end
else
begin
pmp2cfg_readable <= pmp2cfg_readable;
pmp2cfg_writable <= pmp2cfg_writable;
pmp2cfg_executeable <= pmp2cfg_executeable;
pmp2cfg_addr_mode[1:0] <= pmp2cfg_addr_mode[1:0];
pmp2cfg_lock <= pmp2cfg_lock;
end
end
assign pmp_updt_pmp3cfg = pmp_csr_wen[0] && !pmp3cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp3cfg_readable <= 1'b0;
pmp3cfg_writable <= 1'b0;
pmp3cfg_executeable <= 1'b0;
pmp3cfg_addr_mode[1:0] <= 2'b0;
pmp3cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp3cfg)
begin
pmp3cfg_readable <= cp0_pmp_wdata[24];
pmp3cfg_writable <= cp0_pmp_wdata[25];
pmp3cfg_executeable <= cp0_pmp_wdata[26];
pmp3cfg_addr_mode[1:0] <= cp0_pmp_wdata[28:27];
pmp3cfg_lock <= cp0_pmp_wdata[31];
end
else
begin
pmp3cfg_readable <= pmp3cfg_readable;
pmp3cfg_writable <= pmp3cfg_writable;
pmp3cfg_executeable <= pmp3cfg_executeable;
pmp3cfg_addr_mode[1:0] <= pmp3cfg_addr_mode[1:0];
pmp3cfg_lock <= pmp3cfg_lock;
end
end
assign pmp_updt_pmp4cfg = pmp_csr_wen[0] && !pmp4cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp4cfg_readable <= 1'b0;
pmp4cfg_writable <= 1'b0;
pmp4cfg_executeable <= 1'b0;
pmp4cfg_addr_mode[1:0] <= 2'b0;
pmp4cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp4cfg)
begin
pmp4cfg_readable <= cp0_pmp_wdata[32];
pmp4cfg_writable <= cp0_pmp_wdata[33];
pmp4cfg_executeable <= cp0_pmp_wdata[34];
pmp4cfg_addr_mode[1:0] <= cp0_pmp_wdata[36:35];
pmp4cfg_lock <= cp0_pmp_wdata[39];
end
else
begin
pmp4cfg_readable <= pmp4cfg_readable;
pmp4cfg_writable <= pmp4cfg_writable;
pmp4cfg_executeable <= pmp4cfg_executeable;
pmp4cfg_addr_mode[1:0] <= pmp4cfg_addr_mode[1:0];
pmp4cfg_lock <= pmp4cfg_lock;
end
end
assign pmp_updt_pmp5cfg = pmp_csr_wen[0] && !pmp5cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp5cfg_readable <= 1'b0;
pmp5cfg_writable <= 1'b0;
pmp5cfg_executeable <= 1'b0;
pmp5cfg_addr_mode[1:0] <= 2'b0;
pmp5cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp5cfg)
begin
pmp5cfg_readable <= cp0_pmp_wdata[40];
pmp5cfg_writable <= cp0_pmp_wdata[41];
pmp5cfg_executeable <= cp0_pmp_wdata[42];
pmp5cfg_addr_mode[1:0] <= cp0_pmp_wdata[44:43];
pmp5cfg_lock <= cp0_pmp_wdata[47];
end
else
begin
pmp5cfg_readable <= pmp5cfg_readable;
pmp5cfg_writable <= pmp5cfg_writable;
pmp5cfg_executeable <= pmp5cfg_executeable;
pmp5cfg_addr_mode[1:0] <= pmp5cfg_addr_mode[1:0];
pmp5cfg_lock <= pmp5cfg_lock;
end
end
assign pmp_updt_pmp6cfg = pmp_csr_wen[0] && !pmp6cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp6cfg_readable <= 1'b0;
pmp6cfg_writable <= 1'b0;
pmp6cfg_executeable <= 1'b0;
pmp6cfg_addr_mode[1:0] <= 2'b0;
pmp6cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp6cfg)
begin
pmp6cfg_readable <= cp0_pmp_wdata[48];
pmp6cfg_writable <= cp0_pmp_wdata[49];
pmp6cfg_executeable <= cp0_pmp_wdata[50];
pmp6cfg_addr_mode[1:0] <= cp0_pmp_wdata[52:51];
pmp6cfg_lock <= cp0_pmp_wdata[55];
end
else
begin
pmp6cfg_readable <= pmp6cfg_readable;
pmp6cfg_writable <= pmp6cfg_writable;
pmp6cfg_executeable <= pmp6cfg_executeable;
pmp6cfg_addr_mode[1:0] <= pmp6cfg_addr_mode[1:0];
pmp6cfg_lock <= pmp6cfg_lock;
end
end
assign pmp_updt_pmp7cfg = pmp_csr_wen[0] && !pmp7cfg_lock;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
pmp7cfg_readable <= 1'b0;
pmp7cfg_writable <= 1'b0;
pmp7cfg_executeable <= 1'b0;
pmp7cfg_addr_mode[1:0] <= 2'b0;
pmp7cfg_lock <= 1'b0;
end
else if(pmp_updt_pmp7cfg)
begin
pmp7cfg_readable <= cp0_pmp_wdata[56];
pmp7cfg_writable <= cp0_pmp_wdata[57];
pmp7cfg_executeable <= cp0_pmp_wdata[58];
pmp7cfg_addr_mode[1:0] <= cp0_pmp_wdata[60:59];
pmp7cfg_lock <= cp0_pmp_wdata[63];
end
else
begin
pmp7cfg_readable <= pmp7cfg_readable;
pmp7cfg_writable <= pmp7cfg_writable;
pmp7cfg_executeable <= pmp7cfg_executeable;
pmp7cfg_addr_mode[1:0] <= pmp7cfg_addr_mode[1:0];
pmp7cfg_lock <= pmp7cfg_lock;
end
end
//------------------------------------------------
//pmpcfg1 register
//------------------------------------------------
// &Force("output","pmpcfg0_value"); @506
// &Force("output","pmpcfg2_value"); @507
assign pmpcfg0_value[31:0] = {pmp3cfg_lock,2'b0,pmp3cfg_addr_mode[1:0],pmp3cfg_executeable,pmp3cfg_writable,pmp3cfg_readable,
pmp2cfg_lock,2'b0,pmp2cfg_addr_mode[1:0],pmp2cfg_executeable,pmp2cfg_writable,pmp2cfg_readable,
pmp1cfg_lock,2'b0,pmp1cfg_addr_mode[1:0],pmp1cfg_executeable,pmp1cfg_writable,pmp1cfg_readable,
pmp0cfg_lock,2'b0,pmp0cfg_addr_mode[1:0],pmp0cfg_executeable,pmp0cfg_writable,pmp0cfg_readable};
assign pmpcfg0_value[63:32] = {pmp7cfg_lock,2'b0,pmp7cfg_addr_mode[1:0],pmp7cfg_executeable,pmp7cfg_writable,pmp7cfg_readable,
pmp6cfg_lock,2'b0,pmp6cfg_addr_mode[1:0],pmp6cfg_executeable,pmp6cfg_writable,pmp6cfg_readable,
pmp5cfg_lock,2'b0,pmp5cfg_addr_mode[1:0],pmp5cfg_executeable,pmp5cfg_writable,pmp5cfg_readable,
pmp4cfg_lock,2'b0,pmp4cfg_addr_mode[1:0],pmp4cfg_executeable,pmp4cfg_writable,pmp4cfg_readable};
assign pmpcfg2_value[63:0] = 64'b0;
//==========================================================
// PMP Entry Address Register
//==========================================================
//------------------------------------------------
//pmpaddr0 register
//------------------------------------------------
assign pmp_updt_pmpaddr0 = pmp_csr_wen[2] && !pmpcfg0_value[7] && !(pmpcfg0_value[15] && (pmpcfg0_value[12:11] == 2'b01)) ;
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr0_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr0)
pmpaddr0_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr0_value[ADDR_WIDTH-1:0] <= pmpaddr0_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr0_value"); @547
assign pmp_updt_pmpaddr1 = pmp_csr_wen[3] && !pmpcfg0_value[15] && !(pmpcfg0_value[23] && (pmpcfg0_value[20:19] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr1_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr1)
pmpaddr1_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr1_value[ADDR_WIDTH-1:0] <= pmpaddr1_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr1_value"); @559
assign pmp_updt_pmpaddr2 = pmp_csr_wen[4] && !pmpcfg0_value[23] && !(pmpcfg0_value[31] && (pmpcfg0_value[28:27] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr2_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr2)
pmpaddr2_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr2_value[ADDR_WIDTH-1:0] <= pmpaddr2_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr2_value"); @571
assign pmp_updt_pmpaddr3 = pmp_csr_wen[5] && !pmpcfg0_value[31] && !(pmpcfg0_value[39] && (pmpcfg0_value[36:35] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr3_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr3)
pmpaddr3_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr3_value[ADDR_WIDTH-1:0] <= pmpaddr3_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr3_value"); @583
assign pmp_updt_pmpaddr4 = pmp_csr_wen[6] && !pmpcfg0_value[39] && !(pmpcfg0_value[47] && (pmpcfg0_value[44:43] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr4_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr4)
pmpaddr4_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr4_value[ADDR_WIDTH-1:0] <= pmpaddr4_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr4_value"); @595
assign pmp_updt_pmpaddr5 = pmp_csr_wen[7] && !pmpcfg0_value[47] && !(pmpcfg0_value[55] && (pmpcfg0_value[52:51] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr5_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr5)
pmpaddr5_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr5_value[ADDR_WIDTH-1:0] <= pmpaddr5_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr5_value"); @607
assign pmp_updt_pmpaddr6 = pmp_csr_wen[8] && !pmpcfg0_value[55] && !(pmpcfg0_value[63] && (pmpcfg0_value[60:59] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr6_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr6)
pmpaddr6_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr6_value[ADDR_WIDTH-1:0] <= pmpaddr6_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr6_value"); @619
assign pmp_updt_pmpaddr7 = pmp_csr_wen[9] && !pmpcfg0_value[63] && !(pmpcfg2_value[7] && (pmpcfg2_value[4:3] == 2'b01));
always @(posedge cpuclk or negedge cpurst_b)
begin
if(!cpurst_b)
pmpaddr7_value[ADDR_WIDTH-1:0] <= {ADDR_WIDTH{1'b0}};
else if(pmp_updt_pmpaddr7)
pmpaddr7_value[ADDR_WIDTH-1:0] <= cp0_pmp_wdata[ADDR_WIDTH+8:9];
else
pmpaddr7_value[ADDR_WIDTH-1:0] <= pmpaddr7_value[ADDR_WIDTH-1:0];
end
// &Force("output","pmpaddr7_value"); @631
assign pmpaddr8_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr9_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr10_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr11_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr12_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr13_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr14_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
assign pmpaddr15_value[ADDR_WIDTH-1:0] = {ADDR_WIDTH{1'b0}};
// &Force("output","pmpaddr8_value"); @655
// &Force("output","pmpaddr9_value"); @667
// &Force("output","pmpaddr10_value"); @679
// &Force("output","pmpaddr11_value"); @691
// &Force("output","pmpaddr12_value"); @703
// &Force("output","pmpaddr13_value"); @715
// &Force("output","pmpaddr14_value"); @727
// &Force("output","pmpaddr15_value"); @739
//----------------------------------------------------------
// Interface to CP0
//----------------------------------------------------------
assign pmp_cp0_data[63:0] = {64{pmp_csr_sel[0]}} & pmpcfg0_value[63:0]
| {64{pmp_csr_sel[1]}} & pmpcfg2_value[63:0]
| {64{pmp_csr_sel[2]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr0_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[3]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr1_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[4]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr2_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[5]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr3_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[6]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr4_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[7]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr5_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[8]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr6_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[9]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr7_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[10]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr8_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[11]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr9_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[12]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr10_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[13]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr11_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[14]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr12_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[15]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr13_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[16]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr14_value[ADDR_WIDTH-1:0], 9'b0}
| {64{pmp_csr_sel[17]}} & {{(64-ADDR_WIDTH-9){1'b0}}, pmpaddr15_value[ADDR_WIDTH-1:0], 9'b0};
// &ModuleEnd; @765
endmodule |
module ct_pmp_acc(
cp0_pmp_mpp,
cur_priv_mode,
mmu_pmp_pa_y,
pmp_mmu_flg_y,
pmp_mprv_status_y,
pmpaddr0_value,
pmpaddr1_value,
pmpaddr2_value,
pmpaddr3_value,
pmpaddr4_value,
pmpaddr5_value,
pmpaddr6_value,
pmpaddr7_value,
pmpcfg0_value,
pmpcfg2_value
);
// &Ports; @25
input [1 :0] cp0_pmp_mpp;
input [1 :0] cur_priv_mode;
input [27:0] mmu_pmp_pa_y;
input pmp_mprv_status_y;
input [28:0] pmpaddr0_value;
input [28:0] pmpaddr1_value;
input [28:0] pmpaddr2_value;
input [28:0] pmpaddr3_value;
input [28:0] pmpaddr4_value;
input [28:0] pmpaddr5_value;
input [28:0] pmpaddr6_value;
input [28:0] pmpaddr7_value;
input [63:0] pmpcfg0_value;
input [63:0] pmpcfg2_value;
output [3 :0] pmp_mmu_flg_y;
// &Regs; @26
reg [3 :0] pmp_mmu_flg_y;
// &Wires; @27
wire [1 :0] addr_match_mode0;
wire [1 :0] addr_match_mode1;
wire [1 :0] addr_match_mode2;
wire [1 :0] addr_match_mode3;
wire [1 :0] addr_match_mode4;
wire [1 :0] addr_match_mode5;
wire [1 :0] addr_match_mode6;
wire [1 :0] addr_match_mode7;
wire cp0_mach_mode;
wire [1 :0] cp0_pmp_mpp;
wire [1 :0] cp0_priv_mode;
wire [1 :0] cur_priv_mode;
wire mmu_addr_ge_bottom0;
wire mmu_addr_ge_bottom1;
wire mmu_addr_ge_bottom2;
wire mmu_addr_ge_bottom3;
wire mmu_addr_ge_bottom4;
wire mmu_addr_ge_bottom5;
wire mmu_addr_ge_bottom6;
wire mmu_addr_ge_bottom7;
wire mmu_addr_ge_upaddr0;
wire mmu_addr_ge_upaddr1;
wire mmu_addr_ge_upaddr2;
wire mmu_addr_ge_upaddr3;
wire mmu_addr_ge_upaddr4;
wire mmu_addr_ge_upaddr5;
wire mmu_addr_ge_upaddr6;
wire mmu_addr_ge_upaddr7;
wire [27:0] mmu_pmp_pa_y;
wire [3 :0] pmp_default_flg;
wire [15:0] pmp_hit;
wire pmp_mmu_hit0;
wire pmp_mmu_hit1;
wire pmp_mmu_hit2;
wire pmp_mmu_hit3;
wire pmp_mmu_hit4;
wire pmp_mmu_hit5;
wire pmp_mmu_hit6;
wire pmp_mmu_hit7;
wire pmp_mprv_status_y;
wire [28:0] pmpaddr0_value;
wire [28:0] pmpaddr1_value;
wire [28:0] pmpaddr2_value;
wire [28:0] pmpaddr3_value;
wire [28:0] pmpaddr4_value;
wire [28:0] pmpaddr5_value;
wire [28:0] pmpaddr6_value;
wire [28:0] pmpaddr7_value;
wire [63:0] pmpcfg0_value;
wire [63:0] pmpcfg2_value;
// priviledged mode judgement
assign cp0_priv_mode[1:0] = pmp_mprv_status_y ? cp0_pmp_mpp[1:0]
: cur_priv_mode[1:0];
assign cp0_mach_mode = cp0_priv_mode[1:0] == 2'b11;
// get bottom compare infor from last entry
// &Force("nonport", "mmu_addr_ge_upaddr7"); @35
assign {mmu_addr_ge_bottom7, mmu_addr_ge_bottom6,
mmu_addr_ge_bottom5, mmu_addr_ge_bottom4,
mmu_addr_ge_bottom3, mmu_addr_ge_bottom2,
mmu_addr_ge_bottom1, mmu_addr_ge_bottom0} =
{mmu_addr_ge_upaddr6, mmu_addr_ge_upaddr5,
mmu_addr_ge_upaddr4, mmu_addr_ge_upaddr3,
mmu_addr_ge_upaddr2, mmu_addr_ge_upaddr1,
mmu_addr_ge_upaddr0, 1'b1};
// gather the hit information
assign pmp_hit[7:0] = {pmp_mmu_hit7, pmp_mmu_hit6,
pmp_mmu_hit5, pmp_mmu_hit4,
pmp_mmu_hit3, pmp_mmu_hit2,
pmp_mmu_hit1, pmp_mmu_hit0};
// get addr match mode from pmp configure register
assign addr_match_mode0[1:0] = pmpcfg0_value[4:3] ;
assign addr_match_mode1[1:0] = pmpcfg0_value[12:11];
assign addr_match_mode2[1:0] = pmpcfg0_value[20:19];
assign addr_match_mode3[1:0] = pmpcfg0_value[28:27];
assign addr_match_mode4[1:0] = pmpcfg0_value[36:35];
assign addr_match_mode5[1:0] = pmpcfg0_value[44:43];
assign addr_match_mode6[1:0] = pmpcfg0_value[52:51];
assign addr_match_mode7[1:0] = pmpcfg0_value[60:59];
// &ConnRule(s/_x/0/); @61
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_0"); @62
ct_pmp_comp_hit x_ct_pmp_comp_hit_0 (
.addr_match_mode_x (addr_match_mode0 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom0 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr0 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit0 ),
.pmpaddr_x_value (pmpaddr0_value )
);
// &ConnRule(s/_x/1/); @64
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_1"); @65
ct_pmp_comp_hit x_ct_pmp_comp_hit_1 (
.addr_match_mode_x (addr_match_mode1 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom1 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr1 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit1 ),
.pmpaddr_x_value (pmpaddr1_value )
);
// &ConnRule(s/_x/2/); @67
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_2"); @68
ct_pmp_comp_hit x_ct_pmp_comp_hit_2 (
.addr_match_mode_x (addr_match_mode2 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom2 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr2 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit2 ),
.pmpaddr_x_value (pmpaddr2_value )
);
// &ConnRule(s/_x/3/); @70
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_3"); @71
ct_pmp_comp_hit x_ct_pmp_comp_hit_3 (
.addr_match_mode_x (addr_match_mode3 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom3 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr3 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit3 ),
.pmpaddr_x_value (pmpaddr3_value )
);
// &ConnRule(s/_x/4/); @73
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_4"); @74
ct_pmp_comp_hit x_ct_pmp_comp_hit_4 (
.addr_match_mode_x (addr_match_mode4 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom4 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr4 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit4 ),
.pmpaddr_x_value (pmpaddr4_value )
);
// &ConnRule(s/_x/5/); @76
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_5"); @77
ct_pmp_comp_hit x_ct_pmp_comp_hit_5 (
.addr_match_mode_x (addr_match_mode5 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom5 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr5 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit5 ),
.pmpaddr_x_value (pmpaddr5_value )
);
// &ConnRule(s/_x/6/); @79
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_6"); @80
ct_pmp_comp_hit x_ct_pmp_comp_hit_6 (
.addr_match_mode_x (addr_match_mode6 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom6 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr6 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit6 ),
.pmpaddr_x_value (pmpaddr6_value )
);
// &ConnRule(s/_x/7/); @82
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_7"); @83
ct_pmp_comp_hit x_ct_pmp_comp_hit_7 (
.addr_match_mode_x (addr_match_mode7 ),
.mmu_addr_ge_bottom_x (mmu_addr_ge_bottom7 ),
.mmu_addr_ge_upaddr_x (mmu_addr_ge_upaddr7 ),
.mmu_pmp_pa_y (mmu_pmp_pa_y ),
.pmp_mmu_hit_x (pmp_mmu_hit7 ),
.pmpaddr_x_value (pmpaddr7_value )
);
// &Force("nonport", "mmu_addr_ge_upaddr15"); @87
// &ConnRule(s/_x/8/); @113
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_8"); @114
// &ConnRule(s/_x/9/); @116
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_9"); @117
// &ConnRule(s/_x/10/); @119
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_10"); @120
// &ConnRule(s/_x/11/); @122
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_11"); @123
// &ConnRule(s/_x/12/); @125
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_12"); @126
// &ConnRule(s/_x/13/); @128
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_13"); @129
// &ConnRule(s/_x/14/); @131
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_14"); @132
// &ConnRule(s/_x/15/); @134
// &Instance("ct_pmp_comp_hit", "x_ct_pmp_comp_hit_15"); @135
assign pmp_hit[15:8] = 8'b0;
//----------------------------------------------------------
//priority encoder for access_deny
//----------------------------------------------------------
assign pmp_default_flg[3:0] = cp0_mach_mode ? 4'b0111 : 4'b0;
// &CombBeg; @145
always @( pmpcfg0_value[34:31]
or pmpcfg0_value[63]
or pmpcfg0_value[26:23]
or pmpcfg2_value[34:31]
or pmpcfg2_value[18:15]
or pmpcfg0_value[10:07]
or pmpcfg0_value[42:39]
or pmp_default_flg[3:0]
or pmpcfg0_value[2:0]
or pmpcfg2_value[58:55]
or pmpcfg0_value[58:55]
or pmp_hit[15:0]
or pmpcfg0_value[18:15]
or pmpcfg0_value[50:47]
or pmpcfg2_value[10:07]
or pmpcfg2_value[42:39]
or pmpcfg2_value[50:47]
or pmpcfg2_value[26:23]
or pmpcfg2_value[63]
or pmpcfg2_value[2:0])
begin
casez(pmp_hit[15:0])
16'b???????????????1 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[07], pmpcfg0_value[2:0]};
16'b??????????????10 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[15], pmpcfg0_value[10:8]};
16'b?????????????100 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[23], pmpcfg0_value[18:16]};
16'b????????????1000 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[31], pmpcfg0_value[26:24]};
16'b???????????10000 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[39], pmpcfg0_value[34:32]};
16'b??????????100000 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[47], pmpcfg0_value[42:40]};
16'b?????????1000000 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[55], pmpcfg0_value[50:48]};
16'b????????10000000 : pmp_mmu_flg_y[3:0] = {pmpcfg0_value[63], pmpcfg0_value[58:56]};
16'b???????100000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[07], pmpcfg2_value[2:0]};
16'b??????1000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[15], pmpcfg2_value[10:8]};
16'b?????10000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[23], pmpcfg2_value[18:16]};
16'b????100000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[31], pmpcfg2_value[26:24]};
16'b???1000000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[39], pmpcfg2_value[34:32]};
16'b??10000000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[47], pmpcfg2_value[42:40]};
16'b?100000000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[55], pmpcfg2_value[50:48]};
16'b1000000000000000 : pmp_mmu_flg_y[3:0] = {pmpcfg2_value[63], pmpcfg2_value[58:56]};
16'b0000000000000000 : pmp_mmu_flg_y[3:0] = pmp_default_flg[3:0];
default : pmp_mmu_flg_y[3:0] = {4{1'bx}};
endcase
// &CombEnd; @166
end
// &ModuleEnd; @168
endmodule |
module ct_pmp_top(
cp0_pmp_icg_en,
cp0_pmp_mpp,
cp0_pmp_mprv,
cp0_pmp_reg_num,
cp0_pmp_wdata,
cp0_pmp_wreg,
cp0_yy_priv_mode,
cpurst_b,
forever_cpuclk,
mmu_pmp_fetch3,
mmu_pmp_pa0,
mmu_pmp_pa1,
mmu_pmp_pa2,
mmu_pmp_pa3,
mmu_pmp_pa4,
pad_yy_icg_scan_en,
pmp_cp0_data,
pmp_mmu_flg0,
pmp_mmu_flg1,
pmp_mmu_flg2,
pmp_mmu_flg3,
pmp_mmu_flg4
);
// &Ports; @25
input cp0_pmp_icg_en;
input [1 :0] cp0_pmp_mpp;
input cp0_pmp_mprv;
input [4 :0] cp0_pmp_reg_num;
input [63:0] cp0_pmp_wdata;
input cp0_pmp_wreg;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input forever_cpuclk;
input mmu_pmp_fetch3;
input [27:0] mmu_pmp_pa0;
input [27:0] mmu_pmp_pa1;
input [27:0] mmu_pmp_pa2;
input [27:0] mmu_pmp_pa3;
input [27:0] mmu_pmp_pa4;
input pad_yy_icg_scan_en;
output [63:0] pmp_cp0_data;
output [3 :0] pmp_mmu_flg0;
output [3 :0] pmp_mmu_flg1;
output [3 :0] pmp_mmu_flg2;
output [3 :0] pmp_mmu_flg3;
output [3 :0] pmp_mmu_flg4;
// &Regs; @26
// &Wires; @27
wire [11:0] cp0_pmp_addr;
wire cp0_pmp_icg_en;
wire [1 :0] cp0_pmp_mpp;
wire cp0_pmp_mprv;
wire [4 :0] cp0_pmp_reg_num;
wire [63:0] cp0_pmp_wdata;
wire cp0_pmp_wreg;
wire [1 :0] cp0_yy_priv_mode;
wire cpuclk;
wire cpurst_b;
wire [1 :0] cur_priv_mode;
wire forever_cpuclk;
wire mmu_pmp_fetch3;
wire [27:0] mmu_pmp_pa0;
wire [27:0] mmu_pmp_pa1;
wire [27:0] mmu_pmp_pa2;
wire [27:0] mmu_pmp_pa3;
wire [27:0] mmu_pmp_pa4;
wire pad_yy_icg_scan_en;
wire [63:0] pmp_cp0_data;
wire [17:0] pmp_csr_sel;
wire [17:0] pmp_csr_wen;
wire [3 :0] pmp_mmu_flg0;
wire [3 :0] pmp_mmu_flg1;
wire [3 :0] pmp_mmu_flg2;
wire [3 :0] pmp_mmu_flg3;
wire [3 :0] pmp_mmu_flg4;
wire pmp_mprv_status0;
wire pmp_mprv_status1;
wire pmp_mprv_status2;
wire pmp_mprv_status3;
wire pmp_mprv_status4;
wire [28:0] pmpaddr0_value;
wire [28:0] pmpaddr1_value;
wire [28:0] pmpaddr2_value;
wire [28:0] pmpaddr3_value;
wire [28:0] pmpaddr4_value;
wire [28:0] pmpaddr5_value;
wire [28:0] pmpaddr6_value;
wire [28:0] pmpaddr7_value;
wire [63:0] pmpcfg0_value;
wire [63:0] pmpcfg2_value;
wire wr_pmp_regs;
// &Force("output", "pmp_biu_pready"); @30
// &Force("output", "pmp_biu_perr"); @31
// &Instance("gated_clk_cell", "x_l2pmp_gateclk"); @33
// &Connect( .clk_in (forever_cpuclk), @34
// .external_en(1'b0 ), @35
// .global_en (1'b1 ), @36
// .module_en (cp0_pmp_icg_en), @37
// .local_en (l2pmp_clk_en ), @38
// .clk_out (l2pmp_clk ) @39
// ); @40
// &Instance("ct_l2pmp_apbif", "x_ct_l2pmp_apbif"); @42
// &Instance("ct_l2pmp_regs", "x_ct_l2pmp_regs"); @44
// &ConnRule(s/g_y/g0/); @46
// &ConnRule(s/a_y/a0/); @47
// &Instance("ct_l2pmp_func", "x_ct_l2pmp_func0"); @48
// &ConnRule(s/g_y/g1/); @50
// &ConnRule(s/a_y/a1/); @51
// &Instance("ct_l2pmp_func", "x_ct_l2pmp_func1"); @52
// &ConnRule(s/g_y/g2/); @54
// &ConnRule(s/a_y/a2/); @55
// &Instance("ct_l2pmp_func", "x_ct_l2pmp_func2"); @56
// &ConnRule(s/g_y/g3/); @58
// &ConnRule(s/a_y/a3/); @59
// &Instance("ct_l2pmp_func", "x_ct_l2pmp_func3"); @60
// &ConnRule(s/g_y/g4/); @62
// &ConnRule(s/a_y/a4/); @63
// &Instance("ct_l2pmp_func", "x_ct_l2pmp_func4"); @64
// &Force("input", "cp0_pmp_reg_num"); &Force("bus", "cp0_pmp_reg_num", 4, 0); @66
// &Force("input", "cp0_pmp_wdata"); &Force("bus", "cp0_pmp_wdata", 63, 0); @67
// &Force("input", "cp0_pmp_mpp"); &Force("bus", "cp0_pmp_mpp", 1, 0); @68
// &Force("input", "cp0_pmp_mprv"); @69
// &Force("input", "cp0_pmp_wreg"); @70
// &Force("input", "mmu_pmp_fetch3"); @71
parameter PMPCFG0 = 12'h3A0;
parameter PMPCFG2 = 12'h3A2;
parameter PMPADDR0 = 12'h3B0;
parameter PMPADDR1 = 12'h3B1;
parameter PMPADDR2 = 12'h3B2;
parameter PMPADDR3 = 12'h3B3;
parameter PMPADDR4 = 12'h3B4;
parameter PMPADDR5 = 12'h3B5;
parameter PMPADDR6 = 12'h3B6;
parameter PMPADDR7 = 12'h3B7;
parameter PMPADDR8 = 12'h3B8;
parameter PMPADDR9 = 12'h3B9;
parameter PMPADDR10 = 12'h3BA;
parameter PMPADDR11 = 12'h3BB;
parameter PMPADDR12 = 12'h3BC;
parameter PMPADDR13 = 12'h3BD;
parameter PMPADDR14 = 12'h3BE;
parameter PMPADDR15 = 12'h3BF;
assign cp0_pmp_addr[11:0] = {7'b0011101, cp0_pmp_reg_num[4:0]};
assign pmp_csr_sel[0] = cp0_pmp_addr[11:0] == PMPCFG0;
assign pmp_csr_sel[1] = cp0_pmp_addr[11:0] == PMPCFG2;
assign pmp_csr_sel[2] = cp0_pmp_addr[11:0] == PMPADDR0;
assign pmp_csr_sel[3] = cp0_pmp_addr[11:0] == PMPADDR1;
assign pmp_csr_sel[4] = cp0_pmp_addr[11:0] == PMPADDR2;
assign pmp_csr_sel[5] = cp0_pmp_addr[11:0] == PMPADDR3;
assign pmp_csr_sel[6] = cp0_pmp_addr[11:0] == PMPADDR4;
assign pmp_csr_sel[7] = cp0_pmp_addr[11:0] == PMPADDR5;
assign pmp_csr_sel[8] = cp0_pmp_addr[11:0] == PMPADDR6;
assign pmp_csr_sel[9] = cp0_pmp_addr[11:0] == PMPADDR7;
assign pmp_csr_sel[10] = cp0_pmp_addr[11:0] == PMPADDR8;
assign pmp_csr_sel[11] = cp0_pmp_addr[11:0] == PMPADDR9;
assign pmp_csr_sel[12] = cp0_pmp_addr[11:0] == PMPADDR10;
assign pmp_csr_sel[13] = cp0_pmp_addr[11:0] == PMPADDR11;
assign pmp_csr_sel[14] = cp0_pmp_addr[11:0] == PMPADDR12;
assign pmp_csr_sel[15] = cp0_pmp_addr[11:0] == PMPADDR13;
assign pmp_csr_sel[16] = cp0_pmp_addr[11:0] == PMPADDR14;
assign pmp_csr_sel[17] = cp0_pmp_addr[11:0] == PMPADDR15;
assign pmp_csr_wen[17:0] = pmp_csr_sel[17:0] & {18{cp0_pmp_wreg}};
assign wr_pmp_regs = |pmp_csr_wen[17:0];
// &Instance("gated_clk_cell", "x_pmp_gated_clk"); @118
gated_clk_cell x_pmp_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (cpuclk ),
.external_en (1'b0 ),
.global_en (1'b1 ),
.local_en (wr_pmp_regs ),
.module_en (cp0_pmp_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( @119
// .clk_in (forever_cpuclk), @120
// .global_en (1'b1 ), @121
// .module_en (cp0_pmp_icg_en), @122
// .local_en (wr_pmp_regs ), @123
// .external_en (1'b0 ), @124
// .clk_out (cpuclk ), @125
// ); @126
// &Instance("ct_pmp_regs"); @128
ct_pmp_regs x_ct_pmp_regs (
.cp0_pmp_wdata (cp0_pmp_wdata ),
.cpuclk (cpuclk ),
.cpurst_b (cpurst_b ),
.pmp_cp0_data (pmp_cp0_data ),
.pmp_csr_sel (pmp_csr_sel ),
.pmp_csr_wen (pmp_csr_wen ),
.pmpaddr0_value (pmpaddr0_value),
.pmpaddr1_value (pmpaddr1_value),
.pmpaddr2_value (pmpaddr2_value),
.pmpaddr3_value (pmpaddr3_value),
.pmpaddr4_value (pmpaddr4_value),
.pmpaddr5_value (pmpaddr5_value),
.pmpaddr6_value (pmpaddr6_value),
.pmpaddr7_value (pmpaddr7_value),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
assign cur_priv_mode[1:0] = cp0_yy_priv_mode[1:0];
assign pmp_mprv_status0 = cp0_pmp_mprv;
assign pmp_mprv_status1 = cp0_pmp_mprv;
assign pmp_mprv_status2 = 1'b0;
assign pmp_mprv_status3 = cp0_pmp_mprv && !mmu_pmp_fetch3;
assign pmp_mprv_status4 = cp0_pmp_mprv;
// &ConnRule(s/_y/0/); @136
// &Instance("ct_pmp_acc", "x_ct_pmp_acc0"); @137
ct_pmp_acc x_ct_pmp_acc0 (
.cp0_pmp_mpp (cp0_pmp_mpp ),
.cur_priv_mode (cur_priv_mode ),
.mmu_pmp_pa_y (mmu_pmp_pa0 ),
.pmp_mmu_flg_y (pmp_mmu_flg0 ),
.pmp_mprv_status_y (pmp_mprv_status0 ),
.pmpaddr0_value (pmpaddr0_value ),
.pmpaddr1_value (pmpaddr1_value ),
.pmpaddr2_value (pmpaddr2_value ),
.pmpaddr3_value (pmpaddr3_value ),
.pmpaddr4_value (pmpaddr4_value ),
.pmpaddr5_value (pmpaddr5_value ),
.pmpaddr6_value (pmpaddr6_value ),
.pmpaddr7_value (pmpaddr7_value ),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
// &ConnRule(s/_y/1/); @139
// &Instance("ct_pmp_acc", "x_ct_pmp_acc1"); @140
ct_pmp_acc x_ct_pmp_acc1 (
.cp0_pmp_mpp (cp0_pmp_mpp ),
.cur_priv_mode (cur_priv_mode ),
.mmu_pmp_pa_y (mmu_pmp_pa1 ),
.pmp_mmu_flg_y (pmp_mmu_flg1 ),
.pmp_mprv_status_y (pmp_mprv_status1 ),
.pmpaddr0_value (pmpaddr0_value ),
.pmpaddr1_value (pmpaddr1_value ),
.pmpaddr2_value (pmpaddr2_value ),
.pmpaddr3_value (pmpaddr3_value ),
.pmpaddr4_value (pmpaddr4_value ),
.pmpaddr5_value (pmpaddr5_value ),
.pmpaddr6_value (pmpaddr6_value ),
.pmpaddr7_value (pmpaddr7_value ),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
// &ConnRule(s/_y/2/); @142
// &Instance("ct_pmp_acc", "x_ct_pmp_acc2"); @143
ct_pmp_acc x_ct_pmp_acc2 (
.cp0_pmp_mpp (cp0_pmp_mpp ),
.cur_priv_mode (cur_priv_mode ),
.mmu_pmp_pa_y (mmu_pmp_pa2 ),
.pmp_mmu_flg_y (pmp_mmu_flg2 ),
.pmp_mprv_status_y (pmp_mprv_status2 ),
.pmpaddr0_value (pmpaddr0_value ),
.pmpaddr1_value (pmpaddr1_value ),
.pmpaddr2_value (pmpaddr2_value ),
.pmpaddr3_value (pmpaddr3_value ),
.pmpaddr4_value (pmpaddr4_value ),
.pmpaddr5_value (pmpaddr5_value ),
.pmpaddr6_value (pmpaddr6_value ),
.pmpaddr7_value (pmpaddr7_value ),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
// &ConnRule(s/_y/3/); @145
// &Instance("ct_pmp_acc", "x_ct_pmp_acc3"); @146
ct_pmp_acc x_ct_pmp_acc3 (
.cp0_pmp_mpp (cp0_pmp_mpp ),
.cur_priv_mode (cur_priv_mode ),
.mmu_pmp_pa_y (mmu_pmp_pa3 ),
.pmp_mmu_flg_y (pmp_mmu_flg3 ),
.pmp_mprv_status_y (pmp_mprv_status3 ),
.pmpaddr0_value (pmpaddr0_value ),
.pmpaddr1_value (pmpaddr1_value ),
.pmpaddr2_value (pmpaddr2_value ),
.pmpaddr3_value (pmpaddr3_value ),
.pmpaddr4_value (pmpaddr4_value ),
.pmpaddr5_value (pmpaddr5_value ),
.pmpaddr6_value (pmpaddr6_value ),
.pmpaddr7_value (pmpaddr7_value ),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
// &ConnRule(s/_y/4/); @148
// &Instance("ct_pmp_acc", "x_ct_pmp_acc4"); @149
ct_pmp_acc x_ct_pmp_acc4 (
.cp0_pmp_mpp (cp0_pmp_mpp ),
.cur_priv_mode (cur_priv_mode ),
.mmu_pmp_pa_y (mmu_pmp_pa4 ),
.pmp_mmu_flg_y (pmp_mmu_flg4 ),
.pmp_mprv_status_y (pmp_mprv_status4 ),
.pmpaddr0_value (pmpaddr0_value ),
.pmpaddr1_value (pmpaddr1_value ),
.pmpaddr2_value (pmpaddr2_value ),
.pmpaddr3_value (pmpaddr3_value ),
.pmpaddr4_value (pmpaddr4_value ),
.pmpaddr5_value (pmpaddr5_value ),
.pmpaddr6_value (pmpaddr6_value ),
.pmpaddr7_value (pmpaddr7_value ),
.pmpcfg0_value (pmpcfg0_value ),
.pmpcfg2_value (pmpcfg2_value )
);
// &ModuleEnd; @170
endmodule |
module ct_vfpu_cbus(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idu_vfpu_rf_pipe6_gateclk_sel,
idu_vfpu_rf_pipe6_iid,
idu_vfpu_rf_pipe6_sel,
idu_vfpu_rf_pipe7_gateclk_sel,
idu_vfpu_rf_pipe7_iid,
idu_vfpu_rf_pipe7_sel,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
vfpu_rtu_pipe6_cmplt,
vfpu_rtu_pipe6_iid,
vfpu_rtu_pipe7_cmplt,
vfpu_rtu_pipe7_iid
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input idu_vfpu_rf_pipe6_gateclk_sel;
input [6:0] idu_vfpu_rf_pipe6_iid;
input idu_vfpu_rf_pipe6_sel;
input idu_vfpu_rf_pipe7_gateclk_sel;
input [6:0] idu_vfpu_rf_pipe7_iid;
input idu_vfpu_rf_pipe7_sel;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
output vfpu_rtu_pipe6_cmplt;
output [6:0] vfpu_rtu_pipe6_iid;
output vfpu_rtu_pipe7_cmplt;
output [6:0] vfpu_rtu_pipe7_iid;
// &Regs; @24
reg [6:0] cbus_pipe6_iid;
reg cbus_pipe6_inst_vld;
reg [6:0] cbus_pipe7_iid;
reg cbus_pipe7_inst_vld;
// &Wires; @25
wire cbus_pipe6_cmplt;
wire cbus_pipe6_gateclk_cmplt;
wire cbus_pipe7_cmplt;
wire cbus_pipe7_gateclk_cmplt;
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire idu_vfpu_rf_pipe6_gateclk_sel;
wire [6:0] idu_vfpu_rf_pipe6_iid;
wire idu_vfpu_rf_pipe6_sel;
wire idu_vfpu_rf_pipe7_gateclk_sel;
wire [6:0] idu_vfpu_rf_pipe7_iid;
wire idu_vfpu_rf_pipe7_sel;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
wire vfpu_inst_vld_clk;
wire vfpu_inst_vld_clk_en;
wire vfpu_pipe6_data_clk;
wire vfpu_pipe6_data_clk_en;
wire vfpu_pipe7_data_clk;
wire vfpu_pipe7_data_clk_en;
wire vfpu_rtu_pipe6_cmplt;
wire [6:0] vfpu_rtu_pipe6_iid;
wire vfpu_rtu_pipe7_cmplt;
wire [6:0] vfpu_rtu_pipe7_iid;
// &Depend("cpu_cfig.h"); @26
// //&Force("bus","vfpu_yy_xx_expt_en",31,0); @27
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign vfpu_inst_vld_clk_en = cbus_pipe6_gateclk_cmplt
|| cbus_pipe7_gateclk_cmplt
|| cbus_pipe6_inst_vld
|| cbus_pipe7_inst_vld;
// &Instance("gated_clk_cell", "x_vfpu_inst_vld_gated_clk"); @36
gated_clk_cell x_vfpu_inst_vld_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vfpu_inst_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vfpu_inst_vld_clk_en),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_vfpu_icg_en), @40
// .local_en (vfpu_inst_vld_clk_en), @41
// .clk_out (vfpu_inst_vld_clk)); @42
//==========================================================
// Pipe6 Complete Signals
//==========================================================
assign cbus_pipe6_cmplt = idu_vfpu_rf_pipe6_sel;
assign cbus_pipe6_gateclk_cmplt = idu_vfpu_rf_pipe6_gateclk_sel;
//----------------------------------------------------------
// Complete Instruction Valid
//----------------------------------------------------------
always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe6_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
cbus_pipe6_inst_vld <= 1'b0;
else
cbus_pipe6_inst_vld <= cbus_pipe6_cmplt;
end
//output to RTU
assign vfpu_rtu_pipe6_cmplt = cbus_pipe6_inst_vld;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign vfpu_pipe6_data_clk_en = cbus_pipe6_gateclk_cmplt;
// &Instance("gated_clk_cell", "x_vfpu_pipe6_data_gated_clk"); @70
gated_clk_cell x_vfpu_pipe6_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vfpu_pipe6_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vfpu_pipe6_data_clk_en),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @71
// .external_en (1'b0), @72
// .global_en (cp0_yy_clk_en), @73
// .module_en (cp0_vfpu_icg_en), @74
// .local_en (vfpu_pipe6_data_clk_en), @75
// .clk_out (vfpu_pipe6_data_clk)); @76
//----------------------------------------------------------
// Complete Data
//----------------------------------------------------------
always @(posedge vfpu_pipe6_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe6_iid[6:0] <= 7'b0;
else if(cbus_pipe6_cmplt)
cbus_pipe6_iid[6:0] <= idu_vfpu_rf_pipe6_iid[6:0];
else
cbus_pipe6_iid[6:0] <= cbus_pipe6_iid[6:0];
end
//output to RTU
assign vfpu_rtu_pipe6_iid[6:0] = cbus_pipe6_iid[6:0];
//==========================================================
// Pipe6 Complete Signals
//==========================================================
assign cbus_pipe7_cmplt = idu_vfpu_rf_pipe7_sel;
assign cbus_pipe7_gateclk_cmplt = idu_vfpu_rf_pipe7_gateclk_sel;
//----------------------------------------------------------
// Complete Instruction Valid
//----------------------------------------------------------
always @(posedge vfpu_inst_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe7_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
cbus_pipe7_inst_vld <= 1'b0;
else
cbus_pipe7_inst_vld <= cbus_pipe7_cmplt;
end
//output to RTU
assign vfpu_rtu_pipe7_cmplt = cbus_pipe7_inst_vld;
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign vfpu_pipe7_data_clk_en = cbus_pipe7_gateclk_cmplt;
// &Instance("gated_clk_cell", "x_vfpu_pipe7_data_gated_clk"); @119
gated_clk_cell x_vfpu_pipe7_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (vfpu_pipe7_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (vfpu_pipe7_data_clk_en),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @120
// .external_en (1'b0), @121
// .global_en (cp0_yy_clk_en), @122
// .module_en (cp0_vfpu_icg_en), @123
// .local_en (vfpu_pipe7_data_clk_en), @124
// .clk_out (vfpu_pipe7_data_clk)); @125
//----------------------------------------------------------
// Complete Data
//----------------------------------------------------------
always @(posedge vfpu_pipe7_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe7_iid[6:0] <= 7'b0;
else if(cbus_pipe7_cmplt)
cbus_pipe7_iid[6:0] <= idu_vfpu_rf_pipe7_iid[6:0];
else
cbus_pipe7_iid[6:0] <= cbus_pipe7_iid[6:0];
end
//output to RTU
assign vfpu_rtu_pipe7_iid[6:0] = cbus_pipe7_iid[6:0];
// &ModuleEnd; @143
endmodule |
module ct_iu_rbus(
alu_rbus_ex1_pipe0_data,
alu_rbus_ex1_pipe0_data_vld,
alu_rbus_ex1_pipe0_fwd_data,
alu_rbus_ex1_pipe0_fwd_vld,
alu_rbus_ex1_pipe0_preg,
alu_rbus_ex1_pipe1_data,
alu_rbus_ex1_pipe1_data_vld,
alu_rbus_ex1_pipe1_fwd_data,
alu_rbus_ex1_pipe1_fwd_vld,
alu_rbus_ex1_pipe1_preg,
cp0_iu_ex3_rslt_data,
cp0_iu_ex3_rslt_preg,
cp0_iu_ex3_rslt_vld,
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
div_rbus_data,
div_rbus_pipe0_data_vld,
div_rbus_preg,
forever_cpuclk,
had_idu_wbbr_data,
had_idu_wbbr_vld,
iu_idu_ex1_pipe0_fwd_preg,
iu_idu_ex1_pipe0_fwd_preg_data,
iu_idu_ex1_pipe0_fwd_preg_vld,
iu_idu_ex1_pipe1_fwd_preg,
iu_idu_ex1_pipe1_fwd_preg_data,
iu_idu_ex1_pipe1_fwd_preg_vld,
iu_idu_ex2_pipe0_wb_preg,
iu_idu_ex2_pipe0_wb_preg_data,
iu_idu_ex2_pipe0_wb_preg_dup0,
iu_idu_ex2_pipe0_wb_preg_dup1,
iu_idu_ex2_pipe0_wb_preg_dup2,
iu_idu_ex2_pipe0_wb_preg_dup3,
iu_idu_ex2_pipe0_wb_preg_dup4,
iu_idu_ex2_pipe0_wb_preg_expand,
iu_idu_ex2_pipe0_wb_preg_vld,
iu_idu_ex2_pipe0_wb_preg_vld_dup0,
iu_idu_ex2_pipe0_wb_preg_vld_dup1,
iu_idu_ex2_pipe0_wb_preg_vld_dup2,
iu_idu_ex2_pipe0_wb_preg_vld_dup3,
iu_idu_ex2_pipe0_wb_preg_vld_dup4,
iu_idu_ex2_pipe1_wb_preg,
iu_idu_ex2_pipe1_wb_preg_data,
iu_idu_ex2_pipe1_wb_preg_dup0,
iu_idu_ex2_pipe1_wb_preg_dup1,
iu_idu_ex2_pipe1_wb_preg_dup2,
iu_idu_ex2_pipe1_wb_preg_dup3,
iu_idu_ex2_pipe1_wb_preg_dup4,
iu_idu_ex2_pipe1_wb_preg_expand,
iu_idu_ex2_pipe1_wb_preg_vld,
iu_idu_ex2_pipe1_wb_preg_vld_dup0,
iu_idu_ex2_pipe1_wb_preg_vld_dup1,
iu_idu_ex2_pipe1_wb_preg_vld_dup2,
iu_idu_ex2_pipe1_wb_preg_vld_dup3,
iu_idu_ex2_pipe1_wb_preg_vld_dup4,
iu_rtu_ex2_pipe0_wb_preg_expand,
iu_rtu_ex2_pipe0_wb_preg_vld,
iu_rtu_ex2_pipe1_wb_preg_expand,
iu_rtu_ex2_pipe1_wb_preg_vld,
mult_rbus_ex3_data_vld,
mult_rbus_ex3_preg,
mult_rbus_ex4_data,
mult_rbus_ex4_data_vld,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
special_rbus_ex1_data,
special_rbus_ex1_data_vld,
special_rbus_ex1_preg,
vfpu_iu_ex2_pipe6_mfvr_data,
vfpu_iu_ex2_pipe6_mfvr_data_vld,
vfpu_iu_ex2_pipe6_mfvr_preg,
vfpu_iu_ex2_pipe7_mfvr_data,
vfpu_iu_ex2_pipe7_mfvr_data_vld,
vfpu_iu_ex2_pipe7_mfvr_preg
);
// &Ports; @26
input [63:0] alu_rbus_ex1_pipe0_data;
input alu_rbus_ex1_pipe0_data_vld;
input [63:0] alu_rbus_ex1_pipe0_fwd_data;
input alu_rbus_ex1_pipe0_fwd_vld;
input [6 :0] alu_rbus_ex1_pipe0_preg;
input [63:0] alu_rbus_ex1_pipe1_data;
input alu_rbus_ex1_pipe1_data_vld;
input [63:0] alu_rbus_ex1_pipe1_fwd_data;
input alu_rbus_ex1_pipe1_fwd_vld;
input [6 :0] alu_rbus_ex1_pipe1_preg;
input [63:0] cp0_iu_ex3_rslt_data;
input [6 :0] cp0_iu_ex3_rslt_preg;
input cp0_iu_ex3_rslt_vld;
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [63:0] div_rbus_data;
input div_rbus_pipe0_data_vld;
input [6 :0] div_rbus_preg;
input forever_cpuclk;
input [63:0] had_idu_wbbr_data;
input had_idu_wbbr_vld;
input mult_rbus_ex3_data_vld;
input [6 :0] mult_rbus_ex3_preg;
input [63:0] mult_rbus_ex4_data;
input mult_rbus_ex4_data_vld;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input [63:0] special_rbus_ex1_data;
input special_rbus_ex1_data_vld;
input [6 :0] special_rbus_ex1_preg;
input [63:0] vfpu_iu_ex2_pipe6_mfvr_data;
input vfpu_iu_ex2_pipe6_mfvr_data_vld;
input [6 :0] vfpu_iu_ex2_pipe6_mfvr_preg;
input [63:0] vfpu_iu_ex2_pipe7_mfvr_data;
input vfpu_iu_ex2_pipe7_mfvr_data_vld;
input [6 :0] vfpu_iu_ex2_pipe7_mfvr_preg;
output [6 :0] iu_idu_ex1_pipe0_fwd_preg;
output [63:0] iu_idu_ex1_pipe0_fwd_preg_data;
output iu_idu_ex1_pipe0_fwd_preg_vld;
output [6 :0] iu_idu_ex1_pipe1_fwd_preg;
output [63:0] iu_idu_ex1_pipe1_fwd_preg_data;
output iu_idu_ex1_pipe1_fwd_preg_vld;
output [6 :0] iu_idu_ex2_pipe0_wb_preg;
output [63:0] iu_idu_ex2_pipe0_wb_preg_data;
output [6 :0] iu_idu_ex2_pipe0_wb_preg_dup0;
output [6 :0] iu_idu_ex2_pipe0_wb_preg_dup1;
output [6 :0] iu_idu_ex2_pipe0_wb_preg_dup2;
output [6 :0] iu_idu_ex2_pipe0_wb_preg_dup3;
output [6 :0] iu_idu_ex2_pipe0_wb_preg_dup4;
output [95:0] iu_idu_ex2_pipe0_wb_preg_expand;
output iu_idu_ex2_pipe0_wb_preg_vld;
output iu_idu_ex2_pipe0_wb_preg_vld_dup0;
output iu_idu_ex2_pipe0_wb_preg_vld_dup1;
output iu_idu_ex2_pipe0_wb_preg_vld_dup2;
output iu_idu_ex2_pipe0_wb_preg_vld_dup3;
output iu_idu_ex2_pipe0_wb_preg_vld_dup4;
output [6 :0] iu_idu_ex2_pipe1_wb_preg;
output [63:0] iu_idu_ex2_pipe1_wb_preg_data;
output [6 :0] iu_idu_ex2_pipe1_wb_preg_dup0;
output [6 :0] iu_idu_ex2_pipe1_wb_preg_dup1;
output [6 :0] iu_idu_ex2_pipe1_wb_preg_dup2;
output [6 :0] iu_idu_ex2_pipe1_wb_preg_dup3;
output [6 :0] iu_idu_ex2_pipe1_wb_preg_dup4;
output [95:0] iu_idu_ex2_pipe1_wb_preg_expand;
output iu_idu_ex2_pipe1_wb_preg_vld;
output iu_idu_ex2_pipe1_wb_preg_vld_dup0;
output iu_idu_ex2_pipe1_wb_preg_vld_dup1;
output iu_idu_ex2_pipe1_wb_preg_vld_dup2;
output iu_idu_ex2_pipe1_wb_preg_vld_dup3;
output iu_idu_ex2_pipe1_wb_preg_vld_dup4;
output [95:0] iu_rtu_ex2_pipe0_wb_preg_expand;
output iu_rtu_ex2_pipe0_wb_preg_vld;
output [95:0] iu_rtu_ex2_pipe1_wb_preg_expand;
output iu_rtu_ex2_pipe1_wb_preg_vld;
// &Regs; @27
reg [63:0] rbus_pipe0_rslt_data;
reg [6 :0] rbus_pipe0_rslt_preg;
reg [63:0] rbus_pipe0_wb_data;
reg [6 :0] rbus_pipe0_wb_preg_dup0;
reg [6 :0] rbus_pipe0_wb_preg_dup1;
reg [6 :0] rbus_pipe0_wb_preg_dup2;
reg [6 :0] rbus_pipe0_wb_preg_dup3;
reg [6 :0] rbus_pipe0_wb_preg_dup4;
reg [6 :0] rbus_pipe0_wb_preg_dup5;
reg [95:0] rbus_pipe0_wb_preg_expand;
reg [6 :0] rbus_pipe0_wb_vld;
reg [63:0] rbus_pipe1_rslt_data;
reg [6 :0] rbus_pipe1_rslt_preg;
reg [63:0] rbus_pipe1_wb_data;
reg [6 :0] rbus_pipe1_wb_preg_dup0;
reg [6 :0] rbus_pipe1_wb_preg_dup1;
reg [6 :0] rbus_pipe1_wb_preg_dup2;
reg [6 :0] rbus_pipe1_wb_preg_dup3;
reg [6 :0] rbus_pipe1_wb_preg_dup4;
reg [6 :0] rbus_pipe1_wb_preg_dup5;
reg [95:0] rbus_pipe1_wb_preg_expand;
reg [6 :0] rbus_pipe1_wb_vld;
// &Wires; @28
wire [63:0] alu_rbus_ex1_pipe0_data;
wire [63:0] alu_rbus_ex1_pipe0_data_aft_wbbr;
wire alu_rbus_ex1_pipe0_data_vld;
wire [63:0] alu_rbus_ex1_pipe0_fwd_data;
wire alu_rbus_ex1_pipe0_fwd_vld;
wire [6 :0] alu_rbus_ex1_pipe0_preg;
wire [63:0] alu_rbus_ex1_pipe1_data;
wire [63:0] alu_rbus_ex1_pipe1_data_aft_wbbr;
wire alu_rbus_ex1_pipe1_data_vld;
wire [63:0] alu_rbus_ex1_pipe1_fwd_data;
wire alu_rbus_ex1_pipe1_fwd_vld;
wire [6 :0] alu_rbus_ex1_pipe1_preg;
wire [63:0] cp0_iu_ex3_rslt_data;
wire [6 :0] cp0_iu_ex3_rslt_preg;
wire cp0_iu_ex3_rslt_vld;
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [63:0] div_rbus_data;
wire div_rbus_pipe0_data_vld;
wire [6 :0] div_rbus_preg;
wire forever_cpuclk;
wire [63:0] had_idu_wbbr_data;
wire had_idu_wbbr_vld;
wire [6 :0] iu_idu_ex1_pipe0_fwd_preg;
wire [63:0] iu_idu_ex1_pipe0_fwd_preg_data;
wire iu_idu_ex1_pipe0_fwd_preg_vld;
wire [6 :0] iu_idu_ex1_pipe1_fwd_preg;
wire [63:0] iu_idu_ex1_pipe1_fwd_preg_data;
wire iu_idu_ex1_pipe1_fwd_preg_vld;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg;
wire [63:0] iu_idu_ex2_pipe0_wb_preg_data;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dup0;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dup1;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dup2;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dup3;
wire [6 :0] iu_idu_ex2_pipe0_wb_preg_dup4;
wire [95:0] iu_idu_ex2_pipe0_wb_preg_expand;
wire iu_idu_ex2_pipe0_wb_preg_vld;
wire iu_idu_ex2_pipe0_wb_preg_vld_dup0;
wire iu_idu_ex2_pipe0_wb_preg_vld_dup1;
wire iu_idu_ex2_pipe0_wb_preg_vld_dup2;
wire iu_idu_ex2_pipe0_wb_preg_vld_dup3;
wire iu_idu_ex2_pipe0_wb_preg_vld_dup4;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg;
wire [63:0] iu_idu_ex2_pipe1_wb_preg_data;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dup0;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dup1;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dup2;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dup3;
wire [6 :0] iu_idu_ex2_pipe1_wb_preg_dup4;
wire [95:0] iu_idu_ex2_pipe1_wb_preg_expand;
wire iu_idu_ex2_pipe1_wb_preg_vld;
wire iu_idu_ex2_pipe1_wb_preg_vld_dup0;
wire iu_idu_ex2_pipe1_wb_preg_vld_dup1;
wire iu_idu_ex2_pipe1_wb_preg_vld_dup2;
wire iu_idu_ex2_pipe1_wb_preg_vld_dup3;
wire iu_idu_ex2_pipe1_wb_preg_vld_dup4;
wire [95:0] iu_rtu_ex2_pipe0_wb_preg_expand;
wire iu_rtu_ex2_pipe0_wb_preg_vld;
wire [95:0] iu_rtu_ex2_pipe1_wb_preg_expand;
wire iu_rtu_ex2_pipe1_wb_preg_vld;
wire mult_rbus_ex3_data_vld;
wire [6 :0] mult_rbus_ex3_preg;
wire [63:0] mult_rbus_ex4_data;
wire mult_rbus_ex4_data_vld;
wire pad_yy_icg_scan_en;
wire pipe0_data_clk;
wire pipe0_data_clk_en;
wire pipe1_data_clk;
wire pipe1_data_clk_en;
wire [95:0] rbus_pipe0_rslt_preg_expand;
wire rbus_pipe0_rslt_vld;
wire [95:0] rbus_pipe1_rslt_preg_expand;
wire rbus_pipe1_rslt_vld;
wire rslt_vld_clk;
wire rslt_vld_clk_en;
wire rtu_yy_xx_flush;
wire [63:0] special_rbus_ex1_data;
wire special_rbus_ex1_data_vld;
wire [6 :0] special_rbus_ex1_preg;
wire [63:0] vfpu_iu_ex2_pipe6_mfvr_data;
wire vfpu_iu_ex2_pipe6_mfvr_data_vld;
wire [6 :0] vfpu_iu_ex2_pipe6_mfvr_preg;
wire [63:0] vfpu_iu_ex2_pipe7_mfvr_data;
wire vfpu_iu_ex2_pipe7_mfvr_data_vld;
wire [6 :0] vfpu_iu_ex2_pipe7_mfvr_preg;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign rslt_vld_clk_en = rbus_pipe0_rslt_vld
|| rbus_pipe1_rslt_vld
|| rbus_pipe0_wb_vld[0]
|| rbus_pipe1_wb_vld[0];
// &Instance("gated_clk_cell", "x_rslt_vld_gated_clk"); @38
gated_clk_cell x_rslt_vld_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (rslt_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (rslt_vld_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @39
// .external_en (1'b0), @40
// .global_en (cp0_yy_clk_en), @41
// .module_en (cp0_iu_icg_en), @42
// .local_en (rslt_vld_clk_en), @43
// .clk_out (rslt_vld_clk)); @44
//==========================================================
// Pipe0 GPR result Data Path
//==========================================================
//----------------------------------------------------------
// Result Valid Control Signal
//----------------------------------------------------------
assign rbus_pipe0_rslt_vld = alu_rbus_ex1_pipe0_data_vld
|| div_rbus_pipe0_data_vld
|| special_rbus_ex1_data_vld
|| cp0_iu_ex3_rslt_vld
|| vfpu_iu_ex2_pipe6_mfvr_data_vld;
//----------------------------------------------------------
// Write Back Valid
//----------------------------------------------------------
always @(posedge rslt_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rbus_pipe0_wb_vld[6:0] <= 7'b0;
else if(rtu_yy_xx_flush)
rbus_pipe0_wb_vld[6:0] <= 7'b0;
else
rbus_pipe0_wb_vld[6:0] <= {7{rbus_pipe0_rslt_vld}};
end
//output to IDU
assign iu_idu_ex2_pipe0_wb_preg_vld_dup0 = rbus_pipe0_wb_vld[0];
assign iu_idu_ex2_pipe0_wb_preg_vld_dup1 = rbus_pipe0_wb_vld[1];
assign iu_idu_ex2_pipe0_wb_preg_vld_dup2 = rbus_pipe0_wb_vld[2];
assign iu_idu_ex2_pipe0_wb_preg_vld_dup3 = rbus_pipe0_wb_vld[3];
assign iu_idu_ex2_pipe0_wb_preg_vld_dup4 = rbus_pipe0_wb_vld[4];
assign iu_idu_ex2_pipe0_wb_preg_vld = rbus_pipe0_wb_vld[5];
//output to RTU
assign iu_rtu_ex2_pipe0_wb_preg_vld = rbus_pipe0_wb_vld[6];
//----------------------------------------------------------
// Write Back Data Selection
//----------------------------------------------------------
// &CombBeg; @87
always @( special_rbus_ex1_preg[6:0]
or vfpu_iu_ex2_pipe6_mfvr_data_vld
or div_rbus_pipe0_data_vld
or vfpu_iu_ex2_pipe6_mfvr_preg[6:0]
or cp0_iu_ex3_rslt_preg[6:0]
or cp0_iu_ex3_rslt_vld
or special_rbus_ex1_data_vld
or div_rbus_preg[6:0]
or alu_rbus_ex1_pipe0_preg[6:0]
or alu_rbus_ex1_pipe0_data_vld)
begin
case ({special_rbus_ex1_data_vld,
vfpu_iu_ex2_pipe6_mfvr_data_vld,
cp0_iu_ex3_rslt_vld,
div_rbus_pipe0_data_vld,
alu_rbus_ex1_pipe0_data_vld})
5'h01 : rbus_pipe0_rslt_preg[6:0] = alu_rbus_ex1_pipe0_preg[6:0];
5'h02 : rbus_pipe0_rslt_preg[6:0] = div_rbus_preg[6:0];
5'h04 : rbus_pipe0_rslt_preg[6:0] = cp0_iu_ex3_rslt_preg[6:0];
5'h08 : rbus_pipe0_rslt_preg[6:0] = vfpu_iu_ex2_pipe6_mfvr_preg[6:0];
5'h10 : rbus_pipe0_rslt_preg[6:0] = special_rbus_ex1_preg[6:0];
default: rbus_pipe0_rslt_preg[6:0] = {7{1'bx}};
endcase
// &CombEnd; @100
end
assign alu_rbus_ex1_pipe0_data_aft_wbbr[63:0] = (had_idu_wbbr_vld)
? had_idu_wbbr_data[63:0]
: alu_rbus_ex1_pipe0_data[63:0];
// &CombBeg; @106
always @( special_rbus_ex1_data[63:0]
or div_rbus_data[63:0]
or vfpu_iu_ex2_pipe6_mfvr_data_vld
or div_rbus_pipe0_data_vld
or cp0_iu_ex3_rslt_vld
or special_rbus_ex1_data_vld
or cp0_iu_ex3_rslt_data[63:0]
or alu_rbus_ex1_pipe0_data_aft_wbbr[63:0]
or vfpu_iu_ex2_pipe6_mfvr_data[63:0]
or alu_rbus_ex1_pipe0_data_vld)
begin
case ({special_rbus_ex1_data_vld,
vfpu_iu_ex2_pipe6_mfvr_data_vld,
cp0_iu_ex3_rslt_vld,
div_rbus_pipe0_data_vld,
alu_rbus_ex1_pipe0_data_vld})
5'h01 : rbus_pipe0_rslt_data[63:0] = alu_rbus_ex1_pipe0_data_aft_wbbr[63:0];
5'h02 : rbus_pipe0_rslt_data[63:0] = div_rbus_data[63:0];
5'h04 : rbus_pipe0_rslt_data[63:0] = cp0_iu_ex3_rslt_data[63:0];
5'h08 : rbus_pipe0_rslt_data[63:0] = vfpu_iu_ex2_pipe6_mfvr_data[63:0];
5'h10 : rbus_pipe0_rslt_data[63:0] = special_rbus_ex1_data[63:0];
default: rbus_pipe0_rslt_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @119
end
// &ConnRule(s/^x_num/rbus_pipe0_rslt_preg/); @121
// &Instance("ct_rtu_expand_96","x_ct_rtu_expand_96_rbus_pipe0_rslt_preg"); @122
ct_rtu_expand_96 x_ct_rtu_expand_96_rbus_pipe0_rslt_preg (
.x_num (rbus_pipe0_rslt_preg ),
.x_num_expand (rbus_pipe0_rslt_preg_expand)
);
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign pipe0_data_clk_en = rbus_pipe0_rslt_vld;
// &Instance("gated_clk_cell", "x_pipe0_data_gated_clk"); @128
gated_clk_cell x_pipe0_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pipe0_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pipe0_data_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @129
// .external_en (1'b0), @130
// .global_en (cp0_yy_clk_en), @131
// .module_en (cp0_iu_icg_en), @132
// .local_en (pipe0_data_clk_en), @133
// .clk_out (pipe0_data_clk)); @134
//----------------------------------------------------------
// Write Back Data
//----------------------------------------------------------
always @(posedge pipe0_data_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
rbus_pipe0_wb_preg_dup0[6:0] <= 7'b0;
rbus_pipe0_wb_preg_dup1[6:0] <= 7'b0;
rbus_pipe0_wb_preg_dup2[6:0] <= 7'b0;
rbus_pipe0_wb_preg_dup3[6:0] <= 7'b0;
rbus_pipe0_wb_preg_dup4[6:0] <= 7'b0;
rbus_pipe0_wb_preg_dup5[6:0] <= 7'b0;
rbus_pipe0_wb_preg_expand[95:0] <= 96'b0;
rbus_pipe0_wb_data[63:0] <= 64'b0;
end
else if(rbus_pipe0_rslt_vld) begin
rbus_pipe0_wb_preg_dup0[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_dup1[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_dup2[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_dup3[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_dup4[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_dup5[6:0] <= rbus_pipe0_rslt_preg[6:0];
rbus_pipe0_wb_preg_expand[95:0] <= rbus_pipe0_rslt_preg_expand[95:0];
rbus_pipe0_wb_data[63:0] <= rbus_pipe0_rslt_data[63:0];
end
else begin
rbus_pipe0_wb_preg_dup0[6:0] <= rbus_pipe0_wb_preg_dup0[6:0];
rbus_pipe0_wb_preg_dup1[6:0] <= rbus_pipe0_wb_preg_dup1[6:0];
rbus_pipe0_wb_preg_dup2[6:0] <= rbus_pipe0_wb_preg_dup2[6:0];
rbus_pipe0_wb_preg_dup3[6:0] <= rbus_pipe0_wb_preg_dup3[6:0];
rbus_pipe0_wb_preg_dup4[6:0] <= rbus_pipe0_wb_preg_dup4[6:0];
rbus_pipe0_wb_preg_dup5[6:0] <= rbus_pipe0_wb_preg_dup5[6:0];
rbus_pipe0_wb_preg_expand[95:0] <= rbus_pipe0_wb_preg_expand[95:0];
rbus_pipe0_wb_data[63:0] <= rbus_pipe0_wb_data[63:0];
end
end
//output to idu
assign iu_idu_ex2_pipe0_wb_preg_dup0[6:0] = rbus_pipe0_wb_preg_dup0[6:0];
assign iu_idu_ex2_pipe0_wb_preg_dup1[6:0] = rbus_pipe0_wb_preg_dup1[6:0];
assign iu_idu_ex2_pipe0_wb_preg_dup2[6:0] = rbus_pipe0_wb_preg_dup2[6:0];
assign iu_idu_ex2_pipe0_wb_preg_dup3[6:0] = rbus_pipe0_wb_preg_dup3[6:0];
assign iu_idu_ex2_pipe0_wb_preg_dup4[6:0] = rbus_pipe0_wb_preg_dup4[6:0];
assign iu_idu_ex2_pipe0_wb_preg[6:0] = rbus_pipe0_wb_preg_dup5[6:0];
assign iu_idu_ex2_pipe0_wb_preg_expand[95:0] = rbus_pipe0_wb_preg_expand[95:0];
assign iu_idu_ex2_pipe0_wb_preg_data[63:0] = rbus_pipe0_wb_data[63:0];
//output to rtu
assign iu_rtu_ex2_pipe0_wb_preg_expand[95:0] = rbus_pipe0_wb_preg_expand[95:0];
//----------------------------------------------------------
// Forward Signals
//----------------------------------------------------------
//ex1 forward path: only alu0
assign iu_idu_ex1_pipe0_fwd_preg_vld = alu_rbus_ex1_pipe0_fwd_vld;
assign iu_idu_ex1_pipe0_fwd_preg[6:0] = alu_rbus_ex1_pipe0_preg[6:0];
assign iu_idu_ex1_pipe0_fwd_preg_data[63:0] = alu_rbus_ex1_pipe0_fwd_data[63:0];
//==========================================================
// Pipe1 GPR result Data Path
//==========================================================
//----------------------------------------------------------
// Result Valid Control Signal
//----------------------------------------------------------
assign rbus_pipe1_rslt_vld = alu_rbus_ex1_pipe1_data_vld
|| mult_rbus_ex3_data_vld
|| vfpu_iu_ex2_pipe7_mfvr_data_vld;
//----------------------------------------------------------
// Write Back Valid
//----------------------------------------------------------
always @(posedge rslt_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
rbus_pipe1_wb_vld[6:0] <= 7'b0;
else if(rtu_yy_xx_flush)
rbus_pipe1_wb_vld[6:0] <= 7'b0;
else
rbus_pipe1_wb_vld[6:0] <= {7{rbus_pipe1_rslt_vld}};
end
//output to IDU
assign iu_idu_ex2_pipe1_wb_preg_vld_dup0 = rbus_pipe1_wb_vld[0];
assign iu_idu_ex2_pipe1_wb_preg_vld_dup1 = rbus_pipe1_wb_vld[1];
assign iu_idu_ex2_pipe1_wb_preg_vld_dup2 = rbus_pipe1_wb_vld[2];
assign iu_idu_ex2_pipe1_wb_preg_vld_dup3 = rbus_pipe1_wb_vld[3];
assign iu_idu_ex2_pipe1_wb_preg_vld_dup4 = rbus_pipe1_wb_vld[4];
assign iu_idu_ex2_pipe1_wb_preg_vld = rbus_pipe1_wb_vld[5];
//output to RTU
assign iu_rtu_ex2_pipe1_wb_preg_vld = rbus_pipe1_wb_vld[6];
//----------------------------------------------------------
// Write Back Data Selection
//----------------------------------------------------------
// &CombBeg; @237
always @( vfpu_iu_ex2_pipe7_mfvr_preg[6:0]
or mult_rbus_ex3_preg[6:0]
or alu_rbus_ex1_pipe1_data_vld
or vfpu_iu_ex2_pipe7_mfvr_data_vld
or mult_rbus_ex3_data_vld
or alu_rbus_ex1_pipe1_preg[6:0])
begin
case ({vfpu_iu_ex2_pipe7_mfvr_data_vld,
mult_rbus_ex3_data_vld,
alu_rbus_ex1_pipe1_data_vld})
3'h1 : rbus_pipe1_rslt_preg[6:0] = alu_rbus_ex1_pipe1_preg[6:0];
3'h2 : rbus_pipe1_rslt_preg[6:0] = mult_rbus_ex3_preg[6:0];
3'h4 : rbus_pipe1_rslt_preg[6:0] = vfpu_iu_ex2_pipe7_mfvr_preg[6:0];
default: rbus_pipe1_rslt_preg[6:0] = {7{1'bx}};
endcase
// &CombEnd; @246
end
assign alu_rbus_ex1_pipe1_data_aft_wbbr[63:0] = (had_idu_wbbr_vld)
? had_idu_wbbr_data[63:0]
: alu_rbus_ex1_pipe1_data[63:0];
//mult data is available at EX4
// &CombBeg; @253
always @( alu_rbus_ex1_pipe1_data_vld
or vfpu_iu_ex2_pipe7_mfvr_data_vld
or alu_rbus_ex1_pipe1_data_aft_wbbr[63:0]
or vfpu_iu_ex2_pipe7_mfvr_data[63:0])
begin
case ({vfpu_iu_ex2_pipe7_mfvr_data_vld,
alu_rbus_ex1_pipe1_data_vld})
2'h1 : rbus_pipe1_rslt_data[63:0] = alu_rbus_ex1_pipe1_data_aft_wbbr[63:0];
2'h2 : rbus_pipe1_rslt_data[63:0] = vfpu_iu_ex2_pipe7_mfvr_data[63:0];
default: rbus_pipe1_rslt_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @260
end
// &ConnRule(s/^x_num/rbus_pipe1_rslt_preg/); @262
// &Instance("ct_rtu_expand_96","x_ct_rtu_expand_96_rbus_pipe1_rslt_preg"); @263
ct_rtu_expand_96 x_ct_rtu_expand_96_rbus_pipe1_rslt_preg (
.x_num (rbus_pipe1_rslt_preg ),
.x_num_expand (rbus_pipe1_rslt_preg_expand)
);
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign pipe1_data_clk_en = rbus_pipe1_rslt_vld;
// &Instance("gated_clk_cell", "x_pipe1_data_gated_clk"); @269
gated_clk_cell x_pipe1_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pipe1_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pipe1_data_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @270
// .external_en (1'b0), @271
// .global_en (cp0_yy_clk_en), @272
// .module_en (cp0_iu_icg_en), @273
// .local_en (pipe1_data_clk_en), @274
// .clk_out (pipe1_data_clk)); @275
//----------------------------------------------------------
// Write Back Data
//----------------------------------------------------------
always @(posedge pipe1_data_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
rbus_pipe1_wb_preg_dup0[6:0] <= 7'b0;
rbus_pipe1_wb_preg_dup1[6:0] <= 7'b0;
rbus_pipe1_wb_preg_dup2[6:0] <= 7'b0;
rbus_pipe1_wb_preg_dup3[6:0] <= 7'b0;
rbus_pipe1_wb_preg_dup4[6:0] <= 7'b0;
rbus_pipe1_wb_preg_dup5[6:0] <= 7'b0;
rbus_pipe1_wb_preg_expand[95:0] <= 96'b0;
rbus_pipe1_wb_data[63:0] <= 64'b0;
end
else if(rbus_pipe1_rslt_vld) begin
rbus_pipe1_wb_preg_dup0[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_dup1[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_dup2[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_dup3[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_dup4[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_dup5[6:0] <= rbus_pipe1_rslt_preg[6:0];
rbus_pipe1_wb_preg_expand[95:0] <= rbus_pipe1_rslt_preg_expand[95:0];
rbus_pipe1_wb_data[63:0] <= rbus_pipe1_rslt_data[63:0];
end
else begin
rbus_pipe1_wb_preg_dup0[6:0] <= rbus_pipe1_wb_preg_dup0[6:0];
rbus_pipe1_wb_preg_dup1[6:0] <= rbus_pipe1_wb_preg_dup1[6:0];
rbus_pipe1_wb_preg_dup2[6:0] <= rbus_pipe1_wb_preg_dup2[6:0];
rbus_pipe1_wb_preg_dup3[6:0] <= rbus_pipe1_wb_preg_dup3[6:0];
rbus_pipe1_wb_preg_dup4[6:0] <= rbus_pipe1_wb_preg_dup4[6:0];
rbus_pipe1_wb_preg_dup5[6:0] <= rbus_pipe1_wb_preg_dup5[6:0];
rbus_pipe1_wb_preg_expand[95:0] <= rbus_pipe1_wb_preg_expand[95:0];
rbus_pipe1_wb_data[63:0] <= rbus_pipe1_wb_data[63:0];
end
end
//output to idu
assign iu_idu_ex2_pipe1_wb_preg_dup0[6:0] = rbus_pipe1_wb_preg_dup0[6:0];
assign iu_idu_ex2_pipe1_wb_preg_dup1[6:0] = rbus_pipe1_wb_preg_dup1[6:0];
assign iu_idu_ex2_pipe1_wb_preg_dup2[6:0] = rbus_pipe1_wb_preg_dup2[6:0];
assign iu_idu_ex2_pipe1_wb_preg_dup3[6:0] = rbus_pipe1_wb_preg_dup3[6:0];
assign iu_idu_ex2_pipe1_wb_preg_dup4[6:0] = rbus_pipe1_wb_preg_dup4[6:0];
assign iu_idu_ex2_pipe1_wb_preg[6:0] = rbus_pipe1_wb_preg_dup5[6:0];
assign iu_idu_ex2_pipe1_wb_preg_expand[95:0] = rbus_pipe1_wb_preg_expand[95:0];
assign iu_idu_ex2_pipe1_wb_preg_data[63:0] = (mult_rbus_ex4_data_vld)
? mult_rbus_ex4_data[63:0]
: rbus_pipe1_wb_data[63:0];
//output to rtu
assign iu_rtu_ex2_pipe1_wb_preg_expand[95:0] = rbus_pipe1_wb_preg_expand[95:0];
//----------------------------------------------------------
// Forward Signals
//----------------------------------------------------------
//ex1 forward path: only alu
assign iu_idu_ex1_pipe1_fwd_preg_vld = alu_rbus_ex1_pipe1_fwd_vld;
assign iu_idu_ex1_pipe1_fwd_preg[6:0] = alu_rbus_ex1_pipe1_preg[6:0];
assign iu_idu_ex1_pipe1_fwd_preg_data[63:0] = alu_rbus_ex1_pipe1_fwd_data[63:0];
// &ModuleEnd; @343
endmodule |
module ct_iu_mult(
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idu_iu_rf_mult_gateclk_sel,
idu_iu_rf_mult_sel,
idu_iu_rf_pipe1_dst_preg,
idu_iu_rf_pipe1_mla_src2_preg,
idu_iu_rf_pipe1_mla_src2_vld,
idu_iu_rf_pipe1_mult_func,
idu_iu_rf_pipe1_src0,
idu_iu_rf_pipe1_src1_no_imm,
idu_iu_rf_pipe1_src2,
iu_idu_ex1_pipe1_mult_stall,
iu_idu_ex2_pipe1_mult_inst_vld_dup0,
iu_idu_ex2_pipe1_mult_inst_vld_dup1,
iu_idu_ex2_pipe1_mult_inst_vld_dup2,
iu_idu_ex2_pipe1_mult_inst_vld_dup3,
iu_idu_ex2_pipe1_mult_inst_vld_dup4,
iu_idu_ex2_pipe1_preg_dup0,
iu_idu_ex2_pipe1_preg_dup1,
iu_idu_ex2_pipe1_preg_dup2,
iu_idu_ex2_pipe1_preg_dup3,
iu_idu_ex2_pipe1_preg_dup4,
iu_idu_pipe1_mla_src2_no_fwd,
mult_rbus_ex3_data_vld,
mult_rbus_ex3_preg,
mult_rbus_ex4_data,
mult_rbus_ex4_data_vld,
pad_yy_icg_scan_en,
rtu_yy_xx_flush
);
// &Ports; @26
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input idu_iu_rf_mult_gateclk_sel;
input idu_iu_rf_mult_sel;
input [6 :0] idu_iu_rf_pipe1_dst_preg;
input [6 :0] idu_iu_rf_pipe1_mla_src2_preg;
input idu_iu_rf_pipe1_mla_src2_vld;
input [7 :0] idu_iu_rf_pipe1_mult_func;
input [63 :0] idu_iu_rf_pipe1_src0;
input [63 :0] idu_iu_rf_pipe1_src1_no_imm;
input [63 :0] idu_iu_rf_pipe1_src2;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
output iu_idu_ex1_pipe1_mult_stall;
output iu_idu_ex2_pipe1_mult_inst_vld_dup0;
output iu_idu_ex2_pipe1_mult_inst_vld_dup1;
output iu_idu_ex2_pipe1_mult_inst_vld_dup2;
output iu_idu_ex2_pipe1_mult_inst_vld_dup3;
output iu_idu_ex2_pipe1_mult_inst_vld_dup4;
output [6 :0] iu_idu_ex2_pipe1_preg_dup0;
output [6 :0] iu_idu_ex2_pipe1_preg_dup1;
output [6 :0] iu_idu_ex2_pipe1_preg_dup2;
output [6 :0] iu_idu_ex2_pipe1_preg_dup3;
output [6 :0] iu_idu_ex2_pipe1_preg_dup4;
output iu_idu_pipe1_mla_src2_no_fwd;
output mult_rbus_ex3_data_vld;
output [6 :0] mult_rbus_ex3_preg;
output [63 :0] mult_rbus_ex4_data;
output mult_rbus_ex4_data_vld;
// &Regs; @27
reg [6 :0] mult_ex1_dst_preg;
reg mult_ex1_inst_vld;
reg mult_ex1_mla;
reg [64 :0] mult_ex1_pipedown_src2;
reg [1 :0] mult_ex1_rslt_sel;
reg [64 :0] mult_ex1_src0;
reg [64 :0] mult_ex1_src1;
reg [64 :0] mult_ex1_src2;
reg mult_ex1_src2_ex1_sel_ex3;
reg mult_ex1_src2_ex1_sel_ex4;
reg mult_ex1_src2_ex2_sel_ex3;
reg mult_ex1_src2_h;
reg mult_ex1_sub;
reg [6 :0] mult_ex2_dst_preg;
reg [6 :0] mult_ex2_dst_preg_dup0;
reg [6 :0] mult_ex2_dst_preg_dup1;
reg [6 :0] mult_ex2_dst_preg_dup2;
reg [6 :0] mult_ex2_dst_preg_dup3;
reg [6 :0] mult_ex2_dst_preg_dup4;
reg mult_ex2_inst_vld;
reg [4 :0] mult_ex2_inst_vld_dup;
reg mult_ex2_mla;
reg [1 :0] mult_ex2_rslt_sel;
reg [64 :0] mult_ex2_src2;
reg mult_ex2_src2_ex2_sel_ex3;
reg mult_ex2_src2_h;
reg [6 :0] mult_ex3_dst_preg;
reg mult_ex3_inst_vld;
reg mult_ex3_mla;
reg [1 :0] mult_ex3_rslt_sel;
reg [6 :0] mult_ex4_dst_preg;
reg mult_ex4_inst_vld;
reg [127:0] mult_ex4_result;
reg [1 :0] mult_ex4_rslt_sel;
reg [63 :0] mult_rbus_ex4_data;
// &Wires; @28
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire ex1_inst_clk;
wire ex1_inst_clk_en;
wire ex2_inst_clk;
wire ex2_inst_clk_en;
wire ex3_inst_clk;
wire ex3_inst_clk_en;
wire ex4_inst_clk;
wire ex4_inst_clk_en;
wire forever_cpuclk;
wire idu_iu_rf_mult_gateclk_sel;
wire idu_iu_rf_mult_sel;
wire [6 :0] idu_iu_rf_pipe1_dst_preg;
wire [6 :0] idu_iu_rf_pipe1_mla_src2_preg;
wire idu_iu_rf_pipe1_mla_src2_vld;
wire [7 :0] idu_iu_rf_pipe1_mult_func;
wire [63 :0] idu_iu_rf_pipe1_src0;
wire [63 :0] idu_iu_rf_pipe1_src1_no_imm;
wire [63 :0] idu_iu_rf_pipe1_src2;
wire iu_idu_ex1_pipe1_mult_stall;
wire iu_idu_ex2_pipe1_mult_inst_vld_dup0;
wire iu_idu_ex2_pipe1_mult_inst_vld_dup1;
wire iu_idu_ex2_pipe1_mult_inst_vld_dup2;
wire iu_idu_ex2_pipe1_mult_inst_vld_dup3;
wire iu_idu_ex2_pipe1_mult_inst_vld_dup4;
wire [6 :0] iu_idu_ex2_pipe1_preg_dup0;
wire [6 :0] iu_idu_ex2_pipe1_preg_dup1;
wire [6 :0] iu_idu_ex2_pipe1_preg_dup2;
wire [6 :0] iu_idu_ex2_pipe1_preg_dup3;
wire [6 :0] iu_idu_ex2_pipe1_preg_dup4;
wire iu_idu_pipe1_mla_src2_no_fwd;
wire mult_clk;
wire mult_clk_en;
wire mult_ex1_src2_ex1_sel_ex1;
wire [64 :0] mult_ex2_src2_data;
wire [64 :0] mult_ex2_src2_fwd_data;
wire [64 :0] mult_ex3_src2_fwd_data;
wire [64 :0] mult_ex4_src2_fwd_data;
wire [129:0] mult_multiplier_result;
wire mult_rbus_ex3_data_vld;
wire [6 :0] mult_rbus_ex3_preg;
wire mult_rbus_ex4_data_vld;
wire mult_rf_mla_match_ex1;
wire mult_rf_mla_match_ex2;
wire mult_rf_mla_match_ex3;
wire [64 :0] mult_rf_src0;
wire [64 :0] mult_rf_src1;
wire [64 :0] mult_rf_src2;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
// &Depend("compressor_32.v"); @30
// &Depend("compressor_42.v"); @31
// &Depend("booth_code.v"); @32
//==========================================================
// RF/EX1 Pipeline Register
//==========================================================
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign mult_clk_en = idu_iu_rf_mult_gateclk_sel
|| mult_ex1_inst_vld
|| mult_ex2_inst_vld
|| mult_ex3_inst_vld
|| mult_ex4_inst_vld;
// &Instance("gated_clk_cell", "x_mult_gated_clk"); @45
gated_clk_cell x_mult_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (mult_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (mult_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @46
// .external_en (1'b0), @47
// .global_en (cp0_yy_clk_en), @48
// .module_en (cp0_iu_icg_en), @49
// .local_en (mult_clk_en), @50
// .clk_out (mult_clk)); @51
assign ex1_inst_clk_en = idu_iu_rf_mult_gateclk_sel;
// &Instance("gated_clk_cell", "x_ex1_inst_gated_clk"); @54
gated_clk_cell x_ex1_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_inst_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @55
// .external_en (1'b0), @56
// .global_en (cp0_yy_clk_en), @57
// .module_en (cp0_iu_icg_en), @58
// .local_en (ex1_inst_clk_en), @59
// .clk_out (ex1_inst_clk)); @60
assign ex2_inst_clk_en = mult_ex1_inst_vld;
// &Instance("gated_clk_cell", "x_ex2_inst_gated_clk"); @63
gated_clk_cell x_ex2_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_inst_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @64
// .external_en (1'b0), @65
// .global_en (cp0_yy_clk_en), @66
// .module_en (cp0_iu_icg_en), @67
// .local_en (ex2_inst_clk_en), @68
// .clk_out (ex2_inst_clk)); @69
assign ex3_inst_clk_en = mult_ex2_inst_vld;
// &Instance("gated_clk_cell", "x_ex3_inst_gated_clk"); @72
gated_clk_cell x_ex3_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex3_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex3_inst_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @73
// .external_en (1'b0), @74
// .global_en (cp0_yy_clk_en), @75
// .module_en (cp0_iu_icg_en), @76
// .local_en (ex3_inst_clk_en), @77
// .clk_out (ex3_inst_clk)); @78
assign ex4_inst_clk_en = mult_ex3_inst_vld;
// &Instance("gated_clk_cell", "x_ex4_inst_gated_clk"); @81
gated_clk_cell x_ex4_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex4_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex4_inst_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @82
// .external_en (1'b0), @83
// .global_en (cp0_yy_clk_en), @84
// .module_en (cp0_iu_icg_en), @85
// .local_en (ex4_inst_clk_en), @86
// .clk_out (ex4_inst_clk)); @87
//----------------------------------------------------------
// Pipe1 RF Operand Prepare
//----------------------------------------------------------
//mul : rz = (rx * ry)[63:0]
//mulh : rz = (rx * ry)[127:64]
//mulhu : rz = (unsign_rx * unsign_ry)[127:64]
//mulhsu : rz = (rx * unsign_ry)[127:64]
//mulw : rz = sign_extend(rx[31:0] * ry[31:0])[31:0]
assign mult_rf_src0[64] = (idu_iu_rf_pipe1_mult_func[2])
? 1'b0 : idu_iu_rf_pipe1_src0[63];
assign mult_rf_src0[63:32] = (idu_iu_rf_pipe1_mult_func[1])
? 32'b0 : idu_iu_rf_pipe1_src0[63:32];
assign mult_rf_src0[31:0] = (idu_iu_rf_pipe1_mult_func[4])
? {{16{idu_iu_rf_pipe1_src0[15]}},
idu_iu_rf_pipe1_src0[15:0]}
: idu_iu_rf_pipe1_src0[31:0];
assign mult_rf_src1[64] = (idu_iu_rf_pipe1_mult_func[3])
? 1'b0 : idu_iu_rf_pipe1_src1_no_imm[63];
assign mult_rf_src1[63:32] = (idu_iu_rf_pipe1_mult_func[1])
? 32'b0 : idu_iu_rf_pipe1_src1_no_imm[63:32];
assign mult_rf_src1[31:0] = (idu_iu_rf_pipe1_mult_func[4])
? {{16{idu_iu_rf_pipe1_src1_no_imm[15]}},
idu_iu_rf_pipe1_src1_no_imm[15:0]}
: idu_iu_rf_pipe1_src1_no_imm[31:0];
assign mult_rf_src2[64:32] = (idu_iu_rf_pipe1_mult_func[6])
? {idu_iu_rf_pipe1_src2[63],
idu_iu_rf_pipe1_src2[63:32]}
: 33'b0;
assign mult_rf_src2[31:0] = (idu_iu_rf_pipe1_mult_func[5])
? idu_iu_rf_pipe1_src2[31:0] : 32'b0;
//----------------------------------------------------------
// Indicate Internal Forward
//----------------------------------------------------------
assign mult_rf_mla_match_ex1 = idu_iu_rf_pipe1_mla_src2_vld
&& mult_ex1_inst_vld && mult_ex1_mla
&& (idu_iu_rf_pipe1_mult_func[1]
== mult_ex1_rslt_sel[1])
&& (idu_iu_rf_pipe1_mla_src2_preg[6:0]
== mult_ex1_dst_preg[6:0]);
assign mult_rf_mla_match_ex2 = idu_iu_rf_pipe1_mla_src2_vld
&& mult_ex2_inst_vld && mult_ex2_mla
&& (idu_iu_rf_pipe1_mult_func[1]
== mult_ex2_rslt_sel[1])
&& (idu_iu_rf_pipe1_mla_src2_preg[6:0]
== mult_ex2_dst_preg[6:0]);
assign mult_rf_mla_match_ex3 = idu_iu_rf_pipe1_mla_src2_vld
&& mult_ex3_inst_vld && mult_ex3_mla
&& (idu_iu_rf_pipe1_mult_func[1]
== mult_ex3_rslt_sel[1])
&& (idu_iu_rf_pipe1_mla_src2_preg[6:0]
== mult_ex3_dst_preg[6:0]);
assign iu_idu_pipe1_mla_src2_no_fwd = !mult_rf_mla_match_ex1
&& !mult_rf_mla_match_ex2
&& !mult_rf_mla_match_ex3;
//----------------------------------------------------------
// Pipe1 EX1 Instruction valid
//----------------------------------------------------------
always @(posedge mult_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mult_ex1_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
mult_ex1_inst_vld <= 1'b0;
else
mult_ex1_inst_vld <= idu_iu_rf_mult_sel;
end
//stop issue alu inst
assign iu_idu_ex1_pipe1_mult_stall = mult_ex1_inst_vld;
//----------------------------------------------------------
// Pipe1 EX1 Instruction Data
//----------------------------------------------------------
always @(posedge ex1_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex1_dst_preg[6:0] <= 7'b0;
mult_ex1_rslt_sel[1:0] <= 2'b0;
mult_ex1_sub <= 1'b0;
mult_ex1_src2_h <= 1'b0;
mult_ex1_mla <= 1'b0;
mult_ex1_src0[64:0] <= 65'b0;
mult_ex1_src1[64:0] <= 65'b0;
mult_ex1_src2[64:0] <= 65'b0;
mult_ex1_src2_ex1_sel_ex4 <= 1'b0;
mult_ex1_src2_ex1_sel_ex3 <= 1'b0;
mult_ex1_src2_ex2_sel_ex3 <= 1'b0;
end
else if(idu_iu_rf_mult_gateclk_sel) begin
mult_ex1_dst_preg[6:0] <= idu_iu_rf_pipe1_dst_preg[6:0];
mult_ex1_rslt_sel[1:0] <= idu_iu_rf_pipe1_mult_func[1:0];
mult_ex1_sub <= idu_iu_rf_pipe1_mult_func[7];
mult_ex1_src2_h <= idu_iu_rf_pipe1_mult_func[6];
mult_ex1_mla <= idu_iu_rf_pipe1_mla_src2_vld;
mult_ex1_src0[64:0] <= mult_rf_src0[64:0];
mult_ex1_src1[64:0] <= mult_rf_src1[64:0];
mult_ex1_src2[64:0] <= mult_rf_src2[64:0];
mult_ex1_src2_ex1_sel_ex4 <= mult_rf_mla_match_ex3;
mult_ex1_src2_ex1_sel_ex3 <= mult_rf_mla_match_ex2;
mult_ex1_src2_ex2_sel_ex3 <= mult_rf_mla_match_ex1;
end
else begin
mult_ex1_dst_preg[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex1_rslt_sel[1:0] <= mult_ex1_rslt_sel[1:0];
mult_ex1_sub <= mult_ex1_sub;
mult_ex1_src2_h <= mult_ex1_src2_h;
mult_ex1_mla <= mult_ex1_mla;
mult_ex1_src0[64:0] <= mult_ex1_src0[64:0];
mult_ex1_src1[64:0] <= mult_ex1_src1[64:0];
mult_ex1_src2[64:0] <= mult_ex1_src2[64:0];
mult_ex1_src2_ex1_sel_ex4 <= mult_ex1_src2_ex1_sel_ex4;
mult_ex1_src2_ex1_sel_ex3 <= mult_ex1_src2_ex1_sel_ex3;
mult_ex1_src2_ex2_sel_ex3 <= mult_ex1_src2_ex2_sel_ex3;
end
end
//----------------------------------------------------------
// Pipe1 EX1 Internal Forward
//----------------------------------------------------------
assign mult_ex1_src2_ex1_sel_ex1 = !(mult_ex1_src2_ex1_sel_ex3
|| mult_ex1_src2_ex1_sel_ex4);
// &CombBeg; @215
always @( mult_ex1_src2[64:0]
or mult_ex1_src2_ex1_sel_ex4
or mult_ex1_src2_ex1_sel_ex3
or mult_ex4_src2_fwd_data[64:0]
or mult_ex1_src2_ex1_sel_ex1
or mult_ex3_src2_fwd_data[64:0])
begin
case({mult_ex1_src2_ex1_sel_ex4,
mult_ex1_src2_ex1_sel_ex3,
mult_ex1_src2_ex1_sel_ex1})
3'b001: mult_ex1_pipedown_src2[64:0] = mult_ex1_src2[64:0];
3'b010: mult_ex1_pipedown_src2[64:0] = mult_ex3_src2_fwd_data[64:0];
3'b100: mult_ex1_pipedown_src2[64:0] = mult_ex4_src2_fwd_data[64:0];
default: mult_ex1_pipedown_src2[64:0] = {65{1'bx}};
endcase
// &CombEnd; @224
end
//----------------------------------------------------------
// Pipe1 EX2 Instruction valid
//----------------------------------------------------------
always @(posedge mult_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex2_inst_vld <= 1'b0;
mult_ex2_inst_vld_dup[4:0] <= 5'b0;
end
else if(rtu_yy_xx_flush) begin
mult_ex2_inst_vld <= 1'b0;
mult_ex2_inst_vld_dup[4:0] <= 5'b0;
end
else begin
mult_ex2_inst_vld <= mult_ex1_inst_vld;
mult_ex2_inst_vld_dup[4:0] <= {5{mult_ex1_inst_vld}};
end
end
//indicate result ready
assign iu_idu_ex2_pipe1_mult_inst_vld_dup0 = mult_ex2_inst_vld_dup[0];
assign iu_idu_ex2_pipe1_mult_inst_vld_dup1 = mult_ex2_inst_vld_dup[1];
assign iu_idu_ex2_pipe1_mult_inst_vld_dup2 = mult_ex2_inst_vld_dup[2];
assign iu_idu_ex2_pipe1_mult_inst_vld_dup3 = mult_ex2_inst_vld_dup[3];
assign iu_idu_ex2_pipe1_mult_inst_vld_dup4 = mult_ex2_inst_vld_dup[4];
//----------------------------------------------------------
// Pipe1 EX2 Instruction Data
//----------------------------------------------------------
always @(posedge ex2_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex2_dst_preg[6:0] <= 7'b0;
mult_ex2_dst_preg_dup0[6:0] <= 7'b0;
mult_ex2_dst_preg_dup1[6:0] <= 7'b0;
mult_ex2_dst_preg_dup2[6:0] <= 7'b0;
mult_ex2_dst_preg_dup3[6:0] <= 7'b0;
mult_ex2_dst_preg_dup4[6:0] <= 7'b0;
mult_ex2_rslt_sel[1:0] <= 2'b0;
mult_ex2_src2[64:0] <= 65'b0;
mult_ex2_src2_h <= 1'b0;
mult_ex2_mla <= 1'b0;
mult_ex2_src2_ex2_sel_ex3 <= 1'b0;
end
else if(mult_ex1_inst_vld) begin
mult_ex2_dst_preg[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_dst_preg_dup0[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_dst_preg_dup1[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_dst_preg_dup2[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_dst_preg_dup3[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_dst_preg_dup4[6:0] <= mult_ex1_dst_preg[6:0];
mult_ex2_rslt_sel[1:0] <= mult_ex1_rslt_sel[1:0];
mult_ex2_src2[64:0] <= mult_ex1_pipedown_src2[64:0];
mult_ex2_src2_h <= mult_ex1_src2_h;
mult_ex2_mla <= mult_ex1_mla;
mult_ex2_src2_ex2_sel_ex3 <= mult_ex1_src2_ex2_sel_ex3;
end
else begin
mult_ex2_dst_preg[6:0] <= mult_ex2_dst_preg[6:0];
mult_ex2_dst_preg_dup0[6:0] <= mult_ex2_dst_preg_dup0[6:0];
mult_ex2_dst_preg_dup1[6:0] <= mult_ex2_dst_preg_dup1[6:0];
mult_ex2_dst_preg_dup2[6:0] <= mult_ex2_dst_preg_dup2[6:0];
mult_ex2_dst_preg_dup3[6:0] <= mult_ex2_dst_preg_dup3[6:0];
mult_ex2_dst_preg_dup4[6:0] <= mult_ex2_dst_preg_dup4[6:0];
mult_ex2_rslt_sel[1:0] <= mult_ex2_rslt_sel[1:0];
mult_ex2_src2[64:0] <= mult_ex2_src2[64:0];
mult_ex2_src2_h <= mult_ex2_src2_h;
mult_ex2_mla <= mult_ex2_mla;
mult_ex2_src2_ex2_sel_ex3 <= mult_ex2_src2_ex2_sel_ex3;
end
end
assign iu_idu_ex2_pipe1_preg_dup0[6:0] = mult_ex2_dst_preg_dup0[6:0];
assign iu_idu_ex2_pipe1_preg_dup1[6:0] = mult_ex2_dst_preg_dup1[6:0];
assign iu_idu_ex2_pipe1_preg_dup2[6:0] = mult_ex2_dst_preg_dup2[6:0];
assign iu_idu_ex2_pipe1_preg_dup3[6:0] = mult_ex2_dst_preg_dup3[6:0];
assign iu_idu_ex2_pipe1_preg_dup4[6:0] = mult_ex2_dst_preg_dup4[6:0];
//----------------------------------------------------------
// Pipe1 EX2 Internal Forward
//----------------------------------------------------------
assign mult_ex2_src2_fwd_data[64:0] = mult_ex2_src2_ex2_sel_ex3
? mult_ex3_src2_fwd_data[64:0]
: mult_ex2_src2[64:0];
assign mult_ex2_src2_data[64:32] = mult_ex2_src2_h
? mult_ex2_src2_fwd_data[64:32] : 33'b0;
assign mult_ex2_src2_data[31:0] = mult_ex2_src2_fwd_data[31:0];
//----------------------------------------------------------
// Pipe1 EX3 Instruction valid
//----------------------------------------------------------
always @(posedge mult_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mult_ex3_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
mult_ex3_inst_vld <= 1'b0;
else
mult_ex3_inst_vld <= mult_ex2_inst_vld;
end
assign mult_rbus_ex3_data_vld = mult_ex3_inst_vld;
//----------------------------------------------------------
// Pipe1 EX3 Instruction Data
//----------------------------------------------------------
always @(posedge ex3_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex3_dst_preg[6:0] <= 7'b0;
mult_ex3_rslt_sel[1:0] <= 2'b0;
mult_ex3_mla <= 1'b0;
end
else if(mult_ex2_inst_vld) begin
mult_ex3_dst_preg[6:0] <= mult_ex2_dst_preg[6:0];
mult_ex3_rslt_sel[1:0] <= mult_ex2_rslt_sel[1:0];
mult_ex3_mla <= mult_ex2_mla;
end
else begin
mult_ex3_dst_preg[6:0] <= mult_ex3_dst_preg[6:0];
mult_ex3_rslt_sel[1:0] <= mult_ex3_rslt_sel[1:0];
mult_ex3_mla <= mult_ex3_mla;
end
end
assign mult_rbus_ex3_preg[6:0] = mult_ex3_dst_preg[6:0];
//----------------------------------------------------------
// Pipe1 EX4 Instruction valid
//----------------------------------------------------------
always @(posedge mult_clk or negedge cpurst_b)
begin
if(!cpurst_b)
mult_ex4_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
mult_ex4_inst_vld <= 1'b0;
else
mult_ex4_inst_vld <= mult_ex3_inst_vld;
end
assign mult_rbus_ex4_data_vld = mult_ex4_inst_vld;
//----------------------------------------------------------
// Pipe1 EX4 Instruction Data
//----------------------------------------------------------
always @(posedge ex4_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex4_dst_preg[6:0] <= 7'b0;
mult_ex4_rslt_sel[1:0] <= 2'b0;
end
else if(mult_ex3_inst_vld) begin
mult_ex4_dst_preg[6:0] <= mult_ex3_dst_preg[6:0];
mult_ex4_rslt_sel[1:0] <= mult_ex3_rslt_sel[1:0];
end
else begin
mult_ex4_dst_preg[6:0] <= mult_ex4_dst_preg[6:0];
mult_ex4_rslt_sel[1:0] <= mult_ex4_rslt_sel[1:0];
end
end
//----------------------------------------------------------
// Pipe1 EX4 Instruction Data
//----------------------------------------------------------
always @(posedge ex4_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
mult_ex4_result[127:0] <= 128'b0;
end
else if(mult_ex3_inst_vld) begin
mult_ex4_result[127:0] <= mult_multiplier_result[127:0];
end
else begin
mult_ex4_result[127:0] <= mult_ex4_result[127:0];
end
end
assign mult_ex4_src2_fwd_data[64:0] = {mult_ex4_result[63],
mult_ex4_result[63:0]};
//==========================================================
// EX1~EX3 Design Ware 65x65 multiplier
// this multiplier cross from ex1 stage to ex3 stage
//==========================================================
// &Force("nonport", "mult_multiplier_result"); @410
// &Force("bus","mult_multiplier_result",129,0); @411
// &Instance("multiplier_65x65_3_stage", "x_ct_iu_mult_multiplier_65x65_3_stage"); @413
multiplier_65x65_3_stage x_ct_iu_mult_multiplier_65x65_3_stage (
.addend (mult_ex2_src2_data[64:0] ),
.cpurst_b (cpurst_b ),
.multiplicand (mult_ex1_src0[64:0] ),
.multiplier (mult_ex1_src1[64:0] ),
.pipe1_clk (ex2_inst_clk ),
.pipe1_down (mult_ex1_inst_vld ),
.pipe2_clk (ex3_inst_clk ),
.pipe2_down (mult_ex2_inst_vld ),
.product (mult_multiplier_result[129:0]),
.sub_vld (mult_ex1_sub )
);
// &Connect(.pipe1_clk (ex2_inst_clk), @414
// .pipe2_clk (ex3_inst_clk), @415
// .pipe1_down (mult_ex1_inst_vld), @416
// .pipe2_down (mult_ex2_inst_vld), @417
// .sub_vld (mult_ex1_sub), @418
// .multiplicand (mult_ex1_src0[64:0]), @419
// .multiplier (mult_ex1_src1[64:0]), @420
// .addend (mult_ex2_src2_data[64:0]), @421
// .product (mult_multiplier_result[129:0]) @422
// ); @423
assign mult_ex3_src2_fwd_data[64:0] = {mult_multiplier_result[63],
mult_multiplier_result[63:0]};
//==========================================================
// EX4 Result Selection
//==========================================================
// &CombBeg; @431
always @( mult_ex4_result[127:0]
or mult_ex4_result[31:0]
or mult_ex4_rslt_sel[1:0])
begin
case (mult_ex4_rslt_sel[1:0])
2'b00 : mult_rbus_ex4_data[63:0] = mult_ex4_result[63:0];
2'b01 : mult_rbus_ex4_data[63:0] = mult_ex4_result[127:64];
2'b10 : mult_rbus_ex4_data[63:0] = {{32{mult_ex4_result[31]}},
mult_ex4_result[31:0]};
default: mult_rbus_ex4_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @439
end
// &ModuleEnd; @441
endmodule |
module multiplier_65x65_3_stage(
pipe1_clk,
pipe2_clk,
cpurst_b,
pipe1_down,
pipe2_down,
multiplicand,
multiplier,
addend,
sub_vld,
product
);
input [64:0] multiplicand;
input [64:0] multiplier;
input [64:0] addend;
input sub_vld;
input pipe1_clk;
input pipe2_clk;
input cpurst_b;
input pipe1_down;
input pipe2_down;
output [129:0] product;
wire [64:0] multiplicand_not;
wire [65:0] part_product0, part_product1, part_product2, part_product3;
wire [65:0] part_product4, part_product5, part_product6, part_product7;
wire [65:0] part_product8, part_product9, part_product10,part_product11;
wire [65:0] part_product12,part_product13,part_product14,part_product15;
wire [65:0] part_product16,part_product17,part_product18,part_product19;
wire [65:0] part_product20,part_product21,part_product22,part_product23;
wire [65:0] part_product24,part_product25,part_product26,part_product27;
wire [65:0] part_product28,part_product29,part_product30,part_product31;
wire [65:0] part_product32;
wire [63:0] part_product33;
wire [ 1:0] h0,h1,h2,h3,h4,h5,h6,h7,h8,h9,h10,h11,h12,h13,h14,h15,h16,h17,h18,h19,h20,h21,h22,h23,h24,h25,h26,h27,h28,h29,h30,h31,h32;
wire [32:0] sign_not;
//for calculate a-b*c, mult calculate can be extend as:
// (~multiplicand + 1) * multiplier
//= ~multiplicand * multiplier + multiplier
assign multiplicand_not[64:0] = (sub_vld)
? ~multiplicand[64:0]
: multiplicand[64:0];
// partial product
booth_code #(65) x_booth_code0 (.A(multiplicand_not),.code({multiplier[1:0],1'b0}), .product(part_product0), .h(h0), .sn(sign_not[0]));
booth_code #(65) x_booth_code1 (.A(multiplicand_not),.code(multiplier[ 3: 1]), .product(part_product1), .h(h1), .sn(sign_not[1]));
booth_code #(65) x_booth_code2 (.A(multiplicand_not),.code(multiplier[ 5: 3]), .product(part_product2), .h(h2), .sn(sign_not[2]));
booth_code #(65) x_booth_code3 (.A(multiplicand_not),.code(multiplier[ 7: 5]), .product(part_product3), .h(h3), .sn(sign_not[3]));
booth_code #(65) x_booth_code4 (.A(multiplicand_not),.code(multiplier[ 9: 7]), .product(part_product4), .h(h4), .sn(sign_not[4]));
booth_code #(65) x_booth_code5 (.A(multiplicand_not),.code(multiplier[11: 9]), .product(part_product5), .h(h5), .sn(sign_not[5]));
booth_code #(65) x_booth_code6 (.A(multiplicand_not),.code(multiplier[13:11]), .product(part_product6), .h(h6), .sn(sign_not[6]));
booth_code #(65) x_booth_code7 (.A(multiplicand_not),.code(multiplier[15:13]), .product(part_product7), .h(h7), .sn(sign_not[7]));
booth_code #(65) x_booth_code8 (.A(multiplicand_not),.code(multiplier[17:15]), .product(part_product8), .h(h8), .sn(sign_not[8]));
booth_code #(65) x_booth_code9 (.A(multiplicand_not),.code(multiplier[19:17]), .product(part_product9), .h(h9), .sn(sign_not[9]));
booth_code #(65) x_booth_code10(.A(multiplicand_not),.code(multiplier[21:19]), .product(part_product10),.h(h10),.sn(sign_not[10]));
booth_code #(65) x_booth_code11(.A(multiplicand_not),.code(multiplier[23:21]), .product(part_product11),.h(h11),.sn(sign_not[11]));
booth_code #(65) x_booth_code12(.A(multiplicand_not),.code(multiplier[25:23]), .product(part_product12),.h(h12),.sn(sign_not[12]));
booth_code #(65) x_booth_code13(.A(multiplicand_not),.code(multiplier[27:25]), .product(part_product13),.h(h13),.sn(sign_not[13]));
booth_code #(65) x_booth_code14(.A(multiplicand_not),.code(multiplier[29:27]), .product(part_product14),.h(h14),.sn(sign_not[14]));
booth_code #(65) x_booth_code15(.A(multiplicand_not),.code(multiplier[31:29]), .product(part_product15),.h(h15),.sn(sign_not[15]));
booth_code #(65) x_booth_code16(.A(multiplicand_not),.code(multiplier[33:31]), .product(part_product16),.h(h16),.sn(sign_not[16]));
booth_code #(65) x_booth_code17(.A(multiplicand_not),.code(multiplier[35:33]), .product(part_product17),.h(h17),.sn(sign_not[17]));
booth_code #(65) x_booth_code18(.A(multiplicand_not),.code(multiplier[37:35]), .product(part_product18),.h(h18),.sn(sign_not[18]));
booth_code #(65) x_booth_code19(.A(multiplicand_not),.code(multiplier[39:37]), .product(part_product19),.h(h19),.sn(sign_not[19]));
booth_code #(65) x_booth_code20(.A(multiplicand_not),.code(multiplier[41:39]), .product(part_product20),.h(h20),.sn(sign_not[20]));
booth_code #(65) x_booth_code21(.A(multiplicand_not),.code(multiplier[43:41]), .product(part_product21),.h(h21),.sn(sign_not[21]));
booth_code #(65) x_booth_code22(.A(multiplicand_not),.code(multiplier[45:43]), .product(part_product22),.h(h22),.sn(sign_not[22]));
booth_code #(65) x_booth_code23(.A(multiplicand_not),.code(multiplier[47:45]), .product(part_product23),.h(h23),.sn(sign_not[23]));
booth_code #(65) x_booth_code24(.A(multiplicand_not),.code(multiplier[49:47]), .product(part_product24),.h(h24),.sn(sign_not[24]));
booth_code #(65) x_booth_code25(.A(multiplicand_not),.code(multiplier[51:49]), .product(part_product25),.h(h25),.sn(sign_not[25]));
booth_code #(65) x_booth_code26(.A(multiplicand_not),.code(multiplier[53:51]), .product(part_product26),.h(h26),.sn(sign_not[26]));
booth_code #(65) x_booth_code27(.A(multiplicand_not),.code(multiplier[55:53]), .product(part_product27),.h(h27),.sn(sign_not[27]));
booth_code #(65) x_booth_code28(.A(multiplicand_not),.code(multiplier[57:55]), .product(part_product28),.h(h28),.sn(sign_not[28]));
booth_code #(65) x_booth_code29(.A(multiplicand_not),.code(multiplier[59:57]), .product(part_product29),.h(h29),.sn(sign_not[29]));
booth_code #(65) x_booth_code30(.A(multiplicand_not),.code(multiplier[61:59]), .product(part_product30),.h(h30),.sn(sign_not[30]));
booth_code #(65) x_booth_code31(.A(multiplicand_not),.code(multiplier[63:61]), .product(part_product31),.h(h31),.sn(sign_not[31]));
booth_code #(65) x_booth_code32(.A(multiplicand_not),.code({multiplier[64],multiplier[64:63]}), .product(part_product32),.h(h32),.sn(sign_not[32]));
//for a-b*c(mult sub),regard multiplier as one part product
assign part_product33[63:0] = (sub_vld)
? multiplier[63:0]
: 64'b0;
//----------------------------------------------------------
// L1 compressor
//----------------------------------------------------------
// first level compressor:
// components: 8 4:2 compressor
// result: 34 partial products -> 18 paritial products
wire [72:0] p0_0,p0_1,p0_2,p0_3,p0_cin,cout0_0;
wire [74:0] p1_0,p1_1,p1_2,p1_3,p1_cin,cout0_1;
wire [74:0] p2_0,p2_1,p2_2,p2_3,p2_cin,cout0_2;
wire [74:0] p3_0,p3_1,p3_2,p3_3,p3_cin,cout0_3;
wire [74:0] p4_0,p4_1,p4_2,p4_3,p4_cin,cout0_4;
wire [74:0] p5_0,p5_1,p5_2,p5_3,p5_cin,cout0_5;
wire [74:0] p6_0,p6_1,p6_2,p6_3,p6_cin,cout0_6;
wire [74:0] p7_0,p7_1,p7_2,p7_3,p7_cin,cout0_7;
assign p0_0[72:0] = {4'b0,sign_not[0],{2{!sign_not[0]}},part_product0[65:0]}; //0
assign p0_1[72:0] = {4'b0,sign_not[1],part_product1[65:0],h0[1:0]};
assign p0_2[72:0] = {2'b0,sign_not[2],part_product2[65:0],h1[1:0],2'b0};
assign p0_3[72:0] = {sign_not[3],part_product3[65:0],h2[1:0],3'b0,1'b0};
assign p0_cin[72:0] = {cout0_0[71:0],1'b0};
assign p1_0[74:0] = {6'b0,sign_not[4],part_product4[65:0],h3[1:0]};
assign p1_1[74:0] = {4'b0,sign_not[5],part_product5[65:0],h4[1:0],2'b0};
assign p1_2[74:0] = {2'b0,sign_not[6],part_product6[65:0],h5[1:0],4'b0};
assign p1_3[74:0] = {sign_not[7],part_product7[65:0],h6[1:0],6'b0};
assign p1_cin[74:0] = {cout0_1[73:0],1'b0};
assign p2_0[74:0] = {6'b0,sign_not[8],part_product8[65:0],h7[1:0]};
assign p2_1[74:0] = {4'b0,sign_not[9],part_product9[65:0],h8[1:0],2'b0};
assign p2_2[74:0] = {2'b0,sign_not[10],part_product10[65:0],h9[1:0],4'b0};
assign p2_3[74:0] = {sign_not[11],part_product11[65:0],h10[1:0],6'b0};
assign p2_cin[74:0] = {cout0_2[73:0],1'b0};
assign p3_0[74:0] = {6'b0,sign_not[12],part_product12[65:0],h11[1:0]};
assign p3_1[74:0] = {4'b0,sign_not[13],part_product13[65:0],h12[1:0],2'b0};
assign p3_2[74:0] = {2'b0,sign_not[14],part_product14[65:0],h13[1:0],4'b0};
assign p3_3[74:0] = {sign_not[15],part_product15[65:0],h14[1:0],6'b0};
assign p3_cin[74:0] = {cout0_3[73:0],1'b0};
assign p4_0[74:0] = {6'b0,sign_not[16],part_product16[65:0],h15[1:0]};
assign p4_1[74:0] = {4'b0,sign_not[17],part_product17[65:0],h16[1:0],2'b0};
assign p4_2[74:0] = {2'b0,sign_not[18],part_product18[65:0],h17[1:0],4'b0};
assign p4_3[74:0] = {sign_not[19],part_product19[65:0],h18[1:0],6'b0};
assign p4_cin[74:0] = {cout0_4[73:0],1'b0};
assign p5_0[74:0] = {6'b0,sign_not[20],part_product20[65:0],h19[1:0]};
assign p5_1[74:0] = {4'b0,sign_not[21],part_product21[65:0],h20[1:0],2'b0};
assign p5_2[74:0] = {2'b0,sign_not[22],part_product22[65:0],h21[1:0],4'b0};
assign p5_3[74:0] = {sign_not[23],part_product23[65:0],h22[1:0],6'b0};
assign p5_cin[74:0] = {cout0_5[73:0],1'b0};
assign p6_0[74:0] = {6'b0,sign_not[24],part_product24[65:0],h23[1:0]};
assign p6_1[74:0] = {4'b0,sign_not[25],part_product25[65:0],h24[1:0],2'b0};
assign p6_2[74:0] = {2'b0,sign_not[26],part_product26[65:0],h25[1:0],4'b0};
assign p6_3[74:0] = {sign_not[27],part_product27[65:0],h26[1:0],6'b0};
assign p6_cin[74:0] = {cout0_6[73:0],1'b0};
assign p7_0[74:0] = {6'b0,sign_not[28],part_product28[65:0],h27[1:0]};
assign p7_1[74:0] = {4'b0,sign_not[29],part_product29[65:0],h28[1:0],2'b0};
assign p7_2[74:0] = {2'b0,sign_not[30],part_product30[65:0],h29[1:0],4'b0};
assign p7_3[74:0] = {sign_not[31],part_product31[65:0],h30[1:0],6'b0};
assign p7_cin[74:0] = {cout0_7[73:0],1'b0};
wire [72:0] s0_0,c0_0;
wire [74:0] s0_1,c0_1;
wire [74:0] s0_2,c0_2;
wire [74:0] s0_3,c0_3;
wire [74:0] s0_4,c0_4;
wire [74:0] s0_5,c0_5;
wire [74:0] s0_6,c0_6;
wire [74:0] s0_7,c0_7;
compressor_42 #(73) x_comp0_0(.p0 (p0_0[72:0]),
.p1 (p0_1[72:0]),
.p2 (p0_2[72:0]),
.p3 (p0_3[72:0]),
.cin (p0_cin[72:0]),
.s (s0_0[72:0]),
.ca (c0_0[72:0]),
.cout (cout0_0[72:0]));
compressor_42 #(75) x_comp0_1(.p0 (p1_0[74:0]),
.p1 (p1_1[74:0]),
.p2 (p1_2[74:0]),
.p3 (p1_3[74:0]),
.cin (p1_cin[74:0]),
.s (s0_1[74:0]),
.ca (c0_1[74:0]),
.cout (cout0_1[74:0]));
compressor_42 #(75) x_comp0_2(.p0 (p2_0[74:0]),
.p1 (p2_1[74:0]),
.p2 (p2_2[74:0]),
.p3 (p2_3[74:0]),
.cin (p2_cin[74:0]),
.s (s0_2[74:0]),
.ca (c0_2[74:0]),
.cout (cout0_2[74:0]));
compressor_42 #(75) x_comp0_3(.p0 (p3_0[74:0]),
.p1 (p3_1[74:0]),
.p2 (p3_2[74:0]),
.p3 (p3_3[74:0]),
.cin (p3_cin[74:0]),
.s (s0_3[74:0]),
.ca (c0_3[74:0]),
.cout (cout0_3[74:0]));
compressor_42 #(75) x_comp0_4(.p0 (p4_0[74:0]),
.p1 (p4_1[74:0]),
.p2 (p4_2[74:0]),
.p3 (p4_3[74:0]),
.cin (p4_cin[74:0]),
.s (s0_4[74:0]),
.ca (c0_4[74:0]),
.cout (cout0_4[74:0]));
compressor_42 #(75) x_comp0_5(.p0 (p5_0[74:0]),
.p1 (p5_1[74:0]),
.p2 (p5_2[74:0]),
.p3 (p5_3[74:0]),
.cin (p5_cin[74:0]),
.s (s0_5[74:0]),
.ca (c0_5[74:0]),
.cout (cout0_5[74:0]));
compressor_42 #(75) x_comp0_6(.p0 (p6_0[74:0]),
.p1 (p6_1[74:0]),
.p2 (p6_2[74:0]),
.p3 (p6_3[74:0]),
.cin (p6_cin[74:0]),
.s (s0_6[74:0]),
.ca (c0_6[74:0]),
.cout (cout0_6[74:0]));
compressor_42 #(75) x_comp0_7(.p0 (p7_0[74:0]),
.p1 (p7_1[74:0]),
.p2 (p7_2[74:0]),
.p3 (p7_3[74:0]),
.cin (p7_cin[74:0]),
.s (s0_7[74:0]),
.ca (c0_7[74:0]),
.cout (cout0_7[74:0]));
//----------------------------------------------------------
// L2 compressor
//----------------------------------------------------------
// second level compressor:
// components: 6 3:2 compressor
// result: 18 partial products -> 12 paritial products
wire [80:0] q0_0,q0_1,q0_2;
wire [82:0] q1_0,q1_1,q1_2;
wire [82:0] q2_0,q2_1,q2_2;
wire [82:0] q3_0,q3_1,q3_2;
wire [82:0] q4_0,q4_1,q4_2;
wire [74:0] q5_0,q5_1,q5_2;
assign q0_0[80:0] = {8'b0,s0_0[72:0]};
assign q0_1[80:0] = {7'b0,c0_0[72:0],1'b0};
assign q0_2[80:0] = {s0_1[74:0],6'b0};
assign q1_0[82:0] = {8'b0,c0_1[74:0]};
assign q1_1[82:0] = {1'b0,s0_2[74:0],7'b0};
assign q1_2[82:0] = {c0_2[74:0],8'b0};
assign q2_0[82:0] = {8'b0,s0_3[74:0]};
assign q2_1[82:0] = {7'b0,c0_3[74:0],1'b0};
assign q2_2[82:0] = {s0_4[74:0],8'b0};
assign q3_0[82:0] = {8'b0,c0_4[74:0]};
assign q3_1[82:0] = {1'b0,s0_5[74:0],7'b0};
assign q3_2[82:0] = {c0_5[74:0],8'b0};
assign q4_0[82:0] = {8'b0,s0_6[74:0]};
assign q4_1[82:0] = {7'b0,c0_6[74:0],1'b0};
assign q4_2[82:0] = {s0_7[74:0],8'b0};
assign q5_0[74:0] = c0_7[74:0];
assign q5_1[74:0] = {part_product32[65:0],h31[1:0],7'b0};
assign q5_2[74:0] = {{31{2'b10}},2'b0,h32[1:0],part_product33[63:55]};
wire [80:0] s1_0,c1_0;
wire [82:0] s1_1,c1_1;
wire [82:0] s1_2,c1_2;
wire [82:0] s1_3,c1_3;
wire [82:0] s1_4,c1_4;
wire [74:0] s1_5,c1_5;
compressor_32 #(81) x_comp1_0(.a (q0_0[80:0]), .b (q0_1[80:0]), .c (q0_2[80:0]), .s (s1_0[80:0]), .ca (c1_0[80:0]));
compressor_32 #(83) x_comp1_1(.a (q1_0[82:0]), .b (q1_1[82:0]), .c (q1_2[82:0]), .s (s1_1[82:0]), .ca (c1_1[82:0]));
compressor_32 #(83) x_comp1_2(.a (q2_0[82:0]), .b (q2_1[82:0]), .c (q2_2[82:0]), .s (s1_2[82:0]), .ca (c1_2[82:0]));
compressor_32 #(83) x_comp1_3(.a (q3_0[82:0]), .b (q3_1[82:0]), .c (q3_2[82:0]), .s (s1_3[82:0]), .ca (c1_3[82:0]));
compressor_32 #(83) x_comp1_4(.a (q4_0[82:0]), .b (q4_1[82:0]), .c (q4_2[82:0]), .s (s1_4[82:0]), .ca (c1_4[82:0]));
compressor_32 #(75) x_comp1_5(.a (q5_0[74:0]), .b (q5_1[74:0]), .c (q5_2[74:0]), .s (s1_5[74:0]), .ca (c1_5[74:0]));
reg [80:0] s0_reg,c0_reg;
reg [82:0] s1_reg,c1_reg;
reg [82:0] s2_reg,c2_reg;
reg [82:0] s3_reg,c3_reg;
reg [82:0] s4_reg,c4_reg;
reg [74:0] s5_reg,c5_reg;
reg [54:0] s6_reg;
always @(posedge pipe1_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
s0_reg[80:0] <= 81'b0;
s1_reg[82:0] <= 83'b0;
s2_reg[82:0] <= 83'b0;
s3_reg[82:0] <= 83'b0;
s4_reg[82:0] <= 83'b0;
s5_reg[74:0] <= 75'b0;
s6_reg[54:0] <= 55'b0;
c0_reg[80:0] <= 81'b0;
c1_reg[82:0] <= 83'b0;
c2_reg[82:0] <= 83'b0;
c3_reg[82:0] <= 83'b0;
c4_reg[82:0] <= 83'b0;
c5_reg[74:0] <= 75'b0;
end
else if(pipe1_down) begin
s0_reg[80:0] <= s1_0[80:0];
s1_reg[82:0] <= s1_1[82:0];
s2_reg[82:0] <= s1_2[82:0];
s3_reg[82:0] <= s1_3[82:0];
s4_reg[82:0] <= s1_4[82:0];
s5_reg[74:0] <= s1_5[74:0];
s6_reg[54:0] <= part_product33[54:0];
c0_reg[80:0] <= c1_0[80:0];
c1_reg[82:0] <= c1_1[82:0];
c2_reg[82:0] <= c1_2[82:0];
c3_reg[82:0] <= c1_3[82:0];
c4_reg[82:0] <= c1_4[82:0];
c5_reg[74:0] <= c1_5[74:0];
end
else begin
s0_reg[80:0] <= s0_reg[80:0];
s1_reg[82:0] <= s1_reg[82:0];
s2_reg[82:0] <= s2_reg[82:0];
s3_reg[82:0] <= s3_reg[82:0];
s4_reg[82:0] <= s4_reg[82:0];
s5_reg[74:0] <= s5_reg[74:0];
s6_reg[54:0] <= s6_reg[54:0];
c0_reg[80:0] <= c0_reg[80:0];
c1_reg[82:0] <= c1_reg[82:0];
c2_reg[82:0] <= c2_reg[82:0];
c3_reg[82:0] <= c3_reg[82:0];
c4_reg[82:0] <= c4_reg[82:0];
c5_reg[74:0] <= c5_reg[74:0];
end
end
//----------------------------------------------------------
// L3 compressor
//----------------------------------------------------------
// third level compressor:
// components: 3 4:2 compressor
// result: 12 partial products -> 6 paritial products
wire [90:0] r0_0,r0_1,r0_2,r0_3,r0_cin,cout2_0;
wire [92:0] r1_0,r1_1,r1_2,r1_3,r1_cin,cout2_1;
wire [83:0] r2_0,r2_1,r2_2,r2_3,r2_cin,cout2_2;
assign r0_0[90:0] = {10'b0,s0_reg[80:0]};
assign r0_1[90:0] = {9'b0,c0_reg[80:0],1'b0};
assign r0_2[90:0] = {1'b0,s1_reg[82:0],7'b0};
assign r0_3[90:0] = {c1_reg[82:0],8'b0};
assign r0_cin[90:0] = {cout2_0[89:0],1'b0};
assign r1_0[92:0] = {10'b0,s2_reg[82:0]};
assign r1_1[92:0] = {9'b0,c2_reg[82:0],1'b0};
assign r1_2[92:0] = {1'b0,s3_reg[82:0],9'b0};
assign r1_3[92:0] = {c3_reg[82:0],10'b0};
assign r1_cin[92:0] = {cout2_1[91:0],1'b0};
assign r2_0[83:0] = {1'b0,s4_reg[82:0]};
assign r2_1[83:0] = {c4_reg[82:0],1'b0};
assign r2_2[83:0] = {s5_reg[74:0],9'b0};
assign r2_3[83:0] = {c5_reg[73:0],1'b0,s6_reg[54:46]};
assign r2_cin[83:0] = {cout2_2[82:0],1'b0};
wire [90:0] s2_0,c2_0;
wire [92:0] s2_1,c2_1;
wire [83:0] s2_2,c2_2;
compressor_42 #(91) x_comp2_0(.p0 (r0_0[90:0]),
.p1 (r0_1[90:0]),
.p2 (r0_2[90:0]),
.p3 (r0_3[90:0]),
.cin (r0_cin[90:0]),
.s (s2_0[90:0]),
.ca (c2_0[90:0]),
.cout (cout2_0[90:0]));
compressor_42 #(93) x_comp2_1(.p0 (r1_0[92:0]),
.p1 (r1_1[92:0]),
.p2 (r1_2[92:0]),
.p3 (r1_3[92:0]),
.cin (r1_cin[92:0]),
.s (s2_1[92:0]),
.ca (c2_1[92:0]),
.cout (cout2_1[92:0]));
compressor_42 #(84) x_comp2_2(.p0 (r2_0[83:0]),
.p1 (r2_1[83:0]),
.p2 (r2_2[83:0]),
.p3 (r2_3[83:0]),
.cin (r2_cin[83:0]),
.s (s2_2[83:0]),
.ca (c2_2[83:0]),
.cout (cout2_2[83:0]));
//----------------------------------------------------------
// L4 compressor
//----------------------------------------------------------
// forth level compressor:
// components: 2 3:2 compressor
// result: 6 partial products -> 4 paritial products
wire [114:0] t0_0,t0_1,t0_2;
wire [106:0] t1_0,t1_1,t1_2;
assign t0_0[114:0] = {24'b0,s2_0[90:0]};
assign t0_1[114:0] = {23'b0,c2_0[90:0],1'b0};
assign t0_2[114:0] = {s2_1[92:0],22'b0};
assign t1_0[106:0] = {14'b0,c2_1[92:0]};
assign t1_1[106:0] = {s2_2[83:0],23'b0};
assign t1_2[106:0] = {c2_2[82:0],1'b0,s6_reg[45:23]};
wire [114:0] s3_0,c3_0;
wire [106:0] s3_1,c3_1;
compressor_32 #(115) x_comp3_0(.a (t0_0[114:0]), .b (t0_1[114:0]), .c (t0_2[114:0]), .s (s3_0[114:0]), .ca (c3_0[114:0]));
compressor_32 #(107) x_comp3_1(.a (t1_0[106:0]), .b (t1_1[106:0]), .c (t1_2[106:0]), .s (s3_1[106:0]), .ca (c3_1[106:0]));
//----------------------------------------------------------
// L5 compressor
//----------------------------------------------------------
// fifth level compressor:
// components: 1 4:2 compressor
// result: 4 partial products -> 2 paritial products
wire [129:0] v0_0,v0_1,v0_2,v0_3,v0_cin,cout4_0;
assign v0_0[129:0] = {15'b0, s3_0[114:0]};
assign v0_1[129:0] = {14'b0, c3_0[114:0],1'b0};
assign v0_2[129:0] = { s3_1[106:0],23'b0};
assign v0_3[129:0] = { c3_1[105:0],1'b0,s6_reg[22:0]};
assign v0_cin[129:0] = { cout4_0[128:0],1'b0};
wire [129:0] s4_0,c4_0;
compressor_42 #(130) x_comp4_1(.p0 (v0_0[129:0]),
.p1 (v0_1[129:0]),
.p2 (v0_2[129:0]),
.p3 (v0_3[129:0]),
.cin (v0_cin[129:0]),
.s (s4_0[129:0]),
.ca (c4_0[129:0]),
.cout (cout4_0[129:0]));
reg [129:0] sum,carry;
reg [63:0] addend_reg;
always @(posedge pipe2_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
sum[129:0] <= 130'b0;
carry[129:0] <= 130'b0;
addend_reg[63:0] <= 64'b0;
end
else if(pipe2_down) begin
sum[129:0] <= s4_0[129:0];
carry[129:0] <= c4_0[129:0];
addend_reg[63:0] <= addend[63:0];
end
else begin
sum[129:0] <= sum[129:0];
carry[129:0] <= carry[129:0];
addend_reg[63:0] <= addend_reg[63:0];
end
end
//----------------------------------------------------------
// L6 compressor
//----------------------------------------------------------
// sixth level compressor:
// components: 1 3:2 compressor
// result: 3 partial products -> 2 paritial products
wire [63:0] w0_0,w0_1,w0_2;
wire [63:0] s5_0,c5_0;
assign w0_0[63:0] = sum[63:0];
assign w0_1[63:0] = {carry[62:0],1'b0};
assign w0_2[63:0] = addend_reg[63:0];
compressor_32 #(64) x_comp5_0(
.a (w0_0[63:0]),
.b (w0_1[63:0]),
.c (w0_2[63:0]),
.s (s5_0[63:0]),
.ca (c5_0[63:0]));
wire [129:0] product_mult;
wire [63:0] product_mult_add;
assign product_mult[129:0] = sum[129:0] + {carry[128:0],1'b0};
assign product_mult_add[63:0] = s5_0[63:0] + {c5_0[62:0],1'b0};
//final result:
//mult_add: only low 64-bit result is valid
//mult: all 129 bit is valid,
assign product[129:0] = {product_mult[129:64],product_mult_add[63:0]};
endmodule |
module ct_iu_cbus(
bju_cbus_ex2_pipe2_abnormal,
bju_cbus_ex2_pipe2_bht_mispred,
bju_cbus_ex2_pipe2_iid,
bju_cbus_ex2_pipe2_jmp_mispred,
bju_cbus_ex2_pipe2_sel,
cp0_iu_ex3_abnormal,
cp0_iu_ex3_efpc,
cp0_iu_ex3_efpc_vld,
cp0_iu_ex3_expt_vec,
cp0_iu_ex3_expt_vld,
cp0_iu_ex3_flush,
cp0_iu_ex3_iid,
cp0_iu_ex3_inst_vld,
cp0_iu_ex3_mtval,
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
idu_iu_rf_div_sel,
idu_iu_rf_mult_sel,
idu_iu_rf_pipe0_cbus_gateclk_sel,
idu_iu_rf_pipe0_iid,
idu_iu_rf_pipe0_sel,
idu_iu_rf_pipe1_cbus_gateclk_sel,
idu_iu_rf_pipe1_iid,
idu_iu_rf_pipe1_sel,
iu_rtu_pipe0_abnormal,
iu_rtu_pipe0_bkpt,
iu_rtu_pipe0_cmplt,
iu_rtu_pipe0_efpc,
iu_rtu_pipe0_efpc_vld,
iu_rtu_pipe0_expt_vec,
iu_rtu_pipe0_expt_vld,
iu_rtu_pipe0_flush,
iu_rtu_pipe0_high_hw_expt,
iu_rtu_pipe0_iid,
iu_rtu_pipe0_immu_expt,
iu_rtu_pipe0_mtval,
iu_rtu_pipe0_vsetvl,
iu_rtu_pipe0_vstart,
iu_rtu_pipe0_vstart_vld,
iu_rtu_pipe1_cmplt,
iu_rtu_pipe1_iid,
iu_rtu_pipe2_abnormal,
iu_rtu_pipe2_bht_mispred,
iu_rtu_pipe2_cmplt,
iu_rtu_pipe2_iid,
iu_rtu_pipe2_jmp_mispred,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
special_cbus_ex1_abnormal,
special_cbus_ex1_bkpt,
special_cbus_ex1_expt_vec,
special_cbus_ex1_expt_vld,
special_cbus_ex1_flush,
special_cbus_ex1_high_hw_expt,
special_cbus_ex1_iid,
special_cbus_ex1_immu_expt,
special_cbus_ex1_inst_gateclk_vld,
special_cbus_ex1_inst_vld,
special_cbus_ex1_mtval,
special_cbus_ex1_vsetvl,
special_cbus_ex1_vstart,
special_cbus_ex1_vstart_vld
);
// &Ports; @27
input bju_cbus_ex2_pipe2_abnormal;
input bju_cbus_ex2_pipe2_bht_mispred;
input [6 :0] bju_cbus_ex2_pipe2_iid;
input bju_cbus_ex2_pipe2_jmp_mispred;
input bju_cbus_ex2_pipe2_sel;
input cp0_iu_ex3_abnormal;
input [38:0] cp0_iu_ex3_efpc;
input cp0_iu_ex3_efpc_vld;
input [4 :0] cp0_iu_ex3_expt_vec;
input cp0_iu_ex3_expt_vld;
input cp0_iu_ex3_flush;
input [6 :0] cp0_iu_ex3_iid;
input cp0_iu_ex3_inst_vld;
input [31:0] cp0_iu_ex3_mtval;
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input idu_iu_rf_div_sel;
input idu_iu_rf_mult_sel;
input idu_iu_rf_pipe0_cbus_gateclk_sel;
input [6 :0] idu_iu_rf_pipe0_iid;
input idu_iu_rf_pipe0_sel;
input idu_iu_rf_pipe1_cbus_gateclk_sel;
input [6 :0] idu_iu_rf_pipe1_iid;
input idu_iu_rf_pipe1_sel;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input special_cbus_ex1_abnormal;
input special_cbus_ex1_bkpt;
input [4 :0] special_cbus_ex1_expt_vec;
input special_cbus_ex1_expt_vld;
input special_cbus_ex1_flush;
input special_cbus_ex1_high_hw_expt;
input [6 :0] special_cbus_ex1_iid;
input special_cbus_ex1_immu_expt;
input special_cbus_ex1_inst_gateclk_vld;
input special_cbus_ex1_inst_vld;
input [31:0] special_cbus_ex1_mtval;
input special_cbus_ex1_vsetvl;
input [6 :0] special_cbus_ex1_vstart;
input special_cbus_ex1_vstart_vld;
output iu_rtu_pipe0_abnormal;
output iu_rtu_pipe0_bkpt;
output iu_rtu_pipe0_cmplt;
output [38:0] iu_rtu_pipe0_efpc;
output iu_rtu_pipe0_efpc_vld;
output [4 :0] iu_rtu_pipe0_expt_vec;
output iu_rtu_pipe0_expt_vld;
output iu_rtu_pipe0_flush;
output iu_rtu_pipe0_high_hw_expt;
output [6 :0] iu_rtu_pipe0_iid;
output iu_rtu_pipe0_immu_expt;
output [31:0] iu_rtu_pipe0_mtval;
output iu_rtu_pipe0_vsetvl;
output [6 :0] iu_rtu_pipe0_vstart;
output iu_rtu_pipe0_vstart_vld;
output iu_rtu_pipe1_cmplt;
output [6 :0] iu_rtu_pipe1_iid;
output iu_rtu_pipe2_abnormal;
output iu_rtu_pipe2_bht_mispred;
output iu_rtu_pipe2_cmplt;
output [6 :0] iu_rtu_pipe2_iid;
output iu_rtu_pipe2_jmp_mispred;
// &Regs; @28
reg cbus_pipe0_abnormal;
reg cbus_pipe0_bkpt;
reg [38:0] cbus_pipe0_efpc;
reg cbus_pipe0_efpc_vld;
reg [4 :0] cbus_pipe0_expt_vec;
reg cbus_pipe0_expt_vld;
reg cbus_pipe0_flush;
reg cbus_pipe0_high_hw_expt;
reg [6 :0] cbus_pipe0_iid;
reg cbus_pipe0_immu_expt;
reg cbus_pipe0_inst_vld;
reg [31:0] cbus_pipe0_mtval;
reg cbus_pipe0_vsetvl;
reg [6 :0] cbus_pipe0_vstart;
reg cbus_pipe0_vstart_vld;
reg [6 :0] cbus_pipe1_iid;
reg cbus_pipe1_inst_vld;
// &Wires; @29
wire bju_cbus_ex2_pipe2_abnormal;
wire bju_cbus_ex2_pipe2_bht_mispred;
wire [6 :0] bju_cbus_ex2_pipe2_iid;
wire bju_cbus_ex2_pipe2_jmp_mispred;
wire bju_cbus_ex2_pipe2_sel;
wire cbus_pipe0_cmplt;
wire cbus_pipe0_gateclk_cmplt;
wire cbus_pipe0_gateclk_src_abnormal;
wire cbus_pipe0_src_abnormal;
wire cbus_pipe0_src_bkpt;
wire [38:0] cbus_pipe0_src_efpc;
wire cbus_pipe0_src_efpc_vld;
wire [4 :0] cbus_pipe0_src_expt_vec;
wire cbus_pipe0_src_expt_vld;
wire cbus_pipe0_src_flush;
wire cbus_pipe0_src_high_hw_expt;
wire [6 :0] cbus_pipe0_src_iid;
wire cbus_pipe0_src_immu_expt;
wire [31:0] cbus_pipe0_src_mtval;
wire cbus_pipe0_src_vsetvl;
wire [6 :0] cbus_pipe0_src_vstart;
wire cbus_pipe0_src_vstart_vld;
wire cbus_pipe1_cmplt;
wire cbus_pipe1_gateclk_cmplt;
wire [6 :0] cbus_pipe1_src_iid;
wire cp0_iu_ex3_abnormal;
wire [38:0] cp0_iu_ex3_efpc;
wire cp0_iu_ex3_efpc_vld;
wire [4 :0] cp0_iu_ex3_expt_vec;
wire cp0_iu_ex3_expt_vld;
wire cp0_iu_ex3_flush;
wire [6 :0] cp0_iu_ex3_iid;
wire cp0_iu_ex3_inst_vld;
wire [31:0] cp0_iu_ex3_mtval;
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire idu_iu_rf_div_sel;
wire idu_iu_rf_mult_sel;
wire idu_iu_rf_pipe0_cbus_gateclk_sel;
wire [6 :0] idu_iu_rf_pipe0_iid;
wire idu_iu_rf_pipe0_sel;
wire idu_iu_rf_pipe1_cbus_gateclk_sel;
wire [6 :0] idu_iu_rf_pipe1_iid;
wire idu_iu_rf_pipe1_sel;
wire inst_vld_clk;
wire inst_vld_clk_en;
wire iu_rtu_pipe0_abnormal;
wire iu_rtu_pipe0_bkpt;
wire iu_rtu_pipe0_cmplt;
wire [38:0] iu_rtu_pipe0_efpc;
wire iu_rtu_pipe0_efpc_vld;
wire [4 :0] iu_rtu_pipe0_expt_vec;
wire iu_rtu_pipe0_expt_vld;
wire iu_rtu_pipe0_flush;
wire iu_rtu_pipe0_high_hw_expt;
wire [6 :0] iu_rtu_pipe0_iid;
wire iu_rtu_pipe0_immu_expt;
wire [31:0] iu_rtu_pipe0_mtval;
wire iu_rtu_pipe0_vsetvl;
wire [6 :0] iu_rtu_pipe0_vstart;
wire iu_rtu_pipe0_vstart_vld;
wire iu_rtu_pipe1_cmplt;
wire [6 :0] iu_rtu_pipe1_iid;
wire iu_rtu_pipe2_abnormal;
wire iu_rtu_pipe2_bht_mispred;
wire iu_rtu_pipe2_cmplt;
wire [6 :0] iu_rtu_pipe2_iid;
wire iu_rtu_pipe2_jmp_mispred;
wire pad_yy_icg_scan_en;
wire pipe0_abnormal_clk;
wire pipe0_abnormal_clk_en;
wire pipe0_data_clk;
wire pipe0_data_clk_en;
wire pipe1_data_clk;
wire pipe1_data_clk_en;
wire rtu_yy_xx_flush;
wire special_cbus_ex1_abnormal;
wire special_cbus_ex1_bkpt;
wire [4 :0] special_cbus_ex1_expt_vec;
wire special_cbus_ex1_expt_vld;
wire special_cbus_ex1_flush;
wire special_cbus_ex1_high_hw_expt;
wire [6 :0] special_cbus_ex1_iid;
wire special_cbus_ex1_immu_expt;
wire special_cbus_ex1_inst_gateclk_vld;
wire special_cbus_ex1_inst_vld;
wire [31:0] special_cbus_ex1_mtval;
wire special_cbus_ex1_vsetvl;
wire [6 :0] special_cbus_ex1_vstart;
wire special_cbus_ex1_vstart_vld;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign inst_vld_clk_en = cbus_pipe0_gateclk_cmplt
|| cbus_pipe1_gateclk_cmplt
|| cbus_pipe0_inst_vld
|| cbus_pipe1_inst_vld;
// &Instance("gated_clk_cell", "x_inst_vld_gated_clk"); @39
gated_clk_cell x_inst_vld_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (inst_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (inst_vld_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @40
// .external_en (1'b0), @41
// .global_en (cp0_yy_clk_en), @42
// .module_en (cp0_iu_icg_en), @43
// .local_en (inst_vld_clk_en), @44
// .clk_out (inst_vld_clk)); @45
//==========================================================
// Pipe0 Complete Signals
//==========================================================
//----------------------------------------------------------
// Complete Source Control Signal
//----------------------------------------------------------
assign cbus_pipe0_cmplt = idu_iu_rf_pipe0_sel
|| idu_iu_rf_div_sel
|| special_cbus_ex1_inst_vld
|| cp0_iu_ex3_inst_vld;
assign cbus_pipe0_gateclk_cmplt = idu_iu_rf_pipe0_cbus_gateclk_sel
|| special_cbus_ex1_inst_gateclk_vld
|| cp0_iu_ex3_inst_vld;
//----------------------------------------------------------
// Complete Instruction Valid
//----------------------------------------------------------
always @(posedge inst_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe0_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
cbus_pipe0_inst_vld <= 1'b0;
else
cbus_pipe0_inst_vld <= cbus_pipe0_cmplt;
end
//output to RTU
assign iu_rtu_pipe0_cmplt = cbus_pipe0_inst_vld;
//----------------------------------------------------------
// Complete Data Selection
//----------------------------------------------------------
assign cbus_pipe0_src_iid[6:0] =
{7{idu_iu_rf_pipe0_sel}} & idu_iu_rf_pipe0_iid[6:0]
| {7{idu_iu_rf_div_sel}} & idu_iu_rf_pipe0_iid[6:0]
| {7{special_cbus_ex1_inst_vld}} & special_cbus_ex1_iid[6:0]
| {7{cp0_iu_ex3_inst_vld}} & cp0_iu_ex3_iid[6:0];
assign cbus_pipe0_src_abnormal =
special_cbus_ex1_inst_vld && special_cbus_ex1_abnormal
|| cp0_iu_ex3_inst_vld && cp0_iu_ex3_abnormal;
assign cbus_pipe0_gateclk_src_abnormal =
special_cbus_ex1_inst_gateclk_vld && special_cbus_ex1_abnormal
|| cp0_iu_ex3_inst_vld && cp0_iu_ex3_abnormal;
assign cbus_pipe0_src_expt_vld =
special_cbus_ex1_inst_vld && special_cbus_ex1_expt_vld
|| cp0_iu_ex3_inst_vld && cp0_iu_ex3_expt_vld;
assign cbus_pipe0_src_expt_vec[4:0] =
{5{special_cbus_ex1_inst_vld}} & special_cbus_ex1_expt_vec[4:0]
| {5{cp0_iu_ex3_inst_vld}} & cp0_iu_ex3_expt_vec[4:0];
assign cbus_pipe0_src_high_hw_expt=
special_cbus_ex1_inst_vld && special_cbus_ex1_high_hw_expt;
assign cbus_pipe0_src_bkpt =
special_cbus_ex1_inst_vld && special_cbus_ex1_bkpt;
assign cbus_pipe0_src_vsetvl =
special_cbus_ex1_inst_vld && special_cbus_ex1_vsetvl;
assign cbus_pipe0_src_vstart_vld =
special_cbus_ex1_inst_vld && special_cbus_ex1_vstart_vld;
assign cbus_pipe0_src_vstart[6:0] =
{7{special_cbus_ex1_inst_vld}} & special_cbus_ex1_vstart[6:0];
assign cbus_pipe0_src_immu_expt =
special_cbus_ex1_inst_vld && special_cbus_ex1_immu_expt;
assign cbus_pipe0_src_mtval[31:0] =
{32{special_cbus_ex1_inst_vld}} & special_cbus_ex1_mtval[31:0]
| {32{cp0_iu_ex3_inst_vld}} & cp0_iu_ex3_mtval[31:0];
assign cbus_pipe0_src_flush =
cp0_iu_ex3_inst_vld && cp0_iu_ex3_flush
|| special_cbus_ex1_inst_vld && special_cbus_ex1_flush;
assign cbus_pipe0_src_efpc_vld =
cp0_iu_ex3_inst_vld && cp0_iu_ex3_efpc_vld;
assign cbus_pipe0_src_efpc[38:0] =
{39{cp0_iu_ex3_inst_vld}} & cp0_iu_ex3_efpc[38:0];
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign pipe0_data_clk_en = cbus_pipe0_gateclk_cmplt;
// &Instance("gated_clk_cell", "x_pipe0_data_gated_clk"); @137
gated_clk_cell x_pipe0_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pipe0_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pipe0_data_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @138
// .external_en (1'b0), @139
// .global_en (cp0_yy_clk_en), @140
// .module_en (cp0_iu_icg_en), @141
// .local_en (pipe0_data_clk_en), @142
// .clk_out (pipe0_data_clk)); @143
assign pipe0_abnormal_clk_en = cbus_pipe0_gateclk_cmplt
&& (cbus_pipe0_gateclk_src_abnormal
|| cbus_pipe0_abnormal);
// &Instance("gated_clk_cell", "x_pipe0_abnormal_gated_clk"); @148
gated_clk_cell x_pipe0_abnormal_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pipe0_abnormal_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pipe0_abnormal_clk_en),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect(.clk_in (forever_cpuclk), @149
// .external_en (1'b0), @150
// .global_en (cp0_yy_clk_en), @151
// .module_en (cp0_iu_icg_en), @152
// .local_en (pipe0_abnormal_clk_en), @153
// .clk_out (pipe0_abnormal_clk)); @154
//----------------------------------------------------------
// Complete Data
//----------------------------------------------------------
always @(posedge pipe0_data_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
cbus_pipe0_iid[6:0] <= 7'b0;
cbus_pipe0_abnormal <= 1'b0;
end
else if(cbus_pipe0_cmplt) begin
cbus_pipe0_iid[6:0] <= cbus_pipe0_src_iid[6:0];
cbus_pipe0_abnormal <= cbus_pipe0_src_abnormal;
end
else begin
cbus_pipe0_iid[6:0] <= cbus_pipe0_iid[6:0];
cbus_pipe0_abnormal <= cbus_pipe0_abnormal;
end
end
//power optimization: clock enable only when abnormal complete
always @(posedge pipe0_abnormal_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
cbus_pipe0_expt_vld <= 1'b0;
cbus_pipe0_expt_vec[4:0] <= 5'b0;
cbus_pipe0_high_hw_expt <= 1'b0;
cbus_pipe0_bkpt <= 1'b0;
cbus_pipe0_vsetvl <= 1'b0;
cbus_pipe0_immu_expt <= 1'b0;
cbus_pipe0_mtval[31:0] <= 32'b0;
cbus_pipe0_flush <= 1'b0;
cbus_pipe0_efpc_vld <= 1'b0;
cbus_pipe0_efpc[38:0] <= 39'b0;
cbus_pipe0_vstart_vld <= 1'b0;
cbus_pipe0_vstart[6:0] <= 7'b0;
end
else if(cbus_pipe0_cmplt) begin
cbus_pipe0_expt_vld <= cbus_pipe0_src_expt_vld;
cbus_pipe0_expt_vec[4:0] <= cbus_pipe0_src_expt_vec[4:0];
cbus_pipe0_high_hw_expt <= cbus_pipe0_src_high_hw_expt;
cbus_pipe0_bkpt <= cbus_pipe0_src_bkpt;
cbus_pipe0_vsetvl <= cbus_pipe0_src_vsetvl;
cbus_pipe0_immu_expt <= cbus_pipe0_src_immu_expt;
cbus_pipe0_mtval[31:0] <= cbus_pipe0_src_mtval[31:0];
cbus_pipe0_flush <= cbus_pipe0_src_flush;
cbus_pipe0_efpc_vld <= cbus_pipe0_src_efpc_vld;
cbus_pipe0_efpc[38:0] <= cbus_pipe0_src_efpc[38:0];
cbus_pipe0_vstart_vld <= cbus_pipe0_src_vstart_vld;
cbus_pipe0_vstart[6:0] <= cbus_pipe0_src_vstart[6:0];
end
else begin
cbus_pipe0_expt_vld <= cbus_pipe0_expt_vld;
cbus_pipe0_expt_vec[4:0] <= cbus_pipe0_expt_vec[4:0];
cbus_pipe0_high_hw_expt <= cbus_pipe0_high_hw_expt;
cbus_pipe0_bkpt <= cbus_pipe0_bkpt;
cbus_pipe0_vsetvl <= cbus_pipe0_vsetvl;
cbus_pipe0_immu_expt <= cbus_pipe0_immu_expt;
cbus_pipe0_mtval[31:0] <= cbus_pipe0_mtval[31:0];
cbus_pipe0_flush <= cbus_pipe0_flush;
cbus_pipe0_efpc_vld <= cbus_pipe0_efpc_vld;
cbus_pipe0_efpc[38:0] <= cbus_pipe0_efpc[38:0];
cbus_pipe0_vstart_vld <= cbus_pipe0_vstart_vld;
cbus_pipe0_vstart[6:0] <= cbus_pipe0_vstart[6:0];
end
end
//output to RTU
assign iu_rtu_pipe0_iid[6:0] = cbus_pipe0_iid[6:0];
assign iu_rtu_pipe0_abnormal = cbus_pipe0_abnormal;
assign iu_rtu_pipe0_expt_vld = cbus_pipe0_expt_vld;
assign iu_rtu_pipe0_expt_vec[4:0] = cbus_pipe0_expt_vec[4:0];
assign iu_rtu_pipe0_high_hw_expt = cbus_pipe0_high_hw_expt;
assign iu_rtu_pipe0_bkpt = cbus_pipe0_bkpt;
assign iu_rtu_pipe0_vsetvl = cbus_pipe0_vsetvl;
assign iu_rtu_pipe0_immu_expt = cbus_pipe0_immu_expt;
assign iu_rtu_pipe0_mtval[31:0] = cbus_pipe0_mtval[31:0];
assign iu_rtu_pipe0_flush = cbus_pipe0_flush;
assign iu_rtu_pipe0_efpc_vld = cbus_pipe0_efpc_vld;
assign iu_rtu_pipe0_efpc[38:0] = cbus_pipe0_efpc[38:0];
assign iu_rtu_pipe0_vstart_vld = cbus_pipe0_vstart_vld;
assign iu_rtu_pipe0_vstart[6:0] = cbus_pipe0_vstart[6:0];
//==========================================================
// Pipe1 Complete Signals
//==========================================================
//----------------------------------------------------------
// Complete Source Control Signal
//----------------------------------------------------------
assign cbus_pipe1_cmplt = idu_iu_rf_pipe1_sel
|| idu_iu_rf_mult_sel;
assign cbus_pipe1_gateclk_cmplt = idu_iu_rf_pipe1_cbus_gateclk_sel;
//----------------------------------------------------------
// Complete Instruction Valid
//----------------------------------------------------------
always @(posedge inst_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe1_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
cbus_pipe1_inst_vld <= 1'b0;
else
cbus_pipe1_inst_vld <= cbus_pipe1_cmplt;
end
//output to RTU
assign iu_rtu_pipe1_cmplt = cbus_pipe1_inst_vld;
//----------------------------------------------------------
// Complete Data Selection
//----------------------------------------------------------
assign cbus_pipe1_src_iid[6:0] = idu_iu_rf_pipe1_iid[6:0];
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign pipe1_data_clk_en = cbus_pipe1_gateclk_cmplt;
// &Instance("gated_clk_cell", "x_pipe1_data_gated_clk"); @272
gated_clk_cell x_pipe1_data_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (pipe1_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (pipe1_data_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @273
// .external_en (1'b0), @274
// .global_en (cp0_yy_clk_en), @275
// .module_en (cp0_iu_icg_en), @276
// .local_en (pipe1_data_clk_en), @277
// .clk_out (pipe1_data_clk)); @278
//----------------------------------------------------------
// Complete Data
//----------------------------------------------------------
always @(posedge pipe1_data_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cbus_pipe1_iid[6:0] <= 7'b0;
else if(cbus_pipe1_cmplt)
cbus_pipe1_iid[6:0] <= cbus_pipe1_src_iid[6:0];
else
cbus_pipe1_iid[6:0] <= cbus_pipe1_iid[6:0];
end
//output to RTU
assign iu_rtu_pipe1_iid[6:0] = cbus_pipe1_iid[6:0];
//==========================================================
// Pipe2 Complete Signals
//==========================================================
//----------------------------------------------------------
// Complete Signals
//----------------------------------------------------------
//pipe2 complete signals are flopped by BJU, only rename in cbus
assign iu_rtu_pipe2_cmplt = bju_cbus_ex2_pipe2_sel;
assign iu_rtu_pipe2_iid[6:0] = bju_cbus_ex2_pipe2_iid[6:0];
assign iu_rtu_pipe2_abnormal = bju_cbus_ex2_pipe2_abnormal;
assign iu_rtu_pipe2_jmp_mispred = bju_cbus_ex2_pipe2_jmp_mispred;
assign iu_rtu_pipe2_bht_mispred = bju_cbus_ex2_pipe2_bht_mispred;
// &ModuleEnd; @309
endmodule |
module ct_iu_bju_pcfifo_entry(
bju_pcfifo_ex2_bht_mispred,
bju_pcfifo_ex2_condbr,
bju_pcfifo_ex2_jmp,
bju_pcfifo_ex2_length,
bju_pcfifo_ex2_pc,
bju_pcfifo_ex2_pcall,
bju_pcfifo_ex2_pret,
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
iu_yy_xx_cancel,
pad_yy_icg_scan_en,
pcfifo_create0_data,
pcfifo_create1_data,
pcfifo_create2_data,
rtu_iu_flush_fe,
rtu_yy_xx_flush,
x_cmplt_en,
x_create_en,
x_flush,
x_pop_en,
x_pop_gateclk_en,
x_rf_read_data,
x_rt_read_data,
x_vld
);
// &Ports; @28
input bju_pcfifo_ex2_bht_mispred;
input bju_pcfifo_ex2_condbr;
input bju_pcfifo_ex2_jmp;
input bju_pcfifo_ex2_length;
input [39:0] bju_pcfifo_ex2_pc;
input bju_pcfifo_ex2_pcall;
input bju_pcfifo_ex2_pret;
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input iu_yy_xx_cancel;
input pad_yy_icg_scan_en;
input [66:0] pcfifo_create0_data;
input [66:0] pcfifo_create1_data;
input [66:0] pcfifo_create2_data;
input rtu_iu_flush_fe;
input rtu_yy_xx_flush;
input x_cmplt_en;
input [2 :0] x_create_en;
input x_pop_en;
input x_pop_gateclk_en;
output x_flush;
output [66:0] x_rf_read_data;
output [50:0] x_rt_read_data;
output x_vld;
// &Regs; @29
reg bht_mispred;
reg bht_pred;
reg bju;
reg [24:0] chk_idx;
reg cmplt;
reg condbr;
reg flush;
reg jmp;
reg jmp_mispred;
reg length;
reg [39:0] pc;
reg pcall;
reg pret;
reg vld;
reg [66:0] x_create_data;
// &Wires; @30
wire bju_pcfifo_ex2_bht_mispred;
wire bju_pcfifo_ex2_condbr;
wire bju_pcfifo_ex2_jmp;
wire bju_pcfifo_ex2_length;
wire [39:0] bju_pcfifo_ex2_pc;
wire bju_pcfifo_ex2_pcall;
wire bju_pcfifo_ex2_pret;
wire cmplt_clk;
wire cmplt_clk_en;
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire create_clk;
wire create_clk_en;
wire create_en;
wire entry_clk;
wire entry_clk_en;
wire forever_cpuclk;
wire iu_yy_xx_cancel;
wire pad_yy_icg_scan_en;
wire [66:0] pcfifo_create0_data;
wire [66:0] pcfifo_create1_data;
wire [66:0] pcfifo_create2_data;
wire rtu_iu_flush_fe;
wire rtu_yy_xx_flush;
wire x_cmplt_bht_mispred;
wire x_cmplt_condbr;
wire x_cmplt_en;
wire x_cmplt_jmp;
wire x_cmplt_length;
wire [39:0] x_cmplt_pc;
wire x_cmplt_pcall;
wire x_cmplt_pret;
wire x_create_bht_pred;
wire [24:0] x_create_chk_idx;
wire [2 :0] x_create_en;
wire x_create_jmp_mispred;
wire [39:0] x_create_pc;
wire x_flush;
wire x_pop_en;
wire x_pop_gateclk_en;
wire x_read_bht_mispred;
wire x_read_bht_pred;
wire x_read_bju;
wire [24:0] x_read_chk_idx;
wire x_read_cmplt;
wire x_read_condbr;
wire x_read_flush;
wire x_read_jmp;
wire x_read_jmp_mispred;
wire x_read_length;
wire [39:0] x_read_pc;
wire x_read_pcall;
wire x_read_pret;
wire x_read_vld;
wire [66:0] x_rf_read_data;
wire [50:0] x_rt_read_data;
wire x_vld;
parameter CREATE_WIDTH = 67;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = create_en
|| rtu_yy_xx_flush
|| iu_yy_xx_cancel
|| rtu_iu_flush_fe
|| x_pop_gateclk_en
|| x_cmplt_en;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @44
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @45
// .external_en (1'b0), @46
// .global_en (cp0_yy_clk_en), @47
// .module_en (cp0_iu_icg_en), @48
// .local_en (entry_clk_en), @49
// .clk_out (entry_clk)); @50
assign create_clk_en = create_en;
// &Instance("gated_clk_cell", "x_create_gated_clk"); @53
gated_clk_cell x_create_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (create_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (create_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @54
// .external_en (1'b0), @55
// .global_en (cp0_yy_clk_en), @56
// .module_en (cp0_iu_icg_en), @57
// .local_en (create_clk_en), @58
// .clk_out (create_clk)); @59
assign cmplt_clk_en = create_en || x_cmplt_en;
// &Instance("gated_clk_cell", "x_cmplt_gated_clk"); @62
gated_clk_cell x_cmplt_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (cmplt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (cmplt_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @63
// .external_en (1'b0), @64
// .global_en (cp0_yy_clk_en), @65
// .module_en (cp0_iu_icg_en), @66
// .local_en (cmplt_clk_en), @67
// .clk_out (cmplt_clk)); @68
//==========================================================
// Create Ports
//==========================================================
assign create_en = |x_create_en[2:0];
// &CombBeg; @75
always @( pcfifo_create1_data[66:0]
or pcfifo_create0_data[66:0]
or x_create_en[2:0]
or pcfifo_create2_data[66:0])
begin
case (x_create_en[2:0])
3'b001 : x_create_data[CREATE_WIDTH-1:0] = pcfifo_create0_data[CREATE_WIDTH-1:0];
3'b010 : x_create_data[CREATE_WIDTH-1:0] = pcfifo_create1_data[CREATE_WIDTH-1:0];
3'b100 : x_create_data[CREATE_WIDTH-1:0] = pcfifo_create2_data[CREATE_WIDTH-1:0];
default: x_create_data[CREATE_WIDTH-1:0] = {CREATE_WIDTH{1'bx}};
endcase
// &CombEnd; @82
end
//==========================================================
// Create and Read Bus
//==========================================================
assign x_create_chk_idx[24:0] = x_create_data[66:42];
assign x_create_jmp_mispred = x_create_data[41];
assign x_create_bht_pred = x_create_data[40];
assign x_create_pc[39:0] = x_create_data[39:0];
assign x_cmplt_length = bju_pcfifo_ex2_length;
assign x_cmplt_bht_mispred = bju_pcfifo_ex2_bht_mispred;
assign x_cmplt_jmp = bju_pcfifo_ex2_jmp;
assign x_cmplt_pret = bju_pcfifo_ex2_pret;
assign x_cmplt_pcall = bju_pcfifo_ex2_pcall;
assign x_cmplt_condbr = bju_pcfifo_ex2_condbr;
assign x_cmplt_pc[39:0] = bju_pcfifo_ex2_pc[39:0];
assign x_rf_read_data[66:42] = x_read_chk_idx[24:0];
assign x_rf_read_data[41] = x_read_jmp_mispred;
assign x_rf_read_data[40] = x_read_bht_pred;
assign x_rf_read_data[39:0] = x_read_pc[39:0];
assign x_rt_read_data[50] = x_read_cmplt;
assign x_rt_read_data[49] = x_read_flush;
assign x_rt_read_data[48] = x_read_vld;
assign x_rt_read_data[47] = x_read_length;
assign x_rt_read_data[46] = x_read_bht_pred;
assign x_rt_read_data[45] = x_read_bju;
assign x_rt_read_data[44] = x_read_bht_mispred;
assign x_rt_read_data[43] = x_read_jmp;
assign x_rt_read_data[42] = x_read_pret;
assign x_rt_read_data[41] = x_read_pcall;
assign x_rt_read_data[40] = x_read_condbr;
assign x_rt_read_data[39:0] = x_read_pc[39:0];
//==========================================================
// Entry Valid
//==========================================================
assign x_vld = vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vld <= 1'b0;
else if(vld && rtu_yy_xx_flush && (flush || iu_yy_xx_cancel || rtu_iu_flush_fe))
vld <= 1'b0;
else if(create_en)
vld <= 1'b1;
else if(x_pop_en)
vld <= 1'b0;
else
vld <= vld;
end
assign x_read_vld = vld;
//==========================================================
// Entry Cmplt
//==========================================================
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cmplt <= 1'b0;
else if(vld && rtu_yy_xx_flush && (flush || iu_yy_xx_cancel || rtu_iu_flush_fe))
cmplt <= 1'b0;
else if(create_en)
cmplt <= 1'b0;
else if(x_cmplt_en)
cmplt <= 1'b1;
else if(x_pop_en)
cmplt <= 1'b0;
else
cmplt <= cmplt;
end
assign x_read_cmplt = cmplt;
//==========================================================
// Flush
//==========================================================
assign x_flush = flush;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
flush <= 1'b0;
else if(vld && (iu_yy_xx_cancel || rtu_iu_flush_fe) && !rtu_yy_xx_flush)
flush <= 1'b1;
else if(create_en)
flush <= 1'b0;
else
flush <= flush;
end
assign x_read_flush = flush;
//==========================================================
// Information
//==========================================================
always @(posedge create_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
chk_idx[24:0] <= 25'b0;
bht_pred <= 1'b0;
jmp_mispred <= 1'b0;
end
else if(create_en) begin
chk_idx[24:0] <= x_create_chk_idx[24:0];
bht_pred <= x_create_bht_pred;
jmp_mispred <= x_create_jmp_mispred;
end
else begin
chk_idx[24:0] <= chk_idx[24:0];
bht_pred <= bht_pred;
jmp_mispred <= jmp_mispred;
end
end
assign x_read_chk_idx[24:0] = chk_idx[24:0];
assign x_read_bht_pred = bht_pred;
assign x_read_jmp_mispred = jmp_mispred;
always @(posedge cmplt_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
pc[39:0] <= 40'b0;
bju <= 1'b0;
condbr <= 1'b0;
pcall <= 1'b0;
pret <= 1'b0;
jmp <= 1'b0;
bht_mispred <= 1'b0;
length <= 1'b0;
end
else if(create_en) begin
pc[39:0] <= x_create_pc[39:0];
bju <= 1'b0;
condbr <= 1'b0;
pcall <= 1'b0;
pret <= 1'b0;
jmp <= 1'b0;
bht_mispred <= 1'b0;
length <= 1'b0;
end
else if(x_cmplt_en) begin
pc[39:0] <= x_cmplt_pc[39:0];
bju <= 1'b1;
condbr <= x_cmplt_condbr;
pcall <= x_cmplt_pcall;
pret <= x_cmplt_pret;
jmp <= x_cmplt_jmp;
bht_mispred <= x_cmplt_bht_mispred;
length <= x_cmplt_length;
end
else begin
pc[39:0] <= pc[39:0];
bju <= bju;
condbr <= condbr;
pcall <= pcall;
pret <= pret;
jmp <= jmp;
bht_mispred <= bht_mispred;
length <= length;
end
end
assign x_read_pc[39:0] = pc[39:0];
assign x_read_bju = bju;
assign x_read_condbr = condbr;
assign x_read_pcall = pcall;
assign x_read_pret = pret;
assign x_read_jmp = jmp;
assign x_read_bht_mispred = bht_mispred;
assign x_read_length = length;
// &ModuleEnd; @256
endmodule |
module ct_iu_special(
bju_special_pc,
cp0_iu_icg_en,
cp0_iu_vill,
cp0_iu_vl,
cp0_iu_vsetvli_pre_decd_disable,
cp0_iu_vstart,
cp0_yy_clk_en,
cp0_yy_priv_mode,
cpurst_b,
forever_cpuclk,
idu_iu_rf_pipe0_dst_preg,
idu_iu_rf_pipe0_expt_vec,
idu_iu_rf_pipe0_expt_vld,
idu_iu_rf_pipe0_func,
idu_iu_rf_pipe0_high_hw_expt,
idu_iu_rf_pipe0_iid,
idu_iu_rf_pipe0_opcode,
idu_iu_rf_pipe0_special_imm,
idu_iu_rf_pipe0_src0,
idu_iu_rf_pipe0_src1_no_imm,
idu_iu_rf_pipe0_vl,
idu_iu_rf_special_gateclk_sel,
idu_iu_rf_special_sel,
mmu_xx_mmu_en,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
special_cbus_ex1_abnormal,
special_cbus_ex1_bkpt,
special_cbus_ex1_expt_vec,
special_cbus_ex1_expt_vld,
special_cbus_ex1_flush,
special_cbus_ex1_high_hw_expt,
special_cbus_ex1_iid,
special_cbus_ex1_immu_expt,
special_cbus_ex1_inst_gateclk_vld,
special_cbus_ex1_inst_vld,
special_cbus_ex1_mtval,
special_cbus_ex1_vsetvl,
special_cbus_ex1_vstart,
special_cbus_ex1_vstart_vld,
special_rbus_ex1_data,
special_rbus_ex1_data_vld,
special_rbus_ex1_preg
);
// &Ports; @29
input [39:0] bju_special_pc;
input cp0_iu_icg_en;
input cp0_iu_vill;
input [7 :0] cp0_iu_vl;
input cp0_iu_vsetvli_pre_decd_disable;
input [6 :0] cp0_iu_vstart;
input cp0_yy_clk_en;
input [1 :0] cp0_yy_priv_mode;
input cpurst_b;
input forever_cpuclk;
input [6 :0] idu_iu_rf_pipe0_dst_preg;
input [4 :0] idu_iu_rf_pipe0_expt_vec;
input idu_iu_rf_pipe0_expt_vld;
input [4 :0] idu_iu_rf_pipe0_func;
input idu_iu_rf_pipe0_high_hw_expt;
input [6 :0] idu_iu_rf_pipe0_iid;
input [31:0] idu_iu_rf_pipe0_opcode;
input [19:0] idu_iu_rf_pipe0_special_imm;
input [63:0] idu_iu_rf_pipe0_src0;
input [63:0] idu_iu_rf_pipe0_src1_no_imm;
input [7 :0] idu_iu_rf_pipe0_vl;
input idu_iu_rf_special_gateclk_sel;
input idu_iu_rf_special_sel;
input mmu_xx_mmu_en;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
output special_cbus_ex1_abnormal;
output special_cbus_ex1_bkpt;
output [4 :0] special_cbus_ex1_expt_vec;
output special_cbus_ex1_expt_vld;
output special_cbus_ex1_flush;
output special_cbus_ex1_high_hw_expt;
output [6 :0] special_cbus_ex1_iid;
output special_cbus_ex1_immu_expt;
output special_cbus_ex1_inst_gateclk_vld;
output special_cbus_ex1_inst_vld;
output [31:0] special_cbus_ex1_mtval;
output special_cbus_ex1_vsetvl;
output [6 :0] special_cbus_ex1_vstart;
output special_cbus_ex1_vstart_vld;
output [63:0] special_rbus_ex1_data;
output special_rbus_ex1_data_vld;
output [6 :0] special_rbus_ex1_preg;
// &Regs; @30
reg [31:0] special_cbus_ex1_mtval;
reg [6 :0] special_ex1_dst_preg;
reg [4 :0] special_ex1_ecall_expt_vec;
reg [4 :0] special_ex1_expt_vec;
reg special_ex1_expt_vld;
reg [4 :0] special_ex1_func;
reg special_ex1_high_hw_expt;
reg [6 :0] special_ex1_iid;
reg [19:0] special_ex1_imm;
reg special_ex1_inst_vld;
reg [31:0] special_ex1_opcode;
reg [39:0] special_ex1_pc;
reg [7 :0] special_ex1_pred_vl;
reg [63:0] special_ex1_src0;
reg [63:0] special_ex1_src1;
reg [7 :0] special_ex1_vsetvl_src_vl;
reg [7 :0] special_ex1_vsetvl_vl;
reg special_ex1_vsetvl_vl_mispred;
reg [1 :0] special_ex1_vsetvl_vlmul;
reg [2 :0] special_ex1_vsetvl_vsew;
// &Wires; @31
wire [39:0] bju_special_pc;
wire cp0_iu_icg_en;
wire cp0_iu_vill;
wire [7 :0] cp0_iu_vl;
wire cp0_iu_vsetvli_pre_decd_disable;
wire [6 :0] cp0_iu_vstart;
wire cp0_yy_clk_en;
wire [1 :0] cp0_yy_priv_mode;
wire cpurst_b;
wire ex1_ctrl_clk;
wire ex1_ctrl_clk_en;
wire ex1_inst_clk;
wire ex1_inst_clk_en;
wire forever_cpuclk;
wire [6 :0] idu_iu_rf_pipe0_dst_preg;
wire [4 :0] idu_iu_rf_pipe0_expt_vec;
wire idu_iu_rf_pipe0_expt_vld;
wire [4 :0] idu_iu_rf_pipe0_func;
wire idu_iu_rf_pipe0_high_hw_expt;
wire [6 :0] idu_iu_rf_pipe0_iid;
wire [31:0] idu_iu_rf_pipe0_opcode;
wire [19:0] idu_iu_rf_pipe0_special_imm;
wire [63:0] idu_iu_rf_pipe0_src0;
wire [63:0] idu_iu_rf_pipe0_src1_no_imm;
wire [7 :0] idu_iu_rf_pipe0_vl;
wire idu_iu_rf_special_gateclk_sel;
wire idu_iu_rf_special_sel;
wire mmu_xx_mmu_en;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
wire [63:0] special_auipc_rslt;
wire special_cbus_ex1_abnormal;
wire special_cbus_ex1_bkpt;
wire [4 :0] special_cbus_ex1_expt_vec;
wire special_cbus_ex1_expt_vld;
wire special_cbus_ex1_flush;
wire special_cbus_ex1_high_hw_expt;
wire [6 :0] special_cbus_ex1_iid;
wire special_cbus_ex1_immu_expt;
wire special_cbus_ex1_inst_gateclk_vld;
wire special_cbus_ex1_inst_vld;
wire special_cbus_ex1_vsetvl;
wire [6 :0] special_cbus_ex1_vstart;
wire special_cbus_ex1_vstart_vld;
wire special_ex1_illegal_expt;
wire special_ex1_inst_auipc;
wire special_ex1_inst_ebreak;
wire special_ex1_inst_ecall;
wire special_ex1_inst_nop;
wire special_ex1_inst_pseudo_auipc;
wire special_ex1_inst_vsetvl;
wire special_ex1_inst_vsetvli;
wire [63:0] special_ex1_offset;
wire [63:0] special_ex1_pc_addend;
wire special_ex1_vsetvl_avl_ge_128;
wire special_ex1_vsetvl_avl_ge_16;
wire special_ex1_vsetvl_avl_ge_2;
wire special_ex1_vsetvl_avl_ge_32;
wire special_ex1_vsetvl_avl_ge_4;
wire special_ex1_vsetvl_avl_ge_64;
wire special_ex1_vsetvl_avl_ge_8;
wire special_ex1_vsetvl_illegal;
wire [31:0] special_ex1_vsetvl_mtval;
wire special_ex1_vsetvl_rs1_x0;
wire [63:0] special_ex1_vsetvl_rslt;
wire [63:0] special_ex1_vsetvl_src_avl;
wire [1 :0] special_ex1_vsetvl_src_vediv;
wire [1 :0] special_ex1_vsetvl_src_vlmul;
wire [2 :0] special_ex1_vsetvl_src_vsew;
wire [7 :0] special_ex1_vsetvl_vl_128;
wire [7 :0] special_ex1_vsetvl_vl_16;
wire [7 :0] special_ex1_vsetvl_vl_2;
wire [7 :0] special_ex1_vsetvl_vl_32;
wire [7 :0] special_ex1_vsetvl_vl_4;
wire [7 :0] special_ex1_vsetvl_vl_64;
wire [7 :0] special_ex1_vsetvl_vl_8;
wire special_ex1_vsetvl_vl_mispred_128;
wire special_ex1_vsetvl_vl_mispred_16;
wire special_ex1_vsetvl_vl_mispred_2;
wire special_ex1_vsetvl_vl_mispred_32;
wire special_ex1_vsetvl_vl_mispred_4;
wire special_ex1_vsetvl_vl_mispred_64;
wire special_ex1_vsetvl_vl_mispred_8;
wire special_ex1_vsetvl_vl_modified_from_0;
wire special_ex1_vsetvlx_abnormal;
wire special_ex1_vstart_clr;
wire [63:0] special_rbus_ex1_data;
wire special_rbus_ex1_data_vld;
wire [6 :0] special_rbus_ex1_preg;
//==========================================================
// Parameters
//==========================================================
parameter SPECIAL_NOP = 5'b00000;
parameter SPECIAL_ECALL = 5'b00010;
parameter SPECIAL_EBREAK = 5'b00011;
parameter SPECIAL_AUIPC = 5'b00100;
parameter SPECIAL_PSEUDO_AUIPC = 5'b00101;
parameter SPECIAL_VSETVLI = 5'b00110;
parameter SPECIAL_VSETVL = 5'b00111;
//==========================================================
// RF/EX1 Pipeline Register
//==========================================================
//----------------------------------------------------------
// Instance of Gated Cell
//----------------------------------------------------------
assign ex1_ctrl_clk_en = idu_iu_rf_special_gateclk_sel || special_ex1_inst_vld;
// &Instance("gated_clk_cell", "x_ex1_ctrl_gated_clk"); @52
gated_clk_cell x_ex1_ctrl_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_ctrl_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_ctrl_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @53
// .external_en (1'b0), @54
// .global_en (cp0_yy_clk_en), @55
// .module_en (cp0_iu_icg_en), @56
// .local_en (ex1_ctrl_clk_en), @57
// .clk_out (ex1_ctrl_clk)); @58
assign ex1_inst_clk_en = idu_iu_rf_special_gateclk_sel;
// &Instance("gated_clk_cell", "x_ex1_inst_gated_clk"); @61
gated_clk_cell x_ex1_inst_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_inst_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_inst_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @62
// .external_en (1'b0), @63
// .global_en (cp0_yy_clk_en), @64
// .module_en (cp0_iu_icg_en), @65
// .local_en (ex1_inst_clk_en), @66
// .clk_out (ex1_inst_clk)); @67
//----------------------------------------------------------
// Pipe2 EX1 Instruction valid
//----------------------------------------------------------
always @(posedge ex1_ctrl_clk or negedge cpurst_b)
begin
if(!cpurst_b)
special_ex1_inst_vld <= 1'b0;
else if(rtu_yy_xx_flush)
special_ex1_inst_vld <= 1'b0;
else
special_ex1_inst_vld <= idu_iu_rf_special_sel;
end
//----------------------------------------------------------
// Pipe2 EX1 Instruction Data
//----------------------------------------------------------
always @(posedge ex1_inst_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
special_ex1_iid[6:0] <= 7'b0;
special_ex1_opcode[31:0] <= 32'b0;
special_ex1_dst_preg[6:0] <= 7'b0;
special_ex1_func[4:0] <= 5'b0;
special_ex1_pc[39:0] <= 40'b0;
special_ex1_imm[19:0] <= 20'b0;
special_ex1_expt_vld <= 1'b0;
special_ex1_expt_vec[4:0] <= 5'b0;
special_ex1_high_hw_expt <= 1'b0;
special_ex1_src0[63:0] <= 64'b0;
special_ex1_src1[63:0] <= 64'b0;
special_ex1_pred_vl[7:0] <= 8'b0;
end
else if(idu_iu_rf_special_gateclk_sel) begin
special_ex1_iid[6:0] <= idu_iu_rf_pipe0_iid[6:0];
special_ex1_opcode[31:0] <= idu_iu_rf_pipe0_opcode[31:0];
special_ex1_dst_preg[6:0] <= idu_iu_rf_pipe0_dst_preg[6:0];
special_ex1_func[4:0] <= idu_iu_rf_pipe0_func[4:0];
special_ex1_pc[39:0] <= bju_special_pc[39:0];
special_ex1_imm[19:0] <= idu_iu_rf_pipe0_special_imm[19:0];
special_ex1_expt_vld <= idu_iu_rf_pipe0_expt_vld;
special_ex1_expt_vec[4:0] <= idu_iu_rf_pipe0_expt_vec[4:0];
special_ex1_high_hw_expt <= idu_iu_rf_pipe0_high_hw_expt;
special_ex1_src0[63:0] <= idu_iu_rf_pipe0_src0[63:0];
special_ex1_src1[63:0] <= idu_iu_rf_pipe0_src1_no_imm[63:0];
special_ex1_pred_vl[7:0] <= idu_iu_rf_pipe0_vl[7:0];
end
else begin
special_ex1_iid[6:0] <= special_ex1_iid[6:0];
special_ex1_opcode[31:0] <= special_ex1_opcode[31:0];
special_ex1_dst_preg[6:0] <= special_ex1_dst_preg[6:0];
special_ex1_func[4:0] <= special_ex1_func[4:0];
special_ex1_pc[39:0] <= special_ex1_pc[39:0];
special_ex1_imm[19:0] <= special_ex1_imm[19:0];
special_ex1_expt_vld <= special_ex1_expt_vld;
special_ex1_expt_vec[4:0] <= special_ex1_expt_vec[4:0];
special_ex1_high_hw_expt <= special_ex1_high_hw_expt;
special_ex1_src0[63:0] <= special_ex1_src0[63:0];
special_ex1_src1[63:0] <= special_ex1_src1[63:0];
special_ex1_pred_vl[7:0] <= special_ex1_pred_vl[7:0];
end
end
//==========================================================
// Instruction Selection
//==========================================================
assign special_ex1_inst_nop = (special_ex1_func[4:0] == SPECIAL_NOP);
assign special_ex1_inst_ecall = (special_ex1_func[4:0] == SPECIAL_ECALL);
assign special_ex1_inst_ebreak = (special_ex1_func[4:0] == SPECIAL_EBREAK);
assign special_ex1_inst_auipc = (special_ex1_func[4:0] == SPECIAL_AUIPC);
assign special_ex1_inst_pseudo_auipc = (special_ex1_func[4:0] == SPECIAL_PSEUDO_AUIPC);
assign special_ex1_inst_vsetvli = (special_ex1_func[4:0] == SPECIAL_VSETVLI);
assign special_ex1_inst_vsetvl = (special_ex1_func[4:0] == SPECIAL_VSETVL);
//==========================================================
// AUIPC result
//==========================================================
assign special_ex1_offset[63:0] =
special_ex1_inst_pseudo_auipc
? {{44{special_ex1_imm[19]}}, special_ex1_imm[19:0]}
: {{32{special_ex1_imm[19]}}, special_ex1_imm[19:0], 12'b0};
assign special_ex1_pc_addend[63:0] =
mmu_xx_mmu_en
? {{24{special_ex1_pc[39]}}, special_ex1_pc[39:0]}
: {24'b0, special_ex1_pc[39:0]};
assign special_auipc_rslt[63:0] = special_ex1_pc_addend[63:0]
+ special_ex1_offset[63:0];
//==========================================================
// VSETVL/VSETVLI
//==========================================================
//----------------------------------------------------------
// Prepare Source values
//----------------------------------------------------------
assign special_ex1_vsetvl_src_vlmul[1:0] = special_ex1_inst_vsetvli
? special_ex1_opcode[21:20]
: special_ex1_src1[1:0];
assign special_ex1_vsetvl_src_vsew[2:0] = special_ex1_inst_vsetvli
? special_ex1_opcode[24:22]
: special_ex1_src1[4:2];
assign special_ex1_vsetvl_src_vediv[1:0] = special_ex1_inst_vsetvli
? special_ex1_opcode[26:25]
: special_ex1_src1[6:5];
assign special_ex1_vsetvl_src_avl[63:0] = special_ex1_src0[63:0];
//----------------------------------------------------------
// VL values
//----------------------------------------------------------
assign special_ex1_vsetvl_rs1_x0 = (special_ex1_opcode[19:15] == 5'b0);
assign special_ex1_vsetvl_avl_ge_2 = (|special_ex1_vsetvl_src_avl[63:1])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_4 = (|special_ex1_vsetvl_src_avl[63:2])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_8 = (|special_ex1_vsetvl_src_avl[63:3])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_16 = (|special_ex1_vsetvl_src_avl[63:4])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_32 = (|special_ex1_vsetvl_src_avl[63:5])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_64 = (|special_ex1_vsetvl_src_avl[63:6])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_avl_ge_128 = (|special_ex1_vsetvl_src_avl[63:7])
|| special_ex1_vsetvl_rs1_x0;
assign special_ex1_vsetvl_vl_2[7:0] = {6'b0,special_ex1_vsetvl_avl_ge_2,
!special_ex1_vsetvl_avl_ge_2
& special_ex1_vsetvl_src_avl[0]};
assign special_ex1_vsetvl_vl_4[7:0] = {5'b0,special_ex1_vsetvl_avl_ge_4,
{2{!special_ex1_vsetvl_avl_ge_4}}
& special_ex1_vsetvl_src_avl[1:0]};
assign special_ex1_vsetvl_vl_8[7:0] = {4'b0,special_ex1_vsetvl_avl_ge_8,
{3{!special_ex1_vsetvl_avl_ge_8}}
& special_ex1_vsetvl_src_avl[2:0]};
assign special_ex1_vsetvl_vl_16[7:0] = {3'b0,special_ex1_vsetvl_avl_ge_16,
{4{!special_ex1_vsetvl_avl_ge_16}}
& special_ex1_vsetvl_src_avl[3:0]};
assign special_ex1_vsetvl_vl_32[7:0] = {2'b0,special_ex1_vsetvl_avl_ge_32,
{5{!special_ex1_vsetvl_avl_ge_32}}
& special_ex1_vsetvl_src_avl[4:0]};
assign special_ex1_vsetvl_vl_64[7:0] = {1'b0,special_ex1_vsetvl_avl_ge_64,
{6{!special_ex1_vsetvl_avl_ge_64}}
& special_ex1_vsetvl_src_avl[5:0]};
assign special_ex1_vsetvl_vl_128[7:0] = {special_ex1_vsetvl_avl_ge_128,
{7{!special_ex1_vsetvl_avl_ge_128}}
& special_ex1_vsetvl_src_avl[6:0]};
assign special_ex1_vsetvl_vl_mispred_2 = special_ex1_vsetvl_avl_ge_2
? (special_ex1_pred_vl[7:0] != 8'd2)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_4 = special_ex1_vsetvl_avl_ge_4
? (special_ex1_pred_vl[7:0] != 8'd4)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_8 = special_ex1_vsetvl_avl_ge_8
? (special_ex1_pred_vl[7:0] != 8'd8)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_16 = special_ex1_vsetvl_avl_ge_16
? (special_ex1_pred_vl[7:0] != 8'd16)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_32 = special_ex1_vsetvl_avl_ge_32
? (special_ex1_pred_vl[7:0] != 8'd32)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_64 = special_ex1_vsetvl_avl_ge_64
? (special_ex1_pred_vl[7:0] != 8'd64)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
assign special_ex1_vsetvl_vl_mispred_128 = special_ex1_vsetvl_avl_ge_128
? (special_ex1_pred_vl[7:0] != 8'd128)
: (special_ex1_pred_vl[7:0] != special_ex1_vsetvl_src_avl[7:0]);
// &CombBeg; @238
always @( special_ex1_vsetvl_vl_64[7:0]
or special_ex1_vsetvl_vl_128[7:0]
or special_ex1_vsetvl_vl_8[7:0]
or special_ex1_vsetvl_src_vsew[1:0]
or special_ex1_vsetvl_vl_32[7:0]
or special_ex1_vsetvl_vl_2[7:0]
or special_ex1_vsetvl_src_vlmul[1:0]
or special_ex1_vsetvl_vl_16[7:0]
or special_ex1_vsetvl_vl_4[7:0])
begin
case({special_ex1_vsetvl_src_vlmul[1:0],special_ex1_vsetvl_src_vsew[1:0]})
4'b0000: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_16[7:0];
4'b0001: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_8[7:0];
4'b0010: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_4[7:0];
4'b0011: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_2[7:0];
4'b0100: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_32[7:0];
4'b0101: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_16[7:0];
4'b0110: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_8[7:0];
4'b0111: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_4[7:0];
4'b1000: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_64[7:0];
4'b1001: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_32[7:0];
4'b1010: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_16[7:0];
4'b1011: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_8[7:0];
4'b1100: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_128[7:0];
4'b1101: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_64[7:0];
4'b1110: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_32[7:0];
4'b1111: special_ex1_vsetvl_src_vl[7:0] = special_ex1_vsetvl_vl_16[7:0];
default: special_ex1_vsetvl_src_vl[7:0] = {8{1'bx}};
endcase
// &CombEnd; @258
end
// &CombBeg; @260
always @( special_ex1_vsetvl_vl_mispred_32
or special_ex1_vsetvl_vl_mispred_8
or special_ex1_vsetvl_vl_mispred_64
or special_ex1_vsetvl_vl_mispred_2
or special_ex1_vsetvl_src_vsew[1:0]
or special_ex1_vsetvl_vl_mispred_16
or special_ex1_vsetvl_vl_mispred_4
or special_ex1_vsetvl_src_vlmul[1:0]
or special_ex1_vsetvl_vl_mispred_128)
begin
case({special_ex1_vsetvl_src_vlmul[1:0],special_ex1_vsetvl_src_vsew[1:0]})
4'b0000: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_16;
4'b0001: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_8;
4'b0010: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_4;
4'b0011: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_2;
4'b0100: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_32;
4'b0101: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_16;
4'b0110: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_8;
4'b0111: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_4;
4'b1000: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_64;
4'b1001: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_32;
4'b1010: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_16;
4'b1011: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_8;
4'b1100: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_128;
4'b1101: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_64;
4'b1110: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_32;
4'b1111: special_ex1_vsetvl_vl_mispred = special_ex1_vsetvl_vl_mispred_16;
default: special_ex1_vsetvl_vl_mispred = 1'bx;
endcase
// &CombEnd; @280
end
// &CombBeg; @282
always @( special_ex1_vsetvl_src_vsew[2:0]
or special_ex1_vsetvl_src_vlmul[1:0]
or special_ex1_vsetvl_illegal
or special_ex1_vsetvl_src_vl[7:0])
begin
if(special_ex1_vsetvl_illegal) begin
special_ex1_vsetvl_vl[7:0] = 8'b0;
special_ex1_vsetvl_vsew[2:0] = 3'b0;
special_ex1_vsetvl_vlmul[1:0] = 2'b0;
end
else begin
special_ex1_vsetvl_vl[7:0] = special_ex1_vsetvl_src_vl[7:0];
special_ex1_vsetvl_vsew[2:0] = special_ex1_vsetvl_src_vsew[2:0];
special_ex1_vsetvl_vlmul[1:0] = special_ex1_vsetvl_src_vlmul[1:0];
end
// &CombEnd; @293
end
assign special_ex1_vsetvl_vl_modified_from_0 = (special_ex1_vsetvl_vl[7:0] != 8'b0)
&& (cp0_iu_vl[7:0] == 8'b0);
//----------------------------------------------------------
// vstart values
//----------------------------------------------------------
assign special_ex1_vstart_clr = (special_ex1_inst_vsetvl || special_ex1_inst_vsetvli)
&& (cp0_iu_vstart[6:0] != 7'b0);
//----------------------------------------------------------
// cmplt value
//----------------------------------------------------------
assign special_ex1_vsetvl_illegal = (special_ex1_vsetvl_src_vediv[1:0] != 2'b0)
|| (special_ex1_vsetvl_src_vsew[2:0] == 3'b100)
|| (special_ex1_vsetvl_src_vsew[2:0] == 3'b101)
|| (special_ex1_vsetvl_src_vsew[2:0] == 3'b110)
|| (special_ex1_vsetvl_src_vsew[2:0] == 3'b111);
assign special_ex1_vsetvlx_abnormal = special_ex1_inst_vsetvl
|| special_ex1_inst_vsetvli
&& (special_ex1_vsetvl_illegal
|| special_ex1_vsetvl_vl_mispred
|| cp0_iu_vill
|| special_ex1_vsetvl_vl_modified_from_0
|| cp0_iu_vsetvli_pre_decd_disable);
assign special_ex1_vsetvl_mtval[31:16] = 16'b0;
assign special_ex1_vsetvl_mtval[15] = 1'b0; //fof_expt
assign special_ex1_vsetvl_mtval[14] = special_ex1_vsetvl_vl_mispred;
assign special_ex1_vsetvl_mtval[13] = special_ex1_vsetvl_illegal;
assign special_ex1_vsetvl_mtval[12:5] = special_ex1_vsetvl_vl[7:0];
assign special_ex1_vsetvl_mtval[4:2] = special_ex1_vsetvl_vsew[2:0];
assign special_ex1_vsetvl_mtval[1:0] = special_ex1_vsetvl_vlmul[1:0];
//----------------------------------------------------------
// write back value
//----------------------------------------------------------
assign special_ex1_vsetvl_rslt[63:8] = 56'b0;
assign special_ex1_vsetvl_rslt[7:0] = special_ex1_vsetvl_vl[7:0];
//==========================================================
// RF stage Complete Bus signals
//==========================================================
// &CombBeg; @338
always @( cp0_yy_priv_mode[1:0])
begin
case(cp0_yy_priv_mode[1:0])
2'b00 : special_ex1_ecall_expt_vec[4:0] = 5'd8;
2'b01 : special_ex1_ecall_expt_vec[4:0] = 5'd9;
2'b11 : special_ex1_ecall_expt_vec[4:0] = 5'd11;
default: special_ex1_ecall_expt_vec[4:0] = {5{1'bx}};
endcase
// &CombEnd; @345
end
assign special_cbus_ex1_inst_vld = special_ex1_inst_vld;
assign special_cbus_ex1_inst_gateclk_vld = special_ex1_inst_vld;
assign special_cbus_ex1_abnormal = special_ex1_inst_nop
&& special_ex1_expt_vld
|| special_ex1_inst_ecall
|| special_ex1_inst_ebreak
|| special_ex1_vsetvlx_abnormal
|| special_ex1_vstart_clr;
assign special_cbus_ex1_iid[6:0] = special_ex1_iid[6:0];
assign special_cbus_ex1_flush = special_ex1_vsetvlx_abnormal
|| special_ex1_vstart_clr;
assign special_cbus_ex1_bkpt = special_ex1_inst_ebreak;
assign special_cbus_ex1_vsetvl = special_ex1_vsetvlx_abnormal;
assign special_cbus_ex1_vstart_vld = special_ex1_vstart_clr;
assign special_cbus_ex1_vstart[6:0] = 7'b0;
//----------------------------------------------------------
// Exception
//----------------------------------------------------------
assign special_cbus_ex1_expt_vld = special_ex1_inst_ecall
|| special_ex1_inst_ebreak
|| special_ex1_inst_nop
&& special_ex1_expt_vld;
assign special_cbus_ex1_expt_vec[4:0] =
{5{special_ex1_inst_ecall}} & special_ex1_ecall_expt_vec[4:0]
| {5{special_ex1_inst_ebreak}} & 5'd3
| {5{special_ex1_inst_nop}} & special_ex1_expt_vec[4:0];
assign special_cbus_ex1_high_hw_expt = special_ex1_high_hw_expt;
assign special_ex1_illegal_expt = special_ex1_inst_nop
&& special_ex1_expt_vld
&& (special_ex1_expt_vec[4:0] == 5'd2);
assign special_cbus_ex1_immu_expt = special_ex1_inst_nop
&& special_ex1_expt_vld
&& ((special_ex1_expt_vec[4:0] == 5'd0)
|| (special_ex1_expt_vec[4:0] == 5'd1)
|| (special_ex1_expt_vec[4:0] == 5'd12));
// &CombBeg; @392
always @( special_ex1_illegal_expt
or special_ex1_vsetvl_mtval[31:0]
or special_ex1_inst_vsetvl
or special_ex1_opcode[31:0]
or special_ex1_inst_vsetvli)
begin
if(special_ex1_illegal_expt)
special_cbus_ex1_mtval[31:0] = special_ex1_opcode[31:0];
else if(special_ex1_inst_vsetvl || special_ex1_inst_vsetvli)
special_cbus_ex1_mtval[31:0] = special_ex1_vsetvl_mtval[31:0];
else
special_cbus_ex1_mtval[31:0] = 32'b0;
// &CombEnd; @399
end
//==========================================================
// Result Bus signals
//==========================================================
assign special_rbus_ex1_data_vld = special_ex1_inst_vld
&& (special_ex1_inst_auipc
|| special_ex1_inst_pseudo_auipc
|| special_ex1_inst_vsetvli
|| special_ex1_inst_vsetvl);
assign special_rbus_ex1_preg[6:0] = special_ex1_dst_preg[6:0];
assign special_rbus_ex1_data[63:0] = (special_ex1_inst_vsetvli || special_ex1_inst_vsetvl)
? special_ex1_vsetvl_rslt[63:0]
: special_auipc_rslt[63:0];
// &ModuleEnd; @414
endmodule |
module ct_iu_bju_pcfifo_read_entry(
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
iu_yy_xx_cancel,
pad_yy_icg_scan_en,
rtu_iu_flush_fe,
rtu_yy_xx_flush,
x_create_data,
x_create_en,
x_create_gateclk_en,
x_rt_read_data
);
// &Ports; @28
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input iu_yy_xx_cancel;
input pad_yy_icg_scan_en;
input rtu_iu_flush_fe;
input rtu_yy_xx_flush;
input [50:0] x_create_data;
input x_create_en;
input x_create_gateclk_en;
output [50:0] x_rt_read_data;
// &Regs; @29
reg bht_mispred;
reg bht_pred;
reg bju;
reg cmplt;
reg condbr;
reg flush;
reg jmp;
reg length;
reg [39:0] pc;
reg pcall;
reg pret;
reg vld;
// &Wires; @30
wire cmplt_clk;
wire cmplt_clk_en;
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_clk;
wire entry_clk_en;
wire flush_with_create;
wire forever_cpuclk;
wire iu_yy_xx_cancel;
wire pad_yy_icg_scan_en;
wire rtu_iu_flush_fe;
wire rtu_yy_xx_flush;
wire vld_with_create;
wire x_create_bht_mispred;
wire x_create_bht_pred;
wire x_create_bju;
wire x_create_cmplt;
wire x_create_condbr;
wire [50:0] x_create_data;
wire x_create_en;
wire x_create_flush;
wire x_create_gateclk_en;
wire x_create_jmp;
wire x_create_length;
wire [39:0] x_create_pc;
wire x_create_pcall;
wire x_create_pret;
wire x_create_vld;
wire x_read_bht_mispred;
wire x_read_bht_pred;
wire x_read_bju;
wire x_read_cmplt;
wire x_read_condbr;
wire x_read_flush;
wire x_read_jmp;
wire x_read_length;
wire [39:0] x_read_pc;
wire x_read_pcall;
wire x_read_pret;
wire x_read_vld;
wire [50:0] x_rt_read_data;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign entry_clk_en = x_create_gateclk_en
|| rtu_yy_xx_flush
|| iu_yy_xx_cancel
|| rtu_iu_flush_fe;
// &Instance("gated_clk_cell", "x_entry_gated_clk"); @40
gated_clk_cell x_entry_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (entry_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (entry_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @41
// .external_en (1'b0), @42
// .global_en (cp0_yy_clk_en), @43
// .module_en (cp0_iu_icg_en), @44
// .local_en (entry_clk_en), @45
// .clk_out (entry_clk)); @46
assign cmplt_clk_en = x_create_gateclk_en;
// &Instance("gated_clk_cell", "x_cmplt_gated_clk"); @49
gated_clk_cell x_cmplt_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (cmplt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (cmplt_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @50
// .external_en (1'b0), @51
// .global_en (cp0_yy_clk_en), @52
// .module_en (cp0_iu_icg_en), @53
// .local_en (cmplt_clk_en), @54
// .clk_out (cmplt_clk)); @55
//==========================================================
// Create and Read Bus
//==========================================================
assign x_create_cmplt = x_create_data[50];
assign x_create_flush = x_create_data[49];
assign x_create_vld = x_create_data[48];
assign x_create_length = x_create_data[47];
assign x_create_bht_pred = x_create_data[46];
assign x_create_bju = x_create_data[45];
assign x_create_bht_mispred = x_create_data[44];
assign x_create_jmp = x_create_data[43];
assign x_create_pret = x_create_data[42];
assign x_create_pcall = x_create_data[41];
assign x_create_condbr = x_create_data[40];
assign x_create_pc[39:0] = x_create_data[39:0];
//assign x_cmplt_length = bju_pcfifo_ex2_length;
//assign x_cmplt_bht_mispred = bju_pcfifo_ex2_bht_mispred;
//assign x_cmplt_jmp = bju_pcfifo_ex2_jmp;
//assign x_cmplt_pret = bju_pcfifo_ex2_pret;
//assign x_cmplt_pcall = bju_pcfifo_ex2_pcall;
//assign x_cmplt_condbr = bju_pcfifo_ex2_condbr;
//assign x_cmplt_pc[39:0] = bju_pcfifo_ex2_pc[39:0];
assign x_rt_read_data[50] = x_read_cmplt;
assign x_rt_read_data[49] = x_read_flush;
assign x_rt_read_data[48] = x_read_vld;
assign x_rt_read_data[47] = x_read_length;
assign x_rt_read_data[46] = x_read_bht_pred;
assign x_rt_read_data[45] = x_read_bju;
assign x_rt_read_data[44] = x_read_bht_mispred;
assign x_rt_read_data[43] = x_read_jmp;
assign x_rt_read_data[42] = x_read_pret;
assign x_rt_read_data[41] = x_read_pcall;
assign x_rt_read_data[40] = x_read_condbr;
assign x_rt_read_data[39:0] = x_read_pc[39:0];
//==========================================================
// Entry Valid
//==========================================================
assign vld_with_create = x_create_en ? x_create_vld : vld;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
vld <= 1'b0;
else if(vld_with_create && rtu_yy_xx_flush
&& (flush_with_create || iu_yy_xx_cancel || rtu_iu_flush_fe))
vld <= 1'b0;
else if(x_create_en)
vld <= x_create_vld;
else
vld <= vld;
end
assign x_read_vld = vld;
//==========================================================
// Entry Cmplt
//==========================================================
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
cmplt <= 1'b0;
else if(vld_with_create && rtu_yy_xx_flush
&& (flush_with_create || iu_yy_xx_cancel || rtu_iu_flush_fe))
cmplt <= 1'b0;
else if(x_create_en)
cmplt <= x_create_cmplt;
else
cmplt <= cmplt;
end
assign x_read_cmplt = cmplt;
//==========================================================
// Flush
//==========================================================
assign flush_with_create = x_create_en ? x_create_flush : flush;
always @(posedge entry_clk or negedge cpurst_b)
begin
if(!cpurst_b)
flush <= 1'b0;
else if(vld_with_create && (iu_yy_xx_cancel || rtu_iu_flush_fe)
&& !rtu_yy_xx_flush)
flush <= 1'b1;
else if(x_create_en)
flush <= x_create_flush;
else
flush <= flush;
end
assign x_read_flush = flush;
//==========================================================
// Information
//==========================================================
always @(posedge cmplt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
bht_pred <= 1'b0;
else if(x_create_en)
bht_pred <= x_create_bht_pred;
else
bht_pred <= bht_pred;
end
always @(posedge cmplt_clk or negedge cpurst_b)
begin
if(!cpurst_b) begin
pc[39:0] <= 40'b0;
bju <= 1'b0;
condbr <= 1'b0;
pcall <= 1'b0;
pret <= 1'b0;
jmp <= 1'b0;
bht_mispred <= 1'b0;
length <= 1'b0;
end
else if(x_create_en) begin
pc[39:0] <= x_create_pc[39:0];
bju <= x_create_bju;
condbr <= x_create_condbr;
pcall <= x_create_pcall;
pret <= x_create_pret;
jmp <= x_create_jmp;
bht_mispred <= x_create_bht_mispred;
length <= x_create_length;
end
else begin
pc[39:0] <= pc[39:0];
bju <= bju;
condbr <= condbr;
pcall <= pcall;
pret <= pret;
jmp <= jmp;
bht_mispred <= bht_mispred;
length <= length;
end
end
//rename for read output
assign x_read_pc[39:0] = pc[39:0];
assign x_read_bju = bju;
assign x_read_condbr = condbr;
assign x_read_pcall = pcall;
assign x_read_pret = pret;
assign x_read_jmp = jmp;
assign x_read_bht_mispred = bht_mispred;
assign x_read_bht_pred = bht_pred;
assign x_read_length = length;
// &ModuleEnd; @208
endmodule |
module ct_iu_div_entry(
cp0_iu_div_entry_disable_clr,
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
div_clk,
div_entry0_read_data,
div_entry0_read_vld,
div_entry1_read_data,
div_entry1_read_vld,
div_entry_write_data,
div_entry_write_en,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @26
input cp0_iu_div_entry_disable_clr;
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input div_clk;
input div_entry0_read_vld;
input div_entry1_read_vld;
input [257:0] div_entry_write_data;
input div_entry_write_en;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [257:0] div_entry0_read_data;
output [257:0] div_entry1_read_data;
// &Regs; @27
reg [257:0] div_entry0_data;
reg div_entry0_older;
reg [257:0] div_entry1_data;
// &Wires; @28
wire cp0_iu_div_entry_disable_clr;
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire div_clk;
wire div_entry0_clk;
wire div_entry0_clk_en;
wire [257:0] div_entry0_read_data;
wire div_entry0_read_vld;
wire div_entry1_clk;
wire div_entry1_clk_en;
wire [257:0] div_entry1_read_data;
wire div_entry1_read_vld;
wire [257:0] div_entry_write_data;
wire div_entry_write_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//==========================================================
// Instance of Gated Cell
//==========================================================
assign div_entry0_clk_en = div_entry_write_en && div_entry0_older
|| cp0_iu_div_entry_disable_clr;
// &Instance("gated_clk_cell", "x_div_entry0_gated_clk"); @36
gated_clk_cell x_div_entry0_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (div_entry0_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (div_entry0_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @37
// .external_en (1'b0), @38
// .global_en (cp0_yy_clk_en), @39
// .module_en (cp0_iu_icg_en), @40
// .local_en (div_entry0_clk_en), @41
// .clk_out (div_entry0_clk)); @42
assign div_entry1_clk_en = div_entry_write_en && !div_entry0_older
|| cp0_iu_div_entry_disable_clr;
// &Instance("gated_clk_cell", "x_div_entry1_gated_clk"); @46
gated_clk_cell x_div_entry1_gated_clk (
.clk_in (forever_cpuclk ),
.clk_out (div_entry1_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (div_entry1_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in (forever_cpuclk), @47
// .external_en (1'b0), @48
// .global_en (cp0_yy_clk_en), @49
// .module_en (cp0_iu_icg_en), @50
// .local_en (div_entry1_clk_en), @51
// .clk_out (div_entry1_clk)); @52
//==========================================================
// Write Select bit
//==========================================================
//indicate whether entry0 is older than entry1
always @(posedge div_clk or negedge cpurst_b)
begin
if(!cpurst_b)
div_entry0_older <= 1'b0;
else if(cp0_iu_div_entry_disable_clr)
div_entry0_older <= 1'b0;
else if(div_entry0_read_vld)
div_entry0_older <= 1'b0;
else if(div_entry1_read_vld)
div_entry0_older <= 1'b1;
else if(div_entry_write_en)
div_entry0_older <= !div_entry0_older;
else
div_entry0_older <= div_entry0_older;
end
//==========================================================
// Div Entry0
//==========================================================
always @(posedge div_entry0_clk or negedge cpurst_b)
begin
if(!cpurst_b)
//reset as unsign 64'bffffffffffffffff / 64'b1
div_entry0_data[257:0] <= {1'b0, 1'b0,
64'b0, 64'hffffffffffffffff,
64'b1, 64'hffffffffffffffff};
else if(cp0_iu_div_entry_disable_clr)
//reset as unsign 64'bffffffffffffffff / 64'b1
div_entry0_data[257:0] <= {1'b0, 1'b0,
64'b0, 64'hffffffffffffffff,
64'b1, 64'hffffffffffffffff};
else if(div_entry_write_en && div_entry0_older)
div_entry0_data[257:0] <= div_entry_write_data[257:0];
else
div_entry0_data[257:0] <= div_entry0_data[257:0];
end
assign div_entry0_read_data[257:0] = div_entry0_data[257:0];
//==========================================================
// Div Entry1
//==========================================================
always @(posedge div_entry1_clk or negedge cpurst_b)
begin
if(!cpurst_b)
//reset as sign 64'b7fffffffffffffff / 64'b1
div_entry1_data[257:0] <= {1'b0, 1'b1,
64'b0, 64'h7fffffffffffffff,
64'b1, 64'h7fffffffffffffff};
else if(cp0_iu_div_entry_disable_clr)
//reset as sign 64'b7fffffffffffffff / 64'b1
div_entry1_data[257:0] <= {1'b0, 1'b1,
64'b0, 64'h7fffffffffffffff,
64'b1, 64'h7fffffffffffffff};
else if(div_entry_write_en && !div_entry0_older)
div_entry1_data[257:0] <= div_entry_write_data[257:0];
else
div_entry1_data[257:0] <= div_entry1_data[257:0];
end
assign div_entry1_read_data[257:0] = div_entry1_data[257:0];
// &ModuleEnd; @121
endmodule |
module ct_iu_div_srt_radix16(
cp0_iu_icg_en,
cp0_yy_clk_en,
cpurst_b,
div_ex2_disp_0,
div_ex2_dvd_disp,
div_ex2_dvr_disp,
div_ex2_inst_vld,
div_exp_disp,
forever_cpuclk,
pad_yy_icg_scan_en,
rtu_yy_xx_flush,
srt_iter_finish,
x_srt_div_result,
x_srt_dvd,
x_srt_dvr,
x_srt_finish,
x_srt_on,
x_srt_rem_result,
x_srt_select_vld,
x_srt_shift_vld
);
// &Ports; @23
input cp0_iu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input div_ex2_disp_0;
input [5 :0] div_ex2_dvd_disp;
input [5 :0] div_ex2_dvr_disp;
input div_ex2_inst_vld;
input [6 :0] div_exp_disp;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input rtu_yy_xx_flush;
input [63:0] x_srt_dvd;
input [63:0] x_srt_dvr;
input x_srt_on;
input x_srt_select_vld;
input x_srt_shift_vld;
output srt_iter_finish;
output [63:0] x_srt_div_result;
output x_srt_finish;
output [63:0] x_srt_rem_result;
// &Regs; @24
reg [6 :0] srt_cnt;
reg [6 :0] srt_exp_disp;
reg [63:0] srt_pos_remainder;
// &Wires; @25
wire cp0_iu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire div_ex2_disp_0;
wire [5 :0] div_ex2_dvd_disp;
wire [5 :0] div_ex2_dvr_disp;
wire div_ex2_inst_vld;
wire [6 :0] div_exp_disp;
wire [63:0] ex2_dvd_saved;
wire [63:0] ex2_dvr_saved;
wire forever_cpuclk;
wire [65:0] initial_divisor_in;
wire [70:0] initial_remainder_in;
wire initial_srt_en;
wire [3 :0] last_sel_bit;
wire pad_yy_icg_scan_en;
wire rtu_yy_xx_flush;
wire srt_clk;
wire srt_clk_en;
wire [6 :0] srt_cnt_ini;
wire [6 :0] srt_cnt_ini_tmp;
wire srt_cnt_one;
wire srt_cnt_zero;
wire srt_div_clk;
wire srt_div_clk_en;
wire [65:0] srt_divisor_borrowed_val;
wire [65:0] srt_divisor_flop_borrow_in;
wire srt_divisor_flop_borrow_vld;
wire srt_finish;
wire srt_iter_finish;
wire [63:0] srt_pos_qt;
wire [63:0] srt_qt_flop_borrow_in_0;
wire [63:0] srt_qt_flop_borrow_in_1;
wire srt_qt_flop_borrow_vld;
wire [67:0] srt_qt_flop_borrowed_val_0;
wire [67:0] srt_qt_flop_borrowed_val_1;
wire [65:0] srt_remainder_borrowed_val;
wire [65:0] srt_remainder_flop_borrow_in;
wire srt_remainder_flop_borrow_vld;
wire [70:0] srt_remainder_neg;
wire [70:0] srt_remainder_out;
wire [70:0] srt_remainder_pos;
wire srt_remainder_zero;
wire srt_sm_on;
wire [67:0] total_qt_rt;
wire [67:0] total_qt_rt_minus;
wire [63:0] x_srt_div_result;
wire [63:0] x_srt_dvd;
wire [63:0] x_srt_dvr;
wire [5 :0] x_srt_dvr_disp;
wire [6 :0] x_srt_exp_disp;
wire x_srt_finish;
wire x_srt_inst_vld;
wire x_srt_on;
wire [63:0] x_srt_rem_result;
wire x_srt_select_vld;
wire x_srt_shift_vld;
//==========================================================
// SRT Remainder & Divisor for Quotient/Root Generate
//==========================================================
//===================Remainder Generate=====================
//gate clk
// &Instance("gated_clk_cell","x_srt_clk"); @32
gated_clk_cell x_srt_clk (
.clk_in (forever_cpuclk ),
.clk_out (srt_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (srt_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @33
// .clk_out (srt_clk),//Out Clock @34
// .external_en (1'b0), @35
// .global_en (cp0_yy_clk_en), @36
// .local_en (srt_clk_en),//Local Condition @37
// .module_en (cp0_iu_icg_en) @38
// ); @39
assign srt_clk_en = rtu_yy_xx_flush
|| x_srt_shift_vld
|| x_srt_inst_vld
|| x_srt_on
|| x_srt_select_vld;
assign srt_remainder_flop_borrow_vld = x_srt_shift_vld;
assign srt_remainder_flop_borrow_in[65:0] = {2'b0,x_srt_dvd[63:0]};
assign srt_divisor_flop_borrow_vld = x_srt_shift_vld;
assign srt_divisor_flop_borrow_in[65:0] = {2'b0,x_srt_dvr[63:0]};
assign srt_qt_flop_borrow_vld = x_srt_select_vld;
assign ex2_dvd_saved[63:0] = srt_remainder_borrowed_val[63:0];
assign ex2_dvr_saved[63:0] = srt_divisor_borrowed_val[63:0];
assign initial_srt_en = x_srt_inst_vld;
assign x_srt_inst_vld = div_ex2_inst_vld && !div_ex2_disp_0;
assign initial_remainder_in[70:0] = {7'b0,ex2_dvd_saved[63:0] << div_ex2_dvd_disp[5:0]};
assign initial_divisor_in[65:0] = {ex2_dvr_saved[63:0] << div_ex2_dvr_disp[5:0],2'b0};
assign x_srt_exp_disp[6:0] = div_exp_disp[6:0]; //used for calculate the iteration num
assign x_srt_dvr_disp[5:0] = div_ex2_dvr_disp[5:0];
// &Instance("ct_vfdsu_srt_radix16_only_div"); @62
ct_vfdsu_srt_radix16_only_div x_ct_vfdsu_srt_radix16_only_div (
.cpurst_b (cpurst_b ),
.initial_divisor_in (initial_divisor_in ),
.initial_remainder_in (initial_remainder_in ),
.initial_srt_en (initial_srt_en ),
.last_sel_bit (last_sel_bit ),
.qt_clk (srt_clk ),
.srt_div_clk (srt_div_clk ),
.srt_divisor_borrowed_val (srt_divisor_borrowed_val ),
.srt_divisor_flop_borrow_in (srt_divisor_flop_borrow_in ),
.srt_divisor_flop_borrow_vld (srt_divisor_flop_borrow_vld ),
.srt_qt_flop_borrow_in_0 (srt_qt_flop_borrow_in_0 ),
.srt_qt_flop_borrow_in_1 (srt_qt_flop_borrow_in_1 ),
.srt_qt_flop_borrow_vld (srt_qt_flop_borrow_vld ),
.srt_qt_flop_borrowed_val_0 (srt_qt_flop_borrowed_val_0 ),
.srt_qt_flop_borrowed_val_1 (srt_qt_flop_borrowed_val_1 ),
.srt_rem_clk (srt_clk ),
.srt_remainder_borrowed_val (srt_remainder_borrowed_val ),
.srt_remainder_flop_borrow_in (srt_remainder_flop_borrow_in ),
.srt_remainder_flop_borrow_vld (srt_remainder_flop_borrow_vld),
.srt_remainder_neg (srt_remainder_neg ),
.srt_remainder_out (srt_remainder_out ),
.srt_remainder_pos (srt_remainder_pos ),
.srt_remainder_zero (srt_remainder_zero ),
.srt_sm_on (srt_sm_on ),
.total_qt_rt (total_qt_rt ),
.total_qt_rt_minus (total_qt_rt_minus )
);
// &Connect(.srt_first_round(1'b0)); @63
// &Connect(.srt_rem_clk(srt_clk)); @64
// &Connect(.qt_clk(srt_clk)); @65
//=====================Gated Cell===========================
//gate clk
assign srt_div_clk_en = x_srt_shift_vld || x_srt_inst_vld || rtu_yy_xx_flush;
// &Instance("gated_clk_cell","x_srt_div_clk"); @70
gated_clk_cell x_srt_div_clk (
.clk_in (forever_cpuclk ),
.clk_out (srt_div_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (srt_div_clk_en ),
.module_en (cp0_iu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @71
// .clk_out (srt_div_clk),//Out Clock @72
// .external_en (1'b0), @73
// .global_en (cp0_yy_clk_en), @74
// .local_en (srt_div_clk_en),//Local Condition @75
// .module_en (cp0_iu_icg_en) @76
// ); @77
//=================Save exponent displacement===============
always @(posedge srt_div_clk or negedge cpurst_b)
begin
if(!cpurst_b)
srt_exp_disp[6:0] <= 7'b0;
else if(rtu_yy_xx_flush)
srt_exp_disp[6:0] <= 7'b0;
else if(x_srt_inst_vld)
srt_exp_disp[6:0] <= x_srt_exp_disp[6:0];
else
srt_exp_disp[6:0] <= srt_exp_disp[6:0];
end
//assign srt_exp_neg = srt_exp_disp[6];
//==========================================================
// srt counter and on
//==========================================================
always @(posedge srt_clk or negedge cpurst_b)
begin
if(!cpurst_b)
srt_cnt[6:0] <= 7'b0;
else if(x_srt_inst_vld)
srt_cnt[6:0] <= {1'b0,srt_cnt_ini[5:0]};
else if(srt_sm_on)
srt_cnt[6:0] <= srt_cnt[6:0] - 7'b1;
else
srt_cnt[6:0] <= srt_cnt[6:0];
end
//srt_cnt_ini[5:0]
//For Long, initial is 5'd32, calculate 33 round
//For Double, initial is 5'b11100('d28), calculate 29 round
//For Single, initial is 5'b01110('d14), calculate 15 round
assign srt_cnt_ini_tmp[6:0] = {x_srt_exp_disp[6:0]}+7'b10;
assign srt_cnt_ini[6:0] = {2'b0, srt_cnt_ini_tmp[6:2]}
+ {6'b0, |srt_cnt_ini_tmp[1:0]}-7'd1;
assign last_sel_bit[3:0]= srt_cnt_zero ? {srt_cnt_ini_tmp[1:0]==2'b00,
srt_cnt_ini_tmp[1:0]==2'b11,
srt_cnt_ini_tmp[1:0]==2'b10,
srt_cnt_ini_tmp[1:0]==2'b01}
: 4'b1000;
assign srt_cnt_zero = ~|srt_cnt[5:0] || srt_cnt[6];
assign srt_cnt_one = srt_cnt[5:0] == 6'b1 || srt_cnt_zero;
assign srt_sm_on = x_srt_on;
//assign srt_sm_on = x_srt_on && (srt_cnt[6:0] != 7'b0);
//assign srt_last_round = x_srt_on && (srt_remainder_zero || srt_cnt_zero);
assign srt_finish = srt_remainder_zero || srt_cnt_one;
assign x_srt_finish = srt_finish;
assign srt_iter_finish = srt_remainder_zero || srt_cnt_zero;
//==========================================================
// final result select
//==========================================================
// the last round, because we only select few bit of last round's quotient
// the remainder is kindly be shifted, we should shifted back
// &CombBeg; @137
always @( srt_remainder_pos[68:2]
or srt_remainder_neg[68:2]
or srt_remainder_out[70]
or last_sel_bit[3:0])
begin
case({srt_remainder_out[70],last_sel_bit[3:0]})
5'b01000: srt_pos_remainder[63:0] = srt_remainder_pos[65:2];
5'b00100: srt_pos_remainder[63:0] = srt_remainder_pos[66:3];
5'b00010: srt_pos_remainder[63:0] = srt_remainder_pos[67:4];
5'b00001: srt_pos_remainder[63:0] = srt_remainder_pos[68:5];
5'b11000: srt_pos_remainder[63:0] = srt_remainder_neg[65:2];
5'b10100: srt_pos_remainder[63:0] = srt_remainder_neg[66:3];
5'b10010: srt_pos_remainder[63:0] = srt_remainder_neg[67:4];
5'b10001: srt_pos_remainder[63:0] = srt_remainder_neg[68:5];
default: srt_pos_remainder[63:0] = {64{1'bx}};
endcase
// &CombEnd; @149
end
assign srt_qt_flop_borrow_in_1[63:0] = srt_pos_remainder[63:0] >> x_srt_dvr_disp[5:0];
assign srt_pos_qt[63:0] = srt_remainder_out[70] ? total_qt_rt_minus[66:3]
: total_qt_rt[66:3];
assign srt_qt_flop_borrow_in_0[63:0] = srt_pos_qt[63:0] >> (6'd63-srt_exp_disp[5:0]);
assign x_srt_rem_result[63:0] = srt_qt_flop_borrowed_val_1[63:0];
assign x_srt_div_result[63:0] = srt_qt_flop_borrowed_val_0[63:0];
// &ModuleEnd; @161
endmodule |
module sync_level2pulse(
clk,
rst_b,
sync_in,
sync_out,
sync_ack
);
input clk;
input rst_b;
input sync_in;
output sync_out;
output sync_ack;
reg sync_ff;
wire clk;
wire rst_b;
wire sync_in;
wire sync_out;
wire sync_ack;
wire sync_out_level;
sync_level2level x_sync_level2level (
.clk (clk),
.rst_b (rst_b),
.sync_in (sync_in),
.sync_out (sync_out_level)
);
always @ (posedge clk or negedge rst_b)
begin
if (!rst_b)
sync_ff <= 1'b0;
else
sync_ff <= sync_out_level;
end
assign sync_out = sync_out_level & ~sync_ff;
assign sync_ack = sync_out_level;
endmodule |
module compressor_42(p0,p1,p2,p3,cin,s,ca,cout);
parameter B_SIZE = 8;
input [B_SIZE-1:0] p0;
input [B_SIZE-1:0] p1;
input [B_SIZE-1:0] p2;
input [B_SIZE-1:0] p3;
input [B_SIZE-1:0] cin;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;
output [B_SIZE-1:0] cout;
wire [B_SIZE-1:0] xor0;
wire [B_SIZE-1:0] xor1;
wire [B_SIZE-1:0] xor2;
wire [B_SIZE-1:0] s;
wire [B_SIZE-1:0] ca;
wire [B_SIZE-1:0] cout;
assign xor0[B_SIZE-1:0] = p0[B_SIZE-1:0] ^ p1[B_SIZE-1:0];
assign xor1[B_SIZE-1:0] = p2[B_SIZE-1:0] ^ p3[B_SIZE-1:0];
assign xor2[B_SIZE-1:0] = xor1[B_SIZE-1:0] ^ xor0[B_SIZE-1:0];
//cout is used for input cin
assign cout[B_SIZE-1:0] = xor0[B_SIZE-1:0] & p2[B_SIZE-1:0]
| (~xor0[B_SIZE-1:0] & p0[B_SIZE-1:0]);
assign s[B_SIZE-1:0] = xor2[B_SIZE-1:0] ^ cin[B_SIZE-1:0];
assign ca[B_SIZE-1:0] = xor2[B_SIZE-1:0] & cin[B_SIZE-1:0]
| ~xor2[B_SIZE-1:0] & p3[B_SIZE-1:0];
endmodule |
module booth_code(
A, // mulitplicand
code, // booth code
product, // partial product
h,
sn // partial_sign
);
parameter B_SIZE = 53;
input [B_SIZE-1:0] A;
input [ 2:0] code;
output [B_SIZE:0] product;
output [ 1:0] h;
output sn;
reg [B_SIZE:0] product;
reg [ 1:0] h;
reg sn;
wire A_sign;
assign A_sign = A[B_SIZE-1];
always @(A[B_SIZE-1:0]
or code[2:0]
or A_sign)
begin
case(code[2:0])
3'b000 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
3'b001 : product[B_SIZE:0] = { A_sign , A[B_SIZE-1:0]};
3'b010 : product[B_SIZE:0] = { A_sign , A[B_SIZE-1:0]};
3'b011 : product[B_SIZE:0] = { A[B_SIZE-1:0],1'b0 };
3'b100 : product[B_SIZE:0] = {~A[B_SIZE-1:0],1'b1 };
3'b101 : product[B_SIZE:0] = { ~A_sign ,~A[B_SIZE-1:0]};
3'b110 : product[B_SIZE:0] = { ~A_sign ,~A[B_SIZE-1:0]};
3'b111 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
default: product[B_SIZE:0] = {B_SIZE+1{1'bx}};
endcase
end
always @(code[2:0]
or A_sign)
begin
case(code[2:0])
3'b000 : sn = 1'b1;
3'b001 : sn = ~A_sign;
3'b010 : sn = ~A_sign;
3'b011 : sn = ~A_sign;
3'b100 : sn = A_sign;
3'b101 : sn = A_sign;
3'b110 : sn = A_sign;
3'b111 : sn = 1'b1;
endcase
end
always @(code[2:0])
begin
case(code[2:0])
3'b000 : h[1:0] = 2'b00;
3'b001 : h[1:0] = 2'b00;
3'b010 : h[1:0] = 2'b00;
3'b011 : h[1:0] = 2'b00;
3'b100 : h[1:0] = 2'b01;
3'b101 : h[1:0] = 2'b01;
3'b110 : h[1:0] = 2'b01;
3'b111 : h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
end
endmodule |
module booth_code_v1(
A, // mulitplicand
code, // booth code
product, // partial product
h,
sn // partial_sign
);
parameter B_SIZE = 53;
input [B_SIZE-1:0] A;
input [ 2:0] code;
output [B_SIZE:0] product;
output [ 1:0] h;
output sn;
reg [B_SIZE:0] product;
reg [ 1:0] h;
reg sn;
always @(A[B_SIZE-1:0]
or code[2:0])
begin
case(code[2:0])
3'b000 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
3'b001 : product[B_SIZE:0] = { 1'b0 , A[B_SIZE-1:0]};
3'b010 : product[B_SIZE:0] = { 1'b0 , A[B_SIZE-1:0]};
3'b011 : product[B_SIZE:0] = { A[B_SIZE-1:0],1'b0 };
3'b100 : product[B_SIZE:0] = {~A[B_SIZE-1:0],1'b1 };
3'b101 : product[B_SIZE:0] = { 1'b1 ,~A[B_SIZE-1:0]};
3'b110 : product[B_SIZE:0] = { 1'b1 ,~A[B_SIZE-1:0]};
3'b111 : product[B_SIZE:0] = {B_SIZE+1{1'b0}};
default: product[B_SIZE:0] = {B_SIZE+1{1'bx}};
endcase
end
always @* begin
case(code[2:0])
3'b000 : sn = 1'b1;
3'b001 : sn = 1'b1;
3'b010 : sn = 1'b1;
3'b011 : sn = 1'b1;
3'b100 : sn = 1'b0;
3'b101 : sn = 1'b0;
3'b110 : sn = 1'b0;
3'b111 : sn = 1'b1;
endcase
end
always @(code[2:0])
begin
case(code[2:0])
3'b000 : h[1:0] = 2'b00;
3'b001 : h[1:0] = 2'b00;
3'b010 : h[1:0] = 2'b00;
3'b011 : h[1:0] = 2'b00;
3'b100 : h[1:0] = 2'b01;
3'b101 : h[1:0] = 2'b01;
3'b110 : h[1:0] = 2'b01;
3'b111 : h[1:0] = 2'b00;
default: h[1:0] = {2{1'bx}};
endcase
end
endmodule |
module compressor_32(a,b,c,s,ca);
parameter B_SIZE = 8;
input [B_SIZE-1:0] a;
input [B_SIZE-1:0] b;
input [B_SIZE-1:0] c;
output [B_SIZE-1:0] s;
output [B_SIZE-1:0] ca;
wire [B_SIZE-1:0] s;
wire [B_SIZE-1:0]ca;
assign s[B_SIZE-1:0] = a[B_SIZE-1:0]^b[B_SIZE-1:0]^c[B_SIZE-1:0];
assign ca[B_SIZE-1:0] = (a[B_SIZE-1:0]&b[B_SIZE-1:0])
| (c[B_SIZE-1:0]&b[B_SIZE-1:0])
| (a[B_SIZE-1:0]&c[B_SIZE-1:0]);
//reg [B_SIZE-1:0]s,ca;
//integer i;
//always @(a[B_SIZE-1:0]
// or b[B_SIZE-1:0]
// or c[B_SIZE-1:0])
//begin
// for(i= 0;i<B_SIZE;i=i+1) begin
// {ca[i],s[i]} = a[i] + b[i] + c[i];
// end
//end
endmodule |
module ct_fadd_close_s1_h(
close_adder0,
close_adder1,
close_op_chg,
close_sum,
close_sum_m1,
ff1_pred,
ff1_pred_onehot
);
// &Ports; @23
input [11:0] close_adder0;
input [11:0] close_adder1;
output close_op_chg;
output [11:0] close_sum;
output [11:0] close_sum_m1;
output [5 :0] ff1_pred;
output [11:0] ff1_pred_onehot;
// &Regs; @24
reg [5 :0] ff1_pred_t0;
reg [11:0] ff1_pred_t0_onehot;
// &Wires; @25
wire [11:0] close_adder0;
wire [11:0] close_adder0_t0;
wire [11:0] close_adder1;
wire [11:0] close_adder1_t0;
wire [11:0] close_ff1_a_t0;
wire [11:0] close_ff1_b_t0;
wire [11:0] close_ff1_c_t0;
wire [11:0] close_ff1_f_t0;
wire [11:0] close_ff1_g_t0;
wire [11:0] close_ff1_t_t0;
wire [11:0] close_ff1_z_t0;
wire [11:0] close_m1_oper2;
wire close_op_chg;
wire [11:0] close_sum;
wire [11:0] close_sum_m1;
wire [11:0] close_sum_m1_t0;
wire [11:0] close_sum_t0;
wire [5 :0] ff1_pred;
wire [11:0] ff1_pred_onehot;
//Three Type
//t0 : !src0_e_is_0 && !src1_e_is_0
//t1 : !src0_e_is_0 && src1_e_is_0
//t2 : src0_e_is_0 && src1_e_is_0
//assign close_sum[11:0] = {12{type0_sel}} & close_sum_t0[11:0] |
// {12{type1_sel}} & close_sum_t1[11:0] |
// {12{type2_sel}} & close_sum_t2[11:0];
//assign close_sum_m1[11:0] = {12{type0_sel}} & close_sum_m1_t0[11:0] |
// {12{type1_sel}} & close_sum_m1_t1[11:0] |
// {12{type2_sel}} & close_sum_m1_t2[11:0];
//assign ff1_pred[11:0] = {12{type0_sel}} & ff1_pred_t0_onehot[11:0] |
// {12{type1_sel}} & ff1_pred_t1_onehot[11:0] |
// {12{type2_sel}} & ff1_pred_t2[11:0];
assign close_sum[11:0] = close_sum_t0[11:0];
assign close_sum_m1[11:0] = close_sum_m1_t0[11:0];
assign ff1_pred_onehot[11:0] = ff1_pred_t0_onehot[11:0];
assign ff1_pred[5:0] = ff1_pred_t0[5:0];
assign close_op_chg = close_sum[11];
// &Force("output","close_sum"); @49
assign close_adder0_t0[11:0] = close_adder0[11:0];
assign close_adder1_t0[11:0] = close_adder1[11:0];
assign close_m1_oper2[11:0] = 12'b10;
// &Force("nonport","close_sum_t0"); @55
// &Force("nonport","close_sum_m1_t0"); @56
// &Force("nonport","close_m1_oper2"); @57
//csky vperl_off
//close_sum0 for F0-F1
assign close_sum_t0[11:0] = $unsigned($signed(close_adder0_t0[11:0]) - $signed(close_adder1_t0[11:0]));
//close_sum0 for F1-F0
//close_sum select, keep sum not negative
//close_sum0_m1
assign close_sum_m1_t0[11:0] = $unsigned($signed(close_adder0_t0[11:0])
- $signed(close_adder1_t0[11:0])
+ $signed(close_m1_oper2[11:0]));
//csky vperl_on
//FF1 Logic of Close Path S0
//If predict first 1 set at r[n]
//Actual first 1 may set at r[n+1] or r[n]
//A and B are to oprand
assign close_ff1_a_t0[11:0] = close_adder0_t0[11:0];
assign close_ff1_b_t0[11:0] = close_adder1_t0[11:0];
//C = B && act_add || ~B && act_sub
assign close_ff1_c_t0[11:0] = ~close_ff1_b_t0[11:0];
//T = A^C G=A&C Z=(~A)&(~C)
assign close_ff1_t_t0[11:0] = close_ff1_a_t0[11:0] ^ close_ff1_c_t0[11:0];
assign close_ff1_g_t0[11:0] = close_ff1_a_t0[11:0] & close_ff1_c_t0[11:0];
assign close_ff1_z_t0[11:0] = (~close_ff1_a_t0[11:0]) & (~close_ff1_c_t0[11:0]);
//F :
//fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
//f0 = t1(g0En+z0) + (~t1)(z0En+g0)
//fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
assign close_ff1_f_t0[11] = ( close_ff1_g_t0[11] & (~close_ff1_z_t0[10])) |
( close_ff1_z_t0[11] & (~close_ff1_g_t0[10]));
assign close_ff1_f_t0[0] = (( close_ff1_t_t0[1]) & (close_ff1_g_t0[0] | close_ff1_z_t0[0])) |
((~close_ff1_t_t0[1]) & (close_ff1_z_t0[0] | close_ff1_g_t0[0]));
assign close_ff1_f_t0[10:1] = (( close_ff1_t_t0[11:2]) & ((close_ff1_g_t0[10:1] & (~close_ff1_z_t0[9:0])) |
( close_ff1_z_t0[10:1] & (~close_ff1_g_t0[9:0])))) |
((~close_ff1_t_t0[11:2]) & ((close_ff1_g_t0[10:1] & (~close_ff1_g_t0[9:0])) |
( close_ff1_z_t0[10:1] & (~close_ff1_z_t0[9:0]))));
// &CombBeg; @97
always @( close_ff1_f_t0[11:0])
begin
casez(close_ff1_f_t0[11:0])
12'b1?????_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b100000_000000;
ff1_pred_t0[5:0] = 6'd0;
end
12'b01????_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b010000_000000;
ff1_pred_t0[5:0] = 6'd1;
end
12'b001???_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b001000_000000;
ff1_pred_t0[5:0] = 6'd2;
end
12'b0001??_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b000100_000000;
ff1_pred_t0[5:0] = 6'd3;
end
12'b00001?_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b000010_000000;
ff1_pred_t0[5:0] = 6'd4;
end
12'b000001_?????? : begin
ff1_pred_t0_onehot[11:0] = 12'b000001_000000;
ff1_pred_t0[5:0] = 6'd5;
end
12'b000000_1????? : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_100000;
ff1_pred_t0[5:0] = 6'd6;
end
12'b000000_01???? : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_010000;
ff1_pred_t0[5:0] = 6'd7;
end
12'b000000_001??? : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_001000;
ff1_pred_t0[5:0] = 6'd8;
end
12'b000000_0001?? : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_000100;
ff1_pred_t0[5:0] = 6'd9;
end
12'b000000_00001? : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_000010;
ff1_pred_t0[5:0] = 6'd10;
end
12'b000000_000001 : begin
ff1_pred_t0_onehot[11:0] = 12'b000000_000001;
ff1_pred_t0[5:0] = 6'd11;
end
default : begin
ff1_pred_t0_onehot[11:0] = {12{1'bx}};
ff1_pred_t0[5:0] = {6{1'bx}};
end
endcase
// &CombEnd; @152
end
// &ModuleEnd; @155
endmodule |
module ct_fspu_top(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_mtvr_src0,
dp_vfalu_ex1_pipex_sel,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
forever_cpuclk,
fspu_forward_r_vld,
fspu_forward_result,
fspu_mfvr_data,
pad_yy_icg_scan_en
);
// &Ports; @24
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
input [2 :0] dp_vfalu_ex1_pipex_sel;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output fspu_forward_r_vld;
output [63:0] fspu_forward_result;
output [63:0] fspu_mfvr_data;
// &Regs; @25
// &Wires; @26
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire ex1_pipedown;
wire ex2_pipedown;
wire ex3_pipedown;
wire forever_cpuclk;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire pad_yy_icg_scan_en;
// &Instance("ct_fspu_ctrl"); @28
ct_fspu_ctrl x_ct_fspu_ctrl (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel),
.ex1_pipedown (ex1_pipedown ),
.ex2_pipedown (ex2_pipedown ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_fspu_dp"); @29
ct_fspu_dp x_ct_fspu_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_mtvr_src0 (dp_vfalu_ex1_pipex_mtvr_src0),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.ex1_pipedown (ex1_pipedown ),
.ex2_pipedown (ex2_pipedown ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.fspu_forward_r_vld (fspu_forward_r_vld ),
.fspu_forward_result (fspu_forward_result ),
.fspu_mfvr_data (fspu_mfvr_data ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &ModuleEnd; @31
endmodule |
module ct_fspu_ctrl(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_sel,
ex1_pipedown,
ex2_pipedown,
ex3_pipedown,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [2:0] dp_vfalu_ex1_pipex_sel;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output ex1_pipedown;
output ex2_pipedown;
output ex3_pipedown;
// &Regs; @24
reg ex2_pipedown;
reg ex3_pipedown;
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [2:0] dp_vfalu_ex1_pipex_sel;
wire ex1_pipedown;
wire ex1_vld_clk;
wire ex1_vld_clk_en;
wire ex2_vld_clk;
wire ex2_vld_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//EX1 Control
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0); @28
assign ex1_pipedown = dp_vfalu_ex1_pipex_sel[0];
// &Force("output","ex1_pipedown"); @30
//EX2 Control
//gate clk
// &Instance("gated_clk_cell","x_ex1_vld_clk"); @37
gated_clk_cell x_ex1_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @38
// .clk_out (ex1_vld_clk),//Out Clock @39
// .external_en (1'b0), @40
// .global_en (cp0_yy_clk_en), @41
// .local_en (ex1_vld_clk_en),//Local Condition @42
// .module_en (cp0_vfpu_icg_en) @43
// ); @44
assign ex1_vld_clk_en = ex1_pipedown || ex2_pipedown;
always @(posedge ex1_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex2_pipedown <= 1'b0;
else if(ex1_pipedown)
ex2_pipedown <= 1'b1;
else
ex2_pipedown <= 1'b0;
end
// &Force("output","ex2_pipedown"); @55
//EX3 Control
//gate clk
// &Instance("gated_clk_cell","x_ex2_vld_clk"); @59
gated_clk_cell x_ex2_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @60
// .clk_out (ex2_vld_clk),//Out Clock @61
// .external_en (1'b0), @62
// .global_en (cp0_yy_clk_en), @63
// .local_en (ex2_vld_clk_en),//Local Condition @64
// .module_en (cp0_vfpu_icg_en) @65
// ); @66
assign ex2_vld_clk_en = ex2_pipedown || ex3_pipedown;
always @(posedge ex2_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex3_pipedown <= 1'b0;
else if(ex2_pipedown)
ex3_pipedown <= 1'b1;
else
ex3_pipedown <= 1'b0;
end
// &Force("output","ex3_pipedown"); @77
// &ModuleEnd; @79
endmodule |
module ct_fspu_dp(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_mtvr_src0,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
ex1_pipedown,
ex2_pipedown,
ex3_pipedown,
forever_cpuclk,
fspu_forward_r_vld,
fspu_forward_result,
fspu_mfvr_data,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input ex1_pipedown;
input ex2_pipedown;
input ex3_pipedown;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output fspu_forward_r_vld;
output [63:0] fspu_forward_result;
output [63:0] fspu_mfvr_data;
// &Regs; @24
reg [63:0] fspu_ex2_result;
reg [63:0] fspu_ex3_result;
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [63:0] doub_mtvr_src0;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire ex1_doub_op_fmv;
wire ex1_double;
wire [63:0] ex1_freg_result;
wire ex1_half_op_fmv;
wire ex1_op_class;
wire ex1_op_doub_fmvfx;
wire ex1_op_doub_fsgnj;
wire ex1_op_doub_fsgnjn;
wire ex1_op_doub_fsgnjx;
wire ex1_op_fmvfx;
wire ex1_op_fmvxf;
wire ex1_op_fsgnj;
wire ex1_op_fsgnjn;
wire ex1_op_fsgnjx;
wire ex1_op_half_fmvfx;
wire ex1_op_sing_fmvfx;
wire ex1_op_sing_fsgnj;
wire ex1_op_sing_fsgnjn;
wire ex1_op_sing_fsgnjx;
wire ex1_pipe_clk;
wire ex1_pipe_clk_en;
wire ex1_pipedown;
wire [63:0] ex1_pipex_src0;
wire [63:0] ex1_pipex_src1;
wire [63:0] ex1_result;
wire [63:0] ex1_set0_doub_result;
wire [63:0] ex1_set0_half0_result;
wire [63:0] ex1_set0_sing0_result;
wire ex1_sing_op_fmv;
wire ex1_single;
wire ex2_pipe_clk;
wire ex2_pipe_clk_en;
wire ex2_pipedown;
wire ex3_pipedown;
wire forever_cpuclk;
wire [63:0] fspu_ex3_result_pre;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire [19:0] func;
wire pad_yy_icg_scan_en;
wire [63:0] scalar_int_class_result;
wire [63:0] scalar_int_mvxf_result;
wire [63:0] scalar_x_result;
wire [63:0] set0_doub_result_fclass;
wire [63:0] set0_doub_result_fmfvr;
wire [15:0] set0_half0_result_fclass;
wire [63:0] set0_half0_result_fmfvr;
wire [63:0] set0_oper0;
wire [63:0] set0_oper1;
wire [31:0] set0_sing0_result_fclass;
wire [63:0] set0_sing0_result_fmfvr;
parameter FMV_SI32_F32 = 0;
parameter FMV_SI64_F64 = 1;
parameter FMV_F32_SI32 = 2;
parameter FMV_F64_SI64 = 3;
parameter FSGNJS = 4;
parameter FSGNJD = 5;
parameter FSGNJNS = 6;
parameter FSGNJND = 7;
parameter FSGNJXS = 8;
parameter FSGNJXD = 9;
parameter FCLASSS = 10;
parameter FCLASSD = 11;
//=====================ins_type generate====================
// &Force("bus","dp_vfalu_ex1_pipex_func",19,0); @42
assign func[19:0] = dp_vfalu_ex1_pipex_func[19:0];
assign ex1_double = func[16];
assign ex1_single = func[15];
assign ex1_op_fsgnjx = func[6] && func[2];
assign ex1_op_fsgnjn = func[6] && func[1];
assign ex1_op_fsgnj = func[6] && func[0];
assign ex1_op_fmvfx = func[5] && func[0];
assign ex1_op_fmvxf = func[5] && func[2];
assign ex1_op_class = func[18];
assign ex1_op_sing_fsgnjx = ex1_op_fsgnjx && ex1_single;
assign ex1_op_sing_fsgnjn = ex1_op_fsgnjn && ex1_single;
assign ex1_op_sing_fsgnj = ex1_op_fsgnj && ex1_single;
assign ex1_op_doub_fsgnjx = ex1_op_fsgnjx && ex1_double;
assign ex1_op_doub_fsgnjn = ex1_op_fsgnjn && ex1_double;
assign ex1_op_doub_fsgnj = ex1_op_fsgnj && ex1_double;
assign ex1_op_sing_fmvfx = ex1_op_fmvfx && ex1_single;
//assign ex1_op_sing_fmvxf = ex1_op_fmvxf && ex1_single;
assign ex1_op_half_fmvfx = ex1_op_fmvfx && !ex1_single && !ex1_double;
assign ex1_op_doub_fmvfx = ex1_op_fmvfx && ex1_double;
//assign ex1_op_doub_fmvxf = ex1_op_fmvxf && ex1_double;
// &Force("bus","dp_vfalu_ex1_pipex_srcv0",127,0); @93
// &Force("bus","dp_vfalu_ex1_pipex_srcv1",127,0); @94
// &Force("bus","dp_vfalu_ex1_pipex_mtvr_src0",63,0); @95
// &Force("bus","dp_vfalu_ex1_pipex_mtvr_src1",63,0); @96
// &Force("bus","dp_vfalu_ex1_pipex_srcv0",63,0); @104
// &Force("bus","dp_vfalu_ex1_pipex_srcv1",63,0); @105
// &Force("bus","dp_vfalu_ex1_pipex_mtvr_src0",63,0); @106
assign ex1_pipex_src0[63:0] = dp_vfalu_ex1_pipex_srcf0[63:0];
assign ex1_pipex_src1[63:0] = dp_vfalu_ex1_pipex_srcf1[63:0];
// &Force("nonport","set0_sing1_result_fmfvr"); @125
// &ConnRule(s/result/set0_doub_result/); @126
// &ConnRule(s/ex1_op_/ex1_op_doub_/); @127
// &Instance("ct_fspu_double","x_set0_ct_fspu_double"); @128
// &Connect(.ex1_oper0(set0_oper0[63:0])); @129
// &Connect(.ex1_oper1(set0_oper1[63:0])); @130
// &Connect(.mtvr_src0(doub_mtvr_src0)); @131
// &Connect(.ex1_op_fmvvf(ex1_doub_op_fmv)); @132
// &ConnRule(s/result/set0_sing0_result/); @134
// &ConnRule(s/ex1_op_/ex1_op_sing_/); @135
// &Instance("ct_fspu_single","x_set0_ct_fspu_single0"); @136
// &Connect(.ex1_oper0(set0_oper0[63:0])); @137
// &Connect(.ex1_oper1(set0_oper1[63:0])); @138
// &Connect(.mtvr_src0(doub_mtvr_src0[63:0])); @139
// &Connect(.ex1_op_fmvvf(ex1_sing_op_fmv)); @140
// &ConnRule(s/result/set0_sing1_result/); @144
// &ConnRule(s/ex1_op_/ex1_op_sing_/); @145
// &Instance("ct_fspu_single","x_set0_ct_fspu_single1"); @146
// &Connect(.ex1_oper0(set0_sing1_oper0[63:0])); @147
// &Connect(.ex1_oper1(set0_sing1_oper1[63:0])); @148
// &Connect(.mtvr_src0(set0_oper1[63:0])); @149
// &ConnRule(s/result/set0_half0_result/); @152
// &ConnRule(s/ex1_op_/ex1_op_half_/); @153
// &Instance("ct_fspu_half","x_set0_ct_fspu_half0"); @154
// &Connect(.ex1_oper0(set0_oper0[63:0])); @155
// &Connect(.ex1_oper1(set0_oper1[63:0])); @156
// &Connect(.mtvr_src0(doub_mtvr_src0[63:0])); @157
// &Connect(.ex1_op_fmvvf(ex1_half_op_fmv)); @158
// &ConnRule(s/result/set0_half1_result/); @162
// &ConnRule(s/ex1_op_/ex1_op_half_/); @163
// &Instance("ct_fspu_half","x_set0_ct_fspu_half1"); @164
// &Connect(.ex1_oper0(set0_half1_oper0[63:0])); @165
// &Connect(.ex1_oper1(set0_half1_oper1[63:0])); @166
// &Connect(.mtvr_src0(set0_oper1[63:0])); @167
// &ConnRule(s/result/set0_half2_result/); @171
// &ConnRule(s/ex1_op_/ex1_op_half_/); @172
// &Instance("ct_fspu_half","x_set0_ct_fspu_half2"); @173
// &Connect(.ex1_oper0(set0_half2_oper0[63:0])); @174
// &Connect(.ex1_oper1(set0_half2_oper1[63:0])); @175
// &Connect(.mtvr_src0(set0_oper1[63:0])); @176
// &ConnRule(s/result/set0_half3_result/); @180
// &ConnRule(s/ex1_op_/ex1_op_half_/); @181
// &Instance("ct_fspu_half","x_set0_ct_fspu_half3"); @182
// &Connect(.ex1_oper0(set0_half3_oper0[63:0])); @183
// &Connect(.ex1_oper1(set0_half3_oper1[63:0])); @184
// &Connect(.mtvr_src0(set0_oper1[63:0])); @185
// &Force("nonport","set1_doub_result_fmfvr"); @191
// &Force("nonport","set1_sing0_result_fmfvr"); @192
// &Force("nonport","set1_sing1_result_fmfvr"); @193
// &ConnRule(s/result/set1_doub_result/); @195
// &Instance("ct_fspu_double","x_set1_ct_fspu_double"); @196
// &Connect(.ex1_oper0(set1_oper0[63:0])); @197
// &Connect(.ex1_oper1(set1_oper1[63:0])); @198
// &Connect(.mtvr_src0(set1_oper1[63:0])); @199
// &ConnRule(s/result/set1_sing0_result/); @201
// &Instance("ct_fspu_single","x_set1_ct_fspu_single0"); @202
// &Connect(.ex1_oper0(set1_oper0[63:0])); @203
// &Connect(.ex1_oper1(set1_oper1[63:0])); @204
// &Connect(.mtvr_src0(set1_oper1[63:0])); @205
// &ConnRule(s/result/set1_sing1_result/); @209
// &Instance("ct_fspu_single","x_set1_ct_fspu_single1"); @210
// &Connect(.ex1_oper0(set1_sing1_oper0[63:0])); @211
// &Connect(.ex1_oper1(set1_sing1_oper1[63:0])); @212
// &Connect(.mtvr_src0(set1_oper1[63:0])); @213
// &ConnRule(s/result/set1_half0_result/); @215
// &Instance("ct_fspu_half","x_set1_ct_fspu_half0"); @216
// &Connect(.ex1_oper0(set1_oper0[63:0])); @217
// &Connect(.ex1_oper1(set1_oper1[63:0])); @218
// &Connect(.mtvr_src0(set1_oper1[63:0])); @219
// &ConnRule(s/result/set1_half1_result/); @223
// &Instance("ct_fspu_half","x_set1_ct_fspu_half1"); @224
// &Connect(.ex1_oper0(set1_half1_oper0[63:0])); @225
// &Connect(.ex1_oper1(set1_half1_oper1[63:0])); @226
// &Connect(.mtvr_src0(set1_oper1[63:0])); @227
// &ConnRule(s/result/set1_half2_result/); @231
// &Instance("ct_fspu_half","x_set1_ct_fspu_half2"); @232
// &Connect(.ex1_oper0(set1_half2_oper0[63:0])); @233
// &Connect(.ex1_oper1(set1_half2_oper1[63:0])); @234
// &Connect(.mtvr_src0(set1_oper1[63:0])); @235
// &ConnRule(s/result/set1_half3_result/); @239
// &Instance("ct_fspu_half","x_set1_ct_fspu_half3"); @240
// &Connect(.ex1_oper0(set1_half3_oper0[63:0])); @241
// &Connect(.ex1_oper1(set1_half3_oper1[63:0])); @242
// &Connect(.mtvr_src0(set1_oper1[63:0])); @243
// &Force("nonport","set0_half1_result_fmfvr"); @244
// &Force("nonport","set0_half2_result_fmfvr"); @245
// &Force("nonport","set0_half3_result_fmfvr"); @246
// &Force("nonport","set1_half0_result_fmfvr"); @247
// &Force("nonport","set1_half1_result_fmfvr"); @248
// &Force("nonport","set1_half2_result_fmfvr"); @249
// &Force("nonport","set1_half3_result_fmfvr"); @250
assign doub_mtvr_src0[63:0] = ex1_op_fmvfx ? dp_vfalu_ex1_pipex_mtvr_src0[63:0]
: ex1_pipex_src1[63:0];
assign set0_oper0[63:0] = ex1_pipex_src0[63:0];
assign set0_oper1[63:0] = ex1_pipex_src1[63:0];
assign ex1_doub_op_fmv = ex1_op_doub_fmvfx;
assign ex1_sing_op_fmv = ex1_op_sing_fmvfx;
assign ex1_half_op_fmv = ex1_op_half_fmvfx;
//double
// &Force("nonport","set0_sing1_result_fmfvr"); @315
// &ConnRule(s/result/set0_doub_result/); @316
// &ConnRule(s/ex1_op_/ex1_op_doub_/); @317
// &Instance("ct_fspu_double","x_set0_ct_fspu_double"); @318
ct_fspu_double x_set0_ct_fspu_double (
.ex1_op_fmvvf (ex1_doub_op_fmv ),
.ex1_op_fsgnj (ex1_op_doub_fsgnj ),
.ex1_op_fsgnjn (ex1_op_doub_fsgnjn ),
.ex1_op_fsgnjx (ex1_op_doub_fsgnjx ),
.ex1_oper0 (set0_oper0[63:0] ),
.ex1_oper1 (set0_oper1[63:0] ),
.ex1_result (ex1_set0_doub_result ),
.mtvr_src0 (doub_mtvr_src0 ),
.result_fclass (set0_doub_result_fclass),
.result_fmfvr (set0_doub_result_fmfvr )
);
// &Connect(.ex1_oper0(set0_oper0[63:0])); @319
// &Connect(.ex1_oper1(set0_oper1[63:0])); @320
// &Connect(.mtvr_src0(doub_mtvr_src0)); @321
// &Connect(.ex1_op_fmvvf(ex1_doub_op_fmv)); @322
//single 0
// &ConnRule(s/result/set0_sing0_result/); @324
// &ConnRule(s/ex1_op_/ex1_op_sing_/); @325
// &Instance("ct_fspu_single","x_set0_ct_fspu_single0"); @326
ct_fspu_single x_set0_ct_fspu_single0 (
.check_nan (1'b0 ),
.ex1_op_fmvvf (ex1_sing_op_fmv ),
.ex1_op_fsgnj (ex1_op_sing_fsgnj ),
.ex1_op_fsgnjn (ex1_op_sing_fsgnjn ),
.ex1_op_fsgnjx (ex1_op_sing_fsgnjx ),
.ex1_oper0 (set0_oper0[63:0] ),
.ex1_oper1 (set0_oper1[63:0] ),
.ex1_result (ex1_set0_sing0_result ),
.ex1_scalar (1'b1 ),
.mtvr_src0 (doub_mtvr_src0[63:0] ),
.result_fclass (set0_sing0_result_fclass),
.result_fmfvr (set0_sing0_result_fmfvr )
);
// &Connect(.ex1_oper0(set0_oper0[63:0])); @327
// &Connect(.ex1_oper1(set0_oper1[63:0])); @328
// &Connect(.mtvr_src0(doub_mtvr_src0[63:0])); @329
// &Connect(.ex1_op_fmvvf(ex1_sing_op_fmv)); @330
// &Connect(.ex1_scalar(1'b1)); @331
// &Connect(.check_nan(1'b0)); @332
//half 0
// &ConnRule(s/result/set0_half0_result/); @334
// &Instance("ct_fspu_half","x_set0_ct_fspu_half0"); @335
ct_fspu_half x_set0_ct_fspu_half0 (
.check_nan (1'b0 ),
.ex1_op_fmvvf (ex1_half_op_fmv ),
.ex1_op_fsgnj (ex1_op_fsgnj ),
.ex1_op_fsgnjn (ex1_op_fsgnjn ),
.ex1_op_fsgnjx (ex1_op_fsgnjx ),
.ex1_oper0 (set0_oper0[63:0] ),
.ex1_oper1 (set0_oper1[63:0] ),
.ex1_result (ex1_set0_half0_result ),
.ex1_scalar (1'b1 ),
.mtvr_src0 (doub_mtvr_src0[63:0] ),
.result_fclass (set0_half0_result_fclass),
.result_fmfvr (set0_half0_result_fmfvr )
);
// &Connect(.ex1_oper0(set0_oper0[63:0])); @336
// &Connect(.ex1_oper1(set0_oper1[63:0])); @337
// &Connect(.mtvr_src0(doub_mtvr_src0[63:0])); @338
// &Connect(.ex1_scalar(1'b1)); @339
// &Connect(.ex1_op_fmvvf(ex1_half_op_fmv)); @340
// &Connect(.check_nan(1'b0)); @341
assign scalar_int_mvxf_result[63:0] = ex1_double ? set0_doub_result_fmfvr[63:0] :
ex1_single ? set0_sing0_result_fmfvr[63:0]
: set0_half0_result_fmfvr[63:0];
assign scalar_int_class_result[63:0] = ex1_double ? set0_doub_result_fclass[63:0] :
ex1_single ? {32'b0,set0_sing0_result_fclass[31:0]}
: {48'b0,set0_half0_result_fclass[15:0]} ;
assign scalar_x_result[63:0] = {64{ex1_op_class}} & scalar_int_class_result[63:0] |
{64{ex1_op_fmvxf}} & scalar_int_mvxf_result[63:0];
//assign pipex_dp_ex1_vfalu_mfvr_data[63:0] = scalar_x_result[63:0];
assign fspu_mfvr_data[63:0] = scalar_x_result[63:0];
assign ex1_freg_result[63:0] = ex1_double ? ex1_set0_doub_result[63:0] :
ex1_single ? ex1_set0_sing0_result[63:0] :
ex1_set0_half0_result[63:0];
assign ex1_result[63:0] = ex1_freg_result[63:0];
//=======================Pipe to EX2========================
//gate clk
// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @365
gated_clk_cell x_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @366
// .clk_out (ex1_pipe_clk),//Out Clock @367
// .external_en (1'b0), @368
// .global_en (cp0_yy_clk_en), @369
// .local_en (ex1_pipe_clk_en),//Local Condition @370
// .module_en (cp0_vfpu_icg_en) @371
// ); @372
assign ex1_pipe_clk_en = ex1_pipedown;
always @(posedge ex1_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
fspu_ex2_result[63:0] <= 64'b0;
end
else if(ex1_pipedown)
begin
fspu_ex2_result[63:0] <= ex1_result[63:0];
end
else
begin
fspu_ex2_result[63:0] <= fspu_ex2_result[63:0];
end
end
//=======================Pipe to EX3========================
//gate clk
// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @421
gated_clk_cell x_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @422
// .clk_out (ex2_pipe_clk),//Out Clock @423
// .external_en (1'b0), @424
// .global_en (cp0_yy_clk_en), @425
// .local_en (ex2_pipe_clk_en),//Local Condition @426
// .module_en (cp0_vfpu_icg_en) @427
// ); @428
assign ex2_pipe_clk_en = ex2_pipedown;
always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
fspu_ex3_result[63:0] <= 64'b0;
else if(ex2_pipedown)
fspu_ex3_result[63:0] <= fspu_ex3_result_pre[63:0];
else
fspu_ex3_result[63:0] <= fspu_ex3_result[63:0];
end
assign fspu_ex3_result_pre[63:0] = fspu_ex2_result[63:0];
assign fspu_forward_result[63:0] = fspu_ex3_result[63:0];
assign fspu_forward_r_vld = ex3_pipedown;
// &ModuleEnd; @495
endmodule |
module ct_fadd_ctrl(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_sel,
ex1_pipe_clk,
ex1_pipedown,
ex2_pipedown,
ex3_pipedown,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @22
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [2:0] dp_vfalu_ex1_pipex_sel;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output ex1_pipe_clk;
output ex1_pipedown;
output ex2_pipedown;
output ex3_pipedown;
// &Regs; @23
reg ex2_pipedown;
reg ex3_pipedown;
// &Wires; @24
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [2:0] dp_vfalu_ex1_pipex_sel;
wire ex1_pipe_clk;
wire ex1_pipe_clk_en;
wire ex1_pipedown;
wire ex1_vld_clk;
wire ex1_vld_clk_en;
wire ex2_vld_clk;
wire ex2_vld_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//EX1 Control
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0); @27
assign ex1_pipedown = dp_vfalu_ex1_pipex_sel[1];
// &Force("output","ex1_pipedown"); @29
//EX2 Control
//gate clk
// &Instance("gated_clk_cell","x_ex1_vld_clk"); @33
gated_clk_cell x_ex1_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @34
// .clk_out (ex1_vld_clk),//Out Clock @35
// .external_en (1'b0), @36
// .global_en (cp0_yy_clk_en), @37
// .local_en (ex1_vld_clk_en),//Local Condition @38
// .module_en (cp0_vfpu_icg_en) @39
// ); @40
assign ex1_vld_clk_en = ex1_pipedown || ex2_pipedown;
always @(posedge ex1_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
ex2_pipedown <= 1'b0;
end
else if(ex1_pipedown)
begin
ex2_pipedown <= 1'b1;
end
else
begin
ex2_pipedown <= 1'b0;
end
end
// &Force("output","ex2_pipedown"); @57
//gate clk
// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @59
gated_clk_cell x_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @60
// .clk_out (ex1_pipe_clk),//Out Clock @61
// .external_en (1'b0), @62
// .global_en (cp0_yy_clk_en), @63
// .local_en (ex1_pipe_clk_en),//Local Condition @64
// .module_en (cp0_vfpu_icg_en) @65
// ); @66
assign ex1_pipe_clk_en = ex1_pipedown;
//EX3 Control
//gate clk
// &Instance("gated_clk_cell","x_ex2_vld_clk"); @71
gated_clk_cell x_ex2_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @72
// .clk_out (ex2_vld_clk),//Out Clock @73
// .external_en (1'b0), @74
// .global_en (cp0_yy_clk_en), @75
// .local_en (ex2_vld_clk_en),//Local Condition @76
// .module_en (cp0_vfpu_icg_en) @77
// ); @78
assign ex2_vld_clk_en = ex2_pipedown || ex3_pipedown;
always @(posedge ex2_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
ex3_pipedown <= 1'b0;
end
else if(ex2_pipedown)
begin
ex3_pipedown <= 1'b1;
end
else
begin
ex3_pipedown <= 1'b0;
end
end
// &Force("output","ex3_pipedown"); @95
// &ModuleEnd; @97
endmodule |
module ct_fcnvt_stod_sh(
stod_sh_cnt,
stod_sh_f_v,
stod_sh_src
);
// &Ports; @23
input [22:0] stod_sh_src;
output [11:0] stod_sh_cnt;
output [23:0] stod_sh_f_v;
// &Regs; @24
reg [11:0] stod_sh_cnt;
reg [23:0] stod_sh_f_v;
// &Wires; @25
wire [22:0] stod_sh_src;
// &CombBeg; @27
always @( stod_sh_src[22:0])
begin
casez(stod_sh_src[22:0])
23'b1??????????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[22:0],1'b0};
stod_sh_cnt[11:0] = 12'hf81; //-127
end
23'b01?????????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[21:0],2'b0};
stod_sh_cnt[11:0] = 12'hf80; //-128
end
23'b001????????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[20:0],3'b0};
stod_sh_cnt[11:0] = 12'hf7f; //-129
end
23'b0001???????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[19:0],4'b0};
stod_sh_cnt[11:0] = 12'hf7e; //-130
end
23'b00001??????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[18:0],5'b0};
stod_sh_cnt[11:0] = 12'hf7d; //-131
end
23'b000001?????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[17:0],6'b0};
stod_sh_cnt[11:0] = 12'hf7c; //-132
end
23'b0000001????????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[16:0],7'b0};
stod_sh_cnt[11:0] = 12'hf7b; //-133
end
23'b00000001???????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[15:0],8'b0};
stod_sh_cnt[11:0] = 12'hf7a; //-134
end
23'b000000001??????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[14:0],9'b0};
stod_sh_cnt[11:0] = 12'hf79; //-135
end
23'b0000000001?????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[13:0],10'b0};
stod_sh_cnt[11:0] = 12'hf78; //-136
end
23'b00000000001????????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[12:0],11'b0};
stod_sh_cnt[11:0] = 12'hf77; //-137
end
23'b000000000001???????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[11:0],12'b0};
stod_sh_cnt[11:0] = 12'hf76; //-138
end
23'b0000000000001??????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[10:0],13'b0};
stod_sh_cnt[11:0] = 12'hf75; //-139
end
23'b00000000000001?????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[9:0],14'b0};
stod_sh_cnt[11:0] = 12'hf74; //-140
end
23'b000000000000001????????: begin
stod_sh_f_v[23:0] = {stod_sh_src[8:0],15'b0};
stod_sh_cnt[11:0] = 12'hf73; //-141
end
23'b0000000000000001???????: begin
stod_sh_f_v[23:0] = {stod_sh_src[7:0],16'b0};
stod_sh_cnt[11:0] = 12'hf72; //-142
end
23'b00000000000000001??????: begin
stod_sh_f_v[23:0] = {stod_sh_src[6:0],17'b0};
stod_sh_cnt[11:0] = 12'hf71; //-143
end
23'b000000000000000001?????: begin
stod_sh_f_v[23:0] = {stod_sh_src[5:0],18'b0};
stod_sh_cnt[11:0] = 12'hf70; //-144
end
23'b0000000000000000001????: begin
stod_sh_f_v[23:0] = {stod_sh_src[4:0],19'b0};
stod_sh_cnt[11:0] = 12'hf6f; //-145
end
23'b00000000000000000001???: begin
stod_sh_f_v[23:0] = {stod_sh_src[3:0],20'b0};
stod_sh_cnt[11:0] = 12'hf6e; //-146
end
23'b000000000000000000001??: begin
stod_sh_f_v[23:0] = {stod_sh_src[2:0],21'b0};
stod_sh_cnt[11:0] = 12'hf6d; //-137
end
23'b0000000000000000000001?: begin
stod_sh_f_v[23:0] = {stod_sh_src[1:0],22'b0};
stod_sh_cnt[11:0] = 12'hf6c; //-138
end
23'b00000000000000000000001: begin
stod_sh_f_v[23:0] = {1'b1,23'b0};
stod_sh_cnt[11:0] = 12'hf6b; //-149
end
default: begin
stod_sh_f_v[23:0] = 24'b0;
stod_sh_cnt[11:0] = 12'h0;
end
endcase
// &CombEnd; @126
end
// &ModuleEnd; @129
endmodule |
module ct_fadd_scalar_dp(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
ex1_doub_cmp_result,
ex1_doub_half_cmp_result,
ex1_double,
ex1_op_add,
ex1_op_cmp,
ex1_op_feq,
ex1_op_fle,
ex1_op_flt,
ex1_op_fne,
ex1_op_ford,
ex1_op_maxnm,
ex1_op_minnm,
ex1_op_sub,
ex1_pipe_clk,
ex1_pipedown,
ex1_single,
ex2_double,
ex2_op_add,
ex2_op_cmp,
ex2_op_fle,
ex2_op_flt,
ex2_op_maxnm,
ex2_op_minnm,
ex2_op_sub,
ex2_pipedown,
ex2_rm_rdn,
ex2_rm_rmm,
ex2_rm_rne,
ex2_rm_rtz,
ex2_rm_rup,
ex2_single,
ex3_expt,
ex3_pipedown,
ex3_result,
fadd_ctrl_src0,
fadd_ctrl_src1,
fadd_ereg_ex3_forward_r_vld,
fadd_ereg_ex3_result,
fadd_forward_r_vld,
fadd_forward_result,
fadd_mfvr_cmp_result,
forever_cpuclk,
half_expt,
half_result,
pad_yy_icg_scan_en,
vfpu_yy_xx_rm
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input ex1_doub_cmp_result;
input ex1_doub_half_cmp_result;
input ex1_pipe_clk;
input ex1_pipedown;
input ex2_pipedown;
input [4 :0] ex3_expt;
input ex3_pipedown;
input [63:0] ex3_result;
input forever_cpuclk;
input [4 :0] half_expt;
input [15:0] half_result;
input pad_yy_icg_scan_en;
input [2 :0] vfpu_yy_xx_rm;
output ex1_double;
output ex1_op_add;
output ex1_op_cmp;
output ex1_op_feq;
output ex1_op_fle;
output ex1_op_flt;
output ex1_op_fne;
output ex1_op_ford;
output ex1_op_maxnm;
output ex1_op_minnm;
output ex1_op_sub;
output ex1_single;
output ex2_double;
output ex2_op_add;
output ex2_op_cmp;
output ex2_op_fle;
output ex2_op_flt;
output ex2_op_maxnm;
output ex2_op_minnm;
output ex2_op_sub;
output ex2_rm_rdn;
output ex2_rm_rmm;
output ex2_rm_rne;
output ex2_rm_rtz;
output ex2_rm_rup;
output ex2_single;
output [63:0] fadd_ctrl_src0;
output [63:0] fadd_ctrl_src1;
output fadd_ereg_ex3_forward_r_vld;
output [4 :0] fadd_ereg_ex3_result;
output fadd_forward_r_vld;
output [63:0] fadd_forward_result;
output [63:0] fadd_mfvr_cmp_result;
// &Regs; @24
reg [4 :0] fadd_ex2_cmp_op;
reg fadd_ex2_double;
reg [4 :0] fadd_ex2_op;
reg fadd_ex2_rm_rdn;
reg fadd_ex2_rm_rmm;
reg fadd_ex2_rm_rne;
reg fadd_ex2_rm_rtz;
reg fadd_ex2_rm_rup;
reg fadd_ex2_single;
reg fadd_ex3_half;
reg fadd_ex3_op_cmp;
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire [4 :0] ex1_cmp_op;
wire ex1_cmp_result;
wire ex1_doub_cmp_result;
wire ex1_doub_half_cmp_result;
wire ex1_double;
wire [4 :0] ex1_op;
wire ex1_op_add;
wire ex1_op_cmp;
wire ex1_op_feq;
wire ex1_op_fle;
wire ex1_op_flt;
wire ex1_op_fne;
wire ex1_op_ford;
wire ex1_op_maxnm;
wire ex1_op_minnm;
wire ex1_op_sub;
wire ex1_pipe_clk;
wire ex1_pipedown;
wire ex1_rm_rdn;
wire ex1_rm_rmm;
wire ex1_rm_rne;
wire ex1_rm_rtz;
wire ex1_rm_rup;
wire ex1_single;
wire ex2_double;
wire ex2_op_add;
wire ex2_op_cmp;
wire ex2_op_fle;
wire ex2_op_flt;
wire ex2_op_maxnm;
wire ex2_op_minnm;
wire ex2_op_sub;
wire ex2_pipe_clk;
wire ex2_pipe_clk_en;
wire ex2_pipedown;
wire ex2_rm_rdn;
wire ex2_rm_rmm;
wire ex2_rm_rne;
wire ex2_rm_rtz;
wire ex2_rm_rup;
wire ex2_single;
wire [4 :0] ex3_expt;
wire ex3_pipedown;
wire [63:0] ex3_result;
wire [63:0] fadd_ctrl_src0;
wire [63:0] fadd_ctrl_src1;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_ex2_half;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire forever_cpuclk;
wire [19:0] func;
wire [4 :0] half_expt;
wire [15:0] half_result;
wire pad_yy_icg_scan_en;
wire [2 :0] vfalu_rm;
wire [2 :0] vfalu_static_rm;
wire [2 :0] vfpu_yy_xx_rm;
//Global Signals from FCR (set by user)
//Rounding Mode
assign vfalu_static_rm[2:0] = dp_vfalu_ex1_pipex_imm0[2:0];
assign vfalu_rm[2:0] = (vfalu_static_rm[2:0] == 3'b111)
? vfpu_yy_xx_rm[2:0]
: vfalu_static_rm[2:0];
assign ex1_rm_rne = (vfalu_rm[2:0] == 3'b000);
assign ex1_rm_rtz = (vfalu_rm[2:0] == 3'b001);
assign ex1_rm_rdn = (vfalu_rm[2:0] == 3'b010);
assign ex1_rm_rup = (vfalu_rm[2:0] == 3'b011);
assign ex1_rm_rmm = (vfalu_rm[2:0] == 3'b100);
assign fadd_ctrl_src0[63:0] = dp_vfalu_ex1_pipex_srcf0[63:0];
assign fadd_ctrl_src1[63:0] = dp_vfalu_ex1_pipex_srcf1[63:0];
// &Force("bus","dp_vfalu_ex1_pipex_func",19,0); @42
assign func[19:0] = dp_vfalu_ex1_pipex_func[19:0];
assign ex1_double = func[16];
assign ex1_single = func[15];
// &Force("output","ex1_double"); @46
// &Force("output","ex1_single"); @47
//====================Operation Type=======================
assign ex1_op_add = func[12];
assign ex1_op_sub = func[11];
assign ex1_op_cmp = func[10];
assign ex1_op_maxnm = func[9];
assign ex1_op_minnm = func[8];
assign ex1_op[4:0] = {ex1_op_maxnm,
ex1_op_minnm,
ex1_op_cmp,
ex1_op_sub,
ex1_op_add};
// &Force("output","ex1_op_add"); @59
// &Force("output","ex1_op_cmp"); @60
// &Force("output","ex1_op_maxnm"); @61
// &Force("output","ex1_op_minnm"); @62
// &Force("output","ex1_op_sub"); @63
assign ex1_op_feq = ex1_op_cmp && func[0];
assign ex1_op_flt = ex1_op_cmp && func[1];
assign ex1_op_fle = ex1_op_cmp && func[2];
assign ex1_op_ford = ex1_op_cmp && func[3];
assign ex1_op_fne = ex1_op_cmp && func[4];
assign ex1_cmp_op[4:0] = {ex1_op_fne,
ex1_op_ford,
ex1_op_feq,
ex1_op_flt,
ex1_op_fle};
// &Force("output","ex1_op_fne"); @74
// &Force("output","ex1_op_ford"); @75
// &Force("output","ex1_op_feq"); @76
// &Force("output","ex1_op_flt"); @77
// &Force("output","ex1_op_fle"); @78
// handle the f compare result
assign ex1_cmp_result = ex1_double || ex1_single ? ex1_doub_cmp_result
: ex1_doub_half_cmp_result;
assign fadd_mfvr_cmp_result[63:0] = {63'b0,ex1_cmp_result};
//======================Flop to EX2=========================
always @(posedge ex1_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
fadd_ex2_double <= 1'b0;
fadd_ex2_single <= 1'b0;
fadd_ex2_op[4:0] <= 5'b0;
fadd_ex2_cmp_op[4:0] <= 5'b0;
fadd_ex2_rm_rne <= 1'b0;
fadd_ex2_rm_rtz <= 1'b0;
fadd_ex2_rm_rdn <= 1'b0;
fadd_ex2_rm_rup <= 1'b0;
fadd_ex2_rm_rmm <= 1'b0;
end
else if(ex1_pipedown)
begin
fadd_ex2_double <= ex1_double;
fadd_ex2_single <= ex1_single;
fadd_ex2_op[4:0] <= ex1_op[4:0];
fadd_ex2_cmp_op[4:0] <= ex1_cmp_op[4:0];
fadd_ex2_rm_rne <= ex1_rm_rne;
fadd_ex2_rm_rtz <= ex1_rm_rtz;
fadd_ex2_rm_rdn <= ex1_rm_rdn;
fadd_ex2_rm_rup <= ex1_rm_rup;
fadd_ex2_rm_rmm <= ex1_rm_rmm;
end
else
begin
fadd_ex2_double <= fadd_ex2_double;
fadd_ex2_single <= fadd_ex2_single;
fadd_ex2_op[4:0] <= fadd_ex2_op[4:0];
fadd_ex2_cmp_op[4:0] <= fadd_ex2_cmp_op[4:0];
fadd_ex2_rm_rne <= fadd_ex2_rm_rne;
fadd_ex2_rm_rtz <= fadd_ex2_rm_rtz;
fadd_ex2_rm_rdn <= fadd_ex2_rm_rdn;
fadd_ex2_rm_rup <= fadd_ex2_rm_rup;
fadd_ex2_rm_rmm <= fadd_ex2_rm_rmm;
end
end
//EX2 Signal Prepare
assign ex2_double = fadd_ex2_double;
assign ex2_single = fadd_ex2_single;
assign fadd_ex2_half = !fadd_ex2_double && !fadd_ex2_single;
// &Force("output","ex2_double"); @132
assign ex2_op_maxnm = fadd_ex2_op[4];
assign ex2_op_minnm = fadd_ex2_op[3];
assign ex2_op_cmp = fadd_ex2_op[2];
assign ex2_op_sub = fadd_ex2_op[1];
assign ex2_op_add = fadd_ex2_op[0];
// &Force("output","ex2_op_cmp"); @138
//assign ex2_op_feq = fadd_ex2_cmp_op[2];
assign ex2_op_flt = fadd_ex2_cmp_op[1];
assign ex2_op_fle = fadd_ex2_cmp_op[0];
//assign ex2_op_ford = fadd_ex2_cmp_op[3];
//assign ex2_op_fne = fadd_ex2_cmp_op[4];
assign ex2_rm_rne = fadd_ex2_rm_rne;
assign ex2_rm_rtz = fadd_ex2_rm_rtz;
assign ex2_rm_rdn = fadd_ex2_rm_rdn;
assign ex2_rm_rup = fadd_ex2_rm_rup;
assign ex2_rm_rmm = fadd_ex2_rm_rmm;
// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @150
gated_clk_cell x_ex2_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @151
// .clk_out (ex2_pipe_clk),//Out Clock @152
// .external_en (1'b0), @153
// .global_en (cp0_yy_clk_en), @154
// .local_en (ex2_pipe_clk_en),//Local Condition @155
// .module_en (cp0_vfpu_icg_en) @156
// ); @157
assign ex2_pipe_clk_en = ex2_pipedown;
always @(posedge ex2_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
fadd_ex3_half <= 1'b0;
fadd_ex3_op_cmp <= 1'b0;
end
else if(ex2_pipedown)
begin
fadd_ex3_half <= fadd_ex2_half;
fadd_ex3_op_cmp <= ex2_op_cmp;
end
else
begin
fadd_ex3_half <= fadd_ex3_half;
fadd_ex3_op_cmp <= fadd_ex3_op_cmp;
end
end
assign fadd_forward_result[63:0] = fadd_ex3_half ? {{48{!fadd_ex3_op_cmp}},half_result[15:0]} : ex3_result[63:0];
assign fadd_ereg_ex3_result[4:0] = fadd_ex3_half ? half_expt[4:0] : ex3_expt[4:0];
assign fadd_ereg_ex3_forward_r_vld = ex3_pipedown;
assign fadd_forward_r_vld = ex3_pipedown;
//assign fadd_vreg_ex4_forward_r_vld = ex4_inst_vld;
// &ModuleEnd; @184
endmodule |
module ct_fadd_close_s0_d(
close_adder0,
close_adder1,
close_eq,
close_op_chg,
close_sum_a_b,
close_sum_b_a,
ff1_pred,
ff1_pred_onehot
);
// &Ports; @23
input [52:0] close_adder0;
input [52:0] close_adder1;
output close_eq;
output close_op_chg;
output [52:0] close_sum_a_b;
output [52:0] close_sum_b_a;
output [5 :0] ff1_pred;
output [52:0] ff1_pred_onehot;
// &Regs; @24
reg [5 :0] ff1_pred_50_0;
reg [52:0] ff1_pred_onehot_50_0;
// &Wires; @25
wire [52:0] close_adder0;
wire [52:0] close_adder1;
wire close_eq;
wire [52:0] close_ff1_a;
wire [52:0] close_ff1_b;
wire [52:0] close_ff1_c;
wire [52:0] close_ff1_f;
wire [52:0] close_ff1_g;
wire [52:0] close_ff1_t;
wire [52:0] close_ff1_z;
wire close_op_chg;
wire [53:0] close_sum0;
wire [53:0] close_sum1;
wire [52:0] close_sum_a_b;
wire [52:0] close_sum_b_a;
wire [5 :0] ff1_pred;
wire [5 :0] ff1_pred_52_51;
wire [5 :0] ff1_pred_nz;
wire [52:0] ff1_pred_nz_onehot;
wire [52:0] ff1_pred_onehot;
wire [52:0] ff1_pred_onehot_52_51;
// &Force("nonport","close_sum1"); @26
// &Force("nonport","close_sum0"); @27
//close_sum0 for F0-F1
assign close_sum0[53:0] = {1'b0,close_adder0[52:0]}
- {1'b0,close_adder1[52:0]};
assign close_sum1[53:0] = {1'b0,close_adder1[52:0]}
- {1'b0,close_adder0[52:0]};
//notice that this situation, there is no need for m1, because the round
// m1 will never happen, there is no tail number used for rounding,
// here, it is different with the previous design
//close_sum select, keep sum not negative
//assign close_sum[52:0] = (close_sum0[53])
// ? close_sum1[52:0]
// : close_sum0[52:0];
assign close_sum_a_b[52:0] = close_sum0[52:0];
assign close_sum_b_a[52:0] = close_sum1[52:0];
assign close_op_chg = close_sum0[53];
assign close_eq = !close_sum0[53] && !close_sum1[53];
//FF1 Logic of Close Path S0
//If predict first 1 set at r[n]
//Actual first 1 may set at r[n+1] or r[n]
//A and B are to oprand
assign close_ff1_a[52:0] = close_adder0[52:0];
assign close_ff1_b[52:0] = close_adder1[52:0];
//C = B && act_add || ~B && act_sub
assign close_ff1_c[52:0] = ~close_ff1_b[52:0];
//T = A^C G=A&C Z=(~A)&(~C)
assign close_ff1_t[52:0] = close_ff1_a[52:0] ^ close_ff1_c[52:0];
assign close_ff1_g[52:0] = close_ff1_a[52:0] & close_ff1_c[52:0];
assign close_ff1_z[52:0] = (~close_ff1_a[52:0]) & (~close_ff1_c[52:0]);
//F :
//fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
//f0 = t1(g0En+z0) + (~t1)(z0En+g0)
//fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
assign close_ff1_f[52] = ( close_ff1_g[52] & (~close_ff1_z[51])) |
( close_ff1_z[52] & (~close_ff1_g[51]));
assign close_ff1_f[0] = (( close_ff1_t[1]) & (close_ff1_g[0] | close_ff1_z[0])) |
((~close_ff1_t[1]) & (close_ff1_z[0] | close_ff1_g[0]));
assign close_ff1_f[51:1] = (( close_ff1_t[52:2]) & ((close_ff1_g[51:1] & (~close_ff1_z[50:0])) |
( close_ff1_z[51:1] & (~close_ff1_g[50:0])))) |
((~close_ff1_t[52:2]) & ((close_ff1_g[51:1] & (~close_ff1_g[50:0])) |
( close_ff1_z[51:1] & (~close_ff1_z[50:0]))));
// &CombBeg; @73
always @( close_ff1_f[50:0])
begin
casez(close_ff1_f[50:0])
// 53'b1????_????????_????????_????????_????????_????????_???????? :
// ff1_pred_onehot_50_0[52:0] = 53'b10000_00000000_00000000_00000000_00000000_00000000_00000000;
// 53'b01???_????????_????????_????????_????????_????????_???????? :
// ff1_pred_onehot_50_0[52:0] = 53'b01000_00000000_00000000_00000000_00000000_00000000_00000000;
51'b1??_????????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00100_00000000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd2;
end
51'b01?_????????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00010_00000000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd3;
end
51'b001_????????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00001_00000000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd4;
end
51'b000_1???????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_10000000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd5;
end
51'b000_01??????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_01000000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd6;
end
51'b000_001?????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00100000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd7;
end
51'b000_0001????_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00010000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd8;
end
51'b000_00001???_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00001000_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd9;
end
51'b000_000001??_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000100_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd10;
end
51'b000_0000001?_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000010_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd11;
end
51'b000_00000001_????????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000001_00000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd12;
end
51'b000_00000000_1???????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_10000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd13;
end
51'b000_00000000_01??????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_01000000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd14;
end
51'b000_00000000_001?????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00100000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd15;
end
51'b000_00000000_0001????_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00010000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd16;
end
51'b000_00000000_00001???_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00001000_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd17;
end
51'b000_00000000_000001??_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000100_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd18;
end
51'b000_00000000_0000001?_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000010_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd19;
end
51'b000_00000000_00000001_????????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000001_00000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd20;
end
51'b000_00000000_00000000_1???????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_10000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd21;
end
51'b000_00000000_00000000_01??????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_01000000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd22;
end
51'b000_00000000_00000000_001?????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00100000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd23;
end
51'b000_00000000_00000000_0001????_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00010000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd24;
end
51'b000_00000000_00000000_00001???_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00001000_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd25;
end
51'b000_00000000_00000000_000001??_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000100_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd26;
end
51'b000_00000000_00000000_0000001?_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000010_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd27;
end
51'b000_00000000_00000000_00000001_????????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000001_00000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd28;
end
51'b000_00000000_00000000_00000000_1???????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_10000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd29;
end
51'b000_00000000_00000000_00000000_01??????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_01000000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd30;
end
51'b000_00000000_00000000_00000000_001?????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00100000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd31;
end
51'b000_00000000_00000000_00000000_0001????_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00010000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd32;
end
51'b000_00000000_00000000_00000000_00001???_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00001000_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd33;
end
51'b000_00000000_00000000_00000000_000001??_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000100_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd34;
end
51'b000_00000000_00000000_00000000_0000001?_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000010_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd35;
end
51'b000_00000000_00000000_00000000_00000001_????????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000001_00000000_00000000;
ff1_pred_50_0[5:0] = 6'd36;
end
51'b000_00000000_00000000_00000000_00000000_1???????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_10000000_00000000;
ff1_pred_50_0[5:0] = 6'd37;
end
51'b000_00000000_00000000_00000000_00000000_01??????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_01000000_00000000;
ff1_pred_50_0[5:0] = 6'd38;
end
51'b000_00000000_00000000_00000000_00000000_001?????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00100000_00000000;
ff1_pred_50_0[5:0] = 6'd39;
end
51'b000_00000000_00000000_00000000_00000000_0001????_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00010000_00000000;
ff1_pred_50_0[5:0] = 6'd40;
end
51'b000_00000000_00000000_00000000_00000000_00001???_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00001000_00000000;
ff1_pred_50_0[5:0] = 6'd41;
end
51'b000_00000000_00000000_00000000_00000000_000001??_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000100_00000000;
ff1_pred_50_0[5:0] = 6'd42;
end
51'b000_00000000_00000000_00000000_00000000_0000001?_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000010_00000000;
ff1_pred_50_0[5:0] = 6'd43;
end
51'b000_00000000_00000000_00000000_00000000_00000001_???????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000001_00000000;
ff1_pred_50_0[5:0] = 6'd44;
end
51'b000_00000000_00000000_00000000_00000000_00000000_1??????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_10000000;
ff1_pred_50_0[5:0] = 6'd45;
end
51'b000_00000000_00000000_00000000_00000000_00000000_01?????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_01000000;
ff1_pred_50_0[5:0] = 6'd46;
end
51'b000_00000000_00000000_00000000_00000000_00000000_001????? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00100000;
ff1_pred_50_0[5:0] = 6'd47;
end
51'b000_00000000_00000000_00000000_00000000_00000000_0001???? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00010000;
ff1_pred_50_0[5:0] = 6'd48;
end
51'b000_00000000_00000000_00000000_00000000_00000000_00001??? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00001000;
ff1_pred_50_0[5:0] = 6'd49;
end
51'b000_00000000_00000000_00000000_00000000_00000000_000001?? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00000100;
ff1_pred_50_0[5:0] = 6'd50;
end
51'b000_00000000_00000000_00000000_00000000_00000000_0000001? : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00000010;
ff1_pred_50_0[5:0] = 6'd51;
end
51'b000_00000000_00000000_00000000_00000000_00000000_00000001 : begin
ff1_pred_onehot_50_0[52:0] = 53'b00000_00000000_00000000_00000000_00000000_00000000_00000001;
ff1_pred_50_0[5:0] = 6'd52;
end
default : begin
ff1_pred_onehot_50_0[52:0] = {53{1'bx}};
ff1_pred_50_0[5:0] = {6{1'bx}};
end
endcase
// &CombEnd; @288
end
assign ff1_pred_onehot_52_51[52:0] = (close_ff1_f[52])
? 53'b10000_00000000_00000000_00000000_00000000_00000000_00000000
: 53'b01000_00000000_00000000_00000000_00000000_00000000_00000000;
assign ff1_pred_52_51[5:0] = (close_ff1_f[52])
? 6'b0
: 6'b1;
assign ff1_pred_nz_onehot[52:0] = (|close_ff1_f[52:51])
? ff1_pred_onehot_52_51[52:0]
: ff1_pred_onehot_50_0[52:0];
assign ff1_pred_nz[5:0] = (|close_ff1_f[52:51])
? ff1_pred_52_51[5:0]
: ff1_pred_50_0[5:0];
assign ff1_pred_onehot[52:0] = ff1_pred_nz_onehot[52:0];
assign ff1_pred[5:0] = ff1_pred_nz[5:0];
// &ModuleEnd; @307
endmodule |
module ct_fspu_double(
ex1_op_fmvvf,
ex1_op_fsgnj,
ex1_op_fsgnjn,
ex1_op_fsgnjx,
ex1_oper0,
ex1_oper1,
ex1_result,
mtvr_src0,
result_fclass,
result_fmfvr
);
// &Ports; @20
input ex1_op_fmvvf;
input ex1_op_fsgnj;
input ex1_op_fsgnjn;
input ex1_op_fsgnjx;
input [63:0] ex1_oper0;
input [63:0] ex1_oper1;
input [63:0] mtvr_src0;
output [63:0] ex1_result;
output [63:0] result_fclass;
output [63:0] result_fmfvr;
// &Regs; @21
// &Wires; @22
wire ex1_doub_expnt0_max;
wire ex1_doub_expnt0_zero;
wire ex1_doub_frac0_all0;
wire ex1_doub_frac0_msb;
wire ex1_doub_neg_dn;
wire ex1_doub_neg_inf;
wire ex1_doub_neg_nm;
wire ex1_doub_neg_zero;
wire ex1_doub_op0_sign;
wire ex1_doub_pos_dn;
wire ex1_doub_pos_inf;
wire ex1_doub_pos_nm;
wire ex1_doub_pos_zero;
wire ex1_doub_qnan;
wire ex1_doub_snan;
wire ex1_op_fmvvf;
wire ex1_op_fsgnj;
wire ex1_op_fsgnjn;
wire ex1_op_fsgnjx;
wire [63:0] ex1_oper0;
wire [63:0] ex1_oper1;
wire [63:0] ex1_result;
wire [63:0] mtvr_src0;
wire [63:0] result_fclass;
wire [63:0] result_fclassd;
wire [63:0] result_fmfvr;
wire [63:0] result_fmfvrd;
wire [63:0] result_fmtvrd;
wire [63:0] result_fsgnjd;
wire [63:0] result_fsgnjnd;
wire [63:0] result_fsgnjxd;
// &Force("bus","ex1_oper1",63,0); @23
//Sign bit prepare
assign ex1_doub_op0_sign = ex1_oper0[63];
//exponent max
assign ex1_doub_expnt0_max = &ex1_oper0[62:52];
//exponent zero
assign ex1_doub_expnt0_zero = ~|ex1_oper0[62:52];
//fraction zero
assign ex1_doub_frac0_all0 = ~|ex1_oper0[51:0];
//freaction msb
assign ex1_doub_frac0_msb = ex1_oper0[51];
//FCLASS.D
assign ex1_doub_neg_inf = ex1_doub_op0_sign && ex1_doub_expnt0_max && ex1_doub_frac0_all0;
assign ex1_doub_neg_nm = ex1_doub_op0_sign && !ex1_doub_expnt0_max && !ex1_doub_expnt0_zero;
assign ex1_doub_neg_dn = ex1_doub_op0_sign && ex1_doub_expnt0_zero && !ex1_doub_frac0_all0;
assign ex1_doub_neg_zero = ex1_doub_op0_sign && ex1_doub_expnt0_zero && ex1_doub_frac0_all0;
assign ex1_doub_pos_zero = !ex1_doub_op0_sign && ex1_doub_expnt0_zero && ex1_doub_frac0_all0;
assign ex1_doub_pos_dn = !ex1_doub_op0_sign && ex1_doub_expnt0_zero && !ex1_doub_frac0_all0;
assign ex1_doub_pos_nm = !ex1_doub_op0_sign && !ex1_doub_expnt0_max && !ex1_doub_expnt0_zero;
assign ex1_doub_pos_inf = !ex1_doub_op0_sign && ex1_doub_expnt0_max && ex1_doub_frac0_all0;
assign ex1_doub_snan = ex1_doub_expnt0_max && !ex1_doub_frac0_all0 && !ex1_doub_frac0_msb;
assign ex1_doub_qnan = ex1_doub_expnt0_max && ex1_doub_frac0_msb;
assign result_fclassd[63:0] = {
54'b0,
ex1_doub_qnan,
ex1_doub_snan,
ex1_doub_pos_inf,
ex1_doub_pos_nm,
ex1_doub_pos_dn,
ex1_doub_pos_zero,
ex1_doub_neg_zero,
ex1_doub_neg_dn,
ex1_doub_neg_nm,
ex1_doub_neg_inf
};
//FSGNJX.D
assign result_fsgnjxd[63:0] = {ex1_oper0[63]^ex1_oper1[63],ex1_oper0[62:0]};
//FSGNJN.D:
assign result_fsgnjnd[63:0] = {~ex1_oper1[63],ex1_oper0[62:0]};
//FSGNJ.D
assign result_fsgnjd[63:0] = {ex1_oper1[63],ex1_oper0[62:0]};
//FMV.D.X
assign result_fmtvrd[63:0] = mtvr_src0[63:0];
//FMV.X.D
assign result_fmfvrd[63:0] = ex1_oper0[63:0];
assign result_fmfvr[63:0] = result_fmfvrd[63:0];
assign result_fclass[63:0] = result_fclassd[63:0];
//Final Result
assign ex1_result[63:0] = {64{ex1_op_fmvvf}} & result_fmtvrd[63:0] |
{64{ex1_op_fsgnj}} & result_fsgnjd[63:0] |
{64{ex1_op_fsgnjn}} & result_fsgnjnd[63:0] |
{64{ex1_op_fsgnjx}} & result_fsgnjxd[63:0];
// &ModuleEnd; @95
endmodule |
module ct_fadd_onehot_sel_h(
data_in,
onehot,
result
);
// &Ports; @23
input [11:0] data_in;
input [11:0] onehot;
output [11:0] result;
// &Regs; @24
reg [11:0] result_h;
// &Wires; @25
wire [11:0] data_in;
wire [11:0] onehot;
wire [11:0] result;
// &Force("bus","data_in",11,0); @27
// &CombBeg; @28
always @( onehot[11:0]
or data_in[11:0])
begin
case(onehot[11:0])
12'h800 : result_h[11:0] = data_in[11:0];
12'h400 : result_h[11:0] = {data_in[10:0],1'b0};
12'h200 : result_h[11:0] = {data_in[9:0],2'b0};
12'h100 : result_h[11:0] = {data_in[8:0],2'b0,1'b0};
12'h080 : result_h[11:0] = {data_in[7:0],2'b0,2'b0};
12'h040 : result_h[11:0] = {data_in[6:0],2'b0,3'b0};
12'h020 : result_h[11:0] = {data_in[5:0],2'b0,4'b0};
12'h010 : result_h[11:0] = {data_in[4:0],2'b0,5'b0};
12'h008 : result_h[11:0] = {data_in[3:0],2'b0,6'b0};
12'h004 : result_h[11:0] = {data_in[2:0],2'b0,7'b0};
12'h002 : result_h[11:0] = {data_in[1:0],2'b0,8'b0};
12'h001 : result_h[11:0] = {data_in[0],2'b0,9'b0};
12'h000 : result_h[11:0] = 12'b0;
default : result_h[11:0] = {12{1'bx}};
endcase
// &CombEnd; @45
end
assign result[11:0] = result_h[11:0];
// &ModuleEnd; @48
endmodule |
module ct_vfalu_dp_pipe6(
dp_vfalu_ex1_pipex_sel,
fadd_ereg_ex3_forward_r_vld,
fadd_ereg_ex3_result,
fadd_forward_r_vld,
fadd_forward_result,
fadd_mfvr_cmp_result,
fspu_forward_r_vld,
fspu_forward_result,
fspu_mfvr_data,
pipex_dp_ex1_vfalu_mfvr_data,
pipex_dp_ex3_vfalu_ereg_data,
pipex_dp_ex3_vfalu_freg_data
);
// &Ports; @23
input [2 :0] dp_vfalu_ex1_pipex_sel;
input fadd_ereg_ex3_forward_r_vld;
input [4 :0] fadd_ereg_ex3_result;
input fadd_forward_r_vld;
input [63:0] fadd_forward_result;
input [63:0] fadd_mfvr_cmp_result;
input fspu_forward_r_vld;
input [63:0] fspu_forward_result;
input [63:0] fspu_mfvr_data;
output [63:0] pipex_dp_ex1_vfalu_mfvr_data;
output [4 :0] pipex_dp_ex3_vfalu_ereg_data;
output [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Regs; @24
reg [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Wires; @25
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire [63:0] pipex_dp_ex1_vfalu_mfvr_data;
wire [4 :0] pipex_dp_ex3_vfalu_ereg_data;
//assign pipex_dp_ex3_vfalu_expt_vec[4:0] = 5'd30;
// &Force("output","pipex_dp_ex3_vfalu_ereg_data"); @28
assign pipex_dp_ex3_vfalu_ereg_data[4:0] = {5{fadd_ereg_ex3_forward_r_vld}} & fadd_ereg_ex3_result[4:0];
assign pipex_dp_ex1_vfalu_mfvr_data[63:0] = {64{dp_vfalu_ex1_pipex_sel[1]}} & fadd_mfvr_cmp_result[63:0] |
{64{dp_vfalu_ex1_pipex_sel[0]}} & fspu_mfvr_data[63:0];
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0); @32
// &CombBeg; @34
// &CombEnd; @40
// &CombBeg; @42
// &CombEnd; @48
// &CombBeg; @56
always @( fspu_forward_result[63:0]
or fspu_forward_r_vld
or fadd_forward_r_vld
or fadd_forward_result[63:0])
begin
case({fadd_forward_r_vld,fspu_forward_r_vld})
2'b10 : pipex_dp_ex3_vfalu_freg_data[63:0] = fadd_forward_result[63:0];
2'b01 : pipex_dp_ex3_vfalu_freg_data[63:0] = fspu_forward_result[63:0];
default : pipex_dp_ex3_vfalu_freg_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @62
end
// &ModuleEnd; @65
endmodule |
module ct_fcnvt_dtoh_sh(
dtos_sh_cnt,
dtos_sh_f_v,
dtos_sh_f_x,
dtos_sh_src
);
// &Ports; @17
input [10:0] dtos_sh_cnt;
input [51:0] dtos_sh_src;
output [10:0] dtos_sh_f_v;
output [53:0] dtos_sh_f_x;
// &Regs; @18
reg [10:0] dtos_sh_f_v;
reg [53:0] dtos_sh_f_x;
// &Wires; @19
wire [10:0] dtos_sh_cnt;
wire [51:0] dtos_sh_src;
// &CombBeg; @22
always @( dtos_sh_cnt[10:0]
or dtos_sh_src[51:0])
begin
case(dtos_sh_cnt[10:0])
11'h3f0: begin //-15
dtos_sh_f_v[10:0] = {2'b1,dtos_sh_src[51:43]};
dtos_sh_f_x[53:0] = {dtos_sh_src[42:0],11'b0};
end
11'h3ef: begin //-16
dtos_sh_f_v[10:0] = {3'b1,dtos_sh_src[51:44]};
dtos_sh_f_x[53:0] = {dtos_sh_src[43:0],10'b0};
end
11'h3ee: begin //-17
dtos_sh_f_v[10:0] = {4'b1,dtos_sh_src[51:45]};
dtos_sh_f_x[53:0] = {dtos_sh_src[44:0],9'b0};
end
11'h3ed: begin //-18
dtos_sh_f_v[10:0] = {5'b1,dtos_sh_src[51:46]};
dtos_sh_f_x[53:0] = {dtos_sh_src[45:0],8'b0};
end
11'h3ec: begin //-19
dtos_sh_f_v[10:0] = {6'b1,dtos_sh_src[51:47]};
dtos_sh_f_x[53:0] = {dtos_sh_src[46:0],7'b0};
end
11'h3eb: begin //-20
dtos_sh_f_v[10:0] = {7'b1,dtos_sh_src[51:48]};
dtos_sh_f_x[53:0] = {dtos_sh_src[47:0],6'b0};
end
11'h3ea: begin //-21
dtos_sh_f_v[10:0] = {8'b1,dtos_sh_src[51:49]};
dtos_sh_f_x[53:0] = {dtos_sh_src[48:0],5'b0};
end
11'h3e9: begin //-22
dtos_sh_f_v[10:0] = {9'b1,dtos_sh_src[51:50]};
dtos_sh_f_x[53:0] = {dtos_sh_src[49:0],4'b0};
end
11'h3e8: begin //-135
dtos_sh_f_v[10:0] = {10'b1,dtos_sh_src[51]};
dtos_sh_f_x[53:0] = {dtos_sh_src[50:0],3'b0};
end
11'h3e7: begin //-136
dtos_sh_f_v[10:0] = {11'b1};
dtos_sh_f_x[53:0] = {dtos_sh_src[51:0],2'b0};
end
11'h3e6: begin //-137
dtos_sh_f_v[10:0] = 11'b0;
dtos_sh_f_x[53:0] = {1'b1,dtos_sh_src[51:0],1'b0};
end
11'h3e5: begin //-138
dtos_sh_f_v[10:0] = 11'b0;
dtos_sh_f_x[53:0] = {2'b1,dtos_sh_src[51:0]};
end
default: begin
dtos_sh_f_v[10:0] = 11'b0;
dtos_sh_f_x[53:0] = {3'b1,51'b0};
end
endcase
// &CombEnd; @77
end
// &ModuleEnd; @80
endmodule |
module ct_fadd_top(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_sel,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
fadd_ereg_ex3_forward_r_vld,
fadd_ereg_ex3_result,
fadd_forward_r_vld,
fadd_forward_result,
fadd_mfvr_cmp_result,
forever_cpuclk,
pad_yy_icg_scan_en,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @22
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [2 :0] dp_vfalu_ex1_pipex_sel;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output fadd_ereg_ex3_forward_r_vld;
output [4 :0] fadd_ereg_ex3_result;
output fadd_forward_r_vld;
output [63:0] fadd_forward_result;
output [63:0] fadd_mfvr_cmp_result;
// &Regs; @23
// &Wires; @24
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire ex1_doub_cmp_result;
wire ex1_doub_half_cmp_result;
wire ex1_double;
wire ex1_op_add;
wire ex1_op_cmp;
wire ex1_op_feq;
wire ex1_op_fle;
wire ex1_op_flt;
wire ex1_op_fne;
wire ex1_op_ford;
wire ex1_op_maxnm;
wire ex1_op_minnm;
wire ex1_op_sub;
wire ex1_pipe_clk;
wire ex1_pipedown;
wire ex1_single;
wire ex2_double;
wire ex2_op_add;
wire ex2_op_cmp;
wire ex2_op_fle;
wire ex2_op_flt;
wire ex2_op_maxnm;
wire ex2_op_minnm;
wire ex2_op_sub;
wire ex2_pipedown;
wire ex2_rm_rdn;
wire ex2_rm_rmm;
wire ex2_rm_rne;
wire ex2_rm_rtz;
wire ex2_rm_rup;
wire ex2_single;
wire [4 :0] ex3_expt;
wire ex3_pipedown;
wire [63:0] ex3_result;
wire [63:0] fadd_ctrl_src0;
wire [63:0] fadd_ctrl_src1;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire forever_cpuclk;
wire [4 :0] half_expt;
wire [15:0] half_result;
wire pad_yy_icg_scan_en;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Instance("ct_fadd_ctrl"); @27
// &Instance("ct_fadd_dp"); @28
// &ConnRule(s/ex3/set0_doub_ex3/); @30
// &ConnRule(s/ex1_cmp_result/set0_doub_ex1_cmp_result/); @31
// &ConnRule(s/ex2_result/set0_doub_ex2_result/); @32
// &ConnRule(s/fadd_ctrl_/dp_set0_doub_/); @33
// &ConnRule(s/ex2_src/set0_doub_ex2_src/); @34
// &ConnRule(s/ex2_r_/set0_doub_ex2_r_/); @35
// &Instance("ct_fadd_double_dp","x_set0_ct_fadd_double_dp"); @36
// &Connect(.ex2_double(set0_double_ex2_double)); @37
// &Connect(.ex2_single(set0_double_ex2_single)); @38
// &Connect(.ex1_double(fadd_set0_double)); @39
// &Connect(.ex1_single(fadd_set0_single)); @40
// &ConnRule(s/ex3/set0_doub_half_ex3/); @43
// &ConnRule(s/ex1_cmp_result/set0_doub_half_ex1_cmp_result/); @44
// &ConnRule(s/ex2_result/set0_doub_half_ex2_result/); @45
// &ConnRule(s/fadd_ctrl_/dp_set0_doub_half_/); @46
// &ConnRule(s/ex2_src/set0_doub_half_ex2_src/); @47
// &ConnRule(s/ex2_r_/set0_doub_half_ex2_r_/); @48
// &Instance("ct_fadd_half_dp", "x_set0_ct_fadd_doub_half_dp"); @49
// &ConnRule(s/ex3/set0_half0_ex3/); @53
// &ConnRule(s/ex1_cmp_result/set0_half0_ex1_cmp_result/); @54
// &ConnRule(s/ex2_result/set0_half0_ex2_result/); @55
// &ConnRule(s/fadd_ctrl_/dp_set0_half0_/); @56
// &ConnRule(s/ex2_src/set0_half0_ex2_src/); @57
// &ConnRule(s/ex2_r_/set0_half0_ex2_r_/); @58
// &Instance("ct_fadd_half_dp", "x_set0_ct_fadd_half0_dp"); @59
// &Connect(.ex1_scalar(1'b0)); @60
// &ConnRule(s/ex3/set0_sing_ex3/); @62
// &ConnRule(s/ex1_cmp_result/set0_sing_ex1_cmp_result/); @63
// &ConnRule(s/ex2_result/set0_sing_ex2_result/); @64
// &ConnRule(s/fadd_ctrl_/dp_set0_sing_/); @65
// &ConnRule(s/ex2_src/set0_sing_ex2_src/); @66
// &ConnRule(s/ex2_r_/set0_sing_ex2_r_/); @67
// &Instance("ct_fadd_single_dp","x_set0_ct_fadd_single_dp"); @68
// &Connect(.ex2_single(set0_single_ex2_single)); @69
// &ConnRule(s/ex3/set0_half1_ex3/); @72
// &ConnRule(s/ex1_cmp_result/set0_half1_ex1_cmp_result/); @73
// &ConnRule(s/ex2_result/set0_half1_ex2_result/); @74
// &ConnRule(s/fadd_ctrl_/dp_set0_half1_/); @75
// &ConnRule(s/ex2_src/set0_half1_ex2_src/); @76
// &ConnRule(s/ex2_r_/set0_half1_ex2_r_/); @77
// &Instance("ct_fadd_half_dp", "x_set0_ct_fadd_half1_dp"); @78
// &Connect(.ex1_scalar(1'b0)); @79
// &ConnRule(s/ex3/set1_doub_ex3/); @81
// &ConnRule(s/ex1_cmp_result/set1_doub_ex1_cmp_result/); @82
// &ConnRule(s/ex2_result/set1_doub_ex2_result/); @83
// &ConnRule(s/fadd_ctrl_/dp_set1_doub_/); @84
// &ConnRule(s/ex2_src/set1_doub_ex2_src/); @85
// &ConnRule(s/ex2_r_/set1_doub_ex2_r_/); @86
// &Instance("ct_fadd_double_dp","x_set1_ct_fadd_double_dp"); @87
// &Connect(.ex2_double(set1_double_ex2_double)); @88
// &Connect(.ex2_single(set1_double_ex2_single)); @89
// &Connect(.ex1_double(fadd_set1_double)); @90
// &Connect(.ex1_single(fadd_set1_single)); @91
// &ConnRule(s/ex3/set1_doub_half_ex3/); @93
// &ConnRule(s/ex1_cmp_result/set1_doub_half_ex1_cmp_result/); @94
// &ConnRule(s/ex2_result/set1_doub_half_ex2_result/); @95
// &ConnRule(s/fadd_ctrl_/dp_set1_doub_half_/); @96
// &ConnRule(s/ex2_src/set1_doub_half_ex2_src/); @97
// &ConnRule(s/ex2_r_/set1_doub_half_ex2_r_/); @98
// &Instance("ct_fadd_half_dp", "x_set1_ct_fadd_doub_half_dp"); @99
// &ConnRule(s/ex3/set1_half0_ex3/); @101
// &ConnRule(s/ex1_cmp_result/set1_half0_ex1_cmp_result/); @102
// &ConnRule(s/ex2_result/set1_half0_ex2_result/); @103
// &ConnRule(s/fadd_ctrl_/dp_set1_half0_/); @104
// &ConnRule(s/ex2_src/set1_half0_ex2_src/); @105
// &ConnRule(s/ex2_r_/set1_half0_ex2_r_/); @106
// &Instance("ct_fadd_half_dp", "x_set1_ct_fadd_half0_dp"); @107
// &Connect(.ex1_scalar(1'b0)); @108
// &ConnRule(s/ex3/set1_sing_ex3/); @110
// &ConnRule(s/ex1_cmp_result/set1_sing_ex1_cmp_result/); @111
// &ConnRule(s/ex2_result/set1_sing_ex2_result/); @112
// &ConnRule(s/fadd_ctrl_/dp_set1_sing_/); @113
// &ConnRule(s/ex2_src/set1_sing_ex2_src/); @114
// &ConnRule(s/ex2_r_/set1_sing_ex2_r_/); @115
// &Instance("ct_fadd_single_dp","x_set1_ct_fadd_single_dp"); @116
// &Connect(.ex2_single(set1_single_ex2_single)); @117
// &ConnRule(s/ex3/set1_half1_ex3/); @119
// &ConnRule(s/ex1_cmp_result/set1_half1_ex1_cmp_result/); @120
// &ConnRule(s/ex2_result/set1_half1_ex2_result/); @121
// &ConnRule(s/fadd_ctrl_/dp_set1_half1_/); @122
// &ConnRule(s/ex2_src/set1_half1_ex2_src/); @123
// &ConnRule(s/ex2_r_/set1_half1_ex2_r_/); @124
// &Instance("ct_fadd_half_dp", "x_set1_ct_fadd_half1_dp"); @125
// &Connect(.ex1_scalar(1'b0)); @126
// &Force("nonport","set1_half1_ex1_cmp_result"); @128
// &Force("nonport","set1_doub_half_ex1_cmp_result"); @129
// &Force("nonport","set1_sing_ex1_cmp_result"); @130
// &Force("nonport","set1_half0_ex1_cmp_result"); @131
// &Force("nonport","set1_doub_ex1_cmp_result"); @132
// &Force("nonport","set0_half1_ex1_cmp_result"); @134
// &Force("nonport","set0_doub_half_ex1_cmp_result"); @135
// &Force("nonport","set0_sing_ex1_cmp_result"); @136
// &Force("nonport","set0_half0_ex1_cmp_result"); @137
// &Force("nonport","set0_doub_ex1_cmp_result"); @138
// &Instance("ct_fadd_ctrl"); @140
ct_fadd_ctrl x_ct_fadd_ctrl (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel),
.ex1_pipe_clk (ex1_pipe_clk ),
.ex1_pipedown (ex1_pipedown ),
.ex2_pipedown (ex2_pipedown ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_fadd_scalar_dp"); @141
ct_fadd_scalar_dp x_ct_fadd_scalar_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_imm0 (dp_vfalu_ex1_pipex_imm0 ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.ex1_doub_cmp_result (ex1_doub_cmp_result ),
.ex1_doub_half_cmp_result (ex1_doub_half_cmp_result ),
.ex1_double (ex1_double ),
.ex1_op_add (ex1_op_add ),
.ex1_op_cmp (ex1_op_cmp ),
.ex1_op_feq (ex1_op_feq ),
.ex1_op_fle (ex1_op_fle ),
.ex1_op_flt (ex1_op_flt ),
.ex1_op_fne (ex1_op_fne ),
.ex1_op_ford (ex1_op_ford ),
.ex1_op_maxnm (ex1_op_maxnm ),
.ex1_op_minnm (ex1_op_minnm ),
.ex1_op_sub (ex1_op_sub ),
.ex1_pipe_clk (ex1_pipe_clk ),
.ex1_pipedown (ex1_pipedown ),
.ex1_single (ex1_single ),
.ex2_double (ex2_double ),
.ex2_op_add (ex2_op_add ),
.ex2_op_cmp (ex2_op_cmp ),
.ex2_op_fle (ex2_op_fle ),
.ex2_op_flt (ex2_op_flt ),
.ex2_op_maxnm (ex2_op_maxnm ),
.ex2_op_minnm (ex2_op_minnm ),
.ex2_op_sub (ex2_op_sub ),
.ex2_pipedown (ex2_pipedown ),
.ex2_rm_rdn (ex2_rm_rdn ),
.ex2_rm_rmm (ex2_rm_rmm ),
.ex2_rm_rne (ex2_rm_rne ),
.ex2_rm_rtz (ex2_rm_rtz ),
.ex2_rm_rup (ex2_rm_rup ),
.ex2_single (ex2_single ),
.ex3_expt (ex3_expt ),
.ex3_pipedown (ex3_pipedown ),
.ex3_result (ex3_result ),
.fadd_ctrl_src0 (fadd_ctrl_src0 ),
.fadd_ctrl_src1 (fadd_ctrl_src1 ),
.fadd_ereg_ex3_forward_r_vld (fadd_ereg_ex3_forward_r_vld),
.fadd_ereg_ex3_result (fadd_ereg_ex3_result ),
.fadd_forward_r_vld (fadd_forward_r_vld ),
.fadd_forward_result (fadd_forward_result ),
.fadd_mfvr_cmp_result (fadd_mfvr_cmp_result ),
.forever_cpuclk (forever_cpuclk ),
.half_expt (half_expt ),
.half_result (half_result ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_fadd_double_dp"); @142
ct_fadd_double_dp x_ct_fadd_double_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex1_as_double (ex1_double ),
.ex1_as_single (ex1_single ),
.ex1_cmp_result (ex1_doub_cmp_result),
.ex1_double (ex1_double ),
.ex1_op_add (ex1_op_add ),
.ex1_op_cmp (ex1_op_cmp ),
.ex1_op_feq (ex1_op_feq ),
.ex1_op_fle (ex1_op_fle ),
.ex1_op_flt (ex1_op_flt ),
.ex1_op_fne (ex1_op_fne ),
.ex1_op_ford (ex1_op_ford ),
.ex1_op_maxnm (ex1_op_maxnm ),
.ex1_op_minnm (ex1_op_minnm ),
.ex1_op_sub (ex1_op_sub ),
.ex1_pipedown (ex1_pipedown ),
.ex1_scalar (1'b1 ),
.ex1_single (ex1_single ),
.ex2_double (ex2_double ),
.ex2_op_add (ex2_op_add ),
.ex2_op_cmp (ex2_op_cmp ),
.ex2_op_fle (ex2_op_fle ),
.ex2_op_flt (ex2_op_flt ),
.ex2_op_maxnm (ex2_op_maxnm ),
.ex2_op_minnm (ex2_op_minnm ),
.ex2_op_sub (ex2_op_sub ),
.ex2_pipedown (ex2_pipedown ),
.ex2_rm_rdn (ex2_rm_rdn ),
.ex2_rm_rmm (ex2_rm_rmm ),
.ex2_rm_rne (ex2_rm_rne ),
.ex2_rm_rtz (ex2_rm_rtz ),
.ex2_rm_rup (ex2_rm_rup ),
.ex2_single (ex2_single ),
.ex3_expt (ex3_expt ),
.ex3_result (ex3_result ),
.fadd_ctrl_src0 (fadd_ctrl_src0 ),
.fadd_ctrl_src1 (fadd_ctrl_src1 ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan )
);
// &Connect(.ex1_cmp_result(ex1_doub_cmp_result)); @143
// &Connect(.ex1_as_double(ex1_double)); @144
// &Connect(.ex1_as_single(ex1_single)); @145
// &Connect(.ex1_scalar(1'b1)); @146
// &Instance("ct_fadd_half_dp","x_ct_fadd_double_half_dp"); @147
ct_fadd_half_dp x_ct_fadd_double_half_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.ex1_cmp_result (ex1_doub_half_cmp_result),
.ex1_op_add (ex1_op_add ),
.ex1_op_cmp (ex1_op_cmp ),
.ex1_op_feq (ex1_op_feq ),
.ex1_op_fle (ex1_op_fle ),
.ex1_op_flt (ex1_op_flt ),
.ex1_op_fne (ex1_op_fne ),
.ex1_op_ford (ex1_op_ford ),
.ex1_op_maxnm (ex1_op_maxnm ),
.ex1_op_minnm (ex1_op_minnm ),
.ex1_op_sub (ex1_op_sub ),
.ex1_pipedown (ex1_pipedown ),
.ex1_scalar (1'b1 ),
.ex2_op_add (ex2_op_add ),
.ex2_op_cmp (ex2_op_cmp ),
.ex2_op_fle (ex2_op_fle ),
.ex2_op_flt (ex2_op_flt ),
.ex2_op_maxnm (ex2_op_maxnm ),
.ex2_op_minnm (ex2_op_minnm ),
.ex2_op_sub (ex2_op_sub ),
.ex2_pipedown (ex2_pipedown ),
.ex2_rm_rdn (ex2_rm_rdn ),
.ex2_rm_rmm (ex2_rm_rmm ),
.ex2_rm_rne (ex2_rm_rne ),
.ex2_rm_rtz (ex2_rm_rtz ),
.ex2_rm_rup (ex2_rm_rup ),
.ex3_expt (half_expt ),
.ex3_result (half_result ),
.fadd_ctrl_src0 (fadd_ctrl_src0 ),
.fadd_ctrl_src1 (fadd_ctrl_src1 ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan )
);
// &Connect(.ex1_cmp_result(ex1_doub_half_cmp_result)); @148
// &Connect(.ex3_result(half_result)); @149
// &Connect(.ex3_expt(half_expt)); @150
// &Connect(.ex1_scalar(1'b1)); @151
// &ModuleEnd; @154
endmodule |
module ct_fcnvt_ctrl(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_sel,
ex1_pipedown,
ex2_pipedown,
ex3_pipedown,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @22
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [2:0] dp_vfalu_ex1_pipex_sel;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output ex1_pipedown;
output ex2_pipedown;
output ex3_pipedown;
// &Regs; @23
reg ex2_pipedown;
reg ex3_pipedown;
// &Wires; @24
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [2:0] dp_vfalu_ex1_pipex_sel;
wire ex1_pipedown;
wire ex1_vld_clk;
wire ex1_vld_clk_en;
wire ex2_vld_clk;
wire ex2_vld_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//EX1 Control
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0); @27
assign ex1_pipedown = dp_vfalu_ex1_pipex_sel[2];
// &Force("output","ex1_pipedown"); @29
//EX2 Control
//gate clk
// &Instance("gated_clk_cell","x_ex1_vld_clk"); @33
gated_clk_cell x_ex1_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @34
// .clk_out (ex1_vld_clk),//Out Clock @35
// .external_en (1'b0), @36
// .global_en (cp0_yy_clk_en), @37
// .local_en (ex1_vld_clk_en),//Local Condition @38
// .module_en (cp0_vfpu_icg_en) @39
// ); @40
assign ex1_vld_clk_en = ex1_pipedown || ex2_pipedown;
always @(posedge ex1_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex2_pipedown <= 1'b0;
else if(ex1_pipedown)
ex2_pipedown <= 1'b1;
else
ex2_pipedown <= 1'b0;
end
// &Force("output","ex2_pipedown"); @51
//EX3 Control
//gate clk
// &Instance("gated_clk_cell","x_ex2_vld_clk"); @55
gated_clk_cell x_ex2_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex2_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex2_vld_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @56
// .clk_out (ex2_vld_clk),//Out Clock @57
// .external_en (1'b0), @58
// .global_en (cp0_yy_clk_en), @59
// .local_en (ex2_vld_clk_en),//Local Condition @60
// .module_en (cp0_vfpu_icg_en) @61
// ); @62
assign ex2_vld_clk_en = ex2_pipedown || ex3_pipedown;
always @(posedge ex2_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
ex3_pipedown <= 1'b0;
else if(ex2_pipedown)
ex3_pipedown <= 1'b1;
else
ex3_pipedown <= 1'b0;
end
// &Force("output","ex3_pipedown"); @73
// //&Force("bus","dp_vfalu_ex1_pipex_func",19,0); @77
// //&Force("output","ex1_simd_pipedown"); @82
// //&Connect( .clk_in (forever_cpuclk), @87
// // .clk_out (ex1_simd_vld_clk),//Out Clock @88
// // .external_en (1'b0), @89
// // .global_en (cp0_yy_clk_en), @90
// // .local_en (ex1_simd_vld_clk_en),//Local Condition @91
// // .module_en (cp0_vfpu_icg_en) @92
// // ); @93
// //&Force("output","ex2_simd_pipedown"); @110
// //&Connect( .clk_in (forever_cpuclk), @115
// // .clk_out (ex2_simd_vld_clk),//Out Clock @116
// // .external_en (1'b0), @117
// // .global_en (cp0_yy_clk_en), @118
// // .local_en (ex2_simd_vld_clk_en),//Local Condition @119
// // .module_en (cp0_vfpu_icg_en) @120
// // ); @121
// ////&Force("output","ex3_simd_pipedown"); @138
// &ModuleEnd; @149
endmodule |
module ct_vfalu_top_pipe7(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_mtvr_src0,
dp_vfalu_ex1_pipex_sel,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
forever_cpuclk,
pad_yy_icg_scan_en,
pipex_dp_ex1_vfalu_mfvr_data,
pipex_dp_ex3_vfalu_ereg_data,
pipex_dp_ex3_vfalu_freg_data,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
input [2 :0] dp_vfalu_ex1_pipex_sel;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output [63:0] pipex_dp_ex1_vfalu_mfvr_data;
output [4 :0] pipex_dp_ex3_vfalu_ereg_data;
output [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Regs; @24
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire fcnvt_ereg_forward_r_vld;
wire [4 :0] fcnvt_ereg_forward_result;
wire fcnvt_forward_r_vld;
wire [63:0] fcnvt_forward_result;
wire forever_cpuclk;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire pad_yy_icg_scan_en;
wire [63:0] pipex_dp_ex1_vfalu_mfvr_data;
wire [4 :0] pipex_dp_ex3_vfalu_ereg_data;
wire [63:0] pipex_dp_ex3_vfalu_freg_data;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Instance("ct_fcnvt_top"); @27
ct_fcnvt_top x_ct_fcnvt_top (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_imm0 (dp_vfalu_ex1_pipex_imm0 ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.fcnvt_ereg_forward_r_vld (fcnvt_ereg_forward_r_vld ),
.fcnvt_ereg_forward_result (fcnvt_ereg_forward_result),
.fcnvt_forward_r_vld (fcnvt_forward_r_vld ),
.fcnvt_forward_result (fcnvt_forward_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_fadd_top"); @28
ct_fadd_top x_ct_fadd_top (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_imm0 (dp_vfalu_ex1_pipex_imm0 ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.fadd_ereg_ex3_forward_r_vld (fadd_ereg_ex3_forward_r_vld),
.fadd_ereg_ex3_result (fadd_ereg_ex3_result ),
.fadd_forward_r_vld (fadd_forward_r_vld ),
.fadd_forward_result (fadd_forward_result ),
.fadd_mfvr_cmp_result (fadd_mfvr_cmp_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_fspu_top"); @29
ct_fspu_top x_ct_fspu_top (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_mtvr_src0 (dp_vfalu_ex1_pipex_mtvr_src0),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.forever_cpuclk (forever_cpuclk ),
.fspu_forward_r_vld (fspu_forward_r_vld ),
.fspu_forward_result (fspu_forward_result ),
.fspu_mfvr_data (fspu_mfvr_data ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_vfalu_dp_pipe7"); @30
ct_vfalu_dp_pipe7 x_ct_vfalu_dp_pipe7 (
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.fadd_ereg_ex3_forward_r_vld (fadd_ereg_ex3_forward_r_vld ),
.fadd_ereg_ex3_result (fadd_ereg_ex3_result ),
.fadd_forward_r_vld (fadd_forward_r_vld ),
.fadd_forward_result (fadd_forward_result ),
.fadd_mfvr_cmp_result (fadd_mfvr_cmp_result ),
.fcnvt_ereg_forward_r_vld (fcnvt_ereg_forward_r_vld ),
.fcnvt_ereg_forward_result (fcnvt_ereg_forward_result ),
.fcnvt_forward_r_vld (fcnvt_forward_r_vld ),
.fcnvt_forward_result (fcnvt_forward_result ),
.fspu_forward_r_vld (fspu_forward_r_vld ),
.fspu_forward_result (fspu_forward_result ),
.fspu_mfvr_data (fspu_mfvr_data ),
.pipex_dp_ex1_vfalu_mfvr_data (pipex_dp_ex1_vfalu_mfvr_data),
.pipex_dp_ex3_vfalu_ereg_data (pipex_dp_ex3_vfalu_ereg_data),
.pipex_dp_ex3_vfalu_freg_data (pipex_dp_ex3_vfalu_freg_data)
);
// &ModuleEnd; @32
endmodule |
module ct_fadd_onehot_sel_d(
data_in,
onehot,
result
);
// &Ports; @23
input [53:0] data_in;
input [53:0] onehot;
output [53:0] result;
// &Regs; @24
reg [53:0] result_d;
// &Wires; @25
wire [53:0] data_in;
wire [53:0] onehot;
wire [53:0] result;
// &Force("bus","data_in",53,0); @27
// &CombBeg; @28
always @( onehot[53:0]
or data_in[53:0])
begin
case(onehot[53:0])
54'h20_0000_0000_0000 : result_d[53:0] = data_in[53:0];
54'h10_0000_0000_0000 : result_d[53:0] = {data_in[52:0],1'b0};
54'h08_0000_0000_0000 : result_d[53:0] = {data_in[51:0],2'b0};
54'h04_0000_0000_0000 : result_d[53:0] = {data_in[50:0],2'b0,1'b0};
54'h02_0000_0000_0000 : result_d[53:0] = {data_in[49:0],2'b0,2'b0};
54'h01_0000_0000_0000 : result_d[53:0] = {data_in[48:0],2'b0,3'b0};
54'h00_8000_0000_0000 : result_d[53:0] = {data_in[47:0],2'b0,4'b0};
54'h00_4000_0000_0000 : result_d[53:0] = {data_in[46:0],2'b0,5'b0};
54'h00_2000_0000_0000 : result_d[53:0] = {data_in[45:0],2'b0,6'b0};
54'h00_1000_0000_0000 : result_d[53:0] = {data_in[44:0],2'b0,7'b0};
54'h00_0800_0000_0000 : result_d[53:0] = {data_in[43:0],2'b0,8'b0};
54'h00_0400_0000_0000 : result_d[53:0] = {data_in[42:0],2'b0,9'b0};
54'h00_0200_0000_0000 : result_d[53:0] = {data_in[41:0],2'b0,10'b0};
54'h00_0100_0000_0000 : result_d[53:0] = {data_in[40:0],2'b0,11'b0};
54'h00_0080_0000_0000 : result_d[53:0] = {data_in[39:0],2'b0,12'b0};
54'h00_0040_0000_0000 : result_d[53:0] = {data_in[38:0],2'b0,13'b0};
54'h00_0020_0000_0000 : result_d[53:0] = {data_in[37:0],2'b0,14'b0};
54'h00_0010_0000_0000 : result_d[53:0] = {data_in[36:0],2'b0,15'b0};
54'h00_0008_0000_0000 : result_d[53:0] = {data_in[35:0],2'b0,16'b0};
54'h00_0004_0000_0000 : result_d[53:0] = {data_in[34:0],2'b0,17'b0};
54'h00_0002_0000_0000 : result_d[53:0] = {data_in[33:0],2'b0,18'b0};
54'h00_0001_0000_0000 : result_d[53:0] = {data_in[32:0],2'b0,19'b0};
54'h00_0000_8000_0000 : result_d[53:0] = {data_in[31:0],2'b0,20'b0};
54'h00_0000_4000_0000 : result_d[53:0] = {data_in[30:0],2'b0,21'b0};
54'h00_0000_2000_0000 : result_d[53:0] = {data_in[29:0],2'b0,22'b0};
54'h00_0000_1000_0000 : result_d[53:0] = {data_in[28:0],2'b0,23'b0};
54'h00_0000_0800_0000 : result_d[53:0] = {data_in[27:0],2'b0,24'b0};
54'h00_0000_0400_0000 : result_d[53:0] = {data_in[26:0],2'b0,25'b0};
54'h00_0000_0200_0000 : result_d[53:0] = {data_in[25:0],2'b0,26'b0};
54'h00_0000_0100_0000 : result_d[53:0] = {data_in[24:0],2'b0,27'b0};
54'h00_0000_0080_0000 : result_d[53:0] = {data_in[23:0],2'b0,28'b0};
54'h00_0000_0040_0000 : result_d[53:0] = {data_in[22:0],2'b0,29'b0};
54'h00_0000_0020_0000 : result_d[53:0] = {data_in[21:0],2'b0,30'b0};
54'h00_0000_0010_0000 : result_d[53:0] = {data_in[20:0],2'b0,31'b0};
54'h00_0000_0008_0000 : result_d[53:0] = {data_in[19:0],2'b0,32'b0};
54'h00_0000_0004_0000 : result_d[53:0] = {data_in[18:0],2'b0,33'b0};
54'h00_0000_0002_0000 : result_d[53:0] = {data_in[17:0],2'b0,34'b0};
54'h00_0000_0001_0000 : result_d[53:0] = {data_in[16:0],2'b0,35'b0};
54'h00_0000_0000_8000 : result_d[53:0] = {data_in[15:0],2'b0,36'b0};
54'h00_0000_0000_4000 : result_d[53:0] = {data_in[14:0],2'b0,37'b0};
54'h00_0000_0000_2000 : result_d[53:0] = {data_in[13:0],2'b0,38'b0};
54'h00_0000_0000_1000 : result_d[53:0] = {data_in[12:0],2'b0,39'b0};
54'h00_0000_0000_0800 : result_d[53:0] = {data_in[11:0],2'b0,40'b0};
54'h00_0000_0000_0400 : result_d[53:0] = {data_in[10:0],2'b0,41'b0};
54'h00_0000_0000_0200 : result_d[53:0] = {data_in[9:0],2'b0,42'b0};
54'h00_0000_0000_0100 : result_d[53:0] = {data_in[8:0],2'b0,43'b0};
54'h00_0000_0000_0080 : result_d[53:0] = {data_in[7:0],2'b0,44'b0};
54'h00_0000_0000_0040 : result_d[53:0] = {data_in[6:0],2'b0,45'b0};
54'h00_0000_0000_0020 : result_d[53:0] = {data_in[5:0],2'b0,46'b0};
54'h00_0000_0000_0010 : result_d[53:0] = {data_in[4:0],2'b0,47'b0};
54'h00_0000_0000_0008 : result_d[53:0] = {data_in[3:0],2'b0,48'b0};
54'h00_0000_0000_0004 : result_d[53:0] = {data_in[2:0],2'b0,49'b0};
54'h00_0000_0000_0002 : result_d[53:0] = {data_in[1:0],2'b0,50'b0};
54'h00_0000_0000_0001 : result_d[53:0] = {data_in[0] ,2'b0,51'b0};
54'h00_0000_0000_0000 : result_d[53:0] = 54'b0;
default : result_d[53:0] = {54{1'bx}};
endcase
// &CombEnd; @87
end
assign result[53:0] = result_d[53:0];
// &ModuleEnd; @91
endmodule |
module ct_fcnvt_stoh_sh(
stoh_sh_cnt,
stoh_sh_f_v,
stoh_sh_f_x,
stoh_sh_src
);
// &Ports; @17
input [7 :0] stoh_sh_cnt;
input [22:0] stoh_sh_src;
output [10:0] stoh_sh_f_v;
output [24:0] stoh_sh_f_x;
// &Regs; @18
reg [10:0] stoh_sh_f_v;
reg [24:0] stoh_sh_f_x;
// &Wires; @19
wire [7 :0] stoh_sh_cnt;
wire [22:0] stoh_sh_src;
// &CombBeg; @22
always @( stoh_sh_src[22:0]
or stoh_sh_cnt[7:0])
begin
case(stoh_sh_cnt[7:0])
8'h70: begin //-15
stoh_sh_f_v[10:0] = {2'b1,stoh_sh_src[22:14]};
stoh_sh_f_x[24:0] = {stoh_sh_src[13:0],11'b0};
end
8'h6f: begin //-16
stoh_sh_f_v[10:0] = {3'b1,stoh_sh_src[22:15]};
stoh_sh_f_x[24:0] = {stoh_sh_src[14:0],10'b0};
end
8'h6e: begin //-17
stoh_sh_f_v[10:0] = {4'b1,stoh_sh_src[22:16]};
stoh_sh_f_x[24:0] = {stoh_sh_src[15:0],9'b0};
end
8'h6d: begin //-18
stoh_sh_f_v[10:0] = {5'b1,stoh_sh_src[22:17]};
stoh_sh_f_x[24:0] = {stoh_sh_src[16:0],8'b0};
end
8'h6c: begin //-19
stoh_sh_f_v[10:0] = {6'b1,stoh_sh_src[22:18]};
stoh_sh_f_x[24:0] = {stoh_sh_src[17:0],7'b0};
end
8'h6b: begin //-20
stoh_sh_f_v[10:0] = {7'b1,stoh_sh_src[22:19]};
stoh_sh_f_x[24:0] = {stoh_sh_src[18:0],6'b0};
end
8'h6a: begin //-21
stoh_sh_f_v[10:0] = {8'b1,stoh_sh_src[22:20]};
stoh_sh_f_x[24:0] = {stoh_sh_src[19:0],5'b0};
end
8'h69: begin //-22
stoh_sh_f_v[10:0] = {9'b1,stoh_sh_src[22:21]};
stoh_sh_f_x[24:0] = {stoh_sh_src[20:0],4'b0};
end
8'h68: begin //-23
stoh_sh_f_v[10:0] = {10'b1,stoh_sh_src[22]};
stoh_sh_f_x[24:0] = {stoh_sh_src[21:0],3'b0};
end
8'h67: begin //-24
stoh_sh_f_v[10:0] = {11'b1};
stoh_sh_f_x[24:0] = {stoh_sh_src[22:0],2'b0};
end
8'h66: begin //-25
stoh_sh_f_v[10:0] = 11'b0;
stoh_sh_f_x[24:0] = {1'b1,stoh_sh_src[22:0],1'b0};
end
8'h65: begin //-26
stoh_sh_f_v[10:0] = 11'b0;
stoh_sh_f_x[24:0] = {2'b1,stoh_sh_src[22:0]};
end
default: begin
stoh_sh_f_v[10:0] = 11'b0;
stoh_sh_f_x[24:0] = {3'b1,22'b0};
end
endcase
// &CombEnd; @77
end
// &ModuleEnd; @80
endmodule |
module ct_fadd_close_s0_h(
close_adder0,
close_adder1,
close_eq,
close_op_chg,
close_sum,
ff1_pred,
ff1_pred_onehot
);
// &Ports; @23
input [10:0] close_adder0;
input [10:0] close_adder1;
output close_eq;
output close_op_chg;
output [10:0] close_sum;
output [3 :0] ff1_pred;
output [10:0] ff1_pred_onehot;
// &Regs; @24
reg [3 :0] ff1_pred_8_0;
reg [10:0] ff1_pred_onehot_8_0;
// &Wires; @25
wire [10:0] close_adder0;
wire [10:0] close_adder1;
wire close_eq;
wire [10:0] close_ff1_a;
wire [10:0] close_ff1_b;
wire [10:0] close_ff1_c;
wire [10:0] close_ff1_f;
wire [10:0] close_ff1_g;
wire [10:0] close_ff1_t;
wire [10:0] close_ff1_z;
wire close_op_chg;
wire [10:0] close_sum;
wire [11:0] close_sum0;
wire [11:0] close_sum1;
wire [3 :0] ff1_pred;
wire [3 :0] ff1_pred_10_9;
wire [3 :0] ff1_pred_nz;
wire [10:0] ff1_pred_nz_onehot;
wire [10:0] ff1_pred_onehot;
wire [10:0] ff1_pred_onehot_10_9;
//close_sum0 for F0-F1
assign close_sum0[11:0] = {1'b0,close_adder0[10:0]} - {1'b0,close_adder1[10:0]};
//close_sum0 for F1-F0
assign close_sum1[11:0] = {1'b0,close_adder1[10:0]} - {1'b0,close_adder0[10:0]};
//close_sum select, keep sum not negative
assign close_sum[10:0] = (close_sum0[11])
? close_sum1[10:0]
: close_sum0[10:0];
assign close_op_chg = close_sum0[11];
assign close_eq = !close_sum0[11] && !close_sum1[11];
//FF1 Logic of Close Path S0
//If predict first 1 set at r[n]
//Actual first 1 may set at r[n+1] or r[n]
//A and B are to oprand
assign close_ff1_a[10:0] = close_adder0[10:0];
assign close_ff1_b[10:0] = close_adder1[10:0];
//C = B && act_add || ~B && act_sub
assign close_ff1_c[10:0] = ~close_ff1_b[10:0];
//T = A^C G=A&C Z=(~A)&(~C)
assign close_ff1_t[10:0] = close_ff1_a[10:0] ^ close_ff1_c[10:0];
assign close_ff1_g[10:0] = close_ff1_a[10:0] & close_ff1_c[10:0];
assign close_ff1_z[10:0] = (~close_ff1_a[10:0]) & (~close_ff1_c[10:0]);
//F :
//fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
//f0 = t1(g0En+z0) + (~t1)(z0En+g0)
//fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
assign close_ff1_f[10] = ( close_ff1_g[10] & (~close_ff1_z[9])) |
( close_ff1_z[10] & (~close_ff1_g[9]));
assign close_ff1_f[0] = (( close_ff1_t[1]) & (close_ff1_g[0] | close_ff1_z[0])) |
((~close_ff1_t[1]) & (close_ff1_z[0] | close_ff1_g[0]));
assign close_ff1_f[9:1] = (( close_ff1_t[10:2]) & ((close_ff1_g[9:1] & (~close_ff1_z[8:0])) |
( close_ff1_z[9:1] & (~close_ff1_g[8:0])))) |
((~close_ff1_t[10:2]) & ((close_ff1_g[9:1] & (~close_ff1_g[8:0])) |
( close_ff1_z[9:1] & (~close_ff1_z[8:0]))));
// &CombBeg; @62
always @( close_ff1_f[8:0])
begin
casez(close_ff1_f[8:0])
9'b1???????? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00100_000000;
ff1_pred_8_0[3:0] = 4'd2;
end
9'b01??????? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00010_000000;
ff1_pred_8_0[3:0] = 4'd3;
end
9'b001?????? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00001_000000;
ff1_pred_8_0[3:0] = 4'd4;
end
9'b0001????? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_100000;
ff1_pred_8_0[3:0] = 4'd5;
end
9'b00001???? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_010000;
ff1_pred_8_0[3:0] = 4'd6;
end
9'b000001??? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_001000;
ff1_pred_8_0[3:0] = 4'd7;
end
9'b0000001?? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_000100;
ff1_pred_8_0[3:0] = 4'd8;
end
9'b00000001? : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_000010;
ff1_pred_8_0[3:0] = 4'd9;
end
9'b000000001 : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_000001;
ff1_pred_8_0[3:0] = 4'd10;
end
default : begin
ff1_pred_onehot_8_0[10:0] = 11'b00000_000000;
ff1_pred_8_0[3:0] = 4'd0;
end
endcase
// &CombEnd; @105
end
assign ff1_pred_onehot_10_9[10:0] = (close_ff1_f[10])
? 11'b10000_000000
: 11'b01000_000000;
assign ff1_pred_10_9[3:0] = (close_ff1_f[10])
? 4'b0
: 4'b1;
assign ff1_pred_nz_onehot[10:0] = (|close_ff1_f[10:9])
? ff1_pred_onehot_10_9[10:0]
: ff1_pred_onehot_8_0[10:0];
assign ff1_pred_nz[3:0] = (|close_ff1_f[10:9])
? ff1_pred_10_9[3:0]
: ff1_pred_8_0[3:0];
assign ff1_pred_onehot[10:0] = ff1_pred_nz_onehot[10:0];
assign ff1_pred[3:0] = ff1_pred_nz[3:0];
// &ModuleEnd; @124
endmodule |
module ct_fcnvt_top(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_sel,
dp_vfalu_ex1_pipex_srcf0,
fcnvt_ereg_forward_r_vld,
fcnvt_ereg_forward_result,
fcnvt_forward_r_vld,
fcnvt_forward_result,
forever_cpuclk,
pad_yy_icg_scan_en,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @22
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [2 :0] dp_vfalu_ex1_pipex_sel;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output fcnvt_ereg_forward_r_vld;
output [4 :0] fcnvt_ereg_forward_result;
output fcnvt_forward_r_vld;
output [63:0] fcnvt_forward_result;
// &Regs; @23
// &Wires; @24
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [63:0] dp_ex1_src;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire ex1_dest_double;
wire ex1_dest_float;
wire ex1_dest_single;
wire ex1_narrow;
wire ex1_pipedown;
wire [4 :0] ex1_rm;
wire ex1_sover;
wire ex1_src_double;
wire ex1_src_float;
wire ex1_src_l16;
wire ex1_src_l32;
wire ex1_src_l64;
wire ex1_src_si;
wire ex1_src_single;
wire ex1_widden;
wire ex2_dest_double;
wire ex2_dest_float;
wire ex2_dest_half;
wire ex2_dest_l16;
wire ex2_dest_l32;
wire ex2_dest_l64;
wire ex2_dest_l8;
wire ex2_dest_si;
wire ex2_dest_single;
wire ex2_pipedown;
wire ex2_src_float;
wire ex3_pipedown;
wire fcnvt_ereg_forward_r_vld;
wire [4 :0] fcnvt_ereg_forward_result;
wire [4 :0] fcnvt_ex3_expt;
wire [63:0] fcnvt_ex3_result;
wire fcnvt_forward_r_vld;
wire [63:0] fcnvt_forward_result;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
// &Instance("ct_fcnvt_ctrl"); @28
// &Instance("ct_fcnvt_dp"); @29
// &ConnRule(s/fcnvt_ex3/set0_doub_ex3/); @30
// &ConnRule(s/dp_ex1_src/dp_set0_doub_src/); @31
// &ConnRule(s/ex2_r_/set0_doub_ex2_r_/); @32
// &ConnRule(s/ex2_src2/set0_doub_ex2_src2/); @33
// &Instance("ct_fcnvt_double_dp","x_set0_ct_fcnvt_double_dp"); @34
// &Connect(.dp_ex1_widden_src(dp_set0_doub_widden_src)); @35
// &Connect(.ex1_vec_widden(dp_set0_doub_vec_widden)); @36
// &ConnRule(s/fcnvt_ex3/set0_half0_ex3/); @39
// &ConnRule(s/dp_ex1_src/dp_set0_half0_src/); @40
// &ConnRule(s/ex2_r_/set0_half0_ex2_r_/); @41
// &ConnRule(s/ex2_src2/set0_half0_ex2_src2/); @42
// &Instance("ct_fcnvt_half_dp", "x_set0_ct_fcnvt_half0_dp"); @43
// &ConnRule(s/fcnvt_ex3/set0_sing_ex3/); @45
// &ConnRule(s/dp_ex1_src/dp_set0_sing_src/); @46
// &ConnRule(s/ex2_r_/set0_sing_ex2_r_/); @47
// &ConnRule(s/ex2_src2/set0_sing_ex2_src2/); @48
// &Instance("ct_fcnvt_single_dp","x_set0_ct_fcnvt_single_dp"); @49
// &ConnRule(s/fcnvt_ex3/set0_half1_ex3/); @51
// &ConnRule(s/dp_ex1_src/dp_set0_half1_src/); @52
// &ConnRule(s/ex2_src2/set0_half1_ex2_src2/); @53
// &ConnRule(s/ex2_r_/set0_half1_ex2_r_/); @54
// &Instance("ct_fcnvt_half_dp", "x_set0_ct_fcnvt_half1_dp"); @55
// &ConnRule(s/fcnvt_ex3/set1_doub_ex3/); @57
// &ConnRule(s/dp_ex1_src/dp_set1_doub_src/); @58
// &ConnRule(s/ex2_src2/set1_doub_ex2_src2/); @59
// &ConnRule(s/ex2_r_/set1_doub_ex2_r_/); @60
// &Instance("ct_fcnvt_double_dp","x_set1_ct_fcnvt_double_dp"); @61
// &Connect(.dp_ex1_widden_src(dp_set1_doub_widden_src)); @62
// &Connect(.ex1_vec_widden(dp_set1_doub_vec_widden)); @63
// &ConnRule(s/fcnvt_ex3/set1_half0_ex3/); @65
// &ConnRule(s/dp_ex1_src/dp_set1_half0_src/); @66
// &ConnRule(s/ex2_src2/set1_half0_ex2_src2/); @67
// &ConnRule(s/ex2_r_/set1_half0_ex2_r_/); @68
// &Instance("ct_fcnvt_half_dp", "x_set1_ct_fcnvt_half0_dp"); @69
// &ConnRule(s/fcnvt_ex3/set1_sing_ex3/); @71
// &ConnRule(s/dp_ex1_src/dp_set1_sing_src/); @72
// &ConnRule(s/ex2_src2/set1_sing_ex2_src2/); @73
// &ConnRule(s/ex2_r_/set1_sing_ex2_r_/); @74
// &Instance("ct_fcnvt_single_dp","x_set1_ct_fcnvt_single_dp"); @75
// &ConnRule(s/fcnvt_ex3/set1_half1_ex3/); @77
// &ConnRule(s/dp_ex1_src/dp_set1_half1_src/); @78
// &ConnRule(s/ex2_src2/set1_half1_ex2_src2/); @79
// &ConnRule(s/ex2_r_/set1_half1_ex2_r_/); @80
// &Instance("ct_fcnvt_half_dp", "x_set1_ct_fcnvt_half1_dp"); @81
// &Instance("ct_fcnvt_ctrl"); @84
ct_fcnvt_ctrl x_ct_fcnvt_ctrl (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel),
.ex1_pipedown (ex1_pipedown ),
.ex2_pipedown (ex2_pipedown ),
.ex3_pipedown (ex3_pipedown ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_fcnvt_scalar_dp"); @85
ct_fcnvt_scalar_dp x_ct_fcnvt_scalar_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_ex1_src (dp_ex1_src ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_imm0 (dp_vfalu_ex1_pipex_imm0 ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.ex1_dest_double (ex1_dest_double ),
.ex1_dest_float (ex1_dest_float ),
.ex1_dest_single (ex1_dest_single ),
.ex1_narrow (ex1_narrow ),
.ex1_pipedown (ex1_pipedown ),
.ex1_rm (ex1_rm ),
.ex1_sover (ex1_sover ),
.ex1_src_double (ex1_src_double ),
.ex1_src_float (ex1_src_float ),
.ex1_src_l16 (ex1_src_l16 ),
.ex1_src_l32 (ex1_src_l32 ),
.ex1_src_l64 (ex1_src_l64 ),
.ex1_src_si (ex1_src_si ),
.ex1_src_single (ex1_src_single ),
.ex1_widden (ex1_widden ),
.ex2_dest_double (ex2_dest_double ),
.ex2_dest_float (ex2_dest_float ),
.ex2_dest_half (ex2_dest_half ),
.ex2_dest_l16 (ex2_dest_l16 ),
.ex2_dest_l32 (ex2_dest_l32 ),
.ex2_dest_l64 (ex2_dest_l64 ),
.ex2_dest_l8 (ex2_dest_l8 ),
.ex2_dest_si (ex2_dest_si ),
.ex2_dest_single (ex2_dest_single ),
.ex2_src_float (ex2_src_float ),
.ex3_pipedown (ex3_pipedown ),
.fcnvt_ereg_forward_r_vld (fcnvt_ereg_forward_r_vld ),
.fcnvt_ereg_forward_result (fcnvt_ereg_forward_result),
.fcnvt_ex3_expt (fcnvt_ex3_expt ),
.fcnvt_ex3_result (fcnvt_ex3_result ),
.fcnvt_forward_r_vld (fcnvt_forward_r_vld ),
.fcnvt_forward_result (fcnvt_forward_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_fcnvt_double_dp","x_set0_ct_fcnvt_double_dp"); @86
ct_fcnvt_double_dp x_set0_ct_fcnvt_double_dp (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_ex1_src (dp_ex1_src ),
.ex1_dest_double (ex1_dest_double ),
.ex1_dest_float (ex1_dest_float ),
.ex1_dest_single (ex1_dest_single ),
.ex1_narrow (ex1_narrow ),
.ex1_pipedown (ex1_pipedown ),
.ex1_rm (ex1_rm ),
.ex1_scalar (1'b1 ),
.ex1_sover (ex1_sover ),
.ex1_src_double (ex1_src_double ),
.ex1_src_float (ex1_src_float ),
.ex1_src_l16 (ex1_src_l16 ),
.ex1_src_l32 (ex1_src_l32 ),
.ex1_src_l64 (ex1_src_l64 ),
.ex1_src_si (ex1_src_si ),
.ex1_src_single (ex1_src_single ),
.ex1_widden (ex1_widden ),
.ex2_dest_double (ex2_dest_double ),
.ex2_dest_float (ex2_dest_float ),
.ex2_dest_half (ex2_dest_half ),
.ex2_dest_l16 (ex2_dest_l16 ),
.ex2_dest_l32 (ex2_dest_l32 ),
.ex2_dest_l64 (ex2_dest_l64 ),
.ex2_dest_l8 (ex2_dest_l8 ),
.ex2_dest_si (ex2_dest_si ),
.ex2_dest_single (ex2_dest_single ),
.ex2_pipedown (ex2_pipedown ),
.ex2_src_float (ex2_src_float ),
.fcnvt_ex3_expt (fcnvt_ex3_expt ),
.fcnvt_ex3_result (fcnvt_ex3_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan )
);
// &Connect(.ex1_scalar(1'b1)); @87
// &ModuleEnd; @91
endmodule |
module ct_fadd_close_s1_d(
close_adder0,
close_adder1,
close_op_chg,
close_sum,
ex1_double,
ex1_single,
ff1_pred,
ff1_pred_onehot
);
// &Ports; @23
input [53:0] close_adder0;
input [53:0] close_adder1;
input ex1_double;
input ex1_single;
output close_op_chg;
output [53:0] close_sum;
output [5 :0] ff1_pred;
output [53:0] ff1_pred_onehot;
// &Regs; @24
reg [5 :0] ff1_pred_t0;
reg [53:0] ff1_pred_t0_onehot;
// &Wires; @25
wire [53:0] close_adder0;
wire [53:0] close_adder0_t0;
wire [53:0] close_adder1;
wire [53:0] close_adder1_t0;
wire [53:0] close_ff1_a_t0;
wire [53:0] close_ff1_b_t0;
wire [53:0] close_ff1_c_t0;
wire [53:0] close_ff1_f_t0;
wire [53:0] close_ff1_g_t0;
wire [53:0] close_ff1_t_t0;
wire [53:0] close_ff1_z_t0;
wire [53:0] close_m1_oper2;
wire close_op_chg;
wire [53:0] close_sum;
wire [53:0] close_sum_t0;
wire ex1_double;
wire ex1_single;
wire [5 :0] ff1_pred;
wire [53:0] ff1_pred_onehot;
//Three Type
//t0 : !src0_e_is_0 && !src1_e_is_0
//t1 : !src0_e_is_0 && src1_e_is_0
//t2 : src0_e_is_0 && src1_e_is_0
//assign type0_sel = !src0_e_is_0 && !src1_e_is_0;
//assign type1_sel = !src0_e_is_0 && src1_e_is_0;
//assign type2_sel = src0_e_is_0 && src1_e_is_0;
//assign close_sum[53:0] = {54{type0_sel}} & close_sum_t0[53:0] |
// {54{type1_sel}} & close_sum_t1[53:0] |
// {54{type2_sel}} & close_sum_t2[53:0];
//assign close_sum_m1[53:0] = {54{type0_sel}} & close_sum_m1_t0[53:0] |
// {54{type1_sel}} & close_sum_m1_t1[53:0] |
// {54{type2_sel}} & close_sum_m1_t2[53:0];
//assign ff1_pred[53:0] = {54{type0_sel}} & ff1_pred_t0_onehot[53:0] |
// {54{type1_sel}} & ff1_pred_t1_onehot[53:0] |
// {54{type2_sel}} & ff1_pred_t2[53:0];
assign close_sum[53:0] = close_sum_t0[53:0];
//assign close_sum_m1[53:0] = close_sum_m1_t0[53:0];
assign ff1_pred_onehot[53:0] = ff1_pred_t0_onehot[53:0];
assign ff1_pred[5:0] = ff1_pred_t0[5:0];
assign close_op_chg = close_sum[53];
// &Force("output","close_sum"); @51
assign close_adder0_t0[53:0] = close_adder0[53:0];
assign close_adder1_t0[53:0] = close_adder1[53:0];
//assign close_adder0_t1[53:0] = close_adder0[53:0];
//assign close_adder1_t1[53:0] = {1'b0, 1'b0, 22'b0, 29'b0};
assign close_m1_oper2[53:0] = {54{ex1_double}} & 54'b10 |
{54{ex1_single}} & {24'b1,30'b0};
// &Force("nonport","close_sum_t0"); @60
// &Force("nonport","close_sum_m1_t0"); @61
// &Force("nonport","close_m1_oper2"); @62
//csky vperl_off
//close_sum0 for F0-F1
assign close_sum_t0[53:0] = $unsigned($signed(close_adder0_t0[53:0]) - $signed(close_adder1_t0[53:0]));
//close_sum0 for F1-F0
//close_sum select, keep sum not negative
//close_sum0_m1
//assign close_sum_m1_t0[53:0] = $unsigned($signed(close_adder0_t0[53:0])
// - $signed(close_adder1_t0[53:0])
// + $signed(close_m1_oper2[53:0]));
//csky vperl_on
//FF1 Logic of Close Path S0
//If predict first 1 set at r[n]
//Actual first 1 may set at r[n+1] or r[n]
//A and B are to oprand
assign close_ff1_a_t0[53:0] = close_adder0_t0[53:0];
assign close_ff1_b_t0[53:0] = close_adder1_t0[53:0];
//C = B && act_add || ~B && act_sub
assign close_ff1_c_t0[53:0] = ~close_ff1_b_t0[53:0];
//T = A^C G=A&C Z=(~A)&(~C)
assign close_ff1_t_t0[53:0] = close_ff1_a_t0[53:0] ^ close_ff1_c_t0[53:0];
assign close_ff1_g_t0[53:0] = close_ff1_a_t0[53:0] & close_ff1_c_t0[53:0];
assign close_ff1_z_t0[53:0] = (~close_ff1_a_t0[53:0]) & (~close_ff1_c_t0[53:0]);
//F :
//fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
//f0 = t1(g0En+z0) + (~t1)(z0En+g0)
//fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
assign close_ff1_f_t0[53] = ( close_ff1_g_t0[53] & (~close_ff1_z_t0[52])) |
( close_ff1_z_t0[53] & (~close_ff1_g_t0[52]));
assign close_ff1_f_t0[0] = (( close_ff1_t_t0[1]) & (close_ff1_g_t0[0] | close_ff1_z_t0[0])) |
((~close_ff1_t_t0[1]) & (close_ff1_z_t0[0] | close_ff1_g_t0[0]));
assign close_ff1_f_t0[52:1] = (( close_ff1_t_t0[53:2]) & ((close_ff1_g_t0[52:1] & (~close_ff1_z_t0[51:0])) |
( close_ff1_z_t0[52:1] & (~close_ff1_g_t0[51:0])))) |
((~close_ff1_t_t0[53:2]) & ((close_ff1_g_t0[52:1] & (~close_ff1_g_t0[51:0])) |
( close_ff1_z_t0[52:1] & (~close_ff1_z_t0[51:0]))));
// &CombBeg; @99
always @( close_ff1_f_t0[53:0])
begin
casez(close_ff1_f_t0[53:0])
54'b1????_????????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b10000_00000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd0;
end
54'b01???_????????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b01000_00000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd1;
end
54'b001??_????????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00100_00000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd2;
end
54'b0001?_????????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00010_00000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd3;
end
54'b00001_????????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00001_00000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd4;
end
54'b00000_1???????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_10000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd5;
end
54'b00000_01??????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_01000000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd6;
end
54'b00000_001?????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00100000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd7;
end
54'b00000_0001????_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00010000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd8;
end
54'b00000_00001???_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00001000_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd9;
end
54'b00000_000001??_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000100_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd10;
end
54'b00000_0000001?_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000010_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd11;
end
54'b00000_00000001_????????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000001_00000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd12;
end
54'b00000_00000000_1???????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_10000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd13;
end
54'b00000_00000000_01??????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_01000000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd14;
end
54'b00000_00000000_001?????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00100000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd15;
end
54'b00000_00000000_0001????_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00010000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd16;
end
54'b00000_00000000_00001???_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00001000_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd17;
end
54'b00000_00000000_000001??_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000100_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd18;
end
54'b00000_00000000_0000001?_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000010_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd19;
end
54'b00000_00000000_00000001_????????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000001_00000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd20;
end
54'b00000_00000000_00000000_1???????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_10000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd21;
end
54'b00000_00000000_00000000_01??????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_01000000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd22;
end
54'b00000_00000000_00000000_001?????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00100000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd23;
end
54'b00000_00000000_00000000_0001????_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00010000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd24;
end
54'b00000_00000000_00000000_00001???_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00001000_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd25;
end
54'b00000_00000000_00000000_000001??_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000100_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd26;
end
54'b00000_00000000_00000000_0000001?_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000010_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd27;
end
54'b00000_00000000_00000000_00000001_????????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000001_00000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd28;
end
54'b00000_00000000_00000000_00000000_1???????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_10000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd29;
end
54'b00000_00000000_00000000_00000000_01??????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_01000000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd30;
end
54'b00000_00000000_00000000_00000000_001?????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00100000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd31;
end
54'b00000_00000000_00000000_00000000_0001????_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00010000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd32;
end
54'b00000_00000000_00000000_00000000_00001???_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00001000_00000000_000000000;
ff1_pred_t0[5:0] = 6'd33;
end
54'b00000_00000000_00000000_00000000_000001??_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000100_00000000_000000000;
ff1_pred_t0[5:0] = 6'd34;
end
54'b00000_00000000_00000000_00000000_0000001?_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000010_00000000_000000000;
ff1_pred_t0[5:0] = 6'd35;
end
54'b00000_00000000_00000000_00000000_00000001_????????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000001_00000000_000000000;
ff1_pred_t0[5:0] = 6'd36;
end
54'b00000_00000000_00000000_00000000_00000000_1???????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_10000000_000000000;
ff1_pred_t0[5:0] = 6'd37;
end
54'b00000_00000000_00000000_00000000_00000000_01??????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_01000000_000000000;
ff1_pred_t0[5:0] = 6'd38;
end
54'b00000_00000000_00000000_00000000_00000000_001?????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00100000_000000000;
ff1_pred_t0[5:0] = 6'd39;
end
54'b00000_00000000_00000000_00000000_00000000_0001????_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00010000_000000000;
ff1_pred_t0[5:0] = 6'd40;
end
54'b00000_00000000_00000000_00000000_00000000_00001???_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00001000_000000000;
ff1_pred_t0[5:0] = 6'd41;
end
54'b00000_00000000_00000000_00000000_00000000_000001??_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000100_000000000;
ff1_pred_t0[5:0] = 6'd42;
end
54'b00000_00000000_00000000_00000000_00000000_0000001?_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000010_000000000;
ff1_pred_t0[5:0] = 6'd43;
end
54'b00000_00000000_00000000_00000000_00000000_00000001_????????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000001_000000000;
ff1_pred_t0[5:0] = 6'd44;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_1???????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_100000000;
ff1_pred_t0[5:0] = 6'd45;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_01??????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_010000000;
ff1_pred_t0[5:0] = 6'd46;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_001?????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_001000000;
ff1_pred_t0[5:0] = 6'd47;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_0001????? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000100000;
ff1_pred_t0[5:0] = 6'd48;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_00001???? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000010000;
ff1_pred_t0[5:0] = 6'd49;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_000001??? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000001000;
ff1_pred_t0[5:0] = 6'd50;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_0000001?? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000000100;
ff1_pred_t0[5:0] = 6'd51;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_00000001? : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000000010;
ff1_pred_t0[5:0] = 6'd52;
end
54'b00000_00000000_00000000_00000000_00000000_00000000_000000001 : begin
ff1_pred_t0_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000000001;
ff1_pred_t0[5:0] = 6'd53;
end
default : begin
ff1_pred_t0_onehot[53:0] = {54{1'bx}};
ff1_pred_t0[5:0] = {6{1'bx}};
end
endcase
// &CombEnd; @323
end
////close_sum0 for F0-F1
//assign close_sum_t1[53:0] = close_adder0_t1[53:0] + ~close_adder1_t1[53:0] + 54'b1;
////close_sum0 for F1-F0
////close_sum select, keep sum not negative
////close_sum0_m1
//assign close_sum_m1_t1[53:0] = close_adder0_t1[53:0] + ~close_adder1_t1[53:0];
//
////FF1 Logic of Close Path S0
////If predict first 1 set at r[n]
////Actual first 1 may set at r[n+1] or r[n]
////A and B are to oprand
//assign close_ff1_a_t1[53:0] = close_adder0_t1[53:0];
//assign close_ff1_b_t1[53:0] = close_adder1_t1[53:0];
//
////C = B && act_add || ~B && act_sub
//assign close_ff1_c_t1[53:0] = ~close_ff1_b_t1[53:0];
////T = A^C G=A&C Z=(~A)&(~C)
//assign close_ff1_t_t1[53:0] = close_ff1_a_t1[53:0] ^ close_ff1_c_t1[53:0];
//assign close_ff1_g_t1[53:0] = close_ff1_a_t1[53:0] & close_ff1_c_t1[53:0];
//assign close_ff1_z_t1[53:0] = (~close_ff1_a_t1[53:0]) & (~close_ff1_c_t1[53:0]);
////F :
////fn-1 = En[gi(~zi-1) + zi(~gi-1)] + (~En)[gi(~gi-1) + zi(~zi-1)], En=act_sub
////f0 = t1(g0En+z0) + (~t1)(z0En+g0)
////fi = ti+1[gi(~zi-1) + zi(~gi-1)] + (~ti+1)[gi(~gi-1) + zi(~zi-1)]
//assign close_ff1_f_t1[53] = ( close_ff1_g_t1[53] & (~close_ff1_z_t1[52])) |
// ( close_ff1_z_t1[53] & (~close_ff1_g_t1[52]));
//assign close_ff1_f_t1[0] = (( close_ff1_t_t1[1]) & (close_ff1_g_t1[0] | close_ff1_z_t1[0])) |
// ((~close_ff1_t_t1[1]) & (close_ff1_z_t1[0] | close_ff1_g_t1[0]));
//assign close_ff1_f_t1[52:1] = (( close_ff1_t_t1[53:2]) & ((close_ff1_g_t1[52:1] & (~close_ff1_z_t1[51:0])) |
// ( close_ff1_z_t1[52:1] & (~close_ff1_g_t1[51:0])))) |
// ((~close_ff1_t_t1[53:2]) & ((close_ff1_g_t1[52:1] & (~close_ff1_g_t1[51:0])) |
// ( close_ff1_z_t1[52:1] & (~close_ff1_z_t1[51:0]))));
//
//
//&CombBeg;
//casez(close_ff1_f_t1[53:0])
// 54'b1????_????????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b10000_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd0;
// end
// 54'b01???_????????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b01000_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd1;
// end
// 54'b001??_????????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00100_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd2;
// end
// 54'b0001?_????????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00010_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd3;
// end
// 54'b00001_????????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00001_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd4;
// end
// 54'b00000_1???????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_10000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd5;
// end
// 54'b00000_01??????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_01000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd6;
// end
// 54'b00000_001?????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00100000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd7;
// end
// 54'b00000_0001????_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00010000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd8;
// end
// 54'b00000_00001???_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00001000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd9;
// end
// 54'b00000_000001??_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000100_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd10;
// end
// 54'b00000_0000001?_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000010_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd11;
// end
// 54'b00000_00000001_????????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000001_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd12;
// end
// 54'b00000_00000000_1???????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_10000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd13;
// end
// 54'b00000_00000000_01??????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_01000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd14;
// end
// 54'b00000_00000000_001?????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00100000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd15;
// end
// 54'b00000_00000000_0001????_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00010000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd16;
// end
// 54'b00000_00000000_00001???_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00001000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd17;
// end
// 54'b00000_00000000_000001??_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000100_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd18;
// end
// 54'b00000_00000000_0000001?_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000010_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd19;
// end
// 54'b00000_00000000_00000001_????????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000001_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd20;
// end
// 54'b00000_00000000_00000000_1???????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_10000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd21;
// end
// 54'b00000_00000000_00000000_01??????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_01000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd22;
// end
// 54'b00000_00000000_00000000_001?????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00100000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd23;
// end
// 54'b00000_00000000_00000000_0001????_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00010000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd24;
// end
// 54'b00000_00000000_00000000_00001???_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00001000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd25;
// end
// 54'b00000_00000000_00000000_000001??_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000100_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd26;
// end
// 54'b00000_00000000_00000000_0000001?_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000010_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd27;
// end
// 54'b00000_00000000_00000000_00000001_????????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000001_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd28;
// end
// 54'b00000_00000000_00000000_00000000_1???????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_10000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd29;
// end
// 54'b00000_00000000_00000000_00000000_01??????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_01000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd30;
// end
// 54'b00000_00000000_00000000_00000000_001?????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00100000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd31;
// end
// 54'b00000_00000000_00000000_00000000_0001????_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00010000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd32;
// end
// 54'b00000_00000000_00000000_00000000_00001???_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00001000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd33;
// end
// 54'b00000_00000000_00000000_00000000_000001??_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000100_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd34;
// end
// 54'b00000_00000000_00000000_00000000_0000001?_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000010_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd35;
// end
// 54'b00000_00000000_00000000_00000000_00000001_????????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000001_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd36;
// end
// 54'b00000_00000000_00000000_00000000_00000000_1???????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_10000000_000000000;
// ff1_pred_t1[5:0] = 6'd37;
// end
// 54'b00000_00000000_00000000_00000000_00000000_01??????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_01000000_000000000;
// ff1_pred_t1[5:0] = 6'd38;
// end
// 54'b00000_00000000_00000000_00000000_00000000_001?????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00100000_000000000;
// ff1_pred_t1[5:0] = 6'd39;
// end
// 54'b00000_00000000_00000000_00000000_00000000_0001????_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00010000_000000000;
// ff1_pred_t1[5:0] = 6'd40;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00001???_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00001000_000000000;
// ff1_pred_t1[5:0] = 6'd41;
// end
// 54'b00000_00000000_00000000_00000000_00000000_000001??_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000100_000000000;
// ff1_pred_t1[5:0] = 6'd42;
// end
// 54'b00000_00000000_00000000_00000000_00000000_0000001?_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000010_000000000;
// ff1_pred_t1[5:0] = 6'd43;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000001_????????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000001_000000000;
// ff1_pred_t1[5:0] = 6'd44;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_1???????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_100000000;
// ff1_pred_t1[5:0] = 6'd45;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_01??????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_010000000;
// ff1_pred_t1[5:0] = 6'd46;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_001?????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_001000000;
// ff1_pred_t1[5:0] = 6'd47;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_0001????? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000100000;
// ff1_pred_t1[5:0] = 6'd48;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_00001???? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000010000;
// ff1_pred_t1[5:0] = 6'd49;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_000001?? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000001000;
// ff1_pred_t1[5:0] = 6'd51;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_0000001? : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_00000010;
// ff1_pred_t1[5:0] = 6'd52;
// end
// 54'b00000_00000000_00000000_00000000_00000000_00000000_00000001 : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_00000001;
// ff1_pred_t1[5:0] = 6'd53;
// end
// default : begin
// ff1_pred_t1_onehot[53:0] = 54'b00000_00000000_00000000_00000000_00000000_00000000_000000000;
// ff1_pred_t1[5:0] = 6'd0;
// end
//endcase
//&CombEnd;
//
//
//assign close_sum_t2[53:0] = 54'b0;
//assign close_sum_m1_t2[53:0] = 54'h1f_ffff_ffff_ffff;
//assign ff1_pred_t2_onehot[53:0] = 54'b0;
//assign ff1_pred_t2[5:0] = 6'h0;
//
// &ModuleEnd; @586
endmodule |
module ct_vfalu_dp_pipe7(
dp_vfalu_ex1_pipex_sel,
fadd_ereg_ex3_forward_r_vld,
fadd_ereg_ex3_result,
fadd_forward_r_vld,
fadd_forward_result,
fadd_mfvr_cmp_result,
fcnvt_ereg_forward_r_vld,
fcnvt_ereg_forward_result,
fcnvt_forward_r_vld,
fcnvt_forward_result,
fspu_forward_r_vld,
fspu_forward_result,
fspu_mfvr_data,
pipex_dp_ex1_vfalu_mfvr_data,
pipex_dp_ex3_vfalu_ereg_data,
pipex_dp_ex3_vfalu_freg_data
);
// &Ports; @23
input [2 :0] dp_vfalu_ex1_pipex_sel;
input fadd_ereg_ex3_forward_r_vld;
input [4 :0] fadd_ereg_ex3_result;
input fadd_forward_r_vld;
input [63:0] fadd_forward_result;
input [63:0] fadd_mfvr_cmp_result;
input fcnvt_ereg_forward_r_vld;
input [4 :0] fcnvt_ereg_forward_result;
input fcnvt_forward_r_vld;
input [63:0] fcnvt_forward_result;
input fspu_forward_r_vld;
input [63:0] fspu_forward_result;
input [63:0] fspu_mfvr_data;
output [63:0] pipex_dp_ex1_vfalu_mfvr_data;
output [4 :0] pipex_dp_ex3_vfalu_ereg_data;
output [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Regs; @24
reg [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Wires; @25
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire fcnvt_ereg_forward_r_vld;
wire [4 :0] fcnvt_ereg_forward_result;
wire fcnvt_forward_r_vld;
wire [63:0] fcnvt_forward_result;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire [63:0] pipex_dp_ex1_vfalu_mfvr_data;
wire [4 :0] pipex_dp_ex3_vfalu_ereg_data;
//assign pipex_dp_ex3_vfalu_expt_vec[4:0] = 5'd30;
// &Force("output","pipex_dp_ex3_vfalu_ereg_data"); @28
assign pipex_dp_ex3_vfalu_ereg_data[4:0] = {5{fadd_ereg_ex3_forward_r_vld}} & fadd_ereg_ex3_result[4:0] |
{5{fcnvt_ereg_forward_r_vld}} & fcnvt_ereg_forward_result[4:0];
assign pipex_dp_ex1_vfalu_mfvr_data[63:0] = {64{dp_vfalu_ex1_pipex_sel[1]}} & fadd_mfvr_cmp_result[63:0] |
{64{dp_vfalu_ex1_pipex_sel[0]}} & fspu_mfvr_data[63:0];
// &Force("bus","dp_vfalu_ex1_pipex_sel",2,0); @33
// &CombBeg; @35
// &CombEnd; @42
// &CombBeg; @44
// &CombEnd; @51
// &CombBeg; @57
always @( fspu_forward_result[63:0]
or fspu_forward_r_vld
or fadd_forward_r_vld
or fadd_forward_result[63:0]
or fcnvt_forward_result[63:0]
or fcnvt_forward_r_vld)
begin
case({fadd_forward_r_vld,fcnvt_forward_r_vld,fspu_forward_r_vld})
3'b100 : pipex_dp_ex3_vfalu_freg_data[63:0] = fadd_forward_result[63:0];
3'b010 : pipex_dp_ex3_vfalu_freg_data[63:0] = fcnvt_forward_result[63:0];
3'b001 : pipex_dp_ex3_vfalu_freg_data[63:0] = fspu_forward_result[63:0];
default : pipex_dp_ex3_vfalu_freg_data[63:0] = {64{1'bx}};
endcase
// &CombEnd; @64
end
// &ModuleEnd; @68
endmodule |
module ct_fcnvt_scalar_dp(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_ex1_src,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_srcf0,
ex1_dest_double,
ex1_dest_float,
ex1_dest_single,
ex1_narrow,
ex1_pipedown,
ex1_rm,
ex1_sover,
ex1_src_double,
ex1_src_float,
ex1_src_l16,
ex1_src_l32,
ex1_src_l64,
ex1_src_si,
ex1_src_single,
ex1_widden,
ex2_dest_double,
ex2_dest_float,
ex2_dest_half,
ex2_dest_l16,
ex2_dest_l32,
ex2_dest_l64,
ex2_dest_l8,
ex2_dest_si,
ex2_dest_single,
ex2_src_float,
ex3_pipedown,
fcnvt_ereg_forward_r_vld,
fcnvt_ereg_forward_result,
fcnvt_ex3_expt,
fcnvt_ex3_result,
fcnvt_forward_r_vld,
fcnvt_forward_result,
forever_cpuclk,
pad_yy_icg_scan_en,
vfpu_yy_xx_rm
);
// &Ports; @22
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input ex1_pipedown;
input ex3_pipedown;
input [4 :0] fcnvt_ex3_expt;
input [63:0] fcnvt_ex3_result;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input [2 :0] vfpu_yy_xx_rm;
output [63:0] dp_ex1_src;
output ex1_dest_double;
output ex1_dest_float;
output ex1_dest_single;
output ex1_narrow;
output [4 :0] ex1_rm;
output ex1_sover;
output ex1_src_double;
output ex1_src_float;
output ex1_src_l16;
output ex1_src_l32;
output ex1_src_l64;
output ex1_src_si;
output ex1_src_single;
output ex1_widden;
output ex2_dest_double;
output ex2_dest_float;
output ex2_dest_half;
output ex2_dest_l16;
output ex2_dest_l32;
output ex2_dest_l64;
output ex2_dest_l8;
output ex2_dest_si;
output ex2_dest_single;
output ex2_src_float;
output fcnvt_ereg_forward_r_vld;
output [4 :0] fcnvt_ereg_forward_result;
output fcnvt_forward_r_vld;
output [63:0] fcnvt_forward_result;
// &Regs; @23
reg ex2_dest_double;
reg ex2_dest_float;
reg ex2_dest_half;
reg ex2_dest_l16;
reg ex2_dest_l32;
reg ex2_dest_l64;
reg ex2_dest_si;
reg ex2_dest_single;
reg ex2_src_float;
// &Wires; @24
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [63:0] dp_ex1_src;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire ex1_dest_double;
wire ex1_dest_float;
wire ex1_dest_half;
wire ex1_dest_l16;
wire ex1_dest_l32;
wire ex1_dest_l64;
wire ex1_dest_si;
wire ex1_dest_single;
wire ex1_equal;
wire ex1_narrow;
wire ex1_pipe_clk;
wire ex1_pipe_clk_en;
wire ex1_pipedown;
wire [4 :0] ex1_rm;
wire ex1_rm_rdn;
wire ex1_rm_rmm;
wire ex1_rm_rne;
wire ex1_rm_rtz;
wire ex1_rm_rup;
wire ex1_sover;
wire [63:0] ex1_src0;
wire ex1_src_double;
wire ex1_src_float;
wire ex1_src_l16;
wire ex1_src_l32;
wire ex1_src_l64;
wire ex1_src_si;
wire ex1_src_single;
wire ex1_widden;
wire ex2_dest_l8;
wire ex3_pipedown;
wire fcnvt_ereg_forward_r_vld;
wire [4 :0] fcnvt_ereg_forward_result;
wire [4 :0] fcnvt_ex3_expt;
wire [63:0] fcnvt_ex3_result;
wire fcnvt_forward_r_vld;
wire [63:0] fcnvt_forward_result;
wire forever_cpuclk;
wire [19:0] func;
wire pad_yy_icg_scan_en;
wire [2 :0] vfalu_rm;
wire [2 :0] vfalu_static_rm;
wire [2 :0] vfpu_yy_xx_rm;
//Round Mode Set
assign vfalu_static_rm[2:0] = dp_vfalu_ex1_pipex_imm0[2:0];
assign vfalu_rm[2:0] = (vfalu_static_rm[2:0] == 3'b111)
? vfpu_yy_xx_rm[2:0]
: vfalu_static_rm[2:0];
assign ex1_rm_rne = (vfalu_rm[2:0] == 3'b000);
assign ex1_rm_rtz = (vfalu_rm[2:0] == 3'b001);
assign ex1_rm_rdn = (vfalu_rm[2:0] == 3'b010);
assign ex1_rm_rup = (vfalu_rm[2:0] == 3'b011);
assign ex1_rm_rmm = (vfalu_rm[2:0] == 3'b100);
assign ex1_rm[4:0] = {ex1_rm_rmm,
ex1_rm_rdn,
ex1_rm_rup,
ex1_rm_rtz,
ex1_rm_rne};
//======================Data Prepare========================
// &Force("bus","dp_vfalu_ex1_pipe6_func",19,0); @42
// &Force("bus","dp_vfalu_ex1_pipex_imm0", 2,0); @43
// &Force("bus","dp_vfalu_ex1_pipex_split_count",5,0); @44
assign func[19:0] = dp_vfalu_ex1_pipex_func[19:0];
assign ex1_src_l64 = func[16] || func[15] && ex1_narrow;
assign ex1_src_l32 = func[15] && !ex1_narrow || !func[16] && !func[15] && ex1_narrow;
assign ex1_src_l16 = !func[16] && !func[15] && !ex1_narrow;
//assign ex1_src_l16 = 1'b0;
assign ex1_widden = func[14] && !func[13];
assign ex1_narrow = !func[14] && func[13];
assign ex1_equal = !func[13] && !func[14];
assign ex1_sover = func[14] && func[13]; //this means the 16->64,64->16
//assign ex1_fcnvt = func[7];
assign ex1_src_si = func[0];
assign ex1_src_float = func[1];
assign ex1_dest_float = func[2];
assign ex1_dest_si = func[3];
assign ex1_src_single = ex1_src_l32;
assign ex1_src_double = ex1_src_l64;
//assign ex1_dest_l16 = ex1_src_l32 && ex1_narrow ||
// ex1_src_l8 && ex1_widden ||
// ex1_src_l16 && ex1_equal ||
// ex1_src_l64 && ex1_sover;
assign ex1_dest_l64 = ex1_src_l64 && ex1_equal ||
ex1_src_l32 && ex1_widden ||
ex1_src_l16 && ex1_sover;
assign ex1_dest_l32 = ex1_src_l32 && ex1_equal ||
ex1_src_l16 && ex1_widden ||
ex1_src_l64 && ex1_narrow;
assign ex1_dest_l16 = ex1_src_l32 && ex1_narrow ||
ex1_src_l16 && ex1_equal ||
ex1_src_l64 && ex1_sover;
assign ex1_dest_half = ex1_dest_float && ex1_dest_l16;
assign ex1_dest_single = ex1_dest_float && ex1_dest_l32;
assign ex1_dest_double = ex1_dest_float && ex1_dest_l64;
// &Force("output","ex1_dest_float"); @80
// &Force("output","ex1_src_float"); @81
// &Force("output","ex1_src_si"); @82
// &Force("output","ex1_rm"); @83
// &Force("output","ex1_narrow"); @84
// &Force("output","ex1_src_l64"); @85
// &Force("output","ex1_src_l32"); @86
// &Force("output","ex1_src_l16"); @87
// &Force("output","ex1_src_single"); @88
// &Force("output","ex1_src_double"); @89
// &Force("output","ex1_widden"); @90
// //&Force("output","ex1_dest_half"); @91
// &Force("output","ex1_dest_double"); @92
// &Force("output","ex1_dest_single"); @93
// //&Force("output","ex1_dest_si"); @94
// &Force("output","ex1_sover"); @95
assign ex1_src0[63:0] = dp_vfalu_ex1_pipex_srcf0[63:0];
assign dp_ex1_src[63:0] = ex1_src0[63:0];
//gate clk
// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @102
gated_clk_cell x_ex1_pipe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ex1_pipe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ex1_pipe_clk_en ),
.module_en (cp0_vfpu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect( .clk_in (forever_cpuclk), @103
// .clk_out (ex1_pipe_clk),//Out Clock @104
// .external_en (1'b0), @105
// .global_en (cp0_yy_clk_en), @106
// .local_en (ex1_pipe_clk_en),//Local Condition @107
// .module_en (cp0_vfpu_icg_en) @108
// ); @109
assign ex1_pipe_clk_en = ex1_pipedown;
always @(posedge ex1_pipe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
ex2_dest_float <= 1'b0;
ex2_dest_double <= 1'b0;
ex2_dest_single <= 1'b0;
ex2_dest_half <= 1'b0;
ex2_dest_l32 <= 1'b0;
ex2_dest_l64 <= 1'b0;
ex2_dest_l16 <= 1'b0;
ex2_dest_si <= 1'b0;
ex2_src_float <= 1'b0;
end
else if(ex1_pipedown)
begin
ex2_dest_double <= ex1_dest_double;
ex2_dest_single <= ex1_dest_single;
ex2_dest_float <= ex1_dest_float;
ex2_dest_l32 <= ex1_dest_l32;
ex2_dest_l64 <= ex1_dest_l64;
ex2_dest_l16 <= ex1_dest_l16;
ex2_dest_half <= ex1_dest_half;
ex2_dest_si <= ex1_dest_si;
ex2_src_float <= ex1_src_float;
end
end
// &Force("output","ex2_dest_float"); @139
// &Force("output","ex2_dest_l32"); @140
// &Force("output","ex2_dest_l64"); @141
assign ex2_dest_l8 = 1'b0;
//=======================Pipe to EX3========================
//gate clk
//&Instance("gated_clk_cell","x_ex2_pipe_clk");
// //&Connect( .clk_in (forever_cpuclk), @148
// // .clk_out (ex2_pipe_clk),//Out Clock @149
// // .external_en (1'b0), @150
// // .global_en (cp0_yy_clk_en), @151
// // .local_en (ex2_pipe_clk_en),//Local Condition @152
// // .module_en (cp0_vfpu_icg_en) @153
// // ); @154
//assign ex2_pipe_clk_en = ex2_pipedown;
//always @(posedge ex2_pipe_clk or negedge cpurst_b)
//begin
// if(!cpurst_b)
// begin
// ex3_dest_float <= 1'b0;
// end
// else if(ex2_pipedown)
// begin
// ex3_dest_float <= ex2_dest_float;
// end
//end
//==========================================================
// EX3 Result Merge
//==========================================================
assign fcnvt_ereg_forward_result[4:0] = fcnvt_ex3_expt[4:0];
assign fcnvt_forward_result[63:0] = fcnvt_ex3_result[63:0];
assign fcnvt_forward_r_vld = ex3_pipedown;
assign fcnvt_ereg_forward_r_vld = ex3_pipedown;
// &ModuleEnd; @179
endmodule |
module ct_fcnvt_htos_sh(
htos_sh_cnt,
htos_sh_f_v,
htos_sh_src
);
// &Ports; @23
input [9 :0] htos_sh_src;
output [5 :0] htos_sh_cnt;
output [10:0] htos_sh_f_v;
// &Regs; @24
reg [5 :0] htos_sh_cnt;
reg [10:0] htos_sh_f_v;
// &Wires; @25
wire [9 :0] htos_sh_src;
// &CombBeg; @27
always @( htos_sh_src[9:0])
begin
casez(htos_sh_src[9:0])
10'b1?????????: begin
htos_sh_f_v[10:0] = {htos_sh_src[9:0],1'b0};
htos_sh_cnt[5:0] = 6'h31; //-15:
end
10'b01????????: begin
htos_sh_f_v[10:0] = {htos_sh_src[8:0],2'b0};
htos_sh_cnt[5:0] = 6'h30; //-16
end
10'b001???????: begin
htos_sh_f_v[10:0] = {htos_sh_src[7:0],3'b0};
htos_sh_cnt[5:0] = 6'h2f; //-17
end
10'b0001??????: begin
htos_sh_f_v[10:0] = {htos_sh_src[6:0],4'b0};
htos_sh_cnt[5:0] = 6'h2e; //-18
end
10'b00001?????: begin
htos_sh_f_v[10:0] = {htos_sh_src[5:0],5'b0};
htos_sh_cnt[5:0] = 6'h2d; //-19
end
10'b000001????: begin
htos_sh_f_v[10:0] = {htos_sh_src[4:0],6'b0};
htos_sh_cnt[5:0] = 6'h2c; //-20
end
10'b0000001???: begin
htos_sh_f_v[10:0] = {htos_sh_src[3:0],7'b0};
htos_sh_cnt[5:0] = 6'h2b; //-9
end
10'b00000001??: begin
htos_sh_f_v[10:0] = {htos_sh_src[2:0],8'b0};
htos_sh_cnt[5:0] = 6'h2a; //-155
end
10'b000000001?: begin
htos_sh_f_v[10:0] = {htos_sh_src[1:0],9'b0};
htos_sh_cnt[5:0] = 6'h29; //-155
end
10'b0000000001: begin
htos_sh_f_v[10:0] = {htos_sh_src[0],10'b0};
htos_sh_cnt[5:0] = 6'h28; //-156
end
default: begin
htos_sh_f_v[10:0] = 11'b0;
htos_sh_cnt[5:0] = 6'h0;
end
endcase
// &CombEnd; @74
end
// &ModuleEnd; @77
endmodule |
module ct_fspu_single(
check_nan,
ex1_op_fmvvf,
ex1_op_fsgnj,
ex1_op_fsgnjn,
ex1_op_fsgnjx,
ex1_oper0,
ex1_oper1,
ex1_result,
ex1_scalar,
mtvr_src0,
result_fclass,
result_fmfvr
);
// &Ports; @19
input check_nan;
input ex1_op_fmvvf;
input ex1_op_fsgnj;
input ex1_op_fsgnjn;
input ex1_op_fsgnjx;
input [63:0] ex1_oper0;
input [63:0] ex1_oper1;
input ex1_scalar;
input [63:0] mtvr_src0;
output [63:0] ex1_result;
output [31:0] result_fclass;
output [63:0] result_fmfvr;
// &Regs; @20
// &Wires; @21
wire check_nan;
wire ex1_mtvr_cnan;
wire ex1_op0_cnan;
wire ex1_op1_cnan;
wire ex1_op_fmvvf;
wire ex1_op_fsgnj;
wire ex1_op_fsgnjn;
wire ex1_op_fsgnjx;
wire [63:0] ex1_oper0;
wire [31:0] ex1_oper0_single;
wire [63:0] ex1_oper1;
wire [31:0] ex1_oper1_single;
wire [63:0] ex1_result;
wire ex1_scalar;
wire ex1_sing_expnt0_max;
wire ex1_sing_expnt0_zero;
wire ex1_sing_frac0_all0;
wire ex1_sing_frac0_msb;
wire ex1_sing_neg_dn;
wire ex1_sing_neg_inf;
wire ex1_sing_neg_nm;
wire ex1_sing_neg_zero;
wire ex1_sing_op0_sign;
wire ex1_sing_pos_dn;
wire ex1_sing_pos_inf;
wire ex1_sing_pos_nm;
wire ex1_sing_pos_zero;
wire ex1_sing_qnan;
wire ex1_sing_snan;
wire [63:0] mtvr_src0;
wire [31:0] mtvr_src0_f;
wire [31:0] result_fclass;
wire [31:0] result_fclasss;
wire [63:0] result_fmfvr;
wire [63:0] result_fmfvrs;
wire [63:0] result_fmtvrs;
wire [63:0] result_fsgnjns;
wire [63:0] result_fsgnjs;
wire [63:0] result_fsgnjxs;
// &Force("bus","ex1_oper1",63,0); @22
assign ex1_op0_cnan = ex1_scalar && !(&ex1_oper0[63:32]);
assign ex1_op1_cnan = ex1_scalar && !(&ex1_oper1[63:32]);
assign ex1_oper0_single[31:0] = (ex1_op0_cnan)
? 32'h7fc00000
: ex1_oper0[31:0];
assign ex1_oper1_single[31:0] = (ex1_op1_cnan)
? 32'h7fc00000
: ex1_oper1[31:0];
//Sign bit prepare
assign ex1_sing_op0_sign = ex1_oper0_single[31];
//exponent max
assign ex1_sing_expnt0_max = &ex1_oper0_single[30:23];
//exponent zero
assign ex1_sing_expnt0_zero = ~|ex1_oper0_single[30:23];
//fraction zero
assign ex1_sing_frac0_all0 = ~|ex1_oper0_single[22:0];
//freaction msb
assign ex1_sing_frac0_msb = ex1_oper0_single[22];
//FLASS.S
assign ex1_sing_neg_inf = ex1_sing_op0_sign && ex1_sing_expnt0_max && ex1_sing_frac0_all0;
assign ex1_sing_neg_nm = ex1_sing_op0_sign && !ex1_sing_expnt0_max && !ex1_sing_expnt0_zero;
assign ex1_sing_neg_dn = ex1_sing_op0_sign && ex1_sing_expnt0_zero && !ex1_sing_frac0_all0;
assign ex1_sing_neg_zero = ex1_sing_op0_sign && ex1_sing_expnt0_zero && ex1_sing_frac0_all0;
assign ex1_sing_pos_zero = !ex1_sing_op0_sign && ex1_sing_expnt0_zero && ex1_sing_frac0_all0;
assign ex1_sing_pos_dn = !ex1_sing_op0_sign && ex1_sing_expnt0_zero && !ex1_sing_frac0_all0;
assign ex1_sing_pos_nm = !ex1_sing_op0_sign && !ex1_sing_expnt0_max && !ex1_sing_expnt0_zero;
assign ex1_sing_pos_inf = !ex1_sing_op0_sign && ex1_sing_expnt0_max && ex1_sing_frac0_all0;
assign ex1_sing_snan = ex1_sing_expnt0_max && !ex1_sing_frac0_all0 && !ex1_sing_frac0_msb;
assign ex1_sing_qnan = ex1_sing_expnt0_max && ex1_sing_frac0_msb;
assign result_fclasss[31:0] = {
22'b0,
ex1_sing_qnan,
ex1_sing_snan,
ex1_sing_pos_inf,
ex1_sing_pos_nm,
ex1_sing_pos_dn,
ex1_sing_pos_zero,
ex1_sing_neg_zero,
ex1_sing_neg_dn,
ex1_sing_neg_nm,
ex1_sing_neg_inf
};
//FSGNJX.S
assign result_fsgnjxs[63:0] = {32'hffffffff,
ex1_oper0_single[31]^ex1_oper1_single[31],
ex1_oper0_single[30:0]};
//FSGNJN.S
assign result_fsgnjns[63:0] = {32'hffffffff,
~ex1_oper1_single[31],
ex1_oper0_single[30:0]};
//FSGNJ.S
assign result_fsgnjs[63:0] = {32'hffffffff,
ex1_oper1_single[31],
ex1_oper0_single[30:0]};
assign ex1_mtvr_cnan = check_nan && !(&mtvr_src0[63:32]);
assign mtvr_src0_f[31:0] = ex1_mtvr_cnan ? 32'h7fc00000
: mtvr_src0[31:0];
//FMV.W.X
assign result_fmtvrs[63:0] = {32'hffffffff,mtvr_src0_f[31:0]};
//FMV.X.W
assign result_fmfvrs[63:0] = {{32{ex1_oper0[31]}},ex1_oper0[31:0]};
assign result_fmfvr[63:0] = result_fmfvrs[63:0];
assign result_fclass[31:0] = result_fclasss[31:0];
//Final Result
assign ex1_result[63:0] = {64{ex1_op_fmvvf}} & result_fmtvrs[63:0] |
{64{ex1_op_fsgnj}} & result_fsgnjs[63:0] |
{64{ex1_op_fsgnjn}} & result_fsgnjns[63:0] |
{64{ex1_op_fsgnjx}} & result_fsgnjxs[63:0];
// &ModuleEnd; @113
endmodule |
module ct_vfalu_top_pipe6(
cp0_vfpu_icg_en,
cp0_yy_clk_en,
cpurst_b,
dp_vfalu_ex1_pipex_func,
dp_vfalu_ex1_pipex_imm0,
dp_vfalu_ex1_pipex_mtvr_src0,
dp_vfalu_ex1_pipex_sel,
dp_vfalu_ex1_pipex_srcf0,
dp_vfalu_ex1_pipex_srcf1,
forever_cpuclk,
pad_yy_icg_scan_en,
pipex_dp_ex1_vfalu_mfvr_data,
pipex_dp_ex3_vfalu_ereg_data,
pipex_dp_ex3_vfalu_freg_data,
vfpu_yy_xx_dqnan,
vfpu_yy_xx_rm
);
// &Ports; @23
input cp0_vfpu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input [19:0] dp_vfalu_ex1_pipex_func;
input [2 :0] dp_vfalu_ex1_pipex_imm0;
input [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
input [2 :0] dp_vfalu_ex1_pipex_sel;
input [63:0] dp_vfalu_ex1_pipex_srcf0;
input [63:0] dp_vfalu_ex1_pipex_srcf1;
input forever_cpuclk;
input pad_yy_icg_scan_en;
input vfpu_yy_xx_dqnan;
input [2 :0] vfpu_yy_xx_rm;
output [63:0] pipex_dp_ex1_vfalu_mfvr_data;
output [4 :0] pipex_dp_ex3_vfalu_ereg_data;
output [63:0] pipex_dp_ex3_vfalu_freg_data;
// &Regs; @24
// &Wires; @25
wire cp0_vfpu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire [19:0] dp_vfalu_ex1_pipex_func;
wire [2 :0] dp_vfalu_ex1_pipex_imm0;
wire [63:0] dp_vfalu_ex1_pipex_mtvr_src0;
wire [2 :0] dp_vfalu_ex1_pipex_sel;
wire [63:0] dp_vfalu_ex1_pipex_srcf0;
wire [63:0] dp_vfalu_ex1_pipex_srcf1;
wire fadd_ereg_ex3_forward_r_vld;
wire [4 :0] fadd_ereg_ex3_result;
wire fadd_forward_r_vld;
wire [63:0] fadd_forward_result;
wire [63:0] fadd_mfvr_cmp_result;
wire forever_cpuclk;
wire fspu_forward_r_vld;
wire [63:0] fspu_forward_result;
wire [63:0] fspu_mfvr_data;
wire pad_yy_icg_scan_en;
wire [63:0] pipex_dp_ex1_vfalu_mfvr_data;
wire [4 :0] pipex_dp_ex3_vfalu_ereg_data;
wire [63:0] pipex_dp_ex3_vfalu_freg_data;
wire vfpu_yy_xx_dqnan;
wire [2 :0] vfpu_yy_xx_rm;
//&Instance("ct_fcnvt_top");
// &Instance("ct_fadd_top"); @28
ct_fadd_top x_ct_fadd_top (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_imm0 (dp_vfalu_ex1_pipex_imm0 ),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.fadd_ereg_ex3_forward_r_vld (fadd_ereg_ex3_forward_r_vld),
.fadd_ereg_ex3_result (fadd_ereg_ex3_result ),
.fadd_forward_r_vld (fadd_forward_r_vld ),
.fadd_forward_result (fadd_forward_result ),
.fadd_mfvr_cmp_result (fadd_mfvr_cmp_result ),
.forever_cpuclk (forever_cpuclk ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en ),
.vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ),
.vfpu_yy_xx_rm (vfpu_yy_xx_rm )
);
// &Instance("ct_fspu_top"); @29
ct_fspu_top x_ct_fspu_top (
.cp0_vfpu_icg_en (cp0_vfpu_icg_en ),
.cp0_yy_clk_en (cp0_yy_clk_en ),
.cpurst_b (cpurst_b ),
.dp_vfalu_ex1_pipex_func (dp_vfalu_ex1_pipex_func ),
.dp_vfalu_ex1_pipex_mtvr_src0 (dp_vfalu_ex1_pipex_mtvr_src0),
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.dp_vfalu_ex1_pipex_srcf0 (dp_vfalu_ex1_pipex_srcf0 ),
.dp_vfalu_ex1_pipex_srcf1 (dp_vfalu_ex1_pipex_srcf1 ),
.forever_cpuclk (forever_cpuclk ),
.fspu_forward_r_vld (fspu_forward_r_vld ),
.fspu_forward_result (fspu_forward_result ),
.fspu_mfvr_data (fspu_mfvr_data ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Instance("ct_vfalu_dp_pipe6"); @30
ct_vfalu_dp_pipe6 x_ct_vfalu_dp_pipe6 (
.dp_vfalu_ex1_pipex_sel (dp_vfalu_ex1_pipex_sel ),
.fadd_ereg_ex3_forward_r_vld (fadd_ereg_ex3_forward_r_vld ),
.fadd_ereg_ex3_result (fadd_ereg_ex3_result ),
.fadd_forward_r_vld (fadd_forward_r_vld ),
.fadd_forward_result (fadd_forward_result ),
.fadd_mfvr_cmp_result (fadd_mfvr_cmp_result ),
.fspu_forward_r_vld (fspu_forward_r_vld ),
.fspu_forward_result (fspu_forward_result ),
.fspu_mfvr_data (fspu_mfvr_data ),
.pipex_dp_ex1_vfalu_mfvr_data (pipex_dp_ex1_vfalu_mfvr_data),
.pipex_dp_ex3_vfalu_ereg_data (pipex_dp_ex3_vfalu_ereg_data),
.pipex_dp_ex3_vfalu_freg_data (pipex_dp_ex3_vfalu_freg_data)
);
// &Force("nonport","fadd_ereg_ex3_forward_r_vld") @31
// &ModuleEnd; @32
endmodule |
module ct_fspu_half(
check_nan,
ex1_op_fmvvf,
ex1_op_fsgnj,
ex1_op_fsgnjn,
ex1_op_fsgnjx,
ex1_oper0,
ex1_oper1,
ex1_result,
ex1_scalar,
mtvr_src0,
result_fclass,
result_fmfvr
);
// &Ports; @19
input check_nan;
input ex1_op_fmvvf;
input ex1_op_fsgnj;
input ex1_op_fsgnjn;
input ex1_op_fsgnjx;
input [63:0] ex1_oper0;
input [63:0] ex1_oper1;
input ex1_scalar;
input [63:0] mtvr_src0;
output [63:0] ex1_result;
output [15:0] result_fclass;
output [63:0] result_fmfvr;
// &Regs; @20
// &Wires; @21
wire check_nan;
wire ex1_half_expnt0_max;
wire ex1_half_expnt0_zero;
wire ex1_half_frac0_all0;
wire ex1_half_frac0_msb;
wire ex1_half_neg_dn;
wire ex1_half_neg_inf;
wire ex1_half_neg_nm;
wire ex1_half_neg_zero;
wire ex1_half_op0_sign;
wire ex1_half_pos_dn;
wire ex1_half_pos_inf;
wire ex1_half_pos_nm;
wire ex1_half_pos_zero;
wire ex1_half_qnan;
wire ex1_half_snan;
wire ex1_mtvr_cnan;
wire ex1_op0_cnan;
wire ex1_op1_cnan;
wire ex1_op_fmvvf;
wire ex1_op_fsgnj;
wire ex1_op_fsgnjn;
wire ex1_op_fsgnjx;
wire [63:0] ex1_oper0;
wire [15:0] ex1_oper0_half;
wire [63:0] ex1_oper1;
wire [15:0] ex1_oper1_half;
wire [63:0] ex1_result;
wire ex1_scalar;
wire [63:0] mtvr_src0;
wire [15:0] mtvr_src0_f;
wire [15:0] result_fclass;
wire [15:0] result_fclasss;
wire [63:0] result_fmfvr;
wire [63:0] result_fmfvrs;
wire [63:0] result_fmtvrs;
wire [63:0] result_fsgnjns;
wire [63:0] result_fsgnjs;
wire [63:0] result_fsgnjxs;
// &Force("bus","ex1_oper1",63,0); @22
assign ex1_op0_cnan = ex1_scalar && !(&ex1_oper0[63:16]);
assign ex1_op1_cnan = ex1_scalar && !(&ex1_oper1[63:16]);
assign ex1_oper0_half[15:0] = (ex1_op0_cnan)
? 16'h7e00
: ex1_oper0[15:0];
assign ex1_oper1_half[15:0] = (ex1_op1_cnan)
? 16'h7e00
: ex1_oper1[15:0];
//Sign bit prepare
assign ex1_half_op0_sign = ex1_oper0_half[15];
//exponent max
assign ex1_half_expnt0_max = &ex1_oper0_half[14:10];
//exponent zero
assign ex1_half_expnt0_zero = ~|ex1_oper0_half[14:10];
//fraction zero
assign ex1_half_frac0_all0 = ~|ex1_oper0_half[9:0];
//freaction msb
assign ex1_half_frac0_msb = ex1_oper0_half[9];
//FLASS.S
assign ex1_half_neg_inf = ex1_half_op0_sign && ex1_half_expnt0_max && ex1_half_frac0_all0;
assign ex1_half_neg_nm = ex1_half_op0_sign && !ex1_half_expnt0_max && !ex1_half_expnt0_zero;
assign ex1_half_neg_dn = ex1_half_op0_sign && ex1_half_expnt0_zero && !ex1_half_frac0_all0;
assign ex1_half_neg_zero = ex1_half_op0_sign && ex1_half_expnt0_zero && ex1_half_frac0_all0;
assign ex1_half_pos_zero = !ex1_half_op0_sign && ex1_half_expnt0_zero && ex1_half_frac0_all0;
assign ex1_half_pos_dn = !ex1_half_op0_sign && ex1_half_expnt0_zero && !ex1_half_frac0_all0;
assign ex1_half_pos_nm = !ex1_half_op0_sign && !ex1_half_expnt0_max && !ex1_half_expnt0_zero;
assign ex1_half_pos_inf = !ex1_half_op0_sign && ex1_half_expnt0_max && ex1_half_frac0_all0;
assign ex1_half_snan = ex1_half_expnt0_max && !ex1_half_frac0_all0 && !ex1_half_frac0_msb;
assign ex1_half_qnan = ex1_half_expnt0_max && ex1_half_frac0_msb;
assign result_fclasss[15:0] = {
6'b0,
ex1_half_qnan,
ex1_half_snan,
ex1_half_pos_inf,
ex1_half_pos_nm,
ex1_half_pos_dn,
ex1_half_pos_zero,
ex1_half_neg_zero,
ex1_half_neg_dn,
ex1_half_neg_nm,
ex1_half_neg_inf
};
//FSGNJX.S
assign result_fsgnjxs[63:0] = {48'hffffffffffff,
ex1_oper0_half[15]^ex1_oper1_half[15],
ex1_oper0_half[14:0]};
//FSGNJN.S
assign result_fsgnjns[63:0] = {48'hffffffffffff,
~ex1_oper1_half[15],
ex1_oper0_half[14:0]};
//FSGNJ.S
assign result_fsgnjs[63:0] = {48'hffffffffffff,
ex1_oper1_half[15],
ex1_oper0_half[14:0]};
assign ex1_mtvr_cnan = check_nan && !(&mtvr_src0[63:16]);
assign mtvr_src0_f[15:0] = ex1_mtvr_cnan ? 16'h7e00
: mtvr_src0[15:0];
//FMV.W.X
assign result_fmtvrs[63:0] = {48'hffffffffffff,mtvr_src0_f[15:0]};
//FMV.X.W
assign result_fmfvrs[63:0] = {{48{ex1_oper0[15]}},ex1_oper0[15:0]};
assign result_fmfvr[63:0] = result_fmfvrs[63:0];
assign result_fclass[15:0] = result_fclasss[15:0];
//Final Result
assign ex1_result[63:0] = {64{ex1_op_fmvvf}} & result_fmtvrs[63:0] |
{64{ex1_op_fsgnj}} & result_fsgnjs[63:0] |
{64{ex1_op_fsgnjn}} & result_fsgnjns[63:0] |
{64{ex1_op_fsgnjx}} & result_fsgnjxs[63:0];
// &ModuleEnd; @113
endmodule |
module ct_ifu_bht_sel_array(
bht_sel_array_cen_b,
bht_sel_array_clk_en,
bht_sel_array_din,
bht_sel_array_gwen,
bht_sel_array_index,
bht_sel_bwen,
bht_sel_data_out,
cp0_ifu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input bht_sel_array_cen_b;
input bht_sel_array_clk_en;
input [15:0] bht_sel_array_din;
input bht_sel_array_gwen;
input [6 :0] bht_sel_array_index;
input [15:0] bht_sel_bwen;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [15:0] bht_sel_data_out;
// &Regs; @24
// &Wires; @25
wire bht_sel_array_cen_b;
wire bht_sel_array_clk_en;
wire [15:0] bht_sel_array_din;
wire bht_sel_array_gwen;
wire [6 :0] bht_sel_array_index;
wire [15:0] bht_sel_bwen;
wire bht_sel_clk;
wire [15:0] bht_sel_data_out;
wire bht_sel_en;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//Gate Clk
// &Instance("gated_clk_cell", "x_bht_sel_clk"); @28
gated_clk_cell x_bht_sel_clk (
.clk_in (forever_cpuclk ),
.clk_out (bht_sel_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (bht_sel_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in(forever_cpuclk), @29
// .external_en(1'b0), @30
// .global_en(cp0_yy_clk_en), @31
// .module_en(cp0_ifu_icg_en), @32
// .local_en(bht_sel_en), @33
// .clk_out(bht_sel_clk) @34
// ); @35
assign bht_sel_en = bht_sel_array_clk_en;
//Instance Logic
// &Instance("ct_spsram_128x16", "x_ct_spsram_128x16"); @40
ct_spsram_128x16 x_ct_spsram_128x16 (
.A (bht_sel_array_index),
.CEN (bht_sel_array_cen_b),
.CLK (bht_sel_clk ),
.D (bht_sel_array_din ),
.GWEN (bht_sel_array_gwen ),
.Q (bht_sel_data_out ),
.WEN (bht_sel_bwen )
);
// &Connect( @41
// .CLK (bht_sel_clk ), @42
// .Q (bht_sel_data_out ), @43
// .CEN (bht_sel_array_cen_b), @44
// .WEN (bht_sel_bwen ), @45
// .D (bht_sel_array_din ), @46
// .A (bht_sel_array_index), @47
// .GWEN (bht_sel_array_gwen ) @48
// ); @49
// &ModuleEnd; @51
endmodule |
module ct_ifu_precode(
inst_data,
pre_code
);
// &Ports; @23
input [127:0] inst_data;
output [31 :0] pre_code;
// &Regs; @24
// &Wires; @25
wire h1_ab_br;
wire h1_br;
wire h1_bry0;
wire h1_bry1;
wire h1_bry1_32;
wire [15 :0] h1_data;
wire [3 :0] h1_pre_code;
wire h2_ab_br;
wire h2_br;
wire h2_bry0;
wire h2_bry0_32;
wire h2_bry1;
wire h2_bry1_16;
wire h2_bry1_32;
wire [15 :0] h2_data;
wire [3 :0] h2_pre_code;
wire h3_ab_br;
wire h3_br;
wire h3_bry0;
wire h3_bry0_16;
wire h3_bry0_32;
wire h3_bry1;
wire h3_bry1_16;
wire h3_bry1_32;
wire [15 :0] h3_data;
wire [3 :0] h3_pre_code;
wire h4_ab_br;
wire h4_br;
wire h4_bry0;
wire h4_bry0_16;
wire h4_bry0_32;
wire h4_bry1;
wire h4_bry1_16;
wire h4_bry1_32;
wire [15 :0] h4_data;
wire [3 :0] h4_pre_code;
wire h5_ab_br;
wire h5_br;
wire h5_bry0;
wire h5_bry0_16;
wire h5_bry0_32;
wire h5_bry1;
wire h5_bry1_16;
wire h5_bry1_32;
wire [15 :0] h5_data;
wire [3 :0] h5_pre_code;
wire h6_ab_br;
wire h6_br;
wire h6_bry0;
wire h6_bry0_16;
wire h6_bry0_32;
wire h6_bry1;
wire h6_bry1_16;
wire h6_bry1_32;
wire [15 :0] h6_data;
wire [3 :0] h6_pre_code;
wire h7_ab_br;
wire h7_br;
wire h7_bry0;
wire h7_bry0_16;
wire h7_bry0_32;
wire h7_bry1;
wire h7_bry1_16;
wire h7_bry1_32;
wire [15 :0] h7_data;
wire [3 :0] h7_pre_code;
wire h8_ab_br;
wire h8_br;
wire h8_bry0;
wire h8_bry0_16;
wire h8_bry0_32;
wire h8_bry1;
wire h8_bry1_16;
wire h8_bry1_32;
wire [15 :0] h8_data;
wire [3 :0] h8_pre_code;
wire [127:0] inst_data;
wire [31 :0] pre_code;
//==========================================================
// Precode Information
//==========================================================
//pre_code[23:21] -- {h1_br, h1_bry1, h1_bry0} -- inst_data[127:112]
//pre_code[20:18] -- {h2_br, h2_bry1, h2_bry0} -- inst_data[111: 96]
//pre_code[17:15] -- {h3_br, h3_bry1, h3_bry0} -- inst_data[ 95: 80]
//pre_code[14:12] -- {h4_br, h4_bry1, h4_bry0} -- inst_data[ 79: 64]
//pre_code[11: 9] -- {h5_br, h5_bry1, h5_bry0} -- inst_data[ 63: 48]
//pre_code[ 8: 6] -- {h6_br, h6_bry1, h6_bry0} -- inst_data[ 47: 32]
//pre_code[ 5: 3] -- {h7_br, h7_bry1, h7_bry0} -- inst_data[ 31: 16]
//pre_code[ 2: 0] -- {h8_br, h8_bry1, h8_bry0} -- inst_data[ 15: 0]
assign h1_data[15:0] = inst_data[127:112];
assign h2_data[15:0] = inst_data[111: 96];
assign h3_data[15:0] = inst_data[ 95: 80];
assign h4_data[15:0] = inst_data[ 79: 64];
assign h5_data[15:0] = inst_data[ 63: 48];
assign h6_data[15:0] = inst_data[ 47: 32];
assign h7_data[15:0] = inst_data[ 31: 16];
assign h8_data[15:0] = inst_data[ 15: 0];
//hn_br
assign h1_br = (h1_data[6:0] == 7'b1101111) || //jal
({h1_data[14:12],h1_data[6:0]} == 10'b000_1100011) || //beq
({h1_data[14:12],h1_data[6:0]} == 10'b001_1100011) || //bne
({h1_data[14:12],h1_data[6:0]} == 10'b100_1100011) || //blt
({h1_data[14:12],h1_data[6:0]} == 10'b101_1100011) || //bge
({h1_data[14:12],h1_data[6:0]} == 10'b110_1100011) || //bltu
({h1_data[14:12],h1_data[6:0]} == 10'b111_1100011) || //bgeu
({h1_data[15:14],h1_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h1_data[15:13],h1_data[1:0]} == 5'b10101); //c.j
assign h2_br = (h2_data[6:0] == 7'b1101111) || //jal
({h2_data[14:12],h2_data[6:0]} == 10'b000_1100011) || //beq
({h2_data[14:12],h2_data[6:0]} == 10'b001_1100011) || //bne
({h2_data[14:12],h2_data[6:0]} == 10'b100_1100011) || //blt
({h2_data[14:12],h2_data[6:0]} == 10'b101_1100011) || //bge
({h2_data[14:12],h2_data[6:0]} == 10'b110_1100011) || //bltu
({h2_data[14:12],h2_data[6:0]} == 10'b111_1100011) || //bgeu
({h2_data[15:14],h2_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h2_data[15:13],h2_data[1:0]} == 5'b10101); //c.j
assign h3_br = (h3_data[6:0] == 7'b1101111) || //jal
({h3_data[14:12],h3_data[6:0]} == 10'b000_1100011) || //beq
({h3_data[14:12],h3_data[6:0]} == 10'b001_1100011) || //bne
({h3_data[14:12],h3_data[6:0]} == 10'b100_1100011) || //blt
({h3_data[14:12],h3_data[6:0]} == 10'b101_1100011) || //bge
({h3_data[14:12],h3_data[6:0]} == 10'b110_1100011) || //bltu
({h3_data[14:12],h3_data[6:0]} == 10'b111_1100011) || //bgeu
({h3_data[15:14],h3_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h3_data[15:13],h3_data[1:0]} == 5'b10101); //c.j
assign h4_br = (h4_data[6:0] == 7'b1101111) || //jal
({h4_data[14:12],h4_data[6:0]} == 10'b000_1100011) || //beq
({h4_data[14:12],h4_data[6:0]} == 10'b001_1100011) || //bne
({h4_data[14:12],h4_data[6:0]} == 10'b100_1100011) || //blt
({h4_data[14:12],h4_data[6:0]} == 10'b101_1100011) || //bge
({h4_data[14:12],h4_data[6:0]} == 10'b110_1100011) || //bltu
({h4_data[14:12],h4_data[6:0]} == 10'b111_1100011) || //bgeu
({h4_data[15:14],h4_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h4_data[15:13],h4_data[1:0]} == 5'b10101); //c.j
assign h5_br = (h5_data[6:0] == 7'b1101111) || //jal
({h5_data[14:12],h5_data[6:0]} == 10'b000_1100011) || //beq
({h5_data[14:12],h5_data[6:0]} == 10'b001_1100011) || //bne
({h5_data[14:12],h5_data[6:0]} == 10'b100_1100011) || //blt
({h5_data[14:12],h5_data[6:0]} == 10'b101_1100011) || //bge
({h5_data[14:12],h5_data[6:0]} == 10'b110_1100011) || //bltu
({h5_data[14:12],h5_data[6:0]} == 10'b111_1100011) || //bgeu
({h5_data[15:14],h5_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h5_data[15:13],h5_data[1:0]} == 5'b10101); //c.j
assign h6_br = (h6_data[6:0] == 7'b1101111) || //jal
({h6_data[14:12],h6_data[6:0]} == 10'b000_1100011) || //beq
({h6_data[14:12],h6_data[6:0]} == 10'b001_1100011) || //bne
({h6_data[14:12],h6_data[6:0]} == 10'b100_1100011) || //blt
({h6_data[14:12],h6_data[6:0]} == 10'b101_1100011) || //bge
({h6_data[14:12],h6_data[6:0]} == 10'b110_1100011) || //bltu
({h6_data[14:12],h6_data[6:0]} == 10'b111_1100011) || //bgeu
({h6_data[15:14],h6_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h6_data[15:13],h6_data[1:0]} == 5'b10101); //c.j
assign h7_br = (h7_data[6:0] == 7'b1101111) || //jal
({h7_data[14:12],h7_data[6:0]} == 10'b000_1100011) || //beq
({h7_data[14:12],h7_data[6:0]} == 10'b001_1100011) || //bne
({h7_data[14:12],h7_data[6:0]} == 10'b100_1100011) || //blt
({h7_data[14:12],h7_data[6:0]} == 10'b101_1100011) || //bge
({h7_data[14:12],h7_data[6:0]} == 10'b110_1100011) || //bltu
({h7_data[14:12],h7_data[6:0]} == 10'b111_1100011) || //bgeu
({h7_data[15:14],h7_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h7_data[15:13],h7_data[1:0]} == 5'b10101); //c.j
assign h8_br = (h8_data[6:0] == 7'b1101111) || //jal
({h8_data[14:12],h8_data[6:0]} == 10'b000_1100011) || //beq
({h8_data[14:12],h8_data[6:0]} == 10'b001_1100011) || //bne
({h8_data[14:12],h8_data[6:0]} == 10'b100_1100011) || //blt
({h8_data[14:12],h8_data[6:0]} == 10'b101_1100011) || //bge
({h8_data[14:12],h8_data[6:0]} == 10'b110_1100011) || //bltu
({h8_data[14:12],h8_data[6:0]} == 10'b111_1100011) || //bgeu
({h8_data[15:14],h8_data[1:0]} == 4'b1101) || //c.beqz/c.bnez
({h8_data[15:13],h8_data[1:0]} == 5'b10101); //c.j
//hn_ab_br
assign h1_ab_br = (h1_data[6:0] == 7'b1101111) || //jal
({h1_data[15:13],h1_data[1:0]} == 5'b10101); //c.j
assign h2_ab_br = (h2_data[6:0] == 7'b1101111) || //jal
({h2_data[15:13],h2_data[1:0]} == 5'b10101); //c.j
assign h3_ab_br = (h3_data[6:0] == 7'b1101111) || //jal
({h3_data[15:13],h3_data[1:0]} == 5'b10101); //c.j
assign h4_ab_br = (h4_data[6:0] == 7'b1101111) || //jal
({h4_data[15:13],h4_data[1:0]} == 5'b10101); //c.j
assign h5_ab_br = (h5_data[6:0] == 7'b1101111) || //jal
({h5_data[15:13],h5_data[1:0]} == 5'b10101); //c.j
assign h6_ab_br = (h6_data[6:0] == 7'b1101111) || //jal
({h6_data[15:13],h6_data[1:0]} == 5'b10101); //c.j
assign h7_ab_br = (h7_data[6:0] == 7'b1101111) || //jal
({h7_data[15:13],h7_data[1:0]} == 5'b10101); //c.j
assign h8_ab_br = (h8_data[6:0] == 7'b1101111) || //jal
({h8_data[15:13],h8_data[1:0]} == 5'b10101); //c.j
//hn_bry1 : suppose h1 is the start of one inst
assign h1_bry1_32 = (h1_data[1:0] == 2'b11);
assign h1_bry1 = 1'b1;
assign h2_bry1_32 = (h2_data[1:0] == 2'b11) && !h1_bry1_32;
assign h2_bry1_16 = !(h2_data[1:0] == 2'b11) && !h1_bry1_32;
assign h2_bry1 = h2_bry1_32 || h2_bry1_16;
assign h3_bry1_32 = (h3_data[1:0] == 2'b11) && !h2_bry1_32;
assign h3_bry1_16 = !(h3_data[1:0] == 2'b11) && !h2_bry1_32;
assign h3_bry1 = h3_bry1_32 || h3_bry1_16;
assign h4_bry1_32 = (h4_data[1:0] == 2'b11) && !h3_bry1_32;
assign h4_bry1_16 = !(h4_data[1:0] == 2'b11) && !h3_bry1_32;
assign h4_bry1 = h4_bry1_32 || h4_bry1_16;
assign h5_bry1_32 = (h5_data[1:0] == 2'b11) && !h4_bry1_32;
assign h5_bry1_16 = !(h5_data[1:0] == 2'b11) && !h4_bry1_32;
assign h5_bry1 = h5_bry1_32 || h5_bry1_16;
assign h6_bry1_32 = (h6_data[1:0] == 2'b11) && !h5_bry1_32;
assign h6_bry1_16 = !(h6_data[1:0] == 2'b11) && !h5_bry1_32;
assign h6_bry1 = h6_bry1_32 || h6_bry1_16;
assign h7_bry1_32 = (h7_data[1:0] == 2'b11) && !h6_bry1_32;
assign h7_bry1_16 = !(h7_data[1:0] == 2'b11) && !h6_bry1_32;
assign h7_bry1 = h7_bry1_32 || h7_bry1_16;
assign h8_bry1_32 = (h8_data[1:0] == 2'b11) && !h7_bry1_32;
assign h8_bry1_16 = !(h8_data[1:0] == 2'b11) && !h7_bry1_32;
assign h8_bry1 = h8_bry1_32 || h8_bry1_16;
//hn_bry0 : suppose h1 is not the start of one inst
assign h1_bry0 = 1'b0;
assign h2_bry0_32 = (h2_data[1:0] == 2'b11);
assign h2_bry0 = 1'b1;
assign h3_bry0_32 = (h3_data[1:0] == 2'b11) && !h2_bry0_32;
assign h3_bry0_16 = !(h3_data[1:0] == 2'b11) && !h2_bry0_32;
assign h3_bry0 = h3_bry0_32 || h3_bry0_16;
assign h4_bry0_32 = (h4_data[1:0] == 2'b11) && !h3_bry0_32;
assign h4_bry0_16 = !(h4_data[1:0] == 2'b11) && !h3_bry0_32;
assign h4_bry0 = h4_bry0_32 || h4_bry0_16;
assign h5_bry0_32 = (h5_data[1:0] == 2'b11) && !h4_bry0_32;
assign h5_bry0_16 = !(h5_data[1:0] == 2'b11) && !h4_bry0_32;
assign h5_bry0 = h5_bry0_32 || h5_bry0_16;
assign h6_bry0_32 = (h6_data[1:0] == 2'b11) && !h5_bry0_32;
assign h6_bry0_16 = !(h6_data[1:0] == 2'b11) && !h5_bry0_32;
assign h6_bry0 = h6_bry0_32 || h6_bry0_16;
assign h7_bry0_32 = (h7_data[1:0] == 2'b11) && !h6_bry0_32;
assign h7_bry0_16 = !(h7_data[1:0] == 2'b11) && !h6_bry0_32;
assign h7_bry0 = h7_bry0_32 || h7_bry0_16;
assign h8_bry0_32 = (h8_data[1:0] == 2'b11) && !h7_bry0_32;
assign h8_bry0_16 = !(h8_data[1:0] == 2'b11) && !h7_bry0_32;
assign h8_bry0 = h8_bry0_32 || h8_bry0_16;
//Merge
assign h1_pre_code[3:0] = {h1_ab_br,h1_br, h1_bry1, h1_bry0};
assign h2_pre_code[3:0] = {h2_ab_br,h2_br, h2_bry1, h2_bry0};
assign h3_pre_code[3:0] = {h3_ab_br,h3_br, h3_bry1, h3_bry0};
assign h4_pre_code[3:0] = {h4_ab_br,h4_br, h4_bry1, h4_bry0};
assign h5_pre_code[3:0] = {h5_ab_br,h5_br, h5_bry1, h5_bry0};
assign h6_pre_code[3:0] = {h6_ab_br,h6_br, h6_bry1, h6_bry0};
assign h7_pre_code[3:0] = {h7_ab_br,h7_br, h7_bry1, h7_bry0};
assign h8_pre_code[3:0] = {h8_ab_br,h8_br, h8_bry1, h8_bry0};
assign pre_code[31:0] = {h1_pre_code[3:0],
h2_pre_code[3:0],
h3_pre_code[3:0],
h4_pre_code[3:0],
h5_pre_code[3:0],
h6_pre_code[3:0],
h7_pre_code[3:0],
h8_pre_code[3:0]};
// &ModuleEnd; @235
endmodule |
module ct_ifu_decd_normal(
cp0_ifu_vl,
cp0_ifu_vsetvli_pred_disable,
x_auipc,
x_br,
x_branch,
x_chgflw,
x_con_br,
x_dst_vld,
x_ind_br,
x_inst,
x_jal,
x_jalr,
x_ld,
x_offset,
x_pc_oper,
x_pcall,
x_preturn,
x_st,
x_vlmax,
x_vlmul,
x_vsetvli,
x_vsew
);
// &Ports; @26
input [7 :0] cp0_ifu_vl;
input cp0_ifu_vsetvli_pred_disable;
input x_br;
input [31:0] x_inst;
output x_auipc;
output x_branch;
output x_chgflw;
output x_con_br;
output x_dst_vld;
output x_ind_br;
output x_jal;
output x_jalr;
output x_ld;
output [20:0] x_offset;
output x_pc_oper;
output x_pcall;
output x_preturn;
output x_st;
output [7 :0] x_vlmax;
output [1 :0] x_vlmul;
output x_vsetvli;
output [2 :0] x_vsew;
// &Regs; @27
// &Wires; @28
wire [7 :0] cp0_ifu_vl;
wire cp0_ifu_vsetvli_pred_disable;
wire x_ab_br;
wire x_auipc;
wire x_br;
wire x_branch;
wire x_chgflw;
wire x_con_br;
wire x_dst_vld;
wire x_ind_br;
wire [31:0] x_inst;
wire x_jal;
wire x_jalr;
wire x_ld;
wire [20:0] x_offset;
wire [20:0] x_offset_12_ab_br;
wire x_offset_12_ab_br_vld;
wire [20:0] x_offset_12_ind_br;
wire x_offset_12_ind_br_vld;
wire [20:0] x_offset_13_con_br;
wire x_offset_13_con_br_vld;
wire [20:0] x_offset_21_ab_br;
wire x_offset_21_ab_br_vld;
wire [20:0] x_offset_9_con_br;
wire x_offset_9_con_br_vld;
wire x_pc_oper;
wire x_pcall;
wire x_preturn;
wire x_st;
wire [7 :0] x_vlmax;
wire [1 :0] x_vlmul;
wire x_vsetvli;
wire [2 :0] x_vsew;
//==========================================================
// Decode Normal Type
//==========================================================
// &Force("bus","x_inst",31,0); @34
//Hn_ab_br
assign x_ab_br = x_br &&
(
(x_inst[2:1] == 2'b11) || //jal
({x_inst[14],x_inst[1]} == 2'b00) //c.j
);
//Hn_con_br
assign x_con_br = x_br &&
(
(x_inst[2:1] == 2'b01) || //32-bit con-br
({x_inst[14],x_inst[1]} == 2'b10) //16-bit con-br
);
// &Force("output","x_con_br"); @48
//Hn_auipc
assign x_auipc = (x_inst[6:0] == 7'b0010111); //auipc
// &Force("output","x_auipc"); @52
//Hn_pc_oper
assign x_pc_oper = x_br ||
({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) || //jalr
({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) || //c.jr/c.jalr
(x_inst[6:0] == 7'b0010111); //auipc
// &Force("output","x_pc_oper"); @59
//Hn_chgflw_not_br
//contain all the chgflw inst except con_br
assign x_chgflw = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) || //jalr
({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) || //c.jr/c.jalr
x_ab_br;
// &Force("output","x_chgflw"); @66
//Hn_branch
//contain all the branch inst include con_br
assign x_branch = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) || //jalr
({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) || //c.jr/c.jalr
x_br;
// &Force("output","x_branch"); @73
//Hn_jal
assign x_jal = (x_inst[6:0] == 7'b1101111) || //jal
({x_inst[15:13], x_inst[1:0]} == 5'b10101); //c.j
// &Force("output","x_jal"); @78
//Hn_jalr
assign x_jalr = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) || //jalr
({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0); //c.jr/c.jalr
// &Force("output","x_jalr"); @83
//Hn_dst_vld
assign x_dst_vld = ((x_inst[6:0] == 7'b1101111) || ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111)) && (x_inst[11:7] != 5'b0)
|| ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && (x_inst[11:7] != 5'b0);
//==========================================================
// Decode Indrect Branch
//==========================================================
//Pcall and Preturn judgement
// +-------+-------+--------+--------------+
// | rd | rs1 | rs1=rd | RAS action |
// +-------+-------+--------+--------------+
// | !link | !link | - | none |
// +-------+-------+--------+--------------+
// | !link | link | - | pop |
// +-------+-------+--------+--------------+
// | link | !link | - | push |
// +-------+-------+--------+--------------+
// | link | link | 0 | push and pop |
// +-------+-------+--------+--------------+
// | link | link | 1 | push |
// +-------+-------+--------+--------------+
//Hn_pcall
//1. jalr: rd == x1 or rd == x5
//2. jal : rd == x1 or rd == x5
//3. c.jalr
assign x_pcall = (
({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) && //jalr
(
(x_inst[11:7] == 5'b00001) ||
(x_inst[11:7] == 5'b00101)
)
) ||
(
(x_inst[6:0] == 7'b1101111) && //jal
(
(x_inst[11:7] == 5'b00001) ||
(x_inst[11:7] == 5'b00101)
)
) ||
(
({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && //c.jalr
(x_inst[11:7] != 5'b0)
);
//Hn_preturn
//1. jalr: when rs1 == x1 or rs1 == x5 and rs1!=rd
//2. c.jr: when rs1 ==x1 or rs1 == x5
//3. c.jalr: when rs1 == x5(c.jalr use x1 as default rd)
assign x_preturn = (
({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) && //jalr
(x_inst[11:7] != x_inst[19:15]) &&
(
(x_inst[19:15] == 5'b00001) ||
(x_inst[19:15] == 5'b00101)
) &&
(x_inst[31:20] == 12'b0)
) ||
(
({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) && //c.jr
(
(x_inst[11:7] == 5'b00001) ||
(x_inst[11:7] == 5'b00101)
) &&
(x_inst[11:7] != 5'b00000)
) ||
(
({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && //c.jalr
(x_inst[11:7] == 5'b00101)
);
//Hn_ind_jmp
assign x_ind_br = (
({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) && //jalr
(
(
((x_inst[19:15] != 5'b1) &&
(x_inst[19:15] != 5'b00101)
) ||
(x_inst[31:20] != 12'b0)
) ||
(x_inst[11:7] == x_inst[19:15])
)
) ||
(
({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) && //c.jr
!(x_inst[11:7] == 5'b00001) &&
!(x_inst[11:7] == 5'b00101) &&
!(x_inst[11:7] == 5'b0)
) ||
(
({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && //c.jalr
!(x_inst[11:7] == 5'b00101) && !(x_inst[11:7] == 5'b0)
);
//==========================================================
// Decode Store Inst
//==========================================================
// &Force("bus","x_inst",31,0); @187
assign x_st = ({x_inst[14:12],x_inst[6:0]} == 10'b000_0100011) //sb
|| ({x_inst[14:12],x_inst[6:0]} == 10'b001_0100011) //sh
|| ({x_inst[14:12],x_inst[6:0]} == 10'b010_0100011) //sw
|| ({x_inst[14:12],x_inst[6:0]} == 10'b011_0100011) //sd
|| (x_inst[6:0] == 7'b0100111) //fsh/fsw/fsd/vfst
|| ({x_inst[15:13],x_inst[1:0]} == 5'b101_00) //c.fsd
|| ({x_inst[15:13],x_inst[1:0]} == 5'b110_00) //c.sw
|| ({x_inst[15:13],x_inst[1:0]} == 5'b111_00) //c.sd
|| ({x_inst[15:13],x_inst[1:0]} == 5'b101_10) //c.fsdsp
|| ({x_inst[15:13],x_inst[1:0]} == 5'b110_10) //c.swsp
|| ({x_inst[15:13],x_inst[1:0]} == 5'b111_10) //c.sdsp
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_101_0001011) //srb
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_101_0001011) //srh
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_101_0001011) //srw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_101_0001011) //srd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_101_0001011) //surb
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_101_0001011) //surh
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_101_0001011) //surw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_101_0001011) //surd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_101_0001011) //sbib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_101_0001011) //sbia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_101_0001011) //shib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_101_0001011) //shia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_101_0001011) //swib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_101_0001011) //swia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_101_0001011) //sdib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_101_0001011) //sdia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_101_0001011) //swd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_101_0001011) //sdd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_111_0001011) //fsrw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_111_0001011) //fsrd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_111_0001011) //fsurw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_111_0001011); //fsurd
//==========================================================
// Decode lsfifo Instruction
//==========================================================
assign x_ld=({x_inst[14:12],x_inst[6:0]} == 10'b000_0000011) //lb
|| ({x_inst[14:12],x_inst[6:0]} == 10'b001_0000011) //lh
|| ({x_inst[14:12],x_inst[6:0]} == 10'b010_0000011) //lw
|| ({x_inst[14:12],x_inst[6:0]} == 10'b011_0000011) //ld
|| ({x_inst[14:12],x_inst[6:0]} == 10'b100_0000011) //lbu
|| ({x_inst[14:12],x_inst[6:0]} == 10'b101_0000011) //lhu
|| ({x_inst[14:12],x_inst[6:0]} == 10'b110_0000011) //lwu
|| (x_inst[6:0] == 7'b0000111) //flh/flw/fld/vfld
|| ({x_inst[15:13],x_inst[1:0]} == 5'b001_00) //c.fld
|| ({x_inst[15:13],x_inst[1:0]} == 5'b010_00) //c.lw
|| ({x_inst[15:13],x_inst[1:0]} == 5'b011_00) //c.ld
|| ({x_inst[15:13],x_inst[1:0]} == 5'b001_10) //c.fldsp
|| ({x_inst[15:13],x_inst[1:0]} == 5'b010_10) //c.lwsp
&& (x_inst[11:7] != 5'b0)
|| ({x_inst[15:13],x_inst[1:0]} == 5'b011_10) //c.ldsp
&& (x_inst[11:7] != 5'b0)
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_100_0001011) //lrb
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_100_0001011) //lrh
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_100_0001011) //lrw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_100_0001011) //lrd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10000_100_0001011) //lrbu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10100_100_0001011) //lrhu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11000_100_0001011) //lrwu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_100_0001011) //lurb
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_100_0001011) //lurh
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_100_0001011) //lurw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_100_0001011) //lurd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10010_100_0001011) //lurbu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10110_100_0001011) //lurhu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11010_100_0001011) //lurwu
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_100_0001011) //lbib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_100_0001011) //lbia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_100_0001011) //lhib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_100_0001011) //lhia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_100_0001011) //lwib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_100_0001011) //lwia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_100_0001011) //ldib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_100_0001011) //ldia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10001_100_0001011) //lbuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10011_100_0001011) //lbuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10101_100_0001011) //lhuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10111_100_0001011) //lhuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11001_100_0001011) //lwuib
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11011_100_0001011) //lwuia
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_100_0001011) //lwd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11110_100_0001011) //lwud
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_100_0001011) //ldd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_110_0001011) //flrw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_110_0001011) //flrd
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_110_0001011) //flurw
|| ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_110_0001011); //flurd
//==========================================================
// Decode Vtype Inst
//==========================================================
//vsetvli inst :
//-----+----------------+---------+-------+-------+---------------+
// 31 |30 20|19 15|14 12|11 7|6 0 |
// 1 | zimm[10:0] | rs1 | 1 1 1 | rd | 1 0 1 0 1 1 1 |
//-----+----------------+---------+-------+-------+---------------+
assign x_vsetvli = !x_inst[31]
&& (x_inst[14:12] == 3'b111)
&& (x_inst[6:0] == 7'b1010111);
//vlmul & vsew
//zimm[10:0]:
//10:7: Reserverd
// 6:5: vediv, Used for EDIV extention,reserved for xuantie910
// 4:2: vsew,standard element width setting
// 1:0: vlmul,vector register group multiplier setting
assign x_vsew[2:0] = x_inst[24:22];
assign x_vlmul[1:0] = x_inst[21:20];
assign x_vlmax[7:0] = (cp0_ifu_vsetvli_pred_disable)
? cp0_ifu_vl[7:0]
: ((8'b00010000 >> x_inst[23:22]) <<x_inst[21:20]);
//==========================================================
// Decode Immediate Offset
//==========================================================
assign x_offset_21_ab_br_vld = (x_inst[6:0] == 7'b1101111); //JAL
assign x_offset_21_ab_br[20:0] = {
x_inst[31],
x_inst[19:12],
x_inst[20],
x_inst[30:21],
1'b0
};
assign x_offset_12_ind_br_vld = (x_inst[6:0] == 7'b1100111); //JARL
assign x_offset_12_ind_br[20:0] = {
{9{x_inst[31]}},
x_inst[31:20]
};
assign x_offset_13_con_br_vld = (x_inst[6:0] == 7'b1100011); //BEQ/BNE/BLT/BGE/BLTU/BGEU
assign x_offset_13_con_br[20:0] = {
{9{x_inst[31]}},
x_inst[7],
x_inst[30:25],
x_inst[11:8],
1'b0
};
assign x_offset_12_ab_br_vld = ({x_inst[15:13],x_inst[1:0]} == 5'b10101); //C.J
assign x_offset_12_ab_br[20:0] = {
{10{x_inst[12]}},
x_inst[8],
x_inst[10:9],
x_inst[6],
x_inst[7],
x_inst[2],
x_inst[11],
x_inst[5:3],
1'b0
};
assign x_offset_9_con_br_vld = ({x_inst[15:14],x_inst[1:0]} == 4'b1101); //C.BEQZ/C.BNEZ
assign x_offset_9_con_br[20:0] = {
{13{x_inst[12]}},
x_inst[6:5],
x_inst[2],
x_inst[11:10],
x_inst[4:3],
1'b0
};
//default will choose 0 as C.J/C.JARL result
assign x_offset[20:0] =
{21{x_offset_21_ab_br_vld}} & x_offset_21_ab_br[20:0]
| {21{x_offset_12_ind_br_vld}} & x_offset_12_ind_br[20:0]
| {21{x_offset_13_con_br_vld}} & x_offset_13_con_br[20:0]
| {21{x_offset_12_ab_br_vld}} & x_offset_12_ab_br[20:0]
| {21{x_offset_9_con_br_vld}} & x_offset_9_con_br[20:0];
// &ModuleEnd; @361
endmodule |
module ct_ifu_addrgen(
addrgen_btb_index,
addrgen_btb_tag,
addrgen_btb_target_pc,
addrgen_btb_update_vld,
addrgen_ibctrl_cancel,
addrgen_ipdp_chgflw_vl,
addrgen_ipdp_chgflw_vlmul,
addrgen_ipdp_chgflw_vsew,
addrgen_l0_btb_update_entry,
addrgen_l0_btb_update_vld,
addrgen_l0_btb_update_vld_bit,
addrgen_l0_btb_wen,
addrgen_pcgen_pc,
addrgen_pcgen_pcload,
addrgen_xx_pcload,
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
forever_cpuclk,
ibdp_addrgen_branch_base,
ibdp_addrgen_branch_offset,
ibdp_addrgen_branch_result,
ibdp_addrgen_branch_valid,
ibdp_addrgen_branch_vl,
ibdp_addrgen_branch_vlmul,
ibdp_addrgen_branch_vsew,
ibdp_addrgen_btb_index_pc,
ibdp_addrgen_l0_btb_hit,
ibdp_addrgen_l0_btb_hit_entry,
ifu_hpcp_btb_inst,
ifu_hpcp_btb_mispred,
lbuf_addrgen_active_state,
lbuf_addrgen_cache_state,
lbuf_addrgen_chgflw_mask,
pad_yy_icg_scan_en,
pcgen_addrgen_cancel
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input forever_cpuclk;
input [38:0] ibdp_addrgen_branch_base;
input [20:0] ibdp_addrgen_branch_offset;
input [38:0] ibdp_addrgen_branch_result;
input ibdp_addrgen_branch_valid;
input [7 :0] ibdp_addrgen_branch_vl;
input [1 :0] ibdp_addrgen_branch_vlmul;
input [2 :0] ibdp_addrgen_branch_vsew;
input [38:0] ibdp_addrgen_btb_index_pc;
input ibdp_addrgen_l0_btb_hit;
input [15:0] ibdp_addrgen_l0_btb_hit_entry;
input lbuf_addrgen_active_state;
input lbuf_addrgen_cache_state;
input lbuf_addrgen_chgflw_mask;
input pad_yy_icg_scan_en;
input pcgen_addrgen_cancel;
output [9 :0] addrgen_btb_index;
output [9 :0] addrgen_btb_tag;
output [19:0] addrgen_btb_target_pc;
output addrgen_btb_update_vld;
output addrgen_ibctrl_cancel;
output [7 :0] addrgen_ipdp_chgflw_vl;
output [1 :0] addrgen_ipdp_chgflw_vlmul;
output [2 :0] addrgen_ipdp_chgflw_vsew;
output [15:0] addrgen_l0_btb_update_entry;
output addrgen_l0_btb_update_vld;
output addrgen_l0_btb_update_vld_bit;
output [3 :0] addrgen_l0_btb_wen;
output [38:0] addrgen_pcgen_pc;
output addrgen_pcgen_pcload;
output addrgen_xx_pcload;
output ifu_hpcp_btb_inst;
output ifu_hpcp_btb_mispred;
// &Regs; @24
reg [9 :0] addrgen_branch_index;
reg [9 :0] addrgen_branch_tag;
reg [7 :0] addrgen_branch_vl;
reg [1 :0] addrgen_branch_vlmul;
reg [2 :0] addrgen_branch_vsew;
reg addrgen_btb_mispred;
reg [38:0] addrgen_cal_result_flop;
reg addrgen_l0_btb_hit;
reg [15:0] addrgen_l0_btb_hit_entry;
reg addrgen_vld;
// &Wires; @25
wire [9 :0] addrgen_btb_index;
wire [9 :0] addrgen_btb_tag;
wire [19:0] addrgen_btb_target_pc;
wire addrgen_btb_update_vld;
wire addrgen_flop_clk;
wire addrgen_flop_clk_en;
wire addrgen_ibctrl_cancel;
wire [7 :0] addrgen_ipdp_chgflw_vl;
wire [1 :0] addrgen_ipdp_chgflw_vlmul;
wire [2 :0] addrgen_ipdp_chgflw_vsew;
wire [15:0] addrgen_l0_btb_update_entry;
wire addrgen_l0_btb_update_vld;
wire addrgen_l0_btb_update_vld_bit;
wire [3 :0] addrgen_l0_btb_wen;
wire [38:0] addrgen_pcgen_pc;
wire addrgen_pcgen_pcload;
wire addrgen_xx_pcload;
wire [38:0] branch_base;
wire [38:0] branch_cal_result;
wire [9 :0] branch_index;
wire branch_mispred;
wire [38:0] branch_offset;
wire [38:0] branch_pred_result;
wire [9 :0] branch_tag;
wire [7 :0] branch_vl;
wire branch_vld;
wire branch_vld_for_gateclk;
wire [1 :0] branch_vlmul;
wire [2 :0] branch_vsew;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire forever_cpuclk;
wire [38:0] ibdp_addrgen_branch_base;
wire [20:0] ibdp_addrgen_branch_offset;
wire [38:0] ibdp_addrgen_branch_result;
wire ibdp_addrgen_branch_valid;
wire [7 :0] ibdp_addrgen_branch_vl;
wire [1 :0] ibdp_addrgen_branch_vlmul;
wire [2 :0] ibdp_addrgen_branch_vsew;
wire [38:0] ibdp_addrgen_btb_index_pc;
wire ibdp_addrgen_l0_btb_hit;
wire [15:0] ibdp_addrgen_l0_btb_hit_entry;
wire ifu_hpcp_btb_inst;
wire ifu_hpcp_btb_mispred;
wire l0_btb_hit;
wire [15:0] l0_btb_hit_entry;
wire l0_btb_update_vld;
wire [3 :0] l0_btb_wen;
wire lbuf_addrgen_active_state;
wire lbuf_addrgen_cache_state;
wire lbuf_addrgen_chgflw_mask;
wire pad_yy_icg_scan_en;
wire pcgen_addrgen_cancel;
parameter PC_WIDTH = 40;
// &Force("bus","ibdp_addrgen_branch_offset",20,0); @27
// &Force("bus","ibdp_addrgen_btb_index_pc",38,0); @28
//==========================================================
// Branch Adder Result Calculate
//==========================================================
//The reason why addrgen should not chgflw when lbuf cache state:
//When lbuf cache state, the miss/mispred branch can only be loop end
//While for loop end branch, we will not use BTB target as target PC
//We use Loop Buffer adder get its target and it will not mispred/miss
assign branch_vld_for_gateclk = ibdp_addrgen_branch_valid &&
!lbuf_addrgen_active_state &&
!lbuf_addrgen_cache_state;
assign branch_vld = branch_vld_for_gateclk &&
!lbuf_addrgen_chgflw_mask;
assign branch_base[PC_WIDTH-2:0] = ibdp_addrgen_branch_base[PC_WIDTH-2:0];
assign branch_offset[PC_WIDTH-2:0] = {{19{ibdp_addrgen_branch_offset[20]}},ibdp_addrgen_branch_offset[20:1]};
assign branch_vlmul[1:0] = ibdp_addrgen_branch_vlmul[1:0];
assign branch_vsew[2:0] = ibdp_addrgen_branch_vsew[2:0];
assign branch_vl[7:0] = ibdp_addrgen_branch_vl[7:0];
assign branch_pred_result[PC_WIDTH-2:0] = ibdp_addrgen_branch_result[PC_WIDTH-2:0];
assign branch_cal_result[PC_WIDTH-2:0] = branch_base[PC_WIDTH-2:0] + branch_offset[PC_WIDTH-2:0];
assign branch_mispred = (branch_pred_result[PC_WIDTH-2:0] != branch_cal_result[PC_WIDTH-2:0]);
assign branch_index[9:0] = ibdp_addrgen_btb_index_pc[12:3];
assign branch_tag[9:0] = {ibdp_addrgen_btb_index_pc[19:13],
ibdp_addrgen_btb_index_pc[2:0]};
assign l0_btb_hit = ibdp_addrgen_l0_btb_hit;
assign l0_btb_hit_entry[15:0] = ibdp_addrgen_l0_btb_hit_entry[15:0];
//==========================================================
// Addrgen Flop Infor
//==========================================================
always @(posedge addrgen_flop_clk or negedge cpurst_b)
begin
if(!cpurst_b)
addrgen_vld <= 1'b0;
else if(pcgen_addrgen_cancel)
addrgen_vld <= 1'b0;
else
addrgen_vld <= branch_vld;
end
//_flop means the next cycle of addrgen IB stage
always @(posedge addrgen_flop_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
addrgen_cal_result_flop[PC_WIDTH-2:0] <= {PC_WIDTH-1{1'b0}};
addrgen_branch_index[9:0] <= 10'b0;
addrgen_branch_tag[9:0] <= 10'b0;
addrgen_btb_mispred <= 1'b0;
addrgen_branch_vlmul[1:0] <= 2'b0;
addrgen_branch_vsew[2:0] <= 3'b0;
addrgen_branch_vl[7:0] <= 8'b0;
addrgen_l0_btb_hit <= 1'b0;
addrgen_l0_btb_hit_entry[15:0] <= 16'b0;
end
else if(branch_vld)
begin
addrgen_cal_result_flop[PC_WIDTH-2:0] <= branch_cal_result[PC_WIDTH-2:0];
addrgen_branch_index[9:0] <= branch_index[9:0];
addrgen_branch_tag[9:0] <= branch_tag[9:0];
addrgen_btb_mispred <= branch_mispred;
addrgen_branch_vlmul[1:0] <= branch_vlmul[1:0];
addrgen_branch_vsew[2:0] <= branch_vsew[2:0];
addrgen_branch_vl[7:0] <= branch_vl[7:0];
addrgen_l0_btb_hit <= l0_btb_hit;
addrgen_l0_btb_hit_entry[15:0] <= l0_btb_hit_entry[15:0];
end
else
begin
addrgen_cal_result_flop[PC_WIDTH-2:0] <= addrgen_cal_result_flop[PC_WIDTH-2:0];
addrgen_branch_index[9:0] <= addrgen_branch_index[9:0];
addrgen_branch_tag[9:0] <= addrgen_branch_tag[9:0];
addrgen_btb_mispred <= addrgen_btb_mispred;
addrgen_branch_vlmul[1:0] <= addrgen_branch_vlmul[1:0];
addrgen_branch_vsew[2:0] <= addrgen_branch_vsew[2:0];
addrgen_branch_vl[7:0] <= addrgen_branch_vl[7:0];
addrgen_l0_btb_hit <= addrgen_l0_btb_hit;
addrgen_l0_btb_hit_entry[15:0] <= addrgen_l0_btb_hit_entry[15:0];
end
end
//Gate Clk
// &Instance("gated_clk_cell","x_addrgen_flop_clk"); @117
gated_clk_cell x_addrgen_flop_clk (
.clk_in (forever_cpuclk ),
.clk_out (addrgen_flop_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (addrgen_flop_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @118
// .clk_out (addrgen_flop_clk),//Out Clock @119
// .external_en (1'b0), @120
// .global_en (cp0_yy_clk_en), @121
// .local_en (addrgen_flop_clk_en),//Local Condition @122
// .module_en (cp0_ifu_icg_en) @123
// ); @124
assign addrgen_flop_clk_en = branch_vld_for_gateclk ||
addrgen_vld ||
pcgen_addrgen_cancel;
//==========================================================
// Addrgen Change Flow
//==========================================================
assign addrgen_pcgen_pcload = addrgen_vld && addrgen_btb_mispred;
assign addrgen_xx_pcload = addrgen_vld && addrgen_btb_mispred;
assign addrgen_pcgen_pc[PC_WIDTH-2:0] = addrgen_cal_result_flop[PC_WIDTH-2:0];
assign addrgen_ipdp_chgflw_vlmul[1:0] = addrgen_branch_vlmul[1:0];
assign addrgen_ipdp_chgflw_vsew[2:0] = addrgen_branch_vsew[2:0];
assign addrgen_ipdp_chgflw_vl[7:0] = addrgen_branch_vl[7:0];
assign addrgen_btb_index[9:0] = addrgen_branch_index[9:0];
assign addrgen_btb_tag[9:0] = addrgen_branch_tag[9:0];
assign addrgen_btb_target_pc[19:0] = addrgen_cal_result_flop[19:0];
assign addrgen_btb_update_vld = addrgen_pcgen_pcload;
// &Force("output","addrgen_pcgen_pcload"); @144
assign ifu_hpcp_btb_mispred = addrgen_vld && addrgen_btb_mispred;
assign ifu_hpcp_btb_inst = addrgen_vld;
//==========================================================
// Addrgen IB Cancel
//==========================================================
assign addrgen_ibctrl_cancel = addrgen_pcgen_pcload;
//==========================================================
// Addrgen L0 BTB Update
//==========================================================
assign l0_btb_update_vld = addrgen_vld
&& addrgen_btb_mispred
&& addrgen_l0_btb_hit;
assign l0_btb_wen[3] = l0_btb_update_vld;
assign l0_btb_wen[2:0] = 3'b0;
assign addrgen_l0_btb_update_vld = l0_btb_update_vld;
assign addrgen_l0_btb_wen[3:0] = l0_btb_wen[3:0];
assign addrgen_l0_btb_update_vld_bit = 1'b0;
assign addrgen_l0_btb_update_entry[15:0] = addrgen_l0_btb_hit_entry[15:0];
// &ModuleEnd; @169
endmodule |
module ct_ifu_bht_pre_array(
bht_pre_array_clk_en,
bht_pre_data_out,
bht_pred_array_cen_b,
bht_pred_array_din,
bht_pred_array_gwen,
bht_pred_array_index,
bht_pred_bwen,
cp0_ifu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input bht_pre_array_clk_en;
input bht_pred_array_cen_b;
input [63:0] bht_pred_array_din;
input bht_pred_array_gwen;
input [9 :0] bht_pred_array_index;
input [63:0] bht_pred_bwen;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [63:0] bht_pre_data_out;
// &Regs; @24
// &Wires; @25
wire bht_pre_array_clk_en;
wire bht_pre_clk;
wire [63:0] bht_pre_data_out;
wire bht_pre_en;
wire bht_pred_array_cen_b;
wire [63:0] bht_pred_array_din;
wire bht_pred_array_gwen;
wire [9 :0] bht_pred_array_index;
wire [63:0] bht_pred_bwen;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//Gate Clk
// &Instance("gated_clk_cell", "x_bht_pre_clk"); @28
gated_clk_cell x_bht_pre_clk (
.clk_in (forever_cpuclk ),
.clk_out (bht_pre_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (bht_pre_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in(forever_cpuclk), @29
// .external_en(1'b0), @30
// .global_en(cp0_yy_clk_en), @31
// .module_en(cp0_ifu_icg_en), @32
// .local_en(bht_pre_en), @33
// .clk_out(bht_pre_clk) @34
// ); @35
assign bht_pre_en = bht_pre_array_clk_en;
//Instance Logic
// &Instance("ct_spsram_1024x64", "x_ct_spsram_1024x64"); @40
ct_spsram_1024x64 x_ct_spsram_1024x64 (
.A (bht_pred_array_index),
.CEN (bht_pred_array_cen_b),
.CLK (bht_pre_clk ),
.D (bht_pred_array_din ),
.GWEN (bht_pred_array_gwen ),
.Q (bht_pre_data_out ),
.WEN (bht_pred_bwen )
);
// &Connect( @41
// .CLK (bht_pre_clk ), @42
// .Q (bht_pre_data_out ), @43
// .CEN (bht_pred_array_cen_b), @44
// .WEN (bht_pred_bwen ), @45
// .D (bht_pred_array_din ), @46
// .A (bht_pred_array_index), @47
// .GWEN (bht_pred_array_gwen ) @48
// ); @49
// &ModuleEnd; @51
endmodule |
module ct_ifu_btb_data_array(
btb_data_cen_b,
btb_data_clk_en,
btb_data_din,
btb_data_dout,
btb_data_wen,
btb_index,
cp0_ifu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
pad_yy_icg_scan_en
);
// &Ports; @23
input btb_data_cen_b;
input btb_data_clk_en;
input [43:0] btb_data_din;
input [3 :0] btb_data_wen;
input [9 :0] btb_index;
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input pad_yy_icg_scan_en;
output [87:0] btb_data_dout;
// &Regs; @24
// &Wires; @25
wire [43:0] btb_data_bwen_bank0;
wire [43:0] btb_data_bwen_bank1;
wire btb_data_cen_b;
wire btb_data_clk;
wire btb_data_clk_en;
wire [43:0] btb_data_din;
wire [87:0] btb_data_dout;
wire btb_data_en;
wire btb_data_gwen_bank0;
wire btb_data_gwen_bank1;
wire [3 :0] btb_data_wen;
wire [9 :0] btb_index;
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire pad_yy_icg_scan_en;
//Gate Clk
// &Instance("gated_clk_cell", "x_btb_data_clk"); @28
gated_clk_cell x_btb_data_clk (
.clk_in (forever_cpuclk ),
.clk_out (btb_data_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (btb_data_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in(forever_cpuclk), @29
// .external_en(1'b0), @30
// .global_en(cp0_yy_clk_en), @31
// .module_en(cp0_ifu_icg_en), @32
// .local_en(btb_data_en), @33
// .clk_out(btb_data_clk) @34
// ); @35
assign btb_data_en = btb_data_clk_en;
//Instance Logic
// &Force("bus","btb_index",9,0); @40
//Support Bit Write
assign btb_data_bwen_bank0[43:0] = {{22{btb_data_wen[1]}}, {22{btb_data_wen[0]}}};
assign btb_data_gwen_bank0 = btb_data_wen[1] && btb_data_wen[0];
assign btb_data_bwen_bank1[43:0] = {{22{btb_data_wen[3]}}, {22{btb_data_wen[2]}}};
assign btb_data_gwen_bank1 = btb_data_wen[3] && btb_data_wen[2];
//Icache Size define
// &Instance("ct_spsram_1024x44", "x_ct_spsram_1024x44_bank0"); @49
// &Connect( @50
// .CLK (btb_data_clk ), @51
// .Q (btb_data_dout[43:0] ), @52
// .CEN (btb_data_cen_b ), @53
// .WEN (btb_data_bwen_bank0 ), @54
// .D (btb_data_din ), @55
// .A (btb_index[9:0] ), @56
// .GWEN (btb_data_gwen_bank0 ) @57
// ); @58
// &Instance("ct_spsram_1024x44", "x_ct_spsram_1024x44_bank1"); @60
// &Connect( @61
// .CLK (btb_data_clk ), @62
// .Q (btb_data_dout[87:44] ), @63
// .CEN (btb_data_cen_b ), @64
// .WEN (btb_data_bwen_bank1 ), @65
// .D (btb_data_din ), @66
// .A (btb_index[9:0] ), @67
// .GWEN (btb_data_gwen_bank1 ) @68
// ); @69
// &Instance("ct_spsram_512x44", "x_ct_spsram_512x44_bank0"); @74
ct_spsram_512x44 x_ct_spsram_512x44_bank0 (
.A (btb_index[8:0] ),
.CEN (btb_data_cen_b ),
.CLK (btb_data_clk ),
.D (btb_data_din ),
.GWEN (btb_data_gwen_bank0),
.Q (btb_data_dout[43:0]),
.WEN (btb_data_bwen_bank0)
);
// &Connect( @75
// .CLK (btb_data_clk ), @76
// .Q (btb_data_dout[43:0] ), @77
// .CEN (btb_data_cen_b ), @78
// .WEN (btb_data_bwen_bank0 ), @79
// .D (btb_data_din ), @80
// .A (btb_index[8:0] ), @81
// .GWEN (btb_data_gwen_bank0 ) @82
// ); @83
// &Instance("ct_spsram_512x44", "x_ct_spsram_512x44_bank1"); @85
ct_spsram_512x44 x_ct_spsram_512x44_bank1 (
.A (btb_index[8:0] ),
.CEN (btb_data_cen_b ),
.CLK (btb_data_clk ),
.D (btb_data_din ),
.GWEN (btb_data_gwen_bank1 ),
.Q (btb_data_dout[87:44]),
.WEN (btb_data_bwen_bank1 )
);
// &Connect( @86
// .CLK (btb_data_clk ), @87
// .Q (btb_data_dout[87:44] ), @88
// .CEN (btb_data_cen_b ), @89
// .WEN (btb_data_bwen_bank1 ), @90
// .D (btb_data_din ), @91
// .A (btb_index[8:0] ), @92
// .GWEN (btb_data_gwen_bank1 ) @93
// ); @94
// &ModuleEnd; @99
endmodule |
module ct_ifu_ind_btb_array(
cp0_ifu_icg_en,
cp0_yy_clk_en,
forever_cpuclk,
ind_btb_cen_b,
ind_btb_clk_en,
ind_btb_data_in,
ind_btb_dout,
ind_btb_index,
ind_btb_wen_b,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input forever_cpuclk;
input ind_btb_cen_b;
input ind_btb_clk_en;
input [22:0] ind_btb_data_in;
input [7 :0] ind_btb_index;
input ind_btb_wen_b;
input pad_yy_icg_scan_en;
output [22:0] ind_btb_dout;
// &Regs; @24
// &Wires; @25
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire forever_cpuclk;
wire [22:0] ind_btb_bwen;
wire ind_btb_cen_b;
wire ind_btb_clk;
wire ind_btb_clk_en;
wire [22:0] ind_btb_data_in;
wire [22:0] ind_btb_dout;
wire [7 :0] ind_btb_index;
wire ind_btb_local_en;
wire ind_btb_wen_b;
wire pad_yy_icg_scan_en;
//Gate Clk
// &Instance("gated_clk_cell", "x_ind_btb_clk"); @28
gated_clk_cell x_ind_btb_clk (
.clk_in (forever_cpuclk ),
.clk_out (ind_btb_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ind_btb_local_en ),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);
// &Connect(.clk_in(forever_cpuclk), @29
// .external_en(1'b0), @30
// .global_en(cp0_yy_clk_en), @31
// .module_en(cp0_ifu_icg_en), @32
// .local_en(ind_btb_local_en), @33
// .clk_out(ind_btb_clk) @34
// ); @35
assign ind_btb_local_en = ind_btb_clk_en;
assign ind_btb_bwen[22:0] = {23{ind_btb_wen_b}};
//Instance Logic
// &Instance("ct_spsram_256x23", "x_ct_spsram_256x23"); @40
ct_spsram_256x23 x_ct_spsram_256x23 (
.A (ind_btb_index ),
.CEN (ind_btb_cen_b ),
.CLK (ind_btb_clk ),
.D (ind_btb_data_in),
.GWEN (ind_btb_wen_b ),
.Q (ind_btb_dout ),
.WEN (ind_btb_bwen )
);
// &Connect( @41
// .CLK (ind_btb_clk ), @42
// .Q (ind_btb_dout ), @43
// .CEN (ind_btb_cen_b ), @44
// .WEN (ind_btb_bwen ), @45
// .D (ind_btb_data_in), @46
// .A (ind_btb_index ), @47
// .GWEN (ind_btb_wen_b ) @48
// ); @49
// &ModuleEnd; @51
endmodule |
module ct_ifu_ibuf_entry(
cp0_ifu_icg_en,
cp0_yy_clk_en,
cpurst_b,
entry_32_start_x,
entry_acc_err_x,
entry_bkpta_x,
entry_bkptb_x,
entry_create_32_start_x,
entry_create_acc_err_x,
entry_create_bkpta_x,
entry_create_bkptb_x,
entry_create_fence_x,
entry_create_high_expt_x,
entry_create_inst_data_v,
entry_create_no_spec_x,
entry_create_pc_v,
entry_create_pgflt_x,
entry_create_split0_x,
entry_create_split1_x,
entry_create_vl_pred_x,
entry_create_vl_v,
entry_create_vlmul_v,
entry_create_vsew_v,
entry_create_x,
entry_data_create_clk_en_x,
entry_data_create_x,
entry_fence_x,
entry_high_expt_x,
entry_inst_data_v,
entry_no_spec_x,
entry_pc_create_clk_en_x,
entry_pc_create_x,
entry_pc_v,
entry_pgflt_x,
entry_retire_x,
entry_spe_data_vld,
entry_split0_x,
entry_split1_x,
entry_vl_pred_x,
entry_vl_v,
entry_vld_create_clk_en_x,
entry_vld_retire_clk_en_x,
entry_vld_x,
entry_vlmul_v,
entry_vsew_v,
forever_cpuclk,
ibuf_flush,
pad_yy_icg_scan_en
);
// &Ports; @23
input cp0_ifu_icg_en;
input cp0_yy_clk_en;
input cpurst_b;
input entry_create_32_start_x;
input entry_create_acc_err_x;
input entry_create_bkpta_x;
input entry_create_bkptb_x;
input entry_create_fence_x;
input entry_create_high_expt_x;
input [15:0] entry_create_inst_data_v;
input entry_create_no_spec_x;
input [14:0] entry_create_pc_v;
input entry_create_pgflt_x;
input entry_create_split0_x;
input entry_create_split1_x;
input entry_create_vl_pred_x;
input [7 :0] entry_create_vl_v;
input [1 :0] entry_create_vlmul_v;
input [2 :0] entry_create_vsew_v;
input entry_create_x;
input entry_data_create_clk_en_x;
input entry_data_create_x;
input entry_pc_create_clk_en_x;
input entry_pc_create_x;
input entry_retire_x;
input entry_spe_data_vld;
input entry_vld_create_clk_en_x;
input entry_vld_retire_clk_en_x;
input forever_cpuclk;
input ibuf_flush;
input pad_yy_icg_scan_en;
output entry_32_start_x;
output entry_acc_err_x;
output entry_bkpta_x;
output entry_bkptb_x;
output entry_fence_x;
output entry_high_expt_x;
output [15:0] entry_inst_data_v;
output entry_no_spec_x;
output [14:0] entry_pc_v;
output entry_pgflt_x;
output entry_split0_x;
output entry_split1_x;
output entry_vl_pred_x;
output [7 :0] entry_vl_v;
output entry_vld_x;
output [1 :0] entry_vlmul_v;
output [2 :0] entry_vsew_v;
// &Regs; @24
reg entry_32_start_x;
reg entry_acc_err_x;
reg entry_bkpta_x;
reg entry_bkptb_x;
reg entry_fence_x;
reg entry_high_expt_x;
reg [15:0] entry_inst_data_v;
reg entry_no_spec_x;
reg [14:0] entry_pc_v;
reg entry_pgflt_x;
reg entry_split0_x;
reg entry_split1_x;
reg entry_vl_pred_x;
reg [7 :0] entry_vl_v;
reg entry_vld_x;
reg [1 :0] entry_vlmul_v;
reg [2 :0] entry_vsew_v;
// &Wires; @25
wire cp0_ifu_icg_en;
wire cp0_yy_clk_en;
wire cpurst_b;
wire entry_create_32_start_x;
wire entry_create_acc_err_x;
wire entry_create_bkpta_x;
wire entry_create_bkptb_x;
wire entry_create_fence_x;
wire entry_create_high_expt_x;
wire [15:0] entry_create_inst_data_v;
wire entry_create_no_spec_x;
wire [14:0] entry_create_pc_v;
wire entry_create_pgflt_x;
wire entry_create_split0_x;
wire entry_create_split1_x;
wire entry_create_vl_pred_x;
wire [7 :0] entry_create_vl_v;
wire [1 :0] entry_create_vlmul_v;
wire [2 :0] entry_create_vsew_v;
wire entry_create_x;
wire entry_data_create_clk_en_x;
wire entry_data_create_x;
wire entry_pc_create_clk_en_x;
wire entry_pc_create_x;
wire entry_retire_x;
wire entry_spe_data_vld;
wire entry_vld_create_clk_en_x;
wire entry_vld_retire_clk_en_x;
wire forever_cpuclk;
wire ibuf_entry_pc_clk;
wire ibuf_entry_pc_clk_en;
wire ibuf_entry_spe_clk;
wire ibuf_entry_spe_clk_en;
wire ibuf_entry_update_clk;
wire ibuf_entry_update_clk_en;
wire ibuf_entry_vld_clk;
wire ibuf_entry_vld_clk_en;
wire ibuf_flush;
wire pad_yy_icg_scan_en;
//==========================================================
//Inst Buffer Entry Fields Description:
//+-----+------+----------+---------+-------+-----------+--------+--------+-------+
//| vld | inst | 32_start | acc_err | pgflt | high_expt | split1 | split0 | fence |
//+-----+------+----------+---------+-------+-----------+--------+--------+-------+
//==========================================================
//vld means entry valid
//inst[15:0] means the half word inst data
//32_start means this half is the start of 32 inst
//acc_err means this half have acc_err expt
//pgflt means this half have pgflt expt
//tinv means this half have tinv expt
//tfatal means this half have tfatal expt
//high_expt means 32 bit inst & expt happen at low half
//split1 means predecode info
//split0 means predecode info
//fence means predecode info
//==========================================================
// Entry Valid Signal
//==========================================================
//----------------------Gate Clock--------------------------
// &Instance("gated_clk_cell","x_ibuf_entry_vld_clk"); @49
gated_clk_cell x_ibuf_entry_vld_clk (
.clk_in (forever_cpuclk ),
.clk_out (ibuf_entry_vld_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ibuf_entry_vld_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @50
// .clk_out (ibuf_entry_vld_clk),//Out Clock @51
// .external_en (1'b0), @52
// .global_en (cp0_yy_clk_en), @53
// .local_en (ibuf_entry_vld_clk_en),//Local Condition @54
// .module_en (cp0_ifu_icg_en) @55
// ); @56
assign ibuf_entry_vld_clk_en = entry_vld_create_clk_en_x ||
entry_vld_retire_clk_en_x ||
ibuf_flush;
always @(posedge ibuf_entry_vld_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_vld_x <= 1'b0;
else if(ibuf_flush)
entry_vld_x <= 1'b0;
else if(entry_create_x)
entry_vld_x <= 1'b1;
else if(entry_retire_x)
entry_vld_x <= 1'b0;
else
entry_vld_x <= entry_vld_x;
end
//==========================================================
// Entry Data Signal
//==========================================================
//----------------------Gate Clock--------------------------
// &Instance("gated_clk_cell","x_ibuf_entry_update_clk"); @78
gated_clk_cell x_ibuf_entry_update_clk (
.clk_in (forever_cpuclk ),
.clk_out (ibuf_entry_update_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ibuf_entry_update_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @79
// .clk_out (ibuf_entry_update_clk),//Out Clock @80
// .external_en (1'b0), @81
// .global_en (cp0_yy_clk_en), @82
// .local_en (ibuf_entry_update_clk_en),//Local Condition @83
// .module_en (cp0_ifu_icg_en) @84
// ); @85
assign ibuf_entry_update_clk_en = entry_data_create_clk_en_x;
// &Instance("gated_clk_cell","x_ibuf_entry_spe_clk"); @88
gated_clk_cell x_ibuf_entry_spe_clk (
.clk_in (forever_cpuclk ),
.clk_out (ibuf_entry_spe_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ibuf_entry_spe_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @89
// .clk_out (ibuf_entry_spe_clk),//Out Clock @90
// .external_en (1'b0), @91
// .global_en (cp0_yy_clk_en), @92
// .local_en (ibuf_entry_spe_clk_en),//Local Condition @93
// .module_en (cp0_ifu_icg_en) @94
// ); @95
assign ibuf_entry_spe_clk_en = entry_spe_data_vld ||
entry_acc_err_x ||
entry_pgflt_x ||
entry_high_expt_x ||
entry_bkpta_x ||
entry_bkptb_x ||
entry_no_spec_x;
// &Instance("gated_clk_cell","x_ibuf_entry_pc_clk"); @104
gated_clk_cell x_ibuf_entry_pc_clk (
.clk_in (forever_cpuclk ),
.clk_out (ibuf_entry_pc_clk ),
.external_en (1'b0 ),
.global_en (cp0_yy_clk_en ),
.local_en (ibuf_entry_pc_clk_en),
.module_en (cp0_ifu_icg_en ),
.pad_yy_icg_scan_en (pad_yy_icg_scan_en )
);
// &Connect( .clk_in (forever_cpuclk), @105
// .clk_out (ibuf_entry_pc_clk),//Out Clock @106
// .external_en (1'b0), @107
// .global_en (cp0_yy_clk_en), @108
// .local_en (ibuf_entry_pc_clk_en),//Local Condition @109
// .module_en (cp0_ifu_icg_en) @110
// ); @111
assign ibuf_entry_pc_clk_en = entry_pc_create_clk_en_x;
//--------------------Register Update-----------------------
//_x _v for instance entry convinent
//entry 32 start is control signal, should use entry create to
always @(posedge ibuf_entry_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_32_start_x <= 1'b0;
else if(entry_create_x)
entry_32_start_x <= entry_create_32_start_x;
else
entry_32_start_x <= entry_32_start_x;
end
always @(posedge ibuf_entry_update_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
entry_inst_data_v[15:0] <= 16'b0;
// entry_32_start_x <= 1'b0;
entry_split1_x <= 1'b0;
entry_split0_x <= 1'b0;
entry_fence_x <= 1'b0;
entry_vlmul_v[1:0] <= 2'b0;
entry_vsew_v[2:0] <= 3'b0;
entry_vl_v[7:0] <= 8'b0;
end
else if(entry_data_create_x)
begin
entry_inst_data_v[15:0] <= entry_create_inst_data_v[15:0];
// entry_32_start_x <= entry_create_32_start_x;
entry_split1_x <= entry_create_split1_x;
entry_split0_x <= entry_create_split0_x;
entry_fence_x <= entry_create_fence_x;
entry_vlmul_v[1:0] <= entry_create_vlmul_v[1:0];
entry_vsew_v[2:0] <= entry_create_vsew_v[2:0];
entry_vl_v[7:0] <= entry_create_vl_v[7:0];
end
else
begin
entry_inst_data_v[15:0] <= entry_inst_data_v[15:0];
// entry_32_start_x <= entry_32_start_x;
entry_split1_x <= entry_split1_x;
entry_split0_x <= entry_split0_x;
entry_fence_x <= entry_fence_x;
entry_vlmul_v[1:0] <= entry_vlmul_v[1:0];
entry_vsew_v[2:0] <= entry_vsew_v[2:0];
entry_vl_v[7:0] <= entry_vl_v[7:0];
end
end
always @(posedge ibuf_entry_spe_clk or negedge cpurst_b)
begin
if(!cpurst_b)
begin
entry_acc_err_x <= 1'b0;
entry_pgflt_x <= 1'b0;
entry_high_expt_x <= 1'b0;
entry_bkpta_x <= 1'b0;
entry_bkptb_x <= 1'b0;
entry_no_spec_x <= 1'b0;
entry_vl_pred_x <= 1'b0;
end
else if(entry_data_create_x)
begin
entry_acc_err_x <= entry_create_acc_err_x;
entry_pgflt_x <= entry_create_pgflt_x;
entry_high_expt_x <= entry_create_high_expt_x;
entry_bkpta_x <= entry_create_bkpta_x;
entry_bkptb_x <= entry_create_bkptb_x;
entry_no_spec_x <= entry_create_no_spec_x;
entry_vl_pred_x <= entry_create_vl_pred_x;
end
else
begin
entry_acc_err_x <= entry_acc_err_x;
entry_pgflt_x <= entry_pgflt_x;
entry_high_expt_x <= entry_high_expt_x;
entry_bkpta_x <= entry_bkpta_x;
entry_bkptb_x <= entry_bkptb_x;
entry_no_spec_x <= entry_no_spec_x;
entry_vl_pred_x <= entry_vl_pred_x;
end
end
// &Force("output","entry_ecc_err_x"); @208
always @(posedge ibuf_entry_pc_clk or negedge cpurst_b)
begin
if(!cpurst_b)
entry_pc_v[14:0] <= 15'b0;
else if(entry_pc_create_x)
entry_pc_v[14:0] <= entry_create_pc_v[14:0];
else
entry_pc_v[14:0] <= entry_pc_v[14:0];
end
// &Force("output","entry_inst_data_v"); @222
// &Force("output","entry_pc_v"); @223
// &Force("output","entry_32_start_x"); @224
// &Force("output","entry_acc_err_x"); @225
// &Force("output","entry_pgflt_x"); @226
// &Force("output","entry_high_expt_x"); @227
// &Force("output","entry_split1_x"); @228
// &Force("output","entry_split0_x"); @229
// &Force("output","entry_fence_x"); @230
// &Force("output","entry_vlmul_v"); @231
// &Force("output","entry_vl_v"); @232
// &Force("output","entry_vsew_v"); @233
// &Force("output","entry_bkpta_x"); @234
// &Force("output","entry_bkptb_x"); @235
// &Force("output","entry_no_spec_x"); @236
// &Force("output","entry_vl_pred_x"); @237
// &Force("output","entry_vld_x"); @238
// &ModuleEnd; @240
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.