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module ram_128_11 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [10:0] data;
input [6:0] rdaddress;
input rden;
input [6:0] wraddress;
input wren;
output [10:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] sub_wire0;
wire [10:0] q = sub_wire0[10:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({11{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 11,
altsyncram_component.width_b = 11,
altsyncram_component.width_byteena_a = 1;
endmodule |
module fifo_16_5 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [4:0] data;
input rdreq;
input wrreq;
output empty;
output [4:0] q;
wire sub_wire0;
wire [4:0] sub_wire1;
wire empty = sub_wire0;
wire [4:0] q = sub_wire1[4:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 5,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_64_12 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [11:0] data;
input rdreq;
input wrreq;
output empty;
output [11:0] q;
wire sub_wire0;
wire [11:0] sub_wire1;
wire empty = sub_wire0;
wire [11:0] q = sub_wire1[11:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire sub_wire1;
wire [0:0] q = sub_wire0[0:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 64,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 1,
dcfifo_component.lpm_widthu = 6,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module ram_64_256 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [63:0] data;
input [7:0] rdaddress;
input rden;
input [7:0] wraddress;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 1;
endmodule |
module fifo_32_24 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [23:0] data;
input rdreq;
input wrreq;
output empty;
output [23:0] q;
wire sub_wire0;
wire [23:0] sub_wire1;
wire empty = sub_wire0;
wire [23:0] q = sub_wire1[23:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 24,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_64_1 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output empty;
output [0:0] q;
wire sub_wire0;
wire [0:0] sub_wire1;
wire empty = sub_wire0;
wire [0:0] q = sub_wire1[0:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 1,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_32_5 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [4:0] data;
input rdreq;
input wrreq;
output empty;
output [4:0] q;
wire sub_wire0;
wire [4:0] sub_wire1;
wire empty = sub_wire0;
wire [4:0] q = sub_wire1[4:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 5,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_512_7 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [6:0] data;
input rdreq;
input wrreq;
output empty;
output [6:0] q;
output [8:0] usedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire [8:0] sub_wire2;
wire empty = sub_wire0;
wire [6:0] q = sub_wire1[6:0];
wire [8:0] usedw = sub_wire2[8:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 7,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [7:0] sub_wire1;
wire [133:0] q = sub_wire0[133:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule |
module card1_pll (
inclk0,
c0,
c1,
c2,
c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
wire [9:0] sub_wire0;
wire sub_wire5;
wire [0:0] sub_wire8 = 1'h0;
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire locked = sub_wire5;
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
altpll altpll_component (
.inclk (sub_wire7),
.clk (sub_wire0),
.locked (sub_wire5),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 25,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 8,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 5,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 1,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=card1_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule |
module IPE_PPS(
input clk,
input reset,
input [5:0] in_fpgaac_channel_num,
input in_fpgaac_cpuid_cs,//switch cpuid allocate mode 0:round robin 1:port bind
input [31:0] cpuid_valid,//lxj20131224
input in_inputctrl_pkt_wr,
input [133:0] in_inputctrl_pkt,
input in_inputctrl_valid_wr,
input in_inputctrl_valid,
output out_inputctrl_pkt_almostfull,
output out_rdma_pkt_wr,
output [133:0] out_rdma_pkt,
output out_rdma_valid_wr,
output out_rdma_valid,
input in_rdma_pkt_almostfull,
input in_tdma_pkt_wr,
input [133:0] in_tdma_pkt,
input in_tdma_valid_wr,
input in_tdma_valid,
output out_tdma_pkt_almostfull,
output out_outputctrl_pkt_wr,
output [133:0] out_outputctrl_pkt,
output out_outputctrl_valid_wr,
output out_outputctrl_valid,
input in_outputctrl_pkt_almostfull
);
EGRESS EGRESS(
.clk(clk),
.reset(reset),
.in_tdma_pkt_wr(in_tdma_pkt_wr),
.in_tdma_pkt(in_tdma_pkt),
.in_tdma_valid_wr(in_tdma_valid_wr),
.in_tdma_valid(in_tdma_valid),
.out_tdma_pkt_almostfull(out_tdma_pkt_almostfull),
.out_outputctrl_pkt_wr(out_outputctrl_pkt_wr),
.out_outputctrl_pkt(out_outputctrl_pkt),
.out_outputctrl_valid_wr(out_outputctrl_valid_wr),
.out_outputctrl_valid(out_outputctrl_valid),
.in_outputctrl_pkt_almostfull(in_outputctrl_pkt_almostfull)
);
wire in_ingress_key_wr;
wire [133:0] in_ingress_key;
wire out_ingress_key_almostfull;
wire in_ingress_valid_wr;
wire in_ingress_valid;
wire out_offset_key_wr;
wire [133:0] out_offset_key;
wire out_offset_valid;
wire out_offset_valid_wr;
wire in_offset_key_almostfull;
CLASSIFY CLASSIFY(
.clk(clk),
.reset(reset),
.in_ingress_key_wr(in_ingress_key_wr),
.in_ingress_key(in_ingress_key),
.out_ingress_key_almostfull(out_ingress_key_almostfull),
.in_ingress_valid_wr(in_ingress_valid_wr),
.in_ingress_valid(in_ingress_valid),
.out_offset_key_wr(out_offset_key_wr),
.out_offset_key(out_offset_key),
.out_offset_valid(out_offset_valid),
.out_offset_valid_wr(out_offset_valid_wr),
.in_offset_key_almostfull(in_offset_key_almostfull)
);
wire out_dispather_pkt_wr;
wire [133:0] out_dispather_pkt;
wire out_dispather_valid_wr;
wire out_dispather_valid;
wire in_dispather_pkt_almostfull;
INGRESS INGRESS(
.clk(clk),
.reset(reset),
.in_inputctrl_pkt_wr(in_inputctrl_pkt_wr),
.in_inputctrl_pkt(in_inputctrl_pkt),
.in_inputctrl_valid_wr(in_inputctrl_valid_wr),
.in_inputctrl_valid(in_inputctrl_valid),
.out_inputctrl_pkt_almostfull(out_inputctrl_pkt_almostfull),
.out_class_key_wr(in_ingress_key_wr),
.out_class_key(in_ingress_key),
.in_class_key_almostfull(out_ingress_key_almostfull),
.out_class_valid(in_ingress_valid),
.out_class_valid_wr(in_ingress_valid_wr),
.in_class_key_wr(out_offset_key_wr),
.in_class_key(out_offset_key),
.in_class_valid_wr(out_offset_valid_wr),
.in_class_valid(out_offset_valid),
.out_class_key_almostfull(in_offset_key_almostfull),
.out_dispather_pkt_wr(out_dispather_pkt_wr),
.out_dispather_pkt(out_dispather_pkt),
.out_dispather_valid_wr(out_dispather_valid_wr),
.out_dispather_valid(out_dispather_valid),
.in_dispather_pkt_almostfull(in_dispather_pkt_almostfull)
);
wire in_ppc_pkt_wr;
wire [133:0] in_ppc_pkt;
wire in_ppc_valid_wr;
wire in_ppc_valid;
wire out_ppc_pkt_almostfull;
/*wire out_ppc_pkt_wr;
wire [133:0] out_ppc_pkt;
wire out_ppc_valid_wr;
wire out_ppc_valid;
wire in_ppc_pkt_almostfull;*/
DISPATHER DISPATHER(
.clk(clk),
.reset(reset),
.in_fpgaac_channel_num(in_fpgaac_channel_num),
.in_fpgaac_cpuid_cs(in_fpgaac_cpuid_cs),
.cpuid_valid(cpuid_valid),
.in_ingress_pkt_wr(out_dispather_pkt_wr),
.in_ingress_pkt(out_dispather_pkt),
.in_ingress_valid_wr(out_dispather_valid_wr),
.in_ingress_valid(out_dispather_valid),
.out_ingress_pkt_almostfull(in_dispather_pkt_almostfull),
.out_rdma_pkt_wr(out_rdma_pkt_wr),
.out_rdma_pkt(out_rdma_pkt),
.out_rdma_valid_wr(out_rdma_valid_wr),
.out_rdma_valid(out_rdma_valid),
.in_rdma_pkt_almostfull(in_rdma_pkt_almostfull),
.in_ppc_pkt_wr(in_ppc_pkt_wr),
.in_ppc_pkt(in_ppc_pkt),
.in_ppc_valid_wr(in_ppc_valid_wr),
.in_ppc_valid(in_ppc_valid),
.out_ppc_pkt_almostfull(out_ppc_pkt_almostfull),
.out_ppc_pkt_wr(in_ppc_pkt_wr),
.out_ppc_pkt(in_ppc_pkt),
.out_ppc_valid_wr(in_ppc_valid_wr),
.out_ppc_valid(in_ppc_valid),
.in_ppc_pkt_almostfull(out_ppc_pkt_almostfull)
);
endmodule |
module CLASSIFY(
input clk,
input reset,
input in_ingress_key_wr,// the key write request of inputctrl to classfy
input [133:0] in_ingress_key,// the key of inputctrl to classfy
input in_ingress_valid_wr,//the valid flag write request of inputctrl to classfy
input in_ingress_valid,//the valid flag of inputctrl to classfy
output out_ingress_key_almostfull,//the valid fifo almostfull signal of classfy to inputctrl
output reg out_offset_key_wr,// the key write request of classfy to inputctrl
output reg [133:0] out_offset_key,// the key of classfy to inputctrl
output reg out_offset_valid,// the valid flag of classfy to inputctrl
output reg out_offset_valid_wr,//the valid flag write request of classfy to inputctrl
input in_offset_key_almostfull//the valid fifo almostfull signal of inputctrl to classfy
);
reg [2:0] state;
wire in_ingress_valid_q; //the output valid flag from the valid flag fifo
wire in_ingress_valid_empty;//the empty signal of the valid flag fifo
reg out_ingress_valid_rd; //the read request of the valid flag fifo
wire [7:0] out_ingress_key_usedw;//the usedw signal of the key fifo
assign out_ingress_key_almostfull = out_ingress_key_usedw[7];
reg out_ingress_key_rd;//the read request of the key fifo
wire [133:0]in_ingress_key_q;//the output key from the valid flag fifo
reg is_unknown;
reg [7:0]tos;
reg [15:0]l3_protocol;
reg [7:0]l4_protocol;
reg [31:0]sip;
reg [31:0]dip;
reg [15:0]sport;
reg [15:0]dport;
reg [7:0]tcp_flag;
reg [7:0]layer_type;
reg [7:0]code;
reg tcp_icmp;
parameter idle=3'd0,
l2=3'd1,
l3=3'd2,
l4=3'd3,
prepad1=3'd4,
prepad2=3'd5,
prepad3=3'd6,
prepad4=3'd7;
always @(posedge clk or negedge reset) begin
if(!reset)begin
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
state<=idle;
end
else begin
case(state)
idle:begin// according to the in_offset_key_almostfull and in_ingress_valid_empty signals to judge whether or not the classfy module can receive packet from inputctrl
out_offset_key_wr<=1'b0;
out_offset_key<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
is_unknown<=1'b0;
tos<=8'b0;
l3_protocol<=16'b0;
l4_protocol<=8'b0;
sip<=32'b0;
dip<=32'b0;
sport<=16'b0;
dport<=16'b0;
tcp_flag<=8'b0;
layer_type<=8'b0;
code<=8'b0;
tcp_icmp<=1'b0;
if(in_offset_key_almostfull==1'b0 && in_ingress_valid_empty==1'b0 )begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
state<=l2;
end
else begin
state<=idle;
end
end
l2: begin//according to the layer_type field of the ethrnet hearder to parsing packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
state<=l3;
if(in_ingress_key_q[31:16]==16'h0800 &&in_ingress_key_q[11:8] ==4'd5)//judge the packet whether or not a IP packet and its header length equal the 20bytes
begin
l3_protocol<=in_ingress_key_q[31:16];
tos<=in_ingress_key_q[7:0];
end
else
begin
is_unknown<=1'b1;
end
end
l3:begin//according to the protocol field of the IP hearder to judge the packet whether or not a TCP packet or ICMP packet
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=l4;
end
else if(in_ingress_key_q[71:64]==8'd6|| in_ingress_key_q[71:64]==8'd1)//judge the packet whether or not a TCP packet or ICMP packet
begin
l4_protocol<=in_ingress_key_q[71:64];
sip<=in_ingress_key_q[47:16];
dip[31:16]<=in_ingress_key_q[15:0];
end
else
begin
is_unknown<=1'b1;
end
state<=l4;
end
l4:begin
out_ingress_key_rd<=1'b1;
out_ingress_valid_rd<=1'b0;
if(is_unknown==1'b1)
begin
state<=prepad1;
end
else if(l4_protocol==8'd6)
begin
dip[15:0]<=in_ingress_key_q[127:112];
sport<=in_ingress_key_q[111:96];
dport<=in_ingress_key_q[95:80];
tcp_flag<=in_ingress_key_q[7:0];
state<=prepad1;
end
else if(l4_protocol==8'd1)
begin
dip[15:0]<=in_ingress_key_q[127:112];
layer_type<=in_ingress_key_q[111:104];
code<=in_ingress_key_q[103:96];
tcp_flag<=8'b0;
end
else
begin
is_unknown<=1'b1;
end
state<=prepad1;
end
prepad1:begin//to structure the first pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b010000,3'b001,125'b0};
state<=prepad2;
end
prepad2:begin//to structure the second pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b110000,48'b0,l3_protocol,tos,l4_protocol,sip,dip[31:16]};
state<=prepad3;
end
prepad3:begin//to structure the third pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
if(tcp_icmp==1'b0)
begin
out_offset_key<={6'b110000,dip[15:0],sport,dport,tcp_flag,72'b0};
end
else
begin
out_offset_key<={6'b110000,dip[15:0],layer_type,code,96'b0};
end
state<=prepad4;
end
prepad4:begin//to structure the fourth pat prepad
out_ingress_key_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_offset_key_wr<=1'b1;
out_offset_key<={6'b100000,128'b0};
out_offset_valid<=1'b1;
out_offset_valid_wr<=1'b1;
state<=idle;
end
endcase
end
end
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_key_input (
.aclr(!reset),
.data(in_ingress_key),
.clock(clk),
.rdreq(out_ingress_key_rd),
.wrreq(in_ingress_key_wr),
.q(in_ingress_key_q),
.usedw(out_ingress_key_usedw)
);
endmodule |
module UE1_PORT(
clk,
ammc_clk,
reset,
//rx_clk,
sgmii_clk,
out_pkt_wrreq,
out_pkt,
out_valid_wrreq,
out_valid,
out_pkt_almostfull,
out2_pkt_wrreq,
out2_pkt,
out2_pkt_almost_full,
out2_valid_wrreq,
out2_valid,
pkt_receive_add,
pkt_discard_add,
pkt_send_add,
//gmii
tx_clk,
rx_clk,
gm_tx_d,
gm_tx_en,
gm_tx_err,
gm_rx_d,
gm_rx_dv,
gm_rx_err,
address,
write,
read,
writedata,
readdata,
waitrequest);
input clk;
input ammc_clk;
input sgmii_clk;
input reset;
input out2_pkt_wrreq;//output to port2;
input [133:0] out2_pkt;
output out2_pkt_almost_full;
input out2_valid_wrreq;
input out2_valid;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
output pkt_receive_add;
output pkt_discard_add;
output pkt_send_add;
//gmii
input tx_clk;
input rx_clk;
input [7:0] gm_rx_d;
input gm_rx_dv;
input gm_rx_err;
output [7:0] gm_tx_d;
output gm_tx_en;
output gm_tx_err;
//
input [7:0] address;
input write;
input read;
input [31:0] writedata;
output [31:0]readdata;
output waitrequest;
SGMII_TX1 SGMII_TX1(
.clk (clk),
.reset (reset),
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
.pkt_send_add (pkt_send_add),
.data_in_wrreq (out2_pkt_wrreq),
.data_in (out2_pkt),
.data_in_almostfull (out2_pkt_almost_full),
.data_in_valid_wrreq (out2_valid_wrreq),
.data_in_valid (out2_valid) );
SGMII_RX1 SGMII_RX1(
.reset (reset),
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
.pkt_receive_add (pkt_receive_add),
.pkt_discard_add (pkt_discard_add),
.out_pkt_wrreq (out_pkt_wrreq),
.out_pkt (out_pkt),
.out_pkt_almostfull (out_pkt_almostfull),
.out_valid_wrreq (out_valid_wrreq),
.out_valid (out_valid)
);
wire ff_tx_clk;
wire [7:0] ff_tx_data;
wire ff_tx_sop;
wire ff_tx_eop;
wire ff_tx_err;
wire ff_tx_wren;
wire ff_tx_crc_fwd;
wire tx_ff_uflow;
wire ff_tx_rdy;
wire ff_tx_septy;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire reset;
wire ff_rx_clk;
wire ff_rx_rdy;
wire [7:0] ff_rx_data;
wire ff_rx_sop;
wire ff_rx_eop;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_a_full;
wire ff_rx_a_empty;
mac_core mac_core(
//MAC Transmit Interface Signals
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
//MAC Receive Interface Signals
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
// //MAC Contro
// .clk (ammc_clk),
// .address (address),
// .write (write),
// .read (read),
// .writedata (writedata),
// .readdata (readdata),
// .waitrequest (waitrequest),
//MAC Contro
.clk (ammc_clk),
.reg_addr (address),
.reg_wr (write),
.reg_rd (read),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_busy (waitrequest),
//reset sgmii
.reset (~reset),
.tx_clk (tx_clk),
.rx_clk (rx_clk),
//GMII
.gm_rx_d (gm_rx_d),
.gm_rx_dv (gm_rx_dv),
.gm_rx_err (gm_rx_err),
.gm_tx_d (gm_tx_d),
.gm_tx_en (gm_tx_en),
.gm_tx_err (gm_tx_err),
//MII
.m_rx_d (4'b0),
.m_rx_en (1'b0),
.m_rx_err (1'b0),
.m_tx_d (),
.m_tx_en (),
.m_tx_err (),
.set_10 (1'b0),
.set_1000 (1'b1),
.ena_10 (),
.eth_mode ());
endmodule |
module SGMII_TX(
clk,
reset,
ff_tx_clk,
ff_tx_data,//
ff_tx_sop,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_wren,
ff_tx_crc_fwd,//CRC ADD
tx_ff_uflow,
ff_tx_rdy,//core ready
ff_tx_septy,
ff_tx_a_full,
ff_tx_a_empty,
pkt_send_add,
data_in_wrreq,
data_in,
data_in_almostfull,
data_in_valid_wrreq,
data_in_valid );
input clk;
input reset;
input ff_tx_clk;
output [31:0] ff_tx_data;
output [1:0] ff_tx_mod;
output ff_tx_sop;
output ff_tx_eop;
output ff_tx_err;
output ff_tx_wren;
output ff_tx_crc_fwd;
input tx_ff_uflow;
input ff_tx_rdy;
input ff_tx_septy;
input ff_tx_a_full;
input ff_tx_a_empty;
output pkt_send_add;
input data_in_wrreq;
input [133:0] data_in;
output data_in_almostfull;
input data_in_valid_wrreq;
input data_in_valid;
reg [31:0] ff_tx_data;
reg [1:0] ff_tx_mod;
reg ff_tx_sop;
reg ff_tx_eop;
reg ff_tx_err;
reg ff_tx_wren;
reg ff_tx_crc_fwd;
reg pkt_send_add;
reg [133:0] data_in_q_r;
reg [2:0] current_state;
parameter idle_s = 3'b000,
transmit_byte0_s = 3'b001,
transmit_byte1_s = 3'b010,
transmit_byte2_s = 3'b011,
transmit_byte3_s = 3'b100,
discard_s = 3'b101;
always@(posedge ff_tx_clk or negedge reset)
if(!reset) begin
ff_tx_data <= 32'b0;
ff_tx_mod <= 2'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b0;
ff_tx_crc_fwd <= 1'b1;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
data_in_q_r <= 134'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ff_tx_crc_fwd <= 1'b1;
ff_tx_wren <= 1'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_mod <= 2'b0;
if(ff_tx_rdy == 1'b1) begin
if(!data_in_valid_empty) begin//0:has pkt 1:no pkt
data_in_rdreq <= 1'b1;
data_in_valid_rdreq <= 1'b1;
if(data_in_valid_q == 1'b1) begin//pkt valid
pkt_send_add <= 1'b1;
data_in_q_r <= data_in_q;
ff_tx_sop <= 1'b1;
ff_tx_data <= data_in_q[127:96];
ff_tx_wren <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin//pkt error
pkt_send_add <= 1'b0;
current_state <= discard_s;
end
end
else begin
current_state <= idle_s;
end
end
else begin
current_state <= idle_s;
end
end
transmit_byte0_s: begin
data_in_rdreq <= 1'b0;
if(ff_tx_rdy == 1'b0) begin//MAC core don't ready need wait
current_state <= transmit_byte0_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[127:96];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin//pkt tail
if(data_in_q_r[131:130] == 2'b11)begin
ff_tx_eop <= 1'b1;
ff_tx_mod <= data_in_q_r[129:128];
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else
current_state <= transmit_byte1_s;
end
else begin
current_state <= transmit_byte1_s;
end
end
end
transmit_byte1_s: begin
ff_tx_sop <= 1'b0;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte1_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[95:64];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b10)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte2_s;
end
else begin
current_state <= transmit_byte2_s;
end
end
end
transmit_byte2_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte2_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[63:32];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:130] == 2'b01)begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else
current_state <= transmit_byte3_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
end
transmit_byte3_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte3_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[31:0];
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
ff_tx_mod <= data_in_q_r[129:128];
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
end
end
discard_s: begin
data_in_valid_rdreq <= 1'b0;
if(data_in_q[133:132]==2'b10) begin
data_in_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
current_state <= discard_s;
end
end
endcase
end
reg data_in_rdreq;
wire [7:0] data_in_usedw;
assign data_in_almostfull = data_in_usedw[7];
wire [133:0] data_in_q;
asyn_256_134 asyn_256_134(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_wrreq),
.data(data_in),
.rdclk(ff_tx_clk),
.rdreq(data_in_rdreq),
.q(data_in_q),
.wrusedw(data_in_usedw)
);
reg data_in_valid_rdreq;
wire data_in_valid_q;
wire data_in_valid_empty;
asyn_64_1 asyn_64_1(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_valid_wrreq),
.data(data_in_valid),
.rdclk(ff_tx_clk),
.rdreq(data_in_valid_rdreq),
.q(data_in_valid_q),
.rdempty(data_in_valid_empty)
);
endmodule |
module SGMII_RX1
(reset,
ff_rx_clk,
ff_rx_rdy,
ff_rx_data,
ff_rx_sop,
ff_rx_eop,
rx_err,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_dval,
ff_rx_a_full,
ff_rx_a_empty,
pkt_receive_add,
pkt_discard_add,
out_pkt_wrreq,
out_pkt,
out_pkt_almostfull,
out_valid_wrreq,
out_valid
);
input reset;
input ff_rx_clk;
output ff_rx_rdy;
input [7:0] ff_rx_data;
input ff_rx_sop;
input ff_rx_eop;
input [5:0] rx_err;
input [17:0] rx_err_stat;
input [3:0] rx_frm_type;
input ff_rx_dsav;
input ff_rx_dval;
input ff_rx_a_full;
input ff_rx_a_empty;
output pkt_receive_add;
output pkt_discard_add;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
reg ff_rx_rdy;
reg pkt_receive_add;
reg pkt_discard_add;
reg out_pkt_wrreq;
reg [133:0] out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [4:0]current_state;
parameter //idle_s = 5'b00000,
transmit_byte0_s = 5'b00001,
transmit_byte1_s = 5'b00010,
transmit_byte2_s = 5'b00011,
transmit_byte3_s = 5'b00100,
transmit_byte4_s = 5'b00101,
transmit_byte5_s = 5'b00110,
transmit_byte6_s = 5'b00111,
transmit_byte7_s = 5'b01000,
transmit_byte8_s = 5'b01001,
transmit_byte9_s = 5'b01010,
transmit_byte10_s = 5'b01011,
transmit_byte11_s = 5'b01100,
transmit_byte12_s = 5'b01101,
transmit_byte13_s = 5'b01110,
transmit_byte14_s = 5'b01111,
transmit_byte15_s = 5'b10000,
discard_s = 5'b10001;
always@(posedge ff_rx_clk or negedge reset)
if(!reset) begin
ff_rx_rdy <= 1'b0;
out_pkt_wrreq <= 1'b0;
out_pkt <= 134'b0;
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
pkt_receive_add <= 1'b0;
pkt_discard_add <= 1'b0;
current_state <= transmit_byte0_s;
end
else begin
ff_rx_rdy <= 1'b1;
case(current_state)
transmit_byte0_s: begin
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[127:120] <= ff_rx_data;
if(ff_rx_sop == 1'b1) begin //pkt head
if(!out_pkt_almostfull) begin//FIFO can receive a 1518B pkt
out_pkt[133:132] <= 2'b01;
pkt_receive_add <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin
pkt_discard_add <= 1'b1;
current_state <= discard_s;
end
end
else if(ff_rx_eop == 1'b1) begin//pkt tail
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte0_s;
end
end
transmit_byte1_s: begin
out_pkt_wrreq <= 1'b0;
pkt_receive_add <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[119:112] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin//pkt head
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
transmit_byte2_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[111:104] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
transmit_byte3_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[103:96] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte4_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
transmit_byte4_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[95:88] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte5_s;
end
end
else begin
current_state <= transmit_byte4_s;
end
end
transmit_byte5_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[87:80] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte6_s;
end
end
else begin
current_state <= transmit_byte5_s;
end
end
transmit_byte6_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[79:72] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte7_s;
end
end
else begin
current_state <= transmit_byte6_s;
end
end
transmit_byte7_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[71:64] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte8_s;
end
end
else begin
current_state <= transmit_byte7_s;
end
end
transmit_byte8_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[63:56] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte9_s;
end
end
else begin
current_state <= transmit_byte8_s;
end
end
transmit_byte9_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[55:48] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte10_s;
end
end
else begin
current_state <= transmit_byte9_s;
end
end
transmit_byte10_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[47:40] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte11_s;
end
end
else begin
current_state <= transmit_byte10_s;
end
end
transmit_byte11_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[39:32] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte12_s;
end
end
else begin
current_state <= transmit_byte11_s;
end
end
transmit_byte12_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[31:24] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte13_s;
end
end
else begin
current_state <= transmit_byte12_s;
end
end
transmit_byte13_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[23:16] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte14_s;
end
end
else begin
current_state <= transmit_byte13_s;
end
end
transmit_byte14_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[15:8] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte15_s;
end
end
else begin
current_state <= transmit_byte14_s;
end
end
transmit_byte15_s: begin
if(ff_rx_dval == 1'b1) begin
out_pkt_wrreq <= 1'b1;
out_pkt[7:0] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte0_s;
end
end
else begin
current_state <= transmit_byte15_s;
end
end
discard_s:begin
out_pkt_wrreq <= 1'b0;
pkt_discard_add <= 1'b0;
if((ff_rx_dval == 1'b1)&&(ff_rx_eop == 1'b1))begin
current_state <= transmit_byte0_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
endmodule |
module SGMII_DMUX(
clk,
reset,
//-------To path0-------------------
out_xaui0_pkt_wr,
out_xaui0_pkt,
in_xaui0_pkt_almostfull,
out_xaui0_pkt_valid_wr,
out_xaui0_pkt_valid,
//-------To path1-------------------
out_xaui1_pkt_wr,
out_xaui1_pkt,
in_xaui1_pkt_almostfull,
out_xaui1_pkt_valid_wr,
out_xaui1_pkt_valid,
//-------To path2-------------------
out_xaui2_pkt_wr,
out_xaui2_pkt,
in_xaui2_pkt_almostfull,
out_xaui2_pkt_valid_wr,
out_xaui2_pkt_valid,
//-------To path3-------------------
out_xaui3_pkt_wr,
out_xaui3_pkt,
in_xaui3_pkt_almostfull,
out_xaui3_pkt_valid_wr,
out_xaui3_pkt_valid,
//-------To path4-------------------
out_xaui4_pkt_wr,
out_xaui4_pkt,
in_xaui4_pkt_almostfull,
out_xaui4_pkt_valid_wr,
out_xaui4_pkt_valid,
//-------From EGRESS -------------------
in_egress_pkt_wr,
in_egress_pkt,
out_egress_pkt_almostfull,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
dmux_receive_pkt_add,
dmux_discard_error_pkt_add,
dmux_send_port0_pkt_add,
dmux_send_port1_pkt_add,
dmux_send_port2_pkt_add,
dmux_send_port3_pkt_add,
dmux_send_port4_pkt_add);
input clk;
input reset;
//path0
output out_xaui0_pkt_wr;
output [133:0] out_xaui0_pkt;
input in_xaui0_pkt_almostfull;
output out_xaui0_pkt_valid_wr;
output out_xaui0_pkt_valid;
//path1
output out_xaui1_pkt_wr;
output [133:0] out_xaui1_pkt;
input in_xaui1_pkt_almostfull;
output out_xaui1_pkt_valid_wr;
output out_xaui1_pkt_valid;
//path2
output out_xaui2_pkt_wr;
output [133:0] out_xaui2_pkt;
input in_xaui2_pkt_almostfull;
output out_xaui2_pkt_valid_wr;
output out_xaui2_pkt_valid;
//path3
output out_xaui3_pkt_wr;
output [133:0] out_xaui3_pkt;
input in_xaui3_pkt_almostfull;
output out_xaui3_pkt_valid_wr;
output out_xaui3_pkt_valid;
//path4
output out_xaui4_pkt_wr;
output [133:0] out_xaui4_pkt;
input in_xaui4_pkt_almostfull;
output out_xaui4_pkt_valid_wr;
output out_xaui4_pkt_valid;
// egress
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
output out_egress_pkt_almostfull;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
reg out_xaui0_pkt_wr;
reg [133:0] out_xaui0_pkt;
reg out_xaui0_pkt_valid_wr;
reg out_xaui0_pkt_valid;
reg out_xaui1_pkt_wr;
reg [133:0] out_xaui1_pkt;
reg out_xaui1_pkt_valid_wr;
reg out_xaui1_pkt_valid;
reg out_xaui2_pkt_wr;
reg [133:0] out_xaui2_pkt;
reg out_xaui2_pkt_valid_wr;
reg out_xaui2_pkt_valid;
reg out_xaui3_pkt_wr;
reg [133:0] out_xaui3_pkt;
reg out_xaui3_pkt_valid_wr;
reg out_xaui3_pkt_valid;
reg out_xaui4_pkt_wr;
reg [133:0] out_xaui4_pkt;
reg out_xaui4_pkt_valid_wr;
reg out_xaui4_pkt_valid;
output dmux_receive_pkt_add;
output dmux_discard_error_pkt_add;
output dmux_send_port0_pkt_add;
output dmux_send_port1_pkt_add;
output dmux_send_port2_pkt_add;
output dmux_send_port3_pkt_add;
output dmux_send_port4_pkt_add;
reg dmux_receive_pkt_add;
reg dmux_discard_error_pkt_add;
reg dmux_send_port0_pkt_add;
reg dmux_send_port1_pkt_add;
reg dmux_send_port2_pkt_add;
reg dmux_send_port3_pkt_add;
reg dmux_send_port4_pkt_add;
reg [2:0] xaui_channel;//outport extract from metadata 000:port0 001:port1 010:port2 011:port3 100:port4
reg [133:0] in_egress_pkt_q_r;//store the metadata pkt for reverse it easily
reg flag;//turn current pat data to head flag of pkt 0:current pat data is pkt body 1:current pat data is pkt head
reg [2:0] current_state;//transmit processed pkt to 4 paths by the outport in the metadata of pkt
parameter idle_s = 3'b000,
discard_s = 3'b001,
transmit_s = 3'b010,
wait_s = 3'b011,
pkt_cut_s = 3'b100;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_xaui0_pkt_wr <= 1'b0;
out_xaui0_pkt <= 134'b0;
out_xaui0_pkt_valid_wr <= 1'b0;
out_xaui0_pkt_valid <= 1'b0;
out_xaui1_pkt_wr <= 1'b0;
out_xaui1_pkt <= 134'b0;
out_xaui1_pkt_valid_wr <= 1'b0;
out_xaui1_pkt_valid <= 1'b0;
out_xaui2_pkt_wr <= 1'b0;
out_xaui2_pkt <= 134'b0;
out_xaui2_pkt_valid_wr <= 1'b0;
out_xaui2_pkt_valid <= 1'b0;
out_xaui3_pkt_wr <= 1'b0;
out_xaui3_pkt <= 134'b0;
out_xaui3_pkt_valid_wr <= 1'b0;
out_xaui3_pkt_valid <= 1'b0;
out_xaui4_pkt_wr <= 1'b0;
out_xaui4_pkt <= 134'b0;
out_xaui4_pkt_valid_wr <= 1'b0;
out_xaui4_pkt_valid <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
in_egress_pkt_rd <= 1'b0;
in_egress_pkt_q_r <= 134'b0;
flag <= 1'b0;
xaui_channel <= 3'b0;
dmux_receive_pkt_add <= 1'b0;
dmux_discard_error_pkt_add <= 1'b0;
dmux_send_port0_pkt_add <= 1'b0;
dmux_send_port1_pkt_add <= 1'b0;
dmux_send_port2_pkt_add <= 1'b0;
dmux_send_port3_pkt_add <= 1'b0;
dmux_send_port4_pkt_add <= 1'b0;
current_state <= idle_s;
end
else
begin
case(current_state)
idle_s:begin//judge and poll pkt from pcietx and iace fifo,and reverse order metadata
out_xaui0_pkt_wr <= 1'b0;
out_xaui0_pkt <= 134'b0;
out_xaui0_pkt_valid_wr <= 1'b0;
out_xaui0_pkt_valid <= 1'b0;
out_xaui1_pkt_wr <= 1'b0;
out_xaui1_pkt <= 134'b0;
out_xaui1_pkt_valid_wr <= 1'b0;
out_xaui1_pkt_valid <= 1'b0;
out_xaui2_pkt_wr <= 1'b0;
out_xaui2_pkt <= 134'b0;
out_xaui2_pkt_valid_wr <= 1'b0;
out_xaui2_pkt_valid <= 1'b0;
out_xaui3_pkt_wr <= 1'b0;
out_xaui3_pkt <= 134'b0;
out_xaui3_pkt_valid_wr <= 1'b0;
out_xaui3_pkt_valid <= 1'b0;
out_xaui4_pkt_wr <= 1'b0;
out_xaui4_pkt <= 134'b0;
out_xaui4_pkt_valid_wr <= 1'b0;
out_xaui4_pkt_valid <= 1'b0;
dmux_discard_error_pkt_add <= 1'b0;
dmux_send_port0_pkt_add <= 1'b0;
dmux_send_port1_pkt_add <= 1'b0;
dmux_send_port2_pkt_add <= 1'b0;
dmux_send_port3_pkt_add <= 1'b0;
dmux_send_port4_pkt_add <= 1'b0;
if(in_egress_pkt_valid_empty == 1'b0) begin//judge and poll pkt from pcietx and iace fifo
if(in_egress_pkt_valid_q == 1'b1) begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
in_egress_pkt_q_r <= in_egress_pkt_q;
current_state <= wait_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
current_state <= discard_s;
end
end
else
current_state <= idle_s;
end
wait_s:begin//wait for head pkt from egress and generate xaui_channel and delete this metadata by outport in meatadata
in_egress_pkt_valid_rd<=1'b0;
in_egress_pkt_rd<=1'b0;
case(in_egress_pkt_q_r[73:64])//outport in metadata
10'h001:begin//port0
if(in_xaui0_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b000;//port0
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
10'h002:begin//port1
if(in_xaui1_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b001;//port1
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
10'h004:begin//port2
if(in_xaui2_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b010;//port2
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
10'h008:begin//port3
if(in_xaui3_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b011;//port3
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
10'h010:begin//port4
if(in_xaui4_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b100;//port4
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
default:begin//port0
if(in_xaui0_pkt_almostfull==1'b1)
begin
current_state<= wait_s;
end
else
begin
xaui_channel<=3'b000;//port0
in_egress_pkt_rd<=1'b1;
current_state<= pkt_cut_s;
end
end
endcase
end
pkt_cut_s:begin//delete the second metadata from egress
out_xaui0_pkt_wr <= 1'b0;
out_xaui1_pkt_wr <= 1'b0;
out_xaui2_pkt_wr <= 1'b0;
out_xaui3_pkt_wr <= 1'b0;
out_xaui4_pkt_wr <= 1'b0;
flag <= 1'b1;
dmux_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
discard_s:begin//discard the error pkt from egress
in_egress_pkt_valid_rd <= 1'b0;
if(in_egress_pkt_q[133:132]==2'b10)
begin
dmux_discard_error_pkt_add <= 1'b1;
in_egress_pkt_rd <= 1'b0;
current_state <= idle_s;
end
else
begin
current_state<= discard_s;
end
end
transmit_s:begin//transmit pkt body from egress
flag <= 1'b0;
dmux_receive_pkt_add <= 1'b0;
case(xaui_channel[2:0])//outport(path)
3'b000:begin
out_xaui0_pkt_wr <=1'b1;
if(flag == 1'b0) begin//turn to body of pkt
out_xaui0_pkt <=in_egress_pkt_q;
end
else begin//turn to head of pkt
out_xaui0_pkt <={2'b01,in_egress_pkt_q[131:0]};
end
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <=1'b0;
out_xaui0_pkt_valid_wr <= 1'b1;
dmux_send_port0_pkt_add <= 1'b1;
out_xaui0_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
3'b001:begin
out_xaui1_pkt_wr <=1'b1;
if(flag == 1'b0) begin
out_xaui1_pkt <=in_egress_pkt_q;
end
else begin
out_xaui1_pkt <={2'b01,in_egress_pkt_q[131:0]};
end
if(in_egress_pkt_q[133:132]==2'b10)
begin
in_egress_pkt_rd <= 1'b0;
out_xaui1_pkt_valid_wr <= 1'b1;
dmux_send_port1_pkt_add <= 1'b1;
out_xaui1_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
3'b010:begin
out_xaui2_pkt_wr <=1'b1;
if(flag == 1'b0) begin
out_xaui2_pkt <=in_egress_pkt_q;
end
else begin
out_xaui2_pkt <={2'b01,in_egress_pkt_q[131:0]};
end
if(in_egress_pkt_q[133:132]==2'b10)
begin
in_egress_pkt_rd <= 1'b0;
out_xaui2_pkt_valid_wr <= 1'b1;
dmux_send_port2_pkt_add <= 1'b1;
out_xaui2_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
3'b011:begin
out_xaui3_pkt_wr <=1'b1;
if(flag == 1'b0) begin
out_xaui3_pkt <=in_egress_pkt_q;
end
else begin
out_xaui3_pkt <={2'b01,in_egress_pkt_q[131:0]};
end
if(in_egress_pkt_q[133:132]==2'b10)
begin
in_egress_pkt_rd <= 1'b0;
out_xaui3_pkt_valid_wr <= 1'b1;
dmux_send_port3_pkt_add <= 1'b1;
out_xaui3_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
3'b100:begin
out_xaui4_pkt_wr <=1'b1;
if(flag == 1'b0) begin
out_xaui4_pkt <=in_egress_pkt_q;
end
else begin
out_xaui4_pkt <={2'b01,in_egress_pkt_q[131:0]};
end
if(in_egress_pkt_q[133:132]==2'b10)
begin
in_egress_pkt_rd <= 1'b0;
out_xaui4_pkt_valid_wr <= 1'b1;
dmux_send_port4_pkt_add <= 1'b1;
out_xaui4_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
endcase
end
endcase
end
wire out_egress_pkt_almostfull;
wire [7:0] in_egress_pkt_usedw;
assign out_egress_pkt_almostfull = in_egress_pkt_usedw[7];
reg in_egress_pkt_rd;
wire [133:0] in_egress_pkt_q;
fifo_256_134 egress_pkt(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt),
.rdreq(in_egress_pkt_rd),
.wrreq(in_egress_pkt_wr),
.q(in_egress_pkt_q),
.usedw(in_egress_pkt_usedw)
);
reg in_egress_pkt_valid_rd;
wire in_egress_pkt_valid_empty;
wire in_egress_pkt_valid_q;
fifo_64_1 egress_pkt_valid(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt_valid),
.rdreq(in_egress_pkt_valid_rd),
.wrreq(in_egress_pkt_valid_wr),
.empty(in_egress_pkt_valid_empty),
.q(in_egress_pkt_valid_q)
);
endmodule |
module SGMII_RX
(reset,
ff_rx_clk,
ff_rx_rdy,
ff_rx_data,
ff_rx_mod,
ff_rx_sop,
ff_rx_eop,
rx_err,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_dval,
ff_rx_a_full,
ff_rx_a_empty,
pkt_receive_add,
pkt_discard_add,
out_pkt_wrreq,
out_pkt,
out_pkt_almostfull,
out_valid_wrreq,
out_valid
);
input reset;
input ff_rx_clk;
output ff_rx_rdy;
input [31:0] ff_rx_data;
input [1:0] ff_rx_mod;
input ff_rx_sop;
input ff_rx_eop;
input [5:0] rx_err;
input [17:0] rx_err_stat;
input [3:0] rx_frm_type;
input ff_rx_dsav;
input ff_rx_dval;
input ff_rx_a_full;
input ff_rx_a_empty;
output pkt_receive_add;
output pkt_discard_add;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
reg ff_rx_rdy;
reg pkt_receive_add;
reg pkt_discard_add;
reg out_pkt_wrreq;
reg [133:0] out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [2:0]current_state;
parameter
transmit_byte0_s = 3'b001,
transmit_byte1_s = 3'b010,
transmit_byte2_s = 3'b011,
transmit_byte3_s = 3'b100,
discard_s = 3'b101;
always@(posedge ff_rx_clk or negedge reset)
if(!reset) begin
ff_rx_rdy <= 1'b0;
out_pkt_wrreq <= 1'b0;
out_pkt <= 134'b0;
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
pkt_receive_add <= 1'b0;
pkt_discard_add <= 1'b0;
current_state <= transmit_byte0_s;
end
else begin
ff_rx_rdy <= 1'b1;
case(current_state)
transmit_byte0_s: begin
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[127:96] <= ff_rx_data;
if(ff_rx_sop == 1'b1) begin //pkt head
if(!out_pkt_almostfull) begin//FIFO can receive a 1518B pkt
out_pkt[133:132] <= 2'b01;
pkt_receive_add <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin
pkt_discard_add <= 1'b1;
current_state <= discard_s;
end
end
else if(ff_rx_eop == 1'b1) begin//pkt tail
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b11,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte0_s;
end
end
transmit_byte1_s: begin
out_pkt_wrreq <= 1'b0;
pkt_receive_add <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[95:64] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin//pkt head
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b10,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
transmit_byte2_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[63:32] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b01,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
transmit_byte3_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[31:0] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b00,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
discard_s:begin
out_pkt_wrreq <= 1'b0;
pkt_discard_add <= 1'b0;
if((ff_rx_dval == 1'b1)&&(ff_rx_eop == 1'b1))begin
current_state <= transmit_byte0_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
endmodule |
module SGMII_MUX(
clk,
wrclk0,
wrclk1,
wrclk2,
wrclk3,
wrclk4,
reset,
//sgmii0
in_xaui0_pkt_wrreq,
in_xaui0_pkt,
out_xaui0_pkt_almostfull,
in_xaui0_pkt_valid_wrreq,
in_xaui0_pkt_valid,
//sgmii1
in_xaui1_pkt_wrreq,
in_xaui1_pkt,
out_xaui1_pkt_almostfull,
in_xaui1_pkt_valid_wrreq,
in_xaui1_pkt_valid,
//sgmii2
in_xaui2_pkt_wrreq,
in_xaui2_pkt,
out_xaui2_pkt_almostfull,
in_xaui2_pkt_valid_wrreq,
in_xaui2_pkt_valid,
//sgmii3
in_xaui3_pkt_wrreq,
in_xaui3_pkt,
out_xaui3_pkt_almostfull,
in_xaui3_pkt_valid_wrreq,
in_xaui3_pkt_valid,
//sgmii4
in_xaui4_pkt_wrreq,
in_xaui4_pkt,
out_xaui4_pkt_almostfull,
in_xaui4_pkt_valid_wrreq,
in_xaui4_pkt_valid,
//to input_ctl
out_xaui_pkt_wrreq,
out_xaui_pkt,
in_xaui_pkt_almostfull,
out_xaui_pkt_valid_wrreq,
out_xaui_pkt_valid,
pkt_inport0,
pkt_inport1,
pkt_inport2,
pkt_inport3,
pkt_inport4,
slot_ID,
card_ID,
receive_pkt_add,
discard_error_pkt_add
);
input clk;
input wrclk0;//sgmii0 FIFO wr clk
input wrclk1;//sgmii1 FIFO wr clk
input wrclk2;//sgmii2 FIFO wr clk
input wrclk3;//sgmii3 FIFO wr clk
input wrclk4;//sgmii4 FIFO wr clk
input reset;
//sgmii0
input in_xaui0_pkt_wrreq;
input [133:0] in_xaui0_pkt;
output out_xaui0_pkt_almostfull;
input in_xaui0_pkt_valid_wrreq;
input in_xaui0_pkt_valid;
//sgmii1
input in_xaui1_pkt_wrreq;
input [133:0] in_xaui1_pkt;
output out_xaui1_pkt_almostfull;
input in_xaui1_pkt_valid_wrreq;
input in_xaui1_pkt_valid;
//sgmii2
input in_xaui2_pkt_wrreq;
input [133:0] in_xaui2_pkt;
output out_xaui2_pkt_almostfull;
input in_xaui2_pkt_valid_wrreq;
input in_xaui2_pkt_valid;
//sgmii3
input in_xaui3_pkt_wrreq;
input [133:0] in_xaui3_pkt;
output out_xaui3_pkt_almostfull;
input in_xaui3_pkt_valid_wrreq;
input in_xaui3_pkt_valid;
//sgmii4
input in_xaui4_pkt_wrreq;
input [133:0] in_xaui4_pkt;
output out_xaui4_pkt_almostfull;
input in_xaui4_pkt_valid_wrreq;
input in_xaui4_pkt_valid;
//to input_ctl
output out_xaui_pkt_wrreq;
output [133:0] out_xaui_pkt;
input in_xaui_pkt_almostfull;
output out_xaui_pkt_valid_wrreq;
output [11:0] out_xaui_pkt_valid;
input [3:0] pkt_inport0;
input [3:0] pkt_inport1;
input [3:0] pkt_inport2;
input [3:0] pkt_inport3;
input [3:0] pkt_inport4;
input [2:0] slot_ID;
input [3:0] card_ID;
output receive_pkt_add;
output discard_error_pkt_add;
reg receive_pkt_add;
reg discard_error_pkt_add;
reg out_xaui_pkt_wrreq;
reg [133:0] out_xaui_pkt;
reg out_xaui_pkt_valid_wrreq;
reg [11:0] out_xaui_pkt_valid;
reg [31:0] port0_pkt_id;
reg [31:0] port1_pkt_id;
reg [31:0] port2_pkt_id;
reg [31:0] port3_pkt_id;
reg [31:0] port4_pkt_id;
reg [2:0] xaui_num;
reg xaui_channel;
reg [10:0] pkt_length;
reg [3:0] current_state;
parameter idle0_s = 4'b0000,
idle1_s = 4'b0001,
idle2_s = 4'b0010,
idle3_s = 4'b0011,
idle4_s = 4'b0100,
add_pkt_s0 = 4'b0101,
add_pkt_s1 = 4'b0110,
discard_s = 4'b0111,
transmit_s = 4'b1000;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt <= 134'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
out_xaui_pkt_valid <= 12'b0;
in_xaui0_pkt_rdreq <= 1'b0;
in_xaui0_pkt_valid_rdreq <= 1'b0;
in_xaui1_pkt_rdreq <= 1'b0;
in_xaui1_pkt_valid_rdreq <= 1'b0;
in_xaui2_pkt_rdreq <= 1'b0;
in_xaui2_pkt_valid_rdreq <= 1'b0;
in_xaui3_pkt_rdreq <= 1'b0;
in_xaui3_pkt_valid_rdreq <= 1'b0;
in_xaui4_pkt_rdreq <= 1'b0;
in_xaui4_pkt_valid_rdreq <= 1'b0;
port0_pkt_id <= 32'b0;
port1_pkt_id <= 32'b0;
port2_pkt_id <= 32'b0;
port3_pkt_id <= 32'b0;
port4_pkt_id <= 32'b0;
pkt_length <= 11'b0;
xaui_num <= 3'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
current_state <= idle0_s;
end
else
begin
case(current_state)
idle0_s:begin//SGMII0
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
pkt_length <= 11'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
if(in_xaui_pkt_almostfull == 1'b1)
current_state <= idle0_s;
else begin
if(in_xaui0_pkt_valid_empty == 1'b1)//no pkt
current_state <= idle1_s;
else
begin
xaui_num <= 3'b000;//SGMII channl
if(in_xaui0_pkt_valid_q == 1'b0) begin//error pkt
in_xaui0_pkt_valid_rdreq <= 1'b1;
in_xaui0_pkt_rdreq <=1'b1;
current_state <= discard_s;
end
else
begin
in_xaui0_pkt_valid_rdreq <= 1'b1;
in_xaui0_pkt_rdreq <= 1'b0;
current_state <= add_pkt_s0;
end
end
end
end
idle1_s:begin//SGMII1
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
pkt_length <= 11'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
if(in_xaui_pkt_almostfull == 1'b1)
current_state <= idle1_s;
else begin
if(in_xaui1_pkt_valid_empty == 1'b1)//no pkt
current_state <= idle2_s;
else
begin
xaui_num <= 3'b001;
if(in_xaui1_pkt_valid_q == 1'b0)//error pkt
begin
in_xaui1_pkt_valid_rdreq <= 1'b1;
in_xaui1_pkt_rdreq <= 1'b1;
current_state <= discard_s;
end
else
begin
in_xaui1_pkt_valid_rdreq <= 1'b1;
in_xaui1_pkt_rdreq <= 1'b0;
current_state <= add_pkt_s0;
end
end
end
end
idle2_s:begin//SGMII2
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
pkt_length <= 11'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
if(in_xaui_pkt_almostfull == 1'b1)
current_state <= idle2_s;
else begin
if(in_xaui2_pkt_valid_empty == 1'b1)//no pkt
current_state <= idle3_s;
else
begin
xaui_num <= 3'b010;//error pkt
if(in_xaui2_pkt_valid_q == 1'b0)//error pkt
begin
in_xaui2_pkt_valid_rdreq <= 1'b1;
in_xaui2_pkt_rdreq <= 1'b1;
current_state <= discard_s;
end
else
begin
in_xaui2_pkt_valid_rdreq <= 1'b1;
in_xaui2_pkt_rdreq <= 1'b0;
current_state <= add_pkt_s0;
end
end
end
end
idle3_s:begin//SGMII3
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
pkt_length <= 11'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
if(in_xaui_pkt_almostfull == 1'b1)
current_state <= idle3_s;
else begin
if(in_xaui3_pkt_valid_empty == 1'b1)//no pkt
current_state <= idle4_s;
else
begin
xaui_num <= 3'b011;
if(in_xaui3_pkt_valid_q == 1'b0)//error pkt
begin
in_xaui3_pkt_valid_rdreq <= 1'b1;
in_xaui3_pkt_rdreq <= 1'b1;
current_state <= discard_s;
end
else
begin
in_xaui3_pkt_valid_rdreq <= 1'b1;
in_xaui3_pkt_rdreq <= 1'b0;
current_state <= add_pkt_s0;
end
end
end
end
idle4_s:begin//SGMII4
out_xaui_pkt_wrreq <= 1'b0;
out_xaui_pkt_valid_wrreq <= 1'b0;
pkt_length <= 11'b0;
receive_pkt_add <= 1'b0;
discard_error_pkt_add <= 1'b0;
if(in_xaui_pkt_almostfull == 1'b1)
current_state <= idle4_s;
else begin
if(in_xaui4_pkt_valid_empty == 1'b1)//no pkt
current_state <= idle0_s;
else
begin
xaui_num <= 3'b100;
if(in_xaui4_pkt_valid_q == 1'b0)//error pkt
begin
in_xaui4_pkt_valid_rdreq <= 1'b1;
in_xaui4_pkt_rdreq <= 1'b1;
current_state <= discard_s;
end
else
begin
in_xaui4_pkt_valid_rdreq <= 1'b1;
in_xaui4_pkt_rdreq <= 1'b0;
current_state <= add_pkt_s0;
end
end
end
end
discard_s:begin
in_xaui0_pkt_valid_rdreq <= 1'b0;
in_xaui1_pkt_valid_rdreq <= 1'b0;
in_xaui2_pkt_valid_rdreq <= 1'b0;
in_xaui3_pkt_valid_rdreq <= 1'b0;
in_xaui4_pkt_valid_rdreq <= 1'b0;
case(xaui_num[2:0])//
3'b000:begin
if(in_xaui0_pkt_q[133:132]==2'b10)
begin
discard_error_pkt_add <= 1'b1;
in_xaui0_pkt_rdreq <= 1'b0;
current_state <= idle1_s;
end
else
begin
in_xaui0_pkt_rdreq<=1'b1;
current_state <= discard_s;
end
end
3'b001: begin
if(in_xaui1_pkt_q[133:132]==2'b10)
begin
discard_error_pkt_add <= 1'b0;
in_xaui1_pkt_rdreq <= 1'b0;
current_state <= idle2_s;
end
else
begin
in_xaui1_pkt_rdreq<=1'b1;
current_state <= discard_s;
end
end
3'b010: begin
if(in_xaui2_pkt_q[133:132]==2'b10)
begin
discard_error_pkt_add <= 1'b0;
in_xaui2_pkt_rdreq <= 1'b0;
current_state <= idle3_s;
end
else
begin
in_xaui2_pkt_rdreq<=1'b1;
current_state <= discard_s;
end
end
3'b011: begin
if(in_xaui3_pkt_q[133:132]==2'b10)
begin
discard_error_pkt_add <= 1'b0;
in_xaui3_pkt_rdreq <= 1'b0;
current_state <= idle4_s;
end
else
begin
in_xaui3_pkt_rdreq<=1'b1;
current_state <= discard_s;
end
end
default: begin
if(in_xaui4_pkt_q[133:132]==2'b10)
begin
discard_error_pkt_add <= 1'b0;
in_xaui4_pkt_rdreq <= 1'b0;
current_state <= idle0_s;
end
else
begin
in_xaui4_pkt_rdreq<=1'b1;
current_state <= discard_s;
end
end
endcase
end
add_pkt_s0:begin//matedata 0
in_xaui0_pkt_valid_rdreq <= 1'b0;
in_xaui1_pkt_valid_rdreq <= 1'b0;
in_xaui2_pkt_valid_rdreq <= 1'b0;
in_xaui3_pkt_valid_rdreq <= 1'b0;
in_xaui4_pkt_valid_rdreq <= 1'b0;
pkt_length <= pkt_length + 11'd32;//pkt length count
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b01;
out_xaui_pkt[131:128] <= 4'b0;
out_xaui_pkt[127:125] <= 3'b0;//ctl
out_xaui_pkt[124] <= 1'b0;//Encrypt
out_xaui_pkt[123:113] <= 11'b0;//pkt length
out_xaui_pkt[112:110] <= slot_ID;//slot ID
out_xaui_pkt[109:78] <= 32'b0;//
out_xaui_pkt[77:74] <= card_ID;//card ID
out_xaui_pkt[73:64] <= 10'b0;//output port
out_xaui_pkt[63] <= 1'b1;//busy
out_xaui_pkt[57:32] <= 26'b0;//
current_state <= add_pkt_s1;
case(xaui_num[2:0])
3'b000: begin
in_xaui0_pkt_rdreq <=1'b0;
out_xaui_pkt[31:0] <= port0_pkt_id;// port0 sequence ID
port0_pkt_id <= port0_pkt_id +1'b1;
out_xaui_pkt[62:58] <= pkt_inport0;//input port num
end
3'b001: begin
in_xaui1_pkt_rdreq <=1'b0;
out_xaui_pkt[31:0] <= port1_pkt_id;// port1 sequence ID
port1_pkt_id <= port1_pkt_id +1'b1;
out_xaui_pkt[62:58] <= pkt_inport1;//input port num
end
3'b010: begin
in_xaui2_pkt_rdreq <=1'b0;
out_xaui_pkt[31:0] <= port2_pkt_id;// port2 sequence ID
port2_pkt_id <= port2_pkt_id +1'b1;
out_xaui_pkt[62:58] <= pkt_inport2;//input port num
end
3'b011: begin
in_xaui3_pkt_rdreq <=1'b0;
out_xaui_pkt[31:0] <= port3_pkt_id;// port3 sequence ID
port3_pkt_id <= port3_pkt_id +1'b1;
out_xaui_pkt[62:58] <= pkt_inport3;//input port num
end
default: begin
in_xaui4_pkt_rdreq <=1'b0;
out_xaui_pkt[31:0] <= port4_pkt_id;// port4 sequence ID
port4_pkt_id <= port4_pkt_id +1'b1;
out_xaui_pkt[62:58] <= pkt_inport4;//input port num
end
endcase
end
add_pkt_s1:begin//matadata 1
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:128] <= 4'b0;
out_xaui_pkt[127:0] <= 128'b0;
case(xaui_num[2:0])
3'b000: in_xaui0_pkt_rdreq <=1'b1;
3'b001: in_xaui1_pkt_rdreq <=1'b1;
3'b010: in_xaui2_pkt_rdreq <=1'b1;
3'b011: in_xaui3_pkt_rdreq <=1'b1;
default: in_xaui4_pkt_rdreq <=1'b1;
endcase
current_state <= transmit_s;
end
transmit_s:begin//pkt
case(xaui_num)
3'b000:begin
if(in_xaui0_pkt_q[133:132] == 2'b01)//header
begin
in_xaui0_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:0] <= in_xaui0_pkt_q[131:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
else if(in_xaui0_pkt_q[133:132] == 2'b10)//tail
begin
receive_pkt_add <= 1'b1;
in_xaui0_pkt_rdreq <= 1'b0;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui0_pkt_q[133:0];
out_xaui_pkt_valid_wrreq <= 1'b1;
out_xaui_pkt_valid[11] <= 1'b1;
out_xaui_pkt_valid[10:0] <= pkt_length + 11'd16 - in_xaui0_pkt_q[131:128];
current_state <= idle1_s;
end
else//midle
begin
in_xaui0_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui0_pkt_q[133:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
end
3'b001: begin
if(in_xaui1_pkt_q[133:132] == 2'b01)//header
begin
in_xaui1_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:0] <= in_xaui1_pkt_q[131:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
else if(in_xaui1_pkt_q[133:132] == 2'b10)//tail
begin
receive_pkt_add <= 1'b1;
in_xaui1_pkt_rdreq <= 1'b0;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui1_pkt_q[133:0];
out_xaui_pkt_valid_wrreq <= 1'b1;
out_xaui_pkt_valid[11] <= 1'b1;
out_xaui_pkt_valid[10:0] <= pkt_length + 11'd16 - in_xaui1_pkt_q[131:128];
current_state <= idle2_s;
end
else//midle
begin
in_xaui1_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui1_pkt_q[133:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
end
3'b010: begin
if(in_xaui2_pkt_q[133:132] == 2'b01)//header
begin
in_xaui2_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:0] <= in_xaui2_pkt_q[131:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
else if(in_xaui2_pkt_q[133:132] == 2'b10)//tail
begin
receive_pkt_add <= 1'b1;
in_xaui2_pkt_rdreq <= 1'b0;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui2_pkt_q[133:0];
out_xaui_pkt_valid_wrreq <= 1'b1;
out_xaui_pkt_valid[11] <= 1'b1;
out_xaui_pkt_valid[10:0] <= pkt_length + 11'd16 - in_xaui2_pkt_q[131:128];
current_state <= idle3_s;
end
else//midle
begin
in_xaui2_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui2_pkt_q[133:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
end
3'b011: begin
if(in_xaui3_pkt_q[133:132] == 2'b01)//header
begin
in_xaui3_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:0] <= in_xaui3_pkt_q[131:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
else if(in_xaui3_pkt_q[133:132]== 2'b10)//tail
begin
receive_pkt_add <= 1'b1;
in_xaui3_pkt_rdreq <= 1'b0;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui3_pkt_q[133:0];
out_xaui_pkt_valid_wrreq <= 1'b1;
out_xaui_pkt_valid[11] <= 1'b1;
out_xaui_pkt_valid[10:0] <= pkt_length + 11'd16 - in_xaui3_pkt_q[131:128];
current_state <= idle4_s;
end
else//midle
begin
in_xaui3_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui3_pkt_q[133:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
end
default: begin
if(in_xaui4_pkt_q[133:132] == 2'b01)//header
begin
in_xaui4_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:132] <= 2'b11;
out_xaui_pkt[131:0] <= in_xaui4_pkt_q[131:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
else if(in_xaui4_pkt_q[133:132]== 2'b10)//tail
begin
receive_pkt_add <= 1'b1;
in_xaui4_pkt_rdreq <= 1'b0;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui4_pkt_q[133:0];
out_xaui_pkt_valid_wrreq <= 1'b1;
out_xaui_pkt_valid[11] <= 1'b1;
out_xaui_pkt_valid[10:0] <= pkt_length + 11'd16 - in_xaui4_pkt_q[131:128];
current_state <= idle0_s;
end
else//midle
begin
in_xaui4_pkt_rdreq <= 1'b1;
out_xaui_pkt_wrreq <= 1'b1;
out_xaui_pkt[133:0] <= in_xaui4_pkt_q[133:0];
pkt_length <= pkt_length +11'd16;
current_state <= transmit_s;
end
end
endcase
end
endcase
end
//xaui0
reg in_xaui0_pkt_rdreq;
wire [133:0] in_xaui0_pkt_q;
wire out_xaui0_pkt_almostfull;
wire [7:0] fifo0_na_wrusedw;
reg in_xaui0_pkt_valid_rdreq;
wire in_xaui0_pkt_valid_q;
wire in_xaui0_pkt_valid_empty;
assign out_xaui0_pkt_almostfull = fifo0_na_wrusedw[7];
asyn_256_134 xaui0_pkt(
.aclr(!reset),
.data(in_xaui0_pkt),
.rdclk(clk),
.rdreq(in_xaui0_pkt_rdreq),
.wrclk(wrclk0),
.wrreq(in_xaui0_pkt_wrreq),
.q(in_xaui0_pkt_q),
.wrusedw(fifo0_na_wrusedw)
);
asyn_64_1 xaui0_pkt_valid(
.aclr(!reset),
.data(in_xaui0_pkt_valid),
.rdclk(clk),
.rdreq(in_xaui0_pkt_valid_rdreq),
.wrclk(wrclk0),
.wrreq(in_xaui0_pkt_valid_wrreq),
.q(in_xaui0_pkt_valid_q),
.rdempty(in_xaui0_pkt_valid_empty));
//xaui1
reg in_xaui1_pkt_rdreq;
wire [133:0] in_xaui1_pkt_q;
wire out_xaui1_pkt_almostfull;
wire [7:0] fifo1_na_wrusedw;
reg in_xaui1_pkt_valid_rdreq;
wire in_xaui1_pkt_valid_q;
wire in_xaui1_pkt_valid_empty;
assign out_xaui1_pkt_almostfull = fifo1_na_wrusedw[7];
asyn_256_134 xaui1_pkt(
.aclr(!reset),
.data(in_xaui1_pkt),
.rdclk(clk),
.rdreq(in_xaui1_pkt_rdreq),
.wrclk(wrclk1),
.wrreq(in_xaui1_pkt_wrreq),
.q(in_xaui1_pkt_q),
.wrusedw(fifo1_na_wrusedw)
);
asyn_64_1 xaui1_pkt_valid(
.aclr(!reset),
.data(in_xaui1_pkt_valid),
.rdclk(clk),
.rdreq(in_xaui1_pkt_valid_rdreq),
.wrclk(wrclk1),
.wrreq(in_xaui1_pkt_valid_wrreq),
.q(in_xaui1_pkt_valid_q),
.rdempty(in_xaui1_pkt_valid_empty));
//xaui2
reg in_xaui2_pkt_rdreq;
wire [133:0] in_xaui2_pkt_q;
wire out_xaui2_pkt_almostfull;
wire [7:0] fifo2_na_wrusedw;
reg in_xaui2_pkt_valid_rdreq;
wire in_xaui2_pkt_valid_q;
wire in_xaui2_pkt_valid_empty;
assign out_xaui2_pkt_almostfull = fifo2_na_wrusedw[7];
asyn_256_134 xaui2_pkt(
.aclr(!reset),
.data(in_xaui2_pkt),
.rdclk(clk),
.rdreq(in_xaui2_pkt_rdreq),
.wrclk(wrclk2),
.wrreq(in_xaui2_pkt_wrreq),
.q(in_xaui2_pkt_q),
.wrusedw(fifo2_na_wrusedw)
);
asyn_64_1 xaui2_pkt_valid(
.aclr(!reset),
.data(in_xaui2_pkt_valid),
.rdclk(clk),
.rdreq(in_xaui2_pkt_valid_rdreq),
.wrclk(wrclk2),
.wrreq(in_xaui2_pkt_valid_wrreq),
.q(in_xaui2_pkt_valid_q),
.rdempty(in_xaui2_pkt_valid_empty));
//xaui3
reg in_xaui3_pkt_rdreq;
wire [133:0] in_xaui3_pkt_q;
wire out_xaui3_pkt_almostfull;
wire [7:0] fifo3_na_wrusedw;
reg in_xaui3_pkt_valid_rdreq;
wire in_xaui3_pkt_valid_q;
wire in_xaui3_pkt_valid_empty;
assign out_xaui3_pkt_almostfull = fifo3_na_wrusedw[7];
asyn_256_134 xaui3_pkt(
.aclr(!reset),
.data(in_xaui3_pkt),
.rdclk(clk),
.rdreq(in_xaui3_pkt_rdreq),
.wrclk(wrclk3),
.wrreq(in_xaui3_pkt_wrreq),
.q(in_xaui3_pkt_q),
.wrusedw(fifo3_na_wrusedw)
);
asyn_64_1 xaui3_pkt_valid(
.aclr(!reset),
.data(in_xaui3_pkt_valid),
.rdclk(clk),
.rdreq(in_xaui3_pkt_valid_rdreq),
.wrclk(wrclk3),
.wrreq(in_xaui3_pkt_valid_wrreq),
.q(in_xaui3_pkt_valid_q),
.rdempty(in_xaui3_pkt_valid_empty));
//xaui4
reg in_xaui4_pkt_rdreq;
wire [133:0] in_xaui4_pkt_q;
wire out_xaui4_pkt_almostfull;
wire [7:0] fifo4_na_wrusedw;
reg in_xaui4_pkt_valid_rdreq;
wire in_xaui4_pkt_valid_q;
wire in_xaui4_pkt_valid_empty;
assign out_xaui4_pkt_almostfull = fifo4_na_wrusedw[7];
asyn_256_134 xaui4_pkt(
.aclr(!reset),
.data(in_xaui4_pkt),
.rdclk(clk),
.rdreq(in_xaui4_pkt_rdreq),
.wrclk(wrclk4),
.wrreq(in_xaui4_pkt_wrreq),
.q(in_xaui4_pkt_q),
.wrusedw(fifo4_na_wrusedw)
);
asyn_64_1 xaui4_pkt_valid(
.aclr(!reset),
.data(in_xaui4_pkt_valid),
.rdclk(clk),
.rdreq(in_xaui4_pkt_valid_rdreq),
.wrclk(wrclk4),
.wrreq(in_xaui4_pkt_valid_wrreq),
.q(in_xaui4_pkt_valid_q),
.rdempty(in_xaui4_pkt_valid_empty));
endmodule |
module SGMII_PORT(
clk,
ammc_clk,
reset,
//rx_clk,
sgmii_clk,
out_pkt_wrreq,
out_pkt,
out_valid_wrreq,
out_valid,
out_pkt_almostfull,
out2_pkt_wrreq,
out2_pkt,
//out2_pkt_usedw,
out2_pkt_almost_full,
out2_valid_wrreq,
out2_valid,
pkt_receive_add,
pkt_discard_add,
pkt_send_add,
ref_clk,
txp,
rxp,
address,
write,
read,
writedata,
readdata,
waitrequest,
reconfig_clk//37.5Mhz ----50Mhz
);
input clk;
input ammc_clk;
input sgmii_clk;
//output rx_clk;
input reset;
input out2_pkt_wrreq;//output to port2;
input [133:0] out2_pkt;
output out2_pkt_almost_full;
input out2_valid_wrreq;
input out2_valid;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
output pkt_receive_add;
output pkt_discard_add;
output pkt_send_add;
input ref_clk;
output txp;
input rxp;
input [7:0] address;
input write;
input read;
input [31:0] writedata;
output [31:0] readdata;
output waitrequest;
input reconfig_clk;//37.5Mhz ----50Mhz
wire [7:0] acc_address;
wire acc_write;
wire acc_read;
wire [31:0] acc_writedata;
wire [31:0] acc_readdata;
wire acc_waitrequest;
SGMII_TX SGMII_TX(
.clk (clk),
.reset (reset),
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
.pkt_send_add (pkt_send_add),
.data_in_wrreq (out2_pkt_wrreq),
.data_in (out2_pkt),
.data_in_almostfull (out2_pkt_almost_full),
.data_in_valid_wrreq (out2_valid_wrreq),
.data_in_valid (out2_valid) );
SGMII_RX SGMII_RX(
.reset (reset),
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
.pkt_receive_add (pkt_receive_add),
.pkt_discard_add (pkt_discard_add),
.out_pkt_wrreq (out_pkt_wrreq),
.out_pkt (out_pkt),
.out_pkt_almostfull (out_pkt_almostfull),
.out_valid_wrreq (out_valid_wrreq),
.out_valid (out_valid)
);
wire ff_tx_clk;
wire [31:0] ff_tx_data;
wire [1:0] ff_tx_mod;
wire ff_tx_sop;
wire ff_tx_eop;
wire ff_tx_err;
wire ff_tx_wren;
wire ff_tx_crc_fwd;
wire tx_ff_uflow;
wire ff_tx_rdy;
wire ff_tx_septy;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire reset;
wire ff_rx_clk;
wire ff_rx_rdy;
wire [31:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_a_full;
wire ff_rx_a_empty;
mac_sgmii mac_sgmii(
//MAC Transmit Interface Signals
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
//MAC Receive Interface Signals
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
//MAC Contro
.clk (ammc_clk),
// .address (address),
// .write (write),
// .read (read),
// .writedata (writedata),
// .readdata (readdata),
// .waitrequest (waitrequest),
.reg_addr (address),
.reg_wr (write),
.reg_rd (read),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_busy (waitrequest),
// .reg_addr (acc_address),
// .reg_wr (acc_write),
// .reg_rd (acc_read),
// .reg_data_in (acc_writedata),
// .reg_data_out (acc_readdata),
// .reg_busy (acc_waitrequest),
//reset sgmii
.reset (~reset),
.rxp (rxp),
.txp (txp),
.ref_clk (ref_clk),
//LED
.led_an (),
.led_char_err (),
.led_link (),
.led_disp_err (),
.led_crs (),
.led_col (),
//SERDES Control Signals
.rx_recovclkout (),
//.gxb_cal_blk_clk (ref_clk),
.pcs_pwrdn_out (),
// .gxb_pwrdn_in (1'b0),
//.gxb_pwrdn_in (~reset),//ZQ0830
// .reconfig_clk (reconfig_clk),
.reconfig_togxb (4'b010),
.reconfig_fromgxb ()
// .reconfig_busy (1'b0)
);
//MAC_REG_ACC MAC_REG_ACC(
//.clk (ammc_clk),
//.reset (reset),
//.waitrequest (waitrequest),
//.readdata (readdata),
//
//.address (address),
//.write (write),
//.read (read),
//.writedata (writedata) );
/*MAC_REG_ACC MAC_REG_ACC(
.clk (ammc_clk),
.reset (reset),
.waitrequest (acc_waitrequest),
.readdata (acc_readdata),
.address (acc_address),
.write (acc_write),
.read (acc_read),
.writedata (acc_writedata) );*/
endmodule |
module MAC_REG_ACC(
input clk,
input reset,
input waitrequest,
input [31:0] readdata,
output reg [7:0] address,
output reg write,
output reg read,
output reg [31:0] writedata);
reg [2:0] reg_count;
reg [3:0] count;
reg [1:0] current_state;
parameter idle_s = 2'b00,
wait_clk_s = 2'b01,
write_s = 2'b10,
wait_s = 2'b11;
always@(posedge clk or negedge reset)
if(!reset) begin
address <= 8'b0;
write <= 1'b0;
read <= 1'b0;
writedata <= 32'b0;
reg_count <= 3'b0;
count <= 4'b0;
current_state <= wait_clk_s;
end
else begin
case(current_state)
wait_clk_s:begin
reg_count <= 3'b0;
count <=count +1'b1;
if(count[3] == 1'b1)
current_state <= idle_s;
else
current_state <= wait_clk_s;
end
idle_s: begin
address <= 8'b0;
write <= 1'b0;
read <= 1'b0;
writedata <= 32'b0;
count <= 4'b0;
if(reg_count < 3'd4)begin
reg_count <= reg_count + 3'b1;
current_state <= write_s;
end
else begin
current_state <= idle_s;
end
end
write_s: begin
current_state <= wait_s;
case(reg_count)
3'd1: begin
address <= 8'h2;
write <= 1'b1;
writedata <= 32'h1000093;
end
3'd2: begin
address <= 8'he;
write <= 1'b1;
writedata <= 32'h4;
end
3'd3: begin
address <= 8'h94;
write <= 1'b1;
writedata <= 32'h7;
end
default: begin
address <= 8'h2;
writedata <= 32'h1000093;
end
endcase
end
wait_s: begin
write <= 1'b1;
if(waitrequest == 1'b0)begin
current_state <= idle_s;
write <= 1'b1;
end
else begin
current_state <= wait_s;
end
end
endcase
end
endmodule |
module OUTPUT_CTL(
clk,
reset,
in_egress_pkt_wr,
in_egress_pkt,
in_egress_pkt_valid_wr,
in_egress_pkt_valid,
out_egress_pkt_almostfull,
out_slot0_pkt,
out_slot0_pkt_wr,
out_slot0_pkt_valid,
out_slot0_pkt_valid_wr,
in_slot0_pkt_almostfull,
out_slot1_pkt,
out_slot1_pkt_wr,
out_slot1_pkt_valid,
out_slot1_pkt_valid_wr,
in_slot1_pkt_almostfull,
output_receive_pkt_add,
output_discard_error_pkt_add,
output_send_slot0_pkt_add,
output_send_slot1_pkt_add
);
input clk;
input reset;
input in_egress_pkt_wr;
input [133:0] in_egress_pkt;
input in_egress_pkt_valid_wr;
input in_egress_pkt_valid;
output wire out_egress_pkt_almostfull;
output reg [133:0] out_slot0_pkt;
output reg out_slot0_pkt_wr;
output reg out_slot0_pkt_valid;
output reg out_slot0_pkt_valid_wr;
input in_slot0_pkt_almostfull;
output reg [133:0] out_slot1_pkt;
output reg out_slot1_pkt_wr;
output reg out_slot1_pkt_valid;
output reg out_slot1_pkt_valid_wr;
input in_slot1_pkt_almostfull;
output reg output_receive_pkt_add;
output reg output_discard_error_pkt_add;
output reg output_send_slot0_pkt_add;
output reg output_send_slot1_pkt_add;
reg [2:0] xaui_channel;
reg [2:0] current_state;//transmit processed pkt to 4 paths by the outport in the metadata of pkt
parameter idle_s = 3'b000,
discard_s = 3'b001,
transmit_s = 3'b010,
wait_s = 3'b011,
pkt_cut_s = 3'b100;
always@(posedge clk or negedge reset)
if(!reset)
begin
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
in_egress_pkt_rd <= 1'b0;
xaui_channel <= 3'b0;//slot ID
output_receive_pkt_add <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
current_state <= idle_s;
end
else
begin
case(current_state)
idle_s:begin//judge and poll pkt from pcietx and iace fifo,and reverse order metadata
out_slot0_pkt_wr <= 1'b0;
out_slot0_pkt <= 134'b0;
out_slot0_pkt_valid_wr <= 1'b0;
out_slot0_pkt_valid <= 1'b0;
out_slot1_pkt_wr <= 1'b0;
out_slot1_pkt <= 134'b0;
out_slot1_pkt_valid_wr <= 1'b0;
out_slot1_pkt_valid <= 1'b0;
output_discard_error_pkt_add <= 1'b0;
output_send_slot0_pkt_add <= 1'b0;
output_send_slot1_pkt_add <= 1'b0;
if(in_egress_pkt_valid_empty == 1'b0) begin//judge and poll pkt from pcietx and iace fifo
if(in_egress_pkt_valid_q == 1'b1) begin
if(in_egress_pkt_q[110] == 1'b0) begin//SLOTid
if(in_slot0_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];//slot ID
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
else begin
if(in_slot1_pkt_almostfull == 1'b1) begin
current_state <= idle_s;
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
xaui_channel <= in_egress_pkt_q[112:110];
output_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
end
end
else begin
in_egress_pkt_rd <= 1'b1;
in_egress_pkt_valid_rd <= 1'b1;
current_state <= discard_s;
end
end
else
current_state <= idle_s;
end
discard_s:begin//discard the error pkt from pcietx
in_egress_pkt_valid_rd <= 1'b0;
if(in_egress_pkt_q[133:132]==2'b10)
begin
output_discard_error_pkt_add <= 1'b1;
in_egress_pkt_rd <= 1'b0;
current_state <= idle_s;
end
else
begin
current_state<= discard_s;
end
end
transmit_s:begin//transmit pkt body from pcietx
output_receive_pkt_add <= 1'b0;
in_egress_pkt_valid_rd <= 1'b0;
case(xaui_channel[2:0])//slot
3'b000:begin
out_slot0_pkt_wr <=1'b1;
out_slot0_pkt <= in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot0_pkt_valid_wr <= 1'b1;
output_send_slot0_pkt_add <= 1'b1;
out_slot0_pkt_valid <= 1'b1;
current_state<= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <= 1'b1;
current_state<= transmit_s;
end
end
3'b001:begin
out_slot1_pkt_wr <=1'b1;
out_slot1_pkt <=in_egress_pkt_q;
if(in_egress_pkt_q[133:132]==2'b10)//pkt tail
begin
in_egress_pkt_rd <= 1'b0;
out_slot1_pkt_valid_wr <= 1'b1;
output_send_slot1_pkt_add <= 1'b1;
out_slot1_pkt_valid <= 1'b1;
current_state <= idle_s;
end
else//pkt head and pkt middle
begin
in_egress_pkt_rd <=1'b1;
current_state<= transmit_s;
end
end
endcase
end
endcase
end
wire [7:0] in_egress_pkt_usedw;
assign out_egress_pkt_almostfull = in_egress_pkt_usedw[7];
reg in_egress_pkt_rd;
wire [133:0] in_egress_pkt_q;
fifo_256_134 egress_pkt(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt),
.rdreq(in_egress_pkt_rd),
.wrreq(in_egress_pkt_wr),
.q(in_egress_pkt_q),
.usedw(in_egress_pkt_usedw)
);
reg in_egress_pkt_valid_rd;
wire in_egress_pkt_valid_empty;
wire in_egress_pkt_valid_q;
fifo_64_1 egress_pkt_valid(
.aclr(!reset),
.clock(clk),
.data(in_egress_pkt_valid),
.rdreq(in_egress_pkt_valid_rd),
.wrreq(in_egress_pkt_valid_wr),
.empty(in_egress_pkt_valid_empty),
.q(in_egress_pkt_valid_q)
);
endmodule |
module SGMII_TX1(
clk,
reset,
ff_tx_clk,
ff_tx_data,//
ff_tx_sop,
ff_tx_eop,
ff_tx_err,
ff_tx_wren,
ff_tx_crc_fwd,//CRC ADD
tx_ff_uflow,
ff_tx_rdy,//core ready
ff_tx_septy,
ff_tx_a_full,
ff_tx_a_empty,
pkt_send_add,
data_in_wrreq,
data_in,
data_in_almostfull,
data_in_valid_wrreq,
data_in_valid );
input clk;
input reset;
input ff_tx_clk;
output [7:0] ff_tx_data;
output ff_tx_sop;
output ff_tx_eop;
output ff_tx_err;
output ff_tx_wren;
output ff_tx_crc_fwd;
input tx_ff_uflow;
input ff_tx_rdy;
input ff_tx_septy;
input ff_tx_a_full;
input ff_tx_a_empty;
output pkt_send_add;
input data_in_wrreq;
input [133:0] data_in;
output data_in_almostfull;
input data_in_valid_wrreq;
input data_in_valid;
reg [7:0] ff_tx_data;
reg ff_tx_sop;
reg ff_tx_eop;
reg ff_tx_err;
reg ff_tx_wren;
reg ff_tx_crc_fwd;
reg pkt_send_add;
reg [133:0] data_in_q_r;
reg [4:0]current_state;
parameter idle_s = 5'b00000,
transmit_byte0_s = 5'b00001,
transmit_byte1_s = 5'b00010,
transmit_byte2_s = 5'b00011,
transmit_byte3_s = 5'b00100,
transmit_byte4_s = 5'b00101,
transmit_byte5_s = 5'b00110,
transmit_byte6_s = 5'b00111,
transmit_byte7_s = 5'b01000,
transmit_byte8_s = 5'b01001,
transmit_byte9_s = 5'b01010,
transmit_byte10_s = 5'b01011,
transmit_byte11_s = 5'b01100,
transmit_byte12_s = 5'b01101,
transmit_byte13_s = 5'b01110,
transmit_byte14_s = 5'b01111,
transmit_byte15_s = 5'b10000,
discard_s = 5'b10001;
always@(posedge ff_tx_clk or negedge reset)
if(!reset) begin
ff_tx_data <= 8'b0;
ff_tx_sop <= 1'b0;
ff_tx_eop <= 1'b0;
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b0;
ff_tx_crc_fwd <= 1'b1;
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
data_in_q_r <= 134'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ff_tx_crc_fwd <= 1'b1;
ff_tx_wren <= 1'b0;
ff_tx_eop <= 1'b0;
if(ff_tx_rdy == 1'b1) begin
if(!data_in_valid_empty) begin//0:has pkt 1:no pkt
if(data_in_valid_q == 1'b1) begin//pkt valid
data_in_rdreq <= 1'b1;
data_in_valid_rdreq <= 1'b1;
pkt_send_add <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
else begin//pkt error
data_in_rdreq <= 1'b1;
data_in_valid_rdreq <= 1'b1;
current_state <= discard_s;
end
end
else begin
current_state <= idle_s;
end
end
else begin
current_state <= idle_s;
end
end
transmit_byte0_s: begin
data_in_rdreq <= 1'b0;
data_in_valid_rdreq <= 1'b0;
pkt_send_add <= 1'b0;
if(ff_tx_rdy == 1'b0) begin//MAC core don't ready need wait
current_state <= transmit_byte0_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[127:120];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b01) begin//pkt head
ff_tx_sop <= 1'b1;
current_state <= transmit_byte1_s;
end
else if(data_in_q_r[133:132] == 2'b10) begin//pkt tail
if(data_in_q_r[131:128] == 4'b1111) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
end
transmit_byte1_s: begin
ff_tx_sop <= 1'b0;
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte1_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[119:112];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1110) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
end
transmit_byte2_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte2_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[111:104];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1101) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
end
transmit_byte3_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte3_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[103:96];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1100) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte4_s;
end
end
else begin
current_state <= transmit_byte4_s;
end
end
end
transmit_byte4_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte4_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[95:88];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1011) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte5_s;
end
end
else begin
current_state <= transmit_byte5_s;
end
end
end
transmit_byte5_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte5_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[87:80];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1010) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte6_s;
end
end
else begin
current_state <= transmit_byte6_s;
end
end
end
transmit_byte6_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte6_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[79:72];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1001) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte7_s;
end
end
else begin
current_state <= transmit_byte7_s;
end
end
end
transmit_byte7_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte7_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[71:64];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b1000) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte8_s;
end
end
else begin
current_state <= transmit_byte8_s;
end
end
end
transmit_byte8_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte8_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[63:56];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0111) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte9_s;
end
end
else begin
current_state <= transmit_byte9_s;
end
end
end
transmit_byte9_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte9_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[55:48];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0110) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte10_s;
end
end
else begin
current_state <= transmit_byte10_s;
end
end
end
transmit_byte10_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte10_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[47:40];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0101) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte11_s;
end
end
else begin
current_state <= transmit_byte11_s;
end
end
end
transmit_byte11_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte11_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[39:32];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0100) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte12_s;
end
end
else begin
current_state <= transmit_byte12_s;
end
end
end
transmit_byte12_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte12_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[31:24];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0011) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte13_s;
end
end
else begin
current_state <= transmit_byte13_s;
end
end
end
transmit_byte13_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte13_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[23:16];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0010) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte14_s;
end
end
else begin
current_state <= transmit_byte14_s;
end
end
end
transmit_byte14_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte14_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[15:8];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0001) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= transmit_byte15_s;
end
end
else begin
current_state <= transmit_byte15_s;
end
end
end
transmit_byte15_s: begin
if(ff_tx_rdy == 1'b0) begin
current_state <= transmit_byte15_s;
ff_tx_wren <= 1'b0;
end
else begin
ff_tx_data <= data_in_q_r[7:0];
ff_tx_err <= 1'b0;
ff_tx_wren <= 1'b1;
if(data_in_q_r[133:132] == 2'b10) begin
if(data_in_q_r[131:128] == 4'b0000) begin
ff_tx_eop <= 1'b1;
ff_tx_crc_fwd <= 1'b0;
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
end
else begin
data_in_rdreq <= 1'b1;
data_in_q_r <= data_in_q;
current_state <= transmit_byte0_s;
end
end
end
discard_s: begin
data_in_valid_rdreq <= 1'b0;
if(data_in_q[133:132]==2'b10) begin
data_in_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
data_in_rdreq <= 1'b1;
current_state <= discard_s;
end
end
endcase
end
reg data_in_rdreq;
wire [7:0] data_in_usedw;
assign data_in_almostfull = data_in_usedw[7];
wire [133:0] data_in_q;
asyn_256_134 asyn_256_134(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_wrreq),
.data(data_in),
.rdclk(ff_tx_clk),
.rdreq(data_in_rdreq),
.q(data_in_q),
.wrusedw(data_in_usedw)
);
reg data_in_valid_rdreq;
wire data_in_valid_q;
wire data_in_valid_empty;
asyn_64_1 asyn_64_1(
.aclr(!reset),
.wrclk(clk),
.wrreq(data_in_valid_wrreq),
.data(data_in_valid),
.rdclk(ff_tx_clk),
.rdreq(data_in_valid_rdreq),
.q(data_in_valid_q),
.rdempty(data_in_valid_empty)
);
endmodule |
module INPUT_CTL(
clk,
reset,
pkt_send_count,
//-------From MUX0 FIFO--------------------
in_xaui0_pkt_wr,
in_xaui0_pkt,
out_xaui0_pkt_almostfull,
in_xaui0_pkt_valid_wr,
in_xaui0_pkt_valid,
//-------From MUX1 FIFO--------------------
in_xaui1_pkt_wr,
in_xaui1_pkt,
out_xaui1_pkt_almostfull,
in_xaui1_pkt_valid_wr,
in_xaui1_pkt_valid,
//-------To ingress FIFO--------------------
out_xaui_pkt_wr,
out_xaui_pkt,
in_xaui_pkt_almostfull,
out_xaui_valid_wr,
out_xaui_valid,
inputctl_receive_pkt_add);
input clk;
input reset;
input in_xaui0_pkt_wr;
input [133:0] in_xaui0_pkt;
output out_xaui0_pkt_almostfull;
input in_xaui0_pkt_valid_wr;
input [11:0] in_xaui0_pkt_valid;
input in_xaui1_pkt_wr;
input [133:0] in_xaui1_pkt;
output out_xaui1_pkt_almostfull;
input in_xaui1_pkt_valid_wr;
input [11:0] in_xaui1_pkt_valid;
output out_xaui_pkt_wr;
output [133:0] out_xaui_pkt;
input in_xaui_pkt_almostfull;
output out_xaui_valid_wr;
output out_xaui_valid;
output inputctl_receive_pkt_add;
reg inputctl_receive_pkt_add;
reg out_xaui_pkt_wr;
reg [133:0] out_xaui_pkt;
reg out_xaui_valid_wr;
reg out_xaui_valid;
reg in_xaui0_pkt_rd;
reg in_xaui0_pkt_valid_rd;
wire in_xaui0_pkt_valid_empty;
reg in_xaui1_pkt_rd;
reg in_xaui1_pkt_valid_rd;
wire in_xaui1_pkt_valid_empty;
reg turner;
reg [1:0] current_state;//receive pkts from two paths,add necessary message for other module and transmit these processed pkt
output [31:0] pkt_send_count;
reg [31:0] pkt_send_count;//sum of the pkt have send
parameter idle_s = 2'b00,
transmit_s = 2'b01,
transmit1_s = 2'b10;
always@(posedge clk or negedge reset)
if(!reset)begin
out_xaui_pkt_wr <= 1'b0;
out_xaui_pkt <= 134'b0;
out_xaui_valid_wr <= 1'b0;
out_xaui_valid <= 1'b0;
in_xaui0_pkt_rd <= 1'b0;
in_xaui0_pkt_valid_rd <= 1'b0;
in_xaui1_pkt_rd <= 1'b0;
in_xaui1_pkt_valid_rd <= 1'b0;
turner <= 1'b0;
pkt_send_count <= 32'b0;
inputctl_receive_pkt_add <= 1'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin//receive pkt by poll fifo of two paths
out_xaui_pkt_wr <= 1'b0;
out_xaui_valid_wr <= 1'b0;
in_xaui0_pkt_rd <= 1'b0;
in_xaui0_pkt_valid_rd <= 1'b0;
in_xaui1_pkt_rd <= 1'b0;
in_xaui1_pkt_valid_rd <= 1'b0;
inputctl_receive_pkt_add <= 1'b0;
case({in_xaui0_pkt_valid_empty,in_xaui1_pkt_valid_empty})//which fifo have complete pkt 0:have 1:have not
2'b01:begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui0_pkt_rd <= 1'b1;
in_xaui0_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
else begin
current_state <= idle_s;
end
end
2'b10:begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui1_pkt_rd <= 1'b1;
in_xaui1_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
current_state <= transmit1_s;
end
else begin
current_state <= idle_s;
end
end
2'b00:begin
if(turner == 1'b0)begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui0_pkt_rd <= 1'b1;
in_xaui0_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
turner <= 1'b1;
current_state <= transmit_s;
end
else begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui1_pkt_rd <= 1'b1;
in_xaui1_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
current_state <= transmit1_s;
end
else begin
current_state <= idle_s;
end
end
end
else begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui1_pkt_rd <= 1'b1;
in_xaui1_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
turner <= 1'b0;
current_state <= transmit1_s;
end
else begin
if(in_xaui_pkt_almostfull == 1'b0) begin
in_xaui0_pkt_rd <= 1'b1;
in_xaui0_pkt_valid_rd <= 1'b1;
inputctl_receive_pkt_add <= 1'b1;
current_state <= transmit_s;
end
else begin
current_state <= idle_s;
end
end
end
end
default:begin
current_state <= idle_s;
end
endcase
end
transmit_s:begin//add outport to the metadata
if(in_xaui0_pkt_q[133:132] == 2'b01) begin
in_xaui0_pkt_rd <= 1'b1;
in_xaui0_pkt_valid_rd <= 1'b0;
inputctl_receive_pkt_add <= 1'b0;
out_xaui_pkt_wr <= 1'b1;
out_xaui_pkt <= in_xaui0_pkt_q;
//out_xaui_pkt[77:64] <= 14'h0000;
out_xaui_pkt[55:47] <= 9'b0;//output port
out_xaui_pkt[123:113] <= in_xaui0_pkt_valid_q[10:0];//pkt length
current_state <= transmit_s;
end
else if(in_xaui0_pkt_q[133:132] == 2'b10)begin
in_xaui0_pkt_rd <= 1'b0;
out_xaui_pkt <= in_xaui0_pkt_q;
pkt_send_count <= pkt_send_count+32'd1;//lxj0107
out_xaui_valid_wr <= 1'b1;
out_xaui_valid <= 1'b1;
current_state <= idle_s;
end
else begin
out_xaui_pkt <= in_xaui0_pkt_q;
current_state <= transmit_s;
end
end
transmit1_s:begin//transmit current pkt to the next module
out_xaui_pkt <= in_xaui1_pkt_q;
if(in_xaui1_pkt_q[133:132] == 2'b01) begin
in_xaui1_pkt_rd <= 1'b1;
in_xaui1_pkt_valid_rd <= 1'b0;
inputctl_receive_pkt_add <= 1'b0;
out_xaui_pkt_wr <= 1'b1;
out_xaui_pkt[55:47] <= 9'b0;//lxj0605
//out_xaui_pkt[77:64] <= 14'h0000;
out_xaui_pkt[123:113] <= in_xaui1_pkt_valid_q[10:0];//pkt length
current_state <= transmit1_s;
end
else if(in_xaui1_pkt_q[133:132] == 2'b10)begin
in_xaui1_pkt_rd <= 1'b0;
out_xaui_pkt <= in_xaui1_pkt_q;
pkt_send_count <= pkt_send_count+32'd1;//lxj0107
out_xaui_valid_wr <= 1'b1;
out_xaui_valid <= 1'b1;
current_state <= idle_s;
end
else begin
out_xaui_pkt <= in_xaui1_pkt_q;
current_state <= transmit1_s;
end
end
default:current_state <= idle_s;
endcase
end
wire [133:0] in_xaui0_pkt_q;
wire [7:0] out_xaui0_pkt_usedw;
assign out_xaui0_pkt_almostfull = out_xaui0_pkt_usedw[7];
fifo_256_134 FIFO_XAUI0_PKT(
.aclr(!reset),
.data(in_xaui0_pkt),
.clock(clk),
.rdreq(in_xaui0_pkt_rd),
.wrreq(in_xaui0_pkt_wr),
.q(in_xaui0_pkt_q),
.usedw(out_xaui0_pkt_usedw)
);
wire [11:0] in_xaui0_pkt_valid_q;
fifo_64_12 FIFO_XAUI0_VALID(
.aclr(!reset),
.data(in_xaui0_pkt_valid),
.clock(clk),
.rdreq(in_xaui0_pkt_valid_rd),
.wrreq(in_xaui0_pkt_valid_wr),
.q(in_xaui0_pkt_valid_q),
.empty(in_xaui0_pkt_valid_empty));
wire [133:0] in_xaui1_pkt_q;
wire [7:0] out_xaui1_pkt_usedw;
assign out_xaui1_pkt_almostfull = out_xaui1_pkt_usedw[7];
fifo_256_134 FIFO_XAUI1_PKT(
.aclr(!reset),
.data(in_xaui1_pkt),
.clock(clk),
.rdreq(in_xaui1_pkt_rd),
.wrreq(in_xaui1_pkt_wr),
.q(in_xaui1_pkt_q),
.usedw(out_xaui1_pkt_usedw)
);
wire [11:0] in_xaui1_pkt_valid_q;
fifo_64_12 FIFO_XAUI1_VALID(
.aclr(!reset),
.data(in_xaui1_pkt_valid),
.clock(clk),
.rdreq(in_xaui1_pkt_valid_rd),
.wrreq(in_xaui1_pkt_valid_wr),
.q(in_xaui1_pkt_valid_q),
.empty(in_xaui1_pkt_valid_empty));
endmodule |
module search_engine(
clk,
reset,
key_in_valid,
key_in,
bv_out_valid,
bv_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_in_valid;
input [71:0] key_in;
output wire bv_out_valid;
output wire [35:0] bv_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
reg set_valid[0:7];
reg read_valid[0:7];
reg [8:0] addr;
wire data_out_valid[0:7];
wire [35:0] data_out[0:7];
wire stage_enable[0:1];
wire bv_valid_temp[0:7];
wire [35:0] bv_temp[0:7];
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--set--//
reg [31:0] localbus_addr;
reg [35:0] set_data_temp;
wire[35:0] data_out_temp;
wire data_out_valid_temp;
reg [35:0] data_out_temp_reg;
assign data_out_valid_temp = (data_out_valid[0] == 1'b1)? 1'b1:
(data_out_valid[1] == 1'b1)? 1'b1:
(data_out_valid[2] == 1'b1)? 1'b1:
(data_out_valid[3] == 1'b1)? 1'b1:
(data_out_valid[4] == 1'b1)? 1'b1:
(data_out_valid[5] == 1'b1)? 1'b1:
(data_out_valid[6] == 1'b1)? 1'b1:
(data_out_valid[7] == 1'b1)? 1'b1:
1'b0;
assign data_out_temp = (data_out_valid[0] == 1'b1)? data_out[0]:
(data_out_valid[1] == 1'b1)? data_out[1]:
(data_out_valid[2] == 1'b1)? data_out[2]:
(data_out_valid[3] == 1'b1)? data_out[3]:
(data_out_valid[4] == 1'b1)? data_out[4]:
(data_out_valid[5] == 1'b1)? data_out[5]:
(data_out_valid[6] == 1'b1)? data_out[6]:
(data_out_valid[7] == 1'b1)? data_out[7]:
36'b0;
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
set_data_temp <= 36'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_temp[35:32] <= localbus_data[3:0];
1'd1:
begin
set_data_temp[31:0] <= localbus_data;
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: set_valid[0] <= 1'b1;
3'd1: set_valid[1] <= 1'b1;
3'd2: set_valid[2] <= 1'b1;
3'd3: set_valid[3] <= 1'b1;
3'd4: set_valid[4] <= 1'b1;
3'd5: set_valid[5] <= 1'b1;
3'd6: set_valid[6] <= 1'b1;
3'd7: set_valid[7] <= 1'b1;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: read_valid[0] <= 1'b1;
3'd1: read_valid[1] <= 1'b1;
3'd2: read_valid[2] <= 1'b1;
3'd3: read_valid[3] <= 1'b1;
3'd4: read_valid[4] <= 1'b1;
3'd5: read_valid[5] <= 1'b1;
3'd6: read_valid[6] <= 1'b1;
3'd7: read_valid[7] <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out_temp_reg[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
if(data_out_valid_temp == 1'b1)begin
localbus_data_out <={28'b0,data_out_temp[35:32]};
data_out_temp_reg <= data_out_temp;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
generate
genvar i;
for(i=0; i<8; i= i+1) begin : lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.set_valid(set_valid[i]),
.set_data(set_data_temp[35:0]),
.read_valid(read_valid[i]),
.addr(addr),
.data_out_valid(data_out_valid[i]),
.data_out(data_out[i]),
.key_valid(key_in_valid),
.key(key_in[((i+1)*9-1):i*9]),
.bv_valid(bv_valid_temp[i]),
.bv(bv_temp[i])
);
end
endgenerate
bv_and_8 bv_and_8(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_valid_temp[0]),
.bv_1(bv_temp[0]),
.bv_2(bv_temp[1]),
.bv_3(bv_temp[2]),
.bv_4(bv_temp[3]),
.bv_5(bv_temp[4]),
.bv_6(bv_temp[5]),
.bv_7(bv_temp[6]),
.bv_8(bv_temp[7]),
.bv_out_valid(bv_out_valid),
.bv_out(bv_out)
);
endmodule |
module lookup(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
metadata_valid,
metadata,
countid_valid,
countid
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output wire localbus_ack_n;
output wire [31:0] localbus_data_out;
input metadata_valid;
input [287:0] metadata;// 32*9
output wire countid_valid;
output wire [5:0] countid;// rule num_max = 64;
//-------temp------//
wire localbus_ale_temp[0:3];
wire localbus_ack_n_temp[0:3];
wire [31:0] localbus_data_out_temp[0:3];
wire bv_out_valid[0:3];
wire [35:0] bv_out[0:3];
wire bv_and_valid;
wire [63:0] bv_and;
assign localbus_ale_temp[0] = (localbus_data[18:16] == 3'd0)? localbus_ale:1'b0;
assign localbus_ale_temp[1] = (localbus_data[18:16] == 3'd1)? localbus_ale:1'b0;
assign localbus_ale_temp[2] = (localbus_data[18:16] == 3'd2)? localbus_ale:1'b0;
assign localbus_ale_temp[3] = (localbus_data[18:16] == 3'd3)? localbus_ale:1'b0;
assign localbus_ack_n = (localbus_ack_n_temp[0] == 1'b0)? 1'b0:
(localbus_ack_n_temp[1] == 1'b0)? 1'b0:
(localbus_ack_n_temp[2] == 1'b0)? 1'b0:
(localbus_ack_n_temp[3] == 1'b0)? 1'b0:
1'b1;
assign localbus_data_out = (localbus_ack_n_temp[0] == 1'b0)? localbus_data_out_temp[0]:
(localbus_ack_n_temp[1] == 1'b0)? localbus_data_out_temp[1]:
(localbus_ack_n_temp[2] == 1'b0)? localbus_data_out_temp[2]:
(localbus_ack_n_temp[3] == 1'b0)? localbus_data_out_temp[3]:
32'b0;
generate
genvar i;
for(i=0; i<4; i=i+1) begin : search_engine
search_engine se(
.clk(clk),
.reset(reset),
.key_in_valid(metadata_valid),
.key_in(metadata[((i+1)*72-1):i*72]),
.bv_out_valid(bv_out_valid[i]),
.bv_out(bv_out[i]),
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),
.localbus_data(localbus_data),
.localbus_ale(localbus_ale_temp[i]),
.localbus_ack_n(localbus_ack_n_temp[i]),
.localbus_data_out(localbus_data_out_temp[i])
);
end
endgenerate
bv_and_4 bv_and_4(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_out_valid[0]),
.bv_1(bv_out[0]),
.bv_2(bv_out[1]),
.bv_3(bv_out[2]),
.bv_4(bv_out[3]),
.bv_out_valid(bv_and_valid),
.bv_out(bv_and)
);
calculate_countid calculate_countid(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_and_valid),
.bv_in(bv_and),
.countid_valid(countid_valid),
.countid(countid)
);
endmodule |
module bv_and_4(
clk,
reset,
bv_in_valid,
bv_1,
bv_2,
bv_3,
bv_4,
bv_out_valid,
bv_out
);
input clk;
input reset;
input bv_in_valid;
input [35:0] bv_1;
input [35:0] bv_2;
input [35:0] bv_3;
input [35:0] bv_4;
output reg bv_out_valid;
output reg [63:0] bv_out;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
bv_out <= 64'b0;
bv_out_valid <= 1'b0;
end
else
begin
if(bv_in_valid == 1'b1)
begin
bv_out <= {28'b0,bv_1 & bv_2 & bv_3 &bv_4};
bv_out_valid <= 1'b1;
end
else bv_out_valid <= 1'b0;
end
end
endmodule |
module calculate_countid(
clk,
reset,
bv_in_valid,
bv_in,
countid_valid,
countid
);
parameter width_bv_and = 64;
parameter width_count = 6;
input clk;
input reset;
input bv_in_valid;
input [width_bv_and-1:0] bv_in;
output wire countid_valid;
output wire [width_count-1:0] countid;
wire [width_count-1:0] count_out[0:width_count];
wire [width_count-1:0] count[0:width_count];
wire bv_valid[0:width_count];
wire [width_bv_and-1:0] bv[0:width_count];
wire bv_out_valid[0:width_count];
wire [width_bv_and-1:0] bv_out[0:width_count];
assign count[width_count] = {width_count{1'b0}};
assign bv_valid[width_count] = bv_in_valid;
assign bv[width_count] = bv_in;
generate
genvar i;
for(i=2; i<= width_count; i=i+1) begin : bv_count
bv_count bv_c
(
.reset(reset),
.clk(clk),
.bv_valid(bv_valid[i]),
.bv(bv[i]),
.count(count[i]),
.bv_out_valid(bv_valid[i-1]),
.bv_out(bv[i-1]),
.count_out(count[i-1])
);
defparam
/*
bv_count[i].bv_c.width = width_bv_and,
bv_count[i].bv_c.width_count= width_count,
bv_count[i].bv_c.stage = i,
bv_count[i].bv_c.range_end = 1<<(i-1);
*/
bv_c.width = width_bv_and,
bv_c.width_count= width_count,
bv_c.stage = i,
bv_c.range_end = 1<<(i-1);
end
endgenerate
bv_count bv_count_1(
.reset(reset),
.clk(clk),
.bv_valid(bv_valid[1]),
.bv(bv[1]),
.count(count[1]),
.bv_out_valid(countid_valid),
.bv_out(bv[0]),
.count_out(countid)
);
endmodule |
module bv_count(
reset,
clk,
bv_valid,
bv,
count,
bv_out_valid,
bv_out,
count_out
);
parameter width = 64;
parameter width_count = 6;
parameter stage = 1;
parameter range_end = 1;
input reset;
input clk;
input bv_valid;
input [width-1:0] bv;
input [width_count-1:0] count;
output reg bv_out_valid;
output reg [width-1:0] bv_out;
output reg [width_count-1:0] count_out;
always @ (posedge clk)begin
if(bv_valid == 1'b1)begin
bv_out_valid <= 1'b1;
if(bv[range_end-1:0])begin
bv_out <= bv;
count_out <= count;
end
else begin
bv_out <= bv >> range_end;
count_out <= count + range_end;
end
end
else begin
bv_out_valid <= 1'b0;
bv_out <= {width{1'b0}};
count_out <= {width_count{1'b0}};
end
end
endmodule |
module lookup_bit(
clk,
reset,
set_valid,
set_data,
read_valid,
addr,
data_out_valid,
data_out,
key_valid,
key,
bv_valid,
bv
);
input clk;
input reset;
input set_valid;
input [35:0] set_data;
input read_valid;
input [8:0] addr;
output reg data_out_valid;
output reg [35:0] data_out;
input key_valid;
input [8:0] key;
output wire bv_valid;
output wire [35:0] bv;
wire stage_enable;
//----ram---//a:lookup; b:set;
reg [8:0] address_b;
reg rden_b;
reg wren_a,wren_b;
reg [35:0] data_b;
wire [35:0] q_a,q_b;
//-------state----//
reg [3:0] set_state;
parameter idle = 4'd0,
read_wait = 4'd1,
read_ram = 4'd3;
//-----------------------state--------------------------//
//---set---//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
data_out_valid <= 1'b0;
end
else
begin
case(set_state)
idle:
begin
data_out_valid <= 1'b0;
if(read_valid == 1'b1)
begin
set_state <= read_wait;
end
end
read_wait:
begin
set_state <= read_ram;
end
read_ram:
begin
data_out_valid <= 1'b1;
data_out <= q_b;
set_state <= idle;
end
default:
begin
set_state <= idle;
end
endcase
end
end
ram_36_512 ram_1(
.address_a(key),
.address_b(addr),
.clock(clk),
.data_a(36'b0),
.data_b(set_data),
.rden_a(key_valid),
.rden_b(read_valid),
.wren_a(1'b0),
.wren_b(set_valid),
.q_a(bv),
.q_b(q_b)
);
hold1clk hold1clk_1(
.clk(clk),
.reset(reset),
.stage_enable_in(key_valid),
.stage_enable_out(stage_enable)
);
hold1clk hold1clk_2(
.clk(clk),
.reset(reset),
.stage_enable_in(stage_enable),
.stage_enable_out(bv_valid)
);
endmodule |
module bv_and_8(
clk,
reset,
bv_in_valid,
bv_1,
bv_2,
bv_3,
bv_4,
bv_5,
bv_6,
bv_7,
bv_8,
bv_out_valid,
bv_out
);
input clk;
input reset;
input bv_in_valid;
input [35:0] bv_1;
input [35:0] bv_2;
input [35:0] bv_3;
input [35:0] bv_4;
input [35:0] bv_5;
input [35:0] bv_6;
input [35:0] bv_7;
input [35:0] bv_8;
output reg bv_out_valid;
output reg [35:0] bv_out;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
bv_out <= 36'b0;
bv_out_valid <= 1'b0;
end
else
begin
if(bv_in_valid == 1'b1)
begin
bv_out <= bv_1 & bv_2 & bv_3 &bv_4 & bv_5 & bv_6 & bv_7 & bv_8;
bv_out_valid <= 1'b1;
end
else bv_out_valid <= 1'b0;
end
end
endmodule |
module fifo_64_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [5:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire [5:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
wire [5:0] usedw = sub_wire3[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module rulefifo_64_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [31:0] q;
output [5:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire [5:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
wire [5:0] usedw = sub_wire3[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fifo_65_256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [64:0] data;
input rdreq;
input wrreq;
output empty;
output [64:0] q;
wire sub_wire0;
wire [64:0] sub_wire1;
wire empty = sub_wire0;
wire [64:0] q = sub_wire1[64:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 65,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module EGRESS_OFFSET(
input clk,
input reset,
input in_tdma_pkt_wr,
input [133:0] in_tdma_pkt,
input in_tdma_valid_wr,
input in_tdma_valid,
output out_tdma_pkt_almostfull,
output reg out_outputctrl_pkt_wr,
output reg [133:0] out_outputctrl_pkt,
output reg out_outputctrl_valid_wr,
output reg out_outputctrl_valid,
input in_outputctrl_pkt_almostfull
);
reg [2:0] prepad_discard_count;//the cycle of pkt can be discard that all of 16 bytes should be offset
reg [3:0] switch_offset_count;//the sum of bytes that the body of pkt should be offset(must <16)
reg [127:0] shift_reg;//store the data that leave by front cycle offset
reg [3:0] tail_valid;//valid bytes of last cycle
reg [1:0] tail_mode;//the process mode of tail of pkt 0:last cycle of pkt will be remain 1:last cycle of pkt will be delete 2: send straight
wire in_tdma_valid_q;
wire in_tdma_valid_empty;
reg out_tdma_valid_rd;
wire [7:0] out_tdma_pkt_usedw;
wire out_tdma_pkt_empty;
assign out_tdma_pkt_almostfull = out_tdma_pkt_usedw[7];//lxj0107
reg out_tdma_pkt_rd;
wire [133:0]in_tdma_pkt_q;
reg [3:0] current_state;
parameter idle_s = 4'd0,
metadata0_s = 4'd1,
metadata1_s = 4'd2,
discard_prepad_s = 4'd3,
send_s = 4'd4,
shift_s = 4'd5,
tail_remain_s = 4'd6;
always@(posedge clk or negedge reset) begin //asynchronous reset
if(!reset) begin
out_outputctrl_pkt_wr<=1'b0;
out_outputctrl_pkt<=134'b0;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
switch_offset_count<=4'b0;
prepad_discard_count<=3'b0;
shift_reg<=128'b0;
tail_valid<=4'b0;
tail_mode<=2'd0;
out_tdma_valid_rd<=1'b0;
out_tdma_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s: begin//wait a complete pkt
out_outputctrl_pkt_wr<=1'b0;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
if((in_tdma_valid_empty==1'b0)&&(in_outputctrl_pkt_almostfull==1'b0))begin
out_tdma_valid_rd<=1'b1;
out_tdma_pkt_rd<=1'b1;
prepad_discard_count<=in_tdma_pkt_q[38:36];//the cycle of pkt that all of 16 bytes should be offset
switch_offset_count<=in_tdma_pkt_q[35:32];//the sum of bytes that the body of pkt should be offset
out_outputctrl_pkt[123:113]<=in_tdma_pkt_q[123:113]-in_tdma_pkt_q[38:32];//the length of pkt have offset
current_state<=metadata0_s;
end
else begin
out_tdma_valid_rd<=1'b0;
out_tdma_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
metadata0_s: begin//send metadata0(length bytes have process in the idle_s state)
out_tdma_valid_rd<=1'b0;
out_outputctrl_pkt_wr<=1'b1;
out_outputctrl_pkt[133:124]<=in_tdma_pkt_q[133:124];
out_outputctrl_pkt[112:0]<=in_tdma_pkt_q[112:0];
if(in_tdma_pkt_q[35:32]!=4'b0) begin//
if(in_tdma_pkt_q[116:113]!=4'b0) begin
if(in_tdma_pkt_q[35:32]<in_tdma_pkt_q[116:113]) begin//last cycle of pkt will be remain
tail_valid<=4'd15-(in_tdma_pkt_q[116:113]-in_tdma_pkt_q[35:32])+4'd1;//valid value of last cycle of pkt
tail_mode<=2'd0;
end
else begin//last cycle of pkt will be delete
tail_valid<=in_tdma_pkt_q[35:32]-in_tdma_pkt_q[116:113];
tail_mode<=2'd1;
end
end
else begin
tail_valid<=in_tdma_pkt_q[35:32];//valid value of last cycle of pkt
tail_mode<=2'd0;
end
end
else begin//pkt send straight
tail_mode<=2'd2;
end
current_state<=metadata1_s;
end
metadata1_s: begin//send the metadata1
out_outputctrl_pkt<=in_tdma_pkt_q;
current_state<=discard_prepad_s;
end
discard_prepad_s: begin//discard one full cycle of offset bytes; and register first cycle of pkt body
prepad_discard_count<=prepad_discard_count-3'd1;
if(prepad_discard_count==3'b0) begin
if(tail_mode[1]==1'd1) begin
out_outputctrl_pkt_wr<=1'b1;
out_outputctrl_pkt<=in_tdma_pkt_q;
current_state<=send_s;////pkt send straight(no need offset,maybe need discard full cycle )
end
else begin
out_outputctrl_pkt_wr<=1'b0;
shift_reg<=in_tdma_pkt_q[127:0];//register first cycle of pkt body
current_state<=shift_s;//store 1 cycle pkt for left shift
end
end
else begin
out_outputctrl_pkt_wr<=1'b0;
current_state<=discard_prepad_s;
end
end
send_s: begin//pkt send straight(no need offset,maybe need discard full cycle )
out_outputctrl_pkt_wr<=1'b1;
out_outputctrl_pkt<=in_tdma_pkt_q;
if(in_tdma_pkt_q[133:132]==2'b10) begin
out_tdma_pkt_rd<=1'b0;
out_outputctrl_valid_wr<=1'b1;
out_outputctrl_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_tdma_pkt_rd<=1'b1;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
current_state<=send_s;
end
end
shift_s: begin//shift body of pkt
shift_reg<=in_tdma_pkt_q[127:0];//store the data that leave by front cycle offset
out_outputctrl_pkt_wr<=1'b1;
if(in_tdma_pkt_q[133:132]==2'b10) begin//pkt tail
out_tdma_pkt_rd<=1'b0;
if(tail_mode==1'b0) begin//last cycle of pkt will be remain
out_outputctrl_pkt[133:128]<=6'b110000;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
current_state<=tail_remain_s;
end
else begin//last cycle of pkt will be delete
out_outputctrl_pkt[133:132]<=2'b10;
out_outputctrl_pkt[131:128]<=tail_valid[3:0];
out_outputctrl_valid_wr<=1'b1;
out_outputctrl_valid<=1'b1;
current_state<=idle_s;
end
end
else begin
out_tdma_pkt_rd<=1'b1;
out_outputctrl_pkt[133:128]<=6'b110000;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
current_state<=shift_s;
end
case(switch_offset_count)
4'd1: begin
out_outputctrl_pkt[127:1*8]<=shift_reg[127-1*8:0];//put the data leave from front cycle to the high site of current cycle pkt
out_outputctrl_pkt[1*8-1:0]<= in_tdma_pkt_q[127:128-1*8];
end
4'd2: begin
out_outputctrl_pkt[127:2*8]<=shift_reg[127-2*8:0];
out_outputctrl_pkt[2*8-1:0]<= in_tdma_pkt_q[127:128-2*8];
end
4'd3: begin
out_outputctrl_pkt[127:3*8]<=shift_reg[127-3*8:0];
out_outputctrl_pkt[3*8-1:0]<= in_tdma_pkt_q[127:128-3*8];
end
4'd4: begin
out_outputctrl_pkt[127:4*8]<=shift_reg[127-4*8:0];
out_outputctrl_pkt[4*8-1:0]<= in_tdma_pkt_q[127:128-4*8];
end
4'd5: begin
out_outputctrl_pkt[127:5*8]<=shift_reg[127-5*8:0];
out_outputctrl_pkt[5*8-1:0]<= in_tdma_pkt_q[127:128-5*8];
end
4'd6: begin
out_outputctrl_pkt[127:6*8]<=shift_reg[127-6*8:0];
out_outputctrl_pkt[6*8-1:0]<= in_tdma_pkt_q[127:128-6*8];
end
4'd7: begin
out_outputctrl_pkt[127:7*8]<=shift_reg[127-7*8:0];
out_outputctrl_pkt[7*8-1:0]<= in_tdma_pkt_q[127:128-7*8];
end
4'd8: begin
out_outputctrl_pkt[127:8*8]<=shift_reg[127-8*8:0];
out_outputctrl_pkt[8*8-1:0]<= in_tdma_pkt_q[127:128-8*8];
end
4'd9: begin
out_outputctrl_pkt[127:9*8]<=shift_reg[127-9*8:0];
out_outputctrl_pkt[9*8-1:0]<= in_tdma_pkt_q[127:128-9*8];
end
4'd10: begin
out_outputctrl_pkt[127:10*8]<=shift_reg[127-10*8:0];
out_outputctrl_pkt[10*8-1:0]<= in_tdma_pkt_q[127:128-10*8];
end
4'd11: begin
out_outputctrl_pkt[127:11*8]<=shift_reg[127-11*8:0];
out_outputctrl_pkt[11*8-1:0]<= in_tdma_pkt_q[127:128-11*8];
end
4'd12: begin
out_outputctrl_pkt[127:12*8]<=shift_reg[127-12*8:0];
out_outputctrl_pkt[12*8-1:0]<= in_tdma_pkt_q[127:128-12*8];
end
4'd13: begin
out_outputctrl_pkt[127:13*8]<=shift_reg[127-13*8:0];
out_outputctrl_pkt[13*8-1:0]<= in_tdma_pkt_q[127:128-13*8];
end
4'd14: begin
out_outputctrl_pkt[127:14*8]<=shift_reg[127-14*8:0];
out_outputctrl_pkt[14*8-1:0]<= in_tdma_pkt_q[127:128-14*8];
end
4'd15: begin
out_outputctrl_pkt[127:15*8]<=shift_reg[127-15*8:0];
out_outputctrl_pkt[15*8-1:0]<= in_tdma_pkt_q[127:128-15*8];
end
default: begin
out_outputctrl_pkt[127:0]<=128'b0;
end
endcase
end
tail_remain_s: begin//the last cycle of pkt can't be offset over,so must modify it and send it.
out_outputctrl_pkt_wr<=1'b1;
out_outputctrl_valid_wr<=1'b1;
out_outputctrl_valid<=1'b1;
out_outputctrl_pkt[133:132]<=2'b10;
out_outputctrl_pkt[131:128]<=tail_valid[3:0];//the sum of invalid bytes
current_state<=idle_s;
case(switch_offset_count)
4'd1: begin
out_outputctrl_pkt[127:1*8]<=shift_reg[127-1*8:0];
end
4'd2: begin
out_outputctrl_pkt[127:2*8]<=shift_reg[127-2*8:0];
end
4'd3: begin
out_outputctrl_pkt[127:3*8]<=shift_reg[127-3*8:0];
end
4'd4: begin
out_outputctrl_pkt[127:4*8]<=shift_reg[127-4*8:0];
end
4'd5: begin
out_outputctrl_pkt[127:5*8]<=shift_reg[127-5*8:0];
end
4'd6: begin
out_outputctrl_pkt[127:6*8]<=shift_reg[127-6*8:0];
end
4'd7: begin
out_outputctrl_pkt[127:7*8]<=shift_reg[127-7*8:0];
end
4'd8: begin
out_outputctrl_pkt[127:8*8]<=shift_reg[127-8*8:0];
end
4'd9: begin
out_outputctrl_pkt[127:9*8]<=shift_reg[127-9*8:0];
end
4'd10: begin
out_outputctrl_pkt[127:10*8]<=shift_reg[127-10*8:0];
end
4'd11: begin
out_outputctrl_pkt[127:11*8]<=shift_reg[127-11*8:0];
end
4'd12: begin
out_outputctrl_pkt[127:12*8]<=shift_reg[127-12*8:0];
end
4'd13: begin
out_outputctrl_pkt[127:13*8]<=shift_reg[127-13*8:0];
end
4'd14: begin
out_outputctrl_pkt[127:14*8]<=shift_reg[127-14*8:0];
end
4'd15: begin
out_outputctrl_pkt[127:15*8]<=shift_reg[127-15*8:0];
end
default: begin
out_outputctrl_pkt[127:0]<=128'b0;
end
endcase
end
default: begin
out_outputctrl_pkt_wr<=1'b0;
out_outputctrl_pkt<=134'b0;
out_outputctrl_valid_wr<=1'b0;
out_outputctrl_valid<=1'b0;
out_tdma_valid_rd<=1'b0;
out_tdma_pkt_rd<=1'b0;
current_state<=idle_s;
end
endcase
end
end
//----------------From PCIE_TX Module-----------------
//----------------VALID FIFO-----------------
fifo_64_1 FIFO_VALID_pcietx (
.aclr(!reset),
.data(in_tdma_valid),
.clock(clk),
.rdreq(out_tdma_valid_rd),
.wrreq(in_tdma_valid_wr),
.q(in_tdma_valid_q),
.empty(in_tdma_valid_empty)
);
//-------------- DATA FIFO-----------------
fifo_256_134 FIFO_PKT_pcietx (
.aclr(!reset),
.data(in_tdma_pkt),
.clock(clk),
.rdreq(out_tdma_pkt_rd),
.wrreq(in_tdma_pkt_wr),
.q(in_tdma_pkt_q),
.usedw(out_tdma_pkt_usedw),
.empty(out_tdma_pkt_empty)
);
endmodule |
module EGRESS(
input clk,
input reset,
input in_tdma_pkt_wr,
input [133:0] in_tdma_pkt,
input in_tdma_valid_wr,
input in_tdma_valid,
output out_tdma_pkt_almostfull,
output out_outputctrl_pkt_wr,
output [133:0] out_outputctrl_pkt,
output out_outputctrl_valid_wr,
output out_outputctrl_valid,
input in_outputctrl_pkt_almostfull
);
EGRESS_OFFSET EGRESS_OFFSET(
.clk(clk),
.reset(reset),
.in_tdma_pkt_wr(in_tdma_pkt_wr),
.in_tdma_pkt(in_tdma_pkt),
.in_tdma_valid_wr(in_tdma_valid_wr),
.in_tdma_valid(in_tdma_valid),
.out_tdma_pkt_almostfull(out_tdma_pkt_almostfull),
.out_outputctrl_pkt_wr(out_outputctrl_pkt_wr),
.out_outputctrl_pkt(out_outputctrl_pkt),
.out_outputctrl_valid_wr(out_outputctrl_valid_wr),
.out_outputctrl_valid(out_outputctrl_valid),
.in_outputctrl_pkt_almostfull(in_outputctrl_pkt_almostfull)
);
endmodule |
module INGRESS(
input clk,
input reset,
input in_inputctrl_pkt_wr,
input [133:0] in_inputctrl_pkt,
input in_inputctrl_valid_wr,
input in_inputctrl_valid,
output out_inputctrl_pkt_almostfull,
output out_class_key_wr,
output [133:0] out_class_key,
input in_class_key_almostfull,
output out_class_valid,
output out_class_valid_wr,
input in_class_key_wr,
input [133:0] in_class_key,
input in_class_valid_wr,
input in_class_valid,
output out_class_key_almostfull,
output out_dispather_pkt_wr,
output [133:0] out_dispather_pkt,
output out_dispather_valid_wr,
output out_dispather_valid,
input in_dispather_pkt_almostfull
);
wire out_offset_pkt_wr;
wire [133:0] out_offset_pkt;
wire out_offset_valid;
wire out_offset_valid_wr;
wire in_offset_pkt_almostfull;
INGRESS_CTRL INGRESS_CTRL(
.clk(clk),
.reset(reset),
.in_inputctrl_pkt_wr(in_inputctrl_pkt_wr),
.in_inputctrl_pkt(in_inputctrl_pkt),
.in_inputctrl_valid_wr(in_inputctrl_valid_wr),
.in_inputctrl_valid(in_inputctrl_valid),
.out_inputctrl_pkt_almostfull(out_inputctrl_pkt_almostfull),
.out_class_key_wr(out_class_key_wr),
.out_class_key(out_class_key),
.in_class_key_almostfull(in_class_key_almostfull),
.out_class_valid(out_class_valid),
.out_class_valid_wr(out_class_valid_wr),
.out_offset_pkt_wr(out_offset_pkt_wr),
.out_offset_pkt(out_offset_pkt),
.out_offset_valid(out_offset_valid),
.out_offset_valid_wr(out_offset_valid_wr),
.in_offset_pkt_almostfull(in_offset_pkt_almostfull)
);
INGRESS_OFFSET INGRESS_OFFSET(
.clk(clk),
.reset(reset),
.in_class_key_wr(in_class_key_wr),
.in_class_key(in_class_key),
.in_class_valid_wr(in_class_valid_wr),
.in_class_valid(in_class_valid),
.out_class_key_almostfull(out_class_key_almostfull),
.in_ingress_pkt_wr(out_offset_pkt_wr),
.in_ingress_pkt(out_offset_pkt),
.in_ingress_valid_wr(out_offset_valid_wr),
.in_ingress_valid(out_offset_valid),
.out_ingress_pkt_almostfull(in_offset_pkt_almostfull),
.out_dispather_pkt_wr(out_dispather_pkt_wr),
.out_dispather_pkt(out_dispather_pkt),
.out_dispather_valid_wr(out_dispather_valid_wr),
.out_dispather_valid(out_dispather_valid),
.in_dispather_pkt_almostfull(in_dispather_pkt_almostfull)
);
endmodule |
module INGRESS_OFFSET(
input clk,
input reset,
input in_class_key_wr,
input [133:0] in_class_key,
input in_class_valid_wr,
input in_class_valid,
output out_class_key_almostfull,
input in_ingress_pkt_wr,
input [133:0] in_ingress_pkt,
input in_ingress_valid_wr,
input in_ingress_valid,
output out_ingress_pkt_almostfull,
output reg out_dispather_pkt_wr,
output reg [133:0] out_dispather_pkt,
output reg out_dispather_valid_wr,
output reg out_dispather_valid,
input in_dispather_pkt_almostfull
);
wire in_ingress_valid_q;
wire in_ingress_valid_empty;
reg out_ingress_valid_rd;
wire [7:0] out_ingress_pkt_usedw;
wire out_ingress_pkt_empty;
assign out_ingress_pkt_almostfull = out_ingress_pkt_usedw[7];//lxj0107
reg out_ingress_pkt_rd;
wire [133:0]in_ingress_pkt_q;
wire in_class_valid_q;
wire in_class_valid_empty;
reg out_class_valid_rd;
wire [7:0] out_class_key_usedw;
wire out_class_key_empty;
assign out_class_key_almostfull = out_class_key_usedw[7];//lxj0107
reg out_class_key_rd;
wire [133:0]in_class_key_q;
reg [15:0] shift_reg;//register offset 2 byte from pkt
reg [6:0] align_count;//num of pkt's cycle after offset and prepad
reg [4:0] current_state;
parameter idle_s = 5'd0,
metadata1_s = 5'd1,
metadata2_s = 5'd2,
wait_s = 5'd3,
front_pad_s = 5'd4,
shift_s = 5'd5,
align_pad_s = 5'd6;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_dispather_pkt_wr<=1'b0;
out_dispather_pkt<=134'b0;
out_dispather_valid_wr<=1'b0;
out_dispather_valid<=1'b0;
out_ingress_valid_rd<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_class_valid_rd<=1'b0;
out_class_key_rd<=1'b0;
align_count<=7'b0;
shift_reg<=16'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin//wait for pkt from INGRESS CTRL Moudle
out_dispather_pkt_wr<=1'b0;
out_dispather_valid_wr<=1'b0;
out_dispather_valid<=1'b0;
out_class_valid_rd<=1'b0;
out_class_key_rd<=1'b0;
shift_reg<=16'b0;
align_count<=7'b0;
if((in_ingress_valid_empty==1'b0) &&(in_dispather_pkt_almostfull==1'b0))begin//have a complete pkt receive from INGRESS_CTRL Module
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= metadata1_s;
end
else begin
out_ingress_valid_rd<=1'b0;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
end
metadata1_s: begin//process the first cycle metadata --->add length of pkt
out_ingress_valid_rd<=1'b0;
out_dispather_pkt_wr<=1'b1;
out_dispather_pkt[133:124]<=in_ingress_pkt_q[133:124];
out_dispather_pkt[123:113]<=in_ingress_pkt_q[123:113]+11'd66;//64byte prepad +2 byte offset
out_dispather_pkt[112:0]<=in_ingress_pkt_q[112:0];
current_state <= metadata2_s;
end
metadata2_s: begin//process the first cycle metadata and wait for prepad pkt from CLASSIFY Module
if(out_dispather_pkt[118:113]==6'b0) begin//count sum of cycle of pkt by it's 64bytes block
align_count[6:2]<=out_dispather_pkt[123:119]-5'd2;//-1 64byte prepad block -1 metadata block (2 cycle metadata)
end
else begin
align_count[6:2]<=out_dispather_pkt[123:119]-5'd1;//+1 last block (need to be pad) -1 64byte prepad block -1 metadata block (2 cycle metadata)
end
align_count[1:0]<=2'd2;
out_ingress_pkt_rd<=1'b0;
out_dispather_pkt[133:0]<=in_ingress_pkt_q[133:0];
if(in_class_valid_empty==1'b0) begin//have a complete pkt receive from CLASSIFY Module
out_class_key_rd<=1'b1;
out_class_valid_rd<=1'b1;
current_state <= front_pad_s;
end
else begin
out_class_valid_rd<=1'b0;
out_class_key_rd<=1'b0;
current_state <= wait_s;
end
end
wait_s: begin//wait for pkt from CLASSIFY Moudle
out_dispather_pkt_wr<=1'b0;
if(in_class_valid_empty==1'b0) begin
out_class_key_rd<=1'b1;
out_class_valid_rd<=1'b1;
current_state <= front_pad_s;
end
else begin
out_class_valid_rd<=1'b0;
out_class_key_rd<=1'b0;
current_state <= wait_s;
end
end
front_pad_s: begin//get 4 cycle prepad from CLASSIFY Module
out_dispather_pkt_wr<=1'b1;
out_dispather_pkt[133:132]<=2'b11;
out_dispather_pkt[131:0]<=in_class_key_q[131:0];
out_class_valid_rd<=1'b0;
if(in_class_key_q[133:132]==2'b10) begin
out_ingress_pkt_rd<=1'b1;
out_class_key_rd<=1'b0;
current_state <= shift_s;
end
else begin
out_ingress_pkt_rd<=1'b0;
out_class_key_rd<=1'b1;
current_state <= front_pad_s;
end
end
shift_s: begin//OFFSET 2 byte in pkt body
out_dispather_pkt[127:112]<=shift_reg[15:0];
out_dispather_pkt[111:0]<=in_ingress_pkt_q[127:16];
shift_reg[15:0]<=in_ingress_pkt_q[15:0];
align_count<=align_count-7'd1;
if(in_ingress_pkt_q[133:132]==2'b10) begin
out_ingress_pkt_rd<=1'b0;
if(align_count==7'd1) begin
out_dispather_valid_wr<=1'b1;
out_dispather_valid<=1'b1;
out_dispather_pkt[133:128]<=6'b100000;
current_state <= idle_s;
end
else begin
out_dispather_valid_wr<=1'b0;
out_dispather_valid<=1'b0;
out_dispather_pkt[133:128]<=6'b110000;
current_state <= align_pad_s;
end
end
else begin
out_ingress_pkt_rd<=1'b1;
current_state <= shift_s;
end
end
align_pad_s: begin//64 byte align pad of pkt
out_dispather_pkt[127:112]<=shift_reg[15:0];
if(align_count>7'd1) begin
align_count<=align_count-7'd1;
out_dispather_valid_wr<=1'b0;
out_dispather_valid<=1'b0;
out_dispather_pkt[133:128]<=6'b110000;
current_state <= align_pad_s;
end
else begin
out_dispather_valid_wr<=1'b1;
out_dispather_valid<=1'b1;
out_dispather_pkt[133:128]<=6'b100000;
current_state <= idle_s;
end
end
default: begin
out_dispather_pkt_wr<=1'b0;
out_dispather_pkt<=134'b0;
out_dispather_valid_wr<=1'b0;
out_dispather_valid<=1'b0;
out_ingress_valid_rd<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_class_valid_rd<=1'b0;
out_class_key_rd<=1'b0;
current_state <= idle_s;
end
endcase
end
end
//--------------------------------From INGRESS CTRL Module-------------------------
fifo_64_1 FIFO_VALID_INGRESS (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_PKT_INGRESS (
.aclr(!reset),
.data(in_ingress_pkt),
.clock(clk),
.rdreq(out_ingress_pkt_rd),
.wrreq(in_ingress_pkt_wr),
.q(in_ingress_pkt_q),
.usedw(out_ingress_pkt_usedw),
.empty(out_ingress_pkt_empty)
);
//--------------------------------From CLASS Module-------------------------
fifo_64_1 FIFO_VALID_CLASS (
.aclr(!reset),
.data(in_class_valid),
.clock(clk),
.rdreq(out_class_valid_rd),
.wrreq(in_class_valid_wr),
.q(in_class_valid_q),
.empty(in_class_valid_empty)
);
fifo_256_134 FIFO_PKT_CLASS (
.aclr(!reset),
.data(in_class_key),
.clock(clk),
.rdreq(out_class_key_rd),
.wrreq(in_class_key_wr),
.q(in_class_key_q),
.usedw(out_class_key_usedw),
.empty(out_class_key_empty)
);
endmodule |
module INGRESS_CTRL(
input clk,
input reset,
input in_inputctrl_pkt_wr,// the packet write request of input_ctrl moudle to inputctrl module
input [133:0] in_inputctrl_pkt,// the packet of input_ctrl moudle to inputctrl module
input in_inputctrl_valid_wr,//the valid flag write request of input_ctrl moudle to inputctrl module
input in_inputctrl_valid,// the valid flag of input_ctrl moudle to inputctrl module
output out_inputctrl_pkt_almostfull,
output reg out_class_key_wr,// the packet write request of input_ctrl moudle to classification module
output reg [133:0] out_class_key,// the packet of input_ctrl moudle to classification module
input in_class_key_almostfull,
output reg out_class_valid,// the valid flag of input_ctrl moudle to classification module
output reg out_class_valid_wr,//the valid flag write request of input_ctrl moudle to classification module
output reg out_offset_pkt_wr,// the packet write request of input_ctrl moudle to offset module
output reg [133:0] out_offset_pkt,// the packet of input_ctrl moudle to offset module
output reg out_offset_valid,// the valid flag of input_ctrl moudle to offset module
output reg out_offset_valid_wr,//the valid flag write request of iinput_ctrl moudle to offset module
input in_offset_pkt_almostfull
);
reg [2:0] current_state;
reg [2:0] counter;
wire in_inputctrl_valid_q;
wire in_inputctrl_valid_empty;
reg out_inputctrl_valid_rd;
wire [7:0] out_inputctrl_pkt_usedw;
assign out_inputctrl_pkt_almostfull = out_inputctrl_pkt_usedw[7];
reg out_inputctrl_pkt_rd;
wire [133:0]in_inputctrl_pkt_q;
parameter idle_s = 3'd0,
send_meta1_s = 3'd1,
send_meta2_s = 3'd2,
send_key_s = 3'd3,
send_data_s = 3'd4,
discard_s=3'd5;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_class_key_wr<=1'b0;
out_class_key<=134'b0;
out_class_valid<=1'b1;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_pkt<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
counter<=3'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s:begin
counter<=3'b0;
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if((in_offset_pkt_almostfull==1'b0) && (in_inputctrl_valid_empty==1'b0) && (in_class_key_almostfull==1'b0))begin
if(in_inputctrl_valid_q==1'b1)begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=send_meta1_s;
end
else begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
else begin
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
send_meta1_s:begin//forward to first pat metadata
out_inputctrl_valid_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_meta2_s;
end
send_meta2_s:begin//forward to second pat metadata
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_key_s;
end
send_key_s:begin//forward to first pat packet
out_offset_pkt_wr<=1'b1;
out_class_key_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_class_key<=in_inputctrl_pkt_q;
counter<=counter+1'b1;//the number of forward to packet
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
out_class_valid_wr<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if(counter<3'd3)begin //four packets forward to inputctrl
out_class_valid_wr<=1'b0;
current_state<=send_key_s;
end
else begin
out_class_valid_wr<=1'b1;
current_state<=send_data_s;
end
end
end
send_data_s:begin//forward other packets to offset module
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_data_s;
end
end
discard_s:begin
out_inputctrl_valid_rd<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
default:;
endcase
end
end
fifo_64_1 FIFO_VALID_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_valid),
.clock(clk),
.rdreq(out_inputctrl_valid_rd),
.wrreq(in_inputctrl_valid_wr),
.q(in_inputctrl_valid_q),
.empty(in_inputctrl_valid_empty)
);
fifo_256_134 FIFO_PKT_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_pkt),
.clock(clk),
.rdreq(out_inputctrl_pkt_rd),
.wrreq(in_inputctrl_pkt_wr),
.q(in_inputctrl_pkt_q),
.usedw(out_inputctrl_pkt_usedw)
);
endmodule |
module DISPATHER_OUTPUT(
input clk,
input reset,
input in_input_pkt_wr,// the packet write request of input moudle to dispather_output module
input [133:0] in_input_pkt,//// the packet of input moudle to dispather_output module
input in_input_valid_wr,//the valid flag write request of input moudle to dispather_output module
input in_input_valid,//// the valid flag of input moudle to dispather_output module
output out_input_pkt_almostfull,
input in_ppc_pkt_wr,//the packet write request of ppc moudle to dispather_output module
input [133:0] in_ppc_pkt,// the packet of ppc moudle to dispather_output module
input in_ppc_valid_wr,//the valid flag write request of ppc moudle to dispather_output module
input in_ppc_valid,// the valid flag of ppc moudle to dispather_output module
output out_ppc_pkt_almostfull,
output reg out_rdma_pkt_wr,//the packet write request of dispather_output moudle to rdma module
output reg [133:0] out_rdma_pkt,// the packet of dispather_output moudle to rdma module
output reg out_rdma_valid_wr,//the valid flag write request of dispather_output moudle to rdma module
output reg out_rdma_valid,//the valid flag of dispather_output moudle to rdma module
input in_rdma_pkt_almostfull
);
wire in_input_valid_q;
wire in_input_valid_empty;
reg out_input_valid_rd;
wire [7:0] out_input_pkt_usedw;
assign out_input_pkt_almostfull = out_input_pkt_usedw[7];
reg out_input_pkt_rd;
wire [133:0]in_input_pkt_q;
wire in_ppc_valid_q;
wire in_ppc_valid_empty;
reg out_ppc_valid_rd;
wire out_ppc_pkt_empty;
wire [7:0] out_ppc_pkt_usedw;
assign out_ppc_pkt_almostfull = out_ppc_pkt_usedw[7];
reg out_ppc_pkt_rd;
wire [133:0]in_ppc_pkt_q;
reg ppc_input;//1:input 0:ppc
reg [2:0] current_state;
parameter idle_s = 3'd0,
send_ppc_s = 3'd1,
send_input_s = 3'd2,
discard_input_s=3'd3,
discard_ppc_s=3'd4;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_pkt<= 134'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
ppc_input<=1'b0;
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s: begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
if(in_rdma_pkt_almostfull==1'b0) begin
case({in_input_valid_empty,in_ppc_valid_empty})
2'b00: begin//both PPC and INPUT have pkt
if(ppc_input==1'b0) begin//get pkt from PPC Module
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b1;
out_ppc_pkt_rd<=1'b1;
current_state<=send_ppc_s;
end
else begin
out_input_valid_rd<=1'b1;
out_input_pkt_rd<=1'b1;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=send_input_s;
end
end
2'b01: begin//only INPUT has pkt
out_input_valid_rd<=1'b1;
out_input_pkt_rd<=1'b1;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=send_input_s;
end
2'b10: begin//only ppc has pkt
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b1;
out_ppc_pkt_rd<=1'b1;
current_state<=send_ppc_s;
end
default: begin
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
endcase
end
else begin
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
send_input_s:begin
out_input_valid_rd<=1'b0;
out_rdma_pkt_wr<=1'b1;
out_rdma_pkt<=in_input_pkt_q;
ppc_input<=1'b0;//get pkt from PPC��Module next time
if(in_input_pkt_q[133:132]==2'b10) begin
out_input_pkt_rd<=1'b0;
out_rdma_valid_wr<=1'b1;
out_rdma_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_input_pkt_rd<=1'b1;
out_rdma_valid_wr<=1'b0;
current_state<=send_input_s;
end
end
send_ppc_s:begin
out_ppc_valid_rd<=1'b0;
out_rdma_pkt_wr<=1'b1;
out_rdma_pkt<=in_ppc_pkt_q;
ppc_input<=1'b1;//get pkt from INPUT��Module next time
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_ppc_pkt_rd<=1'b0;
out_rdma_valid_wr<=1'b1;
current_state<=idle_s;
end
else begin
out_ppc_pkt_rd<=1'b1;
out_rdma_valid_wr<=1'b0;
current_state<=send_ppc_s;
end
end
discard_input_s:begin
out_input_valid_rd<=1'b0;
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_input_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_input_pkt_rd<=1'b1;
current_state<=discard_input_s;
end
end
discard_ppc_s:begin
out_ppc_valid_rd<=1'b0;
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_ppc_valid_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_ppc_pkt_rd<=1'b1;
current_state<=discard_ppc_s;
end
end
default: begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
endcase
end
end
//--------------------------------From INPUT Module-------------------------
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_input_valid),
.clock(clk),
.rdreq(out_input_valid_rd),
.wrreq(in_input_valid_wr),
.q(in_input_valid_q),
.empty(in_input_valid_empty)
);
fifo_256_134 FIFO_PKT_input (
.aclr(!reset),
.data(in_input_pkt),
.clock(clk),
.rdreq(out_input_pkt_rd),
.wrreq(in_input_pkt_wr),
.q(in_input_pkt_q),
.usedw(out_input_pkt_usedw)
);
//--------------------------------From PPC Module-------------------------
fifo_64_1 FIFO_VALID_PPC (
.aclr(!reset),
.data(in_ppc_valid),
.clock(clk),
.rdreq(out_ppc_valid_rd),
.wrreq(in_ppc_valid_wr),
.q(in_ppc_valid_q),
.empty(in_ppc_valid_empty)
);
fifo_256_134 FIFO_PKT_PPC (
.aclr(!reset),
.data(in_ppc_pkt),
.clock(clk),
.rdreq(out_ppc_pkt_rd),
.wrreq(in_ppc_pkt_wr),
.q(in_ppc_pkt_q),
.usedw(out_ppc_pkt_usedw),
.empty(out_ppc_pkt_empty)
);
endmodule |
module DISPATHER_CPUID(
input clk,
input reset,
input in_fpgaac_cpuid_cs,
input [5:0] in_fpgaac_channel_num,
input [31:0] cpuid_valid,
input [4:0] in_input_key,
input in_input_ctl,
output reg out_input_ack,
output reg out_input_valid,
output reg [4:0] out_input_cpuid
);
reg current_cpuid_valid;
reg [4:0] cpuid_reg;
reg [2:0] current_state;
parameter idle_s = 3'd0,
match_s = 3'd1,
judge_s = 3'd2,
wait_s = 3'd3;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_input_ack<=1'b0;
out_input_valid<=1'b0;
out_input_cpuid<=5'd0;
cpuid_reg<=5'd0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin//wait for the req signal(in_input_ctl) from Input module
out_input_ack<=1'b0;
out_input_valid<=1'b0;
current_cpuid_valid<=1'b0;
if(in_input_ctl==1'b0) begin//Input module have not req for cpuid
current_state <= idle_s;
end
else begin//
if(in_fpgaac_cpuid_cs==1'b0) begin//round robin mode
out_input_cpuid<=cpuid_reg;
end
else begin//port bind mode
out_input_cpuid<=in_input_key;
end
current_state <= match_s;
end
end
match_s: begin
case(out_input_cpuid)
5'd0: current_cpuid_valid <= cpuid_valid[0];
5'd1: current_cpuid_valid <= cpuid_valid[1];
5'd2: current_cpuid_valid <= cpuid_valid[2];
5'd3: current_cpuid_valid <= cpuid_valid[3];
5'd4: current_cpuid_valid <= cpuid_valid[4];
5'd5: current_cpuid_valid <= cpuid_valid[5];
5'd6: current_cpuid_valid <= cpuid_valid[6];
5'd7: current_cpuid_valid <= cpuid_valid[7];
5'd8: current_cpuid_valid <= cpuid_valid[8];
5'd9: current_cpuid_valid <= cpuid_valid[9];
5'd10: current_cpuid_valid <= cpuid_valid[10];
5'd11: current_cpuid_valid <= cpuid_valid[11];
5'd12: current_cpuid_valid <= cpuid_valid[12];
5'd13: current_cpuid_valid <= cpuid_valid[13];
5'd14: current_cpuid_valid <= cpuid_valid[14];
5'd15: current_cpuid_valid <= cpuid_valid[15];
5'd16: current_cpuid_valid <= cpuid_valid[16];
5'd17: current_cpuid_valid <= cpuid_valid[17];
5'd18: current_cpuid_valid <= cpuid_valid[18];
5'd19: current_cpuid_valid <= cpuid_valid[19];
5'd20: current_cpuid_valid <= cpuid_valid[20];
5'd21: current_cpuid_valid <= cpuid_valid[21];
5'd22: current_cpuid_valid <= cpuid_valid[22];
5'd23: current_cpuid_valid <= cpuid_valid[23];
5'd24: current_cpuid_valid <= cpuid_valid[24];
5'd25: current_cpuid_valid <= cpuid_valid[25];
5'd26: current_cpuid_valid <= cpuid_valid[26];
5'd27: current_cpuid_valid <= cpuid_valid[27];
5'd28: current_cpuid_valid <= cpuid_valid[28];
5'd29: current_cpuid_valid <= cpuid_valid[29];
5'd30: current_cpuid_valid <= cpuid_valid[30];
5'd31: current_cpuid_valid <= cpuid_valid[31];
endcase
current_state <= judge_s;
end
judge_s: begin
if(in_fpgaac_cpuid_cs==1'b0) begin//round robin mode
if(cpuid_reg<in_fpgaac_channel_num-6'd1) begin//cpuid start from 0,and the num guide by software start from 1
cpuid_reg<=cpuid_reg+5'd1;//round robin mode
end
else begin//cpuid can't > the num guide by software
cpuid_reg<=5'd0;
end
if(current_cpuid_valid==1'b0) begin
out_input_ack<=1'b0;
out_input_valid<=1'b0;
current_state <= idle_s;
end
else begin
out_input_ack<=1'b1;//cpuid is valid,Input module can get it
out_input_valid<=1'b1;
current_state <= wait_s;
end
end
else begin//port bind mode
out_input_ack<=1'b1;//cpuid is valid,Input module can get it
if(current_cpuid_valid==1'b0) begin
out_input_valid<=1'b0;
end
else begin
out_input_valid<=1'b1;
end
current_state <= wait_s;
end
end
wait_s: begin//wait for req signal invalid after allocated cpuid
if(in_input_ctl==1'b1) begin
out_input_ack<=1'b1;
current_state <= wait_s;
end
else begin
out_input_ack<=1'b0;//cpuid is invalid
current_state <= idle_s;
end
end
default: begin
out_input_ack<=1'b0;
out_input_cpuid<=5'b0;
cpuid_reg<=5'b0;
current_state <= idle_s;
end
endcase
end
end
endmodule |
module DISPATHER(
input clk,
input reset,
input in_ingress_pkt_wr,
input [133:0] in_ingress_pkt,
input in_ingress_valid_wr,
input in_ingress_valid,
output out_ingress_pkt_almostfull,
output out_rdma_pkt_wr,
output [133:0] out_rdma_pkt,
output out_rdma_valid_wr,
output out_rdma_valid,
input in_rdma_pkt_almostfull,
input [5:0] in_fpgaac_channel_num,
input in_fpgaac_cpuid_cs,//switch cpuid allocate mode 0:round robin 1:port bind
input [31:0] cpuid_valid,
input in_ppc_pkt_wr,
input [133:0] in_ppc_pkt,
input in_ppc_valid_wr,
input in_ppc_valid,
output out_ppc_pkt_almostfull,
output out_ppc_pkt_wr,
output [133:0] out_ppc_pkt,
output out_ppc_valid_wr,
output out_ppc_valid,
input in_ppc_pkt_almostfull
);
wire [4:0] in_cpuid;//id of cpu thread which pkt would be send to
wire in_cpuid_ack;
wire in_cpuid_valid;
wire out_cpuid_ctl;
wire [4:0] out_cpuid_key;
wire in_input_pkt_wr;
wire [133:0] in_input_pkt;
wire in_input_valid_wr;
wire in_input_valid;
wire out_input_pkt_almostfull;
DISPATHER_INPUT DISPATHER_INPUT (
.clk(clk),
.reset(reset),
.in_cpuid(in_cpuid),//id of cpu thread which pkt would be send to
.in_cpuid_ack(in_cpuid_ack),
.in_cpuid_valid(in_cpuid_valid),
.out_cpuid_ctl(out_cpuid_ctl),
.out_cpuid_key(out_cpuid_key),
.in_ingress_pkt_wr(in_ingress_pkt_wr),
.in_ingress_pkt(in_ingress_pkt),
.in_ingress_valid_wr(in_ingress_valid_wr),
.in_ingress_valid(in_ingress_valid),
.out_ingress_pkt_almostfull(out_ingress_pkt_almostfull),
.out_output_pkt_wr(in_input_pkt_wr),
.out_output_pkt(in_input_pkt),
.out_output_valid_wr(in_input_valid_wr),
.out_output_valid(in_input_valid),
.in_output_pkt_almostfull(out_input_pkt_almostfull),
.out_ppc_pkt_wr(out_ppc_pkt_wr),
.out_ppc_pkt(out_ppc_pkt),
.out_ppc_valid_wr(out_ppc_valid_wr),
.out_ppc_valid(out_ppc_valid),
.in_ppc_pkt_almostfull(in_ppc_pkt_almostfull)
);
DISPATHER_CPUID DISPATHER_CPUID (//round robin mode & port bind mode
.clk(clk),
.reset(reset),
.in_fpgaac_cpuid_cs(in_fpgaac_cpuid_cs),
.in_fpgaac_channel_num(in_fpgaac_channel_num),
.cpuid_valid(cpuid_valid),
.out_input_cpuid(in_cpuid),//id of cpu thread which pkt would be send to
.out_input_ack(in_cpuid_ack),
.out_input_valid(in_cpuid_valid),
.in_input_ctl(out_cpuid_ctl),
.in_input_key(out_cpuid_key)
);
DISPATHER_OUTPUT DISPATHER_OUTPUT(
.clk(clk),
.reset(reset),
.in_input_pkt_wr(in_input_pkt_wr),
.in_input_pkt(in_input_pkt),
.in_input_valid_wr(in_input_valid_wr),
.in_input_valid(in_input_valid),
.out_input_pkt_almostfull(out_input_pkt_almostfull),
.in_ppc_pkt_wr(in_ppc_pkt_wr),
.in_ppc_pkt(in_ppc_pkt),
.in_ppc_valid_wr(in_ppc_valid_wr),
.in_ppc_valid(in_ppc_valid),
.out_ppc_pkt_almostfull(out_ppc_pkt_almostfull),
.out_rdma_pkt_wr(out_rdma_pkt_wr),
.out_rdma_pkt(out_rdma_pkt),
.out_rdma_valid_wr(out_rdma_valid_wr),
.out_rdma_valid(out_rdma_valid),
.in_rdma_pkt_almostfull(in_rdma_pkt_almostfull)
);
endmodule |
module DISPATHER_INPUT(
input clk,
input reset,
//--------------------------------CPUID Manage Module-------------------------
input [4:0] in_cpuid,//id of cpu thread which pkt would be send to
input in_cpuid_ack,
input in_cpuid_valid,
output reg out_cpuid_ctl,
output reg [4:0] out_cpuid_key,
//--------------------------------INGRESS Module<Data Input>-------------------------
input in_ingress_pkt_wr,
input [133:0] in_ingress_pkt,
input in_ingress_valid_wr,
input in_ingress_valid,
output out_ingress_pkt_almostfull,
//--------------------------------OUTPUT Module<Data Output Path 1>-------------------------
output reg out_output_pkt_wr,
output reg [133:0] out_output_pkt,
output reg out_output_valid_wr,
output reg out_output_valid,
input in_output_pkt_almostfull,
//--------------------------------PPC_SUBSYS Module<Data Output Path 2>-------------------------
output reg out_ppc_pkt_wr,
output reg [133:0] out_ppc_pkt,
output reg out_ppc_valid_wr,
output reg out_ppc_valid,
input in_ppc_pkt_almostfull
);
wire in_ingress_valid_q;
wire in_ingress_valid_empty;
reg out_ingress_valid_rd;
wire [7:0] out_ingress_pkt_usedw;
wire out_ingress_pkt_empty;
assign out_ingress_pkt_almostfull = out_ingress_pkt_usedw[7];//lxj0107
reg out_ingress_pkt_rd;
wire [133:0]in_ingress_pkt_q;
reg [2:0] current_state;
parameter idle_s = 3'd0,
wait_s = 3'd1,
send_output_s = 3'd2,
send_ppc_s = 3'd3,
discard_s = 3'd4;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_cpuid_ctl<=1'b0;
out_cpuid_key<=5'b0;
out_output_pkt_wr<=1'b0;
out_output_pkt<=134'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_pkt<=134'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_valid_rd<=1'b0;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
out_output_pkt_wr<=1'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
if((out_ingress_pkt_empty == 1'b0)&&(in_ingress_pkt_q[133:132]==2'b01)) begin
out_cpuid_ctl<=1'b1;
if(in_ingress_pkt_q[111:110]==2'b0)//slot_id
out_cpuid_key<=in_ingress_pkt_q[62:58];//inport
else
out_cpuid_key<=in_ingress_pkt_q[62:58]+5'd5;
current_state <= wait_s;
end
else begin
out_cpuid_ctl<=1'b0;
current_state <= idle_s;
end
end
wait_s: begin
out_cpuid_ctl<=1'b1;
if((in_cpuid_ack==1'b1) &&(in_ingress_valid_empty==1'b0)) begin
if((in_ingress_valid_q == 1'b1)&&(in_cpuid_valid==1'b1)) begin//pkt is valid && the sum of pkt which mount in it's cpuid have too more ,so discard this pkt
if((in_ingress_pkt_q[124]==1'b0)&&(in_output_pkt_almostfull==1'b0))begin//send to OUTPUT Module && OUTPUT Moudle can receive this pkt
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= send_output_s;
end
else if((in_ingress_pkt_q[124]==1'b1)&&(in_ppc_pkt_almostfull==1'b0)) begin //send to PPC Module && PPC Moudle can receive this pkt
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= send_ppc_s;
end
else begin
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
current_state <= wait_s;
end
end
else begin
out_ingress_pkt_rd<=1'b1;
out_ingress_valid_rd<=1'b1;
current_state <= discard_s;
end
end
else begin
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
current_state <= wait_s;
end
end
send_output_s: begin
out_cpuid_ctl<=1'b0;
out_ingress_valid_rd<=1'b0;
out_output_pkt_wr<=1'b1;
out_output_pkt<=in_ingress_pkt_q;
if(in_ingress_pkt_q[133:132]==2'b01) begin
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_output_pkt[55:47]<={4'b0,in_cpuid};
out_ingress_pkt_rd<=1'b1;
current_state <= send_output_s;
end
else if(in_ingress_pkt_q[133:132]==2'b10) begin
out_output_valid_wr<=1'b1;
out_output_valid<=1'b1;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ingress_pkt_rd<=1'b1;
current_state <= send_output_s;
end
end
send_ppc_s: begin
out_cpuid_ctl<=1'b0;
out_ingress_valid_rd<=1'b0;
out_output_pkt_wr<=1'b1;
out_ppc_pkt<=in_ingress_pkt_q;
if(in_ingress_pkt_q[133:132]==2'b01) begin
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ppc_pkt[55:47]<={4'b0,in_cpuid};
out_ingress_pkt_rd<=1'b1;
current_state <= send_ppc_s;
end
else if(in_ingress_pkt_q[133:132]==2'b10) begin
out_ppc_valid_wr<=1'b1;
out_ppc_valid<=1'b1;
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b1;
current_state <= send_ppc_s;
end
end
discard_s: begin
out_ingress_valid_rd<=1'b0;
if(in_ingress_pkt_q[133:132]==2'b10) begin
out_ingress_pkt_rd<=1'b0;
current_state <= idle_s;
end
else begin
out_ingress_pkt_rd<=1'b1;
current_state <= discard_s;
end
end
default: begin
out_output_pkt_wr<=1'b0;
out_output_valid_wr<=1'b0;
out_output_valid<=1'b0;
out_ppc_pkt_wr<=1'b0;
out_ppc_valid_wr<=1'b0;
out_ppc_valid<=1'b0;
out_ingress_pkt_rd<=1'b0;
out_ingress_valid_rd<=1'b0;
out_cpuid_ctl<=1'b0;
current_state <= idle_s;
end
endcase
end
end
//--------------------------------From INGRESS Module-------------------------
fifo_64_1 FIFO_VALID_INGRESS (
.aclr(!reset),
.data(in_ingress_valid),
.clock(clk),
.rdreq(out_ingress_valid_rd),
.wrreq(in_ingress_valid_wr),
.q(in_ingress_valid_q),
.empty(in_ingress_valid_empty)
);
fifo_256_134 FIFO_PKT_INGRESS (
.aclr(!reset),
.data(in_ingress_pkt),
.clock(clk),
.rdreq(out_ingress_pkt_rd),
.wrreq(in_ingress_pkt_wr),
.q(in_ingress_pkt_q),
.usedw(out_ingress_pkt_usedw),
.empty(out_ingress_pkt_empty)
);
endmodule |
module mac_core_0002 (
input wire clk, // control_port_clock_connection.clk
input wire reset, // reset_connection.reset
input wire [7:0] reg_addr, // control_port.address
output wire [31:0] reg_data_out, // .readdata
input wire reg_rd, // .read
input wire [31:0] reg_data_in, // .writedata
input wire reg_wr, // .write
output wire reg_busy, // .waitrequest
input wire tx_clk, // pcs_mac_tx_clock_connection.clk
input wire rx_clk, // pcs_mac_rx_clock_connection.clk
input wire set_10, // mac_status_connection.set_10
input wire set_1000, // .set_1000
output wire eth_mode, // .eth_mode
output wire ena_10, // .ena_10
input wire [7:0] gm_rx_d, // mac_gmii_connection.gmii_rx_d
input wire gm_rx_dv, // .gmii_rx_dv
input wire gm_rx_err, // .gmii_rx_err
output wire [7:0] gm_tx_d, // .gmii_tx_d
output wire gm_tx_en, // .gmii_tx_en
output wire gm_tx_err, // .gmii_tx_err
input wire [3:0] m_rx_d, // mac_mii_connection.mii_rx_d
input wire m_rx_en, // .mii_rx_dv
input wire m_rx_err, // .mii_rx_err
output wire [3:0] m_tx_d, // .mii_tx_d
output wire m_tx_en, // .mii_tx_en
output wire m_tx_err, // .mii_tx_err
input wire m_rx_crs, // .mii_crs
input wire m_rx_col, // .mii_col
input wire ff_rx_clk, // receive_clock_connection.clk
input wire ff_tx_clk, // transmit_clock_connection.clk
output wire [31:0] ff_rx_data, // receive.data
output wire ff_rx_eop, // .endofpacket
output wire [5:0] rx_err, // .error
output wire [1:0] ff_rx_mod, // .empty
input wire ff_rx_rdy, // .ready
output wire ff_rx_sop, // .startofpacket
output wire ff_rx_dval, // .valid
input wire [31:0] ff_tx_data, // transmit.data
input wire ff_tx_eop, // .endofpacket
input wire ff_tx_err, // .error
input wire [1:0] ff_tx_mod, // .empty
output wire ff_tx_rdy, // .ready
input wire ff_tx_sop, // .startofpacket
input wire ff_tx_wren, // .valid
output wire magic_wakeup, // mac_misc_connection.magic_wakeup
input wire magic_sleep_n, // .magic_sleep_n
input wire ff_tx_crc_fwd, // .ff_tx_crc_fwd
output wire ff_tx_septy, // .ff_tx_septy
output wire tx_ff_uflow, // .tx_ff_uflow
output wire ff_tx_a_full, // .ff_tx_a_full
output wire ff_tx_a_empty, // .ff_tx_a_empty
output wire [17:0] rx_err_stat, // .rx_err_stat
output wire [3:0] rx_frm_type, // .rx_frm_type
output wire ff_rx_dsav, // .ff_rx_dsav
output wire ff_rx_a_full, // .ff_rx_a_full
output wire ff_rx_a_empty // .ff_rx_a_empty
);
altera_eth_tse_mac #(
.ING_ADDR (11),
.ENABLE_MAC_RX_VLAN (0),
.ENABLE_SUP_ADDR (0),
.DEVICE_FAMILY ("STRATIXIV"),
.INSERT_TA (0),
.ING_FIFO (2048),
.ENABLE_ECC (0),
.CRC32DWIDTH (8),
.ENABLE_ENA (32),
.SYNCHRONIZER_DEPTH (4),
.ENABLE_MAC_TX_VLAN (0),
.RESET_LEVEL (1),
.STAT_CNT_ENA (1),
.CUST_VERSION (0),
.CRC32S1L2_EXTERN (0),
.MBIT_ONLY (1),
.EG_ADDR (11),
.CORE_VERSION (3584),
.CRC32GENDELAY (6),
.EG_FIFO (2048),
.REDUCED_INTERFACE_ENA (0),
.ENABLE_MAGIC_DETECT (1),
.ENABLE_MDIO (0),
.ENABLE_MAC_TXADDR_SET (1),
.RAM_TYPE ("AUTO"),
.CRC32CHECK16BIT (0),
.ENABLE_LGTH_CHECK (1),
.ENABLE_MAC_FLOW_CTRL (0),
.ENABLE_SHIFT16 (1),
.USE_SYNC_RESET (1),
.REDUCED_CONTROL (0),
.MDIO_CLK_DIV (40),
.ENABLE_PADDING (1),
.ENABLE_GMII_LOOPBACK (0),
.GBIT_ONLY (1),
.ENA_HASH (0),
.ENABLE_EXTENDED_STAT_REG (0),
.ENABLE_HD_LOGIC (1)
) i_tse_mac (
.clk (clk), // control_port_clock_connection.clk
.reset (reset), // reset_connection.reset
.reg_addr (reg_addr), // control_port.address
.reg_data_out (reg_data_out), // .readdata
.reg_rd (reg_rd), // .read
.reg_data_in (reg_data_in), // .writedata
.reg_wr (reg_wr), // .write
.reg_busy (reg_busy), // .waitrequest
.ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
.ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
.ff_rx_data (ff_rx_data), // receive.data
.ff_rx_eop (ff_rx_eop), // .endofpacket
.rx_err (rx_err), // .error
.ff_rx_mod (ff_rx_mod), // .empty
.ff_rx_rdy (ff_rx_rdy), // .ready
.ff_rx_sop (ff_rx_sop), // .startofpacket
.ff_rx_dval (ff_rx_dval), // .valid
.ff_tx_data (ff_tx_data), // transmit.data
.ff_tx_eop (ff_tx_eop), // .endofpacket
.ff_tx_err (ff_tx_err), // .error
.ff_tx_mod (ff_tx_mod), // .empty
.ff_tx_rdy (ff_tx_rdy), // .ready
.ff_tx_sop (ff_tx_sop), // .startofpacket
.ff_tx_wren (ff_tx_wren), // .valid
.magic_wakeup (magic_wakeup), // mac_misc_connection.export
.magic_sleep_n (magic_sleep_n), // .export
.ff_tx_crc_fwd (ff_tx_crc_fwd), // .export
.ff_tx_septy (ff_tx_septy), // .export
.tx_ff_uflow (tx_ff_uflow), // .export
.ff_tx_a_full (ff_tx_a_full), // .export
.ff_tx_a_empty (ff_tx_a_empty), // .export
.rx_err_stat (rx_err_stat), // .export
.rx_frm_type (rx_frm_type), // .export
.ff_rx_dsav (ff_rx_dsav), // .export
.ff_rx_a_full (ff_rx_a_full), // .export
.ff_rx_a_empty (ff_rx_a_empty), // .export
.gm_rx_d (gm_rx_d), // mac_gmii_connection.gmii_rx_d
.gm_rx_dv (gm_rx_dv), // .gmii_rx_dv
.gm_rx_err (gm_rx_err), // .gmii_rx_err
.gm_tx_d (gm_tx_d), // .gmii_tx_d
.gm_tx_en (gm_tx_en), // .gmii_tx_en
.gm_tx_err (gm_tx_err), // .gmii_tx_err
.m_rx_d (m_rx_d), // mac_mii_connection.mii_rx_d
.m_rx_en (m_rx_en), // .mii_rx_dv
.m_rx_err (m_rx_err), // .mii_rx_err
.m_tx_d (m_tx_d), // .mii_tx_d
.m_tx_en (m_tx_en), // .mii_tx_en
.m_tx_err (m_tx_err), // .mii_tx_err
.m_rx_crs (m_rx_crs), // .mii_crs
.m_rx_col (m_rx_col), // .mii_col
.set_10 (set_10), // mac_status_connection.set_10
.set_1000 (set_1000), // .set_1000
.eth_mode (eth_mode), // .eth_mode
.ena_10 (ena_10), // .ena_10
.tx_clk (tx_clk), // pcs_mac_tx_clock_connection.clk
.rx_clk (rx_clk), // pcs_mac_rx_clock_connection.clk
.rx_clkena (1'b1), // (terminated)
.tx_clkena (1'b1), // (terminated)
.xon_gen (1'b0), // (terminated)
.xoff_gen (1'b0), // (terminated)
.mac_eccstatus (), // (terminated)
.mdc (), // (terminated)
.mdio_in (1'b0), // (terminated)
.mdio_out (), // (terminated)
.mdio_oen (), // (terminated)
.rgmii_out1_aclr (), // (terminated)
.rgmii_out1_din (), // (terminated)
.rgmii_in1_dout (2'b00), // (terminated)
.rgmii_in1_ck (), // (terminated)
.rgmii_out4_din (), // (terminated)
.rgmii_out4_ck (), // (terminated)
.rgmii_in1_pad (), // (terminated)
.rgmii_out4_aclr (), // (terminated)
.rgmii_out1_pad (1'b0), // (terminated)
.rgmii_out1_ck (), // (terminated)
.rgmii_in4_dout (8'b00000000), // (terminated)
.rgmii_in4_pad (), // (terminated)
.rgmii_out4_pad (4'b0000), // (terminated)
.rgmii_in4_ck (), // (terminated)
.rgmii_in (4'b0000), // (terminated)
.rgmii_out (), // (terminated)
.rx_control (1'b0), // (terminated)
.tx_control () // (terminated)
);
endmodule |
module altera_tse_false_path_marker
#(
parameter MARKER_WIDTH = 1
)
(
input reset,
input clk,
input [MARKER_WIDTH - 1 : 0] data_in,
output [MARKER_WIDTH - 1 : 0] data_out
);
(* ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \" set_false_path -to [get_registers *altera_tse_false_path_marker:*|data_out_reg*]\"" *)
(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {MARKER_WIDTH{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule |
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
wire speed_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(speed), //INPUT
.dout(speed_reg));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed_reg)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed_reg)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule |
module altera_tse_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
// Please check the false paths setting in TSE SDC
(*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
reg altera_tse_reset_synchronizer_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
altera_tse_reset_synchronizer_chain_out <= 1'b1;
end
else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end
endgenerate
endmodule |
module altera_tse_false_path_marker
#(
parameter MARKER_WIDTH = 1
)
(
input reset,
input clk,
input [MARKER_WIDTH - 1 : 0] data_in,
output [MARKER_WIDTH - 1 : 0] data_out
);
(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
assign data_out = data_out_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data_out_reg <= {MARKER_WIDTH{1'b0}};
end
else
begin
data_out_reg <= data_in;
end
end
endmodule |
module altera_tse_fake_master(
// Clock and reset
input clk,
input reset,
// Avalon MM master interface
output [8:0] phy_mgmt_address,
output phy_mgmt_read,
input [31:0] phy_mgmt_readdata,
output phy_mgmt_write,
output reg [31:0] phy_mgmt_writedata,
input phy_mgmt_waitrequest,
// Serial data loopback control
input sd_loopback
);
//////////////////////////////////internal registers and paramaters//////////////////////////////////
reg [1:0] state;
reg [1:0] next_state;
reg sd_loopback_r1, sd_loopback_r2;
reg bit_event;
localparam IDLE = 2'b0 ;
localparam WRITE_DATA = 2'b1;
////////////////////to detect the toggled data from sd_loopback //////////
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sd_loopback_r1 <= 1'b0;
sd_loopback_r2 <= 1'b0;
end
else
begin
sd_loopback_r2 <= sd_loopback_r1;
sd_loopback_r1 <= sd_loopback;
end
end
// bit_event is the bit to remember there is an event happening at the sd_loopback
// and used to trigger IDLE -> WRITE_DATA state transition
// This bit is only cleared during WRITE_DATA -> IDLE transition and make sure that
// phy_mgmt_writedata[0] value is equal to sd_loopback data
// This is to ensure that our Avalon MM write transaction is always in sync with sd_loopback value
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bit_event <= 0;
end
else
begin
if ( sd_loopback_r1 != sd_loopback_r2)
begin
bit_event <= 1'b1;
end
else
begin
if (next_state == IDLE && state == WRITE_DATA && phy_mgmt_writedata[0] == sd_loopback)
begin
bit_event <= 1'b0;
end
end
end
end
// State machine
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= IDLE;
else
state <= next_state;
end
// next_state logic
always @ (*)
begin
case (state)
IDLE:
begin
if (bit_event)
next_state = WRITE_DATA;
else
next_state = IDLE;
end
WRITE_DATA:
begin
if (!phy_mgmt_waitrequest)
next_state = IDLE;
else
next_state = WRITE_DATA;
end
default : next_state = IDLE;
endcase
end
// Connection to PHYIP (Avalon MM master signals)
assign phy_mgmt_write = (state == WRITE_DATA)? 1'b1 : 1'b0;
assign phy_mgmt_read = 1'b0;
assign phy_mgmt_address = (state == WRITE_DATA) ? 9'h61 : 9'h0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
phy_mgmt_writedata <= 32'b0;
end
else
begin
if (state == IDLE && next_state == WRITE_DATA)
begin
phy_mgmt_writedata <= {31'b0, sd_loopback};
end
else if (state == WRITE_DATA && next_state == IDLE)
begin
phy_mgmt_writedata <= 32'b0;
end
end
end
endmodule |
module altera_wait_generate
//#(
//This code only works when wait_cycle =1, if need other case, you need to modify this code.
//please set wait_cycle default value as 1 to keep old design works.
// parameter wait_cycle =1
// )
(
input wire rst,
input wire clk,
input wire launch_signal,
output wire wait_req
);
reg launch_reg = 0;
reg wait_reg = 0;
always @ (posedge clk, posedge rst) begin
if(rst) launch_reg <= 1'b0;
else launch_reg <= launch_signal;
end
always @ (posedge clk, posedge rst) begin
if(rst) wait_reg <= 1'b0;
else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
end
// waitrequest should be asserted during reset - note that in the reconfig
// controller, reset is locally synchronized. If you are using this module
// outside the reconfig controller, you may want to ensure that the reset
// signal is synchronized to prevent glitches, as waitrequest is not
// necessarily a registered output.
wire reset_sync;
alt_xcvr_resync #(.INIT_VALUE (1)) rst_sync (.clk(clk),.reset(rst),.d(1'b0),.q(reset_sync));
assign wait_req = reset_sync | (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
endmodule |
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule |
module mac_sgmii_0002 (
input wire clk, // control_port_clock_connection.clk
input wire reset, // reset_connection.reset
output wire [31:0] reg_data_out, // control_port.readdata
input wire reg_rd, // .read
input wire [31:0] reg_data_in, // .writedata
input wire reg_wr, // .write
output wire reg_busy, // .waitrequest
input wire [7:0] reg_addr, // .address
input wire ff_rx_clk, // receive_clock_connection.clk
input wire ff_tx_clk, // transmit_clock_connection.clk
output wire [31:0] ff_rx_data, // receive.data
output wire ff_rx_eop, // .endofpacket
output wire [5:0] rx_err, // .error
output wire [1:0] ff_rx_mod, // .empty
input wire ff_rx_rdy, // .ready
output wire ff_rx_sop, // .startofpacket
output wire ff_rx_dval, // .valid
input wire [31:0] ff_tx_data, // transmit.data
input wire ff_tx_eop, // .endofpacket
input wire ff_tx_err, // .error
input wire [1:0] ff_tx_mod, // .empty
output wire ff_tx_rdy, // .ready
input wire ff_tx_sop, // .startofpacket
input wire ff_tx_wren, // .valid
input wire ff_tx_crc_fwd, // mac_misc_connection.ff_tx_crc_fwd
output wire ff_tx_septy, // .ff_tx_septy
output wire tx_ff_uflow, // .tx_ff_uflow
output wire ff_tx_a_full, // .ff_tx_a_full
output wire ff_tx_a_empty, // .ff_tx_a_empty
output wire [17:0] rx_err_stat, // .rx_err_stat
output wire [3:0] rx_frm_type, // .rx_frm_type
output wire ff_rx_dsav, // .ff_rx_dsav
output wire ff_rx_a_full, // .ff_rx_a_full
output wire ff_rx_a_empty, // .ff_rx_a_empty
input wire ref_clk, // pcs_ref_clk_clock_connection.clk
output wire led_crs, // status_led_connection.crs
output wire led_link, // .link
output wire led_panel_link, // .panel_link
output wire led_col, // .col
output wire led_an, // .an
output wire led_char_err, // .char_err
output wire led_disp_err, // .disp_err
output wire rx_recovclkout, // serdes_control_connection.rx_recovclkout
input wire [139:0] reconfig_togxb, // .reconfig_togxb
output wire [91:0] reconfig_fromgxb, // .reconfig_fromgxb
input wire rxp, // serial_connection.rxp
output wire txp // .txp
);
wire [31:0] avalon_arbiter_av_mac_master_0_readdata; // i_tse_mac:reg_data_out -> avalon_arbiter:mac_readdata_0
wire avalon_arbiter_av_mac_master_0_waitrequest; // i_tse_mac:reg_busy -> avalon_arbiter:mac_waitrequest_0
wire [7:0] avalon_arbiter_av_mac_master_0_address; // avalon_arbiter:mac_address_0 -> i_tse_mac:reg_addr
wire avalon_arbiter_av_mac_master_0_read; // avalon_arbiter:mac_read_0 -> i_tse_mac:reg_rd
wire [31:0] avalon_arbiter_av_mac_master_0_writedata; // avalon_arbiter:mac_writedata_0 -> i_tse_mac:reg_data_in
wire avalon_arbiter_av_mac_master_0_write; // avalon_arbiter:mac_write_0 -> i_tse_mac:reg_wr
wire i_tse_pcs_0_sd_loopback_export; // i_tse_pcs_0:sd_loopback -> i_phyip_terminator_0:sd_loopback
wire [0:0] i_custom_phyip_0_rx_clkout_export; // i_custom_phyip_0:rx_clkout -> i_tse_pcs_0:rx_pcs_clk
wire [0:0] i_custom_phyip_0_rx_disperr_export; // i_custom_phyip_0:rx_disperr -> i_tse_pcs_0:rx_disp_err
wire [0:0] i_custom_phyip_0_tx_clkout_export; // i_custom_phyip_0:tx_clkout -> i_tse_pcs_0:tx_pcs_clk
wire [0:0] i_custom_phyip_0_rx_runningdisp_export; // i_custom_phyip_0:rx_runningdisp -> i_tse_pcs_0:rx_runningdisp
wire [7:0] i_custom_phyip_0_rx_parallel_data_export; // i_custom_phyip_0:rx_parallel_data -> i_tse_pcs_0:rx_frame
wire [0:0] i_custom_phyip_0_rx_rlv_export; // i_custom_phyip_0:rx_rlv -> i_tse_pcs_0:rx_runlengthviolation
wire [0:0] i_custom_phyip_0_rx_errdetect_export; // i_custom_phyip_0:rx_errdetect -> i_tse_pcs_0:rx_char_err_gx
wire [7:0] i_tse_pcs_0_tx_frame_export; // i_tse_pcs_0:tx_frame -> i_custom_phyip_0:tx_parallel_data
wire [0:0] i_custom_phyip_0_rx_patterndetect_export; // i_custom_phyip_0:rx_patterndetect -> i_tse_pcs_0:rx_patterndetect
wire [0:0] i_custom_phyip_0_rx_datak_export; // i_custom_phyip_0:rx_datak -> i_tse_pcs_0:rx_kchar
wire [0:0] i_custom_phyip_0_rx_syncstatus_export; // i_custom_phyip_0:rx_syncstatus -> i_tse_pcs_0:rx_syncstatus
wire [4:0] i_custom_phyip_0_rx_bitslipboundaryselectout_export; // i_custom_phyip_0:rx_bitslipboundaryselectout -> i_tse_pcs_0:wa_boundary
wire i_tse_pcs_0_tx_kchar_export; // i_tse_pcs_0:tx_kchar -> i_custom_phyip_0:tx_datak
wire i_custom_phyip_0_tx_ready_export; // i_custom_phyip_0:tx_ready -> i_phyip_terminator_0:tx_ready
wire [0:0] i_custom_phyip_0_tx_serial_data_export; // i_custom_phyip_0:tx_serial_data -> i_phyip_terminator_0:tx_serial_data
wire [139:0] i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr; // i_phyip_terminator_0:reconfig_to_xcvr -> i_custom_phyip_0:reconfig_to_xcvr
wire [0:0] i_custom_phyip_0_pll_locked_export; // i_custom_phyip_0:pll_locked -> i_phyip_terminator_0:pll_locked
wire [91:0] i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr; // i_custom_phyip_0:reconfig_from_xcvr -> i_phyip_terminator_0:reconfig_from_xcvr
wire i_custom_phyip_0_rx_ready_export; // i_custom_phyip_0:rx_ready -> i_phyip_terminator_0:rx_ready
wire i_phyip_terminator_0_rx_serial_data_export; // i_phyip_terminator_0:rx_serial_data -> i_custom_phyip_0:rx_serial_data
wire [0:0] i_custom_phyip_0_rx_recovered_clk_export; // i_custom_phyip_0:rx_recovered_clk -> i_phyip_terminator_0:rx_recovered_clk
wire [31:0] i_phyip_terminator_0_av_dummy_master_readdata; // i_custom_phyip_0:phy_mgmt_readdata -> i_phyip_terminator_0:readdata
wire i_phyip_terminator_0_av_dummy_master_waitrequest; // i_custom_phyip_0:phy_mgmt_waitrequest -> i_phyip_terminator_0:waitrequest
wire [8:0] i_phyip_terminator_0_av_dummy_master_address; // i_phyip_terminator_0:address -> i_custom_phyip_0:phy_mgmt_address
wire i_phyip_terminator_0_av_dummy_master_read; // i_phyip_terminator_0:read -> i_custom_phyip_0:phy_mgmt_read
wire [31:0] i_phyip_terminator_0_av_dummy_master_writedata; // i_phyip_terminator_0:writedata -> i_custom_phyip_0:phy_mgmt_writedata
wire i_phyip_terminator_0_av_dummy_master_write; // i_phyip_terminator_0:write -> i_custom_phyip_0:phy_mgmt_write
wire [15:0] avalon_arbiter_av_pcs_master_0_readdata; // i_tse_pcs_0:reg_data_out -> avalon_arbiter:pcs_readdata_0
wire avalon_arbiter_av_pcs_master_0_waitrequest; // i_tse_pcs_0:reg_busy -> avalon_arbiter:pcs_waitrequest_0
wire [4:0] avalon_arbiter_av_pcs_master_0_address; // avalon_arbiter:pcs_address_0 -> i_tse_pcs_0:reg_addr
wire avalon_arbiter_av_pcs_master_0_read; // avalon_arbiter:pcs_read_0 -> i_tse_pcs_0:reg_rd
wire [15:0] avalon_arbiter_av_pcs_master_0_writedata; // avalon_arbiter:pcs_writedata_0 -> i_tse_pcs_0:reg_data_in
wire avalon_arbiter_av_pcs_master_0_write; // avalon_arbiter:pcs_write_0 -> i_tse_pcs_0:reg_wr
wire i_tse_pcs_0_pcs_transmit_clock_connection_clk; // i_tse_pcs_0:tx_clk -> [i_tse_mac:tx_clk, rst_controller:clk]
wire i_tse_pcs_0_pcs_receive_clock_connection_clk; // i_tse_pcs_0:rx_clk -> [i_tse_mac:rx_clk, rst_controller_001:clk]
wire [7:0] i_tse_pcs_0_gmii_connection_gmii_rx_d; // i_tse_pcs_0:gmii_rx_d -> i_tse_mac:gm_rx_d
wire i_tse_pcs_0_gmii_connection_gmii_rx_err; // i_tse_pcs_0:gmii_rx_err -> i_tse_mac:gm_rx_err
wire i_tse_pcs_0_gmii_connection_gmii_rx_dv; // i_tse_pcs_0:gmii_rx_dv -> i_tse_mac:gm_rx_dv
wire [7:0] i_tse_mac_mac_gmii_connection_gmii_tx_d; // i_tse_mac:gm_tx_d -> i_tse_pcs_0:gmii_tx_d
wire i_tse_mac_mac_gmii_connection_gmii_tx_en; // i_tse_mac:gm_tx_en -> i_tse_pcs_0:gmii_tx_en
wire i_tse_mac_mac_gmii_connection_gmii_tx_err; // i_tse_mac:gm_tx_err -> i_tse_pcs_0:gmii_tx_err
wire i_tse_mac_mac_mii_connection_mii_tx_en; // i_tse_mac:m_tx_en -> i_tse_pcs_0:mii_tx_en
wire [3:0] i_tse_pcs_0_mii_connection_mii_rx_d; // i_tse_pcs_0:mii_rx_d -> i_tse_mac:m_rx_d
wire i_tse_pcs_0_mii_connection_mii_col; // i_tse_pcs_0:mii_col -> i_tse_mac:m_rx_col
wire [3:0] i_tse_mac_mac_mii_connection_mii_tx_d; // i_tse_mac:m_tx_d -> i_tse_pcs_0:mii_tx_d
wire i_tse_mac_mac_mii_connection_mii_tx_err; // i_tse_mac:m_tx_err -> i_tse_pcs_0:mii_tx_err
wire i_tse_pcs_0_mii_connection_mii_crs; // i_tse_pcs_0:mii_crs -> i_tse_mac:m_rx_crs
wire i_tse_pcs_0_mii_connection_mii_rx_err; // i_tse_pcs_0:mii_rx_err -> i_tse_mac:m_rx_err
wire i_tse_pcs_0_mii_connection_mii_rx_dv; // i_tse_pcs_0:mii_rx_dv -> i_tse_mac:m_rx_en
wire i_tse_pcs_0_sgmii_status_connection_set_1000; // i_tse_pcs_0:set_1000 -> i_tse_mac:set_1000
wire i_tse_pcs_0_sgmii_status_connection_set_10; // i_tse_pcs_0:set_10 -> i_tse_mac:set_10
wire i_tse_pcs_0_clock_enable_connection_tx_clkena; // i_tse_pcs_0:tx_clkena -> i_tse_mac:tx_clkena
wire i_tse_pcs_0_clock_enable_connection_rx_clkena; // i_tse_pcs_0:rx_clkena -> i_tse_mac:rx_clkena
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> i_tse_pcs_0:reset_tx_clk
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> i_tse_pcs_0:reset_rx_clk
altera_eth_tse_mac #(
.ING_ADDR (9),
.ENABLE_MAC_RX_VLAN (0),
.ENABLE_SUP_ADDR (0),
.DEVICE_FAMILY ("STRATIXV"),
.INSERT_TA (0),
.ING_FIFO (512),
.ENABLE_ECC (0),
.CRC32DWIDTH (8),
.ENABLE_ENA (32),
.SYNCHRONIZER_DEPTH (3),
.ENABLE_MAC_TX_VLAN (0),
.RESET_LEVEL (1),
.STAT_CNT_ENA (1),
.CUST_VERSION (0),
.CRC32S1L2_EXTERN (0),
.MBIT_ONLY (1),
.EG_ADDR (9),
.CORE_VERSION (3840),
.CRC32GENDELAY (6),
.EG_FIFO (512),
.REDUCED_INTERFACE_ENA (0),
.ENABLE_MAGIC_DETECT (0),
.ENABLE_MDIO (0),
.ENABLE_MAC_TXADDR_SET (1),
.RAM_TYPE ("AUTO"),
.CRC32CHECK16BIT (0),
.ENABLE_LGTH_CHECK (1),
.ENABLE_MAC_FLOW_CTRL (0),
.ENABLE_SHIFT16 (0),
.USE_SYNC_RESET (1),
.REDUCED_CONTROL (0),
.MDIO_CLK_DIV (40),
.ENABLE_PADDING (1),
.ENABLE_GMII_LOOPBACK (0),
.GBIT_ONLY (1),
.ENA_HASH (0),
.ENABLE_EXTENDED_STAT_REG (1),
.ENABLE_HD_LOGIC (0)
) i_tse_mac (
.clk (clk), // control_port_clock_connection.clk
.reset (reset), // reset_connection.reset
.reg_addr (avalon_arbiter_av_mac_master_0_address), // control_port.address
.reg_data_out (avalon_arbiter_av_mac_master_0_readdata), // .readdata
.reg_rd (avalon_arbiter_av_mac_master_0_read), // .read
.reg_data_in (avalon_arbiter_av_mac_master_0_writedata), // .writedata
.reg_wr (avalon_arbiter_av_mac_master_0_write), // .write
.reg_busy (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
.ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
.ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
.ff_rx_data (ff_rx_data), // receive.data
.ff_rx_eop (ff_rx_eop), // .endofpacket
.rx_err (rx_err), // .error
.ff_rx_mod (ff_rx_mod), // .empty
.ff_rx_rdy (ff_rx_rdy), // .ready
.ff_rx_sop (ff_rx_sop), // .startofpacket
.ff_rx_dval (ff_rx_dval), // .valid
.ff_tx_data (ff_tx_data), // transmit.data
.ff_tx_eop (ff_tx_eop), // .endofpacket
.ff_tx_err (ff_tx_err), // .error
.ff_tx_mod (ff_tx_mod), // .empty
.ff_tx_rdy (ff_tx_rdy), // .ready
.ff_tx_sop (ff_tx_sop), // .startofpacket
.ff_tx_wren (ff_tx_wren), // .valid
.ff_tx_crc_fwd (ff_tx_crc_fwd), // mac_misc_connection.export
.ff_tx_septy (ff_tx_septy), // .export
.tx_ff_uflow (tx_ff_uflow), // .export
.ff_tx_a_full (ff_tx_a_full), // .export
.ff_tx_a_empty (ff_tx_a_empty), // .export
.rx_err_stat (rx_err_stat), // .export
.rx_frm_type (rx_frm_type), // .export
.ff_rx_dsav (ff_rx_dsav), // .export
.ff_rx_a_full (ff_rx_a_full), // .export
.ff_rx_a_empty (ff_rx_a_empty), // .export
.gm_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // mac_gmii_connection.gmii_rx_d
.gm_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // .gmii_rx_dv
.gm_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
.gm_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
.gm_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
.gm_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
.m_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // mac_mii_connection.mii_rx_d
.m_rx_en (i_tse_pcs_0_mii_connection_mii_rx_dv), // .mii_rx_dv
.m_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
.m_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
.m_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
.m_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
.m_rx_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
.m_rx_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
.set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // mac_status_connection.set_10
.set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
.rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // mac_clkena_connection.rx_clkena
.tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // .tx_clkena
.tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_mac_tx_clock_connection.clk
.rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_mac_rx_clock_connection.clk
.magic_sleep_n (1'b1), // (terminated)
.xon_gen (1'b0), // (terminated)
.xoff_gen (1'b0), // (terminated)
.magic_wakeup (), // (terminated)
.mac_eccstatus (), // (terminated)
.mdc (), // (terminated)
.mdio_in (1'b0), // (terminated)
.mdio_out (), // (terminated)
.mdio_oen (), // (terminated)
.rgmii_out1_aclr (), // (terminated)
.rgmii_out1_din (), // (terminated)
.rgmii_in1_dout (2'b00), // (terminated)
.rgmii_in1_ck (), // (terminated)
.rgmii_out4_din (), // (terminated)
.rgmii_out4_ck (), // (terminated)
.rgmii_in1_pad (), // (terminated)
.rgmii_out4_aclr (), // (terminated)
.rgmii_out1_pad (1'b0), // (terminated)
.rgmii_out1_ck (), // (terminated)
.rgmii_in4_dout (8'b00000000), // (terminated)
.rgmii_in4_pad (), // (terminated)
.rgmii_out4_pad (4'b0000), // (terminated)
.rgmii_in4_ck (), // (terminated)
.rgmii_in (4'b0000), // (terminated)
.rgmii_out (), // (terminated)
.rx_control (1'b0), // (terminated)
.tx_control (), // (terminated)
.eth_mode (), // (terminated)
.ena_10 () // (terminated)
);
altera_eth_tse_avalon_arbiter #(
.MAX_CHANNELS (1),
.MAC_ONLY (0),
.SLAVE_ADDR_WIDTH (8)
) avalon_arbiter (
.clk (clk), // clk.clk
.reset (reset), // reset.reset
.reg_data_out (reg_data_out), // av_slave.readdata
.reg_rd (reg_rd), // .read
.reg_data_in (reg_data_in), // .writedata
.reg_wr (reg_wr), // .write
.reg_busy (reg_busy), // .waitrequest
.reg_addr (reg_addr), // .address
.mac_address_0 (avalon_arbiter_av_mac_master_0_address), // av_mac_master_0.address
.mac_readdata_0 (avalon_arbiter_av_mac_master_0_readdata), // .readdata
.mac_read_0 (avalon_arbiter_av_mac_master_0_read), // .read
.mac_writedata_0 (avalon_arbiter_av_mac_master_0_writedata), // .writedata
.mac_write_0 (avalon_arbiter_av_mac_master_0_write), // .write
.mac_waitrequest_0 (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
.pcs_address_0 (avalon_arbiter_av_pcs_master_0_address), // av_pcs_master_0.address
.pcs_readdata_0 (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
.pcs_read_0 (avalon_arbiter_av_pcs_master_0_read), // .read
.pcs_writedata_0 (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
.pcs_write_0 (avalon_arbiter_av_pcs_master_0_write), // .write
.pcs_waitrequest_0 (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
.mac_address_1 (), // (terminated)
.mac_readdata_1 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_1 (), // (terminated)
.mac_writedata_1 (), // (terminated)
.mac_write_1 (), // (terminated)
.mac_waitrequest_1 (1'b0), // (terminated)
.pcs_address_1 (), // (terminated)
.pcs_readdata_1 (16'b0000000000000000), // (terminated)
.pcs_read_1 (), // (terminated)
.pcs_writedata_1 (), // (terminated)
.pcs_write_1 (), // (terminated)
.pcs_waitrequest_1 (1'b0), // (terminated)
.mac_address_2 (), // (terminated)
.mac_readdata_2 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_2 (), // (terminated)
.mac_writedata_2 (), // (terminated)
.mac_write_2 (), // (terminated)
.mac_waitrequest_2 (1'b0), // (terminated)
.pcs_address_2 (), // (terminated)
.pcs_readdata_2 (16'b0000000000000000), // (terminated)
.pcs_read_2 (), // (terminated)
.pcs_writedata_2 (), // (terminated)
.pcs_write_2 (), // (terminated)
.pcs_waitrequest_2 (1'b0), // (terminated)
.mac_address_3 (), // (terminated)
.mac_readdata_3 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_3 (), // (terminated)
.mac_writedata_3 (), // (terminated)
.mac_write_3 (), // (terminated)
.mac_waitrequest_3 (1'b0), // (terminated)
.pcs_address_3 (), // (terminated)
.pcs_readdata_3 (16'b0000000000000000), // (terminated)
.pcs_read_3 (), // (terminated)
.pcs_writedata_3 (), // (terminated)
.pcs_write_3 (), // (terminated)
.pcs_waitrequest_3 (1'b0), // (terminated)
.mac_address_4 (), // (terminated)
.mac_readdata_4 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_4 (), // (terminated)
.mac_writedata_4 (), // (terminated)
.mac_write_4 (), // (terminated)
.mac_waitrequest_4 (1'b0), // (terminated)
.pcs_address_4 (), // (terminated)
.pcs_readdata_4 (16'b0000000000000000), // (terminated)
.pcs_read_4 (), // (terminated)
.pcs_writedata_4 (), // (terminated)
.pcs_write_4 (), // (terminated)
.pcs_waitrequest_4 (1'b0), // (terminated)
.mac_address_5 (), // (terminated)
.mac_readdata_5 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_5 (), // (terminated)
.mac_writedata_5 (), // (terminated)
.mac_write_5 (), // (terminated)
.mac_waitrequest_5 (1'b0), // (terminated)
.pcs_address_5 (), // (terminated)
.pcs_readdata_5 (16'b0000000000000000), // (terminated)
.pcs_read_5 (), // (terminated)
.pcs_writedata_5 (), // (terminated)
.pcs_write_5 (), // (terminated)
.pcs_waitrequest_5 (1'b0), // (terminated)
.mac_address_6 (), // (terminated)
.mac_readdata_6 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_6 (), // (terminated)
.mac_writedata_6 (), // (terminated)
.mac_write_6 (), // (terminated)
.mac_waitrequest_6 (1'b0), // (terminated)
.pcs_address_6 (), // (terminated)
.pcs_readdata_6 (16'b0000000000000000), // (terminated)
.pcs_read_6 (), // (terminated)
.pcs_writedata_6 (), // (terminated)
.pcs_write_6 (), // (terminated)
.pcs_waitrequest_6 (1'b0), // (terminated)
.mac_address_7 (), // (terminated)
.mac_readdata_7 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_7 (), // (terminated)
.mac_writedata_7 (), // (terminated)
.mac_write_7 (), // (terminated)
.mac_waitrequest_7 (1'b0), // (terminated)
.pcs_address_7 (), // (terminated)
.pcs_readdata_7 (16'b0000000000000000), // (terminated)
.pcs_read_7 (), // (terminated)
.pcs_writedata_7 (), // (terminated)
.pcs_write_7 (), // (terminated)
.pcs_waitrequest_7 (1'b0), // (terminated)
.mac_address_8 (), // (terminated)
.mac_readdata_8 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_8 (), // (terminated)
.mac_writedata_8 (), // (terminated)
.mac_write_8 (), // (terminated)
.mac_waitrequest_8 (1'b0), // (terminated)
.pcs_address_8 (), // (terminated)
.pcs_readdata_8 (16'b0000000000000000), // (terminated)
.pcs_read_8 (), // (terminated)
.pcs_writedata_8 (), // (terminated)
.pcs_write_8 (), // (terminated)
.pcs_waitrequest_8 (1'b0), // (terminated)
.mac_address_9 (), // (terminated)
.mac_readdata_9 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_9 (), // (terminated)
.mac_writedata_9 (), // (terminated)
.mac_write_9 (), // (terminated)
.mac_waitrequest_9 (1'b0), // (terminated)
.pcs_address_9 (), // (terminated)
.pcs_readdata_9 (16'b0000000000000000), // (terminated)
.pcs_read_9 (), // (terminated)
.pcs_writedata_9 (), // (terminated)
.pcs_write_9 (), // (terminated)
.pcs_waitrequest_9 (1'b0), // (terminated)
.mac_address_10 (), // (terminated)
.mac_readdata_10 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_10 (), // (terminated)
.mac_writedata_10 (), // (terminated)
.mac_write_10 (), // (terminated)
.mac_waitrequest_10 (1'b0), // (terminated)
.pcs_address_10 (), // (terminated)
.pcs_readdata_10 (16'b0000000000000000), // (terminated)
.pcs_read_10 (), // (terminated)
.pcs_writedata_10 (), // (terminated)
.pcs_write_10 (), // (terminated)
.pcs_waitrequest_10 (1'b0), // (terminated)
.mac_address_11 (), // (terminated)
.mac_readdata_11 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_11 (), // (terminated)
.mac_writedata_11 (), // (terminated)
.mac_write_11 (), // (terminated)
.mac_waitrequest_11 (1'b0), // (terminated)
.pcs_address_11 (), // (terminated)
.pcs_readdata_11 (16'b0000000000000000), // (terminated)
.pcs_read_11 (), // (terminated)
.pcs_writedata_11 (), // (terminated)
.pcs_write_11 (), // (terminated)
.pcs_waitrequest_11 (1'b0), // (terminated)
.mac_address_12 (), // (terminated)
.mac_readdata_12 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_12 (), // (terminated)
.mac_writedata_12 (), // (terminated)
.mac_write_12 (), // (terminated)
.mac_waitrequest_12 (1'b0), // (terminated)
.pcs_address_12 (), // (terminated)
.pcs_readdata_12 (16'b0000000000000000), // (terminated)
.pcs_read_12 (), // (terminated)
.pcs_writedata_12 (), // (terminated)
.pcs_write_12 (), // (terminated)
.pcs_waitrequest_12 (1'b0), // (terminated)
.mac_address_13 (), // (terminated)
.mac_readdata_13 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_13 (), // (terminated)
.mac_writedata_13 (), // (terminated)
.mac_write_13 (), // (terminated)
.mac_waitrequest_13 (1'b0), // (terminated)
.pcs_address_13 (), // (terminated)
.pcs_readdata_13 (16'b0000000000000000), // (terminated)
.pcs_read_13 (), // (terminated)
.pcs_writedata_13 (), // (terminated)
.pcs_write_13 (), // (terminated)
.pcs_waitrequest_13 (1'b0), // (terminated)
.mac_address_14 (), // (terminated)
.mac_readdata_14 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_14 (), // (terminated)
.mac_writedata_14 (), // (terminated)
.mac_write_14 (), // (terminated)
.mac_waitrequest_14 (1'b0), // (terminated)
.pcs_address_14 (), // (terminated)
.pcs_readdata_14 (16'b0000000000000000), // (terminated)
.pcs_read_14 (), // (terminated)
.pcs_writedata_14 (), // (terminated)
.pcs_write_14 (), // (terminated)
.pcs_waitrequest_14 (1'b0), // (terminated)
.mac_address_15 (), // (terminated)
.mac_readdata_15 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_15 (), // (terminated)
.mac_writedata_15 (), // (terminated)
.mac_write_15 (), // (terminated)
.mac_waitrequest_15 (1'b0), // (terminated)
.pcs_address_15 (), // (terminated)
.pcs_readdata_15 (16'b0000000000000000), // (terminated)
.pcs_read_15 (), // (terminated)
.pcs_writedata_15 (), // (terminated)
.pcs_write_15 (), // (terminated)
.pcs_waitrequest_15 (1'b0), // (terminated)
.mac_address_16 (), // (terminated)
.mac_readdata_16 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_16 (), // (terminated)
.mac_writedata_16 (), // (terminated)
.mac_write_16 (), // (terminated)
.mac_waitrequest_16 (1'b0), // (terminated)
.pcs_address_16 (), // (terminated)
.pcs_readdata_16 (16'b0000000000000000), // (terminated)
.pcs_read_16 (), // (terminated)
.pcs_writedata_16 (), // (terminated)
.pcs_write_16 (), // (terminated)
.pcs_waitrequest_16 (1'b0), // (terminated)
.mac_address_17 (), // (terminated)
.mac_readdata_17 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_17 (), // (terminated)
.mac_writedata_17 (), // (terminated)
.mac_write_17 (), // (terminated)
.mac_waitrequest_17 (1'b0), // (terminated)
.pcs_address_17 (), // (terminated)
.pcs_readdata_17 (16'b0000000000000000), // (terminated)
.pcs_read_17 (), // (terminated)
.pcs_writedata_17 (), // (terminated)
.pcs_write_17 (), // (terminated)
.pcs_waitrequest_17 (1'b0), // (terminated)
.mac_address_18 (), // (terminated)
.mac_readdata_18 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_18 (), // (terminated)
.mac_writedata_18 (), // (terminated)
.mac_write_18 (), // (terminated)
.mac_waitrequest_18 (1'b0), // (terminated)
.pcs_address_18 (), // (terminated)
.pcs_readdata_18 (16'b0000000000000000), // (terminated)
.pcs_read_18 (), // (terminated)
.pcs_writedata_18 (), // (terminated)
.pcs_write_18 (), // (terminated)
.pcs_waitrequest_18 (1'b0), // (terminated)
.mac_address_19 (), // (terminated)
.mac_readdata_19 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_19 (), // (terminated)
.mac_writedata_19 (), // (terminated)
.mac_write_19 (), // (terminated)
.mac_waitrequest_19 (1'b0), // (terminated)
.pcs_address_19 (), // (terminated)
.pcs_readdata_19 (16'b0000000000000000), // (terminated)
.pcs_read_19 (), // (terminated)
.pcs_writedata_19 (), // (terminated)
.pcs_write_19 (), // (terminated)
.pcs_waitrequest_19 (1'b0), // (terminated)
.mac_address_20 (), // (terminated)
.mac_readdata_20 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_20 (), // (terminated)
.mac_writedata_20 (), // (terminated)
.mac_write_20 (), // (terminated)
.mac_waitrequest_20 (1'b0), // (terminated)
.pcs_address_20 (), // (terminated)
.pcs_readdata_20 (16'b0000000000000000), // (terminated)
.pcs_read_20 (), // (terminated)
.pcs_writedata_20 (), // (terminated)
.pcs_write_20 (), // (terminated)
.pcs_waitrequest_20 (1'b0), // (terminated)
.mac_address_21 (), // (terminated)
.mac_readdata_21 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_21 (), // (terminated)
.mac_writedata_21 (), // (terminated)
.mac_write_21 (), // (terminated)
.mac_waitrequest_21 (1'b0), // (terminated)
.pcs_address_21 (), // (terminated)
.pcs_readdata_21 (16'b0000000000000000), // (terminated)
.pcs_read_21 (), // (terminated)
.pcs_writedata_21 (), // (terminated)
.pcs_write_21 (), // (terminated)
.pcs_waitrequest_21 (1'b0), // (terminated)
.mac_address_22 (), // (terminated)
.mac_readdata_22 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_22 (), // (terminated)
.mac_writedata_22 (), // (terminated)
.mac_write_22 (), // (terminated)
.mac_waitrequest_22 (1'b0), // (terminated)
.pcs_address_22 (), // (terminated)
.pcs_readdata_22 (16'b0000000000000000), // (terminated)
.pcs_read_22 (), // (terminated)
.pcs_writedata_22 (), // (terminated)
.pcs_write_22 (), // (terminated)
.pcs_waitrequest_22 (1'b0), // (terminated)
.mac_address_23 (), // (terminated)
.mac_readdata_23 (32'b00000000000000000000000000000000), // (terminated)
.mac_read_23 (), // (terminated)
.mac_writedata_23 (), // (terminated)
.mac_write_23 (), // (terminated)
.mac_waitrequest_23 (1'b0), // (terminated)
.pcs_address_23 (), // (terminated)
.pcs_readdata_23 (16'b0000000000000000), // (terminated)
.pcs_read_23 (), // (terminated)
.pcs_writedata_23 (), // (terminated)
.pcs_write_23 (), // (terminated)
.pcs_waitrequest_23 (1'b0) // (terminated)
);
altera_eth_tse_pcs_pma_phyip #(
.ENABLE_TIMESTAMPING (0),
.DEV_VERSION (3840),
.ENABLE_ECC (0),
.DEVICE_FAMILY ("STRATIXV"),
.SYNCHRONIZER_DEPTH (3),
.ENABLE_CLK_SHARING (0),
.ENABLE_SGMII (1),
.PHY_IDENTIFIER (0)
) i_tse_pcs_0 (
.clk (clk), // control_port_clock_connection.clk
.reset (reset), // reset_connection.reset
.reg_addr (avalon_arbiter_av_pcs_master_0_address), // control_port.address
.reg_data_out (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
.reg_rd (avalon_arbiter_av_pcs_master_0_read), // .read
.reg_data_in (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
.reg_wr (avalon_arbiter_av_pcs_master_0_write), // .write
.reg_busy (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
.ref_clk (ref_clk), // pcs_ref_clk_clock_connection.clk
.rx_pcs_clk (i_custom_phyip_0_rx_clkout_export), // rx_pcs_clk.export
.sd_loopback (i_tse_pcs_0_sd_loopback_export), // sd_loopback.export
.rx_disp_err (i_custom_phyip_0_rx_disperr_export), // rx_disp_err.export
.tx_pcs_clk (i_custom_phyip_0_tx_clkout_export), // tx_pcs_clk.export
.rx_runningdisp (i_custom_phyip_0_rx_runningdisp_export), // rx_runningdisp.export
.rx_frame (i_custom_phyip_0_rx_parallel_data_export), // rx_frame.export
.rx_runlengthviolation (i_custom_phyip_0_rx_rlv_export), // rx_runlengthviolation.export
.rx_char_err_gx (i_custom_phyip_0_rx_errdetect_export), // rx_char_err_gx.export
.tx_frame (i_tse_pcs_0_tx_frame_export), // tx_frame.export
.rx_patterndetect (i_custom_phyip_0_rx_patterndetect_export), // rx_patterndetect.export
.rx_kchar (i_custom_phyip_0_rx_datak_export), // rx_kchar.export
.rx_syncstatus (i_custom_phyip_0_rx_syncstatus_export), // rx_syncstatus.export
.tx_kchar (i_tse_pcs_0_tx_kchar_export), // tx_kchar.export
.tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // clock_enable_connection.tx_clkena
.rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // .rx_clkena
.gmii_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // gmii_connection.gmii_rx_dv
.gmii_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // .gmii_rx_d
.gmii_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
.gmii_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
.gmii_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
.gmii_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
.mii_rx_dv (i_tse_pcs_0_mii_connection_mii_rx_dv), // mii_connection.mii_rx_dv
.mii_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // .mii_rx_d
.mii_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
.mii_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
.mii_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
.mii_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
.mii_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
.mii_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
.set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // sgmii_status_connection.set_10
.set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
.tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_transmit_clock_connection.clk
.rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_receive_clock_connection.clk
.reset_tx_clk (rst_controller_reset_out_reset), // pcs_transmit_reset_connection.reset
.reset_rx_clk (rst_controller_001_reset_out_reset), // pcs_receive_reset_connection.reset
.led_crs (led_crs), // status_led_connection.export
.led_link (led_link), // .export
.led_panel_link (led_panel_link), // .export
.led_col (led_col), // .export
.led_an (led_an), // .export
.led_char_err (led_char_err), // .export
.led_disp_err (led_disp_err), // .export
.wa_boundary (i_custom_phyip_0_rx_bitslipboundaryselectout_export), // wa_boundary.export
.rx_rmfifodatadeleted (1'b0), // (terminated)
.rx_rmfifodatainserted (1'b0), // (terminated)
.set_100 (), // (terminated)
.hd_ena (), // (terminated)
.pcs_phase_measure_clk (1'b0), // (terminated)
.rx_latency_adj (), // (terminated)
.tx_latency_adj (), // (terminated)
.tx_ptp_alignment (), // (terminated)
.pcs_eccstatus () // (terminated)
);
altera_xcvr_custom #(
.device_family ("Stratix V"),
.protocol_hint ("gige"),
.operation_mode ("Duplex"),
.lanes (1),
.bonded_group_size (1),
.bonded_mode ("xN"),
.pma_bonding_mode ("x1"),
.pcs_pma_width (10),
.ser_base_factor (8),
.ser_words (1),
.data_rate ("1250 Mbps"),
.base_data_rate ("2500 Mbps"),
.en_synce_support (0),
.tx_bitslip_enable ("false"),
.rx_use_coreclk ("false"),
.tx_use_coreclk ("false"),
.use_8b10b ("true"),
.use_8b10b_manual_control ("false"),
.std_tx_pcfifo_mode ("low_latency"),
.std_rx_pcfifo_mode ("low_latency"),
.word_aligner_mode ("sync_state_machine"),
.word_aligner_state_machine_datacnt (3),
.word_aligner_state_machine_errcnt (4),
.word_aligner_state_machine_patterncnt (4),
.word_aligner_pattern_length (7),
.word_align_pattern ("1111100"),
.run_length_violation_checking (5),
.use_rate_match_fifo (0),
.rate_match_pattern1 ("11010000111010000011"),
.rate_match_pattern2 ("00101111000101111100"),
.byte_order_mode ("none"),
.byte_order_pattern ("111111011"),
.byte_order_pad_pattern ("000000000"),
.coreclk_0ppm_enable ("false"),
.pll_refclk_cnt (1),
.pll_refclk_freq ("125.0 MHz"),
.pll_refclk_select ("0"),
.cdr_refclk_select (0),
.plls (1),
.pll_type ("ATX"),
.pll_select (0),
.pll_reconfig (0),
.pll_external_enable (0),
.gxb_analog_power ("AUTO"),
.pll_lock_speed ("AUTO"),
.tx_analog_power ("AUTO"),
.tx_slew_rate ("OFF"),
.tx_termination ("OCT_100_OHMS"),
.tx_use_external_termination ("false"),
.tx_preemp_pretap (0),
.tx_preemp_pretap_inv ("false"),
.tx_preemp_tap_1 (0),
.tx_preemp_tap_2 (0),
.tx_preemp_tap_2_inv ("false"),
.tx_vod_selection (2),
.tx_common_mode ("0.65V"),
.rx_pll_lock_speed ("AUTO"),
.rx_common_mode ("0.82V"),
.rx_termination ("OCT_100_OHMS"),
.rx_use_external_termination ("false"),
.rx_eq_dc_gain (1),
.rx_eq_ctrl (16),
.mgmt_clk_in_mhz (250),
.embedded_reset (1),
.channel_interface (0)
) i_custom_phyip_0 (
.phy_mgmt_clk (clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset (reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address (i_phyip_terminator_0_av_dummy_master_address), // phy_mgmt.address
.phy_mgmt_read (i_phyip_terminator_0_av_dummy_master_read), // .read
.phy_mgmt_readdata (i_phyip_terminator_0_av_dummy_master_readdata), // .readdata
.phy_mgmt_waitrequest (i_phyip_terminator_0_av_dummy_master_waitrequest), // .waitrequest
.phy_mgmt_write (i_phyip_terminator_0_av_dummy_master_write), // .write
.phy_mgmt_writedata (i_phyip_terminator_0_av_dummy_master_writedata), // .writedata
.tx_ready (i_custom_phyip_0_tx_ready_export), // tx_ready.export
.rx_ready (i_custom_phyip_0_rx_ready_export), // rx_ready.export
.pll_ref_clk (ref_clk), // pll_ref_clk.clk
.tx_serial_data (i_custom_phyip_0_tx_serial_data_export), // tx_serial_data.export
.pll_locked (i_custom_phyip_0_pll_locked_export), // pll_locked.export
.rx_serial_data (i_phyip_terminator_0_rx_serial_data_export), // rx_serial_data.export
.rx_runningdisp (i_custom_phyip_0_rx_runningdisp_export), // rx_runningdisp.export
.rx_disperr (i_custom_phyip_0_rx_disperr_export), // rx_disperr.export
.rx_errdetect (i_custom_phyip_0_rx_errdetect_export), // rx_errdetect.export
.rx_patterndetect (i_custom_phyip_0_rx_patterndetect_export), // rx_patterndetect.export
.rx_syncstatus (i_custom_phyip_0_rx_syncstatus_export), // rx_syncstatus.export
.rx_bitslipboundaryselectout (i_custom_phyip_0_rx_bitslipboundaryselectout_export), // rx_bitslipboundaryselectout.export
.rx_rlv (i_custom_phyip_0_rx_rlv_export), // rx_rlv.export
.rx_recovered_clk (i_custom_phyip_0_rx_recovered_clk_export), // rx_recovered_clk.export
.tx_clkout (i_custom_phyip_0_tx_clkout_export), // tx_clkout.export
.rx_clkout (i_custom_phyip_0_rx_clkout_export), // rx_clkout.export
.tx_parallel_data (i_tse_pcs_0_tx_frame_export), // tx_parallel_data.export
.tx_datak (i_tse_pcs_0_tx_kchar_export), // tx_datak.export
.rx_parallel_data (i_custom_phyip_0_rx_parallel_data_export), // rx_parallel_data.export
.rx_datak (i_custom_phyip_0_rx_datak_export), // rx_datak.export
.reconfig_from_xcvr (i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr), // reconfig_from_xcvr.reconfig_from_xcvr
.reconfig_to_xcvr (i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr), // reconfig_to_xcvr.reconfig_to_xcvr
.tx_forceelecidle (1'b0), // (terminated)
.tx_bitslipboundaryselect (5'b00000), // (terminated)
.rx_is_lockedtoref (), // (terminated)
.rx_is_lockedtodata (), // (terminated)
.rx_signaldetect (), // (terminated)
.rx_enabyteord (1'b0), // (terminated)
.rx_bitslip (1'b0), // (terminated)
.rx_rmfifodatainserted (), // (terminated)
.rx_rmfifodatadeleted (), // (terminated)
.rx_byteordflag (), // (terminated)
.tx_coreclkin (1'b0), // (terminated)
.rx_coreclkin (1'b0), // (terminated)
.cdr_ref_clk (1'b0), // (terminated)
.tx_dispval (1'b0), // (terminated)
.tx_forcedisp (1'b0), // (terminated)
.pll_powerdown (1'b0), // (terminated)
.tx_digitalreset (1'b0), // (terminated)
.tx_analogreset (1'b0), // (terminated)
.tx_cal_busy (), // (terminated)
.rx_digitalreset (1'b0), // (terminated)
.rx_analogreset (1'b0), // (terminated)
.rx_cal_busy (), // (terminated)
.ext_pll_clk (1'b0) // (terminated)
);
altera_eth_tse_phyip_terminator #(
.RECONFIG_TO_WIDTH (140),
.RECONFIG_FROM_WIDTH (92),
.ENABLE_TIMESTAMPING (0)
) i_phyip_terminator_0 (
.clk (clk), // clk.clk
.reset (reset), // reset.reset
.address (i_phyip_terminator_0_av_dummy_master_address), // av_dummy_master.address
.readdata (i_phyip_terminator_0_av_dummy_master_readdata), // .readdata
.read (i_phyip_terminator_0_av_dummy_master_read), // .read
.writedata (i_phyip_terminator_0_av_dummy_master_writedata), // .writedata
.write (i_phyip_terminator_0_av_dummy_master_write), // .write
.waitrequest (i_phyip_terminator_0_av_dummy_master_waitrequest), // .waitrequest
.rxp (rxp), // serial_connection.export
.txp (txp), // .export
.rx_recovclkout (rx_recovclkout), // serdes_control_connection.export
.reconfig_togxb (reconfig_togxb), // .export
.reconfig_fromgxb (reconfig_fromgxb), // .export
.tx_ready (i_custom_phyip_0_tx_ready_export), // tx_ready.export
.tx_serial_data (i_custom_phyip_0_tx_serial_data_export), // tx_serial_data.export
.sd_loopback (i_tse_pcs_0_sd_loopback_export), // sd_loopback.export
.rx_recovered_clk (i_custom_phyip_0_rx_recovered_clk_export), // rx_recovered_clk.export
.pll_locked (i_custom_phyip_0_pll_locked_export), // pll_locked.export
.rx_ready (i_custom_phyip_0_rx_ready_export), // rx_ready.export
.rx_serial_data (i_phyip_terminator_0_rx_serial_data_export), // rx_serial_data.export
.reconfig_to_xcvr (i_phyip_terminator_0_reconfig_to_xcvr_reconfig_to_xcvr), // reconfig_to_xcvr.reconfig_to_xcvr
.reconfig_from_xcvr (i_custom_phyip_0_reconfig_from_xcvr_reconfig_from_xcvr), // reconfig_from_xcvr.reconfig_from_xcvr
.cdr_ref_clk_out (), // (terminated)
.cdr_ref_clk_in (1'b0), // (terminated)
.terminate_rx_recovered_clk (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (reset), // reset_in0.reset
.clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (reset), // reset_in0.reset
.clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module altera_tse_gxb_aligned_rxsync (
input clk,
input reset,
input [7:0] alt_dataout,
input alt_sync,
input alt_disperr,
input alt_ctrldetect,
input alt_errdetect,
input alt_rmfifodatadeleted,
input alt_rmfifodatainserted,
input alt_runlengthviolation,
input alt_patterndetect,
input alt_runningdisp,
output reg [7:0] altpcs_dataout,
output altpcs_sync,
output reg altpcs_disperr,
output reg altpcs_ctrldetect,
output reg altpcs_errdetect,
output reg altpcs_rmfifodatadeleted,
output reg altpcs_rmfifodatainserted,
output reg altpcs_carrierdetect) ;
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
//-------------------------------------------------------------------------------
// intermediate wires
wire alt_dataout_sync;
wire alt_patterndetect_sync;
wire alt_runningdisp_sync;
//reg altpcs_dataout
// pipelined 1
reg [7:0] alt_dataout_reg1;
reg alt_sync_reg1;
reg alt_sync_reg2;
reg alt_disperr_reg1;
reg alt_ctrldetect_reg1;
reg alt_errdetect_reg1;
reg alt_rmfifodatadeleted_reg1;
reg alt_rmfifodatainserted_reg1;
reg alt_patterndetect_reg1;
reg alt_runningdisp_reg1;
reg alt_runlengthviolation_latched;
reg alt_runlengthviolation_latched_reg;
//-------------------------------------------------------------------------------
always @(posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
// pipelined 1
alt_dataout_reg1 <= 8'h0;
alt_sync_reg1 <= 1'b0;
alt_disperr_reg1 <= 1'b0;
alt_ctrldetect_reg1 <= 1'b0;
alt_errdetect_reg1 <= 1'b0;
alt_rmfifodatadeleted_reg1 <= 1'b0;
alt_rmfifodatainserted_reg1 <= 1'b0;
alt_patterndetect_reg1 <= 1'b0;
alt_runningdisp_reg1 <= 1'b0;
end
else
begin
// pipelined 1
alt_dataout_reg1 <= alt_dataout;
alt_sync_reg1 <= alt_sync;
alt_disperr_reg1 <= alt_disperr;
alt_ctrldetect_reg1 <= alt_ctrldetect;
alt_errdetect_reg1 <= alt_errdetect;
alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
alt_patterndetect_reg1 <= alt_patterndetect;
alt_runningdisp_reg1 <= alt_runningdisp;
end
end
altera_std_synchronizer #(2) alt_dataout_altera_std_synchronizer (
.clk ( clk ),
.reset_n ( ~reset ),
.din ( alt_dataout ),
.dout ( alt_dataout_sync )
);
altera_std_synchronizer #(2) alt_patterndetect_altera_std_synchronizer (
.clk ( clk ),
.reset_n ( ~reset ),
.din ( alt_patterndetect_reg1 ),
.dout ( alt_patterndetect_sync )
);
altera_std_synchronizer #(2) alt_runningdisp_altera_std_synchronizer (
.clk ( clk ),
.reset_n ( ~reset ),
.din ( alt_runningdisp_reg1 ),
.dout ( alt_runningdisp_sync )
);
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX" )
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
else
begin
if (alt_sync == 1'b1 )
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
end
else
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
end
end
end
assign altpcs_sync = alt_sync_reg1;
end
else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGZ" || DEVICE_FAMILY == "STRATIXV" || DEVICE_FAMILY == "ARRIAV" || DEVICE_FAMILY == "ARRIAVGZ" || DEVICE_FAMILY == "CYCLONEV" || DEVICE_FAMILY == "ARRIA10")
begin
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_dataout <= 8'h0;
altpcs_disperr <= 1'b1;
altpcs_ctrldetect <= 1'b0;
altpcs_errdetect <= 1'b1;
altpcs_rmfifodatadeleted <= 1'b0;
altpcs_rmfifodatainserted <= 1'b0;
alt_sync_reg2 <= 1'b0;
end
else
begin
altpcs_dataout <= alt_dataout_reg1;
altpcs_disperr <= alt_disperr_reg1;
altpcs_ctrldetect <= alt_ctrldetect_reg1;
altpcs_errdetect <= alt_errdetect_reg1;
altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
alt_sync_reg2 <= alt_sync_reg1 ;
end
end
assign altpcs_sync = alt_sync_reg2;
end
endgenerate
//latched runlength violation assertion for "carrier_detect" signal generation block
//reset the latch value after carrier_detect goes de-asserted
// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
// begin
// if (altpcs_carrierdetect == 1'b0)
// begin
// alt_runlengthviolation_latched <= 1'b0;
// end
// else
// begin
// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
// begin
// alt_runlengthviolation_latched <= 1'b1;
// end
// end
// end
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
begin
alt_runlengthviolation_latched <= 1'b0;
end
else
begin
if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
begin
alt_runlengthviolation_latched <= 1'b1;
end
end
end
end
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
alt_runlengthviolation_latched_reg <= 1'b0;
end
else
begin
alt_runlengthviolation_latched_reg <= alt_runlengthviolation_latched;
end
end
// carrier_detect signal generation
always @ (posedge reset or posedge clk)
begin
if (reset == 1'b1)
begin
altpcs_carrierdetect <= 1'b1;
end
else
// This portion of code is to workaround the issue with PHYIP (hard PCS) for not implementing the carrier_detect,
// which suppose to be implemented based on 10b character, not 8b.
//
// The real challenge is to detect the /INVALID/ 10b code group
//
// This is the Table 36.3.2.1 in UNH test plan
// =====================================================
// RD- code-group RD+ code-group
// =====================================================
// 001111 1010 /K28.5/ 110000 0101 /K28.5/
// 001111 1011 /INVALID/ 110000 0100 /INVALID/
// 001111 1000 /K28.7/ 110000 0111 /K28.7/
// 001111 1110 /INVALID/ 110000 0001 /INVALID/
// 001111 0010 /K28.4/ 110000 1101 /K28.4/
// 001110 1010 /D28.5/ 110001 0101 /D3.2/
// 001101 1010 /D12.5/ 110010 0101 /D19.2/
// 001011 1010 /D20.5/ 110100 0101 /D11.2/
// 000111 1010 /D7.5/ 111000 0101 /D7.2/
// 011111 1010 /INVALID/ 100000 0101 /INVALID/
// 101111 1010 /INVALID/ 010000 0101 /INVALID/
begin
if ( (alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_sync == 1'b1 & alt_runlengthviolation_latched_reg == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
& alt_disperr_reg1 ==1'b1 & alt_patterndetect_sync == 1'b0 & alt_runlengthviolation_latched_reg == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_sync == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b1 & alt_runlengthviolation_latched_reg == 1'b1 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b0 ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b0 & alt_runlengthviolation_latched_reg == 1'b1
& ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
(alt_sync_reg1 == 1'b1 & alt_dataout_sync == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_sync == 1'b0
& alt_runningdisp_sync == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
(alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
)
begin
altpcs_carrierdetect <= 1'b0;
end
else
begin
altpcs_carrierdetect <= 1'b1;
end
end
end
endmodule |
module pll_vhdl_altpll
(
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
output [9:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
cycloneiv_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.fref(),
.icdrclk(),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 1,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 5,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 2,
pll1.clk1_phase_shift = "0",
pll1.inclk0_input_frequency = 8000,
pll1.operation_mode = "no_compensation",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneiv_pll";
assign
clk = {{5{1'b0}}, wire_pll1_clk[4:0]},
locked = wire_pll1_locked;
endmodule //pll_vhdl_altpll |
module altpcie_rs_serdes (
input pld_clk,
input [39:0] test_in,
input [4:0] ltssm,
input npor,
input pll_locked,
input busy_altgxb_reconfig,
input [7:0] rx_pll_locked,
input [7:0] rx_freqlocked,
input [7:0] rx_signaldetect,
input use_c4gx_serdes,
input fifo_err,
input rc_inclk_eq_125mhz,
input detect_mask_rxdrst,
output txdigitalreset,
output rxanalogreset,
output rxdigitalreset
);
localparam [19:0] WS_SIM = 20'h00020;
localparam [19:0] WS_1MS_10000 = 20'h186a0;
localparam [19:0] WS_1MS_12500 = 20'h1e848;
localparam [19:0] WS_1MS_15625 = 20'h2625a;
localparam [19:0] WS_1MS_25000 = 20'h3d090;
localparam [1:0] STROBE_TXPLL_LOCKED_SD_CNT = 2'b00;
localparam [1:0] IDLE_ST_CNT = 2'b01;
localparam [1:0] STABLE_TX_PLL_ST_CNT = 2'b10;
localparam [1:0] WAIT_STATE_ST_CNT = 2'b11;
localparam [1:0] IDLE_ST_SD = 2'b00;
localparam [1:0] RSET_ST_SD = 2'b01;
localparam [1:0] DONE_ST_SD = 2'b10;
localparam [1:0] DFLT_ST_SD = 2'b11;
localparam [4:0] LTSSM_POL = 5'b00010;
localparam [4:0] LTSSM_DET = 5'b00000;
genvar i;
// Reset
wire arst;
reg [2:0] arst_r;
// Test
wire test_sim; // When 1 simulation mode
wire test_cbb_compliance; // When 1 DUT is under PCIe Compliance board test mode
(* syn_encoding = "user" *) reg [1:0] serdes_rst_state;
reg [19:0] waitstate_timer;
reg txdigitalreset_r;
reg rxanalogreset_r;
reg rxdigitalreset_r;
reg ws_tmr_eq_0;
reg ld_ws_tmr;
reg ld_ws_tmr_short;
wire rx_pll_freq_locked;
reg [7:0] rx_pll_locked_sync_r;
reg [2:0] rx_pll_freq_locked_cnt ;
reg rx_pll_freq_locked_sync_r ;
reg [1:0] busy_altgxb_reconfig_r;
wire pll_locked_sync;
reg [2:0] pll_locked_r;
reg [6:0] pll_locked_cnt;
reg pll_locked_stable;
reg [4:0] ltssm_r;
wire rx_pll_freq_locked_sync;
reg [2:0] rx_pll_freq_locked_r;
wire [7:0] rx_pll_locked_sync;
reg [7:0] rx_pll_locked_r;
reg [7:0] rx_pll_locked_rr;
reg [7:0] rx_pll_locked_rrr;
wire [7:0] rx_signaldetect_sync;
reg [7:0] rx_signaldetect_r;
reg [7:0] rx_signaldetect_rr;
reg [7:0] rx_signaldetect_rrr;
reg ltssm_detect; // when 1 , the LTSSM is in detect state
reg [7:0] rx_sd_strb0;
reg [7:0] rx_sd_strb1;
wire stable_sd;
wire rst_rxpcs_sd;
(* syn_encoding = "user" *) reg [1:0] sd_state; //State machine for rx_signaldetect strobing;
reg [ 19: 0] rx_sd_idl_cnt;
assign test_sim =test_in[0];
assign test_cbb_compliance =test_in[32];
// SERDES reset outputs
assign txdigitalreset = txdigitalreset_r ;
assign rxanalogreset = (use_c4gx_serdes==1'b1)?arst:rxanalogreset_r ;
assign rxdigitalreset = (detect_mask_rxdrst==1'b0)?rxdigitalreset_r|rst_rxpcs_sd:(ltssm_detect==1'b1)?1'b0:rxdigitalreset_r | rst_rxpcs_sd;
//npor Reset Synchronizer on pld_clk
always @(posedge pld_clk or negedge npor) begin
if (npor == 1'b0) begin
arst_r[2:0] <= 3'b111;
end
else begin
arst_r[2:0] <= {arst_r[1],arst_r[0],1'b0};
end
end
assign arst = arst_r[2];
// Synchronize pll_lock,rx_pll_freq_locked to pld_clk
// using 3 level sync circuit
assign rx_pll_freq_locked = &(rx_pll_locked_sync_r[7:0] | rx_freqlocked[7:0] );
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
pll_locked_r[2:0] <= 3'b000;
rx_pll_freq_locked_r[2:0] <= 3'b000;
ltssm_r <= 5'h0;
end
else begin
pll_locked_r[2:0] <= {pll_locked_r[1],pll_locked_r[0],pll_locked};
rx_pll_freq_locked_r[2:0] <= {rx_pll_freq_locked_r[1],rx_pll_freq_locked_r[0],rx_pll_freq_locked};
ltssm_r <= ltssm;
end
end
assign pll_locked_sync = pll_locked_r[2];
assign rx_pll_freq_locked_sync = rx_pll_freq_locked_r[2];
// Synchronize rx_pll_locked[7:0],rx_signaldetect[7:0] to pld_clk
// using 3 level sync circuit
generate
for (i=0;i<8;i=i+1) begin : g_rx_pll_locked_sync
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_pll_locked_r[i] <= 1'b0;
rx_pll_locked_rr[i] <= 1'b0;
rx_pll_locked_rrr[i] <= 1'b0;
rx_signaldetect_r[i] <= 1'b0;
rx_signaldetect_rr[i] <= 1'b0;
rx_signaldetect_rrr[i] <= 1'b0;
end
else begin
rx_pll_locked_r[i] <= rx_pll_locked[i];
rx_pll_locked_rr[i] <= rx_pll_locked_r[i];
rx_pll_locked_rrr[i] <= rx_pll_locked_rr[i];
rx_signaldetect_r[i] <= rx_signaldetect[i];
rx_signaldetect_rr[i] <= rx_signaldetect_r[i];
rx_signaldetect_rrr[i] <= rx_signaldetect_rr[i];
end
end
assign rx_pll_locked_sync[i] = rx_pll_locked_rrr[i];
assign rx_signaldetect_sync[i] = rx_signaldetect_rrr[i];
end
endgenerate
always @(posedge pld_clk or posedge arst)
begin
if (arst == 1'b1) begin
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
waitstate_timer <= 20'hFFFFF ;
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
ws_tmr_eq_0 <= 1'b0 ;
ld_ws_tmr <= 1'b1 ;
ld_ws_tmr_short <= 1'b0 ;
rx_pll_freq_locked_cnt <= 3'h0;
rx_pll_freq_locked_sync_r <= 1'b0;
rx_pll_locked_sync_r <= 8'h00;
busy_altgxb_reconfig_r[1:0] <= 2'b11;
pll_locked_cnt <= 7'h0;
pll_locked_stable <= 1'b0;
ltssm_detect <= 1'b1;
end
else begin
if ((ltssm_r==5'h0)||(ltssm_r==5'h1)) begin
ltssm_detect <= 1'b1;
end
else begin
ltssm_detect <= 1'b0;
end
if ( rx_pll_locked_sync[7:0]==8'hFF ) begin
rx_pll_locked_sync_r <= 8'hFF;
end
// add hysteresis for losing lock
if (rx_pll_freq_locked_sync == 1'b1) begin
rx_pll_freq_locked_cnt <= 3'h7;
end
else if (rx_pll_freq_locked_cnt == 3'h0) begin
rx_pll_freq_locked_cnt <= 3'h0;
end
else if (rx_pll_freq_locked_sync == 1'b0) begin
rx_pll_freq_locked_cnt <= rx_pll_freq_locked_cnt - 3'h1;
end
rx_pll_freq_locked_sync_r <= (rx_pll_freq_locked_cnt != 3'h0);
busy_altgxb_reconfig_r[1] <= busy_altgxb_reconfig_r[0];
busy_altgxb_reconfig_r[0] <= busy_altgxb_reconfig;
if (pll_locked_sync==1'b0) begin
pll_locked_cnt <= 7'h0;
end
else if (pll_locked_cnt < 7'h7F) begin
pll_locked_cnt <= pll_locked_cnt+7'h1;
end
pll_locked_stable <= (pll_locked_cnt==7'h7F)?1'b1:1'b0;
if (ld_ws_tmr == 1'b1) begin
if (test_sim == 1'b1) begin
waitstate_timer <= WS_SIM ;
end
else if (rc_inclk_eq_125mhz == 1'b1) begin
waitstate_timer <= WS_1MS_12500 ;
end
else begin
waitstate_timer <= WS_1MS_25000 ;
end
end
else if (ld_ws_tmr_short == 1'b1) begin
waitstate_timer <= WS_SIM ;
end
else if (waitstate_timer != 20'h00000) begin
waitstate_timer <= waitstate_timer - 20'h1 ;
end
if (ld_ws_tmr == 1'b1 | ld_ws_tmr_short) begin
ws_tmr_eq_0 <= 1'b0 ;
end
else if (waitstate_timer == 20'h00000) begin
ws_tmr_eq_0 <= 1'b1 ;
end
else begin
ws_tmr_eq_0 <= 1'b0 ;
end
case (serdes_rst_state)
STROBE_TXPLL_LOCKED_SD_CNT : begin
ld_ws_tmr <= 1'b0 ;
if ((pll_locked_sync == 1'b1) && (ws_tmr_eq_0 == 1'b1) && (pll_locked_stable==1'b1)) begin
serdes_rst_state <= (busy_altgxb_reconfig_r[1]==1'b1)?STROBE_TXPLL_LOCKED_SD_CNT:STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= (busy_altgxb_reconfig_r[1]==1'b1)?1'b1:1'b0;
rxdigitalreset_r <= 1'b1 ;
end
else begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
end
end
IDLE_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
if (fifo_err == 1'b1) begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
end
else begin
serdes_rst_state <= IDLE_ST_CNT ;
end
end
else begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
ld_ws_tmr <= 1'b1 ;
end
end
STABLE_TX_PLL_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
serdes_rst_state <= WAIT_STATE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
ld_ws_tmr_short <= 1'b1 ;
end
else begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
WAIT_STATE_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
ld_ws_tmr_short <= 1'b0 ;
if (ld_ws_tmr_short == 1'b0 & ws_tmr_eq_0 == 1'b1) begin
serdes_rst_state <= IDLE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b0 ;
end
else begin
serdes_rst_state <= WAIT_STATE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
else begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
default : begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
waitstate_timer <= 20'hFFFFF ;
end
endcase
end
end
////////////////////////////////////////////////////////////////
//
// Signal detect logic use suffix/prefix _sd
//
// rx_signaldetect strobing (stable_sd)
assign rst_rxpcs_sd = ((test_cbb_compliance==1'b1)||(use_c4gx_serdes==1'b1))?1'b0:sd_state[0];
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_sd_strb0[7:0] <= 8'h00;
rx_sd_strb1[7:0] <= 8'h00;
end
else begin
rx_sd_strb0[7:0] <= rx_signaldetect_sync[7:0];
rx_sd_strb1[7:0] <= rx_sd_strb0[7:0];
end
end
assign stable_sd = (rx_sd_strb1[7:0] == rx_sd_strb0[7:0]) & (rx_sd_strb1[7:0] != 8'h00);
//signal detect based reset logic
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= IDLE_ST_SD;
end
else begin
case (sd_state)
IDLE_ST_SD: begin
//reset RXPCS on polling.active
if (ltssm_r == LTSSM_POL) begin
rx_sd_idl_cnt <= (rx_sd_idl_cnt > 20'd10) ? rx_sd_idl_cnt - 20'd10 : 20'h0;
sd_state <= RSET_ST_SD;
end
else begin //Incoming signal unstable, clear counter
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
end
else if ((stable_sd == 1'b1) & (rx_sd_idl_cnt < 20'd750000)) begin
rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
end
end
end
RSET_ST_SD: begin
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= (ltssm_r == LTSSM_DET) ? IDLE_ST_SD : RSET_ST_SD;
end
else begin
if ((test_sim == 1'b1) & (rx_sd_idl_cnt >= 20'd32)) begin
rx_sd_idl_cnt <= 20'd32;
sd_state <= DONE_ST_SD;
end
else begin
if (rx_sd_idl_cnt == 20'd750000) begin
rx_sd_idl_cnt <= 20'd750000;
sd_state <= DONE_ST_SD;
end
else if (stable_sd == 1'b1) begin
rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
end
end
end
end
DONE_ST_SD: begin
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= (ltssm_r == LTSSM_DET) ? IDLE_ST_SD : DONE_ST_SD;
end
end
default: begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= IDLE_ST_SD;
end
endcase
end
end
endmodule |
module altpcie_reconfig_3cgx_alt_dprio_v5k
(
address,
busy,
datain,
dataout,
dpclk,
dpriodisable,
dprioin,
dprioload,
dprioout,
quad_address,
rden,
reset,
wren,
wren_data) /* synthesis synthesis_clearbox=2 */;
input [15:0] address;
output busy;
input [15:0] datain;
output [15:0] dataout;
input dpclk;
output dpriodisable;
output dprioin;
output dprioload;
input dprioout;
input [8:0] quad_address;
input rden;
input reset;
input wren;
input wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [15:0] datain;
tri0 rden;
tri0 reset;
tri0 wren;
tri0 wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] addr_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] in_data_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] rd_out_data_shift_reg;
wire [2:0] wire_startup_cntr_d;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [2:0] startup_cntr;
wire [2:0] wire_startup_cntr_ena;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg [2:0] state_mc_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] wr_out_data_shift_reg;
wire wire_pre_amble_cmpr_aeb;
wire wire_pre_amble_cmpr_agb;
wire wire_rd_data_output_cmpr_ageb;
wire wire_rd_data_output_cmpr_alb;
wire wire_state_mc_cmpr_aeb;
wire [5:0] wire_state_mc_counter_q;
wire [7:0] wire_state_mc_decode_eq;
wire wire_dprioin_mux_dataout;
wire busy_state;
wire idle_state;
wire rd_addr_done;
wire rd_addr_state;
wire rd_data_done;
wire rd_data_input_state;
wire rd_data_output_state;
wire rd_data_state;
wire rdinc;
wire read_state;
wire s0_to_0;
wire s0_to_1;
wire s1_to_0;
wire s1_to_1;
wire s2_to_0;
wire s2_to_1;
wire startup_done;
wire startup_idle;
wire wr_addr_done;
wire wr_addr_state;
wire wr_data_done;
wire wr_data_state;
wire write_state;
// synopsys translate_off
initial
addr_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) addr_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, 1'b0, quad_address[8:0], 2'b10, address};
else addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
// synopsys translate_off
initial
in_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) in_data_shift_reg <= 16'b0;
else if (rd_data_input_state == 1'b1) in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
// synopsys translate_off
initial
rd_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) rd_out_data_shift_reg <= 16'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, 1'b0, quad_address, 2'b10};
else rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
// synopsys translate_off
initial
startup_cntr[0:0] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[0:0] == 1'b1)
if (reset == 1'b1) startup_cntr[0:0] <= 1'b0;
else startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
// synopsys translate_off
initial
startup_cntr[1:1] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[1:1] == 1'b1)
if (reset == 1'b1) startup_cntr[1:1] <= 1'b0;
else startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
// synopsys translate_off
initial
startup_cntr[2:2] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[2:2] == 1'b1)
if (reset == 1'b1) startup_cntr[2:2] <= 1'b0;
else startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
assign
wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
assign
wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
// synopsys translate_off
initial
state_mc_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) state_mc_reg <= 3'b0;
else state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
// synopsys translate_off
initial
wr_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) wr_out_data_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, 1'b0, quad_address[8:0], 2'b10, datain};
else wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
lpm_compare pre_amble_cmpr
(
.aeb(wire_pre_amble_cmpr_aeb),
.agb(wire_pre_amble_cmpr_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b011111)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pre_amble_cmpr.lpm_width = 6,
pre_amble_cmpr.lpm_type = "lpm_compare";
lpm_compare rd_data_output_cmpr
(
.aeb(),
.agb(),
.ageb(wire_rd_data_output_cmpr_ageb),
.alb(wire_rd_data_output_cmpr_alb),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b110000)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rd_data_output_cmpr.lpm_width = 6,
rd_data_output_cmpr.lpm_type = "lpm_compare";
lpm_compare state_mc_cmpr
(
.aeb(wire_state_mc_cmpr_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab({6{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_cmpr.lpm_width = 6,
state_mc_cmpr.lpm_type = "lpm_compare";
lpm_counter state_mc_counter
(
.clock(dpclk),
.cnt_en((write_state | read_state)),
.cout(),
.eq(),
.q(wire_state_mc_counter_q),
.sclr(reset)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({6{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_counter.lpm_port_updown = "PORT_UNUSED",
state_mc_counter.lpm_width = 6,
state_mc_counter.lpm_type = "lpm_counter";
lpm_decode state_mc_decode
(
.data(state_mc_reg),
.eq(wire_state_mc_decode_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_decode.lpm_decodes = 8,
state_mc_decode.lpm_width = 3,
state_mc_decode.lpm_type = "lpm_decode";
or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
assign
busy = busy_state,
busy_state = (write_state | read_state),
dataout = in_data_shift_reg,
dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
dprioin = wire_dprioin_mux_dataout,
dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
idle_state = wire_state_mc_decode_eq[0],
rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
rdinc = 1'b0,
read_state = (rd_addr_state | rd_data_state),
s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
write_state = (wr_addr_state | wr_data_state);
endmodule //altpcie_reconfig_3cgx_alt_dprio_v5k |
module altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp
(
busy,
offset_cancellation_reset,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb) /* synthesis synthesis_clearbox=2 */;
output busy;
input offset_cancellation_reset;
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output [3:0] reconfig_togxb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 offset_cancellation_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_calibration_c3gxb_busy;
wire [15:0] wire_calibration_c3gxb_dprio_addr;
wire [15:0] wire_calibration_c3gxb_dprio_dataout;
wire wire_calibration_c3gxb_dprio_rden;
wire wire_calibration_c3gxb_dprio_wren;
wire [8:0] wire_calibration_c3gxb_quad_addr;
wire wire_calibration_c3gxb_retain_addr;
wire wire_dprio_busy;
wire [15:0] wire_dprio_dataout;
wire wire_dprio_dpriodisable;
wire wire_dprio_dprioin;
wire wire_dprio_dprioload;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
reg [11:0] address_pres_reg;
wire cal_busy;
wire [0:0] cal_dprioout_wire;
wire [3:0] cal_testbuses;
wire [2:0] channel_address;
wire [15:0] dprio_address;
wire [8:0] quad_address;
wire reconfig_reset_all;
alt_cal_c3gxb calibration_c3gxb
(
.busy(wire_calibration_c3gxb_busy),
.cal_error(),
.clock(reconfig_clk),
.dprio_addr(wire_calibration_c3gxb_dprio_addr),
.dprio_busy(wire_dprio_busy),
.dprio_datain(wire_dprio_dataout),
.dprio_dataout(wire_calibration_c3gxb_dprio_dataout),
.dprio_rden(wire_calibration_c3gxb_dprio_rden),
.dprio_wren(wire_calibration_c3gxb_dprio_wren),
.quad_addr(wire_calibration_c3gxb_quad_addr),
.remap_addr(address_pres_reg),
.reset((offset_cancellation_reset | reconfig_reset_all)),
.retain_addr(wire_calibration_c3gxb_retain_addr),
.testbuses(cal_testbuses)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.start(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
calibration_c3gxb.channel_address_width = 2,
calibration_c3gxb.number_of_channels = 4,
calibration_c3gxb.sim_model_mode = "FALSE",
calibration_c3gxb.lpm_type = "alt_cal_c3gxb";
altpcie_reconfig_3cgx_alt_dprio_v5k dprio
(
.address(({16{wire_calibration_c3gxb_busy}} & dprio_address)),
.busy(wire_dprio_busy),
.datain(({16{wire_calibration_c3gxb_busy}} & wire_calibration_c3gxb_dprio_dataout)),
.dataout(wire_dprio_dataout),
.dpclk(reconfig_clk),
.dpriodisable(wire_dprio_dpriodisable),
.dprioin(wire_dprio_dprioin),
.dprioload(wire_dprio_dprioload),
.dprioout(cal_dprioout_wire),
.quad_address(address_pres_reg[11:3]),
.rden((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_rden)),
.reset(reconfig_reset_all),
.wren((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_wren)),
.wren_data(wire_calibration_c3gxb_retain_addr));
// synopsys translate_off
initial
address_pres_reg = 0;
// synopsys translate_on
always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
if (reconfig_reset_all == 1'b1) address_pres_reg <= 12'b0;
else address_pres_reg <= {quad_address, channel_address};
assign
busy = cal_busy,
cal_busy = wire_calibration_c3gxb_busy,
cal_dprioout_wire = {reconfig_fromgxb[0]},
cal_testbuses = {reconfig_fromgxb[4:1]},
channel_address = wire_calibration_c3gxb_dprio_addr[14:12],
dprio_address = {wire_calibration_c3gxb_dprio_addr[15], address_pres_reg[2:0], wire_calibration_c3gxb_dprio_addr[11:0]},
quad_address = wire_calibration_c3gxb_quad_addr,
reconfig_reset_all = 1'b0,
reconfig_togxb = {wire_calibration_c3gxb_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin};
endmodule //altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp |
module altpcie_reconfig_3cgx (
offset_cancellation_reset,
reconfig_clk,
reconfig_fromgxb,
busy,
reconfig_togxb)/* synthesis synthesis_clearbox = 2 */;
input offset_cancellation_reset;
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output busy;
output [3:0] reconfig_togxb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 offset_cancellation_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire sub_wire1;
wire [3:0] reconfig_togxb = sub_wire0[3:0];
wire busy = sub_wire1;
altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp_component (
.reconfig_clk (reconfig_clk),
.offset_cancellation_reset (offset_cancellation_reset),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (sub_wire0),
.busy (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb_reconfig
clearbox_defparam = "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;" */;
endmodule |
module pcie_c4_4x_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
)
;
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [ 4: 0] ltssm;
input npor;
input pld_clk;
input test_sim;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg app_rstn;
reg app_rstn0;
reg crst;
reg crst0;
reg [ 4: 0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
wire otb0;
wire otb1;
reg [ 10: 0] rsnt_cntn;
reg srst;
reg srst0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end
else
begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
dl_ltssm_r <= 0;
else
dl_ltssm_r <= ltssm;
end
//reset Synchronizer
always @(posedge pld_clk or negedge npor)
begin
if (npor == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//reset counter
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
rsnt_cntn <= 0;
else if (exits_r == 1'b1)
rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024)
rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end
else if (exits_r == 1'b1)
begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end
else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32))
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
else // synthesis translate_on
if (rsnt_cntn == 11'd1024)
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end
else
begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
endmodule |
module top(
//////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
ENETCLK_25,
//////// LED //////////
LEDG,
LEDR,
//////// KEY //////////
KEY,
//////// SW //////////
SW,
//////// RS232 //////////
UART_RXD,
UART_TXD,
//////// SRAM //////////
SRAM_ADDR,
SRAM_CE_N,
SRAM_DQ,
SRAM_LB_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_WE_N
);
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input ENETCLK_25;
//////////// LED //////////
output [8:0] LEDG;
output [17:0] LEDR;
//////////// KEY //////////
input [3:0] KEY;
//////////// SW //////////
input [17:0] SW;
//////////// RS232 //////////
input UART_RXD;
output UART_TXD;
//////////// SRAM //////////
output [19:0] SRAM_ADDR;
output SRAM_CE_N;
inout [15:0] SRAM_DQ;
output SRAM_LB_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_WE_N;
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
/*
// 下面是SW拨码开关的配置
[0]: reserved，恒为0
[1]: reserved，恒为0
[2]: reserved，恒为0
[3]: 按钮KEY[3]按下触发CNN；1-->使能按钮触发
[4]: reserved，恒为0
[5]: 串口触发CNN运算，测试硬件化正确性；1-->使能串口触发
*/
////////////////////////////////////////////////////////
// 三种模式
wire TEST_MODE = (SW[5:1]==5'B10100);
wire SAMP_MODE = (SW[5:1]==5'B00011);
wire RUN_MODE = (SW[5:1]==5'B01001);
wire SIMU_MODE = (SW[5:1]==5'B01000); // 仿真模式，切断MFCC写入SRAM的过程
////////////////////////////////////////////////
// 全局复位信号
wire RESET_N = KEY[0];
// 同时用PLL重新生成一下全局时钟
wire CLOCK50, CLOCK60, CLOCK40, CLOCK10, CLOCK12p28;
alt_pll_ip_core alt_pll_ip_core_inst(
.inclk0(CLOCK_50),
.c0(CLOCK50),
.c1(CLOCK60),
.c2(CLOCK40),
.c3(CLOCK10),
.c4(CLOCK12p28)
);
////////////////////////////////////////////////////////////////
// 系统运行的时钟和复位信号
wire sys_clk = CLOCK60;
wire sys_rst_n = RESET_N;
// 然后是uart接口
// 然后需要一个命令解析器，能够将数据扩充之后返回
// 和uart的接口
wire [31:0] sys_uart_write_data /* synthesis keep */;
wire sys_uart_write_data_valid /* synthesis keep */;
wire sys_uart_write_data_permitted /* synthesis keep */;
wire [15:0] sys_uart_read_data /* synthesis keep */;
wire sys_uart_read_data_req /* synthesis keep */;
wire sys_uart_read_data_permitted /* synthesis keep */;
// 和ddr的接口
wire [31:0] sys_ddr_write_addr /* synthesis keep */;
wire [31:0] sys_ddr_write_data /* synthesis keep */;
wire sys_ddr_write_data_valid /* synthesis keep */;
wire sys_ddr_write_burst_begin /* synthesis keep */;
wire sys_ddr_write_data_permitted /* synthesis keep */;
wire [31:0] sys_ddr_read_addr /* synthesis keep */;
wire [31:0] sys_ddr_read_data /* synthesis keep */;
wire sys_ddr_read_data_valid /* synthesis keep */;
wire sys_ddr_read_burst_begin /* synthesis keep */;
wire sys_ddr_read_data_req /* synthesis keep */;
wire sys_ddr_read_data_permitted /* synthesis keep */;
wire logic_receive_valid_cmd;
/********************************************************************************************/
// NPU指令接口
wire [31:0] npu_inst_part;
wire npu_inst_part_en;
/*
*/
cmd_parser cmd_parser_inst(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.sys_uart_write_data(sys_uart_write_data),
.sys_uart_write_data_valid(sys_uart_write_data_valid),
.sys_uart_write_data_permitted(sys_uart_write_data_permitted),
.sys_uart_read_data(sys_uart_read_data),
.sys_uart_read_data_req(sys_uart_read_data_req),
.sys_uart_read_data_permitted(sys_uart_read_data_permitted),
.sys_ddr_write_addr(sys_ddr_write_addr),
.sys_ddr_write_data(sys_ddr_write_data),
.sys_ddr_write_data_valid(sys_ddr_write_data_valid),
.sys_ddr_write_burst_begin(sys_ddr_write_burst_begin),
.sys_ddr_write_data_permitted(sys_ddr_write_data_permitted),
.sys_ddr_read_addr(sys_ddr_read_addr),
.sys_ddr_read_data(sys_ddr_read_data),
.sys_ddr_read_data_valid(sys_ddr_read_data_valid),
.sys_ddr_read_data_req(sys_ddr_read_data_req),
.sys_ddr_read_burst_begin(sys_ddr_read_burst_begin),
.sys_ddr_read_data_permitted(sys_ddr_read_data_permitted),
.receive_valid_cmd(logic_receive_valid_cmd),
.sys_key_fn(8'HFF),
//
.adc_ddr_write_addr(),
.adc_ddr_write_addr_mask(),
//
.audio_sample_en(audio_sample_en),
// NPU指令接口
.npu_inst_part(npu_inst_part),
.npu_inst_part_en(npu_inst_part_en)
);
// 串口
// 例化一个cypress uart的读写模块
// uart的slavefifo读写模块
uart_wr uart_wr_inst(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.uart_rxd(UART_RXD),
.uart_txd(UART_TXD),
.uart_sys_clk(CLOCK50),
.uart_sys_rst_n(RESET_N),
.sys_write_data(sys_uart_write_data),
.sys_write_data_valid(sys_uart_write_data_valid),
.sys_write_data_permitted(sys_uart_write_data_permitted),
.sys_read_data(sys_uart_read_data),
.sys_read_data_req(sys_uart_read_data_req),
.sys_read_data_permitted(sys_uart_read_data_permitted)
);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
///////////////////////////// NPU 指令集架构
/*
*/
wire [127:0] npu_inst /* synthesis noprune */;
wire npu_inst_en /* synthesis noprune */;
wire npu_inst_ready;
// 计量NPU指令计算周期数
wire [31:0] npu_inst_time;
wire NPU_DDR_WRITE_CLK;
wire [31:0] NPU_DDR_WRITE_ADDR;
wire [31:0] NPU_DDR_WRITE_DATA;
wire NPU_DDR_WRITE_REQ;
wire NPU_DDR_WRITE_READY;
wire NPU_DDR_READ_CLK;
wire [31:0] NPU_DDR_READ_ADDR;
wire NPU_DDR_READ_REQ;
wire NPU_DDR_READ_READY;
wire [31:0] NPU_DDR_READ_DATA;
wire NPU_DDR_READ_DATA_VALID;
wire npu_inst_clk = CLOCK60;
wire npu_inst_rst_n = RESET_N;
wire [31:0] npu_inst_addr;
wire [127:0] npu_inst_q;
wire npu_inst_start_vad; // 允许另一个模块启动NPU运算
// 这里debug一下；因为不确定NPU卡住/不断被触发
// 所以NPU运算使能，需要有debug措施：如果 KEY_CNN ==1，那么由按钮按下触发；否则，就是正常工作 // mark: 2018/6/4
wire KEY3_DOWN; // 按下按钮3
wire npu_inst_start = TEST_MODE? ((npu_inst_en && npu_inst==128'D2)|KEY3_DOWN) : (RUN_MODE||SIMU_MODE)? npu_inst_start_vad : 0;
npu_inst_fsm npu_inst_fsm_inst(
.clk(npu_inst_clk),
.rst_n(npu_inst_rst_n),
.npu_inst_addr(npu_inst_addr),
.npu_inst_q(npu_inst_q),
.npu_inst_start(npu_inst_start),
.npu_inst_ready(npu_inst_ready),
.npu_inst_time(npu_inst_time),
// DDR
.DDR_WRITE_CLK(NPU_DDR_WRITE_CLK),
.DDR_WRITE_ADDR(NPU_DDR_WRITE_ADDR),
.DDR_WRITE_DATA(NPU_DDR_WRITE_DATA),
.DDR_WRITE_REQ(NPU_DDR_WRITE_REQ),
.DDR_WRITE_READY(NPU_DDR_WRITE_READY),
.DDR_READ_CLK(NPU_DDR_READ_CLK),
.DDR_READ_ADDR(NPU_DDR_READ_ADDR),
.DDR_READ_REQ(NPU_DDR_READ_REQ),
.DDR_READ_READY(NPU_DDR_READ_READY),
.DDR_READ_DATA(NPU_DDR_READ_DATA),
.DDR_READ_DATA_VALID(NPU_DDR_READ_DATA_VALID)
);
// 生成 按下按钮的信号
reg [1:0] KEY3;
always @(posedge npu_inst_clk)
KEY3 <= {KEY3[0], KEY[3]};
assign KEY3_DOWN = (KEY3==2'B10);
// 存储NPU指令的地址
reg [31:0] npu_inst_wraddr;
always @(posedge npu_inst_clk)
if(npu_inst_en && npu_inst==128'D1)
npu_inst_wraddr <= 0;
else if(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2)
npu_inst_wraddr <= npu_inst_wraddr +1;
// 然后要将NPU指令存储到RAM里面去
npu_inst_ram npu_inst_ram_inst(
.data(npu_inst),
.wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
.wraddress(npu_inst_wraddr),
.wrclock(npu_inst_clk),
.rdclock(npu_inst_clk),
.rdaddress(npu_inst_addr),
.q(npu_inst_q)
);
// 然后要将NPU指令存储到RAM里面去，并可以通过memory editor观察
npu_inst_ram_bak npu_inst_ram_bak_inst(
.data(npu_inst),
.wren(npu_inst_en && npu_inst!=128'D1 && npu_inst!=128'D2),
.address(npu_inst_wraddr),
.clock(npu_inst_clk)
);
// 生成npu_inst/npu_inst_en
// 超时等待机制
npu_inst_join npu_inst_join_inst(
.npu_inst_clk(npu_inst_clk),
.npu_inst_rst_n(npu_inst_rst_n),
.npu_inst_part(npu_inst_part),
.npu_inst_part_en(npu_inst_part_en),
.npu_inst(npu_inst),
.npu_inst_en(npu_inst_en)
);
/////////////////////////////////////////////////////////////////////
// 配置CNN的参数
// 配置CNN的参数
wire cnn_paras_ready; // 参数配置模块闲置状态
wire cnn_paras_en = !KEY[2]; // 使能配置
wire [31:0] cnn_paras_q; // CNN的参数
wire [31:0] cnn_paras_addr; // CNN参数的地址
// DDR接口
wire CNN_DDR_WRITE_CLK;
wire [31:0] CNN_DDR_WRITE_ADDR;
wire [31:0] CNN_DDR_WRITE_DATA;
wire CNN_DDR_WRITE_REQ;
wire CNN_DDR_WRITE_READY;
//
npu_paras_rom npu_paras_rom_inst(
.clock(CLOCK60),
.address(cnn_paras_addr),
.q(cnn_paras_q)
);
npu_paras_config npu_paras_config_inst(
.clk(CLOCK60),
.rst_n(RESET_N),
.npu_paras_ready(cnn_paras_ready),
.npu_paras_en(cnn_paras_en),
.npu_paras_addr(cnn_paras_addr),
.npu_paras_q(cnn_paras_q),
// DDR
.DDR_WRITE_CLK(CNN_DDR_WRITE_CLK),
.DDR_WRITE_ADDR(CNN_DDR_WRITE_ADDR),
.DDR_WRITE_DATA(CNN_DDR_WRITE_DATA),
.DDR_WRITE_REQ(CNN_DDR_WRITE_REQ),
.DDR_WRITE_READY(CNN_DDR_WRITE_READY)
);
/////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
///////////////////
// 和内存有关的时钟和复位
wire afi_phy_clk /* synthesis keep */;
wire afi_phy_rst_n /* synthesis keep */;
// SSRAM
// 添加一个缓存空间 // 使用ddr的IP核
// // 声明核心多路选通控制器
wire local_ready; // local.waitrequest_n
wire local_burstbegin; // .beginbursttransfer
wire [31:0] local_addr; // .address
wire local_rdata_valid; // .readdatavalid
wire [31:0] local_rdata; // .readdata
wire [31:0] local_wdata; // .writedata
wire [3:0] local_be; // .byteenable
wire local_read_req; // .read
wire local_write_req; // .write
wire [2:0] local_size; // .burstcount
wire local_waitrequest;
// // 声明附属多路选通控制器
wire attach_ready; // attach.waitrequest_n
wire attach_burstbegin; // .beginbursttransfer
wire [31:0] attach_addr; // .address
wire attach_rdata_valid; // .readdatavalid
wire [31:0] attach_rdata; // .readdata
wire [31:0] attach_wdata; // .writedata
wire [3:0] attach_be; // .byteenable
wire attach_read_req; // .read
wire attach_write_req; // .write
wire [2:0] attach_size; // .burstcount
wire attach_ready_w, attach_ready_r; // 读写允许
assign attach_ready = attach_write_req? attach_ready_w :
attach_read_req? attach_ready_r :
attach_ready_w && attach_ready_r; // 挂载在核心选通上，必须读写都允许的情况下可以允许附属选通器读写
//
///////// 复位信号
// 例化SSRAM控制器
sram_controller sram_controller_inst(
.CLOCK(CLOCK40),
.RESET_N(RESET_N),
.sram_avalon_clock(afi_phy_clk),
.sram_avalon_reset_n(afi_phy_rst_n),
.sram_avalon_address(local_addr),
.sram_avalon_writedata(local_wdata),
.sram_avalon_write_n(!local_write_req),
.sram_avalon_read_n(!local_read_req),
.sram_avalon_readdata(local_rdata),
.sram_avalon_readdatavalid(local_rdata_valid),
.sram_avalon_waitrequest(local_waitrequest),
//
.sram_pins_addr(SRAM_ADDR),
.sram_pins_dq(SRAM_DQ),
.sram_pins_ce_n(SRAM_CE_N),
.sram_pins_oe_n(SRAM_OE_N),
.sram_pins_we_n(SRAM_WE_N),
.sram_pins_lb_n(SRAM_LB_N),
.sram_pins_ub_n(SRAM_UB_N)
);
////////////////////////////////////////////////////////////////////////////////////////
mux_ddr_access mux_ddr_access_local_inst(
.afi_phy_clk(afi_phy_clk),
.afi_phy_rst_n(afi_phy_rst_n),
//
.local_address(local_addr),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_ready(!local_waitrequest),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
//.local_refresh_ack,
.local_init_done(RESET_N),
///////////////
// 附属的多路选通器
.wport_clock_6(afi_phy_clk),
.wport_addr_6(attach_addr),
.wport_data_6(attach_wdata),
.wport_req_6(attach_write_req),
.wport_ready_6(attach_ready_w),
.rport_clock_7(afi_phy_clk),
.rport_addr_7(attach_addr),
.rport_data_7(attach_rdata),
.rport_data_valid_7(attach_rdata_valid),
.rport_req_7(attach_read_req),
.rport_ready_7(attach_ready_r),
// MFCC特征搬运 mark[2018/6/6]: 测试CNN状态下，禁止MFCC写入
.wport_clock_4(),
.wport_addr_4(),
.wport_data_4(),
.wport_req_4(),
.wport_ready_4(),
// MFCC特征搬运
.rport_clock_3(),
.rport_addr_3(),
.rport_data_3(),
.rport_data_valid_3(),
.rport_req_3(),
.rport_ready_3(),
// CNN参数配置接口 mark[2018/6/6]: 测试CNN状态下，不能禁止CNN参数写入
.wport_clock_2(CNN_DDR_WRITE_CLK),
.wport_addr_2(CNN_DDR_WRITE_ADDR),
.wport_data_2(CNN_DDR_WRITE_DATA),
.wport_req_2(CNN_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
.wport_ready_2(CNN_DDR_WRITE_READY),
// NPU读写接口
.wport_clock_0(NPU_DDR_WRITE_CLK),
.wport_addr_0(NPU_DDR_WRITE_ADDR),
.wport_data_0(NPU_DDR_WRITE_DATA),
.wport_req_0(NPU_DDR_WRITE_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
.wport_ready_0(NPU_DDR_WRITE_READY),
// NPU读写接口
.rport_clock_1(NPU_DDR_READ_CLK),
.rport_addr_1(NPU_DDR_READ_ADDR),
.rport_data_1(NPU_DDR_READ_DATA),
.rport_data_valid_1(NPU_DDR_READ_DATA_VALID),
.rport_req_1(NPU_DDR_READ_REQ && (RUN_MODE||TEST_MODE||SIMU_MODE)),
.rport_ready_1(NPU_DDR_READ_READY)
);
// 附属多路选通
mux_ddr_access mux_ddr_access_attach_inst(
.afi_phy_clk(afi_phy_clk),
.afi_phy_rst_n(afi_phy_rst_n),
//
.local_address(attach_addr),
.local_write_req(attach_write_req),
.local_read_req(attach_read_req),
.local_burstbegin(attach_burstbegin),
.local_wdata(attach_wdata),
.local_be(attach_be),
.local_size(attach_size),
.local_ready(attach_ready),
.local_rdata(attach_rdata),
.local_rdata_valid(attach_rdata_valid),
//.local_refresh_ack,
.local_init_done(RESET_N),
///////////////
// 测试 写入
.wport_clock_4(sys_clk),
.wport_addr_4(sys_ddr_write_addr),
.wport_data_4(sys_ddr_write_data),
.wport_req_4(sys_ddr_write_data_valid),
.wport_ready_4(sys_ddr_write_data_permitted),
// 测试 读取
.rport_clock_5(sys_clk),
.rport_addr_5(sys_ddr_read_addr),
.rport_data_5(sys_ddr_read_data),
.rport_data_valid_5(sys_ddr_read_data_valid),
.rport_req_5(sys_ddr_read_data_req),
.rport_ready_5(sys_ddr_read_data_permitted),
// 音频信号 写入
.wport_clock_0(),
.wport_addr_0(),
.wport_data_0(),
.wport_req_0(),
.wport_ready_0(),
// MFCC特征 写入
.wport_clock_2(),
.wport_addr_2(),
.wport_data_2(),
.wport_req_2(),
.wport_ready_2()
);
endmodule |
module tb_sdiv;
reg CLOCK100, CLOCK150, CLOCK65, RESET_N;
always #1 CLOCK100 <= ~CLOCK100;
always #1 CLOCK150 <= ~CLOCK150;
always #2 CLOCK65 <= ~CLOCK65;
//////////////////////////////////////////////////////////////////////
initial
begin
#0 CLOCK100 = 0; CLOCK150 = 0; CLOCK65 = 0; RESET_N = 0;
#100 RESET_N = 1;
/// 结束
#200 $stop;
end
///////////////////////////////////////////////////////////////////////
// 测试除法
wire signed [31:0] quotient;
fixed_sdiv fixed_sdiv_inst(.sys_clk(CLOCK100),.sys_rst_n(RESET_N),.numer(32765),.denom(-100),.quotient(quotient));
endmodule |
module tb_cordic;
reg CLOCK100, CLOCK150, CLOCK65, RESET_N;
always #1 CLOCK100 <= ~CLOCK100;
always #1 CLOCK150 <= ~CLOCK150;
always #2 CLOCK65 <= ~CLOCK65;
///////////////////////////////////////////////////////////////////////
// 首先 测试模运算
wire sys_clk = CLOCK100;
wire sys_rst_n = RESET_N;
reg [31:0] mask;
always @(posedge sys_clk)
if(!sys_rst_n)
mask <= 0;
else if(mask<=200)
mask <= mask + 1;
reg signed [63:0] r_in_;
reg r_in_en_;
always @(posedge sys_clk)
if(mask<=200)
begin
r_in_ <= -65536*256;
r_in_en_ <= 0;
end
else if(r_in_<65536*20000)
begin
r_in_ <= r_in_ + 32768;
r_in_en_ <= 1;
end
else
begin
r_in_ <= -65536*20000;
r_in_en_ <= 1;
end
wire signed [31:0] ln_r_out_; // 观察波形，ln(x)模块是11个clock的pipeline
cordic_ln cordic_ln_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.r(r_in_),.ln_r(ln_r_out_));
wire signed [31:0] rho;
wire signed [31:0] phase; // 观察波形，rotation模块是10个clock的pipeline
cordic_rot cordic_rot_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(1024),.src_y(r_in_),.rho(rho),.theta(phase));
// 验证exp指数运算函数
wire signed [31:0] rho_exp;
cordic_exp_rtl cordic_exp_rtl_inst(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_),.rho(rho_exp));
// 验证sigmoid函数
wire signed [31:0] rho_tanh_sigmoid;
cordic_tanh_sigm_rtl cordic_tanh_sigm_rtl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(r_in_), .rho(rho_tanh_sigmoid),.algorithm(2'B10));
///////////////////////////////////////////////////////////////////////////
// 记录
reg [15:0] r_in_en_shifter;
reg signed [31:0] r_in_shifter [0:15];
integer p;
always @(posedge sys_clk)
begin
r_in_en_shifter <= {r_in_en_shifter[14:0], r_in_en_};
//
for(p=1; p<16; p=p+1)
r_in_shifter[p] <= r_in_shifter[p-1];
r_in_shifter[0] <= r_in_;
end
wire signed [31:0] r_in_shifter10 = r_in_shifter[10];
integer fp_ln;
always @(posedge sys_clk)
if(r_in_en_shifter[10])
$fwrite(fp_ln, "%d, %d\n", r_in_shifter[10], ln_r_out_);
//////////////////////////////////////////////////////////////////////
initial
begin
#0 CLOCK100 = 0; CLOCK150 = 0; CLOCK65 = 0; RESET_N = 0; fp_ln = $fopen("./cordic_ln.txt", "w");
#100 RESET_N = 1;
/// 结束
#1500000 $stop; $fclose(fp_ln);
end
endmodule |
module cordic_factor_exp_rom_ip (
address,
clock,
q);
input [7:0] address;
input clock;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({64{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../04_scripts/exp_cordic_factor_Kn.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ln",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 1;
endmodule |
module cordic_factor_exp_rom_ip (
address,
clock,
q);
input [7:0] address;
input clock;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module npu_inst_ram (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [127:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({128{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "../04_scripts/cnn_instruction_rom.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 128,
altsyncram_component.width_b = 128,
altsyncram_component.width_byteena_a = 1;
endmodule |
module npu_inst_ram (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [127:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module cordic_int_part_exp_rom_ip (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../04_scripts/exp_cordic_int_part.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=expi",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule |
module cordic_int_part_exp_rom_ip (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module npu_inst_ram_bak (
address,
clock,
data,
wren,
q);
input [9:0] address;
input clock;
input [127:0] data;
input wren;
output [127:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module npu_inst_ram_bak (
address,
clock,
data,
wren,
q);
input [9:0] address;
input clock;
input [127:0] data;
input wren;
output [127:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=inst",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 128,
altsyncram_component.width_byteena_a = 1;
endmodule |
module alt_pll_ip_core (
inclk0,
c0,
c1,
c2,
c3,
c4);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
endmodule |
module npu_paras_rom (
address,
clock,
q);
input [15:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module sync_dual_clock
#(
parameter WIDTH = 6, // 带同步的数据宽度
parameter SYNC_STAGE = 2 // 同步的级数（级数越多，竞争冒险越少）
)
(
input wire clock_dst,
input wire [WIDTH-1:0] src,
output wire [WIDTH-1:0] dst
);
//
reg [WIDTH-1:0] sync_reg [0:SYNC_STAGE-1];
integer p;
always @(posedge clock_dst)
begin
sync_reg[0] <= src;
for(p=1; p<SYNC_STAGE; p=p+1)
sync_reg[p] <= sync_reg[p-1];
end
assign dst = sync_reg[SYNC_STAGE-1]; // 输出
endmodule |
module gray_enc_1p
#(
parameter WIDTH = 6 // 宽度
)
(
input wire clock, // 时钟
input wire [WIDTH-1:0] src, // 源数据
output reg [WIDTH-1:0] dst // 目标数据
);
//
integer p;
reg [WIDTH-1:0] dst_x;
always @(*)
begin
dst_x[WIDTH-1] = src[WIDTH-1]; // g[N-1] = b[N-1]
for(p=WIDTH-2; p>=0; p=p-1)
begin
dst_x[p] = src[p]^src[p+1]; // g[n] = b[n]^b[n+1] , 0 <= n <= N-2
end
end
// 输出打一拍
always @(posedge clock)
dst <= dst_x;
endmodule |
module dc_fifo
#(
parameter LOG2N = 6, // 这是FIFO深度的对数值
parameter N = (1<<LOG2N), // FIFO的深度
parameter DATA_WIDTH = 32, // 数据宽度
parameter ADDR_WIDTH = LOG2N, // 地址宽度
parameter SYNC_STAGE = 4 // 同步级数
)
(
input wire aclr, // 异步复位
// 写入端口的信号线
input wire wrclock, // 写时钟
input wire [DATA_WIDTH-1:0] data, // 写数据
input wire wrreq, // 写请求
output wire [ADDR_WIDTH-1:0] wrusedw, // 写数据量
output wire wrfull, // 写满标志
output wire wrempty, // 写空标志
// 读取端口的信号线
input wire rdclock, // 读时钟
output reg [DATA_WIDTH-1:0] q, // 读数据
input wire rdreq, // 读请求
output wire [ADDR_WIDTH-1:0] rdusedw, // 读数据量
output wire rdfull, // 读满标志
output wire rdempty // 读空标志
);
/*-------------------------------------------------------------------------*\
signals
\*-------------------------------------------------------------------------*/
// 首先声明一块内存空间
reg [DATA_WIDTH-1:0] dpram [0:N-1]; // 内存空间，试图转换成DPRAM
reg [ADDR_WIDTH:0] wr_addr; // 写入地址
reg [ADDR_WIDTH:0] rd_addr; // 读取地址
/////////////// 然后是gray码
wire [ADDR_WIDTH:0] wr_addr_gray_enc /* synthesis preserve */; // 1-clock pipeline
wire [ADDR_WIDTH:0] rd_addr_gray_enc /* synthesis preserve */; // 1-clock pipeline
// 同步时钟域
wire [ADDR_WIDTH:0] wr_addr_gray_sync /* synthesis preserve */; // write-gray --> read-clock
wire [ADDR_WIDTH:0] rd_addr_gray_sync /* synthesis preserve */; // read-gray --> write-clock
// 最后是格雷码译码
wire [ADDR_WIDTH:0] wr_addr_gray_dec /* synthesis preserve */; // write-addr --> read-clock
wire [ADDR_WIDTH:0] rd_addr_gray_dec /* synthesis preserve */; // read-addr --> write-clock
/*-------------------------------------------------------------------------*\
process
\*-------------------------------------------------------------------------*/
// 首先是写入地址生成
always @(posedge wrclock or posedge aclr)
if(aclr==1)
wr_addr <= 0;
else if(wrreq && !wrfull)
wr_addr <= wr_addr + {{(ADDR_WIDTH){1'B0}}, 1'B1};
// 然后是读取地址生成
always @(posedge rdclock or posedge aclr)
if(aclr==1)
rd_addr <= 0;
else if(rdreq && !rdempty)
rd_addr <= rd_addr + {{(ADDR_WIDTH){1'B0}}, 1'B1};
// 现在是内存的行为
// 写入
always @(posedge wrclock)
if(wrreq && !wrfull)
dpram[wr_addr[ADDR_WIDTH-1:0]] <= data;
// 读取
always @(*)
q = dpram[rd_addr[ADDR_WIDTH-1:0]];
//
// 然后是要生成一些标志信号
assign wrusedw = (wr_addr - rd_addr_gray_dec + N);
assign wrfull = (wrusedw>=(N-SYNC_STAGE-4));
assign wrempty = (wrusedw==0);
assign rdusedw = (wr_addr_gray_dec - rd_addr + N);
assign rdfull = (rdusedw>=(N-SYNC_STAGE-4));
assign rdempty = (rdusedw==0);
/*-------------------------------------------------------------------------*\
instantiation
\*-------------------------------------------------------------------------*/
// 例化格雷码编码模块
gray_enc_1p
#(
.WIDTH(ADDR_WIDTH+1)
)
u0_gray_enc_1p(
.clock(wrclock),
.src(wr_addr),
.dst(wr_addr_gray_enc)
);
gray_enc_1p
#(
.WIDTH(ADDR_WIDTH+1)
)
u1_gray_enc_1p(
.clock(rdclock),
.src(rd_addr),
.dst(rd_addr_gray_enc)
);
// 例化时钟域同步器
sync_dual_clock
#(
.WIDTH(ADDR_WIDTH+1),
.SYNC_STAGE(SYNC_STAGE)
)
u0_sync_dual_clock
(
.clock_dst(rdclock),
.src(wr_addr_gray_enc),
.dst(wr_addr_gray_sync)
);
sync_dual_clock
#(
.WIDTH(ADDR_WIDTH+1),
.SYNC_STAGE(SYNC_STAGE)
)
u1_sync_dual_clock
(
.clock_dst(wrclock),
.src(rd_addr_gray_enc),
.dst(rd_addr_gray_sync)
);
gray_dec_1p
#(
.WIDTH(ADDR_WIDTH+1)
)
u0_gray_dec_1p(
.clock(wrclock),
.src(rd_addr_gray_sync),
.dst(rd_addr_gray_dec)
);
gray_dec_1p
#(
.WIDTH(ADDR_WIDTH+1)
)
u1_gray_dec_1p(
.clock(rdclock),
.src(wr_addr_gray_sync),
.dst(wr_addr_gray_dec)
);
//////////////////////////////////////////////////////////////
endmodule |
module uart_rtl(clock,rst,uart_rxd,rx_en,rx_data,uart_txd,tx_en,tx_data,tx_busy);
input clock,rst; // clock and reset signals
input uart_rxd; // rxd line for uart
output rx_en; // impulse for rx_data_valid
output [7:0] rx_data; // received data
output uart_txd; // txd line for uart
input tx_en; // impulse for tx_data_valid
input [31:0] tx_data; // data to transfer
output reg tx_busy; // busy when transfering
//////////////////////
reg [15:0] base_counter;
reg [3:0] bit_counter;
wire bit_count_zero_flag; // flag that says bit counter is zero
reg ready;
reg bit_in;
always @(posedge clock)
if(rst || !ready)
base_counter <= 16'D0;
else if(bit_count_zero_flag && base_counter==(`UART_ONE_HALF_CYCLE))
begin
base_counter <= 16'D0;
bit_in <= 1'B1;
end
else if(!bit_count_zero_flag && base_counter == (`UART_ONE_CYCLE))
begin
base_counter <= 16'D0;
bit_in <= 1'B1;
end
else
begin
base_counter <= base_counter + 16'D1;
bit_in <= 1'B0;
end
always @(posedge clock)
if(rst || !ready || (bit_counter == 4'D8 && bit_in && uart_rxd==1'B1))
bit_counter <= 4'D0;
else if(bit_in)
bit_counter <= bit_counter + 4'D1;
assign bit_count_zero_flag = (bit_counter==4'D0);
reg [15:0] counter;
wire sample = (counter == (`UART_ONE_CYCLE));
always @(posedge clock)
if(rst)
counter <= 16'D0;
else if(sample)
counter <= 16'D0;
else
counter <= counter + 16'D1;
reg [10:0] recv;
always @(posedge clock)
if(rst)
recv <= 11'H000;
else if(sample)
//recv <= {iRXD,recv[9:1]};
recv <= {recv[9:0],uart_rxd};
reg first_bit;
always @(posedge clock)
if(rst)
first_bit <= 1'B0;
else if(bit_count_zero_flag && base_counter==(`UART_HALF_CYCLE))
first_bit <= uart_rxd;
// ϽµÑصļì²âºÜÖØÒª
reg [3:0] jrxd;
always @(posedge clock)
if(rst)
jrxd <= 4'H0;
else
jrxd <= {jrxd[2:0],uart_rxd};
wire rxd_dn = (jrxd == 4'HC);
reg recv_ones;
always @(posedge clock)
if(rst)
recv_ones <= 1'B0;
else if(recv == 11'H7FF)
recv_ones <= 1'B1;
else
recv_ones <= 1'B0;
reg recv_ones_x;
always @(posedge clock)
recv_ones_x <= recv_ones;
wire recv_ones_up = !recv_ones_x && recv_ones;
always @(posedge clock)
if(rst || recv_ones_up)
ready <= 1'B0;
else if(!ready && rxd_dn)
ready <= 1'B1;
// ÐèÒª ֹͣλ µÄ ¼ì²â
else if(ready && bit_counter==4'D8 && bit_in && uart_rxd==1'B1)
ready <= 1'B0;
reg [9:0] ready_x;
always @(posedge clock)
if(rst)
ready_x <= 10'H000;
else
ready_x <= {ready_x[8:0],ready};
// LSB >> MSB
reg [7:0] rx_datax;
reg [7:0] data_recv;
always @(posedge clock)
if(rst || !ready)
rx_datax <= 8'H00;
else if(ready && bit_in && bit_counter<=4'D7)
rx_datax <= {uart_rxd,rx_datax[7:1]};
always @(posedge clock)
if(rst)
data_recv <= 8'H00;
else if(ready && bit_counter==4'D8 && bit_in)
data_recv <= rx_datax;
assign rx_en = (ready_x==10'H3E0);
assign rx_data = data_recv;
/////////////////////////////////
// °ÑÊý¾ÝLSBÓëMSB½»»»
integer i;
reg [31:0] tx_data_reversed;
always @(*)
for(i=0; i<32; i=i+1)
tx_data_reversed[i] = tx_data[31-i];
// È»ºóÊÇ·¢ËͲ¿·Ö
reg [31:0] tx_cnt;
reg [43:0] tx_shifter;
reg [9:0] tx_bit;
reg [3:0] tx_state;
always @(posedge clock)
if(rst)
begin
tx_shifter <= 44'HFFF_FFFF_FFFF;
tx_cnt <= 0;
tx_bit <= 0;
tx_busy <= 0;
tx_state <= 0;
end
else
begin
case(tx_state)
0: begin
if(tx_en)
begin
tx_shifter <= { 2'B10, tx_data_reversed[7:0], 1'B1,
2'B10, tx_data_reversed[15:8], 1'B1,
2'B10, tx_data_reversed[23:16], 1'B1,
2'B10, tx_data_reversed[31:24], 1'B1
};
tx_busy <= 1;
tx_cnt <= 0;
tx_bit <= 0;
tx_state <= 1;
end
end
1: begin
if(tx_cnt>=`UART_ONE_CYCLE)
begin
tx_cnt <= 0;
if(tx_bit>=43)
begin
tx_busy <= 0;
tx_state <= 0;
tx_bit <= 0;
end
else
begin
tx_bit <= tx_bit + 1;
tx_shifter <= {tx_shifter[42:0], 1'B1};
end
end
else
tx_cnt <= tx_cnt + 1;
end
default: begin
tx_shifter <= 44'HFFF_FFFF_FFFF;
tx_cnt <= 0;
tx_bit <= 0;
tx_busy <= 0;
tx_state <= 0;
end
endcase
end
assign uart_txd = tx_shifter[43];
endmodule |
module uart_wr
#(
parameter UART_DATA_WIDTH = 8, // uart Êý¾Ýλ¿í
parameter UART_ADDR_WIDTH = 2, // endpoint-µØַλ¿í
parameter SYS_UART_DATA_MULT = 4, // system ºÍ cypress uart µÄÊý¾Ýλ¿íµÄ±ÈÀý
parameter SYS_DATA_WIDTH = UART_DATA_WIDTH*SYS_UART_DATA_MULT // system µÄÊý¾Ýλ¿í
)
(
input wire sys_clk, sys_rst_n, // ϵͳʱÖӺ͸´Î»ÐźÅ
/* CYPRESS UART SLAVEFIFO */
input wire uart_sys_clk, uart_sys_rst_n,
input wire uart_rxd,
output wire uart_txd,
/* ºÍÍâ½çµÄ½Ó¿Ú */
input [SYS_DATA_WIDTH-1:0] sys_write_data, // Òª·¢Ë͵½ fifoµÄÊý¾Ý
input sys_write_data_valid, // Òª·¢Ë͵ÄÊý¾ÝÓÐЧ
output sys_write_data_permitted, // ÔÊÐí·¢ËÍÊý¾Ý
output [UART_DATA_WIDTH-1:0] sys_read_data, // ´Ó fifo ÖлñÈ¡µÄÊý¾Ý
input sys_read_data_req, // ´Ó fifo ÖлñÈ¡µÄÊý¾ÝʹÄÜ/ÇëÇó
output sys_read_data_permitted // ÔÊÐí´ÓfifoÖлñÈ¡Êý¾Ý
);
wire logic_uart_write_data_empty;
wire [SYS_DATA_WIDTH-1:0] logic_uart_write_data /* synthesis keep */;
wire logic_uart_write_data_valid = !logic_uart_write_data_empty /* synthesis keep */;
wire logic_uart_write_data_req;
wire [UART_DATA_WIDTH-1:0] logic_uart_read_data /* synthesis keep*/;
wire logic_uart_read_data_valid /* synthesis keep*/;
wire [SYS_DATA_WIDTH-1:0] logic_fifo_write_data /* synthesis keep */;
wire logic_fifo_write_data_valid /* synthesis keep */;
wire [5:0] logic_fifo_write_usedw /* synthesis keep */;
wire logic_fifo_write_full /* synthesis keep */;
wire [UART_DATA_WIDTH-1:0] logic_fifo_read_data /* synthesis keep */;
wire logic_fifo_read_data_req /* synthesis keep */;
wire logic_fifo_read_empty /* synthesis keep */;
// ºÍÍⲿµÄ½Ó¿Ú¸³Öµ
assign logic_fifo_write_data = sys_write_data;
assign logic_fifo_write_data_valid = sys_write_data_valid;
assign sys_write_data_permitted = (logic_fifo_write_usedw[5:3]==0); // Ó¦¸ÃÒªÁô³ö´ó°ë²¿·ÖµÄ¿Õ¼ä£¬ÓÃÓÚ»º³å
assign sys_read_data = logic_fifo_read_data;
assign logic_fifo_read_data_req = sys_read_data_req;
assign sys_read_data_permitted = !logic_fifo_read_empty;
wire uart_tx_busy;
assign logic_uart_write_data_req = !uart_tx_busy && !logic_uart_write_data_empty;
// uart ״̬»ú
uart_rtl uart_rtl_inst(
.clock(uart_sys_clk),
.rst(!uart_sys_rst_n),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
// system
.rx_en(logic_uart_read_data_valid),
.rx_data(logic_uart_read_data),
.tx_en(logic_uart_write_data_req),
.tx_busy(uart_tx_busy),
.tx_data(logic_uart_write_data)
);
// È»ºóÀý»¯1¸ö·¢ËÍÊý¾ÝµÄdcfifo
// alt_fifo_32b_64w
dc_fifo #(
.LOG2N(6),
.DATA_WIDTH(32)
)
alt_fifo_32b_64w_inst(
.aclr(!uart_sys_rst_n),
.wrclock(sys_clk),
.wrreq(logic_fifo_write_data_valid),
.data(logic_fifo_write_data),
.wrfull(logic_fifo_write_full),
.wrusedw(logic_fifo_write_usedw),
.rdclock(uart_sys_clk),
.rdreq(logic_uart_write_data_req),
.q(logic_uart_write_data),
.rdempty(logic_uart_write_data_empty)
);
// ÔÙÊÇÀý»¯Ò»¸öÓÃÓÚ½ÓÊÕslavefifoÀïÃæµÄÊý¾ÝµÄdcfifo
// alt_fifo_8b_4w
dc_fifo #(
.LOG2N(4),
.DATA_WIDTH(8)
)
alt_fifo_8b_4w_inst(
.aclr(!uart_sys_rst_n),
.wrclock(uart_sys_clk),
.wrreq(logic_uart_read_data_valid),
.data(logic_uart_read_data),
.rdclock(sys_clk),
.rdreq(logic_fifo_read_data_req),
.q(logic_fifo_read_data),
.rdempty(logic_fifo_read_empty)
);
endmodule |
module npu_paras_config
#(parameter DATA_WIDTH = 32, // 数据位宽
parameter FRAC_WIDTH = 16, // 小数部分
parameter RAM_LATENCY = 2, // ram的IP核读取需要延时
parameter PARA_BIAS = 32'H00010000 // CNN参数的偏移地址
)
(
input wire clk, rst_n, // 时钟和复位信号
input wire npu_paras_en, // 使能配置
output wire npu_paras_ready, // CNN参数配置空闲
input wire [DATA_WIDTH-1:0] npu_paras_q, // CNN的参数
output reg [DATA_WIDTH-1:0] npu_paras_addr, // CNN参数的地址
// DDR接口
output wire DDR_WRITE_CLK,
output wire [DATA_WIDTH-1:0] DDR_WRITE_ADDR,
output wire [DATA_WIDTH-1:0] DDR_WRITE_DATA,
output wire DDR_WRITE_REQ,
input wire DDR_WRITE_READY
);
reg [31:0] ddr_write_addr;
reg ddr_write_req;
wire ddr_write_ready;
reg [31:0] ddr_write_data;
///////////
assign DDR_WRITE_CLK = clk;
assign DDR_WRITE_ADDR = ddr_write_addr;
assign DDR_WRITE_DATA = ddr_write_data;
assign DDR_WRITE_REQ = ddr_write_req;
assign ddr_write_ready = DDR_WRITE_READY;
wire ddr_write_data_valid = ddr_write_ready && ddr_write_req; // 表示一次数据成功写入
//
// 检测 npu_paras_en 上升沿
reg npu_paras_enx;
always @(posedge clk)
npu_paras_enx <= npu_paras_en;
wire npu_paras_en_up = (!npu_paras_enx && npu_paras_en); // 上升沿
//
reg [3:0] cstate;
reg [31:0] delay;
reg [31:0] total_paras_num; // 所有的参数数量
always @(posedge clk)
if(!rst_n)
begin
cstate <= 0;
delay <= 0;
npu_paras_addr <= 0;
ddr_write_req <= 0; // 撤销DDR写入使能
end
else
begin
case(cstate)
0: begin
if(npu_paras_en_up)
begin
cstate <= 1;
npu_paras_addr <= 0;
delay <= 0;
end
//
ddr_write_req <= 0; // 撤销DDR写入使能
end
// 等待RAM读取完成
1: begin
if(delay>RAM_LATENCY)
begin
cstate <= 2; // 进入逐步读取所有参数
total_paras_num <= npu_paras_q; // 获取参数数量
delay <= 0;
ddr_write_addr <= PARA_BIAS;
end
else
delay <= delay + 1;
///////
ddr_write_req <= 0; // 撤销DDR写入使能
end
// 逐步读取所有的参数
2: begin
if(npu_paras_addr>total_paras_num)
begin
cstate <= 0;
npu_paras_addr <= 0;
delay <= 0;
end
else
begin
cstate <= 3; // 进入读取RAM的等待阶段
npu_paras_addr <= npu_paras_addr + 1;
delay <= 0;
end
ddr_write_req <= 0; // 撤销DDR写入使能
end
// 等待参数读取出来
3: begin
if(delay>RAM_LATENCY)
begin
cstate <= 4; // 进入写入DDR的状态
ddr_write_data <= npu_paras_q;
ddr_write_req <= 1; // 写入DDR，然后等待写入完成
delay <= 0;
end
else
delay <= delay + 1;
end
// 等待参数写入DDR完成
4: begin
if(ddr_write_ready)
begin
ddr_write_req <= 0; // 撤销DDR写入使能
ddr_write_addr <= ddr_write_addr + 1; // DDR写入地址+1
cstate <= 2; // 进入读取下一个参数的任务
end
end
//
default: begin
cstate <= 0;
delay <= 0;
npu_paras_addr <= 0;
ddr_write_req <= 0; // 撤销DDR写入使能
end
endcase
end
/////////////////////////////////////////////////////////
assign npu_paras_ready = (cstate==0);
////////////////////////////////////////////////////
endmodule |
module npu_inst_join
(
input wire npu_inst_clk, npu_inst_rst_n,
input wire [31:0] npu_inst_part,
input wire npu_inst_part_en,
output reg [127:0] npu_inst,
output reg npu_inst_en
);
wire RESETN = npu_inst_rst_n;
// 生成npu_inst/npu_inst_en
// 要用状态机来生成
reg [3:0] npu_inst_state;
reg [31:0] npu_inst_delay; // 延时计数单元，如果超时了，就说明指令传输完成
always @(posedge npu_inst_clk)
if(!RESETN)
begin
npu_inst_state <= 0;
npu_inst <= 0;
npu_inst_en <= 0;
npu_inst_delay <= 0;
end
else
begin
case(npu_inst_state)
0: begin
if(npu_inst_part_en)
begin
npu_inst <= {npu_inst[95:0], npu_inst_part};
npu_inst_en <= 0;
npu_inst_state <= 1;
npu_inst_delay <= 0;
end
end
// 等待超时了，就说明指令传输完成
1: begin
if(npu_inst_part_en)
begin
npu_inst <= {npu_inst[95:0], npu_inst_part};
npu_inst_en <= 0;
npu_inst_delay <= 0;
end
else if(npu_inst_delay>=2000000) // 40ms超时等待机制
begin
npu_inst_en <= 1;
npu_inst_state <= 2;
npu_inst_delay <= 0;
end
else
npu_inst_delay <= npu_inst_delay + 1; // 超时等待计数器++
end
//
2: begin
npu_inst_en <= 0;
npu_inst_state <= 0;
end
default: begin
npu_inst_state <= 0;
npu_inst <= 0;
npu_inst_en <= 0;
npu_inst_delay <= 0;
end
endcase
end
endmodule |
module npu_conv_rtl
#(
parameter Km = 3, // 卷积核row
parameter Kn = 3, // 卷积核col
parameter Ksz = Km * Kn, // 卷积核尺寸
parameter ATlayer = CeilLog2(Ksz)+1, // ceil( log2( Ksz ) + 1 ) // 加法树的层数
parameter ATsize = 1<<(ATlayer), // 加法树的规模
parameter logW = 9, // 支持的图像的最大宽度（列数量）
parameter ADDR_WIDTH = 9, //
parameter DATA_WIDTH = 32, // 数据位宽
parameter FRAC_WIDTH = 16, // 小数部分
parameter DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // 固定的单位1
parameter DATA_ZERO = {DATA_WIDTH{1'B0}}, // 固定的0值
parameter DATA_MINF = {1'B1, {(DATA_WIDTH-1){1'B0}}}, // 负无穷
parameter DATA_PINF = {1'B0, {(DATA_WIDTH-1){1'B1}}} // 正无穷
)
(
clk,
rst,
//
kernel_clr,
kernel_m,
kernel_n,
kernel_data,
kernel_data_valid,
//
width,
read_data,
read_data_valid,
//
write_data,
write_data_valid,
// conv/pool
arith_type,
pool_type,
// 输出一行的数据
pool_opt_col
);
/*-------------------------------------------------------------------*\
functions
\*-------------------------------------------------------------------*/
function integer CeilLog2;
input [31:0] size;
integer i;
begin
CeilLog2 = 1;
for ( i = 1; 2 ** i < size; i = i + 1 )
CeilLog2 = i + 1;
end
endfunction
/*-------------------------------------------------------------------*\
I/O signals
\*-------------------------------------------------------------------*/
input wire clk, rst; // 时钟/复位
input wire kernel_clr; // 清空卷积核
input wire [ADDR_WIDTH-1:0] kernel_m; // 卷积核的横向尺寸
input wire [ADDR_WIDTH-1:0] kernel_n; // 卷积核的纵向尺寸
input wire [DATA_WIDTH-1:0] kernel_data; // 读取到的卷积核数据
input wire kernel_data_valid; // 读取卷积核数据有效
input wire [DATA_WIDTH-1:0] width; // 图像的纵向尺寸
input wire [DATA_WIDTH-1:0] read_data; // 读取到的数据
input wire read_data_valid; // 读取数据有效
//
output reg [DATA_WIDTH-1:0] write_data; // 写入的数据
output reg write_data_valid; // 写入数据有效
// 卷积/池化选项
input wire arith_type; // 0-convolution, 1-pooling
input wire pool_type; // 0-mean_pool, 1-max_pool
//
output reg [DATA_WIDTH-1:0] pool_opt_col;
/*-------------------------------------------------------------------*\
parameters
\*-------------------------------------------------------------------*/
localparam CONV_TYPE = 1'B0;
localparam POOL_TYPE = 1'B1;
localparam MEAN_TYPE = 1'B0;
localparam MAX_TYPE = 1'B1;
/*-------------------------------------------------------------------*\
signals
\*-------------------------------------------------------------------*/
// 生成卷积核数据地址
reg [ADDR_WIDTH-1:0] kernel_row;
reg [ADDR_WIDTH-1:0] kernel_col;
reg [ADDR_WIDTH-1:0] kernel_addr; // 卷积核地址
reg [DATA_WIDTH-1:0] kernel_datax; // 读取到的卷积核数据
reg kernel_data_validx; // 读取卷积核数据有效
//
reg signed [DATA_WIDTH-1:0] kernel_q [0:Ksz-1]; // 卷积核里面的数据
//wire signed [DATA_WIDTH-1:0] kernel_qs [0:Ksz-1]; // 卷积核里面的数据
reg signed [DATA_WIDTH-1:0] field_q [0:Ksz-1]; // 卷积域里面的数据
//wire signed [DATA_WIDTH-1:0] field_qs [0:Ksz-1]; // 卷积域里面的数据
reg field_q_en;
reg [DATA_WIDTH-1:0] field_con_idx[0:Km-1]; // 互联网络
//wire [DATA_WIDTH-1:0] field_con_idx_s[0:Km-1];// = field_con_idx[0];
reg signed [DATA_WIDTH-1:0] field_data [0:Km-1]; // 卷积域里面的数据【源】
//wire signed [DATA_WIDTH-1:0] field_data_s[0:Km-1]; // 卷积域里面的数据【源】
reg field_data_valid ; // 数据源有效
// 然后是进行p2p乘法
reg signed [DATA_WIDTH-1:0] field_mult [0:Ksz-1]; // 点对点乘法
reg signed [2*DATA_WIDTH-1:0] field_mults [0:Ksz-1]; // 点对点乘法
reg field_zero [0:Ksz-1]; // 点对点乘法 ==0
//wire signed [DATA_WIDTH-1:0] field_mult_s[0:Ksz-1]; // 点对点乘法
reg field_mult_en;
reg field_mults_en;
// 求和
reg signed [DATA_WIDTH-1:0] ATnode [0:ATsize-1]; // 加法树
//wire signed [DATA_WIDTH-1:0] ATnodes [0:ATsize-1]; // 加法树
reg ATnode_en [0:ATlayer-1];// 加法树节点数据有效使能
//wire ATnode_ens[0:ATlayer-1];// 加法树节点数据有效使能
//
reg [DATA_WIDTH-1:0] ConvResRow; // 卷积结果的行计数
reg [DATA_WIDTH-1:0] ConvResCol; // 卷积结果的列计数
reg [DATA_WIDTH-1:0] ConvCycRow; // 卷积结果的行计数(0 ~ kernel_m-1)内循环计数
reg [DATA_WIDTH-1:0] ConvCycCol; // 卷积结果的列计数(0 ~ kernel_n-1)内循环计数
// pooling
reg signed [DATA_WIDTH-1:0] div_numer; // divider的分子部分
reg signed [DATA_WIDTH-1:0] div_denom; // divider的分母部分
wire signed [DATA_WIDTH-1:0] div_quotient; // 商
wire div_dst_en; // 除法器输出有效
reg div_src_en; // 除法器输入有效
// 输出数据有效
wire write_data_validx;
wire [DATA_WIDTH-1:0] opt_colx;
reg pool_opt_col_rdy; // 除法结果
// 这里是shifter taps
reg [DATA_WIDTH-1:0] ram_wptr ; // 指向正在写入的ram
reg [DATA_WIDTH-1:0] ram_wptr_sync [0:1] ; // 同步
reg ram_wren_sync [0:1] ; // 同步
reg [DATA_WIDTH-1:0] ram_rptr ; // 指向正在读取的ram // ram_wptr同步3个clock
reg ram_rden ; //
reg [DATA_WIDTH-1:0] ram_waddr ; // 写入ram的地址
wire signed [DATA_WIDTH-1:0] ram_data [0:Km-1]; // 写入ram的数据
wire [DATA_WIDTH-1:0] ram_wraddr [0:Km-1]; // 写入ram的地址
wire ram_wrreq [0:Km-1]; // 写入ram的请求
wire signed [DATA_WIDTH-1:0] ram_q [0:Km-1]; // 读取ram的数据
wire [DATA_WIDTH-1:0] ram_rdaddr [0:Km-1]; // 读取ram的地址
wire ram_rdreq [0:Km-1]; // 读取ram的请求
/*-------------------------------------------------------------------*\
timing
//
// Ex. width == 45, kernel_m == 3, kernel_n == 3
clk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_
rst : ___|-----|________________________________________________________________________________________________________________________
read_data : _________________| d0| d1| d2| d3| d4| d5| d6| d7| d8| d9|d10|d11|...|d33|d34|d35|d36|d37|d38|d39|d40|d41|d42|d43|d44|
read_data_valid : _________________|------------------------------------------------...------------------------------------------------|_____
ram_wptr : |0 | 1
ram_wraddr[0] : _____|0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11|...| 33| 34| 35| 36| 37| 38| 39| 40| 41| 42| 43| 44| 0
ram_rdaddr[0] : _____|44 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10|...| 32| 33| 34| 35| 36| 37| 38| 39| 40| 41| 42| 43| 44
ram_q[0] : _____________| q44 | q0| q1| q2| q3| q4| q5| q6| q7| q8|...|q30|q31|q32|q33|q34|q35|q36|q37|q38|q39|q40|q41|q42|q43|q44
ram_wptr_sync[0]: _________|0 | 1
ram_wptr_sync[0]: _____________|0 | 1
ram_rden : _____________________________|------------------------------------------------...------------------------------------------------|_____
ram_rptr : _________________|0 | 1
field_con_idx[0]: _________________| 1 | 2
field_con_idx[1]: _________________| 2 | 3
field_con_idx[2]: _________________| 3 | 4
// 要写入卷积域的数据
field_data[0] : _____________________|q44 | q0| q1| q2| q3| q4| q5| q6| q7| q8|...|q30|q31|q32|q33|q34|q35|q36|q37|q38|q39|q40|q41|q42|q43|q44
field_data_valid: _________________________________|------------------------------------------------...------------------------------------------------|_____
// 卷积域中的数据
field_q[x] : _________________________|q44 | q0| q1| q2| q3| q4| q5| q6| q7| q8|...|q30|q31|q32|q33|q34|q35|q36|q37|q38|q39|q40|q41|q42|q43|q44
field_q_en : _____________________________________|------------------------------------------------...------------------------------------------------|_____
// 点对点乘法
field_mults[x] : _____________________________|m44 | m0| m1| m2| m3| m4| m5| m6| m7| m8|...|m30|m31|m32|m33|m34|m35|m36|m37|m38|m39|m40|m41|m42|m43|m44
field_mults_en : _________________________________________|------------------------------------------------...------------------------------------------------|_____
field_mult[x] : _________________________________|m44 | m0| m1| m2| m3| m4| m5| m6| m7| m8|...|m30|m31|m32|m33|m34|m35|m36|m37|m38|m39|m40|m41|m42|m43|m44
field_mult_en : _____________________________________________|------------------------------------------------...------------------------------------------------|_____
// 加法树
ATnode[#L0] : _________________________________________________| m0| m1| m2| m3| m4| m5| m6| m7| m8|...|m30|m31|m32|m33|m34|m35|m36|m37|m38|m39|m40|m41|m42|m43|m44
ATnode[#L1] : _____________________________________________________| m0| m1| m2| m3| m4| m5| m6| m7| m8|...|m30|m31|m32|m33|m34|m35|m36|m37|m38|m39|m40|m41|m42|m43|m44
...
ATnode[#L4] : _________________________________________________________________| m0| m1| m2| m3| m4| m5| m6| m7| m8|...|m30|m31|m32|m33|m34|m35|m36|m37|m38|m39|m40|m41|m42|m43|m44
ATnode_en[#L4] : _________________________________________________________________|------------------------------------------------...------------------------------------------------|_____
// 行列计数
ConvResCol : _____|0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11|...| 33| 34| 35| 36| 37| 38| 39| 40| 41| 42| 43| 44| 0
ConvResRow : _____|0 | 1
ConvCycCol : _____|0 | 1 | 2 | 0 | 1 | 2 | 0 | 1 | 2 | 0 | 1 | 2 |...| 0 | 1 | 2 | 0 | 1 | 2 | 0 | 1 | 2 | 0 | 1 | 2 | 0
ConvCycRow : _____|0 | 1
\*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*\
process
\*-------------------------------------------------------------------*/
// 生成卷积核数据地址
always @ ( posedge clk )
if ( kernel_clr == 1'B1 )
begin
kernel_row <= 0;
kernel_col <= 0;
end
else if ( kernel_data_valid == 1'B1 )
begin
if ( kernel_col >= ( kernel_n - 1 ) )
begin
kernel_row <= kernel_row + 1;
kernel_col <= 0;
end
else
kernel_col <= kernel_col + 1;
end
// 只能打一排了
always @ ( posedge clk )
begin
kernel_addr <= ( kernel_row * Kn + kernel_col );
kernel_datax <= kernel_data;
kernel_data_validx <= kernel_data_valid;
end
// 首先是卷积核
genvar ki;
genvar kj;
generate
for ( ki = 0; ki < Km; ki = ki + 1 )
begin : conv_kernel_row
for ( kj = 0; kj < Kn; kj = kj + 1 )
begin : conv_kernel_col
always @ ( posedge clk )
begin
if ( kernel_clr == 1'B1 )
begin
if ( arith_type == CONV_TYPE )
kernel_q[ki*Kn+kj] <= DATA_ZERO;
else if ( arith_type == POOL_TYPE && pool_type == MEAN_TYPE )
begin
if (( ki < kernel_m ) && ( kj < kernel_n ))
kernel_q[ki*Kn+kj] <= DATA_UNIT;
else
kernel_q[ki*Kn+kj] <= DATA_ZERO;
end
else if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
kernel_q[ki*Kn+kj] <= DATA_UNIT;
end
else if ( kernel_addr == ( ki*Kn+kj ) && kernel_data_validx == 1'B1)
kernel_q[ki*Kn+kj] <= kernel_datax;
end
//
//assign kernel_qs[ki*Kn+kj] = kernel_q[ki*Kn+kj];
end
end
endgenerate
// 然后是ram操作，构造shifter-taps
// 生成wraddr
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
ram_waddr <= 0;
ram_wptr <= 0;
end
else if ( read_data_valid )
begin
if ( ram_waddr >= ( width - 1) )
begin
ram_waddr <= 0;
//
if ( ram_wptr >= (kernel_m - 1) )
ram_wptr <= 0;
else
ram_wptr <= ram_wptr + 1'B1;
end
else
ram_waddr <= ram_waddr + 1;
end
end
// 同步3个clock
always @ ( posedge clk )
begin
//
ram_rden <= ram_wren_sync[1];
ram_wren_sync[1] <= ram_wren_sync[0];
ram_wren_sync[0] <= read_data_valid;
//
ram_rptr <= ram_wptr_sync[1];
ram_wptr_sync[1] <= ram_wptr_sync[0];
ram_wptr_sync[0] <= ram_wptr;
//
end
// ram_q[x] ===[Km, ram_rptr]==> field_data[y]
// x = (ram_rptr - y + kernel_m)%kernel_m
genvar y;
generate
for ( y = 0; y < Km; y = y + 1 )
begin : connect
always @ ( posedge clk )
begin : index
if ( y < kernel_m )
begin
if ((( ram_wptr_sync[1] + kernel_m - y ) == kernel_m ) || (( ram_wptr_sync[1] + kernel_m - y ) == ( kernel_m <<< 1 )))
field_con_idx[y] <= 0;
else if((( ram_wptr_sync[1] + kernel_m - y ) > kernel_m ) && (( ram_wptr_sync[1] + kernel_m - y ) < ( kernel_m <<< 1 )))
field_con_idx[y] <= ( ram_wptr_sync[1] + kernel_m - y - kernel_m );
else
field_con_idx[y] <= ( ram_wptr_sync[1] + kernel_m - y );
end
else
field_con_idx[y] <= 0;
end
//
//assign field_con_idx_s[y] = field_con_idx[y];
//assign field_data_s[y] = field_data[y];
//
always @ ( posedge clk )
begin : value
//
field_data[y] <= ram_q[field_con_idx[y]];
end
end
endgenerate
always @ ( posedge clk )
field_data_valid <= ram_rden;
// 生成卷积域
genvar convi;
genvar convj;
generate
for ( convi = 0; convi < Km; convi = convi + 1 )
begin : conv_row
for ( convj = 0; convj < Kn; convj = convj + 1 )
begin : conv_col
begin : construct
if ( convj == 0 )
// 首先是【0】列
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
field_q[convi*Kn+convj] <= DATA_MINF;
else
field_q[convi*Kn+convj] <= DATA_ZERO;
end
else
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
begin
if ( field_data_valid == 1'B1 && convi < kernel_m )
field_q[convi*Kn+convj] <= field_data[convi];
else if ( field_data_valid == 1'B1 && convi >= kernel_m )
field_q[convi*Kn+convj] <= DATA_MINF;
end
else
begin
if ( field_data_valid == 1'B1 )
field_q[convi*Kn+convj] <= field_data[convi];
end
end
end
else
begin
// 然后是【1...Kn-1】列
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
field_q[convi*Kn+convj] <= DATA_MINF;
else
field_q[convi*Kn+convj] <= DATA_ZERO;
end
else
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
begin
if ( field_data_valid == 1'B1 && convj < kernel_n )
field_q[convi*Kn+convj] <= field_q[convi*Kn+convj-1];
else if ( field_data_valid == 1'B1 && convj >= kernel_n )
field_q[convi*Kn+convj] <= DATA_MINF;
end
else
begin
if ( field_data_valid == 1'B1 )
field_q[convi*Kn+convj] <= field_q[convi*Kn+convj-1];
end
end
end
end
//
//assign field_qs[convi*Kn+convj] = field_q[convi*Kn+convj];
end
end
end
endgenerate
//
always @ ( posedge clk )
field_q_en <= field_data_valid;
// 然后是进行点对点乘法
genvar pts;
generate
for ( pts = 0; pts < Ksz; pts = pts + 1 )
begin : multi
// 先计算乘法
always @ ( posedge clk )
begin
field_mults[pts] <= field_q[pts] * kernel_q[pts];
field_zero[pts] <= ( kernel_q[pts] == DATA_ZERO );
end
// 然后移位寄存
always @ ( posedge clk )
begin
field_mult[pts] <= ( field_zero[pts] == 1'B1 )? DATA_ZERO : field_mults[pts][DATA_WIDTH+FRAC_WIDTH-1:FRAC_WIDTH];
end
// 调试用
//assign field_mult_s[pts] = field_mult[pts];
end
endgenerate
always @ ( posedge clk )
begin
field_mult_en <= field_mults_en;
field_mults_en <= field_q_en;
end
// 加法树
genvar at_layer;
genvar at_node_idx;
generate
for ( at_layer = 0; at_layer < ATlayer; at_layer = at_layer + 1 )
begin : ATtree
//
//assign ATnode_ens[ at_layer ] = ATnode_en[ at_layer ];
// 对于第0层，输入点对点乘法结果
if ( at_layer == 0 )
begin
for ( at_node_idx = 0; at_node_idx < ( ATsize >> ( 1 + at_layer )); at_node_idx = at_node_idx + 1 )
begin : layer_0
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
if ( arith_type == CONV_TYPE )
ATnode[ at_node_idx ] <= DATA_ZERO;
else if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE)
ATnode[ at_node_idx ] <= DATA_MINF;
else
ATnode[ at_node_idx ] <= DATA_ZERO;
end
else if ( at_node_idx < Ksz && field_mult_en == 1'B1 )
ATnode[ at_node_idx ] <= field_mult[ at_node_idx ];
end
//assign ATnodes[ at_node_idx ] = ATnode[ at_node_idx ];
end
always @ ( posedge clk )
ATnode_en[ at_layer ] <= field_mult_en;
end
// 对于其它层
/*
*/
else
begin
for ( at_node_idx = 0; at_node_idx < ( ATsize >> ( 1 + at_layer )); at_node_idx = at_node_idx + 1 )
begin : layer_else
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
ATnode[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ] <= DATA_MINF;
else
ATnode[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ] <= DATA_ZERO;
end
else
begin
if ( arith_type == POOL_TYPE && pool_type == MAX_TYPE )
ATnode[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ] <=
( ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 )] > ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 ) +1 ] )?
ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 )] :
ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 ) +1 ];
else
ATnode[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ] <=
ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 )] +
ATnode[ ATsize - ( ATsize >> ( at_layer - 1 )) + ( at_node_idx <<< 1 ) +1 ];
end
end
//assign ATnodes[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ] = ATnode[ ATsize - ( ATsize >> ( at_layer )) + at_node_idx ];
end
always @ ( posedge clk )
ATnode_en[ at_layer ] <= ATnode_en[ at_layer - 1 ];
end
end
endgenerate
// 输入定点除法器，实现pool（mean-pool）
always @ ( posedge clk )
begin
if ( rst == 1'B1 && arith_type == POOL_TYPE )
begin
div_numer <= width;
// mean_pool要 / 卷积核尺度
div_denom <= kernel_n;
div_src_en <= 1'B1;
end
else
begin
div_numer <= ATnode[ ATsize - ( ATsize >> ( ATlayer - 1 ) ) ];
// mean_pool要 / 卷积核尺度
div_denom <= ( arith_type == POOL_TYPE && pool_type == MEAN_TYPE )? {32'D0, ( kernel_m * kernel_n ), {FRAC_WIDTH{1'B0}}} : DATA_UNIT;
div_src_en <= ATnode_en[ ATlayer - 1 ];
end
end
// 统计输出的行列计数
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
ConvResRow <= 0;
ConvResCol <= 0;
end
// 如果AT加法树结果有效，行列计数
else if ( pool_opt_col_rdy == 1'B1 && div_dst_en == 1'B1 )
begin
if ( ConvResCol >= ( width - 1 ) )
begin
ConvResRow <= ConvResRow + 1;
ConvResCol <= 0;
end
else
ConvResCol <= ConvResCol + 1;
end
end
// 统计输出的循环行列计数
always @ ( posedge clk )
begin
if ( rst == 1'B1 )
begin
ConvCycRow <= 0;
ConvCycCol <= 0;
end
// 如果AT加法树结果有效，行列计数
else if ( pool_opt_col_rdy == 1'B1 && div_dst_en == 1'B1 )
begin
if ( ConvCycCol >= ( kernel_n - 1 ) || ConvResCol >= ( width - 1 ))
ConvCycCol <= 0;
else
ConvCycCol <= ConvCycCol + 1;
//
if ( ConvResCol >= ( width - 1 ) )
begin
//
if ( ConvCycRow >= ( kernel_m - 1 ))
ConvCycRow <= 0;
else
ConvCycRow <= ConvCycRow + 1;
end
end
end
// 最后生成卷积结果
// 过滤掉无效的卷及结果
assign write_data_validx = ( arith_type == CONV_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvResCol >= ( kernel_n - 1 )) && ( ConvResRow >= ( kernel_m - 1 )) ) :
( arith_type == POOL_TYPE )? ( pool_opt_col_rdy && div_dst_en && ( ConvCycCol == ( kernel_n - 1 )) && ( ConvCycRow == ( kernel_m - 1 )) ) :
1'B0;
// 寄存器打一拍输出
always @ ( posedge clk )
begin
write_data <= div_quotient;
write_data_valid <= write_data_validx;
end
// 因为pooloing池化运算，需要先计算最后输出的数据列数
always @ ( posedge clk )
if ( rst == 1'B1 )
begin
if ( arith_type == POOL_TYPE )
pool_opt_col_rdy <= 1'B0;
else
pool_opt_col_rdy <= 1'B1;
end
else if ( pool_opt_col_rdy == 1'B0 && div_dst_en == 1'B1 && arith_type == POOL_TYPE )
begin
pool_opt_col <= div_quotient>>>FRAC_WIDTH;
pool_opt_col_rdy <= 1'B1;
end
/*-------------------------------------------------------------------*\
instances
\*-------------------------------------------------------------------*/
// 统计输出的一行数量
// 定点除法器
fixed_sdiv u0_fixed_sdiv
(
.sys_clk ( clk ),
.sys_rst_n ( !rst ),
.numer ( div_numer ),
.denom ( div_denom ),
.quotient ( div_quotient ),
.src_en ( div_src_en ),
.dst_en ( div_dst_en )
);
// 偏上缓存
genvar rami;
generate
for ( rami = 0; rami < Km; rami = rami + 1 )
begin : ram
//
assign ram_wraddr[rami] = ram_waddr;
assign ram_data[rami] = read_data;
assign ram_wrreq[rami] = read_data_valid && ( ram_wptr == rami );
assign ram_rdreq[rami] = 1'B1;
assign ram_rdaddr[rami] = ( ram_wraddr[rami]==0 )? ( width - 1'B1 ) : ( ram_wraddr[rami] - 1'B1 );
dpram_2p
#(
.LOG2N ( logW ),
.DATA_WIDTH ( DATA_WIDTH )
) u_dpram_2p
(
.wrclock ( clk ),
.data ( ram_data[rami] ),
.wrreq ( ram_wrreq[rami] ),
.wraddr ( ram_wraddr[rami] ),
.rdclock ( clk ),
.q ( ram_q[rami] ),
.rdreq ( ram_rdreq[rami] ),
.rdaddr ( ram_rdaddr[rami] )
);
end
endgenerate
endmodule |
module npu_inst_fsm
#(parameter DATA_WIDTH = 32, // 数据位宽
parameter FRAC_WIDTH = 16, // 小数部分
parameter RAM_LATENCY = 2, // ram的IP核读取需要延时
parameter MAC_LATENCY = 2, // ram的IP核读取需要延时
parameter DIV_LATENCY = 50, // 除法器的延时
parameter DMI_LATENCY = 2, // 除法器的延时
parameter DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // 固定的单位1
parameter DATA_ZERO = {DATA_WIDTH{1'B0}}, // 固定的0值
parameter INST_WIDTH = 128 // 指令的长度
)
(
input wire clk, rst_n, // 时钟和复位信号
input wire [INST_WIDTH-1:0] npu_inst_q, // CNN的指令
output reg [DATA_WIDTH-1:0] npu_inst_addr, // CNN的指令地址
input wire npu_inst_start, // 指令使能标志
output reg npu_inst_ready, // 指令执行完成标志
output reg [DATA_WIDTH-1:0] npu_inst_time, // 计量指令执行时间
// DDR接口
output wire DDR_WRITE_CLK,
output wire [DATA_WIDTH-1:0] DDR_WRITE_ADDR,
output wire [DATA_WIDTH-1:0] DDR_WRITE_DATA,
output wire DDR_WRITE_REQ,
input wire DDR_WRITE_READY,
output wire DDR_READ_CLK,
output wire [DATA_WIDTH-1:0] DDR_READ_ADDR,
output wire DDR_READ_REQ,
input wire DDR_READ_READY,
input wire [DATA_WIDTH-1:0] DDR_READ_DATA,
input wire DDR_READ_DATA_VALID
);
// 使用状态机控制
reg [3:0] cstate;
reg [10:0] delay;
reg npu_inst_parser_en;
wire npu_inst_parser_ready;
always @(posedge clk)
if(!rst_n)
begin
cstate <= 0;
npu_inst_parser_en <= 0;
end
else
begin
case(cstate)
0: begin
if(npu_inst_start)
begin
npu_inst_addr <= 0;
cstate <= 1;
delay <= 0;
npu_inst_parser_en <= 0;
end
end
1: begin
if(delay>=3)
begin
if(npu_inst_q==128'D0) // NOP指令
begin
cstate <= 0;
npu_inst_parser_en <= 0;
end
else if(npu_inst_parser_ready)
begin
cstate <= 2;
npu_inst_parser_en <= 1;
end
end
else
delay <= delay + 1;
end
2: begin
npu_inst_parser_en <= 0; // 关断使能信号
cstate <= 5;
delay <= 0;
end
// 延时一下
5: begin
if(delay>=5)
cstate <= 3;
else
delay <= delay + 1;
end
3: begin
if(npu_inst_parser_ready)
begin
cstate <= 4;
npu_inst_parser_en <= 0;
end
end
4: begin
npu_inst_addr <= npu_inst_addr + 1;
cstate <= 1;
delay <= 0;
end
default: begin
cstate <= 0;
npu_inst_parser_en <= 0;
end
endcase
end
//
always @(posedge clk)
npu_inst_ready <= (cstate==0);
always @(posedge clk)
if(npu_inst_start)
npu_inst_time <= 0;
else if(!npu_inst_ready)
npu_inst_time <= npu_inst_time + 1;
// CNN指令执行
npu_inst_excutor npu_inst_excutor_inst(
.clk(clk),
.rst_n(rst_n),
.npu_inst(npu_inst_q),
.npu_inst_en(npu_inst_parser_en),
.npu_inst_ready(npu_inst_parser_ready),
// DDR
.DDR_WRITE_CLK(DDR_WRITE_CLK),
.DDR_WRITE_ADDR(DDR_WRITE_ADDR),
.DDR_WRITE_DATA(DDR_WRITE_DATA),
.DDR_WRITE_REQ(DDR_WRITE_REQ),
.DDR_WRITE_READY(DDR_WRITE_READY),
.DDR_READ_CLK(DDR_READ_CLK),
.DDR_READ_ADDR(DDR_READ_ADDR),
.DDR_READ_REQ(DDR_READ_REQ),
.DDR_READ_READY(DDR_READ_READY),
.DDR_READ_DATA(DDR_READ_DATA),
.DDR_READ_DATA_VALID(DDR_READ_DATA_VALID)
);
endmodule |
module dpram_2p
#(
parameter LOG2N = 6, // 这是FIFO深度的对数值
parameter N = (1<<LOG2N), // FIFO的深度
parameter DATA_WIDTH = 32, // 数据宽度
parameter ADDR_WIDTH = LOG2N // 地址宽度
)
(
input wire aclr, // 异步复位
// 写入端口的信号线
input wire wrclock, // 写时钟
input wire [DATA_WIDTH-1:0] data, // 写数据
input wire wrreq, // 写请求
input wire [ADDR_WIDTH-1:0] wraddr, // 写地址
// 读取端口的信号线
input wire rdclock, // 读时钟
output reg [DATA_WIDTH-1:0] q, // 读数据
input wire rdreq, // 读请求
input wire [ADDR_WIDTH-1:0] rdaddr // 读地址
);
/*-------------------------------------------------------------------------*\
signals
\*-------------------------------------------------------------------------*/
// 首先声明一块内存空间
reg [DATA_WIDTH-1:0] dpram [0:N-1]; // 内存空间，试图转换成DPRAM
reg [ADDR_WIDTH-1:0] wraddrx; // 写入地址
reg [DATA_WIDTH-1:0] datax;
reg wrreqx;
reg rdreqx;
reg [ADDR_WIDTH-1:0] rdaddrx; // 读取地址
/*-------------------------------------------------------------------------*\
timing
\*-------------------------------------------------------------------------*/
/*
for writing:
wrclock _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|-
wraddr ____| a1| a2| a3| a4| a5| a6| a7| a8| a9|________
data ____| d1| d2| d3| d4| d5| d6| d7| d8| d9|________
wrreq ____|-----------------------------------|_______
for reading:
rdclock _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|-
rdaddr ____| a1| a2| a3| a4| a5| a6| a7| a8| a9|________
rdreq ____|-----------------------------------|_______
rdaddrx _________| a1| a2| a3| a4| a5| a6| a7| a8| a9|________
rdreqx _________|-----------------------------------|_______
q _________| d1| d2| d3| d4| d5| d6| d7| d8| d9|___
*/
/*-------------------------------------------------------------------------*\
process
\*-------------------------------------------------------------------------*/
// 首先是写入地址生成
always @(posedge wrclock or posedge aclr)
if(aclr==1)
begin
wraddrx <= 0;
wrreqx <= 0;
datax <= 0;
end
else
begin
wraddrx <= wraddr;
wrreqx <= wrreq;
datax <= data;
end
// 然后是读取地址生成
always @(posedge rdclock or posedge aclr)
if(aclr==1)
begin
rdaddrx <= 0;
rdreqx <= 0;
end
else
begin
rdaddrx <= rdaddr;
rdreqx <= rdreq;
end
// 现在是内存的行为
// 写入
always @(posedge wrclock)
if(wrreqx==1)
dpram[wraddrx[ADDR_WIDTH-1:0]] <= datax;
// 读取
always @(posedge rdclock)
if(rdreqx==1)
q <= dpram[rdaddrx[ADDR_WIDTH-1:0]];
//
//////////////////////////////////////////////////////////////
endmodule |
module fixed_sdiv
#(parameter DATA_WIDTH = 32, // 数据位宽
parameter FRAC_WIDTH = 16, // 小数部分
parameter DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // 固定的单位1
parameter DATA_ZERO = {DATA_WIDTH{1'B0}}, // 固定的0值
parameter PERIOD = ((DATA_WIDTH+FRAC_WIDTH)>>1)
)
(
input wire sys_clk, sys_rst_n, // 模块的时钟、复位信号
//
input wire [DATA_WIDTH-1:0] numer,
input wire [DATA_WIDTH-1:0] denom,
input wire src_en,
output reg [DATA_WIDTH-1:0] quotient,
output reg dst_en
);
// 首先输入的翻转
wire [DATA_WIDTH-1:0] numer_pos;
wire [DATA_WIDTH-1:0] denom_pos;
assign numer_pos = numer[DATA_WIDTH-1]? (~numer+1) : numer;
assign denom_pos = denom[DATA_WIDTH-1]? (~denom+1) : denom;
// 迭代运算
// 考虑到radix-2算法太消耗面积，而且总的clock周期太多
// 这里采用radix-4的算法
reg src_enx [0:PERIOD];
reg [2*DATA_WIDTH-1:0] denom_tmp [0:PERIOD];
reg [2*DATA_WIDTH-1:0] numer_tmp [0:PERIOD];
reg result_polar [0:PERIOD];
reg [2*DATA_WIDTH-1:0] judge_0 [0:PERIOD]; // 比较numer_tmp和denom_tmp
reg [2*DATA_WIDTH-1:0] judge_1 [0:PERIOD]; // 比较numer_tmp和denom_tmp
reg [2*DATA_WIDTH-1:0] judge_2 [0:PERIOD]; // 比较numer_tmp和denom_tmp
reg [2*DATA_WIDTH-1:0] judge_3 [0:PERIOD]; // 比较numer_tmp和denom_tmp
reg [3:0] _judge_ [0:PERIOD]; // 比较numer_tmp和denom_tmp
// 要将比较器和减法器实现资源复用（FPGA内比较器就是减法器）
integer q;
always @(*)
begin
for(q=0; q<PERIOD; q=q+1)
begin
judge_0[q] = ({numer_tmp[q], 2'B00}-denom_tmp[q]);
judge_1[q] = ({numer_tmp[q], 2'B00}-(denom_tmp[q]<<1));
judge_2[q] = ({numer_tmp[q], 2'B00}-(denom_tmp[q] + (denom_tmp[q]<<1)));
judge_3[q] = ({numer_tmp[q], 2'B00}-(denom_tmp[q]<<2));
_judge_[q] = {judge_3[q][2*DATA_WIDTH-1], judge_2[q][2*DATA_WIDTH-1], judge_1[q][2*DATA_WIDTH-1], judge_0[q][2*DATA_WIDTH-1]};
end
end
//assign result_polar = denom[DATA_WIDTH-1]^numer[DATA_WIDTH-1];
integer p;
always @(posedge sys_clk)
begin
// 复位的时候不要动，控制功耗
if(!sys_rst_n)
begin
for(p=PERIOD; p>=0; p=p-1)
begin
result_polar[p] <= 0;
numer_tmp[p] <= 0;
denom_tmp[p] <= 0;
end
end
//
else
begin
result_polar[0] <= denom[DATA_WIDTH-1]^numer[DATA_WIDTH-1];
numer_tmp[0] <= {8'H0, numer_pos};
denom_tmp[0] <= {8'H0, denom_pos, {(DATA_WIDTH){1'B0}}};
// 迭代
for(p=PERIOD; p>=1; p=p-1)
begin
case(_judge_[p-1])
4'B1000: numer_tmp[p] <= judge_2[p-1]+3;
4'B1100: numer_tmp[p] <= judge_1[p-1]+2;
4'B1110: numer_tmp[p] <= judge_0[p-1]+1;
4'B1111: numer_tmp[p] <= {numer_tmp[p-1], 2'B00};
default: numer_tmp[p] <= {numer_tmp[p-1], 2'B00};
endcase
//
denom_tmp[p] <= denom_tmp[p-1];
result_polar[p] <= result_polar[p-1];
end
end
end
always @(posedge sys_clk)
begin
if(result_polar[PERIOD])
quotient <= ~numer_tmp[PERIOD]+1;
else
quotient <= numer_tmp[PERIOD];
end
integer dp;
always @ ( posedge sys_clk)
begin
for(dp=1; dp<=PERIOD; dp=dp+1)
src_enx[dp] <= src_enx[dp-1];
src_enx[0] <= src_en;
dst_en <= src_enx[PERIOD];
end
endmodule |
module cmd_parser
#(
parameter UART_DATA_WIDTH = 8, // uart 数据位宽
parameter UART_ADDR_WIDTH = 2, // endpoint-地址位宽
parameter SYS_UART_DATA_MULT = 4, // system 和 cypress uart 的数据位宽的比例
parameter SYS_DATA_WIDTH = UART_DATA_WIDTH*SYS_UART_DATA_MULT // system 的数据位宽
)
(
output wire receive_valid_cmd, // 收到有效命令
input wire sys_clk, sys_rst_n, // 系统时钟和复位信号
input wire [5:1] sys_key_fn, // 按键，用于调控！
//
input wire [SYS_DATA_WIDTH-1:0] adc_ddr_write_addr, // adc要写入ddr的地址
input wire [SYS_DATA_WIDTH-1:0] adc_ddr_write_addr_mask, // adc要写入ddr的地址掩码
// 要控制音频信号的采集
output reg audio_sample_en, // 音频采集使能
// 最后，是传输NPU指令（允许通过串口修改NPU运行的指令）
output reg [SYS_DATA_WIDTH-1:0] npu_inst_part,
output reg npu_inst_part_en,
// uart
output reg [SYS_DATA_WIDTH-1:0] sys_uart_write_data, // 要发送到 fifo的数据
output reg sys_uart_write_data_valid, // 要发送的数据有效
input sys_uart_write_data_permitted, // 允许发送数据
input [UART_DATA_WIDTH-1:0] sys_uart_read_data, // 从 fifo 中获取的数据
output reg sys_uart_read_data_req, // 从 fifo 中获取的数据使能/请求
input sys_uart_read_data_permitted, // 允许从fifo中获取数据
// ddr
output reg [SYS_DATA_WIDTH-1:0] sys_ddr_write_addr, // 要写入ddr的地址
output reg [SYS_DATA_WIDTH-1:0] sys_ddr_write_data, // 要发送到 ddr的数据
output reg sys_ddr_write_data_valid, // 要发送ddr的数据有效
output reg sys_ddr_write_burst_begin, // 要发送ddr的burst突发请求（1-clock宽度）
input sys_ddr_write_data_permitted, // 允许发送ddr数据
output reg [SYS_DATA_WIDTH-1:0] sys_ddr_read_addr, // 要读取 ddr的地址
input [SYS_DATA_WIDTH-1:0] sys_ddr_read_data, // 从 ddr 中获取的数据
input sys_ddr_read_data_valid, // 从 ddr 中获取的数据有效
output reg sys_ddr_read_burst_begin, // 要读取ddr的burst突发请求（1-clock宽度）
output reg sys_ddr_read_data_req, // 从 ddr 中获取的数据使能/请求
input sys_ddr_read_data_permitted // 允许从 ddr 中获取数据
);
// 首先，要能根据rfifo的情况，获取uart发送过来的命令
// 使用状态机：0看，1拿，2求，3空
reg [3:0] read_cnt;
reg [127:0] uart_cmd_shift /* synthesis noprune */;
always @(posedge sys_clk)
if(!sys_rst_n)
begin
uart_cmd_shift <= 0;
read_cnt <= 0;
end
else
begin
case(read_cnt)
// 生成rfifo的读取使能信号
0: begin
if(sys_uart_read_data_permitted)
begin
read_cnt <= 1;
sys_uart_read_data_req <= 0;
end
end
// 要把收到的命令进行移位存储
1: begin
read_cnt <= 2;
uart_cmd_shift <= {uart_cmd_shift[119:0],
sys_uart_read_data[7:0]
};
sys_uart_read_data_req <= 1; // 生成FIFO读取请求
end
// 撤销rfifo的读取时能信号
2: begin
read_cnt <= 3;
sys_uart_read_data_req <= 0;
end
// 这个3主要是为了能够“凑时序”，在uart-cmd_shift移位之后给出使能
3: read_cnt <= 0;
default:
read_cnt <= 0;
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////
// 如果收到 hello = {68,65,6c,6c,6f, xx, yy, zz, aa} 其中{xx, yy, zz, aa} 表示要发送的数据量（32 bit为单元）
// 就要返回 helloworldhh = {68,65,6c,6c,6f, 77 6F 72 6C 64 68 68, mm, nn, ...} 其中{mm, nn}表示的是要发送的数据
reg [31:0] send_back_cnt;
reg test_uart_cmd; // 测试uart的命令(hello/xxxx)
reg read_ddr_cmd; // 读取ddr的命令(r_ddr/xxxx)
reg write_ddr_cmd; // 写入ddr的命令(w_ddr/xxxx/yyyy)
reg cont_read_cmd; // 连续读取ddr的命令(contr/xxxx/yyyy)
reg cont_write_cmd; // 写入ddr的命令(contw/xxxx/yyyy)
reg adc_read_cmd; // 要读取adc写入ddr的命令(cradc/ffff/yyyy)
reg audio_sample_cmd; // 要采集音频信号的命令(audio/tttttttt)
reg measure_ram_cmd; // 测试RAM的读写速度的命令(msddr/xxxx/yyyy)
reg npu_inst_cmd; // 传输的是NPU指令的命令（npust/tttttttt)
always @(posedge sys_clk)
begin
test_uart_cmd <= (uart_cmd_shift[79:40]==40'H68656C6C6F && (read_cnt==3));
read_ddr_cmd <= (uart_cmd_shift[79:40]==40'H725F646472 && (read_cnt==3));
write_ddr_cmd <= (uart_cmd_shift[111:72]==40'H775F646472 && (read_cnt==3));
cont_read_cmd <= (uart_cmd_shift[111:72]==40'H636F6E7472 && (read_cnt==3));
cont_write_cmd <= (uart_cmd_shift[111:72]==40'H636F6E7477 && (read_cnt==3));
adc_read_cmd <= (uart_cmd_shift[111:72]==40'H6372616463 && (read_cnt==3));
audio_sample_cmd <= (uart_cmd_shift[79:40]==40'H617564696F && (read_cnt==3));
measure_ram_cmd <= (uart_cmd_shift[111:72]==40'H6D73646472 && (read_cnt==3));
npu_inst_cmd <= (uart_cmd_shift[79:40]==40'H6E70757374 && (read_cnt==3));
end
assign receive_valid_cmd = (npu_inst_cmd|test_uart_cmd|read_ddr_cmd|write_ddr_cmd|cont_read_cmd|cont_write_cmd|adc_read_cmd|audio_sample_cmd|measure_ram_cmd);
reg [8:0] receive_cmd_type;
always @(posedge sys_clk)
if(receive_valid_cmd)
receive_cmd_type <= {npu_inst_cmd, measure_ram_cmd, audio_sample_cmd, adc_read_cmd, cont_write_cmd, cont_read_cmd, write_ddr_cmd, read_ddr_cmd, test_uart_cmd};
/////////////////
// DDR-HMC出来的数据 sys_ddr_read_data 和数据有效 sys_ddr_read_data_valid 路径太长
// 所以中间再用register打一拍，拆开这条路径
reg [SYS_DATA_WIDTH-1:0] sys_ddr_read_data_reg;
reg sys_ddr_read_data_valid_reg;
always @(posedge sys_clk)
begin
sys_ddr_read_data_reg <= sys_ddr_read_data;
sys_ddr_read_data_valid_reg <= sys_ddr_read_data_valid;
end
/////////////////////////////////
// 为了优化时序，所以要把uart_cmd_shift 打一拍
reg [127:0] uart_cmd_shift_reg;
always @(posedge sys_clk)
if(receive_valid_cmd) // 可恶！居然漏了！这样的话，一旦发送命令的时候多了0x0D/0x0A就会出错！ 2018-05-04
uart_cmd_shift_reg <= uart_cmd_shift;
// 此外，由于发送到uart的fifo已经是一个安全深度了， 可以把 sys_ddr_write_data_permitted 也打一拍
reg sys_uart_write_data_permitted_reg;
always @(posedge sys_clk)
sys_uart_write_data_permitted_reg <= sys_uart_write_data_permitted;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 要读写ddr的接口
// 考虑到wfifo的almost full状态，以及HMC核的闲置与否，这里引入
// wfifo的写入锁与HMC的读取锁
// HMC的写入锁，使用状态机来实现
reg [4:0] ddr_wr_state;
reg [31:0] ddr_wr_number; // 计数 ddr 读写的次数
reg [31:0] ddr_wr_time; // 计量DDR读写的时间
always @(posedge sys_clk)
if(!sys_rst_n)
begin
sys_ddr_read_data_req <= 0; // 撤销读取请求
sys_ddr_write_data_valid <= 0; // 撤销写入请求
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
sys_ddr_write_burst_begin <= 0; // 撤销写入burst请求
ddr_wr_state <= 0; // 复位ddr读写状态机
// 撤销音频采样
audio_sample_en <= 0;
// 清除NPU指令有效
npu_inst_part_en <= 0;
end
else
begin
case(ddr_wr_state)
0: begin
sys_ddr_read_data_req <= 0; // 撤销读取请求
sys_ddr_write_data_valid <= 0; // 撤销写入请求
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
sys_ddr_write_burst_begin <= 0; // 撤销写入burst请求
// 清除NPU指令有效
npu_inst_part_en <= 0;
//
// 读取ddr请求
if(read_ddr_cmd)
ddr_wr_state <= 1;
// 写入ddr请求
else if(write_ddr_cmd)
ddr_wr_state <= 3;
// 连续写入ddr的请求
else if(cont_write_cmd)
begin
ddr_wr_state <= 5;
ddr_wr_number <= 0;
end
// 连续读取ddr的请求
else if(cont_read_cmd)
begin
ddr_wr_state <= 7;
ddr_wr_number <= 0;
end
// 连续读取adc写入的数据
else if(adc_read_cmd)
begin
ddr_wr_state <= 10;
ddr_wr_number <= 0;
end
// 采集音频信号
else if(audio_sample_cmd)
begin
ddr_wr_state <= 13;
ddr_wr_number <= 0;
audio_sample_en <= 1; // 使能音频采样
end
// 测试DDR读写速率的指令
else if(measure_ram_cmd)
begin
ddr_wr_state <= 14; // 首先是进行写入测速
ddr_wr_number <= 0;
ddr_wr_time <= 0; // 计时器清零
end
// 传输NPU指令的命令
else if(npu_inst_cmd)
begin
ddr_wr_state <= 18;
end
end
// 单次读取
1: begin
// 检查ddr是否允许读取
if(sys_ddr_read_data_permitted)
begin
sys_ddr_read_addr <= uart_cmd_shift_reg[39:8];
sys_ddr_read_data_req <= 1;
sys_ddr_read_burst_begin <= 1; // 给出读取burst请求（但在下一个clock撤销！）
ddr_wr_state <= 2;
end
end
2: begin
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
// 等待ddr读取完成
if(sys_ddr_read_data_permitted)
begin
//sys_ddr_read_addr <= 0;
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 0;
end
end
// 单次写入
3: begin
// 检查ddr是否允许写入
if(sys_ddr_write_data_permitted)
begin
sys_ddr_write_addr <= uart_cmd_shift_reg[71:40];
sys_ddr_write_data <= uart_cmd_shift_reg[39:8];
sys_ddr_write_data_valid <= 1;
sys_ddr_write_burst_begin <= 1; // 给出写入burst请求（但在下一个clock撤销！）
ddr_wr_state <= 4;
end
end
4: begin
sys_ddr_write_burst_begin <= 0; // 撤销写入burst请求
// 等待ddr写入完成
if(sys_ddr_write_data_permitted)
begin
//sys_ddr_write_addr <= 0;
//sys_ddr_write_data <= 0;
sys_ddr_write_data_valid <= 0;
ddr_wr_state <= 0;
end
end
// 连续写入
5: begin
// 检查ddr是否允许写入
if(sys_ddr_write_data_permitted)
begin
sys_ddr_write_addr <= uart_cmd_shift_reg[71:40];
sys_ddr_write_data <= uart_cmd_shift_reg[71:40]; // 地址和数据一致
sys_ddr_write_data_valid <= 1;
sys_ddr_write_burst_begin <= 1; // 给出写入burst请求（但在下一个clock撤销！）
ddr_wr_state <= 6;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
6: begin
sys_ddr_write_burst_begin <= 0; // 撤销写入burst请求
// 等待ddr写入完成
if(sys_ddr_write_data_permitted)
begin
sys_ddr_write_addr <= sys_ddr_write_addr+1;
sys_ddr_write_data <= sys_ddr_write_data+1;
if(ddr_wr_number<uart_cmd_shift_reg[39:8])
begin
sys_ddr_write_data_valid <= 1;
ddr_wr_number <= ddr_wr_number+1;
end
else
begin
sys_ddr_write_data_valid <= 0;
ddr_wr_state <= 0;
end
end
end
// 连续读取ddr的命令
7: begin
// 检查ddr是否允许读取
if(sys_ddr_read_data_permitted)
begin
sys_ddr_read_addr <= uart_cmd_shift_reg[71:40];
sys_ddr_read_data_req <= 1;
sys_ddr_read_burst_begin <= 1; // 给出读取burst请求（但在下一个clock撤销！）
ddr_wr_state <= 8;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
8: begin
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
// 等待ddr读取完成
if(sys_ddr_read_data_permitted)
begin
// 考察是不是读取够了，如果不够，就要考察slavefifo是否允许写入
if(ddr_wr_number<uart_cmd_shift_reg[39:8])
begin
// 如果允许uart写入，那么ddr的读取地址++，并且给出读取请求
if(sys_uart_write_data_permitted_reg)
begin
sys_ddr_read_addr <= sys_ddr_read_addr+1;
sys_ddr_read_data_req <= 1;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
// 如果uart不能写入，那么撤销ddr读取请求
// ，并且跳到新的状态，需要重新给出burst_begin
else
begin
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 9;
end
end
// 读取够了，就要跳出循环
else
begin
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 0;
end
end
end
9: begin
// 检查uart是否允许写入
if(sys_uart_write_data_permitted_reg)
begin
sys_ddr_read_addr <= sys_ddr_read_addr+1;
sys_ddr_read_data_req <= 1;
sys_ddr_read_burst_begin <= 1; // 给出读取burst请求（但在下一个clock撤销！）
ddr_wr_state <= 8;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
/////////////////////////////////////////////////
// 连续读取adc写入ddr数据的命令
10: begin
// 检查ddr是否允许读取
if(sys_ddr_read_data_permitted)
begin
sys_ddr_read_addr <= ((adc_ddr_write_addr-uart_cmd_shift_reg[39:8])&adc_ddr_write_addr_mask);
sys_ddr_read_data_req <= 1;
sys_ddr_read_burst_begin <= 1; // 给出读取burst请求（但在下一个clock撤销！）
ddr_wr_state <= 11;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
11: begin
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
// 等待ddr读取完成
if(sys_ddr_read_data_permitted)
begin
// 考察是不是读取够了，如果不够，就要考察slavefifo是否允许写入
if(ddr_wr_number<uart_cmd_shift_reg[39:8])
begin
// 如果允许uart写入，那么ddr的读取地址++，并且给出读取请求
if(sys_uart_write_data_permitted_reg)
begin
sys_ddr_read_addr <= ((sys_ddr_read_addr+1)&adc_ddr_write_addr_mask);
sys_ddr_read_data_req <= 1;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
// 如果uart不能写入，那么撤销ddr读取请求
// ，并且跳到新的状态，需要重新给出burst_begin
else
begin
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 12;
end
end
// 读取够了，就要跳出循环
else
begin
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 0;
end
end
end
12: begin
// 检查uart是否允许写入
if(sys_uart_write_data_permitted_reg)
begin
sys_ddr_read_addr <= ((sys_ddr_read_addr+1)&adc_ddr_write_addr_mask);
sys_ddr_read_data_req <= 1;
sys_ddr_read_burst_begin <= 1; // 给出读取burst请求（但在下一个clock撤销！）
ddr_wr_state <= 11;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
13: begin
// 等待tttttttt个clock
if(ddr_wr_number>=uart_cmd_shift_reg[39:8])
begin
audio_sample_en <= 0; // 采集够了，关断写入
ddr_wr_number <= 0;
ddr_wr_state <= 0;
end
else
ddr_wr_number <= ddr_wr_number + 1; // 否则继续采集
end
// 进行DDR读写测试
14: begin
ddr_wr_time <= ddr_wr_time + 1;
// 检查ddr是否允许写入
if(sys_ddr_write_data_permitted)
begin
sys_ddr_write_addr <= uart_cmd_shift_reg[71:40];
sys_ddr_write_data <= uart_cmd_shift_reg[71:40]; // 地址和数据一致
sys_ddr_write_data_valid <= 1;
ddr_wr_state <= 15;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
15: begin
ddr_wr_time <= ddr_wr_time + 1;
// 等待ddr写入完成
if(sys_ddr_write_data_permitted)
begin
sys_ddr_write_addr <= sys_ddr_write_addr+1;
sys_ddr_write_data <= sys_ddr_write_data+1;
if(ddr_wr_number<uart_cmd_shift_reg[39:8])
begin
sys_ddr_write_data_valid <= 1;
ddr_wr_number <= ddr_wr_number+1;
end
else
begin
sys_ddr_write_data_valid <= 0;
ddr_wr_state <= 16; // 然后进行DDR读取测试
ddr_wr_number <= 0;
end
end
end
16: begin
ddr_wr_time <= ddr_wr_time + 1;
// 检查ddr是否允许读取
if(sys_ddr_read_data_permitted)
begin
sys_ddr_read_addr <= uart_cmd_shift_reg[71:40];
sys_ddr_read_data_req <= 1;
ddr_wr_state <= 17;
// 计数++
ddr_wr_number <= ddr_wr_number+1;
end
end
17: begin
ddr_wr_time <= ddr_wr_time + 1;
// 等待ddr写入完成
if(sys_ddr_read_data_permitted)
begin
sys_ddr_read_addr <= sys_ddr_read_addr+1;
if(ddr_wr_number<uart_cmd_shift_reg[39:8])
begin
sys_ddr_read_data_req <= 1;
ddr_wr_number <= ddr_wr_number+1;
end
else
begin
sys_ddr_read_data_req <= 0;
ddr_wr_state <= 0; // 然后回到IDLE状态
end
end
end
// 传输NPU指令的命令
18: begin
npu_inst_part <= uart_cmd_shift_reg[39:8];
npu_inst_part_en <= 1;
ddr_wr_state <= 0; // 然后回到IDLE状态
end
//////////////////////////////////////////////
default: begin
sys_ddr_read_data_req <= 0; // 撤销读取请求
sys_ddr_write_data_valid <= 0; // 撤销写入请求
sys_ddr_read_burst_begin <= 0; // 撤销读取burst请求
sys_ddr_write_burst_begin <= 0; // 撤销写入burst请求
ddr_wr_state <= 0;
end
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 数据包构造，还是使用状态机来实现
reg [4:0] pkt_state;
reg [31:0] pkt_cnt;
always @(posedge sys_clk)
if(!sys_rst_n)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else
begin
case(pkt_state)
0: begin
sys_uart_write_data_valid <= 0;
if(test_uart_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 1;
end
else if(read_ddr_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 2;
end
else if(write_ddr_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 3;
end
else if(cont_read_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 4;
end
else if(cont_write_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 5;
end
else if(adc_read_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 6;
end
else if(audio_sample_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 7;
end
else if(measure_ram_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 8;
end
else if(npu_inst_cmd)
begin
pkt_cnt <= 0;
pkt_state <= 11;
end
end
// uart 测试
1: begin
if(pkt_cnt >= (uart_cmd_shift_reg[39:8]+3))
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else
begin
if(sys_uart_write_data_permitted_reg)
begin
if(pkt_cnt==0) sys_uart_write_data <= 32'H68656C6C; // hell
else if(pkt_cnt==1) sys_uart_write_data <= 32'H6F776F72; // owor
else if(pkt_cnt==2) sys_uart_write_data <= 32'H6C646868; // ldhh
else sys_uart_write_data <= pkt_cnt-3; // 测试数据（00, 01, 02, ...
pkt_cnt <= pkt_cnt + 1;
end
sys_uart_write_data_valid <= sys_uart_write_data_permitted_reg;
end
end
// ddr单次读取
2 : begin
if(pkt_cnt >= 2)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else
begin
if(pkt_cnt==0)
begin
if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H72646472; // rddr
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
else if(sys_ddr_read_data_valid_reg)
begin
sys_uart_write_data <= sys_key_fn[2]? sys_ddr_read_data_reg : {sys_ddr_read_data_reg[15:0], sys_ddr_read_data_reg[31:16]};
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
end
// ddr单次写入
3: begin
if(pkt_cnt >= 1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H77646472; // wddr
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
// ddr连续读取
4: begin
if(pkt_cnt >= uart_cmd_shift_reg[39:8]+1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else
begin
//
if(pkt_cnt==0)
begin
if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H72636F6E; // rcon
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
else if(sys_ddr_read_data_valid_reg)
begin
sys_uart_write_data <= sys_key_fn[2]? sys_ddr_read_data_reg : {sys_ddr_read_data_reg[15:0], sys_ddr_read_data_reg[31:16]};
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
end
// ddr 连续写入
5: begin
if(pkt_cnt >= 1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H77636F6E; // wcon
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
// ddr连续读取
6: begin
if(pkt_cnt >= uart_cmd_shift_reg[39:8]+1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else
begin
//
if(pkt_cnt==0)
begin
if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H72616463; // radc
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
else if(sys_ddr_read_data_valid_reg)
begin
sys_uart_write_data <= sys_key_fn[2]? sys_ddr_read_data_reg : {sys_ddr_read_data_reg[15:0], sys_ddr_read_data_reg[31:16]};
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
end
// 音频采集使能
7: begin
if(pkt_cnt >= 1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H61756469; // audi
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
// 然后是DDR读写速度的测试
8: begin
// 首先等待DDR读写状态机进入读写状态
if(ddr_wr_state>=15 && ddr_wr_number<=17)
begin
pkt_state <= 9;
pkt_cnt <= 0;
end
end
9: begin
// 等待DDR读写测试完成
if(ddr_wr_state==0)
begin
pkt_state <= 10;
pkt_cnt <= 0;
end
end
10: begin
// 然后就是发送DDR速度
if(pkt_cnt >= 2)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
// 生成数据报文
else
begin
if(pkt_cnt==0)
begin
if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H6D646472; // mddr
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
end
else if(pkt_cnt == 1)
begin
if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= ddr_wr_time; // 读写时间（cmd系统时钟频率计数）
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
end
end
end
// NPU指令传输完毕
11: begin
if(pkt_cnt >= 1)
begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
else if(sys_uart_write_data_permitted_reg)
begin
sys_uart_write_data <= 32'H696e7374; // inst
pkt_cnt <= pkt_cnt + 1;
sys_uart_write_data_valid <= 1;
end
else
sys_uart_write_data_valid <= 0;
end
//
default: begin
pkt_state <= 0;
sys_uart_write_data_valid <= 0;
end
///////////
endcase
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule |
module sc_fifo
#(
parameter LOG2N = 6, // 这是FIFO深度的对数值
parameter N = (1<<LOG2N), // FIFO的深度
parameter DATA_WIDTH = 32, // 数据宽度
parameter ADDR_WIDTH = LOG2N // 地址宽度
)
(
input wire aclr, // 异步复位
input wire clock, // 读写时钟
// 写入端口的信号线
input wire [DATA_WIDTH-1:0] data, // 写数据
input wire wrreq, // 写请求
// 读取端口的信号线
output reg [DATA_WIDTH-1:0] q, // 读数据
input wire rdreq, // 读请求
// 标志位
output wire [ADDR_WIDTH-1:0] usedw, // 写数据量
output wire full, // 写满标志
output wire empty // 写空标志
);
/*-------------------------------------------------------------------------*\
signals
\*-------------------------------------------------------------------------*/
// 首先声明一块内存空间
reg [DATA_WIDTH-1:0] dpram [0:N-1]; // 内存空间，试图转换成DPRAM
reg [ADDR_WIDTH:0] wr_addr; // 写入地址
reg [ADDR_WIDTH:0] rd_addr; // 读取地址
/*-------------------------------------------------------------------------*\
timing
\*-------------------------------------------------------------------------*/
/*
for writing:
clock _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|-
aclr __|-|____________________________________________
wrreq ____|-----------------------------------|_______
wraddr _| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |________
data ____| d0| d1| d2| d3| d4| d5| d6| d7| d8|________
for reading:
clock _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|-
aclr __|-|____________________________________________
rdreq ____|-----------------------------------|_______
rdaddr _| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |________
q _| d0 | d1| d2| d3| d4| d5| d6| d7| d8|________
*/
/*-------------------------------------------------------------------------*\
process
\*-------------------------------------------------------------------------*/
// 首先是写入地址生成
always @(posedge clock or posedge aclr)
if(aclr==1)
wr_addr <= 0;
else if(wrreq && !full)
wr_addr <= wr_addr + {{(ADDR_WIDTH){1'B0}}, 1'B1};
// 然后是读取地址生成
always @(posedge clock or posedge aclr)
if(aclr==1)
rd_addr <= 0;
else if(rdreq && !empty)
rd_addr <= rd_addr + {{(ADDR_WIDTH){1'B0}}, 1'B1};
// 现在是内存的行为
// 写入
always @(posedge clock)
if(wrreq && !full)
dpram[wr_addr[ADDR_WIDTH-1:0]] <= data;
// 读取
always @(*)
q = dpram[rd_addr[ADDR_WIDTH-1:0]];
//
// 然后是要生成一些标志信号
assign usedw = (wr_addr - rd_addr + N);
assign full = (usedw>=N);
assign empty = (usedw==0);
/*-------------------------------------------------------------------------*\
instantiation
\*-------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////
endmodule |
module cordic_exp_rtl
#(parameter DATA_WIDTH = 32, // Êý¾Ýλ¿í
parameter FRAC_WIDTH = 16, // СÊý²¿·Ö
parameter EPSILON = 16, // ÊÕÁ²ãÐÖµ
parameter ITERATION = 8, // µü´ú´ÎÊý
parameter ROM_LATENCY = 2, // romµÄIPºË¶ÁÈ¡ÐèÒªÑÓʱ
parameter DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // ¹Ì¶¨µÄµ¥Î»1
parameter DATA_ZERO = {DATA_WIDTH{1'B0}}, // ¹Ì¶¨µÄ0Öµ
parameter DATA_LOF = (FRAC_WIDTH*11)<<(FRAC_WIDTH-4), // ÏÂÒç ==> Ö±½Ó·µ»Ø0 e^-11 ==> 2^-16,
parameter DATA_UOF = ((DATA_WIDTH-FRAC_WIDTH-1)*11)<<(FRAC_WIDTH-4) // ÉÏÒç ==> Ö±½Ó·µ»Ø(2**31-1) e^10.39 ==> 2^15,
)
(
input wire sys_clk, sys_rst_n,
input wire signed [DATA_WIDTH-1:0] src_x,
output reg signed [DATA_WIDTH-1:0] rho
);
// ´æ´¢KnµÄϵÊý±í£¬Ê¹ÓÃPython½Å±¾À´Éú³ÉÏàÓ¦µÄÊýÖµ
wire [DATA_WIDTH-1:0] Kn_THETAn_address;
wire [DATA_WIDTH-1:0] Kn;
wire [DATA_WIDTH-1:0] THETAn;
cordic_factor_exp_rom_ip exp_cordic_rom_ip_core (.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));
//////////////////////////////////
// ÒòΪҪд³ÉÁ÷Ë®ÏßÐ͵ÄCORDICÔËËã
// ËùÒÔÐèÒª½¨Á¢Ò»¸ö¾Þ´óµÄregÕóÁÐ
reg signed [DATA_WIDTH-1:0] Xn [0:ITERATION-1]; // ÒòΪÊÇÁ÷Ë®Ïߣ¬ËùÒÔÐèÒª²»¶ÏµØ¡°ÒÆλ¡±µü´úÊäÈëµÄx(СÊý²¿·Ö)
reg signed [DATA_WIDTH-1:0] In [0:ITERATION-1]; // ÒòΪÊÇÁ÷Ë®Ïߣ¬ËùÒÔÐèÒª²»¶ÏµØ¡°ÒÆλ¡±µü´úÊäÈëµÄx(ÕûÊý²¿·Ö)
reg signed [DATA_WIDTH-1:0] Zn [0:ITERATION-1];
reg LOFn[0:ITERATION-1]; // ÏÂÒç
reg UOFn[0:ITERATION+2]; // ÉÏÒç
// µü´ú´ÎÊý£¬ÒòΪZnÊÇ¿ÉÄÜÖÐ;ÊÕÁ²µÄ£¬ÐèÒª±êעʲôʱºòÊÕÁ²ÁË
reg [DATA_WIDTH-1:0] Nn [0:ITERATION+1]; // Ò»¸ö³ÌÐòµÄbug£¬ÕâÀïµÄNnÓ¦¸Ã¼ÌÐø´«µÝ
// »¹Òª¼Ç¼ÐýתµÄ½Ç¶È
reg signed [DATA_WIDTH-1:0] Tn [0:ITERATION-1];
reg signed [DATA_WIDTH-1:0] T0n [0:ITERATION-1]; // ÕâÊÇÒª´ÓROMÀïÃæ¼ÓÔصÄ
reg signed [DATA_WIDTH-1:0] K0n [0:ITERATION-1]; // ÕâÊÇÒª´ÓROMÀïÃæ¼ÓÔصÄ
//
reg [4:0] cstate; // ״̬¼ÆÊýÆ÷
parameter IDLE = 0; // ÏÐÖÃ״̬
parameter LOAD = 1; // ¼ÓÔØROMÖеÄÊý¾Ý
parameter COMP = 2; // Õý³£µÄ¹¤×÷/ÔËËã½×¶Î
reg [DATA_WIDTH-1:0] timer_in_state; // ÿ¸ö½×¶ÎµÄ¼ÆÊýÆ÷
reg [DATA_WIDTH-1:0] rom_address; // ¶ÁÈ¡ROMµÄµØÖ·¼ÆÊýÆ÷
// cordic µü´úÔËËã + Êý¾ÝÊäÈë&1/4ÏóÏÞУÕý´¦Àí
always @(posedge sys_clk)
// ³õʼ»¯
if(!sys_rst_n)
init_system_task;
// ·ñÔò¾ÍÊÇÕý³£µÄµü´ú¼ÆËã
else
begin
case(cstate)
IDLE: prepare_load_task;
LOAD: execute_load_task;
COMP: execute_comp_task;
default: init_system_task;
endcase
end
///////////////////////////////
// ÏÂÃæÊǾßÌåµÄtaskµÄÃèÊö
integer n;
// Ê×ÏÈÊÇϵͳ³õʼ»¯µÄÃèÊö
task init_system_task;
begin
cstate <= IDLE; // Ê×ÏÈÇл»µ½ÏÐÖÃ״̬
// È»ºó¸´Î»ËùÓеļĴæÆ÷
for(n=0; n<ITERATION; n=n+1)
begin
Xn[n] <= DATA_ZERO;
Zn[n] <= DATA_ZERO;
Nn[n] <= DATA_ZERO;
Tn[n] <= DATA_ZERO;
//
LOFn[n] <= 0;
UOFn[n] <= 0;
end
// ¼ÆÊýÆ÷¸´Î»
timer_in_state <= DATA_ZERO;
// ¶ÁÈ¡romµÄµØÖ·¼ÆÊýÆ÷ÇåÁã
rom_address <= 0;
end
endtask
////////////////////
// È»ºóÊÇIDLE½×¶Î£¬²»Ö±½Ó½øÈëload½×¶Î£¬
// Ö÷ÒªÊÇÒòΪromµÄ¶ÁÈ¡ÊÇÓÐlatencyʱ¼äµÄ
task prepare_load_task;
begin
// Èç¹ûµÈ´ý¹»Á˾ÍÒªÌø³ö£¬½øÈëromÊý¾Ý¼ÓÔؽ׶Î
if(timer_in_state>=(ROM_LATENCY-1))
begin
cstate <= LOAD;
// ¼ÆÊýÆ÷¸´Î»
timer_in_state <= DATA_ZERO;
end
// ·ñÔò£¬¾ÍÒª¼ÌÐø¼ÓÔØROMÊý¾Ý
else
begin
timer_in_state <= timer_in_state+1;
end
// rom¶ÁÈ¡²»ÒªÍ£
rom_address <= rom_address+1;
end
endtask
// È»ºóÊÇLOAD½×¶Î£¬Ö´ÐÐloadÖ¸Áî
task execute_load_task;
begin
// ¼ÓÔع»ÁË£¬¾ÍÒªÌø³ö£¬¿ÉÒÔ¿ªÊ¼¼ÆËãÁË
if(timer_in_state>=(ITERATION))
begin
cstate <= COMP;
// ¼ÆÊýÆ÷¸´Î»
timer_in_state <= DATA_ZERO;
end
else
begin
// ·ñÔò£¬¼ÓÔØromÀïÃæµÄÊý¾Ý
T0n[timer_in_state] <= THETAn;
K0n[timer_in_state] <= Kn;
rom_address <= rom_address+1;
timer_in_state <= timer_in_state+1;
end
end
endtask
// ÏÖÔÚÊÇÖØÍ·Ï·£¬¾ÍÊÇÕû¸öcoedicµü´ú¹ý³ÌÁË
task execute_comp_task;
begin
// Ê×ÏÈÊÇÊäÈëÊý¾Ý
// ·Ö¸îÊý¾ÝµÄÕûÊý - СÊý²¿·Ö
Xn[0] <= {{(DATA_WIDTH-FRAC_WIDTH){1'B0}}, src_x[FRAC_WIDTH-1:0]};
In[0] <= (src_x >>> FRAC_WIDTH);
// ÉÏÒç/ÏÂÒçÅбð
LOFn[0] <= src_x < (-DATA_LOF);
UOFn[0] <= src_x >= (DATA_UOF);
// ³õʼ»¯Z = 1
Zn[0] <= DATA_UNIT;
// È»ºóN = 0
Nn[0] <= DATA_ZERO;
// T=0
Tn[0] <= DATA_ZERO;
// È»ºóÊÇcordicµü´úµÄ¹ý³Ì£¬ÕâÀïʹÓÃforÑ»·£¬·½±ãд³ÌÐò£¬×¢Òâ×ۺϽá¹û
for(n=ITERATION-1; n>=1; n=n-1)
begin
// ÊäÈë X & I ÐèÒª²»¶ÏµØÒÆλÏÂÈ¥
Xn[n] <= Xn[n-1];
In[n] <= In[n-1];
// Èç¹ûTn[n-1]>Xn[n-1]£¬ÄÇô˳ʱÕëÐýת
if(Tn[n-1]>(Xn[n-1]+EPSILON))
begin
Zn[n] <= Zn[n-1] - (Zn[n-1]>>>(n));
Nn[n] <= Nn[n-1] + 1; // ¼ÌÐøµü´ú£¬µü´ú´ÎÊý+1
Tn[n] <= Tn[n-1] - T0n[n-1]; // Ð޸ĽǶÈÖµ
end
// Èç¹ûTn[n-1]<Xn[n-1]£¬ÄÇôÄæʱÕëÐýת
else if(Xn[n-1]>(Tn[n-1]+EPSILON))
begin
Zn[n] <= Zn[n-1] + (Zn[n-1]>>>(n));
Nn[n] <= Nn[n-1] + 1; // ¼ÌÐøµü´ú£¬µü´ú´ÎÊý+1
Tn[n] <= Tn[n-1] + T0n[n-1]; // Ð޸ĽǶÈÖµ
end
// ·ñÔò¾Í˵Ã÷ÊÕÁ²ÁË£¬Í£Ö¹µü´ú¹ý³Ì
else
begin
Zn[n] <= Zn[n-1];
Nn[n] <= Nn[n-1];
Tn[n] <= Tn[n-1];
end
//
LOFn[n] <= LOFn[n-1];
UOFn[n] <= UOFn[n-1];
end
// Nn»¹ÔÚ´«µÝ
Nn[ITERATION] <= Nn[ITERATION-1];
Nn[ITERATION+1] <= Nn[ITERATION];
// ÉÏÒçÖ¸±ê»¹ÔÚ´«µÝ
UOFn[ITERATION] <= UOFn[ITERATION-1];
UOFn[ITERATION+1] <= UOFn[ITERATION];
UOFn[ITERATION+2] <= UOFn[ITERATION+1];
end
endtask
//////////////////////////////////////////////////
// ×îºó£¬¿¼Âǵ½romµÄipºË¶ÁÈ¡£¬ÐèÒª¸ø³öROMµÄ¶ÁÈ¡µØÖ·
assign Kn_THETAn_address = rom_address;
// ÓÉÓÚÔÚKn[]ÀïÃæÑ°Ö· + Êä³öУÕýµÄ³Ë·¨ÔËË㣬ʮ·ÖÏûºÄ×ÊÔ´£¬Ó°ÏìʱÐò
// ËùÒÔÕâÀïÏȰѸ÷¸öÊý¾Ý¶¼¼Ä´æһϣ¬ÄÇôºóÃæµÄ¾ÍÖ»Êdz˷¨Ó°ÏìʱÐòÁË
reg [DATA_WIDTH-1:0] Kn_res [0:1]; // ÊÂʵ֤Ã÷£¬Õâ¸öK0n»¹²»ÈçÖ±½Ó±ä³Éram£¡
reg [DATA_WIDTH-1:0] Zn_res [0:1];
reg [DATA_WIDTH-1:0] Xn_res [0:1];
reg [DATA_WIDTH-1:0] In_res [0:1];
always @(posedge sys_clk)
begin
Kn_res[0] <= K0n[Nn[ITERATION-1]-1];
Zn_res[0] <= LOFn[ITERATION-1]? DATA_ZERO : UOFn[ITERATION-1]? {1'B0, {(DATA_WIDTH-1){1'B1}}} : Zn[ITERATION-1]; // Ôö¼ÓÉÏÒç/ÏÂÒçָʾ
Xn_res[0] <= Xn[ITERATION-1];
In_res[0] <= In[ITERATION-1];
// ΪÁËʱÐòÒ²ÊÇÆ´ÁË
Kn_res[1] <= Kn_res[0];
Zn_res[1] <= Zn_res[0];
Xn_res[1] <= Xn_res[0];
In_res[1] <= In_res[0];
end
// È»ºóÊÇУÕýrho£¬ÐèÒªKnϵÊý
// ×¢Òâµ½ÕâÀïµÄKn¶¼ÊÇ0~1µÄϵÊý£¬ËùÒÔÎÒÃÇ´æµÄʱºò£¬¾¡¹ÜÊÇ32bitµÄsigned±äÁ¿£¬Êµ¼ÊÖÐÓõ½ÁË(FRAC_WIDTH)-bit
// Òò´Ë£¬×îºóÊä³öµÄʱºò£¬ÐèÒª×öһЩÅжϵÄ
reg [2*DATA_WIDTH-1:0] rho_reg [0:1]; // ÕâÊÇУÕýÏòÁ¿Ä£Êä³öµÄʱºòµÄ¡°ÔÝ´æ±äÁ¿¡±£¬ÊÇ64-bitµÄ£¬×îºóÒª½ØµôLSB
reg [DATA_WIDTH-1:0] x_reg [0:1]; // ÊäÈëÏòÁ¿µÄÒÆλ»º´æ£¬ÎªÁËÄܹ»ºÍÊä³örho½øÐбȶÔ
// [0] ÊÇûÓÐÕûÊý²¿·ÖʱºòµÄÊý¾ÝÖµ£¬ [1]ÊÇÓÐÕûÊý²¿·ÖÒÔºóµÄÊý¾ÝÖµ
wire [DATA_WIDTH-1:0] int_part_exp_val; // ÕûÊý²¿·ÖµÄ exp ÔËËã½á¹ûÊý¾ÝÖµ
reg [DATA_WIDTH-1:0] x;
always @(posedge sys_clk)
begin
// Èç¹ûûÓÐÏòÉÏÒç³ö
if(UOFn[ITERATION+1]==0)
begin
if(Nn[ITERATION+1]==0)
rho_reg[0] <= Zn_res[1]*DATA_UNIT;
else
rho_reg[0] <= Zn_res[1]*Kn_res[1]; // ×¢Ò⣡ ÕâÀïÊÇʱÐò·Ç³£²îµÄµØ·½£¬ÒªÏë°ì·¨µ÷Õû
end
// Èç¹ûÏòÉÏÒç³ö
else
rho_reg[0] <= {1'B0, {(2*DATA_WIDTH-1){1'B1}}};
//
x_reg[0] <= Xn_res[1]|(In_res[1]<<<FRAC_WIDTH);
////////
// ¼ÓÈëÕûÊý²¿·ÖµÄУÕý
x_reg[1] <= x_reg[0];
// Èç¹ûûÓÐÏòÉÏÒç³ö
if(UOFn[ITERATION+2]==0)
rho_reg[1] <= rho_reg[0][2*DATA_WIDTH-1:FRAC_WIDTH]*int_part_exp_val;
else
rho_reg[1] <= (1<<(DATA_WIDTH+FRAC_WIDTH-1))-1;
////////
rho <= rho_reg[1][DATA_WIDTH+FRAC_WIDTH-1:FRAC_WIDTH];
x <= x_reg[1];
end
// ´ÓROMÀïÃæ¶Á³öÕûÊý²¿·ÖµÄÖ¸ÊýÔËËã½á¹û
cordic_int_part_exp_rom_ip int_part_mdl(.address(In_res[0]+128), .clock(sys_clk), .q(int_part_exp_val));
endmodule |
module cordic_ln
#( parameter DATA_WIDTH = 32, // 数据位宽
parameter FRAC_WIDTH = 16,
parameter EPSILON = 3, // 收敛阈值
parameter ITERATION = 8, // 迭代次数
parameter ROM_LATENCY = 2, // rom的IP核读取需要延时
parameter DATA_ZERO = {DATA_WIDTH{1'B0}}, // 固定的0值
parameter DATA_UNIT = {{(DATA_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // 固定的1值
parameter LN_2 = 32'D45426, // ln(2)定点化
parameter LN_EPS = -2362156 // 近零（np.log(np.finfo(float).eps)*2**16）
)
(
input wire sys_clk, sys_rst_n,
input wire signed [DATA_WIDTH-1:0] r,
output reg signed [DATA_WIDTH-1:0] ln_r
);
// 存储Kn的系数表，使用Python脚本来生成相应的数值
wire [DATA_WIDTH-1:0] Kn_THETAn_address;
wire [DATA_WIDTH-1:0] Kn;
wire [DATA_WIDTH-1:0] THETAn;
cordic_factor_exp_rom_ip exp_cordic_rom_ip_core (.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));
//////////////////////////////////
// tanh^-1(a) = 1/2 * ln^-1((1+a)/(1-a)), and if we let 1+a/1-a = b,
// then we have: tanh^-1((b-1)/(b+1)) = 1/2 * ln(b)
// 因为要写成流水线型的CORDIC运算
// 所以需要建立一个巨大的reg阵列
reg signed [DATA_WIDTH-1:0] Xn [0:ITERATION-1]; // 归一化以后的数值，减去1
reg signed [DATA_WIDTH-1:0] Yn [0:ITERATION-1]; // 归一化以后的数值，加上1
reg signed [DATA_WIDTH-1:0] Pn [0:ITERATION-1]; // 左移/右移，归一化模块输入到[1/2, 1]
reg LOFn[0:ITERATION]; // 零输入的标记
// 迭代次数，因为Zn是可能中途收敛的，需要标注什么时候收敛了
reg [DATA_WIDTH-1:0] Nn [0:ITERATION+1]; // 一个程序的bug，这里的Nn应该继续传递
// 还要记录旋转的角度
reg signed [DATA_WIDTH-1:0] Tn [0:ITERATION-1];
reg signed [DATA_WIDTH-1:0] T0n [0:ITERATION-1]; // 这是要从ROM里面加载的
reg signed [DATA_WIDTH-1:0] K0n [0:ITERATION-1]; // 这是要从ROM里面加载的
//
reg [4:0] cstate; // 状态计数器
parameter IDLE = 0; // 闲置状态
parameter LOAD = 1; // 加载ROM中的数据
parameter COMP = 2; // 正常的工作/运算阶段
reg [DATA_WIDTH-1:0] timer_in_state; // 每个阶段的计数器
reg [DATA_WIDTH-1:0] rom_address; // 读取ROM的地址计数器
// cordic 迭代运算 + 数据输入&1/4象限校正处理
always @(posedge sys_clk)
// 初始化
if(!sys_rst_n)
init_system_task;
// 否则就是正常的迭代计算
else
begin
case(cstate)
IDLE: prepare_load_task;
LOAD: execute_load_task;
COMP: execute_comp_task;
default: init_system_task;
endcase
end
///////////////////////////////
// 下面是具体的task的描述
integer n;
// 首先是系统初始化的描述
task init_system_task;
begin
cstate <= IDLE; // 首先切换到闲置状态
// 然后复位所有的寄存器
for(n=0; n<ITERATION; n=n+1)
begin
Xn[n] <= DATA_ZERO;
Yn[n] <= DATA_ZERO;
Pn[n] <= DATA_ZERO;
Nn[n] <= DATA_ZERO;
Tn[n] <= DATA_ZERO;
LOFn[n] <= 0;
end
// 计数器复位
timer_in_state <= DATA_ZERO;
// 读取rom的地址计数器清零
rom_address <= 0;
end
endtask
////////////////////
// 然后是IDLE阶段，不直接进入load阶段，
// 主要是因为rom的读取是有latency时间的
task prepare_load_task;
begin
// 如果等待够了就要跳出，进入rom数据加载阶段
if(timer_in_state>=(ROM_LATENCY-1))
begin
cstate <= LOAD;
// 计数器复位
timer_in_state <= DATA_ZERO;
end
// 否则，就要继续加载ROM数据
else
begin
timer_in_state <= timer_in_state+1;
end
// rom读取不要停
rom_address <= rom_address+1;
end
endtask
// 然后是LOAD阶段，执行load指令
task execute_load_task;
begin
// 加载够了，就要跳出，可以开始计算了
if(timer_in_state>=(ITERATION))
begin
cstate <= COMP;
// 计数器复位
timer_in_state <= DATA_ZERO;
end
else
begin
// 否则，加载rom里面的数据
T0n[timer_in_state] <= THETAn;
K0n[timer_in_state] <= Kn;
rom_address <= rom_address+1;
timer_in_state <= timer_in_state+1;
end
end
endtask
// 现在是重头戏，就是整个cordic迭代过程了
reg [DATA_WIDTH-1:0] rx;
always @(posedge sys_clk)
rx <= r[DATA_WIDTH-1]? (~r+1) : r;
task execute_comp_task;
begin
// 首先是输入数据
// 使用casex语句，用面积换时序
casex(rx)
32'B1XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 17;
Xn[0] <= (rx>>>17) + DATA_UNIT;
Yn[0] <= (rx>>>17) - DATA_UNIT;
end
32'B01XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 16;
Xn[0] <= (rx>>>16) + DATA_UNIT;
Yn[0] <= (rx>>>16) - DATA_UNIT;
end
32'B001XXXXXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 15;
Xn[0] <= (rx>>>15) + DATA_UNIT;
Yn[0] <= (rx>>>15) - DATA_UNIT;
end
32'B0001XXXXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 14;
Xn[0] <= (rx>>>14) + DATA_UNIT;
Yn[0] <= (rx>>>14) - DATA_UNIT;
end
32'B00001XXXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 13;
Xn[0] <= (rx>>>13) + DATA_UNIT;
Yn[0] <= (rx>>>13) - DATA_UNIT;
end
32'B000001XXXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 12;
Xn[0] <= (rx>>>12) + DATA_UNIT;
Yn[0] <= (rx>>>12) - DATA_UNIT;
end
32'B0000001XXXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 11;
Xn[0] <= (rx>>>11) + DATA_UNIT;
Yn[0] <= (rx>>>11) - DATA_UNIT;
end
32'B00000001XXXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 10;
Xn[0] <= (rx>>>10) + DATA_UNIT;
Yn[0] <= (rx>>>10) - DATA_UNIT;
end
32'B000000001XXXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 9;
Xn[0] <= (rx>>>9) + DATA_UNIT;
Yn[0] <= (rx>>>9) - DATA_UNIT;
end
32'B0000000001XXXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 8;
Xn[0] <= (rx>>>8) + DATA_UNIT;
Yn[0] <= (rx>>>8) - DATA_UNIT;
end
32'B00000000001XXXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 7;
Xn[0] <= (rx>>>7) + DATA_UNIT;
Yn[0] <= (rx>>>7) - DATA_UNIT;
end
32'B000000000001XXXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 6;
Xn[0] <= (rx>>>6) + DATA_UNIT;
Yn[0] <= (rx>>>6) - DATA_UNIT;
end
32'B0000000000001XXXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 5;
Xn[0] <= (rx>>>5) + DATA_UNIT;
Yn[0] <= (rx>>>5) - DATA_UNIT;
end
32'B00000000000001XXXXXXXXXXXXXXXXXX : begin
Pn[0] <= 4;
Xn[0] <= (rx>>>4) + DATA_UNIT;
Yn[0] <= (rx>>>4) - DATA_UNIT;
end
32'B000000000000001XXXXXXXXXXXXXXXXX : begin
Pn[0] <= 3;
Xn[0] <= (rx>>>3) + DATA_UNIT;
Yn[0] <= (rx>>>3) - DATA_UNIT;
end
32'B0000000000000001XXXXXXXXXXXXXXXX : begin
Pn[0] <= 2;
Xn[0] <= (rx>>>2) + DATA_UNIT;
Yn[0] <= (rx>>>2) - DATA_UNIT;
end
32'B00000000000000001XXXXXXXXXXXXXXX : begin
Pn[0] <= 1;
Xn[0] <= (rx>>>1) + DATA_UNIT;
Yn[0] <= (rx>>>1) - DATA_UNIT;
end
32'B000000000000000001XXXXXXXXXXXXXX : begin
Pn[0] <= 0;
Xn[0] <= rx + DATA_UNIT;
Yn[0] <= rx - DATA_UNIT;
end
32'B0000000000000000001XXXXXXXXXXXXX : begin
Pn[0] <= -1;
Xn[0] <= (rx<<<1) + DATA_UNIT;
Yn[0] <= (rx<<<1) - DATA_UNIT;
end
32'B00000000000000000001XXXXXXXXXXXX : begin
Pn[0] <= -2;
Xn[0] <= (rx<<<2) + DATA_UNIT;
Yn[0] <= (rx<<<2) - DATA_UNIT;
end
32'B000000000000000000001XXXXXXXXXXX : begin
Pn[0] <= -3;
Xn[0] <= (rx<<<3) + DATA_UNIT;
Yn[0] <= (rx<<<3) - DATA_UNIT;
end
32'B0000000000000000000001XXXXXXXXXX : begin
Pn[0] <= -4;
Xn[0] <= (rx<<<4) + DATA_UNIT;
Yn[0] <= (rx<<<4) - DATA_UNIT;
end
32'B00000000000000000000001XXXXXXXXX : begin
Pn[0] <= -5;
Xn[0] <= (rx<<<5) + DATA_UNIT;
Yn[0] <= (rx<<<5) - DATA_UNIT;
end
32'B000000000000000000000001XXXXXXXX : begin
Pn[0] <= -6;
Xn[0] <= (rx<<<6) + DATA_UNIT;
Yn[0] <= (rx<<<6) - DATA_UNIT;
end
32'B0000000000000000000000001XXXXXXX : begin
Pn[0] <= -7;
Xn[0] <= (rx<<<7) + DATA_UNIT;
Yn[0] <= (rx<<<7) - DATA_UNIT;
end
32'B00000000000000000000000001XXXXXX : begin
Pn[0] <= -8;
Xn[0] <= (rx<<<8) + DATA_UNIT;
Yn[0] <= (rx<<<8) - DATA_UNIT;
end
32'B000000000000000000000000001XXXXX : begin
Pn[0] <= -9;
Xn[0] <= (rx<<<9) + DATA_UNIT;
Yn[0] <= (rx<<<9) - DATA_UNIT;
end
32'B0000000000000000000000000001XXXX : begin
Pn[0] <= -10;
Xn[0] <= (rx<<<10) + DATA_UNIT;
Yn[0] <= (rx<<<10) - DATA_UNIT;
end
32'B00000000000000000000000000001XXX : begin
Pn[0] <= -11;
Xn[0] <= (rx<<<11) + DATA_UNIT;
Yn[0] <= (rx<<<11) - DATA_UNIT;
end
32'B000000000000000000000000000001XX : begin
Pn[0] <= -12;
Xn[0] <= (rx<<<12) + DATA_UNIT;
Yn[0] <= (rx<<<12) - DATA_UNIT;
end
32'B0000000000000000000000000000001X : begin
Pn[0] <= -13;
Xn[0] <= (rx<<<13) + DATA_UNIT;
Yn[0] <= (rx<<<13) - DATA_UNIT;
end
32'B00000000000000000000000000000001 : begin
Pn[0] <= -14;
Xn[0] <= (rx<<<14) + DATA_UNIT;
Yn[0] <= (rx<<<14) - DATA_UNIT;
end
default: begin
Pn[0] <= 0;
Xn[0] <= + DATA_UNIT;
Yn[0] <= - DATA_UNIT;
end
endcase
//////////////////////////////////
// 下溢指示?
LOFn[0] <= (rx==0);
// 然后N = 0
Nn[0] <= DATA_ZERO;
// T=0
Tn[0] <= DATA_ZERO;
// 然后是cordic迭代的过程，这里使用for循环，方便写程序，注意综合结果
for(n=ITERATION-1; n>=1; n=n-1)
begin
// 移位情况 Pn 需要不断地移位下去
Pn[n] <= Pn[n-1];
LOFn[n] <= LOFn[n-1];
// 如果Yn[n-1]>0，那么顺时针旋转
if(Yn[n-1]>EPSILON)
begin
Xn[n] <= Xn[n-1] - (Yn[n-1]>>>(n));
Yn[n] <= Yn[n-1] - (Xn[n-1]>>>(n));
Nn[n] <= Nn[n-1] + 1; // 继续迭代，迭代次数+1
Tn[n] <= Tn[n-1] + T0n[n-1]; // 修改角度值
end
// 如果Yn[n-1]<0，那么逆时针旋转
else if(Yn[n-1]<-EPSILON)
begin
Xn[n] <= Xn[n-1] + (Yn[n-1]>>>(n));
Yn[n] <= Yn[n-1] + (Xn[n-1]>>>(n));
Nn[n] <= Nn[n-1] + 1; // 继续迭代，迭代次数+1
Tn[n] <= Tn[n-1] - T0n[n-1]; // 修改角度值
end
// 否则就说明收敛了，停止迭代过程
else
begin
Xn[n] <= Xn[n-1];
Yn[n] <= Yn[n-1];
Nn[n] <= Nn[n-1];
Tn[n] <= Tn[n-1];
end
end
LOFn[ITERATION] <= LOFn[ITERATION-1];
end
endtask
// 最后，考虑到rom的ip核读取，需要给出ROM的读取地址
assign Kn_THETAn_address = rom_address;
// 最后输出
reg signed [2*DATA_WIDTH-1:0] bias;// = (Pn[ITERATION-1] * LN_2);
reg signed [DATA_WIDTH-1:0] theta;
always @(posedge sys_clk)
begin
bias <= (Pn[ITERATION-1] * LN_2);
theta <= Tn[ITERATION-1] * 2;
ln_r <= LOFn[ITERATION]? LN_EPS : (theta + bias); // 这里对于ln(0)进行了定义
end
// 为了调试
wire signed [31:0] P0 = Pn[0];
wire signed [31:0] X0 = Xn[0];
wire signed [31:0] Y0 = Yn[0];
wire signed [31:0] Pf = Pn[ITERATION-1];
wire signed [31:0] Xf = Xn[ITERATION-1];
wire signed [31:0] Yf = Yn[ITERATION-1];
endmodule |
module cordic_rot
#(parameter DATA_WIDTH = 32, // 数据位宽
parameter EPSILON = 3, // 收敛阈值
parameter ITERATION = 8, // 迭代次数
parameter ROM_LATENCY = 2, // rom的IP核读取需要延时
parameter DATA_ZERO = {DATA_WIDTH{1'B0}} // 固定的0值
)
(
input wire sys_clk, sys_rst_n,
input wire [DATA_WIDTH-1:0] src_x,
input wire [DATA_WIDTH-1:0] src_y,
output reg [DATA_WIDTH-1:0] rho,
output reg [DATA_WIDTH-1:0] theta
);
// 存储Kn的系数表，使用Python脚本来生成相应的数值
wire [DATA_WIDTH-1:0] Kn_THETAn_address;
wire [DATA_WIDTH-1:0] Kn;
wire [DATA_WIDTH-1:0] THETAn;
cordic_factor_Kn_rom_ip Kn_rom_ip_core (.address(Kn_THETAn_address),.clock(sys_clk),.q({Kn, THETAn}));
//////////////////////////////////
// 因为要写成流水线型的CORDIC运算
// 所以需要建立一个巨大的reg阵列
reg signed [DATA_WIDTH-1:0] Xn [0:ITERATION-1];
reg signed [DATA_WIDTH-1:0] Yn [0:ITERATION-1];
reg Sn [0:ITERATION-1];// 用来记录是否进行y-轴对称翻转
// 迭代次数，因为Yn是可能中途收敛的，需要标注什么时候收敛了
reg [DATA_WIDTH-1:0] Nn [0:ITERATION-1];
// 还要记录旋转的角度
reg signed [DATA_WIDTH-1:0] Tn [0:ITERATION-1];
reg signed [DATA_WIDTH-1:0] T0n [0:ITERATION-1]; // 这是要从ROM里面加载的
reg signed [DATA_WIDTH-1:0] K0n [0:ITERATION-1]; // 这是要从ROM里面加载的
//
reg [4:0] cstate; // 状态计数器
parameter IDLE = 0; // 闲置状态
parameter LOAD = 1; // 加载ROM中的数据
parameter COMP = 2; // 正常的工作/运算阶段
reg [DATA_WIDTH-1:0] timer_in_state; // 每个阶段的计数器
reg [DATA_WIDTH-1:0] rom_address; // 读取ROM的地址计数器
// cordic 迭代运算 + 数据输入&1/4象限校正处理
always @(posedge sys_clk)
// 初始化
if(!sys_rst_n)
init_system_task;
// 否则就是正常的迭代计算
else
begin
case(cstate)
IDLE: prepare_load_task;
LOAD: execute_load_task;
COMP: execute_comp_task;
default: init_system_task;
endcase
end
///////////////////////////////
// 下面是具体的task的描述
integer n;
// 首先是系统初始化的描述
task init_system_task;
begin
cstate <= IDLE; // 首先切换到闲置状态
// 然后复位所有的寄存器
for(n=0; n<ITERATION; n=n+1)
begin
Xn[n] <= DATA_ZERO;
Yn[n] <= DATA_ZERO;
Nn[n] <= DATA_ZERO;
Tn[n] <= DATA_ZERO;
end
// 计数器复位
timer_in_state <= DATA_ZERO;
// 读取rom的地址计数器清零
rom_address <= 0;
end
endtask
////////////////////
// 然后是IDLE阶段，不直接进入load阶段，
// 主要是因为rom的读取是有latency时间的
task prepare_load_task;
begin
// 如果等待够了就要跳出，进入rom数据加载阶段
if(timer_in_state>=(ROM_LATENCY-1))
begin
cstate <= LOAD;
// 计数器复位
timer_in_state <= DATA_ZERO;
end
// 否则，就要继续加载ROM数据
else
begin
timer_in_state <= timer_in_state+1;
end
// rom读取不要停
rom_address <= rom_address+1;
end
endtask
// 然后是LOAD阶段，执行load指令
task execute_load_task;
begin
// 加载够了，就要跳出，可以开始计算了
if(timer_in_state>=(ITERATION))
begin
cstate <= COMP;
// 计数器复位
timer_in_state <= DATA_ZERO;
end
else
begin
// 否则，加载rom里面的数据
T0n[timer_in_state] <= THETAn;
K0n[timer_in_state] <= Kn;
rom_address <= rom_address+1;
timer_in_state <= timer_in_state+1;
end
end
endtask
// 现在是重头戏，就是整个coedic迭代过程了
task execute_comp_task;
begin
// 首先是校正输入数据进入1/4象限
Xn[0] <= src_x[DATA_WIDTH-1]? (~src_x+1) : src_x;
Sn[0] <= src_x[DATA_WIDTH-1];
Yn[0] <= src_y;
Nn[0] <= DATA_ZERO;
Tn[0] <= DATA_ZERO;
// 然后是cordic迭代的过程，这里使用for循环，方便写程序，注意综合结果
for(n=ITERATION-1; n>=1; n=n-1)
begin
// 如果Yn[n-1]>0，那么顺时针旋转
if(Yn[n-1]>EPSILON)
begin
Xn[n] <= Xn[n-1] + (Yn[n-1]>>>(n-1));
Yn[n] <= Yn[n-1] - (Xn[n-1]>>>(n-1));
Nn[n] <= Nn[n-1] + 1; // 继续迭代，迭代次数+1
Tn[n] <= Tn[n-1] + T0n[n-1]; // 修改角度值
end
// 如果Yn[n-1]<0，那么逆时针旋转
else if(Yn[n-1]<-EPSILON)
begin
Xn[n] <= Xn[n-1] - (Yn[n-1]>>>(n-1));
Yn[n] <= Yn[n-1] + (Xn[n-1]>>>(n-1));
Nn[n] <= Nn[n-1] + 1; // 继续迭代，迭代次数+1
Tn[n] <= Tn[n-1] - T0n[n-1]; // 修改角度值
end
// 否则就说明收敛了，停止迭代过程
else
begin
Xn[n] <= Xn[n-1];
Yn[n] <= Yn[n-1];
Nn[n] <= Nn[n-1];
Tn[n] <= Tn[n-1];
end
//
Sn[n] <= Sn[n-1];
end
end
endtask
//////////////////////////////////////////////////
// 最后，考虑到rom的ip核读取，需要给出ROM的读取地址
assign Kn_THETAn_address = rom_address;
// 然后是校正rho，需要Kn系数
// 注意到这里的Kn都是0~1的系数，所以我们存的时候，尽管是32bit的signed变量，实际中用到了31-bit
// 因此，最后输出的时候，需要做一些判断的
reg [2*DATA_WIDTH-1:0] rho_reg; // 这是校正向量模输出的时候的“暂存变量”，是64-bit的，最后要截掉LSB
reg [DATA_WIDTH-1:0] theta_reg; // 为了同步rho & theta而设置的register
always @(posedge sys_clk)
begin
if(Nn[ITERATION-1]==0)
rho_reg <= {Xn[ITERATION-1], DATA_ZERO} >>> 1; // // 这里有一个bug，之前没有意识到，主要是数据放大时候的bit问题
else
rho_reg <= Xn[ITERATION-1]*K0n[Nn[ITERATION-1]-1]; // 注意！ 这里是时序非常差的地方，要想办法调整
// 如果不涉及Y-axis翻转，直接输出角度
if(Sn[ITERATION-1]==0)
theta_reg <= Tn[ITERATION-1];
else
begin
if(Tn[ITERATION-1][DATA_WIDTH-1]) // 需要-pi-theta
theta_reg <= {1'B1, {(DATA_WIDTH-1){1'B0}}} - Tn[ITERATION-1];
else // 需要pi-theta
theta_reg <= {1'B0, {(DATA_WIDTH-1){1'B1}}} - Tn[ITERATION-1];
end
////////
rho <= rho_reg[2*DATA_WIDTH-1:DATA_WIDTH-1];
theta <= theta_reg;
end
endmodule |
module cordic_tanh_sigm_rtl
#(parameter DATA_WIDTH = 32, // Êý¾Ýλ¿í
parameter FRAC_WIDTH = 16, // СÊý²¿·Ö
parameter EPSILON = 16, // ÊÕÁ²ãÐÖµ
parameter ITERATION = 8, // µü´ú´ÎÊý
parameter ROM_LATENCY = 2, // romµÄIPºË¶ÁÈ¡ÐèÒªÑÓʱ
parameter DATA_UNIT = {{(DATA_WIDTH-FRAC_WIDTH-1){1'B0}}, 1'B1, {FRAC_WIDTH{1'B0}}}, // ¹Ì¶¨µÄµ¥Î»1
parameter DATA_ZERO = {DATA_WIDTH{1'B0}} // ¹Ì¶¨µÄ0Öµ
)
(
input wire sys_clk, sys_rst_n,
input wire [DATA_WIDTH-1:0] src_x,
output wire [DATA_WIDTH-1:0] rho,
input wire [1:0] algorithm // 10--tanh, 01--sigmoid
);
// ÐèÒªÒ»¸ö¼ÇÒäÆ÷
reg [1:0] algorithm_reg [0:ITERATION+4];
integer n;
always @(posedge sys_clk)
if(!sys_rst_n)
begin
for(n=0; n<ITERATION+5; n=n+1)
algorithm_reg[n] <= 2'B00;
end
else
begin
for(n=ITERATION+4; n>=1; n=n-1)
algorithm_reg[n] <= algorithm_reg[n-1];
algorithm_reg[0] <= algorithm;
end
// Ê×ÏÈÒªÓÐexp(2x)Ö¸ÊýÔËËãµÄ½á¹û
wire [31:0] rho_exp;
wire [31:0] src_x_exp = (algorithm==2'B10)? {src_x[DATA_WIDTH-2:0], 1'B0} :
(algorithm==2'B01)? {src_x[DATA_WIDTH-1:0]} :
0;
cordic_exp_rtl cordic_exp_mdl(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.src_x(src_x_exp), .rho(rho_exp));
// È»ºóÊdzý·¨ÔËËã2/(exp(2x)+1)
wire [31:0] rho_div;
wire [35:0] numer_div = (algorithm_reg[ITERATION+4]==2'B10)? {DATA_UNIT, 1'B0} :
(algorithm_reg[ITERATION+4]==2'B01)? {DATA_UNIT} :
0;
fixed_sdiv fixed_sdiv_inst(.sys_clk(sys_clk),.sys_rst_n(sys_rst_n),.denom((rho_exp+DATA_UNIT)),.numer(numer_div),.quotient(rho_div));
// ×îºóÊä³ö1-2/(exp(2x)+1)
assign rho = DATA_UNIT-rho_div[DATA_WIDTH-1:0];
endmodule |
module openFPGA_Pocket_Analogizer #(parameter MASTER_CLK_FREQ=50_000_000) (
input wire i_clk,
input wire i_rst,
input wire i_ena,
//Video interface
input wire [3:0] analog_video_type,
input wire [7:0] R,
input wire [7:0] G,
input wire [7:0] B,
input wire Hblank,
input wire Vblank,
input wire BLANKn,
input wire Hsync,
input wire Vsync,
input wire Csync,
input wire video_clk,
//Video Y/C Encoder interface
input wire PALFLAG,
//input wire CVBS,
input wire MULFLAG,
input wire [4:0] CHROMA_ADD,
input wire [4:0] CHROMA_MULT,
input wire [39:0] CHROMA_PHASE_INC,
input wire [26:0] COLORBURST_RANGE,
//Video SVGA Scandoubler interface
input wire [2:0] ce_divider,
//SNAC interface
input wire conf_AB, //0 conf. A(default), 1 conf. B (see graph above)
input wire [4:0] game_cont_type, //0-15 Conf. A, 16-31 Conf. B
output wire [15:0] p1_btn_state,
output wire [15:0] p2_btn_state,
output wire [15:0] p3_btn_state,
output wire [15:0] p4_btn_state,
output wire busy,
//Pocket Analogizer IO interface to the cartridge port
inout wire [7:0] cart_tran_bank2,
output wire cart_tran_bank2_dir,
inout wire [7:0] cart_tran_bank3,
output wire cart_tran_bank3_dir,
inout wire [7:0] cart_tran_bank1,
output wire cart_tran_bank1_dir,
inout wire [7:4] cart_tran_bank0,
output wire cart_tran_bank0_dir,
inout wire cart_tran_pin30,
output wire cart_tran_pin30_dir,
output wire cart_pin30_pwroff_reset,
inout wire cart_tran_pin31,
output wire cart_tran_pin31_dir,
//debug
output wire o_stb
);
wire [7:4] CART_BK0_OUT ;
wire [7:4] CART_BK0_IN ;
wire CART_BK0_DIR ;
wire [7:6] CART_BK1_OUT_P76 ;
wire CART_PIN30_OUT ;
wire CART_PIN30_IN ;
wire CART_PIN30_DIR ;
wire CART_PIN31_OUT ;
wire CART_PIN31_IN ;
wire CART_PIN31_DIR ;
openFPGA_Pocket_Analogizer_SNAC #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) snac
(
.i_clk(i_clk),
.i_rst(i_rst),
.conf_AB(conf_AB), //0 conf. A(default), 1 conf. B (see graph above)
.game_cont_type(game_cont_type), //0-15 Conf. A, 16-31 Conf. B
//.game_cont_sample_rate(game_cont_sample_rate), //0 compatibility mode (slowest), 1 normal mode, 2 fast mode, 3 superfast mode
.p1_btn_state(p1_btn_state),
.p2_btn_state(p2_btn_state),
.p3_btn_state(p3_btn_state),
.p4_btn_state(p4_btn_state),
.busy(busy),
//SNAC Pocket cartridge port interface (see graph above)
.CART_BK0_OUT(CART_BK0_OUT),
.CART_BK0_IN(CART_BK0_IN),
.CART_BK0_DIR(CART_BK0_DIR),
.CART_BK1_OUT_P76(CART_BK1_OUT_P76),
.CART_PIN30_OUT(CART_PIN30_OUT),
.CART_PIN30_IN(CART_PIN30_IN),
.CART_PIN30_DIR(CART_PIN30_DIR),
.CART_PIN31_OUT(CART_PIN31_OUT),
.CART_PIN31_IN(CART_PIN31_IN),
.CART_PIN31_DIR(CART_PIN31_DIR),
//debug
.o_stb(o_stb)
);
//Choose type of analog video type of signal
reg [5:0] Rout, Gout, Bout;
reg HsyncOut, VsyncOut, BLANKnOut;
wire [7:0] Yout, PrOut, PbOut;
wire [5:0] R_Sd, G_Sd, B_Sd;
wire Hsync_Sd, Vsync_Sd;
wire Hblank_Sd, Vblank_Sd;
wire BLANKn_SD = ~(Hblank_Sd || Vblank_Sd);
always @(*) begin
case(analog_video_type)
4'h0, 4'h8: begin //RGBS
Rout = R[7:2]&{6{BLANKn}};
Gout = G[7:2]&{6{BLANKn}};
Bout = B[7:2]&{6{BLANKn}};
HsyncOut = Csync;
VsyncOut = 1'b1;
BLANKnOut = BLANKn;
end
4'h3, 4'h4, 4'hB, 4'hC: begin// Y/C Modes works for Analogizer R1, R2 Adapters
Rout = yc_o[23:18];
Gout = yc_o[15:10];
Bout = yc_o[7:2];
HsyncOut = yc_cs;
VsyncOut = 1'b1;
BLANKnOut = 1'b1;
end
4'h1, 4'h9: begin //RGsB
Rout = R[7:2]&{6{BLANKn}};
Gout = G[7:2]&{6{BLANKn}};
Bout = B[7:2]&{6{BLANKn}};
HsyncOut = 1'b1;
VsyncOut = Csync; //to DAC SYNC pin, SWITCH SOG ON
BLANKnOut = BLANKn;
end
4'h2, 4'hA: begin //YPbPr
Rout = PrOut[7:2];
Gout = Yout[7:2];
Bout = PbOut[7:2];
HsyncOut = 1'b1;
VsyncOut = YPbPr_sync; //to DAC SYNC pin, SWITCH SOG ON
BLANKnOut = 1'b1; //ADV7123 needs this
end
4'h5, 4'hD: begin //Scandoubler modes
Rout = R_Sd;
Gout = G_Sd;
Bout = B_Sd;
HsyncOut = Hsync_Sd;
VsyncOut = Vsync_Sd;
BLANKnOut = 1'b1;
end
default: begin
Rout = 6'h0;
Gout = 6'h0;
Bout = 6'h3F;
HsyncOut = Hsync;
VsyncOut = 1'b1;
BLANKnOut = BLANKn;
end
endcase
end
wire YPbPr_sync, YPbPr_blank;
vga_out ybpr_video
(
.clk(video_clk),
.ypbpr_en(1'b1),
.csync(Csync),
.de(BLANKn),
.din({R&{8{BLANKn}},G&{8{BLANKn}},B&{8{BLANKn}}}), //NES specific override, because not zero color data while blanking period.
.dout({PrOut,Yout,PbOut}),
.csync_o(YPbPr_sync),
.de_o(YPbPr_blank)
);
wire [23:0] yc_o;
//wire yc_hs, yc_vs,
wire yc_cs;
yc_out yc_out
(
.clk(i_clk),
.PAL_EN(PALFLAG),
.CVBS(1'b0),
.PHASE_INC(CHROMA_PHASE_INC),
.COLORBURST_RANGE(COLORBURST_RANGE),
.MULFLAG(MULFLAG),
.CHRADD(CHROMA_ADD), //fine tune 0-31
.CHRMUL(CHROMA_MULT), //fine tune 0-31
.hsync(Hsync),
.vsync(Vsync),
.csync(Csync),
.dout(yc_o),
//.din(rgb_color_r),
.din({R&{8{BLANKn}},G&{8{BLANKn}},B&{8{BLANKn}}}),
.hsync_o(),
.vsync_o(),
.csync_o(yc_cs)
);
//delay hsync one pixel clock period
// reg [1:0] delayed_hsync = 0;
// reg pclk_r = 0;
// always @(posedge i_clk) begin
// pclk_r <= video_clk;
// if(!pclk_r && video_clk) begin
// delayed_hsync[0] <= Hsync;
// delayed_hsync[1] <= delayed_hsync[0];
// end
// end
scandoubler sc_video
(
// system interface
.clk_sys(i_clk),
.bypass(1'b0),
// Pixelclock
.ce_divider(ce_divider), // 0 - clk_sys/4, 1 - clk_sys/2, 2 - clk_sys/3, 3 - clk_sys/4, etc.
//.ce_divider(3'd0), // 0 - clk_sys/4, 1 - clk_sys/2, 2 - clk_sys/3, 3 - clk_sys/4, etc.
.pixel_ena(), //output
.scanlines(2'd2), // scanlines (00-none 01-25% 10-50% 11-75%)
// shifter video interface
.hb_in(Hblank),
.vb_in(Vblank),
.hs_in(Hsync),
//.hs_in(delayed_hsync[1]),
.vs_in(Vsync),
.r_in({R[7:2]&{6{BLANKn}}}),
.g_in({G[7:2]&{6{BLANKn}}}),
.b_in({B[7:2]&{6{BLANKn}}}),
// output interface
.hb_out(Hblank_Sd),
.vb_out(Vblank_Sd),
.hs_out(Hsync_Sd),
.vs_out(Vsync_Sd),
.r_out(R_Sd),
.g_out(G_Sd),
.b_out(B_Sd)
);
//infer tri-state buffers for cartridge data signals
//BK0
assign cart_tran_bank0 = i_rst | ~i_ena ? 4'hf : ((CART_BK0_DIR) ? CART_BK0_OUT : 4'hZ); //on reset state set ouput value to 4'hf
assign cart_tran_bank0_dir = i_rst | ~i_ena ? 1'b1 : CART_BK0_DIR; //on reset state set pin dir to output
assign CART_BK0_IN = cart_tran_bank0;
//BK3
assign cart_tran_bank3 = i_rst | ~i_ena ? 8'hzz : {Rout[5:0],HsyncOut,VsyncOut}; //on reset state set ouput value to 8'hZ
assign cart_tran_bank3_dir = i_rst | ~i_ena ? 1'b0 : 1'b1; //on reset state set pin dir to input
//BK2
assign cart_tran_bank2 = i_rst | ~i_ena ? 8'hzz : {Bout[0],BLANKnOut,Gout[5:0]}; //on reset state set ouput value to 8'hZ
assign cart_tran_bank2_dir = i_rst | ~i_ena ? 1'b0 : 1'b1; //on reset state set pin dir to input
//BK1
assign cart_tran_bank1 = i_rst | ~i_ena ? 8'hzz : {CART_BK1_OUT_P76,video_clk,Bout[5:1]}; //on reset state set ouput value to 8'hZ
assign cart_tran_bank1_dir = i_rst | ~i_ena ? 1'b0 : 1'b1; //on reset state set pin dir to input
//PIN30
assign cart_tran_pin30 = i_rst | ~i_ena ? 1'bz : ((CART_PIN30_DIR) ? CART_PIN30_OUT : 1'bZ); //on reset state set ouput value to 4'hf
assign cart_tran_pin30_dir = i_rst | ~i_ena ? 1'b0 : CART_PIN30_DIR; //on reset state set pin dir to output
assign CART_PIN30_IN = cart_tran_pin30;
assign cart_pin30_pwroff_reset = i_rst | ~i_ena ? 1'b0 : 1'b1; //1'b1 (GPIO USE)
//PIN31
assign cart_tran_pin31 = i_rst | ~i_ena ? 1'bz : ((CART_PIN31_DIR) ? CART_PIN31_OUT : 1'bZ); //on reset state set ouput value to 4'hf
assign cart_tran_pin31_dir = i_rst | ~i_ena ? 1'b0 : CART_PIN31_DIR; //on reset state set pin dir to input
assign CART_PIN31_IN = cart_tran_pin31;
endmodule |
module openFPGA_Pocket_Analogizer_SNAC #(parameter MASTER_CLK_FREQ=50_000_000)
(
input wire i_clk, //Core Master Freq.
input wire i_rst, //Core general reset
input wire conf_AB, //0 conf. A(default), 1 conf. B (see graph above)
input wire [4:0] game_cont_type, //0-15 Conf. A, 16-31 Conf. B
//input wire [2:0] game_cont_sample_rate, //0 compatibility mode (slowest), 1 normal mode, 2 fast mode, 3 superfast mode
output reg [15:0] p1_btn_state,
output reg [15:0] p2_btn_state,
output reg [15:0] p3_btn_state,
output reg [15:0] p4_btn_state,
output reg busy,
//SNAC Pocket cartridge port interface (see graph above)
output reg [7:4] CART_BK0_OUT,
input wire [7:4] CART_BK0_IN,
output reg CART_BK0_DIR,
output reg [7:6] CART_BK1_OUT_P76,
output reg CART_PIN30_OUT,
input wire CART_PIN30_IN,
output reg CART_PIN30_DIR,
output reg CART_PIN31_OUT,
input wire CART_PIN31_IN,
output reg CART_PIN31_DIR,
//debug
output wire o_stb
);
//
reg SNAC_OUT1 /* synthesis preserve */; //cart_tran_bank1[6] D-
reg SNAC_OUT2 /* synthesis preserve */; //cart_tran_bank1[7] D+
reg SNAC_IO3_A /* synthesis preserve */;//Conf.A: cart_tran_bank0[4] (in), Conf.B: pin30(out) RX-
reg SNAC_IO3_B /* synthesis preserve */;//Conf.A: cart_tran_bank0[4] (in), Conf.B: pin30(out) RX-
reg SNAC_IN4 /* synthesis preserve */; //cart_tran_bank0[7] RX+
wire SNAC_IO5_A /* synthesis preserve */;//Conf.A: pin30(out), Conf.B: cart_tran_bank1[6] GND_D
reg SNAC_IO5_B /* synthesis preserve */;//Conf.A: pin30(out), Conf.B: cart_tran_bank1[6] GND_D
reg SNAC_IO6_A /* synthesis preserve */;//Conf.A: pin31(in), Conf.B: pin31(out) TX-
reg SNAC_IO6_B /* synthesis preserve */;//Conf.A: pin31(in), Conf.B: pin31(out) TX-
reg SNAC_IN7 /* synthesis preserve */; //cart_tran_bank0[5] TX+
//calculate step sizes for fract clock enables
// localparam pce_compat_polling_freq = 20_000; // 20_000 / 5 = 4K samples/sec PCE
localparam pce_normal_polling_freq = 40_000; // 40_000 / 5 = 8K samples/sec PCE
localparam pce_fast_polling_freq = 80_000; // 80_000 / 5 = 16K samples/sec PCE
// localparam pce_very_fast_polling_freq = 100_000; // 100_000 / 5 = 20K samples/sec PCE
// localparam Compat_60Hz_polling_freq = 1_080; //
// localparam Compat_120Hz_polling_freq = 2_160; //
localparam snes_compat_polling_freq = 50_000; //
// localparam serlatch_compat_polling_freq = 100_000; // 100_000 / 25 = 4K samples/sec DB15 100_000 / 18 = 5.55K samples/sec NES/SNES
localparam serlatch_normal_polling_freq = 200_000; // 200_000 / 25 = 8K samples/sec DB15 200_000 / 18 = 11.11K samples/sec NES/SNES
localparam serlatch_fast_polling_freq = 400_000; // 400_000 / 25 = 16K samples/sec DB15 400_000 / 18 = 22.22K samples/sec NES/SNES
// localparam serlatch_very_fast_polling_freq = 1_000_000; //1_000_000 / 25 = 32K samples/sec DB15 1_000_000 / 18 = 55.55K samples/sec NES/SNES
//the FSM is clocked 2x the polling freq.
localparam [32:0] MAX_INT = 33'h0ffffffff;
// localparam [64:0] pce_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * pce_compat_polling_freq * 2) / 1000;
// localparam [32:0] pce_compat_pstep = pce_compat_pstep_[32:0];
localparam [64:0] pce_normal_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * pce_normal_polling_freq * 2) / 1000;
localparam [32:0] pce_normal_pstep = pce_normal_pstep_[32:0];
localparam [64:0] pce_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) *pce_fast_polling_freq * 2) / 1000;
localparam [32:0] pce_fast_pstep = pce_fast_pstep_[32:0];
// localparam [64:0] pce_very_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) *pce_very_fast_polling_freq * 2) / 1000;
// localparam [32:0] pce_very_fast_pstep = pce_very_fast_pstep_[32:0];
// localparam [64:0] serlatch_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_compat_polling_freq * 2) / 1000;
// localparam [32:0] serlatch_compat_pstep = serlatch_compat_pstep_[32:0];
localparam [64:0] serlatch_normal_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_normal_polling_freq * 2) / 1000;
localparam [32:0] serlatch_normal_pstep = serlatch_normal_pstep_[32:0];
localparam [64:0] serlatch_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_fast_polling_freq * 2) / 1000;
localparam [32:0] serlatch_fast_pstep = serlatch_fast_pstep_[32:0];
// localparam [64:0] serlatch_very_fast_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * serlatch_very_fast_polling_freq * 2) / 1000;
// localparam [32:0] serlatch_very_fast_pstep = serlatch_very_fast_pstep_[32:0];
localparam [64:0] snes_compat_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * snes_compat_polling_freq * 2) / 1000;
localparam [32:0] snes_compat_pstep = snes_compat_pstep_[32:0];
// localparam [64:0] Compat_60Hz_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * Compat_60Hz_polling_freq * 2) / 1000;
// localparam [32:0] Compat_60Hz_pstep = Compat_60Hz_pstep_[32:0];
// localparam [64:0] Compat_120Hz_pstep_ = ((MAX_INT / (MASTER_CLK_FREQ / 1000)) * Compat_120Hz_polling_freq * 2) / 1000;
// localparam [32:0] Compat_120Hz_pstep = Compat_120Hz_pstep_[32:0];
//Supported game controller types
localparam GC_DISABLED = 5'h0;
localparam GC_DB15 = 5'h1;
localparam GC_NES = 5'h2;
localparam GC_SNES = 5'h3;
localparam GC_PCE_2BTN = 5'h4;
localparam GC_PCE_6BTN = 5'h5;
localparam GC_PCE_MULTITAP = 5'h6;
localparam GC_DB15_FAST = 5'h9;
localparam GC_SNES_SWAP = 5'hB;
//parameter GC_PSX= 5'h16;
//Configuration:
localparam CONF_A = 1'b0;
localparam CONF_B = 1'b1;
reg conf_AB_r;
reg [4:0] game_cont_type_r;
// reg [2:0] game_cont_sample_rate_r;
reg [32:0] strobe_step_size;
reg reset_on_change;
always @(posedge i_clk) begin
//register SNAC settings
conf_AB_r <= conf_AB;
game_cont_type_r <= game_cont_type;
//game_cont_sample_rate_r <= game_cont_sample_rate;
//detect change of SNAC settings and reset clock divider and set new settings
reset_on_change <= 1'b0;
//if(i_rst || (game_cont_type_r != game_cont_type) || (game_cont_sample_rate_r != game_cont_sample_rate)) begin
if(i_rst || (game_cont_type_r != game_cont_type)) begin
reset_on_change <= 1'b1;
end
end
reg serlat_ena;
reg pce_ena;
always @(posedge i_clk) begin
serlat_ena <= 1'b0;
pce_ena <= 1'b0;
case (game_cont_type)
GC_DB15: begin
serlat_ena <= 1'b1;
strobe_step_size <= serlatch_normal_pstep;
// case (game_cont_sample_rate)
// 0: begin strobe_step_size <= serlatch_compat_pstep; end
// 1: begin strobe_step_size <= serlatch_normal_pstep; end
// 2: begin strobe_step_size <= serlatch_fast_pstep; end
// // 3: begin strobe_step_size <= serlatch_very_fast_pstep; end
// // 4: begin strobe_step_size <= snes_compat_pstep; end
// // 5: begin strobe_step_size <= Compat_60Hz_pstep; end
// // 6: begin strobe_step_size <= Compat_120Hz_pstep; end
// default: begin strobe_step_size <= serlatch_compat_pstep ; end
// endcase
end
GC_DB15_FAST: begin
serlat_ena <= 1'b1;
strobe_step_size <= serlatch_fast_pstep;
end
GC_NES, GC_SNES, GC_SNES_SWAP: begin
serlat_ena <= 1'b1;
strobe_step_size <= snes_compat_pstep;
// case (game_cont_sample_rate)
// 0: begin strobe_step_size <= serlatch_compat_pstep ; end
// 1: begin strobe_step_size <= serlatch_normal_pstep; end
// 2: begin strobe_step_size <= serlatch_fast_pstep; end
// // 3: begin strobe_step_size <= serlatch_very_fast_pstep; end
// // 4: begin strobe_step_size <= snes_compat_pstep; end
// // 5: begin strobe_step_size <= Compat_60Hz_pstep; end
// // 6: begin strobe_step_size <= Compat_120Hz_pstep; end
// default: begin strobe_step_size <= serlatch_compat_pstep ; end
// endcase
end
GC_PCE_2BTN, GC_PCE_6BTN: begin
pce_ena <= 1'b1;
strobe_step_size <= pce_normal_pstep;
// case (game_cont_sample_rate)
// 0: begin strobe_step_size <= pce_compat_pstep; end
// 1: begin strobe_step_size <= pce_normal_pstep; end
// 2: begin strobe_step_size <= pce_fast_pstep; end
// 3: begin strobe_step_size <= pce_very_fast_pstep; end
// default: begin strobe_step_size <= pce_compat_pstep; end
// endcase
end
GC_PCE_MULTITAP: begin
pce_ena <= 1'b1;
strobe_step_size <= pce_fast_pstep;
end
default: //disabled
strobe_step_size <= 33'h0;
endcase
end
always @(posedge i_clk) begin
case (conf_AB)
CONF_A: begin
CART_BK0_DIR <= 1'b0; //INPUT
{SNAC_IN4,SNAC_IN7,SNAC_IO3_A} <= {CART_BK0_IN[7],CART_BK0_IN[5],CART_BK0_IN[4]}; //OUTPUT
CART_BK1_OUT_P76 <= {SNAC_OUT2,SNAC_OUT1}; //OUTPUT
CART_PIN30_DIR <= 1'b1; //OUTPUT
CART_PIN30_OUT <= SNAC_IO5_A;
CART_PIN31_DIR <= 1'b0; //INPUT
SNAC_IO6_A <= CART_PIN31_IN;
end
CONF_B: begin
CART_BK0_DIR <= 1'b0; //INPUT
{SNAC_IN4,SNAC_IO5_B,SNAC_IN7} <= {CART_BK0_IN[7],CART_BK0_IN[6],CART_BK0_IN[5]}; //OUTPUT
CART_BK1_OUT_P76 <= {SNAC_OUT2,SNAC_OUT1}; //OUTPUT
CART_PIN30_DIR <= 1'b1; //OUTPUT
CART_PIN30_OUT <= SNAC_IO3_B;
CART_PIN31_DIR <= 1'b1; //OUTPUT
CART_PIN31_OUT <= SNAC_IO6_B;
end
endcase
end
wire stb_clk /* synthesis keep */;
clock_divider_fract ckdiv(
.i_clk (i_clk),
.i_rst(reset_on_change), //reset on polling freq change
.i_step(strobe_step_size[31:0]),
.o_stb (stb_clk)
);
wire dbg_clk_w;
reg dbg_clk /* synthesis noprune */;
clock_divider_fract dbgckdiv(
.i_clk (i_clk),
.i_rst(reset_on_change), //reset on polling freq change
.i_step({strobe_step_size[29:0],2'b00}),
.o_stb (dbg_clk_w)
);
always @(posedge i_clk) dbg_clk <= dbg_clk_w;
assign o_stb = stb_clk;
//DB15/NES/SNES game controller
wire [15:0] sl_p1 /* synthesis keep */;
wire [15:0] sl_p2 /* synthesis keep */;
wire SERLAT_SNAC_OUT1 /* synthesis keep */;
wire SERLAT_SNAC_OUT2 /* synthesis keep */;
//wire SERLAT_SNAC_IO5_A /* synthesis keep */;
serlatch_game_controller #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) slgc
(
.i_clk(i_clk),
.i_rst(reset_on_change),
.game_controller_type(game_cont_type[3:0]), //0x1 DB15, 0x2 NES, 0x3 SNES, 0x9 DB15 FAST, 0XB SNES SWAP A,B<->X,Y
.i_stb(stb_clk),
.p1_btn_state(sl_p1),
.p2_btn_state(sl_p2),
.busy(),
//SNAC Game controller interface
.o_clk(SERLAT_SNAC_OUT1), //shared for 2 controllers
.o_clk2(SNAC_IO5_A),
.o_lat(SERLAT_SNAC_OUT2), //shared for 2 controllers
.i_dat1(SNAC_IO3_A), //data from controller 1
.i_dat2(SNAC_IN7) //data from controller 2
);
//PCENGINE game controller
wire [15:0] pce_p1 /* synthesis keep */;
wire PCE_SNAC_OUT1 /* synthesis keep */;
wire PCE_SNAC_OUT2 /* synthesis keep */;
pcengine_game_controller #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ), .PULSE_CLR_LINE(1'b1)) pcegc1
(
.i_clk(i_clk),
.i_rst(reset_on_change),
.game_controller_type(game_cont_type[3:0]), //0X4 2btn, 0X5 6btn
.i_stb(stb_clk),
.player_btn_state(pce_p1),
.busy(),
//SNAC Game controller interface
.o_clr(PCE_SNAC_OUT1), //shared for 2 controllers
.o_sel(PCE_SNAC_OUT2), //shared for 2 controllers
.i_dat({SNAC_IN7,SNAC_IO3_A,SNAC_IO6_A,SNAC_IN4}) //data from controller
);
wire [15:0] pce_multitap_p1, pce_multitap_p2, pce_multitap_p3, pce_multitap_p4;
wire PCE_MULTITAP_SNAC_OUT1, PCE_MULTITAP_SNAC_OUT2;
pcengine_game_controller_multitap #(.MASTER_CLK_FREQ(MASTER_CLK_FREQ)) pcegmutitap
(
.i_clk(i_clk),
.i_rst(reset_on_change),
.game_controller_type(game_cont_type[3:0]), //0x6 multitap
.i_stb(stb_clk),
.player1_btn_state(pce_multitap_p1),
.player2_btn_state(pce_multitap_p2),
.player3_btn_state(pce_multitap_p3),
.player4_btn_state(pce_multitap_p4),
.player5_btn_state(),
.busy(),
//SNAC Game controller interface
.o_clr(PCE_MULTITAP_SNAC_OUT1), //shared for 2 controllers
.o_sel(PCE_MULTITAP_SNAC_OUT2), //shared for 2 controllers
.i_dat({SNAC_IN7,SNAC_IO3_A,SNAC_IO6_A,SNAC_IN4}) //data from controller
);
always @(*) begin
case(game_cont_type)
GC_DISABLED: begin
SNAC_OUT1 = 1'b0;
SNAC_OUT2 = 1'b0;
p1_btn_state = 16'h0;
p2_btn_state = 16'h0;
p3_btn_state = 16'h0;
p4_btn_state = 16'h0;
end
GC_DB15, GC_DB15_FAST, GC_NES, GC_SNES, GC_SNES_SWAP: begin
SNAC_OUT1 = SERLAT_SNAC_OUT1;
SNAC_OUT2 = SERLAT_SNAC_OUT2;
p1_btn_state = sl_p1;
p2_btn_state = sl_p2;
p3_btn_state = 16'h0;
p4_btn_state = 16'h0;
end
GC_PCE_2BTN, GC_PCE_6BTN: begin
SNAC_OUT1 = PCE_SNAC_OUT1;
SNAC_OUT2 = PCE_SNAC_OUT2;
p1_btn_state = pce_p1;
p2_btn_state = 16'h0;
p3_btn_state = 16'h0;
p4_btn_state = 16'h0;
end
GC_PCE_MULTITAP: begin
SNAC_OUT1 = PCE_MULTITAP_SNAC_OUT1;
SNAC_OUT2 = PCE_MULTITAP_SNAC_OUT2;
p1_btn_state = pce_multitap_p1;
p2_btn_state = pce_multitap_p2;
p3_btn_state = pce_multitap_p3;
p4_btn_state = pce_multitap_p4;
end
default: begin
SNAC_OUT1 = 1'b0;
SNAC_OUT2 = 1'b0;
p1_btn_state = 16'h0;
p2_btn_state = 16'h0;
p3_btn_state = 16'h0;
p4_btn_state = 16'h0;
end
endcase
end
endmodule |
module pcengine_game_controller #(parameter MASTER_CLK_FREQ=50_000_000, parameter PULSE_CLR_LINE=1'b0)
(
input wire i_clk,
input wire i_rst,
input wire [3:0] game_controller_type, //0X4 2btn,0X5 6btn
input wire i_stb,
output reg [15:0] player_btn_state,
output reg busy,
//SNAC Game controller interface
output wire o_clr,
output wire o_sel,
input wire [3:0] i_dat //data from controller
);
//FSM states
parameter IDLE = 3'b001;
parameter CLR = 3'b010;
parameter DATA = 3'b100;
//store module settings
reg [3:0] game_controller_type_r;
wire pulse_clr = PULSE_CLR_LINE;
reg [2:0] state /* synthesis preserve */;
reg [3:0] counter;
reg [3:0] scan_number;
reg [3:0] counter_top_value;
reg clr_internal;
reg sel_internal;
reg [11:0] pb_r;
wire latch_level,disable_clock_on_latch;
wire sample_data;
reg btn6;
//always sample data at falling edge of o_clk starting and second clock pulse in latch phase.
assign sample_data = ~counter[0] && i_stb && (counter > 0) && (counter <= counter_top_value);
always @(posedge i_clk) begin
game_controller_type_r <= game_controller_type;
//detect any change on gamepad configuration and restart FSM at IDLE state.
if(i_rst || (game_controller_type != game_controller_type_r)) begin
state <= IDLE;
pb_r <= 12'hfff;
end
else begin
if(i_stb) begin
case(state)
IDLE:
begin
//fetch data from last read
//button order from first to last
//0 1 2 3 4 5 6 7 8 9 10 11
//UP RIGHT DOWN LEFT I II SELECT RUN III IV V VI
//follow Pocket game controls order: D C B A E F
if(game_controller_type_r == 4'h5) begin
//6btn mapping
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP
player_btn_state <= ~{pb_r[7], pb_r[6], 4'b1111, pb_r[11], pb_r[10], pb_r[9], pb_r[8], pb_r[5], pb_r[4], pb_r[1], pb_r[3], pb_r[2], pb_r[0]};
end
else if (game_controller_type_r == 4'h4) begin
//2btn mapping RUN+A = X, RUN+B = Y not implemented
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP
player_btn_state <= ~{pb_r[7], pb_r[6], 6'b111111, 1'b1, 1'b1, pb_r[5], pb_r[4], pb_r[1], pb_r[3], pb_r[2], pb_r[0]};
end
else begin
player_btn_state <= 16'h0;
end
counter <= 0;
scan_number <= 0;
// if (game_controller_type_r == 5'd4) counter_top_value <= 4'd4;
// else if(game_controller_type_r == 5'd5) counter_top_value <= 4'd8;
counter_top_value <= 4'd4;
sel_internal <= 1'b1;
clr_internal <= pulse_clr;
busy <= 1'b1;
//if (~btn6) pb_r <= 12'hfff;
state <= CLR;
end
CLR:
begin
counter <= counter + 1;
if (counter == 1) begin
state <= DATA;
sel_internal <= 1'b1;
clr_internal <= 1'b0;
end
end
DATA:
begin
counter <= counter + 1; //should be start clocking at 3
//following data samples are get in DATA phase.
if(counter[0]) begin
sel_internal <= ~sel_internal;
scan_number <= scan_number + 1;
end
if(sample_data) begin//read button state
case(scan_number)
0: begin
if(i_dat == 4'b0000) begin
btn6 <= 1'b1;
//pb_r[3:0] <= pb_r[3:0];
end
else begin
btn6 <= 1'b0;
pb_r[3:0] <= i_dat;
end
end
1: begin
if(btn6) begin
pb_r[11:8] <= i_dat;
end
else begin
pb_r[7:4] <= i_dat;
end
//btn6 <= 1'b0;
end
// 3: pb_r[11:8] <= i_dat;
default: pb_r <= pb_r;
endcase
end
//the gamepads buton state are fetched at the end of DATA phase
if(counter == counter_top_value) begin
state <= IDLE;
busy <= 1'b0;
end
end
endcase
end
end
end
assign o_clr = (game_controller_type_r == 4'd0) ? 1'b0 : clr_internal;
assign o_sel = (game_controller_type_r == 4'd0) ? 1'b0 : sel_internal;
endmodule |
module pcengine_game_controller_multitap #(parameter MASTER_CLK_FREQ=50_000_000)
(
input wire i_clk,
input wire i_rst,
input wire [3:0] game_controller_type, //0x4 2btn, 0x5 6btn, 0x6 multitap
input wire i_stb,
output reg [15:0] player1_btn_state,
output reg [15:0] player2_btn_state,
output reg [15:0] player3_btn_state,
output reg [15:0] player4_btn_state,
output reg [15:0] player5_btn_state,
output reg busy,
//SNAC Game controller interface
output wire o_clr,
output wire o_sel,
input wire [3:0] i_dat //data from controller
);
//FSM states
parameter IDLE = 3'b001;
parameter CLR = 3'b010;
parameter PRE_CLR = 3'b011;
parameter DATA = 3'b100;
//store module settings
reg [3:0] game_controller_type_r;
reg [6:0] state /* synthesis preserve */;
reg [4:0] counter;
reg [4:0] scan_number;
reg [4:0] counter_top_value;
reg clr_internal;
reg sel_internal;
reg [11:0] pb1_r, pb2_r, pb3_r, pb4_r, pb5_r;
wire sample_data;
//always sample data at falling edge of o_clk starting and second clock pulse in latch phase.
assign sample_data = ~counter[0] && i_stb && (counter > 0) && (counter <= counter_top_value);
always @(posedge i_clk) begin
game_controller_type_r <= game_controller_type;
//detect any change on gamepad configuration and restart FSM at IDLE state.
if(i_rst || (game_controller_type != game_controller_type_r)) begin
state <= IDLE;
pb1_r <= 12'hfff;
pb2_r <= 12'hfff;
pb3_r <= 12'hfff;
pb4_r <= 12'hfff;
pb5_r <= 12'hfff;
end
else begin
if(i_stb) begin
case(state)
IDLE:
begin
//fetch data from last read
//button order from first to last
//0 1 2 3 4 5 6 7 8 9 10 11
//UP RIGHT DOWN LEFT I II SELECT RUN III IV V VI
//follow Pocket game controls order: D C B A E F
// up down left right btn_y btn_x btn_b btn_a btn_l1 btn_r1 btn_l2 btn_r2 btn_l3 btn_r3 select start
//player_btn_state <= ~{pb_r[0], pb_r[2], pb_r[3], pb_r[1], pb_r[9], pb_r[8], pb_r[5], pb_r[4], pb_r[10], pb_r[11], 1'b1, 1'b1, 1'b1, 1'b1,pb_r[6],pb_r[7]};
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP
player1_btn_state <= ~{pb1_r[7], pb1_r[6], 8'b11111111, pb1_r[5], pb1_r[4],pb1_r[1], pb1_r[3], pb1_r[2], pb1_r[0]};
player2_btn_state <= ~{pb2_r[7], pb2_r[6], 8'b11111111, pb2_r[5], pb2_r[4],pb2_r[1], pb2_r[3], pb2_r[2], pb2_r[0]};
player3_btn_state <= ~{pb3_r[7], pb3_r[6], 8'b11111111, pb3_r[5], pb3_r[4],pb3_r[1], pb3_r[3], pb3_r[2], pb3_r[0]};
player4_btn_state <= ~{pb4_r[7], pb4_r[6], 8'b11111111, pb4_r[5], pb4_r[4],pb4_r[1], pb4_r[3], pb4_r[2], pb4_r[0]};
player5_btn_state <= ~{pb5_r[7], pb5_r[6], 8'b11111111, pb5_r[5], pb5_r[4],pb5_r[1], pb5_r[3], pb5_r[2], pb5_r[0]};
counter <= 0;
scan_number <= 0;
counter_top_value <= 5'd12;
sel_internal <= 1'b1;
clr_internal <= 1'b0;
busy <= 1'b1;
pb1_r <= 12'hfff;
pb2_r <= 12'hfff;
pb3_r <= 12'hfff;
pb4_r <= 12'hfff;
pb5_r <= 12'hfff;
state <= PRE_CLR;
end
PRE_CLR: begin
sel_internal <= 1'b1;
clr_internal <= 1'b1;
state <= CLR;
end
CLR:
begin
counter <= counter + 1;
sel_internal <= 1'b1;
clr_internal <= 1'b0;
pb1_r[3:0] <= i_dat;
state <= DATA;
end
DATA:
begin
counter <= counter + 1; //should be start clocking at 3
//following data samples are get in DATA phase.
if(counter[0]) begin
sel_internal <= ~sel_internal;
scan_number <= scan_number + 1;
end
if(sample_data) begin//read button state
case(scan_number)
//0: pb1_r[3:0] <= i_dat;
1: pb1_r[7:4] <= i_dat;
2: pb2_r[3:0] <= i_dat;
3: pb2_r[7:4] <= i_dat;
4: pb3_r[3:0] <= i_dat;
5: pb3_r[7:4] <= i_dat;
6: pb4_r[3:0] <= i_dat;
7: pb4_r[7:4] <= i_dat;
8: pb5_r[3:0] <= i_dat;
9: pb5_r[7:4] <= i_dat;
default:
begin
pb1_r <= pb1_r;
pb2_r <= pb2_r;
pb3_r <= pb3_r;
pb4_r <= pb4_r;
pb5_r <= pb5_r;
end
endcase
end
//the gamepads buton state are fetched at the end of DATA phase 1101 0101
if(scan_number == 9) begin
state <= IDLE;
busy <= 1'b0;
end
end
endcase
end
end
end
assign o_clr = (game_controller_type_r == 4'h6) ? clr_internal : 1'b0;
assign o_sel = (game_controller_type_r == 4'h6) ? sel_internal : 1'b0;
endmodule |
module clock_divider_fract (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_step,
output reg o_stb
);
reg [31:0] counter=33'd0;
always @(posedge i_clk) begin
if(i_rst) //synchronous reset
counter <= 32'd0;
else
{o_stb,counter} <= counter + i_step;
end
endmodule |
module serlatch_game_controller #(parameter MASTER_CLK_FREQ=53_600_000)
(
input wire i_clk,
input wire i_rst,
input wire [3:0] game_controller_type, //0x0 DISABLED, 0x1 DB15, 0x2 NES, 0x3 SNES, 0x9 DB15 Fast, 0xB SNES SWAP A,B<->X,Y
input wire i_stb,
output reg [15:0] p1_btn_state,
output reg [15:0] p2_btn_state,
output reg busy,
//SNAC Game controller interface
output wire o_clk, //for controller 1
output wire o_clk2, //for controller 2
output wire o_lat, //shared for 2 controllers
input wire i_dat1, //data from controller 1
input wire i_dat2 //data from controller 2
);
//FSM states
parameter IDLE = 3'b001;
parameter LATCH = 3'b010;
parameter DATA = 3'b100;
//store module settings
reg [3:0] game_controller_type_r;
reg [2:0] state = IDLE;
reg [5:0] counter;
//reg [4:0] btn_cnt;
reg [5:0] counter_top_value;
reg latch_internal;
reg clk_internal;
reg [23:0] bstat_r;
reg [15:0] p1b_r;
reg [15:0] p2b_r;
wire latch_level /* synthesis keep */;
wire disable_clock_on_latch /* synthesis keep */;
wire sample_data /* synthesis keep */;
//always sample data at falling edge of o_clk starting and second clock pulse in latch phase.
assign sample_data = ~counter[0] && i_stb && (counter > 1) && (counter <= counter_top_value);
always @(posedge i_clk) begin
//detect reset or any change on gamepad configuration and restart FSM at IDLE state.
if(i_rst || (game_controller_type != game_controller_type_r)) begin
state <= IDLE;
//clear internal register button state
p1b_r <= 16'hffff;
p2b_r <= 16'hffff;
bstat_r <= 24'hffffff;
end
game_controller_type_r <= game_controller_type;
if(i_stb) begin
case(state)
IDLE:
begin
//fetch data from last read
//set button status output
case(game_controller_type_r)
4'h0: begin //DISABLED
p1_btn_state = 16'd0;
p2_btn_state = 16'd0;
end
4'h1,4'h9: begin //DB15, DB15 FAST
// Pocket logic button order:
// [0] dpad_up
// [1] dpad_down
// [2] dpad_left
// [3] dpad_right
// [4] face_a
// [5] face_b
// [6] face_x
// [7] face_y
// [8] trig_l1
// [9] trig_r1
// [10] trig_l2
// [11] trig_r2
// [12] trig_l3
// [13] trig_r3
// [14] face_select
// [15] face_start
//SNAC DB15 adapter button order from first to last
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
//P1D,P1C,P1B,P1A,P1R,P1L,P1D,P1U,P2R,P2L,P2D,P2U,P1F,P1E,P1SEL,P1ST,P2F,P2E,P2SEL,P2ST,P2D,P2C,P2B,P2A
//follow Pocket game controls order:
//PLAYER1 START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP
p1_btn_state <= ~{bstat_r[15], bstat_r[14], 4'b1111, bstat_r[12], bstat_r[13], bstat_r[0], bstat_r[1], bstat_r[2], bstat_r[3], bstat_r[4], bstat_r[5], bstat_r[6], bstat_r[7]};
//PLAYER2 START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGH LEFT DOWN UP
p2_btn_state <= ~{bstat_r[19], bstat_r[18], 4'b1111, bstat_r[16], bstat_r[17], bstat_r[20], bstat_r[21], bstat_r[22], bstat_r[23], bstat_r[8], bstat_r[9], bstat_r[10], bstat_r[11]};
end
4'h2: begin //NES
//SNAC NES adapter button order from first to last
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
// A B SEL ST UP DW LF RG H H H H H H H H
//follow Pocket game controls order:
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP
p1_btn_state <= ~{p1b_r[3],p1b_r[2], 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, p1b_r[1], p1b_r[0],p1b_r[7],p1b_r[6],p1b_r[5],p1b_r[4]};
p2_btn_state <= ~{p2b_r[3],p2b_r[2], 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, p2b_r[1], p2b_r[0],p2b_r[7],p2b_r[6],p2b_r[5],p2b_r[4]};
end
4'h3: begin //SNES
//SNAC SNES adapter button order from first to last
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
// B Y SEL ST UP DW LF RG A X LT LR H H H H
//follow Pocket game controls order:
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP
p1_btn_state <= ~{p1b_r[3],p1b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p1b_r[11], p1b_r[10], p1b_r[1], p1b_r[9], p1b_r[0], p1b_r[8],p1b_r[7],p1b_r[6], p1b_r[5],p1b_r[4]};
p2_btn_state <= ~{p2b_r[3],p2b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p2b_r[11], p2b_r[10], p2b_r[1], p2b_r[9], p2b_r[0], p2b_r[8],p2b_r[7],p2b_r[6], p2b_r[5],p2b_r[4]};
end
4'hB: begin //SNES SWAP A,B <-> X,Y
//SNAC SNES adapter button order from first to last
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
// B Y SEL ST UP DW LF RG A X LT LR H H H H
//follow Pocket game controls order:
// START SELECT R3 L3 R2 L2 R1 L1 Y X B A RIGHT LEFT DOWN UP
p1_btn_state <= ~{p1b_r[3],p1b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p1b_r[11], p1b_r[10], p1b_r[0], p1b_r[8], p1b_r[1], p1b_r[9],p1b_r[7],p1b_r[6], p1b_r[5],p1b_r[4]};
p2_btn_state <= ~{p2b_r[3],p2b_r[2],1'b1, 1'b1, 1'b1, 1'b1, p2b_r[11], p2b_r[10], p2b_r[0], p2b_r[8], p2b_r[1], p2b_r[9],p2b_r[7],p2b_r[6], p2b_r[5],p2b_r[4]};
end
default:
begin //disabled
p1_btn_state <= 16'd0;
p2_btn_state <= 16'd0;
end
endcase
//init counter and set initial LAT,CLK values on IDLE state
counter <= 6'd0;
counter_top_value <= 6'd0;
if ((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) counter_top_value <= 6'd48;
else if((game_controller_type_r == 4'h2) || (game_controller_type_r == 4'h3) || (game_controller_type_r == 4'hB)) counter_top_value <= 6'd34;
latch_internal <= latch_level;
clk_internal <= disable_clock_on_latch ? 1'b0 : 1'b1;
state <= LATCH;
busy <= 1'b1;
p1b_r <= 16'hffff;
p2b_r <= 16'hffff;
bstat_r <= 24'hffffff;
end
LATCH:
begin
counter <= counter + 6'd1;
latch_internal <= ~latch_level;
clk_internal <= disable_clock_on_latch ? 1'b0 : ~clk_internal;
//first sample of data is available in LATCH phase.
if(sample_data) begin//read button state
if((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) begin //if is selected DB15,DB15 FAST all button state is store in one 24bit register
bstat_r[0] <= i_dat1; //3->0, 5->1, 7->2, 9->3, ...
// $display("DB15 [LATCH] BTN_CNT:%d i_dat1:%d", btn_cnt, i_dat1);
end
else begin
p1b_r[0] <= i_dat1;
p2b_r[0] <= i_dat2;
end
end
if(counter == 6'd2) begin
state <= DATA;
latch_internal <= latch_level;
end
end
DATA:
begin
counter <= counter + 6'd1; //should be start clocking at 3
clk_internal <= ~clk_internal;
//following data samples are get in DATA phase.
if(sample_data) begin//read button state
if((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9) ) begin //if is selected DB15,DB15 FAST all button state is store in one 24bit register
bstat_r[((counter>>1)-1)] <= i_dat1; //3->0, 5->1, 7->2, 9->3, ...
//$display("DB15 [DATA] BTN_CNT:%d i_dat1:%d r_dat[%d]:%d", btn_cnt, i_dat1, btn_cnt,bstat_r[btn_cnt]);
end
else if((game_controller_type_r == 4'h2) || (game_controller_type_r == 4'h3) || (game_controller_type_r == 4'hB)) begin
p1b_r[((counter>>1)-1)] <= i_dat1;
p2b_r[((counter>>1)-1)] <= i_dat2;
end
end
//the gamepads buton state are fetched at the end of DATA phase
if(counter == counter_top_value) begin
state <= IDLE;
busy <= 1'b0;
end
end
endcase
end
end
//the DB15 SNAC interface uses active LOW latch signal, NES,SNES use active HIGH latch:
// ----- ------ ...
//DB15 LATCH |___|
//
// ___
//NES,SNES LATCH _____| |_____ ...
assign latch_level = ((game_controller_type_r == 4'h1) || (game_controller_type_r == 4'h9)) ? 1'b1 : 1'b0; //DB15, DB15 FAST
//the NES,SNES SNAC interfaces disable clock signal while are in LATCH phase
//but internally the falling edge CLK is used for sample the button state
// ___
//LATCH ______| |_________ ...
// _ _ _
//o_clk | |_________| |_| |_ ...
// _ _ _ _ _
//CLK | |_|X|_|X|_| |_| |_ ...
// ... 1 2 3 4 5 6 7 8 ...
assign disable_clock_on_latch = ((game_controller_type_r != 4'h1) && (game_controller_type_r != 4'h9)) ? 1'b1 : 1'b0; //en caso de que sea controlador NES,SNES
//counter values: 36 for NES,SNES, 50 for DB15
assign o_clk = (game_controller_type_r == 4'h0) ? 1'b0 : clk_internal;
assign o_clk2 = (game_controller_type_r == 4'h0) ? 1'b0 : clk_internal;
assign o_lat = (game_controller_type_r == 4'h0) ? 1'b0 : latch_internal;
endmodule |
module oc8051_ram (clk, rst, rd_addr, rd_data, wr_addr, wr_data, wr);
// clk clock
// rd_addr read addres
// rd_data read data
// wr_addr write addres
// wr_data write data
// wr write
input clk, wr, rst;
input [7:0] rd_addr, wr_addr, wr_data;
output [7:0] rd_data;
wire [7:0] dob;
RAMB4_S8_S8 ram1(.DOA(rd_data), .DOB(dob), .ADDRA({1'b0, rd_addr}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({1'b0, wr_addr}), .DIB(wr_data), .ENB(1'b1), .CLKB(clk), .WEB(wr), .RSTB(rst));
endmodule |
module RAMB4_S8_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [7:0] DOA;
output [7:0] DOB;
input [8:0] ADDRA;
input [7:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [8:0] ADDRB;
input [7:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule |
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7'b1110111;
4'h1: out[13:7] = 7'b0100100;
4'h2: out[13:7] = 7'b1011101;
4'h3: out[13:7] = 7'b1101101;
4'h4: out[13:7] = 7'b0101110;
4'h5: out[13:7] = 7'b1101011;
4'h6: out[13:7] = 7'b1111011;
4'h7: out[13:7] = 7'b0100111;
4'h8: out[13:7] = 7'b1111111;
4'h9: out[13:7] = 7'b1101111;
4'ha: out[13:7] = 7'b0111111;
4'hb: out[13:7] = 7'b1111010;
4'hc: out[13:7] = 7'b1010011;
4'hd: out[13:7] = 7'b1111100;
4'he: out[13:7] = 7'b1011011;
4'hf: out[13:7] = 7'b0011011;
default: out[13:7] = 7'b0000000;
endcase
case (in[3:0])
4'h0: out[6:0] = 7'b1110111;
4'h1: out[6:0] = 7'b0100100;
4'h2: out[6:0] = 7'b1011101;
4'h3: out[6:0] = 7'b1101101;
4'h4: out[6:0] = 7'b0101110;
4'h5: out[6:0] = 7'b1101011;
4'h6: out[6:0] = 7'b1111011;
4'h7: out[6:0] = 7'b0100111;
4'h8: out[6:0] = 7'b1111111;
4'h9: out[6:0] = 7'b1101111;
4'ha: out[6:0] = 7'b0111111;
4'hb: out[6:0] = 7'b1111010;
4'hc: out[6:0] = 7'b1010011;
4'hd: out[6:0] = 7'b1111100;
4'he: out[6:0] = 7'b1011011;
4'hf: out[6:0] = 7'b0011011;
default: out[6:0] = 7'b0000000;
endcase
end
endmodule |
module oc8051_fpga_top (clk, rst,
//
// interrupt interface
//
int1, int2,
//
// 2x7 led display output (port 0)
//
dispout,
//
// ports
//
p0_out, p1_out, p2_out, p3_out,
//
// external instruction rom interface
//
ea, iadr_o, istb_o, iack_i, icyc_o, idat_i,
//
// external data ram interface
//
stb_o, cyc_o, dat_i, dat_o, adr_o, ack_i, we_o,
//
// serial interface
//
rxd, txd,
//
// timer/counter interface
//
t0, t1);
input clk, rst, int1, int2, ea, iack_i, ack_i, rxd, t0, t1;
input [7:0] dat_i;
input [31:0] idat_i;
output txd, istb_o, icyc_o, stb_o, cyc_o, we_o;
output [13:0] dispout;
output [7:0] p0_out, p1_out, p2_out, p3_out, dat_o;
output [15:0] adr_o, iadr_o;
wire cstb_o, ccyc_o, cack_i;
wire [15:0] cadr_o;
wire [31:0] cdat_i;
wire nrst;
assign nrst = ~rst;
oc8051_top oc8051_top_1(.rst(nrst), .clk(clk),
//
// interrupt interface
//
.int0(int1), .int1(int2),
//
// external rom interface
//
.ea(ea), .iadr_o(cadr_o), .idat_i(cdat_i), .istb_o(cstb_o), .iack_i(cack_i), .icyc_o(ccyc_o),
//
// external ram interface
//
.dat_i(dat_i), .dat_o(dat_o), .adr_o(adr_o), .we_o(we_o), .ack_i(ack_i), .stb_o(stb_o),
.cyc_o(cyc_o),
//
// ports interface
//
.p0_in(8'hb0), .p1_in(8'hb1), .p2_in(8'hb2), .p3_in(8'hb3),
.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
//
// serial interface
//
.rxd(rxd), .txd(txd),
//
// timer/counter interface
//
.t0(t0), .t1(t1));
oc8051_icache oc8051_icache1(.rst(rst), .clk(clk),
// oc8051
.adr_i(cadr_o), .dat_o(cdat_i), .stb_i(cstb_o), .ack_o(cack_i),
.cyc_i(ccyc_o),
// external rom
.dat_i(idat_i), .stb_o(istb_o), .adr_o(iadr_o), .ack_i(iack_i),
.cyc_o(icyc_o));
defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
defparam oc8051_icache1.LINE_WIDTH = 3; // line address width (2 => 4x32)
defparam oc8051_icache1.BL_NUM = 7; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
disp disp1(.in(p0_out), .out(dispout));
endmodule |
module oc8051_cache_ram (clk, rst, addr0, data0, addr1, data1_i, data1_o, wr1);
//
// this module is part of oc8051_icache
// it's tehnology dependent
//
// clk (in) clock
// addr0 (in) addres port 0
// data0 (out) data output port 0
// addr1 (in) address port 1
// data1_i (in) data input port 1
// data1_o (out) data output port 1
// wr1 (in) write port 1
//
parameter ADR_WIDTH = 7; // cache address wihth
parameter CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
input clk, wr1, rst;
input [ADR_WIDTH-1:0] addr0, addr1;
input [31:0] data1_i;
output [31:0] data0, data1_o;
//
wire [7:0] dob;
RAMB4_S8_S8 ram1(.DOA(data0), .DOB(data1_o), .ADDRA({1'b0, addr0}), .DIA(8'h00), .ENA(1'b1), .CLKA(clk), .WEA(1'b0),
.RSTA(rst), .ADDRB({1'b0, addr1}), .DIB(data1_i), .ENB(1'b1), .CLKB(clk), .WEB(wr1), .RSTB(rst));
endmodule |
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