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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule |
module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O6 = I0 ? s1[1] : s1[0];
wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule |
module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule |
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule |
module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
parameter CYINIT_FABRIC = 0;
wire CI_COMBINE;
if(CYINIT_FABRIC) begin
assign CI_COMBINE = CI_INIT;
end else begin
assign CI_COMBINE = CI;
end
assign CO_CHAIN = S ? CI_COMBINE : DI;
assign CO_FABRIC = S ? CI_COMBINE : DI;
assign O = S ^ CI_COMBINE;
endmodule |
module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
assign CO_CHAIN = S ? CI : DI;
assign CO_FABRIC = S ? CI : DI;
assign O = S ^ CI;
endmodule |
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule |
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule |
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule |
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate
endmodule |
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule |
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule |
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule |
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule |
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [63:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule |
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
reg [127:0] mem = INIT;
assign SPO = mem[A];
assign DPO = mem[DPRA];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
endmodule |
module SRL16E (
output Q,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [15:0] r = INIT;
assign Q = r[{A3,A2,A1,A0}];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
endmodule |
module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [31:0] r = INIT;
assign Q31 = r[31];
assign Q = r[A];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[30:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[30:0], D };
endgenerate
endmodule |
module AL_MAP_SEQ (
output q,
input ce,
input clk,
input sr,
input d
);
parameter DFFMODE = "FF"; //FF,LATCH
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
endmodule |
module AL_MAP_LUT2 (
output o,
input a,
input b
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
assign o = INIT >> {b, a};
endmodule |
module AL_MAP_LUT3 (
output o,
input a,
input b,
input c
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
assign o = INIT >> {c, b, a};
endmodule |
module AL_MAP_LUT4 (
output o,
input a,
input b,
input c,
input d
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
assign o = INIT >> {d, c, b, a};
endmodule |
module AL_MAP_ADDER (
input a,
input b,
input c,
output [1:0] o
);
parameter ALUTYPE = "ADD";
endmodule |
module \$_DFF_N_ (input D, C, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule |
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire R_i = ~ R;
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule |
module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
endmodule |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin
fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end*/ else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule // |
module twentynm_io_ibuf (output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // twentynm_io_ibuf |
module twentynm_io_obuf (output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // twentynm_io_obuf |
module twentynm_lcell_comb (output combout, cout, sumout,
input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
parameter dont_touch = "off";
parameter lpm_type = "twentynm_lcell_comb";
parameter shared_arith = "off";
parameter extended_lut = "off";
// TODO: This is still WIP
initial begin
$display("Simulation model is still under investigation\n");
end
endmodule // twentynm_lcell_comb |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
wire VCC;
wire GND;
assign {VCC,GND} = {1'b1,1'b0};
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end
else
if (WIDTH == 2) begin
cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(VCC),
.datad(VCC),
.datae(VCC),
.dataf(VCC),
.datag(VCC));
end
else
if(WIDTH == 3) begin
cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(VCC),
.datae(VCC),
.dataf(VCC),
.datag(VCC));
end
else
if(WIDTH == 4) begin
cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(VCC),
.dataf(VCC),
.datag(VCC));
end
else
if(WIDTH == 5) begin
cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
.dataf(VCC),
.datag(VCC));
end
else
if(WIDTH == 6) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_
(.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]),
.datae(A[4]),
.dataf(A[5]),
.datag(VCC));
end
/*else
if(WIDTH == 7) begin
TODO: There's not a just 7-input function on Cyclone V, see the following note:
**Extended LUT Mode**
Use extended LUT mode to implement a specific set of 7-input functions. The set must
be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
[source](Device Interfaces and Integration Basics for Cyclone V Devices).
end*/
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule // lut |
module cyclonev_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // cyclonev_io_ibuf |
module cyclonev_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // cyclonev_io_obuf |
module displayNumber(in,out10,out1);
//input number
input [7:0]in;
//out10 mean 10's, out1 mean 1's
output [6:0]out10;
output [6:0]out1;
reg [6:0]out10;
reg [6:0]out1;
always@(in)
begin
case(in%100-in%10)
8'd0: out10=7'b1000000;
8'd1: out10=7'b1111001;
8'd2: out10=7'b0100100;
8'd3: out10=7'b0110000;
8'd4: out10=7'b0011001;
8'd5: out10=7'b0010010;
8'd6: out10=7'b0000010;
8'd7: out10=7'b1011000;
8'd8: out10=7'b0000000;
8'd9: out10=7'b0010000;
endcase
case(in%10)
8'd0: out1=7'b1000000;
8'd1: out1=7'b1111001;
8'd2: out1=7'b0100100;
8'd3: out1=7'b0110000;
8'd4: out1=7'b0011001;
8'd5: out1=7'b0010010;
8'd6: out1=7'b0000010;
8'd7: out1=7'b1011000;
8'd8: out1=7'b0000000;
8'd9: out1=7'b0010000;
endcase
end
endmodule |
module window(reset,out1,out10,light,switch,finish);
input reset;
input [7:0] switch;
//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [7:0]light;
output finish;
wire [6:0]out1;
wire [6:0]out10;
//
//logic counter neeed to declear as reg
reg [7:0]tries;
reg [7:0]light;
reg [3:0] i;
reg finish;
//
displayNumber DISNUM (.in(tries),.out10(out10),.out1(out1));
always@(reset)
begin
if(reset)
begin
tries<=8'd0;
finish<=1'b0;
i=($random)%8;
light=8'b00000000;
light[i]=1'b1;
end
end
always@(switch)
begin
for(i=4'd0;i<4'd8;i++)
begin
if(switch[i]==1'b1)
begin
if(i>=1) light[i-4'd1]=~light[i-1];
if(i<=6) light[i+1]=~light[i+1];
light[i]=~light[i];
tries<=tries+1'd1;
end
end
if(light==8'b00000000) finish=1'b1;
end
endmodule |
module vga (
output [7:0] light,
input clk, // 50 MHz
input down,
input right,
input check,
output [2:0] red,
output [2:0] green,
output [2:0] blue,
output hsync,vsync,
output [6:0] out10,
output [6:0] out1
);
reg [11:0] hcount; // VGA horizontal counter
reg [10:0] vcount; // VGA vertical counter
integer i,j;
integer pixelSize=30;
integer size=50;
reg [7:0] tries;
reg [3:0] map [0:3];
reg [2:0] selectX=2'd0;
reg [2:0] selectY=2'd0;
wire hcount_ov, vcount_ov, video_active;
displayNumber DISNUM (.in(tries),.out10(out10),.out1(out1));
// VGA mode parameters
parameter
hsync_end = 12'd119,
hdat_begin = 12'd242,
hdat_end = 12'd1266,
hpixel_end = 12'd1345,
vsync_end = 11'd5,
vdat_begin = 11'd32,
vdat_end = 11'd632,
vline_end = 11'd665;
always @(posedge clk)
begin
if (hcount_ov) hcount <= 12'd0;
else hcount <= hcount + 12'd1;
end
assign hcount_ov = hcount == hpixel_end;
always @(posedge clk)
begin
if (hcount_ov)
begin
if (vcount_ov) vcount <= 11'd0;
else vcount <= vcount + 11'd1;
end
end
assign vcount_ov = vcount == vline_end;
assign video_active = hdat_begin <= hcount && hcount < hdat_end &&
vdat_begin <= vcount && vcount < vdat_end;
assign hsync = hcount > hsync_end;
assign vsync = vcount > vsync_end;
reg [3:0] VGAr=7,VGAg=7,VGAb=7;
assign red= video_active ? VGAr : 3'b0;
assign blue= video_active ? VGAb :3'b0;
assign green= video_active ? VGAg : 3'b0;
assign light= (map[0]==4'b1111&&map[1]==4'b1111&&map[2]==4'b1111&&map[3]==4'b1111) ? 8'b11111111 : 8'b00000000;
//fowarding down
always @(posedge down)
begin
if(down==1)
begin
if(selectY>2) selectY<=0;
else selectY<=selectY+1;
end
end
//forward right
always @ (posedge right)
begin
if(right==1)
begin
if(selectX>2) selectX<=0;
else selectX<=selectX+1;
end
end
//press the light
always @ (posedge check)
begin
if(check==1)
begin
if(selectX>=1) map[selectX-1][selectY]=~map[selectX-1][selectY];
if(selectX<=2) map[selectX+1][selectY]=~map[selectX+1][selectY];
if(selectY>=1) map[selectX][selectY-1]=~map[selectX][selectY-1];
if(selectY<=2) map[selectX][selectY+1]=~map[selectX][selectY+1];
map[selectX][selectY]=~map[selectX][selectY];
tries<=tries+1;
end
end
//generate game screen
always @(posedge clk)
begin
//setup background
if(hcount>=hdat_begin&&hcount<=hdat_end&&vcount>=vdat_begin&&vcount<=vdat_end)
begin
VGAr<=0;
VGAb<=0;
VGAg<=0;
end
//setup map
for(i=0;i<=3;i=i+1)
begin
for(j=0;j<=3;j=j+1)
begin
if(hcount>i*size+hdat_begin && hcount<i*size+pixelSize+hdat_begin)
begin
if(vcount>j*size+vdat_begin && vcount<j*size+pixelSize+vdat_begin)
begin
if(map[i][j]==1'b1)
begin
VGAr<=7;
VGAb<=7;
VGAg<=7;
end
else
begin
VGAr<=3;
VGAb<=3;
VGAg<=3;
end
end
end
end
//setup player position
if(hcount>selectX*size+hdat_begin && hcount<selectX*size+pixelSize+hdat_begin)
begin
if(vcount>selectY*size+vdat_begin && vcount<selectY*size+pixelSize+vdat_begin)
begin
if(map[selectX][selectY]==1)
begin
VGAr<=3;
VGAb<=5;
VGAg<=7;
end
else
begin
VGAr<=7;
VGAb<=5;
VGAg<=3;
end
end
end
end
end
endmodule |
module displayLight(safe,light);
input safe;
//display current LED light
output [2:0] light;
reg [2:0] light;
always@(safe)
begin
//display one
if(safe) light=3'b100;
//display another one
else light=3'b001;
end
endmodule |
module countdown(reset,clk,out1,out10,light);
input reset,clk;
//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [2:0]light;
wire [6:0]out1;
wire [6:0]out10;
wire [2:0]light;
//
//logic counter neeed to declear as reg
reg [31:0]count;
reg [7:0]second;
reg safe;
//
displayNumber DISNUM (.in(second),.out10(out10),.out1(out1));
displayLight DISLIT (.safe(safe),.light(light));
always@(posedge clk,negedge reset)
begin
if(reset)
begin
count<=32'd0;
second<=`countdownTime;
safe<=1'b1;
end
else
begin
if(count==`TimeExpire)
begin
count<=32'd0;
if(second==5'd0)
begin
second=5'd7;
safe=1'b0;
end
else second=second-1'b1;
end
else count<=count+32'd1;
end
end
endmodule |
module vga(clk ,p1_pos,p2_pos,p1_size,p2_size,ball_posx,ball_posy ,VGA_r,VGA_g,VGA_b,hs,vs);
input clk;
input [9:0]p1_pos,p2_pos;
input [7:0]p1_size,p2_size;
input [10:0]ball_posx;//640
input [9:0]ball_posy;//480
output [3:0]VGA_r,VGA_g,VGA_b;
output hs,vs;
reg [19:0]vt;
reg [10:0]ht;
///////
reg [11:0] hc,hcount,r,g,b; // VGA horizontal counter
reg [10:0] vc,vcount; // VGA vertical counter
wire hcount_ov,vcount_ov,video_active;
// VGA mode parameters
parameter
hsync_end = 12'd119,
hdat_begin = 12'd242,
hdat_end = 12'd1266,
hpixel_end = 12'd1345,
vsync_end = 11'd5,
vdat_begin = 11'd32,
vdat_end = 11'd632,
vline_end = 11'd665;
always@(posedge clk) hcount<=(hcount_ov)? 12'd0:(hcount+12'd1);
always@(posedge clk) vcount<=(hcount_ov)? (vcount_ov)? 11'd0:(vcount+11'd1):vcount;
assign hcount_ov=hcount == hpixel_end;
assign vcount_ov=vcount == vline_end;
assign video_active=hdat_begin<=hcount&&hcount<hdat_end&&
vdat_begin<=vcount&&vcount<vdat_end;
assign hs=hcount>hsync_end;
assign vs=vcount>vsync_end;
assign VGA_r=(video_active)? r[3:0]:0;
assign VGA_g=(video_active)? g[3:0]:0;
assign VGA_b=(video_active)? b[3:0]:0;
// generate "image",p.s.:you can only use clk there,or it will too late to
// show image
always@(posedge clk)
begin
vc<=vcount-vdat_begin;
hc<=hcount-hdat_begin;
//show ball
if( (hc>=ball_posx)&&(hc<(ball_posx+`Ball_size))&&
(vc>=ball_posy)&&(vc<(ball_posy+`Ball_size)))
begin
r<=12;
g<=6;
b<=0;
end
else
begin
r<=15;
g<=15;
b<=15;
end
//show player1
if( hc>10'd30&&hc<=10'd62&&
vc>=p1_pos&&vc<(p1_pos+p1_size))
begin
r<=r-((hc-30)>>1);
g<=g-((hc-30)>>1);
end
else
begin
//show player2
if( hc>10'd962&&hc<=10'd994&&
vc>=p2_pos&&vc<(p2_pos+p2_size))
begin
g<=g-((962-hc)>>1);
b<=b-((962-hc)>>1);
end
end
end
endmodule |
module ball_pos(b_clk,b_rst,ball_posx,ball_posy,p1_pos,p2_pos,p1_size,p2_size);
input b_clk,b_rst;
input [9:0]p1_pos,p2_pos;
input [7:0]p1_size,p2_size;
output [10:0]ball_posx;
output [9:0]ball_posy;
reg [10:0]ball_posx;
reg [9:0]ball_posy;
reg [1:0]direction;//0:x,1:y//0:+,1:-
always@(posedge b_clk,negedge b_rst)
begin
if(!b_rst)
begin
ball_posx<=11'd305;
ball_posy<=10'd100;
direction<=2'd0;
end
else
begin
//bounce
if(ball_posy<=3)
direction[1]<=0;
if((ball_posy+`Ball_size)>=600)
direction[1]<=1;
if(ball_posx==62&&(ball_posy+`Ball_size)>=p1_pos&&ball_posy<(p1_pos+p1_size))
direction[0]<=0;
if((ball_posx+`Ball_size)==962&&(ball_posy+`Ball_size)>=p2_pos&&ball_posy<(p2_pos+p2_size))//player 2 defend
direction[0]<=1;
//ball move
ball_posx<=ball_posx+((direction[0])? -1:1);
ball_posy<=ball_posy+((direction[1])? -1:1);
end
end
endmodule |
module player_move(rst,clk,in,size,pos);
input rst,clk;
input [1:0]in;
input [7:0]size;
output [9:0]pos;
reg [9:0]pos;
reg [31:0]count;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
pos<=10'd210;
count<=32'd0;
end
else
begin
if(count==`Buttun_time)
begin
count<=32'd0;
case(in)
2'b01:pos<=pos+((pos+size)<=600);
2'b10:pos<=pos-(pos!=0);
default:pos<=pos;
endcase
end
else count<=count+32'd1;
end
end
endmodule |
module game_rule_setter(rst,clk,p1_point,p2_point,rule ,p1_size,p2_size,b_clk);
input rst,clk;
input [3:0]p1_point,p2_point;
input [2:0]rule;//0:size,1:speed
output [7:0]p1_size,p2_size;
output b_clk;
reg [7:0]p1_size,p2_size;
reg b_clk;
reg [31:0]count,clock,shrink;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
clock<=32'd100000;
count<=32'd0;
p1_size<=8'd200;
p2_size<=8'd200;
end
else
begin
if(count==clock)
begin
count<=32'd0;
//let ball move faster
clock<=clock-(32'd4)*rule[1];
b_clk<=1'b1;
//let player smaller
//(it may have bug when ball faster,player shrink faster,need fix)
shrink<=shrink+1;
if(!(shrink%40))
begin
p1_size<=p1_size-rule[0]*(p1_size>60);
p2_size<=p2_size-rule[0]*(p2_size>60);
end
end
else
begin
count<=count+32'd1;
b_clk=1'b0;
end
//end game,player disappear
if((rule[2]&&((p1_point+p2_point)>=5))||((p1_point+p2_point)>=3))
begin
if(p1_point>p2_point)
p2_size<=0;
else
p1_size<=0;
end
end
end
endmodule |
module seven_segment(clk,rst,point,out);
input clk,rst;
input [3:0]point;
output [6:0]out;
reg [6:0]out;
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
out=7'b0111111;
end
else
begin
case(point)
4'h0:out=7'b1000000;
4'h1:out=7'b1111001;
4'h2:out=7'b0100100;
4'h3:out=7'b0110000;
4'h4:out=7'b0011001;
4'h5:out=7'b0010010;
4'h6:out=7'b0000010;
4'h7:out=7'b1011000;
4'h8:out=7'b0000000;
4'h9:out=7'b0010000;
4'ha:out=7'b0001000;
4'hb:out=7'b0000011;
4'hc:out=7'b1000110;
4'hd:out=7'b0100001;
4'he:out=7'b0000110;
4'hf:out=7'b0001110;
endcase
end
end
endmodule |
module referee(rst,clk ,ball_posx ,b_rst,seven_1,seven_2,seven_3,p1_point,p2_point);
input rst,clk;
input [10:0]ball_posx;
output b_rst;
output [6:0]seven_1,seven_2,seven_3;//seven segment
output [3:0]p1_point,p2_point;
reg b_rst;
reg [3:0]p1_point,p2_point;
seven_segment scorer_1 (.clk(clk),.rst(rst),.point(p1_point),.out(seven_1));//"p1"
seven_segment scorer_2 (.clk(clk),.rst(1'd0),.point(4'd0),.out(seven_2));//"-"
seven_segment scorer_3 (.clk(clk),.rst(rst),.point(p2_point),.out(seven_3));//"p2"
always@(posedge clk,negedge rst)
begin
if(!rst)
begin
b_rst=1'd0;
p1_point=4'd0;
p2_point=4'd0;
end
else
begin
//player 2 got point
if(ball_posx==0)
begin
b_rst=1'd0;
p2_point=p2_point+1;
end
else
begin
//player 1 got point
if(ball_posx+`Ball_size==1024)
begin
b_rst=1'd0;
p1_point=p1_point+1;
end
else
b_rst=1'd1;
end
end
end
endmodule |
module pingpong(rst,clk ,rule,p1,p2,r,g,b,hs,vs,seven_1,seven_2,seven_3);
input rst,clk;
input [2:0]rule;
input [1:0]p1,p2;
output [3:0]r,g,b;
output hs,vs;
output [6:0]seven_1,seven_2,seven_3;//seven segment,//"p1" "-" "p2"
wire [7:0]p1_size,p2_size;
wire [3:0]p1_point,p2_point;
wire [9:0]p1_pos,p2_pos;
wire b_clk;
wire [10:0]ball_posx;
wire [9:0]ball_posy;
game_rule_setter rule_holder (.rst(b_rst),.clk(clk),.p1_point(p1_point),.p2_point(p2_point),.rule(rule),.p1_size(p1_size),.p2_size(p2_size),.b_clk(b_clk));
player_move player1 (.rst(rst),.clk(clk),.in(p1),.size(p1_size),.pos(p1_pos));
player_move player2 (.rst(rst),.clk(clk),.in(p2),.size(p2_size),.pos(p2_pos));
ball_pos ball (
.b_clk(b_clk),.b_rst(b_rst),.ball_posx(ball_posx),.ball_posy(ball_posy),
.p1_pos(p1_pos),.p2_pos(p2_pos),.p1_size(p1_size),.p2_size(p2_size));
vga DIS (
.clk(clk),
.p1_pos(p1_pos),.p2_pos(p2_pos),.p1_size(p1_size),.p2_size(p2_size),.ball_posx(ball_posx),.ball_posy(ball_posy),
.VGA_r(r),.VGA_g(g),.VGA_b(b),.hs(hs),.vs(vs));
referee noob (.rst(rst),.clk(clk),.ball_posx(ball_posx),.b_rst(b_rst),.seven_1(seven_1),.seven_2(seven_2),.seven_3(seven_3),.p1_point(p1_point),.p2_point(p2_point));
endmodule |
module displayGraph(safe,row,column,count);
//decide is green/yellow time or not
input safe;
input [31:0] count;
//display matrix
output [7:0] row;
output [7:0] column;
reg [7:0]row;
reg [7:0]column;
always@(safe)
begin
if(safe)
begin
if(count%8==4'd0)
begin
row=8'b01111111;
column=8'b00011000;
end
if(count%8==4'd1)
begin
row=8'b10111111;
column=8'b00100100;
end
if(count%8==4'd2)
begin
row=8'b11011111;
column=8'b01000010;
end
if(count%8==4'd3)
begin
row=8'b11101111;
column=8'b11000011;
end
if(count%8==4'd4)
begin
row=8'b11110111;
column=8'b01000010;
end
if(count%8==4'd5)
begin
row=8'b11111011;
column=8'b01000010;
end
if(count%8==4'd6)
begin
row=8'b11111101;
column=8'b01000010;
end
if(count%8==4'd7)
begin
row=8'b11111110;
column=8'b01111110;
end
end
else
begin
if(count%8==4'd0)
begin
row=8'b01111111;
column=8'b00011000;
end
if(count%8==4'd1)
begin
row=8'b10111111;
column=8'b00011000;
end
if(count%8==4'd2)
begin
row=8'b11011111;
column=8'b00111100;
end
if(count%8==4'd3)
begin
row=8'b11101111;
column=8'b01111110;
end
if(count%8==4'd4)
begin
row=8'b11110111;
column=8'b01011010;
end
if(count%8==4'd5)
begin
row=8'b11111011;
column=8'b00011000;
end
if(count%8==4'd6)
begin
row=8'b11111101;
column=8'b00100100;
end
if(count%8==4'd7)
begin
row=8'b11111110;
column=8'b00100100;
end
end
end
endmodule |
module displayLight(in,safe,light);
input [4:0] in;
input safe;
//display current LED light
output [2:0] light;
reg [2:0] light;
always@(in&&safe)
begin
if(safe)
begin
//display green one
if(in>=5'd13&&in<=5'd3) light=3'b100;
//display yellow one
else light=3'b010;
end
//display red one
else light=3'b001;
end
endmodule |
module lab11(reset,clk,out1,out10,row,column,light);
input reset,clk;
//display need to declear as output and wire
output [6:0]out1;
output [6:0]out10;
output [7:0]row;
output [7:0]column;
output [2:0]light;
wire [6:0]out1;
wire [6:0]out10;
wire [7:0]row;
wire [7:0]column;
wire [2:0]light;
//
//logic counter neeed to declear as reg
reg [31:0]count;
reg [4:0]second;
reg safe;
//
displayNumber DISNUM (.in(second),.out10(out10),.out1(out1));
displayGraph DISGPH (.safe(safe),.row(row),.column(column),.count(count));
displayLight DISLIT (.in(second),.safe(safe),.light(light));
always@(posedge clk,negedge reset)
begin
if(reset)
begin
count<=32'd0;
second<=5'd13;
safe<=1'b1;
end
else
begin
if(count==`TimeExpire)
begin
count<=32'd0;
if(second==5'd0&&safe==1'b1)
begin
second=5'd7;
safe=1'b0;
end
else if(second==5'd0&&safe==1'b0)
begin
second=5'd13;
safe=1'b1;
end
else
begin
second=second-1'b1;
end
end
else count<=count+32'd1;
end
end
endmodule |
module traffic_light(clk,rst,out,dot_row,dot_col);
input clk,rst;
output reg [6:0] out;
output reg [7:0] dot_row,dot_col;
reg [31:0] clk_count;
reg [31:0] clk_count_2;
reg [1:0] cur_state,next_state;
reg [3:0] counter;
reg [2:0] row_count;
reg clk_div;
parameter [1:0] GREEN = 2'b00;
parameter [1:0] RED = 2'b01;
parameter [1:0] YELLOW = 2'b10;
always@(posedge clk ) begin
if (~rst) begin
clk_count <= 32'b0;
cur_state <= GREEN;
counter <= 4'b1;
clk_div <= 1'b0;
clk_count_2 <= 32'b0;
end
else begin
if (clk_count_2 == 5000 ) begin
clk_div <= ~clk_div;
clk_count_2 <= 32'b0;
end
else begin
clk_count_2 <= clk_count_2 + 32'b1;
end
if (clk_count == 50000000 ) begin
clk_count <= 32'b0;
cur_state <= next_state;
if ( next_state != cur_state)
counter <= 4'b1;
else
counter <= counter + 4'b1;
end
else
clk_count <= clk_count + 32'b1;
end
end
always@(*) begin
case (cur_state)
GREEN : begin
if ( counter == 15 ) // 15
next_state = YELLOW;
else
next_state = GREEN;
end
YELLOW : begin
if ( counter == 5 ) // 3
next_state = RED;
else
next_state = YELLOW;
end
default : begin
if ( counter == 10 ) // 8
next_state = GREEN;
else
next_state = RED;
end
endcase
end
always@ (posedge clk_div or negedge rst ) begin
if (~rst) begin
dot_row <= 8'b0;
dot_col <= 8'b0;
row_count <= 0;
end
else begin
row_count <= row_count + 1;
if ( cur_state == GREEN) begin
case (row_count)
3'd0: dot_row <= 8'b01111111;
3'd1: dot_row <= 8'b10111111;
3'd2: dot_row <= 8'b11011111;
3'd3: dot_row <= 8'b11101111;
3'd4: dot_row <= 8'b11110111;
3'd5: dot_row <= 8'b11111011;
3'd6: dot_row <= 8'b11111101;
3'd7: dot_row <= 8'b11111110;
endcase
case (row_count)
3'd0: dot_col <= 8'b00001100;
3'd1: dot_col <= 8'b00001100;
3'd2: dot_col <= 8'b00011001;
3'd3: dot_col <= 8'b01111110;
3'd4: dot_col <= 8'b10011000;
3'd5: dot_col <= 8'b00011000;
3'd6: dot_col <= 8'b00101000;
3'd7: dot_col <= 8'b01001000;
endcase
end
else if (cur_state == RED) begin
case (row_count)
3'd0: dot_row <= 8'b01111111;
3'd1: dot_row <= 8'b10111111;
3'd2: dot_row <= 8'b11011111;
3'd3: dot_row <= 8'b11101111;
3'd4: dot_row <= 8'b11110111;
3'd5: dot_row <= 8'b11111011;
3'd6: dot_row <= 8'b11111101;
3'd7: dot_row <= 8'b11111110;
endcase
case (row_count)
3'd0: dot_col <= 8'b00011000;
3'd1: dot_col <= 8'b00011000;
3'd2: dot_col <= 8'b00111100;
3'd3: dot_col <= 8'b00111100;
3'd4: dot_col <= 8'b01011010;
3'd5: dot_col <= 8'b00011000;
3'd6: dot_col <= 8'b00011000;
3'd7: dot_col <= 8'b00100100;
endcase
end
else if (cur_state == YELLOW) begin
case (row_count)
3'd0: dot_row <= 8'b01111111;
3'd1: dot_row <= 8'b10111111;
3'd2: dot_row <= 8'b11011111;
3'd3: dot_row <= 8'b11101111;
3'd4: dot_row <= 8'b11110111;
3'd5: dot_row <= 8'b11111011;
3'd6: dot_row <= 8'b11111101;
3'd7: dot_row <= 8'b11111110;
endcase
case (row_count)
3'd0: dot_col <= 8'b00000000;
3'd1: dot_col <= 8'b00100100;
3'd2: dot_col <= 8'b00111100;
3'd3: dot_col <= 8'b10111101;
3'd4: dot_col <= 8'b11111111;
3'd5: dot_col <= 8'b00111100;
3'd6: dot_col <= 8'b00111100;
3'd7: dot_col <= 8'b00000000;
endcase
end
end
end
always@(*) begin
case (counter)
0 : begin
out = 7'b0000001;
end
1 : begin
out = 7'b1001111;
end
2 : begin
out = 7'b0010010;
end
3 : begin
out = 7'b0000110;
end
4 : begin
out = 7'b1001100;
end
5 : begin
out = 7'b0100100;
end
6 : begin
out = 7'b0100000;
end
7 : begin
out = 7'b0001111;
end
8 : begin
out = 7'b0000000;
end
9 : begin
out = 7'b0000100;
end
10 : begin
out = 7'b0001000;
end
11 : begin
out = 7'b1100000;
end
12 : begin
out = 7'b0110001;
end
13 : begin
out = 7'b1000010;
end
14 : begin
out = 7'b0110000;
end
15 : begin
out = 7'b0111000;
end
endcase
end
endmodule |
module adder_substractor (a,b,select,out);
input [3:0]a;
input [3:0]b;
input select;
output [4:0]out;
reg [4:0]out;
always @(select or a or b)
begin
if (select)
begin
out = a+b;
end
else
begin
out = a-b;
end
end
endmodule |
module encoder (in,out,valid);
input [7:0]in;
output valid;
output [2:0]out;
reg [2:0]out;
reg valid;
always @ (in)
begin
case (in)
8'b00000001: begin
out = 3'b000;
valid = 1;
end
8'b00000010: begin
out = 3'b001;
valid = 1;
end
8'b00000100: begin
out = 3'b010;
valid = 1;
end
8'b00001000: begin
out = 3'b011;
valid = 1;
end
8'b00010000: begin
out = 3'b100;
valid = 1;
end
8'b00100000: begin
out = 3'b101;
valid = 1;
end
8'b01000000: begin
out = 3'b110;
valid = 1;
end
8'b10000000: begin
out = 3'b111;
valid = 1;
end
default: begin
out = 3'b000;
valid = 0;
end
endcase
end
endmodule |
module multiplexer (in,out);
input [3:0]in;
output [6:0]out;
reg [6:0]out;
always @(in)
begin
case (in)
4'd0: out = 7'b1000000;
4'd1: out = 7'b1111001;
4'd2: out = 7'b0100100;
4'd3: out = 7'b0010010;
4'd4: out = 7'b1111000;
4'd5: out = 7'b0010000;
4'd6: out = 7'b0100001;
4'd7: out = 7'b0001110;
endcase
end
endmodule |
module dot_matrix(clk,rst,btn_left,btn_right,move_left, move_right, dot_row,dot_col);
input clk,rst,btn_left,btn_right;
output reg [7:0] dot_row;
output reg [15:0] dot_col;
output move_left,move_right;
reg [31:0] cnt_div,cnt_dot;
reg [15:0] dot_col_buff[0:7];
reg [2:0] row_count;
wire clk_div,clk_dot;
btn_control left_btn_control(clk,rst,btn_left,move_left);
btn_control right_btn_control(clk,rst,btn_right,move_right);
clk_divi myclk (clk,rst,32'd6250000, clk_div);
clk_divi myclk2 (clk,rst,32'd5000, clk_dot);
always@ (posedge clk_dot or negedge rst)
begin
if (~rst)
begin
dot_row <= 8'd0;
dot_col <= 16'd0;
row_count <= 3'd0;
end
else
begin
row_count <= row_count + 1;
dot_col <= dot_col_buff[row_count];
case (row_count)
3'd0: dot_row <= 8'b01111111;
3'd1: dot_row <= 8'b10111111;
3'd2: dot_row <= 8'b11011111;
3'd3: dot_row <= 8'b11101111;
3'd4: dot_row <= 8'b11110111;
3'd5: dot_row <= 8'b11111011;
3'd6: dot_row <= 8'b11111101;
3'd7: dot_row <= 8'b11111110;
endcase
end
end
always@ (posedge clk_div or negedge rst)
begin
if (~rst)
begin
dot_col_buff[0] <= 16'b0001110000000000;
dot_col_buff[1] <= 16'b0001011000000000;
dot_col_buff[2] <= 16'b0001111000000000;
dot_col_buff[3] <= 16'b0011100000000000;
dot_col_buff[4] <= 16'b1111110000000000;
dot_col_buff[5] <= 16'b1111100000000000;
dot_col_buff[6] <= 16'b0111100000000000;
dot_col_buff[7] <= 16'b0010100000000000;
end
else
begin
if (move_left)
begin
dot_col_buff[0] <= {dot_col_buff[0][14:0],dot_col_buff[0][15]};
dot_col_buff[1] <= {dot_col_buff[1][14:0],dot_col_buff[1][15]};
dot_col_buff[2] <= {dot_col_buff[2][14:0],dot_col_buff[2][15]};
dot_col_buff[3] <= {dot_col_buff[3][14:0],dot_col_buff[3][15]};
dot_col_buff[4] <= {dot_col_buff[4][14:0],dot_col_buff[4][15]};
dot_col_buff[5] <= {dot_col_buff[5][14:0],dot_col_buff[5][15]};
dot_col_buff[6] <= {dot_col_buff[6][14:0],dot_col_buff[6][15]};
dot_col_buff[7] <= {dot_col_buff[7][14:0],dot_col_buff[7][15]};
end
else if (move_right)
begin
dot_col_buff[0] <= {dot_col_buff[0][0],dot_col_buff[0][15:1]};
dot_col_buff[1] <= {dot_col_buff[1][0],dot_col_buff[1][15:1]};
dot_col_buff[2] <= {dot_col_buff[2][0],dot_col_buff[2][15:1]};
dot_col_buff[3] <= {dot_col_buff[3][0],dot_col_buff[3][15:1]};
dot_col_buff[4] <= {dot_col_buff[4][0],dot_col_buff[4][15:1]};
dot_col_buff[5] <= {dot_col_buff[5][0],dot_col_buff[5][15:1]};
dot_col_buff[6] <= {dot_col_buff[6][0],dot_col_buff[6][15:1]};
dot_col_buff[7] <= {dot_col_buff[7][0],dot_col_buff[7][15:1]};
end
end
end
endmodule |
module btn_control(clk,rst,btn_signal,move);
input clk,rst,btn_signal;
output reg move;
reg [31:0] cnt;
always@(posedge clk or negedge rst)
begin
if (~rst)
begin
move <= 1'b0;
cnt <= 32'd0;
end
else
begin
if (cnt == 12500000)
begin
move <= 1'b0;
cnt <= 32'd0;
end
else if(cnt[7:0] == 8'd0)
begin
move <= (!btn_signal)? 1'b1 : move;
cnt <= cnt + 32'b1;
end
else
begin
cnt <= cnt + 32'b1;
end
end
end
endmodule |
module clk_divi (clk,rst,counter,div_clk);
input clk,rst;
input [31:0]counter;
output div_clk;
reg div_clk;
reg [31:0]count;
always @ (posedge clk)
begin
if (!rst)
begin
count <= 32'd0;
div_clk <=1'b0;
end
else
begin
if (count == counter)
begin
count<=32'd0;
div_clk <=~div_clk;
end
else
begin
count <= count + 32'd1;
end
end
end
endmodule |
module full_adder (cin, a,b, sum, cout);
input cin,a,b;
output sum,cout;
wire temp,store,result;
xor (temp,a,b);
xor (sum,temp,cin);
and (result,a,b);
and (store,temp,cin);
or (cout,result, store);
endmodule |
module lab11(clk,rst,keypad_row,keypad_col,dot_row,dot_col,seven_seg);
input clk,rst;
output [3:0] keypad_row;
input [3:0] keypad_col;
output reg [7:0] dot_row,dot_col;
output reg [6:0] seven_seg;
reg [31:0] cnt_div,cnt_dot;
reg [7:0] dot_col_buf[0:7];
wire [4:0] keypad_buf;
reg [2:0] row_count;
wire clk_div,clk_dot;
clk_divi myclk (clk,rst,32'd6250000, clk_div); // for button
clk_divi myclk2 (clk,rst,32'd10000, clk_dot); // for dot matrix
checkkeypad keypad_detect(clk,rst,keypad_row,keypad_col,keypad_buf);
always@ (posedge clk_dot or negedge rst)
begin
if (~rst)
begin
dot_row <= 8'd0;
dot_col <= 8'd0;
row_count <= 3'd0;
end
else
begin
row_count <= row_count + 1;
dot_col <= dot_col_buf[row_count];
case (row_count)
3'd0: dot_row <= 8'b01111111;
3'd1: dot_row <= 8'b10111111;
3'd2: dot_row <= 8'b11011111;
3'd3: dot_row <= 8'b11101111;
3'd4: dot_row <= 8'b11110111;
3'd5: dot_row <= 8'b11111011;
3'd6: dot_row <= 8'b11111101;
3'd7: dot_row <= 8'b11111110;
endcase
end
end
always@(posedge clk_div or negedge rst)
begin
if (~rst)
begin
dot_col_buf[0] <= 8'd0;
dot_col_buf[1] <= 8'd0;
dot_col_buf[2] <= 8'd0;
dot_col_buf[3] <= 8'd0;
dot_col_buf[4] <= 8'd0;
dot_col_buf[5] <= 8'd0;
dot_col_buf[6] <= 8'd0;
dot_col_buf[7] <= 8'd0;
end
else
begin
case (keypad_buf)
5'h0:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b11000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b11000000 | dot_col_buf[7];
end
5'h1:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00110000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00110000 | dot_col_buf[7];
end
5'h2:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00110000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00110000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'h3:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00110000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00110000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'h4:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00001100 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00001100 | dot_col_buf[7];
end
5'h5:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00001100 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00001100 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'h6:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00001100 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00001100 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'h7:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000011 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000011 | dot_col_buf[7];
end
5'h8:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000011 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000011 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'h9:
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000011 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000011 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
5'ha:
begin
dot_col_buf[0] <= 8'b00000000| dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000| dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000| dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000| dot_col_buf[3];
dot_col_buf[4] <= 8'b11000000| dot_col_buf[4];
dot_col_buf[5] <= 8'b11000000| dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000| dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000| dot_col_buf[7];
end
5'hb:
begin
dot_col_buf[0] <= 8'b00000000| dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000| dot_col_buf[1];
dot_col_buf[2] <= 8'b11000000| dot_col_buf[2];
dot_col_buf[3] <= 8'b11000000| dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000| dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000| dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000| dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000| dot_col_buf[7];
end
5'hc:
begin
dot_col_buf[0] <= 8'b00000011| dot_col_buf[0];
dot_col_buf[1] <= 8'b00000011| dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000| dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000| dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000| dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000| dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000| dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000| dot_col_buf[7];
end
5'hd:
begin
dot_col_buf[0] <= 8'b00001100| dot_col_buf[0];
dot_col_buf[1] <= 8'b00001100| dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000| dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000| dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000| dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000| dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000| dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000| dot_col_buf[7];
end
5'he:
begin
dot_col_buf[0] <= 8'b00110000| dot_col_buf[0];
dot_col_buf[1] <= 8'b00110000| dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000| dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000| dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000| dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000| dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000| dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000| dot_col_buf[7];
end
5'hf:
begin
dot_col_buf[0] <= 8'b11000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b11000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
default
begin
dot_col_buf[0] <= 8'b00000000 | dot_col_buf[0];
dot_col_buf[1] <= 8'b00000000 | dot_col_buf[1];
dot_col_buf[2] <= 8'b00000000 | dot_col_buf[2];
dot_col_buf[3] <= 8'b00000000 | dot_col_buf[3];
dot_col_buf[4] <= 8'b00000000 | dot_col_buf[4];
dot_col_buf[5] <= 8'b00000000 | dot_col_buf[5];
dot_col_buf[6] <= 8'b00000000 | dot_col_buf[6];
dot_col_buf[7] <= 8'b00000000 | dot_col_buf[7];
end
endcase
end
end
always@(*)
begin
case(keypad_buf)
5'h0:seven_seg = 7'b1000000;
5'h1:seven_seg = 7'b1111001;
5'h2:seven_seg = 7'b0100100;
5'h3:seven_seg = 7'b0110000;
5'h4:seven_seg = 7'b0011001;
5'h5:seven_seg = 7'b0010010;
5'h6:seven_seg = 7'b0000010;
5'h7:seven_seg = 7'b1111000;
5'h8:seven_seg = 7'b0000000;
5'h9:seven_seg = 7'b0010000;
5'ha:seven_seg = 7'b0100000;
5'hb:seven_seg = 7'b0000011;
5'hc:seven_seg = 7'b1000110;
5'hd:seven_seg = 7'b0100001;
5'he:seven_seg = 7'b0000100;
5'hf:seven_seg = 7'b0001110;
default: seven_seg = 7'b1000000;
endcase
end
endmodule |
module checkkeypad (clk,rst,keypadRow,keypadCol,keypadBuf); // output keypad buffer
input clk,rst;
input [3:0]keypadCol;
output reg[3:0]keypadRow;
output reg [4:0]keypadBuf;
reg [31:0]keypadDelay;
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
keypadRow <= 4'b1110;
keypadBuf <= 5'b11111;
keypadDelay <= 31'd0;
end
else
begin
if (keypadDelay == 32'd250000)
begin
keypadDelay <= 31'd0;
case ({keypadRow, keypadCol})
8'b1110_1110: keypadBuf <= 5'h7;
8'b1110_1101: keypadBuf <= 5'h4;
8'b1110_1011: keypadBuf <= 5'h1;
8'b1110_0111: keypadBuf <= 5'h0;
8'b1101_1110: keypadBuf <= 5'h8;
8'b1101_1101: keypadBuf <= 5'h5;
8'b1101_1011: keypadBuf <= 5'h2;
8'b1101_0111: keypadBuf <= 5'ha;
8'b1011_1110: keypadBuf <= 5'h9;
8'b1011_1101: keypadBuf <= 5'h6;
8'b1011_1011: keypadBuf <= 5'h3;
8'b1011_0111: keypadBuf <= 5'hb;
8'b0111_1110: keypadBuf <= 5'hc;
8'b0111_1101: keypadBuf <= 5'hd;
8'b0111_1011: keypadBuf <= 5'he;
8'b0111_0111: keypadBuf <= 5'hf;
default: keypadBuf <= keypadBuf;
endcase
case (keypadRow)
4'b1110: keypadRow <= 4'b1101;
4'b1101: keypadRow <= 4'b1011;
4'b1011: keypadRow <= 4'b0111;
4'b0111: keypadRow <= 4'b1110;
default: keypadRow <= 4'b1110;
endcase
end
else
keypadDelay <= keypadDelay + 1'b1;
end
end
endmodule |
module number_display (select,out1, out2, out3);
input [1:0]select;
output [6:0]out1;
output [6:0]out2;
output [6:0]out3;
reg [6:0]out1;
reg [6:0]out2;
reg [6:0]out3;
always @ (select)
begin
case (select)
2'b00:begin
out1 = 7'b1000000;
out2 = 7'b1111001;
out3 = 7'b0100100;
end
2'b01:begin
out1 = 7'b0000010;
out2 = 7'b1111000;
out3 = 7'b0000000;
end
2'b10:begin
out1 = 7'b0110000;
out2 = 7'b0100100;
out3 = 7'b1111001;
end
2'b11:begin
out1 = 7'b0000110;
out2 = 7'b0001000;
out3 = 7'b0001000;
end
endcase
end
endmodule |
module pkt_mux(
input clk,
input reset,
input [339:0] pkt_metadata_nocut,
input pkt_metadata_nocut_valid,
input [339:0] pkt_metadata_out, //[349:336]==pkt_addr,[335:0]
input pkt_metadata_out_valid,
output reg [4:0] pkt_addr,
output reg pkt_addr_wr,
output reg [63:0] metadata_data,
output reg metadata_data_wr,
output reg p2k_valid,
output reg [7:0] p2k_ingress,
output reg [127:0] p2k_rloc_src,
output reg [127:0] p2k_eid_dst,
output reg [71:0] p2k_metadata
);
reg pkt_metadata_nocut_rdreq,pkt_metadata_out_rdreq;
wire pkt_metadata_nocut_empty,pkt_metadata_out_empty;
wire [339:0] pkt_metadata_nocut_q,pkt_metadata_out_q;
reg [2:0] current_state;
parameter idle_s = 3'd0,
idle_s1 = 3'd1,
trans_s = 3'd2,
trans_s1 = 3'd3;
always @ (posedge clk or negedge reset)
if(!reset) begin
pkt_metadata_nocut_rdreq <= 1'b0;
pkt_metadata_out_rdreq <= 1'b0;
pkt_addr <= 5'b0;
pkt_addr_wr <= 1'b0;
p2k_valid <= 1'b0;
p2k_ingress <= 8'b0;
p2k_rloc_src <= 128'b0;
p2k_eid_dst <= 128'b0;
p2k_metadata <= 72'b0;
metadata_data_wr <= 1'b0;
metadata_data <= 64'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
pkt_addr <= 5'b0;
pkt_addr_wr <= 1'b0;
p2k_valid <= 1'b0;
p2k_ingress <= 8'b0;
p2k_rloc_src <= 128'b0;
p2k_eid_dst <= 128'b0;
p2k_metadata <= 72'b0;
metadata_data_wr <= 1'b0;
metadata_data <= 64'b0;
if(pkt_metadata_nocut_empty == 1'b1) begin
current_state <= idle_s1;
end
else begin
pkt_metadata_nocut_rdreq <= 1'b1;
current_state <= trans_s;
end
end
idle_s1: begin
pkt_addr <= 5'b0;
pkt_addr_wr <= 1'b0;
p2k_valid <= 1'b0;
p2k_ingress <= 8'b0;
p2k_rloc_src <= 128'b0;
p2k_eid_dst <= 128'b0;
p2k_metadata <= 72'b0;
metadata_data_wr <= 1'b0;
metadata_data <= 64'b0;
if(pkt_metadata_out_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
pkt_metadata_out_rdreq <= 1'b1;
current_state <= trans_s1;
end
end
trans_s: begin
pkt_metadata_nocut_rdreq <= 1'b0;
pkt_addr <= {1'b0,pkt_metadata_nocut_q[339:336]};
pkt_addr_wr <= 1'b1;
p2k_valid <= 1'b1;
p2k_ingress <= pkt_metadata_nocut_q[335:328];
p2k_rloc_src <= pkt_metadata_nocut_q[327:200];
p2k_eid_dst <= pkt_metadata_nocut_q[199:72];
p2k_metadata <= pkt_metadata_nocut_q[71:0];
metadata_data_wr <= 1'b1;
metadata_data <= pkt_metadata_nocut_q[63:0];
current_state <= idle_s1;
end
trans_s1: begin
pkt_metadata_out_rdreq <= 1'b0;
pkt_addr <= {1'b1,pkt_metadata_out_q[339:336]};
pkt_addr_wr <= 1'b1;
p2k_valid <= 1'b1;
p2k_ingress <= pkt_metadata_out_q[335:328];
p2k_rloc_src <= pkt_metadata_out_q[327:200];
p2k_eid_dst <= pkt_metadata_out_q[199:72];
p2k_metadata <= pkt_metadata_out_q[71:0];
metadata_data_wr <= 1'b1;
metadata_data <= pkt_metadata_out_q[63:0];
current_state <= idle_s;
end
endcase
end
fifo_340_16 pkt_metadata_nocut_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_metadata_nocut),
.rdreq(pkt_metadata_nocut_rdreq),
.wrreq(pkt_metadata_nocut_valid),
.empty(pkt_metadata_nocut_empty),
.q(pkt_metadata_nocut_q)
);
fifo_340_16 pkt_metadata_out_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_metadata_out),
.rdreq(pkt_metadata_out_rdreq),
.wrreq(pkt_metadata_out_valid),
.empty(pkt_metadata_out_empty),
.q(pkt_metadata_out_q)
);
endmodule |
module um(
input clk,
input reset,
output um2cdp_path,
input cdp2um_data_valid,
input [138:0] cdp2um_data,
output um2cdp_tx_enable,
output um2cdp_data_valid,
output [138:0] um2cdp_data,
input cdp2um_tx_enable,
output um2cdp_rule_wrreq,
output [29:0] um2cdp_rule,
input [4:0] cdp2um_rule_usedw,
input localbus_cs_n,
input localbus_rd_wr,
input [31:0] localbus_data,
input localbus_ale,
output localbus_ack_n,
output [31:0] localbus_data_out);
wire cs_n;
wire rd_wr;
wire [31:0] data;
wire ale;
wire ack_n;
wire [31:0] data_out;
wire mode;
wire ip_src_valid;
wire [130:0] ip_src;
wire [7:0] xtr_id;
wire pkt_metadata_cut_out_valid;
wire [359:0] pkt_metadata_cut_out;
wire [138:0] pkt_cut_data;
wire pkt_cut_data_valid;
wire [7:0] pkt_cut_data_usedw;
wire pkt_metadata_nocut_out_valid;
wire [359:0] pkt_metadata_nocut_out;
wire [138:0] pkt_nocut_data;
wire pkt_nocut_data_valid;
wire [7:0] pkt_nocut_data_usedw;
wire [4:0] pkt_addr; //[4] == cutpkt 0 nocut pkt
wire pkt_addr_wr;
wire [63:0] metadata_data;
wire metadata_data_wr;
wire [3:0] pkt_out_recycle_addr;
wire pkt_out_recycle_addr_wr;
wire [3:0] nocutpkt_out_recycle_addr;
wire nocutpkt_out_recycle_addr_wr;
wire [10:0] nocut_pkt_ram_rd_addr;
wire nocut_pkt_ram_rd;
wire [138:0] nocut_pkt_ram_data_q;
wire [10:0] ram_rd_addr;
wire ram_rd;
wire [138:0] ram_data_q;
wire p2k_valid;
wire [7:0] p2k_ingress;
wire [127:0] p2k_rloc_src;
wire [127:0] p2k_eid_dst;
wire [71:0] p2k_metadata;
wire k2m_metadata_valid;
wire [107:0] k2m_metadata;
wire action_valid;
wire [15:0] action;
wire action_data_valid;
wire [351:0] action_data;
wire pkt_ctl_valid; //contorl
wire [138:0] pkt_ctl;
wire [7:0] pkt_ctl_usedw;
wire rule_wr;
wire [19:0] rule; // [19] lisp pkt capsulate flag [18:8] length [7:0] out port;
wire pkt_out_valid;
wire [138:0] pkt_out;
wire [7:0] pkt_out_usedw;
localbus_manage localbus_manage(
.clk (clk),
.reset (reset),
.localbus_cs_n (localbus_cs_n),
.localbus_rd_wr (localbus_rd_wr),
.localbus_data (localbus_data),
.localbus_ale (localbus_ale),
.localbus_ack_n (localbus_ack_n),
.localbus_data_out (localbus_data_out),
.cs_n (cs_n),
.rd_wr (rd_wr),
.data (data),
.ale (ale),
.ack_n (ack_n),
.data_out (data_out),
.set_ip_src_valid (ip_src_valid),
.set_ip_src (ip_src),
.mode (mode),
.xtr_id (xtr_id));
parser parser(
.clk (clk),
.reset (reset),
.ip_src_valid (ip_src_valid),
.ip_src (ip_src),
.cdp2um_data_valid (cdp2um_data_valid),
.cdp2um_data (cdp2um_data),
.um2cdp_tx_enable (um2cdp_tx_enable),
.um2cdp_path (um2cdp_path),
.pkt_ctl_valid (pkt_ctl_valid), //contorl
.pkt_ctl (pkt_ctl),
.pkt_ctl_usedw (pkt_ctl_usedw),
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw));
buf_manage buf_manage(
.clk (clk),
.reset (reset),
//cut pkt
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.ram_rd_addr (ram_rd_addr),
.ram_rd (ram_rd),
.ram_data_q (ram_data_q),
.pkt_out_recycle_addr (pkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (pkt_out_recycle_addr_wr),
//no cut pkt
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw),
.nocut_pkt_ram_rd_addr (nocut_pkt_ram_rd_addr),
.nocut_pkt_ram_rd (nocut_pkt_ram_rd),
.nocut_pkt_ram_data_q (nocut_pkt_ram_data_q),
.nocutpkt_out_recycle_addr (nocutpkt_out_recycle_addr),
.nocutpkt_out_recycle_addr_wr (nocutpkt_out_recycle_addr_wr),
//result
.pkt_addr (pkt_addr), //[4] == cutpkt 0 nocut pkt
.pkt_addr_wr (pkt_addr_wr),
.metadata_data (metadata_data),
.metadata_data_wr (metadata_data_wr),
.p2k_valid (p2k_valid),
.p2k_ingress (p2k_ingress),
.p2k_rloc_src (p2k_rloc_src),
.p2k_eid_dst (p2k_eid_dst),
.p2k_metadata (p2k_metadata));
key_gen key_gen(
.clk (clk),
.reset (reset),
.p2k_valid (p2k_valid),
.p2k_ingress (p2k_ingress),
.p2k_rloc_src (p2k_rloc_src),
.p2k_eid_dst (p2k_eid_dst),
.p2k_metadata (p2k_metadata[71:64]),
.mode (mode),
.k2m_metadata_valid (k2m_metadata_valid),
.k2m_metadata (k2m_metadata));
match match(
.clk (clk),
.reset (reset),
.metadata_valid (k2m_metadata_valid),
.metadata (k2m_metadata),
.localbus_cs_n (cs_n),
.localbus_rd_wr (rd_wr),
.localbus_data (data),
.localbus_ale (ale),
.localbus_ack_n (ack_n),
.localbus_data_out (data_out),
.action_valid (action_valid),
.action (action),
.action_data_valid (action_data_valid),
.action_data (action_data));
action action_init(
.clk (clk),
.reset (reset),
.xtr_id (xtr_id),
//act
.action_valid (action_valid),
.action (action),
.action_data_valid (action_data_valid),
.action_data (action_data),
//pkt addr
.pkt_addr (pkt_addr), //[4] == cutpkt 0 nocut pkt
.pkt_addr_wr (pkt_addr_wr),
.metadata_data (metadata_data),
.metadata_data_wr (metadata_data_wr),
// cut pkt addr recycle
.pkt_out_recycle_addr (pkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (pkt_out_recycle_addr_wr),
//nopktcut pkt addr recycle
.nocutpkt_out_recycle_addr (nocutpkt_out_recycle_addr),
.nocutpkt_out_recycle_addr_wr (nocutpkt_out_recycle_addr_wr),
//no cut ram READ
.nocut_pkt_ram_rd_addr (nocut_pkt_ram_rd_addr),
.nocut_pkt_ram_rd (nocut_pkt_ram_rd),
.nocut_pkt_ram_data_q (nocut_pkt_ram_data_q),
//cut pkt RAM READ
.ram_rd_addr (ram_rd_addr),
.ram_rd (ram_rd),
.ram_data_q (ram_data_q),
//rule out
.rule_wr (rule_wr),
.rule (rule), // [19] lisp pkt capsulate flag [18:8] length [7:0] out port;
//pkt out
.pkt_out_valid (pkt_out_valid),
.pkt_out (pkt_out),
.pkt_out_usedw (pkt_out_usedw));
transmit transmit(
.clk (clk),
.reset (reset),
.mode (mode), //1:cengdie wang 0:shi wang
.pkt_ctl_valid (pkt_ctl_valid), //contorl
.pkt_ctl (pkt_ctl),
.pkt_ctl_usedw (pkt_ctl_usedw),
//rule
.rule_wr (rule_wr),
.rule (rule), // [19] lisp pkt capsulate flag [18:8] length [7:0] out port;
//pkt
.pkt_out_valid (pkt_out_valid),
.pkt_out (pkt_out),
.pkt_out_usedw (pkt_out_usedw),
.um2cdp_rule_wrreq (um2cdp_rule_wrreq),
.um2cdp_rule (um2cdp_rule),
.um2cdp_data_valid (um2cdp_data_valid),
.um2cdp_data (um2cdp_data),
.cdp2um_rule_usedw (cdp2um_rule_usedw),
.cdp2um_tx_enable (cdp2um_tx_enable));
endmodule |
module localbus_manage(
clk,
reset,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out,
cs_n,
rd_wr,
data,
ale,
ack_n,
data_out,
set_ip_src_valid,
set_ip_src,
mode,
xtr_id,
set_port
);
input clk;
input reset;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
output wire cs_n;
output wire rd_wr;
output wire [31:0] data;
output reg ale;
input ack_n;
input [31:0] data_out;
output reg set_ip_src_valid;
output reg [130:0] set_ip_src;
output reg mode;
output reg [7:0] xtr_id;
output reg [7:0] set_port;
//----------reg--------------//
reg [31:0] localbus_addr;
reg [127:0] ip_src_1,ip_src_2,ip_src_3,ip_src_4,ip_src_5,ip_src_6,ip_src_7,ip_src_8;
reg [127:0] read_ip_src;
//--state--//
reg [3:0] localbus_state;
parameter idle_s = 4'd0,
wait_set_s = 4'd1,
wait_read_s = 4'd2,
wait_ack_s = 4'd3,
wait_back_s = 4'd4;
assign rd_wr = localbus_rd_wr;
assign data = localbus_data;
assign cs_n = localbus_cs_n;
//----------------localbus_state-------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_ip_src_valid <= 1'b0;
set_ip_src <= 130'b0;
mode <= 1'b1;
xtr_id <= 8'h12;
set_port <= 8'h80;
ale <= 1'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
localbus_addr <= 32'b0;
read_ip_src <= 128'b0;
// ip_src_1 <= 128'b0;
ip_src_2 <= 128'b0;ip_src_3 <= 128'b0;ip_src_4 <= 128'b0;
ip_src_5 <= 128'b0;ip_src_6 <= 128'b0;ip_src_7 <= 128'b0;ip_src_8 <= 128'b0;
localbus_state <= idle_s;
end
else
begin
case(localbus_state)
idle_s:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_data[23] == 1'b1)
begin
ale <= 1'b0;
if(localbus_rd_wr == 1'b1) localbus_state <= wait_read_s;
else localbus_state <= wait_set_s;
case(localbus_data[6:4])
3'd0: read_ip_src <= ip_src_1;
3'd1: read_ip_src <= ip_src_2;
3'd2: read_ip_src <= ip_src_3;
3'd3: read_ip_src <= ip_src_4;
3'd4: read_ip_src <= ip_src_5;
3'd5: read_ip_src <= ip_src_6;
3'd6: read_ip_src <= ip_src_7;
3'd7: read_ip_src <= ip_src_8;
endcase
end
else
begin
ale <= 1'b1;
localbus_state <= wait_ack_s;
end
end
else
begin
ale <= 1'b0;
localbus_state <= idle_s;
end
end
wait_set_s:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[13:12])
2'd0: mode <= localbus_data[0];
2'd1:
begin
case(localbus_addr[1:0])
2'd0: set_ip_src[130:96] <= {localbus_addr[6:4],localbus_data};
2'd1: set_ip_src[95:64] <= localbus_data;
2'd2: set_ip_src[63:32] <= localbus_data;
2'd3:
begin
set_ip_src_valid <= 1'b1;
set_ip_src[31:0] <= localbus_data;
end
endcase
end
2'd2: xtr_id <= localbus_data[7:0];
2'd3: set_port <= localbus_data[7:0];
endcase
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_set_s;
end
wait_read_s:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[13:12])
2'd0: localbus_data_out <= {31'b0,mode};
2'd1:
begin
case(localbus_addr[1:0])
2'd0: localbus_data_out <= read_ip_src[127:96];
2'd1: localbus_data_out <= read_ip_src[95:64];
2'd2: localbus_data_out <= read_ip_src[63:32];
2'd3: localbus_data_out <= read_ip_src[31:0];
endcase
end
2'd2: localbus_data_out <= {24'b0,xtr_id};
2'd3: localbus_data_out <= {24'b0,set_port};
endcase
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_read_s;
end
wait_ack_s:
begin
ale <= 1'b0;
if(ack_n == 1'b0)
begin
localbus_data_out <= data_out;
localbus_ack_n <= 1'b0;
localbus_state <= wait_back_s;
end
else localbus_state <= wait_ack_s;
end
wait_back_s:
begin
if(set_ip_src_valid == 1'b1)
begin
case(set_ip_src[130:128])
3'd0: ip_src_1 <= set_ip_src[127:0];
3'd1: ip_src_2 <= set_ip_src[127:0];
3'd2: ip_src_3 <= set_ip_src[127:0];
3'd3: ip_src_4 <= set_ip_src[127:0];
3'd4: ip_src_5 <= set_ip_src[127:0];
3'd5: ip_src_6 <= set_ip_src[127:0];
3'd6: ip_src_7 <= set_ip_src[127:0];
3'd7: ip_src_8 <= set_ip_src[127:0];
endcase
end
set_ip_src_valid <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
localbus_state <= idle_s;
end
else localbus_state <= wait_back_s;
end
default:
begin
localbus_state <= idle_s;
end
endcase
end
end
endmodule |
module packet_buffer(
clk,
reset,
p2pb_pkt_valid,
p2pb_pkt,
p2pb_label_valid,
p2pb_label,
pb2p_label_valid,
pb2p_label,
pb2p_enable,
pb2b_label_enable,
fragment_valid,
fragment_label,
t2pb_label_valid,
t2pb_label,
pb2t_pkt_valid,
pb2t_pkt,
pb2t_enable,
pkt_buffer_count
);
input clk;
input reset;
input p2pb_pkt_valid;
input [138:0] p2pb_pkt;
input p2pb_label_valid;
input [31:0] p2pb_label;
output pb2p_label_valid;
output [31:0] pb2p_label;
output pb2p_enable;
input pb2b_label_enable;
input fragment_valid;
input [31:0] fragment_label;
input t2pb_label_valid;
input [31:0] t2pb_label;
output pb2t_pkt_valid;
output [138:0] pb2t_pkt;
output pb2t_enable;
output [7:0] pkt_buffer_count;
reg pb2p_label_valid;
reg [31:0] pb2p_label;
reg pb2p_enable;
reg pb2t_pkt_valid;
reg [138:0] pb2t_pkt;
reg pb2t_enable;
//----------------fifo-----------------//
//--pkt--//
reg fifo_pkt_rdreq;
wire [138:0] fifo_pkt_q;
wire [7:0] fifo_pkt_usedw;
wire fifo_pkt_empty;
//--parser_label--//
reg fifo_p_rdreq;
wire [31:0] fifo_p_q;
wire [3:0] fifo_p_usedw;
wire fifo_p_empty;
//--transmit_label--//
reg fifo_t_rdreq;
wire [31:0] fifo_t_q;
wire [3:0] fifo_t_usedw;
wire fifo_t_empty;
//--addr--//
reg fifo_addr_rdreq;
reg fifo_addr_wrreq;
reg [9:0] fifo_addr_data;
wire [9:0] fifo_addr_q;
wire [3:0] fifo_addr_usedw;
wire fifo_addr_empty;
reg [9:0] fifo_addr_q_r;
//--aging--//
reg fifo_aging_rdreq;
wire [9:0] fifo_aging_q;
wire [3:0] fifo_aging_usedw;
wire fifo_aging_empty;
reg fifo_aging_wrreq;
reg [9:0] fifo_aging_data;
//--recycle--//
reg fifo_recycle_rdreq;
wire [9:0] fifo_recycle_q;
wire [3:0] fifo_recycle_usedw;
wire fifo_recycle_empty;
reg fifo_recycle_wrreq;
reg [9:0] fifo_recycle_data;
//---ram---//
reg [10:0] addr_a,addr_b;
reg wren_a,wren_b,rden_a,rden_b;
wire [138:0] q_a,q_b;
reg [138:0] data_a;
//---------reg--------//
reg [31:0] label_p,label_t;
reg [9:0] addr_ini;
reg initial_finish;
reg flag_aging;
reg [7:0] pkt_buffer_count;
//---state---//
reg [3:0] store_state;
reg [3:0] read_state;
reg [3:0] addr_manage_state;
parameter idle = 4'd0,
initialization = 4'd1,
read_p_fifo = 4'd2,
label_parser = 4'd4,
assemble = 4'd5,
read_addr_fifo = 4'd6,
wait_store_tail = 4'd7,
discard = 4'd8;
parameter read_t_fifo = 4'd2,
wait_ram_1 = 4'd3,
wait_ram_2 = 4'd4,
read_ram = 4'd5;
parameter read_fifo_recycle = 4'd3,
read_fifo_aging = 4'd4;
//-------------------store_state-------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
fifo_p_rdreq <= 1'b0;
fifo_pkt_rdreq <= 1'b0;
fifo_addr_rdreq <= 1'b0;
wren_a <= 1'b0;
rden_a <= 1'b0;
addr_a <= 11'b0;
fifo_aging_wrreq <= 1'b0;
fifo_aging_data <= 10'b0;
fifo_addr_q_r <= 10'b0;
pkt_buffer_count <= 8'b0;
pb2p_label_valid <= 1'b0;
pb2p_label <= 32'b0;
store_state <= initialization;
end
else
begin
case(store_state)
initialization:
begin
if(initial_finish == 1'b1)
store_state <= idle;
end
idle:
begin
wren_a <= 1'b0;
fifo_aging_wrreq <= 1'b0;
pb2p_label_valid <= 1'b0;
fifo_addr_rdreq <= 1'b0;//zq0906
if((fifo_p_empty == 1'b0)&&(pb2b_label_enable == 1'b0))//zq0906
begin
fifo_p_rdreq <= 1'b1;
store_state <= read_p_fifo;
end
else
begin
store_state <= idle;
fifo_p_rdreq <= 1'b0;
end
end
read_p_fifo:
begin
fifo_p_rdreq <= 1'b0;
label_p <= fifo_p_q;
if(fifo_p_q[27] == 1'b1) //pkt aging
begin
fifo_aging_data <= fifo_p_q[9:0];
fifo_aging_wrreq <= 1'b1;
store_state <= idle;
end
else
begin
if(fifo_p_q[30] == 1'b1)//no body pkt
begin
pb2p_label <= fifo_p_q;
pb2p_label_valid <= 1'b1;
store_state <= idle;
end
else store_state <= label_parser;
end
end
label_parser:
begin
if(label_p[29:28]==2'b11)//no0
begin
if(fifo_pkt_empty == 1'b0)
begin
fifo_pkt_rdreq <= 1'b1;
store_state <= assemble;
end
else store_state <= label_parser;
end
else
begin
if((fifo_pkt_empty == 1'b0) && (fifo_addr_empty == 1'b0))
begin
fifo_addr_rdreq <= 1'b1;//zq0906
fifo_pkt_rdreq <= 1'b1;
fifo_addr_q_r <= fifo_addr_q;
store_state <= read_addr_fifo;
end
else store_state <= label_parser;
end
end
assemble:
begin
// addr_a <= {label_p[3:0],7'b0} + 11'd64;
addr_a <= {fifo_addr_q_r[3:0],7'b0} + 11'd64;//zq0906
data_a <= fifo_pkt_q;
wren_a <= 1'b1;
//pb2p_label_valid <= 1'b1;//zq0907
// pb2p_label <= {22'b0,label_p[9:0]};//zq0907
pb2p_label <= {22'b0,fifo_addr_q_r[9:0]};//zq0907
pkt_buffer_count <= pkt_buffer_count +8'd1;
if(fifo_pkt_q[138:136] == 3'b110)
begin
fifo_pkt_rdreq <= 1'b0;
pb2p_label_valid <= 1'b1;//zq0907
store_state <= idle;
end
else
begin
fifo_pkt_rdreq <= 1'b1;
store_state <= wait_store_tail;
end
end
read_addr_fifo:
begin
fifo_addr_rdreq <= 1'b0;
addr_a <= {fifo_addr_q_r[3:0],7'b0};
data_a <= fifo_pkt_q;
wren_a <= 1'b1;
if(fifo_pkt_q[138:136] == 3'b110)
begin
fifo_pkt_rdreq <= 1'b0;
pb2p_label_valid <= 1'b1;//zq0907
store_state <= idle;
end
else
begin
fifo_pkt_rdreq <= 1'b1;
store_state <= wait_store_tail;
end
// pb2p_label_valid <= 1'b1;
pb2p_label <= {label_p[31:10],fifo_addr_q_r};
pkt_buffer_count <= pkt_buffer_count +8'd1;
end
wait_store_tail:
begin
pb2p_label_valid <= 1'b0;
wren_a <= 1'b1;
addr_a <= addr_a + 11'd1;
if(fifo_pkt_q[138:136] == 3'b110)
begin
fifo_pkt_rdreq <= 1'b0;
pb2p_label_valid <= 1'b1;//zq0907
store_state <= idle;
if(label_p[29:28] == 2'b10)begin
data_a <= {3'b100,fifo_pkt_q[135:0]};
end
else begin
data_a <= fifo_pkt_q;
end
end
else data_a <= fifo_pkt_q;
end
discard:
begin
fifo_p_rdreq <= 1'b0;
pb2p_label_valid <= 1'b0;
if(fifo_pkt_q[138:136] == 3'b110)
begin
fifo_pkt_rdreq <= 1'b0;
store_state <=idle;
end
end
default:
begin
store_state <= idle;
end
endcase
end
end
//-------------------read_state-------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
fifo_t_rdreq <= 1'b0;
wren_b <= 1'b0;
addr_b <= 11'b0;
rden_b <= 1'b0;
pb2t_enable <= 1'b1;
pb2t_pkt_valid <= 1'b0;
pb2t_pkt <= 139'b0;
fifo_recycle_wrreq <= 1'b0;
fifo_recycle_data <= 10'b0;
read_state <= initialization;
end
else
begin
case(read_state)
initialization:
begin
if(initial_finish == 1'b1)
begin
read_state <= idle;
end
else read_state <= initialization;
end
idle:
begin
pb2t_pkt_valid <= 1'b0;
if(fifo_t_empty == 1'b0)
begin
fifo_t_rdreq <= 1'b1;
read_state <= read_t_fifo;
end
else read_state <= idle;
end
read_t_fifo:
begin
fifo_t_rdreq <= 1'b0;
label_t <= fifo_t_q;
if(fifo_t_q[30] == 1'b0)
begin
rden_b <= 1'b1;
case(fifo_t_q[29:28])
2'b10: addr_b <= {fifo_t_q[3:0],7'b0};
2'b11:
begin
addr_b <= {fifo_t_q[3:0],7'b0} + 11'd64;
fifo_recycle_data <= fifo_t_q[9:0];
fifo_recycle_wrreq <= 1'b1;
end
default:
begin
addr_b <= {fifo_t_q[3:0],7'b0};
fifo_recycle_data <= fifo_t_q[9:0];
fifo_recycle_wrreq <= 1'b1;
end
endcase
read_state <= wait_ram_1;
end
else
begin
read_state <= idle;
end
end
wait_ram_1:
begin
fifo_recycle_wrreq <= 1'b0;
addr_b <= addr_b + 11'd1;
read_state <= wait_ram_2;
end
wait_ram_2:
begin
addr_b <= addr_b + 11'd1;
read_state <= read_ram;
end
read_ram:
begin
addr_b <= addr_b + 11'd1;
pb2t_pkt_valid <= 1'b1;
if(q_b[138:136]== 3'b110)
begin
pb2t_pkt <= q_b;
read_state <= idle;
rden_b <= 1'b0;
end
else
begin
if((label_t[29:28] == 2'b10) && (addr_b[5:0] == 6'd1))//1024
begin
pb2t_pkt <= {3'b110,q_b[135:0]};
read_state <= idle;
rden_b <= 1'b0;
end
else
begin
pb2t_pkt <= q_b;
read_state <= read_ram;
end
end
end
default:
begin
read_state <= idle;
end
endcase
end
end
//---addr_manage_state--//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
initial_finish <= 1'b0;
fifo_addr_wrreq <= 1'b0;
fifo_addr_data <= 10'b0;
fifo_aging_rdreq <= 1'b0;
fifo_recycle_rdreq <= 1'b0;
addr_ini <= 10'b0;
addr_manage_state <= initialization;
end
else
begin
case(addr_manage_state)
initialization:
begin
fifo_addr_wrreq <= 1'b1;
fifo_addr_data <= addr_ini;
addr_ini <= addr_ini+10'd1;
if(addr_ini == 10'd15)
begin
initial_finish <= 1'b1;
addr_manage_state <= idle;
end
end
idle:
begin
fifo_addr_wrreq <= 1'b0;
if(fifo_recycle_empty == 1'b0)
begin
fifo_recycle_rdreq <= 1'b1;
addr_manage_state <= read_fifo_recycle;
end
else
begin
if(fifo_aging_empty == 1'b0)
begin
fifo_aging_rdreq <= 1'b1;
addr_manage_state <= read_fifo_aging;
end
else addr_manage_state <= idle;
end
end
read_fifo_recycle:
begin
fifo_recycle_rdreq <= 1'b0;
fifo_addr_data <= fifo_recycle_q;
fifo_addr_wrreq <= 1'b1;
addr_manage_state <= idle;
end
read_fifo_aging:
begin
fifo_recycle_rdreq <= 1'b0;
fifo_addr_data <= fifo_aging_q;
fifo_addr_wrreq <= 1'b1;
addr_manage_state <= idle;
end
default:
begin
addr_ini <= 10'b0;
initial_finish <= 1'b0;
fifo_addr_wrreq <= 1'b0;
addr_manage_state <= idle;
end
endcase
end
end
//-------------------enable_state-------------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
pb2p_enable <= 1'b0;
end
else
begin
if((fifo_addr_empty == 1'b0) && (initial_finish == 1'b1))
begin
pb2p_enable <= 1'b1;
end
else pb2p_enable <= 1'b0;
end
end
fifo_139_256 fifo_pkt(
.aclr(!reset),
.clock(clk),
.data(p2pb_pkt),
.rdreq(fifo_pkt_rdreq),
.wrreq(p2pb_pkt_valid),
.empty(fifo_pkt_empty),
.full(),
.q(fifo_pkt_q),
.usedw(fifo_pkt_usedw)
);
fifo_32_16 fifo_parser_label(
.aclr(!reset),
.clock(clk),
.data(p2pb_label),
.rdreq(fifo_p_rdreq),
.wrreq(p2pb_label_valid),
.empty(fifo_p_empty),
.full(),
.q(fifo_p_q),
.usedw(fifo_p_usedw)
);
fifo_32_16 fifo_transmit_label(
.aclr(!reset),
.clock(clk),
.data(t2pb_label),
.rdreq(fifo_t_rdreq),
.wrreq(t2pb_label_valid),
.empty(fifo_t_empty),
.full(),
.q(fifo_t_q),
.usedw(fifo_t_usedw)
);
//--addr_fifo--//
fifo_10_16 fifo_addr(
.aclr(!reset),
.clock(clk),
.data(fifo_addr_data),
.rdreq(fifo_addr_rdreq),
.wrreq(fifo_addr_wrreq),
.empty(fifo_addr_empty),
.full(),
.q(fifo_addr_q),
.usedw(fifo_addr_usedw)
);
ram_139_2048 ram_packt_payload(
.address_a(addr_a),
.address_b(addr_b),
.clock(clk),
.data_a(data_a),
.data_b(139'b0),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(1'b0),
.q_a(q_a),
.q_b(q_b)
);
fifo_10_16 fifo_aging(
.aclr(!reset),
.clock(clk),
.data(label_p[9:0]),
.rdreq(fifo_aging_rdreq),
.wrreq(flag_aging),
.empty(fifo_aging_empty),
.full(),
.q(fifo_aging_q),
.usedw(fifo_aging_usedw)
);
fifo_10_16 fifo_recycle(
.aclr(!reset),
.clock(clk),
.data(fifo_recycle_data),
.rdreq(fifo_recycle_rdreq),
.wrreq(fifo_recycle_wrreq),
.empty(fifo_recycle_empty),
.full(),
.q(fifo_recycle_q),
.usedw(fifo_recycle_usedw)
);
endmodule |
module pll_0 (
inclk0,
c0,
c1,
c2,
c3,
c4,
c5,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
wire [6:0] sub_wire0;
wire sub_wire7;
wire [0:0] sub_wire10 = 1'h0;
wire [3:3] sub_wire6 = sub_wire0[3:3];
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire c3 = sub_wire6;
wire locked = sub_wire7;
wire sub_wire8 = inclk0;
wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
altpll altpll_component (
.inclk (sub_wire9),
.clk (sub_wire0),
.locked (sub_wire7),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "2500",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 1,
altpll_component.clk3_phase_shift = "2500",
altpll_component.clk4_divide_by = 5,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 1,
altpll_component.clk4_phase_shift = "15000",
altpll_component.clk5_divide_by = 10,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 1,
altpll_component.clk5_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_0",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule |
module hold1clk(
clk,
reset,
stage_enable_in,
stage_enable_out
);
input clk;
input reset;
input stage_enable_in;
output stage_enable_out;
reg stage_enable_out;
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
stage_enable_out <= 1'b0;
end
else
begin
if(stage_enable_in == 1'b1)
begin
stage_enable_out <= 1'b1;
end
else stage_enable_out <= 1'b0;
end
end
endmodule |
module pll_clk(
clk_125m_sys,
clk_125m_core,
clk_25m_core,
clk_125m_tx0_7,
clk_125m_tx8_15,
clk_25m_tx,
clk_12m_5_mdio
);
input clk_125m_sys;
output clk_125m_tx0_7;
output clk_125m_core;
output clk_25m_core;
output clk_125m_tx8_15;
output clk_25m_tx;
output clk_12m_5_mdio;
wire clk_125m_tx0_7;
wire clk_125m_core;
wire clk_25m_core;
wire clk_125m_tx8_15;
wire clk_25m_tx;
wire clk_12m_5_mdio;
pll_0 pll_0(
.inclk0(clk_125m_sys),//125M sys
.c0(clk_125m_core),
.c1(clk_25m_core),
.c2(clk_125m_tx0_7),//port tx clk 0-7;
.c3(clk_125m_tx8_15),//port tx clk 8-15;
.c4(clk_25m_tx),
.c5(clk_12m_5_mdio),
.locked());
endmodule |
module pkt_recomb(
input clk,
input reset,
input pkt_metadata_cut_out_valid,
input [359:0] pkt_metadata_cut_out,
input [138:0] pkt_cut_data,
input pkt_cut_data_valid,
output [7:0] pkt_cut_data_usedw,
input buf_addr_wr,
input [3:0] buf_addr,
output reg [3:0] aging_recycle_addr,
output reg aging_recycle_addr_wr,
output reg [339:0] pkt_metadata_out, //[339:336]==pkt_addr,[335:0]
output reg pkt_metadata_out_valid,
input [10:0] ram_rd_addr,
input ram_rd,
output [138:0] ram_data_q
);
wire [3:0] buf_addr_q;
reg buf_addr_rd;
wire buf_addr_empty;
wire [138:0] pkt_cut_data_q;
reg pkt_cut_data_rdreq;
reg pkt_metadata_cut_out_rdreq;
wire [359:0] pkt_metadata_cut_out_q;
wire pkt_metadata_cut_out_empty;
reg [138:0] ram_data_in;
reg [10:0] ram_wr_addr;
reg ram_wr;
reg [359:0] pkt_metadata_cut_out_q_r;
reg [3:0] count;
reg [127:0] addr_3_0_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_7_4_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_11_8_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [127:0] addr_15_12_pkt_a_timing; //[127:96]==addr3 [95:64]=addr2 [63:32]=addr1 [31:0]==addr0
//[31:0] valid+timing(15)+id(16)
reg [10:0] buf_addr_q_r;
reg [3:0] timing_count;
reg flag;
reg [63:0] count_timing;
reg [14:0] timing;
reg [2:0] current_state;
parameter idle_s = 3'd0,
initial_s = 3'd1,
parse_metadata_s = 3'd2,
trans_b_s = 3'd3,
delete_5clock = 3'd4,
discard_s = 3'd5,
check_aging_s = 3'd6;
always @ (posedge clk or negedge reset)
if(!reset) begin
pkt_metadata_cut_out_rdreq <= 1'b0;
pkt_cut_data_rdreq <= 1'b0;
//buf_addr <= 4'b0;
buf_addr_rd <= 1'b0;
//buf_addr_wr <= 1'b0;
flag <= 1'b0;
count <= 4'b0;
buf_addr_q_r <= 11'b0;
addr_3_0_pkt_a_timing <= 128'b0;
addr_7_4_pkt_a_timing <= 128'b0;
addr_11_8_pkt_a_timing <= 128'b0;
addr_15_12_pkt_a_timing <= 128'b0;
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
pkt_metadata_out <= 340'b0;
pkt_metadata_out_valid <= 1'b0;
aging_recycle_addr <= 4'b0;
aging_recycle_addr_wr <= 1'b0;
timing_count <= 4'b0;
current_state <= initial_s;
end
else begin
case(current_state)
initial_s: begin
if(count == 4'hf) begin
count <= 4'b0;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
current_state <= initial_s;
end
end
idle_s: begin
count <= 4'b0;
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
pkt_metadata_out_valid <= 1'b0;
aging_recycle_addr_wr <= 1'b0;
if((buf_addr_empty == 1'b0)&&(pkt_metadata_cut_out_empty == 1'b0)) begin
pkt_metadata_cut_out_rdreq <= 1'b1;
pkt_metadata_cut_out_q_r <= pkt_metadata_cut_out_q;
current_state <= parse_metadata_s;
end
else begin
current_state <= idle_s;
end
end
parse_metadata_s: begin
pkt_metadata_cut_out_rdreq <= 1'b0;
if(pkt_metadata_cut_out_q_r[354] == 1'b0) begin //part 0
pkt_cut_data_rdreq <= 1'b1;
count <= 4'b0;
buf_addr_q_r <= {buf_addr_q[3:0],7'b0};
buf_addr_rd <= 1'b1;
flag <= 1'b0;
current_state <= delete_5clock;
case(buf_addr_q)
4'b0000: addr_3_0_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0001: addr_3_0_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0010: addr_3_0_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0011: addr_3_0_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0100: addr_7_4_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0101: addr_7_4_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0110: addr_7_4_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b0111: addr_7_4_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1000: addr_11_8_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1001: addr_11_8_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1010: addr_11_8_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1011: addr_11_8_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1100: addr_15_12_pkt_a_timing[31:0] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1101: addr_15_12_pkt_a_timing[63:32] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
4'b1110: addr_15_12_pkt_a_timing[95:64] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
default: addr_15_12_pkt_a_timing[127:96] <= {1'b1,timing[14:0],pkt_metadata_cut_out_q_r[351:336]};
endcase
end
else begin //part 1
flag <= 1'b1;
pkt_cut_data_rdreq <= 1'b1;
if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h0,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h1,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'h2,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_3_0_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'h3,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h4,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h5,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'h6,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_7_4_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'h7,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'h8,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'h9,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'ha,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_11_8_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'hb,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[15:0]) begin
buf_addr_q_r <= {4'hc,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[47:32]) begin
buf_addr_q_r <= {4'hd,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[79:64]) begin
buf_addr_q_r <= {4'he,7'b0} +11'd64;
current_state <= delete_5clock;
end
else if(pkt_metadata_cut_out_q_r[351:336] == addr_15_12_pkt_a_timing[111:96]) begin
buf_addr_q_r <= {4'hf,7'b0} +11'd64;
current_state <= delete_5clock;
end
else begin
current_state <= discard_s;
end
end
end
delete_5clock: begin
buf_addr_rd <= 1'b0;
if(count == 4'd4) begin
current_state <= trans_b_s;
end
else begin
count <= count + 1'b1;
current_state <= delete_5clock;
end
end
trans_b_s: begin
if(pkt_cut_data_q[138:136] == 3'b110) begin
pkt_cut_data_rdreq <= 1'b0;
if(flag == 1'b1) begin
pkt_metadata_out_valid <= 1'b1;
pkt_metadata_out <= {buf_addr_q_r[10:7],pkt_metadata_cut_out_q_r[335:0]};
ram_data_in <= {3'b110,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= check_aging_s;
end
else begin
ram_data_in <= {3'b100,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= idle_s;
end
end
else begin
buf_addr_q_r <= buf_addr_q_r + 1'b1;
ram_data_in <= {3'b100,pkt_cut_data_q[135:0]};
ram_wr_addr <= buf_addr_q_r;
ram_wr <= 1'b1;
current_state <= trans_b_s;
end
end
check_aging_s: begin
ram_data_in <= 139'b0;
ram_wr_addr <= 11'b0;
ram_wr <= 1'b0;
timing_count <= timing_count + 1'b1;
pkt_metadata_out_valid <= 1'b0;
case(timing_count)
4'b0000: begin
if(addr_3_0_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[30:16]) begin
if(timing > addr_3_0_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h0;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h0;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0001: begin
if(addr_3_0_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[62:48]) begin
if(timing > addr_3_0_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h1;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h1;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0010: begin
if(addr_3_0_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[94:80]) begin
if(timing > addr_3_0_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'h2;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'h2;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0011: begin
if(addr_3_0_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_3_0_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[126:112]) begin
if(timing > addr_3_0_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'h3;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'h3;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0100: begin
if(addr_7_4_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[30:16]) begin
if(timing > addr_7_4_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h4;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h4;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0101: begin
if(addr_7_4_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[62:48]) begin
if(timing > addr_7_4_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h5;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h5;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0110: begin
if(addr_7_4_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[94:80]) begin
if(timing > addr_7_4_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'h6;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'h6;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b0111: begin
if(addr_7_4_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_7_4_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_7_4_pkt_a_timing[126:112]) begin
if(timing > addr_7_4_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'h7;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_7_4_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'h7;
aging_recycle_addr_wr <= 1'b1;
addr_7_4_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1000: begin
if(addr_11_8_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[30:16]) begin
if(timing > addr_11_8_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'h8;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'h8;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1001: begin
if(addr_11_8_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[62:48]) begin
if(timing > addr_11_8_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'h9;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'h9;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1010: begin
if(addr_11_8_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[94:80]) begin
if(timing > addr_11_8_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'ha;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'ha;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1011: begin
if(addr_11_8_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_11_8_pkt_a_timing[126:112]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_11_8_pkt_a_timing[126:112]) begin
if(timing > addr_11_8_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'hb;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_11_8_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'hb;
aging_recycle_addr_wr <= 1'b1;
addr_11_8_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1100: begin
if(addr_15_12_pkt_a_timing[31] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[30:16]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_15_12_pkt_a_timing[30:16]) begin
if(timing > addr_15_12_pkt_a_timing[30:16] +15'd4) begin
aging_recycle_addr <= 4'hc;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[30:16]>15'd4) begin
aging_recycle_addr <= 4'hc;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[31:0] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1101: begin
if(addr_15_12_pkt_a_timing[63] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[62:48]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_15_12_pkt_a_timing[62:48]) begin
if(timing > addr_15_12_pkt_a_timing[62:48] +15'd4) begin
aging_recycle_addr <= 4'hd;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[62:48]>15'd4) begin
aging_recycle_addr <= 4'hd;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[63:32] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
4'b1110: begin
if(addr_3_0_pkt_a_timing[95] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[94:80]) begin
current_state <= check_aging_s;
end
else
if(timing > addr_3_0_pkt_a_timing[94:80]) begin
if(timing > addr_3_0_pkt_a_timing[94:80] +15'd4) begin
aging_recycle_addr <= 4'he;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
else begin
if(15'h7fff+ timing - addr_3_0_pkt_a_timing[94:80]>15'd4) begin
aging_recycle_addr <= 4'he;
aging_recycle_addr_wr <= 1'b1;
addr_3_0_pkt_a_timing[95:64] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= check_aging_s;
end
end
end
else begin
current_state <= check_aging_s;
end
end
default: begin
if(addr_15_12_pkt_a_timing[127] == 1'b1) begin
if(timing == addr_15_12_pkt_a_timing[126:112]) begin
current_state <= idle_s;
end
else
if(timing > addr_15_12_pkt_a_timing[126:112]) begin
if(timing > addr_15_12_pkt_a_timing[126:112] +15'd4) begin
aging_recycle_addr <= 4'hf;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= idle_s;
end
end
else begin
if(15'h7fff+ timing - addr_15_12_pkt_a_timing[126:112]>15'd4) begin
aging_recycle_addr <= 4'hf;
aging_recycle_addr_wr <= 1'b1;
addr_15_12_pkt_a_timing[127:96] <= 32'b0;
current_state <= idle_s;
end
else begin
current_state <= idle_s;
end
end
end
else begin
current_state <= idle_s;
end
end
endcase
end
discard_s: begin
if(pkt_cut_data_q[138:136] == 3'b110) begin
pkt_cut_data_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
//////////////////////////////////aging timing
always @ (posedge clk or negedge reset)
if(!reset) begin
timing <= 15'b0;
count_timing <= 64'b0;
end
else begin
if(count_timing == 64'd125000000) begin
timing <= timing + 1'b1;
count_timing <= 64'b0;
end
else begin
count_timing <= count_timing + 1'b1;
end
end
fifo_4_16 fifo_4_16_addr (
.aclr (!reset),
.clock (clk),
.data (buf_addr),
.rdreq (buf_addr_rd),
.wrreq (buf_addr_wr),
.empty (buf_addr_empty),
.q (buf_addr_q));
ram_2048_139 ram_2048_139 (
.aclr (!reset),
.clock (clk),
.data (ram_data_in),
.rdaddress (ram_rd_addr),
.rden (ram_rd),
.wraddress (ram_wr_addr),
.wren (ram_wr),
.q (ram_data_q));
fifo_139_256 pkt_cut_data_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_cut_data),
.rdreq (pkt_cut_data_rdreq),
.wrreq (pkt_cut_data_valid),
.q (pkt_cut_data_q),
.usedw (pkt_cut_data_usedw));
fifo_360_64 pkt_metadata_cut_out_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_metadata_cut_out),
.rdreq (pkt_metadata_cut_out_rdreq),
.wrreq (pkt_metadata_cut_out_valid),
.empty (pkt_metadata_cut_out_empty),
.q (pkt_metadata_cut_out_q));
endmodule |
module pkt_in_buf(
input clk,
input reset,
input pkt_metadata_nocut_out_valid,
input [359:0] pkt_metadata_nocut_out,
input [138:0] pkt_nocut_data,
input pkt_nocut_data_valid,
output [7:0] pkt_nocut_data_usedw,
input buf_addr_wr,
input [3:0] buf_addr,
output reg [339:0] pkt_metadata_nocut,
output reg pkt_metadata_nocut_valid,
/*
output reg [138:0] nocut_pkt_ram_data_in,
output reg [10:0] nocut_pkt_ram_wr_addr,
output reg nocut_pkt_ram_wr,
*/
input [10:0] nocut_pkt_ram_rd_addr,
input nocut_pkt_ram_rd,
output [138:0] nocut_pkt_ram_data_q
);
reg [359:0] pkt_metadata_nocut_out_q_r;
reg [10:0] buf_addr_q_r;
wire [3:0] buf_addr_q;
reg buf_addr_rd;
wire buf_addr_empty;
wire [359:0] pkt_metadata_nocut_out_q;
reg pkt_metadata_nocut_out_rdreq;
wire pkt_metadata_nocut_out_empty;
reg [138:0] nocut_pkt_ram_data_in;
reg [10:0] nocut_pkt_ram_wr_addr;
reg nocut_pkt_ram_wr;
wire [138:0] pkt_nocut_data_q;
reg pkt_nocut_data_rdreq;
reg [3:0] count;
reg [2:0] current_state;
parameter idle_s = 3'd0,
initial_s = 3'd1,
parse_metadata_s = 3'd2,
trans_b_s = 3'd3,
delete_5clock = 3'd4;
always @ (posedge clk or negedge reset)
if(!reset) begin
pkt_metadata_nocut <= 340'b0;
pkt_metadata_nocut_valid <= 1'b0;
buf_addr_rd <= 1'b0;
pkt_metadata_nocut_out_rdreq <= 1'b0;
pkt_metadata_nocut_out_q_r <= 360'b0;
buf_addr_q_r <= 11'b0;
nocut_pkt_ram_data_in <= 139'b0;
nocut_pkt_ram_wr_addr <= 11'b0;
nocut_pkt_ram_wr <= 1'b0;
pkt_nocut_data_rdreq <= 1'b0;
count <= 4'b0;
current_state <= initial_s;
end
else begin
case(current_state)
initial_s: begin
if(count == 4'hf) begin
count <= 4'b0;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
current_state <= initial_s;
end
end
idle_s: begin
pkt_metadata_nocut <= 340'b0;
pkt_metadata_nocut_valid <= 1'b0;
pkt_nocut_data_rdreq <= 1'b0;
nocut_pkt_ram_data_in <= 139'b0;
nocut_pkt_ram_wr_addr <= 11'b0;
nocut_pkt_ram_wr <= 1'b0;
count <= 4'b0;
if((pkt_metadata_nocut_out_empty == 1'b0)&&(buf_addr_empty == 1'b0)) begin
pkt_metadata_nocut_out_rdreq <= 1'b1;
buf_addr_rd <= 1'b1;
current_state <= parse_metadata_s;
end
else begin
current_state <= idle_s;
end
end
parse_metadata_s: begin
pkt_metadata_nocut_out_rdreq <= 1'b0;
buf_addr_rd <= 1'b0;
pkt_metadata_nocut_out_q_r <= pkt_metadata_nocut_out_q;
buf_addr_q_r <= {buf_addr_q[3:0],7'b0};
pkt_nocut_data_rdreq <= 1'b1;
if(pkt_metadata_nocut_out_q[335:328] == 8'd0) begin
count <= 4'b0;
current_state <= delete_5clock;
end
else begin
current_state <= trans_b_s;
end
end
delete_5clock: begin
if(count == 4'd4) begin
current_state <= trans_b_s;
end
else begin
count <= count + 1'b1;
current_state <= delete_5clock;
end
end
trans_b_s: begin
nocut_pkt_ram_data_in <= pkt_nocut_data_q;
nocut_pkt_ram_wr_addr <= buf_addr_q_r;
nocut_pkt_ram_wr <= 1'b1;
if(pkt_nocut_data_q[138:136] == 3'b110) begin
pkt_nocut_data_rdreq <= 1'b0;
pkt_metadata_nocut_valid <= 1'b1;
pkt_metadata_nocut <= {buf_addr_q_r[10:7],pkt_metadata_nocut_out_q_r[335:0]};
current_state <= idle_s;
end
else begin
buf_addr_q_r <= buf_addr_q_r + 1'b1;
current_state <= trans_b_s;
end
end
endcase
end
fifo_4_16 fifo_4_16_addr (
.aclr (!reset),
.clock (clk),
.data (buf_addr),
.rdreq (buf_addr_rd),
.wrreq (buf_addr_wr),
.empty (buf_addr_empty),
.q (buf_addr_q));
ram_2048_139 ram_2048_139 (
.aclr (!reset),
.clock (clk),
.data (nocut_pkt_ram_data_in),
.rdaddress (nocut_pkt_ram_rd_addr),
.rden (nocut_pkt_ram_rd),
.wraddress (nocut_pkt_ram_wr_addr),
.wren (nocut_pkt_ram_wr),
.q (nocut_pkt_ram_data_q));
fifo_139_256 pkt_cut_data_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_nocut_data),
.rdreq (pkt_nocut_data_rdreq),
.wrreq (pkt_nocut_data_valid),
.q (pkt_nocut_data_q),
.usedw (pkt_nocut_data_usedw));
fifo_360_64 pkt_metadata_nocut_out_fifo(
.aclr (!reset),
.clock (clk),
.data (pkt_metadata_nocut_out),
.rdreq (pkt_metadata_nocut_out_rdreq),
.wrreq (pkt_metadata_nocut_out_valid),
.empty (pkt_metadata_nocut_out_empty),
.q (pkt_metadata_nocut_out_q));
endmodule |
module alt_ddrx_cmd_queue
# (parameter MEM_IF_CSR_COL_WIDTH = 4,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 2,
MEM_IF_CSR_CS_WIDTH = 2,
CTL_CMD_QUEUE_DEPTH = 4,
CTL_LOOK_AHEAD_DEPTH = 4,
MEM_IF_ROW_WIDTH = 16,
MEM_IF_COL_WIDTH = 12,
MEM_IF_BA_WIDTH = 3,
MEM_IF_CHIP_BITS = 2,
LOCAL_ADDR_WIDTH = 33,
DWIDTH_RATIO = 4,
ENABLE_BURST_MERGE = 1,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
//input
ctl_clk ,
ctl_reset_n ,
read_req_to_cmd_queue ,
write_req_to_cmd_queue ,
local_size ,
local_autopch_req ,
local_multicast ,
local_cs_addr ,
local_bank_addr ,
local_row_addr ,
local_col_addr ,
//input from State Machine
fetch,
//output
cmd_fifo_empty,
cmd_fifo_full,
cmd_fifo_wren,
cmd0_is_a_read,
cmd0_is_a_write,
cmd0_autopch_req,
cmd0_burstcount,
cmd0_chip_addr,
cmd0_row_addr,
cmd0_bank_addr,
cmd0_col_addr,
cmd0_is_valid,
cmd0_multicast_req,
cmd1_is_a_read,
cmd1_is_a_write,
cmd1_chip_addr,
cmd1_row_addr,
cmd1_bank_addr,
cmd1_is_valid,
cmd1_multicast_req,
cmd2_is_a_read,
cmd2_is_a_write,
cmd2_chip_addr,
cmd2_row_addr,
cmd2_bank_addr,
cmd2_is_valid,
cmd2_multicast_req,
cmd3_is_a_read,
cmd3_is_a_write,
cmd3_chip_addr,
cmd3_row_addr,
cmd3_bank_addr,
cmd3_is_valid,
cmd3_multicast_req,
cmd4_is_a_read,
cmd4_is_a_write,
cmd4_is_valid,
cmd4_chip_addr,
cmd4_row_addr,
cmd4_bank_addr,
cmd4_multicast_req,
cmd5_is_a_read,
cmd5_is_a_write,
cmd5_is_valid,
cmd5_chip_addr,
cmd5_row_addr,
cmd5_bank_addr,
cmd5_multicast_req,
cmd6_is_a_read,
cmd6_is_a_write,
cmd6_is_valid,
cmd6_chip_addr,
cmd6_row_addr,
cmd6_bank_addr,
cmd6_multicast_req,
cmd7_is_a_read,
cmd7_is_a_write,
cmd7_is_valid,
cmd7_chip_addr,
cmd7_row_addr,
cmd7_bank_addr,
cmd7_multicast_req
);
localparam LOCAL_SIZE_WIDTH = 2;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH + MEM_IF_COL_WIDTH;
localparam THIS_ENTRY_WIDTH = 1 + 1 + 1 + MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH + MEM_IF_COL_WIDTH;
localparam MAX_COL = MEM_IF_COL_WIDTH;
localparam MAX_ROW = MEM_IF_ROW_WIDTH;
localparam MAX_BANK = MEM_IF_BA_WIDTH;
localparam MAX_CS = MEM_IF_CHIP_BITS;
input ctl_clk ; // controller clock
input ctl_reset_n ; // controller reset_n, synchronous to ctl_clk
input read_req_to_cmd_queue ;
input write_req_to_cmd_queue ;
input [LOCAL_SIZE_WIDTH-1:0] local_size ;
input local_autopch_req ;
input local_multicast ;
input [MEM_IF_CHIP_BITS-1:0] local_cs_addr ;
input [MEM_IF_ROW_WIDTH-1:0] local_row_addr ;
input [MEM_IF_BA_WIDTH-1:0] local_bank_addr ;
input [MEM_IF_COL_WIDTH-1:0] local_col_addr ;
output cmd_fifo_empty ;
output cmd_fifo_full ;
output cmd_fifo_wren ;
//input from State Machine
input fetch;
output cmd0_is_valid;
output cmd0_is_a_read;
output cmd0_is_a_write;
output cmd0_autopch_req;
output [LOCAL_SIZE_WIDTH-1:0] cmd0_burstcount;
output [MEM_IF_CHIP_BITS-1:0] cmd0_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd0_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd0_bank_addr;
output [MEM_IF_COL_WIDTH-1:0] cmd0_col_addr;
output cmd0_multicast_req;
output cmd1_is_valid;
output cmd1_is_a_read;
output cmd1_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd1_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd1_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd1_bank_addr;
output cmd1_multicast_req;
output cmd2_is_valid;
output cmd2_is_a_read;
output cmd2_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd2_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd2_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd2_bank_addr;
output cmd2_multicast_req;
output cmd3_is_valid;
output cmd3_is_a_read;
output cmd3_is_a_write;
output [MEM_IF_CHIP_BITS-1:0] cmd3_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd3_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd3_bank_addr;
output cmd3_multicast_req;
output cmd4_is_a_read;
output cmd4_is_a_write;
output cmd4_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd4_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd4_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd4_bank_addr;
output cmd4_multicast_req;
output cmd5_is_a_read;
output cmd5_is_a_write;
output cmd5_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd5_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd5_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd5_bank_addr;
output cmd5_multicast_req;
output cmd6_is_a_read;
output cmd6_is_a_write;
output cmd6_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd6_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd6_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd6_bank_addr;
output cmd6_multicast_req;
output cmd7_is_a_read;
output cmd7_is_a_write;
output cmd7_is_valid;
output [MEM_IF_CHIP_BITS-1:0] cmd7_chip_addr;
output [MEM_IF_ROW_WIDTH-1:0] cmd7_row_addr;
output [MEM_IF_BA_WIDTH-1:0] cmd7_bank_addr;
output cmd7_multicast_req;
integer n;
integer j;
integer k;
integer m;
reg [BUFFER_WIDTH-1:0] pipe[CTL_CMD_QUEUE_DEPTH-1:0];
reg pipefull[CTL_CMD_QUEUE_DEPTH-1:0];
reg [LOCAL_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [MEM_IF_CHIP_BITS-1:0] last_chip_addr;
reg [MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [LOCAL_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [MEM_IF_CHIP_BITS-1:0] last2_chip_addr;
reg [MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [MEM_IF_COL_WIDTH-1:0] last2_col_addr;
wire [MEM_IF_CHIP_BITS-1:0] cs_addr ;
wire [MEM_IF_ROW_WIDTH-1:0] row_addr ;
wire [MEM_IF_BA_WIDTH-1:0] bank_addr;
wire [MEM_IF_COL_WIDTH-1:0] col_addr ;
wire read_req_to_cmd_queue ;
wire write_req_to_cmd_queue ;
wire local_autopch_req ;
wire local_multicast;
wire local_multicast_gated;
wire [LOCAL_SIZE_WIDTH-1:0] local_size;
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire wreq_to_fifo;
wire [MEM_IF_CHIP_BITS-1:0] pipe_chip_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_ROW_WIDTH-1:0] pipe_row_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_BA_WIDTH-1:0] pipe_bank_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire [MEM_IF_COL_WIDTH-1:0] pipe_col_addr [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_read_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_write_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_autopch_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire pipe_multicast_req [CTL_CMD_QUEUE_DEPTH-1:0];
wire [LOCAL_SIZE_WIDTH-1:0] pipe_burstcount [CTL_CMD_QUEUE_DEPTH-1:0];
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last;
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CTL_CMD_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
wire cmd_fifo_wren;
wire cmd0_is_valid;
wire cmd0_is_a_read;
wire cmd0_is_a_write;
wire cmd0_autopch_req;
wire [LOCAL_SIZE_WIDTH-1:0] cmd0_burstcount;
wire [MEM_IF_CHIP_BITS-1:0] cmd0_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd0_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd0_bank_addr;
wire [MEM_IF_COL_WIDTH-1:0] cmd0_col_addr;
wire cmd0_multicast_req;
wire cmd1_is_valid;
wire cmd1_is_a_read;
wire cmd1_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd1_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd1_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd1_bank_addr;
wire cmd1_multicast_req;
wire cmd2_is_valid;
wire cmd2_is_a_read;
wire cmd2_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd2_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd2_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd2_bank_addr;
wire cmd2_multicast_req;
wire cmd3_is_valid;
wire cmd3_is_a_read;
wire cmd3_is_a_write;
wire [MEM_IF_CHIP_BITS-1:0] cmd3_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd3_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd3_bank_addr;
wire cmd3_multicast_req;
wire cmd4_is_a_read;
wire cmd4_is_a_write;
wire cmd4_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd4_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd4_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd4_bank_addr;
wire cmd4_multicast_req;
wire cmd5_is_a_read;
wire cmd5_is_a_write;
wire cmd5_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd5_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd5_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd5_bank_addr;
wire cmd5_multicast_req;
wire cmd6_is_a_read;
wire cmd6_is_a_write;
wire cmd6_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd6_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd6_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd6_bank_addr;
wire cmd6_multicast_req;
wire cmd7_is_a_read;
wire cmd7_is_a_write;
wire cmd7_is_valid;
wire [MEM_IF_CHIP_BITS-1:0] cmd7_chip_addr;
wire [MEM_IF_ROW_WIDTH-1:0] cmd7_row_addr;
wire [MEM_IF_BA_WIDTH-1:0] cmd7_bank_addr;
wire cmd7_multicast_req;
genvar i;
assign cs_addr = local_cs_addr;
assign bank_addr = local_bank_addr;
assign row_addr = local_row_addr;
assign col_addr = local_col_addr;
// gate multicast request with write request, we only support multicast write
assign local_multicast_gated = local_multicast & write_req_to_cmd_queue;
// mapping of buffer_input
assign buffer_input = {read_req_to_cmd_queue,write_req_to_cmd_queue,local_multicast_gated,local_autopch_req,local_size,cs_addr,row_addr,bank_addr,col_addr};
//====================== Bus to output signals mapping =======================
//pipe address
generate begin
for(i=0; i<CTL_CMD_QUEUE_DEPTH; i=i+1) begin : pipe_loop
assign pipe_read_req[i] = pipe[i][BUFFER_WIDTH-1];
assign pipe_write_req[i] = pipe[i][BUFFER_WIDTH-2];
assign pipe_multicast_req[i] = pipe[i][BUFFER_WIDTH-3];
assign pipe_autopch_req[i] = pipe[i][BUFFER_WIDTH-4];
assign pipe_burstcount[i] = pipe[i][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_chip_addr[i] = pipe[i][MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_row_addr[i] = pipe[i][MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH];
assign pipe_bank_addr[i] = pipe[i][MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_COL_WIDTH];
assign pipe_col_addr[i] = pipe[i][MEM_IF_COL_WIDTH - 1 : 0];
end
end
endgenerate
assign cmd0_is_valid = pipefull[0];
assign cmd0_is_a_read = pipe_read_req [0];
assign cmd0_is_a_write = pipe_write_req [0];
assign cmd0_autopch_req = pipe_autopch_req[0];
assign cmd0_burstcount = pipe_burstcount [0];
assign cmd0_chip_addr = pipe_chip_addr [0];
assign cmd0_row_addr = pipe_row_addr [0];
assign cmd0_bank_addr = pipe_bank_addr [0];
assign cmd0_col_addr = pipe_col_addr [0];
assign cmd0_multicast_req = pipe_multicast_req [0];
generate
if (CTL_LOOK_AHEAD_DEPTH > 0)
begin
assign cmd1_is_valid = pipefull[1];
assign cmd1_is_a_read = pipe_read_req [1];
assign cmd1_is_a_write = pipe_write_req [1];
assign cmd1_chip_addr = pipe_chip_addr [1];
assign cmd1_row_addr = pipe_row_addr [1];
assign cmd1_bank_addr = pipe_bank_addr [1];
assign cmd1_multicast_req = pipe_multicast_req [1];
end
else
begin
assign cmd1_is_valid = 0;
assign cmd1_is_a_read = 0;
assign cmd1_is_a_write = 0;
assign cmd1_chip_addr = 0;
assign cmd1_row_addr = 0;
assign cmd1_bank_addr = 0;
assign cmd1_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 2)
begin
assign cmd2_is_valid = pipefull[2];
assign cmd2_is_a_read = pipe_read_req [2];
assign cmd2_is_a_write = pipe_write_req [2];
assign cmd2_chip_addr = pipe_chip_addr [2];
assign cmd2_row_addr = pipe_row_addr [2];
assign cmd2_bank_addr = pipe_bank_addr [2];
assign cmd2_multicast_req = pipe_multicast_req [2];
assign cmd3_is_valid = pipefull[3];
assign cmd3_is_a_read = pipe_read_req [3];
assign cmd3_is_a_write = pipe_write_req [3];
assign cmd3_chip_addr = pipe_chip_addr [3];
assign cmd3_row_addr = pipe_row_addr [3];
assign cmd3_bank_addr = pipe_bank_addr [3];
assign cmd3_multicast_req = pipe_multicast_req [3];
end
else
begin
assign cmd2_is_valid = 0;
assign cmd2_is_a_read = 0;
assign cmd2_is_a_write = 0;
assign cmd2_chip_addr = 0;
assign cmd2_row_addr = 0;
assign cmd2_bank_addr = 0;
assign cmd2_multicast_req = 0;
assign cmd3_is_valid = 0;
assign cmd3_is_a_read = 0;
assign cmd3_is_a_write = 0;
assign cmd3_chip_addr = 0;
assign cmd3_row_addr = 0;
assign cmd3_bank_addr = 0;
assign cmd3_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 4)
begin
assign cmd4_is_valid = pipefull[4];
assign cmd4_is_a_read = pipe_read_req [4];
assign cmd4_is_a_write = pipe_write_req[4];
assign cmd4_chip_addr = pipe_chip_addr[4];
assign cmd4_row_addr = pipe_row_addr [4];
assign cmd4_bank_addr = pipe_bank_addr[4];
assign cmd4_multicast_req = pipe_multicast_req [4];
assign cmd5_is_valid = pipefull[5];
assign cmd5_is_a_read = pipe_read_req [5];
assign cmd5_is_a_write = pipe_write_req[5];
assign cmd5_chip_addr = pipe_chip_addr[5];
assign cmd5_row_addr = pipe_row_addr [5];
assign cmd5_bank_addr = pipe_bank_addr[5];
assign cmd5_multicast_req = pipe_multicast_req [5];
end
else
begin
assign cmd4_is_valid = 0;
assign cmd4_is_a_read = 0;
assign cmd4_is_a_write = 0;
assign cmd4_chip_addr = 0;
assign cmd4_row_addr = 0;
assign cmd4_bank_addr = 0;
assign cmd4_multicast_req = 0;
assign cmd5_is_valid = 0;
assign cmd5_is_a_read = 0;
assign cmd5_is_a_write = 0;
assign cmd5_chip_addr = 0;
assign cmd5_row_addr = 0;
assign cmd5_bank_addr = 0;
assign cmd5_multicast_req = 0;
end
endgenerate
generate
if (CTL_LOOK_AHEAD_DEPTH > 6)
begin
assign cmd6_is_valid = pipefull[6];
assign cmd6_is_a_read = pipe_read_req [6];
assign cmd6_is_a_write = pipe_write_req[6];
assign cmd6_chip_addr = pipe_chip_addr[6];
assign cmd6_row_addr = pipe_row_addr [6];
assign cmd6_bank_addr = pipe_bank_addr[6];
assign cmd6_multicast_req = pipe_multicast_req [6];
assign cmd7_is_valid = pipefull[7];
assign cmd7_is_a_read = pipe_read_req [7];
assign cmd7_is_a_write = pipe_write_req[7];
assign cmd7_chip_addr = pipe_chip_addr[7];
assign cmd7_row_addr = pipe_row_addr [7];
assign cmd7_bank_addr = pipe_bank_addr[7];
assign cmd7_multicast_req = pipe_multicast_req [7];
end
else
begin
assign cmd6_is_valid = 0;
assign cmd6_is_a_read = 0;
assign cmd6_is_a_write = 0;
assign cmd6_chip_addr = 0;
assign cmd6_row_addr = 0;
assign cmd6_bank_addr = 0;
assign cmd6_multicast_req = 0;
assign cmd7_is_valid = 0;
assign cmd7_is_a_read = 0;
assign cmd7_is_a_write = 0;
assign cmd7_chip_addr = 0;
assign cmd7_row_addr = 0;
assign cmd7_bank_addr = 0;
assign cmd7_multicast_req = 0;
end
endgenerate
//====================== end of Bus to output signals mapping ================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {MEM_IF_CHIP_BITS{1'b0}};
last_row_addr <= {MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {MEM_IF_COL_WIDTH{1'b0}};
last_size <= {LOCAL_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (wreq_to_fifo) begin
last_read_req <= read_req_to_cmd_queue;
last_write_req <= write_req_to_cmd_queue;
last_multicast <= local_multicast_gated;
last_chip_addr <= cs_addr;
last_bank_addr <= bank_addr;
last_row_addr <= row_addr;
last_col_addr <= col_addr;
last_size <= local_size;
end
else if (can_merge)
last_size <= 2;
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {MEM_IF_CHIP_BITS{1'b0}};
last2_row_addr <= {MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {LOCAL_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (wreq_to_fifo) begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
if (fetch) begin // fetch and write
if (can_merge && last != 1)
begin
if (wreq_to_fifo)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (wreq_to_fifo) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (wreq_to_fifo) begin // write only
if (can_merge)
begin
// do nothing
end
else
if (!cmd_fifo_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
assign can_merge = (ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((DWIDTH_RATIO == 2) ? (last2_col_addr[MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[MEM_IF_COL_WIDTH-1 : 3]) )
& ((DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign wreq_to_fifo = (read_req_to_cmd_queue) | (write_req_to_cmd_queue);
assign cmd_fifo_wren = (read_req_to_cmd_queue) | (write_req_to_cmd_queue);
assign cmd_fifo_empty = !pipefull[0];
assign cmd_fifo_full = pipefull[CTL_CMD_QUEUE_DEPTH-1];
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH; j=j+1) begin
pipefull[j] <= 1'b0;
pipe[j] <= 0;
end
end
else
if (fetch) begin // fetch and write
if (can_merge && last != 1)
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0) begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one) begin
pipefull[j] <= wreq_to_fifo;
pipe[j] <= buffer_input;
end
else if (j == last_minus_two) begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else begin
pipefull[j] <= pipefull[j+1];
pipe[j] <= pipe[j+1];
end
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= 1'b0;
pipe[CTL_CMD_QUEUE_DEPTH-1] <= pipe[CTL_CMD_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0) begin
pipefull[j] <= wreq_to_fifo;
pipe[j] <= buffer_input;
end
else begin
pipefull[j] <= pipefull[j+1];
pipe[j] <= pipe[j+1];
end
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= pipefull[CTL_CMD_QUEUE_DEPTH-1] & wreq_to_fifo;
pipe[CTL_CMD_QUEUE_DEPTH-1] <= pipe[CTL_CMD_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (wreq_to_fifo) begin // write only
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CTL_CMD_QUEUE_DEPTH; j=j+1) begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0) begin
pipefull[j] <= 1'b1;
pipe[j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0) begin
pipefull[0] <= 1'b1;
pipe[0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CTL_CMD_QUEUE_DEPTH-1; j=j+1) begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
pipefull[j] <= 1'b0;
else
pipefull[j] <= pipefull[j+1];
end
pipefull[CTL_CMD_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][LOCAL_SIZE_WIDTH + MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH - 1 : MEM_IF_CHIP_BITS + MEM_IF_ROW_WIDTH + MEM_IF_BA_WIDTH + MEM_IF_COL_WIDTH] <= 2;
end
end
//============================ end of queue ===============================
function integer log2; //constant function
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule |
module altera_avalon_half_rate_bridge (
avs_reset_n,
avm_reset_n,
// Avalon slave
avs_clk,
avs_chipselect,
avs_address,
avs_write,
avs_read,
avs_byteenable,
avs_writedata,
avs_readdata,
avs_waitrequest,
avs_readdatavalid,
// Avalon master
avm_clk,
avm_burstcount,
avm_address,
avm_write,
avm_read,
avm_byteenable,
avm_writedata,
avm_readdata,
avm_waitrequest,
avm_readdatavalid
);
localparam ENABLE_BURSTING_MASTER = 1;
parameter AVM_DATA_WIDTH = 32;
parameter AVM_ADDR_WIDTH = 28;
parameter AVM_BYTE_WIDTH = 4;
parameter AVS_DATA_WIDTH = 64;
parameter AVS_ADDR_WIDTH = 25;
parameter AVS_BYTE_WIDTH = 8;
// constant function to get number of bits from size
// e.g. burstlength 8 requires 4 bit burstcount [3:0]
function integer log2 (input integer size);
begin
for(log2 = 0; size > 0; log2 = log2 + 1)
size = size >> 1;
log2 = log2 - 1;
end
endfunction
// Avalon slave
input avs_reset_n; // Active low asynch reset
input avm_reset_n;
input avs_clk;
input avs_chipselect;
input [AVS_ADDR_WIDTH-1:0] avs_address;
input avs_write;
input avs_read;
input [AVS_BYTE_WIDTH-1:0] avs_byteenable;
input [AVS_DATA_WIDTH-1:0] avs_writedata;
output [AVS_DATA_WIDTH-1:0] avs_readdata;
output avs_waitrequest;
output avs_readdatavalid;
// Avalon master
input avm_clk; // Must be 2x and synchronous to avs_clk
input [AVM_DATA_WIDTH-1:0] avm_readdata;
input avm_waitrequest;
input avm_readdatavalid;
output [AVM_ADDR_WIDTH-1:0] avm_address;
output avm_write;
output avm_read;
output [AVM_BYTE_WIDTH-1:0] avm_byteenable;
output [AVM_DATA_WIDTH-1:0] avm_writedata;
output [1:0] avm_burstcount;
reg avs_waitrequest;
wire [2:0] avm_nxt_wr_txfers;
wire [2:0] avm_nxt_rd_txfers;
reg avm_read;
reg avm_write;
reg [AVM_ADDR_WIDTH-1:0] avm_address;
reg [AVM_BYTE_WIDTH-1:0] avm_byteenable;
reg [AVM_DATA_WIDTH-1:0] avm_writedata;
wire [1:0] avm_burstcount = 2'd2;
wire [AVM_BYTE_WIDTH:0] avm_addr_offset;
generate
if (ENABLE_BURSTING_MASTER)
assign avm_addr_offset = 0;
else
assign avm_addr_offset = (1'b1<<((log2(AVM_BYTE_WIDTH))));
endgenerate
//---------------------------------------------------------------------------
// AVS Control
//---------------------------------------------------------------------------
wire [2:0] avm_nxt_txfers;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_waitrequest <= 1'b1;
else
avs_waitrequest <= (avm_nxt_txfers >= 4'b011);
reg avs_toggle;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_toggle <= 1'b0;
else
avs_toggle <= ~avs_toggle;
reg avm_toggle;
reg avm_toggle_r;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_toggle <= 1'b0;
avm_toggle_r <= 1'b0;
end
else
begin
avm_toggle <= avs_toggle;
avm_toggle_r <= avm_toggle;
end
wire avs_clk_ph = avm_toggle ^ avm_toggle_r;
//---------------------------------------------------------------------------
// Write path
//---------------------------------------------------------------------------
// Buffers can hold two avs transfers equivalent to four avm transfers
reg [AVS_DATA_WIDTH-1:0] avs_writedata_r;
reg [AVS_BYTE_WIDTH-1:0] avs_byteenable_r;
reg [AVM_ADDR_WIDTH-1:0] avs_addr_r;
reg [AVS_DATA_WIDTH-1:0] avs_skid;
reg [AVS_BYTE_WIDTH-1:0] avs_byte_skid;
reg [AVM_ADDR_WIDTH-1:0] avs_addr_skid;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
begin
avs_writedata_r <= {AVS_DATA_WIDTH{1'b0}};
avs_byteenable_r <= {AVS_BYTE_WIDTH{1'b0}};
avs_addr_r <= {AVM_ADDR_WIDTH{1'b0}};
avs_skid <= {AVS_DATA_WIDTH{1'b0}};
avs_byte_skid <= {AVS_BYTE_WIDTH{1'b0}};
avs_addr_skid <= {AVM_ADDR_WIDTH{1'b0}};
end
else if (avs_chipselect & ~avs_waitrequest)
begin
avs_writedata_r <= avs_writedata;
avs_byteenable_r <= avs_byteenable;
avs_addr_r <= {avs_address, {log2(AVS_BYTE_WIDTH){1'b0}}};
avs_skid <= avs_writedata_r;
avs_byte_skid <= avs_byteenable_r;
avs_addr_skid <= avs_addr_r;
end
// Count number of oustanding avm write transfers
reg [2:0] avm_wr_txfers;
// decrement by 1 for every avm transfer
wire wr_txfers_dec = avm_write & ~avm_waitrequest;
// increment by 2 for every avs transfer
wire wr_txfers_inc2 = avs_write & ~avs_waitrequest & avs_clk_ph;
assign avm_nxt_wr_txfers = avm_wr_txfers + (wr_txfers_inc2 ? 3'b010 : 3'b0)
- (wr_txfers_dec ? 3'b001 : 3'b0);
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_wr_txfers <= 3'b0;
else
avm_wr_txfers <= avm_nxt_wr_txfers;
//---------------------------------------------------------------------------
// Read path
//---------------------------------------------------------------------------
reg avs_readdatavalid;
reg [AVS_DATA_WIDTH-1:0] avs_readdata;
// Count number of oustanding avm read requests
reg [2:0] avm_rd_txfers;
// decrement for every avm transfer
wire rd_txfers_dec = avm_read & ~avm_waitrequest;
// increment by 2 for every avs transfer
wire rd_txfers_inc2 = avs_read & ~avs_waitrequest & avs_clk_ph;
generate
if (ENABLE_BURSTING_MASTER)
// decrement by 2 for each avm read if bursting is enabled
assign avm_nxt_rd_txfers = avm_rd_txfers + (rd_txfers_inc2 ? 3'b010 : 3'b0)
- (rd_txfers_dec ? 3'b010 : 3'b0);
else
assign avm_nxt_rd_txfers = avm_rd_txfers + (rd_txfers_inc2 ? 3'b010 : 3'b0)
- (rd_txfers_dec ? 3'b001 : 3'b0);
endgenerate
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_rd_txfers <= 3'b0;
else
avm_rd_txfers <= avm_nxt_rd_txfers;
// Count number of oustanding avm read data transfers
reg [2:0] avm_rd_data_txfers;
// decrement by 2 for every avs transfer
wire rd_data_txfers_dec2 = avs_readdatavalid & avs_clk_ph;
// increment by 1 for every avm transfer
wire rd_data_txfers_inc = avm_readdatavalid;
wire [2:0] avm_nxt_rd_data_txfers = avm_rd_data_txfers + (rd_data_txfers_inc ? 3'b001 : 3'b0)
- (rd_data_txfers_dec2 ? 3'b010 : 3'b0);
assign avm_nxt_txfers = avm_nxt_rd_txfers + avm_nxt_wr_txfers;
wire [2:0] avm_txfers = avm_rd_txfers + avm_wr_txfers;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_rd_data_txfers <= 3'b0;
else
avm_rd_data_txfers <= avm_nxt_rd_data_txfers;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_readdatavalid <= 1'b0;
else
avs_readdatavalid <= (avm_nxt_rd_data_txfers >= 3'b010);
reg [AVS_DATA_WIDTH-1:0] avm_readdata_r;
reg [AVS_DATA_WIDTH-1:0] avm_skid;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_readdata_r <= {AVS_DATA_WIDTH{1'b0}};
avm_skid <= {AVS_DATA_WIDTH{1'b0}};
end
else if (avm_readdatavalid & avm_nxt_rd_data_txfers[0])
begin
avm_readdata_r[AVM_DATA_WIDTH-1:0] <= avm_readdata;
avm_skid <= avm_readdata_r;
end
else if (avm_readdatavalid)
begin
avm_readdata_r[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH] <= avm_readdata;
end
always @(avm_readdata_r, avm_rd_data_txfers, avm_skid)
case (avm_rd_data_txfers)
3'd4, 3'd3: avs_readdata = avm_skid;
default: avs_readdata = avm_readdata_r;
endcase
//---------------------------------------------------------------------------
// AVM control
//---------------------------------------------------------------------------
reg [5:0] avm_state;
localparam AVM_IDLE = 6'b000001,
AVM_WRITE1 = 6'b000010,
AVM_READ1 = 6'b000100;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_write <= 1'b0;
avm_read <= 1'b0;
avm_state <= AVM_IDLE;
end
else
case (avm_state)
AVM_IDLE:
if (|(avm_nxt_wr_txfers))
begin
avm_write <= 1'b1;
avm_state <= AVM_WRITE1;
end
else if (|(avm_nxt_rd_txfers))
begin
avm_read <= 1'b1;
avm_state <= AVM_READ1;
end
AVM_WRITE1:
if (~(|avm_nxt_wr_txfers) & ~(|avm_nxt_rd_txfers) & ~avm_waitrequest)
begin
avm_write <= 1'b0;
avm_state <= AVM_IDLE;
end
else if (~(|avm_nxt_wr_txfers) & (|avm_nxt_rd_txfers) & ~avm_waitrequest)
begin
avm_write <= 1'b0;
avm_read <= 1'b1;
avm_state <= AVM_READ1;
end
AVM_READ1:
if (~(|avm_nxt_rd_txfers) & ~(|avm_nxt_wr_txfers) & ~avm_waitrequest)
begin
avm_read <= 1'b0;
avm_state <= AVM_IDLE;
end
else if (~(|avm_nxt_rd_txfers) & (|avm_nxt_wr_txfers) & ~avm_waitrequest)
begin
avm_read <= 1'b0;
avm_write <= 1'b1;
avm_state <= AVM_WRITE1;
end
default:
avm_state <= AVM_IDLE;
endcase
// Write data is selected from the buffers depending on how many transfers
// are outstanding
always @(avs_writedata_r, avs_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_writedata <= avs_skid[AVM_DATA_WIDTH-1:0];
3'd3: avm_writedata <= avs_skid[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH];
3'd2: avm_writedata <= avs_writedata_r[AVM_DATA_WIDTH-1:0];
3'd1: avm_writedata <= avs_writedata_r[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH];
default: avm_writedata <= {AVM_DATA_WIDTH{1'b0}};
endcase
// Similarly for byte enables
always @(avm_state, avs_byteenable_r, avs_byte_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_byteenable <= avs_byte_skid[AVM_BYTE_WIDTH-1:0];
3'd3: avm_byteenable <= avs_byte_skid[AVS_BYTE_WIDTH-1:AVM_BYTE_WIDTH];
3'd2: avm_byteenable <= avs_byteenable_r[AVM_BYTE_WIDTH-1:0];
3'd1: avm_byteenable <= avs_byteenable_r[AVS_BYTE_WIDTH-1:AVM_BYTE_WIDTH];
default: avm_byteenable <= {AVM_BYTE_WIDTH{1'b0}};
endcase
// And address
always @(avm_state, avs_addr_r, avs_addr_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_address <= avs_addr_skid;
3'd3: avm_address <= avs_addr_skid | avm_addr_offset;
3'd2: avm_address <= avs_addr_r;
3'd1: avm_address <= avs_addr_r | avm_addr_offset;
default: avm_address <= {AVM_ADDR_WIDTH{1'b0}};
endcase
endmodule |
module alt_ddrx_decoder #
( parameter
INPUT_DATA_WIDTH = 72,
OUTPUT_DATA_WIDTH = 64
)
(
ctl_clk,
input_data,
err_corrected,
err_detected,
err_fatal,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
output err_corrected;
output err_detected;
output err_fatal;
wire [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire err_corrected;
wire err_detected;
wire err_fatal;
generate
if (INPUT_DATA_WIDTH == 40)
begin
// encoder only have 32/29 combination
alt_ddrx_decoder_40 decoder_40_inst
(
.clock (ctl_clk),
.data (input_data [INPUT_DATA_WIDTH - 2 : 0]),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
else if (INPUT_DATA_WIDTH == 72)
begin
alt_ddrx_decoder_72 decoder_72_inst
(
.clock (ctl_clk),
.data (input_data),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
endgenerate
endmodule |
module alt_ddrx_cache #
( parameter
// controller settings
MEM_IF_CHIP_BITS = 2,
MEM_IF_CS_WIDTH = 4,
MEM_IF_ROW_WIDTH = 16, // max supported row bits
MEM_IF_BA_WIDTH = 3, // max supported bank bits
MEM_TYPE = "DDR3",
DWIDTH_RATIO = 2, // 2 - fullrate, 4 - halfrate
CLOSE_PAGE_POLICY = 1,
CTL_LOOK_AHEAD_DEPTH = 4,
CTL_CMD_QUEUE_DEPTH = 8
)
(
ctl_clk,
ctl_reset_n,
// state machine inputs
fetch,
// ecc inputs
ecc_fetch_error_addr,
// command queue inputs
cmd_is_valid,
// command inputs
in_cs_all_banks_closed,
in_cs_can_precharge_all,
in_cs_can_refresh,
in_cs_can_self_refresh,
in_cs_can_power_down,
in_cs_can_exit_power_saving_mode,
in_cs_zq_cal_req,
in_cs_power_down_req,
in_cs_refresh_req,
in_cmd_bank_is_open,
in_cmd_row_is_open,
in_cmd_can_write,
in_cmd_can_read,
in_cmd_can_activate,
in_cmd_can_precharge,
// command outputs
out_cs_all_banks_closed,
out_cs_can_precharge_all,
out_cs_can_refresh,
out_cs_can_self_refresh,
out_cs_can_power_down,
out_cs_can_exit_power_saving_mode,
out_cs_zq_cal_req,
out_cs_power_down_req,
out_cs_refresh_req,
out_cmd_bank_is_open,
out_cmd_row_is_open,
out_cmd_can_write,
out_cmd_can_read,
out_cmd_can_activate,
out_cmd_can_precharge,
out_cmd_info_valid
);
input ctl_clk;
input ctl_reset_n;
// state machine inputs
input fetch;
// ecc inputs
input ecc_fetch_error_addr;
// command queue inputs
input [CTL_CMD_QUEUE_DEPTH : 0] cmd_is_valid;
// command inputs
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_all_banks_closed;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_precharge_all;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_refresh;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_self_refresh;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_power_down;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_can_exit_power_saving_mode;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_zq_cal_req;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_power_down_req;
input [MEM_IF_CS_WIDTH - 1 : 0] in_cs_refresh_req;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_bank_is_open;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_row_is_open;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_write;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_read;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_activate;
input [CTL_LOOK_AHEAD_DEPTH : 0] in_cmd_can_precharge;
// command outputs
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_all_banks_closed;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_precharge_all;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_refresh;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_self_refresh;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_power_down;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_exit_power_saving_mode;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_zq_cal_req;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_power_down_req;
output [MEM_IF_CS_WIDTH - 1 : 0] out_cs_refresh_req;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_bank_is_open;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_row_is_open;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_write;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_read;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_activate;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_precharge;
output [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_info_valid;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Registers & Wires
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Cache Logic
------------------------------------------------------------------------------*/
reg cache;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_bank_is_open;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_row_is_open;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_write;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_read;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_activate;
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_can_precharge;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_all_banks_closed;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_precharge_all;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_refresh;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_self_refresh;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_power_down;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_can_exit_power_saving_mode;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_zq_cal_req;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_power_down_req;
wire [MEM_IF_CS_WIDTH - 1 : 0] out_cs_refresh_req;
/*------------------------------------------------------------------------------
Command Valid Logic
------------------------------------------------------------------------------*/
reg [CTL_LOOK_AHEAD_DEPTH : 0] out_cmd_info_valid;
reg [CTL_LOOK_AHEAD_DEPTH : 0] int_cmd_info_valid;
reg int_current_info_valid_r1;
reg fetch_r1;
reg ecc_fetch_error_addr_r1;
/*------------------------------------------------------------------------------
Assignment
------------------------------------------------------------------------------*/
// no changes made to these signals
assign out_cs_all_banks_closed = in_cs_all_banks_closed;
assign out_cs_can_precharge_all = in_cs_can_precharge_all;
assign out_cs_can_refresh = in_cs_can_refresh;
assign out_cs_can_self_refresh = in_cs_can_self_refresh;
assign out_cs_can_power_down = in_cs_can_power_down;
assign out_cs_can_exit_power_saving_mode = in_cs_can_exit_power_saving_mode;
assign out_cs_zq_cal_req = in_cs_zq_cal_req;
assign out_cs_power_down_req = in_cs_power_down_req;
assign out_cs_refresh_req = in_cs_refresh_req;
/*------------------------------------------------------------------------------
[END] Registers & Wires
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Cache Logic
------------------------------------------------------------------------------*/
// Determine when to cache
always @ (*)
begin
if (fetch)
cache = 1'b1;
else
cache = 1'b0;
end
/*------------------------------------------------------------------------------
Cache Logic
------------------------------------------------------------------------------*/
always @ (*)
begin
if (cache)
begin
out_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_write [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_write [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_read [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_read [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = int_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_bank_is_open [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_write [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_read [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_activate [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_can_precharge [CTL_LOOK_AHEAD_DEPTH] = 0;
out_cmd_info_valid [CTL_LOOK_AHEAD_DEPTH] = 0;
end
else
begin
out_cmd_bank_is_open = in_cmd_bank_is_open;
out_cmd_can_write = in_cmd_can_write;
out_cmd_can_read = in_cmd_can_read;
out_cmd_can_activate = in_cmd_can_activate;
out_cmd_can_precharge = in_cmd_can_precharge;
out_cmd_info_valid = int_cmd_info_valid;
end
end
always @ (*)
begin
if (cache || fetch_r1)
begin
out_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0] = in_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH : 1];
out_cmd_row_is_open [CTL_LOOK_AHEAD_DEPTH] = 0;
end
else
begin
out_cmd_row_is_open = in_cmd_row_is_open;
end
end
/*------------------------------------------------------------------------------
[END] Cache Logic
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Command Valid Logic
------------------------------------------------------------------------------*/
// register fetch signals
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
fetch_r1 <= 1'b0;
ecc_fetch_error_addr_r1 <= 1'b0;
end
else
begin
fetch_r1 <= fetch;
ecc_fetch_error_addr_r1 <= ecc_fetch_error_addr;
end
end
// Command valid logic
generate
genvar z_lookahead;
for (z_lookahead = 1; z_lookahead < CTL_LOOK_AHEAD_DEPTH + 1;z_lookahead = z_lookahead + 1)
begin : cmd_valid_logic_per_lookahead
always @ (*)
begin
int_cmd_info_valid [z_lookahead] = cmd_is_valid [z_lookahead];
end
end
endgenerate
// Current valid logic
always @ (*)
begin
if (fetch)
int_cmd_info_valid [0] = 1'b0;
else if (fetch_r1)
int_cmd_info_valid [0] = 1'b1;
//we will need to deassert current info valid signal for 2 clock cycle so that state machine will not capture the wrong information
else if (ecc_fetch_error_addr)
int_cmd_info_valid [0] = 1'b0;
else if (ecc_fetch_error_addr_r1)
int_cmd_info_valid [0] = 1'b1;
else
int_cmd_info_valid [0] = int_current_info_valid_r1;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_current_info_valid_r1 <= 1'b0;
else
int_current_info_valid_r1 <= int_cmd_info_valid [0];
end
/*------------------------------------------------------------------------------
[END] Command Valid Logic
------------------------------------------------------------------------------*/
endmodule |
module alt_ddrx_addr_cmd
# (parameter
// memory interface bus sizing parameters
MEM_IF_CS_WIDTH = 1,
MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
MEM_IF_ADDR_WIDTH = 13, // max supported address bits, must be >= row bits
MEM_IF_ROW_WIDTH = 13, // max supported row bits
MEM_IF_COL_WIDTH = 10, // max supported column bits
MEM_IF_BA_WIDTH = 3, // max supported bank bits
MEM_TYPE = "DDR2",
MEM_IF_PCHADDR_BIT = 10,
CTL_OUTPUT_REGD = 0,
DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
// state machine command inputs
do_write,
do_read,
do_auto_precharge,
do_burst_chop,
do_activate,
do_precharge,
do_refresh,
do_power_down,
do_self_rfsh,
do_lmr,
do_precharge_all,
do_zqcal,
// address information
to_chip, // active high input (one hot)
to_bank_addr,
to_row_addr,
to_col_addr,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
// state machine command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_burst_chop;
input do_activate;
input do_precharge;
input do_refresh;
input do_power_down;
input do_self_rfsh;
input do_lmr;
input do_precharge_all;
input do_zqcal;
input [MEM_IF_CS_WIDTH-1:0] to_chip;
input [MEM_IF_BA_WIDTH-1:0] to_bank_addr;
input [MEM_IF_ROW_WIDTH-1:0] to_row_addr;
input [MEM_IF_COL_WIDTH-1:0] to_col_addr;
//output
output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_activate;
wire do_precharge;
wire do_refresh;
wire do_power_down;
wire do_self_rfsh;
wire do_lmr;
wire do_auto_precharge;
wire do_precharge_all;
wire [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
wire [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
wire [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
wire [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
wire [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(MEM_IF_CS_WIDTH) - 1:0] int_cs_n;
reg int_ras_n;
reg int_cas_n;
reg int_we_n;
reg [(MEM_IF_BA_WIDTH) - 1:0] int_ba;
reg [(MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(MEM_IF_CS_WIDTH) - 1:0] combi_cs_n;
reg combi_ras_n;
reg combi_cas_n;
reg combi_we_n;
reg [(MEM_IF_BA_WIDTH) - 1:0] combi_ba;
reg [(MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
wire [(MEM_IF_ADDR_WIDTH) - 1:0] int_row;
wire [(MEM_IF_ADDR_WIDTH) - 1:0] temp_col;
wire [(MEM_IF_ADDR_WIDTH) - 1:0] int_col;
reg [MEM_IF_CS_WIDTH-1:0] chip_in_self_rfsh;
assign int_row = {{(MEM_IF_ADDR_WIDTH - MEM_IF_ROW_WIDTH){1'b0}},to_row_addr};
assign temp_col = {{(MEM_IF_ADDR_WIDTH - MEM_IF_COL_WIDTH){1'b0}},to_col_addr};
assign afi_rst_n = {(DWIDTH_RATIO/2){1'b1}};
generate
if (MEM_TYPE == "DDR3" && MEM_IF_ADDR_WIDTH-3 < 11)
assign int_col = {~do_burst_chop,temp_col[10:MEM_IF_PCHADDR_BIT],do_auto_precharge,temp_col[MEM_IF_PCHADDR_BIT-1:0]};
else if (MEM_TYPE == "DDR3")
assign int_col = {temp_col[MEM_IF_ADDR_WIDTH-3:11],~do_burst_chop,temp_col[10:MEM_IF_PCHADDR_BIT],do_auto_precharge,temp_col[MEM_IF_PCHADDR_BIT-1:0]};
else if (MEM_IF_ADDR_WIDTH-2 < MEM_IF_PCHADDR_BIT)
assign int_col = {do_auto_precharge,temp_col[MEM_IF_PCHADDR_BIT-1:0]};
else
assign int_col = {temp_col[MEM_IF_ADDR_WIDTH-2:MEM_IF_PCHADDR_BIT],do_auto_precharge,temp_col[MEM_IF_PCHADDR_BIT-1:0]};
endgenerate
generate
if (DWIDTH_RATIO == 2)
begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_ras_n = int_ras_n;
assign afi_cas_n = int_cas_n;
assign afi_we_n = int_we_n;
assign afi_ba = int_ba;
assign afi_addr = int_addr;
end
else
begin
assign afi_cke = {int_cke,int_cke_r};
assign afi_cs_n = {int_cs_n,{MEM_IF_CS_WIDTH{1'b1}}};
assign afi_ras_n = {int_ras_n,int_ras_n};
assign afi_cas_n = {int_cas_n,int_cas_n};
assign afi_we_n = {int_we_n,int_we_n};
assign afi_ba = {int_ba,int_ba};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_cke_r <= {(MEM_IF_CKE_WIDTH){1'b0}};
else
int_cke_r <= int_cke;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
chip_in_self_rfsh <= {(MEM_IF_CS_WIDTH){1'b0}};
else
if (do_self_rfsh)
chip_in_self_rfsh <= to_chip;
else
chip_in_self_rfsh <= {(MEM_IF_CS_WIDTH){1'b0}};
end
generate
if (CTL_OUTPUT_REGD == 1)
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cke <= {(MEM_IF_CKE_WIDTH){1'b1}};
int_cs_n <= {(MEM_IF_CS_WIDTH){1'b1}};
int_ras_n <= 1'b1;
int_cas_n <= 1'b1;
int_we_n <= 1'b1;
int_ba <= {(MEM_IF_BA_WIDTH){1'b0}};
int_addr <= {(MEM_IF_ADDR_WIDTH){1'b0}};
end
else
begin
int_cke <= combi_cke;
int_cs_n <= combi_cs_n;
int_ras_n <= combi_ras_n;
int_cas_n <= combi_cas_n;
int_we_n <= combi_we_n;
int_ba <= combi_ba;
int_addr <= combi_addr;
end
end
end
else // no register
begin
always @(*)
begin
int_cke <= combi_cke;
int_cs_n <= combi_cs_n;
int_ras_n <= combi_ras_n;
int_cas_n <= combi_cas_n;
int_we_n <= combi_we_n;
int_ba <= combi_ba;
int_addr <= combi_addr;
end
end
endgenerate
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(MEM_IF_CS_WIDTH){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(MEM_IF_ADDR_WIDTH){1'b0}};
if (do_refresh)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
end
if (do_precharge_all)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = to_bank_addr;
combi_addr[10]= 1'b1;
end
if (do_activate)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = to_bank_addr;
combi_addr = int_row;
end
if (do_precharge)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b0;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_ba = to_bank_addr;
end
if (do_write)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b0;
combi_ba = to_bank_addr;
combi_addr = int_col;
end
if (do_read)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
combi_ba = to_bank_addr;
combi_addr = int_col;
end
if (do_power_down)
begin
combi_cke = ~to_chip;
combi_cs_n = {(MEM_IF_CS_WIDTH){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
end
if (do_self_rfsh)
begin
combi_cke = ~to_chip;
combi_cs_n = (~to_chip | chip_in_self_rfsh);
combi_ras_n = 1'b0;
combi_cas_n = 1'b0;
combi_we_n = 1'b1;
end
if (do_zqcal)
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b0;
combi_addr[10]= 1'b0; // short ZQcal
end
end
else
begin
combi_cke = {(MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(MEM_IF_CS_WIDTH){1'b1}};
combi_ras_n = 1'b1;
combi_cas_n = 1'b1;
combi_we_n = 1'b1;
combi_ba = {(MEM_IF_BA_WIDTH){1'b0}};
combi_addr = {(MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule |
module ddr2_ex_lfsr8 (
clk, reset_n, enable, pause, load, data, ldata);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output[8 - 1:0] data;
wire[8 - 1:0] data;
input[8 - 1:0] ldata;
reg[8 - 1:0] lfsr_data;
assign data = lfsr_data ;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
// Reset - asynchronously reset to seed value
lfsr_data <= seed[7:0] ;
end
else
begin
if (!enable)
begin
lfsr_data <= seed[7:0];
end
else
begin
if (load)
begin
lfsr_data <= ldata ;
end
else
begin
// Registered mode - synchronous propagation of signals
if (!pause)
begin
lfsr_data[0] <= lfsr_data[7] ;
lfsr_data[1] <= lfsr_data[0] ;
lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;
lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;
lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;
lfsr_data[5] <= lfsr_data[4] ;
lfsr_data[6] <= lfsr_data[5] ;
lfsr_data[7] <= lfsr_data[6] ;
end
end
end
end
end
endmodule |
module alt_ddrx_encoder #
( parameter
INPUT_DATA_WIDTH = 64,
OUTPUT_DATA_WIDTH = 72
)
(
ctl_clk,
input_data,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
generate
if (OUTPUT_DATA_WIDTH == 40)
begin
alt_ddrx_encoder_40 encoder_40_inst
(
.clock (ctl_clk),
.data (input_data),
.q (output_data [OUTPUT_DATA_WIDTH - 2 : 0])
);
// encoder only have 32/29 combination, will have to hardcode MSB to '0'
assign output_data [OUTPUT_DATA_WIDTH - 1] = 1'b0;
end
else if (OUTPUT_DATA_WIDTH == 72)
begin
alt_ddrx_encoder_72 encoder_72_inst
(
.clock (ctl_clk),
.data (input_data),
.q (output_data)
);
end
endgenerate
endmodule |
module alt_ddrx_cmd_gen
# (parameter
MEM_IF_CSR_COL_WIDTH = 4,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 2,
MEM_IF_CSR_CS_WIDTH = 2,
MEM_IF_ROW_WIDTH = 16,
MEM_IF_COL_WIDTH = 12,
MEM_IF_BA_WIDTH = 3,
MEM_IF_CHIP_BITS = 2,
LOCAL_ADDR_WIDTH = 33,
INTERNAL_SIZE_WIDTH = 6,
DWIDTH_RATIO = 4,
MEMORY_BURSTLENGTH = 8,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
//local input
local_read_req,
local_write_req,
processed_write_req,
local_size,
local_autopch_req,
local_addr,
local_multicast,
//input from CSR
addr_order,
col_width_from_csr,
row_width_from_csr,
bank_width_from_csr,
cs_width_from_csr,
//misc
ready_out,
ready_in,
//output
read_req,
write_req,
size,
autopch_req,
cs_addr,
bank_addr,
row_addr,
col_addr,
multicast
);
localparam MAX_COL = MEM_IF_COL_WIDTH;
localparam MAX_ROW = MEM_IF_ROW_WIDTH;
localparam MAX_BANK = MEM_IF_BA_WIDTH;
localparam MAX_CS = MEM_IF_CHIP_BITS;
input ctl_clk;
input ctl_reset_n;
input local_read_req;
input local_write_req;
input processed_write_req;
input [INTERNAL_SIZE_WIDTH-1:0] local_size;
input local_autopch_req;
input [LOCAL_ADDR_WIDTH-1:0] local_addr;
input local_multicast;
input [1:0] addr_order;
input [MEM_IF_CSR_COL_WIDTH-1:0] col_width_from_csr;
input [MEM_IF_CSR_ROW_WIDTH-1:0] row_width_from_csr;
input [MEM_IF_CSR_BANK_WIDTH-1:0] bank_width_from_csr;
input [MEM_IF_CSR_CS_WIDTH-1:0] cs_width_from_csr;
output ready_out;
input ready_in;
output read_req;
output write_req;
output [1:0] size;
output autopch_req;
output [MEM_IF_CHIP_BITS-1:0] cs_addr;
output [MEM_IF_BA_WIDTH-1:0] bank_addr;
output [MEM_IF_ROW_WIDTH-1:0] row_addr;
output [MEM_IF_COL_WIDTH-1:0] col_addr;
output multicast;
integer n;
integer j;
integer k;
integer m;
reg [MEM_IF_CHIP_BITS-1:0] cs_addr;
reg [MEM_IF_BA_WIDTH-1:0] bank_addr;
reg [MEM_IF_ROW_WIDTH-1:0] row_addr;
reg [MEM_IF_COL_WIDTH-1:0] col_addr;
reg [MEM_IF_CHIP_BITS-1:0] int_cs_addr;
reg [MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [MEM_IF_COL_WIDTH-1:0] int_col_addr;
reg read_req;
reg write_req;
reg [1:0] size;
reg autopch_req;
reg multicast;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg [INTERNAL_SIZE_WIDTH-1:0] buf_size;
reg [MEM_IF_CHIP_BITS-1:0] buf_cs_addr;
reg [MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [INTERNAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [MEM_IF_CHIP_BITS-1:0] incrmntd_cs_addr;
reg [MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
wire [MEM_IF_CHIP_BITS-1:0] max_chip_from_csr;
wire [MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
wire [MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
wire [MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
wire unaligned_burst;
wire require_gen;
reg hold_ready;
reg registered;
reg generating;
reg pass_write;
//======================= local_addr remapping ===========================
//derive column address from local_addr
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - DWIDTH_RATIO/2 - 1 : 0] = local_addr[MIN_COL - DWIDTH_RATIO/2 - 1 : 0];
for (n=MIN_COL - DWIDTH_RATIO/2; n<MAX_COL; n=n+1'b1) begin
if(n < col_width_from_csr - DWIDTH_RATIO/2) begin // bit of col_addr can be configured in CSR using col_width_from_csr
int_col_addr[n] = local_addr[n];
end
else begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = (int_col_addr << (log2 (DWIDTH_RATIO)));
end
//derive row address from local_addr
always @(*)
begin : Row_addr_loop
for (j=0; j<MIN_ROW; j=j+1'b1) begin //The purpose of using this for-loop is to get rid of "if(j < row_width_from_csr) begin" which causes multiplexers
if(addr_order == 2'd1) // local_addr can arrange in 2 patterns depending on addr_order (i) cs, bank, row, col (ii) cs, row, bank, col
int_row_addr[j] = local_addr[j + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 1
else // addr_order == 2'd0 or others
int_row_addr[j] = local_addr[j + bank_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 2
end
for (j=MIN_ROW; j<MAX_ROW; j=j+1'b1) begin
if(j < row_width_from_csr) begin // bit of row_addr can be configured in CSR using row_width_from_csr
if(addr_order == 2'd1)
int_row_addr[j] = local_addr[j + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 1
else // addr_order == 2'd0 or others
int_row_addr[j] = local_addr[j + bank_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 2
end
else begin
int_row_addr[j] = 1'b0;
end
end
end
always @(*)
begin : Bank_addr_loop
for (k=0; k<MIN_BANK; k=k+1'b1) begin //The purpose of using this for-loop is to get rid of "if(k < bank_width_from_csr) begin" which causes multiplexers
if(addr_order == 2'd1) // local_addr can arrange in 2 patterns depending on addr_order (i) cs, bank, row, col (ii) cs, row, bank, col
int_bank_addr[k] = local_addr[k + row_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 1
else // addr_order == 2'd0 or others
int_bank_addr[k] = local_addr[k + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 2
end
for (k=MIN_BANK; k<MAX_BANK; k=k+1'b1) begin
if(k < bank_width_from_csr) begin // bit of bank_addr can be configured in CSR using bank_width_from_csr
if(addr_order == 2'd1)
int_bank_addr[k] = local_addr[k + row_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 1
else // addr_order == 2'd0 or others
int_bank_addr[k] = local_addr[k + col_width_from_csr - DWIDTH_RATIO/2]; //address order pattern 2
end
else begin
int_bank_addr[k] = 1'b0;
end
end
end
always @(*)
begin
m=0;
if (cs_width_from_csr > 1'b0) begin //if cs_width_from_csr =< 1'b1, local_addr doesn't have cs_addr bit
for (m=0; m<MIN_CS; m=m+1'b1) begin //The purpose of using this for-loop is to get rid of "if(m < cs_width_from_csr) begin" which causes multiplexers
int_cs_addr[m] = local_addr[m + bank_width_from_csr + row_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1) begin
if(m < cs_width_from_csr) begin // bit of cs_addr can be configured in CSR using cs_width_from_csr
int_cs_addr[m] = local_addr[m + bank_width_from_csr + row_width_from_csr + col_width_from_csr - DWIDTH_RATIO/2];
end
else begin
int_cs_addr[m] = 1'b0;
end
end
end
else begin
int_cs_addr = {MEM_IF_CHIP_BITS{1'b0}}; //if MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
end
end
//===================== end of local_addr remapping =========================
// csr wiring
assign max_chip_from_csr = (2**cs_width_from_csr) - 1'b1;
assign max_bank_from_csr = (2**bank_width_from_csr) - 1'b1;
assign max_row_from_csr = (2**row_width_from_csr) - 1'b1;
assign max_col_from_csr = (2**col_width_from_csr) - 1'b1;
assign ready_out = ready_in & ~hold_ready;
assign copy = ready_in & (local_read_req | processed_write_req);
assign unaligned_burst = (DWIDTH_RATIO == 2 && int_col_addr[1]) || (DWIDTH_RATIO == 4 && int_col_addr[2]);
assign require_gen = local_size > 2 | (local_size > 1 & unaligned_burst);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
hold_ready <= 0;
else
begin
if (copy && require_gen)
hold_ready <= 1;
else if (buf_read_req && buf_size > 4)
hold_ready <= 1;
else if ((generating && buf_read_req && ready_in) || (buf_write_req))
hold_ready <= 0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
registered <= 0;
else
begin
if (copy && require_gen)
registered <= 1;
else
registered <= 0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
generating <= 0;
else
begin
if (registered)
generating <= 1;
else if (generating && buf_size > 4)
generating <= 1;
else if ((buf_read_req && ready_in) || (local_write_req && ready_in && pass_write))
generating <= 0;
end
end
always @(*)
begin
if (INTERNAL_SIZE_WIDTH > 1)
begin
if (!generating)
if (local_size > 1 && !unaligned_burst)
size <= 2;
else
size <= 1;
else
if (decrmntd_size > 1)
size <= 2;
else
size <= 1;
end
else
size <= 1;
end
always @(*)
if (!generating) // not generating so take direct input from avalon if
begin
read_req <= local_read_req;
write_req <= processed_write_req;
autopch_req <= local_autopch_req;
multicast <= local_multicast;
cs_addr <= int_cs_addr;
bank_addr <= int_bank_addr;
row_addr <= int_row_addr;
col_addr <= int_col_addr;
end
else // generating cmd so process buffer content
begin
read_req <= buf_read_req & ready_in;
write_req <= local_write_req & ready_in & pass_write;
autopch_req <= buf_autopch_req;
multicast <= buf_multicast;
cs_addr <= incrmntd_cs_addr;
bank_addr <= incrmntd_bank_addr;
row_addr <= incrmntd_row_addr;
if (DWIDTH_RATIO == 2)
col_addr <= {incrmntd_col_addr[MEM_IF_COL_WIDTH-1:2],2'b00};
else
col_addr <= {incrmntd_col_addr[MEM_IF_COL_WIDTH-1:3],3'b000};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
pass_write <= 0;
else
begin
if (copy && require_gen && !unaligned_burst)
pass_write <= 0;
else if (copy && require_gen && unaligned_burst)
pass_write <= 1;
else if (local_write_req && !registered)
pass_write <= ~pass_write;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
end
else
if (copy)
begin
buf_read_req <= local_read_req;
buf_write_req <= local_write_req;
buf_autopch_req <= local_autopch_req;
buf_multicast <= local_multicast;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
buf_size <= 0;
else
begin
if (copy)
buf_size <= local_size + unaligned_burst;
else if (!registered && buf_read_req && buf_size > 2 && ready_in)
buf_size <= buf_size - 2'b10;
else if (!registered && local_write_req && buf_size > 2 && ready_in && pass_write)
buf_size <= buf_size - 2'b10;
end
end
always @(*)
decrmntd_size <= buf_size - 2'b10;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (buf_read_req && generating && ready_in) || (local_write_req && generating && ready_in && pass_write))
if ((MEMORY_BURSTLENGTH == 8 && buf_col_addr[MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[MEM_IF_COL_WIDTH-1:3]) || (MEMORY_BURSTLENGTH == 4 && buf_col_addr[MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[MEM_IF_COL_WIDTH-1:2]))
begin
if (MEMORY_BURSTLENGTH == 8)
buf_col_addr[MEM_IF_COL_WIDTH-1:3] <= 0;
else
buf_col_addr[MEM_IF_COL_WIDTH-1:2] <= 0;
if (addr_order == 1) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
begin
if (MEMORY_BURSTLENGTH == 8)
buf_col_addr <= buf_col_addr + 4'b1000;
else
buf_col_addr <= buf_col_addr + 3'b100;
end
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
function integer log2; //constant function
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule |
module alt_ddrx_ddr3_odt_gen
# (parameter
DWIDTH_RATIO = 2,
TCL_BUS_WIDTH = 4,
CAS_WR_LAT_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [CAS_WR_LAT_BUS_WIDTH-1:0] mem_cas_wr_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
wire do_write;
wire int_do_read;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
reg int_odt_l_int;
reg int_odt_l_int_r;
wire int_odt_l;
wire int_odt_h;
reg [2:0] doing_write_count;
reg [2:0] doing_read_count;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
assign diff_unreg = mem_tcl - mem_cas_wr_lat;
assign int_do_read = (diff > 1) ? do_read_r : do_read;
generate
if (DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = int_odt_l_int;
assign int_odt_l = int_odt_l_int;
end
else // half rate
begin
assign int_odt_h = int_odt_l_int | do_write | (int_do_read & ~|diff);
assign int_odt_l = int_odt_l_int | int_odt_l_int_r;
end
endgenerate
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
diff <= 0;
else
diff <= diff_unreg;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_r <= 0;
else
do_read_r <= do_read;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (do_write)
doing_write_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_write_count == 4) || (DWIDTH_RATIO != 2 && doing_write_count == 1))
doing_write_count <= 0;
else if (doing_write_count > 0)
doing_write_count <= doing_write_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read_count <= 0;
else
if (int_do_read)
doing_read_count <= 1;
else if ((DWIDTH_RATIO == 2 && doing_read_count == 4) || (DWIDTH_RATIO != 2 && doing_read_count == 1))
doing_read_count <= 0;
else if (doing_read_count > 0)
doing_read_count <= doing_read_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_odt_l_int <= 1'b0;
else
if (do_write || int_do_read)
int_odt_l_int <= 1'b1;
else if (doing_write_count > 0 || doing_read_count > 0)
int_odt_l_int <= 1'b1;
else
int_odt_l_int <= 1'b0;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_odt_l_int_r <= 1'b0;
else
int_odt_l_int_r <= int_odt_l_int;
end
endmodule |
module alt_ddrx_ddr2_odt_gen
# (parameter
DWIDTH_RATIO = 2,
MEMORY_BURSTLENGTH = 8,
ADD_LAT_BUS_WIDTH = 3,
CTL_OUTPUT_REGD = 0,
TCL_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_add_lat,
do_write,
do_read,
int_odt_l,
int_odt_h
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [ADD_LAT_BUS_WIDTH-1:0] mem_add_lat;
input do_write;
input do_read;
output int_odt_l;
output int_odt_h;
localparam TCL_PIPE_LENGTH = 2**TCL_BUS_WIDTH; // okay to size this to 4 since max latency in DDR2 is 7+6=13
localparam TAOND = 2;
localparam TAOFD = 2.5;
wire do_write;
wire do_read;
wire [1:0] regd_output;
wire [TCL_BUS_WIDTH-1:0] int_tcwl_unreg;
reg [TCL_BUS_WIDTH-1:0] int_tcwl;
wire int_odt_l;
wire int_odt_h;
reg reg_odt_l;
reg reg_odt_h;
reg combi_odt_l;
reg combi_odt_h;
reg [1:0] offset_code;
reg start_odt_write;
reg start_odt_read;
reg [TCL_PIPE_LENGTH-1:0] do_write_pipe;
reg [TCL_PIPE_LENGTH-1:0] do_read_pipe;
assign int_odt_l = combi_odt_l | reg_odt_l;
assign int_odt_h = combi_odt_h | reg_odt_h;
assign regd_output = (DWIDTH_RATIO == 2) ? (CTL_OUTPUT_REGD ? 2'd1 : 2'd0) : (CTL_OUTPUT_REGD ? 2'd2 : 2'd0);
assign int_tcwl_unreg = (mem_tcl + mem_add_lat + regd_output - 1'b1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_tcwl <= 0;
else
int_tcwl <= int_tcwl_unreg;
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[int_tcwl - 4];
end
else // half rate
begin
if (int_tcwl < 4)
start_odt_write <= do_write;
else
start_odt_write <= do_write_pipe[(int_tcwl - 4)/2];
end
end
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[int_tcwl - 3];
end
else // half rate
begin
if (int_tcwl < 3)
start_odt_read <= do_read;
else
start_odt_read <= do_read_pipe[(int_tcwl - 3)/2];
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_write_pipe <= 0;
else
if (do_write)
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],do_write};
else
do_write_pipe <= {do_write_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_read_pipe <= 0;
else
if (do_read)
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],do_read};
else
do_read_pipe <= {do_read_pipe[TCL_PIPE_LENGTH-2:0],1'b0};
end
// these blocks already assumes burstlength 8 in half rate and BL4 in full rate
always @(*)
begin
if (DWIDTH_RATIO == 2)
begin
if (start_odt_write || start_odt_read)
combi_odt_l <= 1'b1;
else
combi_odt_l <= 1'b0;
end
else // half rate
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_read)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
else
begin
if (start_odt_read)
begin
combi_odt_l <= 1'b1;
combi_odt_h <= 1'b1;
end
else if (start_odt_write)
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b1;
end
else
begin
combi_odt_l <= 1'b0;
combi_odt_h <= 1'b0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else
if (DWIDTH_RATIO == 2)
begin
reg_odt_h <= 1'b0;
if (start_odt_write || start_odt_read)
begin
reg_odt_l <= 1'b1;
offset_code <= 2;
end
else if (offset_code == 2)
offset_code <= 3;
else if (offset_code == 3)
begin
offset_code <= 0;
reg_odt_l <= 1'b0;
end
end
else
begin
if (int_tcwl % 2 == 0) //even
begin
if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
else
begin
if (start_odt_read)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 3;
end
else if (start_odt_write)
begin
reg_odt_l <= 1'b1;
reg_odt_h <= 1'b1;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 0)
offset_code <= 1;
else if (reg_odt_h && reg_odt_l && offset_code == 1)
begin
reg_odt_l <= 1'b0;
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (reg_odt_h && reg_odt_l && offset_code == 3)
begin
reg_odt_h <= 1'b0;
offset_code <= 0;
end
else if (!reg_odt_h && reg_odt_l)
begin
reg_odt_l <= 1'b0;
offset_code <= 0;
end
end
end
end
endmodule |
module alt_ddrx_afi_block
# (parameter
DWIDTH_RATIO = 2,
MEM_IF_DQ_WIDTH = 8,
MEM_IF_DQS_WIDTH = 1,
MEM_IF_DM_WIDTH = 1,
CTL_ECC_ENABLED = 0,
CTL_OUTPUT_REGD = 0,
STATEMACHINE_TYPE = "TWO_CK",
WLAT_BUS_WIDTH = 5
)
(
ctl_clk,
ctl_reset_n,
afi_wlat,
// state machine command inputs
do_write,
do_read,
do_burst_chop,
rdwr_data_valid,
ecc_wdata,
ecc_be,
// output from AFi block
ecc_wdata_fifo_read,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_doing_read,
afi_doing_read_full
);
input ctl_clk;
input ctl_reset_n;
input [WLAT_BUS_WIDTH-1:0] afi_wlat;
localparam WLAT_PIPE_LENGTH = 2**WLAT_BUS_WIDTH;
localparam WLAT_SUBTRACT = (CTL_OUTPUT_REGD == 0) ? 2 : 1;
// state machine command inputs
input do_write;
input do_read;
input do_burst_chop;
input rdwr_data_valid;
input [MEM_IF_DQ_WIDTH*DWIDTH_RATIO-1:0] ecc_wdata;
input [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO)/8-1:0] ecc_be;
// output from AFi block
output ecc_wdata_fifo_read;
output [MEM_IF_DQS_WIDTH*DWIDTH_RATIO/2-1:0] afi_dqs_burst;
output [MEM_IF_DQS_WIDTH*DWIDTH_RATIO/2-1:0] afi_wdata_valid;
output [MEM_IF_DQ_WIDTH*DWIDTH_RATIO-1:0] afi_wdata;
output [MEM_IF_DM_WIDTH*DWIDTH_RATIO-1:0] afi_dm;
output [MEM_IF_DQS_WIDTH*DWIDTH_RATIO/2-1:0] afi_doing_read;
output [MEM_IF_DQS_WIDTH*DWIDTH_RATIO/2-1:0] afi_doing_read_full;
reg [WLAT_BUS_WIDTH-1:0] afi_wlat_r;
wire do_write;
wire do_read;
wire rdwr_data_valid;
reg ecc_wdata_fifo_read;
wire [MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
wire [MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
wire [MEM_IF_DQ_WIDTH*DWIDTH_RATIO-1:0] afi_wdata;
wire [MEM_IF_DM_WIDTH*DWIDTH_RATIO-1:0] afi_dm;
wire [MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2)-1:0] afi_doing_read;
wire [MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
reg int_dqs_burst;
reg int_dqs_burst_hr;
reg int_wdata_valid;
reg int_real_wdata_valid;
reg int_real_wdata_valid_r;
wire real_wdata_valid;
reg [WLAT_PIPE_LENGTH-1:0] rdwr_data_valid_pipe;
reg doing_write;
reg [1:0] doing_write_count;
reg [WLAT_PIPE_LENGTH-1:0] doing_write_pipe;
reg doing_read;
reg doing_read_combi;
reg doing_read_combi_full;
reg [1:0] doing_read_count;
reg doing_read_r;
reg doing_read_r_full;
// reads and writes are word-aligned
generate
genvar I;
for (I = 0; I < MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2); I = I + 1)
begin : B
assign afi_wdata_valid[I] = int_wdata_valid;
assign afi_doing_read[I] = (CTL_OUTPUT_REGD == 1) ? doing_read_r : doing_read_combi;
assign afi_doing_read_full[I] = (CTL_OUTPUT_REGD == 1) ? doing_read_r_full : doing_read_combi_full;
end
endgenerate
// dqs_burst to AFI, in half rate one bus will start earlier than the other
generate
if (DWIDTH_RATIO == 2)
begin
genvar I;
for (I = 0; I < MEM_IF_DQS_WIDTH; I = I + 1)
begin : C
assign afi_dqs_burst[I] = int_dqs_burst;
end
end
else
begin
genvar I;
for (I = 0; I < MEM_IF_DQS_WIDTH; I = I + 1)
begin : D
assign afi_dqs_burst[I + MEM_IF_DQS_WIDTH] = int_dqs_burst;
assign afi_dqs_burst[I] = int_dqs_burst_hr;
end
end
endgenerate
// this is how we did it in the older controller
// but enhanced for x4 mode where ecc_be is less wide than afi_dm
generate
if ((MEM_IF_DQ_WIDTH*DWIDTH_RATIO)/8 < MEM_IF_DM_WIDTH*DWIDTH_RATIO) // happens in x4 mode
begin
genvar J;
for (J = 0; J < MEM_IF_DM_WIDTH*DWIDTH_RATIO; J = J + 1)
begin : E
if (J % 2 == 0) //even
assign afi_dm[J] = ~ecc_be[J/2] | ~real_wdata_valid;
else //odd
assign afi_dm[J] = ~ecc_be[(J-1)/2] | ~real_wdata_valid;
end
end
else
begin
genvar J;
for (J = 0; J < MEM_IF_DM_WIDTH*DWIDTH_RATIO; J = J + 1)
begin : F
assign afi_dm[J] = ~ecc_be[J] | ~real_wdata_valid;
end
end
endgenerate
// no data manipulation here
assign afi_wdata = ecc_wdata;
// ECC support
assign real_wdata_valid = (CTL_ECC_ENABLED == 0) ? int_real_wdata_valid : int_real_wdata_valid_r;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
afi_wlat_r <= 0;
else
afi_wlat_r <= afi_wlat;
end
// generate doing read count for non-burst chop operation
// four clock state machine has higher reset value
generate
if (STATEMACHINE_TYPE == "FOUR_CK")
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read_count <= 0;
else
if (do_read && !do_burst_chop)
doing_read_count <= 1;
else if (doing_read_count == 2)
doing_read_count <= 0;
else if (doing_read_count > 0)
doing_read_count <= doing_read_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read <= 1'b0;
else
if (do_read)
doing_read <= 1'b1;
else if (doing_read_count > 0)
doing_read <= 1'b1;
else
doing_read <= 1'b0;
end
end
else // STATEMACHINE_TYPE == "TWO_CK"
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read <= 1'b0;
else
doing_read <= do_read & ~do_burst_chop;
end
end
endgenerate
// almost phy output generated here
// starts when there's a read and rdwr_data_valid
// continue as long as doing read count or bchop read count is positive
always @(*)
begin
if ((do_read || doing_read) && rdwr_data_valid)
doing_read_combi <= 1'b1;
else
doing_read_combi <= 1'b0;
end
// SPR 341664, we need a full signal so that uniphy can capture read data properly
always @(*)
begin
if (do_read || doing_read)
doing_read_combi_full <= 1'b1;
else
doing_read_combi_full <= 1'b0;
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_r <= 1'b0;
doing_read_r_full <= 1'b0;
end
else
begin
doing_read_r <= doing_read_combi;
doing_read_r_full <= doing_read_combi_full;
end
end
// doing write generation using do write and doing write count
// doing write count starts everytime there's a write
// in two-clock state machine doing write only needed to be high 1 clock cycle, anded with do write we'll get two
// four-clock state machine, counter counts up to two, doing write high 3 clock cycles, and with do write we'll get four
generate
if (STATEMACHINE_TYPE == "FOUR_CK")
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_count <= 0;
else
if (do_write && !do_burst_chop)
doing_write_count <= 1;
else if (doing_write_count == 2)
doing_write_count <= 0;
else if (doing_write_count > 0)
doing_write_count <= doing_write_count + 1'b1;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write <= 1'b0;
else
if (do_write)
doing_write <= 1'b1;
else if (doing_write_count > 0)
doing_write <= 1'b1;
else
doing_write <= 1'b0;
end
end
else // STATEMACHINE_TYPE == "TWO_CK"
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write <= 1'b0;
else
doing_write <= do_write & ~do_burst_chop;
end
end
endgenerate
// do_write is pushed into pipe
// generated doing write is pushed after do_write
// content of pipe shows how long dqs should toggle, used to generate dqs_burst
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_write_pipe <= 0;
else
if (do_write)
doing_write_pipe <= {doing_write_pipe[WLAT_PIPE_LENGTH-2:0],do_write};
else
doing_write_pipe <= {doing_write_pipe[WLAT_PIPE_LENGTH-2:0],doing_write};
end
// rdwr_data_valid pushed into its pipe
// content indicate which data should not be masked (valid) for reads and writes
// used to generate ecc_wdata_fifo_read and wdata_valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
rdwr_data_valid_pipe <= 0;
else
rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[WLAT_PIPE_LENGTH-2:0],rdwr_data_valid};
end
generate
if (CTL_ECC_ENABLED == 0)
begin
// signal to pull data out of wdata_fifo
// high when we are in the burst (doing_write), and valid (rdwr_data_valid)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
ecc_wdata_fifo_read <= 1'b0;
else
if ((CTL_OUTPUT_REGD == 1 && afi_wlat_r == 0) || (CTL_OUTPUT_REGD == 0 && (afi_wlat_r == 0 || afi_wlat_r == 1)))
if ((rdwr_data_valid && do_write) || (rdwr_data_valid && doing_write))
ecc_wdata_fifo_read <= 1'b1;
else
ecc_wdata_fifo_read <= 1'b0;
else
if (rdwr_data_valid_pipe[afi_wlat_r-WLAT_SUBTRACT] && doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT])
ecc_wdata_fifo_read <= 1'b1;
else
ecc_wdata_fifo_read <= 1'b0;
end
end
else // ecc case
begin
// signal to pull data out of wdata_fifo
// high when we are in the burst (doing_write), and valid (rdwr_data_valid)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
ecc_wdata_fifo_read <= 1'b0;
else
if ((CTL_OUTPUT_REGD == 1 && (afi_wlat_r == 0 || afi_wlat_r == 1)) || (CTL_OUTPUT_REGD == 0 && (afi_wlat_r == 0 || afi_wlat_r == 1 || afi_wlat_r == 2)))
begin
//if (afi_wlat_r == 0)
// begin
// $write($time);
// $write(" --- wlat zero not supported in ECC --- \n");
// $stop;
// end
if ((rdwr_data_valid && do_write) || (rdwr_data_valid && doing_write))
ecc_wdata_fifo_read <= 1'b1;
else
ecc_wdata_fifo_read <= 1'b0;
end
else
if (rdwr_data_valid_pipe[afi_wlat_r-WLAT_SUBTRACT-1] && doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT-1])
ecc_wdata_fifo_read <= 1'b1;
else
ecc_wdata_fifo_read <= 1'b0;
end
end
endgenerate
// data valid one clock cycle after read
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_real_wdata_valid <= 1'b0;
else
int_real_wdata_valid <= ecc_wdata_fifo_read;
end
// for ECC, data valid two clock cycles later
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_real_wdata_valid_r <= 1'b0;
else
int_real_wdata_valid_r <= int_real_wdata_valid;
end
// SPR: 313227
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_wdata_valid <= 1'b0;
else
if (CTL_OUTPUT_REGD == 0 && afi_wlat_r == 0)
if (do_write || doing_write_pipe[afi_wlat_r])
int_wdata_valid <= 1'b1;
else
int_wdata_valid <= 1'b0;
else
if (doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT+1])
int_wdata_valid <= 1'b1;
else
int_wdata_valid <= 1'b0;
end
// high earlier than wdata_valid but ends the same
// for writes only, where dqs should toggle, use doing_write_pipe
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_dqs_burst <= 1'b0;
else
if ((CTL_OUTPUT_REGD == 1 && afi_wlat_r == 0) || (CTL_OUTPUT_REGD == 0 && (afi_wlat_r == 0 || afi_wlat_r == 1)))
if (do_write || doing_write_pipe[0])
int_dqs_burst <= 1'b1;
else
int_dqs_burst <= 1'b0;
else
if (doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT] || doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT+1])
int_dqs_burst <= 1'b1;
else
int_dqs_burst <= 1'b0;
end
// signal is only used in half rate
// dqs_burst bus in half rate is not identical
// [0] need to be high first then [1], go low the same time
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_dqs_burst_hr <= 1'b0;
else
if (doing_write_pipe[afi_wlat_r-WLAT_SUBTRACT+1])
int_dqs_burst_hr <= 1'b1;
else
int_dqs_burst_hr <= 1'b0;
end
endmodule |
module ddr2_controller_phy (
// inputs:
dqs_delay_ctrl_import,
dqs_offset_delay_ctrl,
global_reset_n,
hc_scan_ck,
hc_scan_din,
hc_scan_enable_access,
hc_scan_enable_dm,
hc_scan_enable_dq,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_update,
local_address,
local_autopch_req,
local_be,
local_burstbegin,
local_multicast_req,
local_read_req,
local_refresh_chip,
local_refresh_req,
local_self_rfsh_req,
local_size,
local_wdata,
local_write_req,
oct_ctl_rs_value,
oct_ctl_rt_value,
pll_phasecounterselect,
pll_phasestep,
pll_phaseupdown,
pll_reconfig,
pll_reconfig_counter_param,
pll_reconfig_counter_type,
pll_reconfig_data_in,
pll_reconfig_enable,
pll_reconfig_read_param,
pll_reconfig_soft_reset_en_n,
pll_reconfig_write_param,
pll_ref_clk,
soft_reset_n,
// outputs:
aux_full_rate_clk,
aux_half_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
ecc_interrupt,
hc_scan_dout,
local_init_done,
local_power_down_ack,
local_rdata,
local_rdata_error,
local_rdata_valid,
local_ready,
local_refresh_ack,
local_self_rfsh_ack,
local_wdata_req,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
phy_clk,
pll_phase_done,
pll_reconfig_busy,
pll_reconfig_clk,
pll_reconfig_data_out,
pll_reconfig_reset,
reset_phy_clk_n,
reset_request_n
)
;
output aux_full_rate_clk;
output aux_half_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output dll_reference_clk;
output [ 5: 0] dqs_delay_ctrl_export;
output ecc_interrupt;
output [ 15: 0] hc_scan_dout;
output local_init_done;
output local_power_down_ack;
output [ 31: 0] local_rdata;
output local_rdata_error;
output local_rdata_valid;
output local_ready;
output local_refresh_ack;
output local_self_rfsh_ack;
output local_wdata_req;
output [ 12: 0] mem_addr;
output [ 1: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 1: 0] mem_dm;
inout [ 15: 0] mem_dq;
inout [ 1: 0] mem_dqs;
inout [ 1: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output phy_clk;
output pll_phase_done;
output pll_reconfig_busy;
output pll_reconfig_clk;
output [ 8: 0] pll_reconfig_data_out;
output pll_reconfig_reset;
output reset_phy_clk_n;
output reset_request_n;
input [ 5: 0] dqs_delay_ctrl_import;
input [ 5: 0] dqs_offset_delay_ctrl;
input global_reset_n;
input hc_scan_ck;
input [ 1: 0] hc_scan_din;
input hc_scan_enable_access;
input [ 1: 0] hc_scan_enable_dm;
input [ 15: 0] hc_scan_enable_dq;
input [ 1: 0] hc_scan_enable_dqs;
input [ 1: 0] hc_scan_enable_dqs_config;
input [ 1: 0] hc_scan_update;
input [ 23: 0] local_address;
input local_autopch_req;
input [ 3: 0] local_be;
input local_burstbegin;
input local_multicast_req;
input local_read_req;
input local_refresh_chip;
input local_refresh_req;
input local_self_rfsh_req;
input [ 3: 0] local_size;
input [ 31: 0] local_wdata;
input local_write_req;
input [ 13: 0] oct_ctl_rs_value;
input [ 13: 0] oct_ctl_rt_value;
input [ 3: 0] pll_phasecounterselect;
input pll_phasestep;
input pll_phaseupdown;
input pll_reconfig;
input [ 2: 0] pll_reconfig_counter_param;
input [ 3: 0] pll_reconfig_counter_type;
input [ 8: 0] pll_reconfig_data_in;
input pll_reconfig_enable;
input pll_reconfig_read_param;
input pll_reconfig_soft_reset_en_n;
input pll_reconfig_write_param;
input pll_ref_clk;
input soft_reset_n;
wire [ 12: 0] afi_addr;
wire [ 1: 0] afi_ba;
wire afi_cas_n;
wire afi_cke;
wire afi_cs_n;
wire [ 3: 0] afi_dm;
wire [ 1: 0] afi_doing_rd;
wire [ 1: 0] afi_dqs_burst;
wire afi_odt;
wire afi_ras_n;
wire [ 31: 0] afi_rdata;
wire afi_rdata_valid;
wire afi_rst_n;
wire [ 31: 0] afi_wdata;
wire [ 1: 0] afi_wdata_valid;
wire afi_we_n;
wire [ 4: 0] afi_wlat;
wire aux_full_rate_clk;
wire aux_half_rate_clk;
wire aux_scan_clk;
wire aux_scan_clk_reset_n;
wire [ 31: 0] csr_rdata_sig;
wire csr_rdata_valid_sig;
wire csr_waitrequest_sig;
wire [ 1: 0] ctl_cal_byte_lane_sel_n;
wire ctl_cal_fail;
wire ctl_cal_req;
wire ctl_cal_success;
wire ctl_clk;
wire ctl_mem_clk_disable;
wire [ 4: 0] ctl_rlat;
wire [ 31: 0] dbg_rd_data_sig;
wire dbg_waitrequest_sig;
wire dll_reference_clk;
wire [ 5: 0] dqs_delay_ctrl_export;
wire ecc_interrupt;
wire [ 15: 0] hc_scan_dout;
wire local_init_done;
wire local_power_down_ack;
wire [ 31: 0] local_rdata;
wire local_rdata_error;
wire local_rdata_valid;
wire local_ready;
wire local_refresh_ack;
wire local_self_rfsh_ack;
wire local_wdata_req;
wire [ 12: 0] mem_addr;
wire [ 1: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 1: 0] mem_dm;
wire [ 15: 0] mem_dq;
wire [ 1: 0] mem_dqs;
wire [ 1: 0] mem_dqsn;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pll_phase_done;
wire pll_reconfig_busy;
wire pll_reconfig_clk;
wire [ 8: 0] pll_reconfig_data_out;
wire pll_reconfig_reset;
wire reset_ctl_clk_n;
wire reset_phy_clk_n;
wire reset_request_n;
assign phy_clk = ctl_clk;
assign reset_phy_clk_n = reset_ctl_clk_n;
ddr2_alt_ddrx_controller_wrapper ddr2_alt_ddrx_controller_wrapper_inst
(
.afi_addr (afi_addr),
.afi_ba (afi_ba),
.afi_cas_n (afi_cas_n),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_dm (afi_dm),
.afi_doing_read (afi_doing_rd),
.afi_dqs_burst (afi_dqs_burst),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_rdata (afi_rdata),
.afi_rdata_valid (afi_rdata_valid),
.afi_rst_n (afi_rst_n),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_we_n (afi_we_n),
.afi_wlat (afi_wlat),
.csr_addr (16'b0),
.csr_be (4'b0),
.csr_rdata (csr_rdata_sig),
.csr_rdata_valid (csr_rdata_valid_sig),
.csr_read_req (1'b0),
.csr_waitrequest (csr_waitrequest_sig),
.csr_wdata (32'b0),
.csr_write_req (1'b0),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_clk (ctl_clk),
.ctl_half_clk (aux_half_rate_clk),
.ctl_half_clk_reset_n (reset_ctl_clk_n),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_reset_n (reset_ctl_clk_n),
.ecc_interrupt (ecc_interrupt),
.local_addr (local_address),
.local_autopch_req (local_autopch_req),
.local_be (local_be),
.local_burstbegin (local_burstbegin),
.local_init_done (local_init_done),
.local_multicast (local_multicast_req),
.local_power_down_ack (local_power_down_ack),
.local_rdata (local_rdata),
.local_rdata_error (local_rdata_error),
.local_rdata_valid (local_rdata_valid),
.local_read_req (local_read_req),
.local_ready (local_ready),
.local_refresh_ack (local_refresh_ack),
.local_refresh_chip (local_refresh_chip),
.local_refresh_req (local_refresh_req),
.local_self_rfsh_ack (local_self_rfsh_ack),
.local_self_rfsh_chip ({1{1'b1}}),
.local_self_rfsh_req (local_self_rfsh_req),
.local_size (local_size),
.local_wdata (local_wdata),
.local_wdata_req (local_wdata_req),
.local_write_req (local_write_req)
);
ddr2_phy ddr2_phy_inst
(
.aux_full_rate_clk (aux_full_rate_clk),
.aux_half_rate_clk (aux_half_rate_clk),
.ctl_addr (afi_addr),
.ctl_ba (afi_ba),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_cas_n (afi_cas_n),
.ctl_cke (afi_cke),
.ctl_clk (ctl_clk),
.ctl_cs_n (afi_cs_n),
.ctl_dm (afi_dm),
.ctl_doing_rd (afi_doing_rd),
.ctl_dqs_burst (afi_dqs_burst),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_odt (afi_odt),
.ctl_ras_n (afi_ras_n),
.ctl_rdata (afi_rdata),
.ctl_rdata_valid (afi_rdata_valid),
.ctl_reset_n (reset_ctl_clk_n),
.ctl_rlat (ctl_rlat),
.ctl_rst_n (afi_rst_n),
.ctl_wdata (afi_wdata),
.ctl_wdata_valid (afi_wdata_valid),
.ctl_we_n (afi_we_n),
.ctl_wlat (afi_wlat),
.dbg_addr (13'b0),
.dbg_clk (ctl_clk),
.dbg_cs (1'b0),
.dbg_rd (1'b0),
.dbg_rd_data (dbg_rd_data_sig),
.dbg_reset_n (reset_ctl_clk_n),
.dbg_waitrequest (dbg_waitrequest_sig),
.dbg_wr (1'b0),
.dbg_wr_data (32'b0),
.dll_reference_clk (dll_reference_clk),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export),
.dqs_delay_ctrl_import (dqs_delay_ctrl_import),
.dqs_offset_delay_ctrl (dqs_offset_delay_ctrl),
.global_reset_n (global_reset_n),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm[1 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[1 : 0]),
.mem_dqs_n (mem_dqsn[1 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.pll_ref_clk (pll_ref_clk),
.reset_request_n (reset_request_n),
.soft_reset_n (soft_reset_n)
);
//<< start europa
endmodule |
module ddr2_example_driver (
// inputs:
clk,
local_rdata,
local_rdata_valid,
local_ready,
reset_n,
// outputs:
local_bank_addr,
local_be,
local_burstbegin,
local_col_addr,
local_cs_addr,
local_read_req,
local_row_addr,
local_size,
local_wdata,
local_write_req,
pnf_per_byte,
pnf_persist,
test_complete,
test_status
)
/* synthesis ALTERA_ATTRIBUTE = "MESSAGE_DISABLE=14130;MESSAGE_DISABLE=14110" */ ;
output [ 1: 0] local_bank_addr;
output [ 3: 0] local_be;
output local_burstbegin;
output [ 9: 0] local_col_addr;
output local_cs_addr;
output local_read_req;
output [ 12: 0] local_row_addr;
output [ 3: 0] local_size;
output [ 31: 0] local_wdata;
output local_write_req;
output [ 3: 0] pnf_per_byte;
output pnf_persist;
output test_complete;
output [ 7: 0] test_status;
input clk;
input [ 31: 0] local_rdata;
input local_rdata_valid;
input local_ready;
input reset_n;
wire [ 19: 0] COUNTER_VALUE;
wire [ 3: 0] LOCAL_BURST_LEN_s;
wire [ 1: 0] MAX_BANK;
wire MAX_CHIPSEL;
wire [ 9: 0] MAX_COL;
wire [ 12: 0] MAX_ROW;
wire [ 12: 0] MAX_ROW_PIN;
wire MIN_CHIPSEL;
wire [ 5: 0] addr_value;
wire avalon_burst_mode;
reg [ 1: 0] bank_addr;
reg [ 3: 0] be;
reg [ 3: 0] burst_beat_count;
reg burst_begin;
reg [ 9: 0] col_addr;
wire [ 3: 0] compare;
reg [ 3: 0] compare_reg;
reg [ 3: 0] compare_valid;
reg [ 3: 0] compare_valid_reg;
reg cs_addr;
wire [ 31: 0] dgen_data;
reg dgen_enable;
reg [ 31: 0] dgen_ldata;
reg dgen_load;
wire dgen_pause;
wire enable_be;
reg full_burst_on;
reg last_rdata_valid;
reg last_wdata_req;
wire [ 1: 0] local_bank_addr;
wire [ 3: 0] local_be;
wire local_burstbegin;
wire [ 9: 0] local_col_addr;
wire local_cs_addr;
wire local_read_req;
wire [ 12: 0] local_row_addr;
wire [ 3: 0] local_size;
wire [ 31: 0] local_wdata;
wire local_write_req;
wire [ 9: 0] max_col_value;
wire p_burst_begin;
wire p_read_req;
reg p_state_on;
wire pause_be;
wire [ 3: 0] pnf_per_byte;
reg pnf_persist;
reg pnf_persist1;
wire pnf_persist_compare;
wire powerdn_on;
reg rdata_valid_flag;
reg rdata_valid_flag_reg;
reg rdata_valid_flag_reg_2;
wire reached_max_address;
reg read_req;
reg [ 7: 0] reads_remaining;
reg reset_address;
reg reset_be;
reg reset_data;
wire restart_LFSR_n;
reg [ 12: 0] row_addr;
wire selfrfsh_on;
wire [ 3: 0] size;
reg [ 4: 0] state;
reg test_addr_pin;
reg test_addr_pin_mode;
wire test_addr_pin_on;
reg test_complete;
reg test_dm_pin;
reg test_dm_pin_mode;
wire test_dm_pin_on;
reg test_incomplete_writes;
reg test_incomplete_writes_mode;
wire test_incomplete_writes_on;
reg test_seq_addr;
reg test_seq_addr_mode;
wire test_seq_addr_on;
wire [ 7: 0] test_status;
reg wait_first_write_data;
wire [ 31: 0] wdata;
wire wdata_req;
reg write_req;
reg [ 7: 0] writes_remaining;
//
//Turn on this mode to test sequential address
assign test_seq_addr_on = 1'b1;
//Turn on this mode to test all address pins by a One-hot pattern address generator
assign test_addr_pin_on = 1'b1;
//Turn on this mode to make use of dm pins
assign test_dm_pin_on = 1'b1;
//Turn on this mode to exercise write process in Full rate, size 1 or DDR3 Half rate, size 1
assign test_incomplete_writes_on = 1'b1;
//restart_LFSR_n is an active low signal, set it to 1'b0 to restart LFSR data generator after a complete test
assign restart_LFSR_n = 1'b1;
//Change COUNTER_VALUE to control the period of power down and self refresh mode
assign COUNTER_VALUE = 150;
//Change MAX_ROW to test more or lesser row address in test_seq_addr_mode, maximum value is 2^(row bits) -1, while minimum value is 0
assign MAX_ROW = 3;
//Change MAX_COL to test more or lesser column address in test_seq_addr_mode, maximum value is 2^(column bits) - (LOCAL_BURST_LEN_s * dwidth_ratio (aka half-rate (4) or full-rate (2))), while minimum value is 0 for Half rate and (LOCAL_BURST_LEN_s * dwidth_ratio) for Full rate
assign MAX_COL = 16;
//Decrease MAX_BANK to test lesser bank address, minimum value is 0
assign MAX_BANK = 3;
//Decrease MAX_CHIPSEL to test lesser memory chip, minimum value is MIN_CHIPSEL
assign MAX_CHIPSEL = 0;
//
assign MIN_CHIPSEL = 0;
assign MAX_ROW_PIN = {13{1'b1}};
assign max_col_value = ((addr_value == 2) == 0)? MAX_COL :
(MAX_COL + 2);
assign powerdn_on = 1'b0;
assign selfrfsh_on = 1'b0;
assign local_burstbegin = burst_begin | p_burst_begin;
assign avalon_burst_mode = 1;
//
//One hot decoder for test_status signal
assign test_status[0] = test_seq_addr_mode;
assign test_status[1] = test_incomplete_writes_mode;
assign test_status[2] = test_dm_pin_mode;
assign test_status[3] = test_addr_pin_mode;
assign test_status[4] = 0;
assign test_status[5] = 0;
assign test_status[6] = 0;
assign test_status[7] = test_complete;
assign p_read_req = 0;
assign p_burst_begin = 0;
assign local_cs_addr = cs_addr;
assign local_row_addr = row_addr;
assign local_bank_addr = bank_addr;
assign local_col_addr = col_addr;
assign local_write_req = write_req;
assign local_wdata = wdata;
assign local_read_req = read_req | p_read_req;
assign wdata = (reset_data == 0)? dgen_data :
32'd0;
//The LOCAL_BURST_LEN_s is a signal used insted of the parameter LOCAL_BURST_LEN
assign LOCAL_BURST_LEN_s = 2;
//LOCAL INTERFACE (AVALON)
assign wdata_req = write_req & local_ready;
// Generate new data (enable lfsr) when writing or reading valid data
assign dgen_pause = ~ ((wdata_req & ~reset_data) | (local_rdata_valid));
assign enable_be = (wdata_req & test_dm_pin_mode & ~reset_data) | (test_dm_pin_mode & local_rdata_valid);
assign pnf_per_byte = compare_valid_reg;
assign pause_be = (reset_data & test_dm_pin_mode) | ~test_dm_pin_mode;
assign local_be = be;
assign local_size = size;
assign size = (full_burst_on == 0)? 1'd1 :
LOCAL_BURST_LEN_s[3 : 0];
assign reached_max_address = ((test_dm_pin_mode | test_addr_pin_mode | state == 5'd9) & (row_addr == MAX_ROW_PIN)) || ((test_seq_addr_mode | test_incomplete_writes_mode) & (col_addr == (max_col_value)) & (row_addr == MAX_ROW) & (bank_addr == MAX_BANK) & (cs_addr == MAX_CHIPSEL));
assign addr_value = ((test_incomplete_writes_mode & write_req & ~full_burst_on) == 0)? 4 :
2;
assign pnf_persist_compare = (rdata_valid_flag_reg_2 == 0)? 1'd1 :
pnf_persist1;
ddr2_ex_lfsr8 LFSRGEN_0_lfsr_inst
(
.clk (clk),
.data (dgen_data[7 : 0]),
.enable (dgen_enable),
.ldata (dgen_ldata[7 : 0]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_0_lfsr_inst.seed = 1;
// 8 bit comparator per local byte lane
assign compare[0] = (dgen_data[7 : 0] & {8 {be[0]}}) === local_rdata[7 : 0];
ddr2_ex_lfsr8 LFSRGEN_1_lfsr_inst
(
.clk (clk),
.data (dgen_data[15 : 8]),
.enable (dgen_enable),
.ldata (dgen_ldata[15 : 8]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_1_lfsr_inst.seed = 11;
// 8 bit comparator per local byte lane
assign compare[1] = (dgen_data[15 : 8] & {8 {be[1]}}) === local_rdata[15 : 8];
ddr2_ex_lfsr8 LFSRGEN_2_lfsr_inst
(
.clk (clk),
.data (dgen_data[23 : 16]),
.enable (dgen_enable),
.ldata (dgen_ldata[23 : 16]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_2_lfsr_inst.seed = 21;
// 8 bit comparator per local byte lane
assign compare[2] = (dgen_data[23 : 16] & {8 {be[2]}}) === local_rdata[23 : 16];
ddr2_ex_lfsr8 LFSRGEN_3_lfsr_inst
(
.clk (clk),
.data (dgen_data[31 : 24]),
.enable (dgen_enable),
.ldata (dgen_ldata[31 : 24]),
.load (dgen_load),
.pause (dgen_pause),
.reset_n (reset_n)
);
defparam LFSRGEN_3_lfsr_inst.seed = 31;
// 8 bit comparator per local byte lane
assign compare[3] = (dgen_data[31 : 24] & {8 {be[3]}}) === local_rdata[31 : 24];
//
//-----------------------------------------------------------------
//Main clocked process
//-----------------------------------------------------------------
//Read / Write control state machine & address counter
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
//Reset - asynchronously force all register outputs LOW
state <= 5'd0;
write_req <= 1'b0;
read_req <= 1'b0;
burst_begin <= 1'b0;
burst_beat_count <= 0;
dgen_load <= 1'b0;
wait_first_write_data <= 1'b0;
test_complete <= 1'b0;
reset_data <= 1'b0;
reset_be <= 1'b0;
writes_remaining <= 0;
reads_remaining <= 0;
test_addr_pin <= 1'b0;
test_dm_pin <= 1'b0;
test_seq_addr <= 1'b0;
test_incomplete_writes <= 1'b0;
test_addr_pin_mode <= 1'b0;
test_dm_pin_mode <= 1'b0;
test_seq_addr_mode <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
full_burst_on <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= 1'b1;
end
else
begin
if (write_req & local_ready)
begin
if (wdata_req)
writes_remaining <= writes_remaining + (size - 1);
else
writes_remaining <= writes_remaining + size;
end
else if ((wdata_req) & (writes_remaining > 0))
//size
writes_remaining <= writes_remaining - 1'b1;
else
writes_remaining <= writes_remaining;
if ((read_req | p_read_req) & local_ready)
begin
if (local_rdata_valid)
reads_remaining <= reads_remaining + (size - 1);
else
reads_remaining <= reads_remaining + size;
end
else if ((local_rdata_valid) & (reads_remaining > 0))
reads_remaining <= reads_remaining - 1'b1;
else
reads_remaining <= reads_remaining;
case (state)
5'd0: begin
test_addr_pin <= test_addr_pin_on;
test_dm_pin <= test_dm_pin_on;
test_seq_addr <= test_seq_addr_on;
test_incomplete_writes <= test_incomplete_writes_on;
test_complete <= 1'b0;
state <= 5'd1;
end // 5'd0
5'd1: begin
//Reset just in case!
reset_address <= 1'b0;
reset_be <= 1'b0;
write_req <= 1'b1;
writes_remaining <= 1'b0;
reads_remaining <= 1'b0;
wait_first_write_data <= 1'b1;
dgen_enable <= 1'b1;
if (test_seq_addr == 1'b1)
begin
test_seq_addr_mode <= 1;
if (avalon_burst_mode == 0)
begin
state <= 5'd5;
burst_begin <= 1'b1;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else if (test_incomplete_writes == 1'b1)
begin
full_burst_on <= 1'b0;
test_incomplete_writes_mode <= 1;
state <= 5'd5;
if (avalon_burst_mode == 1)
burst_begin <= 1'b1;
end
else if (test_dm_pin == 1'b1)
begin
reset_data <= 1'b1;
test_dm_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd2;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd10;
end
end
else if (test_addr_pin == 1'b1)
begin
test_addr_pin_mode <= 1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else if (avalon_burst_mode == 1)
begin
state <= 5'd13;
burst_begin <= 1'b1;
end
end
else
begin
write_req <= 1'b0;
wait_first_write_data <= 1'b0;
state <= 5'd9;
end
end // 5'd1
5'd10: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd11;
end
end // 5'd10
5'd11: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd12;
else
state <= 5'd10;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd11
5'd12: begin
burst_begin <= 1'b0;
if (write_req & local_ready)
state <= 5'd3;
end // 5'd12
5'd13: begin
wait_first_write_data <= 1'b0;
burst_begin <= 1'b0;
reset_be <= 1'b0;
if (write_req & local_ready)
begin
burst_beat_count <= burst_beat_count + 1'b1;
state <= 5'd14;
end
end // 5'd13
5'd14: begin
if (write_req & local_ready)
if (burst_beat_count == size - 1'b1)
begin
burst_beat_count <= 0;
burst_begin <= 1'b1;
if (reached_max_address)
state <= 5'd15;
else
state <= 5'd13;
end
else
burst_beat_count <= burst_beat_count + 1'b1;
end // 5'd14
5'd15: begin
if (write_req & local_ready)
begin
reset_address <= 1'b1;
burst_begin <= 1'b0;
state <= 5'd6;
end
end // 5'd15
5'd16: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd16
5'd2: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd3;
end
end // 5'd2
5'd3: begin
if (avalon_burst_mode == 0)
begin
if (!wdata_req)
if (writes_remaining == 0)
begin
reset_be <= 1'b1;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end
else if (write_req & local_ready)
begin
reset_be <= 1'b1;
write_req <= 1'b0;
reset_address <= 1'b1;
dgen_load <= 1'b1;
state <= 5'd4;
end
end // 5'd3
5'd4: begin
reset_address <= 1'b0;
dgen_load <= 1'b0;
reset_be <= 1'b0;
reset_data <= 1'b0;
write_req <= 1'b1;
if (avalon_burst_mode == 0)
begin
burst_begin <= 1'b1;
state <= 5'd5;
end
else
begin
burst_begin <= 1'b1;
state <= 5'd13;
end
end // 5'd4
5'd5: begin
wait_first_write_data <= 1'b0;
if (write_req & local_ready)
if (reached_max_address)
begin
reset_address <= 1'b1;
write_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd6;
if (test_incomplete_writes_mode)
full_burst_on <= 1'b1;
end
end // 5'd5
5'd6: begin
reset_address <= 1'b0;
if (avalon_burst_mode == 0)
begin
if (writes_remaining == 0)
begin
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd7;
end
end
else if (test_incomplete_writes_mode)
begin
dgen_load <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
else if (write_req & local_ready)
begin
write_req <= 1'b0;
dgen_load <= 1'b1;
reset_be <= 1'b1;
read_req <= 1'b1;
burst_begin <= 1'b1;
state <= 5'd16;
end
end // 5'd6
5'd7: begin
dgen_load <= 1'b0;
reset_be <= 1'b0;
if (local_ready & read_req)
if (reached_max_address)
begin
read_req <= 1'b0;
burst_begin <= 1'b0;
state <= 5'd8;
end
end // 5'd7
5'd8: begin
if (reads_remaining == 1'b0)
begin
reset_address <= 1'b1;
if (test_seq_addr)
begin
test_seq_addr <= 1'b0;
test_seq_addr_mode <= 1'b0;
state <= 5'd1;
end
else if (test_incomplete_writes)
begin
test_incomplete_writes <= 1'b0;
test_incomplete_writes_mode <= 1'b0;
state <= 5'd1;
end
else if (test_dm_pin)
begin
test_dm_pin <= 1'b0;
test_dm_pin_mode <= 1'b0;
state <= 5'd1;
end
else if (test_addr_pin)
begin
test_addr_pin_mode <= 1'b0;
dgen_load <= 1'b1;
state <= 5'd9;
end
else
state <= 5'd9;
end
end // 5'd8
5'd9: begin
reset_address <= 1'b0;
reset_be <= 1'b0;
dgen_load <= 1'b0;
if (powerdn_on == 1'b0 & selfrfsh_on == 1'b0)
begin
test_complete <= 1'b1;
p_state_on <= 1'b0;
dgen_enable <= restart_LFSR_n;
state <= 5'd0;
end
else if (reached_max_address & reads_remaining == 0)
begin
p_state_on <= 1'b1;
reset_address <= 1'b1;
reset_be <= 1'b1;
dgen_load <= 1'b1;
end
end // 5'd9
endcase // state
end
end
//
//-----------------------------------------------------------------
//Logics that detect the first read data
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rdata_valid_flag <= 1'b0;
else if (local_rdata_valid)
rdata_valid_flag <= 1'b1;
end
//
//-----------------------------------------------------------------
//Address Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
cs_addr <= 0;
bank_addr <= 0;
row_addr <= 0;
col_addr <= 0;
end
else if (reset_address)
begin
cs_addr <= MIN_CHIPSEL;
row_addr <= 0;
bank_addr <= 0;
col_addr <= 0;
end
else if (((local_ready & write_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_dm_pin_mode | test_addr_pin_mode)) & (state == 5'd7 | state == 5'd16)) | ((local_ready & p_read_req) & (state == 5'd9)))
begin
col_addr[9 : 2] <= {col_addr[8 : 2],col_addr[9]};
row_addr[12 : 0] <= {row_addr[11 : 0],row_addr[12]};
if (row_addr == 13'd0)
begin
col_addr <= 10'd4;
row_addr <= 13'd1;
end
else if (row_addr == {1'b1,{12{1'b0}}})
begin
col_addr <= {{7{1'b1}},{3{1'b0}}};
row_addr <= {{12{1'b1}},1'b0};
end
else if (row_addr == {1'b0,{12{1'b1}}})
begin
col_addr <= {{8{1'b1}},{2{1'b0}}};
row_addr <= {13{1'b1}};
end
if (bank_addr == MAX_BANK)
bank_addr <= 0;
else
bank_addr <= bank_addr + 1'b1;
if (cs_addr == MAX_CHIPSEL)
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else if ((local_ready & write_req & (test_seq_addr_mode | test_incomplete_writes_mode) & (state == 5'd2 | state == 5'd5 | state == 5'd10 | state == 5'd13)) | ((local_ready & read_req & (test_seq_addr_mode | test_incomplete_writes_mode)) & (state == 5'd7 | state == 5'd16)))
if (col_addr >= max_col_value)
begin
col_addr <= 0;
if (row_addr == MAX_ROW)
begin
row_addr <= 0;
if (bank_addr == MAX_BANK)
begin
bank_addr <= 0;
if (cs_addr == MAX_CHIPSEL)
//reached_max_count <= TRUE
//(others => '0')
cs_addr <= MIN_CHIPSEL;
else
cs_addr <= cs_addr + 1'b1;
end
else
bank_addr <= bank_addr + 1'b1;
end
else
row_addr <= row_addr + 1'b1;
end
else
col_addr <= col_addr + addr_value;
end
//
//-----------------------------------------------------------------
//Byte Enable Generator Process
//-----------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
be <= {4{1'b1}};
else if (reset_be)
be <= 4'd1;
else if (enable_be)
be[3 : 0] <= {be[2 : 0],be[3]};
else if (pause_be)
be <= {4{1'b1}};
else
be <= be;
end
//------------------------------------------------------------
//LFSR re-load data storage
//Comparator masking and test pass signal generation
//------------------------------------------------------------
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dgen_ldata <= 0;
last_wdata_req <= 1'b0;
//all ones
compare_valid <= {4 {1'b1}};
//all ones
compare_valid_reg <= {4 {1'b1}};
pnf_persist <= 1'b0;
pnf_persist1 <= 1'b0;
//all ones
compare_reg <= {4 {1'b1}};
last_rdata_valid <= 1'b0;
rdata_valid_flag_reg <= 1'b0;
rdata_valid_flag_reg_2 <= 1'b0;
end
else
begin
last_wdata_req <= wdata_req;
last_rdata_valid <= local_rdata_valid;
rdata_valid_flag_reg <= rdata_valid_flag;
rdata_valid_flag_reg_2 <= rdata_valid_flag_reg;
compare_reg <= compare;
if (wait_first_write_data)
dgen_ldata <= dgen_data;
//Enable the comparator result when read data is valid
if (last_rdata_valid)
compare_valid <= compare_reg;
//Create the overall persistent passnotfail output
if (&compare_valid & rdata_valid_flag_reg & pnf_persist_compare)
pnf_persist1 <= 1'b1;
else
pnf_persist1 <= 1'b0;
//Extra register stage to help Tco / Fmax on comparator output pins
compare_valid_reg <= compare_valid;
pnf_persist <= pnf_persist1;
end
end
endmodule |
module ddr2_alt_ddrx_controller_wrapper (
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
local_ready,
local_read_req,
local_write_req,
local_wdata_req,
local_size,
local_burstbegin,
local_addr,
local_rdata_valid,
local_rdata_error,
local_rdata,
local_wdata,
local_be,
local_autopch_req,
local_multicast,
local_init_done,
local_refresh_req,
local_refresh_chip,
local_refresh_ack,
local_self_rfsh_req,
local_self_rfsh_chip,
local_self_rfsh_ack,
local_power_down_ack,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_odt,
afi_rst_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_doing_read,
afi_rdata,
afi_rdata_valid,
csr_write_req,
csr_read_req,
csr_addr,
csr_be,
csr_wdata,
csr_waitrequest,
csr_rdata,
csr_rdata_valid,
ecc_interrupt,
bank_information,
bank_open
);
//Inserted Generics
localparam MEM_TYPE = "DDR2";
localparam LOCAL_SIZE_WIDTH = 4;
localparam LOCAL_ADDR_WIDTH = 24;
localparam LOCAL_DATA_WIDTH = 32;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CHIP_BITS = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_ROW_WIDTH = 13;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 2;
localparam MEM_IF_DQS_WIDTH = 2;
localparam MEM_IF_DQ_WIDTH = 16;
localparam MEM_IF_DM_WIDTH = 2;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 2;
localparam CTL_LOOK_AHEAD_DEPTH = 4;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 5;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 5;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 8;
localparam MEM_TRFC = 15;
localparam MEM_TREFI = 1400;
localparam MEM_TRCD = 3;
localparam MEM_TRP = 3;
localparam MEM_TWR = 3;
localparam MEM_TWTR = 3;
localparam MEM_TRTP = 2;
localparam MEM_TRAS = 9;
localparam MEM_TRC = 12;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 3;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_ECC_MULTIPLES_40_72 = 0;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output local_ready;
input local_read_req;
input local_write_req;
output local_wdata_req;
input [LOCAL_SIZE_WIDTH-1:0] local_size;
input local_burstbegin;
input [LOCAL_ADDR_WIDTH-1:0] local_addr;
output local_rdata_valid;
output local_rdata_error;
output [LOCAL_DATA_WIDTH-1:0] local_rdata;
input [LOCAL_DATA_WIDTH-1:0] local_wdata;
input [LOCAL_DATA_WIDTH/8-1:0] local_be;
input local_autopch_req;
input local_multicast;
output local_init_done;
input local_refresh_req;
input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip;
output local_refresh_ack;
input local_self_rfsh_req;
input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip;
output local_self_rfsh_ack;
output local_power_down_ack;
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable;
output [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n;
output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt;
output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid;
output [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO) - 1:0] afi_wdata;
output [(MEM_IF_DM_WIDTH*DWIDTH_RATIO) - 1:0] afi_dm;
input [4:0] afi_wlat;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read;
input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata;
input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid;
input csr_write_req;
input csr_read_req;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output csr_waitrequest;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
output csr_rdata_valid;
output ecc_interrupt;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open;
alt_ddrx_controller # (
.MEM_TYPE ( MEM_TYPE ),
.LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.LOCAL_IF_TYPE ( LOCAL_IF_TYPE ),
.MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ),
.MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ),
.MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ),
.MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ),
.MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ),
.MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ),
.MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ),
.MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ),
.MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ),
.MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ),
.MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ),
.MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ),
.MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ),
.DWIDTH_RATIO ( DWIDTH_RATIO ),
.CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ),
.CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ),
.CTL_HRB_ENABLED ( CTL_HRB_ENABLED ),
.CTL_ECC_ENABLED ( CTL_ECC_ENABLED ),
.CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ),
.CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ),
.CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ),
.CTL_CSR_ENABLED ( CTL_CSR_ENABLED ),
.CTL_ODT_ENABLED ( CTL_ODT_ENABLED ),
.CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ),
.CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CSR_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ),
.CTL_USR_REFRESH ( CTL_USR_REFRESH ),
.MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ),
.MEM_ADD_LAT ( MEM_ADD_LAT ),
.MEM_TCL ( MEM_TCL ),
.MEM_TRRD ( MEM_TRRD ),
.MEM_TFAW ( MEM_TFAW ),
.MEM_TRFC ( MEM_TRFC ),
.MEM_TREFI ( MEM_TREFI ),
.MEM_TRCD ( MEM_TRCD ),
.MEM_TRP ( MEM_TRP ),
.MEM_TWR ( MEM_TWR ),
.MEM_TWTR ( MEM_TWTR ),
.MEM_TRTP ( MEM_TRTP ),
.MEM_TRAS ( MEM_TRAS ),
.MEM_TRC ( MEM_TRC ),
.MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ),
.ADDR_ORDER ( ADDR_ORDER ),
.MULTICAST_WR_EN ( MULTICAST_WR_EN ),
.LOW_LATENCY ( LOW_LATENCY ),
.CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ),
.CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ),
.ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE )
) alt_ddrx_controller_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_half_clk ( ctl_half_clk ),
.ctl_half_clk_reset_n ( ctl_half_clk_reset_n ),
.local_ready ( local_ready ),
.local_read_req ( local_read_req ),
.local_write_req ( local_write_req ),
.local_wdata_req ( local_wdata_req ),
.local_size ( local_size ),
.local_burstbegin ( local_burstbegin ),
.local_addr ( local_addr ),
.local_rdata_valid ( local_rdata_valid ),
.local_rdata_error ( local_rdata_error ),
.local_rdata ( local_rdata ),
.local_wdata ( local_wdata ),
.local_be ( local_be ),
.local_autopch_req ( local_autopch_req ),
.local_multicast ( local_multicast ),
.local_init_done ( local_init_done ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_power_down_ack ( local_power_down_ack ),
.ctl_cal_success ( ctl_cal_success ),
.ctl_cal_fail ( ctl_cal_fail ),
.ctl_cal_req ( ctl_cal_req ),
.ctl_mem_clk_disable ( ctl_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_doing_read ( afi_doing_read ),
.afi_doing_read_full ( ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.csr_write_req ( csr_write_req ),
.csr_read_req ( csr_read_req ),
.csr_addr ( csr_addr ),
.csr_be ( csr_be ),
.csr_wdata ( csr_wdata ),
.csr_waitrequest ( csr_waitrequest ),
.csr_rdata ( csr_rdata ),
.csr_rdata_valid ( csr_rdata_valid ),
.ecc_interrupt ( ecc_interrupt ),
.bank_information ( bank_information ),
.bank_open ( bank_open )
);
endmodule |
module alt_ddrx_input_if
#(parameter MEM_TYPE = "DDR3",
INTERNAL_SIZE_WIDTH = 7,
INTERNAL_DATA_WIDTH = 64,
CTL_HRB_ENABLED = 0,
CTL_CSR_ENABLED = 0,
CTL_REGDIMM_ENABLED = 0,
MEM_IF_CSR_COL_WIDTH = 4,
MEM_IF_CSR_ROW_WIDTH = 5,
MEM_IF_CSR_BANK_WIDTH = 2,
MEM_IF_CSR_CS_WIDTH = 2,
WDATA_BEATS_WIDTH = 9,
LOCAL_DATA_WIDTH = 64,
LOCAL_ADDR_WIDTH = 33,
LOCAL_SIZE_WIDTH = 6,
CTL_LOOK_AHEAD_DEPTH = 4,
CTL_CMD_QUEUE_DEPTH = 4,
MEM_IF_ROW_WIDTH = 16,
MEM_IF_COL_WIDTH = 12,
MEM_IF_BA_WIDTH = 3,
MEM_IF_CHIP_BITS = 2,
DWIDTH_RATIO = 2,
MEMORY_BURSTLENGTH = 8,
ENABLE_BURST_MERGE = 1,
FAMILY = "Stratix",
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1,
LOCAL_IF_TYPE = "AVALON"
)(
// port connections
ctl_clk ,
ctl_reset_n ,
ctl_half_clk ,
ctl_half_clk_reset_n ,
//---------------------------------------------------------------------
// user side signals
//---------------------------------------------------------------------
local_read_req ,
local_write_req ,
local_ready ,
local_size ,
local_autopch_req ,
local_multicast ,
local_burstbegin ,
local_init_done ,
local_addr ,
local_rdata_error ,
local_rdata_valid ,
local_rdata ,
local_wdata ,
local_be ,
local_wdata_req ,
ecc_rdata ,
ecc_rdata_valid ,
ecc_rdata_error ,
wdata_fifo_wdata ,
wdata_fifo_be ,
beats_in_wfifo ,
write_req_to_wfifo ,
be_to_wfifo ,
addr_order ,
col_width_from_csr ,
row_width_from_csr ,
bank_width_from_csr ,
cs_width_from_csr ,
regdimm_enable ,
wdata_fifo_read ,
fetch ,
ctl_cal_success ,
ctl_cal_fail ,
cmd_fifo_empty ,
cmd_fifo_full ,
cmd_fifo_wren ,
cmd0_is_a_read ,
cmd0_is_a_write ,
cmd0_autopch_req ,
cmd0_burstcount ,
cmd0_chip_addr ,
cmd0_row_addr ,
cmd0_bank_addr ,
cmd0_col_addr ,
cmd0_is_valid ,
cmd0_multicast_req ,
cmd1_is_a_read ,
cmd1_is_a_write ,
cmd1_chip_addr ,
cmd1_row_addr ,
cmd1_bank_addr ,
cmd1_is_valid ,
cmd1_multicast_req ,
cmd2_is_a_read ,
cmd2_is_a_write ,
cmd2_chip_addr ,
cmd2_row_addr ,
cmd2_bank_addr ,
cmd2_is_valid ,
cmd2_multicast_req ,
cmd3_is_a_read ,
cmd3_is_a_write ,
cmd3_chip_addr ,
cmd3_row_addr ,
cmd3_bank_addr ,
cmd3_is_valid ,
cmd3_multicast_req ,
cmd4_is_a_read ,
cmd4_is_a_write ,
cmd4_chip_addr ,
cmd4_row_addr ,
cmd4_bank_addr ,
cmd4_is_valid ,
cmd4_multicast_req ,
cmd5_is_a_read ,
cmd5_is_a_write ,
cmd5_chip_addr ,
cmd5_row_addr ,
cmd5_bank_addr ,
cmd5_is_valid ,
cmd5_multicast_req ,
cmd6_is_a_read ,
cmd6_is_a_write ,
cmd6_chip_addr ,
cmd6_row_addr ,
cmd6_bank_addr ,
cmd6_is_valid ,
cmd6_multicast_req ,
cmd7_is_a_read ,
cmd7_is_a_write ,
cmd7_chip_addr ,
cmd7_row_addr ,
cmd7_bank_addr ,
cmd7_is_valid ,
cmd7_multicast_req
);
localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8;
localparam INTERNAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH + CTL_HRB_ENABLED;
input ctl_clk ;
input [4 : 0] ctl_reset_n ; // Resynced reset to remove revocery failure in HCx
input ctl_half_clk ;
input ctl_half_clk_reset_n;
input local_read_req ;
input local_write_req ;
input [LOCAL_SIZE_WIDTH-1:0] local_size ;
input local_autopch_req ;
input local_multicast ;
input local_burstbegin ;
input [LOCAL_ADDR_WIDTH-1:0] local_addr ;
input [LOCAL_DATA_WIDTH -1 : 0] local_wdata ;
input [LOCAL_BE_WIDTH -1 : 0] local_be ;
input [1:0] addr_order ;
input [MEM_IF_CSR_COL_WIDTH-1:0] col_width_from_csr ;
input [MEM_IF_CSR_ROW_WIDTH-1:0] row_width_from_csr ;
input [MEM_IF_CSR_BANK_WIDTH-1:0] bank_width_from_csr ;
input [MEM_IF_CSR_CS_WIDTH-1:0] cs_width_from_csr ;
input regdimm_enable ;
input [INTERNAL_DATA_WIDTH -1 : 0] ecc_rdata ;
input [DWIDTH_RATIO/2-1:0] ecc_rdata_valid ;
input ecc_rdata_error ;
//input from state machine
input wdata_fifo_read ;
input fetch ;
//input from phy
input ctl_cal_success ;
input ctl_cal_fail ;
output local_init_done ;
output local_ready ;
output local_rdata_valid ;
output local_rdata_error ;
output [LOCAL_DATA_WIDTH -1 : 0] local_rdata ;
output local_wdata_req ;
output [INTERNAL_DATA_WIDTH -1 : 0]wdata_fifo_wdata ;
output [INTERNAL_DATA_WIDTH/8 -1 : 0]wdata_fifo_be ;
output [WDATA_BEATS_WIDTH-1:0] beats_in_wfifo ;
output write_req_to_wfifo ;
output [INTERNAL_DATA_WIDTH/8 -1 : 0]be_to_wfifo ;
output cmd_fifo_empty ;
output cmd_fifo_full ;
output cmd_fifo_wren ;
output cmd0_is_a_read ;
output cmd0_is_a_write ;
output cmd0_autopch_req ;
output [1:0] cmd0_burstcount ;
output [MEM_IF_CHIP_BITS-1:0] cmd0_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd0_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd0_bank_addr ;
output [MEM_IF_COL_WIDTH-1:0] cmd0_col_addr ;
output cmd0_is_valid ;
output cmd0_multicast_req ;
output cmd1_is_a_read ;
output cmd1_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd1_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd1_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd1_bank_addr ;
output cmd1_is_valid ;
output cmd1_multicast_req ;
output cmd2_is_a_read ;
output cmd2_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd2_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd2_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd2_bank_addr ;
output cmd2_is_valid ;
output cmd2_multicast_req ;
output cmd3_is_a_read ;
output cmd3_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd3_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd3_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd3_bank_addr ;
output cmd3_is_valid ;
output cmd3_multicast_req ;
output cmd4_is_a_read ;
output cmd4_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd4_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd4_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd4_bank_addr ;
output cmd4_is_valid ;
output cmd4_multicast_req ;
output cmd5_is_a_read ;
output cmd5_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd5_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd5_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd5_bank_addr ;
output cmd5_is_valid ;
output cmd5_multicast_req ;
output cmd6_is_a_read ;
output cmd6_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd6_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd6_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd6_bank_addr ;
output cmd6_is_valid ;
output cmd6_multicast_req ;
output cmd7_is_a_read ;
output cmd7_is_a_write ;
output [MEM_IF_CHIP_BITS-1:0] cmd7_chip_addr ;
output [MEM_IF_ROW_WIDTH-1:0] cmd7_row_addr ;
output [MEM_IF_BA_WIDTH-1:0] cmd7_bank_addr ;
output cmd7_is_valid ;
output cmd7_multicast_req ;
wire local_ready ;
wire internal_ready ;
wire wdata_fifo_full;
wire read_req_to_cmd_gen ;
wire write_req_to_cmd_gen ;
wire write_req_to_wfifo;
wire [INTERNAL_DATA_WIDTH -1 : 0] wdata_to_wfifo;
wire [INTERNAL_DATA_WIDTH/8 -1 : 0]be_to_wfifo;
wire avalon_write_req;
wire [INTERNAL_DATA_WIDTH -1 : 0] avalon_wdata;
wire [INTERNAL_ADDR_WIDTH -1 : 0] avalon_addr;
wire [INTERNAL_ADDR_WIDTH -1 : 0] addr_to_cmd_gen;
wire [INTERNAL_SIZE_WIDTH -1 : 0] avalon_size;
wire [INTERNAL_SIZE_WIDTH -1 : 0] size_to_cmd_gen;
wire [INTERNAL_DATA_WIDTH/8 -1 : 0]avalon_be;
wire avalon_read_req;
wire avalon_burstbegin;
wire avalon_multicast;
wire avalon_autopch_req;
wire multicast_to_cmd_gen;
wire autopch_to_cmd_gen;
reg gate_ready_in_reset;
wire int_local_multicast;
wire ready_from_cmd_gen;
wire read_req_from_cmd_gen;
wire write_req_from_cmd_gen;
wire [1 : 0] size_from_cmd_gen;
wire autopch_from_cmd_gen;
wire [MEM_IF_CHIP_BITS -1 : 0] cs_addr_from_cmd_gen;
wire [MEM_IF_BA_WIDTH -1 : 0] bank_addr_from_cmd_gen;
wire [MEM_IF_ROW_WIDTH -1 : 0] row_addr_from_cmd_gen;
wire [MEM_IF_COL_WIDTH -1 : 0] col_addr_from_cmd_gen;
wire multicast_from_cmd_gen;
//======================= Instantiation of alt_ddrx_wdata_fifo =========================
alt_ddrx_wdata_fifo #(
.WDATA_BEATS_WIDTH (WDATA_BEATS_WIDTH),
.LOCAL_DATA_WIDTH (INTERNAL_DATA_WIDTH),
.LOCAL_SIZE_WIDTH (LOCAL_SIZE_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.FAMILY (FAMILY)
) wdata_fifo_inst (
// input
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[0]),
.write_req_to_wfifo (write_req_to_wfifo),
.wdata_to_wfifo (wdata_to_wfifo),
.be_to_wfifo (be_to_wfifo),
.wdata_fifo_read (wdata_fifo_read),
//output
.wdata_fifo_full (wdata_fifo_full),
.wdata_fifo_wdata (wdata_fifo_wdata),
.wdata_fifo_be (wdata_fifo_be),
.beats_in_wfifo (beats_in_wfifo)
);
//======================= End of Instantiation of alt_ddrx_wdata_fifo ===================
//======================= Instantiation of alt_ddrx_cmd_gen ===========================
alt_ddrx_cmd_gen #(
.MEM_IF_CSR_COL_WIDTH (MEM_IF_CSR_COL_WIDTH ),
.MEM_IF_CSR_ROW_WIDTH (MEM_IF_CSR_ROW_WIDTH ),
.MEM_IF_CSR_BANK_WIDTH (MEM_IF_CSR_BANK_WIDTH ),
.MEM_IF_CSR_CS_WIDTH (MEM_IF_CSR_CS_WIDTH ),
.MEM_IF_ROW_WIDTH (MEM_IF_ROW_WIDTH),
.MEM_IF_COL_WIDTH (MEM_IF_COL_WIDTH),
.MEM_IF_BA_WIDTH (MEM_IF_BA_WIDTH),
.MEM_IF_CHIP_BITS (MEM_IF_CHIP_BITS),
.LOCAL_ADDR_WIDTH (INTERNAL_ADDR_WIDTH),
.INTERNAL_SIZE_WIDTH (INTERNAL_SIZE_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEMORY_BURSTLENGTH (MEMORY_BURSTLENGTH),
.MIN_COL (MIN_COL),
.MIN_ROW (MIN_ROW),
.MIN_BANK (MIN_BANK),
.MIN_CS (MIN_CS)
) cmd_gen_inst (
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[1]),
//local input
.local_read_req (read_req_to_cmd_gen),
.local_write_req (avalon_write_req),
.processed_write_req (write_req_to_cmd_gen),
.local_size (size_to_cmd_gen),
.local_autopch_req (autopch_to_cmd_gen),
.local_addr (addr_to_cmd_gen),
.local_multicast (multicast_to_cmd_gen),
//input from CSR
.addr_order (addr_order),
.col_width_from_csr (col_width_from_csr ),
.row_width_from_csr (row_width_from_csr ),
.bank_width_from_csr (bank_width_from_csr),
.cs_width_from_csr (cs_width_from_csr),
//misc
.ready_out (ready_from_cmd_gen),
.ready_in (internal_ready),
//output
.read_req (read_req_from_cmd_gen),
.write_req (write_req_from_cmd_gen),
.size (size_from_cmd_gen),
.autopch_req (autopch_from_cmd_gen),
.cs_addr (cs_addr_from_cmd_gen),
.bank_addr (bank_addr_from_cmd_gen),
.row_addr (row_addr_from_cmd_gen),
.col_addr (col_addr_from_cmd_gen),
.multicast (multicast_from_cmd_gen)
);
//================= End of instantiation of alt_ddrx_cmd_gen ======================
//======================= Instantiation of alt_ddrx_cmd_queue ===========================
alt_ddrx_cmd_queue #(
.MEM_IF_CSR_COL_WIDTH (MEM_IF_CSR_COL_WIDTH ),
.MEM_IF_CSR_ROW_WIDTH (MEM_IF_CSR_ROW_WIDTH ),
.MEM_IF_CSR_BANK_WIDTH (MEM_IF_CSR_BANK_WIDTH ),
.MEM_IF_CSR_CS_WIDTH (MEM_IF_CSR_CS_WIDTH ),
.CTL_CMD_QUEUE_DEPTH (CTL_CMD_QUEUE_DEPTH),
.CTL_LOOK_AHEAD_DEPTH (CTL_LOOK_AHEAD_DEPTH),
.MEM_IF_ROW_WIDTH (MEM_IF_ROW_WIDTH),
.MEM_IF_COL_WIDTH (MEM_IF_COL_WIDTH),
.MEM_IF_BA_WIDTH (MEM_IF_BA_WIDTH),
.MEM_IF_CHIP_BITS (MEM_IF_CHIP_BITS),
.LOCAL_ADDR_WIDTH (INTERNAL_ADDR_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.ENABLE_BURST_MERGE (ENABLE_BURST_MERGE),
.MIN_COL (MIN_COL),
.MIN_ROW (MIN_ROW),
.MIN_BANK (MIN_BANK),
.MIN_CS (MIN_CS)
) cmd_queue_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n[2] ),
.read_req_to_cmd_queue (read_req_from_cmd_gen),
.write_req_to_cmd_queue (write_req_from_cmd_gen),
.local_size (size_from_cmd_gen ),
.local_autopch_req (autopch_from_cmd_gen ),
.local_cs_addr (cs_addr_from_cmd_gen ),
.local_bank_addr (bank_addr_from_cmd_gen ),
.local_row_addr (row_addr_from_cmd_gen ),
.local_col_addr (col_addr_from_cmd_gen ),
.local_multicast (multicast_from_cmd_gen ),
//input from State Machine
.fetch (fetch ),
.cmd_fifo_empty (cmd_fifo_empty ),
.cmd_fifo_full (cmd_fifo_full ),
//output
.cmd_fifo_wren (cmd_fifo_wren ),
.cmd0_is_a_read (cmd0_is_a_read ),
.cmd0_is_a_write (cmd0_is_a_write ),
.cmd0_autopch_req (cmd0_autopch_req ),
.cmd0_burstcount (cmd0_burstcount ),
.cmd0_chip_addr (cmd0_chip_addr ),
.cmd0_row_addr (cmd0_row_addr ),
.cmd0_bank_addr (cmd0_bank_addr ),
.cmd0_col_addr (cmd0_col_addr ),
.cmd0_is_valid (cmd0_is_valid ),
.cmd0_multicast_req (cmd0_multicast_req ),
.cmd1_is_a_read (cmd1_is_a_read ),
.cmd1_is_a_write (cmd1_is_a_write ),
.cmd1_chip_addr (cmd1_chip_addr ),
.cmd1_row_addr (cmd1_row_addr ),
.cmd1_bank_addr (cmd1_bank_addr ),
.cmd1_is_valid (cmd1_is_valid ),
.cmd1_multicast_req (cmd1_multicast_req ),
.cmd2_is_a_read (cmd2_is_a_read ),
.cmd2_is_a_write (cmd2_is_a_write ),
.cmd2_chip_addr (cmd2_chip_addr ),
.cmd2_row_addr (cmd2_row_addr ),
.cmd2_bank_addr (cmd2_bank_addr ),
.cmd2_is_valid (cmd2_is_valid ),
.cmd2_multicast_req (cmd2_multicast_req ),
.cmd3_is_a_read (cmd3_is_a_read ),
.cmd3_is_a_write (cmd3_is_a_write ),
.cmd3_chip_addr (cmd3_chip_addr ),
.cmd3_row_addr (cmd3_row_addr ),
.cmd3_bank_addr (cmd3_bank_addr ),
.cmd3_is_valid (cmd3_is_valid ),
.cmd3_multicast_req (cmd3_multicast_req ),
.cmd4_is_a_read (cmd4_is_a_read ),
.cmd4_is_a_write (cmd4_is_a_write ),
.cmd4_chip_addr (cmd4_chip_addr ),
.cmd4_row_addr (cmd4_row_addr ),
.cmd4_bank_addr (cmd4_bank_addr ),
.cmd4_is_valid (cmd4_is_valid ),
.cmd4_multicast_req (cmd4_multicast_req ),
.cmd5_is_a_read (cmd5_is_a_read ),
.cmd5_is_a_write (cmd5_is_a_write ),
.cmd5_chip_addr (cmd5_chip_addr ),
.cmd5_row_addr (cmd5_row_addr ),
.cmd5_bank_addr (cmd5_bank_addr ),
.cmd5_is_valid (cmd5_is_valid ),
.cmd5_multicast_req (cmd5_multicast_req ),
.cmd6_is_a_read (cmd6_is_a_read ),
.cmd6_is_a_write (cmd6_is_a_write ),
.cmd6_chip_addr (cmd6_chip_addr ),
.cmd6_row_addr (cmd6_row_addr ),
.cmd6_bank_addr (cmd6_bank_addr ),
.cmd6_is_valid (cmd6_is_valid ),
.cmd6_multicast_req (cmd6_multicast_req ),
.cmd7_is_a_read (cmd7_is_a_read ),
.cmd7_is_a_write (cmd7_is_a_write ),
.cmd7_chip_addr (cmd7_chip_addr ),
.cmd7_row_addr (cmd7_row_addr ),
.cmd7_bank_addr (cmd7_bank_addr ),
.cmd7_is_valid (cmd7_is_valid ),
.cmd7_multicast_req (cmd7_multicast_req )
);
//================= End of instantiation of alt_ddrx_cmd_queue ======================
assign internal_ready = (cmd_fifo_full == 1'b0) & (wdata_fifo_full == 1'b0) & (gate_ready_in_reset == 1'b1);
assign local_init_done = ctl_cal_success & ~ctl_cal_fail;
//registered gate_ready_in_reset
always @(posedge ctl_clk or negedge ctl_reset_n[4]) begin
if (~ctl_reset_n[4]) begin
gate_ready_in_reset <= 1'b0;
end
else begin
gate_ready_in_reset <= 1'b1;
end
end
generate if(LOCAL_IF_TYPE == "AVALON") begin
assign local_wdata_req = 1'b0;
assign write_req_to_wfifo = avalon_write_req;
assign read_req_to_cmd_gen = avalon_read_req;
assign be_to_wfifo = avalon_be;
assign wdata_to_wfifo = avalon_wdata;
assign addr_to_cmd_gen = avalon_addr;
assign size_to_cmd_gen = avalon_size;
assign multicast_to_cmd_gen = avalon_multicast;
assign autopch_to_cmd_gen = avalon_autopch_req;
if (CTL_HRB_ENABLED == 0) begin
reg prolong_burstbegin;
assign write_req_to_cmd_gen = avalon_write_req & (avalon_burstbegin | prolong_burstbegin);
// Removed reset logic in order to capture burst begin signal when request is issued before internal resynced reset signal de-asserted
always @(posedge ctl_clk) begin
//To detect the case where internal_ready gone low at the start of the burst.
//Burst begin gone high for one clock cycle only, so we need to manually prolong
//burst begin signal until internal_ready goes high.
if(ready_from_cmd_gen == 1'b0 & local_write_req == 1'b1)begin
if(avalon_burstbegin == 1'b1) begin
prolong_burstbegin <= 1'b1;
end
else
prolong_burstbegin <= prolong_burstbegin;
end
else if(ready_from_cmd_gen == 1'b1 & local_write_req == 1'b1)begin
prolong_burstbegin <= 1'b0;
end
end
end
else begin
assign write_req_to_cmd_gen = avalon_write_req & avalon_burstbegin;
end
//======================= Instantiation of alt_ddrx_avalon_if =========================
alt_ddrx_avalon_if #(
.INTERNAL_SIZE_WIDTH (INTERNAL_SIZE_WIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO),
.LOCAL_DATA_WIDTH (LOCAL_DATA_WIDTH),
.INTERNAL_DATA_WIDTH (INTERNAL_DATA_WIDTH),
.CTL_HRB_ENABLED (CTL_HRB_ENABLED ),
.LOCAL_ADDR_WIDTH (LOCAL_ADDR_WIDTH),
.INTERNAL_ADDR_WIDTH (INTERNAL_ADDR_WIDTH),
.LOCAL_SIZE_WIDTH (LOCAL_SIZE_WIDTH)
) avalon_if_inst (
// input
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n[3]),
.ctl_half_clk (ctl_half_clk),
.ctl_half_clk_reset_n (ctl_half_clk_reset_n),
.local_write_req (local_write_req),
.local_wdata (local_wdata),
.local_be (local_be),
.local_addr (local_addr),
.internal_ready (ready_from_cmd_gen),
.local_read_req (local_read_req),
.local_size (local_size),
.local_burstbegin (local_burstbegin),
.ecc_rdata (ecc_rdata),
.ecc_rdata_valid (ecc_rdata_valid ),
.ecc_rdata_error (ecc_rdata_error),
.local_multicast (int_local_multicast),
.local_autopch_req (local_autopch_req),
//output
.avalon_wdata (avalon_wdata),
.avalon_be (avalon_be),
.avalon_write_req (avalon_write_req),
.avalon_read_req (avalon_read_req),
.avalon_addr (avalon_addr),
.avalon_size (avalon_size),
.local_ready (local_ready),
.avalon_burstbegin (avalon_burstbegin),
.local_rdata (local_rdata),
.local_rdata_error (local_rdata_error),
.local_rdata_valid (local_rdata_valid),
.avalon_multicast (avalon_multicast),
.avalon_autopch_req (avalon_autopch_req)
);
//======================= End of Instantiation of alt_ddrx_avalon_if ===================
end
else begin //native mode
reg wdata_req;
reg wdata_req_r;
reg [WDATA_BEATS_WIDTH-1:0] beats_to_ask_for;
assign local_wdata_req = wdata_req;
assign write_req_to_cmd_gen = local_write_req;
assign write_req_to_wfifo = wdata_req_r;
assign read_req_to_cmd_gen = local_read_req;
assign be_to_wfifo = local_be;
assign wdata_to_wfifo = local_wdata;
assign addr_to_cmd_gen = local_addr;
assign size_to_cmd_gen = local_size;
assign multicast_to_cmd_gen = int_local_multicast;
assign autopch_to_cmd_gen = local_autopch_req;
//used only in native mode
always @(posedge ctl_clk or negedge ctl_reset_n[4]) begin
if (~ctl_reset_n[4]) begin
wdata_req <= 1'b0; //request signal to user
wdata_req_r <= 1'b0; //request signal to wdata fifo
beats_to_ask_for <= 0;
end
else begin
wdata_req_r <= wdata_req;
if ((internal_ready == 1'b1) & (local_write_req == 1'b1) & (LOCAL_IF_TYPE == "NATIVE")) begin
if (wdata_req == 1'b1) begin
wdata_req <= beats_to_ask_for > 0;
beats_to_ask_for <= beats_to_ask_for + local_size - 1;
end
else begin
if (local_init_done == 1'b1) begin
wdata_req <= 1'b1;
end
beats_to_ask_for <= beats_to_ask_for + local_size;
end
end
else if ((beats_to_ask_for > 0) & (wdata_req == 1'b1) & (local_init_done == 1'b1)) begin
beats_to_ask_for <= beats_to_ask_for - 1;
wdata_req <= beats_to_ask_for > 1;
end
else begin
wdata_req <= 1'b0;
beats_to_ask_for <= beats_to_ask_for;
end
end
end
end
endgenerate
generate
if ((CTL_CSR_ENABLED == 1) && (MEM_TYPE == "DDR3")) begin
assign int_local_multicast = (regdimm_enable == 1) ? 0 : local_multicast ;
end
else if ((CTL_REGDIMM_ENABLED == 1) && (MEM_TYPE == "DDR3")) begin
assign int_local_multicast = 0;
end
else begin
assign int_local_multicast = local_multicast ;
end
endgenerate
endmodule |
module ddr2_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module ddr2_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire5;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [4:4] sub_wire7 = sub_wire0[4:4];
wire [0:0] sub_wire6 = sub_wire0[0:0];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire locked = sub_wire5;
wire c0 = sub_wire6;
wire c4 = sub_wire7;
wire phasedone = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire0),
.locked (sub_wire5),
.phasedone (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "833",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 2,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 2,
altpll_component.clk3_phase_shift = "-1250",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 2,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 1,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 2,
altpll_component.clk5_phase_shift = "0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 78,
altpll_component.width_clock = 7;
endmodule |
module alt_ddrx_wdata_fifo
#(parameter WDATA_BEATS_WIDTH = 9,
LOCAL_DATA_WIDTH = 32,
LOCAL_SIZE_WIDTH = 6,
DWIDTH_RATIO = 2,
FAMILY = "Stratix"
)(
// input
ctl_clk,
ctl_reset_n,
write_req_to_wfifo,
wdata_to_wfifo,
be_to_wfifo,
wdata_fifo_read,
//output
wdata_fifo_full,
wdata_fifo_wdata,
wdata_fifo_be,
beats_in_wfifo
);
localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8;
localparam LOCAL_WFIFO_Q_WIDTH = LOCAL_DATA_WIDTH + LOCAL_BE_WIDTH;
input ctl_clk; // controller clock
input ctl_reset_n; // controller reset_n, synchronous to ctl_clk
input write_req_to_wfifo;
input wdata_fifo_read;
input [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
input [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
output [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
output [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
output wdata_fifo_full;
output [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
wire ctl_clk;
wire ctl_reset_n;
wire reset;
wire write_req_to_wfifo;
wire wdata_fifo_read;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_to_wfifo;
wire [LOCAL_BE_WIDTH-1 : 0] be_to_wfifo;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_data;
wire [LOCAL_WFIFO_Q_WIDTH-1 : 0] wfifo_q;
wire wdata_fifo_full;
wire [LOCAL_DATA_WIDTH-1 : 0] wdata_fifo_wdata;
wire [LOCAL_BE_WIDTH-1 : 0] wdata_fifo_be;
reg [WDATA_BEATS_WIDTH-1 : 0] beats_in_wfifo;
assign wfifo_data = {be_to_wfifo,wdata_to_wfifo};
assign wdata_fifo_be = wfifo_q[LOCAL_WFIFO_Q_WIDTH-1 : LOCAL_DATA_WIDTH];
assign wdata_fifo_wdata = wfifo_q[LOCAL_DATA_WIDTH-1 : 0];
assign reset = !ctl_reset_n; // scfifo has an active high async reset
//We fix the fifo depth to 256 in order to match the depth of the M9k memories that has the maximum data width (256 depth x 36 width),
//by doing this, we can minimize the usage of M9k.
//Currently, we need at lease 18 M9k (256 x 36)
//Calculation : Maximum data width that we support, 72 (with ecc) * 8 (quarter rate) = 576, byteen bit = 576 / 8 = 72, LOCAL_WFIFO_Q_WIDTH = 576 + 72 = 648
//Number of M9k we need = 648 / 36 = 18.
scfifo #(
.intended_device_family (FAMILY),
.lpm_width (LOCAL_WFIFO_Q_WIDTH), // one BE per byte, not per DQS
.lpm_numwords (256),
.lpm_widthu (log2 (256)),
.almost_full_value (256-16), // a bit of slack to avoid overflowing
.lpm_type ("scfifo"),
.lpm_showahead ("OFF"), // Always OFF at the moment
.overflow_checking ("OFF"),
.underflow_checking ("OFF"),
.use_eab ("ON"),
.add_ram_output_register ("ON") // Always ON at the moment
) wdata_fifo (
.rdreq (wdata_fifo_read),
.aclr (reset),
.clock (ctl_clk),
.wrreq (write_req_to_wfifo),
.data (wfifo_data),
.full (),
.q (wfifo_q),
.sclr (1'b0),
.usedw (),
.empty (),
.almost_full (wdata_fifo_full),
.almost_empty ()
);
// Tell the state machine how many data entry is in the write data fifo
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (~ctl_reset_n) begin
beats_in_wfifo <= 0;
end
else if(write_req_to_wfifo) begin
if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo;
end
else begin
beats_in_wfifo <= beats_in_wfifo + 1'b1;
end
end
else if(wdata_fifo_read) begin
beats_in_wfifo <= beats_in_wfifo - 1'b1;
end
end
function integer log2;
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule |
module alt_ddrx_odt_gen
# (parameter
DWIDTH_RATIO = 2,
MEM_TYPE = "DDR2",
MEM_IF_CS_WIDTH = 1,
MEM_IF_ODT_WIDTH = 1,
CTL_ODT_ENABLED = 1,
CTL_OUTPUT_REGD = 0,
MEM_IF_CS_PER_DIMM = 1,
MEMORY_BURSTLENGTH = 8,
ADD_LAT_BUS_WIDTH = 3,
CAS_WR_LAT_BUS_WIDTH= 4,
CTL_REGDIMM_ENABLED = 0,
TCL_BUS_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
mem_tcl,
mem_cas_wr_lat,
mem_add_lat,
// state machine command inputs
do_write,
do_read,
// address information
to_chip, // active high input (one hot)
// ODT output
afi_odt
);
input ctl_clk;
input ctl_reset_n;
input [TCL_BUS_WIDTH-1:0] mem_tcl;
input [CAS_WR_LAT_BUS_WIDTH-1:0] mem_cas_wr_lat;
input [ADD_LAT_BUS_WIDTH-1:0] mem_add_lat;
// state machine command inputs
input do_write;
input do_read;
// address information
input [MEM_IF_CS_WIDTH-1:0] to_chip;
// ODT output
output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt;
wire [MEM_IF_ODT_WIDTH - 1:0] write_to_this_chip;
wire [MEM_IF_ODT_WIDTH - 1:0] read_to_this_chip;
wire [MEM_IF_ODT_WIDTH - 1:0] odt_bus_l; // second half
wire [MEM_IF_ODT_WIDTH - 1:0] odt_bus_h; // first half
wire [MEM_IF_ODT_WIDTH - 1:0] correct_odt_l;
wire [MEM_IF_ODT_WIDTH - 1:0] correct_odt_h;
wire do_write;
wire do_read;
wire [MEM_IF_CS_WIDTH-1:0] to_chip;
reg do_write_r;
reg do_read_r;
reg [MEM_IF_CS_WIDTH-1:0] to_chip_r;
reg [MEM_IF_CS_WIDTH-1:0] to_chip_gen;
// generate block for *_r signals, these signals are only used by DDR3 ODT block
// DDR2 ODT block uses the original signal and register them inside their blocks
generate
if (CTL_OUTPUT_REGD == 1)
begin
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_write_r <= 0;
do_read_r <= 0;
to_chip_r <= 0;
end
else
begin
do_write_r <= do_write;
do_read_r <= do_read;
to_chip_r <= to_chip;
end
end
end
else
begin
always @(do_write)
do_write_r <= do_write;
always @(do_read)
do_read_r <= do_read;
always @(to_chip)
to_chip_r <= to_chip;
end
endgenerate
generate
if (CTL_ODT_ENABLED == 1)
begin
if (DWIDTH_RATIO == 2)
assign afi_odt = correct_odt_l;
else
assign afi_odt = {correct_odt_h,correct_odt_l};
end
else
assign afi_odt = {(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)){1'b0}};
endgenerate
/*
DDR3
four chip selects odt scheme, for two ranks per dimm configuration
.---------------------------------------++---------------------------------------.
| write to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || 1 | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | 1 | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | 1 |
'---------+---------+---------+---------++---------+---------+---------+---------'
.---------------------------------------++---------------------------------------.
| read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chip 0 | chip 1 | chip 2 | chip 3 || chip 0 | chip 1 | chip 2 | chip 3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | |
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
generate
if (MEM_TYPE == "DDR3")
begin
assign correct_odt_l = odt_bus_l;
assign correct_odt_h = odt_bus_h;
end
endgenerate
/*
DDR2
four or more chip selects odt scheme, assumes two ranks per dimm
.---------------------------------------++---------------------------------------.
| write/read to || odt to |
+---------+---------+---------+---------++---------+---------+---------+---------+
| chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 || chipJ+0 | chipJ+1 | chipJ+2 | chipJ+3 |
|=--------+---------+---------+---------++---------+---------+---------+--------=|
| 1 | | | || | | 1 | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | 1 | | || | | | 1 |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | 1 | || 1 | | | |
+---------+---------+---------+---------++---------+---------+---------+---------+
| | | | 1 || | 1 | | |
'---------+---------+---------+---------++---------+---------+---------+---------'
*/
generate
if (MEM_TYPE == "DDR2")
begin
assign correct_odt_l = odt_bus_l;
assign correct_odt_h = odt_bus_h;
end
endgenerate
generate
if (MEM_TYPE == "DDR3")
begin
integer i;
integer j;
always @(*)
begin
if (MEM_IF_CS_PER_DIMM == 1)
begin
if (MEM_IF_ODT_WIDTH == 1)
begin
if (do_read_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b0}};
else
to_chip_gen <= to_chip_r;
end
else if (MEM_IF_ODT_WIDTH == 2)
begin
if (do_read_r)
to_chip_gen <= ~to_chip_r;
else
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
end
else // when 2 rank per slot ODT width can only be 2 or more, so this is for 4 and 8
begin
if (do_read_r)
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : H
for (j = 0; j < 4; j = j + 1)
begin : G
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip_r[(i*4)+j];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip_r[(i*4)+j];
end
end
end
else // write
begin
if (&to_chip_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : L
for (j = 0; j < 4; j = j + 1)
begin : K
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j+2)];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j-2)];
end
end
end
end
end
end
else if (MEM_IF_CS_PER_DIMM == 2)
begin
if (MEM_IF_ODT_WIDTH == 2)
begin
if (do_read_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b0}};
else
begin
if (&to_chip_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
to_chip_gen <= to_chip_r;
end
end
else // when 2 rank per slot ODT width can only be 2 or more, so this is for 4 and 8
begin
if (do_read_r)
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : N
for (j = 0; j < 4; j = j + 1)
begin : M
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip_r[(i*4)+j];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip_r[(i*4)+j];
end
end
end
else // write
begin
if (&to_chip_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : P
for (j = 0; j < 4; j = j + 1)
begin : O
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j+2)];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j-2)];
end
end
end
end
end
end
else // 4 ranks per slot
begin
if (MEM_IF_ODT_WIDTH == 4)
begin
if (do_read_r)
to_chip_gen <= 0;
else
begin
if (&to_chip_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
to_chip_gen <= to_chip_r;
end
end
else // when 4 rank per slot ODT width can only be 4 or more, so this is for 8
begin
if (do_read_r)
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/8; i = i + 1)
begin : R
for (j = 0; j < 8; j = j + 1)
begin : Q
if (j < 4)
to_chip_gen[(i*4)+(j+4)] <= to_chip_r[(i*4)+j];
else
to_chip_gen[(i*4)+(j-4)] <= to_chip_r[(i*4)+j];
end
end
end
else // write
begin
if (&to_chip_r)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/8; i = i + 1)
begin : T
for (j = 0; j < 8; j = j + 1)
begin : S
if (j < 4)
to_chip_gen[(i*4)+(j+4)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j+4)];
else
to_chip_gen[(i*4)+(j-4)] <= to_chip_r[(i*4)+j] | to_chip_r[(i*4)+(j-4)];
end
end
end
end
end
end
end
genvar I;
for (I = 0; I < MEM_IF_ODT_WIDTH; I = I + 1)
begin : F
assign write_to_this_chip[I] = do_write_r & to_chip_gen[I];
assign read_to_this_chip[I] = do_read_r & to_chip_gen[I];
alt_ddrx_ddr3_odt_gen # (
.DWIDTH_RATIO (DWIDTH_RATIO),
.TCL_BUS_WIDTH (TCL_BUS_WIDTH),
.CAS_WR_LAT_BUS_WIDTH (CAS_WR_LAT_BUS_WIDTH)
) odt_gen_inst (
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.mem_tcl (mem_tcl),
.mem_cas_wr_lat (mem_cas_wr_lat),
.do_write (write_to_this_chip[I]),
.do_read (read_to_this_chip[I]),
.int_odt_l (odt_bus_l[I]),
.int_odt_h (odt_bus_h[I])
);
end
end
else
begin
integer i;
integer j;
always @(*)
begin
if (MEM_IF_CS_PER_DIMM == 1)
begin
if (MEM_IF_ODT_WIDTH == 1)
begin
if (do_read)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b0}};
else
to_chip_gen <= to_chip;
end
else if (MEM_IF_ODT_WIDTH == 2)
to_chip_gen <= ~to_chip;
else // when 2 rank per slot ODT width can only be 2 or more, so this is for 4 and 8
begin
if (&to_chip)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : L
for (j = 0; j < 4; j = j + 1)
begin : K
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip[(i*4)+j];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip[(i*4)+j];
end
end
end
end
end
else if (MEM_IF_CS_PER_DIMM == 2)
begin
if (MEM_IF_ODT_WIDTH == 2)
begin
if (do_read)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b0}};
else
begin
if (&to_chip)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
to_chip_gen <= to_chip;
end
end
else // when 2 rank per slot ODT width can only be 2 or more, so this is for 4 and 8
begin
if (&to_chip)
to_chip_gen <= {MEM_IF_CS_WIDTH{1'b1}};
else
begin
for (i = 0; i < MEM_IF_ODT_WIDTH/4; i = i + 1)
begin : P
for (j = 0; j < 4; j = j + 1)
begin : O
if (j < 2)
to_chip_gen[(i*4)+(j+2)] <= to_chip[(i*4)+j];
else
to_chip_gen[(i*4)+(j-2)] <= to_chip[(i*4)+j];
end
end
end
end
end
end
genvar I;
for (I = 0; I < MEM_IF_ODT_WIDTH; I = I + 1)
begin : F
assign write_to_this_chip[I] = do_write & to_chip_gen[I];
assign read_to_this_chip[I] = do_read & to_chip_gen[I];
alt_ddrx_ddr2_odt_gen # (
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEMORY_BURSTLENGTH (MEMORY_BURSTLENGTH),
.ADD_LAT_BUS_WIDTH (ADD_LAT_BUS_WIDTH),
.CTL_OUTPUT_REGD (CTL_OUTPUT_REGD),
.TCL_BUS_WIDTH (TCL_BUS_WIDTH)
) odt_gen_inst (
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.mem_tcl (mem_tcl),
.mem_add_lat (mem_add_lat),
.do_write (write_to_this_chip[I]),
.do_read (read_to_this_chip[I]),
.int_odt_l (odt_bus_l[I]),
.int_odt_h (odt_bus_h[I])
);
end
end
endgenerate
endmodule |
module alt_ddrx_clock_and_reset #
( parameter
CTL_RESET_SYNC_STAGES = 4,
CTL_NUM_RESET_OUTPUT = 1,
CTL_HALF_RESET_SYNC_STAGES = 4,
CTL_HALF_NUM_RESET_OUTPUT = 1
)
(
// Inputs
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
// Outputs
resynced_ctl_reset_n,
resynced_ctl_half_clk_reset_n
);
// Inputs
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
// Outputs
output [CTL_NUM_RESET_OUTPUT - 1 : 0] resynced_ctl_reset_n;
output [CTL_HALF_NUM_RESET_OUTPUT - 1 : 0] resynced_ctl_half_clk_reset_n;
alt_ddrx_reset_sync #(
.RESET_SYNC_STAGES (CTL_RESET_SYNC_STAGES),
.NUM_RESET_OUTPUT (CTL_NUM_RESET_OUTPUT)
) reset_sync_inst (
.reset_n (ctl_reset_n),
.clk (ctl_clk),
.reset_n_sync (resynced_ctl_reset_n)
);
alt_ddrx_reset_sync #(
.RESET_SYNC_STAGES (CTL_HALF_RESET_SYNC_STAGES),
.NUM_RESET_OUTPUT (CTL_HALF_NUM_RESET_OUTPUT)
) half_reset_sync_inst (
.reset_n (ctl_half_clk_reset_n),
.clk (ctl_half_clk),
.reset_n_sync (resynced_ctl_half_clk_reset_n)
);
endmodule |
module alt_ddrx_avalon_if
#(parameter INTERNAL_SIZE_WIDTH = 7,
LOCAL_SIZE_WIDTH = 6,
CTL_HRB_ENABLED = 0,
LOCAL_ADDR_WIDTH = 28,
INTERNAL_ADDR_WIDTH = 33,
DWIDTH_RATIO = 2,
LOCAL_DATA_WIDTH = 64,
INTERNAL_DATA_WIDTH = 32
)
(
// input
ctl_clk,
ctl_reset_n,
ctl_half_clk ,
ctl_half_clk_reset_n ,
local_write_req,
local_wdata,
local_be,
local_addr,
internal_ready,
local_read_req,
local_size,
local_burstbegin,
ecc_rdata,
ecc_rdata_valid,
ecc_rdata_error,
local_multicast,
local_autopch_req,
//output
avalon_wdata,
avalon_be,
avalon_addr,
avalon_write_req,
avalon_read_req,
avalon_size,
avalon_burstbegin,
local_ready,
local_rdata,
local_rdata_error,
local_rdata_valid,
avalon_multicast,
avalon_autopch_req
);
localparam LOCAL_BE_WIDTH = LOCAL_DATA_WIDTH/8;
localparam INTERNAL_BE_WIDTH = INTERNAL_DATA_WIDTH/8;
localparam AVM_ADDR_WIDTH = LOCAL_ADDR_WIDTH + log2(LOCAL_BE_WIDTH);
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
input local_write_req;
input [LOCAL_DATA_WIDTH -1 : 0] local_wdata;
input [LOCAL_BE_WIDTH -1 : 0] local_be;
input [LOCAL_ADDR_WIDTH -1 : 0] local_addr;
input internal_ready;
input local_read_req;
input [INTERNAL_DATA_WIDTH -1 : 0] ecc_rdata;
input [DWIDTH_RATIO/2-1:0] ecc_rdata_valid;
input ecc_rdata_error;
input [LOCAL_SIZE_WIDTH-1:0] local_size;
input local_burstbegin;
input local_multicast;
input local_autopch_req;
output [INTERNAL_DATA_WIDTH -1 : 0] avalon_wdata;
output [INTERNAL_BE_WIDTH -1 : 0] avalon_be;
output [INTERNAL_ADDR_WIDTH - 1 : 0]avalon_addr;
output avalon_write_req;
output avalon_read_req;
output [INTERNAL_SIZE_WIDTH-1:0] avalon_size;
output avalon_burstbegin;
output local_ready;
output [LOCAL_DATA_WIDTH -1 : 0] local_rdata;
output local_rdata_valid;
output local_rdata_error;
output avalon_multicast;
output avalon_autopch_req;
generate if (CTL_HRB_ENABLED == 1) begin
wire avs_chipselect;
wire [LOCAL_DATA_WIDTH -1 : 0] avs_readdata;
wire [LOCAL_DATA_WIDTH -1 : 0] avs_writedata;
wire avs_waitrequest;
wire avm_write;
wire avm_read;
wire [AVM_ADDR_WIDTH - 1 : 0] avm_address;
reg [LOCAL_ADDR_WIDTH -1 : 0] avs_address;
reg [2:0] state;
reg [INTERNAL_SIZE_WIDTH-1 : 0] burstcount;
reg [INTERNAL_SIZE_WIDTH-1:0] internal_size;
reg [INTERNAL_SIZE_WIDTH-1:0] internal_size_r;
reg [INTERNAL_SIZE_WIDTH-1:0] avalon_avm_size;
wire [2:0] avalon_avm_count;
reg [2:0] avalon_avm_count_r;
reg avalon_avs_toggle;
reg avalon_avm_toggle;
reg avalon_avm_toggle_r;
wire avalon_avs_clk_ph;
reg internal_multicast;
reg internal_multicast_r;
reg internal_autopch;
reg internal_autopch_r;
reg avalon_avm_multicast;
reg avalon_avm_autopch;
assign local_ready = !avs_waitrequest;
assign avalon_write_req = avm_write & internal_ready;
assign avalon_read_req = avm_read & internal_ready;
assign avalon_addr = {avm_address[AVM_ADDR_WIDTH - 1 : log2(LOCAL_BE_WIDTH)],1'b0};
assign avs_chipselect = local_read_req|local_write_req;
//burst adaptor logic
assign avalon_burstbegin = (burstcount == 0);
assign avalon_size = avalon_avm_size;
assign avalon_multicast = avalon_avm_multicast;
assign avalon_autopch_req = avalon_avm_autopch;
assign avalon_avs_clk_ph = avalon_avm_toggle ^ avalon_avm_toggle_r;
always @(posedge ctl_half_clk or negedge ctl_reset_n)
if (~ctl_reset_n)
avalon_avs_toggle <= 1'b0;
else
avalon_avs_toggle <= ~avalon_avs_toggle;
always @(posedge ctl_clk or negedge ctl_reset_n)
if (~ctl_reset_n)
begin
avalon_avm_toggle <= 1'b0;
avalon_avm_toggle_r <= 1'b0;
end
else
begin
avalon_avm_toggle <= avalon_avs_toggle;
avalon_avm_toggle_r <= avalon_avm_toggle;
end
always @(avalon_avm_count_r,internal_size,internal_multicast,internal_autopch,internal_size_r,internal_multicast_r,internal_autopch_r) begin
if(avalon_avm_count_r >=3) begin
avalon_avm_size <= internal_size_r;
avalon_avm_multicast <= internal_multicast_r;
avalon_avm_autopch <= internal_autopch_r;
end
else begin
avalon_avm_size <= internal_size;
avalon_avm_multicast <= internal_multicast;
avalon_avm_autopch <= internal_autopch;
end
end
assign avalon_avm_count = avalon_avm_count_r + (((local_write_req | local_read_req) & local_ready & avalon_avs_clk_ph) ? 3'd2 : 3'd0)
- (avalon_write_req ? 3'd1 : 3'd0)
- (avalon_read_req ? 3'd2 : 3'd0);
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
avalon_avm_count_r <= 0;
end
else begin
avalon_avm_count_r <= avalon_avm_count;
end
end
always @(posedge ctl_half_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
internal_size <= 0;
internal_size_r <= 0;
internal_multicast <= 0;
internal_multicast_r <= 0;
internal_autopch <= 0;
internal_autopch_r <= 0;
end
else if((local_write_req | local_read_req) & local_ready) begin
internal_size <= {local_size,1'b0}; // multiply local_size by 2
internal_size_r <= internal_size;
internal_multicast <= local_multicast;
internal_multicast_r <= internal_multicast;
internal_autopch <= local_autopch_req;
internal_autopch_r <= internal_autopch;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n) begin
burstcount <= 0;
state <= 3'd0;
end
else begin
case (state)
3'd0: begin
if(avalon_write_req) begin
burstcount <= burstcount + 1;
state <= 3'd1;
end
end
3'd1: begin
if(avalon_write_req) begin
if(burstcount == avalon_avm_size -1) begin
burstcount <= 0;
state <= 3'd0;
end
else begin
burstcount <= burstcount + 1;
end
end
end
endcase
end
end
altera_avalon_half_rate_bridge #(
.AVM_DATA_WIDTH (INTERNAL_DATA_WIDTH),
.AVM_ADDR_WIDTH (AVM_ADDR_WIDTH),
.AVM_BYTE_WIDTH (INTERNAL_BE_WIDTH),
.AVS_DATA_WIDTH (LOCAL_DATA_WIDTH),
.AVS_ADDR_WIDTH (LOCAL_ADDR_WIDTH),
.AVS_BYTE_WIDTH (LOCAL_BE_WIDTH)
) HRB_inst (
.avs_reset_n (ctl_reset_n),
.avm_reset_n (ctl_half_clk_reset_n),
// Avalon slave input
.avs_clk (ctl_half_clk ),
.avs_chipselect (avs_chipselect ),
.avs_address (local_addr ),
.avs_write (local_write_req ),
.avs_read (local_read_req ),
.avs_byteenable (local_be ),
.avs_writedata (local_wdata ),
// Avalon slave output
.avs_readdata (local_rdata ),
.avs_waitrequest (avs_waitrequest ),
.avs_readdatavalid (local_rdata_valid ),
// Avalon master input
.avm_clk (ctl_clk ),
.avm_readdata (ecc_rdata ),
.avm_waitrequest (!internal_ready ),
.avm_readdatavalid (ecc_rdata_valid[0] ),
// Avalon master output
.avm_burstcount (), //not going to use it, because burstcount in the HRB is fixed at 2
.avm_address (avm_address ),
.avm_write (avm_write ),
.avm_read (avm_read ),
.avm_byteenable (avalon_be ),
.avm_writedata (avalon_wdata )
);
end
else begin
assign avalon_write_req = local_write_req & internal_ready;
assign avalon_wdata = local_wdata;
assign avalon_be = local_be;
assign avalon_read_req = local_read_req & internal_ready;
assign local_rdata = ecc_rdata;
assign local_rdata_valid = ecc_rdata_valid[0];
assign local_rdata_error = ecc_rdata_error;
assign avalon_addr = local_addr;
assign avalon_size = local_size;
assign avalon_burstbegin = local_burstbegin;
assign local_ready = internal_ready;
assign avalon_multicast = local_multicast;
assign avalon_autopch_req = local_autopch_req;
end
endgenerate
function integer log2; //constant function
input integer value;
begin
for (log2=0; value>0; log2=log2+1)
value = value>>1;
log2 = log2 - 1;
end
endfunction
endmodule |
module parser_h(
input ip_src_valid,
input [130:0] ip_src,
input clk,
input reset,
input buf_addr_full,
input cdp2um_data_valid,
input [138:0] cdp2um_data,
output reg um2cdp_tx_enable,
output reg um2cdp_path,
output reg pkt_head_valid,
output reg [138:0] pkt_head,
output reg pkt_payload_valid,
output reg [138:0] pkt_payload,
output reg pkt_metadata_valid,
output reg [359:0] pkt_metadata, //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
output reg [7:0] input_count,
output reg [7:0] p0_a_count,
output reg [7:0] p0_b_count,
output reg [7:0] input_nobody_count
);
reg [15:0] identify;
//---reg---//
reg [7:0] ingress;
reg [127:0] rloc_src,eid_dst;
reg [71:0] metadata_parser;
reg [7:0] ip_protocol;
reg [127:0] ip_src_1,ip_src_2,ip_src_3,ip_src_4,ip_src_5,ip_src_6,ip_src_7,ip_src_8;
reg [127:0] ip_src_match;
//------state------//
reg [3:0] parser_state;
parameter idle = 4'd0,
parser_ip_src = 4'd1,
parser_ip_dst = 4'd2,
parser_udp = 4'd3,
parser_lisp_flag = 4'd4,
parser_eth_2 = 4'd5,
parser_eid_src = 4'd6,
parser_eid_dst = 4'd7,
parser_udp_2 = 4'd8,
trans_payload_notlisp = 4'd9,
trans_pkt_controller = 4'd10,
trans_payload = 4'd11,
discard = 4'd12,
discard_notlisp = 4'd13;
//-----------------state------------------//
reg cdp2um_state;
//-------------------cdp2um_state-------------------//
always @ (posedge clk or negedge reset)
if(!reset) begin
um2cdp_tx_enable <= 1'b1;
cdp2um_state <= 1'b0;
um2cdp_path <= 1'b0;
end
else begin
case(cdp2um_state)
1'b0:
begin
if((cdp2um_data_valid == 1'b0)&&(buf_addr_full == 1'b0))//zq0823
begin
um2cdp_tx_enable <= 1'b1;
cdp2um_state <= 1'b1;
end
else
begin
um2cdp_tx_enable <= 1'b0;
end
end
1'b1:
begin
if(cdp2um_data_valid == 1'b1)
begin
um2cdp_tx_enable <= 1'b0;
cdp2um_state <= 1'b0;
end
end
endcase
end
//----------------------parser_state-------------------------//
always @ (posedge clk or negedge reset)
if(!reset) begin
input_count <= 8'b0;
p0_a_count <= 8'b0;
p0_b_count <= 8'b0;
input_nobody_count <= 8'b0;
ingress <= 8'b0;
rloc_src <= 128'b0;
eid_dst <= 128'b0;
metadata_parser <= 72'b0;
pkt_metadata <= 360'b0;
pkt_metadata_valid <= 1'b0;
pkt_head_valid <= 1'b0;
pkt_head <= 139'b0;
pkt_payload_valid <= 1'b0;
pkt_payload <= 139'b0;
identify <= 16'b0;
ip_src_match <= 128'b0;
parser_state <= idle;
end
else begin
case(parser_state)
idle: begin
pkt_head_valid <= 1'b0;//zq0829
pkt_payload_valid <= 1'b0;
pkt_metadata_valid <= 1'b0;
if(cdp2um_data_valid == 1'b1)
begin
if((cdp2um_data[138:136] == 3'b101) && (cdp2um_data[31:16] == 16'h86dd))
begin
parser_state <= parser_ip_src;
ingress <= {4'b0,cdp2um_data[131:128]};
metadata_parser[63:48] <= cdp2um_data[15:0];
pkt_head_valid <= 1'b1;
pkt_head <= cdp2um_data;
end
else
begin
pkt_head_valid <= 1'b0;
parser_state <= discard;
end
end
else
begin
parser_state <= idle;
pkt_head_valid <= 1'b0;
end
end
parser_ip_src: begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
pkt_head_valid <= 1'b1;
rloc_src[127:48] <= cdp2um_data[79:0];
metadata_parser[47:0] <= cdp2um_data[127:80];
ip_protocol <= cdp2um_data[95:88];
case(ingress[2:0])
3'd0: ip_src_match <= ip_src_1;
3'd1: ip_src_match <= ip_src_2;
3'd2: ip_src_match <= ip_src_3;
3'd3: ip_src_match <= ip_src_4;
3'd4: ip_src_match <= ip_src_5;
3'd5: ip_src_match <= ip_src_6;
3'd6: ip_src_match <= ip_src_7;
3'd7: ip_src_match <= ip_src_8;
endcase
parser_state <= parser_ip_dst;
end
parser_ip_dst:
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
pkt_head_valid <= 1'b1;
rloc_src[47:0] <= cdp2um_data[127:80];
eid_dst[127:48] <= cdp2um_data[79:0];
parser_state <= parser_udp;
end
parser_udp:
begin
case(ingress[2:0])
3'd0://ingress==1;
begin
if({eid_dst[127:48],cdp2um_data[127:80]} != ip_src_1) begin //discard
pkt_metadata_valid <= 1'b1;
pkt_metadata <= {4'b1000,356'b0};
pkt_head_valid <= 1'b1;
if((cdp2um_data[138:136] == 3'b110) || (cdp2um_data_valid == 1'b0))
begin
pkt_head <={3'b110,cdp2um_data[135:0]};
parser_state <= idle;
end
else
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
parser_state <= trans_pkt_controller;
end
end
else
begin
if((ip_protocol == 8'd17) && (cdp2um_data[63:48]==16'd4341))//lisp
begin
parser_state <= parser_lisp_flag;
p0_a_count <= p0_a_count +1'b1;
pkt_head_valid <= 1'b1;
pkt_head <= {3'b100,cdp2um_data[135:0]};
pkt_metadata_valid <= 1'b0;
metadata_parser[71:64] <= {2'b11,6'b0};
end
else//discard
begin
pkt_metadata_valid <= 1'b1;
pkt_metadata <= {4'b1000,356'b0};
pkt_head_valid <= 1'b1;
if((cdp2um_data[138:136] == 3'b110) || (cdp2um_data_valid == 1'b0))
begin
pkt_head <={3'b110,cdp2um_data[135:0]};
parser_state <= idle;
end
else
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
parser_state <= trans_pkt_controller;
end
end
end
end
default:
begin
if({eid_dst[127:48],cdp2um_data[127:80]} == ip_src_match)
begin
pkt_metadata_valid <= 1'b1;
pkt_metadata <= {2'b01,358'b0};
pkt_head_valid <= 1'b1;
if((cdp2um_data[138:136] == 3'b110) || (cdp2um_data_valid == 1'b0))
begin
pkt_head <={3'b110,cdp2um_data[135:0]};
parser_state <= idle;
end
else
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
parser_state <= trans_pkt_controller;
end
end
else
begin
pkt_head_valid <= 1'b1;
if((cdp2um_data[138:136] == 3'b110) || (cdp2um_data_valid == 1'b0))
begin
pkt_head <={3'b110,cdp2um_data[135:0]};
pkt_metadata_valid <= 1'b1;
input_nobody_count <= input_nobody_count +1'b1;
pkt_metadata <= {4'h1,4'b0,16'b0,ingress,rloc_src,eid_dst,metadata_parser};
parser_state <= idle;
end
else
begin
pkt_head <= {3'b110,cdp2um_data[135:0]};
input_count <= 8'd1 + input_count;
parser_state <= trans_payload_notlisp;
end
end
end
endcase
end
parser_lisp_flag:
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
if(cdp2um_data[79:72] == 8'd1) //cut pkt marting
begin
if(cdp2um_data[48] == 1'b1)//fragment--No.2 //FSN
begin
identify <= cdp2um_data[71:56]; //id
p0_b_count <= p0_b_count +1'b1;
pkt_metadata <= {4'b0,4'b1100,cdp2um_data[71:56],ingress,rloc_src,eid_dst,metadata_parser};
end
else//fragment-No.1
begin
identify <= cdp2um_data[71:56];
pkt_metadata <= {4'b0,4'b1000,cdp2um_data[71:56],ingress,rloc_src,eid_dst,metadata_parser};
end
end
else
begin
pkt_metadata <= {8'b0,16'b0,ingress,rloc_src,eid_dst,metadata_parser};
end
parser_state <= parser_eth_2;
end
parser_eth_2:
begin
pkt_head_valid <= 1'b1;
pkt_head <= {3'b100,cdp2um_data[135:0]};
parser_state <= parser_eid_src;
end
parser_eid_src:
begin
pkt_head <= {3'b100,cdp2um_data[135:0]};
parser_state <= parser_eid_dst;
end
parser_eid_dst:
begin
pkt_head_valid <= 1'b1;
pkt_head <= {3'b100,cdp2um_data[135:0]};
eid_dst[127:48] <= cdp2um_data[79:0];
parser_state <= parser_udp_2;
end
parser_udp_2:
begin
pkt_head_valid <= 1'b1;
pkt_metadata_valid <= 1'b1;
eid_dst[47:0] <= cdp2um_data[127:80];
if(cdp2um_data[138:136]==3'b110)
begin
pkt_head <= {3'b110,cdp2um_data[135:0]};//head_tail;
parser_state <= idle;
pkt_metadata <= {4'h1,pkt_metadata[355:200],eid_dst[127:48],cdp2um_data[127:80],metadata_parser};
end
else
begin
pkt_head <= {3'b110,cdp2um_data[135:0]};//head_tail;
parser_state <= trans_payload;
pkt_metadata <= {4'h0,pkt_metadata[355:200],eid_dst[127:48],cdp2um_data[127:80],metadata_parser};
end
end
trans_payload_notlisp:
begin
if(metadata_parser[31:16]>16'd1300) pkt_metadata <= {4'h2,4'b0,16'b0,ingress,rloc_src,eid_dst,metadata_parser};
else pkt_metadata <= {8'b0,16'b0,ingress,rloc_src,eid_dst,metadata_parser};
pkt_metadata_valid <= 1'b1;
pkt_head_valid <= 1'b0;
pkt_payload_valid <= 1'b1;
if((cdp2um_data_valid == 1'b0) || (cdp2um_data[138:136] == 3'b110))
begin
parser_state <= idle;
pkt_payload <= {3'b110,cdp2um_data[135:0]};
end
else
begin
parser_state <= trans_payload;
pkt_payload <= {3'b100,cdp2um_data[135:0]};
end
end
trans_payload:
begin
pkt_head_valid <= 1'b0;
pkt_metadata_valid <= 1'b0;
pkt_payload_valid <= 1'b1;
if((cdp2um_data_valid == 1'b0) || (cdp2um_data[138:136] == 3'b110))
begin
parser_state <= idle;
pkt_payload <= {3'b110,cdp2um_data[135:0]};
end
else
begin
parser_state <= trans_payload;
pkt_payload <= {3'b100,cdp2um_data[135:0]};
end
end
trans_pkt_controller:
begin
pkt_metadata_valid <= 1'b0;
if((cdp2um_data_valid == 1'b0) || (cdp2um_data[138:136] == 3'b110))
begin
parser_state <= idle;
pkt_head <= {3'b110,cdp2um_data[135:0]};
end
else
begin
parser_state <= trans_pkt_controller;
pkt_head <= {3'b100,cdp2um_data[135:0]};
end
end
discard:
begin
if(cdp2um_data[138:136] == 3'b110) parser_state <= idle;
end
default:
begin
parser_state <= idle;
end
endcase
end
//-------------------ip_src_set_state-------------------//
always @ (posedge clk or negedge reset)
if(!reset) begin
// ip_src_1 <= 128'b0;
ip_src_2 <= 128'b0;ip_src_3 <= 128'b0;ip_src_4 <= 128'b0;
ip_src_5 <= 128'b0;ip_src_6 <= 128'b0;ip_src_7 <= 128'b0;ip_src_8 <= 128'b0;
end
else
begin
if(ip_src_valid == 1'b1)
begin
case(ip_src[130:128])
3'd0: ip_src_1 <= ip_src[127:0];
3'd1: ip_src_2 <= ip_src[127:0];
3'd2: ip_src_3 <= ip_src[127:0];
3'd3: ip_src_4 <= ip_src[127:0];
3'd4: ip_src_5 <= ip_src[127:0];
3'd5: ip_src_6 <= ip_src[127:0];
3'd6: ip_src_7 <= ip_src[127:0];
3'd7: ip_src_8 <= ip_src[127:0];
endcase
end
else ip_src_1 <= ip_src_1;
end
endmodule |
module parser(
input clk,
input reset,
input ip_src_valid,
input [130:0] ip_src,
input cdp2um_data_valid,
input [138:0] cdp2um_data,
output um2cdp_tx_enable,
output um2cdp_path,
output pkt_ctl_valid, //contorl
output [138:0] pkt_ctl,
input [7:0] pkt_ctl_usedw,
output pkt_metadata_cut_out_valid,
output [359:0] pkt_metadata_cut_out,
output [138:0] pkt_cut_data,
output pkt_cut_data_valid,
input [7:0] pkt_cut_data_usedw,
output pkt_metadata_nocut_out_valid,
output [359:0] pkt_metadata_nocut_out,
output [138:0] pkt_nocut_data,
output pkt_nocut_data_valid,
input [7:0] pkt_nocut_data_usedw);
wire buf_addr_full;
wire pkt_head_valid;
wire [138:0] pkt_head;
wire pkt_payload_valid;
wire [138:0] pkt_payload;
wire pkt_metadata_valid;
wire [359:0] pkt_metadata; //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
parser_h parser_h(
.ip_src_valid (ip_src_valid),
.ip_src (ip_src),
.clk (clk),
.reset (reset),
.buf_addr_full (buf_addr_full),
.cdp2um_data_valid (cdp2um_data_valid),
.cdp2um_data (cdp2um_data),
.um2cdp_tx_enable (um2cdp_tx_enable),
.um2cdp_path (um2cdp_path),
.pkt_head_valid (pkt_head_valid),
.pkt_head (pkt_head),
.pkt_payload_valid (pkt_payload_valid),
.pkt_payload (pkt_payload),
.pkt_metadata_valid (pkt_metadata_valid),
.pkt_metadata (pkt_metadata)); //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
parse_pkt_disp parse_pkt_disp(
.clk (clk),
.reset (reset),
.pkt_head_valid (pkt_head_valid),
.pkt_head (pkt_head),
.pkt_payload_valid (pkt_payload_valid),
.pkt_payload (pkt_payload),
.pkt_metadata_valid (pkt_metadata_valid),
.pkt_metadata (pkt_metadata), //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
.pkt_ctl_valid (pkt_ctl_valid), //contorl
.pkt_ctl (pkt_ctl),
.pkt_ctl_usedw (pkt_ctl_usedw),
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw),
.buf_addr_full (buf_addr_full));
endmodule |
module parse_pkt_disp(
input clk,
input reset,
input pkt_head_valid,
input [138:0] pkt_head,
input pkt_payload_valid,
input [138:0] pkt_payload,
input pkt_metadata_valid,
input [359:0] pkt_metadata, //wait to define;8bit-action; 16bit-identify;8bit-ingress; 128bit-rloc_src; 128bit-eid_dst; 72bit-metadata;
output reg pkt_ctl_valid,
output reg [138:0] pkt_ctl,
input [7:0] pkt_ctl_usedw,
output reg pkt_metadata_cut_out_valid,
output reg [359:0] pkt_metadata_cut_out,
output reg [138:0] pkt_cut_data,
output reg pkt_cut_data_valid,
input [7:0] pkt_cut_data_usedw,
output reg pkt_metadata_nocut_out_valid,
output reg [359:0] pkt_metadata_nocut_out,
output reg [138:0] pkt_nocut_data,
output reg pkt_nocut_data_valid,
input [7:0] pkt_nocut_data_usedw,
output reg buf_addr_full);
reg flag;
wire [7:0] pkt_head_usedw, pkt_payload_usedw;
wire [3:0] pkt_metadata_usedw;
reg pkt_head_rdreq,pkt_payload_rdreq, pkt_metadata_rdreq;
wire [138:0] pkt_head_q,pkt_payload_q;
wire [359:0] pkt_metadata_q;
wire pkt_metadata_empty;
reg [2:0] current_state;
parameter idle_s = 3'd0,
parse_metadata_s = 3'd1,
discard_h_s = 3'd2,
trans_ctl_s = 3'd3,
trans_h_s = 3'd4,
trans_b_s = 3'd5;
always @ (posedge clk or negedge reset)
if(!reset) begin
pkt_head_rdreq <= 1'b0;
pkt_payload_rdreq <= 1'b0;
pkt_metadata_rdreq <= 1'b0;
pkt_metadata_nocut_out_valid <= 1'b0;
pkt_metadata_nocut_out <= 360'b0;
pkt_metadata_cut_out_valid <= 1'b0;
pkt_metadata_cut_out <= 360'b0;
pkt_ctl_valid <= 1'b0;
flag <= 1'b0;
pkt_ctl <= 139'b0;
pkt_cut_data_valid <= 1'b0;
pkt_cut_data <= 139'b0;
pkt_nocut_data_valid <= 1'b0;
pkt_nocut_data <= 139'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
pkt_ctl_valid <= 1'b0;
flag <= 1'b0;
pkt_nocut_data_valid <= 1'b0;
pkt_metadata_cut_out_valid <= 1'b0;
pkt_cut_data_valid <= 1'b0;
pkt_metadata_nocut_out_valid <= 1'b0;
if(pkt_metadata_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
pkt_head_rdreq <= 1'b0;
pkt_metadata_rdreq <= 1'b1;
pkt_metadata_nocut_out <= pkt_metadata_q;
current_state <= parse_metadata_s;
end
end
parse_metadata_s: begin
pkt_head_rdreq <= 1'b0;
pkt_metadata_rdreq <= 1'b0;
if(pkt_metadata_nocut_out[359] == 1'b1) begin //discard
pkt_head_rdreq <= 1'b1;
current_state <= discard_h_s;
end
else if(pkt_metadata_nocut_out[358] == 1'b1) begin //ctl
if(pkt_ctl_usedw < 8'd161) begin
pkt_head_rdreq <= 1'b1;
current_state <= trans_ctl_s;
end
else begin
current_state <= parse_metadata_s;
end
end
else if(pkt_metadata_nocut_out[355] == 1'b1) begin//cut
pkt_metadata_cut_out <= pkt_metadata_nocut_out;
if(pkt_cut_data_usedw < 8'd161) begin
pkt_head_rdreq <= 1'b1;
flag <= 1'b0;
current_state <= trans_h_s;
end
else begin
current_state <= idle_s;
end
end
else begin
if(pkt_nocut_data_usedw < 8'd161) begin
pkt_head_rdreq <= 1'b1;
flag <= 1'b1;
current_state <= trans_h_s;
end
else begin
current_state <= idle_s;
end
end
end
trans_h_s: begin
if(pkt_head_q[138:136] == 3'b110) begin
pkt_head_rdreq <= 1'b0;
if(flag == 1'b1) begin
if(pkt_metadata_nocut_out[356]) begin //no body
pkt_nocut_data_valid <= 1'b1;
pkt_nocut_data <= pkt_head_q;
pkt_metadata_nocut_out_valid <= 1'b1;
current_state <= idle_s;
end
else begin
pkt_nocut_data_valid <= 1'b1;
pkt_nocut_data <= {3'b100,pkt_head_q[135:0]};
pkt_payload_rdreq <= 1'b1;
current_state <= trans_b_s;
end
end
else begin
if(pkt_metadata_nocut_out[356]) begin //no body
pkt_cut_data_valid <= 1'b1;
pkt_cut_data <= pkt_head_q;
pkt_metadata_cut_out_valid <= 1'b1;
current_state <= idle_s;
end
else begin
pkt_cut_data_valid <= 1'b1;
pkt_cut_data <= {3'b100,pkt_head_q[135:0]};
pkt_payload_rdreq <= 1'b1;
current_state <= trans_b_s;
end
end
end
else begin
current_state <= trans_h_s;
if(flag == 1'b1) begin
pkt_nocut_data_valid <= 1'b1;
pkt_nocut_data <= pkt_head_q;
end
else begin
pkt_cut_data_valid <= 1'b1;
pkt_cut_data <= pkt_head_q;
end
end
end
trans_b_s: begin
if(pkt_payload_q[138:136] == 3'b110) begin
pkt_payload_rdreq <= 1'b0;
current_state <= idle_s;
if(flag == 1'b1) begin
pkt_nocut_data_valid <= 1'b1;
pkt_metadata_nocut_out_valid <= 1'b1;
pkt_nocut_data <= pkt_payload_q;
end
else begin
pkt_cut_data_valid <= 1'b1;
pkt_metadata_cut_out_valid <= 1'b1;
pkt_cut_data <= pkt_payload_q;
end
end
else begin
current_state <= trans_b_s;
if(flag == 1'b1) begin
pkt_nocut_data_valid <= 1'b1;
pkt_nocut_data <= pkt_payload_q;
end
else begin
pkt_cut_data_valid <= 1'b1;
pkt_cut_data <= pkt_payload_q;
end
end
end
trans_ctl_s: begin
pkt_ctl_valid <= 1'b1;
pkt_ctl <= pkt_head_q;
if(pkt_head_q[138:136] == 3'b110) begin
pkt_head_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= trans_ctl_s;
end
end
discard_h_s: begin
if(pkt_head_q[138:136] == 3'b110) begin
pkt_head_rdreq <= 1'b0;
current_state <= idle_s;
end
else begin
current_state <= discard_h_s;
end
end
endcase
end
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
buf_addr_full <= 1'b0;
end
else
begin
if((pkt_head_usedw < 8'd160) && (pkt_payload_usedw < 8'd160) &&(pkt_metadata_usedw < 4'd13))
begin
buf_addr_full <= 1'b0;
end
else buf_addr_full <= 1'b1;
end
end
fifo_139_256 head_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_head),
.rdreq(pkt_head_rdreq),
.wrreq(pkt_head_valid),
.empty(),
.full(),
.q(pkt_head_q),
.usedw(pkt_head_usedw)
);
fifo_139_256 payload_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_payload),
.rdreq(pkt_payload_rdreq),
.wrreq(pkt_payload_valid),
.empty(),
.full(),
.q(pkt_payload_q),
.usedw(pkt_payload_usedw)
);
fifo_360_16 metadata_fifo(
.aclr(!reset),
.clock(clk),
.data(pkt_metadata),
.rdreq(pkt_metadata_rdreq),
.wrreq(pkt_metadata_valid),
.empty(pkt_metadata_empty),
.full(),
.q(pkt_metadata_q),
.usedw(pkt_metadata_usedw)
);
endmodule |
module tx_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [9:0] sub_wire1;
wire [35:0] sub_wire2;
wire rdempty = sub_wire0;
wire [9:0] wrusedw = sub_wire1[9:0];
wire [35:0] q = sub_wire2[35:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 36,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module NET_MAGIC_CTRL(
clk,
reset_n, //active low
/////// local bus interface start///////
ale, //Address Latch Enable.active high output
cs_n, //local bus chip select ,active low.
data, //32-bit bidirectional multiplexed write data and address bus output
rd_wr,
ack_n_um, //local bus ack.active low. input
ack_n_cdp, //local bus ack.active low. input
ack_n_sram, //local bus ack.active low. input
rdata_um, //local bus read data from um
rdata_cdp, //local bus read data from cdp
rdata_sram, //local bus read data from sram
////passthrough module interface////////
pass_pkt,
pass_pkt_wrreq,
pass_pkt_usedw,
pass_valid_wrreq,
pass_valid,
//////rx/tx module interface///////////
tx_pkt,
tx_pkt_wrreq,
tx_pkt_valid,
tx_pkt_valid_wrreq,
tx_pkt_usedw,
////crc_check module interface///
pkt_wrreq,
pkt,
pkt_usedw,
valid_wrreq,
valid,
////pkt insert module interface ////
datapath_pkt_wrreq,
datapath_pkt,
datapath_pkt_usedw,
datapath_valid_wrreq,
datapath_valid,
FPGA_MAC,
FPGA_IP
);
input [47:0] FPGA_MAC;
input [31:0] FPGA_IP;
/////////////// ??? ///////////////////////
//parameter FPGA_MAC = 48'h888888888888;
//parameter FPGA_IP = 32'h88888888;
/////////////// ??? ///////////////////////
/////////////// IO DATA///////////////////////
input clk;
input reset_n; //active low
/////// local bus interface start///////
output ale; //Address Latch Enable.active high output
output cs_n; //local bus chip select ,active low.
output rd_wr; //read or write request.1: read 0: write output
output [31:0]data; //32-bit bidirectional multiplexed write data and address bus output
input ack_n_um; //local bus ack.active low. input
input ack_n_cdp; //local bus ack.active low. input
input ack_n_sram; //local bus ack.active low. input
input [31:0] rdata_um; //local bus read data from um
input [31:0] rdata_cdp; //local bus read data from cdp
input [31:0] rdata_sram; //local bus read data from sram
////crc_check module interface///
input pkt_wrreq;
input[138:0] pkt;
output [7:0] pkt_usedw;
input valid_wrreq;
input valid;
////pkt insert module interface ////
output datapath_pkt_wrreq;
output[138:0] datapath_pkt;
input [7:0] datapath_pkt_usedw;
output datapath_valid_wrreq;
output datapath_valid;
input[138:0] pass_pkt;
input pass_pkt_wrreq;
output [7:0] pass_pkt_usedw;
input pass_valid_wrreq;
input pass_valid;
output [138:0]tx_pkt;
output tx_pkt_wrreq;
output tx_pkt_valid;
output tx_pkt_valid_wrreq;
input [7:0] tx_pkt_usedw;
wire [47:0] PROXY_MAC;
wire [31:0] PROXY_IP;
wire proxy_addr_valid;
wire [34:0] command_data;
wire command_wr;
wire command_fifo_full;
wire [16:0] sequence_d;
wire sequence_wr;
wire sequence_fifo_full;
wire [36:0] pkt_to_gen;
wire pkt_to_gen_wr;
wire pkt_to_gen_afull;
wire [32:0] length_to_gen;
wire length_to_gen_wr;
wire length_to_gen_afull;
wire [35:0] ack_pkt;
wire ack_wr;
wire ack_afull;
wire ack_valid_wr;
wire ack_valid_afull;
wire ack_fifo_wrclk;
manage_rx manage_rx(
.clk(clk),
.reset_n(reset_n),
////crc_check module interface///
.pkt_wrreq(pkt_wrreq),
.pkt(pkt),
.pkt_usedw(pkt_usedw),
.valid_wrreq(valid_wrreq),
.valid(valid),
////pkt insert module interface ////
.datapath_pkt_wrreq(datapath_pkt_wrreq),
.datapath_pkt(datapath_pkt),
.datapath_pkt_usedw(datapath_pkt_usedw),
.datapath_valid_wrreq(datapath_valid_wrreq),
.datapath_valid(datapath_valid),
//////command parse module interface/////////
.command_data(command_data), //command [34:32]001:??????? 011:??????? 010:???????? 111:???????? [31:0]:??
.command_wr(command_wr),
.command_fifo_full(command_fifo_full),
.sequence_d(sequence_d), //[15:0]:??????[16]:?????? 1????? 0????? ???
.sequence_wr(sequence_wr),
.sequence_fifo_full(sequence_fifo_full),
.PROXY_MAC(PROXY_MAC),
.PROXY_IP(PROXY_IP),
.FPGA_MAC(FPGA_MAC),
.FPGA_IP(FPGA_IP),
.proxy_addr_valid(proxy_addr_valid)
);
command_parse command_parse(
.clk(clk),
.reset_n(reset_n),// active low
//////??////////////
.command_data(command_data), //???[34:32]001:??????? 011:??????? 010:???????? 111:???????? [31:0]:??
.command_wr(command_wr),
.command_fifo_full(command_fifo_full),
.sequence_d(sequence_d), //[15:0]:??????[16]:?????? 1????? 0????? ???
.sequence_wr(sequence_wr),
.sequence_fifo_full(sequence_fifo_full),
//////////////////////////
/////// local_bus ////////
.ale(ale), //Address Latch Enable.active high output
.cs_n(cs_n), //local bus chip select ,active low.
.rd_wr(rd_wr), //read or write request.1: read 0: write output
.ack_n_um(ack_n_um), //local bus ack.active low. input
.ack_n_cdp(ack_n_cdp), //local bus ack.active low. input
.ack_n_sram(ack_n_sram), //local bus ack.active low. input
.rdata_um(rdata_um), //local bus read data from um
.rdata_cdp(rdata_cdp), //local bus read data from cdp
.rdata_sram(rdata_sram), //local bus read data from sram
//32-bit bidirectional multiplexed write data and address bus output
.data_out(data),
.pkt_to_gen(pkt_to_gen),//[36:34] 001:??????? 011:??????? 010:???????? 100:???? [33:31]:????? [31:0]:??
.pkt_to_gen_wr(pkt_to_gen_wr),
.pkt_to_gen_afull(pkt_to_gen_afull),
.length_to_gen(length_to_gen),//[32:24]:?????? [23:16]:count [15:0]???
.length_to_gen_wr(length_to_gen_wr),
.length_to_gen_afull(length_to_gen_afull)
);
pkt_gen pkt_gen(
.clk(clk),
.reset_n(reset_n),
.PROXY_MAC(PROXY_MAC),
.PROXY_IP(PROXY_IP),
.FPGA_MAC(FPGA_MAC),
.FPGA_IP(FPGA_IP),
.proxy_addr_valid(proxy_addr_valid),
.pkt_to_gen(pkt_to_gen),//[36:34] 001:??????? 011:??????? 010:???????? 100:???? [33:31]:????? [31:0]:??
.pkt_to_gen_wr(pkt_to_gen_wr),
.pkt_to_gen_afull(pkt_to_gen_afull),
.length_to_gen(length_to_gen),//[24:16]:?????? [15:0]???
.length_to_gen_wr(length_to_gen_wr),
.length_to_gen_afull(length_to_gen_afull),
//FPGA??????????;
.ack_pkt(ack_pkt), //[35:34]01:??????? 11:??????? 10:???????? [33:32]:????? [31:0]:??
.ack_wr(ack_wr),
.ack_afull(ack_afull),
//FPGA???????????????;??FIFO??????FIFO????????????
.ack_valid_wr(ack_valid_wr),
.ack_valid_afull(ack_valid_afull));
manage_tx manage_tx(
.clk(clk),
.reset_n(reset_n),
// ack_fifo_wrclk,.
.ack_pkt(ack_pkt), //[35:34]01:??????? 11:??????? 10:???????? [33:32]:????? [31:0]:??
.ack_wr(ack_wr),
.ack_afull(ack_afull),
//FPGA???????????????;??FIFO??????FIFO????????????
.ack_valid_wr(ack_valid_wr),
.ack_valid_afull(ack_valid_afull),
.pass_pkt(pass_pkt),
.pass_pkt_wrreq(pass_pkt_wrreq),
.pass_pkt_usedw(pass_pkt_usedw),
.pass_valid_wrreq(pass_valid_wrreq),
.pass_valid(pass_valid),
.tx_pkt(tx_pkt),
.tx_pkt_wrreq(tx_pkt_wrreq),
.tx_pkt_valid(tx_pkt_valid),
.tx_pkt_valid_wrreq(tx_pkt_valid_wrreq),
.tx_pkt_usedw(tx_pkt_usedw)
);
endmodule |
module command_parse(
clk,
reset_n,// active low
//////??////////////
command_data, //???[34:32]001:??????? 011:??????? 010:???????? 111:???????? [31:0]:??
command_wr,
command_fifo_full,
sequence_d, //[15:0]:??????[16]:?????? 1????? 0????? ???
sequence_wr,
sequence_fifo_full,
//////////////////////////
/////// local_bus ////////
ale, //Address Latch Enable.active high output
cs_n, //local bus chip select ,active low.
rd_wr, //read or write request.1: read 0: write output
//32-bit bidirectional multiplexed data and address bus inout
data_out,
ack_n_um, //local bus ack.active low. input
ack_n_cdp, //local bus ack.active low. input
ack_n_sram, //local bus ack.active low. input
rdata_um, //local bus read data from um
rdata_cdp, //local bus read data from cdp
rdata_sram, //local bus read data from sram
pkt_to_gen,//[36:34] 001:??????? 011:??????? 010:???????? 100:???? [33:32]:????? [31:0]:??
pkt_to_gen_wr,
pkt_to_gen_afull,
length_to_gen,//[32:24]:?????? [23:16]:count [15:0]???
length_to_gen_wr,
length_to_gen_afull
);
input clk;
input reset_n;//active low
output ale; //Address Latch Enable.active high output
output cs_n; //local bus chip select ,active low.
output rd_wr; //read or write request.1: read 0: write output
//32-bit bidirectional multiplexed data and address bus inout
output[31:0] data_out;
input ack_n_um; //local bus ack.active low. input
input ack_n_cdp; //local bus ack.active low. input
input ack_n_sram; //local bus ack.active low. input
input [31:0] rdata_um; //local bus read data from um
input [31:0] rdata_cdp; //local bus read data from cdp
input [31:0] rdata_sram; //local bus read data from sram
input [34:0] command_data; //???[34:32]001:??????? 011:??????? 010:???????? 100:???????? [31:0]:??
input command_wr;
output command_fifo_full;
input [16:0] sequence_d; //[15:0]:??????[16]:?????? 1????? 0????? ???
input sequence_wr;
output sequence_fifo_full;
output [36:0]pkt_to_gen;//[36:34] 001:??????? 011:??????? 010:???????? 100:???? [33:32]:????? [31:0]:??
output pkt_to_gen_wr;
input pkt_to_gen_afull;
output [32:0]length_to_gen;
output length_to_gen_wr;
input length_to_gen_afull;
reg ale; //Address Latch Enable.active high output
reg cs_n; //local bus chip select ,active low.
reg rd_wr; //read or write request.1: read 0: write output
reg [31:0] data_out; //32-bit bidirectional multiplexed data and address bus inout
reg [36:0] pkt_to_gen;
reg pkt_to_gen_wr;
reg [32:0] length_to_gen;
reg length_to_gen_wr;
reg [31:0] com_rdout;
reg [15:0] result_cnt; //??????????
reg [2:0] head_tail_flag; //???????
reg [31:0] op_addr; //??????
reg [15:0] burst;
reg [8:0] timer;
reg [1:0] wait_cnt;
reg [7:0] count;//??????
//////////////FIFO ???//////////////
wire [9:0] wrusedw_com;
wire [34:0] command_rdata;
reg command_rd;
wire command_empty;
wire command_fifo_full;
data_fifo com_fifo(
.aclr(!reset_n),
.data(command_data),
.rdclk(clk),
.wrclk(clk),
.rdreq(command_rd),
.wrreq(command_wr),
.q(command_rdata),
.rdempty(command_empty),
.wrusedw(wrusedw_com));
assign command_fifo_full = (wrusedw_com > 10'd650)?1'b1:1'b0;
wire[8:0] wrusedw_sequence;
wire[16:0]sequence_rdata;
reg sequence_rd;
wire sequence_empty;
wire sequence_fifo_full;
com_valid_fifo com_valid_fifo(
.aclr(!reset_n),
.data(sequence_d),
.rdclk(clk),
.wrclk(clk),
.rdreq(sequence_rd),
.wrreq(sequence_wr),
.q(sequence_rdata),
.rdempty(sequence_empty),
.wrusedw(wrusedw_sequence));
assign sequence_fifo_full = (wrusedw_sequence > 9'd510)?1'b1:1'b0;
reg [33:0] result_head_data;
reg result_head_rdreq;
reg result_head_wrreq;
wire[33:0] result_head_rdata;
wire result_head_afull;
wire[9:0] wrusedw_head;
// ?????????????????
result_fifo result_head_fifo (
.aclr(!reset_n),
.data(result_head_data),
.clock(clk),
.rdreq(result_head_rdreq),
.wrreq(result_head_wrreq),
.q(result_head_rdata),
.usedw(wrusedw_head));
assign result_head_afull = (wrusedw_head > 10'd650)?1'b1:1'b0;
// ?????????????????---?n?
reg [33:0] result_data;
reg result_rdreq;
reg result_wrreq;
wire [33:0] result_rdata;
wire result_afull;
wire [9:0] wrusedw_result;
//??????????????????????????????????
result_fifo result_fifo(
.aclr(!reset_n),
.data(result_data),
.clock(clk),
.rdreq(result_rdreq),
.wrreq(result_wrreq),
.q(result_rdata),
.usedw(wrusedw_result));
assign result_afull = (wrusedw_result > 10'd650)?1'b1:1'b0;
reg [32:0] pkt_length_data;//[15:0]??? [23:16]:????[32:24]:???????????????4???
reg pkt_length_rdreq;
reg pkt_length_wrreq;
wire pkt_length_empty;
wire [32:0]pkt_length_rdata;
wire pkt_length_afull;
wire [8:0] wrusedw_pkt_length;
//??????????????????? ???????????????4???
pkt_length_fifo pkt_length_fifo (
.aclr(!reset_n),
.data(pkt_length_data),
.clock(clk),
.rdreq(pkt_length_rdreq),
.wrreq(pkt_length_wrreq),
.q(pkt_length_rdata),
.empty(pkt_length_empty),
.usedw(wrusedw_pkt_length));
assign pkt_length_afull = (wrusedw_pkt_length > 9'd510)?1'b1:1'b0;
wire parse_permit;
assign parse_permit = (~command_empty) & (~sequence_empty) & (~result_head_afull) & (~result_afull) & (~pkt_length_afull);//1:???? 0????
wire ack_n;
assign ack_n = ack_n_um & ack_n_cdp & ack_n_sram;
parameter idle_s = 4'h0,
parse_s = 4'h1,
read_addr_s = 4'h2,
read_s = 4'h3,
read_ale_s = 4'h4,
read_wait_s = 4'h5,
read_cs_s = 4'h6,
read_ack_s = 4'h7,
write_addr_s = 4'h8,
write_s = 4'h9,
write_ale_s = 4'ha,
write_wait_s = 4'hb,
write_data_s = 4'hc,
write_cs_s = 4'hd,
write_ack_s = 4'he,
drop_s = 4'hf;
reg [3:0] com_parse_state;
always@(posedge clk or negedge reset_n)
begin
if(~reset_n)begin
command_rd <= 1'b0;
sequence_rd <= 1'b0;
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
result_wrreq <= 1'b0;
result_head_wrreq <= 1'b0;
pkt_length_wrreq <= 1'b0;
timer <= 9'b0;
com_parse_state <= idle_s;
end
else begin
case(com_parse_state)
idle_s: begin
ale <= 1'b0;
cs_n <= 1'b1;
result_wrreq <= 1'b0;
result_head_wrreq <= 1'b0;
pkt_length_wrreq <= 1'b0;
result_cnt <= 16'h0;
pkt_length_data <= 33'h0;
timer <= 9'b0;
casex({parse_permit,sequence_rdata[16]})
2'b11: begin
command_rd <= 1'b1;
sequence_rd <= 1'b1;
com_rdout <= command_rdata[31:0];//2011 4 12
head_tail_flag <= command_rdata[34:32];
pkt_length_data[15:0] <= sequence_rdata[15:0];
com_parse_state <= parse_s;
end
2'b10: begin
command_rd <= 1'b1;
sequence_rd <= 1'b1;
com_parse_state <= drop_s;
end
default:begin
command_rd <= 1'b0;
sequence_rd <= 1'b0;
com_parse_state <= idle_s;
end
endcase
end
parse_s:begin
command_rd <= 1'b0;
sequence_rd <= 1'b0;
result_cnt <= 16'b0;
case(com_rdout[27:24])
4'h1:begin//??????
case({head_tail_flag,com_rdout[8]})
4'b1001:begin//????
result_head_data <= 34'h001000100;
result_head_wrreq <= 1'b1;
result_wrreq <= 1'b0;
pkt_length_data[32:24] <= 9'h001;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
4'b1000:begin//????????
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
pkt_length_wrreq <= 1'b0;
com_parse_state <= idle_s;
end
default:begin
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
if(pkt_length_data[32:24] == 9'h0)
pkt_length_wrreq <= 1'b0;
else
pkt_length_wrreq <= 1'b1;
com_parse_state <= drop_s;
end
endcase
end
4'h2:begin//????
case({head_tail_flag,com_rdout[9]})
4'b1001:begin//????
result_head_data <= 34'h002000200;
result_head_wrreq <= 1'b1;
result_wrreq <= 1'b0;
pkt_length_data[32:24] <= 9'h001;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
4'b1000:begin//???? ???
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
pkt_length_wrreq <= 1'b0;
com_parse_state <= idle_s;
end
default:begin
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
if(pkt_length_data[32:24] == 9'h0)
pkt_length_wrreq <= 1'b0;
else
pkt_length_wrreq <= 1'b1;
com_parse_state <= drop_s;
end
endcase
end
4'h3:begin//???
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
burst <= com_rdout[23:8];
command_rd <= 1'b1;
com_parse_state <= read_addr_s;
end
4'h4:begin//???
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
burst <= com_rdout[23:8];
command_rd <= 1'b1;
com_parse_state <= write_addr_s;
end
default:begin
result_head_wrreq <= 1'b0;
result_wrreq <= 1'b0;
command_rd <= 1'b1;
com_parse_state <= drop_s;
end
endcase
end
read_addr_s:begin
command_rd <= 1'b0;
op_addr <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
com_parse_state <= read_s;
end
read_s: begin
result_wrreq <= 1'b0;
if( ack_n != 1'b0 )begin
data_out <= op_addr;//??
rd_wr <= 1'b1;//read
wait_cnt <= 2'b0;
com_parse_state <= read_ale_s;
end
else begin//??????????
com_parse_state <= read_s;
end
end
read_ale_s:begin
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
ale <= 1'b1;//????
com_parse_state <= read_wait_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= read_ale_s;
end
end
read_wait_s:begin
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
ale <= 1'b0;
com_parse_state <= read_cs_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= read_wait_s;
end
end
read_cs_s:begin//????
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
data_out <= 32'h0;
cs_n <= 1'b0;
result_cnt <= result_cnt + 1'b1;
burst <= burst - 1'b1;
com_parse_state <= read_ack_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= read_cs_s;
end
end
read_ack_s:begin
case({ack_n,timer[8],(|burst)})
3'b000,3'b010:begin//??????
case({ack_n_um,ack_n_cdp,ack_n_sram})
3'b011:begin
result_data <= {2'b0,rdata_um};
end
3'b101:begin
result_data <= {2'b0,rdata_cdp};
end
3'b110:begin
result_data <= {2'b0,rdata_sram};
end
default:begin
result_data <= 34'b0;
end
endcase
result_wrreq <= 1'b1;
cs_n <= 1'b1;
timer <= 9'b0;
pkt_length_data[32:24] <= pkt_length_data[32:24] + 9'h002;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
result_head_data <= {10'h005,result_cnt,8'h0};
result_head_wrreq <= 1'b1;
if(head_tail_flag == 3'b010)begin//???
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
else begin//?????????????
command_rd <= 1'b1;
com_rdout <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
com_parse_state <= parse_s;
end
end
3'b110,3'b111:begin//??
cs_n <= 1'b1;
pkt_length_data[32:24] <= pkt_length_data[32:24] + 9'h001;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
result_head_data <= {10'h005,(result_cnt-1'b1),8'h0};
result_head_wrreq <= 1'b1;
timer <= 9'b0;
if(head_tail_flag == 3'b010)begin//???
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
else begin//?????????????
command_rd <= 1'b1;
com_rdout <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
com_parse_state <= parse_s;
end
end
3'b001,3'b011:begin//????????
case({ack_n_um,ack_n_cdp,ack_n_sram})
3'b011:begin
result_data <= {2'b0,rdata_um};
end
3'b101:begin
result_data <= {2'b0,rdata_cdp};
end
3'b110:begin
result_data <= {2'b0,rdata_sram};
end
default:begin
result_data <= 34'b0;
end
endcase
result_wrreq <= 1'b1;
timer <= 9'b0;
cs_n <= 1'b1;
op_addr <= op_addr + 1'b1;
pkt_length_data[32:24] <= pkt_length_data[32:24] + 9'h001;
com_parse_state <= read_s;
end
3'b100,3'b101:begin
result_wrreq <= 1'b0;
timer <= timer + 1'b1;
com_parse_state <= read_ack_s;
end
endcase
end
write_addr_s:begin
command_rd <= 1'b0;
op_addr <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
com_parse_state <= write_s;
end
write_s:begin
if( ack_n != 1'b0 )begin
data_out <= op_addr;//??
rd_wr <= 1'b0;//write
wait_cnt <= 2'b0;
com_parse_state <= write_ale_s;
end
else begin//??????????
com_parse_state <= write_s;
end
end
write_ale_s:begin
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
ale <= 1'b1;//????
com_parse_state <= write_wait_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= write_ale_s;
end
end
write_wait_s:begin
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
ale <= 1'b0;
com_parse_state <= write_data_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= write_wait_s;
end
end
write_data_s:begin
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
command_rd <= 1'b1;
data_out <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
wait_cnt <= 2'b0;
com_parse_state <= write_cs_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= write_data_s;
end
end
write_cs_s:begin//????
command_rd <= 1'b0;
if(wait_cnt==2'b10)begin
wait_cnt <= 2'b0;
cs_n <= 1'b0;
result_cnt <= result_cnt + 1'b1;
burst <= burst - 1'b1;
com_parse_state <= write_ack_s;
end
else begin
wait_cnt <= wait_cnt + 1'b1;
com_parse_state <= write_cs_s;
end
end
write_ack_s:begin
case({ack_n,timer[8],(|burst)})
3'b000,3'b010:begin//??????
cs_n <= 1'b1;
rd_wr <= 1'b1;
timer <= 9'b0;
pkt_length_data[32:24] <= pkt_length_data[32:24] + 9'h001;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
result_head_data <= {10'h006,result_cnt,8'h0};
result_head_wrreq <= 1'b1;
if(head_tail_flag == 3'b010)begin//???
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
else begin//?????????????
command_rd <= 1'b1;
com_rdout <= command_rdata[31:0];
head_tail_flag <= command_rdata[34:32];
com_parse_state <= parse_s;
end
end
3'b110,3'b111:begin//??
cs_n <= 1'b1;
timer <= 9'b0;
rd_wr <= 1'b1;
pkt_length_data[32:24] <= pkt_length_data[32:24] + 9'h001;
pkt_length_data[23:16] <= pkt_length_data[23:16] + 1'b1;
result_head_data <= {10'h006,(result_cnt-1'b1),8'h0};
result_head_wrreq <= 1'b1;
if(head_tail_flag == 3'b010)begin//???
pkt_length_wrreq <= 1'b1;
com_parse_state <= idle_s;
end
else begin//????????????? ???????????????????
command_rd <= 1'b1;
pkt_length_wrreq <= 1'b1;
com_parse_state <= drop_s;
end
end
3'b001,3'b011:begin//????????
cs_n <= 1'b1;
rd_wr <= 1'b1;
timer <= 9'b0;
op_addr <= op_addr + 1'b1;
com_parse_state <= write_s;
end
3'b100,3'b101:begin
timer <= timer + 1'b1;
com_parse_state <= write_ack_s;
end
endcase
end
drop_s: begin
sequence_rd <= 1'b0;
pkt_length_wrreq <= 1'b0;
if((command_rdata[34:32]==3'b010)||(command_rdata[34:32]==3'b100))
begin
command_rd <= 1'b0;
com_parse_state <= idle_s;
end
else
begin
command_rd <= 1'b1;
com_parse_state <= drop_s;
end
end
default:begin
command_rd <= 1'b0;
sequence_rd <= 1'b0;
ale <= 1'b0;
cs_n <= 1'b1;
com_parse_state <= idle_s;
end
endcase
end
end
reg [8:0] result_cnt0;
reg first_head_flag;
reg [15:0] rd_result_cnt;//????????
parameter gen_idle_s = 2'h0,
gen_wr_head_s = 2'h1,
gen_wr_rdresult_s = 2'h2;
reg [1:0] pkt_to_gen_state;
always@(posedge clk or negedge reset_n)
begin
if(~reset_n)begin
pkt_length_rdreq <= 1'b0;
result_rdreq <= 1'b0;
result_head_rdreq <= 1'b0;
pkt_to_gen_wr <= 1'b0;
length_to_gen_wr <= 1'b0;
pkt_to_gen_state <= gen_idle_s;
end
else begin
case(pkt_to_gen_state)
gen_idle_s:begin
pkt_length_rdreq <= 1'b0;
result_rdreq <= 1'b0;
result_head_rdreq <= 1'b0;
pkt_to_gen_wr <= 1'b0;
length_to_gen_wr <= 1'b0;
if((!pkt_length_empty)&(!pkt_to_gen_afull)&(!length_to_gen_afull))
begin
length_to_gen <= pkt_length_rdata;
result_cnt0 <= pkt_length_rdata[32:24];
result_head_rdreq <= 1'b1;//?????
pkt_length_rdreq <= 1'b1; //??????
first_head_flag <= 1'b1;
pkt_to_gen_state <= gen_wr_head_s;
end
else
begin
result_head_rdreq <= 1'b0;
pkt_length_rdreq <= 1'b0;
pkt_to_gen_state <= gen_idle_s;
end
end
gen_wr_head_s:begin
pkt_length_rdreq <= 1'b0;
result_head_rdreq <= 1'b0;
pkt_to_gen[33:0] <= result_head_rdata;
pkt_to_gen_wr <= 1'b1;
if(result_cnt0==9'h001)begin//??????
result_head_rdreq <= 1'b0;
//?????FIFO
length_to_gen_wr <= 1'b1;//?????FIFO
if(first_head_flag)
pkt_to_gen[36:34]<= 3'b100;
else
pkt_to_gen[36:34]<= 3'b010;
pkt_to_gen_state <= gen_idle_s;
end
else begin////??????
result_cnt0 <= result_cnt0 - 1'b1;
if(first_head_flag)
begin
first_head_flag <= 1'b0;
pkt_to_gen[36:34] <= 3'b001;
end
else
begin
pkt_to_gen[36:34] <= 3'b011;
end
case(result_head_rdata[27:24])
4'h1,4'h2,4'h6:begin//???????????????
result_head_rdreq <= 1'b1;//??????????
pkt_to_gen_state <= gen_wr_head_s;
end
4'h5:begin//???
if(result_head_rdata[23:8]==16'h0)begin//???
result_head_rdreq <= 1'b1;//??????????
pkt_to_gen_state <= gen_wr_head_s;
end
else begin//??????
result_head_rdreq <= 1'b0;
rd_result_cnt <= result_head_rdata[23:8];
result_rdreq <= 1'b1;
pkt_to_gen_state <= gen_wr_rdresult_s;
end
end
default:begin
result_rdreq <= 1'b1;
pkt_to_gen_state <= gen_idle_s;
end
endcase
end
end
gen_wr_rdresult_s:begin
pkt_to_gen[33:0] <= result_rdata[33:0];
if(rd_result_cnt==16'h01)//?????????
begin
result_rdreq <= 1'b0;
if(result_cnt0==9'h001)
begin
result_head_rdreq <= 1'b0;
//?????FIFO
length_to_gen_wr <= 1'b1;
pkt_to_gen[36:34] <= 3'b010;
pkt_to_gen_state <= gen_idle_s;
end
else
begin
pkt_to_gen[36:34] <= 3'b011;
result_head_rdreq <= 1'b1;
pkt_to_gen_state <= gen_wr_head_s;
end
end
else
begin
result_rdreq <= 1'b1;
pkt_to_gen[36:34] <= 3'b011;
pkt_to_gen_state <= gen_wr_rdresult_s;
end
result_cnt0 <= result_cnt0 - 1'b1;
rd_result_cnt <= rd_result_cnt - 1'b1;
pkt_to_gen_wr <= 1'b1;
end
default:begin
pkt_length_rdreq <= 1'b0;
result_rdreq <= 1'b0;
result_head_rdreq <= 1'b0;
pkt_to_gen_wr <= 1'b0;
length_to_gen_wr <= 1'b0;
pkt_to_gen_state <= gen_idle_s;
end
endcase
end
end
endmodule |
module pkt_length_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [32:0] data;
input rdreq;
input wrreq;
output empty;
output [32:0] q;
output [8:0] usedw;
wire [8:0] sub_wire0;
wire sub_wire1;
wire [32:0] sub_wire2;
wire [8:0] usedw = sub_wire0[8:0];
wire empty = sub_wire1;
wire [32:0] q = sub_wire2[32:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 33,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module manage_rx(
clk,
reset_n,
////crc_check module interface///
pkt_wrreq,
pkt,
pkt_usedw,
valid_wrreq,
valid,
////pkt insert module interface ////
datapath_pkt_wrreq,
datapath_pkt,
datapath_pkt_usedw,
datapath_valid_wrreq,
datapath_valid,
//////command parse module interface/////////
command_data, //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
command_wr,
command_fifo_full,
sequence_d, //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
sequence_wr,
sequence_fifo_full,
PROXY_MAC,
PROXY_IP,
FPGA_MAC,
FPGA_IP,
proxy_addr_valid
);
input clk;
input reset_n;
////crc_check module interface///
input pkt_wrreq;
input[138:0] pkt;
output [7:0] pkt_usedw;
input valid_wrreq;
input valid;
////pkt insert module interface ////
output datapath_pkt_wrreq;
output[138:0] datapath_pkt;
input [7:0] datapath_pkt_usedw;
output datapath_valid_wrreq;
output datapath_valid;
//////command parse module interface/////////
output [34:0] command_data; //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
output command_wr;
input command_fifo_full;
output [16:0] sequence_d; //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
output sequence_wr;
input sequence_fifo_full;
output [47:0] PROXY_MAC;
output [31:0] PROXY_IP;
output proxy_addr_valid;
input [47:0] FPGA_MAC;
input [31:0] FPGA_IP;
reg datapath_pkt_wrreq;
reg[138:0] datapath_pkt;
reg datapath_valid_wrreq;
reg datapath_valid;
//////command parse module interface/////////
reg [34:0] command_data; //command [34:32]001:��ʾ���ݵ�һ�� 011:��ʾ�����м��� 010:��ʾ��������һ�� 111:��ʾ����ͷβͬ�� [31:0]:����
reg command_wr;
reg [16:0] sequence_d; //[15:0]:�������кţ�[16]:������Ч��־ 1��������Ч 0��������Ч �趪��
reg sequence_wr;
reg [47:0] PROXY_MAC;
reg [31:0] PROXY_IP;
reg proxy_addr_valid;
reg [47:0] S_MAC;//?MAC??
reg [31:0] S_IP; //?IP??
reg [47:0] D_MAC;//add by bhf in 2014.5.24
reg [7:0] protocol;//add by bhf in 2014.5.24
reg [138:0] first_pkt;//add by bhf in 2014.5.24
reg [138:0] second_pkt;//add by bhf in 2014.5.24
reg [138:0] third_pkt;//add by bhf in 2014.5.24
reg [15:0]packet_length;//coammand length
reg [15:0]dip_h16;
reg [138:0]pkt_reg;
reg fifo_wr_permit;
reg empty;
reg fifo_valid;
reg [3:0]state;
parameter idle_s = 4'h0,
command_smac_s = 4'h1,
command_type_s = 4'h2,
command_dip_s = 4'h3,
command0_s = 4'h4,
command1_s = 4'h5,
command2_s = 4'h6,
command3_s = 4'h7,
command4_s = 4'h8,
wr_datapath_s = 4'h9,
wait_s = 4'ha,
discard_s = 4'hb,
wr_fpkt_s = 4'hc,//add by bhf in 2014.5.24
wr_spkt_s = 4'hd,//add by bhf in 2014.5.24
wr_tpkt_s = 4'he;//add by bhf in 2014.5.24
always@(posedge clk or negedge reset_n)
begin
if(~reset_n)begin
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
empty <= 1'b0;
fifo_valid <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
proxy_addr_valid <= 1'b0;
state <= idle_s;
end
else begin
fifo_wr_permit <= ~(command_fifo_full | sequence_fifo_full);// 1:permit
empty <= valid_empty;
fifo_valid <= 1'b0;
case(state)
idle_s:begin
datapath_pkt_wrreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
if(valid_empty==1'b0)begin
if(valid_q==1'b0) begin//invalid pkt
pkt_rdreq<=1'b1;
valid_rdreq<=1'b1;
state <= discard_s;
end
else begin
if(fifo_wr_permit == 1'b1)begin
pkt_rdreq <=1'b1;
valid_rdreq <=1'b1;
state <= command_smac_s;
end
else begin//command fifo afull
pkt_rdreq<=1'b1;
valid_rdreq<=1'b1;
state <= discard_s;
end
end
end
else begin
state <= idle_s;
end
end
command_smac_s:begin
pkt_rdreq<=1'b1;
valid_rdreq <=1'b0;
first_pkt <= pkt_q;//add by bhf in 2014.5.24
D_MAC <= pkt_q[127:80];//add by bhf in 2014.5.24
S_MAC <= pkt_q[79:32];
state <= command_type_s;
end
command_type_s:begin
packet_length <= pkt_q[127:112] - 16'd26;
S_IP <= pkt_q[47:16];
dip_h16 <= pkt_q[15:0];
second_pkt <= pkt_q;//add by bhf in 2014.5.24
protocol <= pkt_q[71:64];//add by bhf in 2014.5.24
pkt_rdreq<=1'b1;
state <= command_dip_s;
end
command_dip_s:begin
pkt_rdreq<=1'b0;
third_pkt <= pkt_q;//add by bhf in 2014.5.24
pkt_reg <= pkt_q;
if(({dip_h16,pkt_q[127:112]}== FPGA_IP) && (D_MAC == FPGA_MAC) && (protocol == 8'd253))//NMAC okt,dest mac and ip is NetMagic
begin
sequence_d[15:0] <= pkt_q[95:80];
command_data[31:0] <= pkt_q[63:32];
command_wr <= 1'b1;
if(pkt_q[63:56]==8'h01)begin//establish
command_data[34:32] <= 3'b100;
PROXY_MAC <= S_MAC;
PROXY_IP <= S_IP;
proxy_addr_valid <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else if ((pkt_q[63:56]==8'h03) || (pkt_q[63:56]==8'h04)) begin//read or write
if(packet_length <= 16'h4)begin//only one cycle command
command_data[34:32] <= 3'b100;
command_wr <= 1'b1;
sequence_d[16] <= 1'b1; //????
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b001;
command_wr <= 1'b1;
sequence_wr <= 1'b0;
packet_length <= packet_length - 4'h4;
state <= command0_s;
end
end
else begin//other nmac pkt is to data path
state <= wr_fpkt_s;
end
end
else begin
state <= wr_fpkt_s;
end
end
wr_fpkt_s:begin
if(datapath_pkt_usedw <= 8'd161)begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= first_pkt;
state <= wr_spkt_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
wr_spkt_s:begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= second_pkt;
state <= wr_tpkt_s;
end
wr_tpkt_s:begin
datapath_pkt_wrreq <= 1'b1;
datapath_pkt <= third_pkt;
pkt_rdreq<=1'b1;
state <= wr_datapath_s;
end
command0_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
pkt_rdreq<=1'b1;
state <= command1_s;
end
end
command1_s:begin
pkt_rdreq<=1'b0;
pkt_reg <= pkt_q;
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_q[127:96];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_q[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_q[127:96];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command2_s;
end
end
command2_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[95:64];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[95:64];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command3_s;
end
end
command3_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[63:32];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[63:32];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
state <= command4_s;
end
end
command4_s:begin
if(packet_length <= 16'h4)begin
command_data[34:32] <= 3'b010;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
sequence_d[16] <= 1'b1;
sequence_wr <= 1'b1;
if(pkt_reg[138:136]==3'b110) begin
state<=wait_s;
end
else begin
pkt_rdreq<=1'b1;
state <= discard_s;
end
end
else begin
command_data[34:32] <= 3'b011;
command_data[31:0] <= pkt_reg[31:0];
command_wr <= 1'b1;
packet_length <= packet_length - 4'h4;
pkt_rdreq<=1'b1;
state <= command1_s;
end
end
wr_datapath_s:begin
valid_rdreq <= 1'b0;
datapath_pkt <= pkt_q;
datapath_pkt_wrreq <= 1'b1;
if(pkt_q[138:136]==3'b110)//tail;
begin
pkt_rdreq<=1'b0;
datapath_valid_wrreq <= 1'b1;
datapath_valid <= 1'b1;
state<=wait_s;
end
else begin
pkt_rdreq <= 1'b1;
state <= wr_datapath_s;
end
end
wait_s:begin//wait the fifo empty signal to 1
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
state <= idle_s;
end
discard_s:begin
datapath_pkt_wrreq <= 1'b0;
pkt_rdreq <= 1'b0;
valid_rdreq <= 1'b0;
datapath_valid_wrreq <= 1'b0;
command_wr <= 1'b0;
sequence_wr <= 1'b0;
if(pkt_q[138:136]==3'b110)//tail;
begin
pkt_rdreq<=1'b0;
state<=wait_s;
end
else
begin
pkt_rdreq<=1'b1;
state<=discard_s;
end
end
endcase
end
end
reg pkt_rdreq;
wire [138:0]pkt_q;
wire [7:0] pkt_usedw;
fifo_256_139 fifo_256_139_manage_rx(
.aclr(!reset_n),
.clock(clk),
.data(pkt),
.rdreq(pkt_rdreq),
.wrreq(pkt_wrreq),
.q(pkt_q),
.usedw(pkt_usedw)
);
reg valid_rdreq;
wire valid_q;
wire valid_empty;
fifo_64_1 fifo_64_1_manage_rx(
.aclr(!reset_n),
.clock(clk),
.data(valid),
.rdreq(valid_rdreq),
.wrreq(valid_wrreq),
.empty(valid_empty),
.q(valid_q)
);
endmodule |
module pkt_gen_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [36:0] data;
input rdreq;
input wrreq;
output empty;
output [36:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire [36:0] sub_wire2;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire [36:0] q = sub_wire2[36:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 37,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule |
module pkt_gen(
clk,
reset_n,
PROXY_MAC,
PROXY_IP,
FPGA_MAC,
FPGA_IP,
proxy_addr_valid,
pkt_to_gen, //[36:34] 001:±íʾÊý¾ÝµÚÒ»ÅÄ 011:±íʾÊý¾ÝÖмäÅÄ 010:±íʾÊý¾Ý×îºóÒ»ÅÄ 100:ͷβͬÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
pkt_to_gen_wr,
pkt_to_gen_afull,
length_to_gen,//[32:24]:ÃüÁîµÄ×ÜÅÄÊý [23:16]:count [15:0]ÐòÁкÅ
length_to_gen_wr,
length_to_gen_afull,
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄ;
// ack_fifo_wrclk,
ack_pkt, //[35:34]01:±íʾÊý¾ÝµÚÒ»ÅÄ 11:±íʾÊý¾ÝÖмäÅÄ 10:±íʾÊý¾Ý×îºóÒ»ÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
ack_wr,
ack_afull,
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄÓÐЧ±ê־λ;Õâ¸öFIFO·Ç¿Õ±íʾ±¨ÎÄFIFOÖÐÖÁÉÙÓÐÒ»¸öÍêÕûµÄ±¨ÎÄÁË
ack_valid_wr,
ack_valid_afull
);
input clk;
input reset_n;
input [47:0] PROXY_MAC;
input [31:0] PROXY_IP;
input [47:0] FPGA_MAC;
input [31:0] FPGA_IP;
input proxy_addr_valid;
input [36:0] pkt_to_gen;//[36:34] 001:±íʾÊý¾ÝµÚÒ»ÅÄ 011:±íʾÊý¾ÝÖмäÅÄ 010:±íʾÊý¾Ý×îºóÒ»ÅÄ 100:ͷβͬÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
input pkt_to_gen_wr;
output pkt_to_gen_afull;
input [32:0] length_to_gen;//[32:24]:ÃüÁîµÄ×ÜÅÄÊý [23:16]:count [15:0]ÐòÁкÅ
input length_to_gen_wr;
output length_to_gen_afull;
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄ;
//output ack_fifo_wrclk;
output[35:0] ack_pkt; //[35:34] 01:±íʾÊý¾ÝµÚÒ»ÅÄ 11:±íʾÊý¾ÝÖмäÅÄ 10:±íʾÊý¾Ý×îºóÒ»ÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
output ack_wr;
input ack_afull;
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄÓÐЧ±ê־λ;Õâ¸öFIFO·Ç¿Õ±íʾ±¨ÎÄFIFOÖÐÖÁÉÙÓÐÒ»¸öÍêÕûµÄ±¨ÎÄÁË
output ack_valid_wr;
input ack_valid_afull;
wire pkt_to_gen_afull;
wire length_to_gen_afull;
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄ;
//wire ack_fifo_wrclk;
reg [35:0] ack_pkt; //[35:34] 01:±íʾÊý¾ÝµÚÒ»ÅÄ 11:±íʾÊý¾ÝÖмäÅÄ 10:±íʾÊý¾Ý×îºóÒ»ÅÄ [33:32]:ÓÐЧ×Ö½ÚÊý [31:0]:±¨ÎÄ
reg ack_wr;
//FPGA·µ»Ø¸ø¹ÜÀí½Ó¿ÚµÄ±¨ÎÄÓÐЧ±ê־λ;Õâ¸öFIFO·Ç¿Õ±íʾ±¨ÎÄFIFOÖÐÖÁÉÙÓÐÒ»¸öÍêÕûµÄ±¨ÎÄÁË
reg ack_valid_wr;
//assign ack_fifo_wrclk = clk;
reg length_to_gen_rdreq;
reg pkt_to_gen_rdreq;
reg ack_afull_reg;
reg ack_valid_afull_reg;
reg [15:0]sequence_number;
reg [7:0] count;
reg [3:0]pad_data_counter;
reg crc_check_end;
reg crc_result_req;
reg crc_gen_status;
reg [31:0] crc_source_data,crc_checksum_data,check_sum_data;
wire [31:0] crc_result_data;
reg [1:0] data_empty;
reg source_data_valid,source_data_sop,source_data_eop,crc_result_valid;
wire crc_valid;
wire[9:0] wrusedw_pkt_gen;
wire [36:0]pkt_to_gen_rdata;
wire pkt_to_gen_empty;
wire[8:0] wrusedw_length_gen;
wire[32:0]length_to_gen_rdata;
wire length_to_gen_empty;
wire ack_fifo_wrpermit;
assign ack_fifo_wrpermit = (~ack_afull_reg) & (~ack_valid_afull_reg);
reg [2:0] checksum_computing_status;
//IPͷЧÑéºÍ¼ÆËã
reg [15:0] packet_number;
reg ip_head_checksum_ack;
reg ip_head_checksum_req;
reg [16:0] ip_checksum;
reg [19:0] check_sum;
reg [15:0] packet_length;
reg [15:0]ip_checksum_result;
//IPͷЧÑéºÍ¼ÆËã״̬»ú
parameter checksum_idle_s = 3'h0,
checksum_1_s = 3'h1,
checksum_2_s = 3'h2,
checksum_3_s = 3'h3,
checksum_4_s = 3'h4,
checksum_5_s = 3'h5,
checksum_end_s = 3'h6;
always @(posedge clk or negedge reset_n)
if(~reset_n) begin
ip_head_checksum_ack <= 1'b0;//IPЧÑéºÍ¼ì²éÇëÇóºÍÓ¦´ð£¬ÎÕÊÖÐźš£
check_sum <= 20'h0_84fe;//4500 + 4000£¨rag flag , Frag segment£© + fffd£¨TTL , and protocol£© = 184fd °Ñ½øλ¼Óµ½×îµÍλ µÃµ½84fe
checksum_computing_status <= checksum_idle_s;
end
else begin
case(checksum_computing_status)
checksum_idle_s: begin
ip_head_checksum_ack <= 1'b0;//IPЧÑéºÍ¼ì²éÇëÇóºÍÓ¦´ð£¬ÎÕÊÖÐźš£
if(proxy_addr_valid) begin
check_sum <= check_sum + FPGA_IP[31:16] + FPGA_IP[15:0]; //Ô´IPµØÖ·µÄ¸ß16λ µÍ16λ
ip_checksum <= PROXY_IP[15:0]+ PROXY_IP[31:16];//Ä¿µÄIPµØÖ·µÍ16λ Ä¿µÄIPµØÖ·¸ß16λ
checksum_computing_status <= checksum_1_s;
end
else begin
checksum_computing_status <= checksum_idle_s;
end
end
checksum_1_s: begin
check_sum <= check_sum + ip_checksum;
checksum_computing_status <= checksum_2_s;
end
checksum_2_s: begin
if(|check_sum[19:16] == 1'b1) begin
check_sum <= check_sum[15:0] + check_sum[19:16];
checksum_computing_status <= checksum_2_s;
end
else
checksum_computing_status <= checksum_3_s;
end
checksum_3_s: begin
if(ip_head_checksum_req == 1'b1) begin
ip_checksum <= check_sum[15:0] + packet_number;
checksum_computing_status <= checksum_4_s;
end
else
checksum_computing_status <= checksum_3_s;
end
checksum_4_s: begin
ip_checksum <= ip_checksum[15:0] + packet_length + ip_checksum[16];
checksum_computing_status <= checksum_5_s;
end
checksum_5_s: begin
if(ip_checksum[16] == 1'b1) begin
ip_checksum <= ip_checksum[15:0] + ip_checksum[16];
checksum_computing_status <= checksum_5_s;
end
else begin
checksum_computing_status <= checksum_end_s;
ip_head_checksum_ack <= 1'b1;
ip_checksum_result <= ~ip_checksum[15:0];
end
end
checksum_end_s: begin
if(ip_head_checksum_req) begin
ip_head_checksum_ack <= 1'b1;
checksum_computing_status <= checksum_end_s;
end
else begin
ip_head_checksum_ack <= 1'b0;
check_sum <= 20'h0_84fe;
checksum_computing_status <= checksum_idle_s;
end
end
default : begin
ip_head_checksum_ack <= 1'b0;
checksum_computing_status <= checksum_idle_s;
end
endcase
end
parameter idle_s = 4'h0,
wr0_s = 4'h1,
wr1_s = 4'h2,
wr2_s = 4'h3,
wr3_s = 4'h4,
wr4_s = 4'h5,
wr5_s = 4'h6,
wr6_s = 4'h7,
wr7_s = 4'h8,
wr8_s = 4'h9,
wr9_s = 4'ha,
wr10_s = 4'hb,
wr11_s = 4'hc,
add_pad_s = 4'hd,
wait_crc_s = 4'he;
reg [3:0]gen_pkt_state;
always@(posedge clk or negedge reset_n)
begin
if(!reset_n)
begin
ack_wr <= 1'b0;
ack_valid_wr <= 1'b0;
length_to_gen_rdreq <= 1'b0;
pkt_to_gen_rdreq <= 1'b0;
packet_number <= 16'h0;
gen_pkt_state <= idle_s;
end
else begin
ack_afull_reg <= ack_afull;
ack_valid_afull_reg <= ack_valid_afull;
case(gen_pkt_state)
idle_s:
begin
ack_wr <= 1'b0;
ack_valid_wr <= 1'b0;
length_to_gen_rdreq <= 1'b0;
pkt_to_gen_rdreq <= 1'b0;
pad_data_counter <= 4'h0;
if(ack_fifo_wrpermit&(!pkt_to_gen_empty)&(!length_to_gen_empty))
begin
length_to_gen_rdreq <= 1'b1;
ip_head_checksum_req <= 1'b1;
packet_number <= packet_number + 1'b1;
packet_length <= {length_to_gen_rdata[32:24],2'b0} + 16'h1a;//ÃüÁî×ÜÅÄÊý³ËÒÔ4 ¼ÓÉÏ20×Ö½ÚµÄIPÍ· ¼ÓÉÏÃüÁîÊý ÐòÁкŠ6×Ö½Ú
count <= length_to_gen_rdata[23:16];
sequence_number <= length_to_gen_rdata[15:0];
gen_pkt_state <= wr0_s;
end
else
begin
pkt_to_gen_rdreq <= 1'b0;
length_to_gen_rdreq <= 1'b0;
gen_pkt_state <= idle_s;
end
end
wr0_s:begin//Ä¿µÄMAC
length_to_gen_rdreq <= 1'b0;
ack_pkt <= {4'h4,PROXY_MAC[47:16]};
ack_wr <= 1'b1;
gen_pkt_state <= wr1_s;
end
wr1_s: begin
ack_pkt <= {4'hc,PROXY_MAC[15:0],FPGA_MAC[47:32]};
ack_wr <= 1'b1;
gen_pkt_state <= wr2_s;
end
wr2_s:begin//Ô´MAC
ack_pkt <= {4'hc,FPGA_MAC[31:0]};
ack_wr <= 1'b1;
gen_pkt_state <= wr3_s;
end
wr3_s:begin//0800 4500
ack_pkt <= {4'hc,32'h0800_4500};
ack_wr <= 1'b1;
gen_pkt_state <= wr4_s;
end
wr4_s:begin//×ܳ¤¶È¡¢±êʶ
ack_pkt <= {4'hc,packet_length,packet_number};
ack_wr <= 1'b1;
gen_pkt_state <= wr5_s;
end
wr5_s:begin//±ê¼Ç Ƭ¶ÎÆ«ÒÆ Éú´æÆÚ ÐÒé 4000 fffd
ack_pkt <= {4'hc,32'h4000_fffd};
ack_wr <= 1'b1;
gen_pkt_state <= wr6_s;
end
wr6_s:begin//IPͷУÑéºÍ¡¢Ô´IP¸ß16λ
if(ip_head_checksum_ack)begin
ack_pkt <= {4'hc,ip_checksum_result,FPGA_IP[31:16]};
ack_wr <= 1'b1;
ip_head_checksum_req <= 1'b0;
gen_pkt_state <= wr7_s;
end
else begin
ack_wr <= 1'b0;
gen_pkt_state <= wr6_s;
end
end
wr7_s:begin
ack_pkt <= {4'hc,FPGA_IP[15:0],PROXY_IP[31:16]};
ack_wr <= 1'b1;
gen_pkt_state <= wr8_s;
end
wr8_s:begin
ack_pkt <= {4'hc,PROXY_IP[15:0],count,8'b0};
ack_wr <= 1'b1;
gen_pkt_state <= wr9_s;
end
wr9_s:begin
ack_pkt <= {4'hc,sequence_number,16'b0};
ack_wr <= 1'b1;
pkt_to_gen_rdreq <= 1'b1;
gen_pkt_state <= wr10_s;
end
wr10_s:begin
if(pkt_to_gen_rdata[36:34]==3'b100)
begin
pkt_to_gen_rdreq <= 1'b0;
ack_pkt <= {2'h3,pkt_to_gen_rdata[33:0]};
pad_data_counter <= 1'h1 + pad_data_counter;
ack_wr <= 1'b1;
gen_pkt_state <= add_pad_s;
end
else //if(pkt_to_gen_rdata[36:34]==3'b001)
begin
ack_pkt <= {2'h3,pkt_to_gen_rdata[33:0]};
ack_wr <= 1'b1;
pad_data_counter <= 1'h1 + pad_data_counter;
pkt_to_gen_rdreq <= 1'b1;
gen_pkt_state <= wr11_s;
end
end
wr11_s:
begin
if(pkt_to_gen_rdata[36:34]==3'b010)
begin
ack_pkt <= {2'h3,pkt_to_gen_rdata[33:0]};
pad_data_counter <= 1'h1 + pad_data_counter;
ack_wr <= 1'b1;
pkt_to_gen_rdreq <= 1'b0;
if(pad_data_counter>=4'h4)
begin
crc_check_end <= 1'b1;
gen_pkt_state <= wait_crc_s;
end
else
begin
pkt_to_gen_rdreq <= 1'b0;
gen_pkt_state <= add_pad_s;
end
end
else
begin
ack_pkt <= {2'h3,pkt_to_gen_rdata[33:0]};
pad_data_counter <= 1'h1 + pad_data_counter;
ack_wr <= 1'b1;
pkt_to_gen_rdreq <= 1'b1;
gen_pkt_state <= wr11_s;
end
end
add_pad_s:begin
pkt_to_gen_rdreq <= 1'b0;
pad_data_counter <= 1'h1 + pad_data_counter;
ack_pkt[35:0] <= 36'hc_0000_0000;
ack_wr <= 1'b1; //Ó¦¸ÃÊÇËĸö×Ö½ÚÈ«ÓÐЧ
if(pad_data_counter == 4'h4)
begin //²¹³ä6ÅÄÊý¾Ý£¬µ½64×Ö½Ú£¡
gen_pkt_state <= wait_crc_s;
crc_check_end <= 1'b1;
end
else
begin
crc_check_end <= 1'b0;
gen_pkt_state <= add_pad_s;
end
end
wait_crc_s: begin
pkt_to_gen_rdreq <= 1'b0;
crc_check_end <= 1'b0;
if(crc_result_req == 1'b1)
begin
ack_pkt <= {4'h8,check_sum_data[7:0],check_sum_data[15:8],check_sum_data[23:16],check_sum_data[31:24]};
ack_wr <= 1'b1;
ack_valid_wr <= 1'b1;
gen_pkt_state <= idle_s;
end
else
begin
ack_wr <= 1'b0;
gen_pkt_state <= wait_crc_s;
end
end
default:begin
ack_wr <= 1'b0;
ack_valid_wr <= 1'b0;
length_to_gen_rdreq <= 1'b0;
pkt_to_gen_rdreq <= 1'b0;
packet_number <= 16'h0;
gen_pkt_state <= idle_s;
end
endcase
end
end
parameter crc_gen_ip_packet = 1'b0,
crc_gen_wait_result = 1'b1;
always @(posedge clk or negedge reset_n)
if(!reset_n ) begin
source_data_valid <= 1'b0;
source_data_sop <= 1'b0;
source_data_eop <= 1'b0;
crc_result_valid <= 1'b0;
data_empty <= 2'h0;
crc_result_req <= 1'b0;
crc_gen_status <= crc_gen_ip_packet;
end
else begin
crc_result_valid <= crc_valid;
crc_checksum_data <= crc_result_data;
case(crc_gen_status)
crc_gen_ip_packet:
begin
crc_result_req <= 1'b0;
case({crc_check_end,ack_wr,ack_pkt[35:34]})
4'b0101:
begin
source_data_valid <= 1'b1;
source_data_sop <= 1'b1;
crc_source_data <= ack_pkt[31:0];
crc_gen_status <= crc_gen_ip_packet;
end
4'b0111:
begin
source_data_valid <= 1'b1;
source_data_sop <= 1'b0;
crc_source_data <= ack_pkt[31:0];
crc_gen_status <= crc_gen_ip_packet;
end
4'b1111:
begin
source_data_valid <= 1'b1;
source_data_sop <= 1'b0;
crc_source_data <= ack_pkt[31:0];
crc_gen_status <= crc_gen_wait_result;
source_data_eop <= 1'b1;
data_empty <= 2'b0;
end
4'b1110:
begin
source_data_valid <= 1'b1;
source_data_sop <= 1'b0;
crc_source_data <= ack_pkt[31:0];
crc_gen_status <= crc_gen_wait_result;
source_data_eop <= 1'b1;
data_empty <= 2'b0;
end
default:
begin
source_data_valid <= 1'b0;
crc_gen_status <= crc_gen_ip_packet;
end
endcase
end
crc_gen_wait_result:
begin
source_data_valid <= 1'b0;
source_data_eop <= 1'b0;
data_empty <= 2'h0;
if(crc_result_valid == 1'b1)
begin
crc_result_req <= 1'b1;
check_sum_data <= crc_checksum_data;
crc_gen_status <= crc_gen_ip_packet; //CRCÉú³É½áÊø
end
else
begin
crc_result_req <= 1'b0;
crc_gen_status <= crc_gen_wait_result;
end
end
default:
begin
data_empty <= 2'h0;
source_data_valid <= 1'b0;
source_data_sop <= 1'b0;
source_data_eop <= 1'b0;
crc_result_valid <= 1'b0;
data_empty <= 2'h0;
crc_gen_status <= crc_gen_ip_packet;
end
endcase
end
crc32_gen My_CRC32_GEN(
.clk(clk),
.data(crc_source_data),
.datavalid(source_data_valid),
.empty(data_empty),
.endofpacket(source_data_eop),
.reset_n(reset_n),
.startofpacket(source_data_sop),
.checksum(crc_result_data),
.crcvalid(crc_valid)
);
//FIFOʵÀý»¯/////////
pkt_gen_fifo pkt_gen_fifo(
.aclr(!reset_n),
.data(pkt_to_gen),
.clock(clk),
.rdreq(pkt_to_gen_rdreq),
.wrreq(pkt_to_gen_wr),
.q(pkt_to_gen_rdata),
.empty(pkt_to_gen_empty),
.usedw(wrusedw_pkt_gen));
assign pkt_to_gen_afull = (wrusedw_pkt_gen > 10'd650)?1'b1:1'b0;
length_gen_fifo length_gen_fifo(
.aclr(!reset_n),
.data(length_to_gen),
.clock(clk),
.rdreq(length_to_gen_rdreq),
.wrreq(length_to_gen_wr),
.q(length_to_gen_rdata),
.empty(length_to_gen_empty),
.usedw(wrusedw_length_gen));
assign length_to_gen_afull = (wrusedw_length_gen > 9'd510)?1'b1:1'b0;
endmodule |
module com_valid_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [16:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [16:0] q;
output rdempty;
output [8:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [8:0] sub_wire1;
wire [16:0] sub_wire2;
wire rdempty = sub_wire0;
wire [8:0] wrusedw = sub_wire1[8:0];
wire [16:0] q = sub_wire2[16:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 17,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
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