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module bcd_nibble (daa, dsa, sb, bcd, b1, b2);
input daa;
input dsa;
input [3:0] sb;
output [3:0] bcd;
input b1;
input b2;
assign bcd[0] = sb[0];
xor (bcd[1], ~(daa|dsa), ~sb[1]);
xor (bcd[2], ((~(b1&daa)) & (~(~b1&dsa))), ~sb[2]);
wire t1, t2;
nand (t1, b1, b2);
nor (t2, b1, b2);
xor (bcd[3], ((~(t1&daa)) & (~(~t2&dsa))), ~sb[3]);
endmodule // bcd_nibble |
module ALU_Control (
PHI1, PHI2,
BRFW, n_ready, BRK6E, STKOP, PGX,
X,
T0, T1, T6, T7,
n_DOUT, n_COUT,
INC_SB, SR, AND,
NDB_ADD, DB_ADD, Z_ADD, SB_ADD, ADL_ADD, ADD_SB06, ADD_SB7, ADD_ADL, ANDS, EORS, ORS, SRS, SUMS, n_ACIN, n_DAA, n_DSA);
input PHI1;
input PHI2;
input BRFW;
input n_ready;
input BRK6E;
input STKOP;
input PGX;
input [129:0] X;
input T0;
input T1;
input T6;
input T7;
input n_DOUT;
input n_COUT;
output INC_SB;
output SR;
output AND;
output NDB_ADD;
output DB_ADD;
output Z_ADD;
output SB_ADD;
output ADL_ADD;
output ADD_SB06;
output ADD_SB7;
output ADD_ADL;
output ANDS;
output EORS;
output ORS;
output SRS;
output SUMS;
output n_ACIN;
output n_DAA;
output n_DSA;
// Implementation
wire SBC0;
wire BRX;
wire CSET;
wire OR;
wire NOADL;
wire sb_add; // internal #SB/ADD
wire n_ndb_add; // internal #NDB/ADD
wire n_adl_add; // internal #ADL/ADD
wire EOR;
wire D_OUT;
wire nADDSB06;
wire nADDSB7;
assign SBC0 = X[51];
or (BRX, X[49], X[50], ~(~X[93]|BRFW));
assign CSET = ~((~((~(n_COUT|(~(T0|T6))))&(X[52]|X[53])))&~X[54]);
or (OR, X[32], n_ready);
or (AND, X[69], X[70]);
or (SR, X[75], (X[76]&T6));
nor (NOADL, X[84], X[85], X[86], X[87], X[88], X[89], X[26]);
or (INC_SB, X[39], X[40], X[41], X[42], X[43], (X[44]&T6));
nor (sb_add, X[30], X[31], X[45], X[48], INC_SB, X[47], BRK6E, n_ready);
nand (n_ndb_add, (BRX|X[56]|SBC0), ~n_ready);
nor (n_adl_add, (X[33]&~X[34]), X[35], X[36], X[37], X[38], X[39], n_ready);
assign EOR = X[29];
assign D_OUT = ~n_DOUT;
nor (nADDSB06, STKOP, X[56], PGX, T1, T7);
// Carry in
wire acin_latch1_q;
wire acin_latch2_q;
wire acin_latch3_q;
wire acin_latch4_q;
wire acin_latch5_nq;
dlatch acin_latch1 (.d(~(n_adl_add|~X[47])), .en(PHI2), .q(acin_latch1_q));
dlatch acin_latch2 (.d(INC_SB), .en(PHI2), .q(acin_latch2_q));
dlatch acin_latch3 (.d(BRX), .en(PHI2), .q(acin_latch3_q));
dlatch acin_latch4 (.d(CSET), .en(PHI2), .q(acin_latch4_q));
dlatch acin_latch5 (.d(~(acin_latch1_q|acin_latch2_q|acin_latch3_q|acin_latch4_q)), .en(PHI1), .nq(acin_latch5_nq));
assign n_ACIN = ~acin_latch5_nq;
// ->ADD
wire ndbadd_latch_q;
wire dbadd_latch_q;
wire zadd_latch_q;
wire sbadd_latch_q;
wire adladd_latch_q;
dlatch ndbadd_latch (.d(n_ndb_add), .en(PHI2), .q(ndbadd_latch_q));
dlatch dbadd_latch (.d(~(n_ndb_add&n_adl_add)), .en(PHI2), .q(dbadd_latch_q));
dlatch zadd_latch (.d(sb_add), .en(PHI2), .q(zadd_latch_q));
dlatch sbadd_latch (.d(~sb_add), .en(PHI2), .q(sbadd_latch_q));
dlatch adladd_latch (.d(n_adl_add), .en(PHI2), .q(adladd_latch_q));
nor (NDB_ADD, ndbadd_latch_q, PHI2);
nor (DB_ADD, dbadd_latch_q, PHI2);
nor (Z_ADD, zadd_latch_q, PHI2);
nor (SB_ADD, sbadd_latch_q, PHI2);
nor (ADL_ADD, adladd_latch_q, PHI2);
// ALU ops
wire ands_latch1_nq;
wire eors_latch1_nq;
wire ors_latch1_nq;
wire srs_latch1_nq;
wire sums_latch1_nq;
dlatch ands_latch1 (.d(AND), .en(PHI2), .nq(ands_latch1_nq));
dlatch ands_latch2 (.d(ands_latch1_nq), .en(PHI1), .nq(ANDS));
dlatch eors_latch1 (.d(EOR), .en(PHI2), .nq(eors_latch1_nq));
dlatch eors_latch2 (.d(eors_latch1_nq), .en(PHI1), .nq(EORS));
dlatch ors_latch1 (.d(OR), .en(PHI2), .nq(ors_latch1_nq));
dlatch ors_latch2 (.d(ors_latch1_nq), .en(PHI1), .nq(ORS));
dlatch srs_latch1 (.d(SR), .en(PHI2), .nq(srs_latch1_nq));
dlatch srs_latch2 (.d(srs_latch1_nq), .en(PHI1), .nq(SRS));
dlatch sums_latch1 (.d(~(AND|EOR|OR|SR)), .en(PHI2), .nq(sums_latch1_nq));
dlatch sums_latch2 (.d(sums_latch1_nq), .en(PHI1), .nq(SUMS));
// BCD
wire DAATemp;
wire DSATemp;
wire daa_latch1_nq;
wire dsa_latch1_nq;
assign DAATemp = ~(~(~(X[52]&D_OUT)|SBC0));
nand (DSATemp, D_OUT, SBC0);
dlatch daa_latch1 (.d(DAATemp), .en(PHI2), .nq(daa_latch1_nq));
dlatch daa_latch2 (.d(daa_latch1_nq), .en(PHI1), .nq(n_DAA));
dlatch dsa_latch1 (.d(DSATemp), .en(PHI2), .nq(dsa_latch1_nq));
dlatch dsa_latch2 (.d(dsa_latch1_nq), .en(PHI1), .nq(n_DSA));
// ADD->
dlatch addsb7_latch (.d(~(nADDSB06|nADDSB7)), .en(PHI2), .q(ADD_SB7)); // care!
dlatch addsb06_latch (.d(nADDSB06), .en(PHI2), .nq(ADD_SB06));
dlatch addadl_latch (.d(~(~(NOADL|PGX))), .en(PHI2), .nq(ADD_ADL));
// https://www.youtube.com/watch?v=Uk_QC1eU0Fg
ROR_Unit ror (.PHI1(PHI1), .PHI2(PHI2), .n_COUT(n_COUT), .n_ready(n_ready), .SR(SR), .n_ROR(~X[27]), .nADDSB7(nADDSB7) );
endmodule // ALU_Control |
module ROR_Unit (PHI1, PHI2, n_COUT, n_ready, SR, n_ROR, nADDSB7);
input PHI1;
input PHI2;
input n_COUT;
input n_ready;
input SR;
input n_ROR;
output nADDSB7;
wire cout_latch_nq;
wire nready_latch_q;
wire mux_latch1_q;
wire ff_latch1_nq;
wire ff_latch2_q;
wire sr_latch1_nq;
wire sr_latch2_q;
wire mux_latch_in;
nor (mux_latch_in, nready_latch_q, ~SR);
wire ff1_d;
assign ff1_d = ~(mux_latch1_q ? cout_latch_nq : ff_latch2_q);
dlatch cout_latch (.d(~n_COUT), .en(PHI2), .nq(cout_latch_nq));
dlatch nready_latch (.d(n_ready), .en(PHI1), .q(nready_latch_q));
dlatch mux_latch1 (.d(mux_latch_in), .en(PHI2), .q(mux_latch1_q));
dlatch ff_latch1 (.d(ff1_d), .en(PHI1), .nq(ff_latch1_nq));
dlatch ff_latch2 (.d(ff_latch1_nq), .en(PHI2), .q(ff_latch2_q));
dlatch sr_latch1 (.d(SR), .en(PHI2), .nq(sr_latch1_nq));
dlatch sr_latch2 (.d(sr_latch1_nq), .en(PHI1), .q(sr_latch2_q));
nor (nADDSB7, ff_latch1_nq, sr_latch2_q, n_ROR);
endmodule // ROR_Unit |
module BranchLogic (
PHI1, PHI2,
n_IR5, X, n_COUT, n_VOUT, n_NOUT, n_ZOUT, DB, BR2,
n_BRTAKEN, BRFW);
input PHI1;
input PHI2;
input n_IR5;
input [129:0] X;
input n_COUT;
input n_VOUT;
input n_NOUT;
input n_ZOUT;
inout [7:0] DB;
input BR2;
output n_BRTAKEN;
output BRFW;
// Branch forward
wire br2_latch_q;
wire br2_latch_nq;
wire brfw_latch1_nq;
wire brfw_latch2_q;
wire brfw_latch1_d;
dlatch br2_latch (.d(BR2), .en(PHI2), .q(br2_latch_q), .nq(br2_latch_nq));
nor (brfw_latch1_d, br2_latch_q & ~DB[7], br2_latch_nq & brfw_latch2_q);
dlatch brfw_latch1 (.d(brfw_latch1_d), .en(PHI1), .nq(brfw_latch1_nq));
dlatch brfw_latch2 (.d(brfw_latch1_nq), .en(PHI2), .q(brfw_latch2_q));
not (BRFW, brfw_latch1_nq);
// Branch taken
wire n_IR6;
wire IR6;
wire n_IR7;
wire IR7;
assign n_IR6 = X[121];
assign n_IR7 = X[126];
not (IR6, n_IR6);
not (IR7, n_IR7);
// The flag test logic is a 2-4 multiplexer
wire ctest;
wire vtest;
wire ntest;
wire ztest;
nor (ctest, IR6, n_IR7, n_COUT);
nor (vtest, n_IR6, IR7, n_VOUT);
nor (ntest, IR6, IR7, n_NOUT);
nor (ztest, n_IR6, n_IR7, n_ZOUT);
wire mux_out;
nor (mux_out, ctest, vtest, ntest, ztest);
xor (n_BRTAKEN, mux_out, n_IR5);
endmodule // BranchLogic |
module AclkGenStandalone (CLK, RES, PHI1, ACLK1, nACLK2);
input CLK;
input RES;
output PHI1; // Sometimes it is required from the outside (triangle channel for example)
output ACLK1;
output nACLK2;
wire PHI0;
wire PHI2;
// The ACLK pattern requires all of these "spares".
CLK_Divider div (
.n_CLK_frompad(~CLK),
.PHI0_tocore(PHI0));
BogusCorePhi phi (.PHI0(PHI0), .PHI1(PHI1), .PHI2(PHI2));
ACLKGen clkgen (
.PHI1(PHI1),
.PHI2(PHI2),
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES));
endmodule // AclkGenStandalone |
module BogusCorePhi (PHI0, PHI1, PHI2);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule // BogusCorePhi |
module BogusLFO (CLK, RES, nACLK2, LFO);
input CLK;
input RES;
input nACLK2;
output reg LFO; // inverse polarity (0: LFO triggers)
reg [1:0] cnt;
wire [1:0] n_cnt;
wire all_ones;
initial begin
cnt <= 0;
end
always @ (negedge nACLK2) begin
cnt <= cnt + 1;
LFO <= all_ones && ~RES ? 1'b0 : 1'b1;
end
always @ (posedge CLK)
LFO <= 1'b1;
assign n_cnt = ~cnt;
nor (all_ones, n_cnt[0], n_cnt[1]);
endmodule // BogusLFO |
module AUX (AUX_A, AUX_B, AOut, BOut);
input [7:0] AUX_A; // Digital input AUX A {SQB[3:0],SQA[3:0]}
input [14:0] AUX_B; // Digital input AUX B {DMC[6:0],RND[3:0],TRI[3:0]}
output [31:0] AOut; // Analog output AUX A (float)
output [31:0] BOut; // Analog output AUX B (float)
reg [31:0] auxa_rom [0:255];
reg [31:0] auxb_rom [0:32767];
initial begin
$readmemh("auxa.mem", auxa_rom);
$readmemh("auxb.mem", auxb_rom);
end
assign AOut = auxa_rom[AUX_A];
assign BOut = auxb_rom[AUX_B];
endmodule // AUX |
module AUX_Dumper (addr, val);
input [23:0] addr;
input [31:0] val;
reg [31:0] mem [0:16777215];
integer i;
initial begin
for (i = 0; i<16777216; i=i+1) begin
mem[i] = 32'h00000000;
end
end
always @(*) mem[addr] = val;
endmodule |
module TestCounters_Run();
reg CLK;
reg DownCount;
always #25 CLK = ~CLK;
UpCounterTest up_counter (.CLK(CLK));
DownCounterTest down_counter (.CLK(CLK));
RevCounterTest rev_counter (.CLK(CLK), .DownCount(DownCount));
initial begin
CLK <= 1'b0;
$dumpfile("test_counters.vcd");
$dumpvars(0, up_counter);
$dumpvars(1, down_counter);
$dumpvars(2, rev_counter);
DownCount <= 1'b0;
repeat (256) @ (posedge CLK);
DownCount <= 1'b1;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // TestCounters_Run |
module UpCounterTest(CLK);
input CLK;
wire [7:0] carry_chain;
wire [7:0] q;
CounterBit cnt [7:0] (
.ACLK1(~CLK),
.clear(1'b0),
.step(CLK),
.load(1'b0),
.q(q),
.cin({carry_chain[6:0], 1'b1}),
.cout(carry_chain) );
endmodule // UpCounterTest |
module RevCounterTest(CLK, DownCount);
input CLK;
input DownCount;
wire [7:0] carry_chain;
wire [7:0] q;
RevCounterBit cnt [7:0] (
.ACLK1(~CLK),
.clear(1'b0),
.step(CLK),
.load(1'b0),
.q(q),
.dec(DownCount),
.cin({carry_chain[6:0], 1'b1}),
.cout(carry_chain) );
endmodule // UpCounterTest |
module Core6502 (n_NMI, n_IRQ, n_RES, PHI0, PHI1, PHI2, RDY, SO, RnW, SYNC, A, D);
input n_NMI; // Non-maskable interrupt signal, active low
input n_IRQ; // Maskable interrupt signal, active low
input n_RES; // Reset signal, active low
input PHI0; // Reference clock signal
output PHI1; // First half-cycle, processor in `Set RW / Address` mode
output PHI2; // Second half-cycle, processor in `Read/Write Data` mode
input RDY; // Processor Ready (1: ready)
input SO; // Forced setting of the overflow flag (V)
output RnW; // Data bus direction (R/W=1: processor reads data, R/W=0: processor writes)
output SYNC; // The processor is on cycle T1 (opcode fetch)
output [15:0] A; // Address bus
inout [7:0] D; // Data bus (bidirectional)
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
assign SYNC = 1'b0;
reg [31:0] regdump_rom [0:32767];
wire [23:0] regdump_addr;
initial begin
$readmemh("regdump.mem", regdump_rom);
end
RegDumpProcessor rp (
.PHI0(PHI0),
.n_RES(n_RES),
.RnW(RnW),
.addr_bus(A),
.data_bus(D),
.regdump_data(regdump_rom[regdump_addr]),
.regdump_addr(regdump_addr) );
endmodule // Core6502 |
module RegDumpProcessor (PHI0, n_RES, RnW, addr_bus, data_bus, regdump_data, regdump_addr);
input PHI0; // Core PHI0
input n_RES; // Core #RES
output RnW; // Core R/W
output [15:0] addr_bus; // Core address bus
inout [7:0] data_bus; // Core data bus
input [31:0] regdump_data; // Data bus for external asynchronous memory where registers dump is stored (`APULogEntry` entries)
output [23:0] regdump_addr; // Address bus for external asynchronous memory
reg [31:0] phi_dec_cnt; // PHI delta down-counter
reg [31:0] delta_phi_word; // word[0] from regdump
reg [31:0] regop_word; // word[1] from regdump
reg cnt_ovf_reg;
reg [31:0] addr_cnt; // negedge
wire cntz; // 1: Counter is zero
wire deltanz; // 1: Delta PHI is NOT zero
wire inc_address; // 1: Increment addr_cnt
wire DoRegOp; // 1: Issue register operation
wire LoadPhiCounter; // 1: Reload PHI decrement counter
wire [15:0] RegAddress;
wire [7:0] RegValue; // if write
wire ReadMode; // 1: read register
initial begin
phi_dec_cnt <= 0;
delta_phi_word <= 0;
regop_word <= 0;
cnt_ovf_reg <= 0;
addr_cnt <= 0;
end
// Counter + control words
always @(posedge PHI0) begin
delta_phi_word <= regdump_data;
if (LoadPhiCounter) regop_word <= 0;
if (LoadPhiCounter) phi_dec_cnt <= regdump_data >= 2 ? regdump_data - 2 : 0; // Take into account 2 cycles on the RegDump logic
else if (n_RES) phi_dec_cnt <= phi_dec_cnt - 1;
cnt_ovf_reg <= cntz;
end
assign cntz = phi_dec_cnt == 0;
assign LoadPhiCounter = cnt_ovf_reg & n_RES;
assign deltanz = delta_phi_word != 0;
assign DoRegOp = (PHI0 & deltanz & cntz & ~LoadPhiCounter & n_RES);
assign inc_address = DoRegOp | LoadPhiCounter;
always @(posedge DoRegOp) begin
regop_word <= regdump_data;
end
always @(negedge inc_address) begin
if (n_RES) addr_cnt <= addr_cnt + 1;
end
// RegOp
assign RegAddress = 'h4000 | ({11'b0, regop_word[4:0]});
assign RegValue = regop_word[15:8];
assign ReadMode = regop_word[7];
// Default core mode: read address 0
assign RnW = DoRegOp ? ReadMode : 1'b1;
assign addr_bus = DoRegOp ? RegAddress : 16'b0;
assign data_bus = (DoRegOp & ~ReadMode) ? RegValue : 8'bz;
assign regdump_addr = addr_cnt;
endmodule // RegDumpProcessor |
module VidOut_Run ();
reg CLK;
reg RES;
wire PCLK;
wire n_PCLK;
wire [8:0] HCnt;
wire [8:0] VCnt;
wire [23:0] HDecoder_out;
wire [9:0] VDecoder_out;
wire HC;
wire VC;
wire V_IN;
wire VB;
wire BLNK;
// Tune CLK/PCLK timing according to 2C02/2C07
`ifdef RP2C02
always #23.28 CLK = ~CLK;
`elsif RP2C07
always #18.79 CLK = ~CLK;
`else
always #1 CLK = ~CLK;
`endif
PixelClock pclk (
.n_CLK(~CLK), .CLK(CLK), .RES(RES),
.n_PCLK(n_PCLK), .PCLK(PCLK) );
HVCounters hv (
.n_PCLK(n_PCLK), .PCLK(PCLK),
.RES(RES), .HC(HC), .VC(VC), .V_IN(V_IN),
.H_out(HCnt), .V_out(VCnt) );
HVDecoder dec (
.H_in(HCnt), .V_in(VCnt), .VB(VB), .BLNK(BLNK),
.HPLA_out(HDecoder_out), .VPLA_out(VDecoder_out) );
// VideoGen
wire [10:0] RawVOut;
VideoGen vidgen (
.n_CLK(~CLK), .CLK(CLK), .n_PCLK(n_PCLK), .PCLK(PCLK),
.RES(RES),
.n_CC(4'b0100), .n_LL(2'b00),
.BURST(1'b0), .SYNC(1'b0), .n_PICTURE(1'b0),
.n_TR(1'b0), .n_TG(1'b0), .n_TB(1'b0),
`ifdef RP2C07
.V0(VCnt[0]),
`endif
.RawVOut(RawVOut) );
initial begin
$dumpfile("vidout_test.vcd");
$dumpvars(0, VidOut_Run);
CLK <= 1'b0;
RES <= 1'b0;
// Run the number of cycles
repeat (1000) @ (posedge CLK);
$finish;
end
endmodule // VidOut_Run |
module FSM_Run ();
reg CLK;
reg RES;
wire PCLK;
wire n_PCLK;
wire [8:0] HCnt;
wire [8:0] VCnt;
wire [23:0] HDecoder_out;
wire [9:0] VDecoder_out;
wire HC;
wire VC;
wire V_IN;
wire VB;
wire BLNK;
// Tune CLK/PCLK timing according to 2C02/2C07
`ifdef RP2C02
always #23.28 CLK = ~CLK;
`elsif RP2C07
always #18.79 CLK = ~CLK;
`else
always #1 CLK = ~CLK;
`endif
PixelClock pclk (
.n_CLK(~CLK), .CLK(CLK), .RES(RES),
.n_PCLK(n_PCLK), .PCLK(PCLK) );
HVCounters hv (
.n_PCLK(n_PCLK), .PCLK(PCLK),
.RES(RES), .HC(HC), .VC(VC), .V_IN(V_IN),
.H_out(HCnt), .V_out(VCnt) );
HVDecoder dec (
.H_in(HCnt), .V_in(VCnt), .VB(VB), .BLNK(BLNK),
.HPLA_out(HDecoder_out), .VPLA_out(VDecoder_out) );
// There is no need to connect all FSM output signals, they will be perfectly visible in the .vcd dump
PPU_FSM fsm (
.n_PCLK(n_PCLK), .PCLK(PCLK),
.H_out(HCnt), .V_out(VCnt), .HPLA_out(HDecoder_out), .VPLA_out(VDecoder_out),
.RES(RES), .VBL_EN(1'b0), .n_R2(1'b1), .n_DBE(1'b1), .n_OBCLIP(1'b0), .n_BGCLIP(1'b0), .BLACK(1'b0),
.VB(VB), .BLNK(BLNK),
.V_IN(V_IN), .HC(HC), .VC(VC) );
initial begin
`ifdef RP2C02
$dumpfile("fsm_test_ntsc.vcd");
`elsif RP2C07
$dumpfile("fsm_test_pal.vcd");
`else
$display("wtf?");
$finish;
`endif
$dumpvars(0, FSM_Run);
CLK <= 1'b0;
RES <= 1'b0;
// Run the number of cycles sufficient to capture the full field.
`ifdef RP2C02
repeat (2048 * 262) @ (posedge CLK);
`elsif RP2C07
repeat (2048 * 312) @ (posedge CLK);
`else
`endif
$finish;
end
endmodule // FSM_Run |
module busmux_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] SB, DB, ADL, ADH;
BusMux busmux (
.PHI2(PHI2),
.SB(SB),
.DB(DB),
.ADL(ADL),
.ADH(ADH),
.Z_ADL0(1'b0),
.Z_ADL1(1'b0),
.Z_ADL2(1'b0),
.Z_ADH0(1'b0),
.Z_ADH17(1'b0),
.SB_DB(1'b0),
.SB_ADH(1'b0) );
initial begin
$dumpfile("busmux_test.vcd");
$dumpvars(0, busmux_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // busmux_test |
module regs_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] SB, ADL;
Regs regs (
.PHI2(PHI2),
.Y_SB(1'b0),
.SB_Y(1'b0),
.X_SB(1'b0),
.SB_X(1'b0),
.S_SB(1'b0),
.S_ADL(1'b0),
.S_S(1'b1),
.SB_S(1'b0),
.SB(SB),
.ADL(ADL) );
initial begin
$dumpfile("regs_test.vcd");
$dumpvars(0, regs_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // regs_test |
module Core_Run ();
reg CLK;
reg n_RES;
reg n_IRQ;
reg n_NMI;
reg SO;
reg RDY;
wire [15:0] addr_bus;
wire [7:0] data_bus;
wire PHI1;
wire PHI2;
wire SYNC;
wire RnW;
always #25 CLK = ~CLK;
Core6502 core (
.n_NMI(n_NMI),
.n_IRQ(n_IRQ),
.n_RES(n_RES),
.PHI0(CLK),
.PHI1(PHI1),
.PHI2(PHI2),
.RDY(RDY),
.SO(SO),
.RnW(RnW),
.SYNC(SYNC),
.A(addr_bus),
.D(data_bus) );
ExtMem mem (
.M2(PHI2),
.WE(~RnW),
.OE(RnW),
.Addr(addr_bus),
.Data(data_bus) );
initial begin
$display("Check that MOS6502 Core is moving.");
RDY <= 1'b1; // Always ready
SO <= 1'b1; // SO is enough to set to 1 to prevent the falling edge detector from triggering
CLK <= 1'b0;
n_IRQ <= 1'b1;
n_NMI <= 1'b1;
$dumpfile("core.vcd");
$dumpvars(0, Core_Run);
// Perform reset
n_RES <= 1'b0;
repeat (8) @ (posedge CLK);
n_RES <= 1'b1;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // Core_Run |
module ExtMem (M2, WE, OE, Addr, Data);
input M2;
input WE;
input OE;
input [15:0] Addr;
inout [7:0] Data;
reg [7:0] mem [0:65535];
reg [7:0] temp;
// You need to pre-fill the memory with some value so you don't run into `xx`
integer j;
initial
for(j = 0; j < 65536; j = j+1)
mem[j] = 0;
initial $readmemh("core.mem", mem);
always @(M2) begin
if (OE)
temp <= mem[Addr];
else if (WE)
mem[Addr] <= Data;
end
assign Data = (M2 & OE) ? temp : 'bz;
endmodule // ExtMem |
module pads_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
PadsLogic pads (
.PHI1(PHI1),
.PHI2(PHI2),
.n_NMI(1'b1),
.n_IRQ(1'b1),
.n_RES(1'b1),
.RDY(1'b1),
.T1_topad(1'b0),
.SO(1'b1),
.WR_topad(1'b0) );
initial begin
$dumpfile("pads_test.vcd");
$dumpvars(0, pads_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // pads_test |
module extra_counter_test ();
reg CLK;
wire PHI1;
wire PHI2;
reg TRES2;
reg n_ready;
reg T1;
always #25 CLK = ~CLK;
ClkGen clk (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2));
ExtraCounter extra_cnt (
.PHI1(PHI1), .PHI2(PHI2), .TRES2(TRES2), .n_ready(n_ready), .T1(T1));
initial begin
$dumpfile("extra_counter_test.vcd");
$dumpvars(0, extra_counter_test);
CLK <= 1'b0;
TRES2 <= 1'b0;
n_ready <= 1'b0;
T1 <= 1'b0;
// Just work
repeat (4) @ (posedge CLK);
// Load T1 and check how it is pushed out through outputs T2-T5
T1 <= 1'b1;
repeat (1) @ (posedge CLK);
T1 <= 1'b0;
repeat (8) @ (posedge CLK);
// Load T1, then suddenly do NotReady; then ready
T1 <= 1'b1;
repeat (1) @ (posedge CLK);
T1 <= 1'b0;
repeat (2) @ (posedge CLK);
n_ready <= 1'b1;
repeat (4) @ (posedge CLK);
n_ready <= 1'b0;
repeat (4) @ (posedge CLK);
// Load T1, then suddenly do TRES2; then just work
T1 <= 1'b1;
repeat (1) @ (posedge CLK);
T1 <= 1'b0;
repeat (2) @ (posedge CLK);
TRES2 <= 1'b1;
repeat (4) @ (posedge CLK);
TRES2 <= 1'b0;
repeat (4) @ (posedge CLK);
$finish;
end
endmodule // extra_counter_test |
module data_bus_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire ADL, ADH, DB, DB_Ext;
DataBusBit databus_bit (
.PHI1(PHI1),
.PHI2(PHI2),
.ADL(ADL),
.ADH(ADH),
.DB(DB),
.DB_Ext(DB_Ext),
.DL_ADL(1'b0),
.DL_ADH(1'b0),
.DL_DB(1'b0),
.RD(RD) );
WRLatch wrlatch (
.PHI1(PHI1),
.PHI2(PHI2),
.WR(1'b0), // From dispatch
.RD(RD) );
wire RD;
initial begin
$dumpfile("data_bus_test.vcd");
$dumpvars(0, data_bus_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // data_bus_test |
module decoder_test ();
reg CLK;
integer f;
always #1 CLK = ~CLK;
reg [13:0] Decoder_cnt; // The counter acts as an enumerator for all decoder inputs
wire [129:0] Decoder_out;
wire n_T0;
wire n_T1X;
wire n_T2;
wire n_T3;
wire n_T4;
wire n_T5;
wire IR01;
wire [7:0] IR;
// Assign the decoder inputs.
// The lower six bits represent the Tx. The remaining high bits are IR.
assign n_T0 = ~Decoder_cnt[0];
assign n_T1X = ~Decoder_cnt[1];
assign n_T2 = ~Decoder_cnt[2];
assign n_T3 = ~Decoder_cnt[3];
assign n_T4 = ~Decoder_cnt[4];
assign n_T5 = ~Decoder_cnt[5];
assign IR = Decoder_cnt[13:6];
assign IR01 = IR[0]|IR[1];
Decoder dec (
.n_T0(n_T0), .n_T1X(n_T1X),
.n_T2(n_T2), .n_T3(n_T3), .n_T4(n_T4), .n_T5(n_T5),
.IR01(IR01),
.IR(IR), .n_IR(~IR),
.X(Decoder_out) );
always @(posedge CLK) begin
$fwrite (f, "%b,%b\n", Decoder_cnt, Decoder_out);
Decoder_cnt = Decoder_cnt + 1;
end
initial begin
$dumpfile("decoder_test.vcd");
$dumpvars(0, decoder_test);
f = $fopen("decoder_6502.csv","w");
$fwrite(f, "inputs,outputs\n");
Decoder_cnt <= 0;
CLK <= 1'b0;
repeat (1<<14) @ (posedge CLK);
$fclose (f);
$finish;
end
endmodule // decoder_test |
module alu_control_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire INC_SB, SR, AND;
ALU_Control alu_control (
.PHI1(PHI1),
.PHI2(PHI2),
.BRFW(1'b0),
.n_ready(1'b0),
.BRK6E(1'b0),
.STKOP(1'b0),
.PGX(1'b0),
.X({130{1'b0}}),
.T0(1'b0),
.T1(1'b0),
.T6(1'b0),
.T7(1'b0),
.n_DOUT(1'b1),
.n_COUT(1'b1),
.INC_SB(INC_SB),
.SR(SR),
.AND(AND) );
initial begin
$dumpfile("alu_control_test.vcd");
$dumpvars(0, alu_control_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // alu_control_test |
module flags_control_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
Flags_Control flags_control (
.PHI2(PHI2),
.X({130{1'b0}}),
.T7(1'b0),
.ZTST(1'b0),
.n_ready(1'b1),
.SR(1'b0) );
initial begin
$dumpfile("flags_control_test.vcd");
$dumpvars(0, flags_control_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // flags_control_test |
module addr_bus_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
reg ADX;
reg ADX_ABX;
wire ABus_out;
AddrBusBit ab (
.PHI1(PHI1), .PHI2(PHI2),
.ADX(ADX), .ADX_ABX(ADX_ABX),
.ABus_out(ABus_out) );
initial begin
$dumpfile("addr_bus_test.vcd");
$dumpvars(0, addr_bus_test);
CLK <= 1'b0;
ADX <= 1'b0;
ADX_ABX <= 1'b0;
repeat (16) @ (posedge CLK);
ADX_ABX <= 1'b1;
ADX <= 1'b1;
repeat (16) @ (posedge CLK);
ADX_ABX <= 1'b0;
repeat (16) @ (posedge CLK);
ADX_ABX <= 1'b1;
ADX <= 1'b0;
repeat (16) @ (posedge CLK);
ADX_ABX <= 1'b0;
repeat (16) @ (posedge CLK);
$finish;
end
endmodule // addr_bus_test |
module bus_control_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire ZTST, PGX;
Bus_Control bus_control (
.PHI1(PHI1),
.PHI2(PHI2),
.n_SBXY(1'b1),
.AND(1'b0),
.STOR(1'b0),
.Z_ADL0(1'b0),
.ACRL2(1'b0),
.DL_PCH(1'b0),
.n_ready(1'b0),
.INC_SB(1'b0),
.BRK6E(1'b0),
.STXY(1'b0),
.n_PCH_PCH(1'b1),
.T0(1'b0),
.T1(1'b0),
.T6(1'b0),
.T7(1'b0),
.BR0(1'b0),
.X({130{1'b0}}),
.ZTST(ZTST),
.PGX(PGX) );
initial begin
$dumpfile("bus_control_test.vcd");
$dumpvars(0, bus_control_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // bus_control_test |
module branch_logic_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] DB;
wire n_BRTAKEN, BRFW;
BranchLogic branch_logic (
.PHI1(PHI1),
.PHI2(PHI2),
.n_IR5(1'b1),
.X({130{1'b0}}),
.n_COUT(1'b1),
.n_VOUT(1'b1),
.n_NOUT(1'b1),
.n_ZOUT(1'b1),
.DB(DB),
.BR2(1'b0),
.n_BRTAKEN(n_BRTAKEN),
.BRFW(BRFW) );
initial begin
$dumpfile("branch_logic_test.vcd");
$dumpvars(0, branch_logic_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // branch_logic_test |
module flags_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] DB;
Flags flags (
.PHI1(PHI1),
.PHI2(PHI2),
.P_DB(1'b0),
.DB_P(1'b0),
.DBZ_Z(1'b0),
.DB_N(1'b0),
.IR5_C(1'b0),
.DB_C(1'b0),
.ACR_C(1'b0),
.IR5_D(1'b0),
.IR5_I(1'b0),
.DB_V(1'b0),
.Z_V(1'b0),
.ACR(1'b0),
.AVR(1'b0),
.B_OUT(1'b0),
.n_IR5(1'b0),
.BRK6E(1'b0),
.Dec112(1'b0),
.SO_frompad(1'b0),
.DB(DB) );
initial begin
$dumpfile("flags_test.vcd");
$dumpvars(0, flags_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // flags_test |
module clock_test ();
reg CLK;
always #25 CLK = ~CLK;
wire PHI1, PHI2, PHI1_topad, PHI2_topad;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2), .PHI1_topad(PHI1_topad), .PHI2_topad(PHI2_topad) );
initial begin
$dumpfile("clock_test.vcd");
$dumpvars(0, clock_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // clock_test |
module alu_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] SB, DB, ADL, ADH;
wire ACR, AVR;
ALU alu (
.PHI2(PHI2),
.NDB_ADD(1'b0),
.DB_ADD(1'b0),
.Z_ADD(1'b0),
.SB_ADD(1'b0),
.ADL_ADD(1'b0),
.ADD_SB06(1'b0),
.ADD_SB7(1'b0),
.ADD_ADL(1'b0),
.ANDS(1'b0),
.EORS(1'b0),
.ORS(1'b0),
.SRS(1'b0),
.SUMS(1'b0),
.SB_AC(1'b0),
.AC_SB(1'b0),
.AC_DB(1'b0),
.SB_DB(1'b0),
.SB_ADH(1'b0),
.Z_ADH0(1'b0),
.Z_ADH17(1'b0),
.n_ACIN(1'b1),
.n_DAA(1'b1),
.n_DSA(1'b1),
.SB(SB),
.DB(DB),
.ADL(ADL),
.ADH(ADH),
.ACR(ACR),
.AVR(AVR) );
initial begin
$dumpfile("alu_test.vcd");
$dumpvars(0, alu_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // alu_test |
module predecode_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] Data_bus, n_PD;
wire n_IMPLIED, n_TWOCYCLE;
PreDecode predecode (
.PHI2(PHI2),
.Z_IR(1'b0),
.Data_bus(Data_bus),
.n_PD(n_PD),
.n_IMPLIED(n_IMPLIED),
.n_TWOCYCLE(n_TWOCYCLE) );
initial begin
$dumpfile("predecode_test.vcd");
$dumpvars(0, predecode_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // predecode_test |
module dispatch_test ();
reg CLK;
wire PHI1;
wire PHI2;
always #25 CLK = ~CLK;
wire [7:0] DataBus;
wire Z_IR;
wire [7:0] n_PD;
wire n_IMPLIED;
wire n_TWOCYCLE;
wire TRES2;
wire n_ready;
wire T0;
wire T1;
wire n_T2;
wire n_T3;
wire n_T4;
wire n_T5;
wire FETCH;
wire IR01;
wire [7:0] IR;
wire [7:0] n_IR;
wire [129:0] X;
ClkGen clk (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2));
PreDecode predecode (
.PHI2(PHI2),
.Z_IR(Z_IR),
.Data_bus(DataBus), .n_PD(n_PD),
.n_IMPLIED(n_IMPLIED), .n_TWOCYCLE(n_TWOCYCLE));
ExtraCounter extra_counter (
.PHI1(PHI1), .PHI2(PHI2), .TRES2(TRES2), .n_ready(n_ready), .T1(T1),
.n_T2(n_T2), .n_T3(n_T3), .n_T4(n_T4), .n_T5(n_T5));
IR ir (
.PHI1(PHI1), .PHI2(PHI2),
.n_PD(n_PD), .FETCH(FETCH),
.IR01(IR01), .IR_out(IR), .n_IR_out(n_IR));
Decoder decoder (
.n_T0(n_T0), .n_T1X(n_T1X),
.n_T2(n_T2), .n_T3(n_T3), .n_T4(n_T4), .n_T5(n_T5),
.IR01(IR01),
.IR(IR), .n_IR(n_IR),
.X(X));
Dispatch dispatch (
.PHI1(PHI1), .PHI2(PHI2),
.BRK6E(1'b0), .RESP(1'b0), .ACR(1'b0), .DORES(1'b0), .PC_DB(1'b0), .RDY(1'b1), .B_OUT(1'b1), .BRFW(1'b0), .n_BRTAKEN(1'b0),
.n_TWOCYCLE(n_TWOCYCLE), .n_IMPLIED(n_IMPLIED), .n_ADL_PCL(1'b0),
.X(X),
.TRES2(TRES2), .Z_IR(Z_IR), .FETCH(FETCH), .n_ready(n_ready), .T1(T1), .n_T0(n_T0), .T0(T0), .n_T1X(n_T1X));
MemoryDevice mem (.DataBus(DataBus));
initial begin
$dumpfile("dispatch_test.vcd");
$dumpvars(0, dispatch_test);
CLK <= 1'b0;
repeat (32) @ (posedge CLK);
$finish;
end
endmodule // dispatch_test |
module MemoryDevice (DataBus);
inout [7:0] DataBus;
assign DataBus = 8'h8D; // STA abs
endmodule // MemoryDevice |
module ir_test ();
reg CLK;
reg FETCH;
wire PHI1;
wire PHI2;
always #1 CLK = ~CLK;
ClkGen clk (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2));
IR ir (
.PHI1(PHI1), .PHI2(PHI2),
.n_PD(8'ha5), .FETCH(FETCH) );
initial begin
$dumpfile("ir_test.vcd");
$dumpvars(0, ir_test);
CLK <= 1'b0;
FETCH <= 1'b0;
repeat (8) @ (posedge CLK);
FETCH <= 1'b1;
repeat (8) @ (posedge CLK);
FETCH <= 1'b0;
repeat (8) @ (posedge CLK);
$finish;
end
endmodule // ir_test |
module brk_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire BRK6E, BRK7, BRK5_RDY, DORES, n_DONMI, B_OUT;
BRKProcessing brk (
.PHI1(PHI1),
.PHI2(PHI2),
.BRK5(1'b0),
.n_ready(1'b0),
.RESP(1'b0),
.n_NMIP(1'b1),
.BR2(1'b0),
.T0(1'b0),
.n_IRQP(1'b1),
.n_IOUT(1'b1),
.BRK6E(BRK6E),
.BRK7(BRK7),
.BRK5_RDY(BRK5_RDY),
.DORES(DORES),
.n_DONMI(n_DONMI),
.B_OUT(B_OUT) );
wire Z_ADL0, Z_ADL1, Z_ADL2;
IntVector intaddr (
.PHI2(PHI2),
.BRK5_RDY(BRK5_RDY),
.BRK7(BRK7),
.DORES(DORES),
.n_DONMI(n_DONMI),
.Z_ADL0(Z_ADL0),
.Z_ADL1(Z_ADL1),
.Z_ADL2(Z_ADL2) );
initial begin
$dumpfile("brk_test.vcd");
$dumpvars(0, brk_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // brk_test |
module regs_control_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire STXY, n_SBXY, STKOP;
Regs_Control regs_control (
.PHI1(PHI1),
.PHI2(PHI2),
.STOR(1'b0),
.n_ready(1'b0),
.X({130{1'b0}}),
.STXY(STXY),
.n_SBXY(n_SBXY),
.STKOP(STKOP) );
initial begin
$dumpfile("regs_control_test.vcd");
$dumpvars(0, regs_control_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // regs_control_test |
module pc_control_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
PC_Control pc_control (
.PHI1(PHI1),
.PHI2(PHI2),
.n_ready(1'b0),
.T0(1'b0),
.T1(1'b0),
.BR0(1'b0),
.X({130{1'b0}}) );
initial begin
$dumpfile("pc_control_test.vcd");
$dumpvars(0, pc_control_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // pc_control_test |
module pc_test ();
reg CLK;
wire PHI1, PHI2;
always #25 CLK = ~CLK;
ClkGen clkgen (.PHI0(CLK), .PHI1(PHI1), .PHI2(PHI2) );
wire [7:0] ADL, ADH, DB;
PC pc (
.PHI2(PHI2),
.n_IPC(1'b0),
.ADL_PCL(1'b0),
.PCL_PCL(1'b1),
.PCL_ADL(1'b0),
.PCL_DB(1'b0),
.ADH_PCH(1'b0),
.PCH_PCH(1'b1),
.PCH_ADH(1'b0),
.PCH_DB(1'b0),
.ADL(ADL),
.ADH(ADH),
.DB(DB) );
// Single bit
/*
wire AD_bit, DB_bit;
pc_carry pc_bit (
.PHI2(PHI2),
.carry(1'b1),
.AD(AD_bit),
.DB(DB_bit),
.PC_AD(1'b0),
.PC_DB(1'b0),
.AD_PC(1'b0),
.PC_PC(1'b1) );
*/
initial begin
$dumpfile("pc_test.vcd");
$dumpvars(0, pc_test);
CLK <= 1'b0;
repeat (256) @ (posedge CLK);
$finish;
end
endmodule // pc_test |
module AdderExtModule(
input [15:0] foo,
output [15:0] bar
);
assign bar = foo + 1;
endmodule |
module SimpleExtModule(
input [15:0] foo,
output [15:0] bar
);
assign bar = foo;
endmodule |
module LargeParam #(parameter DATA=0, WIDTH=1) (
output [WIDTH-1:0] out
);
assign out = DATA;
endmodule |
module ParameterizedViaHeaderAdderExtModule(
input [15:0] foo,
output [15:0] bar
);
`include "VerilogHeaderFile.vh"
assign bar = foo + VALUE;
endmodule |
module mem_ctrl(
input clock,
input reset,
input meta_reset,
input sdram_valid,
input [1:0] sdram_data_i,
input flash_valid,
input [3:0] flash_data_i,
input rom_valid,
input rom_data_i,
output sdram_ready,
output flash_ready,
output rom_ready,
output out_valid,
output [3:0] out_data,
output [5:0] coverage,
output [5:0] io_cov_sum,
output bug
);
reg[1:0] state_sdram; // READY, RECEIVING, BUSY
reg[1:0] state_flash; // READY, BUSY
reg[1:0] state_rom;
reg[3:0] data_sdram;
reg[3:0] data_flash;
reg[3:0] data_rom;
reg covmap[0:63];
reg[5:0] reg_state;
reg[5:0] covsum;
assign coverage = covsum;
assign io_cov_sum = covsum;
integer i;
initial begin
for (i=0; i<64; i=i+1)
covmap[i] = 0;
covsum = 0;
end
always @(posedge clock) begin
reg_state <= {state_flash, state_sdram, state_rom};
if (!covmap[reg_state]) begin
covsum <= covsum + 1'h1;
covmap[reg_state] <= 1'h1;
end
if (meta_reset) begin
covsum <= 6'h0;
for (i=0; i<64; i=i+1)
covmap[i] = 1'h0;
end
end
assign bug = ((state_sdram == `BUSY_S) && (state_flash == `BUSY_F) && (state_rom == `BUSY_R))? 1 : 0;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign rom_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F) ||
(state_rom == `BUSY_R);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (reset) begin
state_sdram <= `READY_S;
state_flash <= `READY_F;
state_rom <= `READY_R;
data_sdram <= 4'h0;
data_flash <= 4'h0;
data_rom <= 4'h0;
end else begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S1;
data_sdram <= {2'b00, sdram_data_i};
end
end else if (state_sdram == `PENDING_S1) begin
if (sdram_valid) begin
state_sdram <= `BUSY_S;
data_sdram <= {sdram_data_i, 2'b00} | data_sdram;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `READY_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `PENDING_F1;
data_flash <= flash_data_i;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F1) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
end else begin
state_flash <= `READY_F;
end
end else begin
state_flash <= `READY_F;
end
if (state_rom == `READY_R) begin
if (rom_valid) begin
state_rom <= `PENDING_R1;
data_rom <= {3'b000, rom_data_i};
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R1) begin
if (rom_valid) begin
state_rom <= `BUSY_R;
data_rom <= {2'b00, rom_data_i, 1'b0} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else begin
state_rom <= `READY_R;
end
end
end
endmodule |
module mem_ctrl(
input clock,
input sdram_valid,
input [3:0] sdram_data_i,
input flash_valid,
input [7:0] flash_data_i,
output sdram_ready,
output flash_ready,
output out_valid,
output [7:0] out_data
);
reg[1:0] state_sdram; // READY, RECEIVING, BUSY
reg state_flash; // READY, BUSY
reg[7:0] data_sdram;
reg[7:0] data_flash;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S;
data_sdram <= {4'b0000, sdram_data_i};
end
end else if (state_sdram == `PENDING_S) begin
if (sdram_valid) begin
state_sdram <= `BUSY_S;
data_sdram <= {sdram_data_i, 4'b0000} | data_sdram;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `PENDING_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
data_flash <= flash_data_i;
end
end else if (state_flash == `BUSY_F) begin
state_flash <= `READY_F;
end
end
endmodule |
module mem_ctrl(
input clock,
input reset,
input meta_reset,
input sdram_valid,
input [1:0] sdram_data_i,
input flash_valid,
input [3:0] flash_data_i,
input rom_valid,
input rom_data_i,
output sdram_ready,
output flash_ready,
output rom_ready,
output out_valid,
output [3:0] out_data,
output [8:0] coverage,
output [8:0] io_cov_sum,
output bug
);
reg[2:0] state_sdram; // READY, RECEIVING, BUSY
reg[2:0] state_flash; // READY, BUSY
reg[2:0] state_rom;
reg[3:0] data_sdram;
reg[3:0] data_flash;
reg[3:0] data_rom;
reg covmap[0:511];
reg[8:0] reg_state;
reg[8:0] covsum;
assign coverage = covsum;
assign io_cov_sum = covsum;
integer i;
initial begin
for (i=0; i<512; i=i+1)
covmap[i] = 0;
covsum = 0;
end
always @(posedge clock) begin
reg_state <= {state_flash, state_sdram, state_rom};
if (!covmap[reg_state]) begin
covsum <= covsum + 1'h1;
covmap[reg_state] <= 1'h1;
end
if (meta_reset) begin
covsum <= 9'h0;
for (i=0; i<512; i=i+1)
covmap[i] = 1'h0;
end
end
assign bug = ((state_sdram == `BUSY_S) && (state_flash == `BUSY_F) && (state_rom == `BUSY_R))? 1 : 0;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign rom_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F) ||
(state_rom == `BUSY_R);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (reset) begin
state_sdram <= `READY_S;
state_flash <= `READY_F;
state_rom <= `READY_R;
data_sdram <= 4'h0;
data_flash <= 4'h0;
data_rom <= 4'h0;
end else begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S1;
data_sdram <= {2'b00, sdram_data_i};
end
end else if (state_sdram == `PENDING_S1) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S2;
data_sdram <= {sdram_data_i, 2'b00} | data_sdram;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `PENDING_S2) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S3;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `PENDING_S3) begin
if (sdram_valid) begin
state_sdram <= `READY_S;
end else begin
state_sdram <= `BUSY_S;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `READY_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `PENDING_F1;
data_flash <= flash_data_i;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F1) begin
if (flash_valid) begin
state_flash <= `PENDING_F2;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F2) begin
if (flash_valid) begin
state_flash <= `PENDING_F3;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F3) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
end else begin
state_flash <= `READY_F;
end
end else begin
state_flash <= `READY_F;
end
if (state_rom == `READY_R) begin
if (rom_valid) begin
state_rom <= `PENDING_R1;
data_rom <= {3'b000, rom_data_i};
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R1) begin
if (rom_valid) begin
state_rom <= `PENDING_R2;
data_rom <= {2'b00, rom_data_i, 1'b0} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R2) begin
if (rom_valid) begin
state_rom <= `PENDING_R3;
data_rom <= {1'b0, rom_data_i, 2'b00} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R3) begin
if (rom_valid) begin
state_rom <= `BUSY_R;
data_rom <= {rom_data_i, 3'b000} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else begin
state_rom <= `READY_R;
end
end
end
endmodule |
module mem_ctrl(
input clock,
input reset,
input meta_reset,
input sdram_valid,
input [1:0] sdram_data_i,
input flash_valid,
input [3:0] flash_data_i,
input rom_valid,
input rom_data_i,
output sdram_ready,
output flash_ready,
output rom_ready,
output out_valid,
output [3:0] out_data,
output [11:0] coverage,
output [5:0] io_cov_sum,
output bug
);
reg[1:0] state_sdram; // READY, RECEIVING, BUSY
reg[1:0] state_flash; // READY, BUSY
reg[1:0] state_rom;
reg[3:0] data_sdram;
reg[3:0] data_flash;
reg[3:0] data_rom;
reg covmap[0:63];
reg[5:0] reg_state;
reg[5:0] covsum;
assign io_cov_sum = covsum;
integer i;
initial begin
for (i=0; i<64; i=i+1)
covmap[i] = 0;
covsum = 0;
end
always @(posedge clock) begin
reg_state <= {state_flash, state_sdram, state_rom};
if (!covmap[reg_state]) begin
covsum <= covsum + 1'h1;
covmap[reg_state] <= 1'h1;
end
if (meta_reset) begin
covsum <= 6'h0;
for (i=0; i<64; i=i+1)
covmap[i] = 1'h0;
end
end
assign bug = ((state_sdram == `BUSY_S) && (state_flash == `BUSY_F) && (state_rom == `BUSY_R))? 1 : 0;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign rom_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F) ||
(state_rom == `BUSY_R);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (reset) begin
state_sdram <= `READY_S;
state_flash <= `READY_F;
state_rom <= `READY_R;
data_sdram <= 4'h0;
data_flash <= 4'h0;
data_rom <= 4'h0;
end else begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S1;
data_sdram <= {2'b00, sdram_data_i};
end
end else if (state_sdram == `PENDING_S1) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S2;
data_sdram <= {sdram_data_i, 2'b00} | data_sdram;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `PENDING_S2) begin
if (sdram_valid) begin
state_sdram <= `BUSY_S;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `READY_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `PENDING_F1;
data_flash <= flash_data_i;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F1) begin
if (flash_valid) begin
state_flash <= `PENDING_F2;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F2) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
end else begin
state_flash <= `READY_F;
end
end else begin
state_flash <= `READY_F;
end
if (state_rom == `READY_R) begin
if (rom_valid) begin
state_rom <= `PENDING_R1;
data_rom <= {3'b000, rom_data_i};
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R1) begin
if (rom_valid) begin
state_rom <= `PENDING_R2;
data_rom <= {2'b00, rom_data_i, 1'b0} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R2) begin
if (rom_valid) begin
state_rom <= `BUSY_R;
data_rom <= {1'b0, rom_data_i, 2'b00} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else begin
state_rom <= `READY_R;
end
end
end
wire mux1;
wire mux2;
wire mux3;
wire mux4;
wire mux5;
wire mux6;
wire mux7;
wire mux8;
wire mux9;
wire mux10;
wire mux11;
wire mux12;
wire mux13;
wire mux14;
wire mux15;
wire tog1;
wire tog2;
wire tog3;
wire tog4;
wire tog5;
wire tog6;
wire tog7;
wire tog8;
wire tog9;
wire tog10;
wire tog11;
wire tog12;
wire tog13;
wire tog14;
wire tog15;
wire [11:0] mux_cov;
assign mux_cov = {tog1, tog2, tog3, tog4, tog5, tog6, tog7, tog8, tog9, tog10, tog11, tog12};
assign coverage = mux_cov;
assign mux1 = (state_sdram == `READY_S)? 1 : 0;
assign mux2 = (state_sdram == `PENDING_S1)? 1 : 0;
assign mux3 = (state_sdram == `PENDING_S2)? 1 : 0;
assign mux4 = sdram_valid;
assign mux5 = (state_flash == `READY_F)? 1 : 0;
assign mux6 = (state_flash == `PENDING_F1)? 1 : 0;
assign mux7 = (state_flash == `PENDING_F2)? 1 : 0;
assign mux8 = flash_valid;
assign mux9 = (state_rom == `READY_R)? 1 : 0;
assign mux10 = (state_rom == `PENDING_R1)? 1 : 0;
assign mux11 = (state_rom == `PENDING_R2)? 1 : 0;
assign mux12 = rom_valid;
saturating_counter c1(
.clock(clock),
.reset(reset),
.signal(mux1),
.toggled(tog1)
);
saturating_counter c2(
.clock(clock),
.reset(reset),
.signal(mux2),
.toggled(tog2)
);
saturating_counter c3(
.clock(clock),
.reset(reset),
.signal(mux3),
.toggled(tog3)
);
saturating_counter c4(
.clock(clock),
.reset(reset),
.signal(mux4),
.toggled(tog4)
);
saturating_counter c5(
.clock(clock),
.reset(reset),
.signal(mux5),
.toggled(tog5)
);
saturating_counter c6(
.clock(clock),
.reset(reset),
.signal(mux6),
.toggled(tog6)
);
saturating_counter c7(
.clock(clock),
.reset(reset),
.signal(mux7),
.toggled(tog7)
);
saturating_counter c8(
.clock(clock),
.reset(reset),
.signal(mux8),
.toggled(tog8)
);
saturating_counter c9(
.clock(clock),
.reset(reset),
.signal(mux9),
.toggled(tog9)
);
saturating_counter c10(
.clock(clock),
.reset(reset),
.signal(mux10),
.toggled(tog10)
);
saturating_counter c11(
.clock(clock),
.reset(reset),
.signal(mux11),
.toggled(tog11)
);
saturating_counter c12(
.clock(clock),
.reset(reset),
.signal(mux12),
.toggled(tog12)
);
endmodule |
module saturating_counter(
input clock,
input reset,
input signal,
output toggled
);
reg count;
reg last;
assign toggled = count;
always @(posedge clock) begin
if (reset) begin
count <= 0;
end else if (last ^ signal) begin
count <= 1;
end
last <= signal;
end
endmodule |
module mem_ctrl(
input clock,
input reset,
input meta_reset,
input sdram_valid,
input [1:0] sdram_data_i,
input flash_valid,
input [3:0] flash_data_i,
input rom_valid,
input rom_data_i,
output sdram_ready,
output flash_ready,
output rom_ready,
output out_valid,
output [3:0] out_data,
output [14:0] coverage,
output [8:0] io_cov_sum,
output bug
);
reg[2:0] state_sdram; // READY, RECEIVING, BUSY
reg[2:0] state_flash; // READY, BUSY
reg[2:0] state_rom;
reg[3:0] data_sdram;
reg[3:0] data_flash;
reg[3:0] data_rom;
reg covmap[0:511];
reg[8:0] reg_state;
reg[8:0] covsum;
assign io_cov_sum = covsum;
integer i;
initial begin
for (i=0; i<512; i=i+1)
covmap[i] = 0;
covsum = 0;
end
always @(posedge clock) begin
reg_state <= {state_flash, state_sdram, state_rom};
if (!covmap[reg_state]) begin
covsum <= covsum + 1'h1;
covmap[reg_state] <= 1'h1;
end
if (meta_reset) begin
covsum <= 9'h0;
for (i=0; i<512; i=i+1)
covmap[i] = 1'h0;
end
end
assign bug = ((state_sdram == `BUSY_S) && (state_flash == `BUSY_F) && (state_rom == `BUSY_R))? 1 : 0;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign rom_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F) ||
(state_rom == `BUSY_R);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (reset) begin
state_sdram <= `READY_S;
state_flash <= `READY_F;
state_rom <= `READY_R;
data_sdram <= 4'h0;
data_flash <= 4'h0;
data_rom <= 4'h0;
end else begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S1;
data_sdram <= {2'b00, sdram_data_i};
end
end else if (state_sdram == `PENDING_S1) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S2;
data_sdram <= {sdram_data_i, 2'b00} | data_sdram;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `PENDING_S2) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S3;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `PENDING_S3) begin
if (sdram_valid) begin
state_sdram <= `READY_S;
end else begin
state_sdram <= `BUSY_S;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `READY_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `PENDING_F1;
data_flash <= flash_data_i;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F1) begin
if (flash_valid) begin
state_flash <= `PENDING_F2;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F2) begin
if (flash_valid) begin
state_flash <= `PENDING_F3;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F3) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
end else begin
state_flash <= `READY_F;
end
end else begin
state_flash <= `READY_F;
end
if (state_rom == `READY_R) begin
if (rom_valid) begin
state_rom <= `PENDING_R1;
data_rom <= {3'b000, rom_data_i};
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R1) begin
if (rom_valid) begin
state_rom <= `PENDING_R2;
data_rom <= {2'b00, rom_data_i, 1'b0} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R2) begin
if (rom_valid) begin
state_rom <= `PENDING_R3;
data_rom <= {1'b0, rom_data_i, 2'b00} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R3) begin
if (rom_valid) begin
state_rom <= `BUSY_R;
data_rom <= {rom_data_i, 3'b000} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else begin
state_rom <= `READY_R;
end
end
end
wire mux1;
wire mux2;
wire mux3;
wire mux4;
wire mux5;
wire mux6;
wire mux7;
wire mux8;
wire mux9;
wire mux10;
wire mux11;
wire mux12;
wire mux13;
wire mux14;
wire mux15;
wire tog1;
wire tog2;
wire tog3;
wire tog4;
wire tog5;
wire tog6;
wire tog7;
wire tog8;
wire tog9;
wire tog10;
wire tog11;
wire tog12;
wire tog13;
wire tog14;
wire tog15;
wire [14:0] mux_cov;
assign mux_cov = {tog1, tog2, tog3, tog4, tog5, tog6, tog7, tog8, tog9, tog10, tog11, tog12, tog13, tog14, tog15};
assign coverage = mux_cov;
assign mux1 = (state_sdram == `READY_S)? 1 : 0;
assign mux2 = (state_sdram == `PENDING_S1)? 1 : 0;
assign mux3 = (state_sdram == `PENDING_S2)? 1 : 0;
assign mux4 = (state_sdram == `PENDING_S3)? 1 : 0;
assign mux5 = sdram_valid;
assign mux6 = (state_flash == `READY_F)? 1 : 0;
assign mux7 = (state_flash == `PENDING_F1)? 1 : 0;
assign mux8 = (state_flash == `PENDING_F2)? 1 : 0;
assign mux9 = (state_flash == `PENDING_F3)? 1 : 0;
assign mux10 = flash_valid;
assign mux11 = (state_rom == `READY_R)? 1 : 0;
assign mux12 = (state_rom == `PENDING_R1)? 1 : 0;
assign mux13 = (state_rom == `PENDING_R2)? 1 : 0;
assign mux14 = (state_rom == `PENDING_R3)? 1 : 0;
assign mux15 = rom_valid;
saturating_counter c1(
.clock(clock),
.reset(reset),
.signal(mux1),
.toggled(tog1)
);
saturating_counter c2(
.clock(clock),
.reset(reset),
.signal(mux2),
.toggled(tog2)
);
saturating_counter c3(
.clock(clock),
.reset(reset),
.signal(mux3),
.toggled(tog3)
);
saturating_counter c4(
.clock(clock),
.reset(reset),
.signal(mux4),
.toggled(tog4)
);
saturating_counter c5(
.clock(clock),
.reset(reset),
.signal(mux5),
.toggled(tog5)
);
saturating_counter c6(
.clock(clock),
.reset(reset),
.signal(mux6),
.toggled(tog6)
);
saturating_counter c7(
.clock(clock),
.reset(reset),
.signal(mux7),
.toggled(tog7)
);
saturating_counter c8(
.clock(clock),
.reset(reset),
.signal(mux8),
.toggled(tog8)
);
saturating_counter c9(
.clock(clock),
.reset(reset),
.signal(mux9),
.toggled(tog9)
);
saturating_counter c10(
.clock(clock),
.reset(reset),
.signal(mux10),
.toggled(tog10)
);
saturating_counter c11(
.clock(clock),
.reset(reset),
.signal(mux11),
.toggled(tog11)
);
saturating_counter c12(
.clock(clock),
.reset(reset),
.signal(mux12),
.toggled(tog12)
);
saturating_counter c13(
.clock(clock),
.reset(reset),
.signal(mux13),
.toggled(tog13)
);
saturating_counter c14(
.clock(clock),
.reset(reset),
.signal(mux14),
.toggled(tog14)
);
saturating_counter c15(
.clock(clock),
.reset(reset),
.signal(mux15),
.toggled(tog15)
);
endmodule |
module mem_ctrl(
input clock,
input reset,
input meta_reset,
input sdram_valid,
input [1:0] sdram_data_i,
input flash_valid,
input [3:0] flash_data_i,
input rom_valid,
input rom_data_i,
output sdram_ready,
output flash_ready,
output rom_ready,
output out_valid,
output [3:0] out_data,
output [8:0] coverage,
output [5:0] io_cov_sum,
output bug
);
reg[1:0] state_sdram; // READY, RECEIVING, BUSY
reg[1:0] state_flash; // READY, BUSY
reg[1:0] state_rom;
reg[3:0] data_sdram;
reg[3:0] data_flash;
reg[3:0] data_rom;
reg covmap[0:63];
reg[5:0] reg_state;
reg[5:0] covsum;
assign io_cov_sum = covsum;
integer i;
initial begin
for (i=0; i<64; i=i+1)
covmap[i] = 0;
covsum = 0;
end
always @(posedge clock) begin
reg_state <= {state_flash, state_sdram, state_rom};
if (!covmap[reg_state]) begin
covsum <= covsum + 1'h1;
covmap[reg_state] <= 1'h1;
end
if (meta_reset) begin
covsum <= 6'h0;
for (i=0; i<64; i=i+1)
covmap[i] = 1'h0;
end
end
assign bug = ((state_sdram == `BUSY_S) && (state_flash == `BUSY_F) && (state_rom == `BUSY_R))? 1 : 0;
/********** combinational **********/
assign sdram_ready = (state_sdram != `BUSY_S);
assign flash_ready = (state_flash != `BUSY_F);
assign rom_ready = (state_flash != `BUSY_F);
assign out_valid = (state_sdram == `BUSY_S) ||
(state_flash == `BUSY_F) ||
(state_rom == `BUSY_R);
assign out_data = (state_sdram == `BUSY_S) ?
data_sdram : data_flash;
/********** sequential **********/
always @(posedge clock) begin
if (reset) begin
state_sdram <= `READY_S;
state_flash <= `READY_F;
state_rom <= `READY_R;
data_sdram <= 4'h0;
data_flash <= 4'h0;
data_rom <= 4'h0;
end else begin
if (state_sdram == `READY_S) begin
if (sdram_valid) begin
state_sdram <= `PENDING_S1;
data_sdram <= {2'b00, sdram_data_i};
end
end else if (state_sdram == `PENDING_S1) begin
if (sdram_valid) begin
state_sdram <= `BUSY_S;
data_sdram <= {sdram_data_i, 2'b00} | data_sdram;
end else begin
state_sdram <= `READY_S;
end
end else if (state_sdram == `BUSY_S) begin
state_sdram <= `READY_S;
end
if (state_flash == `READY_F) begin
if (flash_valid) begin
state_flash <= `PENDING_F1;
data_flash <= flash_data_i;
end else begin
state_flash <= `READY_F;
end
end else if (state_flash == `PENDING_F1) begin
if (flash_valid) begin
state_flash <= `BUSY_F;
end else begin
state_flash <= `READY_F;
end
end else begin
state_flash <= `READY_F;
end
if (state_rom == `READY_R) begin
if (rom_valid) begin
state_rom <= `PENDING_R1;
data_rom <= {3'b000, rom_data_i};
end else begin
state_rom <= `READY_R;
end
end else if (state_rom == `PENDING_R1) begin
if (rom_valid) begin
state_rom <= `BUSY_R;
data_rom <= {2'b00, rom_data_i, 1'b0} | data_rom;
end else begin
state_rom <= `READY_R;
end
end else begin
state_rom <= `READY_R;
end
end
end
wire mux1;
wire mux2;
wire mux3;
wire mux4;
wire mux5;
wire mux6;
wire mux7;
wire mux8;
wire mux9;
wire tog1;
wire tog2;
wire tog3;
wire tog4;
wire tog5;
wire tog6;
wire tog7;
wire tog8;
wire tog9;
wire [8:0] mux_cov;
assign mux_cov = {tog1, tog2, tog3, tog4, tog5, tog6, tog7, tog8, tog9};
assign coverage = mux_cov;
assign mux1 = (state_sdram == `READY_S)? 1 : 0;
assign mux2 = (state_sdram == `PENDING_S1)? 1 : 0;
assign mux3 = sdram_valid;
assign mux4 = (state_flash == `READY_F)? 1 : 0;
assign mux5 = (state_flash == `PENDING_F1)? 1 : 0;
assign mux6 = flash_valid;
assign mux7 = (state_rom == `READY_R)? 1 : 0;
assign mux8 = (state_rom == `PENDING_R1)? 1 : 0;
assign mux9 = rom_valid;
saturating_counter c1(
.clock(clock),
.reset(reset),
.signal(mux1),
.toggled(tog1)
);
saturating_counter c2(
.clock(clock),
.reset(reset),
.signal(mux2),
.toggled(tog2)
);
saturating_counter c3(
.clock(clock),
.reset(reset),
.signal(mux3),
.toggled(tog3)
);
saturating_counter c4(
.clock(clock),
.reset(reset),
.signal(mux4),
.toggled(tog4)
);
saturating_counter c5(
.clock(clock),
.reset(reset),
.signal(mux5),
.toggled(tog5)
);
saturating_counter c6(
.clock(clock),
.reset(reset),
.signal(mux6),
.toggled(tog6)
);
saturating_counter c7(
.clock(clock),
.reset(reset),
.signal(mux7),
.toggled(tog7)
);
saturating_counter c8(
.clock(clock),
.reset(reset),
.signal(mux8),
.toggled(tog8)
);
saturating_counter c9(
.clock(clock),
.reset(reset),
.signal(mux9),
.toggled(tog9)
);
endmodule |
module LUT4(input A, B, C, D, output Z);
parameter [15:0] INIT = 16'h0000;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
endmodule |
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1, COUT);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
parameter INJECT1_1 = "YES";
// First half
wire LUT4_0, LUT2_0;
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
assign S0 = LUT4_0 ^ gated_cin_0;
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
// Second half
wire LUT4_1, LUT2_1;
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
assign S1 = LUT4_1 ^ gated_cin_1;
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
endmodule |
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
reg muxce;
always @(*)
case (CEMUX)
"1": muxce = 1'b1;
"0": muxce = 1'b0;
"INV": muxce = ~CE;
default: muxce = CE;
endcase
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval;
generate
if (LSRMODE == "PRLD")
assign srval = M;
else
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
endgenerate
initial Q = srval;
generate
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
endgenerate
endmodule |
module OBZ(input I, T, output O);
assign O = T ? 1'bz : I;
endmodule |
module IB(input I, output O);
assign O = I;
endmodule |
module OB(input I, output O);
assign O = I;
endmodule |
module BB(input I, T, output O, inout B);
assign B = T ? 1'bz : I;
assign O = B;
endmodule |
module TRELLIS_SLICE(
input A0, B0, C0, D0,
input A1, B1, C1, D1,
input M0, M1,
input FCI, FXA, FXB,
input CLK, LSR, CE,
input DI0, DI1,
input WD0, WD1,
input WAD0, WAD1, WAD2, WAD3,
input WRE, WCK,
output F0, Q0,
output F1, Q1,
output FCO, OFX0, OFX1,
output WDO0, WDO1, WDO2, WDO3,
output WADO0, WADO1, WADO2, WADO3
);
parameter MODE = "LOGIC";
parameter GSR = "ENABLED";
parameter SRMODE = "LSR_OVER_CE";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter LUT0_INITVAL = 16'h0000;
parameter LUT1_INITVAL = 16'h0000;
parameter REG0_SD = "0";
parameter REG1_SD = "0";
parameter REG0_REGSET = "RESET";
parameter REG1_REGSET = "RESET";
parameter REG0_LSRMODE = "LSR";
parameter REG1_LSRMODE = "LSR";
parameter [127:0] CCU2_INJECT1_0 = "NO";
parameter [127:0] CCU2_INJECT1_1 = "NO";
parameter WREMUX = "WRE";
function [15:0] permute_initval;
input [15:0] initval;
integer i;
begin
for (i = 0; i < 16; i = i + 1) begin
permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
end
end
endfunction
generate
if (MODE == "LOGIC") begin
// LUTs
LUT4 #(
.INIT(LUT0_INITVAL)
) lut4_0 (
.A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0)
);
LUT4 #(
.INIT(LUT1_INITVAL)
) lut4_1 (
.A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1)
);
// LUT expansion muxes
PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
end else if (MODE == "CCU2") begin
CCU2C #(
.INIT0(LUT0_INITVAL),
.INIT1(LUT1_INITVAL),
.INJECT1_0(CCU2_INJECT1_0),
.INJECT1_1(CCU2_INJECT1_1)
) ccu2c_i (
.CIN(FCI),
.A0(A0), .B0(B0), .C0(C0), .D0(D0),
.A1(A1), .B1(B1), .C1(C1), .D1(D1),
.S0(F0), .S1(F1),
.COUT(FCO)
);
end else if (MODE == "RAMW") begin
assign WDO0 = C1;
assign WDO1 = A1;
assign WDO2 = D1;
assign WDO3 = B1;
assign WADO0 = D0;
assign WADO1 = B0;
assign WADO2 = C0;
assign WADO3 = A0;
end else if (MODE == "DPRAM") begin
TRELLIS_RAM16X2 #(
.INITVAL_0(permute_initval(LUT0_INITVAL)),
.INITVAL_1(permute_initval(LUT1_INITVAL)),
.WREMUX(WREMUX)
) ram_i (
.DI0(WD0), .DI1(WD1),
.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
.WRE(WRE), .WCK(WCK),
.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
.DO0(F0), .DO1(F1)
);
// TODO: confirm RAD and INITVAL ordering
// DPRAM mode contract?
always @(*) begin
assert(A0==A1);
assert(B0==B1);
assert(C0==C1);
assert(D0==D1);
end
end else begin
ERROR_UNKNOWN_SLICE_MODE error();
end
endgenerate
// FF input selection muxes
wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
// Flipflops
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG0_REGSET),
.LSRMODE(REG0_LSRMODE)
) ff_0 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi0), .M(M0),
.Q(Q0)
);
TRELLIS_FF #(
.GSR(GSR),
.CEMUX(CEMUX),
.CLKMUX(CLKMUX),
.LSRMUX(LSRMUX),
.SRMODE(SRMODE),
.REGSET(REG1_REGSET),
.LSRMODE(REG1_LSRMODE)
) ff_1 (
.CLK(CLK), .LSR(LSR), .CE(CE),
.DI(muxdi1), .M(M1),
.Q(Q1)
);
endmodule |
module DP16KD(
input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
input CEA, OCEA, CLKA, WEA, RSTA,
input CSA2, CSA1, CSA0,
output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
input CEB, OCEB, CLKB, WEB, RSTB,
input CSB2, CSB1, CSB0,
output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
);
parameter DATA_WIDTH_A = 18;
parameter DATA_WIDTH_B = 18;
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
parameter RESETMODE = "SYNC";
parameter ASYNC_RESET_RELEASE = "SYNC";
parameter CSDECODE_A = "0b000";
parameter CSDECODE_B = "0b000";
parameter WRITEMODE_A = "NORMAL";
parameter WRITEMODE_B = "NORMAL";
parameter CLKAMUX = "CLKA";
parameter CLKBMUX = "CLKB";
parameter GSR = "ENABLED";
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
endmodule |
module FD1S3BX(input PD, D, CK, output Q);
TRELLIS_FF #(
.GSR("DISABLED"),
.CEMUX("1"),
.CLKMUX("CLK"),
.LSRMUX("LSR"),
.REGSET("SET"),
.SRMODE("ASYNC")
) tff_i (
.CLK(CK),
.LSR(PD),
.DI(D),
.Q(Q)
);
endmodule |
module \$_DFF_PP0_ (input D, C, R, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule |
module \$_DFF_PP1_ (input D, C, R, output Q);
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
endmodule |
module ADD2 (
input A, B,
output Y
);
assign Y = A & B;
endmodule |
module ADD3 (
input A, B, C,
output Y
);
assign Y = A & B & C;
endmodule |
module ADD4 (
input A, B, C, D,
output Y
);
assign Y = A & B & C & D;
endmodule |
module CLKINT_PRESERVE (
input A,
output Y
);
assign Y = A;
endmodule |
module CLKBUF (
input PAD,
output Y
);
assign Y = PAD;
endmodule |
module INBUF (
input PAD,
output Y
);
assign Y = PAD;
endmodule |
module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
ALU #(.ALU_MODE(32'b0))
alu(.I0(AA[i]),
.I1(BB[i]),
.I3(1'b0),
.CIN(C[i]),
.COUT(CO[i]),
.SUM(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule |
module LUT1(output F, input I0);
parameter [1:0] INIT = 0;
assign F = I0 ? INIT[1] : INIT[0];
endmodule |
module LUT2(output F, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule |
module LUT3(output F, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule |
module LUT4(output F, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
endmodule |
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK)
Q <= D;
endmodule |
module DFFN (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge CLK)
Q <= D;
endmodule |
module DFFR (output reg Q, input D, CLK, RESET);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK) begin
if (RESET)
Q <= 1'b0;
else
Q <= D;
end
endmodule // DFFR (positive clock edge; synchronous reset) |
module VCC(output V);
assign V = 1;
endmodule |
module GND(output G);
assign G = 0;
endmodule |
module OBUF(output O, input I);
assign O = I;
endmodule |
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule |
module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
parameter [3:0] ALU_MODE = 0; // default 0 = ADD
assign {COUT, SUM} = CIN + I1 + I0;
endmodule // alu |
module RAM16S4 (DO, DI, AD, WRE, CLK);
parameter WIDTH = 4;
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
parameter INIT_2 = 16'h0000;
parameter INIT_3 = 16'h0000;
input [WIDTH-1:0] AD;
input [WIDTH-1:0] DI;
output [WIDTH-1:0] DO;
input CLK;
input WRE;
reg [15:0] mem0, mem1, mem2, mem3;
initial begin
mem0 = INIT_0;
mem1 = INIT_1;
mem2 = INIT_2;
mem3 = INIT_3;
end
assign DO[0] = mem0[AD];
assign DO[1] = mem1[AD];
assign DO[2] = mem2[AD];
assign DO[3] = mem3[AD];
always @(posedge CLK) begin
if (WRE) begin
mem0[AD] <= DI[0];
mem1[AD] <= DI[1];
mem2[AD] <= DI[2];
mem3[AD] <= DI[3];
end
end
endmodule // RAM16S4 |
module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
//1'b0: Bypass mode; 1'b1 Pipeline mode
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE; // clock enable of memory output register
input RESETA, RESETB; // resets output registers, not memory contents
input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSEL;
output [31:0] DO;
endmodule |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 2) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 3) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule |
module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
SB_CARRY carry (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.CO(CO[i])
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(AA[i]),
.I2(BB[i]),
.I3(C[i]),
.O(Y[i])
);
end endgenerate
assign X = AA ^ BB;
endmodule |
module RAMB18E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [13:0] ADDRARDADDR,
input [13:0] ADDRBWRADDR,
input [15:0] DIADI,
input [15:0] DIBDI,
input [1:0] DIPADIP,
input [1:0] DIPBDIP,
input [1:0] WEA,
input [3:0] WEBWE,
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_DEVICE = "VIRTEX6";
endmodule |
module RAMB36E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [15:0] ADDRARDADDR,
input [15:0] ADDRBWRADDR,
input [31:0] DIADI,
input [31:0] DIBDI,
input [3:0] DIPADIP,
input [3:0] DIPBDIP,
input [3:0] WEA,
input [7:0] WEBWE,
output [31:0] DOADO,
output [31:0] DOBDO,
output [3:0] DOPADOP,
output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RAM_MODE = "TDP";
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter SIM_DEVICE = "VIRTEX6";
endmodule |
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 7) begin
wire T0, T1;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
end else
if (WIDTH == 8) begin
wire T0, T1, T2, T3, T4, T5;
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule |
module _80_xilinx_lcu (P, G, CI, CO);
parameter WIDTH = 2;
input [WIDTH-1:0] P, G;
input CI;
output [WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = WIDTH <= 2;
genvar i;
`ifdef _CLB_CARRY
localparam CARRY4_COUNT = (WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
wire [MAX_WIDTH-1:0] C = CO;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
// Partially occupied CARRY4
if ((i+1)*4 > WIDTH) begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_part
(
.CYINIT(CI),
.CI (1'd0),
.DI (G [(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4]),
);
// Another one
end else begin
CARRY4 carry4_part
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (G [(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4]),
);
end
// Fully occupied CARRY4
end else begin
// First one
if (i == 0) begin
CARRY4 carry4_1st_full
(
.CYINIT(CI),
.CI (1'd0),
.DI (G [((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4]),
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (G [((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4]),
);
end
end
end endgenerate
`elsif _EXPLICIT_CARRY
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
`else
wire [WIDTH-1:0] C = {CO, CI};
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(G[i]),
.S(S[i]),
.O(CO[i])
);
end endgenerate
`endif
endmodule |
module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
`ifdef _CLB_CARRY
localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
wire [MAX_WIDTH-1:0] C = CO;
genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
// Partially occupied CARRY4
if ((i+1)*4 > Y_WIDTH) begin
// First one
if (i == 0) begin
CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_part
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
end
// Fully occupied CARRY4
end else begin
// First one
if (i == 0) begin
CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
(
.CYINIT(CI),
.CI (1'd0),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
end
end
end endgenerate
`elsif _EXPLICIT_CARRY
wire [Y_WIDTH-1:0] S = AA ^ BB;
wire [Y_WIDTH-1:0] DI = AA & BB;
wire CINIT;
// Carry chain.
//
// VPR requires that the carry chain never hit the fabric. The CO input
// to this techmap is the carry outputs for synthesis, e.g. might hit the
// fabric.
//
// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
// e.g. off fabric dedicated chain. CO is the carry outputs that are
// available to the fabric.
wire [Y_WIDTH-1:0] CO_CHAIN;
wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
// If carry chain is being initialized to a constant, techmap the constant
// source. Otherwise techmap the fabric source.
generate for (i = 0; i < 1; i = i + 1) begin:slice
CARRY0 #(.CYINIT_FABRIC(1)) carry(
.CI_INIT(CI),
.DI(DI[0]),
.S(S[0]),
.CO_CHAIN(CO_CHAIN[0]),
.CO_FABRIC(CO[0]),
.O(Y[0])
);
end endgenerate
generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
if(i % 4 == 0) begin
CARRY0 carry (
.CI(C[i]),
.DI(DI[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.CO_FABRIC(CO[i]),
.O(Y[i])
);
end
else
begin
CARRY carry (
.CI(C[i]),
.DI(DI[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.CO_FABRIC(CO[i]),
.O(Y[i])
);
end
end endgenerate
generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
if(i % 4 == 0) begin
CARRY0 top_of_carry (
.CI(C[i]),
.DI(DI[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.O(Y[i])
);
end
else
begin
CARRY top_of_carry (
.CI(C[i]),
.DI(DI[i]),
.S(S[i]),
.CO_CHAIN(CO_CHAIN[i]),
.O(Y[i])
);
end
// Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
// a non-congested path to output the top of the carry chain.
// Registering the output of the CARRY block would solve this, but not
// all designs do that.
if((i+1) % 4 == 0) begin
CARRY0 carry_output (
.CI(CO_CHAIN[i]),
.DI(0),
.S(0),
.O(CO[i])
);
end
else
begin
CARRY carry_output (
.CI(CO_CHAIN[i]),
.DI(0),
.S(0),
.O(CO[i])
);
end
end endgenerate
`else
wire [Y_WIDTH-1:0] S = AA ^ BB;
wire [Y_WIDTH-1:0] DI = AA & BB;
wire [Y_WIDTH-1:0] C = {CO, CI};
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
MUXCY muxcy (
.CI(C[i]),
.DI(DI[i]),
.S(S[i]),
.O(CO[i])
);
XORCY xorcy (
.CI(C[i]),
.LI(S[i]),
.O(Y[i])
);
end endgenerate
`endif
assign X = S;
endmodule |
module VCC(output P);
assign P = 1;
endmodule |
module GND(output G);
assign G = 0;
endmodule |
module IBUF(output O, input I);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
endmodule |
module OBUF(output O, input I);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
endmodule |
module BUFGCTRL(
output O,
input I0, input I1,
input S0, input S1,
input CE0, input CE1,
input IGNORE0, input IGNORE1);
parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
wire S0_true = (S0 ^ IS_S0_INVERTED);
wire S1_true = (S1 ^ IS_S1_INVERTED);
assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule |
module BUFHCE(output O, input I, input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
endmodule |
module INV(output O, input I);
assign O = !I;
endmodule |
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
assign O = I0 ? INIT[1] : INIT[0];
endmodule |
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule |
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