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module DPCM_SampleBuffer (ACLK1, RES, BLOAD, BSTEP, PCM, DB, n_BOUT);
input ACLK1;
input RES;
input BLOAD;
input BSTEP;
input PCM;
inout [7:0] DB;
output n_BOUT;
wire [7:0] buf_nq;
wire [7:0] sout;
RegisterBit buf_reg [7:0] (.ACLK1(ACLK1), .ena(PCM), .d(DB), .nq(buf_nq) );
DPCM_SRBit shift_reg [7:0] (.ACLK1(ACLK1), .clear(RES), .load(BLOAD), .step(BSTEP), .n_val(buf_nq), .sin({1'b0,sout[7:1]}), .sout(sout) );
assign n_BOUT = ~sout[0];
endmodule // DPCM_SampleBuffer |
module DPCM_SRBit (ACLK1, clear, load, step, n_val, sin, sout);
input ACLK1;
input clear;
input load;
input step;
input n_val;
input sin;
output sout;
wire d;
wire in_latch_nq;
assign d = clear ? 1'b0 : (load ? n_val : (step ? in_latch_nq : (ACLK1 ? ~sout : 1'bz)));
dlatch in_latch (.d(sin), .en(ACLK1), .nq(in_latch_nq) );
dlatch out_latch (.d(d), .en(1'b1), .nq(sout) );
endmodule // DPCM_SRBit |
module DPCM_AddressReg (ACLK1, W4012, DB, DPA);
input ACLK1;
input W4012;
inout [7:0] DB;
output [7:0] DPA;
RegisterBit addr_reg [7:0] (.ACLK1(ACLK1), .ena(W4012), .d(DB[7:0]), .q(DPA[7:0]) );
endmodule // DPCM_AddressReg |
module DPCM_AddressCounter (ACLK1, RES, DSLOAD, DSSTEP, DPA, DMC_Addr);
input ACLK1;
input RES;
input DSLOAD;
input DSSTEP;
input [7:0] DPA;
output [15:0] DMC_Addr;
wire [7:0] addr_lo_cout;
wire [6:0] addr_hi_cout;
wire [7:0] addr_lo_q;
wire [6:0] addr_hi_q;
CounterBit addr_lo [7:0] (.ACLK1(ACLK1), .d({DPA[1:0], 6'b000000}), .load(DSLOAD), .clear(RES), .step(DSSTEP), .cin({addr_lo_cout[6:0],1'b1}), .q(addr_lo_q), .cout(addr_lo_cout));
CounterBit addr_hi [6:0] (.ACLK1(ACLK1), .d({1'b1, DPA[7:2]}), .load(DSLOAD), .clear(RES), .step(DSSTEP), .cin({addr_hi_cout[5:0],addr_lo_cout[7]}), .q(addr_hi_q), .cout(addr_hi_cout) );
assign DMC_Addr = {1'b1,addr_hi_q,addr_lo_q};
endmodule // DPCM_AddressCounter |
module DPCM_Output (ACLK1, RES, W4011, CountDown, DSTEP, DB, DMC_Out, DOUT);
input ACLK1;
input RES;
input W4011;
input CountDown;
input DSTEP;
inout [7:0] DB;
output [6:0] DMC_Out;
output DOUT;
wire out_reg_q;
wire [5:0] out_cnt_q;
wire [5:0] cout;
RevCounterBit out_cnt [5:0] (.ACLK1(ACLK1), .d(DB[6:1]), .load(W4011), .clear(RES), .step(DSTEP), .cin({cout[4:0],1'b1}), .dec(CountDown), .q(out_cnt_q), .cout(cout) );
RegisterBit out_reg (.ACLK1(ACLK1), .ena(W4011), .d(DB[0]), .q(out_reg_q) );
assign DMC_Out = {out_cnt_q,out_reg_q};
assign DOUT = cout[5];
endmodule // DPCM_Output |
module APU(AUX_A, AUX_B, n_RES, A, D, CLK, DBG, M2, n_IRQ, n_NMI, RnW, n_IN0, n_IN1, OUT0, OUT1, OUT2);
output [7:0] AUX_A;
output [14:0] AUX_B;
input n_RES;
output [15:0] A;
inout [7:0] D;
input CLK;
input DBG;
output M2;
input n_IRQ;
input n_NMI;
output RnW;
output n_IN0;
output n_IN1;
output OUT0;
output OUT1;
output OUT2;
// Wires
wire n_CLK;
wire PHI0;
wire PHI1;
wire PHI2;
wire nACLK2;
wire ACLK1;
wire n_M2;
wire RES;
wire DBG_frompad;
wire n_IRQINT;
wire RW_fromcore;
wire RW;
wire RD;
wire WR;
wire n_R4018;
wire n_R401A;
wire n_R4015;
wire W4002;
wire W4001;
wire W4005;
wire W4006;
wire W4008;
wire W400A;
wire W400B;
wire W400E;
wire W4013;
wire W4012;
wire W4010;
wire W4014;
wire n_R4019;
wire W401A;
wire W4003;
wire W4007;
wire W4004;
wire W400C;
wire W4000;
wire W4015;
wire W4011;
wire W400F;
wire n_R4017;
wire n_R4016;
wire W4016;
wire W4017;
wire Timer_Int;
wire nLFO1;
wire nLFO2;
wire SQA_LC;
wire SQB_LC;
wire TRI_LC;
wire RND_LC;
wire NOSQA;
wire NOSQB;
wire NOTRI;
wire NORND;
wire n_DMCAB;
wire RUNDMC;
wire DMCRDY;
wire DMCINT;
wire [15:0] DMC_Addr;
wire SPR_PPU;
wire RDY_tocore;
wire [7:0] DB;
wire [15:0] Addr_fromcore;
wire [15:0] Addr_topad;
wire n_DBGRD;
wire DebugLock;
wire [3:0] SQA;
wire [3:0] SQB;
wire [3:0] RND;
wire [3:0] TRI;
wire [6:0] DMC;
// Module instantiation
ApuPadsLogic pads(
.CLKPad(CLK),
.n_CLK_frompad(n_CLK),
.n_RESPad(n_RES),
.RES_frompad(RES),
.n_IRQPad(n_IRQ),
.Timer_Int(Timer_Int),
.n_IRQ_tocore(n_IRQINT),
.n_M2_topad(n_M2),
.M2Pad(M2),
.DBGPad(DBG),
.DBG_frompad(DBG_frompad),
.RD(RD),
.WR(WR),
.DB(DB),
.DPads(D),
.RW_topad(RW),
.RWPad(RnW),
.Addr_topad(Addr_topad),
.APads(A) );
Core core(
.core_PHI0(PHI0),
.core_PHI1(PHI1),
.core_PHI2(PHI2),
.core_nNMI(n_NMI),
.core_nIRQ(n_IRQINT),
.core_nRES(~RES),
.core_RDY(RDY_tocore),
.core_SO(1'b1),
.core_RnW(RW_fromcore),
.core_DPads(DB),
.core_APads(Addr_fromcore) );
CLK_Divider div(
.n_CLK_frompad(n_CLK),
.PHI0_tocore(PHI0),
.PHI2_fromcore(PHI2),
.n_M2_topad(n_M2) );
ACLKGen aclk(
.PHI1(PHI1),
.PHI2(PHI2),
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES) );
SoftTimer softclk (
.PHI1(PHI1),
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.n_R4015(n_R4015),
.W4017(W4017),
.DB(DB),
.DMCINT(DMCINT),
.INT_out(Timer_Int),
.nLFO1(nLFO1),
.nLFO2(nLFO2) );
DMABuffer sprdma_buf(
.PHI2(PHI2),
.SPR_PPU(SPR_PPU),
.DB(DB),
.RnW_fromcore(RW_fromcore),
.RW_topad(RW),
.n_R4015(n_R4015),
.n_DBGRD(n_DBGRD),
.WR_topad(WR),
.RD_topad(RD) );
ApuRegsDecoder regs(
.PHI1(PHI1),
.Addr_fromcore(Addr_fromcore),
.Addr_frommux(Addr_topad),
.RnW_fromcore(RW_fromcore),
.DBG_frompad(DBG_frompad),
.n_R4018(n_R4018),
.n_R401A(n_R401A),
.n_R4015(n_R4015),
.W4002(W4002),
.W4001(W4001),
.W4005(W4005),
.W4006(W4006),
.W4008(W4008),
.W400A(W400A),
.W400B(W400B),
.W400E(W400E),
.W4013(W4013),
.W4012(W4012),
.W4010(W4010),
.W4014(W4014),
.n_R4019(n_R4019),
.W401A(W401A),
.W4003(W4003),
.W4007(W4007),
.W4004(W4004),
.W400C(W400C),
.W4000(W4000),
.W4015(W4015),
.W4011(W4011),
.W400F(W400F),
.n_R4017(n_R4017),
.n_R4016(n_R4016),
.W4016(W4016),
.W4017(W4017),
.n_DBGRD(n_DBGRD) );
IOPorts io(
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.W4016(W4016),
.n_R4016(n_R4016),
.n_R4017(n_R4017),
.DB(DB),
.RES(RES),
.OUT0_Pad(OUT0),
.OUT1_Pad(OUT1),
.OUT2_Pad(OUT2),
.nIN0_Pad(n_IN0),
.nIN1_Pad(n_IN1) );
Sprite_DMA sprdma(
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.PHI1(PHI1),
.RES(RES),
.RnW(RW_fromcore),
.W4014(W4014),
.DB(DB),
.RUNDMC(RUNDMC),
.n_DMCAB(n_DMCAB),
.DMCRDY(DMCRDY),
.DMC_Addr(DMC_Addr),
.CPU_Addr(Addr_fromcore),
.Addr(Addr_topad),
.RDY_tocore(RDY_tocore),
.SPR_PPU(SPR_PPU) );
LengthCounters length(
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.n_R4015(n_R4015),
.W4015(W4015),
.nLFO2(nLFO2),
.W4003(W4003),
.W4007(W4007),
.W400B(W400B),
.W400F(W400F),
.SQA_LC(SQA_LC),
.SQB_LC(SQB_LC),
.TRI_LC(TRI_LC),
.RND_LC(RND_LC),
.NOSQA(NOSQA),
.NOSQB(NOSQB),
.NOTRI(NOTRI),
.NORND(NORND) );
SquareChan sqa(
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.WR0(W4000),
.WR1(W4001),
.WR2(W4002),
.WR3(W4003),
.nLFO1(nLFO1),
.nLFO2(nLFO2),
.SQ_LC(SQA_LC),
.NOSQ(NOSQA),
.LOCK(DebugLock),
.AdderCarryMode(1'b1),
.SQ_Out(SQA) );
SquareChan sqb(
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.WR0(W4004),
.WR1(W4005),
.WR2(W4006),
.WR3(W4007),
.nLFO1(nLFO1),
.nLFO2(nLFO2),
.SQ_LC(SQB_LC),
.NOSQ(NOSQB),
.LOCK(DebugLock),
.AdderCarryMode(1'b0),
.SQ_Out(SQB) );
NoiseChan noise(
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.DB(DB),
.W400C(W400C),
.W400E(W400E),
.W400F(W400F),
.nLFO1(nLFO1),
.RND_LC(RND_LC),
.NORND(NORND),
.LOCK(DebugLock),
.RND_out(RND) );
TriangleChan triangle (
.PHI1(PHI1),
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.W4008(W4008),
.W400A(W400A),
.W400B(W400B),
.W401A(W401A),
.nLFO1(nLFO1),
.TRI_LC(TRI_LC),
.NOTRI(NOTRI),
.LOCK(DebugLock),
.TRI_Out(TRI) );
DPCMChan dpcm(
.PHI1(PHI1),
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.DB(DB),
.RnW(RW_fromcore),
.LOCK(DebugLock),
.W4010(W4010),
.W4011(W4011),
.W4012(W4012),
.W4013(W4013),
.W4015(W4015),
.n_R4015(n_R4015),
.n_DMCAB(n_DMCAB),
.RUNDMC(RUNDMC),
.DMCRDY(DMCRDY),
.DMCINT(DMCINT),
.DMC_Addr(DMC_Addr),
.DMC_Out(DMC) );
DAC_Square auxa(
.SQA(SQA),
.SQB(SQB),
.AUX_A(AUX_A) );
DAC_Others auxb(
.TRI(TRI),
.RND(RND),
.DMC(DMC),
.AUX_B(AUX_B) );
Test dbg(
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.W401A(W401A),
.n_R4018(n_R4018),
.n_R4019(n_R4019),
.n_R401A(n_R401A),
.SQA_in(SQA),
.SQB_in(SQB),
.TRI_in(TRI),
.RND_in(RND),
.DMC_in(DMC),
.LOCK(DebugLock) );
endmodule // APU |
module NoiseChan(
ACLK1, nACLK2,
RES, DB, W400C, W400E, W400F, nLFO1, RND_LC, NORND, LOCK,
RND_out);
input ACLK1;
input nACLK2;
input RES;
inout [7:0] DB;
input W400C;
input W400E;
input W400F;
input nLFO1;
output RND_LC;
input NORND;
input LOCK;
output [3:0] RND_out;
// Internal wires
wire [3:0] NF;
wire [10:0] NNF;
wire RSTEP;
wire RNDOUT;
wire [3:0] Vol;
// Instantiate
NOISE_FreqReg freq_reg (.ACLK1(ACLK1), .RES(RES), .W400E(W400E), .DB(DB), .NF(NF) );
NOISE_Decoder dec (.NF(NF), .NNF(NNF) );
NOISE_FreqLFSR freq_lfsr (.nACLK2(nACLK2), .ACLK1(ACLK1), .RES(RES), .NNF(NNF), .RSTEP(RSTEP) );
NOISE_RandomLFSR rnd_lfsr (.ACLK1(ACLK1), .RSTEP(RSTEP), .NORND(NORND), .LOCK(LOCK), .W400E(W400E), .DB(DB), .RNDOUT(RNDOUT) );
Envelope_Unit env_unit (.ACLK1(ACLK1), .RES(RES), .WR_Reg(W400C), .WR_LC(W400F), .n_LFO1(nLFO1), .DB(DB), .V(Vol), .LC(RND_LC) );
assign RND_out = ~(~Vol | {4{RNDOUT}});
endmodule // NoiseChan |
module NOISE_FreqReg (ACLK1, RES, W400E, DB, NF);
input ACLK1;
input RES;
input W400E;
inout [7:0] DB;
output [3:0] NF;
RegisterBitRes freq_reg [3:0] (.ACLK1(ACLK1), .ena(W400E), .d(DB[3:0]), .res(RES), .q(NF) );
endmodule // NOISE_FreqReg |
module NOISE_Decoder (NF, NNF);
input [3:0] NF;
output [10:0] NNF;
wire [15:0] Dec1_out;
NOISE_Decoder1 dec1 (.Dec1_in(NF), .Dec1_out(Dec1_out) );
NOISE_Decoder2 dec2 (.Dec2_in(Dec1_out), .Dec2_out(NNF) );
endmodule // NOISE_Decoder |
module NOISE_FreqLFSR (nACLK2, ACLK1, RES, NNF, RSTEP);
input nACLK2;
input ACLK1;
input RES;
input [10:0] NNF;
output RSTEP;
wire ACLK4;
wire [10:0] sout;
wire step_load;
wire NFLOAD;
wire NFSTEP;
wire NSIN;
wire NFZ;
wire NFOUT;
assign ACLK4 = ~nACLK2;
NOISE_FreqLFSRBit freq_lfsr [10:0] (.ACLK1(ACLK1), .load(NFLOAD), .step(NFSTEP), .val(NNF), .sin({NSIN,sout[10:1]}), .sout(sout) );
nor (NFZ, sout[0], sout[1], sout[2], sout[3], sout[4], sout[5], sout[6], sout[7], sout[8], sout[9], sout[10]);
nor (NFOUT, ~sout[0], sout[1], sout[2], sout[3], sout[4], sout[5], sout[6], sout[7], sout[8], sout[9], sout[10]);
nor (step_load, ~NFOUT, RES);
nor (NFLOAD, ~ACLK4, ~step_load);
nor (NFSTEP, ~ACLK4, step_load);
nor (NSIN, (sout[0] & sout[2]), ~(sout[0] | sout[2] | NFZ), RES);
assign RSTEP = NFLOAD;
endmodule // NOISE_FreqLFSR |
module NOISE_RandomLFSR (ACLK1, RSTEP, NORND, LOCK, W400E, DB, RNDOUT);
input ACLK1;
input RSTEP;
input NORND;
input LOCK;
input W400E;
inout [7:0] DB;
output RNDOUT;
wire rmod_q;
wire [14:0] sout;
wire RIN;
wire RSOZ;
wire mux_out;
RegisterBit rmod_reg (.ACLK1(ACLK1), .ena(W400E), .d(DB[7]), .q(rmod_q) );
NOISE_RandomLFSRBit rnd_lfsr [14:0] (.ACLK1(ACLK1), .load(RSTEP), .sin({RIN,sout[14:1]}), .sout(sout) );
nor (RSOZ, sout[0], sout[1], sout[2], sout[3], sout[4], sout[5], sout[6], sout[7], sout[8], sout[9], sout[10], sout[11], sout[12], sout[13], sout[14]);
assign mux_out = rmod_q ? sout[6] : sout[1];
nor (RIN, LOCK, ~(RSOZ | sout[0] | mux_out), (sout[0] & mux_out));
nor (RNDOUT, ~(sout[0] | NORND), LOCK);
endmodule // NOISE_RandomLFSR |
module NOISE_RandomLFSRBit (ACLK1, load, sin, sout);
input ACLK1;
input load;
input sin;
output sout;
wire in_reg_nq;
RegisterBit in_reg (.ACLK1(ACLK1), .ena(load), .d(sin), .nq(in_reg_nq) );
dlatch out_latch (.d(in_reg_nq), .en(ACLK1), .nq(sout) );
endmodule // NOISE_RandomLFSRBit |
module Test(
ACLK1,
RES, DB, W401A, n_R4018, n_R4019, n_R401A,
SQA_in, SQB_in, TRI_in, RND_in, DMC_in,
LOCK);
input ACLK1;
input RES;
inout [7:0] DB;
input W401A;
input n_R4018;
input n_R4019;
input n_R401A;
input [3:0] SQA_in;
input [3:0] SQB_in;
input [3:0] TRI_in;
input [3:0] RND_in;
input [6:0] DMC_in;
output LOCK;
sdffre LOCK_FF(
.d(DB[7]),
.en(W401A),
.res(RES),
.phi_keep(ACLK1),
.q(LOCK) );
bustris sqa_tris [3:0] (
.a(~SQA_in),
.n_x(DB[3:0]),
.n_en(n_R4018) );
bustris sqb_tris [3:0] (
.a(~SQB_in),
.n_x(DB[7:4]),
.n_en(n_R4018) );
bustris tria_tris [3:0] (
.a(~TRI_in),
.n_x(DB[3:0]),
.n_en(n_R4019) );
bustris rnd_tris [3:0] (
.a(~RND_in),
.n_x(DB[7:4]),
.n_en(n_R4019) );
bustris dmc_tris [6:0] (
.a(~DMC_in),
.n_x(DB[6:0]),
.n_en(n_R401A) );
endmodule // Test |
module DAC_Square(SQA, SQB, AUX_A);
input [3:0] SQA;
input [3:0] SQB;
output [7:0] AUX_A;
assign AUX_A = {SQB,SQA};
endmodule // DAC_Square |
module DAC_Others(TRI, RND, DMC, AUX_B);
input [3:0] TRI;
input [3:0] RND;
input [6:0] DMC;
output [14:0] AUX_B;
assign AUX_B = {DMC,RND,TRI};
endmodule // DAC_Others |
module ApuPadsLogic(
CLKPad, n_CLK_frompad,
n_RESPad, RES_frompad,
n_IRQPad, Timer_Int, n_IRQ_tocore,
n_M2_topad, M2Pad,
DBGPad, DBG_frompad,
RD, WR, DB, DPads,
RW_topad, RWPad,
Addr_topad, APads);
input CLKPad; // CLK Input Pad
output n_CLK_frompad; // Output intermediate signal /CLK for divider
input n_RESPad; // Input Pad /RES
output RES_frompad; // Value from /RES pad (inverted for convenience)
input n_IRQPad; // Input Pad /RES
input Timer_Int; // Timer interrupt (combined with DMC interrupt)
output n_IRQ_tocore; // Signal /IRQ for 6502 core
input n_M2_topad; // Output signal #M2 from the divider for pad M2
output M2Pad; // Input Pad /RES
input DBGPad; // DBG Input Pad (2A03 Test Mode)
output DBG_frompad; // Value from the DBG pad to the APU internals
input RD; // Internal signal for data bus mode (read/write)
input WR; // Internal signal for data bus mode (read/write)
inout [7:0] DB; // Internal data bus
inout [7:0] DPads; // External data bus pads
input RW_topad; // The value for the R/W pad (obtained in the ...mm...sprite DMA buffer)
output RWPad; // Output Pad R/W
input [15:0] Addr_topad; // Value for address bus pads
output [15:0] APads; // External address bus pads
// Connect all
not (RES_frompad, n_RESPad);
wire [15:0] ax;
pnor addr_out [15:0] (
.a0(Addr_topad),
.a1({16{RES_frompad}}),
.x(ax) );
bustris addr_tris [15:0] (
.a(ax),
.n_x(APads),
.n_en(RES_frompad) );
bustris data_tris_in [7:0] (
.a(~DPads),
.n_x(DB),
.n_en(WR) );
wire [7:0] dx;
pnor data_out [7:0] (
.a0(DB),
.a1({8{RD}}),
.x(dx) );
bustris data_tris_out [7:0] (
.a(dx),
.n_x(DPads),
.n_en(RD) );
wire rw;
nor (rw, RW_topad, RES_frompad);
bustris rw_tris (
.a(rw),
.n_x(RWPad),
.n_en(RES_frompad) );
not (n_CLK_frompad, CLKPad);
assign DBG_frompad = DBGPad;
wire nDBG;
not (nDBG, DBG_frompad);
wire NotDBG_RES;
nor (NotDBG_RES, ~nDBG, ~RES_frompad);
wire m2;
nor (m2, n_M2_topad, NotDBG_RES);
bufif0 (M2Pad, m2, NotDBG_RES); // data_out, data_in, ctrl
nor (n_IRQ_tocore, ~n_IRQPad, Timer_Int);
endmodule // PadsLogic |
module RegisterBit (ACLK1, ena, d, q, nq);
input ACLK1;
input ena;
input d;
output q;
output nq;
wire tq;
wire ntq;
wire latch_in;
assign latch_in = ena ? d : (ACLK1 ? q : 1'bz);
dlatch transp (.d(latch_in), .en(1'b1), .nq(ntq));
assign tq = ~ntq;
assign q = tq;
assign nq = ntq;
endmodule // RegisterBit |
module RegisterBitRes (ACLK1, ena, d, res, q, nq);
input ACLK1;
input ena;
input d;
input res;
output q;
output nq;
wire tq;
wire ntq;
wire latch_in;
assign latch_in = ena ? d : (ACLK1 ? q : 1'bz);
dlatch transp (.d(latch_in & ~res), .en(1'b1), .nq(ntq));
assign tq = ~ntq;
assign q = tq;
assign nq = ntq;
endmodule // RegisterBitRes2 |
module RegisterBitRes2 (ACLK1, ena, d, res1, res2, q, nq);
input ACLK1;
input ena;
input d;
input res1;
input res2;
output q;
output nq;
wire tq;
wire ntq;
wire latch_in;
assign latch_in = ena ? d : (ACLK1 ? q : 1'bz);
dlatch transp (.d(latch_in & ~(res1 | res2)), .en(1'b1), .nq(ntq));
assign tq = ~ntq;
assign q = tq;
assign nq = ntq;
endmodule // RegisterBitRes2 |
module CounterBit (ACLK1, d, load, clear, step, cin, q, nq, cout);
input ACLK1;
input d;
input load;
input clear;
input step;
input cin;
output q;
output nq;
output cout;
wire tq;
wire ntq;
wire latch_in;
wire cgnq;
assign latch_in = load ? d : (clear ? 1'b0 : (step ? cgnq : (ACLK1 ? tq : 1'bz) ) );
dlatch transp (.d(latch_in), .en(1'b1), .nq(ntq));
assign tq = ~ntq;
dlatch cg (.d(cin ? tq : ntq), .en(ACLK1), .nq(cgnq));
assign cout = ~(~cin | ntq);
assign q = tq;
assign nq = ntq;
endmodule // CounterBit |
module SquareChan (
nACLK2, ACLK1,
RES, DB, WR0, WR1, WR2, WR3, nLFO1, nLFO2, SQ_LC, NOSQ, LOCK, AdderCarryMode,
SQ_Out);
input nACLK2;
input ACLK1;
input RES;
inout [7:0] DB;
input WR0;
input WR1;
input WR2;
input WR3;
input nLFO1;
input nLFO2;
output SQ_LC;
input NOSQ;
input LOCK;
input AdderCarryMode; // 0: input n_carry connected to INC, 1: input n_carry connected to Vdd
output [3:0] SQ_Out;
// Internal wires
wire [10:0] Fx;
wire [10:0] nFx;
wire [10:0] n_sum;
wire [10:0] S;
wire [2:0] SR;
wire [11:0] BS;
wire DEC;
wire INC;
wire n_COUT;
wire SW_UVF;
wire FCO;
wire FLOAD;
wire DO_SWEEP;
wire SW_OVF;
wire DUTY;
wire [3:0] Vol;
// Instantiate
RegisterBit dir_reg (.ACLK1(ACLK1), .ena(WR1), .d(DB[3]), .q(DEC) );
assign INC = ~DEC;
assign BS = {DEC, DEC ? nFx : Fx};
SQUARE_FreqReg freq_reg (.nACLK2(nACLK2), .ACLK1(ACLK1), .WR2(WR2), .WR3(WR3), .DB(DB), .DO_SWEEP(DO_SWEEP), .n_sum(n_sum), .nFx(nFx), .Fx(Fx) );
SQUARE_ShiftReg shift_reg (.ACLK1(ACLK1), .WR1(WR1), .DB(DB), .SR(SR) );
SQUARE_BarrelShifter barrel (.BS(BS), .SR(SR), .S(S) );
SQUARE_Adder adder (.CarryMode(AdderCarryMode), .INC(INC), .nFx(nFx), .Fx(Fx), .S(S), .n_sum(n_sum), .n_COUT(n_COUT), .SW_UVF(SW_UVF) );
SQUARE_FreqCounter freq_cnt (.nACLK2(nACLK2), .ACLK1(ACLK1), .RES(RES), .Fx(Fx), .FCO(FCO), .FLOAD(FLOAD) );
Envelope_Unit env_unit (.ACLK1(ACLK1), .RES(RES), .WR_Reg(WR0), .WR_LC(WR3), .n_LFO1(nLFO1), .DB(DB), .V(Vol), .LC(SQ_LC) );
SQUARE_Sweep sweep_unit (.ACLK1(ACLK1), .RES(RES), .WR1(WR1), .SR(SR), .DEC(DEC), .n_COUT(n_COUT), .SW_UVF(SW_UVF), .NOSQ(NOSQ), .n_LFO2(nLFO2),
.DB(DB), .DO_SWEEP(DO_SWEEP), .SW_OVF(SW_OVF) );
SQUARE_Duty duty_unit (.ACLK1(ACLK1), .RES(RES), .FLOAD(FLOAD), .FCO(FCO), .WR0(WR0), .WR3(WR3), .DB(DB), .DUTY(DUTY) );
SQUARE_Output sqo (.ACLK1(ACLK1), .DUTY(DUTY), .LOCK(LOCK), .SW_UVF(SW_UVF), .NOSQ(NOSQ), .SW_OVF(SW_OVF), .V(Vol), .SQ_Out(SQ_Out) );
endmodule // SquareChan |
module SQUARE_FreqReg (nACLK2, ACLK1, WR2, WR3, DB, DO_SWEEP, n_sum, nFx, Fx);
input nACLK2;
input ACLK1;
input WR2;
input WR3;
inout [7:0] DB;
input DO_SWEEP;
input [10:0] n_sum;
output [10:0] nFx;
output [10:0] Fx;
wire ACLK3;
assign ACLK3 = ~nACLK2;
SQUARE_FreqRegBit freq_reg [10:0] (.ACLK3(ACLK3), .ACLK1(ACLK1),
.WR({ {3{WR3}}, {8{WR2}} }), .DB_in({ DB[2:0], DB[7:0] }), .DO_SWEEP(DO_SWEEP), .n_sum(n_sum), .nFx(nFx), .Fx(Fx) );
endmodule // SQUARE_FreqReg |
module SQUARE_FreqRegBit (ACLK3, ACLK1, WR, DB_in, DO_SWEEP, n_sum, nFx, Fx);
input ACLK3;
input ACLK1;
input WR;
inout DB_in;
input DO_SWEEP;
input n_sum;
output nFx;
output Fx;
wire d;
wire transp_latch_q;
wire sum_latch_q;
wire sum_latch_nq;
assign d = WR ? DB_in : (ACLK3 ? Fx : 1'bz);
dlatch transp_latch (.d(d), .en(1'b1), .q(transp_latch_q) );
dlatch sum_latch (.d(n_sum), .en(ACLK1), .q(sum_latch_q), .nq(sum_latch_nq) );
nor (nFx, (sum_latch_nq & DO_SWEEP), transp_latch_q);
nor (Fx, nFx, (sum_latch_q & DO_SWEEP));
endmodule // SQUARE_FreqRegBit |
module SQUARE_ShiftReg (ACLK1, WR1, DB, SR);
input ACLK1;
input WR1;
input [7:0] DB;
output [2:0] SR;
RegisterBit sr_reg [2:0] (.ACLK1(ACLK1), .ena(WR1), .d(DB[2:0]), .q(SR) );
endmodule // SQUARE_ShiftReg |
module SQUARE_BarrelShifter (BS, SR, S);
input [11:0] BS;
input [2:0] SR;
output [10:0] S;
wire [10:0] q1;
wire [10:0] q2;
assign q1[0] = SR[0] ? BS[1] : BS[0];
assign q1[1] = SR[0] ? BS[2] : BS[1];
assign q1[2] = SR[0] ? BS[3] : BS[2];
assign q1[3] = SR[0] ? BS[4] : BS[3];
assign q1[4] = SR[0] ? BS[5] : BS[4];
assign q1[5] = SR[0] ? BS[6] : BS[5];
assign q1[6] = SR[0] ? BS[7] : BS[6];
assign q1[7] = SR[0] ? BS[8] : BS[7];
assign q1[8] = SR[0] ? BS[9] : BS[8];
assign q1[9] = SR[0] ? BS[10] : BS[9];
assign q1[10] = SR[0] ? BS[11] : BS[10];
assign q2[0] = SR[1] ? q1[2] : q1[0];
assign q2[1] = SR[1] ? q1[3] : q1[1];
assign q2[2] = SR[1] ? q1[4] : q1[2];
assign q2[3] = SR[1] ? q1[5] : q1[3];
assign q2[4] = SR[1] ? q1[6] : q1[4];
assign q2[5] = SR[1] ? q1[7] : q1[5];
assign q2[6] = SR[1] ? q1[8] : q1[6];
assign q2[7] = SR[1] ? q1[9] : q1[7];
assign q2[8] = SR[1] ? q1[10] : q1[8];
assign q2[9] = SR[1] ? BS[11] : q1[9];
assign q2[10] = SR[1] ? BS[11] : q1[10];
assign S[0] = SR[2] ? q2[4] : q2[0];
assign S[1] = SR[2] ? q2[5] : q2[1];
assign S[2] = SR[2] ? q2[6] : q2[2];
assign S[3] = SR[2] ? q2[7] : q2[3];
assign S[4] = SR[2] ? q2[8] : q2[4];
assign S[5] = SR[2] ? q2[9] : q2[5];
assign S[6] = SR[2] ? q2[10] : q2[6];
assign S[7] = SR[2] ? BS[11] : q2[7];
assign S[8] = SR[2] ? BS[11] : q2[8];
assign S[9] = SR[2] ? BS[11] : q2[9];
assign S[10] = SR[2] ? BS[11] : q2[10];
endmodule // SQUARE_BarrelShifter |
module SQUARE_Adder (CarryMode, INC, nFx, Fx, S, n_sum, n_COUT, SW_UVF);
input CarryMode;
input INC;
input [10:0] nFx;
input [10:0] Fx;
input [10:0] S;
output [10:0] n_sum;
output n_COUT;
output SW_UVF;
wire n_cin;
assign n_cin = CarryMode ? 1'b1 : INC;
wire [10:0] n_cout;
wire [10:0] cout;
SQUARE_AdderBit adder [10:0] (.F(Fx), .nF(nFx), .S(S), .nS(~S),
.C({cout[9:0],~n_cin}), .nC({n_cout[9:0],n_cin}), .n_cout(n_cout), .cout(cout), .n_sum(n_sum) );
assign n_COUT = n_cout[10];
nor (SW_UVF, Fx[2], Fx[3], Fx[4], Fx[5], Fx[6], Fx[7], Fx[8], Fx[9], Fx[10]);
endmodule // SQUARE_Adder |
module SQUARE_AdderBit (F, nF, S, nS, C, nC, n_cout, cout, n_sum);
input F;
input nF;
input S;
input nS;
input C;
input nC;
output n_cout;
output cout;
output n_sum;
nor (n_cout, (F & S), (F & nS & C), (nF & S & C));
nor (n_sum, (F & nS & nC), (nF & S & nC), (nF & nS & C), (F & S & C) );
assign cout = ~n_cout;
endmodule // SQUARE_AdderBit |
module SQUARE_FreqCounter (nACLK2, ACLK1, RES, Fx, FCO, FLOAD);
input nACLK2;
input ACLK1;
input RES;
input [10:0] Fx;
output FCO;
output FLOAD;
wire FSTEP;
wire fco_latch_nq;
wire [10:0] cout;
dlatch fco_latch (.d(FCO), .en(ACLK1), .nq(fco_latch_nq) );
DownCounterBit freq_cnt [10:0] (.ACLK1(ACLK1), .d(Fx), .load(FLOAD), .clear(RES), .step(FSTEP), .cin({cout[9:0],1'b1}), .cout(cout) );
assign FCO = cout[10];
nor (FLOAD, nACLK2, fco_latch_nq);
nor (FSTEP, nACLK2, ~fco_latch_nq);
endmodule // SQUARE_FreqCounter |
module SQUARE_Sweep (ACLK1, RES, WR1, SR, DEC, n_COUT, SW_UVF, NOSQ, n_LFO2, DB, DO_SWEEP, SW_OVF);
input ACLK1;
input RES;
input WR1;
input [2:0] SR;
input DEC;
input n_COUT;
input SW_UVF;
input NOSQ;
input n_LFO2;
inout [7:0] DB;
output DO_SWEEP;
output SW_OVF;
wire SRZ;
wire SWDIS;
wire SWRELOAD;
wire SSTEP;
wire SLOAD;
wire SCO;
wire n_SCO;
wire reload_latch_q;
wire sco_latch_q;
wire reload_ff_q;
wire [2:0] sweep_reg_q;
wire [2:0] cnt_q; // debug
wire [2:0] cout;
wire temp_reload;
dlatch reload_latch (.d(reload_ff_q), .en(ACLK1), .q(reload_latch_q), .nq(SWRELOAD) );
dlatch sco_latch (.d(SCO), .en(ACLK1), .q(sco_latch_q), .nq(n_SCO) );
rsff reload_ff (.r(WR1), .s(~(n_LFO2 | reload_latch_q)), .q(reload_ff_q) );
RegisterBit swdis_reg (.ACLK1(ACLK1), .ena(WR1), .d(DB[7]), .nq(SWDIS) );
RegisterBit sweep_reg [2:0] (.ACLK1(ACLK1), .ena(WR1), .d(DB[6:4]), .q(sweep_reg_q) );
DownCounterBit sweep_cnt [2:0] (.ACLK1(ACLK1), .d(sweep_reg_q), .load(SLOAD), .clear(RES), .step(SSTEP), .cin({cout[1:0],1'b1}), .cout(cout), .q(cnt_q) );
assign SCO = cout[2];
nor (temp_reload, SWRELOAD, sco_latch_q);
nor (SSTEP, n_LFO2, ~temp_reload);
nor (SLOAD, n_LFO2, temp_reload);
nor (SW_OVF, DEC, n_COUT);
nor (SRZ, SR[0], SR[1], SR[2]);
nor (DO_SWEEP, SRZ, SWDIS, NOSQ, SW_OVF, n_SCO, n_LFO2, SW_UVF);
endmodule // SQUARE_Sweep |
module SQUARE_Duty (ACLK1, RES, FLOAD, FCO, WR0, WR3, DB, DUTY);
input ACLK1;
input RES;
input FLOAD;
input FCO;
input WR0;
input WR3;
inout [7:0] DB;
output DUTY;
wire [2:0] cout;
wire [2:0] DC;
wire [1:0] DT;
wire [3:0] in;
RegisterBit duty_reg [1:0] (.ACLK1(ACLK1), .ena(WR0), .d(DB[7:6]), .q(DT) );
DownCounterBit duty_cnt [2:0] (.ACLK1(ACLK1), .d(3'b000), .load(WR3), .clear(RES), .step(FLOAD), .cin({cout[1:0],1'b1}), .q(DC), .cout(cout) );
nand (in[3], DC[1], DC[2]);
nor (in[0], ~DC[0], in[3]);
assign in[1] = ~in[3];
assign in[2] = DC[2];
assign DUTY = DT[1] ? (DT[0] ? in[3] : in[2]) : (DT[0] ? in[1] : in[0]); // mux 4-to-1
endmodule // SQUARE_Duty |
module SQUARE_Output (ACLK1, DUTY, LOCK, SW_UVF, NOSQ, SW_OVF, V, SQ_Out);
input ACLK1;
input DUTY;
input LOCK;
input SW_UVF;
input NOSQ;
input SW_OVF;
input [3:0] V;
output [3:0] SQ_Out;
wire d;
wire sqo_latch_q;
wire sqv;
nor (d, ~DUTY, SW_UVF, NOSQ, SW_OVF);
dlatch sqo_latch (.d(d), .en(ACLK1), .q(sqo_latch_q) );
nor (sqv, sqo_latch_q, LOCK);
pnor vout [3:0] (.a0({4{sqv}}), .a1(~V), .x(SQ_Out) );
endmodule // SQUARE_Output |
module Envelope_Unit (ACLK1, RES, WR_Reg, WR_LC, n_LFO1, DB, V, LC);
input ACLK1;
input RES;
input WR_Reg;
input WR_LC;
input n_LFO1;
inout [7:0] DB;
output [3:0] V;
output LC;
// Internal wires
wire RELOAD;
wire RLOAD;
wire RSTEP;
wire RCO;
wire ESTEP;
wire ERES;
wire EIN;
wire ECO;
wire [3:0] VOL;
wire [3:0] ENV;
wire ENVDIS;
wire [3:0] decay_cnt_cout;
wire [3:0] env_cnt_cout;
wire EnvReload_q;
wire erld_latch_q;
wire reload_latch_q;
wire rco_latch_q;
wire rco_latch_nq;
wire eco_latch_q;
wire eco_reload;
// Logic
RegisterBit envdis_reg (.ACLK1(ACLK1), .ena(WR_Reg), .d(DB[4]), .q(ENVDIS) );
RegisterBit lc_reg (.ACLK1(ACLK1), .ena(WR_Reg), .d(DB[5]), .nq(LC) );
RegisterBit vol_reg [3:0] (.ACLK1(ACLK1), .ena(WR_Reg), .d(DB[3:0]), .q(VOL) );
DownCounterBit decay_cnt [3:0] (.ACLK1(ACLK1), .d(VOL), .load(RLOAD), .clear(RES), .step(RSTEP), .cin({decay_cnt_cout[2:0],1'b1}), .cout(decay_cnt_cout) );
DownCounterBit env_cnt [3:0] (.ACLK1(ACLK1), .d({4{EIN}}), .load(ERES), .clear(RES), .step(ESTEP), .q(ENV), .cin({env_cnt_cout[2:0],1'b1}), .cout(env_cnt_cout) );
assign RCO = decay_cnt_cout[3];
assign ECO = env_cnt_cout[3];
rsff EnvReload (.r(WR_LC), .s(~(n_LFO1 | erld_latch_q)), .q(EnvReload_q), .nq(RELOAD) );
dlatch erld_latch (.d(EnvReload_q), .en(ACLK1), .q(erld_latch_q) );
dlatch reload_latch (.d(RELOAD), .en(ACLK1), .q(reload_latch_q) );
dlatch rco_latch (.d(~(RCO | RELOAD)), .en(ACLK1), .q(rco_latch_q), .nq(rco_latch_nq) );
dlatch eco_latch (.d(ECO & ~RELOAD), .en(ACLK1), .q(eco_latch_q) );
nor (RLOAD, n_LFO1, rco_latch_q);
nor (RSTEP, n_LFO1, rco_latch_nq);
nand (EIN, eco_latch_q, LC);
nor (eco_reload, eco_latch_q, reload_latch_q);
nor (ESTEP, ~RLOAD, ~eco_reload);
nor (ERES, ~RLOAD, eco_reload);
assign V = ENVDIS ? VOL : ENV;
endmodule // Envelope_Unit |
module IOPorts(
nACLK2, ACLK1, W4016, n_R4016, n_R4017, DB, RES,
OUT0_Pad, OUT1_Pad, OUT2_Pad, nIN0_Pad, nIN1_Pad);
input nACLK2;
input ACLK1;
input W4016;
input n_R4016;
input n_R4017;
inout [7:0] DB;
input RES;
output OUT0_Pad;
output OUT1_Pad;
output OUT2_Pad;
output nIN0_Pad;
output nIN1_Pad;
wire [2:0] OUT_topad;
wire [1:0] IN_topad;
// The output value for pins /IN0-1 is the internal signals /R4016 and /R4017 from the register selector.
assign IN_topad[0] = n_R4016;
assign IN_topad[1] = n_R4017;
OutPort out_ports [2:0] (
.DB_bit(DB[2:0]),
.W4016(W4016),
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.OUT_val(OUT_topad) );
IOPad out_pads [2:0] (
.bit_val(OUT_topad[2:0]),
.res(RES),
.pad({OUT2_Pad, OUT1_Pad, OUT0_Pad}) );
IOPad in_pads [1:0] (
.bit_val(IN_topad[1:0]),
.res(RES),
.pad({nIN1_Pad, nIN0_Pad}) );
endmodule // IOPorts |
module OutPort(DB_bit, W4016, nACLK2, ACLK1, OUT_val);
inout DB_bit;
input W4016;
input nACLK2;
input ACLK1;
output OUT_val;
wire ff_out;
wire ACLK5;
assign ACLK5 = ~nACLK2; // Other ACLK
RegisterBit out_ff (
.d(DB_bit),
.ena(W4016),
.ACLK1(ACLK1),
.q(ff_out) );
wire n_latch_out;
dlatch out_latch (
.d(ff_out),
.en(ACLK5),
.nq(n_latch_out) );
assign OUT_val = ~n_latch_out;
endmodule // OutPort |
module IOPad(bit_val, res, pad);
input bit_val;
input res;
output pad;
wire n1;
nor (n1, bit_val, res);
bustris io_tris(
.a(n1),
.n_x(pad),
.n_en(res) );
endmodule // IOPad |
module ApuRegsDecoder (
PHI1,
Addr_fromcore, Addr_frommux, RnW_fromcore, DBG_frompad,
n_R4018, n_R401A, n_R4015, W4002, W4001, W4005, W4006, W4008, W400A, W400B, W400E, W4013, W4012, W4010, W4014,
n_R4019, W401A, W4003, W4007, W4004, W400C, W4000, W4015, W4011, W400F, n_R4017, n_R4016, W4016, W4017,
n_DBGRD);
input PHI1;
// ⚠️ The APU registers address space is selected by the value of the CPU address bus (CPU_Ax). But the choice of register is made by the value of the address, which is formed at the address multiplexer of DMA-controller (signals A0-A4).
input [15:0] Addr_fromcore;
input [15:0] Addr_frommux;
input RnW_fromcore;
input DBG_frompad;
output n_R4018;
output n_R401A;
output n_R4015;
output W4002;
output W4001;
output W4005;
output W4006;
output W4008;
output W400A;
output W400B;
output W400E;
output W4013;
output W4012;
output W4010;
output W4014;
output n_R4019;
output W401A;
output W4003;
output W4007;
output W4004;
output W400C;
output W4000;
output W4015;
output W4011;
output W400F;
output n_R4017;
output n_R4016;
output W4016;
output W4017;
output n_DBGRD;
// Check that the CPU address falls in the APU registers mapped to the address space.
wire [15:0] CpuA;
assign CpuA = Addr_fromcore;
wire REGWR;
wire nREGWR;
nor (REGWR, CpuA[5], CpuA[6], CpuA[7], CpuA[8], CpuA[9], CpuA[10], CpuA[11], CpuA[12], CpuA[13], ~CpuA[14], CpuA[15], RnW_fromcore);
assign nREGWR = ~REGWR;
wire REGRD;
wire nREGRD;
nor (REGRD, CpuA[5], CpuA[6], CpuA[7], CpuA[8], CpuA[9], CpuA[10], CpuA[11], CpuA[12], CpuA[13], ~CpuA[14], CpuA[15], ~RnW_fromcore);
assign nREGRD = ~REGRD;
nand (n_DBGRD, DBG_frompad, ~nREGRD);
// PLA
wire [28:0] pla;
ApuRegs_PLA regs_pla (
.nREGRD(nREGRD),
.nREGWR(nREGWR),
.A(Addr_frommux[4:0]),
.nA(~Addr_frommux[4:0]),
.pla(pla) );
// Select a register index.
// Note that during PHI1 all write operations are disabled.
nand(n_R4018, DBG_frompad, pla[0]);
nand(n_R401A, DBG_frompad, pla[2]);
not(n_R4015, pla[4]);
nor(W4002, PHI1, ~pla[6]);
nor(W4001, PHI1, ~pla[8]);
nor(W4005, PHI1, ~pla[10]);
nor(W4006, PHI1, ~pla[12]);
nor(W4008, PHI1, ~pla[14]);
nor(W400A, PHI1, ~pla[16]);
nor(W400B, PHI1, ~pla[18]);
nor(W400E, PHI1, ~pla[20]);
nor(W4013, PHI1, ~pla[22]);
nor(W4012, PHI1, ~pla[24]);
nor(W4010, PHI1, ~pla[26]);
nor(W4014, PHI1, ~pla[28]);
nand(n_R4019, DBG_frompad, pla[1]);
wire w401a_temp;
nand (w401a_temp, DBG_frompad, pla[3]);
nor(W401A, PHI1, w401a_temp);
nor(W4003, PHI1, ~pla[5]);
nor(W4007, PHI1, ~pla[7]);
nor(W4004, PHI1, ~pla[9]);
nor(W400C, PHI1, ~pla[11]);
nor(W4000, PHI1, ~pla[13]);
nor(W4015, PHI1, ~pla[15]);
nor(W4011, PHI1, ~pla[17]);
nor(W400F, PHI1, ~pla[19]);
not(n_R4017, pla[21]);
not(n_R4016, pla[23]);
nor(W4016, PHI1, ~pla[25]);
nor(W4017, PHI1, ~pla[27]);
endmodule // ApuRegsDecoder |
module ApuRegs_PLA(nREGRD, nREGWR, A, nA, pla);
input nREGRD;
input nREGWR;
input [4:0] A;
input [4:0] nA;
output [28:0] pla;
nor (pla[0], nREGRD, A[0], A[1], A[2], nA[3], nA[4]);
nor (pla[1], nREGRD, nA[0], A[1], A[2], nA[3], nA[4]);
nor (pla[2], nREGRD, A[0], nA[1], A[2], nA[3], nA[4]);
nor (pla[3], nREGWR, A[0], nA[1], A[2], nA[3], nA[4]);
nor (pla[4], nREGRD, nA[0], A[1], nA[2], A[3], nA[4]);
nor (pla[5], nREGWR, nA[0], nA[1], A[2], A[3], A[4]);
nor (pla[6], nREGWR, A[0], nA[1], A[2], A[3], A[4]);
nor (pla[7], nREGWR, nA[0], nA[1], nA[2], A[3], A[4]);
nor (pla[8], nREGWR, nA[0], A[1], A[2], A[3], A[4]);
nor (pla[9], nREGWR, A[0], A[1], nA[2], A[3], A[4]);
nor (pla[10], nREGWR, nA[0], A[1], nA[2], A[3], A[4]);
nor (pla[11], nREGWR, A[0], A[1], nA[2], nA[3], A[4]);
nor (pla[12], nREGWR, A[0], nA[1], nA[2], A[3], A[4]);
nor (pla[13], nREGWR, A[0], A[1], A[2], A[3], A[4]);
nor (pla[14], nREGWR, A[0], A[1], A[2], nA[3], A[4]);
nor (pla[15], nREGWR, nA[0], A[1], nA[2], A[3], nA[4]);
nor (pla[16], nREGWR, A[0], nA[1], A[2], nA[3], A[4]);
nor (pla[17], nREGWR, nA[0], A[1], A[2], A[3], nA[4]);
nor (pla[18], nREGWR, nA[0], nA[1], A[2], nA[3], A[4]);
nor (pla[19], nREGWR, nA[0], nA[1], nA[2], nA[3], A[4]);
nor (pla[20], nREGWR, A[0], nA[1], nA[2], nA[3], A[4]);
nor (pla[21], nREGRD, nA[0], nA[1], nA[2], A[3], nA[4]);
nor (pla[22], nREGWR, nA[0], nA[1], A[2], A[3], nA[4]);
nor (pla[23], nREGRD, A[0], nA[1], nA[2], A[3], nA[4]);
nor (pla[24], nREGWR, A[0], nA[1], A[2], A[3], nA[4]);
nor (pla[25], nREGWR, A[0], nA[1], nA[2], A[3], nA[4]);
nor (pla[26], nREGWR, A[0], A[1], A[2], A[3], nA[4]);
nor (pla[27], nREGWR, nA[0], nA[1], nA[2], A[3], nA[4]);
nor (pla[28], nREGWR, A[0], A[1], nA[2], A[3], nA[4]);
endmodule // ApuRegs_PLA |
module TriangleChan(
PHI1, ACLK1,
RES, DB, W4008, W400A, W400B, W401A, nLFO1, TRI_LC, NOTRI, LOCK,
TRI_Out);
input PHI1;
input ACLK1;
input RES;
inout [7:0] DB;
input W4008;
input W400A;
input W400B;
input W401A;
input nLFO1;
output TRI_LC;
input NOTRI;
input LOCK;
output [3:0] TRI_Out;
// Internal wires
wire TCO;
wire FOUT;
wire LOAD;
wire STEP;
wire FLOAD;
wire FSTEP;
wire TSTEP;
// Instantiate
TRIANGLE_Control ctrl (.PHI1(PHI1), .ACLK1(ACLK1), .W4008(W4008), .W400B(W400B), .n_LFO1(nLFO1), .NOTRI(NOTRI), .LOCK(LOCK), .TCO(TCO), .FOUT(FOUT),
.DB(DB), .TRI_LC(TRI_LC), .LOAD(LOAD), .STEP(STEP), .FLOAD(FLOAD), .FSTEP(FSTEP), .TSTEP(TSTEP) );
TRIANGLE_LinearCounter lin_cnt (.ACLK1(ACLK1), .RES(RES), .W4008(W4008), .LOAD(LOAD), .STEP(STEP), .DB(DB), .TCO(TCO) );
TRIANGLE_FreqCounter freq_cnt (.PHI1(PHI1), .RES(RES), .W400A(W400A), .W400B(W400B), .DB(DB), .FLOAD(FLOAD), .FSTEP(FSTEP), .FOUT(FOUT) );
TRIANGLE_Output tri_out (.PHI1(PHI1), .RES(RES), .W401A(W401A), .TSTEP(TSTEP), .DB(DB), .TRI_Out(TRI_Out) );
endmodule // TriangleChan |
module TRIANGLE_Control (PHI1, ACLK1, W4008, W400B, n_LFO1, NOTRI, LOCK, TCO, FOUT, DB, TRI_LC, LOAD, STEP, FLOAD, FSTEP, TSTEP);
input PHI1;
input ACLK1;
input W4008;
input W400B;
input n_LFO1;
input NOTRI;
input LOCK;
input TCO;
input FOUT;
inout [7:0] DB;
output TRI_LC;
output LOAD;
output STEP;
output FLOAD;
output FSTEP;
output TSTEP;
wire n_FOUT;
wire TRELOAD;
wire lc_reg_q;
wire Reload_FF_q;
wire reload_latch1_q;
wire reload_latch2_q;
wire reload_latch2_nq;
wire tco_latch_q;
dlatch fout_latch (.d(FOUT), .en(PHI1), .nq(n_FOUT) );
nor (FLOAD, PHI1, n_FOUT);
nor (FSTEP, PHI1, ~n_FOUT);
RegisterBit lc_reg (.ACLK1(ACLK1), .ena(W4008), .d(DB[7]), .q(lc_reg_q), .nq(TRI_LC) );
rsff Reload_FF (.r(~(reload_latch1_q | lc_reg_q | n_LFO1)), .s(W400B), .q(TRELOAD), .nq(Reload_FF_q) );
dlatch reload_latch1 (.d(Reload_FF_q), .en(ACLK1), .q(reload_latch1_q) );
dlatch reload_latch2 (.d(TRELOAD), .en(ACLK1), .q(reload_latch2_q), .nq(reload_latch2_nq) );
dlatch tco_latch (.d(TCO), .en(ACLK1), .q(tco_latch_q) );
nor (LOAD, n_LFO1, reload_latch2_nq);
nor (STEP, n_LFO1, reload_latch2_q, tco_latch_q);
nor (TSTEP, TCO, LOCK, PHI1, NOTRI, n_FOUT);
endmodule // TRIANGLE_Control |
module TRIANGLE_LinearCounter (ACLK1, RES, W4008, LOAD, STEP, DB, TCO);
input ACLK1;
input RES;
input W4008;
input LOAD;
input STEP;
inout [7:0] DB;
output TCO;
wire [6:0] lq;
wire [6:0] cout;
RegisterBit lin_reg [6:0] (.ACLK1(ACLK1), .ena(W4008), .d(DB[6:0]), .q(lq) );
DownCounterBit lin_cnt [6:0] (.ACLK1(ACLK1), .d(lq), .load(LOAD), .clear(RES), .step(STEP), .cin({cout[5:0],1'b1}), .cout(cout) );
assign TCO = cout[6];
endmodule // TRIANGLE_LinearCounter |
module TRIANGLE_FreqCounter (PHI1, RES, W400A, W400B, DB, FLOAD, FSTEP, FOUT);
input PHI1;
input RES;
input W400A;
input W400B;
inout [7:0] DB;
input FLOAD;
input FSTEP;
output FOUT;
wire [10:0] fq;
wire [10:0] cout;
RegisterBit freq_reg [10:0] (.ACLK1(PHI1), .ena({ {3{W400B}}, {8{W400A}} }), .d({DB[2:0],DB[7:0]}), .q(fq) );
DownCounterBit freq_cnt [10:0] (.ACLK1(PHI1), .d(fq), .load(FLOAD), .clear(RES), .step(FSTEP), .cin({cout[9:0],1'b1}), .cout(cout) );
assign FOUT = cout[10];
endmodule // TRIANGLE_FreqCounter |
module TRIANGLE_Output (PHI1, RES, W401A, TSTEP, DB, TRI_Out);
input PHI1;
input RES;
input W401A;
input TSTEP;
inout [7:0] DB;
output [3:0] TRI_Out;
wire [4:0] cout;
wire [4:0] T;
wire [4:0] nT;
// The developers decided to use PHI1 for the triangle channel instead of ACLK to smooth out the "stepped" signal.
CounterBit out_cnt [4:0] (.ACLK1(PHI1), .d(DB[4:0]), .load(W401A), .clear(RES), .step(TSTEP), .cin({cout[3:0],1'b1}), .q(T), .nq(nT), .cout(cout) );
assign TRI_Out = ~(T[4] ? nT[3:0] : T[3:0]);
endmodule // TRIANGLE_Output |
module Sprite_DMA(
ACLK1, nACLK2, PHI1,
RES, RnW, W4014, DB,
RUNDMC, n_DMCAB, DMCRDY, DMC_Addr, CPU_Addr,
Addr, RDY_tocore, SPR_PPU);
input ACLK1;
input nACLK2;
input PHI1; // Sprite DMA can only start if the processor goes into a read cycle (PHI1 = 0 and R/W = 1)
// This is done to delay the start of the DMA because the RDY clearing is ignored on the 6502 write cycles.
input RES;
input RnW;
input W4014; // Writing to register $4014 clears the lower part of the address and puts the value to be written into the higher part. The DMA process then starts.
inout [7:0] DB;
input RUNDMC; // As long as the RUNDMC signal is 1 the sprite DMA is in standby mode
input n_DMCAB; // The address bus is controlled by the DMC circuitry to perform DMC DMA
input DMCRDY; // DMC Ready. If the DMC is not ready - the RDY signal is also forced to 0.
input [15:0] DMC_Addr;
input [15:0] CPU_Addr;
output [15:0] Addr;
output RDY_tocore;
output SPR_PPU; // A constant address value is set for writing to the PPU register $2004
wire SPRDmaEnd; // End DMA execution ("End")
wire SPRDmaStep; // Increment the low-order part of the address ("Step")
wire [15:0] SPR_Addr;
wire SPR_CPU; // Memory address to read during sprite DMA
SPRDMA_AddrLowCounter dma_addr_low (
.ACLK1(ACLK1),
.Clear(RES),
.Step(SPRDmaStep),
.Load(W4014),
.EndCount(SPRDmaEnd),
.AddrLow(SPR_Addr[7:0]) );
SPRDMA_AddrHigh dma_addr_high (
.ACLK1(ACLK1),
.SetAddr(W4014),
.DB(DB),
.AddrHigh(SPR_Addr[15:8]) );
SPRDMA_Control sprdma_ctl (
.PHI1(PHI1),
.RnW(RnW),
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.W4014(W4014),
.RUNDMC(RUNDMC),
.DMCReady(DMCRDY),
.SPRE(SPRDmaEnd),
.SPRS(SPRDmaStep),
.RDY(RDY_tocore),
.SPR_PPU(SPR_PPU),
.SPR_CPU(SPR_CPU) );
Address_MUX addr_mux (
.SPR_CPU(SPR_CPU),
.SPR_PPU(SPR_PPU),
.n_DMCAB(n_DMCAB),
.DMC_Addr(DMC_Addr),
.SPR_Addr(SPR_Addr),
.CPU_Addr(CPU_Addr),
.AddrOut(Addr) );
endmodule // Sprite_DMA |
module SPRDMA_AddrLowCounter(ACLK1, Clear, Step, Load, EndCount, AddrLow);
input ACLK1;
input Clear;
input Step;
input Load;
output EndCount;
output [7:0] AddrLow;
wire [7:0] cc; // Carry chain
CounterBit cnt [7:0] (
.ACLK1(ACLK1),
.clear(Clear),
.step(Step),
.load(Load),
.cin({cc[6:0], 1'b1}),
.d(8'h00),
.q(AddrLow),
.cout(cc) );
assign EndCount = cc[7];
endmodule // SPRDMA_AddrLowCounter |
module SPRDMA_AddrHigh(ACLK1, SetAddr, DB, AddrHigh);
input ACLK1;
input SetAddr;
inout [7:0] DB;
output [7:0] AddrHigh;
RegisterBit val_hi [7:0] (
.d(DB),
.ena(SetAddr),
.ACLK1(ACLK1),
.q(AddrHigh) );
endmodule // SPRDMA_AddrHigh |
module SPRDMA_Control(PHI1, RnW, ACLK1, nACLK2, RES, W4014, RUNDMC, DMCReady, SPRE, SPRS, RDY, SPR_PPU, SPR_CPU);
input PHI1;
input RnW;
input ACLK1;
input nACLK2;
input RES;
input W4014;
input RUNDMC;
input DMCReady;
input SPRE;
output SPRS;
output RDY;
output SPR_PPU; // DMA Buffer -> PPU
output SPR_CPU; // RAM -> DMA Buffer
wire ACLK2 = ~ACLK2;
wire NOSPR;
wire DOSPR;
wire spre_out;
wire dospr_out;
wire StopDma;
wire StartDma;
wire n_StartDma;
wire toggle;
nor (SPRS, NOSPR, RUNDMC, ~ACLK2);
dlatch spre_latch (.d(SPRE), .en(ACLK1), .q(spre_out) );
dlatch nospr_latch (.d(StopDma), .en(ACLK1), .nq(NOSPR) );
dlatch dospr_latch (.d(n_StartDma), .en(ACLK2), .q(dospr_out) );
rsff_2_3 StopDMA (.res1(SPRS & spre_out), .res2(RES), .s(DOSPR), .q(StopDma) );
rsff_2_3 StartDMA (.res1(~NOSPR), .res2(RES), .s(W4014), .q(StartDma), .nq(n_StartDma) );
rsff DMADirToggle (.r(ACLK1), .s(ACLK2), .q(toggle) );
nor(SPR_PPU, NOSPR, RUNDMC, ~toggle);
nor(SPR_CPU, NOSPR, RUNDMC, toggle);
// Ready control
wire sprdma_rdy;
nor (sprdma_rdy, ~NOSPR, StartDma);
assign RDY = sprdma_rdy & DMCReady; // -> to core
// 6502 read cycle detect
wire read_cyc;
nand (read_cyc, ~PHI1, RnW);
nor (DOSPR, dospr_out, read_cyc);
endmodule // SPRDMA_Control |
module Address_MUX(SPR_CPU, SPR_PPU, n_DMCAB, DMC_Addr, SPR_Addr, CPU_Addr, AddrOut);
input SPR_CPU;
input SPR_PPU;
input n_DMCAB;
input [15:0] DMC_Addr;
input [15:0] SPR_Addr;
input [15:0] CPU_Addr;
output [15:0] AddrOut;
wire DMC_AB = ~n_DMCAB;
wire CPU_AB;
nor (CPU_AB, SPR_CPU, SPR_PPU, DMC_AB);
assign AddrOut = SPR_PPU ? 16'h2004 :
(SPR_CPU ? SPR_Addr :
(DMC_AB ? DMC_Addr :
(CPU_AB ? CPU_Addr : 16'hzzzz) ) );
endmodule // Address_MUX |
module DMABuffer(PHI2, SPR_PPU, DB, RnW_fromcore, RW_topad, n_R4015, n_DBGRD, WR_topad, RD_topad);
input PHI2;
input SPR_PPU;
inout [7:0] DB;
input RnW_fromcore;
output RW_topad;
input n_R4015;
input n_DBGRD;
output WR_topad;
output RD_topad;
wire PPU_SPR;
assign PPU_SPR = ~SPR_PPU;
nor (RW_topad, ~RnW_fromcore, SPR_PPU);
assign RD_topad = RW_topad;
nand (WR_topad, n_R4015, n_DBGRD, RW_topad);
wire [7:0] spr_buf_out;
dlatch spr_buf [7:0] (
.d(DB),
.en(PHI2),
.nq(spr_buf_out) );
bustris spr_tris [7:0] (
.a(spr_buf_out),
.n_x(DB),
.n_en(PPU_SPR) );
endmodule // DMABuffer |
module aoi (a0, a1, b, x);
input a0;
input a1;
input b;
output x;
nor (x, a0 & a1, b);
endmodule // aoi |
module aoi211 (a0, a1, b, c, x);
input a0;
input a1;
input b;
input c;
output x;
nor (x, a0 & a1, b, c);
endmodule // aoi |
module rsff (r, s, q, nq);
input r; // 1: Reset value (0)
input s; // 1: Set value (1)
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg val;
always @(r or s) begin
if (r)
val <= 1'b0;
else if (s)
val <= 1'b1;
end
assign q = val;
assign nq = ~val;
initial val <= 1'b0;
`else
wire nor1_out;
wire nor2_out;
nor (nor1_out, r, nor2_out);
nor (nor2_out, s, nor1_out);
assign q = nor1_out;
assign nq = nor2_out;
`endif
endmodule // rsff |
module rsff_2_3 (res1, res2, s, q, nq);
input res1; // 1: Reset1 value (0)
input res2; // 1: Reset2 value (0)
input s; // 1: Set value (1)
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg val;
always @(*) begin
if (res1 | res2)
val <= 1'b0;
else if (s)
val <= 1'b1;
end
assign q = val;
assign nq = ~val;
initial val <= 1'b0;
`else
wire nor1_out;
wire nor2_out;
nor (nor1_out, res1, res2, nor2_out);
nor (nor2_out, s, nor1_out);
assign q = nor1_out;
assign nq = nor2_out;
`endif
endmodule // rsff_2_3 |
module oai (a0, a1, b, x);
input a0;
input a1;
input b;
output x;
nand (x, a0 | a1, b);
endmodule // oai |
module sdffr (d, res, phi_keep, q, nq);
input d; // Input value for write
input res; // 1: Reset
input phi_keep; // 1: Keep the current value, 0: You can write, the old value is "cut off"
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg val;
always @(*) begin
if (!phi_keep)
val <= d;
if (res)
val <= 1'b0;
end
assign q = val;
assign nq = ~val;
initial val <= 1'b0;
`else
(* keep = "true" *) wire muxout;
assign muxout = phi_keep ? oldval : d;
(* keep = "true" *) wire n_oldval;
assign n_oldval = ~muxout;
(* keep = "true" *) wire oldval;
nor (oldval, n_oldval, res);
assign q = oldval;
assign nq = n_oldval;
`endif
endmodule // sdffr |
module sdffre(d, en, res, phi_keep, q, nq);
input d; // Input value for write
input en; // 1: Enables Write
input res; // 1: Reset
input phi_keep; // 1: Keep the current value, 0: You can write, the old value is "cut off"
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg val;
always @(*) begin
if (en & !phi_keep)
val <= d;
if (res)
val <= 1'b0;
end
assign q = val;
assign nq = ~val;
initial val <= 1'b0;
`else
(* keep = "true" *) wire dval;
bufif1 (dval, d, en);
(* keep = "true" *) wire muxout;
assign muxout = phi_keep ? oldval : dval;
(* keep = "true" *) wire n_oldval;
assign n_oldval = ~muxout;
(* keep = "true" *) wire oldval;
nor (oldval, n_oldval, res);
assign q = oldval;
assign nq = n_oldval;
`endif
endmodule // sdffre |
module dlatch (d, en, q, nq);
input d; // Input value
input en; // 1: Allow write
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg dout;
always @(d or en) begin
if (en == 1'b1 && (d == 1'b0 || d == 1'b1))
dout <= d; // Use non-blocking
end
assign q = dout;
assign nq = ~dout;
initial dout <= 1'b0;
`elsif QUARTUS
LATCH MyLatch (.d(d), .ena(en), .q(q), .nq(nq));
`else
(* keep = "true" *) wire floater;
bufif1(floater, d, en);
buf (q, floater);
not (nq, floater);
`endif
endmodule // dlatch |
module pnor (a0, a1, x);
input a0;
input a1;
output x;
nor (x, a0, a1);
endmodule // pnor |
module sdff (d, phi_keep, q, nq);
input d; // Input value for write
input phi_keep; // 1: Keep the current value, 0: You can write, the old value is "cut off"
output q; // Current value
output nq; // Current value (complement)
`ifdef ICARUS
reg val;
always @(*) begin
if (!phi_keep)
val <= d;
end
assign q = val;
assign nq = ~val;
initial val <= 1'b0;
`else
(* keep = "true" *) wire muxout;
assign muxout = phi_keep ? oldval : d;
(* keep = "true" *) wire n_oldval;
assign n_oldval = ~muxout;
(* keep = "true" *) wire oldval;
assign oldval = ~n_oldval;
assign q = oldval;
assign nq = n_oldval;
`endif
endmodule // sdff |
module bustris (a, n_x, n_en);
input a;
output n_x;
input n_en;
notif0 (n_x, a, n_en);
endmodule // bustris |
module TestNmosDesign(
dlatch_d, dlatch_en, dlatch_q, dlatch_nq,
sdffe_d, sdffe_en, sdffe_phi_keep, sdffe_q, sdffe_nq,
sdffre_d, sdffre_en, sdffre_res, sdffre_phi_keep, sdffre_q, sdffre_nq,
bustris_a, bustris_n_x, bustris_n_en,
rsff_r, rsff_s, rsff_q, rsff_nq );
input dlatch_d;
input dlatch_en;
output dlatch_q;
output dlatch_nq;
input sdffe_d;
input sdffe_en;
input sdffe_phi_keep;
output sdffe_q;
output sdffe_nq;
input sdffre_d;
input sdffre_en;
input sdffre_res;
input sdffre_phi_keep;
output sdffre_q;
output sdffre_nq;
input bustris_a;
output bustris_n_x;
input bustris_n_en;
input rsff_r;
input rsff_s;
output rsff_q;
output rsff_nq;
dlatch c2 (
.d(dlatch_d),
.en(dlatch_en),
.q(dlatch_q),
.nq(dlatch_nq) );
sdffe c3 (
.d(sdffe_d),
.en(sdffe_en),
.phi_keep(sdffe_phi_keep),
.q(sdffe_q),
.nq(sdffe_nq) );
sdffre c4 (
.d(sdffre_d),
.en(sdffre_en),
.res(sdffre_res),
.phi_keep(sdffre_phi_keep),
.q(sdffre_q),
.nq(sdffre_nq) );
bustris c5 (
.a(bustris_a),
.n_x(bustris_n_x),
.n_en(bustris_n_en) );
rsff c6 (
.r(rsff_r),
.s(rsff_s),
.q(rsff_q),
.nq(rsff_nq) );
endmodule // TestNmosDesign |
module BusMux (PHI2, SB, DB, ADL, ADH, Z_ADL0, Z_ADL1, Z_ADL2, Z_ADH0, Z_ADH17, SB_DB, SB_ADH );
input PHI2;
inout [7:0] SB;
inout [7:0] DB;
inout [7:0] ADL;
inout [7:0] ADH;
input Z_ADL0;
input Z_ADL1;
input Z_ADL2;
input Z_ADH0;
input Z_ADH17;
input SB_DB;
input SB_ADH;
BusPrecharge precharge (
.PHI2(PHI2),
.SB(SB),
.DB(DB),
.ADL(ADL),
.ADH(ADH) );
ConstGen constgen (
.ADL(ADL),
.ADH(ADH),
.Z_ADL0(Z_ADL0),
.Z_ADL1(Z_ADL1),
.Z_ADL2(Z_ADL2),
.Z_ADH0(Z_ADH0),
.Z_ADH17(Z_ADH17) );
BusVsBus busbus (
.SB(SB),
.DB(DB),
.ADH(ADH),
.SB_DB(SB_DB),
.SB_ADH(SB_ADH) );
endmodule // BusMux |
module BusPrecharge (PHI2, SB, DB, ADL, ADH );
input PHI2;
inout [7:0] SB;
inout [7:0] DB;
inout [7:0] ADL;
inout [7:0] ADH;
assign SB = PHI2 ? 8'b11111111 : 8'bzzzzzzzz;
assign DB = PHI2 ? 8'b11111111 : 8'bzzzzzzzz;
assign ADL = PHI2 ? 8'b11111111 : 8'bzzzzzzzz;
assign ADH = PHI2 ? 8'b11111111 : 8'bzzzzzzzz;
endmodule // BusPrecharge |
module ConstGen (ADL, ADH, Z_ADL0, Z_ADL1, Z_ADL2, Z_ADH0, Z_ADH17);
inout [7:0] ADL;
inout [7:0] ADH;
input Z_ADL0;
input Z_ADL1;
input Z_ADL2;
input Z_ADH0;
input Z_ADH17;
assign ADL[0] = Z_ADL0 ? 1'b0 : 1'bz;
assign ADL[1] = Z_ADL1 ? 1'b0 : 1'bz;
assign ADL[2] = Z_ADL2 ? 1'b0 : 1'bz;
assign ADH[0] = Z_ADH0 ? 1'b0 : 1'bz;
assign ADH[7:1] = Z_ADH17 ? 7'b0000000 : 7'bzzzzzzz;
endmodule // ConstGen |
module BusVsBus (SB, DB, ADH, SB_DB, SB_ADH);
inout [7:0] SB;
inout [7:0] DB;
inout [7:0] ADH;
input SB_DB;
input SB_ADH;
tranif1 sb_db [7:0] (SB, DB, {8{SB_DB}});
tranif1 sb_adh [7:0] (SB, ADH, {8{SB_ADH}});
endmodule // BusVsBus |
module Flags_Control (
PHI2, X,
T7, ZTST, n_ready, SR,
P_DB, IR5_I, IR5_C, IR5_D, Z_V, ACR_C, DBZ_Z, DB_N, DB_P, DB_C, DB_V);
input PHI2;
input [129:0] X;
input T7;
input ZTST;
input n_ready;
input SR;
output P_DB;
output IR5_I;
output IR5_C;
output IR5_D;
output Z_V;
output ACR_C;
output DBZ_Z;
output DB_N;
output DB_P;
output DB_C;
output DB_V;
wire dbz_latch_q;
wire dbn_latch_q;
wire pin_latch_q;
wire bit_latch_q;
wire nARITH;
assign nARITH = ~((X[107] & T7) | X[112] | X[116] | X[117] | X[118] | X[119]);
dlatch pdb_latch (.d(~(X[98]|X[99])), .en(PHI2), .nq(P_DB));
dlatch iri_latch (.d(~X[108]), .en(PHI2), .nq(IR5_I));
dlatch irc_latch (.d(~X[110]), .en(PHI2), .nq(IR5_C));
dlatch ird_latch (.d(~X[120]), .en(PHI2), .nq(IR5_D));
dlatch zv_latch (.d(~X[127]), .en(PHI2), .nq(Z_V));
dlatch acrc_latch (.d(nARITH), .en(PHI2), .nq(ACR_C));
dlatch dbz_latch (.d(~(ACR_C|ZTST|X[109])), .en(PHI2), .q(dbz_latch_q), .nq(DBZ_Z));
dlatch dbn_latch (.d(X[109]), .en(PHI2), .q(dbn_latch_q));
dlatch dbc_latch (.d(~(SR|DB_P)), .en(PHI2), .nq(DB_C));
dlatch pin_latch (.d(~(X[114]|X[115])), .en(PHI2), .q(pin_latch_q));
dlatch bit_latch (.d(~X[113]), .en(PHI2), .q(bit_latch_q));
assign DB_N = ~((dbz_latch_q&pin_latch_q) | dbn_latch_q);
assign DB_P = ~(pin_latch_q | n_ready);
assign DB_V = ~(pin_latch_q & bit_latch_q);
endmodule // Flags_Control |
module DataBusBit (
PHI1, PHI2,
ADL, ADH, DB, DB_Ext,
DL_ADL, DL_ADH, DL_DB,
RD);
input PHI1;
input PHI2;
inout ADL;
inout ADH;
inout DB;
inout DB_Ext;
input DL_ADL;
input DL_ADH;
input DL_DB;
input RD;
dlatch transp_latch (.d(DB_Ext), .en(1'b1), .nq(transp_latch_nq) );
wire transp_latch_nq;
dlatch dir_latch (.d(transp_latch_nq), .en(PHI2), .nq(dir_latch_nq) );
wire dir_latch_nq;
wire dir_val;
assign dir_val = PHI1 ? dir_latch_nq : 1'bz;
assign ADL = DL_ADL ? dir_val : 1'bz;
assign ADH = DL_ADH ? dir_val : 1'bz;
assign DB = DL_DB ? dir_val : 1'bz;
dlatch int_db_latch (.d(DB), .en(1'b1), .nq(int_db_latch_nq) );
wire int_db_latch_nq;
dlatch dor_latch (.d(int_db_latch_nq), .en(PHI1), .nq(dor_latch_nq) );
wire dor_latch_nq;
bufif0 (DB_Ext, dor_latch_nq, RD);
endmodule // DataBusBit |
module WRLatch (PHI1, PHI2, WR, RD);
input PHI1;
input PHI2;
input WR;
output RD;
dlatch wr_latch (.d(WR), .en(PHI1), .nq(wr_latch_nq) );
wire wr_latch_nq;
wire tmp1;
nor (tmp1, ~PHI2, wr_latch_nq);
not (RD, tmp1);
endmodule // WRLatch |
module IR (
PHI1, PHI2,
n_PD, FETCH,
IR01, IR_out, n_IR_out);
input PHI1;
input PHI2;
input [7:0] n_PD;
input FETCH;
output IR01;
output [7:0] IR_out;
output [7:0] n_IR_out;
wire ena;
and (ena, FETCH, PHI1);
dlatch ir [7:0] (.d(n_PD), .en(ena), .q(n_IR_out), .nq(IR_out));
or (IR01, IR_out[0], IR_out[1]);
endmodule // IR |
module AddrBusBit (
PHI1, PHI2,
ADX, ADX_ABX,
ABus_out);
input PHI1;
input PHI2;
input ADX;
input ADX_ABX;
output ABus_out;
wire n_adx = ~(ADX);
wire abff_out;
AddrBusFF abff (
.phi_load(PHI1),
.phi_keep(PHI2),
.en(ADX_ABX),
.val(n_adx),
.q(abff_out));
assign ABus_out = ~abff_out;
endmodule // AddrBusBit |
module AddrBusFF (phi_load, phi_keep, en, val, q, nq);
input phi_load; // PHI phase during which the FF value can be modified
input phi_keep; // PHI phase during which the current value is "holding".
input en; // 1: Writing a value is enabled
input val; // New value
output q; // Current value
output nq; // Current value (complement)
(* keep = "true" *) wire inp;
not (inp, val);
(* keep = "true" *) wire not1out;
not(not1out, floater);
(* keep = "true" *) wire not2out;
not(not2out, not1out);
(* keep = "true" *) wire floater;
bufif1(floater, not2out, phi_keep);
(* keep = "true" *) wire mid;
bufif1(mid, inp, phi_load);
bufif1(floater, mid, en);
assign q = ~not2out;
assign nq = not2out;
endmodule // AddrBusFF |
module ExtraCounter (
PHI1, PHI2, TRES2, n_ready, T1,
n_T2, n_T3, n_T4, n_T5);
input PHI1;
input PHI2;
input TRES2;
input n_ready;
input T1;
output n_T2;
output n_T3;
output n_T4;
output n_T5;
wire t1_latch_nq;
wire [3:0] nq;
dlatch t1_latch (.d(T1), .en(PHI2), .nq(t1_latch_nq));
ExtraCounter_SRBit sr [3:0] (
.PHI1(PHI1),
.PHI2(PHI2),
.nd({nq[2:0],t1_latch_nq}),
.n_EN(n_ready),
.RES(TRES2),
.nq(nq),
.nsout({n_T5,n_T4,n_T3,n_T2}));
endmodule // ExtraCounter |
module ExtraCounter_SRBit (PHI1, PHI2, nd, n_EN, RES, nq, nsout);
input PHI1;
input PHI2;
input nd;
input n_EN;
input RES;
output nq;
output nsout;
wire latch1_q;
wire latch2_d;
nor (latch2_d, latch1_q, RES);
dlatch latch1 (.d(n_EN ? nq : nd), .en(PHI1), .q(latch1_q));
dlatch latch2 (.d(latch2_d), .en(PHI2), .nq(nq));
assign nsout = ~latch2_d;
endmodule // ExtraCounter_SRBit |
module PreDecode (
PHI2,
Z_IR,
Data_bus, n_PD,
n_IMPLIED, n_TWOCYCLE);
input PHI2;
input Z_IR;
inout [7:0] Data_bus;
output [7:0] n_PD;
output n_IMPLIED;
output n_TWOCYCLE;
// Implementation
wire [7:0] PD;
wire [7:0] transp_latch_nq;
wire [7:0] PD_latch_q;
wire implied;
wire tmp1;
wire tmp2;
wire tmp3;
dlatch transp_latch [7:0] (.d(Data_bus), .en(1'b1), .nq(transp_latch_nq));
dlatch PD_latch [7:0] (.d(transp_latch_nq), .en(PHI2), .q(PD_latch_q));
pnor pd_nors [7:0] (.a0(PD_latch_q), .a1(Z_IR), .x(PD));
assign n_PD = ~PD;
nor (implied, PD[0], PD[2], n_PD[3]);
nor (tmp1, PD[1], PD[4], PD[7]);
nor (tmp2, n_PD[0], PD[2], n_PD[3], PD[4]);
nor (tmp3, PD[0], PD[2], PD[3], PD[4], n_PD[7]);
assign n_IMPLIED = ~implied;
assign n_TWOCYCLE = ~((implied&~tmp1)|tmp2|tmp3);
endmodule // PreDecode |
module Bus_Control (
PHI1, PHI2,
n_SBXY, AND, STOR, Z_ADL0, ACRL2, DL_PCH, n_ready, INC_SB, BRK6E, STXY, n_PCH_PCH,
T0, T1, T6, T7, BR0,
X,
ZTST, PGX,
Z_ADH0, Z_ADH17, SB_AC, ADL_ABL, AC_SB, SB_DB, AC_DB, SB_ADH, DL_ADH, DL_ADL, ADH_ABH, DL_DB);
input PHI1;
input PHI2;
input n_SBXY;
input AND;
input STOR;
input Z_ADL0;
input ACRL2;
input DL_PCH;
input n_ready;
input INC_SB;
input BRK6E;
input STXY;
input n_PCH_PCH;
input T0;
input T1;
input T6;
input T7;
input BR0;
input [129:0] X;
output ZTST;
output PGX;
output Z_ADH0;
output Z_ADH17;
output SB_AC;
output ADL_ABL;
output AC_SB;
output SB_DB;
output AC_DB;
output SB_ADH;
output DL_ADH;
output DL_ADL;
output ADH_ABH;
output DL_DB;
wire nready_latch_nq;
wire sb_ac_latch_q;
wire ac_sb_latch_q;
wire ac_db_latch_q;
wire nDLADL;
nor (nDLADL, X[81], X[82]);
wire nSBAC;
nor (nSBAC, X[58], X[59], X[60], X[61], X[62], X[63], X[64]);
wire temp1;
nand (temp1, T6, X[55]);
wire temp2;
nor (temp2, nZTST, AND);
wire nSBDB;
nor (nSBDB, ~temp1, temp2, X[67], T1, BR2, JSXY);
wire JSXY;
wire JSR2;
assign JSR2 = X[48];
nand (JSXY, ~JSR2, STXY);
wire JMP4;
assign JMP4 = X[101];
wire JSR5;
assign JSR5 = X[56];
wire nZADH17;
nor (nZADH17, X[57], ~nDLADL);
wire nIND;
wire RTS5;
assign RTS5 = X[84];
wire pp;
assign pp = X[129];
nor (nIND, X[89], (X[90] & ~pp), X[91], RTS5);
wire ABS2;
assign ABS2 = X[83] & ~pp;
wire nABS2_T0;
nor (nABS2_T0, ABS2, T0);
wire temp11;
wire IMPLIED;
assign IMPLIED = X[128] & ~pp;
nor (temp11, nABS2_T0, IMPLIED);
wire nDLDB;
nor (nDLDB, BR2, temp11, ~temp5, JMP4, T6);
wire temp5;
nor (temp5, INC_SB, X[45], BRK6E, X[46], X[47], JSR2);
wire nSBADH;
nor (nSBADH, PGX, BR3);
wire nr;
nand (nr, ACRL2, nready_latch_nq);
wire SBA;
nor (SBA, nSBADH, nr);
wire temp3;
nor (temp3, IND, T2, n_PCH_PCH, JSR5);
wire temp4;
nor (temp4, n_ready, temp3);
wire temp6;
or (temp6, SBA, temp5);
wire temp7;
assign temp7 = temp6 & ~BR3;
wire nADHABH;
nor (nADHABH, Z_ADL0, temp7);
wire nDLADH;
nor (nDLADH, DL_PCH, IND);
wire nACDB;
wire STA;
assign STA = X[79];
nor (nACDB, X[74], STA & STOR);
wire nACSB;
nor (nACSB, X[65] & ~X[64], X[66], X[67], X[68], AND);
wire temp8;
nor (temp8, X[71], X[72]);
nand (PGX, temp8, ~BR0);
wire temp9;
nor (temp9, ~temp8, n_ready);
wire nRMW;
nor (nRMW, T6, T7);
wire nADLABL;
nand (nADLABL, nRMW, temp9);
nor (nZTST, n_SBXY, ~nSBAC, T7, AND);
dlatch nready_latch (.d(n_ready), .en(PHI1), .nq(nready_latch_nq) );
dlatch z_adh0_latch (.d(nDLADL), .en(PHI2), .nq(Z_ADH0) );
dlatch z_adh17_latch (.d(nZADH17), .en(PHI2), .nq(Z_ADH17) );
dlatch sb_ac_latch (.d(nSBAC), .en(PHI2), .q(sb_ac_latch_q) );
dlatch adl_abl_latch (.d(nADLABL), .en(PHI2), .nq(ADL_ABL) );
dlatch ac_sb_latch (.d(nACSB), .en(PHI2), .q(ac_sb_latch_q) );
dlatch sb_db_latch (.d(nSBDB), .en(PHI2), .nq(SB_DB) );
dlatch ac_db_latch (.d(nACDB), .en(PHI2), .q(ac_db_latch_q) );
dlatch sb_adh_latch (.d(nSBADH), .en(PHI2), .nq(SB_ADH) );
dlatch dl_adh_latch (.d(nDLADH), .en(PHI2), .nq(DL_ADH) );
dlatch dl_adl_latch (.d(nDLADL), .en(PHI2), .nq(DL_ADL) );
dlatch adh_abh_latch (.d(nADHABH), .en(PHI2), .nq(ADH_ABH) );
dlatch dl_db_latch (.d(nDLDB), .en(PHI2), .nq(DL_DB) );
nor (SB_AC, sb_ac_latch_q, PHI2);
nor (AC_SB, ac_sb_latch_q, PHI2);
nor (AC_DB, ac_db_latch_q, PHI2);
assign ZTST = ~nZTST;
endmodule // Bus_Control |
module BRKProcessing (
PHI1, PHI2,
BRK5, n_ready, RESP, n_NMIP, BR2, T0, n_IRQP, n_IOUT,
BRK6E, BRK7, BRK5_RDY, DORES, n_DONMI, B_OUT);
input PHI1;
input PHI2;
input BRK5;
input n_ready;
input RESP;
input n_NMIP;
input BR2;
input T0;
input n_IRQP;
input n_IOUT;
output BRK6E;
output BRK7;
output BRK5_RDY;
output DORES;
output n_DONMI;
output B_OUT;
// BRK sequence cycles 6-7
wire BRK5_RDY;
and (BRK5_RDY, BRK5, ~n_ready);
dlatch brk5_latch (.d(BRK5_RDY), .en(PHI2), .q(brk5_latch_q) );
wire brk5_latch_q;
wire tmp2;
nand (tmp2, n_ready, brk6_latch1_nq);
wire brk6_latch1_d;
and (brk6_latch1_d, ~brk5_latch_q, tmp2);
dlatch brk6_latch1 (.d(brk6_latch1_d), .en(PHI1), .nq(brk6_latch1_nq) );
wire brk6_latch1_nq;
dlatch brk6_latch2 (.d(brk6_latch1_nq), .en(PHI2), .nq(brk6_latch2) );
wire brk6_latch2_nq;
nor (BRK6E, brk6_latch2_nq, n_ready);
nor (BRK7, brk6_latch1_nq, BRK5_RDY);
// Reset FF
wire nDORES;
nor (nDORES, res_latch1_q, res_latch2_q);
dlatch res_latch1 (.d(RESP), .en(PHI2), .q(res_latch1_q) );
wire res_latch1_q;
wire res_latch2_d;
nor (res_latch2_d, nDORES, BRK6E);
dlatch res_latch2 (.d(res_latch2_d), .en(PHI1), .q(res_latch2_q) );
wire res_latch2_q;
not (DORES, nDORES);
// NMI Edge Detect
wire tmp1;
nor (tmp1, ff2_latch_q, delay_latch2_q);
wire ff2_latch_d;
nor (ff2_latch_d, nmip_latch_q, tmp1);
dlatch brk7_latch (.d(BRK7), .en(PHI2), .nq(brk7_latch_nq) );
wire brk7_latch_nq;
wire donmi_latch_d;
nor (donmi_latch_d, brk7_latch_nq, n_NMIP, ff2_latch_d);
dlatch donmi_latch (.d(donmi_latch_d), .en(PHI1), .q(donmi_latch_q) );
wire donmi_latch_q;
dlatch nmip_latch (.d(n_NMIP), .en(PHI1), .q(nmip_latch_q) );
wire nmip_latch_q;
dlatch ff2_latch (.d(ff2_latch_d), .en(PHI2), .q(ff2_latch_q) );
wire ff2_latch_q;
dlatch delay_latch1 (.d(n_DONMI), .en(PHI2), .nq(delay_latch1_nq) );
wire delay_latch1_nq;
dlatch delay_latch2 (.d(delay_latch1_nq), .en(PHI1), .q(delay_latch2_q) );
wire delay_latch2_q;
dlatch ff1_latch (.d(n_DONMI), .en(PHI2), .q(ff1_latch_q) );
wire ff1_latch_q;
dlatch brk6e_latch (.d(BRK6E), .en(PHI1), .q(brk6e_latch_q) );
wire brk6e_latch_q;
wire nmitmp1;
nor (nmitmp1, ff1_latch_q, brk6e_latch_q);
nor (n_DONMI, donmi_latch_q, nmitmp1);
// Interrupt Check
wire intr = ~( (BR2|T0) & (~((n_IRQP|~n_IOUT)&n_DONMI)) );
wire b_latch2_d;
nor (b_latch2_d, b_latch1_q, BRK6E);
dlatch b_latch2 (.d(b_latch2_d), .en(PHI1), .q(b_latch2_q) );
wire b_latch2_q;
wire b_latch1_d;
and (b_latch1_d, intr, ~b_latch2_q);
dlatch b_latch1 (.d(b_latch1_d), .en(PHI2), .q(b_latch1_q) );
wire b_latch1_q;
nor (B_OUT, DORES, b_latch2_d);
endmodule // BRKProcessing |
module IntVector (
PHI2, BRK5_RDY, BRK7, DORES, n_DONMI,
Z_ADL0, Z_ADL1, Z_ADL2);
input PHI2;
input BRK5_RDY;
input BRK7;
input DORES;
input n_DONMI;
output Z_ADL0;
output Z_ADL1;
output Z_ADL2;
dlatch zadl0_latch (.d(~BRK5_RDY), .en(PHI2), .nq(Z_ADL0) );
wire tmp1;
nor (tmp1, BRK7, ~DORES);
dlatch zadl1_latch (.d(~tmp1), .en(PHI2), .nq(Z_ADL1) );
wire zadl2_latch_d;
nor (zadl2_latch_d, BRK7, DORES, n_DONMI);
dlatch zadl2_latch (.d(zadl2_latch_d), .en(PHI2), .nq(zadl2_latch_nq) );
wire zadl2_latch_nq;
not (Z_ADL2, zadl2_latch_nq);
endmodule // IntVector |
module ClkGen (PHI0, PHI1, PHI2, PHI1_topad, PHI2_topad);
input PHI0;
output PHI1;
output PHI2;
output PHI1_topad;
output PHI2_topad;
Phi1Gen phi1_tocore (.PHI0(PHI0), .PHI1(PHI1) );
Phi2Gen phi2_tocore (.PHI0(PHI0), .PHI1(PHI1), .PHI2(PHI2) );
Phi1Gen phi1_topad (.PHI0(PHI0), .PHI1(PHI1_topad) );
Phi2Gen phi2_topad (.PHI0(PHI0), .PHI1(PHI1_topad), .PHI2(PHI2_topad) );
endmodule // ClkGen |
module Phi1Gen (PHI0, PHI1);
input PHI0;
output PHI1;
assign PHI1 = ~(~(~PHI0));
endmodule // Phi1Gen |
module Phi2Gen (PHI0, PHI1, PHI2);
input PHI0;
input PHI1;
output PHI2;
wire tmp1;
wire tmp2;
assign tmp1 = ~PHI0 | PHI1;
assign tmp2 = ~PHI0 & tmp1;
assign PHI2 = ~(tmp2 ? tmp2 : tmp1);
endmodule // Phi2Gen |
module PadsLogic (
PHI1, PHI2,
n_NMI, n_IRQ, n_RES, n_NMIP, n_IRQP, RESP,
RDY, RDY_frompad, n_PRDY,
T1_topad, SYNC, SO, SO_frompad,
WR_topad, RnW);
input PHI1;
input PHI2;
input n_NMI;
input n_IRQ;
input n_RES;
output n_NMIP;
output n_IRQP;
output RESP;
input RDY;
output RDY_frompad;
output n_PRDY;
input T1_topad;
output SYNC;
input SO;
output SO_frompad;
input WR_topad;
output RnW;
// Implementation of logic that is located around terminals (pads)
// Interrupt pads
// Input inverters can act as transparent latches (since the values of external interrupt signals can be `Z`),
// but there's probably no point in doing that, they usually put pull-ups on the outside for them anyway.
wire nmip_ff_q;
int_ff nmip_ff (.PHI2(PHI2), .d(~n_NMI), .q(nmip_ff_q));
assign n_NMIP = ~nmip_ff_q;
wire irqp_ff_q;
int_ff irqp_ff (.PHI2(PHI2), .d(~n_IRQ), .q(irqp_ff_q));
dlatch irqp_latch (.d(irqp_ff_q), .en(PHI1), .nq(n_IRQP));
wire resp_ff_nq; // !!!
int_ff resp_ff (.PHI2(PHI2), .d(~n_RES), .nq(resp_ff_nq));
dlatch resp_latch (.d(resp_ff_nq), .en(PHI1), .nq(RESP));
// Others
assign RDY_frompad = RDY;
wire prdy_latch1_nq;
dlatch prdy_latch1 (.d(~RDY), .en(PHI2), .nq(prdy_latch1_nq));
dlatch prdy_latch2 (.d(prdy_latch1_nq), .en(PHI1), .nq(n_PRDY));
buf (SYNC, T1_topad);
wire so_latch1_nq;
wire so_latch2_nq;
wire so_latch3_q;
dlatch so_latch1 (.d(~SO), .en(PHI1), .nq(so_latch1_nq));
dlatch so_latch2 (.d(so_latch1_nq), .en(PHI2), .nq(so_latch2_nq));
dlatch so_latch3 (.d(so_latch2_nq), .en(PHI1), .q(so_latch3_q));
nor (SO_frompad, so_latch3_q, so_latch1_nq);
dlatch rw_latch (.d(WR_topad), .en(PHI1), .nq(RnW));
endmodule // PadsLogic |
module int_ff (PHI2, d, q, nq);
input PHI2; // 1: enable (level-triggered)
input d;
output q;
output nq;
// Cycle of two AOI-21s
wire g0_out;
wire g1_out;
aoi g0 (.a0(~d), .a1(PHI2), .b(g1_out), .x(g0_out));
aoi g1 (.a0(d), .a1(PHI2), .b(g0_out), .x(g1_out));
assign q = g0_out;
assign nq = g1_out;
endmodule // int_ff |
module PC (
PHI2,
n_IPC,
ADL_PCL, PCL_PCL, PCL_ADL, PCL_DB, ADH_PCH, PCH_PCH, PCH_ADH, PCH_DB,
ADL, ADH, DB);
input PHI2;
input n_IPC;
input ADL_PCL;
input PCL_PCL;
input PCL_ADL;
input PCL_DB;
input ADH_PCH;
input PCH_PCH;
input PCH_ADH;
input PCH_DB;
inout [7:0] ADL;
inout [7:0] ADH;
inout [7:0] DB;
wire [7:0] pcl_nout;
wire [3:0] pch_nout;
wire [7:1] pclc;
wire [7:1] pchc;
wire PCLC;
nor (PCLC, n_IPC, pcl_nout[0], pcl_nout[1], pcl_nout[2], pcl_nout[3], pcl_nout[4], pcl_nout[5], pcl_nout[6], pcl_nout[7] );
wire PCHC;
nor (PCHC, ~PCLC, pch_nout[0], pch_nout[1], pch_nout[2], pch_nout[3] );
// PCL
pc_notcarry pcl0 (.pc(pc[0]), .pcs(pcs[0]), .PHI2(PHI2), .n_carry(n_IPC), .AD(ADL[0]), .DB(DB[0]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[0]), .cout(pclc[1]) );
pc_carry pcl1 (.pc(pc[1]), .pcs(pcs[1]), .PHI2(PHI2), .carry(pclc[1]), .AD(ADL[1]), .DB(DB[1]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[1]), .n_cout(pclc[2]) );
pc_notcarry pcl2 (.pc(pc[2]), .pcs(pcs[2]), .PHI2(PHI2), .n_carry(pclc[2]), .AD(ADL[2]), .DB(DB[2]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[2]), .cout(pclc[3]) );
pc_carry pcl3 (.pc(pc[3]), .pcs(pcs[3]), .PHI2(PHI2), .carry(pclc[3]), .AD(ADL[3]), .DB(DB[3]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[3]), .n_cout(pclc[4]) );
pc_notcarry pcl4 (.pc(pc[4]), .pcs(pcs[4]), .PHI2(PHI2), .n_carry(pclc[4]), .AD(ADL[4]), .DB(DB[4]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[4]), .cout(pclc[5]) );
pc_carry pcl5 (.pc(pc[5]), .pcs(pcs[5]), .PHI2(PHI2), .carry(pclc[5]), .AD(ADL[5]), .DB(DB[5]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[5]), .n_cout(pclc[6]) );
pc_notcarry pcl6 (.pc(pc[6]), .pcs(pcs[6]), .PHI2(PHI2), .n_carry(pclc[6]), .AD(ADL[6]), .DB(DB[6]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[6]), .cout(pclc[7]) );
pc_carry pcl7 (.pc(pc[7]), .pcs(pcs[7]), .PHI2(PHI2), .carry(pclc[7]), .AD(ADL[7]), .DB(DB[7]), .PC_AD(PCL_ADL), .PC_DB(PCL_DB), .AD_PC(ADL_PCL), .PC_PC(PCL_PCL), .n_val(pcl_nout[7]) ); // discard output carry, PCLC used instead
// PCH
pc_carry pch0 (.pc(pc[8]), .pcs(pcs[8]), .PHI2(PHI2), .carry(PCLC), .AD(ADH[0]), .DB(DB[0]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_val(pch_nout[0]), .n_cout(pchc[1]) );
pc_notcarry pch1 (.pc(pc[9]), .pcs(pcs[9]), .PHI2(PHI2), .n_carry(pchc[1]), .AD(ADH[1]), .DB(DB[1]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_val(pch_nout[1]), .cout(pchc[2]) );
pc_carry pch2 (.pc(pc[10]), .pcs(pcs[10]), .PHI2(PHI2), .carry(pchc[2]), .AD(ADH[2]), .DB(DB[2]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_val(pch_nout[2]), .n_cout(pchc[3]) );
pc_notcarry pch3 (.pc(pc[11]), .pcs(pcs[11]), .PHI2(PHI2), .n_carry(pchc[3]), .AD(ADH[3]), .DB(DB[3]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_val(pch_nout[3]) ); // discard output carry, PCHC used instead
pc_carry pch4 (.pc(pc[12]), .pcs(pcs[12]), .PHI2(PHI2), .carry(PCHC), .AD(ADH[4]), .DB(DB[4]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_cout(pchc[5]) );
pc_notcarry pch5 (.pc(pc[13]), .pcs(pcs[13]), .PHI2(PHI2), .n_carry(pchc[5]), .AD(ADH[5]), .DB(DB[5]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .cout(pchc[6]) );
pc_carry pch6 (.pc(pc[14]), .pcs(pcs[14]), .PHI2(PHI2), .carry(pchc[6]), .AD(ADH[6]), .DB(DB[6]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH), .n_cout(pchc[7]) );
pc_notcarry pch7 (.pc(pc[15]), .pcs(pcs[15]), .PHI2(PHI2), .n_carry(pchc[7]), .AD(ADH[7]), .DB(DB[7]), .PC_AD(PCH_ADH), .PC_DB(PCH_DB), .AD_PC(ADH_PCH), .PC_PC(PCH_PCH) ); // discard output carry, no need
// Debug
wire IPC; // 1: Incerement PC
not (IPC, n_IPC);
wire [15:0] pc; // PC
wire [15:0] pcs; // PC Shadow aka Select
endmodule // PC |
module pc_notcarry (PHI2, n_carry, AD, DB, PC_AD, PC_DB, AD_PC, PC_PC, n_val, cout, pc, pcs);
input PHI2;
input n_carry;
inout AD;
inout DB;
input PC_AD;
input PC_DB;
input AD_PC;
input PC_PC;
output n_val;
output cout;
output pc; // Not on a real chip
output pcs; // Not on a real chip
wire in_latch_d;
assign #2 in_latch_d = AD_PC ? AD : (PC_PC ? q : 1'bz);
wire out_latch_d;
aoi g1 (.a0(n_val), .a1(n_carry), .b(cout), .x(out_latch_d) );
dlatch in_latch (.d(in_latch_d), .en(1'b1), .nq(n_val) ); // PCLS/PCHS bits
dlatch out_latch (.d(out_latch_d), .en(PHI2), .nq(out_latch_nq) ); // PCL/PCH bits
wire out_latch_nq;
wire q;
not (q, out_latch_nq);
nor (cout, n_val, n_carry);
assign DB = PC_DB ? q : 1'bz;
assign AD = PC_AD ? q : 1'bz;
assign pcs = ~n_val;
assign pc = q;
endmodule // pc_notcarry |
module pc_carry (PHI2, carry, AD, DB, PC_AD, PC_DB, AD_PC, PC_PC, n_val, n_cout, pc, pcs);
input PHI2;
input carry;
inout AD;
inout DB;
input PC_AD;
input PC_DB;
input AD_PC;
input PC_PC;
output n_val;
output n_cout;
output pc; // Not on a real chip
output pcs; // Not on a real chip
wire in_latch_d;
assign #2 in_latch_d = AD_PC ? AD : (PC_PC ? q : 1'bz);
wire out_latch_d;
oai g1 (.a0(val), .a1(carry), .b(n_cout), .x(out_latch_d) );
dlatch in_latch (.d(in_latch_d), .en(1'b1), .nq(n_val) ); // PCLS/PCHS bits
wire val;
not (val, n_val);
dlatch out_latch (.d(out_latch_d), .en(PHI2), .nq(q) ); // PCL/PCH bits
wire q;
nand (n_cout, val, carry);
assign DB = PC_DB ? q : 1'bz;
assign AD = PC_AD ? q : 1'bz;
assign pcs = val;
assign pc = q;
endmodule // pc_carry |
module PC_Control (
PHI1, PHI2,
n_ready, T0, T1, BR0,
X,
PCL_DB, PCH_DB, PC_DB, PCL_ADL, PCH_ADH, PCL_PCL, ADL_PCL, n_ADL_PCL, DL_PCH, ADH_PCH, PCH_PCH, n_PCH_PCH);
input PHI1;
input PHI2;
input n_ready;
input T0;
input T1;
input BR0;
input [129:0] X;
output PCL_DB;
output PCH_DB;
output PC_DB;
output PCL_ADL;
output PCH_ADH;
output PCL_PCL;
output ADL_PCL;
output n_ADL_PCL;
output DL_PCH;
output ADH_PCH;
output PCH_PCH;
output n_PCH_PCH;
wire BR2;
wire BR3;
wire n_PCH_DB;
wire n_PCL_DB;
wire ABS_2;
wire JB;
wire n_PCL_ADL;
wire n_ADL_PCL;
wire n_ADH_PCH;
wire n_T0;
wire t1;
wire t2;
wire t3;
wire nready_latch_q;
wire pch_db_latch1_q;
wire pcl_db_latch1_nq;
wire pcl_pcl_latch_q;
wire adl_pcl_latch_q;
wire adh_pch_latch_q;
wire pch_pch_latch_q;
wire pcl_db_latch1_d;
wire pch_adh_latch_d;
assign BR2 = X[80];
assign BR3 = X[93];
not (n_T0, T0);
nor (t1, JB, nready_latch_q);
nor (t2, t1, n_T0);
nor (n_PCH_DB, X[77], X[78]);
nor (JB, X[94], X[95], X[96]);
assign ABS_2 = X[83] & ~X[129];
nor (n_PCL_ADL, T1, X[56], ABS_2, t2, BR2);
nor (n_ADL_PCL, ~n_PCL_ADL, X[84], T0, BR3 & ~nready_latch_q);
nor (n_ADH_PCH, X[84], ABS_2, T0, T1, BR2, BR3 );
nor (DL_PCH, n_T0, JB);
nor (pcl_db_latch1_d, pch_db_latch1_q, n_ready);
nor (t3, n_PCL_ADL, DL_PCH, BR0);
nor (pch_adh_latch_d, t3, BR3);
nand (PC_DB, n_PCL_DB, n_PCH_DB);
dlatch nready_latch (.d(n_ready), .en(PHI1), .q(nready_latch_q) );
dlatch pcl_db_latch1 (.d(pcl_db_latch1_d), .en(PHI1), .nq(n_PCL_DB) );
dlatch pch_db_latch1 (.d(n_PCH_DB), .en(PHI2), .q(pch_db_latch1_q) );
dlatch pcl_db_latch2 (.d(n_PCL_DB), .en(PHI2), .nq(PCL_DB) );
dlatch pch_db_latch2 (.d(n_PCH_DB), .en(PHI2), .nq(PCH_DB) );
dlatch pcl_adl_latch (.d(n_PCL_ADL), .en(PHI2), .nq(PCL_ADL) );
dlatch pch_adh_latch (.d(pch_adh_latch_d), .en(PHI2), .nq(PCH_ADH) );
dlatch pcl_pcl_latch (.d(~n_ADL_PCL), .en(PHI2), .q(pcl_pcl_latch_q) );
dlatch adl_pcl_latch (.d(n_ADL_PCL), .en(PHI2), .q(adl_pcl_latch_q) );
dlatch adh_pch_latch (.d(n_ADH_PCH), .en(PHI2), .q(adh_pch_latch_q) );
dlatch pch_pch_latch (.d(n_PCH_PCH), .en(PHI2), .q(pch_pch_latch_q) );
nor (PCL_PCL, pcl_pcl_latch_q, PHI2);
nor (ADL_PCL, adl_pcl_latch_q, PHI2);
nor (ADH_PCH, adh_pch_latch_q, PHI2);
nor (PCH_PCH, pch_pch_latch_q, PHI2);
not (n_PCH_PCH, n_ADH_PCH);
endmodule // PC_Control |
module Dispatch (
PHI1, PHI2,
BRK6E, RESP, ACR, DORES, PC_DB, RDY, B_OUT, BRFW, n_BRTAKEN, n_TWOCYCLE, n_IMPLIED, n_ADL_PCL,
X,
ACRL2, T6, T7, TRES2, STOR, Z_IR, FETCH, n_ready, WR, T1, n_T0, T0, n_T1X, n_IPC);
input PHI1;
input PHI2;
input BRK6E;
input RESP;
input ACR;
input DORES;
input PC_DB;
input RDY;
input B_OUT;
input BRFW;
input n_BRTAKEN;
input n_TWOCYCLE;
input n_IMPLIED;
input n_ADL_PCL;
input [129:0] X;
output ACRL2;
output T6;
output T7;
output TRES2;
output STOR;
output Z_IR;
output FETCH;
output n_ready;
output WR;
output T1;
output n_T0;
output T0;
output n_T1X;
output n_IPC;
// Implementation
wire n_STORE;
wire n_SHIFT;
wire n_MemOP;
wire STOR;
wire REST;
wire BR2;
wire BR3;
wire NotReadyPhi1;
wire ACRL1;
wire ENDS;
wire n_TRESX;
wire BRA;
assign n_STORE = ~X[97];
nor (n_SHIFT, X[106], X[107]);
nor (n_MemOP, X[111], X[122], X[123], X[124], X[125]);
nor (STOR, n_MemOP, n_STORE);
nand (REST, n_SHIFT, n_STORE);
assign BR2 = X[80];
assign BR3 = X[93];
ReadyRW ready_rw (
.PHI1(PHI1),
.PHI2(PHI2),
.RDY(RDY),
.STOR(STOR),
.PC_DB(PC_DB),
.D98(X[98]),
.D100(X[100]),
.T6(T6),
.T7(T7),
.DORES(DORES),
.n_ready(n_ready),
.NotReadyPhi1(NotReadyPhi1),
.WR(WR) );
ACRLatch acrl (
.PHI1(PHI1),
.PHI2(PHI2),
.ACR(ACR),
.NotReadyPhi1(NotReadyPhi1),
.ACRL1(ACRL1),
.ACRL2(ACRL2) );
RMWCycle rmw (
.PHI1(PHI1),
.PHI2(PHI2),
.n_ready(n_ready),
.n_SHIFT(n_SHIFT),
.n_MemOP(n_MemOP),
.T6(T6),
.T7(T7) );
TwoCycle twocyc (
.PHI1(PHI1),
.PHI2(PHI2),
.n_ready(n_ready),
.RESP(RESP),
.ENDS(ENDS),
.n_TWOCYCLE(n_TWOCYCLE),
.n_TRESX(n_TRESX),
.BRA(BRA),
.T0(T0),
.T1(T1),
.n_T0(n_T0),
.n_T1X(n_T1X) );
CompletionUnit comp_unit (
.PHI1(PHI1),
.PHI2(PHI2),
.n_ready(n_ready),
.ACRL1(ACRL1),
.REST(REST),
.BRK6E(BRK6E),
.RESP(RESP),
.n_SHIFT(n_SHIFT),
.n_MemOP(n_MemOP),
.X(X),
.T0(T0),
.T1(T1),
.T7(T7),
.n_BRTAKEN(n_BRTAKEN),
.BR2(BR2),
.BR3(BR3),
.TRES2(TRES2),
.n_TRESX(n_TRESX),
.ENDS(ENDS) );
IncrementPC incpc (
.PHI1(PHI1),
.PHI2(PHI2),
.B_OUT(B_OUT),
.NotReadyPhi1(NotReadyPhi1),
.BRFW(BRFW),
.ACR(ACR),
.n_ready(n_ready),
.n_BRTAKEN(n_BRTAKEN),
.n_ADL_PCL(n_ADL_PCL),
.n_IMPLIED(n_IMPLIED),
.BR2(BR2),
.BR3(BR3),
.BRA(BRA),
.n_IPC(n_IPC) );
FetchUnit fetch_unit (
.PHI2(PHI2),
.B_OUT(B_OUT),
.T1(T1),
.n_ready(n_ready),
.Z_IR(Z_IR),
.FETCH(FETCH) );
endmodule // Dispatch |
module ReadyRW (PHI1, PHI2, RDY, STOR, PC_DB, D98, D100, T6, T7, DORES, n_ready, NotReadyPhi1, WR);
input PHI1;
input PHI2;
input RDY;
input STOR;
input PC_DB;
input D98;
input D100;
input T6;
input T7;
input DORES;
output n_ready;
output NotReadyPhi1;
output WR;
wire wr_latch_d;
wire wr_latch_q;
wire ready_latch1_d;
wire ready_latch1_nq;
wire ready_latch2_q;
wire rdydelay_latch1_nq;
nor (wr_latch_d, STOR, PC_DB, D98, D100, T6, T7);
nor (ready_latch1_d, RDY, ready_latch2_q);
nor (WR, n_ready, wr_latch_q, DORES);
dlatch wr_latch (.d(wr_latch_d), .en(PHI2), .q(wr_latch_q));
dlatch ready_latch1 (.d(ready_latch1_d), .en(PHI2), .nq(ready_latch1_nq));
dlatch ready_latch2 (.d(WR), .en(PHI1), .q(ready_latch2_q));
dlatch rdydelay_latch1 (.d(n_ready), .en(PHI1), .nq(rdydelay_latch1_nq));
dlatch rdydelay_latch2 (.d(rdydelay_latch1_nq), .en(PHI2), .nq(NotReadyPhi1));
assign n_ready = ~ready_latch1_nq;
endmodule // ReadyRW |
module ACRLatch (PHI1, PHI2, ACR, NotReadyPhi1, ACRL1, ACRL2);
input PHI1;
input PHI2;
input ACR;
input NotReadyPhi1;
output ACRL1;
output ACRL2;
wire acr_latch1_nq;
wire ReadyPhi1;
wire t1;
wire t2;
assign ReadyPhi1 = ~NotReadyPhi1;
and (t1, ~ACR, ReadyPhi1);
nor (t2, ReadyPhi1, ACRL2);
nor (ACRL1, t1, t2);
dlatch acr_latch1 (.d(ACRL1), .en(PHI1), .nq(acr_latch1_nq));
dlatch acr_latch2 (.d(acr_latch1_nq), .en(PHI2), .nq(ACRL2));
endmodule // ACRLatch |
module TwoCycle (PHI1, PHI2, n_ready, RESP, ENDS, n_TWOCYCLE, n_TRESX, BRA, T0, T1, n_T0, n_T1X);
input PHI1;
input PHI2;
input n_ready;
input RESP;
input ENDS;
input n_TWOCYCLE;
input n_TRESX;
input BRA;
output T0;
output T1;
output n_T0;
output n_T1X;
wire nready_latch_q;
wire step_latch1_d;
wire step_latch1_q;
wire step_latch2_d;
wire step_latch2_q;
wire t2;
wire t1_latch_d;
wire TRES1;
nor (step_latch1_d, RESP, nready_latch_q, step_latch2_q);
nor (step_latch2_d, step_latch1_q, BRA);
nor (t2, step_latch2_d, n_ready);
nor (t1_latch_d, t2, ENDS);
assign TRES1 = ~t1_latch_d;
dlatch nready_latch (.d(~n_ready), .en(PHI1), .q(nready_latch_q));
dlatch step_latch1 (.d(step_latch1_d), .en(PHI2), .q(step_latch1_q));
dlatch step_latch2 (.d(step_latch2_d), .en(PHI1), .q(step_latch2_q));
dlatch t1_latch (.d(t1_latch_d), .en(PHI1), .nq(T1));
wire comp_latch1_q;
wire comp_latch2_q;
wire comp_latch3_q;
wire t3;
wire t4;
wire t0_latch_q;
wire t1x_latch_q;
wire t1x_latch_d;
nor (t3, comp_latch1_q, comp_latch2_q & comp_latch3_q);
nor (t4, t0_latch_q, t1x_latch_q);
nor (n_T0, t3, t4);
assign T0 = ~n_T0;
nor (t1x_latch_d, t0_latch_q, n_ready);
dlatch comp_latch1 (.d(TRES1), .en(PHI1), .q(comp_latch1_q));
dlatch comp_latch2 (.d(n_TWOCYCLE), .en(PHI1), .q(comp_latch2_q));
dlatch comp_latch3 (.d(n_TRESX), .en(PHI1), .q(comp_latch3_q));
dlatch t0_latch (.d(n_T0), .en(PHI2), .q(t0_latch_q));
dlatch t1x_latch (.d(t1x_latch_d), .en(PHI1), .q(t1x_latch_q), .nq(n_T1X));
endmodule // TwoCycle |
module RMWCycle (PHI1, PHI2, n_ready, n_SHIFT, n_MemOP, T6, T7);
input PHI1;
input PHI2;
input n_ready;
input n_SHIFT;
input n_MemOP;
output T6;
output T7;
wire t67_latch_d;
wire t67_latch_q;
wire t6_latch1_d;
wire t6_latch2_q;
wire t7_latch1_d;
wire t7_latch1_nq;
wire t7_latch2_nq;
nor (t67_latch_d, n_SHIFT, n_MemOP, n_ready);
nor (t6_latch1_d, t67_latch_q, t6_latch2_q & n_ready);
nand (t7_latch1_d, T6, ~n_ready);
dlatch t67_latch (.d(t67_latch_d), .en(PHI2), .q(t67_latch_q));
dlatch t6_latch1 (.d(t6_latch1_d), .en(PHI1), .nq(T6));
dlatch t6_latch2 (.d(T6), .en(PHI2), .q(t6_latch2_q));
dlatch t7_latch1 (.d(t7_latch1_d), .en(PHI2), .nq(t7_latch1_nq));
dlatch t7_latch2 (.d(t7_latch1_nq), .en(PHI1), .nq(t7_latch2_nq));
assign T7 = ~t7_latch2_nq;
endmodule // RMWCycle |
module CompletionUnit (PHI1, PHI2, n_ready, ACRL1, REST, BRK6E, RESP, n_SHIFT, n_MemOP, X, T0, T1, T7, n_BRTAKEN, BR2, BR3, TRES2, n_TRESX, ENDS);
input PHI1;
input PHI2;
input n_ready;
input ACRL1;
input REST;
input BRK6E;
input RESP;
input n_SHIFT;
input n_MemOP;
input [129:0] X;
input T0;
input T1;
input T7;
input n_BRTAKEN;
input BR2;
input BR3;
output TRES2;
output n_TRESX;
output ENDS;
wire tresx_latch1_q;
wire tresx_latch1_d;
wire tresx_latch2_nq;
wire tresx_latch2_d;
wire ends_latch1_q;
wire ends_latch1_d;
wire ends_latch2_q;
wire t1;
wire t2;
wire t3;
wire t4;
wire ENDX;
wire t5;
nor (tresx_latch1_d, X[91], X[92]);
nor (t1, ACRL1, tresx_latch1_q, n_ready, REST);
nor (n_TRESX, t1, BRK6E, tresx_latch2_nq);
nor (t2, X[96], ~n_SHIFT, n_MemOP);
nor (t3, X[100], X[101], X[102], X[103], X[104], X[105]);
nor (ENDX, t2, T7, ~t3, BR3);
nor (t4, n_ready, ENDX);
nor (tresx_latch2_d, RESP, ENDS, t4);
nor (t5, T0, n_BRTAKEN & BR2);
assign ends_latch1_d = n_ready ? ~T1 : t5;
dlatch tresx_latch1 (.d(tresx_latch1_d), .en(PHI2), .q(tresx_latch1_q));
dlatch tresx_latch2 (.d(tresx_latch2_d), .en(PHI2), .nq(tresx_latch2_nq));
dlatch tres2_latch (.d(n_TRESX), .en(PHI1), .nq(TRES2));
dlatch ends_latch1 (.d(ends_latch1_d), .en(PHI2), .q(ends_latch1_q));
dlatch ends_latch2 (.d(RESP), .en(PHI2), .q(ends_latch2_q));
nor (ENDS, ends_latch1_q, ends_latch2_q);
endmodule // CompletionUnit |
module IncrementPC (PHI1, PHI2, B_OUT, NotReadyPhi1, BRFW, ACR, n_ready, n_BRTAKEN, n_ADL_PCL, n_IMPLIED, BR2, BR3, BRA, n_IPC);
input PHI1;
input PHI2;
input B_OUT;
input NotReadyPhi1;
input BRFW;
input ACR;
input n_ready;
input n_BRTAKEN;
input n_ADL_PCL;
input n_IMPLIED;
input BR2;
input BR3;
output BRA;
output n_IPC;
wire br_latch2_d;
wire br_latch2_nq;
wire br_latch1_q;
wire br_latch1_d;
wire ipc_latch1_q;
wire ipc_latch2_q;
wire ipc_latch3_q;
wire ipc_latch3_d;
wire t1;
wire t2;
nor (br_latch2_d, ~BR3, NotReadyPhi1);
xor (t1, BRFW, ~ACR);
and (BRA, t1, ~br_latch2_nq);
nor (t2, n_ADL_PCL, BR2 | BR3);
nor (br_latch1_d, t2, n_BRTAKEN & BR2);
nor (ipc_latch3_d, n_ready, br_latch1_q, ~n_IMPLIED);
dlatch br_latch2 (.d(br_latch2_d), .en(PHI2), .nq(br_latch2_nq));
dlatch br_latch1 (.d(br_latch1_d), .en(PHI2), .q(br_latch1_q));
dlatch ipc_latch1 (.d(B_OUT), .en(PHI1), .q(ipc_latch1_q));
dlatch ipc_latch2 (.d(BRA), .en(PHI1), .q(ipc_latch2_q));
dlatch ipc_latch3 (.d(ipc_latch3_d), .en(PHI1), .q(ipc_latch3_q));
nand (n_IPC, ipc_latch1_q, ipc_latch2_q | ipc_latch3_q);
endmodule // IncrementPC |
module FetchUnit (PHI2, B_OUT, T1, n_ready, Z_IR, FETCH);
input PHI2;
input B_OUT;
input T1;
input n_ready;
output Z_IR;
output FETCH;
wire fetch_latch_nq;
dlatch fetch_latch (.d(T1), .en(PHI2), .nq(fetch_latch_nq));
nor (FETCH, fetch_latch_nq, n_ready);
nand (Z_IR, FETCH, B_OUT);
endmodule // FetchUnit |
module Decoder(
n_T0, n_T1X,
n_T2, n_T3, n_T4, n_T5,
IR01,
IR, n_IR,
X);
input n_T0;
input n_T1X;
input n_T2;
input n_T3;
input n_T4;
input n_T5;
input IR01;
input [7:0] IR;
input [7:0] n_IR;
output [129:0] X;
wire [20:0] d;
assign d = {n_T1X,n_T0,n_IR[5],IR[5],n_IR[6],IR[6],n_IR[2],IR[2],n_IR[3],IR[3],n_IR[4],IR[4],n_IR[7],IR[7],n_IR[0],IR01,n_IR[1],n_T2,n_T3,n_T4,n_T5};
assign X[0] = ~|{d[5],d[8],d[14],d[15],d[17]};
assign X[1] = ~|{d[2],d[6],d[10],d[11],d[13]};
assign X[2] = ~|{d[3],d[6],d[10],d[12],d[13]};
assign X[3] = ~|{d[5],d[8],d[9],d[12],d[13],d[17],d[19]};
assign X[4] = ~|{d[5],d[8],d[10],d[12],d[13],d[15],d[17],d[19]};
assign X[5] = ~|{d[5],d[8],d[9],d[16],d[17],d[19]};
assign X[6] = ~|{d[3],d[10],d[14]};
assign X[7] = ~|{d[4],d[8],d[15]};
assign X[8] = ~|{d[3],d[6],d[9],d[11],d[13]};
assign X[9] = ~|{d[4],d[8],d[9],d[12],d[13],d[15],d[17],d[19]};
assign X[10] = ~|{d[4],d[8],d[9],d[12],d[13],d[16],d[17],d[19]};
assign X[11] = ~|{d[5],d[8],d[9],d[16],d[18],d[19]};
assign X[12] = ~|{d[4],d[8],d[15],d[17]};
assign X[13] = ~|{d[4],d[8],d[10],d[12],d[13],d[15],d[17],d[19]};
assign X[14] = ~|{d[4],d[8],d[15],d[18],d[19]};
assign X[15] = ~|{d[4],d[8],d[9],d[12],d[13],d[16],d[17],d[20]};
assign X[16] = ~|{d[5],d[8],d[9],d[12],d[13],d[16],d[18],d[20]};
assign X[17] = ~|{d[4],d[8],d[10],d[12],d[13],d[15],d[18],d[19]};
assign X[18] = ~|{d[5],d[8],d[9],d[12],d[13],d[17],d[20]};
assign X[19] = ~|{d[5],d[8],d[14],d[15],d[18],d[19]};
assign X[20] = ~|{d[5],d[8],d[9],d[15],d[18],d[19]};
assign X[21] = ~|{d[5],d[7],d[9],d[11],d[13],d[15],d[18],d[19]};
assign X[22] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign X[23] = ~|{d[5],d[7],d[9],d[12],d[13],d[17],d[19]};
assign X[24] = ~|{d[1],d[5],d[7],d[9],d[11],d[13],d[16],d[18]};
assign X[25] = ~|{d[2],d[5],d[7],d[9],d[12],d[13],d[18]};
assign X[26] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[16],d[17]};
assign X[27] = ~|{d[4],d[7],d[16],d[18]};
assign X[28] = ~|{d[3]};
assign X[29] = ~|{d[6],d[7],d[16],d[17],d[19]};
assign X[30] = ~|{d[5],d[7],d[9],d[12],d[14],d[16]};
assign X[31] = ~|{d[3],d[9],d[12],d[14]};
assign X[32] = ~|{d[6],d[7],d[15],d[17],d[19]};
assign X[33] = ~|{d[3],d[11]};
assign X[34] = ~|{d[19]};
assign X[35] = ~|{d[3],d[5],d[7],d[9],d[13]};
assign X[36] = ~|{d[2],d[5],d[7],d[9]};
assign X[37] = ~|{d[1],d[5],d[7],d[9],d[11],d[13],d[15]};
assign X[38] = ~|{d[1],d[5],d[7],d[9],d[11],d[13],d[16],d[17]};
assign X[39] = ~|{d[2],d[6],d[9],d[11],d[13]};
assign X[40] = ~|{d[1],d[6],d[10],d[11],d[13]};
assign X[41] = ~|{d[3],d[6],d[10],d[11],d[13]};
assign X[42] = ~|{d[2],d[10],d[12]};
assign X[43] = ~|{d[5],d[7],d[9],d[12],d[13],d[18]};
assign X[44] = ~|{d[4],d[8],d[16],d[18]};
assign X[45] = ~|{d[1],d[6],d[9],d[11],d[13]};
assign X[46] = ~|{d[2],d[6],d[10],d[11],d[13]};
assign X[47] = ~|{d[5],d[7],d[9],d[11],d[13],d[16]};
assign X[48] = ~|{d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[18]};
assign X[49] = ~|{d[5],d[8],d[9],d[16],d[19]};
assign X[50] = ~|{d[6],d[8],d[16],d[17],d[19]};
assign X[51] = ~|{d[6],d[8],d[16],d[18],d[19]};
assign X[52] = ~|{d[6],d[16],d[18],d[19]};
assign X[53] = ~|{d[4],d[7],d[15],d[18]};
assign X[54] = ~|{d[2],d[5],d[7],d[9],d[12],d[14],d[16]};
assign X[55] = ~|{d[4],d[7],d[15]};
assign X[56] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[15],d[18]};
assign X[57] = ~|{d[3],d[5],d[7],d[9],d[13]};
assign X[58] = ~|{d[5],d[8],d[10],d[12],d[13],d[15],d[17],d[19]};
assign X[59] = ~|{d[6],d[7],d[20]};
assign X[60] = ~|{d[6],d[16],d[18],d[20]};
assign X[61] = ~|{d[4],d[7],d[9],d[12],d[13],d[20]};
assign X[62] = ~|{d[4],d[8],d[9],d[12],d[13],d[15],d[17],d[19]};
assign X[63] = ~|{d[5],d[7],d[9],d[12],d[13],d[16],d[18],d[19]};
assign X[64] = ~|{d[6],d[8],d[15],d[18],d[19]};
assign X[65] = ~|{d[6],d[19]};
assign X[66] = ~|{d[5],d[8],d[9],d[12],d[13],d[15],d[18],d[19]};
assign X[67] = ~|{d[4],d[7],d[9],d[12],d[13],d[19]};
assign X[68] = ~|{d[4],d[8],d[9],d[12],d[13],d[15],d[18],d[19]};
assign X[69] = ~|{d[5],d[7],d[9],d[14],d[15],d[18],d[19]};
assign X[70] = ~|{d[6],d[7],d[15],d[18],d[19]};
assign X[71] = ~|{d[1],d[10],d[12]};
assign X[72] = ~|{d[0],d[6],d[10],d[11],d[13]};
assign X[73] = ~|{d[5],d[10],d[11],d[13],d[19]};
assign X[74] = ~|{d[3],d[5],d[7],d[9],d[12],d[13],d[16],d[17]};
assign X[75] = ~|{d[4],d[7],d[9],d[12],d[13],d[16],d[19]};
assign X[76] = ~|{d[4],d[7],d[16]};
assign X[77] = ~|{d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign X[78] = ~|{d[2],d[5],d[7],d[9],d[11],d[13],d[15],d[18]};
assign X[79] = ~|{d[6],d[8],d[15],d[17]};
assign X[80] = ~|{d[3],d[5],d[10],d[11],d[13]};
assign X[81] = ~|{d[3],d[11],d[14]};
assign X[82] = ~|{d[3],d[6],d[11],d[13]};
assign X[83] = ~|{d[3],d[12]};
assign X[84] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[16],d[18]};
assign X[85] = ~|{d[1]};
assign X[86] = ~|{d[2]};
assign X[87] = ~|{d[5],d[7],d[9],d[11],d[13],d[17],d[19]};
assign X[88] = ~|{d[5],d[7],d[9],d[12],d[14],d[16],d[19]};
assign X[89] = ~|{d[0],d[6],d[9],d[11],d[13]};
assign X[90] = ~|{d[2],d[12]};
assign X[91] = ~|{d[1],d[6],d[10],d[11],d[13]};
assign X[92] = ~|{d[2],d[10],d[12]};
assign X[93] = ~|{d[2],d[5],d[10],d[11],d[13]};
assign X[94] = ~|{d[5],d[7],d[9],d[11],d[13],d[17]};
assign X[95] = ~|{d[5],d[7],d[9],d[11],d[13],d[15],d[18]};
assign X[96] = ~|{d[5],d[7],d[9],d[12],d[14],d[16]};
assign X[97] = ~|{d[8],d[15],d[17]};
assign X[98] = ~|{d[1],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign X[99] = ~|{d[3],d[5],d[7],d[9],d[12],d[13],d[15],d[17]};
assign X[100] = ~|{d[3],d[5],d[7],d[9],d[12],d[13],d[17]};
assign X[101] = ~|{d[1],d[5],d[7],d[9],d[12],d[14],d[16]};
assign X[102] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[16]};
assign X[103] = ~|{d[0],d[5],d[7],d[9],d[11],d[13],d[15],d[18]};
assign X[104] = ~|{d[3],d[5],d[7],d[9],d[12],d[14],d[16],d[17]};
assign X[105] = ~|{d[2],d[5],d[7],d[9],d[12],d[13],d[18]};
assign X[106] = ~|{d[4],d[16]};
assign X[107] = ~|{d[4],d[7],d[15]};
assign X[108] = ~|{d[5],d[7],d[10],d[12],d[13],d[16],d[19]};
assign X[109] = ~|{d[5],d[7],d[9],d[14],d[15],d[18],d[20]};
assign X[110] = ~|{d[5],d[7],d[10],d[12],d[13],d[15],d[19]};
assign X[111] = ~|{d[2],d[10],d[11],d[14]};
assign X[112] = ~|{d[6],d[16],d[18],d[20]};
assign X[113] = ~|{d[5],d[7],d[9],d[14],d[15],d[18],d[19]};
assign X[114] = ~|{d[5],d[7],d[9],d[12],d[13],d[15],d[18],d[19]};
assign X[115] = ~|{d[1],d[5],d[7],d[9],d[11],d[13],d[16],d[17]};
assign X[116] = ~|{d[6],d[8],d[16],d[17],d[20]};
assign X[117] = ~|{d[5],d[8],d[9],d[12],d[14],d[16],d[20]};
assign X[118] = ~|{d[4],d[7],d[9],d[12],d[13],d[15],d[20]};
assign X[119] = ~|{d[5],d[8],d[9],d[11],d[16],d[20]};
assign X[120] = ~|{d[5],d[8],d[10],d[12],d[13],d[16],d[19]};
assign X[121] = ~|{d[15]};
assign X[122] = ~|{d[2],d[9],d[12],d[14]};
assign X[123] = ~|{d[3],d[9],d[11],d[14]};
assign X[124] = ~|{d[0],d[6],d[11],d[13]};
assign X[125] = ~|{d[1],d[10],d[12]};
assign X[126] = ~|{d[7]};
assign X[127] = ~|{d[5],d[8],d[10],d[12],d[13],d[15],d[18]};
assign X[128] = ~|{d[12],d[13]};
assign X[129] = ~|{d[5],d[7],d[9],d[12],d[13]};
endmodule // Decoder |
module Regs (
PHI2,
Y_SB, SB_Y, X_SB, SB_X, S_SB, S_ADL, S_S, SB_S,
SB, ADL);
input PHI2;
input Y_SB;
input SB_Y;
input X_SB;
input SB_X;
input S_SB;
input S_ADL;
input S_S; // Stack reg -> Shadow Stack reg
input SB_S;
inout [7:0] SB;
inout [7:0] ADL;
XYRegBit yreg[7:0] (.PHI2(PHI2), .Reg_SB(Y_SB), .SB_Reg(SB_Y), .SB_bit(SB), .dbg(y) );
XYRegBit xreg[7:0] (.PHI2(PHI2), .Reg_SB(X_SB), .SB_Reg(SB_X), .SB_bit(SB), .dbg(x) );
SRegBit sreg[7:0] (.PHI2(PHI2), .S_SB(S_SB), .S_ADL(S_ADL), .SB_S(SB_S), .S_S(S_S), .SB_bit(SB), .ADL_bit(ADL), .S_dbg(s), .SS_dbg(ss) );
// Debug. Not on a real chip
wire [7:0] x, y, ss, s;
endmodule // Regs |
module XYRegBit (PHI2, Reg_SB, SB_Reg, SB_bit, dbg);
input PHI2;
input Reg_SB;
input SB_Reg;
inout SB_bit;
output dbg; // Not on a real chip
wire d;
assign d = SB_Reg ? SB_bit : (PHI2 ? not_nq : 1'bz);
wire hold_latch_nq;
wire not_nq;
dlatch hold_latch (.d(d), .en(1'b1), .q(dbg), .nq(hold_latch_nq));
not (not_nq, hold_latch_nq);
assign SB_bit = Reg_SB ? not_nq : 1'bz;
endmodule // XYRegBit |
module SRegBit (PHI2, S_SB, S_ADL, SB_S, S_S, SB_bit, ADL_bit, S_dbg, SS_dbg);
input PHI2;
input S_SB;
input S_ADL;
input SB_S;
input S_S;
inout SB_bit;
inout ADL_bit;
output S_dbg; // Not on a real chip
output SS_dbg; // Not on a real chip
wire d;
assign d = SB_S ? SB_bit : (S_S ? out_latch_nq : 1'bz);
wire in_latch_nq;
wire out_latch_nq;
dlatch in_latch (.d(d), .en(1'b1), .q(SS_dbg), .nq(in_latch_nq)); // Shadow Stack reg
dlatch out_latch (.d(in_latch_nq), .en(PHI2), .nq(out_latch_nq)); // Stack reg
assign S_dbg = out_latch_nq;
assign SB_bit = S_SB ? out_latch_nq : 1'bz;
assign ADL_bit = S_ADL ? out_latch_nq : 1'bz;
endmodule // SRegBit |
module Regs_Control (
PHI1, PHI2,
STOR, n_ready,
X,
STXY, n_SBXY, STKOP,
Y_SB, X_SB, S_SB, SB_X, SB_Y, SB_S, S_S, S_ADL);
input PHI1;
input PHI2;
input STOR;
input n_ready;
input [129:0] X;
output STXY;
output n_SBXY;
output STKOP;
output Y_SB;
output X_SB;
output S_SB;
output SB_X;
output SB_Y;
output SB_S;
output S_S;
output S_ADL;
wire nYSB;
wire nXSB;
wire nSBX;
wire nSBY;
wire nSBS;
wire nSADL;
wire tmp1;
wire nready_latch_q;
wire nready_latch_nq;
wire ysb_latch_q;
wire xsb_latch_q;
wire sbx_latch_q;
wire sby_latch_q;
wire sbs_latch_q;
wire ss_latch_q;
assign nYSB = ~(X[1] | X[2] | X[3] | X[4] | X[5] | (X[6]&X[7]) | (X[0]&STOR));
assign nXSB = ~(X[8] | X[9] | X[10] | X[11] | X[13] | (X[6]&~X[7]) | (X[12]&STOR));
assign nSBX = ~(X[14] | X[15] | X[16]);
assign nSBY = ~(X[18] | X[19] | X[20]);
assign tmp1 = ~(X[21] | X[22] | X[23] | X[24] | X[25] | X[26]);
assign nSBS = ~(X[13] | ~(~X[48]|n_ready) | STKOP);
assign nSADL = ~((X[21]&nready_latch_nq) | X[35]);
assign STXY = ~((X[0]&STOR) | (X[12]&STOR));
assign n_SBXY = ~(nSBX & nSBY);
assign STKOP = ~(tmp1|nready_latch_q);
dlatch nready_latch (.d(n_ready), .en(PHI1), .q(nready_latch_q), .nq(nready_latch_nq));
dlatch ysb_latch (.d(nYSB), .en(PHI2), .q(ysb_latch_q));
dlatch xsb_latch (.d(nXSB), .en(PHI2), .q(xsb_latch_q));
dlatch ssb_latch (.d(~X[17]), .en(PHI2), .nq(S_SB));
dlatch sbx_latch (.d(nSBX), .en(PHI2), .q(sbx_latch_q));
dlatch sby_latch (.d(nSBY), .en(PHI2), .q(sby_latch_q));
dlatch sbs_latch (.d(nSBS), .en(PHI2), .q(sbs_latch_q));
dlatch ss_latch (.d(~nSBS), .en(PHI2), .q(ss_latch_q));
dlatch sadl_latch (.d(nSADL), .en(PHI2), .nq(S_ADL));
assign Y_SB = ~(ysb_latch_q|PHI2);
assign X_SB = ~(xsb_latch_q|PHI2);
assign SB_X = ~(sbx_latch_q|PHI2);
assign SB_Y = ~(sby_latch_q|PHI2);
assign SB_S = ~(sbs_latch_q|PHI2);
assign S_S = ~(ss_latch_q|PHI2);
endmodule // Regs_Control |
module Flags (
PHI1, PHI2,
P_DB, DB_P, DBZ_Z, DB_N, IR5_C, DB_C, ACR_C, IR5_D, IR5_I, DB_V, Z_V,
ACR, AVR, B_OUT, n_IR5, BRK6E, Dec112, SO_frompad,
DB,
n_ZOUT, n_NOUT, n_COUT, n_DOUT, n_IOUT, n_VOUT);
input PHI1;
input PHI2;
input P_DB;
input DB_P;
input DBZ_Z;
input DB_N;
input IR5_C;
input DB_C;
input ACR_C;
input IR5_D;
input IR5_I;
input DB_V;
input Z_V;
input ACR;
input AVR;
input B_OUT; // From the BRK sequencer
input n_IR5;
input BRK6E;
input Dec112; // AVR/V
input SO_frompad; // Directly from the pad
inout [7:0] DB;
output n_ZOUT;
output n_NOUT;
output n_COUT;
output n_DOUT;
output n_IOUT;
output n_VOUT;
wire DBZ;
nor (DBZ, DB[0], DB[1], DB[2], DB[3], DB[4], DB[5], DB[6], DB[7]);
// Z Flag
wire z_latch1_d;
assign z_latch1_d = ~( (~DB[1] & DB_P) | (~DBZ & DBZ_Z) | (~(DB_P|DBZ_Z) & z_latch2_q) ); // 222-aoi
dlatch z_latch1 (.d(z_latch1_d), .en(PHI1), .nq(n_ZOUT) );
dlatch z_latch2 (.d(n_ZOUT), .en(PHI2), .q(z_latch2_q) );
wire z_latch2_q;
// N Flag
wire n_latch1_d;
assign n_latch1_d = ~( (~DB[7] & DB_N) | (~DB_N & n_latch2_q) ); // 22-aoi
dlatch n_latch1 (.d(n_latch1_d), .en(PHI1), .nq(n_NOUT) );
dlatch n_latch2 (.d(n_NOUT), .en(PHI2), .q(n_latch2_q) );
wire n_latch2_q;
// C Flag
wire c_latch1_d;
assign c_latch1_d = ~( (n_IR5 & IR5_C) | (~ACR & ACR_C) | (~DB[0] & DB_C) | (~(DB_C|IR5_C|ACR_C) & c_latch2_q) ); // 2222-aoi
dlatch c_latch1 (.d(c_latch1_d), .en(PHI1), .nq(n_COUT) );
dlatch c_latch2 (.d(n_COUT), .en(PHI2), .q(c_latch2_q) );
wire c_latch2_q;
// D Flag
wire d_latch1_d;
assign d_latch1_d = ~( (IR5_D & n_IR5) | (~DB[3] & DB_P) | (~(IR5_D|DB_P) & d_latch2_q) ); // 222-aoi
dlatch d_latch1 (.d(d_latch1_d), .en(PHI1), .nq(n_DOUT) );
dlatch d_latch2 (.d(n_DOUT), .en(PHI2), .q(d_latch2_q) );
wire d_latch2_q;
// I Flag
wire i_latch1_nq;
wire i_latch1_d;
assign i_latch1_d = ~( (n_IR5 & IR5_I) | (~DB[2] & DB_P) | (~(DB_P|IR5_I) & i_latch2_q) ); // 222-aoi
dlatch i_latch1 (.d(i_latch1_d), .en(PHI1), .nq(i_latch1_nq));
assign n_IOUT = i_latch1_nq & ~BRK6E;
dlatch i_latch2 (.d(n_IOUT), .en(PHI2), .q(i_latch2_q) );
wire i_latch2_q;
// V Flag
wire AVR_V;
assign AVR_V = Dec112;
dlatch avr_latch (.d(AVR_V), .en(PHI2), .q(avr_latch_q) );
wire avr_latch_q;
wire v_latch1_d;
assign v_latch1_d = ~( (~AVR & avr_latch_q) | (~DB[6] & DB_V) | ( ~(DB_V|avr_latch_q|One_V) & v_latch2_q) | Z_V ); // 2221-aoi
dlatch v_latch1 (.d(v_latch1_d), .en(PHI1), .nq(n_VOUT) );
dlatch v_latch2 (.d(n_VOUT), .en(PHI2), .q(v_latch2_q) );
wire v_latch2_q;
// 1/V
// SO Pad falling edge detector is integrated right there
wire One_V;
dlatch so_latch1 (.d(~SO_frompad), .en(PHI1), .nq(so_latch1_nq) );
wire so_latch1_nq;
dlatch so_latch2 (.d(so_latch1_nq), .en(PHI2), .nq(so_latch2_nq) );
wire so_latch2_nq;
dlatch so_latch3 (.d(so_latch2_nq), .en(PHI1), .q(so_latch3_q) );
wire so_latch3_q;
wire vset_latch_d;
nor (vset_latch_d, so_latch3_q, so_latch1_nq);
dlatch vset_latch (.d(vset_latch_d), .en(PHI2), .q(One_V) );
// decomplements and debug at the same time
wire COUT, ZOUT, IOUT, DOUT, VOUT, NOUT;
not (COUT, n_COUT);
not (ZOUT, n_ZOUT);
not (IOUT, n_IOUT);
not (DOUT, n_DOUT);
not (VOUT, n_VOUT);
not (NOUT, n_NOUT);
// Flags Out
assign DB[0] = P_DB ? COUT : 1'bz;
assign DB[1] = P_DB ? ZOUT : 1'bz;
assign DB[2] = P_DB ? IOUT : 1'bz;
assign DB[3] = P_DB ? DOUT : 1'bz;
assign DB[4] = P_DB ? B_OUT : 1'bz; // From the BRK sequencer
assign DB[5] = 1'bz;
assign DB[6] = P_DB ? VOUT : 1'bz;
assign DB[7] = P_DB ? NOUT : 1'bz;
endmodule // Flags |
module ALU (
PHI2,
NDB_ADD, DB_ADD, Z_ADD, SB_ADD, ADL_ADD, ADD_SB06, ADD_SB7, ADD_ADL,
ANDS, EORS, ORS, SRS, SUMS,
SB_AC, AC_SB, AC_DB,
n_ACIN, n_DAA, n_DSA,
SB, DB, ADL, ADH,
ACR, AVR);
input PHI2;
input NDB_ADD;
input DB_ADD;
input Z_ADD;
input SB_ADD;
input ADL_ADD;
input ADD_SB06;
input ADD_SB7;
input ADD_ADL;
input ANDS;
input EORS;
input ORS;
input SRS;
input SUMS;
input SB_AC;
input AC_SB;
input AC_DB;
input n_ACIN;
input n_DAA;
input n_DSA;
inout [7:0] SB;
inout [7:0] DB;
inout [7:0] ADL;
inout [7:0] ADH;
output ACR;
output AVR;
// To debug: ai(AI), bi(BI), add_out(ADD), ACIN(CarryIn), ACR(CarryOut), AVR(OverflowOut), AC_q(A)
// ALU Ops intermediate results
wire [7:0] nands;
wire [7:0] ands; // odd bits only
wire [7:0] nors;
wire [7:0] ors; // even bits only
wire [7:0] xors; // odd bits only
wire [7:0] xnors; // even bits only
wire [7:0] nsums;
wire [7:0] nres;
wire [7:0] cout; // inverted carry chain (even bits out: regular polarity, odd bits out: inverted polarity)
// AI/BI Latches
wire [7:0] ai_d;
assign ai_d = Z_ADD ? 8'b00000000 : (SB_ADD ? SB : 8'bzzzzzzzz);
wire [7:0] bi_d;
assign bi_d = ADL_ADD ? ADL : (DB_ADD ? DB : ( NDB_ADD ? ~DB : 8'bzzzzzzzz) );
dlatch ai_latch [7:0] (.d(ai_d), .en(8'b11111111), .q(ai) );
wire [7:0] ai;
dlatch bi_latch [7:0] (.d(bi_d), .en(8'b11111111), .q(bi) );
wire [7:0] bi;
// ALU Ops
nand na [7:0] (nands, ai, bi);
nor no [7:0] (nors, ai, bi);
not (ands[1], nands[1]);
not (ands[3], nands[3]);
not (ands[5], nands[5]);
not (ands[7], nands[7]);
nor (ors[0], nors[0]);
nor (ors[2], nors[2]);
nor (ors[4], nors[4]);
nor (ors[6], nors[6]);
nand (xnors[0], ors[0], nands[0]);
nand (xnors[2], ors[2], nands[2]);
nand (xnors[4], ors[4], nands[4]);
nand (xnors[6], ors[6], nands[6]);
nor (xors[1], nors[1], ands[1]);
nor (xors[3], nors[3], ands[3]);
nor (xors[5], nors[5], ands[5]);
nor (xors[7], nors[7], ands[7]);
wire ACIN;
not (ACIN, n_ACIN);
assign nsums[0] = ~((xnors[0]&ACIN) | ~(xnors[0]|ACIN));
assign nsums[1] = ~(( xors[1]&~cout[0]) | ~( xors[1]|~cout[0]));
assign nsums[2] = ~((xnors[2]&~cout[1]) | ~(xnors[2]|~cout[1]));
assign nsums[3] = ~(( xors[3]&~cout[2]) | ~( xors[3]|~cout[2]));
assign nsums[4] = ~((xnors[4]&~cout[3]) | ~(xnors[4]|~cout[3]));
assign nsums[5] = ~(( xors[5]&~cout[4]) | ~( xors[5]|~cout[4]));
assign nsums[6] = ~((xnors[6]&~cout[5]) | ~(xnors[6]|~cout[5]));
assign nsums[7] = ~(( xors[7]&~cout[6]) | ~( xors[7]|~cout[6]));
assign nres = SRS ? ({1'b1,nands[7:1]}) : (
ANDS ? nands : (
ORS ? nors : (
EORS ? xnors : (
SUMS ? nsums : 8'bzzzzzzzz ))));
// Carry Chain
aoi cc0 (.a0(n_ACIN), .a1(nands[0]), .b(nors[0]), .x(cout[0]) );
aoi cc1 (.a0(cout[0]), .a1(ors[1]), .b(ands[1]), .x(cout[1]) );
aoi cc2 (.a0(cout[1]), .a1(nands[2]), .b(nors[2]), .x(cout[2]) );
aoi211 cc3 (.a0(cout[2]), .a1(ors[3]), .b(ands[3]), .c(DC3), .x(cout[3]) );
aoi cc4 (.a0(cout[3]), .a1(nands[4]), .b(nors[4]), .x(cout[4]) );
aoi cc5 (.a0(cout[4]), .a1(ors[5]), .b(ands[5]), .x(cout[5]) );
aoi cc6 (.a0(cout[5]), .a1(nands[6]), .b(nors[6]), .x(cout[6]) );
aoi cc7 (.a0(cout[6]), .a1(ors[7]), .b(ands[7]), .x(cout[7]) );
// Fast BCD Carry (https://patents.google.com/patent/US3991307A)
wire nncarry4 = ~(~cout[4]);
wire a0, b0, c0;
wire temp1;
assign temp1 = ~((n_ACIN&nands[0]) | nors[0]);
assign a0 = ~(nors[2] | ~(ands[1] & temp1));
wire nnands2;
assign nnands2 = ~nands[2];
assign b0 = ~(nnands2 | xors[3]);
assign c0 = ~(temp1 | ~(nnands2|nors[2]) | ands[1] | xors[1]);
assign DC3 = (a0 | ~(b0|c0)) & ~n_DAA;
wire a1, b1, c1;
assign a1 = ~(xnors[6] | ~(ands[5]&nncarry4));
assign b1 = ~(xors[7] | ~nands[6]);
assign c1 = ~(nncarry4 | ands[5] | xors[5] | ~xnors[6]);
assign DC7 = (a1 | ~(b1|c1)) & ~n_DAA;
// ACR, AVR
dlatch DCLatch (.d(DC7), .en(PHI2), .q(DCLatch_q) );
wire DCLatch_q;
wire AC7;
not (AC7, cout[7]);
dlatch ACLatch (.d(AC7), .en(PHI2), .q(ACLatch_q) );
wire ACLatch_q;
wire AVRLatch_d;
assign AVRLatch_d = ~(~(cout[6]|nands[7]) | (cout[6]&nors[7]));
dlatch AVRLatch (.d(AVRLatch_d), .en(PHI2), .nq(AVR) );
wire nACR;
nor (nACR, DCLatch_q, ACLatch_q);
not (ACR, nACR);
// Adder Hold
wire nADD1, nADD2, nADD5, nADD6;
wire [7:0] add_out;
dlatch add [7:0] (.d(nres), .en(PHI2), .nq(add_out) );
assign ADL = ADD_ADL ? add_out : 8'bzzzzzzzz;
assign SB[6:0] = ADD_SB06 ? add_out[6:0] : 7'bzzzzzzz;
assign SB[7] = ADD_SB7 ? add_out[7] : 1'bz;
not (nADD1, add_out[1]);
not (nADD2, add_out[2]);
not (nADD5, add_out[5]);
not (nADD6, add_out[6]);
// BCD Correction
wire DAAL, DAAH, DSAL, DSAH;
wire daal_latch_d;
nand (daal_latch_d, ~n_DAA, ~cout[3]);
dlatch daal_latch (.d(daal_latch_d), .en(PHI2), .nq(DAAL) );
dlatch daah_latch (.d(~n_DAA), .en(PHI2), .nq(daah_latch_nq) );
wire daah_latch_nq;
nor (DAAH, nACR, daah_latch_nq);
wire dsal_latch_d;
nor (dsal_latch_d, ~cout[3], n_DSA);
dlatch dsal_latch (.d(dsal_latch_d), .en(PHI2), .q(DSAL) );
dlatch dsah_latch (.d(~n_DSA), .en(PHI2), .nq(dsah_latch_nq) );
wire dsah_latch_nq;
nor (DSAH, ACR, dsah_latch_nq);
bcd_nibble bcd_lo (.daa(DAAL), .dsa(DSAL), .sb(SB[3:0]), .bcd(acin[3:0]), .b1(nADD1), .b2(nADD2) );
bcd_nibble bcd_hi (.daa(DAAH), .dsa(DSAH), .sb(SB[7:4]), .bcd(acin[7:4]), .b1(nADD5), .b2(nADD6) );
// Accumulator + Bus Mpx
wire [7:0] acin;
wire [7:0] ac_d;
assign ac_d = PHI2 ? AC_q : (SB_AC ? acin : 8'bzzzzzzzz);
dlatch AC [7:0] (.d(ac_d), .en(8'b11111111), .nq(AC_nq) );
wire [7:0] AC_nq;
wire [7:0] AC_q;
assign AC_q = ~AC_nq;
assign SB = AC_SB ? AC_q : 8'bzzzzzzzz;
assign DB = AC_DB ? AC_q : 8'bzzzzzzzz;
endmodule // ALU |
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