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module pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 6: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 128,
the_altsyncram.numwords_a = 128,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 7;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule |
module pr_region_default_mm_bridge_1 #(
parameter DATA_WIDTH = 512,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 32,
parameter BURSTCOUNT_WIDTH = 5,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [63:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [63:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_1 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 64, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 64, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule |
module pr_region_alternate_clock_in (
input wire in_clk, // in_clk.clk
output wire out_clk // out_clk.clk
);
endmodule |
module pr_region_alternate_reset_in (
input wire clk, // clk.clk
input wire in_reset, // in_reset.reset
output wire out_reset // out_reset.reset
);
endmodule |
module pr_region_alternate_sysid_qsys_0 (
input wire clock, // clk.clk
output wire [31:0] readdata, // control_slave.readdata
input wire address, // .address
input wire reset_n // reset.reset_n
);
altera_avalon_sysid_qsys #(
.ID_VALUE (-1161889074),
.TIMESTAMP (0)
) sysid_qsys_0 (
.clock (clock), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.readdata (readdata), // output, width = 32, control_slave.readdata
.address (address) // input, width = 1, .address
);
endmodule |
module ghrd_10as066n2_avlmm_pr_freeze_bridge_0 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire reset_n, // reset_n.reset_n
output wire slv_bridge_to_pr_read, // slv_bridge_to_pr.read
input wire slv_bridge_to_pr_waitrequest, // .waitrequest
output wire slv_bridge_to_pr_write, // .write
output wire [9:0] slv_bridge_to_pr_address, // .address
output wire [3:0] slv_bridge_to_pr_byteenable, // .byteenable
output wire [31:0] slv_bridge_to_pr_writedata, // .writedata
input wire [31:0] slv_bridge_to_pr_readdata, // .readdata
output wire [2:0] slv_bridge_to_pr_burstcount, // .burstcount
input wire slv_bridge_to_pr_readdatavalid, // .readdatavalid
output wire slv_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
output wire slv_bridge_to_pr_debugaccess, // .debugaccess
input wire [1:0] slv_bridge_to_pr_response, // .response
output wire slv_bridge_to_pr_lock, // .lock
input wire slv_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
input wire slv_bridge_to_sr_read, // slv_bridge_to_sr.read
output wire slv_bridge_to_sr_waitrequest, // .waitrequest
input wire slv_bridge_to_sr_write, // .write
input wire [9:0] slv_bridge_to_sr_address, // .address
input wire [3:0] slv_bridge_to_sr_byteenable, // .byteenable
input wire [31:0] slv_bridge_to_sr_writedata, // .writedata
output wire [31:0] slv_bridge_to_sr_readdata, // .readdata
input wire [2:0] slv_bridge_to_sr_burstcount, // .burstcount
output wire slv_bridge_to_sr_readdatavalid, // .readdatavalid
input wire slv_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
input wire slv_bridge_to_sr_debugaccess, // .debugaccess
output wire [1:0] slv_bridge_to_sr_response, // .response
input wire slv_bridge_to_sr_lock, // .lock
output wire slv_bridge_to_sr_writeresponsevalid // .writeresponsevalid
);
endmodule |
module ghrd_10as066n2_led_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.in_port
output wire [3:0] out_port, // .out_port
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
endmodule |
module ghrd_10as066n2_clk_0 (
input wire in_clk, // in_clk.clk
output wire out_clk // out_clk.clk
);
endmodule |
module ghrd_10as066n2_issp_0 (
input wire source_clk, // source_clk.clk
output wire [2:0] source // sources.source
);
endmodule |
module ghrd_10as066n2_pr_region_controller_0 (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
endmodule |
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire mst_bridge_to_pr_read, // mst_bridge_to_pr.read
output wire mst_bridge_to_pr_waitrequest, // .waitrequest
input wire mst_bridge_to_pr_write, // .write
input wire [31:0] mst_bridge_to_pr_address, // .address
input wire [3:0] mst_bridge_to_pr_byteenable, // .byteenable
input wire [31:0] mst_bridge_to_pr_writedata, // .writedata
output wire [31:0] mst_bridge_to_pr_readdata, // .readdata
input wire [2:0] mst_bridge_to_pr_burstcount, // .burstcount
output wire mst_bridge_to_pr_readdatavalid, // .readdatavalid
input wire mst_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
input wire mst_bridge_to_pr_debugaccess, // .debugaccess
output wire [1:0] mst_bridge_to_pr_response, // .response
input wire mst_bridge_to_pr_lock, // .lock
output wire mst_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
output wire mst_bridge_to_sr_read, // mst_bridge_to_sr.read
input wire mst_bridge_to_sr_waitrequest, // .waitrequest
output wire mst_bridge_to_sr_write, // .write
output wire [31:0] mst_bridge_to_sr_address, // .address
output wire [3:0] mst_bridge_to_sr_byteenable, // .byteenable
output wire [31:0] mst_bridge_to_sr_writedata, // .writedata
input wire [31:0] mst_bridge_to_sr_readdata, // .readdata
output wire [2:0] mst_bridge_to_sr_burstcount, // .burstcount
input wire mst_bridge_to_sr_readdatavalid, // .readdatavalid
output wire mst_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
output wire mst_bridge_to_sr_debugaccess, // .debugaccess
input wire [1:0] mst_bridge_to_sr_response, // .response
output wire mst_bridge_to_sr_lock, // .lock
input wire mst_bridge_to_sr_writeresponsevalid, // .writeresponsevalid
input wire reset_n // reset_n.reset_n
);
endmodule |
module ghrd_10as066n2_emif_hps (
input wire global_reset_n, // global_reset_reset_sink.reset_n
input wire [4095:0] hps_to_emif, // hps_emif_conduit_end.hps_to_emif
output wire [4095:0] emif_to_hps, // .emif_to_hps
input wire [1:0] hps_to_emif_gp, // .gp_to_emif
output wire [0:0] emif_to_hps_gp, // .emif_to_gp
output wire [0:0] mem_ck, // mem_conduit_end.mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [16:0] mem_a, // .mem_a
output wire [0:0] mem_act_n, // .mem_act_n
output wire [1:0] mem_ba, // .mem_ba
output wire [0:0] mem_bg, // .mem_bg
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [0:0] mem_odt, // .mem_odt
output wire [0:0] mem_reset_n, // .mem_reset_n
output wire [0:0] mem_par, // .mem_par
input wire [0:0] mem_alert_n, // .mem_alert_n
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dbi_n, // .mem_dbi_n
input wire oct_rzqin, // oct_conduit_end.oct_rzqin
input wire pll_ref_clk // pll_ref_clk_clock_sink.clk
);
endmodule |
module ghrd_10as066n2_rst_in (
input wire clk, // clk.clk
input wire in_reset_n, // in_reset.reset_n
output wire out_reset_n // out_reset.reset_n
);
endmodule |
module ghrd_10as066n2_button_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.export
output wire irq, // irq.irq
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
endmodule |
module ghrd_10as066n2_axi_bridge_0 #(
parameter USE_PIPELINE = 1,
parameter USE_M0_AWID = 1,
parameter USE_M0_AWREGION = 1,
parameter USE_M0_AWLEN = 1,
parameter USE_M0_AWSIZE = 1,
parameter USE_M0_AWBURST = 1,
parameter USE_M0_AWLOCK = 1,
parameter USE_M0_AWCACHE = 1,
parameter USE_M0_AWQOS = 1,
parameter USE_S0_AWREGION = 1,
parameter USE_S0_AWLOCK = 1,
parameter USE_S0_AWCACHE = 1,
parameter USE_S0_AWQOS = 1,
parameter USE_S0_AWPROT = 1,
parameter USE_M0_WSTRB = 1,
parameter USE_S0_WLAST = 1,
parameter USE_M0_BID = 1,
parameter USE_M0_BRESP = 1,
parameter USE_S0_BRESP = 1,
parameter USE_M0_ARID = 1,
parameter USE_M0_ARREGION = 1,
parameter USE_M0_ARLEN = 1,
parameter USE_M0_ARSIZE = 1,
parameter USE_M0_ARBURST = 1,
parameter USE_M0_ARLOCK = 1,
parameter USE_M0_ARCACHE = 1,
parameter USE_M0_ARQOS = 1,
parameter USE_S0_ARREGION = 1,
parameter USE_S0_ARLOCK = 1,
parameter USE_S0_ARCACHE = 1,
parameter USE_S0_ARQOS = 1,
parameter USE_S0_ARPROT = 1,
parameter USE_M0_RID = 1,
parameter USE_M0_RRESP = 1,
parameter USE_M0_RLAST = 1,
parameter USE_S0_RRESP = 1,
parameter M0_ID_WIDTH = 3,
parameter S0_ID_WIDTH = 6,
parameter DATA_WIDTH = 512,
parameter WRITE_ADDR_USER_WIDTH = 32,
parameter READ_ADDR_USER_WIDTH = 32,
parameter WRITE_DATA_USER_WIDTH = 32,
parameter WRITE_RESP_USER_WIDTH = 32,
parameter READ_DATA_USER_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter USE_S0_AWUSER = 0,
parameter USE_S0_ARUSER = 0,
parameter USE_S0_WUSER = 0,
parameter USE_S0_RUSER = 0,
parameter USE_S0_BUSER = 0,
parameter USE_M0_AWUSER = 0,
parameter USE_M0_ARUSER = 0,
parameter USE_M0_WUSER = 0,
parameter USE_M0_RUSER = 0,
parameter USE_M0_BUSER = 0,
parameter AXI_VERSION = "AXI4"
) (
input wire aclk, // clk.clk
input wire aresetn, // clk_reset.reset_n
output wire [2:0] m0_awid, // m0.awid
output wire [31:0] m0_awaddr, // .awaddr
output wire [7:0] m0_awlen, // .awlen
output wire [2:0] m0_awsize, // .awsize
output wire [1:0] m0_awburst, // .awburst
output wire [0:0] m0_awlock, // .awlock
output wire [3:0] m0_awcache, // .awcache
output wire [2:0] m0_awprot, // .awprot
output wire [3:0] m0_awqos, // .awqos
output wire [3:0] m0_awregion, // .awregion
output wire m0_awvalid, // .awvalid
input wire m0_awready, // .awready
output wire [511:0] m0_wdata, // .wdata
output wire [63:0] m0_wstrb, // .wstrb
output wire m0_wlast, // .wlast
output wire m0_wvalid, // .wvalid
input wire m0_wready, // .wready
input wire [2:0] m0_bid, // .bid
input wire [1:0] m0_bresp, // .bresp
input wire m0_bvalid, // .bvalid
output wire m0_bready, // .bready
output wire [2:0] m0_arid, // .arid
output wire [31:0] m0_araddr, // .araddr
output wire [7:0] m0_arlen, // .arlen
output wire [2:0] m0_arsize, // .arsize
output wire [1:0] m0_arburst, // .arburst
output wire [0:0] m0_arlock, // .arlock
output wire [3:0] m0_arcache, // .arcache
output wire [2:0] m0_arprot, // .arprot
output wire [3:0] m0_arqos, // .arqos
output wire [3:0] m0_arregion, // .arregion
output wire m0_arvalid, // .arvalid
input wire m0_arready, // .arready
input wire [2:0] m0_rid, // .rid
input wire [511:0] m0_rdata, // .rdata
input wire [1:0] m0_rresp, // .rresp
input wire m0_rlast, // .rlast
input wire m0_rvalid, // .rvalid
output wire m0_rready, // .rready
input wire [5:0] s0_awid, // s0.awid
input wire [31:0] s0_awaddr, // .awaddr
input wire [7:0] s0_awlen, // .awlen
input wire [2:0] s0_awsize, // .awsize
input wire [1:0] s0_awburst, // .awburst
input wire [0:0] s0_awlock, // .awlock
input wire [3:0] s0_awcache, // .awcache
input wire [2:0] s0_awprot, // .awprot
input wire [3:0] s0_awqos, // .awqos
input wire [3:0] s0_awregion, // .awregion
input wire s0_awvalid, // .awvalid
output wire s0_awready, // .awready
input wire [511:0] s0_wdata, // .wdata
input wire [63:0] s0_wstrb, // .wstrb
input wire s0_wlast, // .wlast
input wire s0_wvalid, // .wvalid
output wire s0_wready, // .wready
output wire [5:0] s0_bid, // .bid
output wire [1:0] s0_bresp, // .bresp
output wire s0_bvalid, // .bvalid
input wire s0_bready, // .bready
input wire [5:0] s0_arid, // .arid
input wire [31:0] s0_araddr, // .araddr
input wire [7:0] s0_arlen, // .arlen
input wire [2:0] s0_arsize, // .arsize
input wire [1:0] s0_arburst, // .arburst
input wire [0:0] s0_arlock, // .arlock
input wire [3:0] s0_arcache, // .arcache
input wire [2:0] s0_arprot, // .arprot
input wire [3:0] s0_arqos, // .arqos
input wire [3:0] s0_arregion, // .arregion
input wire s0_arvalid, // .arvalid
output wire s0_arready, // .arready
output wire [5:0] s0_rid, // .rid
output wire [511:0] s0_rdata, // .rdata
output wire [1:0] s0_rresp, // .rresp
output wire s0_rlast, // .rlast
output wire s0_rvalid, // .rvalid
input wire s0_rready // .rready
);
endmodule |
module ghrd_10as066n2_f2sdram2_m (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
endmodule |
module ghrd_10as066n2_ocm_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [17:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [7:0] readdata, // .readdata
input wire [7:0] writedata // .writedata
);
endmodule |
module ghrd_10as066n2_rst_bdg (
input wire clk, // clk.clk
input wire in_reset, // in_reset.reset
output wire out_reset // out_reset.reset
);
endmodule |
module ghrd_10as066n2_ILC (
input wire [5:0] avmm_addr, // avalon_slave.address
input wire [31:0] avmm_wrdata, // .writedata
input wire avmm_write, // .write
input wire avmm_read, // .read
output wire [31:0] avmm_rddata, // .readdata
input wire clk, // clk.clk
input wire [1:0] irq, // irq.irq
input wire reset_n // reset_n.reset_n
);
endmodule |
module ghrd_10as066n2_avlmm_pr_freeze_bridge_0_altera_avlmm_pr_freeze_bridge_171_bb3qwvq #(
parameter ENABLE_FREEZE_FROM_PR_REGION = 0,
parameter ENABLE_TRAFFIC_TRACKING = 0
) (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire reset_n, // reset_n.reset_n
output wire slv_bridge_to_pr_read, // slv_bridge_to_pr.read
input wire slv_bridge_to_pr_waitrequest, // .waitrequest
output wire slv_bridge_to_pr_write, // .write
output wire [9:0] slv_bridge_to_pr_address, // .address
output wire [3:0] slv_bridge_to_pr_byteenable, // .byteenable
output wire [31:0] slv_bridge_to_pr_writedata, // .writedata
input wire [31:0] slv_bridge_to_pr_readdata, // .readdata
output wire [2:0] slv_bridge_to_pr_burstcount, // .burstcount
input wire slv_bridge_to_pr_readdatavalid, // .readdatavalid
output wire slv_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
output wire slv_bridge_to_pr_debugaccess, // .debugaccess
input wire [1:0] slv_bridge_to_pr_response, // .response
output wire slv_bridge_to_pr_lock, // .lock
input wire slv_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
input wire slv_bridge_to_sr_read, // slv_bridge_to_sr.read
output wire slv_bridge_to_sr_waitrequest, // .waitrequest
input wire slv_bridge_to_sr_write, // .write
input wire [9:0] slv_bridge_to_sr_address, // .address
input wire [3:0] slv_bridge_to_sr_byteenable, // .byteenable
input wire [31:0] slv_bridge_to_sr_writedata, // .writedata
output wire [31:0] slv_bridge_to_sr_readdata, // .readdata
input wire [2:0] slv_bridge_to_sr_burstcount, // .burstcount
output wire slv_bridge_to_sr_readdatavalid, // .readdatavalid
input wire slv_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
input wire slv_bridge_to_sr_debugaccess, // .debugaccess
output wire [1:0] slv_bridge_to_sr_response, // .response
input wire slv_bridge_to_sr_lock, // .lock
output wire slv_bridge_to_sr_writeresponsevalid // .writeresponsevalid
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (ENABLE_FREEZE_FROM_PR_REGION != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_freeze_from_pr_region_check ( .error(1'b1) );
end
if (ENABLE_TRAFFIC_TRACKING != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_traffic_tracking_check ( .error(1'b1) );
end
endgenerate
altera_avlmm_slv_freeze_bridge #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0),
.ENABLED_BACKPRESSURE_BRIDGE (0),
.USE_BURSTCOUNT (1),
.USE_READ_DATA_VALID (1),
.USE_READ_WAIT_TIME (0),
.USE_WRITE_WAIT_TIME (0),
.USE_WRRESPONSEVALID (1),
.SLV_BRIDGE_ADDR_WIDTH (10),
.SLV_BRIDGE_BYTEEN_WIDTH (4),
.SLV_BRIDGE_MAX_RDTRANS_WIDTH (3),
.SLV_BRIDGE_MAX_WRTRANS_WIDTH (3),
.SLV_BRIDGE_RWT_WIDTH (1),
.SLV_BRIDGE_WWT_WIDTH (1),
.SLV_BRIDGE_FIX_RDLATENCY_WIDTH (1),
.SLV_BRIDGE_BURSTCOUNT_WIDTH (3),
.SLV_BRIDGE_WRDATA_WIDTH (32),
.SLV_BRIDGE_RDDATA_WIDTH (32),
.SLV_BRIDGE_FIX_READ_LATENCY (0),
.SLV_BRIDGE_READ_WAIT_TIME (1),
.SLV_BRIDGE_WRITE_WAIT_TIME (0)
) avlmm_slv_freeze_bridge (
.clk (clock), // input, width = 1, clock_sink.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.freeze (freeze_conduit_freeze), // input, width = 1, freeze_conduit.freeze
.illegal_request (freeze_conduit_illegal_request), // output, width = 1, .illegal_request
.slv_bridge_to_pr_read (slv_bridge_to_pr_read), // output, width = 1, slv_bridge_to_pr.read
.slv_bridge_to_pr_waitrequest (slv_bridge_to_pr_waitrequest), // input, width = 1, .waitrequest
.slv_bridge_to_pr_write (slv_bridge_to_pr_write), // output, width = 1, .write
.slv_bridge_to_pr_addr (slv_bridge_to_pr_address), // output, width = 10, .address
.slv_bridge_to_pr_byteenable (slv_bridge_to_pr_byteenable), // output, width = 4, .byteenable
.slv_bridge_to_pr_wrdata (slv_bridge_to_pr_writedata), // output, width = 32, .writedata
.slv_bridge_to_pr_rddata (slv_bridge_to_pr_readdata), // input, width = 32, .readdata
.slv_bridge_to_pr_burstcount (slv_bridge_to_pr_burstcount), // output, width = 3, .burstcount
.slv_bridge_to_pr_rddata_valid (slv_bridge_to_pr_readdatavalid), // input, width = 1, .readdatavalid
.slv_bridge_to_pr_beginbursttransfer (slv_bridge_to_pr_beginbursttransfer), // output, width = 1, .beginbursttransfer
.slv_bridge_to_pr_debugaccess (slv_bridge_to_pr_debugaccess), // output, width = 1, .debugaccess
.slv_bridge_to_pr_response (slv_bridge_to_pr_response), // input, width = 2, .response
.slv_bridge_to_pr_lock (slv_bridge_to_pr_lock), // output, width = 1, .lock
.slv_bridge_to_pr_writeresponsevalid (slv_bridge_to_pr_writeresponsevalid), // input, width = 1, .writeresponsevalid
.slv_bridge_to_sr_read (slv_bridge_to_sr_read), // input, width = 1, slv_bridge_to_sr.read
.slv_bridge_to_sr_waitrequest (slv_bridge_to_sr_waitrequest), // output, width = 1, .waitrequest
.slv_bridge_to_sr_write (slv_bridge_to_sr_write), // input, width = 1, .write
.slv_bridge_to_sr_addr (slv_bridge_to_sr_address), // input, width = 10, .address
.slv_bridge_to_sr_byteenable (slv_bridge_to_sr_byteenable), // input, width = 4, .byteenable
.slv_bridge_to_sr_wrdata (slv_bridge_to_sr_writedata), // input, width = 32, .writedata
.slv_bridge_to_sr_rddata (slv_bridge_to_sr_readdata), // output, width = 32, .readdata
.slv_bridge_to_sr_burstcount (slv_bridge_to_sr_burstcount), // input, width = 3, .burstcount
.slv_bridge_to_sr_rddata_valid (slv_bridge_to_sr_readdatavalid), // output, width = 1, .readdatavalid
.slv_bridge_to_sr_beginbursttransfer (slv_bridge_to_sr_beginbursttransfer), // input, width = 1, .beginbursttransfer
.slv_bridge_to_sr_debugaccess (slv_bridge_to_sr_debugaccess), // input, width = 1, .debugaccess
.slv_bridge_to_sr_response (slv_bridge_to_sr_response), // output, width = 2, .response
.slv_bridge_to_sr_lock (slv_bridge_to_sr_lock), // input, width = 1, .lock
.slv_bridge_to_sr_writeresponsevalid (slv_bridge_to_sr_writeresponsevalid), // output, width = 1, .writeresponsevalid
.pr_freeze (1'b0) // (terminated),
);
endmodule |
module ghrd_10as066n2_led_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.in_port
output wire [3:0] out_port, // .out_port
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa led_pio (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.out_port (out_port) // output, width = 4, .export
);
endmodule |
module ghrd_10as066n2_led_pio_altera_avalon_pio_171_yz2rppa (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 3: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire [ 3: 0] data_in;
reg [ 3: 0] data_out;
wire [ 3: 0] out_port;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign out_port = data_out;
assign data_in = in_port;
endmodule |
module ghrd_10as066n2_issp_0 (
input wire source_clk, // source_clk.clk
output wire [2:0] source // sources.source
);
altsource_probe_top #(
.sld_auto_instance_index ("YES"),
.sld_instance_index (0),
.instance_id ("RST"),
.probe_width (0),
.source_width (3),
.source_initial_value ("0"),
.enable_metastability ("YES")
) issp_0 (
.source (source), // output, width = 3, sources.source
.source_clk (source_clk), // input, width = 1, source_clk.clk
.source_ena (1'b1) // (terminated),
);
endmodule |
module altsource_probe_top
#(
parameter lpm_type = "altsource_probe", // required by the coding standard
parameter lpm_hint = "UNUSED", // required by the coding standard
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance.
parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
parameter sld_ir_width = 4,
parameter instance_id = "UNUSED", // optional name for the instance.
parameter probe_width = 1, // probe port width
parameter source_width= 1, // source port width
parameter source_initial_value = "0", // initial source port value
parameter enable_metastability = "NO" // yes to add two register
)
(
input [probe_width - 1 : 0] probe, // probe inputs
output [source_width - 1 : 0] source, // source outputs
input source_clk, // clock of the registers used to metastabilize the source output
input tri1 source_ena // enable of the registers used to metastabilize the source output
);
altsource_probe #(
.lpm_type(lpm_type),
.lpm_hint(lpm_hint),
.sld_auto_instance_index(sld_auto_instance_index),
.sld_instance_index(sld_instance_index),
.SLD_NODE_INFO(sld_node_info_parameter),
.sld_ir_width(sld_ir_width),
.instance_id(instance_id),
.probe_width(probe_width),
.source_width(source_width),
.source_initial_value(source_initial_value),
.enable_metastability(enable_metastability)
)issp_impl
(
.probe(probe),
.source(source),
.source_clk(source_clk),
.source_ena(source_ena)
);
endmodule |
module ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
wire freeze_control_freeze_if_freeze_in; // freeze_control:freeze -> conduit_merger:freeze_in
wire [1:0] conduit_merger_conduit_ctrl_if_illegal_request_out; // conduit_merger:illegal_request_out -> freeze_control:illegal_request
wire [1:0] freeze_control_conduit_control_illegal_req; // freeze_control:illegal_req -> freeze_csr:illegal_req
wire freeze_csr_conduit_control_freeze_req; // freeze_csr:freeze_req -> freeze_control:freeze_req
wire freeze_csr_conduit_control_unfreeze_req; // freeze_csr:unfreeze_req -> freeze_control:unfreeze_req
wire freeze_control_conduit_control_unfreeze_status; // freeze_control:unfreeze_status -> freeze_csr:unfreeze_status
wire freeze_csr_conduit_control_reset; // freeze_csr:reset_req -> freeze_control:reset_req
wire freeze_control_conduit_control_freeze_status; // freeze_control:freeze_status -> freeze_csr:freeze_status
altera_freeze_control #(
.NUM_INTF_BRIDGE (2)
) freeze_control (
.clk (clock_clk), // input, width = 1, clock_sink.clk
.reset_n (~reset_reset), // input, width = 1, reset.reset_n
.start_req (pr_handshake_start_req), // output, width = 1, pr_handshake.start_req
.start_ack (pr_handshake_start_ack), // input, width = 1, .start_ack
.stop_req (pr_handshake_stop_req), // output, width = 1, .stop_req
.stop_ack (pr_handshake_stop_ack), // input, width = 1, .stop_ack
.freeze_status (freeze_control_conduit_control_freeze_status), // output, width = 1, conduit_control.freeze_status
.freeze_req (freeze_csr_conduit_control_freeze_req), // input, width = 1, .freeze_req
.unfreeze_req (freeze_csr_conduit_control_unfreeze_req), // input, width = 1, .unfreeze_req
.unfreeze_status (freeze_control_conduit_control_unfreeze_status), // output, width = 1, .unfreeze_status
.reset_req (freeze_csr_conduit_control_reset), // input, width = 1, .reset
.illegal_req (freeze_control_conduit_control_illegal_req), // output, width = 2, .illegal_req
.freeze (freeze_control_freeze_if_freeze_in), // output, width = 1, freeze_if.freeze_in
.illegal_request (conduit_merger_conduit_ctrl_if_illegal_request_out), // input, width = 2, .illegal_request_out
.region_reset (reset_source_reset) // output, width = 1, reset_source.reset
);
ghrd_10as066n2_pr_region_controller_0_altera_conduit_merger_171_nva7cjy #(
.NUM_INTF_BRIDGE (2)
) conduit_merger (
.freeze_in (freeze_control_freeze_if_freeze_in), // input, width = 1, conduit_ctrl_if.freeze_in
.illegal_request_out (conduit_merger_conduit_ctrl_if_illegal_request_out), // output, width = 2, .illegal_request_out
.freeze0 (bridge_freeze0_freeze), // output, width = 1, conduit_bridge_if0.freeze
.illegal_request0 (bridge_freeze0_illegal_request), // input, width = 1, .illegal_request
.freeze1 (bridge_freeze1_freeze), // output, width = 1, conduit_bridge_if1.freeze
.illegal_request1 (bridge_freeze1_illegal_request), // input, width = 1, .illegal_request
.pr_freeze0 () // (terminated),
);
altera_freeze_csr #(
.NUM_INTF_BRIDGE (2)
) freeze_csr (
.clk (clock_clk), // input, width = 1, clock_sink.clk
.reset_n (~reset_reset), // input, width = 1, reset.reset_n
.avl_csr_read (avl_csr_read), // input, width = 1, avl_csr.read
.avl_csr_write (avl_csr_write), // input, width = 1, .write
.avl_csr_addr (avl_csr_address), // input, width = 2, .address
.avl_csr_wrdata (avl_csr_writedata), // input, width = 32, .writedata
.avl_csr_rddata (avl_csr_readdata), // output, width = 32, .readdata
.freeze_status (freeze_control_conduit_control_freeze_status), // input, width = 1, conduit_control.freeze_status
.freeze_req (freeze_csr_conduit_control_freeze_req), // output, width = 1, .freeze_req
.unfreeze_req (freeze_csr_conduit_control_unfreeze_req), // output, width = 1, .unfreeze_req
.reset_req (freeze_csr_conduit_control_reset), // output, width = 1, .reset
.unfreeze_status (freeze_control_conduit_control_unfreeze_status), // input, width = 1, .unfreeze_status
.illegal_req (freeze_control_conduit_control_illegal_req), // input, width = 2, .illegal_req
.irq () // (terminated),
);
endmodule |
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1_altera_avlmm_pr_freeze_bridge_171_yvsimhi #(
parameter ENABLE_FREEZE_FROM_PR_REGION = 0,
parameter ENABLE_TRAFFIC_TRACKING = 0
) (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire mst_bridge_to_pr_read, // mst_bridge_to_pr.read
output wire mst_bridge_to_pr_waitrequest, // .waitrequest
input wire mst_bridge_to_pr_write, // .write
input wire [31:0] mst_bridge_to_pr_address, // .address
input wire [3:0] mst_bridge_to_pr_byteenable, // .byteenable
input wire [31:0] mst_bridge_to_pr_writedata, // .writedata
output wire [31:0] mst_bridge_to_pr_readdata, // .readdata
input wire [2:0] mst_bridge_to_pr_burstcount, // .burstcount
output wire mst_bridge_to_pr_readdatavalid, // .readdatavalid
input wire mst_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
input wire mst_bridge_to_pr_debugaccess, // .debugaccess
output wire [1:0] mst_bridge_to_pr_response, // .response
input wire mst_bridge_to_pr_lock, // .lock
output wire mst_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
output wire mst_bridge_to_sr_read, // mst_bridge_to_sr.read
input wire mst_bridge_to_sr_waitrequest, // .waitrequest
output wire mst_bridge_to_sr_write, // .write
output wire [31:0] mst_bridge_to_sr_address, // .address
output wire [3:0] mst_bridge_to_sr_byteenable, // .byteenable
output wire [31:0] mst_bridge_to_sr_writedata, // .writedata
input wire [31:0] mst_bridge_to_sr_readdata, // .readdata
output wire [2:0] mst_bridge_to_sr_burstcount, // .burstcount
input wire mst_bridge_to_sr_readdatavalid, // .readdatavalid
output wire mst_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
output wire mst_bridge_to_sr_debugaccess, // .debugaccess
input wire [1:0] mst_bridge_to_sr_response, // .response
output wire mst_bridge_to_sr_lock, // .lock
input wire mst_bridge_to_sr_writeresponsevalid, // .writeresponsevalid
input wire reset_n // reset_n.reset_n
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (ENABLE_FREEZE_FROM_PR_REGION != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_freeze_from_pr_region_check ( .error(1'b1) );
end
if (ENABLE_TRAFFIC_TRACKING != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
enable_traffic_tracking_check ( .error(1'b1) );
end
endgenerate
altera_avlmm_mst_freeze_bridge #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0),
.USE_BURSTCOUNT (1),
.USE_READ_WAIT_TIME (0),
.USE_WRITE_WAIT_TIME (0),
.MST_BRIDGE_ADDR_WIDTH (32),
.MST_BRIDGE_BYTEEN_WIDTH (4),
.MST_BRIDGE_BURSTCOUNT_WIDTH (3),
.MST_BRIDGE_RWT_WIDTH (1),
.MST_BRIDGE_WWT_WIDTH (1),
.MST_BRIDGE_WRDATA_WIDTH (32),
.MST_BRIDGE_RDDATA_WIDTH (32),
.MST_BRIDGE_READ_WAIT_TIME (1),
.MST_BRIDGE_WRITE_WAIT_TIME (0)
) avlmm_mst_freeze_bridge (
.clk (clock), // input, width = 1, clock_sink.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.freeze (freeze_conduit_freeze), // input, width = 1, freeze_conduit.freeze
.illegal_request (freeze_conduit_illegal_request), // output, width = 1, .illegal_request
.mst_bridge_to_pr_read (mst_bridge_to_pr_read), // input, width = 1, mst_bridge_to_pr.read
.mst_bridge_to_pr_waitrequest (mst_bridge_to_pr_waitrequest), // output, width = 1, .waitrequest
.mst_bridge_to_pr_write (mst_bridge_to_pr_write), // input, width = 1, .write
.mst_bridge_to_pr_addr (mst_bridge_to_pr_address), // input, width = 32, .address
.mst_bridge_to_pr_byteenable (mst_bridge_to_pr_byteenable), // input, width = 4, .byteenable
.mst_bridge_to_pr_wrdata (mst_bridge_to_pr_writedata), // input, width = 32, .writedata
.mst_bridge_to_pr_rddata (mst_bridge_to_pr_readdata), // output, width = 32, .readdata
.mst_bridge_to_pr_burstcount (mst_bridge_to_pr_burstcount), // input, width = 3, .burstcount
.mst_bridge_to_pr_rddata_valid (mst_bridge_to_pr_readdatavalid), // output, width = 1, .readdatavalid
.mst_bridge_to_pr_beginbursttransfer (mst_bridge_to_pr_beginbursttransfer), // input, width = 1, .beginbursttransfer
.mst_bridge_to_pr_debugaccess (mst_bridge_to_pr_debugaccess), // input, width = 1, .debugaccess
.mst_bridge_to_pr_response (mst_bridge_to_pr_response), // output, width = 2, .response
.mst_bridge_to_pr_lock (mst_bridge_to_pr_lock), // input, width = 1, .lock
.mst_bridge_to_pr_writeresponsevalid (mst_bridge_to_pr_writeresponsevalid), // output, width = 1, .writeresponsevalid
.mst_bridge_to_sr_read (mst_bridge_to_sr_read), // output, width = 1, mst_bridge_to_sr.read
.mst_bridge_to_sr_waitrequest (mst_bridge_to_sr_waitrequest), // input, width = 1, .waitrequest
.mst_bridge_to_sr_write (mst_bridge_to_sr_write), // output, width = 1, .write
.mst_bridge_to_sr_addr (mst_bridge_to_sr_address), // output, width = 32, .address
.mst_bridge_to_sr_byteenable (mst_bridge_to_sr_byteenable), // output, width = 4, .byteenable
.mst_bridge_to_sr_wrdata (mst_bridge_to_sr_writedata), // output, width = 32, .writedata
.mst_bridge_to_sr_rddata (mst_bridge_to_sr_readdata), // input, width = 32, .readdata
.mst_bridge_to_sr_burstcount (mst_bridge_to_sr_burstcount), // output, width = 3, .burstcount
.mst_bridge_to_sr_rddata_valid (mst_bridge_to_sr_readdatavalid), // input, width = 1, .readdatavalid
.mst_bridge_to_sr_beginbursttransfer (mst_bridge_to_sr_beginbursttransfer), // output, width = 1, .beginbursttransfer
.mst_bridge_to_sr_debugaccess (mst_bridge_to_sr_debugaccess), // output, width = 1, .debugaccess
.mst_bridge_to_sr_response (mst_bridge_to_sr_response), // input, width = 2, .response
.mst_bridge_to_sr_lock (mst_bridge_to_sr_lock), // output, width = 1, .lock
.mst_bridge_to_sr_writeresponsevalid (mst_bridge_to_sr_writeresponsevalid), // input, width = 1, .writeresponsevalid
.pr_freeze (1'b0) // (terminated),
);
endmodule |
module ghrd_10as066n2_emif_hps (
input wire global_reset_n, // global_reset_reset_sink.reset_n
input wire [4095:0] hps_to_emif, // hps_emif_conduit_end.hps_to_emif
output wire [4095:0] emif_to_hps, // .emif_to_hps
input wire [1:0] hps_to_emif_gp, // .gp_to_emif
output wire [0:0] emif_to_hps_gp, // .emif_to_gp
output wire [0:0] mem_ck, // mem_conduit_end.mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [16:0] mem_a, // .mem_a
output wire [0:0] mem_act_n, // .mem_act_n
output wire [1:0] mem_ba, // .mem_ba
output wire [0:0] mem_bg, // .mem_bg
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [0:0] mem_odt, // .mem_odt
output wire [0:0] mem_reset_n, // .mem_reset_n
output wire [0:0] mem_par, // .mem_par
input wire [0:0] mem_alert_n, // .mem_alert_n
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dbi_n, // .mem_dbi_n
input wire oct_rzqin, // oct_conduit_end.oct_rzqin
input wire pll_ref_clk // pll_ref_clk_clock_sink.clk
);
ghrd_10as066n2_emif_hps_altera_emif_a10_hps_171_or5co3i emif_hps (
.global_reset_n (global_reset_n), // input, width = 1, global_reset_reset_sink.reset_n
.hps_to_emif (hps_to_emif), // input, width = 4096, hps_emif_conduit_end.hps_to_emif
.emif_to_hps (emif_to_hps), // output, width = 4096, .emif_to_hps
.hps_to_emif_gp (hps_to_emif_gp), // input, width = 2, .gp_to_emif
.emif_to_hps_gp (emif_to_hps_gp), // output, width = 1, .emif_to_gp
.mem_ck (mem_ck), // output, width = 1, mem_conduit_end.mem_ck
.mem_ck_n (mem_ck_n), // output, width = 1, .mem_ck_n
.mem_a (mem_a), // output, width = 17, .mem_a
.mem_act_n (mem_act_n), // output, width = 1, .mem_act_n
.mem_ba (mem_ba), // output, width = 2, .mem_ba
.mem_bg (mem_bg), // output, width = 1, .mem_bg
.mem_cke (mem_cke), // output, width = 1, .mem_cke
.mem_cs_n (mem_cs_n), // output, width = 1, .mem_cs_n
.mem_odt (mem_odt), // output, width = 1, .mem_odt
.mem_reset_n (mem_reset_n), // output, width = 1, .mem_reset_n
.mem_par (mem_par), // output, width = 1, .mem_par
.mem_alert_n (mem_alert_n), // input, width = 1, .mem_alert_n
.mem_dqs (mem_dqs), // inout, width = 4, .mem_dqs
.mem_dqs_n (mem_dqs_n), // inout, width = 4, .mem_dqs_n
.mem_dq (mem_dq), // inout, width = 32, .mem_dq
.mem_dbi_n (mem_dbi_n), // inout, width = 4, .mem_dbi_n
.oct_rzqin (oct_rzqin), // input, width = 1, oct_conduit_end.oct_rzqin
.pll_ref_clk (pll_ref_clk) // input, width = 1, pll_ref_clk_clock_sink.clk
);
endmodule |
module ghrd_10as066n2_button_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.export
output wire irq, // irq.irq
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
ghrd_10as066n2_button_pio_altera_avalon_pio_171_3t26uui button_pio (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.irq (irq) // output, width = 1, irq.irq
);
endmodule |
module ghrd_10as066n2_f2sdram2_m (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) f2sdram2_m (
.clk_clk (clk_clk), // input, width = 1, clk.clk
.clk_reset_reset (clk_reset_reset), // input, width = 1, clk_reset.reset
.master_address (master_address), // output, width = 32, master.address
.master_readdata (master_readdata), // input, width = 32, .readdata
.master_read (master_read), // output, width = 1, .read
.master_write (master_write), // output, width = 1, .write
.master_writedata (master_writedata), // output, width = 32, .writedata
.master_waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.master_readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.master_byteenable (master_byteenable), // output, width = 4, .byteenable
.master_reset_reset (master_reset_reset) // output, width = 1, master_reset.reset
);
endmodule |
module ghrd_10as066n2_sys_id (
input wire clock, // clk.clk
output wire [31:0] readdata, // control_slave.readdata
input wire address, // .address
input wire reset_n // reset.reset_n
);
altera_avalon_sysid_qsys #(
.ID_VALUE (-1073195008),
.TIMESTAMP (1509046992)
) sys_id (
.clock (clock), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.readdata (readdata), // output, width = 32, control_slave.readdata
.address (address) // input, width = 1, .address
);
endmodule |
module ghrd_10as066n2_ocm_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [17:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [7:0] readdata, // .readdata
input wire [7:0] writedata // .writedata
);
ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii ocm_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 18, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 8, .readdata
.writedata (writedata), // input, width = 8, .writedata
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule |
module ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii (
// inputs:
address,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "ghrd_10as066n2_ocm_0_ocm_0.hex";
output [ 7: 0] readdata;
input [ 17: 0] address;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 7: 0] writedata;
wire clocken0;
wire [ 7: 0] readdata;
wire wren;
assign wren = chipselect & write & clken;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 262144,
the_altsyncram.numwords_a = 262144,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 8,
the_altsyncram.widthad_a = 18;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule |
module ghrd_10as066n2_dipsw_pio (
input wire clk, // clk.clk
input wire [3:0] in_port, // external_connection.export
output wire irq, // irq.irq
input wire reset_n, // reset.reset_n
input wire [1:0] address, // s1.address
input wire write_n, // .write_n
input wire [31:0] writedata, // .writedata
input wire chipselect, // .chipselect
output wire [31:0] readdata // .readdata
);
ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq dipsw_pio (
.clk (clk), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.address (address), // input, width = 2, s1.address
.write_n (write_n), // input, width = 1, .write_n
.writedata (writedata), // input, width = 32, .writedata
.chipselect (chipselect), // input, width = 1, .chipselect
.readdata (readdata), // output, width = 32, .readdata
.in_port (in_port), // input, width = 4, external_connection.export
.irq (irq) // output, width = 1, irq.irq
);
endmodule |
module ghrd_10as066n2_ILC (
input wire [5:0] avmm_addr, // avalon_slave.address
input wire [31:0] avmm_wrdata, // .writedata
input wire avmm_write, // .write
input wire avmm_read, // .read
output wire [31:0] avmm_rddata, // .readdata
input wire clk, // clk.clk
input wire [1:0] irq, // irq.irq
input wire reset_n // reset_n.reset_n
);
interrupt_latency_counter #(
.INTR_TYPE (0),
.CLOCK_RATE (100000000),
.IRQ_PORT_CNT (2)
) ilc (
.reset_n (reset_n), // input, width = 1, reset_n.reset_n
.clk (clk), // input, width = 1, clk.clk
.irq (irq), // input, width = 2, irq.irq
.avmm_addr (avmm_addr), // input, width = 6, avalon_slave.address
.avmm_wrdata (avmm_wrdata), // input, width = 32, .writedata
.avmm_write (avmm_write), // input, width = 1, .write
.avmm_read (avmm_read), // input, width = 1, .read
.avmm_rddata (avmm_rddata) // output, width = 32, .readdata
);
endmodule |
module Computer_System (
expansion_jp1_export,
expansion_jp2_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO40,
hps_io_hps_io_gpio_inst_GPIO41,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
pushbuttons_export,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
sdram_clk_clk,
slider_switches_export,
system_pll_ref_clk_clk,
system_pll_ref_reset_reset,
vga_CLK,
vga_HS,
vga_VS,
vga_BLANK,
vga_SYNC,
vga_R,
vga_G,
vga_B,
vga_pll_ref_clk_clk,
vga_pll_ref_reset_reset,
video_in_TD_CLK27,
video_in_TD_DATA,
video_in_TD_HS,
video_in_TD_VS,
video_in_clk27_reset,
video_in_TD_RESET,
video_in_overflow_flag);
inout [31:0] expansion_jp1_export;
inout [31:0] expansion_jp2_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO40;
inout hps_io_hps_io_gpio_inst_GPIO41;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input [3:0] pushbuttons_export;
output [12:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [15:0] sdram_dq;
output [1:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output sdram_clk_clk;
input [9:0] slider_switches_export;
input system_pll_ref_clk_clk;
input system_pll_ref_reset_reset;
output vga_CLK;
output vga_HS;
output vga_VS;
output vga_BLANK;
output vga_SYNC;
output [7:0] vga_R;
output [7:0] vga_G;
output [7:0] vga_B;
input vga_pll_ref_clk_clk;
input vga_pll_ref_reset_reset;
input video_in_TD_CLK27;
input [7:0] video_in_TD_DATA;
input video_in_TD_HS;
input video_in_TD_VS;
input video_in_clk27_reset;
output video_in_TD_RESET;
output video_in_overflow_flag;
endmodule |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Splitter (
// Inputs
clk,
reset,
sync_ready,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready_0,
stream_out_ready_1,
stream_select,
// Bidirectional
// Outputs
sync_data,
sync_valid,
stream_in_ready,
stream_out_data_0,
stream_out_startofpacket_0,
stream_out_endofpacket_0,
stream_out_empty_0,
stream_out_valid_0,
stream_out_data_1,
stream_out_startofpacket_1,
stream_out_endofpacket_1,
stream_out_empty_1,
stream_out_valid_1
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 23; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input sync_ready;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready_0;
input stream_out_ready_1;
input stream_select;
// Bidirectional
// Outputs
output reg sync_data;
output reg sync_valid;
output stream_in_ready;
output reg [DW: 0] stream_out_data_0;
output reg stream_out_startofpacket_0;
output reg stream_out_endofpacket_0;
output reg [EW: 0] stream_out_empty_0;
output reg stream_out_valid_0;
output reg [DW: 0] stream_out_data_1;
output reg stream_out_startofpacket_1;
output reg stream_out_endofpacket_1;
output reg [EW: 0] stream_out_empty_1;
output reg stream_out_valid_1;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire enable_setting_stream_select;
// Internal Registers
reg between_frames;
reg stream_select_reg;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
sync_data <= 1'b0;
sync_valid <= 1'b0;
end
else if (enable_setting_stream_select)
begin
sync_data <= stream_select;
sync_valid <= 1'b1;
end
else if (sync_ready)
sync_valid <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_0 <= 'h0;
stream_out_startofpacket_0 <= 1'b0;
stream_out_endofpacket_0 <= 1'b0;
stream_out_empty_0 <= 'h0;
stream_out_valid_0 <= 1'b0;
end
else if (stream_in_ready & ~stream_select_reg)
begin
stream_out_data_0 <= stream_in_data;
stream_out_startofpacket_0 <= stream_in_startofpacket;
stream_out_endofpacket_0 <= stream_in_endofpacket;
stream_out_empty_0 <= stream_in_empty;
stream_out_valid_0 <= stream_in_valid;
end
else if (stream_out_ready_0)
stream_out_valid_0 <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_1 <= 'h0;
stream_out_startofpacket_1 <= 1'b0;
stream_out_endofpacket_1 <= 1'b0;
stream_out_empty_1 <= 'h0;
stream_out_valid_1 <= 1'b0;
end
else if (stream_in_ready & stream_select_reg)
begin
stream_out_data_1 <= stream_in_data;
stream_out_startofpacket_1 <= stream_in_startofpacket;
stream_out_endofpacket_1 <= stream_in_endofpacket;
stream_out_empty_1 <= stream_in_empty;
stream_out_valid_1 <= stream_in_valid;
end
else if (stream_out_ready_1)
stream_out_valid_1 <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_endofpacket)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_startofpacket)
between_frames <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
stream_select_reg <= 1'b0;
else if (enable_setting_stream_select)
stream_select_reg <= stream_select;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = (stream_select_reg) ?
stream_in_valid & (~stream_out_valid_1 | stream_out_ready_1) :
stream_in_valid & (~stream_out_valid_0 | stream_out_ready_0);
// Internal Assignments
assign enable_setting_stream_select =
(stream_in_ready & stream_in_endofpacket) |
(~(stream_in_ready & stream_in_startofpacket) & between_frames);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_edge_detection_sobel_operator (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 8: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 9: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 8: 0] shift_reg_out[ 1: 0];
// Internal Registers
reg [ 8: 0] original_line_1[ 2: 0];
reg [ 8: 0] original_line_2[ 2: 0];
reg [ 8: 0] original_line_3[ 2: 0];
reg [11: 0] gx_level_1[ 3: 0];
reg [11: 0] gx_level_2[ 1: 0];
reg [11: 0] gx_level_3;
reg [11: 0] gy_level_1[ 3: 0];
reg [11: 0] gy_level_2[ 1: 0];
reg [11: 0] gy_level_3;
reg [11: 0] gx_magnitude;
reg [11: 0] gy_magnitude;
reg [ 1: 0] gx_sign;
reg [ 1: 0] gy_sign;
reg [11: 0] g_magnitude;
reg gy_over_gx;
reg [ 9: 0] result;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Sobel Operator
//
// [ -1 0 1 ] [ 1 2 1 ]
// Gx [ -2 0 2 ] Gy [ 0 0 0 ]
// [ -1 0 1 ] [ -1 -2 -1 ]
//
// |G| = |Gx| + |Gy|
always @(posedge clk)
begin
if (reset == 1'b1)
begin
for (i = 2; i >= 0; i = i-1)
begin
original_line_1[i] <= 9'h000;
original_line_2[i] <= 9'h000;
original_line_3[i] <= 9'h000;
end
gx_level_1[0] <= 12'h000;
gx_level_1[1] <= 12'h000;
gx_level_1[2] <= 12'h000;
gx_level_1[3] <= 12'h000;
gx_level_2[0] <= 12'h000;
gx_level_2[1] <= 12'h000;
gx_level_3 <= 12'h000;
gy_level_1[0] <= 12'h000;
gy_level_1[1] <= 12'h000;
gy_level_1[2] <= 12'h000;
gy_level_1[3] <= 12'h000;
gy_level_2[0] <= 12'h000;
gy_level_2[1] <= 12'h000;
gy_level_3 <= 12'h000;
gx_magnitude <= 12'h000;
gy_magnitude <= 12'h000;
gx_sign <= 2'h0;
gy_sign <= 2'h0;
g_magnitude <= 12'h000;
gy_over_gx <= 1'b0;
result <= 9'h000;
end
else if (data_en == 1'b1)
begin
for (i = 2; i > 0; i = i-1)
begin
original_line_1[i] <= original_line_1[i-1];
original_line_2[i] <= original_line_2[i-1];
original_line_3[i] <= original_line_3[i-1];
end
original_line_1[0] <= data_in;
original_line_2[0] <= shift_reg_out[0];
original_line_3[0] <= shift_reg_out[1];
// Calculate Gx
gx_level_1[0] <= {3'h0,original_line_1[0]} + {3'h0,original_line_3[0]};
gx_level_1[1] <= {2'h0,original_line_2[0], 1'b0};
gx_level_1[2] <= {3'h0,original_line_1[2]} + {3'h0,original_line_3[2]};
gx_level_1[3] <= {2'h0,original_line_2[2], 1'b0};
gx_level_2[0] <= gx_level_1[0] + gx_level_1[1];
gx_level_2[1] <= gx_level_1[2] + gx_level_1[3];
gx_level_3 <= gx_level_2[0] - gx_level_2[1];
// Calculate Gy
gy_level_1[0] <= {3'h0,original_line_1[0]} + {3'h0,original_line_1[2]};
gy_level_1[1] <= {2'h0,original_line_1[1], 1'b0};
gy_level_1[2] <= {3'h0,original_line_3[0]} + {3'h0,original_line_3[2]};
gy_level_1[3] <= {2'h0,original_line_3[1], 1'b0};
gy_level_2[0] <= gy_level_1[0] + gy_level_1[1];
gy_level_2[1] <= gy_level_1[2] + gy_level_1[3];
gy_level_3 <= gy_level_2[0] - gy_level_2[1];
// Calculate the magnitude and sign of Gx and Gy
gx_magnitude <= (gx_level_3[11]) ? (~gx_level_3) + 12'h001 : gx_level_3;
gy_magnitude <= (gy_level_3[11]) ? (~gy_level_3) + 12'h001 : gy_level_3;
gx_sign <= {gx_sign[0], gx_level_3[11]};
gy_sign <= {gy_sign[0], gy_level_3[11]};
// Calculate the magnitude G
g_magnitude <= gx_magnitude + gy_magnitude;
gy_over_gx <= (gx_magnitude >= gy_magnitude) ? 1'b0 : 1'b1;
// Calculate the final result
result[9] <= gx_sign[1] ^ gy_sign[1];
result[8] <= gx_sign[1] ^ gy_sign[1] ^ gy_over_gx;
result[7:0] <= (g_magnitude[11:10] == 2'h0) ? g_magnitude[9:2] : 8'hFF;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign data_out = result;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_in),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 9,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 9,
shift_register_2.SIZE = WIDTH;
endmodule |
module altera_up_video_ascii_rom_128 (
// Inputs
clk,
clk_en,
character,
x_coordinate,
y_coordinate,
// Bidirectionals
// Outputs
character_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input [ 6: 0] character;
input [ 2: 0] x_coordinate;
input [ 2: 0] y_coordinate;
// Bidirectionals
// Outputs
output reg character_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [12: 0] character_address;
// Internal Registers
reg rom [8191:0];
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
initial
begin
$readmemb("altera_up_video_ascii_rom_128.txt", rom);
end
always @ (posedge clk)
begin
if (clk_en)
character_data <= rom[character_address];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign character_address = {character, y_coordinate, x_coordinate};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_VGA_Pixel_FIFO (
// Inputs
clk_stream_in,
reset_stream_in,
clk_stream_out,
reset_stream_out,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's data width
parameter EW = 0; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk_stream_in;
input reset_stream_in;
input clk_stream_out;
input reset_stream_out;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 6: 0] fifo_wr_used;
wire fifo_empty;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = ~(&(fifo_wr_used[6:4]));
assign stream_out_empty = 'h0;
assign stream_out_valid = ~fifo_empty;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
dcfifo Data_FIFO (
// Inputs
.wrclk (clk_stream_in),
.wrreq (stream_in_ready & stream_in_valid),
.data ({stream_in_data, stream_in_endofpacket, stream_in_startofpacket}),
.rdclk (clk_stream_out),
.rdreq (stream_out_ready & ~fifo_empty),
// Outputs
.wrusedw (fifo_wr_used),
.rdempty (fifo_empty),
.q ({stream_out_data, stream_out_endofpacket, stream_out_startofpacket})
// synopsys translate_off
,
.aclr (),
.wrfull (),
.wrempty (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
Data_FIFO.intended_device_family = "Cyclone II",
Data_FIFO.lpm_hint = "MAXIMIZE_SPEED=7",
Data_FIFO.lpm_numwords = 128,
Data_FIFO.lpm_showahead = "ON",
Data_FIFO.lpm_type = "dcfifo",
Data_FIFO.lpm_width = DW + 3,
Data_FIFO.lpm_widthu = 7,
Data_FIFO.overflow_checking = "OFF",
Data_FIFO.rdsync_delaypipe = 5,
Data_FIFO.underflow_checking = "OFF",
Data_FIFO.use_eab = "ON",
Data_FIFO.wrsync_delaypipe = 5;
endmodule |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Chroma_Upsampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 7; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = 8'h80;
assign converted_data[15: 8] = 8'h80;
assign converted_data[ 7: 0] = data[7:0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_avalon_video_vga_timing (
// inputs
clk,
reset,
red_to_vga_display,
green_to_vga_display,
blue_to_vga_display,
color_select,
// bidirectional
// outputs
read_enable,
end_of_active_frame,
end_of_frame,
// dac pins
vga_blank, // VGA BLANK
vga_c_sync, // VGA COMPOSITE SYNC
vga_h_sync, // VGA H_SYNC
vga_v_sync, // VGA V_SYNC
vga_data_enable, // VGA DEN
vga_red, // VGA Red[9:0]
vga_green, // VGA Green[9:0]
vga_blue, // VGA Blue[9:0]
vga_color_data // VGA Color[9:0] for TRDB_LCM
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter PW = 10; // Number of bits for pixels
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
parameter LW = 10; // Number of bits for lines
parameter LINE_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] red_to_vga_display;
input [CW: 0] green_to_vga_display;
input [CW: 0] blue_to_vga_display;
input [ 3: 0] color_select;
// Bidirectionals
// Outputs
output read_enable;
output reg end_of_active_frame;
output reg end_of_frame;
// dac pins
output reg vga_blank; // VGA BLANK
output reg vga_c_sync; // VGA COMPOSITE SYNC
output reg vga_h_sync; // VGA H_SYNC
output reg vga_v_sync; // VGA V_SYNC
output reg vga_data_enable; // VGA DEN
output reg [CW: 0] vga_red; // VGA Red[9:0]
output reg [CW: 0] vga_green; // VGA Green[9:0]
output reg [CW: 0] vga_blue; // VGA Blue[9:0]
output reg [CW: 0] vga_color_data; // VGA Color[9:0] for TRDB_LCM
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
//reg clk_en;
reg [PW:1] pixel_counter;
reg [LW:1] line_counter;
reg early_hsync_pulse;
reg early_vsync_pulse;
reg hsync_pulse;
reg vsync_pulse;
reg csync_pulse;
reg hblanking_pulse;
reg vblanking_pulse;
reg blanking_pulse;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
vga_c_sync <= 1'b1;
vga_blank <= 1'b1;
vga_h_sync <= 1'b1;
vga_v_sync <= 1'b1;
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_blank <= ~blanking_pulse;
vga_c_sync <= ~csync_pulse;
vga_h_sync <= ~hsync_pulse;
vga_v_sync <= ~vsync_pulse;
// vga_data_enable <= hsync_pulse | vsync_pulse;
vga_data_enable <= ~blanking_pulse;
if (blanking_pulse)
begin
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_red <= red_to_vga_display;
vga_green <= green_to_vga_display;
vga_blue <= blue_to_vga_display;
vga_color_data <= ({(CW + 1){color_select[0]}} & red_to_vga_display) |
({(CW + 1){color_select[1]}} & green_to_vga_display) |
({(CW + 1){color_select[2]}} & blue_to_vga_display);
end
end
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
begin
pixel_counter <= H_TOTAL - 3; // {PW{1'b0}};
line_counter <= V_TOTAL - 1; // {LW{1'b0}};
end
else
begin
// last pixel in the line
if (pixel_counter == (H_TOTAL - 1))
begin
pixel_counter <= {PW{1'b0}};
// last pixel in last line of frame
if (line_counter == (V_TOTAL - 1))
line_counter <= {LW{1'b0}};
// last pixel but not last line
else
line_counter <= line_counter + LINE_COUNTER_INCREMENT;
end
else
pixel_counter <= pixel_counter + PIXEL_COUNTER_INCREMENT;
end
end
always @ (posedge clk)
begin
if (reset)
begin
end_of_active_frame <= 1'b0;
end_of_frame <= 1'b0;
end
else
begin
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_ACTIVE - 2)))
end_of_active_frame <= 1'b1;
else
end_of_active_frame <= 1'b0;
if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
end_of_frame <= 1'b1;
else
end_of_frame <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
begin
early_hsync_pulse <= 1'b0;
early_vsync_pulse <= 1'b0;
hsync_pulse <= 1'b0;
vsync_pulse <= 1'b0;
csync_pulse <= 1'b0;
end
else
begin
// start of horizontal sync
if (pixel_counter == (H_ACTIVE + H_FRONT_PORCH - 2))
early_hsync_pulse <= 1'b1;
// end of horizontal sync
else if (pixel_counter == (H_TOTAL - H_BACK_PORCH - 2))
early_hsync_pulse <= 1'b0;
// start of vertical sync
if ((line_counter == (V_ACTIVE + V_FRONT_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b1;
// end of vertical sync
else if ((line_counter == (V_TOTAL - V_BACK_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b0;
hsync_pulse <= early_hsync_pulse;
vsync_pulse <= early_vsync_pulse;
csync_pulse <= early_hsync_pulse ^ early_vsync_pulse;
end
end
always @ (posedge clk)
begin
if (reset)
begin
hblanking_pulse <= 1'b1;
vblanking_pulse <= 1'b1;
blanking_pulse <= 1'b1;
end
else
begin
if (pixel_counter == (H_ACTIVE - 2))
hblanking_pulse <= 1'b1;
else if (pixel_counter == (H_TOTAL - 2))
hblanking_pulse <= 1'b0;
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b1;
else if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b0;
blanking_pulse <= hblanking_pulse | vblanking_pulse;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign read_enable = ~blanking_pulse;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_SDRAM_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 24: 0] rdaddress;
input rdclken;
input [ 24: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [33554431: 0];
wire [ 15: 0] q;
reg [ 24: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("Computer_System_SDRAM_test_component.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 25,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule |
module Computer_System_SDRAM_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dqm,
zs_ras_n,
zs_we_n,
// outputs:
zs_dq
)
;
inout [ 15: 0] zs_dq;
input clk;
input [ 12: 0] zs_addr;
input [ 1: 0] zs_ba;
input zs_cas_n;
input zs_cke;
input zs_cs_n;
input [ 1: 0] zs_dqm;
input zs_ras_n;
input zs_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
wire [ 9: 0] addr_col;
reg [ 14: 0] addr_crb;
wire [ 1: 0] ba;
wire cas_n;
wire cke;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] dqm;
wire [ 2: 0] index;
reg [ 2: 0] latency;
wire [ 1: 0] mask;
wire [ 15: 0] mem_bytes;
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 1: 0] rd_mask_pipe_0;
reg [ 1: 0] rd_mask_pipe_1;
reg [ 1: 0] rd_mask_pipe_2;
reg [ 2: 0] rd_valid_pipe;
wire [ 24: 0] read_addr;
wire [ 15: 0] read_data;
wire [ 1: 0] read_mask;
wire [ 15: 0] read_temp;
wire read_valid;
wire [ 15: 0] rmw_temp;
wire [ 24: 0] test_addr;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 15: 0] zs_dq;
initial
begin
$write("\n");
$write("************************************************************\n");
$write("This testbench includes an SOPC Builder Generated Altera model:\n");
$write("'Computer_System_SDRAM_test_component.v', to simulate accesses to SDRAM.\n");
$write("Initial contents are loaded from the file: 'Computer_System_SDRAM_test_component.dat'.\n");
$write("************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
Computer_System_SDRAM_test_component_ram_module Computer_System_SDRAM_test_component_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress ((CODE == 24'h205752) ? test_addr : read_addr),
.rdclken (1'b1),
.wraddress (test_addr),
.wrclock (clk),
.wren (CODE == 24'h205752)
);
assign cke = zs_cke;
assign cs_n = zs_cs_n;
assign ras_n = zs_ras_n;
assign cas_n = zs_cas_n;
assign we_n = zs_we_n;
assign dqm = zs_dqm;
assign ba = zs_ba;
assign a = zs_addr;
assign cmd_code = {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 0];
assign test_addr = {addr_crb, addr_col};
assign mem_bytes = read_data;
assign rmw_temp[7 : 0] = dqm[0] ? mem_bytes[7 : 0] : zs_dq[7 : 0];
assign rmw_temp[15 : 8] = dqm[1] ? mem_bytes[15 : 8] : zs_dq[15 : 8];
// Handle Input.
always @(posedge clk)
begin
// No Activity of Clock Disabled
if (cke)
begin
// LMR: Get CAS_Latency.
if (CODE == 24'h4c4d52)
latency <= a[6 : 4];
// ACT: Get Row/Bank Address.
if (CODE == 24'h414354)
addr_crb <= {ba[1], a, ba[0]};
rd_valid_pipe[2] <= rd_valid_pipe[1];
rd_valid_pipe[1] <= rd_valid_pipe[0];
rd_valid_pipe[0] <= CODE == 24'h205244;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end
end
assign read_temp[7 : 0] = mask[0] ? 8'bz : read_data[7 : 0];
assign read_temp[15 : 8] = mask[1] ? 8'bz : read_data[15 : 8];
//use index to select which pipeline stage drives addr
assign read_addr = (index == 0)? rd_addr_pipe_0 :
(index == 1)? rd_addr_pipe_1 :
rd_addr_pipe_2;
//use index to select which pipeline stage drives mask
assign read_mask = (index == 0)? rd_mask_pipe_0 :
(index == 1)? rd_mask_pipe_1 :
rd_mask_pipe_2;
//use index to select which pipeline stage drives valid
assign read_valid = (index == 0)? rd_valid_pipe[0] :
(index == 1)? rd_valid_pipe[1] :
rd_valid_pipe[2];
assign index = latency - 1'b1;
assign mask = read_mask;
assign zs_dq = read_valid ? read_temp : {16{1'bz}};
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0 (
input wire Sys_Clk_clk_clk, // Sys_Clk_clk.clk
input wire Char_Buf_DMA_reset_reset_bridge_in_reset_reset, // Char_Buf_DMA_reset_reset_bridge_in_reset.reset
input wire [31:0] Char_Buf_DMA_avalon_dma_master_address, // Char_Buf_DMA_avalon_dma_master.address
output wire Char_Buf_DMA_avalon_dma_master_waitrequest, // .waitrequest
input wire Char_Buf_DMA_avalon_dma_master_read, // .read
output wire [7:0] Char_Buf_DMA_avalon_dma_master_readdata, // .readdata
output wire Char_Buf_DMA_avalon_dma_master_readdatavalid, // .readdatavalid
input wire Char_Buf_DMA_avalon_dma_master_lock, // .lock
output wire [10:0] Onchip_SRAM_s2_address, // Onchip_SRAM_s2.address
output wire Onchip_SRAM_s2_write, // .write
input wire [31:0] Onchip_SRAM_s2_readdata, // .readdata
output wire [31:0] Onchip_SRAM_s2_writedata, // .writedata
output wire [3:0] Onchip_SRAM_s2_byteenable, // .byteenable
output wire Onchip_SRAM_s2_chipselect, // .chipselect
output wire Onchip_SRAM_s2_clken // .clken
);
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest; // Char_Buf_DMA_avalon_dma_master_agent:av_waitrequest -> Char_Buf_DMA_avalon_dma_master_translator:uav_waitrequest
wire [7:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata; // Char_Buf_DMA_avalon_dma_master_agent:av_readdata -> Char_Buf_DMA_avalon_dma_master_translator:uav_readdata
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess; // Char_Buf_DMA_avalon_dma_master_translator:uav_debugaccess -> Char_Buf_DMA_avalon_dma_master_agent:av_debugaccess
wire [31:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address; // Char_Buf_DMA_avalon_dma_master_translator:uav_address -> Char_Buf_DMA_avalon_dma_master_agent:av_address
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read; // Char_Buf_DMA_avalon_dma_master_translator:uav_read -> Char_Buf_DMA_avalon_dma_master_agent:av_read
wire [0:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable; // Char_Buf_DMA_avalon_dma_master_translator:uav_byteenable -> Char_Buf_DMA_avalon_dma_master_agent:av_byteenable
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid; // Char_Buf_DMA_avalon_dma_master_agent:av_readdatavalid -> Char_Buf_DMA_avalon_dma_master_translator:uav_readdatavalid
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock; // Char_Buf_DMA_avalon_dma_master_translator:uav_lock -> Char_Buf_DMA_avalon_dma_master_agent:av_lock
wire char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write; // Char_Buf_DMA_avalon_dma_master_translator:uav_write -> Char_Buf_DMA_avalon_dma_master_agent:av_write
wire [7:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata; // Char_Buf_DMA_avalon_dma_master_translator:uav_writedata -> Char_Buf_DMA_avalon_dma_master_agent:av_writedata
wire [0:0] char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount; // Char_Buf_DMA_avalon_dma_master_translator:uav_burstcount -> Char_Buf_DMA_avalon_dma_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Char_Buf_DMA_avalon_dma_master_agent:rp_valid
wire [74:0] rsp_mux_src_data; // rsp_mux:src_data -> Char_Buf_DMA_avalon_dma_master_agent:rp_data
wire rsp_mux_src_ready; // Char_Buf_DMA_avalon_dma_master_agent:rp_ready -> rsp_mux:src_ready
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Char_Buf_DMA_avalon_dma_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Char_Buf_DMA_avalon_dma_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Char_Buf_DMA_avalon_dma_master_agent:rp_endofpacket
wire [31:0] onchip_sram_s2_agent_m0_readdata; // Onchip_SRAM_s2_translator:uav_readdata -> Onchip_SRAM_s2_agent:m0_readdata
wire onchip_sram_s2_agent_m0_waitrequest; // Onchip_SRAM_s2_translator:uav_waitrequest -> Onchip_SRAM_s2_agent:m0_waitrequest
wire onchip_sram_s2_agent_m0_debugaccess; // Onchip_SRAM_s2_agent:m0_debugaccess -> Onchip_SRAM_s2_translator:uav_debugaccess
wire [31:0] onchip_sram_s2_agent_m0_address; // Onchip_SRAM_s2_agent:m0_address -> Onchip_SRAM_s2_translator:uav_address
wire [3:0] onchip_sram_s2_agent_m0_byteenable; // Onchip_SRAM_s2_agent:m0_byteenable -> Onchip_SRAM_s2_translator:uav_byteenable
wire onchip_sram_s2_agent_m0_read; // Onchip_SRAM_s2_agent:m0_read -> Onchip_SRAM_s2_translator:uav_read
wire onchip_sram_s2_agent_m0_readdatavalid; // Onchip_SRAM_s2_translator:uav_readdatavalid -> Onchip_SRAM_s2_agent:m0_readdatavalid
wire onchip_sram_s2_agent_m0_lock; // Onchip_SRAM_s2_agent:m0_lock -> Onchip_SRAM_s2_translator:uav_lock
wire [31:0] onchip_sram_s2_agent_m0_writedata; // Onchip_SRAM_s2_agent:m0_writedata -> Onchip_SRAM_s2_translator:uav_writedata
wire onchip_sram_s2_agent_m0_write; // Onchip_SRAM_s2_agent:m0_write -> Onchip_SRAM_s2_translator:uav_write
wire [2:0] onchip_sram_s2_agent_m0_burstcount; // Onchip_SRAM_s2_agent:m0_burstcount -> Onchip_SRAM_s2_translator:uav_burstcount
wire onchip_sram_s2_agent_rf_source_valid; // Onchip_SRAM_s2_agent:rf_source_valid -> Onchip_SRAM_s2_agent_rsp_fifo:in_valid
wire [102:0] onchip_sram_s2_agent_rf_source_data; // Onchip_SRAM_s2_agent:rf_source_data -> Onchip_SRAM_s2_agent_rsp_fifo:in_data
wire onchip_sram_s2_agent_rf_source_ready; // Onchip_SRAM_s2_agent_rsp_fifo:in_ready -> Onchip_SRAM_s2_agent:rf_source_ready
wire onchip_sram_s2_agent_rf_source_startofpacket; // Onchip_SRAM_s2_agent:rf_source_startofpacket -> Onchip_SRAM_s2_agent_rsp_fifo:in_startofpacket
wire onchip_sram_s2_agent_rf_source_endofpacket; // Onchip_SRAM_s2_agent:rf_source_endofpacket -> Onchip_SRAM_s2_agent_rsp_fifo:in_endofpacket
wire onchip_sram_s2_agent_rsp_fifo_out_valid; // Onchip_SRAM_s2_agent_rsp_fifo:out_valid -> Onchip_SRAM_s2_agent:rf_sink_valid
wire [102:0] onchip_sram_s2_agent_rsp_fifo_out_data; // Onchip_SRAM_s2_agent_rsp_fifo:out_data -> Onchip_SRAM_s2_agent:rf_sink_data
wire onchip_sram_s2_agent_rsp_fifo_out_ready; // Onchip_SRAM_s2_agent:rf_sink_ready -> Onchip_SRAM_s2_agent_rsp_fifo:out_ready
wire onchip_sram_s2_agent_rsp_fifo_out_startofpacket; // Onchip_SRAM_s2_agent_rsp_fifo:out_startofpacket -> Onchip_SRAM_s2_agent:rf_sink_startofpacket
wire onchip_sram_s2_agent_rsp_fifo_out_endofpacket; // Onchip_SRAM_s2_agent_rsp_fifo:out_endofpacket -> Onchip_SRAM_s2_agent:rf_sink_endofpacket
wire char_buf_dma_avalon_dma_master_agent_cp_valid; // Char_Buf_DMA_avalon_dma_master_agent:cp_valid -> router:sink_valid
wire [74:0] char_buf_dma_avalon_dma_master_agent_cp_data; // Char_Buf_DMA_avalon_dma_master_agent:cp_data -> router:sink_data
wire char_buf_dma_avalon_dma_master_agent_cp_ready; // router:sink_ready -> Char_Buf_DMA_avalon_dma_master_agent:cp_ready
wire char_buf_dma_avalon_dma_master_agent_cp_startofpacket; // Char_Buf_DMA_avalon_dma_master_agent:cp_startofpacket -> router:sink_startofpacket
wire char_buf_dma_avalon_dma_master_agent_cp_endofpacket; // Char_Buf_DMA_avalon_dma_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [74:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire onchip_sram_s2_agent_rp_valid; // Onchip_SRAM_s2_agent:rp_valid -> router_001:sink_valid
wire [101:0] onchip_sram_s2_agent_rp_data; // Onchip_SRAM_s2_agent:rp_data -> router_001:sink_data
wire onchip_sram_s2_agent_rp_ready; // router_001:sink_ready -> Onchip_SRAM_s2_agent:rp_ready
wire onchip_sram_s2_agent_rp_startofpacket; // Onchip_SRAM_s2_agent:rp_startofpacket -> router_001:sink_startofpacket
wire onchip_sram_s2_agent_rp_endofpacket; // Onchip_SRAM_s2_agent:rp_endofpacket -> router_001:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [74:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [74:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Onchip_SRAM_s2_cmd_width_adapter:in_valid
wire [74:0] cmd_mux_src_data; // cmd_mux:src_data -> Onchip_SRAM_s2_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // Onchip_SRAM_s2_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Onchip_SRAM_s2_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Onchip_SRAM_s2_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Onchip_SRAM_s2_cmd_width_adapter:in_endofpacket
wire onchip_sram_s2_cmd_width_adapter_src_valid; // Onchip_SRAM_s2_cmd_width_adapter:out_valid -> Onchip_SRAM_s2_agent:cp_valid
wire [101:0] onchip_sram_s2_cmd_width_adapter_src_data; // Onchip_SRAM_s2_cmd_width_adapter:out_data -> Onchip_SRAM_s2_agent:cp_data
wire onchip_sram_s2_cmd_width_adapter_src_ready; // Onchip_SRAM_s2_agent:cp_ready -> Onchip_SRAM_s2_cmd_width_adapter:out_ready
wire [0:0] onchip_sram_s2_cmd_width_adapter_src_channel; // Onchip_SRAM_s2_cmd_width_adapter:out_channel -> Onchip_SRAM_s2_agent:cp_channel
wire onchip_sram_s2_cmd_width_adapter_src_startofpacket; // Onchip_SRAM_s2_cmd_width_adapter:out_startofpacket -> Onchip_SRAM_s2_agent:cp_startofpacket
wire onchip_sram_s2_cmd_width_adapter_src_endofpacket; // Onchip_SRAM_s2_cmd_width_adapter:out_endofpacket -> Onchip_SRAM_s2_agent:cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> Onchip_SRAM_s2_rsp_width_adapter:in_valid
wire [101:0] router_001_src_data; // router_001:src_data -> Onchip_SRAM_s2_rsp_width_adapter:in_data
wire router_001_src_ready; // Onchip_SRAM_s2_rsp_width_adapter:in_ready -> router_001:src_ready
wire [0:0] router_001_src_channel; // router_001:src_channel -> Onchip_SRAM_s2_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> Onchip_SRAM_s2_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> Onchip_SRAM_s2_rsp_width_adapter:in_endofpacket
wire onchip_sram_s2_rsp_width_adapter_src_valid; // Onchip_SRAM_s2_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [74:0] onchip_sram_s2_rsp_width_adapter_src_data; // Onchip_SRAM_s2_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire onchip_sram_s2_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> Onchip_SRAM_s2_rsp_width_adapter:out_ready
wire [0:0] onchip_sram_s2_rsp_width_adapter_src_channel; // Onchip_SRAM_s2_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire onchip_sram_s2_rsp_width_adapter_src_startofpacket; // Onchip_SRAM_s2_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire onchip_sram_s2_rsp_width_adapter_src_endofpacket; // Onchip_SRAM_s2_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire onchip_sram_s2_agent_rdata_fifo_src_valid; // Onchip_SRAM_s2_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] onchip_sram_s2_agent_rdata_fifo_src_data; // Onchip_SRAM_s2_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire onchip_sram_s2_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Onchip_SRAM_s2_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Onchip_SRAM_s2_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Onchip_SRAM_s2_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Onchip_SRAM_s2_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Onchip_SRAM_s2_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (8),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (1),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (1),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) char_buf_dma_avalon_dma_master_translator (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Char_Buf_DMA_avalon_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (Char_Buf_DMA_avalon_dma_master_waitrequest), // .waitrequest
.av_read (Char_Buf_DMA_avalon_dma_master_read), // .read
.av_readdata (Char_Buf_DMA_avalon_dma_master_readdata), // .readdata
.av_readdatavalid (Char_Buf_DMA_avalon_dma_master_readdatavalid), // .readdatavalid
.av_lock (Char_Buf_DMA_avalon_dma_master_lock), // .lock
.av_burstcount (1'b1), // (terminated)
.av_byteenable (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (8'b00000000), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_sram_s2_translator (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_sram_s2_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_sram_s2_agent_m0_burstcount), // .burstcount
.uav_read (onchip_sram_s2_agent_m0_read), // .read
.uav_write (onchip_sram_s2_agent_m0_write), // .write
.uav_waitrequest (onchip_sram_s2_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_sram_s2_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_sram_s2_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_sram_s2_agent_m0_readdata), // .readdata
.uav_writedata (onchip_sram_s2_agent_m0_writedata), // .writedata
.uav_lock (onchip_sram_s2_agent_m0_lock), // .lock
.uav_debugaccess (onchip_sram_s2_agent_m0_debugaccess), // .debugaccess
.av_address (Onchip_SRAM_s2_address), // avalon_anti_slave_0.address
.av_write (Onchip_SRAM_s2_write), // .write
.av_readdata (Onchip_SRAM_s2_readdata), // .readdata
.av_writedata (Onchip_SRAM_s2_writedata), // .writedata
.av_byteenable (Onchip_SRAM_s2_byteenable), // .byteenable
.av_chipselect (Onchip_SRAM_s2_chipselect), // .chipselect
.av_clken (Onchip_SRAM_s2_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (74),
.PKT_ORI_BURST_SIZE_L (72),
.PKT_RESPONSE_STATUS_H (71),
.PKT_RESPONSE_STATUS_L (70),
.PKT_QOS_H (59),
.PKT_QOS_L (59),
.PKT_DATA_SIDEBAND_H (57),
.PKT_DATA_SIDEBAND_L (57),
.PKT_ADDR_SIDEBAND_H (56),
.PKT_ADDR_SIDEBAND_L (56),
.PKT_BURST_TYPE_H (55),
.PKT_BURST_TYPE_L (54),
.PKT_CACHE_H (69),
.PKT_CACHE_L (66),
.PKT_THREAD_ID_H (62),
.PKT_THREAD_ID_L (62),
.PKT_BURST_SIZE_H (53),
.PKT_BURST_SIZE_L (51),
.PKT_TRANS_EXCLUSIVE (46),
.PKT_TRANS_LOCK (45),
.PKT_BEGIN_BURST (58),
.PKT_PROTECTION_H (65),
.PKT_PROTECTION_L (63),
.PKT_BURSTWRAP_H (50),
.PKT_BURSTWRAP_L (50),
.PKT_BYTE_CNT_H (49),
.PKT_BYTE_CNT_L (47),
.PKT_ADDR_H (40),
.PKT_ADDR_L (9),
.PKT_TRANS_COMPRESSED_READ (41),
.PKT_TRANS_POSTED (42),
.PKT_TRANS_WRITE (43),
.PKT_TRANS_READ (44),
.PKT_DATA_H (7),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (8),
.PKT_BYTEEN_L (8),
.PKT_SRC_ID_H (60),
.PKT_SRC_ID_L (60),
.PKT_DEST_ID_H (61),
.PKT_DEST_ID_L (61),
.ST_DATA_W (75),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (1),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) char_buf_dma_avalon_dma_master_agent (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (char_buf_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (char_buf_dma_avalon_dma_master_agent_cp_valid), // cp.valid
.cp_data (char_buf_dma_avalon_dma_master_agent_cp_data), // .data
.cp_startofpacket (char_buf_dma_avalon_dma_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (char_buf_dma_avalon_dma_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (char_buf_dma_avalon_dma_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (88),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (1),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_sram_s2_agent (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_sram_s2_agent_m0_address), // m0.address
.m0_burstcount (onchip_sram_s2_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_sram_s2_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_sram_s2_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_sram_s2_agent_m0_lock), // .lock
.m0_readdata (onchip_sram_s2_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_sram_s2_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_sram_s2_agent_m0_read), // .read
.m0_waitrequest (onchip_sram_s2_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_sram_s2_agent_m0_writedata), // .writedata
.m0_write (onchip_sram_s2_agent_m0_write), // .write
.rp_endofpacket (onchip_sram_s2_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_sram_s2_agent_rp_ready), // .ready
.rp_valid (onchip_sram_s2_agent_rp_valid), // .valid
.rp_data (onchip_sram_s2_agent_rp_data), // .data
.rp_startofpacket (onchip_sram_s2_agent_rp_startofpacket), // .startofpacket
.cp_ready (onchip_sram_s2_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (onchip_sram_s2_cmd_width_adapter_src_valid), // .valid
.cp_data (onchip_sram_s2_cmd_width_adapter_src_data), // .data
.cp_startofpacket (onchip_sram_s2_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (onchip_sram_s2_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (onchip_sram_s2_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (onchip_sram_s2_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_sram_s2_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_sram_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_sram_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_sram_s2_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_sram_s2_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_sram_s2_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_sram_s2_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_sram_s2_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_sram_s2_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (onchip_sram_s2_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_sram_s2_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_sram_s2_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_sram_s2_agent_rsp_fifo (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_sram_s2_agent_rf_source_data), // in.data
.in_valid (onchip_sram_s2_agent_rf_source_valid), // .valid
.in_ready (onchip_sram_s2_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_sram_s2_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_sram_s2_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_sram_s2_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_sram_s2_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_sram_s2_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_sram_s2_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_sram_s2_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router router (
.sink_ready (char_buf_dma_avalon_dma_master_agent_cp_ready), // sink.ready
.sink_valid (char_buf_dma_avalon_dma_master_agent_cp_valid), // .valid
.sink_data (char_buf_dma_avalon_dma_master_agent_cp_data), // .data
.sink_startofpacket (char_buf_dma_avalon_dma_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (char_buf_dma_avalon_dma_master_agent_cp_endofpacket), // .endofpacket
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_router_001 router_001 (
.sink_ready (onchip_sram_s2_agent_rp_ready), // sink.ready
.sink_valid (onchip_sram_s2_agent_rp_valid), // .valid
.sink_data (onchip_sram_s2_agent_rp_data), // .data
.sink_startofpacket (onchip_sram_s2_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_sram_s2_agent_rp_endofpacket), // .endofpacket
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_demux cmd_demux (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_mux cmd_mux (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_cmd_demux rsp_demux (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (onchip_sram_s2_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (onchip_sram_s2_rsp_width_adapter_src_channel), // .channel
.sink_data (onchip_sram_s2_rsp_width_adapter_src_data), // .data
.sink_startofpacket (onchip_sram_s2_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (onchip_sram_s2_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (onchip_sram_s2_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0_rsp_mux rsp_mux (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (40),
.IN_PKT_ADDR_L (9),
.IN_PKT_DATA_H (7),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (8),
.IN_PKT_BYTEEN_L (8),
.IN_PKT_BYTE_CNT_H (49),
.IN_PKT_BYTE_CNT_L (47),
.IN_PKT_TRANS_COMPRESSED_READ (41),
.IN_PKT_TRANS_WRITE (43),
.IN_PKT_BURSTWRAP_H (50),
.IN_PKT_BURSTWRAP_L (50),
.IN_PKT_BURST_SIZE_H (53),
.IN_PKT_BURST_SIZE_L (51),
.IN_PKT_RESPONSE_STATUS_H (71),
.IN_PKT_RESPONSE_STATUS_L (70),
.IN_PKT_TRANS_EXCLUSIVE (46),
.IN_PKT_BURST_TYPE_H (55),
.IN_PKT_BURST_TYPE_L (54),
.IN_PKT_ORI_BURST_SIZE_L (72),
.IN_PKT_ORI_BURST_SIZE_H (74),
.IN_ST_DATA_W (75),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (98),
.OUT_PKT_RESPONSE_STATUS_L (97),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (99),
.OUT_PKT_ORI_BURST_SIZE_H (101),
.OUT_ST_DATA_W (102),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) onchip_sram_s2_cmd_width_adapter (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (onchip_sram_s2_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (onchip_sram_s2_cmd_width_adapter_src_data), // .data
.out_channel (onchip_sram_s2_cmd_width_adapter_src_channel), // .channel
.out_valid (onchip_sram_s2_cmd_width_adapter_src_valid), // .valid
.out_ready (onchip_sram_s2_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (onchip_sram_s2_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (98),
.IN_PKT_RESPONSE_STATUS_L (97),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (99),
.IN_PKT_ORI_BURST_SIZE_H (101),
.IN_ST_DATA_W (102),
.OUT_PKT_ADDR_H (40),
.OUT_PKT_ADDR_L (9),
.OUT_PKT_DATA_H (7),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (8),
.OUT_PKT_BYTEEN_L (8),
.OUT_PKT_BYTE_CNT_H (49),
.OUT_PKT_BYTE_CNT_L (47),
.OUT_PKT_TRANS_COMPRESSED_READ (41),
.OUT_PKT_BURST_SIZE_H (53),
.OUT_PKT_BURST_SIZE_L (51),
.OUT_PKT_RESPONSE_STATUS_H (71),
.OUT_PKT_RESPONSE_STATUS_L (70),
.OUT_PKT_TRANS_EXCLUSIVE (46),
.OUT_PKT_BURST_TYPE_H (55),
.OUT_PKT_BURST_TYPE_L (54),
.OUT_PKT_ORI_BURST_SIZE_L (72),
.OUT_PKT_ORI_BURST_SIZE_H (74),
.OUT_ST_DATA_W (75),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) onchip_sram_s2_rsp_width_adapter (
.clk (Sys_Clk_clk_clk), // clk.clk
.reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (onchip_sram_s2_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (onchip_sram_s2_rsp_width_adapter_src_data), // .data
.out_channel (onchip_sram_s2_rsp_width_adapter_src_channel), // .channel
.out_valid (onchip_sram_s2_rsp_width_adapter_src_valid), // .valid
.out_ready (onchip_sram_s2_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (onchip_sram_s2_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (Sys_Clk_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Char_Buf_DMA_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_sram_s2_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_sram_s2_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_sram_s2_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection (
// Inputs
clk,
reset,
in_data,
in_startofpacket,
in_endofpacket,
in_empty,
in_valid,
out_ready,
// Bidirectional
// Outputs
in_ready,
out_data,
out_startofpacket,
out_endofpacket,
out_empty,
out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 720; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] in_data;
input in_startofpacket;
input in_endofpacket;
input in_empty;
input in_valid;
input out_ready;
// Bidirectional
// Outputs
output in_ready;
output reg [ 7: 0] out_data;
output reg out_startofpacket;
output reg out_endofpacket;
output reg out_empty;
output reg out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ 8: 0] filter_1_data_out; // Gaussian_Smoothing
wire [ 9: 0] filter_2_data_out; // Sobel operator
wire [ 7: 0] filter_3_data_out; // Nonmaximum Suppression
wire [ 7: 0] filter_4_data_out; // Hyteresis
wire [ 7: 0] final_value; // Intensity Correction
wire [ 1: 0] pixel_info_in;
wire [ 1: 0] pixel_info_out;
// Internal Registers
reg [ 7: 0] data;
reg startofpacket;
reg endofpacket;
reg empty;
reg valid;
reg flush_pipeline;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
out_data <= 8'h00;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_empty <= 1'b0;
out_valid <= 1'b0;
end
else if (transfer_data)
begin
out_data <= final_value;
out_startofpacket <= pixel_info_out[1] & ~(&(pixel_info_out));
out_endofpacket <= pixel_info_out[0] & ~(&(pixel_info_out));
out_empty <= 1'b0;
out_valid <= (|(pixel_info_out));
end
else if (out_ready)
out_valid <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 8'h00;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 1'b0;
valid <= 1'b0;
end
else if (in_ready)
begin
data <= in_data;
startofpacket <= in_startofpacket;
endofpacket <= in_endofpacket;
empty <= in_empty;
valid <= in_valid;
end
end
always @(posedge clk)
begin
if (reset)
flush_pipeline <= 1'b0;
else if (in_ready & in_endofpacket)
flush_pipeline <= 1'b1;
else if (in_ready & in_startofpacket)
flush_pipeline <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign in_ready = in_valid & (out_ready | ~out_valid);
// Internal Assignments
assign transfer_data = in_ready |
(flush_pipeline & (out_ready | ~out_valid));
assign final_value = filter_4_data_out;
assign pixel_info_in[1] = in_valid & ~in_endofpacket;
assign pixel_info_in[0] = in_valid & ~in_startofpacket;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_gaussian_smoothing_filter Filter_1 (
// Inputs
.clk (clk),
.reset (reset),
.data_in (data),
.data_en (transfer_data),
// Bidirectionals
// Outputs
.data_out (filter_1_data_out)
);
defparam
Filter_1.WIDTH = WIDTH;
altera_up_edge_detection_sobel_operator Filter_2 (
// Inputs
.clk (clk),
.reset (reset),
.data_in (filter_1_data_out),
.data_en (transfer_data),
// Bidirectionals
// Outputs
.data_out (filter_2_data_out)
);
defparam
Filter_2.WIDTH = WIDTH;
altera_up_edge_detection_nonmaximum_suppression Filter_3 (
// Inputs
.clk (clk),
.reset (reset),
.data_in (filter_2_data_out),
.data_en (transfer_data),
// Bidirectionals
// Outputs
.data_out (filter_3_data_out)
);
defparam
Filter_3.WIDTH = WIDTH;
altera_up_edge_detection_hysteresis Filter_4 (
// Inputs
.clk (clk),
.reset (reset),
.data_in (filter_3_data_out),
.data_en (transfer_data),
// Bidirectionals
// Outputs
.data_out (filter_4_data_out)
);
defparam
Filter_4.WIDTH = WIDTH;
altera_up_edge_detection_pixel_info_shift_register Pixel_Info_Shift_Register (
// Inputs
.clock (clk),
.clken (transfer_data),
.shiftin (pixel_info_in),
// Bidirectionals
// Outputs
.shiftout (pixel_info_out),
.taps ()
);
// defparam Pixel_Info_Shift_Register.SIZE = WIDTH;
defparam
Pixel_Info_Shift_Register.SIZE = (WIDTH * 5) + 28;
endmodule |
module altera_up_video_alpha_blender_simple (
// Inputs
background_data,
foreground_data,
// Bidirectionals
// Outputs
new_red,
new_green,
new_blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [29: 0] background_data;
input [39: 0] foreground_data;
// Bidirectionals
// Outputs
output [ 9: 0] new_red;
output [ 9: 0] new_green;
output [ 9: 0] new_blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign new_red =
(({10{foreground_data[39]}} & foreground_data[29:20]) |
({10{~foreground_data[39]}} & background_data[29:20]));
assign new_green =
(({10{foreground_data[39]}} & foreground_data[19:10]) |
({10{~foreground_data[39]}} & background_data[19:10]));
assign new_blue =
(({10{foreground_data[39]}} & foreground_data[ 9: 0]) |
({10{~foreground_data[39]}} & background_data[ 9: 0]));
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_VGA_Controller (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule |
module Computer_System_SDRAM_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 43: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 43: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 43: 0] entry_0;
reg [ 43: 0] entry_1;
wire full;
reg rd_address;
reg [ 43: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule |
module Computer_System_SDRAM (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 24: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 24: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 24: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 43: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 13: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
Computer_System_SDRAM_input_efifo_module the_Computer_System_SDRAM_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[24],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 10000;
else if (refresh_counter == 0)
refresh_counter <= 1562;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 1;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 7;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[24],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 1;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[23 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 2;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 1;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 7;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule |
module Computer_System_Video_In_Subsystem_Video_In_CSC (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 23;
parameter OW = 23;
parameter EIW = 1;
parameter EOW = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EIW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [OW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EOW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [OW: 0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [EOW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IW: 0] data;
reg startofpacket;
reg endofpacket;
reg [EIW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 2'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'b0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data = ~stream_out_valid |
(stream_out_ready & stream_out_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_YCrCb_to_RGB_converter YCrCb_to_RGB (
// Inputs
.clk (clk),
.clk_en (transfer_data),
.reset (reset),
.Y (data[ 7: 0]),
.Cr (data[23:16]),
.Cb (data[15: 8]),
.stream_in_startofpacket (startofpacket),
.stream_in_endofpacket (endofpacket),
.stream_in_empty (empty),
.stream_in_valid (valid),
// Bidirectionals
// Outputs
.R (converted_data[23:16]),
.G (converted_data[15: 8]),
.B (converted_data[ 7: 0]),
.stream_out_startofpacket (converted_startofpacket),
.stream_out_endofpacket (converted_endofpacket),
.stream_out_empty (converted_empty),
.stream_out_valid (converted_valid)
);
endmodule |
module Computer_System_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule |
module Computer_System_Video_In_Subsystem_Video_In_DMA (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_ready,
master_address,
master_write,
master_writedata,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 320; // Frame's width in pixels
parameter HEIGHT = 240; // Frame's height in lines
parameter AW = 16; // Frame's address width
parameter WW = 8; // Frame width's address width
parameter HW = 7; // Frame height's address width
parameter MDW = 15; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd134217728;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd134217728;
parameter ADDRESSING_BITS = 16'd2057;
parameter COLOR_BITS = 4'd15;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b0; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output stream_ready;
output [31: 0] master_address;
output master_write;
output [MDW:0] master_writedata;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [WW: 0] w_address; // Frame's width address
reg [HW: 0] h_address; // Frame's height address
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (reset_address)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (inc_address)
begin
if (w_address == (WIDTH - 1))
begin
w_address <= 'h0;
h_address <= h_address + 1;
end
else
w_address <= w_address + 1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
{h_address, w_address, 1'b0};
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b0,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_memory From_Stream_to_Memory (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_waitrequest (master_waitrequest),
// Bidirectional
// Outputs
.stream_ready (stream_ready),
.master_write (master_write),
.master_writedata (master_writedata),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Stream_to_Memory.DW = DW,
From_Stream_to_Memory.EW = EW,
From_Stream_to_Memory.MDW = MDW;
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Char_Buf_DMA (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_address,
master_arbiterlock,
master_read,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 7; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 80; // Frame's width in pixels
parameter HEIGHT = 60; // Frame's height in lines
parameter AW = 12; // Frame's address width
parameter WW = 6; // Frame width's address width
parameter HW = 5; // Frame height's address width
parameter MDW = 7; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd150994944;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd150994944;
parameter ADDRESSING_BITS = 16'd1543;
parameter COLOR_BITS = 4'd7;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output [31: 0] master_address;
output master_arbiterlock;
output master_read;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [WW: 0] w_address; // Frame's width address
reg [HW: 0] h_address; // Frame's height address
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (reset_address)
begin
w_address <= 'h0;
h_address <= 'h0;
end
else if (inc_address)
begin
if (w_address == (WIDTH - 1))
begin
w_address <= 'h0;
h_address <= h_address + 1;
end
else
w_address <= w_address + 1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
{h_address, w_address};
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b0,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_stream From_Memory_to_Stream (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_ready (stream_ready),
.master_readdata (master_readdata),
.master_readdatavalid (master_readdatavalid),
.master_waitrequest (master_waitrequest),
.reading_first_pixel_in_frame ((w_address == 0) && (h_address == 0)),
.reading_last_pixel_in_frame ((w_address == (WIDTH - 1)) && (h_address == (HEIGHT - 1))),
// Bidirectional
// Outputs
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_arbiterlock (master_arbiterlock),
.master_read (master_read),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Memory_to_Stream.DW = DW,
From_Memory_to_Stream.EW = EW,
From_Memory_to_Stream.MDW = MDW;
endmodule |
module Computer_System_ARM_A9_HPS #(
parameter F2S_Width = 2,
parameter S2F_Width = 3
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [63:0] f2h_WDATA, // .wdata
input wire [7:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [63:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [127:0] h2f_WDATA, // .wdata
output wire [15:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [127:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO41, // .hps_io_gpio_inst_GPIO41
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 3)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
Computer_System_ARM_A9_HPS_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
Computer_System_ARM_A9_HPS_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO41 (hps_io_gpio_inst_GPIO41), // .hps_io_gpio_inst_GPIO41
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule |
module altera_up_edge_detection_gaussian_smoothing_filter (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 8: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 7: 0] shift_reg_out[ 3: 0];
// Internal Registers
reg [ 7: 0] original_line_1[ 4: 0];
reg [ 7: 0] original_line_2[ 4: 0];
reg [ 7: 0] original_line_3[ 4: 0];
reg [ 7: 0] original_line_4[ 4: 0];
reg [ 7: 0] original_line_5[ 4: 0];
reg [15: 0] sum_level_1[12: 0];
reg [15: 0] sum_level_2[ 6: 0];
reg [15: 0] sum_level_3[ 4: 0];
reg [15: 0] sum_level_4[ 2: 0];
reg [15: 0] sum_level_5[ 1: 0];
reg [15: 0] sum_level_6;
reg [ 8: 0] sum_level_7;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Gaussian Smoothing Filter
//
// [ 2 4 5 4 2 ]
// [ 4 9 12 9 4 ]
// 1 / 115 [ 5 12 15 12 5 ]
// [ 4 9 12 9 4 ]
// [ 2 4 5 4 2 ]
//
always @(posedge clk)
begin
if (reset == 1'b1)
begin
for (i = 4; i >= 0; i = i-1)
begin
original_line_1[i] <= 8'h00;
original_line_2[i] <= 8'h00;
original_line_3[i] <= 8'h00;
original_line_4[i] <= 8'h00;
original_line_5[i] <= 8'h00;
end
for (i = 12; i >= 0; i = i-1)
begin
sum_level_1[i] <= 16'h0000;
end
for (i = 6; i >= 0; i = i-1)
begin
sum_level_2[i] <= 16'h0000;
end
for (i = 4; i >= 0; i = i-1)
begin
sum_level_3[i] <= 16'h0000;
end
sum_level_4[0] <= 16'h0000;
sum_level_4[1] <= 16'h0000;
sum_level_4[2] <= 16'h0000;
sum_level_5[0] <= 16'h0000;
sum_level_5[1] <= 16'h0000;
sum_level_6 <= 16'h0000;
sum_level_7 <= 9'h000;
end
else if (data_en == 1'b1)
begin
for (i = 4; i > 0; i = i-1)
begin
original_line_1[i] <= original_line_1[i-1];
original_line_2[i] <= original_line_2[i-1];
original_line_3[i] <= original_line_3[i-1];
original_line_4[i] <= original_line_4[i-1];
original_line_5[i] <= original_line_5[i-1];
end
original_line_1[0] <= data_in;
original_line_2[0] <= shift_reg_out[0];
original_line_3[0] <= shift_reg_out[1];
original_line_4[0] <= shift_reg_out[2];
original_line_5[0] <= shift_reg_out[3];
// Add numbers that are multiplied by 2 and multiply by 2
sum_level_1[ 0] <= {7'h00,original_line_1[0], 1'b0} + {7'h00,original_line_1[4], 1'b0};
sum_level_1[ 1] <= {7'h00,original_line_5[0], 1'b0} + {7'h00,original_line_5[4], 1'b0};
// Add numbers that are multiplied by 4 and multiply by 4
sum_level_1[ 2] <= {6'h00,original_line_1[1], 2'h0} + {6'h00,original_line_1[3], 2'h0};
sum_level_1[ 3] <= {6'h00,original_line_2[0], 2'h0} + {6'h00,original_line_2[4], 2'h0};
sum_level_1[ 4] <= {6'h00,original_line_4[0], 2'h0} + {6'h00,original_line_4[4], 2'h0};
sum_level_1[ 5] <= {6'h00,original_line_5[1], 2'h0} + {6'h00,original_line_5[3], 2'h0};
// Add numbers that are multiplied by 5
sum_level_1[ 6] <= {8'h00,original_line_1[2]} + {8'h00,original_line_5[2]};
sum_level_1[ 7] <= {8'h00,original_line_3[0]} + {8'h00,original_line_3[4]};
// Add numbers that are multiplied by 9
sum_level_1[ 8] <= {8'h00,original_line_2[1]} + {8'h00,original_line_2[3]};
sum_level_1[ 9] <= {8'h00,original_line_4[1]} + {8'h00,original_line_4[3]};
// Add numbers that are multiplied by 12
sum_level_1[10] <= {8'h00,original_line_2[2]} + {8'h00,original_line_4[2]};
sum_level_1[11] <= {8'h00,original_line_3[1]} + {8'h00,original_line_3[3]};
// Add numbers that are multiplied by 15
sum_level_1[12] <= {4'h0,original_line_3[2], 4'h0} - original_line_3[2];
// Add numbers that are multiplied by 2
sum_level_2[ 0] <= sum_level_1[ 0] + sum_level_1[ 1];
// Add numbers that are multiplied by 4
sum_level_2[ 1] <= sum_level_1[ 2] + sum_level_1[ 3];
sum_level_2[ 2] <= sum_level_1[ 4] + sum_level_1[ 5];
// Add numbers that are multiplied by 5
sum_level_2[ 3] <= sum_level_1[ 6] + sum_level_1[ 7];
// Add numbers that are multiplied by 9
sum_level_2[ 4] <= sum_level_1[ 8] + sum_level_1[ 9];
// Add numbers that are multiplied by 12
sum_level_2[ 5] <= sum_level_1[10] + sum_level_1[11];
// Multiplied by 15
sum_level_2[ 6] <= sum_level_1[12];
// Add 2s and 15s
sum_level_3[ 0] <= sum_level_2[ 0] + sum_level_2[ 6];
// Add numbers that are multiplied by 4
sum_level_3[ 1] <= sum_level_2[ 1] + sum_level_2[ 2];
// Multiplied by 5
sum_level_3[ 2] <= {sum_level_2[ 3], 2'h0} + sum_level_2[ 3];
// Multiplied by 9
sum_level_3[ 3] <= {sum_level_2[ 4], 3'h0} + sum_level_2[ 4];
// Multiplied by 12
sum_level_3[ 4] <= {sum_level_2[ 5], 3'h0} + {sum_level_2[ 5], 2'h0};
// Add
sum_level_4[ 0] <= sum_level_3[ 0] + sum_level_3[ 1];
sum_level_4[ 1] <= sum_level_3[ 2] + sum_level_3[ 3];
sum_level_4[ 2] <= sum_level_3[ 4];
sum_level_5[ 0] <= sum_level_4[ 0] + sum_level_4[ 1];
sum_level_5[ 1] <= sum_level_4[ 2];
sum_level_6 <= sum_level_5[ 0] + sum_level_5[ 1];
// Divide by 128, which is close enough to 115
sum_level_7 <= sum_level_6[15:7];
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign data_out = sum_level_7;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_in),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 8,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 8,
shift_register_2.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_3 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[1]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[2]),
.taps ()
);
defparam
shift_register_3.DW = 8,
shift_register_3.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_4 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[2]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[3]),
.taps ()
);
defparam
shift_register_4.DW = 8,
shift_register_4.SIZE = WIDTH;
endmodule |
module altera_up_RGB_to_YCrCb_converter (
// Inputs
clk,
clk_en,
reset,
R,
G,
B,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
// Bidirectionals
// Outputs
Y,
Cr,
Cb,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input reset;
input [ 7: 0] R;
input [ 7: 0] G;
input [ 7: 0] B;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_empty;
input stream_in_valid;
// Bidirectionals
// Outputs
output reg [ 7: 0] Y;
output reg [ 7: 0] Cr;
output reg [ 7: 0] Cb;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [35: 0] product_0;
wire [35: 0] product_1;
wire [35: 0] product_2;
wire [35: 0] product_3;
wire [35: 0] product_4;
wire [35: 0] product_5;
wire [35: 0] product_6;
wire [35: 0] product_7;
wire [35: 0] product_8;
wire [10: 0] Y_sum;
wire [10: 0] Cr_sum;
wire [10: 0] Cb_sum;
// Internal Registers
reg [ 7: 0] R_in;
reg [ 7: 0] G_in;
reg [ 7: 0] B_in;
reg [10: 0] R_0d257;
reg [10: 0] G_0d504;
reg [10: 0] B_0d098;
reg [10: 0] R_0d148;
reg [10: 0] G_0d291;
reg [10: 0] B_0d439;
reg [10: 0] R_0d439;
reg [10: 0] G_0d368;
reg [10: 0] B_0d071;
reg [ 1: 0] startofpacket_shift_reg;
reg [ 1: 0] endofpacket_shift_reg;
reg [ 1: 0] empty_shift_reg;
reg [ 1: 0] valid_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
Y <= 8'h00;
Cr <= 8'h00;
Cb <= 8'h00;
end
else if (clk_en)
begin
if (Y_sum[10] == 1'b1) // Negative number
Y <= 8'h00;
else if ((Y_sum[9] | Y_sum[8]) == 1'b1) // Number greater than 255
Y <= 8'hFF;
else
Y <= Y_sum[ 7: 0];
if (Cr_sum[10] == 1'b1) // Negative number
Cr <= 8'h00;
else if ((Cr_sum[9] | Cr_sum[8]) == 1'b1) // Number greater than 255
Cr <= 8'hFF;
else
Cr <= Cr_sum[ 7: 0];
if (Cb_sum[10] == 1'b1) // Negative number
Cb <= 8'h00;
else if ((Cb_sum[9] | Cb_sum[8]) == 1'b1) // Number greater than 255
Cb <= 8'hFF;
else
Cb <= Cb_sum[ 7: 0];
end
end
always @ (posedge clk)
begin
if (clk_en)
begin
stream_out_startofpacket <= startofpacket_shift_reg[1];
stream_out_endofpacket <= endofpacket_shift_reg[1];
stream_out_empty <= empty_shift_reg[1];
stream_out_valid <= valid_shift_reg[1];
end
end
// Internal Registers
// ---------------------------------------------------------------------------
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
R_in <= 8'h00;
G_in <= 8'h00;
B_in <= 8'h00;
end
else if (clk_en)
begin
R_in <= R;
G_in <= G;
B_in <= B;
end
end
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
R_0d257 <= 11'h000;
G_0d504 <= 11'h000;
B_0d098 <= 11'h000;
R_0d148 <= 11'h000;
G_0d291 <= 11'h000;
B_0d439 <= 11'h000;
R_0d439 <= 11'h000;
G_0d368 <= 11'h000;
B_0d071 <= 11'h000;
end
else if (clk_en)
begin
R_0d257 <= product_0[25:15];
G_0d504 <= product_1[25:15];
B_0d098 <= product_2[25:15];
R_0d148 <= product_3[25:15];
G_0d291 <= product_4[25:15];
B_0d439 <= product_5[25:15];
R_0d439 <= product_6[25:15];
G_0d368 <= product_7[25:15];
B_0d071 <= product_8[25:15];
end
end
always @(posedge clk)
begin
if (reset)
begin
startofpacket_shift_reg <= 2'h0;
endofpacket_shift_reg <= 2'h0;
empty_shift_reg <= 2'h0;
valid_shift_reg <= 2'h0;
end
else if (clk_en)
begin
startofpacket_shift_reg[1] <= startofpacket_shift_reg[0];
endofpacket_shift_reg[1] <= endofpacket_shift_reg[0];
empty_shift_reg[1] <= empty_shift_reg[0];
valid_shift_reg[1] <= valid_shift_reg[0];
startofpacket_shift_reg[0] <= stream_in_startofpacket;
endofpacket_shift_reg[0] <= stream_in_endofpacket;
empty_shift_reg[0] <= stream_in_empty;
valid_shift_reg[0] <= stream_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
// ---------------------------------------------------------------------------
//
// Sum the proper outputs from the multiply to form YCrCb
//
assign Y_sum = 11'd16 + R_0d257 + G_0d504 + B_0d098;
assign Cr_sum = 11'd128 + R_0d439 - G_0d368 - B_0d071;
assign Cb_sum = 11'd128 - R_0d148 - G_0d291 + B_0d439;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// Formula Set #1 (Corrected for 0 to 255 Color Range)
// ---------------------------------------------------------------------------
// Y = 0.257R + 0.504G + 0.098B + 16
// Cr = 0.439R - 0.368G - 0.071B + 128
// Cb = -0.148R - 0.291G + 0.439B + 128
//
// use full precision of multiply to experiment with coefficients
// 0.257 -> I[1:0].F[14:0] .257 X 2^15 = 020E5
// 0.504 -> I[1:0].F[14:0] .504 X 2^15 = 04083
// 0.098 -> I[1:0].F[14:0] .098 X 2^15 = 00C8D
// 0.148 -> I[1:0].F[14:0] .148 X 2^15 = 012F2
// 0.291 -> I[1:0].F[14:0] .291 X 2^15 = 0253F
// 0.439 -> I[1:0].F[14:0] .439 X 2^15 = 03831
// 0.368 -> I[1:0].F[14:0] .368 X 2^15 = 02F1B
// 0.071 -> I[1:0].F[14:0] .071 X 2^15 = 00917
lpm_mult lpm_mult_component_0 (
// Inputs
.dataa ({10'h000, R_in}),
.datab (18'h020E5),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_0),
.sum (1'b0)
);
defparam
lpm_mult_component_0.lpm_widtha = 18,
lpm_mult_component_0.lpm_widthb = 18,
lpm_mult_component_0.lpm_widthp = 36,
lpm_mult_component_0.lpm_widths = 1,
lpm_mult_component_0.lpm_type = "LPM_MULT",
lpm_mult_component_0.lpm_representation = "SIGNED",
lpm_mult_component_0.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_1 (
// Inputs
.dataa ({10'h000, G_in}),
.datab (18'h04083),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_1),
.sum (1'b0)
);
defparam
lpm_mult_component_1.lpm_widtha = 18,
lpm_mult_component_1.lpm_widthb = 18,
lpm_mult_component_1.lpm_widthp = 36,
lpm_mult_component_1.lpm_widths = 1,
lpm_mult_component_1.lpm_type = "LPM_MULT",
lpm_mult_component_1.lpm_representation = "SIGNED",
lpm_mult_component_1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_2 (
// Inputs
.dataa ({10'h000, B_in}),
.datab (18'h00C8D),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_2),
.sum (1'b0)
);
defparam
lpm_mult_component_2.lpm_widtha = 18,
lpm_mult_component_2.lpm_widthb = 18,
lpm_mult_component_2.lpm_widthp = 36,
lpm_mult_component_2.lpm_widths = 1,
lpm_mult_component_2.lpm_type = "LPM_MULT",
lpm_mult_component_2.lpm_representation = "SIGNED",
lpm_mult_component_2.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_6 (
// Inputs
.dataa ({10'h000, R_in}),
.datab (18'h03831),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_6),
.sum (1'b0)
);
defparam
lpm_mult_component_6.lpm_widtha = 18,
lpm_mult_component_6.lpm_widthb = 18,
lpm_mult_component_6.lpm_widthp = 36,
lpm_mult_component_6.lpm_widths = 1,
lpm_mult_component_6.lpm_type = "LPM_MULT",
lpm_mult_component_6.lpm_representation = "SIGNED",
lpm_mult_component_6.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_7 (
// Inputs
.dataa ({10'h000, G_in}),
.datab (18'h02F1B),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_7),
.sum (1'b0)
);
defparam
lpm_mult_component_7.lpm_widtha = 18,
lpm_mult_component_7.lpm_widthb = 18,
lpm_mult_component_7.lpm_widthp = 36,
lpm_mult_component_7.lpm_widths = 1,
lpm_mult_component_7.lpm_type = "LPM_MULT",
lpm_mult_component_7.lpm_representation = "SIGNED",
lpm_mult_component_7.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_8 (
// Inputs
.dataa ({10'h000, B_in}),
.datab (18'h00917),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_8),
.sum (1'b0)
);
defparam
lpm_mult_component_8.lpm_widtha = 18,
lpm_mult_component_8.lpm_widthb = 18,
lpm_mult_component_8.lpm_widthp = 36,
lpm_mult_component_8.lpm_widths = 1,
lpm_mult_component_8.lpm_type = "LPM_MULT",
lpm_mult_component_8.lpm_representation = "SIGNED",
lpm_mult_component_8.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_3 (
// Inputs
.dataa ({10'h000, R_in}),
.datab (18'h012F2),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_3),
.sum (1'b0)
);
defparam
lpm_mult_component_3.lpm_widtha = 18,
lpm_mult_component_3.lpm_widthb = 18,
lpm_mult_component_3.lpm_widthp = 36,
lpm_mult_component_3.lpm_widths = 1,
lpm_mult_component_3.lpm_type = "LPM_MULT",
lpm_mult_component_3.lpm_representation = "SIGNED",
lpm_mult_component_3.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_4 (
// Inputs
.dataa ({10'h000, G_in}),
.datab (18'h0253F),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_4),
.sum (1'b0)
);
defparam
lpm_mult_component_4.lpm_widtha = 18,
lpm_mult_component_4.lpm_widthb = 18,
lpm_mult_component_4.lpm_widthp = 36,
lpm_mult_component_4.lpm_widths = 1,
lpm_mult_component_4.lpm_type = "LPM_MULT",
lpm_mult_component_4.lpm_representation = "SIGNED",
lpm_mult_component_4.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_5 (
// Inputs
.dataa ({10'h000, B_in}),
.datab (18'h03831),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_5),
.sum (1'b0)
);
defparam
lpm_mult_component_5.lpm_widtha = 18,
lpm_mult_component_5.lpm_widthb = 18,
lpm_mult_component_5.lpm_widthp = 36,
lpm_mult_component_5.lpm_widths = 1,
lpm_mult_component_5.lpm_type = "LPM_MULT",
lpm_mult_component_5.lpm_representation = "SIGNED",
lpm_mult_component_5.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
// Formula Set #2 (BT.601 Gamma Corrected Color Conversion)
// ---------------------------------------------------------------------------
// Y = ( 77 / 256)R + (150 / 256)G + ( 29 / 256)B
// Cr = -( 44 / 256)R - ( 87 / 256)G + (131 / 256)B + 128
// Cb = (131 / 256)R - (110 / 256)G - ( 21 / 256)B + 128
//
// use full precision of multiply to experiment with coefficients
// ( 77 / 256) -> I[1:0].F[14:0] 0.30078 X 2^15 = 02680
// (150 / 256) -> I[1:0].F[14:0] 0.58594 X 2^15 = 04B00
// ( 29 / 256) -> I[1:0].F[14:0] 0.11328 X 2^15 = 00E80
// ( 44 / 256) -> I[1:0].F[14:0] 0.17188 X 2^15 = 01600
// ( 87 / 256) -> I[1:0].F[14:0] 0.33984 X 2^15 = 02B80
// (131 / 256) -> I[1:0].F[14:0] 0.51172 X 2^15 = 04180
// (110 / 256) -> I[1:0].F[14:0] 0.42969 X 2^15 = 03700
// ( 21 / 256) -> I[1:0].F[14:0] 0.08103 X 2^15 = 00A80
endmodule |
module Computer_System_VGA_Subsystem_VGA_Pixel_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15;
parameter ODW = 29;
parameter IEW = 0;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[15:11], stream_in_data[15:11]};
assign g = {stream_in_data[10: 5], stream_in_data[10: 7]};
assign b = {stream_in_data[ 4: 0], stream_in_data[ 4: 0]};
assign a = ALPHA;
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_edge_detection_hysteresis (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 7: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 8: 0] shift_reg_out[ 1: 0];
wire data_above_high_threshold;
wire [ 8: 0] data_to_shift_register_1;
wire above_threshold;
wire overflow;
// Internal Registers
reg [ 8: 0] data_line_2[ 1: 0];
reg [ 2: 0] thresholds[ 2: 0];
reg [ 7: 0] result;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
begin
data_line_2[0] <= 8'h00;
data_line_2[1] <= 8'h00;
for (i = 2; i >= 0; i = i-1)
thresholds[i] <= 3'h0;
end
else if (data_en == 1'b1)
begin
// Increase edge visibility by 32 and saturate at 255
data_line_2[1] <= data_line_2[0] | {9{data_line_2[0][8]}};
data_line_2[0] <= {1'b0, shift_reg_out[0][7:0]} + 32;
thresholds[0] <= {thresholds[0][1:0], data_above_high_threshold};
thresholds[1] <= {thresholds[1][1:0], shift_reg_out[0][8]};
thresholds[2] <= {thresholds[2][1:0], shift_reg_out[1][8]};
result <= (above_threshold) ? data_line_2[1][7:0] : 8'h00;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// External Assignments
assign data_out = result;
// Internal Assignments
assign data_above_high_threshold = (data_in >= 8'h0A) ? 1'b1 : 1'b0;
assign data_to_shift_register_1 = {data_above_high_threshold,data_in};
assign above_threshold =
((|(thresholds[0])) | (|(thresholds[1])) | (|(thresholds[2])));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_to_shift_register_1),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 9,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 9,
shift_register_2.SIZE = WIDTH;
endmodule |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem (
input wire [1:0] edge_detection_control_slave_address, // edge_detection_control_slave.address
input wire edge_detection_control_slave_write_n, // .write_n
input wire [31:0] edge_detection_control_slave_writedata, // .writedata
input wire edge_detection_control_slave_chipselect, // .chipselect
output wire [31:0] edge_detection_control_slave_readdata, // .readdata
input wire sys_clk_clk, // sys_clk.clk
input wire sys_reset_reset_n, // sys_reset.reset_n
input wire [23:0] video_stream_sink_data, // video_stream_sink.data
input wire video_stream_sink_startofpacket, // .startofpacket
input wire video_stream_sink_endofpacket, // .endofpacket
input wire video_stream_sink_valid, // .valid
output wire video_stream_sink_ready, // .ready
input wire video_stream_source_ready, // video_stream_source.ready
output wire [23:0] video_stream_source_data, // .data
output wire video_stream_source_startofpacket, // .startofpacket
output wire video_stream_source_endofpacket, // .endofpacket
output wire video_stream_source_valid // .valid
);
wire chroma_filter_avalon_chroma_source_valid; // Chroma_Filter:stream_out_valid -> Edge_Detection:in_valid
wire [7:0] chroma_filter_avalon_chroma_source_data; // Chroma_Filter:stream_out_data -> Edge_Detection:in_data
wire chroma_filter_avalon_chroma_source_ready; // Edge_Detection:in_ready -> Chroma_Filter:stream_out_ready
wire chroma_filter_avalon_chroma_source_startofpacket; // Chroma_Filter:stream_out_startofpacket -> Edge_Detection:in_startofpacket
wire chroma_filter_avalon_chroma_source_endofpacket; // Chroma_Filter:stream_out_endofpacket -> Edge_Detection:in_endofpacket
wire chroma_upsampler_avalon_chroma_source_valid; // Chroma_Upsampler:stream_out_valid -> Video_Stream_Merger:stream_in_valid_1
wire [23:0] chroma_upsampler_avalon_chroma_source_data; // Chroma_Upsampler:stream_out_data -> Video_Stream_Merger:stream_in_data_1
wire chroma_upsampler_avalon_chroma_source_ready; // Video_Stream_Merger:stream_in_ready_1 -> Chroma_Upsampler:stream_out_ready
wire chroma_upsampler_avalon_chroma_source_startofpacket; // Chroma_Upsampler:stream_out_startofpacket -> Video_Stream_Merger:stream_in_startofpacket_1
wire chroma_upsampler_avalon_chroma_source_endofpacket; // Chroma_Upsampler:stream_out_endofpacket -> Video_Stream_Merger:stream_in_endofpacket_1
wire edge_detection_avalon_edge_detection_source_valid; // Edge_Detection:out_valid -> Chroma_Upsampler:stream_in_valid
wire [7:0] edge_detection_avalon_edge_detection_source_data; // Edge_Detection:out_data -> Chroma_Upsampler:stream_in_data
wire edge_detection_avalon_edge_detection_source_ready; // Chroma_Upsampler:stream_in_ready -> Edge_Detection:out_ready
wire edge_detection_avalon_edge_detection_source_startofpacket; // Edge_Detection:out_startofpacket -> Chroma_Upsampler:stream_in_startofpacket
wire edge_detection_avalon_edge_detection_source_endofpacket; // Edge_Detection:out_endofpacket -> Chroma_Upsampler:stream_in_endofpacket
wire video_stream_splitter_avalon_stream_router_source_0_valid; // Video_Stream_Splitter:stream_out_valid_0 -> Video_Stream_Merger:stream_in_valid_0
wire [23:0] video_stream_splitter_avalon_stream_router_source_0_data; // Video_Stream_Splitter:stream_out_data_0 -> Video_Stream_Merger:stream_in_data_0
wire video_stream_splitter_avalon_stream_router_source_0_ready; // Video_Stream_Merger:stream_in_ready_0 -> Video_Stream_Splitter:stream_out_ready_0
wire video_stream_splitter_avalon_stream_router_source_0_startofpacket; // Video_Stream_Splitter:stream_out_startofpacket_0 -> Video_Stream_Merger:stream_in_startofpacket_0
wire video_stream_splitter_avalon_stream_router_source_0_endofpacket; // Video_Stream_Splitter:stream_out_endofpacket_0 -> Video_Stream_Merger:stream_in_endofpacket_0
wire video_stream_splitter_avalon_stream_router_source_1_valid; // Video_Stream_Splitter:stream_out_valid_1 -> Chroma_Filter:stream_in_valid
wire [23:0] video_stream_splitter_avalon_stream_router_source_1_data; // Video_Stream_Splitter:stream_out_data_1 -> Chroma_Filter:stream_in_data
wire video_stream_splitter_avalon_stream_router_source_1_ready; // Chroma_Filter:stream_in_ready -> Video_Stream_Splitter:stream_out_ready_1
wire video_stream_splitter_avalon_stream_router_source_1_startofpacket; // Video_Stream_Splitter:stream_out_startofpacket_1 -> Chroma_Filter:stream_in_startofpacket
wire video_stream_splitter_avalon_stream_router_source_1_endofpacket; // Video_Stream_Splitter:stream_out_endofpacket_1 -> Chroma_Filter:stream_in_endofpacket
wire video_stream_splitter_avalon_sync_source_valid; // Video_Stream_Splitter:sync_valid -> Video_Stream_Merger:sync_valid
wire video_stream_splitter_avalon_sync_source_data; // Video_Stream_Splitter:sync_data -> Video_Stream_Merger:sync_data
wire video_stream_splitter_avalon_sync_source_ready; // Video_Stream_Merger:sync_ready -> Video_Stream_Splitter:sync_ready
wire edge_detection_router_controller_external_connection_export; // Edge_Detection_Router_Controller:out_port -> Video_Stream_Splitter:stream_select
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [Chroma_Filter:reset, Chroma_Upsampler:reset, Edge_Detection:reset, Edge_Detection_Router_Controller:reset_n, Video_Stream_Merger:reset, Video_Stream_Splitter:reset]
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Chroma_Filter chroma_filter (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (video_stream_splitter_avalon_stream_router_source_1_startofpacket), // avalon_chroma_sink.startofpacket
.stream_in_endofpacket (video_stream_splitter_avalon_stream_router_source_1_endofpacket), // .endofpacket
.stream_in_valid (video_stream_splitter_avalon_stream_router_source_1_valid), // .valid
.stream_in_ready (video_stream_splitter_avalon_stream_router_source_1_ready), // .ready
.stream_in_data (video_stream_splitter_avalon_stream_router_source_1_data), // .data
.stream_out_ready (chroma_filter_avalon_chroma_source_ready), // avalon_chroma_source.ready
.stream_out_startofpacket (chroma_filter_avalon_chroma_source_startofpacket), // .startofpacket
.stream_out_endofpacket (chroma_filter_avalon_chroma_source_endofpacket), // .endofpacket
.stream_out_valid (chroma_filter_avalon_chroma_source_valid), // .valid
.stream_out_data (chroma_filter_avalon_chroma_source_data) // .data
);
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Chroma_Upsampler chroma_upsampler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (edge_detection_avalon_edge_detection_source_startofpacket), // avalon_chroma_sink.startofpacket
.stream_in_endofpacket (edge_detection_avalon_edge_detection_source_endofpacket), // .endofpacket
.stream_in_valid (edge_detection_avalon_edge_detection_source_valid), // .valid
.stream_in_ready (edge_detection_avalon_edge_detection_source_ready), // .ready
.stream_in_data (edge_detection_avalon_edge_detection_source_data), // .data
.stream_out_ready (chroma_upsampler_avalon_chroma_source_ready), // avalon_chroma_source.ready
.stream_out_startofpacket (chroma_upsampler_avalon_chroma_source_startofpacket), // .startofpacket
.stream_out_endofpacket (chroma_upsampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_out_valid (chroma_upsampler_avalon_chroma_source_valid), // .valid
.stream_out_data (chroma_upsampler_avalon_chroma_source_data) // .data
);
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection edge_detection (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.in_data (chroma_filter_avalon_chroma_source_data), // avalon_edge_detection_sink.data
.in_startofpacket (chroma_filter_avalon_chroma_source_startofpacket), // .startofpacket
.in_endofpacket (chroma_filter_avalon_chroma_source_endofpacket), // .endofpacket
.in_valid (chroma_filter_avalon_chroma_source_valid), // .valid
.in_ready (chroma_filter_avalon_chroma_source_ready), // .ready
.out_ready (edge_detection_avalon_edge_detection_source_ready), // avalon_edge_detection_source.ready
.out_data (edge_detection_avalon_edge_detection_source_data), // .data
.out_startofpacket (edge_detection_avalon_edge_detection_source_startofpacket), // .startofpacket
.out_endofpacket (edge_detection_avalon_edge_detection_source_endofpacket), // .endofpacket
.out_valid (edge_detection_avalon_edge_detection_source_valid) // .valid
);
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Edge_Detection_Router_Controller edge_detection_router_controller (
.clk (sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (edge_detection_control_slave_address), // s1.address
.write_n (edge_detection_control_slave_write_n), // .write_n
.writedata (edge_detection_control_slave_writedata), // .writedata
.chipselect (edge_detection_control_slave_chipselect), // .chipselect
.readdata (edge_detection_control_slave_readdata), // .readdata
.out_port (edge_detection_router_controller_external_connection_export) // external_connection.export
);
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Merger video_stream_merger (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_data_0 (video_stream_splitter_avalon_stream_router_source_0_data), // avalon_stream_router_sink_0.data
.stream_in_startofpacket_0 (video_stream_splitter_avalon_stream_router_source_0_startofpacket), // .startofpacket
.stream_in_endofpacket_0 (video_stream_splitter_avalon_stream_router_source_0_endofpacket), // .endofpacket
.stream_in_valid_0 (video_stream_splitter_avalon_stream_router_source_0_valid), // .valid
.stream_in_ready_0 (video_stream_splitter_avalon_stream_router_source_0_ready), // .ready
.stream_in_data_1 (chroma_upsampler_avalon_chroma_source_data), // avalon_stream_router_sink_1.data
.stream_in_startofpacket_1 (chroma_upsampler_avalon_chroma_source_startofpacket), // .startofpacket
.stream_in_endofpacket_1 (chroma_upsampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_in_valid_1 (chroma_upsampler_avalon_chroma_source_valid), // .valid
.stream_in_ready_1 (chroma_upsampler_avalon_chroma_source_ready), // .ready
.sync_data (video_stream_splitter_avalon_sync_source_data), // avalon_sync_sink.data
.sync_valid (video_stream_splitter_avalon_sync_source_valid), // .valid
.sync_ready (video_stream_splitter_avalon_sync_source_ready), // .ready
.stream_out_ready (video_stream_source_ready), // avalon_stream_router_source.ready
.stream_out_data (video_stream_source_data), // .data
.stream_out_startofpacket (video_stream_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_stream_source_endofpacket), // .endofpacket
.stream_out_valid (video_stream_source_valid) // .valid
);
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Splitter video_stream_splitter (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_data (video_stream_sink_data), // avalon_stream_router_sink.data
.stream_in_startofpacket (video_stream_sink_startofpacket), // .startofpacket
.stream_in_endofpacket (video_stream_sink_endofpacket), // .endofpacket
.stream_in_valid (video_stream_sink_valid), // .valid
.stream_in_ready (video_stream_sink_ready), // .ready
.sync_ready (video_stream_splitter_avalon_sync_source_ready), // avalon_sync_source.ready
.sync_data (video_stream_splitter_avalon_sync_source_data), // .data
.sync_valid (video_stream_splitter_avalon_sync_source_valid), // .valid
.stream_out_ready_0 (video_stream_splitter_avalon_stream_router_source_0_ready), // avalon_stream_router_source_0.ready
.stream_out_data_0 (video_stream_splitter_avalon_stream_router_source_0_data), // .data
.stream_out_startofpacket_0 (video_stream_splitter_avalon_stream_router_source_0_startofpacket), // .startofpacket
.stream_out_endofpacket_0 (video_stream_splitter_avalon_stream_router_source_0_endofpacket), // .endofpacket
.stream_out_valid_0 (video_stream_splitter_avalon_stream_router_source_0_valid), // .valid
.stream_out_ready_1 (video_stream_splitter_avalon_stream_router_source_1_ready), // avalon_stream_router_source_1.ready
.stream_out_data_1 (video_stream_splitter_avalon_stream_router_source_1_data), // .data
.stream_out_startofpacket_1 (video_stream_splitter_avalon_stream_router_source_1_startofpacket), // .startofpacket
.stream_out_endofpacket_1 (video_stream_splitter_avalon_stream_router_source_1_endofpacket), // .endofpacket
.stream_out_valid_1 (video_stream_splitter_avalon_stream_router_source_1_valid), // .valid
.stream_select (edge_detection_router_controller_external_connection_export) // external_interface.export
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~sys_reset_reset_n), // reset_in0.reset
.clk (sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module altera_up_edge_detection_nonmaximum_suppression (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 9: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 7: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] shift_reg_out[ 1: 0];
// Internal Registers
reg [ 9: 0] original_line_1[ 2: 0];
reg [ 9: 0] original_line_2[ 2: 0];
reg [ 9: 0] original_line_3[ 2: 0];
reg [ 7: 0] suppress_level_1[ 4: 0];
reg [ 8: 0] suppress_level_2[ 2: 0];
reg [ 7: 0] suppress_level_3;
reg [ 1: 0] average_flags;
reg [ 7: 0] result;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
begin
for (i = 2; i >= 0; i = i-1)
begin
original_line_1[i] <= 10'h000;
original_line_2[i] <= 10'h000;
original_line_3[i] <= 10'h000;
end
for (i = 4; i >= 0; i = i-1)
begin
suppress_level_1[i] <= 8'h00;
end
suppress_level_2[0] <= 9'h000;
suppress_level_2[1] <= 9'h000;
suppress_level_2[2] <= 9'h000;
suppress_level_3 <= 8'h00;
average_flags <= 2'h0;
end
else if (data_en == 1'b1)
begin
for (i = 2; i > 0; i = i-1)
begin
original_line_1[i] <= original_line_1[i-1];
original_line_2[i] <= original_line_2[i-1];
original_line_3[i] <= original_line_3[i-1];
end
original_line_1[0] <= data_in;
original_line_2[0] <= shift_reg_out[0];
original_line_3[0] <= shift_reg_out[1];
suppress_level_1[0] <= original_line_2[1][ 7: 0];
case (original_line_2[1][9:8])
2'b00 :
begin
suppress_level_1[1] <= original_line_1[0][ 7: 0];
suppress_level_1[2] <= original_line_2[0][ 7: 0];
suppress_level_1[3] <= original_line_2[2][ 7: 0];
suppress_level_1[4] <= original_line_3[2][ 7: 0];
end
2'b01 :
begin
suppress_level_1[1] <= original_line_1[0][ 7: 0];
suppress_level_1[2] <= original_line_1[1][ 7: 0];
suppress_level_1[3] <= original_line_3[1][ 7: 0];
suppress_level_1[4] <= original_line_3[2][ 7: 0];
end
2'b10 :
begin
suppress_level_1[1] <= original_line_1[1][ 7: 0];
suppress_level_1[2] <= original_line_1[2][ 7: 0];
suppress_level_1[3] <= original_line_3[0][ 7: 0];
suppress_level_1[4] <= original_line_3[1][ 7: 0];
end
2'b11 :
begin
suppress_level_1[1] <= original_line_1[2][ 7: 0];
suppress_level_1[2] <= original_line_2[2][ 7: 0];
suppress_level_1[3] <= original_line_2[0][ 7: 0];
suppress_level_1[4] <= original_line_3[0][ 7: 0];
end
endcase
// Calculate Averages
suppress_level_2[0] <= {1'b0,suppress_level_1[0]};
suppress_level_2[1] <= {1'b0,suppress_level_1[1]} + {1'h0,suppress_level_1[2]};
suppress_level_2[2] <= {1'b0,suppress_level_1[3]} + {1'h0,suppress_level_1[3]};
// Calculate if pixel is nonmaximum
suppress_level_3 <= suppress_level_2[0][ 7: 0];
average_flags[0] <= (suppress_level_2[0][ 7: 0] >= suppress_level_2[1][ 8: 1]) ? 1'b1 : 1'b0;
average_flags[1] <= (suppress_level_2[0][ 7: 0] >= suppress_level_2[2][ 8: 1]) ? 1'b1 : 1'b0;
result <= (average_flags == 2'b11) ? suppress_level_3 : 8'h00;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign data_out = result;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_in),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 10,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 10,
shift_register_2.SIZE = WIDTH;
endmodule |
module Computer_System_VGA_Subsystem_VGA_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire vga_clk_clk, // vga_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire video_pll_locked_export; // video_pll:locked -> reset_from_locked:locked
Computer_System_VGA_Subsystem_VGA_PLL_video_pll video_pll (
.refclk (ref_clk_clk), // refclk.clk
.rst (ref_reset_reset), // reset.reset
.outclk_0 (), // outclk0.clk
.outclk_1 (vga_clk_clk), // outclk1.clk
.outclk_2 (), // outclk2.clk
.locked (video_pll_locked_export) // locked.export
);
altera_up_avalon_reset_from_locked_signal reset_from_locked (
.reset (reset_source_reset), // reset_source.reset
.locked (video_pll_locked_export) // locked.export
);
endmodule |
module Computer_System_Video_In_Subsystem_Video_In (
// Inputs
clk,
reset,
TD_CLK27,
TD_DATA,
TD_HS,
TD_VS,
clk27_reset,
stream_out_ready,
// Bidirectional
// Outputs
TD_RESET,
overflow_flag,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 7;
parameter OW = 15;
parameter FW = 17;
parameter PIXELS = 1280;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
input TD_VS;
input clk27_reset;
input stream_out_ready;
// Bidirectional
// Outputs
output TD_RESET;
output reg overflow_flag;
output [OW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire video_clk;
wire video_clk_reset;
wire [OW: 0] decoded_pixel;
wire decoded_startofpacket;
wire decoded_endofpacket;
wire decoded_valid;
wire [FW: 0] data_from_fifo;
wire [ 6: 0] fifo_used_words;
wire [ 6: 0] wrusedw;
wire wrfull;
wire rdempty;
// Internal Registers
reg reached_start_of_frame;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
overflow_flag <= 1'b0;
else if (decoded_valid & reached_start_of_frame & wrfull)
overflow_flag <= 1'b1;
end
// Internal Registers
always @(posedge video_clk)
begin
if (video_clk_reset)
reached_start_of_frame <= 1'b0;
else if (decoded_valid & decoded_startofpacket)
reached_start_of_frame <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign TD_RESET = 1'b1;
assign stream_out_data = data_from_fifo[OW: 0];
assign stream_out_startofpacket = data_from_fifo[(FW - 1)];
assign stream_out_endofpacket = data_from_fifo[FW];
assign stream_out_empty = 1'b0;
assign stream_out_valid = ~rdempty;
// Internal Assignments
assign video_clk = TD_CLK27;
assign video_clk_reset = clk27_reset;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// NTSC Video In Decoding
altera_up_video_itu_656_decoder ITU_R_656_Decoder (
// Inputs
.clk (video_clk),
.reset (video_clk_reset),
.TD_DATA (TD_DATA),
.ready (decoded_valid & ~wrfull),
// Bidirectionals
// Outputs
.data (decoded_pixel),
.startofpacket (decoded_startofpacket),
.endofpacket (decoded_endofpacket),
.valid (decoded_valid)
);
altera_up_video_dual_clock_fifo Video_In_Dual_Clock_FIFO (
// Inputs
.wrclk (video_clk),
.wrreq (decoded_valid & reached_start_of_frame & ~wrfull),
// .data ({1'b0, decoded_startofpacket, decoded_pixel}),
.data ({decoded_endofpacket, decoded_startofpacket, decoded_pixel}),
.rdclk (clk),
.rdreq (stream_out_valid & stream_out_ready),
// Bidirectionals
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (data_from_fifo),
.rdusedw (fifo_used_words),
.rdempty (rdempty)
);
defparam
Video_In_Dual_Clock_FIFO.DW = (FW + 1);
endmodule |
module altera_up_video_clipper_add (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (pass_inner_frame)
stream_out_data <= stream_in_data;
else
stream_out_data <= ADD_DATA;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= 'h0;
if (pass_inner_frame)
stream_out_valid <= stream_in_valid;
else
stream_out_valid <= 1'b1;
end
end
// Internal registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = pass_inner_frame & (~stream_out_valid | stream_out_ready);
// Internal assignments
assign increment_counters = (~stream_out_valid | stream_out_ready) &
(~pass_inner_frame | stream_in_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Add_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bidirectional
// Outputs
.start_of_outer_frame (new_startofpacket),
.end_of_outer_frame (new_endofpacket),
.start_of_inner_frame (),
.end_of_inner_frame (),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Add_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Add_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Add_Counters.WW = WW,
Clipper_Add_Counters.HW = HW,
Clipper_Add_Counters.LEFT_OFFSET = ADD_PIXELS_AT_START,
Clipper_Add_Counters.RIGHT_OFFSET = ADD_PIXELS_AT_END,
Clipper_Add_Counters.TOP_OFFSET = ADD_LINES_AT_START,
Clipper_Add_Counters.BOTTOM_OFFSET = ADD_LINES_AT_END;
endmodule |
module Computer_System_System_PLL (
input wire ref_clk_clk, // ref_clk.clk
input wire ref_reset_reset, // ref_reset.reset
output wire sys_clk_clk, // sys_clk.clk
output wire sdram_clk_clk, // sdram_clk.clk
output wire reset_source_reset // reset_source.reset
);
wire sys_pll_locked_export; // sys_pll:locked -> reset_from_locked:locked
Computer_System_System_PLL_sys_pll sys_pll (
.refclk (ref_clk_clk), // refclk.clk
.rst (ref_reset_reset), // reset.reset
.outclk_0 (sys_clk_clk), // outclk0.clk
.outclk_1 (sdram_clk_clk), // outclk1.clk
.locked (sys_pll_locked_export) // locked.export
);
altera_up_avalon_reset_from_locked_signal reset_from_locked (
.reset (reset_source_reset), // reset_source.reset
.locked (sys_pll_locked_export) // locked.export
);
endmodule |
module Computer_System_VGA_Subsystem_avalon_st_adapter #(
parameter inBitsPerSymbol = 10,
parameter inUsePackets = 1,
parameter inDataWidth = 30,
parameter inChannelWidth = 2,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 30,
parameter outChannelWidth = 0,
parameter outErrorWidth = 0,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [29:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
input wire in_0_startofpacket, // .startofpacket
input wire in_0_endofpacket, // .endofpacket
input wire [1:0] in_0_channel, // .channel
output wire [29:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire out_0_startofpacket, // .startofpacket
output wire out_0_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 10)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 30)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 30)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_VGA_Subsystem_avalon_st_adapter_channel_adapter_0 channel_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.in_startofpacket (in_0_startofpacket), // .startofpacket
.in_endofpacket (in_0_endofpacket), // .endofpacket
.in_channel (in_0_channel), // .channel
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_startofpacket (out_0_startofpacket), // .startofpacket
.out_endofpacket (out_0_endofpacket) // .endofpacket
);
endmodule |
module altera_up_edge_detection_pixel_info_shift_register (
clken,
clock,
shiftin,
shiftout,
taps);
parameter SIZE = 3628; // Shift reg size
input clken;
input clock;
input [1:0] shiftin;
output [1:0] shiftout;
output [1:0] taps;
wire [1:0] sub_wire0;
wire [1:0] sub_wire1;
wire [1:0] taps = sub_wire0[1:0];
wire [1:0] shiftout = sub_wire1[1:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire1));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 1,
altshift_taps_component.tap_distance = SIZE,
altshift_taps_component.width = 2;
endmodule |
module Computer_System_mm_interconnect_5 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP2_reset_reset_bridge_in_reset_reset, // Expansion_JP2_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi2_streamin_address, // Video_In_Subsystem_top_io_gpi2_streamin.address
input wire Video_In_Subsystem_top_io_gpi2_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi2_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi2_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo2_streamout_address, // Video_In_Subsystem_top_io_gpo2_streamout.address
input wire Video_In_Subsystem_top_io_gpo2_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo2_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo2_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP2_s1_address, // Expansion_JP2_s1.address
output wire Expansion_JP2_s1_write, // .write
input wire [31:0] Expansion_JP2_s1_readdata, // .readdata
output wire [31:0] Expansion_JP2_s1_writedata, // .writedata
output wire Expansion_JP2_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp2_s1_agent_m0_readdata; // Expansion_JP2_s1_translator:uav_readdata -> Expansion_JP2_s1_agent:m0_readdata
wire expansion_jp2_s1_agent_m0_waitrequest; // Expansion_JP2_s1_translator:uav_waitrequest -> Expansion_JP2_s1_agent:m0_waitrequest
wire expansion_jp2_s1_agent_m0_debugaccess; // Expansion_JP2_s1_agent:m0_debugaccess -> Expansion_JP2_s1_translator:uav_debugaccess
wire [3:0] expansion_jp2_s1_agent_m0_address; // Expansion_JP2_s1_agent:m0_address -> Expansion_JP2_s1_translator:uav_address
wire [3:0] expansion_jp2_s1_agent_m0_byteenable; // Expansion_JP2_s1_agent:m0_byteenable -> Expansion_JP2_s1_translator:uav_byteenable
wire expansion_jp2_s1_agent_m0_read; // Expansion_JP2_s1_agent:m0_read -> Expansion_JP2_s1_translator:uav_read
wire expansion_jp2_s1_agent_m0_readdatavalid; // Expansion_JP2_s1_translator:uav_readdatavalid -> Expansion_JP2_s1_agent:m0_readdatavalid
wire expansion_jp2_s1_agent_m0_lock; // Expansion_JP2_s1_agent:m0_lock -> Expansion_JP2_s1_translator:uav_lock
wire [31:0] expansion_jp2_s1_agent_m0_writedata; // Expansion_JP2_s1_agent:m0_writedata -> Expansion_JP2_s1_translator:uav_writedata
wire expansion_jp2_s1_agent_m0_write; // Expansion_JP2_s1_agent:m0_write -> Expansion_JP2_s1_translator:uav_write
wire [2:0] expansion_jp2_s1_agent_m0_burstcount; // Expansion_JP2_s1_agent:m0_burstcount -> Expansion_JP2_s1_translator:uav_burstcount
wire expansion_jp2_s1_agent_rf_source_valid; // Expansion_JP2_s1_agent:rf_source_valid -> Expansion_JP2_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp2_s1_agent_rf_source_data; // Expansion_JP2_s1_agent:rf_source_data -> Expansion_JP2_s1_agent_rsp_fifo:in_data
wire expansion_jp2_s1_agent_rf_source_ready; // Expansion_JP2_s1_agent_rsp_fifo:in_ready -> Expansion_JP2_s1_agent:rf_source_ready
wire expansion_jp2_s1_agent_rf_source_startofpacket; // Expansion_JP2_s1_agent:rf_source_startofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp2_s1_agent_rf_source_endofpacket; // Expansion_JP2_s1_agent:rf_source_endofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_valid; // Expansion_JP2_s1_agent_rsp_fifo:out_valid -> Expansion_JP2_s1_agent:rf_sink_valid
wire [74:0] expansion_jp2_s1_agent_rsp_fifo_out_data; // Expansion_JP2_s1_agent_rsp_fifo:out_data -> Expansion_JP2_s1_agent:rf_sink_data
wire expansion_jp2_s1_agent_rsp_fifo_out_ready; // Expansion_JP2_s1_agent:rf_sink_ready -> Expansion_JP2_s1_agent_rsp_fifo:out_ready
wire expansion_jp2_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP2_s1_agent:rf_sink_startofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP2_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP2_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP2_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP2_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP2_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP2_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP2_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi2_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo2_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp2_s1_agent_rp_valid; // Expansion_JP2_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp2_s1_agent_rp_data; // Expansion_JP2_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp2_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP2_s1_agent:rp_ready
wire expansion_jp2_s1_agent_rp_startofpacket; // Expansion_JP2_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp2_s1_agent_rp_endofpacket; // Expansion_JP2_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp2_s1_agent_rdata_fifo_src_valid; // Expansion_JP2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp2_s1_agent_rdata_fifo_src_data; // Expansion_JP2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP2_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi2_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi2_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi2_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi2_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi2_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo2_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo2_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo2_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo2_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo2_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp2_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp2_s1_agent_m0_read), // .read
.uav_write (expansion_jp2_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP2_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP2_s1_write), // .write
.av_readdata (Expansion_JP2_s1_readdata), // .readdata
.av_writedata (Expansion_JP2_s1_writedata), // .writedata
.av_chipselect (Expansion_JP2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi2_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo2_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp2_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp2_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp2_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp2_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp2_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp2_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp2_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp2_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp2_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp2_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule |
module altera_up_video_itu_656_decoder (
// Inputs
clk,
reset,
TD_DATA,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 7: 0] TD_DATA;
input ready;
// Bidirectional
// Outputs
output [15: 0] data;
output startofpacket;
output endofpacket;
output valid;
//output reg [15: 0] data;
//output reg startofpacket;
//output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire timing_reference; // 4-Bytes: FF 00 00 XY
wire start_of_an_even_line;
wire start_of_an_odd_line;
wire [ 7: 0] last_data;
// Internal Registers
reg [ 7: 0] io_register;
reg [ 7: 0] video_shift_reg [ 5: 1];
reg possible_timing_reference;
reg [ 6: 1] active_video;
reg last_line;
reg [15: 0] internal_data;
reg internal_startofpacket;
reg internal_valid;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
io_register <= TD_DATA;
// Output Registers
/*
always @ (posedge clk)
data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
startofpacket <= 1'b1;
else if (valid)
startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
valid <= valid ^ 1'b1;
else
valid <= 1'b0;
end
*/
// Internal Registers
always @ (posedge clk)
begin
for (i = 5; i > 1; i = i - 1)
video_shift_reg[i] <= video_shift_reg[(i - 1)];
video_shift_reg[1] <= io_register;
end
always @(posedge clk)
begin
if ((video_shift_reg[3] == 8'hFF) &&
(video_shift_reg[2] == 8'h00) &&
(video_shift_reg[1] == 8'h00))
possible_timing_reference <= 1'b1;
else
possible_timing_reference <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
active_video <= 6'h00;
else if (start_of_an_even_line | start_of_an_odd_line)
active_video <= {active_video[5:1], 1'b1};
else if (timing_reference == 1'b1)
active_video <= 6'h00;
else
active_video[6:2] <= active_video[5:1];
end
always @ (posedge clk)
begin
if (reset)
last_line <= 1'b0;
else if (start_of_an_odd_line)
last_line <= 1'b1;
else if (start_of_an_even_line)
last_line <= 1'b0;
end
always @ (posedge clk)
internal_data <= {video_shift_reg[5], video_shift_reg[4]};
always @ (posedge clk)
begin
if (~last_line & start_of_an_odd_line)
internal_startofpacket <= 1'b1;
else if (last_line & start_of_an_even_line)
internal_startofpacket <= 1'b1;
else if (valid)
internal_startofpacket <= 1'b0;
end
always @(posedge clk)
begin
if (active_video[5])
internal_valid <= internal_valid ^ 1'b1;
else
internal_valid <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign last_data = video_shift_reg[1];
assign timing_reference =
( possible_timing_reference &
( (last_data[5] ^ last_data[4]) == last_data[3]) &
( (last_data[6] ^ last_data[4]) == last_data[2]) &
( (last_data[6] ^ last_data[5]) == last_data[1]) &
( (last_data[6] ^ last_data[5] ^ last_data[4]) == last_data[0])
);
assign start_of_an_even_line = timing_reference &
last_data[6] & ~last_data[5] & ~last_data[4];
assign start_of_an_odd_line = timing_reference &
~last_data[6] & ~last_data[5] & ~last_data[4];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_decoder_add_endofpacket Add_EndofPacket (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (1'b0),
.stream_in_valid (internal_valid),
.stream_out_ready (ready),
// Bidirectional
// Outputs
.stream_in_ready (),
.stream_out_data (data),
.stream_out_startofpacket (startofpacket),
.stream_out_endofpacket (endofpacket),
.stream_out_valid (valid)
);
defparam
Add_EndofPacket.DW = 15;
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Set_Black_Transparent (
// Global Signals
clk,
reset,
// Input Stream
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_in_ready,
// Output Stream
stream_out_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 29; // Frame's Data Width (color portion only)
parameter DW = 39; // Frame's Data Width
parameter COLOR = 30'd0; // Color to apply alpha value
parameter ALPHA = 10'd0; // The alpha value to apply
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Global Signals
input clk;
input reset;
// Input Stream
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
output stream_in_ready;
// Output Stream
input stream_out_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign converted_data = (stream_in_data[CW:0] == COLOR) ?
{ALPHA, stream_in_data[CW:0]} :
stream_in_data;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_video_scaler_shrink (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter WW = 9; // Image In: width's address width
parameter HW = 9; // Image In: height's address width
parameter WIDTH_IN = 640; // Image In's width in pixels
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire drop;
wire capture_inputs;
wire transfer_data;
// Internal Registers
reg saved_startofpacket;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [WW: 0] width_counter;
reg [HW: 0] height_counter;
reg [ 3: 0] drop_pixel;
reg [ 3: 0] drop_line;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= data;
stream_out_startofpacket <= startofpacket;
stream_out_endofpacket <= endofpacket;
stream_out_valid <= valid;
end
else if (stream_out_ready & stream_out_valid)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
end
// Internal Registers
always @(posedge clk)
if (reset)
saved_startofpacket <= 1'b0;
else if (capture_inputs)
saved_startofpacket <= 1'b0;
else if (stream_in_ready)
saved_startofpacket <= saved_startofpacket | stream_in_startofpacket;
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (capture_inputs)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket | saved_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
else if (stream_in_ready)
endofpacket <= endofpacket | stream_in_endofpacket;
end
always @(posedge clk)
begin
if (reset)
width_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket | (width_counter == (WIDTH_IN - 1)))
width_counter <= 'h0;
else
width_counter <= width_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
height_counter <= 'h0;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
height_counter <= 'h0;
else if (width_counter == (WIDTH_IN - 1))
height_counter <= height_counter + 1;
end
end
always @(posedge clk)
begin
if (reset)
drop_pixel <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_pixel <= WIDTH_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_pixel <= WIDTH_DROP_MASK;
else
drop_pixel <= {drop_pixel[2:0], drop_pixel[3]};
end
end
always @(posedge clk)
begin
if (reset)
drop_line <= 4'b0000;
else if (stream_in_ready)
begin
if (stream_in_startofpacket)
drop_line <= HEIGHT_DROP_MASK;
else if (width_counter == (WIDTH_IN - 1))
drop_line <= {drop_line[2:0], drop_line[3]};
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (drop | ~valid | transfer_data);
// Internal Assignments
assign drop = drop_pixel[0] | drop_line[0];
assign capture_inputs = stream_in_ready & ~drop;
assign transfer_data = ~stream_out_valid & stream_in_valid & ~drop;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_video_clipper_drop (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Image in width in pixels
parameter IMAGE_HEIGHT = 480; // Image in height in lines
parameter WW = 9; // Image in width address width
parameter HW = 8; // Image in height address width
parameter DROP_PIXELS_AT_START = 0;
parameter DROP_PIXELS_AT_END = 0;
parameter DROP_LINES_AT_START = 0;
parameter DROP_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam STATE_0_WAIT_FOR_START = 2'h0,
STATE_1_RUN_CLIPPER = 2'h1,
STATE_2_ADD_MISSING_PART = 2'h2;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire full_frame_endofpacket;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
reg [ 1: 0] s_video_clipper_drop;
reg [ 1: 0] ns_video_clipper_drop;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_video_clipper_drop <= STATE_0_WAIT_FOR_START;
else
s_video_clipper_drop <= ns_video_clipper_drop;
end
always @(*)
begin
case (s_video_clipper_drop)
STATE_0_WAIT_FOR_START:
begin
if (stream_in_startofpacket & stream_in_valid)
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
else
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
STATE_1_RUN_CLIPPER:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else if (increment_counters & stream_in_endofpacket)
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
else
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
end
STATE_2_ADD_MISSING_PART:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
end
default:
begin
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_data <= ADD_DATA;
else
stream_out_data <= stream_in_data;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= stream_in_empty;
if (s_video_clipper_drop == STATE_1_RUN_CLIPPER)
stream_out_valid <= pass_inner_frame & stream_in_valid;
else if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_valid <= pass_inner_frame;
else
stream_out_valid <= 1'b0;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready =
(s_video_clipper_drop == STATE_0_WAIT_FOR_START) ?
~(stream_in_startofpacket & stream_in_valid) :
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
// Internal Assignments
assign increment_counters =
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
stream_in_valid & stream_in_ready :
(s_video_clipper_drop == STATE_2_ADD_MISSING_PART) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Drop_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bi-Directional
// Outputs
.start_of_outer_frame (),
.end_of_outer_frame (full_frame_endofpacket),
.start_of_inner_frame (new_startofpacket),
.end_of_inner_frame (new_endofpacket),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Drop_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Drop_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Drop_Counters.WW = WW,
Clipper_Drop_Counters.HW = HW,
Clipper_Drop_Counters.LEFT_OFFSET = DROP_PIXELS_AT_START,
Clipper_Drop_Counters.RIGHT_OFFSET = DROP_PIXELS_AT_END,
Clipper_Drop_Counters.TOP_OFFSET = DROP_LINES_AT_START,
Clipper_Drop_Counters.BOTTOM_OFFSET = DROP_LINES_AT_END;
endmodule |
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_video_decoder_add_endofpacket (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire internal_ready;
// Internal Registers
reg [DW: 0] internal_data;
reg internal_startofpacket;
reg internal_endofpacket;
reg internal_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_in_ready & stream_in_valid)
begin
stream_out_data <= internal_data;
stream_out_startofpacket <= internal_startofpacket;
stream_out_endofpacket <= internal_endofpacket | stream_in_startofpacket;
stream_out_valid <= internal_valid;
end
else if (stream_out_ready)
stream_out_valid <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
internal_data <= 'h0;
internal_startofpacket <= 1'b0;
internal_endofpacket <= 1'b0;
internal_valid <= 1'b0;
end
else if (stream_in_ready & stream_in_valid)
begin
internal_data <= stream_in_data;
internal_startofpacket <= stream_in_startofpacket;
internal_endofpacket <= stream_in_endofpacket;
internal_valid <= stream_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_video_dma_control_slave (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
swap_addresses_enable,
// Bi-Directional
// Outputs
readdata,
current_start_address,
dma_enabled
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter DEFAULT_BUFFER_ADDRESS = 32'h00000000;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'h00000000;
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter ADDRESSING_BITS = 16'h0809;
parameter COLOR_BITS = 4'h7; // Bits per color plane minus 1
parameter COLOR_PLANES = 2'h2; // Color planes per pixel minus 1
parameter ADDRESSING_MODE = 1'b1; // 0: X-Y or 1: Consecutive
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input swap_addresses_enable;
// Bi-Directional
// Outputs
output reg [31: 0] readdata;
output [31: 0] current_start_address;
output reg dma_enabled;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [31: 0] buffer_start_address;
reg [31: 0] back_buf_start_address;
reg buffer_swap;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (read & (address == 2'h0))
readdata <= buffer_start_address;
else if (read & (address == 2'h1))
readdata <= back_buf_start_address;
else if (read & (address == 2'h2))
begin
readdata[31:16] <= HEIGHT;
readdata[15: 0] <= WIDTH;
end
else if (read)
begin
readdata[31:16] <= ADDRESSING_BITS;
readdata[15:12] <= 4'h0;
readdata[11: 8] <= COLOR_BITS;
readdata[ 7: 6] <= COLOR_PLANES;
readdata[ 5: 3] <= 3'h0;
readdata[ 2] <= dma_enabled;
readdata[ 1] <= ADDRESSING_MODE;
readdata[ 0] <= buffer_swap;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
buffer_start_address <= DEFAULT_BUFFER_ADDRESS;
back_buf_start_address <= DEFAULT_BACK_BUF_ADDRESS;
end
else if (write & (address == 2'h1))
begin
if (byteenable[0])
back_buf_start_address[ 7: 0] <= writedata[ 7: 0];
if (byteenable[1])
back_buf_start_address[15: 8] <= writedata[15: 8];
if (byteenable[2])
back_buf_start_address[23:16] <= writedata[23:16];
if (byteenable[3])
back_buf_start_address[31:24] <= writedata[31:24];
end
else if (buffer_swap & swap_addresses_enable)
begin
buffer_start_address <= back_buf_start_address;
back_buf_start_address <= buffer_start_address;
end
end
always @(posedge clk)
begin
if (reset)
buffer_swap <= 1'b0;
else if (write & (address == 2'h0))
buffer_swap <= 1'b1;
else if (swap_addresses_enable)
buffer_swap <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
dma_enabled <= DEFAULT_DMA_ENABLED;
else if (write & (address == 2'h3) & byteenable[0])
dma_enabled <= writedata[2];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign current_start_address = buffer_start_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_VGA_Pixel_DMA (
// Inputs
clk,
reset,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
master_readdata,
master_readdatavalid,
master_waitrequest,
stream_ready,
// Bi-Directional
// Outputs
slave_readdata,
master_address,
master_arbiterlock,
master_read,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter DEFAULT_BUFFER_ADDRESS = 32'd134217728;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd134217728;
parameter WW = 8; // Image width's address width
parameter HW = 7; // Image height's address width
parameter MW = 15; // Avalon master's data width
parameter DW = 15; // Image pixel width
parameter EW = 0; // Streaming empty signel width
parameter PIXELS = 320; // Image width - number of pixels
parameter LINES = 240; // Image height - number of lines
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
input [MW: 0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input stream_ready;
// Bi-Directional
// Outputs
output reg [31: 0] slave_readdata;
output [31: 0] master_address;
output master_arbiterlock;
output master_read;
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
//wire [ 9: 0] red;
//wire [ 9: 0] green;
//wire [ 9: 0] blue;
// Data fifo signals
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [31: 0] buffer_start_address;
reg [31: 0] back_buf_start_address;
reg buffer_swap;
reg [ 3: 0] pending_reads;
reg reading_first_pixel_in_image;
reg [WW: 0] pixel_address;
reg [HW: 0] line_address;
// State Machine Registers
reg [ 1: 0] s_pixel_buffer;
reg [ 1: 0] ns_pixel_buffer;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_pixel_buffer <= STATE_0_IDLE;
else
s_pixel_buffer <= ns_pixel_buffer;
end
always @(*)
begin
case (s_pixel_buffer)
STATE_0_IDLE:
begin
if (fifo_almost_empty)
ns_pixel_buffer = STATE_2_READ_BUFFER;
else
ns_pixel_buffer = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_pixel_buffer = STATE_0_IDLE;
else
ns_pixel_buffer = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if ((pixel_address == (PIXELS - 1)) &
(line_address == (LINES - 1)))
ns_pixel_buffer = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_pixel_buffer = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_pixel_buffer = STATE_3_MAX_PENDING_READS_STALL;
else
ns_pixel_buffer = STATE_2_READ_BUFFER;
end
else
ns_pixel_buffer = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_pixel_buffer = STATE_2_READ_BUFFER;
else
ns_pixel_buffer = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_pixel_buffer = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
slave_readdata <= 32'h00000000;
else if (slave_read & (slave_address == 2'h0))
slave_readdata <= buffer_start_address;
else if (slave_read & (slave_address == 2'h1))
slave_readdata <= back_buf_start_address;
else if (slave_read & (slave_address == 2'h2))
begin
slave_readdata[31:16] <= LINES;
slave_readdata[15: 0] <= PIXELS;
end
else if (slave_read)
begin
slave_readdata[31:24] <= HW + 8'h01;
slave_readdata[23:16] <= WW + 8'h01;
slave_readdata[15: 8] <= 8'h00;
slave_readdata[ 7: 4] <= 4'h2;
slave_readdata[ 3: 2] <= 2'h0;
slave_readdata[ 1] <= 1'b0;
slave_readdata[ 0] <= buffer_swap;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
buffer_start_address <= DEFAULT_BUFFER_ADDRESS;
back_buf_start_address <= DEFAULT_BACK_BUF_ADDRESS;
end
else if (slave_write & (slave_address == 2'h1))
begin
if (slave_byteenable[0])
back_buf_start_address[ 7: 0] <= slave_writedata[ 7: 0];
if (slave_byteenable[1])
back_buf_start_address[15: 8] <= slave_writedata[15: 8];
if (slave_byteenable[2])
back_buf_start_address[23:16] <= slave_writedata[23:16];
if (slave_byteenable[3])
back_buf_start_address[31:24] <= slave_writedata[31:24];
end
else if (buffer_swap & master_read & ~master_waitrequest &
((pixel_address == (PIXELS - 1)) &
(line_address == (LINES - 1))))
begin
buffer_start_address <= back_buf_start_address;
back_buf_start_address <= buffer_start_address;
end
end
always @(posedge clk)
begin
if (reset)
buffer_swap <= 1'b0;
else if (slave_write & (slave_address == 2'h0))
buffer_swap <= 1'b1;
else if ((pixel_address == 0) & (line_address == 0))
buffer_swap <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
reading_first_pixel_in_image <= 1'b0;
else if ((s_pixel_buffer == STATE_0_IDLE) &
((pixel_address == 0) & (line_address == 0)))
reading_first_pixel_in_image <= 1'b1;
else if (master_readdatavalid)
reading_first_pixel_in_image <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
pixel_address <= 'h0;
else if (master_read & ~master_waitrequest)
begin
if (pixel_address == (PIXELS - 1))
pixel_address <= 'h0;
else
pixel_address <= pixel_address + 1;
end
end
always @(posedge clk)
begin
if (reset)
line_address <= 'h0;
else if ((master_read & ~master_waitrequest) &&
(pixel_address == (PIXELS - 1)))
begin
if (line_address == (LINES - 1))
line_address <= 'h0;
else
line_address <= line_address + 1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
{line_address, pixel_address, 1'b0};
assign master_arbiterlock = !((s_pixel_buffer == STATE_2_READ_BUFFER) |
(s_pixel_buffer == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_pixel_buffer == STATE_2_READ_BUFFER);
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = reading_first_pixel_in_image;
assign fifo_data_in[DW+2] = (s_pixel_buffer == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full)
// synopsys translate_off
,
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule |
module altera_up_YCrCb_to_RGB_converter (
// Inputs
clk,
clk_en,
reset,
Y,
Cr,
Cb,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
// Bidirectionals
// Outputs
R,
G,
B,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input reset;
input [ 7: 0] Y;
input [ 7: 0] Cr;
input [ 7: 0] Cb;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_empty;
input stream_in_valid;
// Bidirectionals
// Outputs
output reg [ 7: 0] R;
output reg [ 7: 0] G;
output reg [ 7: 0] B;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [35: 0] product_0;
wire [35: 0] product_1;
wire [35: 0] product_2;
wire [35: 0] product_3;
wire [35: 0] product_4;
wire [10: 0] R_sum;
wire [10: 0] G_sum;
wire [10: 0] B_sum;
// Internal Registers
reg [10: 0] Y_sub;
reg [10: 0] Cr_sub;
reg [10: 0] Cb_sub;
reg [10: 0] Y_1d1640;
reg [10: 0] Cr_0d813;
reg [10: 0] Cr_1d596;
reg [10: 0] Cb_2d017;
reg [10: 0] Cb_0d392;
reg [ 1: 0] startofpacket_shift_reg;
reg [ 1: 0] endofpacket_shift_reg;
reg [ 1: 0] empty_shift_reg;
reg [ 1: 0] valid_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
R <= 8'h00;
G <= 8'h00;
B <= 8'h00;
end
else if (clk_en)
begin
if (R_sum[10] == 1'b1) // Negative number
R <= 8'h00;
else if ((R_sum[9] | R_sum[8]) == 1'b1) // Number greater than 255
R <= 8'hFF;
else
R <= R_sum[7:0];
if (G_sum[10] == 1'b1) // Negative number
G <= 8'h00;
else if ((G_sum[9] | G_sum[8]) == 1'b1) // Number greater than 255
G <= 8'hFF;
else
G <= G_sum[7:0];
if (B_sum[10] == 1'b1) // Negative number
B <= 8'h00;
else if ((B_sum[9] | B_sum[8]) == 1'b1) // Number greater than 255
B <= 8'hFF;
else
B <= B_sum[7:0];
end
end
always @ (posedge clk)
begin
if (clk_en)
begin
stream_out_startofpacket <= startofpacket_shift_reg[1];
stream_out_endofpacket <= endofpacket_shift_reg[1];
stream_out_empty <= empty_shift_reg[1];
stream_out_valid <= valid_shift_reg[1];
end
end
// Internal Registers
// ---------------------------------------------------------------------------
//
// Offset Y, Cr, and Cb.
// Note: Internal wires are all 11 bits from here out, to allow for
// increasing bit extent due to additions, subtractions, and multiplies
// Note: Signs are not extended when appropriate.
always @ (posedge clk)
begin
if (reset)
begin
Y_sub <= 11'h000;
Cr_sub <= 11'h000;
Cb_sub <= 11'h000;
end
else if (clk_en)
begin
// Y_sub <= ({{3{Y[7]}}, Y} - 'd16); // result always positive
// Cr_sub <= ({{3{Cr[7]}}, Cr} - 'd128); // result is positive or negative
// Cb_sub <= ({{3{Cb[7]}}, Cb} - 'd128); // result is positive or negative
Y_sub <= ({3'b000, Y} - 11'd16); // result always positive
Cr_sub <= ({3'b000, Cr} - 11'd128); // result is positive or negative
Cb_sub <= ({3'b000, Cb} - 11'd128); // result is positive or negative
end
end
always @ (posedge clk)
begin
if (reset)
begin
Y_1d1640 <= 11'h000;
Cr_0d813 <= 11'h000;
Cr_1d596 <= 11'h000;
Cb_2d017 <= 11'h000;
Cb_0d392 <= 11'h000;
end
else if (clk_en)
begin
Y_1d1640 <= product_0[25:15];
Cr_0d813 <= product_1[25:15];
Cr_1d596 <= product_2[25:15];
Cb_2d017 <= product_3[25:15];
Cb_0d392 <= product_4[25:15];
end
end
always @(posedge clk)
begin
if (reset)
begin
startofpacket_shift_reg <= 2'h0;
endofpacket_shift_reg <= 2'h0;
empty_shift_reg <= 2'h0;
valid_shift_reg <= 2'h0;
end
else if (clk_en)
begin
startofpacket_shift_reg[1] <= startofpacket_shift_reg[0];
endofpacket_shift_reg[1] <= endofpacket_shift_reg[0];
empty_shift_reg[1] <= empty_shift_reg[0];
valid_shift_reg[1] <= valid_shift_reg[0];
startofpacket_shift_reg[0] <= stream_in_startofpacket;
endofpacket_shift_reg[0] <= stream_in_endofpacket;
empty_shift_reg[0] <= stream_in_empty;
valid_shift_reg[0] <= stream_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
// ---------------------------------------------------------------------------
//
// Sum the proper outputs from the multiply to form R'G'B'
//
assign R_sum = Y_1d1640 + Cr_1d596;
assign G_sum = Y_1d1640 - Cr_0d813 - Cb_0d392;
assign B_sum = Y_1d1640 + Cb_2d017;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// Formula Set #1
// ---------------------------------------------------------------------------
// R' = 1.164(Y-16) + 1.596(Cr-128)
// G' = 1.164(Y-16) - .813(Cr-128) - .392(Cb-128)
// B' = 1.164(Y-16) + 2.017(Cb-128)
//
// use full precision of multiply to experiment with coefficients
// 1.164 -> I[1:0].F[14:0] .164 X 2^15 = 094FD or 00 1.001 0100 1111 1101
// 0.813 -> I[1:0].F[14:0] .813 X 2^15 = 06810 or 00 0.110 1000 0001 0000
// 1.596 -> I[1:0].F[14:0] .596 X 2^15 = 0CC49 or 00 1.100 1100 0100 1001
// 2.017 -> I[1:0].F[14:0] .017 X 2^15 = 1022D or 01 0.000 0010 0010 1101
// 0.392 -> I[1:0].F[14:0] .392 X 2^15 = 0322D or 00 0.011 0010 0010 1101
lpm_mult lpm_mult_component_0 (
// Inputs
.dataa ({{7{Y_sub[10]}}, Y_sub}),
.datab (18'h094FD),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_0),
.sum (1'b0)
);
defparam
lpm_mult_component_0.lpm_widtha = 18,
lpm_mult_component_0.lpm_widthb = 18,
lpm_mult_component_0.lpm_widthp = 36,
lpm_mult_component_0.lpm_widths = 1,
lpm_mult_component_0.lpm_type = "LPM_MULT",
lpm_mult_component_0.lpm_representation = "SIGNED",
lpm_mult_component_0.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_1 (
// Inputs
.dataa ({{7{Cr_sub[10]}}, Cr_sub}),
.datab (18'h06810),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_1),
.sum (1'b0)
);
defparam
lpm_mult_component_1.lpm_widtha = 18,
lpm_mult_component_1.lpm_widthb = 18,
lpm_mult_component_1.lpm_widthp = 36,
lpm_mult_component_1.lpm_widths = 1,
lpm_mult_component_1.lpm_type = "LPM_MULT",
lpm_mult_component_1.lpm_representation = "SIGNED",
lpm_mult_component_1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_2 (
// Inputs
.dataa ({{7{Cr_sub[10]}}, Cr_sub}),
.datab (18'h0CC49),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_2),
.sum (1'b0)
);
defparam
lpm_mult_component_2.lpm_widtha = 18,
lpm_mult_component_2.lpm_widthb = 18,
lpm_mult_component_2.lpm_widthp = 36,
lpm_mult_component_2.lpm_widths = 1,
lpm_mult_component_2.lpm_type = "LPM_MULT",
lpm_mult_component_2.lpm_representation = "SIGNED",
lpm_mult_component_2.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_3 (
// Inputs
.dataa ({{7{Cb_sub[10]}}, Cb_sub}),
.datab (18'h1022D),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_3),
.sum (1'b0)
);
defparam
lpm_mult_component_3.lpm_widtha = 18,
lpm_mult_component_3.lpm_widthb = 18,
lpm_mult_component_3.lpm_widthp = 36,
lpm_mult_component_3.lpm_widths = 1,
lpm_mult_component_3.lpm_type = "LPM_MULT",
lpm_mult_component_3.lpm_representation = "SIGNED",
lpm_mult_component_3.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_4 (
// Inputs
.dataa ({{7{Cb_sub[10]}}, Cb_sub}),
.datab (18'h0322D),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_4),
.sum (1'b0)
);
defparam
lpm_mult_component_4.lpm_widtha = 18,
lpm_mult_component_4.lpm_widthb = 18,
lpm_mult_component_4.lpm_widthp = 36,
lpm_mult_component_4.lpm_widths = 1,
lpm_mult_component_4.lpm_type = "LPM_MULT",
lpm_mult_component_4.lpm_representation = "SIGNED",
lpm_mult_component_4.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
// Formula Set #2
// ---------------------------------------------------------------------------
// R = Y + 1.402 (Cr-128)
// G = Y - 0.71414 (Cr-128) - 0.34414 (Cb-128)
// B = Y + 1.772 (Cb-128)
//
// use full precision of multiply to experiment with coefficients
// 1.00000 -> I[0].F[16:0] 1.00000 X 2^15 = 08000
// 1.40200 -> I[0].F[16:0] 1.40200 X 2^15 = 0B375
// 0.71414 -> I[0].F[16:0] 0.71414 X 2^15 = 05B69
// 0.34414 -> I[0].F[16:0] 0.34414 X 2^15 = 02C0D
// 1.77200 -> I[0].F[16:0] 1.77200 X 2^15 = 0E2D1
endmodule |
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Merger (
// Inputs
clk,
reset,
sync_data,
sync_valid,
stream_in_data_0,
stream_in_startofpacket_0,
stream_in_endofpacket_0,
stream_in_empty_0,
stream_in_valid_0,
stream_in_data_1,
stream_in_startofpacket_1,
stream_in_endofpacket_1,
stream_in_empty_1,
stream_in_valid_1,
stream_out_ready,
// Bidirectional
// Outputs
sync_ready,
stream_in_ready_0,
stream_in_ready_1,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 23; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input sync_data;
input sync_valid;
input [DW: 0] stream_in_data_0;
input stream_in_startofpacket_0;
input stream_in_endofpacket_0;
input [EW: 0] stream_in_empty_0;
input stream_in_valid_0;
input [DW: 0] stream_in_data_1;
input stream_in_startofpacket_1;
input stream_in_endofpacket_1;
input [EW: 0] stream_in_empty_1;
input stream_in_valid_1;
input stream_out_ready;
// Bidirectional
// Outputs
output sync_ready;
output stream_in_ready_0;
output stream_in_ready_1;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire enable_setting_stream_select;
// Internal Registers
reg between_frames;
reg stream_select_reg;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_in_ready_0)
begin
stream_out_data <= stream_in_data_0;
stream_out_startofpacket <= stream_in_startofpacket_0;
stream_out_endofpacket <= stream_in_endofpacket_0;
stream_out_empty <= stream_in_empty_0;
stream_out_valid <= stream_in_valid_0;
end
else if (stream_in_ready_1)
begin
stream_out_data <= stream_in_data_1;
stream_out_startofpacket <= stream_in_startofpacket_1;
stream_out_endofpacket <= stream_in_endofpacket_1;
stream_out_empty <= stream_in_empty_1;
stream_out_valid <= stream_in_valid_1;
end
else if (stream_out_ready)
stream_out_valid <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
between_frames <= 1'b1;
else if (stream_in_ready_0 & stream_in_endofpacket_0)
between_frames <= 1'b1;
else if (stream_in_ready_1 & stream_in_endofpacket_1)
between_frames <= 1'b1;
else if (stream_in_ready_0 & stream_in_startofpacket_0)
between_frames <= 1'b0;
else if (stream_in_ready_1 & stream_in_startofpacket_1)
between_frames <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
stream_select_reg <= 1'b0;
else if (enable_setting_stream_select & sync_valid)
stream_select_reg <= sync_data;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign sync_ready = enable_setting_stream_select;
assign stream_in_ready_0 = (stream_select_reg) ?
1'b0 : stream_in_valid_0 & (~stream_out_valid | stream_out_ready);
assign stream_in_ready_1 = (stream_select_reg) ?
stream_in_valid_1 & (~stream_out_valid | stream_out_ready) : 1'b0;
// Internal Assignments
assign enable_setting_stream_select =
(stream_in_ready_0 & stream_in_endofpacket_0) |
(stream_in_ready_1 & stream_in_endofpacket_1) |
(~(stream_in_ready_0 & stream_in_startofpacket_0) & between_frames) |
(~(stream_in_ready_1 & stream_in_startofpacket_1) & between_frames);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_mm_interconnect_4 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP1_reset_reset_bridge_in_reset_reset, // Expansion_JP1_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi1_streamin_address, // Video_In_Subsystem_top_io_gpi1_streamin.address
input wire Video_In_Subsystem_top_io_gpi1_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi1_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi1_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo1_streamout_address, // Video_In_Subsystem_top_io_gpo1_streamout.address
input wire Video_In_Subsystem_top_io_gpo1_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo1_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo1_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP1_s1_address, // Expansion_JP1_s1.address
output wire Expansion_JP1_s1_write, // .write
input wire [31:0] Expansion_JP1_s1_readdata, // .readdata
output wire [31:0] Expansion_JP1_s1_writedata, // .writedata
output wire Expansion_JP1_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi1_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi1_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi1_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo1_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo1_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo1_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp1_s1_agent_m0_readdata; // Expansion_JP1_s1_translator:uav_readdata -> Expansion_JP1_s1_agent:m0_readdata
wire expansion_jp1_s1_agent_m0_waitrequest; // Expansion_JP1_s1_translator:uav_waitrequest -> Expansion_JP1_s1_agent:m0_waitrequest
wire expansion_jp1_s1_agent_m0_debugaccess; // Expansion_JP1_s1_agent:m0_debugaccess -> Expansion_JP1_s1_translator:uav_debugaccess
wire [3:0] expansion_jp1_s1_agent_m0_address; // Expansion_JP1_s1_agent:m0_address -> Expansion_JP1_s1_translator:uav_address
wire [3:0] expansion_jp1_s1_agent_m0_byteenable; // Expansion_JP1_s1_agent:m0_byteenable -> Expansion_JP1_s1_translator:uav_byteenable
wire expansion_jp1_s1_agent_m0_read; // Expansion_JP1_s1_agent:m0_read -> Expansion_JP1_s1_translator:uav_read
wire expansion_jp1_s1_agent_m0_readdatavalid; // Expansion_JP1_s1_translator:uav_readdatavalid -> Expansion_JP1_s1_agent:m0_readdatavalid
wire expansion_jp1_s1_agent_m0_lock; // Expansion_JP1_s1_agent:m0_lock -> Expansion_JP1_s1_translator:uav_lock
wire [31:0] expansion_jp1_s1_agent_m0_writedata; // Expansion_JP1_s1_agent:m0_writedata -> Expansion_JP1_s1_translator:uav_writedata
wire expansion_jp1_s1_agent_m0_write; // Expansion_JP1_s1_agent:m0_write -> Expansion_JP1_s1_translator:uav_write
wire [2:0] expansion_jp1_s1_agent_m0_burstcount; // Expansion_JP1_s1_agent:m0_burstcount -> Expansion_JP1_s1_translator:uav_burstcount
wire expansion_jp1_s1_agent_rf_source_valid; // Expansion_JP1_s1_agent:rf_source_valid -> Expansion_JP1_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp1_s1_agent_rf_source_data; // Expansion_JP1_s1_agent:rf_source_data -> Expansion_JP1_s1_agent_rsp_fifo:in_data
wire expansion_jp1_s1_agent_rf_source_ready; // Expansion_JP1_s1_agent_rsp_fifo:in_ready -> Expansion_JP1_s1_agent:rf_source_ready
wire expansion_jp1_s1_agent_rf_source_startofpacket; // Expansion_JP1_s1_agent:rf_source_startofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp1_s1_agent_rf_source_endofpacket; // Expansion_JP1_s1_agent:rf_source_endofpacket -> Expansion_JP1_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_valid; // Expansion_JP1_s1_agent_rsp_fifo:out_valid -> Expansion_JP1_s1_agent:rf_sink_valid
wire [74:0] expansion_jp1_s1_agent_rsp_fifo_out_data; // Expansion_JP1_s1_agent_rsp_fifo:out_data -> Expansion_JP1_s1_agent:rf_sink_data
wire expansion_jp1_s1_agent_rsp_fifo_out_ready; // Expansion_JP1_s1_agent:rf_sink_ready -> Expansion_JP1_s1_agent_rsp_fifo:out_ready
wire expansion_jp1_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP1_s1_agent:rf_sink_startofpacket
wire expansion_jp1_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP1_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP1_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP1_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP1_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP1_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP1_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP1_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP1_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi1_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi1_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo1_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo1_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp1_s1_agent_rp_valid; // Expansion_JP1_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp1_s1_agent_rp_data; // Expansion_JP1_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp1_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP1_s1_agent:rp_ready
wire expansion_jp1_s1_agent_rp_startofpacket; // Expansion_JP1_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp1_s1_agent_rp_endofpacket; // Expansion_JP1_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp1_s1_agent_rdata_fifo_src_valid; // Expansion_JP1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp1_s1_agent_rdata_fifo_src_data; // Expansion_JP1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP1_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi1_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi1_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi1_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi1_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi1_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo1_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo1_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo1_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo1_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo1_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp1_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp1_s1_agent_m0_read), // .read
.uav_write (expansion_jp1_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP1_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP1_s1_write), // .write
.av_readdata (Expansion_JP1_s1_readdata), // .readdata
.av_writedata (Expansion_JP1_s1_writedata), // .writedata
.av_chipselect (Expansion_JP1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi1_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi1_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo1_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo1_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp1_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp1_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp1_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp1_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp1_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp1_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp1_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp1_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp1_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp1_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp1_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi1_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi1_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi1_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi1_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo1_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo1_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo1_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo1_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp1_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp1_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp1_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp1_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP1_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule |
module Computer_System_Video_In_Subsystem_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 16,
parameter inUsePackets = 1,
parameter inDataWidth = 16,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 1,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 16,
parameter outChannelWidth = 0,
parameter outErrorWidth = 0,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [15:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
input wire in_0_startofpacket, // .startofpacket
input wire in_0_endofpacket, // .endofpacket
input wire in_0_empty, // .empty
output wire [15:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire out_0_startofpacket, // .startofpacket
output wire out_0_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_Video_In_Subsystem_avalon_st_adapter_001_data_format_adapter_0 data_format_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.in_startofpacket (in_0_startofpacket), // .startofpacket
.in_endofpacket (in_0_endofpacket), // .endofpacket
.in_empty (in_0_empty), // .empty
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_startofpacket (out_0_startofpacket), // .startofpacket
.out_endofpacket (out_0_endofpacket) // .endofpacket
);
endmodule |
module Computer_System_VGA_Subsystem_VGA_Alpha_Blender (
// Inputs
clk,
reset,
background_data,
background_startofpacket,
background_endofpacket,
background_empty,
background_valid,
foreground_data,
foreground_startofpacket,
foreground_endofpacket,
foreground_empty,
foreground_valid,
output_ready,
// Bidirectionals
// Outputs
background_ready,
foreground_ready,
output_data,
output_startofpacket,
output_endofpacket,
output_empty,
output_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [29: 0] background_data;
input background_startofpacket;
input background_endofpacket;
input [ 1: 0] background_empty;
input background_valid;
input [39: 0] foreground_data;
input foreground_startofpacket;
input foreground_endofpacket;
input [ 1: 0] foreground_empty;
input foreground_valid;
input output_ready;
// Bidirectionals
// Outputs
output background_ready;
output foreground_ready;
output [29: 0] output_data;
output output_startofpacket;
output output_endofpacket;
output [ 1: 0] output_empty;
output output_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] new_red;
wire [ 9: 0] new_green;
wire [ 9: 0] new_blue;
wire sync_foreground;
wire sync_background;
wire valid;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign background_ready = (output_ready & output_valid) | sync_background;
assign foreground_ready = (output_ready & output_valid) | sync_foreground;
assign output_data = {new_red, new_green, new_blue};
assign output_startofpacket = foreground_startofpacket;
assign output_endofpacket = foreground_endofpacket;
assign output_empty = 2'h0;
assign output_valid = valid;
// Internal Assignments
assign sync_foreground = (foreground_valid & background_valid &
((background_startofpacket & ~foreground_startofpacket) |
(background_endofpacket & ~foreground_endofpacket)));
assign sync_background = (foreground_valid & background_valid &
((foreground_startofpacket & ~background_startofpacket) |
(foreground_endofpacket & ~background_endofpacket)));
assign valid = foreground_valid & background_valid &
~sync_foreground & ~sync_background;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_alpha_blender_simple alpha_blender (
// Inputs
.background_data (background_data),
.foreground_data (foreground_data),
// Bidirectionals
// Outputs
.new_red (new_red),
.new_green (new_green),
.new_blue (new_blue)
);
endmodule |
module altera_up_avalon_video_dma_ctrl_addr_trans (
// Inputs
clk,
reset,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
master_readdata,
master_waitrequest,
// Bi-Directional
// Outputs
slave_readdata,
slave_waitrequest,
master_address,
master_byteenable,
master_read,
master_write,
master_writedata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter ADDRESS_TRANSLATION_MASK = 32'hC0000000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
input [31: 0] master_readdata;
input master_waitrequest;
// Bi-Directional
// Outputs
output [31: 0] slave_readdata;
output slave_waitrequest;
output [ 1: 0] master_address;
output [ 3: 0] master_byteenable;
output master_read;
output master_write;
output [31: 0] master_writedata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign slave_readdata = (slave_address[1] == 1'b0) ?
master_readdata | ADDRESS_TRANSLATION_MASK :
master_readdata;
assign slave_waitrequest = master_waitrequest;
assign master_address = slave_address;
assign master_byteenable = slave_byteenable;
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = (slave_address[1] == 1'b0) ?
slave_writedata & ~ADDRESS_TRANSLATION_MASK :
slave_writedata;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_ASCII_to_Image (
// Global Signals
clk,
reset,
// ASCII Character Stream (input stream)
ascii_in_channel,
ascii_in_data,
ascii_in_startofpacket,
ascii_in_endofpacket,
ascii_in_valid,
ascii_in_ready,
// Image Stream (output stream)
image_out_ready,
image_out_data,
image_out_startofpacket,
image_out_endofpacket,
image_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 7;
parameter ODW = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Global Signals
input clk;
input reset;
// ASCII Character Stream (avalon stream - sink)
input [ 5: 0] ascii_in_channel;
input [IDW:0] ascii_in_data;
input ascii_in_startofpacket;
input ascii_in_endofpacket;
input ascii_in_valid;
output ascii_in_ready;
// Image Stream (avalon stream - source)
input image_out_ready;
output reg [ODW:0] image_out_data;
output reg image_out_startofpacket;
output reg image_out_endofpacket;
output reg image_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire rom_data;
// Internal Registers
reg internal_startofpacket;
reg internal_endofpacket;
reg internal_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
image_out_data <= 'h0;
image_out_startofpacket <= 1'b0;
image_out_endofpacket <= 1'b0;
image_out_valid <= 1'b0;
end
else if (image_out_ready | ~image_out_valid)
begin
image_out_data <= rom_data;
image_out_startofpacket <= internal_startofpacket;
image_out_endofpacket <= internal_endofpacket;
image_out_valid <= internal_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
internal_startofpacket <= 1'b0;
internal_endofpacket <= 1'b0;
internal_valid <= 1'b0;
end
else if (ascii_in_ready)
begin
internal_startofpacket <= ascii_in_startofpacket;
internal_endofpacket <= ascii_in_endofpacket;
internal_valid <= ascii_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ascii_in_ready = ~ascii_in_valid | image_out_ready | ~image_out_valid;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_ascii_rom_128 ASCII_Character_Rom (
// Global Signals
.clk (clk),
.clk_en (ascii_in_ready),
// Inputs
.character (ascii_in_data[ 6: 0]),
.x_coordinate (ascii_in_channel[ 2: 0]),
.y_coordinate (ascii_in_channel[ 5: 3]),
// Outputs
.character_data (rom_data)
);
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem (
input wire avalon_char_source_ready, // avalon_char_source.ready
output wire avalon_char_source_startofpacket, // .startofpacket
output wire avalon_char_source_endofpacket, // .endofpacket
output wire avalon_char_source_valid, // .valid
output wire [39:0] avalon_char_source_data, // .data
input wire [1:0] char_buffer_control_slave_address, // char_buffer_control_slave.address
input wire [3:0] char_buffer_control_slave_byteenable, // .byteenable
input wire char_buffer_control_slave_read, // .read
input wire char_buffer_control_slave_write, // .write
input wire [31:0] char_buffer_control_slave_writedata, // .writedata
output wire [31:0] char_buffer_control_slave_readdata, // .readdata
input wire [10:0] char_buffer_slave_address, // char_buffer_slave.address
input wire char_buffer_slave_clken, // .clken
input wire char_buffer_slave_chipselect, // .chipselect
input wire char_buffer_slave_write, // .write
output wire [31:0] char_buffer_slave_readdata, // .readdata
input wire [31:0] char_buffer_slave_writedata, // .writedata
input wire [3:0] char_buffer_slave_byteenable, // .byteenable
input wire sys_clk_clk, // sys_clk.clk
input wire sys_reset_reset_n // sys_reset.reset_n
);
wire ascii_to_image_avalon_image_source_valid; // ASCII_to_Image:image_out_valid -> Char_Buf_RGB_Resampler:stream_in_valid
wire ascii_to_image_avalon_image_source_data; // ASCII_to_Image:image_out_data -> Char_Buf_RGB_Resampler:stream_in_data
wire ascii_to_image_avalon_image_source_ready; // Char_Buf_RGB_Resampler:stream_in_ready -> ASCII_to_Image:image_out_ready
wire ascii_to_image_avalon_image_source_startofpacket; // ASCII_to_Image:image_out_startofpacket -> Char_Buf_RGB_Resampler:stream_in_startofpacket
wire ascii_to_image_avalon_image_source_endofpacket; // ASCII_to_Image:image_out_endofpacket -> Char_Buf_RGB_Resampler:stream_in_endofpacket
wire char_buf_dma_avalon_pixel_source_valid; // Char_Buf_DMA:stream_valid -> Char_Buf_Scaler:stream_in_valid
wire [7:0] char_buf_dma_avalon_pixel_source_data; // Char_Buf_DMA:stream_data -> Char_Buf_Scaler:stream_in_data
wire char_buf_dma_avalon_pixel_source_ready; // Char_Buf_Scaler:stream_in_ready -> Char_Buf_DMA:stream_ready
wire char_buf_dma_avalon_pixel_source_startofpacket; // Char_Buf_DMA:stream_startofpacket -> Char_Buf_Scaler:stream_in_startofpacket
wire char_buf_dma_avalon_pixel_source_endofpacket; // Char_Buf_DMA:stream_endofpacket -> Char_Buf_Scaler:stream_in_endofpacket
wire char_buf_rgb_resampler_avalon_rgb_source_valid; // Char_Buf_RGB_Resampler:stream_out_valid -> Set_Black_Transparent:stream_in_valid
wire [39:0] char_buf_rgb_resampler_avalon_rgb_source_data; // Char_Buf_RGB_Resampler:stream_out_data -> Set_Black_Transparent:stream_in_data
wire char_buf_rgb_resampler_avalon_rgb_source_ready; // Set_Black_Transparent:stream_in_ready -> Char_Buf_RGB_Resampler:stream_out_ready
wire char_buf_rgb_resampler_avalon_rgb_source_startofpacket; // Char_Buf_RGB_Resampler:stream_out_startofpacket -> Set_Black_Transparent:stream_in_startofpacket
wire char_buf_rgb_resampler_avalon_rgb_source_endofpacket; // Char_Buf_RGB_Resampler:stream_out_endofpacket -> Set_Black_Transparent:stream_in_endofpacket
wire char_buf_scaler_avalon_scaler_source_valid; // Char_Buf_Scaler:stream_out_valid -> ASCII_to_Image:ascii_in_valid
wire [7:0] char_buf_scaler_avalon_scaler_source_data; // Char_Buf_Scaler:stream_out_data -> ASCII_to_Image:ascii_in_data
wire char_buf_scaler_avalon_scaler_source_ready; // ASCII_to_Image:ascii_in_ready -> Char_Buf_Scaler:stream_out_ready
wire [5:0] char_buf_scaler_avalon_scaler_source_channel; // Char_Buf_Scaler:stream_out_channel -> ASCII_to_Image:ascii_in_channel
wire char_buf_scaler_avalon_scaler_source_startofpacket; // Char_Buf_Scaler:stream_out_startofpacket -> ASCII_to_Image:ascii_in_startofpacket
wire char_buf_scaler_avalon_scaler_source_endofpacket; // Char_Buf_Scaler:stream_out_endofpacket -> ASCII_to_Image:ascii_in_endofpacket
wire char_buf_dma_avalon_dma_master_waitrequest; // mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_waitrequest -> Char_Buf_DMA:master_waitrequest
wire [7:0] char_buf_dma_avalon_dma_master_readdata; // mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_readdata -> Char_Buf_DMA:master_readdata
wire [31:0] char_buf_dma_avalon_dma_master_address; // Char_Buf_DMA:master_address -> mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_address
wire char_buf_dma_avalon_dma_master_read; // Char_Buf_DMA:master_read -> mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_read
wire char_buf_dma_avalon_dma_master_readdatavalid; // mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_readdatavalid -> Char_Buf_DMA:master_readdatavalid
wire char_buf_dma_avalon_dma_master_lock; // Char_Buf_DMA:master_arbiterlock -> mm_interconnect_0:Char_Buf_DMA_avalon_dma_master_lock
wire mm_interconnect_0_onchip_sram_s2_chipselect; // mm_interconnect_0:Onchip_SRAM_s2_chipselect -> Onchip_SRAM:chipselect2
wire [31:0] mm_interconnect_0_onchip_sram_s2_readdata; // Onchip_SRAM:readdata2 -> mm_interconnect_0:Onchip_SRAM_s2_readdata
wire [10:0] mm_interconnect_0_onchip_sram_s2_address; // mm_interconnect_0:Onchip_SRAM_s2_address -> Onchip_SRAM:address2
wire [3:0] mm_interconnect_0_onchip_sram_s2_byteenable; // mm_interconnect_0:Onchip_SRAM_s2_byteenable -> Onchip_SRAM:byteenable2
wire mm_interconnect_0_onchip_sram_s2_write; // mm_interconnect_0:Onchip_SRAM_s2_write -> Onchip_SRAM:write2
wire [31:0] mm_interconnect_0_onchip_sram_s2_writedata; // mm_interconnect_0:Onchip_SRAM_s2_writedata -> Onchip_SRAM:writedata2
wire mm_interconnect_0_onchip_sram_s2_clken; // mm_interconnect_0:Onchip_SRAM_s2_clken -> Onchip_SRAM:clken2
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [ASCII_to_Image:reset, Char_Buf_DMA:reset, Char_Buf_RGB_Resampler:reset, Char_Buf_Scaler:reset, Onchip_SRAM:reset, Set_Black_Transparent:reset, mm_interconnect_0:Char_Buf_DMA_reset_reset_bridge_in_reset_reset, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [Onchip_SRAM:reset_req, rst_translator:reset_req_in]
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_ASCII_to_Image ascii_to_image (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.ascii_in_channel (char_buf_scaler_avalon_scaler_source_channel), // avalon_ascii_sink.channel
.ascii_in_startofpacket (char_buf_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.ascii_in_endofpacket (char_buf_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.ascii_in_valid (char_buf_scaler_avalon_scaler_source_valid), // .valid
.ascii_in_ready (char_buf_scaler_avalon_scaler_source_ready), // .ready
.ascii_in_data (char_buf_scaler_avalon_scaler_source_data), // .data
.image_out_ready (ascii_to_image_avalon_image_source_ready), // avalon_image_source.ready
.image_out_startofpacket (ascii_to_image_avalon_image_source_startofpacket), // .startofpacket
.image_out_endofpacket (ascii_to_image_avalon_image_source_endofpacket), // .endofpacket
.image_out_valid (ascii_to_image_avalon_image_source_valid), // .valid
.image_out_data (ascii_to_image_avalon_image_source_data) // .data
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Char_Buf_DMA char_buf_dma (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.master_address (char_buf_dma_avalon_dma_master_address), // avalon_dma_master.address
.master_waitrequest (char_buf_dma_avalon_dma_master_waitrequest), // .waitrequest
.master_arbiterlock (char_buf_dma_avalon_dma_master_lock), // .lock
.master_read (char_buf_dma_avalon_dma_master_read), // .read
.master_readdata (char_buf_dma_avalon_dma_master_readdata), // .readdata
.master_readdatavalid (char_buf_dma_avalon_dma_master_readdatavalid), // .readdatavalid
.slave_address (char_buffer_control_slave_address), // avalon_dma_control_slave.address
.slave_byteenable (char_buffer_control_slave_byteenable), // .byteenable
.slave_read (char_buffer_control_slave_read), // .read
.slave_write (char_buffer_control_slave_write), // .write
.slave_writedata (char_buffer_control_slave_writedata), // .writedata
.slave_readdata (char_buffer_control_slave_readdata), // .readdata
.stream_ready (char_buf_dma_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_data (char_buf_dma_avalon_pixel_source_data), // .data
.stream_startofpacket (char_buf_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (char_buf_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (char_buf_dma_avalon_pixel_source_valid) // .valid
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Char_Buf_RGB_Resampler char_buf_rgb_resampler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (ascii_to_image_avalon_image_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (ascii_to_image_avalon_image_source_endofpacket), // .endofpacket
.stream_in_valid (ascii_to_image_avalon_image_source_valid), // .valid
.stream_in_ready (ascii_to_image_avalon_image_source_ready), // .ready
.stream_in_data (ascii_to_image_avalon_image_source_data), // .data
.stream_out_ready (char_buf_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (char_buf_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (char_buf_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (char_buf_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (char_buf_rgb_resampler_avalon_rgb_source_data) // .data
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Char_Buf_Scaler char_buf_scaler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (char_buf_dma_avalon_pixel_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (char_buf_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (char_buf_dma_avalon_pixel_source_valid), // .valid
.stream_in_ready (char_buf_dma_avalon_pixel_source_ready), // .ready
.stream_in_data (char_buf_dma_avalon_pixel_source_data), // .data
.stream_out_ready (char_buf_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (char_buf_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (char_buf_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (char_buf_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (char_buf_scaler_avalon_scaler_source_data), // .data
.stream_out_channel (char_buf_scaler_avalon_scaler_source_channel) // .channel
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Onchip_SRAM onchip_sram (
.address (char_buffer_slave_address), // s1.address
.clken (char_buffer_slave_clken), // .clken
.chipselect (char_buffer_slave_chipselect), // .chipselect
.write (char_buffer_slave_write), // .write
.readdata (char_buffer_slave_readdata), // .readdata
.writedata (char_buffer_slave_writedata), // .writedata
.byteenable (char_buffer_slave_byteenable), // .byteenable
.address2 (mm_interconnect_0_onchip_sram_s2_address), // s2.address
.chipselect2 (mm_interconnect_0_onchip_sram_s2_chipselect), // .chipselect
.clken2 (mm_interconnect_0_onchip_sram_s2_clken), // .clken
.write2 (mm_interconnect_0_onchip_sram_s2_write), // .write
.readdata2 (mm_interconnect_0_onchip_sram_s2_readdata), // .readdata
.writedata2 (mm_interconnect_0_onchip_sram_s2_writedata), // .writedata
.byteenable2 (mm_interconnect_0_onchip_sram_s2_byteenable), // .byteenable
.clk (sys_clk_clk), // clk1.clk
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Set_Black_Transparent set_black_transparent (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (char_buf_rgb_resampler_avalon_rgb_source_startofpacket), // avalon_apply_alpha_sink.startofpacket
.stream_in_endofpacket (char_buf_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (char_buf_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (char_buf_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_in_data (char_buf_rgb_resampler_avalon_rgb_source_data), // .data
.stream_out_ready (avalon_char_source_ready), // avalon_apply_alpha_source.ready
.stream_out_startofpacket (avalon_char_source_startofpacket), // .startofpacket
.stream_out_endofpacket (avalon_char_source_endofpacket), // .endofpacket
.stream_out_valid (avalon_char_source_valid), // .valid
.stream_out_data (avalon_char_source_data) // .data
);
Computer_System_VGA_Subsystem_Char_Buf_Subsystem_mm_interconnect_0 mm_interconnect_0 (
.Sys_Clk_clk_clk (sys_clk_clk), // Sys_Clk_clk.clk
.Char_Buf_DMA_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // Char_Buf_DMA_reset_reset_bridge_in_reset.reset
.Char_Buf_DMA_avalon_dma_master_address (char_buf_dma_avalon_dma_master_address), // Char_Buf_DMA_avalon_dma_master.address
.Char_Buf_DMA_avalon_dma_master_waitrequest (char_buf_dma_avalon_dma_master_waitrequest), // .waitrequest
.Char_Buf_DMA_avalon_dma_master_read (char_buf_dma_avalon_dma_master_read), // .read
.Char_Buf_DMA_avalon_dma_master_readdata (char_buf_dma_avalon_dma_master_readdata), // .readdata
.Char_Buf_DMA_avalon_dma_master_readdatavalid (char_buf_dma_avalon_dma_master_readdatavalid), // .readdatavalid
.Char_Buf_DMA_avalon_dma_master_lock (char_buf_dma_avalon_dma_master_lock), // .lock
.Onchip_SRAM_s2_address (mm_interconnect_0_onchip_sram_s2_address), // Onchip_SRAM_s2.address
.Onchip_SRAM_s2_write (mm_interconnect_0_onchip_sram_s2_write), // .write
.Onchip_SRAM_s2_readdata (mm_interconnect_0_onchip_sram_s2_readdata), // .readdata
.Onchip_SRAM_s2_writedata (mm_interconnect_0_onchip_sram_s2_writedata), // .writedata
.Onchip_SRAM_s2_byteenable (mm_interconnect_0_onchip_sram_s2_byteenable), // .byteenable
.Onchip_SRAM_s2_chipselect (mm_interconnect_0_onchip_sram_s2_chipselect), // .chipselect
.Onchip_SRAM_s2_clken (mm_interconnect_0_onchip_sram_s2_clken) // .clken
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~sys_reset_reset_n), // reset_in0.reset
.clk (sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module altera_up_avalon_reset_from_locked_signal (
// Inputs
locked,
// Bidirectional
// Outputs
reset
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input locked;
// Bidirectionals
// Outputs
output reset;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset = ~locked;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module altera_up_video_scaler_multiply_height (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's data width
parameter WW = 8; // Image width's address width
parameter WIDTH = 320; // Image's width in pixels
parameter MCW = 0; // Multiply height's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [MCW:0] stream_out_channel;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam STATE_0_GET_CURRENT_LINE = 2'h0,
STATE_1_LOOP_FIFO = 2'h1,
STATE_2_OUTPUT_LAST_LINE = 2'h2;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW + 2): 0] fifo_data_in;
wire [(DW + 2): 0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_read;
wire fifo_write;
// Internal Registers
reg [WW: 0] width_in;
reg [WW: 0] width_out;
reg [MCW:0] enlarge_height_counter;
// State Machine Registers
reg [ 1: 0] s_multiply_height;
reg [ 1: 0] ns_multiply_height;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_multiply_height <= STATE_0_GET_CURRENT_LINE;
else
s_multiply_height <= ns_multiply_height;
end
always @(*)
begin
case (s_multiply_height)
STATE_0_GET_CURRENT_LINE:
begin
if (width_in == WIDTH)
ns_multiply_height = STATE_1_LOOP_FIFO;
else
ns_multiply_height = STATE_0_GET_CURRENT_LINE;
end
STATE_1_LOOP_FIFO:
begin
if (fifo_read & (width_out == (WIDTH - 1)) &
(&(enlarge_height_counter | 1'b1)))
ns_multiply_height = STATE_2_OUTPUT_LAST_LINE;
else
ns_multiply_height = STATE_1_LOOP_FIFO;
end
STATE_2_OUTPUT_LAST_LINE:
begin
if (fifo_read & (width_out == (WIDTH - 1)))
ns_multiply_height = STATE_0_GET_CURRENT_LINE;
else
ns_multiply_height = STATE_2_OUTPUT_LAST_LINE;
end
default:
begin
ns_multiply_height = STATE_0_GET_CURRENT_LINE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_channel <= enlarge_height_counter;
stream_out_data <= fifo_data_out[DW : 0];
if (|(enlarge_height_counter))
stream_out_startofpacket <= 1'b0;
else
stream_out_startofpacket <= fifo_data_out[DW + 1];
if (&(enlarge_height_counter))
stream_out_endofpacket <= fifo_data_out[DW + 2];
else
stream_out_endofpacket <= 1'b0;
if (s_multiply_height == STATE_0_GET_CURRENT_LINE)
stream_out_valid <= 1'b0;
else
stream_out_valid <= ~fifo_empty;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
width_in <= 'h0;
else if (s_multiply_height == STATE_1_LOOP_FIFO)
width_in <= 'h0;
else if (stream_in_ready & stream_in_valid)
width_in <= width_in + 1;
end
always @(posedge clk)
begin
if (reset)
width_out <= 'h0;
else if (fifo_read)
begin
if (width_out == (WIDTH - 1))
width_out <= 'h0;
else
width_out <= width_out + 1;
end
end
always @(posedge clk)
begin
if (reset)
enlarge_height_counter <= 'h0;
else if (s_multiply_height == STATE_0_GET_CURRENT_LINE)
enlarge_height_counter <= 'h0;
else if (fifo_read & (width_out == (WIDTH - 1)))
enlarge_height_counter <= enlarge_height_counter + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready =
(s_multiply_height == STATE_1_LOOP_FIFO) ?
1'b0 :
~fifo_full & ~(width_in == WIDTH);
// Internal assignments
assign fifo_data_in[DW : 0] =
(s_multiply_height == STATE_1_LOOP_FIFO) ?
fifo_data_out[DW : 0] :
stream_in_data;
assign fifo_data_in[DW + 1] =
(s_multiply_height == STATE_1_LOOP_FIFO) ?
fifo_data_out[DW + 1] :
stream_in_startofpacket;
assign fifo_data_in[DW + 2] =
(s_multiply_height == STATE_1_LOOP_FIFO) ?
fifo_data_out[DW + 2] :
stream_in_endofpacket;
assign fifo_write =
(s_multiply_height == STATE_1_LOOP_FIFO) ?
fifo_read :
stream_in_ready & stream_in_valid & ~fifo_full;
assign fifo_read =
(s_multiply_height == STATE_0_GET_CURRENT_LINE) ?
1'b0 :
(stream_out_ready | ~stream_out_valid) & ~fifo_empty;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Multiply_Height_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ()
// synopsys translate_on
);
defparam
Multiply_Height_FIFO.add_ram_output_register = "OFF",
Multiply_Height_FIFO.intended_device_family = "Cyclone II",
Multiply_Height_FIFO.lpm_numwords = WIDTH + 1,
Multiply_Height_FIFO.lpm_showahead = "ON",
Multiply_Height_FIFO.lpm_type = "scfifo",
Multiply_Height_FIFO.lpm_width = DW + 3,
Multiply_Height_FIFO.lpm_widthu = WW + 1,
Multiply_Height_FIFO.overflow_checking = "OFF",
Multiply_Height_FIFO.underflow_checking = "OFF",
Multiply_Height_FIFO.use_eab = "ON";
endmodule |
module Computer_System_Video_In_Subsystem_Video_In_Clipper (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's data width
parameter EW = 0; // Frame's empty width
parameter WIDTH_IN = 720; // Incoming frame's width in pixels
parameter HEIGHT_IN = 244; // Incoming frame's height in lines
parameter WW_IN = 9; // Incoming frame's width's address width
parameter HW_IN = 7; // Incoming frame's height's address width
parameter DROP_PIXELS_AT_START = 40;
parameter DROP_PIXELS_AT_END = 40;
parameter DROP_LINES_AT_START = 2;
parameter DROP_LINES_AT_END = 2;
parameter WIDTH_OUT = 640; // Final frame's width in pixels
parameter HEIGHT_OUT = 240; // Final frame's height in lines
parameter WW_OUT = 9; // Final frame's width's address width
parameter HW_OUT = 7; // Final frame's height's address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 16'd0; // Data value for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire [EW: 0] internal_empty;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_drop Clipper_Drop (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_empty (stream_in_empty),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_empty (internal_empty),
.stream_out_valid (internal_valid)
);
defparam
Clipper_Drop.DW = DW,
Clipper_Drop.EW = EW,
Clipper_Drop.IMAGE_WIDTH = WIDTH_IN,
Clipper_Drop.IMAGE_HEIGHT = HEIGHT_IN,
Clipper_Drop.WW = WW_IN,
Clipper_Drop.HW = HW_IN,
Clipper_Drop.DROP_PIXELS_AT_START = DROP_PIXELS_AT_START,
Clipper_Drop.DROP_PIXELS_AT_END = DROP_PIXELS_AT_END,
Clipper_Drop.DROP_LINES_AT_START = DROP_LINES_AT_START,
Clipper_Drop.DROP_LINES_AT_END = DROP_LINES_AT_END,
Clipper_Drop.ADD_DATA = ADD_DATA;
altera_up_video_clipper_add Clipper_Add (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_empty (internal_empty),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (internal_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_empty (stream_out_empty),
.stream_out_valid (stream_out_valid)
);
defparam
Clipper_Add.DW = DW,
Clipper_Add.EW = EW,
Clipper_Add.IMAGE_WIDTH = WIDTH_OUT,
Clipper_Add.IMAGE_HEIGHT = HEIGHT_OUT,
Clipper_Add.WW = WW_OUT,
Clipper_Add.HW = HW_OUT,
Clipper_Add.ADD_PIXELS_AT_START = ADD_PIXELS_AT_START,
Clipper_Add.ADD_PIXELS_AT_END = ADD_PIXELS_AT_END,
Clipper_Add.ADD_LINES_AT_START = ADD_LINES_AT_START,
Clipper_Add.ADD_LINES_AT_END = ADD_LINES_AT_END,
Clipper_Add.ADD_DATA = ADD_DATA;
endmodule |
module Computer_System_Expansion_JP1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
irq,
readdata
)
;
inout [ 31: 0] bidir_port;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 31: 0] bidir_port;
wire clk_en;
reg [ 31: 0] d1_data_in;
reg [ 31: 0] d2_data_in;
reg [ 31: 0] data_dir;
wire [ 31: 0] data_in;
reg [ 31: 0] data_out;
reg [ 31: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 31: 0] edge_detect;
wire irq;
reg [ 31: 0] irq_mask;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({32 {(address == 0)}} & data_in) |
({32 {(address == 1)}} & data_dir) |
({32 {(address == 2)}} & irq_mask) |
({32 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[31 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign bidir_port[5] = data_dir[5] ? data_out[5] : 1'bZ;
assign bidir_port[6] = data_dir[6] ? data_out[6] : 1'bZ;
assign bidir_port[7] = data_dir[7] ? data_out[7] : 1'bZ;
assign bidir_port[8] = data_dir[8] ? data_out[8] : 1'bZ;
assign bidir_port[9] = data_dir[9] ? data_out[9] : 1'bZ;
assign bidir_port[10] = data_dir[10] ? data_out[10] : 1'bZ;
assign bidir_port[11] = data_dir[11] ? data_out[11] : 1'bZ;
assign bidir_port[12] = data_dir[12] ? data_out[12] : 1'bZ;
assign bidir_port[13] = data_dir[13] ? data_out[13] : 1'bZ;
assign bidir_port[14] = data_dir[14] ? data_out[14] : 1'bZ;
assign bidir_port[15] = data_dir[15] ? data_out[15] : 1'bZ;
assign bidir_port[16] = data_dir[16] ? data_out[16] : 1'bZ;
assign bidir_port[17] = data_dir[17] ? data_out[17] : 1'bZ;
assign bidir_port[18] = data_dir[18] ? data_out[18] : 1'bZ;
assign bidir_port[19] = data_dir[19] ? data_out[19] : 1'bZ;
assign bidir_port[20] = data_dir[20] ? data_out[20] : 1'bZ;
assign bidir_port[21] = data_dir[21] ? data_out[21] : 1'bZ;
assign bidir_port[22] = data_dir[22] ? data_out[22] : 1'bZ;
assign bidir_port[23] = data_dir[23] ? data_out[23] : 1'bZ;
assign bidir_port[24] = data_dir[24] ? data_out[24] : 1'bZ;
assign bidir_port[25] = data_dir[25] ? data_out[25] : 1'bZ;
assign bidir_port[26] = data_dir[26] ? data_out[26] : 1'bZ;
assign bidir_port[27] = data_dir[27] ? data_out[27] : 1'bZ;
assign bidir_port[28] = data_dir[28] ? data_out[28] : 1'bZ;
assign bidir_port[29] = data_dir[29] ? data_out[29] : 1'bZ;
assign bidir_port[30] = data_dir[30] ? data_out[30] : 1'bZ;
assign bidir_port[31] = data_dir[31] ? data_out[31] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[31 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[4])
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[5])
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[6])
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[7])
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[8])
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[9])
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[10] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[10])
edge_capture[10] <= 0;
else if (edge_detect[10])
edge_capture[10] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[11] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[11])
edge_capture[11] <= 0;
else if (edge_detect[11])
edge_capture[11] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[12] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[12])
edge_capture[12] <= 0;
else if (edge_detect[12])
edge_capture[12] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[13] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[13])
edge_capture[13] <= 0;
else if (edge_detect[13])
edge_capture[13] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[14] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[14])
edge_capture[14] <= 0;
else if (edge_detect[14])
edge_capture[14] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[15] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[15])
edge_capture[15] <= 0;
else if (edge_detect[15])
edge_capture[15] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[16] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[16])
edge_capture[16] <= 0;
else if (edge_detect[16])
edge_capture[16] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[17] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[17])
edge_capture[17] <= 0;
else if (edge_detect[17])
edge_capture[17] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[18] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[18])
edge_capture[18] <= 0;
else if (edge_detect[18])
edge_capture[18] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[19] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[19])
edge_capture[19] <= 0;
else if (edge_detect[19])
edge_capture[19] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[20] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[20])
edge_capture[20] <= 0;
else if (edge_detect[20])
edge_capture[20] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[21] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[21])
edge_capture[21] <= 0;
else if (edge_detect[21])
edge_capture[21] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[22] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[22])
edge_capture[22] <= 0;
else if (edge_detect[22])
edge_capture[22] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[23] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[23])
edge_capture[23] <= 0;
else if (edge_detect[23])
edge_capture[23] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[24] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[24])
edge_capture[24] <= 0;
else if (edge_detect[24])
edge_capture[24] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[25] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[25])
edge_capture[25] <= 0;
else if (edge_detect[25])
edge_capture[25] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[26] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[26])
edge_capture[26] <= 0;
else if (edge_detect[26])
edge_capture[26] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[27] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[27])
edge_capture[27] <= 0;
else if (edge_detect[27])
edge_capture[27] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[28] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[28])
edge_capture[28] <= 0;
else if (edge_detect[28])
edge_capture[28] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[29] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[29])
edge_capture[29] <= 0;
else if (edge_detect[29])
edge_capture[29] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[30] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[30])
edge_capture[30] <= 0;
else if (edge_detect[30])
edge_capture[30] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[31] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[31])
edge_capture[31] <= 0;
else if (edge_detect[31])
edge_capture[31] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule |
module altera_up_video_scaler_multiply_width (
// Inputs
clk,
reset,
stream_in_channel,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 15; // Image's Channel Width
parameter DW = 15; // Image's data width
parameter MCW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] stream_in_channel;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [CW: 0] stream_out_channel;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [CW: 0] channel;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [MCW:0] enlarge_width_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_channel <= 'h0;
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_channel <= {channel, enlarge_width_counter};
stream_out_data <= data;
if (|(enlarge_width_counter))
stream_out_startofpacket <= 1'b0;
else
stream_out_startofpacket <= startofpacket;
if (&(enlarge_width_counter))
stream_out_endofpacket <= endofpacket;
else
stream_out_endofpacket <= 1'b0;
stream_out_valid <= valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
channel <= 'h0;
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
channel <= stream_in_channel;
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
end
always @(posedge clk)
begin
if (reset)
enlarge_width_counter <= 'h0;
else if ((stream_out_ready | ~stream_out_valid) & valid)
enlarge_width_counter <= enlarge_width_counter + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = (~valid) |
((&(enlarge_width_counter)) & (stream_out_ready | ~stream_out_valid));
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_Slider_Switches (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 9: 0] in_port;
input reset_n;
wire clk_en;
wire [ 9: 0] data_in;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule |
module altera_up_video_dma_to_stream (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
reading_first_pixel_in_frame,
reading_last_pixel_in_frame,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_arbiterlock,
master_read,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input reading_first_pixel_in_frame;
input reading_last_pixel_in_frame;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output master_arbiterlock;
output master_read;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [ 3: 0] pending_reads;
reg startofpacket;
// State Machine Registers
reg [ 1: 0] s_dma_to_stream;
reg [ 1: 0] ns_dma_to_stream;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
s_dma_to_stream <= STATE_0_IDLE;
else
s_dma_to_stream <= ns_dma_to_stream;
end
always @(*)
begin
case (s_dma_to_stream)
STATE_0_IDLE:
begin
if (reset)
ns_dma_to_stream = STATE_0_IDLE;
else if (fifo_almost_empty)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else
ns_dma_to_stream = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if (reading_last_pixel_in_frame)
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_dma_to_stream = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
startofpacket <= 1'b0;
else if ((s_dma_to_stream == STATE_0_IDLE) & (reading_first_pixel_in_frame))
startofpacket <= 1'b1;
else if (master_readdatavalid)
startofpacket <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
assign master_arbiterlock = !((s_dma_to_stream == STATE_2_READ_BUFFER) |
(s_dma_to_stream == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_dma_to_stream == STATE_2_READ_BUFFER);
assign inc_address = master_read & ~master_waitrequest;
assign reset_address = inc_address & reading_last_pixel_in_frame;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = startofpacket;
assign fifo_data_in[DW+2] = (s_dma_to_stream == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full),
// synopsys translate_off
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule |
module altera_up_edge_detection_data_shift_register (
clken,
clock,
shiftin,
shiftout,
taps);
parameter DW = 10;
parameter SIZE = 720;
input clken;
input clock;
input [DW:1] shiftin;
output [DW:1] shiftout;
output [DW:1] taps;
wire [DW:1] sub_wire0;
wire [DW:1] sub_wire1;
wire [DW:1] taps = sub_wire0[DW:1];
wire [DW:1] shiftout = sub_wire1[DW:1];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire1));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 1,
altshift_taps_component.tap_distance = SIZE,
altshift_taps_component.width = DW;
endmodule |
module Computer_System_SysID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1494562059 : 0;
endmodule |
module altera_up_video_alpha_blender_normal (
// Inputs
background_data,
foreground_data,
// Bidirectionals
// Outputs
new_red,
new_green,
new_blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [29: 0] background_data;
input [39: 0] foreground_data;
// Bidirectionals
// Outputs
output [ 9: 0] new_red;
output [ 9: 0] new_green;
output [ 9: 0] new_blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] one_minus_a;
wire [17: 0] r_x_alpha;
wire [17: 0] g_x_alpha;
wire [17: 0] b_x_alpha;
wire [17: 0] r_x_one_minus_alpha;
wire [17: 0] g_x_one_minus_alpha;
wire [17: 0] b_x_one_minus_alpha;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign new_red = {1'b0, r_x_alpha[17:9]} +
{1'b0, r_x_one_minus_alpha[17:9]};
assign new_green = {1'b0, g_x_alpha[17:9]} +
{1'b0, g_x_one_minus_alpha[17:9]};
assign new_blue = {1'b0, b_x_alpha[17:9]} +
{1'b0, b_x_one_minus_alpha[17:9]};
// Internal Assignments
assign one_minus_a = 10'h3FF - foreground_data[39:30];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
lpm_mult r_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[29:21]),
.datab (foreground_data[39:31]),
// Outputs
.result (r_x_alpha)
);
defparam
r_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_alpha.lpm_representation = "UNSIGNED",
r_times_alpha.lpm_type = "LPM_MULT",
r_times_alpha.lpm_widtha = 9,
r_times_alpha.lpm_widthb = 9,
r_times_alpha.lpm_widthp = 18;
lpm_mult g_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[19:11]),
.datab (foreground_data[39:31]),
// Outputs
.result (g_x_alpha)
);
defparam
g_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_alpha.lpm_representation = "UNSIGNED",
g_times_alpha.lpm_type = "LPM_MULT",
g_times_alpha.lpm_widtha = 9,
g_times_alpha.lpm_widthb = 9,
g_times_alpha.lpm_widthp = 18;
lpm_mult b_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[ 9: 1]),
.datab (foreground_data[39:31]),
// Outputs
.result (b_x_alpha)
);
defparam
b_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_alpha.lpm_representation = "UNSIGNED",
b_times_alpha.lpm_type = "LPM_MULT",
b_times_alpha.lpm_widtha = 9,
b_times_alpha.lpm_widthb = 9,
b_times_alpha.lpm_widthp = 18;
lpm_mult r_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[29:21]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (r_x_one_minus_alpha)
);
defparam
r_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_one_minus_alpha.lpm_representation = "UNSIGNED",
r_times_one_minus_alpha.lpm_type = "LPM_MULT",
r_times_one_minus_alpha.lpm_widtha = 9,
r_times_one_minus_alpha.lpm_widthb = 9,
r_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult g_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[19:11]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (g_x_one_minus_alpha)
);
defparam
g_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_one_minus_alpha.lpm_representation = "UNSIGNED",
g_times_one_minus_alpha.lpm_type = "LPM_MULT",
g_times_one_minus_alpha.lpm_widtha = 9,
g_times_one_minus_alpha.lpm_widthb = 9,
g_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult b_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[ 9: 1]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (b_x_one_minus_alpha)
);
defparam
b_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_one_minus_alpha.lpm_representation = "UNSIGNED",
b_times_one_minus_alpha.lpm_type = "LPM_MULT",
b_times_one_minus_alpha.lpm_widtha = 9,
b_times_one_minus_alpha.lpm_widthb = 9,
b_times_one_minus_alpha.lpm_widthp = 18;
endmodule |
module altera_up_video_clipper_counters (
// Inputs
clk,
reset,
increment_counters,
// Bi-Directional
// Outputs
start_of_outer_frame,
end_of_outer_frame,
start_of_inner_frame,
end_of_inner_frame,
inner_frame_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IMAGE_WIDTH = 640; // Final image width in pixels
parameter IMAGE_HEIGHT = 480; // Final image height in lines
parameter WW = 9; // Final image width address width
parameter HW = 8; // Final image height address width
parameter LEFT_OFFSET = 0;
parameter RIGHT_OFFSET = 0;
parameter TOP_OFFSET = 0;
parameter BOTTOM_OFFSET = 0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input increment_counters;
// Bi-Directional
// Outputs
output start_of_outer_frame;
output end_of_outer_frame;
output start_of_inner_frame;
output end_of_inner_frame;
output inner_frame_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [WW: 0] width;
reg [HW: 0] height;
reg inner_width_valid;
reg inner_height_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output registers
// Internal registers
always @(posedge clk)
begin
if (reset)
width <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
width <= 'h0;
else if (increment_counters)
width <= width + 1;
end
always @(posedge clk)
begin
if (reset)
height <= 'h0;
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
height <= 'h0;
else
height <= height + 1;
end
end
always @(posedge clk)
begin
if (reset)
inner_width_valid <= (LEFT_OFFSET == 0);
else if (increment_counters)
begin
if (width == (IMAGE_WIDTH - 1))
inner_width_valid <= (LEFT_OFFSET == 0);
else if (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1))
inner_width_valid <= 1'b0;
else if (width == (LEFT_OFFSET - 1))
inner_width_valid <= 1'b1;
end
end
always @(posedge clk)
begin
if (reset)
inner_height_valid <= (TOP_OFFSET == 0);
else if (increment_counters & (width == (IMAGE_WIDTH - 1)))
begin
if (height == (IMAGE_HEIGHT - 1))
inner_height_valid <= (TOP_OFFSET == 0);
else if (height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1))
inner_height_valid <= 1'b0;
else if (height == (TOP_OFFSET - 1))
inner_height_valid <= 1'b1;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign start_of_outer_frame = (width == 'h0) & (height == 'h0);
assign end_of_outer_frame = (width == (IMAGE_WIDTH - 1)) &
(height == (IMAGE_HEIGHT - 1));
assign start_of_inner_frame = (width == LEFT_OFFSET) &
(height == TOP_OFFSET);
assign end_of_inner_frame = (width == (IMAGE_WIDTH - RIGHT_OFFSET - 1)) &
(height == (IMAGE_HEIGHT - BOTTOM_OFFSET - 1));
assign inner_frame_valid = inner_width_valid & inner_height_valid;
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_VGA_Pixel_Scaler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 29; // Frame's Data Width
parameter EW = 1; // Frame's Empty Width
parameter WIW = 8; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 320;
parameter WIDTH_DROP_MASK = 4'b0000;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 8; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 320; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_multiply_height Multiply_Height (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
// Bi-Directional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_channel (internal_channel),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_valid (internal_valid)
);
defparam
Multiply_Height.DW = DW,
Multiply_Height.WW = MH_WW,
Multiply_Height.WIDTH = MH_WIDTH_IN,
Multiply_Height.MCW = MH_CW;
altera_up_video_scaler_multiply_width Multiply_Width (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_channel (internal_channel),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
// Bi-Directional
// Outputs
.stream_in_ready (internal_ready),
.stream_out_channel (stream_out_channel),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Multiply_Width.CW = CW,
Multiply_Width.DW = DW,
Multiply_Width.MCW = MW_CW;
endmodule |
module Computer_System_VGA_Subsystem (
input wire [1:0] char_buffer_control_slave_address, // char_buffer_control_slave.address
input wire [3:0] char_buffer_control_slave_byteenable, // .byteenable
input wire char_buffer_control_slave_read, // .read
input wire char_buffer_control_slave_write, // .write
input wire [31:0] char_buffer_control_slave_writedata, // .writedata
output wire [31:0] char_buffer_control_slave_readdata, // .readdata
input wire [10:0] char_buffer_slave_address, // char_buffer_slave.address
input wire char_buffer_slave_clken, // .clken
input wire char_buffer_slave_chipselect, // .chipselect
input wire char_buffer_slave_write, // .write
output wire [31:0] char_buffer_slave_readdata, // .readdata
input wire [31:0] char_buffer_slave_writedata, // .writedata
input wire [3:0] char_buffer_slave_byteenable, // .byteenable
input wire [1:0] pixel_dma_control_slave_address, // pixel_dma_control_slave.address
input wire [3:0] pixel_dma_control_slave_byteenable, // .byteenable
input wire pixel_dma_control_slave_read, // .read
input wire pixel_dma_control_slave_write, // .write
input wire [31:0] pixel_dma_control_slave_writedata, // .writedata
output wire [31:0] pixel_dma_control_slave_readdata, // .readdata
input wire pixel_dma_master_readdatavalid, // pixel_dma_master.readdatavalid
input wire pixel_dma_master_waitrequest, // .waitrequest
output wire [31:0] pixel_dma_master_address, // .address
output wire pixel_dma_master_lock, // .lock
output wire pixel_dma_master_read, // .read
input wire [15:0] pixel_dma_master_readdata, // .readdata
input wire sys_clk_clk, // sys_clk.clk
input wire sys_reset_reset_n, // sys_reset.reset_n
output wire vga_CLK, // vga.CLK
output wire vga_HS, // .HS
output wire vga_VS, // .VS
output wire vga_BLANK, // .BLANK
output wire vga_SYNC, // .SYNC
output wire [7:0] vga_R, // .R
output wire [7:0] vga_G, // .G
output wire [7:0] vga_B, // .B
input wire vga_pll_ref_clk_clk, // vga_pll_ref_clk.clk
input wire vga_pll_ref_reset_reset // vga_pll_ref_reset.reset
);
wire vga_alpha_blender_avalon_blended_source_valid; // VGA_Alpha_Blender:output_valid -> VGA_Dual_Clock_FIFO:stream_in_valid
wire [29:0] vga_alpha_blender_avalon_blended_source_data; // VGA_Alpha_Blender:output_data -> VGA_Dual_Clock_FIFO:stream_in_data
wire vga_alpha_blender_avalon_blended_source_ready; // VGA_Dual_Clock_FIFO:stream_in_ready -> VGA_Alpha_Blender:output_ready
wire vga_alpha_blender_avalon_blended_source_startofpacket; // VGA_Alpha_Blender:output_startofpacket -> VGA_Dual_Clock_FIFO:stream_in_startofpacket
wire vga_alpha_blender_avalon_blended_source_endofpacket; // VGA_Alpha_Blender:output_endofpacket -> VGA_Dual_Clock_FIFO:stream_in_endofpacket
wire char_buf_subsystem_avalon_char_source_valid; // Char_Buf_Subsystem:avalon_char_source_valid -> VGA_Alpha_Blender:foreground_valid
wire [39:0] char_buf_subsystem_avalon_char_source_data; // Char_Buf_Subsystem:avalon_char_source_data -> VGA_Alpha_Blender:foreground_data
wire char_buf_subsystem_avalon_char_source_ready; // VGA_Alpha_Blender:foreground_ready -> Char_Buf_Subsystem:avalon_char_source_ready
wire char_buf_subsystem_avalon_char_source_startofpacket; // Char_Buf_Subsystem:avalon_char_source_startofpacket -> VGA_Alpha_Blender:foreground_startofpacket
wire char_buf_subsystem_avalon_char_source_endofpacket; // Char_Buf_Subsystem:avalon_char_source_endofpacket -> VGA_Alpha_Blender:foreground_endofpacket
wire vga_pixel_fifo_avalon_dc_buffer_source_valid; // VGA_Pixel_FIFO:stream_out_valid -> VGA_Pixel_RGB_Resampler:stream_in_valid
wire [15:0] vga_pixel_fifo_avalon_dc_buffer_source_data; // VGA_Pixel_FIFO:stream_out_data -> VGA_Pixel_RGB_Resampler:stream_in_data
wire vga_pixel_fifo_avalon_dc_buffer_source_ready; // VGA_Pixel_RGB_Resampler:stream_in_ready -> VGA_Pixel_FIFO:stream_out_ready
wire vga_pixel_fifo_avalon_dc_buffer_source_startofpacket; // VGA_Pixel_FIFO:stream_out_startofpacket -> VGA_Pixel_RGB_Resampler:stream_in_startofpacket
wire vga_pixel_fifo_avalon_dc_buffer_source_endofpacket; // VGA_Pixel_FIFO:stream_out_endofpacket -> VGA_Pixel_RGB_Resampler:stream_in_endofpacket
wire vga_dual_clock_fifo_avalon_dc_buffer_source_valid; // VGA_Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
wire [29:0] vga_dual_clock_fifo_avalon_dc_buffer_source_data; // VGA_Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
wire vga_dual_clock_fifo_avalon_dc_buffer_source_ready; // VGA_Controller:ready -> VGA_Dual_Clock_FIFO:stream_out_ready
wire vga_dual_clock_fifo_avalon_dc_buffer_source_startofpacket; // VGA_Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
wire vga_dual_clock_fifo_avalon_dc_buffer_source_endofpacket; // VGA_Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
wire vga_pixel_dma_avalon_pixel_source_valid; // VGA_Pixel_DMA:stream_valid -> VGA_Pixel_FIFO:stream_in_valid
wire [15:0] vga_pixel_dma_avalon_pixel_source_data; // VGA_Pixel_DMA:stream_data -> VGA_Pixel_FIFO:stream_in_data
wire vga_pixel_dma_avalon_pixel_source_ready; // VGA_Pixel_FIFO:stream_in_ready -> VGA_Pixel_DMA:stream_ready
wire vga_pixel_dma_avalon_pixel_source_startofpacket; // VGA_Pixel_DMA:stream_startofpacket -> VGA_Pixel_FIFO:stream_in_startofpacket
wire vga_pixel_dma_avalon_pixel_source_endofpacket; // VGA_Pixel_DMA:stream_endofpacket -> VGA_Pixel_FIFO:stream_in_endofpacket
wire vga_pixel_rgb_resampler_avalon_rgb_source_valid; // VGA_Pixel_RGB_Resampler:stream_out_valid -> VGA_Pixel_Scaler:stream_in_valid
wire [29:0] vga_pixel_rgb_resampler_avalon_rgb_source_data; // VGA_Pixel_RGB_Resampler:stream_out_data -> VGA_Pixel_Scaler:stream_in_data
wire vga_pixel_rgb_resampler_avalon_rgb_source_ready; // VGA_Pixel_Scaler:stream_in_ready -> VGA_Pixel_RGB_Resampler:stream_out_ready
wire vga_pixel_rgb_resampler_avalon_rgb_source_startofpacket; // VGA_Pixel_RGB_Resampler:stream_out_startofpacket -> VGA_Pixel_Scaler:stream_in_startofpacket
wire vga_pixel_rgb_resampler_avalon_rgb_source_endofpacket; // VGA_Pixel_RGB_Resampler:stream_out_endofpacket -> VGA_Pixel_Scaler:stream_in_endofpacket
wire vga_pll_vga_clk_clk; // VGA_PLL:vga_clk_clk -> [VGA_Controller:clk, VGA_Dual_Clock_FIFO:clk_stream_out, rst_controller_001:clk]
wire vga_pixel_scaler_avalon_scaler_source_valid; // VGA_Pixel_Scaler:stream_out_valid -> avalon_st_adapter:in_0_valid
wire [29:0] vga_pixel_scaler_avalon_scaler_source_data; // VGA_Pixel_Scaler:stream_out_data -> avalon_st_adapter:in_0_data
wire vga_pixel_scaler_avalon_scaler_source_ready; // avalon_st_adapter:in_0_ready -> VGA_Pixel_Scaler:stream_out_ready
wire [1:0] vga_pixel_scaler_avalon_scaler_source_channel; // VGA_Pixel_Scaler:stream_out_channel -> avalon_st_adapter:in_0_channel
wire vga_pixel_scaler_avalon_scaler_source_startofpacket; // VGA_Pixel_Scaler:stream_out_startofpacket -> avalon_st_adapter:in_0_startofpacket
wire vga_pixel_scaler_avalon_scaler_source_endofpacket; // VGA_Pixel_Scaler:stream_out_endofpacket -> avalon_st_adapter:in_0_endofpacket
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> VGA_Alpha_Blender:background_valid
wire [29:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> VGA_Alpha_Blender:background_data
wire avalon_st_adapter_out_0_ready; // VGA_Alpha_Blender:background_ready -> avalon_st_adapter:out_0_ready
wire avalon_st_adapter_out_0_startofpacket; // avalon_st_adapter:out_0_startofpacket -> VGA_Alpha_Blender:background_startofpacket
wire avalon_st_adapter_out_0_endofpacket; // avalon_st_adapter:out_0_endofpacket -> VGA_Alpha_Blender:background_endofpacket
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [VGA_Alpha_Blender:reset, VGA_Dual_Clock_FIFO:reset_stream_in, VGA_Pixel_DMA:reset, VGA_Pixel_FIFO:reset_stream_in, VGA_Pixel_FIFO:reset_stream_out, VGA_Pixel_RGB_Resampler:reset, VGA_Pixel_Scaler:reset, avalon_st_adapter:in_rst_0_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [VGA_Controller:reset, VGA_Dual_Clock_FIFO:reset_stream_out]
wire vga_pll_reset_source_reset; // VGA_PLL:reset_source_reset -> rst_controller_001:reset_in0
Computer_System_VGA_Subsystem_Char_Buf_Subsystem char_buf_subsystem (
.avalon_char_source_ready (char_buf_subsystem_avalon_char_source_ready), // avalon_char_source.ready
.avalon_char_source_startofpacket (char_buf_subsystem_avalon_char_source_startofpacket), // .startofpacket
.avalon_char_source_endofpacket (char_buf_subsystem_avalon_char_source_endofpacket), // .endofpacket
.avalon_char_source_valid (char_buf_subsystem_avalon_char_source_valid), // .valid
.avalon_char_source_data (char_buf_subsystem_avalon_char_source_data), // .data
.char_buffer_control_slave_address (char_buffer_control_slave_address), // char_buffer_control_slave.address
.char_buffer_control_slave_byteenable (char_buffer_control_slave_byteenable), // .byteenable
.char_buffer_control_slave_read (char_buffer_control_slave_read), // .read
.char_buffer_control_slave_write (char_buffer_control_slave_write), // .write
.char_buffer_control_slave_writedata (char_buffer_control_slave_writedata), // .writedata
.char_buffer_control_slave_readdata (char_buffer_control_slave_readdata), // .readdata
.char_buffer_slave_address (char_buffer_slave_address), // char_buffer_slave.address
.char_buffer_slave_clken (char_buffer_slave_clken), // .clken
.char_buffer_slave_chipselect (char_buffer_slave_chipselect), // .chipselect
.char_buffer_slave_write (char_buffer_slave_write), // .write
.char_buffer_slave_readdata (char_buffer_slave_readdata), // .readdata
.char_buffer_slave_writedata (char_buffer_slave_writedata), // .writedata
.char_buffer_slave_byteenable (char_buffer_slave_byteenable), // .byteenable
.sys_clk_clk (sys_clk_clk), // sys_clk.clk
.sys_reset_reset_n (sys_reset_reset_n) // sys_reset.reset_n
);
Computer_System_VGA_Subsystem_VGA_Alpha_Blender vga_alpha_blender (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.foreground_data (char_buf_subsystem_avalon_char_source_data), // avalon_foreground_sink.data
.foreground_startofpacket (char_buf_subsystem_avalon_char_source_startofpacket), // .startofpacket
.foreground_endofpacket (char_buf_subsystem_avalon_char_source_endofpacket), // .endofpacket
.foreground_valid (char_buf_subsystem_avalon_char_source_valid), // .valid
.foreground_ready (char_buf_subsystem_avalon_char_source_ready), // .ready
.background_data (avalon_st_adapter_out_0_data), // avalon_background_sink.data
.background_startofpacket (avalon_st_adapter_out_0_startofpacket), // .startofpacket
.background_endofpacket (avalon_st_adapter_out_0_endofpacket), // .endofpacket
.background_valid (avalon_st_adapter_out_0_valid), // .valid
.background_ready (avalon_st_adapter_out_0_ready), // .ready
.output_ready (vga_alpha_blender_avalon_blended_source_ready), // avalon_blended_source.ready
.output_data (vga_alpha_blender_avalon_blended_source_data), // .data
.output_startofpacket (vga_alpha_blender_avalon_blended_source_startofpacket), // .startofpacket
.output_endofpacket (vga_alpha_blender_avalon_blended_source_endofpacket), // .endofpacket
.output_valid (vga_alpha_blender_avalon_blended_source_valid) // .valid
);
Computer_System_VGA_Subsystem_VGA_Controller vga_controller (
.clk (vga_pll_vga_clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.data (vga_dual_clock_fifo_avalon_dc_buffer_source_data), // avalon_vga_sink.data
.startofpacket (vga_dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.endofpacket (vga_dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.valid (vga_dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.ready (vga_dual_clock_fifo_avalon_dc_buffer_source_ready), // .ready
.VGA_CLK (vga_CLK), // external_interface.export
.VGA_HS (vga_HS), // .export
.VGA_VS (vga_VS), // .export
.VGA_BLANK (vga_BLANK), // .export
.VGA_SYNC (vga_SYNC), // .export
.VGA_R (vga_R), // .export
.VGA_G (vga_G), // .export
.VGA_B (vga_B) // .export
);
Computer_System_VGA_Subsystem_VGA_Dual_Clock_FIFO vga_dual_clock_fifo (
.clk_stream_in (sys_clk_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_reset_out_reset), // reset_stream_in.reset
.clk_stream_out (vga_pll_vga_clk_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_001_reset_out_reset), // reset_stream_out.reset
.stream_in_ready (vga_alpha_blender_avalon_blended_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (vga_alpha_blender_avalon_blended_source_startofpacket), // .startofpacket
.stream_in_endofpacket (vga_alpha_blender_avalon_blended_source_endofpacket), // .endofpacket
.stream_in_valid (vga_alpha_blender_avalon_blended_source_valid), // .valid
.stream_in_data (vga_alpha_blender_avalon_blended_source_data), // .data
.stream_out_ready (vga_dual_clock_fifo_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (vga_dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (vga_dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (vga_dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (vga_dual_clock_fifo_avalon_dc_buffer_source_data) // .data
);
Computer_System_VGA_Subsystem_VGA_PLL vga_pll (
.ref_clk_clk (vga_pll_ref_clk_clk), // ref_clk.clk
.ref_reset_reset (vga_pll_ref_reset_reset), // ref_reset.reset
.vga_clk_clk (vga_pll_vga_clk_clk), // vga_clk.clk
.reset_source_reset (vga_pll_reset_source_reset) // reset_source.reset
);
Computer_System_VGA_Subsystem_VGA_Pixel_DMA vga_pixel_dma (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.master_readdatavalid (pixel_dma_master_readdatavalid), // avalon_pixel_dma_master.readdatavalid
.master_waitrequest (pixel_dma_master_waitrequest), // .waitrequest
.master_address (pixel_dma_master_address), // .address
.master_arbiterlock (pixel_dma_master_lock), // .lock
.master_read (pixel_dma_master_read), // .read
.master_readdata (pixel_dma_master_readdata), // .readdata
.slave_address (pixel_dma_control_slave_address), // avalon_control_slave.address
.slave_byteenable (pixel_dma_control_slave_byteenable), // .byteenable
.slave_read (pixel_dma_control_slave_read), // .read
.slave_write (pixel_dma_control_slave_write), // .write
.slave_writedata (pixel_dma_control_slave_writedata), // .writedata
.slave_readdata (pixel_dma_control_slave_readdata), // .readdata
.stream_ready (vga_pixel_dma_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_startofpacket (vga_pixel_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (vga_pixel_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (vga_pixel_dma_avalon_pixel_source_valid), // .valid
.stream_data (vga_pixel_dma_avalon_pixel_source_data) // .data
);
Computer_System_VGA_Subsystem_VGA_Pixel_FIFO vga_pixel_fifo (
.clk_stream_in (sys_clk_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_reset_out_reset), // reset_stream_in.reset
.clk_stream_out (sys_clk_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_reset_out_reset), // reset_stream_out.reset
.stream_in_ready (vga_pixel_dma_avalon_pixel_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (vga_pixel_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_in_endofpacket (vga_pixel_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (vga_pixel_dma_avalon_pixel_source_valid), // .valid
.stream_in_data (vga_pixel_dma_avalon_pixel_source_data), // .data
.stream_out_ready (vga_pixel_fifo_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (vga_pixel_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (vga_pixel_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (vga_pixel_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (vga_pixel_fifo_avalon_dc_buffer_source_data) // .data
);
Computer_System_VGA_Subsystem_VGA_Pixel_RGB_Resampler vga_pixel_rgb_resampler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (vga_pixel_fifo_avalon_dc_buffer_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (vga_pixel_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_in_valid (vga_pixel_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_in_ready (vga_pixel_fifo_avalon_dc_buffer_source_ready), // .ready
.stream_in_data (vga_pixel_fifo_avalon_dc_buffer_source_data), // .data
.stream_out_ready (vga_pixel_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (vga_pixel_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (vga_pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (vga_pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (vga_pixel_rgb_resampler_avalon_rgb_source_data) // .data
);
Computer_System_VGA_Subsystem_VGA_Pixel_Scaler vga_pixel_scaler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (vga_pixel_rgb_resampler_avalon_rgb_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (vga_pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (vga_pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (vga_pixel_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_in_data (vga_pixel_rgb_resampler_avalon_rgb_source_data), // .data
.stream_out_ready (vga_pixel_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (vga_pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (vga_pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (vga_pixel_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (vga_pixel_scaler_avalon_scaler_source_data), // .data
.stream_out_channel (vga_pixel_scaler_avalon_scaler_source_channel) // .channel
);
Computer_System_VGA_Subsystem_avalon_st_adapter #(
.inBitsPerSymbol (10),
.inUsePackets (1),
.inDataWidth (30),
.inChannelWidth (2),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (30),
.outChannelWidth (0),
.outErrorWidth (0),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (rst_controller_reset_out_reset), // in_rst_0.reset
.in_0_data (vga_pixel_scaler_avalon_scaler_source_data), // in_0.data
.in_0_valid (vga_pixel_scaler_avalon_scaler_source_valid), // .valid
.in_0_ready (vga_pixel_scaler_avalon_scaler_source_ready), // .ready
.in_0_startofpacket (vga_pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.in_0_endofpacket (vga_pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.in_0_channel (vga_pixel_scaler_avalon_scaler_source_channel), // .channel
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_startofpacket (avalon_st_adapter_out_0_startofpacket), // .startofpacket
.out_0_endofpacket (avalon_st_adapter_out_0_endofpacket) // .endofpacket
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~sys_reset_reset_n), // reset_in0.reset
.clk (sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (vga_pll_reset_source_reset), // reset_in0.reset
.clk (vga_pll_vga_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module altera_up_video_dma_to_memory (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
// Bidirectional
// Outputs
stream_ready,
master_write,
master_writedata,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
// Bidirectional
// Outputs
output stream_ready;
output master_write;
output [MDW:0] master_writedata;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [DW: 0] temp_data;
reg temp_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
begin
temp_data <= 'h0;
temp_valid <= 1'b0;
end
else if (stream_ready)
begin
temp_data <= stream_data;
temp_valid <= stream_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_ready = ~reset & (~temp_valid | ~master_waitrequest);
assign master_write = temp_valid;
assign master_writedata = temp_data;
assign inc_address = stream_ready & stream_valid;
assign reset_address = inc_address & stream_startofpacket;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_Video_In_Subsystem_Video_In_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 23;
parameter ODW = 15;
parameter IEW = 1;
parameter OEW = 0;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[23:16], stream_in_data[23:22]};
assign g = {stream_in_data[15: 8], stream_in_data[15:14]};
assign b = {stream_in_data[ 7: 0], stream_in_data[ 7: 6]};
assign a = ALPHA;
assign converted_data[15:11] = r[ 9: 5];
assign converted_data[10: 5] = g[ 9: 4];
assign converted_data[ 4: 0] = b[ 9: 5];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule |
module Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Onchip_SRAM (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clken,
clken2,
freeze,
reset,
reset_req,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "Computer_System_VGA_Subsystem_Char_Buf_Subsystem_Onchip_SRAM.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 10: 0] address;
input [ 10: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clken;
input clken2;
input freeze;
input reset;
input reset_req;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire not_clken;
wire not_clken2;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write & clken;
assign not_clken = ~clken;
assign not_clken2 = ~clken2;
assign clocken0 = ~reset_req;
assign wren2 = chipselect2 & write2 & clken2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.addressstall_a (not_clken),
.addressstall_b (not_clken2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK0",
the_altsyncram.indata_reg_b = "CLOCK0",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2048,
the_altsyncram.numwords_a = 2048,
the_altsyncram.numwords_b = 2048,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 11,
the_altsyncram.widthad_b = 11,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule |
module Computer_System_Video_In_Subsystem_Video_In_Scaler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 0; // Frame's Channel Width
parameter DW = 15; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 8; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 320; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [CW: 0] stream_out_channel;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [CW: 0] internal_channel;
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_channel = 'h0;
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_shrink Shrink_Frame (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Shrink_Frame.DW = DW,
Shrink_Frame.WW = WIW,
Shrink_Frame.HW = HIW,
Shrink_Frame.WIDTH_IN = WIDTH_IN,
Shrink_Frame.WIDTH_DROP_MASK = WIDTH_DROP_MASK,
Shrink_Frame.HEIGHT_DROP_MASK = HEIGHT_DROP_MASK;
endmodule |
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