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module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a(clock, a_in, b_in, temp);
always @(posedge clock)
begin
out <= a_in & temp;
end
endmodule |
module timescale_syntax (a,b,c);
input a;
input b;
output c;
assign c = a ^ b;
endmodule |
module include_test (a,b,c);
input a;
input b;
output c;
`ifndef include_test_def
assign c = a & b;
`else
assign c = a | b;
`endif
endmodule |
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule |
module inferred_ram (clk,a,b,reset);
input reset;
input clk;
input [31:0] a;
output [31:0] b;
reg [31:0] mregs [8:0];
reg [8:0] adr;
reg [31:0] b;
always @ (posedge clk )
if (!reset)
begin
mregs [adr] <= a;
b <= mregs [adr-1];
adr <= adr+1;
end
else
adr <= 8'b00000000;
endmodule |
module delay_syntax (clock,a,b,c,d);
input clock;
input a;
output b;
output c;
output d;
reg x;
reg y;
reg delayed;
assign b = x;
assign c = y;
assign #10 d = delayed;
always @ (posedge clock)
begin
x <= a;
y <= x;
delayed <= x;
end
endmodule |
module define_syntax (a,b,c);
input a;
input b;
output c;
wire c_wire;
assign c = c_wire;
`ifdef and_module
assign c_wire = a & b;
`elsif or_module
assign c_wire = a | b;
`else
assign c_wire = a ^ b;
`endif
endmodule |
module function_syntax (clock, a, b, c );
input clock;
input a;
input b;
output c;
//range of function xor_them returns a wire
function [1:1] xor_them;
input x;
input y;
reg regz;
begin
xor_them = x ^ y;
end
endfunction
assign c = xor_them(a,b);
endmodule |
module bm_DL_behavioural_full_adder (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
reg s, Cout;
always @(x or y or Cin)
{Cout, s} = x + y + Cin;
endmodule |
module bm_dag2_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= temp_a & temp_b;
out1 <= c_in & d_in;
end
endmodule |
module bm_expr_all_mod(clock,
reset_n,
a_in,
b_in,
number_in_1,
number_in_2,
number_in_3,
land_1,
lor_1,
lor_2,
land_2,
land_out,
lor_out,
leq_out,
lneq_out,
lgt_out,
lge_out,
llt_out,
lle_out,
add_out,
sub_out,
shift_l1_out,
shift_r1_out,
shift_l2_out,
shift_r2_out,
and_out,
or_out,
xor_out,
xnor_out,
lembed_out,
embed_out,
bit_sel_out,
concat_out,
range_select_out,
number_out,
number_out2,
not_out,
lnot_out,
two_compliment_out
);
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
//------------------------------------------------------------
input [`BITS-1:0] number_in_1;
input [`BITS-1:0] number_in_2;
input [`BITS-2:0] number_in_3;
input [`BITS-1:0]land_1;
input [`BITS-1:0]lor_1;
input lor_2;
input land_2;
//------------------------------------------------------------
output land_out;
reg land_out;
output lor_out;
reg lor_out;
output leq_out;
reg leq_out;
output lneq_out;
reg lneq_out;
output lgt_out;
reg lgt_out;
output lge_out;
reg lge_out;
output llt_out;
reg llt_out;
output lle_out;
reg lle_out;
output [`BITS-1:0] add_out;
reg [`BITS-1:0] add_out;
output [`BITS-1:0] sub_out;
reg [`BITS-1:0] sub_out;
output [`BITS-1:0] shift_l1_out;
reg [`BITS-1:0] shift_l1_out;
output [`BITS-1:0] shift_r1_out;
reg [`BITS-1:0] shift_r1_out;
output [`BITS-1:0] shift_l2_out;
reg [`BITS-1:0] shift_l2_out;
output [`BITS-1:0] shift_r2_out;
reg [`BITS-1:0] shift_r2_out;
output [`BITS-1:0] and_out;
reg [`BITS-1:0] and_out;
output [`BITS-1:0] or_out;
reg [`BITS-1:0] or_out;
output [`BITS-1:0] xor_out;
reg [`BITS-1:0] xor_out;
output [`BITS-1:0] xnor_out;
reg [`BITS-1:0] xnor_out;
output lembed_out;
reg lembed_out;
output [`BITS-1:0] embed_out;
reg [`BITS-1:0] embed_out;
always @(posedge clock)
begin
/* simple tests of all the binary expressions */
land_out <= land_1 && land_2;
lor_out <= lor_1 || lor_2;
leq_out <= land_1 == lor_1;
lneq_out <= land_1 != lor_1;
// leq_out <= land_1 === land_2; /* not synthesizable */
// lneq_out <= land_1 !== land_2; /* not synthesizable */
lgt_out <= land_1 > lor_1;
lge_out <= land_1 >= lor_1;
lle_out <= land_1 <= lor_1;
llt_out <= land_1 < lor_1;
add_out <= number_in_1 + number_in_2;
sub_out <= number_in_1 - number_in_2;
shift_l1_out <= number_in_1 << 4'b0010;
shift_l2_out <= number_in_1 << 3;
shift_r1_out <= number_in_1 >> 4'b0011;
shift_r2_out <= number_in_1 >> 1;
and_out <= number_in_1 & number_in_3;
or_out <= number_in_1 | number_in_3;
xor_out <= number_in_1 ^ number_in_3;
xnor_out <= number_in_1 ~^ number_in_3;
/* tests of embedded */
lembed_out <= (((land_1 == lor_1) || (land_2 != lor_2) || (number_in_1 > number_in_2)) && (number_in_1 <= number_in_2));
embed_out <= (((number_in_1 + number_in_2 - number_in_3) & (number_in_3)) | (((number_in_1 ~^ number_in_2) ^ number_in_1)));
end /* binary exp testing */
//------------------------------------------------------------
output bit_sel_out;
reg bit_sel_out;
output [`BITS-1:0] concat_out;
reg [`BITS-1:0] concat_out;
output [`BITS-1:0] range_select_out;
reg [`BITS-1:0] range_select_out;
/* simple selctions and concatenation */
always @(posedge clock)
begin
bit_sel_out <= number_in_1[2] & land_2;
concat_out <= {number_in_1[0], number_in_2[0], number_in_3[0], number_in_1[1]} & land_1;
range_select_out <= number_in_1[2:1] & {land_2, land_2};
end /* bitselect and concatenation */
//------------------------------------------------------------
output [`BITS-1:0] number_out;
reg [`BITS-1:0] number_out;
output [`BITS-1:0] number_out2;
reg [`BITS-1:0] number_out2;
always @(posedge clock)
begin
number_out <= 4'b1010 & land_1;
number_out2 <= 4'b1010 & lor_1;
end
//------------------------------------------------------------
output [`BITS-1:0] not_out;
reg [`BITS-1:0] not_out;
output lnot_out;
reg lnot_out;
output [`BITS-1:0] two_compliment_out;
reg [`BITS-1:0] two_compliment_out;
/* Testing simple unary operations */
always @(posedge clock)
begin
not_out <= ~number_in_1;
lnot_out <= !number_in_1;
two_compliment_out <= -number_in_1;
end
endmodule |
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire temp;
reg [`BITS-1:0]temp2;
d mya_d(clock, a_in[0], b_in[0], temp);
always @(posedge clock)
begin
temp2 <= a_in & temp;
out <= b_in & temp2;
end
endmodule |
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c(clock, a_in[0], b_in[0], temp2);
always @(posedge clock)
begin
temp <= a_in | b_in ^ temp2;
out <= a_in ^ temp;
end
endmodule |
module c(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
reg out1;
reg temp;
wire temp2;
d myc_d(clock, c_in, d_in, temp2);
always @(posedge clock)
begin
temp <= c_in & temp2;
out1 <= temp ^ d_in;
end
endmodule |
module d(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
reg out1;
reg temp;
always @(posedge clock)
begin
temp <= c_in ^ d_in;
out1 <= temp | d_in;
end
endmodule |
module bm_dag3_lpm_log(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1:0] d;
// ASSIGN STATEMENTS
assign out = a | b | c | d;
assign a = b_in + c;
assign b = a_in ^ c;
assign c = ~a_in;
assign d = b - b_in;
endmodule |
module bm_DL_4_bit_shift_register (R, L, w, Clock, Q);
input [3:0] R;
input L, w, Clock;
output [3:0] Q;
wire [3:0] Q;
muxdff Stage3 (w, R[3], L, Clock, Q[3]);
muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);
muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);
muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);
endmodule |
module muxdff (D0, D1, Sel, Clock, Q);
input D0, D1, Sel, Clock;
output Q;
reg Q;
always @(posedge Clock)
if (~Sel)
Q <= D0;
else
Q <= D1;
endmodule |
module bm_DL_74381_ALU(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)
3'b000: F = 4'b0000;
3'b001: F = B - A;
3'b010: F = A - B;
3'b011: F = A + B;
3'b100: F = A ^ B;
3'b101: F = A | B;
3'b110: F = A & B;
3'b111: F = 4'b1111;
endcase
endmodule |
module bm_DL_4_16_encoder(W, Y, En);
input [3:0] W;
input En;
output [15:0] Y;
wire [3:0] M;
dec2to4 Dec1 (W[3:2], M[3:0], En);
dec2to4 Dec2 (W[1:0], Y[3:0], M[0]);
dec2to4 Dec3 (W[1:0], Y[7:4], M[1]);
dec2to4 Dec4 (W[1:0], Y[11:8], M[2]);
dec2to4 Dec5 (W[1:0], Y[15:12], M[3]);
endmodule |
module dec2to4(W, Y, En);
input [1:0] W;
input En;
output [3:0] Y;
reg [3:0] Y;
always @(W or En)
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule |
module bm_dag1_log(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 | temp2 | temp3;
assign temp1 = a_in & b_in;
assign temp2 = a_in ^ b_in;
assign temp3 = b_in ^ b_in;
endmodule |
module bm_DL_4_bit_comparator (A, B, AeqB, AgtB, AltB);
input [3:0] A;
input [3:0] B;
output AeqB, AgtB, AltB;
reg AeqB, AgtB, AltB;
always @(A or B)
begin
// Andrew: added missing conditions.
if(A == B)
AeqB = 1;
else
AeqB = 0;
if (A > B)
AgtB = 1;
else
AgtB = 0;
if (A < B)
AltB = 1;
else
AltB = 0;
end
endmodule |
module bm_DL_four_bit_adder_continuous_assign (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule |
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule |
module bm_dag2_log(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 & temp2;
assign temp1 = a_in | b_in;
assign temp2 = temp1 ^ b_in;
endmodule |
module bm_DL_16_1_mux (W, S16, f);
input [15:0] W;
input [3:0] S16;
output f;
wire [3:0] M;
mux4to1 Mux1 (W[3:0], S16[1:0], M[0]);
mux4to1 Mux2 (W[7:4], S16[1:0], M[1]);
mux4to1 Mux3 (W[11:8], S16[1:0], M[2]);
mux4to1 Mux4 (W[15:12], S16[1:0], M[3]);
mux4to1 Mux5 (M[3:0], S16[3:2], f);
endmodule |
module mux4to1 (W, S, f);
input [3:0] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
if (S == 2'b00)
f = W[0];
else if (S == 2'b01)
f = W[1];
else if (S == 2'b10)
f = W[2];
else if (S == 2'b11)
f = W[3];
endmodule |
module bm_stmt_all_mod(clock,
reset_n,
a_in,
b_in,
out1,
out0,
out3,
out4,
out5,
out6,
out7,
out8,
out10,
out9);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
output out3;
output [`BITS-1:0] out4;
output out5;
output [`BITS-1:0] out6;
output out7;
output [`BITS-1:0] out8;
output out9;
output [`BITS-1:0] out10;
reg [`BITS-1:0] out0;
reg out1;
reg out3;
reg [`BITS-1:0] out4;
reg out5;
reg [`BITS-1:0] out6;
reg out7;
reg [`BITS-1:0] out8;
reg out9;
reg [`BITS-1:0] out10;
always @(posedge clock)
begin
case (a_in)
4'b0000: out0 <= 4'b1111 ;
4'b0001: out0 <= 4'b1110 ;
4'b0010: out0 <= 4'b1101 ;
4'b0011: out0 <= 4'b1100 ;
4'b0100: out0 <= 4'b1011 ;
4'b0101: out0 <= 4'b1010 ;
4'b0110: out0 <= 4'b1001 ;
4'b0111: out0 <= 4'b1000 ;
4'b1000: out0 <= 4'b0111 ;
4'b1001: out0 <= 4'b0110 ;
4'b1010: out0 <= 4'b0101 ;
4'b1011: out0 <= 4'b0100 ;
4'b1100: out0 <= 4'b0011 ;
4'b1101: out0 <= 4'b0010 ;
4'b1110: out0 <= 4'b0001 ;
4'b1111: out0 <= 4'b0000 ;
default: out0 <= 4'b0000 ;
endcase
end
always @(posedge clock)
begin
case (b_in)
1'b0: out1 <= 1'b1 ;
1'b1: out1 <= 1'b0 ;
default: out1 <= 1'b0 ;
endcase
end
always @(posedge clock)
begin
case (b_in)
1'b0:
begin
out3 <= 1'b1 ;
out4 <= 4'b0001 ;
end
1'b1:
begin
out3 <= 1'b0 ;
out4 <= 4'b0000 ;
end
default: out3 <= 1'b0 ;
endcase
end
always @(posedge clock)
begin
if (b_in == 1'b0)
begin
out5 <= 1'b1 ;
out6 <= 4'b0001 ;
end
else
begin
out5 <= 1'b0 ;
out6 <= 4'b0000 ;
end
end
always @(posedge clock)
begin
if (b_in == 1'b0)
begin
out7 <= 1'b1 ;
out8 <= 4'b0001 ;
end
else if (a_in == 4'b0000)
begin
out7 <= 1'b0 ;
out8 <= 4'b0100 ;
end
else
begin
out7 <= 1'b1 ;
out8 <= 4'b0000 ;
end
end
always @(posedge clock)
begin
out9 <= 1'b1;
out10 <= 4'b0000;
end
endmodule |
module bm_DL_4_1_mux (w0, w1, w2, w3, S, f);
input w0, w1, w2, w3;
input [1:0] S;
output f;
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
endmodule |
module bm_base_memory(clock,
we,
address_in,
address_out,
value_out,
out1,
out2,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input we;
input [`BITS-1:0]value_in;
input [`BITS-1:0]address_in;
input [`BITS-1:0]address_out;
output [`BITS-1:0] value_out;
wire [`BITS-1:0] value_out;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
reg [`BITS-1:0] address;
reg [`BITS-1:0] memory [`MEMORY_WORDS-1:0]; // 4 memory slots of Bits wide
wire [`BITS-1:0] temp;
always @(posedge clock)
begin
address <= address_in;
if (we == 1'b1)
memory[address] <= value_in;
end
assign value_out = memory[address_out];
always @(posedge clock)
begin
out1 <= value_out & address_in;
out2 <= out1 & 1'b0;
end
endmodule |
module bm_functional_test(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
counter
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [7:0] counter;
reg [`B2TS-1:0] out0;
reg [`B2TS-1:0] out1;
wire [`B2TS-1:0] temp1;
wire [`B2TS-1:0] temp2;
wire [`B2TS-1:0] temp3;
wire [`B2TS-1:0] temp4;
reg [7:0]counter;
always @(posedge clock or negedge reset_n)
begin
if (~reset_n)
begin
counter <= 0;
out1<= 0;
out0<= 0;
end
else
begin
case (counter)
8'b00000000: out0 <= a_in & b_in;
8'b00000001: out0 <= a_in | b_in;
8'b00000010: out0 <= a_in ^ b_in;
8'b00000011: out0 <= a_in * b_in;
8'b00000100: out0 <= a_in + b_in;
8'b00000101: out0 <= a_in - b_in;
8'b00000110: out0 <= temp1;
8'b00000111: out0 <= temp2;
8'b00001000: out0 <= temp3;
8'b00001001: out0 <= temp4;
8'b00001010: out0 <= temp1 ? temp2 : temp3;
default: out0 <= 8'b11001101;
endcase
if (counter <= 8'b00001111)
begin
out1 <= 1;
end
else
begin
out1 <= 0;
end
if (counter == 8'b11111111)
counter <= 0;
else
counter <= counter + 1;
end
end
assign temp1 = c_in * d_in;
assign temp2 = c_in + d_in;
assign temp3 = c_in - d_in;
assign temp4 = ~c_in & d_in;
endmodule |
module bm_if_reset(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
a top_a(clock, a_in, temp_a);
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 1'b0)
begin
out0 <= 2'b00;
out1 <= 1'b0;
end
else
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
end
endmodule |
module a(clock,
a_in,
out);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
case (a_in)
2'b00: out <= 2'b11 ;
2'b01: out <= 2'b10 ;
2'b10: out <= 2'b01 ;
2'b11: out <= 2'b00 ;
endcase
end
endmodule |
module memory_controller
(
clk,
addr1,
addr2,
we1,
we2,
data1,
data2,
sp_out,
dp_out1,
dp_out2
);
input clk;
input we1, we2;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] addr1,addr2;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] data1,data2;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] spi_out,dpi_out1,dpi_out2;
single_port_ram sp_ram (
.addr (addr1),
.data (data1),
.we (we1),
.clk (clk),
.out (spi_out)
);
dual_port_ram dp_ram (
.addr1 (addr1),
.addr2 (addr2),
.data1 (data1),
.data2 (data2),
.we1 (we1),
.we2 (we2),
.clk (clk),
.out1 (dpi_out1),
.out2 (dpi_out2)
);
always @ (posedge clk)
begin
sp_out <= spi_out;
dp_out1 <= dpi_out1;
dp_out2 <= dpi_out2;
end
endmodule |
module bm_DL_four_bit_adder_continuous_assign_using_vectors (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);
endmodule |
module bm_DL_2_1_mux (w0, w1, s, f);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule |
module bm_DL_logic_w_Dff2(x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output f, g;
reg f, g;
always @(posedge Clock)
begin
f <= x1 & x2;
g <= f | x3;
end
endmodule |
module bm_dag3_log_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
c top_c(clock, c_in, d_in, temp_c);
d top_d(clock, c_in, d_in, temp_d);
assign out0 = temp_a & temp_b;
assign out1 = temp_c & temp_d;
endmodule |
module c(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
wire out1;
wire temp;
wire temp2;
d myc_d(clock, c_in, d_in, temp2);
assign out1 = temp ^ d_in;
assign temp = c_in & temp2;
endmodule |
module bm_dag3_lpm_log_mod(clock,
reset_n,
first,
sceond,
third,
fourth,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, first, sceond, temp_a);
b top_b(clock, first, sceond, temp_b);
c top_c(clock, third, fourth, temp_c);
d top_d(clock, third, fourth, temp_d);
assign out0 = temp_a & temp_b;
assign out1 = temp_c + temp_d;
endmodule |
module a(clock,
fifth,
sixth,
out2);
input clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out2;
wire [`BITS-1:0] temp1;
d mya_d(clock, fifth[0], sixth[0], temp1[0]);
d mya_d2(clock, fifth[0], sixth[1], temp1[1]);
always @(posedge clock)
begin
out2 <= fifth & sixth & temp1;
end
endmodule |
module b(clock,
seventh,
eight,
out3);
input clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0] out3;
reg [`BITS-1:0] out3;
c myb_c(clock, seventh[0], eight[0], temp3);
always @(posedge clock)
begin
temp2 <= seventh | eight ^ temp3;
out3 <= seventh ^ temp2;
end
endmodule |
module c(clock,
ninth,
tenth,
out4);
// SIGNAL DECLARATIONS
input clock;
input ninth;
input tenth;
output out4;
wire out4;
wire temp4;
wire temp5;
d myc_d(clock, ninth, tenth, temp5);
assign out4 = temp4 ^ tenth;
assign temp4 = ninth - temp5;
endmodule |
module d(clock,
eleventh,
twelfth,
out5);
// SIGNAL DECLARATIONS
input clock;
input eleventh;
input twelfth;
output out5;
reg out5;
reg temp6;
always @(posedge clock)
begin
temp6 <= eleventh ^ twelfth;
out5 <= temp6 | twelfth;
end
endmodule |
module bm_my_D_latch2(D, C, Q);
input D, C;
output Q;
reg Q;
always @(D or C)
Q = D;
endmodule |
module bm_sfifo_rtl(
clock,
reset_n,
data_in,
read_n,
write_n,
data_out,
full,
empty,
half);
// INPUTS
input clock; // Clock input
input reset_n; // Active low reset
input [`FIFO_WIDTH-1:0] data_in; // Data input to FIFO
input read_n; // Read FIFO (active low)
input write_n; // Write FIFO (active low)
// OUTPUTS
output [`FIFO_WIDTH-1:0] data_out; // FIFO output data
output full; // FIFO is full
output empty; // FIFO is empty
output half; // FIFO is half full
// or more
// INOUTS
// SIGNAL DECLARATIONS
wire clock;
wire reset_n;
wire [`FIFO_WIDTH-1:0] data_in;
wire read_n;
wire write_n;
reg [`FIFO_WIDTH-1:0] data_out;
wire full;
wire empty;
wire half;
// The FIFO memory.
reg [`FIFO_WIDTH-1:0] fifo_mem[`FIFO_DEPTH-1:0];
// How many locations in the FIFO
// are occupied?
reg [`FIFO_BITS-1:0] counter;
// FIFO read pointer points to
// the location in the FIFO to
// read from next
reg [`FIFO_BITS-1:0] rd_pointer;
// FIFO write pointer points to
// the location in the FIFO to
// write to next
reg [`FIFO_BITS-1:0] wr_pointer;
// PARAMETERS
// ASSIGN STATEMENTS
assign full = (counter == `FIFO_DEPTH) ? 1'b1 : 1'b0;
assign empty = (counter == 0) ? 1'b1 : 1'b0;
assign half = (counter >= `FIFO_HALF) ? 1'b1 : 1'b0;
// MAIN CODE
// This block contains all devices affected by the clock
// and reset inputs
always @(posedge clock) begin
if (~reset_n) begin
// Reset the FIFO pointer
rd_pointer <= 0;
wr_pointer <= 0;
counter <= 0;
end
else begin
// If we are doing a simultaneous read and write,
// there is no change to the counter
if (~read_n && write_n) begin
// Decrement the FIFO counter
counter <= counter - 1;
end
else if (~write_n && read_n) begin
// Increment the FIFO counter
counter <= counter + 1;
end
if (~read_n) begin
// Increment the read pointer
// Check if the read pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (rd_pointer == `FIFO_DEPTH-1)
rd_pointer <= 0;
else
rd_pointer <= rd_pointer + 1;
end
if (~write_n) begin
// Increment the write pointer
// Check if the write pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (wr_pointer == `FIFO_DEPTH-1)
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end
end
end
// This block contains all devices affected by the clock
// but not reset
always @(posedge clock) begin
if (~read_n) begin
// Output the data
data_out <= fifo_mem[rd_pointer];
end
if (~write_n) begin
// Store the data
fifo_mem[wr_pointer] <= data_in;
end
end
endmodule // Sfifo |
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp2;
a my_a(clock, a_in, b_in, temp);
always @(posedge clock)
begin
temp2 <= a_in & b_in;
out <= a_in ^ temp;
end
endmodule |
module bm_DL_BCD_7_segment_without_x (bcd, leds);
input [3:0] bcd;
output [7:1] leds;
reg [7:1] leds;
always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
6: leds = 7'b1011111;
7: leds = 7'b1110000;
8: leds = 7'b1111111;
9: leds = 7'b1111011;
default: leds = 7'b1111111;
endcase
endmodule |
module bm_DL_logic_w_Dff(x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output f, g;
reg f, g;
always @(posedge Clock)
begin
f <= x1 & x2;
g <= f | x3;
end
endmodule |
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock)
begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule |
module bm_DL_2_cascaded_flip_flops(D, Clock, Q1, Q2);
input D, Clock;
output Q1, Q2;
reg Q1, Q2;
always @(posedge Clock)
begin
Q1 <= D;
Q2 <= Q1;
end
endmodule |
module bm_add_lpm(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in + b_in;
endmodule |
module bm_dag4_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(.clock(clock), .a_in(a_in), .b_in(b_in), .out(temp_a));
b top_b(clock, a_in, b_in, temp_b);
c top_c(clock, c_in, d_in, temp_c);
d top_d(clock, c_in, d_in, temp_d);
always @(posedge clock)
begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule |
module bm_DL_structural_logic (x1, x2, x3, f);
input x1, x2, x3;
output f;
wire k, g, h;
and (g, x1, x2);
not (k,x2);
and (h, k, x3);
or (f, g, h);
endmodule |
module bm_and_log(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in & b_in;
endmodule |
module c(
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input c_in;
input d_in;
output out1;
wire out1;
wire temp;
assign out1 = temp ^ d_in;
assign temp = c_in & d_in;
endmodule |
module bm_DL_D_flipflop(D, Clock, Q);
input D, Clock;
output Q;
reg Q;
always @(posedge Clock)
Q <= D;
endmodule |
module bm_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
always @(posedge clock)
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
endmodule |
module bm_dag1_lpm(clock,
reset_n,
a_in,
b_in,
out);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 + temp2 - temp3;
assign temp1 = a_in + b_in;
assign temp2 = a_in - b_in;
assign temp3 = b_in + b_in;
endmodule |
module bm_if_common(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, temp_a);
always @(posedge clock)
begin
if (c_in == 1'b0)
begin
out0 <= 2'b00;
out1 <= 1'b0;
end
else
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
out2 <= temp_a;
end
endmodule |
module a(clock,
a_in,
out);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock)
begin
case (a_in)
2'b00: out2 <= 2'b11 ;
2'b01: out1 <= 2'b10 ;
2'b10: out1 <= 2'b01 ;
2'b11: out1 <= 2'b00 ;
endcase
out <= out1 & out2;
end
endmodule |
module bm_DL_structural_logic2 (x1, x2, x3, x4, f, g, h);
input x1, x2, x3, x4;
output f, g, h;
wire z1, z2, z3, z4;
and (z1, x1, x3);
and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);
endmodule |
module bm_DL_Dff_w_synch_reset(D, Clock, Resetn, Q);
input D, Clock, Resetn;
output Q;
reg Q;
always @(posedge Clock)
if (!Resetn)
Q <= 0;
else
Q <= D;
endmodule |
module bm_my_D_latch1(D, C, Q, reset);
input D, C;
input reset;
output Q;
reg Q;
always @(*)
begin
if (~reset)
begin
Q = 0;
end
else
begin
Q = D;
end
end
endmodule |
module bm_DL_BCD_adder (Cin, X, Y, S, Cout, Z);
input Cin;
input [3:0] X, Y;
output [3:0] S;
output Cout;
reg [3:0] S;
reg Cout;
output [4:0] Z;
reg [4:0] Z;
always @(X or Y or Cin)
begin
Z = X + Y + Cin;
if (Z[3:0] < 4'b1010)
{Cout, S} = Z;
else
{Cout, S} = Z + 6;
end
endmodule |
module bm_if_collapse(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
a top_a(clock, a_in, b_in, temp_a);
always @(posedge clock)
begin
if (c_in == 1'b0)
begin
out0 <= 2'b00;
out1 <= 1'b0;
end
else
begin
if (d_in == 1'b1)
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
end
out2 <= temp_a;
end
endmodule |
module sv_chip3_hierarchy_no_mem (tm3_clk_v0, tm3_clk_v2, tm3_vidin_llc, tm3_vidin_vs, tm3_vidin_href, tm3_vidin_cref, tm3_vidin_rts0, tm3_vidin_vpo, tm3_vidin_sda, tm3_vidin_scl, vidin_new_data, vidin_rgb_reg, vidin_addr_reg);
input tm3_clk_v0;
input tm3_clk_v2;
input tm3_vidin_llc;
input tm3_vidin_vs;
input tm3_vidin_href;
input tm3_vidin_cref;
input tm3_vidin_rts0;
input[15:0] tm3_vidin_vpo;
output tm3_vidin_sda;
wire tm3_vidin_sda;
reg tm3_vidin_sda_xhdl0;
output tm3_vidin_scl;
reg tm3_vidin_scl;
output vidin_new_data;
reg vidin_new_data;
output[7:0] vidin_rgb_reg;
reg[7:0] vidin_rgb_reg;
output[18:0] vidin_addr_reg;
reg[18:0] vidin_addr_reg;
reg temp_reg1;
reg temp_reg2;
reg[9:0] horiz;
reg[7:0] vert;
reg creg1;
reg creg2;
reg creg3;
reg[18:0] vidin_addr_reg1;
reg[23:0] vidin_rgb_reg1;
reg[23:0] vidin_rgb_reg2;
parameter[4:0] reg_prog1 = 5'b00001;
parameter[4:0] reg_prog2 = 5'b00010;
parameter[4:0] reg_prog3 = 5'b00011;
parameter[4:0] reg_prog4 = 5'b00100;
parameter[4:0] reg_prog5 = 5'b00101;
parameter[4:0] reg_prog6 = 5'b00110;
parameter[4:0] reg_prog7 = 5'b00111;
parameter[4:0] reg_prog8 = 5'b01000;
parameter[4:0] reg_prog9 = 5'b01001;
parameter[4:0] reg_prog10 = 5'b01010;
parameter[4:0] reg_prog11 = 5'b01011;
parameter[4:0] reg_prog12 = 5'b01100;
parameter[4:0] reg_prog13 = 5'b01101;
parameter[4:0] reg_prog14 = 5'b01110;
parameter[4:0] reg_prog15 = 5'b01111;
parameter[4:0] reg_prog16 = 5'b10000;
parameter[4:0] reg_prog17 = 5'b10001;
parameter[4:0] reg_prog18 = 5'b10010;
parameter[4:0] reg_prog19 = 5'b10011;
parameter[4:0] reg_prog20 = 5'b10100;
parameter[4:0] reg_prog21 = 5'b10101;
parameter[4:0] reg_prog22 = 5'b10110;
parameter[4:0] reg_prog23 = 5'b10111;
parameter[4:0] reg_prog24 = 5'b11000;
parameter[4:0] reg_prog25 = 5'b11001;
parameter[4:0] reg_prog26 = 5'b11010;
parameter[4:0] reg_prog_end = 5'b11011;
reg rst;
reg rst_done;
reg[7:0] iicaddr;
reg[7:0] iicdata;
// wire vidin_llc;
// wire vidin_llc_int;
reg[6:0] iic_state;
reg iic_stop;
reg iic_start;
reg[4:0] reg_prog_state;
reg[4:0] reg_prog_nextstate;
assign tm3_vidin_sda = tm3_vidin_sda_xhdl0;
// ibuf ibuf_inst (tm3_vidin_llc, vidin_llc_int);
// bufg bufg_inst (vidin_llc_int, vidin_llc);
// PAJ double clock is trouble...always @(vidin_llc)
always @(posedge tm3_clk_v0)
begin
if (tm3_vidin_href == 1'b0)
begin
horiz <= 10'b0000000000 ;
end
else
begin
if (tm3_vidin_cref == 1'b0)
begin
horiz <= horiz + 1 ;
end
end
if (tm3_vidin_vs == 1'b1)
begin
vert <= 8'b00000000 ;
end
else
begin
if ((tm3_vidin_href == 1'b0) & (horiz != 10'b0000000000))
begin
vert <= vert + 1 ;
end
end
if (tm3_vidin_cref == 1'b1)
begin
vidin_rgb_reg1[23:19] <= tm3_vidin_vpo[15:11] ;
vidin_rgb_reg1[15:13] <= tm3_vidin_vpo[10:8] ;
vidin_rgb_reg1[18:16] <= tm3_vidin_vpo[7:5] ;
vidin_rgb_reg1[9:8] <= tm3_vidin_vpo[4:3] ;
vidin_rgb_reg1[2:0] <= tm3_vidin_vpo[2:0] ;
vidin_rgb_reg2 <= vidin_rgb_reg1 ;
end
else
begin
vidin_rgb_reg1[12:10] <= tm3_vidin_vpo[7:5] ;
vidin_rgb_reg1[7:3] <= tm3_vidin_vpo[4:0] ;
vidin_addr_reg1 <= {vert, tm3_vidin_rts0, horiz} ;
end
end
always @(posedge tm3_clk_v0)
begin
creg1 <= tm3_vidin_cref ;
creg2 <= creg1 ;
creg3 <= creg2 ;
if ((creg2 == 1'b0) & (creg3 == 1'b1) & ((vidin_addr_reg1[10]) == 1'b0) & ((vidin_addr_reg1[0]) == 1'b0))
begin
vidin_new_data <= 1'b1 ;
vidin_rgb_reg <= vidin_rgb_reg2[7:0] ;
vidin_addr_reg <= {({2'b00, vidin_addr_reg1[18:11]}), vidin_addr_reg1[9:1]} ;
end
else
begin
vidin_new_data <= 1'b0 ;
end
end
always @(posedge tm3_clk_v2)
begin
iic_stop <= 1'b0 ;
case (iic_state)
7'b0000000 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0000001 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0000010 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0000011 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0000100 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0000101 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0000110 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0000111 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0001000 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0001001 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0001010 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0001011 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0001100 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0001101 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0001110 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0001111 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0010000 :
begin
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0010001 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0010010 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0010011 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0010101 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0010110 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0010111 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0011000 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0011001 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0011010 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0011011 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0011100 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[7] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0011101 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0011110 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0011111 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[6] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100000 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100001 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0100010 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[5] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100011 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100100 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0100101 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[4] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100110 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0100111 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0101000 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[3] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0101001 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0101010 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0101011 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[2] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0101100 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0101101 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0101110 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[1] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0101111 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0110000 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0110001 :
begin
tm3_vidin_sda_xhdl0 <= iicaddr[0] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0110010 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0110011 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0110100 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0110101 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0110110 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0110111 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[7] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111000 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111001 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0111010 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[6] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111011 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111100 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b0111101 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[5] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111110 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b0111111 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1000000 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[4] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1000001 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1000010 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1000011 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[3] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1000100 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1000101 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1000110 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[2] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1000111 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1001000 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1001001 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[1] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1001010 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1001011 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1001100 :
begin
tm3_vidin_sda_xhdl0 <= iicdata[0] ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1001101 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1001110 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1001111 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b0 ;
end
7'b1010000 :
begin
tm3_vidin_sda_xhdl0 <= 1'b0 ;
tm3_vidin_scl <= 1'b1 ;
end
7'b1010001 :
begin
iic_stop <= 1'b1 ;
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b1 ;
end
default :
begin
iic_stop <= 1'b1 ;
tm3_vidin_sda_xhdl0 <= 1'b1 ;
tm3_vidin_scl <= 1'b1 ;
end
endcase
end
always @(reg_prog_state or iic_stop)
begin
case (reg_prog_state)
reg_prog1 :
begin
rst_done = 1'b1 ;
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog2 ;
end
else
begin
reg_prog_nextstate = reg_prog1 ;
end
end
reg_prog2 :
begin
iicaddr = 8'b00000010 ;
iicdata = {5'b11000, 3'b000} ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog3 ;
end
else
begin
reg_prog_nextstate = reg_prog2 ;
end
end
reg_prog3 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog4 ;
end
else
begin
reg_prog_nextstate = reg_prog3 ;
end
end
reg_prog4 :
begin
iicaddr = 8'b00000011 ;
iicdata = 8'b00100011 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog5 ;
end
else
begin
reg_prog_nextstate = reg_prog4 ;
end
end
reg_prog5 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog6 ;
end
else
begin
reg_prog_nextstate = reg_prog5 ;
end
end
reg_prog6 :
begin
iicaddr = 8'b00000110 ;
iicdata = 8'b11101011 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog7 ;
end
else
begin
reg_prog_nextstate = reg_prog6 ;
end
end
reg_prog7 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog8 ;
end
else
begin
reg_prog_nextstate = reg_prog7 ;
end
end
reg_prog8 :
begin
iicaddr = 8'b00000111 ;
iicdata = 8'b11100000 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog9 ;
end
else
begin
reg_prog_nextstate = reg_prog8 ;
end
end
reg_prog9 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog10 ;
end
else
begin
reg_prog_nextstate = reg_prog9 ;
end
end
reg_prog10 :
begin
iicaddr = 8'b00001000 ;
iicdata = 8'b10000000 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog11 ;
end
else
begin
reg_prog_nextstate = reg_prog10 ;
end
end
reg_prog11 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog12 ;
end
else
begin
reg_prog_nextstate = reg_prog11 ;
end
end
reg_prog12 :
begin
iicaddr = 8'b00001001 ;
iicdata = 8'b00000001 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog13 ;
end
else
begin
reg_prog_nextstate = reg_prog12 ;
end
end
reg_prog13 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog14 ;
end
else
begin
reg_prog_nextstate = reg_prog13 ;
end
end
reg_prog14 :
begin
iicaddr = 8'b00001010 ;
iicdata = 8'b10000000 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog15 ;
end
else
begin
reg_prog_nextstate = reg_prog14 ;
end
end
reg_prog15 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog16 ;
end
else
begin
reg_prog_nextstate = reg_prog15 ;
end
end
reg_prog16 :
begin
iicaddr = 8'b00001011 ;
iicdata = 8'b01000111 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog17 ;
end
else
begin
reg_prog_nextstate = reg_prog16 ;
end
end
reg_prog17 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog18 ;
end
else
begin
reg_prog_nextstate = reg_prog17 ;
end
end
reg_prog18 :
begin
iicaddr = 8'b00001100 ;
iicdata = 8'b01000000 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog19 ;
end
else
begin
reg_prog_nextstate = reg_prog18 ;
end
end
reg_prog19 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog20 ;
end
else
begin
reg_prog_nextstate = reg_prog19 ;
end
end
reg_prog20 :
begin
iicaddr = 8'b00001110 ;
iicdata = 8'b00000001 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog21 ;
end
else
begin
reg_prog_nextstate = reg_prog20 ;
end
end
reg_prog21 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog22 ;
end
else
begin
reg_prog_nextstate = reg_prog21 ;
end
end
reg_prog22 :
begin
iicaddr = 8'b00010000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog23 ;
end
else
begin
reg_prog_nextstate = reg_prog22 ;
end
end
reg_prog23 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog24 ;
end
else
begin
reg_prog_nextstate = reg_prog23 ;
end
end
reg_prog24 :
begin
iicaddr = 8'b00010001 ;
iicdata = 8'b00011100 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog25 ;
end
else
begin
reg_prog_nextstate = reg_prog24 ;
end
end
reg_prog25 :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b1 ;
if (iic_stop == 1'b0)
begin
reg_prog_nextstate = reg_prog26 ;
end
else
begin
reg_prog_nextstate = reg_prog25 ;
end
end
reg_prog26 :
begin
iicaddr = 8'b00010010 ;
iicdata = 8'b00001001 ;
iic_start = 1'b0 ;
if (iic_stop == 1'b1)
begin
reg_prog_nextstate = reg_prog_end ;
end
else
begin
reg_prog_nextstate = reg_prog26 ;
end
end
reg_prog_end :
begin
iicaddr = 8'b00000000 ;
iicdata = 8'b00000000 ;
iic_start = 1'b0 ;
reg_prog_nextstate = reg_prog_end ;
end
endcase
end
always @(posedge tm3_clk_v2)
begin
if (rst_done == 1'b1)
begin
rst <= 1'b1 ;
end
temp_reg1 <= tm3_vidin_rts0 ;
temp_reg2 <= temp_reg1 ;
if (rst == 1'b0)
begin
reg_prog_state <= reg_prog1 ;
end
else if ((temp_reg1 == 1'b0) & (temp_reg2 == 1'b1))
begin
reg_prog_state <= reg_prog1 ;
end
else
begin
reg_prog_state <= reg_prog_nextstate ;
end
if (iic_stop == 1'b0)
begin
iic_state <= iic_state + 1 ;
end
else if (iic_start == 1'b1)
begin
iic_state <= 7'b0000001 ;
end
end
endmodule |
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule |
module diffeq_paj_convert (Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport, CLK, reset);
input[31:0] Xinport;
input[31:0] Yinport;
input[31:0] Uinport;
input[31:0] Aport;
input[31:0] DXport;
input CLK;
input reset;
output[31:0] Xoutport;
output[31:0] Youtport;
output[31:0] Uoutport;
reg[31:0] Xoutport;
reg[31:0] Youtport;
reg[31:0] Uoutport;
reg[31:0] x_var;
reg[31:0] y_var;
reg[31:0] u_var;
wire[31:0] temp;
reg looping;
assign temp = u_var * DXport;
always @(posedge CLK)
begin
if (reset == 1'b1)
begin
looping <= 1'b0;
x_var <= 0;
y_var <= 0;
u_var <= 0;
end
else
if (looping == 1'b0)
begin
x_var <= Xinport;
y_var <= Yinport;
u_var <= Uinport;
looping <= 1'b1;
end
else if (x_var < Aport)
begin
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
y_var <= y_var + temp;//(u_var * DXport);
x_var <= x_var + DXport;
looping <= looping;
end
else
begin
Xoutport <= x_var ;
Youtport <= y_var ;
Uoutport <= u_var ;
looping <= 1'b0;
end
end
endmodule |
module spram(clock,
we,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input we;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0]value_out;
reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;
single_port_ram inst1(
.we(we),
.clk(clock),
.data(value_in),
.out(value_out),
.addr(address_counter));
always @(posedge clock)
begin
if (reset_n == 1'b1) begin
address_counter <= 4'b0000;
end
else
begin
address_counter <= address_counter + 1;
end
end
endmodule |
module spram_big(clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out;
reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;
single_port_ram inst1(
.we(clock),
.data(value_in),
.out(value_out),
.addr(address_counter));
always @(posedge clock)
begin
if (reset_n == 1'b1) begin
address_counter <= 4'b00000000;
end
else
begin
address_counter <= address_counter + 1;
end
end
endmodule |
module dpram(clock,
wren1,
wren2,
reset_n,
value_out,
value_out2,
value_in,
value_in2
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input wren1;
input wren2;
input [`WIDTH-1:0] value_in;
input [`WIDTH-1:0] value_in2;
output [`WIDTH-1:0] value_out;
output [`WIDTH-1:0] value_out2;
wire [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out2;
reg [`DEPTH-1:0] address_counter;
reg [`DEPTH-1:0] address_counter2;
reg [`WIDTH-1:0] temp;
reg [`WIDTH-1:0] temp2;
dual_port_ram inst1(
.we1(wren1),
.we2(wren2),
.clk(clock),
.data1(value_in),
.data2(value_in2),
.out1(value_out),
.out2(value_out2),
.addr1(address_counter),
.addr2(address_counter2));
always @(posedge clock)
begin
if (reset_n == 1'b1) begin
address_counter <= 4'b0000;
address_counter2 <= 4'b1111;
end
else
begin
address_counter <= address_counter + 1;
address_counter2 <= address_counter2 - 1;
end
end
endmodule |
module bar(a,b,c,d,clk);
input a,b,c;
input clk;
output d;
wire x;
register new_reg (a,clk,b, c,x);
endmodule |
module register(d,clk,resetn,en,q);
//parameter WIDTH=32;
input clk;
input resetn;
input en;
input [31:0] d;
output [31:0] q;
reg [31:0] q;
always @(posedge clk )
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule |
module define_tester (a,b, c);
input [31:0] a;
input [31:0] b;
output [31:0] c;
testmodule mymod (a,b,c);
endmodule |
module edge_testing (d0,clk, resetn, en,q0);
input clk;
input resetn;
input en;
input d0;
output q0;
posedge_reg_sync_reset zzxx_posedge_reg_sync_reset_zzxx (d2,clk,resetn,en,q2);
endmodule |
module posedge_reg_sync_reset(d,clk,resetn,en,q);
input clk;
input resetn;
input en;
input d;
output q;
reg q;
always @(posedge clk )
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule |
module testmodule (a,b,c);
input [31:0] a;
input [31:0] b;
output [31:0] c;
assign c = a & b;
endmodule |
module foobar (clk,d_in, d_out);
input clk;
input d_in;
output d_out;
assign d_out = a;
wire a;
wire b;
/*
assign wire2= 1'b1;
*/
assign a = (b & d_in);
endmodule |
module memory_loop(d_addr,d_loadresult,clk,wren,d1, do_something);
input do_something;
input wren;
input clk;
input [31:0] d1;
input [3:0] d_addr;
output [31:0] d_loadresult;
reg [31:0] d_loadresult;
wire [31:0] loaded_data;
single_port_ram smem_replace(
.clk (clk),
.we(wren),
.data(d1),
.out(loaded_data),
.addr(d_addr));
//assign d_loadresult = loaded_data; // trivial circuit in/out works (minus outputs "not beign driven")
always @(posedge clk) //procedural block dependant on memory.out
begin
case (do_something)
1'b0:
begin
d_loadresult <= loaded_data; //this line creates "combinational loops"
end
1'b1:
begin
d_loadresult <= ~loaded_data;
end
endcase
end
endmodule |
module bm_DL_nbit_adder_with_carryout_and_overflow_simplified (carryin, X, Y, S, carryout, overflow);
parameter n = 6'b100000;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
reg [n-1:0] S;
reg carryout, overflow;
always @(X or Y or carryin)
begin
{carryout, S} = X + Y + carryin;
overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1];
end
endmodule |
module bm_DL_simple_fsm (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [1:0] y, Y;
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'b00;
endcase
// Define the sequential block
always @(posedge Clock)
if (Resetn == 1'b0) y <= A;
else y <= Y;
// Define output
assign z = (y == C);
endmodule |
module bm_simple_memory(clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0]value_in;
output [`BITS-1:0] value_out;
wire [`BITS-1:0] value_out;
reg [`BITS-1:0] memory [3:0]; // 4 memory slots of Bits wide
reg [1:0] address_counter;
reg [1:0] address_counter2;
wire [`BITS-1:0] temp;
always @(posedge clock)
begin
address_counter <= 2'b00;
address_counter2 <= 2'b01;
if (reset_n == 1'b1)
memory[address_counter] <= value_in;
end
assign value_out = memory[address_counter2];
endmodule |
module bm_jk_rtl(
clk,
clr_n,
j,
k,
q,
q_n);
// INPUTS
input clk; // Clock
input clr_n; // Active low, asynchronous reset
input j; // J input
input k; // K input
// OUTPUTS
output q; // Output
output q_n; // Inverted output
// INOUTS
// SIGNAL DECLARATIONS
wire clk;
wire clr_n;
wire j;
wire k;
reg q;
wire q_n;
// PARAMETERS
// Define the J-K input combinations as parameters
parameter[1:0] HOLD = 0,
RESET = 1,
SET = 2,
TOGGLE = 3;
// ASSIGN STATEMENTS
assign #`DEL q_n = ~q;
// MAIN CODE
// Look at the falling edge of clock for state transitions
always @(negedge clk or negedge clr_n) begin
if (~clr_n) begin
// This is the reset condition. Most synthesis tools
// require an asynchronous reset to be defined this
// way.
q <= #`DEL 1'b0;
end
else begin
case ({j,k})
RESET: q <= #`DEL 1'b0;
SET: q <= #`DEL 1'b1;
TOGGLE: q <= #`DEL ~q;
endcase
end
end
endmodule // jk_FlipFlop |
module bm_DL_D_latch(D, Clk, Q);
input D, Clk;
output Q;
reg Q;
always @(D or Clk)
if (Clk)
Q = D;
endmodule |
module xbar(input clk, input reset,
input [30:0] io_xbar_in,
output [39:0] io_xbar_out,
input [199:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[4:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[9:5]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[14:10]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[19:15]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[24:20]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[29:25]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[34:30]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[39:35]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[44:40]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[49:45]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[54:50]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[59:55]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[64:60]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[69:65]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[74:70]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[79:75]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[84:80]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[89:85]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[94:90]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[99:95]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[104:100]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[109:105]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[114:110]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[119:115]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[124:120]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[129:125]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[134:130]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[139:135]];
assign io_xbar_out[28] = io_xbar_in[io_mux_configs[144:140]];
assign io_xbar_out[29] = io_xbar_in[io_mux_configs[149:145]];
assign io_xbar_out[30] = io_xbar_in[io_mux_configs[154:150]];
assign io_xbar_out[31] = io_xbar_in[io_mux_configs[159:155]];
assign io_xbar_out[32] = io_xbar_in[io_mux_configs[164:160]];
assign io_xbar_out[33] = io_xbar_in[io_mux_configs[169:165]];
assign io_xbar_out[34] = io_xbar_in[io_mux_configs[174:170]];
assign io_xbar_out[35] = io_xbar_in[io_mux_configs[179:175]];
assign io_xbar_out[36] = io_xbar_in[io_mux_configs[184:180]];
assign io_xbar_out[37] = io_xbar_in[io_mux_configs[189:185]];
assign io_xbar_out[38] = io_xbar_in[io_mux_configs[194:190]];
assign io_xbar_out[39] = io_xbar_in[io_mux_configs[199:195]];
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [21:0] io_configs_en,
output reg [703:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
always @ (io_configs_en[14] or io_d_in)
begin
if (io_configs_en[14])
begin
io_configs_out[479:448] = io_d_in;
end
end
always @ (io_configs_en[15] or io_d_in)
begin
if (io_configs_en[15])
begin
io_configs_out[511:480] = io_d_in;
end
end
always @ (io_configs_en[16] or io_d_in)
begin
if (io_configs_en[16])
begin
io_configs_out[543:512] = io_d_in;
end
end
always @ (io_configs_en[17] or io_d_in)
begin
if (io_configs_en[17])
begin
io_configs_out[575:544] = io_d_in;
end
end
always @ (io_configs_en[18] or io_d_in)
begin
if (io_configs_en[18])
begin
io_configs_out[607:576] = io_d_in;
end
end
always @ (io_configs_en[19] or io_d_in)
begin
if (io_configs_en[19])
begin
io_configs_out[639:608] = io_d_in;
end
end
always @ (io_configs_en[20] or io_d_in)
begin
if (io_configs_en[20])
begin
io_configs_out[671:640] = io_d_in;
end
end
always @ (io_configs_en[21] or io_d_in)
begin
if (io_configs_en[21])
begin
io_configs_out[703:672] = io_d_in;
end
end
endmodule |
module xbar(input clk, input reset,
input [23:0] io_xbar_in,
output [27:0] io_xbar_out,
input [139:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[4:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[9:5]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[14:10]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[19:15]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[24:20]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[29:25]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[34:30]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[39:35]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[44:40]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[49:45]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[54:50]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[59:55]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[64:60]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[69:65]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[74:70]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[79:75]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[84:80]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[89:85]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[94:90]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[99:95]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[104:100]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[109:105]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[114:110]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[119:115]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[124:120]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[129:125]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[134:130]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[139:135]];
endmodule |
module xbar(input clk, input reset,
input [34:0] io_xbar_in,
output [47:0] io_xbar_out,
input [287:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[5:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[11:6]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[17:12]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[23:18]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[29:24]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[35:30]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[41:36]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[47:42]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[53:48]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[59:54]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[65:60]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[71:66]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[77:72]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[83:78]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[89:84]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[95:90]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[101:96]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[107:102]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[113:108]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[119:114]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[125:120]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[131:126]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[137:132]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[143:138]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[149:144]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[155:150]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[161:156]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[167:162]];
assign io_xbar_out[28] = io_xbar_in[io_mux_configs[173:168]];
assign io_xbar_out[29] = io_xbar_in[io_mux_configs[179:174]];
assign io_xbar_out[30] = io_xbar_in[io_mux_configs[185:180]];
assign io_xbar_out[31] = io_xbar_in[io_mux_configs[191:186]];
assign io_xbar_out[32] = io_xbar_in[io_mux_configs[197:192]];
assign io_xbar_out[33] = io_xbar_in[io_mux_configs[203:198]];
assign io_xbar_out[34] = io_xbar_in[io_mux_configs[209:204]];
assign io_xbar_out[35] = io_xbar_in[io_mux_configs[215:210]];
assign io_xbar_out[36] = io_xbar_in[io_mux_configs[221:216]];
assign io_xbar_out[37] = io_xbar_in[io_mux_configs[227:222]];
assign io_xbar_out[38] = io_xbar_in[io_mux_configs[233:228]];
assign io_xbar_out[39] = io_xbar_in[io_mux_configs[239:234]];
assign io_xbar_out[40] = io_xbar_in[io_mux_configs[245:240]];
assign io_xbar_out[41] = io_xbar_in[io_mux_configs[251:246]];
assign io_xbar_out[42] = io_xbar_in[io_mux_configs[257:252]];
assign io_xbar_out[43] = io_xbar_in[io_mux_configs[263:258]];
assign io_xbar_out[44] = io_xbar_in[io_mux_configs[269:264]];
assign io_xbar_out[45] = io_xbar_in[io_mux_configs[275:270]];
assign io_xbar_out[46] = io_xbar_in[io_mux_configs[281:276]];
assign io_xbar_out[47] = io_xbar_in[io_mux_configs[287:282]];
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [33:0] io_configs_en,
output reg [1087:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
always @ (io_configs_en[14] or io_d_in)
begin
if (io_configs_en[14])
begin
io_configs_out[479:448] = io_d_in;
end
end
always @ (io_configs_en[15] or io_d_in)
begin
if (io_configs_en[15])
begin
io_configs_out[511:480] = io_d_in;
end
end
always @ (io_configs_en[16] or io_d_in)
begin
if (io_configs_en[16])
begin
io_configs_out[543:512] = io_d_in;
end
end
always @ (io_configs_en[17] or io_d_in)
begin
if (io_configs_en[17])
begin
io_configs_out[575:544] = io_d_in;
end
end
always @ (io_configs_en[18] or io_d_in)
begin
if (io_configs_en[18])
begin
io_configs_out[607:576] = io_d_in;
end
end
always @ (io_configs_en[19] or io_d_in)
begin
if (io_configs_en[19])
begin
io_configs_out[639:608] = io_d_in;
end
end
always @ (io_configs_en[20] or io_d_in)
begin
if (io_configs_en[20])
begin
io_configs_out[671:640] = io_d_in;
end
end
always @ (io_configs_en[21] or io_d_in)
begin
if (io_configs_en[21])
begin
io_configs_out[703:672] = io_d_in;
end
end
always @ (io_configs_en[22] or io_d_in)
begin
if (io_configs_en[22])
begin
io_configs_out[735:704] = io_d_in;
end
end
always @ (io_configs_en[23] or io_d_in)
begin
if (io_configs_en[23])
begin
io_configs_out[767:736] = io_d_in;
end
end
always @ (io_configs_en[24] or io_d_in)
begin
if (io_configs_en[24])
begin
io_configs_out[799:768] = io_d_in;
end
end
always @ (io_configs_en[25] or io_d_in)
begin
if (io_configs_en[25])
begin
io_configs_out[831:800] = io_d_in;
end
end
always @ (io_configs_en[26] or io_d_in)
begin
if (io_configs_en[26])
begin
io_configs_out[863:832] = io_d_in;
end
end
always @ (io_configs_en[27] or io_d_in)
begin
if (io_configs_en[27])
begin
io_configs_out[895:864] = io_d_in;
end
end
always @ (io_configs_en[28] or io_d_in)
begin
if (io_configs_en[28])
begin
io_configs_out[927:896] = io_d_in;
end
end
always @ (io_configs_en[29] or io_d_in)
begin
if (io_configs_en[29])
begin
io_configs_out[959:928] = io_d_in;
end
end
always @ (io_configs_en[30] or io_d_in)
begin
if (io_configs_en[30])
begin
io_configs_out[991:960] = io_d_in;
end
end
always @ (io_configs_en[31] or io_d_in)
begin
if (io_configs_en[31])
begin
io_configs_out[1023:992] = io_d_in;
end
end
always @ (io_configs_en[32] or io_d_in)
begin
if (io_configs_en[32])
begin
io_configs_out[1055:1024] = io_d_in;
end
end
always @ (io_configs_en[33] or io_d_in)
begin
if (io_configs_en[33])
begin
io_configs_out[1087:1056] = io_d_in;
end
end
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [13:0] io_configs_en,
output reg [447:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [15:0] io_configs_en,
output reg [511:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
always @ (io_configs_en[14] or io_d_in)
begin
if (io_configs_en[14])
begin
io_configs_out[479:448] = io_d_in;
end
end
always @ (io_configs_en[15] or io_d_in)
begin
if (io_configs_en[15])
begin
io_configs_out[511:480] = io_d_in;
end
end
endmodule |
module xbar(input clk, input reset,
input [42:0] io_xbar_in,
output [59:0] io_xbar_out,
input [359:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[5:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[11:6]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[17:12]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[23:18]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[29:24]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[35:30]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[41:36]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[47:42]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[53:48]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[59:54]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[65:60]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[71:66]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[77:72]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[83:78]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[89:84]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[95:90]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[101:96]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[107:102]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[113:108]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[119:114]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[125:120]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[131:126]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[137:132]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[143:138]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[149:144]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[155:150]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[161:156]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[167:162]];
assign io_xbar_out[28] = io_xbar_in[io_mux_configs[173:168]];
assign io_xbar_out[29] = io_xbar_in[io_mux_configs[179:174]];
assign io_xbar_out[30] = io_xbar_in[io_mux_configs[185:180]];
assign io_xbar_out[31] = io_xbar_in[io_mux_configs[191:186]];
assign io_xbar_out[32] = io_xbar_in[io_mux_configs[197:192]];
assign io_xbar_out[33] = io_xbar_in[io_mux_configs[203:198]];
assign io_xbar_out[34] = io_xbar_in[io_mux_configs[209:204]];
assign io_xbar_out[35] = io_xbar_in[io_mux_configs[215:210]];
assign io_xbar_out[36] = io_xbar_in[io_mux_configs[221:216]];
assign io_xbar_out[37] = io_xbar_in[io_mux_configs[227:222]];
assign io_xbar_out[38] = io_xbar_in[io_mux_configs[233:228]];
assign io_xbar_out[39] = io_xbar_in[io_mux_configs[239:234]];
assign io_xbar_out[40] = io_xbar_in[io_mux_configs[245:240]];
assign io_xbar_out[41] = io_xbar_in[io_mux_configs[251:246]];
assign io_xbar_out[42] = io_xbar_in[io_mux_configs[257:252]];
assign io_xbar_out[43] = io_xbar_in[io_mux_configs[263:258]];
assign io_xbar_out[44] = io_xbar_in[io_mux_configs[269:264]];
assign io_xbar_out[45] = io_xbar_in[io_mux_configs[275:270]];
assign io_xbar_out[46] = io_xbar_in[io_mux_configs[281:276]];
assign io_xbar_out[47] = io_xbar_in[io_mux_configs[287:282]];
assign io_xbar_out[48] = io_xbar_in[io_mux_configs[293:288]];
assign io_xbar_out[49] = io_xbar_in[io_mux_configs[299:294]];
assign io_xbar_out[50] = io_xbar_in[io_mux_configs[305:300]];
assign io_xbar_out[51] = io_xbar_in[io_mux_configs[311:306]];
assign io_xbar_out[52] = io_xbar_in[io_mux_configs[317:312]];
assign io_xbar_out[53] = io_xbar_in[io_mux_configs[323:318]];
assign io_xbar_out[54] = io_xbar_in[io_mux_configs[329:324]];
assign io_xbar_out[55] = io_xbar_in[io_mux_configs[335:330]];
assign io_xbar_out[56] = io_xbar_in[io_mux_configs[341:336]];
assign io_xbar_out[57] = io_xbar_in[io_mux_configs[347:342]];
assign io_xbar_out[58] = io_xbar_in[io_mux_configs[353:348]];
assign io_xbar_out[59] = io_xbar_in[io_mux_configs[359:354]];
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [40:0] io_configs_en,
output reg [1311:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
always @ (io_configs_en[14] or io_d_in)
begin
if (io_configs_en[14])
begin
io_configs_out[479:448] = io_d_in;
end
end
always @ (io_configs_en[15] or io_d_in)
begin
if (io_configs_en[15])
begin
io_configs_out[511:480] = io_d_in;
end
end
always @ (io_configs_en[16] or io_d_in)
begin
if (io_configs_en[16])
begin
io_configs_out[543:512] = io_d_in;
end
end
always @ (io_configs_en[17] or io_d_in)
begin
if (io_configs_en[17])
begin
io_configs_out[575:544] = io_d_in;
end
end
always @ (io_configs_en[18] or io_d_in)
begin
if (io_configs_en[18])
begin
io_configs_out[607:576] = io_d_in;
end
end
always @ (io_configs_en[19] or io_d_in)
begin
if (io_configs_en[19])
begin
io_configs_out[639:608] = io_d_in;
end
end
always @ (io_configs_en[20] or io_d_in)
begin
if (io_configs_en[20])
begin
io_configs_out[671:640] = io_d_in;
end
end
always @ (io_configs_en[21] or io_d_in)
begin
if (io_configs_en[21])
begin
io_configs_out[703:672] = io_d_in;
end
end
always @ (io_configs_en[22] or io_d_in)
begin
if (io_configs_en[22])
begin
io_configs_out[735:704] = io_d_in;
end
end
always @ (io_configs_en[23] or io_d_in)
begin
if (io_configs_en[23])
begin
io_configs_out[767:736] = io_d_in;
end
end
always @ (io_configs_en[24] or io_d_in)
begin
if (io_configs_en[24])
begin
io_configs_out[799:768] = io_d_in;
end
end
always @ (io_configs_en[25] or io_d_in)
begin
if (io_configs_en[25])
begin
io_configs_out[831:800] = io_d_in;
end
end
always @ (io_configs_en[26] or io_d_in)
begin
if (io_configs_en[26])
begin
io_configs_out[863:832] = io_d_in;
end
end
always @ (io_configs_en[27] or io_d_in)
begin
if (io_configs_en[27])
begin
io_configs_out[895:864] = io_d_in;
end
end
always @ (io_configs_en[28] or io_d_in)
begin
if (io_configs_en[28])
begin
io_configs_out[927:896] = io_d_in;
end
end
always @ (io_configs_en[29] or io_d_in)
begin
if (io_configs_en[29])
begin
io_configs_out[959:928] = io_d_in;
end
end
always @ (io_configs_en[30] or io_d_in)
begin
if (io_configs_en[30])
begin
io_configs_out[991:960] = io_d_in;
end
end
always @ (io_configs_en[31] or io_d_in)
begin
if (io_configs_en[31])
begin
io_configs_out[1023:992] = io_d_in;
end
end
always @ (io_configs_en[32] or io_d_in)
begin
if (io_configs_en[32])
begin
io_configs_out[1055:1024] = io_d_in;
end
end
always @ (io_configs_en[33] or io_d_in)
begin
if (io_configs_en[33])
begin
io_configs_out[1087:1056] = io_d_in;
end
end
always @ (io_configs_en[34] or io_d_in)
begin
if (io_configs_en[34])
begin
io_configs_out[1119:1088] = io_d_in;
end
end
always @ (io_configs_en[35] or io_d_in)
begin
if (io_configs_en[35])
begin
io_configs_out[1151:1120] = io_d_in;
end
end
always @ (io_configs_en[36] or io_d_in)
begin
if (io_configs_en[36])
begin
io_configs_out[1183:1152] = io_d_in;
end
end
always @ (io_configs_en[37] or io_d_in)
begin
if (io_configs_en[37])
begin
io_configs_out[1215:1184] = io_d_in;
end
end
always @ (io_configs_en[38] or io_d_in)
begin
if (io_configs_en[38])
begin
io_configs_out[1247:1216] = io_d_in;
end
end
always @ (io_configs_en[39] or io_d_in)
begin
if (io_configs_en[39])
begin
io_configs_out[1279:1248] = io_d_in;
end
end
always @ (io_configs_en[40] or io_d_in)
begin
if (io_configs_en[40])
begin
io_configs_out[1311:1280] = io_d_in;
end
end
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [24:0] io_configs_en,
output reg [799:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
always @ (io_configs_en[11] or io_d_in)
begin
if (io_configs_en[11])
begin
io_configs_out[383:352] = io_d_in;
end
end
always @ (io_configs_en[12] or io_d_in)
begin
if (io_configs_en[12])
begin
io_configs_out[415:384] = io_d_in;
end
end
always @ (io_configs_en[13] or io_d_in)
begin
if (io_configs_en[13])
begin
io_configs_out[447:416] = io_d_in;
end
end
always @ (io_configs_en[14] or io_d_in)
begin
if (io_configs_en[14])
begin
io_configs_out[479:448] = io_d_in;
end
end
always @ (io_configs_en[15] or io_d_in)
begin
if (io_configs_en[15])
begin
io_configs_out[511:480] = io_d_in;
end
end
always @ (io_configs_en[16] or io_d_in)
begin
if (io_configs_en[16])
begin
io_configs_out[543:512] = io_d_in;
end
end
always @ (io_configs_en[17] or io_d_in)
begin
if (io_configs_en[17])
begin
io_configs_out[575:544] = io_d_in;
end
end
always @ (io_configs_en[18] or io_d_in)
begin
if (io_configs_en[18])
begin
io_configs_out[607:576] = io_d_in;
end
end
always @ (io_configs_en[19] or io_d_in)
begin
if (io_configs_en[19])
begin
io_configs_out[639:608] = io_d_in;
end
end
always @ (io_configs_en[20] or io_d_in)
begin
if (io_configs_en[20])
begin
io_configs_out[671:640] = io_d_in;
end
end
always @ (io_configs_en[21] or io_d_in)
begin
if (io_configs_en[21])
begin
io_configs_out[703:672] = io_d_in;
end
end
always @ (io_configs_en[22] or io_d_in)
begin
if (io_configs_en[22])
begin
io_configs_out[735:704] = io_d_in;
end
end
always @ (io_configs_en[23] or io_d_in)
begin
if (io_configs_en[23])
begin
io_configs_out[767:736] = io_d_in;
end
end
always @ (io_configs_en[24] or io_d_in)
begin
if (io_configs_en[24])
begin
io_configs_out[799:768] = io_d_in;
end
end
endmodule |
module xbar(input clk, input reset,
input [14:0] io_xbar_in,
output [15:0] io_xbar_out,
input [63:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[3:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[7:4]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[11:8]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[15:12]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[19:16]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[23:20]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[27:24]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[31:28]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[35:32]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[39:36]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[43:40]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[47:44]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[51:48]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[55:52]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[59:56]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[63:60]];
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [10:0] io_configs_en,
output reg [351:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
always @ (io_configs_en[10] or io_d_in)
begin
if (io_configs_en[10])
begin
io_configs_out[351:320] = io_d_in;
end
end
endmodule |
module xbar(input clk, input reset,
input [32:0] io_xbar_in,
output [39:0] io_xbar_out,
input [239:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[5:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[11:6]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[17:12]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[23:18]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[29:24]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[35:30]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[41:36]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[47:42]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[53:48]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[59:54]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[65:60]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[71:66]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[77:72]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[83:78]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[89:84]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[95:90]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[101:96]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[107:102]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[113:108]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[119:114]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[125:120]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[131:126]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[137:132]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[143:138]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[149:144]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[155:150]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[161:156]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[167:162]];
assign io_xbar_out[28] = io_xbar_in[io_mux_configs[173:168]];
assign io_xbar_out[29] = io_xbar_in[io_mux_configs[179:174]];
assign io_xbar_out[30] = io_xbar_in[io_mux_configs[185:180]];
assign io_xbar_out[31] = io_xbar_in[io_mux_configs[191:186]];
assign io_xbar_out[32] = io_xbar_in[io_mux_configs[197:192]];
assign io_xbar_out[33] = io_xbar_in[io_mux_configs[203:198]];
assign io_xbar_out[34] = io_xbar_in[io_mux_configs[209:204]];
assign io_xbar_out[35] = io_xbar_in[io_mux_configs[215:210]];
assign io_xbar_out[36] = io_xbar_in[io_mux_configs[221:216]];
assign io_xbar_out[37] = io_xbar_in[io_mux_configs[227:222]];
assign io_xbar_out[38] = io_xbar_in[io_mux_configs[233:228]];
assign io_xbar_out[39] = io_xbar_in[io_mux_configs[239:234]];
endmodule |
module configs_latches(input clk, input reset,
input [31:0] io_d_in,
input [9:0] io_configs_en,
output reg [319:0] io_configs_out);
always @ (io_configs_en[0] or io_d_in)
begin
if (io_configs_en[0])
begin
io_configs_out[31:0] = io_d_in;
end
end
always @ (io_configs_en[1] or io_d_in)
begin
if (io_configs_en[1])
begin
io_configs_out[63:32] = io_d_in;
end
end
always @ (io_configs_en[2] or io_d_in)
begin
if (io_configs_en[2])
begin
io_configs_out[95:64] = io_d_in;
end
end
always @ (io_configs_en[3] or io_d_in)
begin
if (io_configs_en[3])
begin
io_configs_out[127:96] = io_d_in;
end
end
always @ (io_configs_en[4] or io_d_in)
begin
if (io_configs_en[4])
begin
io_configs_out[159:128] = io_d_in;
end
end
always @ (io_configs_en[5] or io_d_in)
begin
if (io_configs_en[5])
begin
io_configs_out[191:160] = io_d_in;
end
end
always @ (io_configs_en[6] or io_d_in)
begin
if (io_configs_en[6])
begin
io_configs_out[223:192] = io_d_in;
end
end
always @ (io_configs_en[7] or io_d_in)
begin
if (io_configs_en[7])
begin
io_configs_out[255:224] = io_d_in;
end
end
always @ (io_configs_en[8] or io_d_in)
begin
if (io_configs_en[8])
begin
io_configs_out[287:256] = io_d_in;
end
end
always @ (io_configs_en[9] or io_d_in)
begin
if (io_configs_en[9])
begin
io_configs_out[319:288] = io_d_in;
end
end
endmodule |
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