module
stringlengths 21
82.9k
|
|---|
module xbar(input clk, input reset,
input [17:0] io_xbar_in,
output [19:0] io_xbar_out,
input [99:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[4:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[9:5]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[14:10]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[19:15]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[24:20]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[29:25]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[34:30]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[39:35]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[44:40]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[49:45]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[54:50]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[59:55]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[64:60]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[69:65]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[74:70]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[79:75]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[84:80]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[89:85]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[94:90]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[99:95]];
endmodule |
module xbar(input clk, input reset,
input [22:0] io_xbar_in,
output [29:0] io_xbar_out,
input [149:0] io_mux_configs);
assign io_xbar_out[0] = io_xbar_in[io_mux_configs[4:0]];
assign io_xbar_out[1] = io_xbar_in[io_mux_configs[9:5]];
assign io_xbar_out[2] = io_xbar_in[io_mux_configs[14:10]];
assign io_xbar_out[3] = io_xbar_in[io_mux_configs[19:15]];
assign io_xbar_out[4] = io_xbar_in[io_mux_configs[24:20]];
assign io_xbar_out[5] = io_xbar_in[io_mux_configs[29:25]];
assign io_xbar_out[6] = io_xbar_in[io_mux_configs[34:30]];
assign io_xbar_out[7] = io_xbar_in[io_mux_configs[39:35]];
assign io_xbar_out[8] = io_xbar_in[io_mux_configs[44:40]];
assign io_xbar_out[9] = io_xbar_in[io_mux_configs[49:45]];
assign io_xbar_out[10] = io_xbar_in[io_mux_configs[54:50]];
assign io_xbar_out[11] = io_xbar_in[io_mux_configs[59:55]];
assign io_xbar_out[12] = io_xbar_in[io_mux_configs[64:60]];
assign io_xbar_out[13] = io_xbar_in[io_mux_configs[69:65]];
assign io_xbar_out[14] = io_xbar_in[io_mux_configs[74:70]];
assign io_xbar_out[15] = io_xbar_in[io_mux_configs[79:75]];
assign io_xbar_out[16] = io_xbar_in[io_mux_configs[84:80]];
assign io_xbar_out[17] = io_xbar_in[io_mux_configs[89:85]];
assign io_xbar_out[18] = io_xbar_in[io_mux_configs[94:90]];
assign io_xbar_out[19] = io_xbar_in[io_mux_configs[99:95]];
assign io_xbar_out[20] = io_xbar_in[io_mux_configs[104:100]];
assign io_xbar_out[21] = io_xbar_in[io_mux_configs[109:105]];
assign io_xbar_out[22] = io_xbar_in[io_mux_configs[114:110]];
assign io_xbar_out[23] = io_xbar_in[io_mux_configs[119:115]];
assign io_xbar_out[24] = io_xbar_in[io_mux_configs[124:120]];
assign io_xbar_out[25] = io_xbar_in[io_mux_configs[129:125]];
assign io_xbar_out[26] = io_xbar_in[io_mux_configs[134:130]];
assign io_xbar_out[27] = io_xbar_in[io_mux_configs[139:135]];
assign io_xbar_out[28] = io_xbar_in[io_mux_configs[144:140]];
assign io_xbar_out[29] = io_xbar_in[io_mux_configs[149:145]];
endmodule |
module multi_consumer
(
d_in,
d_out_1, d_out_2, d_out_4, d_out_7,
clock, rst, rdy
);
input clock;
input rst;
input [15:0] d_in;
output [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
output reg rdy;
wire [79:0]fpga_top_in;
wire [79:0] fpga_top_out;
wire [79:0] fpga_bot_in;
wire [79:0] fpga_bot_out;
wire [79:0] fpga_left_in;
wire [79:0] fpga_left_out;
wire [79:0] fpga_right_in;
wire [79:0] fpga_right_out;
reg [383:0] fpga_configs_in;
reg [266:0] fpga_configs_en;
assign d_out_2[4] = fpga_top_out[74];
assign d_out_4[6] = fpga_top_out[78];
assign d_out_4[1] = fpga_top_out[79];
assign d_out_2[0] = fpga_right_out[0];
assign d_out_7[9] = fpga_right_out[1];
assign d_out_4[0] = fpga_right_out[2];
assign d_out_7[15] = fpga_right_out[5];
assign d_out_7[2] = fpga_right_out[8];
assign d_out_2[14] = fpga_right_out[9];
assign d_out_4[14] = fpga_right_out[10];
assign d_out_1[0] = fpga_right_out[11];
assign d_out_7[1] = fpga_right_out[12];
assign d_out_1[14] = fpga_right_out[13];
assign d_out_7[0] = fpga_right_out[14];
assign d_out_1[2] = fpga_right_out[15];
assign d_out_4[3] = fpga_right_out[16];
assign d_out_1[4] = fpga_right_out[17];
assign d_out_2[2] = fpga_right_out[18];
assign d_out_4[2] = fpga_right_out[20];
assign d_out_4[4] = fpga_right_out[21];
assign d_out_2[3] = fpga_right_out[23];
assign d_out_7[10] = fpga_right_out[24];
assign d_out_7[14] = fpga_right_out[30];
assign d_out_7[13] = fpga_right_out[31];
assign d_out_1[12] = fpga_right_out[32];
assign d_out_1[13] = fpga_right_out[34];
assign d_out_4[13] = fpga_right_out[36];
assign d_out_2[13] = fpga_right_out[38];
assign d_out_4[12] = fpga_right_out[39];
assign d_out_2[15] = fpga_right_out[42];
assign d_out_1[1] = fpga_right_out[43];
assign d_out_1[15] = fpga_right_out[44];
assign d_out_2[12] = fpga_right_out[45];
assign d_out_1[11] = fpga_right_out[46];
assign d_out_2[11] = fpga_right_out[47];
assign d_out_2[8] = fpga_right_out[48];
assign d_out_7[12] = fpga_right_out[49];
assign d_out_4[11] = fpga_right_out[51];
assign d_out_2[1] = fpga_right_out[52];
assign d_out_7[11] = fpga_right_out[53];
assign d_out_1[7] = fpga_right_out[54];
assign d_out_4[10] = fpga_right_out[55];
assign d_out_2[10] = fpga_right_out[56];
assign d_out_1[9] = fpga_right_out[57];
assign d_out_4[9] = fpga_right_out[59];
assign d_out_2[9] = fpga_right_out[60];
assign d_out_1[8] = fpga_right_out[61];
assign d_out_4[8] = fpga_right_out[62];
assign d_out_1[3] = fpga_right_out[64];
assign d_out_1[6] = fpga_right_out[65];
assign d_out_7[4] = fpga_right_out[66];
assign d_out_2[5] = fpga_right_out[67];
assign d_out_1[5] = fpga_right_out[68];
assign d_out_4[15] = fpga_right_out[69];
assign d_out_7[3] = fpga_right_out[70];
assign d_out_4[5] = fpga_right_out[71];
assign d_out_7[6] = fpga_right_out[72];
assign d_out_1[10] = fpga_right_out[73];
assign d_out_7[5] = fpga_right_out[74];
assign d_out_7[7] = fpga_right_out[75];
assign d_out_7[8] = fpga_right_out[76];
assign d_out_2[7] = fpga_right_out[77];
assign d_out_2[6] = fpga_right_out[78];
assign d_out_4[7] = fpga_right_out[79];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_top_in[40] = 1'b0;
assign fpga_top_in[41] = 1'b0;
assign fpga_top_in[42] = 1'b0;
assign fpga_top_in[43] = 1'b0;
assign fpga_top_in[44] = 1'b0;
assign fpga_top_in[45] = 1'b0;
assign fpga_top_in[46] = 1'b0;
assign fpga_top_in[47] = 1'b0;
assign fpga_top_in[48] = 1'b0;
assign fpga_top_in[49] = 1'b0;
assign fpga_top_in[50] = 1'b0;
assign fpga_top_in[51] = 1'b0;
assign fpga_top_in[52] = 1'b0;
assign fpga_top_in[53] = 1'b0;
assign fpga_top_in[54] = 1'b0;
assign fpga_top_in[55] = 1'b0;
assign fpga_top_in[56] = 1'b0;
assign fpga_top_in[57] = 1'b0;
assign fpga_top_in[58] = 1'b0;
assign fpga_top_in[59] = 1'b0;
assign fpga_top_in[60] = 1'b0;
assign fpga_top_in[61] = 1'b0;
assign fpga_top_in[62] = 1'b0;
assign fpga_top_in[63] = 1'b0;
assign fpga_top_in[64] = 1'b0;
assign fpga_top_in[65] = 1'b0;
assign fpga_top_in[66] = 1'b0;
assign fpga_top_in[67] = 1'b0;
assign fpga_top_in[68] = 1'b0;
assign fpga_top_in[69] = 1'b0;
assign fpga_top_in[70] = 1'b0;
assign fpga_top_in[71] = 1'b0;
assign fpga_top_in[72] = 1'b0;
assign fpga_top_in[73] = 1'b0;
assign fpga_top_in[74] = 1'b0;
assign fpga_top_in[75] = 1'b0;
assign fpga_top_in[76] = 1'b0;
assign fpga_top_in[77] = 1'b0;
assign fpga_top_in[78] = 1'b0;
assign fpga_top_in[79] = 1'b0;
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_bot_in[40] = 1'b0;
assign fpga_bot_in[41] = 1'b0;
assign fpga_bot_in[42] = 1'b0;
assign fpga_bot_in[43] = 1'b0;
assign fpga_bot_in[44] = 1'b0;
assign fpga_bot_in[45] = 1'b0;
assign fpga_bot_in[46] = 1'b0;
assign fpga_bot_in[47] = 1'b0;
assign fpga_bot_in[48] = 1'b0;
assign fpga_bot_in[49] = 1'b0;
assign fpga_bot_in[50] = 1'b0;
assign fpga_bot_in[51] = 1'b0;
assign fpga_bot_in[52] = 1'b0;
assign fpga_bot_in[53] = 1'b0;
assign fpga_bot_in[54] = 1'b0;
assign fpga_bot_in[55] = 1'b0;
assign fpga_bot_in[56] = 1'b0;
assign fpga_bot_in[57] = 1'b0;
assign fpga_bot_in[58] = 1'b0;
assign fpga_bot_in[59] = 1'b0;
assign fpga_bot_in[60] = 1'b0;
assign fpga_bot_in[61] = 1'b0;
assign fpga_bot_in[62] = 1'b0;
assign fpga_bot_in[63] = 1'b0;
assign fpga_bot_in[64] = 1'b0;
assign fpga_bot_in[65] = 1'b0;
assign fpga_bot_in[66] = 1'b0;
assign fpga_bot_in[67] = 1'b0;
assign fpga_bot_in[68] = 1'b0;
assign fpga_bot_in[69] = 1'b0;
assign fpga_bot_in[70] = 1'b0;
assign fpga_bot_in[71] = 1'b0;
assign fpga_bot_in[72] = 1'b0;
assign fpga_bot_in[73] = 1'b0;
assign fpga_bot_in[74] = 1'b0;
assign fpga_bot_in[75] = 1'b0;
assign fpga_bot_in[76] = 1'b0;
assign fpga_bot_in[77] = 1'b0;
assign fpga_bot_in[78] = 1'b0;
assign fpga_bot_in[79] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_left_in[40] = 1'b0;
assign fpga_left_in[41] = 1'b0;
assign fpga_left_in[42] = 1'b0;
assign fpga_left_in[43] = 1'b0;
assign fpga_left_in[44] = 1'b0;
assign fpga_left_in[45] = 1'b0;
assign fpga_left_in[46] = 1'b0;
assign fpga_left_in[47] = 1'b0;
assign fpga_left_in[48] = 1'b0;
assign fpga_left_in[49] = 1'b0;
assign fpga_left_in[50] = 1'b0;
assign fpga_left_in[51] = 1'b0;
assign fpga_left_in[52] = 1'b0;
assign fpga_left_in[53] = 1'b0;
assign fpga_left_in[54] = 1'b0;
assign fpga_left_in[55] = 1'b0;
assign fpga_left_in[56] = 1'b0;
assign fpga_left_in[57] = 1'b0;
assign fpga_left_in[58] = 1'b0;
assign fpga_left_in[59] = 1'b0;
assign fpga_left_in[60] = 1'b0;
assign fpga_left_in[61] = 1'b0;
assign fpga_left_in[62] = 1'b0;
assign fpga_left_in[63] = 1'b0;
assign fpga_left_in[64] = 1'b0;
assign fpga_left_in[65] = 1'b0;
assign fpga_left_in[66] = 1'b0;
assign fpga_left_in[67] = 1'b0;
assign fpga_left_in[68] = 1'b0;
assign fpga_left_in[69] = 1'b0;
assign fpga_left_in[70] = 1'b0;
assign fpga_left_in[71] = 1'b0;
assign fpga_left_in[72] = 1'b0;
assign fpga_left_in[73] = 1'b0;
assign fpga_left_in[74] = 1'b0;
assign fpga_left_in[75] = 1'b0;
assign fpga_left_in[76] = 1'b0;
assign fpga_left_in[77] = 1'b0;
assign fpga_left_in[78] = 1'b0;
assign fpga_left_in[79] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = d_in[0];
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = d_in[14];
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = d_in[13];
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = d_in[12];
assign fpga_right_in[26] = d_in[9];
assign fpga_right_in[27] = d_in[1];
assign fpga_right_in[28] = d_in[11];
assign fpga_right_in[29] = d_in[15];
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = d_in[4];
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = d_in[6];
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = d_in[8];
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
assign fpga_right_in[40] = d_in[2];
assign fpga_right_in[41] = d_in[3];
assign fpga_right_in[42] = 1'b0;
assign fpga_right_in[43] = 1'b0;
assign fpga_right_in[44] = 1'b0;
assign fpga_right_in[45] = 1'b0;
assign fpga_right_in[46] = 1'b0;
assign fpga_right_in[47] = 1'b0;
assign fpga_right_in[48] = 1'b0;
assign fpga_right_in[49] = 1'b0;
assign fpga_right_in[50] = d_in[7];
assign fpga_right_in[51] = 1'b0;
assign fpga_right_in[52] = 1'b0;
assign fpga_right_in[53] = 1'b0;
assign fpga_right_in[54] = 1'b0;
assign fpga_right_in[55] = 1'b0;
assign fpga_right_in[56] = 1'b0;
assign fpga_right_in[57] = 1'b0;
assign fpga_right_in[58] = d_in[10];
assign fpga_right_in[59] = 1'b0;
assign fpga_right_in[60] = 1'b0;
assign fpga_right_in[61] = 1'b0;
assign fpga_right_in[62] = 1'b0;
assign fpga_right_in[63] = d_in[5];
assign fpga_right_in[64] = 1'b0;
assign fpga_right_in[65] = 1'b0;
assign fpga_right_in[66] = 1'b0;
assign fpga_right_in[67] = 1'b0;
assign fpga_right_in[68] = 1'b0;
assign fpga_right_in[69] = 1'b0;
assign fpga_right_in[70] = 1'b0;
assign fpga_right_in[71] = 1'b0;
assign fpga_right_in[72] = 1'b0;
assign fpga_right_in[73] = 1'b0;
assign fpga_right_in[74] = 1'b0;
assign fpga_right_in[75] = 1'b0;
assign fpga_right_in[76] = 1'b0;
assign fpga_right_in[77] = 1'b0;
assign fpga_right_in[78] = 1'b0;
assign fpga_right_in[79] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("multi_consumer.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module multi_consumer
(
d_in,
d_out_1, d_out_2, d_out_4, d_out_7,
clock, rst, rdy
);
input clock;
input rst;
input [15:0] d_in;
output [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
output reg rdy;
wire [39:0]fpga_top_in;
wire [39:0] fpga_top_out;
wire [39:0] fpga_bot_in;
wire [39:0] fpga_bot_out;
wire [39:0] fpga_left_in;
wire [39:0] fpga_left_out;
wire [39:0] fpga_right_in;
wire [39:0] fpga_right_out;
reg [223:0] fpga_configs_in;
reg [244:0] fpga_configs_en;
assign d_out_2[7] = fpga_top_out[16];
assign d_out_2[10] = fpga_top_out[17];
assign d_out_7[10] = fpga_top_out[18];
assign d_out_2[8] = fpga_top_out[19];
assign d_out_4[12] = fpga_top_out[20];
assign d_out_4[8] = fpga_top_out[21];
assign d_out_1[7] = fpga_top_out[22];
assign d_out_2[9] = fpga_top_out[23];
assign d_out_7[5] = fpga_top_out[24];
assign d_out_4[6] = fpga_top_out[25];
assign d_out_2[6] = fpga_top_out[26];
assign d_out_2[5] = fpga_top_out[29];
assign d_out_7[4] = fpga_top_out[30];
assign d_out_4[5] = fpga_top_out[31];
assign d_out_4[7] = fpga_top_out[32];
assign d_out_4[10] = fpga_top_out[34];
assign d_out_1[8] = fpga_top_out[36];
assign d_out_4[9] = fpga_top_out[37];
assign d_out_2[12] = fpga_top_out[38];
assign d_out_1[4] = fpga_bot_out[24];
assign d_out_2[4] = fpga_bot_out[25];
assign d_out_4[4] = fpga_bot_out[26];
assign d_out_4[0] = fpga_bot_out[27];
assign d_out_4[2] = fpga_bot_out[28];
assign d_out_4[3] = fpga_bot_out[29];
assign d_out_1[0] = fpga_bot_out[30];
assign d_out_7[0] = fpga_bot_out[31];
assign d_out_7[1] = fpga_bot_out[32];
assign d_out_1[3] = fpga_bot_out[33];
assign d_out_1[2] = fpga_bot_out[34];
assign d_out_2[0] = fpga_bot_out[36];
assign d_out_2[3] = fpga_bot_out[37];
assign d_out_4[1] = fpga_bot_out[38];
assign d_out_2[1] = fpga_bot_out[39];
assign d_out_1[6] = fpga_left_out[26];
assign d_out_7[2] = fpga_right_out[0];
assign d_out_7[3] = fpga_right_out[1];
assign d_out_2[2] = fpga_right_out[3];
assign d_out_1[1] = fpga_right_out[5];
assign d_out_1[14] = fpga_right_out[6];
assign d_out_4[14] = fpga_right_out[9];
assign d_out_1[13] = fpga_right_out[10];
assign d_out_7[9] = fpga_right_out[12];
assign d_out_1[5] = fpga_right_out[15];
assign d_out_2[13] = fpga_right_out[16];
assign d_out_2[14] = fpga_right_out[19];
assign d_out_4[15] = fpga_right_out[20];
assign d_out_1[15] = fpga_right_out[21];
assign d_out_4[13] = fpga_right_out[22];
assign d_out_2[15] = fpga_right_out[23];
assign d_out_7[12] = fpga_right_out[24];
assign d_out_7[8] = fpga_right_out[25];
assign d_out_7[6] = fpga_right_out[26];
assign d_out_7[7] = fpga_right_out[27];
assign d_out_7[15] = fpga_right_out[28];
assign d_out_7[11] = fpga_right_out[29];
assign d_out_7[13] = fpga_right_out[30];
assign d_out_7[14] = fpga_right_out[31];
assign d_out_4[11] = fpga_right_out[32];
assign d_out_1[11] = fpga_right_out[33];
assign d_out_1[10] = fpga_right_out[34];
assign d_out_2[11] = fpga_right_out[37];
assign d_out_1[9] = fpga_right_out[38];
assign d_out_1[12] = fpga_right_out[39];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = d_in[12];
assign fpga_top_in[28] = d_in[6];
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = d_in[11];
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = d_in[10];
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = d_in[14];
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = d_in[1];
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = d_in[13];
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = d_in[0];
assign fpga_right_in[8] = d_in[4];
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = d_in[3];
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = d_in[15];
assign fpga_right_in[14] = d_in[2];
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = d_in[8];
assign fpga_right_in[18] = d_in[9];
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = 1'b0;
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = d_in[7];
assign fpga_right_in[36] = d_in[5];
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("multi_consumer.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module simple_comp
(
a_in, b_in, c_in,
d_out,
clock, rst, rdy
);
input [15:0] a_in;
input [15:0] b_in;
input [15:0] c_in;
input clock;
input rst;
output [15:0] d_out;
output reg rdy;
wire [39:0]fpga_top_in;
wire [39:0] fpga_top_out;
wire [39:0] fpga_bot_in;
wire [39:0] fpga_bot_out;
wire [39:0] fpga_left_in;
wire [39:0] fpga_left_out;
wire [39:0] fpga_right_in;
wire [39:0] fpga_right_out;
reg [223:0] fpga_configs_in;
reg [244:0] fpga_configs_en;
assign d_out[14] = fpga_top_out[13];
assign d_out[15] = fpga_top_out[15];
assign d_out[4] = fpga_bot_out[9];
assign d_out[3] = fpga_bot_out[11];
assign d_out[7] = fpga_bot_out[14];
assign d_out[6] = fpga_bot_out[15];
assign d_out[9] = fpga_left_out[16];
assign d_out[8] = fpga_left_out[19];
assign d_out[5] = fpga_left_out[21];
assign d_out[1] = fpga_left_out[24];
assign d_out[13] = fpga_left_out[25];
assign d_out[0] = fpga_left_out[28];
assign d_out[12] = fpga_left_out[29];
assign d_out[2] = fpga_left_out[31];
assign d_out[10] = fpga_left_out[33];
assign d_out[11] = fpga_right_out[16];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = c_in[11];
assign fpga_top_in[2] = c_in[10];
assign fpga_top_in[3] = c_in[13];
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = c_in[12];
assign fpga_top_in[6] = c_in[9];
assign fpga_top_in[7] = c_in[8];
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = c_in[14];
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_bot_in[0] = c_in[0];
assign fpga_bot_in[1] = c_in[1];
assign fpga_bot_in[2] = c_in[2];
assign fpga_bot_in[3] = c_in[5];
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = a_in[15];
assign fpga_bot_in[8] = a_in[3];
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = a_in[0];
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = b_in[5];
assign fpga_bot_in[13] = b_in[6];
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = c_in[6];
assign fpga_bot_in[18] = c_in[4];
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = c_in[3];
assign fpga_bot_in[22] = c_in[7];
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_left_in[0] = b_in[14];
assign fpga_left_in[1] = b_in[1];
assign fpga_left_in[2] = b_in[8];
assign fpga_left_in[3] = a_in[1];
assign fpga_left_in[4] = b_in[0];
assign fpga_left_in[5] = b_in[11];
assign fpga_left_in[6] = b_in[2];
assign fpga_left_in[7] = a_in[11];
assign fpga_left_in[8] = b_in[4];
assign fpga_left_in[9] = a_in[4];
assign fpga_left_in[10] = a_in[7];
assign fpga_left_in[11] = b_in[15];
assign fpga_left_in[12] = a_in[5];
assign fpga_left_in[13] = a_in[2];
assign fpga_left_in[14] = a_in[14];
assign fpga_left_in[15] = a_in[8];
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = b_in[7];
assign fpga_left_in[18] = a_in[9];
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = a_in[6];
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = b_in[3];
assign fpga_left_in[23] = b_in[9];
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = a_in[10];
assign fpga_left_in[27] = b_in[10];
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = rst;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = b_in[12];
assign fpga_left_in[36] = a_in[13];
assign fpga_left_in[37] = b_in[13];
assign fpga_left_in[38] = a_in[12];
assign fpga_left_in[39] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = c_in[15];
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = 1'b0;
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("simple_comp.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module counter
(
d_out, clock, rst, d_en, rdy
);
input clock;
input rst;
input d_en;
output [11:0] d_out;
output reg rdy;
wire [39:0]fpga_top_in;
wire [39:0] fpga_top_out;
wire [39:0] fpga_bot_in;
wire [39:0] fpga_bot_out;
wire [39:0] fpga_left_in;
wire [39:0] fpga_left_out;
wire [39:0] fpga_right_in;
wire [39:0] fpga_right_out;
reg [223:0] fpga_configs_in;
reg [244:0] fpga_configs_en;
assign d_out[7] = fpga_bot_out[0];
assign d_out[8] = fpga_bot_out[1];
assign d_out[9] = fpga_bot_out[3];
assign d_out[1] = fpga_bot_out[12];
assign d_out[3] = fpga_left_out[0];
assign d_out[4] = fpga_left_out[1];
assign d_out[6] = fpga_left_out[2];
assign d_out[5] = fpga_left_out[3];
assign d_out[0] = fpga_left_out[4];
assign d_out[2] = fpga_left_out[5];
assign d_out[10] = fpga_left_out[6];
assign d_out[11] = fpga_left_out[7];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = d_en;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = rst;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = 1'b0;
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("counter.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module simple_comp
(
a_in, b_in, c_in,
d_out,
clock, rst, rdy
);
input [15:0] a_in;
input [15:0] b_in;
input [15:0] c_in;
input clock;
input rst;
output [15:0] d_out;
output reg rdy;
wire [39:0]fpga_top_in;
wire [39:0] fpga_top_out;
wire [39:0] fpga_bot_in;
wire [39:0] fpga_bot_out;
wire [39:0] fpga_left_in;
wire [39:0] fpga_left_out;
wire [39:0] fpga_right_in;
wire [39:0] fpga_right_out;
reg [223:0] fpga_configs_in;
reg [42:0] fpga_configs_en;
assign d_out[2] = fpga_top_out[8];
assign d_out[3] = fpga_top_out[11];
assign d_out[4] = fpga_top_out[22];
assign d_out[5] = fpga_top_out[33];
assign d_out[6] = fpga_top_out[39];
assign d_out[14] = fpga_bot_out[3];
assign d_out[15] = fpga_bot_out[7];
assign d_out[12] = fpga_bot_out[10];
assign d_out[9] = fpga_bot_out[24];
assign d_out[8] = fpga_bot_out[25];
assign d_out[10] = fpga_bot_out[33];
assign d_out[13] = fpga_left_out[10];
assign d_out[1] = fpga_left_out[22];
assign d_out[11] = fpga_right_out[8];
assign d_out[0] = fpga_right_out[9];
assign d_out[7] = fpga_right_out[22];
assign fpga_top_in[0] = a_in[0];
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = a_in[2];
assign fpga_top_in[4] = b_in[0];
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = b_in[1];
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = c_in[2];
assign fpga_top_in[13] = c_in[1];
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = c_in[0];
assign fpga_top_in[16] = a_in[3];
assign fpga_top_in[17] = a_in[4];
assign fpga_top_in[18] = a_in[1];
assign fpga_top_in[19] = b_in[2];
assign fpga_top_in[20] = b_in[3];
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = b_in[4];
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = c_in[4];
assign fpga_top_in[26] = c_in[7];
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = c_in[5];
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = c_in[3];
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_bot_in[0] = c_in[15];
assign fpga_bot_in[1] = c_in[13];
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = c_in[14];
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = a_in[12];
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = c_in[12];
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = c_in[10];
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = c_in[11];
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = c_in[8];
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = a_in[11];
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = b_in[8];
assign fpga_bot_in[29] = b_in[11];
assign fpga_bot_in[30] = a_in[8];
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = c_in[9];
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = a_in[13];
assign fpga_left_in[9] = b_in[13];
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = b_in[12];
assign fpga_left_in[16] = a_in[14];
assign fpga_left_in[17] = a_in[15];
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = b_in[14];
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = b_in[15];
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = a_in[9];
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = b_in[9];
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = a_in[10];
assign fpga_right_in[12] = rst;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = c_in[6];
assign fpga_right_in[15] = b_in[10];
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = b_in[5];
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = a_in[5];
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = a_in[7];
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = b_in[7];
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = a_in[6];
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = b_in[6];
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("simple_comp.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module lut4(input clk, input reset,
input [3:0] io_lut_in,
output io_lut_out,
input [15:0] io_lut_configs,
input io_mux_configs,
input io_ff_en);
wire T0;
wire T1;
wire T2;
wire[1:0] T3;
wire lut4_o;
wire[3:0] T4;
reg[0:0] ff1;
wire T5;
assign io_lut_out = T0;
assign T0 = T3[T1];
assign T1 = T2;
assign T2 = io_mux_configs;
assign T3 = {ff1, lut4_o};
assign lut4_o = io_lut_configs[T4];
assign T4 = io_lut_in;
assign T5 = 1'h1/* 1*/ ? lut4_o : ff1;
always @(posedge clk) begin
if(reset) begin
ff1 <= 1'b0/* 0*/;
end else if(io_ff_en) begin
ff1 <= T5;
end
end
endmodule |
module clb(input clk, input reset,
input [15:0] io_clb_in,
output[3:0] io_clb_out,
input [63:0] io_lut_configs,
input [3:0] io_mux_configs,
input io_ff_en);
wire T0;
wire[15:0] T1;
wire[3:0] T2;
wire T3;
wire[15:0] T4;
wire[3:0] T5;
wire T6;
wire[15:0] T7;
wire[3:0] T8;
wire T9;
wire[15:0] T10;
wire[3:0] T11;
wire[3:0] T12;
wire[3:0] T13;
wire[2:0] T14;
wire[2:0] T15;
wire[1:0] T16;
wire[1:0] T17;
wire T18;
wire T19;
wire lut4_io_lut_out;
wire T20;
wire T21;
wire lut4_1_io_lut_out;
wire T22;
wire T23;
wire lut4_2_io_lut_out;
wire T24;
wire T25;
wire lut4_3_io_lut_out;
assign T0 = io_mux_configs[2'h3/* 3*/:2'h3/* 3*/];
assign T1 = io_lut_configs[6'h3f/* 63*/:6'h30/* 48*/];
assign T2 = io_clb_in[4'hf/* 15*/:4'hc/* 12*/];
assign T3 = io_mux_configs[2'h2/* 2*/:2'h2/* 2*/];
assign T4 = io_lut_configs[6'h2f/* 47*/:6'h20/* 32*/];
assign T5 = io_clb_in[4'hb/* 11*/:4'h8/* 8*/];
assign T6 = io_mux_configs[1'h1/* 1*/:1'h1/* 1*/];
assign T7 = io_lut_configs[5'h1f/* 31*/:5'h10/* 16*/];
assign T8 = io_clb_in[3'h7/* 7*/:3'h4/* 4*/];
assign T9 = io_mux_configs[1'h0/* 0*/:1'h0/* 0*/];
assign T10 = io_lut_configs[4'hf/* 15*/:1'h0/* 0*/];
assign T11 = io_clb_in[2'h3/* 3*/:1'h0/* 0*/];
assign io_clb_out = T12;
assign T12 = T13;
assign T13 = {T24, T14};
assign T14 = T15;
assign T15 = {T22, T16};
assign T16 = T17;
assign T17 = {T20, T18};
assign T18 = T19;
assign T19 = lut4_io_lut_out;
assign T20 = T21;
assign T21 = lut4_1_io_lut_out;
assign T22 = T23;
assign T23 = lut4_2_io_lut_out;
assign T24 = T25;
assign T25 = lut4_3_io_lut_out;
lut4 lut4(.clk(clk), .reset(reset),
.io_lut_in( T11 ),
.io_lut_out( lut4_io_lut_out ),
.io_lut_configs( T10 ),
.io_mux_configs( T9 ),
.io_ff_en( io_ff_en ));
lut4 lut4_1(.clk(clk), .reset(reset),
.io_lut_in( T8 ),
.io_lut_out( lut4_1_io_lut_out ),
.io_lut_configs( T7 ),
.io_mux_configs( T6 ),
.io_ff_en( io_ff_en ));
lut4 lut4_2(.clk(clk), .reset(reset),
.io_lut_in( T5 ),
.io_lut_out( lut4_2_io_lut_out ),
.io_lut_configs( T4 ),
.io_mux_configs( T3 ),
.io_ff_en( io_ff_en ));
lut4 lut4_3(.clk(clk), .reset(reset),
.io_lut_in( T2 ),
.io_lut_out( lut4_3_io_lut_out ),
.io_lut_configs( T1 ),
.io_mux_configs( T0 ),
.io_ff_en( io_ff_en ));
endmodule |
module sbcb(
input [43:0] io_ipin_in,
input [21:0] io_ipin_config,
input [195:0] io_chanxy_in,
input [79:0] io_chanxy_config,
output[10:0] io_ipin_out,
output[19:0] io_chanxy_out);
wire[19:0] T0;
wire[19:0] T1;
wire[18:0] T2;
wire[18:0] T3;
wire[17:0] T4;
wire[17:0] T5;
wire[16:0] T6;
wire[16:0] T7;
wire[15:0] T8;
wire[15:0] T9;
wire[14:0] T10;
wire[14:0] T11;
wire[13:0] T12;
wire[13:0] T13;
wire[12:0] T14;
wire[12:0] T15;
wire[11:0] T16;
wire[11:0] T17;
wire[10:0] T18;
wire[10:0] T19;
wire[9:0] T20;
wire[9:0] T21;
wire[8:0] T22;
wire[8:0] T23;
wire[7:0] T24;
wire[7:0] T25;
wire[6:0] T26;
wire[6:0] T27;
wire[5:0] T28;
wire[5:0] T29;
wire[4:0] T30;
wire[4:0] T31;
wire[3:0] T32;
wire[3:0] T33;
wire[2:0] T34;
wire[2:0] T35;
wire[1:0] T36;
wire[1:0] T37;
wire T38;
wire T39;
wire T40;
wire[3:0] T41;
wire[3:0] T42;
wire[3:0] T43;
wire[9:0] T44;
wire[9:0] T45;
wire T46;
wire T47;
wire T48;
wire[3:0] T49;
wire[3:0] T50;
wire[3:0] T51;
wire[9:0] T52;
wire[9:0] T53;
wire T54;
wire T55;
wire T56;
wire[3:0] T57;
wire[3:0] T58;
wire[3:0] T59;
wire[9:0] T60;
wire[9:0] T61;
wire T62;
wire T63;
wire T64;
wire[3:0] T65;
wire[3:0] T66;
wire[3:0] T67;
wire[9:0] T68;
wire[9:0] T69;
wire T70;
wire T71;
wire T72;
wire[3:0] T73;
wire[3:0] T74;
wire[3:0] T75;
wire[8:0] T76;
wire[8:0] T77;
wire T78;
wire T79;
wire T80;
wire[3:0] T81;
wire[3:0] T82;
wire[3:0] T83;
wire[9:0] T84;
wire[9:0] T85;
wire T86;
wire T87;
wire T88;
wire[3:0] T89;
wire[3:0] T90;
wire[3:0] T91;
wire[9:0] T92;
wire[9:0] T93;
wire T94;
wire T95;
wire T96;
wire[3:0] T97;
wire[3:0] T98;
wire[3:0] T99;
wire[9:0] T100;
wire[9:0] T101;
wire T102;
wire T103;
wire T104;
wire[3:0] T105;
wire[3:0] T106;
wire[3:0] T107;
wire[9:0] T108;
wire[9:0] T109;
wire T110;
wire T111;
wire T112;
wire[3:0] T113;
wire[3:0] T114;
wire[3:0] T115;
wire[8:0] T116;
wire[8:0] T117;
wire T118;
wire T119;
wire T120;
wire[3:0] T121;
wire[3:0] T122;
wire[3:0] T123;
wire[9:0] T124;
wire[9:0] T125;
wire T126;
wire T127;
wire T128;
wire[3:0] T129;
wire[3:0] T130;
wire[3:0] T131;
wire[9:0] T132;
wire[9:0] T133;
wire T134;
wire T135;
wire T136;
wire[3:0] T137;
wire[3:0] T138;
wire[3:0] T139;
wire[9:0] T140;
wire[9:0] T141;
wire T142;
wire T143;
wire T144;
wire[3:0] T145;
wire[3:0] T146;
wire[3:0] T147;
wire[9:0] T148;
wire[9:0] T149;
wire T150;
wire T151;
wire T152;
wire[3:0] T153;
wire[3:0] T154;
wire[3:0] T155;
wire[8:0] T156;
wire[8:0] T157;
wire T158;
wire T159;
wire T160;
wire[3:0] T161;
wire[3:0] T162;
wire[3:0] T163;
wire[9:0] T164;
wire[9:0] T165;
wire T166;
wire T167;
wire T168;
wire[3:0] T169;
wire[3:0] T170;
wire[3:0] T171;
wire[9:0] T172;
wire[9:0] T173;
wire T174;
wire T175;
wire T176;
wire[3:0] T177;
wire[3:0] T178;
wire[3:0] T179;
wire[9:0] T180;
wire[9:0] T181;
wire T182;
wire T183;
wire T184;
wire[3:0] T185;
wire[3:0] T186;
wire[3:0] T187;
wire[9:0] T188;
wire[9:0] T189;
wire T190;
wire T191;
wire T192;
wire[3:0] T193;
wire[3:0] T194;
wire[3:0] T195;
wire[8:0] T196;
wire[8:0] T197;
wire[10:0] T198;
wire[10:0] T199;
wire[9:0] T200;
wire[9:0] T201;
wire[8:0] T202;
wire[8:0] T203;
wire[7:0] T204;
wire[7:0] T205;
wire[6:0] T206;
wire[6:0] T207;
wire[5:0] T208;
wire[5:0] T209;
wire[4:0] T210;
wire[4:0] T211;
wire[3:0] T212;
wire[3:0] T213;
wire[2:0] T214;
wire[2:0] T215;
wire[1:0] T216;
wire[1:0] T217;
wire T218;
wire T219;
wire T220;
wire[1:0] T221;
wire[1:0] T222;
wire[1:0] T223;
wire[3:0] T224;
wire[3:0] T225;
wire T226;
wire T227;
wire T228;
wire[1:0] T229;
wire[1:0] T230;
wire[1:0] T231;
wire[3:0] T232;
wire[3:0] T233;
wire T234;
wire T235;
wire T236;
wire[1:0] T237;
wire[1:0] T238;
wire[1:0] T239;
wire[3:0] T240;
wire[3:0] T241;
wire T242;
wire T243;
wire T244;
wire[1:0] T245;
wire[1:0] T246;
wire[1:0] T247;
wire[3:0] T248;
wire[3:0] T249;
wire T250;
wire T251;
wire T252;
wire[1:0] T253;
wire[1:0] T254;
wire[1:0] T255;
wire[3:0] T256;
wire[3:0] T257;
wire T258;
wire T259;
wire T260;
wire[1:0] T261;
wire[1:0] T262;
wire[1:0] T263;
wire[3:0] T264;
wire[3:0] T265;
wire T266;
wire T267;
wire T268;
wire[1:0] T269;
wire[1:0] T270;
wire[1:0] T271;
wire[3:0] T272;
wire[3:0] T273;
wire T274;
wire T275;
wire T276;
wire[1:0] T277;
wire[1:0] T278;
wire[1:0] T279;
wire[3:0] T280;
wire[3:0] T281;
wire T282;
wire T283;
wire T284;
wire[1:0] T285;
wire[1:0] T286;
wire[1:0] T287;
wire[3:0] T288;
wire[3:0] T289;
wire T290;
wire T291;
wire T292;
wire[1:0] T293;
wire[1:0] T294;
wire[1:0] T295;
wire[3:0] T296;
wire[3:0] T297;
wire T298;
wire T299;
wire T300;
wire[1:0] T301;
wire[1:0] T302;
wire[1:0] T303;
wire[3:0] T304;
wire[3:0] T305;
assign io_chanxy_out = T0;
assign T0 = T1;
assign T1 = {T190, T2};
assign T2 = T3;
assign T3 = {T182, T4};
assign T4 = T5;
assign T5 = {T174, T6};
assign T6 = T7;
assign T7 = {T166, T8};
assign T8 = T9;
assign T9 = {T158, T10};
assign T10 = T11;
assign T11 = {T150, T12};
assign T12 = T13;
assign T13 = {T142, T14};
assign T14 = T15;
assign T15 = {T134, T16};
assign T16 = T17;
assign T17 = {T126, T18};
assign T18 = T19;
assign T19 = {T118, T20};
assign T20 = T21;
assign T21 = {T110, T22};
assign T22 = T23;
assign T23 = {T102, T24};
assign T24 = T25;
assign T25 = {T94, T26};
assign T26 = T27;
assign T27 = {T86, T28};
assign T28 = T29;
assign T29 = {T78, T30};
assign T30 = T31;
assign T31 = {T70, T32};
assign T32 = T33;
assign T33 = {T62, T34};
assign T34 = T35;
assign T35 = {T54, T36};
assign T36 = T37;
assign T37 = {T46, T38};
assign T38 = T39;
assign T39 = T40;
assign T40 = T44[T41];
assign T41 = T42;
assign T42 = T43;
assign T43 = io_chanxy_config[2'h3/* 3*/:1'h0/* 0*/];
assign T44 = T45;
assign T45 = io_chanxy_in[4'h9/* 9*/:1'h0/* 0*/];
assign T46 = T47;
assign T47 = T48;
assign T48 = T52[T49];
assign T49 = T50;
assign T50 = T51;
assign T51 = io_chanxy_config[3'h7/* 7*/:3'h4/* 4*/];
assign T52 = T53;
assign T53 = io_chanxy_in[5'h13/* 19*/:4'ha/* 10*/];
assign T54 = T55;
assign T55 = T56;
assign T56 = T60[T57];
assign T57 = T58;
assign T58 = T59;
assign T59 = io_chanxy_config[4'hb/* 11*/:4'h8/* 8*/];
assign T60 = T61;
assign T61 = io_chanxy_in[5'h1d/* 29*/:5'h14/* 20*/];
assign T62 = T63;
assign T63 = T64;
assign T64 = T68[T65];
assign T65 = T66;
assign T66 = T67;
assign T67 = io_chanxy_config[4'hf/* 15*/:4'hc/* 12*/];
assign T68 = T69;
assign T69 = io_chanxy_in[6'h27/* 39*/:5'h1e/* 30*/];
assign T70 = T71;
assign T71 = T72;
assign T72 = T76[T73];
assign T73 = T74;
assign T74 = T75;
assign T75 = io_chanxy_config[5'h13/* 19*/:5'h10/* 16*/];
assign T76 = T77;
assign T77 = io_chanxy_in[6'h30/* 48*/:6'h28/* 40*/];
assign T78 = T79;
assign T79 = T80;
assign T80 = T84[T81];
assign T81 = T82;
assign T82 = T83;
assign T83 = io_chanxy_config[5'h17/* 23*/:5'h14/* 20*/];
assign T84 = T85;
assign T85 = io_chanxy_in[6'h3a/* 58*/:6'h31/* 49*/];
assign T86 = T87;
assign T87 = T88;
assign T88 = T92[T89];
assign T89 = T90;
assign T90 = T91;
assign T91 = io_chanxy_config[5'h1b/* 27*/:5'h18/* 24*/];
assign T92 = T93;
assign T93 = io_chanxy_in[7'h44/* 68*/:6'h3b/* 59*/];
assign T94 = T95;
assign T95 = T96;
assign T96 = T100[T97];
assign T97 = T98;
assign T98 = T99;
assign T99 = io_chanxy_config[5'h1f/* 31*/:5'h1c/* 28*/];
assign T100 = T101;
assign T101 = io_chanxy_in[7'h4e/* 78*/:7'h45/* 69*/];
assign T102 = T103;
assign T103 = T104;
assign T104 = T108[T105];
assign T105 = T106;
assign T106 = T107;
assign T107 = io_chanxy_config[6'h23/* 35*/:6'h20/* 32*/];
assign T108 = T109;
assign T109 = io_chanxy_in[7'h58/* 88*/:7'h4f/* 79*/];
assign T110 = T111;
assign T111 = T112;
assign T112 = T116[T113];
assign T113 = T114;
assign T114 = T115;
assign T115 = io_chanxy_config[6'h27/* 39*/:6'h24/* 36*/];
assign T116 = T117;
assign T117 = io_chanxy_in[7'h61/* 97*/:7'h59/* 89*/];
assign T118 = T119;
assign T119 = T120;
assign T120 = T124[T121];
assign T121 = T122;
assign T122 = T123;
assign T123 = io_chanxy_config[6'h2b/* 43*/:6'h28/* 40*/];
assign T124 = T125;
assign T125 = io_chanxy_in[7'h6b/* 107*/:7'h62/* 98*/];
assign T126 = T127;
assign T127 = T128;
assign T128 = T132[T129];
assign T129 = T130;
assign T130 = T131;
assign T131 = io_chanxy_config[6'h2f/* 47*/:6'h2c/* 44*/];
assign T132 = T133;
assign T133 = io_chanxy_in[7'h75/* 117*/:7'h6c/* 108*/];
assign T134 = T135;
assign T135 = T136;
assign T136 = T140[T137];
assign T137 = T138;
assign T138 = T139;
assign T139 = io_chanxy_config[6'h33/* 51*/:6'h30/* 48*/];
assign T140 = T141;
assign T141 = io_chanxy_in[7'h7f/* 127*/:7'h76/* 118*/];
assign T142 = T143;
assign T143 = T144;
assign T144 = T148[T145];
assign T145 = T146;
assign T146 = T147;
assign T147 = io_chanxy_config[6'h37/* 55*/:6'h34/* 52*/];
assign T148 = T149;
assign T149 = io_chanxy_in[8'h89/* 137*/:8'h80/* 128*/];
assign T150 = T151;
assign T151 = T152;
assign T152 = T156[T153];
assign T153 = T154;
assign T154 = T155;
assign T155 = io_chanxy_config[6'h3b/* 59*/:6'h38/* 56*/];
assign T156 = T157;
assign T157 = io_chanxy_in[8'h92/* 146*/:8'h8a/* 138*/];
assign T158 = T159;
assign T159 = T160;
assign T160 = T164[T161];
assign T161 = T162;
assign T162 = T163;
assign T163 = io_chanxy_config[6'h3f/* 63*/:6'h3c/* 60*/];
assign T164 = T165;
assign T165 = io_chanxy_in[8'h9c/* 156*/:8'h93/* 147*/];
assign T166 = T167;
assign T167 = T168;
assign T168 = T172[T169];
assign T169 = T170;
assign T170 = T171;
assign T171 = io_chanxy_config[7'h43/* 67*/:7'h40/* 64*/];
assign T172 = T173;
assign T173 = io_chanxy_in[8'ha6/* 166*/:8'h9d/* 157*/];
assign T174 = T175;
assign T175 = T176;
assign T176 = T180[T177];
assign T177 = T178;
assign T178 = T179;
assign T179 = io_chanxy_config[7'h47/* 71*/:7'h44/* 68*/];
assign T180 = T181;
assign T181 = io_chanxy_in[8'hb0/* 176*/:8'ha7/* 167*/];
assign T182 = T183;
assign T183 = T184;
assign T184 = T188[T185];
assign T185 = T186;
assign T186 = T187;
assign T187 = io_chanxy_config[7'h4b/* 75*/:7'h48/* 72*/];
assign T188 = T189;
assign T189 = io_chanxy_in[8'hba/* 186*/:8'hb1/* 177*/];
assign T190 = T191;
assign T191 = T192;
assign T192 = T196[T193];
assign T193 = T194;
assign T194 = T195;
assign T195 = io_chanxy_config[7'h4f/* 79*/:7'h4c/* 76*/];
assign T196 = T197;
assign T197 = io_chanxy_in[8'hc3/* 195*/:8'hbb/* 187*/];
assign io_ipin_out = T198;
assign T198 = T199;
assign T199 = {T298, T200};
assign T200 = T201;
assign T201 = {T290, T202};
assign T202 = T203;
assign T203 = {T282, T204};
assign T204 = T205;
assign T205 = {T274, T206};
assign T206 = T207;
assign T207 = {T266, T208};
assign T208 = T209;
assign T209 = {T258, T210};
assign T210 = T211;
assign T211 = {T250, T212};
assign T212 = T213;
assign T213 = {T242, T214};
assign T214 = T215;
assign T215 = {T234, T216};
assign T216 = T217;
assign T217 = {T226, T218};
assign T218 = T219;
assign T219 = T220;
assign T220 = T224[T221];
assign T221 = T222;
assign T222 = T223;
assign T223 = io_ipin_config[1'h1/* 1*/:1'h0/* 0*/];
assign T224 = T225;
assign T225 = io_ipin_in[2'h3/* 3*/:1'h0/* 0*/];
assign T226 = T227;
assign T227 = T228;
assign T228 = T232[T229];
assign T229 = T230;
assign T230 = T231;
assign T231 = io_ipin_config[2'h3/* 3*/:2'h2/* 2*/];
assign T232 = T233;
assign T233 = io_ipin_in[3'h7/* 7*/:3'h4/* 4*/];
assign T234 = T235;
assign T235 = T236;
assign T236 = T240[T237];
assign T237 = T238;
assign T238 = T239;
assign T239 = io_ipin_config[3'h5/* 5*/:3'h4/* 4*/];
assign T240 = T241;
assign T241 = io_ipin_in[4'hb/* 11*/:4'h8/* 8*/];
assign T242 = T243;
assign T243 = T244;
assign T244 = T248[T245];
assign T245 = T246;
assign T246 = T247;
assign T247 = io_ipin_config[3'h7/* 7*/:3'h6/* 6*/];
assign T248 = T249;
assign T249 = io_ipin_in[4'hf/* 15*/:4'hc/* 12*/];
assign T250 = T251;
assign T251 = T252;
assign T252 = T256[T253];
assign T253 = T254;
assign T254 = T255;
assign T255 = io_ipin_config[4'h9/* 9*/:4'h8/* 8*/];
assign T256 = T257;
assign T257 = io_ipin_in[5'h13/* 19*/:5'h10/* 16*/];
assign T258 = T259;
assign T259 = T260;
assign T260 = T264[T261];
assign T261 = T262;
assign T262 = T263;
assign T263 = io_ipin_config[4'hb/* 11*/:4'ha/* 10*/];
assign T264 = T265;
assign T265 = io_ipin_in[5'h17/* 23*/:5'h14/* 20*/];
assign T266 = T267;
assign T267 = T268;
assign T268 = T272[T269];
assign T269 = T270;
assign T270 = T271;
assign T271 = io_ipin_config[4'hd/* 13*/:4'hc/* 12*/];
assign T272 = T273;
assign T273 = io_ipin_in[5'h1b/* 27*/:5'h18/* 24*/];
assign T274 = T275;
assign T275 = T276;
assign T276 = T280[T277];
assign T277 = T278;
assign T278 = T279;
assign T279 = io_ipin_config[4'hf/* 15*/:4'he/* 14*/];
assign T280 = T281;
assign T281 = io_ipin_in[5'h1f/* 31*/:5'h1c/* 28*/];
assign T282 = T283;
assign T283 = T284;
assign T284 = T288[T285];
assign T285 = T286;
assign T286 = T287;
assign T287 = io_ipin_config[5'h11/* 17*/:5'h10/* 16*/];
assign T288 = T289;
assign T289 = io_ipin_in[6'h23/* 35*/:6'h20/* 32*/];
assign T290 = T291;
assign T291 = T292;
assign T292 = T296[T293];
assign T293 = T294;
assign T294 = T295;
assign T295 = io_ipin_config[5'h13/* 19*/:5'h12/* 18*/];
assign T296 = T297;
assign T297 = io_ipin_in[6'h27/* 39*/:6'h24/* 36*/];
assign T298 = T299;
assign T299 = T300;
assign T300 = T304[T301];
assign T301 = T302;
assign T302 = T303;
assign T303 = io_ipin_config[5'h15/* 21*/:5'h14/* 20*/];
assign T304 = T305;
assign T305 = io_ipin_in[6'h2b/* 43*/:6'h28/* 40*/];
endmodule |
module lut_tile(input clk, input reset,
input io_ff_en,
input [31:0] io_configs_in,
input [7:0] io_configs_en,
input [43:0] io_ipin_in,
input [195:0] io_chanxy_in,
output[19:0] io_chanxy_out,
output[3:0] io_opin_out);
wire[79:0] T0;
wire[255:0] this_config_io_configs_out;
wire[21:0] T1;
wire[63:0] T2;
wire[14:0] T3;
wire[10:0] this_sbcb_io_ipin_out;
wire[3:0] this_clb_io_clb_out;
wire[3:0] T4;
wire[63:0] T5;
wire[15:0] this_xbar_io_xbar_out;
wire[19:0] this_sbcb_io_chanxy_out;
assign T0 = this_config_io_configs_out[8'he9/* 233*/:8'h9a/* 154*/];
assign T1 = this_config_io_configs_out[8'h99/* 153*/:8'h84/* 132*/];
assign T2 = this_config_io_configs_out[8'h83/* 131*/:7'h44/* 68*/];
assign T3 = {this_clb_io_clb_out, this_sbcb_io_ipin_out};
assign T4 = this_config_io_configs_out[7'h43/* 67*/:7'h40/* 64*/];
assign T5 = this_config_io_configs_out[6'h3f/* 63*/:1'h0/* 0*/];
assign io_opin_out = this_clb_io_clb_out;
assign io_chanxy_out = this_sbcb_io_chanxy_out;
clb this_clb(.clk(clk), .reset(reset),
.io_clb_in( this_xbar_io_xbar_out ),
.io_clb_out( this_clb_io_clb_out ),
.io_lut_configs( T5 ),
.io_mux_configs( T4 ),
.io_ff_en( io_ff_en ));
xbar this_xbar(.clk(clk), .reset(reset),
.io_xbar_in( T3 ),
.io_xbar_out( this_xbar_io_xbar_out ),
.io_mux_configs( T2 ));
configs_latches_8 this_config(.clk(clk), .reset(reset),
.io_d_in( io_configs_in ),
.io_configs_out( this_config_io_configs_out ),
.io_configs_en( io_configs_en ));
sbcb this_sbcb(
.io_ipin_in( io_ipin_in ),
.io_ipin_config( T1 ),
.io_chanxy_in( io_chanxy_in ),
.io_chanxy_config( T0 ),
.io_ipin_out( this_sbcb_io_ipin_out ),
.io_chanxy_out( this_sbcb_io_chanxy_out ));
endmodule |
module multi_consumer
(
d_in,
d_out_1, d_out_2, d_out_4, d_out_7,
clock, rst, rdy
);
input clock;
input rst;
input [15:0] d_in;
output [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
output reg rdy;
wire [63:0]fpga_top_in;
wire [63:0] fpga_top_out;
wire [63:0] fpga_bot_in;
wire [63:0] fpga_bot_out;
wire [63:0] fpga_left_in;
wire [63:0] fpga_left_out;
wire [63:0] fpga_right_in;
wire [63:0] fpga_right_out;
reg [319:0] fpga_configs_in;
reg [171:0] fpga_configs_en;
assign d_out_1[14] = fpga_top_out[41];
assign d_out_2[12] = fpga_top_out[42];
assign d_out_4[15] = fpga_top_out[48];
assign d_out_2[15] = fpga_top_out[50];
assign d_out_1[0] = fpga_top_out[51];
assign d_out_1[1] = fpga_top_out[52];
assign d_out_7[0] = fpga_top_out[54];
assign d_out_2[13] = fpga_top_out[56];
assign d_out_1[13] = fpga_top_out[61];
assign d_out_2[14] = fpga_top_out[63];
assign d_out_2[1] = fpga_bot_out[34];
assign d_out_2[2] = fpga_bot_out[37];
assign d_out_4[2] = fpga_bot_out[38];
assign d_out_4[3] = fpga_bot_out[39];
assign d_out_1[2] = fpga_bot_out[40];
assign d_out_1[8] = fpga_bot_out[41];
assign d_out_2[3] = fpga_bot_out[42];
assign d_out_1[7] = fpga_bot_out[43];
assign d_out_2[8] = fpga_bot_out[44];
assign d_out_7[2] = fpga_bot_out[45];
assign d_out_1[3] = fpga_bot_out[46];
assign d_out_2[7] = fpga_bot_out[47];
assign d_out_4[7] = fpga_bot_out[48];
assign d_out_2[4] = fpga_bot_out[49];
assign d_out_7[3] = fpga_bot_out[50];
assign d_out_4[8] = fpga_bot_out[52];
assign d_out_7[10] = fpga_bot_out[53];
assign d_out_1[4] = fpga_bot_out[54];
assign d_out_4[4] = fpga_bot_out[55];
assign d_out_2[10] = fpga_right_out[1];
assign d_out_1[10] = fpga_right_out[2];
assign d_out_2[9] = fpga_right_out[5];
assign d_out_4[10] = fpga_right_out[6];
assign d_out_7[9] = fpga_right_out[8];
assign d_out_7[7] = fpga_right_out[11];
assign d_out_7[6] = fpga_right_out[12];
assign d_out_7[8] = fpga_right_out[14];
assign d_out_7[5] = fpga_right_out[16];
assign d_out_2[6] = fpga_right_out[17];
assign d_out_1[9] = fpga_right_out[19];
assign d_out_1[6] = fpga_right_out[20];
assign d_out_4[6] = fpga_right_out[21];
assign d_out_4[9] = fpga_right_out[22];
assign d_out_7[11] = fpga_right_out[24];
assign d_out_4[0] = fpga_right_out[25];
assign d_out_7[12] = fpga_right_out[26];
assign d_out_7[13] = fpga_right_out[28];
assign d_out_4[13] = fpga_right_out[32];
assign d_out_2[5] = fpga_right_out[35];
assign d_out_1[5] = fpga_right_out[36];
assign d_out_4[5] = fpga_right_out[37];
assign d_out_7[4] = fpga_right_out[38];
assign d_out_4[14] = fpga_right_out[39];
assign d_out_7[14] = fpga_right_out[40];
assign d_out_4[12] = fpga_right_out[41];
assign d_out_2[0] = fpga_right_out[44];
assign d_out_4[11] = fpga_right_out[45];
assign d_out_7[15] = fpga_right_out[46];
assign d_out_1[15] = fpga_right_out[51];
assign d_out_7[1] = fpga_right_out[52];
assign d_out_1[12] = fpga_right_out[60];
assign d_out_4[1] = fpga_right_out[61];
assign d_out_1[11] = fpga_right_out[62];
assign d_out_2[11] = fpga_right_out[63];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_top_in[40] = 1'b0;
assign fpga_top_in[41] = 1'b0;
assign fpga_top_in[42] = 1'b0;
assign fpga_top_in[43] = 1'b0;
assign fpga_top_in[44] = 1'b0;
assign fpga_top_in[45] = 1'b0;
assign fpga_top_in[46] = 1'b0;
assign fpga_top_in[47] = 1'b0;
assign fpga_top_in[48] = 1'b0;
assign fpga_top_in[49] = 1'b0;
assign fpga_top_in[50] = 1'b0;
assign fpga_top_in[51] = 1'b0;
assign fpga_top_in[52] = 1'b0;
assign fpga_top_in[53] = 1'b0;
assign fpga_top_in[54] = 1'b0;
assign fpga_top_in[55] = 1'b0;
assign fpga_top_in[56] = 1'b0;
assign fpga_top_in[57] = 1'b0;
assign fpga_top_in[58] = 1'b0;
assign fpga_top_in[59] = 1'b0;
assign fpga_top_in[60] = 1'b0;
assign fpga_top_in[61] = 1'b0;
assign fpga_top_in[62] = 1'b0;
assign fpga_top_in[63] = 1'b0;
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_bot_in[40] = 1'b0;
assign fpga_bot_in[41] = 1'b0;
assign fpga_bot_in[42] = 1'b0;
assign fpga_bot_in[43] = 1'b0;
assign fpga_bot_in[44] = 1'b0;
assign fpga_bot_in[45] = 1'b0;
assign fpga_bot_in[46] = 1'b0;
assign fpga_bot_in[47] = 1'b0;
assign fpga_bot_in[48] = 1'b0;
assign fpga_bot_in[49] = 1'b0;
assign fpga_bot_in[50] = 1'b0;
assign fpga_bot_in[51] = d_in[0];
assign fpga_bot_in[52] = 1'b0;
assign fpga_bot_in[53] = 1'b0;
assign fpga_bot_in[54] = 1'b0;
assign fpga_bot_in[55] = 1'b0;
assign fpga_bot_in[56] = 1'b0;
assign fpga_bot_in[57] = 1'b0;
assign fpga_bot_in[58] = 1'b0;
assign fpga_bot_in[59] = 1'b0;
assign fpga_bot_in[60] = 1'b0;
assign fpga_bot_in[61] = 1'b0;
assign fpga_bot_in[62] = 1'b0;
assign fpga_bot_in[63] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_left_in[40] = 1'b0;
assign fpga_left_in[41] = 1'b0;
assign fpga_left_in[42] = 1'b0;
assign fpga_left_in[43] = 1'b0;
assign fpga_left_in[44] = 1'b0;
assign fpga_left_in[45] = 1'b0;
assign fpga_left_in[46] = 1'b0;
assign fpga_left_in[47] = 1'b0;
assign fpga_left_in[48] = 1'b0;
assign fpga_left_in[49] = 1'b0;
assign fpga_left_in[50] = 1'b0;
assign fpga_left_in[51] = 1'b0;
assign fpga_left_in[52] = 1'b0;
assign fpga_left_in[53] = 1'b0;
assign fpga_left_in[54] = 1'b0;
assign fpga_left_in[55] = 1'b0;
assign fpga_left_in[56] = 1'b0;
assign fpga_left_in[57] = 1'b0;
assign fpga_left_in[58] = 1'b0;
assign fpga_left_in[59] = 1'b0;
assign fpga_left_in[60] = 1'b0;
assign fpga_left_in[61] = 1'b0;
assign fpga_left_in[62] = 1'b0;
assign fpga_left_in[63] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = d_in[6];
assign fpga_right_in[10] = d_in[8];
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = d_in[7];
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = d_in[3];
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = d_in[2];
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = d_in[1];
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = d_in[10];
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = d_in[9];
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = d_in[5];
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = d_in[4];
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
assign fpga_right_in[40] = 1'b0;
assign fpga_right_in[41] = 1'b0;
assign fpga_right_in[42] = d_in[14];
assign fpga_right_in[43] = d_in[13];
assign fpga_right_in[44] = 1'b0;
assign fpga_right_in[45] = 1'b0;
assign fpga_right_in[46] = 1'b0;
assign fpga_right_in[47] = 1'b0;
assign fpga_right_in[48] = d_in[11];
assign fpga_right_in[49] = d_in[12];
assign fpga_right_in[50] = 1'b0;
assign fpga_right_in[51] = 1'b0;
assign fpga_right_in[52] = 1'b0;
assign fpga_right_in[53] = 1'b0;
assign fpga_right_in[54] = 1'b0;
assign fpga_right_in[55] = d_in[15];
assign fpga_right_in[56] = 1'b0;
assign fpga_right_in[57] = 1'b0;
assign fpga_right_in[58] = 1'b0;
assign fpga_right_in[59] = 1'b0;
assign fpga_right_in[60] = 1'b0;
assign fpga_right_in[61] = 1'b0;
assign fpga_right_in[62] = 1'b0;
assign fpga_right_in[63] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("multi_consumer.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module simple_comp
(
a_in, b_in, c_in,
d_out,
clock, rst, rdy
);
input [15:0] a_in;
input [15:0] b_in;
input [15:0] c_in;
input clock;
input rst;
output [15:0] d_out;
output reg rdy;
wire [63:0]fpga_top_in;
wire [63:0] fpga_top_out;
wire [63:0] fpga_bot_in;
wire [63:0] fpga_bot_out;
wire [63:0] fpga_left_in;
wire [63:0] fpga_left_out;
wire [63:0] fpga_right_in;
wire [63:0] fpga_right_out;
reg [319:0] fpga_configs_in;
reg [171:0] fpga_configs_en;
assign d_out[0] = fpga_top_out[40];
assign d_out[3] = fpga_top_out[43];
assign d_out[4] = fpga_top_out[47];
assign d_out[14] = fpga_top_out[51];
assign d_out[10] = fpga_top_out[53];
assign d_out[15] = fpga_top_out[54];
assign d_out[11] = fpga_top_out[55];
assign d_out[6] = fpga_right_out[18];
assign d_out[7] = fpga_right_out[22];
assign d_out[8] = fpga_right_out[24];
assign d_out[9] = fpga_right_out[30];
assign d_out[5] = fpga_right_out[34];
assign d_out[2] = fpga_right_out[42];
assign d_out[1] = fpga_right_out[43];
assign d_out[12] = fpga_right_out[56];
assign d_out[13] = fpga_right_out[59];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_top_in[40] = 1'b0;
assign fpga_top_in[41] = 1'b0;
assign fpga_top_in[42] = 1'b0;
assign fpga_top_in[43] = 1'b0;
assign fpga_top_in[44] = 1'b0;
assign fpga_top_in[45] = 1'b0;
assign fpga_top_in[46] = 1'b0;
assign fpga_top_in[47] = 1'b0;
assign fpga_top_in[48] = c_in[15];
assign fpga_top_in[49] = c_in[11];
assign fpga_top_in[50] = c_in[10];
assign fpga_top_in[51] = 1'b0;
assign fpga_top_in[52] = c_in[14];
assign fpga_top_in[53] = 1'b0;
assign fpga_top_in[54] = 1'b0;
assign fpga_top_in[55] = 1'b0;
assign fpga_top_in[56] = rst;
assign fpga_top_in[57] = c_in[13];
assign fpga_top_in[58] = 1'b0;
assign fpga_top_in[59] = 1'b0;
assign fpga_top_in[60] = 1'b0;
assign fpga_top_in[61] = 1'b0;
assign fpga_top_in[62] = 1'b0;
assign fpga_top_in[63] = c_in[12];
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_bot_in[40] = 1'b0;
assign fpga_bot_in[41] = 1'b0;
assign fpga_bot_in[42] = 1'b0;
assign fpga_bot_in[43] = 1'b0;
assign fpga_bot_in[44] = 1'b0;
assign fpga_bot_in[45] = 1'b0;
assign fpga_bot_in[46] = 1'b0;
assign fpga_bot_in[47] = 1'b0;
assign fpga_bot_in[48] = 1'b0;
assign fpga_bot_in[49] = 1'b0;
assign fpga_bot_in[50] = 1'b0;
assign fpga_bot_in[51] = 1'b0;
assign fpga_bot_in[52] = 1'b0;
assign fpga_bot_in[53] = 1'b0;
assign fpga_bot_in[54] = 1'b0;
assign fpga_bot_in[55] = 1'b0;
assign fpga_bot_in[56] = 1'b0;
assign fpga_bot_in[57] = 1'b0;
assign fpga_bot_in[58] = 1'b0;
assign fpga_bot_in[59] = 1'b0;
assign fpga_bot_in[60] = 1'b0;
assign fpga_bot_in[61] = 1'b0;
assign fpga_bot_in[62] = c_in[5];
assign fpga_bot_in[63] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_left_in[40] = 1'b0;
assign fpga_left_in[41] = 1'b0;
assign fpga_left_in[42] = 1'b0;
assign fpga_left_in[43] = 1'b0;
assign fpga_left_in[44] = 1'b0;
assign fpga_left_in[45] = 1'b0;
assign fpga_left_in[46] = 1'b0;
assign fpga_left_in[47] = 1'b0;
assign fpga_left_in[48] = 1'b0;
assign fpga_left_in[49] = 1'b0;
assign fpga_left_in[50] = 1'b0;
assign fpga_left_in[51] = 1'b0;
assign fpga_left_in[52] = 1'b0;
assign fpga_left_in[53] = 1'b0;
assign fpga_left_in[54] = 1'b0;
assign fpga_left_in[55] = 1'b0;
assign fpga_left_in[56] = 1'b0;
assign fpga_left_in[57] = 1'b0;
assign fpga_left_in[58] = 1'b0;
assign fpga_left_in[59] = 1'b0;
assign fpga_left_in[60] = 1'b0;
assign fpga_left_in[61] = 1'b0;
assign fpga_left_in[62] = 1'b0;
assign fpga_left_in[63] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = b_in[5];
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = a_in[7];
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = a_in[6];
assign fpga_right_in[15] = b_in[7];
assign fpga_right_in[16] = b_in[6];
assign fpga_right_in[17] = c_in[7];
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = a_in[4];
assign fpga_right_in[20] = a_in[5];
assign fpga_right_in[21] = c_in[6];
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = b_in[3];
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = b_in[8];
assign fpga_right_in[26] = b_in[4];
assign fpga_right_in[27] = c_in[9];
assign fpga_right_in[28] = a_in[9];
assign fpga_right_in[29] = a_in[8];
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = b_in[9];
assign fpga_right_in[32] = a_in[3];
assign fpga_right_in[33] = b_in[2];
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = c_in[8];
assign fpga_right_in[36] = b_in[1];
assign fpga_right_in[37] = c_in[4];
assign fpga_right_in[38] = a_in[2];
assign fpga_right_in[39] = c_in[3];
assign fpga_right_in[40] = a_in[1];
assign fpga_right_in[41] = b_in[0];
assign fpga_right_in[42] = 1'b0;
assign fpga_right_in[43] = 1'b0;
assign fpga_right_in[44] = c_in[2];
assign fpga_right_in[45] = c_in[0];
assign fpga_right_in[46] = c_in[1];
assign fpga_right_in[47] = a_in[0];
assign fpga_right_in[48] = a_in[11];
assign fpga_right_in[49] = b_in[10];
assign fpga_right_in[50] = a_in[10];
assign fpga_right_in[51] = a_in[15];
assign fpga_right_in[52] = a_in[14];
assign fpga_right_in[53] = b_in[14];
assign fpga_right_in[54] = b_in[11];
assign fpga_right_in[55] = b_in[15];
assign fpga_right_in[56] = 1'b0;
assign fpga_right_in[57] = 1'b0;
assign fpga_right_in[58] = b_in[13];
assign fpga_right_in[59] = 1'b0;
assign fpga_right_in[60] = a_in[12];
assign fpga_right_in[61] = b_in[12];
assign fpga_right_in[62] = a_in[13];
assign fpga_right_in[63] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("simple_comp.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module ff_en
(
d_in, d_out, clock, rst, d_en, rdy
);
input clock;
input rst;
input d_en;
input [9:0] d_in;
output [9:0] d_out;
output reg rdy;
wire [63:0]fpga_top_in;
wire [63:0] fpga_top_out;
wire [63:0] fpga_bot_in;
wire [63:0] fpga_bot_out;
wire [63:0] fpga_left_in;
wire [63:0] fpga_left_out;
wire [63:0] fpga_right_in;
wire [63:0] fpga_right_out;
reg [319:0] fpga_configs_in;
reg [171:0] fpga_configs_en;
assign d_out[6] = fpga_left_out[40];
assign d_out[4] = fpga_left_out[43];
assign d_out[5] = fpga_left_out[45];
assign d_out[3] = fpga_left_out[46];
assign d_out[1] = fpga_left_out[50];
assign d_out[2] = fpga_left_out[54];
assign d_out[8] = fpga_left_out[57];
assign d_out[0] = fpga_left_out[59];
assign d_out[7] = fpga_left_out[61];
assign d_out[9] = fpga_left_out[62];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = d_in[8];
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = d_in[7];
assign fpga_top_in[6] = d_in[9];
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = rst;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_top_in[40] = 1'b0;
assign fpga_top_in[41] = 1'b0;
assign fpga_top_in[42] = 1'b0;
assign fpga_top_in[43] = 1'b0;
assign fpga_top_in[44] = 1'b0;
assign fpga_top_in[45] = 1'b0;
assign fpga_top_in[46] = 1'b0;
assign fpga_top_in[47] = 1'b0;
assign fpga_top_in[48] = 1'b0;
assign fpga_top_in[49] = 1'b0;
assign fpga_top_in[50] = 1'b0;
assign fpga_top_in[51] = 1'b0;
assign fpga_top_in[52] = 1'b0;
assign fpga_top_in[53] = 1'b0;
assign fpga_top_in[54] = 1'b0;
assign fpga_top_in[55] = 1'b0;
assign fpga_top_in[56] = 1'b0;
assign fpga_top_in[57] = 1'b0;
assign fpga_top_in[58] = 1'b0;
assign fpga_top_in[59] = 1'b0;
assign fpga_top_in[60] = 1'b0;
assign fpga_top_in[61] = 1'b0;
assign fpga_top_in[62] = 1'b0;
assign fpga_top_in[63] = 1'b0;
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_bot_in[40] = 1'b0;
assign fpga_bot_in[41] = 1'b0;
assign fpga_bot_in[42] = 1'b0;
assign fpga_bot_in[43] = 1'b0;
assign fpga_bot_in[44] = 1'b0;
assign fpga_bot_in[45] = 1'b0;
assign fpga_bot_in[46] = 1'b0;
assign fpga_bot_in[47] = 1'b0;
assign fpga_bot_in[48] = 1'b0;
assign fpga_bot_in[49] = 1'b0;
assign fpga_bot_in[50] = 1'b0;
assign fpga_bot_in[51] = 1'b0;
assign fpga_bot_in[52] = 1'b0;
assign fpga_bot_in[53] = 1'b0;
assign fpga_bot_in[54] = 1'b0;
assign fpga_bot_in[55] = 1'b0;
assign fpga_bot_in[56] = 1'b0;
assign fpga_bot_in[57] = 1'b0;
assign fpga_bot_in[58] = 1'b0;
assign fpga_bot_in[59] = 1'b0;
assign fpga_bot_in[60] = 1'b0;
assign fpga_bot_in[61] = 1'b0;
assign fpga_bot_in[62] = 1'b0;
assign fpga_bot_in[63] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_left_in[40] = 1'b0;
assign fpga_left_in[41] = d_in[4];
assign fpga_left_in[42] = d_in[6];
assign fpga_left_in[43] = 1'b0;
assign fpga_left_in[44] = d_in[5];
assign fpga_left_in[45] = 1'b0;
assign fpga_left_in[46] = 1'b0;
assign fpga_left_in[47] = d_in[3];
assign fpga_left_in[48] = d_en;
assign fpga_left_in[49] = d_in[1];
assign fpga_left_in[50] = 1'b0;
assign fpga_left_in[51] = 1'b0;
assign fpga_left_in[52] = d_in[2];
assign fpga_left_in[53] = 1'b0;
assign fpga_left_in[54] = 1'b0;
assign fpga_left_in[55] = 1'b0;
assign fpga_left_in[56] = 1'b0;
assign fpga_left_in[57] = 1'b0;
assign fpga_left_in[58] = 1'b0;
assign fpga_left_in[59] = 1'b0;
assign fpga_left_in[60] = 1'b0;
assign fpga_left_in[61] = 1'b0;
assign fpga_left_in[62] = 1'b0;
assign fpga_left_in[63] = d_in[0];
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = 1'b0;
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
assign fpga_right_in[40] = 1'b0;
assign fpga_right_in[41] = 1'b0;
assign fpga_right_in[42] = 1'b0;
assign fpga_right_in[43] = 1'b0;
assign fpga_right_in[44] = 1'b0;
assign fpga_right_in[45] = 1'b0;
assign fpga_right_in[46] = 1'b0;
assign fpga_right_in[47] = 1'b0;
assign fpga_right_in[48] = 1'b0;
assign fpga_right_in[49] = 1'b0;
assign fpga_right_in[50] = 1'b0;
assign fpga_right_in[51] = 1'b0;
assign fpga_right_in[52] = 1'b0;
assign fpga_right_in[53] = 1'b0;
assign fpga_right_in[54] = 1'b0;
assign fpga_right_in[55] = 1'b0;
assign fpga_right_in[56] = 1'b0;
assign fpga_right_in[57] = 1'b0;
assign fpga_right_in[58] = 1'b0;
assign fpga_right_in[59] = 1'b0;
assign fpga_right_in[60] = 1'b0;
assign fpga_right_in[61] = 1'b0;
assign fpga_right_in[62] = 1'b0;
assign fpga_right_in[63] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("ff_en.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module multi_consumer
(
d_in,
d_out_1, d_out_2, d_out_4, d_out_7,
clock, rst, rdy
);
input clock;
input rst;
input [15:0] d_in;
output [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
output reg rdy;
wire [199:0]fpga_top_in;
wire [199:0] fpga_top_out;
wire [199:0] fpga_bot_in;
wire [199:0] fpga_bot_out;
wire [199:0] fpga_left_in;
wire [199:0] fpga_left_out;
wire [199:0] fpga_right_in;
wire [199:0] fpga_right_out;
reg [863:0] fpga_configs_in;
reg [354:0] fpga_configs_en;
assign d_out_1[13] = fpga_top_out[176];
assign d_out_1[10] = fpga_top_out[177];
assign d_out_4[12] = fpga_top_out[180];
assign d_out_1[12] = fpga_top_out[181];
assign d_out_2[11] = fpga_top_out[183];
assign d_out_2[14] = fpga_top_out[198];
assign d_out_2[15] = fpga_right_out[92];
assign d_out_1[15] = fpga_right_out[107];
assign d_out_2[1] = fpga_right_out[112];
assign d_out_1[1] = fpga_right_out[113];
assign d_out_7[1] = fpga_right_out[116];
assign d_out_4[4] = fpga_right_out[117];
assign d_out_7[2] = fpga_right_out[119];
assign d_out_4[5] = fpga_right_out[120];
assign d_out_4[3] = fpga_right_out[121];
assign d_out_7[3] = fpga_right_out[122];
assign d_out_2[3] = fpga_right_out[123];
assign d_out_4[2] = fpga_right_out[124];
assign d_out_1[3] = fpga_right_out[125];
assign d_out_1[4] = fpga_right_out[126];
assign d_out_1[5] = fpga_right_out[127];
assign d_out_7[6] = fpga_right_out[128];
assign d_out_7[4] = fpga_right_out[129];
assign d_out_1[8] = fpga_right_out[130];
assign d_out_1[7] = fpga_right_out[131];
assign d_out_2[4] = fpga_right_out[132];
assign d_out_2[8] = fpga_right_out[133];
assign d_out_7[5] = fpga_right_out[134];
assign d_out_7[8] = fpga_right_out[135];
assign d_out_4[7] = fpga_right_out[136];
assign d_out_2[6] = fpga_right_out[137];
assign d_out_4[8] = fpga_right_out[138];
assign d_out_4[6] = fpga_right_out[139];
assign d_out_7[15] = fpga_right_out[140];
assign d_out_1[6] = fpga_right_out[141];
assign d_out_2[5] = fpga_right_out[142];
assign d_out_2[7] = fpga_right_out[143];
assign d_out_7[7] = fpga_right_out[148];
assign d_out_7[9] = fpga_right_out[150];
assign d_out_7[14] = fpga_right_out[152];
assign d_out_4[15] = fpga_right_out[155];
assign d_out_1[14] = fpga_right_out[159];
assign d_out_7[12] = fpga_right_out[160];
assign d_out_2[10] = fpga_right_out[161];
assign d_out_7[0] = fpga_right_out[162];
assign d_out_2[9] = fpga_right_out[163];
assign d_out_1[2] = fpga_right_out[164];
assign d_out_2[2] = fpga_right_out[165];
assign d_out_1[0] = fpga_right_out[166];
assign d_out_2[13] = fpga_right_out[167];
assign d_out_4[1] = fpga_right_out[168];
assign d_out_4[14] = fpga_right_out[169];
assign d_out_2[0] = fpga_right_out[172];
assign d_out_2[12] = fpga_right_out[173];
assign d_out_1[11] = fpga_right_out[174];
assign d_out_7[13] = fpga_right_out[175];
assign d_out_4[0] = fpga_right_out[178];
assign d_out_4[9] = fpga_right_out[180];
assign d_out_7[10] = fpga_right_out[182];
assign d_out_4[10] = fpga_right_out[183];
assign d_out_4[11] = fpga_right_out[184];
assign d_out_4[13] = fpga_right_out[188];
assign d_out_1[9] = fpga_right_out[190];
assign d_out_7[11] = fpga_right_out[196];
assign fpga_top_in[0] = 1'b0;
assign fpga_top_in[1] = 1'b0;
assign fpga_top_in[2] = 1'b0;
assign fpga_top_in[3] = 1'b0;
assign fpga_top_in[4] = 1'b0;
assign fpga_top_in[5] = 1'b0;
assign fpga_top_in[6] = 1'b0;
assign fpga_top_in[7] = 1'b0;
assign fpga_top_in[8] = 1'b0;
assign fpga_top_in[9] = 1'b0;
assign fpga_top_in[10] = 1'b0;
assign fpga_top_in[11] = 1'b0;
assign fpga_top_in[12] = 1'b0;
assign fpga_top_in[13] = 1'b0;
assign fpga_top_in[14] = 1'b0;
assign fpga_top_in[15] = 1'b0;
assign fpga_top_in[16] = 1'b0;
assign fpga_top_in[17] = 1'b0;
assign fpga_top_in[18] = 1'b0;
assign fpga_top_in[19] = 1'b0;
assign fpga_top_in[20] = 1'b0;
assign fpga_top_in[21] = 1'b0;
assign fpga_top_in[22] = 1'b0;
assign fpga_top_in[23] = 1'b0;
assign fpga_top_in[24] = 1'b0;
assign fpga_top_in[25] = 1'b0;
assign fpga_top_in[26] = 1'b0;
assign fpga_top_in[27] = 1'b0;
assign fpga_top_in[28] = 1'b0;
assign fpga_top_in[29] = 1'b0;
assign fpga_top_in[30] = 1'b0;
assign fpga_top_in[31] = 1'b0;
assign fpga_top_in[32] = 1'b0;
assign fpga_top_in[33] = 1'b0;
assign fpga_top_in[34] = 1'b0;
assign fpga_top_in[35] = 1'b0;
assign fpga_top_in[36] = 1'b0;
assign fpga_top_in[37] = 1'b0;
assign fpga_top_in[38] = 1'b0;
assign fpga_top_in[39] = 1'b0;
assign fpga_top_in[40] = 1'b0;
assign fpga_top_in[41] = 1'b0;
assign fpga_top_in[42] = 1'b0;
assign fpga_top_in[43] = 1'b0;
assign fpga_top_in[44] = 1'b0;
assign fpga_top_in[45] = 1'b0;
assign fpga_top_in[46] = 1'b0;
assign fpga_top_in[47] = 1'b0;
assign fpga_top_in[48] = 1'b0;
assign fpga_top_in[49] = 1'b0;
assign fpga_top_in[50] = 1'b0;
assign fpga_top_in[51] = 1'b0;
assign fpga_top_in[52] = 1'b0;
assign fpga_top_in[53] = 1'b0;
assign fpga_top_in[54] = 1'b0;
assign fpga_top_in[55] = 1'b0;
assign fpga_top_in[56] = 1'b0;
assign fpga_top_in[57] = 1'b0;
assign fpga_top_in[58] = 1'b0;
assign fpga_top_in[59] = 1'b0;
assign fpga_top_in[60] = 1'b0;
assign fpga_top_in[61] = 1'b0;
assign fpga_top_in[62] = 1'b0;
assign fpga_top_in[63] = 1'b0;
assign fpga_top_in[64] = 1'b0;
assign fpga_top_in[65] = 1'b0;
assign fpga_top_in[66] = 1'b0;
assign fpga_top_in[67] = 1'b0;
assign fpga_top_in[68] = 1'b0;
assign fpga_top_in[69] = 1'b0;
assign fpga_top_in[70] = 1'b0;
assign fpga_top_in[71] = 1'b0;
assign fpga_top_in[72] = 1'b0;
assign fpga_top_in[73] = 1'b0;
assign fpga_top_in[74] = 1'b0;
assign fpga_top_in[75] = 1'b0;
assign fpga_top_in[76] = 1'b0;
assign fpga_top_in[77] = 1'b0;
assign fpga_top_in[78] = 1'b0;
assign fpga_top_in[79] = 1'b0;
assign fpga_top_in[80] = 1'b0;
assign fpga_top_in[81] = 1'b0;
assign fpga_top_in[82] = 1'b0;
assign fpga_top_in[83] = 1'b0;
assign fpga_top_in[84] = 1'b0;
assign fpga_top_in[85] = 1'b0;
assign fpga_top_in[86] = 1'b0;
assign fpga_top_in[87] = 1'b0;
assign fpga_top_in[88] = 1'b0;
assign fpga_top_in[89] = 1'b0;
assign fpga_top_in[90] = 1'b0;
assign fpga_top_in[91] = 1'b0;
assign fpga_top_in[92] = 1'b0;
assign fpga_top_in[93] = 1'b0;
assign fpga_top_in[94] = 1'b0;
assign fpga_top_in[95] = 1'b0;
assign fpga_top_in[96] = 1'b0;
assign fpga_top_in[97] = 1'b0;
assign fpga_top_in[98] = 1'b0;
assign fpga_top_in[99] = 1'b0;
assign fpga_top_in[100] = 1'b0;
assign fpga_top_in[101] = 1'b0;
assign fpga_top_in[102] = 1'b0;
assign fpga_top_in[103] = 1'b0;
assign fpga_top_in[104] = 1'b0;
assign fpga_top_in[105] = 1'b0;
assign fpga_top_in[106] = 1'b0;
assign fpga_top_in[107] = 1'b0;
assign fpga_top_in[108] = 1'b0;
assign fpga_top_in[109] = 1'b0;
assign fpga_top_in[110] = 1'b0;
assign fpga_top_in[111] = 1'b0;
assign fpga_top_in[112] = 1'b0;
assign fpga_top_in[113] = 1'b0;
assign fpga_top_in[114] = 1'b0;
assign fpga_top_in[115] = 1'b0;
assign fpga_top_in[116] = 1'b0;
assign fpga_top_in[117] = 1'b0;
assign fpga_top_in[118] = 1'b0;
assign fpga_top_in[119] = 1'b0;
assign fpga_top_in[120] = 1'b0;
assign fpga_top_in[121] = 1'b0;
assign fpga_top_in[122] = 1'b0;
assign fpga_top_in[123] = 1'b0;
assign fpga_top_in[124] = 1'b0;
assign fpga_top_in[125] = 1'b0;
assign fpga_top_in[126] = 1'b0;
assign fpga_top_in[127] = 1'b0;
assign fpga_top_in[128] = 1'b0;
assign fpga_top_in[129] = 1'b0;
assign fpga_top_in[130] = 1'b0;
assign fpga_top_in[131] = 1'b0;
assign fpga_top_in[132] = 1'b0;
assign fpga_top_in[133] = 1'b0;
assign fpga_top_in[134] = 1'b0;
assign fpga_top_in[135] = 1'b0;
assign fpga_top_in[136] = 1'b0;
assign fpga_top_in[137] = 1'b0;
assign fpga_top_in[138] = 1'b0;
assign fpga_top_in[139] = 1'b0;
assign fpga_top_in[140] = 1'b0;
assign fpga_top_in[141] = 1'b0;
assign fpga_top_in[142] = 1'b0;
assign fpga_top_in[143] = 1'b0;
assign fpga_top_in[144] = 1'b0;
assign fpga_top_in[145] = 1'b0;
assign fpga_top_in[146] = 1'b0;
assign fpga_top_in[147] = 1'b0;
assign fpga_top_in[148] = 1'b0;
assign fpga_top_in[149] = 1'b0;
assign fpga_top_in[150] = 1'b0;
assign fpga_top_in[151] = 1'b0;
assign fpga_top_in[152] = 1'b0;
assign fpga_top_in[153] = 1'b0;
assign fpga_top_in[154] = 1'b0;
assign fpga_top_in[155] = 1'b0;
assign fpga_top_in[156] = 1'b0;
assign fpga_top_in[157] = 1'b0;
assign fpga_top_in[158] = 1'b0;
assign fpga_top_in[159] = 1'b0;
assign fpga_top_in[160] = 1'b0;
assign fpga_top_in[161] = 1'b0;
assign fpga_top_in[162] = 1'b0;
assign fpga_top_in[163] = 1'b0;
assign fpga_top_in[164] = 1'b0;
assign fpga_top_in[165] = 1'b0;
assign fpga_top_in[166] = 1'b0;
assign fpga_top_in[167] = 1'b0;
assign fpga_top_in[168] = 1'b0;
assign fpga_top_in[169] = 1'b0;
assign fpga_top_in[170] = 1'b0;
assign fpga_top_in[171] = 1'b0;
assign fpga_top_in[172] = 1'b0;
assign fpga_top_in[173] = 1'b0;
assign fpga_top_in[174] = 1'b0;
assign fpga_top_in[175] = 1'b0;
assign fpga_top_in[176] = 1'b0;
assign fpga_top_in[177] = 1'b0;
assign fpga_top_in[178] = 1'b0;
assign fpga_top_in[179] = 1'b0;
assign fpga_top_in[180] = 1'b0;
assign fpga_top_in[181] = 1'b0;
assign fpga_top_in[182] = 1'b0;
assign fpga_top_in[183] = 1'b0;
assign fpga_top_in[184] = 1'b0;
assign fpga_top_in[185] = 1'b0;
assign fpga_top_in[186] = 1'b0;
assign fpga_top_in[187] = 1'b0;
assign fpga_top_in[188] = 1'b0;
assign fpga_top_in[189] = 1'b0;
assign fpga_top_in[190] = 1'b0;
assign fpga_top_in[191] = 1'b0;
assign fpga_top_in[192] = 1'b0;
assign fpga_top_in[193] = 1'b0;
assign fpga_top_in[194] = 1'b0;
assign fpga_top_in[195] = 1'b0;
assign fpga_top_in[196] = 1'b0;
assign fpga_top_in[197] = 1'b0;
assign fpga_top_in[198] = 1'b0;
assign fpga_top_in[199] = 1'b0;
assign fpga_bot_in[0] = 1'b0;
assign fpga_bot_in[1] = 1'b0;
assign fpga_bot_in[2] = 1'b0;
assign fpga_bot_in[3] = 1'b0;
assign fpga_bot_in[4] = 1'b0;
assign fpga_bot_in[5] = 1'b0;
assign fpga_bot_in[6] = 1'b0;
assign fpga_bot_in[7] = 1'b0;
assign fpga_bot_in[8] = 1'b0;
assign fpga_bot_in[9] = 1'b0;
assign fpga_bot_in[10] = 1'b0;
assign fpga_bot_in[11] = 1'b0;
assign fpga_bot_in[12] = 1'b0;
assign fpga_bot_in[13] = 1'b0;
assign fpga_bot_in[14] = 1'b0;
assign fpga_bot_in[15] = 1'b0;
assign fpga_bot_in[16] = 1'b0;
assign fpga_bot_in[17] = 1'b0;
assign fpga_bot_in[18] = 1'b0;
assign fpga_bot_in[19] = 1'b0;
assign fpga_bot_in[20] = 1'b0;
assign fpga_bot_in[21] = 1'b0;
assign fpga_bot_in[22] = 1'b0;
assign fpga_bot_in[23] = 1'b0;
assign fpga_bot_in[24] = 1'b0;
assign fpga_bot_in[25] = 1'b0;
assign fpga_bot_in[26] = 1'b0;
assign fpga_bot_in[27] = 1'b0;
assign fpga_bot_in[28] = 1'b0;
assign fpga_bot_in[29] = 1'b0;
assign fpga_bot_in[30] = 1'b0;
assign fpga_bot_in[31] = 1'b0;
assign fpga_bot_in[32] = 1'b0;
assign fpga_bot_in[33] = 1'b0;
assign fpga_bot_in[34] = 1'b0;
assign fpga_bot_in[35] = 1'b0;
assign fpga_bot_in[36] = 1'b0;
assign fpga_bot_in[37] = 1'b0;
assign fpga_bot_in[38] = 1'b0;
assign fpga_bot_in[39] = 1'b0;
assign fpga_bot_in[40] = 1'b0;
assign fpga_bot_in[41] = 1'b0;
assign fpga_bot_in[42] = 1'b0;
assign fpga_bot_in[43] = 1'b0;
assign fpga_bot_in[44] = 1'b0;
assign fpga_bot_in[45] = 1'b0;
assign fpga_bot_in[46] = 1'b0;
assign fpga_bot_in[47] = 1'b0;
assign fpga_bot_in[48] = 1'b0;
assign fpga_bot_in[49] = 1'b0;
assign fpga_bot_in[50] = 1'b0;
assign fpga_bot_in[51] = 1'b0;
assign fpga_bot_in[52] = 1'b0;
assign fpga_bot_in[53] = 1'b0;
assign fpga_bot_in[54] = 1'b0;
assign fpga_bot_in[55] = 1'b0;
assign fpga_bot_in[56] = 1'b0;
assign fpga_bot_in[57] = 1'b0;
assign fpga_bot_in[58] = 1'b0;
assign fpga_bot_in[59] = 1'b0;
assign fpga_bot_in[60] = 1'b0;
assign fpga_bot_in[61] = 1'b0;
assign fpga_bot_in[62] = 1'b0;
assign fpga_bot_in[63] = 1'b0;
assign fpga_bot_in[64] = 1'b0;
assign fpga_bot_in[65] = 1'b0;
assign fpga_bot_in[66] = 1'b0;
assign fpga_bot_in[67] = 1'b0;
assign fpga_bot_in[68] = 1'b0;
assign fpga_bot_in[69] = 1'b0;
assign fpga_bot_in[70] = 1'b0;
assign fpga_bot_in[71] = 1'b0;
assign fpga_bot_in[72] = 1'b0;
assign fpga_bot_in[73] = 1'b0;
assign fpga_bot_in[74] = 1'b0;
assign fpga_bot_in[75] = 1'b0;
assign fpga_bot_in[76] = 1'b0;
assign fpga_bot_in[77] = 1'b0;
assign fpga_bot_in[78] = 1'b0;
assign fpga_bot_in[79] = 1'b0;
assign fpga_bot_in[80] = 1'b0;
assign fpga_bot_in[81] = 1'b0;
assign fpga_bot_in[82] = 1'b0;
assign fpga_bot_in[83] = 1'b0;
assign fpga_bot_in[84] = 1'b0;
assign fpga_bot_in[85] = 1'b0;
assign fpga_bot_in[86] = 1'b0;
assign fpga_bot_in[87] = 1'b0;
assign fpga_bot_in[88] = 1'b0;
assign fpga_bot_in[89] = 1'b0;
assign fpga_bot_in[90] = 1'b0;
assign fpga_bot_in[91] = 1'b0;
assign fpga_bot_in[92] = 1'b0;
assign fpga_bot_in[93] = 1'b0;
assign fpga_bot_in[94] = 1'b0;
assign fpga_bot_in[95] = 1'b0;
assign fpga_bot_in[96] = 1'b0;
assign fpga_bot_in[97] = 1'b0;
assign fpga_bot_in[98] = 1'b0;
assign fpga_bot_in[99] = 1'b0;
assign fpga_bot_in[100] = 1'b0;
assign fpga_bot_in[101] = 1'b0;
assign fpga_bot_in[102] = 1'b0;
assign fpga_bot_in[103] = 1'b0;
assign fpga_bot_in[104] = 1'b0;
assign fpga_bot_in[105] = 1'b0;
assign fpga_bot_in[106] = 1'b0;
assign fpga_bot_in[107] = 1'b0;
assign fpga_bot_in[108] = 1'b0;
assign fpga_bot_in[109] = 1'b0;
assign fpga_bot_in[110] = 1'b0;
assign fpga_bot_in[111] = 1'b0;
assign fpga_bot_in[112] = 1'b0;
assign fpga_bot_in[113] = 1'b0;
assign fpga_bot_in[114] = 1'b0;
assign fpga_bot_in[115] = 1'b0;
assign fpga_bot_in[116] = 1'b0;
assign fpga_bot_in[117] = 1'b0;
assign fpga_bot_in[118] = 1'b0;
assign fpga_bot_in[119] = 1'b0;
assign fpga_bot_in[120] = 1'b0;
assign fpga_bot_in[121] = 1'b0;
assign fpga_bot_in[122] = 1'b0;
assign fpga_bot_in[123] = 1'b0;
assign fpga_bot_in[124] = 1'b0;
assign fpga_bot_in[125] = 1'b0;
assign fpga_bot_in[126] = 1'b0;
assign fpga_bot_in[127] = 1'b0;
assign fpga_bot_in[128] = 1'b0;
assign fpga_bot_in[129] = 1'b0;
assign fpga_bot_in[130] = 1'b0;
assign fpga_bot_in[131] = 1'b0;
assign fpga_bot_in[132] = 1'b0;
assign fpga_bot_in[133] = 1'b0;
assign fpga_bot_in[134] = 1'b0;
assign fpga_bot_in[135] = 1'b0;
assign fpga_bot_in[136] = 1'b0;
assign fpga_bot_in[137] = 1'b0;
assign fpga_bot_in[138] = 1'b0;
assign fpga_bot_in[139] = 1'b0;
assign fpga_bot_in[140] = 1'b0;
assign fpga_bot_in[141] = 1'b0;
assign fpga_bot_in[142] = 1'b0;
assign fpga_bot_in[143] = 1'b0;
assign fpga_bot_in[144] = 1'b0;
assign fpga_bot_in[145] = 1'b0;
assign fpga_bot_in[146] = 1'b0;
assign fpga_bot_in[147] = 1'b0;
assign fpga_bot_in[148] = 1'b0;
assign fpga_bot_in[149] = 1'b0;
assign fpga_bot_in[150] = 1'b0;
assign fpga_bot_in[151] = 1'b0;
assign fpga_bot_in[152] = 1'b0;
assign fpga_bot_in[153] = 1'b0;
assign fpga_bot_in[154] = 1'b0;
assign fpga_bot_in[155] = 1'b0;
assign fpga_bot_in[156] = 1'b0;
assign fpga_bot_in[157] = 1'b0;
assign fpga_bot_in[158] = 1'b0;
assign fpga_bot_in[159] = 1'b0;
assign fpga_bot_in[160] = 1'b0;
assign fpga_bot_in[161] = 1'b0;
assign fpga_bot_in[162] = 1'b0;
assign fpga_bot_in[163] = 1'b0;
assign fpga_bot_in[164] = 1'b0;
assign fpga_bot_in[165] = 1'b0;
assign fpga_bot_in[166] = 1'b0;
assign fpga_bot_in[167] = 1'b0;
assign fpga_bot_in[168] = 1'b0;
assign fpga_bot_in[169] = 1'b0;
assign fpga_bot_in[170] = 1'b0;
assign fpga_bot_in[171] = 1'b0;
assign fpga_bot_in[172] = 1'b0;
assign fpga_bot_in[173] = 1'b0;
assign fpga_bot_in[174] = 1'b0;
assign fpga_bot_in[175] = 1'b0;
assign fpga_bot_in[176] = 1'b0;
assign fpga_bot_in[177] = 1'b0;
assign fpga_bot_in[178] = 1'b0;
assign fpga_bot_in[179] = 1'b0;
assign fpga_bot_in[180] = 1'b0;
assign fpga_bot_in[181] = 1'b0;
assign fpga_bot_in[182] = 1'b0;
assign fpga_bot_in[183] = 1'b0;
assign fpga_bot_in[184] = 1'b0;
assign fpga_bot_in[185] = 1'b0;
assign fpga_bot_in[186] = 1'b0;
assign fpga_bot_in[187] = 1'b0;
assign fpga_bot_in[188] = 1'b0;
assign fpga_bot_in[189] = 1'b0;
assign fpga_bot_in[190] = 1'b0;
assign fpga_bot_in[191] = 1'b0;
assign fpga_bot_in[192] = 1'b0;
assign fpga_bot_in[193] = 1'b0;
assign fpga_bot_in[194] = 1'b0;
assign fpga_bot_in[195] = 1'b0;
assign fpga_bot_in[196] = 1'b0;
assign fpga_bot_in[197] = 1'b0;
assign fpga_bot_in[198] = 1'b0;
assign fpga_bot_in[199] = 1'b0;
assign fpga_left_in[0] = 1'b0;
assign fpga_left_in[1] = 1'b0;
assign fpga_left_in[2] = 1'b0;
assign fpga_left_in[3] = 1'b0;
assign fpga_left_in[4] = 1'b0;
assign fpga_left_in[5] = 1'b0;
assign fpga_left_in[6] = 1'b0;
assign fpga_left_in[7] = 1'b0;
assign fpga_left_in[8] = 1'b0;
assign fpga_left_in[9] = 1'b0;
assign fpga_left_in[10] = 1'b0;
assign fpga_left_in[11] = 1'b0;
assign fpga_left_in[12] = 1'b0;
assign fpga_left_in[13] = 1'b0;
assign fpga_left_in[14] = 1'b0;
assign fpga_left_in[15] = 1'b0;
assign fpga_left_in[16] = 1'b0;
assign fpga_left_in[17] = 1'b0;
assign fpga_left_in[18] = 1'b0;
assign fpga_left_in[19] = 1'b0;
assign fpga_left_in[20] = 1'b0;
assign fpga_left_in[21] = 1'b0;
assign fpga_left_in[22] = 1'b0;
assign fpga_left_in[23] = 1'b0;
assign fpga_left_in[24] = 1'b0;
assign fpga_left_in[25] = 1'b0;
assign fpga_left_in[26] = 1'b0;
assign fpga_left_in[27] = 1'b0;
assign fpga_left_in[28] = 1'b0;
assign fpga_left_in[29] = 1'b0;
assign fpga_left_in[30] = 1'b0;
assign fpga_left_in[31] = 1'b0;
assign fpga_left_in[32] = 1'b0;
assign fpga_left_in[33] = 1'b0;
assign fpga_left_in[34] = 1'b0;
assign fpga_left_in[35] = 1'b0;
assign fpga_left_in[36] = 1'b0;
assign fpga_left_in[37] = 1'b0;
assign fpga_left_in[38] = 1'b0;
assign fpga_left_in[39] = 1'b0;
assign fpga_left_in[40] = 1'b0;
assign fpga_left_in[41] = 1'b0;
assign fpga_left_in[42] = 1'b0;
assign fpga_left_in[43] = 1'b0;
assign fpga_left_in[44] = 1'b0;
assign fpga_left_in[45] = 1'b0;
assign fpga_left_in[46] = 1'b0;
assign fpga_left_in[47] = 1'b0;
assign fpga_left_in[48] = 1'b0;
assign fpga_left_in[49] = 1'b0;
assign fpga_left_in[50] = 1'b0;
assign fpga_left_in[51] = 1'b0;
assign fpga_left_in[52] = 1'b0;
assign fpga_left_in[53] = 1'b0;
assign fpga_left_in[54] = 1'b0;
assign fpga_left_in[55] = 1'b0;
assign fpga_left_in[56] = 1'b0;
assign fpga_left_in[57] = 1'b0;
assign fpga_left_in[58] = 1'b0;
assign fpga_left_in[59] = 1'b0;
assign fpga_left_in[60] = 1'b0;
assign fpga_left_in[61] = 1'b0;
assign fpga_left_in[62] = 1'b0;
assign fpga_left_in[63] = 1'b0;
assign fpga_left_in[64] = 1'b0;
assign fpga_left_in[65] = 1'b0;
assign fpga_left_in[66] = 1'b0;
assign fpga_left_in[67] = 1'b0;
assign fpga_left_in[68] = 1'b0;
assign fpga_left_in[69] = 1'b0;
assign fpga_left_in[70] = 1'b0;
assign fpga_left_in[71] = 1'b0;
assign fpga_left_in[72] = 1'b0;
assign fpga_left_in[73] = 1'b0;
assign fpga_left_in[74] = 1'b0;
assign fpga_left_in[75] = 1'b0;
assign fpga_left_in[76] = 1'b0;
assign fpga_left_in[77] = 1'b0;
assign fpga_left_in[78] = 1'b0;
assign fpga_left_in[79] = 1'b0;
assign fpga_left_in[80] = 1'b0;
assign fpga_left_in[81] = 1'b0;
assign fpga_left_in[82] = 1'b0;
assign fpga_left_in[83] = 1'b0;
assign fpga_left_in[84] = 1'b0;
assign fpga_left_in[85] = 1'b0;
assign fpga_left_in[86] = 1'b0;
assign fpga_left_in[87] = 1'b0;
assign fpga_left_in[88] = 1'b0;
assign fpga_left_in[89] = 1'b0;
assign fpga_left_in[90] = 1'b0;
assign fpga_left_in[91] = 1'b0;
assign fpga_left_in[92] = 1'b0;
assign fpga_left_in[93] = 1'b0;
assign fpga_left_in[94] = 1'b0;
assign fpga_left_in[95] = 1'b0;
assign fpga_left_in[96] = 1'b0;
assign fpga_left_in[97] = 1'b0;
assign fpga_left_in[98] = 1'b0;
assign fpga_left_in[99] = 1'b0;
assign fpga_left_in[100] = 1'b0;
assign fpga_left_in[101] = 1'b0;
assign fpga_left_in[102] = 1'b0;
assign fpga_left_in[103] = 1'b0;
assign fpga_left_in[104] = 1'b0;
assign fpga_left_in[105] = 1'b0;
assign fpga_left_in[106] = 1'b0;
assign fpga_left_in[107] = 1'b0;
assign fpga_left_in[108] = 1'b0;
assign fpga_left_in[109] = 1'b0;
assign fpga_left_in[110] = 1'b0;
assign fpga_left_in[111] = 1'b0;
assign fpga_left_in[112] = 1'b0;
assign fpga_left_in[113] = 1'b0;
assign fpga_left_in[114] = 1'b0;
assign fpga_left_in[115] = 1'b0;
assign fpga_left_in[116] = 1'b0;
assign fpga_left_in[117] = 1'b0;
assign fpga_left_in[118] = 1'b0;
assign fpga_left_in[119] = 1'b0;
assign fpga_left_in[120] = 1'b0;
assign fpga_left_in[121] = 1'b0;
assign fpga_left_in[122] = 1'b0;
assign fpga_left_in[123] = 1'b0;
assign fpga_left_in[124] = 1'b0;
assign fpga_left_in[125] = 1'b0;
assign fpga_left_in[126] = 1'b0;
assign fpga_left_in[127] = 1'b0;
assign fpga_left_in[128] = 1'b0;
assign fpga_left_in[129] = 1'b0;
assign fpga_left_in[130] = 1'b0;
assign fpga_left_in[131] = 1'b0;
assign fpga_left_in[132] = 1'b0;
assign fpga_left_in[133] = 1'b0;
assign fpga_left_in[134] = 1'b0;
assign fpga_left_in[135] = 1'b0;
assign fpga_left_in[136] = 1'b0;
assign fpga_left_in[137] = 1'b0;
assign fpga_left_in[138] = 1'b0;
assign fpga_left_in[139] = 1'b0;
assign fpga_left_in[140] = 1'b0;
assign fpga_left_in[141] = 1'b0;
assign fpga_left_in[142] = 1'b0;
assign fpga_left_in[143] = 1'b0;
assign fpga_left_in[144] = 1'b0;
assign fpga_left_in[145] = 1'b0;
assign fpga_left_in[146] = 1'b0;
assign fpga_left_in[147] = 1'b0;
assign fpga_left_in[148] = 1'b0;
assign fpga_left_in[149] = 1'b0;
assign fpga_left_in[150] = 1'b0;
assign fpga_left_in[151] = 1'b0;
assign fpga_left_in[152] = 1'b0;
assign fpga_left_in[153] = 1'b0;
assign fpga_left_in[154] = 1'b0;
assign fpga_left_in[155] = 1'b0;
assign fpga_left_in[156] = 1'b0;
assign fpga_left_in[157] = 1'b0;
assign fpga_left_in[158] = 1'b0;
assign fpga_left_in[159] = 1'b0;
assign fpga_left_in[160] = 1'b0;
assign fpga_left_in[161] = 1'b0;
assign fpga_left_in[162] = 1'b0;
assign fpga_left_in[163] = 1'b0;
assign fpga_left_in[164] = 1'b0;
assign fpga_left_in[165] = 1'b0;
assign fpga_left_in[166] = 1'b0;
assign fpga_left_in[167] = 1'b0;
assign fpga_left_in[168] = 1'b0;
assign fpga_left_in[169] = 1'b0;
assign fpga_left_in[170] = 1'b0;
assign fpga_left_in[171] = 1'b0;
assign fpga_left_in[172] = 1'b0;
assign fpga_left_in[173] = 1'b0;
assign fpga_left_in[174] = 1'b0;
assign fpga_left_in[175] = 1'b0;
assign fpga_left_in[176] = 1'b0;
assign fpga_left_in[177] = 1'b0;
assign fpga_left_in[178] = 1'b0;
assign fpga_left_in[179] = 1'b0;
assign fpga_left_in[180] = 1'b0;
assign fpga_left_in[181] = 1'b0;
assign fpga_left_in[182] = 1'b0;
assign fpga_left_in[183] = 1'b0;
assign fpga_left_in[184] = 1'b0;
assign fpga_left_in[185] = 1'b0;
assign fpga_left_in[186] = 1'b0;
assign fpga_left_in[187] = 1'b0;
assign fpga_left_in[188] = 1'b0;
assign fpga_left_in[189] = 1'b0;
assign fpga_left_in[190] = 1'b0;
assign fpga_left_in[191] = 1'b0;
assign fpga_left_in[192] = 1'b0;
assign fpga_left_in[193] = 1'b0;
assign fpga_left_in[194] = 1'b0;
assign fpga_left_in[195] = 1'b0;
assign fpga_left_in[196] = 1'b0;
assign fpga_left_in[197] = 1'b0;
assign fpga_left_in[198] = 1'b0;
assign fpga_left_in[199] = 1'b0;
assign fpga_right_in[0] = 1'b0;
assign fpga_right_in[1] = 1'b0;
assign fpga_right_in[2] = 1'b0;
assign fpga_right_in[3] = 1'b0;
assign fpga_right_in[4] = 1'b0;
assign fpga_right_in[5] = 1'b0;
assign fpga_right_in[6] = 1'b0;
assign fpga_right_in[7] = 1'b0;
assign fpga_right_in[8] = 1'b0;
assign fpga_right_in[9] = 1'b0;
assign fpga_right_in[10] = 1'b0;
assign fpga_right_in[11] = 1'b0;
assign fpga_right_in[12] = 1'b0;
assign fpga_right_in[13] = 1'b0;
assign fpga_right_in[14] = 1'b0;
assign fpga_right_in[15] = 1'b0;
assign fpga_right_in[16] = 1'b0;
assign fpga_right_in[17] = 1'b0;
assign fpga_right_in[18] = 1'b0;
assign fpga_right_in[19] = 1'b0;
assign fpga_right_in[20] = 1'b0;
assign fpga_right_in[21] = 1'b0;
assign fpga_right_in[22] = 1'b0;
assign fpga_right_in[23] = 1'b0;
assign fpga_right_in[24] = 1'b0;
assign fpga_right_in[25] = 1'b0;
assign fpga_right_in[26] = 1'b0;
assign fpga_right_in[27] = 1'b0;
assign fpga_right_in[28] = 1'b0;
assign fpga_right_in[29] = 1'b0;
assign fpga_right_in[30] = 1'b0;
assign fpga_right_in[31] = 1'b0;
assign fpga_right_in[32] = 1'b0;
assign fpga_right_in[33] = 1'b0;
assign fpga_right_in[34] = 1'b0;
assign fpga_right_in[35] = 1'b0;
assign fpga_right_in[36] = 1'b0;
assign fpga_right_in[37] = 1'b0;
assign fpga_right_in[38] = 1'b0;
assign fpga_right_in[39] = 1'b0;
assign fpga_right_in[40] = 1'b0;
assign fpga_right_in[41] = 1'b0;
assign fpga_right_in[42] = 1'b0;
assign fpga_right_in[43] = 1'b0;
assign fpga_right_in[44] = 1'b0;
assign fpga_right_in[45] = 1'b0;
assign fpga_right_in[46] = 1'b0;
assign fpga_right_in[47] = 1'b0;
assign fpga_right_in[48] = 1'b0;
assign fpga_right_in[49] = 1'b0;
assign fpga_right_in[50] = 1'b0;
assign fpga_right_in[51] = 1'b0;
assign fpga_right_in[52] = 1'b0;
assign fpga_right_in[53] = 1'b0;
assign fpga_right_in[54] = 1'b0;
assign fpga_right_in[55] = 1'b0;
assign fpga_right_in[56] = 1'b0;
assign fpga_right_in[57] = 1'b0;
assign fpga_right_in[58] = 1'b0;
assign fpga_right_in[59] = 1'b0;
assign fpga_right_in[60] = 1'b0;
assign fpga_right_in[61] = 1'b0;
assign fpga_right_in[62] = 1'b0;
assign fpga_right_in[63] = 1'b0;
assign fpga_right_in[64] = 1'b0;
assign fpga_right_in[65] = 1'b0;
assign fpga_right_in[66] = 1'b0;
assign fpga_right_in[67] = 1'b0;
assign fpga_right_in[68] = 1'b0;
assign fpga_right_in[69] = 1'b0;
assign fpga_right_in[70] = 1'b0;
assign fpga_right_in[71] = 1'b0;
assign fpga_right_in[72] = 1'b0;
assign fpga_right_in[73] = 1'b0;
assign fpga_right_in[74] = 1'b0;
assign fpga_right_in[75] = 1'b0;
assign fpga_right_in[76] = 1'b0;
assign fpga_right_in[77] = 1'b0;
assign fpga_right_in[78] = 1'b0;
assign fpga_right_in[79] = 1'b0;
assign fpga_right_in[80] = 1'b0;
assign fpga_right_in[81] = 1'b0;
assign fpga_right_in[82] = 1'b0;
assign fpga_right_in[83] = 1'b0;
assign fpga_right_in[84] = 1'b0;
assign fpga_right_in[85] = 1'b0;
assign fpga_right_in[86] = 1'b0;
assign fpga_right_in[87] = 1'b0;
assign fpga_right_in[88] = 1'b0;
assign fpga_right_in[89] = 1'b0;
assign fpga_right_in[90] = 1'b0;
assign fpga_right_in[91] = 1'b0;
assign fpga_right_in[92] = 1'b0;
assign fpga_right_in[93] = 1'b0;
assign fpga_right_in[94] = 1'b0;
assign fpga_right_in[95] = 1'b0;
assign fpga_right_in[96] = 1'b0;
assign fpga_right_in[97] = 1'b0;
assign fpga_right_in[98] = 1'b0;
assign fpga_right_in[99] = 1'b0;
assign fpga_right_in[100] = 1'b0;
assign fpga_right_in[101] = 1'b0;
assign fpga_right_in[102] = 1'b0;
assign fpga_right_in[103] = 1'b0;
assign fpga_right_in[104] = 1'b0;
assign fpga_right_in[105] = 1'b0;
assign fpga_right_in[106] = 1'b0;
assign fpga_right_in[107] = 1'b0;
assign fpga_right_in[108] = 1'b0;
assign fpga_right_in[109] = 1'b0;
assign fpga_right_in[110] = 1'b0;
assign fpga_right_in[111] = 1'b0;
assign fpga_right_in[112] = 1'b0;
assign fpga_right_in[113] = 1'b0;
assign fpga_right_in[114] = d_in[0];
assign fpga_right_in[115] = d_in[15];
assign fpga_right_in[116] = 1'b0;
assign fpga_right_in[117] = 1'b0;
assign fpga_right_in[118] = 1'b0;
assign fpga_right_in[119] = 1'b0;
assign fpga_right_in[120] = 1'b0;
assign fpga_right_in[121] = 1'b0;
assign fpga_right_in[122] = 1'b0;
assign fpga_right_in[123] = 1'b0;
assign fpga_right_in[124] = 1'b0;
assign fpga_right_in[125] = 1'b0;
assign fpga_right_in[126] = 1'b0;
assign fpga_right_in[127] = 1'b0;
assign fpga_right_in[128] = 1'b0;
assign fpga_right_in[129] = 1'b0;
assign fpga_right_in[130] = 1'b0;
assign fpga_right_in[131] = 1'b0;
assign fpga_right_in[132] = 1'b0;
assign fpga_right_in[133] = 1'b0;
assign fpga_right_in[134] = 1'b0;
assign fpga_right_in[135] = 1'b0;
assign fpga_right_in[136] = 1'b0;
assign fpga_right_in[137] = 1'b0;
assign fpga_right_in[138] = 1'b0;
assign fpga_right_in[139] = 1'b0;
assign fpga_right_in[140] = 1'b0;
assign fpga_right_in[141] = 1'b0;
assign fpga_right_in[142] = 1'b0;
assign fpga_right_in[143] = 1'b0;
assign fpga_right_in[144] = d_in[6];
assign fpga_right_in[145] = d_in[7];
assign fpga_right_in[146] = d_in[8];
assign fpga_right_in[147] = 1'b0;
assign fpga_right_in[148] = 1'b0;
assign fpga_right_in[149] = d_in[1];
assign fpga_right_in[150] = 1'b0;
assign fpga_right_in[151] = d_in[10];
assign fpga_right_in[152] = 1'b0;
assign fpga_right_in[153] = d_in[2];
assign fpga_right_in[154] = d_in[3];
assign fpga_right_in[155] = 1'b0;
assign fpga_right_in[156] = d_in[5];
assign fpga_right_in[157] = d_in[4];
assign fpga_right_in[158] = 1'b0;
assign fpga_right_in[159] = 1'b0;
assign fpga_right_in[160] = 1'b0;
assign fpga_right_in[161] = 1'b0;
assign fpga_right_in[162] = 1'b0;
assign fpga_right_in[163] = 1'b0;
assign fpga_right_in[164] = 1'b0;
assign fpga_right_in[165] = 1'b0;
assign fpga_right_in[166] = 1'b0;
assign fpga_right_in[167] = 1'b0;
assign fpga_right_in[168] = 1'b0;
assign fpga_right_in[169] = 1'b0;
assign fpga_right_in[170] = 1'b0;
assign fpga_right_in[171] = d_in[9];
assign fpga_right_in[172] = 1'b0;
assign fpga_right_in[173] = 1'b0;
assign fpga_right_in[174] = 1'b0;
assign fpga_right_in[175] = 1'b0;
assign fpga_right_in[176] = d_in[11];
assign fpga_right_in[177] = d_in[12];
assign fpga_right_in[178] = 1'b0;
assign fpga_right_in[179] = d_in[13];
assign fpga_right_in[180] = 1'b0;
assign fpga_right_in[181] = d_in[14];
assign fpga_right_in[182] = 1'b0;
assign fpga_right_in[183] = 1'b0;
assign fpga_right_in[184] = 1'b0;
assign fpga_right_in[185] = 1'b0;
assign fpga_right_in[186] = 1'b0;
assign fpga_right_in[187] = 1'b0;
assign fpga_right_in[188] = 1'b0;
assign fpga_right_in[189] = 1'b0;
assign fpga_right_in[190] = 1'b0;
assign fpga_right_in[191] = 1'b0;
assign fpga_right_in[192] = 1'b0;
assign fpga_right_in[193] = 1'b0;
assign fpga_right_in[194] = 1'b0;
assign fpga_right_in[195] = 1'b0;
assign fpga_right_in[196] = 1'b0;
assign fpga_right_in[197] = 1'b0;
assign fpga_right_in[198] = 1'b0;
assign fpga_right_in[199] = 1'b0;
reg ff_en;
integer in_f;
integer read_status; initial begin
in_f = $fopen("multi_consumer.bs", "r");
fpga_configs_in = 1'b0;
ff_en = 1'b0;
rdy = 1'b0;
fpga_configs_en = 1'b1;
end
initial begin
repeat (10) @ (posedge clock);
while ( ! $feof(in_f)) begin
@ (posedge clock);
read_status = $fscanf(in_f, "%b\n", fpga_configs_in);
@ (posedge clock);
fpga_configs_en = fpga_configs_en << 1;
end
repeat (10) @ (posedge clock);
$fclose(in_f);
#100 ff_en = 1'b1;
#100 rdy = 1'b1;
end
fpga fpag_dut (
.top_in(fpga_top_in),
.bot_in(fpga_bot_in),
.left_in(fpga_left_in),
.right_in(fpga_right_in),
.top_out(fpga_top_out),
.bot_out(fpga_bot_out),
.left_out(fpga_left_out),
.right_out(fpga_right_out),
.ff_en(ff_en),
.configs_en(fpga_configs_en),
.configs_in(fpga_configs_in),
.clock(clock),
.rst(rst)
);
endmodule |
module dma_bench #
(
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = 64,
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA immediate enable
parameter DMA_IMM_ENABLE = 0,
// DMA immediate width
parameter DMA_IMM_WIDTH = 32,
// DMA Length field width
parameter DMA_LEN_WIDTH = 16,
// DMA Tag field width
parameter DMA_TAG_WIDTH = 8,
// RAM select width
parameter RAM_SEL_WIDTH = 2,
// RAM address width
parameter RAM_ADDR_WIDTH = 16,
// RAM segment count
parameter RAM_SEG_COUNT = 2,
// RAM segment data width
parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
// RAM segment byte enable width
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
// RAM segment address width
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 16,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI Lite control interface
*/
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_ctrl_awaddr,
input wire [2:0] s_axil_ctrl_awprot,
input wire s_axil_ctrl_awvalid,
output wire s_axil_ctrl_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_ctrl_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_ctrl_wstrb,
input wire s_axil_ctrl_wvalid,
output wire s_axil_ctrl_wready,
output wire [1:0] s_axil_ctrl_bresp,
output wire s_axil_ctrl_bvalid,
input wire s_axil_ctrl_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_ctrl_araddr,
input wire [2:0] s_axil_ctrl_arprot,
input wire s_axil_ctrl_arvalid,
output wire s_axil_ctrl_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_ctrl_rdata,
output wire [1:0] s_axil_ctrl_rresp,
output wire s_axil_ctrl_rvalid,
input wire s_axil_ctrl_rready,
/*
* AXI read descriptor output
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_SEL_WIDTH-1:0] m_axis_dma_read_desc_ram_sel,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* AXI read descriptor status input
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid,
/*
* AXI write descriptor output
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_SEL_WIDTH-1:0] m_axis_dma_write_desc_ram_sel,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_IMM_WIDTH-1:0] m_axis_dma_write_desc_imm,
output wire m_axis_dma_write_desc_imm_en,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* AXI write descriptor status input
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid,
/*
* RAM interface
*/
input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel,
input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr,
input wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid,
output wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_ready,
output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_rd_resp_data,
output wire [RAM_SEG_COUNT-1:0] ram_rd_resp_valid,
input wire [RAM_SEG_COUNT-1:0] ram_rd_resp_ready,
input wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel,
input wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
input wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid,
output wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready,
output wire [RAM_SEG_COUNT-1:0] ram_wr_done,
/*
* MSI request outputs
*/
output wire [31:0] msi_irq,
/*
* Statistics increment input
*/
input wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
input wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
input wire s_axis_stat_tvalid,
output wire s_axis_stat_tready
);
localparam RAM_ADDR_IMM_WIDTH = (DMA_IMM_ENABLE && (DMA_IMM_WIDTH > RAM_ADDR_WIDTH)) ? DMA_IMM_WIDTH : RAM_ADDR_WIDTH;
// parameter sizing helpers
function [31:0] w_32(input [31:0] val);
w_32 = val;
endfunction
wire [AXIL_ADDR_WIDTH-1:0] axil_csr_awaddr;
wire [2:0] axil_csr_awprot;
wire axil_csr_awvalid;
wire axil_csr_awready;
wire [AXIL_DATA_WIDTH-1:0] axil_csr_wdata;
wire [AXIL_STRB_WIDTH-1:0] axil_csr_wstrb;
wire axil_csr_wvalid;
wire axil_csr_wready;
wire [1:0] axil_csr_bresp;
wire axil_csr_bvalid;
wire axil_csr_bready;
wire [AXIL_ADDR_WIDTH-1:0] axil_csr_araddr;
wire [2:0] axil_csr_arprot;
wire axil_csr_arvalid;
wire axil_csr_arready;
wire [AXIL_DATA_WIDTH-1:0] axil_csr_rdata;
wire [1:0] axil_csr_rresp;
wire axil_csr_rvalid;
wire axil_csr_rready;
wire [AXIL_ADDR_WIDTH-1:0] axil_stats_awaddr;
wire [2:0] axil_stats_awprot;
wire axil_stats_awvalid;
wire axil_stats_awready;
wire [AXIL_DATA_WIDTH-1:0] axil_stats_wdata;
wire [AXIL_STRB_WIDTH-1:0] axil_stats_wstrb;
wire axil_stats_wvalid;
wire axil_stats_wready;
wire [1:0] axil_stats_bresp;
wire axil_stats_bvalid;
wire axil_stats_bready;
wire [AXIL_ADDR_WIDTH-1:0] axil_stats_araddr;
wire [2:0] axil_stats_arprot;
wire axil_stats_arvalid;
wire axil_stats_arready;
wire [AXIL_DATA_WIDTH-1:0] axil_stats_rdata;
wire [1:0] axil_stats_rresp;
wire axil_stats_rvalid;
wire axil_stats_rready;
axil_interconnect #(
.DATA_WIDTH(AXIL_DATA_WIDTH),
.ADDR_WIDTH(AXIL_ADDR_WIDTH),
.S_COUNT(1),
.M_COUNT(2),
.M_BASE_ADDR(0),
.M_ADDR_WIDTH({2{w_32(16)}}),
.M_CONNECT_READ({2{1'b1}}),
.M_CONNECT_WRITE({2{1'b1}})
)
axil_interconnect_inst (
.clk(clk),
.rst(rst),
.s_axil_awaddr(s_axil_ctrl_awaddr),
.s_axil_awprot(s_axil_ctrl_awprot),
.s_axil_awvalid(s_axil_ctrl_awvalid),
.s_axil_awready(s_axil_ctrl_awready),
.s_axil_wdata(s_axil_ctrl_wdata),
.s_axil_wstrb(s_axil_ctrl_wstrb),
.s_axil_wvalid(s_axil_ctrl_wvalid),
.s_axil_wready(s_axil_ctrl_wready),
.s_axil_bresp(s_axil_ctrl_bresp),
.s_axil_bvalid(s_axil_ctrl_bvalid),
.s_axil_bready(s_axil_ctrl_bready),
.s_axil_araddr(s_axil_ctrl_araddr),
.s_axil_arprot(s_axil_ctrl_arprot),
.s_axil_arvalid(s_axil_ctrl_arvalid),
.s_axil_arready(s_axil_ctrl_arready),
.s_axil_rdata(s_axil_ctrl_rdata),
.s_axil_rresp(s_axil_ctrl_rresp),
.s_axil_rvalid(s_axil_ctrl_rvalid),
.s_axil_rready(s_axil_ctrl_rready),
.m_axil_awaddr( {axil_stats_awaddr, axil_csr_awaddr }),
.m_axil_awprot( {axil_stats_awprot, axil_csr_awprot }),
.m_axil_awvalid({axil_stats_awvalid, axil_csr_awvalid}),
.m_axil_awready({axil_stats_awready, axil_csr_awready}),
.m_axil_wdata( {axil_stats_wdata, axil_csr_wdata }),
.m_axil_wstrb( {axil_stats_wstrb, axil_csr_wstrb }),
.m_axil_wvalid( {axil_stats_wvalid, axil_csr_wvalid }),
.m_axil_wready( {axil_stats_wready, axil_csr_wready }),
.m_axil_bresp( {axil_stats_bresp, axil_csr_bresp }),
.m_axil_bvalid( {axil_stats_bvalid, axil_csr_bvalid }),
.m_axil_bready( {axil_stats_bready, axil_csr_bready }),
.m_axil_araddr( {axil_stats_araddr, axil_csr_araddr }),
.m_axil_arprot( {axil_stats_arprot, axil_csr_arprot }),
.m_axil_arvalid({axil_stats_arvalid, axil_csr_arvalid}),
.m_axil_arready({axil_stats_arready, axil_csr_arready}),
.m_axil_rdata( {axil_stats_rdata, axil_csr_rdata }),
.m_axil_rresp( {axil_stats_rresp, axil_csr_rresp }),
.m_axil_rvalid( {axil_stats_rvalid, axil_csr_rvalid }),
.m_axil_rready( {axil_stats_rready, axil_csr_rready })
);
// control registers
reg axil_csr_awready_reg = 1'b0, axil_csr_awready_next;
reg axil_csr_wready_reg = 1'b0, axil_csr_wready_next;
reg [1:0] axil_csr_bresp_reg = 2'b00, axil_csr_bresp_next;
reg axil_csr_bvalid_reg = 1'b0, axil_csr_bvalid_next;
reg axil_csr_arready_reg = 1'b0, axil_csr_arready_next;
reg [AXIL_DATA_WIDTH-1:0] axil_csr_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, axil_csr_rdata_next;
reg [1:0] axil_csr_rresp_reg = 2'b00, axil_csr_rresp_next;
reg axil_csr_rvalid_reg = 1'b0, axil_csr_rvalid_next;
reg [63:0] cycle_count_reg = 0;
reg [15:0] dma_read_active_count_reg = 0;
reg [15:0] dma_write_active_count_reg = 0;
reg [DMA_ADDR_WIDTH-1:0] dma_read_desc_dma_addr_reg = 0, dma_read_desc_dma_addr_next;
reg [RAM_ADDR_WIDTH-1:0] dma_read_desc_ram_addr_reg = 0, dma_read_desc_ram_addr_next;
reg [DMA_LEN_WIDTH-1:0] dma_read_desc_len_reg = 0, dma_read_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] dma_read_desc_tag_reg = 0, dma_read_desc_tag_next;
reg dma_read_desc_valid_reg = 0, dma_read_desc_valid_next;
reg [DMA_TAG_WIDTH-1:0] dma_read_desc_status_tag_reg = 0, dma_read_desc_status_tag_next;
reg [3:0] dma_read_desc_status_error_reg = 0, dma_read_desc_status_error_next;
reg dma_read_desc_status_valid_reg = 0, dma_read_desc_status_valid_next;
reg [DMA_ADDR_WIDTH-1:0] dma_write_desc_dma_addr_reg = 0, dma_write_desc_dma_addr_next;
reg [RAM_ADDR_IMM_WIDTH-1:0] dma_write_desc_ram_addr_imm_reg = 0, dma_write_desc_ram_addr_imm_next;
reg dma_write_desc_imm_en_reg = 0, dma_write_desc_imm_en_next;
reg [DMA_LEN_WIDTH-1:0] dma_write_desc_len_reg = 0, dma_write_desc_len_next;
reg [DMA_TAG_WIDTH-1:0] dma_write_desc_tag_reg = 0, dma_write_desc_tag_next;
reg dma_write_desc_valid_reg = 0, dma_write_desc_valid_next;
reg [DMA_TAG_WIDTH-1:0] dma_write_desc_status_tag_reg = 0, dma_write_desc_status_tag_next;
reg [3:0] dma_write_desc_status_error_reg = 0, dma_write_desc_status_error_next;
reg dma_write_desc_status_valid_reg = 0, dma_write_desc_status_valid_next;
reg dma_enable_reg = 0, dma_enable_next;
reg dma_rd_int_en_reg = 0, dma_rd_int_en_next;
reg dma_wr_int_en_reg = 0, dma_wr_int_en_next;
reg dma_read_block_run_reg = 1'b0, dma_read_block_run_next;
reg [DMA_LEN_WIDTH-1:0] dma_read_block_len_reg = 0, dma_read_block_len_next;
reg [31:0] dma_read_block_count_reg = 0, dma_read_block_count_next;
reg [63:0] dma_read_block_cycle_count_reg = 0, dma_read_block_cycle_count_next;
reg [DMA_ADDR_WIDTH-1:0] dma_read_block_dma_base_addr_reg = 0, dma_read_block_dma_base_addr_next;
reg [DMA_ADDR_WIDTH-1:0] dma_read_block_dma_offset_reg = 0, dma_read_block_dma_offset_next;
reg [DMA_ADDR_WIDTH-1:0] dma_read_block_dma_offset_mask_reg = 0, dma_read_block_dma_offset_mask_next;
reg [DMA_ADDR_WIDTH-1:0] dma_read_block_dma_stride_reg = 0, dma_read_block_dma_stride_next;
reg [RAM_ADDR_WIDTH-1:0] dma_read_block_ram_base_addr_reg = 0, dma_read_block_ram_base_addr_next;
reg [RAM_ADDR_WIDTH-1:0] dma_read_block_ram_offset_reg = 0, dma_read_block_ram_offset_next;
reg [RAM_ADDR_WIDTH-1:0] dma_read_block_ram_offset_mask_reg = 0, dma_read_block_ram_offset_mask_next;
reg [RAM_ADDR_WIDTH-1:0] dma_read_block_ram_stride_reg = 0, dma_read_block_ram_stride_next;
reg dma_write_block_run_reg = 1'b0, dma_write_block_run_next;
reg [DMA_LEN_WIDTH-1:0] dma_write_block_len_reg = 0, dma_write_block_len_next;
reg [31:0] dma_write_block_count_reg = 0, dma_write_block_count_next;
reg [63:0] dma_write_block_cycle_count_reg = 0, dma_write_block_cycle_count_next;
reg [DMA_ADDR_WIDTH-1:0] dma_write_block_dma_base_addr_reg = 0, dma_write_block_dma_base_addr_next;
reg [DMA_ADDR_WIDTH-1:0] dma_write_block_dma_offset_reg = 0, dma_write_block_dma_offset_next;
reg [DMA_ADDR_WIDTH-1:0] dma_write_block_dma_offset_mask_reg = 0, dma_write_block_dma_offset_mask_next;
reg [DMA_ADDR_WIDTH-1:0] dma_write_block_dma_stride_reg = 0, dma_write_block_dma_stride_next;
reg [RAM_ADDR_WIDTH-1:0] dma_write_block_ram_base_addr_reg = 0, dma_write_block_ram_base_addr_next;
reg [RAM_ADDR_WIDTH-1:0] dma_write_block_ram_offset_reg = 0, dma_write_block_ram_offset_next;
reg [RAM_ADDR_WIDTH-1:0] dma_write_block_ram_offset_mask_reg = 0, dma_write_block_ram_offset_mask_next;
reg [RAM_ADDR_WIDTH-1:0] dma_write_block_ram_stride_reg = 0, dma_write_block_ram_stride_next;
assign axil_csr_awready = axil_csr_awready_reg;
assign axil_csr_wready = axil_csr_wready_reg;
assign axil_csr_bresp = axil_csr_bresp_reg;
assign axil_csr_bvalid = axil_csr_bvalid_reg;
assign axil_csr_arready = axil_csr_arready_reg;
assign axil_csr_rdata = axil_csr_rdata_reg;
assign axil_csr_rresp = axil_csr_rresp_reg;
assign axil_csr_rvalid = axil_csr_rvalid_reg;
assign m_axis_dma_read_desc_dma_addr = dma_read_desc_dma_addr_reg;
assign m_axis_dma_read_desc_ram_sel = 0;
assign m_axis_dma_read_desc_ram_addr = dma_read_desc_ram_addr_reg;
assign m_axis_dma_read_desc_len = dma_read_desc_len_reg;
assign m_axis_dma_read_desc_tag = dma_read_desc_tag_reg;
assign m_axis_dma_read_desc_valid = dma_read_desc_valid_reg;
assign m_axis_dma_write_desc_dma_addr = dma_write_desc_dma_addr_reg;
assign m_axis_dma_write_desc_ram_sel = 0;
assign m_axis_dma_write_desc_ram_addr = dma_write_desc_ram_addr_imm_reg;
assign m_axis_dma_write_desc_imm = dma_write_desc_ram_addr_imm_reg;
assign m_axis_dma_write_desc_imm_en = dma_write_desc_imm_en_reg;
assign m_axis_dma_write_desc_len = dma_write_desc_len_reg;
assign m_axis_dma_write_desc_tag = dma_write_desc_tag_reg;
assign m_axis_dma_write_desc_valid = dma_write_desc_valid_reg;
assign msi_irq[0] = (s_axis_dma_read_desc_status_valid && dma_rd_int_en_reg) || (s_axis_dma_write_desc_status_valid && dma_wr_int_en_reg);
assign msi_irq[31:1] = 31'd0;
always @* begin
axil_csr_awready_next = 1'b0;
axil_csr_wready_next = 1'b0;
axil_csr_bresp_next = 2'b00;
axil_csr_bvalid_next = axil_csr_bvalid_reg && !axil_csr_bready;
axil_csr_arready_next = 1'b0;
axil_csr_rdata_next = axil_csr_rdata_reg;
axil_csr_rresp_next = 2'b00;
axil_csr_rvalid_next = axil_csr_rvalid_reg && !axil_csr_rready;
dma_read_desc_dma_addr_next = dma_read_desc_dma_addr_reg;
dma_read_desc_ram_addr_next = dma_read_desc_ram_addr_reg;
dma_read_desc_len_next = dma_read_desc_len_reg;
dma_read_desc_tag_next = dma_read_desc_tag_reg;
dma_read_desc_valid_next = dma_read_desc_valid_reg && !m_axis_dma_read_desc_ready;
dma_read_desc_status_tag_next = dma_read_desc_status_tag_reg;
dma_read_desc_status_error_next = dma_read_desc_status_error_reg;
dma_read_desc_status_valid_next = dma_read_desc_status_valid_reg;
dma_write_desc_dma_addr_next = dma_write_desc_dma_addr_reg;
dma_write_desc_ram_addr_imm_next = dma_write_desc_ram_addr_imm_reg;
dma_write_desc_imm_en_next = dma_write_desc_imm_en_reg;
dma_write_desc_len_next = dma_write_desc_len_reg;
dma_write_desc_tag_next = dma_write_desc_tag_reg;
dma_write_desc_valid_next = dma_write_desc_valid_reg && !m_axis_dma_write_desc_ready;
dma_write_desc_status_tag_next = dma_write_desc_status_tag_reg;
dma_write_desc_status_error_next = dma_write_desc_status_error_reg;
dma_write_desc_status_valid_next = dma_write_desc_status_valid_reg;
dma_enable_next = dma_enable_reg;
dma_rd_int_en_next = dma_rd_int_en_reg;
dma_wr_int_en_next = dma_wr_int_en_reg;
dma_read_block_run_next = dma_read_block_run_reg;
dma_read_block_len_next = dma_read_block_len_reg;
dma_read_block_count_next = dma_read_block_count_reg;
dma_read_block_cycle_count_next = dma_read_block_cycle_count_reg;
dma_read_block_dma_base_addr_next = dma_read_block_dma_base_addr_reg;
dma_read_block_dma_offset_next = dma_read_block_dma_offset_reg;
dma_read_block_dma_offset_mask_next = dma_read_block_dma_offset_mask_reg;
dma_read_block_dma_stride_next = dma_read_block_dma_stride_reg;
dma_read_block_ram_base_addr_next = dma_read_block_ram_base_addr_reg;
dma_read_block_ram_offset_next = dma_read_block_ram_offset_reg;
dma_read_block_ram_offset_mask_next = dma_read_block_ram_offset_mask_reg;
dma_read_block_ram_stride_next = dma_read_block_ram_stride_reg;
dma_write_block_run_next = dma_write_block_run_reg;
dma_write_block_len_next = dma_write_block_len_reg;
dma_write_block_count_next = dma_write_block_count_reg;
dma_write_block_cycle_count_next = dma_write_block_cycle_count_reg;
dma_write_block_dma_base_addr_next = dma_write_block_dma_base_addr_reg;
dma_write_block_dma_offset_next = dma_write_block_dma_offset_reg;
dma_write_block_dma_offset_mask_next = dma_write_block_dma_offset_mask_reg;
dma_write_block_dma_stride_next = dma_write_block_dma_stride_reg;
dma_write_block_ram_base_addr_next = dma_write_block_ram_base_addr_reg;
dma_write_block_ram_offset_next = dma_write_block_ram_offset_reg;
dma_write_block_ram_offset_mask_next = dma_write_block_ram_offset_mask_reg;
dma_write_block_ram_stride_next = dma_write_block_ram_stride_reg;
if (axil_csr_awvalid && axil_csr_wvalid && !axil_csr_bvalid_reg) begin
// write operation
axil_csr_awready_next = 1'b1;
axil_csr_wready_next = 1'b1;
axil_csr_bresp_next = 2'b00;
axil_csr_bvalid_next = 1'b1;
case ({axil_csr_awaddr[15:2], 2'b00})
// control
16'h0000: begin
dma_enable_next = axil_csr_wdata[0];
end
16'h0008: begin
dma_rd_int_en_next = axil_csr_wdata[0];
dma_wr_int_en_next = axil_csr_wdata[1];
end
// single read
16'h0100: dma_read_desc_dma_addr_next[31:0] = axil_csr_wdata;
16'h0104: dma_read_desc_dma_addr_next[63:32] = axil_csr_wdata;
16'h0108: dma_read_desc_ram_addr_next = axil_csr_wdata;
16'h0110: dma_read_desc_len_next = axil_csr_wdata;
16'h0114: begin
dma_read_desc_tag_next = axil_csr_wdata;
dma_read_desc_valid_next = 1'b1;
end
// single write
16'h0200: dma_write_desc_dma_addr_next[31:0] = axil_csr_wdata;
16'h0204: dma_write_desc_dma_addr_next[63:32] = axil_csr_wdata;
16'h0208: dma_write_desc_ram_addr_imm_next = axil_csr_wdata;
16'h0210: dma_write_desc_len_next = axil_csr_wdata;
16'h0214: begin
dma_write_desc_tag_next = axil_csr_wdata[23:0];
dma_write_desc_imm_en_next = axil_csr_wdata[31];
dma_write_desc_valid_next = 1'b1;
end
// block read
16'h1000: begin
dma_read_block_run_next = axil_csr_wdata[0];
end
16'h1008: dma_read_block_cycle_count_next[31:0] = axil_csr_wdata;
16'h100c: dma_read_block_cycle_count_next[63:32] = axil_csr_wdata;
16'h1010: dma_read_block_len_next = axil_csr_wdata;
16'h1018: dma_read_block_count_next[31:0] = axil_csr_wdata;
16'h1080: dma_read_block_dma_base_addr_next[31:0] = axil_csr_wdata;
16'h1084: dma_read_block_dma_base_addr_next[63:32] = axil_csr_wdata;
16'h1088: dma_read_block_dma_offset_next[31:0] = axil_csr_wdata;
16'h108c: dma_read_block_dma_offset_next[63:32] = axil_csr_wdata;
16'h1090: dma_read_block_dma_offset_mask_next[31:0] = axil_csr_wdata;
16'h1094: dma_read_block_dma_offset_mask_next[63:32] = axil_csr_wdata;
16'h1098: dma_read_block_dma_stride_next[31:0] = axil_csr_wdata;
16'h109c: dma_read_block_dma_stride_next[63:32] = axil_csr_wdata;
16'h10c0: dma_read_block_ram_base_addr_next = axil_csr_wdata;
16'h10c8: dma_read_block_ram_offset_next = axil_csr_wdata;
16'h10d0: dma_read_block_ram_offset_mask_next = axil_csr_wdata;
16'h10d8: dma_read_block_ram_stride_next = axil_csr_wdata;
// block write
16'h1100: begin
dma_write_block_run_next = axil_csr_wdata[0];
end
16'h1108: dma_write_block_cycle_count_next[31:0] = axil_csr_wdata;
16'h110c: dma_write_block_cycle_count_next[63:32] = axil_csr_wdata;
16'h1110: dma_write_block_len_next = axil_csr_wdata;
16'h1118: dma_write_block_count_next[31:0] = axil_csr_wdata;
16'h1180: dma_write_block_dma_base_addr_next[31:0] = axil_csr_wdata;
16'h1184: dma_write_block_dma_base_addr_next[63:32] = axil_csr_wdata;
16'h1188: dma_write_block_dma_offset_next[31:0] = axil_csr_wdata;
16'h118c: dma_write_block_dma_offset_next[63:32] = axil_csr_wdata;
16'h1190: dma_write_block_dma_offset_mask_next[31:0] = axil_csr_wdata;
16'h1194: dma_write_block_dma_offset_mask_next[63:32] = axil_csr_wdata;
16'h1198: dma_write_block_dma_stride_next[31:0] = axil_csr_wdata;
16'h119c: dma_write_block_dma_stride_next[63:32] = axil_csr_wdata;
16'h11c0: dma_write_block_ram_base_addr_next = axil_csr_wdata;
16'h11c8: dma_write_block_ram_offset_next = axil_csr_wdata;
16'h11d0: dma_write_block_ram_offset_mask_next = axil_csr_wdata;
16'h11d8: dma_write_block_ram_stride_next = axil_csr_wdata;
endcase
end
if (axil_csr_arvalid && !axil_csr_rvalid_reg) begin
// read operation
axil_csr_arready_next = 1'b1;
axil_csr_rresp_next = 2'b00;
axil_csr_rdata_next = 32'd0;
axil_csr_rvalid_next = 1'b1;
case ({axil_csr_araddr[15:2], 2'b00})
// control
16'h0000: begin
axil_csr_rdata_next[0] = dma_enable_reg;
end
16'h0008: begin
axil_csr_rdata_next[0] = dma_rd_int_en_reg;
axil_csr_rdata_next[1] = dma_wr_int_en_reg;
end
16'h0010: axil_csr_rdata_next = cycle_count_reg;
16'h0014: axil_csr_rdata_next = cycle_count_reg >> 32;
16'h0020: axil_csr_rdata_next = dma_read_active_count_reg;
16'h0028: axil_csr_rdata_next = dma_write_active_count_reg;
// single read
16'h0100: axil_csr_rdata_next = dma_read_desc_dma_addr_reg;
16'h0104: axil_csr_rdata_next = dma_read_desc_dma_addr_reg >> 32;
16'h0108: axil_csr_rdata_next = dma_read_desc_ram_addr_reg;
16'h010c: axil_csr_rdata_next = dma_read_desc_ram_addr_reg >> 32;
16'h0110: axil_csr_rdata_next = dma_read_desc_len_reg;
16'h0114: axil_csr_rdata_next = dma_read_desc_tag_reg;
16'h0118: begin
axil_csr_rdata_next[15:0] = dma_read_desc_status_tag_reg;
axil_csr_rdata_next[27:24] = dma_read_desc_status_error_reg;
axil_csr_rdata_next[31] = dma_read_desc_status_valid_reg;
dma_read_desc_status_valid_next = 1'b0;
end
// single write
16'h0200: axil_csr_rdata_next = dma_write_desc_dma_addr_reg;
16'h0204: axil_csr_rdata_next = dma_write_desc_dma_addr_reg >> 32;
16'h0208: axil_csr_rdata_next = dma_write_desc_ram_addr_imm_reg;
16'h020c: axil_csr_rdata_next = dma_write_desc_ram_addr_imm_reg >> 32;
16'h0210: axil_csr_rdata_next = dma_write_desc_len_reg;
16'h0214: begin
axil_csr_rdata_next[23:0] = dma_write_desc_tag_reg;
axil_csr_rdata_next[31] = dma_write_desc_imm_en_reg;
end
16'h0218: begin
axil_csr_rdata_next[15:0] = dma_write_desc_status_tag_reg;
axil_csr_rdata_next[27:24] = dma_write_desc_status_error_reg;
axil_csr_rdata_next[31] = dma_write_desc_status_valid_reg;
dma_write_desc_status_valid_next = 1'b0;
end
// block read
16'h1000: begin
axil_csr_rdata_next[0] = dma_read_block_run_reg;
end
16'h1008: axil_csr_rdata_next = dma_read_block_cycle_count_reg;
16'h100c: axil_csr_rdata_next = dma_read_block_cycle_count_reg >> 32;
16'h1010: axil_csr_rdata_next = dma_read_block_len_reg;
16'h1018: axil_csr_rdata_next = dma_read_block_count_reg;
16'h101c: axil_csr_rdata_next = dma_read_block_count_reg >> 32;
16'h1080: axil_csr_rdata_next = dma_read_block_dma_base_addr_reg;
16'h1084: axil_csr_rdata_next = dma_read_block_dma_base_addr_reg >> 32;
16'h1088: axil_csr_rdata_next = dma_read_block_dma_offset_reg;
16'h108c: axil_csr_rdata_next = dma_read_block_dma_offset_reg >> 32;
16'h1090: axil_csr_rdata_next = dma_read_block_dma_offset_mask_reg;
16'h1094: axil_csr_rdata_next = dma_read_block_dma_offset_mask_reg >> 32;
16'h1098: axil_csr_rdata_next = dma_read_block_dma_stride_reg;
16'h109c: axil_csr_rdata_next = dma_read_block_dma_stride_reg >> 32;
16'h10c0: axil_csr_rdata_next = dma_read_block_ram_base_addr_reg;
16'h10c4: axil_csr_rdata_next = dma_read_block_ram_base_addr_reg >> 32;
16'h10c8: axil_csr_rdata_next = dma_read_block_ram_offset_reg;
16'h10cc: axil_csr_rdata_next = dma_read_block_ram_offset_reg >> 32;
16'h10d0: axil_csr_rdata_next = dma_read_block_ram_offset_mask_reg;
16'h10d4: axil_csr_rdata_next = dma_read_block_ram_offset_mask_reg >> 32;
16'h10d8: axil_csr_rdata_next = dma_read_block_ram_stride_reg;
16'h10dc: axil_csr_rdata_next = dma_read_block_ram_stride_reg >> 32;
// block write
16'h1100: begin
axil_csr_rdata_next[0] = dma_write_block_run_reg;
end
16'h1108: axil_csr_rdata_next = dma_write_block_cycle_count_reg;
16'h110c: axil_csr_rdata_next = dma_write_block_cycle_count_reg >> 32;
16'h1110: axil_csr_rdata_next = dma_write_block_len_reg;
16'h1118: axil_csr_rdata_next = dma_write_block_count_reg;
16'h111c: axil_csr_rdata_next = dma_write_block_count_reg >> 32;
16'h1180: axil_csr_rdata_next = dma_write_block_dma_base_addr_reg;
16'h1184: axil_csr_rdata_next = dma_write_block_dma_base_addr_reg >> 32;
16'h1188: axil_csr_rdata_next = dma_write_block_dma_offset_reg;
16'h118c: axil_csr_rdata_next = dma_write_block_dma_offset_reg >> 32;
16'h1190: axil_csr_rdata_next = dma_write_block_dma_offset_mask_reg;
16'h1194: axil_csr_rdata_next = dma_write_block_dma_offset_mask_reg >> 32;
16'h1198: axil_csr_rdata_next = dma_write_block_dma_stride_reg;
16'h119c: axil_csr_rdata_next = dma_write_block_dma_stride_reg >> 32;
16'h11c0: axil_csr_rdata_next = dma_write_block_ram_base_addr_reg;
16'h11c4: axil_csr_rdata_next = dma_write_block_ram_base_addr_reg >> 32;
16'h11c8: axil_csr_rdata_next = dma_write_block_ram_offset_reg;
16'h11cc: axil_csr_rdata_next = dma_write_block_ram_offset_reg >> 32;
16'h11d0: axil_csr_rdata_next = dma_write_block_ram_offset_mask_reg;
16'h11d4: axil_csr_rdata_next = dma_write_block_ram_offset_mask_reg >> 32;
16'h11d8: axil_csr_rdata_next = dma_write_block_ram_stride_reg;
16'h11dc: axil_csr_rdata_next = dma_write_block_ram_stride_reg >> 32;
endcase
end
// store read response
if (s_axis_dma_read_desc_status_valid) begin
dma_read_desc_status_tag_next = s_axis_dma_read_desc_status_tag;
dma_read_desc_status_error_next = s_axis_dma_read_desc_status_error;
dma_read_desc_status_valid_next = s_axis_dma_read_desc_status_valid;
end
// store write response
if (s_axis_dma_write_desc_status_valid) begin
dma_write_desc_status_tag_next = s_axis_dma_write_desc_status_tag;
dma_write_desc_status_error_next = s_axis_dma_write_desc_status_error;
dma_write_desc_status_valid_next = s_axis_dma_write_desc_status_valid;
end
// block read
if (dma_read_block_run_reg) begin
dma_read_block_cycle_count_next = dma_read_block_cycle_count_reg + 1;
if (dma_read_block_count_reg == 0) begin
if (dma_read_active_count_reg == 0) begin
dma_read_block_run_next = 1'b0;
end
end else begin
if (!dma_read_desc_valid_reg || m_axis_dma_read_desc_ready) begin
dma_read_block_dma_offset_next = dma_read_block_dma_offset_reg + dma_read_block_dma_stride_reg;
dma_read_desc_dma_addr_next = dma_read_block_dma_base_addr_reg + (dma_read_block_dma_offset_reg & dma_read_block_dma_offset_mask_reg);
dma_read_block_ram_offset_next = dma_read_block_ram_offset_reg + dma_read_block_ram_stride_reg;
dma_read_desc_ram_addr_next = dma_read_block_ram_base_addr_reg + (dma_read_block_ram_offset_reg & dma_read_block_ram_offset_mask_reg);
dma_read_desc_len_next = dma_read_block_len_reg;
dma_read_block_count_next = dma_read_block_count_reg - 1;
dma_read_desc_tag_next = dma_read_block_count_reg;
dma_read_desc_valid_next = 1'b1;
end
end
end
// block write
if (dma_write_block_run_reg) begin
dma_write_block_cycle_count_next = dma_write_block_cycle_count_reg + 1;
if (dma_write_block_count_reg == 0) begin
if (dma_write_active_count_reg == 0) begin
dma_write_block_run_next = 1'b0;
end
end else begin
if (!dma_write_desc_valid_reg || m_axis_dma_write_desc_ready) begin
dma_write_block_dma_offset_next = dma_write_block_dma_offset_reg + dma_write_block_dma_stride_reg;
dma_write_desc_dma_addr_next = dma_write_block_dma_base_addr_reg + (dma_write_block_dma_offset_reg & dma_write_block_dma_offset_mask_reg);
dma_write_block_ram_offset_next = dma_write_block_ram_offset_reg + dma_write_block_ram_stride_reg;
dma_write_desc_ram_addr_imm_next = dma_write_block_ram_base_addr_reg + (dma_write_block_ram_offset_reg & dma_write_block_ram_offset_mask_reg);
dma_write_desc_imm_en_next = 1'b0;
dma_write_desc_len_next = dma_write_block_len_reg;
dma_write_block_count_next = dma_write_block_count_reg - 1;
dma_write_desc_tag_next = dma_write_block_count_reg;
dma_write_desc_valid_next = 1'b1;
end
end
end
end
always @(posedge clk) begin
axil_csr_awready_reg <= axil_csr_awready_next;
axil_csr_wready_reg <= axil_csr_wready_next;
axil_csr_bresp_reg <= axil_csr_bresp_next;
axil_csr_bvalid_reg <= axil_csr_bvalid_next;
axil_csr_arready_reg <= axil_csr_arready_next;
axil_csr_rdata_reg <= axil_csr_rdata_next;
axil_csr_rresp_reg <= axil_csr_rresp_next;
axil_csr_rvalid_reg <= axil_csr_rvalid_next;
cycle_count_reg <= cycle_count_reg + 1;
dma_read_active_count_reg <= dma_read_active_count_reg
+ (m_axis_dma_read_desc_valid && m_axis_dma_read_desc_ready)
- s_axis_dma_read_desc_status_valid;
dma_write_active_count_reg <= dma_write_active_count_reg
+ (m_axis_dma_write_desc_valid && m_axis_dma_write_desc_ready)
- s_axis_dma_write_desc_status_valid;
dma_read_desc_dma_addr_reg <= dma_read_desc_dma_addr_next;
dma_read_desc_ram_addr_reg <= dma_read_desc_ram_addr_next;
dma_read_desc_len_reg <= dma_read_desc_len_next;
dma_read_desc_tag_reg <= dma_read_desc_tag_next;
dma_read_desc_valid_reg <= dma_read_desc_valid_next;
dma_read_desc_status_tag_reg <= dma_read_desc_status_tag_next;
dma_read_desc_status_error_reg <= dma_read_desc_status_error_next;
dma_read_desc_status_valid_reg <= dma_read_desc_status_valid_next;
dma_write_desc_dma_addr_reg <= dma_write_desc_dma_addr_next;
dma_write_desc_ram_addr_imm_reg <= dma_write_desc_ram_addr_imm_next;
dma_write_desc_imm_en_reg <= dma_write_desc_imm_en_next;
dma_write_desc_len_reg <= dma_write_desc_len_next;
dma_write_desc_tag_reg <= dma_write_desc_tag_next;
dma_write_desc_valid_reg <= dma_write_desc_valid_next;
dma_write_desc_status_tag_reg <= dma_write_desc_status_tag_next;
dma_write_desc_status_error_reg <= dma_write_desc_status_error_next;
dma_write_desc_status_valid_reg <= dma_write_desc_status_valid_next;
dma_enable_reg <= dma_enable_next;
dma_rd_int_en_reg <= dma_rd_int_en_next;
dma_wr_int_en_reg <= dma_wr_int_en_next;
dma_read_block_run_reg <= dma_read_block_run_next;
dma_read_block_len_reg <= dma_read_block_len_next;
dma_read_block_count_reg <= dma_read_block_count_next;
dma_read_block_cycle_count_reg <= dma_read_block_cycle_count_next;
dma_read_block_dma_base_addr_reg <= dma_read_block_dma_base_addr_next;
dma_read_block_dma_offset_reg <= dma_read_block_dma_offset_next;
dma_read_block_dma_offset_mask_reg <= dma_read_block_dma_offset_mask_next;
dma_read_block_dma_stride_reg <= dma_read_block_dma_stride_next;
dma_read_block_ram_base_addr_reg <= dma_read_block_ram_base_addr_next;
dma_read_block_ram_offset_reg <= dma_read_block_ram_offset_next;
dma_read_block_ram_offset_mask_reg <= dma_read_block_ram_offset_mask_next;
dma_read_block_ram_stride_reg <= dma_read_block_ram_stride_next;
dma_write_block_run_reg <= dma_write_block_run_next;
dma_write_block_len_reg <= dma_write_block_len_next;
dma_write_block_count_reg <= dma_write_block_count_next;
dma_write_block_cycle_count_reg <= dma_write_block_cycle_count_next;
dma_write_block_dma_base_addr_reg <= dma_write_block_dma_base_addr_next;
dma_write_block_dma_offset_reg <= dma_write_block_dma_offset_next;
dma_write_block_dma_offset_mask_reg <= dma_write_block_dma_offset_mask_next;
dma_write_block_dma_stride_reg <= dma_write_block_dma_stride_next;
dma_write_block_ram_base_addr_reg <= dma_write_block_ram_base_addr_next;
dma_write_block_ram_offset_reg <= dma_write_block_ram_offset_next;
dma_write_block_ram_offset_mask_reg <= dma_write_block_ram_offset_mask_next;
dma_write_block_ram_stride_reg <= dma_write_block_ram_stride_next;
if (rst) begin
axil_csr_awready_reg <= 1'b0;
axil_csr_wready_reg <= 1'b0;
axil_csr_bvalid_reg <= 1'b0;
axil_csr_arready_reg <= 1'b0;
axil_csr_rvalid_reg <= 1'b0;
cycle_count_reg <= 0;
dma_read_active_count_reg <= 0;
dma_write_active_count_reg <= 0;
dma_read_desc_valid_reg <= 1'b0;
dma_read_desc_status_valid_reg <= 1'b0;
dma_write_desc_valid_reg <= 1'b0;
dma_write_desc_status_valid_reg <= 1'b0;
dma_enable_reg <= 1'b0;
dma_rd_int_en_reg <= 1'b0;
dma_wr_int_en_reg <= 1'b0;
dma_read_block_run_reg <= 1'b0;
dma_write_block_run_reg <= 1'b0;
end
end
dma_psdpram #(
.SIZE(16384),
.SEG_COUNT(RAM_SEG_COUNT),
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.PIPELINE(2)
)
dma_ram_inst (
.clk(clk),
.rst(rst),
/*
* Write port
*/
.wr_cmd_be(ram_wr_cmd_be),
.wr_cmd_addr(ram_wr_cmd_addr),
.wr_cmd_data(ram_wr_cmd_data),
.wr_cmd_valid(ram_wr_cmd_valid),
.wr_cmd_ready(ram_wr_cmd_ready),
.wr_done(ram_wr_done),
/*
* Read port
*/
.rd_cmd_addr(ram_rd_cmd_addr),
.rd_cmd_valid(ram_rd_cmd_valid),
.rd_cmd_ready(ram_rd_cmd_ready),
.rd_resp_data(ram_rd_resp_data),
.rd_resp_valid(ram_rd_resp_valid),
.rd_resp_ready(ram_rd_resp_ready)
);
stats_counter #(
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH),
.STAT_COUNT_WIDTH(64),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH)
)
stats_counter_inst (
.clk(clk),
.rst(rst),
/*
* Statistics increment input
*/
.s_axis_stat_tdata(s_axis_stat_tdata),
.s_axis_stat_tid(s_axis_stat_tid),
.s_axis_stat_tvalid(s_axis_stat_tvalid),
.s_axis_stat_tready(s_axis_stat_tready),
/*
* AXI Lite register interface
*/
.s_axil_awaddr(axil_stats_awaddr),
.s_axil_awprot(axil_stats_awprot),
.s_axil_awvalid(axil_stats_awvalid),
.s_axil_awready(axil_stats_awready),
.s_axil_wdata(axil_stats_wdata),
.s_axil_wstrb(axil_stats_wstrb),
.s_axil_wvalid(axil_stats_wvalid),
.s_axil_wready(axil_stats_wready),
.s_axil_bresp(axil_stats_bresp),
.s_axil_bvalid(axil_stats_bvalid),
.s_axil_bready(axil_stats_bready),
.s_axil_araddr(axil_stats_araddr),
.s_axil_arprot(axil_stats_arprot),
.s_axil_arvalid(axil_stats_arvalid),
.s_axil_arready(axil_stats_arready),
.s_axil_rdata(axil_stats_rdata),
.s_axil_rresp(axil_stats_rresp),
.s_axil_rvalid(axil_stats_rvalid),
.s_axil_rready(axil_stats_rready)
);
endmodule |
module dma_bench_pcie #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 5,
// TX sequence number tracking enable
parameter TX_SEQ_NUM_ENABLE = 0,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Immediate enable
parameter IMM_ENABLE = 1,
// Immediate width
parameter IMM_WIDTH = 32,
// Operation table size (read)
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter PCIE_DMA_READ_TX_FC_ENABLE = 0,
// Operation table size (write)
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 0,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0,
// Requester ID mash
parameter CHECK_BUS_NUMBER = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* TLP input (completion)
*/
input wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
output wire rx_cpl_tlp_ready,
/*
* TLP output (read request)
*/
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
input wire tx_rd_req_tlp_ready,
/*
* TLP output (write request)
*/
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
input wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number input
*/
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_rd_req_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_rd_req_tx_seq_num_valid,
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_wr_req_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_wr_req_tx_seq_num_valid,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_ph_av,
input wire [11:0] pcie_tx_fc_pd_av,
input wire [7:0] pcie_tx_fc_nph_av,
/*
* Configuration
*/
input wire [7:0] bus_num,
input wire ext_tag_enable,
input wire [2:0] max_read_request_size,
input wire [2:0] max_payload_size,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor,
/*
* MSI request outputs
*/
output wire [31:0] msi_irq
);
parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_ADDR_WIDTH = BAR0_APERTURE;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter RAM_SEL_WIDTH = 2;
parameter RAM_ADDR_WIDTH = 16;
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
parameter RAM_SEG_DATA_WIDTH = TLP_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH);
parameter PCIE_ADDR_WIDTH = 64;
parameter DMA_LEN_WIDTH = 16;
parameter DMA_TAG_WIDTH = 8;
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
wire [2:0] axil_ctrl_awprot;
wire axil_ctrl_awvalid;
wire axil_ctrl_awready;
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
wire axil_ctrl_wvalid;
wire axil_ctrl_wready;
wire [1:0] axil_ctrl_bresp;
wire axil_ctrl_bvalid;
wire axil_ctrl_bready;
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
wire [2:0] axil_ctrl_arprot;
wire axil_ctrl_arvalid;
wire axil_ctrl_arready;
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
wire [1:0] axil_ctrl_rresp;
wire axil_ctrl_rvalid;
wire axil_ctrl_rready;
wire [PCIE_ADDR_WIDTH-1:0] axis_dma_read_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] axis_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] axis_dma_read_desc_ram_addr;
wire [DMA_LEN_WIDTH-1:0] axis_dma_read_desc_len;
wire [DMA_TAG_WIDTH-1:0] axis_dma_read_desc_tag;
wire axis_dma_read_desc_valid;
wire axis_dma_read_desc_ready;
wire [DMA_TAG_WIDTH-1:0] axis_dma_read_desc_status_tag;
wire [3:0] axis_dma_read_desc_status_error;
wire axis_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] axis_dma_write_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] axis_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] axis_dma_write_desc_ram_addr;
wire [IMM_WIDTH-1:0] axis_dma_write_desc_imm;
wire axis_dma_write_desc_imm_en;
wire [DMA_LEN_WIDTH-1:0] axis_dma_write_desc_len;
wire [DMA_TAG_WIDTH-1:0] axis_dma_write_desc_tag;
wire axis_dma_write_desc_valid;
wire axis_dma_write_desc_ready;
wire [DMA_TAG_WIDTH-1:0] axis_dma_write_desc_status_tag;
wire [3:0] axis_dma_write_desc_status_error;
wire axis_dma_write_desc_status_valid;
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid;
wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_ready;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_rd_resp_data;
wire [RAM_SEG_COUNT-1:0] ram_rd_resp_valid;
wire [RAM_SEG_COUNT-1:0] ram_rd_resp_ready;
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready;
wire [RAM_SEG_COUNT-1:0] ram_wr_done;
wire [1:0] status_error_cor_int;
wire [1:0] status_error_uncor_int;
pcie_axil_master #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
)
pcie_axil_master_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(rx_req_tlp_data),
.rx_req_tlp_hdr(rx_req_tlp_hdr),
.rx_req_tlp_valid(rx_req_tlp_valid),
.rx_req_tlp_sop(rx_req_tlp_sop),
.rx_req_tlp_eop(rx_req_tlp_eop),
.rx_req_tlp_ready(rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(tx_cpl_tlp_data),
.tx_cpl_tlp_strb(tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
.m_axil_awaddr(axil_ctrl_awaddr),
.m_axil_awprot(axil_ctrl_awprot),
.m_axil_awvalid(axil_ctrl_awvalid),
.m_axil_awready(axil_ctrl_awready),
.m_axil_wdata(axil_ctrl_wdata),
.m_axil_wstrb(axil_ctrl_wstrb),
.m_axil_wvalid(axil_ctrl_wvalid),
.m_axil_wready(axil_ctrl_wready),
.m_axil_bresp(axil_ctrl_bresp),
.m_axil_bvalid(axil_ctrl_bvalid),
.m_axil_bready(axil_ctrl_bready),
.m_axil_araddr(axil_ctrl_araddr),
.m_axil_arprot(axil_ctrl_arprot),
.m_axil_arvalid(axil_ctrl_arvalid),
.m_axil_arready(axil_ctrl_arready),
.m_axil_rdata(axil_ctrl_rdata),
.m_axil_rresp(axil_ctrl_rresp),
.m_axil_rvalid(axil_ctrl_rvalid),
.m_axil_rready(axil_ctrl_rready),
/*
* Configuration
*/
.completer_id({bus_num, 5'd0, 3'd0}),
/*
* Status
*/
.status_error_cor(status_error_cor_int[0]),
.status_error_uncor(status_error_uncor_int[0])
);
wire [$clog2(PCIE_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag;
wire [DMA_LEN_WIDTH-1:0] stat_rd_op_start_len;
wire stat_rd_op_start_valid;
wire [$clog2(PCIE_DMA_READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag;
wire [3:0] stat_rd_op_finish_status;
wire stat_rd_op_finish_valid;
wire [$clog2(PCIE_TAG_COUNT)-1:0] stat_rd_req_start_tag;
wire [12:0] stat_rd_req_start_len;
wire stat_rd_req_start_valid;
wire [$clog2(PCIE_TAG_COUNT)-1:0] stat_rd_req_finish_tag;
wire [3:0] stat_rd_req_finish_status;
wire stat_rd_req_finish_valid;
wire stat_rd_req_timeout;
wire stat_rd_op_table_full;
wire stat_rd_no_tags;
wire stat_rd_tx_no_credit;
wire stat_rd_tx_limit;
wire stat_rd_tx_stall;
wire [$clog2(PCIE_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag;
wire [DMA_LEN_WIDTH-1:0] stat_wr_op_start_len;
wire stat_wr_op_start_valid;
wire [$clog2(PCIE_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag;
wire [3:0] stat_wr_op_finish_status;
wire stat_wr_op_finish_valid;
wire [$clog2(PCIE_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag;
wire [12:0] stat_wr_req_start_len;
wire stat_wr_req_start_valid;
wire [$clog2(PCIE_DMA_WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag;
wire [3:0] stat_wr_req_finish_status;
wire stat_wr_req_finish_valid;
wire stat_wr_op_table_full;
wire stat_wr_tx_no_credit;
wire stat_wr_tx_limit;
wire stat_wr_tx_stall;
dma_if_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(DMA_LEN_WIDTH),
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
.CHECK_BUS_NUMBER(CHECK_BUS_NUMBER)
)
dma_if_pcie_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (completion)
*/
.rx_cpl_tlp_data(rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(rx_cpl_tlp_error),
.rx_cpl_tlp_valid(rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(rx_cpl_tlp_ready),
/*
* TLP output (read request)
*/
.tx_rd_req_tlp_hdr(tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rd_req_tx_seq_num(s_axis_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(s_axis_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(s_axis_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(s_axis_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(axis_dma_read_desc_dma_addr),
.s_axis_read_desc_ram_sel(axis_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(axis_dma_read_desc_ram_addr),
.s_axis_read_desc_len(axis_dma_read_desc_len),
.s_axis_read_desc_tag(axis_dma_read_desc_tag),
.s_axis_read_desc_valid(axis_dma_read_desc_valid),
.s_axis_read_desc_ready(axis_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(axis_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(axis_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(axis_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(axis_dma_write_desc_dma_addr),
.s_axis_write_desc_ram_sel(axis_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(axis_dma_write_desc_ram_addr),
.s_axis_write_desc_imm(axis_dma_write_desc_imm),
.s_axis_write_desc_imm_en(axis_dma_write_desc_imm_en),
.s_axis_write_desc_len(axis_dma_write_desc_len),
.s_axis_write_desc_tag(axis_dma_write_desc_tag),
.s_axis_write_desc_valid(axis_dma_write_desc_valid),
.s_axis_write_desc_ready(axis_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(axis_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(axis_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(axis_dma_write_desc_status_valid),
/*
* RAM interface
*/
.ram_rd_cmd_sel(ram_rd_cmd_sel),
.ram_rd_cmd_addr(ram_rd_cmd_addr),
.ram_rd_cmd_valid(ram_rd_cmd_valid),
.ram_rd_cmd_ready(ram_rd_cmd_ready),
.ram_rd_resp_data(ram_rd_resp_data),
.ram_rd_resp_valid(ram_rd_resp_valid),
.ram_rd_resp_ready(ram_rd_resp_ready),
.ram_wr_cmd_sel(ram_wr_cmd_sel),
.ram_wr_cmd_be(ram_wr_cmd_be),
.ram_wr_cmd_addr(ram_wr_cmd_addr),
.ram_wr_cmd_data(ram_wr_cmd_data),
.ram_wr_cmd_valid(ram_wr_cmd_valid),
.ram_wr_cmd_ready(ram_wr_cmd_ready),
.ram_wr_done(ram_wr_done),
/*
* Configuration
*/
.read_enable(1'b1),
.write_enable(1'b1),
.ext_tag_enable(ext_tag_enable),
.requester_id({bus_num, 5'd0, 3'd0}),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
/*
* Status
*/
.status_error_cor(status_error_cor_int[1]),
.status_error_uncor(status_error_uncor_int[1]),
/*
* Statistics
*/
.stat_rd_op_start_tag(stat_rd_op_start_tag),
.stat_rd_op_start_len(stat_rd_op_start_len),
.stat_rd_op_start_valid(stat_rd_op_start_valid),
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
.stat_rd_op_finish_status(stat_rd_op_finish_status),
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
.stat_rd_req_start_tag(stat_rd_req_start_tag),
.stat_rd_req_start_len(stat_rd_req_start_len),
.stat_rd_req_start_valid(stat_rd_req_start_valid),
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
.stat_rd_req_finish_status(stat_rd_req_finish_status),
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
.stat_rd_req_timeout(stat_rd_req_timeout),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_no_tags(stat_rd_no_tags),
.stat_rd_tx_no_credit(stat_rd_tx_no_credit),
.stat_rd_tx_limit(stat_rd_tx_limit),
.stat_rd_tx_stall(stat_rd_tx_stall),
.stat_wr_op_start_tag(stat_wr_op_start_tag),
.stat_wr_op_start_len(stat_wr_op_start_len),
.stat_wr_op_start_valid(stat_wr_op_start_valid),
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
.stat_wr_op_finish_status(stat_wr_op_finish_status),
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
.stat_wr_req_start_tag(stat_wr_req_start_tag),
.stat_wr_req_start_len(stat_wr_req_start_len),
.stat_wr_req_start_valid(stat_wr_req_start_valid),
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_no_credit(stat_wr_tx_no_credit),
.stat_wr_tx_limit(stat_wr_tx_limit),
.stat_wr_tx_stall(stat_wr_tx_stall)
);
pulse_merge #(
.INPUT_WIDTH(2),
.COUNT_WIDTH(4)
)
status_error_cor_pm_inst (
.clk(clk),
.rst(rst),
.pulse_in(status_error_cor_int),
.count_out(),
.pulse_out(status_error_cor)
);
pulse_merge #(
.INPUT_WIDTH(2),
.COUNT_WIDTH(4)
)
status_error_uncor_pm_inst (
.clk(clk),
.rst(rst),
.pulse_in(status_error_uncor_int),
.count_out(),
.pulse_out(status_error_uncor)
);
wire [23:0] axis_stat_pcie_tdata;
wire [5:0] axis_stat_pcie_tid;
wire axis_stat_pcie_tvalid;
wire axis_stat_pcie_tready;
stats_pcie_if #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.STAT_INC_WIDTH(24),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(1024)
)
stats_pcie_if_inst (
.clk(clk),
.rst(rst),
/*
* monitor input (request to BAR)
*/
.rx_req_tlp_hdr(rx_req_tlp_hdr),
.rx_req_tlp_valid(rx_req_tlp_valid && rx_req_tlp_ready),
.rx_req_tlp_sop(rx_req_tlp_sop),
.rx_req_tlp_eop(rx_req_tlp_eop),
/*
* monitor input (completion to DMA)
*/
.rx_cpl_tlp_hdr(rx_cpl_tlp_hdr),
.rx_cpl_tlp_valid(rx_cpl_tlp_valid && rx_cpl_tlp_ready),
.rx_cpl_tlp_sop(rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(rx_cpl_tlp_eop),
/*
* monitor input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_valid(tx_rd_req_tlp_valid && tx_rd_req_tlp_ready),
.tx_rd_req_tlp_sop(tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(tx_rd_req_tlp_eop),
/*
* monitor input (write request from DMA)
*/
.tx_wr_req_tlp_hdr(tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_valid(tx_wr_req_tlp_valid && tx_wr_req_tlp_ready),
.tx_wr_req_tlp_sop(tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(tx_wr_req_tlp_eop),
/*
* monitor input (completion from BAR)
*/
.tx_cpl_tlp_hdr(tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(tx_cpl_tlp_valid && tx_cpl_tlp_ready),
.tx_cpl_tlp_sop(tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(tx_cpl_tlp_eop),
/*
* Statistics output
*/
.m_axis_stat_tdata(axis_stat_pcie_tdata),
.m_axis_stat_tid(axis_stat_pcie_tid[4:0]),
.m_axis_stat_tvalid(axis_stat_pcie_tvalid),
.m_axis_stat_tready(axis_stat_pcie_tready),
/*
* Control inputs
*/
.update(1'b0)
);
assign axis_stat_pcie_tid[5] = 0;
wire [23:0] axis_stat_dma_tdata;
wire [5:0] axis_stat_dma_tid;
wire axis_stat_dma_tvalid;
wire axis_stat_dma_tready;
stats_dma_if_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.LEN_WIDTH(DMA_LEN_WIDTH),
.READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.STAT_INC_WIDTH(24),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(1024)
)
stats_dma_if_pcie_inst (
.clk(clk),
.rst(rst),
/*
* Statistics from dma_if_pcie
*/
.stat_rd_op_start_tag(stat_rd_op_start_tag),
.stat_rd_op_start_len(stat_rd_op_start_len),
.stat_rd_op_start_valid(stat_rd_op_start_valid),
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
.stat_rd_op_finish_status(stat_rd_op_finish_status),
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
.stat_rd_req_start_tag(stat_rd_req_start_tag),
.stat_rd_req_start_len(stat_rd_req_start_len),
.stat_rd_req_start_valid(stat_rd_req_start_valid),
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
.stat_rd_req_finish_status(stat_rd_req_finish_status),
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
.stat_rd_req_timeout(stat_rd_req_timeout),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_no_tags(stat_rd_no_tags),
.stat_rd_tx_no_credit(stat_rd_tx_no_credit),
.stat_rd_tx_limit(stat_rd_tx_limit),
.stat_rd_tx_stall(stat_rd_tx_stall),
.stat_wr_op_start_tag(stat_wr_op_start_tag),
.stat_wr_op_start_len(stat_wr_op_start_len),
.stat_wr_op_start_valid(stat_wr_op_start_valid),
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
.stat_wr_op_finish_status(stat_wr_op_finish_status),
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
.stat_wr_req_start_tag(stat_wr_req_start_tag),
.stat_wr_req_start_len(stat_wr_req_start_len),
.stat_wr_req_start_valid(stat_wr_req_start_valid),
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_no_credit(stat_wr_tx_no_credit),
.stat_wr_tx_limit(stat_wr_tx_limit),
.stat_wr_tx_stall(stat_wr_tx_stall),
/*
* Statistics output
*/
.m_axis_stat_tdata(axis_stat_dma_tdata),
.m_axis_stat_tid(axis_stat_dma_tid[4:0]),
.m_axis_stat_tvalid(axis_stat_dma_tvalid),
.m_axis_stat_tready(axis_stat_dma_tready),
/*
* Control inputs
*/
.update(1'b0)
);
assign axis_stat_dma_tid[5] = 1;
wire [23:0] axis_stat_tdata;
wire [5:0] axis_stat_tid;
wire axis_stat_tvalid;
wire axis_stat_tready;
axis_arb_mux #(
.S_COUNT(2),
.DATA_WIDTH(24),
.KEEP_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(6),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LAST_ENABLE(0),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_LSB_HIGH_PRIORITY(1)
)
axis_stat_mux_inst (
.clk(clk),
.rst(rst),
/*
* AXI Stream inputs
*/
.s_axis_tdata({axis_stat_dma_tdata, axis_stat_pcie_tdata}),
.s_axis_tkeep(0),
.s_axis_tvalid({axis_stat_dma_tvalid, axis_stat_pcie_tvalid}),
.s_axis_tready({axis_stat_dma_tready, axis_stat_pcie_tready}),
.s_axis_tlast(0),
.s_axis_tid({axis_stat_dma_tid, axis_stat_pcie_tid}),
.s_axis_tdest(0),
.s_axis_tuser(0),
/*
* AXI Stream output
*/
.m_axis_tdata(axis_stat_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(axis_stat_tvalid),
.m_axis_tready(axis_stat_tready),
.m_axis_tlast(),
.m_axis_tid(axis_stat_tid),
.m_axis_tdest(),
.m_axis_tuser()
);
dma_bench #(
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_IMM_ENABLE(IMM_ENABLE),
.DMA_IMM_WIDTH(IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.STAT_INC_WIDTH(24),
.STAT_ID_WIDTH(6)
)
dma_bench_inst (
.clk(clk),
.rst(rst),
/*
* AXI Lite control interface
*/
.s_axil_ctrl_awaddr(axil_ctrl_awaddr),
.s_axil_ctrl_awprot(axil_ctrl_awprot),
.s_axil_ctrl_awvalid(axil_ctrl_awvalid),
.s_axil_ctrl_awready(axil_ctrl_awready),
.s_axil_ctrl_wdata(axil_ctrl_wdata),
.s_axil_ctrl_wstrb(axil_ctrl_wstrb),
.s_axil_ctrl_wvalid(axil_ctrl_wvalid),
.s_axil_ctrl_wready(axil_ctrl_wready),
.s_axil_ctrl_bresp(axil_ctrl_bresp),
.s_axil_ctrl_bvalid(axil_ctrl_bvalid),
.s_axil_ctrl_bready(axil_ctrl_bready),
.s_axil_ctrl_araddr(axil_ctrl_araddr),
.s_axil_ctrl_arprot(axil_ctrl_arprot),
.s_axil_ctrl_arvalid(axil_ctrl_arvalid),
.s_axil_ctrl_arready(axil_ctrl_arready),
.s_axil_ctrl_rdata(axil_ctrl_rdata),
.s_axil_ctrl_rresp(axil_ctrl_rresp),
.s_axil_ctrl_rvalid(axil_ctrl_rvalid),
.s_axil_ctrl_rready(axil_ctrl_rready),
/*
* AXI read descriptor output
*/
.m_axis_dma_read_desc_dma_addr(axis_dma_read_desc_dma_addr),
.m_axis_dma_read_desc_ram_sel(axis_dma_read_desc_ram_sel),
.m_axis_dma_read_desc_ram_addr(axis_dma_read_desc_ram_addr),
.m_axis_dma_read_desc_len(axis_dma_read_desc_len),
.m_axis_dma_read_desc_tag(axis_dma_read_desc_tag),
.m_axis_dma_read_desc_valid(axis_dma_read_desc_valid),
.m_axis_dma_read_desc_ready(axis_dma_read_desc_ready),
/*
* AXI read descriptor status input
*/
.s_axis_dma_read_desc_status_tag(axis_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(axis_dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(axis_dma_read_desc_status_valid),
/*
* AXI write descriptor output
*/
.m_axis_dma_write_desc_dma_addr(axis_dma_write_desc_dma_addr),
.m_axis_dma_write_desc_ram_sel(axis_dma_write_desc_ram_sel),
.m_axis_dma_write_desc_ram_addr(axis_dma_write_desc_ram_addr),
.m_axis_dma_write_desc_imm(axis_dma_write_desc_imm),
.m_axis_dma_write_desc_imm_en(axis_dma_write_desc_imm_en),
.m_axis_dma_write_desc_len(axis_dma_write_desc_len),
.m_axis_dma_write_desc_tag(axis_dma_write_desc_tag),
.m_axis_dma_write_desc_valid(axis_dma_write_desc_valid),
.m_axis_dma_write_desc_ready(axis_dma_write_desc_ready),
/*
* AXI write descriptor status input
*/
.s_axis_dma_write_desc_status_tag(axis_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(axis_dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(axis_dma_write_desc_status_valid),
/*
* RAM interface
*/
.ram_rd_cmd_sel(ram_rd_cmd_sel),
.ram_rd_cmd_addr(ram_rd_cmd_addr),
.ram_rd_cmd_valid(ram_rd_cmd_valid),
.ram_rd_cmd_ready(ram_rd_cmd_ready),
.ram_rd_resp_data(ram_rd_resp_data),
.ram_rd_resp_valid(ram_rd_resp_valid),
.ram_rd_resp_ready(ram_rd_resp_ready),
.ram_wr_cmd_sel(ram_wr_cmd_sel),
.ram_wr_cmd_be(ram_wr_cmd_be),
.ram_wr_cmd_addr(ram_wr_cmd_addr),
.ram_wr_cmd_data(ram_wr_cmd_data),
.ram_wr_cmd_valid(ram_wr_cmd_valid),
.ram_wr_cmd_ready(ram_wr_cmd_ready),
.ram_wr_done(ram_wr_done),
/*
* MSI request outputs
*/
.msi_irq(msi_irq),
/*
* Statistics input
*/
.s_axis_stat_tdata(axis_stat_tdata),
.s_axis_stat_tid(axis_stat_tid),
.s_axis_stat_tvalid(axis_stat_tvalid),
.s_axis_stat_tready(axis_stat_tready)
);
endmodule |
module stats_collect #
(
// Channel count
parameter COUNT = 8,
// Increment width (bits)
parameter INC_WIDTH = 8,
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 16,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = $clog2(COUNT),
// Statistics counter update period (cycles)
parameter UPDATE_PERIOD = 1024,
// Base ID (ID for first channel)
parameter BASE_ID = 0
)
(
input wire clk,
input wire rst,
/*
* Increment inputs
*/
input wire [INC_WIDTH*COUNT-1:0] stat_inc,
input wire [COUNT-1:0] stat_valid,
/*
* Statistics increment output
*/
output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata,
output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid,
output wire m_axis_stat_tvalid,
input wire m_axis_stat_tready,
/*
* Control inputs
*/
input wire update
);
parameter COUNT_WIDTH = $clog2(COUNT);
parameter PERIOD_COUNT_WIDTH = $clog2(UPDATE_PERIOD-1);
parameter ACC_WIDTH = INC_WIDTH+COUNT_WIDTH+1;
// bus width assertions
initial begin
if (COUNT > 2**STAT_ID_WIDTH) begin
$error("Error: ID width insufficient for channel count (instance %m)");
$finish;
end
if (INC_WIDTH+PERIOD_COUNT_WIDTH > STAT_INC_WIDTH) begin
$warning("Warning: accumulator may overflow before periodic update (instance %m)");
end
end
localparam [1:0]
STATE_READ = 2'd0,
STATE_WRITE = 2'd1;
reg [1:0] state_reg = STATE_READ, state_next;
reg [STAT_INC_WIDTH-1:0] m_axis_stat_tdata_reg = 0, m_axis_stat_tdata_next;
reg [STAT_ID_WIDTH-1:0] m_axis_stat_tid_reg = 0, m_axis_stat_tid_next;
reg m_axis_stat_tvalid_reg = 0, m_axis_stat_tvalid_next;
reg [COUNT_WIDTH-1:0] count_reg = 0, count_next;
reg [PERIOD_COUNT_WIDTH-1:0] update_period_reg = UPDATE_PERIOD-1, update_period_next;
reg [COUNT-1:0] zero_reg = {COUNT{1'b1}}, zero_next;
reg [COUNT-1:0] update_reg = {COUNT{1'b0}}, update_next;
wire [ACC_WIDTH-1:0] acc_int[COUNT-1:0];
reg [COUNT-1:0] acc_clear;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [STAT_INC_WIDTH-1:0] mem_reg[COUNT-1:0];
reg [STAT_INC_WIDTH-1:0] mem_rd_data_reg = 0;
reg mem_rd_en;
reg mem_wr_en;
reg [STAT_INC_WIDTH-1:0] mem_wr_data;
assign m_axis_stat_tdata = m_axis_stat_tdata_reg;
assign m_axis_stat_tid = m_axis_stat_tid_reg;
assign m_axis_stat_tvalid = m_axis_stat_tvalid_reg;
generate
genvar n;
for (n = 0; n < COUNT; n = n + 1) begin
reg [ACC_WIDTH-1:0] acc_reg = 0;
assign acc_int[n] = acc_reg;
always @(posedge clk) begin
if (acc_clear[n]) begin
if (stat_valid[n]) begin
acc_reg <= stat_inc[n*INC_WIDTH +: INC_WIDTH];
end else begin
acc_reg <= 0;
end
end else begin
if (stat_valid[n]) begin
acc_reg <= acc_reg + stat_inc[n*INC_WIDTH +: INC_WIDTH];
end
end
if (rst) begin
acc_reg <= 0;
end
end
end
endgenerate
always @* begin
state_next = STATE_READ;
m_axis_stat_tdata_next = m_axis_stat_tdata_reg;
m_axis_stat_tid_next = m_axis_stat_tid_reg;
m_axis_stat_tvalid_next = m_axis_stat_tvalid_reg && !m_axis_stat_tready;
count_next = count_reg;
update_period_next = update_period_reg;
zero_next = zero_reg;
update_next = update_reg;
acc_clear = {COUNT{1'b0}};
mem_rd_en = 1'b0;
mem_wr_en = 1'b0;
mem_wr_data = 0;
case (state_reg)
STATE_READ: begin
mem_rd_en = 1'b1;
state_next = STATE_WRITE;
end
STATE_WRITE: begin;
mem_wr_en = 1'b1;
acc_clear[count_reg] = 1'b1;
if (!m_axis_stat_tvalid_reg && (update_reg[count_reg] || mem_rd_data_reg[STAT_INC_WIDTH-1])) begin
update_next[count_reg] = 1'b0;
mem_wr_data = 0;
if (zero_reg[count_reg]) begin
m_axis_stat_tdata_next = acc_int[count_reg];
m_axis_stat_tid_next = count_reg + BASE_ID;
m_axis_stat_tvalid_next = acc_int[count_reg] != 0;
end else begin
m_axis_stat_tdata_next = mem_rd_data_reg + acc_int[count_reg];
m_axis_stat_tid_next = count_reg + BASE_ID;
m_axis_stat_tvalid_next = mem_rd_data_reg != 0 || acc_int[count_reg] != 0;
end
end else begin
if (zero_reg[count_reg]) begin
mem_wr_data = acc_int[count_reg];
end else begin
mem_wr_data = mem_rd_data_reg + acc_int[count_reg];
end
end
zero_next[count_reg] = 1'b0;
if (count_reg == COUNT-1) begin
count_next = 0;
end else begin
count_next = count_reg + 1;
end
state_next = STATE_READ;
end
endcase
if (update_period_reg == 0 || update) begin
update_next = {COUNT{1'b1}};
update_period_next = UPDATE_PERIOD-1;
end else begin
update_period_next = update_period_reg - 1;
end
end
always @(posedge clk) begin
state_reg <= state_next;
m_axis_stat_tdata_reg <= m_axis_stat_tdata_next;
m_axis_stat_tid_reg <= m_axis_stat_tid_next;
m_axis_stat_tvalid_reg <= m_axis_stat_tvalid_next;
count_reg <= count_next;
update_period_reg <= update_period_next;
zero_reg <= zero_next;
update_reg <= update_next;
if (mem_wr_en) begin
mem_reg[count_reg] <= mem_wr_data;
end else if (mem_rd_en) begin
mem_rd_data_reg <= mem_reg[count_reg];
end
if (rst) begin
state_reg <= STATE_READ;
m_axis_stat_tvalid_reg <= 1'b0;
count_reg <= 0;
update_period_reg <= UPDATE_PERIOD-1;
zero_reg <= {COUNT{1'b1}};
update_reg <= {COUNT{1'b0}};
end
end
endmodule |
module stats_pcie_if #
(
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 24,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = 5,
// Statistics counter update period (cycles)
parameter UPDATE_PERIOD = 1024
)
(
input wire clk,
input wire rst,
/*
* monitor input (request to BAR)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
/*
* monitor input (completion to DMA)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
/*
* monitor input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
/*
* monitor input (write request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
/*
* monitor input (completion from BAR)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
/*
* Statistics output
*/
output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata,
output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid,
output wire m_axis_stat_tvalid,
input wire m_axis_stat_tready,
/*
* Control inputs
*/
input wire update
);
wire stat_rx_req_tlp_mem_rd;
wire stat_rx_req_tlp_mem_wr;
wire stat_rx_req_tlp_io;
wire stat_rx_req_tlp_cfg;
wire stat_rx_req_tlp_msg;
wire stat_rx_req_tlp_cpl;
wire stat_rx_req_tlp_cpl_ur;
wire stat_rx_req_tlp_cpl_ca;
wire stat_rx_req_tlp_atomic;
wire stat_rx_req_tlp_ep;
wire [2:0] stat_rx_req_tlp_hdr_dw;
wire [10:0] stat_rx_req_tlp_req_dw;
wire [10:0] stat_rx_req_tlp_payload_dw;
wire [10:0] stat_rx_req_tlp_cpl_dw;
stats_pcie_tlp #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
stats_pcie_rx_req_tlp_inst (
.clk(clk),
.rst(rst),
/*
* TLP monitor input
*/
.tlp_hdr(rx_req_tlp_hdr),
.tlp_valid(rx_req_tlp_valid),
.tlp_sop(rx_req_tlp_sop),
.tlp_eop(rx_req_tlp_eop),
/*
* Statistics outputs
*/
.stat_tlp_mem_rd(stat_rx_req_tlp_mem_rd),
.stat_tlp_mem_wr(stat_rx_req_tlp_mem_wr),
.stat_tlp_io(stat_rx_req_tlp_io),
.stat_tlp_cfg(stat_rx_req_tlp_cfg),
.stat_tlp_msg(stat_rx_req_tlp_msg),
.stat_tlp_cpl(stat_rx_req_tlp_cpl),
.stat_tlp_cpl_ur(stat_rx_req_tlp_cpl_ur),
.stat_tlp_cpl_ca(stat_rx_req_tlp_cpl_ca),
.stat_tlp_atomic(stat_rx_req_tlp_atomic),
.stat_tlp_ep(stat_rx_req_tlp_ep),
.stat_tlp_hdr_dw(stat_rx_req_tlp_hdr_dw),
.stat_tlp_req_dw(stat_rx_req_tlp_req_dw),
.stat_tlp_payload_dw(stat_rx_req_tlp_payload_dw),
.stat_tlp_cpl_dw(stat_rx_req_tlp_cpl_dw)
);
wire stat_rx_cpl_tlp_mem_rd;
wire stat_rx_cpl_tlp_mem_wr;
wire stat_rx_cpl_tlp_io;
wire stat_rx_cpl_tlp_cfg;
wire stat_rx_cpl_tlp_msg;
wire stat_rx_cpl_tlp_cpl;
wire stat_rx_cpl_tlp_cpl_ur;
wire stat_rx_cpl_tlp_cpl_ca;
wire stat_rx_cpl_tlp_atomic;
wire stat_rx_cpl_tlp_ep;
wire [2:0] stat_rx_cpl_tlp_hdr_dw;
wire [10:0] stat_rx_cpl_tlp_req_dw;
wire [10:0] stat_rx_cpl_tlp_payload_dw;
wire [10:0] stat_rx_cpl_tlp_cpl_dw;
stats_pcie_tlp #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
stats_pcie_rx_cpl_tlp_inst (
.clk(clk),
.rst(rst),
/*
* TLP monitor input
*/
.tlp_hdr(rx_cpl_tlp_hdr),
.tlp_valid(rx_cpl_tlp_valid),
.tlp_sop(rx_cpl_tlp_sop),
.tlp_eop(rx_cpl_tlp_eop),
/*
* Statistics outputs
*/
.stat_tlp_mem_rd(stat_rx_cpl_tlp_mem_rd),
.stat_tlp_mem_wr(stat_rx_cpl_tlp_mem_wr),
.stat_tlp_io(stat_rx_cpl_tlp_io),
.stat_tlp_cfg(stat_rx_cpl_tlp_cfg),
.stat_tlp_msg(stat_rx_cpl_tlp_msg),
.stat_tlp_cpl(stat_rx_cpl_tlp_cpl),
.stat_tlp_cpl_ur(stat_rx_cpl_tlp_cpl_ur),
.stat_tlp_cpl_ca(stat_rx_cpl_tlp_cpl_ca),
.stat_tlp_atomic(stat_rx_cpl_tlp_atomic),
.stat_tlp_ep(stat_rx_cpl_tlp_ep),
.stat_tlp_hdr_dw(stat_rx_cpl_tlp_hdr_dw),
.stat_tlp_req_dw(stat_rx_cpl_tlp_req_dw),
.stat_tlp_payload_dw(stat_rx_cpl_tlp_payload_dw),
.stat_tlp_cpl_dw(stat_rx_cpl_tlp_cpl_dw)
);
wire [12:0] stat_rx_tlp_mem_rd_inc = stat_rx_req_tlp_mem_rd;
wire [12:0] stat_rx_tlp_mem_wr_inc = stat_rx_req_tlp_mem_wr;
wire [12:0] stat_rx_tlp_io_inc = stat_rx_req_tlp_io;
wire [12:0] stat_rx_tlp_cfg_inc = stat_rx_req_tlp_cfg;
wire [12:0] stat_rx_tlp_msg_inc = stat_rx_req_tlp_msg;
wire [12:0] stat_rx_tlp_cpl_inc = stat_rx_cpl_tlp_cpl;
wire [12:0] stat_rx_tlp_cpl_ur_inc = stat_rx_cpl_tlp_cpl_ur;
wire [12:0] stat_rx_tlp_cpl_ca_inc = stat_rx_cpl_tlp_cpl_ca;
wire [12:0] stat_rx_tlp_atomic_inc = stat_rx_req_tlp_atomic;
wire [12:0] stat_rx_tlp_ep_inc = stat_rx_req_tlp_ep + stat_rx_cpl_tlp_ep;
wire [12:0] stat_rx_tlp_hdr_dw_inc = stat_rx_req_tlp_hdr_dw + stat_rx_cpl_tlp_hdr_dw;
wire [12:0] stat_rx_tlp_req_dw_inc = stat_rx_req_tlp_req_dw;
wire [12:0] stat_rx_tlp_payload_dw_inc = stat_rx_req_tlp_payload_dw;
wire [12:0] stat_rx_tlp_cpl_dw_inc = stat_rx_cpl_tlp_cpl_dw;
wire stat_tx_rd_req_tlp_mem_rd;
wire stat_tx_rd_req_tlp_mem_wr;
wire stat_tx_rd_req_tlp_io;
wire stat_tx_rd_req_tlp_cfg;
wire stat_tx_rd_req_tlp_msg;
wire stat_tx_rd_req_tlp_cpl;
wire stat_tx_rd_req_tlp_cpl_ur;
wire stat_tx_rd_req_tlp_cpl_ca;
wire stat_tx_rd_req_tlp_atomic;
wire stat_tx_rd_req_tlp_ep;
wire [2:0] stat_tx_rd_req_tlp_hdr_dw;
wire [10:0] stat_tx_rd_req_tlp_req_dw;
wire [10:0] stat_tx_rd_req_tlp_payload_dw;
wire [10:0] stat_tx_rd_req_tlp_cpl_dw;
stats_pcie_tlp #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
stats_pcie_tx_rd_req_tlp_inst (
.clk(clk),
.rst(rst),
/*
* TLP monitor input
*/
.tlp_hdr(tx_rd_req_tlp_hdr),
.tlp_valid(tx_rd_req_tlp_valid),
.tlp_sop(tx_rd_req_tlp_sop),
.tlp_eop(tx_rd_req_tlp_eop),
/*
* Statistics outputs
*/
.stat_tlp_mem_rd(stat_tx_rd_req_tlp_mem_rd),
.stat_tlp_mem_wr(stat_tx_rd_req_tlp_mem_wr),
.stat_tlp_io(stat_tx_rd_req_tlp_io),
.stat_tlp_cfg(stat_tx_rd_req_tlp_cfg),
.stat_tlp_msg(stat_tx_rd_req_tlp_msg),
.stat_tlp_cpl(stat_tx_rd_req_tlp_cpl),
.stat_tlp_cpl_ur(stat_tx_rd_req_tlp_cpl_ur),
.stat_tlp_cpl_ca(stat_tx_rd_req_tlp_cpl_ca),
.stat_tlp_atomic(stat_tx_rd_req_tlp_atomic),
.stat_tlp_ep(stat_tx_rd_req_tlp_ep),
.stat_tlp_hdr_dw(stat_tx_rd_req_tlp_hdr_dw),
.stat_tlp_req_dw(stat_tx_rd_req_tlp_req_dw),
.stat_tlp_payload_dw(stat_tx_rd_req_tlp_payload_dw),
.stat_tlp_cpl_dw(stat_tx_rd_req_tlp_cpl_dw)
);
wire stat_tx_wr_req_tlp_mem_rd;
wire stat_tx_wr_req_tlp_mem_wr;
wire stat_tx_wr_req_tlp_io;
wire stat_tx_wr_req_tlp_cfg;
wire stat_tx_wr_req_tlp_msg;
wire stat_tx_wr_req_tlp_cpl;
wire stat_tx_wr_req_tlp_cpl_ur;
wire stat_tx_wr_req_tlp_cpl_ca;
wire stat_tx_wr_req_tlp_atomic;
wire stat_tx_wr_req_tlp_ep;
wire [2:0] stat_tx_wr_req_tlp_hdr_dw;
wire [10:0] stat_tx_wr_req_tlp_req_dw;
wire [10:0] stat_tx_wr_req_tlp_payload_dw;
wire [10:0] stat_tx_wr_req_tlp_cpl_dw;
stats_pcie_tlp #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
stats_pcie_tx_wr_req_tlp_inst (
.clk(clk),
.rst(rst),
/*
* TLP monitor input
*/
.tlp_hdr(tx_wr_req_tlp_hdr),
.tlp_valid(tx_wr_req_tlp_valid),
.tlp_sop(tx_wr_req_tlp_sop),
.tlp_eop(tx_wr_req_tlp_eop),
/*
* Statistics outputs
*/
.stat_tlp_mem_rd(stat_tx_wr_req_tlp_mem_rd),
.stat_tlp_mem_wr(stat_tx_wr_req_tlp_mem_wr),
.stat_tlp_io(stat_tx_wr_req_tlp_io),
.stat_tlp_cfg(stat_tx_wr_req_tlp_cfg),
.stat_tlp_msg(stat_tx_wr_req_tlp_msg),
.stat_tlp_cpl(stat_tx_wr_req_tlp_cpl),
.stat_tlp_cpl_ur(stat_tx_wr_req_tlp_cpl_ur),
.stat_tlp_cpl_ca(stat_tx_wr_req_tlp_cpl_ca),
.stat_tlp_atomic(stat_tx_wr_req_tlp_atomic),
.stat_tlp_ep(stat_tx_wr_req_tlp_ep),
.stat_tlp_hdr_dw(stat_tx_wr_req_tlp_hdr_dw),
.stat_tlp_req_dw(stat_tx_wr_req_tlp_req_dw),
.stat_tlp_payload_dw(stat_tx_wr_req_tlp_payload_dw),
.stat_tlp_cpl_dw(stat_tx_wr_req_tlp_cpl_dw)
);
wire stat_tx_cpl_tlp_mem_rd;
wire stat_tx_cpl_tlp_mem_wr;
wire stat_tx_cpl_tlp_io;
wire stat_tx_cpl_tlp_cfg;
wire stat_tx_cpl_tlp_msg;
wire stat_tx_cpl_tlp_cpl;
wire stat_tx_cpl_tlp_cpl_ur;
wire stat_tx_cpl_tlp_cpl_ca;
wire stat_tx_cpl_tlp_atomic;
wire stat_tx_cpl_tlp_ep;
wire [2:0] stat_tx_cpl_tlp_hdr_dw;
wire [10:0] stat_tx_cpl_tlp_req_dw;
wire [10:0] stat_tx_cpl_tlp_payload_dw;
wire [10:0] stat_tx_cpl_tlp_cpl_dw;
stats_pcie_tlp #(
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
stats_pcie_tx_cpl_tlp_inst (
.clk(clk),
.rst(rst),
/*
* TLP monitor input
*/
.tlp_hdr(tx_cpl_tlp_hdr),
.tlp_valid(tx_cpl_tlp_valid),
.tlp_sop(tx_cpl_tlp_sop),
.tlp_eop(tx_cpl_tlp_eop),
/*
* Statistics outputs
*/
.stat_tlp_mem_rd(stat_tx_cpl_tlp_mem_rd),
.stat_tlp_mem_wr(stat_tx_cpl_tlp_mem_wr),
.stat_tlp_io(stat_tx_cpl_tlp_io),
.stat_tlp_cfg(stat_tx_cpl_tlp_cfg),
.stat_tlp_msg(stat_tx_cpl_tlp_msg),
.stat_tlp_cpl(stat_tx_cpl_tlp_cpl),
.stat_tlp_cpl_ur(stat_tx_cpl_tlp_cpl_ur),
.stat_tlp_cpl_ca(stat_tx_cpl_tlp_cpl_ca),
.stat_tlp_atomic(stat_tx_cpl_tlp_atomic),
.stat_tlp_ep(stat_tx_cpl_tlp_ep),
.stat_tlp_hdr_dw(stat_tx_cpl_tlp_hdr_dw),
.stat_tlp_req_dw(stat_tx_cpl_tlp_req_dw),
.stat_tlp_payload_dw(stat_tx_cpl_tlp_payload_dw),
.stat_tlp_cpl_dw(stat_tx_cpl_tlp_cpl_dw)
);
wire [12:0] stat_tx_tlp_mem_rd_inc = stat_tx_rd_req_tlp_mem_rd;
wire [12:0] stat_tx_tlp_mem_wr_inc = stat_tx_wr_req_tlp_mem_wr;
wire [12:0] stat_tx_tlp_io_inc = 0;
wire [12:0] stat_tx_tlp_cfg_inc = 0;
wire [12:0] stat_tx_tlp_msg_inc = 0;
wire [12:0] stat_tx_tlp_cpl_inc = stat_tx_cpl_tlp_cpl;
wire [12:0] stat_tx_tlp_cpl_ur_inc = stat_tx_cpl_tlp_cpl_ur;
wire [12:0] stat_tx_tlp_cpl_ca_inc = stat_tx_cpl_tlp_cpl_ca;
wire [12:0] stat_tx_tlp_atomic_inc = 0;
wire [12:0] stat_tx_tlp_ep_inc = 0;
wire [12:0] stat_tx_tlp_hdr_dw_inc = stat_tx_rd_req_tlp_hdr_dw + stat_tx_wr_req_tlp_hdr_dw + stat_tx_cpl_tlp_hdr_dw;
wire [12:0] stat_tx_tlp_req_dw_inc = stat_tx_rd_req_tlp_req_dw;
wire [12:0] stat_tx_tlp_payload_dw_inc = stat_tx_wr_req_tlp_payload_dw;
wire [12:0] stat_tx_tlp_cpl_dw_inc = stat_tx_cpl_tlp_cpl_dw;
stats_collect #(
.COUNT(32),
.INC_WIDTH(13),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(UPDATE_PERIOD)
)
stats_collect_inst (
.clk(clk),
.rst(rst),
/*
* Increment inputs
*/
.stat_inc({
13'd0, // index 31
13'd0, // index 30
stat_tx_tlp_cpl_dw_inc, // index 29
stat_tx_tlp_payload_dw_inc, // index 28
stat_tx_tlp_req_dw_inc, // index 27
stat_tx_tlp_hdr_dw_inc, // index 26
stat_tx_tlp_ep_inc, // index 25
stat_tx_tlp_atomic_inc, // index 24
stat_tx_tlp_cpl_ca_inc, // index 23
stat_tx_tlp_cpl_ur_inc, // index 22
stat_tx_tlp_cpl_inc, // index 21
stat_tx_tlp_msg_inc, // index 20
stat_tx_tlp_cfg_inc, // index 19
stat_tx_tlp_io_inc, // index 18
stat_tx_tlp_mem_wr_inc, // index 17
stat_tx_tlp_mem_rd_inc, // index 16
13'd0, // index 15
13'd0, // index 14
stat_rx_tlp_cpl_dw_inc, // index 13
stat_rx_tlp_payload_dw_inc, // index 12
stat_rx_tlp_req_dw_inc, // index 11
stat_rx_tlp_hdr_dw_inc, // index 10
stat_rx_tlp_ep_inc, // index 9
stat_rx_tlp_atomic_inc, // index 8
stat_rx_tlp_cpl_ca_inc, // index 7
stat_rx_tlp_cpl_ur_inc, // index 6
stat_rx_tlp_cpl_inc, // index 5
stat_rx_tlp_msg_inc, // index 4
stat_rx_tlp_cfg_inc, // index 3
stat_rx_tlp_io_inc, // index 2
stat_rx_tlp_mem_wr_inc, // index 1
stat_rx_tlp_mem_rd_inc // index 0
}),
.stat_valid({32{1'b1}}),
/*
* Statistics increment output
*/
.m_axis_stat_tdata(m_axis_stat_tdata),
.m_axis_stat_tid(m_axis_stat_tid),
.m_axis_stat_tvalid(m_axis_stat_tvalid),
.m_axis_stat_tready(m_axis_stat_tready),
/*
* Control inputs
*/
.update(update)
);
endmodule |
module stats_counter #
(
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 16,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = 8,
// Statistics counter (bits)
parameter STAT_COUNT_WIDTH = 32,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
parameter AXIL_ADDR_WIDTH = STAT_ID_WIDTH+$clog2(((AXIL_DATA_WIDTH > STAT_COUNT_WIDTH ? AXIL_DATA_WIDTH : STAT_COUNT_WIDTH)+7)/8),
// Width of AXI lite wstrb (width of data bus in words)
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Statistics increment input
*/
input wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
input wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
input wire s_axis_stat_tvalid,
output wire s_axis_stat_tready,
/*
* AXI Lite register interface
*/
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready
);
parameter ID_SHIFT = $clog2(((AXIL_DATA_WIDTH > STAT_COUNT_WIDTH ? AXIL_DATA_WIDTH : STAT_COUNT_WIDTH)+7)/8);
parameter WORD_SELECT_SHIFT = $clog2(AXIL_DATA_WIDTH/8);
parameter WORD_SELECT_WIDTH = STAT_COUNT_WIDTH > AXIL_DATA_WIDTH ? $clog2((STAT_COUNT_WIDTH+7)/8) - $clog2(AXIL_DATA_WIDTH/8) : 0;
// bus width assertions
initial begin
if (AXIL_STRB_WIDTH * 8 != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
if (AXIL_ADDR_WIDTH < STAT_ID_WIDTH+ID_SHIFT) begin
$error("Error: AXI lite address width too narrow (instance %m)");
$finish;
end
end
localparam [1:0]
STATE_INIT = 2'd0,
STATE_IDLE = 2'd1,
STATE_READ = 2'd2,
STATE_WRITE = 2'd3;
reg [1:0] state_reg = STATE_INIT, state_next;
reg s_axis_stat_tready_reg = 1'b0, s_axis_stat_tready_next;
reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
reg [AXIL_DATA_WIDTH-1:0] s_axil_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, s_axil_rdata_next;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
reg [STAT_ID_WIDTH-1:0] id_reg = {STAT_ID_WIDTH{1'b0}}, id_next;
reg [STAT_INC_WIDTH-1:0] inc_reg = {STAT_INC_WIDTH{1'b0}}, inc_next;
reg rd_data_valid_reg = 1'b0, rd_data_valid_next;
reg [WORD_SELECT_WIDTH-1:0] rd_data_shift_reg = 0, rd_data_shift_next;
(* ramstyle = "no_rw_check" *)
reg [STAT_COUNT_WIDTH-1:0] mem_reg[(2**STAT_ID_WIDTH)-1:0];
reg [STAT_COUNT_WIDTH-1:0] mem_rd_data_reg = {STAT_COUNT_WIDTH{1'b0}};
reg [STAT_COUNT_WIDTH-1:0] mem_rd_data_axil_reg = {STAT_COUNT_WIDTH{1'b0}};
reg mem_rd_en;
reg mem_wr_en;
reg [STAT_COUNT_WIDTH-1:0] mem_wr_data;
reg mem_rd_en_axil;
wire [STAT_ID_WIDTH-1:0] s_axil_araddr_id = s_axil_araddr >> ID_SHIFT;
wire [WORD_SELECT_WIDTH-1:0] s_axil_araddr_word = s_axil_araddr >> WORD_SELECT_SHIFT;
assign s_axis_stat_tready = s_axis_stat_tready_reg;
assign s_axil_awready = s_axil_awready_reg;
assign s_axil_wready = s_axil_wready_reg;
assign s_axil_bresp = 2'b00;
assign s_axil_bvalid = s_axil_bvalid_reg;
assign s_axil_arready = s_axil_arready_reg;
assign s_axil_rdata = s_axil_rdata_reg;
assign s_axil_rresp = 2'b00;
assign s_axil_rvalid = s_axil_rvalid_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**STAT_ID_WIDTH; i = i + 2**(STAT_ID_WIDTH/2)) begin
for (j = i; j < i + 2**(STAT_ID_WIDTH/2); j = j + 1) begin
mem_reg[j] = 0;
end
end
end
// accumulate
always @* begin
state_next = STATE_IDLE;
s_axis_stat_tready_next = 1'b0;
id_next = id_reg;
inc_next = inc_reg;
mem_rd_en = 1'b0;
mem_wr_en = 1'b0;
mem_wr_data = mem_rd_data_reg + inc_reg;
case (state_reg)
STATE_INIT: begin
id_next = id_reg + 1;
mem_wr_en = 1'b1;
mem_wr_data = 0;
if (id_reg == {STAT_ID_WIDTH{1'b1}}) begin
state_next = STATE_IDLE;
end else begin
state_next = STATE_INIT;
end
end
STATE_IDLE: begin
s_axis_stat_tready_next = 1'b1;
if (s_axis_stat_tvalid && s_axis_stat_tready) begin
inc_next = s_axis_stat_tdata;
id_next = s_axis_stat_tid;
s_axis_stat_tready_next = 1'b0;
state_next = STATE_READ;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ: begin
s_axis_stat_tready_next = 1'b1;
mem_rd_en = 1'b1;
state_next = STATE_WRITE;
end
STATE_WRITE: begin
s_axis_stat_tready_next = 1'b1;
mem_wr_en = 1'b1;
mem_wr_data = mem_rd_data_reg + inc_reg;
if (s_axis_stat_tvalid && s_axis_stat_tready) begin
inc_next = s_axis_stat_tdata;
id_next = s_axis_stat_tid;
s_axis_stat_tready_next = 1'b0;
state_next = STATE_READ;
end else begin
state_next = STATE_IDLE;
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
s_axis_stat_tready_reg <= s_axis_stat_tready_next;
id_reg <= id_next;
inc_reg <= inc_next;
if (mem_wr_en) begin
mem_reg[id_reg] <= mem_wr_data;
end else if (mem_rd_en) begin
mem_rd_data_reg <= mem_reg[id_reg];
end
if (rst) begin
state_reg <= STATE_INIT;
s_axis_stat_tready_reg <= 1'b0;
id_reg <= {STAT_ID_WIDTH{1'b0}};
end
end
// register interface
always @* begin
s_axil_awready_next = 1'b0;
s_axil_wready_next = 1'b0;
s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
if (s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready)) begin
s_axil_awready_next = 1'b1;
s_axil_wready_next = 1'b1;
s_axil_bvalid_next = 1'b1;
end
end
always @(posedge clk) begin
s_axil_awready_reg <= s_axil_awready_next;
s_axil_wready_reg <= s_axil_wready_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
if (rst) begin
s_axil_awready_reg <= 1'b0;
s_axil_wready_reg <= 1'b0;
s_axil_bvalid_reg <= 1'b0;
end
end
always @* begin
s_axil_arready_next = 1'b0;
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;
s_axil_rdata_next = s_axil_rdata_reg;
rd_data_valid_next = rd_data_valid_reg;
rd_data_shift_next = rd_data_shift_reg;
mem_rd_en_axil = 1'b0;
if (rd_data_valid_reg && (!s_axil_rvalid || s_axil_rready)) begin
s_axil_rvalid_next = 1'b1;
rd_data_valid_next = 1'b0;
if (STAT_COUNT_WIDTH > AXIL_DATA_WIDTH) begin
s_axil_rdata_next = mem_rd_data_axil_reg >> rd_data_shift_reg*AXIL_DATA_WIDTH;
end else begin
s_axil_rdata_next = mem_rd_data_axil_reg;
end
end
if (s_axil_arvalid && (!s_axil_rvalid || s_axil_rready || !rd_data_valid_reg) && !s_axil_arready) begin
s_axil_arready_next = 1'b1;
rd_data_valid_next = 1'b1;
rd_data_shift_next = s_axil_araddr_word;
mem_rd_en_axil = 1'b1;
end
end
always @(posedge clk) begin
s_axil_arready_reg <= s_axil_arready_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;
s_axil_rdata_reg <= s_axil_rdata_next;
rd_data_valid_reg <= rd_data_valid_next;
rd_data_shift_reg <= rd_data_shift_next;
if (mem_rd_en_axil) begin
mem_rd_data_axil_reg <= mem_reg[s_axil_araddr_id];
end
if (rst) begin
s_axil_arready_reg <= 1'b0;
s_axil_rvalid_reg <= 1'b0;
rd_data_valid_reg <= 1'b0;
end
end
endmodule |
module stats_pcie_tlp #
(
// TLP segment header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
/*
* TLP monitor input
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tlp_eop,
/*
* Statistics outputs
*/
output wire stat_tlp_mem_rd,
output wire stat_tlp_mem_wr,
output wire stat_tlp_io,
output wire stat_tlp_cfg,
output wire stat_tlp_msg,
output wire stat_tlp_cpl,
output wire stat_tlp_cpl_ur,
output wire stat_tlp_cpl_ca,
output wire stat_tlp_atomic,
output wire stat_tlp_ep,
output wire [2:0] stat_tlp_hdr_dw,
output wire [10:0] stat_tlp_req_dw,
output wire [10:0] stat_tlp_payload_dw,
output wire [10:0] stat_tlp_cpl_dw
);
localparam [2:0]
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
localparam [2:0]
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] tlp_eop_reg = 0;
reg stat_tlp_mem_rd_reg = 1'b0;
reg stat_tlp_mem_wr_reg = 1'b0;
reg stat_tlp_io_reg = 1'b0;
reg stat_tlp_cfg_reg = 1'b0;
reg stat_tlp_msg_reg = 1'b0;
reg stat_tlp_cpl_reg = 1'b0;
reg stat_tlp_cpl_ur_reg = 1'b0;
reg stat_tlp_cpl_ca_reg = 1'b0;
reg stat_tlp_atomic_reg = 1'b0;
reg stat_tlp_ep_reg = 1'b0;
reg [2:0] stat_tlp_hdr_dw_reg = 3'd0;
reg [10:0] stat_tlp_req_dw_reg = 11'd0;
reg [10:0] stat_tlp_payload_dw_reg = 11'd0;
reg [10:0] stat_tlp_cpl_dw_reg = 11'd0;
wire tlp_hdr_valid = tlp_valid_reg && tlp_sop_reg;
wire [7:0] tlp_hdr_fmt_type = tlp_hdr_reg[127:120];
wire [2:0] tlp_hdr_fmt = tlp_hdr_reg[127:125];
wire [4:0] tlp_hdr_type = tlp_hdr_reg[124:120];
wire tlp_hdr_ep = tlp_hdr_reg[110];
wire [9:0] tlp_hdr_length = tlp_hdr_reg[105:96];
wire [3:0] tlp_hdr_cpl_status = tlp_hdr_reg[79:77];
assign stat_tlp_mem_rd = stat_tlp_mem_rd_reg;
assign stat_tlp_mem_wr = stat_tlp_mem_wr_reg;
assign stat_tlp_io = stat_tlp_io_reg;
assign stat_tlp_cfg = stat_tlp_cfg_reg;
assign stat_tlp_msg = stat_tlp_msg_reg;
assign stat_tlp_cpl = stat_tlp_cpl_reg;
assign stat_tlp_cpl_ur = stat_tlp_cpl_ur_reg;
assign stat_tlp_cpl_ca = stat_tlp_cpl_ca_reg;
assign stat_tlp_atomic = stat_tlp_atomic_reg;
assign stat_tlp_ep = stat_tlp_ep_reg;
assign stat_tlp_hdr_dw = stat_tlp_hdr_dw_reg;
assign stat_tlp_req_dw = stat_tlp_req_dw_reg;
assign stat_tlp_payload_dw = stat_tlp_payload_dw_reg;
assign stat_tlp_cpl_dw = stat_tlp_cpl_dw_reg;
always @(posedge clk) begin
tlp_hdr_reg <= tlp_hdr;
tlp_valid_reg <= tlp_valid;
tlp_sop_reg <= tlp_sop;
tlp_eop_reg <= tlp_eop;
stat_tlp_mem_rd_reg <= 1'b0;
stat_tlp_mem_wr_reg <= 1'b0;
stat_tlp_io_reg <= 1'b0;
stat_tlp_cfg_reg <= 1'b0;
stat_tlp_msg_reg <= 1'b0;
stat_tlp_cpl_reg <= 1'b0;
stat_tlp_cpl_ur_reg <= 1'b0;
stat_tlp_cpl_ca_reg <= 1'b0;
stat_tlp_atomic_reg <= 1'b0;
stat_tlp_ep_reg <= 1'b0;
stat_tlp_hdr_dw_reg <= 0;
stat_tlp_req_dw_reg <= 0;
stat_tlp_payload_dw_reg <= 0;
stat_tlp_cpl_dw_reg <= 0;
if (tlp_hdr_valid) begin
casez (tlp_hdr_fmt_type)
8'b00z_0000z: stat_tlp_mem_rd_reg <= 1'b1;
8'b01z_00000: stat_tlp_mem_wr_reg <= 1'b1;
8'b0z0_00010: stat_tlp_io_reg <= 1'b1;
8'b0z0_0010z: stat_tlp_cfg_reg <= 1'b1;
8'b0z1_10zzz: stat_tlp_msg_reg <= 1'b1;
8'b0z0_0101z: begin
stat_tlp_cpl_reg <= 1'b1;
stat_tlp_cpl_ur_reg <= tlp_hdr_cpl_status == CPL_STATUS_UR;
stat_tlp_cpl_ca_reg <= tlp_hdr_cpl_status == CPL_STATUS_CA;
end
8'b01z_01100: stat_tlp_atomic_reg <= 1'b1;
8'b01z_01101: stat_tlp_atomic_reg <= 1'b1;
8'b01z_01110: stat_tlp_atomic_reg <= 1'b1;
endcase
stat_tlp_ep_reg <= tlp_hdr_ep;
stat_tlp_hdr_dw_reg <= tlp_hdr_fmt[0] ? 3'd4 : 3'd3;
if (tlp_hdr_fmt[1]) begin
if (tlp_hdr_type == 5'b01010 || tlp_hdr_type == 5'b01011) begin
stat_tlp_cpl_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
end else begin
stat_tlp_payload_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
end
end else begin
stat_tlp_req_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
end
end
if (rst) begin
tlp_valid_reg <= 0;
tlp_sop_reg <= 0;
tlp_eop_reg <= 0;
stat_tlp_mem_rd_reg <= 0;
stat_tlp_mem_wr_reg <= 0;
stat_tlp_io_reg <= 0;
stat_tlp_cfg_reg <= 0;
stat_tlp_msg_reg <= 0;
stat_tlp_cpl_reg <= 0;
stat_tlp_cpl_ur_reg <= 0;
stat_tlp_cpl_ca_reg <= 0;
stat_tlp_atomic_reg <= 0;
stat_tlp_ep_reg <= 0;
stat_tlp_hdr_dw_reg <= 0;
stat_tlp_req_dw_reg <= 0;
stat_tlp_payload_dw_reg <= 0;
stat_tlp_cpl_dw_reg <= 0;
end
end
endmodule |
module stats_dma_if_pcie #
(
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Length field width
parameter LEN_WIDTH = 16,
// Operation table size (read)
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 64,
// Statistics counter increment width (bits)
parameter STAT_INC_WIDTH = 24,
// Statistics counter ID width (bits)
parameter STAT_ID_WIDTH = 5,
// Statistics counter update period (cycles)
parameter UPDATE_PERIOD = 1024
)
(
input wire clk,
input wire rst,
/*
* Statistics from dma_if_pcie
*/
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag,
input wire [LEN_WIDTH-1:0] stat_rd_op_start_len,
input wire stat_rd_op_start_valid,
input wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag,
input wire [3:0] stat_rd_op_finish_status,
input wire stat_rd_op_finish_valid,
input wire [$clog2(PCIE_TAG_COUNT)-1:0] stat_rd_req_start_tag,
input wire [12:0] stat_rd_req_start_len,
input wire stat_rd_req_start_valid,
input wire [$clog2(PCIE_TAG_COUNT)-1:0] stat_rd_req_finish_tag,
input wire [3:0] stat_rd_req_finish_status,
input wire stat_rd_req_finish_valid,
input wire stat_rd_req_timeout,
input wire stat_rd_op_table_full,
input wire stat_rd_no_tags,
input wire stat_rd_tx_no_credit,
input wire stat_rd_tx_limit,
input wire stat_rd_tx_stall,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
input wire [LEN_WIDTH-1:0] stat_wr_op_start_len,
input wire stat_wr_op_start_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag,
input wire [3:0] stat_wr_op_finish_status,
input wire stat_wr_op_finish_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag,
input wire [12:0] stat_wr_req_start_len,
input wire stat_wr_req_start_valid,
input wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag,
input wire [3:0] stat_wr_req_finish_status,
input wire stat_wr_req_finish_valid,
input wire stat_wr_op_table_full,
input wire stat_wr_tx_no_credit,
input wire stat_wr_tx_limit,
input wire stat_wr_tx_stall,
/*
* Statistics output
*/
output wire [STAT_INC_WIDTH-1:0] m_axis_stat_tdata,
output wire [STAT_ID_WIDTH-1:0] m_axis_stat_tid,
output wire m_axis_stat_tvalid,
input wire m_axis_stat_tready,
/*
* Control inputs
*/
input wire update
);
wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_tag;
wire [LEN_WIDTH-1:0] stat_rd_op_len;
wire [3:0] stat_rd_op_status;
wire [15:0] stat_rd_op_latency;
wire stat_rd_op_valid;
wire [$clog2(PCIE_TAG_COUNT)-1:0] stat_rd_req_tag;
wire [12:0] stat_rd_req_len;
wire [3:0] stat_rd_req_status;
wire [15:0] stat_rd_req_latency;
wire stat_rd_req_valid;
wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_tag;
wire [LEN_WIDTH-1:0] stat_wr_op_len;
wire [3:0] stat_wr_op_status;
wire [15:0] stat_wr_op_latency;
wire stat_wr_op_valid;
wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_tag;
wire [12:0] stat_wr_req_len;
wire [3:0] stat_wr_req_status;
wire [15:0] stat_wr_req_latency;
wire stat_wr_req_valid;
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(READ_OP_TABLE_SIZE)),
.LEN_WIDTH(LEN_WIDTH),
.STATUS_WIDTH(4)
)
stats_dma_latency_rd_op_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_rd_op_start_tag),
.in_start_len(stat_rd_op_start_len),
.in_start_valid(stat_rd_op_start_valid),
.in_finish_tag(stat_rd_op_finish_tag),
.in_finish_status(stat_rd_op_finish_status),
.in_finish_valid(stat_rd_op_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_rd_op_tag),
.out_len(stat_rd_op_len),
.out_status(stat_rd_op_status),
.out_latency(stat_rd_op_latency),
.out_valid(stat_rd_op_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(PCIE_TAG_COUNT)),
.LEN_WIDTH(13),
.STATUS_WIDTH(4)
)
stats_dma_latency_rd_req_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_rd_req_start_tag),
.in_start_len(stat_rd_req_start_len),
.in_start_valid(stat_rd_req_start_valid),
.in_finish_tag(stat_rd_req_finish_tag),
.in_finish_status(stat_rd_req_finish_status),
.in_finish_valid(stat_rd_req_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_rd_req_tag),
.out_len(stat_rd_req_len),
.out_status(stat_rd_req_status),
.out_latency(stat_rd_req_latency),
.out_valid(stat_rd_req_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(WRITE_OP_TABLE_SIZE)),
.LEN_WIDTH(LEN_WIDTH),
.STATUS_WIDTH(4)
)
stats_dma_latency_wr_op_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_wr_op_start_tag),
.in_start_len(stat_wr_op_start_len),
.in_start_valid(stat_wr_op_start_valid),
.in_finish_tag(stat_wr_op_finish_tag),
.in_finish_status(stat_wr_op_finish_status),
.in_finish_valid(stat_wr_op_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_wr_op_tag),
.out_len(stat_wr_op_len),
.out_status(stat_wr_op_status),
.out_latency(stat_wr_op_latency),
.out_valid(stat_wr_op_valid)
);
stats_dma_latency #(
.COUNT_WIDTH(16),
.TAG_WIDTH($clog2(WRITE_OP_TABLE_SIZE)),
.LEN_WIDTH(13),
.STATUS_WIDTH(4)
)
stats_dma_latency_wr_req_inst (
.clk(clk),
.rst(rst),
/*
* Tag inputs
*/
.in_start_tag(stat_wr_req_start_tag),
.in_start_len(stat_wr_req_start_len),
.in_start_valid(stat_wr_req_start_valid),
.in_finish_tag(stat_wr_req_finish_tag),
.in_finish_status(stat_wr_req_finish_status),
.in_finish_valid(stat_wr_req_finish_valid),
/*
* Statistics increment output
*/
.out_tag(stat_wr_req_tag),
.out_len(stat_wr_req_len),
.out_status(stat_wr_req_status),
.out_latency(stat_wr_req_latency),
.out_valid(stat_wr_req_valid)
);
wire [15:0] stat_rd_op_count_inc = stat_rd_op_valid;
wire [15:0] stat_rd_op_bytes_inc = stat_rd_op_len;
wire [15:0] stat_rd_op_latency_inc = stat_rd_op_latency;
wire [15:0] stat_rd_op_error_inc = stat_rd_op_valid && (stat_rd_op_status != 0);
wire [15:0] stat_rd_req_count_inc = stat_rd_req_valid;
wire [15:0] stat_rd_req_latency_inc = stat_rd_req_latency;
wire [15:0] stat_rd_req_timeout_inc = stat_rd_req_timeout;
wire [15:0] stat_rd_op_table_full_inc = stat_rd_op_table_full;
wire [15:0] stat_rd_no_tags_inc = stat_rd_no_tags;
wire [15:0] stat_rd_tx_no_credit_inc = stat_rd_tx_no_credit;
wire [15:0] stat_rd_tx_limit_inc = stat_rd_tx_limit;
wire [15:0] stat_rd_tx_stall_inc = stat_rd_tx_stall;
wire [15:0] stat_wr_op_count_inc = stat_wr_op_valid;
wire [15:0] stat_wr_op_bytes_inc = stat_wr_op_len;
wire [15:0] stat_wr_op_latency_inc = stat_wr_op_latency;
wire [15:0] stat_wr_op_error_inc = stat_wr_op_valid && (stat_wr_op_status != 0);
wire [15:0] stat_wr_req_count_inc = stat_wr_req_valid;
wire [15:0] stat_wr_req_latency_inc = stat_wr_req_latency;
wire [15:0] stat_wr_op_table_full_inc = stat_wr_op_table_full;
wire [15:0] stat_wr_tx_no_credit_inc = stat_wr_tx_no_credit;
wire [15:0] stat_wr_tx_limit_inc = stat_wr_tx_limit;
wire [15:0] stat_wr_tx_stall_inc = stat_wr_tx_stall;
stats_collect #(
.COUNT(32),
.INC_WIDTH(16),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(5),
.UPDATE_PERIOD(UPDATE_PERIOD)
)
stats_collect_tx_inst (
.clk(clk),
.rst(rst),
/*
* Increment inputs
*/
.stat_inc({
16'd0, // index 31
16'd0, // index 30
16'd0, // index 29
16'd0, // index 28
stat_wr_tx_stall_inc, // index 27
stat_wr_tx_limit_inc, // index 26
stat_wr_tx_no_credit_inc, // index 25
16'd0, // index 24
stat_wr_op_table_full_inc, // index 23
16'd0, // index 22
stat_wr_req_latency_inc, // index 21
stat_wr_req_count_inc, // index 20
stat_wr_op_error_inc, // index 19
stat_wr_op_latency_inc, // index 18
stat_wr_op_bytes_inc, // index 17
stat_wr_op_count_inc, // index 16
16'd0, // index 15
16'd0, // index 14
16'd0, // index 13
16'd0, // index 12
stat_rd_tx_stall_inc, // index 11
stat_rd_tx_limit_inc, // index 10
stat_rd_tx_no_credit_inc, // index 9
stat_rd_no_tags_inc, // index 8
stat_rd_op_table_full_inc, // index 7
stat_rd_req_timeout_inc, // index 6
stat_rd_req_latency_inc, // index 5
stat_rd_req_count_inc, // index 4
stat_rd_op_error_inc, // index 3
stat_rd_op_latency_inc, // index 2
stat_rd_op_bytes_inc, // index 1
stat_rd_op_count_inc // index 0
}),
.stat_valid({32{1'b1}}),
/*
* Statistics increment output
*/
.m_axis_stat_tdata(m_axis_stat_tdata),
.m_axis_stat_tid(m_axis_stat_tid),
.m_axis_stat_tvalid(m_axis_stat_tvalid),
.m_axis_stat_tready(m_axis_stat_tready),
/*
* Control inputs
*/
.update(update)
);
endmodule |
module stats_dma_latency #
(
// Counter width (bits)
parameter COUNT_WIDTH = 16,
// Tag width (bits)
parameter TAG_WIDTH = 8,
// Length field width (bits)
parameter LEN_WIDTH = 16,
// Status field width (bits)
parameter STATUS_WIDTH = 4
)
(
input wire clk,
input wire rst,
/*
* Tag inputs
*/
input wire [TAG_WIDTH-1:0] in_start_tag,
input wire [LEN_WIDTH-1:0] in_start_len,
input wire in_start_valid,
input wire [TAG_WIDTH-1:0] in_finish_tag,
input wire [STATUS_WIDTH-1:0] in_finish_status,
input wire in_finish_valid,
/*
* Statistics increment output
*/
output wire [TAG_WIDTH-1:0] out_tag,
output wire [LEN_WIDTH-1:0] out_len,
output wire [STATUS_WIDTH-1:0] out_status,
output wire [COUNT_WIDTH-1:0] out_latency,
output wire out_valid
);
reg [COUNT_WIDTH-1:0] count_reg = 0;
reg [TAG_WIDTH-1:0] out_tag_reg = 0;
reg [LEN_WIDTH-1:0] out_len_reg = 0;
reg [STATUS_WIDTH-1:0] out_status_reg = 0;
reg [COUNT_WIDTH-1:0] out_latency_reg = 0;
reg out_valid_reg = 1'b0;
assign out_tag = out_tag_reg;
assign out_len = out_len_reg;
assign out_status = out_status_reg;
assign out_latency = out_latency_reg;
assign out_valid = out_valid_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [LEN_WIDTH-1:0] len_mem_reg[2**TAG_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [COUNT_WIDTH-1:0] count_mem_reg[2**TAG_WIDTH-1:0];
integer i;
initial begin
for (i = 0; i < 2**TAG_WIDTH; i = i + 1) begin
len_mem_reg[i] = 0;
count_mem_reg[i] = 0;
end
end
always @(posedge clk) begin
count_reg <= count_reg + 1;
out_tag_reg <= 0;
out_len_reg <= 0;
out_status_reg <= 0;
out_latency_reg <= 0;
out_valid_reg <= 0;
if (in_start_valid) begin
len_mem_reg[in_start_tag] <= in_start_len;
count_mem_reg[in_start_tag] <= count_reg;
end
if (in_finish_valid) begin
out_tag_reg <= in_finish_tag;
out_len_reg <= len_mem_reg[in_finish_tag];
out_status_reg <= in_finish_status;
out_latency_reg <= count_reg - count_mem_reg[in_finish_tag];
out_valid_reg <= 1'b1;
end
if (rst) begin
count_reg <= 0;
out_tag_reg <= 0;
out_len_reg <= 0;
out_status_reg <= 0;
out_latency_reg <= 0;
out_valid_reg <= 0;
end
end
endmodule |
module dma_bench_pcie_us #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream RC tuser signal width
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
// PCIe AXI stream RQ tuser signal width
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
// PCIe AXI stream CQ tuser signal width
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
// PCIe AXI stream CC tuser signal width
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
// RQ sequence number width
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
// RQ sequence number tracking enable
parameter RQ_SEQ_NUM_ENABLE = 1,
// Immediate enable
parameter IMM_ENABLE = 1,
// Immediate width
parameter IMM_WIDTH = 32,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Operation table size (read)
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter PCIE_DMA_READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (read)
parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
// In-flight transmit limit (write)
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (write)
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* AXI input (RC)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tvalid,
output wire s_axis_rc_tready,
input wire s_axis_rc_tlast,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
/*
* AXI output (RQ)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tvalid,
input wire m_axis_rq_tready,
output wire m_axis_rq_tlast,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
/*
* AXI input (CQ)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tvalid,
output wire s_axis_cq_tready,
input wire s_axis_cq_tlast,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
/*
* AXI output (CC)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tvalid,
input wire m_axis_cc_tready,
output wire m_axis_cc_tlast,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
/*
* Transmit sequence number input
*/
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
/*
* Flow control
*/
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
/*
* Configuration
*/
input wire [2:0] cfg_max_read_req,
input wire [2:0] cfg_max_payload,
/*
* Configuration interface
*/
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
/*
* Interrupt interface
*/
input wire [3:0] cfg_interrupt_msi_enable,
input wire [7:0] cfg_interrupt_msi_vf_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [7:0] cfg_interrupt_msi_function_number,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32;
parameter TLP_HDR_WIDTH = 128;
parameter TLP_SEG_COUNT = 1;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
parameter TX_SEQ_NUM_ENABLE = RQ_SEQ_NUM_ENABLE;
parameter PF_COUNT = 1;
parameter VF_COUNT = 0;
parameter F_COUNT = PF_COUNT+VF_COUNT;
parameter MSI_COUNT = 32;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_rd_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_wr_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire [MSI_COUNT-1:0] msi_irq;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.F_COUNT(PF_COUNT+VF_COUNT),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSIX_ENABLE(0),
.MSI_ENABLE(1),
.MSI_COUNT(MSI_COUNT)
)
pcie_us_if_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
dma_bench_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0),
.BAR0_APERTURE(BAR0_APERTURE)
)
dma_bench_pcie_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (completion)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP output (read request)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* Configuration
*/
.bus_num(8'd0),
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor),
/*
* MSI request outputs
*/
.msi_irq(msi_irq)
);
endmodule |
module dma_bench_pcie_s10 #
(
// H-tile segment count
parameter SEG_COUNT = 1,
// H-tile segment data width
parameter SEG_DATA_WIDTH = 256,
// H-tile segment empty signal width
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
// Immediate enable
parameter IMM_ENABLE = 1,
// Immediate width
parameter IMM_WIDTH = 32,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 6,
// TX sequence number tracking enable
parameter TX_SEQ_NUM_ENABLE = 1,
// Tile selection (0 for H-Tile, 1 for L-Tile)
parameter L_TILE = 0,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Operation table size (read)
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* H-tile RX AVST interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
/*
* H-tile TX AVST interface
*/
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
/*
* H-tile TX flow control
*/
input wire [7:0] tx_ph_cdts,
input wire [11:0] tx_pd_cdts,
input wire [7:0] tx_nph_cdts,
input wire [11:0] tx_npd_cdts,
input wire [7:0] tx_cplh_cdts,
input wire [11:0] tx_cpld_cdts,
input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
/*
* H-tile MSI interrupt interface
*/
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
/*
* H-tile configuration interface
*/
input wire [31:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [1:0] tl_cfg_func,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32;
parameter TLP_HDR_WIDTH = 128;
parameter TLP_SEG_COUNT = 1;
parameter TX_SEQ_NUM_COUNT = SEG_COUNT;
parameter PF_COUNT = 1;
parameter VF_COUNT = 0;
parameter F_COUNT = PF_COUNT+VF_COUNT;
parameter MSI_COUNT = 32;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_rd_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_wr_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire [7:0] bus_num;
wire [2:0] max_read_request_size;
wire [2:0] max_payload_size;
wire [MSI_COUNT-1:0] msi_irq;
pcie_s10_if #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.L_TILE(L_TILE),
.PF_COUNT(1),
.VF_COUNT(0),
.F_COUNT(PF_COUNT+VF_COUNT),
.IO_BAR_INDEX(5),
.MSI_ENABLE(1),
.MSI_COUNT(MSI_COUNT)
)
pcie_s10_if_inst (
.clk(clk),
.rst(rst),
/*
* H-Tile/L-Tile RX AVST interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
/*
* H-Tile/L-Tile TX AVST interface
*/
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
/*
* H-Tile/L-Tile TX flow control
*/
.tx_ph_cdts(tx_ph_cdts),
.tx_pd_cdts(tx_pd_cdts),
.tx_nph_cdts(tx_nph_cdts),
.tx_npd_cdts(tx_npd_cdts),
.tx_cplh_cdts(tx_cplh_cdts),
.tx_cpld_cdts(tx_cpld_cdts),
.tx_hdr_cdts_consumed(tx_hdr_cdts_consumed),
.tx_data_cdts_consumed(tx_data_cdts_consumed),
.tx_cdts_type(tx_cdts_type),
.tx_cdts_data_value(tx_cdts_data_value),
/*
* H-Tile/L-Tile MSI interrupt interface
*/
.app_msi_req(app_msi_req),
.app_msi_ack(app_msi_ack),
.app_msi_tc(app_msi_tc),
.app_msi_num(app_msi_num),
.app_msi_func_num(app_msi_func_num),
/*
* H-Tile/L-Tile configuration interface
*/
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (write request from MSI)
*/
.tx_msi_wr_req_tlp_data(0),
.tx_msi_wr_req_tlp_strb(0),
.tx_msi_wr_req_tlp_hdr(0),
.tx_msi_wr_req_tlp_valid(0),
.tx_msi_wr_req_tlp_sop(0),
.tx_msi_wr_req_tlp_eop(0),
.tx_msi_wr_req_tlp_ready(),
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.bus_num(bus_num),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
.msix_enable(),
.msix_mask(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
dma_bench_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_READ_TX_FC_ENABLE(PCIE_DMA_READ_TX_FC_ENABLE),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.PCIE_DMA_WRITE_TX_FC_ENABLE(PCIE_DMA_WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(0),
.CHECK_BUS_NUMBER(1),
.BAR0_APERTURE(BAR0_APERTURE)
)
dma_bench_pcie_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (completion)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP output (read request)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* Configuration
*/
.bus_num(bus_num),
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor),
/*
* MSI request outputs
*/
.msi_irq(msi_irq)
);
endmodule |
module pcie_us_if_cc #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream CC tuser signal width
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
/*
* AXI output (CC)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tvalid,
input wire m_axis_cc_tready,
output wire m_axis_cc_tlast,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
/*
* TLP input (completion from BAR)
*/
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready
);
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXIS_PCIE_DATA_WIDTH == 512) begin
if (AXIS_PCIE_CC_USER_WIDTH != 81) begin
$error("Error: PCIe CC tuser width must be 81 (instance %m)");
$finish;
end
end else begin
if (AXIS_PCIE_CC_USER_WIDTH != 33) begin
$error("Error: PCIe CC tuser width must be 33 (instance %m)");
$finish;
end
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
end
localparam [2:0]
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
localparam [2:0]
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
reg tx_cpl_tlp_ready_cmb;
assign tx_cpl_tlp_ready = tx_cpl_tlp_ready_cmb;
// process outgoing TLPs
localparam [1:0]
TLP_OUTPUT_STATE_IDLE = 2'd0,
TLP_OUTPUT_STATE_HEADER = 2'd1,
TLP_OUTPUT_STATE_PAYLOAD = 2'd2;
reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
reg [2:0] tx_cpl_tlp_hdr_fmt;
reg [4:0] tx_cpl_tlp_hdr_type;
reg [2:0] tx_cpl_tlp_hdr_tc;
reg tx_cpl_tlp_hdr_ln;
reg tx_cpl_tlp_hdr_th;
reg tx_cpl_tlp_hdr_td;
reg tx_cpl_tlp_hdr_ep;
reg [2:0] tx_cpl_tlp_hdr_attr;
reg [1:0] tx_cpl_tlp_hdr_at;
reg [9:0] tx_cpl_tlp_hdr_length;
reg [15:0] tx_cpl_tlp_hdr_completer_id;
reg [2:0] tx_cpl_tlp_hdr_cpl_status;
reg tx_cpl_tlp_hdr_bcm;
reg [11:0] tx_cpl_tlp_hdr_byte_count;
reg [15:0] tx_cpl_tlp_hdr_requester_id;
reg [9:0] tx_cpl_tlp_hdr_tag;
reg [6:0] tx_cpl_tlp_hdr_lower_addr;
reg [95:0] tlp_header_data;
reg [AXIS_PCIE_CC_USER_WIDTH-1:0] tlp_tuser;
reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int = 0;
reg m_axis_cc_tvalid_int = 0;
wire m_axis_cc_tready_int;
reg m_axis_cc_tlast_int = 0;
reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_int = 0;
always @* begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
out_tlp_data_next = out_tlp_data_reg;
out_tlp_strb_next = out_tlp_strb_reg;
out_tlp_eop_next = out_tlp_eop_reg;
tx_cpl_tlp_ready_cmb = 1'b0;
// TLP header parsing
// DW 0
tx_cpl_tlp_hdr_fmt = tx_cpl_tlp_hdr[127:125]; // fmt
tx_cpl_tlp_hdr_type = tx_cpl_tlp_hdr[124:120]; // type
tx_cpl_tlp_hdr_tag[9] = tx_cpl_tlp_hdr[119]; // T9
tx_cpl_tlp_hdr_tc = tx_cpl_tlp_hdr[118:116]; // TC
tx_cpl_tlp_hdr_tag[8] = tx_cpl_tlp_hdr[115]; // T8
tx_cpl_tlp_hdr_attr[2] = tx_cpl_tlp_hdr[114]; // attr
tx_cpl_tlp_hdr_ln = tx_cpl_tlp_hdr[113]; // LN
tx_cpl_tlp_hdr_th = tx_cpl_tlp_hdr[112]; // TH
tx_cpl_tlp_hdr_td = tx_cpl_tlp_hdr[111]; // TD
tx_cpl_tlp_hdr_ep = tx_cpl_tlp_hdr[110]; // EP
tx_cpl_tlp_hdr_attr[1:0] = tx_cpl_tlp_hdr[109:108]; // attr
tx_cpl_tlp_hdr_at = tx_cpl_tlp_hdr[107:106]; // AT
tx_cpl_tlp_hdr_length = tx_cpl_tlp_hdr[105:96]; // length
// DW 1
tx_cpl_tlp_hdr_completer_id = tx_cpl_tlp_hdr[95:80]; // completer ID
tx_cpl_tlp_hdr_cpl_status = tx_cpl_tlp_hdr[79:77]; // completion status
tx_cpl_tlp_hdr_bcm = tx_cpl_tlp_hdr[76]; // BCM
tx_cpl_tlp_hdr_byte_count = tx_cpl_tlp_hdr[75:64]; // byte count
// DW 2
tx_cpl_tlp_hdr_requester_id = tx_cpl_tlp_hdr[63:48]; // requester ID
tx_cpl_tlp_hdr_tag[7:0] = tx_cpl_tlp_hdr[47:40]; // tag
tx_cpl_tlp_hdr_lower_addr = tx_cpl_tlp_hdr[38:32]; // lower address
tlp_header_data[6:0] = tx_cpl_tlp_hdr_lower_addr; // lower address
tlp_header_data[7] = 1'b0;
tlp_header_data[9:8] = tx_cpl_tlp_hdr_at; // AT
tlp_header_data[15:10] = 6'd0;
tlp_header_data[28:16] = tx_cpl_tlp_hdr_byte_count; // Byte count
tlp_header_data[29] = 1'b0; // locked read completion
tlp_header_data[31:30] = 2'd0;
tlp_header_data[42:32] = tx_cpl_tlp_hdr_length; // DWORD count
tlp_header_data[45:43] = tx_cpl_tlp_hdr_cpl_status; // completion status
tlp_header_data[46] = tx_cpl_tlp_hdr_ep; // poisoned
tlp_header_data[47] = 1'b0;
tlp_header_data[63:48] = tx_cpl_tlp_hdr_requester_id; // requester ID
tlp_header_data[71:64] = tx_cpl_tlp_hdr_tag; // tag
tlp_header_data[87:72] = tx_cpl_tlp_hdr_completer_id; // completer ID
tlp_header_data[88] = 1'b0; // completer ID enable
tlp_header_data[91:89] = tx_cpl_tlp_hdr_tc; // TC
tlp_header_data[94:92] = tx_cpl_tlp_hdr_attr; // attr
tlp_header_data[95] = 1'b0; // force ECRC
if (AXIS_PCIE_DATA_WIDTH == 512) begin
tlp_tuser[1:0] = 2'b01; // is_sop
tlp_tuser[3:2] = 2'd0; // is_sop0_ptr
tlp_tuser[5:4] = 2'd0; // is_sop1_ptr
tlp_tuser[7:6] = 2'b01; // is_eop
tlp_tuser[11:8] = 4'd3; // is_eop0_ptr
tlp_tuser[15:12] = 4'd0; // is_eop1_ptr
tlp_tuser[16] = 1'b0; // discontinue
tlp_tuser[80:17] = 64'd0; // parity
end else begin
tlp_tuser[0] = 1'b0; // discontinue
tlp_tuser[32:1] = 32'd0; // parity
end
// TLP output
m_axis_cc_tdata_int = 0;
m_axis_cc_tkeep_int = 0;
m_axis_cc_tvalid_int = 1'b0;
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = 0;
// combine header and payload, merge in read request TLPs
case (tlp_output_state_reg)
TLP_OUTPUT_STATE_IDLE: begin
// idle state
if (tx_cpl_tlp_valid && m_axis_cc_tready_int) begin
if (AXIS_PCIE_DATA_WIDTH == 64) begin
// 64 bit interface, send first half of header
m_axis_cc_tdata_int = tlp_header_data[63:0];
m_axis_cc_tkeep_int = 2'b11;
m_axis_cc_tvalid_int = 1'b1;
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = tlp_tuser;
tlp_output_state_next = TLP_OUTPUT_STATE_HEADER;
end else begin
// wider interface, send header and start of payload
m_axis_cc_tdata_int = {tx_cpl_tlp_data, tlp_header_data};
m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, 3'b111};
m_axis_cc_tvalid_int = 1'b1;
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = tlp_tuser;
tx_cpl_tlp_ready_cmb = 1'b1;
out_tlp_data_next = tx_cpl_tlp_data;
out_tlp_strb_next = tx_cpl_tlp_strb;
out_tlp_eop_next = tx_cpl_tlp_eop;
if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
m_axis_cc_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end
end
TLP_OUTPUT_STATE_HEADER: begin
// second cycle of header (64 bit interface width only)
if (AXIS_PCIE_DATA_WIDTH == 64) begin
m_axis_cc_tdata_int = {tx_cpl_tlp_data, tlp_header_data[95:64]};
m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, 1'b1};
m_axis_cc_tvalid_int = 1'b1;
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = tlp_tuser;
tx_cpl_tlp_ready_cmb = 1'b1;
out_tlp_data_next = tx_cpl_tlp_data;
out_tlp_strb_next = tx_cpl_tlp_strb;
out_tlp_eop_next = tx_cpl_tlp_eop;
if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-1)) == 0)) begin
m_axis_cc_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end
end
TLP_OUTPUT_STATE_PAYLOAD: begin
// transfer payload
if (AXIS_PCIE_DATA_WIDTH >= 128) begin
m_axis_cc_tdata_int = {tx_cpl_tlp_data, out_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
if (tx_cpl_tlp_valid && !out_tlp_eop_reg) begin
m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-3]};
end else begin
m_axis_cc_tkeep_int = out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-3];
end
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = tlp_tuser;
if ((tx_cpl_tlp_valid || out_tlp_eop_reg) && m_axis_cc_tready_int) begin
m_axis_cc_tvalid_int = 1'b1;
tx_cpl_tlp_ready_cmb = !out_tlp_eop_reg;
out_tlp_data_next = tx_cpl_tlp_data;
out_tlp_strb_next = tx_cpl_tlp_strb;
out_tlp_eop_next = tx_cpl_tlp_eop;
if (out_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
m_axis_cc_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end else begin
m_axis_cc_tdata_int = {tx_cpl_tlp_data, out_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-32]};
if (tx_cpl_tlp_valid && !out_tlp_eop_reg) begin
m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-1]};
end else begin
m_axis_cc_tkeep_int = out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-1];
end
m_axis_cc_tlast_int = 1'b0;
m_axis_cc_tuser_int = tlp_tuser;
if ((tx_cpl_tlp_valid || out_tlp_eop_reg) && m_axis_cc_tready_int) begin
m_axis_cc_tvalid_int = 1'b1;
tx_cpl_tlp_ready_cmb = !out_tlp_eop_reg;
out_tlp_data_next = tx_cpl_tlp_data;
out_tlp_strb_next = tx_cpl_tlp_strb;
out_tlp_eop_next = tx_cpl_tlp_eop;
if (out_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-1)) == 0))) begin
m_axis_cc_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
end
end
end
endcase
end
always @(posedge clk) begin
tlp_output_state_reg <= tlp_output_state_next;
out_tlp_data_reg <= out_tlp_data_next;
out_tlp_strb_reg <= out_tlp_strb_next;
out_tlp_eop_reg <= out_tlp_eop_next;
if (rst) begin
tlp_output_state_reg <= TLP_OUTPUT_STATE_IDLE;
end
end
// output datapath logic (PCIe TLP)
reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}};
reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}};
reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next;
reg m_axis_cc_tlast_reg = 1'b0;
reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed" *)
reg [AXIS_PCIE_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg [AXIS_PCIE_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg [AXIS_PCIE_CC_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign m_axis_cc_tready_int = !out_fifo_half_full_reg;
assign m_axis_cc_tdata = m_axis_cc_tdata_reg;
assign m_axis_cc_tkeep = m_axis_cc_tkeep_reg;
assign m_axis_cc_tvalid = m_axis_cc_tvalid_reg;
assign m_axis_cc_tlast = m_axis_cc_tlast_reg;
assign m_axis_cc_tuser = m_axis_cc_tuser_reg;
always @(posedge clk) begin
m_axis_cc_tvalid_reg <= m_axis_cc_tvalid_reg && !m_axis_cc_tready;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_cc_tvalid_int) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tdata_int;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tkeep_int;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tlast_int;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tuser_int;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_cc_tvalid_reg || m_axis_cc_tready)) begin
m_axis_cc_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_cc_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_cc_tvalid_reg <= 1'b1;
m_axis_cc_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_cc_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_cc_tvalid_reg <= 1'b0;
end
end
endmodule |
module pcie_s10_if_rx #
(
// H-Tile/L-Tile AVST segment count
parameter SEG_COUNT = 1,
// H-Tile/L-Tile AVST segment data width
parameter SEG_DATA_WIDTH = 256,
// H-Tile/L-Tile AVST segment empty signal width
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
// TLP data width
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// IO bar index
// rx_st_bar_range = 6 is mapped to IO_BAR_INDEX on rx_req_tlp_bar_id
parameter IO_BAR_INDEX = 5
)
(
input wire clk,
input wire rst,
// H-Tile/L-Tile RX AVST interface
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
/*
* TLP output (request to BAR)
*/
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
input wire rx_req_tlp_ready,
/*
* TLP output (completion to DMA)
*/
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready
);
parameter SEG_STRB_WIDTH = SEG_DATA_WIDTH/32;
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
parameter OUTPUT_FIFO_LIMIT = 8;
// bus width assertions
initial begin
if (SEG_COUNT != 1) begin
$error("Error: segment count must be 1 (instance %m)");
$finish;
end
if (SEG_DATA_WIDTH != 256) begin
$error("Error: segment data width must be 256 (instance %m)");
$finish;
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
end
localparam [1:0]
TLP_INPUT_STATE_IDLE = 2'd0,
TLP_INPUT_STATE_HEADER = 2'd1,
TLP_INPUT_STATE_PAYLOAD = 2'd2;
reg [1:0] tlp_input_state_reg = TLP_INPUT_STATE_IDLE, tlp_input_state_next;
reg payload_offset_reg = 0, payload_offset_next;
reg cpl_reg = 1'b0, cpl_next;
// internal datapath
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_int;
wire rx_req_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_int;
wire rx_cpl_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_int;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data_int_reg = 0, rx_st_data_int_next;
reg [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty_int_reg = 0, rx_st_empty_int_next;
reg [SEG_COUNT*SEG_STRB_WIDTH-1:0] rx_st_strb_int_reg = 0, rx_st_strb_int_next;
reg [SEG_COUNT-1:0] rx_st_sop_int_reg = 0, rx_st_sop_int_next;
reg [SEG_COUNT-1:0] rx_st_eop_int_reg = 0, rx_st_eop_int_next;
reg [SEG_COUNT-1:0] rx_st_valid_int_reg = 0, rx_st_valid_int_next;
reg [SEG_COUNT-1:0] rx_st_vf_active_int_reg = 0, rx_st_vf_active_int_next;
reg [SEG_COUNT*2-1:0] rx_st_func_num_int_reg = 0, rx_st_func_num_int_next;
reg [SEG_COUNT*11-1:0] rx_st_vf_num_int_reg = 0, rx_st_vf_num_int_next;
reg [SEG_COUNT*3-1:0] rx_st_bar_range_int_reg = 0, rx_st_bar_range_int_next;
wire [SEG_COUNT*SEG_STRB_WIDTH] rx_st_strb = rx_st_eop ? {SEG_STRB_WIDTH{1'b1}} >> rx_st_empty : {SEG_STRB_WIDTH{1'b1}};
wire [SEG_COUNT*SEG_DATA_WIDTH*2-1:0] rx_st_data_full = {rx_st_data, rx_st_data_int_reg};
wire [SEG_COUNT*SEG_STRB_WIDTH*2-1:0] rx_st_strb_full = {rx_st_strb, rx_st_strb_int_reg};
assign rx_st_ready = rx_req_tlp_ready_int && rx_cpl_tlp_ready_int;
always @* begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
payload_offset_next = payload_offset_reg;
cpl_next = cpl_reg;
if (payload_offset_reg) begin
rx_req_tlp_data_int = rx_st_data_full >> 128;
rx_req_tlp_strb_int = rx_st_strb_full >> 4;
end else begin
rx_req_tlp_data_int = rx_st_data_full >> 96;
rx_req_tlp_strb_int = rx_st_strb_full >> 3;
end
rx_req_tlp_hdr_int[127:96] = rx_st_data_full[31:0];
rx_req_tlp_hdr_int[95:64] = rx_st_data_full[63:32];
rx_req_tlp_hdr_int[63:32] = rx_st_data_full[95:64];
rx_req_tlp_hdr_int[31:0] = rx_st_data_full[127:96];
if (rx_st_bar_range == 6) begin
// IO BAR
rx_req_tlp_bar_id_int = IO_BAR_INDEX;
end else if (rx_st_bar_range == 7) begin
// expansion ROM BAR
rx_req_tlp_bar_id_int = 6;
end else begin
// memory BAR
rx_req_tlp_bar_id_int = rx_st_bar_range;
end
rx_req_tlp_func_num_int = rx_st_func_num;
rx_req_tlp_valid_int = 1'b0;
rx_req_tlp_sop_int = 1'b1;
rx_req_tlp_eop_int = 1'b1;
rx_cpl_tlp_valid_int = 1'b0;
rx_st_data_int_next = rx_st_data_int_reg;
rx_st_strb_int_next = rx_st_strb_int_reg;
rx_st_empty_int_next = rx_st_empty_int_reg;
rx_st_sop_int_next = rx_st_sop_int_reg;
rx_st_eop_int_next = rx_st_eop_int_reg;
rx_st_valid_int_next = rx_st_valid_int_reg;
rx_st_vf_active_int_next = rx_st_vf_active_int_reg;
rx_st_func_num_int_next = rx_st_func_num_int_reg;
rx_st_vf_num_int_next = rx_st_vf_num_int_reg;
rx_st_bar_range_int_next = rx_st_bar_range_int_reg;
case (tlp_input_state_reg)
TLP_INPUT_STATE_IDLE: begin
if (rx_st_valid_int_reg) begin
rx_req_tlp_hdr_int[127:96] = rx_st_data_full[31:0];
rx_req_tlp_hdr_int[95:64] = rx_st_data_full[63:32];
rx_req_tlp_hdr_int[63:32] = rx_st_data_full[95:64];
rx_req_tlp_hdr_int[31:0] = rx_st_data_full[127:96];
payload_offset_next = rx_st_data_full[29];
if (rx_st_bar_range == 6) begin
// IO BAR
rx_req_tlp_bar_id_int = IO_BAR_INDEX;
end else if (rx_st_bar_range == 7) begin
// expansion ROM BAR
rx_req_tlp_bar_id_int = 6;
end else begin
// memory BAR
rx_req_tlp_bar_id_int = rx_st_bar_range;
end
rx_req_tlp_func_num_int = rx_st_func_num;
if (payload_offset_next) begin
rx_req_tlp_data_int = rx_st_data_full >> 128;
rx_req_tlp_strb_int = rx_st_strb_full >> 4;
end else begin
rx_req_tlp_data_int = rx_st_data_full >> 96;
rx_req_tlp_strb_int = rx_st_strb_full >> 3;
end
rx_req_tlp_sop_int = 1'b1;
rx_req_tlp_eop_int = 1'b0;
cpl_next = !rx_st_data_full[29] && rx_st_data_full[28:25] == 4'b0101;
if (rx_st_eop_int_reg) begin
rx_req_tlp_valid_int = !cpl_next;
rx_cpl_tlp_valid_int = cpl_next;
if (payload_offset_next) begin
rx_req_tlp_strb_int = rx_st_strb_int_reg >> 4;
end else begin
rx_req_tlp_strb_int = rx_st_strb_int_reg >> 3;
end
rx_req_tlp_eop_int = 1'b1;
rx_st_valid_int_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (rx_st_valid) begin
rx_req_tlp_valid_int = !cpl_next;
rx_cpl_tlp_valid_int = cpl_next;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end
TLP_INPUT_STATE_PAYLOAD: begin
if (rx_st_valid_int_reg) begin
if (payload_offset_reg) begin
rx_req_tlp_data_int = rx_st_data_full >> 128;
rx_req_tlp_strb_int = rx_st_strb_full >> 4;
end else begin
rx_req_tlp_data_int = rx_st_data_full >> 96;
rx_req_tlp_strb_int = rx_st_strb_full >> 3;
end
rx_req_tlp_sop_int = 1'b0;
rx_req_tlp_eop_int = 1'b0;
if (rx_st_eop_int_reg) begin
rx_req_tlp_valid_int = !cpl_reg;
rx_cpl_tlp_valid_int = cpl_reg;
if (payload_offset_next) begin
rx_req_tlp_strb_int = rx_st_strb_int_reg >> 4;
end else begin
rx_req_tlp_strb_int = rx_st_strb_int_reg >> 3;
end
rx_req_tlp_eop_int = 1'b1;
rx_st_valid_int_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (rx_st_valid) begin
rx_req_tlp_valid_int = !cpl_reg;
rx_cpl_tlp_valid_int = cpl_reg;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end
endcase
if (rx_st_valid) begin
rx_st_data_int_next = rx_st_data;
rx_st_empty_int_next = rx_st_empty;
rx_st_strb_int_next = rx_st_strb;
rx_st_sop_int_next = rx_st_sop;
rx_st_eop_int_next = rx_st_eop;
rx_st_valid_int_next = rx_st_valid;
rx_st_vf_active_int_next = rx_st_vf_active;
rx_st_func_num_int_next = rx_st_func_num;
rx_st_vf_num_int_next = rx_st_vf_num;
rx_st_bar_range_int_next = rx_st_bar_range;
end
end
always @(posedge clk) begin
tlp_input_state_reg <= tlp_input_state_next;
payload_offset_reg <= payload_offset_next;
cpl_reg <= cpl_next;
rx_st_data_int_reg <= rx_st_data_int_next;
rx_st_empty_int_reg <= rx_st_empty_int_next;
rx_st_strb_int_reg <= rx_st_strb_int_next;
rx_st_sop_int_reg <= rx_st_sop_int_next;
rx_st_eop_int_reg <= rx_st_eop_int_next;
rx_st_valid_int_reg <= rx_st_valid_int_next;
rx_st_vf_active_int_reg <= rx_st_vf_active_int_next;
rx_st_func_num_int_reg <= rx_st_func_num_int_next;
rx_st_vf_num_int_reg <= rx_st_vf_num_int_next;
rx_st_bar_range_int_reg <= rx_st_bar_range_int_next;
if (rst) begin
tlp_input_state_reg <= TLP_INPUT_STATE_IDLE;
rx_st_valid_int_reg <= 1'b0;
end
end
// output datapath logic (request TLP)
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_req_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_req_fifo_rd_ptr_reg = 0;
reg out_req_fifo_watermark_reg = 1'b0;
wire out_req_fifo_full = out_req_fifo_wr_ptr_reg == (out_req_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_req_fifo_empty = out_req_fifo_wr_ptr_reg == out_req_fifo_rd_ptr_reg;
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_DATA_WIDTH-1:0] out_req_fifo_rx_req_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_STRB_WIDTH-1:0] out_req_fifo_rx_req_tlp_strb[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_req_fifo_rx_req_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*3-1:0] out_req_fifo_rx_req_tlp_bar_id[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*8-1:0] out_req_fifo_rx_req_tlp_func_num[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign rx_req_tlp_ready_int = !out_req_fifo_watermark_reg;
assign rx_req_tlp_data = rx_req_tlp_data_reg;
assign rx_req_tlp_strb = rx_req_tlp_strb_reg;
assign rx_req_tlp_hdr = rx_req_tlp_hdr_reg;
assign rx_req_tlp_bar_id = rx_req_tlp_bar_id_reg;
assign rx_req_tlp_func_num = rx_req_tlp_func_num_reg;
assign rx_req_tlp_valid = rx_req_tlp_valid_reg;
assign rx_req_tlp_sop = rx_req_tlp_sop_reg;
assign rx_req_tlp_eop = rx_req_tlp_eop_reg;
always @(posedge clk) begin
rx_req_tlp_valid_reg <= rx_req_tlp_valid_reg && !rx_req_tlp_ready;
out_req_fifo_watermark_reg <= $unsigned(out_req_fifo_wr_ptr_reg - out_req_fifo_rd_ptr_reg) >= OUTPUT_FIFO_LIMIT;
if (!out_req_fifo_full && rx_req_tlp_valid_int) begin
out_req_fifo_rx_req_tlp_data[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_data_int;
out_req_fifo_rx_req_tlp_strb[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_strb_int;
out_req_fifo_rx_req_tlp_hdr[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_hdr_int;
out_req_fifo_rx_req_tlp_bar_id[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_bar_id_int;
out_req_fifo_rx_req_tlp_func_num[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_func_num_int;
out_req_fifo_rx_req_tlp_sop[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_sop_int;
out_req_fifo_rx_req_tlp_eop[out_req_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_eop_int;
out_req_fifo_wr_ptr_reg <= out_req_fifo_wr_ptr_reg + 1;
end
if (!out_req_fifo_empty && (!rx_req_tlp_valid_reg || rx_req_tlp_ready)) begin
rx_req_tlp_data_reg <= out_req_fifo_rx_req_tlp_data[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_strb_reg <= out_req_fifo_rx_req_tlp_strb[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_hdr_reg <= out_req_fifo_rx_req_tlp_hdr[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_bar_id_reg <= out_req_fifo_rx_req_tlp_bar_id[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_func_num_reg <= out_req_fifo_rx_req_tlp_func_num[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_sop_reg <= out_req_fifo_rx_req_tlp_sop[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_eop_reg <= out_req_fifo_rx_req_tlp_eop[out_req_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_req_tlp_valid_reg <= 1'b1;
out_req_fifo_rd_ptr_reg <= out_req_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_req_fifo_wr_ptr_reg <= 0;
out_req_fifo_rd_ptr_reg <= 0;
rx_req_tlp_valid_reg <= 1'b0;
end
end
// output datapath logic (completion TLP)
reg [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_cpl_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_cpl_fifo_rd_ptr_reg = 0;
reg out_cpl_fifo_watermark_reg = 1'b0;
wire out_cpl_fifo_full = out_cpl_fifo_wr_ptr_reg == (out_cpl_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_cpl_fifo_empty = out_cpl_fifo_wr_ptr_reg == out_cpl_fifo_rd_ptr_reg;
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_DATA_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_STRB_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_strb[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign rx_cpl_tlp_ready_int = !out_cpl_fifo_watermark_reg;
assign rx_cpl_tlp_data = rx_cpl_tlp_data_reg;
assign rx_cpl_tlp_strb = rx_cpl_tlp_strb_reg;
assign rx_cpl_tlp_hdr = rx_cpl_tlp_hdr_reg;
assign rx_cpl_tlp_error = 0;
assign rx_cpl_tlp_valid = rx_cpl_tlp_valid_reg;
assign rx_cpl_tlp_sop = rx_cpl_tlp_sop_reg;
assign rx_cpl_tlp_eop = rx_cpl_tlp_eop_reg;
always @(posedge clk) begin
rx_cpl_tlp_valid_reg <= rx_cpl_tlp_valid_reg && !rx_cpl_tlp_ready;
out_cpl_fifo_watermark_reg <= $unsigned(out_cpl_fifo_wr_ptr_reg - out_cpl_fifo_rd_ptr_reg) >= OUTPUT_FIFO_LIMIT;
if (!out_cpl_fifo_full && rx_cpl_tlp_valid_int) begin
out_cpl_fifo_rx_cpl_tlp_data[out_cpl_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_data_int;
out_cpl_fifo_rx_cpl_tlp_strb[out_cpl_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_strb_int;
out_cpl_fifo_rx_cpl_tlp_hdr[out_cpl_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_hdr_int;
out_cpl_fifo_rx_cpl_tlp_sop[out_cpl_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_sop_int;
out_cpl_fifo_rx_cpl_tlp_eop[out_cpl_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= rx_req_tlp_eop_int;
out_cpl_fifo_wr_ptr_reg <= out_cpl_fifo_wr_ptr_reg + 1;
end
if (!out_cpl_fifo_empty && (!rx_cpl_tlp_valid_reg || rx_cpl_tlp_ready)) begin
rx_cpl_tlp_data_reg <= out_cpl_fifo_rx_cpl_tlp_data[out_cpl_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_cpl_tlp_strb_reg <= out_cpl_fifo_rx_cpl_tlp_strb[out_cpl_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_cpl_tlp_hdr_reg <= out_cpl_fifo_rx_cpl_tlp_hdr[out_cpl_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_cpl_tlp_sop_reg <= out_cpl_fifo_rx_cpl_tlp_sop[out_cpl_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_cpl_tlp_eop_reg <= out_cpl_fifo_rx_cpl_tlp_eop[out_cpl_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
rx_cpl_tlp_valid_reg <= 1'b1;
out_cpl_fifo_rd_ptr_reg <= out_cpl_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_cpl_fifo_wr_ptr_reg <= 0;
out_cpl_fifo_rd_ptr_reg <= 0;
rx_cpl_tlp_valid_reg <= 1'b0;
end
end
endmodule |
module pcie_tlp_demux_bar #
(
// Output count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// Base BAR
parameter BAR_BASE = 0,
// BAR stride
parameter BAR_STRIDE = 1,
// Explicit BAR numbers (set to 0 to use base/stride)
parameter BAR_IDS = 0
)
(
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
/*
* TLP output
*/
output wire [PORTS*TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
/*
* Control
*/
input wire enable
);
// default BAR number computation
function [PORTS*3-1:0] calcBarIds(input [2:0] base, input [2:0] stride);
integer i;
reg [2:0] bar;
begin
calcBarIds = {PORTS*3{1'b0}};
bar = base;
for (i = 0; i < PORTS; i = i + 1) begin
calcBarIds[i*3 +: 3] = bar;
bar = bar + stride;
end
end
endfunction
parameter BAR_IDS_INT = BAR_IDS ? BAR_IDS : calcBarIds(BAR_BASE, BAR_STRIDE);
integer i, j;
// check configuration
initial begin
for (i = 0; i < PORTS; i = i + 1) begin
if (BAR_IDS_INT[i*3 +: 3] > 5) begin
$error("Error: BAR out of range (instance %m)");
$finish;
end
end
for (i = 0; i < PORTS; i = i + 1) begin
for (j = i+1; j < PORTS; j = j + 1) begin
if (BAR_IDS_INT[i*3 +: 3] == BAR_IDS_INT[j*3 +: 3]) begin
$display("Duplicate BAR:");
$display("%d: %d", i, BAR_IDS_INT[i*3 +: 3]);
$display("%d: %d", j, BAR_IDS_INT[j*3 +: 3]);
$error("Error: Duplicate BAR (instance %m)");
$finish;
end
end
end
end
wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id;
wire [TLP_SEG_COUNT-1:0] drop;
wire [TLP_SEG_COUNT*PORTS-1:0] select;
generate
genvar m, n;
for (n = 0; n < TLP_SEG_COUNT; n = n + 1) begin
for (m = 0; m < PORTS; m = m + 1) begin
assign select[n*PORTS+m] = match_tlp_bar_id[n*3 +: 3] == BAR_IDS_INT[m*3 +: 3];
end
assign drop[n] = select[n*PORTS +: PORTS] == 0;
end
endgenerate
pcie_tlp_demux #(
.PORTS(PORTS),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_tlp_demux_inst (
.clk(clk),
.rst(rst),
/*
* TLP input
*/
.in_tlp_data(in_tlp_data),
.in_tlp_strb(in_tlp_strb),
.in_tlp_hdr(in_tlp_hdr),
.in_tlp_seq(0),
.in_tlp_bar_id(in_tlp_bar_id),
.in_tlp_func_num(in_tlp_func_num),
.in_tlp_error(in_tlp_error),
.in_tlp_valid(in_tlp_valid),
.in_tlp_sop(in_tlp_sop),
.in_tlp_eop(in_tlp_eop),
.in_tlp_ready(in_tlp_ready),
/*
* TLP output
*/
.out_tlp_data(out_tlp_data),
.out_tlp_strb(out_tlp_strb),
.out_tlp_hdr(out_tlp_hdr),
.out_tlp_seq(),
.out_tlp_bar_id(out_tlp_bar_id),
.out_tlp_func_num(out_tlp_func_num),
.out_tlp_error(out_tlp_error),
.out_tlp_valid(out_tlp_valid),
.out_tlp_sop(out_tlp_sop),
.out_tlp_eop(out_tlp_eop),
.out_tlp_ready(out_tlp_ready),
/*
* Fields
*/
.match_tlp_hdr(),
.match_tlp_bar_id(match_tlp_bar_id),
.match_tlp_func_num(),
/*
* Control
*/
.enable(enable),
.drop(drop),
.select(select)
);
endmodule |
module pcie_s10_if_tx #
(
// H-Tile/L-Tile AVST segment count
parameter SEG_COUNT = 1,
// H-Tile/L-Tile AVST segment data width
parameter SEG_DATA_WIDTH = 256,
// TLP data width
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 6
)
(
input wire clk,
input wire rst,
// H-Tile/L-Tile TX AVST interface
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
/*
* Transmit sequence number output (DMA read request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
/*
* TLP input (write request from DMA)
*/
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number output (DMA write request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
/*
* TLP input (completion from BAR)
*/
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready,
/*
* TLP input (write request from MSI)
*/
input wire [TLP_DATA_WIDTH-1:0] tx_msi_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_msi_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_eop,
output wire tx_msi_wr_req_tlp_ready
);
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
parameter FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (SEG_COUNT != 1) begin
$error("Error: segment count must be 1 (instance %m)");
$finish;
end
if (SEG_DATA_WIDTH != 256) begin
$error("Error: segment data width must be 256 (instance %m)");
$finish;
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
end
localparam [0:0]
WR_REQ_STATE_IDLE = 1'd0,
WR_REQ_STATE_PAYLOAD = 1'd1;
reg [0:0] wr_req_state_reg = WR_REQ_STATE_IDLE, wr_req_state_next;
localparam [0:0]
CPL_STATE_IDLE = 1'd0,
CPL_STATE_PAYLOAD = 1'd1;
reg [0:0] cpl_state_reg = CPL_STATE_IDLE, cpl_state_next;
localparam [1:0]
TLP_OUTPUT_STATE_IDLE = 2'd0,
TLP_OUTPUT_STATE_WR_PAYLOAD = 2'd1,
TLP_OUTPUT_STATE_CPL_PAYLOAD = 2'd2;
reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg wr_req_payload_offset_reg = 1'b0, wr_req_payload_offset_next;
reg [TLP_DATA_WIDTH-1:0] wr_req_tlp_data_reg = 0, wr_req_tlp_data_next;
reg [TLP_SEG_COUNT-1:0] wr_req_tlp_eop_reg = 0, wr_req_tlp_eop_next;
reg [TLP_DATA_WIDTH-1:0] cpl_tlp_data_reg = 0, cpl_tlp_data_next;
reg [TLP_SEG_COUNT-1:0] cpl_tlp_eop_reg = 0, cpl_tlp_eop_next;
reg tx_rd_req_tlp_ready_reg = 1'b0, tx_rd_req_tlp_ready_next;
reg tx_wr_req_tlp_ready_reg = 1'b0, tx_wr_req_tlp_ready_next;
reg tx_cpl_tlp_ready_reg = 1'b0, tx_cpl_tlp_ready_next;
reg tx_msi_wr_req_tlp_ready_reg = 1'b0, tx_msi_wr_req_tlp_ready_next;
reg [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num_reg = 0, m_axis_rd_req_tx_seq_num_next;
reg [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid_reg = 0, m_axis_rd_req_tx_seq_num_valid_next;
reg [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num_reg = 0, m_axis_wr_req_tx_seq_num_next;
reg [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid_reg = 0, m_axis_wr_req_tx_seq_num_valid_next;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data_reg = 0, tx_st_data_next;
reg [SEG_COUNT-1:0] tx_st_sop_reg = 0, tx_st_sop_next;
reg [SEG_COUNT-1:0] tx_st_eop_reg = 0, tx_st_eop_next;
reg [SEG_COUNT-1:0] tx_st_valid_reg = 0, tx_st_valid_next;
reg [1:0] tx_st_ready_delay_reg = 0;
assign tx_rd_req_tlp_ready = tx_rd_req_tlp_ready_reg;
assign tx_wr_req_tlp_ready = tx_wr_req_tlp_ready_reg;
assign tx_cpl_tlp_ready = tx_cpl_tlp_ready_reg;
assign tx_msi_wr_req_tlp_ready = tx_msi_wr_req_tlp_ready_reg;
assign m_axis_rd_req_tx_seq_num = m_axis_rd_req_tx_seq_num_reg;
assign m_axis_rd_req_tx_seq_num_valid = m_axis_rd_req_tx_seq_num_valid_reg;
assign m_axis_wr_req_tx_seq_num = m_axis_wr_req_tx_seq_num_reg;
assign m_axis_wr_req_tx_seq_num_valid = m_axis_wr_req_tx_seq_num_valid_reg;
assign tx_st_data = tx_st_data_reg;
assign tx_st_sop = tx_st_sop_reg;
assign tx_st_eop = tx_st_eop_reg;
assign tx_st_valid = tx_st_valid_reg;
assign tx_st_err = 0;
// read request FIFO
reg [FIFO_ADDR_WIDTH+1-1:0] rd_req_fifo_wr_ptr_reg = 0;
reg [FIFO_ADDR_WIDTH+1-1:0] rd_req_fifo_rd_ptr_reg = 0, rd_req_fifo_rd_ptr_next;
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_seq[(2**FIFO_ADDR_WIDTH)-1:0];
reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_wr_data;
reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_wr_seq;
reg rd_req_fifo_we;
reg rd_req_fifo_watermark_reg = 1'b0;
reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_rd_data_reg = 0, rd_req_fifo_rd_data_next;
reg rd_req_fifo_rd_valid_reg = 0, rd_req_fifo_rd_valid_next;
reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_rd_seq_reg = 0, rd_req_fifo_rd_seq_next;
// write request FIFO
reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_wr_ptr_reg = 0;
reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_wr_ptr_cur_reg = 0;
reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_rd_ptr_reg = 0, wr_req_fifo_rd_ptr_next;
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT-1:0] wr_req_fifo_eop[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT-1:0] wr_req_fifo_valid[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_seq[(2**FIFO_ADDR_WIDTH)-1:0];
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_wr_data;
reg [SEG_COUNT-1:0] wr_req_fifo_wr_eop;
reg [SEG_COUNT-1:0] wr_req_fifo_wr_valid;
reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_wr_seq;
reg wr_req_fifo_we;
reg wr_req_fifo_watermark_reg = 1'b0;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_rd_data_reg = 0, wr_req_fifo_rd_data_next;
reg [SEG_COUNT-1:0] wr_req_fifo_rd_eop_reg = 0, wr_req_fifo_rd_eop_next;
reg [SEG_COUNT-1:0] wr_req_fifo_rd_valid_reg = 0, wr_req_fifo_rd_valid_next;
reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_rd_seq_reg = 0, wr_req_fifo_rd_seq_next;
// completion FIFO
reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_wr_ptr_reg = 0;
reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_wr_ptr_cur_reg = 0;
reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_rd_ptr_reg = 0, cpl_fifo_rd_ptr_next;
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT-1:0] cpl_fifo_eop[(2**FIFO_ADDR_WIDTH)-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [SEG_COUNT-1:0] cpl_fifo_valid[(2**FIFO_ADDR_WIDTH)-1:0];
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_wr_data;
reg [SEG_COUNT-1:0] cpl_fifo_wr_eop;
reg [SEG_COUNT-1:0] cpl_fifo_wr_valid;
reg cpl_fifo_we;
reg cpl_fifo_watermark_reg = 1'b0;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_rd_data_reg = 0, cpl_fifo_rd_data_next;
reg [SEG_COUNT-1:0] cpl_fifo_rd_eop_reg = 0, cpl_fifo_rd_eop_next;
reg [SEG_COUNT-1:0] cpl_fifo_rd_valid_reg = 0, cpl_fifo_rd_valid_next;
// MSI write request register
reg [SEG_DATA_WIDTH-1:0] msi_wr_req_data_reg = 0, msi_wr_req_data_next;
reg msi_wr_req_valid_reg = 0, msi_wr_req_valid_next;
// Read request processing
always @* begin
tx_rd_req_tlp_ready_next = 1'b0;
rd_req_fifo_wr_data[31:0] = tx_rd_req_tlp_hdr[127:96];
rd_req_fifo_wr_data[63:32] = tx_rd_req_tlp_hdr[95:64];
rd_req_fifo_wr_data[95:64] = tx_rd_req_tlp_hdr[63:32];
rd_req_fifo_wr_data[127:96] = tx_rd_req_tlp_hdr[31:0];
rd_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:128] = 0;
rd_req_fifo_wr_seq = tx_rd_req_tlp_seq;
rd_req_fifo_we = 0;
tx_rd_req_tlp_ready_next = !cpl_fifo_watermark_reg;
if (tx_rd_req_tlp_valid && tx_rd_req_tlp_ready) begin
// send complete header (read request)
rd_req_fifo_we = 1;
end
end
// Write request processing
always @* begin
wr_req_state_next = WR_REQ_STATE_IDLE;
wr_req_payload_offset_next = wr_req_payload_offset_reg;
wr_req_tlp_data_next = wr_req_tlp_data_reg;
wr_req_tlp_eop_next = wr_req_tlp_eop_reg;
tx_wr_req_tlp_ready_next = 1'b0;
if (wr_req_payload_offset_reg) begin
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-128]};
end else begin
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
end
wr_req_fifo_wr_eop = 0;
wr_req_fifo_wr_valid = 1;
wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
wr_req_fifo_we = 0;
// combine header and payload
case (wr_req_state_reg)
WR_REQ_STATE_IDLE: begin
// idle state
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
wr_req_payload_offset_next = tx_wr_req_tlp_hdr[125];
wr_req_fifo_wr_data[31:0] = tx_wr_req_tlp_hdr[127:96];
wr_req_fifo_wr_data[63:32] = tx_wr_req_tlp_hdr[95:64];
wr_req_fifo_wr_data[95:64] = tx_wr_req_tlp_hdr[63:32];
if (wr_req_payload_offset_next) begin
wr_req_fifo_wr_data[127:96] = tx_wr_req_tlp_hdr[31:0];
wr_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:128] = tx_wr_req_tlp_data;
end else begin
wr_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:96] = tx_wr_req_tlp_data;
end
wr_req_fifo_wr_eop = 0;
wr_req_fifo_wr_valid = 1;
wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
if (tx_wr_req_tlp_valid && tx_wr_req_tlp_ready) begin
// send complete header and start of payload (completion)
wr_req_fifo_we = 1;
wr_req_tlp_data_next = tx_wr_req_tlp_data;
wr_req_tlp_eop_next = tx_wr_req_tlp_eop;
if (tx_wr_req_tlp_eop && wr_req_payload_offset_next && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0)) begin
wr_req_fifo_wr_eop = 1;
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
wr_req_state_next = WR_REQ_STATE_IDLE;
end else if (tx_wr_req_tlp_eop && !wr_req_payload_offset_next && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
wr_req_fifo_wr_eop = 1;
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
wr_req_state_next = WR_REQ_STATE_IDLE;
end else begin
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_next;
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
end
end else begin
wr_req_state_next = WR_REQ_STATE_IDLE;
end
end
WR_REQ_STATE_PAYLOAD: begin
// transfer payload (completion)
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_reg;
if (wr_req_payload_offset_reg) begin
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-128]};
end else begin
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
end
wr_req_fifo_wr_eop = 0;
wr_req_fifo_wr_valid = 1;
wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
if ((tx_wr_req_tlp_valid && tx_wr_req_tlp_ready) || (wr_req_tlp_eop_reg && !wr_req_fifo_watermark_reg)) begin
wr_req_fifo_we = 1;
wr_req_tlp_data_next = tx_wr_req_tlp_data;
wr_req_tlp_eop_next = tx_wr_req_tlp_eop;
if (wr_req_tlp_eop_reg || (tx_wr_req_tlp_eop && wr_req_payload_offset_reg && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0))) begin
wr_req_fifo_wr_eop = 1;
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
wr_req_state_next = WR_REQ_STATE_IDLE;
end else if (wr_req_tlp_eop_reg || (tx_wr_req_tlp_eop && !wr_req_payload_offset_reg && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
wr_req_fifo_wr_eop = 1;
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
wr_req_state_next = WR_REQ_STATE_IDLE;
end else begin
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_next;
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
end
end else begin
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
end
end
endcase
end
// Completion processing
always @* begin
cpl_state_next = CPL_STATE_IDLE;
cpl_tlp_data_next = cpl_tlp_data_reg;
cpl_tlp_eop_next = cpl_tlp_eop_reg;
tx_cpl_tlp_ready_next = 1'b0;
cpl_fifo_wr_data = {tx_cpl_tlp_data, cpl_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
cpl_fifo_wr_eop = 0;
cpl_fifo_wr_valid = 1;
cpl_fifo_we = 0;
// combine header and payload
case (cpl_state_reg)
CPL_STATE_IDLE: begin
// idle state
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
cpl_fifo_wr_data[31:0] = tx_cpl_tlp_hdr[127:96];
cpl_fifo_wr_data[63:32] = tx_cpl_tlp_hdr[95:64];
cpl_fifo_wr_data[95:64] = tx_cpl_tlp_hdr[63:32];
cpl_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:96] = tx_cpl_tlp_data;
cpl_fifo_wr_eop = 0;
cpl_fifo_wr_valid = 1;
if (tx_cpl_tlp_valid && tx_cpl_tlp_ready) begin
// send complete header and start of payload (completion)
cpl_fifo_we = 1;
cpl_tlp_data_next = tx_cpl_tlp_data;
cpl_tlp_eop_next = tx_cpl_tlp_eop;
if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
cpl_fifo_wr_eop = 1;
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
cpl_state_next = CPL_STATE_IDLE;
end else begin
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_next;
cpl_state_next = CPL_STATE_PAYLOAD;
end
end else begin
cpl_state_next = CPL_STATE_IDLE;
end
end
CPL_STATE_PAYLOAD: begin
// transfer payload (completion)
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_reg;
cpl_fifo_wr_data = {tx_cpl_tlp_data, cpl_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
cpl_fifo_wr_eop = 0;
cpl_fifo_wr_valid = 1;
if ((tx_cpl_tlp_valid && tx_cpl_tlp_ready) || (cpl_tlp_eop_reg && !cpl_fifo_watermark_reg)) begin
cpl_fifo_we = 1;
cpl_tlp_data_next = tx_cpl_tlp_data;
cpl_tlp_eop_next = tx_cpl_tlp_eop;
if (cpl_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
cpl_fifo_wr_eop = 1;
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
cpl_state_next = CPL_STATE_IDLE;
end else begin
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_next;
cpl_state_next = CPL_STATE_PAYLOAD;
end
end else begin
cpl_state_next = CPL_STATE_PAYLOAD;
end
end
endcase
end
// Output arbitration
always @* begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
m_axis_rd_req_tx_seq_num_next = 0;
m_axis_rd_req_tx_seq_num_valid_next = 0;
m_axis_wr_req_tx_seq_num_next = 0;
m_axis_wr_req_tx_seq_num_valid_next = 0;
tx_st_data_next = 0;
tx_st_sop_next = 0;
tx_st_eop_next = 0;
tx_st_valid_next = 0;
rd_req_fifo_rd_data_next = rd_req_fifo_rd_data_reg;
rd_req_fifo_rd_valid_next = rd_req_fifo_rd_valid_reg;
rd_req_fifo_rd_seq_next = rd_req_fifo_rd_seq_reg;
wr_req_fifo_rd_data_next = wr_req_fifo_rd_data_reg;
wr_req_fifo_rd_eop_next = wr_req_fifo_rd_eop_reg;
wr_req_fifo_rd_valid_next = wr_req_fifo_rd_valid_reg;
wr_req_fifo_rd_seq_next = wr_req_fifo_rd_seq_reg;
cpl_fifo_rd_data_next = cpl_fifo_rd_data_reg;
cpl_fifo_rd_eop_next = cpl_fifo_rd_eop_reg;
cpl_fifo_rd_valid_next = cpl_fifo_rd_valid_reg;
msi_wr_req_data_next = msi_wr_req_data_reg;
msi_wr_req_valid_next = msi_wr_req_valid_reg;
// arbitrate across all sources
case (tlp_output_state_reg)
TLP_OUTPUT_STATE_IDLE: begin
// idle state
if (msi_wr_req_valid_reg && tx_st_ready_delay_reg[1]) begin
// transfer MSI write request
tx_st_data_next = msi_wr_req_data_reg;
tx_st_sop_next = 1;
tx_st_eop_next = 1;
tx_st_valid_next = 1;
msi_wr_req_valid_next = 0;
end else if (cpl_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
// transfer completion
tx_st_data_next = cpl_fifo_rd_data_reg;
tx_st_sop_next = 1;
tx_st_eop_next = cpl_fifo_rd_eop_reg;
tx_st_valid_next = cpl_fifo_rd_valid_reg;
cpl_fifo_rd_valid_next = 0;
if (cpl_fifo_rd_eop_reg) begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
end
end else if (rd_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
// transfer read request
tx_st_data_next = rd_req_fifo_rd_data_reg;
tx_st_sop_next = 1;
tx_st_eop_next = 1;
tx_st_valid_next = 1;
rd_req_fifo_rd_valid_next = 0;
// return read request sequence number
m_axis_rd_req_tx_seq_num_next = rd_req_fifo_rd_seq_reg;
m_axis_rd_req_tx_seq_num_valid_next = 1'b1;
end else if (wr_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
// transfer write request
tx_st_data_next = wr_req_fifo_rd_data_reg;
tx_st_sop_next = 1;
tx_st_eop_next = wr_req_fifo_rd_eop_reg;
tx_st_valid_next = wr_req_fifo_rd_valid_reg;
wr_req_fifo_rd_valid_next = 0;
// return write request sequence number
m_axis_wr_req_tx_seq_num_next = wr_req_fifo_rd_seq_reg;
m_axis_wr_req_tx_seq_num_valid_next = 1'b1;
if (wr_req_fifo_rd_eop_reg) begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end
end
TLP_OUTPUT_STATE_WR_PAYLOAD: begin
// transfer payload (write request)
tx_st_data_next = wr_req_fifo_rd_data_reg;
tx_st_sop_next = 0;
tx_st_eop_next = wr_req_fifo_rd_eop_reg;
if (wr_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
tx_st_valid_next = wr_req_fifo_rd_valid_reg;
wr_req_fifo_rd_valid_next = 0;
if (wr_req_fifo_rd_eop_reg) begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end
TLP_OUTPUT_STATE_CPL_PAYLOAD: begin
// transfer payload (completion)
tx_st_data_next = cpl_fifo_rd_data_reg;
tx_st_sop_next = 0;
tx_st_eop_next = cpl_fifo_rd_eop_reg;
if (cpl_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
tx_st_valid_next = cpl_fifo_rd_valid_reg;
cpl_fifo_rd_valid_next = 0;
if (cpl_fifo_rd_eop_reg) begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
end
end
endcase
rd_req_fifo_rd_ptr_next = rd_req_fifo_rd_ptr_reg;
if (!rd_req_fifo_rd_valid_next && rd_req_fifo_rd_ptr_reg != rd_req_fifo_wr_ptr_reg) begin
// read request FIFO not empty
rd_req_fifo_rd_data_next = rd_req_fifo_data[rd_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
rd_req_fifo_rd_valid_next = 1;
rd_req_fifo_rd_seq_next = rd_req_fifo_seq[rd_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
rd_req_fifo_rd_ptr_next = rd_req_fifo_rd_ptr_reg + 1;
end
wr_req_fifo_rd_ptr_next = wr_req_fifo_rd_ptr_reg;
if (!wr_req_fifo_rd_valid_next && wr_req_fifo_rd_ptr_reg != wr_req_fifo_wr_ptr_reg) begin
// write request FIFO not empty
wr_req_fifo_rd_data_next = wr_req_fifo_data[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
wr_req_fifo_rd_eop_next = wr_req_fifo_eop[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
wr_req_fifo_rd_valid_next = wr_req_fifo_valid[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
wr_req_fifo_rd_seq_next = wr_req_fifo_seq[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
wr_req_fifo_rd_ptr_next = wr_req_fifo_rd_ptr_reg + 1;
end
cpl_fifo_rd_ptr_next = cpl_fifo_rd_ptr_reg;
if (!cpl_fifo_rd_valid_next && cpl_fifo_rd_ptr_reg != cpl_fifo_wr_ptr_reg) begin
// completion FIFO not empty
cpl_fifo_rd_data_next = cpl_fifo_data[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
cpl_fifo_rd_eop_next = cpl_fifo_eop[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
cpl_fifo_rd_valid_next = cpl_fifo_valid[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
cpl_fifo_rd_ptr_next = cpl_fifo_rd_ptr_reg + 1;
end
tx_msi_wr_req_tlp_ready_next = 1'b0;
if (!msi_wr_req_valid_reg && tx_msi_wr_req_tlp_valid) begin
msi_wr_req_data_next[31:0] = tx_msi_wr_req_tlp_hdr[127:96];
msi_wr_req_data_next[63:32] = tx_msi_wr_req_tlp_hdr[95:64];
msi_wr_req_data_next[95:64] = tx_msi_wr_req_tlp_hdr[63:32];
if (tx_msi_wr_req_tlp_hdr[125]) begin
msi_wr_req_data_next[127:96] = tx_msi_wr_req_tlp_hdr[31:0];
msi_wr_req_data_next[SEG_COUNT*SEG_DATA_WIDTH-1:128] = tx_msi_wr_req_tlp_data;
end else begin
msi_wr_req_data_next[SEG_COUNT*SEG_DATA_WIDTH-1:96] = tx_msi_wr_req_tlp_data;
end
msi_wr_req_valid_next = 1'b1;
tx_msi_wr_req_tlp_ready_next = 1'b1;
end
end
always @(posedge clk) begin
wr_req_state_reg <= wr_req_state_next;
cpl_state_reg <= cpl_state_next;
tlp_output_state_reg <= tlp_output_state_next;
wr_req_payload_offset_reg <= wr_req_payload_offset_next;
wr_req_tlp_data_reg <= wr_req_tlp_data_next;
wr_req_tlp_eop_reg <= wr_req_tlp_eop_next;
cpl_tlp_data_reg <= cpl_tlp_data_next;
cpl_tlp_eop_reg <= cpl_tlp_eop_next;
tx_rd_req_tlp_ready_reg <= tx_rd_req_tlp_ready_next;
tx_wr_req_tlp_ready_reg <= tx_wr_req_tlp_ready_next;
tx_cpl_tlp_ready_reg <= tx_cpl_tlp_ready_next;
tx_msi_wr_req_tlp_ready_reg <= tx_msi_wr_req_tlp_ready_next;
m_axis_rd_req_tx_seq_num_reg <= m_axis_rd_req_tx_seq_num_next;
m_axis_rd_req_tx_seq_num_valid_reg <= m_axis_rd_req_tx_seq_num_valid_next;
m_axis_wr_req_tx_seq_num_reg <= m_axis_wr_req_tx_seq_num_next;
m_axis_wr_req_tx_seq_num_valid_reg <= m_axis_wr_req_tx_seq_num_valid_next;
tx_st_data_reg <= tx_st_data_next;
tx_st_sop_reg <= tx_st_sop_next;
tx_st_eop_reg <= tx_st_eop_next;
tx_st_valid_reg <= tx_st_valid_next;
tx_st_ready_delay_reg <= {tx_st_ready_delay_reg, tx_st_ready};
if (rd_req_fifo_we) begin
rd_req_fifo_data[rd_req_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= rd_req_fifo_wr_data;
rd_req_fifo_seq[rd_req_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= rd_req_fifo_wr_seq;
rd_req_fifo_wr_ptr_reg <= rd_req_fifo_wr_ptr_reg + 1;
end
rd_req_fifo_rd_ptr_reg <= rd_req_fifo_rd_ptr_next;
rd_req_fifo_rd_data_reg <= rd_req_fifo_rd_data_next;
rd_req_fifo_rd_valid_reg <= rd_req_fifo_rd_valid_next;
rd_req_fifo_rd_seq_reg <= rd_req_fifo_rd_seq_next;
rd_req_fifo_watermark_reg <= $unsigned(rd_req_fifo_wr_ptr_reg - rd_req_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
if (wr_req_fifo_we) begin
wr_req_fifo_data[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_data;
wr_req_fifo_eop[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_eop;
wr_req_fifo_valid[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_valid;
wr_req_fifo_seq[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_seq;
wr_req_fifo_wr_ptr_cur_reg <= wr_req_fifo_wr_ptr_cur_reg + 1;
if (wr_req_fifo_wr_eop) begin
// update write pointer at end of frame
wr_req_fifo_wr_ptr_reg <= wr_req_fifo_wr_ptr_cur_reg + 1;
end
end
wr_req_fifo_rd_ptr_reg <= wr_req_fifo_rd_ptr_next;
wr_req_fifo_rd_data_reg <= wr_req_fifo_rd_data_next;
wr_req_fifo_rd_eop_reg <= wr_req_fifo_rd_eop_next;
wr_req_fifo_rd_valid_reg <= wr_req_fifo_rd_valid_next;
wr_req_fifo_rd_seq_reg <= wr_req_fifo_rd_seq_next;
wr_req_fifo_watermark_reg <= $unsigned(wr_req_fifo_wr_ptr_cur_reg - wr_req_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
if (cpl_fifo_we) begin
cpl_fifo_data[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_data;
cpl_fifo_eop[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_eop;
cpl_fifo_valid[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_valid;
cpl_fifo_wr_ptr_cur_reg <= cpl_fifo_wr_ptr_cur_reg + 1;
if (cpl_fifo_wr_eop) begin
// update write pointer at end of frame
cpl_fifo_wr_ptr_reg <= cpl_fifo_wr_ptr_cur_reg + 1;
end
end
cpl_fifo_rd_ptr_reg <= cpl_fifo_rd_ptr_next;
cpl_fifo_rd_data_reg <= cpl_fifo_rd_data_next;
cpl_fifo_rd_eop_reg <= cpl_fifo_rd_eop_next;
cpl_fifo_rd_valid_reg <= cpl_fifo_rd_valid_next;
cpl_fifo_watermark_reg <= $unsigned(cpl_fifo_wr_ptr_cur_reg - cpl_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
msi_wr_req_data_reg <= msi_wr_req_data_next;
msi_wr_req_valid_reg <= msi_wr_req_valid_next;
if (rst) begin
wr_req_state_reg <= WR_REQ_STATE_IDLE;
cpl_state_reg <= CPL_STATE_IDLE;
tlp_output_state_reg <= TLP_OUTPUT_STATE_IDLE;
tx_rd_req_tlp_ready_reg <= 1'b0;
tx_wr_req_tlp_ready_reg <= 1'b0;
tx_cpl_tlp_ready_reg <= 1'b0;
tx_msi_wr_req_tlp_ready_reg <= 1'b0;
m_axis_rd_req_tx_seq_num_valid_reg <= 0;
m_axis_wr_req_tx_seq_num_valid_reg <= 0;
tx_st_valid_reg <= 0;
tx_st_ready_delay_reg <= 0;
rd_req_fifo_wr_ptr_reg <= 0;
rd_req_fifo_rd_ptr_reg <= 0;
rd_req_fifo_rd_valid_reg <= 1'b0;
wr_req_fifo_wr_ptr_reg <= 0;
wr_req_fifo_wr_ptr_cur_reg <= 0;
wr_req_fifo_rd_ptr_reg <= 0;
wr_req_fifo_rd_valid_reg <= 0;
cpl_fifo_wr_ptr_reg <= 0;
cpl_fifo_wr_ptr_cur_reg <= 0;
cpl_fifo_rd_ptr_reg <= 0;
cpl_fifo_rd_valid_reg <= 0;
msi_wr_req_valid_reg <= 0;
end
end
endmodule |
module pcie_tlp_demux #
(
// Output count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// Sequence number width
parameter SEQ_NUM_WIDTH = 6,
// TLP segment count
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] in_tlp_seq,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
/*
* TLP output
*/
output wire [PORTS*TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
/*
* Fields
*/
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] match_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
/*
* Control
*/
input wire enable,
input wire [TLP_SEG_COUNT-1:0] drop,
input wire [TLP_SEG_COUNT*PORTS-1:0] select
);
parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
end
reg [CL_PORTS-1:0] select_reg = {CL_PORTS{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg in_tlp_ready_reg = 1'b0, in_tlp_ready_next;
reg [TLP_DATA_WIDTH-1:0] temp_in_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_in_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_in_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] temp_in_tlp_seq_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_in_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_in_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_in_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_valid_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_sop_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_eop_reg = 1'b0;
// internal datapath
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
assign in_tlp_ready = in_tlp_ready_reg && enable;
assign match_tlp_hdr = in_tlp_hdr;
assign match_tlp_bar_id = in_tlp_bar_id;
assign match_tlp_func_num = in_tlp_func_num;
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
in_tlp_ready_next = 1'b0;
if (in_tlp_valid && in_tlp_ready) begin
// end of frame detection
if (in_tlp_eop) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && in_tlp_valid && in_tlp_ready) begin
// start of frame, grab select value
select_ctl = 0;
drop_ctl = 1'b1;
frame_ctl = 1'b1;
for (i = PORTS-1; i >= 0; i = i - 1) begin
if (select[i]) begin
select_ctl = i;
drop_ctl = 1'b0;
end
end
drop_ctl = drop_ctl || drop;
if (!(in_tlp_ready && in_tlp_valid && in_tlp_eop)) begin
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = 1'b1;
end
end
in_tlp_ready_next = out_tlp_ready_int_early || drop_ctl;
out_tlp_data_int = in_tlp_data;
out_tlp_strb_int = in_tlp_strb;
out_tlp_hdr_int = in_tlp_hdr;
out_tlp_seq_int = in_tlp_seq;
out_tlp_bar_id_int = in_tlp_bar_id;
out_tlp_func_num_int = in_tlp_func_num;
out_tlp_error_int = in_tlp_error;
out_tlp_valid_int = (in_tlp_valid && in_tlp_ready && !drop_ctl && frame_ctl) << select_ctl;
out_tlp_sop_int = in_tlp_sop;
out_tlp_eop_int = in_tlp_eop;
end
always @(posedge clk) begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
in_tlp_ready_reg <= in_tlp_ready_next;
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
in_tlp_ready_reg <= 1'b0;
end
end
// output datapath logic
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 1, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] temp_out_tlp_seq_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
// datapath control
reg store_int_to_output;
reg store_int_to_temp;
reg store_temp_to_output;
assign out_tlp_data = {PORTS{out_tlp_data_reg}};
assign out_tlp_strb = {PORTS{out_tlp_strb_reg}};
assign out_tlp_hdr = {PORTS{out_tlp_hdr_reg}};
assign out_tlp_seq = {PORTS{out_tlp_seq_reg}};
assign out_tlp_bar_id = {PORTS{out_tlp_bar_id_reg}};
assign out_tlp_func_num = {PORTS{out_tlp_func_num_reg}};
assign out_tlp_error = {PORTS{out_tlp_error_reg}};
assign out_tlp_valid = out_tlp_valid_reg;
assign out_tlp_sop = {PORTS{out_tlp_sop_reg}};
assign out_tlp_eop = {PORTS{out_tlp_eop_reg}};
// enable ready input next cycle if output is ready or if both output registers are empty
assign out_tlp_ready_int_early = (out_tlp_ready & out_tlp_valid) || (!temp_out_tlp_valid_reg && !out_tlp_valid_reg);
always @* begin
// transfer sink ready state to source
out_tlp_valid_next = out_tlp_valid_reg;
temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
store_int_to_output = 1'b0;
store_int_to_temp = 1'b0;
store_temp_to_output = 1'b0;
if (out_tlp_ready_int_reg) begin
// input is ready
if ((out_tlp_ready & out_tlp_valid) || !out_tlp_valid) begin
// output is ready or currently not valid, transfer data to output
out_tlp_valid_next = out_tlp_valid_int;
store_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_out_tlp_valid_next = out_tlp_valid_int;
store_int_to_temp = 1'b1;
end
end else if (out_tlp_ready & out_tlp_valid) begin
// input is not ready, but output is ready
out_tlp_valid_next = temp_out_tlp_valid_reg;
temp_out_tlp_valid_next = 1'b0;
store_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
out_tlp_valid_reg <= out_tlp_valid_next;
out_tlp_ready_int_reg <= out_tlp_ready_int_early;
temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
// datapath
if (store_int_to_output) begin
out_tlp_data_reg <= out_tlp_data_int;
out_tlp_strb_reg <= out_tlp_strb_int;
out_tlp_hdr_reg <= out_tlp_hdr_int;
out_tlp_seq_reg <= out_tlp_seq_int;
out_tlp_bar_id_reg <= out_tlp_bar_id_int;
out_tlp_func_num_reg <= out_tlp_func_num_int;
out_tlp_error_reg <= out_tlp_error_int;
out_tlp_sop_reg <= out_tlp_sop_int;
out_tlp_eop_reg <= out_tlp_eop_int;
end else if (store_temp_to_output) begin
out_tlp_data_reg <= temp_out_tlp_data_reg;
out_tlp_strb_reg <= temp_out_tlp_strb_reg;
out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
out_tlp_seq_reg <= temp_out_tlp_seq_reg;
out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
out_tlp_error_reg <= temp_out_tlp_error_reg;
out_tlp_sop_reg <= temp_out_tlp_sop_reg;
out_tlp_eop_reg <= temp_out_tlp_eop_reg;
end
if (store_int_to_temp) begin
temp_out_tlp_data_reg <= out_tlp_data_int;
temp_out_tlp_strb_reg <= out_tlp_strb_int;
temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
temp_out_tlp_seq_reg <= out_tlp_seq_int;
temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
temp_out_tlp_error_reg <= out_tlp_error_int;
temp_out_tlp_sop_reg <= out_tlp_sop_int;
temp_out_tlp_eop_reg <= out_tlp_eop_int;
end
if (rst) begin
out_tlp_valid_reg <= {PORTS{1'b0}};
out_tlp_ready_int_reg <= 1'b0;
temp_out_tlp_valid_reg <= 1'b0;
end
end
endmodule |
module pcie_tlp_mux #
(
// Input count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// Sequence number width
parameter SEQ_NUM_WIDTH = 6,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [PORTS*TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [PORTS*TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [PORTS*TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] in_tlp_seq,
input wire [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire [PORTS-1:0] in_tlp_ready,
/*
* TLP output
*/
output wire [TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq,
output wire [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire out_tlp_ready
);
parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
end
wire [PORTS-1:0] request;
wire [PORTS-1:0] acknowledge;
wire [PORTS-1:0] grant;
wire grant_valid;
wire [CL_PORTS-1:0] grant_encoded;
// input registers to pipeline arbitration delay
reg [PORTS*TLP_DATA_WIDTH-1:0] in_tlp_data_reg = 0;
reg [PORTS*TLP_STRB_WIDTH-1:0] in_tlp_strb_reg = 0;
reg [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr_reg = 0;
reg [PORTS*TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] in_tlp_seq_reg = 0;
reg [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id_reg = 0;
reg [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num_reg = 0;
reg [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop_reg = 0;
// internal datapath
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
assign in_tlp_ready = ~in_tlp_valid_reg | ({PORTS{out_tlp_ready_int_reg}} & grant);
// mux for incoming packet
wire [TLP_DATA_WIDTH-1:0] current_in_tlp_data = in_tlp_data_reg[grant_encoded*TLP_DATA_WIDTH +: TLP_DATA_WIDTH];
wire [TLP_STRB_WIDTH-1:0] current_in_tlp_strb = in_tlp_strb_reg[grant_encoded*TLP_STRB_WIDTH +: TLP_STRB_WIDTH];
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] current_in_tlp_hdr = in_tlp_hdr_reg[grant_encoded*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH];
wire [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] current_in_tlp_seq = in_tlp_seq_reg[grant_encoded*TLP_SEG_COUNT*SEQ_NUM_WIDTH +: TLP_SEG_COUNT*SEQ_NUM_WIDTH];
wire [TLP_SEG_COUNT*3-1:0] current_in_tlp_bar_id = in_tlp_bar_id_reg[grant_encoded*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
wire [TLP_SEG_COUNT*8-1:0] current_in_tlp_func_num = in_tlp_func_num_reg[grant_encoded*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
wire [TLP_SEG_COUNT*4-1:0] current_in_tlp_error = in_tlp_error_reg[grant_encoded*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_valid = in_tlp_valid_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_sop = in_tlp_sop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_eop = in_tlp_eop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire current_in_tlp_ready = in_tlp_ready[grant_encoded];
// arbiter instance
arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = (in_tlp_valid_reg & ~grant) | (in_tlp_valid & grant);
assign acknowledge = grant & in_tlp_valid_reg & {PORTS{out_tlp_ready_int_reg}} & in_tlp_eop_reg;
always @* begin
// pass through selected packet data
out_tlp_data_int = current_in_tlp_data;
out_tlp_strb_int = current_in_tlp_strb;
out_tlp_hdr_int = current_in_tlp_hdr;
out_tlp_seq_int = current_in_tlp_seq;
out_tlp_bar_id_int = current_in_tlp_bar_id;
out_tlp_func_num_int = current_in_tlp_func_num;
out_tlp_error_int = current_in_tlp_error;
out_tlp_valid_int = current_in_tlp_valid && out_tlp_ready_int_reg && grant_valid;
out_tlp_sop_int = current_in_tlp_sop;
out_tlp_eop_int = current_in_tlp_eop;
end
integer i;
always @(posedge clk) begin
// register inputs
for (i = 0; i < PORTS; i = i + 1) begin
if (in_tlp_ready[i]) begin
in_tlp_data_reg[i*TLP_DATA_WIDTH +: TLP_DATA_WIDTH] <= in_tlp_data[i*TLP_DATA_WIDTH +: TLP_DATA_WIDTH];
in_tlp_strb_reg[i*TLP_STRB_WIDTH +: TLP_STRB_WIDTH] <= in_tlp_strb[i*TLP_STRB_WIDTH +: TLP_STRB_WIDTH];
in_tlp_hdr_reg[i*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH] <= in_tlp_hdr[i*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH];
in_tlp_seq_reg[i*TLP_SEG_COUNT*SEQ_NUM_WIDTH +: TLP_SEG_COUNT*SEQ_NUM_WIDTH] <= in_tlp_seq[i*TLP_SEG_COUNT*SEQ_NUM_WIDTH +: TLP_SEG_COUNT*SEQ_NUM_WIDTH];
in_tlp_bar_id_reg[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3] <= in_tlp_bar_id[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
in_tlp_func_num_reg[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8] <= in_tlp_func_num[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
in_tlp_error_reg[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4] <= in_tlp_error[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
in_tlp_valid_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_valid[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
in_tlp_sop_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_sop[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
in_tlp_eop_reg[i*TLP_SEG_COUNT +: TLP_SEG_COUNT] <= in_tlp_eop[i*TLP_SEG_COUNT +: TLP_SEG_COUNT];
end
end
if (rst) begin
in_tlp_valid_reg <= 0;
end
end
// output datapath logic
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] temp_out_tlp_seq_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign out_tlp_data = out_tlp_data_reg;
assign out_tlp_strb = out_tlp_strb_reg;
assign out_tlp_hdr = out_tlp_hdr_reg;
assign out_tlp_seq = out_tlp_seq_reg;
assign out_tlp_bar_id = out_tlp_bar_id_reg;
assign out_tlp_func_num = out_tlp_func_num_reg;
assign out_tlp_error = out_tlp_error_reg;
assign out_tlp_valid = out_tlp_valid_reg;
assign out_tlp_sop = out_tlp_sop_reg;
assign out_tlp_eop = out_tlp_eop_reg;
// enable ready input next cycle if output is ready or if both output registers are empty
assign out_tlp_ready_int_early = out_tlp_ready || (!temp_out_tlp_valid_reg && !out_tlp_valid_reg);
always @* begin
// transfer sink ready state to source
out_tlp_valid_next = out_tlp_valid_reg;
temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (out_tlp_ready_int_reg) begin
// input is ready
if (out_tlp_ready || !out_tlp_valid_reg) begin
// output is ready or currently not valid, transfer data to output
out_tlp_valid_next = out_tlp_valid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_out_tlp_valid_next = out_tlp_valid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (out_tlp_ready) begin
// input is not ready, but output is ready
out_tlp_valid_next = temp_out_tlp_valid_reg;
temp_out_tlp_valid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
out_tlp_valid_reg <= out_tlp_valid_next;
out_tlp_ready_int_reg <= out_tlp_ready_int_early;
temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
// datapath
if (store_axis_int_to_output) begin
out_tlp_data_reg <= out_tlp_data_int;
out_tlp_strb_reg <= out_tlp_strb_int;
out_tlp_hdr_reg <= out_tlp_hdr_int;
out_tlp_seq_reg <= out_tlp_seq_int;
out_tlp_bar_id_reg <= out_tlp_bar_id_int;
out_tlp_func_num_reg <= out_tlp_func_num_int;
out_tlp_error_reg <= out_tlp_error_int;
out_tlp_sop_reg <= out_tlp_sop_int;
out_tlp_eop_reg <= out_tlp_eop_int;
end else if (store_axis_temp_to_output) begin
out_tlp_data_reg <= temp_out_tlp_data_reg;
out_tlp_strb_reg <= temp_out_tlp_strb_reg;
out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
out_tlp_seq_reg <= temp_out_tlp_seq_reg;
out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
out_tlp_error_reg <= temp_out_tlp_error_reg;
out_tlp_sop_reg <= temp_out_tlp_sop_reg;
out_tlp_eop_reg <= temp_out_tlp_eop_reg;
end
if (store_axis_int_to_temp) begin
temp_out_tlp_data_reg <= out_tlp_data_int;
temp_out_tlp_strb_reg <= out_tlp_strb_int;
temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
temp_out_tlp_seq_reg <= out_tlp_seq_int;
temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
temp_out_tlp_error_reg <= out_tlp_error_int;
temp_out_tlp_sop_reg <= out_tlp_sop_int;
temp_out_tlp_eop_reg <= out_tlp_eop_int;
end
if (rst) begin
out_tlp_valid_reg <= 1'b0;
out_tlp_ready_int_reg <= 1'b0;
temp_out_tlp_valid_reg <= 1'b0;
end
end
endmodule |
module pcie_us_if_rq #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream RQ tuser signal width
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
// RQ sequence number width
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1
)
(
input wire clk,
input wire rst,
/*
* AXI output (RQ)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tvalid,
input wire m_axis_rq_tready,
output wire m_axis_rq_tlast,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
/*
* Transmit sequence number input
*/
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
/*
* Transmit sequence number output (DMA read request)
*/
output wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
/*
* TLP input (write request from DMA)
*/
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number output (DMA write request)
*/
output wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid
);
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
parameter SEQ_NUM_MASK = {RQ_SEQ_NUM_WIDTH-1{1'b1}};
parameter SEQ_NUM_FLAG = {1'b1, {RQ_SEQ_NUM_WIDTH-1{1'b0}}};
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXIS_PCIE_DATA_WIDTH == 512) begin
if (AXIS_PCIE_RQ_USER_WIDTH != 137) begin
$error("Error: PCIe RQ tuser width must be 137 (instance %m)");
$finish;
end
if (TX_SEQ_NUM_COUNT != 2) begin
$error("Error: TX sequence number count must be 2 (instance %m)");
$finish;
end
end else begin
if (AXIS_PCIE_RQ_USER_WIDTH != 60 && AXIS_PCIE_RQ_USER_WIDTH != 62) begin
$error("Error: PCIe RQ tuser width must be 60 or 62 (instance %m)");
$finish;
end
if (TX_SEQ_NUM_COUNT != 1) begin
$error("Error: TX sequence number count must be 1 (instance %m)");
$finish;
end
end
if (AXIS_PCIE_RQ_USER_WIDTH == 60) begin
if (RQ_SEQ_NUM_WIDTH != 4) begin
$error("Error: RQ sequence number width must be 4 (instance %m)");
$finish;
end
end else begin
if (RQ_SEQ_NUM_WIDTH != 6) begin
$error("Error: RQ sequence number width must be 6 (instance %m)");
$finish;
end
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (TX_SEQ_NUM_WIDTH > RQ_SEQ_NUM_WIDTH-1) begin
$error("Error: TX sequence number width must be less than RQ_SEQ_NUM_WIDTH (instance %m)");
$finish;
end
end
localparam [3:0]
REQ_MEM_READ = 4'b0000,
REQ_MEM_WRITE = 4'b0001,
REQ_IO_READ = 4'b0010,
REQ_IO_WRITE = 4'b0011,
REQ_MEM_FETCH_ADD = 4'b0100,
REQ_MEM_SWAP = 4'b0101,
REQ_MEM_CAS = 4'b0110,
REQ_MEM_READ_LOCKED = 4'b0111,
REQ_CFG_READ_0 = 4'b1000,
REQ_CFG_READ_1 = 4'b1001,
REQ_CFG_WRITE_0 = 4'b1010,
REQ_CFG_WRITE_1 = 4'b1011,
REQ_MSG = 4'b1100,
REQ_MSG_VENDOR = 4'b1101,
REQ_MSG_ATS = 4'b1110;
reg tx_rd_req_tlp_ready_cmb;
wire [TLP_SEG_COUNT*RQ_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq_int = {1'b1, tx_rd_req_tlp_seq};
reg tx_wr_req_tlp_ready_cmb;
wire [TLP_SEG_COUNT*RQ_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq_int = {1'b0, tx_wr_req_tlp_seq};
assign tx_rd_req_tlp_ready = tx_rd_req_tlp_ready_cmb;
assign tx_wr_req_tlp_ready = tx_wr_req_tlp_ready_cmb;
generate
assign m_axis_rd_req_tx_seq_num[TX_SEQ_NUM_WIDTH*0 +: TX_SEQ_NUM_WIDTH] = s_axis_rq_seq_num_0;
assign m_axis_rd_req_tx_seq_num_valid[0] = s_axis_rq_seq_num_valid_0 && ((s_axis_rq_seq_num_0 & SEQ_NUM_FLAG) != 0);
if (TX_SEQ_NUM_COUNT > 1) begin
assign m_axis_rd_req_tx_seq_num[TX_SEQ_NUM_WIDTH*1 +: TX_SEQ_NUM_WIDTH] = s_axis_rq_seq_num_1;
assign m_axis_rd_req_tx_seq_num_valid[1] = s_axis_rq_seq_num_valid_1 && ((s_axis_rq_seq_num_1 & SEQ_NUM_FLAG) != 0);
end
assign m_axis_wr_req_tx_seq_num[TX_SEQ_NUM_WIDTH*0 +: TX_SEQ_NUM_WIDTH] = s_axis_rq_seq_num_0;
assign m_axis_wr_req_tx_seq_num_valid[0] = s_axis_rq_seq_num_valid_0 && ((s_axis_rq_seq_num_0 & SEQ_NUM_FLAG) == 0);
if (TX_SEQ_NUM_COUNT > 1) begin
assign m_axis_wr_req_tx_seq_num[TX_SEQ_NUM_WIDTH*1 +: TX_SEQ_NUM_WIDTH] = s_axis_rq_seq_num_1;
assign m_axis_wr_req_tx_seq_num_valid[1] = s_axis_rq_seq_num_valid_1 && ((s_axis_rq_seq_num_1 & SEQ_NUM_FLAG) == 0);
end
endgenerate
localparam [1:0]
TLP_OUTPUT_STATE_IDLE = 2'd0,
TLP_OUTPUT_STATE_RD_HEADER = 2'd1,
TLP_OUTPUT_STATE_WR_HEADER = 2'd2,
TLP_OUTPUT_STATE_WR_PAYLOAD = 2'd3;
reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
reg [127:0] tlp_header_data_rd;
reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] tlp_tuser_rd;
reg [127:0] tlp_header_data_wr;
reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] tlp_tuser_wr;
reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_int = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_int = 0;
reg m_axis_rq_tvalid_int = 0;
wire m_axis_rq_tready_int;
reg m_axis_rq_tlast_int = 0;
reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_int = 0;
always @* begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
out_tlp_data_next = out_tlp_data_reg;
out_tlp_strb_next = out_tlp_strb_reg;
out_tlp_eop_next = out_tlp_eop_reg;
tx_rd_req_tlp_ready_cmb = 1'b0;
tx_wr_req_tlp_ready_cmb = 1'b0;
// TLP header and sideband data
tlp_header_data_rd[1:0] = tx_rd_req_tlp_hdr[107:106]; // address type
tlp_header_data_rd[63:2] = tx_rd_req_tlp_hdr[63:2]; // address
tlp_header_data_rd[74:64] = (tx_rd_req_tlp_hdr[105:96] != 0) ? tx_rd_req_tlp_hdr[105:96] : 11'd1024; // DWORD count
if (tx_rd_req_tlp_hdr[124:120] == 5'h02) begin
tlp_header_data_rd[78:75] = REQ_IO_READ; // request type - IO read
end else begin
tlp_header_data_rd[78:75] = REQ_MEM_READ; // request type - memory read
end
tlp_header_data_rd[79] = tx_rd_req_tlp_hdr[110]; // poisoned request
tlp_header_data_rd[95:80] = tx_rd_req_tlp_hdr[95:80]; // requester ID
tlp_header_data_rd[103:96] = tx_rd_req_tlp_hdr[79:72]; // tag
tlp_header_data_rd[119:104] = 16'd0; // completer ID
tlp_header_data_rd[120] = 1'b0; // requester ID enable
tlp_header_data_rd[123:121] = tx_rd_req_tlp_hdr[118:116]; // traffic class
tlp_header_data_rd[126:124] = {tx_rd_req_tlp_hdr[114], tx_rd_req_tlp_hdr[109:108]}; // attr
tlp_header_data_rd[127] = 1'b0; // force ECRC
if (AXIS_PCIE_DATA_WIDTH == 512) begin
tlp_tuser_rd[3:0] = tx_rd_req_tlp_hdr[67:64]; // first BE 0
tlp_tuser_rd[7:4] = 4'd0; // first BE 1
tlp_tuser_rd[11:8] = tx_rd_req_tlp_hdr[71:68]; // last BE 0
tlp_tuser_rd[15:12] = 4'd0; // last BE 1
tlp_tuser_rd[19:16] = 3'd0; // addr_offset
tlp_tuser_rd[21:20] = 2'b01; // is_sop
tlp_tuser_rd[23:22] = 2'd0; // is_sop0_ptr
tlp_tuser_rd[25:24] = 2'd0; // is_sop1_ptr
tlp_tuser_rd[27:26] = 2'b01; // is_eop
tlp_tuser_rd[31:28] = 4'd3; // is_eop0_ptr
tlp_tuser_rd[35:32] = 4'd0; // is_eop1_ptr
tlp_tuser_rd[36] = 1'b0; // discontinue
tlp_tuser_rd[38:37] = 2'b00; // tph_present
tlp_tuser_rd[42:39] = 4'b0000; // tph_type
tlp_tuser_rd[44:43] = 2'b00; // tph_indirect_tag_en
tlp_tuser_rd[60:45] = 16'd0; // tph_st_tag
tlp_tuser_rd[66:61] = tx_rd_req_tlp_seq_int; // seq_num0
tlp_tuser_rd[72:67] = 6'd0; // seq_num1
tlp_tuser_rd[136:73] = 64'd0; // parity
end else begin
tlp_tuser_rd[3:0] = tx_rd_req_tlp_hdr[67:64]; // first BE
tlp_tuser_rd[7:4] = tx_rd_req_tlp_hdr[71:68]; // last BE
tlp_tuser_rd[10:8] = 3'd0; // addr_offset
tlp_tuser_rd[11] = 1'b0; // discontinue
tlp_tuser_rd[12] = 1'b0; // tph_present
tlp_tuser_rd[14:13] = 2'b00; // tph_type
tlp_tuser_rd[15] = 1'b0; // tph_indirect_tag_en
tlp_tuser_rd[23:16] = 8'd0; // tph_st_tag
tlp_tuser_rd[27:24] = tx_rd_req_tlp_seq_int; // seq_num
tlp_tuser_rd[59:28] = 32'd0; // parity
if (AXIS_PCIE_RQ_USER_WIDTH == 62) begin
tlp_tuser_rd[61:60] = tx_rd_req_tlp_seq_int >> 4; // seq_num
end
end
tlp_header_data_wr[1:0] = tx_wr_req_tlp_hdr[107:106]; // address type
tlp_header_data_wr[63:2] = tx_wr_req_tlp_hdr[63:2]; // address
tlp_header_data_wr[74:64] = (tx_wr_req_tlp_hdr[105:96] != 0) ? tx_wr_req_tlp_hdr[105:96] : 11'd1024; // DWORD count
if (tx_wr_req_tlp_hdr[124:120] == 5'h02) begin
tlp_header_data_wr[78:75] = REQ_IO_WRITE; // request type - IO write
end else begin
tlp_header_data_wr[78:75] = REQ_MEM_WRITE; // request type - memory write
end
tlp_header_data_wr[79] = tx_wr_req_tlp_hdr[110]; // poisoned request
tlp_header_data_wr[95:80] = tx_wr_req_tlp_hdr[95:80]; // requester ID
tlp_header_data_wr[103:96] = tx_wr_req_tlp_hdr[79:72]; // tag
tlp_header_data_wr[119:104] = 16'd0; // completer ID
tlp_header_data_wr[120] = 1'b0; // requester ID enable
tlp_header_data_wr[123:121] = tx_wr_req_tlp_hdr[118:116]; // traffic class
tlp_header_data_wr[126:124] = {tx_wr_req_tlp_hdr[114], tx_wr_req_tlp_hdr[109:108]}; // attr
tlp_header_data_wr[127] = 1'b0; // force ECRC
if (AXIS_PCIE_DATA_WIDTH == 512) begin
tlp_tuser_wr[3:0] = tx_wr_req_tlp_hdr[67:64]; // first BE 0
tlp_tuser_wr[7:4] = 4'd0; // first BE 1
tlp_tuser_wr[11:8] = tx_wr_req_tlp_hdr[71:68]; // last BE 0
tlp_tuser_wr[15:12] = 4'd0; // last BE 1
tlp_tuser_wr[19:16] = 3'd0; // addr_offset
tlp_tuser_wr[21:20] = 2'b01; // is_sop
tlp_tuser_wr[23:22] = 2'd0; // is_sop0_ptr
tlp_tuser_wr[25:24] = 2'd0; // is_sop1_ptr
tlp_tuser_wr[27:26] = 2'b01; // is_eop
tlp_tuser_wr[31:28] = 4'd3; // is_eop0_ptr
tlp_tuser_wr[35:32] = 4'd0; // is_eop1_ptr
tlp_tuser_wr[36] = 1'b0; // discontinue
tlp_tuser_wr[38:37] = 2'b00; // tph_present
tlp_tuser_wr[42:39] = 4'b0000; // tph_type
tlp_tuser_wr[44:43] = 2'b00; // tph_indirect_tag_en
tlp_tuser_wr[60:45] = 16'd0; // tph_st_tag
tlp_tuser_wr[66:61] = tx_wr_req_tlp_seq_int; // seq_num0
tlp_tuser_wr[72:67] = 6'd0; // seq_num1
tlp_tuser_wr[136:73] = 64'd0; // parity
end else begin
tlp_tuser_wr[3:0] = tx_wr_req_tlp_hdr[67:64]; // first BE
tlp_tuser_wr[7:4] = tx_wr_req_tlp_hdr[71:68]; // last BE
tlp_tuser_wr[10:8] = 3'd0; // addr_offset
tlp_tuser_wr[11] = 1'b0; // discontinue
tlp_tuser_wr[12] = 1'b0; // tph_present
tlp_tuser_wr[14:13] = 2'b00; // tph_type
tlp_tuser_wr[15] = 1'b0; // tph_indirect_tag_en
tlp_tuser_wr[23:16] = 8'd0; // tph_st_tag
tlp_tuser_wr[27:24] = tx_wr_req_tlp_seq_int; // seq_num
tlp_tuser_wr[59:28] = 32'd0; // parity
if (AXIS_PCIE_RQ_USER_WIDTH == 62) begin
tlp_tuser_wr[61:60] = tx_wr_req_tlp_seq_int >> 4; // seq_num
end
end
// TLP output
m_axis_rq_tdata_int = 0;
m_axis_rq_tkeep_int = 0;
m_axis_rq_tvalid_int = 1'b0;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = 0;
// combine header and payload, merge in read request TLPs
case (tlp_output_state_reg)
TLP_OUTPUT_STATE_IDLE: begin
// idle state
if (tx_rd_req_tlp_valid && m_axis_rq_tready_int) begin
if (AXIS_PCIE_DATA_WIDTH == 64) begin
// 64 bit interface, send first half of header (read request)
m_axis_rq_tdata_int = tlp_header_data_rd[63:0];
m_axis_rq_tkeep_int = 2'b11;
m_axis_rq_tvalid_int = 1'b1;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_rd;
tlp_output_state_next = TLP_OUTPUT_STATE_RD_HEADER;
end else begin
// wider interface, send complete header (read request)
m_axis_rq_tdata_int = tlp_header_data_rd;
m_axis_rq_tkeep_int = 4'b1111;
m_axis_rq_tvalid_int = 1'b1;
m_axis_rq_tlast_int = 1'b1;
m_axis_rq_tuser_int = tlp_tuser_rd;
tx_rd_req_tlp_ready_cmb = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end
end else if (tx_wr_req_tlp_valid && m_axis_rq_tready_int) begin
if (AXIS_PCIE_DATA_WIDTH == 64) begin
// 64 bit interface, send first half of header (write request)
m_axis_rq_tdata_int = tlp_header_data_wr[63:0];
m_axis_rq_tkeep_int = 2'b11;
m_axis_rq_tvalid_int = 1'b1;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
tlp_output_state_next = TLP_OUTPUT_STATE_WR_HEADER;
end else if (AXIS_PCIE_DATA_WIDTH == 128) begin
// 128 bit interface, send complete header (write request)
m_axis_rq_tdata_int = tlp_header_data_wr;
m_axis_rq_tkeep_int = 4'b1111;
m_axis_rq_tvalid_int = 1'b1;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end else begin
// wider interface, send header and start of payload (write request)
m_axis_rq_tdata_int = {tx_wr_req_tlp_data, tlp_header_data_wr};
m_axis_rq_tkeep_int = {tx_wr_req_tlp_strb, 4'b1111};
m_axis_rq_tvalid_int = 1'b1;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
tx_wr_req_tlp_ready_cmb = 1'b1;
out_tlp_data_next = tx_wr_req_tlp_data;
out_tlp_strb_next = tx_wr_req_tlp_strb;
out_tlp_eop_next = tx_wr_req_tlp_eop;
if (tx_wr_req_tlp_eop && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0)) begin
m_axis_rq_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end
end
TLP_OUTPUT_STATE_RD_HEADER: begin
// second cycle of header (read request) (64 bit interface width only)
if (AXIS_PCIE_DATA_WIDTH == 64) begin
m_axis_rq_tdata_int = tlp_header_data_rd[127:64];
m_axis_rq_tkeep_int = 2'b11;
m_axis_rq_tlast_int = 1'b1;
m_axis_rq_tuser_int = tlp_tuser_rd;
if (tx_rd_req_tlp_valid && m_axis_rq_tready_int) begin
m_axis_rq_tvalid_int = 1'b1;
tx_rd_req_tlp_ready_cmb = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_RD_HEADER;
end
end
end
TLP_OUTPUT_STATE_WR_HEADER: begin
// second cycle of header (write request) (64 bit interface width only)
if (AXIS_PCIE_DATA_WIDTH == 64) begin
m_axis_rq_tdata_int = tlp_header_data_wr[127:64];
m_axis_rq_tkeep_int = 2'b11;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
if (tx_wr_req_tlp_valid && m_axis_rq_tready_int) begin
m_axis_rq_tvalid_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_HEADER;
end
end
end
TLP_OUTPUT_STATE_WR_PAYLOAD: begin
// transfer payload (write request)
if (AXIS_PCIE_DATA_WIDTH >= 256) begin
m_axis_rq_tdata_int = {tx_wr_req_tlp_data, out_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-128]};
if (tx_wr_req_tlp_valid && !out_tlp_eop_reg) begin
m_axis_rq_tkeep_int = {tx_wr_req_tlp_strb, out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-4]};
end else begin
m_axis_rq_tkeep_int = out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-4];
end
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
if ((tx_wr_req_tlp_valid || out_tlp_eop_reg) && m_axis_rq_tready_int) begin
m_axis_rq_tvalid_int = 1'b1;
tx_wr_req_tlp_ready_cmb = !out_tlp_eop_reg;
out_tlp_data_next = tx_wr_req_tlp_data;
out_tlp_strb_next = tx_wr_req_tlp_strb;
out_tlp_eop_next = tx_wr_req_tlp_eop;
if (out_tlp_eop_reg || (tx_wr_req_tlp_eop && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0))) begin
m_axis_rq_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end else begin
m_axis_rq_tdata_int = tx_wr_req_tlp_data;
m_axis_rq_tkeep_int = tx_wr_req_tlp_strb;
m_axis_rq_tlast_int = 1'b0;
m_axis_rq_tuser_int = tlp_tuser_wr;
if (tx_wr_req_tlp_valid && m_axis_rq_tready_int) begin
m_axis_rq_tvalid_int = 1'b1;
tx_wr_req_tlp_ready_cmb = 1'b1;
if (tx_wr_req_tlp_eop) begin
m_axis_rq_tlast_int = 1'b1;
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end else begin
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
end
end
end
endcase
end
always @(posedge clk) begin
tlp_output_state_reg <= tlp_output_state_next;
out_tlp_data_reg <= out_tlp_data_next;
out_tlp_strb_reg <= out_tlp_strb_next;
out_tlp_eop_reg <= out_tlp_eop_next;
if (rst) begin
tlp_output_state_reg <= TLP_OUTPUT_STATE_IDLE;
end
end
// output datapath logic (PCIe TLP)
reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}};
reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}};
reg m_axis_rq_tvalid_reg = 1'b0, m_axis_rq_tvalid_next;
reg m_axis_rq_tlast_reg = 1'b0;
reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser_reg = {AXIS_PCIE_RQ_USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed" *)
reg [AXIS_PCIE_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg [AXIS_PCIE_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed" *)
reg [AXIS_PCIE_RQ_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign m_axis_rq_tready_int = !out_fifo_half_full_reg;
assign m_axis_rq_tdata = m_axis_rq_tdata_reg;
assign m_axis_rq_tkeep = m_axis_rq_tkeep_reg;
assign m_axis_rq_tvalid = m_axis_rq_tvalid_reg;
assign m_axis_rq_tlast = m_axis_rq_tlast_reg;
assign m_axis_rq_tuser = m_axis_rq_tuser_reg;
always @(posedge clk) begin
m_axis_rq_tvalid_reg <= m_axis_rq_tvalid_reg && !m_axis_rq_tready;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_rq_tvalid_int) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_rq_tdata_int;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_rq_tkeep_int;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_rq_tlast_int;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_rq_tuser_int;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_rq_tvalid_reg || m_axis_rq_tready)) begin
m_axis_rq_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_rq_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_rq_tvalid_reg <= 1'b1;
m_axis_rq_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_rq_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_rq_tvalid_reg <= 1'b0;
end
end
endmodule |
module pcie_us_if_cq #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream CQ tuser signal width
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input (CQ)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tvalid,
output wire s_axis_cq_tready,
input wire s_axis_cq_tlast,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
/*
* TLP output (request to BAR)
*/
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
input wire rx_req_tlp_ready
);
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXIS_PCIE_DATA_WIDTH == 512) begin
if (AXIS_PCIE_CQ_USER_WIDTH != 183) begin
$error("Error: PCIe CQ tuser width must be 183 (instance %m)");
$finish;
end
end else begin
if (AXIS_PCIE_CQ_USER_WIDTH != 85 && AXIS_PCIE_CQ_USER_WIDTH != 88) begin
$error("Error: PCIe CQ tuser width must be 85 or 88 (instance %m)");
$finish;
end
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
end
localparam [2:0]
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
localparam [3:0]
REQ_MEM_READ = 4'b0000,
REQ_MEM_WRITE = 4'b0001,
REQ_IO_READ = 4'b0010,
REQ_IO_WRITE = 4'b0011,
REQ_MEM_FETCH_ADD = 4'b0100,
REQ_MEM_SWAP = 4'b0101,
REQ_MEM_CAS = 4'b0110,
REQ_MEM_READ_LOCKED = 4'b0111,
REQ_CFG_READ_0 = 4'b1000,
REQ_CFG_READ_1 = 4'b1001,
REQ_CFG_WRITE_0 = 4'b1010,
REQ_CFG_WRITE_1 = 4'b1011,
REQ_MSG = 4'b1100,
REQ_MSG_VENDOR = 4'b1101,
REQ_MSG_ATS = 4'b1110;
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0, rx_req_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb_reg = 0, rx_req_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0, rx_req_tlp_hdr_next;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0, rx_req_tlp_bar_id_next;
reg [TLP_SEG_COUNT*7-1:0] rx_req_tlp_func_num_reg = 0, rx_req_tlp_func_num_next;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0, rx_req_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_reg = 0, rx_req_tlp_sop_next;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_reg = 0, rx_req_tlp_eop_next;
assign rx_req_tlp_data = rx_req_tlp_data_reg;
assign rx_req_tlp_strb = rx_req_tlp_strb_reg;
assign rx_req_tlp_hdr = rx_req_tlp_hdr_reg;
assign rx_req_tlp_bar_id = rx_req_tlp_bar_id_reg;
assign rx_req_tlp_func_num = rx_req_tlp_func_num_reg;
assign rx_req_tlp_valid = rx_req_tlp_valid_reg;
assign rx_req_tlp_sop = rx_req_tlp_sop_reg;
assign rx_req_tlp_eop = rx_req_tlp_eop_reg;
localparam [1:0]
TLP_INPUT_STATE_IDLE = 2'd0,
TLP_INPUT_STATE_HEADER = 2'd1,
TLP_INPUT_STATE_PAYLOAD = 2'd2;
reg [1:0] tlp_input_state_reg = TLP_INPUT_STATE_IDLE, tlp_input_state_next;
reg s_axis_cq_tready_cmb;
reg tlp_input_frame_reg = 1'b0, tlp_input_frame_next;
reg [AXIS_PCIE_DATA_WIDTH-1:0] cq_tdata_int_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}, cq_tdata_int_next;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] cq_tkeep_int_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}, cq_tkeep_int_next;
reg cq_tvalid_int_reg = 1'b0, cq_tvalid_int_next;
reg cq_tlast_int_reg = 1'b0, cq_tlast_int_next;
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] cq_tuser_int_reg = {AXIS_PCIE_CQ_USER_WIDTH{1'b0}}, cq_tuser_int_next;
wire [AXIS_PCIE_DATA_WIDTH*2-1:0] cq_tdata = {s_axis_cq_tdata, cq_tdata_int_reg};
wire [AXIS_PCIE_KEEP_WIDTH*2-1:0] cq_tkeep = {s_axis_cq_tkeep, cq_tkeep_int_reg};
reg [127:0] tlp_hdr;
reg [2:0] tlp_bar_id;
reg [7:0] tlp_func_num;
assign s_axis_cq_tready = s_axis_cq_tready_cmb;
always @* begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
rx_req_tlp_data_next = rx_req_tlp_data_reg;
rx_req_tlp_strb_next = rx_req_tlp_strb_reg;
rx_req_tlp_hdr_next = rx_req_tlp_hdr_reg;
rx_req_tlp_bar_id_next = rx_req_tlp_bar_id_reg;
rx_req_tlp_func_num_next = rx_req_tlp_func_num_reg;
rx_req_tlp_valid_next = rx_req_tlp_valid_reg && !rx_req_tlp_ready;
rx_req_tlp_sop_next = rx_req_tlp_sop_reg;
rx_req_tlp_eop_next = rx_req_tlp_eop_reg;
s_axis_cq_tready_cmb = rx_req_tlp_ready;
tlp_input_frame_next = tlp_input_frame_reg;
cq_tdata_int_next = cq_tdata_int_reg;
cq_tkeep_int_next = cq_tkeep_int_reg;
cq_tvalid_int_next = cq_tvalid_int_reg;
cq_tlast_int_next = cq_tlast_int_reg;
cq_tuser_int_next = cq_tuser_int_reg;
if (s_axis_cq_tready && s_axis_cq_tvalid) begin
cq_tdata_int_next = s_axis_cq_tdata;
cq_tkeep_int_next = s_axis_cq_tkeep;
cq_tvalid_int_next = s_axis_cq_tvalid;
cq_tlast_int_next = s_axis_cq_tlast;
cq_tuser_int_next = s_axis_cq_tuser;
end
// parse header
// DW 0
case (cq_tdata[78:75])
REQ_MEM_READ: begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
tlp_hdr[124:120] = {5'b00000}; // type
end
REQ_MEM_WRITE: begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
tlp_hdr[124:120] = {5'b00000}; // type
end
REQ_IO_READ: begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
tlp_hdr[124:120] = {5'b00010}; // type
end
REQ_IO_WRITE: begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
tlp_hdr[124:120] = {5'b00010}; // type
end
REQ_MEM_FETCH_ADD: begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
tlp_hdr[124:120] = {5'b01100}; // type
end
REQ_MEM_SWAP: begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
tlp_hdr[124:120] = {5'b01101}; // type
end
REQ_MEM_CAS: begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
tlp_hdr[124:120] = {5'b01110}; // type
end
REQ_MEM_READ_LOCKED: begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
tlp_hdr[124:120] = {5'b00001}; // type
end
REQ_MSG: begin
if (cq_tdata[74:64]) begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
end else begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
end
tlp_hdr[124:120] = {2'b10, cq_tdata[114:112]}; // type
end
REQ_MSG_VENDOR: begin
if (cq_tdata[74:64]) begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
end else begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
end
tlp_hdr[124:120] = {2'b10, cq_tdata[114:112]}; // type
end
REQ_MSG_ATS: begin
if (cq_tdata[74:64]) begin
tlp_hdr[127:125] = TLP_FMT_4DW_DATA; // fmt
end else begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
end
tlp_hdr[124:120] = {2'b10, cq_tdata[114:112]}; // type
end
default: begin
tlp_hdr[127:125] = TLP_FMT_4DW; // fmt
tlp_hdr[124:120] = {5'b00000}; // type
end
endcase
tlp_hdr[119] = 1'b0; // T9
tlp_hdr[118:116] = cq_tdata[123:121]; // TC
tlp_hdr[115] = 1'b0; // T8
tlp_hdr[114] = cq_tdata[126]; // attr
tlp_hdr[113] = 1'b0; // LN
tlp_hdr[112] = 1'b0; // TH
tlp_hdr[111] = 1'b0; // TD
tlp_hdr[110] = 1'b0; // EP
tlp_hdr[109:108] = cq_tdata[125:124]; // attr
tlp_hdr[107:106] = cq_tdata[1:0]; // AT
tlp_hdr[105:96] = cq_tdata[74:64]; // length
// DW 1
tlp_hdr[95:80] = cq_tdata[95:80]; // requester ID
tlp_hdr[79:72] = cq_tdata[103:96]; // tag
if (AXIS_PCIE_DATA_WIDTH == 512) begin
tlp_hdr[71:68] = cq_tuser_int_reg[11:8]; // last BE
tlp_hdr[67:64] = cq_tuser_int_reg[3:0]; // first BE
end else begin
tlp_hdr[71:68] = cq_tuser_int_reg[7:4]; // last BE
tlp_hdr[67:64] = cq_tuser_int_reg[3:0]; // first BE
end
// DW 2+3
tlp_hdr[63:2] = cq_tdata[63:2]; // address
tlp_hdr[1:0] = 2'b00; // PH
tlp_bar_id = cq_tdata[114:112];
tlp_func_num = cq_tdata[111:104];
case (tlp_input_state_reg)
TLP_INPUT_STATE_IDLE: begin
s_axis_cq_tready_cmb = rx_req_tlp_ready;
if (cq_tvalid_int_reg && rx_req_tlp_ready) begin
rx_req_tlp_hdr_next = tlp_hdr;
rx_req_tlp_bar_id_next = tlp_bar_id;
rx_req_tlp_func_num_next = tlp_func_num;
if (AXIS_PCIE_DATA_WIDTH > 64) begin
rx_req_tlp_data_next = cq_tdata >> 128;
rx_req_tlp_strb_next = cq_tkeep >> 4;
rx_req_tlp_sop_next = 1'b1;
rx_req_tlp_eop_next = 1'b0;
tlp_input_frame_next = 1'b1;
if (cq_tlast_int_reg) begin
rx_req_tlp_valid_next = 1'b1;
rx_req_tlp_strb_next = cq_tkeep_int_reg >> 4;
rx_req_tlp_eop_next = 1'b1;
cq_tvalid_int_next = s_axis_cq_tready && s_axis_cq_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
if (s_axis_cq_tlast && s_axis_cq_tkeep >> 4 == 0) begin
rx_req_tlp_valid_next = 1'b1;
rx_req_tlp_eop_next = 1'b1;
cq_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
rx_req_tlp_valid_next = 1'b1;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end else begin
rx_req_tlp_data_next = 0;
rx_req_tlp_strb_next = 0;
rx_req_tlp_sop_next = 1'b1;
rx_req_tlp_eop_next = 1'b0;
if (cq_tlast_int_reg) begin
cq_tvalid_int_next = s_axis_cq_tready && s_axis_cq_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
if (s_axis_cq_tlast) begin
rx_req_tlp_valid_next = 1'b1;
rx_req_tlp_strb_next = 0;
rx_req_tlp_eop_next = 1'b1;
cq_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end
TLP_INPUT_STATE_PAYLOAD: begin
s_axis_cq_tready_cmb = rx_req_tlp_ready;
if (cq_tvalid_int_reg && rx_req_tlp_ready) begin
if (AXIS_PCIE_DATA_WIDTH > 128) begin
rx_req_tlp_data_next = cq_tdata >> 128;
rx_req_tlp_strb_next = cq_tkeep >> 4;
rx_req_tlp_sop_next = 1'b0;
end else begin
rx_req_tlp_data_next = s_axis_cq_tdata;
rx_req_tlp_strb_next = s_axis_cq_tkeep;
rx_req_tlp_sop_next = !tlp_input_frame_reg;
end
rx_req_tlp_eop_next = 1'b0;
if (cq_tlast_int_reg) begin
rx_req_tlp_valid_next = 1'b1;
rx_req_tlp_strb_next = cq_tkeep_int_reg >> 4;
rx_req_tlp_eop_next = 1'b1;
cq_tvalid_int_next = s_axis_cq_tready && s_axis_cq_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_cq_tready && s_axis_cq_tvalid) begin
if (s_axis_cq_tlast && s_axis_cq_tkeep >> 4 == 0) begin
rx_req_tlp_valid_next = 1'b1;
rx_req_tlp_eop_next = 1'b1;
cq_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
rx_req_tlp_valid_next = 1'b1;
tlp_input_frame_next = 1'b1;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end
endcase
end
always @(posedge clk) begin
tlp_input_state_reg <= tlp_input_state_next;
rx_req_tlp_data_reg <= rx_req_tlp_data_next;
rx_req_tlp_strb_reg <= rx_req_tlp_strb_next;
rx_req_tlp_hdr_reg <= rx_req_tlp_hdr_next;
rx_req_tlp_bar_id_reg <= rx_req_tlp_bar_id_next;
rx_req_tlp_func_num_reg <= rx_req_tlp_func_num_next;
rx_req_tlp_valid_reg <= rx_req_tlp_valid_next;
rx_req_tlp_sop_reg <= rx_req_tlp_sop_next;
rx_req_tlp_eop_reg <= rx_req_tlp_eop_next;
tlp_input_frame_reg <= tlp_input_frame_next;
cq_tdata_int_reg <= cq_tdata_int_next;
cq_tkeep_int_reg <= cq_tkeep_int_next;
cq_tvalid_int_reg <= cq_tvalid_int_next;
cq_tlast_int_reg <= cq_tlast_int_next;
cq_tuser_int_reg <= cq_tuser_int_next;
if (rst) begin
tlp_input_state_reg <= TLP_INPUT_STATE_IDLE;
rx_req_tlp_valid_reg <= 0;
cq_tvalid_int_reg <= 1'b0;
end
end
endmodule |
module pcie_us_if_rc #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream RC tuser signal width
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input (RC)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tvalid,
output wire s_axis_rc_tready,
input wire s_axis_rc_tlast,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
/*
* TLP output (completion to DMA)
*/
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready
);
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
$finish;
end
if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
if (AXIS_PCIE_DATA_WIDTH == 512) begin
if (AXIS_PCIE_RC_USER_WIDTH != 161) begin
$error("Error: PCIe RC tuser width must be 161 (instance %m)");
$finish;
end
end else begin
if (AXIS_PCIE_RC_USER_WIDTH != 75) begin
$error("Error: PCIe RC tuser width must be 75 (instance %m)");
$finish;
end
end
if (TLP_SEG_COUNT != 1) begin
$error("Error: TLP segment count must be 1 (instance %m)");
$finish;
end
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
end
localparam [2:0]
TLP_FMT_3DW = 3'b000,
TLP_FMT_4DW = 3'b001,
TLP_FMT_3DW_DATA = 3'b010,
TLP_FMT_4DW_DATA = 3'b011,
TLP_FMT_PREFIX = 3'b100;
localparam [2:0]
CPL_STATUS_SC = 3'b000, // successful completion
CPL_STATUS_UR = 3'b001, // unsupported request
CPL_STATUS_CRS = 3'b010, // configuration request retry status
CPL_STATUS_CA = 3'b100; // completer abort
localparam [3:0]
RC_ERROR_NORMAL_TERMINATION = 4'b0000,
RC_ERROR_POISONED = 4'b0001,
RC_ERROR_BAD_STATUS = 4'b0010,
RC_ERROR_INVALID_LENGTH = 4'b0011,
RC_ERROR_MISMATCH = 4'b0100,
RC_ERROR_INVALID_ADDRESS = 4'b0101,
RC_ERROR_INVALID_TAG = 4'b0110,
RC_ERROR_TIMEOUT = 4'b1001,
RC_ERROR_FLR = 4'b1000;
localparam [3:0]
PCIE_ERROR_NONE = 4'd0,
PCIE_ERROR_POISONED = 4'd1,
PCIE_ERROR_BAD_STATUS = 4'd2,
PCIE_ERROR_MISMATCH = 4'd3,
PCIE_ERROR_INVALID_LEN = 4'd4,
PCIE_ERROR_INVALID_ADDR = 4'd5,
PCIE_ERROR_INVALID_TAG = 4'd6,
PCIE_ERROR_FLR = 4'd8,
PCIE_ERROR_TIMEOUT = 4'd15;
reg [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0, rx_cpl_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb_reg = 0, rx_cpl_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0, rx_cpl_tlp_hdr_next;
reg [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error_reg = 0, rx_cpl_tlp_error_next;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_reg = 0, rx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop_reg = 0, rx_cpl_tlp_sop_next;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop_reg = 0, rx_cpl_tlp_eop_next;
assign rx_cpl_tlp_data = rx_cpl_tlp_data_reg;
assign rx_cpl_tlp_strb = rx_cpl_tlp_strb_reg;
assign rx_cpl_tlp_hdr = rx_cpl_tlp_hdr_reg;
assign rx_cpl_tlp_error = rx_cpl_tlp_error_reg;
assign rx_cpl_tlp_valid = rx_cpl_tlp_valid_reg;
assign rx_cpl_tlp_sop = rx_cpl_tlp_sop_reg;
assign rx_cpl_tlp_eop = rx_cpl_tlp_eop_reg;
localparam [1:0]
TLP_INPUT_STATE_IDLE = 2'd0,
TLP_INPUT_STATE_HEADER = 2'd1,
TLP_INPUT_STATE_PAYLOAD = 2'd2;
reg [1:0] tlp_input_state_reg = TLP_INPUT_STATE_IDLE, tlp_input_state_next;
reg s_axis_rc_tready_cmb;
reg tlp_input_frame_reg = 1'b0, tlp_input_frame_next;
reg [AXIS_PCIE_DATA_WIDTH-1:0] rc_tdata_int_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}}, rc_tdata_int_next;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] rc_tkeep_int_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}}, rc_tkeep_int_next;
reg rc_tvalid_int_reg = 1'b0, rc_tvalid_int_next;
reg rc_tlast_int_reg = 1'b0, rc_tlast_int_next;
wire [AXIS_PCIE_DATA_WIDTH*2-1:0] rc_tdata = {s_axis_rc_tdata, rc_tdata_int_reg};
wire [AXIS_PCIE_KEEP_WIDTH*2-1:0] rc_tkeep = {s_axis_rc_tkeep, rc_tkeep_int_reg};
reg [127:0] tlp_hdr;
reg [3:0] tlp_error;
assign s_axis_rc_tready = s_axis_rc_tready_cmb;
always @* begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
rx_cpl_tlp_data_next = rx_cpl_tlp_data_reg;
rx_cpl_tlp_strb_next = rx_cpl_tlp_strb_reg;
rx_cpl_tlp_hdr_next = rx_cpl_tlp_hdr_reg;
rx_cpl_tlp_error_next = rx_cpl_tlp_error_reg;
rx_cpl_tlp_valid_next = rx_cpl_tlp_valid_reg && !rx_cpl_tlp_ready;
rx_cpl_tlp_sop_next = rx_cpl_tlp_sop_reg;
rx_cpl_tlp_eop_next = rx_cpl_tlp_eop_reg;
s_axis_rc_tready_cmb = rx_cpl_tlp_ready;
tlp_input_frame_next = tlp_input_frame_reg;
rc_tdata_int_next = rc_tdata_int_reg;
rc_tkeep_int_next = rc_tkeep_int_reg;
rc_tvalid_int_next = rc_tvalid_int_reg;
rc_tlast_int_next = rc_tlast_int_reg;
if (s_axis_rc_tready && s_axis_rc_tvalid) begin
rc_tdata_int_next = s_axis_rc_tdata;
rc_tkeep_int_next = s_axis_rc_tkeep;
rc_tvalid_int_next = s_axis_rc_tvalid;
rc_tlast_int_next = s_axis_rc_tlast;
end
// parse header
// DW 0
if (rc_tdata[42:32] != 0) begin
tlp_hdr[127:125] = TLP_FMT_3DW_DATA; // fmt - 3DW with data
end else begin
tlp_hdr[127:125] = TLP_FMT_3DW; // fmt - 3DW without data
end
tlp_hdr[124:120] = {4'b0101, rc_tdata[29]}; // type - completion
tlp_hdr[119] = 1'b0; // T9
tlp_hdr[118:116] = rc_tdata[91:89]; // TC
tlp_hdr[115] = 1'b0; // T8
tlp_hdr[114] = rc_tdata[94]; // attr
tlp_hdr[113] = 1'b0; // LN
tlp_hdr[112] = 1'b0; // TH
tlp_hdr[111] = 1'b0; // TD
tlp_hdr[110] = rc_tdata[46]; // EP
tlp_hdr[109:108] = rc_tdata[93:92]; // attr
tlp_hdr[107:106] = 2'b00; // AT
tlp_hdr[105:96] = rc_tdata[42:32]; // length
// DW 1
tlp_hdr[95:80] = rc_tdata[87:72]; // completer ID
tlp_hdr[79:77] = rc_tdata[45:43]; // completion status
tlp_hdr[76] = 1'b0; // BCM
tlp_hdr[75:64] = rc_tdata[28:16]; // byte count
// DW 2
tlp_hdr[63:48] = rc_tdata[63:48]; // requester ID
tlp_hdr[47:40] = rc_tdata[71:64]; // tag
tlp_hdr[39] = 1'b0;
tlp_hdr[38:32] = rc_tdata[6:0]; // lower address
// DW 3
tlp_hdr[31:0] = 32'd0;
// error code
case (rc_tdata[15:12])
RC_ERROR_NORMAL_TERMINATION: tlp_error = PCIE_ERROR_NONE;
RC_ERROR_POISONED: tlp_error = PCIE_ERROR_POISONED;
RC_ERROR_BAD_STATUS: tlp_error = PCIE_ERROR_BAD_STATUS;
RC_ERROR_INVALID_LENGTH: tlp_error = PCIE_ERROR_INVALID_LEN;
RC_ERROR_MISMATCH: tlp_error = PCIE_ERROR_MISMATCH;
RC_ERROR_INVALID_ADDRESS: tlp_error = PCIE_ERROR_INVALID_ADDR;
RC_ERROR_INVALID_TAG: tlp_error = PCIE_ERROR_INVALID_TAG;
RC_ERROR_FLR: tlp_error = PCIE_ERROR_FLR;
RC_ERROR_TIMEOUT: tlp_error = PCIE_ERROR_TIMEOUT;
default: tlp_error = PCIE_ERROR_NONE;
endcase
case (tlp_input_state_reg)
TLP_INPUT_STATE_IDLE: begin
s_axis_rc_tready_cmb = rx_cpl_tlp_ready;
if (rc_tvalid_int_reg && rx_cpl_tlp_ready) begin
rx_cpl_tlp_hdr_next = tlp_hdr;
rx_cpl_tlp_error_next = tlp_error;
if (AXIS_PCIE_DATA_WIDTH > 64) begin
rx_cpl_tlp_data_next = rc_tdata >> 96;
rx_cpl_tlp_strb_next = rc_tkeep >> 3;
rx_cpl_tlp_sop_next = 1'b1;
rx_cpl_tlp_eop_next = 1'b0;
tlp_input_frame_next = 1'b1;
if (rc_tlast_int_reg) begin
rx_cpl_tlp_valid_next = 1'b1;
rx_cpl_tlp_strb_next = rc_tkeep_int_reg >> 3;
rx_cpl_tlp_eop_next = 1'b1;
rc_tvalid_int_next = s_axis_rc_tready && s_axis_rc_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_rc_tready && s_axis_rc_tvalid) begin
if (s_axis_rc_tlast && s_axis_rc_tkeep >> 3 == 0) begin
rx_cpl_tlp_valid_next = 1'b1;
rx_cpl_tlp_eop_next = 1'b1;
rc_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
rx_cpl_tlp_valid_next = 1'b1;
tlp_input_frame_next = 1'b1;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end else begin
rx_cpl_tlp_data_next = rc_tdata >> 96;
rx_cpl_tlp_strb_next = rc_tkeep >> 3;
rx_cpl_tlp_sop_next = 1'b1;
rx_cpl_tlp_eop_next = 1'b0;
if (rc_tlast_int_reg) begin
rc_tvalid_int_next = s_axis_rc_tready && s_axis_rc_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_rc_tready && s_axis_rc_tvalid) begin
if (s_axis_rc_tlast) begin
rx_cpl_tlp_valid_next = 1'b1;
rx_cpl_tlp_strb_next = s_axis_rc_tkeep >> 1;
rx_cpl_tlp_eop_next = 1'b1;
rc_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end
end
TLP_INPUT_STATE_PAYLOAD: begin
s_axis_rc_tready_cmb = rx_cpl_tlp_ready;
if (rc_tvalid_int_reg && rx_cpl_tlp_ready) begin
if (AXIS_PCIE_DATA_WIDTH > 64) begin
rx_cpl_tlp_data_next = rc_tdata >> 96;
rx_cpl_tlp_strb_next = rc_tkeep >> 3;
rx_cpl_tlp_sop_next = 1'b0;
end else begin
rx_cpl_tlp_data_next = rc_tdata >> 32;
rx_cpl_tlp_strb_next = rc_tkeep >> 1;
rx_cpl_tlp_sop_next = !tlp_input_frame_reg;
end
rx_cpl_tlp_eop_next = 1'b0;
if (rc_tlast_int_reg) begin
rx_cpl_tlp_valid_next = 1'b1;
if (AXIS_PCIE_DATA_WIDTH > 64) begin
rx_cpl_tlp_strb_next = rc_tkeep_int_reg >> 3;
end else begin
rx_cpl_tlp_strb_next = rc_tkeep_int_reg >> 1;
end
rx_cpl_tlp_eop_next = 1'b1;
rc_tvalid_int_next = s_axis_rc_tready && s_axis_rc_tvalid;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else if (s_axis_rc_tready && s_axis_rc_tvalid) begin
if (s_axis_rc_tlast && (s_axis_rc_tkeep >> (AXIS_PCIE_DATA_WIDTH > 64 ? 3 : 1)) == 0) begin
rx_cpl_tlp_valid_next = 1'b1;
rx_cpl_tlp_eop_next = 1'b1;
rc_tvalid_int_next = 1'b0;
tlp_input_frame_next = 1'b0;
tlp_input_state_next = TLP_INPUT_STATE_IDLE;
end else begin
rx_cpl_tlp_valid_next = 1'b1;
tlp_input_frame_next = 1'b1;
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end else begin
tlp_input_state_next = TLP_INPUT_STATE_PAYLOAD;
end
end
endcase
end
always @(posedge clk) begin
tlp_input_state_reg <= tlp_input_state_next;
rx_cpl_tlp_data_reg <= rx_cpl_tlp_data_next;
rx_cpl_tlp_strb_reg <= rx_cpl_tlp_strb_next;
rx_cpl_tlp_hdr_reg <= rx_cpl_tlp_hdr_next;
rx_cpl_tlp_error_reg <= rx_cpl_tlp_error_next;
rx_cpl_tlp_valid_reg <= rx_cpl_tlp_valid_next;
rx_cpl_tlp_sop_reg <= rx_cpl_tlp_sop_next;
rx_cpl_tlp_eop_reg <= rx_cpl_tlp_eop_next;
tlp_input_frame_reg <= tlp_input_frame_next;
rc_tdata_int_reg <= rc_tdata_int_next;
rc_tkeep_int_reg <= rc_tkeep_int_next;
rc_tvalid_int_reg <= rc_tvalid_int_next;
rc_tlast_int_reg <= rc_tlast_int_next;
if (rst) begin
tlp_input_state_reg <= TLP_INPUT_STATE_IDLE;
rx_cpl_tlp_valid_reg <= 0;
rc_tvalid_int_reg <= 1'b0;
end
end
endmodule |
module fpga_core #
(
parameter AXIS_PCIE_DATA_WIDTH = 512,
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
parameter RQ_SEQ_NUM_ENABLE = 1,
parameter PCIE_TAG_COUNT = 64,
parameter BAR0_APERTURE = 24,
parameter BAR2_APERTURE = 24
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* PCIe
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tlast,
input wire m_axis_rq_tready,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
output wire m_axis_rq_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tlast,
output wire s_axis_rc_tready,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
input wire s_axis_rc_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tlast,
output wire s_axis_cq_tready,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
input wire s_axis_cq_tvalid,
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tlast,
input wire m_axis_cc_tready,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
output wire m_axis_cc_tvalid,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor,
output wire status_error_uncor
);
example_core_pcie_us #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
example_core_pcie_us_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(8'd0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Configuration
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module fpga_core #
(
parameter AXIS_PCIE_DATA_WIDTH = 256,
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
parameter AXIS_PCIE_RC_USER_WIDTH = 75,
parameter AXIS_PCIE_RQ_USER_WIDTH = 60,
parameter AXIS_PCIE_CQ_USER_WIDTH = 85,
parameter AXIS_PCIE_CC_USER_WIDTH = 33,
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
parameter RQ_SEQ_NUM_ENABLE = 1,
parameter PCIE_TAG_COUNT = 64,
parameter BAR0_APERTURE = 24,
parameter BAR2_APERTURE = 24
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] sfp_1_led,
output wire [1:0] sfp_2_led,
output wire [1:0] sma_led,
/*
* PCIe
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tlast,
input wire m_axis_rq_tready,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
output wire m_axis_rq_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tlast,
output wire s_axis_rc_tready,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
input wire s_axis_rc_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tlast,
output wire s_axis_cq_tready,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
input wire s_axis_cq_tvalid,
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tlast,
input wire m_axis_cc_tready,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
output wire m_axis_cc_tvalid,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num,
input wire s_axis_rq_seq_num_valid,
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
input wire [3:0] cfg_interrupt_msi_enable,
input wire [7:0] cfg_interrupt_msi_vf_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor,
output wire status_error_uncor
);
assign sfp_1_led = 2'b00;
assign sfp_2_led = 2'b00;
assign sma_led = 2'b00;
example_core_pcie_us #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
example_core_pcie_us_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid),
.s_axis_rq_seq_num_1(0),
.s_axis_rq_seq_num_valid_1(0),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Configuration
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
assign cfg_mgmt_addr[18] = 1'b0;
endmodule |
module fpga (
/*
* GPIO
*/
input wire [3:0] sw,
output wire [2:0] led,
/*
* PCI express
*/
input wire [15:0] pcie_rx_p,
input wire [15:0] pcie_rx_n,
output wire [15:0] pcie_tx_p,
output wire [15:0] pcie_tx_n,
input wire pcie_refclk_p,
input wire pcie_refclk_n,
input wire pcie_reset_n
);
parameter AXIS_PCIE_DATA_WIDTH = 512;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137;
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183;
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81;
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6;
parameter RQ_SEQ_NUM_ENABLE = 1;
parameter PCIE_TAG_COUNT = 64;
parameter BAR0_APERTURE = 24;
parameter BAR2_APERTURE = 24;
// Clock and reset
wire pcie_user_clk;
wire pcie_user_reset;
// GPIO
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(4),
.N(4),
.RATE(250000)
)
debounce_switch_inst (
.clk(pcie_user_clk),
.rst(pcie_user_reset),
.in({sw}),
.out({sw_int})
);
// PCIe
wire pcie_sys_clk;
wire pcie_sys_clk_gt;
IBUFDS_GTE4 #(
.REFCLK_HROW_CK_SEL(2'b00)
)
ibufds_gte4_pcie_mgt_refclk_inst (
.I (pcie_refclk_p),
.IB (pcie_refclk_n),
.CEB (1'b0),
.O (pcie_sys_clk_gt),
.ODIV2 (pcie_sys_clk)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
wire axis_rq_tlast;
wire axis_rq_tready;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
wire axis_rq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
wire axis_rc_tlast;
wire axis_rc_tready;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
wire axis_rc_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
wire axis_cq_tlast;
wire axis_cq_tready;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
wire axis_cq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
wire axis_cc_tlast;
wire axis_cc_tready;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
wire axis_cc_tvalid;
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0;
wire pcie_rq_seq_num_vld0;
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1;
wire pcie_rq_seq_num_vld1;
// ila_0 rq_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rq_tdata),
// .probe1(axis_rq_tkeep),
// .probe2(axis_rq_tlast),
// .probe3(axis_rq_tready),
// .probe4(axis_rq_tuser),
// .probe5(axis_rq_tvalid)
// );
// ila_0 rc_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rc_tdata),
// .probe1(axis_rc_tkeep),
// .probe2(axis_rc_tlast),
// .probe3(axis_rc_tready),
// .probe4(axis_rc_tuser),
// .probe5(axis_rc_tvalid)
// );
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
wire cfg_mgmt_write;
wire [31:0] cfg_mgmt_write_data;
wire [3:0] cfg_mgmt_byte_enable;
wire cfg_mgmt_read;
wire [31:0] cfg_mgmt_read_data;
wire cfg_mgmt_read_write_done;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable;
wire [11:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [31:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_pending_status_data_enable;
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor;
wire status_error_uncor;
pcie4_uscale_plus_0
pcie4_uscale_plus_inst (
.pci_exp_txn(pcie_tx_n),
.pci_exp_txp(pcie_tx_p),
.pci_exp_rxn(pcie_rx_n),
.pci_exp_rxp(pcie_rx_p),
.user_clk(pcie_user_clk),
.user_reset(pcie_user_reset),
.user_lnk_up(),
.s_axis_rq_tdata(axis_rq_tdata),
.s_axis_rq_tkeep(axis_rq_tkeep),
.s_axis_rq_tlast(axis_rq_tlast),
.s_axis_rq_tready(axis_rq_tready),
.s_axis_rq_tuser(axis_rq_tuser),
.s_axis_rq_tvalid(axis_rq_tvalid),
.m_axis_rc_tdata(axis_rc_tdata),
.m_axis_rc_tkeep(axis_rc_tkeep),
.m_axis_rc_tlast(axis_rc_tlast),
.m_axis_rc_tready(axis_rc_tready),
.m_axis_rc_tuser(axis_rc_tuser),
.m_axis_rc_tvalid(axis_rc_tvalid),
.m_axis_cq_tdata(axis_cq_tdata),
.m_axis_cq_tkeep(axis_cq_tkeep),
.m_axis_cq_tlast(axis_cq_tlast),
.m_axis_cq_tready(axis_cq_tready),
.m_axis_cq_tuser(axis_cq_tuser),
.m_axis_cq_tvalid(axis_cq_tvalid),
.s_axis_cc_tdata(axis_cc_tdata),
.s_axis_cc_tkeep(axis_cc_tkeep),
.s_axis_cc_tlast(axis_cc_tlast),
.s_axis_cc_tready(axis_cc_tready),
.s_axis_cc_tuser(axis_cc_tuser),
.s_axis_cc_tvalid(axis_cc_tvalid),
.pcie_rq_seq_num0(pcie_rq_seq_num0),
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
.pcie_rq_seq_num1(pcie_rq_seq_num1),
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
.pcie_rq_tag0(),
.pcie_rq_tag1(),
.pcie_rq_tag_av(),
.pcie_rq_tag_vld0(),
.pcie_rq_tag_vld1(),
.pcie_tfc_nph_av(),
.pcie_tfc_npd_av(),
.pcie_cq_np_req(1'b1),
.pcie_cq_np_req_count(),
.cfg_phy_link_down(),
.cfg_phy_link_status(),
.cfg_negotiated_width(),
.cfg_current_speed(),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_function_status(),
.cfg_function_power_state(),
.cfg_vf_status(),
.cfg_vf_power_state(),
.cfg_link_power_state(),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_mgmt_debug_access(1'b0),
.cfg_err_cor_out(),
.cfg_err_nonfatal_out(),
.cfg_err_fatal_out(),
.cfg_local_error_valid(),
.cfg_local_error_out(),
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
.cfg_tph_st_mode(),
.cfg_vf_tph_requester_enable(),
.cfg_vf_tph_st_mode(),
.cfg_msg_received(),
.cfg_msg_received_data(),
.cfg_msg_received_type(),
.cfg_msg_transmit(1'b0),
.cfg_msg_transmit_type(3'd0),
.cfg_msg_transmit_data(32'd0),
.cfg_msg_transmit_done(),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_dsn(64'd0),
.cfg_bus_number(),
.cfg_power_state_change_ack(1'b1),
.cfg_power_state_change_interrupt(),
.cfg_err_cor_in(status_error_cor),
.cfg_err_uncor_in(status_error_uncor),
.cfg_flr_in_process(),
.cfg_flr_done(4'd0),
.cfg_vf_flr_in_process(),
.cfg_vf_flr_func_num(8'd0),
.cfg_vf_flr_done(8'd0),
.cfg_link_training_enable(1'b1),
.cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0),
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
.cfg_hot_reset_out(),
.cfg_config_space_enable(1'b1),
.cfg_req_pm_transition_l23_ready(1'b0),
.cfg_hot_reset_in(1'b0),
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out()
);
fpga_core #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
core_inst (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk(pcie_user_clk),
.rst(pcie_user_reset),
/*
* GPIO
*/
.sw(sw_int),
.led(led),
/*
* PCIe
*/
.m_axis_rq_tdata(axis_rq_tdata),
.m_axis_rq_tkeep(axis_rq_tkeep),
.m_axis_rq_tlast(axis_rq_tlast),
.m_axis_rq_tready(axis_rq_tready),
.m_axis_rq_tuser(axis_rq_tuser),
.m_axis_rq_tvalid(axis_rq_tvalid),
.s_axis_rc_tdata(axis_rc_tdata),
.s_axis_rc_tkeep(axis_rc_tkeep),
.s_axis_rc_tlast(axis_rc_tlast),
.s_axis_rc_tready(axis_rc_tready),
.s_axis_rc_tuser(axis_rc_tuser),
.s_axis_rc_tvalid(axis_rc_tvalid),
.s_axis_cq_tdata(axis_cq_tdata),
.s_axis_cq_tkeep(axis_cq_tkeep),
.s_axis_cq_tlast(axis_cq_tlast),
.s_axis_cq_tready(axis_cq_tready),
.s_axis_cq_tuser(axis_cq_tuser),
.s_axis_cq_tvalid(axis_cq_tvalid),
.m_axis_cc_tdata(axis_cc_tdata),
.m_axis_cc_tkeep(axis_cc_tkeep),
.m_axis_cc_tlast(axis_cc_tlast),
.m_axis_cc_tready(axis_cc_tready),
.m_axis_cc_tuser(axis_cc_tuser),
.m_axis_cc_tvalid(axis_cc_tvalid),
.s_axis_rq_seq_num_0(pcie_rq_seq_num0),
.s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0),
.s_axis_rq_seq_num_1(pcie_rq_seq_num1),
.s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module fpga (
/*
* GPIO
*/
output wire led_sreg_d,
output wire led_sreg_ld,
output wire led_sreg_clk,
output wire [1:0] led_bmc,
output wire [1:0] led_exp,
/*
* PCI express
*/
input wire [15:0] pcie_rx_p,
input wire [15:0] pcie_rx_n,
output wire [15:0] pcie_tx_p,
output wire [15:0] pcie_tx_n,
input wire pcie_refclk_p,
input wire pcie_refclk_n,
input wire pcie_rst_n
);
parameter AXIS_PCIE_DATA_WIDTH = 512;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137;
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183;
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81;
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6;
parameter RQ_SEQ_NUM_ENABLE = 1;
parameter PCIE_TAG_COUNT = 64;
parameter BAR0_APERTURE = 24;
parameter BAR2_APERTURE = 24;
// PCIe
wire pcie_user_clk;
wire pcie_user_reset;
wire pcie_sys_clk;
wire pcie_sys_clk_gt;
IBUFDS_GTE4 #(
.REFCLK_HROW_CK_SEL(2'b00)
)
ibufds_gte4_pcie_mgt_refclk_inst (
.I (pcie_refclk_p),
.IB (pcie_refclk_n),
.CEB (1'b0),
.O (pcie_sys_clk_gt),
.ODIV2 (pcie_sys_clk)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
wire axis_rq_tlast;
wire axis_rq_tready;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
wire axis_rq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
wire axis_rc_tlast;
wire axis_rc_tready;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
wire axis_rc_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
wire axis_cq_tlast;
wire axis_cq_tready;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
wire axis_cq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
wire axis_cc_tlast;
wire axis_cc_tready;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
wire axis_cc_tvalid;
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0;
wire pcie_rq_seq_num_vld0;
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1;
wire pcie_rq_seq_num_vld1;
// ila_0 rq_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rq_tdata),
// .probe1(axis_rq_tkeep),
// .probe2(axis_rq_tlast),
// .probe3(axis_rq_tready),
// .probe4(axis_rq_tuser),
// .probe5(axis_rq_tvalid)
// );
// ila_0 rc_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rc_tdata),
// .probe1(axis_rc_tkeep),
// .probe2(axis_rc_tlast),
// .probe3(axis_rc_tready),
// .probe4(axis_rc_tuser),
// .probe5(axis_rc_tvalid)
// );
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
wire cfg_mgmt_write;
wire [31:0] cfg_mgmt_write_data;
wire [3:0] cfg_mgmt_byte_enable;
wire cfg_mgmt_read;
wire [31:0] cfg_mgmt_read_data;
wire cfg_mgmt_read_write_done;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
wire [3:0] cfg_interrupt_msi_enable;
wire [11:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [31:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_pending_status_data_enable;
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor;
wire status_error_uncor;
pcie4_uscale_plus_0
pcie4_uscale_plus_inst (
.pci_exp_txn(pcie_tx_n),
.pci_exp_txp(pcie_tx_p),
.pci_exp_rxn(pcie_rx_n),
.pci_exp_rxp(pcie_rx_p),
.user_clk(pcie_user_clk),
.user_reset(pcie_user_reset),
.user_lnk_up(),
.s_axis_rq_tdata(axis_rq_tdata),
.s_axis_rq_tkeep(axis_rq_tkeep),
.s_axis_rq_tlast(axis_rq_tlast),
.s_axis_rq_tready(axis_rq_tready),
.s_axis_rq_tuser(axis_rq_tuser),
.s_axis_rq_tvalid(axis_rq_tvalid),
.m_axis_rc_tdata(axis_rc_tdata),
.m_axis_rc_tkeep(axis_rc_tkeep),
.m_axis_rc_tlast(axis_rc_tlast),
.m_axis_rc_tready(axis_rc_tready),
.m_axis_rc_tuser(axis_rc_tuser),
.m_axis_rc_tvalid(axis_rc_tvalid),
.m_axis_cq_tdata(axis_cq_tdata),
.m_axis_cq_tkeep(axis_cq_tkeep),
.m_axis_cq_tlast(axis_cq_tlast),
.m_axis_cq_tready(axis_cq_tready),
.m_axis_cq_tuser(axis_cq_tuser),
.m_axis_cq_tvalid(axis_cq_tvalid),
.s_axis_cc_tdata(axis_cc_tdata),
.s_axis_cc_tkeep(axis_cc_tkeep),
.s_axis_cc_tlast(axis_cc_tlast),
.s_axis_cc_tready(axis_cc_tready),
.s_axis_cc_tuser(axis_cc_tuser),
.s_axis_cc_tvalid(axis_cc_tvalid),
.pcie_rq_seq_num0(pcie_rq_seq_num0),
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
.pcie_rq_seq_num1(pcie_rq_seq_num1),
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
.pcie_rq_tag0(),
.pcie_rq_tag1(),
.pcie_rq_tag_av(),
.pcie_rq_tag_vld0(),
.pcie_rq_tag_vld1(),
.pcie_tfc_nph_av(),
.pcie_tfc_npd_av(),
.pcie_cq_np_req(1'b1),
.pcie_cq_np_req_count(),
.cfg_phy_link_down(),
.cfg_phy_link_status(),
.cfg_negotiated_width(),
.cfg_current_speed(),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_function_status(),
.cfg_function_power_state(),
.cfg_vf_status(),
.cfg_vf_power_state(),
.cfg_link_power_state(),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_mgmt_debug_access(1'b0),
.cfg_err_cor_out(),
.cfg_err_nonfatal_out(),
.cfg_err_fatal_out(),
.cfg_local_error_valid(),
.cfg_local_error_out(),
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
.cfg_tph_st_mode(),
.cfg_vf_tph_requester_enable(),
.cfg_vf_tph_st_mode(),
.cfg_msg_received(),
.cfg_msg_received_data(),
.cfg_msg_received_type(),
.cfg_msg_transmit(1'b0),
.cfg_msg_transmit_type(3'd0),
.cfg_msg_transmit_data(32'd0),
.cfg_msg_transmit_done(),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_dsn(64'd0),
.cfg_bus_number(),
.cfg_power_state_change_ack(1'b1),
.cfg_power_state_change_interrupt(),
.cfg_err_cor_in(status_error_cor),
.cfg_err_uncor_in(status_error_uncor),
.cfg_flr_in_process(),
.cfg_flr_done(4'd0),
.cfg_vf_flr_in_process(),
.cfg_vf_flr_func_num(8'd0),
.cfg_vf_flr_done(8'd0),
.cfg_link_training_enable(1'b1),
.cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0),
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
.cfg_hot_reset_out(),
.cfg_config_space_enable(1'b1),
.cfg_req_pm_transition_l23_ready(1'b0),
.cfg_hot_reset_in(1'b0),
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),
.sys_reset(pcie_rst_n),
.phy_rdy_out()
);
// GPIO
wire [7:0] led_red;
wire [7:0] led_green;
wire [15:0] led_merged;
assign led_merged[0] = led_red[0];
assign led_merged[1] = led_green[0];
assign led_merged[2] = led_red[1];
assign led_merged[3] = led_green[1];
assign led_merged[4] = led_red[2];
assign led_merged[5] = led_green[2];
assign led_merged[6] = led_red[3];
assign led_merged[7] = led_green[3];
assign led_merged[8] = led_red[4];
assign led_merged[9] = led_green[4];
assign led_merged[10] = led_red[5];
assign led_merged[11] = led_green[5];
assign led_merged[12] = led_red[6];
assign led_merged[13] = led_green[6];
assign led_merged[14] = led_red[7];
assign led_merged[15] = led_green[7];
led_sreg_driver #(
.COUNT(16),
.INVERT(1),
.PRESCALE(63)
)
led_sreg_driver_inst (
.clk(pcie_user_clk),
.rst(pcie_user_reset),
.led(led_merged),
.sreg_d(led_sreg_d),
.sreg_ld(led_sreg_ld),
.sreg_clk(led_sreg_clk)
);
fpga_core #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
core_inst (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk(pcie_user_clk),
.rst(pcie_user_reset),
/*
* GPIO
*/
.led_red(led_red),
.led_green(led_green),
.led_bmc(led_bmc),
.led_exp(led_exp),
/*
* PCIe
*/
.m_axis_rq_tdata(axis_rq_tdata),
.m_axis_rq_tkeep(axis_rq_tkeep),
.m_axis_rq_tlast(axis_rq_tlast),
.m_axis_rq_tready(axis_rq_tready),
.m_axis_rq_tuser(axis_rq_tuser),
.m_axis_rq_tvalid(axis_rq_tvalid),
.s_axis_rc_tdata(axis_rc_tdata),
.s_axis_rc_tkeep(axis_rc_tkeep),
.s_axis_rc_tlast(axis_rc_tlast),
.s_axis_rc_tready(axis_rc_tready),
.s_axis_rc_tuser(axis_rc_tuser),
.s_axis_rc_tvalid(axis_rc_tvalid),
.s_axis_cq_tdata(axis_cq_tdata),
.s_axis_cq_tkeep(axis_cq_tkeep),
.s_axis_cq_tlast(axis_cq_tlast),
.s_axis_cq_tready(axis_cq_tready),
.s_axis_cq_tuser(axis_cq_tuser),
.s_axis_cq_tvalid(axis_cq_tvalid),
.m_axis_cc_tdata(axis_cc_tdata),
.m_axis_cc_tkeep(axis_cc_tkeep),
.m_axis_cc_tlast(axis_cc_tlast),
.m_axis_cc_tready(axis_cc_tready),
.m_axis_cc_tuser(axis_cc_tuser),
.m_axis_cc_tvalid(axis_cc_tvalid),
.s_axis_rq_seq_num_0(pcie_rq_seq_num0),
.s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0),
.s_axis_rq_seq_num_1(pcie_rq_seq_num1),
.s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module example_core_pcie #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 5,
// TX sequence number tracking enable
parameter TX_SEQ_NUM_ENABLE = 1,
// Immediate enable
parameter IMM_ENABLE = 1,
// Immediate width
parameter IMM_WIDTH = 32,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Operation table size (read)
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// Force 64 bit address
parameter TLP_FORCE_64_BIT_ADDR = 0,
// Requester ID mash
parameter CHECK_BUS_NUMBER = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24,
// BAR2 aperture (log2 size)
parameter BAR2_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* TLP input (completion)
*/
input wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
output wire rx_cpl_tlp_ready,
/*
* TLP output (read request)
*/
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
input wire tx_rd_req_tlp_ready,
/*
* TLP output (write request)
*/
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
input wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number input
*/
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_rd_req_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_rd_req_tx_seq_num_valid,
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_wr_req_tx_seq_num,
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_wr_req_tx_seq_num_valid,
/*
* Transmit flow control
*/
input wire [7:0] pcie_tx_fc_ph_av,
input wire [11:0] pcie_tx_fc_pd_av,
input wire [7:0] pcie_tx_fc_nph_av,
/*
* Configuration
*/
input wire [7:0] bus_num,
input wire ext_tag_enable,
input wire [2:0] max_read_request_size,
input wire [2:0] max_payload_size,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor,
/*
* MSI request outputs
*/
output wire [31:0] msi_irq
);
parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_ADDR_WIDTH = BAR0_APERTURE;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = BAR2_APERTURE;
parameter AXI_ID_WIDTH = 8;
parameter RAM_SEL_WIDTH = 2;
parameter RAM_ADDR_WIDTH = 16;
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
parameter RAM_SEG_DATA_WIDTH = TLP_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH);
parameter PCIE_ADDR_WIDTH = 64;
parameter DMA_LEN_WIDTH = 16;
parameter DMA_TAG_WIDTH = 8;
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
wire [2:0] axil_ctrl_awprot;
wire axil_ctrl_awvalid;
wire axil_ctrl_awready;
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
wire axil_ctrl_wvalid;
wire axil_ctrl_wready;
wire [1:0] axil_ctrl_bresp;
wire axil_ctrl_bvalid;
wire axil_ctrl_bready;
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
wire [2:0] axil_ctrl_arprot;
wire axil_ctrl_arvalid;
wire axil_ctrl_arready;
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
wire [1:0] axil_ctrl_rresp;
wire axil_ctrl_rvalid;
wire axil_ctrl_rready;
wire [PCIE_ADDR_WIDTH-1:0] axis_dma_read_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] axis_dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] axis_dma_read_desc_ram_addr;
wire [DMA_LEN_WIDTH-1:0] axis_dma_read_desc_len;
wire [DMA_TAG_WIDTH-1:0] axis_dma_read_desc_tag;
wire axis_dma_read_desc_valid;
wire axis_dma_read_desc_ready;
wire [DMA_TAG_WIDTH-1:0] axis_dma_read_desc_status_tag;
wire [3:0] axis_dma_read_desc_status_error;
wire axis_dma_read_desc_status_valid;
wire [PCIE_ADDR_WIDTH-1:0] axis_dma_write_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] axis_dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] axis_dma_write_desc_ram_addr;
wire [IMM_WIDTH-1:0] axis_dma_write_desc_imm;
wire axis_dma_write_desc_imm_en;
wire [DMA_LEN_WIDTH-1:0] axis_dma_write_desc_len;
wire [DMA_TAG_WIDTH-1:0] axis_dma_write_desc_tag;
wire axis_dma_write_desc_valid;
wire axis_dma_write_desc_ready;
wire [DMA_TAG_WIDTH-1:0] axis_dma_write_desc_status_tag;
wire [3:0] axis_dma_write_desc_status_error;
wire axis_dma_write_desc_status_valid;
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr;
wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid;
wire [RAM_SEG_COUNT-1:0] ram_rd_cmd_ready;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_rd_resp_data;
wire [RAM_SEG_COUNT-1:0] ram_rd_resp_valid;
wire [RAM_SEG_COUNT-1:0] ram_rd_resp_ready;
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready;
wire [RAM_SEG_COUNT-1:0] ram_wr_done;
wire [2:0] status_error_cor_int;
wire [2:0] status_error_uncor_int;
// PCIe connections
wire [TLP_DATA_WIDTH-1:0] ctrl_rx_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ctrl_rx_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ctrl_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ctrl_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ctrl_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_eop;
wire ctrl_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ctrl_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ctrl_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ctrl_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_eop;
wire ctrl_tx_cpl_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ram_rx_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ram_rx_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ram_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ram_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ram_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_eop;
wire ram_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ram_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ram_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ram_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_eop;
wire ram_tx_cpl_tlp_ready;
pcie_tlp_demux_bar #(
.PORTS(2),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.BAR_BASE(0),
.BAR_STRIDE(2),
.BAR_IDS(0)
)
pcie_tlp_demux_inst (
.clk(clk),
.rst(rst),
/*
* TLP input
*/
.in_tlp_data(rx_req_tlp_data),
.in_tlp_strb(rx_req_tlp_strb),
.in_tlp_hdr(rx_req_tlp_hdr),
.in_tlp_bar_id(rx_req_tlp_bar_id),
.in_tlp_func_num(rx_req_tlp_func_num),
.in_tlp_error(0),
.in_tlp_valid(rx_req_tlp_valid),
.in_tlp_sop(rx_req_tlp_sop),
.in_tlp_eop(rx_req_tlp_eop),
.in_tlp_ready(rx_req_tlp_ready),
/*
* TLP output
*/
.out_tlp_data( {ram_rx_req_tlp_data, ctrl_rx_req_tlp_data }),
.out_tlp_strb( {ram_rx_req_tlp_strb, ctrl_rx_req_tlp_strb }),
.out_tlp_hdr( {ram_rx_req_tlp_hdr, ctrl_rx_req_tlp_hdr }),
.out_tlp_bar_id( {ram_rx_req_tlp_bar_id, ctrl_rx_req_tlp_bar_id }),
.out_tlp_func_num({ram_rx_req_tlp_func_num, ctrl_rx_req_tlp_func_num}),
.out_tlp_error(),
.out_tlp_valid( {ram_rx_req_tlp_valid, ctrl_rx_req_tlp_valid }),
.out_tlp_sop( {ram_rx_req_tlp_sop, ctrl_rx_req_tlp_sop }),
.out_tlp_eop( {ram_rx_req_tlp_eop, ctrl_rx_req_tlp_eop }),
.out_tlp_ready( {ram_rx_req_tlp_ready, ctrl_rx_req_tlp_ready }),
/*
* Control
*/
.enable(1'b1)
);
pcie_tlp_mux #(
.PORTS(2),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_LSB_HIGH_PRIORITY(1)
)
pcie_tlp_mux_inst (
.clk(clk),
.rst(rst),
/*
* TLP input
*/
.in_tlp_data( {ram_tx_cpl_tlp_data, ctrl_tx_cpl_tlp_data }),
.in_tlp_strb( {ram_tx_cpl_tlp_strb, ctrl_tx_cpl_tlp_strb }),
.in_tlp_hdr( {ram_tx_cpl_tlp_hdr, ctrl_tx_cpl_tlp_hdr }),
.in_tlp_seq(0),
.in_tlp_bar_id(0),
.in_tlp_func_num(0),
.in_tlp_error(0),
.in_tlp_valid({ram_tx_cpl_tlp_valid, ctrl_tx_cpl_tlp_valid}),
.in_tlp_sop( {ram_tx_cpl_tlp_sop, ctrl_tx_cpl_tlp_sop }),
.in_tlp_eop( {ram_tx_cpl_tlp_eop, ctrl_tx_cpl_tlp_eop }),
.in_tlp_ready({ram_tx_cpl_tlp_ready, ctrl_tx_cpl_tlp_ready}),
/*
* TLP output
*/
.out_tlp_data(tx_cpl_tlp_data),
.out_tlp_strb(tx_cpl_tlp_strb),
.out_tlp_hdr(tx_cpl_tlp_hdr),
.out_tlp_seq(),
.out_tlp_bar_id(),
.out_tlp_func_num(),
.out_tlp_error(),
.out_tlp_valid(tx_cpl_tlp_valid),
.out_tlp_sop(tx_cpl_tlp_sop),
.out_tlp_eop(tx_cpl_tlp_eop),
.out_tlp_ready(tx_cpl_tlp_ready)
);
pcie_axil_master #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
)
pcie_axil_master_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(ctrl_rx_req_tlp_data),
.rx_req_tlp_hdr(ctrl_rx_req_tlp_hdr),
.rx_req_tlp_valid(ctrl_rx_req_tlp_valid),
.rx_req_tlp_sop(ctrl_rx_req_tlp_sop),
.rx_req_tlp_eop(ctrl_rx_req_tlp_eop),
.rx_req_tlp_ready(ctrl_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(ctrl_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(ctrl_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(ctrl_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(ctrl_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(ctrl_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(ctrl_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(ctrl_tx_cpl_tlp_ready),
/*
* AXI Lite Master output
*/
.m_axil_awaddr(axil_ctrl_awaddr),
.m_axil_awprot(axil_ctrl_awprot),
.m_axil_awvalid(axil_ctrl_awvalid),
.m_axil_awready(axil_ctrl_awready),
.m_axil_wdata(axil_ctrl_wdata),
.m_axil_wstrb(axil_ctrl_wstrb),
.m_axil_wvalid(axil_ctrl_wvalid),
.m_axil_wready(axil_ctrl_wready),
.m_axil_bresp(axil_ctrl_bresp),
.m_axil_bvalid(axil_ctrl_bvalid),
.m_axil_bready(axil_ctrl_bready),
.m_axil_araddr(axil_ctrl_araddr),
.m_axil_arprot(axil_ctrl_arprot),
.m_axil_arvalid(axil_ctrl_arvalid),
.m_axil_arready(axil_ctrl_arready),
.m_axil_rdata(axil_ctrl_rdata),
.m_axil_rresp(axil_ctrl_rresp),
.m_axil_rvalid(axil_ctrl_rvalid),
.m_axil_rready(axil_ctrl_rready),
/*
* Configuration
*/
.completer_id({bus_num, 5'd0, 3'd0}),
/*
* Status
*/
.status_error_cor(status_error_cor_int[0]),
.status_error_uncor(status_error_uncor_int[0])
);
wire [AXI_ID_WIDTH-1:0] axi_ram_awid;
wire [AXI_ADDR_WIDTH-1:0] axi_ram_awaddr;
wire [7:0] axi_ram_awlen;
wire [2:0] axi_ram_awsize;
wire [1:0] axi_ram_awburst;
wire axi_ram_awlock;
wire [3:0] axi_ram_awcache;
wire [2:0] axi_ram_awprot;
wire axi_ram_awvalid;
wire axi_ram_awready;
wire [AXI_DATA_WIDTH-1:0] axi_ram_wdata;
wire [AXI_STRB_WIDTH-1:0] axi_ram_wstrb;
wire axi_ram_wlast;
wire axi_ram_wvalid;
wire axi_ram_wready;
wire [AXI_ID_WIDTH-1:0] axi_ram_bid;
wire [1:0] axi_ram_bresp;
wire axi_ram_bvalid;
wire axi_ram_bready;
wire [AXI_ID_WIDTH-1:0] axi_ram_arid;
wire [AXI_ADDR_WIDTH-1:0] axi_ram_araddr;
wire [7:0] axi_ram_arlen;
wire [2:0] axi_ram_arsize;
wire [1:0] axi_ram_arburst;
wire axi_ram_arlock;
wire [3:0] axi_ram_arcache;
wire [2:0] axi_ram_arprot;
wire axi_ram_arvalid;
wire axi_ram_arready;
wire [AXI_ID_WIDTH-1:0] axi_ram_rid;
wire [AXI_DATA_WIDTH-1:0] axi_ram_rdata;
wire [1:0] axi_ram_rresp;
wire axi_ram_rlast;
wire axi_ram_rvalid;
wire axi_ram_rready;
pcie_axi_master #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(256),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
)
pcie_axi_master_isnt (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(ram_rx_req_tlp_data),
.rx_req_tlp_hdr(ram_rx_req_tlp_hdr),
.rx_req_tlp_valid(ram_rx_req_tlp_valid),
.rx_req_tlp_sop(ram_rx_req_tlp_sop),
.rx_req_tlp_eop(ram_rx_req_tlp_eop),
.rx_req_tlp_ready(ram_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(ram_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(ram_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(ram_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(ram_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(ram_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(ram_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(ram_tx_cpl_tlp_ready),
/*
* AXI Master output
*/
.m_axi_awid(axi_ram_awid),
.m_axi_awaddr(axi_ram_awaddr),
.m_axi_awlen(axi_ram_awlen),
.m_axi_awsize(axi_ram_awsize),
.m_axi_awburst(axi_ram_awburst),
.m_axi_awlock(axi_ram_awlock),
.m_axi_awcache(axi_ram_awcache),
.m_axi_awprot(axi_ram_awprot),
.m_axi_awvalid(axi_ram_awvalid),
.m_axi_awready(axi_ram_awready),
.m_axi_wdata(axi_ram_wdata),
.m_axi_wstrb(axi_ram_wstrb),
.m_axi_wlast(axi_ram_wlast),
.m_axi_wvalid(axi_ram_wvalid),
.m_axi_wready(axi_ram_wready),
.m_axi_bid(axi_ram_bid),
.m_axi_bresp(axi_ram_bresp),
.m_axi_bvalid(axi_ram_bvalid),
.m_axi_bready(axi_ram_bready),
.m_axi_arid(axi_ram_arid),
.m_axi_araddr(axi_ram_araddr),
.m_axi_arlen(axi_ram_arlen),
.m_axi_arsize(axi_ram_arsize),
.m_axi_arburst(axi_ram_arburst),
.m_axi_arlock(axi_ram_arlock),
.m_axi_arcache(axi_ram_arcache),
.m_axi_arprot(axi_ram_arprot),
.m_axi_arvalid(axi_ram_arvalid),
.m_axi_arready(axi_ram_arready),
.m_axi_rid(axi_ram_rid),
.m_axi_rdata(axi_ram_rdata),
.m_axi_rresp(axi_ram_rresp),
.m_axi_rlast(axi_ram_rlast),
.m_axi_rvalid(axi_ram_rvalid),
.m_axi_rready(axi_ram_rready),
/*
* Configuration
*/
.completer_id({bus_num, 5'd0, 3'd0}),
.max_payload_size(max_payload_size),
/*
* Status
*/
.status_error_cor(status_error_cor_int[1]),
.status_error_uncor(status_error_uncor_int[1])
);
axi_ram #(
.DATA_WIDTH(AXI_DATA_WIDTH),
.ADDR_WIDTH(AXI_ADDR_WIDTH < 16 ? AXI_ADDR_WIDTH : 16),
.ID_WIDTH(AXI_ID_WIDTH),
.PIPELINE_OUTPUT(1)
)
axi_ram_inst (
.clk(clk),
.rst(rst),
.s_axi_awid(axi_ram_awid),
.s_axi_awaddr(axi_ram_awaddr),
.s_axi_awlen(axi_ram_awlen),
.s_axi_awsize(axi_ram_awsize),
.s_axi_awburst(axi_ram_awburst),
.s_axi_awlock(axi_ram_awlock),
.s_axi_awcache(axi_ram_awcache),
.s_axi_awprot(axi_ram_awprot),
.s_axi_awvalid(axi_ram_awvalid),
.s_axi_awready(axi_ram_awready),
.s_axi_wdata(axi_ram_wdata),
.s_axi_wstrb(axi_ram_wstrb),
.s_axi_wlast(axi_ram_wlast),
.s_axi_wvalid(axi_ram_wvalid),
.s_axi_wready(axi_ram_wready),
.s_axi_bid(axi_ram_bid),
.s_axi_bresp(axi_ram_bresp),
.s_axi_bvalid(axi_ram_bvalid),
.s_axi_bready(axi_ram_bready),
.s_axi_arid(axi_ram_arid),
.s_axi_araddr(axi_ram_araddr),
.s_axi_arlen(axi_ram_arlen),
.s_axi_arsize(axi_ram_arsize),
.s_axi_arburst(axi_ram_arburst),
.s_axi_arlock(axi_ram_arlock),
.s_axi_arcache(axi_ram_arcache),
.s_axi_arprot(axi_ram_arprot),
.s_axi_arvalid(axi_ram_arvalid),
.s_axi_arready(axi_ram_arready),
.s_axi_rid(axi_ram_rid),
.s_axi_rdata(axi_ram_rdata),
.s_axi_rresp(axi_ram_rresp),
.s_axi_rlast(axi_ram_rlast),
.s_axi_rvalid(axi_ram_rvalid),
.s_axi_rready(axi_ram_rready)
);
dma_if_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.LEN_WIDTH(DMA_LEN_WIDTH),
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
.CHECK_BUS_NUMBER(CHECK_BUS_NUMBER)
)
dma_if_pcie_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (completion)
*/
.rx_cpl_tlp_data(rx_cpl_tlp_data),
.rx_cpl_tlp_hdr(rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(rx_cpl_tlp_error),
.rx_cpl_tlp_valid(rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(rx_cpl_tlp_ready),
/*
* TLP output (read request)
*/
.tx_rd_req_tlp_hdr(tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rd_req_tx_seq_num(s_axis_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(s_axis_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(s_axis_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(s_axis_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_pcie_addr(axis_dma_read_desc_dma_addr),
.s_axis_read_desc_ram_sel(axis_dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(axis_dma_read_desc_ram_addr),
.s_axis_read_desc_len(axis_dma_read_desc_len),
.s_axis_read_desc_tag(axis_dma_read_desc_tag),
.s_axis_read_desc_valid(axis_dma_read_desc_valid),
.s_axis_read_desc_ready(axis_dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(axis_dma_read_desc_status_tag),
.m_axis_read_desc_status_error(axis_dma_read_desc_status_error),
.m_axis_read_desc_status_valid(axis_dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_pcie_addr(axis_dma_write_desc_dma_addr),
.s_axis_write_desc_ram_sel(axis_dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(axis_dma_write_desc_ram_addr),
.s_axis_write_desc_imm(axis_dma_write_desc_imm),
.s_axis_write_desc_imm_en(axis_dma_write_desc_imm_en),
.s_axis_write_desc_len(axis_dma_write_desc_len),
.s_axis_write_desc_tag(axis_dma_write_desc_tag),
.s_axis_write_desc_valid(axis_dma_write_desc_valid),
.s_axis_write_desc_ready(axis_dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(axis_dma_write_desc_status_tag),
.m_axis_write_desc_status_error(axis_dma_write_desc_status_error),
.m_axis_write_desc_status_valid(axis_dma_write_desc_status_valid),
/*
* RAM interface
*/
.ram_rd_cmd_sel(ram_rd_cmd_sel),
.ram_rd_cmd_addr(ram_rd_cmd_addr),
.ram_rd_cmd_valid(ram_rd_cmd_valid),
.ram_rd_cmd_ready(ram_rd_cmd_ready),
.ram_rd_resp_data(ram_rd_resp_data),
.ram_rd_resp_valid(ram_rd_resp_valid),
.ram_rd_resp_ready(ram_rd_resp_ready),
.ram_wr_cmd_sel(ram_wr_cmd_sel),
.ram_wr_cmd_be(ram_wr_cmd_be),
.ram_wr_cmd_addr(ram_wr_cmd_addr),
.ram_wr_cmd_data(ram_wr_cmd_data),
.ram_wr_cmd_valid(ram_wr_cmd_valid),
.ram_wr_cmd_ready(ram_wr_cmd_ready),
.ram_wr_done(ram_wr_done),
/*
* Configuration
*/
.read_enable(1'b1),
.write_enable(1'b1),
.ext_tag_enable(ext_tag_enable),
.requester_id({bus_num, 5'd0, 3'd0}),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
/*
* Status
*/
.status_error_cor(status_error_cor_int[2]),
.status_error_uncor(status_error_uncor_int[2])
);
pulse_merge #(
.INPUT_WIDTH(3),
.COUNT_WIDTH(4)
)
status_error_cor_pm_inst (
.clk(clk),
.rst(rst),
.pulse_in(status_error_cor_int),
.count_out(),
.pulse_out(status_error_cor)
);
pulse_merge #(
.INPUT_WIDTH(3),
.COUNT_WIDTH(4)
)
status_error_uncor_pm_inst (
.clk(clk),
.rst(rst),
.pulse_in(status_error_uncor_int),
.count_out(),
.pulse_out(status_error_uncor)
);
example_core #(
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
.DMA_IMM_ENABLE(IMM_ENABLE),
.DMA_IMM_WIDTH(IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH)
)
core_inst (
.clk(clk),
.rst(rst),
/*
* AXI Lite control interface
*/
.s_axil_ctrl_awaddr(axil_ctrl_awaddr),
.s_axil_ctrl_awprot(axil_ctrl_awprot),
.s_axil_ctrl_awvalid(axil_ctrl_awvalid),
.s_axil_ctrl_awready(axil_ctrl_awready),
.s_axil_ctrl_wdata(axil_ctrl_wdata),
.s_axil_ctrl_wstrb(axil_ctrl_wstrb),
.s_axil_ctrl_wvalid(axil_ctrl_wvalid),
.s_axil_ctrl_wready(axil_ctrl_wready),
.s_axil_ctrl_bresp(axil_ctrl_bresp),
.s_axil_ctrl_bvalid(axil_ctrl_bvalid),
.s_axil_ctrl_bready(axil_ctrl_bready),
.s_axil_ctrl_araddr(axil_ctrl_araddr),
.s_axil_ctrl_arprot(axil_ctrl_arprot),
.s_axil_ctrl_arvalid(axil_ctrl_arvalid),
.s_axil_ctrl_arready(axil_ctrl_arready),
.s_axil_ctrl_rdata(axil_ctrl_rdata),
.s_axil_ctrl_rresp(axil_ctrl_rresp),
.s_axil_ctrl_rvalid(axil_ctrl_rvalid),
.s_axil_ctrl_rready(axil_ctrl_rready),
/*
* AXI read descriptor output
*/
.m_axis_dma_read_desc_dma_addr(axis_dma_read_desc_dma_addr),
.m_axis_dma_read_desc_ram_sel(axis_dma_read_desc_ram_sel),
.m_axis_dma_read_desc_ram_addr(axis_dma_read_desc_ram_addr),
.m_axis_dma_read_desc_len(axis_dma_read_desc_len),
.m_axis_dma_read_desc_tag(axis_dma_read_desc_tag),
.m_axis_dma_read_desc_valid(axis_dma_read_desc_valid),
.m_axis_dma_read_desc_ready(axis_dma_read_desc_ready),
/*
* AXI read descriptor status input
*/
.s_axis_dma_read_desc_status_tag(axis_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(axis_dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(axis_dma_read_desc_status_valid),
/*
* AXI write descriptor output
*/
.m_axis_dma_write_desc_dma_addr(axis_dma_write_desc_dma_addr),
.m_axis_dma_write_desc_ram_sel(axis_dma_write_desc_ram_sel),
.m_axis_dma_write_desc_ram_addr(axis_dma_write_desc_ram_addr),
.m_axis_dma_write_desc_imm(axis_dma_write_desc_imm),
.m_axis_dma_write_desc_imm_en(axis_dma_write_desc_imm_en),
.m_axis_dma_write_desc_len(axis_dma_write_desc_len),
.m_axis_dma_write_desc_tag(axis_dma_write_desc_tag),
.m_axis_dma_write_desc_valid(axis_dma_write_desc_valid),
.m_axis_dma_write_desc_ready(axis_dma_write_desc_ready),
/*
* AXI write descriptor status input
*/
.s_axis_dma_write_desc_status_tag(axis_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(axis_dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(axis_dma_write_desc_status_valid),
/*
* RAM interface
*/
.ram_rd_cmd_sel(ram_rd_cmd_sel),
.ram_rd_cmd_addr(ram_rd_cmd_addr),
.ram_rd_cmd_valid(ram_rd_cmd_valid),
.ram_rd_cmd_ready(ram_rd_cmd_ready),
.ram_rd_resp_data(ram_rd_resp_data),
.ram_rd_resp_valid(ram_rd_resp_valid),
.ram_rd_resp_ready(ram_rd_resp_ready),
.ram_wr_cmd_sel(ram_wr_cmd_sel),
.ram_wr_cmd_be(ram_wr_cmd_be),
.ram_wr_cmd_addr(ram_wr_cmd_addr),
.ram_wr_cmd_data(ram_wr_cmd_data),
.ram_wr_cmd_valid(ram_wr_cmd_valid),
.ram_wr_cmd_ready(ram_wr_cmd_ready),
.ram_wr_done(ram_wr_done),
/*
* MSI request outputs
*/
.msi_irq(msi_irq)
);
endmodule |
module example_core_pcie_us #
(
// Width of PCIe AXI stream interfaces in bits
parameter AXIS_PCIE_DATA_WIDTH = 256,
// PCIe AXI stream tkeep signal width (words per cycle)
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream RC tuser signal width
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
// PCIe AXI stream RQ tuser signal width
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
// PCIe AXI stream CQ tuser signal width
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
// PCIe AXI stream CC tuser signal width
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
// RQ sequence number width
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
// RQ sequence number tracking enable
parameter RQ_SEQ_NUM_ENABLE = 1,
// Immediate enable
parameter IMM_ENABLE = 1,
// Immediate width
parameter IMM_WIDTH = 32,
// PCIe tag count
parameter PCIE_TAG_COUNT = 256,
// Operation table size (read)
parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
// In-flight transmit limit (read)
parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (read)
parameter READ_TX_FC_ENABLE = 1,
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
// In-flight transmit limit (write)
parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
// Transmit flow control (write)
parameter WRITE_TX_FC_ENABLE = 1,
// BAR0 aperture (log2 size)
parameter BAR0_APERTURE = 24,
// BAR2 aperture (log2 size)
parameter BAR2_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* AXI input (RC)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tvalid,
output wire s_axis_rc_tready,
input wire s_axis_rc_tlast,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
/*
* AXI output (RQ)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tvalid,
input wire m_axis_rq_tready,
output wire m_axis_rq_tlast,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
/*
* AXI input (CQ)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tvalid,
output wire s_axis_cq_tready,
input wire s_axis_cq_tlast,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
/*
* AXI output (CC)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tvalid,
input wire m_axis_cc_tready,
output wire m_axis_cc_tlast,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
/*
* Transmit sequence number input
*/
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
/*
* Flow control
*/
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
/*
* Configuration interface
*/
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
/*
* Interrupt interface
*/
input wire [3:0] cfg_interrupt_msi_enable,
input wire [7:0] cfg_interrupt_msi_vf_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [7:0] cfg_interrupt_msi_function_number,
/*
* Configuration
*/
input wire [2:0] cfg_max_read_req,
input wire [2:0] cfg_max_payload,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32;
parameter TLP_HDR_WIDTH = 128;
parameter TLP_SEG_COUNT = 1;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
parameter TX_SEQ_NUM_ENABLE = RQ_SEQ_NUM_ENABLE;
parameter PF_COUNT = 1;
parameter VF_COUNT = 0;
parameter F_COUNT = PF_COUNT+VF_COUNT;
parameter MSI_COUNT = 32;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_rx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_rd_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_wr_req_tx_seq_num_valid;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
wire pcie_tx_cpl_tlp_ready;
wire [7:0] pcie_tx_fc_ph_av;
wire [11:0] pcie_tx_fc_pd_av;
wire [7:0] pcie_tx_fc_nph_av;
wire ext_tag_enable;
wire [MSI_COUNT-1:0] msi_irq;
pcie_us_if #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
.VF_COUNT(0),
.F_COUNT(PF_COUNT+VF_COUNT),
.READ_EXT_TAG_ENABLE(1),
.READ_MAX_READ_REQ_SIZE(1),
.READ_MAX_PAYLOAD_SIZE(1),
.MSIX_ENABLE(0),
.MSI_ENABLE(1),
.MSI_COUNT(MSI_COUNT)
)
pcie_us_if_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* TLP output (request to BAR)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion to DMA)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP input (read request from DMA)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* Transmit sequence number output (DMA read request)
*/
.m_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.m_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
/*
* TLP input (write request from DMA)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number output (DMA write request)
*/
.m_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.m_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* TLP input (completion from BAR)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* Flow control
*/
.tx_fc_ph_av(pcie_tx_fc_ph_av),
.tx_fc_pd_av(pcie_tx_fc_pd_av),
.tx_fc_nph_av(pcie_tx_fc_nph_av),
.tx_fc_npd_av(),
.tx_fc_cplh_av(),
.tx_fc_cpld_av(),
/*
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(),
.max_payload_size(),
/*
* MSI request inputs
*/
.msi_irq(msi_irq)
);
example_core_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
.IMM_ENABLE(IMM_ENABLE),
.IMM_WIDTH(IMM_WIDTH),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(READ_TX_LIMIT),
.READ_TX_FC_ENABLE(READ_TX_FC_ENABLE),
.WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(WRITE_TX_LIMIT),
.WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE),
.TLP_FORCE_64_BIT_ADDR(1),
.CHECK_BUS_NUMBER(0),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
core_pcie_inst (
.clk(clk),
.rst(rst),
/*
* TLP input (request)
*/
.rx_req_tlp_data(pcie_rx_req_tlp_data),
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
/*
* TLP output (completion)
*/
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
/*
* TLP input (completion)
*/
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
/*
* TLP output (read request)
*/
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
/*
* TLP output (write request)
*/
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
/*
* Transmit sequence number input
*/
.s_axis_rd_req_tx_seq_num(axis_pcie_rd_req_tx_seq_num),
.s_axis_rd_req_tx_seq_num_valid(axis_pcie_rd_req_tx_seq_num_valid),
.s_axis_wr_req_tx_seq_num(axis_pcie_wr_req_tx_seq_num),
.s_axis_wr_req_tx_seq_num_valid(axis_pcie_wr_req_tx_seq_num_valid),
/*
* Transmit flow control
*/
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
/*
* Configuration
*/
.bus_num(8'd0),
.ext_tag_enable(ext_tag_enable),
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor),
/*
* MSI request outputs
*/
.msi_irq(msi_irq)
);
endmodule |
module fpga_core #
(
parameter SEG_COUNT = 1,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PCIE_TAG_COUNT = 256,
parameter BAR0_APERTURE = 24,
parameter BAR2_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] led_user_grn,
output wire [1:0] led_user_red,
output wire [3:0] led_qsfp,
/*
* H-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
input wire [7:0] tx_ph_cdts,
input wire [11:0] tx_pd_cdts,
input wire [7:0] tx_nph_cdts,
input wire [11:0] tx_npd_cdts,
input wire [7:0] tx_cplh_cdts,
input wire [11:0] tx_cpld_cdts,
input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
input wire [31:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [1:0] tl_cfg_func
);
assign led_user_grn = 0;
assign led_user_red = 0;
assign led_qsfp = 0;
example_core_pcie_s10 #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.L_TILE(0),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.READ_TX_FC_ENABLE(1),
.WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE),
.BAR2_APERTURE(BAR2_APERTURE)
)
example_core_pcie_s10_inst (
.clk(clk),
.rst(rst),
/*
* H-tile RX AVST interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
/*
* H-tile TX AVST interface
*/
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
/*
* H-tile TX flow control
*/
.tx_ph_cdts(tx_ph_cdts),
.tx_pd_cdts(tx_pd_cdts),
.tx_nph_cdts(tx_nph_cdts),
.tx_npd_cdts(tx_npd_cdts),
.tx_cplh_cdts(tx_cplh_cdts),
.tx_cpld_cdts(tx_cpld_cdts),
.tx_hdr_cdts_consumed(tx_hdr_cdts_consumed),
.tx_data_cdts_consumed(tx_data_cdts_consumed),
.tx_cdts_type(tx_cdts_type),
.tx_cdts_data_value(tx_cdts_data_value),
/*
* H-tile MSI interrupt interface
*/
.app_msi_req(app_msi_req),
.app_msi_ack(app_msi_ack),
.app_msi_tc(app_msi_tc),
.app_msi_num(app_msi_num),
.app_msi_func_num(app_msi_func_num),
/*
* H-tile configuration interface
*/
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func)
);
endmodule |
module eth_mac_1g_rgmii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-6, 7-series
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
parameter CLOCK_INPUT_STYLE = "BUFG",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
wire [1:0] speed_int;
reg [1:0] speed_sync_reg_1 = 2'b10;
reg [1:0] speed_sync_reg_2 = 2'b10;
assign speed = speed_sync_reg_2;
always @(posedge logic_clk) begin
speed_sync_reg_1 <= speed_int;
speed_sync_reg_2 <= speed_sync_reg_1;
end
eth_mac_1g_rgmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_rgmii_inst (
.gtx_clk(gtx_clk),
.gtx_clk90(gtx_clk90),
.gtx_rst(gtx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.rgmii_rx_clk(rgmii_rx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.speed(speed_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule |
module eth_mac_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(TX_PTP_TAG_ENABLE),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(tx_axis_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(m_axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
end else begin
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
endgenerate
eth_mac_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
eth_mac_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule |
module eth_mac_phy_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
wire rx_bad_block_int;
wire rx_block_lock_int;
wire rx_high_ber_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;
reg [4:0] rx_sync_reg_3 = 5'd0;
reg [4:0] rx_sync_reg_4 = 5'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
assign rx_block_lock = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
assign rx_high_ber = rx_sync_reg_3[4] ^ rx_sync_reg_4[4];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 5'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 5'd0;
rx_sync_reg_3 <= 5'd0;
rx_sync_reg_4 <= 5'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(TX_PTP_TAG_ENABLE),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(tx_axis_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(m_axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
end else begin
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
endgenerate
eth_mac_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule |
module eth_mac_1g_rgmii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-6, 7-series
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
parameter CLOCK_INPUT_STYLE = "BUFG",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
/*
* Status
*/
output wire tx_error_underflow,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] mac_gmii_rxd;
wire mac_gmii_rx_dv;
wire mac_gmii_rx_er;
wire mac_gmii_tx_clk_en;
wire [7:0] mac_gmii_txd;
wire mac_gmii_tx_en;
wire mac_gmii_tx_er;
reg [1:0] speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
(* srl_style = "register" *)
reg [1:0] tx_mii_select_sync = 2'd0;
always @(posedge tx_clk) begin
tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
end
(* srl_style = "register" *)
reg [1:0] rx_mii_select_sync = 2'd0;
always @(posedge rx_clk) begin
rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
end
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
always @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
end
(* srl_style = "register" *)
reg [2:0] rx_prescale_sync = 3'd0;
always @(posedge gtx_clk) begin
rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
end
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
always @(posedge gtx_clk) begin
if (gtx_rst) begin
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end else begin
rx_speed_count_1 <= rx_speed_count_1 + 1;
if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
rx_speed_count_2 <= rx_speed_count_2 + 1;
end
if (&rx_speed_count_1) begin
// reference count overflow - 10M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b00;
mii_select_reg <= 1'b1;
end
if (&rx_speed_count_2) begin
// prescaled count overflow - 100M or 1000M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
if (rx_speed_count_1[6:5]) begin
// large reference count - 100M
speed_reg <= 2'b01;
mii_select_reg <= 1'b1;
end else begin
// small reference count - 1000M
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end
end
end
end
assign speed = speed_reg;
rgmii_phy_if #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90)
)
rgmii_phy_if_inst (
.clk(gtx_clk),
.clk90(gtx_clk90),
.rst(gtx_rst),
.mac_gmii_rx_clk(rx_clk),
.mac_gmii_rx_rst(rx_rst),
.mac_gmii_rxd(mac_gmii_rxd),
.mac_gmii_rx_dv(mac_gmii_rx_dv),
.mac_gmii_rx_er(mac_gmii_rx_er),
.mac_gmii_tx_clk(tx_clk),
.mac_gmii_tx_rst(tx_rst),
.mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
.mac_gmii_txd(mac_gmii_txd),
.mac_gmii_tx_en(mac_gmii_tx_en),
.mac_gmii_tx_er(mac_gmii_tx_er),
.phy_rgmii_rx_clk(rgmii_rx_clk),
.phy_rgmii_rxd(rgmii_rxd),
.phy_rgmii_rx_ctl(rgmii_rx_ctl),
.phy_rgmii_tx_clk(rgmii_tx_clk),
.phy_rgmii_txd(rgmii_txd),
.phy_rgmii_tx_ctl(rgmii_tx_ctl),
.speed(speed)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_gmii_rxd),
.gmii_rx_dv(mac_gmii_rx_dv),
.gmii_rx_er(mac_gmii_rx_er),
.gmii_txd(mac_gmii_txd),
.gmii_tx_en(mac_gmii_tx_en),
.gmii_tx_er(mac_gmii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(mac_gmii_tx_clk_en),
.rx_mii_select(rx_mii_select_sync[1]),
.tx_mii_select(tx_mii_select_sync[1]),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule |
module eth_mac_mii_fifo #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
parameter AXIS_DATA_WIDTH = 8,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
)
(
input wire rst,
input wire logic_clk,
input wire logic_rst,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* MII interface
*/
input wire mii_rx_clk,
input wire [3:0] mii_rxd,
input wire mii_rx_dv,
input wire mii_rx_er,
input wire mii_tx_clk,
output wire [3:0] mii_txd,
output wire mii_tx_en,
output wire mii_tx_er,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire tx_clk;
wire rx_clk;
wire tx_rst;
wire rx_rst;
wire [7:0] tx_fifo_axis_tdata;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire tx_fifo_axis_tuser;
wire [7:0] rx_fifo_axis_tdata;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire rx_fifo_axis_tuser;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
reg [1:0] rx_sync_reg_1 = 2'd0;
reg [1:0] rx_sync_reg_2 = 2'd0;
reg [1:0] rx_sync_reg_3 = 2'd0;
reg [1:0] rx_sync_reg_4 = 2'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 2'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 2'd0;
rx_sync_reg_3 <= 2'd0;
rx_sync_reg_4 <= 2'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
eth_mac_mii #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_mii_inst (
.rst(rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.mii_rx_clk(mii_rx_clk),
.mii_rxd(mii_rxd),
.mii_rx_dv(mii_rx_dv),
.mii_rx_er(mii_rx_er),
.mii_tx_clk(mii_tx_clk),
.mii_txd(mii_txd),
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.ifg_delay(ifg_delay)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(8),
.M_KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(8),
.S_KEEP_ENABLE(0),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule |
module axis_async_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0
)
(
/*
* AXI input
*/
input wire s_clk,
input wire s_rst,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
input wire m_clk,
input wire m_rst,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire s_status_overflow,
output wire s_status_bad_frame,
output wire s_status_good_frame,
output wire m_status_overflow,
output wire m_status_bad_frame,
output wire m_status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
// check configuration
initial begin
if (PIPELINE_OUTPUT < 1) begin
$error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)");
$finish;
end
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_temp;
reg [ADDR_WIDTH:0] rd_ptr_temp;
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
(* SHREG_EXTRACT = "NO" *)
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
reg wr_ptr_update_valid_reg = 1'b0;
reg wr_ptr_update_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync2_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_sync3_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_ack_sync1_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg wr_ptr_update_ack_sync2_reg = 1'b0;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync1_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync2_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg s_rst_sync3_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync1_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync2_reg = 1'b1;
(* SHREG_EXTRACT = "NO" *)
reg m_rst_sync3_reg = 1'b1;
(* ramstyle = "no_rw_check" *)
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0;
wire [WIDTH-1:0] s_axis;
reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0];
reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0;
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = wr_ptr_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}});
wire full_cur = wr_ptr_cur_gray_reg == (rd_ptr_gray_sync2_reg ^ {2'b11, {ADDR_WIDTH-1{1'b0}}});
// empty when pointers match exactly
wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg);
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// control signals
reg write;
reg read;
reg store_output;
reg s_frame_reg = 1'b0;
reg m_frame_reg = 1'b0;
reg drop_frame_reg = 1'b0;
reg send_frame_reg = 1'b0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
reg m_drop_frame_reg = 1'b0;
reg m_terminate_frame_reg = 1'b0;
reg overflow_sync1_reg = 1'b0;
reg overflow_sync2_reg = 1'b0;
reg overflow_sync3_reg = 1'b0;
reg overflow_sync4_reg = 1'b0;
reg bad_frame_sync1_reg = 1'b0;
reg bad_frame_sync2_reg = 1'b0;
reg bad_frame_sync3_reg = 1'b0;
reg bad_frame_sync4_reg = 1'b0;
reg good_frame_sync1_reg = 1'b0;
reg good_frame_sync2_reg = 1'b0;
reg good_frame_sync3_reg = 1'b0;
reg good_frame_sync4_reg = 1'b0;
assign s_axis_tready = (FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
endgenerate
wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1];
wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis_pipe_reg[PIPELINE_OUTPUT-1][DATA_WIDTH-1:0];
wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][LAST_OFFSET] : 1'b1;
wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign m_axis_tvalid = m_axis_tvalid_pipe;
assign m_axis_tdata = m_axis_tdata_pipe;
assign m_axis_tkeep = m_axis_tkeep_pipe;
assign m_axis_tlast = (m_terminate_frame_reg ? 1'b1 : m_axis_tlast_pipe);
assign m_axis_tid = m_axis_tid_pipe;
assign m_axis_tdest = m_axis_tdest_pipe;
assign m_axis_tuser = (m_terminate_frame_reg ? USER_BAD_FRAME_VALUE : m_axis_tuser_pipe);
assign s_status_overflow = overflow_reg;
assign s_status_bad_frame = bad_frame_reg;
assign s_status_good_frame = good_frame_reg;
assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg;
assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg;
assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg;
// reset synchronization
always @(posedge m_clk or posedge m_rst) begin
if (m_rst) begin
s_rst_sync1_reg <= 1'b1;
end else begin
s_rst_sync1_reg <= 1'b0;
end
end
always @(posedge s_clk) begin
s_rst_sync2_reg <= s_rst_sync1_reg;
s_rst_sync3_reg <= s_rst_sync2_reg;
end
always @(posedge s_clk or posedge s_rst) begin
if (s_rst) begin
m_rst_sync1_reg <= 1'b1;
end else begin
m_rst_sync1_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
m_rst_sync2_reg <= m_rst_sync1_reg;
m_rst_sync3_reg <= m_rst_sync2_reg;
end
// Write logic
always @(posedge s_clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (FRAME_FIFO && wr_ptr_update_valid_reg) begin
// have updated pointer to sync
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_gray_reg <= wr_ptr_gray_reg;
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end
end
if (s_axis_tready && s_axis_tvalid && LAST_ENABLE) begin
// track input frame status
s_frame_reg <= !s_axis_tlast;
end
if (s_rst_sync3_reg && LAST_ENABLE) begin
// if sink side is reset during transfer, drop partial frame
if (s_frame_reg && !(s_axis_tready && s_axis_tvalid && s_axis_tlast)) begin
drop_frame_reg <= 1'b1;
end
if (s_axis_tready && s_axis_tvalid && !s_axis_tlast) begin
drop_frame_reg <= 1'b1;
end
end
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
if (drop_frame_reg && LAST_ENABLE) begin
// currently dropping frame
// (only for frame transfers interrupted by sink reset)
if (s_axis_tlast) begin
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
end
end else begin
// update pointers
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
end
end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_temp = wr_ptr_reg;
wr_ptr_cur_reg <= wr_ptr_temp;
wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_temp = wr_ptr_cur_reg + 1;
wr_ptr_cur_reg <= wr_ptr_temp;
wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis_tlast;
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_temp = wr_ptr_reg;
wr_ptr_cur_reg <= wr_ptr_temp;
wr_ptr_cur_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_temp = wr_ptr_cur_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
good_frame_reg <= s_axis_tlast;
end
end
end
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_temp = wr_ptr_cur_reg;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
if (wr_ptr_update_reg == wr_ptr_update_ack_sync2_reg) begin
// no sync in progress; sync update
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_sync_gray_reg <= wr_ptr_temp ^ (wr_ptr_temp >> 1);
wr_ptr_update_reg <= !wr_ptr_update_ack_sync2_reg;
end else begin
// sync in progress; flag it for later
wr_ptr_update_valid_reg <= 1'b1;
end
end
if (s_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
end
if (s_rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_valid_reg <= 1'b0;
wr_ptr_update_reg <= 1'b0;
s_frame_reg <= 1'b0;
drop_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// pointer synchronization
always @(posedge s_clk) begin
rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg;
wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg;
if (s_rst) begin
rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_ack_sync1_reg <= 1'b0;
wr_ptr_update_ack_sync2_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
if (!FRAME_FIFO) begin
wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin
wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg;
end
wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
wr_ptr_update_sync1_reg <= wr_ptr_update_reg;
wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg;
wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg;
if (FRAME_FIFO && m_rst_sync3_reg) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
end
if (m_rst) begin
wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_update_sync1_reg <= 1'b0;
wr_ptr_update_sync2_reg <= 1'b0;
wr_ptr_update_sync3_reg <= 1'b0;
end
end
// status synchronization
always @(posedge s_clk) begin
overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg;
bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg;
good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg;
if (s_rst) begin
overflow_sync1_reg <= 1'b0;
bad_frame_sync1_reg <= 1'b0;
good_frame_sync1_reg <= 1'b0;
end
end
always @(posedge m_clk) begin
overflow_sync2_reg <= overflow_sync1_reg;
overflow_sync3_reg <= overflow_sync2_reg;
overflow_sync4_reg <= overflow_sync3_reg;
bad_frame_sync2_reg <= bad_frame_sync1_reg;
bad_frame_sync3_reg <= bad_frame_sync2_reg;
bad_frame_sync4_reg <= bad_frame_sync3_reg;
good_frame_sync2_reg <= good_frame_sync1_reg;
good_frame_sync3_reg <= good_frame_sync2_reg;
good_frame_sync4_reg <= good_frame_sync3_reg;
if (m_rst) begin
overflow_sync2_reg <= 1'b0;
overflow_sync3_reg <= 1'b0;
overflow_sync4_reg <= 1'b0;
bad_frame_sync2_reg <= 1'b0;
bad_frame_sync3_reg <= 1'b0;
bad_frame_sync4_reg <= 1'b0;
good_frame_sync2_reg <= 1'b0;
good_frame_sync3_reg <= 1'b0;
good_frame_sync4_reg <= 1'b0;
end
end
// Read logic
integer j;
always @(posedge m_clk) begin
if (m_axis_tready) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin
if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty && !m_rst_sync3_reg && !m_drop_frame_reg) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_temp = rd_ptr_reg + 1;
rd_ptr_reg <= rd_ptr_temp;
rd_ptr_gray_reg <= rd_ptr_temp ^ (rd_ptr_temp >> 1);
end
end
if (m_axis_tvalid && LAST_ENABLE) begin
// track output frame status
if (m_axis_tlast && m_axis_tready) begin
m_frame_reg <= 1'b0;
end else begin
m_frame_reg <= 1'b1;
end
end
if (m_drop_frame_reg && (m_axis_tready || !m_axis_tvalid_pipe) && LAST_ENABLE) begin
// terminate frame
// (only for frame transfers interrupted by source reset)
m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b1;
m_terminate_frame_reg <= 1'b1;
m_drop_frame_reg <= 1'b0;
end
if (m_rst_sync3_reg && LAST_ENABLE) begin
// if source side is reset during transfer, drop partial frame
// empty output pipeline, except for last stage
if (PIPELINE_OUTPUT > 1) begin
m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-2:0] <= 0;
end
if (m_frame_reg && (!m_axis_tvalid || (m_axis_tvalid && !m_axis_tlast)) &&
!(m_drop_frame_reg || m_terminate_frame_reg)) begin
// terminate frame
m_drop_frame_reg <= 1'b1;
end
end
if (m_rst_sync3_reg) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
end
if (m_rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}};
m_frame_reg <= 1'b0;
m_drop_frame_reg <= 1'b0;
m_terminate_frame_reg <= 1'b0;
end
end
endmodule |
module fpga (
/*
* Reset: Push button, active low
*/
input wire reset,
/*
* GPIO
*/
output wire hbm_cattrip,
/*
* Ethernet: QSFP28
*/
output wire qsfp0_tx1_p,
output wire qsfp0_tx1_n,
input wire qsfp0_rx1_p,
input wire qsfp0_rx1_n,
output wire qsfp0_tx2_p,
output wire qsfp0_tx2_n,
input wire qsfp0_rx2_p,
input wire qsfp0_rx2_n,
output wire qsfp0_tx3_p,
output wire qsfp0_tx3_n,
input wire qsfp0_rx3_p,
input wire qsfp0_rx3_n,
output wire qsfp0_tx4_p,
output wire qsfp0_tx4_n,
input wire qsfp0_rx4_p,
input wire qsfp0_rx4_n,
// input wire qsfp0_mgt_refclk_0_p,
// input wire qsfp0_mgt_refclk_0_n,
input wire qsfp0_mgt_refclk_1_p,
input wire qsfp0_mgt_refclk_1_n,
output wire qsfp0_refclk_oe_b,
output wire qsfp0_refclk_fs,
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
// input wire qsfp1_mgt_refclk_0_p,
// input wire qsfp1_mgt_refclk_0_n,
input wire qsfp1_mgt_refclk_1_p,
input wire qsfp1_mgt_refclk_1_n,
output wire qsfp1_refclk_oe_b,
output wire qsfp1_refclk_fs
);
// Clock and reset
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = ~reset;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
assign hbm_cattrip = 1'b0;
// XGMII 10G PHY
// QSFP0
assign qsfp0_refclk_oe_b = 1'b0;
assign qsfp0_refclk_fs = 1'b1;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign clk_156mhz_int = qsfp0_tx_clk_1_int;
assign rst_156mhz_int = qsfp0_tx_rst_1_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp0_gtpowergood;
wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp0_mgt_refclk_1),
.ODIV2 (qsfp0_mgt_refclk_1_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (qsfp0_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp0_mgt_refclk_1_int),
.O (qsfp0_mgt_refclk_1_bufg)
);
wire qsfp0_qpll0lock;
wire qsfp0_qpll0outclk;
wire qsfp0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp0_tx1_p),
.xcvr_txn(qsfp0_tx1_n),
.xcvr_rxp(qsfp0_rx1_p),
.xcvr_rxn(qsfp0_rx1_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_1_int),
.phy_tx_rst(qsfp0_tx_rst_1_int),
.phy_xgmii_txd(qsfp0_txd_1_int),
.phy_xgmii_txc(qsfp0_txc_1_int),
.phy_rx_clk(qsfp0_rx_clk_1_int),
.phy_rx_rst(qsfp0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp0_rxd_1_int),
.phy_xgmii_rxc(qsfp0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx2_p),
.xcvr_txn(qsfp0_tx2_n),
.xcvr_rxp(qsfp0_rx2_p),
.xcvr_rxn(qsfp0_rx2_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_2_int),
.phy_tx_rst(qsfp0_tx_rst_2_int),
.phy_xgmii_txd(qsfp0_txd_2_int),
.phy_xgmii_txc(qsfp0_txc_2_int),
.phy_rx_clk(qsfp0_rx_clk_2_int),
.phy_rx_rst(qsfp0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp0_rxd_2_int),
.phy_xgmii_rxc(qsfp0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx3_p),
.xcvr_txn(qsfp0_tx3_n),
.xcvr_rxp(qsfp0_rx3_p),
.xcvr_rxn(qsfp0_rx3_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_3_int),
.phy_tx_rst(qsfp0_tx_rst_3_int),
.phy_xgmii_txd(qsfp0_txd_3_int),
.phy_xgmii_txc(qsfp0_txc_3_int),
.phy_rx_clk(qsfp0_rx_clk_3_int),
.phy_rx_rst(qsfp0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp0_rxd_3_int),
.phy_xgmii_rxc(qsfp0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx4_p),
.xcvr_txn(qsfp0_tx4_n),
.xcvr_rxp(qsfp0_rx4_p),
.xcvr_rxn(qsfp0_rx4_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_4_int),
.phy_tx_rst(qsfp0_tx_rst_4_int),
.phy_xgmii_txd(qsfp0_txd_4_int),
.phy_xgmii_txc(qsfp0_txc_4_int),
.phy_rx_clk(qsfp0_rx_clk_4_int),
.phy_rx_rst(qsfp0_rx_rst_4_int),
.phy_xgmii_rxd(qsfp0_rxd_4_int),
.phy_xgmii_rxc(qsfp0_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// QSFP1
assign qsfp1_refclk_oe_b = 1'b0;
assign qsfp1_refclk_fs = 1'b1;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire qsfp1_mgt_refclk_1;
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst (
.I (qsfp1_mgt_refclk_1_p),
.IB (qsfp1_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp1_mgt_refclk_1),
.ODIV2 ()
);
wire qsfp1_qpll0lock;
wire qsfp1_qpll0outclk;
wire qsfp1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp1_tx1_p),
.xcvr_txn(qsfp1_tx1_n),
.xcvr_rxp(qsfp1_rx1_p),
.xcvr_rxn(qsfp1_rx1_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_1_int),
.phy_tx_rst(qsfp1_tx_rst_1_int),
.phy_xgmii_txd(qsfp1_txd_1_int),
.phy_xgmii_txc(qsfp1_txc_1_int),
.phy_rx_clk(qsfp1_rx_clk_1_int),
.phy_rx_rst(qsfp1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp1_rxd_1_int),
.phy_xgmii_rxc(qsfp1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx2_p),
.xcvr_txn(qsfp1_tx2_n),
.xcvr_rxp(qsfp1_rx2_p),
.xcvr_rxn(qsfp1_rx2_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_2_int),
.phy_tx_rst(qsfp1_tx_rst_2_int),
.phy_xgmii_txd(qsfp1_txd_2_int),
.phy_xgmii_txc(qsfp1_txc_2_int),
.phy_rx_clk(qsfp1_rx_clk_2_int),
.phy_rx_rst(qsfp1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp1_rxd_2_int),
.phy_xgmii_rxc(qsfp1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx3_p),
.xcvr_txn(qsfp1_tx3_n),
.xcvr_rxp(qsfp1_rx3_p),
.xcvr_rxn(qsfp1_rx3_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_3_int),
.phy_tx_rst(qsfp1_tx_rst_3_int),
.phy_xgmii_txd(qsfp1_txd_3_int),
.phy_xgmii_txc(qsfp1_txc_3_int),
.phy_rx_clk(qsfp1_rx_clk_3_int),
.phy_rx_rst(qsfp1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp1_rxd_3_int),
.phy_xgmii_rxc(qsfp1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx4_p),
.xcvr_txn(qsfp1_tx4_n),
.xcvr_rxp(qsfp1_rx4_p),
.xcvr_rxn(qsfp1_rx4_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_4_int),
.phy_tx_rst(qsfp1_tx_rst_4_int),
.phy_xgmii_txd(qsfp1_txd_4_int),
.phy_xgmii_txc(qsfp1_txc_4_int),
.phy_rx_clk(qsfp1_rx_clk_4_int),
.phy_rx_rst(qsfp1_rx_rst_4_int),
.phy_xgmii_rxd(qsfp1_rxd_4_int),
.phy_xgmii_rxc(qsfp1_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int)
);
endmodule |
module fpga (
/*
* Clock: 100MHz LVDS
*/
input wire clk_100mhz_p,
input wire clk_100mhz_n,
/*
* GPIO
*/
output wire [1:0] sfp_1_led,
output wire [1:0] sfp_2_led,
output wire [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire sfp_1_rx_p,
input wire sfp_1_rx_n,
output wire sfp_1_tx_p,
output wire sfp_1_tx_n,
input wire sfp_2_rx_p,
input wire sfp_2_rx_n,
output wire sfp_2_tx_p,
output wire sfp_2_tx_n,
input wire sfp_mgt_refclk_p,
input wire sfp_mgt_refclk_n,
output wire sfp_1_tx_disable,
output wire sfp_2_tx_disable,
input wire sfp_1_npres,
input wire sfp_2_npres,
input wire sfp_1_los,
input wire sfp_2_los,
output wire sfp_1_rs,
output wire sfp_2_rs
);
// Clock and reset
wire clk_100mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_100mhz_ibufg_inst (
.O (clk_100mhz_ibufg),
.I (clk_100mhz_p),
.IB (clk_100mhz_n)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_100mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [1:0] sfp_1_led_int;
wire [1:0] sfp_2_led_int;
wire [1:0] sma_led_int;
// XGMII 10G PHY
assign sfp_1_tx_disable = 1'b0;
assign sfp_2_tx_disable = 1'b0;
assign sfp_1_rs = 1'b1;
assign sfp_2_rs = 1'b1;
wire sfp_1_tx_clk_int;
wire sfp_1_tx_rst_int;
wire [63:0] sfp_1_txd_int;
wire [7:0] sfp_1_txc_int;
wire sfp_1_rx_clk_int;
wire sfp_1_rx_rst_int;
wire [63:0] sfp_1_rxd_int;
wire [7:0] sfp_1_rxc_int;
wire sfp_2_tx_clk_int;
wire sfp_2_tx_rst_int;
wire [63:0] sfp_2_txd_int;
wire [7:0] sfp_2_txc_int;
wire sfp_2_rx_clk_int;
wire sfp_2_rx_rst_int;
wire [63:0] sfp_2_rxd_int;
wire [7:0] sfp_2_rxc_int;
assign clk_156mhz_int = sfp_1_tx_clk_int;
assign rst_156mhz_int = sfp_1_tx_rst_int;
wire sfp_1_rx_block_lock;
wire sfp_2_rx_block_lock;
wire sfp_mgt_refclk;
IBUFDS_GTE3 ibufds_gte3_sfp_mgt_refclk_inst (
.I (sfp_mgt_refclk_p),
.IB (sfp_mgt_refclk_n),
.CEB (1'b0),
.O (sfp_mgt_refclk),
.ODIV2 ()
);
wire sfp_qpll0lock;
wire sfp_qpll0outclk;
wire sfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
sfp_1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(sfp_mgt_refclk),
.xcvr_qpll0lock_out(sfp_qpll0lock),
.xcvr_qpll0outclk_out(sfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(sfp_1_tx_p),
.xcvr_txn(sfp_1_tx_n),
.xcvr_rxp(sfp_1_rx_p),
.xcvr_rxn(sfp_1_rx_n),
// PHY connections
.phy_tx_clk(sfp_1_tx_clk_int),
.phy_tx_rst(sfp_1_tx_rst_int),
.phy_xgmii_txd(sfp_1_txd_int),
.phy_xgmii_txc(sfp_1_txc_int),
.phy_rx_clk(sfp_1_rx_clk_int),
.phy_rx_rst(sfp_1_rx_rst_int),
.phy_xgmii_rxd(sfp_1_rxd_int),
.phy_xgmii_rxc(sfp_1_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp_2_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp_2_tx_p),
.xcvr_txn(sfp_2_tx_n),
.xcvr_rxp(sfp_2_rx_p),
.xcvr_rxn(sfp_2_rx_n),
// PHY connections
.phy_tx_clk(sfp_2_tx_clk_int),
.phy_tx_rst(sfp_2_tx_rst_int),
.phy_xgmii_txd(sfp_2_txd_int),
.phy_xgmii_txc(sfp_2_txc_int),
.phy_rx_clk(sfp_2_rx_clk_int),
.phy_rx_rst(sfp_2_rx_rst_int),
.phy_xgmii_rxd(sfp_2_rxd_int),
.phy_xgmii_rxc(sfp_2_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
assign sfp_1_led[0] = sfp_1_rx_block_lock;
assign sfp_1_led[1] = 1'b0;
assign sfp_2_led[0] = sfp_2_rx_block_lock;
assign sfp_2_led[1] = 1'b0;
assign sma_led = sma_led_int;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sfp_1_led(sfp_1_led_int),
.sfp_2_led(sfp_2_led_int),
.sma_led(sma_led_int),
/*
* Ethernet: SFP+
*/
.sfp_1_tx_clk(sfp_1_tx_clk_int),
.sfp_1_tx_rst(sfp_1_tx_rst_int),
.sfp_1_txd(sfp_1_txd_int),
.sfp_1_txc(sfp_1_txc_int),
.sfp_1_rx_clk(sfp_1_rx_clk_int),
.sfp_1_rx_rst(sfp_1_rx_rst_int),
.sfp_1_rxd(sfp_1_rxd_int),
.sfp_1_rxc(sfp_1_rxc_int),
.sfp_2_tx_clk(sfp_2_tx_clk_int),
.sfp_2_tx_rst(sfp_2_tx_rst_int),
.sfp_2_txd(sfp_2_txd_int),
.sfp_2_txc(sfp_2_txc_int),
.sfp_2_rx_clk(sfp_2_rx_clk_int),
.sfp_2_rx_rst(sfp_2_rx_rst_int),
.sfp_2_rxd(sfp_2_rxd_int),
.sfp_2_rxc(sfp_2_rxc_int)
);
endmodule |
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_rx_p,
input wire sfp0_rx_n,
output wire sfp0_tx_p,
output wire sfp0_tx_n,
input wire sfp1_rx_p,
input wire sfp1_rx_n,
output wire sfp1_tx_p,
output wire sfp1_tx_n,
input wire sfp_mgt_refclk_0_p,
input wire sfp_mgt_refclk_0_n,
output wire sfp0_tx_disable_b,
output wire sfp1_tx_disable_b
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(8),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_rts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// XGMII 10G PHY
assign sfp0_tx_disable_b = 1'b1;
assign sfp1_tx_disable_b = 1'b1;
wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [63:0] sfp0_txd_int;
wire [7:0] sfp0_txc_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [63:0] sfp0_rxd_int;
wire [7:0] sfp0_rxc_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [63:0] sfp1_txd_int;
wire [7:0] sfp1_txc_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [63:0] sfp1_rxd_int;
wire [7:0] sfp1_rxc_int;
assign clk_156mhz_int = sfp0_tx_clk_int;
assign rst_156mhz_int = sfp0_tx_rst_int;
wire sfp0_rx_block_lock;
wire sfp1_rx_block_lock;
wire sfp_mgt_refclk_0;
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst (
.I (sfp_mgt_refclk_0_p),
.IB (sfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (sfp_mgt_refclk_0),
.ODIV2 ()
);
wire sfp_qpll0lock;
wire sfp_qpll0outclk;
wire sfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
sfp0_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0lock_out(sfp_qpll0lock),
.xcvr_qpll0outclk_out(sfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(sfp0_tx_p),
.xcvr_txn(sfp0_tx_n),
.xcvr_rxp(sfp0_rx_p),
.xcvr_rxn(sfp0_rx_n),
// PHY connections
.phy_tx_clk(sfp0_tx_clk_int),
.phy_tx_rst(sfp0_tx_rst_int),
.phy_xgmii_txd(sfp0_txd_int),
.phy_xgmii_txc(sfp0_txc_int),
.phy_rx_clk(sfp0_rx_clk_int),
.phy_rx_rst(sfp0_rx_rst_int),
.phy_xgmii_rxd(sfp0_rxd_int),
.phy_xgmii_rxc(sfp0_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp0_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp1_tx_p),
.xcvr_txn(sfp1_tx_n),
.xcvr_rxp(sfp1_rx_p),
.xcvr_rxn(sfp1_rx_n),
// PHY connections
.phy_tx_clk(sfp1_tx_clk_int),
.phy_tx_rst(sfp1_tx_rst_int),
.phy_xgmii_txd(sfp1_txd_int),
.phy_xgmii_txc(sfp1_txc_int),
.phy_rx_clk(sfp1_rx_clk_int),
.phy_rx_rst(sfp1_rx_rst_int),
.phy_xgmii_rxd(sfp1_rxd_int),
.phy_xgmii_rxc(sfp1_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: SFP+
*/
.sfp0_tx_clk(sfp0_tx_clk_int),
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp1_tx_clk(sfp1_tx_clk_int),
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int)
);
endmodule |
module fpga (
/*
* Reset: Push button, active low
*/
input wire reset,
/*
* GPIO
*/
input wire [3:0] sw,
output wire [2:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
output wire qsfp0_tx1_p,
output wire qsfp0_tx1_n,
input wire qsfp0_rx1_p,
input wire qsfp0_rx1_n,
output wire qsfp0_tx2_p,
output wire qsfp0_tx2_n,
input wire qsfp0_rx2_p,
input wire qsfp0_rx2_n,
output wire qsfp0_tx3_p,
output wire qsfp0_tx3_n,
input wire qsfp0_rx3_p,
input wire qsfp0_rx3_n,
output wire qsfp0_tx4_p,
output wire qsfp0_tx4_n,
input wire qsfp0_rx4_p,
input wire qsfp0_rx4_n,
// input wire qsfp0_mgt_refclk_0_p,
// input wire qsfp0_mgt_refclk_0_n,
input wire qsfp0_mgt_refclk_1_p,
input wire qsfp0_mgt_refclk_1_n,
output wire qsfp0_modsell,
output wire qsfp0_resetl,
input wire qsfp0_modprsl,
input wire qsfp0_intl,
output wire qsfp0_lpmode,
output wire qsfp0_refclk_reset,
output wire [1:0] qsfp0_fs,
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
// input wire qsfp1_mgt_refclk_0_p,
// input wire qsfp1_mgt_refclk_0_n,
input wire qsfp1_mgt_refclk_1_p,
input wire qsfp1_mgt_refclk_1_n,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
input wire qsfp1_intl,
output wire qsfp1_lpmode,
output wire qsfp1_refclk_reset,
output wire [1:0] qsfp1_fs,
/*
* UART: 500000 bps, 8N1
*/
output wire uart_rxd,
input wire uart_txd
);
// Clock and reset
wire cfgmclk_int;
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(4),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({sw}),
.out({sw_int})
);
wire uart_txd_int;
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_txd}),
.out({uart_txd_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// startupe3 instance
wire cfgmclk;
STARTUPE3
startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(4'd0),
.DO(),
.DTS(1'b1),
.EOS(),
.FCSBO(1'b0),
.FCSBTS(1'b1),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(1'b0),
.USRCCLKTS(1'b1),
.USRDONEO(1'b0),
.USRDONETS(1'b1)
);
BUFG
cfgmclk_bufg_inst (
.I(cfgmclk),
.O(cfgmclk_int)
);
// configure SI5335 clock generators
reg qsfp_refclk_reset_reg = 1'b1;
reg sys_reset_reg = 1'b1;
reg [9:0] reset_timer_reg = 0;
assign mmcm_rst = sys_reset_reg;
always @(posedge cfgmclk_int) begin
if (&reset_timer_reg) begin
if (qsfp_refclk_reset_reg) begin
qsfp_refclk_reset_reg <= 1'b0;
reset_timer_reg <= 0;
end else begin
qsfp_refclk_reset_reg <= 1'b0;
sys_reset_reg <= 1'b0;
end
end else begin
reset_timer_reg <= reset_timer_reg + 1;
end
if (!reset) begin
qsfp_refclk_reset_reg <= 1'b1;
sys_reset_reg <= 1'b1;
reset_timer_reg <= 0;
end
end
// XGMII 10G PHY
// QSFP0
assign qsfp0_modsell = 1'b0;
assign qsfp0_resetl = 1'b1;
assign qsfp0_lpmode = 1'b0;
assign qsfp0_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp0_fs = 2'b10;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign clk_156mhz_int = qsfp0_tx_clk_1_int;
assign rst_156mhz_int = qsfp0_tx_rst_1_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp0_gtpowergood;
wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp0_mgt_refclk_1),
.ODIV2 (qsfp0_mgt_refclk_1_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (qsfp0_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp0_mgt_refclk_1_int),
.O (qsfp0_mgt_refclk_1_bufg)
);
wire qsfp0_qpll0lock;
wire qsfp0_qpll0outclk;
wire qsfp0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp0_tx1_p),
.xcvr_txn(qsfp0_tx1_n),
.xcvr_rxp(qsfp0_rx1_p),
.xcvr_rxn(qsfp0_rx1_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_1_int),
.phy_tx_rst(qsfp0_tx_rst_1_int),
.phy_xgmii_txd(qsfp0_txd_1_int),
.phy_xgmii_txc(qsfp0_txc_1_int),
.phy_rx_clk(qsfp0_rx_clk_1_int),
.phy_rx_rst(qsfp0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp0_rxd_1_int),
.phy_xgmii_rxc(qsfp0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx2_p),
.xcvr_txn(qsfp0_tx2_n),
.xcvr_rxp(qsfp0_rx2_p),
.xcvr_rxn(qsfp0_rx2_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_2_int),
.phy_tx_rst(qsfp0_tx_rst_2_int),
.phy_xgmii_txd(qsfp0_txd_2_int),
.phy_xgmii_txc(qsfp0_txc_2_int),
.phy_rx_clk(qsfp0_rx_clk_2_int),
.phy_rx_rst(qsfp0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp0_rxd_2_int),
.phy_xgmii_rxc(qsfp0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx3_p),
.xcvr_txn(qsfp0_tx3_n),
.xcvr_rxp(qsfp0_rx3_p),
.xcvr_rxn(qsfp0_rx3_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_3_int),
.phy_tx_rst(qsfp0_tx_rst_3_int),
.phy_xgmii_txd(qsfp0_txd_3_int),
.phy_xgmii_txc(qsfp0_txc_3_int),
.phy_rx_clk(qsfp0_rx_clk_3_int),
.phy_rx_rst(qsfp0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp0_rxd_3_int),
.phy_xgmii_rxc(qsfp0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx4_p),
.xcvr_txn(qsfp0_tx4_n),
.xcvr_rxp(qsfp0_rx4_p),
.xcvr_rxn(qsfp0_rx4_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_4_int),
.phy_tx_rst(qsfp0_tx_rst_4_int),
.phy_xgmii_txd(qsfp0_txd_4_int),
.phy_xgmii_txc(qsfp0_txc_4_int),
.phy_rx_clk(qsfp0_rx_clk_4_int),
.phy_rx_rst(qsfp0_rx_rst_4_int),
.phy_xgmii_rxd(qsfp0_rxd_4_int),
.phy_xgmii_rxc(qsfp0_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// QSFP1
assign qsfp1_modsell = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
assign qsfp1_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp1_fs = 2'b10;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire qsfp1_mgt_refclk_1;
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst (
.I (qsfp1_mgt_refclk_1_p),
.IB (qsfp1_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp1_mgt_refclk_1),
.ODIV2 ()
);
wire qsfp1_qpll0lock;
wire qsfp1_qpll0outclk;
wire qsfp1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp1_tx1_p),
.xcvr_txn(qsfp1_tx1_n),
.xcvr_rxp(qsfp1_rx1_p),
.xcvr_rxn(qsfp1_rx1_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_1_int),
.phy_tx_rst(qsfp1_tx_rst_1_int),
.phy_xgmii_txd(qsfp1_txd_1_int),
.phy_xgmii_txc(qsfp1_txc_1_int),
.phy_rx_clk(qsfp1_rx_clk_1_int),
.phy_rx_rst(qsfp1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp1_rxd_1_int),
.phy_xgmii_rxc(qsfp1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx2_p),
.xcvr_txn(qsfp1_tx2_n),
.xcvr_rxp(qsfp1_rx2_p),
.xcvr_rxn(qsfp1_rx2_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_2_int),
.phy_tx_rst(qsfp1_tx_rst_2_int),
.phy_xgmii_txd(qsfp1_txd_2_int),
.phy_xgmii_txc(qsfp1_txc_2_int),
.phy_rx_clk(qsfp1_rx_clk_2_int),
.phy_rx_rst(qsfp1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp1_rxd_2_int),
.phy_xgmii_rxc(qsfp1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx3_p),
.xcvr_txn(qsfp1_tx3_n),
.xcvr_rxp(qsfp1_rx3_p),
.xcvr_rxn(qsfp1_rx3_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_3_int),
.phy_tx_rst(qsfp1_tx_rst_3_int),
.phy_xgmii_txd(qsfp1_txd_3_int),
.phy_xgmii_txc(qsfp1_txc_3_int),
.phy_rx_clk(qsfp1_rx_clk_3_int),
.phy_rx_rst(qsfp1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp1_rxd_3_int),
.phy_xgmii_rxc(qsfp1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx4_p),
.xcvr_txn(qsfp1_tx4_n),
.xcvr_rxp(qsfp1_rx4_p),
.xcvr_rxn(qsfp1_rx4_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_4_int),
.phy_tx_rst(qsfp1_tx_rst_4_int),
.phy_xgmii_txd(qsfp1_txd_4_int),
.phy_xgmii_txc(qsfp1_txc_4_int),
.phy_rx_clk(qsfp1_rx_clk_4_int),
.phy_rx_rst(qsfp1_rx_rst_4_int),
.phy_xgmii_rxd(qsfp1_rxd_4_int),
.phy_xgmii_rxc(qsfp1_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sw(sw_int),
.led(led),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd),
.uart_txd(uart_txd_int)
);
endmodule |
module fpga (
/*
* Clock: 100MHz
*/
input wire init_clk,
/*
* GPIO
*/
output wire led_sreg_d,
output wire led_sreg_ld,
output wire led_sreg_clk,
output wire [1:0] led_bmc,
output wire [1:0] led_exp,
/*
* Board status
*/
input wire [1:0] pg,
/*
* Ethernet: QSFP28
*/
output wire qsfp_0_tx_0_p,
output wire qsfp_0_tx_0_n,
input wire qsfp_0_rx_0_p,
input wire qsfp_0_rx_0_n,
output wire qsfp_0_tx_1_p,
output wire qsfp_0_tx_1_n,
input wire qsfp_0_rx_1_p,
input wire qsfp_0_rx_1_n,
output wire qsfp_0_tx_2_p,
output wire qsfp_0_tx_2_n,
input wire qsfp_0_rx_2_p,
input wire qsfp_0_rx_2_n,
output wire qsfp_0_tx_3_p,
output wire qsfp_0_tx_3_n,
input wire qsfp_0_rx_3_p,
input wire qsfp_0_rx_3_n,
input wire qsfp_0_mgt_refclk_p,
input wire qsfp_0_mgt_refclk_n,
input wire qsfp_0_mod_prsnt_n,
output wire qsfp_0_reset_n,
output wire qsfp_0_lp_mode,
input wire qsfp_0_intr_n,
output wire qsfp_1_tx_0_p,
output wire qsfp_1_tx_0_n,
input wire qsfp_1_rx_0_p,
input wire qsfp_1_rx_0_n,
output wire qsfp_1_tx_1_p,
output wire qsfp_1_tx_1_n,
input wire qsfp_1_rx_1_p,
input wire qsfp_1_rx_1_n,
output wire qsfp_1_tx_2_p,
output wire qsfp_1_tx_2_n,
input wire qsfp_1_rx_2_p,
input wire qsfp_1_rx_2_n,
output wire qsfp_1_tx_3_p,
output wire qsfp_1_tx_3_n,
input wire qsfp_1_rx_3_p,
input wire qsfp_1_rx_3_n,
input wire qsfp_1_mgt_refclk_p,
input wire qsfp_1_mgt_refclk_n,
input wire qsfp_1_mod_prsnt_n,
output wire qsfp_1_reset_n,
output wire qsfp_1_lp_mode,
input wire qsfp_1_intr_n
);
// Clock and reset
wire init_clk_bufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = !pg[0] || !pg[1];
wire mmcm_locked;
wire mmcm_clkfb;
BUFG
init_clk_bufg_inst (
.I(init_clk),
.O(init_clk_bufg)
);
// MMCM instance
// 50 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 20, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(20),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(20.000),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(init_clk_bufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [7:0] led_red;
wire [7:0] led_green;
wire [15:0] led_merged;
assign led_merged[0] = led_red[0];
assign led_merged[1] = led_green[0];
assign led_merged[2] = led_red[1];
assign led_merged[3] = led_green[1];
assign led_merged[4] = led_red[2];
assign led_merged[5] = led_green[2];
assign led_merged[6] = led_red[3];
assign led_merged[7] = led_green[3];
assign led_merged[8] = led_red[4];
assign led_merged[9] = led_green[4];
assign led_merged[10] = led_red[5];
assign led_merged[11] = led_green[5];
assign led_merged[12] = led_red[6];
assign led_merged[13] = led_green[6];
assign led_merged[14] = led_red[7];
assign led_merged[15] = led_green[7];
led_sreg_driver #(
.COUNT(16),
.INVERT(1),
.PRESCALE(31)
)
led_sreg_driver_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.led(led_merged),
.sreg_d(led_sreg_d),
.sreg_ld(led_sreg_ld),
.sreg_clk(led_sreg_clk)
);
// XGMII 10G PHY
// QSFP0
assign qsfp_0_reset_n = 1'b1;
assign qsfp_0_lp_mode = 1'b0;
wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [63:0] qsfp_0_txd_0_int;
wire [7:0] qsfp_0_txc_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [63:0] qsfp_0_rxd_0_int;
wire [7:0] qsfp_0_rxc_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [63:0] qsfp_0_txd_1_int;
wire [7:0] qsfp_0_txc_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [63:0] qsfp_0_rxd_1_int;
wire [7:0] qsfp_0_rxc_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [63:0] qsfp_0_txd_2_int;
wire [7:0] qsfp_0_txc_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [63:0] qsfp_0_rxd_2_int;
wire [7:0] qsfp_0_rxc_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [63:0] qsfp_0_txd_3_int;
wire [7:0] qsfp_0_txc_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [63:0] qsfp_0_rxd_3_int;
wire [7:0] qsfp_0_rxc_3_int;
assign clk_156mhz_int = qsfp_0_tx_clk_0_int;
assign rst_156mhz_int = qsfp_0_tx_rst_0_int;
wire qsfp_0_rx_block_lock_0;
wire qsfp_0_rx_block_lock_1;
wire qsfp_0_rx_block_lock_2;
wire qsfp_0_rx_block_lock_3;
wire qsfp_0_gtpowergood;
wire qsfp_0_mgt_refclk;
wire qsfp_0_mgt_refclk_int;
wire qsfp_0_mgt_refclk_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
.I (qsfp_0_mgt_refclk_p),
.IB (qsfp_0_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_0_mgt_refclk),
.ODIV2 (qsfp_0_mgt_refclk_int)
);
BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
.CE (qsfp_0_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp_0_mgt_refclk_int),
.O (qsfp_0_mgt_refclk_bufg)
);
wire qsfp_0_rst;
sync_reset #(
.N(4)
)
qsfp_0_sync_reset_inst (
.clk(qsfp_0_mgt_refclk_bufg),
.rst(rst_125mhz_int),
.out(qsfp_0_rst)
);
wire qsfp_0_qpll0lock;
wire qsfp_0_qpll0outclk;
wire qsfp_0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_0_phy_0_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_0_rst),
// Common
.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_0_tx_0_p),
.xcvr_txn(qsfp_0_tx_0_n),
.xcvr_rxp(qsfp_0_rx_0_p),
.xcvr_rxn(qsfp_0_rx_0_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_0_int),
.phy_tx_rst(qsfp_0_tx_rst_0_int),
.phy_xgmii_txd(qsfp_0_txd_0_int),
.phy_xgmii_txc(qsfp_0_txc_0_int),
.phy_rx_clk(qsfp_0_rx_clk_0_int),
.phy_rx_rst(qsfp_0_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_0_rxd_0_int),
.phy_xgmii_rxc(qsfp_0_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_0_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_1_p),
.xcvr_txn(qsfp_0_tx_1_n),
.xcvr_rxp(qsfp_0_rx_1_p),
.xcvr_rxn(qsfp_0_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_1_int),
.phy_tx_rst(qsfp_0_tx_rst_1_int),
.phy_xgmii_txd(qsfp_0_txd_1_int),
.phy_xgmii_txc(qsfp_0_txc_1_int),
.phy_rx_clk(qsfp_0_rx_clk_1_int),
.phy_rx_rst(qsfp_0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_0_rxd_1_int),
.phy_xgmii_rxc(qsfp_0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_0_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_2_p),
.xcvr_txn(qsfp_0_tx_2_n),
.xcvr_rxp(qsfp_0_rx_2_p),
.xcvr_rxn(qsfp_0_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_2_int),
.phy_tx_rst(qsfp_0_tx_rst_2_int),
.phy_xgmii_txd(qsfp_0_txd_2_int),
.phy_xgmii_txc(qsfp_0_txc_2_int),
.phy_rx_clk(qsfp_0_rx_clk_2_int),
.phy_rx_rst(qsfp_0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_0_rxd_2_int),
.phy_xgmii_rxc(qsfp_0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_0_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_3_p),
.xcvr_txn(qsfp_0_tx_3_n),
.xcvr_rxp(qsfp_0_rx_3_p),
.xcvr_rxn(qsfp_0_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_3_int),
.phy_tx_rst(qsfp_0_tx_rst_3_int),
.phy_xgmii_txd(qsfp_0_txd_3_int),
.phy_xgmii_txc(qsfp_0_txc_3_int),
.phy_rx_clk(qsfp_0_rx_clk_3_int),
.phy_rx_rst(qsfp_0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_0_rxd_3_int),
.phy_xgmii_rxc(qsfp_0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// QSFP1
assign qsfp_1_reset_n = 1'b1;
assign qsfp_1_lp_mode = 1'b0;
wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [63:0] qsfp_1_txd_0_int;
wire [7:0] qsfp_1_txc_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [63:0] qsfp_1_rxd_0_int;
wire [7:0] qsfp_1_rxc_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [63:0] qsfp_1_txd_1_int;
wire [7:0] qsfp_1_txc_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [63:0] qsfp_1_rxd_1_int;
wire [7:0] qsfp_1_rxc_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [63:0] qsfp_1_txd_2_int;
wire [7:0] qsfp_1_txc_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [63:0] qsfp_1_rxd_2_int;
wire [7:0] qsfp_1_rxc_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [63:0] qsfp_1_txd_3_int;
wire [7:0] qsfp_1_txc_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [63:0] qsfp_1_rxd_3_int;
wire [7:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_block_lock_0;
wire qsfp_1_rx_block_lock_1;
wire qsfp_1_rx_block_lock_2;
wire qsfp_1_rx_block_lock_3;
wire qsfp_1_gtpowergood;
wire qsfp_1_mgt_refclk;
wire qsfp_1_mgt_refclk_int;
wire qsfp_1_mgt_refclk_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
.I (qsfp_1_mgt_refclk_p),
.IB (qsfp_1_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_1_mgt_refclk),
.ODIV2 (qsfp_1_mgt_refclk_int)
);
BUFG_GT bufg_gt_qsfp_1_mgt_refclk_inst (
.CE (qsfp_1_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp_1_mgt_refclk_int),
.O (qsfp_1_mgt_refclk_bufg)
);
wire qsfp_1_rst;
sync_reset #(
.N(4)
)
qsfp_1_sync_reset_inst (
.clk(qsfp_1_mgt_refclk_bufg),
.rst(rst_125mhz_int),
.out(qsfp_1_rst)
);
wire qsfp_1_qpll0lock;
wire qsfp_1_qpll0outclk;
wire qsfp_1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_1_phy_0_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_1_rst),
// Common
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_1_tx_0_p),
.xcvr_txn(qsfp_1_tx_0_n),
.xcvr_rxp(qsfp_1_rx_0_p),
.xcvr_rxn(qsfp_1_rx_0_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_0_int),
.phy_tx_rst(qsfp_1_tx_rst_0_int),
.phy_xgmii_txd(qsfp_1_txd_0_int),
.phy_xgmii_txc(qsfp_1_txc_0_int),
.phy_rx_clk(qsfp_1_rx_clk_0_int),
.phy_rx_rst(qsfp_1_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_1_rxd_0_int),
.phy_xgmii_rxc(qsfp_1_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_1_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_1_p),
.xcvr_txn(qsfp_1_tx_1_n),
.xcvr_rxp(qsfp_1_rx_1_p),
.xcvr_rxn(qsfp_1_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_1_int),
.phy_tx_rst(qsfp_1_tx_rst_1_int),
.phy_xgmii_txd(qsfp_1_txd_1_int),
.phy_xgmii_txc(qsfp_1_txc_1_int),
.phy_rx_clk(qsfp_1_rx_clk_1_int),
.phy_rx_rst(qsfp_1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_1_rxd_1_int),
.phy_xgmii_rxc(qsfp_1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_1_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_2_p),
.xcvr_txn(qsfp_1_tx_2_n),
.xcvr_rxp(qsfp_1_rx_2_p),
.xcvr_rxn(qsfp_1_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_2_int),
.phy_tx_rst(qsfp_1_tx_rst_2_int),
.phy_xgmii_txd(qsfp_1_txd_2_int),
.phy_xgmii_txc(qsfp_1_txc_2_int),
.phy_rx_clk(qsfp_1_rx_clk_2_int),
.phy_rx_rst(qsfp_1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_1_rxd_2_int),
.phy_xgmii_rxc(qsfp_1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(qsfp_1_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_3_p),
.xcvr_txn(qsfp_1_tx_3_n),
.xcvr_rxp(qsfp_1_rx_3_p),
.xcvr_rxn(qsfp_1_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_3_int),
.phy_tx_rst(qsfp_1_tx_rst_3_int),
.phy_xgmii_txd(qsfp_1_txd_3_int),
.phy_xgmii_txc(qsfp_1_txc_3_int),
.phy_rx_clk(qsfp_1_rx_clk_3_int),
.phy_rx_rst(qsfp_1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_1_rxd_3_int),
.phy_xgmii_rxc(qsfp_1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
assign led_green[0] = qsfp_0_rx_block_lock_0;
assign led_green[1] = qsfp_0_rx_block_lock_1;
assign led_green[2] = qsfp_0_rx_block_lock_2;
assign led_green[3] = qsfp_0_rx_block_lock_3;
assign led_green[4] = qsfp_1_rx_block_lock_0;
assign led_green[5] = qsfp_1_rx_block_lock_1;
assign led_green[6] = qsfp_1_rx_block_lock_2;
assign led_green[7] = qsfp_1_rx_block_lock_3;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.led_red(led_red),
// .led_green(led_green),
.led_bmc(led_bmc),
.led_exp(led_exp),
/*
* Ethernet: QSFP28
*/
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
);
endmodule |
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
input wire qsfp_rx1_p,
input wire qsfp_rx1_n,
input wire qsfp_rx2_p,
input wire qsfp_rx2_n,
input wire qsfp_rx3_p,
input wire qsfp_rx3_n,
input wire qsfp_rx4_p,
input wire qsfp_rx4_n,
output wire qsfp_tx1_p,
output wire qsfp_tx1_n,
output wire qsfp_tx2_p,
output wire qsfp_tx2_n,
output wire qsfp_tx3_p,
output wire qsfp_tx3_n,
output wire qsfp_tx4_p,
output wire qsfp_tx4_n,
input wire qsfp_mgt_refclk_0_p,
input wire qsfp_mgt_refclk_0_n,
// input wire qsfp_mgt_refclk_1_p,
// input wire qsfp_mgt_refclk_1_n,
// output wire qsfp_recclk_p,
// output wire qsfp_recclk_n,
output wire qsfp_modsell,
output wire qsfp_resetl,
input wire qsfp_modprsl,
input wire qsfp_intl,
output wire qsfp_lpmode,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// XGMII 10G PHY
assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [63:0] qsfp_txd_1_int;
wire [7:0] qsfp_txc_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [63:0] qsfp_rxd_1_int;
wire [7:0] qsfp_rxc_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [63:0] qsfp_txd_2_int;
wire [7:0] qsfp_txc_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [63:0] qsfp_rxd_2_int;
wire [7:0] qsfp_rxc_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [63:0] qsfp_txd_3_int;
wire [7:0] qsfp_txc_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [63:0] qsfp_rxd_3_int;
wire [7:0] qsfp_rxc_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [63:0] qsfp_txd_4_int;
wire [7:0] qsfp_txc_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [63:0] qsfp_rxd_4_int;
wire [7:0] qsfp_rxc_4_int;
assign clk_156mhz_int = qsfp_tx_clk_1_int;
assign rst_156mhz_int = qsfp_tx_rst_1_int;
wire qsfp_rx_block_lock_1;
wire qsfp_rx_block_lock_2;
wire qsfp_rx_block_lock_3;
wire qsfp_rx_block_lock_4;
wire qsfp_mgt_refclk_0;
IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 ()
);
wire qsfp_qpll0lock;
wire qsfp_qpll0outclk;
wire qsfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
.xcvr_qpll0lock_out(qsfp_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_tx1_p),
.xcvr_txn(qsfp_tx1_n),
.xcvr_rxp(qsfp_rx1_p),
.xcvr_rxn(qsfp_rx1_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_1_int),
.phy_tx_rst(qsfp_tx_rst_1_int),
.phy_xgmii_txd(qsfp_txd_1_int),
.phy_xgmii_txc(qsfp_txc_1_int),
.phy_rx_clk(qsfp_rx_clk_1_int),
.phy_rx_rst(qsfp_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_rxd_1_int),
.phy_xgmii_rxc(qsfp_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx2_p),
.xcvr_txn(qsfp_tx2_n),
.xcvr_rxp(qsfp_rx2_p),
.xcvr_rxn(qsfp_rx2_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_2_int),
.phy_tx_rst(qsfp_tx_rst_2_int),
.phy_xgmii_txd(qsfp_txd_2_int),
.phy_xgmii_txc(qsfp_txc_2_int),
.phy_rx_clk(qsfp_rx_clk_2_int),
.phy_rx_rst(qsfp_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_rxd_2_int),
.phy_xgmii_rxc(qsfp_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx3_p),
.xcvr_txn(qsfp_tx3_n),
.xcvr_rxp(qsfp_rx3_p),
.xcvr_rxn(qsfp_rx3_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_3_int),
.phy_tx_rst(qsfp_tx_rst_3_int),
.phy_xgmii_txd(qsfp_txd_3_int),
.phy_xgmii_txc(qsfp_txc_3_int),
.phy_rx_clk(qsfp_rx_clk_3_int),
.phy_rx_rst(qsfp_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_rxd_3_int),
.phy_xgmii_rxc(qsfp_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx4_p),
.xcvr_txn(qsfp_tx4_n),
.xcvr_rxp(qsfp_rx4_p),
.xcvr_rxn(qsfp_rx4_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_4_int),
.phy_tx_rst(qsfp_tx_rst_4_int),
.phy_xgmii_txd(qsfp_txd_4_int),
.phy_xgmii_txc(qsfp_txc_4_int),
.phy_rx_clk(qsfp_rx_clk_4_int),
.phy_rx_rst(qsfp_rx_rst_4_int),
.phy_xgmii_rxd(qsfp_rxd_4_int),
.phy_xgmii_rxc(qsfp_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
gig_eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (gig_eth_pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (gig_eth_pcspma_status_vector),
.signal_detect (1'b1)
);
wire [7:0] led_int;
assign led[0] = sw[0] ? qsfp_rx_block_lock_1 : led_int[0];
assign led[1] = sw[0] ? qsfp_rx_block_lock_2 : led_int[1];
assign led[2] = sw[0] ? qsfp_rx_block_lock_3 : led_int[2];
assign led[3] = sw[0] ? qsfp_rx_block_lock_4 : led_int[3];
assign led[4] = sw[0] ? 1'b0 : led_int[4];
assign led[5] = sw[0] ? 1'b0 : led_int[5];
assign led[6] = sw[0] ? 1'b0 : led_int[6];
assign led[7] = sw[0] ? 1'b0 : led_int[7];
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: QSFP28
*/
.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule |
module fpga (
/*
* GPIO
*/
output wire [1:0] sfp_1_led,
output wire [1:0] sfp_2_led,
output wire [1:0] sma_led,
/*
* Ethernet: SFP+
*/
input wire sfp_1_rx_p,
input wire sfp_1_rx_n,
output wire sfp_1_tx_p,
output wire sfp_1_tx_n,
input wire sfp_2_rx_p,
input wire sfp_2_rx_n,
output wire sfp_2_tx_p,
output wire sfp_2_tx_n,
input wire sfp_mgt_refclk_p,
input wire sfp_mgt_refclk_n,
output wire sfp_1_tx_disable,
output wire sfp_2_tx_disable,
input wire sfp_1_npres,
input wire sfp_2_npres,
input wire sfp_1_los,
input wire sfp_2_los,
output wire sfp_1_rs,
output wire sfp_2_rs
);
// Clock and reset
wire clk_161mhz_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [1:0] sfp_1_led_int;
wire [1:0] sfp_2_led_int;
wire [1:0] sma_led_int;
// XGMII 10G PHY
assign sfp_1_tx_disable = 1'b0;
assign sfp_2_tx_disable = 1'b0;
assign sfp_1_rs = 1'b1;
assign sfp_2_rs = 1'b1;
wire sfp_1_tx_clk_int;
wire sfp_1_tx_rst_int;
wire [63:0] sfp_1_txd_int;
wire [7:0] sfp_1_txc_int;
wire sfp_1_rx_clk_int;
wire sfp_1_rx_rst_int;
wire [63:0] sfp_1_rxd_int;
wire [7:0] sfp_1_rxc_int;
wire sfp_2_tx_clk_int;
wire sfp_2_tx_rst_int;
wire [63:0] sfp_2_txd_int;
wire [7:0] sfp_2_txc_int;
wire sfp_2_rx_clk_int;
wire sfp_2_rx_rst_int;
wire [63:0] sfp_2_rxd_int;
wire [7:0] sfp_2_rxc_int;
assign clk_156mhz_int = sfp_1_tx_clk_int;
assign rst_156mhz_int = sfp_1_tx_rst_int;
wire sfp_1_rx_block_lock;
wire sfp_2_rx_block_lock;
wire sfp_gtpowergood;
wire sfp_mgt_refclk;
wire sfp_mgt_refclk_int;
wire sfp_mgt_refclk_bufg;
assign clk_161mhz_int = sfp_mgt_refclk_bufg;
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_inst (
.I (sfp_mgt_refclk_p),
.IB (sfp_mgt_refclk_n),
.CEB (1'b0),
.O (sfp_mgt_refclk),
.ODIV2 (sfp_mgt_refclk_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (sfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'b000),
.I (sfp_mgt_refclk_int),
.O (sfp_mgt_refclk_bufg)
);
wire sfp_qpll0lock;
wire sfp_qpll0outclk;
wire sfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
sfp_1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(sfp_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(sfp_mgt_refclk),
.xcvr_qpll0lock_out(sfp_qpll0lock),
.xcvr_qpll0outclk_out(sfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(sfp_1_tx_p),
.xcvr_txn(sfp_1_tx_n),
.xcvr_rxp(sfp_1_rx_p),
.xcvr_rxn(sfp_1_rx_n),
// PHY connections
.phy_tx_clk(sfp_1_tx_clk_int),
.phy_tx_rst(sfp_1_tx_rst_int),
.phy_xgmii_txd(sfp_1_txd_int),
.phy_xgmii_txc(sfp_1_txc_int),
.phy_rx_clk(sfp_1_rx_clk_int),
.phy_rx_rst(sfp_1_rx_rst_int),
.phy_xgmii_rxd(sfp_1_rxd_int),
.phy_xgmii_rxc(sfp_1_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp_2_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp_2_tx_p),
.xcvr_txn(sfp_2_tx_n),
.xcvr_rxp(sfp_2_rx_p),
.xcvr_rxn(sfp_2_rx_n),
// PHY connections
.phy_tx_clk(sfp_2_tx_clk_int),
.phy_tx_rst(sfp_2_tx_rst_int),
.phy_xgmii_txd(sfp_2_txd_int),
.phy_xgmii_txc(sfp_2_txc_int),
.phy_rx_clk(sfp_2_rx_clk_int),
.phy_rx_rst(sfp_2_rx_rst_int),
.phy_xgmii_rxd(sfp_2_rxd_int),
.phy_xgmii_rxc(sfp_2_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp_2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
assign sfp_1_led[0] = sfp_1_rx_block_lock;
assign sfp_1_led[1] = 1'b0;
assign sfp_2_led[0] = sfp_2_rx_block_lock;
assign sfp_2_led[1] = 1'b0;
assign sma_led = sma_led_int;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sfp_1_led(sfp_1_led_int),
.sfp_2_led(sfp_2_led_int),
.sma_led(sma_led_int),
/*
* Ethernet: SFP+
*/
.sfp_1_tx_clk(sfp_1_tx_clk_int),
.sfp_1_tx_rst(sfp_1_tx_rst_int),
.sfp_1_txd(sfp_1_txd_int),
.sfp_1_txc(sfp_1_txc_int),
.sfp_1_rx_clk(sfp_1_rx_clk_int),
.sfp_1_rx_rst(sfp_1_rx_rst_int),
.sfp_1_rxd(sfp_1_rxd_int),
.sfp_1_rxc(sfp_1_rxc_int),
.sfp_2_tx_clk(sfp_2_tx_clk_int),
.sfp_2_tx_rst(sfp_2_tx_rst_int),
.sfp_2_txd(sfp_2_txd_int),
.sfp_2_txc(sfp_2_txc_int),
.sfp_2_rx_clk(sfp_2_rx_clk_int),
.sfp_2_rx_rst(sfp_2_rx_rst_int),
.sfp_2_rxd(sfp_2_rxd_int),
.sfp_2_rxc(sfp_2_rxc_int)
);
endmodule |
module fpga (
/*
* GPIO
*/
output wire qsfp_led_act,
output wire qsfp_led_stat_g,
output wire qsfp_led_stat_y,
output wire hbm_cattrip,
/*
* Ethernet: QSFP28
*/
output wire qsfp_tx1_p,
output wire qsfp_tx1_n,
input wire qsfp_rx1_p,
input wire qsfp_rx1_n,
output wire qsfp_tx2_p,
output wire qsfp_tx2_n,
input wire qsfp_rx2_p,
input wire qsfp_rx2_n,
output wire qsfp_tx3_p,
output wire qsfp_tx3_n,
input wire qsfp_rx3_p,
input wire qsfp_rx3_n,
output wire qsfp_tx4_p,
output wire qsfp_tx4_n,
input wire qsfp_rx4_p,
input wire qsfp_rx4_n,
input wire qsfp_mgt_refclk_0_p,
input wire qsfp_mgt_refclk_0_n
// input wire qsfp_mgt_refclk_1_p,
// input wire qsfp_mgt_refclk_1_n
);
// Clock and reset
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
assign hbm_cattrip = 1'b0;
// XGMII 10G PHY
wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [63:0] qsfp_txd_1_int;
wire [7:0] qsfp_txc_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [63:0] qsfp_rxd_1_int;
wire [7:0] qsfp_rxc_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [63:0] qsfp_txd_2_int;
wire [7:0] qsfp_txc_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [63:0] qsfp_rxd_2_int;
wire [7:0] qsfp_rxc_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [63:0] qsfp_txd_3_int;
wire [7:0] qsfp_txc_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [63:0] qsfp_rxd_3_int;
wire [7:0] qsfp_rxc_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [63:0] qsfp_txd_4_int;
wire [7:0] qsfp_txc_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [63:0] qsfp_rxd_4_int;
wire [7:0] qsfp_rxc_4_int;
assign clk_156mhz_int = qsfp_tx_clk_1_int;
assign rst_156mhz_int = qsfp_tx_rst_1_int;
wire qsfp_rx_block_lock_1;
wire qsfp_rx_block_lock_2;
wire qsfp_rx_block_lock_3;
wire qsfp_rx_block_lock_4;
wire qsfp_gtpowergood;
wire qsfp_mgt_refclk_0;
wire qsfp_mgt_refclk_0_int;
wire qsfp_mgt_refclk_0_bufg;
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 (qsfp_mgt_refclk_0_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (qsfp_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp_mgt_refclk_0_int),
.O (qsfp_mgt_refclk_0_bufg)
);
wire qsfp_qpll0lock;
wire qsfp_qpll0outclk;
wire qsfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(qsfp_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
.xcvr_qpll0lock_out(qsfp_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_tx1_p),
.xcvr_txn(qsfp_tx1_n),
.xcvr_rxp(qsfp_rx1_p),
.xcvr_rxn(qsfp_rx1_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_1_int),
.phy_tx_rst(qsfp_tx_rst_1_int),
.phy_xgmii_txd(qsfp_txd_1_int),
.phy_xgmii_txc(qsfp_txc_1_int),
.phy_rx_clk(qsfp_rx_clk_1_int),
.phy_rx_rst(qsfp_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_rxd_1_int),
.phy_xgmii_rxc(qsfp_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx2_p),
.xcvr_txn(qsfp_tx2_n),
.xcvr_rxp(qsfp_rx2_p),
.xcvr_rxn(qsfp_rx2_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_2_int),
.phy_tx_rst(qsfp_tx_rst_2_int),
.phy_xgmii_txd(qsfp_txd_2_int),
.phy_xgmii_txc(qsfp_txc_2_int),
.phy_rx_clk(qsfp_rx_clk_2_int),
.phy_rx_rst(qsfp_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_rxd_2_int),
.phy_xgmii_rxc(qsfp_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx3_p),
.xcvr_txn(qsfp_tx3_n),
.xcvr_rxp(qsfp_rx3_p),
.xcvr_rxn(qsfp_rx3_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_3_int),
.phy_tx_rst(qsfp_tx_rst_3_int),
.phy_xgmii_txd(qsfp_txd_3_int),
.phy_xgmii_txc(qsfp_txc_3_int),
.phy_rx_clk(qsfp_rx_clk_3_int),
.phy_rx_rst(qsfp_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_rxd_3_int),
.phy_xgmii_rxc(qsfp_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_tx4_p),
.xcvr_txn(qsfp_tx4_n),
.xcvr_rxp(qsfp_rx4_p),
.xcvr_rxn(qsfp_rx4_n),
// PHY connections
.phy_tx_clk(qsfp_tx_clk_4_int),
.phy_tx_rst(qsfp_tx_rst_4_int),
.phy_xgmii_txd(qsfp_txd_4_int),
.phy_xgmii_txc(qsfp_txc_4_int),
.phy_rx_clk(qsfp_rx_clk_4_int),
.phy_rx_rst(qsfp_rx_rst_4_int),
.phy_xgmii_rxd(qsfp_rxd_4_int),
.phy_xgmii_rxc(qsfp_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.qsfp_led_act(qsfp_led_act),
.qsfp_led_stat_g(qsfp_led_stat_g),
.qsfp_led_stat_y(qsfp_led_stat_y),
/*
* Ethernet: QSFP28
*/
.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int)
);
endmodule |
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_rx_p,
input wire sfp0_rx_n,
output wire sfp0_tx_p,
output wire sfp0_tx_n,
input wire sfp1_rx_p,
input wire sfp1_rx_n,
output wire sfp1_tx_p,
output wire sfp1_tx_n,
input wire sfp2_rx_p,
input wire sfp2_rx_n,
output wire sfp2_tx_p,
output wire sfp2_tx_n,
input wire sfp3_rx_p,
input wire sfp3_rx_n,
output wire sfp3_tx_p,
output wire sfp3_tx_n,
input wire sfp_mgt_refclk_0_p,
input wire sfp_mgt_refclk_0_n,
output wire sfp0_tx_disable_b,
output wire sfp1_tx_disable_b,
output wire sfp2_tx_disable_b,
output wire sfp3_tx_disable_b
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_bufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
BUFG
clk_125mhz_bufg_in_inst (
.I(clk_125mhz_ibufg),
.O(clk_125mhz_bufg)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_bufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(8),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_rts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_rts}),
.out({uart_rxd_int, uart_rts_int})
);
// XGMII 10G PHY
assign sfp0_tx_disable_b = 1'b1;
assign sfp1_tx_disable_b = 1'b1;
assign sfp2_tx_disable_b = 1'b1;
assign sfp3_tx_disable_b = 1'b1;
wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [63:0] sfp0_txd_int;
wire [7:0] sfp0_txc_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [63:0] sfp0_rxd_int;
wire [7:0] sfp0_rxc_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [63:0] sfp1_txd_int;
wire [7:0] sfp1_txc_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [63:0] sfp1_rxd_int;
wire [7:0] sfp1_rxc_int;
wire sfp2_tx_clk_int;
wire sfp2_tx_rst_int;
wire [63:0] sfp2_txd_int;
wire [7:0] sfp2_txc_int;
wire sfp2_rx_clk_int;
wire sfp2_rx_rst_int;
wire [63:0] sfp2_rxd_int;
wire [7:0] sfp2_rxc_int;
wire sfp3_tx_clk_int;
wire sfp3_tx_rst_int;
wire [63:0] sfp3_txd_int;
wire [7:0] sfp3_txc_int;
wire sfp3_rx_clk_int;
wire sfp3_rx_rst_int;
wire [63:0] sfp3_rxd_int;
wire [7:0] sfp3_rxc_int;
assign clk_156mhz_int = sfp0_tx_clk_int;
assign rst_156mhz_int = sfp0_tx_rst_int;
wire sfp0_rx_block_lock;
wire sfp1_rx_block_lock;
wire sfp2_rx_block_lock;
wire sfp3_rx_block_lock;
wire sfp_mgt_refclk_0;
IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst (
.I (sfp_mgt_refclk_0_p),
.IB (sfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (sfp_mgt_refclk_0),
.ODIV2 ()
);
wire sfp_qpll0lock;
wire sfp_qpll0outclk;
wire sfp_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
sfp0_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
.xcvr_qpll0lock_out(sfp_qpll0lock),
.xcvr_qpll0outclk_out(sfp_qpll0outclk),
.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(sfp0_tx_p),
.xcvr_txn(sfp0_tx_n),
.xcvr_rxp(sfp0_rx_p),
.xcvr_rxn(sfp0_rx_n),
// PHY connections
.phy_tx_clk(sfp0_tx_clk_int),
.phy_tx_rst(sfp0_tx_rst_int),
.phy_xgmii_txd(sfp0_txd_int),
.phy_xgmii_txc(sfp0_txc_int),
.phy_rx_clk(sfp0_rx_clk_int),
.phy_rx_rst(sfp0_rx_rst_int),
.phy_xgmii_rxd(sfp0_rxd_int),
.phy_xgmii_rxc(sfp0_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp0_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp1_tx_p),
.xcvr_txn(sfp1_tx_n),
.xcvr_rxp(sfp1_rx_p),
.xcvr_rxn(sfp1_rx_n),
// PHY connections
.phy_tx_clk(sfp1_tx_clk_int),
.phy_tx_rst(sfp1_tx_rst_int),
.phy_xgmii_txd(sfp1_txd_int),
.phy_xgmii_txc(sfp1_txc_int),
.phy_rx_clk(sfp1_rx_clk_int),
.phy_rx_rst(sfp1_rx_rst_int),
.phy_xgmii_rxd(sfp1_rxd_int),
.phy_xgmii_rxc(sfp1_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp1_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp2_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp2_tx_p),
.xcvr_txn(sfp2_tx_n),
.xcvr_rxp(sfp2_rx_p),
.xcvr_rxn(sfp2_rx_n),
// PHY connections
.phy_tx_clk(sfp2_tx_clk_int),
.phy_tx_rst(sfp2_tx_rst_int),
.phy_xgmii_txd(sfp2_txd_int),
.phy_xgmii_txc(sfp2_txc_int),
.phy_rx_clk(sfp2_rx_clk_int),
.phy_rx_rst(sfp2_rx_rst_int),
.phy_xgmii_rxd(sfp2_rxd_int),
.phy_xgmii_rxc(sfp2_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp2_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
sfp3_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(sfp_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(sfp_qpll0outclk),
.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
// Serial data
.xcvr_txp(sfp3_tx_p),
.xcvr_txn(sfp3_tx_n),
.xcvr_rxp(sfp3_rx_p),
.xcvr_rxn(sfp3_rx_n),
// PHY connections
.phy_tx_clk(sfp3_tx_clk_int),
.phy_tx_rst(sfp3_tx_rst_int),
.phy_xgmii_txd(sfp3_txd_int),
.phy_xgmii_txc(sfp3_txc_int),
.phy_rx_clk(sfp3_rx_clk_int),
.phy_rx_rst(sfp3_rx_rst_int),
.phy_xgmii_rxd(sfp3_rxd_int),
.phy_xgmii_rxc(sfp3_rxc_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(sfp3_rx_block_lock),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts),
/*
* Ethernet: SFP+
*/
.sfp0_tx_clk(sfp0_tx_clk_int),
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp1_tx_clk(sfp1_tx_clk_int),
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int),
.sfp2_tx_clk(sfp2_tx_clk_int),
.sfp2_tx_rst(sfp2_tx_rst_int),
.sfp2_txd(sfp2_txd_int),
.sfp2_txc(sfp2_txc_int),
.sfp2_rx_clk(sfp2_rx_clk_int),
.sfp2_rx_rst(sfp2_rx_rst_int),
.sfp2_rxd(sfp2_rxd_int),
.sfp2_rxc(sfp2_rxc_int),
.sfp3_tx_clk(sfp3_tx_clk_int),
.sfp3_tx_rst(sfp3_tx_rst_int),
.sfp3_txd(sfp3_txd_int),
.sfp3_txc(sfp3_txc_int),
.sfp3_rx_clk(sfp3_rx_clk_int),
.sfp3_rx_rst(sfp3_rx_rst_int),
.sfp3_rxd(sfp3_rxd_int),
.sfp3_rxc(sfp3_rxc_int)
);
endmodule |
module fpga (
/*
* Clock: 300MHz LVDS
*/
input wire clk_300mhz_p,
input wire clk_300mhz_n,
/*
* GPIO
*/
output wire [1:0] user_led_g,
output wire user_led_r,
output wire [1:0] front_led,
input wire [1:0] user_sw,
/*
* Ethernet: QSFP28
*/
output wire qsfp_0_tx_0_p,
output wire qsfp_0_tx_0_n,
input wire qsfp_0_rx_0_p,
input wire qsfp_0_rx_0_n,
output wire qsfp_0_tx_1_p,
output wire qsfp_0_tx_1_n,
input wire qsfp_0_rx_1_p,
input wire qsfp_0_rx_1_n,
output wire qsfp_0_tx_2_p,
output wire qsfp_0_tx_2_n,
input wire qsfp_0_rx_2_p,
input wire qsfp_0_rx_2_n,
output wire qsfp_0_tx_3_p,
output wire qsfp_0_tx_3_n,
input wire qsfp_0_rx_3_p,
input wire qsfp_0_rx_3_n,
input wire qsfp_0_mgt_refclk_p,
input wire qsfp_0_mgt_refclk_n,
input wire qsfp_0_modprs_l,
output wire qsfp_0_sel_l,
output wire qsfp_1_tx_0_p,
output wire qsfp_1_tx_0_n,
input wire qsfp_1_rx_0_p,
input wire qsfp_1_rx_0_n,
output wire qsfp_1_tx_1_p,
output wire qsfp_1_tx_1_n,
input wire qsfp_1_rx_1_p,
input wire qsfp_1_rx_1_n,
output wire qsfp_1_tx_2_p,
output wire qsfp_1_tx_2_n,
input wire qsfp_1_rx_2_p,
input wire qsfp_1_rx_2_n,
output wire qsfp_1_tx_3_p,
output wire qsfp_1_tx_3_n,
input wire qsfp_1_rx_3_p,
input wire qsfp_1_rx_3_n,
input wire qsfp_1_mgt_refclk_p,
input wire qsfp_1_mgt_refclk_n,
input wire qsfp_1_modprs_l,
output wire qsfp_1_sel_l,
output wire qsfp_reset_l,
input wire qsfp_int_l
);
// Clock and reset
wire clk_300mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = 1'b0;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_300mhz_ibufg_inst (
.O (clk_300mhz_ibufg),
.I (clk_300mhz_p),
.IB (clk_300mhz_n)
);
// MMCM instance
// 300 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 10, D = 3 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(3),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(3.333),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_300mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [1:0] user_sw_int;
debounce_switch #(
.WIDTH(2),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({user_sw}),
.out({user_sw_int})
);
// XGMII 10G PHY
assign qsfp_reset_l = 1'b1;
// QSFP 0
assign qsfp_0_sel_l = 1'b0;
wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [63:0] qsfp_0_txd_0_int;
wire [7:0] qsfp_0_txc_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [63:0] qsfp_0_rxd_0_int;
wire [7:0] qsfp_0_rxc_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [63:0] qsfp_0_txd_1_int;
wire [7:0] qsfp_0_txc_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [63:0] qsfp_0_rxd_1_int;
wire [7:0] qsfp_0_rxc_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [63:0] qsfp_0_txd_2_int;
wire [7:0] qsfp_0_txc_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [63:0] qsfp_0_rxd_2_int;
wire [7:0] qsfp_0_rxc_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [63:0] qsfp_0_txd_3_int;
wire [7:0] qsfp_0_txc_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [63:0] qsfp_0_rxd_3_int;
wire [7:0] qsfp_0_rxc_3_int;
assign clk_156mhz_int = qsfp_0_tx_clk_0_int;
assign rst_156mhz_int = qsfp_0_tx_rst_0_int;
wire qsfp_0_rx_block_lock_0;
wire qsfp_0_rx_block_lock_1;
wire qsfp_0_rx_block_lock_2;
wire qsfp_0_rx_block_lock_3;
wire qsfp_0_mgt_refclk;
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
.I (qsfp_0_mgt_refclk_p),
.IB (qsfp_0_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_0_mgt_refclk),
.ODIV2 ()
);
wire qsfp_0_qpll0lock;
wire qsfp_0_qpll0outclk;
wire qsfp_0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_0_phy_0_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_0_tx_0_p),
.xcvr_txn(qsfp_0_tx_0_n),
.xcvr_rxp(qsfp_0_rx_0_p),
.xcvr_rxn(qsfp_0_rx_0_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_0_int),
.phy_tx_rst(qsfp_0_tx_rst_0_int),
.phy_xgmii_txd(qsfp_0_txd_0_int),
.phy_xgmii_txc(qsfp_0_txc_0_int),
.phy_rx_clk(qsfp_0_rx_clk_0_int),
.phy_rx_rst(qsfp_0_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_0_rxd_0_int),
.phy_xgmii_rxc(qsfp_0_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_1_p),
.xcvr_txn(qsfp_0_tx_1_n),
.xcvr_rxp(qsfp_0_rx_1_p),
.xcvr_rxn(qsfp_0_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_1_int),
.phy_tx_rst(qsfp_0_tx_rst_1_int),
.phy_xgmii_txd(qsfp_0_txd_1_int),
.phy_xgmii_txc(qsfp_0_txc_1_int),
.phy_rx_clk(qsfp_0_rx_clk_1_int),
.phy_rx_rst(qsfp_0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_0_rxd_1_int),
.phy_xgmii_rxc(qsfp_0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_2_p),
.xcvr_txn(qsfp_0_tx_2_n),
.xcvr_rxp(qsfp_0_rx_2_p),
.xcvr_rxn(qsfp_0_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_2_int),
.phy_tx_rst(qsfp_0_tx_rst_2_int),
.phy_xgmii_txd(qsfp_0_txd_2_int),
.phy_xgmii_txc(qsfp_0_txc_2_int),
.phy_rx_clk(qsfp_0_rx_clk_2_int),
.phy_rx_rst(qsfp_0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_0_rxd_2_int),
.phy_xgmii_rxc(qsfp_0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_3_p),
.xcvr_txn(qsfp_0_tx_3_n),
.xcvr_rxp(qsfp_0_rx_3_p),
.xcvr_rxn(qsfp_0_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_3_int),
.phy_tx_rst(qsfp_0_tx_rst_3_int),
.phy_xgmii_txd(qsfp_0_txd_3_int),
.phy_xgmii_txc(qsfp_0_txc_3_int),
.phy_rx_clk(qsfp_0_rx_clk_3_int),
.phy_rx_rst(qsfp_0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_0_rxd_3_int),
.phy_xgmii_rxc(qsfp_0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// QSFP 1
assign qsfp_1_sel_l = 1'b0;
wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [63:0] qsfp_1_txd_0_int;
wire [7:0] qsfp_1_txc_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [63:0] qsfp_1_rxd_0_int;
wire [7:0] qsfp_1_rxc_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [63:0] qsfp_1_txd_1_int;
wire [7:0] qsfp_1_txc_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [63:0] qsfp_1_rxd_1_int;
wire [7:0] qsfp_1_rxc_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [63:0] qsfp_1_txd_2_int;
wire [7:0] qsfp_1_txc_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [63:0] qsfp_1_rxd_2_int;
wire [7:0] qsfp_1_rxc_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [63:0] qsfp_1_txd_3_int;
wire [7:0] qsfp_1_txc_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [63:0] qsfp_1_rxd_3_int;
wire [7:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_block_lock_0;
wire qsfp_1_rx_block_lock_1;
wire qsfp_1_rx_block_lock_2;
wire qsfp_1_rx_block_lock_3;
wire qsfp_1_mgt_refclk;
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
.I (qsfp_1_mgt_refclk_p),
.IB (qsfp_1_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_1_mgt_refclk),
.ODIV2 ()
);
wire qsfp_1_qpll0lock;
wire qsfp_1_qpll0outclk;
wire qsfp_1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp_1_phy_0_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp_1_tx_0_p),
.xcvr_txn(qsfp_1_tx_0_n),
.xcvr_rxp(qsfp_1_rx_0_p),
.xcvr_rxn(qsfp_1_rx_0_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_0_int),
.phy_tx_rst(qsfp_1_tx_rst_0_int),
.phy_xgmii_txd(qsfp_1_txd_0_int),
.phy_xgmii_txc(qsfp_1_txc_0_int),
.phy_rx_clk(qsfp_1_rx_clk_0_int),
.phy_rx_rst(qsfp_1_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_1_rxd_0_int),
.phy_xgmii_rxc(qsfp_1_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_1_p),
.xcvr_txn(qsfp_1_tx_1_n),
.xcvr_rxp(qsfp_1_rx_1_p),
.xcvr_rxn(qsfp_1_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_1_int),
.phy_tx_rst(qsfp_1_tx_rst_1_int),
.phy_xgmii_txd(qsfp_1_txd_1_int),
.phy_xgmii_txc(qsfp_1_txc_1_int),
.phy_rx_clk(qsfp_1_rx_clk_1_int),
.phy_rx_rst(qsfp_1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_1_rxd_1_int),
.phy_xgmii_rxc(qsfp_1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_2_p),
.xcvr_txn(qsfp_1_tx_2_n),
.xcvr_rxp(qsfp_1_rx_2_p),
.xcvr_rxn(qsfp_1_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_2_int),
.phy_tx_rst(qsfp_1_tx_rst_2_int),
.phy_xgmii_txd(qsfp_1_txd_2_int),
.phy_xgmii_txc(qsfp_1_txc_2_int),
.phy_rx_clk(qsfp_1_rx_clk_2_int),
.phy_rx_rst(qsfp_1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_1_rxd_2_int),
.phy_xgmii_rxc(qsfp_1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp_1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_3_p),
.xcvr_txn(qsfp_1_tx_3_n),
.xcvr_rxp(qsfp_1_rx_3_p),
.xcvr_rxn(qsfp_1_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_3_int),
.phy_tx_rst(qsfp_1_tx_rst_3_int),
.phy_xgmii_txd(qsfp_1_txd_3_int),
.phy_xgmii_txc(qsfp_1_txc_3_int),
.phy_rx_clk(qsfp_1_rx_clk_3_int),
.phy_rx_rst(qsfp_1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_1_rxd_3_int),
.phy_xgmii_rxc(qsfp_1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
assign front_led[0] = qsfp_0_rx_block_lock_0;
assign front_led[1] = qsfp_1_rx_block_lock_0;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.user_led_g(user_led_g),
.user_led_r(user_led_r),
//.front_led(front_led),
.user_sw(user_sw_int),
/*
* Ethernet: QSFP28
*/
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
);
endmodule |
module fpga_core #
(
parameter AXIS_PCIE_DATA_WIDTH = 512,
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
parameter AXIS_PCIE_RC_USER_WIDTH = 161,
parameter AXIS_PCIE_RQ_USER_WIDTH = 137,
parameter AXIS_PCIE_CQ_USER_WIDTH = 183,
parameter AXIS_PCIE_CC_USER_WIDTH = 81,
parameter RQ_SEQ_NUM_WIDTH = 6,
parameter BAR0_APERTURE = 24
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* PCIe
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tlast,
input wire m_axis_rq_tready,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
output wire m_axis_rq_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tlast,
output wire s_axis_rc_tready,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
input wire s_axis_rc_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tlast,
output wire s_axis_cq_tready,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
input wire s_axis_cq_tvalid,
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tlast,
input wire m_axis_cc_tready,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
output wire m_axis_cc_tvalid,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
input wire [3:0] cfg_interrupt_msi_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor,
output wire status_error_uncor
);
dma_bench_pcie_us #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.PCIE_TAG_COUNT(64),
.PCIE_DMA_READ_OP_TABLE_SIZE(64),
.PCIE_DMA_READ_TX_LIMIT(32),
.PCIE_DMA_READ_TX_FC_ENABLE(1),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(32),
.PCIE_DMA_WRITE_TX_LIMIT(4),
.PCIE_DMA_WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE)
)
dma_bench_pcie_us_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(8'd0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module fpga_core #
(
parameter AXIS_PCIE_DATA_WIDTH = 512,
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
parameter AXIS_PCIE_RC_USER_WIDTH = 161,
parameter AXIS_PCIE_RQ_USER_WIDTH = 137,
parameter AXIS_PCIE_CQ_USER_WIDTH = 183,
parameter AXIS_PCIE_CC_USER_WIDTH = 81,
parameter RQ_SEQ_NUM_WIDTH = 6,
parameter BAR0_APERTURE = 24
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] sw,
output wire [2:0] led,
/*
* PCIe
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep,
output wire m_axis_rq_tlast,
input wire m_axis_rq_tready,
output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
output wire m_axis_rq_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tlast,
output wire s_axis_rc_tready,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
input wire s_axis_rc_tvalid,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep,
input wire s_axis_cq_tlast,
output wire s_axis_cq_tready,
input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
input wire s_axis_cq_tvalid,
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tlast,
input wire m_axis_cc_tready,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
output wire m_axis_cc_tvalid,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0,
input wire s_axis_rq_seq_num_valid_0,
input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1,
input wire s_axis_rq_seq_num_valid_1,
input wire [7:0] cfg_fc_ph,
input wire [11:0] cfg_fc_pd,
input wire [7:0] cfg_fc_nph,
input wire [11:0] cfg_fc_npd,
input wire [7:0] cfg_fc_cplh,
input wire [11:0] cfg_fc_cpld,
output wire [2:0] cfg_fc_sel,
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
output wire cfg_mgmt_write,
output wire [31:0] cfg_mgmt_write_data,
output wire [3:0] cfg_mgmt_byte_enable,
output wire cfg_mgmt_read,
input wire [31:0] cfg_mgmt_read_data,
input wire cfg_mgmt_read_write_done,
input wire [3:0] cfg_interrupt_msi_enable,
input wire [11:0] cfg_interrupt_msi_mmenable,
input wire cfg_interrupt_msi_mask_update,
input wire [31:0] cfg_interrupt_msi_data,
output wire [3:0] cfg_interrupt_msi_select,
output wire [31:0] cfg_interrupt_msi_int,
output wire [31:0] cfg_interrupt_msi_pending_status,
output wire cfg_interrupt_msi_pending_status_data_enable,
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
input wire cfg_interrupt_msi_sent,
input wire cfg_interrupt_msi_fail,
output wire [2:0] cfg_interrupt_msi_attr,
output wire cfg_interrupt_msi_tph_present,
output wire [1:0] cfg_interrupt_msi_tph_type,
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
output wire [3:0] cfg_interrupt_msi_function_number,
output wire status_error_cor,
output wire status_error_uncor
);
assign led = 3'd0;
dma_bench_pcie_us #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.RQ_SEQ_NUM_ENABLE(1),
.PCIE_TAG_COUNT(64),
.PCIE_DMA_READ_OP_TABLE_SIZE(64),
.PCIE_DMA_READ_TX_LIMIT(32),
.PCIE_DMA_READ_TX_FC_ENABLE(1),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(32),
.PCIE_DMA_WRITE_TX_LIMIT(4),
.PCIE_DMA_WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE)
)
dma_bench_pcie_us_inst (
.clk(clk),
.rst(rst),
/*
* AXI input (RC)
*/
.s_axis_rc_tdata(s_axis_rc_tdata),
.s_axis_rc_tkeep(s_axis_rc_tkeep),
.s_axis_rc_tvalid(s_axis_rc_tvalid),
.s_axis_rc_tready(s_axis_rc_tready),
.s_axis_rc_tlast(s_axis_rc_tlast),
.s_axis_rc_tuser(s_axis_rc_tuser),
/*
* AXI output (RQ)
*/
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),
.m_axis_rq_tready(m_axis_rq_tready),
.m_axis_rq_tlast(m_axis_rq_tlast),
.m_axis_rq_tuser(m_axis_rq_tuser),
/*
* AXI input (CQ)
*/
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
/*
* AXI output (CC)
*/
.m_axis_cc_tdata(m_axis_cc_tdata),
.m_axis_cc_tkeep(m_axis_cc_tkeep),
.m_axis_cc_tvalid(m_axis_cc_tvalid),
.m_axis_cc_tready(m_axis_cc_tready),
.m_axis_cc_tlast(m_axis_cc_tlast),
.m_axis_cc_tuser(m_axis_cc_tuser),
/*
* Transmit sequence number input
*/
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
/*
* Flow control
*/
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
/*
* Configuration
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
/*
* Configuration interface
*/
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
/*
* Interrupt interface
*/
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_vf_enable(8'd0),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
/*
* Status
*/
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module fpga (
/*
* GPIO
*/
output wire qsfp_led_act,
output wire qsfp_led_stat_g,
output wire qsfp_led_stat_y,
output wire hbm_cattrip,
/*
* PCI express
*/
input wire [15:0] pcie_rx_p,
input wire [15:0] pcie_rx_n,
output wire [15:0] pcie_tx_p,
output wire [15:0] pcie_tx_n,
input wire pcie_refclk_1_p,
input wire pcie_refclk_1_n,
input wire pcie_reset_n
);
parameter AXIS_PCIE_DATA_WIDTH = 512;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
parameter AXIS_PCIE_RC_USER_WIDTH = 161;
parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
parameter AXIS_PCIE_CC_USER_WIDTH = 81;
parameter RQ_SEQ_NUM_WIDTH = 6;
parameter BAR0_APERTURE = 24;
// Clock and reset
wire pcie_user_clk;
wire pcie_user_reset;
// GPIO
assign hbm_cattrip = 1'b0;
// PCIe
wire pcie_sys_clk;
wire pcie_sys_clk_gt;
IBUFDS_GTE4 #(
.REFCLK_HROW_CK_SEL(2'b00)
)
ibufds_gte4_pcie_mgt_refclk_inst (
.I (pcie_refclk_1_p),
.IB (pcie_refclk_1_n),
.CEB (1'b0),
.O (pcie_sys_clk_gt),
.ODIV2 (pcie_sys_clk)
);
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep;
wire axis_rq_tlast;
wire axis_rq_tready;
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
wire axis_rq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep;
wire axis_rc_tlast;
wire axis_rc_tready;
wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
wire axis_rc_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep;
wire axis_cq_tlast;
wire axis_cq_tready;
wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
wire axis_cq_tvalid;
wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep;
wire axis_cc_tlast;
wire axis_cc_tready;
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
wire axis_cc_tvalid;
// ila_0 rq_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rq_tdata),
// .probe1(axis_rq_tkeep),
// .probe2(axis_rq_tlast),
// .probe3(axis_rq_tready),
// .probe4(axis_rq_tuser),
// .probe5(axis_rq_tvalid)
// );
// ila_0 rc_ila (
// .clk(pcie_user_clk),
// .probe0(axis_rc_tdata),
// .probe1(axis_rc_tkeep),
// .probe2(axis_rc_tlast),
// .probe3(axis_rc_tready),
// .probe4(axis_rc_tuser),
// .probe5(axis_rc_tvalid)
// );
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num_0;
wire pcie_rq_seq_num_valid_0;
wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num_1;
wire pcie_rq_seq_num_valid_1;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
wire cfg_mgmt_write;
wire [31:0] cfg_mgmt_write_data;
wire [3:0] cfg_mgmt_byte_enable;
wire cfg_mgmt_read;
wire [31:0] cfg_mgmt_read_data;
wire cfg_mgmt_read_write_done;
wire [3:0] cfg_interrupt_msi_enable;
wire [11:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [31:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_pending_status_data_enable;
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [3:0] cfg_interrupt_msi_function_number;
wire status_error_cor;
wire status_error_uncor;
pcie4c_uscale_plus_0
pcie4c_uscale_plus_inst (
.pci_exp_txn(pcie_tx_n),
.pci_exp_txp(pcie_tx_p),
.pci_exp_rxn(pcie_rx_n),
.pci_exp_rxp(pcie_rx_p),
.user_clk(pcie_user_clk),
.user_reset(pcie_user_reset),
.user_lnk_up(),
.s_axis_rq_tdata(axis_rq_tdata),
.s_axis_rq_tkeep(axis_rq_tkeep),
.s_axis_rq_tlast(axis_rq_tlast),
.s_axis_rq_tready(axis_rq_tready),
.s_axis_rq_tuser(axis_rq_tuser),
.s_axis_rq_tvalid(axis_rq_tvalid),
.m_axis_rc_tdata(axis_rc_tdata),
.m_axis_rc_tkeep(axis_rc_tkeep),
.m_axis_rc_tlast(axis_rc_tlast),
.m_axis_rc_tready(axis_rc_tready),
.m_axis_rc_tuser(axis_rc_tuser),
.m_axis_rc_tvalid(axis_rc_tvalid),
.m_axis_cq_tdata(axis_cq_tdata),
.m_axis_cq_tkeep(axis_cq_tkeep),
.m_axis_cq_tlast(axis_cq_tlast),
.m_axis_cq_tready(axis_cq_tready),
.m_axis_cq_tuser(axis_cq_tuser),
.m_axis_cq_tvalid(axis_cq_tvalid),
.s_axis_cc_tdata(axis_cc_tdata),
.s_axis_cc_tkeep(axis_cc_tkeep),
.s_axis_cc_tlast(axis_cc_tlast),
.s_axis_cc_tready(axis_cc_tready),
.s_axis_cc_tuser(axis_cc_tuser),
.s_axis_cc_tvalid(axis_cc_tvalid),
.pcie_rq_seq_num0(pcie_rq_seq_num_0),
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_valid_0),
.pcie_rq_seq_num1(pcie_rq_seq_num_1),
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_valid_1),
.pcie_rq_tag0(),
.pcie_rq_tag1(),
.pcie_rq_tag_av(),
.pcie_rq_tag_vld0(),
.pcie_rq_tag_vld1(),
.pcie_tfc_nph_av(),
.pcie_tfc_npd_av(),
.pcie_cq_np_req(1'b1),
.pcie_cq_np_req_count(),
.cfg_phy_link_down(),
.cfg_phy_link_status(),
.cfg_negotiated_width(),
.cfg_current_speed(),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_function_status(),
.cfg_function_power_state(),
.cfg_vf_status(),
.cfg_vf_power_state(),
.cfg_link_power_state(),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_mgmt_debug_access(1'b0),
.cfg_err_cor_out(),
.cfg_err_nonfatal_out(),
.cfg_err_fatal_out(),
.cfg_local_error_valid(),
.cfg_local_error_out(),
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
.cfg_tph_st_mode(),
.cfg_vf_tph_requester_enable(),
.cfg_vf_tph_st_mode(),
.cfg_msg_received(),
.cfg_msg_received_data(),
.cfg_msg_received_type(),
.cfg_msg_transmit(1'b0),
.cfg_msg_transmit_type(3'd0),
.cfg_msg_transmit_data(32'd0),
.cfg_msg_transmit_done(),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_dsn(64'd0),
.cfg_bus_number(),
.cfg_power_state_change_ack(1'b1),
.cfg_power_state_change_interrupt(),
.cfg_err_cor_in(status_error_cor),
.cfg_err_uncor_in(status_error_uncor),
.cfg_flr_in_process(),
.cfg_flr_done(4'd0),
.cfg_vf_flr_in_process(),
.cfg_vf_flr_func_num(8'd0),
.cfg_vf_flr_done(8'd0),
.cfg_link_training_enable(1'b1),
.cfg_interrupt_int(4'd0),
.cfg_interrupt_pending(4'd0),
.cfg_interrupt_sent(),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.cfg_pm_aspm_l1_entry_reject(1'b0),
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
.cfg_hot_reset_out(),
.cfg_config_space_enable(1'b1),
.cfg_req_pm_transition_l23_ready(1'b0),
.cfg_hot_reset_in(1'b0),
.cfg_ds_port_number(8'd0),
.cfg_ds_bus_number(8'd0),
.cfg_ds_device_number(5'd0),
.sys_clk(pcie_sys_clk),
.sys_clk_gt(pcie_sys_clk_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out()
);
fpga_core #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.BAR0_APERTURE(BAR0_APERTURE)
)
core_inst (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk(pcie_user_clk),
.rst(pcie_user_reset),
/*
* GPIO
*/
.qsfp_led_act(qsfp_led_act),
.qsfp_led_stat_g(qsfp_led_stat_g),
.qsfp_led_stat_y(qsfp_led_stat_y),
/*
* PCIe
*/
.m_axis_rq_tdata(axis_rq_tdata),
.m_axis_rq_tkeep(axis_rq_tkeep),
.m_axis_rq_tlast(axis_rq_tlast),
.m_axis_rq_tready(axis_rq_tready),
.m_axis_rq_tuser(axis_rq_tuser),
.m_axis_rq_tvalid(axis_rq_tvalid),
.s_axis_rc_tdata(axis_rc_tdata),
.s_axis_rc_tkeep(axis_rc_tkeep),
.s_axis_rc_tlast(axis_rc_tlast),
.s_axis_rc_tready(axis_rc_tready),
.s_axis_rc_tuser(axis_rc_tuser),
.s_axis_rc_tvalid(axis_rc_tvalid),
.s_axis_cq_tdata(axis_cq_tdata),
.s_axis_cq_tkeep(axis_cq_tkeep),
.s_axis_cq_tlast(axis_cq_tlast),
.s_axis_cq_tready(axis_cq_tready),
.s_axis_cq_tuser(axis_cq_tuser),
.s_axis_cq_tvalid(axis_cq_tvalid),
.m_axis_cc_tdata(axis_cc_tdata),
.m_axis_cc_tkeep(axis_cc_tkeep),
.m_axis_cc_tlast(axis_cc_tlast),
.m_axis_cc_tready(axis_cc_tready),
.m_axis_cc_tuser(axis_cc_tuser),
.m_axis_cc_tvalid(axis_cc_tvalid),
.s_axis_rq_seq_num_0(pcie_rq_seq_num_0),
.s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_valid_0),
.s_axis_rq_seq_num_1(pcie_rq_seq_num_1),
.s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_valid_1),
.cfg_fc_ph(cfg_fc_ph),
.cfg_fc_pd(cfg_fc_pd),
.cfg_fc_nph(cfg_fc_nph),
.cfg_fc_npd(cfg_fc_npd),
.cfg_fc_cplh(cfg_fc_cplh),
.cfg_fc_cpld(cfg_fc_cpld),
.cfg_fc_sel(cfg_fc_sel),
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),
.cfg_mgmt_write(cfg_mgmt_write),
.cfg_mgmt_write_data(cfg_mgmt_write_data),
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
.cfg_mgmt_read(cfg_mgmt_read),
.cfg_mgmt_read_data(cfg_mgmt_read_data),
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
.status_error_cor(status_error_cor),
.status_error_uncor(status_error_uncor)
);
endmodule |
module fpga_core #
(
parameter SEG_COUNT = 1,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PCIE_TAG_COUNT = 256,
parameter BAR0_APERTURE = 24,
parameter BAR2_APERTURE = 24
)
(
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] led_user_grn,
output wire [1:0] led_user_red,
output wire [3:0] led_qsfp,
/*
* H-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
input wire [7:0] tx_ph_cdts,
input wire [11:0] tx_pd_cdts,
input wire [7:0] tx_nph_cdts,
input wire [11:0] tx_npd_cdts,
input wire [7:0] tx_cplh_cdts,
input wire [11:0] tx_cpld_cdts,
input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
input wire [31:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [1:0] tl_cfg_func
);
assign led_user_grn = 0;
assign led_user_red = 0;
assign led_qsfp = 0;
dma_bench_pcie_s10 #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(1),
.L_TILE(0),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
.PCIE_DMA_READ_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.PCIE_DMA_READ_TX_FC_ENABLE(1),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(2**TX_SEQ_NUM_WIDTH),
.PCIE_DMA_WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
.PCIE_DMA_WRITE_TX_FC_ENABLE(1),
.BAR0_APERTURE(BAR0_APERTURE)
)
dma_bench_pcie_s10_inst (
.clk(clk),
.rst(rst),
/*
* H-tile RX AVST interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
/*
* H-tile TX AVST interface
*/
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
/*
* H-tile TX flow control
*/
.tx_ph_cdts(tx_ph_cdts),
.tx_pd_cdts(tx_pd_cdts),
.tx_nph_cdts(tx_nph_cdts),
.tx_npd_cdts(tx_npd_cdts),
.tx_cplh_cdts(tx_cplh_cdts),
.tx_cpld_cdts(tx_cpld_cdts),
.tx_hdr_cdts_consumed(tx_hdr_cdts_consumed),
.tx_data_cdts_consumed(tx_data_cdts_consumed),
.tx_cdts_type(tx_cdts_type),
.tx_cdts_data_value(tx_cdts_data_value),
/*
* H-tile MSI interrupt interface
*/
.app_msi_req(app_msi_req),
.app_msi_ack(app_msi_ack),
.app_msi_tc(app_msi_tc),
.app_msi_num(app_msi_num),
.app_msi_func_num(app_msi_func_num),
/*
* H-tile configuration interface
*/
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* Status
*/
.status_error_cor(),
.status_error_uncor()
);
endmodule |
module user_tx_wr_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_pipelined,
output wire user_tx_wr_if_empty,
input wire set_if_mem_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire writes_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_wr_addr,
input wire [USER_TAG-1:0] um_tx_wr_tag,
input wire [511:0] um_tx_data,
input wire um_tx_wr_valid,
output wire um_tx_wr_ready,
// User Module RX RD
output reg [USER_TAG-1:0] um_rx_wr_tag,
output reg um_rx_wr_valid,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_wr_valid,
output wire [57:0] usr_arb_tx_wr_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_wr_tag,
output wire [511:0] usr_arb_tx_data,
input wire usr_arb_tx_wr_ready,
input wire usr_arb_rx_wr_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_wr_tag,
output wire [57:0] wif_tx_rd_addr,
output wire [`IF_TAG-1:0] wif_tx_rd_tag,
output wire wif_tx_rd_valid,
input wire wif_tx_rd_ready,
input wire [`IF_TAG-1:0] wif_rx_rd_tag,
input wire [511:0] wif_rx_data,
input wire wif_rx_rd_valid,
//-------------------- To pipeline reader ---------------------------//
input wire usr_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
output wire usr_pipe_tx_rd_ready,
output reg usr_pipe_rx_rd_valid,
output reg [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
output reg [511:0] usr_pipe_rx_data,
input wire usr_pipe_rx_rd_ready
);
wire [512+57+USER_TAG:0] tx_wr_fifo_dout;
wire tx_wr_fifo_valid;
wire tx_wr_fifo_full;
wire tx_wr_fifo_re;
wire tx_wr_fifo_empty;
wire [`IF_TAG-1:0] pipe_rd_pending_fifo_tag;
wire pipe_rd_pending_fifo_valid;
wire pipe_rd_pending_fifo_full;
wire fifo_tx_wr_valid;
wire [57:0] fifo_tx_wr_addr;
wire [USER_TAG+1:0] fifo_tx_wr_tag;
wire [511:0] fifo_tx_data;
wire fifo_tx_wr_ready;
wire [USER_TAG+1:0] fifo_rx_wr_tag;
wire fifo_rx_wr_valid;
wire usr_tx_wr_ready;
wire [USER_TAG-1:0] usr_rx_wr_tag;
wire usr_rx_wr_valid;
wire fifo_done;
reg wr_if_pipelined = 0;
reg in_memory_pipeline = 0;
reg [57:0] fifo_base_addr;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
wr_if_pipelined <= 0;
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
end
else begin
if(set_if_pipelined) begin
wr_if_pipelined <= 1'b1;
end
fifo_base_addr <= mem_pipeline_addr;
if(fifo_done) begin
in_memory_pipeline <= 1'b0;
end
else if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
end
end
end
assign user_tx_wr_if_empty = (in_memory_pipeline)? fifo_done : tx_wr_fifo_empty & ~fifo_tx_wr_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Writer Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(512 + 58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_wr_tag, um_tx_wr_addr, um_tx_data}),
.we (um_tx_wr_valid),
.re (tx_wr_fifo_re),
.dout (tx_wr_fifo_dout),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_fifo_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_wr_ready = ~tx_wr_fifo_full;
assign tx_wr_fifo_re = (wr_if_pipelined)? usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid : usr_tx_wr_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Pass through in-memory FIFO
sw_fifo_writer #(.USER_TAG(USER_TAG) )
sw_fifo_writer(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.setup_fifo (in_memory_pipeline & ~fifo_done),
.writes_finished (writes_finished & tx_wr_fifo_empty),
.fifo_done (fifo_done),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_rd_addr (wif_tx_rd_addr),
.fifo_tx_rd_tag (wif_tx_rd_tag),
.fifo_tx_rd_valid (wif_tx_rd_valid),
.fifo_tx_rd_ready (wif_tx_rd_ready),
// TX WR
.fifo_tx_wr_addr (fifo_tx_wr_addr),
.fifo_tx_wr_tag (fifo_tx_wr_tag),
.fifo_tx_wr_valid (fifo_tx_wr_valid),
.fifo_tx_data (fifo_tx_data),
.fifo_tx_wr_ready (fifo_tx_wr_ready),
// RX RD
.fifo_rx_rd_tag (wif_rx_rd_tag),
.fifo_rx_data (wif_rx_data),
.fifo_rx_rd_valid (wif_rx_rd_valid),
// RX WR
.fifo_rx_wr_valid (fifo_rx_wr_valid),
.fifo_rx_wr_tag (fifo_rx_wr_tag),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_wr_tag (tx_wr_fifo_dout[512+57+USER_TAG:570]),
.usr_tx_wr_valid (tx_wr_fifo_valid & ~wr_if_pipelined),
.usr_tx_wr_addr (tx_wr_fifo_dout[569:512]),
.usr_tx_data (tx_wr_fifo_dout[511:0]),
.usr_tx_wr_ready (usr_tx_wr_ready),
.usr_rx_wr_tag (usr_rx_wr_tag),
.usr_rx_wr_valid (usr_rx_wr_valid)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure_wr #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_wr_addr (fifo_tx_wr_addr),
.usr_tx_wr_tag (fifo_tx_wr_tag),
.usr_tx_wr_valid (fifo_tx_wr_valid),
.usr_tx_data (fifo_tx_data),
.usr_tx_wr_ready (fifo_tx_wr_ready),
// TX RD
.ord_tx_wr_addr (usr_arb_tx_wr_addr),
.ord_tx_wr_tag (usr_arb_tx_wr_tag),
.ord_tx_wr_valid (usr_arb_tx_wr_valid),
.ord_tx_data (usr_arb_tx_data),
.ord_tx_wr_ready (usr_arb_tx_wr_ready),
// RX RD
.ord_rx_wr_tag (usr_arb_rx_wr_tag[7:0]),
.ord_rx_wr_valid (usr_arb_rx_wr_valid),
//
.usr_rx_wr_tag (fifo_rx_wr_tag),
.usr_rx_wr_valid (fifo_rx_wr_valid),
.usr_rx_wr_ready (1'b1)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe RX RD
// data, tag
always @(posedge clk) begin
if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_tag <= pipe_rd_pending_fifo_tag;
usr_pipe_rx_data <= tx_wr_fifo_dout[511:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
usr_pipe_rx_rd_valid <= 0;
end
else if(usr_pipe_rx_rd_ready) begin
usr_pipe_rx_rd_valid <= pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
end
//--------------------------------------------//
// pipe_rd_pending_fifo
quick_fifo #(.FIFO_WIDTH(`IF_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) pipe_rd_pending_fifo(
.clk (clk),
.reset_n (rst_n),
.din (usr_pipe_tx_rd_tag),
.we (usr_pipe_tx_rd_valid & wr_if_pipelined),
.re (tx_wr_fifo_valid & usr_pipe_rx_rd_ready),
.dout (pipe_rd_pending_fifo_tag),
.empty (),
.valid (pipe_rd_pending_fifo_valid),
.full (pipe_rd_pending_fifo_full),
.count (),
.almostfull ()
);
assign usr_pipe_tx_rd_ready = ~pipe_rd_pending_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Write Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// tag
always @(posedge clk) begin
if (wr_if_pipelined) begin
um_rx_wr_tag <= tx_wr_fifo_dout[512+57+USER_TAG:570];
end
else begin
um_rx_wr_tag <= fifo_rx_wr_tag;//[USER_TAG-1:0];
end
end
// valid
always @(posedge clk) begin
if (~rst_n) begin
// reset
um_rx_wr_valid <= 0;
end
else if (wr_if_pipelined) begin
um_rx_wr_valid <= usr_pipe_rx_rd_ready & pipe_rd_pending_fifo_valid & tx_wr_fifo_valid;
end
else begin
um_rx_wr_valid <= usr_rx_wr_valid;
end
end
endmodule |
module sw_fifo_reader #(parameter POLL_CYCLES = 32,
parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire [57:0] fifo_base_addr,
input wire [3:0] fifo_addr_code,
input wire setup_fifo,
input wire reads_finished,
//--------------------- FIFO to QPI ----------------//
// TX RD
output reg [57:0] fifo_tx_rd_addr,
output reg [2+USER_TAG-1:0] fifo_tx_rd_tag,
output reg fifo_tx_rd_valid,
input wire fifo_tx_rd_ready,
// TX WR
output reg [57:0] fifo_tx_wr_addr,
output reg [`IF_TAG-1:0] fifo_tx_wr_tag,
output reg fifo_tx_wr_valid,
output reg [511:0] fifo_tx_data,
input wire fifo_tx_wr_ready,
// RX RD
input wire [2+USER_TAG-1:0] fifo_rx_rd_tag,
input wire [511:0] fifo_rx_data,
input wire fifo_rx_rd_valid,
output wire fifo_rx_rd_ready,
// RX WR
input wire fifo_rx_wr_valid,
input wire [`IF_TAG-1:0] fifo_rx_wr_tag,
///////////////////////// User Logic Interface ////////////////////
input wire [USER_TAG-1:0] usr_tx_rd_tag,
input wire usr_tx_rd_valid,
input wire [57:0] usr_tx_rd_addr,
output wire usr_tx_rd_ready,
output reg [USER_TAG-1:0] usr_rx_rd_tag,
output reg [511:0] usr_rx_data,
output reg usr_rx_rd_valid,
input wire usr_rx_rd_ready
);
///////////////////////////////// Wires Declarations ////////////////////////////
wire update_status;
wire poll_again;
wire data_available;
/////////////////////////////////////// Reg Declarations /////////////////////////
reg [31:0] numPulledCLs;
reg [31:0] otherSideUpdatedBytes;
reg [31:0] sizeInNumCL;
reg [31:0] usr_rd_count;
reg [31:0] poll_count;
reg [57:0] fifo_buff_addr;
reg [57:0] fifo_struct_base;
reg [1:0] fifo_fsm_state;
reg [1:0] poll_fsm_state;
reg update_set;
reg [57:0] poll_rd_addr;
reg poll_rd_valid;
wire poll_rd_ready;
wire [511:0] poll_rx_data;
wire poll_rx_valid;
reg [31:0] readBytes;
reg [31:0] update_status_threashold;
reg write_response_pending;
reg [31:0] lastUpdatedBytes;
reg mem_pipeline;
reg [3:0] fifo_addr_code_reg;
wire mem_fifo_valid;
reg mem_fifo_re;
wire mem_fifo_full;
wire [57+USER_TAG:0] mem_fifo_dout;
wire pipe_fifo_valid;
wire pipe_fifo_re;
wire pipe_fifo_full;
wire pipe_fifo_empty;
wire [USER_TAG-1:0] pipe_fifo_dout;
/////////////////////////////////// Local Parameters /////////////////////////////////////////
localparam [1:0]
FIFO_IDLE_STATE = 2'b00,
FIFO_REQUEST_CONFIG_STATE = 2'b01,
FIFO_READ_CONFIG_STATE = 2'b10,
FIFO_RUN_STATE = 2'b11;
localparam [1:0]
POLL_IDLE_STATE = 2'b00,
POLL_REQUEST_STATE = 2'b01,
POLL_RESP_STATE = 2'b10,
POLL_VALID_STATE = 2'b11;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Reader Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) pipe_fifo(
.clk (clk),
.reset_n (rst_n),
.din (mem_fifo_dout[57+USER_TAG:58]),
.we (mem_fifo_valid & mem_pipeline & (mem_fifo_dout[57:54] == fifo_addr_code_reg)),
.re (pipe_fifo_re),
.dout (pipe_fifo_dout),
.empty (pipe_fifo_empty),
.valid (pipe_fifo_valid),
.full (pipe_fifo_full),
.count (),
.almostfull ()
);
quick_fifo #(.FIFO_WIDTH(58+USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) mem_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({usr_tx_rd_tag, usr_tx_rd_addr}),
.we (usr_tx_rd_valid),
.re (mem_fifo_re),
.dout (mem_fifo_dout),
.empty (),
.valid (mem_fifo_valid),
.full (mem_fifo_full),
.count (),
.almostfull ()
);
assign usr_tx_rd_ready = ~mem_fifo_full;
assign pipe_fifo_re = fifo_tx_rd_ready & data_available & ~poll_rd_valid;
always @(posedge clk) begin
if(~rst_n) begin
mem_pipeline <= 0;
fifo_addr_code_reg <= 0;
end
else if(setup_fifo) begin
mem_pipeline <= 1'b1;
fifo_addr_code_reg <= fifo_addr_code;
end
end
always @(*) begin
if( mem_pipeline ) begin
if( fifo_fsm_state == FIFO_RUN_STATE ) begin
if(mem_fifo_dout[57:54] == fifo_addr_code_reg) begin
mem_fifo_re <= ~pipe_fifo_full;
end
else if(fifo_tx_rd_ready & (~pipe_fifo_empty | poll_rd_valid)) begin
mem_fifo_re <= 0;
end
else begin
mem_fifo_re <= fifo_tx_rd_ready;
end
end
else begin
mem_fifo_re <= 0;
end
end
else begin
mem_fifo_re <= fifo_tx_rd_ready;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// FIFO Polling Logic /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if(~rst_n | reads_finished) begin
otherSideUpdatedBytes <= 0;
poll_fsm_state <= 0;
poll_count <= 0;
poll_rd_addr <= 0;
poll_rd_valid <= 0;
end
else begin
case (poll_fsm_state)
POLL_IDLE_STATE: begin
if (fifo_fsm_state == FIFO_RUN_STATE) begin
poll_fsm_state <= POLL_RESP_STATE;
poll_rd_addr <= fifo_struct_base + `CRB_STRUCT_PRODUCER_LINE_OFFSET;
poll_rd_valid <= 1'b1;
end
end
POLL_REQUEST_STATE: begin // This state enable reading the producer status line
if( poll_count == POLL_CYCLES) begin
poll_rd_valid <= 1'b1;
poll_fsm_state <= POLL_RESP_STATE;
end
poll_count <= poll_count + 1'b1;
end
POLL_RESP_STATE: begin
if(poll_rd_ready) poll_rd_valid <= 1'b0;
if(poll_rx_valid) begin
poll_fsm_state <= POLL_VALID_STATE;
otherSideUpdatedBytes <= poll_rx_data[63:32];
end
poll_count <= 0;
end
POLL_VALID_STATE: begin
if(poll_again) begin
poll_fsm_state <= POLL_REQUEST_STATE;
end
end
endcase
end
end
/////////////////////////////// FIFO Status Logic /////////////////////////////////
assign poll_again = (otherSideUpdatedBytes >> 6) == numPulledCLs;
assign data_available = (otherSideUpdatedBytes >> 6) > numPulledCLs;
assign poll_rd_ready = (fifo_fsm_state == FIFO_RUN_STATE) & fifo_tx_rd_ready;
always @(posedge clk) begin
if(~rst_n) begin
sizeInNumCL <= 0;
fifo_buff_addr <= 0;
fifo_struct_base <= 0;
usr_rd_count <= 0;
fifo_fsm_state <= 0;
numPulledCLs <= 0;
fifo_tx_rd_valid <= 0;
fifo_tx_rd_addr <= 0;
fifo_tx_rd_tag <= 0;
end
else begin
case (fifo_fsm_state)
FIFO_IDLE_STATE: begin
if (setup_fifo) begin
fifo_fsm_state <= FIFO_REQUEST_CONFIG_STATE;
fifo_struct_base <= fifo_base_addr;
end
if(fifo_tx_rd_ready) begin
fifo_tx_rd_valid <= mem_fifo_valid;
fifo_tx_rd_addr <= mem_fifo_dout[57:0];
fifo_tx_rd_tag <= {2'b00, mem_fifo_dout[57+USER_TAG:58]};
end
end
FIFO_REQUEST_CONFIG_STATE: begin // This state enable reading the CRB configuration line
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= fifo_struct_base;
fifo_tx_rd_tag <= {2'b11, {USER_TAG{1'b0}}};
fifo_fsm_state <= FIFO_READ_CONFIG_STATE;
end
FIFO_READ_CONFIG_STATE: begin // This state enable reading the CRB configuration line
if(fifo_tx_rd_ready) fifo_tx_rd_valid <= 1'b0;
if(fifo_rx_rd_valid) fifo_fsm_state <= FIFO_RUN_STATE;
fifo_buff_addr <= fifo_rx_data[63:6];
sizeInNumCL <= (fifo_rx_data[127:96] >> 6) - 1;
update_status_threashold <= fifo_rx_data[159:128];
end
FIFO_RUN_STATE: begin // This state enable writing user generated to the Buffer
if(reads_finished) begin
fifo_fsm_state <= FIFO_IDLE_STATE;
end
if(fifo_tx_rd_ready) begin
if(poll_rd_valid) begin
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= poll_rd_addr;
fifo_tx_rd_tag <= {2'b11, {USER_TAG{1'b0}}};
end
else if(~pipe_fifo_empty) begin
if(data_available & pipe_fifo_valid) begin
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= fifo_buff_addr + usr_rd_count;
fifo_tx_rd_tag <= {2'b01, pipe_fifo_dout};
if(usr_rd_count == sizeInNumCL) begin
usr_rd_count <= 0;
end
else begin
usr_rd_count <= usr_rd_count + 1'b1;
end
numPulledCLs <= numPulledCLs + 1'b1;
end
else begin
fifo_tx_rd_valid <= 1'b0;
end
end
else if(mem_fifo_dout[57:54] != fifo_addr_code_reg) begin
fifo_tx_rd_valid <= mem_fifo_valid;
fifo_tx_rd_addr <= mem_fifo_dout[57:0];
fifo_tx_rd_tag <= {2'b00, mem_fifo_dout[57+USER_TAG:58]};
end
else begin
fifo_tx_rd_valid <= 1'b0;
end
end
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////
////////// RX RD
//////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
usr_rx_rd_valid <= 1'b0;
end
else if( usr_rx_rd_ready ) begin
usr_rx_rd_valid <= fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1];
end
end
always@(posedge clk) begin
if( usr_rx_rd_ready ) begin
usr_rx_data <= fifo_rx_data;
usr_rx_rd_tag <= fifo_rx_rd_tag[USER_TAG-1:0];
end
end
//assign usr_rx_data = fifo_rx_data;
//assign usr_rx_rd_valid = fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1];
//assign usr_rx_rd_tag = fifo_rx_rd_tag[USER_TAG-1:0];
assign fifo_rx_rd_ready = (usr_rx_rd_ready)? 1'b1 : fifo_rx_rd_valid & fifo_rx_rd_tag[USER_TAG+1];
assign poll_rx_data = fifo_rx_data;
assign poll_rx_valid = fifo_rx_rd_valid & fifo_rx_rd_tag[USER_TAG+1];
/////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n)begin
readBytes <= 0;
end
else if(fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1] & fifo_rx_rd_tag[USER_TAG]) begin
readBytes <= readBytes + 64;
end
end
//////////////////////////////////////////////////////////////////////////////////////
///////////////////////////// FIFO Consumer Status Update ////////////////////////////
////////////////////////////// TX WR Requests Generation ////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
fifo_tx_wr_addr <= 0;
fifo_tx_wr_valid <= 0;
fifo_tx_wr_tag <= 0;
update_set <= 1'b0;
lastUpdatedBytes <= 0;
write_response_pending <= 0;
end
else begin
if(fifo_rx_wr_valid)
write_response_pending <= 1'b0;
else if(fifo_tx_wr_ready & fifo_tx_wr_valid)
write_response_pending <= 1'b1;
if(fifo_tx_wr_ready) begin
if(update_status & ~write_response_pending) begin
lastUpdatedBytes <= readBytes;
fifo_tx_data <= {448'b0, readBytes, usr_rd_count};
fifo_tx_wr_addr <= fifo_struct_base + `CRB_STRUCT_CONSUMER_LINE_OFFSET;
fifo_tx_wr_tag <= 0;
fifo_tx_wr_valid <= 1'b1;
end
else begin
fifo_tx_wr_valid <= 0;
end
end
end
end
assign update_status = ((readBytes - lastUpdatedBytes) > update_status_threashold);
endmodule |
module fthread #(parameter AFU_OPERATOR = `UNDEF_AFU,
parameter MAX_FTHREAD_CONFIG_CLS = 2,
parameter USER_RD_TAG = `AFU_TAG,
parameter USER_WR_TAG = `AFU_TAG,
parameter USER_AFU_PARAMETER1 = 1,
parameter USER_AFU_PARAMETER2 = 1) (
input wire clk,
input wire Clk_400,
input wire rst_n,
/// fthread <--> scheduler
input wire cmd_valid,
input wire [`CMD_LINE_WIDTH-1:0] cmd_line,
output wire fthread_job_done,
/// fthread <--> arbiter
//-------------- read interface
output wire tx_rd_valid,
output wire [67:0] tx_rd_hdr,
input wire tx_rd_ready,
input wire rx_rd_valid,
input wire [`FTHREAD_TAG-1:0] rx_rd_tag,
input wire [511:0] rx_data,
//-------------- write interface
output wire [71:0] tx_wr_hdr,
output wire [511:0] tx_data,
output wire tx_wr_valid,
input wire tx_wr_ready,
input wire [`FTHREAD_TAG-1:0] rx_wr_tag,
input wire rx_wr_valid,
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
output wire left_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] left_pipe_tx_rd_tag,
input wire left_pipe_tx_rd_ready,
input wire left_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] left_pipe_rx_rd_tag,
input wire [511:0] left_pipe_rx_data,
output wire left_pipe_rx_rd_ready,
// Right Pipe
input wire right_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] right_pipe_tx_rd_tag,
output wire right_pipe_tx_rd_ready,
output wire right_pipe_rx_rd_valid,
output wire [`IF_TAG-1:0] right_pipe_rx_rd_tag,
output wire [511:0] right_pipe_rx_data,
input wire right_pipe_rx_rd_ready
);
wire start_um;
wire [(MAX_FTHREAD_CONFIG_CLS*512)-1:0] um_params;
wire um_done;
wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters;
wire um_state_counters_valid;
// User Module TX RD
wire [57:0] um_tx_rd_addr;
wire [USER_RD_TAG-1:0] um_tx_rd_tag;
wire um_tx_rd_valid;
wire um_tx_rd_ready;
// User Module TX WR
wire [57:0] um_tx_wr_addr;
wire [USER_WR_TAG-1:0] um_tx_wr_tag;
wire um_tx_wr_valid;
wire [511:0] um_tx_data;
wire um_tx_wr_ready;
// User Module RX RD
wire [USER_RD_TAG-1:0] um_rx_rd_tag;
wire [511:0] um_rx_data;
wire um_rx_rd_valid;
wire um_rx_rd_ready;
// User Module RX WR
wire um_rx_wr_valid;
wire [USER_WR_TAG-1:0] um_rx_wr_tag;
wire reset_user_logic;
reg afu_rst_n = 0;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread Controller ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
FThread_controller #(.MAX_NUM_CONFIG_CL(MAX_FTHREAD_CONFIG_CLS),
.USER_RD_TAG(USER_RD_TAG),
.USER_WR_TAG(USER_WR_TAG)
)
FThread_controller(
.clk (clk),
.rst_n (rst_n),
//--------------- fthread <--> scheduler
.cmd_valid (cmd_valid),
.cmd_line (cmd_line),
.fthread_job_done (fthread_job_done),
.reset_user_logic (reset_user_logic),
//--------------- fthread <--> arbiter
//- TX RD, RX RD
.tx_rd_valid (tx_rd_valid),
.tx_rd_hdr (tx_rd_hdr),
.tx_rd_ready (tx_rd_ready),
.rx_rd_valid (rx_rd_valid),
.rx_rd_tag (rx_rd_tag),
.rx_data (rx_data),
//- TX WR, RX WR
.tx_wr_hdr (tx_wr_hdr),
.tx_data (tx_data),
.tx_wr_valid (tx_wr_valid),
.tx_wr_ready (tx_wr_ready),
.rx_wr_tag (rx_wr_tag),
.rx_wr_valid (rx_wr_valid),
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
.left_pipe_tx_rd_valid (left_pipe_tx_rd_valid),
.left_pipe_tx_rd_tag (left_pipe_tx_rd_tag),
.left_pipe_tx_rd_ready (left_pipe_tx_rd_ready),
.left_pipe_rx_rd_valid (left_pipe_rx_rd_valid),
.left_pipe_rx_rd_tag (left_pipe_rx_rd_tag),
.left_pipe_rx_data (left_pipe_rx_data),
.left_pipe_rx_rd_ready (left_pipe_rx_rd_ready),
// Right Pipe
.right_pipe_tx_rd_valid (right_pipe_tx_rd_valid),
.right_pipe_tx_rd_tag (right_pipe_tx_rd_tag),
.right_pipe_tx_rd_ready (right_pipe_tx_rd_ready),
.right_pipe_rx_rd_valid (right_pipe_rx_rd_valid),
.right_pipe_rx_rd_tag (right_pipe_rx_rd_tag),
.right_pipe_rx_data (right_pipe_rx_data),
.right_pipe_rx_rd_ready (right_pipe_rx_rd_ready),
//------------------------ User Module interface
.start_um (start_um),
.um_params (um_params),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// User AFU ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
afu_rst_n <= rst_n & ~reset_user_logic;
end
AFU #(.AFU_OPERATOR(AFU_OPERATOR),
.MAX_AFU_CONFIG_WIDTH(MAX_FTHREAD_CONFIG_CLS*512),
.USER_RD_TAG(USER_RD_TAG),
.USER_WR_TAG(USER_WR_TAG),
.USER_AFU_PARAMETER1(USER_AFU_PARAMETER1),
.USER_AFU_PARAMETER2(USER_AFU_PARAMETER2)
)
AFU(
.clk (clk),
.Clk_400 (Clk_400),
.rst_n (afu_rst_n ),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
endmodule |
module FThread_controller #(parameter MAX_NUM_CONFIG_CL = 2,
parameter USER_RD_TAG = 2,
parameter USER_WR_TAG = 9) (
input wire clk,
input wire rst_n,
//--------------- channel <--> scheduler
input wire cmd_valid,
input wire [`CMD_LINE_WIDTH-1:0] cmd_line,
output reg fthread_job_done,
output wire reset_user_logic,
//--------------- channel <--> arbiter
//- TX RD, RX RD
output wire tx_rd_valid,
output wire [67:0] tx_rd_hdr,
input wire tx_rd_ready,
input wire rx_rd_valid,
input wire [`FTHREAD_TAG-1:0] rx_rd_tag,
input wire [511:0] rx_data,
//- TX WR, RX WR
output wire [71:0] tx_wr_hdr,
output wire [511:0] tx_data,
output wire tx_wr_valid,
input wire tx_wr_ready,
input wire [`FTHREAD_TAG-1:0] rx_wr_tag,
input wire rx_wr_valid,
//------------------------ Pipeline Interfaces ---------------------//
// Left Pipe
output wire left_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] left_pipe_tx_rd_tag,
input wire left_pipe_tx_rd_ready,
input wire left_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] left_pipe_rx_rd_tag,
input wire [511:0] left_pipe_rx_data,
output wire left_pipe_rx_rd_ready,
// Right Pipe
input wire right_pipe_tx_rd_valid,
input wire [`IF_TAG-1:0] right_pipe_tx_rd_tag,
output wire right_pipe_tx_rd_ready,
output wire right_pipe_rx_rd_valid,
output wire [`IF_TAG-1:0] right_pipe_rx_rd_tag,
output wire [511:0] right_pipe_rx_data,
input wire right_pipe_rx_rd_ready,
//------------------------ User Module interface -------------------//
output reg start_um,
output reg [(MAX_NUM_CONFIG_CL*512)-1:0] um_params,
input wire um_done,
input wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters,
input wire um_state_counters_valid,
// User Module TX RD
input wire [57:0] um_tx_rd_addr,
input wire [USER_RD_TAG-1:0] um_tx_rd_tag,
input wire um_tx_rd_valid,
output wire um_tx_rd_ready,
// User Module TX WR
input wire [57:0] um_tx_wr_addr,
input wire [USER_WR_TAG-1:0] um_tx_wr_tag,
input wire um_tx_wr_valid,
input wire [511:0] um_tx_data,
output wire um_tx_wr_ready,
// User Module RX RD
output wire [USER_RD_TAG-1:0] um_rx_rd_tag,
output wire [511:0] um_rx_data,
output wire um_rx_rd_valid,
input wire um_rx_rd_ready,
// User Module RX WR
output wire um_rx_wr_valid,
output wire [USER_WR_TAG-1:0] um_rx_wr_tag
);
localparam [2:0]
CHANNEL_IDLE_STATE = 3'b000,
CHANNEL_STARTING_STATE = 3'b001,
CHANNEL_CONFIG_STATE = 3'b010,
CHANNEL_RUN_STATE = 3'b011,
CHANNEL_DONE_STATE = 3'b100,
CHANNEL_DRAIN_WR_FIFO_STATE = 3'b101,
CHANNEL_WRFENCE_STATE = 3'b110,
CHANNEL_DONE_RESP_STATE = 3'b111;
reg [2:0] ch_status_state;
wire ft_tx_wr_ready;
reg ft_tx_wr_valid;
reg [57:0] ft_tx_wr_addr;
reg [`FTHREAD_TAG-1:0] ft_tx_wr_tag;
reg [511:0] ft_tx_data;
reg ft_tx_rd_valid;
reg [57:0] ft_tx_rd_addr;
reg [`FTHREAD_TAG-1:0] ft_tx_rd_tag;
wire ft_tx_rd_ready;
reg [(MAX_NUM_CONFIG_CL*512)-1:0] config_param_line;
wire [57:0] cfg_tx_rd_addr;
wire cfg_tx_rd_ready;
wire [`IF_TAG-1:0] cfg_tx_rd_tag;
wire cfg_tx_rd_valid;
reg [`IF_TAG-1:0] cfg_rx_rd_tag;
reg [511:0] cfg_rx_data;
reg cfg_rx_rd_valid;
reg cmd_buff_valid;
reg [`CMD_LINE_WIDTH-1:0] cmd_buff;
reg reserved_cmd_valid;
reg [`CMD_LINE_WIDTH-1:0] reserved_cmd;
wire [3:0] wr_cmd;
reg [31:0] writes_sent;
reg [31:0] writes_done;
reg [31:0] finishCycles;
reg [31:0] RdReqCnt;
reg [31:0] GRdReqCnt;
reg [31:0] WrReqCnt;
reg [31:0] exeCycles;
reg [31:0] ConfigCycles;
reg [31:0] ReadCycles;
reg [31:0] ReadyCycles;
reg rx_rd_valid_reg;
reg [`FTHREAD_TAG-1:0] rx_rd_tag_reg;
reg [511:0] rx_data_reg;
reg [`FTHREAD_TAG-1:0] rx_wr_tag_reg;
reg rx_wr_valid_reg;
wire [(MAX_NUM_CONFIG_CL*512)-1:0] afu_config_struct;
wire afu_config_struct_valid;
wire flush_cmd;
wire read_reserved_cmd;
wire tx_rd_fifo_full;
wire tx_wr_fifo_full;
wire tx_wr_fifo_empty;
reg set_wr_if_direct_pipelined;
reg set_wr_if_mem_pipelined;
reg [57:0] wr_mem_pipeline_addr;
reg set_rd_if_direct_pipelined;
reg set_rd_if_mem_pipelined;
reg [57:0] rd_mem_pipeline_addr;
reg [3:0] rd_direct_pipeline_addr_code;
reg [3:0] rd_mem_pipeline_addr_code;
wire user_tx_wr_if_empty;
wire usr_arb_tx_wr_valid;
wire [57:0] usr_arb_tx_wr_addr;
wire [`IF_TAG-1:0] usr_arb_tx_wr_tag;
wire [511:0] usr_arb_tx_data;
wire usr_arb_tx_wr_ready;
reg usr_arb_rx_wr_valid;
reg [`IF_TAG-1:0] usr_arb_rx_wr_tag;
wire rif_tx_wr_valid;
wire [57:0] rif_tx_wr_addr;
wire [`IF_TAG-1:0] rif_tx_wr_tag;
wire [511:0] rif_tx_data;
wire rif_tx_wr_ready;
reg rif_rx_wr_valid;
reg [`IF_TAG-1:0] rif_rx_wr_tag;
wire wif_tx_rd_valid;
wire [57:0] wif_tx_rd_addr;
wire [`IF_TAG-1:0] wif_tx_rd_tag;
wire wif_tx_rd_ready;
reg wif_rx_rd_valid;
reg [`IF_TAG-1:0] wif_rx_rd_tag;
reg [511:0] wif_rx_data;
wire usr_arb_tx_rd_valid;
wire [57:0] usr_arb_tx_rd_addr;
wire [`IF_TAG-1:0] usr_arb_tx_rd_tag;
wire usr_arb_tx_rd_ready;
reg usr_arb_rx_rd_valid;
reg [`IF_TAG-1:0] usr_arb_rx_rd_tag;
reg [511:0] usr_arb_rx_data;
reg run_rd_tx;
reg run_wr_tx;
reg rif_done;
reg wif_done;
reg start_d0;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread IO ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Register RX RD,WR: Data, tags
always@(posedge clk)begin
rx_rd_tag_reg <= rx_rd_tag;
rx_data_reg <= rx_data;
rx_wr_tag_reg <= rx_wr_tag;
end
// Register RX RD,WR: Valids
always@(posedge clk)begin
if(~rst_n) begin
rx_rd_valid_reg <= 0;
rx_wr_valid_reg <= 0;
end
else begin
rx_rd_valid_reg <= rx_rd_valid;
rx_wr_valid_reg <= rx_wr_valid;
end
end
// RX RD: used by the user module and configurator
// data
always@(posedge clk) begin
usr_arb_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
usr_arb_rx_data <= rx_data_reg;
wif_rx_data <= rx_data_reg;
wif_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
cfg_rx_data <= rx_data_reg;
cfg_rx_rd_tag <= rx_rd_tag_reg[`IF_TAG-1:0];
end
//valids
always@(posedge clk) begin
if(~ rst_n)begin
usr_arb_rx_rd_valid <= 0;
wif_rx_rd_valid <= 0;
cfg_rx_rd_valid <= 0;
end
else begin
usr_arb_rx_rd_valid <= rx_rd_valid_reg & rx_rd_tag_reg[`FTHREAD_TAG-1] & run_rd_tx;
wif_rx_rd_valid <= rx_rd_valid_reg & ~rx_rd_tag_reg[`FTHREAD_TAG-1] & run_rd_tx;
cfg_rx_rd_valid <= rx_rd_valid_reg & ~run_rd_tx;
end
end
//assign cfg_rx_data = rx_data_reg;
//assign cfg_rx_rd_valid = rx_rd_valid_reg & ~run_rd_tx;
//assign cfg_rx_rd_tag = rx_rd_tag_reg[`IF_TAG-1:0];
//////////////////////////////////////////////////////////// TX RD FIFO
quick_fifo #(.FIFO_WIDTH(68),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({ft_tx_rd_addr, ft_tx_rd_tag}),
.we (ft_tx_rd_valid),
.re (tx_rd_ready),
.dout (tx_rd_hdr),
.empty (),
.valid (tx_rd_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
///////////////////////////////////////////////////////////////////////////////////////////////////
// RX WR: used by the user module
// tag
always@(posedge clk) begin
usr_arb_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
rif_rx_wr_tag <= rx_wr_tag_reg[`IF_TAG-1:0];
end
// valid
always@(posedge clk) begin
if(~ rst_n)begin
usr_arb_rx_wr_valid <= 0;
rif_rx_wr_valid <= 0;
end
else begin
usr_arb_rx_wr_valid <= rx_wr_valid_reg & rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
rif_rx_wr_valid <= rx_wr_valid_reg & ~rx_wr_tag_reg[`FTHREAD_TAG-1] & run_wr_tx;
end
end
//////////////////////////////////////////////////////////// TX WR FIFO
assign wr_cmd = (run_wr_tx)? `CCI_REQ_WR_LINE : `CCI_REQ_WR_THRU;
quick_fifo #(.FIFO_WIDTH(512+72),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) tx_wr_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({ wr_cmd, ft_tx_wr_addr, ft_tx_wr_tag, ft_tx_data}),
.we (ft_tx_wr_valid),
.re (tx_wr_ready),
.dout ({tx_wr_hdr, tx_data}),
.empty (tx_wr_fifo_empty),
.valid (tx_wr_valid),
.full (tx_wr_fifo_full),
.count (),
.almostfull ()
);
/////////////////////////////////////////////////////////////////////////////////
// Track All Write requests that are finished
always@(posedge clk) begin
if( ~rst_n | (ch_status_state == CHANNEL_IDLE_STATE) )begin
writes_sent <= 0;
writes_done <= 0;
end
else begin
writes_sent <= (tx_wr_valid & tx_wr_ready)? (writes_sent + 1'b1) : writes_sent;
writes_done <= (rx_wr_valid_reg)? (writes_done + 1'b1) : writes_done;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Command Buffer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// communicate with the scheduler
assign flush_cmd = (ch_status_state == CHANNEL_DONE_STATE);
// cmd_line
always@(posedge clk) begin
if(~cmd_buff_valid) begin
cmd_buff <= reserved_cmd;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
cmd_buff_valid <= 1'b0;
end
else if(flush_cmd) begin
cmd_buff_valid <= 1'b0;
end
else if(reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE)) begin
cmd_buff_valid <= 1'b1;
end
end
// reserved cmd
// cmd_line
always@(posedge clk) begin
if(~reserved_cmd_valid) begin
reserved_cmd <= cmd_line;
end
end
// valid
always@(posedge clk) begin
if(~rst_n) begin
reserved_cmd_valid <= 1'b0;
end
else if(read_reserved_cmd) begin
reserved_cmd_valid <= 1'b0;
end
else if(cmd_valid) begin
reserved_cmd_valid <= 1'b1;
end
end
assign read_reserved_cmd = reserved_cmd_valid & (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// FThread State Machine ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
ch_status_state <= 3'b0;
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
fthread_job_done <= 0;
start_d0 <= 0;
rif_done <= 0;
wif_done <= 0;
config_param_line <= 0;
run_rd_tx <= 0;
run_wr_tx <= 0;
ft_tx_wr_valid <= 0;
ft_tx_data <= 0;
ft_tx_wr_addr <= 0;
ft_tx_wr_tag <= 0;
ft_tx_rd_valid <= 0;
ft_tx_rd_addr <= 0;
ft_tx_rd_tag <= 0;
end
else begin
case (ch_status_state)
CHANNEL_IDLE_STATE: begin
/* If a valid job request is available in the command buffer, then we issue a status update that the job is starting
and compute some necessary flags for the configuration of the FThread Controller */
ft_tx_wr_valid <= 1'b0;
fthread_job_done <= 0;
start_d0 <= 0;
ft_tx_rd_valid <= 0;
rif_done <= 0;
wif_done <= 0;
if(cmd_buff_valid) begin
// Go to start state, set some flags
ch_status_state <= CHANNEL_STARTING_STATE;
// WR IF Config
set_wr_if_direct_pipelined <= (cmd_buff[121:120] == `WR_IF_DIRECT_PIPELINE_CODE);
set_wr_if_mem_pipelined <= (cmd_buff[121:120] == `WR_IF_MEM_PIPELINE_CODE);
wr_mem_pipeline_addr <= cmd_buff[179:122];
// RD IF Config
set_rd_if_direct_pipelined <= cmd_buff[180];
set_rd_if_mem_pipelined <= cmd_buff[181];
rd_mem_pipeline_addr <= cmd_buff[239:182];
rd_mem_pipeline_addr_code <= cmd_buff[243:240];
rd_direct_pipeline_addr_code <= cmd_buff[247:244];
// write fthread status as starting to the SW to see.
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_STARTING_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_STARTING_STATE: begin
/* This state is just a stopby state until the starting status update request is sent to memory*/
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_CONFIG_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_CONFIG_STATE: begin
/* During this state the Config struct reader is started to read the user AFU configuration data structure.
When the configuration is obtained we switch to the Run state and trigger the user AFU*/
if (afu_config_struct_valid) begin
ch_status_state <= CHANNEL_RUN_STATE;
start_d0 <= 1'b1;
run_rd_tx <= 1'b1;
run_wr_tx <= 1'b1;
end
config_param_line <= afu_config_struct;
//
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= cfg_tx_rd_valid;
ft_tx_rd_addr <= cfg_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, cfg_tx_rd_tag};
end
end
CHANNEL_RUN_STATE: begin
/* In this state the user AFU is active, we stay in this state until the user declares it finished processing and producing
all the results. Then we move to the Drain WR FIFO state, to make sure all user generated write requests are submitted to
memory*/
start_d0 <= 1'b0;
if(um_done) begin
ch_status_state <= CHANNEL_DRAIN_WR_FIFO_STATE;
config_param_line <= 0;
wif_done <= 1'b1;
rif_done <= 1'b1;
set_rd_if_direct_pipelined <= 0;
set_rd_if_mem_pipelined <= 0;
rd_mem_pipeline_addr <= 0;
rd_mem_pipeline_addr_code <= 0;
rd_direct_pipeline_addr_code <= 0;
end
//
// TX RD
if(ft_tx_rd_ready) begin
if(wif_tx_rd_valid) begin
ft_tx_rd_valid <= 1'b1;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
else begin
ft_tx_rd_valid <= usr_arb_tx_rd_valid;
ft_tx_rd_addr <= usr_arb_tx_rd_addr;
ft_tx_rd_tag <= {1'b1, usr_arb_tx_rd_tag};
end
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_DRAIN_WR_FIFO_STATE: begin
/* In this state we make sure all the write requests in the different FIFOs are submitted to memory*/
if (user_tx_wr_if_empty & tx_wr_fifo_empty & ~ft_tx_wr_valid) begin
ch_status_state <= CHANNEL_WRFENCE_STATE;
end
if(tx_wr_fifo_empty) begin
set_wr_if_direct_pipelined <= 0;
set_wr_if_mem_pipelined <= 0;
wr_mem_pipeline_addr <= 0;
end
// TX RD
if(ft_tx_rd_ready) begin
ft_tx_rd_valid <= wif_tx_rd_valid;
ft_tx_rd_addr <= wif_tx_rd_addr;
ft_tx_rd_tag <= {1'b0, wif_tx_rd_tag};
end
// TX WR
if(ft_tx_wr_ready) begin
if(rif_tx_wr_valid) begin
ft_tx_wr_valid <= 1'b1;
ft_tx_wr_addr <= rif_tx_wr_addr;
ft_tx_wr_tag <= {1'b0, rif_tx_wr_tag};
ft_tx_data <= rif_tx_data;
end
else begin
ft_tx_wr_valid <= usr_arb_tx_wr_valid;
ft_tx_wr_addr <= usr_arb_tx_wr_addr;
ft_tx_wr_tag <= {1'b1, usr_arb_tx_wr_tag};
ft_tx_data <= usr_arb_tx_data;
end
end
end
CHANNEL_WRFENCE_STATE: begin
run_rd_tx <= 0;
run_wr_tx <= 0;
if (writes_sent == writes_done) begin
ch_status_state <= CHANNEL_DONE_STATE;
//
ft_tx_wr_valid <= 1'b1;
ft_tx_data <= {um_state_counters[255:0], ReadyCycles, ReadCycles, finishCycles, ConfigCycles, exeCycles, WrReqCnt, RdReqCnt, 29'b0, CHANNEL_DONE_STATE};
ft_tx_wr_addr <= cmd_buff[57:0];
ft_tx_wr_tag <= 0;
end
end
CHANNEL_DONE_STATE: begin
if(ft_tx_wr_ready) begin
ch_status_state <= CHANNEL_DONE_RESP_STATE;
ft_tx_wr_valid <= 1'b0;
end
end
CHANNEL_DONE_RESP_STATE: begin
if(rx_wr_valid_reg) begin
ch_status_state <= CHANNEL_IDLE_STATE;
fthread_job_done <= 1'b1;
end
end
endcase
end
end
assign ft_tx_rd_ready = ~tx_rd_fifo_full;
assign wif_tx_rd_ready = ft_tx_rd_ready & run_rd_tx;
assign usr_arb_tx_rd_ready = ft_tx_rd_ready & run_rd_tx & ~wif_tx_rd_valid;
assign cfg_tx_rd_ready = ft_tx_rd_ready;
assign ft_tx_wr_ready = ~tx_wr_fifo_full;
assign rif_tx_wr_ready = ft_tx_wr_ready & run_wr_tx;
assign usr_arb_tx_wr_ready = ft_tx_wr_ready & run_wr_tx & ~rif_tx_wr_valid;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Configurer ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
ReadConfigStruct #(.MAX_NUM_CONFIG_CL(MAX_NUM_CONFIG_CL))
ReadConfigStruct (
.clk (clk),
.rst_n (rst_n & ~(ch_status_state == CHANNEL_DONE_RESP_STATE)),
//-------------------------------------------------//
.get_config_struct ( ch_status_state == CHANNEL_CONFIG_STATE ),
.base_addr (cmd_buff[115:58]),
.config_struct_length ( {28'b0, cmd_buff[119:116]}),
// User Module TX RD
.cs_tx_rd_addr (cfg_tx_rd_addr),
.cs_tx_rd_tag (cfg_tx_rd_tag),
.cs_tx_rd_valid (cfg_tx_rd_valid),
.cs_tx_rd_free (cfg_tx_rd_ready),
// User Module RX RD
.cs_rx_rd_tag (cfg_rx_rd_tag),
.cs_rx_rd_data (cfg_rx_data),
.cs_rx_rd_valid (cfg_rx_rd_valid),
//
.afu_config_struct (afu_config_struct),
.afu_config_struct_valid (afu_config_struct_valid)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////////
////////////////////////////// User Module Control Interface ///////////////////////////////
////////////////////////////////// ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
//
always@(posedge clk) begin
um_params <= config_param_line;
end
always@(posedge clk) begin
if( ~rst_n) begin
start_um <= 0;
end
else begin
start_um <= start_d0;
end
end
//assign um_params = config_param_line;
assign reset_user_logic = (ch_status_state == CHANNEL_IDLE_STATE);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// User Module IO Interfaces ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// RD Interface
user_tx_rd_if #(.USER_TAG(USER_RD_TAG))
user_tx_rd_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_mem_pipelined (set_rd_if_mem_pipelined),
.set_if_direct_pipelined (set_rd_if_direct_pipelined),
.mem_pipeline_addr (rd_mem_pipeline_addr),
.mem_pipeline_addr_code (rd_mem_pipeline_addr_code),
.direct_pipeline_addr_code (rd_direct_pipeline_addr_code),
.reads_finished (rif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_rd_valid (usr_arb_tx_rd_valid),
.usr_arb_tx_rd_addr (usr_arb_tx_rd_addr),
.usr_arb_tx_rd_tag (usr_arb_tx_rd_tag),
.usr_arb_tx_rd_ready (usr_arb_tx_rd_ready),
.usr_arb_rx_rd_valid (usr_arb_rx_rd_valid),
.usr_arb_rx_rd_tag (usr_arb_rx_rd_tag),
.usr_arb_rx_data (usr_arb_rx_data),
.rif_tx_wr_addr (rif_tx_wr_addr),
.rif_tx_wr_tag (rif_tx_wr_tag),
.rif_tx_wr_valid (rif_tx_wr_valid),
.rif_tx_data (rif_tx_data),
.rif_tx_wr_ready (rif_tx_wr_ready),
.rif_rx_wr_tag (rif_rx_wr_tag),
.rif_rx_wr_valid (rif_rx_wr_valid),
//-------------------- to pipeline writer ---------------------------//
.usr_pipe_tx_rd_valid (left_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (left_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (left_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (left_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (left_pipe_rx_rd_tag),
.usr_pipe_rx_data (left_pipe_rx_data),
.usr_pipe_rx_rd_ready (left_pipe_rx_rd_ready)
);
// WR Interface
user_tx_wr_if #(.USER_TAG(USER_WR_TAG) )
user_tx_wr_if(
.clk (clk),
.rst_n (rst_n),
.reset_interface ( (ch_status_state == CHANNEL_IDLE_STATE) ),
.set_if_pipelined (set_wr_if_direct_pipelined),
.user_tx_wr_if_empty (user_tx_wr_if_empty),
.set_if_mem_pipelined (set_wr_if_mem_pipelined),
.mem_pipeline_addr (wr_mem_pipeline_addr),
.writes_finished (wif_done),
//--------------------- User RD Request -----------------------------//
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag),
//-------------------- to Fthread Controller ------------------------//
.usr_arb_tx_wr_valid (usr_arb_tx_wr_valid),
.usr_arb_tx_wr_addr (usr_arb_tx_wr_addr),
.usr_arb_tx_wr_tag (usr_arb_tx_wr_tag),
.usr_arb_tx_wr_ready (usr_arb_tx_wr_ready),
.usr_arb_tx_data (usr_arb_tx_data),
.usr_arb_rx_wr_valid (usr_arb_rx_wr_valid),
.usr_arb_rx_wr_tag (usr_arb_rx_wr_tag),
.wif_tx_rd_addr (wif_tx_rd_addr),
.wif_tx_rd_tag (wif_tx_rd_tag),
.wif_tx_rd_valid (wif_tx_rd_valid),
.wif_tx_rd_ready (wif_tx_rd_ready),
.wif_rx_rd_tag (wif_rx_rd_tag),
.wif_rx_data (wif_rx_data),
.wif_rx_rd_valid (wif_rx_rd_valid),
//-------------------- To pipeline reader
.usr_pipe_tx_rd_valid (right_pipe_tx_rd_valid),
.usr_pipe_tx_rd_tag (right_pipe_tx_rd_tag),
.usr_pipe_tx_rd_ready (right_pipe_tx_rd_ready),
.usr_pipe_rx_rd_valid (right_pipe_rx_rd_valid),
.usr_pipe_rx_rd_tag (right_pipe_rx_rd_tag),
.usr_pipe_rx_data (right_pipe_rx_data),
.usr_pipe_rx_rd_ready (right_pipe_rx_rd_ready)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// //////////////////////////////////////
////////////////////////////// Profiling Counters ///////////////////////////////////
////////////////////////////////// //////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n | (ch_status_state == CHANNEL_IDLE_STATE)) begin
RdReqCnt <= 32'b0;
GRdReqCnt <= 32'b0;
WrReqCnt <= 32'b0;
exeCycles <= 32'b0;
finishCycles <= 32'b0;
ConfigCycles <= 32'b0;
ReadCycles <= 0;
ReadyCycles <= 0;
end
else begin
exeCycles <= exeCycles + 1'b1;
if(tx_rd_valid & tx_rd_ready) begin
GRdReqCnt <= GRdReqCnt + 1'b1;
end
if(um_tx_rd_valid & um_tx_rd_ready) begin
RdReqCnt <= RdReqCnt + 1'b1;
end
//
if(um_tx_wr_valid & um_tx_wr_ready) begin
WrReqCnt <= WrReqCnt + 1'b1;
end
//
if( ch_status_state[2] ) begin
finishCycles <= finishCycles + 1'b1;
end
//
if(ch_status_state == CHANNEL_CONFIG_STATE) begin
ConfigCycles <= ConfigCycles + 1'b1;
end
//
if(um_tx_rd_valid) begin
ReadCycles <= ReadCycles + 1'b1;
end
//
if(tx_rd_ready) begin
ReadyCycles <= ReadyCycles + 1'b1;
end
end
end
endmodule |
module user_tx_rd_if #(parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
input wire reset_interface,
input wire set_if_mem_pipelined,
input wire set_if_direct_pipelined,
input wire [57:0] mem_pipeline_addr,
input wire [3:0] mem_pipeline_addr_code,
input wire [3:0] direct_pipeline_addr_code,
input wire reads_finished,
//--------------------- User RD Request -----------------------------//
// User Module TX RD
input wire [57:0] um_tx_rd_addr,
input wire [USER_TAG-1:0] um_tx_rd_tag,
input wire um_tx_rd_valid,
output wire um_tx_rd_ready,
// User Module RX RD
output wire [USER_TAG-1:0] um_rx_rd_tag,
output wire [511:0] um_rx_data,
output wire um_rx_rd_valid,
input wire um_rx_rd_ready,
//-------------------- to Fthread Controller ------------------------//
output wire usr_arb_tx_rd_valid,
output wire [57:0] usr_arb_tx_rd_addr,
output wire [`IF_TAG-1:0] usr_arb_tx_rd_tag,
input wire usr_arb_tx_rd_ready,
input wire usr_arb_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_arb_rx_rd_tag,
input wire [511:0] usr_arb_rx_data,
output wire [57:0] rif_tx_wr_addr,
output wire [`IF_TAG-1:0] rif_tx_wr_tag,
output wire rif_tx_wr_valid,
output wire [511:0] rif_tx_data,
input wire rif_tx_wr_ready,
input wire [`IF_TAG-1:0] rif_rx_wr_tag,
input wire rif_rx_wr_valid,
//-------------------- To pipeline writer ---------------------------//
output wire usr_pipe_tx_rd_valid,
output wire [`IF_TAG-1:0] usr_pipe_tx_rd_tag,
input wire usr_pipe_tx_rd_ready,
input wire usr_pipe_rx_rd_valid,
input wire [`IF_TAG-1:0] usr_pipe_rx_rd_tag,
input wire [511:0] usr_pipe_rx_data,
output wire usr_pipe_rx_rd_ready
);
wire [57+USER_TAG:0] tx_rd_fifo_dout;
wire tx_rd_fifo_valid;
wire tx_rd_fifo_full;
wire tx_rd_fifo_re;
wire ord_tx_rd_ready;
// RX RD
reg [`IF_TAG-1:0] rx_rd_tag_reg;
reg [511:0] rx_data_reg;
reg rx_rd_valid_reg;
wire tx_rd_ready;
wire tx_rd_valid;
wire [57:0] tx_rd_addr;
wire [`IF_TAG-1:0] tx_rd_tag;
wire usr_tx_rd_ready;
wire usr_tx_rd_valid;
wire [57:0] usr_tx_rd_addr;
wire [USER_TAG+1:0] usr_tx_rd_tag;
wire [USER_TAG+1:0] usr_rx_rd_tag;
wire usr_rx_rd_valid;
wire [511:0] usr_rx_data;
reg [57:0] fifo_base_addr;
reg [3:0] fifo_addr_code;
reg [3:0] direct_pipeline_code;
reg direct_pipeline_code_valid;
reg in_memory_pipeline;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Pipelining Control Flags ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (~rst_n | reset_interface | reads_finished) begin
in_memory_pipeline <= 0;
fifo_base_addr <= 0;
fifo_addr_code <= 0;
direct_pipeline_code <= 0;
direct_pipeline_code_valid <= 1'b0;
end
else begin
if(set_if_mem_pipelined) begin
in_memory_pipeline <= 1'b1;
fifo_base_addr <= mem_pipeline_addr;
fifo_addr_code <= mem_pipeline_addr_code;
end
if(set_if_direct_pipelined) begin
direct_pipeline_code <= direct_pipeline_addr_code;
direct_pipeline_code_valid <= 1'b1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Reader Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(58 + USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) tx_rd_fifo(
.clk (clk),
.reset_n (rst_n & ~reset_interface),
.din ({um_tx_rd_tag, um_tx_rd_addr}),
.we (um_tx_rd_valid),
.re (tx_rd_fifo_re),
.dout (tx_rd_fifo_dout),
.empty (),
.valid (tx_rd_fifo_valid),
.full (tx_rd_fifo_full),
.count (),
.almostfull ()
);
assign um_tx_rd_ready = ~tx_rd_fifo_full;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Through SW FIFO Reader /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
//(direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
// Pass through in-memory FIFO
sw_fifo_reader #(.USER_TAG(USER_TAG) )
sw_fifo_reader(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
.fifo_base_addr (fifo_base_addr),
.fifo_addr_code (fifo_addr_code),
.setup_fifo (in_memory_pipeline),
.reads_finished (reads_finished),
//--------------------- FIFO to QPI ----------------//
// TX RD
.fifo_tx_wr_addr (rif_tx_wr_addr),
.fifo_tx_wr_tag (rif_tx_wr_tag),
.fifo_tx_wr_valid (rif_tx_wr_valid),
.fifo_tx_data (rif_tx_data),
.fifo_tx_wr_ready (rif_tx_wr_ready),
// TX RD
.fifo_tx_rd_addr (usr_tx_rd_addr),
.fifo_tx_rd_tag (usr_tx_rd_tag),
.fifo_tx_rd_valid (usr_tx_rd_valid),
.fifo_tx_rd_ready (usr_tx_rd_ready),
// RX RD
.fifo_rx_wr_tag (rif_rx_wr_tag),
.fifo_rx_wr_valid (rif_rx_wr_valid),
// RX WR
.fifo_rx_rd_valid (usr_rx_rd_valid),
.fifo_rx_rd_tag (usr_rx_rd_tag),
.fifo_rx_data (usr_rx_data),
.fifo_rx_rd_ready (usr_rx_rd_ready),
///////////////////////// User Logic Interface ////////////////////
.usr_tx_rd_tag (tx_rd_fifo_dout[57+USER_TAG:58]),
.usr_tx_rd_valid (tx_rd_fifo_valid),
.usr_tx_rd_addr (tx_rd_fifo_dout[57:0]),
.usr_tx_rd_ready (tx_rd_fifo_re),
.usr_rx_rd_tag (um_rx_rd_tag),
.usr_rx_rd_valid (um_rx_rd_valid),
.usr_rx_data (um_rx_data),
.usr_rx_rd_ready (um_rx_rd_ready)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Requests Ordering Module ////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
order_module_backpressure #(
.TAG_WIDTH(7),
.OUT_TAG_WIDTH(`IF_TAG),
.USER_TAG_WIDTH(USER_TAG+2))
omodule(
.clk (clk),
.rst_n (rst_n & ~reset_interface),
//-------------------------------------------------//
// input requests
.usr_tx_rd_addr (usr_tx_rd_addr),
.usr_tx_rd_tag (usr_tx_rd_tag),
.usr_tx_rd_valid (usr_tx_rd_valid),
.usr_tx_rd_free (usr_tx_rd_ready),
// TX RD
.ord_tx_rd_addr (tx_rd_addr),
.ord_tx_rd_tag (tx_rd_tag),
.ord_tx_rd_valid (tx_rd_valid),
.ord_tx_rd_free (tx_rd_ready),
// RX RD
.ord_rx_rd_tag (rx_rd_tag_reg[6:0]),
.ord_rx_rd_data (rx_data_reg),
.ord_rx_rd_valid (rx_rd_valid_reg),
//
.usr_rx_rd_tag (usr_rx_rd_tag),
.usr_rx_rd_data (usr_rx_data),
.usr_rx_rd_valid (usr_rx_rd_valid),
.usr_rx_rd_ready (usr_rx_rd_ready)
);
//--------------------------------------------//
assign tx_rd_ready = ((tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid)? usr_pipe_tx_rd_ready : usr_arb_tx_rd_ready;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Accesses To Main Memory /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Arbiter TX RD
assign usr_arb_tx_rd_addr = tx_rd_addr;
assign usr_arb_tx_rd_tag = tx_rd_tag;
assign usr_arb_tx_rd_valid = (direct_pipeline_code_valid)?(tx_rd_addr[57:54] != direct_pipeline_code) & tx_rd_valid : tx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Direct AFU-AFU Pipeline /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//-------------------------------------------//
// Pipe TX RD
assign usr_pipe_tx_rd_tag = tx_rd_tag;
assign usr_pipe_tx_rd_valid = (tx_rd_addr[57:54] == direct_pipeline_code) & direct_pipeline_code_valid & tx_rd_valid;
assign usr_pipe_rx_rd_ready = ~usr_arb_rx_rd_valid;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Read Request Responses /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//--------------------------------------------//
// order module rd rx
// data
always @(posedge clk) begin
if(usr_arb_rx_rd_valid) begin
rx_data_reg <= usr_arb_rx_data;
end
else begin
rx_data_reg <= usr_pipe_rx_data;
end
end
// valid
always @(posedge clk) begin
if (~rst_n | reset_interface) begin
rx_rd_tag_reg <= 0;
rx_rd_valid_reg <= 0;
end
else begin
if(usr_arb_rx_rd_valid) begin
rx_rd_tag_reg <= usr_arb_rx_rd_tag;
rx_rd_valid_reg <= 1'b1;
end
else begin
rx_rd_tag_reg <= usr_pipe_rx_rd_tag;
rx_rd_valid_reg <= usr_pipe_rx_rd_valid;
end
end
end
endmodule |
module sw_fifo_writer #(parameter POLL_CYCLES = 32,
parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire [57:0] fifo_base_addr,
input wire setup_fifo,
input wire writes_finished,
output reg fifo_done,
//--------------------- FIFO to QPI ----------------//
// TX RD
output reg [57:0] fifo_tx_rd_addr,
output reg [`IF_TAG-1:0] fifo_tx_rd_tag,
output reg fifo_tx_rd_valid,
input wire fifo_tx_rd_ready,
// TX WR
output reg [57:0] fifo_tx_wr_addr,
output reg [USER_TAG+1:0] fifo_tx_wr_tag,
output reg fifo_tx_wr_valid,
output reg [511:0] fifo_tx_data,
input wire fifo_tx_wr_ready,
// RX RD
input wire [`IF_TAG-1:0] fifo_rx_rd_tag,
input wire [511:0] fifo_rx_data,
input wire fifo_rx_rd_valid,
//output wire fifo_rx_rd_ready,
// RX WR
input wire fifo_rx_wr_valid,
input wire [USER_TAG+1:0] fifo_rx_wr_tag,
///////////////////////// User Logic Interface ////////////////////
input wire [USER_TAG-1:0] usr_tx_wr_tag,
input wire [57:0] usr_tx_wr_addr,
input wire usr_tx_wr_valid,
input wire [511:0] usr_tx_data,
output wire usr_tx_wr_ready,
output wire [USER_TAG-1:0] usr_rx_wr_tag,
output wire usr_rx_wr_valid
);
///////////////////////////////// Wires Declarations ////////////////////////////
//wire update_status;
reg poll_again;
reg space_available;
reg delay_poll_1;
//reg update_set;
reg update_check;
reg update_check_set;
/////////////////////////////////////// Reg Declarations /////////////////////////
reg [31:0] numPushedBytes;
reg [31:0] otherSideUpdatedBytes;
reg [31:0] sizeInNumCL;
reg [31:0] sizeInBytes;
reg [31:0] usr_wr_count;
reg [31:0] poll_count;
reg last_state_set;
wire issue_last_state;
reg [57:0] fifo_buff_addr;
reg [57:0] fifo_struct_base;
reg [2:0] fifo_fsm_state;
reg [1:0] poll_fsm_state;
wire all_writes_done;
reg [31:0] writes_sent;
reg [31:0] writes_done;
reg [31:0] writtenBytes;
reg [31:0] update_status_threashold;
reg write_response_pending;
reg [31:0] lastUpdatedBytes;
wire [31:0] updateBytes;
reg updateStatus_fifo_valid;
wire updateStatus_fifo_full;
wire updateStatus_fifo_re;
reg [32:0] updateStatus_fifo_dout;
/////////////////////////////////// Local Parameters /////////////////////////////////////////
localparam [2:0]
FIFO_IDLE_STATE = 3'b000,
FIFO_REQUEST_CONFIG_STATE = 3'b001,
FIFO_READ_CONFIG_STATE = 3'b010,
FIFO_RUN_STATE = 3'b011,
FIFO_PURGE_STATE = 3'b100,
FIFO_DONE_STATE = 3'b101;
localparam [1:0]
POLL_IDLE_STATE = 2'b00,
POLL_REQUEST_STATE = 2'b01,
POLL_RESP_STATE = 2'b10,
POLL_VALID_STATE = 2'b11;
/////////////////////////////// FIFO Polling Logic /////////////////////////////////
/////////////////////////////// FIFO Status Logic /////////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
sizeInNumCL <= 0;
sizeInBytes <= 0;
fifo_buff_addr <= 0;
fifo_struct_base <= 0;
fifo_fsm_state <= 0;
fifo_tx_rd_valid <= 0;
fifo_tx_rd_addr <= 0;
fifo_tx_rd_tag <= 0;
otherSideUpdatedBytes <= 0;
poll_fsm_state <= 0;
poll_count <= 0;
fifo_done <= 1'b0;
update_status_threashold <= 1024;
poll_again <= 1'b0;
delay_poll_1 <= 1'b0;
end
else begin
poll_again <= (sizeInBytes == (numPushedBytes - otherSideUpdatedBytes)) & ~writes_finished;
delay_poll_1 <= 1'b0;
//
case (fifo_fsm_state)
FIFO_IDLE_STATE: begin
if (setup_fifo) begin
fifo_fsm_state <= FIFO_REQUEST_CONFIG_STATE;
fifo_struct_base <= fifo_base_addr;
end
fifo_done <= 1'b0;
end
FIFO_REQUEST_CONFIG_STATE: begin // This state enable reading the CRB configuration line
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= fifo_struct_base;
fifo_tx_rd_tag <= {1'b0, 8'b0};
fifo_fsm_state <= FIFO_READ_CONFIG_STATE;
end
FIFO_READ_CONFIG_STATE: begin // This state enable reading the CRB configuration line
if(fifo_tx_rd_ready) fifo_tx_rd_valid <= 1'b0;
if(fifo_rx_rd_valid) fifo_fsm_state <= FIFO_RUN_STATE;
fifo_buff_addr <= fifo_rx_data[63:6];
sizeInNumCL <= (fifo_rx_data[127:96] >> 6) - 1;
sizeInBytes <= fifo_rx_data[127:96];
update_status_threashold <= fifo_rx_data[159:128];
end
FIFO_RUN_STATE: begin // This state enable writing user generated to the Buffer
if(writes_finished) begin
fifo_fsm_state <= FIFO_PURGE_STATE;
end
fifo_tx_rd_tag <= {1'b0, 8'b0};
fifo_tx_rd_addr <= fifo_struct_base + `CRB_STRUCT_CONSUMER_LINE_OFFSET;
case (poll_fsm_state)
POLL_IDLE_STATE: begin
poll_fsm_state <= POLL_RESP_STATE;
fifo_tx_rd_valid <= 1'b1;
end
POLL_REQUEST_STATE: begin // This state enable reading the producer status line
if( poll_count == POLL_CYCLES) begin
fifo_tx_rd_valid <= 1'b1;
poll_fsm_state <= POLL_RESP_STATE;
end
poll_count <= poll_count + 1'b1;
end
POLL_RESP_STATE: begin
if(fifo_tx_rd_ready) fifo_tx_rd_valid <= 1'b0;
if(fifo_rx_rd_valid) begin
poll_fsm_state <= POLL_VALID_STATE;
otherSideUpdatedBytes <= fifo_rx_data[63:32];
delay_poll_1 <= 1'b1;
end
poll_count <= 0;
end
POLL_VALID_STATE: begin
if(poll_again & ~delay_poll_1) begin
poll_fsm_state <= POLL_REQUEST_STATE;
end
end
endcase
end
FIFO_PURGE_STATE: begin
if( (fifo_tx_wr_ready & fifo_tx_wr_valid) | ~fifo_tx_wr_valid) begin
fifo_fsm_state <= FIFO_DONE_STATE;
end
end
FIFO_DONE_STATE: begin
if(fifo_tx_wr_ready & last_state_set) begin
fifo_fsm_state <= FIFO_IDLE_STATE;
fifo_done <= 1'b1;
end
end
endcase
end
end
assign all_writes_done = writes_sent == writes_done;
/////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n)begin
writes_sent <= 0;
writes_done <= 0;
end
else begin
if( fifo_tx_wr_valid & fifo_tx_wr_ready) begin
writes_sent <= writes_sent + 1'b1;
end
if( fifo_rx_wr_valid ) begin
writes_done <= writes_done + 1'b1;
end
end
end
always@(posedge clk) begin
if(~rst_n)begin
writtenBytes <= 0;
end
else if(fifo_rx_wr_valid & fifo_rx_wr_tag[USER_TAG+1]) begin
writtenBytes <= writtenBytes + 64;
end
end
//////////////////////////////////////////////////////////////////////////////////////
///////////////////////////// FIFO Consumer Status Update ////////////////////////////
////////////////////////////// TX WR Requests Generation ////////////////////////////
//assign update_check = (writtenBytes - lastUpdatedBytes) >= update_status_threashold;
assign updateBytes = (issue_last_state)? numPushedBytes : lastUpdatedBytes + update_status_threashold;
assign updateStatus_fifo_re = ((fifo_fsm_state == FIFO_RUN_STATE) | (fifo_fsm_state == FIFO_DONE_STATE)) & ~write_response_pending;
always @(posedge clk) begin
if(~rst_n) begin
lastUpdatedBytes <= 0;
update_check <= 0;
update_check_set <= 1'b0;
end
else begin
update_check <= (writtenBytes - lastUpdatedBytes) >= update_status_threashold;
update_check_set <= 1'b0;
if(((update_check & ~update_check_set) | issue_last_state) & ~updateStatus_fifo_full) begin
lastUpdatedBytes <= updateBytes;
update_check_set <= 1'b1;
end
end
end
/*
*/
always @(posedge clk) begin
if(~rst_n) begin
updateStatus_fifo_dout <= 0;
updateStatus_fifo_valid <= 1'b0;
end
else begin
if(updateStatus_fifo_re) begin
updateStatus_fifo_valid <= 1'b0;
end
if(~updateStatus_fifo_full & ((update_check & ~update_check_set) | issue_last_state)) begin
updateStatus_fifo_dout <= {issue_last_state, updateBytes};
updateStatus_fifo_valid <= 1'b1;
end
end
end
assign updateStatus_fifo_full = updateStatus_fifo_valid;
/*
quick_fifo #(.FIFO_WIDTH(33),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) updateStatus_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({issue_last_state, updateBytes}),
.we ((update_check & ~update_check_set) | issue_last_state),
.re (updateStatus_fifo_re),
.dout (updateStatus_fifo_dout),
.empty (),
.valid (updateStatus_fifo_valid),
.full (updateStatus_fifo_full),
.count (),
.almostfull ()
);
*/
always @(posedge clk) begin
if(~rst_n) begin
fifo_tx_wr_addr <= 0;
fifo_tx_wr_valid <= 0;
fifo_tx_wr_tag <= 0;
fifo_tx_data <= 0;
write_response_pending <= 0;
last_state_set <= 0;
numPushedBytes <= 0;
usr_wr_count <= 0;
space_available <= 0;
end
else begin
space_available <= (numPushedBytes - otherSideUpdatedBytes) < sizeInBytes;
if(fifo_rx_wr_valid & ~fifo_rx_wr_tag[USER_TAG+1])
write_response_pending <= 1'b0;
else if(fifo_tx_wr_ready & fifo_tx_wr_valid & ~fifo_tx_wr_tag[USER_TAG+1])
write_response_pending <= 1'b1;
if(fifo_tx_wr_ready) begin
if((fifo_fsm_state == FIFO_RUN_STATE) | (fifo_fsm_state == FIFO_DONE_STATE)) begin
if(updateStatus_fifo_valid & ~write_response_pending) begin
last_state_set <= updateStatus_fifo_dout[32];
fifo_tx_data <= {415'b0, updateStatus_fifo_dout[32], 32'b0, updateStatus_fifo_dout[31:0], usr_wr_count};
fifo_tx_wr_addr <= fifo_struct_base + `CRB_STRUCT_PRODUCER_LINE_OFFSET;
fifo_tx_wr_tag <= {2'b00, usr_tx_wr_tag};
fifo_tx_wr_valid <= 1'b1;
end
else begin
fifo_tx_wr_addr <= fifo_buff_addr + usr_wr_count;
fifo_tx_wr_valid <= usr_tx_wr_valid & space_available;
fifo_tx_wr_tag <= {2'b10, usr_tx_wr_tag};
fifo_tx_data <= usr_tx_data;
if(usr_tx_wr_valid & space_available) begin
if(usr_wr_count == sizeInNumCL) begin
usr_wr_count <= 0;
end
else begin
usr_wr_count <= usr_wr_count + 1'b1;
end
numPushedBytes <= numPushedBytes + 64;
space_available <= (numPushedBytes - otherSideUpdatedBytes) < (sizeInBytes-64);
end
end
end
else if(fifo_fsm_state == FIFO_IDLE_STATE) begin
fifo_tx_wr_addr <= usr_tx_wr_addr;
fifo_tx_wr_valid <= usr_tx_wr_valid;
fifo_tx_wr_tag <= {2'b10, usr_tx_wr_tag};
fifo_tx_data <= usr_tx_data;
end
end
end
end
assign issue_last_state = (fifo_fsm_state == FIFO_DONE_STATE) & ~updateStatus_fifo_full & all_writes_done;
assign usr_tx_wr_ready = (fifo_fsm_state == FIFO_IDLE_STATE)?
fifo_tx_wr_ready:
fifo_tx_wr_ready & space_available & ~(updateStatus_fifo_valid & ~write_response_pending) & (fifo_fsm_state == FIFO_RUN_STATE);
assign usr_rx_wr_valid = fifo_rx_wr_valid & fifo_rx_wr_tag[USER_TAG+1];
assign usr_rx_wr_tag = fifo_rx_wr_tag[USER_TAG-1:0];
endmodule |
module AFU #(parameter AFU_OPERATOR = `UNDEF_AFU, // AFU Common parameters
parameter MAX_AFU_CONFIG_WIDTH = 1536,
parameter USER_RD_TAG = `AFU_TAG,
parameter USER_WR_TAG = `AFU_TAG,
//------ AFU Specific Paramters ----//
parameter DATA_WIDTH_IN = 4,
parameter DATA_WIDTH_OUT = 4,
parameter USER_AFU_PARAMETER1 = 1,
parameter USER_AFU_PARAMETER2 = 1
) (
input wire clk,
input wire Clk_400,
input wire rst_n,
//-------------------------------------------------//
input wire start_um,
input wire [MAX_AFU_CONFIG_WIDTH-1:0] um_params,
output wire um_done,
output wire [`NUM_USER_STATE_COUNTERS*32-1:0] um_state_counters,
output wire um_state_counters_valid,
// TX RD
output wire [57:0] um_tx_rd_addr,
output wire [USER_RD_TAG-1:0] um_tx_rd_tag,
output wire um_tx_rd_valid,
input wire um_tx_rd_ready,
// TX WR
output wire [57:0] um_tx_wr_addr,
output wire [USER_WR_TAG-1:0] um_tx_wr_tag,
output wire um_tx_wr_valid,
output wire [511:0] um_tx_data,
input wire um_tx_wr_ready,
// RX RD
input wire [USER_RD_TAG-1:0] um_rx_rd_tag,
input wire [511:0] um_rx_data,
input wire um_rx_rd_valid,
output wire um_rx_rd_ready,
// RX WR
input wire um_rx_wr_valid,
input wire [USER_WR_TAG-1:0] um_rx_wr_tag
);
generate
if (AFU_OPERATOR == `REGEX_AFU) begin
regex_mdb regex_mdb(
.clk (clk),
.Clk_400 (Clk_400),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[1023:0]),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
end
else if ((AFU_OPERATOR == `SKYLINE256_AFU) | (AFU_OPERATOR == `SKYLINE128_AFU) | (AFU_OPERATOR == `SKYLINE64_AFU) ) begin
skyline #(.NUM_CORES(USER_AFU_PARAMETER1),
.NUM_DIMENSIONS(USER_AFU_PARAMETER2))
skyline_0(
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[1535:0]),
.um_done (um_done),
.um_state_counters (um_state_counters),
.um_state_counters_valid (um_state_counters_valid),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
end
else if (AFU_OPERATOR == `COPY32_AFU) begin
copy copy (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `TEST_AND_COUNT_AFU) begin
test_count test_count (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `SELECTION) begin
selection selection (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `SGD_AFU) begin
sgd sgd (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[1535:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `MAX_MIN_SUM_AFU) begin
minmaxsum minmaxsum (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `PERCENTAGE_AFU) begin
precentage_um precentage_um (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else if (AFU_OPERATOR == `MAC_AFU) begin
addmul addmul (
.clk (clk),
.rst_n (rst_n),
//-------------------------------------------------//
.start_um (start_um),
.um_params (um_params[511:0]),
.um_done (um_done),
// User Module TX RD
.um_tx_rd_addr (um_tx_rd_addr),
.um_tx_rd_tag (um_tx_rd_tag),
.um_tx_rd_valid (um_tx_rd_valid),
.um_tx_rd_ready (um_tx_rd_ready),
// User Module TX WR
.um_tx_wr_addr (um_tx_wr_addr),
.um_tx_wr_tag (um_tx_wr_tag),
.um_tx_wr_valid (um_tx_wr_valid),
.um_tx_data (um_tx_data),
.um_tx_wr_ready (um_tx_wr_ready),
// User Module RX RD
.um_rx_rd_tag (um_rx_rd_tag),
.um_rx_data (um_rx_data),
.um_rx_rd_valid (um_rx_rd_valid),
.um_rx_rd_ready (um_rx_rd_ready),
// User Module RX WR
.um_rx_wr_valid (um_rx_wr_valid),
.um_rx_wr_tag (um_rx_wr_tag)
);
assign um_state_counters_valid = 1'b0;
end
else begin
assign um_tx_rd_valid = 1'b0;
assign um_tx_wr_valid = 1'b0;
assign um_rd_done = 1'b0;
assign um_wr_done = 1'b0;
assign um_state_counters_valid = 1'b0;
end
endgenerate
endmodule // AFU |
module quick_fifo #(
parameter FIFO_WIDTH = 32,
parameter FIFO_DEPTH_BITS = 8,
parameter FIFO_ALMOSTFULL_THRESHOLD = 2**FIFO_DEPTH_BITS - 4
) (
input wire clk,
input wire reset_n,
input wire we, // input write enable
input wire [FIFO_WIDTH - 1:0] din, // input write data with configurable width
input wire re, // input read enable
output reg valid, // dout valid
output reg [FIFO_WIDTH - 1:0] dout, // output read data with configurable width
output reg [FIFO_DEPTH_BITS - 1:0] count, // output FIFOcount
output reg empty, // output FIFO empty
output reg full, // output FIFO full
output reg almostfull // output configurable programmable full/ almost full
);
reg [FIFO_DEPTH_BITS - 1:0] rp = 0;
reg [FIFO_DEPTH_BITS - 1:0] wp = 0;
reg [FIFO_DEPTH_BITS - 1:0] mem_count = 0; // output FIFOcount
reg mem_empty = 1'b1;
reg valid_t1 = 0, valid_t2 = 0;
reg valid0 = 0;
wire remem;
wire wemem;
wire remem_valid;
wire [FIFO_WIDTH-1:0] dout_mem;
assign remem = (re & valid_t1 & valid_t2) | ~(valid_t1 & valid_t2);
assign wemem = we & ~full;
assign remem_valid = remem & ~mem_empty;
spl_sdp_mem #(.DATA_WIDTH(FIFO_WIDTH),
.ADDR_WIDTH(FIFO_DEPTH_BITS)) fifo_mem(
.clk (clk),
.we (wemem),
.re (remem),
.raddr (rp),
.waddr (wp),
.din (din),
.dout (dout_mem)
);
// data
always @(posedge clk) begin
dout <= (valid_t2)? ((re)? dout_mem : dout) : dout_mem;
end
// valids, flags
always @(posedge clk) begin
if (~reset_n) begin
empty <= 1'b1;
full <= 1'b0;
almostfull <= 1'b0;
count <= 0; //32'b0;
rp <= 0;
wp <= 0;
valid_t2 <= 1'b0;
valid_t1 <= 1'b0;
mem_empty <= 1'b1;
mem_count <= 'b0;
//dout <= 0;
valid <= 0;
valid0 <= 0;
end
else begin
valid <= (valid)? ((re)? valid0 : 1'b1) : valid0;
valid0 <= (remem)? ~mem_empty : valid0;
valid_t2 <= (valid_t2)? ((re)? valid_t1 : 1'b1) : valid_t1;
valid_t1 <= (remem)? ~mem_empty : valid_t1;
rp <= (remem & ~mem_empty)? (rp + 1'b1) : rp;
wp <= (wemem)? (wp + 1'b1) : wp;
// mem_empty
if (we) mem_empty <= 1'b0;
else if(remem & (mem_count == 1'b1)) mem_empty <= 1'b1;
// mem_count
if( wemem & ~remem_valid) mem_count <= mem_count + 1'b1;
else if (~wemem & remem_valid) mem_count <= mem_count - 1'b1;
// empty
if (we) empty <= 1'b0;
else if((re & valid_t2 & ~valid_t1) & (count == 1'b1)) empty <= 1'b1;
// count
if( wemem & (~(re & valid_t2) | ~re) ) count <= count + 1'b1;
else if (~wemem & (re & valid_t2)) count <= count - 1'b1;
//
if (we & ~re) begin
if (count == (2**FIFO_DEPTH_BITS-1))
full <= 1'b1;
if (count == (FIFO_ALMOSTFULL_THRESHOLD-1))
almostfull <= 1'b1;
end
//
if ((~we | full) & re) begin //
full <= 1'b0;
if (count == FIFO_ALMOSTFULL_THRESHOLD)
almostfull <= 1'b0;
end
end
end
endmodule |
module spl_sdp_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
input wire we,
input wire re,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [DATA_WIDTH-1:0] din,
output reg [DATA_WIDTH-1:0] dout
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "no_rw_check" *) reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we)
mem[waddr] <= din;
if (re)
dout <= mem[raddr];
end
endmodule |
module spl_pt_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
// port 0, read/write
input wire we0,
input wire re0,
input wire [ADDR_WIDTH-1:0] addr0,
input wire [DATA_WIDTH-1:0] din0,
output reg [DATA_WIDTH-1:0] dout0,
// port 1, read only
input wire re1,
input wire [ADDR_WIDTH-1:0] addr1,
output reg [DATA_WIDTH-1:0] dout1
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "AUTO, no_rw_check" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we0)
mem[addr0] <= din0;
if (re0)
dout0 <= mem[addr0];
if (re1)
dout1 <= mem[addr1];
end
endmodule |
module io_requester(
input clk,
input rst_n,
////////////////// io_requester <--> arbiter
// RD TX
output wire cor_tx_rd_ready,
input wire cor_tx_rd_valid,
input wire [70:0] cor_tx_rd_hdr,
// WR TX
output wire cor_tx_wr_ready,
input wire cor_tx_wr_valid,
input wire [74:0] cor_tx_wr_hdr,
input wire [511:0] cor_tx_data,
//////////////////// io_requester <--> server_io
// TX_RD request,
input wire rq_tx_rd_ready,
output reg rq_tx_rd_valid,
output reg [44:0] rq_tx_rd_hdr,
// TX_WR request
input wire rq_tx_wr_ready,
output reg rq_tx_wr_valid,
output reg [48:0] rq_tx_wr_hdr,
output reg [511:0] rq_tx_data,
///////////////////// io_requester <--> pagetable
// afu_virt_waddr --> afu_phy_waddr
output reg [57:0] afu_virt_wr_addr,
output reg pt_re_wr,
input wire [31:0] afu_phy_wr_addr,
input wire afu_phy_wr_addr_valid,
// afu_virt_raddr --> afu_phy_raddr
output reg [57:0] afu_virt_rd_addr,
output reg pt_re_rd,
input wire [31:0] afu_phy_rd_addr,
input wire afu_phy_rd_addr_valid
);
wire trq_empty;
wire [4:0] trq_count;
wire trq_full;
wire trq_valid;
wire [44:0] trq_dout;
wire twq_empty;
wire [4:0] twq_count;
wire twq_full;
wire twq_valid;
wire [560:0] twq_dout;
reg [31:0] rd_cnt;
reg [511:0] afu_virt_wr_data_d0;
reg [74:0] afu_virt_wr_hdr_d0;
reg afu_virt_wr_valid_d0;
reg [511:0] afu_virt_wr_data_d1;
reg [74:0] afu_virt_wr_hdr_d1;
reg afu_virt_wr_valid_d1;
reg [511:0] afu_virt_wr_data_d2;
reg [74:0] afu_virt_wr_hdr_d2;
reg afu_virt_wr_valid_d2;
reg [511:0] afu_virt_wr_data_d3;
reg [74:0] afu_virt_wr_hdr_d3;
reg afu_virt_wr_valid_d3;
reg [70:0] afu_virt_rd_hdr_d0;
reg afu_virt_rd_valid_d0;
reg [70:0] afu_virt_rd_hdr_d1;
reg afu_virt_rd_valid_d1;
reg [70:0] afu_virt_rd_hdr_d2;
reg afu_virt_rd_valid_d2;
reg [70:0] afu_virt_rd_hdr_d3;
reg afu_virt_rd_valid_d3;
//-------------------------------------------------
always @(posedge clk) begin
if( ~rst_n ) begin
rd_cnt <= 32'b0;
end
else if (rq_tx_rd_valid) begin
rd_cnt <= rd_cnt +1'b1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX RD Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_rd_ready = ~trq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_rd_valid <= 0;
rq_tx_rd_hdr <= 0;
end
else if(rq_tx_rd_ready) begin
rq_tx_rd_valid <= trq_valid;
rq_tx_rd_hdr <= trq_dout;
end
end
// TX_RD transmit queue
quick_fifo #(.FIFO_WIDTH(45), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 - 8)
) txrd_queue(
.clk (clk),
.reset_n (rst_n),
.din (afu_virt_rd_hdr_d3[44:0]),
.we (afu_virt_rd_valid_d3),
.re (rq_tx_rd_ready),
.dout (trq_dout),
.empty (trq_empty),
.valid (trq_valid),
.full (),
.count (trq_count),
.almostfull (trq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_rd <= 0;
afu_virt_rd_addr <= 0;
afu_virt_rd_valid_d0 <= 0;
//afu_virt_rd_hdr_d0 <= 0;
// S1
afu_virt_rd_valid_d1 <= 0;
//afu_virt_rd_hdr_d1 <= 0;
// S2
afu_virt_rd_valid_d2 <= 0;
//afu_virt_rd_hdr_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= 0;
//afu_virt_rd_hdr_d3 <= 0;
end
else begin
pt_re_rd <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_addr <= cor_tx_rd_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_rd_valid_d0 <= cor_tx_rd_valid & cor_tx_rd_ready;
afu_virt_rd_hdr_d0 <= cor_tx_rd_hdr;
// S1
afu_virt_rd_valid_d1 <= afu_virt_rd_valid_d0;
afu_virt_rd_hdr_d1 <= afu_virt_rd_hdr_d0;
// S2
afu_virt_rd_valid_d2 <= afu_virt_rd_valid_d1;
afu_virt_rd_hdr_d2 <= afu_virt_rd_hdr_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_rd_valid_d3 <= afu_virt_rd_valid_d2;
afu_virt_rd_hdr_d3 <= {afu_phy_rd_addr, afu_virt_rd_hdr_d2[12:0]};
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// TX WR Channel ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign cor_tx_wr_ready = ~twq_full;
always@(posedge clk) begin
if(~rst_n) begin
rq_tx_wr_valid <= 0;
rq_tx_data <= 0;
rq_tx_wr_hdr <= 0;
end
else if(rq_tx_wr_ready) begin
rq_tx_wr_valid <= twq_valid;
rq_tx_data <= twq_dout[511:0];
rq_tx_wr_hdr <= twq_dout[560:512];
end
end
// TX_WR transmit queue
quick_fifo #(.FIFO_WIDTH(561), //
.FIFO_DEPTH_BITS(5),
.FIFO_ALMOSTFULL_THRESHOLD(2**5 -8)
) txwr_queue(
.clk (clk),
.reset_n (rst_n),
.din ({afu_virt_wr_hdr_d3[48:0], afu_virt_wr_data_d3}),
.we (afu_virt_wr_valid_d3),
.re (rq_tx_wr_ready),
.dout (twq_dout),
.empty (twq_empty),
.valid (twq_valid),
.full (),
.count (twq_count),
.almostfull (twq_full)
);
always@(posedge clk) begin
if( ~rst_n ) begin
pt_re_wr <= 0;
afu_virt_wr_addr <= 0;
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= 0;
afu_virt_wr_hdr_d0 <= 0;
afu_virt_wr_data_d0 <= 0;
// S1
afu_virt_wr_valid_d1 <= 0;
afu_virt_wr_hdr_d1 <= 0;
afu_virt_wr_data_d1 <= 0;
// S2
afu_virt_wr_valid_d2 <= 0;
afu_virt_wr_hdr_d2 <= 0;
afu_virt_wr_data_d2 <= 0;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= 0;
afu_virt_wr_hdr_d3 <= 0;
afu_virt_wr_data_d3 <= 0;
end
else begin
pt_re_wr <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_addr <= cor_tx_wr_hdr[70:13];
// PT pipeline stages delay
// S0
afu_virt_wr_valid_d0 <= cor_tx_wr_valid & cor_tx_wr_ready;
afu_virt_wr_hdr_d0 <= cor_tx_wr_hdr;
afu_virt_wr_data_d0 <= cor_tx_data;
// S1
afu_virt_wr_valid_d1 <= afu_virt_wr_valid_d0;
afu_virt_wr_hdr_d1 <= afu_virt_wr_hdr_d0;
afu_virt_wr_data_d1 <= afu_virt_wr_data_d0;
// S2
afu_virt_wr_valid_d2 <= afu_virt_wr_valid_d1;
afu_virt_wr_hdr_d2 <= afu_virt_wr_hdr_d1;
afu_virt_wr_data_d2 <= afu_virt_wr_data_d1;
// S3: PT response available at this cycle, compose it to store in the FIFO.
afu_virt_wr_valid_d3 <= afu_virt_wr_valid_d2;
afu_virt_wr_hdr_d3 <= { afu_virt_wr_hdr_d2[74:71], afu_phy_wr_addr, afu_virt_wr_hdr_d2[12:0]};
afu_virt_wr_data_d3 <= afu_virt_wr_data_d2;
end
end
endmodule |
module csr_file(
input wire clk,
input wire reset_n,
output wire spl_reset,
// csr_file --> dsm_module, spl_id, afu_id
output reg csr_spl_dsm_base_valid,
output reg [31:0] csr_spl_dsm_base,
input wire csr_spl_dsm_base_done,
output reg csr_afu_dsm_base_valid,
output reg [31:0] csr_afu_dsm_base,
input wire csr_afu_dsm_base_done,
// csr_file --> ctx_tracker, FPGA virtual memory space
output reg csr_ctx_base_valid,
output reg [31:0] csr_ctx_base,
input wire csr_ctx_base_done,
// server_io --> csr_file
input wire io_rx_csr_valid,
input wire [13:0] io_rx_csr_addr,
input wire [31:0] io_rx_csr_data
);
localparam [5:0]
SPL_CSR_DSR_BASEL = 6'b00_0000, // 1000 //10'h244, // 910
SPL_CSR_DSR_BASEH = 6'b00_0001, // 1004 //10'h245, // 914
SPL_CSR_CTX_BASELL = 6'b00_0010, // 1008 //10'h246, // 918
SPL_CSR_CTX_BASELH = 6'b00_0011, // 100c //10'h247; // 91c
SPL_CSR_CTRL = 6'b00_0100, // 1010 //10'h248, // 920
SPL_CSR_SCRATCH = 6'b11_1111; //10'h27f, // 9fc
localparam [5:0]
AFU_CSR_DSR_BASEL = 6'b00_0000, //10'h280, // a00
AFU_CSR_DSR_BASEH = 6'b00_0001, //10'h281, // a04
AFU_CSR_CTX_BASEL = 6'b00_0010, //10'h282, // a08
AFU_CSR_CTX_BASEH = 6'b00_0011, //10'h283, // a0c
AFU_CSR_SCRATCH = 6'b11_1111, //10'h2bf; // afc
AFU_CSR_CMD_OPCODE = 6'b00_1111;
reg [5:0] spl_dsr_base_hi;
reg [5:0] afu_dsr_base_hi;
reg csr_reset = 0;
reg csr_enable = 0;
assign spl_reset = csr_reset;
//--------------------------------------------------------------------
// RX - spl_csr<--spl_io
//--------------------------------------------------------------------
always @(posedge clk) begin
if (~reset_n) begin
csr_spl_dsm_base_valid <= 1'b0;
csr_afu_dsm_base_valid <= 1'b0;
csr_ctx_base_valid <= 1'b0;
spl_dsr_base_hi <= 0;
afu_dsr_base_hi <= 0;
csr_reset <= 0;
csr_enable <= 0;
end
else begin
csr_reset <= 1'b0;
csr_enable <= 0;
if ( csr_ctx_base_done ) csr_ctx_base_valid <= 1'b0;
if ( csr_spl_dsm_base_done ) csr_spl_dsm_base_valid <= 1'b0;
if ( csr_afu_dsm_base_done ) csr_afu_dsm_base_valid <= 1'b0;
if ( csr_spl_dsm_base_done ) spl_dsr_base_hi <= 0;
if ( csr_afu_dsm_base_done ) afu_dsr_base_hi <= 0;
if (io_rx_csr_valid) begin
if (io_rx_csr_addr[13:6] == 8'h10) begin
case (io_rx_csr_addr[5:0])
SPL_CSR_DSR_BASEH : begin
spl_dsr_base_hi <= io_rx_csr_data[5:0];
end
SPL_CSR_DSR_BASEL : begin
csr_spl_dsm_base_valid <= 1'b1;
csr_spl_dsm_base <= {spl_dsr_base_hi, io_rx_csr_data[31:6]};
end
SPL_CSR_CTX_BASELH : begin
csr_ctx_base[31:26] <= io_rx_csr_data[5:0];
end
SPL_CSR_CTX_BASELL : begin
csr_ctx_base[25:0] <= io_rx_csr_data[31:6];
csr_ctx_base_valid <= 1'b1;
end
SPL_CSR_CTRL : begin
csr_reset <= io_rx_csr_data[0];
csr_enable <= io_rx_csr_data[1];
end
endcase
end
else if (io_rx_csr_addr[13:6] == 8'h8a) begin
case (io_rx_csr_addr[5:0])
AFU_CSR_DSR_BASEH : begin
afu_dsr_base_hi <= io_rx_csr_data[5:0];
end
AFU_CSR_DSR_BASEL : begin
csr_afu_dsm_base_valid <= 1'b1;
csr_afu_dsm_base <= {afu_dsr_base_hi, io_rx_csr_data[31:6]};
end
endcase
end
end
end
end // rx csr
endmodule |
module pt_module (
input clk,
input rst_n,
///////////////////// pagetable <--> io_requester
// afu_virt_waddr --> afu_phy_waddr
input wire [57:0] afu_virt_wr_addr,
input wire pt_re_wr,
output wire [31:0] afu_phy_wr_addr,
output wire afu_phy_wr_addr_valid,
// afu_virt_raddr --> afu_phy_raddr
input wire [57:0] afu_virt_rd_addr,
input wire pt_re_rd,
output wire [31:0] afu_phy_rd_addr,
output wire afu_phy_rd_addr_valid,
////////////////////// pagetable <--> server_io
// pt tx_rd, rx_rd
output wire [31:0] pt_tx_rd_addr,
output wire [`PAGETABLE_TAG-1:0] pt_tx_rd_tag,
output wire pt_tx_rd_valid,
input wire pt_tx_rd_ready,
input wire [255:0] pt_rx_data,
input wire [`PAGETABLE_TAG-1:0] pt_rx_rd_tag,
input wire pt_rx_rd_valid,
/////////////////////// pagetable <--> cmd_server
output wire [1:0] pt_status,
input wire pt_update,
input wire [31:0] pt_base_addr,
output reg [`PTE_WIDTH-1:0] first_page_base_addr,
output reg first_page_base_addr_valid,
output reg [57:0] ws_virt_base_addr,
output reg ws_virt_base_addr_valid
);
wire [`PT_ADDRESS_BITS-1:0] afu_virt_raddr;
reg [31:0] afu_tx_rel_raddr_d1;
reg [32-`PTE_WIDTH-1:0] afu_tx_rel_raddr_d2;
reg pt_re_rd_d1;
reg pt_re_rd_d2;
reg [31:0] afu_tx_rel_waddr_d1;
reg [32-`PTE_WIDTH-1:0] afu_tx_rel_waddr_d2;
reg pt_re_wr_d1;
reg pt_re_wr_d2;
wire tr_pt_re;
reg pt_we;
wire [`PT_ADDRESS_BITS-1:0] pt_addr0;
reg [`PT_ADDRESS_BITS-1:0] pt_waddr0;
reg [`PT_ADDRESS_BITS-1:0] pt_waddr1;
reg [`PTE_WIDTH-1:0] pt_din;
wire [`PTE_WIDTH-1:0] tr_pt_dout;
wire tw_pt_re;
wire [`PT_ADDRESS_BITS-1:0] tw_pt_raddr;
wire [`PTE_WIDTH-1:0] tw_pt_dout;
reg [2:0] pt_state;
reg [31:0] pt_base;
reg [41:0] afu_vir_base;
reg [`PT_ADDRESS_BITS-1:0] pt_raddr;
reg [`PT_ADDRESS_BITS:0] pt_rd_cnt;
reg [`PT_ADDRESS_BITS:0] pt_wr_cnt;
reg [31:0] pt_base_inc;
reg [255:0] pt_rx_data_reg;
reg [`PAGETABLE_TAG-1:0] pt_rx_rd_tag_reg;
reg pt_rx_rd_valid_reg;
localparam [2:0]
PT_FREE_STATE = 3'b000,
PT_CONFIG_REQ_STATE = 3'b001,
PT_CONFIG_READ_STATE = 3'b010,
PT_LOADING_STATE = 3'b011,
PT_VALID_STATE = 3'b100;
////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
pt_rx_data_reg <= 0;
pt_rx_rd_tag_reg <= 0;
pt_rx_rd_valid_reg <= 0;
end
else begin
pt_rx_data_reg <= pt_rx_data;
pt_rx_rd_tag_reg <= pt_rx_rd_tag;
pt_rx_rd_valid_reg <= pt_rx_rd_valid;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// Pagetable TX RD ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////
assign pt_tx_rd_valid = (pt_state == PT_CONFIG_REQ_STATE) |
((pt_state == PT_LOADING_STATE) & (|pt_rd_cnt));
assign pt_tx_rd_addr = (pt_state == PT_CONFIG_REQ_STATE)? pt_base : pt_base_inc;
assign pt_tx_rd_tag = (pt_state == PT_CONFIG_REQ_STATE)? 'b0 : 'b1;
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// Pagetable Status ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// page table
spl_pt_mem #(.ADDR_WIDTH (`PT_ADDRESS_BITS),
.DATA_WIDTH (`PTE_WIDTH)
) pagetable (
.clk (clk),
.we0 (pt_we),
.addr0 (pt_addr0),
.din0 (pt_din),
.re0 (tr_pt_re),
.dout0 (tr_pt_dout),
.re1 (tw_pt_re),
.addr1 (tw_pt_raddr),
.dout1 (tw_pt_dout)
);
always@(posedge clk) begin
if( ~rst_n) begin
pt_we <= 0;
pt_din <= 0;
pt_waddr0 <= 0;
pt_waddr1 <= 0;
end
else begin
pt_we <= 1'b0;
if(pt_rx_rd_valid_reg & (pt_state == PT_LOADING_STATE)) begin
pt_we <= 1'b1;
pt_waddr0 <= pt_waddr0 + 1'b1;
pt_waddr1 <= pt_waddr0;
end
pt_din <= pt_rx_data_reg[37:38-`PTE_WIDTH];
end
end
assign pt_addr0 = (pt_state == PT_LOADING_STATE)? pt_waddr1 : afu_virt_raddr;
assign pt_status = {1'b0, (pt_state == PT_VALID_STATE)};
/////////////////////////////////////////////////////
always@(posedge clk) begin
if( ~rst_n) begin
pt_state <= 3'b000;
pt_base <= 32'b0;
first_page_base_addr_valid <= 0;
first_page_base_addr <= 0;
afu_vir_base <= 0;
pt_base_inc <= 0;
pt_rd_cnt <= 0;
pt_wr_cnt <= 0;
ws_virt_base_addr <= 0;
ws_virt_base_addr_valid <= 1'b0;
end
else begin
case( pt_state )
PT_FREE_STATE: begin
pt_state <= (pt_update)? PT_CONFIG_REQ_STATE : PT_FREE_STATE;
pt_base <= pt_base_addr;
ws_virt_base_addr_valid <= 1'b0;
end
PT_CONFIG_REQ_STATE: begin
pt_state <= (pt_tx_rd_ready)? PT_CONFIG_READ_STATE : PT_CONFIG_REQ_STATE;
end
PT_CONFIG_READ_STATE: begin
if(pt_rx_rd_valid_reg) begin
pt_state <= PT_LOADING_STATE;
pt_base <= pt_rx_data_reg[37:6];
afu_vir_base <= pt_rx_data_reg[111:70];
pt_base_inc <= pt_rx_data_reg[37:6];
pt_rd_cnt <= pt_rx_data_reg[160+`PT_ADDRESS_BITS:160];
pt_wr_cnt <= pt_rx_data_reg[160+`PT_ADDRESS_BITS:160];
ws_virt_base_addr <= pt_rx_data_reg[127:70];
ws_virt_base_addr_valid <= 1'b1;
end
end
PT_LOADING_STATE: begin
pt_state <= ((|pt_rd_cnt) | (|pt_wr_cnt))? PT_LOADING_STATE : PT_VALID_STATE;
if(pt_tx_rd_ready & (|pt_rd_cnt)) begin
pt_rd_cnt <= pt_rd_cnt - 1'b1;
pt_base_inc <= pt_base_inc + 1'b1;
end
//
if(pt_rx_rd_valid_reg) begin
pt_wr_cnt <= pt_wr_cnt - 1'b1;
first_page_base_addr_valid <= 1'b1;
if(~first_page_base_addr_valid) begin
first_page_base_addr <= pt_rx_data_reg[37:38-`PTE_WIDTH];
end
end
end
PT_VALID_STATE: begin
pt_state <= PT_VALID_STATE;
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// WR Addr Translator ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign tw_pt_re = pt_re_wr_d1;
assign tw_pt_raddr = afu_tx_rel_waddr_d1[32-`PTE_WIDTH+`PT_ADDRESS_BITS-1:32-`PTE_WIDTH];
assign afu_phy_wr_addr = {tw_pt_dout, afu_tx_rel_waddr_d2};
assign afu_phy_wr_addr_valid = pt_re_wr_d2;
always@(posedge clk) begin
if( ~rst_n) begin
afu_tx_rel_waddr_d1 <= 0;
afu_tx_rel_waddr_d2 <= 0;
pt_re_wr_d1 <= 1'b0;
pt_re_wr_d2 <= 1'b0;
end
else begin
// Stage 1 of the pipline
afu_tx_rel_waddr_d1 <= (afu_virt_wr_addr[31:0] - afu_vir_base[31:0]);
pt_re_wr_d1 <= pt_re_wr;
// Stage 2 of the pipline
afu_tx_rel_waddr_d2 <= afu_tx_rel_waddr_d1[32-`PTE_WIDTH-1:0];
pt_re_wr_d2 <= pt_re_wr_d1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// //////////////////////////////////
////////////////////////////// RD Addr Translator ///////////////////////////////
///////////////////////////////// //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
assign tr_pt_re = pt_re_rd_d1;
assign afu_virt_raddr = afu_tx_rel_raddr_d1[32-`PTE_WIDTH+`PT_ADDRESS_BITS-1:32-`PTE_WIDTH];
assign afu_phy_rd_addr = {tr_pt_dout, afu_tx_rel_raddr_d2};
assign afu_phy_rd_addr_valid = pt_re_rd_d2;
always@(posedge clk) begin
if( ~rst_n) begin
afu_tx_rel_raddr_d1 <= 0;
afu_tx_rel_raddr_d2 <= 0;
pt_re_rd_d1 <= 1'b0;
pt_re_rd_d2 <= 1'b0;
end
else begin
// Stage 1 of the pipline
afu_tx_rel_raddr_d1 <= afu_virt_rd_addr[31:0] - afu_vir_base[31:0];
pt_re_rd_d1 <= pt_re_rd;
// Stage 2 of the pipline
afu_tx_rel_raddr_d2 <= afu_tx_rel_raddr_d1[32-`PTE_WIDTH-1:0];
pt_re_rd_d2 <= pt_re_rd_d1;
end
end
endmodule |
module pipeline_agent
(
input wire clk,
input wire rst_n,
// Pipelining request
input wire find_pipeline_schedule,
input wire direct_pipeline_schedule,
input wire [0:`NUMBER_OF_FTHREADS-1] fthreads_state,
input wire [0:`NUMBER_OF_FTHREADS-1] src_job_fthread_mapping,
input wire [0:`NUMBER_OF_FTHREADS-1] dst_job_fthread_mapping,
// Pipeline Schedule decision
output reg [0:`NUMBER_OF_FTHREADS-1] src_fthread_select,
output reg [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select,
output reg dst_fthread_reserve,
output reg pipeline_schedule_valid
);
wire [0:`NUMBER_OF_FTHREADS-1] dst_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_src_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] src_job_mapping_shifted;
wire [0:`NUMBER_OF_FTHREADS-1] pipeline_dst_job_mapping;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_dst;
wire [0:`NUMBER_OF_FTHREADS-1] valid_pipeline_mapping_both;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_b;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_s;
wire [0:`NUMBER_OF_FTHREADS-1] src_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_a;
wire [0:`NUMBER_OF_FTHREADS-1] dst_fthread_select_r;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_src;
wire [0:`NUMBER_OF_FTHREADS-1] valid_mapping_dst;
genvar k;
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Memory Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
generate if(`NUMBER_OF_FTHREADS > 1) begin
// any valid mapping
assign valid_mapping_src = src_job_fthread_mapping & ~fthreads_state;
assign valid_mapping_dst = dst_job_fthread_mapping & ~fthreads_state;
// src schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_a
assign src_fthread_select_a[k] = valid_mapping_src[k] & ~(|(valid_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_a[1] = valid_mapping_src[1] & ~valid_mapping_src[0];
assign src_fthread_select_a[0] = valid_mapping_src[0];
// dst schedule decision
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_a
assign dst_fthread_select_a[k] = valid_mapping_dst[k] & ~(|(valid_mapping_dst[0:k-1]));
end
//endgenerate
assign dst_fthread_select_a[1] = valid_mapping_dst[1] & ~valid_mapping_dst[0];
assign dst_fthread_select_a[0] = valid_mapping_dst[0];
// dst schedule reserve
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_dst_r
assign dst_fthread_select_r[k] = dst_job_fthread_mapping[k] & ~(|(dst_job_fthread_mapping[0:k-1]));
end
//endgenerate
assign dst_fthread_select_r[1] = dst_job_fthread_mapping[1] & ~dst_job_fthread_mapping[0];
assign dst_fthread_select_r[0] = dst_job_fthread_mapping[0];
///////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// ///////////////////////////////
/////////////////////////////// Direct Pipeline Schedule Decision /////////////////////////////
////////////////////////////////// ///////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
// Check if at least the src can be mapped
assign dst_job_mapping_shifted = {dst_job_fthread_mapping[1:`NUMBER_OF_FTHREADS-1], 1'b0};
assign pipeline_src_job_mapping = dst_job_mapping_shifted & src_job_fthread_mapping;
assign valid_pipeline_mapping_src = pipeline_src_job_mapping & ~fthreads_state;
// check if at least dst can be mapped
assign src_job_mapping_shifted = {1'b0, src_job_fthread_mapping[0:`NUMBER_OF_FTHREADS-2]};
assign pipeline_dst_job_mapping = src_job_mapping_shifted & dst_job_fthread_mapping;
assign valid_pipeline_mapping_dst = pipeline_dst_job_mapping & ~fthreads_state;
// Check if both src and dst can be mapped
assign valid_pipeline_mapping_both = {valid_pipeline_mapping_dst[1:`NUMBER_OF_FTHREADS-1], 1'b0} &
valid_pipeline_mapping_src;
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping for both src & dst
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_b
assign src_fthread_select_b[k] = valid_pipeline_mapping_both[k] & ~(|(valid_pipeline_mapping_both[0:k-1]));
end
//endgenerate
assign src_fthread_select_b[1] = valid_pipeline_mapping_both[1] & ~valid_pipeline_mapping_both[0];
assign src_fthread_select_b[0] = valid_pipeline_mapping_both[0];
//---------------------------------------------------------------------------------------------------//
// dst schedule decision based on valid mapping for both src & dst
assign dst_fthread_select_b = {1'b0, src_fthread_select_b[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
// src schedule decision based on valid mapping at least for src
//generate
for ( k = `NUMBER_OF_FTHREADS-1; k >1 ; k = k-1) begin: ft_selected_src_s
assign src_fthread_select_s[k] = valid_pipeline_mapping_src[k] & ~(|(valid_pipeline_mapping_src[0:k-1]));
end
//endgenerate
assign src_fthread_select_s[1] = valid_pipeline_mapping_src[1] & ~valid_pipeline_mapping_src[0];
assign src_fthread_select_s[0] = valid_pipeline_mapping_src[0];
//---------------------------------------------------------------------------------------------------//
// dst reserved
assign dst_fthread_select_s = {1'b0, src_fthread_select_s[0:`NUMBER_OF_FTHREADS-2]};
//---------------------------------------------------------------------------------------------------//
always @(posedge clk) begin
if (~rst_n) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
else begin
if(direct_pipeline_schedule) begin
if (|src_fthread_select_b) begin
src_fthread_select <= src_fthread_select_b;
dst_fthread_select <= dst_fthread_select_b;
dst_fthread_reserve <= 1'b0;
end
else begin
src_fthread_select <= src_fthread_select_s;
dst_fthread_select <= dst_fthread_select_s;
dst_fthread_reserve <= 1'b1;
end
end
else begin
src_fthread_select <= src_fthread_select_a;
dst_fthread_select <= 0;
dst_fthread_reserve <= 1'b0;
if(|src_fthread_select_a) begin
if(|dst_fthread_select_a) begin
dst_fthread_select <= dst_fthread_select_a;
end
else begin
dst_fthread_select <= dst_fthread_select_r;
dst_fthread_reserve <= 1'b1;
end
end
end
pipeline_schedule_valid <= find_pipeline_schedule;
end
end
end
else begin
always @(posedge clk) begin
src_fthread_select <= 0;
dst_fthread_select <= 0;
dst_fthread_reserve <= 0;
pipeline_schedule_valid <= 0;
end
end
endgenerate
endmodule |
module job_queue #(parameter POLL_CYCLES = 32)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire start_queue,
input wire [31:0] queue_base_addr,
input wire [31:0] queue_size, // in CLs
input wire [15:0] queue_poll_rate,
input wire queue_reset,
// TX RD
output reg [31:0] jq_tx_rd_addr,
output reg [`JOB_QUEUE_TAG-1:0] jq_tx_rd_tag,
output reg jq_tx_rd_valid,
input wire jq_tx_rd_ready,
// TX WR
output reg [31:0] jq_tx_wr_addr,
output reg [`JOB_QUEUE_TAG-1:0] jq_tx_wr_tag,
output reg jq_tx_wr_valid,
output reg [511:0] jq_tx_data,
input wire jq_tx_wr_ready,
// RX RD
input wire [`JOB_QUEUE_TAG-1:0] jq_rx_rd_tag,
input wire [511:0] jq_rx_data,
input wire jq_rx_rd_valid,
// RX WR
input wire jq_rx_wr_valid,
input wire [`JOB_QUEUE_TAG-1:0] jq_rx_wr_tag,
///////////////////////// User Logic Interface ////////////////////
output reg [511:0] job_queue_out,
output reg job_queue_valid,
input wire job_queue_ready
);
///////////////////////////////// Wires Declarations ////////////////////////////
wire update_status;
wire [15:0] rd_cnt_inc;
/////////////////////////////////////// Reg Declarations /////////////////////////
reg [31:0] numPulledJobs;
reg [31:0] numAvailableJobs;
reg [15:0] queue_buffer_size;
reg [15:0] rd_cnt;
reg [15:0] prog_poll_cycles;
reg [15:0] poll_count;
reg [31:0] queue_struct_base;
reg [31:0] queue_buffer_base;
reg [2:0] jq_fsm_state;
reg last_req_d1;
reg [5:0] rx_rd_tag;
reg [511:0] rx_rd_data;
reg rx_rd_valid;
reg rx_wr_valid;
reg [7:0] rx_wr_tag;
reg write_response_pending;
reg [31:0] lastUpdatedJobs;
reg jq_producer_valid;
/////////////////////////////////// Local Parameters /////////////////////////////////////////
localparam [2:0]
CMQ_IDLE_STATE = 3'b000,
CMQ_READ_CMD_STATE = 3'b001,
CMQ_RECEIVE_STATE = 3'b010,
CMQ_PROCESS_STATE = 3'b011,
CMQ_CHECK_STATE = 3'b100,
CMQ_POLL_STATE = 3'b101,
CMQ_POLL_RESP_STATE = 3'b110;
/////////// buffer response
always@(posedge clk) begin
if(~rst_n | queue_reset) begin
rx_rd_tag <= 0;
//rx_rd_data <= 0;
rx_rd_valid <= 0;
// RX WR
rx_wr_valid <= 0;
rx_wr_tag <= 0;
end
else begin
rx_rd_tag <= jq_rx_rd_tag;
rx_rd_data <= jq_rx_data;
rx_rd_valid <= jq_rx_rd_valid;
// RX WR
rx_wr_valid <= jq_rx_wr_valid;
rx_wr_tag <= jq_rx_wr_tag;
end
end
/////////////////////////////// CRB Status Logic /////////////////////////////////
always @(posedge clk) begin
if(~rst_n | queue_reset) begin
numPulledJobs <= 0;
numAvailableJobs <= 0;
queue_struct_base <= 0;
queue_buffer_base <= 0;
queue_buffer_size <= 0;
jq_fsm_state <= CMQ_IDLE_STATE;
poll_count <= 0;
prog_poll_cycles <= 0;
jq_tx_rd_addr <= 0;
jq_tx_rd_valid <= 0;
jq_tx_rd_tag <= 0;
last_req_d1 <= 0;
jq_producer_valid <= 0;
job_queue_valid <= 0;
job_queue_out <= 0;
rd_cnt <= 0;
end
else begin
case (jq_fsm_state)
CMQ_IDLE_STATE: begin
jq_fsm_state <= (start_queue)? CMQ_POLL_STATE : CMQ_IDLE_STATE;
queue_struct_base <= queue_base_addr;
queue_buffer_base <= queue_base_addr + queue_size[3:0];
queue_buffer_size <= queue_size[31:16];
rd_cnt <= 0;
prog_poll_cycles <= queue_poll_rate;
end
/////////////////////// Read Commands from the Queue States ////////////////////////////
CMQ_READ_CMD_STATE: begin
jq_fsm_state <= CMQ_RECEIVE_STATE;
rd_cnt <= (rd_cnt_inc == queue_buffer_size)? 0 : rd_cnt_inc;
jq_tx_rd_valid <= 1'b1;
jq_tx_rd_addr <= {1'b0, queue_buffer_base} + {1'b0, rd_cnt};
jq_tx_rd_tag <= 'h2;
numAvailableJobs <= numAvailableJobs - 1;
last_req_d1 <= (numAvailableJobs == 1);
end
CMQ_RECEIVE_STATE: begin
if( jq_tx_rd_ready ) jq_tx_rd_valid <= 1'b0;
jq_fsm_state <= (rx_rd_valid)? CMQ_PROCESS_STATE : CMQ_RECEIVE_STATE;
numPulledJobs <= (rx_rd_valid)? numPulledJobs + 1'b1 : numPulledJobs;
job_queue_out <= rx_rd_data;
job_queue_valid <= (rx_rd_valid)? 1'b1 : 1'b0;
end
CMQ_PROCESS_STATE: begin
jq_fsm_state <= (~job_queue_ready)? CMQ_PROCESS_STATE :
(last_req_d1)? CMQ_POLL_STATE : CMQ_READ_CMD_STATE;
job_queue_valid <= (~job_queue_ready)? 1'b1 : 1'b0;
end
/////////////////////////// Poll On CMD Queue Producer and Check Validity //////////////////////
CMQ_CHECK_STATE: begin
jq_fsm_state <= ((numAvailableJobs != 0) & jq_producer_valid)? CMQ_READ_CMD_STATE : CMQ_POLL_STATE;
end
CMQ_POLL_STATE: begin
if( poll_count == prog_poll_cycles) begin
jq_tx_rd_addr <= queue_struct_base + `CRB_STRUCT_PRODUCER_LINE_OFFSET;
jq_tx_rd_valid <= 1'b1;
jq_tx_rd_tag <= 'h1;
jq_fsm_state <= CMQ_POLL_RESP_STATE;
end
poll_count <= poll_count + 1'b1;
end
CMQ_POLL_RESP_STATE: begin
if( jq_tx_rd_ready ) jq_tx_rd_valid <= 1'b0;
poll_count <= 0;
jq_fsm_state <= (rx_rd_valid)? CMQ_CHECK_STATE : CMQ_POLL_RESP_STATE;
numAvailableJobs <= (rx_rd_valid)? ((rx_rd_data[63:32] >> 6) - numPulledJobs) : numAvailableJobs;
jq_producer_valid <= (rx_rd_valid)? (rx_rd_data[95:64] == `CMQ_PROD_VALID_MAGIC_NUMBER) : 0;
end
endcase
end
end
assign rd_cnt_inc = rd_cnt + 1'b1;
//////////////////////////////////////////////////////////////////////////////////////
////////////////////////////// CRB Consumer Status Update ////////////////////////////
////////////////////////////// TX WR Requests Generation ////////////////////////////
always @(posedge clk) begin
if(~rst_n | queue_reset) begin
//jq_tx_data <= 0;
jq_tx_wr_addr <= 0;
jq_tx_wr_valid <= 0;
jq_tx_wr_tag <= 0;
lastUpdatedJobs <= 0;
write_response_pending <= 0;
end
else begin
write_response_pending <= (write_response_pending)? ~rx_wr_valid : (jq_tx_wr_ready & jq_tx_wr_valid);
if(jq_tx_wr_ready | ~jq_tx_wr_valid) begin
if( update_status ) begin
lastUpdatedJobs <= numPulledJobs;
jq_tx_data <= {448'b0, numPulledJobs << 6, numPulledJobs};
jq_tx_wr_addr <= queue_struct_base + `CRB_STRUCT_CONSUMER_LINE_OFFSET;
jq_tx_wr_tag <= 0;
jq_tx_wr_valid <= 1'b1;
end
else begin
jq_tx_wr_valid <= 0;
end
end
end
end
assign update_status = ((numPulledJobs - lastUpdatedJobs) > 0) & ~write_response_pending;
endmodule |
module fpga_setup (
input wire clk,
input wire rst_n,
output reg ctx_status_valid,
// server_io <--> cmd server: RX_RD
input wire io_rx_csr_valid,
input wire [13:0] io_rx_csr_addr,
input wire [31:0] io_rx_csr_data,
// TX WR
input wire setup_tx_wr_ready,
output reg setup_tx_wr_valid,
output reg [`FPGA_SETUP_TAG-1:0] setup_tx_wr_tag,
output reg [31:0] setup_tx_wr_addr,
output reg [511:0] setup_tx_data,
// setup pagetable
input wire [1:0] pt_status,
output wire pt_update,
output wire [31:0] pt_base_addr,
output wire spl_reset_t
);
reg [31:0] pt_update_cycles = 0;
reg afu_dsm_updated = 0;
wire csr_afu_dsm_base_valid;
wire [31:0] csr_afu_dsm_base;
reg spl_dsm_updated = 0;
wire csr_spl_dsm_base_valid;
wire [31:0] csr_spl_dsm_base;
reg vir_ctx_updated = 0;
wire [31:0] csr_vir_ctx_base;
wire csr_vir_ctx_valid;
reg pt_status_updated = 0;
reg afu_config_updated = 0;
wire spl_dsm_update;
wire afu_dsm_update;
wire vir_ctx_update;
wire pt_status_update;
wire afu_config_update;
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ///////////////////////////
////////////////////////////////////////// CSR File ////////////////////////
///////////////////////////////////////////// ///////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
csr_file csr_file(
.clk (clk),
.reset_n (rst_n),
.spl_reset (spl_reset_t),
// server_io --> csr_file
.io_rx_csr_valid (io_rx_csr_valid),
.io_rx_csr_addr (io_rx_csr_addr),
.io_rx_csr_data (io_rx_csr_data),
// csr_file --> dsm_module, spl_id, afu_id
.csr_spl_dsm_base (csr_spl_dsm_base),
.csr_spl_dsm_base_valid (csr_spl_dsm_base_valid),
.csr_spl_dsm_base_done (spl_dsm_updated),
.csr_afu_dsm_base (csr_afu_dsm_base),
.csr_afu_dsm_base_valid (csr_afu_dsm_base_valid),
.csr_afu_dsm_base_done (afu_dsm_updated),
// csr_file --> ctx_tracker, FPGA virtual memory space
.csr_ctx_base_valid (csr_vir_ctx_valid),
.csr_ctx_base (csr_vir_ctx_base),
.csr_ctx_base_done (vir_ctx_updated)
);
///////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ///////////////////////////
////////////////////////////////////////// Setup FSM ////////////////////////
///////////////////////////////////////////// ///////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////
assign spl_dsm_update = csr_spl_dsm_base_valid & ~spl_dsm_updated;
assign afu_dsm_update = csr_afu_dsm_base_valid & ~afu_dsm_updated;
assign vir_ctx_update = csr_vir_ctx_valid & (|pt_status) & ~vir_ctx_updated;
assign pt_status_update = csr_vir_ctx_valid & pt_status[0] & ~pt_status_updated;
assign afu_config_update = afu_dsm_updated & ~afu_config_updated;
always @(posedge clk) begin
if (~rst_n | spl_reset_t) begin
setup_tx_wr_addr <= 0;
setup_tx_wr_valid <= 1'b0;
setup_tx_wr_tag <= 'h0;
setup_tx_data <= 0;
spl_dsm_updated <= 1'b0;
afu_dsm_updated <= 1'b0;
vir_ctx_updated <= 1'b0;
pt_status_updated <= 1'b0;
afu_config_updated <= 1'b0;
ctx_status_valid <= 0;
end
else if( setup_tx_wr_ready ) begin
casex ({spl_dsm_update, afu_dsm_update, afu_config_update, vir_ctx_update, pt_status_update})
5'b1????: begin //
setup_tx_wr_addr <= csr_spl_dsm_base;
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h1;
setup_tx_data <= {480'b0, `SPL_ID};
spl_dsm_updated <= 1'b1;
end
5'b01???: begin //
setup_tx_wr_addr <= csr_afu_dsm_base;
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h2;
setup_tx_data <= {448'b0, `AFU_ID};
afu_dsm_updated <= 1'b1;
end
5'b001??: begin
setup_tx_wr_addr <= (csr_afu_dsm_base + `ALLOC_OPERATORS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h3;
setup_tx_data <= {256'b0,
{16'b0,`FTHREAD_8_PLACED_AFU},
{16'b0,`FTHREAD_7_PLACED_AFU},
{16'b0,`FTHREAD_6_PLACED_AFU},
{16'b0,`FTHREAD_5_PLACED_AFU},
{16'b0,`FTHREAD_4_PLACED_AFU},
{16'b0,`FTHREAD_3_PLACED_AFU},
{16'b0,`FTHREAD_2_PLACED_AFU},
{16'b0,`FTHREAD_1_PLACED_AFU} };
afu_config_updated <= 1'b1;
end
5'b0001?: begin
setup_tx_wr_addr <= (csr_spl_dsm_base + `CTX_STATUS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h4;
setup_tx_data <= {384'b0, 127'b0, pt_status[1]};
vir_ctx_updated <= 1'b1;
end
5'b00001: begin
setup_tx_wr_addr <= (csr_afu_dsm_base + `PT_STATUS_DSM_OFFSET);
setup_tx_wr_valid <= 1'b1;
setup_tx_wr_tag <= 'h5;
setup_tx_data <= {480'b0, pt_update_cycles};
pt_status_updated <= 1'b1;
ctx_status_valid <= pt_status[0];
end
5'b00000: begin
setup_tx_wr_addr <= 0;
setup_tx_wr_valid <= 1'b0;
setup_tx_wr_tag <= 'h0;
setup_tx_data <= 0;
end
endcase
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////
assign pt_update = csr_vir_ctx_valid;
assign pt_base_addr = csr_vir_ctx_base;
//
always @(posedge clk) begin
if (~rst_n | spl_reset_t) begin
pt_update_cycles <= 0;
end
else begin
if(pt_update & ~(|pt_status) ) begin
pt_update_cycles <= pt_update_cycles + 1'b1;
end
end
end
endmodule |
module order_module_backpressure_wr
#(
parameter TAG_WIDTH = 6,
parameter OUT_TAG_WIDTH = 6,
parameter USER_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
parameter ADDR_WIDTH = 58)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
// input requests
input wire [ADDR_WIDTH-1:0] usr_tx_wr_addr,
input wire [USER_TAG_WIDTH-1:0] usr_tx_wr_tag,
input wire usr_tx_wr_valid,
input wire [DATA_WIDTH-1:0] usr_tx_data,
output wire usr_tx_wr_ready,
// User Module TX RD
output wire [ADDR_WIDTH-1:0] ord_tx_wr_addr,
output wire [OUT_TAG_WIDTH-1:0] ord_tx_wr_tag,
output wire ord_tx_wr_valid,
output wire [DATA_WIDTH-1:0] ord_tx_data,
input wire ord_tx_wr_ready,
// User Module RX RD
input wire [TAG_WIDTH-1:0] ord_rx_wr_tag,
input wire ord_rx_wr_valid,
//
output reg [USER_TAG_WIDTH-1:0] usr_rx_wr_tag,
output reg usr_rx_wr_valid,
input wire usr_rx_wr_ready
);
reg [2**TAG_WIDTH-1:0] rob_valid;
reg rob_re;
reg rob_re_d1;
reg [USER_TAG_WIDTH-1:0] rob_rtag;
wire pend_tag_fifo_full;
wire pend_tag_fifo_valid;
wire absorb_pend_tag;
wire [USER_TAG_WIDTH+TAG_WIDTH-1:0] curr_pend_tag;
reg [TAG_WIDTH-1:0] ord_tag;
reg [USER_TAG_WIDTH-1:0] usr_rx_wr_tag_reg;
reg usr_rx_wr_valid_reg;
assign ord_tx_wr_valid = usr_tx_wr_valid & ~pend_tag_fifo_full;
assign ord_tx_wr_tag = {{{OUT_TAG_WIDTH - TAG_WIDTH}{1'b0}}, ord_tag};
assign ord_tx_wr_addr = usr_tx_wr_addr;
assign ord_tx_data = usr_tx_data;
assign usr_tx_wr_ready = ord_tx_wr_ready & ~pend_tag_fifo_full;
// FIFO of tags for sent TX RD requests
quick_fifo #(.FIFO_WIDTH(USER_TAG_WIDTH + TAG_WIDTH),
.FIFO_DEPTH_BITS(TAG_WIDTH),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) pend_tag_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({usr_tx_wr_tag, ord_tag}),
.we (usr_tx_wr_valid & ord_tx_wr_ready),
.re ( absorb_pend_tag),
.dout (curr_pend_tag),
.empty (),
.valid (pend_tag_fifo_valid),
.full (pend_tag_fifo_full),
.count (),
.almostfull ()
);
assign absorb_pend_tag = rob_re;
always@(posedge clk) begin
if(~rst_n) begin
rob_valid <= 0;
usr_rx_wr_valid <= 1'b0;
usr_rx_wr_tag <= 0;
ord_tag <= 0;
rob_re <= 0;
rob_re_d1 <= 0;
rob_rtag <= 0;
end
else begin
if( usr_tx_wr_valid & ord_tx_wr_ready & ~pend_tag_fifo_full ) ord_tag <= ord_tag + 1'b1;
// write response in the responses memory if cannot bypass rob buffer
if(ord_rx_wr_valid) begin
rob_valid[ord_rx_wr_tag[TAG_WIDTH-1:0]] <= 1'b1;
end
rob_re <= 1'b0;
// if current pending tag has valid response then read it from the responses memory
if( ~usr_rx_wr_valid_reg | ~usr_rx_wr_valid | usr_rx_wr_ready) begin
if( rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] && pend_tag_fifo_valid) begin
rob_rtag <= curr_pend_tag[USER_TAG_WIDTH + TAG_WIDTH - 1: TAG_WIDTH];
rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] <= 1'b0;
rob_re <= 1'b1;
rob_re_d1 <= 1'b1;
end
else begin
rob_re_d1 <= 1'b0;
end
rob_re_d1 <= rob_re;
usr_rx_wr_valid_reg <= rob_re_d1;
usr_rx_wr_tag_reg <= rob_rtag;
usr_rx_wr_valid <= usr_rx_wr_valid_reg;
usr_rx_wr_tag <= usr_rx_wr_tag_reg;
end
end
end
endmodule |
module ReadConfigStruct #(parameter MAX_NUM_CONFIG_CL = 2)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire get_config_struct,
input wire [57:0] base_addr,
input wire [31:0] config_struct_length,
// User Module TX RD
output reg [57:0] cs_tx_rd_addr,
output reg [8:0] cs_tx_rd_tag,
output reg cs_tx_rd_valid,
input wire cs_tx_rd_free,
// User Module RX RD
input wire [8:0] cs_rx_rd_tag,
input wire [511:0] cs_rx_rd_data,
input wire cs_rx_rd_valid,
//
output wire [(MAX_NUM_CONFIG_CL<<9)-1:0] afu_config_struct,
output wire afu_config_struct_valid
);
wire rd_done;
wire all_reads_done;
reg [31:0] numReadsSent;
reg [31:0] numReadsDone;
reg [31:0] rd_cnt;
reg [511:0] config_lines[MAX_NUM_CONFIG_CL];
reg config_lines_valid[MAX_NUM_CONFIG_CL];
genvar i;
generate for( i = 0; i < MAX_NUM_CONFIG_CL; i = i + 1) begin: configLines
always@(posedge clk) begin
if(~rst_n) begin
//config_lines[ i ] <= 0;
config_lines_valid[ i ] <= 0;
end
else if(cs_rx_rd_valid) begin
config_lines[ i ] <= (cs_rx_rd_tag[1:0] == i)? cs_rx_rd_data : config_lines[ i ];
config_lines_valid[ i ] <= (cs_rx_rd_tag[1:0] == i)? 1'b1 : config_lines_valid[ i ];
end
end
assign afu_config_struct[512*(i+1) - 1 : 512*i] = config_lines[ i ];
end
endgenerate
/////////////////////////////// Generating Read Requests //////////////////////////////
//
assign all_reads_done = (numReadsSent == numReadsDone) & (numReadsSent != 0);
assign afu_config_struct_valid = rd_done & all_reads_done;
assign rd_done = (rd_cnt == config_struct_length);
always@(posedge clk) begin
if(~rst_n) begin
cs_tx_rd_valid <= 1'b0;
rd_cnt <= 0;
cs_tx_rd_addr <= 0;
cs_tx_rd_tag <= 0;
end
else if(cs_tx_rd_free | ~cs_tx_rd_valid) begin
if( ~rd_done & get_config_struct ) begin
rd_cnt <= rd_cnt + 1'b1;
cs_tx_rd_valid <= 1'b1;
cs_tx_rd_addr <= ({1'b0, base_addr} + {1'b0, rd_cnt});
cs_tx_rd_tag <= rd_cnt[8:0];
end
else begin
cs_tx_rd_valid <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
numReadsSent <= 0;
numReadsDone <= 0;
end
else begin
numReadsSent <= (cs_tx_rd_valid & cs_tx_rd_free)? numReadsSent + 1'b1 : numReadsSent;
numReadsDone <= (cs_rx_rd_valid)? numReadsDone + 1'b1 : numReadsDone;
end
end
endmodule |
module order_module_backpressure
#(
parameter TAG_WIDTH = 6,
parameter OUT_TAG_WIDTH = 6,
parameter USER_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
parameter ADDR_WIDTH = 58)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
// input requests
input wire [ADDR_WIDTH-1:0] usr_tx_rd_addr,
input wire [USER_TAG_WIDTH-1:0] usr_tx_rd_tag,
input wire usr_tx_rd_valid,
output wire usr_tx_rd_free,
// User Module TX RD
output wire [ADDR_WIDTH-1:0] ord_tx_rd_addr,
output wire [OUT_TAG_WIDTH-1:0] ord_tx_rd_tag,
output wire ord_tx_rd_valid,
input wire ord_tx_rd_free,
// User Module RX RD
input wire [TAG_WIDTH-1:0] ord_rx_rd_tag,
input wire [DATA_WIDTH-1:0] ord_rx_rd_data,
input wire ord_rx_rd_valid,
//
output reg [USER_TAG_WIDTH-1:0] usr_rx_rd_tag,
output reg [DATA_WIDTH-1:0] usr_rx_rd_data,
output reg usr_rx_rd_valid,
input wire usr_rx_rd_ready
);
reg [2**TAG_WIDTH-1:0] rob_valid;
reg rob_re;
reg rob_re_d1;
reg [USER_TAG_WIDTH-1:0] rob_rtag;
reg [USER_TAG_WIDTH+TAG_WIDTH-1:0] rob_raddr;
wire pend_tag_fifo_full;
wire pend_tag_fifo_valid;
wire absorb_pend_tag;
wire [USER_TAG_WIDTH+TAG_WIDTH-1:0] curr_pend_tag;
wire [DATA_WIDTH-1:0] rob_rdata;
reg [1:0] pending_valid;
reg [DATA_WIDTH-1:0] pending_data [1:0];
reg [USER_TAG_WIDTH-1:0] pending_tag [1:0];
reg [TAG_WIDTH-1:0] ord_tag;
assign ord_tx_rd_valid = usr_tx_rd_valid & ~pend_tag_fifo_full;
assign ord_tx_rd_tag = {{{OUT_TAG_WIDTH - TAG_WIDTH}{1'b0}}, ord_tag};
assign ord_tx_rd_addr = usr_tx_rd_addr;
assign usr_tx_rd_free = ord_tx_rd_free & ~pend_tag_fifo_full;
// RX_RD reorder buffer for rd data
spl_sdp_mem #(.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (TAG_WIDTH) // transfer size 1, tag width 6 -> 64 entries
) reorder_buf (
.clk (clk),
.we ( ord_rx_rd_valid ),
.waddr ( ord_rx_rd_tag[TAG_WIDTH-1:0] ),
.din ( ord_rx_rd_data ),
.re ( rob_re ),
.raddr ( rob_raddr[TAG_WIDTH-1:0] ),
.dout ( rob_rdata )
);
// FIFO of tags for sent TX RD requests
quick_fifo #(.FIFO_WIDTH(USER_TAG_WIDTH + TAG_WIDTH),
.FIFO_DEPTH_BITS(TAG_WIDTH),
.FIFO_ALMOSTFULL_THRESHOLD(32)
) pend_tag_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({usr_tx_rd_tag, ord_tag}),
.we (usr_tx_rd_valid & ord_tx_rd_free),
.re ( absorb_pend_tag),
.dout (curr_pend_tag),
.empty (),
.valid (pend_tag_fifo_valid),
.full (pend_tag_fifo_full),
.count (),
.almostfull ()
);
assign absorb_pend_tag = rob_re;
always@(posedge clk) begin
if(~rst_n) begin
rob_valid <= 0;
rob_re <= 0;
rob_re_d1 <= 0;
rob_rtag <= 0;
rob_raddr <= 0;
usr_rx_rd_valid <= 1'b0;
//usr_rx_rd_data <= 0;
usr_rx_rd_tag <= 0;
pending_valid <= 0;
ord_tag <= 0;
end
else begin
if( usr_tx_rd_valid & ord_tx_rd_free & ~pend_tag_fifo_full ) ord_tag <= ord_tag + 1'b1;
// write response in the responses memory if cannot bypass rob buffer
if(ord_rx_rd_valid) begin
rob_valid[ord_rx_rd_tag[TAG_WIDTH-1:0]] <= 1'b1;
end
// read rob buffer
rob_re <= 1'b0;
rob_re_d1 <= rob_re;
rob_rtag <= rob_raddr[USER_TAG_WIDTH+TAG_WIDTH-1 : TAG_WIDTH];
// if current pending tag has valid response then read it from the responses memory
if( rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] && pend_tag_fifo_valid && (~pending_valid[0] | (~pending_valid[1] & ~rob_re_d1) )) begin
rob_re <= 1'b1;
rob_raddr <= curr_pend_tag;
rob_valid[curr_pend_tag[TAG_WIDTH-1:0]] <= 1'b0;
end
// usr rx rd:
// Advance if either new data comes from the order memory or new data is requested by the AFU
if(~pending_valid[0]) begin
pending_valid[0] <= rob_re_d1;
pending_data[0] <= rob_rdata;
pending_tag[0] <= rob_rtag;
end
else if( ~usr_rx_rd_valid | usr_rx_rd_ready) begin
if(pending_valid[1]) begin
pending_valid[0] <= 1'b1;
pending_data[0] <= pending_data[1];
pending_tag[0] <= pending_tag[1];
end
else begin
pending_valid[0] <= rob_re_d1;
pending_data[0] <= rob_rdata;
pending_tag[0] <= rob_rtag;
end
end
if( usr_rx_rd_ready) begin
if(pending_valid[1]) begin
pending_valid[1] <= rob_re_d1;
pending_data[1] <= rob_rdata;
pending_tag[1] <= rob_rtag;
end
else begin
pending_valid[1] <= 0;
end
end
else if( pending_valid[0] & ~pending_valid[1] ) begin
pending_valid[1] <= rob_re_d1;
pending_data[1] <= rob_rdata;
pending_tag[1] <= rob_rtag;
end
if(usr_rx_rd_ready | ~usr_rx_rd_valid) begin
usr_rx_rd_valid <= pending_valid[0];
usr_rx_rd_data <= pending_data[0];
usr_rx_rd_tag <= pending_tag[0];
end
// Chekc if data got consumed, in case we are not advancing anyway
//else if (usr_rx_rd_valid && usr_rx_rd_ready) begin
// usr_rx_rd_valid <= 1'b0;
//end
end
end
endmodule |
module RetimeShiftRegister
#(
parameter WIDTH = 1,
parameter STAGES = 1)
(
input clock,
input reset,
input flow,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
integer i;
reg [WIDTH-1:0] sr[0:STAGES]; // Create 'STAGES' number of register, each 'WIDTH' bits wide
/* synopsys dc_tcl_script_begin
set_ungroup [current_design] true
set_flatten true -effort high -phase true -design [current_design]
set_dont_retime [current_design] false
set_optimize_registers true -design [current_design]
*/
always @(posedge clock) begin
if (reset) begin
for(i=0; i<STAGES; i=i+1) begin
sr[i] <= {WIDTH{1'b0}};
end
end else begin
if (flow) begin
sr[0] <= in;
for(i=1; i<STAGES; i=i+1) begin
sr[i] <= sr[i-1];
end
end
end
end
always @(*) begin
out <= sr[STAGES-1];
end
endmodule |
module SRAMVerilogAWS
#(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32)
(
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input [DWIDTH-1:0] wdata,
input flow,
output reg [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] mem [0:WORDS-1];
always @(posedge clk) begin
if (wen) mem[waddr] <= wdata;
if (flow) rdata <= mem[raddr];
end
endmodule |
module SRAMVerilogSim
#(
parameter WORDS = 1024,
parameter AWIDTH = 10,
parameter DWIDTH = 32)
(
input clk,
input [AWIDTH-1:0] raddr,
input [AWIDTH-1:0] waddr,
input raddrEn,
input waddrEn,
input wen,
input flow,
input [DWIDTH-1:0] wdata,
output reg [DWIDTH-1:0] rdata
);
reg [DWIDTH-1:0] mem [0:WORDS-1];
always @(negedge clk) begin
if (wen) begin
mem[waddr] <= wdata;
end
end
always @(posedge clk) begin
if (flow) rdata <= mem[raddr];
end
endmodule |
module DE1_SoC_Computer (
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
// SDRAM
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
// I2C Bus for Configuration of the Audio and Video-In Chips
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
// 40-Pin Headers
GPIO_0,
GPIO_1,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// IR
IRDA_RXD,
IRDA_TXD,
// Pushbuttons
KEY,
// LEDs
LEDR,
// PS2 Ports
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
// Slider Switches
SW,
// Video-In
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
// VGA
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
HPS_DDR3_ADDR,
HPS_DDR3_BA,
HPS_DDR3_CAS_N,
HPS_DDR3_CKE,
HPS_DDR3_CK_N,
HPS_DDR3_CK_P,
HPS_DDR3_CS_N,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_N,
HPS_DDR3_DQS_P,
HPS_DDR3_ODT,
HPS_DDR3_RAS_N,
HPS_DDR3_RESET_N,
HPS_DDR3_RZQ,
HPS_DDR3_WE_N,
// Ethernet
HPS_ENET_GTX_CLK,
HPS_ENET_INT_N,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
// Flash
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
// Accelerometer
HPS_GSENSOR_INT,
// General Purpose I/O
HPS_GPIO,
// I2C
HPS_I2C_CONTROL,
HPS_I2C1_SCLK,
HPS_I2C1_SDAT,
HPS_I2C2_SCLK,
HPS_I2C2_SDAT,
// Pushbutton
HPS_KEY,
// LED
HPS_LED,
// SD Card
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
// SPI
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
// UART
HPS_UART_RX,
HPS_UART_TX,
// USB
HPS_CONV_USB_N,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_STP
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input CLOCK4_50;
// ADC
inout ADC_CS_N;
output ADC_DIN;
input ADC_DOUT;
output ADC_SCLK;
// Audio
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
// SDRAM
output [12: 0] DRAM_ADDR;
output [ 1: 0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15: 0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_RAS_N;
output DRAM_UDQM;
output DRAM_WE_N;
// I2C Bus for Configuration of the Audio and Video-In Chips
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
// 40-pin headers
inout [35: 0] GPIO_0;
inout [35: 0] GPIO_1;
// Seven Segment Displays
output [ 6: 0] HEX0;
output [ 6: 0] HEX1;
output [ 6: 0] HEX2;
output [ 6: 0] HEX3;
output [ 6: 0] HEX4;
output [ 6: 0] HEX5;
// IR
input IRDA_RXD;
output IRDA_TXD;
// Pushbuttons
input [ 3: 0] KEY;
// LEDs
output [ 9: 0] LEDR;
// PS2 Ports
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
// Slider Switches
input [ 9: 0] SW;
// Video-In
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
// VGA
output [ 7: 0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [ 7: 0] VGA_G;
output VGA_HS;
output [ 7: 0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
output [14: 0] HPS_DDR3_ADDR;
output [ 2: 0] HPS_DDR3_BA;
output HPS_DDR3_CAS_N;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_N;
output HPS_DDR3_CK_P;
output HPS_DDR3_CS_N;
output [ 3: 0] HPS_DDR3_DM;
inout [31: 0] HPS_DDR3_DQ;
inout [ 3: 0] HPS_DDR3_DQS_N;
inout [ 3: 0] HPS_DDR3_DQS_P;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_N;
output HPS_DDR3_RESET_N;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_N;
// Ethernet
output HPS_ENET_GTX_CLK;
inout HPS_ENET_INT_N;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
input HPS_ENET_RX_CLK;
input [ 3: 0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [ 3: 0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
// Flash
inout [ 3: 0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
// Accelerometer
inout HPS_GSENSOR_INT;
// General Purpose I/O
inout [ 1: 0] HPS_GPIO;
// I2C
inout HPS_I2C_CONTROL;
inout HPS_I2C1_SCLK;
inout HPS_I2C1_SDAT;
inout HPS_I2C2_SCLK;
inout HPS_I2C2_SDAT;
// Pushbutton
inout HPS_KEY;
// LED
inout HPS_LED;
// SD Card
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [ 3: 0] HPS_SD_DATA;
// SPI
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
inout HPS_SPIM_SS;
// UART
input HPS_UART_RX;
output HPS_UART_TX;
// USB
inout HPS_CONV_USB_N;
input HPS_USB_CLKOUT;
inout [ 7: 0] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_STP;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [31: 0] hex3_hex0;
wire [15: 0] hex5_hex4;
assign HEX0 = ~hex3_hex0[ 6: 0];
assign HEX1 = ~hex3_hex0[14: 8];
assign HEX2 = ~hex3_hex0[22:16];
assign HEX3 = ~hex3_hex0[30:24];
assign HEX4 = ~hex5_hex4[ 6: 0];
assign HEX5 = ~hex5_hex4[14: 8];
//=======================================================
// Structural coding
//=======================================================
Computer_System The_System (
////////////////////////////////////
// FPGA Side
////////////////////////////////////
// Global signals
.system_pll_ref_clk_clk (CLOCK_50),
.system_pll_ref_reset_reset (1'b0),
// AV Config
// .av_config_SCLK (FPGA_I2C_SCLK),
// .av_config_SDAT (FPGA_I2C_SDAT),
// Audio Subsystem
// .audio_pll_ref_clk_clk (CLOCK3_50),
// .audio_pll_ref_reset_reset (1'b0),
// .audio_clk_clk (AUD_XCK),
// .audio_ADCDAT (AUD_ADCDAT),
// .audio_ADCLRCK (AUD_ADCLRCK),
// .audio_BCLK (AUD_BCLK),
// .audio_DACDAT (AUD_DACDAT),
// .audio_DACLRCK (AUD_DACLRCK),
// Slider Switches
.slider_switches_export (SW),
// Pushbuttons
.pushbuttons_export (~KEY[3:0]),
// Expansion JP1
.expansion_jp1_export ({GPIO_0[35:19], GPIO_0[17], GPIO_0[15:3], GPIO_0[1]}),
// Expansion JP2
.expansion_jp2_export ({GPIO_1[35:19], GPIO_1[17], GPIO_1[15:3], GPIO_1[1]}),
// LEDs
.leds_export (LEDR),
// Seven Segs
// .hex3_hex0_export (hex3_hex0),
// .hex5_hex4_export (hex5_hex4),
// PS2 Ports
// .ps2_port_CLK (PS2_CLK),
// .ps2_port_DAT (PS2_DAT),
// .ps2_port_dual_CLK (PS2_CLK2),
// .ps2_port_dual_DAT (PS2_DAT2),
// IrDA
// .irda_RXD (IRDA_RXD),
// .irda_TXD (IRDA_TXD),
// VGA Subsystem
.vga_pll_ref_clk_clk (CLOCK2_50),
.vga_pll_ref_reset_reset (1'b0),
.vga_CLK (VGA_CLK),
.vga_BLANK (VGA_BLANK_N),
.vga_SYNC (VGA_SYNC_N),
.vga_HS (VGA_HS),
.vga_VS (VGA_VS),
.vga_R (VGA_R),
.vga_G (VGA_G),
.vga_B (VGA_B),
// Video In Subsystem
.video_in_TD_CLK27 (TD_CLK27),
.video_in_TD_DATA (TD_DATA),
.video_in_TD_HS (TD_HS),
.video_in_TD_VS (TD_VS),
.video_in_clk27_reset (),
.video_in_TD_RESET (TD_RESET_N),
.video_in_overflow_flag (),
// SDRAM
.sdram_clk_clk (DRAM_CLK),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm ({DRAM_UDQM,DRAM_LDQM}),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
////////////////////////////////////
// HPS Side
////////////////////////////////////
// DDR3 SDRAM
.memory_mem_a (HPS_DDR3_ADDR),
.memory_mem_ba (HPS_DDR3_BA),
.memory_mem_ck (HPS_DDR3_CK_P),
.memory_mem_ck_n (HPS_DDR3_CK_N),
.memory_mem_cke (HPS_DDR3_CKE),
.memory_mem_cs_n (HPS_DDR3_CS_N),
.memory_mem_ras_n (HPS_DDR3_RAS_N),
.memory_mem_cas_n (HPS_DDR3_CAS_N),
.memory_mem_we_n (HPS_DDR3_WE_N),
.memory_mem_reset_n (HPS_DDR3_RESET_N),
.memory_mem_dq (HPS_DDR3_DQ),
.memory_mem_dqs (HPS_DDR3_DQS_P),
.memory_mem_dqs_n (HPS_DDR3_DQS_N),
.memory_mem_odt (HPS_DDR3_ODT),
.memory_mem_dm (HPS_DDR3_DM),
.memory_oct_rzqin (HPS_DDR3_RZQ),
// Ethernet
.hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),
.hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),
.hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),
.hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),
.hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),
.hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),
.hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
.hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
.hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),
.hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),
.hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),
// Flash
.hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),
.hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),
.hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),
.hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),
.hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),
.hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),
// Accelerometer
.hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
// .adc_sclk (ADC_SCLK),
// .adc_cs_n (ADC_CS_N),
// .adc_dout (ADC_DOUT),
// .adc_din (ADC_DIN),
// General Purpose I/O
.hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
.hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),
// I2C
.hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
.hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT),
.hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK),
// Pushbutton
.hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),
// LED
.hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),
// SD Card
.hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),
.hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
.hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
.hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),
.hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
.hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),
// SPI
.hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK),
.hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI),
.hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO),
.hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS),
// UART
.hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),
.hps_io_hps_io_uart0_inst_TX (HPS_UART_TX),
// USB
.hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),
.hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),
.hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),
.hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),
.hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),
.hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),
.hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),
.hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),
.hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),
.hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),
.hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),
.hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT)
);
endmodule |
module ghrd_a10_top (
// FPGA peripherals ports
input wire [3:0] fpga_dipsw_pio,
output wire [3:0] fpga_led_pio,
input wire [3:0] fpga_button_pio,
// HPS memory controller ports
// DDR4 single rank -2133 device
output wire hps_memory_mem_act_n,
output wire hps_memory_mem_bg,
output wire hps_memory_mem_par,
input wire hps_memory_mem_alert_n,
inout wire [4-1:0] hps_memory_mem_dbi_n,
output wire [16:0] hps_memory_mem_a,
output wire [1:0] hps_memory_mem_ba,
output wire hps_memory_mem_ck,
output wire hps_memory_mem_ck_n,
output wire hps_memory_mem_cke,
output wire hps_memory_mem_cs_n,
output wire hps_memory_mem_reset_n,
inout wire [32-1:0] hps_memory_mem_dq,
inout wire [4-1:0] hps_memory_mem_dqs,
inout wire [4-1:0] hps_memory_mem_dqs_n,
output wire hps_memory_mem_odt,
input wire hps_memory_oct_rzqin,
input wire emif_ref_clk,
// HPS peripherals
output wire hps_emac0_TX_CLK,
output wire hps_emac0_TXD0,
output wire hps_emac0_TXD1,
output wire hps_emac0_TXD2,
output wire hps_emac0_TXD3,
input wire hps_emac0_RXD0,
inout wire hps_emac0_MDIO,
output wire hps_emac0_MDC,
input wire hps_emac0_RX_CTL,
output wire hps_emac0_TX_CTL,
input wire hps_emac0_RX_CLK,
input wire hps_emac0_RXD1,
input wire hps_emac0_RXD2,
input wire hps_emac0_RXD3,
inout wire hps_usb0_D0,
inout wire hps_usb0_D1,
inout wire hps_usb0_D2,
inout wire hps_usb0_D3,
inout wire hps_usb0_D4,
inout wire hps_usb0_D5,
inout wire hps_usb0_D6,
inout wire hps_usb0_D7,
input wire hps_usb0_CLK,
output wire hps_usb0_STP,
input wire hps_usb0_DIR,
input wire hps_usb0_NXT,
output wire hps_spim1_CLK,
output wire hps_spim1_MOSI,
input wire hps_spim1_MISO,
output wire hps_spim1_SS0_N,
output wire hps_spim1_SS1_N,
input wire hps_uart1_RX,
output wire hps_uart1_TX,
inout wire hps_i2c1_SDA,
inout wire hps_i2c1_SCL,
inout wire hps_sdio_CMD,
output wire hps_sdio_CLK,
inout wire hps_sdio_D0,
inout wire hps_sdio_D1,
inout wire hps_sdio_D2,
inout wire hps_sdio_D3,
inout wire hps_sdio_D4,
inout wire hps_sdio_D5,
inout wire hps_sdio_D6,
inout wire hps_sdio_D7,
output wire hps_trace_CLK,
output wire hps_trace_D0,
output wire hps_trace_D1,
output wire hps_trace_D2,
output wire hps_trace_D3,
inout wire hps_gpio_GPIO14,
inout wire hps_gpio_GPIO05,
inout wire hps_gpio_GPIO16,
inout wire hps_gpio_GPIO17,
// Other HPS-FPGA peripherals
// FPGA clock and reset
input wire fpga_clk_100,
input wire fpga_reset_n
);
// internal wires and registers declaration
wire [3:0] fpga_debounced_buttons;
wire [3:0] fpga_led_internal;
wire [27:0] stm_hw_events;
wire hps_fpga_reset;
wire [2:0] hps_reset_req;
wire hps_cold_reset;
wire hps_warm_reset;
wire hps_debug_reset;
// connection of internal logics
assign fpga_led_pio = fpga_led_internal;
assign stm_hw_events = {{16{1'b0}}, fpga_dipsw_pio, fpga_led_internal, fpga_debounced_buttons};
wire pr_handshake_start_req;
wire pr_handshake_stop_req;
// SoC sub-system module
ghrd_10as066n2 soc_inst (
.pr_handshake_start_req (pr_handshake_start_req),
.pr_handshake_start_ack (pr_handshake_start_req),
.pr_handshake_stop_req (pr_handshake_stop_req),
.pr_handshake_stop_ack (pr_handshake_stop_req),
.f2h_stm_hw_events_stm_hwevents (stm_hw_events),
.pio_dipsw_external_connection_export (fpga_dipsw_pio),
.pio_led_external_connection_in_port (fpga_led_internal),
.pio_led_external_connection_out_port (fpga_led_internal),
.pio_button_external_connection_export (fpga_debounced_buttons),
.hps_io_hps_io_phery_emac0_TX_CLK (hps_emac0_TX_CLK),
.hps_io_hps_io_phery_emac0_TXD0 (hps_emac0_TXD0),
.hps_io_hps_io_phery_emac0_TXD1 (hps_emac0_TXD1),
.hps_io_hps_io_phery_emac0_TXD2 (hps_emac0_TXD2),
.hps_io_hps_io_phery_emac0_TXD3 (hps_emac0_TXD3),
.hps_io_hps_io_phery_emac0_MDIO (hps_emac0_MDIO),
.hps_io_hps_io_phery_emac0_MDC (hps_emac0_MDC),
.hps_io_hps_io_phery_emac0_RX_CTL (hps_emac0_RX_CTL),
.hps_io_hps_io_phery_emac0_TX_CTL (hps_emac0_TX_CTL),
.hps_io_hps_io_phery_emac0_RX_CLK (hps_emac0_RX_CLK),
.hps_io_hps_io_phery_emac0_RXD0 (hps_emac0_RXD0),
.hps_io_hps_io_phery_emac0_RXD1 (hps_emac0_RXD1),
.hps_io_hps_io_phery_emac0_RXD2 (hps_emac0_RXD2),
.hps_io_hps_io_phery_emac0_RXD3 (hps_emac0_RXD3),
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb0_D0),
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb0_D1),
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb0_D2),
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb0_D3),
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb0_D4),
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb0_D5),
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb0_D6),
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb0_D7),
.hps_io_hps_io_phery_usb0_CLK (hps_usb0_CLK),
.hps_io_hps_io_phery_usb0_STP (hps_usb0_STP),
.hps_io_hps_io_phery_usb0_DIR (hps_usb0_DIR),
.hps_io_hps_io_phery_usb0_NXT (hps_usb0_NXT),
.hps_io_hps_io_phery_spim1_CLK (hps_spim1_CLK),
.hps_io_hps_io_phery_spim1_MOSI (hps_spim1_MOSI),
.hps_io_hps_io_phery_spim1_MISO (hps_spim1_MISO),
.hps_io_hps_io_phery_spim1_SS0_N (hps_spim1_SS0_N),
.hps_io_hps_io_phery_spim1_SS1_N (hps_spim1_SS1_N),
.hps_io_hps_io_phery_uart1_RX (hps_uart1_RX),
.hps_io_hps_io_phery_uart1_TX (hps_uart1_TX),
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_CMD),
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_D0),
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_D1),
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_D2),
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_D3),
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_D4),
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_D5),
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_D6),
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_D7),
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_CLK),
.hps_io_hps_io_phery_trace_CLK (hps_trace_CLK),
.hps_io_hps_io_phery_trace_D0 (hps_trace_D0),
.hps_io_hps_io_phery_trace_D1 (hps_trace_D1),
.hps_io_hps_io_phery_trace_D2 (hps_trace_D2),
.hps_io_hps_io_phery_trace_D3 (hps_trace_D3),
.emif_a10_hps_0_mem_conduit_end_mem_ck (hps_memory_mem_ck),
.emif_a10_hps_0_mem_conduit_end_mem_ck_n (hps_memory_mem_ck_n),
.emif_a10_hps_0_mem_conduit_end_mem_a (hps_memory_mem_a),
.emif_a10_hps_0_mem_conduit_end_mem_act_n (hps_memory_mem_act_n),
.emif_a10_hps_0_mem_conduit_end_mem_ba (hps_memory_mem_ba),
.emif_a10_hps_0_mem_conduit_end_mem_bg (hps_memory_mem_bg),
.emif_a10_hps_0_mem_conduit_end_mem_cke (hps_memory_mem_cke),
.emif_a10_hps_0_mem_conduit_end_mem_cs_n (hps_memory_mem_cs_n),
.emif_a10_hps_0_mem_conduit_end_mem_odt (hps_memory_mem_odt),
.emif_a10_hps_0_mem_conduit_end_mem_reset_n (hps_memory_mem_reset_n),
.emif_a10_hps_0_mem_conduit_end_mem_par (hps_memory_mem_par),
.emif_a10_hps_0_mem_conduit_end_mem_alert_n (hps_memory_mem_alert_n),
.emif_a10_hps_0_mem_conduit_end_mem_dqs (hps_memory_mem_dqs),
.emif_a10_hps_0_mem_conduit_end_mem_dqs_n (hps_memory_mem_dqs_n),
.emif_a10_hps_0_mem_conduit_end_mem_dq (hps_memory_mem_dq),
.emif_a10_hps_0_mem_conduit_end_mem_dbi_n (hps_memory_mem_dbi_n),
.emif_a10_hps_0_oct_conduit_end_oct_rzqin (hps_memory_oct_rzqin),
.emif_a10_hps_0_pll_ref_clk_clock_sink_clk (emif_ref_clk),
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio_GPIO05),
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio_GPIO14),
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio_GPIO16),
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio_GPIO17),
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c1_SDA),
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c1_SCL),
.hps_fpga_reset_reset (hps_fpga_reset),
.issp_hps_resets_source (hps_reset_req),
.f2h_cold_reset_req_reset_n (~hps_cold_reset),
.f2h_warm_reset_req_reset_n (~hps_warm_reset),
.f2h_debug_reset_req_reset_n (~hps_debug_reset),
.reset_reset_n (fpga_reset_n),
.clk_100_clk (fpga_clk_100)
);
// Debounce logic to clean out glitches within 1ms
debounce debounce_inst (
.clk (fpga_clk_100),
.reset_n (~hps_fpga_reset),
.data_in (fpga_button_pio),
.data_out (fpga_debounced_buttons)
);
defparam debounce_inst.WIDTH = 4;
defparam debounce_inst.POLARITY = "LOW";
defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms
defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT))
altera_edge_detector pulse_cold_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[0]),
.pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_warm_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[1]),
.pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_debug_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[2]),
.pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
endmodule |
module Top (
input wire clock, // clock.clk
input wire reset, // reset.reset
input wire [6:0] io_S_AVALON_address, // io_S_AVALON.address
output wire [31:0] io_S_AVALON_readdata, // .readdata
input wire io_S_AVALON_chipselect, // .chipselect
input wire io_S_AVALON_write, // .write
input wire io_S_AVALON_read, // .read
input wire [31:0] io_S_AVALON_writedata, // .writedata
output wire [3:0] io_M_AXI_0_AWID, // io_M_AXI_0_1.awid
output wire [31:0] io_M_AXI_0_AWUSER, // .awuser
output wire [31:0] io_M_AXI_0_AWADDR, // .awaddr
output wire [7:0] io_M_AXI_0_AWLEN, // .awlen
output wire [2:0] io_M_AXI_0_AWSIZE, // .awsize
output wire [1:0] io_M_AXI_0_AWBURST, // .awburst
output wire io_M_AXI_0_AWLOCK, // .awlock
output wire [3:0] io_M_AXI_0_AWCACHE, // .awcache
output wire [2:0] io_M_AXI_0_AWPROT, // .awprot
output wire [3:0] io_M_AXI_0_AWQOS, // .awqos
output wire io_M_AXI_0_AWVALID, // .awvalid
input wire io_M_AXI_0_AWREADY, // .awready
output wire [3:0] io_M_AXI_0_ARID, // .arid
output wire [31:0] io_M_AXI_0_ARUSER, // .aruser
output wire [31:0] io_M_AXI_0_ARADDR, // .araddr
output wire [7:0] io_M_AXI_0_ARLEN, // .arlen
output wire [2:0] io_M_AXI_0_ARSIZE, // .arsize
output wire [1:0] io_M_AXI_0_ARBURST, // .arburst
output wire io_M_AXI_0_ARLOCK, // .arlock
output wire [3:0] io_M_AXI_0_ARCACHE, // .arcache
output wire [2:0] io_M_AXI_0_ARPROT, // .arprot
output wire [3:0] io_M_AXI_0_ARQOS, // .arqos
output wire io_M_AXI_0_ARVALID, // .arvalid
input wire io_M_AXI_0_ARREADY, // .arready
output wire [511:0] io_M_AXI_0_WDATA, // .wdata
output wire [63:0] io_M_AXI_0_WSTRB, // .wstrb
output wire io_M_AXI_0_WLAST, // .wlast
output wire io_M_AXI_0_WVALID, // .wvalid
input wire io_M_AXI_0_WREADY, // .wready
input wire [3:0] io_M_AXI_0_RID, // .rid
input wire [31:0] io_M_AXI_0_RUSER, // .ruser
input wire [511:0] io_M_AXI_0_RDATA, // .rdata
input wire [1:0] io_M_AXI_0_RRESP, // .rresp
input wire io_M_AXI_0_RLAST, // .rlast
input wire io_M_AXI_0_RVALID, // .rvalid
output wire io_M_AXI_0_RREADY, // .rready
input wire [3:0] io_M_AXI_0_BID, // .bid
input wire [31:0] io_M_AXI_0_BUSER, // .buser
input wire [1:0] io_M_AXI_0_BRESP, // .bresp
input wire io_M_AXI_0_BVALID, // .bvalid
output wire io_M_AXI_0_BREADY // .bready
);
// TODO: Auto-generated HDL template
assign io_S_AVALON_readdata = 32'b00000000000000000000000000000000;
assign io_M_AXI_0_AWBURST = 2'b00;
assign io_M_AXI_0_AWUSER = 32'b00000000000000000000000000000000;
assign io_M_AXI_0_ARLEN = 8'b00000000;
assign io_M_AXI_0_ARQOS = 4'b0000;
assign io_M_AXI_0_WSTRB = 64'b0000000000000000000000000000000000000000000000000000000000000000;
assign io_M_AXI_0_RREADY = 1'b0;
assign io_M_AXI_0_AWLEN = 8'b00000000;
assign io_M_AXI_0_AWQOS = 4'b0000;
assign io_M_AXI_0_ARCACHE = 4'b0000;
assign io_M_AXI_0_ARADDR = 32'b00000000000000000000000000000000;
assign io_M_AXI_0_WVALID = 1'b0;
assign io_M_AXI_0_ARPROT = 3'b000;
assign io_M_AXI_0_AWPROT = 3'b000;
assign io_M_AXI_0_ARVALID = 1'b0;
assign io_M_AXI_0_WDATA = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
assign io_M_AXI_0_AWCACHE = 4'b0000;
assign io_M_AXI_0_ARID = 4'b0000;
assign io_M_AXI_0_ARLOCK = 1'b0;
assign io_M_AXI_0_AWLOCK = 1'b0;
assign io_M_AXI_0_AWADDR = 32'b00000000000000000000000000000000;
assign io_M_AXI_0_ARBURST = 2'b00;
assign io_M_AXI_0_ARSIZE = 3'b000;
assign io_M_AXI_0_BREADY = 1'b0;
assign io_M_AXI_0_WLAST = 1'b0;
assign io_M_AXI_0_AWID = 4'b0000;
assign io_M_AXI_0_AWSIZE = 3'b000;
assign io_M_AXI_0_AWVALID = 1'b0;
assign io_M_AXI_0_ARUSER = 32'b00000000000000000000000000000000;
endmodule |
module pdo
(
i, oein, o, obar, oebout, oeout
);
input i;
input oein;
output o;
output obar;
output wire oebout;
output wire oeout;
twentynm_pseudo_diff_out pdo_wys
(
.i(i),
.oein(oein),
.o(o),
.oebout(oebout),
.oeout(oeout),
.dtc(),
.dtcbar(),
.dtcin(),
.obar(obar)
);
endmodule |
module buslvds(
doutp,
oe,
din,
p,
n
);
input wire doutp;
input wire oe;
output wire din;
inout wire p;
inout wire n;
wire oebout;
wire oeout;
wire [0:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
pdo b2v_inst(
.i(doutp),
.oein(oe),
.o(SYNTHESIZED_WIRE_2),
.obar(SYNTHESIZED_WIRE_3),
.oebout(oebout),
.oeout(oeout));
assign din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_1 = ~oe;
twentynm_io_obuf b2v_inst3(
.i(SYNTHESIZED_WIRE_2),
.oe(oeout),
.o(p),
.obar());
twentynm_io_obuf b2v_inst4(
.i(SYNTHESIZED_WIRE_3),
.oe(oebout),
.o(n),
.obar());
diffin b2v_inst5(
.datain(p),
.datain_b(n),
.dataout(SYNTHESIZED_WIRE_0));
endmodule |
module vesa_tpg(
clock,
reset,
dout_ready,
dout_valid,
dout_data,
dout_sop,
dout_eop,
bpp // 3'b000 = 18bpp, 3'b001 = 24bpp
);
parameter MAX_BPC = 8;
input clock;
input reset;
input dout_ready;
output dout_valid;
output [MAX_BPC*3-1:0] dout_data;
output dout_sop;
output dout_eop;
wire [1:0] dout_empty;
input [2:0] bpp;
assign dout_empty = 0;
parameter WIDTH=1920;
parameter HEIGHT=1080;
localparam CTRL_PKT_NUM=3;
localparam CTRL_PKT_HEADER=24'd15;
localparam DATA_PKT_HEADER=24'd0;
///////////////////////
reg [11:0] dot_cnt;
reg [11:0] line_cnt;
///////////////////////
// Catch ready signal
reg dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset)
dout_ready_reg <= 0;
else
dout_ready_reg <= dout_ready;
end
///////////////////////
// valid is always 1 but masked by dout_ready_reg
assign dout_valid = dout_ready_reg;
///////////////////////
// State Machine
//reg out;
reg [1:0] pkt_state;
localparam STATE_CTRL_PKT_SOP = 0;
localparam STATE_CTRL_PKT_DAT = 1;
localparam STATE_DATA_PKT_SOP = 2;
localparam STATE_DATA_PKT_DAT = 3;
wire ctrl_pkt_sop = (pkt_state == STATE_CTRL_PKT_SOP ) ? 1 : 0 ;
wire ctrl_pkt_eop = ((pkt_state == STATE_CTRL_PKT_DAT) & (dot_cnt==(CTRL_PKT_NUM-1)) ) ? 1 : 0 ;
wire data_pkt_sop = (pkt_state == STATE_DATA_PKT_SOP ) ? 1 : 0 ;
wire data_pkt_eop = ((pkt_state == STATE_DATA_PKT_DAT) & (dot_cnt==(WIDTH-1)) & (line_cnt==(HEIGHT-1)) ) ? 1 : 0 ;
always @ (posedge clock or posedge reset) begin
if (reset) pkt_state <= STATE_CTRL_PKT_SOP;
else
case (pkt_state) // state transitions
STATE_CTRL_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_CTRL_PKT_DAT;
STATE_CTRL_PKT_DAT: if (dout_ready_reg & ctrl_pkt_eop) pkt_state <= STATE_DATA_PKT_SOP;
STATE_DATA_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_DATA_PKT_DAT;
STATE_DATA_PKT_DAT: if (dout_ready_reg & data_pkt_eop) pkt_state <= STATE_CTRL_PKT_SOP;
default : pkt_state <= STATE_CTRL_PKT_DAT;
endcase
end
///////////////////////
/////////////////////////
// sop and eop signals
assign dout_sop = (ctrl_pkt_sop | data_pkt_sop) & dout_ready_reg;
assign dout_eop = (ctrl_pkt_eop | data_pkt_eop) & dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset) begin
dot_cnt <= 0;
end
else begin
if (dout_ready_reg)
if ((pkt_state == STATE_DATA_PKT_DAT) ) begin
if ( dot_cnt < (WIDTH-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
else if ((pkt_state == STATE_CTRL_PKT_DAT) )begin // control packet
if ( dot_cnt < (CTRL_PKT_NUM-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
line_cnt <= 0;
end
else begin
if (dout_ready_reg ) begin
if (pkt_state == STATE_DATA_PKT_DAT) begin
if ( dot_cnt == (WIDTH-1) ) begin
if ( line_cnt < (HEIGHT-1) )
line_cnt <= line_cnt+1;
else
line_cnt <= 0;
end
end
else
line_cnt <= 0;
end
end
end
reg [MAX_BPC*3-1:0] ctrl_data;
wire [MAX_BPC-1:0] r_data;
wire [MAX_BPC-1:0] g_data;
wire [MAX_BPC-1:0] b_data;
wire [MAX_BPC*3-1:0] image_data={r_data, g_data, b_data};
///////////////////////
// Making Image Data
// Generate VESA ramp 6bpc
wire r_line_active_18bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_18bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_18bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_18bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_18bpp = {{6{r_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] g_data_18bpp = {{6{g_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] b_data_18bpp = {{6{b_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
// Generate VESA ramp 8bpc
wire r_line_active_24bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_24bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_24bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_24bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_24bpp = {{8{r_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] g_data_24bpp = {{8{g_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] b_data_24bpp = {{8{b_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
// Combiner
assign r_data = 16'd0 | {16{bpp == 3'b001}} & r_data_24bpp | {16{bpp == 3'b000}} & r_data_18bpp;
assign g_data = 16'd0 | {16{bpp == 3'b001}} & g_data_24bpp | {16{bpp == 3'b000}} & g_data_18bpp;
assign b_data = 16'd0 | {16{bpp == 3'b001}} & b_data_24bpp | {16{bpp == 3'b000}} & b_data_18bpp;
///////////////////////
// Making Final Output Data
reg [MAX_BPC*3-1:0] dout_data;
always @(pkt_state or ctrl_data or image_data ) begin
case (pkt_state)
STATE_CTRL_PKT_SOP: dout_data = CTRL_PKT_HEADER;
STATE_CTRL_PKT_DAT: dout_data = ctrl_data;
STATE_DATA_PKT_SOP: dout_data = DATA_PKT_HEADER;
default: dout_data = image_data;
endcase
end
wire [15:0] w_width = WIDTH;
wire [15:0] w_height = HEIGHT;
always @(dot_cnt[3:0]) begin
case (dot_cnt[3:0])
4'd0 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_width[ 7: 4], {MAX_BPC-4{1'b0}}, w_width[11: 8], {MAX_BPC-4{1'b0}}, w_width[15:12]};
4'd1 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_height[11: 8], {MAX_BPC-4{1'b0}}, w_height[15:12], {MAX_BPC-4{1'b0}}, w_width[ 3: 0]};
4'd2 : ctrl_data = {{MAX_BPC-4{1'b0}}, 4'b0011, {MAX_BPC-4{1'b0}}, w_height[ 3: 0], {MAX_BPC-4{1'b0}}, w_height[ 7: 4]};
default : ctrl_data = {MAX_BPC*3{1'bx}};
endcase
end
endmodule |
module pr_region_default_mm_bridge_0 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
endmodule |
module pr_region_default_clock_in (
input wire in_clk, // in_clk.clk
output wire out_clk // out_clk.clk
);
endmodule |
module pr_region_default_sysid_qsys_0 (
input wire clock, // clk.clk
output wire [31:0] readdata, // control_slave.readdata
input wire address, // .address
input wire reset_n // reset.reset_n
);
endmodule |
module pr_region_default_onchip_memory2_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [6:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [31:0] readdata, // .readdata
input wire [31:0] writedata, // .writedata
input wire [3:0] byteenable // .byteenable
);
endmodule |
module pr_region_default_reset_in (
input wire clk, // clk.clk
input wire in_reset, // in_reset.reset
output wire out_reset // out_reset.reset
);
endmodule |
module pr_region_default_Top_0 (
input wire clock, // clock.clk
output wire [5:0] io_M_AXI_0_AWID, // io_M_AXI_0.awid
output wire [31:0] io_M_AXI_0_AWUSER, // .awuser
output wire [31:0] io_M_AXI_0_AWADDR, // .awaddr
output wire [7:0] io_M_AXI_0_AWLEN, // .awlen
output wire [2:0] io_M_AXI_0_AWSIZE, // .awsize
output wire [1:0] io_M_AXI_0_AWBURST, // .awburst
output wire io_M_AXI_0_AWLOCK, // .awlock
output wire [3:0] io_M_AXI_0_AWCACHE, // .awcache
output wire [2:0] io_M_AXI_0_AWPROT, // .awprot
output wire [3:0] io_M_AXI_0_AWQOS, // .awqos
output wire io_M_AXI_0_AWVALID, // .awvalid
input wire io_M_AXI_0_AWREADY, // .awready
output wire [5:0] io_M_AXI_0_ARID, // .arid
output wire [31:0] io_M_AXI_0_ARUSER, // .aruser
output wire [31:0] io_M_AXI_0_ARADDR, // .araddr
output wire [7:0] io_M_AXI_0_ARLEN, // .arlen
output wire [2:0] io_M_AXI_0_ARSIZE, // .arsize
output wire [1:0] io_M_AXI_0_ARBURST, // .arburst
output wire io_M_AXI_0_ARLOCK, // .arlock
output wire [3:0] io_M_AXI_0_ARCACHE, // .arcache
output wire [2:0] io_M_AXI_0_ARPROT, // .arprot
output wire [3:0] io_M_AXI_0_ARQOS, // .arqos
output wire io_M_AXI_0_ARVALID, // .arvalid
input wire io_M_AXI_0_ARREADY, // .arready
output wire [511:0] io_M_AXI_0_WDATA, // .wdata
output wire [63:0] io_M_AXI_0_WSTRB, // .wstrb
output wire io_M_AXI_0_WLAST, // .wlast
output wire io_M_AXI_0_WVALID, // .wvalid
input wire io_M_AXI_0_WREADY, // .wready
input wire [5:0] io_M_AXI_0_RID, // .rid
input wire [31:0] io_M_AXI_0_RUSER, // .ruser
input wire [511:0] io_M_AXI_0_RDATA, // .rdata
input wire [1:0] io_M_AXI_0_RRESP, // .rresp
input wire io_M_AXI_0_RLAST, // .rlast
input wire io_M_AXI_0_RVALID, // .rvalid
output wire io_M_AXI_0_RREADY, // .rready
input wire [5:0] io_M_AXI_0_BID, // .bid
input wire [31:0] io_M_AXI_0_BUSER, // .buser
input wire [1:0] io_M_AXI_0_BRESP, // .bresp
input wire io_M_AXI_0_BVALID, // .bvalid
output wire io_M_AXI_0_BREADY, // .bready
input wire [6:0] io_S_AVALON_address, // io_S_AVALON.address
output wire [31:0] io_S_AVALON_readdata, // .readdata
input wire io_S_AVALON_chipselect, // .chipselect
input wire io_S_AVALON_write, // .write
input wire io_S_AVALON_read, // .read
input wire [31:0] io_S_AVALON_writedata, // .writedata
input wire reset // reset.reset
);
endmodule |
module pr_region_default_mm_bridge_1 #(
parameter DATA_WIDTH = 512,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 32,
parameter BURSTCOUNT_WIDTH = 5,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [63:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [63:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
endmodule |
module pr_region_default_mm_bridge_0 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_0 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 4, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 4, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule |
module pr_region_default_sysid_qsys_0 (
input wire clock, // clk.clk
output wire [31:0] readdata, // control_slave.readdata
input wire address, // .address
input wire reset_n // reset.reset_n
);
altera_avalon_sysid_qsys #(
.ID_VALUE (-87110914),
.TIMESTAMP (0)
) sysid_qsys_0 (
.clock (clock), // input, width = 1, clk.clk
.reset_n (reset_n), // input, width = 1, reset.reset_n
.readdata (readdata), // output, width = 32, control_slave.readdata
.address (address) // input, width = 1, .address
);
endmodule |
module altera_avalon_sysid_qsys #(
parameter ID_VALUE = 1,
parameter TIMESTAMP = 1
)(
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? TIMESTAMP : ID_VALUE;
endmodule |
module pr_region_default_onchip_memory2_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [6:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [31:0] readdata, // .readdata
input wire [31:0] writedata, // .writedata
input wire [3:0] byteenable // .byteenable
);
pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy onchip_memory2_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 7, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 32, .readdata
.writedata (writedata), // input, width = 32, .writedata
.byteenable (byteenable), // input, width = 4, .byteenable
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule |
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