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module Computer_System_Video_In_Subsystem (
input wire [1:0] edge_detection_control_slave_address, // edge_detection_control_slave.address
input wire edge_detection_control_slave_write_n, // .write_n
input wire [31:0] edge_detection_control_slave_writedata, // .writedata
input wire edge_detection_control_slave_chipselect, // .chipselect
output wire [31:0] edge_detection_control_slave_readdata, // .readdata
input wire sys_clk_clk, // sys_clk.clk
input wire sys_reset_reset_n, // sys_reset.reset_n
input wire [15:0] top_avalon_slave_address, // top_avalon_slave.address
output wire [31:0] top_avalon_slave_readdata, // .readdata
input wire [31:0] top_avalon_slave_writedata, // .writedata
input wire top_avalon_slave_write_n, // .write_n
input wire top_avalon_slave_chipselect, // .chipselect
input wire top_io_buff_out_waitrequest, // top_io_buff_out.waitrequest
output wire [31:0] top_io_buff_out_address, // .address
output wire top_io_buff_out_write, // .write
output wire [15:0] top_io_buff_out_writedata, // .writedata
output wire [31:0] top_io_ledr_stream_writedata, // top_io_ledr_stream.writedata
output wire [3:0] top_io_ledr_stream_address, // .address
output wire top_io_ledr_stream_write_n, // .write_n
output wire top_io_ledr_stream_chipselect, // .chipselect
output wire [31:0] top_io_switches_stream_address, // top_io_switches_stream.address
input wire [31:0] top_io_switches_stream_readdata, // .readdata
output wire top_io_switches_stream_read, // .read
input wire video_in_TD_CLK27, // video_in.TD_CLK27
input wire [7:0] video_in_TD_DATA, // .TD_DATA
input wire video_in_TD_HS, // .TD_HS
input wire video_in_TD_VS, // .TD_VS
input wire video_in_clk27_reset, // .clk27_reset
output wire video_in_TD_RESET, // .TD_RESET
output wire video_in_overflow_flag, // .overflow_flag
input wire [1:0] video_in_dma_control_slave_address, // video_in_dma_control_slave.address
input wire [3:0] video_in_dma_control_slave_byteenable, // .byteenable
input wire video_in_dma_control_slave_read, // .read
input wire video_in_dma_control_slave_write, // .write
input wire [31:0] video_in_dma_control_slave_writedata, // .writedata
output wire [31:0] video_in_dma_control_slave_readdata, // .readdata
output wire [31:0] video_in_dma_master_address, // video_in_dma_master.address
input wire video_in_dma_master_waitrequest, // .waitrequest
output wire video_in_dma_master_write, // .write
output wire [15:0] video_in_dma_master_writedata // .writedata
);
wire video_in_chroma_resampler_avalon_chroma_source_valid; // Video_In_Chroma_Resampler:stream_out_valid -> Edge_Detection_Subsystem:video_stream_sink_valid
wire [23:0] video_in_chroma_resampler_avalon_chroma_source_data; // Video_In_Chroma_Resampler:stream_out_data -> Edge_Detection_Subsystem:video_stream_sink_data
wire video_in_chroma_resampler_avalon_chroma_source_ready; // Edge_Detection_Subsystem:video_stream_sink_ready -> Video_In_Chroma_Resampler:stream_out_ready
wire video_in_chroma_resampler_avalon_chroma_source_startofpacket; // Video_In_Chroma_Resampler:stream_out_startofpacket -> Edge_Detection_Subsystem:video_stream_sink_startofpacket
wire video_in_chroma_resampler_avalon_chroma_source_endofpacket; // Video_In_Chroma_Resampler:stream_out_endofpacket -> Edge_Detection_Subsystem:video_stream_sink_endofpacket
wire video_in_clipper_avalon_clipper_source_valid; // Video_In_Clipper:stream_out_valid -> Video_In_Scaler:stream_in_valid
wire [15:0] video_in_clipper_avalon_clipper_source_data; // Video_In_Clipper:stream_out_data -> Video_In_Scaler:stream_in_data
wire video_in_clipper_avalon_clipper_source_ready; // Video_In_Scaler:stream_in_ready -> Video_In_Clipper:stream_out_ready
wire video_in_clipper_avalon_clipper_source_startofpacket; // Video_In_Clipper:stream_out_startofpacket -> Video_In_Scaler:stream_in_startofpacket
wire video_in_clipper_avalon_clipper_source_endofpacket; // Video_In_Clipper:stream_out_endofpacket -> Video_In_Scaler:stream_in_endofpacket
wire video_in_csc_avalon_csc_source_valid; // Video_In_CSC:stream_out_valid -> Video_In_RGB_Resampler:stream_in_valid
wire [23:0] video_in_csc_avalon_csc_source_data; // Video_In_CSC:stream_out_data -> Video_In_RGB_Resampler:stream_in_data
wire video_in_csc_avalon_csc_source_ready; // Video_In_RGB_Resampler:stream_in_ready -> Video_In_CSC:stream_out_ready
wire video_in_csc_avalon_csc_source_startofpacket; // Video_In_CSC:stream_out_startofpacket -> Video_In_RGB_Resampler:stream_in_startofpacket
wire video_in_csc_avalon_csc_source_endofpacket; // Video_In_CSC:stream_out_endofpacket -> Video_In_RGB_Resampler:stream_in_endofpacket
wire video_in_avalon_decoder_source_valid; // Video_In:stream_out_valid -> Video_In_Chroma_Resampler:stream_in_valid
wire [15:0] video_in_avalon_decoder_source_data; // Video_In:stream_out_data -> Video_In_Chroma_Resampler:stream_in_data
wire video_in_avalon_decoder_source_ready; // Video_In_Chroma_Resampler:stream_in_ready -> Video_In:stream_out_ready
wire video_in_avalon_decoder_source_startofpacket; // Video_In:stream_out_startofpacket -> Video_In_Chroma_Resampler:stream_in_startofpacket
wire video_in_avalon_decoder_source_endofpacket; // Video_In:stream_out_endofpacket -> Video_In_Chroma_Resampler:stream_in_endofpacket
wire video_in_rgb_resampler_avalon_rgb_source_valid; // Video_In_RGB_Resampler:stream_out_valid -> Video_In_Clipper:stream_in_valid
wire [15:0] video_in_rgb_resampler_avalon_rgb_source_data; // Video_In_RGB_Resampler:stream_out_data -> Video_In_Clipper:stream_in_data
wire video_in_rgb_resampler_avalon_rgb_source_ready; // Video_In_Clipper:stream_in_ready -> Video_In_RGB_Resampler:stream_out_ready
wire video_in_rgb_resampler_avalon_rgb_source_startofpacket; // Video_In_RGB_Resampler:stream_out_startofpacket -> Video_In_Clipper:stream_in_startofpacket
wire video_in_rgb_resampler_avalon_rgb_source_endofpacket; // Video_In_RGB_Resampler:stream_out_endofpacket -> Video_In_Clipper:stream_in_endofpacket
wire edge_detection_subsystem_video_stream_source_valid; // Edge_Detection_Subsystem:video_stream_source_valid -> Video_In_CSC:stream_in_valid
wire [23:0] edge_detection_subsystem_video_stream_source_data; // Edge_Detection_Subsystem:video_stream_source_data -> Video_In_CSC:stream_in_data
wire edge_detection_subsystem_video_stream_source_ready; // Video_In_CSC:stream_in_ready -> Edge_Detection_Subsystem:video_stream_source_ready
wire edge_detection_subsystem_video_stream_source_startofpacket; // Edge_Detection_Subsystem:video_stream_source_startofpacket -> Video_In_CSC:stream_in_startofpacket
wire edge_detection_subsystem_video_stream_source_endofpacket; // Edge_Detection_Subsystem:video_stream_source_endofpacket -> Video_In_CSC:stream_in_endofpacket
wire video_in_scaler_avalon_scaler_source_valid; // Video_In_Scaler:stream_out_valid -> avalon_st_adapter:in_0_valid
wire [15:0] video_in_scaler_avalon_scaler_source_data; // Video_In_Scaler:stream_out_data -> avalon_st_adapter:in_0_data
wire video_in_scaler_avalon_scaler_source_ready; // avalon_st_adapter:in_0_ready -> Video_In_Scaler:stream_out_ready
wire video_in_scaler_avalon_scaler_source_startofpacket; // Video_In_Scaler:stream_out_startofpacket -> avalon_st_adapter:in_0_startofpacket
wire video_in_scaler_avalon_scaler_source_endofpacket; // Video_In_Scaler:stream_out_endofpacket -> avalon_st_adapter:in_0_endofpacket
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Top:io_S_STREAM_stream_in_valid
wire [15:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Top:io_S_STREAM_stream_in_data
wire avalon_st_adapter_out_0_ready; // Top:io_S_STREAM_stream_in_ready -> avalon_st_adapter:out_0_ready
wire avalon_st_adapter_out_0_startofpacket; // avalon_st_adapter:out_0_startofpacket -> Top:io_S_STREAM_stream_in_startofpacket
wire avalon_st_adapter_out_0_endofpacket; // avalon_st_adapter:out_0_endofpacket -> Top:io_S_STREAM_stream_in_endofpacket
wire avalon_st_adapter_out_0_empty; // avalon_st_adapter:out_0_empty -> Top:io_S_STREAM_stream_in_empty
wire top_avalon_streaming_source_valid; // Top:io_S_STREAM_stream_out_valid -> avalon_st_adapter_001:in_0_valid
wire [15:0] top_avalon_streaming_source_data; // Top:io_S_STREAM_stream_out_data -> avalon_st_adapter_001:in_0_data
wire top_avalon_streaming_source_ready; // avalon_st_adapter_001:in_0_ready -> Top:io_S_STREAM_stream_out_ready
wire top_avalon_streaming_source_startofpacket; // Top:io_S_STREAM_stream_out_startofpacket -> avalon_st_adapter_001:in_0_startofpacket
wire top_avalon_streaming_source_endofpacket; // Top:io_S_STREAM_stream_out_endofpacket -> avalon_st_adapter_001:in_0_endofpacket
wire top_avalon_streaming_source_empty; // Top:io_S_STREAM_stream_out_empty -> avalon_st_adapter_001:in_0_empty
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> Video_In_DMA:stream_valid
wire [15:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> Video_In_DMA:stream_data
wire avalon_st_adapter_001_out_0_ready; // Video_In_DMA:stream_ready -> avalon_st_adapter_001:out_0_ready
wire avalon_st_adapter_001_out_0_startofpacket; // avalon_st_adapter_001:out_0_startofpacket -> Video_In_DMA:stream_startofpacket
wire avalon_st_adapter_001_out_0_endofpacket; // avalon_st_adapter_001:out_0_endofpacket -> Video_In_DMA:stream_endofpacket
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [Top:reset, Video_In:reset, Video_In_CSC:reset, Video_In_Chroma_Resampler:reset, Video_In_Clipper:reset, Video_In_DMA:reset, Video_In_RGB_Resampler:reset, Video_In_Scaler:reset, avalon_st_adapter:in_rst_0_reset, avalon_st_adapter_001:in_rst_0_reset]
Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem edge_detection_subsystem (
.edge_detection_control_slave_address (edge_detection_control_slave_address), // edge_detection_control_slave.address
.edge_detection_control_slave_write_n (edge_detection_control_slave_write_n), // .write_n
.edge_detection_control_slave_writedata (edge_detection_control_slave_writedata), // .writedata
.edge_detection_control_slave_chipselect (edge_detection_control_slave_chipselect), // .chipselect
.edge_detection_control_slave_readdata (edge_detection_control_slave_readdata), // .readdata
.sys_clk_clk (sys_clk_clk), // sys_clk.clk
.sys_reset_reset_n (sys_reset_reset_n), // sys_reset.reset_n
.video_stream_sink_data (video_in_chroma_resampler_avalon_chroma_source_data), // video_stream_sink.data
.video_stream_sink_startofpacket (video_in_chroma_resampler_avalon_chroma_source_startofpacket), // .startofpacket
.video_stream_sink_endofpacket (video_in_chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.video_stream_sink_valid (video_in_chroma_resampler_avalon_chroma_source_valid), // .valid
.video_stream_sink_ready (video_in_chroma_resampler_avalon_chroma_source_ready), // .ready
.video_stream_source_ready (edge_detection_subsystem_video_stream_source_ready), // video_stream_source.ready
.video_stream_source_data (edge_detection_subsystem_video_stream_source_data), // .data
.video_stream_source_startofpacket (edge_detection_subsystem_video_stream_source_startofpacket), // .startofpacket
.video_stream_source_endofpacket (edge_detection_subsystem_video_stream_source_endofpacket), // .endofpacket
.video_stream_source_valid (edge_detection_subsystem_video_stream_source_valid) // .valid
);
Top top (
.clock (sys_clk_clk), // clock_sink.clk
.reset (rst_controller_reset_out_reset), // reset_sink.reset
.io_S_AVALON_address (top_avalon_slave_address), // avalon_slave.address
.io_S_AVALON_readdata (top_avalon_slave_readdata), // .readdata
.io_S_AVALON_writedata (top_avalon_slave_writedata), // .writedata
.io_S_AVALON_write_n (top_avalon_slave_write_n), // .write_n
.io_S_AVALON_chipselect (top_avalon_slave_chipselect), // .chipselect
.io_S_STREAM_stream_in_data (avalon_st_adapter_out_0_data), // avalon_streaming_sink.data
.io_S_STREAM_stream_in_startofpacket (avalon_st_adapter_out_0_startofpacket), // .startofpacket
.io_S_STREAM_stream_in_endofpacket (avalon_st_adapter_out_0_endofpacket), // .endofpacket
.io_S_STREAM_stream_in_empty (avalon_st_adapter_out_0_empty), // .empty
.io_S_STREAM_stream_in_ready (avalon_st_adapter_out_0_ready), // .ready
.io_S_STREAM_stream_in_valid (avalon_st_adapter_out_0_valid), // .valid
.io_S_STREAM_stream_out_data (top_avalon_streaming_source_data), // avalon_streaming_source.data
.io_S_STREAM_stream_out_empty (top_avalon_streaming_source_empty), // .empty
.io_S_STREAM_stream_out_endofpacket (top_avalon_streaming_source_endofpacket), // .endofpacket
.io_S_STREAM_stream_out_startofpacket (top_avalon_streaming_source_startofpacket), // .startofpacket
.io_S_STREAM_stream_out_ready (top_avalon_streaming_source_ready), // .ready
.io_S_STREAM_stream_out_valid (top_avalon_streaming_source_valid), // .valid
.io_LEDR_STREAM_writedata (top_io_ledr_stream_writedata), // io_LEDR_STREAM.writedata
.io_LEDR_STREAM_address (top_io_ledr_stream_address), // .address
.io_LEDR_STREAM_write_n (top_io_ledr_stream_write_n), // .write_n
.io_LEDR_STREAM_chipselect (top_io_ledr_stream_chipselect), // .chipselect
.io_SWITCHES_STREAM_address (top_io_switches_stream_address), // io_SWITCHES_STREAM.address
.io_SWITCHES_STREAM_readdata (top_io_switches_stream_readdata), // .readdata
.io_SWITCHES_STREAM_read (top_io_switches_stream_read), // .read
.io_BUFFOUT_waitrequest (top_io_buff_out_waitrequest), // io_BUFFOUT.waitrequest
.io_BUFFOUT_address (top_io_buff_out_address), // .address
.io_BUFFOUT_write (top_io_buff_out_write), // .write
.io_BUFFOUT_writedata (top_io_buff_out_writedata) // .writedata
);
Computer_System_Video_In_Subsystem_Video_In video_in (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_out_ready (video_in_avalon_decoder_source_ready), // avalon_decoder_source.ready
.stream_out_startofpacket (video_in_avalon_decoder_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_avalon_decoder_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_avalon_decoder_source_valid), // .valid
.stream_out_data (video_in_avalon_decoder_source_data), // .data
.TD_CLK27 (video_in_TD_CLK27), // external_interface.export
.TD_DATA (video_in_TD_DATA), // .export
.TD_HS (video_in_TD_HS), // .export
.TD_VS (video_in_TD_VS), // .export
.clk27_reset (video_in_clk27_reset), // .export
.TD_RESET (video_in_TD_RESET), // .export
.overflow_flag (video_in_overflow_flag) // .export
);
Computer_System_Video_In_Subsystem_Video_In_CSC video_in_csc (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (edge_detection_subsystem_video_stream_source_startofpacket), // avalon_csc_sink.startofpacket
.stream_in_endofpacket (edge_detection_subsystem_video_stream_source_endofpacket), // .endofpacket
.stream_in_valid (edge_detection_subsystem_video_stream_source_valid), // .valid
.stream_in_ready (edge_detection_subsystem_video_stream_source_ready), // .ready
.stream_in_data (edge_detection_subsystem_video_stream_source_data), // .data
.stream_out_ready (video_in_csc_avalon_csc_source_ready), // avalon_csc_source.ready
.stream_out_startofpacket (video_in_csc_avalon_csc_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_csc_avalon_csc_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_csc_avalon_csc_source_valid), // .valid
.stream_out_data (video_in_csc_avalon_csc_source_data) // .data
);
Computer_System_Video_In_Subsystem_Video_In_Chroma_Resampler video_in_chroma_resampler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (video_in_avalon_decoder_source_startofpacket), // avalon_chroma_sink.startofpacket
.stream_in_endofpacket (video_in_avalon_decoder_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_avalon_decoder_source_valid), // .valid
.stream_in_ready (video_in_avalon_decoder_source_ready), // .ready
.stream_in_data (video_in_avalon_decoder_source_data), // .data
.stream_out_ready (video_in_chroma_resampler_avalon_chroma_source_ready), // avalon_chroma_source.ready
.stream_out_startofpacket (video_in_chroma_resampler_avalon_chroma_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_chroma_resampler_avalon_chroma_source_valid), // .valid
.stream_out_data (video_in_chroma_resampler_avalon_chroma_source_data) // .data
);
Computer_System_Video_In_Subsystem_Video_In_Clipper video_in_clipper (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_data (video_in_rgb_resampler_avalon_rgb_source_data), // avalon_clipper_sink.data
.stream_in_startofpacket (video_in_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_in_endofpacket (video_in_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (video_in_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_out_ready (video_in_clipper_avalon_clipper_source_ready), // avalon_clipper_source.ready
.stream_out_data (video_in_clipper_avalon_clipper_source_data), // .data
.stream_out_startofpacket (video_in_clipper_avalon_clipper_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_clipper_avalon_clipper_source_valid) // .valid
);
Computer_System_Video_In_Subsystem_Video_In_DMA video_in_dma (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_data (avalon_st_adapter_001_out_0_data), // avalon_dma_sink.data
.stream_startofpacket (avalon_st_adapter_001_out_0_startofpacket), // .startofpacket
.stream_endofpacket (avalon_st_adapter_001_out_0_endofpacket), // .endofpacket
.stream_valid (avalon_st_adapter_001_out_0_valid), // .valid
.stream_ready (avalon_st_adapter_001_out_0_ready), // .ready
.slave_address (video_in_dma_control_slave_address), // avalon_dma_control_slave.address
.slave_byteenable (video_in_dma_control_slave_byteenable), // .byteenable
.slave_read (video_in_dma_control_slave_read), // .read
.slave_write (video_in_dma_control_slave_write), // .write
.slave_writedata (video_in_dma_control_slave_writedata), // .writedata
.slave_readdata (video_in_dma_control_slave_readdata), // .readdata
.master_address (video_in_dma_master_address), // avalon_dma_master.address
.master_waitrequest (video_in_dma_master_waitrequest), // .waitrequest
.master_write (video_in_dma_master_write), // .write
.master_writedata (video_in_dma_master_writedata) // .writedata
);
Computer_System_Video_In_Subsystem_Video_In_RGB_Resampler video_in_rgb_resampler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (video_in_csc_avalon_csc_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (video_in_csc_avalon_csc_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_csc_avalon_csc_source_valid), // .valid
.stream_in_ready (video_in_csc_avalon_csc_source_ready), // .ready
.stream_in_data (video_in_csc_avalon_csc_source_data), // .data
.stream_out_ready (video_in_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (video_in_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (video_in_rgb_resampler_avalon_rgb_source_data) // .data
);
Computer_System_Video_In_Subsystem_Video_In_Scaler video_in_scaler (
.clk (sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.stream_in_startofpacket (video_in_clipper_avalon_clipper_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (video_in_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_clipper_avalon_clipper_source_valid), // .valid
.stream_in_ready (video_in_clipper_avalon_clipper_source_ready), // .ready
.stream_in_data (video_in_clipper_avalon_clipper_source_data), // .data
.stream_out_ready (video_in_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (video_in_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (video_in_scaler_avalon_scaler_source_data) // .data
);
Computer_System_Video_In_Subsystem_avalon_st_adapter #(
.inBitsPerSymbol (16),
.inUsePackets (1),
.inDataWidth (16),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (16),
.outChannelWidth (0),
.outErrorWidth (0),
.outUseEmptyPort (1),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (rst_controller_reset_out_reset), // in_rst_0.reset
.in_0_data (video_in_scaler_avalon_scaler_source_data), // in_0.data
.in_0_valid (video_in_scaler_avalon_scaler_source_valid), // .valid
.in_0_ready (video_in_scaler_avalon_scaler_source_ready), // .ready
.in_0_startofpacket (video_in_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.in_0_endofpacket (video_in_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_startofpacket (avalon_st_adapter_out_0_startofpacket), // .startofpacket
.out_0_endofpacket (avalon_st_adapter_out_0_endofpacket), // .endofpacket
.out_0_empty (avalon_st_adapter_out_0_empty) // .empty
);
Computer_System_Video_In_Subsystem_avalon_st_adapter_001 #(
.inBitsPerSymbol (16),
.inUsePackets (1),
.inDataWidth (16),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (1),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (16),
.outChannelWidth (0),
.outErrorWidth (0),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (rst_controller_reset_out_reset), // in_rst_0.reset
.in_0_data (top_avalon_streaming_source_data), // in_0.data
.in_0_valid (top_avalon_streaming_source_valid), // .valid
.in_0_ready (top_avalon_streaming_source_ready), // .ready
.in_0_startofpacket (top_avalon_streaming_source_startofpacket), // .startofpacket
.in_0_endofpacket (top_avalon_streaming_source_endofpacket), // .endofpacket
.in_0_empty (top_avalon_streaming_source_empty), // .empty
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_startofpacket (avalon_st_adapter_001_out_0_startofpacket), // .startofpacket
.out_0_endofpacket (avalon_st_adapter_001_out_0_endofpacket) // .endofpacket
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~sys_reset_reset_n), // reset_in0.reset
.clk (sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module altera_up_video_dual_clock_fifo (
// Inputs
wrclk,
wrreq,
data,
rdclk,
rdreq,
// Outputs
wrusedw,
wrfull,
q,
rdusedw,
rdempty
);
parameter DW = 18;
input wrclk;
input wrreq;
input [(DW-1):0] data;
input rdclk;
input rdreq;
output [6:0] wrusedw;
output wrfull;
output [(DW-1):0] q;
output [6:0] rdusedw;
output rdempty;
dcfifo dcfifo_component (
// Inputs
.wrclk (wrclk),
.wrreq (wrreq),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (q),
.rdusedw (rdusedw),
.rdempty (rdempty)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = DW,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule |
module Computer_System_SysID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1493960014 : 0;
endmodule |
module designware_divmod(clock, reset, dividend, divisor, quot_out, rem_out);
parameter DIVIDEND_BIT_WIDTH = 16;
parameter DIVISOR_BIT_WIDTH = 16;
parameter SIGNED = 0; // 0 means unsigned, 1 means two's complement signed numbers
parameter IS_DIV = 1; // 0 means mod, 1 means div
parameter NUM_STAGES = 2; // number of pipeline stages, the latency of the multiply is num_stages - 1
input clock, reset; //note reset is active low
input [DIVIDEND_BIT_WIDTH-1:0] dividend;
input [DIVISOR_BIT_WIDTH-1:0] divisor;
output [DIVIDEND_BIT_WIDTH-1:0] quot_out, rem_out;
wire divide_by_0; //left floating intentionally (assumes we don't need this signal)
//computes dividend / divisor, assumes asynchronous reset
DW_div_pipe #(
.a_width(DIVIDEND_BIT_WIDTH),
.b_width(DIVISOR_BIT_WIDTH),
.tc_mode(SIGNED),
.rem_mode(IS_DIV),
.num_stages(NUM_STAGES),
.stall_mode(1'b0),
.rst_mode(1)) div_pipe_inst (
.clk(clock),
.rst_n(reset),
.en(1'b1),
.a(dividend),
.b(divisor),
.quotient(quot_out),
.remainder(rem_out),
.divide_by_0(divide_by_0)
);
endmodule |
module designware_mult (clock, reset, in0, in1, out);
parameter IN0_BIT_WIDTH = 16;
parameter IN1_BIT_WIDTH = 16;
parameter OUT_BIT_WIDTH = 16;
parameter SIGNED = 0; //0 means unsigned, 1 means two's complement signed numbers
parameter NUM_STAGES = 2; //number of pipeline stages, the latency of the multiply is num_stages - 1
input clock, reset; //note reset is active low
input [IN0_BIT_WIDTH-1:0] in0;
input [IN1_BIT_WIDTH-1:0] in1;
output [OUT_BIT_WIDTH-1:0] out;
//assumes asynchronous reset
DW_mult_pipe #(.a_width(IN0_BIT_WIDTH), .b_width(IN1_BIT_WIDTH), .num_stages(NUM_STAGES), .stall_mode(1'b0), .rst_mode(1)) mult_pipe_inst (.clk(clock), .rst_n(reset), .en(1'b1), .tc(SIGNED), .a(in0), .b(in1), .product(out));
endmodule |
module lab3_user_logic # (
parameter LED_WIDTH = 8
)
(
input S_AXI_ACLK,
input slv_reg_wren,
input [2:0] axi_awaddr,
input [31:0] S_AXI_WDATA,
input S_AXI_ARESETN,
output reg [LED_WIDTH-1:0] LED
);
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
LED <= 4'b0;
else
if (slv_reg_wren && (axi_awaddr == 3'h0))
LED <= S_AXI_WDATA[LED_WIDTH-1:0];
end
endmodule |
module math_ip (
////////////////////////////////////////////////////////////////////////////
// System Signals
////////////////////////////////////////////////////////////////////////////
// AXI clock signal
input wire S_AXI_ACLK,
////////////////////////////////////////////////////////////////////////////
// AXI active low reset signal
input wire S_AXI_ARESETN,
////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address channel Ports
////////////////////////////////////////////////////////////////////////////
// Master Interface Write Address Channel ports
// Write address (issued by master, acceped by Slave)
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_AWADDR,
////////////////////////////////////////////////////////////////////////////
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
////////////////////////////////////////////////////////////////////////////
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Data channel Ports
// Write data (issued by master, acceped by Slave)
input wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
////////////////////////////////////////////////////////////////////////////
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [`C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
////////////////////////////////////////////////////////////////////////////
//Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
////////////////////////////////////////////////////////////////////////////
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Response channel Ports
////////////////////////////////////////////////////////////////////////////
// Write response. This signal indicates the status
// of the write transaction.
output wire [1:0] S_AXI_BRESP,
////////////////////////////////////////////////////////////////////////////
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
////////////////////////////////////////////////////////////////////////////
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
////////////////////////////////////////////////////////////////////////////
// Slave Interface Read Address channel Ports
// Read address (issued by master, acceped by Slave)
input wire [`C_S_AXI_ADDR_WIDTH - 1:0] S_AXI_ARADDR,
////////////////////////////////////////////////////////////////////////////
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
////////////////////////////////////////////////////////////////////////////
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
////////////////////////////////////////////////////////////////////////////
// Slave Interface Read Data channel Ports
// Read data (issued by slave)
output wire [`C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
////////////////////////////////////////////////////////////////////////////
// Read response. This signal indicates the status of the
// read transfer.
output wire [1:0] S_AXI_RRESP,
////////////////////////////////////////////////////////////////////////////
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
////////////////////////////////////////////////////////////////////////////
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY,
// User defined ports
input wire [7:0] ain_vio,
input wire [7:0] bin_vio,
input wire sel,
output wire [8:0] result
);
////////////////////////////////////////////////////////////////////////////
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
////////////////////////////////////////////////////////////////////////////
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bd);
integer bit_depth;
begin
bit_depth = bd;
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
localparam integer ADDR_LSB = clogb2(`C_S_AXI_DATA_WIDTH/8)-1;
localparam integer ADDR_MSB = `C_S_AXI_ADDR_WIDTH;
////////////////////////////////////////////////////////////////////////////
// AXI4 Lite internal signals
////////////////////////////////////////////////////////////////////////////
// read response
reg [1 :0] axi_rresp;
////////////////////////////////////////////////////////////////////////////
// write response
reg [1 :0] axi_bresp;
////////////////////////////////////////////////////////////////////////////
// write address acceptance
reg axi_awready;
////////////////////////////////////////////////////////////////////////////
// write data acceptance
reg axi_wready;
////////////////////////////////////////////////////////////////////////////
// write response valid
reg axi_bvalid;
////////////////////////////////////////////////////////////////////////////
// read data valid
reg axi_rvalid;
////////////////////////////////////////////////////////////////////////////
// write address
reg [ADDR_MSB-1:0] axi_awaddr;
////////////////////////////////////////////////////////////////////////////
// read address valid
reg [ADDR_MSB-1:0] axi_araddr;
////////////////////////////////////////////////////////////////////////////
// read data
reg [`C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
////////////////////////////////////////////////////////////////////////////
// read address acceptance
reg axi_arready;
////////////////////////////////////////////////////////////////////////////
// Example-specific design signals
////////////////////////////////////////////////////////////////////////////
// Signals for user logic chip select generation
////////////////////////////////////////////////////////////////////////////
// Signals for user logic register space example
// Two slave register
////////////////////////////////////////////////////////////////////////////
// Slave register 0
reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
////////////////////////////////////////////////////////////////////////////
// Slave register 1
reg [`C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Slave register read enable
wire slv_reg_rden;
////////////////////////////////////////////////////////////////////////////
// Slave register write enable
wire slv_reg_wren;
////////////////////////////////////////////////////////////////////////////
// register read data
reg [`C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
////////////////////////////////////////////////////////////////////////////
//I/O Connections assignments
////////////////////////////////////////////////////////////////////////////
//Write Address Ready (AWREADY)
assign S_AXI_AWREADY = axi_awready;
////////////////////////////////////////////////////////////////////////////
//Write Data Ready(WREADY)
assign S_AXI_WREADY = axi_wready;
////////////////////////////////////////////////////////////////////////////
//Write Response (BResp)and response valid (BVALID)
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
////////////////////////////////////////////////////////////////////////////
//Read Address Ready(AREADY)
assign S_AXI_ARREADY = axi_arready;
////////////////////////////////////////////////////////////////////////////
//Read and Read Data (RDATA), Read Valid (RVALID) and Response (RRESP)
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RVALID = axi_rvalid;
assign S_AXI_RRESP = axi_rresp;
////////////////////////////////////////////////////////////////////////////
// Implement axi_awready generation
//
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
////////////////////////////////////////////////////////////////////////////
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement axi_awaddr latching
//
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
////////////////////////////////////////////////////////////////////////////
// address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement axi_wready generation
//
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
////////////////////////////////////////////////////////////////////////////
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement memory mapped register select and write logic generation
//
// The write data is accepted and written to memory mapped
// registers (slv_reg0, slv_reg1) when axi_wready,
// S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
//
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= {`C_S_AXI_DATA_WIDTH{1'b0}};
slv_reg1 <= {`C_S_AXI_DATA_WIDTH{1'b0}};
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_MSB-1:ADDR_LSB] )
3'h0 :
for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h1 :
for ( byte_index = 0; byte_index <= (`C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement write response logic generation
//
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement axi_arready generation
//
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= {ADDR_MSB{1'b0}};
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////
// Implement memory mapped register select and read logic generation
//
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////////
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @( result, slv_reg1, S_AXI_ARESETN, slv_reg_rden, axi_araddr)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= {`C_S_AXI_DATA_WIDTH{1'b0}};
end
else
begin
// Read address mux
case ( axi_araddr[ADDR_MSB-1:ADDR_LSB] )
3'h0 : reg_data_out <= {23'b0,result};
3'h1 : reg_data_out <= slv_reg1;
default : reg_data_out <= {`C_S_AXI_DATA_WIDTH{1'b0}};
endcase
//end
end
end
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
////////////////////////////////////////////////////////////////////////////
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
lab2_user_logic U1 (
.clk(S_AXI_ACLK),
.sel(sel),
.ain(slv_reg0),
.bin(slv_reg1),
.ain_vio(ain_vio),
.bin_vio(bin_vio),
.Reset_n(S_AXI_ARESETN),
.result(result)
);
endmodule |
module div_umc ( port_x, port_y, port_nCLK, port_b, port_a, port_c, port_tmp2);
inout wire port_x;
output wire port_y;
input wire port_nCLK;
input wire port_b;
input wire port_a;
input wire port_c;
inout wire port_tmp2;
// Wires
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire ck;
wire cck;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
wire w20;
wire w21;
wire w22;
wire w23;
wire w24;
wire w25;
wire w26;
wire w27;
wire w28;
wire w29;
wire w30;
wire w31;
wire w32;
wire w33;
wire w34;
wire w35;
wire w36;
wire w37;
wire w38;
wire w39;
wire w40;
wire w41;
wire w42;
wire w43;
wire w44;
wire tmp1;
wire w46;
wire w47;
wire w48;
wire fb;
wire w_tmp2;
wire w51;
wire w52;
assign port_x = w39;
assign port_y = w34;
assign w38 = port_nCLK;
assign w46 = port_b;
assign w47 = port_a;
assign w48 = port_c;
assign port_tmp2 = w_tmp2;
// Instances
div_umc_notsuper g1 (.a(w40), .x(w39) );
div_umc_nor g2 (.a(w_tmp2), .b(w46), .x(w34) );
div_umc_nor g3 (.a(w31), .b(w29), .x(w30) );
div_umc_nor g4 (.a(w48), .b(w30), .x(w29) );
div_umc_nor g5 (.a(w28), .b(w27), .x(w35) );
div_umc_nor g6 (.a(w36), .b(w35), .x(w1) );
div_umc_nor g7 (.b(w16), .a(cck), .x(ck) );
div_umc_nor g8 (.a(w15), .b(ck), .x(cck) );
div_umc_nor g9 (.b(w_tmp2), .a(w12), .x(tmp1) );
div_umc_nor g10 (.b(fb), .a(w9), .x(w8) );
div_umc_nor g11 (.a(w6), .b(fb), .x(w5) );
div_umc_nor g12 (.a(w44), .b(w1), .x(w3) );
div_umc_nor g13 (.a(w43), .b(tmp1), .x(w17) );
div_umc_nor g14 (.b(w42), .a(tmp1), .x(w18) );
div_umc_nor g15 (.b(w41), .a(tmp1), .x(w20) );
div_umc_dlatch g16 (.d(w26), .en(ck), .nq(w40) );
div_umc_dlatch g17 (.d(w52), .en(cck), .nq(w26) );
div_umc_dlatch g18 (.d(w_tmp2), .en(ck), .nq(w52) );
div_umc_dlatch g19 (.d(w25), .en(cck), .nq(fb) );
div_umc_dlatch g20 (.d(w24), .en(ck), .nq(w25) );
div_umc_dlatch g21 (.d(w23), .en(cck), .nq(w24) );
div_umc_dlatch g22 (.d(w22), .en(ck), .nq(w23) );
div_umc_dlatch g23 (.d(w21), .en(cck), .nq(w22) );
div_umc_dlatch g24 (.d(w20), .en(ck), .nq(w21) );
div_umc_dlatch g25 (.d(w19), .en(cck), .q(w41) );
div_umc_dlatch g26 (.d(w18), .en(ck), .nq(w19) );
div_umc_dlatch g27 (.d(w51), .en(cck), .q(w42) );
div_umc_dlatch g28 (.d(w17), .en(ck), .nq(w51) );
div_umc_dlatch g29 (.d(w2), .en(cck), .q(w43) );
div_umc_dlatch g30 (.d(w3), .en(ck), .nq(w2) );
div_umc_dlatch g31 (.d(w4), .en(cck), .q(w44) );
div_umc_dlatch g32 (.d(w5), .en(ck), .nq(w4) );
div_umc_dlatch g33 (.d(w7), .en(cck), .q(w6) );
div_umc_dlatch g34 (.d(w8), .en(ck), .nq(w7) );
div_umc_dlatch g35 (.d(w10), .en(cck), .q(w9) );
div_umc_dlatch g36 (.d(w11), .en(ck), .nq(w10) );
div_umc_not g37 (.a(fb), .x(w12) );
div_umc_not g38 (.a(fb), .x(w11) );
div_umc_not g39 (.a(w39), .x(w33) );
div_umc_not g40 (.a(w29), .x(w28) );
div_umc_not g41 (.a(fb), .x(w36) );
div_umc_not g42 (.a(w37), .x(w_tmp2) );
div_umc_not g43 (.a(w38), .x(w15) );
div_umc_not g44 (.a(w15), .x(w16) );
div_umc_mux g45 (.sel(w_tmp2), .a0(w3), .a1(w8), .x(w37) );
div_umc_not g46 (.a(w_tmp2), .x(w27) );
div_umc_dlatch g47 (.d(w32), .en(w33), .nq(w31) );
div_umc_dlatch g48 (.d(w47), .en(w39), .nq(w32) );
endmodule // div_umc |
module div_umc_notsuper ( a, x);
input wire a;
output wire x;
not (x, a);
endmodule // div_umc_notsuper |
module div_umc_nor ( a, b, x);
input wire a;
input wire b;
output wire x;
nor (x, a, b);
endmodule // div_umc_nor |
module div_umc_dlatch ( d, en, nq, q);
input wire d;
input wire en;
output wire nq;
output wire q;
reg dout;
always @(d or en) begin
if (en == 1'b1 && (d == 1'b0 || d == 1'b1))
dout <= d; // Use non-blocking
end
assign q = dout;
assign nq = ~dout;
initial dout <= 1'b0;
endmodule // div_umc_dlatch |
module div_umc_not ( a, x);
input wire a;
output wire x;
not (x, a);
endmodule // div_umc_not |
module div_umc_mux ( sel, a0, a1, x);
input wire sel;
input wire a0;
input wire a1;
output wire x;
assign x = sel ? a1 : a0;
endmodule // div_umc_mux |
module NES (CLK, CIC_CLK, AUDIO_Out, VIDEO_Out);
input CLK; // 21.477272 MHz
input CIC_CLK; // 4 MHz
output AUDIO_Out;
output VIDEO_Out;
wire vdd;
wire gnd;
assign vdd = 1'b1;
assign gnd = 1'b0;
// Clocks
wire PPU_CLK;
wire SYSTEM_CLK;
wire CPU_CLK;
assign PPU_CLK = CLK;
assign SYSTEM_CLK = CLK;
assign CPU_CLK = CLK;
// Buses
wire [7:0] CPU_D;
wire [15:0] CPU_A;
wire [7:0] PPU_D;
wire [13:0] PPU_A;
wire CPU_RnW;
wire [2:0] RS; // PPU register index
// PPU <-> VRAM
wire PPU_nRD;
wire PPU_nWR;
wire PPU_ALE;
// I/O
wire nOE1; // aka nRDP0 from cpu
wire nOE2; // aka nRDP1 from cpu
wire [2:0] OUT; // from cpu
wire [4:0] P1_D; // $4016 bus
wire [4:0] P2_D; // $4017 bus
wire [9:0] EXP;
// Misc
wire nRST;
wire nIRQ;
wire nNMI;
wire M2; // from cpu
wire AUX1;
wire AUX2;
wire PPU_VIDEO;
wire EXP_VIDEO;
wire EXPAUDIO_ToMB;
wire EXPAUDIO_FromMB;
wire WRAM_nCE;
wire PPU_nCE; // 0: Enable CPU/PPU I/F
wire nROMSEL;
wire VRAM_A10;
wire VRAM_nCE;
wire P4_IO_Unused;
wire P5_IO_Unused;
wire [3:0] nY1;
wire [3:0] nY2;
// CIC
wire CIC_TO_MB; // Cart CIC -> MB CIC
wire CIC_TO_CART; // MB CIC -> Cart CIC
wire CIC_RST; // Cart CIC -> MB CIC
// Instantiate
CPU cpu (
.CLK(CPU_CLK),
.M2(M2),
.TST(gnd),
.nRST(nRST),
.nIRQ(nIRQ),
.nNMI(nNMI),
.D(CPU_D),
.A(CPU_A),
.RnW(CPU_RnW),
.nOE1(nOE1),
.nOE2(nOE2),
.OUT(OUT),
.AUX1(AUX1),
.AUX2(AUX2) );
PPU ppu (
.CLK(PPU_CLK),
.nRST(nRST),
.nINT(nNMI),
.nDBE(PPU_nCE),
.CPU_RnW(CPU_RnW),
.CPU_D(CPU_D),
.RS(CPU_A[2:0]),
.EXT({gnd,gnd,gnd,gnd}),
.nRD(PPU_nRD),
.nWR(PPU_nWR),
.AD(PPU_D),
.A(PPU_A[13:8]),
.ALE(PPU_ALE),
.VIDEO(PPU_VIDEO) );
CIC cic (
.CLK_IN(CIC_CLK),
.DATA_OUT(CIC_TO_CART),
.DATA_IN(CIC_TO_MB),
.SEED(vdd),
.LOCK_KEY(vdd),
.RST(vdd),
.CIC_RST(CIC_RST),
.nHOST_RST(nRST) );
RAM WRAM (
.A(CPU_A[10:0]),
.D(CPU_D),
.nCS(WRAM_nCE),
.nWE(CPU_RnW),
.nOE(gnd) );
RAM VRAM (
.A({VRAM_A10,PPU_A[9:0]}),
.D(PPU_D),
.nCS(VRAM_nCE),
.nWE(PPU_nWR),
.nOE(PPU_nRD) );
LS373 PPU_AddrLatch (
.nOE(gnd),
.Q(PPU_A[7:0]),
.D(PPU_D),
.LE(PPU_ALE) );
LS139 DMX (
.First_nE(gnd),
.First_A({CPU_A[15],M2}),
.First_nY(nY1),
.Second_nE(nY1[1]),
.Second_A({CPU_A[14],CPU_A[13]}),
.Second_nY(nY2) );
assign nROMSEL = nY1[3];
assign WRAM_nCE = nY2[0];
assign PPU_nCE = nY2[1];
CtrlPort P4 (
.CUP(nOE1),
.OUT0(OUT[0]),
.D0(P1_D[0]),
.D3(P1_D[3]),
.D4(P1_D[4]) );
CtrlPort P5 (
.CUP(nOE2),
.OUT0(OUT[0]),
.D0(P2_D[0]),
.D3(P2_D[3]),
.D4(P2_D[4]) );
LS368 P4_IO (
.nG1(nOE1),
.nG2(nOE1),
.A({P1_D[4],P1_D[3],P1_D[2],gnd,P1_D[1],P1_D[0]}),
.nY({CPU_D[4],CPU_D[3],CPU_D[2],P4_IO_Unused,CPU_D[1],CPU_D[0]}) );
LS368 P5_IO (
.nG1(nOE2),
.nG2(nOE2),
.A({P2_D[4],P2_D[3],P2_D[2],gnd,P2_D[1],P2_D[0]}),
.nY({CPU_D[4],CPU_D[3],CPU_D[2],P5_IO_Unused,CPU_D[1],CPU_D[0]}) );
CartPort P1 (
.SYSTEM_CLK(SYSTEM_CLK),
.M2(M2),
.CIC_TO_MB(CIC_TO_MB),
.CIC_TO_CART(CIC_TO_CART),
.CIC_CLK(CIC_CLK),
.CIC_RST(CIC_RST),
.CPU_D(CPU_D),
.CPU_A(CPU_A[14:0]), // not using A15
.CPU_RnW(CPU_RnW),
.nROMSEL(nROMSEL),
.EXP(EXP),
.nIRQ(nIRQ),
.PPU_D(PPU_D),
.PPU_A(PPU_A),
.PPU_nA13(~PPU_A[13]),
.VRAM_A10(VRAM_A10),
.VRAM_nCE(VRAM_nCE),
.PPU_nRD(PPU_nRD),
.PPU_nWR(PPU_nWR) );
ExpPort P2 (
.CIC_CLK(CIC_CLK),
.AUDIO_IN(EXPAUDIO_FromMB),
.AUDIO_OUT(EXPAUDIO_ToMB),
.VIDEO(EXP_VIDEO),
.nNMI(nNMI),
.nIRQ(nIRQ),
.A15(CPU_A[15]),
.EXP(EXP),
.P1_D(P1_D),
.P2_D(P2_D),
.nOE1(nOE1),
.nOE2(nOE2),
.OUT(OUT),
.D(CPU_D) );
AudioMix aud_out (.AUX1(AUX1), .AUX2(AUX2), .FromEXP(EXPAUDIO_ToMB), .ToExp(EXPAUDIO_FromMB), .AUDIO_Out(AUDIO_Out) );
VideoMix vid_out (.FromPPU(PPU_VIDEO), .FromEXP(EXP_VIDEO), .VIDEO_Out(VIDEO_Out) );
// Pullups
pullup p1_pullups [4:0] (P1_D);
pullup p2_pullups [4:0] (P2_D);
pullup (nIRQ);
pullup (nNMI);
pullup (nOE1);
pullup (nOE2);
pullup (PPU_A[13]);
pullup (OUT[0]);
endmodule // NES |
module CPU (CLK, M2, TST, nRST, nIRQ, nNMI, D, A, RnW, nOE1, nOE2, OUT, AUX1, AUX2);
input CLK;
output M2;
input TST;
input nRST;
input nIRQ;
input nNMI;
inout [7:0] D;
output [15:0] A;
output RnW;
output nOE1;
output nOE2;
output [2:0] OUT;
output AUX1;
output AUX2;
endmodule // CPU |
module PPU (CLK, nRST, nINT, nDBE, CPU_RnW, CPU_D, RS, EXT, nRD, nWR, AD, A, ALE, VIDEO);
input CLK;
input nRST;
output nINT;
inout [3:0] EXT;
// CPU I/F
input nDBE;
input CPU_RnW;
inout [7:0] CPU_D;
input [2:0] RS;
// VRAM I/F
output nRD;
output nWR;
inout [7:0] AD;
output [13:8] A;
output ALE;
output VIDEO;
endmodule // PPU |
module CIC (CLK_IN, DATA_OUT, DATA_IN, SEED, LOCK_KEY, RST, CIC_RST, nHOST_RST);
input CLK_IN;
output DATA_OUT;
input DATA_IN;
input SEED;
input LOCK_KEY;
input RST;
input CIC_RST;
output nHOST_RST;
endmodule // CIC |
module CartPort (SYSTEM_CLK, M2, CIC_TO_MB, CIC_TO_CART, CIC_CLK, CIC_RST,
CPU_D, CPU_A, CPU_RnW, nROMSEL, EXP, nIRQ,
PPU_D, PPU_A, PPU_nA13, VRAM_A10, VRAM_nCE, PPU_nRD, PPU_nWR);
input SYSTEM_CLK; // NES Board specific ⚠️
input M2;
output CIC_TO_MB; // NES Board specific ⚠️
input CIC_TO_CART; // NES Board specific ⚠️
input CIC_CLK; // NES Board specific ⚠️
output CIC_RST; // NES Board specific ⚠️
// CPU Part
inout [7:0] CPU_D;
input [14:0] CPU_A; // not using A15
input CPU_RnW;
input nROMSEL;
input [9:0] EXP; // NES Board specific ⚠️
output nIRQ;
// PPU Part
// If you've been doing NES/Famicom for a long time, you've long known that the cartridge controls the VRAM access for the PPU. For everyone else, welcome to the world of Alien.
inout [7:0] PPU_D;
input [13:0] PPU_A;
input PPU_nA13;
output VRAM_A10;
output VRAM_nCE;
input PPU_nRD;
input PPU_nWR;
endmodule // CartPort |
module CtrlPort (CUP, OUT0, D0, D3, D4);
input CUP;
input OUT0;
inout D0;
inout D3;
inout D4;
endmodule // CtrlPort |
module ExpPort (CIC_CLK, AUDIO_IN, AUDIO_OUT, VIDEO, nNMI, nIRQ, A15, EXP, P1_D, P2_D, nOE1, nOE2, OUT, D);
input CIC_CLK;
input AUDIO_IN;
output AUDIO_OUT;
output VIDEO;
output nNMI;
output nIRQ;
input A15;
inout [9:0] EXP;
output [4:0] P1_D; // $4016
output [4:0] P2_D; // $4017
input nOE1;
input nOE2;
input [2:0] OUT;
inout [7:0] D;
endmodule // ExpPort |
module RAM (A, D, nCS, nWE, nOE);
input [10:0] A;
input [7:0] D;
input nCS;
input nWE;
input nOE;
endmodule // RAM |
module LS368 (nG1, nG2, A, nY);
input nG1; // 0: Tristates 5,6
input nG2; // 0: Tristates 1,2,3,4
input [5:0] A; // A1-A6 actually
output [5:0] nY; // nY1-nY6 actually
endmodule // LS368 |
module LS139 (First_nE, First_A, First_nY, Second_nE, Second_A, Second_nY);
input First_nE;
input [1:0] First_A;
output [3:0] First_nY;
input Second_nE;
input [1:0] Second_A;
output [3:0] Second_nY;
endmodule // LS139 |
module LS373 (nOE, Q, D, LE);
input nOE; // 3-state output enable input (active LOW)
output [7:0] Q; // 3-state latch outputs
input [7:0] D; // data inputs
input LE; // latch enable input (active HIGH)
endmodule // LS373 |
module AudioMix (AUX1, AUX2, FromEXP, ToExp, AUDIO_Out);
input AUX1;
input AUX2;
input FromEXP;
output ToExp;
output AUDIO_Out;
// There's some kind of magic going on, we don't care.
endmodule // AudioMix |
module VideoMix (FromPPU, FromEXP, VIDEO_Out);
input FromPPU;
input FromEXP;
output VIDEO_Out;
// There's some kind of magic going on, we don't care.
endmodule // VideoMix |
module PixelClock (
n_CLK, CLK, RES,
n_PCLK, PCLK);
input n_CLK;
input CLK; // NTSC: 21477272 Hz (~0,046 µs), PAL: 26601712 Hz (~0,037 µs)
input RES;
output n_PCLK;
output PCLK; // NTSC: 5369318 Hz (~0,186 µs), PAL: 5320342.4 Hz (~0,187 µs)
// wires
wire latch1_in;
wire latch2_in;
wire latch1_out;
wire latch2_out;
wire latch3_out;
wire latch4_out;
wire latch5_out;
wire latch6_out;
wire pclk;
wire pclk_out;
wire npclk_out;
`ifdef RP2C02
// The PCLK is obtained by slowing down (dividing) the input clock signal CLK (21.48 MHz) by a factor of 4.
// For this purpose, a divider on static latches is used:
nor (latch1_in, RES, latch4_out);
dlatch latch1 (.d(latch1_in), .en(n_CLK), .nq(latch1_out) );
dlatch latch2 (.d(latch1_out), .en(CLK), .nq(latch2_out) );
dlatch latch3 (.d(latch2_out), .en(n_CLK), .nq(latch3_out) );
dlatch latch4 (.d(latch3_out), .en(CLK), .nq(latch4_out) );
assign pclk = latch4_out;
`elsif RP2C07
nor (latch2_in, latch1_out, RES);
dlatch latch1 (.d(latch1_in), .en(n_CLK), .q(latch1_out));
dlatch latch2 (.d(latch2_in), .en(CLK), .nq(latch2_out));
dlatch latch3 (.d(latch2_out), .en(n_CLK), .nq(latch3_out));
dlatch latch4 (.d(latch3_out), .en(CLK), .nq(latch4_out));
dlatch latch5 (.d(latch4_out), .en(n_CLK), .nq(latch5_out));
dlatch latch6 (.d(latch5_out), .en(CLK), .nq(latch6_out));
nor (pclk, latch6_out, ~latch5_out);
nor (latch1_in, latch6_out, latch4_out);
`else
`endif
// Just below the divider is the single phase splitter.
// This is a canonical circuit based on a single FF that makes two phases (/PCLK + PCLK) from a single phase (PCLK).
rsff PCLK_FF (.r(pclk), .s(~pclk), .q(pclk_out), .nq(npclk_out) );
assign n_PCLK = ~pclk_out;
assign PCLK = ~npclk_out;
endmodule // PixelClock |
module OAMEval(
n_PCLK, PCLK,
BLNK, I_OAM2, n_VIS, PAR_O, n_EVAL, RESCL, H0_DD, H0_D, n_H2_D, OFETCH, n_FNT, S_EV,
n_W3, n_DBE,
DB5,
n_OAM, OAM8, OAMCTR2, SPR_OV, OV, PD_FIFO, n_SPR0_EV);
input n_PCLK;
input PCLK;
input BLNK;
input I_OAM2;
input n_VIS;
input PAR_O;
input n_EVAL;
input RESCL;
input H0_DD;
input H0_D;
input n_H2_D;
input OFETCH;
input n_FNT;
input S_EV;
input n_W3;
input n_DBE;
inout DB5;
output [7:0] n_OAM;
output OAM8;
output OAMCTR2;
output SPR_OV;
output [7:0] OV;
output PD_FIFO;
output n_SPR0_EV;
endmodule // OAMEval |
module PataddrGen(
n_PCLK,
H0_DD, n_FNT, BGSEL, OBSEL, O8_16, PAR_O, n_SH2, n_H1D, OB, PD, OV, n_FVO,
PAddr_out);
input n_PCLK;
input H0_DD;
input n_FNT;
input BGSEL;
input OBSEL;
input O8_16;
input PAR_O;
input n_SH2;
input n_H1D;
input [7:0] OB;
input [7:0] PD;
input [3:0] OV;
input [2:0] n_FVO;
output [13:0] PAddr_out;
endmodule // PataddrGen |
module PPU_FSM (
n_PCLK, PCLK,
H_out, V_out, HPLA_out, VPLA_out, RES, VBL_EN, n_R2, n_DBE, n_OBCLIP, n_BGCLIP, BLACK,
H0_DD, H0_D, H1_DD, nH1_D, H2_DD, nH2_D, H3_DD, H4_DD, H5_DD,
S_EV, CLIP_O, CLIP_B, Z_HPOS, n_EVAL, E_EV, I_OAM2, PAR_O, n_VIS, n_FNT, F_TB, F_TA, n_FO, F_AT, SC_CNT, BURST, SYNC,
n_PICTURE, RESCL, VB, BLNK,
Int, DB7, V_IN, HC, VC);
input n_PCLK;
input PCLK;
input [8:0] H_out; // HCounter bits 0-5, for outputting to the outside with a delay
input [8:0] V_out; // VCounter bits
input [23:0] HPLA_out; // Outputs from H decoder
input [9:0] VPLA_out; // Outputs from V decoder
input RES; // Global reset signal. Used in EVEN/ODD logic.
input VBL_EN; // Control Regs ($2000[7]); Used in the VBlank interrupt handling circuit.
input n_R2; // 0: Register $2002 read operation. Used in the VBlank interrupt handling circuit.
input n_DBE; // 0: Enable the CPU interface. Used in the VBlank interrupt handling circuit.
input n_OBCLIP; // Control Regs ($2001[2]); To generate the CLIP_O control signal
input n_BGCLIP; // Control Regs ($2001[1]); To generate the CLIP_B control signal
input BLACK; // Active when PPU rendering is disabled (see $2001[3] and $2001[4])
output H0_DD;
output H0_D; // H0 signal delayed by one DLatch
output H1_DD;
output nH1_D; // H1 signal delayed by one DLatch (in inverse logic)
output H2_DD;
output nH2_D; // H2 signal delayed by one DLatch (in inverse logic)
output H3_DD;
output H4_DD;
output H5_DD; // H0-H5 signals delayed by two DLatch
output S_EV; // "Start Sprite Evaluation"
output CLIP_O; // "Clip Objects". 1: Do not show the left 8 screen pixels for sprites. Used to get the CLPO signal that goes into the OAM FIFO.
output CLIP_B; // "Clip Background". 1: Do not show the left 8 pixels of the screen for the background. Used to get the /CLPB signal that goes into the Data Reader.
output Z_HPOS; // "Clear HPos". Clear the H counters in the sprite FIFO and start the FIFO
output n_EVAL; // 0: "Sprite Evaluation in Progress"
output E_EV; // "End Sprite Evaluation"
output I_OAM2; // "Init OAM2". Initialize an extra OAM
output PAR_O; // "PAR for Object". Selecting a tile for an object (sprite)
output n_VIS; // 0: "Not Visible". The invisible part of the signal (used by sprite logic)
output n_FNT; // 0: "Fetch Name Table"
output F_TB; // "Fetch Tile B"
output F_TA; // "Fetch Tile A"
output n_FO; // 0: "Fetch Output Enable"
output F_AT; // "Fetch Attribute Table"
output SC_CNT; // "Scroll Counters Control". Update the scrolling registers.
output BURST; // Color Burst
output SYNC; // Horizontal sync pulse
output n_PICTURE; // 0: Visible part of the scan-lines
output RESCL; // "Reset FF Clear" / "VBlank Clear". VBlank period end event.
output VB; // Active when the invisible part of the video signal is output (used only in H Decoder)
output BLNK; // Active when PPU rendering is disabled (by BLACK signal) or during VBlank
output Int; // "Interrupt". PPU Interrupt
inout DB7;
output V_IN; // "VCounter In". Increment the VCounter
output HC; // "HCounter Clear"
output VC; // "VCounter Clear"
// Wires
wire BPORCH; // "Back Porch"
wire nVSET; // 0: "VBlank Set". VBlank period start event.
wire EvenOddOut; // Intermediate signal for the HCounter control circuit / 2C07: EvenOddOut signal goes into sprite logic instead of controlling the H/V counters
wire n_HB; // 0: "HBlank"
wire VSYNC; // Vertical sync pulse
// Instances
DelayedH delayed_h (
.PCLK(PCLK),
.n_PCLK(n_PCLK),
.H_out(H_out),
.H0_DD(H0_DD),
.H0_D(H0_D),
.H1_DD(H1_DD),
.nH1_D(nH1_D),
.H2_DD(H2_DD),
.nH2_D(nH2_D),
.H3_DD(H3_DD),
.H4_DD(H4_DD),
.H5_DD(H5_DD) );
`ifdef RP2C02
EvenOdd even_odd (
.V8(V_out[8]),
.RES(RES),
.nHPLA_5(~HPLA_out[5]),
.RESCL(RESCL),
.EvenOddOut(EvenOddOut) );
`elsif RP2C07
EvenOdd_2C07 even_odd_pal (
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.BLNK(BLNK),
.H0_D(H0_D),
.VPLA_8(VPLA_out[8]),
.VPLA_9(VPLA_out[9]),
.EvenOddOut(EvenOddOut) );
`else
`endif
VBlankInt vbl (
.PCLK(PCLK),
.n_PCLK(n_PCLK),
.nVSET(nVSET),
.VCLR(RESCL),
.VBL_EN(VBL_EN),
.n_R2(n_R2),
.n_DBE(n_DBE),
.INT(Int),
.DB7Out(DB7) );
`ifdef RP2C02
HVCounterControl hv_ctrl (
.n_PCLK(n_PCLK),
.HPLA_23(HPLA_out[23]),
.EvenOddOut(EvenOddOut),
.VPLA_2(VPLA_out[2]),
.V_IN(V_IN),
.HC(HC),
.VC(VC) );
`elsif RP2C07
HVCounterControl_2C07 hv_ctrl_pal (
.n_PCLK(n_PCLK),
.HPLA_23(HPLA_out[23]),
.VPLA_8(VPLA_out[8]),
.V_IN(V_IN),
.HC(HC),
.VC(VC) );
`else
`endif
HPosLogic hpos (
.PCLK(PCLK),
.n_PCLK(n_PCLK),
.HPLA_out(HPLA_out),
.n_OBCLIP(n_OBCLIP),
.n_BGCLIP(n_BGCLIP),
.VSYNC(VSYNC),
.BLACK(BLACK),
.S_EV(S_EV),
.CLIP_O(CLIP_O),
.CLIP_B(CLIP_B),
.Z_HPOS(Z_HPOS),
.n_EVAL(n_EVAL),
.E_EV(E_EV),
.I_OAM2(I_OAM2),
.PAR_O(PAR_O),
.n_VIS(n_VIS),
.n_FNT(n_FNT),
.F_TB(F_TB),
.F_TA(F_TA),
.n_FO(n_FO),
.F_AT(F_AT),
.BPORCH(BPORCH),
.SC_CNT(SC_CNT),
.n_HB(n_HB),
.BURST(BURST),
.SYNC(SYNC) );
VPosLogic vpos (
.PCLK(PCLK),
.n_PCLK(n_PCLK),
.n_HB(n_HB),
.BPORCH(BPORCH),
.BLACK(BLACK),
.VPLA_out(VPLA_out),
.n_PICTURE(n_PICTURE),
.RESCL(RESCL),
.VSYNC(VSYNC),
.nVSET(nVSET),
.VB(VB),
.BLNK(BLNK) );
endmodule // PPU_FSM |
module DelayedH (PCLK, n_PCLK, H_out, H0_DD, H0_D, H1_DD, nH1_D, H2_DD, nH2_D, H3_DD, H4_DD, H5_DD);
input PCLK;
input n_PCLK;
input [8:0] H_out;
output H0_DD;
output H0_D;
output H1_DD;
output nH1_D;
output H2_DD;
output nH2_D;
output H3_DD;
output H4_DD;
output H5_DD;
// Wires
wire h0_latch1_nq;
wire h3_latch1_nq;
wire h4_latch1_nq;
wire h5_latch1_nq;
// Instances
dlatch h0_latch1 (.d(H_out[0]), .en(n_PCLK), .nq(h0_latch1_nq));
dlatch h0_latch2 (.d(h0_latch1_nq), .en(PCLK), .nq(H0_DD));
dlatch h1_latch1 (.d(H_out[1]), .en(n_PCLK), .nq(nH1_D));
dlatch h1_latch2 (.d(nH1_D), .en(PCLK), .nq(H1_DD));
dlatch h2_latch1 (.d(H_out[2]), .en(n_PCLK), .nq(nH2_D));
dlatch h2_latch2 (.d(nH2_D), .en(PCLK), .nq(H2_DD));
dlatch h3_latch1 (.d(H_out[3]), .en(n_PCLK), .nq(h3_latch1_nq));
dlatch h3_latch2 (.d(h3_latch1_nq), .en(PCLK), .nq(H3_DD));
dlatch h4_latch1 (.d(H_out[4]), .en(n_PCLK), .nq(h4_latch1_nq));
dlatch h4_latch2 (.d(h4_latch1_nq), .en(PCLK), .nq(H4_DD));
dlatch h5_latch1 (.d(H_out[5]), .en(n_PCLK), .nq(h5_latch1_nq));
dlatch h5_latch2 (.d(h5_latch1_nq), .en(PCLK), .nq(H5_DD));
endmodule // DelayedH |
module EvenOdd (V8, RES, nHPLA_5, RESCL, EvenOddOut);
input V8;
input RES;
input nHPLA_5;
input RESCL;
output EvenOddOut;
wire q1;
wire q2;
wire nq2;
sdff FF_1 (.d(nq2), .phi_keep(V8), .q(q1));
sdffr FF_2 (.d(q1), .res(), .phi_keep(~V8), .q(q2), .nq(nq2));
nor (EvenOddOut, q2, nHPLA_5, ~RESCL);
endmodule // EvenOdd |
module EvenOdd_2C07 (n_PCLK, PCLK, BLNK, H0_D, VPLA_8, VPLA_9, EvenOddOut);
input n_PCLK;
input PCLK;
input BLNK;
input H0_D;
input VPLA_8;
input VPLA_9;
output EvenOddOut; // Don't mind the name, it's just historically that way. In fact, it's more like `Sprite_Workaround`.
wire latch1_q;
wire latch2_q;
wire latch3_in;
wire latch3_nq;
wire tmp;
dlatch latch1 (.d(VPLA_9), .en(n_PCLK), .q(latch1_q));
dlatch latch2 (.d(VPLA_8), .en(n_PCLK), .q(latch2_q));
dlatch latch3 (.d(latch3_in), .en(PCLK), .nq(latch3_nq));
rsff FF_1 (.r(latch2_q), .s(latch1_q), .nq());
nand (tmp, BLNK, latch3_nq);
nor (EvenOddOut, ~H0_D, tmp, n_PCLK);
endmodule // EvenOdd_2C07 |
module VBlankInt (PCLK, n_PCLK, nVSET, VCLR, VBL_EN, n_R2, n_DBE, INT, DB7Out);
input PCLK;
input n_PCLK;
input nVSET;
input VCLR;
input VBL_EN;
input n_R2;
input n_DBE;
output INT;
inout DB7Out;
wire R2_EN;
wire vset_latch1_nq;
wire vset_latch2_q;
wire db_latch_nq;
wire int_ff_q;
dlatch vset_latch1 (.d(nVSET), .en(PCLK), .nq(vset_latch1_nq));
dlatch vset_latch2 (.d(vset_latch1_nq), .en(n_PCLK), .q(vset_latch2));
dlatch db_latch (.d(~int_ff_q), .en(~R2_EN), .nq(db_latch_nq));
rsff_2_3 int_ff (.res1(VCLR), .res2(R2_EN), .s(~(n_PCLK | nVSET | vset_latch2_q)), .q(int_ff_q));
nor (R2_EN, n_R2, n_DBE);
nor (INT, ~VBL_EN, ~int_ff_q);
assign DB7Out = R2_EN ? db_latch_nq : 1'bz;
endmodule // VBlankInt |
module HVCounterControl (n_PCLK, HPLA_23, EvenOddOut, VPLA_2, V_IN, HC, VC);
input n_PCLK;
input HPLA_23;
input EvenOddOut;
input VPLA_2;
output V_IN;
output HC;
output VC;
wire ctrl_latch2_nq;
dlatch ctrl_latch1 (.d(~(HPLA_23 | EvenOddOut)), .en(n_PCLK), .nq(HC));
dlatch ctrl_latch2 (.d(VPLA_2), .en(n_PCLK), .nq(ctrl_latch2_nq));
assign V_IN = HPLA_23;
nor (VC, ~HC, ctrl_latch2_nq);
endmodule // HVCounterControl |
module HVCounterControl_2C07 (n_PCLK, HPLA_23, VPLA_8, V_IN, HC, VC);
input n_PCLK;
input HPLA_23;
input VPLA_8;
output V_IN;
output HC;
output VC;
wire ctrl_latch2_nq;
dlatch ctrl_latch1 (.d(~HPLA_23), .en(n_PCLK), .nq(HC));
dlatch ctrl_latch2 (.d(VPLA_8), .en(n_PCLK), .nq(ctrl_latch2_nq));
assign V_IN = HPLA_23;
nor (VC, ~HC, ctrl_latch2_nq);
endmodule // HVCounterControl_2C07 |
module HPosLogic (PCLK, n_PCLK, HPLA_out, n_OBCLIP, n_BGCLIP, VSYNC, BLACK,
S_EV, CLIP_O, CLIP_B, Z_HPOS, n_EVAL, E_EV, I_OAM2, PAR_O, n_VIS, n_FNT, F_TB, F_TA, n_FO, F_AT, BPORCH, SC_CNT, n_HB, BURST, SYNC);
input PCLK;
input n_PCLK;
input [23:0] HPLA_out;
input n_OBCLIP;
input n_BGCLIP;
input VSYNC;
input BLACK;
output S_EV;
output CLIP_O;
output CLIP_B;
output Z_HPOS;
output n_EVAL;
output E_EV;
output I_OAM2;
output PAR_O;
output n_VIS;
output n_FNT;
output F_TB;
output F_TA;
output n_FO;
output F_AT;
output BPORCH;
output SC_CNT;
output n_HB;
output BURST;
output SYNC;
// Wires
wire fp_latch1_q;
wire fp_latch2_q;
wire sev_latch1_nq;
wire sev_latch2_nq;
wire clpo_latch1_q;
wire clpo_latch2_q;
wire clpb_latch1_nq;
wire clpb_latch2_q;
wire hpos_latch1_q;
wire hpos_latch1_nq;
wire hpos_latch2_nq;
wire eval_latch1_q;
wire eval_latch2_nq;
wire eev_latch1_q;
wire eev_latch1_nq;
wire eev_latch2_nq;
wire ioam_latch1_nq;
wire ioam_latch2_nq;
wire paro_latch1_nq;
wire paro_latch2_nq;
wire nvis_latch1_nq;
wire nvis_latch2_nq;
wire fnt_latch1_nq;
wire fnt_latch2_nq;
wire ftb_latch1_nq;
wire ftb_latch2_q;
wire fta_latch1_nq;
wire fta_latch2_q;
wire fo_latch1_q;
wire fo_latch2_q;
wire fo_latch3_q;
wire fo_latch3_nq;
wire fat_latch1_nq;
wire bp_latch1_q;
wire bp_latch2_q;
wire hb_latch1_q;
wire hb_latch2_q;
wire cb_latch1_q;
wire cb_latch2_q;
wire sync_latch1_q;
wire sync_latch2_q;
wire fporch_ff_nq;
wire bporch_ff_q;
wire hblank_ff_q;
wire hblank_ff_nq;
wire burst_ff_nq;
wire clp;
wire fo3;
// Instances
dlatch fp_latch1 (.d(HPLA_out[0]), .en(n_PCLK), .q(fp_latch1_q));
dlatch fp_latch2 (.d(HPLA_out[1]), .en(n_PCLK), .q(fp_latch2_q));
dlatch sev_latch1 (.d(HPLA_out[2]), .en(n_PCLK), .nq(sev_latch1_nq));
dlatch sev_latch2 (.d(sev_latch1_nq), .en(PCLK), .nq(sev_latch2_nq));
dlatch clpo_latch1 (.d(HPLA_out[3]), .en(n_PCLK), .q(clpo_latch1_q));
dlatch clpo_latch2 (.d(clp), .en(PCLK), .q(clpo_latch2_q));
dlatch clpb_latch1 (.d(HPLA_out[4]), .en(n_PCLK), .nq(clpb_latch1_nq));
dlatch clpb_latch2 (.d(clp), .en(PCLK), .q(clpb_latch2_q));
dlatch hpos_latch1 (.d(HPLA_out[5]), .en(n_PCLK), .q(hpos_latch1_q), .nq(hpos_latch1_nq));
dlatch hpos_latch2 (.d(hpos_latch1_nq), .en(PCLK), .nq(hpos_latch2_nq));
dlatch eval_latch1 (.d(HPLA_out[6]), .en(n_PCLK), .q(eval_latch1_q));
dlatch eval_latch2 (.d(~(hpos_latch1_q | eval_latch1_q | eev_latch1_q)), .en(PCLK), .nq(eval_latch2_nq));
dlatch eev_latch1 (.d(HPLA_out[7]), .en(n_PCLK), .q(eev_latch1_q), .nq(eev_latch1_nq));
dlatch eev_latch2 (.d(eev_latch1_nq), .en(PCLK), .nq(eev_latch2_nq));
dlatch ioam_latch1 (.d(HPLA_out[8]), .en(n_PCLK), .nq(ioam_latch1_nq));
dlatch ioam_latch2 (.d(ioam_latch1_nq), .en(PCLK), .nq(ioam_latch2_nq));
dlatch paro_latch1 (.d(HPLA_out[9]), .en(n_PCLK), .nq(paro_latch1_nq));
dlatch paro_latch2 (.d(paro_latch1_nq), .en(PCLK), .nq(paro_latch2_nq));
dlatch nvis_latch1 (.d(HPLA_out[10]), .en(n_PCLK), .nq(nvis_latch1_nq));
dlatch nvis_latch2 (.d(nvis_latch1_nq), .en(PCLK), .nq(nvis_latch2_nq));
dlatch fnt_latch1 (.d(HPLA_out[11]), .en(n_PCLK), .nq(fnt_latch1_nq));
dlatch fnt_latch2 (.d(fnt_latch1_nq), .en(PCLK), .nq(fnt_latch2_nq));
dlatch ftb_latch1 (.d(HPLA_out[12]), .en(n_PCLK), .nq(ftb_latch1_nq));
dlatch ftb_latch2 (.d(ftb_latch1_nq), .en(PCLK), .q(ftb_latch2_q));
dlatch fta_latch1 (.d(HPLA_out[13]), .en(n_PCLK), .nq(fta_latch1_nq));
dlatch fta_latch2 (.d(fta_latch1_nq), .en(PCLK), .q(fta_latch2_q));
dlatch fo_latch1 (.d(HPLA_out[14]), .en(n_PCLK), .q(fo_latch1_q));
dlatch fo_latch2 (.d(HPLA_out[15]), .en(n_PCLK), .q(fo_latch2_q));
dlatch fo_latch3 (.d(fo3), .en(PCLK), .q(fo_latch3_q), .nq(fo_latch3_nq));
dlatch fat_latch1 (.d(HPLA_out[16]), .en(n_PCLK), .nq(fat_latch1_nq));
dlatch bp_latch1 (.d(HPLA_out[17]), .en(n_PCLK), .q(bp_latch1_q));
dlatch bp_latch2 (.d(HPLA_out[18]), .en(n_PCLK), .q(bp_latch2_q));
dlatch hb_latch1 (.d(HPLA_out[19]), .en(n_PCLK), .q(hb_latch1_q));
dlatch hb_latch2 (.d(HPLA_out[20]), .en(n_PCLK), .q(hb_latch2_q));
dlatch cb_latch1 (.d(HPLA_out[21]), .en(n_PCLK), .q(cb_latch1_q));
dlatch cb_latch2 (.d(HPLA_out[22]), .en(n_PCLK), .q(cb_latch2_q));
dlatch sync_latch1 (.d(burst_ff_nq), .en(PCLK), .q(sync_latch1_q));
dlatch sync_latch2 (.d(~fporch_ff_nq), .en(PCLK), .q(sync_latch2_q));
rsff fporch_ff (.r(fp_latch1_q), .s(fp_latch2_q), .nq(fporch_ff_nq));
rsff bporch_ff (.r(bp_latch2_q), .s(bp_latch1_q), .q(bporch_ff_q));
rsff hblank_ff (.r(hb_latch2_q), .s(hb_latch1_q), .q(hblank_ff_q), .nq(hblank_ff_nq));
rsff burst_ff (.r(cb_latch1_q), .s(cb_latch2_q), .nq(burst_ff_nq));
nor (clp, clpo_latch1_q, clpb_latch1_nq);
nor (fo3, fo_latch1_q, fo_latch2_q);
assign S_EV = sev_latch2_nq;
assign CLIP_O = ~(n_OBCLIP | clpo_latch2_q);
assign CLIP_B = ~(n_BGCLIP | clpb_latch2_q);
assign Z_HPOS = hpos_latch2_nq;
assign n_EVAL = ~eval_latch2_nq;
assign E_EV = eev_latch2_nq;
assign I_OAM2 = ioam_latch2_nq;
assign PAR_O = paro_latch2_nq;
assign n_VIS = ~nvis_latch2_nq;
assign n_FNT = ~fnt_latch2_nq;
assign F_TB = ~(ftb_latch2_q | fo_latch3_q);
assign F_TA = ~(fta_latch2_q | fo_latch3_q);
assign n_FO = fo_latch3_nq;
assign F_AT = ~(fo3 | fat_latch1_nq);
assign BPORCH = bporch_ff_q;
assign SC_CNT = ~(hblank_ff_nq | BLACK);
assign n_HB = hblank_ff_q;
assign BURST = ~(sync_latch1_q | SYNC);
assign SYNC = ~(sync_latch2_q | VSYNC);
endmodule // HPosLogic |
module VPosLogic (PCLK, n_PCLK, n_HB, BPORCH, BLACK, VPLA_out,
n_PICTURE, RESCL, VSYNC, nVSET, VB, BLNK);
input PCLK;
input n_PCLK;
input n_HB;
input BPORCH;
input BLACK;
input [9:0] VPLA_out;
output n_PICTURE;
output RESCL;
output VSYNC;
output nVSET;
output VB;
output BLNK;
// Wires
wire vsync_latch1_q;
wire pic_latch1_q;
wire pic_latch2_q;
wire vset_latch1_nq;
wire vb_latch1_q;
wire vb_latch2_q;
wire blnk_latch1_q;
wire vclr_latch1_nq;
wire vclr_latch2_nq;
wire vsync_ff_q;
wire picture_ff_q;
wire vb_ff_nq;
wire blnk_ff_q;
// Instances
dlatch vsync_latch1 (.d(~(n_HB | vsync_ff_q)), .en(PCLK), .q(vsync_latch1_q));
dlatch pic_latch1 (.d(picture_ff_q), .en(PCLK), .q(pic_latch1_q));
dlatch pic_latch2 (.d(BPORCH), .en(PCLK), .q(pic_latch2_q));
dlatch vset_latch1 (.d(VPLA_out[4]), .en(n_PCLK), .nq(vset_latch1_nq));
dlatch vb_latch1 (.d(VPLA_out[5]), .en(n_PCLK), .q(vb_latch1_q));
dlatch vb_latch2 (.d(VPLA_out[6]), .en(n_PCLK), .q(vb_latch2_q));
dlatch blnk_latch1 (.d(VPLA_out[7]), .en(n_PCLK), .q(blnk_latch1_q));
dlatch vclr_latch1 (.d(VPLA_out[8]), .en(n_PCLK), .nq(vclr_latch1_nq));
dlatch vclr_latch2 (.d(vclr_latch1_nq), .en(PCLK), .nq(vclr_latch2_nq));
rsff vsync_ff (.r(n_HB & VPLA_out[0]), .s(n_HB & VPLA_out[1]), .q(vsync_ff_q));
rsff picture_ff (.r(BPORCH & VPLA_out[2]), .s(BPORCH & VPLA_out[3]), .q(picture_ff_q));
rsff vb_ff (.r(vb_latch1_q), .s(vb_latch2_q), .nq(vb_ff_nq));
rsff blnk_ff (.r(blnk_latch1_q), .s(vb_latch2_q), .q(blnk_ff_q));
assign n_PICTURE = ~(~(pic_latch1_q | pic_latch2_q));
assign RESCL = vclr_latch2_nq;
assign VSYNC = vsync_latch1_q;
assign nVSET = vset_latch1_nq;
assign VB = ~vb_ff_nq;
assign BLNK = ~(~blnk_ff_q & ~BLACK);
endmodule // VPosLogic |
module OAMBlock(
n_PCLK, PCLK,
n_OAM, OAM8, BLNK, SPR_OV, OAMCTR2, H0_DD, n_VIS, I_OAM2, n_W4, n_R4, n_DBE,
CPU_DB,
OB_Out, OFETCH);
input n_PCLK;
input PCLK;
input [7:0] n_OAM;
input OAM8;
input BLNK;
input SPR_OV;
input OAMCTR2;
input H0_DD;
input n_VIS;
input I_OAM2;
input n_W4;
input n_R4;
input n_DBE;
inout [7:0] CPU_DB;
output [7:0] OB_Out;
output OFETCH;
endmodule // OAMBlock |
module ScrollRegs(
n_W0, n_W5_1, n_W5_2, n_W6_1, n_W6_2, n_DBE, RC, CPU_DB,
FH, FV, NTH, NTV, TV, TH, W6_2_Ena);
input n_W0;
input n_W5_1;
input n_W5_2;
input n_W6_1;
input n_W6_2;
input n_DBE;
input RC;
inout [7:0] CPU_DB;
output [2:0] FH;
output [2:0] FV;
output NTH;
output NTV;
output [4:0] TV;
output [4:0] TH;
output W6_2_Ena;
endmodule // ScrollRegs |
module PPU_CompositeDAC (RawIn, CompositeOut);
input [10:0] RawIn;
output [31:0] CompositeOut;
assign CompositeOut = 32'b0;
endmodule // PPU_CompositeDAC |
module PictureMUX(
n_PCLK, PCLK,
BGC, n_ZPRIO, n_ZCOL0, n_ZCOL1, ZCOL2, ZCOL3, EXT_in, THO, TH_MUX,
PAL_out, n_EXT_out);
input n_PCLK;
input PCLK;
input [3:0] BGC;
input n_ZPRIO;
input n_ZCOL0;
input n_ZCOL1;
input ZCOL2;
input ZCOL3;
input [3:0] EXT_in;
input [4:0] THO;
input TH_MUX;
output [4:0] PAL_out;
output [3:0] n_EXT_out;
endmodule // PictureMUX |
module Spr0Hit(
PCLK,
BGC, n_SPR0HIT, n_SPR0_EV, n_VIS, n_R2, n_DBE, RESCL,
DB6);
input PCLK;
input [3:0] BGC;
input n_SPR0HIT;
input n_SPR0_EV;
input n_VIS;
input n_R2;
input n_DBE;
input RESCL;
inout DB6;
wire bg;
nor (bg, BGC[0], BGC[1]);
wire Strike;
nor (Strike, PCLK, bg, n_SPR0HIT, n_SPR0_EV, n_VIS);
wire Strike_out;
rsff STRIKE_FF (
.r(RESCL),
.s(Strike),
.q(Strike_out) );
wire R2_Ena;
nor (R2_Ena, n_R2, n_DBE);
bufif1 (DB6, Strike_out, R2_Ena);
endmodule // Spr0Hit |
module PpuPadsLogic(
n_PCLK,
n_CpuRD, n_CpuWR, CPU_DB, DPads,
n_ALE_topad, ALE,
PD_out, n_PA, PAPads, ADPads, RD_topad, WR_topad, n_RDPad, n_WRPad,
EXTPads, n_SLAVE, EXT_in, n_EXT_out,
CLKPad, n_CLK_frompad, CLK_frompad,
n_RESPad, RES, RESCL, RC,
Int_topad, n_INTPad);
input n_PCLK;
input n_CpuRD;
input n_CpuWR;
inout [7:0] CPU_DB;
inout [7:0] DPads;
input n_ALE_topad;
output ALE;
output [7:0] PD_out;
input [13:0] n_PA;
output [5:0] PAPads;
inout [7:0] ADPads;
input RD_topad;
input WR_topad;
output n_RDPad;
output n_WRPad;
inout [3:0] EXTPads;
input n_SLAVE;
output [3:0] EXT_in;
input [3:0] n_EXT_out;
input CLKPad;
output n_CLK_frompad;
output CLK_frompad;
input n_RESPad;
output RES;
input RESCL;
output RC;
input Int_topad;
output n_INTPad;
// Logic
wire [7:0] DB_temp;
pnor DB_out [7:0] (CPU_DB, {8{n_CpuRD}}, DB_temp);
bustris DB_out_tris [7:0] (.a(DB_temp), .n_x(DPads), .n_en(n_CpuRD) );
bustris DB_in_tris [7:0] (.a(~DPads), .n_x(CPU_DB), .n_en(n_CpuWR) );
assign ALE = ~n_ALE_topad;
assign PD_out = ADPads;
bustris AD_out_tris [7:0] (.a(n_PA[7:0] | {8{RD_topad}}), .n_x(ADPads), .n_en(RD_topad) );
assign PAPads = ~n_PA[13:8];
assign n_RDPad = ~RD_topad;
assign n_WRPad = ~WR_topad;
wire [3:0] ext_latch_out;
pnor EXT_in_nors [3:0] (~EXTPads, {4{n_SLAVE}}, EXT_in);
dlatch EXT_out_latch [3:0] (.d(n_EXT_out), .en(n_PCLK), .q(ext_latch_out) );
bustris EXT_out_tris [3:0] (.a(ext_latch_out | {4{~n_SLAVE}}), .n_x(EXTPads), .n_en(~n_SLAVE) );
assign n_CLK_frompad = ~CLKPad;
assign CLK_frompad = CLKPad;
assign RES = ~n_RESPad;
wire Reset_FF_out;
rsff Reset_FF (.r(RESCL), .s(RES), .q(Reset_FF_out) );
assign RC = ~Reset_FF_out;
notif1 (n_INTPad, Int_topad, Int_topad);
endmodule // PadsLogic |
module CRAM_Block (
n_PCLK, PCLK,
n_R7, n_DBE, TH_MUX, DB_PAR, n_PICTURE, BnW,
PAL,
CPU_DB,
n_CC, n_LL);
input n_PCLK;
input PCLK;
input n_R7;
input n_DBE;
input TH_MUX;
input DB_PAR;
input n_PICTURE;
input BnW;
input [4:0] PAL;
inout [7:0] CPU_DB;
output [3:0] n_CC;
output [1:0] n_LL;
wire n_CB_DB;
wire color_mode;
wire n_DB_CB;
wire [5:0] cram_val;
wire [5:0] CB_Out;
wire [3:0] COL;
wire [6:0] ROW;
CB_Control cbctl(
.PCLK(PCLK),
.n_R7(n_R7),
.n_DBE(n_DBE),
.TH_MUX(TH_MUX),
.DB_PAR(DB_PAR),
.n_PICTURE(n_PICTURE),
.BnW(BnW),
.n_CB_DB(n_CB_DB),
.n_BW(color_mode),
.n_DB_CB(n_DB_CB) );
ColorBuf cb(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.CPU_DB(CPU_DB),
.n_DB_CB(n_DB_CB),
.n_CB_DB(n_CB_DB),
.n_OE(color_mode),
.cram_val(cram_val),
.CB_Out(CB_Out) );
CRAM_Decoder cramdec(
.PCLK(PCLK),
.PAL(PAL),
.COL(COL),
.ROW(ROW) );
CRAM cram(
.PCLK(PCLK),
.COL(COL),
.ROW(ROW),
.cram_val(cram_val) );
endmodule // CRAM_Block |
module CB_Control(
PCLK,
n_R7, n_DBE, TH_MUX, DB_PAR, n_PICTURE, BnW,
n_CB_DB, n_BW, n_DB_CB);
input PCLK;
input n_R7;
input n_DBE;
input TH_MUX;
input DB_PAR;
input n_PICTURE;
input BnW;
output n_CB_DB;
output n_BW;
output n_DB_CB;
endmodule // CB_Control |
module ColorBuf(
n_PCLK, PCLK,
CPU_DB,
n_DB_CB, n_CB_DB, n_OE, cram_val,
CB_Out );
input n_PCLK;
input PCLK;
inout [7:0] CPU_DB;
input n_DB_CB;
input n_CB_DB;
input n_OE;
inout [5:0] cram_val;
output [5:0] CB_Out;
endmodule // ColorBuf |
module CRAM_Decoder(PCLK, PAL, COL, ROW);
input PCLK;
input [4:0] PAL;
output [3:0] COL;
output [6:0] ROW;
endmodule // CRAM_Decoder |
module CRAM(PCLK, COL, ROW, cram_val);
input PCLK;
input [3:0] COL;
input [6:0] ROW;
inout [5:0] cram_val;
endmodule // CRAM |
module ObjectFIFO(
n_PCLK, PCLK,
PAR_O, H0_DD, H1_DD, H2_DD, H3_DD, H4_DD, H5_DD, Z_HPOS, n_VIS, PD_FIFO, PD, CLPO,
n_SPR0HIT, n_ZCOL0, n_ZCOL1, ZCOL2, ZCOL3, n_ZPRIO, n_SH2);
input n_PCLK;
input PCLK;
input PAR_O;
input H0_DD;
input H1_DD;
input H2_DD;
input H3_DD;
input H4_DD;
input H5_DD;
input Z_HPOS;
input n_VIS;
input PD_FIFO;
input [7:0] PD;
input CLPO;
output n_SPR0HIT;
output n_ZCOL0;
output n_ZCOL1;
output ZCOL2;
output ZCOL3;
output n_ZPRIO;
output n_SH2;
endmodule // ObjectFIFO |
module HVCounters (
n_PCLK, PCLK,
RES, HC, VC, V_IN,
H_out, V_out);
input n_PCLK;
input PCLK;
input RES;
input HC;
input VC;
input V_IN;
output [8:0] H_out;
output [8:0] V_out;
// Wires
wire [8:0] n_h;
wire [8:0] n_v;
wire [8:0] hc;
wire [8:0] vc;
wire half_hc;
wire half_vc;
// Instances
// The counters use some attempt to speed up the carry propagation, but a questionable one.
// Without these tweaks carry_in looks the usual way: {carry_chain[7:0], Carry_in} (9-bit counter)
HVCounterBit hcnt [8:0] (.PCLK(PCLK), .n_PCLK(n_PCLK), .CLR(HC), .RES(RES),
.cin({hc[7:5],half_hc,hc[3:0],1'b1}),
.val(H_out), .n_val(n_h), .cout(hc) );
assign half_hc = ~(n_h[0] | n_h[1] | n_h[2] | n_h[3] | n_h[4]);
HVCounterBit vcnt [8:0] (.PCLK(PCLK), .n_PCLK(n_PCLK), .CLR(VC), .RES(RES),
.cin({vc[7:5],half_vc,vc[3:0],V_IN}),
.val(V_out), .n_val(n_v), .cout(vc) );
assign half_vc = ~(~V_IN | n_v[0] | n_v[1] | n_v[2] | n_v[3] | n_v[4]);
endmodule // HVCounters |
module HVCounterBit (PCLK, n_PCLK, CLR, RES, cin, val, n_val, cout);
input PCLK;
input n_PCLK;
input CLR;
input RES;
input cin;
output val;
output n_val;
output cout;
wire keep_latch_q;
dlatch keep_latch (.d(cin ? val : n_val), .en(n_PCLK), .q(keep_latch_q) );
dlatch out_latch (.d(PCLK ? ~(keep_latch_q | CLR) : val), .en(1'b1), .nq(n_val) );
assign val = ~(n_val | RES);
assign cout = ~(n_val | ~cin);
endmodule // HVCounterBit |
module PpuRegs(
RC, n_DBE, RS, RnW, CPU_DB,
n_W5_1, n_W5_2, n_W6_1, n_W6_2,
n_R7, n_W7, n_W4, n_W3, n_R2, n_W1, n_W0, n_R4,
I_1_32, OBSEL, BGSEL, O_8_16, n_SLAVE, VBL,
BnW, n_BGCLIP, n_OBCLIP, BGE, BLACK, OBE, n_TR, n_TG, n_TB);
input RC;
input n_DBE;
input [2:0] RS;
input RnW;
inout [7:0] CPU_DB;
output n_W5_1;
output n_W5_2;
output n_W6_1;
output n_W6_2;
output n_R7;
output n_W7;
output n_W4;
output n_W3;
output n_R2;
output n_W1;
output n_W0;
output n_R4;
output I_1_32;
output OBSEL;
output BGSEL;
output O_8_16;
output n_SLAVE;
output VBL;
output BnW;
output n_BGCLIP;
output n_OBCLIP;
output BGE;
output BLACK;
output OBE;
output n_TR;
output n_TG;
output n_TB;
wire n_W56;
wire sccx_first;
wire sccx_second;
SCCXFirstSecond fs(
.RC(RC),
.n_DBE(n_DBE),
.n_R2(n_R2),
.n_W56(n_W56),
.Frst(sccx_first),
.Scnd(sccx_second) );
RegCTRL0 ctrl0(
.RC(RC),
.n_W0(n_W0),
.n_DBE(n_DBE),
.D_in(CPU_DB),
.I_1_32(I_1_32),
.OBSEL(OBSEL),
.BGSEL(BGSEL),
.O_8_16(O_8_16),
.n_SLAVE(n_SLAVE),
.VBL(VBL) );
RegCTRL1 ctrl1(
.RC(RC),
.n_W1(n_W1),
.n_DBE(n_DBE),
.D_in(CPU_DB),
.BnW(BnW),
.n_BGCLIP(n_BGCLIP),
.n_OBCLIP(n_OBCLIP),
.BGE(BGE),
.BLACK(BLACK),
.OBE(OBE),
.n_TR(n_TR),
.n_TG(n_TG),
.n_TB(n_TB) );
endmodule // Regs |
module SCCXFirstSecond(RC, n_DBE, n_R2, n_W56, Frst, Scnd);
input RC;
input n_DBE;
input n_R2;
input n_W56;
output Frst;
output Scnd;
wire q1;
wire nq1;
wire q2;
wire nq2;
wire W56;
wire R2;
assign R2 = n_R2 ~| n_DBE;
assign W56 = n_W56 ~| n_DBE;
sdffr2e FF_1 (.d(q2), .en(~W56), .res1(RC), .res2(R2), .phi_keep(W56), .q(q1), .nq(nq1) );
sdffr2e FF_2 (.d(nq1), .en(W56), .res1(RC), .res2(R2), .phi_keep(~W56), .q(q2), .nq(nq2) );
assign Frst = q1;
assign Scnd = nq1;
endmodule // SCCXFirstSecond |
module RegCTRL0(RC, n_W0, n_DBE, D_in, I_1_32, OBSEL, BGSEL, O_8_16, n_SLAVE, VBL);
input RC;
input n_W0;
input n_DBE;
inout [7:0] D_in;
output I_1_32;
output OBSEL;
output BGSEL;
output O_8_16;
output n_SLAVE;
output VBL;
endmodule // RegCTRL0 |
module RegCTRL1(RC, n_W1, n_DBE, D_in, BnW, n_BGCLIP, n_OBCLIP, BGE, BLACK, OBE, n_TR, n_TG, n_TB);
input RC;
input n_W1;
input n_DBE;
inout [7:0] D_in;
output BnW;
output n_BGCLIP;
output n_OBCLIP;
output BGE;
output BLACK;
output OBE;
output n_TR;
output n_TG;
output n_TB;
endmodule // RegCTRL1 |
module Clipper(n_PCLK, n_VIS, CLIP_B, CLIP_O, BGE, OBE, n_CLPB, CLPO);
input n_PCLK;
input n_VIS;
input CLIP_B;
input CLIP_O;
input BGE;
input OBE;
output n_CLPB;
output CLPO;
endmodule // Clipper |
module RWDecoder(RnW, n_DBE, n_RD, n_WR);
input RnW;
input n_DBE;
output n_RD;
output n_WR;
assign n_RD = ~( ~RnW ~| n_DBE );
assign n_WR = ~( RnW ~| n_DBE );
endmodule // RWDecoder |
module PAR(
n_PCLK, PCLK,
BLNK, DB_PAR, F_AT, SC_CNT, RESCL, E_EV, TSTEP, F_TB, H0_DD, n_H2_D, I_1_32, W6_2_Ena,
PAD_in, CPU_DB, TH, TV, NTH, NTV, FV,
n_FVO, THO, TVO, n_PA );
input n_PCLK;
input PCLK;
input BLNK;
input DB_PAR;
input F_AT;
input SC_CNT;
input RESCL;
input E_EV;
input TSTEP;
input F_TB;
input H0_DD;
input n_H2_D;
input I_1_32;
input W6_2_Ena;
input [13:0] PAD_in;
inout [7:0] CPU_DB;
input [4:0] TH;
input [4:0] TV;
input NTH;
input NTV;
input [2:0] FV;
output [2:0] n_FVO;
output [4:0] THO;
output [4:0] TVO;
output [13:0] n_PA;
endmodule // PAR |
module BGCol(
n_PCLK, PCLK,
H0_DD, F_TA, F_TB, n_FO, F_AT, THO, TVO, FH, PD, n_CLPB,
BGC);
input n_PCLK;
input PCLK;
input H0_DD;
input F_TA;
input F_TB;
input n_FO;
input F_AT;
input [4:0] THO;
input [4:0] TVO;
input [2:0] FH;
input [7:0] PD;
input n_CLPB;
output [3:0] BGC;
endmodule // BGCol |
module HVDecoder (
H_in, V_in, VB, BLNK,
HPLA_out, VPLA_out);
input [8:0] H_in;
input [8:0] V_in;
input VB;
input BLNK;
output [23:0] HPLA_out;
output [9:0] VPLA_out;
HDecoder hpla (.H(H_in), .VB(VB), .BLNK(BLNK), .dec_out(HPLA_out) );
VDecoder vpla (.V(V_in), .dec_out(VPLA_out) );
endmodule // HVDecoder |
module HDecoder (H, VB, BLNK, dec_out);
input [8:0] H;
input VB;
input BLNK;
output [23:0] dec_out;
wire [8:0] nH;
assign nH = ~H;
wire [19:0] d;
assign d = {H[8],nH[8],H[7],nH[7],H[6],nH[6],H[5],nH[5],H[4],nH[4],H[3],nH[3],H[2],nH[2],H[1],nH[1],H[0],nH[0],VB,BLNK};
`ifdef RP2C02
assign dec_out[0] = ~|{d[2],d[4],d[6],d[9],d[10],d[13],d[15],d[17],d[18]};
assign dec_out[1] = ~|{d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17],d[18]};
assign dec_out[2] = ~|{d[0],d[2],d[5],d[7],d[9],d[11],d[13],d[14],d[17],d[19]};
assign dec_out[3] = ~|{d[9],d[11],d[13],d[15],d[17]};
assign dec_out[4] = ~|{d[1],d[19]};
assign dec_out[5] = ~|{d[0],d[2],d[4],d[7],d[9],d[10],d[13],d[14],d[17],d[18]};
assign dec_out[6] = ~|{d[0],d[2],d[4],d[6],d[8],d[10],d[12],d[15],d[17],d[19]};
assign dec_out[7] = ~|{d[0],d[2],d[4],d[6],d[8],d[10],d[12],d[14],d[16]};
assign dec_out[8] = ~|{d[0],d[15],d[17],d[19]};
assign dec_out[9] = ~|{d[0],d[15],d[17],d[18]};
assign dec_out[10] = ~|{d[0],d[1],d[19]};
assign dec_out[11] = ~|{d[0],d[5],d[7]};
assign dec_out[12] = ~|{d[4],d[6]};
assign dec_out[13] = ~|{d[5],d[6]};
assign dec_out[14] = ~|{d[0],d[11],d[13],d[14],d[18]};
assign dec_out[15] = ~|{d[0],d[19]};
assign dec_out[16] = ~|{d[4],d[7]};
assign dec_out[17] = ~|{d[3],d[4],d[6],d[8],d[11],d[13],d[15],d[17],d[18]};
assign dec_out[18] = ~|{d[3],d[5],d[7],d[8],d[11],d[13],d[14],d[17],d[18]};
assign dec_out[19] = ~|{d[2],d[4],d[6],d[9],d[10],d[13],d[15],d[17],d[18]};
assign dec_out[20] = ~|{d[3],d[5],d[7],d[9],d[10],d[12],d[15],d[17],d[18]};
assign dec_out[21] = ~|{d[2],d[4],d[7],d[9],d[11],d[13],d[14],d[17],d[18]};
assign dec_out[22] = ~|{d[3],d[5],d[6],d[9],d[10],d[12],d[15],d[17],d[18]};
assign dec_out[23] = ~|{d[3],d[5],d[6],d[9],d[10],d[13],d[14],d[17],d[18]};
`elsif RP2C07
assign dec_out[0] = ~|{d[2],d[5],d[6],d[9],d[10],d[13],d[15],d[17],d[18]};
assign dec_out[1] = ~|{d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17],d[18]};
assign dec_out[2] = ~|{d[0],d[2],d[5],d[7],d[9],d[11],d[13],d[14],d[17],d[19]};
assign dec_out[3] = ~|{d[9],d[11],d[13],d[15],d[17]};
assign dec_out[4] = ~|{d[1],d[19]};
assign dec_out[5] = ~|{d[0],d[2],d[4],d[7],d[9],d[10],d[13],d[14],d[17],d[18]};
assign dec_out[6] = ~|{d[0],d[2],d[4],d[6],d[8],d[10],d[12],d[15],d[17],d[19]};
assign dec_out[7] = ~|{d[0],d[2],d[4],d[6],d[8],d[10],d[12],d[14],d[16]};
assign dec_out[8] = ~|{d[0],d[15],d[17],d[19]};
assign dec_out[9] = ~|{d[0],d[15],d[17],d[18]};
assign dec_out[10] = ~|{d[0],d[1],d[19]};
assign dec_out[11] = ~|{d[0],d[5],d[7]};
assign dec_out[12] = ~|{d[4],d[6]};
assign dec_out[13] = ~|{d[5],d[6]};
assign dec_out[14] = ~|{d[0],d[11],d[13],d[14],d[18]};
assign dec_out[15] = ~|{d[0],d[19]};
assign dec_out[16] = ~|{d[4],d[7]};
assign dec_out[17] = ~|{d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17],d[18]};
assign dec_out[18] = ~|{d[3],d[5],d[6],d[9],d[11],d[13],d[15],d[17],d[19]};
assign dec_out[19] = ~|{d[2],d[5],d[6],d[9],d[10],d[13],d[15],d[17],d[18]};
assign dec_out[20] = ~|{d[3],d[4],d[6],d[8],d[11],d[12],d[15],d[17],d[18]};
assign dec_out[21] = ~|{d[2],d[5],d[7],d[9],d[11],d[13],d[14],d[17],d[18]};
assign dec_out[22] = ~|{d[3],d[4],d[7],d[9],d[10],d[12],d[15],d[17],d[18]};
assign dec_out[23] = ~|{d[3],d[5],d[6],d[9],d[10],d[13],d[14],d[17],d[18]};
`else
`endif
endmodule // HDecoder |
module VDecoder (V, dec_out);
input [8:0] V;
output [9:0] dec_out;
wire [8:0] nV;
assign nV = ~V;
wire [17:0] d;
assign d = {V[8],nV[8],V[7],nV[7],V[6],nV[6],V[5],nV[5],V[4],nV[4],V[3],nV[3],V[2],nV[2],V[1],nV[1],V[0],nV[0]};
`ifdef RP2C02
assign dec_out[0] = ~|{d[0],d[2],d[4],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[1] = ~|{d[1],d[3],d[4],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[2] = ~|{d[0],d[3],d[4],d[7],d[9],d[11],d[13],d[15],d[16]};
assign dec_out[3] = ~|{d[0],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[4] = ~|{d[0],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[5] = ~|{d[1],d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign dec_out[6] = ~|{d[1],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[7] = ~|{d[0],d[3],d[4],d[7],d[9],d[11],d[13],d[15],d[16]};
assign dec_out[8] = ~|{d[0],d[3],d[4],d[7],d[9],d[11],d[13],d[15],d[16]};
assign dec_out[9] = 1'b0; // Not present in NTSC PPUs
`elsif RP2C07
assign dec_out[0] = ~|{d[1],d[3],d[5],d[7],d[8],d[11],d[13],d[15],d[16]};
assign dec_out[1] = ~|{d[0],d[3],d[4],d[6],d[9],d[11],d[13],d[15],d[16]};
assign dec_out[2] = ~|{d[0],d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign dec_out[3] = ~|{d[1],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[4] = ~|{d[0],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[5] = ~|{d[1],d[3],d[5],d[7],d[9],d[11],d[13],d[15],d[17]};
assign dec_out[6] = ~|{d[1],d[3],d[5],d[7],d[8],d[10],d[12],d[14]};
assign dec_out[7] = ~|{d[0],d[2],d[4],d[7],d[8],d[10],d[13],d[15],d[16]};
assign dec_out[8] = ~|{d[0],d[2],d[4],d[7],d[8],d[10],d[13],d[15],d[16]};
assign dec_out[9] = ~|{d[0],d[3],d[5],d[6],d[9],d[11],d[13],d[15],d[16]};
`else
`endif
endmodule // VDecoder |
module VRAM_Control(
n_PCLK, PCLK,
n_R7, n_W7, n_DBE, H0_D, BLNK, nPA,
DB_PAR, TSTEP, WR, RD, n_ALE, PD_RB, XRB, TH_MUX);
input n_PCLK;
input PCLK;
input n_R7;
input n_W7;
input n_DBE;
input H0_D;
input BLNK;
input [13:0] nPA;
output DB_PAR;
output TSTEP;
output WR;
output RD;
output n_ALE;
output PD_RB;
output XRB;
output TH_MUX;
endmodule // VRAM_Control |
module ReadBuffer(XRB, RC, PD_RB, PD_in, CPU_DB);
input XRB;
input RC;
input PD_RB;
input [7:0] PD_in;
inout [7:0] CPU_DB;
endmodule // ReadBuffer |
module PPU(RnW, D, RS, n_DBE, EXT, CLK, n_INT, ALE, AD, A, n_RD, n_WR, n_RES, VOut);
input RnW; // Read-notWrite. Used to read/write PPU registers. If R/W = 1 it reads, otherwise it writes. It is easy to remember: "Read(1), do not write".
inout [7:0] D; // The data bus for transferring register values. When /DBE = 1 the bus is disconnected (Z)
input [2:0] RS; // Register Select. Sets the PPU register number (0-7)
input n_DBE; // Data Bus Enable. If /DBE = 0, then the D0-D7 bus is used to exchange values with the PPU registers, otherwise the bus is disconnected.
inout [3:0] EXT; // The bus is used to mix the color of the current pixel from another PPU (slave mode), or to output the current color to the outside (master mode).
// The direction of the bus is determined by the register bit $2000[6] (0: PPU slave mode, 1: PPU master mode)
input CLK; // Master Clock
output n_INT; // PPU interrupt signal (VBlank)
output ALE; // Address Latch Enable. If ALE=1, then the bus AD0-AD7 operates as an address bus (A0-A7), otherwise it operates as a data bus (D0-D7)
inout [7:0] AD; // Multiplexed address/data bus. When ALE=1 the bus operates as an address bus, when ALE=0 the bus sends data to the PPU (patterns, attributes), or out from the PPU port (register $2007)
output [5:0] A; // This bus carries the rest of the address lines.
output n_RD; // /RD=0: the PPU data bus (AD0-AD7) is used for reading (VRAM -> PPU)
output n_WR; // /WR=0: the PPU data bus (AD0-AD7) is used for writing (PPU -> VRAM)
input n_RES; // /RES=0: reset the PPU
output [31:0] VOut; // Composite video signal from DAC [float as uint32]
// Wires
wire n_CLK_frompad; // First half of the PPU cycle
wire CLK_frompad; // Second half of the PPU cycle
wire n_PCLK; // First half of the Pixel Clock cycle
wire PCLK; // Second half of the Pixel Clock cycle
wire RES_frompad; // Global reset
wire RegClear;
wire n_CpuRD; // /RD to D0-D7 pads (CPU I/F)
wire n_CpuWR; // /WR to D0-D7 pads (CPU I/F)
wire n_W5_1; // 0: First write to $2005
wire n_W5_2; // 0: Second write to $2005
wire n_W6_1; // 0: First write to $2006
wire n_W6_2; // 0: Second write to $2006
wire n_R7; // 0: Read $2007
wire n_W7; // 0: Write $2007
wire n_W4; // 0: Write $2004
wire n_W3; // 0: Write $2003
wire n_R2; // 0: Read $2002
wire n_W1; // 0: Write $2001
wire n_W0; // 0: Write $2000
wire n_R4; // 0: Read $2004
wire I_1_32; // Increment PPU address 1/32.
wire OBSEL; // Selecting Pattern Table for sprites
wire BGSEL; // Selecting Pattern Table for background
wire O_8_16; // Object lines 8/16 (sprite size).
wire n_SLAVE; // PPU operating mode (Master/Slave)
wire VBL_Ena; // Used in the VBlank interrupt handling circuitry
wire BnW;
wire n_BGCLIP; // To generate the CLIP_B control signal
wire n_OBCLIP; // To generate the CLIP_O control signal
wire BGE;
wire BLACK; // Active when PPU rendering is disabled (see $2001[3] и $2001[4]).
wire OBE;
wire n_TR; // 0: "Tint Red". Modifying value for Emphasis
wire n_TG; // 0: "Tint Green". Modifying value for Emphasis
wire n_TB; // 0: "Tint Blue". Modifying value for Emphasis
wire [8:0] HCnt; // H counter bits
wire [8:0] VCnt; // V counter bits
wire [23:0] HDecoder_out; // H decoder outputs
wire [9:0] VDecoder_out; // V decoder outputs
wire H0_D; // H0 signal delayed by one DLatch
wire nH1_D; // H1 signal delayed by one DLatch (in inverse logic)
wire nH2_D; // H2 signal delayed by one DLatch (in inverse logic)
wire H0_DD; // H0-H5 signals delayed by two DLatch
wire H1_DD;
wire H2_DD;
wire H3_DD;
wire H4_DD;
wire H5_DD;
wire S_EV; // "Start Sprite Evaluation"
wire CLIP_O; // "Clip Objects". 1: Do not show the left 8 screen points for sprites. Used to get the CLPO signal that goes into the OAM FIFO.
wire CLIP_B; // "Clip Background". 1: Do not show the left 8 points of the screen for the background. Used to get the /CLPB signal that goes into the Data Reader.
wire Z_HPOS; // "Clear HPos". Clear the H counters in the sprite FIFO and start the FIFO
wire n_EVAL; // 0: "Sprite Evaluation in Progress"
wire E_EV; // "End Sprite Evaluation"
wire I_OAM2; // "Init OAM2". Initialize an additional (temp) OAM
wire PAR_O; // "PAR for Object". Selecting a tile for an object (sprite)
wire n_VIS; // "Not Visible". The invisible part of the signal (used in sprite logic)
wire n_FNT; // 0: "Fetch Name Table"
wire F_TB; // "Fetch Tile B"
wire F_TA; // "Fetch Tile A"
wire n_FO; // 0: "Fetch Output Enable"
wire F_AT; // "Fetch Attribute Table"
wire SC_CNT; // "Scroll Counters Control". Update the scrolling registers.
wire BURST; // Do Color Burst
wire SYNC; // Do Sync pulse
wire n_PICTURE; // Visible part of the scan-lines
wire RESCL; // "Reset FF Clear" / "VBlank Clear". VBlank period end event. Initially the connection was established with contact /RES, but then it turned out a more global purpose of the signal. Therefore, the signal has two names.
wire VB; // Active when the invisible part of the video signal is output (used only in H Decoder)
wire BLNK; // Active when PPU rendering is disabled (by BLACK signal) or during VBlank
wire Int; // 1: "Interrupt". PPU Interrupt
wire V_IN; // "VCounter In". Increment the VCounter
wire HC; // "HCounter Clear"
wire VC; // "VCounter Clear"
wire n_CLPB; // To enable background clipping
wire CLPO; // To enable sprite clipping
wire [7:0] n_OAM; // OAM Address. (inverse polarity)
wire OAM8; // Selects an additional (temp) OAM for addressing
wire OAMCTR2; // OAM Buffer Control
wire OFETCH;
wire SPR_OV; // Sprites on the current line are more than 8 or the main OAM counter is full, copying is stopped
wire [7:0] OV;
wire PD_FIFO; // To zero the output of the H. Inv circuit
wire n_SPR0_EV; // 0: Sprite "0" is found on the current line. To define a Sprite 0 Hit event
wire n_SPR0HIT; // To detect a Sprite 0 Hit event (from FIFO side)
wire n_ZCOL0; // Sprite color. ⚠️ The lower 2 bits are in inverse logic, the higher 2 bits are in direct logic.
wire n_ZCOL1;
wire ZCOL2;
wire ZCOL3;
wire n_ZPRIO; // 0: Priority of sprite over background
wire n_SH2;
wire [4:0] TH;
wire [4:0] TV;
wire NTH;
wire NTV;
wire [2:0] FH; // Fine H value
wire [2:0] FV; // Fine V value
wire [2:0] n_FVO;
wire [4:0] THO;
wire [4:0] TVO;
wire W6_2_Ena;
wire [3:0] BGC; // Background color
wire [13:0] PAD;
wire [7:0] CPU_DB; // Internal CPU data bus DB
wire [7:0] PD; // Read-only PPU Data bus
wire [13:0] n_PA_out; // VRAM address bus (Output)
wire [7:0] OB; // OAM Buffer output value
wire [3:0] EXT_in; // Input subcolor from Master PPU
wire [3:0] n_EXT_out; // Output color for Slave PPU
wire DB_PAR;
wire TSTEP; // For PAR Counters control logic
wire WR; // Output value for /WR pad
wire RD; // Output value for /RD pad
wire n_ALE; // Output value for ALE pad
wire PD_RB; // Opens RB input (connect PD and RB).
wire XRB; // Opens RB output (connect RB and DB).
wire TH_MUX; // Send the TH Counter value to the MUX input, which will cause the value to go into the palette as Direct Color.
wire [4:0] CRAM_Addr;
wire [3:0] n_CC; // 4 bits of the chrominance of the current "pixel" (inverted value)
wire [1:0] n_LL; // 2 bits of the luminance of the current "pixel" (inverted value)
wire [10:0] RawVOut; // Unprocessed RAW Video
// Module instantiation
PpuPadsLogic pads(
.n_PCLK(n_PCLK),
.n_CpuRD(n_CpuRD),
.n_CpuWR(n_CpuWR),
.CPU_DB(CPU_DB),
.DPads(D),
.n_ALE_topad(n_ALE),
.ALE(ALE),
.PD_out(PD),
.n_PA(n_PA_out),
.PAPads(A),
.ADPads(AD),
.RD_topad(RD),
.WR_topad(WR),
.n_RDPad(n_RD),
.n_WRPad(n_WR),
.EXTPads(EXT),
.n_SLAVE(n_SLAVE),
.EXT_in(EXT_in),
.n_EXT_out(n_EXT_out),
.CLKPad(CLK),
.n_CLK_frompad(n_CLK_frompad),
.CLK_frompad(CLK_frompad),
.n_RESPad(n_RES),
.RES(RES_frompad),
.RESCL(RESCL),
.RC(RegClear),
.Int_topad(Int),
.n_INTPad(n_INT) );
PixelClock pclk(
.n_CLK(n_CLK_frompad),
.CLK(CLK_frompad),
.RES(RES_frompad),
.n_PCLK(n_PCLK),
.PCLK(PCLK) );
RWDecoder rwdec(
.RnW(RnW),
.n_DBE(n_DBE),
.n_RD(n_CpuRD),
.n_WR(n_CpuWR) );
PpuRegs regs(
.RC(RegClear),
.n_DBE(),
.RS(RS),
.RnW(RnW),
.CPU_DB(CPU_DB),
.n_W5_1(n_W5_1),
.n_W5_2(n_W5_2),
.n_W6_1(n_W6_1),
.n_W6_2(n_W6_2),
.n_R7(n_R7),
.n_W7(n_W7),
.n_W4(n_W4),
.n_W3(n_W3),
.n_R2(n_R2),
.n_W1(n_W1),
.n_W0(n_W0),
.n_R4(n_R4),
.I_1_32(I_1_32),
.OBSEL(OBSEL),
.BGSEL(BGSEL),
.O_8_16(O_8_16),
.n_SLAVE(n_SLAVE),
.VBL(VBL_Ena),
.BnW(BnW),
.n_BGCLIP(n_BGCLIP),
.n_OBCLIP(n_OBCLIP),
.BGE(BGE),
.BLACK(BLACK),
.OBE(OBE),
.n_TR(n_TR),
.n_TG(n_TG),
.n_TB(n_TB) );
HVCounters hv(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.RES(RES_frompad),
.HC(HC),
.VC(VC),
.V_IN(V_IN),
.H_out(HCnt),
.V_out(VCnt) );
HVDecoder hvdec(
.H_in(HCnt),
.V_in(VCnt),
.VB(VB),
.BLNK(BLNK),
.HPLA_out(HDecoder_out),
.VPLA_out(VDecoder_out) );
PPU_FSM fsm(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.H_out(HCnt),
.V_out(VCnt),
.HPLA_out(HDecoder_out),
.VPLA_out(VDecoder_out),
.RES(RES_frompad),
.VBL_EN(VBL_Ena),
.n_R2(n_R2),
.n_DBE(n_DBE),
.n_OBCLIP(n_OBCLIP),
.n_BGCLIP(n_BGCLIP),
.BLACK(BLACK),
.H0_DD(H0_DD),
.H0_D(H0_D),
.H1_DD(H1_DD),
.nH1_D(nH1_D),
.H2_DD(H2_DD),
.nH2_D(nH2_D),
.H3_DD(H3_DD),
.H4_DD(H4_DD),
.H5_DD(H5_DD),
.S_EV(S_EV),
.CLIP_O(CLIP_O),
.CLIP_B(CLIP_B),
.Z_HPOS(Z_HPOS),
.n_EVAL(n_EVAL),
.E_EV(E_EV),
.I_OAM2(I_OAM2),
.PAR_O(PAR_O),
.n_VIS(n_VIS),
.n_FNT(n_FNT),
.F_TB(F_TB),
.F_TA(F_TA),
.n_FO(n_FO),
.F_AT(F_AT),
.SC_CNT(SC_CNT),
.BURST(BURST),
.SYNC(SYNC),
.n_PICTURE(n_PICTURE),
.RESCL(RESCL),
.VB(VB),
.BLNK(BLNK),
.Int(Int),
.DB7(CPU_DB[7]),
.V_IN(V_IN),
.HC(HC),
.VC(VC) );
Clipper clip(
.n_PCLK(n_PCLK),
.n_VIS(n_VIS),
.CLIP_B(CLIP_B),
.CLIP_O(CLIP_O),
.BGE(BGE),
.OBE(OBE),
.n_CLPB(n_CLPB),
.CLPO(CLPO) );
OAMEval eval(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.BLNK(BLNK),
.I_OAM2(I_OAM2),
.n_VIS(n_VIS),
.PAR_O(PAR_O),
.n_EVAL(n_EVAL),
.RESCL(RESCL),
.H0_DD(H0_DD),
.H0_D(H0_D),
.n_H2_D(nH2_D),
.OFETCH(OFETCH),
.n_FNT(n_FNT),
.S_EV(S_EV),
.n_W3(n_W3),
.n_DBE(n_DBE),
.DB5(CPU_DB[5]),
.n_OAM(n_OAM),
.OAM8(OAM8),
.OAMCTR2(OAMCTR2),
.SPR_OV(SPR_OV),
.OV(OV),
.PD_FIFO(PD_FIFO),
.n_SPR0_EV(n_SPR0_EV) );
OAMBlock oam(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.n_OAM(n_OAM),
.OAM8(OAM8),
.BLNK(BLNK),
.SPR_OV(SPR_OV),
.OAMCTR2(OAMCTR2),
.H0_DD(H0_DD),
.n_VIS(n_VIS),
.I_OAM2(I_OAM2),
.n_W4(n_W4),
.n_R4(n_R4),
.n_DBE(n_DBE),
.CPU_DB(CPU_DB),
.OB_Out(OB),
.OFETCH(OFETCH) );
ObjectFIFO fifo(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.PAR_O(PAR_O),
.H0_DD(H0_DD),
.H1_DD(H1_DD),
.H2_DD(H2_DD),
.H3_DD(H3_DD),
.H4_DD(H4_DD),
.H5_DD(H5_DD),
.Z_HPOS(Z_HPOS),
.n_VIS(n_VIS),
.PD_FIFO(PD_FIFO),
.PD(PD),
.CLPO(CLPO),
.n_SPR0HIT(n_SPR0HIT),
.n_ZCOL0(n_ZCOL0),
.n_ZCOL1(n_ZCOL1),
.ZCOL2(ZCOL2),
.ZCOL3(ZCOL3),
.n_ZPRIO(n_ZPRIO),
.n_SH2(n_SH2) );
PataddrGen patgen(
.n_PCLK(n_PCLK),
.H0_DD(H0_DD),
.n_FNT(n_FNT),
.BGSEL(BGSEL),
.OBSEL(OBSEL),
.O8_16(O_8_16),
.PAR_O(PAR_O),
.n_SH2(n_SH2),
.n_H1D(nH1_D),
.OB(OB),
.PD(PD),
.OV(OV[3:0]),
.n_FVO(n_FVO),
.PAddr_out(PAD) );
PAR par(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.BLNK(BLNK),
.DB_PAR(DB_PAR),
.F_AT(F_AT),
.SC_CNT(SC_CNT),
.RESCL(RESCL),
.E_EV(E_EV),
.TSTEP(TSTEP),
.F_TB(F_TB),
.H0_DD(H0_DD),
.n_H2_D(nH2_D),
.I_1_32(I_1_32),
.W6_2_Ena(W6_2_Ena),
.PAD_in(PAD),
.CPU_DB(CPU_DB),
.TH(TH),
.TV(TV),
.NTH(NTH),
.NTV(NTV),
.FV(FV),
.n_FVO(n_FVO),
.THO(THO),
.TVO(TVO),
.n_PA(n_PA_out) );
ScrollRegs sccx(
.n_W0(n_W0),
.n_W5_1(n_W5_1),
.n_W5_2(n_W5_2),
.n_W6_1(n_W6_1),
.n_W6_2(n_W6_2),
.n_DBE(n_DBE),
.RC(RegClear),
.CPU_DB(CPU_DB),
.FH(FH),
.FV(FV),
.NTH(NTH),
.NTV(NTV),
.TV(TV),
.TH(TH),
.W6_2_Ena(W6_2_Ena) );
BGCol bg(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.H0_DD(H0_DD),
.F_TA(F_TA),
.F_TB(F_TB),
.n_FO(n_FO),
.F_AT(F_AT),
.THO(THO),
.TVO(TVO),
.FH(FH),
.PD(PD),
.n_CLPB(n_CLPB),
.BGC(BGC) );
VRAM_Control vrctl(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.n_R7(n_R7),
.n_W7(n_W7),
.n_DBE(n_DBE),
.H0_D(H0_D),
.BLNK(BLNK),
.nPA(n_PA_out),
.DB_PAR(DB_PAR),
.TSTEP(TSTEP),
.WR(WR),
.RD(RD),
.n_ALE(n_ALE),
.PD_RB(PD_RB),
.XRB(XRB),
.TH_MUX(TH_MUX) );
ReadBuffer rb(
.XRB(XRB),
.RC(RegClear),
.PD_RB(PD_RB),
.PD_in(PD),
.CPU_DB(CPU_DB) );
PictureMUX pmux(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.BGC(BGC),
.n_ZPRIO(n_ZPRIO),
.n_ZCOL0(n_ZCOL0),
.n_ZCOL1(n_ZCOL1),
.ZCOL2(ZCOL2),
.ZCOL3(ZCOL3),
.EXT_in(EXT_in),
.THO(THO),
.TH_MUX(TH_MUX),
.PAL_out(CRAM_Addr),
.n_EXT_out(n_EXT_out) );
Spr0Hit spr0hit(
.PCLK(PCLK),
.BGC(BGC),
.n_SPR0HIT(n_SPR0HIT),
.n_SPR0_EV(n_SPR0_EV),
.n_VIS(n_VIS),
.n_R2(n_R2),
.n_DBE(n_DBE),
.RESCL(RESCL),
.DB6(CPU_DB[6]) );
CRAM_Block cram(
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.n_R7(n_R7),
.n_DBE(n_DBE),
.TH_MUX(TH_MUX),
.DB_PAR(DB_PAR),
.n_PICTURE(n_PICTURE),
.BnW(BnW),
.PAL(CRAM_Addr),
.CPU_DB(CPU_DB),
.n_CC(n_CC),
.n_LL(n_LL) );
VideoGen vidout(
.n_CLK(n_CLK_frompad),
.CLK(CLK_frompad),
.n_PCLK(n_PCLK),
.PCLK(PCLK),
.RES(RES_frompad),
.n_CC(n_CC),
.n_LL(n_LL),
.BURST(BURST),
.SYNC(SYNC),
.n_PICTURE(n_PICTURE),
.n_TR(n_TR),
.n_TG(n_TG),
.n_TB(n_TB),
`ifdef RP2C07
.V0(VCnt[0]),
`endif
.RawVOut(RawVOut) );
PPU_CompositeDAC dac (.RawIn(RawVOut), .CompositeOut(VOut) );
endmodule // PPU |
module ACLKGen(PHI1, PHI2, ACLK1, nACLK2, RES);
input PHI1;
input PHI2;
output ACLK1;
output nACLK2;
input RES;
wire n_latch1_out;
wire n_latch2_out;
wire latch1_in;
dlatch phi1_latch (
.d(latch1_in),
.en(PHI1),
.nq(n_latch1_out) );
dlatch phi2_latch (
.d(n_latch1_out),
.en(PHI2),
.nq(n_latch2_out) );
nor (latch1_in, RES, n_latch2_out);
wire n1;
nor (n1, ~PHI1, latch1_in);
nor (ACLK1, ~PHI1, n_latch2_out);
not (nACLK2, n1);
endmodule // ACLKGen |
module SoftTimer(
PHI1, ACLK1, nACLK2,
RES, n_R4015, W4017, DB, DMCINT, INT_out, nLFO1, nLFO2);
input PHI1;
input ACLK1;
input nACLK2;
input RES;
input n_R4015;
input W4017;
inout [7:0] DB;
input DMCINT;
output INT_out;
output nLFO1;
output nLFO2;
wire n_mode;
wire mode;
wire [5:0] PLA_out;
wire Z2;
wire F1; // 1: Reset LFSR
wire F2; // 1: Perform the LFSR step
wire sin;
wire [14:0] sout;
wire [14:0] n_sout;
// SoftCLK control circuits have a very conventional division, because they are "scattered" in an even layer on the chip and it is difficult to determine their boundaries
SoftCLK_Control ctrl (
.PHI1(PHI1),
.ACLK1(ACLK1),
.RES(RES),
.DB(DB),
.DMCINT(DMCINT),
.n_R4015(n_R4015),
.W4017(W4017),
.PLA_in(PLA_out),
.n_mdout(n_mode),
.mdout(mode),
.Timer_Int(INT_out) );
SoftCLK_LFSR_Control lfsr_ctrl (
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.W4017(W4017),
.n_mode(n_mode),
.mode(mode),
.PLA_in(PLA_out),
.C13(sout[13]),
.C14(sout[14]),
.Z2(Z2),
.F1(F1),
.F2(F2),
.sin_toLFSR(sin) );
SoftCLK_LFSR lfsr (
.ACLK1(ACLK1),
.F1_Reset(F1),
.F2_Step(F2),
.sin(sin),
.sout(sout),
.n_sout(n_sout) );
SoftCLK_PLA pla (
.s(sout),
.ns(n_sout),
.md(mode),
.PLA_out(PLA_out) );
// LFO Output
wire tmp1;
nor (tmp1, PLA_out[0], PLA_out[1], PLA_out[2], PLA_out[3], PLA_out[4], Z2);
wire tmp2;
nor (tmp2, tmp1, nACLK2);
assign nLFO1 = ~tmp2;
wire tmp3;
nor (tmp3, PLA_out[1], PLA_out[3], PLA_out[4], Z2);
wire tmp4;
nor (tmp4, tmp3, nACLK2);
assign nLFO2 = ~tmp4;
endmodule // SoftTimer |
module SoftCLK_Control(
PHI1, ACLK1,
RES, DB, DMCINT, n_R4015, W4017, PLA_in,
n_mdout, mdout, Timer_Int);
input PHI1;
input ACLK1;
input RES;
inout [7:0] DB;
input DMCINT;
input n_R4015;
input W4017;
input [5:0] PLA_in;
inout n_mdout;
output mdout;
output Timer_Int;
wire R4015_clear;
wire mask_clear;
wire intff_out;
wire n_intff_out;
wire int_sum;
wire int_latch_out;
nor (R4015_clear, n_R4015, PHI1);
RegisterBit mode (.d(DB[7]), .ena(W4017), .ACLK1(ACLK1), .nq(n_mdout) );
RegisterBit mask (.d(DB[6]), .ena(W4017), .ACLK1(ACLK1), .q(mask_clear) );
rsff_2_4 int_ff (.res1(RES), .res2(R4015_clear), .res3(mask_clear), .s(n_mdout & PLA_in[3]), .q(intff_out), .nq(n_intff_out) );
dlatch md_latch (.d(n_mdout), .en(ACLK1), .nq(mdout) );
dlatch int_latch (.d(n_intff_out), .en(ACLK1), .q(int_latch_out) );
bustris int_status (.a(int_latch_out), .n_x(DB[6]), .n_en(n_R4015) );
nor (int_sum, intff_out, DMCINT);
assign Timer_Int = ~int_sum;
endmodule // SoftCLK_Control |
module SoftCLK_LFSR_Control(
ACLK1, nACLK2,
RES, W4017, n_mode, mode, PLA_in, C13, C14,
Z2, F1, F2, sin_toLFSR);
input ACLK1;
input nACLK2;
input RES;
input W4017;
inout n_mode;
input mode;
input [5:0] PLA_in;
input C13;
input C14;
output Z2;
output F1;
output F2;
output sin_toLFSR;
wire Z1;
// LFSR control
wire t1;
nor (t1, PLA_in[3], PLA_in[4], Z1);
nor (F1, t1, nACLK2);
nor (F2, ~t1, nACLK2);
// LFO control
wire z1_out;
wire z2_out;
wire zff_out;
wire zff_set;
nor (zff_set, z1_out, nACLK2);
dlatch z1 (.d(zff_out), .en(ACLK1), .q(z1_out), .nq(Z1) );
dlatch z2 (.d(n_mode), .en(ACLK1), .q(z2_out) );
rsff_2_3 z_ff (.res1(RES), .res2(W4017), .s(zff_set), .q(zff_out) );
nor (Z2, z1_out, z2_out);
// LFSR shift in
wire tmp1;
nor (tmp1, C13, C14, PLA_in[5]);
nor (sin_toLFSR, C13 & C14, tmp1);
endmodule // SoftCLK_LFSR_Control |
module SoftCLK_LFSR_Bit(
ACLK1,
sin, F1, F2,
sout, n_sout);
input ACLK1;
input sin;
input F1;
input F2;
output sout;
output n_sout;
wire inlatch_out;
dlatch in_latch (
.d(F2 ? sin : (F1 ? 1'b1 : 1'bz)),
.en(1'b1), .nq(inlatch_out));
dlatch out_latch (.d(inlatch_out), .en(ACLK1), .q(n_sout), .nq(sout));
endmodule // SoftCLK_LFSR_Bit |
module SoftCLK_LFSR(
ACLK1, F1_Reset, F2_Step, sin,
sout, n_sout);
input ACLK1;
input F1_Reset;
input F2_Step;
input sin;
output [14:0] sout;
output [14:0] n_sout;
SoftCLK_LFSR_Bit bits [14:0] (
.ACLK1(ACLK1),
.sin({sout[13:0],sin}),
.F1(F1_Reset),
.F2(F2_Step),
.sout(sout),
.n_sout(n_sout) );
endmodule // SoftCLK_LFSR |
module SoftCLK_PLA(s, ns, md, PLA_out);
input [14:0] s;
input [14:0] ns;
input md; // For PLA[3]
output [5:0] PLA_out;
nor (PLA_out[0], ns[0], s[1], s[2], s[3], s[4], ns[5], ns[6], s[7], s[8], s[9], s[10], s[11], ns[12], s[13], s[14]);
nor (PLA_out[1], ns[0], ns[1], s[2], s[3], s[4], s[5], s[6], s[7], s[8], ns[9], ns[10], s[11], ns[12], ns[13], s[14]);
nor (PLA_out[2], ns[0], ns[1], s[2], s[3], ns[4], s[5], ns[6], ns[7], s[8], s[9], ns[10], ns[11], s[12], ns[13], s[14]);
nor (PLA_out[3], ns[0], ns[1], ns[2], ns[3], ns[4], s[5], s[6], s[7], s[8], ns[9], s[10], ns[11], s[12], s[13], s[14], md); // ⚠️
nor (PLA_out[4], ns[0], s[1], ns[2], s[3], s[4], s[5], s[6], ns[7], ns[8], s[9], s[10], s[11], ns[12], ns[13], ns[14]);
nor (PLA_out[5], s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7], s[8], s[9], s[10], s[11], s[12], s[13], s[14]);
endmodule // SoftCLK_PLA |
module Core(
core_PHI0, core_PHI1, core_PHI2,
core_nNMI, core_nIRQ, core_nRES, core_RDY,
core_SO, core_RnW, core_SYNC, core_DPads, core_APads);
input core_PHI0;
output core_PHI1;
output core_PHI2;
input core_nNMI;
input core_nIRQ;
input core_nRES;
input core_RDY;
input core_SO;
output core_RnW;
output core_SYNC;
inout [7:0] core_DPads;
output [15:0] core_APads;
Core6502 embedded_6502 (
.n_NMI(core_nNMI),
.n_IRQ(core_nIRQ),
.n_RES(core_nRES),
.PHI0(core_PHI0),
.PHI1(core_PHI1),
.PHI2(core_PHI2),
.RDY(core_RDY),
.SO(core_SO),
.RnW(core_RnW),
.SYNC(core_SYNC),
.A(core_APads),
.D(core_DPads) );
endmodule // Core |
module CLK_Divider(n_CLK_frompad, PHI0_tocore, PHI2_fromcore, n_M2_topad);
input n_CLK_frompad;
output PHI0_tocore;
input PHI2_fromcore;
output n_M2_topad;
wire [5:0] sout;
wire rst;
wire q;
wire nq;
wire nval_4;
DivPhaseSplitter phase_split (
.n_clk(n_CLK_frompad),
.q(q),
.nq(nq) );
assign PHI0_tocore = ~sout[5];
nor (rst, PHI0_tocore, sout[4]);
DivSRBit sr0 (.q(q), .nq(nq), .rst(rst), .sin(PHI0_tocore), .sout(sout[0]));
DivSRBit sr1 (.q(q), .nq(nq), .rst(rst), .sin(sout[0]), .sout(sout[1]));
DivSRBit sr2 (.q(q), .nq(nq), .rst(rst), .sin(sout[1]), .sout(sout[2]));
DivSRBit sr3 (.q(q), .nq(nq), .rst(rst), .sin(sout[2]), .sout(sout[3]));
DivSRBit sr4 (.q(q), .nq(nq), .rst(1'b0), .sin(sout[3]), .sout(sout[4]), .n_val(nval_4));
DivSRBit sr5 (.q(q), .nq(nq), .rst(1'b0), .sin(sout[4]), .sout(sout[5]));
nor (n_M2_topad, nval_4, PHI2_fromcore);
endmodule // CLK_Divider |
module DivSRBit(q, nq, rst, sin, n_val, sout);
input q;
input nq;
input rst;
input sin;
output n_val;
output sout;
wire out_val;
dlatch in_latch (
.d(sin),
.en(q),
.nq(n_val) );
dlatch out_latch (
.d(n_val),
.en(nq),
.q(out_val) );
nor (sout, out_val, rst);
endmodule // DivSRBit |
module DivPhaseSplitter(n_clk, q, nq);
input n_clk;
output q;
output nq;
(* keep = "true" *) wire not1_out;
(* keep = "true" *) wire not2_out;
assign not1_out = ~n_clk;
assign not2_out = ~not1_out;
nor (nq, not1_out, q);
nor (q, nq, not2_out);
endmodule // DivPhaseSplitter |
module LengthCounters(
nACLK2, ACLK1,
RES, DB, n_R4015, W4015, nLFO2,
W4003, W4007, W400B, W400F,
SQA_LC, SQB_LC, TRI_LC, RND_LC,
NOSQA, NOSQB, NOTRI, NORND);
input nACLK2;
input ACLK1;
input RES;
inout [7:0] DB;
input n_R4015;
input W4015;
input nLFO2;
input W4003;
input W4007;
input W400B;
input W400F;
input SQA_LC;
input SQB_LC;
input TRI_LC;
input RND_LC;
output NOSQA;
output NOSQB;
output NOTRI;
output NORND;
wire [7:0] LC;
LengthCounter_PLA pla (
.DB(DB),
.LC_Out(LC) );
LengthCounter length_cnt [3:0] (
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.W400x_load({W400F, W400B, W4007, W4003}),
.n_R4015(n_R4015),
.W4015(W4015),
.LC(LC),
.dbit_ena({DB[3], DB[2], DB[1], DB[0]}),
.nLFO2(nLFO2),
.Carry_in({RND_LC, TRI_LC, SQB_LC, SQA_LC}),
.NotCount({NORND, NOTRI, NOSQB, NOSQA}) );
endmodule // LengthCounters |
module LengthCounter(
nACLK2, ACLK1,
RES, W400x_load, n_R4015, W4015, LC, dbit_ena, nLFO2,
Carry_in, NotCount);
input nACLK2;
input ACLK1;
input RES;
input W400x_load;
input n_R4015;
input W4015;
input [7:0] LC;
inout dbit_ena;
input nLFO2;
input Carry_in;
output NotCount;
wire STEP;
wire Carry_out;
LC_DownCounter cnt (
.Clk(ACLK1),
.Clear(RES),
.Step(STEP),
.Load(W400x_load),
.Val_in(LC),
.Carry_in(Carry_in),
.Carry_out(Carry_out) );
LC_Control ctl (
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.W400x_load(W400x_load),
.n_R4015(n_R4015),
.W4015(W4015),
.dbit_ena(dbit_ena),
.nLFO2(nLFO2),
.cout(Carry_out),
.NotCount(NotCount),
.Step(STEP) );
endmodule // LengthCounter |
module LC_Control(
nACLK2, ACLK1,
RES, W400x_load, n_R4015, W4015, dbit_ena, nLFO2, cout,
NotCount, Step);
input nACLK2;
input ACLK1;
input RES;
input W400x_load;
input n_R4015;
input W4015;
inout dbit_ena;
input nLFO2;
input cout;
output NotCount;
output Step;
wire LCDIS;
wire ena_latch_out;
wire cout_latch_out;
wire StatOut;
wire n_StatOut;
wire step_latch_out;
wire ACLK4; // Other ACLK
assign ACLK4 = ~nACLK2;
sdffre ena_ff (.d(dbit_ena), .en(W4015), .res(RES), .phi_keep(ACLK1), .nq(LCDIS));
dlatch ena_latch (.d(LCDIS), .en(ACLK1), .q(ena_latch_out));
dlatch cout_latch (.d(cout), .en(ACLK1), .q(cout_latch_out));
rsff_2_4 stat_ff (
.res1(ena_latch_out & ACLK4),
.res2(cout_latch_out & Step),
.res3(RES),
.s(W400x_load),
.q(StatOut),
.nq(n_StatOut) );
dlatch step_latch (.d(n_StatOut), .en(ACLK1), .q(step_latch_out));
assign NotCount = ~StatOut;
bustris stat_tris (.a(n_StatOut), .n_x(dbit_ena), .n_en(n_R4015));
nor (Step, step_latch_out, nLFO2);
endmodule // LC_Control |
module LC_DownCounter(Clk, Clear, Step, Load, Val_in, Carry_in, Carry_out);
input Clk;
input Clear;
input Step;
input Load;
input [7:0] Val_in;
input Carry_in;
output Carry_out;
wire [7:0] carry_chain;
wire [7:0] cnt_value; // debug
DownCounterBit lc_cnt [7:0] (
.ACLK1(Clk),
.load(Load),
.clear(Clear),
.step(Step),
.d(Val_in),
.q(cnt_value),
.cin({carry_chain[6:0], Carry_in}),
.cout(carry_chain) );
assign Carry_out = carry_chain[7];
endmodule // LC_DownCounter |
module LengthCounter_PLA(DB, LC_Out);
inout [7:0] DB;
output [7:0] LC_Out;
wire [4:0] Dec1_in;
wire [31:0] Dec1_out;
dlatch din [4:0] (.d(DB[7:3]), .en(1'b1), .q(Dec1_in));
LengthDecoder1 dec1 (.Dec1_in(Dec1_in), .Dec1_out(Dec1_out));
LengthDecoder2 dec2 (.Dec2_in(Dec1_out), .Dec2_out(LC_Out));
endmodule // LengthCounter_PLA |
module LengthDecoder1 (Dec1_in, Dec1_out);
input [4:0] Dec1_in;
output [31:0] Dec1_out;
wire [4:0] d;
wire [4:0] nd;
assign d = Dec1_in;
assign nd = ~Dec1_in;
nor (Dec1_out[0], d[0], d[1], d[2], d[3], d[4]);
nor (Dec1_out[1], d[0], nd[1], d[2], d[3], d[4]);
nor (Dec1_out[2], d[0], d[1], nd[2], d[3], d[4]);
nor (Dec1_out[3], d[0], nd[1], nd[2], d[3], d[4]);
nor (Dec1_out[4], d[0], d[1], d[2], nd[3], d[4]);
nor (Dec1_out[5], d[0], nd[1], d[2], nd[3], d[4]);
nor (Dec1_out[6], d[0], d[1], nd[2], nd[3], d[4]);
nor (Dec1_out[7], d[0], nd[1], nd[2], nd[3], d[4]);
nor (Dec1_out[8], d[0], d[1], d[2], d[3], nd[4]);
nor (Dec1_out[9], d[0], nd[1], d[2], d[3], nd[4]);
nor (Dec1_out[10], d[0], d[1], nd[2], d[3], nd[4]);
nor (Dec1_out[11], d[0], nd[1], nd[2], d[3], nd[4]);
nor (Dec1_out[12], d[0], d[1], d[2], nd[3], nd[4]);
nor (Dec1_out[13], d[0], nd[1], d[2], nd[3], nd[4]);
nor (Dec1_out[14], d[0], d[1], nd[2], nd[3], nd[4]);
nor (Dec1_out[15], d[0], nd[1], nd[2], nd[3], nd[4]);
nor (Dec1_out[16], nd[0], d[1], d[2], d[3], d[4]);
nor (Dec1_out[17], nd[0], nd[1], d[2], d[3], d[4]);
nor (Dec1_out[18], nd[0], d[1], nd[2], d[3], d[4]);
nor (Dec1_out[19], nd[0], nd[1], nd[2], d[3], d[4]);
nor (Dec1_out[20], nd[0], d[1], d[2], nd[3], d[4]);
nor (Dec1_out[21], nd[0], nd[1], d[2], nd[3], d[4]);
nor (Dec1_out[22], nd[0], d[1], nd[2], nd[3], d[4]);
nor (Dec1_out[23], nd[0], nd[1], nd[2], nd[3], d[4]);
nor (Dec1_out[24], nd[0], d[1], d[2], d[3], nd[4]);
nor (Dec1_out[25], nd[0], nd[1], d[2], d[3], nd[4]);
nor (Dec1_out[26], nd[0], d[1], nd[2], d[3], nd[4]);
nor (Dec1_out[27], nd[0], nd[1], nd[2], d[3], nd[4]);
nor (Dec1_out[28], nd[0], d[1], d[2], nd[3], nd[4]);
nor (Dec1_out[29], nd[0], nd[1], d[2], nd[3], nd[4]);
nor (Dec1_out[30], nd[0], d[1], nd[2], nd[3], nd[4]);
nor (Dec1_out[31], nd[0], nd[1], nd[2], nd[3], nd[4]);
endmodule // LengthDecoder1 |
module LengthDecoder2 (Dec2_in, Dec2_out);
input [31:0] Dec2_in;
output [7:0] Dec2_out;
wire [31:0] d;
assign d = Dec2_in;
nor (Dec2_out[7],
d[0], d[1], d[2], d[3], d[5], d[6], d[7],
d[8], d[9], d[10], d[11], d[13], d[14], d[15],
d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31] );
nor (Dec2_out[6],
d[0], d[1], d[2], d[4], d[5], d[6], d[7],
d[8], d[9], d[10], d[12], d[14], d[15],
d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31] );
nor (Dec2_out[5],
d[0], d[1], d[3], d[4], d[6], d[7],
d[8], d[9], d[11], d[13], d[14], d[15],
d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31] );
nor (Dec2_out[4],
d[0], d[2], d[3], d[6],
d[8], d[10], d[13], d[14],
d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24] );
nor (Dec2_out[3],
d[1], d[2],
d[9], d[13],
d[17], d[18], d[19], d[20],
d[25], d[26], d[27], d[28] );
nor (Dec2_out[2],
d[0], d[1], d[5], d[7],
d[8],
d[17], d[18], d[21], d[22],
d[25], d[26], d[29], d[30] );
nor (Dec2_out[1],
d[0], d[6], d[7],
//...
d[16], d[17], d[19], d[21], d[23],
d[25], d[27], d[29], d[31] );
assign Dec2_out[0] = 1'b1;
endmodule // LengthDecoder2 |
module DPCMChan (
PHI1, ACLK1, nACLK2,
RES, DB, RnW, LOCK,
W4010, W4011, W4012, W4013, W4015, n_R4015,
n_DMCAB, RUNDMC, DMCRDY, DMCINT,
DMC_Addr, DMC_Out);
input PHI1; // PHI1 is used together with the R/W core signal to determine the 6502 read cycle, because the RDY setting is ignored by the 6502 core during the write cycle (see datasheet)
input ACLK1;
input nACLK2;
input RES;
inout [7:0] DB;
input RnW; // CPU data bus mode (1: Read, 0: Write)
input LOCK; // The LOCK signal is used to temporarily suspend the sound generators so that their values can be fixed in the debug registers (2A03 only)
input W4010;
input W4011;
input W4012;
input W4013;
input W4015;
input n_R4015;
output n_DMCAB; // 0: Gain control of the address bus to read the DPCM sample
output RUNDMC; // 1: DMC is minding its own business and hijacks DMA control
output DMCRDY; // 1: DMC Ready. Used to control processor readiness (RDY)
output DMCINT; // 1: DMC interrupt is active
output [15:0] DMC_Addr; // Address for reading the DPCM sample
output [6:0] DMC_Out; // Output value for DAC
// Internal wires
wire ACLK2; // Other ACLK
wire LOOPMode; // 1: DPCM looped playback
wire n_IRQEN; // 0: Enable interrupt from DPCM
wire DSLOAD; // Load value into Sample Counter
wire DSSTEP; // Perform Sample Counter decrement
wire BLOAD; // Load value into Sample Buffer
wire BSTEP; // Perform a Sample Buffer bit shift
wire NSTEP; // Perform Sample Bit Counter increment
wire DSTEP; // Increment/decrement the DPCM Output counter
wire PCM; // Load new sample value into Sample Buffer
wire DOUT; // DPCM Out counter has finished counting
wire n_NOUT; // 0: Sample Bit Counter has finished counting
wire SOUT; // Sample Counter has finished counting
wire DFLOAD; // Frequency LFSR finished counting and reloaded itself
wire n_BOUT; // The next bit value pushed out of the Sample Buffer shift register (inverted value)
wire [7:0] DPA; // Register $4012 value
wire [7:0] DSC; // Register $4013 value
wire [3:0] Fx; // Decoder in
wire [8:0] FR; // Decoder out
// Instantiate
// Control
assign ACLK2 = ~nACLK2;
DPCM_ControlReg ctrl_reg (.ACLK1(ACLK1), .W4010(W4010), .DB(DB), .Fx(Fx), .n_IRQEN(n_IRQEN), .LOOPMode(LOOPMode) );
DPCM_Control dpcm_ctrl (
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.ACLK2(ACLK2),
.PHI1(PHI1),
.RES(RES),
.RnW(RnW),
.LOCK(LOCK),
.W4015(W4015),
.n_R4015(n_R4015),
.LOOPMode(LOOPMode),
.n_IRQEN(n_IRQEN),
.DOUT(DOUT),
.n_NOUT(n_NOUT),
.SOUT(SOUT),
.DFLOAD(DFLOAD),
.DB(DB),
.n_DMCAB(n_DMCAB),
.RUNDMC(RUNDMC),
.DMCRDY(DMCRDY),
.DMCINT(DMCINT),
.DSLOAD(DSLOAD),
.DSSTEP(DSSTEP),
.BLOAD(BLOAD),
.BSTEP(BSTEP),
.NSTEP(NSTEP),
.DSTEP(DSTEP),
.PCM(PCM) );
// Sampling
DPCM_Decoder decoder (.Fx(Fx), .FR(FR) );
DPCM_FreqLFSR lfsr (.nACLK2(nACLK2), .ACLK1(ACLK1), .ACLK2(ACLK2), .RES(RES), .FR(FR), .DFLOAD(DFLOAD) );
DPCM_SampleCounterReg scnt_reg (.ACLK1(ACLK1), .W4013(W4013), .DB(DB), .DSC(DSC) );
DPCM_SampleCounter scnt (.ACLK1(ACLK1), .RES(RES), .DSLOAD(DSLOAD), .DSSTEP(DSSTEP), .DSC(DSC), .SOUT(SOUT) );
DPCM_SampleBitCounter sbcnt (.ACLK1(ACLK1), .RES(RES), .NSTEP(NSTEP), .n_NOUT(n_NOUT) );
DPCM_SampleBuffer sbuf (.ACLK1(ACLK1), .RES(RES), .BLOAD(BLOAD), .BSTEP(BSTEP), .PCM(PCM), .DB(DB), .n_BOUT(n_BOUT) );
// Addressing & Output
DPCM_AddressReg addr_reg (.ACLK1(ACLK1), .W4012(W4012), .DB(DB), .DPA(DPA) );
DPCM_AddressCounter addr_cnt (.ACLK1(ACLK1), .RES(RES), .DSLOAD(DSLOAD), .DSSTEP(DSSTEP), .DPA(DPA), .DMC_Addr(DMC_Addr) );
DPCM_Output dpcm_out (.ACLK1(ACLK1), .RES(RES), .W4011(W4011), .CountDown(n_BOUT), .DSTEP(DSTEP), .DB(DB), .DMC_Out(DMC_Out), .DOUT(DOUT) );
endmodule // DPCMChan |
module DPCM_ControlReg (ACLK1, W4010, DB, Fx, n_IRQEN, LOOPMode);
input ACLK1;
input W4010;
inout [7:0] DB;
output [3:0] Fx;
output n_IRQEN;
output LOOPMode;
RegisterBit f_reg [3:0] (.ACLK1(ACLK1), .ena(W4010), .d(DB[3:0]), .q(Fx) );
RegisterBit loop_reg (.ACLK1(ACLK1), .ena(W4010), .d(DB[6]), .q(LOOPMode) );
RegisterBit irq_reg (.ACLK1(ACLK1), .ena(W4010), .d(DB[7]), .nq(n_IRQEN) );
endmodule // DPCM_ControlReg |
module DPCM_Control( nACLK2, ACLK1, ACLK2, PHI1, RES, RnW, LOCK, W4015, n_R4015, LOOPMode, n_IRQEN, DOUT, n_NOUT, SOUT, DFLOAD, DB,
n_DMCAB, RUNDMC, DMCRDY, DMCINT, DSLOAD, DSSTEP, BLOAD, BSTEP, NSTEP, DSTEP, PCM );
input nACLK2;
input ACLK1;
input ACLK2;
input PHI1;
input RES;
input RnW;
input LOCK;
input W4015;
input n_R4015;
input LOOPMode;
input n_IRQEN;
input DOUT;
input n_NOUT;
input SOUT;
input DFLOAD;
inout [7:0] DB;
output n_DMCAB;
output RUNDMC;
output DMCRDY;
output DMCINT;
output DSLOAD;
output DSSTEP;
output BLOAD;
output BSTEP;
output NSTEP;
output DSTEP;
output PCM;
// Internal temp wires
wire ED1;
wire ED2;
wire DMC1;
wire DMC2;
wire CTRL1;
wire CTRL2;
DPCM_IntControl int_ctrl (.RES(RES), .W4015(W4015), .n_R4015(n_R4015), .n_IRQEN(n_IRQEN), .AssertInt(ED1), .DB(DB), .DMCINT(DMCINT) );
DPCM_EnableControl enable_ctrl (.ACLK1(ACLK1), .RES(RES), .W4015(W4015), .n_R4015(n_R4015), .LOOPMode(LOOPMode), .PCMDone(DMC1), .SOUT(SOUT), .DB(DB), .ED1(ED1), .DMC2(DMC2), .ED2(ED2) );
DPCM_DMAControl dma_ctrl (.nACLK2(nACLK2), .ACLK1(ACLK1), .ACLK2(ACLK2), .PHI1(PHI1), .RnW(RnW), .RES(RES), .nDMAStop(CTRL1), .nDMCEnableDelay(CTRL2), .DMCRDY(DMCRDY), .RUNDMC(RUNDMC), .n_DMCAB(n_DMCAB) );
DPCM_SampleCounterControl scnt_ctrl (.nACLK2(nACLK2), .ACLK1(ACLK1), .ACLK2(ACLK2), .PCMDone(DMC1), .DMCFinish(DMC2), .DMCEnable(ED2), .DFLOAD(DFLOAD), .DSLOAD(DSLOAD), .DSSTEP(DSSTEP), .NSTEP(NSTEP), .CTRL2(CTRL2) );
DPCM_SampleBufferControl sbuf_ctrl (.nACLK2(nACLK2), .ACLK1(ACLK1), .ACLK2(ACLK2), .PHI1(PHI1), .RES(RES), .LOCK(LOCK), .DFLOAD(DFLOAD), .DOUT(DOUT), .n_NOUT(n_NOUT), .n_DMCAB(n_DMCAB), .BLOAD(BLOAD), .BSTEP(BSTEP), .PCM(PCM), .DSTEP(DSTEP), .DMC1(DMC1), .CTRL1(CTRL1) );
endmodule // DPCMControl |
module DPCM_IntControl(RES, W4015, n_R4015, n_IRQEN, AssertInt, DB, DMCINT);
input RES;
input W4015;
input n_R4015;
input n_IRQEN;
input AssertInt;
inout [7:0] DB;
output DMCINT;
wire int_ff_nq;
rsff_2_4 int_ff (.res1(W4015), .res2(n_IRQEN), .res3(RES), .s(AssertInt), .nq(int_ff_nq) );
bustris int_stat (.a(int_ff_nq), .n_x(DB[7]), .n_en(n_R4015) );
nor (DMCINT, int_ff_nq, n_IRQEN);
endmodule // DPCMIntControl |
module DPCM_EnableControl(ACLK1, RES, W4015, n_R4015, LOOPMode, PCMDone, SOUT, DB, ED1, DMC2, ED2);
input ACLK1;
input RES;
input W4015;
input n_R4015;
input LOOPMode;
input PCMDone;
input SOUT;
inout [7:0] DB;
output ED1;
output DMC2;
output ED2;
wire sout_latch_nq;
wire ena_ff_nq;
dlatch sout_latch (.d(SOUT), .en(ACLK1), .q(DMC2), .nq(sout_latch_nq) );
RegisterBitRes2 ena_ff (.ACLK1(ACLK1), .ena(W4015), .d(DB[4]), .res1(ED1), .res2(RES), .q(ED2), .nq(ena_ff_nq) );
nor (ED1, LOOPMode, sout_latch_nq, ~PCMDone);
bustris ena_stat (.a(ena_ff_nq), .n_x(DB[4]), .n_en(n_R4015) );
endmodule // DPCMEnableControl |
module DPCM_DMAControl(nACLK2, ACLK1, ACLK2, PHI1, RnW, RES, nDMAStop, nDMCEnableDelay, DMCRDY, RUNDMC, n_DMCAB);
input nACLK2;
input ACLK1;
input ACLK2;
input PHI1;
input RnW;
input RES;
input nDMAStop;
input nDMCEnableDelay;
output DMCRDY;
output RUNDMC;
output n_DMCAB;
wire DMAStart;
wire run_latch1_q;
wire run_latch1_nq;
wire start_set;
wire rdy_ff_nq;
dlatch run_latch1 (.d(DMAStart), .en(ACLK2), .q(run_latch1_q), .nq(run_latch1_nq) );
dlatch run_latch2 (.d(run_latch1_nq), .en(ACLK1), .nq(RUNDMC) );
assign start_set = ~( ~(~PHI1 & RnW) | nDMCEnableDelay | ~nDMAStop );
rsff_2_4 start_ff (.res1(nDMCEnableDelay), .res2(RES), .res3(~nDMAStop), .s(start_set), .q(DMAStart) );
rsff rdy_ff (.r(run_latch1_q & ACLK1), .s(ACLK2), .q(n_DMCAB), .nq(rdy_ff_nq) );
nor (DMCRDY, DMAStart, rdy_ff_nq);
endmodule // DPCM_DMAControl |
module DPCM_SampleCounterControl(nACLK2, ACLK1, ACLK2, PCMDone, DMCFinish, DMCEnable, DFLOAD, DSLOAD, DSSTEP, NSTEP, CTRL2);
input nACLK2;
input ACLK1;
input ACLK2;
input PCMDone;
input DMCFinish;
input DMCEnable;
input DFLOAD;
output DSLOAD;
output DSSTEP;
output NSTEP;
output CTRL2;
wire DMC3;
wire en_latch1_nq;
wire en_latch2_nq;
wire en_latch3_q;
dlatch en_latch1 (.d(DMCEnable), .en(ACLK1), .nq(en_latch1_nq) );
dlatch en_latch2 (.d(en_latch1_nq), .en(ACLK2), .nq(en_latch2_nq) );
dlatch en_latch3 (.d(en_latch2_nq), .en(ACLK1), .q(en_latch3_q), .nq(CTRL2) );
nor (DMC3, nACLK2, en_latch1_nq, en_latch3_q);
assign NSTEP = ~(~DFLOAD);
assign DSLOAD = ~(~((DMCFinish & PCMDone) | DMC3));
assign DSSTEP = ~(~PCMDone | DMC3 | DMCFinish);
endmodule // DPCM_SampleCounterControl |
module DPCM_SampleBufferControl(nACLK2, ACLK1, ACLK2, PHI1, RES, LOCK, DFLOAD, DOUT, n_NOUT, n_DMCAB, BLOAD, BSTEP, PCM, DSTEP, DMC1, CTRL1);
input nACLK2;
input ACLK1;
input ACLK2;
input PHI1;
input RES;
input LOCK;
input DFLOAD;
input DOUT;
input n_NOUT;
input n_DMCAB;
output BLOAD;
output BSTEP;
output PCM;
output DSTEP;
output DMC1;
output CTRL1;
wire n_DFLOAD;
wire step_ff_nq;
wire stop_ff_q;
wire pcm_ff_nq;
wire dout_latch_q;
wire dstep_latch_q;
wire stop_latch_nq;
wire pcm_latch_q;
assign n_DFLOAD = ~DFLOAD;
rsff_2_3 step_ff (.res1(~(~stop_latch_nq | n_DFLOAD | n_NOUT)), .res2(RES), .s(BLOAD), .nq(step_ff_nq) );
rsff_2_3 stop_ff (.res1(BLOAD), .res2(RES), .s(PCM), .q(stop_ff_q), .nq(CTRL1) );
rsff_2_3 pcm_ff (.res1(DMC1), .res2(RES), .s(PCM), .nq(pcm_ff_nq) );
dlatch dout_latch (.d(DOUT), .en(ACLK1), .q(dout_latch_q) );
dlatch dstep_latch (.d(step_ff_nq), .en(ACLK1), .q(dstep_latch_q) );
dlatch stop_latch (.d(stop_ff_q), .en(ACLK1), .nq(stop_latch_nq) );
dlatch pcm_latch (.d(pcm_ff_nq), .en(ACLK1), .q(pcm_latch_q) );
nor (PCM, PHI1, n_DMCAB);
nor (DMC1, pcm_latch_q, ~ACLK2);
nor (DSTEP, dout_latch_q, dstep_latch_q, n_DFLOAD, LOCK);
nor (BLOAD, stop_latch_nq, n_DFLOAD, n_NOUT);
nor (BSTEP, n_DFLOAD, ~n_NOUT);
endmodule // DPCM_SampleBufferControl |
module DPCM_Decoder (Fx, FR);
input [3:0] Fx;
output [8:0] FR;
wire [15:0] Dec1_out;
DPCM_Decoder1 dec1 (.Dec1_in(Fx), .Dec1_out(Dec1_out) );
DPCM_Decoder2 dec2 (.Dec2_in(Dec1_out), .Dec2_out(FR) );
endmodule // DPCM_Decoder |
module DPCM_Decoder1 (Dec1_in, Dec1_out);
input [3:0] Dec1_in;
output [15:0] Dec1_out;
wire [3:0] F;
wire [3:0] nF;
assign F = Dec1_in;
assign nF = ~Dec1_in;
nor (Dec1_out[0], F[0], F[1], F[2], F[3]);
nor (Dec1_out[1], nF[0], F[1], F[2], F[3]);
nor (Dec1_out[2], F[0], nF[1], F[2], F[3]);
nor (Dec1_out[3], nF[0], nF[1], F[2], F[3]);
nor (Dec1_out[4], F[0], F[1], nF[2], F[3]);
nor (Dec1_out[5], nF[0], F[1], nF[2], F[3]);
nor (Dec1_out[6], F[0], nF[1], nF[2], F[3]);
nor (Dec1_out[7], nF[0], nF[1], nF[2], F[3]);
nor (Dec1_out[8], F[0], F[1], F[2], nF[3]);
nor (Dec1_out[9], nF[0], F[1], F[2], nF[3]);
nor (Dec1_out[10], F[0], nF[1], F[2], nF[3]);
nor (Dec1_out[11], nF[0], nF[1], F[2], nF[3]);
nor (Dec1_out[12], F[0], F[1], nF[2], nF[3]);
nor (Dec1_out[13], nF[0], F[1], nF[2], nF[3]);
nor (Dec1_out[14], F[0], nF[1], nF[2], nF[3]);
nor (Dec1_out[15], nF[0], nF[1], nF[2], nF[3]);
endmodule // DPCM_Decoder1 |
module DPCM_Decoder2 (Dec2_in, Dec2_out);
input [15:0] Dec2_in;
output [8:0] Dec2_out;
wire [15:0] d;
assign d = Dec2_in;
nor (Dec2_out[0], d[1], d[4], d[9], d[14], d[15]);
nor (Dec2_out[1], d[6], d[7], d[8], d[9], d[10], d[11], d[12], d[13]);
nor (Dec2_out[2], d[0], d[1], d[2], d[3], d[7], d[8], d[10], d[11], d[13]);
nor (Dec2_out[3], d[0], d[2], d[7], d[10], d[15]);
nor (Dec2_out[4], d[1], d[2], d[4], d[8], d[12], d[13], d[14]);
nor (Dec2_out[5], d[1], d[2], d[3], d[7], d[8], d[9], d[12], d[13], d[14], d[15]);
nor (Dec2_out[6], d[1], d[5], d[8], d[12], d[13], d[14]);
nor (Dec2_out[7], d[0], d[2], d[5], d[6], d[8], d[15]);
nor (Dec2_out[8], d[1], d[3], d[5], d[6], d[8], d[9], d[10], d[11], d[12]);
endmodule // DPCM_Decoder2 |
module DPCM_FreqLFSR (nACLK2, ACLK1, ACLK2, RES, FR, DFLOAD);
input nACLK2;
input ACLK1;
input ACLK2;
input RES;
input [8:0] FR;
output DFLOAD;
wire feedback;
wire DFSTEP;
wire [8:0] sout;
wire nor1_out;
wire nor2_out;
wire nor3_out;
assign feedback = ~((sout[0] & sout[4]) | RES | ~(sout[0] | sout[4] | nor1_out));
assign nor3_out = ~(RES | ~nor2_out);
assign DFLOAD = ~(~ACLK2 | ~nor3_out);
assign DFSTEP = ~(~ACLK2 | nor3_out);
nor (nor1_out, sout[0], sout[1], sout[2], sout[3], sout[4], sout[5], sout[6], sout[7], sout[8]);
nor (nor2_out, ~sout[0], sout[1], sout[2], sout[3], sout[4], sout[5], sout[6], sout[7], sout[8]);
DPCM_LFSRBit lfsr [8:0] (.ACLK1(ACLK1), .load(DFLOAD), .step(DFSTEP), .val(FR), .sin({feedback,sout[8:1]}), .sout(sout) );
endmodule // DPCM_FreqLFSR |
module DPCM_LFSRBit (ACLK1, load, step, val, sin, sout);
input ACLK1;
input load;
input step;
input val;
input sin;
output sout;
wire d;
wire in_latch_nq;
assign d = load ? val : (step ? sin : 1'bz);
dlatch in_latch (.d(d), .en(1'b1), .nq(in_latch_nq) );
dlatch out_latch (.d(in_latch_nq), .en(ACLK1), .nq(sout) );
endmodule // DPCM_LFSRBit |
module DPCM_SampleCounterReg (ACLK1, W4013, DB, DSC);
input ACLK1;
input W4013;
inout [7:0] DB;
output [7:0] DSC;
RegisterBit scnt_reg [7:0] (.ACLK1(ACLK1), .ena(W4013), .d(DB[7:0]), .q(DSC[7:0]) );
endmodule // DPCM_SampleCounterReg |
module DPCM_SampleCounter (ACLK1, RES, DSLOAD, DSSTEP, DSC, SOUT);
input ACLK1;
input RES;
input DSLOAD;
input DSSTEP;
input [7:0] DSC;
output SOUT;
wire [11:0] cout;
DownCounterBit cnt [11:0] (.ACLK1(ACLK1), .d({DSC[7:0],4'b0000}), .load(DSLOAD), .clear(RES), .step(DSSTEP), .cin({cout[10:0],1'b1}), .cout(cout) );
assign SOUT = cout[11];
endmodule // DPCM_SampleCounter |
module DPCM_SampleBitCounter (ACLK1, RES, NSTEP, n_NOUT);
input ACLK1;
input RES;
input NSTEP;
output n_NOUT;
wire [2:0] cout;
CounterBit cnt [2:0] (.ACLK1(ACLK1), .d(3'b000), .load(RES), .clear(RES), .step(NSTEP), .cin({cout[1:0],1'b1}), .cout(cout) );
dlatch nout_latch (.d(cout[2]), .en(ACLK1), .nq(n_NOUT));
endmodule // DPCM_SampleBitCounter |
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