module
stringlengths 21
82.9k
|
|---|
module altera_modular_adc_control_avrg_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [11:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [11:0] q;
wire sub_wire0;
wire sub_wire1;
wire [11:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [11:0] q = sub_wire2[11:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "MAX 10",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule |
module fiftyfivenm_adcblock_top_wrapper(
//reset, // reset
chsel, // 5-bits channel selection.
soc, // signal Start-of-Conversion to ADC
eoc, // signal end of conversion. Data can be latched on the positive edge of clkout_adccore after this signal becomes high. EOC becomes low at every positive edge of the clkout_adccore signal.
dout, // 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge
usr_pwd, // User Power Down during run time. 0 = Power Up; 1 = Power Down.
tsen, // 0 = Normal Mode; 1 = Temperature Sensing Mode.
clkout_adccore, // Output clock from the clock divider
clkin_from_pll_c0 // Clock source from PLL1 c-counter[0] at BL corner or PLL3 c-counter[0] at TL corner
//dout_ch // Indicator to tell that current dout data is for which channel
);
// *******************************************************************************************************
// ** PARAMETERS
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// WRAPPED PARAMETERS USED BY fiftyfivenm_adcblock
// -------------------------------------------------------------------------------------------------------
// 3-bits 1st stage clock divider.
// 0..5 = DIV by 1/2/10/20/40/80;
// 6..7 = invalid
parameter clkdiv = 1;
// 2nd stage clock divider.
// 0 = DIV by 10;
// 1 = DIV by 20
parameter tsclkdiv = 0;
// 0 = Use 1st stage clock divider when TSEN.
// 1 = Use 2nd stage clock divider when TSEN.
parameter tsclksel = 0;
// 2-bits To enable the R ladder for the prescalar input channels.
// 00 = disable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
// 01 = enable prescalar for CH8 only
// 10 = enable prescalar for CH16 only (CH8 for device with 2nd ADC)
// 11 = enable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
// please note that this is not supported in VR mode
parameter prescalar = 0;
// Reference voltage selection for ADC.
// 0 = external;
// 1 = internal VCCADC_2P5
parameter refsel = 0;
// -------------------------------------------------------------------------------------------------------
// WRAPPED PARAMETERS USED BY both chsel_code_converter_sw_to_hw and fiftyfivenm_adcblock
// -------------------------------------------------------------------------------------------------------
// Ordering Part Number 10MXX... code
parameter device_partname_fivechar_prefix = "10M08"; // Valid options = 04, 08, 16, 25, 40, 50
// Some part have two ADC, instantiate which ADC? 1st or 2nd?
parameter is_this_first_or_second_adc = 1; // Valid options = 1 or 2
// 16 bits to indicate whether each of the dual purpose analog input pin (ADCIN) is in use or not.
// 1 bit to indicate whether dedicated analog input pin (ANAIN) is in use or not (bit 16)
parameter analog_input_pin_mask = 17'h0;
// Power Down. Use to disable the ADC during compilation time if no ADC is in use.
parameter hard_pwd = 0;
// Logic simulation parameters which only affects simulation behavior
parameter enable_usr_sim = 0;
parameter reference_voltage_sim = 65536;
parameter simfilename_ch0 = "simfilename_ch0";
parameter simfilename_ch1 = "simfilename_ch1";
parameter simfilename_ch2 = "simfilename_ch2";
parameter simfilename_ch3 = "simfilename_ch3";
parameter simfilename_ch4 = "simfilename_ch4";
parameter simfilename_ch5 = "simfilename_ch5";
parameter simfilename_ch6 = "simfilename_ch6";
parameter simfilename_ch7 = "simfilename_ch7";
parameter simfilename_ch8 = "simfilename_ch8";
parameter simfilename_ch9 = "simfilename_ch9";
parameter simfilename_ch10 = "simfilename_ch10";
parameter simfilename_ch11 = "simfilename_ch11";
parameter simfilename_ch12 = "simfilename_ch12";
parameter simfilename_ch13 = "simfilename_ch13";
parameter simfilename_ch14 = "simfilename_ch14";
parameter simfilename_ch15 = "simfilename_ch15";
parameter simfilename_ch16 = "simfilename_ch16";
// *******************************************************************************************************
// ** INPUTS
// *******************************************************************************************************
//input reset; // reset
input clkin_from_pll_c0; // Clock source from PLL1 c-counter[0] at BL corner or PLL3 c-counter[0] at TL corner
input soc; // signal Start-of-Conversion to ADC
input usr_pwd; // User Power Down during run time. 0 = Power Up; 1 = Power Down.
input tsen; // 0 = Normal Mode; 1 = Temperature Sensing Mode.
input [4:0] chsel; // 5-bits channel selection.
// *******************************************************************************************************
// ** OUTPUTS
// *******************************************************************************************************
output clkout_adccore; // Output clock from the clock divider
output eoc; // signal end of conversion. Data can be latched on the positive edge of clkout_adccore after this signal becomes high. EOC becomes low at every positive edge of the clkout_adccore signal.
output [11:0] dout; // 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge
//output [4:0] dout_ch; // Indicator to tell that current dout data is for which channel (clone of EOC)
// *******************************************************************************************************
// ** INTERNAL NET AND REGISTER DATA TYPE (internal signals used within this module)
// *******************************************************************************************************
//reg [4:0] prev1_chsel; // Backup chsel, because the data available at EOC is always for chsel value at previous EOC
//reg [4:0] prev2_chsel; // Data for previous channel is further delay by 1 clkout_adccore due to adcblock_primitive_wrapper have a register clocked by clkout_adccore
//reg [4:0] dout_ch; // Indicator to tell that current dout data is for which channel
// chsel_to_hw is the output after port mapping will be wired into chsel of fiftyfivenm_adcblock
wire [4:0] chsel_to_hw;
// *******************************************************************************************************
// ** INITIALIZATION
// *******************************************************************************************************
//initial begin
//prev1_chsel = 0;
//prev2_chsel = 0;
//dout_ch = 0;
//end
// *******************************************************************************************************
// ** MAIN CODE
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.00: Instantiate Software to Hardware Channel Mapping module
// -------------------------------------------------------------------------------------------------------
chsel_code_converter_sw_to_hw decoder(
// The 5-bits chsel input port are wired to chsel_from_sw for conversion
.chsel_from_sw(chsel),
// The chsel_code_converter_sw_to_hw output chsel_to_hw which will be wired into fiftyfivenm_adcblock
.chsel_to_hw(chsel_to_hw)
);
defparam decoder.device_partname_fivechar_prefix = device_partname_fivechar_prefix;
defparam decoder.is_this_first_or_second_adc = is_this_first_or_second_adc;
// -------------------------------------------------------------------------------------------------------
// 2.00: Instantiate ADC Block primitive
// -------------------------------------------------------------------------------------------------------
fiftyfivenm_adcblock_primitive_wrapper adcblock_instance(
// .reset (reset),
.chsel (chsel_to_hw),
.soc (soc),
.eoc (eoc),
.dout (dout),
.usr_pwd (usr_pwd),
.tsen (tsen),
.clkout_adccore (clkout_adccore),
.clkin_from_pll_c0(clkin_from_pll_c0)
);
defparam adcblock_instance.clkdiv = clkdiv;
defparam adcblock_instance.tsclkdiv = tsclkdiv;
defparam adcblock_instance.tsclksel = tsclksel;
defparam adcblock_instance.prescalar = prescalar;
defparam adcblock_instance.refsel = refsel;
defparam adcblock_instance.device_partname_fivechar_prefix = device_partname_fivechar_prefix;
defparam adcblock_instance.is_this_first_or_second_adc = is_this_first_or_second_adc;
defparam adcblock_instance.analog_input_pin_mask = analog_input_pin_mask;
defparam adcblock_instance.hard_pwd = hard_pwd;
defparam adcblock_instance.enable_usr_sim = enable_usr_sim;
defparam adcblock_instance.reference_voltage_sim = reference_voltage_sim;
defparam adcblock_instance.simfilename_ch0 = simfilename_ch0;
defparam adcblock_instance.simfilename_ch1 = simfilename_ch1;
defparam adcblock_instance.simfilename_ch2 = simfilename_ch2;
defparam adcblock_instance.simfilename_ch3 = simfilename_ch3;
defparam adcblock_instance.simfilename_ch4 = simfilename_ch4;
defparam adcblock_instance.simfilename_ch5 = simfilename_ch5;
defparam adcblock_instance.simfilename_ch6 = simfilename_ch6;
defparam adcblock_instance.simfilename_ch7 = simfilename_ch7;
defparam adcblock_instance.simfilename_ch8 = simfilename_ch8;
defparam adcblock_instance.simfilename_ch9 = simfilename_ch9;
defparam adcblock_instance.simfilename_ch10 = simfilename_ch10;
defparam adcblock_instance.simfilename_ch11 = simfilename_ch11;
defparam adcblock_instance.simfilename_ch12 = simfilename_ch12;
defparam adcblock_instance.simfilename_ch13 = simfilename_ch13;
defparam adcblock_instance.simfilename_ch14 = simfilename_ch14;
defparam adcblock_instance.simfilename_ch15 = simfilename_ch15;
defparam adcblock_instance.simfilename_ch16 = simfilename_ch16;
// -------------------------------------------------------------------------------------------------------
// 4.00: Update dout_ch to tell current dout data is for which channel
// -------------------------------------------------------------------------------------------------------
// DESCRIBE THE ALWAYS BLOCK:
// output previously backed-up chsel to dout_ch
// backup existing chsel to later use
// always @ (posedge clkout_adccore or posedge reset)
// begin
// if (reset)
// begin
// dout_ch <= 0;
// prev2_chsel <= 0;
// prev1_chsel <= 0;
// end
// else
// begin
// dout_ch <= prev2_chsel;
// prev2_chsel <= prev1_chsel;
// prev1_chsel <= chsel;
// end //end-if
// end
// *******************************************************************************************************
// ** END OF MODULE
// *******************************************************************************************************
endmodule |
module myadc_modular_adc_0 (
input wire clock_clk, // clock.clk
input wire reset_sink_reset_n, // reset_sink.reset_n
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire command_valid, // command.valid
input wire [4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
output wire response_valid, // response.valid
output wire [4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
altera_modular_adc_control #(
.clkdiv (2),
.tsclkdiv (1),
.tsclksel (1),
.hard_pwd (0),
.prescalar (0),
.refsel (1),
.device_partname_fivechar_prefix ("10M08"),
.is_this_first_or_second_adc (1),
.analog_input_pin_mask (65536),
.dual_adc_mode (0),
.enable_usr_sim (0),
.reference_voltage_sim (65536),
.simfilename_ch0 (""),
.simfilename_ch1 (""),
.simfilename_ch2 (""),
.simfilename_ch3 (""),
.simfilename_ch4 (""),
.simfilename_ch5 (""),
.simfilename_ch6 (""),
.simfilename_ch7 (""),
.simfilename_ch8 (""),
.simfilename_ch9 (""),
.simfilename_ch10 (""),
.simfilename_ch11 (""),
.simfilename_ch12 (""),
.simfilename_ch13 (""),
.simfilename_ch14 (""),
.simfilename_ch15 (""),
.simfilename_ch16 ("")
) control_internal (
.clk (clock_clk), // clock.clk
.cmd_valid (command_valid), // command.valid
.cmd_channel (command_channel), // .channel
.cmd_sop (command_startofpacket), // .startofpacket
.cmd_eop (command_endofpacket), // .endofpacket
.cmd_ready (command_ready), // .ready
.rst_n (reset_sink_reset_n), // reset_sink.reset_n
.rsp_valid (response_valid), // response.valid
.rsp_channel (response_channel), // .channel
.rsp_data (response_data), // .data
.rsp_sop (response_startofpacket), // .startofpacket
.rsp_eop (response_endofpacket), // .endofpacket
.clk_in_pll_c0 (adc_pll_clock_clk), // adc_pll_clock.clk
.clk_in_pll_locked (adc_pll_locked_export), // conduit_end.export
.sync_valid (), // (terminated)
.sync_ready (1'b0) // (terminated)
);
endmodule |
module chsel_code_converter_sw_to_hw (
chsel_from_sw, // 5-bits channel selection.
chsel_to_hw // 5-bits channel selection.
);
// *******************************************************************************************************
// ** PARAMETERS
// *******************************************************************************************************
// Ordering Part Number 10MXX... code
parameter device_partname_fivechar_prefix = "10M08"; // Valid options = 04, 08, 16, 25, 40, 50
// Some part have two ADC, instantiate which ADC? 1st or 2nd?
parameter is_this_first_or_second_adc = 1; // Valid options = 1 or 2
// .......................................................................................................
// DESCRIBE THE LOCALPARAM CONSTANT:
// Actual Hardware map CHSEL[4:0] out of sequential order to different channel pad due to route-ability,
// Soft IP will have S/W mapping to translate it back to sequential order from user perspective (PAD label)
// 10M04/08/16 hardware equivalent chsel code for a particular software chsel code
localparam variant_08n16_hw_chsel_code_for_sw_temp_code_10001 = 5'b00000;
localparam variant_08n16_hw_chsel_code_for_sw_ch00_code_00000 = 5'b00011;
localparam variant_08n16_hw_chsel_code_for_sw_ch01_code_00001 = 5'b00100;
localparam variant_08n16_hw_chsel_code_for_sw_ch02_code_00010 = 5'b00110;
localparam variant_08n16_hw_chsel_code_for_sw_ch03_code_00011 = 5'b01010;
localparam variant_08n16_hw_chsel_code_for_sw_ch04_code_00100 = 5'b01100;
localparam variant_08n16_hw_chsel_code_for_sw_ch05_code_00101 = 5'b10000;
localparam variant_08n16_hw_chsel_code_for_sw_ch06_code_00110 = 5'b01110;
localparam variant_08n16_hw_chsel_code_for_sw_ch07_code_00111 = 5'b01101;
localparam variant_08n16_hw_chsel_code_for_sw_ch08_code_01000 = 5'b00010;
localparam variant_08n16_hw_chsel_code_for_sw_ch09_code_01001 = 5'b00101;
localparam variant_08n16_hw_chsel_code_for_sw_ch10_code_01010 = 5'b01001;
localparam variant_08n16_hw_chsel_code_for_sw_ch11_code_01011 = 5'b10001;
localparam variant_08n16_hw_chsel_code_for_sw_ch12_code_01100 = 5'b01111;
localparam variant_08n16_hw_chsel_code_for_sw_ch13_code_01101 = 5'b01000;
localparam variant_08n16_hw_chsel_code_for_sw_ch14_code_01110 = 5'b00111;
localparam variant_08n16_hw_chsel_code_for_sw_ch15_code_01111 = 5'b01011;
localparam variant_08n16_hw_chsel_code_for_sw_ch16_code_10000 = 5'b00001;
// First ADC of 10M25/40/50 hardware equivalent chsel code for a particular software chsel code
localparam dual_first_adc_hw_chsel_code_for_sw_temp_code_10001 = 5'b00000;
localparam dual_first_adc_hw_chsel_code_for_sw_ch00_code_00000 = 5'b00011;
localparam dual_first_adc_hw_chsel_code_for_sw_ch01_code_00001 = 5'b00100;
localparam dual_first_adc_hw_chsel_code_for_sw_ch02_code_00010 = 5'b00110;
localparam dual_first_adc_hw_chsel_code_for_sw_ch03_code_00011 = 5'b01010;
localparam dual_first_adc_hw_chsel_code_for_sw_ch04_code_00100 = 5'b01100;
localparam dual_first_adc_hw_chsel_code_for_sw_ch05_code_00101 = 5'b10000;
localparam dual_first_adc_hw_chsel_code_for_sw_ch06_code_00110 = 5'b01110;
localparam dual_first_adc_hw_chsel_code_for_sw_ch07_code_00111 = 5'b01101;
localparam dual_first_adc_hw_chsel_code_for_sw_ch08_code_01000 = 5'b00010;
// Second ADC of 10M25/40/50 hardware equivalent chsel code for a particular software chsel code
// Note that: Second ADC do not support internal temperature sensor.
// However internal temperature sensor mapping for ADC2 is later included for dual adc mode
// When in dual adc mode, if ADC1 is operating in TSD mode, ADC2 will perform a dummy TSD mode as well
localparam dual_second_adc_hw_chsel_code_for_sw_temp_code_10001 = 5'b00000;
localparam dual_second_adc_hw_chsel_code_for_sw_ch00_code_00000 = 5'b00011;
localparam dual_second_adc_hw_chsel_code_for_sw_ch01_code_00001 = 5'b00101;
localparam dual_second_adc_hw_chsel_code_for_sw_ch02_code_00010 = 5'b01001;
localparam dual_second_adc_hw_chsel_code_for_sw_ch03_code_00011 = 5'b10001;
localparam dual_second_adc_hw_chsel_code_for_sw_ch04_code_00100 = 5'b01111;
localparam dual_second_adc_hw_chsel_code_for_sw_ch05_code_00101 = 5'b01000;
localparam dual_second_adc_hw_chsel_code_for_sw_ch06_code_00110 = 5'b00111;
localparam dual_second_adc_hw_chsel_code_for_sw_ch07_code_00111 = 5'b01011;
localparam dual_second_adc_hw_chsel_code_for_sw_ch08_code_01000 = 5'b00001;
// *******************************************************************************************************
// ** INPUTS
// *******************************************************************************************************
input [4:0] chsel_from_sw; // 5-bits channel selection number from software perspective
// *******************************************************************************************************
// ** OUTPUTS
// *******************************************************************************************************
output [4:0] chsel_to_hw; // 5-bits channel selection code to be send to ADC Hard IP
// *******************************************************************************************************
// ** EXTERNAL NET AND REGISTER DATA TYPE (with input / output / inout ports)
// *******************************************************************************************************
reg [4:0] chsel_to_hw; // 5-bits channel selection code to be send to ADC Hard IP
// *******************************************************************************************************
// ** MAIN CODE
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.00: Channel Mapping
// -------------------------------------------------------------------------------------------------------
// DESCRIBE THE ALWAYS BLOCK:
// This block execute on divided internal clock
// Its job is mainly to determine what value to be set for the digital_out and eoc_rise
always @(chsel_from_sw)
begin
// DESCRIBE THE CASE STATEMENT:
// Output the equivalent chsel code for hardware
if ((device_partname_fivechar_prefix == "10M04") || (device_partname_fivechar_prefix == "10M08") || (device_partname_fivechar_prefix == "10M16"))
begin
// COMMENT FOR THIS BRANCH:
// 10M08/04 channel mapping
case(chsel_from_sw)
5'b10001: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_temp_code_10001;
5'b00000: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch00_code_00000;
5'b00001: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch01_code_00001;
5'b00010: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch02_code_00010;
5'b00011: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch03_code_00011;
5'b00100: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch04_code_00100;
5'b00101: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch05_code_00101;
5'b00110: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch06_code_00110;
5'b00111: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch07_code_00111;
5'b01000: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch08_code_01000;
5'b01001: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch09_code_01001;
5'b01010: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch10_code_01010;
5'b01011: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch11_code_01011;
5'b01100: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch12_code_01100;
5'b01101: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch13_code_01101;
5'b01110: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch14_code_01110;
5'b01111: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch15_code_01111;
5'b10000: chsel_to_hw <= variant_08n16_hw_chsel_code_for_sw_ch16_code_10000;
default : chsel_to_hw <= 5'b11111;
endcase
end
else
if ((is_this_first_or_second_adc == 1) &&
((device_partname_fivechar_prefix == "10M25") ||
(device_partname_fivechar_prefix == "10M40") ||
(device_partname_fivechar_prefix == "10M50")))
begin
// COMMENT FOR THIS BRANCH:
// First ADC of 10M25/40/50 channel mapping
case(chsel_from_sw)
5'b10001: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_temp_code_10001;
5'b00000: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch00_code_00000;
5'b00001: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch01_code_00001;
5'b00010: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch02_code_00010;
5'b00011: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch03_code_00011;
5'b00100: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch04_code_00100;
5'b00101: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch05_code_00101;
5'b00110: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch06_code_00110;
5'b00111: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch07_code_00111;
5'b01000: chsel_to_hw <= dual_first_adc_hw_chsel_code_for_sw_ch08_code_01000;
default : chsel_to_hw <= 5'b11111;
endcase
end
else
if ((is_this_first_or_second_adc == 2) &&
((device_partname_fivechar_prefix == "10M25") ||
(device_partname_fivechar_prefix == "10M40") ||
(device_partname_fivechar_prefix == "10M50")))
begin
// COMMENT FOR THIS BRANCH:
// Second ADC of 10M25/40/50 channel mapping
case(chsel_from_sw)
5'b10001: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_temp_code_10001;
5'b00000: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch00_code_00000;
5'b00001: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch01_code_00001;
5'b00010: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch02_code_00010;
5'b00011: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch03_code_00011;
5'b00100: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch04_code_00100;
5'b00101: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch05_code_00101;
5'b00110: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch06_code_00110;
5'b00111: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch07_code_00111;
5'b01000: chsel_to_hw <= dual_second_adc_hw_chsel_code_for_sw_ch08_code_01000;
default : chsel_to_hw <= 5'b11111;
endcase
end
end // end always
// *******************************************************************************************************
// ** END OF MODULE
// *******************************************************************************************************
endmodule |
module altera_modular_adc_sequencer_csr (
input clk,
input rst_n,
input addr,
input read,
input write,
input [31:0] writedata,
input clr_run,
output reg [31:0] readdata,
output reg run,
output reg sw_clr_run,
output con_mode,
output single_mode,
output recab_mode
);
reg [2:0] mode;
wire cmd_addr;
wire cmd_wr_en;
wire cmd_rd_en;
wire [31:0] cmd_internal;
wire [31:0] readdata_nxt;
//--------------------------------------------------------------------------------------------//
// address decode
//--------------------------------------------------------------------------------------------//
assign cmd_addr = (addr == 1'b0);
//--------------------------------------------------------------------------------------------//
// write enable
//--------------------------------------------------------------------------------------------//
assign cmd_wr_en = cmd_addr & write;
//--------------------------------------------------------------------------------------------//
// read enable
//--------------------------------------------------------------------------------------------//
assign cmd_rd_en = cmd_addr & read;
//--------------------------------------------------------------------------------------------//
// mode register bits
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
mode <= 3'h0;
else if (cmd_wr_en & ~run)
mode <= writedata[3:1];
end
//--------------------------------------------------------------------------------------------//
// run register bit
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
run <= 1'b0;
else if (clr_run)
run <= 1'b0;
else if (cmd_wr_en & writedata[0])
run <= 1'b1;
end
//--------------------------------------------------------------------------------------------//
// Logic to detect SW perform a clear on the run bit
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sw_clr_run <= 1'b0;
else if (clr_run)
sw_clr_run <= 1'b0;
else if (run & con_mode & cmd_wr_en & ~writedata[0])
sw_clr_run <= 1'b1;
end
//--------------------------------------------------------------------------------------------//
// Avalon read data path
//--------------------------------------------------------------------------------------------//
assign cmd_internal = {28'h0, mode, run};
assign readdata_nxt = cmd_internal & {32{cmd_rd_en}};
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
readdata <= 32'h0;
else
readdata <= readdata_nxt;
end
//--------------------------------------------------------------------------------------------//
// Mode decoding
//--------------------------------------------------------------------------------------------//
assign con_mode = (mode == 3'b000);
assign single_mode = (mode == 3'b001);
assign recab_mode = (mode == 3'b111);
endmodule |
module fiftyfivenm_adcblock_primitive_wrapper(
//reset,
chsel, // 5-bits channel selection.
soc, // signal Start-of-Conversion to ADC
eoc, // signal end of conversion. Data can be latched on the positive edge of clk_dft after this signal becomes high. EOC becomes low at every positive edge of the clk_dft signal.
dout, // 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge
usr_pwd, // User Power Down during run time. 0 = Power Up; 1 = Power Down.
tsen, // 0 = Normal Mode; 1 = Temperature Sensing Mode.
clkout_adccore, // Output clock from the clock divider
clkin_from_pll_c0 // Clock source from PLL1 c-counter[0] at BL corner or PLL3 c-counter[0] at TL corner
);
// *******************************************************************************************************
// ** PARAMETERS
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// WRAPPED PARAMETERS USED BY fiftyfivenm_adcblock
// -------------------------------------------------------------------------------------------------------
// 3-bits 1st stage clock divider.
// 0..5 = DIV by 1/2/10/20/40/80;
// 6..7 = invalid
parameter clkdiv = 1;
// 2nd stage clock divider.
// 0 = DIV by 10;
// 1 = DIV by 20
parameter tsclkdiv = 0;
// 0 = Use 1st stage clock divider when TSEN.
// 1 = Use 2nd stage clock divider when TSEN.
parameter tsclksel = 0;
// 2-bits To enable the R ladder for the prescalar input channels.
// 00 = disable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
// 01 = enable prescalar for CH8 only
// 10 = enable prescalar for CH16 only (CH8 for device with 2nd ADC)
// 11 = enable prescalar for CH8 and CH16 (CH8 for device with 2nd ADC)
// please note that this is not supported in VR mode
parameter prescalar = 0;
// Reference voltage selection for ADC.
// 0 = external;
// 1 = internal VCCADC_2P5
parameter refsel = 0;
// Ordering Part Number 10MXX... code
parameter device_partname_fivechar_prefix = "10M08"; // Valid options = 04, 08, 16, 25, 40, 50
// Some part have two ADC, instantiate which ADC? 1st or 2nd?
parameter is_this_first_or_second_adc = 1; // Valid options = 1 or 2
// is_using_dedicated_analog_input_pin_only? -> removed, replaced with analog_input_pin_mask
//parameter is_using_dedicated_analog_input_pin_only = 0;
// 16 bits to indicate whether each of the dual purpose analog input pin (ADCIN) is in use or not.
// 1 bit to indicate whether dedicated analog input pin (ANAIN) is in use or not (bit 16)
parameter analog_input_pin_mask = 17'h0;
// Power Down. Use to disable the ADC during compilation time if no ADC is in use.
parameter hard_pwd = 0;
// Logic simulation parameters which only affects simulation behavior
parameter enable_usr_sim = 0;
parameter reference_voltage_sim = 65536;
parameter simfilename_ch0 = "simfilename_ch0";
parameter simfilename_ch1 = "simfilename_ch1";
parameter simfilename_ch2 = "simfilename_ch2";
parameter simfilename_ch3 = "simfilename_ch3";
parameter simfilename_ch4 = "simfilename_ch4";
parameter simfilename_ch5 = "simfilename_ch5";
parameter simfilename_ch6 = "simfilename_ch6";
parameter simfilename_ch7 = "simfilename_ch7";
parameter simfilename_ch8 = "simfilename_ch8";
parameter simfilename_ch9 = "simfilename_ch9";
parameter simfilename_ch10 = "simfilename_ch10";
parameter simfilename_ch11 = "simfilename_ch11";
parameter simfilename_ch12 = "simfilename_ch12";
parameter simfilename_ch13 = "simfilename_ch13";
parameter simfilename_ch14 = "simfilename_ch14";
parameter simfilename_ch15 = "simfilename_ch15";
parameter simfilename_ch16 = "simfilename_ch16";
// *******************************************************************************************************
// ** INPUTS
// *******************************************************************************************************
//input reset;
input clkin_from_pll_c0; // Clock source from PLL1 c-counter[0] at BL corner or PLL3 c-counter[0] at TL corner
input soc; // signal Start-of-Conversion to ADC
input usr_pwd; // User Power Down during run time. 0 = Power Up; 1 = Power Down.
input tsen; // 0 = Normal Mode; 1 = Temperature Sensing Mode.
input [4:0] chsel; // 5-bits channel selection.
//reg reg_clk_dft_soc;
//reg [4:0] reg_clk_dft_chsel;
// *******************************************************************************************************
// ** OUTPUTS
// *******************************************************************************************************
output clkout_adccore;
output eoc;
output [11:0] dout;
wire [11:0] wire_from_adc_dout;
//reg [11:0] reg_clk_dft_dout;
// *******************************************************************************************************
// ** OUTPUTS ASSIGNMENTS
// *******************************************************************************************************
//assign dout = reg_clk_dft_dout;
assign dout = wire_from_adc_dout;
// *******************************************************************************************************
// ** INITIALIZATION
// *******************************************************************************************************
// *******************************************************************************************************
// ** MAIN CODE
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.00: Instantiate ADC Block primitive
// -------------------------------------------------------------------------------------------------------
`ifdef DEBUG_AND_DEVELOPMENT
fiftyfivenm_adcblock_emulation primitive_instance(
`else
fiftyfivenm_adcblock primitive_instance(
`endif
//.chsel (reg_clk_dft_chsel),
//.soc (reg_clk_dft_soc),
.chsel (chsel),
.soc (soc),
.eoc (eoc),
.dout (wire_from_adc_dout),
.usr_pwd (usr_pwd),
.tsen (tsen),
.clk_dft (clkout_adccore),
.clkin_from_pll_c0(clkin_from_pll_c0)
);
defparam primitive_instance.clkdiv = clkdiv;
defparam primitive_instance.tsclkdiv = tsclkdiv;
defparam primitive_instance.tsclksel = tsclksel;
defparam primitive_instance.prescalar = prescalar;
defparam primitive_instance.refsel = refsel;
defparam primitive_instance.device_partname_fivechar_prefix = device_partname_fivechar_prefix;
defparam primitive_instance.is_this_first_or_second_adc = is_this_first_or_second_adc;
defparam primitive_instance.analog_input_pin_mask = analog_input_pin_mask;
defparam primitive_instance.pwd = hard_pwd;
defparam primitive_instance.enable_usr_sim = enable_usr_sim;
defparam primitive_instance.reference_voltage_sim = reference_voltage_sim;
defparam primitive_instance.simfilename_ch0 = simfilename_ch0;
defparam primitive_instance.simfilename_ch1 = simfilename_ch1;
defparam primitive_instance.simfilename_ch2 = simfilename_ch2;
defparam primitive_instance.simfilename_ch3 = simfilename_ch3;
defparam primitive_instance.simfilename_ch4 = simfilename_ch4;
defparam primitive_instance.simfilename_ch5 = simfilename_ch5;
defparam primitive_instance.simfilename_ch6 = simfilename_ch6;
defparam primitive_instance.simfilename_ch7 = simfilename_ch7;
defparam primitive_instance.simfilename_ch8 = simfilename_ch8;
defparam primitive_instance.simfilename_ch9 = simfilename_ch9;
defparam primitive_instance.simfilename_ch10 = simfilename_ch10;
defparam primitive_instance.simfilename_ch11 = simfilename_ch11;
defparam primitive_instance.simfilename_ch12 = simfilename_ch12;
defparam primitive_instance.simfilename_ch13 = simfilename_ch13;
defparam primitive_instance.simfilename_ch14 = simfilename_ch14;
defparam primitive_instance.simfilename_ch15 = simfilename_ch15;
defparam primitive_instance.simfilename_ch16 = simfilename_ch16;
// -------------------------------------------------------------------------------------------------------
// 2.00: Clock the registers with ADC Clock source
// -------------------------------------------------------------------------------------------------------
// DESCRIBE THE ALWAYS BLOCK:
// The purpose is to clock the registers using clk_dft signal for timing closure
// ADC primitive signals type
// Type Sync: chsel, soc, eoc, dout, clk_dft
// Type Async: usr_pwd, tsen
// Signals need a register clocked by clk_dft: chsel, dout, soc
//always @ (posedge clkout_adccore or posedge reset)
//begin
// if (reset)
// begin
// // Reset signal asserted
// reg_clk_dft_soc <= 0;
// reg_clk_dft_chsel <= 0;
// reg_clk_dft_dout <= 0;
// end
// else
// begin
// reg_clk_dft_soc <= soc;
// reg_clk_dft_chsel <= chsel;
// reg_clk_dft_dout <= wire_from_adc_dout;
// end //end-if
//end
// *******************************************************************************************************
// ** END OF MODULE
// *******************************************************************************************************
endmodule |
module altera_modular_adc_sequencer #(
parameter DUAL_ADC_MODE = 0,
parameter CSD_LENGTH = 64,
parameter CSD_SLOT_0 = 5'h0,
parameter CSD_SLOT_1 = 5'h0,
parameter CSD_SLOT_2 = 5'h0,
parameter CSD_SLOT_3 = 5'h0,
parameter CSD_SLOT_4 = 5'h0,
parameter CSD_SLOT_5 = 5'h0,
parameter CSD_SLOT_6 = 5'h0,
parameter CSD_SLOT_7 = 5'h0,
parameter CSD_SLOT_8 = 5'h0,
parameter CSD_SLOT_9 = 5'h0,
parameter CSD_SLOT_10 = 5'h0,
parameter CSD_SLOT_11 = 5'h0,
parameter CSD_SLOT_12 = 5'h0,
parameter CSD_SLOT_13 = 5'h0,
parameter CSD_SLOT_14 = 5'h0,
parameter CSD_SLOT_15 = 5'h0,
parameter CSD_SLOT_16 = 5'h0,
parameter CSD_SLOT_17 = 5'h0,
parameter CSD_SLOT_18 = 5'h0,
parameter CSD_SLOT_19 = 5'h0,
parameter CSD_SLOT_20 = 5'h0,
parameter CSD_SLOT_21 = 5'h0,
parameter CSD_SLOT_22 = 5'h0,
parameter CSD_SLOT_23 = 5'h0,
parameter CSD_SLOT_24 = 5'h0,
parameter CSD_SLOT_25 = 5'h0,
parameter CSD_SLOT_26 = 5'h0,
parameter CSD_SLOT_27 = 5'h0,
parameter CSD_SLOT_28 = 5'h0,
parameter CSD_SLOT_29 = 5'h0,
parameter CSD_SLOT_30 = 5'h0,
parameter CSD_SLOT_31 = 5'h0,
parameter CSD_SLOT_32 = 5'h0,
parameter CSD_SLOT_33 = 5'h0,
parameter CSD_SLOT_34 = 5'h0,
parameter CSD_SLOT_35 = 5'h0,
parameter CSD_SLOT_36 = 5'h0,
parameter CSD_SLOT_37 = 5'h0,
parameter CSD_SLOT_38 = 5'h0,
parameter CSD_SLOT_39 = 5'h0,
parameter CSD_SLOT_40 = 5'h0,
parameter CSD_SLOT_41 = 5'h0,
parameter CSD_SLOT_42 = 5'h0,
parameter CSD_SLOT_43 = 5'h0,
parameter CSD_SLOT_44 = 5'h0,
parameter CSD_SLOT_45 = 5'h0,
parameter CSD_SLOT_46 = 5'h0,
parameter CSD_SLOT_47 = 5'h0,
parameter CSD_SLOT_48 = 5'h0,
parameter CSD_SLOT_49 = 5'h0,
parameter CSD_SLOT_50 = 5'h0,
parameter CSD_SLOT_51 = 5'h0,
parameter CSD_SLOT_52 = 5'h0,
parameter CSD_SLOT_53 = 5'h0,
parameter CSD_SLOT_54 = 5'h0,
parameter CSD_SLOT_55 = 5'h0,
parameter CSD_SLOT_56 = 5'h0,
parameter CSD_SLOT_57 = 5'h0,
parameter CSD_SLOT_58 = 5'h0,
parameter CSD_SLOT_59 = 5'h0,
parameter CSD_SLOT_60 = 5'h0,
parameter CSD_SLOT_61 = 5'h0,
parameter CSD_SLOT_62 = 5'h0,
parameter CSD_SLOT_63 = 5'h0,
parameter CSD_SLOT_0_ADC2 = 5'h0,
parameter CSD_SLOT_1_ADC2 = 5'h0,
parameter CSD_SLOT_2_ADC2 = 5'h0,
parameter CSD_SLOT_3_ADC2 = 5'h0,
parameter CSD_SLOT_4_ADC2 = 5'h0,
parameter CSD_SLOT_5_ADC2 = 5'h0,
parameter CSD_SLOT_6_ADC2 = 5'h0,
parameter CSD_SLOT_7_ADC2 = 5'h0,
parameter CSD_SLOT_8_ADC2 = 5'h0,
parameter CSD_SLOT_9_ADC2 = 5'h0,
parameter CSD_SLOT_10_ADC2 = 5'h0,
parameter CSD_SLOT_11_ADC2 = 5'h0,
parameter CSD_SLOT_12_ADC2 = 5'h0,
parameter CSD_SLOT_13_ADC2 = 5'h0,
parameter CSD_SLOT_14_ADC2 = 5'h0,
parameter CSD_SLOT_15_ADC2 = 5'h0,
parameter CSD_SLOT_16_ADC2 = 5'h0,
parameter CSD_SLOT_17_ADC2 = 5'h0,
parameter CSD_SLOT_18_ADC2 = 5'h0,
parameter CSD_SLOT_19_ADC2 = 5'h0,
parameter CSD_SLOT_20_ADC2 = 5'h0,
parameter CSD_SLOT_21_ADC2 = 5'h0,
parameter CSD_SLOT_22_ADC2 = 5'h0,
parameter CSD_SLOT_23_ADC2 = 5'h0,
parameter CSD_SLOT_24_ADC2 = 5'h0,
parameter CSD_SLOT_25_ADC2 = 5'h0,
parameter CSD_SLOT_26_ADC2 = 5'h0,
parameter CSD_SLOT_27_ADC2 = 5'h0,
parameter CSD_SLOT_28_ADC2 = 5'h0,
parameter CSD_SLOT_29_ADC2 = 5'h0,
parameter CSD_SLOT_30_ADC2 = 5'h0,
parameter CSD_SLOT_31_ADC2 = 5'h0,
parameter CSD_SLOT_32_ADC2 = 5'h0,
parameter CSD_SLOT_33_ADC2 = 5'h0,
parameter CSD_SLOT_34_ADC2 = 5'h0,
parameter CSD_SLOT_35_ADC2 = 5'h0,
parameter CSD_SLOT_36_ADC2 = 5'h0,
parameter CSD_SLOT_37_ADC2 = 5'h0,
parameter CSD_SLOT_38_ADC2 = 5'h0,
parameter CSD_SLOT_39_ADC2 = 5'h0,
parameter CSD_SLOT_40_ADC2 = 5'h0,
parameter CSD_SLOT_41_ADC2 = 5'h0,
parameter CSD_SLOT_42_ADC2 = 5'h0,
parameter CSD_SLOT_43_ADC2 = 5'h0,
parameter CSD_SLOT_44_ADC2 = 5'h0,
parameter CSD_SLOT_45_ADC2 = 5'h0,
parameter CSD_SLOT_46_ADC2 = 5'h0,
parameter CSD_SLOT_47_ADC2 = 5'h0,
parameter CSD_SLOT_48_ADC2 = 5'h0,
parameter CSD_SLOT_49_ADC2 = 5'h0,
parameter CSD_SLOT_50_ADC2 = 5'h0,
parameter CSD_SLOT_51_ADC2 = 5'h0,
parameter CSD_SLOT_52_ADC2 = 5'h0,
parameter CSD_SLOT_53_ADC2 = 5'h0,
parameter CSD_SLOT_54_ADC2 = 5'h0,
parameter CSD_SLOT_55_ADC2 = 5'h0,
parameter CSD_SLOT_56_ADC2 = 5'h0,
parameter CSD_SLOT_57_ADC2 = 5'h0,
parameter CSD_SLOT_58_ADC2 = 5'h0,
parameter CSD_SLOT_59_ADC2 = 5'h0,
parameter CSD_SLOT_60_ADC2 = 5'h0,
parameter CSD_SLOT_61_ADC2 = 5'h0,
parameter CSD_SLOT_62_ADC2 = 5'h0,
parameter CSD_SLOT_63_ADC2 = 5'h0
) (
input clk,
input rst_n,
input addr,
input read,
input write,
input [31:0] writedata,
input cmd_ready,
input cmd_ready_2,
output [31:0] readdata,
output cmd_valid,
output [4:0] cmd_channel,
output cmd_sop,
output cmd_eop,
output cmd_valid_2,
output [4:0] cmd_channel_2,
output cmd_sop_2,
output cmd_eop_2
);
wire clr_run;
wire clr_run_2;
wire run;
wire sw_clr_run;
wire con_mode;
wire single_mode;
wire recab_mode;
function integer clog2;
input [31:0] value; // Input variable
if (value == 32'h0) begin
clog2 = 1;
end
else begin
for (clog2=0; value>0; clog2=clog2+1)
value = value>>'d1;
end
endfunction
localparam CSD_ASIZE = clog2(CSD_LENGTH - 1);
//--------------------------------------------------------------------------------------------//
// CSR block instantiation
//--------------------------------------------------------------------------------------------//
altera_modular_adc_sequencer_csr u_seq_csr (
// inputs
.clk (clk),
.rst_n (rst_n),
.addr (addr),
.read (read),
.write (write),
.writedata (writedata),
.clr_run (clr_run), // clr_run and clr_run_2 shall assert/de-assert at the same cycle (design requirement)
// therefore, only one of them is feed back into csr block
// outputs
.readdata (readdata),
.run (run),
.sw_clr_run (sw_clr_run),
.con_mode (con_mode),
.single_mode (single_mode),
.recab_mode (recab_mode)
);
//--------------------------------------------------------------------------------------------//
// Sequencer control block instantiation
//--------------------------------------------------------------------------------------------//
altera_modular_adc_sequencer_ctrl #(
.CSD_LENGTH (CSD_LENGTH),
.CSD_ASIZE (CSD_ASIZE),
.CSD_SLOT_0 (CSD_SLOT_0),
.CSD_SLOT_1 (CSD_SLOT_1),
.CSD_SLOT_2 (CSD_SLOT_2),
.CSD_SLOT_3 (CSD_SLOT_3),
.CSD_SLOT_4 (CSD_SLOT_4),
.CSD_SLOT_5 (CSD_SLOT_5),
.CSD_SLOT_6 (CSD_SLOT_6),
.CSD_SLOT_7 (CSD_SLOT_7),
.CSD_SLOT_8 (CSD_SLOT_8),
.CSD_SLOT_9 (CSD_SLOT_9),
.CSD_SLOT_10 (CSD_SLOT_10),
.CSD_SLOT_11 (CSD_SLOT_11),
.CSD_SLOT_12 (CSD_SLOT_12),
.CSD_SLOT_13 (CSD_SLOT_13),
.CSD_SLOT_14 (CSD_SLOT_14),
.CSD_SLOT_15 (CSD_SLOT_15),
.CSD_SLOT_16 (CSD_SLOT_16),
.CSD_SLOT_17 (CSD_SLOT_17),
.CSD_SLOT_18 (CSD_SLOT_18),
.CSD_SLOT_19 (CSD_SLOT_19),
.CSD_SLOT_20 (CSD_SLOT_20),
.CSD_SLOT_21 (CSD_SLOT_21),
.CSD_SLOT_22 (CSD_SLOT_22),
.CSD_SLOT_23 (CSD_SLOT_23),
.CSD_SLOT_24 (CSD_SLOT_24),
.CSD_SLOT_25 (CSD_SLOT_25),
.CSD_SLOT_26 (CSD_SLOT_26),
.CSD_SLOT_27 (CSD_SLOT_27),
.CSD_SLOT_28 (CSD_SLOT_28),
.CSD_SLOT_29 (CSD_SLOT_29),
.CSD_SLOT_30 (CSD_SLOT_30),
.CSD_SLOT_31 (CSD_SLOT_31),
.CSD_SLOT_32 (CSD_SLOT_32),
.CSD_SLOT_33 (CSD_SLOT_33),
.CSD_SLOT_34 (CSD_SLOT_34),
.CSD_SLOT_35 (CSD_SLOT_35),
.CSD_SLOT_36 (CSD_SLOT_36),
.CSD_SLOT_37 (CSD_SLOT_37),
.CSD_SLOT_38 (CSD_SLOT_38),
.CSD_SLOT_39 (CSD_SLOT_39),
.CSD_SLOT_40 (CSD_SLOT_40),
.CSD_SLOT_41 (CSD_SLOT_41),
.CSD_SLOT_42 (CSD_SLOT_42),
.CSD_SLOT_43 (CSD_SLOT_43),
.CSD_SLOT_44 (CSD_SLOT_44),
.CSD_SLOT_45 (CSD_SLOT_45),
.CSD_SLOT_46 (CSD_SLOT_46),
.CSD_SLOT_47 (CSD_SLOT_47),
.CSD_SLOT_48 (CSD_SLOT_48),
.CSD_SLOT_49 (CSD_SLOT_49),
.CSD_SLOT_50 (CSD_SLOT_50),
.CSD_SLOT_51 (CSD_SLOT_51),
.CSD_SLOT_52 (CSD_SLOT_52),
.CSD_SLOT_53 (CSD_SLOT_53),
.CSD_SLOT_54 (CSD_SLOT_54),
.CSD_SLOT_55 (CSD_SLOT_55),
.CSD_SLOT_56 (CSD_SLOT_56),
.CSD_SLOT_57 (CSD_SLOT_57),
.CSD_SLOT_58 (CSD_SLOT_58),
.CSD_SLOT_59 (CSD_SLOT_59),
.CSD_SLOT_60 (CSD_SLOT_60),
.CSD_SLOT_61 (CSD_SLOT_61),
.CSD_SLOT_62 (CSD_SLOT_62),
.CSD_SLOT_63 (CSD_SLOT_63)
) u_seq_ctrl (
// inputs
.clk (clk),
.rst_n (rst_n),
.run (run),
.sw_clr_run (sw_clr_run),
.con_mode (con_mode),
.single_mode (single_mode),
.recab_mode (recab_mode),
.cmd_ready (cmd_ready),
// outputs
.cmd_valid (cmd_valid),
.cmd_channel (cmd_channel),
.cmd_sop (cmd_sop),
.cmd_eop (cmd_eop),
.clr_run (clr_run)
);
generate
if (DUAL_ADC_MODE == 1) begin
altera_modular_adc_sequencer_ctrl #(
.CSD_LENGTH (CSD_LENGTH),
.CSD_ASIZE (CSD_ASIZE),
.CSD_SLOT_0 (CSD_SLOT_0_ADC2),
.CSD_SLOT_1 (CSD_SLOT_1_ADC2),
.CSD_SLOT_2 (CSD_SLOT_2_ADC2),
.CSD_SLOT_3 (CSD_SLOT_3_ADC2),
.CSD_SLOT_4 (CSD_SLOT_4_ADC2),
.CSD_SLOT_5 (CSD_SLOT_5_ADC2),
.CSD_SLOT_6 (CSD_SLOT_6_ADC2),
.CSD_SLOT_7 (CSD_SLOT_7_ADC2),
.CSD_SLOT_8 (CSD_SLOT_8_ADC2),
.CSD_SLOT_9 (CSD_SLOT_9_ADC2),
.CSD_SLOT_10 (CSD_SLOT_10_ADC2),
.CSD_SLOT_11 (CSD_SLOT_11_ADC2),
.CSD_SLOT_12 (CSD_SLOT_12_ADC2),
.CSD_SLOT_13 (CSD_SLOT_13_ADC2),
.CSD_SLOT_14 (CSD_SLOT_14_ADC2),
.CSD_SLOT_15 (CSD_SLOT_15_ADC2),
.CSD_SLOT_16 (CSD_SLOT_16_ADC2),
.CSD_SLOT_17 (CSD_SLOT_17_ADC2),
.CSD_SLOT_18 (CSD_SLOT_18_ADC2),
.CSD_SLOT_19 (CSD_SLOT_19_ADC2),
.CSD_SLOT_20 (CSD_SLOT_20_ADC2),
.CSD_SLOT_21 (CSD_SLOT_21_ADC2),
.CSD_SLOT_22 (CSD_SLOT_22_ADC2),
.CSD_SLOT_23 (CSD_SLOT_23_ADC2),
.CSD_SLOT_24 (CSD_SLOT_24_ADC2),
.CSD_SLOT_25 (CSD_SLOT_25_ADC2),
.CSD_SLOT_26 (CSD_SLOT_26_ADC2),
.CSD_SLOT_27 (CSD_SLOT_27_ADC2),
.CSD_SLOT_28 (CSD_SLOT_28_ADC2),
.CSD_SLOT_29 (CSD_SLOT_29_ADC2),
.CSD_SLOT_30 (CSD_SLOT_30_ADC2),
.CSD_SLOT_31 (CSD_SLOT_31_ADC2),
.CSD_SLOT_32 (CSD_SLOT_32_ADC2),
.CSD_SLOT_33 (CSD_SLOT_33_ADC2),
.CSD_SLOT_34 (CSD_SLOT_34_ADC2),
.CSD_SLOT_35 (CSD_SLOT_35_ADC2),
.CSD_SLOT_36 (CSD_SLOT_36_ADC2),
.CSD_SLOT_37 (CSD_SLOT_37_ADC2),
.CSD_SLOT_38 (CSD_SLOT_38_ADC2),
.CSD_SLOT_39 (CSD_SLOT_39_ADC2),
.CSD_SLOT_40 (CSD_SLOT_40_ADC2),
.CSD_SLOT_41 (CSD_SLOT_41_ADC2),
.CSD_SLOT_42 (CSD_SLOT_42_ADC2),
.CSD_SLOT_43 (CSD_SLOT_43_ADC2),
.CSD_SLOT_44 (CSD_SLOT_44_ADC2),
.CSD_SLOT_45 (CSD_SLOT_45_ADC2),
.CSD_SLOT_46 (CSD_SLOT_46_ADC2),
.CSD_SLOT_47 (CSD_SLOT_47_ADC2),
.CSD_SLOT_48 (CSD_SLOT_48_ADC2),
.CSD_SLOT_49 (CSD_SLOT_49_ADC2),
.CSD_SLOT_50 (CSD_SLOT_50_ADC2),
.CSD_SLOT_51 (CSD_SLOT_51_ADC2),
.CSD_SLOT_52 (CSD_SLOT_52_ADC2),
.CSD_SLOT_53 (CSD_SLOT_53_ADC2),
.CSD_SLOT_54 (CSD_SLOT_54_ADC2),
.CSD_SLOT_55 (CSD_SLOT_55_ADC2),
.CSD_SLOT_56 (CSD_SLOT_56_ADC2),
.CSD_SLOT_57 (CSD_SLOT_57_ADC2),
.CSD_SLOT_58 (CSD_SLOT_58_ADC2),
.CSD_SLOT_59 (CSD_SLOT_59_ADC2),
.CSD_SLOT_60 (CSD_SLOT_60_ADC2),
.CSD_SLOT_61 (CSD_SLOT_61_ADC2),
.CSD_SLOT_62 (CSD_SLOT_62_ADC2),
.CSD_SLOT_63 (CSD_SLOT_63_ADC2)
) u_seq_ctrl_adc2 (
// inputs
.clk (clk),
.rst_n (rst_n),
.run (run),
.sw_clr_run (sw_clr_run),
.con_mode (con_mode),
.single_mode (single_mode),
.recab_mode (recab_mode),
.cmd_ready (cmd_ready_2),
// outputs
.cmd_valid (cmd_valid_2),
.cmd_channel (cmd_channel_2),
.cmd_sop (cmd_sop_2),
.cmd_eop (cmd_eop_2),
.clr_run (clr_run_2) // clr_run_2 shall assert/de-assert at the same cycle as clr_run
);
end
else begin
assign cmd_valid_2 = 1'b0;
assign cmd_channel_2 = 5'h0;
assign cmd_sop_2 = 1'b0;
assign cmd_eop_2 = 1'b0;
end
endgenerate
endmodule |
module altera_modular_adc_control_fsm #(
parameter is_this_first_or_second_adc = 1,
parameter dual_adc_mode = 0
) (
input clk,
input rst_n,
input clk_in_pll_locked,
input cmd_valid,
input [4:0] cmd_channel,
input cmd_sop,
input cmd_eop,
input clk_dft,
input eoc,
input [11:0] dout,
input sync_ready,
output reg rsp_valid,
output reg [4:0] rsp_channel,
output reg [11:0] rsp_data,
output reg rsp_sop,
output reg rsp_eop,
output reg cmd_ready,
output reg [4:0] chsel,
output reg soc,
output reg usr_pwd,
output reg tsen,
output reg sync_valid
);
reg [4:0] ctrl_state;
reg [4:0] ctrl_state_nxt;
reg clk_dft_synch_dly;
reg eoc_synch_dly;
reg [4:0] chsel_nxt;
reg soc_nxt;
reg usr_pwd_nxt;
reg tsen_nxt;
reg prev_cmd_is_ts;
reg cmd_fetched;
reg pend;
reg [4:0] cmd_channel_dly;
reg cmd_sop_dly;
reg cmd_eop_dly;
reg [7:0] int_timer;
reg [17:0] avrg_sum;
reg avrg_cnt_done;
reg frst_64_ptr_done;
reg conv_dly1_s_flp;
reg [11:0] dout_flp;
reg [4:0] prev_ctrl_state;
reg [4:0] sync_ctrl_state;
reg [4:0] sync_ctrl_state_nxt;
wire clk_dft_synch;
wire eoc_synch;
wire clk_dft_lh;
wire clk_dft_hl;
wire eoc_hl;
wire cmd_is_rclb;
wire cmd_is_ts;
wire arc_conv_conv_dly1;
wire arc_sync1_conv_dly1;
wire arc_wait_pend_wait_pend_dly1;
wire arc_sync1_wait_pend_dly1;
wire arc_to_conv;
wire arc_to_avrg_cnt;
wire load_rsp;
wire load_cmd_ready;
wire arc_getcmd_w_pwrdwn;
wire arc_getcmd_pwrdwn;
wire load_cmd_fetched;
wire load_int_timer;
wire incr_int_timer;
wire arc_out_from_pwrup_soc;
wire clr_cmd_fetched;
wire adc_change_mode;
wire add_avrg_sum;
wire add_avrg_sum_run;
wire clear_avrg_sum;
wire clear_avrg_cnt_done;
wire set_frst_64_ptr_done;
wire clear_frst_64_ptr_done;
wire [11:0] fifo_q;
wire fifo_sclr;
wire fifo_rdreq;
wire fifo_wrreq;
wire putresp_s;
wire putresp_pend_s;
wire pwrdwn_s;
wire pwrdwn_tsen_s;
wire avrg_cnt_s;
wire wait_pend_dly1_s;
wire conv_dly1_s;
wire conv_s;
wire putresp_dly3_s;
wire load_dout;
wire avrg_enable;
wire [11:0] rsp_data_nxt;
localparam [4:0] IDLE = 5'b00000;
localparam [4:0] PWRDWN = 5'b00001;
localparam [4:0] PWRDWN_TSEN = 5'b00010;
localparam [4:0] PWRDWN_DONE = 5'b00011;
localparam [4:0] PWRUP_CH = 5'b00100;
localparam [4:0] PWRUP_SOC = 5'b00101;
localparam [4:0] WAIT = 5'b00110;
localparam [4:0] GETCMD = 5'b00111;
localparam [4:0] GETCMD_W = 5'b01000;
localparam [4:0] PRE_CONV = 5'b01001;
localparam [4:0] CONV = 5'b01010; // Drive chsel. Get out of this state when falling edge of EOC detected (DOUT is ready for sample)
// Read averaging fifo.
// Capture DOUT into dout internal buffer register (dout_flp)
localparam [4:0] CONV_DLY1 = 5'b01011; // Additional state for processing when DOUT is ready. Perform averaging calculation (adds and minus operation).
localparam [4:0] PUTRESP = 5'b01100; // Load response
localparam [4:0] PUTRESP_DLY1 = 5'b01101;
localparam [4:0] PUTRESP_DLY2 = 5'b01110;
localparam [4:0] PUTRESP_DLY3 = 5'b01111;
localparam [4:0] WAIT_PEND = 5'b10000; // Get out of this state when falling edge of EOC detected (DOUT is ready for sample)
// Read averaging fifo.
// Capture DOUT into dout internal buffer register (dout_flp)
localparam [4:0] WAIT_PEND_DLY1 = 5'b10001; // Additional state for processing when DOUT is ready. Perform averaging calculation (adds and minus operation).
localparam [4:0] PUTRESP_PEND = 5'b10010; // Load response
localparam [4:0] AVRG_CNT = 5'b10011;
localparam [4:0] SYNC1 = 5'b10100; // Allocates 1 soft ip clock mismatch due to asynchronous between soft ip clock and ADC clock domain
localparam [7:0] NUM_AVRG_POINTS = 8'd64;
//--------------------------------------------------------------------------------------------//
// Double Synchronize control signal from ADC hardblock
//--------------------------------------------------------------------------------------------//
altera_std_synchronizer #(
.depth (2)
) u_clk_dft_synchronizer (
.clk (clk),
.reset_n (rst_n),
.din (clk_dft),
.dout (clk_dft_synch)
);
altera_std_synchronizer #(
.depth (2)
) u_eoc_synchronizer (
.clk (clk),
.reset_n (rst_n),
.din (eoc),
.dout (eoc_synch)
);
//--------------------------------------------------------------------------------------------//
// Edge detection for both synchronized clk_dft and eoc
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
clk_dft_synch_dly <= 1'b0;
eoc_synch_dly <= 1'b0;
end
else begin
clk_dft_synch_dly <= clk_dft_synch;
eoc_synch_dly <= eoc_synch;
end
end
assign clk_dft_lh = clk_dft_synch & ~clk_dft_synch_dly;
assign clk_dft_hl = ~clk_dft_synch & clk_dft_synch_dly;
assign eoc_hl = ~eoc_synch & eoc_synch_dly;
//--------------------------------------------------------------------------------------------//
// Dual ADC
//--------------------------------------------------------------------------------------------//
generate
if (dual_adc_mode == 1) begin
// Buffer up ctrl_state
// To be used when both ADC is out of sync
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
prev_ctrl_state <= IDLE;
else
prev_ctrl_state <= ctrl_state;
end
// Buffer up ctrl_state
// To be used when both ADC mismatches by 1 soft ip clock
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
sync_ctrl_state <= IDLE;
else
sync_ctrl_state <= sync_ctrl_state_nxt;
end
end
else begin
always @* begin
prev_ctrl_state = 5'h0;
sync_ctrl_state = 5'h0;
end
end
endgenerate
//--------------------------------------------------------------------------------------------//
// Main FSM
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
ctrl_state <= IDLE;
else
ctrl_state <= ctrl_state_nxt;
end
always @* begin
// Default assignment, perform assignment only at relevant state
sync_ctrl_state_nxt = sync_ctrl_state;
sync_valid = 1'b0;
case (ctrl_state)
IDLE: begin
if (clk_in_pll_locked)
ctrl_state_nxt = PWRDWN;
else
ctrl_state_nxt = IDLE;
end
PWRDWN: begin
if (int_timer[6])
ctrl_state_nxt = PWRDWN_TSEN;
else
ctrl_state_nxt = PWRDWN;
end
PWRDWN_TSEN: begin
if (int_timer[7])
ctrl_state_nxt = PWRDWN_DONE;
else
ctrl_state_nxt = PWRDWN_TSEN;
end
PWRDWN_DONE: begin
if (dual_adc_mode == 1) begin
if (clk_dft_lh) begin
if (sync_ready)
ctrl_state_nxt = PWRUP_CH;
else
ctrl_state_nxt = SYNC1;
end
else begin
ctrl_state_nxt = PWRDWN_DONE;
end
if (clk_dft_lh) begin
sync_ctrl_state_nxt = PWRUP_CH;
sync_valid = 1'b1;
end
end
else begin
if (clk_dft_lh)
ctrl_state_nxt = PWRUP_CH;
else
ctrl_state_nxt = PWRDWN_DONE;
end
end
PWRUP_CH: begin
if (dual_adc_mode == 1) begin
if (clk_dft_hl) begin
if (sync_ready)
ctrl_state_nxt = PWRUP_SOC;
else
ctrl_state_nxt = SYNC1;
end
else begin
ctrl_state_nxt = PWRUP_CH;
end
if (clk_dft_hl) begin
sync_ctrl_state_nxt = PWRUP_SOC;
sync_valid = 1'b1;
end
end
else begin
if (clk_dft_hl)
ctrl_state_nxt = PWRUP_SOC;
else
ctrl_state_nxt = PWRUP_CH;
end
end
PWRUP_SOC: begin
if (dual_adc_mode == 1) begin
if (eoc_hl) begin
if (sync_ready) begin
if (cmd_fetched & ~cmd_is_rclb)
ctrl_state_nxt = CONV;
else if (cmd_fetched & cmd_is_rclb)
ctrl_state_nxt = PUTRESP;
else if (cmd_valid)
ctrl_state_nxt = GETCMD;
else
ctrl_state_nxt = WAIT;
end
else begin
ctrl_state_nxt = SYNC1;
end
end
else begin
ctrl_state_nxt = PWRUP_SOC;
end
if (eoc_hl) begin
if (cmd_fetched & ~cmd_is_rclb)
sync_ctrl_state_nxt = CONV;
else if (cmd_fetched & cmd_is_rclb)
sync_ctrl_state_nxt = PUTRESP;
else if (cmd_valid)
sync_ctrl_state_nxt = GETCMD;
else
sync_ctrl_state_nxt = WAIT;
sync_valid = 1'b1;
end
end
else begin
if (cmd_fetched & ~cmd_is_rclb & eoc_hl)
ctrl_state_nxt = CONV;
else if (cmd_fetched & cmd_is_rclb & eoc_hl)
ctrl_state_nxt = PUTRESP;
else if (cmd_valid & eoc_hl)
ctrl_state_nxt = GETCMD;
else if (eoc_hl)
ctrl_state_nxt = WAIT;
else
ctrl_state_nxt = PWRUP_SOC;
end
end
SYNC1: begin
if (sync_ready)
ctrl_state_nxt = sync_ctrl_state; // mismatches by 1 soft ip clock, proceed to next state
else
ctrl_state_nxt = prev_ctrl_state; // Both ADC is out of sync, go back to previous state
sync_valid = 1'b1;
end
WAIT: begin
if (cmd_valid)
ctrl_state_nxt = GETCMD_W;
else
ctrl_state_nxt = WAIT;
end
GETCMD_W: begin
if (cmd_is_rclb | adc_change_mode)
ctrl_state_nxt = PWRDWN;
else
ctrl_state_nxt = PRE_CONV;
end
PRE_CONV: begin
if (dual_adc_mode == 1) begin
if (eoc_hl) begin
if (sync_ready)
ctrl_state_nxt = CONV;
else
ctrl_state_nxt = SYNC1;
end
else begin
ctrl_state_nxt = PRE_CONV;
end
if (eoc_hl) begin
sync_ctrl_state_nxt = CONV;
sync_valid = 1'b1;
end
end
else begin
if (eoc_hl)
ctrl_state_nxt = CONV;
else
ctrl_state_nxt = PRE_CONV;
end
end
GETCMD: begin
if ((cmd_is_rclb | adc_change_mode) & ~pend)
ctrl_state_nxt = PWRDWN;
else if ((cmd_is_rclb | adc_change_mode) & pend)
ctrl_state_nxt = WAIT_PEND;
else
ctrl_state_nxt = CONV;
end
CONV: begin
if (dual_adc_mode == 1) begin
if (eoc_hl) begin
if (sync_ready) begin
if (avrg_enable & ~avrg_cnt_done)
ctrl_state_nxt = AVRG_CNT;
else
ctrl_state_nxt = CONV_DLY1;
end
else begin
ctrl_state_nxt = SYNC1;
end
end
else begin
ctrl_state_nxt = CONV;
end
if (eoc_hl) begin
if (avrg_enable & ~avrg_cnt_done)
sync_ctrl_state_nxt = AVRG_CNT;
else
sync_ctrl_state_nxt = CONV_DLY1;
sync_valid = 1'b1;
end
end
else begin
if (eoc_hl & avrg_enable & ~avrg_cnt_done)
ctrl_state_nxt = AVRG_CNT;
else if (eoc_hl)
ctrl_state_nxt = CONV_DLY1;
else
ctrl_state_nxt = CONV;
end
end
AVRG_CNT: begin
ctrl_state_nxt = CONV;
end
CONV_DLY1: begin
ctrl_state_nxt = PUTRESP;
end
PUTRESP: begin
ctrl_state_nxt = PUTRESP_DLY1;
end
PUTRESP_DLY1: begin
ctrl_state_nxt = PUTRESP_DLY2;
end
PUTRESP_DLY2: begin
ctrl_state_nxt = PUTRESP_DLY3;
end
PUTRESP_DLY3: begin
if (cmd_valid)
ctrl_state_nxt = GETCMD;
else if (pend)
ctrl_state_nxt = WAIT_PEND;
else
ctrl_state_nxt = WAIT;
end
WAIT_PEND: begin
if (dual_adc_mode == 1) begin
if (eoc_hl) begin
if (sync_ready)
ctrl_state_nxt = WAIT_PEND_DLY1;
else
ctrl_state_nxt = SYNC1;
end
else begin
ctrl_state_nxt = WAIT_PEND;
end
if (eoc_hl) begin
sync_ctrl_state_nxt = WAIT_PEND_DLY1;
sync_valid = 1'b1;
end
end
else begin
if (eoc_hl)
ctrl_state_nxt = WAIT_PEND_DLY1;
else
ctrl_state_nxt = WAIT_PEND;
end
end
WAIT_PEND_DLY1: begin
ctrl_state_nxt = PUTRESP_PEND;
end
PUTRESP_PEND: begin
if (cmd_valid)
ctrl_state_nxt = GETCMD;
else
ctrl_state_nxt = WAIT;
end
default: begin
ctrl_state_nxt = IDLE;
end
endcase
end
//--------------------------------------------------------------------------------------------//
// ADC control signal generation from FSM
//--------------------------------------------------------------------------------------------//
always @* begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
case (ctrl_state_nxt)
IDLE: begin
chsel_nxt = 5'b11110;
soc_nxt = 1'b0;
usr_pwd_nxt = 1'b1;
tsen_nxt = 1'b0;
end
PWRDWN: begin
chsel_nxt = chsel;
soc_nxt = 1'b0;
usr_pwd_nxt = 1'b1;
tsen_nxt = tsen;
end
PWRDWN_TSEN: begin
chsel_nxt = chsel;
soc_nxt = 1'b0;
usr_pwd_nxt = 1'b1;
if (cmd_fetched & cmd_is_ts) // Transition to TS mode
tsen_nxt = 1'b1;
else if (cmd_fetched & cmd_is_rclb) // In recalibration mode, maintain previous TSEN setting
tsen_nxt = tsen;
else
tsen_nxt = 1'b0; // Transition to Normal mode
end
PWRDWN_DONE: begin
chsel_nxt = chsel;
soc_nxt = 1'b0;
usr_pwd_nxt = 1'b0;
tsen_nxt = tsen;
end
PWRUP_CH: begin
chsel_nxt = 5'b11110;
soc_nxt = soc;
usr_pwd_nxt = 1'b0;
tsen_nxt = tsen;
end
PWRUP_SOC: begin
chsel_nxt = chsel;
soc_nxt = 1'b1;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
SYNC1: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
WAIT: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
GETCMD_W: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PRE_CONV: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
GETCMD: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
CONV: begin
chsel_nxt = cmd_channel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
AVRG_CNT: begin
chsel_nxt = cmd_channel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
CONV_DLY1: begin
chsel_nxt = cmd_channel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PUTRESP: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PUTRESP_DLY1: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PUTRESP_DLY2: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PUTRESP_DLY3: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
WAIT_PEND: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
WAIT_PEND_DLY1: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
PUTRESP_PEND: begin
chsel_nxt = chsel;
soc_nxt = soc;
usr_pwd_nxt = usr_pwd;
tsen_nxt = tsen;
end
default: begin
chsel_nxt = 5'bx;
soc_nxt = 1'bx;
usr_pwd_nxt = 1'bx;
tsen_nxt = 1'bx;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
chsel <= 5'b11110;
soc <= 1'b0;
usr_pwd <= 1'b1;
tsen <= 1'b0;
end
else begin
chsel <= chsel_nxt;
soc <= soc_nxt;
usr_pwd <= usr_pwd_nxt;
tsen <= tsen_nxt;
end
end
//--------------------------------------------------------------------------------------------//
// Control signal from FSM arc transition
//--------------------------------------------------------------------------------------------//
// These 3 events indicate DOUT from ADC hardblock is ready to be consumed.
assign arc_conv_conv_dly1 = (ctrl_state == CONV) & (ctrl_state_nxt == CONV_DLY1);
assign arc_wait_pend_wait_pend_dly1 = (ctrl_state == WAIT_PEND) & (ctrl_state_nxt == WAIT_PEND_DLY1);
assign arc_to_avrg_cnt = ((ctrl_state == CONV) & (ctrl_state_nxt == AVRG_CNT)) | ((ctrl_state == SYNC1) & (ctrl_state_nxt == AVRG_CNT));
// CONV to CONV_DLY1 can also be trasition from SYNC1 in dual adc mode
// WAIT_PEND to WAIT_PEND_DLY1 can also be trasition from SYNC1 in dual adc mode
assign arc_sync1_conv_dly1 = (ctrl_state == SYNC1) & (ctrl_state_nxt == CONV_DLY1); // prev_ctrl_state is guaranteed by design to be CONV
assign arc_sync1_wait_pend_dly1 = (ctrl_state == SYNC1) & (ctrl_state_nxt == WAIT_PEND_DLY1); // prev_ctrl_state is guaranteed by design to be WAIT_PEND
//--------------------------------------------------------------------------------------------//
// Control signal from FSM current state
//--------------------------------------------------------------------------------------------//
assign putresp_s = (ctrl_state == PUTRESP);
assign putresp_pend_s = (ctrl_state == PUTRESP_PEND);
assign pwrdwn_s = (ctrl_state == PWRDWN);
assign pwrdwn_tsen_s = (ctrl_state == PWRDWN_TSEN);
assign avrg_cnt_s = (ctrl_state == AVRG_CNT);
assign wait_pend_dly1_s = (ctrl_state == WAIT_PEND_DLY1);
assign conv_dly1_s = (ctrl_state == CONV_DLY1);
assign conv_s = (ctrl_state == CONV);
assign putresp_dly3_s = (ctrl_state == PUTRESP_DLY3);
// Load Response when
// 1) In putresp state and there is pending response
// 2) In putresp_pend state
assign load_rsp = (putresp_s & ~cmd_is_rclb & pend) | putresp_pend_s;
assign load_dout = ((arc_conv_conv_dly1 | arc_sync1_conv_dly1) & ~cmd_is_rclb & pend) | arc_wait_pend_wait_pend_dly1 | arc_sync1_wait_pend_dly1 | ((int_timer != 8'h0) & arc_to_avrg_cnt);
assign load_cmd_ready = putresp_s;
assign arc_to_conv = (ctrl_state != CONV) & (ctrl_state != AVRG_CNT) & ~((ctrl_state == SYNC1) & (prev_ctrl_state == CONV)) & (ctrl_state_nxt == CONV);
assign arc_getcmd_w_pwrdwn = (ctrl_state == GETCMD_W) & (ctrl_state_nxt == PWRDWN);
assign arc_getcmd_pwrdwn = (ctrl_state == GETCMD) & (ctrl_state_nxt == PWRDWN);
assign load_cmd_fetched = arc_getcmd_w_pwrdwn | arc_getcmd_pwrdwn;
assign load_int_timer = arc_getcmd_w_pwrdwn | arc_getcmd_pwrdwn | arc_to_conv; // arc_to_conv is added for averaging
assign incr_int_timer = pwrdwn_s | pwrdwn_tsen_s | avrg_cnt_s;
assign arc_out_from_pwrup_soc = ((ctrl_state == PWRUP_SOC) & (ctrl_state_nxt != PWRUP_SOC) & (ctrl_state_nxt != SYNC1)) |
((ctrl_state == SYNC1) & (prev_ctrl_state == PWRUP_SOC) & (ctrl_state_nxt != PWRUP_SOC));
assign clr_cmd_fetched = arc_out_from_pwrup_soc;
//--------------------------------------------------------------------------------------------//
// Control signal required by FSM
//--------------------------------------------------------------------------------------------//
assign cmd_is_rclb = (cmd_channel == 5'b11111);
assign cmd_is_ts = (cmd_channel == 5'b10001);
assign adc_change_mode = (~prev_cmd_is_ts & cmd_is_ts) | (prev_cmd_is_ts & ~cmd_is_ts);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
prev_cmd_is_ts <= 1'b0;
else if (load_cmd_ready & ~cmd_is_rclb)
prev_cmd_is_ts <= cmd_is_ts;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cmd_fetched <= 1'b0;
else if (load_cmd_fetched)
cmd_fetched <= 1'b1;
else if (clr_cmd_fetched)
cmd_fetched <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
conv_dly1_s_flp <= 1'b0;
else
conv_dly1_s_flp <= conv_dly1_s;
end
// Using conv_dly1_s_flp instead of (ctrl_state == PUTRESP) to set the pend flag
// This is to cover cases where during recalibration the state can go from PWRUP_SOC to PUTRESP directly
// In averaging pend is set at pt 63, leaving pt 64 to be captured at WAIT PEND state (consistent with non-averaging)
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
pend <= 1'b0;
else if (conv_dly1_s_flp)
pend <= 1'b1;
else if (wait_pend_dly1_s)
pend <= 1'b0;
end
//------------------------------------------------------------------------------------------------------------------//
// Register the DOUT bus from ADC hardblock
// This eliminates sampling invalid DOUT bus (validity of DOUT bus is limited by TDAC timing spec of ADC hardblock)
// if latency of load_rsp increases in future
// Example: Previously DOUT is consumed by the design 2 clocks from falling edge of EOC
// Without this register, to support averaging, DOUT is consumed by the design 4 clocks from falling edge of EOC
// (additional 2 clocks for RAM accesses)
//------------------------------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
dout_flp <= 12'd0;
else if (load_dout)
dout_flp <= dout;
end
//--------------------------------------------------------------------------------------------//
// Internal timer to ensure soft power down stays at least for 1us
// Also used as AVRG counter
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
int_timer <= 8'h0;
else if (load_int_timer)
int_timer <= 8'h0;
else if (incr_int_timer)
int_timer <= int_timer + 8'h1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
avrg_cnt_done <= 1'b0;
else if ((int_timer == (NUM_AVRG_POINTS - 8'd1)) & conv_s)
avrg_cnt_done <= 1'b1;
else if (clear_avrg_cnt_done)
avrg_cnt_done <= 1'b0;
end
assign clear_avrg_cnt_done = putresp_dly3_s & ~cmd_valid; // Restart 64 point sampling if continuous sample is broken
//--------------------------------------------------------------------------------------------//
// Store up CMD information due to
// Resp is always one clk_dft later from current cmd (ADC hardblock characteristic)
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cmd_channel_dly <= 5'h0;
cmd_sop_dly <= 1'b0;
cmd_eop_dly <= 1'b0;
end
else if (load_cmd_ready) begin
cmd_channel_dly <= cmd_channel;
cmd_sop_dly <= cmd_sop;
cmd_eop_dly <= cmd_eop;
end
end
//--------------------------------------------------------------------------------------------//
// Averaging logic
//
//--------------------------------------------------------------------------------------------//
// Only temperature sensing mode has averaging feature
assign avrg_enable = cmd_is_ts;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
avrg_sum <= 18'h0;
else if (clear_avrg_sum)
avrg_sum <= 18'h0;
else if (add_avrg_sum_run)
avrg_sum <= (avrg_sum - fifo_q) + {6'h0, dout_flp};
else if (add_avrg_sum)
avrg_sum <= avrg_sum + {6'h0, dout_flp};
end
assign add_avrg_sum = ((int_timer != 8'h0) & avrg_cnt_s) | // when int_timer == 0 the DOUT is not yet ready (ADC hard block introduce one ADC clock delay in the ADC output)
(conv_dly1_s & avrg_enable & pend) | // cover averaging pt 64 and beyond (in back 2 back TS scenario)
(conv_dly1_s & avrg_enable & ~pend & ~frst_64_ptr_done) | // cover averaging pt 63
(wait_pend_dly1_s & prev_cmd_is_ts); // cover averaging pt 64 and beyond (in switching between ts to non-ts scenario)
assign add_avrg_sum_run = set_frst_64_ptr_done & frst_64_ptr_done;
assign clear_avrg_sum = ~avrg_cnt_done & putresp_pend_s; // Restart 64 point sampling if continuous sample is broken
// Not avrg_cnt_done is to ensure put response pending state is caused by broken continuous sampling
assign set_frst_64_ptr_done = (wait_pend_dly1_s & prev_cmd_is_ts) | // set at averaging pt 64 and beyond (where next conversion is non-ts)
(conv_dly1_s & avrg_enable & pend); // set at averaging pt 64 and beyond (where next conversion is ts)
// No harm to set this signal beyond pt 64
assign clear_frst_64_ptr_done = clear_avrg_sum;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
frst_64_ptr_done <= 1'b0;
else if (set_frst_64_ptr_done)
frst_64_ptr_done <= 1'b1;
else if (clear_frst_64_ptr_done)
frst_64_ptr_done <= 1'b0;
end
assign fifo_sclr = clear_avrg_sum;
assign fifo_rdreq = (((arc_wait_pend_wait_pend_dly1 | arc_sync1_wait_pend_dly1) & prev_cmd_is_ts) | ((arc_conv_conv_dly1 | arc_sync1_conv_dly1) & avrg_enable & pend)) & frst_64_ptr_done;
assign fifo_wrreq = ((int_timer != 8'h0) & avrg_cnt_s) |
(conv_dly1_s & avrg_enable & pend) |
(conv_dly1_s & avrg_enable & ~pend & ~frst_64_ptr_done) |
(wait_pend_dly1_s & prev_cmd_is_ts);
altera_modular_adc_control_avrg_fifo ts_avrg_fifo (
.clock (clk),
.data (dout_flp),
.rdreq (fifo_rdreq),
.wrreq (fifo_wrreq),
.sclr (fifo_sclr),
.empty (),
.full (),
.q (fifo_q)
);
//--------------------------------------------------------------------------------------------//
// Avalon ST response interface output register
// Avalon ST command interface output register (cmd_ready)
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rsp_valid <= 1'b0;
rsp_channel <= 5'h0;
rsp_data <= 12'h0;
rsp_sop <= 1'b0;
rsp_eop <= 1'b0;
end
else if (load_rsp) begin
rsp_valid <= 1'b1;
rsp_channel <= cmd_channel_dly;
rsp_data <= rsp_data_nxt;
rsp_sop <= cmd_sop_dly;
rsp_eop <= cmd_eop_dly;
end
else begin
rsp_valid <= 1'b0;
rsp_channel <= 5'h0;
rsp_data <= 12'h0;
rsp_sop <= 1'b0;
rsp_eop <= 1'b0;
end
end
generate
if (is_this_first_or_second_adc == 2) begin
assign rsp_data_nxt = prev_cmd_is_ts ? 12'h0 : dout_flp; // For ADC2, mask out TSD value since TSD is not supported in ADC2
end
else begin
assign rsp_data_nxt = prev_cmd_is_ts ? avrg_sum[17:6] : dout_flp;
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cmd_ready <= 1'b0;
else if (load_cmd_ready)
cmd_ready <= 1'b1;
else
cmd_ready <= 1'b0;
end
endmodule |
module myadc_modular_adc_0 (
input wire clock_clk, // clock.clk
input wire reset_sink_reset_n, // reset_sink.reset_n
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire command_valid, // command.valid
input wire [4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
output wire response_valid, // response.valid
output wire [4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
altera_modular_adc_control #(
.clkdiv (2),
.tsclkdiv (1),
.tsclksel (1),
.hard_pwd (0),
.prescalar (0),
.refsel (1),
.device_partname_fivechar_prefix ("10M08"),
.is_this_first_or_second_adc (1),
.analog_input_pin_mask (65536),
.dual_adc_mode (0)
) control_internal (
.clk (clock_clk), // clock.clk
.cmd_valid (command_valid), // command.valid
.cmd_channel (command_channel), // .channel
.cmd_sop (command_startofpacket), // .startofpacket
.cmd_eop (command_endofpacket), // .endofpacket
.cmd_ready (command_ready), // .ready
.rst_n (reset_sink_reset_n), // reset_sink.reset_n
.rsp_valid (response_valid), // response.valid
.rsp_channel (response_channel), // .channel
.rsp_data (response_data), // .data
.rsp_sop (response_startofpacket), // .startofpacket
.rsp_eop (response_endofpacket), // .endofpacket
.clk_in_pll_c0 (adc_pll_clock_clk), // adc_pll_clock.clk
.clk_in_pll_locked (adc_pll_locked_export), // conduit_end.export
.sync_valid (), // (terminated)
.sync_ready (1'b0) // (terminated)
);
endmodule |
module user_design(clk, rst, exception, input_rs232_rx, input_gps_rx, input_gps_count, input_rs232_rx_stb, input_gps_rx_stb, input_gps_count_stb, input_rs232_rx_ack, input_gps_rx_ack, input_gps_count_ack, output_tx_ctl, output_rs232_tx, output_leds, output_gps_tx, output_tx_freq, output_tx_am, output_tx_ctl_stb, output_rs232_tx_stb, output_leds_stb, output_gps_tx_stb, output_tx_freq_stb, output_tx_am_stb, output_tx_ctl_ack, output_rs232_tx_ack, output_leds_ack, output_gps_tx_ack, output_tx_freq_ack, output_tx_am_ack);
input clk;
input rst;
output exception;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_gps_rx;
input input_gps_rx_stb;
output input_gps_rx_ack;
input [31:0] input_gps_count;
input input_gps_count_stb;
output input_gps_count_ack;
output [31:0] output_tx_ctl;
output output_tx_ctl_stb;
input output_tx_ctl_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_gps_tx;
output output_gps_tx_stb;
input output_gps_tx_ack;
output [31:0] output_tx_freq;
output output_tx_freq_stb;
input output_tx_freq_ack;
output [31:0] output_tx_am;
output output_tx_am_stb;
input output_tx_am_ack;
wire exception_140447914110056;
main_0 main_0_140447914110056(
.clk(clk),
.rst(rst),
.exception(exception_140447914110056),
.input_gps_count(input_gps_count),
.input_gps_count_stb(input_gps_count_stb),
.input_gps_count_ack(input_gps_count_ack),
.input_gps_rx(input_gps_rx),
.input_gps_rx_stb(input_gps_rx_stb),
.input_gps_rx_ack(input_gps_rx_ack),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_leds(output_leds),
.output_leds_stb(output_leds_stb),
.output_leds_ack(output_leds_ack),
.output_freq_out(output_tx_freq),
.output_freq_out_stb(output_tx_freq_stb),
.output_freq_out_ack(output_tx_freq_ack),
.output_gps_tx(output_gps_tx),
.output_gps_tx_stb(output_gps_tx_stb),
.output_gps_tx_ack(output_gps_tx_ack),
.output_ctl_out(output_tx_ctl),
.output_ctl_out_stb(output_tx_ctl_stb),
.output_ctl_out_ack(output_tx_ctl_ack),
.output_am_out(output_tx_am),
.output_am_out_stb(output_tx_am_stb),
.output_am_out_ack(output_tx_am_ack));
assign exception = exception_140447914110056;
endmodule |
module top(
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
input wire [3:0] sw, // four switches
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output reg [3:0] VGA_R, // 4-bit VGA red output
output reg [3:0] VGA_G, // 4-bit VGA green output
output reg [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 25 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK)
{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire blanking; // high within the blanking period
wire active; // high during active pixel drawing
wire screenend; // high for one tick at the end of screen
wire animate; // high for one tick at end of active drawing
vga320x180 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y),
.o_blanking(blanking),
.o_active(active),
.o_screenend(screenend),
.o_animate(animate)
);
// VRAM frame buffers (read-write)
localparam SCREEN_WIDTH = 320;
localparam SCREEN_HEIGHT = 180;
localparam VRAM_DEPTH = SCREEN_WIDTH * SCREEN_HEIGHT;
localparam VRAM_A_WIDTH = 16; // 2^16 > 320 x 180
localparam VRAM_D_WIDTH = 8; // colour bits per pixel
reg [VRAM_A_WIDTH-1:0] address_a, address_b;
reg [VRAM_D_WIDTH-1:0] datain_a, datain_b;
wire [VRAM_D_WIDTH-1:0] dataout_a, dataout_b;
reg we_a = 0, we_b = 1; // write enable bit
// frame buffer A VRAM
sram #(
.ADDR_WIDTH(VRAM_A_WIDTH),
.DATA_WIDTH(VRAM_D_WIDTH),
.DEPTH(VRAM_DEPTH),
.MEMFILE(""))
vram_a (
.i_addr(address_a),
.i_clk(CLK),
.i_write(we_a),
.i_data(datain_a),
.o_data(dataout_a)
);
// frame buffer B VRAM
sram #(
.ADDR_WIDTH(VRAM_A_WIDTH),
.DATA_WIDTH(VRAM_D_WIDTH),
.DEPTH(VRAM_DEPTH),
.MEMFILE(""))
vram_b (
.i_addr(address_b),
.i_clk(CLK),
.i_write(we_b),
.i_data(datain_b),
.o_data(dataout_b)
);
// sprite buffer (read-only)
localparam SPRITE_SIZE = 32; // dimensions of square sprites in pixels
localparam SPRITE_COUNT = 8; // number of sprites in buffer
localparam SPRITEBUF_D_WIDTH = 8; // colour bits per pixel
localparam SPRITEBUF_DEPTH = SPRITE_SIZE * SPRITE_SIZE * SPRITE_COUNT;
localparam SPRITEBUF_A_WIDTH = 13; // 2^13 == 8,096 == 32 x 256
reg [SPRITEBUF_A_WIDTH-1:0] address_s;
wire [SPRITEBUF_D_WIDTH-1:0] dataout_s;
// sprite buffer memory
sram #(
.ADDR_WIDTH(SPRITEBUF_A_WIDTH),
.DATA_WIDTH(SPRITEBUF_D_WIDTH),
.DEPTH(SPRITEBUF_DEPTH),
.MEMFILE("sprites.mem"))
spritebuf (
.i_addr(address_s),
.i_clk(CLK),
.i_write(0), // read only
.i_data(0),
.o_data(dataout_s)
);
reg [11:0] palette [0:255]; // 256 x 12-bit colour palette entries
reg [11:0] colour;
initial begin
$display("Loading palette.");
$readmemh("sprites_palette.mem", palette);
end
// sprites to load and position of player sprite in frame
localparam SPRITE_BG_INDEX = 7; // background sprite
localparam SPRITE_PL_INDEX = 0; // player sprite
localparam SPRITE_BG_OFFSET = SPRITE_BG_INDEX * SPRITE_SIZE * SPRITE_SIZE;
localparam SPRITE_PL_OFFSET = SPRITE_PL_INDEX * SPRITE_SIZE * SPRITE_SIZE;
localparam SPRITE_PL_X = SCREEN_WIDTH - SPRITE_SIZE >> 1; // centre
localparam SPRITE_PL_Y = SCREEN_HEIGHT - SPRITE_SIZE; // bottom
reg [9:0] draw_x;
reg [8:0] draw_y;
reg [9:0] pl_x = SPRITE_PL_X;
reg [9:0] pl_y = SPRITE_PL_Y;
reg [9:0] pl_pix_x;
reg [8:0] pl_pix_y;
// pipeline registers for for address calculation
reg [VRAM_A_WIDTH-1:0] address_fb1;
reg [VRAM_A_WIDTH-1:0] address_fb2;
always @ (posedge CLK)
begin
// reset drawing
if (rst)
begin
draw_x <= 0;
draw_y <= 0;
pl_x <= SPRITE_PL_X;
pl_y <= SPRITE_PL_Y;
pl_pix_x <= 0;
pl_pix_y <= 0;
end
// draw background
if (address_fb1 < VRAM_DEPTH)
begin
if (draw_x < SCREEN_WIDTH)
draw_x <= draw_x + 1;
else
begin
draw_x <= 0;
draw_y <= draw_y + 1;
end
// calculate address of sprite and frame buffer (with pipeline)
address_s <= SPRITE_BG_OFFSET +
(SPRITE_SIZE * draw_y[4:0]) + draw_x[4:0];
address_fb1 <= (SCREEN_WIDTH * draw_y) + draw_x;
address_fb2 <= address_fb1;
if (we_a)
begin
address_a <= address_fb2;
datain_a <= dataout_s;
end
else
begin
address_b <= address_fb2;
datain_b <= dataout_s;
end
end
// draw player ship
if (address_fb1 >= VRAM_DEPTH) // background drawing is finished
begin
if (pl_pix_y < SPRITE_SIZE)
begin
if (pl_pix_x < SPRITE_SIZE - 1)
pl_pix_x <= pl_pix_x + 1;
else
begin
pl_pix_x <= 0;
pl_pix_y <= pl_pix_y + 1;
end
address_s <= SPRITE_PL_OFFSET
+ (SPRITE_SIZE * pl_pix_y) + pl_pix_x;
address_fb1 <= SCREEN_WIDTH * (pl_y + pl_pix_y)
+ pl_x + pl_pix_x;
address_fb2 <= address_fb1;
if (we_a)
begin
address_a <= address_fb2;
datain_a <= dataout_s;
end
else
begin
address_b <= address_fb2;
datain_b <= dataout_s;
end
end
end
if (pix_stb) // once per pixel
begin
if (we_a) // when drawing to A, output from B
begin
address_b <= y * SCREEN_WIDTH + x;
colour <= active ? palette[dataout_b] : 0;
end
else // otherwise output from A
begin
address_a <= y * SCREEN_WIDTH + x;
colour <= active ? palette[dataout_a] : 0;
end
if (screenend) // switch active buffer once per frame
begin
we_a <= ~we_a;
we_b <= ~we_b;
// reset background position at start of frame
draw_x <= 0;
draw_y <= 0;
// reset player position
pl_pix_x <= 0;
pl_pix_y <= 0;
// reset frame address
address_fb1 <= 0;
end
end
VGA_R <= colour[11:8];
VGA_G <= colour[7:4];
VGA_B <= colour[3:0];
end
endmodule |
module vga320x180(
input wire i_clk, // base clock
input wire i_pix_stb, // pixel clock strobe
input wire i_rst, // reset: restarts frame
output wire o_hs, // horizontal sync
output wire o_vs, // vertical sync
output wire o_blanking, // high during blanking interval
output wire o_active, // high during active pixel drawing
output wire o_screenend, // high for one tick at the end of screen
output wire o_animate, // high for one tick at end of active drawing
output wire [9:0] o_x, // current pixel x position
output wire [8:0] o_y // current pixel y position
);
// VGA timings https://timetoexplore.net/blog/video-timings-vga-720p-1080p
localparam HS_STA = 16; // horizontal sync start
localparam HS_END = 16 + 96; // horizontal sync end
localparam HA_STA = 16 + 96 + 48; // horizontal active pixel start
localparam VS_STA = 480 + 10; // vertical sync start
localparam VS_END = 480 + 10 + 2; // vertical sync end
localparam VA_STA = 60; // vertical active pixel start
localparam VA_END = 420; // vertical active pixel end
localparam LINE = 800; // complete line (pixels)
localparam SCREEN = 525; // complete screen (lines)
reg [9:0] h_count; // line position
reg [9:0] v_count; // screen position
// generate sync signals (active low for 640x480)
assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END));
assign o_vs = ~((v_count >= VS_STA) & (v_count < VS_END));
// keep x and y bound within the active pixels
assign o_x = ((h_count < HA_STA) ? 0 : (h_count - HA_STA)) >> 1;
assign o_y = ((v_count >= VA_END) ?
(VA_END - VA_STA - 1) : (v_count - VA_STA)) >> 1;
// blanking: high within the blanking period
assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));
// active: high during active pixel drawing
assign o_active = ~((h_count < HA_STA) |
(v_count > VA_END - 1) |
(v_count < VA_STA));
// screenend: high for one tick at the end of the screen
assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));
// animate: high for one tick at the end of the final active pixel line
assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));
always @ (posedge i_clk)
begin
if (i_rst) // reset to start of frame
begin
h_count <= 0;
v_count <= 0;
end
if (i_pix_stb) // once per pixel
begin
if (h_count == LINE) // end of line
begin
h_count <= 0;
v_count <= v_count + 1;
end
else
h_count <= h_count + 1;
if (v_count == SCREEN) // end of screen
v_count <= 0;
end
end
endmodule |
module top(
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output reg [3:0] VGA_R, // 4-bit VGA red output
output reg [3:0] VGA_G, // 4-bit VGA green output
output reg [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 25 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK)
{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire active; // high during active pixel drawing
vga640x360 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y),
.o_active(active)
);
// VRAM frame buffers (read-write)
localparam SCREEN_WIDTH = 640;
localparam SCREEN_HEIGHT = 360;
localparam VRAM_DEPTH = SCREEN_WIDTH * SCREEN_HEIGHT;
localparam VRAM_A_WIDTH = 18; // 2^18 > 640 x 360
localparam VRAM_D_WIDTH = 6; // colour bits per pixel
reg [VRAM_A_WIDTH-1:0] address;
wire [VRAM_D_WIDTH-1:0] dataout;
sram #(
.ADDR_WIDTH(VRAM_A_WIDTH),
.DATA_WIDTH(VRAM_D_WIDTH),
.DEPTH(VRAM_DEPTH),
.MEMFILE("game.mem")) // bitmap to load
vram (
.i_addr(address),
.i_clk(CLK),
.i_write(0), // we're always reading
.i_data(0),
.o_data(dataout)
);
reg [11:0] palette [0:63]; // 64 x 12-bit colour palette entries
reg [11:0] colour;
initial begin
$display("Loading palette.");
$readmemh("game_palette.mem", palette); // bitmap palette to load
end
always @ (posedge CLK)
begin
address <= y * SCREEN_WIDTH + x;
if (active)
colour <= palette[dataout];
else
colour <= 0;
VGA_R <= colour[11:8];
VGA_G <= colour[7:4];
VGA_B <= colour[3:0];
end
endmodule |
module vga800x600(
input wire i_clk, // base clock
input wire i_pix_stb, // pixel clock strobe
input wire i_rst, // reset: restarts frame
output wire o_hs, // horizontal sync
output wire o_vs, // vertical sync
output wire o_blanking, // high during blanking interval
output wire o_active, // high during active pixel drawing
output wire o_screenend, // high for one tick at the end of screen
output wire o_animate, // high for one tick at end of active drawing
output wire [10:0] o_x, // current pixel x position
output wire [9:0] o_y // current pixel y position
);
// VGA timings https://timetoexplore.net/blog/video-timings-vga-720p-1080p
localparam HS_STA = 40; // horizontal sync start
localparam HS_END = 40 + 128; // horizontal sync end
localparam HA_STA = 40 + 128 + 88; // horizontal active pixel start
localparam VS_STA = 600 + 1; // vertical sync start
localparam VS_END = 600 + 1 + 4; // vertical sync end
localparam VA_END = 600; // vertical active pixel end
localparam LINE = 1056; // complete line (pixels)
localparam SCREEN = 628; // complete screen (lines)
reg [10:0] h_count; // line position
reg [9:0] v_count; // screen position
// generate sync signals (active high for 800x600)
assign o_hs = ((h_count >= HS_STA) & (h_count < HS_END));
assign o_vs = ((v_count >= VS_STA) & (v_count < VS_END));
// keep x and y bound within the active pixels
assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA);
assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count);
// blanking: high within the blanking period
assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));
// active: high during active pixel drawing
assign o_active = ~((h_count < HA_STA) | (v_count > VA_END - 1));
// screenend: high for one tick at the end of the screen
assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));
// animate: high for one tick at the end of the final active pixel line
assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));
always @ (posedge i_clk)
begin
if (i_rst) // reset to start of frame
begin
h_count <= 0;
v_count <= 0;
end
if (i_pix_stb) // once per pixel
begin
if (h_count == LINE) // end of line
begin
h_count <= 0;
v_count <= v_count + 1;
end
else
h_count <= h_count + 1;
if (v_count == SCREEN) // end of screen
v_count <= 0;
end
end
endmodule |
module top(
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
output wire [3:0] VGA_G, // 4-bit VGA green output
output wire [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 40 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK)
{pix_stb, cnt} <= cnt + 16'h6666; // divide by 2.5: (2^16)/2.5 = 0x6666
wire [10:0] x; // current pixel x position: 11-bit value: 0-2047
wire [9:0] y; // current pixel y position: 10-bit value: 0-1023
vga800x600 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y)
);
// Six overlapping squares
wire sq_a, sq_b, sq_c, sq_d, sq_e, sq_f;
assign sq_a = ((x > 120) & (y > 20) & (x < 280) & (y < 180)) ? 1 : 0;
assign sq_b = ((x > 200) & (y > 100) & (x < 360) & (y < 260)) ? 1 : 0;
assign sq_c = ((x > 280) & (y > 180) & (x < 440) & (y < 340)) ? 1 : 0;
assign sq_d = ((x > 360) & (y > 260) & (x < 520) & (y < 420)) ? 1 : 0;
assign sq_e = ((x > 440) & (y > 340) & (x < 600) & (y < 500)) ? 1 : 0;
assign sq_f = ((x > 520) & (y > 420) & (x < 680) & (y < 580)) ? 1 : 0;
assign VGA_R[3] = sq_b | sq_e; // squares b and e are red
assign VGA_G[3] = sq_a | sq_d; // squares a and d are green
assign VGA_B[3] = sq_c | sq_f; // squares c and f are blue
endmodule |
module top(
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
output wire [3:0] VGA_G, // 4-bit VGA green output
output wire [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire animate; // high when we're ready to animate at end of drawing
// generate a 25 MHz pixel strobe
reg [15:0] cnt = 0;
reg pix_stb = 0;
always @(posedge CLK)
{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
vga640x480 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y),
.o_animate(animate)
);
wire sq_a, sq_b, sq_c;
wire [11:0] sq_a_x1, sq_a_x2, sq_a_y1, sq_a_y2; // 12-bit values: 0-4095
wire [11:0] sq_b_x1, sq_b_x2, sq_b_y1, sq_b_y2;
wire [11:0] sq_c_x1, sq_c_x2, sq_c_y1, sq_c_y2;
square #(.IX(160), .IY(120), .H_SIZE(60)) sq_a_anim (
.i_clk(CLK),
.i_ani_stb(pix_stb),
.i_rst(rst),
.i_animate(animate),
.o_x1(sq_a_x1),
.o_x2(sq_a_x2),
.o_y1(sq_a_y1),
.o_y2(sq_a_y2)
);
square #(.IX(320), .IY(240), .IY_DIR(0)) sq_b_anim (
.i_clk(CLK),
.i_ani_stb(pix_stb),
.i_rst(rst),
.i_animate(animate),
.o_x1(sq_b_x1),
.o_x2(sq_b_x2),
.o_y1(sq_b_y1),
.o_y2(sq_b_y2)
);
square #(.IX(480), .IY(360), .H_SIZE(100)) sq_c_anim (
.i_clk(CLK),
.i_ani_stb(pix_stb),
.i_rst(rst),
.i_animate(animate),
.o_x1(sq_c_x1),
.o_x2(sq_c_x2),
.o_y1(sq_c_y1),
.o_y2(sq_c_y2)
);
assign sq_a = ((x > sq_a_x1) & (y > sq_a_y1) &
(x < sq_a_x2) & (y < sq_a_y2)) ? 1 : 0;
assign sq_b = ((x > sq_b_x1) & (y > sq_b_y1) &
(x < sq_b_x2) & (y < sq_b_y2)) ? 1 : 0;
assign sq_c = ((x > sq_c_x1) & (y > sq_c_y1) &
(x < sq_c_x2) & (y < sq_c_y2)) ? 1 : 0;
assign VGA_R[3] = sq_a; // square a is red
assign VGA_G[3] = sq_b; // square b is green
assign VGA_B[3] = sq_c; // square c is blue
endmodule |
module top(
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
output wire [3:0] VGA_G, // 4-bit VGA green output
output wire [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 25 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK)
{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
vga640x480 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y)
);
// Four overlapping squares
wire sq_a, sq_b, sq_c, sq_d;
assign sq_a = ((x > 120) & (y > 40) & (x < 280) & (y < 200)) ? 1 : 0;
assign sq_b = ((x > 200) & (y > 120) & (x < 360) & (y < 280)) ? 1 : 0;
assign sq_c = ((x > 280) & (y > 200) & (x < 440) & (y < 360)) ? 1 : 0;
assign sq_d = ((x > 360) & (y > 280) & (x < 520) & (y < 440)) ? 1 : 0;
assign VGA_R[3] = sq_b; // square b is red
assign VGA_G[3] = sq_a | sq_d; // squares a and d are green
assign VGA_B[3] = sq_c; // square c is blue
endmodule |
module osr (
input clk,
input penable,
input reset,
input stalled,
input [31:0] din,
input [4:0] shift,
input dir, // 0 - left, 1 - right
input set,
input do_shift,
output [31:0] dout,
output [5:0] shift_count
);
reg [31:0] shift_reg;
reg [5:0] count;
// A shift value of 0 means shift 32
wire [5:0] shift_val = shift == 0 ? 32 : shift;
// Calculate the 64-bit value of the shift register after a shift
wire [63:0] shift64 = dir ? {shift_reg, 32'b0} >> shift_val : {32'b0, shift_reg} << shift_val;
// Calculate the right-aligned shifted out value
wire [31:0] shift_out = dir ? (shift64[31:0] >> (32 - shift_val)) : shift64[63:32];
// Calculate the new shift register value after a shift
wire [31:0] new_shift = dir ? shift64[63:32] : shift64[31:0];
always @(posedge clk) begin
if (reset) begin
shift_reg <= 0;
count <= 32; // Empty (read to trigger auto-pull)
end else if (penable && !stalled) begin
if (set) begin
shift_reg <= din;
count <= 0;
end else if (do_shift) begin
shift_reg <= new_shift;
count <= count + shift_val > 32 ? 32 : count + shift_val;
end
end
end
// The output value is the amount shifted out if do_shift ia active otherwise the current shift register
assign dout = do_shift ? shift_out : shift_reg;
assign shift_count = count;
endmodule |
module pc (
input clk,
input penable,
input reset,
input [4:0] din,
input jmp,
input [4:0] pend,
input stalled,
input [4:0] wrap_target,
output [4:0] dout
);
reg [4:0] index = 0;
assign dout = (penable && !stalled) ? (jmp ? din : index == pend ? wrap_target : index + 1) : index;
always @(posedge clk) begin
if (reset)
index <= 0;
else if (penable && !stalled) begin
if (jmp)
index <= din;
else
index <= index == pend ? wrap_target : index + 1;
end
end
endmodule |
module fifo (
input clk,
input reset,
input push,
input pull,
input [31:0] din,
output [31:0] dout,
output empty,
output full,
output [2:0] level
);
reg [31:0] arr [0:3];
reg [1:0] first;
reg [1:0] next;
reg [2:0] count;
wire do_pull = pull && !empty;
wire do_push = push && !full;
always @(posedge clk) begin
if (reset) begin
first <= 0;
next <= 0;
count <= 0;
end else begin
if (do_push) begin
next <= next + 1;
arr[next] <= din;
if (!do_pull) count <= count + 1;
end
if (do_pull) begin
first <= first + 1;
if (!do_push) count <= count - 1;
end
end
end
assign empty = count == 0;
assign full = count == 4;
assign dout = arr[first];
assign level = count;
endmodule |
module decoder (
input [15:0] instr,
input [2:0] sideset_bits,
input sideset_enable_bit,
output [2:0] op,
output [2:0] op1,
output [4:0] op2,
output [4:0] delay,
output [4:0] side_set,
output sideset_enabled
);
wire [2:0] delay_bits = 5 - sideset_bits;
assign op = instr[15:13];
assign op1 = instr[7:5];
assign op2 = instr[4:0];
assign delay = (instr[12:8] << sideset_bits) >> sideset_bits;
assign side_set = instr[12:8] << sideset_enable_bit >> sideset_enable_bit + delay_bits;
assign sideset_enabled = sideset_enable_bit ? instr[12] : 1;
endmodule |
module scratch (
input clk,
input penable,
input reset,
input stalled,
input [31:0] din,
input set,
input dec,
output [31:0] dout
);
reg [31:0] val;
assign dout = val;
always @(posedge clk) begin
if (reset)
val <= 0;
else if (penable && !stalled) begin
if (set)
val <= din;
else if (dec)
val <= val - 1;
end
end
endmodule |
module divider (
input clk,
input reset,
input [23:0] div,
input use_divider,
output penable,
output pclk
);
reg [23:0] div_counter;
reg pen;
reg old_pen;
always @(posedge clk) begin
if (reset) begin
div_counter <= 0;
pen <= 1;
old_pen <= 0;
end else begin
if (use_divider) begin
old_pen <= pen;
div_counter <= div_counter + 256;
if (div_counter >= div - 256)
div_counter <= div_counter - (div - 256);
pen <= div_counter < (div >> 1);
end
end
end
assign penable = pen & ~old_pen;
assign pclk = pen;
endmodule |
module pio #(
parameter NUM_MACHINES = 4
) (
input clk,
input reset,
input [1:0] mindex,
input [31:0] din,
input [4:0] index,
input [3:0] action,
input [31:0] gpio_in,
output reg [31:0] gpio_out,
output reg [31:0] gpio_dir,
output reg [31:0] dout,
output irq0,
output irq1,
output [3:0] tx_full,
output [3:0] rx_empty,
output [3:0] pclk
);
// Shared instructions memory
reg [15:0] instr [0:31];
// Configuration
reg [NUM_MACHINES-1:0] en;
reg [NUM_MACHINES-1:0] auto_pull;
reg [NUM_MACHINES-1:0] auto_push;
reg [NUM_MACHINES-1:0] sideset_enable_bit;
reg [NUM_MACHINES-1:0] in_shift_dir;
reg [NUM_MACHINES-1:0] out_shift_dir;
reg [NUM_MACHINES-1:0] status_sel;
reg [NUM_MACHINES-1:0] out_sticky;
reg [NUM_MACHINES-1:0] inline_out_en;
reg [NUM_MACHINES-1:0] side_pindir;
reg [NUM_MACHINES-1:0] exec_stalled;
reg [NUM_MACHINES-1:0] use_divider;
// Control
reg [NUM_MACHINES-1:0] imm;
reg [NUM_MACHINES-1:0] push;
reg [NUM_MACHINES-1:0] pull;
reg [NUM_MACHINES-1:0] restart;
reg [NUM_MACHINES-1:0] clkdiv_restart;
// Configuration
reg [4:0] pend [0:NUM_MACHINES-1];
reg [4:0] wrap_target [0:NUM_MACHINES-1];
reg [23:0] div [0:NUM_MACHINES-1];
reg [4:0] pins_in_base [0:NUM_MACHINES-1];
reg [4:0] pins_out_base [0:NUM_MACHINES-1];
reg [4:0] pins_set_base [0:NUM_MACHINES-1];
reg [4:0] pins_side_base [0:NUM_MACHINES-1];
reg [5:0] pins_out_count [0:NUM_MACHINES-1];
reg [2:0] pins_set_count [0:NUM_MACHINES-1];
reg [2:0] pins_side_count [0:NUM_MACHINES-1];
reg [4:0] isr_threshold [0:NUM_MACHINES-1];
reg [4:0] osr_threshold [0:NUM_MACHINES-1];
reg [3:0] status_n [0:NUM_MACHINES-1];
reg [4:0] out_en_sel [0:NUM_MACHINES-1];
reg [4:0] jmp_pin [0:NUM_MACHINES-1];
(* mem2reg *) reg [15:0] curr_instr [0:NUM_MACHINES-1];
// Output from machines and fifos
wire [31:0] output_pins [0:NUM_MACHINES-1];
reg [31:0] output_pins_prev [0:NUM_MACHINES-1];
wire [31:0] pin_directions [0:NUM_MACHINES-1];
reg [31:0] pin_directions_prev [0:NUM_MACHINES-1];
wire [4:0] pc [0:NUM_MACHINES-1];
wire [31:0] mdin [0:NUM_MACHINES-1];
wire [31:0] mdout [0:NUM_MACHINES-1];
wire [31:0] pdout [0:NUM_MACHINES-1];
wire [7:0] irq_flags_out [0:NUM_MACHINES-1];
wire [2:0] rx_level [0:NUM_MACHINES-1];
wire [2:0] tx_level [0:NUM_MACHINES-1];
wire [NUM_MACHINES-1:0] mempty;
wire [NUM_MACHINES-1:0] mfull;
wire [NUM_MACHINES-1:0] mpush;
wire [NUM_MACHINES-1:0] mpull;
integer i;
integer gpio_idx;
// Synchronous fetch of current instruction for each machine
always @(posedge clk) begin
for(i=0;i<NUM_MACHINES;i=i+1) begin
curr_instr[i] <= instr[pc[i]];
// Coalesce output pins, making sure the highest PIO wins
for(gpio_idx=0;gpio_idx<32;gpio_idx=gpio_idx+1) begin
output_pins_prev[i][gpio_idx] <= output_pins[i][gpio_idx];
if (output_pins[i][gpio_idx] != output_pins_prev[i][gpio_idx]) begin
gpio_out[gpio_idx] <= output_pins[i][gpio_idx];
end
pin_directions_prev[i][gpio_idx] <= pin_directions[i][gpio_idx];
if (pin_directions[i][gpio_idx] != pin_directions_prev[i][gpio_idx]) begin
gpio_dir[gpio_idx] <= pin_directions[i][gpio_idx];
end
end
end
end
// Actions
localparam NONE = 0;
localparam INSTR = 1;
localparam PEND = 2;
localparam PULL = 3;
localparam PUSH = 4;
localparam GRPS = 5;
localparam EN = 6;
localparam DIV = 7;
localparam SIDES = 8;
localparam IMM = 9;
localparam SHIFT = 10;
// Configure and control machines
always @(posedge clk) begin
if (reset) begin
en <= 0;
auto_pull <= 0;
auto_push <= 0;
sideset_enable_bit <= 0;
in_shift_dir <= 0;
out_shift_dir <= 0;
status_sel <= 0;
out_sticky <= 0;
inline_out_en <= 0;
side_pindir <= 0;
exec_stalled <= 0;
for(i=0;i<NUM_MACHINES;i++) begin
pend[i] <= 0;
wrap_target[i] <= 0;
div[i] <= 0; // no clock divider
pins_in_base[i] <= 0;
pins_out_base[i] <= 0;
pins_set_base[i] <= 0;
pins_side_base[i] <= 0;
pins_out_count[i] <= 0;
pins_set_count[i] <= 5;
pins_side_count[i] <= 0;
isr_threshold[i] <= 0;
osr_threshold[i] <= 0;
status_n[i] <= 0;
out_en_sel[i] <= 0;
jmp_pin[i] <= 0;
output_pins_prev[i] <= 0;
pin_directions_prev[i] <= 0;
end
gpio_out <= 0;
gpio_dir <= 0;
end else begin
pull <= 0;
push <= 0;
imm <= 0;
restart <= 0;
clkdiv_restart <= 0;
case (action)
INSTR: instr[index] <= din[15:0]; // Set an instruction. INSTR_MEM registers
PEND : begin // Configure pend, wrap_target, etc.
status_n[mindex] <= din[3:0];
status_sel[mindex] <= din[4];
wrap_target[mindex] <= din[11:7];
pend[mindex] <= din[16:12];
out_sticky[mindex] <= din[17];
inline_out_en[mindex] <= din[18];
out_en_sel[mindex] <= din[23:19];
jmp_pin[mindex] <= din[28:24];
side_pindir[mindex] <= din[29];
sideset_enable_bit[mindex] <= din[30];
exec_stalled[mindex] <= din[31];
end
PULL : begin // Pull value from fifo
pull[mindex] <= 1;
dout <= pdout[mindex];
end
PUSH : push[mindex] <= 1; // Push a value to fifo
GRPS : begin // Configure pin groups. PIN_CTRL registers
pins_out_base[mindex] <= din[4:0];
pins_set_base[mindex] <= din[9:5];
pins_side_base[mindex] <= din[14:10];
pins_in_base[mindex] <= din[19:15];
pins_out_count[mindex] <= din[25:20];
pins_set_count[mindex] <= din[28:26];
pins_side_count[mindex] <= din[31:29];
end
EN : begin // Enable machines
en <= din[3:0]; // Equivalent of CTRL register
restart <= din[7:4];
clkdiv_restart <= din[11:8];
end
DIV : begin
div[mindex] <= din[23:0]; // Configure clock dividers. CLKDIV registers
use_divider[mindex] <= din[23:0] >= 24'h200; // Use divider if clock divider is 2 or more
end
IMM : imm[mindex] <= 1; // Immediate instruction
SHIFT: begin
auto_push[mindex] <= din[16]; // SHIFT_CTRL
auto_pull[mindex] <= din[17];
in_shift_dir[mindex] <= din[18];
out_shift_dir[mindex] <= din[19];
isr_threshold[mindex] <= din[24:20];
osr_threshold[mindex] <= din[29:25];
end
NONE : dout <= 32'h01000000; // Hardware version number
endcase
end
end
// Generate the machines and associated TX and RX fifos
generate
genvar j;
for(j=0;j<NUM_MACHINES;j=j+1) begin : mach
machine machine (
.clk(clk),
.reset(reset),
.en(en[j]),
.restart(restart[j]),
.mindex(j[1:0]),
.jmp_pin(jmp_pin[j]),
.input_pins(gpio_in),
.output_pins(output_pins[j]),
.pin_directions(pin_directions[j]),
.sideset_enable_bit(pins_side_count[j] > 0 ? sideset_enable_bit[j] : 1'b0),
.in_shift_dir(in_shift_dir[j]),
.out_shift_dir(out_shift_dir[j]),
.div(div[j]),
.use_divider(use_divider[j]),
.instr(imm[j] ? din[15:0] : curr_instr[j]),
.imm(imm[j]),
.pend(pend[j]),
.wrap_target(wrap_target[j]),
.pins_out_base(pins_out_base[j]),
.pins_out_count(pins_out_count[j]),
.pins_set_base(pins_set_base[j]),
.pins_set_count(pins_set_count[j]),
.pins_in_base(pins_in_base[j]),
.pins_side_base(pins_side_base[j]),
.pins_side_count(pins_side_count[j]),
.auto_pull(auto_pull[j]),
.auto_push(auto_push[j]),
.isr_threshold(isr_threshold[j]),
.osr_threshold(osr_threshold[j]),
.irq_flags_in(8'h0),
.irq_flags_out(irq_flags_out[j]),
.pc(pc[j]),
.din(mdin[j]),
.dout(mdout[j]),
.pull(mpull[j]),
.push(mpush[j]),
.pclk(pclk[j]),
.empty(mempty[j]),
.full(mfull[j])
);
fifo fifo_tx (
.clk(clk),
.reset(reset),
.push(push[j]),
.pull(mpull[j]),
.din(din),
.dout(mdin[j]),
.empty(mempty[j]),
.full(tx_full[j]),
.level(tx_level[j])
);
fifo fifo_rx (
.clk(clk),
.reset(reset),
.push(mpush[j]),
.pull(pull[j]),
.din(mdout[j]),
.dout(pdout[j]),
.full(mfull[j]),
.empty(rx_empty[j]),
.level(rx_level[j])
);
end
endgenerate
endmodule |
module isr (
input clk,
input penable,
input reset,
input stalled,
input [31:0] din,
input [4:0] shift,
input dir,
input set,
input do_shift,
input [5:0] bit_count,
output [31:0] dout,
output [5:0] shift_count
);
reg [31:0] shift_reg;
reg [5:0] count;
// A shift value of 0 means shift 32
wire [5:0] shift_val = shift == 0 ? 32 : shift;
// Left align the input value and concatenate it with the shift register to produce a 64-bit value
wire [63:0] new_shift = dir ? {din, shift_reg} >> shift_val
: {shift_reg, din << (32 - shift_val)} << shift_val;
always @(posedge clk) begin
if (reset) begin
shift_reg <= 0;
count <= 0; // Empty
end else if (penable && !stalled) begin
if (set) begin
shift_reg <= din;
count <= bit_count;
end else if (do_shift) begin
shift_reg <= dir ? new_shift[31:0] : new_shift[63:32];
count <= count + shift_val > 32 ? 32 : count + shift_val;
end
end
end
assign dout = shift_reg;
assign shift_count = count;
endmodule |
module top (
input clk_25mhz,
// Buttons
input [6:0] btn,
// Leds
output [7:0] led,
output [27:0] gn,
input rx,
output tx
);
// PIO registers and wires
reg [31:0] din; // Data sent to PIO
reg [4:0] index; // Instruction index
reg [3:0] action; // Action to be done by PIO
reg [1:0] mindex; // Machine index
wire [31:0] gpio_in; // Input pins to PIO
wire [31:0] gpio_out; // Output pins from PIO
wire [31:0] gpio_dir; // Pin directions
wire [31:0] dout; // Output from PIO
wire irq0, irq1; // IRQ flags from PIO
wire [3:0] tx_full; // Set when TX fifo is full
wire [3:0] rx_empty; // Set when RX fifo is empty
wire [4:0] offset = 4;
// Power-on reset
reg [15:0] pwr_up_reset_counter = 0;
wire pwr_up_reset_n = &pwr_up_reset_counter;
wire n_reset = pwr_up_reset_n & btn[0];
wire reset = ~n_reset;
always @(posedge clk_25mhz) begin
if (!pwr_up_reset_n)
pwr_up_reset_counter <= pwr_up_reset_counter + 1;
end
// Configuration of state machines and program instructions
reg [15:0] program1 [0:31];
initial $readmemh("uart_rx.mem", program1);
wire [4:0] plen1 = 4;
reg [15:0] program2 [0:31];
initial $readmemh("uart_tx.mem", program2);
wire [4:0] plen2 = 4;
reg [35:0] conf1 [0:31];
initial $readmemh("rx_conf.mem", conf1);
wire [4:0] clen1 = 5; // Config 1 length
reg [35:0] conf2 [0:31];
initial $readmemh("tx_conf2.mem", conf2);
wire [4:0] clen2 = 6; // Config 2 length
// State machine to send program to PIO and configure PIO state machines
reg [2:0] state;
reg [4:0] cindex;
reg [4:0] pindex;
reg [2:0] delay_cnt;
reg rx_ready;
reg [7:0] data;
always @(posedge clk_25mhz) begin
if (reset) begin
din <= 0;
action <= 0;
index <= 0;
mindex <= 0;
state <= 0;
cindex <= 0;
pindex <= 0;
end else begin
case (state)
0: begin // Send program 1 to pio
if (pindex < plen1) begin
action <= 1;
din <= program1[pindex];
pindex <= pindex + 1;
index <= pindex;
end else begin
state <= 1;
pindex <= 0;
action <= 0;
end
end
1: begin // Send program 2 to pio
if (pindex < plen2) begin
action <= 1;
din <= program2[pindex][15:13] == 0 ? program2[pindex] + offset : program2[pindex];
pindex <= pindex + 1;
index <= pindex + offset;
end else begin
state <= 2;
action <= 0;
mindex <= 0;
end
end
2: begin // Configure machine 1
cindex <= cindex + 1;
if (cindex == clen1) begin
state <= 3;
action <= 0;
mindex <= 1;
cindex <= 0;
end else begin
action <= conf1[cindex][35:32];
din <= conf1[cindex][31:0];
end
end
3: begin // Configure machine 2
cindex <= cindex + 1;
if (cindex == clen2) begin
state <= 4;
action <= 0;
end else begin
action <= conf2[cindex][35:32];
din <= conf2[cindex][31:0];
end
end
4: begin // Run state
action <= 0;
delay_cnt <= delay_cnt + 1;
rx_ready <= 0;
if (!rx_empty[0] && &delay_cnt) begin
mindex <= 0;
action <= 3; // Pull
rx_ready <= 1;
end
if (rx_ready) begin
mindex <= 1;
din <= dout[31:24];
data <= dout[31:24];
action <= 4; // Push
end
end
endcase
end
end
// PIO instance 1
pio pio_1 (
.clk(clk_25mhz),
.reset(reset),
.mindex(mindex),
.din(din),
.index(index),
.action(action),
.dout(dout),
.gpio_in(gpio_in),
.gpio_out(gpio_out),
.gpio_dir(gpio_dir),
.irq0(irq0),
.irq1(irq1),
.tx_full(tx_full),
.rx_empty(rx_empty)
);
// Led and gpio output
`ifdef blackicemx
assign led = ~{rx_ready, rx_empty[0]};
`else
assign led = data;
`endif
assign tx = gpio_out[0];
assign gpio_in[0] = rx;
endmodule |
module clk_mmcm(clk_200, reset, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_200,reset,locked,clk_in1" */;
output clk_200;
input reset;
output locked;
input clk_in1;
endmodule |
module clk_mmcm_clk_wiz
(// Clock in ports
// Clock out ports
output clk_200,
// Status and control signals
input reset,
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_clk_mmcm;
wire clk_in2_clk_mmcm;
IBUF clkin1_ibufg
(.O (clk_in1_clk_mmcm),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_200_clk_mmcm;
wire clk_out2_clk_mmcm;
wire clk_out3_clk_mmcm;
wire clk_out4_clk_mmcm;
wire clk_out5_clk_mmcm;
wire clk_out6_clk_mmcm;
wire clk_out7_clk_mmcm;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_mmcm;
wire clkfbout_buf_clk_mmcm;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (5.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_mmcm),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_200_clk_mmcm),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_mmcm),
.CLKIN1 (clk_in1_clk_mmcm),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_mmcm),
.I (clkfbout_clk_mmcm));
BUFG clkout1_buf
(.O (clk_200),
.I (clk_200_clk_mmcm));
endmodule |
module clk_mmcm
(
// Clock out ports
output clk_200,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
clk_mmcm_clk_wiz inst
(
// Clock out ports
.clk_200(clk_200),
// Status and control signals
.reset(reset),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule |
module ddr3_controller(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_i, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end,
app_wdf_mask, app_wdf_wren, app_rd_data, app_rd_data_end, app_rd_data_valid, app_rdy,
app_wdf_rdy, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack,
ui_clk, ui_clk_sync_rst, init_calib_complete, device_temp, sys_rst)
/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[15:0],ddr3_dqs_n[1:0],ddr3_dqs_p[1:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[1:0],ddr3_odt[0:0],sys_clk_i,app_addr[27:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,device_temp[11:0],sys_rst" */;
inout [15:0]ddr3_dq;
inout [1:0]ddr3_dqs_n;
inout [1:0]ddr3_dqs_p;
output [13:0]ddr3_addr;
output [2:0]ddr3_ba;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
output [0:0]ddr3_ck_p;
output [0:0]ddr3_ck_n;
output [0:0]ddr3_cke;
output [0:0]ddr3_cs_n;
output [1:0]ddr3_dm;
output [0:0]ddr3_odt;
input sys_clk_i;
input [27:0]app_addr;
input [2:0]app_cmd;
input app_en;
input [127:0]app_wdf_data;
input app_wdf_end;
input [15:0]app_wdf_mask;
input app_wdf_wren;
output [127:0]app_rd_data;
output app_rd_data_end;
output app_rd_data_valid;
output app_rdy;
output app_wdf_rdy;
input app_sr_req;
input app_ref_req;
input app_zq_req;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output ui_clk;
output ui_clk_sync_rst;
output init_calib_complete;
output [11:0]device_temp;
input sys_rst;
endmodule |
module mig_7series_v4_2_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v4_2_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule |
module mig_7series_v4_2_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule |
module mig_7series_v4_2_memc_flow_vcontrol #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter NUM_DQ_PINS = 32,
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 4,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3"
)
(
input clk_i,
input [9:0] rst_i,
input [3:0] data_mode_i,
input [5:0] cmds_gap_delay_value,
input mem_pattern_init_done_i,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [BL_WIDTH - 1:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
input mcb_wr_full_i,
output reg [2:0] cmd_o,
output [31:0] addr_o,
output reg [BL_WIDTH-1:0] bl_o,
output cmd_en_o, // interface to write data path module
// *** interface to qdr ****
output reg qdr_rd_cmd_o,
// *************************
input mcb_wr_en_i,
input last_word_wr_i,
input wdp_rdy_i,
output reg wdp_valid_o,
output reg wdp_validB_o,
output reg wdp_validC_o,
output [31:0] wr_addr_o,
output [BL_WIDTH-1:0] wr_bl_o,
// interface to read data path module
input rdp_rdy_i,
output reg rdp_valid_o,
output [31:0] rd_addr_o,
output [BL_WIDTH-1:0] rd_bl_o
);
//FSM State Defination
localparam READY = 4'b0001,
READ = 4'b0010,
WRITE = 4'b0100,
CMD_WAIT = 4'b1000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101;
reg cmd_fifo_rdy;
reg push_cmd;
reg cmd_rdy;
reg [31:0] addr_r;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [BL_WIDTH-1:0] bl_reg;
reg [BL_WIDTH:0] cmd_counts;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [3:0] current_state;
reg [3:0] next_state;
reg push_cmd_r;
reg cmd_en_r1;
reg wr_in_progress;
reg wrcmd_in_progress;
reg rdcmd_in_progress;
reg [5:0] commands_delay_counters;
reg goahead;
reg cmd_en_r2;
reg cmd_wr_pending_r1;
reg [3:0] addr_INC;
reg COuta;
wire cmd_rd;
wire cmd_wr;
always @ (posedge clk_i) begin
if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6")
addr_INC <= #TCQ 0;
else
addr_INC <= #TCQ MEM_BURST_LEN[3:0];
end
// mcb_command bus outputs
always @(posedge clk_i) begin
if (rst_i[0]) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b1;
end
else if (cmds_gap_delay_value == 5'd0)
goahead <= 1'b1;
else if (wr_in_progress || wrcmd_in_progress ||
rdcmd_in_progress || cmd_rdy_o) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b0;
end
else if (commands_delay_counters == cmds_gap_delay_value) begin
commands_delay_counters <= commands_delay_counters;
goahead <= 1'b1;
end
else
commands_delay_counters <= commands_delay_counters + 1'b1;
end
assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ cmd_rdy;
always @ (posedge clk_i) begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
// else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i))
else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 ))
cmd_en_r1 <= #TCQ 1'b0;
else if ((rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS") ||
(mcb_wr_en_i && MEM_TYPE == "QDR2PLUS"))
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full)
cmd_en_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
if (rst_i[8])
cmd_en_r2 <= #TCQ 1'b0;
else
cmd_en_r2 <= cmd_en_r1;
// QDR read command generation
always @ (posedge clk_i) begin
if (rst_i[8])
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1)
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (rdcmd_in_progress)
qdr_rd_cmd_o <= #TCQ 1'b1;
else if (!mcb_cmd_full)
qdr_rd_cmd_o <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (cmd_en_r1 || mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[9]) begin
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
else if (push_cmd_r && current_state == READ) begin
cmd_o <= #TCQ cmd_i;
bl_o <= #TCQ bl_i - 'b1;
end
else if (push_cmd_r && current_state == WRITE) begin
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
always @ (posedge clk_i)
if ((push_cmd && mem_pattern_init_done_i) | rst_i)
addr_reg <= #TCQ addr_i;
else if (push_cmd && !mem_pattern_init_done_i)
addr_reg <= #TCQ addr_r;
always @ (posedge clk_i) begin
if (push_cmd && cmd_rd || rst_i[0])
addr_r <= #TCQ addr_i;
else if (push_cmd_r && current_state != READ)
addr_r <= #TCQ addr_reg;
else if ((wrcmd_in_progress || rdcmd_in_progress) &&
cmd_en_r1 && ~mcb_cmd_full) begin
if (MEM_TYPE == "QDR2PLUS")
{COuta,addr_r[31:0]} <= addr_o + 1;
else
{COuta,addr_r[31:0]} <= addr_o + addr_INC;
end
end
assign addr_o = addr_r;
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i;
assign wr_bl_o = bl_i;
always @ (posedge clk_i) begin
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
end
always @ (posedge clk_i)
rdp_valid_o <= rdp_valid;
always @(posedge clk_i)
push_cmd_r <= #TCQ push_cmd;
always @(posedge clk_i)
if (push_cmd) begin
cmd_reg <= #TCQ cmd_i;
bl_reg <= #TCQ bl_i - 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_counts <= #TCQ 'b0;
else if (push_cmd_r) begin
if (bl_i == 0) begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}};
else
cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}};
end
else
cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63;
end
else begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= {1'b0,bl_i};
else
cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]};
end
else
cmd_counts <= {1'b0,bl_i};//- 1 ;// {1'b0,bl_i[5:1]} -2;
end
end
else if ((wrcmd_in_progress || rdcmd_in_progress) && cmd_en_r1 && ~mcb_cmd_full) begin
if (cmd_counts > 0) begin
if (FAMILY == "VIRTEX6")
cmd_counts <= cmd_counts - 1'b1;
else if (wrcmd_in_progress)
cmd_counts <= cmd_counts - 1'b1;
else
cmd_counts <= 0;
end
end
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
always @ (posedge clk_i) begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
else if (last_word_wr_i)
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd & cmd_wr)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i)
wr_in_progress <= #TCQ 1'b0;
else if (push_cmd && cmd_wr)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wrcmd_in_progress <= #TCQ 1'b0;
else if (cmd_wr && push_cmd_r)
wrcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts == 0 || (cmd_counts == 1 && ~mcb_cmd_full))
wrcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
rdcmd_in_progress <= #TCQ 1'b0;
else if (cmd_rd && push_cmd_r)
rdcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts <= 1)
rdcmd_in_progress <= #TCQ 1'b0;
end
// mcb_flow_control statemachine
always @ (posedge clk_i)
if (rst_i[0])
current_state <= #TCQ 5'b00001;
else
current_state <= #TCQ next_state;
always @ (*) begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state) // next state logic
READY: begin // 5'h01
if (rdp_rdy_i && cmd_rd && ~mcb_cmd_full) begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
cmd_rdy = 1'b1;
end
else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full) begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
end
else begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
end
end // READY
READ: begin // 5'h02
if (rdcmd_in_progress) begin
next_state = READ;
push_cmd = 1'b0;
rdp_valid = 1'b0;
wdp_valid = 1'b0;
end
else if (!rdp_rdy_i) begin
next_state = READ;
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead) begin
next_state = CMD_WAIT;
end
else if (goahead && ~push_cmd_r) begin
next_state = READY;
cmd_rdy = 1'b0;
end
else
next_state = READ;
end // READ
WRITE: begin // 5'h04
if (wr_in_progress || wrcmd_in_progress || push_cmd_r) begin
next_state = WRITE;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
push_cmd = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i && goahead) begin
next_state = CMD_WAIT;
push_cmd = 1'b0;
end
else if (goahead) begin
next_state = READY;
end
else
next_state = WRITE;
cmd_rdy = 1'b0;
end // WRITE
CMD_WAIT: begin // 5'h08
if (!cmd_fifo_rdy || wr_in_progress) begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
rdp_valid = 1'b0;
end
else if (cmd_fifo_rdy && cmd_wr && goahead &&
cmd_wr_pending_r1) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
end
else begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
end // CMD_WAIT
default: begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
end
endcase
end
endmodule |
module mig_7series_v4_2_traffic_gen_top #(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter SIMULATION = "FALSE",
parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7"
parameter MEM_TYPE = "DDR3",
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "R_W_INSTR_MODE"
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
// parameter BL_WIDTH = 10, // Define User Interface Burst length width.
// // For a maximum 128 continuous back_to_back command, set this to 8.
parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock.
parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design.
parameter MEM_BURST_LEN = 8, // MEMROY Burst Length
parameter MEM_COL_WIDTH = 10, // Memory component column width.
parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width
parameter ADDR_WIDTH = 29, // Command Address Bus width
parameter MASK_SIZE = DATA_WIDTH/8, //
parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern.
// parameters define the address range
parameter BEGIN_ADDRESS = 32'h00000100,
parameter END_ADDRESS = 32'h000002ff,
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00,
// debug parameters
parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles
// after the last command.
parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when
// DATA MODE is hammer pattern. No VICTIM_LINE will be selected if
// SEL_VICTIM_LINE = NUM_DQ_PINS.
parameter CMD_WDT = 'h3FF,
parameter WR_WDT = 'h1FFF,
parameter RD_WDT = 'hFF,
parameter EYE_TEST = "FALSE",
// S6 Only parameters
parameter PORT_MODE = "BI_MODE",
parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits.
parameter CMD_PATTERN = "CGEN_ALL" // Default is to generate all commands pattern circuits.
)
(
input clk,
input rst,
input tg_only_rst,
input manual_clear_error,
input memc_init_done,
input memc_cmd_full,
output memc_cmd_en,
output [2:0] memc_cmd_instr,
output [5:0] memc_cmd_bl,
output [31:0] memc_cmd_addr,
output memc_wr_en,
output memc_wr_end,
output [DATA_WIDTH/8 - 1:0] memc_wr_mask,
output [DATA_WIDTH - 1:0] memc_wr_data,
input memc_wr_full,
output memc_rd_en,
input [DATA_WIDTH - 1:0] memc_rd_data,
input memc_rd_empty,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// Signal declarations that can be connected to vio module
input vio_pause_traffic, // Pause traffic on the fly.
input vio_modify_enable,
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [3:0] vio_instr_mode_value,
input [1:0] vio_bl_mode_value,
input [9:0] vio_fixed_bl_value,
input [2:0] vio_fixed_instr_value, // Allows upper level control write only or read only
// on the fly.
// Set the vio_instr_mode_value to "0001" .
// User has control of the type of commands to be generated
// after memory has been filled with selected data pattern.
// vio_fixed_instr_value = 3'b000: Write command
// vio_fixed_instr_value = 3'b001: Read command
input vio_data_mask_gen, // data_mask generation is only supported
// when data mode = address as data .
//
input [31:0] fixed_addr_i,
// User Specific data pattern interface that used when vio_data_mode vale = 1.4.9.
input [31:0] fixed_data_i,
input [31:0] simple_data0,
input [31:0] simple_data1,
input [31:0] simple_data2,
input [31:0] simple_data3,
input [31:0] simple_data4,
input [31:0] simple_data5,
input [31:0] simple_data6,
input [31:0] simple_data7,
input wdt_en_i,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
// status feedback
output [DATA_WIDTH-1:0] cmp_data,
output cmp_data_valid,
output cmp_error,
output [47:0] wr_data_counts,
output [47:0] rd_data_counts,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DATA_WIDTH - 1):0] error_status,
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error,
output reg cmd_wdt_err_o,
output reg wr_wdt_err_o,
output reg rd_wdt_err_o,
output mem_pattern_init_done
);
//p0 wire declarations
wire tg_run_traffic;
wire tg_data_mask_gen;
wire run_traffic;
wire [31:0] tg_start_addr;
wire [31:0] tg_end_addr;
wire [31:0] tg_cmd_seed;
wire [31:0] tg_data_seed;
wire tg_load_seed;
wire [2:0] tg_addr_mode;
wire [3:0] tg_instr_mode;
wire [1:0] tg_bl_mode;
wire [3:0] tg_data_mode;
wire tg_mode_load;
wire [9:0] tg_fixed_bl;
wire [2:0] tg_fixed_instr;
wire tg_addr_order;
wire [5:0] cmds_gap_delay_value;
wire tg_memc_wr_en;
wire [63:0] mem_tg_tstpoints;
wire [9:0] lcl_v_fixed_bl_value;
wire single_operation;
wire [3:0] tg_instr_mode_value;
wire [3:0] instr_mode_value;
reg tg_rst;
localparam ADDR_WIDTH_MASK = {{31-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH-1{1'b1}}};
localparam ADDR_WIDTH_MASK_1 = {{30-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH{1'b1}}};
localparam BEGIN_ADDRESS_MASK = ADDR_WIDTH_MASK & BEGIN_ADDRESS;
localparam END_ADDRESS_MASK = ADDR_WIDTH_MASK_1 & END_ADDRESS;
localparam SHIFT_COUNT = (31-ADDR_WIDTH) ;
localparam BEGIN_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (BEGIN_ADDRESS >> SHIFT_COUNT) : BEGIN_ADDRESS_MASK ;
localparam END_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (END_ADDRESS >> SHIFT_COUNT) : END_ADDRESS_MASK ;
localparam TG_INIT_DATA_MODE = (DATA_PATTERN == "DGEN_ADDR") ? 4'b0010 :
(DATA_PATTERN == "DGEN_HAMMER") ? 4'b0011 :
(DATA_PATTERN == "DGEN_WALKING1") ? 4'b0101 :
(DATA_PATTERN == "DGEN_WALKING0") ? 4'b0110 :
(DATA_PATTERN == "DGEN_PRBS") ? 4'b0111 :
DATA_MODE ;
assign single_operation = 1'b0; // Disable this for 13.3 release
// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command.
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam CMD_WDT_WIDTH = clogb2(CMD_WDT);
localparam RD_WDT_WIDTH = clogb2(RD_WDT);
localparam WR_WDT_WIDTH = clogb2(WR_WDT);
assign cmds_gap_delay_value = CMDS_GAP_DELAY;
localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES")
|| (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6";
assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ;
assign lcl_v_fixed_bl_value = (vio_data_mode_value == 4) ? 32:vio_fixed_bl_value;
assign tg_run_traffic = (run_traffic & ((vio_modify_enable == 1'b1) ? ~vio_pause_traffic : 1'b1)) ;
assign tg_data_mask_gen = (vio_modify_enable == 1'b1) ? vio_data_mask_gen : 1'b0 ;
assign instr_mode_value = (vio_modify_enable == 1'b1) ? vio_instr_mode_value : 4'b0010;
assign tg_instr_mode_value = (single_operation == 1'b1) ? 4'b0111: instr_mode_value;
reg [CMD_WDT_WIDTH-1 : 0] cmd_wdt;
reg [RD_WDT_WIDTH-1 : 0] rd_wdt;
reg [WR_WDT_WIDTH-1 : 0] wr_wdt;
// The following 'generate' statement activates the traffic generator for
// init_mem_pattern_ctr module instantiation for Port-0
mig_7series_v4_2_init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_TYPE (MEM_TYPE),
.FAMILY (TG_FAMILY),
.BL_WIDTH (10),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS_INT),
.END_ADDRESS (END_ADDRESS_INT),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (TG_INIT_DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (tg_rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.single_write_button (1'b0), // tie off these group of signals for 13.3
.single_read_button (1'b0),
.slow_write_read_button (1'b0),
.single_operation (1'b0),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.vio_fixed_instr_value (vio_fixed_instr_value),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
mig_7series_v4_2_memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.MEM_TYPE (MEM_TYPE),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (10),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS_INT),
.PRBS_EADDR (END_ADDRESS_INT),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (tg_rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands
// instr_mode_i has to be == 4 if want to use this command pattern
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.single_operation (1'b0),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (tg_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (qdr_wr_cmd_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// status feedback
.counts_rst (tg_rst),
.wr_data_counts (wr_data_counts),
.rd_data_counts (rd_data_counts),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
.cumlative_dq_lane_error (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
reg [8:0] wr_cmd_cnt;
reg [8:0] dat_cmd_cnt;
reg rst_remem;
reg [2:0] app_cmd1;
reg [2:0] app_cmd2;
reg [2:0] app_cmd3;
reg [2:0] app_cmd4;
reg [8:0] rst_cntr;
always @(posedge clk) begin
if (rst) begin
rst_remem <= 1'b0;
end else if (tg_only_rst) begin
rst_remem <= 1'b1;
end else if (rst_cntr == 9'h0) begin
rst_remem <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
tg_rst <= 1'b1;
end else begin
tg_rst <= (rst_cntr != 9'h1ff);
end
end
always @ (posedge clk)
begin
if (rst)
rst_cntr <= 9'h1ff;
else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0))
rst_cntr <= 9'h0;
else if (rst_cntr != 9'h1ff)
rst_cntr <= rst_cntr + 1'b1;
end
always @(posedge clk) begin
if (rst | tg_rst) begin
wr_cmd_cnt <= 1'b0;
end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin
wr_cmd_cnt <= wr_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
dat_cmd_cnt <= 1'b0;
end else if (memc_wr_en & (!memc_wr_full)) begin
dat_cmd_cnt <= dat_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
app_cmd1 <= 'b0;
app_cmd2 <= 'b0;
app_cmd3 <= 'b0;
app_cmd4 <= 'b0;
end else if (memc_cmd_en & (!memc_cmd_full)) begin
app_cmd1 <= memc_cmd_instr;
app_cmd2 <= app_cmd1;
app_cmd3 <= app_cmd2;
app_cmd4 <= app_cmd3;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt <= 1'b0;
end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= cmd_wdt + 1'b1;
// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin
end else if ((!memc_cmd_full) & memc_cmd_en) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
rd_wdt <= 1'b0;
end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin
// !app_rd_data_valid
rd_wdt <= rd_wdt + 1'b1;
end else if (!memc_rd_empty) begin
// !app_rd_data_valid
rd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
wr_wdt <= 1'b0;
end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin
// app_wdf_wren
wr_wdt <= wr_wdt + 1'b1;
end else if (memc_wr_en) begin
// app_wdf_wren
wr_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt_err_o <= 'b0;
rd_wdt_err_o <= 'b0;
wr_wdt_err_o <= 'b0;
end else begin
cmd_wdt_err_o <= cmd_wdt == CMD_WDT;
rd_wdt_err_o <= rd_wdt == RD_WDT;
wr_wdt_err_o <= wr_wdt == WR_WDT;
end
end
//synthesis translate_off
initial
begin
@ (posedge cmd_wdt_err_o);
$display ("ERROR: COMMAND Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge rd_wdt_err_o);
$display ("ERROR: READ Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge wr_wdt_err_o)
$display ("ERROR: WRITE Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge error)
repeat (20) @ (posedge clk);
$finish;
end
//synthesis translate_on
endmodule |
module mig_7series_v4_2_read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter nCK_PER_CLK = 4,
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
if (FAMILY == "SPARTAN6")
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
else
// if (nCK_PER_CLK == 2 )
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
// else
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) ))
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
mig_7series_v4_2_afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule |
module mig_7series_v4_2_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule |
module mig_7series_v4_2_tg_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 10, // LFSR shift register length
parameter nCK_PER_CLK = 4 // output:internal clock freq ratio
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
output [2*nCK_PER_CLK-1:0] prbs_o, // generated address
// ReSeedcounter used to indicate when pseudo-PRBS sequence has reached
// the end of it's cycle. May not be needed, but for now included to
// maintain compatibility with current TG code
output [31:0] ReSeedcounter_o
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK);
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg [PRBS_WIDTH-1:0] lfsr_reg_r;
wire [PRBS_WIDTH-1:0] next_lfsr_reg;
reg [PRBS_WIDTH-1:0] reseed_cnt_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
genvar i;
//***************************************************************************
assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r};
always @ (posedge clk_i)
if (rst_i)
reseed_cnt_r <= 'b0;
else if (clk_en_i)
if (reseed_cnt_r == {PRBS_WIDTH {1'b1}})
reseed_cnt_r <= 'b0;
else
reseed_cnt_r <= reseed_cnt_r + 1;
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
if (rst_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
// Load initial seed or update LFSR contents
always @(posedge clk_i)
if (rst_i)
lfsr_reg_r <= #TCQ prbs_seed_i;
else if (clk_en_i)
if (reseed_prbs_r)
lfsr_reg_r <= #TCQ prbs_seed_i;
else begin
lfsr_reg_r <= #TCQ next_lfsr_reg;
end
// Calculate next set of nCK_PER_CLK samplse for LFSR
// Basically we calculate all PRBS_WIDTH samples in parallel, rather
// than serially shifting the LFSR to determine future sample values.
// Shifting is possible, but requires multiple shift registers to be
// instantiated because the fabric clock frequency is running at a
// fraction of the output clock frequency
generate
if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]) ;
assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^
lfsr_reg_r[0] ^ next_lfsr_reg[7]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^
next_lfsr_reg[7] ^ next_lfsr_reg[6]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^
next_lfsr_reg[6] ^ next_lfsr_reg[5]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^
next_lfsr_reg[5] ^ next_lfsr_reg[4]);
end
end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[9] = lfsr_reg_r[5];
assign next_lfsr_reg[8] = lfsr_reg_r[4];
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[9] = lfsr_reg_r[1];
assign next_lfsr_reg[8] = lfsr_reg_r[0];
assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]);
end
end
endgenerate
// Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest"
// tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first
// data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be
// routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the
// output, etc.
generate
for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose
assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i];
end
endgenerate
endmodule |
module mig_7series_v4_2_memc_traffic_gen #
(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6"
parameter MEM_TYPE = "DDR3",
parameter SIMULATION = "FALSE",
parameter tCK = 2500,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen.
// This traffic gen doesn't support DDR3 OTF Burst mode.
parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE"
// VIRTEX6: "BI_MODE"
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30
parameter BANK_WIDTH = 3,
parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0
// memory type specific
parameter MEM_COL_WIDTH = 10, // memory column width
parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16;
// Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144
parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern
// SEL_VICTIM_LINE is only for V6.
// Virtex 6 option: 8,9,16,17,32,36,64,72
parameter DWIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128;
// Virtex 6 Always: 4* NUM_DQ_PINS
// the following parameter is to limit the range of generated PRBS Address
//
// e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with
// PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset.
// PRBS_EADDR = 32'h0000_7fff
// PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to
// zero out the LFSR[31:15]
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00005000,
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals.
// Traffic Generator will only write to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input run_traffic_i,
input single_operation,
input manual_clear_error,
input [5:0] cmds_gap_delay_value, // control delay gap between each sucessive
input [3:0] vio_instr_mode_value,
input [3:0] vio_percent_write,
// burst commands.
// *** runtime parameter ***
input mem_pattern_init_done_i,
input [31:0] start_addr_i, // define the start of address
input [31:0] end_addr_i, // define upper limit addressboundary
input [31:0] cmd_seed_i, // seed for cmd PRBS generators
input [31:0] data_seed_i, // data seed will be added to generated address
// for PRBS data generation
// seed for cmd PRBS generators
input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered.
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface
// "01" = fixed address from the fixed_addr input
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "11" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
input [3:0] instr_mode_i, // "0000" = BRAM
// "0001" = Fixed; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0110" = PRBS
// "1111" = Read Only from Address 0 . Expecting phy calibration data pattern.
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
input [3:0] data_mode_i, // "000" = address as data
// "001" = hammer
// "010" = neighbour
// "011" = prbs
// "100" = walking 0's
// "101" = walking 1's
// "110" =
// "111" =
input wr_data_mask_gen_i, // "1": turn on wr_data_mask generation
// random follow by walking 1's
input mode_load_i,
// fixed pattern inputs interface
input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64
input [2:0] fixed_instr_i, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
input [31:0] fixed_addr_i, // only upper 30 bits will be used
input [31:0] fixed_data_i, //
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
/////////////////////////////////////////////////////////////////////////////
// MCB INTERFACE
// interface to mcb command port
output memc_cmd_en_o,
output [2:0] memc_cmd_instr_o,
output [31:0] memc_cmd_addr_o,
output [5:0] memc_cmd_bl_o, // this output is for Spartan 6
input memc_cmd_full_i,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// interface to mcb wr data port
output memc_wr_en_o,
output [DWIDTH-1:0] memc_wr_data_o,
output memc_wr_data_end_o,
output [(DWIDTH/8) - 1:0] memc_wr_mask_o,
input memc_wr_full_i,
// interface to mcb rd data port
output memc_rd_en_o,
input [DWIDTH-1:0] memc_rd_data_i,
input memc_rd_empty_i,
/////////////////////////////////////////////////////////////////////////////
// status feedback
input counts_rst,
output reg [47:0] wr_data_counts,
output reg [47:0] rd_data_counts,
output cmp_error,
output cmp_data_valid,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped
output [DWIDTH-1:0] cmp_data,
output [DWIDTH-1:0] mem_rd_data,
// **** V6 Signals
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, // V6: latched error byte lane that occure on
// first error
//************************************************
// DQ bit error debug signals.
output [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error ,
output [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error ,
output [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
//
output [NUM_DQ_PINS - 1:0] dq_r0_read_bit, // rising 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f0_read_bit, // falling 0 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r1_read_bit, // rising 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_f1_read_bit, // falling 1 read bits from mc
output [NUM_DQ_PINS - 1:0] dq_r0_expect_bit, // rising 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f0_expect_bit, // falling 0 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_r1_expect_bit, // rising 1 read bits from internal expect data generator
output [NUM_DQ_PINS - 1:0] dq_f1_expect_bit, // falling 1 read bits from internal expect data generator
output [31:0] error_addr // the command address of the returned data.
// Can use dq_rx_bit_error as write enable to latch the address.
);
wire [DWIDTH-1:0] rdpath_rd_data_i;
wire rdpath_data_valid_i;
wire memc_wr_en;
wire cmd2flow_valid;
wire [2:0] cmd2flow_cmd;
wire [31:0] cmd2flow_addr;
wire [BL_WIDTH-1:0] cmd2flow_bl;
wire last_word_wr;
wire flow2cmd_rdy;
wire [31:0] wr_addr;
wire [31:0] rd_addr;
wire [BL_WIDTH-1:0] wr_bl;
wire [BL_WIDTH-1:0] rd_bl;
reg run_traffic_reg;
wire wr_validB, wr_valid,wr_validC;
wire [31:0] bram_addr_i;
wire [2:0] bram_instr_i;
wire [5:0] bram_bl_i;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [7:0] end_boundary_addr;
reg lower_end_matched;
wire [31:0] addr_o;
wire [31:0] m_addr;
wire dcount_rst;
wire [31:0] rd_addr_error;
wire rd_rdy;
//wire cmp_error;
wire cmd_full;
wire rd_mdata_fifo_rd_en;
wire rd_mdata_fifo_afull;
reg memc_wr_en_r;
wire memc_wr_data_end;
reg [DWIDTH-1:0] memc_rd_data_r;
wire [DWIDTH-1:0] memc_wr_data;
reg [DWIDTH-1:0] memc_wr_data_r;
wire wr_path_data_rdy_i;
//
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg [9:0] rst_ra,rst_rb /* synthesis syn_maxfan = 10 */;
wire mem_init_done;
reg [3:0] data_mode_r_a;
reg [3:0] data_mode_r_b;
reg [3:0] data_mode_r_c;
reg error_access_range = 1'b0;
wire [BL_WIDTH-1:0] memc_bl_o;
// generic parameters and need to be tested in both MCB mode and V7 Virtext Mode.
initial begin
if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8) && (MEM_BURST_LEN !== 2))
begin: NO_OTF_Warning_Error
$display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!");
$stop;
end
else
begin: Dummy1
end
end
always @ (memc_cmd_en_o,memc_cmd_addr_o,memc_cmd_bl_o,start_addr_i,end_addr_i)
if (memc_cmd_en_o &&
((FAMILY == "SPARTAN6" && memc_cmd_addr_o + 20) > end_addr_i[ADDR_WIDTH-1:0]) ||
((FAMILY == "VIRTEX6" && memc_cmd_addr_o ) > end_addr_i[ADDR_WIDTH-1:0])
)
begin
$display("Error ! Command access beyond address range");
$display("Assigned Address Space: Start_Address = 0x%h ; End_Addr = 0x%h",start_addr_i,end_addr_i);
$display("Attempted area = 0x%h",memc_cmd_addr_o + (memc_cmd_bl_o - 1) * (DWIDTH/8));
$stop;
end
else
begin: No_Error_Display
end
assign memc_cmd_bl_o = memc_bl_o[5:0];
always @ (posedge clk_i)
begin
data_mode_r_a <= #TCQ data_mode_i;
data_mode_r_b <= #TCQ data_mode_i;
data_mode_r_c <= #TCQ data_mode_i;
end
//reg GSR = 1'b0;
always @(rst_i)
begin
rst_ra = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
rst_rb = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
end
// register it . Just in case the calling modules didn't syn with clk_i
always @(posedge clk_i)
begin
run_traffic_reg <= #TCQ run_traffic_i;
end
assign bram_addr_i = {bram_cmd_i[29:0],2'b00};
assign bram_instr_i = bram_cmd_i[32:30];
assign bram_bl_i[5:0] = bram_cmd_i[38:33]; //41
//
//
reg COutc,COutd;
assign dcount_rst = counts_rst | rst_ra[0];
always @ (posedge clk_i)
begin
if (dcount_rst)
wr_data_counts <= #TCQ 'b0;
else if (memc_wr_en)
{COutc,wr_data_counts} <= #TCQ wr_data_counts + DWIDTH/8;
end
always @ (posedge clk_i)
begin
if (dcount_rst)
rd_data_counts <= #TCQ 'b0;
else if (memc_rd_en_o)
{COutd,rd_data_counts} <= #TCQ rd_data_counts + DWIDTH/8;
end
// **** for debug
// this part of logic is to check there are no commands been duplicated or dropped
// in the cmd_flow_control logic
generate
if (SIMULATION == "TRUE")
begin: cmd_check
wire fifo_error;
wire [31:0] xfer_addr;
wire [BL_WIDTH-1:0] xfer_cmd_bl;
wire cmd_fifo_rd;
assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid;
assign fifo_error = ( xfer_addr != memc_cmd_addr_o) ? 1'b1: 1'b0;
wire cmd_fifo_empty;
//assign cmd_fifo_rd = memc_cmd_en_o & ~memc_cmd_full_i & ~cmd_fifo_empty;
assign cmd_fifo_rd = memc_cmd_en_o & ~cmd_fifo_empty;
mig_7series_v4_2_afifo #
(.TCQ (TCQ),
.DSIZE (32+BL_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
cmd_fifo
(
.wr_clk (clk_i),
.rst (rst_ra[0]),
.wr_en (cmd_fifo_wr),
.wr_data ({cmd2flow_bl,cmd2flow_addr}),
.rd_en (cmd_fifo_rd),
.rd_clk (clk_i),
.rd_data ({xfer_cmd_bl,xfer_addr}),
.full (cmd_fifo_full),
.almost_full (),
.empty (cmd_fifo_empty)
);
end
else
begin
assign fifo_error = 1'b0;
end
endgenerate
reg [31:0] end_addr_r;
always @ (posedge clk_i)
end_addr_r <= end_addr_i;
mig_7series_v4_2_cmd_gen
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.PORT_MODE (PORT_MODE),
.BANK_WIDTH (BANK_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.ADDR_WIDTH (ADDR_WIDTH),
.DWIDTH (DWIDTH),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ),
.PRBS_EADDR (PRBS_EADDR),
.PRBS_SADDR (PRBS_SADDR )
)
u_c_gen
(
.clk_i (clk_i),
.rst_i (rst_ra),
.reading_rd_data_i (memc_rd_en_o),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_percent_write (vio_percent_write),
.single_operation (single_operation),
.run_traffic_i (run_traffic_reg),
.mem_pattern_init_done_i (mem_pattern_init_done_i),
.start_addr_i (start_addr_i),
.end_addr_i (end_addr_r),
.cmd_seed_i (cmd_seed_i),
.load_seed_i (load_seed_i),
.addr_mode_i (addr_mode_i),
.data_mode_i (data_mode_r_a),
.instr_mode_i (instr_mode_i),
.bl_mode_i (bl_mode_i),
.mode_load_i (mode_load_i),
// fixed pattern inputs interface
.fixed_bl_i (fixed_bl_i),
.fixed_addr_i (fixed_addr_i),
.fixed_instr_i (fixed_instr_i),
// BRAM FIFO input : Holist vector inputs
.bram_addr_i (bram_addr_i),
.bram_instr_i (bram_instr_i ),
.bram_bl_i (bram_bl_i ),
.bram_valid_i (bram_valid_i ),
.bram_rdy_o (bram_rdy_o ),
.rdy_i (flow2cmd_rdy),
.instr_o (cmd2flow_cmd),
.addr_o (cmd2flow_addr),
.bl_o (cmd2flow_bl),
// .m_addr_o (m_addr),
.cmd_o_vld (cmd2flow_valid),
.mem_init_done_o (mem_init_done)
);
assign memc_cmd_addr_o = addr_o;
assign qdr_wr_cmd_o = memc_wr_en_r;
assign cmd_full = memc_cmd_full_i;
mig_7series_v4_2_memc_flow_vcontrol #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE)
)
memc_control
(
.clk_i (clk_i),
.rst_i (rst_ra),
.data_mode_i (data_mode_r_b),
.cmds_gap_delay_value (cmds_gap_delay_value),
.mcb_wr_full_i (memc_wr_full_i),
.cmd_rdy_o (flow2cmd_rdy),
.cmd_valid_i (cmd2flow_valid),
.cmd_i (cmd2flow_cmd),
.mem_pattern_init_done_i (mem_pattern_init_done_i),
.addr_i (cmd2flow_addr),
.bl_i (cmd2flow_bl),
// interface to memc_cmd port
.mcb_cmd_full (cmd_full),
.cmd_o (memc_cmd_instr_o),
.addr_o (addr_o),
.bl_o (memc_bl_o),
.cmd_en_o (memc_cmd_en_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// interface to write data path module
.mcb_wr_en_i (memc_wr_en),
.last_word_wr_i (last_word_wr),
.wdp_rdy_i (wr_rdy),//(wr_rdy),
.wdp_valid_o (wr_valid),
.wdp_validB_o (wr_validB),
.wdp_validC_o (wr_validC),
.wr_addr_o (wr_addr),
.wr_bl_o (wr_bl),
// interface to read data path module
.rdp_rdy_i (rd_rdy),// (rd_rdy),
.rdp_valid_o (rd_valid),
.rd_addr_o (rd_addr),
.rd_bl_o (rd_bl)
);
/* afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (5),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_rb[0]),
.wr_en (!memc_rd_empty_i),
.wr_data (memc_rd_data_i),
.rd_en (memc_rd_en_o),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.almost_full (rd_mdata_fifo_afull),
.empty (rd_mdata_fifo_empty)
);
*/
wire cmd_rd_en;
assign cmd_rd_en = memc_cmd_en_o;
assign rdpath_data_valid_i =!memc_rd_empty_i ;
assign rdpath_rd_data_i = memc_rd_data_i ;
generate
if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE")
begin : RD_PATH
mig_7series_v4_2_read_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (PRBS_SADDR),
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
.ADDR_WIDTH (ADDR_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.SIMULATION (SIMULATION)
)
read_data_path
(
.clk_i (clk_i),
.rst_i (rst_rb),
.manual_clear_error (manual_clear_error),
.cmd_rdy_o (rd_rdy),
.cmd_valid_i (rd_valid),
.memc_cmd_full_i (memc_cmd_full_i),
.prbs_fseed_i (data_seed_i),
.cmd_sent (memc_cmd_instr_o),
.bl_sent (memc_bl_o[5:0]),
.cmd_en_i (cmd_rd_en),
.vio_instr_mode_value (vio_instr_mode_value),
.data_mode_i (data_mode_r_b),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (rd_addr),
.bl_i (rd_bl),
.data_rdy_o (memc_rd_en_o),
.data_valid_i (rdpath_data_valid_i),
.data_i (rdpath_rd_data_i),
.data_error_o (cmp_error),
.cmp_data_valid (cmp_data_valid),
.cmp_data_o (cmp_data),
.rd_mdata_o (mem_rd_data ),
.cmp_addr_o (cmp_addr),
.cmp_bl_o (cmp_bl),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
//****************************************************
.cumlative_dq_lane_error_r (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error),
.cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error),
.cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error),
.cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error),
.dq_r0_bit_error_r (dq_r0_bit_error_r),
.dq_f0_bit_error_r (dq_f0_bit_error_r),
.dq_r1_bit_error_r (dq_r1_bit_error_r),
.dq_f1_bit_error_r (dq_f1_bit_error_r),
.dq_r0_read_bit_r (dq_r0_read_bit),
.dq_f0_read_bit_r (dq_f0_read_bit),
.dq_r1_read_bit_r (dq_r1_read_bit),
.dq_f1_read_bit_r (dq_f1_read_bit),
.dq_r0_expect_bit_r (dq_r0_expect_bit),
.dq_f0_expect_bit_r (dq_f0_expect_bit ),
.dq_r1_expect_bit_r (dq_r1_expect_bit),
.dq_f1_expect_bit_r (dq_f1_expect_bit ),
.error_addr_o (error_addr)
);
end
else
begin
assign cmp_error = 1'b0;
assign cmp_data_valid = 1'b0;
assign cmp_data ='b0;
end
endgenerate
assign wr_path_data_rdy_i = !(memc_wr_full_i ) ;//& (~memc_cmd_full_i);
generate
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
begin : WR_PATH
mig_7series_v4_2_write_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_TYPE (MEM_TYPE),
.START_ADDR (PRBS_SADDR),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
write_data_path
(
.clk_i(clk_i),
.rst_i (rst_rb),
.cmd_rdy_o (wr_rdy),
.cmd_valid_i (wr_valid),
.cmd_validB_i (wr_validB),
.cmd_validC_i (wr_validC),
.prbs_fseed_i (data_seed_i),
.mode_load_i (mode_load_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done),
.data_mode_i (data_mode_r_c),
.last_word_wr_o (last_word_wr),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.addr_i (wr_addr),
.bl_i (wr_bl),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (wr_path_data_rdy_i),
.data_valid_o (memc_wr_en),
.data_o (memc_wr_data),
.data_mask_o (memc_wr_mask_o),
.data_wr_end_o (memc_wr_data_end)
);
end
else
begin
assign memc_wr_en = 1'b0;
assign memc_wr_data = 'b0;
assign memc_wr_mask_o = 'b0;
end
endgenerate
generate
if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" ))
begin: nonQDR_WR
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data ;
assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end;
end
// QDR
else
begin: QDR_WR
always @ (posedge clk_i)
memc_wr_data_r <= memc_wr_data;
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data_r ;
assign memc_wr_data_end_o = memc_wr_data_end;
end
endgenerate
//QDR
always @ (posedge clk_i)
begin
if (memc_wr_full_i)
begin
memc_wr_en_r <= 1'b0;
end
else
begin
memc_wr_en_r <= memc_wr_en;
end
end
mig_7series_v4_2_tg_status
#(
.TCQ (TCQ),
.DWIDTH (DWIDTH)
)
tg_status
(
.clk_i (clk_i),
.rst_i (rst_ra[2]),
.manual_clear_error (manual_clear_error),
.data_error_i (cmp_error),
.cmp_data_i (cmp_data),
.rd_data_i (mem_rd_data ),
.cmp_addr_i (cmp_addr),
.cmp_bl_i (cmp_bl),
.mcb_cmd_full_i (memc_cmd_full_i),
.mcb_wr_full_i (memc_wr_full_i),
.mcb_rd_empty_i (memc_rd_empty_i),
.error_status (error_status),
.error (error)
);
endmodule // memc_traffic_gen |
module mig_7series_v4_2_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule |
module mig_7series_v4_2_vio_init_pattern_bram #
(
parameter TCQ = 100,
parameter START_ADDR = 32'h00000000,
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 4,
parameter DEPTH = 16,
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = NUM_DQ_PINS // possible value : 0 to NUM_DQ_PINS
)
(
input clk_i,
input rst_i,
input cmd_start,
input [31:0] cmd_addr, //
input mode_load_i, // signal to initialze internal bram
// with input data1 through data9.
input [3:0] data_mode_i, // selection of data pattern.
input [31:0] data0, // data1 through data8 are
input [31:0] data1, // used as simple traffic data
input [31:0] data2, // pattern that repeats continuously
input [31:0] data3,
input [31:0] data4,
input [31:0] data5,
input [31:0] data6,
input [31:0] data7,
input [31:0] data8, // used a fixed input data
output reg bram_rd_valid_o,
input bram_rd_rdy_i,
output [31:0] dout_o
);
function integer logb2;
input [31:0] number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
reg [ADDR_WIDTH - 1:0] wr_addr /* synthesis syn_maxfan = 8 */;
reg [ADDR_WIDTH - 1:0] rd_addr /* synthesis syn_maxfan = 8 */;
reg init_write;
reg mode_load_r1;
reg mode_load_r2;
reg [31:0] data_in0;
reg [31:0] data_in1;
reg [31:0] data_in2;
reg [31:0] data_in3;
reg [31:0] data_in4;
reg [31:0] data_in5;
reg [31:0] data_in6;
reg [31:0] data_in7;
reg [31:0] data_in8;
reg [31:0] data_in9;
reg [31:0] data_in10;
reg [31:0] data_in11;
reg [31:0] data_in12;
reg [31:0] data_in13;
reg [31:0] data_in14;
reg [31:0] data_in15;
reg [31:0] hdata;
reg [7:0] mem_0 [0:DEPTH - 1];
reg [7:0] mem_1 [0:DEPTH - 1];
reg [7:0] mem_2 [0:DEPTH - 1];
reg [7:0] mem_3 [0:DEPTH - 1];
reg [31:0] data_in;
reg wr_en;
reg cmd_addr_r9;
integer i,j,k;
always @ (posedge clk_i)
begin
mode_load_r1 <= mode_load_i;
mode_load_r2 <= mode_load_r1;
end
always @ (posedge clk_i)
begin
if (rst_i)
init_write <= 'b0;
else if (wr_addr == {4'b0111})
init_write <= 'b1;
else if (mode_load_r1 && ~mode_load_r2 && data_mode_i != 4'b0010)
init_write <= 'b1;
end
// generate a mutil_cycle control siganl to improve timing.
always @ (posedge clk_i)
begin
if (rst_i)
wr_en <= 1'b1;
else if (init_write && data_mode_i != 4'b0010)
wr_en <= 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i)
wr_addr <= 'b0;
else if (data_mode_i == 4'h1)
wr_addr <= 4'b1000;
else if (data_mode_i == 4'b0011)
wr_addr <= 4'b1001;
else if (~init_write && data_mode_i == 4'b0100)
wr_addr <= 4'b0000;
else if (init_write && wr_en && data_mode_i != 4'b0010 && wr_addr != 15)
wr_addr <= wr_addr + 1'b1;
end
// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst.
// The incoming addr_i[5:2] determine the position of the pin driving oppsite polarity
// addr_i[6:2] = 5'h0f ; 32 bit data port
// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level.
always @ (posedge clk_i)
begin
for (i= 0; i <= 31; i= i+1) //begin: hammer_data
if (i >= NUM_DQ_PINS) begin
if (SEL_VICTIM_LINE == NUM_DQ_PINS)
hdata[i] <= 1'b0;
else if (
((i == SEL_VICTIM_LINE-1) || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE ||
(i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE ||
(i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE))
hdata[i] <= 1'b1;
else
hdata[i] <= 1'b0;
end
else
hdata[i] <= 1'b1;
end
// content formats
// {burst length, instruction, address}
initial begin
mem_0[0] = {2'b00,6'h00};
mem_1[0] = 8'h0;
mem_2[0] = 8'h0;
mem_3[0] = 8'h0;
mem_0[1] = {2'b00,6'h04};
mem_1[1] = 8'h0;
mem_2[1] = 8'h0;
mem_3[1] = 8'h0;
mem_0[2] = {2'b00,6'h08};
mem_1[2] = 8'h0;
mem_2[2] = 8'h0;
mem_3[2] = 8'h0;
mem_0[3] = {2'b00,6'h0c};
mem_1[3] = 8'h0;
mem_2[3] = 8'h0;
mem_3[3] = 8'h0;
mem_0[4] = {2'b00,6'h10};
mem_1[4] = 8'h0;
mem_2[4] = 8'h0;
mem_3[4] = 8'h0;
mem_0[5] = {2'b00,6'h14};
mem_1[5] = 8'h0;
mem_2[5] = 8'h0;
mem_3[5] = 8'h0;
mem_0[6] = {2'b00,6'h18};
mem_1[6] = 8'h0;
mem_2[6] = 8'h0;
mem_3[6] = 8'h0;
mem_0[7] = {2'b00,6'h1c};
mem_1[7] = 8'h0;
mem_2[7] = 8'h0;
mem_3[7] = 8'h0;
mem_0[8] = {2'b00,6'h20};
mem_1[8] = 8'h0;
mem_2[8] = 8'h0;
mem_3[8] = 8'h0;
mem_0[9] = {2'b00,6'h24};
mem_1[9] = 8'h0;
mem_2[9] = 8'h0;
mem_3[9] = 8'h0;
mem_0[10] = 8'hff;
mem_1[10] = 8'hff;
mem_2[10] = 8'hff;
mem_3[10] = 8'hff;
mem_0[11] = 8'h0;
mem_1[11] = 8'h0;
mem_2[11] = 8'h0;
mem_3[11] = 8'h0;
mem_0[12] = {2'b00,6'h30};
mem_1[12] = 8'h0;
mem_2[12] = 8'h0;
mem_3[12] = 8'h0;
mem_0[13] = {2'b00,6'h34};
mem_1[13] = 8'h0;
mem_2[13] = 8'h0;
mem_3[13] = 8'h0;
mem_0[14] = {2'b00,6'h38};
mem_1[14] = 8'h0;
mem_2[14] = 8'h0;
mem_3[14] = 8'h0;
mem_0[15] = {2'b00,6'h3c};
mem_1[15] = 8'h0;
mem_2[15] = 8'h0;
mem_3[15] = 8'h0;
end
// address is one cycle earlier.
always @ (posedge clk_i)
begin
if (rst_i)
data_in <= #TCQ data0;
else begin
case(wr_addr)
0: if (init_write)
data_in <= #TCQ data_in1;
else
data_in <= #TCQ data_in0;
1: data_in <= #TCQ data_in2;
2: data_in <= #TCQ data_in3;
3: data_in <= #TCQ data_in4;
4: data_in <= #TCQ data_in5;
5: data_in <= #TCQ data_in6;
6: data_in <= #TCQ data_in7;
7: data_in <= #TCQ data_in7;
8: data_in <= #TCQ data_in8;
9: data_in <= #TCQ data_in9;
10: data_in <= #TCQ data_in10;
11: data_in <= #TCQ data_in11;
12: data_in <= #TCQ data_in12;
13: data_in <= #TCQ data_in13;
14: data_in <= #TCQ data_in14;
15: data_in <= #TCQ data_in15;
default: data_in <= data8;
endcase
end
end
always @(posedge clk_i) begin
mem_0[wr_addr] <= data_in[7:0];
mem_1[wr_addr] <= data_in[15:8];
mem_2[wr_addr] <= data_in[23:16];
mem_3[wr_addr] <= data_in[31:24];
end
always @ (data_mode_i, data0,data1,data2,data3,data4,data5,data6,data7,data8,hdata)
begin
data_in0[31:0] = #TCQ data0;
data_in1[31:0] = #TCQ data1;
data_in2[31:0] = #TCQ data2;
data_in3[31:0] = #TCQ data3;
data_in4[31:0] = #TCQ data4;
data_in5[31:0] = #TCQ data5;
data_in6[31:0] = #TCQ data6;
data_in7[31:0] = #TCQ data7;
data_in8[31:0] = #TCQ data8;
data_in9[31:0] = #TCQ hdata;
data_in10[31:0] = #TCQ 32'hffffffff;
data_in11[31:0] = #TCQ 32'h00000000;
data_in12[31:0] = #TCQ 'b0;
data_in13[31:0] = #TCQ 'b0;
data_in14[31:0] = #TCQ 'b0;
data_in15[31:0] = #TCQ 'b0;
end
always @ (posedge clk_i)
begin
if (cmd_start)
cmd_addr_r9 <= cmd_addr[9];
end
always @ (posedge clk_i)
if (rst_i)
bram_rd_valid_o <= 1'b0;
else if (wr_addr[3:0] == {ADDR_WIDTH - 1{1'b1}} || data_mode_i == 2 || data_mode_i == 3)
bram_rd_valid_o <= 1'b1;
// rd_address generation depending on data pattern mode.
always @ (posedge clk_i)
begin
if (rst_i) begin
if (data_mode_i == 9) begin
rd_addr[3:1] <= #TCQ 3'b101;
rd_addr[0] <= #TCQ cmd_addr[9];
end
else if (data_mode_i == 1)
rd_addr[3:0] <= #TCQ 8;
else if (data_mode_i == 3) // address as data pattern
rd_addr <= #TCQ 9;
else
rd_addr <= #TCQ 0;
end
else if (cmd_start) begin
if (data_mode_i == 3)
rd_addr[3:0] <= #TCQ 9;
else if (data_mode_i == 1)
rd_addr[3:0] <= #TCQ 8;
else if (data_mode_i == 9) begin
rd_addr[3:1] <= #TCQ 3'b101;
rd_addr[0] <= #TCQ cmd_addr[9];
end
else
rd_addr[3:0] <= #TCQ 0;
end
else if (bram_rd_rdy_i) begin
case (data_mode_i)
4'h2: rd_addr <= #TCQ 0;
4'h4: if (rd_addr == 7)
rd_addr <= #TCQ 0;
else
rd_addr <= #TCQ rd_addr+ 1'b1;
4'h1: rd_addr <= #TCQ 8;
4'h3: rd_addr <= #TCQ 9;
4'h9: begin
rd_addr[3:1] <= #TCQ 3'b101;
rd_addr[0] <= #TCQ cmd_addr_r9;
end
default: rd_addr <= #TCQ 0;
endcase
end
end
// need to infer distributed RAM to meet output timing
// in upper level
assign dout_o = {mem_3[rd_addr],mem_2[rd_addr],mem_1[rd_addr],mem_0[rd_addr]}; //
endmodule |
module mig_7series_v4_2_read_data_path #(
parameter TCQ = 100,
parameter START_ADDR = 32'h00000000,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_TYPE = "DDR3",
parameter FAMILY = "VIRTEX6",
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 32,
parameter CMP_DATA_PIPE_STAGES = 3,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter SIMULATION = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
input manual_clear_error,
output cmd_rdy_o,
input cmd_valid_i,
input memc_cmd_full_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input [3:0] vio_instr_mode_value,
input [3:0] data_mode_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
output data_rdy_o,
input data_valid_i,
input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i,
output data_error_o, //data_error on user data bus side
output [DWIDTH-1:0] cmp_data_o,
output [DWIDTH-1:0] rd_mdata_o ,
output cmp_data_valid,
output [31:0] cmp_addr_o,
output [5 :0] cmp_bl_o,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on
// first error
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r ,
output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r,
output [31:0] error_addr_o
);
wire gen_rdy;
wire gen_valid;
wire [31:0] gen_addr;
wire [BL_WIDTH-1:0] gen_bl;
wire cmp_rdy;
wire cmp_valid;
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg data_error;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data;
wire [31:0] tg_st_addr_o;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r1,cmp_data_r2;
reg last_word_rd;
reg [5:0] bl_counter;
wire cmd_rdy;
wire user_bl_cnt_is_1;
wire data_rdy;
reg [DWIDTH:0] delayed_data;
wire rd_mdata_en;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r2;
reg force_wrcmd_gen;
reg wait_bl_end;
reg wait_bl_end_r1;
reg l_data_error ;
reg u_data_error;
reg v6_data_cmp_valid;
wire [DWIDTH -1 :0] rd_v6_mdata;
reg [DWIDTH -1 :0] cmpdata_r;
wire [DWIDTH -1 :0] rd_mdata;
reg cmp_data_en;
localparam ER_WIDTH = ( MEM_TYPE == "QDR2PLUS" && nCK_PER_CLK == 2) ? (NUM_DQ_PINS*MEM_BURST_LEN)/9 :
( MEM_TYPE != "QDR2PLUS" && nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS;
reg [ER_WIDTH - 1:0] error_byte;
reg [ER_WIDTH - 1:0] error_byte_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1;
wire [NUM_DQ_PINS-1:0] dq_bit_error;
wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] dq_lane_error;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2;
reg [NUM_DQ_PINS-1:0] dq_bit_error_r1;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask;
wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c;
reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg;
reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1;
wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ;
reg [31:0] error_addr_r1;
reg [31:0] error_addr_r2;
reg [31:0] error_addr_r3;
reg data_valid_r1;
reg data_valid_r2;
wire cmd_start_i;
always @ (posedge clk_i) begin
wait_bl_end_r1 <= #TCQ wait_bl_end;
rd_data_r1 <= #TCQ data_i;
rd_data_r2 <= #TCQ rd_data_r1;
end
reg [7:0] force_wrcmd_timeout_cnts ;
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111)
force_wrcmd_gen <= #TCQ 1'b0;
else if ((cmd_valid_i && bl_i > 16) || wait_bl_end )
force_wrcmd_gen <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1)
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (force_wrcmd_gen)
force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1;
end
always @ (posedge clk_i)
if (rst_i[0])
wait_bl_end <= #TCQ 1'b0;
else if (force_wrcmd_timeout_cnts == 8'b11111111)
wait_bl_end <= #TCQ 1'b0;
else if (gen_rdy && gen_valid && gen_bl > 16)
wait_bl_end <= #TCQ 1'b1;
else if (wait_bl_end && user_bl_cnt_is_1)
wait_bl_end <= #TCQ 1'b0;
assign cmd_rdy_o = cmd_rdy;
mig_7series_v4_2_read_posted_fifo #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (32),
.BL_WIDTH (BL_WIDTH)
)
read_postedfifo(
.clk_i (clk_i),
.rst_i (rst_i[0]),
.cmd_rdy_o (cmd_rdy ),
.cmd_valid_i (cmd_valid_i ),
.data_valid_i (data_rdy ), // input to
.addr_i (addr_i ),
.bl_i (bl_i ),
.cmd_start_i (cmd_start),
.cmd_sent (cmd_sent),
.bl_sent (bl_sent ),
.cmd_en_i (cmd_en_i),
.memc_cmd_full_i (memc_cmd_full_i),
.gen_valid_o (gen_valid ),
.gen_addr_o (gen_addr ),
.gen_bl_o (gen_bl ),
.rd_mdata_en (rd_mdata_en)
);
mig_7series_v4_2_rd_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH(DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH)
)
rd_datagen(
.clk_i (clk_i ),
.rst_i (rst_i[4:0]),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.vio_instr_mode_value (vio_instr_mode_value),
.cmd_rdy_o (gen_rdy ),
.cmd_valid_i (gen_valid ),
.mode_load_i (mode_load_i),
.cmd_start_o (cmd_start),
// .m_addr_i (m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (gen_addr ),
.bl_i (gen_bl ),
.user_bl_cnt_is_1_o (user_bl_cnt_is_1),
.data_rdy_i (data_valid_i ), // input to
.data_valid_o (cmp_valid ),
.tg_st_addr_o (tg_st_addr_o),
.data_o (cmp_data )
);
mig_7series_v4_2_afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_i[0]),
.wr_en (data_valid_i),
.wr_data (data_i),
.rd_en (rd_mdata_en),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.empty (),
.almost_full ()
);
always @ (posedge clk_i)
begin
// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data};
cmp_data_r1 <= #TCQ cmp_data;
cmp_data_r2 <= #TCQ cmp_data_r1;
end
assign rd_mdata_o = rd_mdata;
assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r1:
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata:
rd_data_r2;
assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en :
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i;
assign cmp_data_o = cmp_data_r2;
assign cmp_addr_o = tg_st_addr_o;//gen_addr;
assign cmp_bl_o = gen_bl[5:0];
assign data_rdy_o = data_rdy;
assign data_rdy = cmp_valid & data_valid_i;
always @ (posedge clk_i)
v6_data_cmp_valid <= #TCQ rd_mdata_en;
always @ (posedge clk_i)
cmp_data_en <= #TCQ data_rdy;
genvar i;
generate
if (FAMILY == "SPARTAN6")
begin: gen_error_sp6
always @ (posedge clk_i)
begin
if (cmp_data_en)
l_data_error <= #TCQ (rd_data_r1[DWIDTH/2-1:0] != cmp_data_r1[DWIDTH/2-1:0]);
else
l_data_error <= #TCQ 1'b0;
if (cmp_data_en)
u_data_error <= #TCQ (rd_data_r1[DWIDTH-1:DWIDTH/2] != cmp_data_r1[DWIDTH-1:DWIDTH/2]);
else
u_data_error <= #TCQ 1'b0;
data_error <= #TCQ l_data_error | u_data_error;
//synthesis translate_off
if (data_error)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
end
else
// if (FAMILY == "VIRTEX6" )
begin: gen_error_v7
if (nCK_PER_CLK == 2)
begin
if (MEM_TYPE == "QDR2PLUS")
begin: qdr_design
for (i = 0; i < (NUM_DQ_PINS*MEM_BURST_LEN)/9; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[9*(i+1)-1:9*i] !== cmp_data[9*(i+1)-1:9*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[9*(i+1)-1:9*i] != cmp_data[9*(i+1)-1:9*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*MEM_BURST_LEN; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
else
begin: ddr_design
for (i = 0; i < NUM_DQ_PINS/2; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*4; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= ( (data_i[i] !== cmp_data[i]) ) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= ( (data_i[i] != cmp_data[i]) ) ;
else
error_bit[i] <= 1'b0;
end
end
end
else //nCK_PER_CLK == 4
begin
for (i = 0; i < NUM_DQ_PINS; i = i + 1)
begin: gen_cmp_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*8; i = i + 1)
begin: gen_cmp_bit_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
always @ (posedge clk_i)
begin
dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0];
dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0];
dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ;
dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ;
dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ;
dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ;
dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1;
dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1;
dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1;
dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1;
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
else if (data_valid_r1) begin
error_byte_r1 <= #TCQ error_byte;
error_bit_r1 <= #TCQ error_bit;
end
else
begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error)
data_error <= #TCQ 1'b0;
else if (data_valid_r2)
data_error <= #TCQ | error_byte_r1;
else
data_error <= #TCQ 1'b0;
//synthesis translate_off
if (data_error)
$display ("ERROR: Expected data=%h, Received data=%h @ %t" ,cmp_data_r2, rd_data_r2, $time);
//synthesis translate_on
end
localparam NUM_OF_DQS = (MEM_TYPE == "QDR2PLUS") ? 9 : 8 ;
if (MEM_TYPE == "QDR2PLUS") begin: qdr_design_error_calc
if (MEM_BURST_LEN == 4) begin: bl4_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else begin: bl2_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end else begin: ddr_design_error_calc
if (nCK_PER_CLK == 4) begin: ck_4to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*4/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*5/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*6/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*7/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else if (nCK_PER_CLK == 2) begin: ck_2to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end
// mapped the user bits error to dq bits error
// mapper the error to rising 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r0_error_mapbit
assign dq_r0_bit_error[i] = (error_bit_r1[i]);
assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i];
end
// mapper the error to falling 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f0_error_mapbit
assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] );
assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i];
end
// mapper the error to rising 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r1_error_mapbit
assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]);
assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i];
end
// mapper the error to falling 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f1_error_mapbit
assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]);
assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i];
end
reg COuta;
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
dq_bit_error_r1 <= #TCQ 'b0;
dq_lane_error_r1 <= #TCQ 'b0;
dq_lane_error_r2 <= #TCQ 'b0;
data_valid_r1 <= #TCQ 1'b0;
data_valid_r2 <= #TCQ 1'b0;
dq_r0_bit_error_r <= #TCQ 'b0;
dq_f0_bit_error_r <= #TCQ 'b0;
dq_r1_bit_error_r <= #TCQ 'b0;
dq_f1_bit_error_r <= #TCQ 'b0;
cumlative_dq_lane_error_reg <= #TCQ 'b0;
cumlative_dq_r0_bit_error_r <= #TCQ 'b0;
cumlative_dq_f0_bit_error_r <= #TCQ 'b0;
cumlative_dq_r1_bit_error_r <= #TCQ 'b0;
cumlative_dq_f1_bit_error_r <= #TCQ 'b0;
error_addr_r1 <= #TCQ 'b0;
error_addr_r2 <= #TCQ 'b0;
error_addr_r3 <= #TCQ 'b0;
end
else begin
data_valid_r1 <= #TCQ data_valid_i;
data_valid_r2 <= #TCQ data_valid_r1;
dq_lane_error_r1 <= #TCQ dq_lane_error;
dq_bit_error_r1 <= #TCQ dq_bit_error;
cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c;
cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c;
cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c;
cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c;
dq_r0_bit_error_r <= #TCQ dq_r0_bit_error;
dq_f0_bit_error_r <= #TCQ dq_f0_bit_error;
dq_r1_bit_error_r <= #TCQ dq_r1_bit_error;
dq_f1_bit_error_r <= #TCQ dq_f1_bit_error;
error_addr_r2 <= #TCQ error_addr_r1;
error_addr_r3 <= #TCQ error_addr_r2;
if (rd_mdata_en)
error_addr_r1 <= #TCQ gen_addr;
else if (data_valid_i)
{COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4;
end
end
end
endgenerate
assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg;
assign dq_error_bytelane_cmp = dq_lane_error_r1;
assign data_error_o = data_error;
assign error_addr_o = error_addr_r3;
endmodule |
module mig_7series_v4_2_memc_ui_top_std #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter SKIP_CALIB = "FALSE",
parameter TAPSPERKCLK = 56,
parameter FPGA_VOLT_TYPE = "N"
)
(
// Clock and reset ports
input clk,
input clk_div2,
input rst_div2,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [2*nCK_PER_CLK-1:0] app_ecc_single_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// Ports to be used with SKIP_CALIB defined
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output [1023:0] dbg_poc
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
assign fi_xor_we = {DQ_WIDTH/8{1'b0}} ;
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}} ;
mig_7series_v4_2_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
mem_intfc0
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
// skip calibration i/f
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.dbg_poc (dbg_poc[1023:0])
);
mig_7series_v4_2_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.app_ecc_single_err (app_ecc_single_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input clk,
input reset
);
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
// byte sum (unsigned)
wire [31:0] cfu0;
assign cfu0[31:0] = cmd_payload_inputs_0[7:0] + cmd_payload_inputs_1[7:0] +
cmd_payload_inputs_0[15:8] + cmd_payload_inputs_1[15:8] +
cmd_payload_inputs_0[23:16] + cmd_payload_inputs_1[23:16] +
cmd_payload_inputs_0[31:24] + cmd_payload_inputs_1[31:24];
// byte swap
wire [31:0] cfu1;
assign cfu1[31:24] = cmd_payload_inputs_0[7:0];
assign cfu1[23:16] = cmd_payload_inputs_0[15:8];
assign cfu1[15:8] = cmd_payload_inputs_0[23:16];
assign cfu1[7:0] = cmd_payload_inputs_0[31:24];
// bit reverse
wire [31:0] cfu2;
genvar n;
generate
for (n=0; n<32; n=n+1) begin
assign cfu2[n] = cmd_payload_inputs_0[31-n];
end
endgenerate
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[1] ? cfu2 :
( cmd_payload_function_id[0] ? cfu1 : cfu0);
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input reset,
input clk
);
// Trivial handshaking for a combinational CFU
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
wire [31:0] mul = $signed(cmd_payload_inputs_0) * $signed(cmd_payload_inputs_1);
wire [31:0] mulsh = $signed(mul) >>> 10;
assign rsp_payload_outputs_0 = cmd_payload_function_id[0] ? mul : mulsh;
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input reset,
input clk
);
// Trivial handshaking for a combinational CFU
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[0] ?
cmd_payload_inputs_1 :
cmd_payload_inputs_0 ;
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output reg rsp_valid,
input rsp_ready,
output reg [31:0] rsp_payload_outputs_0,
input reset,
input clk
);
localparam InputOffset = $signed(9'd128);
// SIMD multiply step:
wire signed [15:0] prod_0, prod_1, prod_2, prod_3;
assign prod_0 = ($signed(cmd_payload_inputs_0[7 : 0]) + InputOffset)
* $signed(cmd_payload_inputs_1[7 : 0]);
assign prod_1 = ($signed(cmd_payload_inputs_0[15: 8]) + InputOffset)
* $signed(cmd_payload_inputs_1[15: 8]);
assign prod_2 = ($signed(cmd_payload_inputs_0[23:16]) + InputOffset)
* $signed(cmd_payload_inputs_1[23:16]);
assign prod_3 = ($signed(cmd_payload_inputs_0[31:24]) + InputOffset)
* $signed(cmd_payload_inputs_1[31:24]);
wire signed [31:0] sum_prods;
assign sum_prods = prod_0 + prod_1 + prod_2 + prod_3;
// Only not ready for a command when we have a response.
assign cmd_ready = ~rsp_valid;
always @(posedge clk) begin
if (reset) begin
rsp_payload_outputs_0 <= 32'b0;
rsp_valid <= 1'b0;
end else if (rsp_valid) begin
// Waiting to hand off response to CPU.
rsp_valid <= ~rsp_ready;
end else if (cmd_valid) begin
rsp_valid <= 1'b1;
// Accumulate step:
rsp_payload_outputs_0 <= |cmd_payload_function_id[9:3]
? 32'b0
: rsp_payload_outputs_0 + sum_prods;
end
end
endmodule |
module Cfu (
input cmd_valid,
output cmd_ready,
input [2:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input clk,
input reset
);
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
// byte sum (unsigned)
wire [31:0] cfu0;
assign cfu0[31:0] = cmd_payload_inputs_0[7:0] + cmd_payload_inputs_1[7:0] +
cmd_payload_inputs_0[15:8] + cmd_payload_inputs_1[15:8] +
cmd_payload_inputs_0[23:16] + cmd_payload_inputs_1[23:16] +
cmd_payload_inputs_0[31:24] + cmd_payload_inputs_1[31:24];
// byte swap
wire [31:0] cfu1;
assign cfu1[31:24] = cmd_payload_inputs_0[7:0];
assign cfu1[23:16] = cmd_payload_inputs_0[15:8];
assign cfu1[15:8] = cmd_payload_inputs_0[23:16];
assign cfu1[7:0] = cmd_payload_inputs_0[31:24];
// bit reverse
wire [31:0] cfu2;
genvar n;
generate
for (n=0; n<32; n=n+1) begin
assign cfu2[n] = cmd_payload_inputs_0[31-n];
end
endgenerate
// select output
assign rsp_payload_outputs_0 = cmd_payload_function_id[1] ? cfu2 :
( cmd_payload_function_id[0] ? cfu1 : cfu0);
endmodule |
module depth_split (we, addr, datain, dataout, clk);
input we;
input[11 - 1:0] addr;
input[2 - 1:0] datain;
output[2 - 1:0] dataout;
wire[2 - 1:0] dataout;
input clk;
single_port_ram new_ram(
.clk (clk),
.we(we),
.data(datain),
.out(dataout),
.addr(addr)
);
endmodule |
module accum (clock, reset_n, D, Q);
input clock, reset_n;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge clock)
begin
if (reset_n)
tmp <= 4'b0000;
else
tmp <= tmp + D;
end
assign Q = tmp;
endmodule |
module simple(clock,
enable,
value_out
);
input clock;
input enable;
reg temp;
output value_out;
always @(posedge clock)
begin
if (enable == 1'b1) begin
temp <= 1'b0;
end
end
assign value_out = temp;
endmodule |
module simple_comp
(
a_in, b_in, c_in,
d_out,
clock, rst
);
input [15:0] a_in;
input [15:0] b_in;
input [15:0] c_in;
input clock;
input rst;
output [15:0] d_out;
reg [15:0] sum_c;
reg [15:0] sum_d;
always @ (posedge clock)
if(rst)
sum_c <= 16'b0;
else
sum_c <= a_in + b_in;
always @ (posedge clock)
if(rst)
sum_d <= 16'b0;
else
sum_d <= sum_c + c_in;
assign d_out = sum_d;
endmodule |
module counter
(
d_out, clock, rst, d_en
);
input clock;
input rst;
input d_en;
output [11:0] d_out;
reg [11:0] counter;
always @ (posedge clock)
if(rst)
begin
counter <= 12'b0;
end
else if(d_en)
begin
counter <= counter + 1'b1;
end
else
begin
counter <= counter;
end
assign d_out = counter;
endmodule |
module inv_shift_reg
(
din,
dout,
clock,
rst
);
input din;
output dout;
input clock;
input rst;
reg [31:0] s_reg;
always @ (posedge clock)
if(rst)
s_reg <= 32'b0;
else
begin
s_reg[31:1] <= s_reg[30:0];
s_reg[0] <= din;
end
assign dout = s_reg[31];
endmodule |
module wide_inv_reg
(
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input [31:0] d_in;
reg [31:0] d_d;
output [31:0] d_out;
always @ (posedge clock)
if(rst)
d_d <= 32'b0;
else
d_d <= ~d_in;
assign d_out = d_d;
endmodule |
module memory_controller
(
clk,
memory_controller_address,
memory_controller_write_enable,
memory_controller_in,
memory_controller_out
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [4:0] str_address;
reg str_write_enable;
reg [7:0] str_in;
wire [7:0] str_out;
single_port_ram _str (
.clk( clk ),
.addr( str_address ),
.we( str_write_enable ),
.data( str_in ),
.out( str_out )
);
wire tag;
//must use all wires inside module.....
assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
prevTag <= tag;
always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
begin
case(tag)
1'b0:
begin
str_address = memory_controller_address[5-1+0:0];
str_write_enable = memory_controller_write_enable;
str_in[8-1:0] = memory_controller_in[8-1:0];
end
endcase
case(prevTag)
1'b0:
memory_controller_out = str_out;
endcase
end
endmodule |
module memset
(
clk,
reset,
start,
finish,
return_val,
m,
c,
n,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
input clk;
input reset;
input start;
output finish;
reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
input [31:0] c;
input [31:0] n;
output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output memory_controller_write_enable;
reg memory_controller_write_enable;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [3:0] cur_state;
/*
parameter Wait = 4'd0;
parameter entry = 4'd1;
parameter entry_1 = 4'd2;
parameter entry_2 = 4'd3;
parameter bb = 4'd4;
parameter bb_1 = 4'd5;
parameter bb1 = 4'd6;
parameter bb1_1 = 4'd7;
parameter bb_nph = 4'd8;
parameter bb2 = 4'd9;
parameter bb2_1 = 4'd10;
parameter bb2_2 = 4'd11;
parameter bb2_3 = 4'd12;
parameter bb2_4 = 4'd13;
parameter bb4 = 4'd14;
*/
memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
reg [31:0] indvar;
reg var1;
reg [31:0] tmp;
reg [31:0] tmp8;
reg var2;
reg [31:0] var0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
reg [31:0] indvar_next;
reg exitcond;
always @(posedge clk)
if (reset)
cur_state <= 4'b0000;
else
case(cur_state)
4'b0000:
begin
finish <= 1'b0;
if (start == 1'b1)
cur_state <= 4'b0001;
else
cur_state <= 4'b0000;
end
4'b0001:
begin
var0 <= n & 32'b00000000000000000000000000000011;
cur_state <= 4'b0010;
end
4'b0010:
begin
var1 <= 1'b0;
var0 <= 32'b00000000000000000000000000000000;
cur_state <= 4'b0011;
end
4'b0011:
begin
if (|var1) begin
cur_state <= 4'b0110;
end
else
begin
cur_state <= 4'b0100;
end
end
4'b0100:
begin
cur_state <= 4'b0101;
end
4'b0101:
begin
cur_state <= 4'b0110;
end
4'b0110:
begin
var2 <= | (n [31:4]);
cur_state <= 4'b0111;
end
4'b0111:
begin
if (|var2)
begin
cur_state <= 4'b1110;
end
else
begin
cur_state <= 4'b1000;
end
end
4'b1000:
begin
tmp <= n ;
indvar <= 32'b00000000000000000000000000000000;
cur_state <= 4'b1001;
end
4'b1001:
begin
cur_state <= 4'b1010;
end
4'b1010:
begin
tmp8 <= indvar;
indvar_next <= indvar;
cur_state <= 4'b1011;
end
4'b1011:
begin
scevgep <= (m & tmp8);
exitcond <= (indvar_next == tmp);
cur_state <= 4'b1100;
end
4'b1100:
begin
s_07 <= scevgep;
cur_state <= 4'b1101;
end
4'b1101:
begin
if (exitcond)
begin
cur_state <= 4'b1110;
end
else
begin
indvar <= indvar_next;
cur_state <= 4'b1001;
end
end
4'b1110:
begin
return_val <= m;
finish <= 1'b1;
cur_state <= 4'b0000;
end
endcase
always @(cur_state)
begin
case(cur_state)
4'b1101:
begin
memory_controller_address = s_07;
memory_controller_write_enable = 1'b1;
memory_controller_in = c;
end
endcase
end
endmodule |
module single_inv_reg
(
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input d_in;
reg d_d;
output d_out;
always @ (posedge clock)
if(rst)
d_d <= 1'b0;
else
d_d <= ~d_in;
assign d_out = d_d;
endmodule |
module wide_inv
(
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input [31:0] d_in;
output [31:0] d_out;
assign d_out = ~d_in;
endmodule |
module single_inv
(
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input d_in;
output d_out;
assign d_out = ~d_in;
endmodule |
module multi_consumer
(
d_in,
d_out_1, d_out_2, d_out_4, d_out_7,
clock, rst
);
input clock;
input rst;
input [15:0] d_in;
output [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
assign d_out_1 = d_in + 1'b1;
assign d_out_2 = d_in + 2'b10;
assign d_out_4 = d_in + 3'b100;
assign d_out_7 = d_in + 3'b111;
endmodule |
module ff_en
(
d_in, d_out, clock, rst, d_en
);
input clock;
input rst;
input d_en;
input [9:0] d_in;
output [9:0] d_out;
reg [9:0] ff_d;
assign d_out = ff_d;
always @ (posedge clock)
if(rst)
ff_d <= 10'b0;
else if(d_en)
ff_d <= d_in;
else
ff_d <= ff_d;
endmodule |
module dcounter
(
d_out, clock, rst, d_en
);
input clock;
input rst;
input d_en;
output [15:0] d_out;
reg [15:0] counter;
always @ (posedge clock)
if(rst)
begin
counter <= 16'b0;
end
else if(d_en)
begin
counter <= counter - 1'b1;
end
else
begin
counter <= counter;
end
assign d_out = counter;
endmodule |
module counter
(
d_out, clock, rst, d_en
);
input clock;
input rst;
input d_en;
output [63:0] d_out;
reg [63:0] counter;
always @ (posedge clock)
if(rst)
begin
counter <= 64'b0;
end
else if(d_en)
begin
counter <= counter + 1'b1;
end
else
begin
counter <= counter;
end
assign d_out = counter;
endmodule |
module bfly(clock,
reset,
re_w,
re_x,
re_y,
im_w,
im_x,
im_y,
re_z,
im_z
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] re_w;
input [`BITS-1:0] re_x;
input [`BITS-1:0] re_y;
input [`BITS-1:0] im_w;
input [`BITS-1:0] im_x;
input [`BITS-1:0] im_y;
output [`BITS-1:0] re_z;
output [`BITS-1:0] im_z;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] x4;
wire [`BITS-1:0] sub5;
wire [`BITS-1:0] add6;
wire [`BITS-1:0] re_z;
wire [`BITS-1:0] im_z;
reg [`BITS-1:0] re_y_reg1;
reg [`BITS-1:0] re_y_reg2;
reg [`BITS-1:0] re_y_reg3;
reg [`BITS-1:0] re_y_reg4;
reg [`BITS-1:0] re_y_reg5;
reg [`BITS-1:0] re_y_reg6;
reg [`BITS-1:0] im_y_reg1;
reg [`BITS-1:0] im_y_reg2;
reg [`BITS-1:0] im_y_reg3;
reg [`BITS-1:0] im_y_reg4;
reg [`BITS-1:0] im_y_reg5;
reg [`BITS-1:0] im_y_reg6;
//assign x1 = re_x * re_w;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(re_x),
.opb(re_w),
.out(x1),
.control(x1_control)
);
//assign x2 = im_x * im_w;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(im_x),
.opb(im_w),
.out(x2),
.control(x2_control)
);
//assign x3 = re_x * im_w;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(re_x),
.opb(im_w),
.out(x3),
.control(x3_control)
);
//assign x4 = im_x * re_w;
wire [7:0] x4_control;
fpu_mul x4_mul
(
.clk(clock),
.opa(im_x),
.opb(re_w),
.out(x4),
.control(x4_control)
);
//assign sub5 = x1 - x2;
wire [7:0] sub5_control;
fpu_add sub5_add
(
.clk(clock),
.opa(x1),
.opb(x2),
.out(sub5),
.control(sub5_control)
);
//assign add6 = x3 + x4;
wire [7:0] add6_control;
fpu_add add6_add
(
.clk(clock),
.opa(x3),
.opb(x4),
.out(add6),
.control(add6_control)
);
//assign re_z = sub5 + re_y_reg1;
wire [7:0] re_z_control;
fpu_add re_z_add
(
.clk(clock),
.opa(sub5),
.opb(re_y_reg6),
.out(re_z),
.control(re_z_control)
);
//assign im_z = add6 + im_y_reg1;
wire [7:0] im_z_control;
fpu_add im_z_add
(
.clk(clock),
.opa(add6),
.opb(im_y_reg6),
.out(im_z),
.control(im_z_control)
);
always @(posedge clock)
begin
re_y_reg1 <= re_y;
re_y_reg2 <= re_y_reg1;
re_y_reg3 <= re_y_reg2;
re_y_reg4 <= re_y_reg3;
re_y_reg5 <= re_y_reg4;
re_y_reg6 <= re_y_reg5;
im_y_reg1 <= im_y;
im_y_reg2 <= im_y_reg1;
im_y_reg3 <= im_y_reg2;
im_y_reg4 <= im_y_reg3;
im_y_reg5 <= im_y_reg4;
im_y_reg6 <= im_y_reg5;
end
endmodule |
module bgm(clock,
reset,
sigma_a,
sigma_b,
sigma_c,
Fn,
dw_x,
dw_y,
dw_z,
dt,
Fn_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] sigma_a;
input [`BITS-1:0] sigma_b;
input [`BITS-1:0] sigma_c;
input [`BITS-1:0] Fn;
input [`BITS-1:0] dw_x;
input [`BITS-1:0] dw_y;
input [`BITS-1:0] dw_z;
input [`BITS-1:0] dt;
output [`BITS-1:0] Fn_out;
wire [`BITS-1:0] x0;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] x4;
wire [`BITS-1:0] x5;
wire [`BITS-1:0] x6;
wire [`BITS-1:0] x7;
wire [`BITS-1:0] x8;
wire [`BITS-1:0] x9;
wire [`BITS-1:0] x10;
wire [`BITS-1:0] a0;
wire [`BITS-1:0] a1;
wire [`BITS-1:0] a2;
wire [`BITS-1:0] a3;
wire [`BITS-1:0] a4;
wire [`BITS-1:0] a5;
wire [`BITS-1:0] a6;
wire [`BITS-1:0] a7;
wire [`BITS-1:0] a8;
wire [`BITS-1:0] Fn_out;
wire [`BITS-1:0] Fn_delay_chain;
wire [`BITS-1:0] Fn_delay_chain_delay5;
wire [`BITS-1:0] dw_x_delay;
wire [`BITS-1:0] dw_y_delay;
wire [`BITS-1:0] dw_z_delay;
wire [`BITS-1:0] sigma_a_delay;
wire [`BITS-1:0] sigma_b_delay;
wire [`BITS-1:0] sigma_c_delay;
wire [`BITS-1:0] fifo_out1;
wire [`BITS-1:0] fifo_out2;
wire [`BITS-1:0] fifo_out3;
wire [`BITS-1:0] a4_delay5;
/*
delay44 delay_u1(clock, dw_x, dw_x_delay);
delay44 delay_u2(clock, dw_y, dw_y_delay);
delay44 delay_u3(clock, dw_z, dw_z_delay);
delay44 delay_u4(clock, sigma_a, sigma_a_delay);
delay44 delay_u5(clock, sigma_b, sigma_b_delay);
delay44 delay_u6(clock, sigma_c, sigma_c_delay);
fifo fifo_1(clock, a0, fifo_out1);
fifo fifo_2(clock, a1, fifo_out2);
fifo fifo_3(clock, a2, fifo_out3);
*/
delay5 delay_u1(clock, dw_x, dw_x_delay);
delay5 delay_u2(clock, dw_y, dw_y_delay);
delay5 delay_u3(clock, dw_z, dw_z_delay);
delay5 delay_u4(clock, sigma_a, sigma_a_delay);
delay5 delay_u5(clock, sigma_b, sigma_b_delay);
delay5 delay_u6(clock, sigma_c, sigma_c_delay);
delay5 fifo_1(clock, a0, fifo_out1);
delay5 fifo_2(clock, a1, fifo_out2);
delay5 fifo_3(clock, a2, fifo_out3);
//assign x0 = Fn * sigma_a;
wire [7:0] x0_control;
fpu_mul x0_mul
(
.clk(clock),
.opa(Fn),
.opb(sigma_a),
.out(x0),
.control(x0_control)
);
//assign x1 = Fn * sigma_b;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(Fn),
.opb(sigma_b),
.out(x1),
.control(x1_control)
);
//assign x2 = Fn * sigma_c;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(Fn),
.opb(sigma_c),
.out(x2),
.control(x2_control)
);
//assign a0 = x0 + fifo_out1;
wire [7:0] a0_control;
fpu_add a0_add
(
.clk(clock),
.opa(x0),
.opb(fifo_out1),
.out(a0),
.control(a0_control)
);
//assign a1 = x1 + fifo_out2;
wire [7:0] a1_control;
fpu_add a1_add
(
.clk(clock),
.opa(x1),
.opb(fifo_out2),
.out(a1),
.control(a1_control)
);
//assign a2 = x2 + fifo_out3;
wire [7:0] a2_control;
fpu_add a2_add
(
.clk(clock),
.opa(x2),
.opb(fifo_out3),
.out(a2),
.control(a2_control)
);
//assign x3 = dw_x_delay * sigma_a_delay;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(dw_x_delay),
.opb(sigma_a_delay),
.out(x3),
.control(x3_control)
);
//assign x4 = a0 * sigma_a_delay;
wire [7:0] x4_control;
fpu_mul x4_mul
(
.clk(clock),
.opa(a0),
.opb(sigma_a_delay),
.out(x4),
.control(x4_control)
);
//assign x5 = dw_y_delay * sigma_b_delay;
wire [7:0] x5_control;
fpu_mul x5_mul
(
.clk(clock),
.opa(dw_y_delay),
.opb(sigma_b_delay),
.out(x5),
.control(x5_control)
);
//assign x6 = a1 * sigma_b_delay;
wire [7:0] x6_control;
fpu_mul x6_mul
(
.clk(clock),
.opa(a1),
.opb(sigma_b_delay),
.out(x6),
.control(x6_control)
);
//assign x7 = dw_z_delay * sigma_c_delay;
wire [7:0] x7_control;
fpu_mul x7_mul
(
.clk(clock),
.opa(dw_z_delay),
.opb(sigma_c_delay),
.out(x7),
.control(x7_control)
);
//assign x8 = a2 * sigma_c_delay;
wire [7:0] x8_control;
fpu_mul x8_mul
(
.clk(clock),
.opa(a2),
.opb(sigma_c_delay),
.out(x8),
.control(x8_control)
);
//assign a3 = x3 + x5;
wire [7:0] a3_control;
fpu_add a3_add
(
.clk(clock),
.opa(x3),
.opb(x5),
.out(a3),
.control(a3_control)
);
//assign a4 = a3 + x7;
wire [7:0] a4_control;
fpu_add a4_add
(
.clk(clock),
.opa(a3),
.opb(x7),
.out(a4),
.control(a4_control)
);
//assign a5 = x4 + x6;
wire [7:0] a5_control;
fpu_add a5_add
(
.clk(clock),
.opa(x4),
.opb(x6),
.out(a5),
.control(a5_control)
);
//assign a6 = a5 + x8;
wire [7:0] a6_control;
fpu_add a6_add
(
.clk(clock),
.opa(a5),
.opb(x8),
.out(a6),
.control(a6_control)
);
delay5 delay_a5(clock, a4, a4_delay5);
//assign x9 = dt * a6;
wire [7:0] x9_control;
fpu_mul x9_mul
(
.clk(clock),
.opa(dt),
.opb(a6),
.out(x9),
.control(x9_control)
);
//assign a7 = a4_delay5 + x9;
wire [7:0] a7_control;
fpu_add a7_add
(
.clk(clock),
.opa(a4_delay5),
.opb(x9),
.out(a7),
.control(a7_control)
);
//delay_chain delay_Fn(clock, Fn, Fn_delay_chain);
delay5 delay_Fn(clock, Fn, Fn_delay_chain);
delay5 delay_Fn_delay5(clock, Fn_delay_chain, Fn_delay_chain_delay5);
//assign x10 = a7 * Fn_delay_chain;
wire [7:0] x10_control;
fpu_mul x10_mul
(
.clk(clock),
.opa(a7),
.opb(Fn_delay_chain),
.out(x10),
.control(x10_control)
);
//assign a8 = Fn_delay_chain_delay5 + x10;
wire [7:0] a8_control;
fpu_add a8_add
(
.clk(clock),
.opa(Fn_delay_chain_delay5),
.opb(x10),
.out(a8),
.control(a8_control)
);
assign Fn_out = a8;
endmodule |
module fifo(clock, fifo_in, fifo_out);
input clock;
input [`BITS-1:0] fifo_in;
output [`BITS-1:0] fifo_out;
wire [`BITS-1:0] fifo_out;
reg [`BITS-1:0] freg1;
reg [`BITS-1:0] freg2;
reg [`BITS-1:0] freg3;
reg [`BITS-1:0] freg4;
reg [`BITS-1:0] freg5;
reg [`BITS-1:0] freg6;
reg [`BITS-1:0] freg7;
reg [`BITS-1:0] freg8;
reg [`BITS-1:0] freg9;
reg [`BITS-1:0] freg10;
reg [`BITS-1:0] freg11;
reg [`BITS-1:0] freg12;
reg [`BITS-1:0] freg13;
reg [`BITS-1:0] freg14;
reg [`BITS-1:0] freg15;
reg [`BITS-1:0] freg16;
reg [`BITS-1:0] freg17;
reg [`BITS-1:0] freg18;
reg [`BITS-1:0] freg19;
reg [`BITS-1:0] freg20;
reg [`BITS-1:0] freg21;
reg [`BITS-1:0] freg22;
reg [`BITS-1:0] freg23;
reg [`BITS-1:0] freg24;
reg [`BITS-1:0] freg25;
reg [`BITS-1:0] freg26;
reg [`BITS-1:0] freg27;
reg [`BITS-1:0] freg28;
reg [`BITS-1:0] freg29;
reg [`BITS-1:0] freg30;
reg [`BITS-1:0] freg31;
reg [`BITS-1:0] freg32;
reg [`BITS-1:0] freg33;
reg [`BITS-1:0] freg34;
assign fifo_out = freg34;
always @(posedge clock)
begin
freg1 <= fifo_in;
freg2 <= freg1;
freg3 <= freg2;
freg4 <= freg3;
freg5 <= freg4;
freg6 <= freg5;
freg7 <= freg6;
freg8 <= freg7;
freg9 <= freg8;
freg10 <= freg9;
freg11 <= freg10;
freg12 <= freg11;
freg13 <= freg12;
freg14 <= freg13;
freg15 <= freg14;
freg16 <= freg15;
freg17 <= freg16;
freg18 <= freg17;
freg19 <= freg18;
freg20 <= freg19;
freg21 <= freg20;
freg22 <= freg21;
freg23 <= freg22;
freg24 <= freg23;
freg25 <= freg24;
freg26 <= freg25;
freg27 <= freg26;
freg28 <= freg27;
freg29 <= freg28;
freg30 <= freg29;
freg31 <= freg30;
freg32 <= freg31;
freg33 <= freg32;
freg34 <= freg33;
end
endmodule |
module delay5 (clock, d5_delay_in, d5_delay_out);
input clock;
input [`BITS-1:0] d5_delay_in;
output [`BITS-1:0] d5_delay_out;
//FIFO delay
reg [`BITS-1:0] d5_reg1;
/*
reg [`BITS-1:0] d5_reg2;
reg [`BITS-1:0] d5_reg3;
reg [`BITS-1:0] d5_reg4;
reg [`BITS-1:0] d5_reg5;
reg [`BITS-1:0] d5_reg6;
*/
assign d5_delay_out = d5_reg1;
always @(posedge clock)
begin
d5_reg1 <= d5_delay_in;
/*
d5_reg2 <= d5_reg1;
d5_reg3 <= d5_reg2;
d5_reg4 <= d5_reg3;
d5_reg5 <= d5_reg4;
d5_reg6 <= d5_reg5;
*/
end
endmodule |
module delay44 (clock, delay_in, delay_out);
input clock;
input [`BITS-1:0] delay_in;
output [`BITS-1:0] delay_out;
// wire [`BITS-1:0] delay_out;
//FIFO delay
wire [`BITS-1:0] fifo_out;
//multiplier delay
wire [`BITS-1:0] delay5_dout1;
//adder delay
wire [`BITS-1:0] delay5_dout2;
fifo fifo_delay(clock, delay_in , fifo_out);
delay5 delay_d1(clock, fifo_out, delay5_dout1);
delay5 delay_d2(clock, delay5_dout1, delay5_dout2);
assign delay_out = delay5_dout2;
// always @(posedge clock)
// begin
// fifo_out <= delay_in;
// delay5_dout1 <= fifo_out;
// delay5_dout2 <= delay5_dout1;
// end
endmodule |
module delay_chain (clock, delay_in, delay_out);
input clock;
input [`BITS-1:0] delay_in;
output [`BITS-1:0] delay_out;
// wire [`BITS-1:0] delay_out;
wire [`BITS-1:0] delay44_out;
wire [`BITS-1:0] delay5_out1;
wire [`BITS-1:0] delay5_out2;
wire [`BITS-1:0] delay5_out3;
wire [`BITS-1:0] delay5_out4;
delay44 delay_c1(clock, delay_in, delay44_out);
delay5 delay_c2(clock, delay44_out, delay5_out1);
delay5 delay_c3(clock, delay5_out1, delay5_out2);
delay5 delay_c4(clock, delay5_out2, delay5_out3);
delay5 delay_c5(clock, delay5_out3, delay5_out4);
assign delay_out = delay5_out4;
endmodule |
module syn7(clock,
// reset,
in1_reg,
in2_reg,
in3_reg,
in4_reg,
in5_reg,
out_1,
out_2,
out_3,
out_4
);
// SIGNAL DECLARATIONS
input clock;
//input reset;
input [`BITS-1:0] in1_reg;
input [`BITS-1:0] in2_reg;
input [`BITS-1:0] in3_reg;
input [`BITS-1:0] in4_reg;
input [`BITS-1:0] in5_reg;
reg [`BITS-1:0] in1;
reg [`BITS-1:0] in2;
reg [`BITS-1:0] in3;
reg [`BITS-1:0] in4;
reg [`BITS-1:0] in5;
output [`BITS-1:0] out_1;
output [`BITS-1:0] out_2;
output [`BITS-1:0] out_3;
output [`BITS-1:0] out_4;
wire [`BITS-1:0] le5;
wire [`BITS-1:0] le6;
wire [`BITS-1:0] le7;
wire [`BITS-1:0] le8;
wire [`BITS-1:0] le9;
wire [`BITS-1:0] le10;
wire [`BITS-1:0] le11;
wire [`BITS-1:0] le12;
wire [`BITS-1:0] le13;
wire [`BITS-1:0] le14;
wire [`BITS-1:0] le15;
wire [`BITS-1:0] le16;
wire [`BITS-1:0] le17;
wire [`BITS-1:0] le18;
wire [`BITS-1:0] le19;
wire [`BITS-1:0] le20;
wire [`BITS-1:0] le21;
wire [`BITS-1:0] le22;
wire [`BITS-1:0] le23;
wire [`BITS-1:0] le24;
wire [`BITS-1:0] le25;
wire [`BITS-1:0] le26;
wire [`BITS-1:0] le27;
wire [`BITS-1:0] le28;
wire [`BITS-1:0] le29;
wire [`BITS-1:0] le30;
wire [`BITS-1:0] le31;
wire [`BITS-1:0] le32;
wire [`BITS-1:0] le33;
wire [`BITS-1:0] le34;
wire [`BITS-1:0] le35;
wire [`BITS-1:0] le36;
wire [`BITS-1:0] le37;
wire [`BITS-1:0] le38;
wire [`BITS-1:0] le39;
wire [`BITS-1:0] le40;
wire [`BITS-1:0] le41;
wire [`BITS-1:0] le42;
wire [`BITS-1:0] le43;
wire [`BITS-1:0] le44;
wire [`BITS-1:0] le45;
wire [`BITS-1:0] le46;
wire [`BITS-1:0] le47;
wire [`BITS-1:0] le48;
wire [`BITS-1:0] le49;
wire [`BITS-1:0] le50;
wire [`BITS-1:0] le51;
wire [`BITS-1:0] le52;
wire [`BITS-1:0] le53;
wire [`BITS-1:0] le54;
//wire [`BITS-1:0] out_1;
//wire [`BITS-1:0] out_2;
//wire [`BITS-1:0] out_3;
//wire [`BITS-1:0] out_4;
// ASSIGN STATEMENTS
//assign le5 = in1 + in2;
wire [7:0] le5_control;
fpu_add le5_add
(
.clk(clock),
.opa(in1),
.opb(in2),
.out(le5),
.control(le5_control)
);
//assign le6 = in3 * in4;
wire [7:0] le6_control;
fpu_mul le6_mul
(
.clk(clock),
.opa(in3),
.opb(in4),
.out(le6),
.control(le6_control)
);
//assign le7 = in3 + in1;
wire [7:0] le7_control;
fpu_add le7_add
(
.clk(clock),
.opa(in3),
.opb(in1),
.out(le7),
.control(le7_control)
);
//assign le8 = in5 * in4;
wire [7:0] le8_control;
fpu_mul le8_mul
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(le8),
.control(le8_control)
);
//assign le9 = le5 + le6;
wire [7:0] le9_control;
fpu_add le9_add
(
.clk(clock),
.opa(le5),
.opb(le6),
.out(le9),
.control(le9_control)
);
//assign le10 = le7 * le8;
wire [7:0] le10_control;
fpu_mul le10_mul
(
.clk(clock),
.opa(le7),
.opb(le8),
.out(le10),
.control(le10_control)
);
//assign le11 = le9 + le10;
wire [7:0] le11_control;
fpu_add le11_add
(
.clk(clock),
.opa(le9),
.opb(le10),
.out(le11),
.control(le11_control)
);
//assign le12 = le9 * le10;
wire [7:0] le12_control;
fpu_mul le12_mul
(
.clk(clock),
.opa(le9),
.opb(le10),
.out(le12),
.control(le12_control)
);
//assign le13 = le5 + le6;
wire [7:0] le13_control;
fpu_add le13_add
(
.clk(clock),
.opa(le5),
.opb(le6),
.out(le13),
.control(le13_control)
);
//assign le14 = le7 * le8;
wire [7:0] le14_control;
fpu_mul le14_mul
(
.clk(clock),
.opa(le7),
.opb(le8),
.out(le14),
.control(le14_control)
);
//assign le15 = le13 + le14;
wire [7:0] le15_control;
fpu_add le15_add
(
.clk(clock),
.opa(le13),
.opb(le14),
.out(le15),
.control(le15_control)
);
//assign le16 = le9 * le13;
wire [7:0] le16_control;
fpu_mul le16_mul
(
.clk(clock),
.opa(le9),
.opb(le13),
.out(le16),
.control(le16_control)
);
//assign le17 = le13 + le14;
wire [7:0] le17_control;
fpu_add le17_add
(
.clk(clock),
.opa(le13),
.opb(le14),
.out(le17),
.control(le17_control)
);
//assign le18 = le10 * le14;
wire [7:0] le18_control;
fpu_mul le18_mul
(
.clk(clock),
.opa(le10),
.opb(le14),
.out(le18),
.control(le18_control)
);
//assign le19 = le15 + le17;
wire [7:0] le19_control;
fpu_add le19_add
(
.clk(clock),
.opa(le15),
.opb(le17),
.out(le19),
.control(le19_control)
);
//assign le20 = le15 * le18;
wire [7:0] le20_control;
fpu_mul le20_mul
(
.clk(clock),
.opa(le20),
.opb(le15),
.out(le20),
.control(le20_control)
);
//assign le21 = le12 + le18;
wire [7:0] le21_control;
fpu_add le21_add
(
.clk(clock),
.opa(le12),
.opb(le18),
.out(le21),
.control(le21_control)
);
//assign le22 = le19 * le20;
wire [7:0] le22_control;
fpu_mul le22_mul
(
.clk(clock),
.opa(le19),
.opb(le20),
.out(le22),
.control(le22_control)
);
//assign le23 = le20 + le21;
wire [7:0] le23_control;
fpu_add le23_add
(
.clk(clock),
.opa(le20),
.opb(le21),
.out(le23),
.control(le23_control)
);
//assign le24 = le19 * le21;
wire [7:0] le24_control;
fpu_mul le24_mul
(
.clk(clock),
.opa(le19),
.opb(le21),
.out(le24),
.control(le24_control)
);
//assign le25 = le22 + le23;
wire [7:0] le25_control;
fpu_add le25_add
(
.clk(clock),
.opa(le22),
.opb(le23),
.out(le25),
.control(le25_control)
);
//assign le26 = le51 * le52;
wire [7:0] le26_control;
fpu_mul le26_mul
(
.clk(clock),
.opa(le51),
.opb(le52),
.out(le26),
.control(le26_control)
);
//assign le27 = le52 + le54;
wire [7:0] le27_control;
fpu_add le27_add
(
.clk(clock),
.opa(le52),
.opb(le54),
.out(le27),
.control(le27_control)
);
//assign le28 = le53 * le54;
wire [7:0] le28_control;
fpu_mul le28_mul
(
.clk(clock),
.opa(le53),
.opb(le54),
.out(le28),
.control(le28_control)
);
//assign le29 = le26 + le27;
wire [7:0] le29_control;
fpu_add le29_add
(
.clk(clock),
.opa(le26),
.opb(le27),
.out(le29),
.control(le29_control)
);
//assign le30 = le26 * le28;
wire [7:0] le30_control;
fpu_mul le30_mul
(
.clk(clock),
.opa(le26),
.opb(le28),
.out(le30),
.control(le30_control)
);
//assign le31 = le27 + le28;
wire [7:0] le31_control;
fpu_add le31_add
(
.clk(clock),
.opa(le27),
.opb(le28),
.out(le31),
.control(le31_control)
);
//assign le32 = le26 * le28;
wire [7:0] le32_control;
fpu_mul le32_mul
(
.clk(clock),
.opa(le26),
.opb(le28),
.out(le32),
.control(le32_control)
);
//assign le33 = le27 + le28;
wire [7:0] le33_control;
fpu_add le33_add
(
.clk(clock),
.opa(le27),
.opb(le28),
.out(le33),
.control(le33_control)
);
//assign le34 = le30 * le32;
wire [7:0] le34_control;
fpu_mul le34_mul
(
.clk(clock),
.opa(le30),
.opb(le32),
.out(le34),
.control(le34_control)
);
//assign le35 = le29 + le31;
wire [7:0] le35_control;
fpu_add le35_add
(
.clk(clock),
.opa(le29),
.opb(le31),
.out(le35),
.control(le35_control)
);
//assign le36 = le31 * le33;
wire [7:0] le36_control;
fpu_mul le36_mul
(
.clk(clock),
.opa(le31),
.opb(le33),
.out(le36),
.control(le36_control)
);
//assign le37 = le32 + le33;
wire [7:0] le37_control;
fpu_add le37_add
(
.clk(clock),
.opa(le32),
.opb(le33),
.out(le37),
.control(le37_control)
);
//assign le38 = le34 * le35;
wire [7:0] le38_control;
fpu_mul le38_mul
(
.clk(clock),
.opa(le34),
.opb(le35),
.out(le38),
.control(le38_control)
);
//assign le39 = le34 + le37;
wire [7:0] le39_control;
fpu_add le39_add
(
.clk(clock),
.opa(le34),
.opb(le37),
.out(le39),
.control(le39_control)
);
//assign le40 = le35 * le36;
wire [7:0] le40_control;
fpu_mul le40_mul
(
.clk(clock),
.opa(le35),
.opb(le36),
.out(le40),
.control(le40_control)
);
//assign le41 = le36 + le37;
wire [7:0] le41_control;
fpu_add le41_add
(
.clk(clock),
.opa(le36),
.opb(le37),
.out(le41),
.control(le41_control)
);
//assign le42 = le11 * le16;
wire [7:0] le42_control;
fpu_mul le42_mul
(
.clk(clock),
.opa(le11),
.opb(le16),
.out(le42),
.control(le42_control)
);
//assign le43 = le19 + le42;
wire [7:0] le43_control;
fpu_add le43_add
(
.clk(clock),
.opa(le19),
.opb(le42),
.out(le43),
.control(le43_control)
);
//assign le44 = le21 * le42;
wire [7:0] le44_control;
fpu_mul le44_mul
(
.clk(clock),
.opa(le21),
.opb(le42),
.out(le44),
.control(le44_control)
);
//assign le45 = le22 + le43;
wire [7:0] le45_control;
fpu_add le45_add
(
.clk(clock),
.opa(le22),
.opb(le43),
.out(le45),
.control(le45_control)
);
//assign le46 = le24 * le43;
wire [7:0] le46_control;
fpu_mul le46_mul
(
.clk(clock),
.opa(le24),
.opb(le43),
.out(le46),
.control(le46_control)
);
//assign le47 = le24 + le44;
wire [7:0] le47_control;
fpu_add le47_add
(
.clk(clock),
.opa(le24),
.opb(le44),
.out(le47),
.control(le47_control)
);
//assign le48 = le45 * le46;
wire [7:0] le48_control;
fpu_mul le48_mul
(
.clk(clock),
.opa(le45),
.opb(le46),
.out(le48),
.control(le48_control)
);
//assign le49 = le45 + le47;
wire [7:0] le49_control;
fpu_add le49_add
(
.clk(clock),
.opa(le45),
.opb(le47),
.out(le49),
.control(le49_control)
);
//assign le50 = le25 * le45;
wire [7:0] le50_control;
fpu_mul le50_mul
(
.clk(clock),
.opa(le25),
.opb(le45),
.out(le50),
.control(le50_control)
);
//assign le51 = le48 + le50;
wire [7:0] le51_control;
fpu_add le51_add
(
.clk(clock),
.opa(le48),
.opb(le50),
.out(le51),
.control(le51_control)
);
//assign le52 = le49 * le50;
wire [7:0] le52_control;
fpu_mul le52_mul
(
.clk(clock),
.opa(le49),
.opb(le50),
.out(le52),
.control(le52_control)
);
//assign le53 = le48 + le50;
wire [7:0] le53_control;
fpu_add le53_add
(
.clk(clock),
.opa(le48),
.opb(le50),
.out(le53),
.control(le53_control)
);
//assign le54 = le49 * le50;
wire [7:0] le54_control;
fpu_mul le54_mul
(
.clk(clock),
.opa(le49),
.opb(le50),
.out(le54),
.control(le54_control)
);
assign out_1 = le38;
assign out_2 = le39;
assign out_3 = le40;
assign out_4 = le41;
always @(posedge clock)
begin
in1 <= in1_reg;
in2 <= in2_reg;
in3 <= in3_reg;
in4 <= in4_reg;
in5 <= in5_reg;
end
endmodule |
module syn2(clock,
reset,
in1,
in2,
in3,
in4,
in5,
out_1,
out_2,
out_3,
out_4
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] in1;
input [`BITS-1:0] in2;
input [`BITS-1:0] in3;
input [`BITS-1:0] in4;
input [`BITS-1:0] in5;
output [`BITS-1:0] out_1;
output [`BITS-1:0] out_2;
output [`BITS-1:0] out_3;
output [`BITS-1:0] out_4;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] x4;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] add2;
wire [`BITS-1:0] add3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
reg [`BITS-1:0] reg1;
reg [`BITS-1:0] reg2;
reg [`BITS-1:0] reg3;
reg [`BITS-1:0] reg4;
reg [`BITS-1:0] reg5;
reg [`BITS-1:0] reg6;
wire [`BITS-1:0] out_1;
wire [`BITS-1:0] out_2;
wire [`BITS-1:0] out_3;
wire [`BITS-1:0] out_4;
// ASSIGN STATEMENTS
//assign add1 = reg1 + in4;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(reg6),
.opb(in4),
.out(add1),
.control(add1_control)
);
//assign x1 = x3 * in1;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(x3),
.opb(in1),
.out(x1),
.control(x1_control)
);
//assign add2 = add5 + add1;
wire [7:0] add2_control;
fpu_add add2_add
(
.clk(clock),
.opa(add5),
.opb(add1),
.out(add2),
.control(add2_control)
);
//assign x2 = x1 * add2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(x1),
.opb(add2),
.out(x2),
.control(x2_control)
);
//assign add3 = in1 + reg1;
wire [7:0] add3_control;
fpu_add add3_add
(
.clk(clock),
.opa(in1),
.opb(reg6),
.out(add3),
.control(add3_control)
);
//assign x3 = in3 * in1;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(in3),
.opb(in1),
.out(x3),
.control(x3_control)
);
//assign add4 = in5 + in3;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(in5),
.opb(in3),
.out(add4),
.control(add4_control)
);
//assign x4 = in5 * in4;
wire [7:0] x4_control;
fpu_mul x4_mul
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(x4),
.control(x4_control)
);
//assign add5 = in5 + in4;
wire [7:0] add5_control;
fpu_add add5_add
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(add5),
.control(add5_control)
);
assign out_1 = x2;
assign out_2 = add3;
assign out_3 = add4;
assign out_4 = x4;
always @(posedge clock)
begin
reg1 <= in2;
reg2 <= reg1;
reg3 <= reg2;
reg4 <= reg3;
reg5 <= reg4;
reg6 <= reg5;
end
endmodule |
module mm3(clock,
reset,
a1,
a2,
a3,
b1,
b2,
b3,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] a1;
input [`BITS-1:0] a2;
input [`BITS-1:0] a3;
input [`BITS-1:0] b1;
input [`BITS-1:0] b2;
input [`BITS-1:0] b3;
output [`BITS-1:0] out;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
reg [`BITS-1:0] x3_reg1;
reg [`BITS-1:0] x3_reg2;
reg [`BITS-1:0] x3_reg3;
reg [`BITS-1:0] x3_reg4;
reg [`BITS-1:0] x3_reg5;
reg [`BITS-1:0] x3_reg6;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
//assign x1 = a1 * b1;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(a1),
.opb(b1),
.out(x1),
.control(x1_control)
);
//assign x2 = a2 * b2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(a2),
.opb(b2),
.out(x2),
.control(x2_control)
);
//assign x3 = a3 * b3;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(a3),
.opb(b3),
.out(x3),
.control(x3_control)
);
//assign add4 = x1 + x2;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(x1),
.opb(x2),
.out(add4),
.control(add4_control)
);
//assign out = add4 + x3_reg5;
wire [7:0] out_control;
fpu_add out_add
(
.clk(clock),
.opa(add4),
.opb(x3_reg6),
.out(out),
.control(out_control)
);
always @(posedge clock)
begin
x3_reg1 <= x3;
x3_reg2 <= x3_reg1;
x3_reg3 <= x3_reg2;
x3_reg4 <= x3_reg3;
x3_reg5 <= x3_reg4;
x3_reg6 <= x3_reg5;
end
endmodule |
module dscg(clock,
reset,
cos,
one,
s1,
s2,
s1_out,
s2_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] cos;
input [`BITS-1:0] one;
input [`BITS-1:0] s1;
input [`BITS-1:0] s2;
output [`BITS-1:0] s1_out;
output [`BITS-1:0] s2_out;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] sub5;
wire [`BITS-1:0] x6;
wire [`BITS-1:0] x7;
wire [`BITS-1:0] s1_out;
wire [`BITS-1:0] s2_out;
reg [`BITS-1:0] x3_reg1;
reg [`BITS-1:0] x3_reg2;
reg [`BITS-1:0] x3_reg3;
reg [`BITS-1:0] x3_reg4;
reg [`BITS-1:0] x3_reg5;
reg [`BITS-1:0] x3_reg6;
reg [`BITS-1:0] x7_reg1;
reg [`BITS-1:0] x7_reg2;
reg [`BITS-1:0] x7_reg3;
reg [`BITS-1:0] x7_reg4;
reg [`BITS-1:0] x7_reg5;
reg [`BITS-1:0] x7_reg6;
//assign add1 = cos + one;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(cos),
.opb(one),
.out(add1),
.control(add1_control)
);
//assign x2 = add1 * s2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(add1),
.opb(s2),
.out(x2),
.control(x2_control)
);
//assign x3 = cos * s1;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(cos),
.opb(s1),
.out(x3),
.control(x3_control)
);
//assign s1_out = x2 + x3_reg1;
wire [7:0] s1_out_control;
fpu_add s1_out_add
(
.clk(clock),
.opa(x2),
.opb(x3_reg6),
.out(s1_out),
.control(s1_out_control)
);
//assign sub5 = one - cos;
wire [7:0] sub5_control;
fpu_add sub5_add
(
.clk(clock),
.opa(one),
.opb(cos),
.out(sub5),
.control(sub5_control)
);
//assign x6 = sub5 * s1;
wire [7:0] x6_control;
fpu_mul x6_mul
(
.clk(clock),
.opa(sub5),
.opb(s1),
.out(x6),
.control(x6_control)
);
//assign x7 = cos * s2;
wire [7:0] x7_control;
fpu_mul x7_mul
(
.clk(clock),
.opa(cos),
.opb(s2),
.out(x7),
.control(x7_control)
);
//assign s2_out = x6 + x7_reg1;
wire [7:0] s2_out_control;
fpu_add s2_out_add
(
.clk(clock),
.opa(x6),
.opb(x7_reg6),
.out(s2_out),
.control(s2_out_control)
);
always @(posedge clock)
begin
x3_reg1 <= x3;
x3_reg2 <= x3_reg1;
x3_reg3 <= x3_reg2;
x3_reg4 <= x3_reg3;
x3_reg5 <= x3_reg4;
x3_reg6 <= x3_reg5;
x7_reg1 <= x7;
x7_reg2 <= x7_reg1;
x7_reg3 <= x7_reg2;
x7_reg4 <= x7_reg3;
x7_reg5 <= x7_reg4;
x7_reg6 <= x7_reg5;
end
endmodule |
module ode(clock,
reset,
select,
h,
half,
y_pi_in,
t_pi_in,
y_pi_out,
t_pi_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input select;
input [`BITS-1:0] h;
input [`BITS-1:0] half;
input [`BITS-1:0] y_pi_in;
input [`BITS-1:0] t_pi_in;
output [`BITS-1:0] y_pi_out;
output [`BITS-1:0] t_pi_out;
output [7:0] x1_control;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] sub2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
wire [`BITS-1:0] y_pi;
wire [`BITS-1:0] t_pi;
reg [`BITS-1:0] t_reg1;
reg [`BITS-1:0] t_reg2;
reg [`BITS-1:0] t_reg3;
reg [`BITS-1:0] t_reg4;
reg [`BITS-1:0] t_reg5;
reg [`BITS-1:0] t_reg6;
reg [`BITS-1:0] t_reg7;
reg [`BITS-1:0] t_reg8;
reg [`BITS-1:0] t_reg9;
reg [`BITS-1:0] t_reg10;
reg [`BITS-1:0] t_reg11;
reg [`BITS-1:0] t_reg12;
reg [`BITS-1:0] y_pi_reg1;
reg [`BITS-1:0] y_pi_reg2;
reg [`BITS-1:0] y_pi_reg3;
reg [`BITS-1:0] y_pi_reg4;
reg [`BITS-1:0] y_pi_reg5;
reg [`BITS-1:0] y_pi_reg6;
reg [`BITS-1:0] y_pi_reg7;
reg [`BITS-1:0] y_pi_reg8;
reg [`BITS-1:0] y_pi_reg9;
reg [`BITS-1:0] y_pi_reg10;
reg [`BITS-1:0] y_pi_reg11;
reg [`BITS-1:0] y_pi_reg12;
wire [`BITS-1:0] y_pi_out;
reg [`BITS-1:0] y_pi_out_reg;
wire [`BITS-1:0] t_pi_out;
// ASSIGN STATEMENTS
assign y_pi = select ? y_pi_in : add4;
assign t_pi = select ? t_pi_in : t_reg1;
//assign x1 = h * half;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(h),
.opb(half),
.out(x1),
.control(x1_control)
);
//assign sub2 = t_pi - y_pi;
wire [7:0] sub2_control;
fpu_add sub2_add
(
.clk(clock),
.opa(t_pi),
.opb(y_pi),
.out(sub2),
.control(sub2_control)
);
//assign x3 = x1 * sub2;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(x1),
.opb(sub2),
.out(x3),
.control(x3_control)
);
//assign add4 = y_pi_reg1 + x3;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(y_pi_reg12),
.opb(x3),
.out(add4),
.control(add4_control)
);
//assign add5 = h + t_pi;
wire [7:0] add5_control;
fpu_add add5_add
(
.clk(clock),
.opa(h),
.opb(t_pi),
.out(add5),
.control(add5_control)
);
//assign y_pi_out = add4;
assign y_pi_out = y_pi_out_reg;
assign t_pi_out = t_reg12;
always @(posedge clock)
begin
y_pi_out_reg <= add4;
t_reg1 <= add5;
t_reg2 <= t_reg1;
t_reg3 <= t_reg2;
t_reg4 <= t_reg3;
t_reg5 <= t_reg4;
t_reg6 <= t_reg5;
t_reg7 <= t_reg6;
t_reg8 <= t_reg7;
t_reg9 <= t_reg8;
t_reg10 <= t_reg9;
t_reg11 <= t_reg10;
t_reg12 <= t_reg11;
y_pi_reg1 <= y_pi;
y_pi_reg2 <= y_pi_reg1;
y_pi_reg3 <= y_pi_reg2;
y_pi_reg4 <= y_pi_reg3;
y_pi_reg5 <= y_pi_reg4;
y_pi_reg6 <= y_pi_reg5;
y_pi_reg7 <= y_pi_reg6;
y_pi_reg8 <= y_pi_reg7;
y_pi_reg9 <= y_pi_reg8;
y_pi_reg10 <= y_pi_reg9;
y_pi_reg11 <= y_pi_reg10;
y_pi_reg12 <= y_pi_reg11;
end
endmodule |
module fir(clock,
reset,
x,
k0,
k1,
k2,
k3,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] x;
input [`BITS-1:0] k0;
input [`BITS-1:0] k1;
input [`BITS-1:0] k2;
input [`BITS-1:0] k3;
output [`BITS-1:0] out;
wire [`BITS-1:0] x0k0;
wire [`BITS-1:0] x1k1;
wire [`BITS-1:0] x2k2;
wire [`BITS-1:0] x3k3;
wire [`BITS-1:0] add0;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] add2;
wire [`BITS-1:0] add3;
reg [`BITS-1:0] x_reg1;
reg [`BITS-1:0] x_reg2;
reg [`BITS-1:0] x_reg3;
reg [`BITS-1:0] x_reg4;
reg [`BITS-1:0] x_reg5;
reg [`BITS-1:0] x_reg6;
reg [`BITS-1:0] x_reg7;
reg [`BITS-1:0] x_reg8;
reg [`BITS-1:0] x_reg9;
reg [`BITS-1:0] x_reg10;
reg [`BITS-1:0] x_reg11;
reg [`BITS-1:0] x_reg12;
reg [`BITS-1:0] x_reg13;
reg [`BITS-1:0] x_reg14;
reg [`BITS-1:0] x_reg15;
reg [`BITS-1:0] x_reg16;
reg [`BITS-1:0] x_reg17;
reg [`BITS-1:0] x_reg18;
wire [`BITS-1:0] out;
wire [`BITS-1:0] out_temp;
reg [`BITS-1:0] out_reg;
assign out= out_reg;
// ASSIGN STATEMENTS
//assign x0k0 = k0 * x;
wire [7:0] x0k0_control;
fpu_mul x0k0_mul
(
.clk(clock),
.opa(k0),
.opb(x),
.out(x0k0),
.control(x0k0_control)
);
//assign x1k1 = k1 * x_reg1;
wire [7:0] x1k1_control;
fpu_mul x1k1_mul
(
.clk(clock),
.opa(k1),
.opb(x_reg6),
.out(x1k1),
.control(x1k1_control)
);
//assign x2k2 = k2 * x_reg2;
wire [7:0] x2k2_control;
fpu_mul x2k2_mul
(
.clk(clock),
.opa(k2),
.opb(x_reg12),
.out(x2k2),
.control(x2k2_control)
);
//assign x3k3 = k3 * x_reg3;
wire [7:0] x3k3_control;
fpu_mul x3k3_mul
(
.clk(clock),
.opa(k3),
.opb(x_reg18),
.out(x3k3),
.control(x3k3_control)
);
//assign add0 = x0k0 + x1k1;
wire [7:0] add0_control;
fpu_add add0_add
(
.clk(clock),
.opa(x0k0),
.opb(x1k1),
.out(add0),
.control(add0_control)
);
//assign add1 = add0 + x2k2;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(add0),
.opb(x2k2),
.out(add1),
.control(add1_control)
);
//assign out = add1 + x3k3;
wire [7:0] out_temp_control;
fpu_add out_temp_add
(
.clk(clock),
.opa(add1),
.opb(x3k3),
.out(out_temp),
.control(out_temp_control)
);
always @(posedge clock)
begin
out_reg <= out_temp;
x_reg1 <= x;
x_reg2 <= x_reg1;
x_reg3 <= x_reg2;
x_reg4 <= x_reg3;
x_reg5 <= x_reg4;
x_reg6 <= x_reg5;
x_reg7 <= x_reg6;
x_reg8 <= x_reg7;
x_reg9 <= x_reg8;
x_reg10 <= x_reg9;
x_reg11 <= x_reg10;
x_reg12 <= x_reg11;
x_reg13 <= x_reg12;
x_reg14 <= x_reg13;
x_reg15 <= x_reg14;
x_reg16 <= x_reg15;
x_reg17 <= x_reg16;
x_reg18 <= x_reg17;
end
endmodule |
module multi_consumer_tb();
reg clock, rst;
reg [15:0] d_in;
wire [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 16'b0;
#30
d_in = 16'hffff;
#20
d_in = 16'h00ff;
#20
d_in = 16'h0000;
#40
$display($time, " << Simulation Complete >>");
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out_1 = %h, d_out_2 = %h d_out_4 = %h d_out_7 = %h",
clock, rst, d_in, d_out_1, d_out_2, d_out_4, d_out_7);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// multi_consumer DUT
multi_consumer dut ( .d_in(d_in),
.d_out_1(d_out_1),
.d_out_2(d_out_2),
.d_out_4(d_out_4),
.d_out_7(d_out_7),
.clock(clock),
.rst(rst)
);
endmodule |
module simple_comp_tb();
reg clock, rst;
reg [15:0] a_in, b_in, c_in;
wire [15:0] d_out;
wire rdy;
initial
begin
$display($time, " << Starting the Simulation >>");
a_in = 16'h0;
b_in = 16'h0;
c_in = 16'b0;
wait ( rdy == 1'b1 )
begin
a_in = 16'h0;
b_in = 16'h0;
c_in = 16'h0;
end
#30
a_in = 16'hfff;
b_in = 16'hfff;
c_in = 16'hfff;
#20
a_in = 16'h0;
b_in = 16'h0;
#20
a_in = 16'h666;
b_in = 16'h666;
c_in = 16'h666;
#100
$display($time, " << Simulation Complete >>");
$finish;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, a_in = %h, b_in = %h, c_in = %h, d_out = %h",
clock, rst, a_in, b_in, c_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// simple_comp DUT
simple_comp dut ( .a_in(a_in),
.b_in(b_in),
.c_in(c_in),
.d_out(d_out),
.clock(clock),
.rst(rst),
.rdy(rdy)
);
endmodule |
module dcounter_tb();
reg clock, rst;
reg d_en;
wire [15:0] d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
#50
rst = 1'b0;
d_en = 1'b1;
#1311220
$display($time, " << Simulation Complete >>");
$stop;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h",
clock, rst, d_en, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#40 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// dcounter DUT
dcounter dut ( .d_out(d_out),
.d_en(d_en),
.clock(clock),
.rst(rst)
);
endmodule |
module ff_en_tb();
reg clock, rst;
reg [9:0] d_in;
reg d_en;
wire [9:0] d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 10'b0;
d_en = 1'b0;
#30
d_in = 10'h3ff;
d_en = 1'b1;
#20
d_in = 10'h0;
d_en = 1'b0;
#20
d_in = 10'h155;
d_en = 1'b1;
#20
d_in = 10'h288;
d_en = 1'b0;
#20
d_in = 10'h288;
d_en = 1'b1;
#20
d_in = 10'h0;
d_en = 1'b1;
#40
$display($time, " << Simulation Complete >>");
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %h, d_en = %b, d_out = %h",
clock, rst, d_in, d_en, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// ff_en DUT
ff_en dut ( .d_in(d_in),
.d_out(d_out),
.d_en(d_en),
.clock(clock),
.rst(rst)
);
endmodule |
module wide_inv_tb();
reg clock, rst;
reg [31:0] d_in;
wire [31:0] d_out;
wire rdy;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 32'b0;
wait( rdy == 1'b1 )
begin
d_in = 32'b0;
end
#20
d_in = 32'hffffffff;
#20
d_in = 32'hffff0000;
#20
d_in = 32'h0000ffff;
#20
d_in = 32'h55555555;
#20
d_in = 32'haaaaaaaa;
#20
d_in = 32'h11111111;
#20
d_in = 32'h22222222;
#20
d_in = 32'h44444444;
#20
d_in = 32'h88888888;
#20
d_in = 32'h00000000;
#20
$display($time, " << Simulation Complete >>");
$finish;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out = %h",
clock, rst, d_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// wide_inv DUT
wide_inv dut ( .d_in(d_in),
.d_out(d_out),
.clock(clock),
.rst(rst),
.rdy(rdy)
);
endmodule |
module counter_tb();
reg clock, rst;
reg d_en;
wire [11:0] d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
#50
rst = 1'b0;
d_en = 1'b1;
#164000
$display($time, " << Simulation Complete >>");
$stop;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h",
clock, rst, d_en, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#40 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// counter DUT
counter dut ( .d_out(d_out),
.d_en(d_en),
.clock(clock),
.rst(rst)
);
endmodule |
module counter_tb();
reg clock, rst;
reg d_en;
wire rdy;
wire [11:0] d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_en = 1'b0;
wait (rdy == 1'b1)
begin
d_en = 1'b0;
end
#10
d_en = 1'b1;
#164000
$display($time, " << Simulation Complete >>");
$finish;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_en = %b, d_out = %h",
clock, rst, d_en, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#40 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// counter DUT
counter dut ( .d_out(d_out),
.d_en(d_en),
.clock(clock),
.rst(rst),
.rdy(rdy)
);
endmodule |
module wide_inv_reg_tb();
reg clock, rst;
reg [31:0] d_in;
wire [31:0] d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 32'b0;
#30
d_in = 32'b0;
#20
d_in = 32'hffffffff;
#20
d_in = 32'hffff0000;
#20
d_in = 32'h0000ffff;
#20
d_in = 32'h55555555;
#20
d_in = 32'haaaaaaaa;
#20
d_in = 32'h11111111;
#20
d_in = 32'h22222222;
#20
d_in = 32'h44444444;
#20
d_in = 32'h88888888;
#20
d_in = 32'h00000000;
#20
$display($time, " << Simulation Complete >>");
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out = %h",
clock, rst, d_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// wide_inv_reg DUT
wide_inv_reg dut ( .d_in(d_in),
.d_out(d_out),
.clock(clock),
.rst(rst)
);
endmodule |
module single_inv_tb();
reg clock, rst;
reg d_in;
wire d_out;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
#30
d_in = 1'b0;
#20
d_in = 1'b1;
#20
d_in = 1'b0;
#20
$display($time, " << Simulation Complete >>");
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %b, d_out = %b",
clock, rst, d_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// single_inv DUT
single_inv dut ( .d_in(d_in),
.d_out(d_out),
.clock(clock),
.rst(rst)
);
endmodule |
module single_inv_tb();
reg clock, rst;
reg d_in;
wire d_out;
wire rdy;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
wait ( rdy == 1'b1 )
begin
d_in = 1'b0;
end
#20
d_in = 1'b1;
#20
d_in = 1'b0;
#20
$display($time, " << Simulation Complete >>");
$finish;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %b, d_out = %b",
clock, rst, d_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// single_inv DUT
single_inv dut ( .d_in(d_in),
.d_out(d_out),
.clock(clock),
.rst(rst),
.rdy(rdy)
);
endmodule |
module single_inv_reg_tb();
reg clock, rst;
reg d_in;
wire d_out;
wire rdy;
initial
begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
wait ( rdy == 1'b1 )
begin
d_in = 1'b0;
end
#30
d_in = 1'b1;
#20
d_in = 1'b0;
#40
$display($time, " << Simulation Complete >>");
$finish;
end
initial
begin
$monitor($time, ", clock = %b, rst = %b, d_in = %b, d_out = %b",
clock, rst, d_in, d_out);
end
initial
begin
clock = 1'b1;
rst = 1'b1;
#20 rst = 1'b0;
end
always
begin
#10 clock = ~clock;
end
// single_inv_reg DUT
single_inv_reg dut ( .d_in(d_in),
.d_out(d_out),
.clock(clock),
.rst(rst),
.rdy(rdy)
);
endmodule |
module fir_scu_rtl_restructured_for_cmm_exp (clk, reset, sample, result);
input clk, reset;
input [7:0] sample;
output [9:0] result;
reg [9:0] result;
reg [7:0] samp_latch;
reg [16:0] pro;
reg [18:0] acc;
reg [19:0] clk_cnt;
reg [7:0] shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8,shift_9,shift_10,shift_11,shift_12,shift_13,shift_14,shift_15,shift_16;
reg [8:0]coefs_0,coefs_1,coefs_2,coefs_3,coefs_4,coefs_5,coefs_6,coefs_7,coefs_8, coefs_9,coefs_10,coefs_11,coefs_12,coefs_13,coefs_14,coefs_15,coefs_16;
/*parameter coefs_0=9'b111111001,coefs_1=9'b111111011,coefs_2=9'b000001101,
coefs_3=9'b000010000,coefs_4=9'b111101101,coefs_5=9'b111010110,
coefs_6=9'b000010111,coefs_7=9'b010011010,coefs_8=9'b011011110,
coefs_9=9'b010011010,coefs_10=9'b000010111,coefs_11=9'b111010110,
coefs_12=9'b111101101,coefs_13=9'b000010000,coefs_14=9'b000001101,
coefs_15=9'b111111011,coefs_16=9'b111111001; */
/*****************FUNCTION TO DO TWO'S COMPLEMENT MULTIPLICATION***************/
/*function [16:0] mul_tc;
input [7:0] A;
input [8:0] B;
reg sgn;
begin
sgn = A[7] ^ B[8];
if (A[7] == 1'b1) A = ~A + 1'b1;
if (B[8] == 1'b1) B = ~B + 1'b1;
mul_tc = A * B;
if (sgn == 1'b1)
mul_tc = ~mul_tc + 1'b1;
end
endfunction */
/**************************************************************************/
/****************counter to count 18 clock cycles**********************/
always @ (posedge clk)
begin
if(reset)
clk_cnt<={18'b000000000000000000,1'b1};
else
clk_cnt<={clk_cnt[18:0],clk_cnt[19]};
end
/***********************************************************************/
always @ (posedge clk)
begin
coefs_0<=9'b111111001;
coefs_1<=9'b111111011;
coefs_2<=9'b000001101;
coefs_3<=9'b000010000;
coefs_4<=9'b111101101;
coefs_5<=9'b111010110;
coefs_6<=9'b000010111;
coefs_7<=9'b010011010;
coefs_8<=9'b011011110;
coefs_9<=9'b010011010;
coefs_10<=9'b000010111;
coefs_11<=9'b111010110;
coefs_12<=9'b111101101;
coefs_13<=9'b000010000;
coefs_14<=9'b000001101;
coefs_15<=9'b111111011;
coefs_16<=9'b111111001;
end
/****************start of the fir filter operation*********************/
always @(posedge clk)
begin
if (reset) begin
shift_0<=8'h00;
shift_1<=8'h00;
shift_2<=8'h00;
shift_3<=8'h00;
shift_4<=8'h00;
shift_5<=8'h00;
shift_6<=8'h00;
shift_7<=8'h00;
shift_8<=8'h00;
shift_9<=8'h00;
shift_10<=8'h00;
shift_11<=8'h00;
shift_12<=8'h00;
shift_13<=8'h00;
shift_14<=8'h00;
shift_15<=8'h00;
shift_16<=8'h00;
samp_latch<=8'h00;
acc<=18'o000000;
pro<=17'h00000;
end
else begin
if(clk_cnt[0]) begin
samp_latch<= sample;
acc<=18'h00000;
end
else if(clk_cnt[1])
begin
//pro <= 1'b0;
pro<=samp_latch*coefs_0;
acc<=18'h00000;
end
else if (clk_cnt[2])
begin
//pro<= mul_tc(shift_15,coefs_16);
acc<={ pro[16], pro[16], pro };
pro<=shift_15*coefs_16;
shift_16<=shift_15;
end
else if (clk_cnt)
begin
// acc moved out here as common factored calculation
acc<=acc+{ pro[16], pro[16], pro };
if (clk_cnt[3])
begin
//pro<= mul_tc(shift_14,coefs_15);
pro<=shift_14*coefs_15;
shift_15<=shift_14;
end
else if (clk_cnt[4])
begin
//pro<= mul_tc(shift_13,coefs_14);
pro<=shift_13*coefs_14;
shift_14<=shift_13;
end
else if (clk_cnt[5])
begin
//pro<= mul_tc(shift_12,coefs_13);
pro<=shift_12*coefs_13;
shift_13<=shift_12;
end
else if (clk_cnt[6])
begin
//pro<= mul_tc(shift_11,coefs_12);
pro<=shift_11*coefs_12;
shift_12<=shift_11;
end
else if (clk_cnt[7])
begin
//pro<= mul_tc(shift_10,coefs_11);
pro<=shift_10*coefs_11;
shift_11<=shift_10;
end
else if (clk_cnt[8])
begin
//pro<= mul_tc(shift_9,coefs_10);
pro<=shift_9*coefs_10;
shift_10<=shift_9;
end
else if (clk_cnt[9])
begin
//pro<= mul_tc(shift_8,coefs_9);
pro<=shift_8*coefs_9;
shift_9<=shift_8;
end
else if (clk_cnt[10])
begin
//pro<= mul_tc(shift_7,coefs_8);
pro<=shift_7*coefs_8;
shift_8<=shift_7;
end
else if (clk_cnt[11])
begin
//pro<= mul_tc(shift_6,coefs_7);
pro<=shift_6*coefs_7;
shift_7<=shift_6;
end
else if (clk_cnt[12])
begin
//pro<= mul_tc(shift_5,coefs_6);
pro<=shift_5*coefs_6;
shift_6<=shift_5;
end
else if (clk_cnt[13])
begin
//pro<= mul_tc(shift_4,coefs_5);
pro<=shift_4*coefs_5;
shift_5<=shift_4;
end
else if (clk_cnt[14])
begin
//pro<= mul_tc(shift_3,coefs_4);
pro<=shift_3*coefs_4;
shift_4<=shift_3;
end
else if (clk_cnt[15])
begin
//pro<= mul_tc(shift_2,coefs_3);
pro<=shift_2*coefs_3;
shift_3<=shift_2;
end
else if (clk_cnt[16])
begin
//pro<= mul_tc(shift_1,coefs_2);
pro<=shift_1*coefs_2;
shift_2<=shift_1;
end
else if (clk_cnt[17])
begin
//pro<= mul_tc(shift_0,coefs_1);
pro<=shift_0*coefs_1;
shift_1<=shift_0;
shift_0<=samp_latch;
end
/*else if (clk_cnt[18])
begin
acc<=acc+{pro[16],pro[16],pro};
end */
end
else
begin
shift_0<=shift_0;
shift_1<=shift_1;
shift_2<=shift_2;
shift_3<=shift_3;
shift_4<=shift_4;
shift_5<=shift_5;
shift_6<=shift_6;
shift_7<=shift_7;
shift_8<=shift_8;
shift_9<=shift_9;
shift_10<=shift_10;
shift_11<=shift_11;
shift_12<=shift_12;
shift_13<=shift_13;
shift_14<=shift_14;
shift_15<=shift_15;
shift_16<=shift_16;
samp_latch<=samp_latch;
acc<=acc;
pro<=pro;
end
end
end
always @ (posedge clk)
begin
if (reset)
result<=10'h000;
else begin
if(clk_cnt[19])
result<=acc[18:9];
else
result<=result;
end
end
endmodule |
module binops(
in_1, in_2,
or_o,
nor_o,
and_o,
nand_o,
xor_o,
xnor_o,
add_o,
sub_o,
mul_o,
//div_o,
equ_o,
neq_o,
gt_o,
lt_o,
geq_o,
leq_o
);
input [`BITS-1:0] in_1, in_2;
output [`BITS-1:0]
or_o,
nor_o,
and_o,
nand_o,
xor_o,
xnor_o,
add_o,
sub_o,
mul_o,
//div_o,
equ_o,
neq_o,
gt_o,
lt_o,
geq_o,
leq_o;
assign or_o = in_1 | in_2;
assign nor_o = in_1 ~| in_2;
assign and_o = in_1 & in_2;
assign nand_o = in_1 ~& in_2;
assign xor_o = in_1 ^ in_2;
assign xnor_o = in_1 ~^ in_2;
assign add_o = in_1 + in_2;
assign sub_o = in_1 - in_2;
assign mul_o = in_1 * in_2;
//assign div_o = in_1 / in_2;
assign equ_o = in_1 == in_2;
assign neq_o = in_1 != in_2;
assign gt_o = in_1 > in_2;
assign lt_o = in_1 < in_2;
assign geq_o = in_1 >= in_2;
assign leq_o = in_1 <= in_2;
endmodule |
module paj_framebuftop_hierarchy_no_mem (fbdata, fbdatavalid, fbnextscanline, tm3_vidout_red, tm3_vidout_green, tm3_vidout_blue, tm3_vidout_clock, tm3_vidout_hsync, tm3_vidout_vsync, tm3_vidout_blank, oe, globalreset, tm3_clk_v0, tm3_clk_v0_2);
input[63:0] fbdata;
input fbdatavalid;
output fbnextscanline;
wire fbnextscanline;
output[9:0] tm3_vidout_red;
wire[9:0] tm3_vidout_red;
output[9:0] tm3_vidout_green;
wire[9:0] tm3_vidout_green;
output[9:0] tm3_vidout_blue;
wire[9:0] tm3_vidout_blue;
output tm3_vidout_clock;
wire tm3_vidout_clock;
output tm3_vidout_hsync;
wire tm3_vidout_hsync;
output tm3_vidout_vsync;
wire tm3_vidout_vsync;
output tm3_vidout_blank;
wire tm3_vidout_blank;
input oe;
input globalreset;
input tm3_clk_v0;
input tm3_clk_v0_2;
wire[20:0] pixeldataA;
wire[20:0] pixeldataB;
wire[20:0] pixeldataC;
wire startframe;
wire nextscanline;
wire nextpixelA;
wire nextpixelB;
wire nextpixelC;
wire fbnextscanlineint;
assign fbnextscanline = ((fbnextscanlineint == 1'b1) & oe == 1'b1) ? 1'b1 : 1'b0 ;
vidout vidoutinst (pixeldataA, pixeldataB, pixeldataC, nextpixelA, nextpixelB, nextpixelC, startframe, nextscanline, globalreset, tm3_clk_v0, tm3_clk_v0_2, tm3_vidout_red, tm3_vidout_green, tm3_vidout_blue, tm3_vidout_clock, tm3_vidout_hsync, tm3_vidout_vsync, tm3_vidout_blank);
scanlinebuffer scanlinebuf (pixeldataA, pixeldataB, pixeldataC, nextpixelA, nextpixelB, nextpixelC, startframe, nextscanline, fbdata, fbnextscanlineint, fbdatavalid, globalreset, tm3_clk_v0);
endmodule |
module vidout (pixeldataA, pixeldataB, pixeldataC, nextpixelA, nextpixelB, nextpixelC, startframe, nextscanline, globalreset, tm3_clk_v0, tm3_clk_v0_2, tm3_vidout_red, tm3_vidout_green, tm3_vidout_blue, tm3_vidout_clock, tm3_vidout_hsync, tm3_vidout_vsync, tm3_vidout_blank);
input[20:0] pixeldataA;
input[20:0] pixeldataB;
input[20:0] pixeldataC;
output nextpixelA;
reg nextpixelA;
output nextpixelB;
reg nextpixelB;
output nextpixelC;
reg nextpixelC;
output startframe;
reg startframe;
output nextscanline;
reg nextscanline;
input globalreset;
input tm3_clk_v0;
input tm3_clk_v0_2; // PAJ modified for VPR flow so no clock in LUT
output[9:0] tm3_vidout_red;
reg[9:0] tm3_vidout_red;
output[9:0] tm3_vidout_green;
reg[9:0] tm3_vidout_green;
output[9:0] tm3_vidout_blue;
reg[9:0] tm3_vidout_blue;
output tm3_vidout_clock;
wire tm3_vidout_clock;
output tm3_vidout_hsync;
reg tm3_vidout_hsync;
output tm3_vidout_vsync;
reg tm3_vidout_vsync;
output tm3_vidout_blank;
reg tm3_vidout_blank;
reg[9:0] horiz;
reg[9:0] vert;
reg video_state;
reg nothsyncd;
reg[20:0] primarypixel;
reg[20:0] secondarypixel;
reg[20:0] primarybuffer;
reg[20:0] secondarybuffer;
reg primarynext;
reg secondarynext;
reg[1:0] pselect;
always @(posedge tm3_clk_v0)
begin
if ((horiz < 641 & vert < 480) & video_state == 1'b0)
begin
if ((vert[0]) == 1'b0)
begin
secondarynext <= 1'b0 ;
// Horizontaly Interpt Line
if ((horiz[0]) == 1'b0)
begin
primarynext <= 1'b1 ;
end
end
else
begin
// Bilinear Line
if ((horiz[0]) == 1'b0)
begin
primarynext <= 1'b1 ;
secondarynext <= 1'b1 ;
end
end
end
end
always @(posedge tm3_clk_v0)
begin
case (pselect)
2'b00 :
begin
primarypixel <= pixeldataA ;
secondarypixel <= pixeldataB ;
nextpixelA <= primarynext ;
nextpixelB <= secondarynext ;
nextpixelC <= 1'b0 ;
end
2'b01 :
begin
primarypixel <= pixeldataB ;
secondarypixel <= pixeldataC ;
nextpixelA <= 1'b0 ;
nextpixelB <= primarynext ;
nextpixelC <= secondarynext ;
end
2'b10 :
begin
primarypixel <= pixeldataC ;
secondarypixel <= pixeldataA ;
nextpixelB <= 1'b0 ;
nextpixelC <= primarynext ;
nextpixelA <= secondarynext ;
end
default :
begin
primarypixel <= 1;
secondarypixel <= 1;
nextpixelA <= 1'b0 ;
nextpixelB <= 1'b0 ;
nextpixelC <= 1'b0 ;
end
endcase
end
assign tm3_vidout_clock = ~(video_state) ;
always @(posedge tm3_clk_v0)
begin
if (globalreset == 1'b1)
begin
nothsyncd <= 1'b0 ;
vert <= 1;
horiz <= 1;
startframe <= 1'b0 ;
pselect <= 2'b00 ;
video_state <= 1'b0 ;
tm3_vidout_blank <= 1'b0 ;
tm3_vidout_vsync <= 1'b0 ;
tm3_vidout_hsync <= 1'b0 ;
tm3_vidout_green <= 1;
tm3_vidout_red <= 1;
tm3_vidout_blue <= 1;
primarybuffer <= 1;
secondarybuffer <= 1;
nextscanline <= 1'b0 ;
end
else if (tm3_clk_v0_2 == 1'b1) // PAJ modified for VPR flow so no clock in LUT
begin
video_state <= ~(video_state) ;
// Code that handles active scanline
// Code that handle new scanline requests
nothsyncd <= ~tm3_vidout_hsync ;
if (tm3_vidout_hsync == 1'b1 & nothsyncd == 1'b1)
begin
if ((vert < 478) & (vert[0]) == 1'b0)
begin
nextscanline <= 1'b1 ;
startframe <= 1'b0 ;
end
else if ((vert < 480) & (vert[0]) == 1'b1)
begin
nextscanline <= 1'b0 ;
startframe <= 1'b0 ;
case (pselect)
2'b00 :
begin
pselect <= 2'b01 ;
end
2'b01 :
begin
pselect <= 2'b10 ;
end
2'b10 :
begin
pselect <= 2'b00 ;
end
default :
begin
pselect <= 2'b0 ;
end
endcase
end
else if (vert == 525)
begin
nextscanline <= 1'b1 ;
startframe <= 1'b1 ;
pselect <= 2'b00 ;
end
end
if (video_state == 1'b0)
begin
if (horiz == 800)
begin
horiz <= 10'b0000000000;
if (vert == 525)
begin
vert <= 10'b0000000000;
end
else
begin
vert <= vert + 1;
end
end
else
begin
horiz <= horiz + 1;
end
if ((vert >= 491) & (vert <= 493))
begin
tm3_vidout_vsync <= 1;
end
else
begin
tm3_vidout_vsync <= 0;
end
if ((horiz >= 664) & (horiz <= 760))
begin
tm3_vidout_hsync <= 1;
end
else
begin
tm3_vidout_hsync <= 1'b0 ;
end
if ((horiz < 640) & (vert < 480))
begin
tm3_vidout_blank <= 1'b1 ;
end
else
begin
tm3_vidout_blank <= 1'b0 ;
end
if (horiz < 643 & vert < 480)
begin
if ((vert[0]) == 1'b0)
begin
// Horizontaly Interpt Line
if ((horiz[0]) == 1'b0)
begin
primarybuffer <= primarypixel ;
tm3_vidout_red <= {primarypixel[20:14], 3'b000} ;
tm3_vidout_green <= {primarypixel[13:7], 3'b000} ;
tm3_vidout_blue <= {primarypixel[6:0], 3'b000} ;
end
else
begin
primarybuffer <= primarypixel ;
//tm3_vidout_red <= (('0' &primarypixel(20 downto 14))+('0' &primarybuffer(20 downto 14)))(7 downto 1) & "000";
//tm3_vidout_green <= (('0' &primarypixel(13 downto 7))+('0' &primarybuffer(13 downto 7)))(7 downto 1) & "000";
//tm3_vidout_blue <= (('0'&primarypixel(6 downto 0))+('0' &primarybuffer(6 downto 0)))(7 downto 1) & "000";
tm3_vidout_red <= {(({1'b0, primarypixel[20:14]}) + ({1'b0, primarybuffer[20:14]})), 3'b000} ;
tm3_vidout_green <= {(({1'b0, primarypixel[13:7]}) + ({1'b0, primarybuffer[13:7]})), 3'b000} ;
tm3_vidout_blue <= {(({1'b0, primarypixel[6:0]}) + ({1'b0, primarybuffer[6:0]})), 3'b000} ;
end
end
else
begin
// Bilinear Line
if ((horiz[0]) == 1'b0)
begin
primarybuffer <= primarypixel ;
secondarybuffer <= secondarypixel ;
//tm3_vidout_red <= (('0' & primarypixel(20 downto 14))+('0' & secondarypixel(20 downto 14)))(7 downto 1) & "000";
//tm3_vidout_green <= (('0' & primarypixel(13 downto 7))+('0' & secondarypixel(13 downto 7)))(7 downto 1) & "000";
//tm3_vidout_blue <= (('0' & primarypixel(6 downto 0))+('0' & secondarypixel(6 downto 0)))(7 downto 1) & "000";
tm3_vidout_red <= {(({1'b0, primarypixel[20:14]}) + ({1'b0, secondarypixel[20:14]})), 3'b000} ;
tm3_vidout_green <= {(({1'b0, primarypixel[13:7]}) + ({1'b0, secondarypixel[13:7]})), 3'b000} ;
tm3_vidout_blue <= {(({1'b0, primarypixel[6:0]}) + ({1'b0, secondarypixel[6:0]})), 3'b000} ;
end
else
begin
//tm3_vidout_red <= (("00" &primarypixel(20 downto 14))+("00" &secondarypixel(20 downto 14))+
// ("00" &primarybuffer(20 downto 14))+("00" &secondarybuffer(20 downto 14)))(8 downto 2) & "000";
//tm3_vidout_green <= (("00" & primarypixel(13 downto 7))+("00" & secondarypixel(13 downto 7))+
// ("00" & primarybuffer(13 downto 7))+("00" & secondarybuffer(13 downto 7)))(8 downto 2) & "000";
//tm3_vidout_blue <= (("00" & primarypixel(6 downto 0))+("00" & secondarypixel(6 downto 0))+
// ("00" & primarybuffer(6 downto 0))+("00" & secondarybuffer(6 downto 0)))(8 downto 2) & "000";
tm3_vidout_red <= {(({2'b00, primarypixel[20:14]})
+ ({2'b00, secondarypixel[20:14]})
+ ({2'b00, primarybuffer[20:14]})
+ ({2'b00, secondarybuffer[20:14]})), 3'b000} ;
tm3_vidout_green <= {(({2'b00, primarypixel[13:7]})
+ ({2'b00, secondarypixel[13:7]})
+ ({2'b00, primarybuffer[13:7]})
+ ({2'b00, secondarybuffer[13:7]})), 3'b000} ;
tm3_vidout_blue <= {(({2'b00, primarypixel[6:0]})
+ ({2'b00, secondarypixel[6:0]})
+ ({2'b00, primarybuffer[6:0]})
+ ({2'b00, secondarybuffer[6:0]})), 3'b000} ;
end
end
end
else
begin
tm3_vidout_green <= 1;
tm3_vidout_red <= 1;
tm3_vidout_blue <= 1;
end
end
end
end
endmodule |
module scanlinebuffer (pixeldataA, pixeldataB, pixeldataC, nextpixelA, nextpixelB, nextpixelC, startframe, nextscanline, fbdata, fbnextscanline, fbdatavalid, globalreset, clk);
output[20:0] pixeldataA;
wire[20:0] pixeldataA;
output[20:0] pixeldataB;
wire[20:0] pixeldataB;
output[20:0] pixeldataC;
wire[20:0] pixeldataC;
input nextpixelA;
input nextpixelB;
input nextpixelC;
input startframe;
input nextscanline;
input[62:0] fbdata;
output fbnextscanline;
reg fbnextscanline;
input fbdatavalid;
input globalreset;
input clk;
reg[1:0] state;
reg[1:0] next_state;
reg weA;
reg weB;
reg weC;
reg temp_fbnextscanline;
scanline scanlineA (nextpixelA, weA, fbdata[62:0], pixeldataA, globalreset, clk);
scanline scanlineB (nextpixelB, weB, fbdata[62:0], pixeldataB, globalreset, clk);
scanline scanlineC (nextpixelC, weC, fbdata[62:0], pixeldataC, globalreset, clk);
always @(posedge clk)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
fbnextscanline <= 1'b0 ;
end
else
begin
state <= next_state ;
if (fbdatavalid == 1'b1)
begin
fbnextscanline <= 1'b0 ;
end
else
begin
fbnextscanline <= temp_fbnextscanline;
end
end
end
always @(posedge clk)
begin
case (state)
0 :
begin
weB <= 1'b0 ;
weC <= 1'b0 ;
weA <= fbdatavalid ;
if (nextscanline == 1'b1 & startframe == 1'b1)
begin
next_state <= 2 ;
end
else
begin
next_state <= 0 ;
end
if (startframe == 1'b1 & nextscanline == 1'b1)
begin
temp_fbnextscanline <= 1'b1 ;
end
end
1 :
begin
weB <= 1'b0 ;
weC <= 1'b0 ;
weA <= fbdatavalid ;
if (nextscanline == 1'b1)
begin
next_state <= 2 ;
end
else
begin
next_state <= 1 ;
end
if (nextscanline == 1'b1)
begin
temp_fbnextscanline <= 1'b1 ;
end
end
2 :
begin
weA <= 1'b0 ;
weC <= 1'b0 ;
weB <= fbdatavalid ;
if (nextscanline == 1'b1)
begin
next_state <= 3 ;
end
else
begin
next_state <= 2 ;
end
if (nextscanline == 1'b1)
begin
temp_fbnextscanline <= 1'b1 ;
end
end
3 :
begin
weA <= 1'b0 ;
weB <= 1'b0 ;
weC <= fbdatavalid ;
if (nextscanline == 1'b1)
begin
next_state <= 1 ;
end
else
begin
next_state <= 3 ;
end
if (nextscanline == 1'b1)
begin
temp_fbnextscanline <= 1'b1 ;
end
end
endcase
end
endmodule |
module scanline (nextpixel, we, datain, pixeldata, globalreset, clk);
input nextpixel;
input we;
input[62:0] datain;
output[20:0] pixeldata;
reg[20:0] pixeldata;
input globalreset;
input clk;
reg[6:0] addr;
reg[6:0] waddr;
reg[6:0] raddr;
reg[1:0] subitem;
reg wedelayed;
reg[62:0]mem1;
reg[62:0]mem2;
wire[62:0] mdataout;
assign mdataout = mem2 ;
always @(posedge clk)
begin
if (globalreset == 1'b1)
begin
subitem <= 2'b00 ;
waddr <= 1;
raddr <= 1;
wedelayed <= 1'b0 ;
pixeldata <= 1;
end
else
begin
wedelayed <= we ;
if (nextpixel == 1'b1 | wedelayed == 1'b1)
begin
case (subitem)
2'b00 :
begin
pixeldata <= mdataout[62:42] ;
end
2'b01 :
begin
pixeldata <= mdataout[41:21] ;
end
2'b10 :
begin
pixeldata <= mdataout[20:0] ;
end
default :
begin
pixeldata <= 1;
end
endcase
end
if (nextpixel == 1'b1)
begin
case (subitem)
2'b00 :
begin
subitem <= 2'b01 ;
end
2'b01 :
begin
subitem <= 2'b10 ;
end
2'b10 :
begin
subitem <= 2'b00 ;
if (raddr != 7'b1101010)
begin
raddr <= raddr + 1 ;
end
else
begin
raddr <= 1;
end
end
endcase
end
if (we == 1'b1)
begin
if (waddr != 7'b1101010)
begin
waddr <= waddr + 1 ;
end
else
begin
waddr <= 1;
end
end
end
end
always @(posedge clk)
begin
addr <= raddr ;
if (we == 1'b1)
begin
mem1 <= datain ;
mem2 <= mem1 ;
end
end
endmodule |
module memory_controller
(
clk,
addr1,
addr2,
we1,
we2,
data1,
data2,
sp_out,
dp_out1,
dp_out2
);
input clk;
input we1, we2;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] addr1,addr2;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] data1,data2;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
wire [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
single_port_ram sp_ram (
.addr (addr1),
.data (data1),
.we (we1),
.clk (clk),
.out (sp_out)
);
dual_port_ram dp_ram (
.addr1 (addr1),
.addr2 (addr2),
.data1 (data1),
.data2 (data2),
.we1 (we1),
.we2 (we2),
.clk (clk),
.out1 (dp_out1),
.out2 (dp_out2)
);
endmodule |
module iir1
(
clk_i, /* Wishbone clk */
rst_i, /* Wishbone asynchronous active high reset */
we_i, /* Wishbone write enable */
stb_i, /* Wishbone strobe */
ack_o, /* Wishbone ack */
dat_i, /* Wishbone input data */
dat_o, /* Wishbone output data */
adr_i, /* Wishbone address bus */
dspclk, /* DSP processing clock */
nreset, /* active low asynchronous reset for filter block */
x, /* input data for filter */
valid, /* data valid input */
y /* filter output data */
);
input clk_i;
input rst_i;
input we_i;
input stb_i;
output ack_o;
input [15:0] dat_i;
output [15:0] dat_o;
input [2:0] adr_i;
input dspclk;
input nreset;
input [`DATAWIDTH-1:0] x;
input valid;
output [`DATAWIDTH-1:0] y;
wire [15:0] a11;
wire [15:0] a12;
wire [15:0] b10;
wire [15:0] b11;
wire [15:0] b12;
/* Filter module */
biquad biquadi
(
.clk(dspclk), /* clock */
.nreset(nreset), /* active low reset */
.x(x), /* data input */
.valid(valid), /* input data valid */
.a11(a11[15:16-`COEFWIDTH]), /* filter pole coefficient */
.a12(a12[15:16-`COEFWIDTH]), /* filter pole coefficient */
.b10(b10[15:16-`COEFWIDTH]), /* filter zero coefficient */
.b11(b11[15:16-`COEFWIDTH]), /* filter zero coefficient */
.b12(b12[15:16-`COEFWIDTH]), /* filter zero coefficient */
.yout(y) /* filter output */
);
/* Wishbone interface module */
coefio coefioi
(
.clk_i(clk_i),
.rst_i(rst_i),
.we_i(we_i),
.stb_i(stb_i),
.ack_o(ack_o),
.dat_i(dat_i),
.dat_o(dat_o),
.adr_i(adr_i),
.a11(a11),
.a12(a12),
.b10(b10),
.b11(b11),
.b12(b12)
);
endmodule |
module biquad
(
clk, /* clock */
nreset, /* active low reset */
x, /* data input */
valid, /* input data valid */
a11, /* filter pole coefficient */
a12, /* filter pole coefficient */
b10, /* filter zero coefficient */
b11, /* filter zero coefficient */
b12, /* filter zero coefficient */
yout /* filter output */
);
// Acumulator width is (`DATAWIDTH + `ACCUM) bits.
input clk;
input nreset;
input [`DATAWIDTH-1:0] x;
input valid;
input [`COEFWIDTH-1:0] a11;
input [`COEFWIDTH-1:0] a12;
input [`COEFWIDTH-1:0] b10;
input [`COEFWIDTH-1:0] b11;
input [`COEFWIDTH-1:0] b12;
output [`DATAWIDTH-1:0] yout;
reg [`DATAWIDTH-1:0] xvalid;
reg [`DATAWIDTH-1:0] xm1;
reg [`DATAWIDTH-1:0] xm2;
reg [`DATAWIDTH-1:0] xm3;
reg [`DATAWIDTH-1:0] xm4;
reg [`DATAWIDTH-1:0] xm5;
reg [`DATAWIDTH+3+`ACCUM:0] sumb10reg;
reg [`DATAWIDTH+3+`ACCUM:0] sumb11reg;
reg [`DATAWIDTH+3+`ACCUM:0] sumb12reg;
reg [`DATAWIDTH+3+`ACCUM:0] suma12reg;
reg [`DATAWIDTH+3:0] y;
reg [`DATAWIDTH-1:0] yout;
wire [`COEFWIDTH-1:0] sa11;
wire [`COEFWIDTH-1:0] sa12;
wire [`COEFWIDTH-1:0] sb10;
wire [`COEFWIDTH-1:0] sb11;
wire [`COEFWIDTH-1:0] sb12;
wire [`DATAWIDTH-2:0] tempsum;
wire [`DATAWIDTH+3+`ACCUM:0] tempsum2;
wire [`DATAWIDTH + `COEFWIDTH - 3:0] mb10out;
wire [`DATAWIDTH+3+`ACCUM:0] sumb10;
wire [`DATAWIDTH + `COEFWIDTH - 3:0] mb11out;
wire [`DATAWIDTH+3+`ACCUM:0] sumb11;
wire [`DATAWIDTH + `COEFWIDTH - 3:0] mb12out;
wire [`DATAWIDTH+3+`ACCUM:0] sumb12;
wire [`DATAWIDTH + `COEFWIDTH + 1:0] ma12out;
wire [`DATAWIDTH+3+`ACCUM:0] suma12;
wire [`DATAWIDTH + `COEFWIDTH + 1:0] ma11out;
wire [`DATAWIDTH+3+`ACCUM:0] suma11;
wire [`DATAWIDTH+2:0] sy;
wire [`DATAWIDTH-1:0] olimit;
/* Two's complement of coefficients */
assign sa11 = a11[`COEFWIDTH-1] ? (-a11) : a11;
assign sa12 = a12[`COEFWIDTH-1] ? (-a12) : a12;
assign sb10 = b10[`COEFWIDTH-1] ? (-b10) : b10;
assign sb11 = b11[`COEFWIDTH-1] ? (-b11) : b11;
assign sb12 = b12[`COEFWIDTH-1] ? (-b12) : b12;
/*
assign sa11 = a11[`COEFWIDTH-1] ? (~a11 + 1) : a11;
assign sa12 = a12[`COEFWIDTH-1] ? (~a12 + 1) : a12;
assign sb10 = b10[`COEFWIDTH-1] ? (~b10 + 1) : b10;
assign sb11 = b11[`COEFWIDTH-1] ? (~b11 + 1) : b11;
assign sb12 = b12[`COEFWIDTH-1] ? (~b12 + 1) : b12;
*/
assign tempsum = -xvalid[`DATAWIDTH-2:0];
//assign tempsum = ~xvalid[`DATAWIDTH-2:0] + 1;
assign tempsum2 = -{4'b0000,mb10out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]};
//assign tempsum2 = ~{4'b0000,mb10out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]} + 1;
/* clock data into pipeline. Divide by 8. Convert to sign magnitude. */
always @(posedge clk or negedge nreset)
begin
if ( ~nreset )
begin
xvalid <= 0;
xm1 <= 0;
xm2 <= 0;
xm3 <= 0;
xm4 <= 0;
xm5 <= 0;
end
else
begin
xvalid <= valid ? x : xvalid;
xm1 <= valid ? (xvalid[`DATAWIDTH-1] ? ({xvalid[`DATAWIDTH-1],tempsum}) : {xvalid}) : xm1;
xm2 <= valid ? xm1 : xm2;
xm3 <= valid ? xm2 : xm3;
xm4 <= valid ? xm3 : xm4;
xm5 <= valid ? xm4 : xm5;
end
end
/* Multiply input by filter coefficient b10 */
multb multb10(.a(sb10[`COEFWIDTH-2:0]),.b(xm1[`DATAWIDTH-2:0]),.r(mb10out));
assign sumb10 = (b10[`COEFWIDTH-1] ^ xm1[`DATAWIDTH-1]) ? (tempsum2) : ({4'b0000,mb10out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]});
/* Multiply input by filter coefficient b11 */
multb multb11(.a(sb11[`COEFWIDTH-2:0]),.b(xm3[`DATAWIDTH-2:0]),.r(mb11out));
/* Divide by two and add or subtract */
assign sumb11 = (b11[`COEFWIDTH-1] ^ xm3[`DATAWIDTH-1]) ? (sumb10reg - {4'b0000,mb11out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]}) :
(sumb10reg + {4'b0000,mb11out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]});
/* Multiply input by filter coefficient b12 */
multb multb12(.a(sb12[`COEFWIDTH-2:0]),.b(xm5[`DATAWIDTH-2:0]),.r(mb12out));
assign sumb12 = (b12[`COEFWIDTH-1] ^ xm5[`DATAWIDTH-1]) ? (sumb11reg - {4'b0000,mb12out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]}) :
(sumb11reg + {4'b0000,mb12out[`COEFWIDTH+`DATAWIDTH-3:`COEFWIDTH-2-`ACCUM]});
/* Twos complement of output for feedback */
//assign sy = y[`DATAWIDTH+3] ? (-y) : y;
assign sy = y[`DATAWIDTH+3] ? (~y + 1) : y;
/* Multiply output by filter coefficient a12 */
multa multa12(.a(sa12[`COEFWIDTH-2:0]),.b(sy[`DATAWIDTH+2:0]),.r(ma12out));
assign suma12 = (a12[`COEFWIDTH-1] ^ y[`DATAWIDTH+3]) ? (sumb12reg - {1'b0,ma12out[`COEFWIDTH+`DATAWIDTH:`COEFWIDTH-2-`ACCUM]}) :
(sumb12reg + {1'b0,ma12out[`COEFWIDTH+`DATAWIDTH:`COEFWIDTH-2-`ACCUM]});
/* Multiply output by filter coefficient a11 */
multa multa11(.a(sa11[`COEFWIDTH-2:0]),.b(sy[`DATAWIDTH+2:0]),.r(ma11out));
assign suma11 = (a11[`COEFWIDTH-1] ^ y[`DATAWIDTH+3]) ? (suma12reg - {1'b0,ma11out[`COEFWIDTH+`DATAWIDTH:`COEFWIDTH-2-`ACCUM]}) :
(suma12reg + {1'b0,ma11out[`COEFWIDTH+`DATAWIDTH:`COEFWIDTH-2-`ACCUM]});
assign olimit = {y[`DATAWIDTH+3],~y[`DATAWIDTH+3],~y[`DATAWIDTH+3],~y[`DATAWIDTH+3],~y[`DATAWIDTH+3],
~y[`DATAWIDTH+3],~y[`DATAWIDTH+3],~y[`DATAWIDTH+3]};
/* State registers */
always @(posedge clk or negedge nreset)
begin
if ( ~nreset )
begin
sumb10reg <= 0;
sumb11reg <= 0;
sumb12reg <= 0;
suma12reg <= 0;
y <= 0;
yout <= 0;
end
else
begin
sumb10reg <= valid ? (sumb10) : (sumb10reg);
sumb11reg <= valid ? (sumb11) : (sumb11reg);
sumb12reg <= valid ? (sumb12) : (sumb12reg);
suma12reg <= valid ? (suma12) : (suma12reg);
y <= valid ? suma11[`DATAWIDTH+3+`ACCUM:`ACCUM] : y;
yout <= valid ? (( (&y[`DATAWIDTH+3:`DATAWIDTH-1]) | (~|y[`DATAWIDTH+3:`DATAWIDTH-1]) ) ?
(y[`DATAWIDTH-1:0]) : (olimit)) : (yout);
end
end
endmodule |
module coefio
(
clk_i,
rst_i,
we_i,
stb_i,
ack_o,
dat_i,
dat_o,
adr_i,
a11,
a12,
b10,
b11,
b12
);
input clk_i;
input rst_i;
input we_i;
input stb_i;
output ack_o;
input [15:0] dat_i;
output [15:0] dat_o;
input [2:0] adr_i;
output [15:0] a11;
output [15:0] a12;
output [15:0] b10;
output [15:0] b11;
output [15:0] b12;
reg [15:0] a11;
reg [15:0] a12;
reg [15:0] b10;
reg [15:0] b11;
reg [15:0] b12;
wire ack_o;
wire sel_a11;
wire sel_a12;
wire sel_b10;
wire sel_b11;
wire sel_b12;
assign sel_a11 = (adr_i == 3'b000);
assign sel_a12 = (adr_i == 3'b001);
assign sel_b10 = (adr_i == 3'b010);
assign sel_b11 = (adr_i == 3'b011);
assign sel_b12 = (adr_i == 3'b100);
assign ack_o = stb_i;
always @(posedge clk_i or posedge rst_i)
if ( rst_i )
begin
a11 <= 15'b11111111;
a12 <= 15'b11111;
b10 <= 15'b1111111;
b11 <= 15'b11;
b12 <= 15'b11111111;
/*
a11 <= 15'd0;
a12 <= 15'd0;
b10 <= 15'd0;
b11 <= 15'd0;
b12 <= 15'd0;
*/
end
else
begin
a11 <= (stb_i & we_i & sel_a11) ? (dat_i) : (a11);
a12 <= (stb_i & we_i & sel_a12) ? (dat_i) : (a12);
b10 <= (stb_i & we_i & sel_b10) ? (dat_i) : (b10);
b11 <= (stb_i & we_i & sel_b11) ? (dat_i) : (b11);
b12 <= (stb_i & we_i & sel_b12) ? (dat_i) : (b12);
end
assign dat_o = sel_a11 ? (a11) :
((sel_a12) ? (a12) :
((sel_b10) ? (b10) :
((sel_b11) ? (b11) :
((sel_b12) ? (b12) :
(16'h0000)))));
endmodule |
module multa
(
// clk,
// nreset,
a, /* data input */
b, /* input data valid */
r /* filter pole coefficient */
);
//input clk;
//input nreset;
input [`COEFWIDTH-2:0] a;
input [`DATAWIDTH+2:0] b;
output [`DATAWIDTH + `COEFWIDTH + 1:0] r;
assign r = a*b;
endmodule |
module multb
(
a, /* data input */
b, /* input data valid */
r /* filter pole coefficient */
);
input [`COEFWIDTH-2:0] a;
input [`DATAWIDTH-2:0] b;
output [`DATAWIDTH + `COEFWIDTH - 3:0] r;
assign r = a*b;
endmodule |
module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
input clk, reset, start;
input [7:0] din;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
reg ready;
reg temp_ready;
reg [6:0] finite_counter;
wire count0;
input iir_start;
output iir_done;
wire iir_done;
reg del_count0;
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
//wire [23:0] b0t, b1t, b2t;
wire [22:0] b0t, b1t, b2t;
wire [22:0] b0tpaj, b1tpaj, b2tpaj;
reg [3:0] obf_state, obf_next_state ;
reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
reg [28:0] temp_ysum ;
reg [26:0] temp_yk ;
reg [22:0] temp_utmp;
reg [7:0] temp_dout;
reg [3:0] temp_wait_counter ;
parameter
idle = 4'b0001 ,
load_a2 = 4'b0010 ,
load_b0 = 4'b0011 ,
load_b1 = 4'b0100 ,
load_b2 = 4'b0101 ,
wait4_start = 4'b0110 ,
latch_din = 4'b0111 ,
compute_a = 4'b1000 ,
compute_b = 4'b1001 ,
compute_yk = 4'b1010 ,
wait4_count = 4'b1011 ,
latch_dout = 4'b1100 ;
always @(posedge clk)
begin
case (obf_state )
idle :
begin
if (iir_start)
obf_next_state <= load_a2 ;
else
obf_next_state <= idle;
temp_a1 <= params ;
end
load_a2 :
begin
obf_next_state <= load_b0 ;
temp_a2 <= params ;
end
load_b0 :
begin
obf_next_state <= load_b1 ;
temp_b0 <= params ;
end
load_b1 :
begin
obf_next_state <= load_b2 ;
temp_b1 <= params ;
end
load_b2 :
begin
obf_next_state <= wait4_start ;
temp_b2 <= params ;
end
wait4_start :
begin
if (start)
begin
obf_next_state <= latch_din ;
temp_uk <= din ;
end
else
begin
obf_next_state <= wait4_start ;
temp_uk <= uk;
end
temp_ready <= wait4_start;
end
latch_din :
begin
obf_next_state <= compute_a ;
end
compute_a :
begin
obf_next_state <= compute_b ;
temp_ysum <= yo1[31:3] + yo2[31:3];
end
compute_b :
begin
obf_next_state <= compute_yk ;
// temp_utmp <= b0t[23:0] + b1t[23:0] + b2t[23:0];
temp_utmp <= b0t + b1t + b2t;
end
compute_yk :
begin
obf_next_state <= wait4_count ;
temp_uk1 <= uk ;
temp_uk2 <= uk1 ;
temp_yk <= ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
temp_wait_counter <= 4 ;
end
wait4_count :
begin
if (wait_counter==0 )
begin
obf_next_state <= latch_dout ;
temp_dout <= yk[26:19];
temp_yk1 <= yk[26:11] ;
temp_yk2 <= yk1 ;
end
else
begin
obf_next_state <= wait4_count ;
temp_dout <= dout;
temp_yk1 <= yk1;
//temp_yk2 <= yk2;
end
temp_wait_counter <= wait_counter - 1;
end
latch_dout :
if (count0)
obf_next_state <= idle;
else
obf_next_state <= wait4_start ;
endcase
end
//assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo1 = yk1 * a1;
//assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign yo2 = yk2*a2;
//assign b0t = mul_tc_8_16(uk, b0, clk);
//assign b1t = mul_tc_8_16(uk1, b1, clk);
//assign b2t = mul_tc_8_16(uk2, b2, clk);
assign b0t = uk*b0;
assign b1t = uk1*b1;
assign b2t = uk2*b2;
// paj added to solve unused high order bit
assign b0tpaj = b0t;
assign b1tpaj = b1t;
assign b2tpaj = b2t;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
obf_state <= idle ;
ready <= 0;
end
else begin
obf_state <= obf_next_state ;
uk1 <= temp_uk1;
uk2 <= temp_uk2;
yk <= temp_yk;
uk <= temp_uk ;
a1 <= temp_a1 ;
a2 <= temp_a2 ;
b0 <= temp_b0 ;
b1 <= temp_b1 ;
b2 <= temp_b2 ;
ysum <= temp_ysum;
utmp <= temp_utmp;
dout <= temp_dout;
yk1 <= temp_yk1;
yk2 <= temp_yk2;
ready <= temp_ready;
end
end
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
wait_counter <= temp_wait_counter ;
end
end
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
assign count0=finite_counter==7'b0;
always @(posedge clk) begin
del_count0 <= count0;
end
assign iir_done = (count0 && ~del_count0);
endmodule |
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in & b_in;
end
endmodule |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.