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module TGATE(in,
sel,
selb,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- INPUT PORTS -----
input [0:0] sel;
//----- INPUT PORTS -----
input [0:0] selb;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
assign out = sel ? in : 1'bz;
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(in => out) = (0.01, 0.01);
(sel => out) = (0.005, 0.005);
(selb => out) = (0.005, 0.005);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
endmodule |
module sb_1__2_(pReset,
prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
chany_bottom_in,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chanx_right_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_2_sram;
wire [0:1] mux_2level_tapbuf_size3_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:5] mux_2level_tapbuf_size7_0_sram;
wire [0:5] mux_2level_tapbuf_size7_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size7_1_sram;
wire [0:5] mux_2level_tapbuf_size7_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size7_mem_0_ccff_tail;
wire [0:7] mux_2level_tapbuf_size9_0_sram;
wire [0:7] mux_2level_tapbuf_size9_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_1_sram;
wire [0:7] mux_2level_tapbuf_size9_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_2_sram;
wire [0:7] mux_2level_tapbuf_size9_2_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_3_sram;
wire [0:7] mux_2level_tapbuf_size9_3_sram_inv;
wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chanx_right_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chanx_left_in[3];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size9 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[1], chany_bottom_in[4], chany_bottom_in[7], chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size9_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_0_sram_inv[0:7]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size9 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[9], chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size9_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_1_sram_inv[0:7]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size9 mux_left_track_1 (
.in({chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], chany_bottom_in[2], chany_bottom_in[5], chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_2_sram_inv[0:7]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size9 mux_left_track_9 (
.in({chanx_right_in[1], chanx_right_in[5], chany_bottom_in[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_3_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_3_sram_inv[0:7]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size9_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_0_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_1_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_2_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_3_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_3_sram_inv[0:7]));
mux_2level_tapbuf_size7 mux_right_track_16 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[2], chany_bottom_in[5], chany_bottom_in[8], chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size7_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size7_0_sram_inv[0:5]),
.out(chanx_right_out[8]));
mux_2level_tapbuf_size7 mux_left_track_17 (
.in({chanx_right_in[2], chanx_right_in[6], chany_bottom_in[1], chany_bottom_in[4], chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size7_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size7_1_sram_inv[0:5]),
.out(chanx_left_out[8]));
mux_2level_tapbuf_size7_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size7_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size7_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size7_0_sram_inv[0:5]));
mux_2level_tapbuf_size7_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size7_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size7_1_sram_inv[0:5]));
mux_2level_tapbuf_size4 mux_bottom_track_1 (
.in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, chanx_left_in[0], chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size4 mux_bottom_track_3 (
.in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[1], chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(chany_bottom_out[1]));
mux_2level_tapbuf_size4_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size7_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size3 mux_bottom_track_5 (
.in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_left_in[2]}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_2level_tapbuf_size3 mux_bottom_track_7 (
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[4]}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_2level_tapbuf_size3 mux_bottom_track_13 (
.in({chanx_right_in[8:9], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_2_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_2level_tapbuf_size3_mem mem_bottom_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_bottom_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_bottom_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_2_sram_inv[0:1]));
mux_2level_tapbuf_size2 mux_bottom_track_9 (
.in({chanx_right_in[5], chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size2 mux_bottom_track_11 (
.in({chanx_right_in[6], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_2level_tapbuf_size2_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
endmodule |
module sb_1__0_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:7] mux_2level_tapbuf_size10_0_sram;
wire [0:7] mux_2level_tapbuf_size10_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size10_1_sram;
wire [0:7] mux_2level_tapbuf_size10_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size10_mem_1_ccff_tail;
wire [0:7] mux_2level_tapbuf_size11_0_sram;
wire [0:7] mux_2level_tapbuf_size11_0_sram_inv;
wire [0:0] mux_2level_tapbuf_size11_mem_0_ccff_tail;
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:5] mux_2level_tapbuf_size5_0_sram;
wire [0:5] mux_2level_tapbuf_size5_0_sram_inv;
wire [0:0] mux_2level_tapbuf_size5_mem_0_ccff_tail;
wire [0:7] mux_2level_tapbuf_size9_0_sram;
wire [0:7] mux_2level_tapbuf_size9_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_1_sram;
wire [0:7] mux_2level_tapbuf_size9_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_2_sram;
wire [0:7] mux_2level_tapbuf_size9_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- Local connection due to Wire 45 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chanx_left_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size5 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, chanx_right_in[0], chanx_right_in[7], chanx_left_in[0], chanx_left_in[3]}),
.sram(mux_2level_tapbuf_size5_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size5_0_sram_inv[0:5]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size5_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size5_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size5_0_sram_inv[0:5]));
mux_2level_tapbuf_size4 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[1], chanx_right_in[9], chanx_left_in[1]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(chany_top_out[1]));
mux_2level_tapbuf_size4_mem mem_top_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size3 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_right_in[2], chanx_left_in[2]}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_2level_tapbuf_size3 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_right_in[4], chanx_left_in[4]}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_2level_tapbuf_size3_mem mem_top_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_top_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
mux_2level_tapbuf_size2 mux_top_track_8 (
.in({chanx_right_in[5], chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size2 mux_top_track_10 (
.in({chanx_right_in[6], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_2level_tapbuf_size2 mux_top_track_12 (
.in({chanx_right_in[8], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_2level_tapbuf_size2 mux_top_track_18 (
.in({chanx_right_in[3], chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_2level_tapbuf_size2_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size10 mux_right_track_0 (
.in({chany_top_in[2], chany_top_in[5], chany_top_in[8], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size10_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size10_0_sram_inv[0:7]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size10 mux_right_track_8 (
.in({chany_top_in[0], chany_top_in[3], chany_top_in[6], chany_top_in[9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size10_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size10_1_sram_inv[0:7]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size10_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size10_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size10_0_sram_inv[0:7]));
mux_2level_tapbuf_size10_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size10_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size10_1_sram_inv[0:7]));
mux_2level_tapbuf_size9 mux_right_track_16 (
.in({chany_top_in[1], chany_top_in[4], chany_top_in[7], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size9_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_0_sram_inv[0:7]),
.out(chanx_right_out[8]));
mux_2level_tapbuf_size9 mux_left_track_9 (
.in({chany_top_in[2], chany_top_in[5], chany_top_in[8], chanx_right_in[1], chanx_right_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_1_sram_inv[0:7]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size9 mux_left_track_17 (
.in({chany_top_in[1], chany_top_in[4], chany_top_in[7], chanx_right_in[2], chanx_right_in[6], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_2_sram_inv[0:7]),
.out(chanx_left_out[8]));
mux_2level_tapbuf_size9_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_0_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_1_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size9_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_2_sram_inv[0:7]));
mux_2level_tapbuf_size11 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3], chany_top_in[6], chany_top_in[9], chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size11_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size11_0_sram_inv[0:7]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size11_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size11_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size11_0_sram_inv[0:7]));
endmodule |
module cby_2__1_(pReset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I_2_,
left_grid_right_width_0_height_0_subtile_0__pin_I_3_,
left_grid_right_width_0_height_0_subtile_0__pin_I_4_,
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_2_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_3_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_4_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_10_sram;
wire [0:5] mux_2level_tapbuf_size4_10_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_11_sram;
wire [0:5] mux_2level_tapbuf_size4_11_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_12_sram;
wire [0:5] mux_2level_tapbuf_size4_12_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_13_sram;
wire [0:5] mux_2level_tapbuf_size4_13_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_7_sram;
wire [0:5] mux_2level_tapbuf_size4_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_8_sram;
wire [0:5] mux_2level_tapbuf_size4_8_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_9_sram;
wire [0:5] mux_2level_tapbuf_size4_9_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_10_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_11_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_12_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_2 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_3 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_4 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_6 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_left_ipin_7 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_7_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_7_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_8_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_8_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_0_));
mux_2level_tapbuf_size4 mux_right_ipin_1 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_2level_tapbuf_size4_9_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_9_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
mux_2level_tapbuf_size4 mux_right_ipin_2 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_10_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_10_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_2_));
mux_2level_tapbuf_size4 mux_right_ipin_3 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_11_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_11_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_3_));
mux_2level_tapbuf_size4 mux_right_ipin_4 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_12_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_12_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_4_));
mux_2level_tapbuf_size4 mux_right_ipin_5 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_13_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_13_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
mux_2level_tapbuf_size4_mem mem_left_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_7_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_7_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_8_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_8_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_8_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_8_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_9_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_9_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_9_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_9_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_10_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_10_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_10_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_10_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_11_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_11_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_11_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_11_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_12_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_12_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_12_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_12_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size4_13_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_13_sram_inv[0:5]));
endmodule |
module sb_0__2_(pReset,
prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
chany_bottom_in,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_10_sram;
wire [0:1] mux_2level_tapbuf_size2_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_11_sram;
wire [0:1] mux_2level_tapbuf_size2_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_12_sram;
wire [0:1] mux_2level_tapbuf_size2_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_13_sram;
wire [0:1] mux_2level_tapbuf_size2_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_14_sram;
wire [0:1] mux_2level_tapbuf_size2_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_15_sram;
wire [0:1] mux_2level_tapbuf_size2_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_6_sram;
wire [0:1] mux_2level_tapbuf_size2_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_7_sram;
wire [0:1] mux_2level_tapbuf_size2_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_8_sram;
wire [0:1] mux_2level_tapbuf_size2_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_9_sram;
wire [0:1] mux_2level_tapbuf_size2_9_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chanx_right_in[0];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chany_bottom_in[0];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chany_bottom_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size2 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[8]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size2 mux_right_track_2 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[7]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_2level_tapbuf_size2 mux_right_track_4 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_2level_tapbuf_size2 mux_right_track_6 (
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[5]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_2level_tapbuf_size2 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[4]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size2 mux_right_track_10 (
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[3]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_2level_tapbuf_size2 mux_right_track_12 (
.in({right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[2]}),
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_2level_tapbuf_size2 mux_right_track_14 (
.in({right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[1]}),
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_2level_tapbuf_size2 mux_bottom_track_1 (
.in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_8_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size2 mux_bottom_track_3 (
.in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_9_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_2level_tapbuf_size2 mux_bottom_track_5 (
.in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_10_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_2level_tapbuf_size2 mux_bottom_track_7 (
.in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_11_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_2level_tapbuf_size2 mux_bottom_track_9 (
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_12_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size2 mux_bottom_track_11 (
.in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_13_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_2level_tapbuf_size2 mux_bottom_track_13 (
.in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_14_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_2level_tapbuf_size2 mux_bottom_track_15 (
.in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_15_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_2level_tapbuf_size2_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_6_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_7_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_8_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_9_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_10_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_11_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_12_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_13_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_14_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_15_sram_inv[0:1]));
endmodule |
module cby_0__1_(pReset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_clk_0_,
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_clk_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_7_sram;
wire [0:5] mux_2level_tapbuf_size4_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_8_sram;
wire [0:5] mux_2level_tapbuf_size4_8_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_clk_0_));
mux_2level_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_1 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_2 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_3 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_4 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_5 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_6 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_7_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_7_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_right_ipin_7 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_8_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_8_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));
mux_2level_tapbuf_size4_mem mem_left_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_7_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_7_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size4_8_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_8_sram_inv[0:5]));
endmodule |
module cbx_1__2_(pReset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_7_sram;
wire [0:5] mux_2level_tapbuf_size4_7_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size4 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_3 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_4 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_5 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_6 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_bottom_ipin_7 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_2level_tapbuf_size4_7_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_7_sram_inv[0:5]),
.out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_bottom_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size4_7_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_7_sram_inv[0:5]));
endmodule |
module sb_2__1_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
ccff_head,
chany_top_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:7] mux_2level_tapbuf_size10_0_sram;
wire [0:7] mux_2level_tapbuf_size10_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size10_1_sram;
wire [0:7] mux_2level_tapbuf_size10_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size10_mem_1_ccff_tail;
wire [0:7] mux_2level_tapbuf_size11_0_sram;
wire [0:7] mux_2level_tapbuf_size11_0_sram_inv;
wire [0:0] mux_2level_tapbuf_size11_mem_0_ccff_tail;
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:7] mux_2level_tapbuf_size9_0_sram;
wire [0:7] mux_2level_tapbuf_size9_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_1_sram;
wire [0:7] mux_2level_tapbuf_size9_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_2_sram;
wire [0:7] mux_2level_tapbuf_size9_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chany_top_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chany_top_in[9];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size11 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8], chanx_left_in[0], chanx_left_in[3], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size11_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size11_0_sram_inv[0:7]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size11_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size11_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size11_0_sram_inv[0:7]));
mux_2level_tapbuf_size9 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[1], chany_bottom_in[5], chanx_left_in[2], chanx_left_in[5], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size9_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_0_sram_inv[0:7]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size9 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[2], chany_bottom_in[6], chanx_left_in[1], chanx_left_in[4], chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size9_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_1_sram_inv[0:7]),
.out(chany_top_out[8]));
mux_2level_tapbuf_size9 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_left_in[2], chanx_left_in[5], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size9_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_2_sram_inv[0:7]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size9_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_0_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_top_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_1_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_2_sram_inv[0:7]));
mux_2level_tapbuf_size10 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[1], chanx_left_in[4], chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size10_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size10_0_sram_inv[0:7]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size10 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[0], chanx_left_in[3], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size10_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size10_1_sram_inv[0:7]),
.out(chany_bottom_out[8]));
mux_2level_tapbuf_size10_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size10_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size10_0_sram_inv[0:7]));
mux_2level_tapbuf_size10_mem mem_bottom_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size10_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size10_1_sram_inv[0:7]));
mux_2level_tapbuf_size4 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3], chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size4 mux_left_track_3 (
.in({chany_top_in[1], chany_bottom_in[1], chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(chanx_left_out[1]));
mux_2level_tapbuf_size4 mux_left_track_5 (
.in({chany_top_in[2], chany_bottom_in[2], chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(chanx_left_out[2]));
mux_2level_tapbuf_size4 mux_left_track_7 (
.in({chany_top_in[4], chany_bottom_in[4], chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(chanx_left_out[3]));
mux_2level_tapbuf_size4_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_left_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size2 mux_left_track_9 (
.in({chany_top_in[5], chany_bottom_in[5]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size2 mux_left_track_11 (
.in({chany_top_in[6], chany_bottom_in[6]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_2level_tapbuf_size2 mux_left_track_13 (
.in({chany_top_in[8], chany_bottom_in[8]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_2level_tapbuf_size2_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
endmodule |
module sb_2__2_(pReset,
prog_clk,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_10_sram;
wire [0:1] mux_2level_tapbuf_size2_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_11_sram;
wire [0:1] mux_2level_tapbuf_size2_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_12_sram;
wire [0:1] mux_2level_tapbuf_size2_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_13_sram;
wire [0:1] mux_2level_tapbuf_size2_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_14_sram;
wire [0:1] mux_2level_tapbuf_size2_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_15_sram;
wire [0:1] mux_2level_tapbuf_size2_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_6_sram;
wire [0:1] mux_2level_tapbuf_size2_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_7_sram;
wire [0:1] mux_2level_tapbuf_size2_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_8_sram;
wire [0:1] mux_2level_tapbuf_size2_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_9_sram;
wire [0:1] mux_2level_tapbuf_size2_9_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chany_bottom_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size3 mux_bottom_track_1 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_left_in[1]}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size3 mux_bottom_track_3 (
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[2]}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_2level_tapbuf_size3_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_bottom_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
mux_2level_tapbuf_size2 mux_bottom_track_5 (
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_2level_tapbuf_size2 mux_bottom_track_7 (
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_2level_tapbuf_size2 mux_bottom_track_9 (
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size2 mux_bottom_track_11 (
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_2level_tapbuf_size2 mux_bottom_track_13 (
.in({bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_2level_tapbuf_size2 mux_bottom_track_15 (
.in({bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_2level_tapbuf_size2 mux_bottom_track_17 (
.in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_2level_tapbuf_size2 mux_bottom_track_19 (
.in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[0]}),
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_bottom_out[9]));
mux_2level_tapbuf_size2 mux_left_track_1 (
.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size2 mux_left_track_3 (
.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_2level_tapbuf_size2 mux_left_track_5 (
.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_2level_tapbuf_size2 mux_left_track_7 (
.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_2level_tapbuf_size2 mux_left_track_9 (
.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size2 mux_left_track_11 (
.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_2level_tapbuf_size2 mux_left_track_13 (
.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_2level_tapbuf_size2 mux_left_track_15 (
.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_2level_tapbuf_size2_mem mem_bottom_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_6_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_track_19 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_7_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_8_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_9_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_10_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_11_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_12_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_13_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_14_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_15_sram_inv[0:1]));
endmodule |
module cbx_1__0_(pReset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_7_sram;
wire [0:5] mux_2level_tapbuf_size4_7_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size2 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
mux_2level_tapbuf_size2 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_));
mux_2level_tapbuf_size2 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_));
mux_2level_tapbuf_size2 mux_bottom_ipin_3 (
.in({chanx_left_in[3], chanx_right_in[3]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_));
mux_2level_tapbuf_size2 mux_bottom_ipin_4 (
.in({chanx_left_in[4], chanx_right_in[4]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_));
mux_2level_tapbuf_size2 mux_bottom_ipin_5 (
.in({chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
mux_2level_tapbuf_size4 mux_top_ipin_0 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_1 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_2 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_3 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_4 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_5 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_6 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));
mux_2level_tapbuf_size4 mux_top_ipin_7 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_2level_tapbuf_size4_7_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_7_sram_inv[0:5]),
.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));
mux_2level_tapbuf_size4_mem mem_top_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_top_ipin_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size4_7_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_7_sram_inv[0:5]));
endmodule |
module sb_0__0_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_10_sram;
wire [0:1] mux_2level_tapbuf_size2_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_11_sram;
wire [0:1] mux_2level_tapbuf_size2_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_12_sram;
wire [0:1] mux_2level_tapbuf_size2_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_13_sram;
wire [0:1] mux_2level_tapbuf_size2_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_14_sram;
wire [0:1] mux_2level_tapbuf_size2_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_15_sram;
wire [0:1] mux_2level_tapbuf_size2_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_6_sram;
wire [0:1] mux_2level_tapbuf_size2_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_7_sram;
wire [0:1] mux_2level_tapbuf_size2_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_8_sram;
wire [0:1] mux_2level_tapbuf_size2_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_9_sram;
wire [0:1] mux_2level_tapbuf_size2_9_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chanx_right_in[0];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size2 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size2 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_2level_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_2level_tapbuf_size2 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_2level_tapbuf_size2 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size2 mux_top_track_10 (
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[6]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_2level_tapbuf_size2 mux_top_track_12 (
.in({top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[7]}),
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_2level_tapbuf_size2 mux_top_track_14 (
.in({top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}),
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_2level_tapbuf_size2 mux_right_track_4 (
.in({chany_top_in[1], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_}),
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_2level_tapbuf_size2 mux_right_track_6 (
.in({chany_top_in[2], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_2level_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_2level_tapbuf_size2 mux_right_track_12 (
.in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_2level_tapbuf_size2 mux_right_track_14 (
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_2level_tapbuf_size2 mux_right_track_16 (
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_2level_tapbuf_size2 mux_right_track_18 (
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_2level_tapbuf_size2_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_6_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_7_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_8_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_9_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_10_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_11_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_12_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_13_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_14_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_15_sram_inv[0:1]));
mux_2level_tapbuf_size3 mux_right_track_0 (
.in({chany_top_in[9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size3 mux_right_track_2 (
.in({chany_top_in[0], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_2level_tapbuf_size3_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_right_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
endmodule |
module sb_1__1_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
chany_bottom_in,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
ccff_head,
chany_top_out,
chanx_right_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:7] mux_2level_tapbuf_size13_0_sram;
wire [0:7] mux_2level_tapbuf_size13_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size13_1_sram;
wire [0:7] mux_2level_tapbuf_size13_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size13_2_sram;
wire [0:7] mux_2level_tapbuf_size13_2_sram_inv;
wire [0:7] mux_2level_tapbuf_size13_3_sram;
wire [0:7] mux_2level_tapbuf_size13_3_sram_inv;
wire [0:0] mux_2level_tapbuf_size13_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size13_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size13_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size13_mem_3_ccff_tail;
wire [0:7] mux_2level_tapbuf_size9_0_sram;
wire [0:7] mux_2level_tapbuf_size9_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_1_sram;
wire [0:7] mux_2level_tapbuf_size9_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_2_sram;
wire [0:7] mux_2level_tapbuf_size9_2_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_3_sram;
wire [0:7] mux_2level_tapbuf_size9_3_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_4_sram;
wire [0:7] mux_2level_tapbuf_size9_4_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_5_sram;
wire [0:7] mux_2level_tapbuf_size9_5_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_6_sram;
wire [0:7] mux_2level_tapbuf_size9_6_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_7_sram;
wire [0:7] mux_2level_tapbuf_size9_7_sram_inv;
wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 43 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 46 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 47 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 48 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 50 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size13 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_right_in[0], chanx_right_in[4], chanx_right_in[7:8], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8], chanx_left_in[0], chanx_left_in[3:4], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size13_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size13_0_sram_inv[0:7]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size13 mux_right_track_0 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8:9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[7:8], chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size13_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size13_1_sram_inv[0:7]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size13 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], chanx_right_in[0], chanx_right_in[4], chanx_right_in[7:8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[0], chanx_left_in[4], chanx_left_in[7:8]}),
.sram(mux_2level_tapbuf_size13_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size13_2_sram_inv[0:7]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size13 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3:4], chany_top_in[8], chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8:9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_2level_tapbuf_size13_3_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size13_3_sram_inv[0:7]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size13_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size13_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size13_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size13_0_sram_inv[0:7]));
mux_2level_tapbuf_size13_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size13_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size13_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size13_1_sram_inv[0:7]));
mux_2level_tapbuf_size13_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size13_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size13_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size13_2_sram_inv[0:7]));
mux_2level_tapbuf_size13_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size13_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size13_3_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size13_3_sram_inv[0:7]));
mux_2level_tapbuf_size9 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[1], chanx_right_in[5], chanx_right_in[9], chany_bottom_in[1], chany_bottom_in[5], chanx_left_in[1], chanx_left_in[5], chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size9_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_0_sram_inv[0:7]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size9 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_right_in[2:3], chanx_right_in[6], chany_bottom_in[2], chany_bottom_in[6], chanx_left_in[2], chanx_left_in[6:7]}),
.sram(mux_2level_tapbuf_size9_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_1_sram_inv[0:7]),
.out(chany_top_out[8]));
mux_2level_tapbuf_size9 mux_right_track_8 (
.in({chany_top_in[1], chany_top_in[3], chany_top_in[5], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1], chany_bottom_in[3], chany_bottom_in[5], chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size9_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_2_sram_inv[0:7]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size9 mux_right_track_16 (
.in({chany_top_in[2], chany_top_in[6:7], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[2], chany_bottom_in[6], chany_bottom_in[9], chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size9_3_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_3_sram_inv[0:7]),
.out(chanx_right_out[8]));
mux_2level_tapbuf_size9 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], chanx_right_in[1], chanx_right_in[3], chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[1], chanx_left_in[5], chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size9_4_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_4_sram_inv[0:7]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size9 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], chanx_right_in[2], chanx_right_in[6], chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_left_in[2:3], chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size9_5_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_5_sram_inv[0:7]),
.out(chany_bottom_out[8]));
mux_2level_tapbuf_size9 mux_left_track_9 (
.in({chany_top_in[1], chany_top_in[5], chany_top_in[9], chanx_right_in[1], chanx_right_in[5], chany_bottom_in[1], chany_bottom_in[3], chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_}),
.sram(mux_2level_tapbuf_size9_6_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_6_sram_inv[0:7]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size9 mux_left_track_17 (
.in({chany_top_in[2], chany_top_in[6:7], chanx_right_in[2], chanx_right_in[6], chany_bottom_in[2], chany_bottom_in[6:7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_}),
.sram(mux_2level_tapbuf_size9_7_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_7_sram_inv[0:7]),
.out(chanx_left_out[8]));
mux_2level_tapbuf_size9_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size13_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_0_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_top_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_1_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size13_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_2_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_right_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_3_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_3_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size13_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_4_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_4_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_bottom_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_5_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_5_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size13_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_6_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_6_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_6_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size9_7_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_7_sram_inv[0:7]));
endmodule |
module sb_2__0_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_10_sram;
wire [0:1] mux_2level_tapbuf_size2_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_11_sram;
wire [0:1] mux_2level_tapbuf_size2_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_12_sram;
wire [0:1] mux_2level_tapbuf_size2_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_13_sram;
wire [0:1] mux_2level_tapbuf_size2_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_14_sram;
wire [0:1] mux_2level_tapbuf_size2_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_15_sram;
wire [0:1] mux_2level_tapbuf_size2_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_6_sram;
wire [0:1] mux_2level_tapbuf_size2_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_7_sram;
wire [0:1] mux_2level_tapbuf_size2_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_8_sram;
wire [0:1] mux_2level_tapbuf_size2_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_9_sram;
wire [0:1] mux_2level_tapbuf_size2_9_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_9_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_2_sram;
wire [0:1] mux_2level_tapbuf_size3_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_3_sram;
wire [0:1] mux_2level_tapbuf_size3_3_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size3 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size3 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_1_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[9]}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_2level_tapbuf_size3 mux_left_track_1 (
.in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_2_sram_inv[0:1]),
.out(chanx_left_out[0]));
mux_2level_tapbuf_size3 mux_left_track_3 (
.in({chany_top_in[9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_3_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_2level_tapbuf_size3_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_top_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_left_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_2_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_left_track_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_3_sram_inv[0:1]));
mux_2level_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_2_, chanx_left_in[8]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_2level_tapbuf_size2 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[7]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_2level_tapbuf_size2 mux_top_track_8 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size2 mux_top_track_10 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_2level_tapbuf_size2 mux_top_track_12 (
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_2level_tapbuf_size2 mux_top_track_14 (
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_2level_tapbuf_size2 mux_top_track_16 (
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_2level_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_2level_tapbuf_size2 mux_top_track_18 (
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[1]}),
.sram(mux_2level_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_2level_tapbuf_size2 mux_left_track_5 (
.in({chany_top_in[8], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_}),
.sram(mux_2level_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_2level_tapbuf_size2 mux_left_track_7 (
.in({chany_top_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_}),
.sram(mux_2level_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_2level_tapbuf_size2 mux_left_track_9 (
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_2level_tapbuf_size2 mux_left_track_11 (
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_2level_tapbuf_size2 mux_left_track_13 (
.in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_2level_tapbuf_size2 mux_left_track_15 (
.in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_2level_tapbuf_size2 mux_left_track_17 (
.in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_2level_tapbuf_size2 mux_left_track_19 (
.in({chany_top_in[1], left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_2level_tapbuf_size2_mem mem_top_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_14 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_6_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_top_track_18 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_7_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_8_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_7 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_9_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_10_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_11 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_11_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_13 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_12_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_15 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_13_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_14_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_left_track_19 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_15_sram_inv[0:1]));
endmodule |
module cbx_1__1_(pReset,
prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_4_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size2 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
mux_2level_tapbuf_size2 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_7_));
mux_2level_tapbuf_size2 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2]}),
.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_8_));
mux_2level_tapbuf_size2 mux_bottom_ipin_3 (
.in({chanx_left_in[3], chanx_right_in[3]}),
.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_9_));
mux_2level_tapbuf_size2 mux_bottom_ipin_4 (
.in({chanx_left_in[4], chanx_right_in[4]}),
.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_10_));
mux_2level_tapbuf_size2 mux_bottom_ipin_5 (
.in({chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_11_));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_bottom_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));
endmodule |
module cby_1__1_(pReset,
prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_clk_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I_2_,
left_grid_right_width_0_height_0_subtile_0__pin_I_3_,
left_grid_right_width_0_height_0_subtile_0__pin_I_4_,
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_clk_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_2_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_3_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_4_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_4_sram;
wire [0:5] mux_2level_tapbuf_size4_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_5_sram;
wire [0:5] mux_2level_tapbuf_size4_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_6_sram;
wire [0:5] mux_2level_tapbuf_size4_6_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_clk_0_));
mux_2level_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_0_));
mux_2level_tapbuf_size4 mux_right_ipin_1 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
mux_2level_tapbuf_size4 mux_right_ipin_2 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_2_));
mux_2level_tapbuf_size4 mux_right_ipin_3 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_2level_tapbuf_size4_4_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_4_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_3_));
mux_2level_tapbuf_size4 mux_right_ipin_4 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_2level_tapbuf_size4_5_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_5_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_4_));
mux_2level_tapbuf_size4 mux_right_ipin_5 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_2level_tapbuf_size4_6_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_6_sram_inv[0:5]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
mux_2level_tapbuf_size4_mem mem_left_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_4_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_4_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_5_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_5_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_ipin_5 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size4_6_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_6_sram_inv[0:5]));
endmodule |
module sb_0__1_(pReset,
prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_,
chany_bottom_in,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size2_mem_1_ccff_tail;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size3_mem_1_ccff_tail;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size4_mem_2_ccff_tail;
wire [0:5] mux_2level_tapbuf_size7_0_sram;
wire [0:5] mux_2level_tapbuf_size7_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size8_0_sram;
wire [0:5] mux_2level_tapbuf_size8_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size8_1_sram;
wire [0:5] mux_2level_tapbuf_size8_1_sram_inv;
wire [0:0] mux_2level_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size8_mem_1_ccff_tail;
wire [0:7] mux_2level_tapbuf_size9_0_sram;
wire [0:7] mux_2level_tapbuf_size9_0_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_1_sram;
wire [0:7] mux_2level_tapbuf_size9_1_sram_inv;
wire [0:7] mux_2level_tapbuf_size9_2_sram;
wire [0:7] mux_2level_tapbuf_size9_2_sram_inv;
wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 34 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chany_bottom_in[3];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_2level_tapbuf_size9 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[1], chanx_right_in[4], chanx_right_in[7], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8]}),
.sram(mux_2level_tapbuf_size9_0_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_0_sram_inv[0:7]),
.out(chany_top_out[0]));
mux_2level_tapbuf_size9 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], chanx_right_in[1], chanx_right_in[4], chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_1_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_1_sram_inv[0:7]),
.out(chany_bottom_out[0]));
mux_2level_tapbuf_size9 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], chanx_right_in[0], chanx_right_in[3], chanx_right_in[6], chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size9_2_sram[0:7]),
.sram_inv(mux_2level_tapbuf_size9_2_sram_inv[0:7]),
.out(chany_bottom_out[4]));
mux_2level_tapbuf_size9_mem mem_top_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_0_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_0_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_bottom_track_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_1_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_1_sram_inv[0:7]));
mux_2level_tapbuf_size9_mem mem_bottom_track_9 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size9_2_sram[0:7]),
.mem_outb(mux_2level_tapbuf_size9_2_sram_inv[0:7]));
mux_2level_tapbuf_size8 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[2], chanx_right_in[5], chanx_right_in[8], chany_bottom_in[1], chany_bottom_in[5]}),
.sram(mux_2level_tapbuf_size8_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size8_0_sram_inv[0:5]),
.out(chany_top_out[4]));
mux_2level_tapbuf_size8 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[0], chanx_right_in[3], chanx_right_in[6], chanx_right_in[9], chany_bottom_in[2], chany_bottom_in[6]}),
.sram(mux_2level_tapbuf_size8_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size8_1_sram_inv[0:5]),
.out(chany_top_out[8]));
mux_2level_tapbuf_size8_mem mem_top_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size8_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size8_0_sram_inv[0:5]));
mux_2level_tapbuf_size8_mem mem_top_track_16 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size8_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size8_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size8_1_sram_inv[0:5]));
mux_2level_tapbuf_size3 mux_right_track_0 (
.in({chany_top_in[0], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_4_, chany_bottom_in[0]}),
.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_2level_tapbuf_size3 mux_right_track_12 (
.in({chany_top_in[8], chany_bottom_in[8:9]}),
.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_2level_tapbuf_size3_mem mem_right_track_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size8_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));
mux_2level_tapbuf_size3_mem mem_right_track_12 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));
mux_2level_tapbuf_size4 mux_right_track_2 (
.in({chany_top_in[1], chany_top_in[3], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_, chany_bottom_in[1]}),
.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
.out(chanx_right_out[1]));
mux_2level_tapbuf_size4 mux_right_track_4 (
.in({chany_top_in[2], chany_top_in[7], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_, chany_bottom_in[2]}),
.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
.out(chanx_right_out[2]));
mux_2level_tapbuf_size4 mux_right_track_6 (
.in({chany_top_in[4], chany_top_in[9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_, chany_bottom_in[4]}),
.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
.out(chanx_right_out[3]));
mux_2level_tapbuf_size4_mem mem_right_track_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_track_4 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));
mux_2level_tapbuf_size4_mem mem_right_track_6 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));
mux_2level_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[5], chany_bottom_in[5]}),
.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_2level_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[6], chany_bottom_in[6]}),
.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_2level_tapbuf_size2_mem mem_right_track_8 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));
mux_2level_tapbuf_size2_mem mem_right_track_10 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_2level_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));
mux_2level_tapbuf_size7 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], chanx_right_in[2], chanx_right_in[5], chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_2level_tapbuf_size7_0_sram[0:5]),
.sram_inv(mux_2level_tapbuf_size7_0_sram_inv[0:5]),
.out(chany_bottom_out[8]));
mux_2level_tapbuf_size7_mem mem_bottom_track_17 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_tapbuf_size7_0_sram[0:5]),
.mem_outb(mux_2level_tapbuf_size7_0_sram_inv[0:5]));
endmodule |
module logical_tile_clb_mode_default__fle(pReset,
prog_clk,
set,
reset,
clk,
fle_in,
fle_cin,
fle_clk,
ccff_head,
fle_out,
fle_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:3] fle_in;
//----- INPUT PORTS -----
input [0:0] fle_cin;
//----- INPUT PORTS -----
input [0:0] fle_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] fle_out;
//----- OUTPUT PORTS -----
output [0:0] fle_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fle_in;
wire [0:0] fle_cin;
wire [0:0] fle_clk;
wire [0:1] fle_out;
wire [0:0] fle_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fabric_in({direct_interc_3_out, direct_interc_4_out, direct_interc_5_out, direct_interc_6_out}),
.fabric_cin(direct_interc_7_out),
.fabric_clk(direct_interc_8_out),
.ccff_head(ccff_head),
.fabric_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0:1]),
.fabric_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[0]),
.out(fle_out[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_out[1]),
.out(fle_out[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_0_fabric_cout),
.out(fle_cout));
direct_interc direct_interc_3_ (
.in(fle_in[0]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(fle_in[1]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(fle_in[2]),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(fle_in[3]),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(fle_cin),
.out(direct_interc_7_out));
direct_interc direct_interc_8_ (
.in(fle_clk),
.out(direct_interc_8_out));
endmodule |
module grid_clb(pReset,
prog_clk,
set,
reset,
clk,
top_width_0_height_0_subtile_0__pin_cin_0_,
right_width_0_height_0_subtile_0__pin_I_0_,
right_width_0_height_0_subtile_0__pin_I_1_,
right_width_0_height_0_subtile_0__pin_I_2_,
right_width_0_height_0_subtile_0__pin_I_3_,
right_width_0_height_0_subtile_0__pin_I_4_,
right_width_0_height_0_subtile_0__pin_I_5_,
bottom_width_0_height_0_subtile_0__pin_I_6_,
bottom_width_0_height_0_subtile_0__pin_I_7_,
bottom_width_0_height_0_subtile_0__pin_I_8_,
bottom_width_0_height_0_subtile_0__pin_I_9_,
bottom_width_0_height_0_subtile_0__pin_I_10_,
bottom_width_0_height_0_subtile_0__pin_I_11_,
left_width_0_height_0_subtile_0__pin_clk_0_,
ccff_head,
right_width_0_height_0_subtile_0__pin_O_0_,
right_width_0_height_0_subtile_0__pin_O_1_,
right_width_0_height_0_subtile_0__pin_O_2_,
right_width_0_height_0_subtile_0__pin_O_3_,
bottom_width_0_height_0_subtile_0__pin_O_4_,
bottom_width_0_height_0_subtile_0__pin_O_5_,
bottom_width_0_height_0_subtile_0__pin_O_6_,
bottom_width_0_height_0_subtile_0__pin_O_7_,
bottom_width_0_height_0_subtile_0__pin_cout_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_cin_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_2_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_3_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_4_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_5_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_7_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_8_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_9_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_10_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_11_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_clk_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_1_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_2_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_3_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_4_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_5_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_6_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_7_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_cout_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.clb_I({right_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, right_width_0_height_0_subtile_0__pin_I_2_, right_width_0_height_0_subtile_0__pin_I_3_, right_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, bottom_width_0_height_0_subtile_0__pin_I_7_, bottom_width_0_height_0_subtile_0__pin_I_8_, bottom_width_0_height_0_subtile_0__pin_I_9_, bottom_width_0_height_0_subtile_0__pin_I_10_, bottom_width_0_height_0_subtile_0__pin_I_11_}),
.clb_cin(top_width_0_height_0_subtile_0__pin_cin_0_),
.clb_clk(left_width_0_height_0_subtile_0__pin_clk_0_),
.ccff_head(ccff_head),
.clb_O({right_width_0_height_0_subtile_0__pin_O_0_, right_width_0_height_0_subtile_0__pin_O_1_, right_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_, bottom_width_0_height_0_subtile_0__pin_O_4_, bottom_width_0_height_0_subtile_0__pin_O_5_, bottom_width_0_height_0_subtile_0__pin_O_6_, bottom_width_0_height_0_subtile_0__pin_O_7_}),
.clb_cout(bottom_width_0_height_0_subtile_0__pin_cout_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric(pReset,
prog_clk,
set,
reset,
clk,
fabric_in,
fabric_cin,
fabric_clk,
ccff_head,
fabric_out,
fabric_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:3] fabric_in;
//----- INPUT PORTS -----
input [0:0] fabric_cin;
//----- INPUT PORTS -----
input [0:0] fabric_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] fabric_out;
//----- OUTPUT PORTS -----
output [0:0] fabric_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fabric_in;
wire [0:0] fabric_cin;
wire [0:0] fabric_clk;
wire [0:1] fabric_out;
wire [0:0] fabric_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] direct_interc_8_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:0] mux_1level_tapbuf_size2_0_out;
wire [0:2] mux_1level_tapbuf_size2_0_sram;
wire [0:2] mux_1level_tapbuf_size2_0_sram_inv;
wire [0:0] mux_1level_tapbuf_size2_1_out;
wire [0:2] mux_1level_tapbuf_size2_1_sram;
wire [0:2] mux_1level_tapbuf_size2_1_sram_inv;
wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail;
wire [0:3] mux_1level_tapbuf_size3_0_sram;
wire [0:3] mux_1level_tapbuf_size3_0_sram_inv;
wire [0:3] mux_1level_tapbuf_size3_1_sram;
wire [0:3] mux_1level_tapbuf_size3_1_sram_inv;
wire [0:0] mux_1level_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_1level_tapbuf_size3_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.frac_logic_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
.ccff_head(ccff_head),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.set(set),
.reset(reset),
.clk(clk),
.ff_D(mux_1level_tapbuf_size2_0_out),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q),
.ff_clk(direct_interc_5_out));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.set(set),
.reset(reset),
.clk(clk),
.ff_D(mux_1level_tapbuf_size2_1_out),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q),
.ff_clk(direct_interc_6_out));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0 (
.adder_a(direct_interc_7_out),
.adder_b(direct_interc_8_out),
.adder_cin(direct_interc_9_out),
.adder_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout),
.adder_sumout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout));
mux_1level_tapbuf_size3 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
.sram(mux_1level_tapbuf_size3_0_sram[0:3]),
.sram_inv(mux_1level_tapbuf_size3_0_sram_inv[0:3]),
.out(fabric_out[0]));
mux_1level_tapbuf_size3 mux_fabric_out_1 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]}),
.sram(mux_1level_tapbuf_size3_1_sram[0:3]),
.sram_inv(mux_1level_tapbuf_size3_1_sram_inv[0:3]),
.out(fabric_out[1]));
mux_1level_tapbuf_size3_mem mem_fabric_out_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail),
.ccff_tail(mux_1level_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_1level_tapbuf_size3_0_sram[0:3]),
.mem_outb(mux_1level_tapbuf_size3_0_sram_inv[0:3]));
mux_1level_tapbuf_size3_mem mem_fabric_out_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_1level_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_1level_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_1level_tapbuf_size3_1_sram[0:3]),
.mem_outb(mux_1level_tapbuf_size3_1_sram_inv[0:3]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout),
.out(fabric_cout));
direct_interc direct_interc_1_ (
.in(fabric_in[0]),
.out(direct_interc_1_out));
direct_interc direct_interc_2_ (
.in(fabric_in[1]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(fabric_in[2]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(fabric_in[3]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(fabric_clk),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(fabric_clk),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]),
.out(direct_interc_7_out));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]),
.out(direct_interc_8_out));
direct_interc direct_interc_9_ (
.in(fabric_cin),
.out(direct_interc_9_out));
mux_1level_tapbuf_size2 mux_ff_0_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_cout}),
.sram(mux_1level_tapbuf_size2_0_sram[0:2]),
.sram_inv(mux_1level_tapbuf_size2_0_sram_inv[0:2]),
.out(mux_1level_tapbuf_size2_0_out));
mux_1level_tapbuf_size2 mux_ff_1_D_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder_0_adder_sumout}),
.sram(mux_1level_tapbuf_size2_1_sram[0:2]),
.sram_inv(mux_1level_tapbuf_size2_1_sram_inv[0:2]),
.out(mux_1level_tapbuf_size2_1_out));
mux_1level_tapbuf_size2_mem mem_ff_0_D_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_1level_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_1level_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_1level_tapbuf_size2_0_sram[0:2]),
.mem_outb(mux_1level_tapbuf_size2_0_sram_inv[0:2]));
mux_1level_tapbuf_size2_mem mem_ff_1_D_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_1level_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_1level_tapbuf_size2_1_sram[0:2]),
.mem_outb(mux_1level_tapbuf_size2_1_sram_inv[0:2]));
endmodule |
module logical_tile_clb_mode_clb_(pReset,
prog_clk,
set,
reset,
clk,
clb_I,
clb_cin,
clb_clk,
ccff_head,
clb_O,
clb_cout,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:11] clb_I;
//----- INPUT PORTS -----
input [0:0] clb_cin;
//----- INPUT PORTS -----
input [0:0] clb_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:7] clb_O;
//----- OUTPUT PORTS -----
output [0:0] clb_cout;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:11] clb_I;
wire [0:0] clb_cin;
wire [0:0] clb_clk;
wire [0:7] clb_O;
wire [0:0] clb_cout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_11_out;
wire [0:0] direct_interc_12_out;
wire [0:0] direct_interc_13_out;
wire [0:0] direct_interc_14_out;
wire [0:0] direct_interc_15_out;
wire [0:0] direct_interc_16_out;
wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_cout;
wire [0:1] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] mux_2level_size20_0_out;
wire [0:9] mux_2level_size20_0_sram;
wire [0:9] mux_2level_size20_0_sram_inv;
wire [0:0] mux_2level_size20_10_out;
wire [0:9] mux_2level_size20_10_sram;
wire [0:9] mux_2level_size20_10_sram_inv;
wire [0:0] mux_2level_size20_11_out;
wire [0:9] mux_2level_size20_11_sram;
wire [0:9] mux_2level_size20_11_sram_inv;
wire [0:0] mux_2level_size20_12_out;
wire [0:9] mux_2level_size20_12_sram;
wire [0:9] mux_2level_size20_12_sram_inv;
wire [0:0] mux_2level_size20_13_out;
wire [0:9] mux_2level_size20_13_sram;
wire [0:9] mux_2level_size20_13_sram_inv;
wire [0:0] mux_2level_size20_14_out;
wire [0:9] mux_2level_size20_14_sram;
wire [0:9] mux_2level_size20_14_sram_inv;
wire [0:0] mux_2level_size20_15_out;
wire [0:9] mux_2level_size20_15_sram;
wire [0:9] mux_2level_size20_15_sram_inv;
wire [0:0] mux_2level_size20_1_out;
wire [0:9] mux_2level_size20_1_sram;
wire [0:9] mux_2level_size20_1_sram_inv;
wire [0:0] mux_2level_size20_2_out;
wire [0:9] mux_2level_size20_2_sram;
wire [0:9] mux_2level_size20_2_sram_inv;
wire [0:0] mux_2level_size20_3_out;
wire [0:9] mux_2level_size20_3_sram;
wire [0:9] mux_2level_size20_3_sram_inv;
wire [0:0] mux_2level_size20_4_out;
wire [0:9] mux_2level_size20_4_sram;
wire [0:9] mux_2level_size20_4_sram_inv;
wire [0:0] mux_2level_size20_5_out;
wire [0:9] mux_2level_size20_5_sram;
wire [0:9] mux_2level_size20_5_sram_inv;
wire [0:0] mux_2level_size20_6_out;
wire [0:9] mux_2level_size20_6_sram;
wire [0:9] mux_2level_size20_6_sram_inv;
wire [0:0] mux_2level_size20_7_out;
wire [0:9] mux_2level_size20_7_sram;
wire [0:9] mux_2level_size20_7_sram_inv;
wire [0:0] mux_2level_size20_8_out;
wire [0:9] mux_2level_size20_8_sram;
wire [0:9] mux_2level_size20_8_sram_inv;
wire [0:0] mux_2level_size20_9_out;
wire [0:9] mux_2level_size20_9_sram;
wire [0:9] mux_2level_size20_9_sram_inv;
wire [0:0] mux_2level_size20_mem_0_ccff_tail;
wire [0:0] mux_2level_size20_mem_10_ccff_tail;
wire [0:0] mux_2level_size20_mem_11_ccff_tail;
wire [0:0] mux_2level_size20_mem_12_ccff_tail;
wire [0:0] mux_2level_size20_mem_13_ccff_tail;
wire [0:0] mux_2level_size20_mem_14_ccff_tail;
wire [0:0] mux_2level_size20_mem_1_ccff_tail;
wire [0:0] mux_2level_size20_mem_2_ccff_tail;
wire [0:0] mux_2level_size20_mem_3_ccff_tail;
wire [0:0] mux_2level_size20_mem_4_ccff_tail;
wire [0:0] mux_2level_size20_mem_5_ccff_tail;
wire [0:0] mux_2level_size20_mem_6_ccff_tail;
wire [0:0] mux_2level_size20_mem_7_ccff_tail;
wire [0:0] mux_2level_size20_mem_8_ccff_tail;
wire [0:0] mux_2level_size20_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_2level_size20_0_out, mux_2level_size20_1_out, mux_2level_size20_2_out, mux_2level_size20_3_out}),
.fle_cin(direct_interc_9_out),
.fle_clk(direct_interc_10_out),
.ccff_head(ccff_head),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out[0:1]),
.fle_cout(logical_tile_clb_mode_default__fle_0_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_2level_size20_4_out, mux_2level_size20_5_out, mux_2level_size20_6_out, mux_2level_size20_7_out}),
.fle_cin(direct_interc_11_out),
.fle_clk(direct_interc_12_out),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out[0:1]),
.fle_cout(logical_tile_clb_mode_default__fle_1_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_2level_size20_8_out, mux_2level_size20_9_out, mux_2level_size20_10_out, mux_2level_size20_11_out}),
.fle_cin(direct_interc_13_out),
.fle_clk(direct_interc_14_out),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out[0:1]),
.fle_cout(logical_tile_clb_mode_default__fle_2_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_2level_size20_12_out, mux_2level_size20_13_out, mux_2level_size20_14_out, mux_2level_size20_15_out}),
.fle_cin(direct_interc_15_out),
.fle_clk(direct_interc_16_out),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out[0:1]),
.fle_cout(logical_tile_clb_mode_default__fle_3_fle_cout),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[0]),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[0]),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[0]),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[0]),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out[1]),
.out(clb_O[4]));
direct_interc direct_interc_5_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out[1]),
.out(clb_O[5]));
direct_interc direct_interc_6_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out[1]),
.out(clb_O[6]));
direct_interc direct_interc_7_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out[1]),
.out(clb_O[7]));
direct_interc direct_interc_8_ (
.in(logical_tile_clb_mode_default__fle_3_fle_cout),
.out(clb_cout));
direct_interc direct_interc_9_ (
.in(clb_cin),
.out(direct_interc_9_out));
direct_interc direct_interc_10_ (
.in(clb_clk),
.out(direct_interc_10_out));
direct_interc direct_interc_11_ (
.in(logical_tile_clb_mode_default__fle_0_fle_cout),
.out(direct_interc_11_out));
direct_interc direct_interc_12_ (
.in(clb_clk),
.out(direct_interc_12_out));
direct_interc direct_interc_13_ (
.in(logical_tile_clb_mode_default__fle_1_fle_cout),
.out(direct_interc_13_out));
direct_interc direct_interc_14_ (
.in(clb_clk),
.out(direct_interc_14_out));
direct_interc direct_interc_15_ (
.in(logical_tile_clb_mode_default__fle_2_fle_cout),
.out(direct_interc_15_out));
direct_interc direct_interc_16_ (
.in(clb_clk),
.out(direct_interc_16_out));
mux_2level_size20 mux_fle_0_in_0 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_0_sram[0:9]),
.sram_inv(mux_2level_size20_0_sram_inv[0:9]),
.out(mux_2level_size20_0_out));
mux_2level_size20 mux_fle_0_in_1 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_1_sram[0:9]),
.sram_inv(mux_2level_size20_1_sram_inv[0:9]),
.out(mux_2level_size20_1_out));
mux_2level_size20 mux_fle_0_in_2 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_2_sram[0:9]),
.sram_inv(mux_2level_size20_2_sram_inv[0:9]),
.out(mux_2level_size20_2_out));
mux_2level_size20 mux_fle_0_in_3 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_3_sram[0:9]),
.sram_inv(mux_2level_size20_3_sram_inv[0:9]),
.out(mux_2level_size20_3_out));
mux_2level_size20 mux_fle_1_in_0 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_4_sram[0:9]),
.sram_inv(mux_2level_size20_4_sram_inv[0:9]),
.out(mux_2level_size20_4_out));
mux_2level_size20 mux_fle_1_in_1 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_5_sram[0:9]),
.sram_inv(mux_2level_size20_5_sram_inv[0:9]),
.out(mux_2level_size20_5_out));
mux_2level_size20 mux_fle_1_in_2 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_6_sram[0:9]),
.sram_inv(mux_2level_size20_6_sram_inv[0:9]),
.out(mux_2level_size20_6_out));
mux_2level_size20 mux_fle_1_in_3 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_7_sram[0:9]),
.sram_inv(mux_2level_size20_7_sram_inv[0:9]),
.out(mux_2level_size20_7_out));
mux_2level_size20 mux_fle_2_in_0 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_8_sram[0:9]),
.sram_inv(mux_2level_size20_8_sram_inv[0:9]),
.out(mux_2level_size20_8_out));
mux_2level_size20 mux_fle_2_in_1 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_9_sram[0:9]),
.sram_inv(mux_2level_size20_9_sram_inv[0:9]),
.out(mux_2level_size20_9_out));
mux_2level_size20 mux_fle_2_in_2 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_10_sram[0:9]),
.sram_inv(mux_2level_size20_10_sram_inv[0:9]),
.out(mux_2level_size20_10_out));
mux_2level_size20 mux_fle_2_in_3 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_11_sram[0:9]),
.sram_inv(mux_2level_size20_11_sram_inv[0:9]),
.out(mux_2level_size20_11_out));
mux_2level_size20 mux_fle_3_in_0 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_12_sram[0:9]),
.sram_inv(mux_2level_size20_12_sram_inv[0:9]),
.out(mux_2level_size20_12_out));
mux_2level_size20 mux_fle_3_in_1 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_13_sram[0:9]),
.sram_inv(mux_2level_size20_13_sram_inv[0:9]),
.out(mux_2level_size20_13_out));
mux_2level_size20 mux_fle_3_in_2 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_14_sram[0:9]),
.sram_inv(mux_2level_size20_14_sram_inv[0:9]),
.out(mux_2level_size20_14_out));
mux_2level_size20 mux_fle_3_in_3 (
.in({clb_I[0:11], logical_tile_clb_mode_default__fle_0_fle_out[0:1], logical_tile_clb_mode_default__fle_1_fle_out[0:1], logical_tile_clb_mode_default__fle_2_fle_out[0:1], logical_tile_clb_mode_default__fle_3_fle_out[0:1]}),
.sram(mux_2level_size20_15_sram[0:9]),
.sram_inv(mux_2level_size20_15_sram_inv[0:9]),
.out(mux_2level_size20_15_out));
mux_2level_size20_mem mem_fle_0_in_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
.ccff_tail(mux_2level_size20_mem_0_ccff_tail),
.mem_out(mux_2level_size20_0_sram[0:9]),
.mem_outb(mux_2level_size20_0_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_0_in_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_0_ccff_tail),
.ccff_tail(mux_2level_size20_mem_1_ccff_tail),
.mem_out(mux_2level_size20_1_sram[0:9]),
.mem_outb(mux_2level_size20_1_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_0_in_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_1_ccff_tail),
.ccff_tail(mux_2level_size20_mem_2_ccff_tail),
.mem_out(mux_2level_size20_2_sram[0:9]),
.mem_outb(mux_2level_size20_2_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_0_in_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_2_ccff_tail),
.ccff_tail(mux_2level_size20_mem_3_ccff_tail),
.mem_out(mux_2level_size20_3_sram[0:9]),
.mem_outb(mux_2level_size20_3_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_1_in_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_3_ccff_tail),
.ccff_tail(mux_2level_size20_mem_4_ccff_tail),
.mem_out(mux_2level_size20_4_sram[0:9]),
.mem_outb(mux_2level_size20_4_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_1_in_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_4_ccff_tail),
.ccff_tail(mux_2level_size20_mem_5_ccff_tail),
.mem_out(mux_2level_size20_5_sram[0:9]),
.mem_outb(mux_2level_size20_5_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_1_in_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_5_ccff_tail),
.ccff_tail(mux_2level_size20_mem_6_ccff_tail),
.mem_out(mux_2level_size20_6_sram[0:9]),
.mem_outb(mux_2level_size20_6_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_1_in_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_6_ccff_tail),
.ccff_tail(mux_2level_size20_mem_7_ccff_tail),
.mem_out(mux_2level_size20_7_sram[0:9]),
.mem_outb(mux_2level_size20_7_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_2_in_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_7_ccff_tail),
.ccff_tail(mux_2level_size20_mem_8_ccff_tail),
.mem_out(mux_2level_size20_8_sram[0:9]),
.mem_outb(mux_2level_size20_8_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_2_in_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_8_ccff_tail),
.ccff_tail(mux_2level_size20_mem_9_ccff_tail),
.mem_out(mux_2level_size20_9_sram[0:9]),
.mem_outb(mux_2level_size20_9_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_2_in_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_9_ccff_tail),
.ccff_tail(mux_2level_size20_mem_10_ccff_tail),
.mem_out(mux_2level_size20_10_sram[0:9]),
.mem_outb(mux_2level_size20_10_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_2_in_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_10_ccff_tail),
.ccff_tail(mux_2level_size20_mem_11_ccff_tail),
.mem_out(mux_2level_size20_11_sram[0:9]),
.mem_outb(mux_2level_size20_11_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_3_in_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_11_ccff_tail),
.ccff_tail(mux_2level_size20_mem_12_ccff_tail),
.mem_out(mux_2level_size20_12_sram[0:9]),
.mem_outb(mux_2level_size20_12_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_3_in_1 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_12_ccff_tail),
.ccff_tail(mux_2level_size20_mem_13_ccff_tail),
.mem_out(mux_2level_size20_13_sram[0:9]),
.mem_outb(mux_2level_size20_13_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_3_in_2 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_13_ccff_tail),
.ccff_tail(mux_2level_size20_mem_14_ccff_tail),
.mem_out(mux_2level_size20_14_sram[0:9]),
.mem_outb(mux_2level_size20_14_sram_inv[0:9]));
mux_2level_size20_mem mem_fle_3_in_3 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(mux_2level_size20_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_2level_size20_15_sram[0:9]),
.mem_outb(mux_2level_size20_15_sram_inv[0:9]));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__adder(adder_a,
adder_b,
adder_cin,
adder_cout,
adder_sumout);
//----- INPUT PORTS -----
input [0:0] adder_a;
//----- INPUT PORTS -----
input [0:0] adder_b;
//----- INPUT PORTS -----
input [0:0] adder_cin;
//----- OUTPUT PORTS -----
output [0:0] adder_cout;
//----- OUTPUT PORTS -----
output [0:0] adder_sumout;
//----- BEGIN wire-connection ports -----
wire [0:0] adder_a;
wire [0:0] adder_b;
wire [0:0] adder_cin;
wire [0:0] adder_cout;
wire [0:0] adder_sumout;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
ADDF ADDF_0_ (
.A(adder_a),
.B(adder_b),
.CI(adder_cin),
.SUM(adder_sumout),
.CO(adder_cout));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4(pReset,
prog_clk,
frac_lut4_in,
ccff_head,
frac_lut4_lut3_out,
frac_lut4_lut4_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_lut4_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_lut4_lut3_out;
//----- OUTPUT PORTS -----
output [0:0] frac_lut4_lut4_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_lut4_in;
wire [0:1] frac_lut4_lut3_out;
wire [0:0] frac_lut4_lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] frac_lut4_0_mode;
wire [0:0] frac_lut4_0_mode_inv;
wire [0:15] frac_lut4_0_sram;
wire [0:15] frac_lut4_0_sram_inv;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
frac_lut4 frac_lut4_0_ (
.in(frac_lut4_in[0:3]),
.sram(frac_lut4_0_sram[0:15]),
.sram_inv(frac_lut4_0_sram_inv[0:15]),
.mode(frac_lut4_0_mode),
.mode_inv(frac_lut4_0_mode_inv),
.lut3_out(frac_lut4_lut3_out[0:1]),
.lut4_out(frac_lut4_lut4_out));
frac_lut4_DFFR_mem frac_lut4_DFFR_mem (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out({frac_lut4_0_sram[0:15], frac_lut4_0_mode}),
.mem_outb({frac_lut4_0_sram_inv[0:15], frac_lut4_0_mode_inv}));
endmodule |
module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic(pReset,
prog_clk,
frac_logic_in,
ccff_head,
frac_logic_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] pReset;
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] frac_logic_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:1] frac_logic_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] frac_logic_in;
wire [0:1] frac_logic_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out;
wire [0:2] mux_1level_tapbuf_size2_0_sram;
wire [0:2] mux_1level_tapbuf_size2_0_sram_inv;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.frac_lut4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
.ccff_head(ccff_head),
.frac_lut4_lut3_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0:1]),
.frac_lut4_lut4_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail));
mux_1level_tapbuf_size2 mux_frac_logic_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out, logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]}),
.sram(mux_1level_tapbuf_size2_0_sram[0:2]),
.sram_inv(mux_1level_tapbuf_size2_0_sram_inv[0:2]),
.out(frac_logic_out[0]));
mux_1level_tapbuf_size2_mem mem_frac_logic_out_0 (
.pReset(pReset),
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_1level_tapbuf_size2_0_sram[0:2]),
.mem_outb(mux_1level_tapbuf_size2_0_sram_inv[0:2]));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[1]),
.out(frac_logic_out[1]));
direct_interc direct_interc_1_ (
.in(frac_logic_in[0]),
.out(direct_interc_1_out));
direct_interc direct_interc_2_ (
.in(frac_logic_in[1]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(frac_logic_in[2]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(frac_logic_in[3]),
.out(direct_interc_4_out));
endmodule |
module frac_lut4(in,
sram,
sram_inv,
mode,
mode_inv,
lut3_out,
lut4_out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:15] sram;
//----- INPUT PORTS -----
input [0:15] sram_inv;
//----- INPUT PORTS -----
input [0:0] mode;
//----- INPUT PORTS -----
input [0:0] mode_inv;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] OR2_0_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
OR2 OR2_0_ (
.a(mode),
.b(in[3]),
.out(OR2_0_out));
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(OR2_0_out),
.out(INVTX1_3_out));
buf4 buf4_0_ (
.in(in[0]),
.out(buf4_0_out));
buf4 buf4_1_ (
.in(in[1]),
.out(buf4_1_out));
buf4 buf4_2_ (
.in(in[2]),
.out(buf4_2_out));
buf4 buf4_3_ (
.in(OR2_0_out),
.out(buf4_3_out));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out));
endmodule |
module mux_2level_tapbuf_basis_input3_mem3(in,
mem,
mem_inv,
out);
//----- INPUT PORTS -----
input [0:2] in;
//----- INPUT PORTS -----
input [0:2] mem;
//----- INPUT PORTS -----
input [0:2] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
TGATE TGATE_0_ (
.in(in[0]),
.sel(mem[0]),
.selb(mem_inv[0]),
.out(out));
TGATE TGATE_1_ (
.in(in[1]),
.sel(mem[1]),
.selb(mem_inv[1]),
.out(out));
TGATE TGATE_2_ (
.in(in[2]),
.sel(mem[2]),
.selb(mem_inv[2]),
.out(out));
endmodule |
module mux_2level_basis_input5_mem5(in,
mem,
mem_inv,
out);
//----- INPUT PORTS -----
input [0:4] in;
//----- INPUT PORTS -----
input [0:4] mem;
//----- INPUT PORTS -----
input [0:4] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
TGATE TGATE_0_ (
.in(in[0]),
.sel(mem[0]),
.selb(mem_inv[0]),
.out(out));
TGATE TGATE_1_ (
.in(in[1]),
.sel(mem[1]),
.selb(mem_inv[1]),
.out(out));
TGATE TGATE_2_ (
.in(in[2]),
.sel(mem[2]),
.selb(mem_inv[2]),
.out(out));
TGATE TGATE_3_ (
.in(in[3]),
.sel(mem[3]),
.selb(mem_inv[3]),
.out(out));
TGATE TGATE_4_ (
.in(in[4]),
.sel(mem[4]),
.selb(mem_inv[4]),
.out(out));
endmodule |
module DFFR(RST,
CK,
D,
Q,
QN);
//----- GLOBAL PORTS -----
input [0:0] RST;
//----- GLOBAL PORTS -----
input [0:0] CK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- OUTPUT PORTS -----
output [0:0] QN;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module ADDF(A,
B,
CI,
SUM,
CO);
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] B;
//----- INPUT PORTS -----
input [0:0] CI;
//----- OUTPUT PORTS -----
output [0:0] SUM;
//----- OUTPUT PORTS -----
output [0:0] CO;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module sb_4__4_(prog_clk,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
ccff_head,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chany_bottom_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chanx_left_in[0];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size2 mux_bottom_track_1 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size2 mux_bottom_track_3 (
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size2 mux_bottom_track_5 (
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size2 mux_bottom_track_7 (
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size2 mux_bottom_track_9 (
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size2 mux_bottom_track_11 (
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size2 mux_bottom_track_13 (
.in({bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size2 mux_bottom_track_15 (
.in({bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size2 mux_bottom_track_17 (
.in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size2 mux_left_track_1 (
.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size2 mux_left_track_3 (
.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size2 mux_left_track_5 (
.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size2 mux_left_track_7 (
.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size2 mux_left_track_9 (
.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size2 mux_left_track_11 (
.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size2 mux_left_track_13 (
.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size2 mux_left_track_15 (
.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size2 mux_left_track_17 (
.in({chany_bottom_in[7], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size2_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]));
endmodule |
module sb_1__0_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size5_0_sram;
wire [0:2] mux_tree_tapbuf_size5_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chanx_right_in[4];
// ----- Net sink id 2 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chanx_right_in[5];
// ----- Net sink id 2 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chanx_left_in[4];
// ----- Net sink id 2 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chanx_left_in[5];
// ----- Net sink id 2 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign chanx_left_out[5] = chany_top_out[2];
assign chanx_left_out[6] = chany_top_out[3];
assign chanx_right_out[5] = chany_top_out[7];
assign chanx_right_out[6] = chany_top_out[6];
// ----- END Local output short connections -----
mux_tree_tapbuf_size5 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_right_in[1], chanx_right_in[7], chanx_left_in[0], chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size5_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size5_0_sram_inv[0:2]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size5_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size5_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size5_0_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_top_track_2 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[2], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size3_mem mem_top_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size5_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_top_track_8 (
.in({chanx_right_in[6], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size2 mux_top_track_10 (
.in({chanx_right_in[8], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size2 mux_top_track_16 (
.in({chanx_left_in[2], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size2_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size4 mux_top_track_18 (
.in({chanx_right_in[0], chanx_right_in[3], chanx_left_in[1], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chany_top_out[9]));
mux_tree_tapbuf_size4_mem mem_top_track_18 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size9 mux_right_track_0 (
.in({chany_top_in[2], chany_top_in[5], chany_top_in[8], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size9 mux_right_track_8 (
.in({chany_top_in[0], chany_top_in[3], chany_top_in[6], chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size9_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_right_track_16 (
.in({chany_top_in[1], chany_top_in[4], chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size8 mux_left_track_9 (
.in({chany_top_in[2], chany_top_in[5], chany_top_in[8], chanx_right_in[1], chanx_right_in[5], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size8 mux_left_track_17 (
.in({chany_top_in[1], chany_top_in[4], chany_top_in[7], chanx_right_in[2], chanx_right_in[6], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size8_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]));
mux_tree_tapbuf_size10 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3], chany_top_in[6], chany_top_in[9], chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size10_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
endmodule |
module sb_4__1_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
ccff_head,
chany_top_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_2_sram;
wire [0:3] mux_tree_tapbuf_size8_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 27 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size10 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8], chanx_left_in[0], chanx_left_in[3], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size10_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_top_track_8 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[1], chany_bottom_in[5], chanx_left_in[2], chanx_left_in[5], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size8 mux_top_track_16 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[2], chany_bottom_in[6], chanx_left_in[1], chanx_left_in[4], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size8 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[2], chanx_left_in[5], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size8_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_2_sram_inv[0:3]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size8_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]));
mux_tree_tapbuf_size9 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[1], chanx_left_in[4], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size9 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[0], chanx_left_in[3], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size9_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]));
mux_tree_tapbuf_size3 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size3 mux_left_track_3 (
.in({chany_bottom_in[0], chany_bottom_in[3], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size3_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_left_track_5 (
.in({chany_bottom_in[1], chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size2 mux_left_track_7 (
.in({chany_bottom_in[2], chany_bottom_in[9]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size2 mux_left_track_9 (
.in({chany_top_in[8], chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size2 mux_left_track_11 (
.in({chany_top_in[6], chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size2 mux_left_track_13 (
.in({chany_top_in[5], chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size2 mux_left_track_15 (
.in({chany_top_in[4], chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size2 mux_left_track_17 (
.in({chany_top_in[2], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size2 mux_left_track_19 (
.in({chany_top_in[1], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_tree_tapbuf_size2_mem mem_left_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
endmodule |
module sb_1__4_(prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
ccff_head,
chanx_right_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_3_sram;
wire [0:3] mux_tree_tapbuf_size9_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size9 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[1], chany_bottom_in[4], chany_bottom_in[7], chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size9 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[9], chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size9 mux_left_track_1 (
.in({chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], chany_bottom_in[2], chany_bottom_in[5], chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size9 mux_left_track_9 (
.in({chanx_right_in[1], chanx_right_in[5], chany_bottom_in[0], chany_bottom_in[3], chany_bottom_in[6], chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size9_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_3_sram_inv[0:3]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size9_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_3_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_right_track_16 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[2], chany_bottom_in[5], chany_bottom_in[8], chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size8 mux_left_track_17 (
.in({chanx_right_in[2], chanx_right_in[6], chany_bottom_in[1], chany_bottom_in[4], chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size8_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size3 mux_bottom_track_1 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[1], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size3 mux_bottom_track_3 (
.in({bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[2], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_bottom_track_5 (
.in({chanx_right_in[8], chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size2 mux_bottom_track_7 (
.in({chanx_right_in[6], chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size2 mux_bottom_track_9 (
.in({chanx_right_in[5], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size2 mux_bottom_track_11 (
.in({chanx_right_in[4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size2 mux_bottom_track_13 (
.in({chanx_right_in[2], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size2 mux_bottom_track_15 (
.in({chanx_right_in[1], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size2 mux_bottom_track_17 (
.in({chanx_right_in[0], chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size2 mux_bottom_track_19 (
.in({chanx_left_in[0], chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_bottom_out[9]));
mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
endmodule |
module sb_0__4_(prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chany_bottom_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size2 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size2 mux_right_track_2 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size2 mux_right_track_4 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size2 mux_right_track_6 (
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size2 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size2 mux_right_track_10 (
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[3]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size2 mux_right_track_12 (
.in({right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[2]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size2 mux_right_track_14 (
.in({right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[1]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0]}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2 mux_bottom_track_1 (
.in({chanx_right_in[8], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size2 mux_bottom_track_3 (
.in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size2 mux_bottom_track_5 (
.in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size2 mux_bottom_track_7 (
.in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size2 mux_bottom_track_9 (
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size2 mux_bottom_track_11 (
.in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size2 mux_bottom_track_13 (
.in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size2 mux_bottom_track_15 (
.in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size2 mux_bottom_track_17 (
.in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size2_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]));
endmodule |
module cbx_1__4_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_7_sram;
wire [0:2] mux_tree_tapbuf_size4_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_8_sram;
wire [0:2] mux_tree_tapbuf_size4_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_9_sram;
wire [0:2] mux_tree_tapbuf_size4_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_3 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_4 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_5 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_6 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_bottom_ipin_7 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_7_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_0 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size4_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_8_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_));
mux_tree_tapbuf_size4 mux_top_ipin_1 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size4_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_9_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_7_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_8_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_9_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_top_ipin_2 (
.in({chanx_left_in[0], chanx_right_in[0]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_));
mux_tree_tapbuf_size2_mem mem_top_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_9_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
endmodule |
module cby_0__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_7_sram;
wire [0:2] mux_tree_tapbuf_size4_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_8_sram;
wire [0:2] mux_tree_tapbuf_size4_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));
mux_tree_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_1 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_2 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_3 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_4 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_5 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_6 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size4_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_7_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_7 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size4_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_8_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size4_mem mem_left_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_7_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size4_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_8_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_left_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));
mux_tree_tapbuf_size2_mem mem_left_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
endmodule |
module cbx_1__0_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_7_sram;
wire [0:2] mux_tree_tapbuf_size4_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_8_sram;
wire [0:2] mux_tree_tapbuf_size4_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_9_sram;
wire [0:2] mux_tree_tapbuf_size4_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));
mux_tree_tapbuf_size4 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));
mux_tree_tapbuf_size4 mux_top_ipin_0 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_1 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_2 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_3 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[6], chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_4 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_5 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size4_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_7_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_6 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size4_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_8_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_top_ipin_7 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_9_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_7_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_8_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size4_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_9_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
mux_tree_tapbuf_size2_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
endmodule |
module sb_0__0_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chanx_right_in[0];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size2 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size2 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size2 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size2 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[4]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size2 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size2 mux_top_track_10 (
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size2 mux_top_track_12 (
.in({top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size2 mux_top_track_14 (
.in({top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size2 mux_top_track_16 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size2 mux_right_track_0 (
.in({chany_top_in[9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size2 mux_right_track_2 (
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size2 mux_right_track_4 (
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size2 mux_right_track_6 (
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size2 mux_right_track_12 (
.in({chany_top_in[5], right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size2 mux_right_track_14 (
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]));
endmodule |
module sb_1__1_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
ccff_head,
chany_top_out,
chanx_right_out,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:3] mux_tree_tapbuf_size10_0_sram;
wire [0:3] mux_tree_tapbuf_size10_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_1_sram;
wire [0:3] mux_tree_tapbuf_size10_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_2_sram;
wire [0:3] mux_tree_tapbuf_size10_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size10_3_sram;
wire [0:3] mux_tree_tapbuf_size10_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail;
wire [0:3] mux_tree_tapbuf_size11_0_sram;
wire [0:3] mux_tree_tapbuf_size11_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size11_1_sram;
wire [0:3] mux_tree_tapbuf_size11_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size11_2_sram;
wire [0:3] mux_tree_tapbuf_size11_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[1] = chanx_right_in[0];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[2] = chanx_right_in[1];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[3] = chanx_right_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[5] = chanx_right_in[4];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[6] = chanx_right_in[5];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_left_out[7] = chanx_right_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 3 -----
assign chanx_left_out[9] = chanx_right_in[8];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 26 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 28 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 30 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[1] = chanx_left_in[0];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[2] = chanx_left_in[1];
// ----- Local connection due to Wire 38 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[3] = chanx_left_in[2];
// ----- Local connection due to Wire 40 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[5] = chanx_left_in[4];
// ----- Local connection due to Wire 41 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[6] = chanx_left_in[5];
// ----- Local connection due to Wire 42 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chanx_right_out[7] = chanx_left_in[6];
// ----- Local connection due to Wire 44 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chanx_right_out[9] = chanx_left_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size11 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_right_in[1], chanx_right_in[5], chanx_right_in[7], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8], chanx_left_in[0], chanx_left_in[3:4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size11_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size11_0_sram_inv[0:3]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size11 mux_right_track_8 (
.in({chany_top_in[0], chany_top_in[3:4], chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[0], chany_bottom_in[3:4], chany_bottom_in[8], chanx_left_in[1], chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size11_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size11_1_sram_inv[0:3]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size11 mux_left_track_1 (
.in({chany_top_in[0], chany_top_in[3:4], chany_top_in[8], chanx_right_in[0], chanx_right_in[4], chanx_right_in[8], chany_bottom_in[2], chany_bottom_in[6], chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_}),
.sram(mux_tree_tapbuf_size11_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size11_2_sram_inv[0:3]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size11_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size11_0_sram_inv[0:3]));
mux_tree_tapbuf_size11_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size11_1_sram_inv[0:3]));
mux_tree_tapbuf_size11_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size11_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size11_2_sram_inv[0:3]));
mux_tree_tapbuf_size9 mux_top_track_8 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[2], chanx_right_in[6], chanx_right_in[9], chany_bottom_in[1], chany_bottom_in[5], chanx_left_in[2], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size9 mux_top_track_16 (
.in({chanx_right_in[0], chanx_right_in[3:4], chanx_right_in[8], chany_bottom_in[2], chany_bottom_in[6], chanx_left_in[1], chanx_left_in[5], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size9 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], chanx_right_in[2], chanx_right_in[6], chanx_right_in[9], chanx_left_in[0], chanx_left_in[3:4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size9_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]));
mux_tree_tapbuf_size10 mux_right_track_0 (
.in({chany_top_in[2], chany_top_in[6], chany_top_in[9], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[7], chanx_left_in[0], chanx_left_in[4], chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size10_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_0_sram_inv[0:3]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size10 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], chanx_right_in[1], chanx_right_in[5], chanx_right_in[7], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_left_in[1], chanx_left_in[5], chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size10_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_1_sram_inv[0:3]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size10 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], chanx_right_in[0], chanx_right_in[3:4], chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[2], chanx_left_in[6], chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size10_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_2_sram_inv[0:3]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size10 mux_left_track_9 (
.in({chany_top_in[2], chany_top_in[6], chany_top_in[9], chanx_right_in[1], chanx_right_in[5], chany_bottom_in[0], chany_bottom_in[3:4], chany_bottom_in[8], left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size10_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size10_3_sram_inv[0:3]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size10_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]));
mux_tree_tapbuf_size10_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size10_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_right_track_16 (
.in({chany_top_in[1], chany_top_in[5], chany_top_in[7], chany_bottom_in[2], chany_bottom_in[6], chany_bottom_in[9], chanx_left_in[2], chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size8 mux_left_track_17 (
.in({chany_top_in[1], chany_top_in[5], chany_top_in[7], chanx_right_in[2], chanx_right_in[6], chany_bottom_in[1], chany_bottom_in[5], chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size8_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size11_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
endmodule |
module cby_4__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
left_grid_right_width_0_height_0_subtile_0__pin_I_9_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_7_sram;
wire [0:2] mux_tree_tapbuf_size4_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_8_sram;
wire [0:2] mux_tree_tapbuf_size4_8_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_2 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_3 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_4 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_6 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[6], chany_top_in[6]}),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_left_ipin_7 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size4_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_7_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size4_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_8_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
mux_tree_tapbuf_size4_mem mem_left_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_7_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_8_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_right_ipin_1 (
.in({chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
mux_tree_tapbuf_size2 mux_right_ipin_2 (
.in({chany_bottom_in[0], chany_top_in[0]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_));
mux_tree_tapbuf_size2_mem mem_right_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
endmodule |
module cbx_1__1_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));
mux_tree_tapbuf_size4 mux_bottom_ipin_2 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));
mux_tree_tapbuf_size4 mux_top_ipin_0 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_));
mux_tree_tapbuf_size4 mux_top_ipin_1 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_bottom_ipin_1 (
.in({chanx_left_in[1], chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
mux_tree_tapbuf_size2 mux_top_ipin_2 (
.in({chanx_left_in[5], chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_));
mux_tree_tapbuf_size2_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
endmodule |
module cby_1__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
left_grid_right_width_0_height_0_subtile_0__pin_I_9_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[5], chany_top_in[5]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));
mux_tree_tapbuf_size4 mux_right_ipin_0 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
mux_tree_tapbuf_size4_mem mem_left_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size2 mux_left_ipin_1 (
.in({chany_bottom_in[1], chany_top_in[1]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));
mux_tree_tapbuf_size2 mux_right_ipin_1 (
.in({chany_bottom_in[3], chany_top_in[3]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
mux_tree_tapbuf_size2 mux_right_ipin_2 (
.in({chany_bottom_in[4], chany_top_in[4]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_));
mux_tree_tapbuf_size2_mem mem_left_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
endmodule |
module sb_0__1_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:9] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:9] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:9] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:3] mux_tree_tapbuf_size8_0_sram;
wire [0:3] mux_tree_tapbuf_size8_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size8_1_sram;
wire [0:3] mux_tree_tapbuf_size8_1_sram_inv;
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail;
wire [0:3] mux_tree_tapbuf_size9_0_sram;
wire [0:3] mux_tree_tapbuf_size9_0_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_1_sram;
wire [0:3] mux_tree_tapbuf_size9_1_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_2_sram;
wire [0:3] mux_tree_tapbuf_size9_2_sram_inv;
wire [0:3] mux_tree_tapbuf_size9_3_sram;
wire [0:3] mux_tree_tapbuf_size9_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[1] = chany_top_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[2] = chany_top_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[3] = chany_top_in[2];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[5] = chany_top_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[6] = chany_top_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_bottom_out[7] = chany_top_in[6];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 2 -----
assign chany_bottom_out[9] = chany_top_in[8];
// ----- Local connection due to Wire 29 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0];
// ----- Local connection due to Wire 31 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[1] = chany_bottom_in[0];
// ----- Local connection due to Wire 32 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[1];
// ----- Local connection due to Wire 33 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[2];
// ----- Local connection due to Wire 35 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[5] = chany_bottom_in[4];
// ----- Local connection due to Wire 36 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[6] = chany_bottom_in[5];
// ----- Local connection due to Wire 37 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[6];
// ----- Local connection due to Wire 39 -----
// ----- Net source id 0 -----
// ----- Net sink id 1 -----
assign chany_top_out[9] = chany_bottom_in[8];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size9 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[1], chanx_right_in[4], chanx_right_in[7], chany_bottom_in[0], chany_bottom_in[4], chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size9_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_0_sram_inv[0:3]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size9 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[0], chanx_right_in[3], chanx_right_in[6], chanx_right_in[9], chany_bottom_in[2], chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size9_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_1_sram_inv[0:3]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size9 mux_bottom_track_1 (
.in({chany_top_in[0], chany_top_in[4], chany_top_in[8], chanx_right_in[1], chanx_right_in[4], chanx_right_in[7], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size9_2_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_2_sram_inv[0:3]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size9 mux_bottom_track_9 (
.in({chany_top_in[1], chany_top_in[5], chanx_right_in[0], chanx_right_in[3], chanx_right_in[6], chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size9_3_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size9_3_sram_inv[0:3]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size9_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_0_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_1_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_2_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_2_sram_inv[0:3]));
mux_tree_tapbuf_size9_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size9_3_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size9_3_sram_inv[0:3]));
mux_tree_tapbuf_size8 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[2], chanx_right_in[5], chanx_right_in[8], chany_bottom_in[1], chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size8_0_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_0_sram_inv[0:3]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size8 mux_bottom_track_17 (
.in({chany_top_in[2], chany_top_in[6], chanx_right_in[2], chanx_right_in[5], chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size8_1_sram[0:3]),
.sram_inv(mux_tree_tapbuf_size8_1_sram_inv[0:3]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size8_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size8_0_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]));
mux_tree_tapbuf_size8_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_3_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size8_1_sram[0:3]),
.mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]));
mux_tree_tapbuf_size3 mux_right_track_2 (
.in({chany_top_in[0], chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size3 mux_right_track_4 (
.in({chany_top_in[1], chany_top_in[7], chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size3 mux_right_track_6 (
.in({chany_top_in[2], chany_top_in[9], chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size3 mux_right_track_12 (
.in({chany_top_in[6], chany_bottom_in[2], chany_bottom_in[9]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size3 mux_right_track_14 (
.in({chany_top_in[8], chany_bottom_in[1], chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size3_mem mem_right_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size9_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_right_track_8 (
.in({chany_top_in[4], chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size2 mux_right_track_10 (
.in({chany_top_in[5], chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size2 mux_right_track_16 (
.in({chany_bottom_in[0], chany_bottom_in[3]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size2_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
endmodule |
module sb_4__0_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:9] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:9] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:9] chany_top_out;
//----- OUTPUT PORTS -----
output [0:9] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_10_sram;
wire [0:1] mux_tree_tapbuf_size2_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_11_sram;
wire [0:1] mux_tree_tapbuf_size2_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_12_sram;
wire [0:1] mux_tree_tapbuf_size2_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_13_sram;
wire [0:1] mux_tree_tapbuf_size2_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_14_sram;
wire [0:1] mux_tree_tapbuf_size2_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_15_sram;
wire [0:1] mux_tree_tapbuf_size2_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_16_sram;
wire [0:1] mux_tree_tapbuf_size2_16_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_17_sram;
wire [0:1] mux_tree_tapbuf_size2_17_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_7_sram;
wire [0:1] mux_tree_tapbuf_size2_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_8_sram;
wire [0:1] mux_tree_tapbuf_size2_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_9_sram;
wire [0:1] mux_tree_tapbuf_size2_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chany_top_in[1];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chanx_left_in[1];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size2 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size2 mux_top_track_2 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size2 mux_top_track_4 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size2 mux_top_track_6 (
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size2 mux_top_track_8 (
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size2 mux_top_track_10 (
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size2 mux_top_track_12 (
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size2 mux_top_track_14 (
.in({top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size2_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_7_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size2 mux_top_track_16 (
.in({top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size2_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_8_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size2 mux_left_track_1 (
.in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_}),
.sram(mux_tree_tapbuf_size2_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_9_sram_inv[0:1]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size2 mux_left_track_3 (
.in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_10_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size2 mux_left_track_5 (
.in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_11_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size2 mux_left_track_7 (
.in({chany_top_in[7], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_12_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size2 mux_left_track_9 (
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_13_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size2 mux_left_track_11 (
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_14_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size2 mux_left_track_13 (
.in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_15_sram_inv[0:1]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size2 mux_left_track_15 (
.in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_16_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_16_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size2 mux_left_track_17 (
.in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_17_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_17_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size2_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_7_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_8_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_9_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_10_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_11_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_12_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_13_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_14_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_15_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_15_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_16_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_16_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_16_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_17_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_17_sram_inv[0:1]));
endmodule |
module mux_tree_tapbuf_size10_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:3] mem_out;
//----- OUTPUT PORTS -----
output [0:3] mem_outb;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[3];
// ----- END Local output short connections -----
DFF DFF_0_ (
.CK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]),
.QN(mem_outb[0]));
DFF DFF_1_ (
.CK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]),
.QN(mem_outb[1]));
DFF DFF_2_ (
.CK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]),
.QN(mem_outb[2]));
DFF DFF_3_ (
.CK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]),
.QN(mem_outb[3]));
endmodule |
module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7,
out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15);
input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7;
input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7;
output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;
assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7};
assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7};
assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15};
assign out = a*b;
endmodule |
module top
(
input wire extclk,
inout wire [19:0] gpio_sensor,
output wire tmds_d0_p,
output wire tmds_d0_n,
output wire tmds_d1_p,
output wire tmds_d1_n,
output wire tmds_d2_p,
output wire tmds_d2_n,
output wire tmds_clk_p,
output wire tmds_clk_n,
output wire hram_r0_ck_p,
output wire hram_r0_ck_n,
output wire hram_r0_reset_n,
output wire hram_r0_cs_n,
inout wire hram_r0_rwds,
inout wire [7:0] hram_r0_dq,
output wire hram_r1_ck_p,
output wire hram_r1_ck_n,
output wire hram_r1_reset_n,
output wire hram_r1_cs_n,
inout wire hram_r1_rwds,
inout wire [7:0] hram_r1_dq,
inout wire cnfg_cs_n,
inout wire cnfg_mosi_miso_0,
inout wire cnfg_miso_miso_1,
inout wire cnfg_miso_2,
inout wire cnfg_miso_3,
output wire fx2_ifclk,
output wire av_clkin,
input wire fx2_pa0,
output wire fx2_pa1_led_act_y,
output wire fx2_pa2,
output wire fx2_pa3_led_act_r,
output wire fx2_pa4,
output wire fx2_pa5,
output wire fx2_pa6,
input wire fx2_pa7_hdmi_cec,
output wire [7:0] fx2_pb,
output wire [7:0] fx2_av_pd,
output wire fx2_rdy0_slrd,
output wire fx2_rdy1_slwr,
input wire fx2_ctl0_flaga,
input wire fx2_ctl1_flagb,
input wire fx2_ctl2_flagc,
output wire lcd_led_ctrl,
output wire lcd_spi_dat,
output wire lcd_spi_sck,
output wire lcd_spi_rst_n,
inout wire sdio_cmd,
inout wire sdio_clk,
inout wire [3:0] sdio_dat,
inout wire i2c_sda,
inout wire i2c_scl,
input wire i2c_irq_n,
output wire sensor_bias_boost_pwr_ena,
output wire sensor_core_pwr_ena,
output wire sensor_bias_pwr_ena,
output wire sensor_io_pwr_ena_n,
output wire sensor_bias_volt_sel,
output wire shtr_drive_ena,
output wire focus_drive_ena,
input wire focus_sensor_pulse,
input wire gpio_aux_spi_sck,
input wire gpio_aux_spi_cs_0,
input wire gpio_aux_spi_cs_1,
input wire gpio_aux_spi_miso,
input wire gpio_aux_spi_mosi,
input wire gpio_aux_i2c_sda,
input wire gpio_aux_i2c_scl,
inout wire ext_gpio_0_buf,
output wire ext_gpio_0_dir,
output wire ext_gpio_0_oc,
inout wire ext_gpio_1_buf,
output wire ext_gpio_1_dir,
output wire ext_gpio_1_oc,
input wire ext_gpi_buf,
output wire pwr_fd_clk,
output wire pwr_fd_dat,
input wire [3:0] btn
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam GPIO_DIR_INPUT = 1'b1,
GPIO_DIR_OUTPUT = 1'b0;
assign ext_gpio_0_buf = 1'bz;
assign ext_gpio_0_dir = GPIO_DIR_OUTPUT;
assign ext_gpio_0_oc = 1'b1;
assign ext_gpio_1_buf = 1'bz;
assign ext_gpio_1_dir = GPIO_DIR_OUTPUT;
assign ext_gpio_1_oc = 1'b1;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire IIC_scl_i;
wire IIC_scl_o;
wire IIC_scl_t;
wire IIC_sda_i;
wire IIC_sda_o;
wire IIC_sda_t;
IOBUF IIC_scl_iobuf
(
.I ( IIC_scl_o ),
.IO ( i2c_scl ),
.O ( IIC_scl_i ),
.T ( IIC_scl_t )
);
IOBUF IIC_sda_iobuf
(
.I ( IIC_sda_o ),
.IO ( i2c_sda ),
.O ( IIC_sda_i ),
.T ( IIC_sda_t )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire SPI_io0_i;
wire SPI_io0_o;
wire SPI_io0_t;
wire SPI_io1_i;
wire SPI_io1_o;
wire SPI_io1_t;
wire SPI_sck_i;
wire SPI_sck_o;
wire SPI_sck_t;
wire SPI_ss_i_0;
wire SPI_ss_o_0;
wire SPI_ss_t;
IOBUF SPI_io0_iobuf
(
.I ( SPI_io0_o ),
.IO ( sdio_cmd ),
.O ( SPI_io0_i ),
.T ( SPI_io0_t )
);
IOBUF SPI_io1_iobuf
(
.I ( SPI_io1_o ),
.IO ( sdio_dat[0] ),
.O ( SPI_io1_i ),
.T ( SPI_io1_t )
);
IOBUF SPI_sck_iobuf
(
.I ( SPI_sck_o ),
.IO ( sdio_clk ),
.O ( SPI_sck_i ),
.T ( SPI_sck_t )
);
IOBUF SPI_ss_iobuf_0
(
.I ( SPI_ss_o_0 ),
.IO ( sdio_dat[3] ),
.O ( SPI_ss_i_0 ),
.T ( SPI_ss_t )
);
assign sdio_dat[1] = 1'bz;
assign sdio_dat[2] = 1'bz;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire QSPI_ss_i;
wire QSPI_ss_o;
wire QSPI_ss_t;
wire QSPI_io0_i;
wire QSPI_io0_o;
wire QSPI_io0_t;
wire QSPI_io1_i;
wire QSPI_io1_o;
wire QSPI_io1_t;
wire QSPI_io2_i;
wire QSPI_io2_o;
wire QSPI_io2_t;
wire QSPI_io3_i;
wire QSPI_io3_o;
wire QSPI_io3_t;
IOBUF QSPI_ss_iobuf_0
(
.I ( QSPI_ss_o ),
.IO ( cnfg_cs_n ),
.O ( QSPI_ss_i ),
.T ( QSPI_ss_t )
);
IOBUF QSPI_io0_iobuf
(
.I ( QSPI_io0_o ),
.IO ( cnfg_mosi_miso_0 ),
.O ( QSPI_io0_i ),
.T ( QSPI_io0_t )
);
IOBUF QSPI_io1_iobuf
(
.I ( QSPI_io1_o ),
.IO ( cnfg_miso_miso_1 ),
.O ( QSPI_io1_i ),
.T ( QSPI_io1_t )
);
IOBUF QSPI_io2_iobuf
(
.I ( QSPI_io2_o ),
.IO ( cnfg_miso_2 ),
.O ( QSPI_io2_i ),
.T ( QSPI_io2_t )
);
IOBUF QSPI_io3_iobuf
(
.I (QSPI_io3_o ),
.IO (cnfg_miso_3 ),
.O (QSPI_io3_i ),
.T (QSPI_io3_t )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire sensor_bias;
wire sensor_clk_fwd;
wire sensor_cmd;
wire sensor_data_even;
wire sensor_data_odd;
wire sensor_ena;
assign gpio_sensor[0] = 1'bz;
assign gpio_sensor[1] = 1'bz;
assign gpio_sensor[2] = sensor_ena;
assign gpio_sensor[3] = 1'bz;
assign gpio_sensor[4] = 1'bz;
assign gpio_sensor[5] = sensor_bias;
assign gpio_sensor[6] = 1'bz;
assign gpio_sensor[7] = 1'bz;
assign gpio_sensor[8] = 1'bz;
assign gpio_sensor[9] = 1'bz;
assign gpio_sensor[10] = 1'bz;
assign gpio_sensor[11] = 1'bz;
assign gpio_sensor[12] = 1'bz;
assign gpio_sensor[13] = sensor_clk_fwd;
assign gpio_sensor[14] = 1'bz;
assign gpio_sensor[15] = 1'bz;
assign gpio_sensor[16] = sensor_cmd;
assign gpio_sensor[17] = 1'bz;
assign gpio_sensor[18] = 1'bz;
assign gpio_sensor[19] = 1'bz;
assign sensor_data_odd = gpio_sensor[3];
assign sensor_data_even = gpio_sensor[15];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
SoC SoC_i
(
.extclk ( extclk ),
.fd_clk ( pwr_fd_clk ),
.fd_dat ( pwr_fd_dat ),
.sensor_bias_boost_pwr_ena ( sensor_bias_boost_pwr_ena ),
.sensor_core_pwr_ena ( sensor_core_pwr_ena ),
.sensor_bias_pwr_ena ( sensor_bias_pwr_ena ),
.sensor_io_pwr_ena_n ( sensor_io_pwr_ena_n ),
.sensor_bias_volt_sel ( sensor_bias_volt_sel ),
.shtr_drive_ena ( shtr_drive_ena ),
.focus_drive_ena ( focus_drive_ena ),
.focus_sensor_pulse ( focus_sensor_pulse ),
.act_led ( {fx2_pa3_led_act_r, fx2_pa1_led_act_y} ),
.btn_0 ( btn[0] ),
.btn_1 ( btn[1] ),
.btn_2 ( btn[2] ),
.btn_3 ( btn[3] ),
.lcd_led_ctrl ( lcd_led_ctrl ),
.lcd_resetn ( lcd_spi_rst_n ),
.lcd_spi_scl ( lcd_spi_sck ),
.lcd_spi_sda ( lcd_spi_dat ),
.i2c_exp_irq ( ~i2c_irq_n ),
.IIC_scl_i ( IIC_scl_i ),
.IIC_scl_o ( IIC_scl_o ),
.IIC_scl_t ( IIC_scl_t ),
.IIC_sda_i ( IIC_sda_i ),
.IIC_sda_o ( IIC_sda_o ),
.IIC_sda_t ( IIC_sda_t ),
.SPI_io0_i ( SPI_io0_i ),
.SPI_io0_o ( SPI_io0_o ),
.SPI_io0_t ( SPI_io0_t ),
.SPI_io1_i ( SPI_io1_i ),
.SPI_io1_o ( SPI_io1_o ),
.SPI_io1_t ( SPI_io1_t ),
.SPI_sck_i ( SPI_sck_i ),
.SPI_sck_o ( SPI_sck_o ),
.SPI_sck_t ( SPI_sck_t ),
.SPI_ss_i ( SPI_ss_i_0 ),
.SPI_ss_o ( SPI_ss_o_0 ),
.SPI_ss_t ( SPI_ss_t ),
.QSPI_ss_i ( QSPI_ss_i ),
.QSPI_ss_o ( QSPI_ss_o ),
.QSPI_ss_t ( QSPI_ss_t ),
.QSPI_io0_i ( QSPI_io0_i ),
.QSPI_io0_o ( QSPI_io0_o ),
.QSPI_io0_t ( QSPI_io0_t ),
.QSPI_io1_i ( QSPI_io1_i ),
.QSPI_io1_o ( QSPI_io1_o ),
.QSPI_io1_t ( QSPI_io1_t ),
.QSPI_io2_i ( QSPI_io2_i ),
.QSPI_io2_o ( QSPI_io2_o ),
.QSPI_io2_t ( QSPI_io2_t ),
.QSPI_io3_i ( QSPI_io3_i ),
.QSPI_io3_o ( QSPI_io3_o ),
.QSPI_io3_t ( QSPI_io3_t ),
.sensor_bias ( sensor_bias ),
.sensor_clk_fwd ( sensor_clk_fwd ),
.sensor_cmd ( sensor_cmd ),
.sensor_data_even ( sensor_data_even ),
.sensor_data_odd ( sensor_data_odd ),
.sensor_ena ( sensor_ena ),
.hdmi_tx_clk_p ( tmds_clk_p ),
.hdmi_tx_clk_n ( tmds_clk_n ),
.hdmi_tx_p ( {tmds_d2_p, tmds_d1_p, tmds_d0_p} ),
.hdmi_tx_n ( {tmds_d2_n, tmds_d1_n, tmds_d0_n} ),
.AV_av_clk ( av_clkin ),
.AV_av_dq ( fx2_av_pd ),
.FX2_sfifo_arst_n ( fx2_pa0 ),
.FX2_sfifo_addr ( {fx2_pa5, fx2_pa4} ),
.FX2_sfifo_dq ( fx2_pb ),
.FX2_sfifo_flag_a ( fx2_ctl0_flaga ),
.FX2_sfifo_flag_b ( fx2_ctl1_flagb ),
.FX2_sfifo_flag_c ( fx2_ctl2_flagc ),
.FX2_sfifo_flag_d ( 1'b1 ),
.FX2_sfifo_ifclk ( fx2_ifclk ),
.FX2_sfifo_pktend_n ( fx2_pa6 ),
.FX2_sfifo_sloe_n ( fx2_pa2 ),
.FX2_sfifo_slrd_n ( fx2_rdy0_slrd ),
.FX2_sfifo_slwr_n ( fx2_rdy1_slwr ),
.HyperBus_R0_hb_ck_p ( hram_r0_ck_p ),
.HyperBus_R0_hb_ck_n ( hram_r0_ck_n ),
.HyperBus_R0_hb_cs_n ( hram_r0_cs_n ),
.HyperBus_R0_hb_dq ( hram_r0_dq ),
.HyperBus_R0_hb_reset_n ( hram_r0_reset_n ),
.HyperBus_R0_hb_rwds ( hram_r0_rwds ),
.HyperBus_R1_hb_ck_p ( hram_r1_ck_p ),
.HyperBus_R1_hb_ck_n ( hram_r1_ck_n ),
.HyperBus_R1_hb_cs_n ( hram_r1_cs_n ),
.HyperBus_R1_hb_dq ( hram_r1_dq ),
.HyperBus_R1_hb_reset_n ( hram_r1_reset_n ),
.HyperBus_R1_hb_rwds ( hram_r1_rwds )
);
endmodule |
module rfifo #
(
parameter integer DATA_BUS_WIDTH = 32
)
(
input wire fifo_arst,
input wire fifo_wr_clk,
input wire [15:0] fifo_wr_din,
input wire fifo_wr_last,
input wire fifo_wr_ena,
output wire fifo_wr_full,
input wire fifo_rd_clk,
output wire [DATA_BUS_WIDTH-1:0] fifo_rd_dout,
output wire fifo_rd_last,
input wire fifo_rd_en,
output wire fifo_rd_empty
);
wire [17:0] din = {1'b0, fifo_wr_last, fifo_wr_din};
generate
case (DATA_BUS_WIDTH)
16: begin
wire [17:0] dout;
assign fifo_rd_dout = dout[15:0];
assign fifo_rd_last = dout[16];
fifo_18b_18b_512w fifo_18b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
32: begin
wire [35:0] dout;
assign fifo_rd_dout = {dout[15:0], dout[33:18]};
assign fifo_rd_last = dout[16];
fifo_18b_36b_512w fifo_18b_36b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [35 : 0] dout
);
end
/*--------------------------------------------------------------------*/
64: begin
wire [71:0] dout;
assign fifo_rd_dout = {dout[15:0], dout[33:18], dout[51:36], dout[69:54]};
assign fifo_rd_last = dout[16];
fifo_18b_72b_512w fifo_18b_72b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [71 : 0] dout
);
end
default: begin
INVALID_PARAMETER invalid_parameter_msg();
end
endcase
endgenerate
endmodule |
module hb_dq_iobuf #
(
parameter integer DRIVE_STRENGTH = 8,
parameter SLEW_RATE = "SLOW",
parameter real IODELAY_REFCLK_MHZ = 200.0,
parameter IODELAY_GROUP_ID = "HBMC",
parameter USE_IDELAY_PRIMITIVE = 0,
parameter [4:0] IDELAY_TAPS_VALUE = 0
)
(
input wire arst,
input wire oddr_clk,
input wire iddr_clk,
input wire idelay_clk,
inout wire buf_io,
input wire buf_t,
input wire [1:0] sdr_i,
output wire [1:0] sdr_o,
output wire sdr_o_vld
);
reg [1:0] dq_vld_pipe = 2'b00;
reg [1:0] dq_sdr_reg = 2'b00;
wire [1:0] dq_sdr;
wire buf_o;
wire buf_i;
wire tristate;
wire idelay_o;
IOBUF #
(
.DRIVE ( DRIVE_STRENGTH ), // Specify the output drive strength
.SLEW ( SLEW_RATE ) // Specify the output slew rate
)
IOBUF_io_buf
(
.O ( buf_o ), // Buffer output
.IO ( buf_io ), // Buffer inout port (connect directly to top-level port)
.I ( buf_i ), // Buffer input
.T ( tristate ) // 3-state enable input, high = input, low = output
);
/*----------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_i
(
.Q ( buf_i ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( sdr_i[0] ), // 1-bit data input (positive edge)
.D2 ( sdr_i[1] ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_t
(
.Q ( tristate ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( buf_t ), // 1-bit data input (positive edge)
.D2 ( buf_t ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
/*----------------------------------------------------------------------------------------------------------------------------*/
generate
if (USE_IDELAY_PRIMITIVE) begin
(* IODELAY_GROUP = IODELAY_GROUP_ID *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #
(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE ( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( (IDELAY_TAPS_VALUE > 31)? 31 : IDELAY_TAPS_VALUE ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( IODELAY_REFCLK_MHZ ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
)
IDELAYE2_inst
(
.C ( idelay_clk ), // 1-bit input: Clock input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( buf_o ), // 1-bit input: Data input from the I/O
.DATAOUT ( idelay_o ), // 1-bit output: Delayed data output
.CNTVALUEIN ( 5'b00000 ), // 5-bit input: Counter value input
.CNTVALUEOUT ( /*--NC--*/ ), // 5-bit output: Counter value output
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
end else begin
/* Bypassing IDELAY primitive */
assign idelay_o = buf_o;
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------*/
IDDR #
(
.DDR_CLK_EDGE ( "SAME_EDGE_PIPELINED" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
.INIT_Q1 ( 1'b0 ), // Initial value of Q1: 1'b0 or 1'b1
.INIT_Q2 ( 1'b0 ), // Initial value of Q2: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
IDDR_inst
(
.Q1 ( dq_sdr[1] ), // 1-bit output forr positive edge of clock
.Q2 ( dq_sdr[0] ), // 1-bit output forr negative edge of clock
.C ( iddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D ( idelay_o ), // 1-bit DDR data input
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
/*
* To improve timings, data coming out of the IDDR is registered by the
* falling edge of the clock, as IDDR buffer in the "SAME_EDGE_PIPELINED"
* mode outputs data with highest T-setup and T-hold margin relatively
* to the falling edge of the IDDR clock.
*
* Special pipelined strobe is used to validate incoming data. Two clock
* cycle shift register allows to compensate single cycle latency of the
* IDDR buffer and the additional register stage.
*/
always @(negedge iddr_clk or posedge arst) begin
if (arst) begin
dq_vld_pipe <= 2'b00;
dq_sdr_reg <= 2'b00;
end else begin
dq_vld_pipe <= {dq_vld_pipe[0], 1'b1};
dq_sdr_reg <= dq_sdr;
end
end
assign sdr_o = dq_sdr_reg;
assign sdr_o_vld = dq_vld_pipe[1];
endmodule |
module sync_cdc_bus #
(
parameter integer C_SYNC_STAGES = 3,
parameter integer C_SYNC_WIDTH = 8
)
(
input wire src_clk,
input wire [C_SYNC_WIDTH - 1 : 0] src_in,
input wire src_req,
output wire src_ack,
input wire dst_clk,
output wire [C_SYNC_WIDTH - 1 : 0] dst_out,
output wire dst_req,
input wire dst_ack
);
xpm_cdc_handshake #
(
.DEST_EXT_HSK ( 1 ), // DECIMAL; 0 = internal handshake, 1 = external handshake
.DEST_SYNC_FF ( C_SYNC_STAGES ), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0 ), // DECIMAL; 0 = disable simulation init values, 1 = enable simulation init values
.SIM_ASSERT_CHK ( 0 ), // DECIMAL; 0 = disable simulation messages, 1 = enable simulation messages
.SRC_SYNC_FF ( C_SYNC_STAGES ), // DECIMAL; range: 2-10
.WIDTH ( C_SYNC_WIDTH ) // DECIMAL; range: 1-1024
)
xpm_cdc_handshake_inst
(
.src_clk ( src_clk ), // 1-bit input: Source clock.
.dest_clk ( dst_clk ), // 1-bit input: Destination clock.
.src_in ( src_in ), // WIDTH-bit input: Input bus that will be synchronized to the destination clock domain.
.dest_out ( dst_out ), // WIDTH-bit output: Input bus (src_in) synchronized to destination clock domain. This output is registered.
.src_send ( src_req ), // 1-bit input: Assertion of this signal allows the src_in bus to be synchronized to
// the destination clock domain. This signal should only be asserted when src_rcv is
// deasserted, indicating that the previous data transfer is complete. This signal
// should only be deasserted once src_rcv is asserted, acknowledging that the src_in
// has been received by the destination logic.
.dest_req ( dst_req ), // 1-bit output: Assertion of this signal indicates that new dest_out data has been
// received and is ready to be used or captured by the destination logic. When
// DEST_EXT_HSK = 1, this signal will deassert once the source handshake
// acknowledges that the destination clock domain has received the transferred data.
// When DEST_EXT_HSK = 0, this signal asserts for one clock period when dest_out bus
// is valid. This output is registered.
.src_rcv ( src_ack ), // 1-bit output: Acknowledgement from destination logic that src_in has been
// received. This signal will be deasserted once destination handshake has fully
// completed, thus completing a full data transfer. This output is registered.
.dest_ack ( dst_ack ) // 1-bit input: optional; required when DEST_EXT_HSK = 1
);
endmodule |
module sync_cdc_bit #
(
parameter integer C_SYNC_STAGES = 3
)
(
input wire clk,
input wire d,
output wire q
);
xpm_cdc_single #
(
.DEST_SYNC_FF ( C_SYNC_STAGES ), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0 ), // DECIMAL; 0 = disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK ( 0 ), // DECIMAL; 0 = disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG ( 0 ) // DECIMAL; 0 = do not register input, 1 = register input
)
xpm_cdc_single_inst
(
.src_clk ( 1'b0 ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.dest_clk ( clk ), // 1-bit input: Clock signal for the destination clock domain.
.src_in ( d ), // 1-bit input: Input signal to be synchronized to dest_clk domain.
.dest_out ( q ) // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
);
endmodule |
module hb_elastic_buf
(
input wire clk_din,
input wire [15:0] din,
input wire din_vld,
input wire srst,
input wire clk_dout,
output wire [15:0] dout,
output wire dout_vld
);
reg [2:0] ram_wr_addra = 3'b000;
reg [2:0] ram_rd_addrb = 3'b000;
reg start = 1'b0;
reg start_latch = 1'b0;
wire start_sync;
/*
* The principle of operation:
*
* It is assumed that phase relation between RDWS strobe
* and memory clock, forwarded by FPGA, is not constant,
* it varies over PVT (process-voltage-temperature) i.e.
* it is completely uncertain.
*
* One of the most reliable ways to transfer incoming
* data from RWDS domain to internal system clock domain
* is using an elastic buffer, based on a dual-port RAM.
* This is working like circular queue buffer.
*
* Incoming data is going to the port A of RAM that is
* clocked by RWDS strobe. Synchronized data is coming
* out of the port B, that is clocked by destination
* domain clock. There are two RAM pointers, the writing
* and the reading one. Both pointers are reseted to zero,
* during reset state.
* As soon as RWDS starts toggling, incoming data will
* be written to the RAM and writing pointer will be
* incremented. At the same time a special start signal
* is asserted in the RWDS domain to signal the reading
* circuit to start reading RAM from the zero pointer.
* As start signal is asynchronous to reading port clock
* domain, it is passed though a single bit synchronizer.
* This synchronizer also acts as a delay for the start
* signal and provides some time margin between writing
* and reading circuits. This time margin allows to
* neutralize the uncertainty of this two clock domains.
* As frequencies of both clock domains are similar, the
* writing and reading pointer will never simultaneously
* point to the same RAM address. The reading circuit
* also erases data valid flag after reading, this feature
* allows not to read previously received data again, when
* writing pointer stops along with RWDS.
*/
always @(posedge clk_din or posedge srst) begin
if (srst) begin
start <= 1'b0;
ram_wr_addra <= 3'b000;
end else begin
start <= 1'b1;
ram_wr_addra <= ram_wr_addra + 1'b1;
end
end
sync_cdc_bit #(.C_SYNC_STAGES(3)) sync_cdc_bit_0
(
.clk ( clk_dout ),
.d ( start ),
.q ( start_sync )
);
dp_ram8x17 dp_ram8x17_inst
(
.clka ( clk_din ), // input clka
.rsta ( 1'b0 ), // input rsta
.ena ( 1'b1 ), // input ena
.wea ( 1'b1 ), // input [0 : 0] wea
.addra ( ram_wr_addra ), // input [2 : 0] addra
.dina ( {din_vld, din} ), // input [16 : 0] dina
.douta ( /*-----NC-----*/ ), // output [16 : 0] douta
.clkb ( clk_dout ), // input clkb
.rstb ( srst ), // input rstb
.enb ( 1'b1 ), // input enb
.web ( 1'b1 ), // input [0 : 0] web
.addrb ( ram_rd_addrb ), // input [2 : 0] addrb
.dinb ( {17{1'b0}} ), // input [16 : 0] dinb
.doutb ( {dout_vld, dout} ) // output [16 : 0] doutb
);
always @(posedge clk_dout) begin
if (srst) begin
start_latch <= 1'b0;
ram_rd_addrb <= 3'b000;
end else begin
start_latch <= (start_latch)? 1'b1 : start_sync;
if (start_sync | start_latch) begin
ram_rd_addrb <= ram_rd_addrb + 1'b1;
end
end
end
endmodule |
module hb_rwds_iobuf #
(
parameter integer DRIVE_STRENGTH = 8,
parameter SLEW_RATE = "SLOW",
parameter real IODELAY_REFCLK_MHZ = 200.0,
parameter IODELAY_GROUP_ID = "HBMC",
parameter USE_IDELAY_PRIMITIVE = 0,
parameter [4:0] IDELAY_TAPS_VALUE = 0
)
(
input wire oddr_clk,
input wire idelay_clk,
inout wire buf_io,
input wire buf_t,
input wire [1:0] sdr_i,
output wire rwds_delayed
);
wire buf_o;
wire buf_i;
wire tristate;
IOBUF #
(
.DRIVE ( DRIVE_STRENGTH ), // Specify the output drive strength
.SLEW ( SLEW_RATE ) // Specify the output slew rate
)
IOBUF_io_buf
(
.O ( buf_o ), // Buffer output
.IO ( buf_io ), // Buffer inout port (connect directly to top-level port)
.I ( buf_i ), // Buffer input
.T ( tristate ) // 3-state enable input, high = input, low = output
);
/*----------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_i
(
.Q ( buf_i ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( sdr_i[0] ), // 1-bit data input (positive edge)
.D2 ( sdr_i[1] ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_buf_t
(
.Q ( tristate ), // 1-bit DDR output
.C ( oddr_clk ), // 1-bit clock input
.CE ( 1'b1 ), // 1-bit clock enable input
.D1 ( buf_t ), // 1-bit data input (positive edge)
.D2 ( buf_t ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
/*----------------------------------------------------------------------------------------------------------------------------*/
generate
if (USE_IDELAY_PRIMITIVE) begin
(* IODELAY_GROUP = IODELAY_GROUP_ID *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #
(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE ( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( (IDELAY_TAPS_VALUE > 31)? 31 : IDELAY_TAPS_VALUE ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( IODELAY_REFCLK_MHZ ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
.SIGNAL_PATTERN ( "CLOCK" ) // DATA, CLOCK input signal
)
IDELAYE2_inst
(
.C ( idelay_clk ), // 1-bit input: Clock input
.CINVCTRL ( 1'b0 ), // 1-bit input: Dynamic clock inversion input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( buf_o ), // 1-bit input: Data input from the I/O
.DATAOUT ( rwds_delayed ), // 1-bit output: Delayed data output
.CNTVALUEIN ( 5'b00000 ), // 5-bit input: Counter value input
.CNTVALUEOUT ( /*---NC---*/ ), // 5-bit output: Counter value output
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
end else begin
/* Bypassing IDELAY primitive */
assign rwds_delayed = buf_o;
end
endgenerate
endmodule |
module wfifo #
(
parameter integer DATA_BUS_WIDTH = 32
)
(
input wire fifo_arst,
input wire fifo_wr_clk,
input wire [DATA_BUS_WIDTH-1:0] fifo_wr_din,
input wire [DATA_BUS_WIDTH/8-1:0] fifo_wr_strb,
input wire fifo_wr_ena,
output wire fifo_wr_full,
input wire fifo_rd_clk,
output wire [15:0] fifo_rd_dout,
output wire [1:0] fifo_rd_strb,
input wire fifo_rd_en,
output wire fifo_rd_empty
);
wire [17:0] dout;
assign fifo_rd_dout = dout[15:0];
assign fifo_rd_strb = dout[17:16];
generate
case (DATA_BUS_WIDTH)
16: begin
wire [17:0] din = {fifo_wr_strb[1:0], fifo_wr_din[15:0]};
fifo_18b_18b_512w fifo_18b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [17 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
32: begin
wire [35:0] din = {
fifo_wr_strb[1:0], fifo_wr_din[15:0],
fifo_wr_strb[3:2], fifo_wr_din[31:16]
};
fifo_36b_18b_512w fifo_36b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [35 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
/*--------------------------------------------------------------------*/
64: begin
wire [71:0] din = {
fifo_wr_strb[1:0], fifo_wr_din[15:0],
fifo_wr_strb[3:2], fifo_wr_din[31:16],
fifo_wr_strb[5:4], fifo_wr_din[47:32],
fifo_wr_strb[7:6], fifo_wr_din[63:48]
};
fifo_72b_18b_512w fifo_72b_18b_512w_inst
(
.rst ( fifo_arst ), // input rst
.wr_clk ( fifo_wr_clk ), // input wr_clk
.wr_en ( fifo_wr_ena ), // input wr_en
.full ( fifo_wr_full ), // output full
.din ( din ), // input [71 : 0] din
.rd_clk ( fifo_rd_clk ), // input rd_clk
.rd_en ( fifo_rd_en ), // input rd_en
.empty ( fifo_rd_empty ), // output empty
.dout ( dout ) // output [17 : 0] dout
);
end
default: begin
INVALID_PARAMETER invalid_parameter_msg();
end
endcase
endgenerate
endmodule |
module gpio_splitter
(
input wire [9:0] gpio,
output wire pwr_off_req,
output wire [4:0] lcd_led_level,
output wire [1:0] act_led,
output wire shtr_drive_ena,
output wire focus_drive_ena
);
assign pwr_off_req = gpio[0];
assign lcd_led_level[0] = gpio[1];
assign lcd_led_level[1] = gpio[2];
assign lcd_led_level[2] = gpio[3];
assign lcd_led_level[3] = gpio[4];
assign lcd_led_level[4] = gpio[5];
assign act_led[0] = gpio[6];
assign act_led[1] = gpio[7];
assign shtr_drive_ena = gpio[8];
assign focus_drive_ena = gpio[9];
endmodule |
module gpio_concat
(
output wire [19:0] gpio,
input wire btn_0_down,
input wire btn_1_down,
input wire btn_2_down,
input wire btn_3_down,
input wire btn_0_up,
input wire btn_1_up,
input wire btn_2_up,
input wire btn_3_up,
input wire btn_0_shrt,
input wire btn_1_shrt,
input wire btn_2_shrt,
input wire btn_3_shrt,
input wire btn_0_long,
input wire btn_1_long,
input wire btn_2_long,
input wire btn_3_long,
input wire btn_0_imm,
input wire btn_1_imm,
input wire btn_2_imm,
input wire btn_3_imm
);
assign gpio[0] = btn_0_down;
assign gpio[1] = btn_1_down;
assign gpio[2] = btn_2_down;
assign gpio[3] = btn_3_down;
assign gpio[4] = btn_0_up;
assign gpio[5] = btn_1_up;
assign gpio[6] = btn_2_up;
assign gpio[7] = btn_3_up;
assign gpio[8] = btn_0_shrt;
assign gpio[9] = btn_1_shrt;
assign gpio[10] = btn_2_shrt;
assign gpio[11] = btn_3_shrt;
assign gpio[12] = btn_0_long;
assign gpio[13] = btn_1_long;
assign gpio[14] = btn_2_long;
assign gpio[15] = btn_3_long;
assign gpio[16] = btn_0_imm;
assign gpio[17] = btn_1_imm;
assign gpio[18] = btn_2_imm;
assign gpio[19] = btn_3_imm;
endmodule |
module av_timing
(
input wire clk,
input wire resetn,
input wire [1:0] mode,
input wire [7:0] din,
output wire din_rdy,
output reg [10:0] vcnt = 11'd0,
output reg [10:0] hcnt = 11'd0,
output reg [7:0] dout = 8'h00
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
function [7:0] calc_xyz_sync;
input [2:0] fvh;
begin
calc_xyz_sync = {
1'b1, /* Always 1'b1 */
fvh, /* F, V, H bits */
fvh[1] ^ fvh[0], /* P3 = V ^ H */
fvh[2] ^ fvh[0], /* P2 = F ^ H */
fvh[2] ^ fvh[1], /* P1 = F ^ V */
fvh[2] ^ fvh[1] ^ fvh[0] /* P0 = F ^ V ^ H */
};
end
endfunction
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] NTSC_ITUR_BT656 = 2'd0,
PAL_ITUR_BT656 = 2'd1;
reg field;
reg vblank;
reg xav_preamb_ena;
reg sav_ena;
reg eav_ena;
reg hblank;
reg data_ena;
reg [10:0] hpos_cnt = 11'd0;
reg [10:0] vpos_cnt = 11'd0;
reg [10:0] vis_hres = 11'd0;
reg [10:0] vis_vres = 11'd0;
reg [10:0] hsize = 11'd0;
reg [10:0] vsize = 11'd0;
assign din_rdy = data_ena & ~vblank;
always @(*) begin
case (mode)
/* 720 x 486 */
NTSC_ITUR_BT656: begin
/*
* LINE F V EAV SAV
* 0-2 1 1 1 0
* 3-19 0 1 1 0
* 20-262 0 0 1 0 (243 lines)
* 263-264 0 1 1 0
* 265-281 1 1 1 0
* 282-524 1 0 1 0 (243 lines)
*
* | EAV | BLANKING | SAV | ACTIVE DATA LINE |
* | CODE | | CODE | |
* |F 0 0 X|8 1 8 1 ... 8 1 8 1|F 0 0 X|C Y C Y ... C Y C Y|
* |F 0 0 Y|0 0 0 0 ... 0 0 0 0|F 0 0 Y|B B ... B B |
* | | | | |
* |<----->|<----------------->|<----->|<----------------->|
* | 4 268 4 1440 |
* |<----------------------------------------------------->|
* 1716
*/
vis_hres = 11'd720;
vis_vres = 11'd486;
vsize = 11'd525;
hsize = 11'd1716;
field = ((vpos_cnt > 11'd2) && (vpos_cnt < 11'd265))? 1'b0 : 1'b1;
vblank = (((vpos_cnt > 11'd19) && (vpos_cnt < 11'd263)) || (vpos_cnt > 11'd281))? 1'b0 : 1'b1;
xav_preamb_ena = ((hpos_cnt < 3) || ((hpos_cnt > 271) && (hpos_cnt < 275)))? 1'b1 : 1'b0;
eav_ena = (hpos_cnt == 3)? 1'b1 : 1'b0;
sav_ena = (hpos_cnt == 275)? 1'b1 : 1'b0;
data_ena = (hpos_cnt > 275)? 1'b1 : 1'b0;
hblank = (((hpos_cnt > 3) && (hpos_cnt < 272)) || (vblank & data_ena))? 1'b1 : 1'b0;
end
/* 720 x 576 */
PAL_ITUR_BT656: begin
/*
* LINE F V EAV SAV
* 0-21 0 1 1 0
* 22-309 0 0 1 0 (288 lines)
* 310-311 0 1 1 0
* 312-334 1 1 1 0
* 335-622 1 0 1 0 (288 lines)
* 623-624 1 1 1 0
*
* | EAV | BLANKING | SAV | ACTIVE DATA LINE |
* | CODE | | CODE | |
* |F 0 0 X|8 1 8 1 ... 8 1 8 1|F 0 0 X|C Y C Y ... C Y C Y|
* |F 0 0 Y|0 0 0 0 ... 0 0 0 0|F 0 0 Y|B B ... B B |
* | | | | |
* |<----->|<----------------->|<----->|<----------------->|
* | 4 280 4 1440 |
* |<----------------------------------------------------->|
* 1728
*/
vis_hres = 11'd720;
vis_vres = 11'd576;
vsize = 11'd625;
hsize = 11'd1728;
field = (vpos_cnt < 11'd312)? 1'b0 : 1'b1;
vblank = (((vpos_cnt > 11'd21) && (vpos_cnt < 11'd310)) || ((vpos_cnt > 11'd334) && (vpos_cnt < 11'd623)))? 1'b0 : 1'b1;
xav_preamb_ena = ((hpos_cnt < 3) || ((hpos_cnt > 283) && (hpos_cnt < 287)))? 1'b1 : 1'b0;
eav_ena = (hpos_cnt == 3)? 1'b1 : 1'b0;
sav_ena = (hpos_cnt == 287)? 1'b1 : 1'b0;
data_ena = (hpos_cnt > 287)? 1'b1 : 1'b0;
hblank = (((hpos_cnt > 3) && (hpos_cnt < 284)) || (vblank & data_ena))? 1'b1 : 1'b0;
end
endcase
end
always @(posedge clk) begin
if (~resetn) begin
hpos_cnt <= 11'd0;
vpos_cnt <= 11'd0;
end else begin
if (hpos_cnt < hsize - 1'b1) begin
hpos_cnt <= hpos_cnt + 1'b1;
end else begin
hpos_cnt <= 11'd0;
if (vpos_cnt < vsize - 1'b1) begin
vpos_cnt <= vpos_cnt + 1'b1;
end else begin
vpos_cnt <= 11'd0;
end
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam SAV = 1'b0, /* SAV (start of active video line) */
EAV = 1'b1; /* EAV (end of active video line) */
localparam BLANKING_Y = 8'h10,
BLANKING_CBCR = 8'h80;
reg [23:0] xav_preamb = 24'h0000ff;
reg [7:0] sav_reg = 8'h00;
reg [7:0] eav_reg = 8'h00;
reg [7:0] blank_reg = BLANKING_CBCR;
/* EAV/SAV sequence */
always @(posedge clk) begin
if (xav_preamb_ena) begin
xav_preamb <= {xav_preamb[7:0], xav_preamb[23:8]};
end else begin
xav_preamb <= 24'h0000ff;
end
sav_reg <= calc_xyz_sync({field, vblank, SAV});
eav_reg <= calc_xyz_sync({field, vblank, EAV});
end
/* Blanking data */
always @(posedge clk) begin
if (hblank) begin
blank_reg <= (blank_reg == BLANKING_CBCR)? BLANKING_Y : BLANKING_CBCR;
end else begin
blank_reg <= BLANKING_CBCR;
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [4:0] EAV_SAV_PREAMB = 5'b10000,
SAV_CODE = 5'b01000,
EAV_CODE = 5'b00100,
BLANKING = 5'b00010,
DATA = 5'b00001;
wire [4:0] sync_event = {xav_preamb_ena, sav_ena, eav_ena, hblank, data_ena};
reg [7:0] data_mux;
always @(*) begin
case (sync_event)
EAV_SAV_PREAMB: data_mux = xav_preamb[7:0];
SAV_CODE: data_mux = sav_reg;
EAV_CODE: data_mux = eav_reg;
BLANKING: data_mux = blank_reg;
DATA: data_mux = din;
default: data_mux = blank_reg;
endcase
end
/* Register output value */
always @(posedge clk) begin
if (~resetn) begin
dout <= 8'h00;
end else begin
dout <= data_mux;
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg din_rdy_1 = 1'b0;
always @(posedge clk) begin
if (~resetn) begin
vcnt <= 11'd0;
hcnt <= 11'd0;
din_rdy_1 <= 1'b0;
end else begin
din_rdy_1 <= din_rdy;
if (din_rdy) begin
hcnt <= (hpos_cnt[0])? hcnt + 1'b1 : hcnt;
end else begin
hcnt <= 11'd0;
end
if (vpos_cnt == 11'd0) begin
vcnt <= 11'd0; // even row 0, 2, 4, 6...
end else begin
if (din_rdy_1 & ~din_rdy) begin
if (vcnt == (vis_vres - 11'd2)) begin
vcnt <= 11'd1; // odd row 1, 3, 5, 7...
end else begin
vcnt <= vcnt + 2'd2;
end
end
end
end
end
endmodule |
module avideo_top #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire s_axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE, ASSOCIATED_RESET s_axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire s_axi_aclk,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET s_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [7:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_INFO = "AnalogDevices:user:AV:1.0 AV av_dq" *) output wire [7:0] av_dq,
(* X_INTERFACE_INFO = "AnalogDevices:user:AV:1.0 AV av_clk" *) output wire av_clk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
output wire master_arst_n
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
wire [31:0] stat_reg;
reg [31:0] back_gnd_ycbcr = 32'h00001080; // 16-bit background color YCbCr {16'hxxxx, Y, CbCr}
reg [31:0] cnfg_win_sp = {32{1'b1}}; // 16-bit X and Y values for start point coordinates
reg [31:0] cnfg_win_ep = {32{1'b1}}; // 16-bit X and Y values for end point coordinates
always @(posedge s_axi_aclk) begin
if (~s_axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[7:2])
6'd0 : ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
/* 6'd1 : read only register */
6'd2 : back_gnd_ycbcr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : back_gnd_ycbcr[i*8 +: 8];
6'd3 : cnfg_win_sp[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : cnfg_win_sp[i*8 +: 8];
6'd4 : cnfg_win_ep[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : cnfg_win_ep[i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[7:2])
6'd0 : s_axi_rdata <= ctrl_reg;
6'd1 : s_axi_rdata <= stat_reg;
6'd2 : s_axi_rdata <= back_gnd_ycbcr;
6'd3 : s_axi_rdata <= cnfg_win_sp;
6'd4 : s_axi_rdata <= cnfg_win_ep;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
assign master_arst_n = ctrl_reg[31];
wire [1:0] av_mode = ctrl_reg[1:0];
assign stat_reg = 32'hDEADFACE;
wire [15:0] win_sp_x = cnfg_win_sp[31:16];
wire [15:0] win_sp_y = cnfg_win_sp[15:0];
wire [15:0] win_ep_x = cnfg_win_ep[31:16];
wire [15:0] win_ep_y = cnfg_win_ep[15:0];
wire [7:0] back_gnd_y = back_gnd_ycbcr[15:8];
wire [7:0] back_gnd_cbcr = back_gnd_ycbcr[7:0];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pix_clk = s_axis_aclk;
wire din_rdy;
wire [10:0] vcnt;
wire [10:0] hcnt;
reg force_read = 1'b0;
wire exp_eof = ((hcnt == win_ep_x) && (vcnt == win_ep_y));
wire eof = (s_axis_tvalid & s_axis_tready & s_axis_tuser);
always @(posedge pix_clk) begin
if (exp_eof & ~eof & ~force_read) begin
force_read <= 1'b1;
end else begin
if (eof) begin
force_read <= 1'b0;
end
end
end
reg act_win = 1'b0;
always @(*) begin
if (din_rdy && (hcnt >= win_sp_x) && (hcnt <= win_ep_x) && (vcnt >= win_sp_y) && (vcnt <= win_ep_y)) begin
act_win = 1'b1;
end else begin
act_win = 1'b0;
end
end
reg [7:0] bg;
always @(posedge pix_clk) begin
if (din_rdy) begin
bg <= (bg == back_gnd_ycbcr)? back_gnd_y : back_gnd_ycbcr;
end else begin
bg <= back_gnd_ycbcr;
end
end
av_timing av_timing
(
.clk ( pix_clk ),
.resetn ( s_axis_aresetn ),
.mode ( av_mode ),
.din_rdy ( din_rdy ),
.vcnt ( vcnt ),
.hcnt ( hcnt ),
.din ( (act_win)? s_axis_tdata : bg ),
.dout ( av_dq )
);
assign s_axis_tready = force_read | act_win;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_ifclk
(
.Q ( av_clk ), // 1-bit DDR output
.C ( pix_clk ), // 1-bit clock input
.CE ( s_axis_aresetn ), // 1-bit clock enable input
.D1 ( 1'b0 ), // 1-bit data input (positive edge)
.D2 ( 1'b1 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
endmodule |
module lcd_backlight_ctrl #
(
parameter integer CLK_HZ = 0
)
(
input wire clk,
input wire srst,
input wire [4:0] level,
output reg pulse_out = 1'b0
);
localparam US_DELAY = CLK_HZ / 1000000;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [4:0] pulse_cnt = 5'd0;
reg [4:0] level_prev = 5'd0;
reg [15:0] timer = 16'd0;
reg timer_hit = 1'b0;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* 10us period timer */
always @(posedge clk) begin
if (srst) begin
timer <= 16'd0;
timer_hit <= 1'b0;
end else begin
if (timer == US_DELAY * 10) begin
timer <= 16'd0;
timer_hit <= 1'b1;
end else begin
timer <= timer + 1'b1;
timer_hit <= 1'b0;
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam ST_RESET = 2'd0,
ST_IDLE = 2'd1,
ST_PULSE_0 = 2'd2,
ST_PULSE_1 = 2'd3;
reg [1:0] state = ST_RESET;
always @(posedge clk) begin
if (srst) begin
pulse_out <= 1'b0;
level_prev <= 5'd0;
state <= ST_RESET;
end else begin
/* FSM state changes with 10us delay */
if (timer_hit) begin
case (state)
ST_RESET: begin
if (level != 5'd0) begin
pulse_out <= 1'b1;
level_prev <= level;
pulse_cnt <= 5'd31 - level;
state <= ST_PULSE_0;
end
end
ST_IDLE: begin
if (level_prev != level) begin
level_prev <= level;
pulse_cnt <= (level_prev > level)? (level_prev - level) : (level_prev - level + 5'd31 + 1'b1);
state <= ST_PULSE_0;
end
end
ST_PULSE_0: begin
if (pulse_cnt == 5'd0) begin
pulse_out <= 1'b1;
state <= ST_IDLE;
end else begin
pulse_out <= 1'b0;
pulse_cnt <= pulse_cnt - 1'b1;
state <= ST_PULSE_1;
end
end
ST_PULSE_1: begin
pulse_out <= 1'b1;
state <= ST_PULSE_0;
end
endcase
end
end
end
endmodule |
module axis_dsp_linear_func #
(
parameter TUSER_WIDTH = 1
)
(
input wire axis_aresetn,
input wire axis_aclk,
input wire dsp_func_sel,
input wire [17:0] dsp_D_s_axis_tdata,
input wire dsp_D_s_axis_tvalid,
output wire dsp_D_s_axis_tready,
input wire dsp_D_s_axis_tlast,
input wire [TUSER_WIDTH - 1:0] dsp_D_s_axis_tuser,
input wire [17:0] dsp_A_s_axis_tdata,
input wire dsp_A_s_axis_tvalid,
output wire dsp_A_s_axis_tready,
input wire dsp_A_s_axis_tlast,
input wire [TUSER_WIDTH - 1:0] dsp_A_s_axis_tuser,
input wire [17:0] dsp_B_s_axis_tdata,
input wire dsp_B_s_axis_tvalid,
output wire dsp_B_s_axis_tready,
input wire dsp_B_s_axis_tlast,
input wire [TUSER_WIDTH - 1:0] dsp_B_s_axis_tuser,
input wire [47:0] dsp_C_s_axis_tdata,
input wire dsp_C_s_axis_tvalid,
output wire dsp_C_s_axis_tready,
input wire dsp_C_s_axis_tlast,
input wire [TUSER_WIDTH - 1:0] dsp_C_s_axis_tuser,
output wire [47:0] dsp_P_m_axis_tdata,
output wire dsp_P_m_axis_tvalid,
input wire dsp_P_m_axis_tready,
output wire dsp_P_m_axis_tlast,
output wire [TUSER_WIDTH - 1:0] dsp_P_m_axis_tuser
);
localparam PIPE_DATA_IN_WIDTH = 1;
localparam PIPE_DATA_OUT_WIDTH = 1;
localparam PIPE_QUAL_WIDTH = 1;
localparam PIPE_STAGES = 4; // DSP_LINEAR_FUNC pipeline delay
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pipe_cen;
wire s_axis_tready;
wire s_axis_tvalid = dsp_D_s_axis_tvalid & dsp_A_s_axis_tvalid & dsp_B_s_axis_tvalid & dsp_C_s_axis_tvalid;
wire s_axis_tlast = dsp_D_s_axis_tlast & dsp_A_s_axis_tlast & dsp_B_s_axis_tlast & dsp_C_s_axis_tlast;
wire [TUSER_WIDTH - 1:0] s_axis_tuser = dsp_D_s_axis_tuser | dsp_A_s_axis_tuser | dsp_B_s_axis_tuser | dsp_C_s_axis_tuser;
wire m_axis_tready = dsp_P_m_axis_tready;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [TUSER_WIDTH - 1:0] m_axis_tuser;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( TUSER_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( 1'b0 ),
.s_axis_tuser ( s_axis_tuser ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.m_axis_tdata (),
.m_axis_tuser ( m_axis_tuser ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( m_axis_tlast ),
.pipe_cen ( pipe_cen ),
.pipe_in_data (),
.pipe_out_data ( 1'b0 )
);
assign dsp_P_m_axis_tvalid = m_axis_tvalid;
assign dsp_P_m_axis_tlast = m_axis_tlast;
assign dsp_P_m_axis_tuser = m_axis_tuser;
assign dsp_D_s_axis_tready = s_axis_tready;
assign dsp_A_s_axis_tready = s_axis_tready;
assign dsp_B_s_axis_tready = s_axis_tready;
assign dsp_C_s_axis_tready = s_axis_tready;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* dsp_func_sel = 0 -> P = (D-A)*B+C
* dsp_func_sel = 1 -> P = (D+A)*B+C */
DSP_LINEAR_FUNC dsp
(
.CLK ( axis_aclk ), // input CLK
.CE ( pipe_cen ), // input CE
.SCLR ( ~axis_aresetn ), // input SCLR
.SEL ( dsp_func_sel ), // input [0 : 0] SEL
.A ( dsp_A_s_axis_tdata ), // input [17 : 0] A
.B ( dsp_B_s_axis_tdata ), // input [17 : 0] B
.C ( dsp_C_s_axis_tdata ), // input [47 : 0] C
.D ( dsp_D_s_axis_tdata ), // input [17 : 0] D
.P ( dsp_P_m_axis_tdata ) // output [47 : 0] P
);
endmodule |
module m_axis_stub
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_RSTIF RST" *)
input wire m_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_CLKIF, ASSOCIATED_BUSIF M_AXIS_STUB, ASSOCIATED_RESET m_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_CLKIF CLK" *)
input wire m_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_STUB, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TDATA" *) output wire [31:0] m_axis_stub_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TVALID" *) output wire m_axis_stub_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TREADY" *) input wire m_axis_stub_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_STUB TUSER" *) output wire m_axis_stub_tlast
);
assign m_axis_stub_tdata = {32{1'b0}};
assign m_axis_stub_tvalid = 1'b0;
assign m_axis_stub_tlast = 1'b0;
endmodule |
module pipeline #
(
parameter PIPE_WIDTH = 32,
parameter PIPE_STAGES = 8
)
(
input wire clk,
input wire cen,
input wire srst,
input wire [PIPE_WIDTH - 1:0] pipe_in,
output wire [PIPE_WIDTH - 1:0] pipe_out
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
genvar i;
generate
for (i = 0; i < PIPE_WIDTH; i = i + 1) begin: loop
reg [PIPE_STAGES - 1:0] pipe_gen;
always @(posedge clk) begin
if (srst) begin
pipe_gen <= {PIPE_STAGES{1'b0}};
end else begin
if (cen) begin
pipe_gen <= (PIPE_STAGES > 1)? {pipe_gen[PIPE_STAGES - 2:0], pipe_in[i]} : pipe_in[i];
end
end
end
assign pipe_out[i] = pipe_gen[PIPE_STAGES - 1];
end
endgenerate
endmodule |
module axis_pipeliner #
(
parameter integer PIPE_DATA_IN_WIDTH = 32,
parameter integer PIPE_DATA_OUT_WIDTH = 32,
parameter integer PIPE_QUAL_WIDTH = 4,
parameter integer PIPE_STAGES = 8
)
(
input wire axis_aclk,
input wire axis_aresetn,
input wire [PIPE_DATA_IN_WIDTH - 1:0] s_axis_tdata,
input wire [PIPE_QUAL_WIDTH - 1:0] s_axis_tuser,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
output wire [PIPE_DATA_OUT_WIDTH - 1:0] m_axis_tdata,
output wire [PIPE_QUAL_WIDTH - 1:0] m_axis_tuser,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire pipe_cen,
output wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data,
input wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [PIPE_STAGES - 1:0] tvalid_pipe = {PIPE_STAGES{1'b0}};
reg [PIPE_STAGES - 1:0] tlast_pipe = {PIPE_STAGES{1'b0}};
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
tvalid_pipe <= {PIPE_STAGES{1'b0}};
tlast_pipe <= {PIPE_STAGES{1'b0}};
end else begin
if (pipe_cen) begin
tvalid_pipe <= (PIPE_STAGES > 1)? {tvalid_pipe[PIPE_STAGES - 2:0], s_axis_tvalid} : s_axis_tvalid;
tlast_pipe <= (PIPE_STAGES > 1)? {tlast_pipe[PIPE_STAGES - 2:0], s_axis_tlast} : s_axis_tlast;
end
end
end
assign s_axis_tready = s_axis_tvalid & (~tvalid_pipe[PIPE_STAGES - 1] | m_axis_tready);
assign pipe_cen = s_axis_tready | ~tvalid_pipe[PIPE_STAGES - 1] | m_axis_tready;
assign pipe_in_data = s_axis_tdata;
assign m_axis_tdata = pipe_out_data;
assign m_axis_tvalid = tvalid_pipe[PIPE_STAGES - 1];
assign m_axis_tlast = tlast_pipe[PIPE_STAGES - 1];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
genvar i;
generate
for (i = 0; i < PIPE_QUAL_WIDTH; i = i + 1) begin: loop
reg [PIPE_STAGES - 1:0] pipe_gen = {PIPE_STAGES{1'b0}};
always @(posedge axis_aclk) begin
if (pipe_cen) begin
pipe_gen <= (PIPE_STAGES > 1)? {pipe_gen[PIPE_STAGES - 2:0], s_axis_tuser[i]} : s_axis_tuser[i];
end
end
assign m_axis_tuser[i] = pipe_gen[PIPE_STAGES - 1];
end
endgenerate
endmodule |
module rom128xN #
(
parameter OUTPUT_REG = "NOT_SELECTED",
parameter integer DATA_WIDTH = 128,
parameter [DATA_WIDTH - 1:0] INIT_ROM_00 = {DATA_WIDTH{1'b0}},
INIT_ROM_01 = {DATA_WIDTH{1'b0}},
INIT_ROM_02 = {DATA_WIDTH{1'b0}},
INIT_ROM_03 = {DATA_WIDTH{1'b0}},
INIT_ROM_04 = {DATA_WIDTH{1'b0}},
INIT_ROM_05 = {DATA_WIDTH{1'b0}},
INIT_ROM_06 = {DATA_WIDTH{1'b0}},
INIT_ROM_07 = {DATA_WIDTH{1'b0}},
INIT_ROM_08 = {DATA_WIDTH{1'b0}},
INIT_ROM_09 = {DATA_WIDTH{1'b0}},
INIT_ROM_0A = {DATA_WIDTH{1'b0}},
INIT_ROM_0B = {DATA_WIDTH{1'b0}},
INIT_ROM_0C = {DATA_WIDTH{1'b0}},
INIT_ROM_0D = {DATA_WIDTH{1'b0}},
INIT_ROM_0E = {DATA_WIDTH{1'b0}},
INIT_ROM_0F = {DATA_WIDTH{1'b0}},
INIT_ROM_10 = {DATA_WIDTH{1'b0}},
INIT_ROM_11 = {DATA_WIDTH{1'b0}},
INIT_ROM_12 = {DATA_WIDTH{1'b0}},
INIT_ROM_13 = {DATA_WIDTH{1'b0}},
INIT_ROM_14 = {DATA_WIDTH{1'b0}},
INIT_ROM_15 = {DATA_WIDTH{1'b0}},
INIT_ROM_16 = {DATA_WIDTH{1'b0}},
INIT_ROM_17 = {DATA_WIDTH{1'b0}},
INIT_ROM_18 = {DATA_WIDTH{1'b0}},
INIT_ROM_19 = {DATA_WIDTH{1'b0}},
INIT_ROM_1A = {DATA_WIDTH{1'b0}},
INIT_ROM_1B = {DATA_WIDTH{1'b0}},
INIT_ROM_1C = {DATA_WIDTH{1'b0}},
INIT_ROM_1D = {DATA_WIDTH{1'b0}},
INIT_ROM_1E = {DATA_WIDTH{1'b0}},
INIT_ROM_1F = {DATA_WIDTH{1'b0}},
INIT_ROM_20 = {DATA_WIDTH{1'b0}},
INIT_ROM_21 = {DATA_WIDTH{1'b0}},
INIT_ROM_22 = {DATA_WIDTH{1'b0}},
INIT_ROM_23 = {DATA_WIDTH{1'b0}},
INIT_ROM_24 = {DATA_WIDTH{1'b0}},
INIT_ROM_25 = {DATA_WIDTH{1'b0}},
INIT_ROM_26 = {DATA_WIDTH{1'b0}},
INIT_ROM_27 = {DATA_WIDTH{1'b0}},
INIT_ROM_28 = {DATA_WIDTH{1'b0}},
INIT_ROM_29 = {DATA_WIDTH{1'b0}},
INIT_ROM_2A = {DATA_WIDTH{1'b0}},
INIT_ROM_2B = {DATA_WIDTH{1'b0}},
INIT_ROM_2C = {DATA_WIDTH{1'b0}},
INIT_ROM_2D = {DATA_WIDTH{1'b0}},
INIT_ROM_2E = {DATA_WIDTH{1'b0}},
INIT_ROM_2F = {DATA_WIDTH{1'b0}},
INIT_ROM_30 = {DATA_WIDTH{1'b0}},
INIT_ROM_31 = {DATA_WIDTH{1'b0}},
INIT_ROM_32 = {DATA_WIDTH{1'b0}},
INIT_ROM_33 = {DATA_WIDTH{1'b0}},
INIT_ROM_34 = {DATA_WIDTH{1'b0}},
INIT_ROM_35 = {DATA_WIDTH{1'b0}},
INIT_ROM_36 = {DATA_WIDTH{1'b0}},
INIT_ROM_37 = {DATA_WIDTH{1'b0}},
INIT_ROM_38 = {DATA_WIDTH{1'b0}},
INIT_ROM_39 = {DATA_WIDTH{1'b0}},
INIT_ROM_3A = {DATA_WIDTH{1'b0}},
INIT_ROM_3B = {DATA_WIDTH{1'b0}},
INIT_ROM_3C = {DATA_WIDTH{1'b0}},
INIT_ROM_3D = {DATA_WIDTH{1'b0}},
INIT_ROM_3E = {DATA_WIDTH{1'b0}},
INIT_ROM_3F = {DATA_WIDTH{1'b0}},
INIT_ROM_40 = {DATA_WIDTH{1'b0}},
INIT_ROM_41 = {DATA_WIDTH{1'b0}},
INIT_ROM_42 = {DATA_WIDTH{1'b0}},
INIT_ROM_43 = {DATA_WIDTH{1'b0}},
INIT_ROM_44 = {DATA_WIDTH{1'b0}},
INIT_ROM_45 = {DATA_WIDTH{1'b0}},
INIT_ROM_46 = {DATA_WIDTH{1'b0}},
INIT_ROM_47 = {DATA_WIDTH{1'b0}},
INIT_ROM_48 = {DATA_WIDTH{1'b0}},
INIT_ROM_49 = {DATA_WIDTH{1'b0}},
INIT_ROM_4A = {DATA_WIDTH{1'b0}},
INIT_ROM_4B = {DATA_WIDTH{1'b0}},
INIT_ROM_4C = {DATA_WIDTH{1'b0}},
INIT_ROM_4D = {DATA_WIDTH{1'b0}},
INIT_ROM_4E = {DATA_WIDTH{1'b0}},
INIT_ROM_4F = {DATA_WIDTH{1'b0}},
INIT_ROM_50 = {DATA_WIDTH{1'b0}},
INIT_ROM_51 = {DATA_WIDTH{1'b0}},
INIT_ROM_52 = {DATA_WIDTH{1'b0}},
INIT_ROM_53 = {DATA_WIDTH{1'b0}},
INIT_ROM_54 = {DATA_WIDTH{1'b0}},
INIT_ROM_55 = {DATA_WIDTH{1'b0}},
INIT_ROM_56 = {DATA_WIDTH{1'b0}},
INIT_ROM_57 = {DATA_WIDTH{1'b0}},
INIT_ROM_58 = {DATA_WIDTH{1'b0}},
INIT_ROM_59 = {DATA_WIDTH{1'b0}},
INIT_ROM_5A = {DATA_WIDTH{1'b0}},
INIT_ROM_5B = {DATA_WIDTH{1'b0}},
INIT_ROM_5C = {DATA_WIDTH{1'b0}},
INIT_ROM_5D = {DATA_WIDTH{1'b0}},
INIT_ROM_5E = {DATA_WIDTH{1'b0}},
INIT_ROM_5F = {DATA_WIDTH{1'b0}},
INIT_ROM_60 = {DATA_WIDTH{1'b0}},
INIT_ROM_61 = {DATA_WIDTH{1'b0}},
INIT_ROM_62 = {DATA_WIDTH{1'b0}},
INIT_ROM_63 = {DATA_WIDTH{1'b0}},
INIT_ROM_64 = {DATA_WIDTH{1'b0}},
INIT_ROM_65 = {DATA_WIDTH{1'b0}},
INIT_ROM_66 = {DATA_WIDTH{1'b0}},
INIT_ROM_67 = {DATA_WIDTH{1'b0}},
INIT_ROM_68 = {DATA_WIDTH{1'b0}},
INIT_ROM_69 = {DATA_WIDTH{1'b0}},
INIT_ROM_6A = {DATA_WIDTH{1'b0}},
INIT_ROM_6B = {DATA_WIDTH{1'b0}},
INIT_ROM_6C = {DATA_WIDTH{1'b0}},
INIT_ROM_6D = {DATA_WIDTH{1'b0}},
INIT_ROM_6E = {DATA_WIDTH{1'b0}},
INIT_ROM_6F = {DATA_WIDTH{1'b0}},
INIT_ROM_70 = {DATA_WIDTH{1'b0}},
INIT_ROM_71 = {DATA_WIDTH{1'b0}},
INIT_ROM_72 = {DATA_WIDTH{1'b0}},
INIT_ROM_73 = {DATA_WIDTH{1'b0}},
INIT_ROM_74 = {DATA_WIDTH{1'b0}},
INIT_ROM_75 = {DATA_WIDTH{1'b0}},
INIT_ROM_76 = {DATA_WIDTH{1'b0}},
INIT_ROM_77 = {DATA_WIDTH{1'b0}},
INIT_ROM_78 = {DATA_WIDTH{1'b0}},
INIT_ROM_79 = {DATA_WIDTH{1'b0}},
INIT_ROM_7A = {DATA_WIDTH{1'b0}},
INIT_ROM_7B = {DATA_WIDTH{1'b0}},
INIT_ROM_7C = {DATA_WIDTH{1'b0}},
INIT_ROM_7D = {DATA_WIDTH{1'b0}},
INIT_ROM_7E = {DATA_WIDTH{1'b0}},
INIT_ROM_7F = {DATA_WIDTH{1'b0}}
)
(
input wire clk,
input wire cen,
input wire [6:0] addr,
output wire [DATA_WIDTH - 1:0] dout
);
/*----------------------------------------------------------------------------------*/
/* Checking input parameters */
generate
if ((OUTPUT_REG != "TRUE") && (OUTPUT_REG != "FALSE")) begin
//INVALID_PARAMETER invalid_parameter_msg();
initial begin
$error("Invalid parameter!");
end
end
endgenerate
/*----------------------------------------------------------------------------------*/
wire [DATA_WIDTH - 1:0] imm_out;
generate
if (OUTPUT_REG == "TRUE") begin
reg [DATA_WIDTH - 1:0] dout_reg = {DATA_WIDTH{1'b0}};
always @(posedge clk) begin
if (cen) begin
dout_reg <= imm_out;
end
end
assign dout = dout_reg;
end else begin
assign dout = imm_out;
end
endgenerate
/*----------------------------------------------------------------------------------------------------------------------------------------------------------------*/
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : rom_array
ROM128X1 #
(
.INIT // Initial contents of ROM
(
{
INIT_ROM_7F[i], INIT_ROM_7E[i], INIT_ROM_7D[i], INIT_ROM_7C[i], INIT_ROM_7B[i], INIT_ROM_7A[i], INIT_ROM_79[i], INIT_ROM_78[i],
INIT_ROM_77[i], INIT_ROM_76[i], INIT_ROM_75[i], INIT_ROM_74[i], INIT_ROM_73[i], INIT_ROM_72[i], INIT_ROM_71[i], INIT_ROM_70[i],
INIT_ROM_6F[i], INIT_ROM_6E[i], INIT_ROM_6D[i], INIT_ROM_6C[i], INIT_ROM_6B[i], INIT_ROM_6A[i], INIT_ROM_69[i], INIT_ROM_68[i],
INIT_ROM_67[i], INIT_ROM_66[i], INIT_ROM_65[i], INIT_ROM_64[i], INIT_ROM_63[i], INIT_ROM_62[i], INIT_ROM_61[i], INIT_ROM_60[i],
INIT_ROM_5F[i], INIT_ROM_5E[i], INIT_ROM_5D[i], INIT_ROM_5C[i], INIT_ROM_5B[i], INIT_ROM_5A[i], INIT_ROM_59[i], INIT_ROM_58[i],
INIT_ROM_57[i], INIT_ROM_56[i], INIT_ROM_55[i], INIT_ROM_54[i], INIT_ROM_53[i], INIT_ROM_52[i], INIT_ROM_51[i], INIT_ROM_50[i],
INIT_ROM_4F[i], INIT_ROM_4E[i], INIT_ROM_4D[i], INIT_ROM_4C[i], INIT_ROM_4B[i], INIT_ROM_4A[i], INIT_ROM_49[i], INIT_ROM_48[i],
INIT_ROM_47[i], INIT_ROM_46[i], INIT_ROM_45[i], INIT_ROM_44[i], INIT_ROM_43[i], INIT_ROM_42[i], INIT_ROM_41[i], INIT_ROM_40[i],
INIT_ROM_3F[i], INIT_ROM_3E[i], INIT_ROM_3D[i], INIT_ROM_3C[i], INIT_ROM_3B[i], INIT_ROM_3A[i], INIT_ROM_39[i], INIT_ROM_38[i],
INIT_ROM_37[i], INIT_ROM_36[i], INIT_ROM_35[i], INIT_ROM_34[i], INIT_ROM_33[i], INIT_ROM_32[i], INIT_ROM_31[i], INIT_ROM_30[i],
INIT_ROM_2F[i], INIT_ROM_2E[i], INIT_ROM_2D[i], INIT_ROM_2C[i], INIT_ROM_2B[i], INIT_ROM_2A[i], INIT_ROM_29[i], INIT_ROM_28[i],
INIT_ROM_27[i], INIT_ROM_26[i], INIT_ROM_25[i], INIT_ROM_24[i], INIT_ROM_23[i], INIT_ROM_22[i], INIT_ROM_21[i], INIT_ROM_20[i],
INIT_ROM_1F[i], INIT_ROM_1E[i], INIT_ROM_1D[i], INIT_ROM_1C[i], INIT_ROM_1B[i], INIT_ROM_1A[i], INIT_ROM_19[i], INIT_ROM_18[i],
INIT_ROM_17[i], INIT_ROM_16[i], INIT_ROM_15[i], INIT_ROM_14[i], INIT_ROM_13[i], INIT_ROM_12[i], INIT_ROM_11[i], INIT_ROM_10[i],
INIT_ROM_0F[i], INIT_ROM_0E[i], INIT_ROM_0D[i], INIT_ROM_0C[i], INIT_ROM_0B[i], INIT_ROM_0A[i], INIT_ROM_09[i], INIT_ROM_08[i],
INIT_ROM_07[i], INIT_ROM_06[i], INIT_ROM_05[i], INIT_ROM_04[i], INIT_ROM_03[i], INIT_ROM_02[i], INIT_ROM_01[i], INIT_ROM_00[i]
}
)
)
ROM128X1_inst
(
.O ( imm_out[i] ), // ROM immediate output
.A0 ( addr[0] ), // ROM address[0]
.A1 ( addr[1] ), // ROM address[1]
.A2 ( addr[2] ), // ROM address[2]
.A3 ( addr[3] ), // ROM address[3]
.A4 ( addr[4] ), // ROM address[4]
.A5 ( addr[5] ), // ROM address[5]
.A6 ( addr[6] ) // ROM address[6]
);
end
endgenerate
endmodule |
module axis_2w_splitter #
(
parameter AXIS_TDATA_WIDTH = 32,
parameter AXIS_TUSER_WIDTH = 4
)
(
input wire axis_aclk,
input wire axis_aresetn,
input wire [AXIS_TDATA_WIDTH - 1:0] s_axis_tdata,
input wire [AXIS_TUSER_WIDTH - 1:0] s_axis_tuser,
input wire s_axis_tvalid,
output reg s_axis_tready = 1'b0,
input wire s_axis_tlast,
output wire [AXIS_TDATA_WIDTH - 1:0] m_axis_0_tdata,
output wire [AXIS_TUSER_WIDTH - 1:0] m_axis_0_tuser,
output reg m_axis_0_tvalid = 1'b0,
input wire m_axis_0_tready,
output wire m_axis_0_tlast,
output wire [AXIS_TDATA_WIDTH - 1:0] m_axis_1_tdata,
output wire [AXIS_TUSER_WIDTH - 1:0] m_axis_1_tuser,
output reg m_axis_1_tvalid = 1'b0,
input wire m_axis_1_tready,
output wire m_axis_1_tlast
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [AXIS_TDATA_WIDTH - 1:0] m_axis_tdata = {AXIS_TDATA_WIDTH{1'b0}};
reg [AXIS_TUSER_WIDTH - 1:0] m_axis_tuser = {AXIS_TUSER_WIDTH{1'b0}};
reg m_axis_tlast = 1'b0;
assign m_axis_0_tdata = m_axis_tdata;
assign m_axis_0_tuser = m_axis_tuser;
assign m_axis_0_tlast = m_axis_tlast;
assign m_axis_1_tdata = m_axis_tdata;
assign m_axis_1_tuser = m_axis_tuser;
assign m_axis_1_tlast = m_axis_tlast;
localparam [1:0] ST_RST = 2'd0,
ST_GET = 2'd1,
ST_SEND = 2'd2;
reg [1:0] state = ST_RST;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
s_axis_tready <= 1'b0;
m_axis_0_tvalid <= 1'b0;
m_axis_1_tvalid <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
s_axis_tready <= 1'b1;
m_axis_0_tvalid <= 1'b0;
m_axis_1_tvalid <= 1'b0;
state <= ST_GET;
end
ST_GET: begin
if (s_axis_tvalid) begin
m_axis_tdata <= s_axis_tdata;
m_axis_tuser <= s_axis_tuser;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= 1'b0;
m_axis_0_tvalid <= 1'b1;
m_axis_1_tvalid <= 1'b1;
state <= ST_SEND;
end
end
ST_SEND: begin
/* TREADY may rise and fall any time, so
* we should prevent TVALID re-assertion */
if (m_axis_0_tready & m_axis_0_tvalid) begin
m_axis_0_tvalid <= 1'b0;
end
/* TREADY may rise and fall any time, so
* we should prevent TVALID re-assertion */
if (m_axis_1_tready & m_axis_1_tvalid) begin
m_axis_1_tvalid <= 1'b0;
end
if (~m_axis_0_tvalid & ~m_axis_1_tvalid) begin
s_axis_tready <= 1'b1;
state <= ST_GET;
end
end
default: begin
state <= ST_RST;
end
endcase
end
end
endmodule |
module ISC0901_ctrl #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE:S_AXIS_RTEMP:M_AXIS_BIAS:M_AXIS_SENSOR_CMD:S_AXIS_MM2S:M_AXIS_S2MM:M_AXIS_MM2S_CMD:S_AXIS_MM2S_STS:M_AXIS_S2MM_CMD:S_AXIS_S2MM_STS, ASSOCIATED_RESET axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axi_aclk,
input wire sof_strb,
input wire eol_strb,
input wire fifo_bias_prog_full,
output wire sensor_rstn,
output wire sensor_bias_volt_sel,
output wire sensor_bias_boost_pwr_ena,
output wire sensor_bias_pwr_ena,
output wire sensor_core_pwr_ena,
output wire sensor_io_pwr_ena_n,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
/* Slave AXIS sensor row temperature/feedback ??? */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_RTEMP, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RTEMP TDATA" *) input wire [31:0] s_axis_rtemp_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RTEMP TVALID" *) input wire s_axis_rtemp_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RTEMP TREADY" *) output wire s_axis_rtemp_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RTEMP TLAST" *) input wire s_axis_rtemp_tlast,
/* Master AXIS sensor bias row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_BIAS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_BIAS TDATA" *) output wire [31:0] m_axis_bias_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_BIAS TVALID" *) output wire m_axis_bias_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_BIAS TREADY" *) input wire m_axis_bias_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_BIAS TLAST" *) output wire m_axis_bias_tlast,
/* Master AXIS sensor command */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_SENSOR_CMD, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_SENSOR_CMD TDATA" *) output wire [31:0] m_axis_sensor_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_SENSOR_CMD TVALID" *) output wire m_axis_sensor_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_SENSOR_CMD TREADY" *) input wire m_axis_sensor_cmd_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_SENSOR_CMD TLAST" *) output wire m_axis_sensor_cmd_tlast,
/* DataMover MM2S (read from memory) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TDATA" *) input wire [31:0] s_axis_mm2s_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TKEEP" *) input wire [3:0] s_axis_mm2s_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TVALID" *) input wire s_axis_mm2s_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TREADY" *) output wire s_axis_mm2s_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TLAST" *) input wire s_axis_mm2s_tlast,
/* DataMover S2MM (write to memory) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_S2MM, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TDATA" *) output wire [31:0] m_axis_s2mm_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TKEEP" *) output wire [3:0] m_axis_s2mm_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TVALID" *) output wire m_axis_s2mm_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TREADY" *) input wire m_axis_s2mm_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TLAST" *) output wire m_axis_s2mm_tlast,
/* DataMover MM2S command interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_MM2S_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TDATA" *) output reg [71:0] m_axis_mm2s_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TVALID" *) output reg m_axis_mm2s_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TREADY" *) input wire m_axis_mm2s_cmd_tready,
/* DataMover MM2S status interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TDATA" *) input wire [7:0] s_axis_mm2s_sts_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TKEEP" *) input wire [0:0] s_axis_mm2s_sts_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TVALID" *) input wire s_axis_mm2s_sts_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TREADY" *) output reg s_axis_mm2s_sts_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TLAST" *) input wire s_axis_mm2s_sts_tlast,
/* DataMover S2MM command interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_S2MM_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TDATA" *) output reg [71:0] m_axis_s2mm_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TVALID" *) output reg m_axis_s2mm_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TREADY" *) input wire m_axis_s2mm_cmd_tready,
/* DataMover S2MM status interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_S2MM_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TDATA" *) input wire [7:0] s_axis_s2mm_sts_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TKEEP" *) input wire [0:0] s_axis_s2mm_sts_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TVALID" *) input wire s_axis_s2mm_sts_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TREADY" *) output reg s_axis_s2mm_sts_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TLAST" *) input wire s_axis_s2mm_sts_tlast
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
reg [31:0] bias_buf_addr = {32{1'b0}};
reg [31:0] rtemp_buf_addr = {32{1'b0}};
reg [31:0] cmd_buf_addr = {32{1'b0}};
reg [31:0] bias_btt = {32{1'b0}};
reg [31:0] rtemp_btt = {32{1'b0}};
reg [31:0] cmd_btt = {32{1'b0}};
always @(posedge axi_aclk) begin
if (~axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[6:2])
5'd0 : ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
5'd1 : bias_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : bias_buf_addr [i*8 +: 8];
5'd2 : rtemp_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : rtemp_buf_addr [i*8 +: 8];
5'd3 : cmd_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : cmd_buf_addr [i*8 +: 8];
5'd4 : bias_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : bias_btt [i*8 +: 8];
5'd5 : rtemp_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : rtemp_btt[i*8 +: 8];
5'd6 : cmd_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : cmd_btt [i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[6:2])
5'd0 : s_axi_rdata <= ctrl_reg;
5'd1 : s_axi_rdata <= bias_buf_addr;
5'd2 : s_axi_rdata <= rtemp_buf_addr;
5'd3 : s_axi_rdata <= cmd_buf_addr;
5'd4 : s_axi_rdata <= bias_btt;
5'd5 : s_axi_rdata <= rtemp_btt;
5'd6 : s_axi_rdata <= cmd_btt;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [3:0] DMA_XFER_OKAY = 4'b1000,
DMA_XFER_SLVERR = 4'b0100,
DMA_XFER_DECERR = 4'b0010,
DMA_XFER_INTERR = 4'b0001;
localparam BIAS_ROW_FIFO_ID = 1'b0,
SENSOR_CMD_ID = 1'b1;
// S2MM
reg s2mm_xfer_ena = 1'b0;
assign m_axis_s2mm_tkeep = {4{1'b1}};
assign m_axis_s2mm_tdata = s_axis_rtemp_tdata;
assign m_axis_s2mm_tlast = s_axis_rtemp_tlast;
assign m_axis_s2mm_tvalid = s_axis_rtemp_tvalid & s2mm_xfer_ena;
assign s_axis_rtemp_tready = s2mm_xfer_ena & m_axis_s2mm_tready;
// MM2S
reg mm2s_xfer_ena = 1'b0;
reg slave_select = 1'b0;
assign m_axis_bias_tdata = s_axis_mm2s_tdata;
assign m_axis_bias_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == BIAS_ROW_FIFO_ID);
assign m_axis_bias_tlast = s_axis_mm2s_tlast;
assign m_axis_sensor_cmd_tdata = s_axis_mm2s_tdata;
assign m_axis_sensor_cmd_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == SENSOR_CMD_ID);
assign m_axis_sensor_cmd_tlast = s_axis_mm2s_tlast;
reg slave_axis_tready;
always @(*) begin
(* parallel_case *)
case (slave_select)
BIAS_ROW_FIFO_ID: slave_axis_tready = m_axis_bias_tready;
SENSOR_CMD_ID: slave_axis_tready = m_axis_sensor_cmd_tready;
endcase
end
assign s_axis_mm2s_tready = slave_axis_tready & mm2s_xfer_ena;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Main data streaming module. Current FSM manages
* data movement by AXI-DataMover IP-core */
localparam [3:0] ST_ERROR = 4'd0,
ST_RESET = 4'd1,
ST_WAIT_EOL = 4'd2,
ST_SEND_BIAS_ROW = 4'd3,
ST_GET_ROW_TEMP = 4'd4,
ST_SEND_SENSOR_CMD = 4'd5,
ST_DATMOV_S2MM_CMD_0 = 4'd6,
ST_DATMOV_S2MM_CMD_1 = 4'd7,
ST_DATMOV_S2MM_XFER = 4'd8,
ST_GET_S2MM_XFER_STAT = 4'd9,
ST_DATMOV_MM2S_CMD_0 = 4'd10,
ST_DATMOV_MM2S_CMD_1 = 4'd11,
ST_DATMOV_MM2S_XFER = 4'd12,
ST_GET_MM2S_XFER_STAT = 4'd13;
reg [3:0] state = ST_RESET;
reg [3:0] state_next = ST_RESET;
reg eol_flag = 1'b0;
reg [31:0] rtemp_frame_ptr = {32{1'b0}};
reg [31:0] bias_frame_ptr = {32{1'b0}};
reg [31:0] byte_offset;
reg [22:0] btt_cnt;
wire [71:0] datmov_cmd = {
4'b0000, // RSVD
4'b0000, // TAG (Command TAG)
byte_offset, // Memory address byte offset
1'b0, // DRR (DRE ReAlignment Request)
1'b1, // EOF (End of Frame)
6'b000000, // DSA (DRE Stream Alignment)
1'b1, // Access type (0 - fix, 1 - inc)
btt_cnt // Bytes to transfer count
};
always @(posedge axi_aclk) begin
if (~axi_aresetn | ~ctrl_reg[31]) begin
mm2s_xfer_ena <= 1'b0;
s2mm_xfer_ena <= 1'b0;
state <= ST_RESET;
end else begin
/* Reset frame pointers at the SOF */
if (sof_strb) begin
bias_frame_ptr <= bias_buf_addr;
rtemp_frame_ptr <= rtemp_buf_addr;
eol_flag <= 1'b1; // to fill all FIFOs at SOF
end
/* Registering EOL flag */
if (eol_strb) begin
eol_flag <= 1'b1;
end
/* Data management FSM */
case (state)
/* Unrecoverable error */
ST_ERROR: begin
state <= state;
end
ST_RESET: begin
mm2s_xfer_ena <= 1'b0;
s2mm_xfer_ena <= 1'b0;
if (sof_strb) begin
state <= ST_WAIT_EOL;
end
end
ST_WAIT_EOL: begin
if (eol_flag) begin
eol_flag <= 1'b0;
state <= ST_SEND_BIAS_ROW;
end
end
ST_SEND_BIAS_ROW: begin
if (~fifo_bias_prog_full) begin
slave_select <= BIAS_ROW_FIFO_ID;
byte_offset <= bias_frame_ptr;
bias_frame_ptr <= bias_frame_ptr + bias_btt;
btt_cnt <= bias_btt[22:0];
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_GET_ROW_TEMP;
end else begin
state <= ST_GET_ROW_TEMP;
end
end
ST_GET_ROW_TEMP: begin
if (s_axis_rtemp_tvalid) begin
byte_offset <= rtemp_frame_ptr;
rtemp_frame_ptr <= rtemp_frame_ptr + rtemp_btt;
btt_cnt <= rtemp_btt[22:0];
state <= ST_DATMOV_S2MM_CMD_0;
state_next <= ST_SEND_SENSOR_CMD;
end else begin
state <= ST_SEND_SENSOR_CMD;
end
end
ST_SEND_SENSOR_CMD: begin
slave_select <= SENSOR_CMD_ID;
byte_offset <= cmd_buf_addr;
btt_cnt <= cmd_btt[22:0];
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_WAIT_EOL;
end
/* Generate S2MM command for DataMover */
ST_DATMOV_S2MM_CMD_0: begin
m_axis_s2mm_cmd_tdata <= datmov_cmd;
m_axis_s2mm_cmd_tvalid <= 1'b1;
state <= ST_DATMOV_S2MM_CMD_1;
end
/* Wait S2MM command to be accepted */
ST_DATMOV_S2MM_CMD_1: begin
if (m_axis_s2mm_cmd_tready) begin
m_axis_s2mm_cmd_tvalid <= 1'b0;
s2mm_xfer_ena <= 1'b1;
state <= ST_DATMOV_S2MM_XFER;
end
end
/* Wait S2MM transfer to be done */
ST_DATMOV_S2MM_XFER: begin
if (m_axis_s2mm_tvalid & m_axis_s2mm_tready & m_axis_s2mm_tlast) begin
s2mm_xfer_ena <= 1'b0;
s_axis_s2mm_sts_tready <= 1'b1;
state <= ST_GET_S2MM_XFER_STAT;
end
end
/* Check S2MM transfer status */
ST_GET_S2MM_XFER_STAT: begin
if (s_axis_s2mm_sts_tvalid) begin
s_axis_s2mm_sts_tready <= 1'b0;
if (s_axis_s2mm_sts_tdata[7:4] == DMA_XFER_OKAY) begin
state <= state_next;
end else begin
state <= ST_ERROR;
end
end
end
/* Generate MM2S command for DataMover */
ST_DATMOV_MM2S_CMD_0: begin
m_axis_mm2s_cmd_tdata <= datmov_cmd;
m_axis_mm2s_cmd_tvalid <= 1'b1;
state <= ST_DATMOV_MM2S_CMD_1;
end
/* Wait MM2S command to be accepted */
ST_DATMOV_MM2S_CMD_1: begin
if (m_axis_mm2s_cmd_tready) begin
m_axis_mm2s_cmd_tvalid <= 1'b0;
mm2s_xfer_ena <= 1'b1;
state <= ST_DATMOV_MM2S_XFER;
end
end
/* Wait MM2S transfer to be done */
ST_DATMOV_MM2S_XFER: begin
if (s_axis_mm2s_tvalid & s_axis_mm2s_tready & s_axis_mm2s_tlast) begin
mm2s_xfer_ena <= 1'b0;
s_axis_mm2s_sts_tready <= 1'b1;
state <= ST_GET_MM2S_XFER_STAT;
end
end
/* Check MM2S transfer status */
ST_GET_MM2S_XFER_STAT: begin
if (s_axis_mm2s_sts_tvalid) begin
s_axis_mm2s_sts_tready <= 1'b0;
if (s_axis_mm2s_sts_tdata[7:4] == DMA_XFER_OKAY) begin
state <= state_next;
end else begin
state <= ST_ERROR;
end
end
end
default: begin
state <= ST_ERROR;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign sensor_bias_volt_sel = ctrl_reg[1];
assign sensor_bias_boost_pwr_ena = ctrl_reg[2];
assign sensor_bias_pwr_ena = ctrl_reg[3];
assign sensor_core_pwr_ena = ctrl_reg[4];
assign sensor_io_pwr_ena_n = ~ctrl_reg[5];
assign sensor_rstn = ctrl_reg[6];
endmodule |
module ISC0901_capture
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire rstn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS_BIAS:S_AXIS_CMD:M_AXIS_IMG:M_AXIS_RTEMP, ASSOCIATED_RESET rstn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire clk,
/* Sensor interface */
output wire sensor_clk_fwd,
output wire sensor_cmd,
output wire sensor_bias,
input wire sensor_data_odd,
input wire sensor_data_even,
/* Auxiliary control output */
output reg fifo_aresetn = 1'b1,
output reg sof = 1'b0,
output wire eol,
/* Sensor bias data stream */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_BIAS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_BIAS TDATA" *) input wire [31:0] s_axis_bias_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_BIAS TVALID" *) input wire s_axis_bias_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_BIAS TREADY" *) output reg s_axis_bias_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_BIAS TLAST" *) input wire s_axis_bias_tlast,
/* Sensor command stream*/
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_CMD, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CMD TDATA" *) input wire [31:0] s_axis_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CMD TVALID" *) input wire s_axis_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CMD TREADY" *) output reg s_axis_cmd_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CMD TLAST" *) input wire s_axis_cmd_tlast,
/* Captured sensor data stream */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_IMG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TDATA" *) output wire [31:0] m_axis_img_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TVALID" *) output wire m_axis_img_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TREADY" *) input wire m_axis_img_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TLAST" *) output wire m_axis_img_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TUSER" *) output wire m_axis_img_tuser,
/* Captured sensor data stream */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_RTEMP, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RTEMP TDATA" *) output wire [31:0] m_axis_rtemp_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RTEMP TVALID" *) output wire m_axis_rtemp_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RTEMP TREADY" *) input wire m_axis_rtemp_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RTEMP TLAST" *) output wire m_axis_rtemp_tlast
);
localparam SENSOR_RES_X = 336;
localparam SENSOR_RES_Y = 256;
localparam BITS_PER_PIXEL = 14;
localparam FRAME_PERIOD = 1228500; // Clock cycles at 73.636MHz
localparam LINE_PERIOD = 4676; // Clock cycles at 73.636MHz
localparam EXTRA_LINE_NUM = 3; // Some meaningless 3 lines at the beginning of each new frame, that do not reflect image content, probably pipeline garbage???
localparam LINE_NUM = (SENSOR_RES_Y + EXTRA_LINE_NUM);
localparam FULL_ROW_TICS = (((SENSOR_RES_X / 2) + 1) * BITS_PER_PIXEL); // Full row duration including 14-bit preamble (14'b10101010101010) at the beginning of each line (+1)
localparam CMD_SIZE = 20; // Command size in bytes
localparam CMD_VEC_LEN = CMD_SIZE * 8 + 16; // Total command word length including 16-bit preamble
localparam CMD_VEC_PREAMBLE = 16'h3fc0; // Command preamble (Interesting: 0x3f = ~0xc0)
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [13:0] pixel_odd = {14{1'b0}};
reg [13:0] pixel_even = {14{1'b0}};
reg [31:0] frame_tc = {32{1'b0}};
reg [15:0] line_tc = {16{1'b0}};
reg [8:0] line_cnt = {9{1'b0}};
reg line_last = 1'b0;
reg cmd_valid_wnd = 1'b0;
reg line_valid_wnd = 1'b0;
reg rtemp_valid = 1'b0;
reg [3:0] pixel_tc = 4'h0;
reg pixel_valid = 1'b0;
reg [7:0] pixel_num = 8'h00;
reg pixel_last = 1'b0;
reg pixel_visible = 1'b0;
reg bias_valid_wnd = 1'b0;
reg [4:0] quad_bias_rd_tc = 5'd1;
reg quad_bias_load = 1'b0;
wire data_valid_wnd = line_valid_wnd & (line_cnt >= EXTRA_LINE_NUM) & (line_tc > (BITS_PER_PIXEL + 1));
wire ext_valid_wnd = line_valid_wnd & (line_cnt >= 0) & (line_cnt < EXTRA_LINE_NUM) & (line_tc > (BITS_PER_PIXEL + 1));
always @(posedge clk) begin
if (~rstn) begin
frame_tc <= {32{1'b0}};
line_tc <= {16{1'b0}};
line_cnt <= {9{1'b0}};
line_last <= 1'b0;
sof <= 1'b0;
fifo_aresetn <= 1'b0;
cmd_valid_wnd <= 1'b0;
line_valid_wnd <= 1'b0;
rtemp_valid <= 1'b0;
pixel_tc <= 4'h0;
pixel_valid <= 1'b0;
pixel_num <= 8'h00;
pixel_last <= 1'b0;
pixel_visible <= 1'b0;
bias_valid_wnd <= 1'b0;
quad_bias_rd_tc <= 5'd1;
s_axis_bias_tready <= 1'b0;
quad_bias_load <= 1'b0;
end else begin
/* Frame counter */
if (frame_tc == FRAME_PERIOD - 1) begin
frame_tc <= {32{1'b0}};
end else begin
frame_tc <= frame_tc + 1'b1;
end
/* Line counter */
if (frame_tc > 32'd201) begin
if (line_tc == LINE_PERIOD - 1) begin
line_tc <= {16{1'b0}};
if (line_cnt < LINE_NUM) begin
line_cnt <= line_cnt + 1'b1;
end
end else begin
line_tc <= line_tc + 1'b1;
end
end else begin
line_tc <= {16{1'b0}};
line_cnt <= {9{1'b0}};
end
/* Line valid window */
if ((line_tc > 0) && (line_tc <= FULL_ROW_TICS) && (line_cnt < LINE_NUM)) begin
line_valid_wnd <= 1'b1;
end else begin
line_valid_wnd <= 1'b0;
end
line_last <= (line_cnt == (LINE_NUM - 1));
/* Bias valid window */
bias_valid_wnd <= line_valid_wnd & (line_cnt < (LINE_NUM - EXTRA_LINE_NUM)) & (line_tc < (BITS_PER_PIXEL * (SENSOR_RES_X / 2) + 2));
/* Bias read strobe */
if (bias_valid_wnd) begin
if (quad_bias_rd_tc == 5'd27) begin // load new bias for 4 pixels each 28 tics
quad_bias_rd_tc <= {5{1'b0}};
end else begin
quad_bias_rd_tc <= quad_bias_rd_tc + 1'b1;
end
if (quad_bias_rd_tc == 5'd26) begin
s_axis_bias_tready <= 1'b1;
end else begin
s_axis_bias_tready <= 1'b0;
end
quad_bias_load <= s_axis_bias_tready;
end else begin
quad_bias_rd_tc <= 5'd1;
s_axis_bias_tready <= 1'b0;
end
/* Command valid window */
cmd_valid_wnd <= (frame_tc < CMD_VEC_LEN)? 1'b1 : 1'b0;
/* Valid pixel and valid last pixel in line */
if (data_valid_wnd | ext_valid_wnd) begin
if (pixel_tc == 4'd13) begin
pixel_tc <= 4'h0;
pixel_valid <= 1'b1;
pixel_num <= pixel_num + 1'b1;
if (pixel_num == (SENSOR_RES_X / 2 - 1)) begin // assert "last" signal for AXI4-Stream at the end of the line
pixel_last <= 1'b1;
end else begin
pixel_last <= 1'b0;
end
end else begin
pixel_tc <= pixel_tc + 1'b1;
pixel_valid <= 1'b0;
pixel_last <= 1'b0;
end
end else begin
pixel_tc <= 4'b0;
pixel_valid <= 1'b0;
pixel_num <= 8'b0;
pixel_last <= 1'b0;
end
/* Separates visible pixels from extended */
pixel_visible <= data_valid_wnd;
/* Row temperature valid strobe */
rtemp_valid <= (line_tc == ((SENSOR_RES_X / 2 + 2) * BITS_PER_PIXEL + 1)) & (line_cnt >= 0) & (line_cnt < LINE_NUM);
/* Start Of Frame strobe */
sof <= (frame_tc == 32'd1222000)? 1'b1 : 1'b0;
/* FIFO reset strobe */
fifo_aresetn <= ((frame_tc > 32'd1221800) && (frame_tc < 32'd1221900))? 1'b0 : 1'b1;
end
end
/* End Of Line strobe */
assign eol = rtemp_valid;
assign m_axis_img_tdata = {2'b00, pixel_odd, 2'b00, pixel_even};
assign m_axis_img_tvalid = pixel_valid & pixel_visible;
assign m_axis_img_tlast = pixel_last;
assign m_axis_img_tuser = pixel_last & line_last;
assign m_axis_rtemp_tdata = {2'b00, pixel_odd, 2'b00, pixel_even};
assign m_axis_rtemp_tvalid = rtemp_valid;
assign m_axis_rtemp_tlast = 1'b1;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/*
* Data is coming out of the sensor over two single ended lines.
* Odd pixels are coming from the one line, even pixels - from another.
* Each 14-bit pixel (odd and even) comes from the sensor LSB first.
*/
always @(posedge clk) begin
if (~rstn) begin
pixel_odd <= {14{1'b0}};
pixel_even <= {14{1'b0}};
end else begin
pixel_odd <= {sensor_data_odd, pixel_odd[13:1]};
pixel_even <= {sensor_data_even, pixel_even[13:1]};
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/*
* Sensor pixel bias value is 7-bit long, but only 6 bits are significant.
* Current values are sent LSB first.
*/
reg [27:0] quad_bias = {28{1'b0}};
always @(posedge clk) begin
if (bias_valid_wnd) begin
if (quad_bias_load) begin
quad_bias <= {
s_axis_bias_tdata[29:24], 1'b0,
s_axis_bias_tdata[21:16], 1'b0,
s_axis_bias_tdata[13:8], 1'b0,
s_axis_bias_tdata[5:0], 1'b0
};
end else begin
quad_bias <= {quad_bias[0], quad_bias[27:1]};
end
end else begin
quad_bias <= {
s_axis_bias_tdata[29:24], 1'b0,
s_axis_bias_tdata[21:16], 1'b0,
s_axis_bias_tdata[13:8], 1'b0,
s_axis_bias_tdata[5:0], 1'b0
};
end
end
assign sensor_bias = quad_bias[0];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [CMD_SIZE * 8 - 1:0] cmd = {CMD_SIZE * 8{1'b0}};
reg cmd_valid = 1'b0;
localparam [1:0] ST_RESET = 2'd0,
ST_IDLE = 2'd1,
ST_LOAD = 2'd2;
reg [1:0] state = ST_RESET;
/* AXI4-Stream command word reception FSM */
always @(posedge clk) begin
if (~rstn) begin
s_axis_cmd_tready <= 1'b0;
cmd_valid <= 1'b0;
state <= ST_RESET;
end else begin
case (state)
ST_RESET: begin
s_axis_cmd_tready <= 1'b0;
cmd_valid <= 1'b0;
state <= ST_IDLE;
end
ST_IDLE: begin
if (s_axis_cmd_tvalid) begin
s_axis_cmd_tready <= 1'b1;
cmd_valid <= 1'b0;
state <= ST_LOAD;
end
end
ST_LOAD: begin
if (s_axis_cmd_tvalid) begin
cmd <= {s_axis_cmd_tdata, cmd[CMD_SIZE * 8 - 1:32]};
if (s_axis_cmd_tlast) begin
s_axis_cmd_tready <= 1'b0;
cmd_valid <= 1'b1;
state <= ST_IDLE;
end
end
end
default: begin
state <= ST_RESET;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [CMD_VEC_LEN - 1:0] sensor_cmd_shreg = {CMD_VEC_PREAMBLE, {CMD_SIZE * 8{1'b0}}};
/* Sensor command word updating process */
always @(posedge clk) begin
if (~rstn) begin
sensor_cmd_shreg <= {CMD_VEC_PREAMBLE, {CMD_SIZE * 8{1'b0}}};
end else begin
if (cmd_valid_wnd) begin
sensor_cmd_shreg <= {sensor_cmd_shreg[CMD_VEC_LEN - 2:0], sensor_cmd_shreg[CMD_VEC_LEN - 1]};
end else begin
if (cmd_valid) begin
sensor_cmd_shreg <= {CMD_VEC_PREAMBLE, cmd};
end
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/*
* Forwarded clock (sensor_clk_fwd) is a full copy of the internal system clock (clk).
* Sensor is working at the falling clock edge.
* ______ ______ ______ ______
* / \ / \ / \ / \
* clk / sensor_clk_fwd: ____/ \______/ \______/ \______/ \______
* ____ ______________ ______________ ______________ ______________
* \/ \/ \/ \/
* sensor_cmd: ____/\______________/\______________/\______________/\______________
* ____________ ______________ ______________ ______________ ______
* \/ \/ \/ \/
* Sensor data odd: ____________/\______________/\______________/\______________/\______
* ____________ ______________ ______________ ______________ ______
* \/ \/ \/ \/
* Sensor data even: ____________/\______________/\______________/\______________/\______
*/
/* Sensor clock buffer */
ODDR #
(
.DDR_CLK_EDGE ( "SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "SYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_sensor_clk_fwd
(
.Q ( sensor_clk_fwd ), // 1-bit DDR output
.C ( clk ), // 1-bit clock input
.CE ( rstn ), // 1-bit clock enable input
.D1 ( 1'b1 ), // 1-bit data input (positive edge)
.D2 ( 1'b0 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
/* Sensor data buffer */
ODDR #
(
.DDR_CLK_EDGE ( "SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "SYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_sensor_data_fwd
(
.Q ( sensor_cmd ), // 1-bit DDR output
.C ( clk ), // 1-bit clock input
.CE ( rstn ), // 1-bit clock enable input
.D1 ( sensor_cmd_shreg[CMD_VEC_LEN - 1] ), // 1-bit data input (positive edge)
.D2 ( sensor_cmd_shreg[CMD_VEC_LEN - 1] ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
endmodule |
module power_switch_fsm #
(
parameter integer CLK_HZ = 0
)
(
input wire clk,
input wire btn_pressed,
input wire pwr_off_req,
output reg fd_clk = 1'b0,
output reg fd_dat = 1'b0
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Checking input parameters */
generate
if ((CLK_HZ < 1000) || (CLK_HZ > 150000000)) begin
//INVALID_PARAMETER invalid_parameter_msg();
initial begin
$error("Invalid parameter!");
end
end
endgenerate
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [31:0] BUTTON_PRESS_DELAY = CLK_HZ, // 1 sec delay for on/off
FD_SETUP_HOLD_DELAY = 100;
reg [31:0] delay_tc = {32{1'b0}};
localparam [2:0] ST_RESET = 3'd0,
ST_DELAY = 3'd1,
ST_PWR_ON_0 = 3'd2,
ST_PWR_ON_1 = 3'd3,
ST_PWR_ON_2 = 3'd4,
ST_IDLE = 3'd5,
ST_PWR_OFF = 3'd6;
reg [2:0] state = ST_RESET;
reg [2:0] next_state = ST_RESET;
always @(posedge clk) begin
case (state)
ST_RESET: begin
fd_clk <= 1'b0;
fd_dat <= 1'b0;
delay_tc <= BUTTON_PRESS_DELAY;
state <= ST_DELAY;
next_state <= ST_PWR_ON_0;
end
ST_DELAY: begin
if (delay_tc == 32'd0) begin
state <= next_state;
end else begin
delay_tc <= delay_tc - 1'b1;
end
end
ST_PWR_ON_0: begin
fd_dat <= 1'b1;
delay_tc <= FD_SETUP_HOLD_DELAY;
state <= ST_DELAY;
next_state <= ST_PWR_ON_1;
end
ST_PWR_ON_1: begin
fd_clk <= 1'b1;
delay_tc <= FD_SETUP_HOLD_DELAY;
state <= ST_DELAY;
next_state <= ST_PWR_ON_2;
end
ST_PWR_ON_2: begin
fd_clk <= 1'b0;
/* Wait power button release */
if (~btn_pressed) begin
state <= ST_IDLE;
end
end
ST_IDLE: begin
/* Immediately power off */
if (pwr_off_req) begin
fd_dat <= 1'b0;
state <= ST_PWR_OFF;
end
/* Emergency manual power off with 5 sec button press delay */
if (btn_pressed) begin
delay_tc <= delay_tc + 1'b1;
if (delay_tc > BUTTON_PRESS_DELAY * 5) begin
fd_dat <= 1'b0;
state <= ST_PWR_OFF;
end
end else begin
delay_tc <= 32'd0;
end
end
ST_PWR_OFF: begin
fd_clk <= ~fd_clk;
delay_tc <= FD_SETUP_HOLD_DELAY;
state <= ST_DELAY;
next_state <= ST_PWR_OFF;
end
default: begin
fd_dat <= 1'b0;
state <= ST_PWR_OFF;
end
endcase
end
endmodule |
module i2c_interconnect
(
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_I" *) output wire s0_scl_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_O" *) input wire s0_scl_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SCL_T" *) input wire s0_scl_t,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_I" *) output wire s0_sda_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_O" *) input wire s0_sda_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S0_IIC SDA_T" *) input wire s0_sda_t,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_I" *) output wire s1_scl_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_O" *) input wire s1_scl_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SCL_T" *) input wire s1_scl_t,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_I" *) output wire s1_sda_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_O" *) input wire s1_sda_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 S1_IIC SDA_T" *) input wire s1_sda_t,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_I" *) input wire m_scl_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_O" *) output wire m_scl_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SCL_T" *) output wire m_scl_t,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_I" *) input wire m_sda_i,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_O" *) output wire m_sda_o,
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 M_IIC SDA_T" *) output wire m_sda_t
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign s0_scl_i = m_scl_i;
assign s1_scl_i = m_scl_i;
assign s0_sda_i = m_sda_i;
assign s1_sda_i = m_sda_i;
assign m_scl_o = s0_scl_o & s1_scl_o;
assign m_scl_t = s0_scl_t & s1_scl_t;
assign m_sda_o = s0_sda_o & s1_sda_o;
assign m_sda_t = s0_sda_t & s1_sda_t;
endmodule |
module fx2lp_master #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire s_axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE, ASSOCIATED_RESET s_axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire s_axi_aclk,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET s_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [7:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output reg s_axis_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_arst_n" *) input wire sfifo_arst_n,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_ifclk" *) output wire sfifo_ifclk,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_dq" *) output wire [7:0] sfifo_dq,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_addr" *) output wire [1:0] sfifo_addr,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_slrd_n" *) output wire sfifo_slrd_n,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_slwr_n" *) output wire sfifo_slwr_n,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_sloe_n" *) output wire sfifo_sloe_n,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_pktend_n" *) output wire sfifo_pktend_n,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_flag_a" *) input wire sfifo_flag_a,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_flag_b" *) input wire sfifo_flag_b,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_flag_c" *) input wire sfifo_flag_c,
(* X_INTERFACE_INFO = "Cypress:user:SFIFO:1.0 SFIFO sfifo_flag_d" *) input wire sfifo_flag_d,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
output wire master_arst_n
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam UVC_HEADER_SIZE = 2;
localparam [1:0] EP2_FIFO_ADDR = 2'b00,
EP4_FIFO_ADDR = 2'b01,
EP6_FIFO_ADDR = 2'b10,
EP8_FIFO_ADDR = 2'b11;
localparam [7:0] HDR_FID_BIT = 8'h01, // Frame identifier (toggles each frame start boundary)
HDR_EOF_BIT = 8'h02, // End of frame (should be set for the last frame packet header)
HDR_PTS_BIT = 8'h04, // PTS (Presentation Time Stamp) is present
HDR_SCR_BIT = 8'h08, // SCR (Source Clock Reference) is present
HDR_RES_BIT = 8'h10, // Reserved (should be zero)
HDR_STI_BIT = 8'h20, // Still image
HDR_ERR_BIT = 8'h40, // Error bit
HDR_EOH_BIT = 8'h80; // End of header
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
wire [31:0] stat_reg;
reg [31:0] ch_config = {32{1'b0}};
always @(posedge s_axi_aclk) begin
if (~s_axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[7:2])
6'd0 : ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
/* 6'd1 : read only register */
6'd2 : ch_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch_config[i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[7:2])
6'd0 : s_axi_rdata <= ctrl_reg;
6'd1 : s_axi_rdata <= stat_reg;
6'd2 : s_axi_rdata <= ch_config;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
assign master_arst_n = ctrl_reg[31];
wire [15:0] img_res_x = ch_config[15:0];
wire [15:0] img_res_y = ch_config[31:16];
assign stat_reg = 32'hDEADFACE;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire sfifo_rst_n;
sync_cdc_bit #
(
.C_SYNC_STAGES (3)
)
sync_cdc_bit_inst
(
.clk ( s_axis_aclk ),
.d ( sfifo_arst_n ),
.q ( sfifo_rst_n )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [2:0] ST_RST = 3'd0,
ST_WAIT_EOF = 3'd1,
ST_IDLE = 3'd2,
ST_UVC_HEADER = 3'd3,
ST_DATA = 3'd4,
ST_STOP = 3'd5,
ST_DELAY = 3'd6;
reg [2:0] state = ST_RST;
reg [7:0] hdr_cnt = 8'd0;
reg [15:0] burst_cnt = 16'd0;
reg [15:0] line_cnt = 16'd0;
reg hdr_fid = 1'b0;
reg hdr_eof = 1'b0;
reg [3:0] hdb_byte = 4'h0;
reg slwr_n = 1'b1;
reg pktend_n = 1'b1;
reg [7:0] dq = 8'h00;
wire fx2_fifo_empty = ~sfifo_flag_a;
wire fx2_fifo_full = ~sfifo_flag_b;
always @(posedge s_axis_aclk) begin
if (~s_axis_aresetn | ~sfifo_rst_n) begin
slwr_n <= 1'b1;
pktend_n <= 1'b1;
s_axis_tready <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
hdr_fid <= 1'b0;
hdr_eof <= 1'b0;
slwr_n <= 1'b1;
s_axis_tready <= 1'b0;
line_cnt <= img_res_y;
if (fx2_fifo_empty) begin
pktend_n <= 1'b1;
state <= ST_WAIT_EOF;
end else begin
pktend_n <= 1'b0;
end
end
ST_WAIT_EOF: begin
if (s_axis_tvalid & s_axis_tready & s_axis_tuser) begin
s_axis_tready <= 1'b0;
state <= ST_IDLE;
end else begin
s_axis_tready <= 1'b1;
end
end
ST_IDLE: begin
slwr_n <= 1'b1;
pktend_n <= 1'b1;
if (fx2_fifo_empty) begin
hdr_cnt <= 8'd0;
state <= ST_UVC_HEADER;
end
end
ST_UVC_HEADER: begin
case (hdr_cnt)
8'd0: dq <= UVC_HEADER_SIZE;
8'd1: begin
dq <= HDR_EOH_BIT | (hdr_eof? HDR_EOF_BIT : 1'b0) | (hdr_fid? HDR_FID_BIT : 1'b0);
hdr_eof <= 1'b0;
end
default: dq <= 8'h00;
endcase
if (hdr_cnt == UVC_HEADER_SIZE) begin
slwr_n <= 1'b1;
s_axis_tready <= 1'b1;
burst_cnt <= img_res_x << 1; // YUYV 4:2:2 mode, i.e. two bytes per pixel
state <= ST_DATA;
end else begin
slwr_n <= 1'b0;
hdr_cnt <= hdr_cnt + 1'b1;
end
end
ST_DATA: begin
dq <= s_axis_tdata;
slwr_n <= ~(s_axis_tvalid & s_axis_tready);
if (s_axis_tvalid & s_axis_tready) begin
if (burst_cnt > 16'd1) begin
burst_cnt <= burst_cnt - 1'b1;
end else begin
line_cnt <= line_cnt - 1'b1;
pktend_n <= 1'b0;
s_axis_tready <= 1'b0;
state <= ST_STOP;
end
end
end
ST_STOP: begin
slwr_n <= 1'b1;
pktend_n <= 1'b1;
s_axis_tready <= 1'b0;
if (line_cnt == 16'd1) begin
hdr_eof <= 1'b1;
end else begin
if (line_cnt == 16'd0) begin
hdr_fid <= ~hdr_fid;
line_cnt <= img_res_y;
end
end
state <= ST_IDLE;
end
default: begin
state <= ST_RST;
end
endcase
end
end
assign sfifo_dq = dq;
assign sfifo_addr = EP2_FIFO_ADDR;
assign sfifo_slrd_n = 1'b1;
assign sfifo_slwr_n = slwr_n;
assign sfifo_sloe_n = 1'b1;
assign sfifo_pktend_n = pktend_n;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_ifclk
(
.Q ( sfifo_ifclk ), // 1-bit DDR output
.C ( s_axis_aclk ), // 1-bit clock input
.CE ( s_axis_aresetn ), // 1-bit clock enable input
.D1 ( 1'b0 ), // 1-bit data input (positive edge)
.D2 ( 1'b1 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
endmodule |
module axis_frame_averager #
(
parameter AVERAGER_BYPASS = 1
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS_AVGI:M_AXIS_AVGO:S_AXIS_IMG:M_AXIS_IMG, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
input wire [2:0] average_level,
input wire sof_strb,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_AVGI, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGI TDATA" *) input wire [31:0] s_axis_avgi_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGI TVALID" *) input wire s_axis_avgi_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGI TREADY" *) output wire s_axis_avgi_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGI TLAST" *) input wire s_axis_avgi_tlast,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_AVGO, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGO TDATA" *) output wire [31:0] m_axis_avgo_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGO TVALID" *) output wire m_axis_avgo_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGO TREADY" *) input wire m_axis_avgo_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGO TLAST" *) output wire m_axis_avgo_tlast,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_IMG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TDATA" *) input wire [31:0] s_axis_img_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TVALID" *) input wire s_axis_img_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TREADY" *) output wire s_axis_img_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TLAST" *) input wire s_axis_img_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TUSER" *) input wire s_axis_img_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_IMG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TDATA" *) output wire [31:0] m_axis_img_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TVALID" *) output wire m_axis_img_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TREADY" *) input wire m_axis_img_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TLAST" *) output wire m_axis_img_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG TUSER" *) output wire m_axis_img_tuser
);
localparam DSP_PIPE_DELAY = 4;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
generate
if (AVERAGER_BYPASS == 0) begin
reg avg_pix_tvalid = 1'b0;
reg [6:0] avg_frame_cnt = 7'd0;
reg [6:0] avg_ref_value = 7'd0;
reg [2:0] average_level_1 = 3'd0;
reg [31:0] dsp_C_mask = {32{1'b0}};
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
avg_pix_tvalid <= 1'b0;
dsp_C_mask <= {32{1'b0}};
end else begin
if (sof_strb) begin
if (average_level_1 != 3'd0) begin
if (avg_frame_cnt == 7'd0) begin
avg_pix_tvalid <= 1'b0;
avg_frame_cnt <= avg_frame_cnt + 1'b1;
average_level_1 <= average_level;
dsp_C_mask <= {32{1'b0}};
end else begin
if (avg_frame_cnt == avg_ref_value) begin
avg_pix_tvalid <= 1'b1;
avg_frame_cnt <= 7'd0;
end else begin
avg_pix_tvalid <= 1'b0;
avg_frame_cnt <= avg_frame_cnt + 1'b1;
end
dsp_C_mask <= {32{1'b1}};
end
end else begin
average_level_1 <= average_level;
avg_pix_tvalid <= 1'b1;
avg_frame_cnt <= 7'd0;
dsp_C_mask <= {32{1'b0}};
end
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [15:0] m_axis_wcd_tdata;
wire m_axis_wcd_tvalid;
wire m_axis_wcd_tready;
wire m_axis_wcd_tlast;
wire [1:0] m_axis_wcd_tuser;
AXIS_WC_4_TO_2 AXIS_WC_4_TO_2_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tvalid ( s_axis_img_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( s_axis_img_tready ), // output wire s_axis_tready
.s_axis_tdata ( s_axis_img_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tlast ( s_axis_img_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( {s_axis_img_tuser, 3'b000} ), // input wire [3 : 0] s_axis_tuser
.m_axis_tvalid ( m_axis_wcd_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcd_tready ), // input wire m_axis_tready
.m_axis_tdata ( m_axis_wcd_tdata ), // output wire [15 : 0] m_axis_tdata
.m_axis_tlast ( m_axis_wcd_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcd_tuser ) // output wire [1 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [47:0] dsp_P_tdata;
wire dsp_P_tvalid;
wire dsp_P_tready;
wire dsp_P_tlast;
wire dsp_P_tuser;
/* P = (D-A)*B+C */
axis_dsp_linear_func #
(
.TUSER_WIDTH(1)
)
axis_dsp_linear_func_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.dsp_func_sel ( 1'b0 ), // (D-A)*B+C
.dsp_D_s_axis_tdata ({{4{1'b0}}, m_axis_wcd_tdata[13:0]}),
.dsp_D_s_axis_tvalid ( m_axis_wcd_tvalid ),
.dsp_D_s_axis_tready ( m_axis_wcd_tready ),
.dsp_D_s_axis_tlast ( m_axis_wcd_tlast ),
.dsp_D_s_axis_tuser ( m_axis_wcd_tuser[1] ),
.dsp_A_s_axis_tdata ( 18'd0 ),
.dsp_A_s_axis_tvalid ( 1'b1 ),
.dsp_A_s_axis_tready ( /*------NC------*/ ),
.dsp_A_s_axis_tlast ( 1'b1 ),
.dsp_A_s_axis_tuser ( 1'b0 ),
.dsp_B_s_axis_tdata ( 18'd1 ),
.dsp_B_s_axis_tvalid ( 1'b1 ),
.dsp_B_s_axis_tready ( /*------NC------*/ ),
.dsp_B_s_axis_tlast ( 1'b1 ),
.dsp_B_s_axis_tuser ( 1'b0 ),
.dsp_C_s_axis_tdata ( {{16{1'b0}}, s_axis_avgi_tdata & dsp_C_mask}),
.dsp_C_s_axis_tvalid ( s_axis_avgi_tvalid ),
.dsp_C_s_axis_tready ( s_axis_avgi_tready ),
.dsp_C_s_axis_tlast ( s_axis_avgi_tlast ),
.dsp_C_s_axis_tuser ( 1'b0 ),
.dsp_P_m_axis_tdata ( dsp_P_tdata ),
.dsp_P_m_axis_tvalid ( dsp_P_tvalid ),
.dsp_P_m_axis_tready ( dsp_P_tready ),
.dsp_P_m_axis_tlast ( dsp_P_tlast ),
.dsp_P_m_axis_tuser ( dsp_P_tuser )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [31:0] m0_axis_tdata;
wire m0_axis_tvalid;
wire m0_axis_tready;
wire m0_axis_tlast;
wire m0_axis_tuser;
wire [31:0] m1_axis_tdata;
wire m1_axis_tvalid;
wire m1_axis_tready;
wire m1_axis_tlast;
axis_2w_splitter #
(
.AXIS_TDATA_WIDTH (32),
.AXIS_TUSER_WIDTH (1)
)
axis_2w_splitter_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( dsp_P_tdata[31:0] ),
.s_axis_tvalid ( dsp_P_tvalid ),
.s_axis_tready ( dsp_P_tready ),
.s_axis_tlast ( dsp_P_tlast ),
.s_axis_tuser ( dsp_P_tuser ),
.m_axis_0_tdata ( m0_axis_tdata ),
.m_axis_0_tvalid ( m0_axis_tvalid ),
.m_axis_0_tready ( m0_axis_tready ),
.m_axis_0_tlast ( m0_axis_tlast ),
.m_axis_0_tuser ( m0_axis_tuser ),
.m_axis_1_tdata ( m1_axis_tdata ),
.m_axis_1_tvalid ( m1_axis_tvalid ),
.m_axis_1_tready ( m1_axis_tready ),
.m_axis_1_tlast ( m1_axis_tlast ),
.m_axis_1_tuser ( /*-----NC-----*/ )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [13:0] avg_result;
always @(*) begin
case (average_level_1)
/* No averaging */
3'd0: begin
avg_ref_value = 7'd0;
avg_result = m0_axis_tdata[13:0];
end
/* 2x averaging */
3'd1: begin
avg_ref_value = 7'd1;
avg_result = m0_axis_tdata[14:1];
end
/* 4x averaging */
3'd2: begin
avg_ref_value = 7'd3;
avg_result = m0_axis_tdata[15:2];
end
/* 8x averaging */
3'd3: begin
avg_ref_value = 7'd7;
avg_result = m0_axis_tdata[16:3];
end
/* 16x averaging */
3'd4: begin
avg_ref_value = 7'd15;
avg_result = m0_axis_tdata[17:4];
end
/* 32x averaging */
3'd5: begin
avg_ref_value = 7'd31;
avg_result = m0_axis_tdata[18:5];
end
/* 64x averaging */
3'd6: begin
avg_ref_value = 7'd63;
avg_result = m0_axis_tdata[19:6];
end
/* 128x averaging */
3'd7: begin
avg_ref_value = 7'd127;
avg_result = m0_axis_tdata[20:7];
end
endcase
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [31:0] m_axis_wcu_tdata;
wire m_axis_wcu_tvalid;
wire m_axis_wcu_tready;
wire m_axis_wcu_tlast;
wire [3:0] m_axis_wcu_tuser;
AXIS_WC_2_TO_4 AXIS_WC_2_TO_4_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tvalid ( m0_axis_tvalid & avg_pix_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( m0_axis_tready ), // output wire s_axis_tready
.s_axis_tdata ( {{2{1'b0}}, avg_result} ), // input wire [15 : 0] s_axis_tdata
.s_axis_tlast ( m0_axis_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( {m0_axis_tuser, 1'b0} ), // input wire [1 : 0] s_axis_tuser
.m_axis_tvalid ( m_axis_wcu_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcu_tready ), // input wire m_axis_tready
.m_axis_tdata ( m_axis_wcu_tdata ), // output wire [31 : 0] m_axis_tdata
.m_axis_tkeep ( /*------------NC------------*/ ), // output wire [3 : 0] m_axis_tkeep
.m_axis_tlast ( m_axis_wcu_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcu_tuser ) // output wire [3 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign m_axis_img_tdata = m_axis_wcu_tdata;
assign m_axis_img_tvalid = m_axis_wcu_tvalid;
assign m_axis_img_tlast = m_axis_wcu_tlast;
assign m_axis_img_tuser = m_axis_wcu_tuser[3];
assign m_axis_wcu_tready = m_axis_img_tready;
assign m_axis_avgo_tdata = m1_axis_tdata;
assign m_axis_avgo_tvalid = m1_axis_tvalid;
assign m_axis_avgo_tlast = m1_axis_tlast;
assign m1_axis_tready = m_axis_avgo_tready;
end else begin
assign s_axis_avgi_tready = 1'b0;
assign m_axis_avgo_tdata = {32{1'b0}};
assign m_axis_avgo_tvalid = 1'b0;
assign m_axis_avgo_tlast = 1'b0;
assign m_axis_img_tdata = s_axis_img_tdata;
assign m_axis_img_tvalid = s_axis_img_tvalid;
assign m_axis_img_tlast = s_axis_img_tlast;
assign m_axis_img_tuser = s_axis_img_tuser;
assign s_axis_img_tready = m_axis_img_tready;
end
endgenerate
endmodule |
module dip_ctrl #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE:S_AXIS_RAW:S_AXIS_EQUAL:S_AXIS_EQUAL_X2:M_AXIS_GAIN:M_AXIS_OFST:M_AXIS_AVGI:S_AXIS_AVGO:S_AXIS_MM2S:M_AXIS_S2MM:M_AXIS_MM2S_CMD:S_AXIS_MM2S_STS:M_AXIS_S2MM_CMD:S_AXIS_S2MM_STS, ASSOCIATED_RESET axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axi_aclk,
input wire sof_strb,
input wire eol_strb,
output wire [2:0] avg_level,
output wire nuc_bypass,
output wire bpr_bypass,
input wire fifo_raw_prog_empty,
input wire fifo_avgo_prog_empty,
input wire fifo_equal_prog_empty,
input wire fifo_equal_x2_prog_empty,
input wire fifo_avgi_prog_full,
input wire fifo_gain_prog_full,
input wire fifo_ofst_prog_full,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
/* Slave AXIS sensor raw image row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_RAW, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TDATA" *) input wire [31:0] s_axis_raw_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TVALID" *) input wire s_axis_raw_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TREADY" *) output wire s_axis_raw_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TLAST" *) input wire s_axis_raw_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TUSER" *) input wire s_axis_raw_tuser,
/* Slave AXIS equalized image row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_EQUAL, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL TDATA" *) input wire [31:0] s_axis_equal_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL TVALID" *) input wire s_axis_equal_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL TREADY" *) output wire s_axis_equal_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL TLAST" *) input wire s_axis_equal_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL TUSER" *) input wire s_axis_equal_tuser,
/* Slave AXIS equalized image row (x2 upscaled) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_EQUAL_X2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL_X2 TDATA" *) input wire [31:0] s_axis_equal_x2_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL_X2 TVALID" *) input wire s_axis_equal_x2_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL_X2 TREADY" *) output wire s_axis_equal_x2_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL_X2 TLAST" *) input wire s_axis_equal_x2_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_EQUAL_X2 TUSER" *) input wire s_axis_equal_x2_tuser,
/* Master AXIS sensor NUC gain row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_GAIN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_GAIN TDATA" *) output wire [31:0] m_axis_gain_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_GAIN TVALID" *) output wire m_axis_gain_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_GAIN TREADY" *) input wire m_axis_gain_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_GAIN TLAST" *) output wire m_axis_gain_tlast,
/* Master AXIS sensor NUC offset row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_OFST, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_OFST TDATA" *) output wire [31:0] m_axis_ofst_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_OFST TVALID" *) output wire m_axis_ofst_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_OFST TREADY" *) input wire m_axis_ofst_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_OFST TLAST" *) output wire m_axis_ofst_tlast,
/* Master AXIS frame averaging output row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_AVGI, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGI TDATA" *) output wire [31:0] m_axis_avgi_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGI TVALID" *) output wire m_axis_avgi_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGI TREADY" *) input wire m_axis_avgi_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_AVGI TLAST" *) output wire m_axis_avgi_tlast,
/* Slave AXIS frame averaging input row */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_AVGO, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGO TDATA" *) input wire [31:0] s_axis_avgo_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGO TVALID" *) input wire s_axis_avgo_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGO TREADY" *) output wire s_axis_avgo_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_AVGO TLAST" *) input wire s_axis_avgo_tlast,
/* DataMover MM2S (read from memory) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TDATA" *) input wire [31:0] s_axis_mm2s_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TKEEP" *) input wire [3:0] s_axis_mm2s_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TVALID" *) input wire s_axis_mm2s_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TREADY" *) output wire s_axis_mm2s_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TLAST" *) input wire s_axis_mm2s_tlast,
/* DataMover S2MM (write to memory) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_S2MM, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TDATA" *) output reg [31:0] m_axis_s2mm_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TKEEP" *) output wire [3:0] m_axis_s2mm_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TVALID" *) output reg m_axis_s2mm_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TREADY" *) input wire m_axis_s2mm_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM TLAST" *) output reg m_axis_s2mm_tlast,
/* DataMover MM2S command interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_MM2S_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TDATA" *) output reg [71:0] m_axis_mm2s_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TVALID" *) output reg m_axis_mm2s_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TREADY" *) input wire m_axis_mm2s_cmd_tready,
/* DataMover MM2S status interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TDATA" *) input wire [7:0] s_axis_mm2s_sts_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TKEEP" *) input wire [0:0] s_axis_mm2s_sts_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TVALID" *) input wire s_axis_mm2s_sts_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TREADY" *) output reg s_axis_mm2s_sts_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TLAST" *) input wire s_axis_mm2s_sts_tlast,
/* DataMover S2MM command interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_S2MM_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TDATA" *) output reg [71:0] m_axis_s2mm_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TVALID" *) output reg m_axis_s2mm_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_S2MM_CMD TREADY" *) input wire m_axis_s2mm_cmd_tready,
/* DataMover S2MM status interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_S2MM_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TDATA" *) input wire [7:0] s_axis_s2mm_sts_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TKEEP" *) input wire [0:0] s_axis_s2mm_sts_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TVALID" *) input wire s_axis_s2mm_sts_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TREADY" *) output reg s_axis_s2mm_sts_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_S2MM_STS TLAST" *) input wire s_axis_s2mm_sts_tlast
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
wire [31:0] stat_reg;
reg [31:0] raw_buf_addr = {32{1'b0}};
reg [31:0] avg_buf_addr = {32{1'b0}};
reg [31:0] gain_buf_addr = {32{1'b0}};
reg [31:0] ofst_buf_addr = {32{1'b0}};
reg [31:0] equal_buf_addr = {32{1'b0}};
reg [31:0] equal_x2_buf_addr = {32{1'b0}};
reg [31:0] raw_btt = {32{1'b0}};
reg [31:0] avg_btt = {32{1'b0}};
reg [31:0] gain_btt = {32{1'b0}};
reg [31:0] ofst_btt = {32{1'b0}};
reg [31:0] equal_btt = {32{1'b0}};
reg [31:0] equal_x2_btt = {32{1'b0}};
always @(posedge axi_aclk) begin
if (~axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[7:2])
6'd0 : ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
/* 6'd1 : read only register */
6'd2 : raw_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : raw_buf_addr [i*8 +: 8];
6'd3 : avg_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : avg_buf_addr [i*8 +: 8];
6'd4 : gain_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : gain_buf_addr [i*8 +: 8];
6'd5 : ofst_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ofst_buf_addr [i*8 +: 8];
6'd6 : equal_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : equal_buf_addr [i*8 +: 8];
6'd7 : equal_x2_buf_addr [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : equal_x2_buf_addr [i*8 +: 8];
6'd8 : raw_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : raw_btt [i*8 +: 8];
6'd9 : avg_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : avg_btt [i*8 +: 8];
6'd10 : gain_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : gain_btt [i*8 +: 8];
6'd11 : ofst_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ofst_btt [i*8 +: 8];
6'd12 : equal_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : equal_btt [i*8 +: 8];
6'd13 : equal_x2_btt [i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : equal_x2_btt [i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[7:2])
6'd0 : s_axi_rdata <= ctrl_reg;
6'd1 : s_axi_rdata <= stat_reg;
6'd2 : s_axi_rdata <= raw_buf_addr;
6'd3 : s_axi_rdata <= avg_buf_addr;
6'd4 : s_axi_rdata <= gain_buf_addr;
6'd5 : s_axi_rdata <= ofst_buf_addr;
6'd6 : s_axi_rdata <= equal_buf_addr;
6'd7 : s_axi_rdata <= equal_x2_buf_addr;
6'd8 : s_axi_rdata <= raw_btt;
6'd9 : s_axi_rdata <= avg_btt;
6'd10 : s_axi_rdata <= gain_btt;
6'd11 : s_axi_rdata <= ofst_btt;
6'd12 : s_axi_rdata <= equal_btt;
6'd13 : s_axi_rdata <= equal_x2_btt;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [3:0] DMA_XFER_OKAY = 4'b1000,
DMA_XFER_SLVERR = 4'b0100,
DMA_XFER_DECERR = 4'b0010,
DMA_XFER_INTERR = 4'b0001;
localparam [1:0] RAW_FIFO_ID = 2'd0,
AVGO_FIFO_ID = 2'd1,
EQUAL_FIFO_ID = 2'd2,
EQUAL_X2_FIFO_ID = 2'd3;
localparam [1:0] GAIN_FIFO_ID = 2'd0,
OFST_FIFO_ID = 2'd1,
AVGI_FIFO_ID = 2'd2;
reg raw_fifo_load_ena = 1'b0;
reg raw_fifo_load_done = 1'b1;
reg raw_fifo_load_req = 1'b0;
reg equal_fifo_load_ena = 1'b0;
reg equal_x2_fifo_load_ena = 1'b0;
// S2MM
reg s2mm_xfer_ena = 1'b0;
reg [1:0] master_select = 2'b00;
assign m_axis_s2mm_tkeep = {4{1'b1}};
always @(*) begin
(* parallel_case *)
case (master_select)
RAW_FIFO_ID: begin
m_axis_s2mm_tdata = s_axis_raw_tdata;
m_axis_s2mm_tlast = s_axis_raw_tlast;
m_axis_s2mm_tvalid = s_axis_raw_tvalid & s2mm_xfer_ena;
end
AVGO_FIFO_ID: begin
m_axis_s2mm_tdata = s_axis_avgo_tdata;
m_axis_s2mm_tlast = s_axis_avgo_tlast;
m_axis_s2mm_tvalid = s_axis_avgo_tvalid & s2mm_xfer_ena;
end
EQUAL_FIFO_ID: begin
m_axis_s2mm_tdata = s_axis_equal_tdata;
m_axis_s2mm_tlast = s_axis_equal_tlast;
m_axis_s2mm_tvalid = s_axis_equal_tvalid & s2mm_xfer_ena;
end
EQUAL_X2_FIFO_ID: begin
m_axis_s2mm_tdata = s_axis_equal_x2_tdata;
m_axis_s2mm_tlast = s_axis_equal_x2_tlast;
m_axis_s2mm_tvalid = s_axis_equal_x2_tvalid & s2mm_xfer_ena;
end
//default: begin
// m_axis_s2mm_tdata = {32{1'b0}};
// m_axis_s2mm_tlast = 1'b1;
// m_axis_s2mm_tvalid = 1'b0;
//end
endcase
end
assign s_axis_raw_tready = (s2mm_xfer_ena & m_axis_s2mm_tready & (master_select == RAW_FIFO_ID)) | (~raw_fifo_load_ena);
assign s_axis_avgo_tready = s2mm_xfer_ena & m_axis_s2mm_tready & (master_select == AVGO_FIFO_ID);
assign s_axis_equal_tready = (s2mm_xfer_ena & m_axis_s2mm_tready & (master_select == EQUAL_FIFO_ID)) | (~equal_fifo_load_ena);
assign s_axis_equal_x2_tready = (s2mm_xfer_ena & m_axis_s2mm_tready & (master_select == EQUAL_X2_FIFO_ID)) | (~equal_x2_fifo_load_ena);
// MM2S
reg mm2s_xfer_ena = 1'b0;
reg [1:0] slave_select = 2'b00;
assign m_axis_gain_tdata = s_axis_mm2s_tdata;
assign m_axis_gain_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == GAIN_FIFO_ID);
assign m_axis_gain_tlast = s_axis_mm2s_tlast;
assign m_axis_ofst_tdata = s_axis_mm2s_tdata;
assign m_axis_ofst_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == OFST_FIFO_ID);
assign m_axis_ofst_tlast = s_axis_mm2s_tlast;
assign m_axis_avgi_tdata = s_axis_mm2s_tdata;
assign m_axis_avgi_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == AVGI_FIFO_ID);
assign m_axis_avgi_tlast = s_axis_mm2s_tlast;
reg slave_axis_tready;
always @(*) begin
(* parallel_case *)
case (slave_select)
GAIN_FIFO_ID: slave_axis_tready = m_axis_gain_tready;
OFST_FIFO_ID: slave_axis_tready = m_axis_ofst_tready;
AVGI_FIFO_ID: slave_axis_tready = m_axis_avgi_tready;
default: slave_axis_tready = 1'b0;
endcase
end
assign s_axis_mm2s_tready = slave_axis_tready & mm2s_xfer_ena;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST1_RST = 2'd0,
ST1_ILDE = 2'd1,
ST1_WAIT_SOF = 2'd2,
ST1_WAIT_EOF = 2'd3;
reg [1:0] state1 = ST1_RST;
always @(posedge axi_aclk) begin
if (~axi_aresetn | ~ctrl_reg[31]) begin
raw_fifo_load_ena <= 1'b0;
raw_fifo_load_done <= 1'b1;
raw_fifo_load_req <= 1'b0;
state1 <= ST1_RST;
end else begin
raw_fifo_load_req <= ctrl_reg[0];
case (state1)
ST1_RST: begin
raw_fifo_load_ena <= 1'b0;
raw_fifo_load_done <= 1'b1;
state1 <= ST1_ILDE;
end
ST1_ILDE: begin
if (raw_fifo_load_req) begin
raw_fifo_load_done <= 1'b0;
state1 <= (ctrl_reg[0])? state1 : ST1_WAIT_SOF;
end
end
ST1_WAIT_SOF: begin
if (s_axis_raw_tvalid & s_axis_raw_tready & s_axis_raw_tuser) begin
raw_fifo_load_ena <= 1'b1;
state1 <= ST1_WAIT_EOF;
end
end
ST1_WAIT_EOF: begin
if (s_axis_raw_tvalid & s_axis_raw_tready & s_axis_raw_tuser) begin // s_axis_raw_tuser - indicates last pixels of the frame
raw_fifo_load_ena <= 1'b0;
raw_fifo_load_done <= 1'b1;
state1 <= ST1_ILDE;
end
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
always @(posedge axi_aclk) begin
if (~axi_aresetn | ~ctrl_reg[31]) begin
equal_fifo_load_ena <= 1'b0;
equal_x2_fifo_load_ena <= 1'b0;
end else begin
/* Equalized buffer refresh flag */
if (s_axis_equal_tvalid & s_axis_equal_tready & s_axis_equal_tuser) begin // tuser - indicates last pixels of the frame
equal_fifo_load_ena <= ctrl_reg[1];
end
if (s_axis_equal_x2_tvalid & s_axis_equal_x2_tready & s_axis_equal_x2_tuser) begin // tuser - indicates last pixels of the frame
equal_x2_fifo_load_ena <= ctrl_reg[1];
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Main data streaming module. Current FSM manages
* data movement by AXI-DataMover IP-core */
localparam [4:0] ST_ERROR = 5'd0,
ST_RESET = 5'd1,
ST_SWITCH_CNSMR = 5'd2,
ST_DATMOV_S2MM_CMD_0 = 5'd3,
ST_DATMOV_S2MM_CMD_1 = 5'd4,
ST_DATMOV_S2MM_XFER = 5'd5,
ST_GET_S2MM_XFER_STAT = 5'd6,
ST_DATMOV_MM2S_CMD_0 = 5'd7,
ST_DATMOV_MM2S_CMD_1 = 5'd8,
ST_DATMOV_MM2S_XFER = 5'd9,
ST_GET_MM2S_XFER_STAT = 5'd10,
ST_SEND_AVGI_ROW = 5'd11,
ST_SEND_GAIN_ROW = 5'd12,
ST_SEND_OFST_ROW = 5'd13,
ST_GET_RAW_ROW = 5'd14,
ST_GET_AVGO_ROW = 5'd15,
ST_GET_EQUAL_ROW = 5'd16,
ST_GET_EQUAL_X2_ROW = 5'd17;
reg [4:0] state = ST_RESET;
reg [4:0] state_next = ST_RESET;
reg eol_flag = 1'b0;
reg [31:0] raw_frame_ptr = {32{1'b0}};
reg [31:0] avgo_frame_ptr = {32{1'b0}};
reg [31:0] gain_frame_ptr = {32{1'b0}};
reg [31:0] ofst_frame_ptr = {32{1'b0}};
reg [31:0] avgi_frame_ptr = {32{1'b0}};
reg [31:0] equal_frame_ptr = {32{1'b0}};
reg [31:0] equal_x2_frame_ptr = {32{1'b0}};
reg [31:0] byte_offset;
reg [22:0] btt_cnt;
wire [71:0] datmov_cmd = {
4'b0000, // RSVD
4'b0000, // TAG (Command TAG)
byte_offset, // Memory address byte offset
1'b0, // DRR (DRE ReAlignment Request)
1'b1, // EOF (End of Frame)
6'b000000, // DSA (DRE Stream Alignment)
1'b1, // Access type (0 - fix, 1 - inc)
btt_cnt // Bytes to transfer count
};
always @(posedge axi_aclk) begin
if (~axi_aresetn | ~ctrl_reg[31]) begin
mm2s_xfer_ena <= 1'b0;
s2mm_xfer_ena <= 1'b0;
state <= ST_RESET;
end else begin
/* Reset frame pointers at the SOF */
if (sof_strb) begin
raw_frame_ptr <= raw_buf_addr;
avgo_frame_ptr <= avg_buf_addr;
gain_frame_ptr <= gain_buf_addr;
ofst_frame_ptr <= ofst_buf_addr;
avgi_frame_ptr <= avg_buf_addr;
equal_frame_ptr <= equal_buf_addr;
equal_x2_frame_ptr <= equal_x2_buf_addr;
eol_flag <= 1'b1; // to fill all FIFOs at SOF
end
/* Registering EOL flag */
if (eol_strb) begin
eol_flag <= 1'b1;
end
/* Data management FSM */
case (state)
/* Unrecoverable error */
ST_ERROR: begin
state <= state;
end
ST_RESET: begin
mm2s_xfer_ena <= 1'b0;
s2mm_xfer_ena <= 1'b0;
if (sof_strb) begin
state <= ST_SWITCH_CNSMR;
end
end
ST_SWITCH_CNSMR: begin
if (eol_flag) begin
/* Here we fill FIFOs that must be mandatory filled
* after each EOL request with highest priority */
eol_flag <= 1'b0;
state <= ST_SEND_AVGI_ROW;
end else begin
state <= ST_GET_EQUAL_ROW;
end
end
ST_SEND_AVGI_ROW: begin
if (~fifo_avgi_prog_full) begin
slave_select <= AVGI_FIFO_ID;
byte_offset <= avgi_frame_ptr;
avgi_frame_ptr <= avgi_frame_ptr + avg_btt;
btt_cnt <= avg_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_GET_RAW_ROW;
end else begin
state <= ST_GET_RAW_ROW;
end
end
ST_GET_RAW_ROW: begin
if (~fifo_raw_prog_empty & raw_fifo_load_ena) begin
master_select <= RAW_FIFO_ID;
byte_offset <= raw_frame_ptr;
raw_frame_ptr <= raw_frame_ptr + raw_btt;
btt_cnt <= raw_btt;
state <= ST_DATMOV_S2MM_CMD_0;
state_next <= ST_SEND_GAIN_ROW;
end else begin
state <= ST_SEND_GAIN_ROW;
end
end
ST_SEND_GAIN_ROW: begin
if (~fifo_gain_prog_full) begin
slave_select <= GAIN_FIFO_ID;
byte_offset <= gain_frame_ptr;
gain_frame_ptr <= gain_frame_ptr + gain_btt;
btt_cnt <= gain_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_SEND_OFST_ROW;
end else begin
state <= ST_SEND_OFST_ROW;
end
end
ST_SEND_OFST_ROW: begin
if (~fifo_ofst_prog_full) begin
slave_select <= OFST_FIFO_ID;
byte_offset <= ofst_frame_ptr;
ofst_frame_ptr <= ofst_frame_ptr + ofst_btt;
btt_cnt <= ofst_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_GET_AVGO_ROW;
end else begin
state <= ST_GET_AVGO_ROW;
end
end
ST_GET_AVGO_ROW: begin
if (~fifo_avgo_prog_empty) begin
master_select <= AVGO_FIFO_ID;
byte_offset <= avgo_frame_ptr;
avgo_frame_ptr <= avgo_frame_ptr + avg_btt;
btt_cnt <= avg_btt;
state <= ST_DATMOV_S2MM_CMD_0;
state_next <= ST_SWITCH_CNSMR;
end else begin
state <= ST_SWITCH_CNSMR;
end
end
ST_GET_EQUAL_ROW: begin
if (~fifo_equal_prog_empty & equal_fifo_load_ena) begin
master_select <= EQUAL_FIFO_ID;
byte_offset <= equal_frame_ptr;
equal_frame_ptr <= equal_frame_ptr + equal_btt;
btt_cnt <= equal_btt;
state <= ST_DATMOV_S2MM_CMD_0;
state_next <= ST_GET_EQUAL_X2_ROW;
end else begin
state <= ST_GET_EQUAL_X2_ROW;
end
end
ST_GET_EQUAL_X2_ROW: begin
if (~fifo_equal_x2_prog_empty & equal_x2_fifo_load_ena) begin
master_select <= EQUAL_X2_FIFO_ID;
byte_offset <= equal_x2_frame_ptr;
equal_x2_frame_ptr <= equal_x2_frame_ptr + equal_x2_btt;
btt_cnt <= equal_x2_btt;
state <= ST_DATMOV_S2MM_CMD_0;
state_next <= ST_SWITCH_CNSMR;
end else begin
state <= ST_SWITCH_CNSMR;
end
end
/* Generate S2MM command for DataMover */
ST_DATMOV_S2MM_CMD_0: begin
m_axis_s2mm_cmd_tdata <= datmov_cmd;
m_axis_s2mm_cmd_tvalid <= 1'b1;
state <= ST_DATMOV_S2MM_CMD_1;
end
/* Wait S2MM command to be accepted */
ST_DATMOV_S2MM_CMD_1: begin
if (m_axis_s2mm_cmd_tready) begin
m_axis_s2mm_cmd_tvalid <= 1'b0;
s2mm_xfer_ena <= 1'b1;
state <= ST_DATMOV_S2MM_XFER;
end
end
/* Wait S2MM transfer to be done */
ST_DATMOV_S2MM_XFER: begin
if (m_axis_s2mm_tvalid & m_axis_s2mm_tready & m_axis_s2mm_tlast) begin
s2mm_xfer_ena <= 1'b0;
s_axis_s2mm_sts_tready <= 1'b1;
state <= ST_GET_S2MM_XFER_STAT;
end
end
/* Check S2MM transfer status */
ST_GET_S2MM_XFER_STAT: begin
if (s_axis_s2mm_sts_tvalid) begin
s_axis_s2mm_sts_tready <= 1'b0;
if (s_axis_s2mm_sts_tdata[7:4] == DMA_XFER_OKAY) begin
state <= state_next;
end else begin
state <= ST_ERROR;
end
end
end
/* Generate MM2S command for DataMover */
ST_DATMOV_MM2S_CMD_0: begin
m_axis_mm2s_cmd_tdata <= datmov_cmd;
m_axis_mm2s_cmd_tvalid <= 1'b1;
state <= ST_DATMOV_MM2S_CMD_1;
end
/* Wait MM2S command to be accepted */
ST_DATMOV_MM2S_CMD_1: begin
if (m_axis_mm2s_cmd_tready) begin
m_axis_mm2s_cmd_tvalid <= 1'b0;
mm2s_xfer_ena <= 1'b1;
state <= ST_DATMOV_MM2S_XFER;
end
end
/* Wait MM2S transfer to be done */
ST_DATMOV_MM2S_XFER: begin
if (s_axis_mm2s_tvalid & s_axis_mm2s_tready & s_axis_mm2s_tlast) begin
mm2s_xfer_ena <= 1'b0;
s_axis_mm2s_sts_tready <= 1'b1;
state <= ST_GET_MM2S_XFER_STAT;
end
end
/* Check MM2S transfer status */
ST_GET_MM2S_XFER_STAT: begin
if (s_axis_mm2s_sts_tvalid) begin
s_axis_mm2s_sts_tready <= 1'b0;
if (s_axis_mm2s_sts_tdata[7:4] == DMA_XFER_OKAY) begin
state <= state_next;
end else begin
state <= ST_ERROR;
end
end
end
default: begin
state <= ST_ERROR;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign avg_level = ctrl_reg[10:8];
assign nuc_bypass = ctrl_reg[11];
assign bpr_bypass = ctrl_reg[12];
assign stat_reg = {
3'b000, state,
16'h0000,
6'b000000,
equal_fifo_load_ena & equal_x2_fifo_load_ena,
raw_fifo_load_done
};
endmodule |
module axis_palette_lut
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire axis_aclk,
input wire toggle_palette,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [31:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire [3:0] s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output wire [31:0] m_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output wire m_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input wire m_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output wire m_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME LUT_RAM, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM CLK" *) input wire lut_ram_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM EN " *) input wire lut_ram_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM RST" *) input wire lut_ram_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM WE" *) input wire [3:0] lut_ram_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM ADDR" *) input wire [31:0] lut_ram_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM DIN" *) input wire [31:0] lut_ram_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM DOUT" *) output wire [31:0] lut_ram_rdata
);
localparam integer PIPE_DATA_IN_WIDTH = 8;
localparam integer PIPE_DATA_OUT_WIDTH = 32;
localparam integer PIPE_QUAL_WIDTH = 1;
localparam integer PIPE_STAGES = 2;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire m_axis_wcd_tvalid;
wire m_axis_wcd_tready;
wire [7:0] m_axis_wcd_tdata;
wire m_axis_wcd_tuser;
AXIS_WC_4_TO_1 AXIS_WC_4_TO_1_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tdata ( s_axis_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tvalid ( s_axis_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( s_axis_tready ), // output wire s_axis_tready
.s_axis_tlast ( 1'b0 ), // input wire s_axis_tlast
.s_axis_tuser ( s_axis_tuser ), // input wire [3 : 0] s_axis_tuser
.m_axis_tdata ( m_axis_wcd_tdata ), // output wire [7 : 0] m_axis_tdata
.m_axis_tvalid ( m_axis_wcd_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcd_tready ), // input wire m_axis_tready
.m_axis_tlast ( /*-----NC-----*/ ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcd_tuser ) // output wire [0 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg palette_sub_addr = 1'b0;
reg toggle_palette_1 = 1'b0;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
palette_sub_addr <= 1'b0;
toggle_palette_1 <= 1'b0;
end else begin
toggle_palette_1 <= toggle_palette;
if (m_axis_wcd_tvalid & m_axis_wcd_tready & m_axis_wcd_tuser) begin
if (toggle_palette) begin
palette_sub_addr <= (toggle_palette_1)? ~palette_sub_addr : 1'b0;
end else begin
palette_sub_addr <= 1'b0;
end
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( m_axis_wcd_tdata ),
.s_axis_tuser ( m_axis_wcd_tuser ),
.s_axis_tvalid ( m_axis_wcd_tvalid ),
.s_axis_tready ( m_axis_wcd_tready ),
.s_axis_tlast ( 1'b0 ),
.m_axis_tdata ( m_axis_tdata ),
.m_axis_tuser ( m_axis_tuser ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( /*-----NC-----*/ ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire ram_clkb;
wire ram_enb;
wire [3:0] ram_web;
wire [9:0] ram_addrb;
wire [31:0] ram_dinb;
wire [31:0] ram_doutb;
PALETTE_LUT_RAM PALETTE_LUT_RAM_inst
(
.clka ( lut_ram_clk ), // input wire clka
.ena ( lut_ram_ena ), // input wire ena
.wea ( lut_ram_we ), // input wire [3 : 0] wea
.addra ( lut_ram_addr[11:2] ), // input wire [9 : 0] addra
.dina ( lut_ram_wdata ), // input wire [31 : 0] dina
.douta ( lut_ram_rdata ), // output wire [31 : 0] douta
.clkb ( ram_clkb ), // input wire clkb
.enb ( ram_enb ), // input wire enb
.web ( ram_web ), // input wire [3 : 0] web
.addrb ( ram_addrb ), // input wire [9 : 0] addrb
.dinb ( ram_dinb ), // input wire [31 : 0] dinb
.doutb ( ram_doutb ) // output wire [31 : 0] doutb
);
assign ram_clkb = axis_aclk;
assign ram_enb = pipe_cen;
assign ram_web = 4'b0000;
assign ram_addrb = {1'b0, palette_sub_addr, pipe_in_data};
assign ram_dinb = {32{1'b0}};
assign pipe_out_data = ram_doutb;
endmodule |
module bram_port_demux
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_IN, MEM_SIZE 32768, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN CLK" *) input wire bram_in_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN EN " *) input wire bram_in_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN RST" *) input wire bram_in_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN WE" *) input wire [3:0] bram_in_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN ADDR" *) input wire [31:0] bram_in_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN DIN" *) input wire [31:0] bram_in_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_IN DOUT" *) output reg [31:0] bram_in_rdata,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_OUT_0, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 CLK" *) output wire bram_out_0_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 EN " *) output reg bram_out_0_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 RST" *) output wire bram_out_0_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 WE" *) output wire [3:0] bram_out_0_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 ADDR" *) output wire [31:0] bram_out_0_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 DIN" *) output wire [31:0] bram_out_0_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_0 DOUT" *) input wire [31:0] bram_out_0_rdata,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_OUT_1, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 CLK" *) output wire bram_out_1_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 EN " *) output reg bram_out_1_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 RST" *) output wire bram_out_1_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 WE" *) output wire [3:0] bram_out_1_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 ADDR" *) output wire [31:0] bram_out_1_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 DIN" *) output wire [31:0] bram_out_1_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_1 DOUT" *) input wire [31:0] bram_out_1_rdata,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_OUT_2, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 CLK" *) output wire bram_out_2_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 EN " *) output reg bram_out_2_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 RST" *) output wire bram_out_2_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 WE" *) output wire [3:0] bram_out_2_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 ADDR" *) output wire [31:0] bram_out_2_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 DIN" *) output wire [31:0] bram_out_2_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_2 DOUT" *) input wire [31:0] bram_out_2_rdata,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_OUT_3, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 CLK" *) output wire bram_out_3_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 EN " *) output reg bram_out_3_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 RST" *) output wire bram_out_3_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 WE" *) output wire [3:0] bram_out_3_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 ADDR" *) output wire [31:0] bram_out_3_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 DIN" *) output wire [31:0] bram_out_3_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_3 DOUT" *) input wire [31:0] bram_out_3_rdata,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT_OUT_4, MEM_SIZE 4096, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 CLK" *) output wire bram_out_4_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 EN " *) output reg bram_out_4_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 RST" *) output wire bram_out_4_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 WE" *) output wire [3:0] bram_out_4_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 ADDR" *) output wire [31:0] bram_out_4_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 DIN" *) output wire [31:0] bram_out_4_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT_OUT_4 DOUT" *) input wire [31:0] bram_out_4_rdata
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign bram_out_0_clk = bram_in_clk;
assign bram_out_0_rst = bram_in_rst;
assign bram_out_0_we = bram_in_we;
assign bram_out_0_addr = bram_in_addr;
assign bram_out_0_wdata = bram_in_wdata;
assign bram_out_1_clk = bram_in_clk;
assign bram_out_1_rst = bram_in_rst;
assign bram_out_1_we = bram_in_we;
assign bram_out_1_addr = bram_in_addr;
assign bram_out_1_wdata = bram_in_wdata;
assign bram_out_2_clk = bram_in_clk;
assign bram_out_2_rst = bram_in_rst;
assign bram_out_2_we = bram_in_we;
assign bram_out_2_addr = bram_in_addr;
assign bram_out_2_wdata = bram_in_wdata;
assign bram_out_3_clk = bram_in_clk;
assign bram_out_3_rst = bram_in_rst;
assign bram_out_3_we = bram_in_we;
assign bram_out_3_addr = bram_in_addr;
assign bram_out_3_wdata = bram_in_wdata;
assign bram_out_4_clk = bram_in_clk;
assign bram_out_4_rst = bram_in_rst;
assign bram_out_4_we = bram_in_we;
assign bram_out_4_addr = bram_in_addr;
assign bram_out_4_wdata = bram_in_wdata;
always @(*) begin
case (bram_in_addr[14:12])
3'd0: begin
bram_in_rdata = bram_out_0_rdata;
bram_out_0_ena = bram_in_ena;
bram_out_1_ena = 1'b0;
bram_out_2_ena = 1'b0;
bram_out_3_ena = 1'b0;
bram_out_4_ena = 1'b0;
end
3'd1: begin
bram_in_rdata = bram_out_1_rdata;
bram_out_0_ena = 1'b0;
bram_out_1_ena = bram_in_ena;
bram_out_2_ena = 1'b0;
bram_out_3_ena = 1'b0;
bram_out_4_ena = 1'b0;
end
3'd2: begin
bram_in_rdata = bram_out_2_rdata;
bram_out_0_ena = 1'b0;
bram_out_1_ena = 1'b0;
bram_out_2_ena = bram_in_ena;
bram_out_3_ena = 1'b0;
bram_out_4_ena = 1'b0;
end
3'd3: begin
bram_in_rdata = bram_out_3_rdata;
bram_out_0_ena = 1'b0;
bram_out_1_ena = 1'b0;
bram_out_2_ena = 1'b0;
bram_out_3_ena = bram_in_ena;
bram_out_4_ena = 1'b0;
end
3'd4: begin
bram_in_rdata = bram_out_4_rdata;
bram_out_0_ena = 1'b0;
bram_out_1_ena = 1'b0;
bram_out_2_ena = 1'b0;
bram_out_3_ena = 1'b0;
bram_out_4_ena = bram_in_ena;
end
default: begin
bram_in_rdata = 32'hABADC0DE;
bram_out_0_ena = 1'b0;
bram_out_1_ena = 1'b0;
bram_out_2_ena = 1'b0;
bram_out_3_ena = 1'b0;
bram_out_4_ena = 1'b0;
end
endcase
end
endmodule |
module yuv444_to_yuv422
(
input wire clk,
input wire cen,
input wire [7:0] y0_in,
input wire [7:0] u0_in,
input wire [7:0] v0_in,
input wire [7:0] y1_in,
input wire [7:0] u1_in,
input wire [7:0] v1_in,
output reg [7:0] y0_out = {8{1'b0}},
output wire [7:0] u_out,
output reg [7:0] y1_out = {8{1'b0}},
output wire [7:0] v_out
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [8:0] u_sum = {9{1'b0}};
reg [8:0] v_sum = {9{1'b0}};
always @(posedge clk) begin
if (cen) begin
y0_out <= y0_in;
y1_out <= y1_in;
u_sum <= u0_in + u1_in + 1'b1;
v_sum <= v0_in + v1_in + 1'b1;
end
end
assign u_out = u_sum[8:1];
assign v_out = v_sum[8:1];
endmodule |
module axis_yuv444_to_yuv422 #
(
parameter BYTE_ORDER = "NOT_SELECTED"
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [31:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output wire [7:0] m_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output wire m_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input wire m_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output wire m_axis_tuser
);
localparam PIPE_DATA_IN_WIDTH = 48;
localparam PIPE_DATA_OUT_WIDTH = 32;
localparam PIPE_QUAL_WIDTH = 2;
localparam PIPE_STAGES = 1;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [63:0] axis_wcu_m_tdata;
wire axis_wcu_m_tvalid;
wire axis_wcu_m_tready;
wire [7:0] axis_wcu_m_tuser;
AXIS_WC_4_TO_8 AXIS_WC_4_TO_8_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tvalid ( s_axis_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( s_axis_tready ), // output wire s_axis_tready
.s_axis_tdata ( s_axis_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tlast ( 1'b0 ), // input wire s_axis_tlast
.s_axis_tuser ( {s_axis_tuser, 3'b000}), // input wire [3 : 0] s_axis_tuser
.m_axis_tvalid ( axis_wcu_m_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( axis_wcu_m_tready ), // input wire m_axis_tready
.m_axis_tdata ( axis_wcu_m_tdata ), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep ( /*--------NC-------*/ ), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast ( /*--------NC-------*/ ), // output wire m_axis_tlast
.m_axis_tuser ( axis_wcu_m_tuser ) // output wire [7 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
wire [31:0] axis_yuv422_m_tdata;
wire axis_yuv422_m_tvalid;
wire axis_yuv422_m_tready;
wire [1:0] axis_yuv422_m_tuser;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ({axis_wcu_m_tdata[55:32],
axis_wcu_m_tdata[23:0]}),
.s_axis_tuser ({axis_wcu_m_tuser[7],
axis_wcu_m_tuser[3]}),
.s_axis_tvalid ( axis_wcu_m_tvalid ),
.s_axis_tready ( axis_wcu_m_tready ),
.s_axis_tlast ( 1'b0 ),
.m_axis_tdata ( axis_yuv422_m_tdata ),
.m_axis_tuser ( axis_yuv422_m_tuser ),
.m_axis_tvalid ( axis_yuv422_m_tvalid ),
.m_axis_tready ( axis_yuv422_m_tready ),
.m_axis_tlast ( /*-------NC-------*/ ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
wire [7:0] Y0_in = pipe_in_data[23:16];
wire [7:0] U0_in = pipe_in_data[15:8];
wire [7:0] V0_in = pipe_in_data[7:0];
wire [7:0] Y1_in = pipe_in_data[47:40];
wire [7:0] U1_in = pipe_in_data[39:32];
wire [7:0] V1_in = pipe_in_data[31:24];
wire [7:0] Y0_out;
wire [7:0] U_out;
wire [7:0] Y1_out;
wire [7:0] V_out;
yuv444_to_yuv422 yuv444_to_yuv422_inst
(
.clk ( axis_aclk ),
.cen ( pipe_cen ),
.y0_in ( Y0_in ),
.u0_in ( U0_in ),
.v0_in ( V0_in ),
.y1_in ( Y1_in ),
.u1_in ( U1_in ),
.v1_in ( V1_in ),
.y0_out ( Y0_out ),
.u_out ( U_out ),
.y1_out ( Y1_out ),
.v_out ( V_out )
);
/* Configure output 422 pixel component byte order */
generate
if (BYTE_ORDER == "VYUY") begin /* USB UVC byte order */
assign pipe_out_data = {V_out, Y1_out, U_out, Y0_out};
end else begin
if (BYTE_ORDER == "YVYU") begin /* AV byte order */
assign pipe_out_data = {Y1_out, V_out, Y0_out, U_out};
end else begin
//INVALID_PARAMETER invalid_parameter_msg();
initial begin
$error("Invalid parameter!");
end
end
end
endgenerate
/*-------------------------------------------------------------------------------------------------------------------------------------*/
AXIS_WC_4_TO_1 AXIS_WC_4_TO_1_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tdata ( axis_yuv422_m_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tvalid ( axis_yuv422_m_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( axis_yuv422_m_tready ), // output wire s_axis_tready
.s_axis_tlast ( 1'b0 ), // input wire s_axis_tlast
.s_axis_tuser ( {axis_yuv422_m_tuser[1], 1'b0,
axis_yuv422_m_tuser[0], 1'b0} ), // input wire [3 : 0] s_axis_tuser
.m_axis_tdata ( m_axis_tdata ), // output wire [7 : 0] m_axis_tdata
.m_axis_tvalid ( m_axis_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_tready ), // input wire m_axis_tready
.m_axis_tlast ( /*----NC---*/ ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_tuser ) // output wire [0 : 0] m_axis_tuser
);
endmodule |
module dvi_generator
(
input wire i_pix_clk, // pixel clock
input wire i_pix_clk_5x, // 5 x pixel clock for DDR serialization
input wire i_rst, // reset (active high)
input wire i_de, // display enable (draw video)
input wire [7:0] i_data_ch0, // channel 0 - 8-bit colour data
input wire [7:0] i_data_ch1, // channel 1 - 8-bit colour data
input wire [7:0] i_data_ch2, // channel 2 - 8-bit colour data
input wire [1:0] i_ctrl_ch0, // channel 0 - 2-bit control data
input wire [1:0] i_ctrl_ch1, // channel 1 - 2-bit control data
input wire [1:0] i_ctrl_ch2, // channel 2 - 2-bit control data
output wire o_tmds_ch0_serial, // channel 0 - serial TMDS
output wire o_tmds_ch1_serial, // channel 1 - serial TMDS
output wire o_tmds_ch2_serial, // channel 2 - serial TMDS
output wire o_tmds_chc_serial // channel clock - serial TMDS
);
wire [9:0] tmds_ch0, tmds_ch1, tmds_ch2;
tmds_encoder_dvi encode_ch0
(
.i_clk ( i_pix_clk ),
.i_rst ( i_rst ),
.i_data ( i_data_ch0 ),
.i_ctrl ( i_ctrl_ch0 ),
.i_de ( i_de ),
.o_tmds ( tmds_ch0 )
);
tmds_encoder_dvi encode_ch1
(
.i_clk ( i_pix_clk ),
.i_rst ( i_rst ),
.i_data ( i_data_ch1 ),
.i_ctrl ( i_ctrl_ch1 ),
.i_de ( i_de ),
.o_tmds ( tmds_ch1 )
);
tmds_encoder_dvi encode_ch2
(
.i_clk ( i_pix_clk ),
.i_rst ( i_rst ),
.i_data ( i_data_ch2 ),
.i_ctrl ( i_ctrl_ch2 ),
.i_de ( i_de ),
.o_tmds ( tmds_ch2 )
);
// common async reset for serdes
wire rst_oserdes;
sync_cdc_bit #
(
.C_SYNC_STAGES (3)
)
sync_cdc_bit_inst
(
.clk ( i_pix_clk ),
.d ( i_rst ),
.q ( rst_oserdes )
);
serializer_10to1 serialize_ch0
(
.i_clk ( i_pix_clk ),
.i_clk_hs ( i_pix_clk_5x ),
.i_rst_oserdes ( rst_oserdes ),
.i_data ( tmds_ch0 ),
.o_data ( o_tmds_ch0_serial )
);
serializer_10to1 serialize_ch1
(
.i_clk ( i_pix_clk ),
.i_clk_hs ( i_pix_clk_5x ),
.i_rst_oserdes ( rst_oserdes ),
.i_data ( tmds_ch1 ),
.o_data ( o_tmds_ch1_serial )
);
serializer_10to1 serialize_ch2
(
.i_clk ( i_pix_clk ),
.i_clk_hs ( i_pix_clk_5x ),
.i_rst_oserdes ( rst_oserdes ),
.i_data ( tmds_ch2 ),
.o_data ( o_tmds_ch2_serial )
);
serializer_10to1 serialize_chc
(
.i_clk ( i_pix_clk ),
.i_clk_hs ( i_pix_clk_5x ),
.i_rst_oserdes ( rst_oserdes ),
.i_data ( 10'b0000011111 ),
.o_data ( o_tmds_chc_serial )
);
endmodule |
module display_timings_variable
(
input wire [15:0] h_res,
input wire [15:0] v_res,
input wire [15:0] h_fp,
input wire [15:0] h_sync,
input wire [15:0] h_bp,
input wire [15:0] v_fp,
input wire [15:0] v_sync,
input wire [15:0] v_bp,
input wire h_pol,
input wire v_pol,
input wire i_pix_clk, // pixel clock
input wire i_rst, // reset: restarts frame (active high)
output wire o_hs, // horizontal sync
output wire o_vs, // vertical sync
output wire o_de, // display enable: high during active video
output wire o_frame, // high for one tick at the start of each frame
output reg signed [15:0] o_sx, // horizontal beam position (including blanking)
output reg signed [15:0] o_sy // vertical beam position (including blanking)
);
reg signed [15:0] h_sta;
reg signed [15:0] hs_sta;
reg signed [15:0] hs_end;
reg signed [15:0] ha_sta;
reg signed [15:0] ha_end;
reg h_pol_reg;
reg signed [15:0] v_sta;
reg signed [15:0] vs_sta;
reg signed [15:0] vs_end;
reg signed [15:0] va_sta;
reg signed [15:0] va_end;
reg v_pol_reg;
always @(posedge i_pix_clk) begin
// horizontal: sync, active, and pixels
h_sta <= 0 - h_fp - h_sync - h_bp; // horizontal start
hs_sta <= h_sta + h_fp; // sync start
hs_end <= hs_sta + h_sync; // sync end
ha_sta <= 0; // active start
ha_end <= h_res - 1; // active end
h_pol_reg <= h_pol; // horizontal sync polarity (0:neg, 1:pos)
// vertical: sync, active, and pixels
v_sta <= 0 - v_fp - v_sync - v_bp; // vertical start
vs_sta <= v_sta + v_fp; // sync start
vs_end <= vs_sta + v_sync; // sync end
va_sta <= 0; // active start
va_end <= v_res - 1; // active end
v_pol_reg <= v_pol; // vertical sync polarity (0:neg, 1:pos)
end
// generate sync signals with correct polarity
assign o_hs = h_pol_reg ? (o_sx > hs_sta && o_sx <= hs_end):
~(o_sx > hs_sta && o_sx <= hs_end);
assign o_vs = v_pol_reg ? (o_sy > vs_sta && o_sy <= vs_end):
~(o_sy > vs_sta && o_sy <= vs_end);
// display enable: high during active period
assign o_de = (o_sx >= 0 && o_sy >= 0);
// o_frame: high for one tick at the start of each frame
assign o_frame = (o_sy == v_sta && o_sx == h_sta);
always @(posedge i_pix_clk) begin
if (i_rst) begin // reset to start of frame
o_sx <= h_sta;
o_sy <= v_sta;
end else begin
if (o_sx == ha_end) begin // end of line
o_sx <= h_sta;
if (o_sy == va_end) begin // end of frame
o_sy <= v_sta;
end else begin
o_sy <= o_sy + 16'sh1;
end
end else begin
o_sx <= o_sx + 16'sh1;
end
end
end
endmodule |
module dvi_top #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire s_axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE, ASSOCIATED_RESET s_axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire s_axi_aclk,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire resetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS_CH0:S_AXIS_CH1, ASSOCIATED_RESET resetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire pix_clk,
input wire pix_clk_5x,
output wire pll_pwr_down,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_CH0, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH0 TDATA" *) input wire [31:0] s_axis_ch0_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH0 TVALID" *) input wire s_axis_ch0_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH0 TREADY" *) output reg s_axis_ch0_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH0 TUSER" *) input wire s_axis_ch0_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_CH1, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH1 TDATA" *) input wire [31:0] s_axis_ch1_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH1 TVALID" *) input wire s_axis_ch1_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH1 TREADY" *) output reg s_axis_ch1_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_CH1 TUSER" *) input wire s_axis_ch1_tuser,
output reg ch0_toggle_palette = 1'b0,
output reg ch1_toggle_palette = 1'b0,
output wire hdmi_tx_clk_n,
output wire hdmi_tx_clk_p,
output wire [2:0] hdmi_tx_n,
output wire [2:0] hdmi_tx_p
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
wire [31:0] stat_reg;
reg [31:0] ch0_win0_sp = {32{1'b1}}; // 16-bit X and Y values for start point coordinates
reg [31:0] ch0_win0_ep = {32{1'b1}}; // 16-bit X and Y values for end point coordinates
reg [31:0] ch0_win1_sp = {32{1'b1}}; // 16-bit X and Y values for start point coordinates
reg [31:0] ch0_win1_ep = {32{1'b1}}; // 16-bit X and Y values for end point coordinates
reg [31:0] ch1_win0_sp = {32{1'b1}}; // 16-bit X and Y values for start point coordinates
reg [31:0] ch1_win0_ep = {32{1'b1}}; // 16-bit X and Y values for end point coordinates
reg [31:0] ch1_win1_sp = {32{1'b1}}; // 16-bit X and Y values for start point coordinates
reg [31:0] ch1_win1_ep = {32{1'b1}}; // 16-bit X and Y values for end point coordinates
reg [31:0] back_gnd_rgb = 32'h00808080; // 24-bit background color RGB {8'hxx, Red, Green, Blue}
always @(posedge s_axi_aclk) begin
if (~s_axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[7:2])
6'd0 : ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
/* 6'd1 : read only register */
6'd2 : back_gnd_rgb[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : back_gnd_rgb[i*8 +: 8];
6'd3 : ch0_win0_sp[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_win0_sp[i*8 +: 8];
6'd4 : ch0_win0_ep[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_win0_ep[i*8 +: 8];
6'd5 : ch0_win1_sp[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_win1_sp[i*8 +: 8];
6'd6 : ch0_win1_ep[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_win1_ep[i*8 +: 8];
6'd7 : ch1_win0_sp[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_win0_sp[i*8 +: 8];
6'd8 : ch1_win0_ep[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_win0_ep[i*8 +: 8];
6'd9 : ch1_win1_sp[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_win1_sp[i*8 +: 8];
6'd10 : ch1_win1_ep[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_win1_ep[i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[7:2])
6'd0 : s_axi_rdata <= ctrl_reg;
6'd1 : s_axi_rdata <= stat_reg;
6'd2 : s_axi_rdata <= back_gnd_rgb;
6'd3 : s_axi_rdata <= ch0_win0_sp;
6'd4 : s_axi_rdata <= ch0_win0_ep;
6'd5 : s_axi_rdata <= ch0_win1_sp;
6'd6 : s_axi_rdata <= ch0_win1_ep;
6'd7 : s_axi_rdata <= ch1_win0_sp;
6'd8 : s_axi_rdata <= ch1_win0_ep;
6'd9 : s_axi_rdata <= ch1_win1_sp;
6'd10 : s_axi_rdata <= ch1_win1_ep;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
assign pll_pwr_down = ~ctrl_reg[31];
wire [1:0] resolution = ctrl_reg[1:0];
wire ch0_palette_toggle_ena = ctrl_reg[2];
wire ch1_palette_toggle_ena = ctrl_reg[3];
assign stat_reg = 32'hDEADFACE;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] RES_640X480 = 2'd0,
RES_800X600 = 2'd1,
RES_1280X720 = 2'd2,
RES_1920X1080 = 2'd3;
// Display Timings
wire signed [15:0] sx; // horizontal screen position (signed)
wire signed [15:0] sy; // vertical screen position (signed)
wire hs; // horizontal sync
wire vs; // vertical sync
wire de; // display enable
wire frame; // frame start
// Display parameters
reg [15:0] h_res;
reg [15:0] v_res;
reg [15:0] h_fp;
reg [15:0] h_sync;
reg [15:0] h_bp;
reg [15:0] v_fp;
reg [15:0] v_sync;
reg [15:0] v_bp;
reg h_pol;
reg v_pol;
always @(*) begin
case (resolution)
RES_640X480: begin
h_res = 16'd640;
v_res = 16'd480;
h_fp = 16'd16;
h_sync = 16'd96;
h_bp = 16'd48;
v_fp = 16'd10;
v_sync = 16'd2;
v_bp = 16'd33;
h_pol = 1'b1;
v_pol = 1'b1;
end
RES_800X600: begin
h_res = 16'd800;
v_res = 16'd600;
h_fp = 16'd40;
h_sync = 16'd128;
h_bp = 16'd88;
v_fp = 16'd1;
v_sync = 16'd4;
v_bp = 16'd23;
h_pol = 1'b1;
v_pol = 1'b1;
end
RES_1280X720: begin
h_res = 16'd1280;
v_res = 16'd720;
h_fp = 16'd110;
h_sync = 16'd40;
h_bp = 16'd220;
v_fp = 16'd5;
v_sync = 16'd5;
v_bp = 16'd20;
h_pol = 1'b1;
v_pol = 1'b1;
end
RES_1920X1080: begin
h_res = 16'd1920;
v_res = 16'd1080;
h_fp = 16'd88;
h_sync = 16'd44;
h_bp = 16'd148;
v_fp = 16'd4;
v_sync = 16'd5;
v_bp = 16'd36;
h_pol = 1'b1;
v_pol = 1'b1;
end
endcase
end
display_timings_variable display_timings_variable_inst
(
.h_res ( h_res ),
.v_res ( v_res ),
.h_fp ( h_fp ),
.h_sync ( h_sync ),
.h_bp ( h_bp ),
.v_fp ( v_fp ),
.v_sync ( v_sync ),
.v_bp ( v_bp ),
.h_pol ( h_pol ),
.v_pol ( v_pol ),
.i_pix_clk ( pix_clk ),
.i_rst ( ~resetn ),
.o_hs ( hs ),
.o_vs ( vs ),
.o_de ( de ),
.o_frame ( frame ),
.o_sx ( sx ),
.o_sy ( sy )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [7:0] red;
wire [7:0] green;
wire [7:0] blue;
reg ch0_frame_sync = 1'b0;
reg ch1_frame_sync = 1'b0;
reg ch0_exp_eof = 1'b0;
reg ch1_exp_eof = 1'b0;
reg ch0_exp_eof_1 = 1'b0;
reg ch1_exp_eof_1 = 1'b0;
reg ch0_win0_x_de = 1'b0;
reg ch0_win0_y_de = 1'b0;
reg ch0_win1_x_de = 1'b0;
reg ch0_win1_y_de = 1'b0;
reg ch1_win0_x_de = 1'b0;
reg ch1_win0_y_de = 1'b0;
reg ch1_win1_x_de = 1'b0;
reg ch1_win1_y_de = 1'b0;
always @(posedge pix_clk) begin
if (~resetn) begin
s_axis_ch0_tready <= 1'b0;
s_axis_ch1_tready <= 1'b0;
ch0_frame_sync <= 1'b0;
ch1_frame_sync <= 1'b0;
ch0_exp_eof <= 1'b0;
ch1_exp_eof <= 1'b0;
ch0_exp_eof_1 <= 1'b0;
ch1_exp_eof_1 <= 1'b0;
ch0_win0_x_de <= 1'b0;
ch0_win0_y_de <= 1'b0;
ch0_win1_x_de <= 1'b0;
ch0_win1_y_de <= 1'b0;
ch1_win0_x_de <= 1'b0;
ch1_win0_y_de <= 1'b0;
ch1_win1_x_de <= 1'b0;
ch1_win1_y_de <= 1'b0;
end else begin
ch0_win0_x_de <= (sx >= ch0_win0_sp[31:16]) && (sx <= ch0_win0_ep[31:16]);
ch0_win0_y_de <= (sy >= ch0_win0_sp[15:0] ) && (sy <= ch0_win0_ep[15:0] );
ch0_win1_x_de <= (sx >= ch0_win1_sp[31:16]) && (sx <= ch0_win1_ep[31:16]);
ch0_win1_y_de <= (sy >= ch0_win1_sp[15:0] ) && (sy <= ch0_win1_ep[15:0] );
ch0_exp_eof <= (sx == (ch0_win0_ep[31:16])) && (sy == (ch0_win0_ep[15:0]));
ch1_exp_eof <= (sx == (ch1_win0_ep[31:16])) && (sy == (ch1_win0_ep[15:0]));
ch0_exp_eof_1 <= ch0_exp_eof;
ch1_exp_eof_1 <= ch1_exp_eof;
ch1_win0_x_de <= (sx >= ch1_win0_sp[31:16]) && (sx <= ch1_win0_ep[31:16]);
ch1_win0_y_de <= (sy >= ch1_win0_sp[15:0] ) && (sy <= ch1_win0_ep[15:0] );
ch1_win1_x_de <= (sx >= ch1_win1_sp[31:16]) && (sx <= ch1_win1_ep[31:16]);
ch1_win1_y_de <= (sy >= ch1_win1_sp[15:0] ) && (sy <= ch1_win1_ep[15:0] );
if (ch0_frame_sync) begin
if ((ch0_win0_x_de & ch0_win0_y_de) || // CH0 window 0
(ch0_win1_x_de & ch0_win1_y_de)) begin // CH0 window 1
s_axis_ch0_tready <= 1'b1;
end else begin
s_axis_ch0_tready <= 1'b0;
end
if (ch0_exp_eof_1) begin
ch0_frame_sync <= (s_axis_ch0_tvalid & s_axis_ch0_tready & s_axis_ch0_tuser)? 1'b1 : 1'b0;
end
end else begin
if (s_axis_ch0_tvalid & s_axis_ch0_tready & s_axis_ch0_tuser) begin
s_axis_ch0_tready <= 1'b0;
ch0_frame_sync <= 1'b1;
end else begin
s_axis_ch0_tready <= 1'b1;
end
end
if (ch1_frame_sync) begin
if ((ch1_win0_x_de & ch1_win0_y_de) || // CH1 window 0
(ch1_win1_x_de & ch1_win1_y_de)) begin // CH1 window 1
s_axis_ch1_tready <= 1'b1;
end else begin
s_axis_ch1_tready <= 1'b0;
end
if (ch1_exp_eof_1) begin
ch1_frame_sync <= (s_axis_ch1_tvalid & s_axis_ch1_tready & s_axis_ch1_tuser)? 1'b1 : 1'b0;
end
end else begin
if (s_axis_ch1_tvalid & s_axis_ch1_tready & s_axis_ch1_tuser) begin
s_axis_ch1_tready <= 1'b0;
ch1_frame_sync <= 1'b1;
end else begin
s_axis_ch1_tready <= 1'b1;
end
end
// Palette selection
if (frame) begin
ch0_toggle_palette <= ch0_palette_toggle_ena;
ch1_toggle_palette <= ch1_palette_toggle_ena;
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire de_d;
wire vs_d;
wire hs_d;
pipeline #
(
.PIPE_WIDTH ( 3 ),
.PIPE_STAGES( 2 )
)
pipeline_inst
(
.clk ( pix_clk ),
.cen ( 1'b1 ),
.srst ( ~resetn ),
.pipe_in ( {de, vs, hs} ),
.pipe_out ( {de_d, vs_d, hs_d} )
);
assign red = (s_axis_ch0_tready & ch0_frame_sync)? s_axis_ch0_tdata[23:16] :
(s_axis_ch1_tready & ch1_frame_sync)? s_axis_ch1_tdata[23:16] : back_gnd_rgb[23:16];
assign green = (s_axis_ch0_tready & ch0_frame_sync)? s_axis_ch0_tdata[15:8] :
(s_axis_ch1_tready & ch1_frame_sync)? s_axis_ch1_tdata[15:8] : back_gnd_rgb[15:8];
assign blue = (s_axis_ch0_tready & ch0_frame_sync)? s_axis_ch0_tdata[7:0] :
(s_axis_ch1_tready & ch1_frame_sync)? s_axis_ch1_tdata[7:0] : back_gnd_rgb[7:0];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire tmds_d0;
wire tmds_d1;
wire tmds_d2;
wire tmds_clk;
dvi_generator dvi_out
(
.i_pix_clk ( pix_clk ),
.i_pix_clk_5x ( pix_clk_5x ),
.i_rst ( ~resetn ),
.i_de ( de_d ),
.i_data_ch0 ( blue ),
.i_data_ch1 ( green ),
.i_data_ch2 ( red ),
.i_ctrl_ch0 ( {vs_d, hs_d} ),
.i_ctrl_ch1 ( 2'b00 ),
.i_ctrl_ch2 ( 2'b00 ),
.o_tmds_ch0_serial ( tmds_d0 ),
.o_tmds_ch1_serial ( tmds_d1 ),
.o_tmds_ch2_serial ( tmds_d2 ),
.o_tmds_chc_serial ( tmds_clk )
);
OBUFDS #(.IOSTANDARD("TMDS_33")) OBUFDS_tmds_d0 (.I(tmds_d0), .O(hdmi_tx_p[0]), .OB(hdmi_tx_n[0]));
OBUFDS #(.IOSTANDARD("TMDS_33")) OBUFDS_tmds_d1 (.I(tmds_d1), .O(hdmi_tx_p[1]), .OB(hdmi_tx_n[1]));
OBUFDS #(.IOSTANDARD("TMDS_33")) OBUFDS_tmds_d2 (.I(tmds_d2), .O(hdmi_tx_p[2]), .OB(hdmi_tx_n[2]));
OBUFDS #(.IOSTANDARD("TMDS_33")) OBUFDS_tmds_clk (.I(tmds_clk), .O(hdmi_tx_clk_p), .OB(hdmi_tx_clk_n));
endmodule |
module nuc_dsp
(
input wire clk,
input wire cen,
input wire sresetn,
input wire bypass,
input wire [13:0] din,
input wire [15:0] gain,
input wire [15:0] ofst,
output reg dout_good = 1'b0,
output reg [13:0] dout = {14{1'b0}}
);
localparam DSP_PIPELINE_DELAY = 4;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/*
* -------------------------------------------------------------------------------
*
* gain[15] - bit indicates that current pixel is good/bad (1/0)
* gain[14:0] - is a 15-bit gain correction value.
*
* Note that a gain factor of one i.e. unity gain is 16384.
*
* Excepting dummy gain value of zero (which is not restricted, but useless)
* each pixel can be adjusted within a factor range of 1/16384 to 32767/16384,
* i.e. 0,00006103515625 to 1,99993896484375
*
* -------------------------------------------------------------------------------
*
* ofst[15:0] - is a 16-bit SIGNED (two's complement) offset correction value.
*
* -------------------------------------------------------------------------------
*/
/* Packing arguments to DSP inputs */
wire [17:0] dsp_a = {18{1'b0}}; // dummy value for A-input
wire [17:0] dsp_b = {{3{1'b0}}, gain[14:0]}; // 15-bit gain value
wire [47:0] dsp_c = {{18{ofst[15]}}, ofst, {14{1'b0}}}; // equal to signed ofst[i] * 16384
wire [17:0] dsp_d = {{4{1'b0}}, din}; // raw 14-bit input pixel value
wire [47:0] dsp_p;
/* (D-A)*B+C */
DSP_LINEAR_FUNC dsp
(
.CLK ( clk ), // input CLK
.CE ( cen ), // input CE
.SCLR ( ~sresetn ), // input SCLR
.SEL ( 1'b0 ), // input [0 : 0] SEL
.A ( dsp_a ), // input [17 : 0] A
.B ( dsp_b ), // input [17 : 0] B
.C ( dsp_c ), // input [47 : 0] C
.D ( dsp_d ), // input [17 : 0] D
.P ( dsp_p ) // output [47 : 0] P
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [13:0] din_pipe_out;
pipeline #
(
.PIPE_WIDTH ( 14 ),
.PIPE_STAGES ( DSP_PIPELINE_DELAY )
)
pipeline_din
(
.clk ( clk ),
.cen ( cen ),
.srst ( ~sresetn ),
.pipe_in ( din ),
.pipe_out ( din_pipe_out )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire good_pipe_out;
pipeline #
(
.PIPE_WIDTH ( 1 ),
.PIPE_STAGES ( DSP_PIPELINE_DELAY )
)
pipeline_good_flag
(
.clk ( clk ),
.cen ( cen ),
.srst ( ~sresetn ),
.pipe_in ( gain[15] ),
.pipe_out ( good_pipe_out )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [13:0] dsp_out = dsp_p[27:14]; // result is divided by 16384
wire [19:0] overflow = dsp_p[47:28];
wire sign = dsp_p[47];
always @(posedge clk) begin
if (~sresetn) begin
dout_good <= 1'b0;
dout <= {14{1'b0}};
end else begin
if (cen) begin
if (bypass) begin
dout_good <= 1'b0;
dout <= din_pipe_out;
end else begin
/* Good pixel flag for dout */
dout_good <= good_pipe_out;
/* Adjust only good pixels */
if (good_pipe_out) begin
/* Clip adjusted pixel output in case of overflow */
if (overflow != 20'd0) begin
/* Checking overflow polarity */
dout <= (sign)? {14{1'b0}} : {14{1'b1}};
end else begin
/* Normal output */
dout <= dsp_out;
end
end else begin
/* Zeroing bad pixels */
dout <= {14{1'b0}};
end
end
end
end
end
endmodule |
module axis_nuc
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS_GAIN:S_AXIS_OFST:S_AXIS_RAW:M_AXIS_NUC, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
input wire bypass,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_GAIN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_GAIN TDATA" *) input wire [31:0] s_axis_gain_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_GAIN TVALID" *) input wire s_axis_gain_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_GAIN TREADY" *) output wire s_axis_gain_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_GAIN TLAST" *) input wire s_axis_gain_tlast,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_OFST, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OFST TDATA" *) input wire [31:0] s_axis_ofst_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OFST TVALID" *) input wire s_axis_ofst_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OFST TREADY" *) output wire s_axis_ofst_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OFST TLAST" *) input wire s_axis_ofst_tlast,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_RAW, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TDATA" *) input wire [31:0] s_axis_raw_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TVALID" *) input wire s_axis_raw_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TREADY" *) output wire s_axis_raw_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TLAST" *) input wire s_axis_raw_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_RAW TUSER" *) input wire s_axis_raw_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_NUC, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_NUC TDATA" *) output wire [31:0] m_axis_nuc_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_NUC TVALID" *) output wire m_axis_nuc_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_NUC TREADY" *) input wire m_axis_nuc_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_NUC TLAST" *) output wire m_axis_nuc_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_NUC TUSER" *) output wire m_axis_nuc_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam PIPE_DATA_IN_WIDTH = 32;
localparam PIPE_DATA_OUT_WIDTH = 32;
localparam PIPE_QUAL_WIDTH = 1;
localparam PIPE_STAGES = 5; // nuc_dsp pipeline delay
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [31:0] s_axis_tdata = s_axis_raw_tdata;
wire s_axis_tvalid = s_axis_gain_tvalid & s_axis_ofst_tvalid & s_axis_raw_tvalid;
wire s_axis_tlast = s_axis_raw_tlast;
wire s_axis_tuser = s_axis_raw_tuser;
wire s_axis_tready;
assign s_axis_gain_tready = s_axis_tready & s_axis_tvalid;
assign s_axis_ofst_tready = s_axis_tready & s_axis_tvalid;
assign s_axis_raw_tready = s_axis_tready & s_axis_tvalid;
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( s_axis_tdata ),
.s_axis_tuser ( s_axis_tuser ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.m_axis_tdata ( m_axis_nuc_tdata ),
.m_axis_tuser ( m_axis_nuc_tuser ),
.m_axis_tvalid ( m_axis_nuc_tvalid ),
.m_axis_tready ( m_axis_nuc_tready ),
.m_axis_tlast ( m_axis_nuc_tlast ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [13:0] dout_even;
wire [13:0] dout_odd;
wire dout_even_good;
wire dout_odd_good;
nuc_dsp nuc_dsp_even_pix
(
.clk ( axis_aclk ),
.cen ( pipe_cen ),
.sresetn ( axis_aresetn ),
.bypass ( bypass ),
.din ( pipe_in_data[13:0] ),
.gain ( s_axis_gain_tdata[15:0] ),
.ofst ( s_axis_ofst_tdata[15:0] ),
.dout_good ( dout_even_good ),
.dout ( dout_even )
);
nuc_dsp nuc_dsp_odd_pix
(
.clk ( axis_aclk ),
.cen ( pipe_cen ),
.sresetn ( axis_aresetn ),
.bypass ( bypass ),
.din ( pipe_in_data[29:16] ),
.gain ( s_axis_gain_tdata[31:16] ),
.ofst ( s_axis_ofst_tdata[31:16] ),
.dout_good ( dout_odd_good ),
.dout ( dout_odd )
);
assign pipe_out_data = {
dout_odd_good, 1'b0, dout_odd,
dout_even_good, 1'b0, dout_even
};
endmodule |
module axis_upscaler_top #
(
parameter IMG_RES_X = 0
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS_IMG_X2:M_AXIS_IMG_X4, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [31:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input wire s_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_IMG_X2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG_X2 TDATA" *) output wire [31:0] m_axis_img_x2_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG_X2 TVALID" *) output wire m_axis_img_x2_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG_X2 TREADY" *) input wire m_axis_img_x2_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG_X2 TLAST" *) output wire m_axis_img_x2_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_IMG_X2 TUSER" *) output wire m_axis_img_x2_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Checking input parameters */
generate
if (IMG_RES_X == 0) begin
//INVALID_PARAMETER invalid_parameter_msg();
initial begin
$error("Invalid parameter!");
end
end
endgenerate
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire m_axis_wcd_tvalid;
wire m_axis_wcd_tready;
wire [7:0] m_axis_wcd_tdata;
wire m_axis_wcd_tlast;
wire m_axis_wcd_tuser;
AXIS_WC_4_TO_1 AXIS_WC_4_TO_1_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tdata ( s_axis_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tvalid ( s_axis_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( s_axis_tready ), // output wire s_axis_tready
.s_axis_tlast ( s_axis_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( {s_axis_tuser, 3'b000} ), // input wire [3 : 0] s_axis_tuser
.m_axis_tdata ( m_axis_wcd_tdata ), // output wire [7 : 0] m_axis_tdata
.m_axis_tvalid ( m_axis_wcd_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcd_tready ), // input wire m_axis_tready
.m_axis_tlast ( m_axis_wcd_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcd_tuser ) // output wire [0 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire m_axis_ups_x2_tvalid;
wire m_axis_ups_x2_tready;
wire [7:0] m_axis_ups_x2_tdata;
wire m_axis_ups_x2_tlast;
wire m_axis_ups_x2_tuser;
axis_nn_upscaler #
(
.IMG_RES_X ( IMG_RES_X )
)
axis_nn_upscaler_x2_inst
(
.axis_aresetn ( axis_aresetn ),
.axis_aclk ( axis_aclk ),
.s_axis_tdata ( m_axis_wcd_tdata ),
.s_axis_tvalid ( m_axis_wcd_tvalid ),
.s_axis_tready ( m_axis_wcd_tready ),
.s_axis_tlast ( m_axis_wcd_tlast ),
.s_axis_tuser ( m_axis_wcd_tuser ),
.m_axis_tdata ( m_axis_ups_x2_tdata ),
.m_axis_tvalid ( m_axis_ups_x2_tvalid ),
.m_axis_tready ( m_axis_ups_x2_tready ),
.m_axis_tlast ( m_axis_ups_x2_tlast ),
.m_axis_tuser ( m_axis_ups_x2_tuser )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [31:0] m_axis_wcu_x2_tdata;
wire m_axis_wcu_x2_tvalid;
wire m_axis_wcu_x2_tready;
wire m_axis_wcu_x2_tlast;
wire [3:0] m_axis_wcu_x2_tuser;
AXIS_WC_1_TO_4 AXIS_WC_1_TO_4_inst_x2
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tdata ( m_axis_ups_x2_tdata ), // input wire [7 : 0] s_axis_tdata
.s_axis_tvalid ( m_axis_ups_x2_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( m_axis_ups_x2_tready ), // output wire s_axis_tready
.s_axis_tlast ( m_axis_ups_x2_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( m_axis_ups_x2_tuser ), // input wire [0 : 0] s_axis_tuser
.m_axis_tdata ( m_axis_wcu_x2_tdata ), // output wire [31 : 0] m_axis_tdata
.m_axis_tvalid ( m_axis_wcu_x2_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcu_x2_tready ), // input wire m_axis_tready
.m_axis_tkeep ( /*-------NC-------*/ ), // output wire [3 : 0] m_axis_tkeep
.m_axis_tlast ( m_axis_wcu_x2_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcu_x2_tuser ) // output wire [3 : 0] m_axis_tuser
);
assign m_axis_img_x2_tdata = m_axis_wcu_x2_tdata;
assign m_axis_img_x2_tvalid = m_axis_wcu_x2_tvalid;
assign m_axis_wcu_x2_tready = m_axis_img_x2_tready;
assign m_axis_img_x2_tlast = m_axis_wcu_x2_tlast;
assign m_axis_img_x2_tuser = m_axis_wcu_x2_tuser[3];
endmodule |
module axis_nn_upscaler #
(
parameter IMG_RES_X = 0
)
(
input wire axis_aresetn,
input wire axis_aclk,
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg s_axis_tready = 1'b0,
input wire s_axis_tlast,
input wire s_axis_tuser,
output reg [7:0] m_axis_tdata = 8'h00,
output reg m_axis_tvalid = 1'b0,
input wire m_axis_tready,
output reg m_axis_tlast = 1'b0,
output reg m_axis_tuser = 1'b0 // eof
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Checking input parameters */
generate
if (IMG_RES_X == 0) begin
//INVALID_PARAMETER invalid_parameter_msg();
initial begin
$error("Invalid parameter!");
end
end
endgenerate
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/*
* original upscaled
* m x n 2m x 2n
*
* 1 1 2 2 3 3 4 4
* 1 2 3 4 1 1 2 2 3 3 4 4
* 5 6 7 8 ---> 5 5 6 6 7 7 8 8
* 9 A B C 5 5 6 6 7 7 8 8
* 9 9 A A B B C C
* 9 9 A A B B C C
*/
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg tlast_temp = 1'b0;
reg tuser_temp = 1'b0;
reg fifo_m_axis_tready = 1'b0;
wire fifo_m_axis_tvalid;
wire [7:0] fifo_m_axis_tdata;
wire fifo_m_axis_tlast;
wire fifo_m_axis_tuser;
reg [15:0] x_cnt = 16'd0;
localparam [2:0] ST_RST = 3'd0,
ST_GET_STREAM_PIX = 3'd1,
ST_COPY_STREAM_PIX_0 = 3'd2,
ST_COPY_STREAM_PIX_1 = 3'd3,
ST_GET_FIFO_PIX = 3'd4,
ST_COPY_FIFO_PIX_0 = 3'd5,
ST_COPY_FIFO_PIX_1 = 3'd6;
reg [2:0] state = ST_RST;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
x_cnt <= 16'd0;
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b0;
fifo_m_axis_tready <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
x_cnt <= 16'd0;
m_axis_tvalid <= 1'b0;
fifo_m_axis_tready <= 1'b0;
if (s_axis_tvalid) begin
s_axis_tready <= 1'b1;
state <= ST_GET_STREAM_PIX;
end else begin
s_axis_tready <= 1'b0;
end
end
ST_GET_STREAM_PIX: begin
if (s_axis_tvalid) begin
x_cnt <= x_cnt + 1'b1;
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b1;
m_axis_tlast <= 1'b0;
m_axis_tuser <= 1'b0;
m_axis_tdata <= s_axis_tdata;
state <= ST_COPY_STREAM_PIX_0;
end
end
ST_COPY_STREAM_PIX_0: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b1;
m_axis_tlast <= 1'b0;
m_axis_tuser <= 1'b0;
state <= ST_COPY_STREAM_PIX_1;
end
end
ST_COPY_STREAM_PIX_1: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b0;
if (x_cnt == IMG_RES_X) begin
x_cnt <= 16'd0;
fifo_m_axis_tready <= 1'b1;
state <= ST_GET_FIFO_PIX;
end else begin
s_axis_tready <= 1'b1;
state <= ST_GET_STREAM_PIX;
end
end
end
ST_GET_FIFO_PIX: begin
if (fifo_m_axis_tvalid) begin
x_cnt <= x_cnt + 1'b1;
fifo_m_axis_tready <= 1'b0;
tuser_temp <= fifo_m_axis_tuser;
m_axis_tvalid <= 1'b1;
m_axis_tlast <= 1'b0;
m_axis_tuser <= 1'b0;
m_axis_tdata <= fifo_m_axis_tdata;
state <= ST_COPY_FIFO_PIX_0;
end
end
ST_COPY_FIFO_PIX_0: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b1;
m_axis_tlast <= (x_cnt == IMG_RES_X)? 1'b1 : 1'b0;
m_axis_tuser <= tuser_temp;
state <= ST_COPY_FIFO_PIX_1;
end
end
ST_COPY_FIFO_PIX_1: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b0;
if (x_cnt == IMG_RES_X) begin
x_cnt <= 16'd0;
s_axis_tready <= 1'b1;
state <= ST_GET_STREAM_PIX;
end else begin
fifo_m_axis_tready <= 1'b1;
state <= ST_GET_FIFO_PIX;
end
end
end
endcase
end
end
AXIS_FIFO_1K_X8 AXIS_FIFO_1K_X8_inst
(
.s_aclk (axis_aclk), // input wire s_axis_aclk
.s_aresetn (axis_aresetn), // input wire s_aresetn
.s_axis_tvalid (s_axis_tvalid & s_axis_tready), // input wire s_axis_tvalid
.s_axis_tready (), // output wire s_axis_tready
.s_axis_tdata (s_axis_tdata), // input wire [7 : 0] s_axis_tdata
.s_axis_tlast (s_axis_tlast), // input wire s_axis_tlast
.s_axis_tuser (s_axis_tuser), // input wire [0 : 0] s_axis_tuser
.m_axis_tvalid (fifo_m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready (fifo_m_axis_tready), // input wire m_axis_tready
.m_axis_tdata (fifo_m_axis_tdata), // output wire [7 : 0] m_axis_tdata
.m_axis_tlast (fifo_m_axis_tlast), // output wire m_axis_tlast
.m_axis_tuser (fifo_m_axis_tuser), // output wire [0 : 0] m_axis_tuser
.wr_rst_busy (), // output wire wr_rst_busy
.rd_rst_busy () // output wire rd_rst_busy
);
endmodule |
module axis_img_border_remover #
(
parameter BYPASS_BIT_MASK = 16'h4000
)
(
input wire axis_aclk,
input wire axis_aresetn,
input wire [15:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg s_axis_tready = 1'b0,
input wire s_axis_tlast,
input wire s_axis_tuser,
output reg [15:0] m_axis_tdata = {16{1'b0}},
output reg m_axis_tvalid = 1'b0,
input wire m_axis_tready,
output reg m_axis_tlast = 1'b0,
output reg m_axis_tuser = 1'b0
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST_RST = 2'd0,
ST_GET = 2'd1,
ST_SEND = 2'd2;
reg [1:0] state = ST_RST;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
s_axis_tready <= 1'b1;
m_axis_tvalid <= 1'b0;
state <= ST_GET;
end
ST_GET: begin
if (s_axis_tvalid && (s_axis_tdata & BYPASS_BIT_MASK)) begin
s_axis_tready <= 1'b0;
m_axis_tvalid <= 1'b1;
m_axis_tdata <= s_axis_tdata & (~BYPASS_BIT_MASK);
m_axis_tlast <= s_axis_tlast;
m_axis_tuser <= s_axis_tuser;
state <= ST_SEND;
end
end
ST_SEND: begin
if (m_axis_tready) begin
m_axis_tvalid <= 1'b0;
s_axis_tready <= 1'b1;
state <= ST_GET;
end
end
default: begin
state <= ST_RST;
end
endcase
end
end
endmodule |
module bpr_3x1_interpol
(
input wire clk,
input wire cen,
input wire srst,
input wire [14:0] pix_in_0,
input wire [14:0] pix_in_1,
input wire [14:0] pix_in_2,
output wire [14:0] pix_out_avg
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [14:0] pix_01_avg;
wire [14:0] pix_12_avg;
bpr_averager bpr_averager_01
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_in_0),
.pix_in_1 (pix_in_1),
.pix_out_avg (pix_01_avg)
);
bpr_averager bpr_averager_12
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_in_1),
.pix_in_1 (pix_in_2),
.pix_out_avg (pix_12_avg)
);
bpr_averager bpr_averager_result
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_01_avg),
.pix_in_1 (pix_12_avg),
.pix_out_avg (pix_out_avg)
);
endmodule |
module bpr_3x3_interpol
(
input wire clk,
input wire cen,
input wire srst,
input wire bypass,
input wire [15:0] pix_mid,
input wire [14:0] pix_top_left,
input wire [14:0] pix_top_mid,
input wire [14:0] pix_top_right,
input wire [14:0] pix_mid_left,
input wire [14:0] pix_mid_right,
input wire [14:0] pix_bot_left,
input wire [14:0] pix_bot_mid,
input wire [14:0] pix_bot_right,
output wire [15:0] pix_out
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [14:0] pix_top_avg;
wire [14:0] pix_bot_avg;
wire [14:0] pix_left_avg;
wire [14:0] pix_right_avg;
wire [14:0] pix_horiz_avg;
wire [14:0] pix_vert_avg;
wire [14:0] pix_interpol;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
bpr_3x1_interpol bpr_3x1_interpol_top
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_top_left),
.pix_in_1 (pix_top_mid),
.pix_in_2 (pix_top_right),
.pix_out_avg (pix_top_avg)
);
bpr_3x1_interpol bpr_3x1_interpol_bot
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_bot_left),
.pix_in_1 (pix_bot_mid),
.pix_in_2 (pix_bot_right),
.pix_out_avg (pix_bot_avg)
);
bpr_3x1_interpol bpr_3x1_interpol_left
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_top_left),
.pix_in_1 (pix_mid_left),
.pix_in_2 (pix_bot_left),
.pix_out_avg (pix_left_avg)
);
bpr_3x1_interpol bpr_3x1_interpol_right
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_top_right),
.pix_in_1 (pix_mid_right),
.pix_in_2 (pix_bot_right),
.pix_out_avg (pix_right_avg)
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
bpr_averager bpr_averager_horiz
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_left_avg),
.pix_in_1 (pix_right_avg),
.pix_out_avg (pix_horiz_avg)
);
bpr_averager bpr_averager_vert
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_top_avg),
.pix_in_1 (pix_bot_avg),
.pix_out_avg (pix_vert_avg)
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
bpr_averager bpr_averager_result
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_horiz_avg),
.pix_in_1 (pix_vert_avg),
.pix_out_avg (pix_interpol)
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [15:0] pix_mid_delayed;
pipeline #
(
.PIPE_WIDTH ( 16 ),
.PIPE_STAGES( 4 )
)
pipeline_inst
(
.clk (clk),
.cen (cen),
.srst (srst),
.pipe_in (pix_mid),
.pipe_out (pix_mid_delayed)
);
reg [15:0] out = {16{1'b0}};
always @(posedge clk) begin
if (cen) begin
if (srst) begin
out <= {16{1'b0}};
end else begin
if (bypass | pix_mid_delayed[15]) begin
out <= pix_mid_delayed;
end else begin
if (pix_interpol[14]) begin
out <= {pix_mid_delayed[15:14], pix_interpol[13:0]};
end else begin
out <= {pix_mid_delayed[15:14], {14{1'b0}}};
end
end
end
end
end
assign pix_out = out;
endmodule |
module bpr_averager
(
input wire clk,
input wire cen,
input wire srst,
input wire [14:0] pix_in_0,
input wire [14:0] pix_in_1,
output wire [14:0] pix_out_avg
);
localparam BOTH_BAD = 2'b00,
PIX_1_BAD = 2'b01,
PIX_0_BAD = 2'b10,
BOTH_GOOD = 2'b11;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [14:0] pix_out = {15{1'b0}};
wire pix_0_good_flag = pix_in_0[14];
wire pix_1_good_flag = pix_in_1[14];
wire [14:0] pix_sum = pix_in_0[13:0] + pix_in_1[13:0] + 1'b1;
always @(posedge clk) begin
if (cen) begin
if (srst) begin
pix_out <= {15{1'b0}};
end else begin
case ({pix_1_good_flag, pix_0_good_flag})
BOTH_GOOD: pix_out <= {1'b1, pix_sum[14:1]};
PIX_0_BAD: pix_out <= pix_in_1;
PIX_1_BAD: pix_out <= pix_in_0;
BOTH_BAD: pix_out <= {1'b0, {14{1'b0}}};
endcase
end
end
end
assign pix_out_avg = pix_out;
endmodule |
module axis_bpr_3x3_interpol
(
input wire axis_aclk,
input wire axis_aresetn,
input wire bypass,
input wire [143:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
output wire [15:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser
);
localparam PIPE_DATA_IN_WIDTH = 144;
localparam PIPE_DATA_OUT_WIDTH = 16;
localparam PIPE_QUAL_WIDTH = 1;
localparam PIPE_STAGES = 5;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( s_axis_tdata ),
.s_axis_tuser ( s_axis_tuser ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.m_axis_tdata ( m_axis_tdata ),
.m_axis_tuser ( m_axis_tuser ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( m_axis_tlast ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
wire [15:0] pix_top_left = pipe_in_data[16*6 +: 16];
wire [15:0] pix_top_mid = pipe_in_data[16*7 +: 16];
wire [15:0] pix_top_right = pipe_in_data[16*8 +: 16];
wire [15:0] pix_mid_left = pipe_in_data[16*3 +: 16];
wire [15:0] pix_mid = pipe_in_data[16*4 +: 16];
wire [15:0] pix_mid_right = pipe_in_data[16*5 +: 16];
wire [15:0] pix_bot_left = pipe_in_data[16*0 +: 16];
wire [15:0] pix_bot_mid = pipe_in_data[16*1 +: 16];
wire [15:0] pix_bot_right = pipe_in_data[16*2 +: 16];
wire [15:0] pix_out;
assign pipe_out_data = pix_out;
bpr_3x3_interpol bpr_3x3_interpol_inst
(
.clk ( axis_aclk ),
.srst ( ~axis_aresetn ),
.cen ( pipe_cen ),
.bypass ( bypass ),
.pix_mid ( pix_mid ),
.pix_top_left ( {pix_top_left[15], pix_top_left[13:0]} ),
.pix_top_mid ( {pix_top_mid[15], pix_top_mid[13:0]} ),
.pix_top_right ( {pix_top_right[15], pix_top_right[13:0]} ),
.pix_mid_left ( {pix_mid_left[15], pix_mid_left[13:0]} ),
.pix_mid_right ( {pix_mid_right[15], pix_mid_right[13:0]} ),
.pix_bot_left ( {pix_bot_left[15], pix_bot_left[13:0]} ),
.pix_bot_mid ( {pix_bot_mid[15], pix_bot_mid[13:0]} ),
.pix_bot_right ( {pix_bot_right[15], pix_bot_right[13:0]} ),
.pix_out ( pix_out )
);
endmodule |
module axis_img_border_gen #
(
parameter IMG_RES_X = 336,
parameter IMG_RES_Y = 256,
parameter BORDER_PIX_MASK = 16'h0000,
parameter DATA_PIX_MASK = 16'h0000
)
(
input wire axis_aclk,
input wire axis_aresetn,
input wire [15:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
output wire [15:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [1:0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg axis_bypass = 1'b0;
reg border_valid = 1'b0;
reg border_pix_last = 1'b0;
assign m_axis_tdata = (axis_bypass)? (s_axis_tdata | DATA_PIX_MASK) : BORDER_PIX_MASK;
assign m_axis_tvalid = (axis_bypass)? s_axis_tvalid : border_valid;
assign m_axis_tlast = (axis_bypass)? s_axis_tlast : 1'b0;
assign s_axis_tready = (axis_bypass)? m_axis_tready : 1'b0;
assign m_axis_tuser = {border_pix_last, s_axis_tuser};
reg [15:0] x_cnt = 16'd0;
reg [15:0] y_cnt = 16'd0;
localparam [2:0] ST_RST = 3'd0,
ST_ROW_FIRST_PIX = 3'd1,
ST_SEL_ROW_TYPE = 3'd2,
ST_BORDER_ROW = 3'd3,
ST_DATA_ROW = 3'd4,
ST_ROW_LAST_PIX = 3'd5;
reg [2:0] state = ST_RST;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
x_cnt <= 16'd0;
y_cnt <= 16'd0;
axis_bypass <= 1'b0;
border_valid <= 1'b0;
border_pix_last <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
x_cnt <= 16'd0;
y_cnt <= 16'd0;
axis_bypass <= 1'b0;
border_valid <= 1'b0;
border_pix_last <= 1'b0;
state <= ST_ROW_FIRST_PIX; // wait for frame start?
end
ST_ROW_FIRST_PIX: begin
axis_bypass <= 1'b0;
border_valid <= 1'b1;
border_pix_last <= 1'b0;
state <= ST_SEL_ROW_TYPE;
end
ST_SEL_ROW_TYPE: begin
if (m_axis_tready) begin
x_cnt <= 16'd0;
if ((y_cnt == 16'd0) || (y_cnt == (IMG_RES_Y + 1))) begin
axis_bypass <= 1'b0;
border_valid <= 1'b1;
border_pix_last <= 1'b0;
state <= ST_BORDER_ROW;
end else begin
axis_bypass <= 1'b1;
border_valid <= 1'b0;
border_pix_last <= 1'b0;
state <= ST_DATA_ROW;
end
end
end
ST_BORDER_ROW: begin
if (m_axis_tready) begin
x_cnt <= x_cnt + 1'b1;
if (x_cnt == (IMG_RES_X - 1)) begin
axis_bypass <= 1'b0;
border_valid <= 1'b1;
border_pix_last <= 1'b1;
x_cnt <= 16'd0;
state <= ST_ROW_LAST_PIX;
end
end
end
ST_DATA_ROW: begin
if (m_axis_tvalid & m_axis_tready) begin
x_cnt <= x_cnt + 1'b1;
if (x_cnt == (IMG_RES_X - 1)) begin
axis_bypass <= 1'b0;
border_valid <= 1'b1;
border_pix_last <= 1'b1;
x_cnt <= 16'd0;
state <= ST_ROW_LAST_PIX;
end
end
end
ST_ROW_LAST_PIX: begin
if (m_axis_tready) begin
x_cnt <= 16'd0;
axis_bypass <= 1'b0;
border_valid <= 1'b0;
border_pix_last <= 1'b0;
if (y_cnt == (IMG_RES_Y + 1)) begin
state <= ST_RST;
end else begin
y_cnt <= y_cnt + 1'b1;
state <= ST_ROW_FIRST_PIX;
end
end
end
endcase
end
end
endmodule |
module axis_bad_pix_replacer #
(
parameter IMG_RES_X = 336,
parameter IMG_RES_Y = 256
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
input wire bypass,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [31:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input wire s_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output wire [15:0] m_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output wire m_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input wire m_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output wire m_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output wire m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [15:0] m_axis_wcd_tdata;
wire m_axis_wcd_tvalid;
wire m_axis_wcd_tready;
wire m_axis_wcd_tlast;
wire [1:0] m_axis_wcd_tuser;
AXIS_WC_4_TO_2 AXIS_WC_4_TO_2_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tvalid ( s_axis_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( s_axis_tready ), // output wire s_axis_tready
.s_axis_tdata ( s_axis_tdata ), // input wire [31 : 0] s_axis_tdata
.s_axis_tlast ( s_axis_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( {s_axis_tuser, 3'b000} ), // input wire [3 : 0] s_axis_tuser
.m_axis_tvalid ( m_axis_wcd_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcd_tready ), // input wire m_axis_tready
.m_axis_tdata ( m_axis_wcd_tdata ), // output wire [15 : 0] m_axis_tdata
.m_axis_tlast ( m_axis_wcd_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcd_tuser ) // output wire [1 : 0] m_axis_tuser
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [15:0] brd_axis_m_tdata;
wire brd_axis_m_tready;
wire brd_axis_m_tvalid;
wire brd_axis_m_tlast;
wire [1:0] brd_axis_m_tuser;
/*
* Incoming 16-bit word structure:
* m_axis_wcd_tdata[15] - good pixel flag
* m_axis_wcd_tdata[14] - not used, reserved
* m_axis_wcd_tdata[13:0] - 14-bit pixel data
*/
axis_img_border_gen #
(
.IMG_RES_X ( IMG_RES_X ),
.IMG_RES_Y ( IMG_RES_Y ),
.BORDER_PIX_MASK ( 16'h0000 ),
.DATA_PIX_MASK ( 16'h4000 )
)
axis_img_border_gen_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( m_axis_wcd_tdata ),
.s_axis_tvalid ( m_axis_wcd_tvalid ),
.s_axis_tready ( m_axis_wcd_tready ),
.s_axis_tlast ( m_axis_wcd_tlast ),
.s_axis_tuser ( m_axis_wcd_tuser[1] ),
.m_axis_tdata ( brd_axis_m_tdata ),
.m_axis_tvalid ( brd_axis_m_tvalid ),
.m_axis_tready ( brd_axis_m_tready ),
.m_axis_tlast ( brd_axis_m_tlast ),
.m_axis_tuser ( brd_axis_m_tuser ) // TUSER[0] is EOF strobe, while TUSER[1] is a new "TLAST" strobe for border pixels
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg line_0_ena = 1'b0;
reg line_1_ena = 1'b0;
reg line_2_ena = 1'b0;
reg [16*9 - 1:0] matrix_3x3 = {16*9{1'b0}};
reg matrix_3x3_valid = 1'b0;
reg [1:0] matrix_3x3_last = 2'b00;
reg [1:0] matrix_3x3_user = 2'b00;
wire matrix_3x3_ready;
wire [15:0] line_0_axis_m_tdata;
wire line_0_axis_m_tready;
wire line_0_axis_m_tvalid;
wire line_0_axis_m_tlast;
wire [1:0] line_0_axis_m_tuser;
wire [15:0] line_1_axis_m_tdata;
wire line_1_axis_m_tready;
wire line_1_axis_m_tvalid;
wire line_1_axis_m_tlast;
wire [1:0] line_1_axis_m_tuser;
wire [15:0] line_2_axis_m_tdata;
wire line_2_axis_m_tready = line_2_ena;
wire line_2_axis_m_tvalid;
wire line_2_axis_m_tlast;
wire [1:0] line_2_axis_m_tuser;
wire [15:0] fixed_pix_m_axis_tdata;
wire fixed_pix_m_axis_tvalid;
wire fixed_pix_m_axis_tready;
wire fixed_pix_m_axis_tlast;
wire fixed_pix_m_axis_tuser;
AXIS_FIFO_2K_X16 AXIS_FIFO_2K_X16_bpr_line_0
(
.s_aclk ( axis_aclk ), // input s_aclk
.s_aresetn ( axis_aresetn ), // input s_aresetn
.s_axis_tvalid ( brd_axis_m_tvalid ), // input s_axis_tvalid
.s_axis_tready ( brd_axis_m_tready ), // output s_axis_tready
.s_axis_tdata ( brd_axis_m_tdata ), // input [15 : 0] s_axis_tdata
.s_axis_tlast ( brd_axis_m_tlast ), // input s_axis_tlast
.s_axis_tuser ( brd_axis_m_tuser ), // input [1 : 0] s_axis_tuser
.m_axis_tvalid ( line_0_axis_m_tvalid ), // output m_axis_tvalid
.m_axis_tready ( line_0_axis_m_tready & line_0_ena), // input m_axis_tready
.m_axis_tdata ( line_0_axis_m_tdata ), // output [15 : 0] m_axis_tdata
.m_axis_tlast ( line_0_axis_m_tlast ), // output m_axis_tlast
.m_axis_tuser ( line_0_axis_m_tuser ), // output [0 : 0] m_axis_tuser
.wr_rst_busy ( /*-------NC-------*/ ), // output wire wr_rst_busy
.rd_rst_busy ( /*-------NC-------*/ ) // output wire rd_rst_busy
);
AXIS_FIFO_2K_X16 AXIS_FIFO_2K_X16_bpr_line_1
(
.s_aclk ( axis_aclk ), // input s_aclk
.s_aresetn ( axis_aresetn ), // input s_aresetn
.s_axis_tvalid ( line_0_axis_m_tvalid & line_0_ena), // input s_axis_tvalid
.s_axis_tready ( line_0_axis_m_tready ), // output s_axis_tready
.s_axis_tdata ( line_0_axis_m_tdata ), // input [15 : 0] s_axis_tdata
.s_axis_tlast ( line_0_axis_m_tlast ), // input s_axis_tlast
.s_axis_tuser ( line_0_axis_m_tuser ), // input [1 : 0] s_axis_tuser
.m_axis_tvalid ( line_1_axis_m_tvalid ), // output m_axis_tvalid
.m_axis_tready ( line_1_axis_m_tready & line_1_ena), // input m_axis_tready
.m_axis_tdata ( line_1_axis_m_tdata ), // output [15 : 0] m_axis_tdata
.m_axis_tlast ( line_1_axis_m_tlast ), // output m_axis_tlast
.m_axis_tuser ( line_1_axis_m_tuser ), // output [1 : 0] m_axis_tuser
.wr_rst_busy ( /*-------NC-------*/ ), // output wire wr_rst_busy
.rd_rst_busy ( /*-------NC-------*/ ) // output wire rd_rst_busy
);
AXIS_FIFO_2K_X16 AXIS_FIFO_2K_X16_bpr_line_2
(
.s_aclk ( axis_aclk ), // input s_aclk
.s_aresetn ( axis_aresetn ), // input s_aresetn
.s_axis_tvalid ( line_1_axis_m_tvalid & line_1_ena), // input s_axis_tvalid
.s_axis_tready ( line_1_axis_m_tready ), // output s_axis_tready
.s_axis_tdata ( line_1_axis_m_tdata ), // input [15 : 0] s_axis_tdata
.s_axis_tlast ( line_1_axis_m_tlast ), // input s_axis_tlast
.s_axis_tuser ( line_1_axis_m_tuser ), // input [1 : 0] s_axis_tuser
.m_axis_tvalid ( line_2_axis_m_tvalid ), // output m_axis_tvalid
.m_axis_tready ( line_2_axis_m_tready ), // input m_axis_tready
.m_axis_tdata ( line_2_axis_m_tdata ), // output [15 : 0] m_axis_tdata
.m_axis_tlast ( line_2_axis_m_tlast ), // output m_axis_tlast
.m_axis_tuser ( line_2_axis_m_tuser ), // output [1 : 0] m_axis_tuser
.wr_rst_busy ( /*-------NC-------*/ ), // output wire wr_rst_busy
.rd_rst_busy ( /*-------NC-------*/ ) // output wire rd_rst_busy
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST_RST = 2'd0,
ST_FILL_PIPELINE = 2'd1,
ST_GET_PIX_COLUMN = 2'd2,
ST_SEND_PIX_MATRIX = 2'd3;
reg [1:0] state = ST_RST;
reg first_row_passed = 1'b0;
always @(posedge axis_aclk) begin
if (~axis_aresetn) begin
line_0_ena <= 1'b0;
line_1_ena <= 1'b0;
line_2_ena <= 1'b0;
matrix_3x3_valid <= 1'b0;
first_row_passed <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
line_0_ena <= 1'b1;
line_1_ena <= 1'b1;
line_2_ena <= 1'b0;
matrix_3x3_valid <= 1'b0;
first_row_passed <= 1'b0;
state <= ST_FILL_PIPELINE; // TODO: wait for frame start?
end
ST_FILL_PIPELINE: begin
// Line 1 FIFO contains complete row if we pass 2 rows for the 1th and 2nd FIFO
if (line_0_axis_m_tvalid & line_0_axis_m_tready & line_0_axis_m_tuser[1]) begin
first_row_passed <= 1'b1;
line_0_ena <= (first_row_passed)? 1'b0 : 1'b1;
end
// Line 2 FIFO contains complete row
if (line_1_axis_m_tvalid & line_1_axis_m_tready & line_1_axis_m_tuser[1]) begin
line_1_ena <= 1'b0;
end
if (~line_0_ena & ~line_1_ena) begin
state <= ST_GET_PIX_COLUMN;
end
end
ST_GET_PIX_COLUMN: begin
if (line_0_axis_m_tvalid) begin
line_0_ena <= 1'b1;
line_1_ena <= 1'b1;
line_2_ena <= 1'b1;
matrix_3x3_last <= {matrix_3x3_last[0], line_1_axis_m_tlast};
matrix_3x3_user <= {matrix_3x3_user[0], line_1_axis_m_tuser[0]};
matrix_3x3_valid <= 1'b1;
matrix_3x3 <= {
line_2_axis_m_tdata, matrix_3x3[16*9 - 1 : 16*7], // 16*9 - 1 : 16*6
line_1_axis_m_tdata, matrix_3x3[16*6 - 1 : 16*4], // 16*6 - 1 : 16*3
line_0_axis_m_tdata, matrix_3x3[16*3 - 1 : 16*1] // 16*3 - 1 : 0
};
state <= ST_SEND_PIX_MATRIX;
end
end
ST_SEND_PIX_MATRIX: begin
line_0_ena <= 1'b0;
line_1_ena <= 1'b0;
line_2_ena <= 1'b0;
if (matrix_3x3_ready) begin
matrix_3x3_valid <= 1'b0;
state <= ST_GET_PIX_COLUMN;
end
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
axis_bpr_3x3_interpol axis_bpr_3x3_interpol_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.bypass ( bypass ),
.s_axis_tdata ( matrix_3x3 ),
.s_axis_tvalid ( matrix_3x3_valid ),
.s_axis_tready ( matrix_3x3_ready ),
.s_axis_tlast ( matrix_3x3_last[1] ),
.s_axis_tuser ( matrix_3x3_user[1] ),
.m_axis_tdata ( fixed_pix_m_axis_tdata ),
.m_axis_tvalid ( fixed_pix_m_axis_tvalid ),
.m_axis_tready ( fixed_pix_m_axis_tready ),
.m_axis_tlast ( fixed_pix_m_axis_tlast ),
.m_axis_tuser ( fixed_pix_m_axis_tuser )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
axis_img_border_remover #
(
.BYPASS_BIT_MASK ( 16'h4000 )
)
axis_img_border_remover_inst
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( fixed_pix_m_axis_tdata ),
.s_axis_tvalid ( fixed_pix_m_axis_tvalid ),
.s_axis_tready ( fixed_pix_m_axis_tready ),
.s_axis_tlast ( fixed_pix_m_axis_tlast ),
.s_axis_tuser ( fixed_pix_m_axis_tuser ),
.m_axis_tdata ( m_axis_tdata ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( m_axis_tlast ),
.m_axis_tuser ( m_axis_tuser )
);
endmodule |
module axis_hist_remapper
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [15:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input wire s_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output wire [31:0] m_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output wire m_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input wire m_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *) output wire m_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output wire m_axis_tuser,
input wire hist_lut_ram_we,
input wire [13:0] hist_lut_ram_addr,
input wire [7:0] hist_lut_ram_din
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam PIPE_DATA_IN_WIDTH = 14;
localparam PIPE_DATA_OUT_WIDTH = 8;
localparam PIPE_QUAL_WIDTH = 1;
localparam PIPE_STAGES = 2;
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
wire [7:0] m_axis_pipe_tdata;
wire m_axis_pipe_tvalid;
wire m_axis_pipe_tready;
wire m_axis_pipe_tlast;
wire m_axis_pipe_tuser;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( s_axis_tdata[13:0] ),
.s_axis_tuser ( s_axis_tuser ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.m_axis_tdata ( m_axis_pipe_tdata ),
.m_axis_tuser ( m_axis_pipe_tuser ),
.m_axis_tvalid ( m_axis_pipe_tvalid ),
.m_axis_tready ( m_axis_pipe_tready ),
.m_axis_tlast ( m_axis_pipe_tlast ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
HIST_LUT_RAM HIST_LUT_RAM
(
.clka ( axis_aclk ), // input clka
.ena ( 1'b1 ), // input ena
.wea ( hist_lut_ram_we ), // input [0 : 0] wea
.addra ( hist_lut_ram_addr ), // input [13 : 0] addra
.dina ( hist_lut_ram_din ), // input [7 : 0] dina
.clkb ( axis_aclk ), // input clkb
.enb ( pipe_cen ), // input enb
.addrb ( pipe_in_data ), // input [13 : 0] addrb
.doutb ( pipe_out_data ) // output [7 : 0] doutb
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [31:0] m_axis_wcu_tdata;
wire m_axis_wcu_tvalid;
wire m_axis_wcu_tready;
wire m_axis_wcu_tlast;
wire [3:0] m_axis_wcu_tuser;
AXIS_WC_1_TO_4 AXIS_WC_1_TO_4_inst
(
.aclk ( axis_aclk ), // input wire aclk
.aresetn ( axis_aresetn ), // input wire aresetn
.s_axis_tvalid ( m_axis_pipe_tvalid ), // input wire s_axis_tvalid
.s_axis_tready ( m_axis_pipe_tready ), // output wire s_axis_tready
.s_axis_tdata ( m_axis_pipe_tdata ), // input wire [7 : 0] s_axis_tdata
.s_axis_tlast ( m_axis_pipe_tlast ), // input wire s_axis_tlast
.s_axis_tuser ( m_axis_pipe_tuser ), // input wire [0 : 0] s_axis_tuser
.m_axis_tvalid ( m_axis_wcu_tvalid ), // output wire m_axis_tvalid
.m_axis_tready ( m_axis_wcu_tready ), // input wire m_axis_tready
.m_axis_tdata ( m_axis_wcu_tdata ), // output wire [31 : 0] m_axis_tdata
.m_axis_tkeep ( /*-------NC-------*/ ), // output wire [3 : 0] m_axis_tkeep
.m_axis_tlast ( m_axis_wcu_tlast ), // output wire m_axis_tlast
.m_axis_tuser ( m_axis_wcu_tuser ) // output wire [3 : 0] m_axis_tuser
);
assign m_axis_tdata = m_axis_wcu_tdata;
assign m_axis_tvalid = m_axis_wcu_tvalid;
assign m_axis_tlast = m_axis_wcu_tlast;
assign m_axis_tuser = m_axis_wcu_tuser[3];
assign m_axis_wcu_tready = m_axis_tready;
endmodule |
module hist_rebuilder
(
input wire clk,
input wire srst,
output wire raw_hist_upd,
input wire raw_hist_rdy,
input wire hist_equal_type,
output wire raw_hist_ram_we,
output wire [13:0] raw_hist_ram_addr,
output wire [17:0] raw_hist_ram_din,
input wire [17:0] raw_hist_ram_dout,
output wire hist_lut_ram_we,
output wire [13:0] hist_lut_ram_addr,
output wire [7:0] hist_lut_ram_din
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam HIST_EQUAL_LINEAR = 1'b0,
HIST_EQUAL_SQRT = 1'b1;
reg [13:0] hist_ram_addr = {14{1'b0}};
reg [13:0] lut_ram_addr = {14{1'b0}};
reg [17:0] hist_raw_max_new = {18{1'b0}};
reg [17:0] hist_raw_max = {18{1'b0}};
reg [17:0] hist_raw_min_new = {18{1'b1}};
reg [17:0] hist_raw_min = {18{1'b1}};
reg [17:0] diff_max = {18{1'b0}};
reg [17:0] diff_min = {18{1'b0}};
reg hist_upd = 1'b0;
reg hist_remap = 1'b0;
reg equal_type = 1'b0;
reg [17:0] scaler_div = {18{1'b0}};
reg [17:0] scaler_add = {18{1'b0}};
reg [13:0] scaler_din = {14{1'b0}};
reg scaler_din_valid = 1'b0;
wire scaler_din_rdy;
wire [7:0] scaler_dout;
wire scaler_dout_valid;
assign raw_hist_upd = hist_upd;
assign raw_hist_ram_we = 1'b0;
assign raw_hist_ram_din = {18{1'b0}};
assign raw_hist_ram_addr = hist_ram_addr;
assign hist_lut_ram_we = scaler_dout_valid;
assign hist_lut_ram_din = scaler_dout;
assign hist_lut_ram_addr = lut_ram_addr;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [3:0] ST_LNR_0 = 4'd0,
ST_LNR_1 = 4'd1,
ST_LNR_2 = 4'd2,
ST_LNR_3 = 4'd3,
ST_LNR_4 = 4'd4,
ST_LNR_5 = 4'd5,
ST_LNR_6 = 4'd6,
ST_LNR_7 = 4'd7,
ST_LNR_8 = 4'd8,
ST_LNR_9 = 4'd9,
ST_LNR_10 = 4'd10,
ST_LNR_11 = 4'd11,
ST_LNR_DONE = 4'd12,
FSM_LNR_RESET_STATE = ST_LNR_0;
reg [3:0] lnr_state = FSM_LNR_RESET_STATE;
wire lnr_done = (lnr_state == ST_LNR_DONE);
task hist_linear_equalize;
begin
case (lnr_state)
ST_LNR_0: begin
hist_remap <= 1'b0;
hist_ram_addr <= 14'd0;
hist_raw_max_new <= {18{1'b0}};
hist_raw_min_new <= {18{1'b1}};
lnr_state <= ST_LNR_2;
end
/* Searching for min value */
ST_LNR_1: begin
if (hist_ram_addr < 14'd16383) begin
hist_ram_addr <= hist_ram_addr + 1'b1;
lnr_state <= ST_LNR_2;
end else begin
/* Failed to find min value */
hist_raw_min_new <= {4'h0, {14{1'b0}}};
hist_ram_addr <= 14'd16383;
lnr_state <= ST_LNR_5;
end
end
/* RAM single cycle read latency */
ST_LNR_2: begin
lnr_state <= ST_LNR_3;
end
/* Save new min value */
ST_LNR_3: begin
if (raw_hist_ram_dout != 18'd0) begin
hist_raw_min_new <= {4'h0, hist_ram_addr};
hist_ram_addr <= 14'd16383;
lnr_state <= ST_LNR_5;
end else begin
lnr_state <= ST_LNR_1;
end
end
/* Searching for max value */
ST_LNR_4: begin
if (hist_ram_addr > 14'd0) begin
hist_ram_addr <= hist_ram_addr - 1'b1;
lnr_state <= ST_LNR_5;
end else begin
/* Failed to find max value */
hist_raw_max_new <= {4'h0, {14{1'b1}}};
lnr_state <= ST_LNR_7;
end
end
/* RAM single cycle read latency */
ST_LNR_5: begin
lnr_state <= ST_LNR_6;
end
/* Save new max value */
ST_LNR_6: begin
if (raw_hist_ram_dout != 18'd0) begin
hist_raw_max_new <= {4'h0, hist_ram_addr};
lnr_state <= ST_LNR_7;
end else begin
lnr_state <= ST_LNR_4;
end
end
/* We are going to map the middle (~97%) of the histogram,
* by cutting out min and max "bins" to make AGC procedure
* to be well immune against large and rapid deviation of
* very small amount of pixels. That helps to prevent
* undesirable image flickering */
ST_LNR_7: begin
hist_raw_max_new <= hist_raw_max_new - ((hist_raw_max_new - hist_raw_min_new) >> 6);
hist_raw_min_new <= hist_raw_min_new + ((hist_raw_max_new - hist_raw_min_new) >> 6);
lnr_state <= ST_LNR_8;
end
/* Calculating differences of the histogram width*/
ST_LNR_8: begin
/* Absolute difference of max */
if (hist_raw_max_new >= hist_raw_max) begin
diff_max <= hist_raw_max_new - hist_raw_max;
end else begin
diff_max <= hist_raw_max - hist_raw_max_new;
end
/* Absolute difference of min */
if (hist_raw_min_new >= hist_raw_min) begin
diff_min <= hist_raw_min_new - hist_raw_min;
end else begin
diff_min <= hist_raw_min - hist_raw_min_new;
end
lnr_state <= ST_LNR_9;
end
/* Due to LSB noise the max and min values will be updated
* only when crossing the threshold. This measure also
* prevents undesirable image flickering */
ST_LNR_9: begin
hist_raw_max <= (diff_max > 18'd3)? hist_raw_max_new : hist_raw_max; // TODO: define threshold value !!!
hist_raw_min <= (diff_min > 18'd3)? hist_raw_min_new : hist_raw_min; // TODO: define threshold value !!!
lnr_state <= ST_LNR_10;
end
/* Preparing parameters for histogram scaling */
ST_LNR_10: begin
scaler_div <= hist_raw_max - hist_raw_min;
scaler_add <= hist_raw_min;
scaler_din <= 14'd0;
scaler_din_valid <= 1'b1;
hist_remap <= 1'b1;
lnr_state <= ST_LNR_11;
end
/* Feeding histogram scaler with data counter */
ST_LNR_11: begin
if (scaler_din_rdy) begin
if (scaler_din < 14'd16383) begin
scaler_din <= scaler_din + 1'b1;
end else begin
scaler_din_valid <= 1'b0;
hist_remap <= 1'b0;
lnr_state <= ST_LNR_DONE;
end
end
end
ST_LNR_DONE: begin
lnr_state <= FSM_LNR_RESET_STATE;
end
endcase
end
endtask
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST_RST = 2'd0,
ST_RAW_HIST_UPD_START = 2'd1,
ST_RAW_HIST_UPD_FINISH = 2'd2,
ST_RAW_HIST_EQUAL = 2'd3;
reg [1:0] state = ST_RST;
always @(posedge clk) begin
if (srst) begin
hist_remap <= 1'b0;
hist_upd <= 1'b0;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
if (raw_hist_rdy) begin
hist_upd <= 1'b1;
state <= ST_RAW_HIST_UPD_START;
end else begin
hist_upd <= 1'b0;
end
end
ST_RAW_HIST_UPD_START: begin
if (~raw_hist_rdy) begin
hist_upd <= 1'b0;
state <= ST_RAW_HIST_UPD_FINISH;
end
end
ST_RAW_HIST_UPD_FINISH: begin
if (raw_hist_rdy) begin
equal_type <= hist_equal_type;
state <= ST_RAW_HIST_EQUAL;
end
end
ST_RAW_HIST_EQUAL: begin
/* Only linear histogram equalization is
* implemented for now, though multiple
* modes are supposed to be */
hist_linear_equalize();
state <= (lnr_done)? ST_RST : state;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
hist_scaler hist_scaler_inst
(
.clk ( clk ),
.srst ( srst ),
.div ( scaler_div ),
.add ( scaler_add ),
.din ( (scaler_din > hist_raw_max)? hist_raw_max : scaler_din),
.din_valid ( scaler_din_valid ),
.din_rdy ( scaler_din_rdy ),
.dout ( scaler_dout ),
.dout_valid ( scaler_dout_valid )
);
always @(posedge clk) begin
if (~hist_remap) begin
lut_ram_addr <= {14{1'b0}};
end else begin
if (scaler_dout_valid) begin
lut_ram_addr <= lut_ram_addr + 1'b1;
end
end
end
endmodule |
module axis_hist_equalizer
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS, ASSOCIATED_RESET s_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [15:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input wire s_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
output wire hist_lut_ram_we,
output wire [13:0] hist_lut_ram_addr,
output wire [7:0] hist_lut_ram_din
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire raw_hist_wea;
wire [13:0] raw_hist_addra;
wire [17:0] raw_hist_dina;
wire [17:0] raw_hist_douta;
wire raw_hist_web;
wire [13:0] raw_hist_addrb;
wire [17:0] raw_hist_dinb;
wire [17:0] raw_hist_doutb;
wire raw_hist_upd;
wire raw_hist_rdy;
hist_calc hist_calc_inst
(
.clk ( s_axis_aclk ),
.srst ( ~s_axis_aresetn ),
.hist_upd ( raw_hist_upd ),
.hist_rdy ( raw_hist_rdy ),
.s_axis_tdata ( s_axis_tdata ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( s_axis_tlast ),
.s_axis_tuser ( s_axis_tuser ),
.ram_we ( raw_hist_wea ),
.ram_addr ( raw_hist_addra ),
.ram_din ( raw_hist_dina ),
.ram_dout ( raw_hist_douta )
);
RAW_HIST_RAM RAW_HIST_RAM_inst
(
.clka ( s_axis_aclk ), // input clka
.ena ( 1'b1 ), // input wire ena
.wea ( raw_hist_wea ), // input [0 : 0] wea
.addra ( raw_hist_addra ), // input [13 : 0] addra
.dina ( raw_hist_dina ), // input [17 : 0] dina
.douta ( raw_hist_douta ), // output [17 : 0] douta
.clkb ( s_axis_aclk ), // input clkb
.enb ( 1'b1 ), // input wire enb
.web ( raw_hist_web ), // input [0 : 0] web
.addrb ( raw_hist_addrb ), // input [13 : 0] addrb
.dinb ( raw_hist_dinb ), // input [17 : 0] dinb
.doutb ( raw_hist_doutb ) // output [17 : 0] doutb
);
hist_rebuilder hist_rebuilder_inst
(
.clk ( s_axis_aclk ),
.srst ( ~s_axis_aresetn ),
.raw_hist_upd ( raw_hist_upd ),
.raw_hist_rdy ( raw_hist_rdy ),
.hist_equal_type ( 1'b0 ),
.raw_hist_ram_we ( raw_hist_web ),
.raw_hist_ram_addr ( raw_hist_addrb ),
.raw_hist_ram_din ( raw_hist_dinb ),
.raw_hist_ram_dout ( raw_hist_doutb ),
.hist_lut_ram_we ( hist_lut_ram_we ),
.hist_lut_ram_addr ( hist_lut_ram_addr ),
.hist_lut_ram_din ( hist_lut_ram_din )
);
endmodule |
module hist_calc
(
input wire clk,
input wire srst,
input wire hist_upd,
output reg hist_rdy = 1'b1,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [15:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output reg s_axis_tready = 1'b1,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *) input wire s_axis_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
output reg ram_we = 1'b0,
output reg [13:0] ram_addr = {14{1'b0}},
output reg [17:0] ram_din = {18{1'b0}},
input wire [17:0] ram_dout
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pix_good = s_axis_tdata[15];
wire [13:0] pix_data = s_axis_tdata[13:0];
localparam [2:0] ST_RST = 3'd0,
ST_ERASE_HIST = 3'd1,
ST_WAIT_SOF = 3'd2,
ST_WAIT_VALID_PIX = 3'd3,
ST_GET_HIST_BIN = 3'd4,
ST_UPD_HIST_BIN = 3'd5;
reg [2:0] state = ST_RST;
always @(posedge clk) begin
if (srst) begin
hist_rdy <= 1'b1;
ram_we <= 1'b0;
s_axis_tready <= 1'b1;
state <= ST_RST;
end else begin
case (state)
ST_RST: begin
s_axis_tready <= 1'b1;
if (hist_upd) begin
hist_rdy <= 1'b0;
ram_we <= 1'b1;
ram_din <= {18{1'b0}};
ram_addr <= {14{1'b0}};
state <= ST_ERASE_HIST;
end else begin
ram_we <= 1'b0;
hist_rdy <= 1'b1;
end
end
ST_ERASE_HIST: begin
if (ram_addr < {14{1'b1}}) begin
ram_addr <= ram_addr + 1'b1;
end else begin
ram_we <= 1'b0;
state <= ST_WAIT_SOF;
end
end
ST_WAIT_SOF: begin
if (s_axis_tvalid & s_axis_tuser) begin
s_axis_tready <= 1'b0;
state <= ST_WAIT_VALID_PIX;
end
end
ST_WAIT_VALID_PIX: begin
ram_we <= 1'b0;
if (s_axis_tvalid & s_axis_tuser) begin
s_axis_tready <= 1'b1;
state <= ST_RST;
end else begin
if (s_axis_tvalid) begin
s_axis_tready <= 1'b1;
if (pix_good) begin
ram_addr <= pix_data;
state <= ST_GET_HIST_BIN;
end
end else begin
s_axis_tready <= 1'b0;
end
end
end
ST_GET_HIST_BIN: begin
s_axis_tready <= 1'b0;
state <= ST_UPD_HIST_BIN;
end
ST_UPD_HIST_BIN: begin
ram_we <= 1'b1;
ram_din <= ram_dout + 1'b1;
state <= ST_WAIT_VALID_PIX;
end
default: begin
state <= ST_RST;
end
endcase
end
end
endmodule |
module hist_scaler
(
input wire clk,
input wire srst,
input wire [17:0] div,
input wire [17:0] add,
input wire [13:0] din,
input wire din_valid,
output wire din_rdy,
output wire [7:0] dout,
output wire dout_valid
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [47:0] dsp_P_tdata;
wire dsp_P_tvalid;
wire dsp_P_tready;
wire [17:0] dsp_D_tdata = {4'h0, din};
wire [17:0] dsp_A_tdata = (add > dsp_D_tdata)? dsp_D_tdata : add;
axis_dsp_linear_func axis_dsp_linear_func_inst
(
.axis_aclk ( clk ),
.axis_aresetn ( ~srst ),
.dsp_func_sel ( 1'b0 ), // P = (D-A)*B+C
.dsp_D_s_axis_tdata ( dsp_D_tdata ),
.dsp_D_s_axis_tvalid ( din_valid ),
.dsp_D_s_axis_tready ( din_rdy ),
.dsp_D_s_axis_tlast ( 1'b0 ),
.dsp_A_s_axis_tdata ( dsp_A_tdata ),
.dsp_A_s_axis_tvalid ( 1'b1 ),
.dsp_A_s_axis_tready ( /*---NC---*/ ),
.dsp_A_s_axis_tlast ( 1'b0 ),
.dsp_B_s_axis_tdata ( 18'd255 ),
.dsp_B_s_axis_tvalid ( 1'b1 ),
.dsp_B_s_axis_tready ( /*---NC---*/ ),
.dsp_B_s_axis_tlast ( 1'b0 ),
.dsp_C_s_axis_tdata ( 48'd0 ),
.dsp_C_s_axis_tvalid ( 1'b1 ),
.dsp_C_s_axis_tready ( /*---NC---*/ ),
.dsp_C_s_axis_tlast ( 1'b0 ),
.dsp_P_m_axis_tdata ( dsp_P_tdata ),
.dsp_P_m_axis_tvalid ( dsp_P_tvalid ),
.dsp_P_m_axis_tready ( dsp_P_tready ),
.dsp_P_m_axis_tlast ( /*---NC---*/ )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [23:0] divider_output;
AXIS_HIST_SCALE_DIVIDER AXIS_HIST_SCALE_DIVIDER_inst
(
.aclk ( clk ), // input wire aclk
.aresetn ( ~srst ), // input wire aresetn
.s_axis_divisor_tvalid ( 1'b1 ), // input wire s_axis_divisor_tvalid
.s_axis_divisor_tready ( /*----------NC----------*/ ), // output wire s_axis_divisor_tready
.s_axis_divisor_tdata ( {2'b00, div[13:0]} ), // input wire [15 : 0] s_axis_divisor_tdata
.s_axis_dividend_tvalid ( dsp_P_tvalid ), // input wire s_axis_dividend_tvalid
.s_axis_dividend_tready ( dsp_P_tready ), // output wire s_axis_dividend_tready
.s_axis_dividend_tdata ( {2'b00, dsp_P_tdata[21:0]} ), // input wire [23 : 0] s_axis_dividend_tdata
.m_axis_dout_tvalid ( dout_valid ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata ( divider_output ) // output wire [23 : 0] m_axis_dout_tdata
);
assign dout = (divider_output > 24'd255)? 8'd255 : divider_output[7:0];
endmodule |
module top
(
input wire extclk,
inout wire [19:0] gpio_sensor,
output wire tmds_d0_p,
output wire tmds_d0_n,
output wire tmds_d1_p,
output wire tmds_d1_n,
output wire tmds_d2_p,
output wire tmds_d2_n,
output wire tmds_clk_p,
output wire tmds_clk_n,
output wire hram_r0_ck_p,
output wire hram_r0_ck_n,
output wire hram_r0_reset_n,
output wire hram_r0_cs_n,
inout wire hram_r0_rwds,
inout wire [7:0] hram_r0_dq,
output wire hram_r1_ck_p,
output wire hram_r1_ck_n,
output wire hram_r1_reset_n,
output wire hram_r1_cs_n,
inout wire hram_r1_rwds,
inout wire [7:0] hram_r1_dq,
inout wire cnfg_cs_n,
inout wire cnfg_mosi_miso_0,
inout wire cnfg_miso_miso_1,
inout wire cnfg_miso_2,
inout wire cnfg_miso_3,
output wire fx2_ifclk,
output wire av_clkin,
input wire fx2_pa0,
output wire fx2_pa1_led_act_y,
input wire fx2_pa2,
output wire fx2_pa3_led_act_r,
input wire fx2_pa4,
input wire fx2_pa5,
input wire fx2_pa6,
input wire fx2_pa7_hdmi_cec,
input wire [7:0] fx2_pb,
input wire [7:0] fx2_av_pd,
input wire fx2_rdy0_slrd,
input wire fx2_rdy1_slwr,
input wire fx2_ctl0_flaga,
input wire fx2_ctl1_flagb,
input wire fx2_ctl2_flagc,
output wire lcd_led_ctrl,
output wire lcd_spi_dat,
output wire lcd_spi_sck,
output wire lcd_spi_rst_n,
inout wire sdio_cmd,
inout wire sdio_clk,
inout wire [3:0] sdio_dat,
inout wire i2c_sda,
inout wire i2c_scl,
input wire i2c_irq_n,
output wire sensor_bias_boost_pwr_ena,
output wire sensor_core_pwr_ena,
output wire sensor_bias_pwr_ena,
output wire sensor_io_pwr_ena_n,
output wire sensor_bias_volt_sel,
output wire shtr_drive_ena,
output wire focus_drive_ena,
input wire focus_sensor_pulse,
input wire gpio_aux_spi_sck,
input wire gpio_aux_spi_cs_0,
input wire gpio_aux_spi_cs_1,
input wire gpio_aux_spi_miso,
input wire gpio_aux_spi_mosi,
input wire gpio_aux_i2c_sda,
input wire gpio_aux_i2c_scl,
inout wire ext_gpio_0_buf,
output wire ext_gpio_0_dir,
output wire ext_gpio_0_oc,
inout wire ext_gpio_1_buf,
output wire ext_gpio_1_dir,
output wire ext_gpio_1_oc,
input wire ext_gpi_buf,
output wire pwr_fd_clk,
output wire pwr_fd_dat,
input wire [3:0] btn
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam GPIO_DIR_INPUT = 1'b1,
GPIO_DIR_OUTPUT = 1'b0;
OBUFDS TMDS0 (.I(1'b0), .O(tmds_d0_p), .OB(tmds_d0_n));
OBUFDS TMDS1 (.I(1'b0), .O(tmds_d1_p), .OB(tmds_d1_n));
OBUFDS TMDS2 (.I(1'b0), .O(tmds_d2_p), .OB(tmds_d2_n));
OBUFDS TMDS3 (.I(1'b0), .O(tmds_clk_p), .OB(tmds_clk_n));
assign fx2_ifclk = 1'bz;
assign av_clkin = 1'bz;
assign av_clkin = 1'bz;
assign ext_gpio_0_buf = 1'bz;
assign ext_gpio_0_dir = GPIO_DIR_OUTPUT;
assign ext_gpio_0_oc = 1'b1;
assign ext_gpio_1_buf = 1'bz;
assign ext_gpio_1_dir = GPIO_DIR_OUTPUT;
assign ext_gpio_1_oc = 1'b1;
assign gpio_sensor = {20{1'bz}};
assign sensor_bias_boost_pwr_ena = 1'b0;
assign sensor_core_pwr_ena = 1'b0;
assign sensor_bias_pwr_ena = 1'b0;
assign sensor_io_pwr_ena_n = 1'b1;
assign sensor_bias_volt_sel = 1'b0;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire IIC_scl_i;
wire IIC_scl_o;
wire IIC_scl_t;
wire IIC_sda_i;
wire IIC_sda_o;
wire IIC_sda_t;
IOBUF IIC_scl_iobuf
(
.I (IIC_scl_o),
.IO (i2c_scl),
.O (IIC_scl_i),
.T (IIC_scl_t)
);
IOBUF IIC_sda_iobuf
(
.I (IIC_sda_o),
.IO (i2c_sda),
.O (IIC_sda_i),
.T (IIC_sda_t)
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire SPI_io0_i;
wire SPI_io0_o;
wire SPI_io0_t;
wire SPI_io1_i;
wire SPI_io1_o;
wire SPI_io1_t;
wire SPI_sck_i;
wire SPI_sck_o;
wire SPI_sck_t;
wire SPI_ss_i_0;
wire SPI_ss_o_0;
wire SPI_ss_t;
IOBUF SPI_io0_iobuf
(
.I (SPI_io0_o),
.IO (sdio_cmd),
.O (SPI_io0_i),
.T (SPI_io0_t)
);
IOBUF SPI_io1_iobuf
(
.I (SPI_io1_o),
.IO (sdio_dat[0]),
.O (SPI_io1_i),
.T (SPI_io1_t)
);
IOBUF SPI_sck_iobuf
(
.I (SPI_sck_o),
.IO (sdio_clk),
.O (SPI_sck_i),
.T (SPI_sck_t)
);
IOBUF SPI_ss_iobuf_0
(
.I (SPI_ss_o_0),
.IO (sdio_dat[3]),
.O (SPI_ss_i_0),
.T (SPI_ss_t)
);
assign sdio_dat[1] = 1'bz;
assign sdio_dat[2] = 1'bz;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire QSPI_ss_i;
wire QSPI_ss_o;
wire QSPI_ss_t;
wire QSPI_io0_i;
wire QSPI_io0_o;
wire QSPI_io0_t;
wire QSPI_io1_i;
wire QSPI_io1_o;
wire QSPI_io1_t;
wire QSPI_io2_i;
wire QSPI_io2_o;
wire QSPI_io2_t;
wire QSPI_io3_i;
wire QSPI_io3_o;
wire QSPI_io3_t;
IOBUF QSPI_ss_iobuf_0
(
.I (QSPI_ss_o),
.IO (cnfg_cs_n),
.O (QSPI_ss_i),
.T (QSPI_ss_t)
);
IOBUF QSPI_io0_iobuf
(
.I (QSPI_io0_o),
.IO (cnfg_mosi_miso_0),
.O (QSPI_io0_i),
.T (QSPI_io0_t)
);
IOBUF QSPI_io1_iobuf
(
.I (QSPI_io1_o),
.IO (cnfg_miso_miso_1),
.O (QSPI_io1_i),
.T (QSPI_io1_t)
);
IOBUF QSPI_io2_iobuf
(
.I (QSPI_io2_o),
.IO (cnfg_miso_2),
.O (QSPI_io2_i),
.T (QSPI_io2_t)
);
IOBUF QSPI_io3_iobuf
(
.I (QSPI_io3_o),
.IO (cnfg_miso_3),
.O (QSPI_io3_i),
.T (QSPI_io3_t)
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
SoC SoC_i
(
.extclk (extclk),
.fd_clk (pwr_fd_clk),
.fd_dat (pwr_fd_dat),
.shtr_drive_ena (shtr_drive_ena),
.focus_drive_ena (focus_drive_ena),
.act_led ({fx2_pa3_led_act_r, fx2_pa1_led_act_y}),
.btn_0 (btn[0]),
.btn_1 (btn[1]),
.btn_2 (btn[2]),
.btn_3 (btn[3]),
.lcd_led_ctrl (lcd_led_ctrl),
.lcd_resetn (lcd_spi_rst_n),
.lcd_spi_scl (lcd_spi_sck),
.lcd_spi_sda (lcd_spi_dat),
.i2c_exp_irq (~i2c_irq_n),
.IIC_scl_i (IIC_scl_i),
.IIC_scl_o (IIC_scl_o),
.IIC_scl_t (IIC_scl_t),
.IIC_sda_i (IIC_sda_i),
.IIC_sda_o (IIC_sda_o),
.IIC_sda_t (IIC_sda_t),
.SPI_io0_i (SPI_io0_i),
.SPI_io0_o (SPI_io0_o),
.SPI_io0_t (SPI_io0_t),
.SPI_io1_i (SPI_io1_i),
.SPI_io1_o (SPI_io1_o),
.SPI_io1_t (SPI_io1_t),
.SPI_sck_i (SPI_sck_i),
.SPI_sck_o (SPI_sck_o),
.SPI_sck_t (SPI_sck_t),
.SPI_ss_i (SPI_ss_i_0),
.SPI_ss_o (SPI_ss_o_0),
.SPI_ss_t (SPI_ss_t),
.QSPI_ss_i (QSPI_ss_i),
.QSPI_ss_o (QSPI_ss_o),
.QSPI_ss_t (QSPI_ss_t),
.QSPI_io0_i (QSPI_io0_i),
.QSPI_io0_o (QSPI_io0_o),
.QSPI_io0_t (QSPI_io0_t),
.QSPI_io1_i (QSPI_io1_i),
.QSPI_io1_o (QSPI_io1_o),
.QSPI_io1_t (QSPI_io1_t),
.QSPI_io2_i (QSPI_io2_i),
.QSPI_io2_o (QSPI_io2_o),
.QSPI_io2_t (QSPI_io2_t),
.QSPI_io3_i (QSPI_io3_i),
.QSPI_io3_o (QSPI_io3_o),
.QSPI_io3_t (QSPI_io3_t),
.HyperBus_R0_hb_ck_p (hram_r0_ck_p),
.HyperBus_R0_hb_ck_n (hram_r0_ck_n),
.HyperBus_R0_hb_cs_n (hram_r0_cs_n),
.HyperBus_R0_hb_dq (hram_r0_dq),
.HyperBus_R0_hb_reset_n (hram_r0_reset_n),
.HyperBus_R0_hb_rwds (hram_r0_rwds),
.HyperBus_R1_hb_ck_p (hram_r1_ck_p),
.HyperBus_R1_hb_ck_n (hram_r1_ck_n),
.HyperBus_R1_hb_cs_n (hram_r1_cs_n),
.HyperBus_R1_hb_dq (hram_r1_dq),
.HyperBus_R1_hb_reset_n (hram_r1_reset_n),
.HyperBus_R1_hb_rwds (hram_r1_rwds)
);
endmodule |
module vdma_ctrl #
(
parameter integer C_S_AXI_ADDR_WIDTH = 8
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire axi_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI_LITE:M_AXIS_CH0:M_AXIS_CH1:M_AXIS_CH2:M_AXIS_CH3:M_AXIS_CH4:M_AXIS_CH5:S_AXIS_MM2S:M_AXIS_MM2S_CMD:S_AXIS_MM2S_STS, ASSOCIATED_RESET axi_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire axi_aclk,
(* X_INTERFACE_PARAMETER = "MAX_BURST_LENGTH 1, SUPPORTS_NARROW_BURST 0, READ_WRITE_MODE READ_WRITE, BUSER_WIDTH 0, RUSER_WIDTH 0, WUSER_WIDTH 0, ARUSER_WIDTH 0, AWUSER_WIDTH 0, ADDR_WIDTH 8, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_awaddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *) input wire s_axi_awvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *) output reg s_axi_awready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *) input wire [31:0] s_axi_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WSTRB" *) input wire [3:0] s_axi_wstrb,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *) input wire s_axi_wvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *) output reg s_axi_wready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *) output reg [1:0] s_axi_bresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *) output reg s_axi_bvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *) input wire s_axi_bready,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *) input wire [C_S_AXI_ADDR_WIDTH - 1:0] s_axi_araddr,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *) input wire s_axi_arvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *) output reg s_axi_arready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *) output reg [31:0] s_axi_rdata = {32{1'b0}},
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *) output reg [1:0] s_axi_rresp = 2'b00,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *) output reg s_axi_rvalid = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *) input wire s_axi_rready,
/* Master AXIS OSD (On Screen Display) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH0, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH0 TDATA" *) output wire [31:0] m_axis_ch0_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH0 TVALID" *) output wire m_axis_ch0_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH0 TREADY" *) input wire m_axis_ch0_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH0 TUSER" *) output wire [3:0] m_axis_ch0_tuser,
/* Master AXIS to consumer 0 */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH1, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH1 TDATA" *) output wire [31:0] m_axis_ch1_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH1 TVALID" *) output wire m_axis_ch1_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH1 TREADY" *) input wire m_axis_ch1_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH1 TUSER" *) output wire [3:0] m_axis_ch1_tuser,
/* Master AXIS to consumer 1 */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH2, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH2 TDATA" *) output wire [31:0] m_axis_ch2_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH2 TVALID" *) output wire m_axis_ch2_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH2 TREADY" *) input wire m_axis_ch2_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH2 TUSER" *) output wire [3:0] m_axis_ch2_tuser,
/* Master AXIS to consumer 2 */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH3, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH3 TDATA" *) output wire [31:0] m_axis_ch3_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH3 TVALID" *) output wire m_axis_ch3_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH3 TREADY" *) input wire m_axis_ch3_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH3 TUSER" *) output wire [3:0] m_axis_ch3_tuser,
/* Master AXIS to consumer 3 */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH4, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH4 TDATA" *) output wire [31:0] m_axis_ch4_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH4 TVALID" *) output wire m_axis_ch4_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH4 TREADY" *) input wire m_axis_ch4_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH4 TUSER" *) output wire [3:0] m_axis_ch4_tuser,
/* Master AXIS to consumer 4 */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_CH5, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH5 TDATA" *) output wire [31:0] m_axis_ch5_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH5 TVALID" *) output wire m_axis_ch5_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH5 TREADY" *) input wire m_axis_ch5_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_CH5 TUSER" *) output wire [3:0] m_axis_ch5_tuser,
/* DataMover MM2S (read from memory) */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TDATA" *) input wire [31:0] s_axis_mm2s_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TKEEP" *) input wire [3:0] s_axis_mm2s_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TVALID" *) input wire s_axis_mm2s_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TREADY" *) output wire s_axis_mm2s_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S TLAST" *) input wire s_axis_mm2s_tlast,
/* DataMover MM2S command interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_MM2S_CMD, TDATA_NUM_BYTES 9, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TDATA" *) output reg [71:0] m_axis_mm2s_cmd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TVALID" *) output reg m_axis_mm2s_cmd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_MM2S_CMD TREADY" *) input wire m_axis_mm2s_cmd_tready,
/* DataMover MM2S status interface */
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_MM2S_STS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TDATA" *) input wire [7:0] s_axis_mm2s_sts_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TKEEP" *) input wire [0:0] s_axis_mm2s_sts_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TVALID" *) input wire s_axis_mm2s_sts_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TREADY" *) output reg s_axis_mm2s_sts_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_MM2S_STS TLAST" *) input wire s_axis_mm2s_sts_tlast,
input wire fifo_ch0_prog_full,
input wire fifo_ch1_prog_full,
input wire fifo_ch2_prog_full,
input wire fifo_ch3_prog_full,
input wire fifo_ch4_prog_full,
input wire fifo_ch5_prog_full
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam AXI_RESP_OKAY = 2'b00,
AXI_RESP_EXOKAY = 2'b01,
AXI_RESP_SLVERR = 2'b10,
AXI_RESP_DECERR = 2'b11;
integer i;
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_awaddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [C_S_AXI_ADDR_WIDTH - 1:0] axi_araddr = {C_S_AXI_ADDR_WIDTH{1'b0}};
reg [31:0] ctrl_reg = {32{1'b0}};
wire [31:0] stat_reg;
reg [31:0] ch0_config = {32{1'b0}};
reg [31:0] ch1_config = {32{1'b0}};
reg [31:0] ch2_config = {32{1'b0}};
reg [31:0] ch3_config = {32{1'b0}};
reg [31:0] ch4_config = {32{1'b0}};
reg [31:0] ch5_config = {32{1'b0}};
reg [31:0] ch0_ping_buf_addr = {32{1'b0}};
reg [31:0] ch1_ping_buf_addr = {32{1'b0}};
reg [31:0] ch2_ping_buf_addr = {32{1'b0}};
reg [31:0] ch3_ping_buf_addr = {32{1'b0}};
reg [31:0] ch4_ping_buf_addr = {32{1'b0}};
reg [31:0] ch5_ping_buf_addr = {32{1'b0}};
reg [31:0] ch0_pong_buf_addr = {32{1'b0}};
reg [31:0] ch1_pong_buf_addr = {32{1'b0}};
reg [31:0] ch2_pong_buf_addr = {32{1'b0}};
reg [31:0] ch3_pong_buf_addr = {32{1'b0}};
reg [31:0] ch4_pong_buf_addr = {32{1'b0}};
reg [31:0] ch5_pong_buf_addr = {32{1'b0}};
reg [31:0] ch0_buf_size = {32{1'b0}};
reg [31:0] ch1_buf_size = {32{1'b0}};
reg [31:0] ch2_buf_size = {32{1'b0}};
reg [31:0] ch3_buf_size = {32{1'b0}};
reg [31:0] ch4_buf_size = {32{1'b0}};
reg [31:0] ch5_buf_size = {32{1'b0}};
reg [31:0] ch0_addr_incr = {32{1'b0}};
reg [31:0] ch1_addr_incr = {32{1'b0}};
reg [31:0] ch2_addr_incr = {32{1'b0}};
reg [31:0] ch3_addr_incr = {32{1'b0}};
reg [31:0] ch4_addr_incr = {32{1'b0}};
reg [31:0] ch5_addr_incr = {32{1'b0}};
reg [31:0] ch0_btt = {32{1'b0}};
reg [31:0] ch1_btt = {32{1'b0}};
reg [31:0] ch2_btt = {32{1'b0}};
reg [31:0] ch3_btt = {32{1'b0}};
reg [31:0] ch4_btt = {32{1'b0}};
reg [31:0] ch5_btt = {32{1'b0}};
always @(posedge axi_aclk) begin
if (~axi_aresetn) begin
s_axi_awready <= 1'b0;
s_axi_wready <= 1'b0;
s_axi_bvalid <= 1'b0;
s_axi_bresp <= AXI_RESP_OKAY;
s_axi_arready <= 1'b0;
s_axi_rvalid <= 1'b0;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
/* Write address handshake */
s_axi_awready <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? 1'b1 : 1'b0;
/* Write address capture */
axi_awaddr <= (~s_axi_awready & s_axi_awvalid & s_axi_wvalid)? s_axi_awaddr : axi_awaddr;
/* Write data handshake */
s_axi_wready <= (~s_axi_wready & s_axi_wvalid & s_axi_awvalid)? 1'b1 : 1'b0;
/* Write data */
if (s_axi_wready & s_axi_wvalid & s_axi_awready & s_axi_awvalid) begin
for (i = 0; i < 4; i = i + 1) begin
case (axi_awaddr[7:2])
6'd0: ctrl_reg[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ctrl_reg[i*8 +: 8];
/* 6'd1: read only register */
6'd2 : ch0_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_config[i*8 +: 8];
6'd3 : ch1_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_config[i*8 +: 8];
6'd4 : ch2_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_config[i*8 +: 8];
6'd5 : ch3_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_config[i*8 +: 8];
6'd6 : ch4_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_config[i*8 +: 8];
6'd7 : ch5_config[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_config[i*8 +: 8];
6'd8 : ch0_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_ping_buf_addr[i*8 +: 8];
6'd9 : ch1_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_ping_buf_addr[i*8 +: 8];
6'd10: ch2_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_ping_buf_addr[i*8 +: 8];
6'd11: ch3_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_ping_buf_addr[i*8 +: 8];
6'd12: ch4_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_ping_buf_addr[i*8 +: 8];
6'd13: ch5_ping_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_ping_buf_addr[i*8 +: 8];
6'd14: ch0_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_pong_buf_addr[i*8 +: 8];
6'd15: ch1_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_pong_buf_addr[i*8 +: 8];
6'd16: ch2_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_pong_buf_addr[i*8 +: 8];
6'd17: ch3_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_pong_buf_addr[i*8 +: 8];
6'd18: ch4_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_pong_buf_addr[i*8 +: 8];
6'd19: ch5_pong_buf_addr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_pong_buf_addr[i*8 +: 8];
6'd20: ch0_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_buf_size[i*8 +: 8];
6'd21: ch1_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_buf_size[i*8 +: 8];
6'd22: ch2_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_buf_size[i*8 +: 8];
6'd23: ch3_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_buf_size[i*8 +: 8];
6'd24: ch4_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_buf_size[i*8 +: 8];
6'd25: ch5_buf_size[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_buf_size[i*8 +: 8];
6'd26: ch0_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_addr_incr[i*8 +: 8];
6'd27: ch1_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_addr_incr[i*8 +: 8];
6'd28: ch2_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_addr_incr[i*8 +: 8];
6'd29: ch3_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_addr_incr[i*8 +: 8];
6'd30: ch4_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_addr_incr[i*8 +: 8];
6'd31: ch5_addr_incr[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_addr_incr[i*8 +: 8];
6'd32: ch0_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch0_btt[i*8 +: 8];
6'd33: ch1_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch1_btt[i*8 +: 8];
6'd34: ch2_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch2_btt[i*8 +: 8];
6'd35: ch3_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch3_btt[i*8 +: 8];
6'd36: ch4_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch4_btt[i*8 +: 8];
6'd37: ch5_btt[i*8 +: 8] <= s_axi_wstrb[i]? s_axi_wdata[i*8 +: 8] : ch5_btt[i*8 +: 8];
default: begin
/* TODO: do nothing? */
end
endcase
end
end
/* Write response */
if (~s_axi_bvalid & s_axi_awready & s_axi_awvalid & s_axi_wready & s_axi_wvalid) begin
s_axi_bvalid <= 1'b1;
s_axi_bresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_bvalid & s_axi_bready) begin
s_axi_bvalid <= 1'b0;
end
end
/* Read address handshake */
s_axi_arready <= (~s_axi_arready & s_axi_arvalid)? 1'b1 : 1'b0;
/* Read address capture */
axi_araddr <= (~s_axi_arready & s_axi_arvalid)? s_axi_araddr : axi_araddr;
/* Read data handshake and response */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
s_axi_rvalid <= 1'b1;
s_axi_rresp <= AXI_RESP_OKAY;
end else begin
if (s_axi_rvalid & s_axi_rready) begin
s_axi_rvalid <= 1'b0;
end
end
/* Read data */
if (~s_axi_rvalid & s_axi_arready & s_axi_arvalid) begin
case (axi_araddr[7:2])
6'd0 : s_axi_rdata <= ctrl_reg;
6'd1 : s_axi_rdata <= stat_reg;
6'd2 : s_axi_rdata <= ch0_config;
6'd3 : s_axi_rdata <= ch1_config;
6'd4 : s_axi_rdata <= ch2_config;
6'd5 : s_axi_rdata <= ch3_config;
6'd6 : s_axi_rdata <= ch4_config;
6'd7 : s_axi_rdata <= ch5_config;
6'd8 : s_axi_rdata <= ch0_ping_buf_addr;
6'd9 : s_axi_rdata <= ch1_ping_buf_addr;
6'd10: s_axi_rdata <= ch2_ping_buf_addr;
6'd11: s_axi_rdata <= ch3_ping_buf_addr;
6'd12: s_axi_rdata <= ch4_ping_buf_addr;
6'd13: s_axi_rdata <= ch5_ping_buf_addr;
6'd14: s_axi_rdata <= ch0_pong_buf_addr;
6'd15: s_axi_rdata <= ch1_pong_buf_addr;
6'd16: s_axi_rdata <= ch2_pong_buf_addr;
6'd17: s_axi_rdata <= ch3_pong_buf_addr;
6'd18: s_axi_rdata <= ch4_pong_buf_addr;
6'd19: s_axi_rdata <= ch5_pong_buf_addr;
6'd20: s_axi_rdata <= ch0_buf_size;
6'd21: s_axi_rdata <= ch1_buf_size;
6'd22: s_axi_rdata <= ch2_buf_size;
6'd23: s_axi_rdata <= ch3_buf_size;
6'd24: s_axi_rdata <= ch4_buf_size;
6'd25: s_axi_rdata <= ch5_buf_size;
6'd26: s_axi_rdata <= ch0_addr_incr;
6'd27: s_axi_rdata <= ch1_addr_incr;
6'd28: s_axi_rdata <= ch2_addr_incr;
6'd29: s_axi_rdata <= ch3_addr_incr;
6'd30: s_axi_rdata <= ch4_addr_incr;
6'd31: s_axi_rdata <= ch5_addr_incr;
6'd32: s_axi_rdata <= ch0_btt;
6'd33: s_axi_rdata <= ch1_btt;
6'd34: s_axi_rdata <= ch2_btt;
6'd35: s_axi_rdata <= ch3_btt;
6'd36: s_axi_rdata <= ch4_btt;
6'd37: s_axi_rdata <= ch5_btt;
default: s_axi_rdata <= 32'hABADC0DE;
endcase
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [3:0] DMA_XFER_OKAY = 4'b1000,
DMA_XFER_SLVERR = 4'b0100,
DMA_XFER_DECERR = 4'b0010,
DMA_XFER_INTERR = 4'b0001;
localparam [2:0] CH0_FIFO_ID = 3'd0,
CH1_FIFO_ID = 3'd1,
CH2_FIFO_ID = 3'd2,
CH3_FIFO_ID = 3'd3,
CH4_FIFO_ID = 3'd4,
CH5_FIFO_ID = 3'd5;
reg mm2s_xfer_last = 1'b0;
reg mm2s_xfer_ena = 1'b0;
reg [2:0] slave_select = 3'b000;
wire frame_last_pix = mm2s_xfer_last & s_axis_mm2s_tlast;
assign m_axis_ch0_tdata = s_axis_mm2s_tdata;
assign m_axis_ch0_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH0_FIFO_ID);
assign m_axis_ch0_tuser = {ch0_config[0]? frame_last_pix : 1'b0,
ch0_config[1]? frame_last_pix : 1'b0,
ch0_config[2]? frame_last_pix : 1'b0,
ch0_config[3]? frame_last_pix : 1'b0};
assign m_axis_ch1_tdata = s_axis_mm2s_tdata;
assign m_axis_ch1_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH1_FIFO_ID);
assign m_axis_ch1_tuser = {ch1_config[0]? frame_last_pix : 1'b0,
ch1_config[1]? frame_last_pix : 1'b0,
ch1_config[2]? frame_last_pix : 1'b0,
ch1_config[3]? frame_last_pix : 1'b0};
assign m_axis_ch2_tdata = s_axis_mm2s_tdata;
assign m_axis_ch2_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH2_FIFO_ID);
assign m_axis_ch2_tuser = {ch2_config[0]? frame_last_pix : 1'b0,
ch2_config[1]? frame_last_pix : 1'b0,
ch2_config[2]? frame_last_pix : 1'b0,
ch2_config[3]? frame_last_pix : 1'b0};
assign m_axis_ch3_tdata = s_axis_mm2s_tdata;
assign m_axis_ch3_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH3_FIFO_ID);
assign m_axis_ch3_tuser = {ch3_config[0]? frame_last_pix : 1'b0,
ch3_config[1]? frame_last_pix : 1'b0,
ch3_config[2]? frame_last_pix : 1'b0,
ch3_config[3]? frame_last_pix : 1'b0};
assign m_axis_ch4_tdata = s_axis_mm2s_tdata;
assign m_axis_ch4_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH4_FIFO_ID);
assign m_axis_ch4_tuser = {ch4_config[0]? frame_last_pix : 1'b0,
ch4_config[1]? frame_last_pix : 1'b0,
ch4_config[2]? frame_last_pix : 1'b0,
ch4_config[3]? frame_last_pix : 1'b0};
assign m_axis_ch5_tdata = s_axis_mm2s_tdata;
assign m_axis_ch5_tvalid = s_axis_mm2s_tvalid & mm2s_xfer_ena & (slave_select == CH5_FIFO_ID);
assign m_axis_ch5_tuser = {ch5_config[0]? frame_last_pix : 1'b0,
ch5_config[1]? frame_last_pix : 1'b0,
ch5_config[2]? frame_last_pix : 1'b0,
ch5_config[3]? frame_last_pix : 1'b0};
reg slave_axis_tready = 1'b0;
always @(*) begin
(* parallel_case *)
case (slave_select)
CH0_FIFO_ID: slave_axis_tready = m_axis_ch0_tready;
CH1_FIFO_ID: slave_axis_tready = m_axis_ch1_tready;
CH2_FIFO_ID: slave_axis_tready = m_axis_ch2_tready;
CH3_FIFO_ID: slave_axis_tready = m_axis_ch3_tready;
CH4_FIFO_ID: slave_axis_tready = m_axis_ch4_tready;
CH5_FIFO_ID: slave_axis_tready = m_axis_ch5_tready;
default: slave_axis_tready = 1'b0;
endcase
end
assign s_axis_mm2s_tready = slave_axis_tready & mm2s_xfer_ena;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* Main data streaming module. Current FSM manages
* data movement by AXI-DataMover IP-core */
localparam [3:0] ST_ERROR = 4'd0,
ST_RESET = 4'd1,
ST_HANDLE_CH0 = 4'd2,
ST_HANDLE_CH1 = 4'd3,
ST_HANDLE_CH2 = 4'd4,
ST_HANDLE_CH3 = 4'd5,
ST_HANDLE_CH4 = 4'd6,
ST_HANDLE_CH5 = 4'd7,
ST_DATMOV_MM2S_CMD_0 = 4'd8,
ST_DATMOV_MM2S_CMD_1 = 4'd9,
ST_DATMOV_MM2S_XFER = 4'd10,
ST_GET_MM2S_XFER_STAT = 4'd11;
reg [3:0] state = ST_RESET;
reg [3:0] state_next = ST_RESET;
reg [31:0] ch0_frame_ptr = {32{1'b0}};
reg [31:0] ch1_frame_ptr = {32{1'b0}};
reg [31:0] ch2_frame_ptr = {32{1'b0}};
reg [31:0] ch3_frame_ptr = {32{1'b0}};
reg [31:0] ch4_frame_ptr = {32{1'b0}};
reg [31:0] ch5_frame_ptr = {32{1'b0}};
reg [31:0] ch0_xfer_cnt = {32{1'b0}};
reg [31:0] ch1_xfer_cnt = {32{1'b0}};
reg [31:0] ch2_xfer_cnt = {32{1'b0}};
reg [31:0] ch3_xfer_cnt = {32{1'b0}};
reg [31:0] ch4_xfer_cnt = {32{1'b0}};
reg [31:0] ch5_xfer_cnt = {32{1'b0}};
reg [31:0] byte_offset;
reg [22:0] btt_cnt;
wire [71:0] datmov_cmd = {
4'b0000, // RSVD
4'b0000, // TAG (Command TAG)
byte_offset, // Memory address byte offset
1'b0, // DRR (DRE ReAlignment Request)
1'b1, // EOF (End of Frame)
6'b000000, // DSA (DRE Stream Alignment)
1'b1, // Access type (0 - fix, 1 - inc)
btt_cnt // Bytes to transfer count
};
always @(posedge axi_aclk) begin
if (~axi_aresetn | ~ctrl_reg[31]) begin
mm2s_xfer_last <= 1'b0;
mm2s_xfer_ena <= 1'b0;
state <= ST_RESET;
end else begin
case (state)
/* Unrecoverable error */
ST_ERROR: begin
state <= state;
end
ST_RESET: begin
mm2s_xfer_last <= 1'b0;
mm2s_xfer_ena <= 1'b0;
ch0_xfer_cnt = ch0_btt;
ch1_xfer_cnt = ch1_btt;
ch2_xfer_cnt = ch2_btt;
ch3_xfer_cnt = ch3_btt;
ch4_xfer_cnt = ch4_btt;
ch5_xfer_cnt = ch5_btt;
ch0_frame_ptr <= ch0_ping_buf_addr;
ch1_frame_ptr <= ch1_ping_buf_addr;
ch2_frame_ptr <= ch2_ping_buf_addr;
ch3_frame_ptr <= ch3_ping_buf_addr;
ch4_frame_ptr <= ch4_ping_buf_addr;
ch5_frame_ptr <= ch5_ping_buf_addr;
state <= ST_HANDLE_CH0;
end
/* Handle CH0 */
ST_HANDLE_CH0: begin
if (~fifo_ch0_prog_full) begin
slave_select <= CH0_FIFO_ID;
byte_offset <= ch0_frame_ptr;
if (ch0_xfer_cnt >= ch0_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch0_xfer_cnt <= ch0_btt;
ch0_frame_ptr <= ch0_config[31]? ch0_pong_buf_addr : ch0_ping_buf_addr;
end else begin
ch0_frame_ptr <= ch0_frame_ptr + ch0_addr_incr;
ch0_xfer_cnt <= ch0_xfer_cnt + ch0_btt;
end
btt_cnt <= ch0_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH1;
end else begin
state <= ST_HANDLE_CH1;
end
end
/* Handle CH1 */
ST_HANDLE_CH1: begin
if (~fifo_ch1_prog_full) begin
slave_select <= CH1_FIFO_ID;
byte_offset <= ch1_frame_ptr;
if (ch1_xfer_cnt >= ch1_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch1_xfer_cnt <= ch1_btt;
ch1_frame_ptr <= ch1_config[31]? ch1_pong_buf_addr : ch1_ping_buf_addr;
end else begin
ch1_frame_ptr <= ch1_frame_ptr + ch1_addr_incr;
ch1_xfer_cnt <= ch1_xfer_cnt + ch1_btt;
end
btt_cnt <= ch1_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH2;
end else begin
state <= ST_HANDLE_CH2;
end
end
/* Handle CH2 */
ST_HANDLE_CH2: begin
if (~fifo_ch2_prog_full) begin
slave_select <= CH2_FIFO_ID;
byte_offset <= ch2_frame_ptr;
if (ch2_xfer_cnt >= ch2_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch2_xfer_cnt <= ch2_btt;
ch2_frame_ptr <= ch2_config[31]? ch2_pong_buf_addr : ch2_ping_buf_addr;
end else begin
ch2_frame_ptr <= ch2_frame_ptr + ch2_addr_incr;
ch2_xfer_cnt <= ch2_xfer_cnt + ch2_btt;
end
btt_cnt <= ch2_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH3;
end else begin
state <= ST_HANDLE_CH3;
end
end
/* Handle CH3 */
ST_HANDLE_CH3: begin
if (~fifo_ch3_prog_full) begin
slave_select <= CH3_FIFO_ID;
byte_offset <= ch3_frame_ptr;
if (ch3_xfer_cnt >= ch3_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch3_xfer_cnt <= ch3_btt;
ch3_frame_ptr <= ch3_config[31]? ch3_pong_buf_addr : ch3_ping_buf_addr;
end else begin
ch3_frame_ptr <= ch3_frame_ptr + ch3_addr_incr;
ch3_xfer_cnt <= ch3_xfer_cnt + ch3_btt;
end
btt_cnt <= ch3_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH4;
end else begin
state <= ST_HANDLE_CH4;
end
end
/* Handle CH4 */
ST_HANDLE_CH4: begin
if (~fifo_ch4_prog_full) begin
slave_select <= CH4_FIFO_ID;
byte_offset <= ch4_frame_ptr;
if (ch4_xfer_cnt >= ch4_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch4_xfer_cnt <= ch4_btt;
ch4_frame_ptr <= ch4_config[31]? ch4_pong_buf_addr : ch4_ping_buf_addr;
end else begin
ch4_frame_ptr <= ch4_frame_ptr + ch4_addr_incr;
ch4_xfer_cnt <= ch4_xfer_cnt + ch4_btt;
end
btt_cnt <= ch4_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH5;
end else begin
state <= ST_HANDLE_CH5;
end
end
/* Handle CH5 */
ST_HANDLE_CH5: begin
if (~fifo_ch5_prog_full) begin
slave_select <= CH5_FIFO_ID;
byte_offset <= ch5_frame_ptr;
if (ch5_xfer_cnt >= ch5_buf_size) begin
mm2s_xfer_last <= 1'b1;
ch5_xfer_cnt <= ch5_btt;
ch5_frame_ptr <= ch5_config[31]? ch5_pong_buf_addr : ch5_ping_buf_addr;
end else begin
ch5_frame_ptr <= ch5_frame_ptr + ch5_addr_incr;
ch5_xfer_cnt <= ch5_xfer_cnt + ch5_btt;
end
btt_cnt <= ch5_btt;
state <= ST_DATMOV_MM2S_CMD_0;
state_next <= ST_HANDLE_CH0;
end else begin
state <= ST_HANDLE_CH0;
end
end
/* Generate MM2S command for DataMover */
ST_DATMOV_MM2S_CMD_0: begin
m_axis_mm2s_cmd_tdata <= datmov_cmd;
m_axis_mm2s_cmd_tvalid <= 1'b1;
state <= ST_DATMOV_MM2S_CMD_1;
end
/* Wait MM2S command to be accepted */
ST_DATMOV_MM2S_CMD_1: begin
if (m_axis_mm2s_cmd_tready) begin
m_axis_mm2s_cmd_tvalid <= 1'b0;
mm2s_xfer_ena <= 1'b1;
state <= ST_DATMOV_MM2S_XFER;
end
end
/* Wait MM2S transfer to be done */
ST_DATMOV_MM2S_XFER: begin
if (s_axis_mm2s_tvalid & s_axis_mm2s_tready & s_axis_mm2s_tlast) begin
mm2s_xfer_last <= 1'b0;
mm2s_xfer_ena <= 1'b0;
s_axis_mm2s_sts_tready <= 1'b1;
state <= ST_GET_MM2S_XFER_STAT;
end
end
/* Check MM2S transfer status */
ST_GET_MM2S_XFER_STAT: begin
if (s_axis_mm2s_sts_tvalid) begin
s_axis_mm2s_sts_tready <= 1'b0;
if (s_axis_mm2s_sts_tdata[7:4] == DMA_XFER_OKAY) begin
state <= state_next;
end else begin
state <= ST_ERROR;
end
end
end
default: begin
state <= ST_ERROR;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign stat_reg = {
4'b0000, state,
{24{1'b0}}
};
endmodule |
module lcd_ctrl #
(
parameter integer LCD_CLK_HZ = 0,
parameter [15:0] TRANSPARENT_PIX_COLOR = 16'hFFFF
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS_IMG:S_AXIS_OSD, ASSOCIATED_RESET s_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_IMG, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TDATA" *) input wire [15:0] s_axis_img_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TVALID" *) input wire s_axis_img_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TREADY" *) output reg s_axis_img_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_IMG TUSER" *) input wire s_axis_img_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_OSD, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 2, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OSD TDATA" *) input wire [15:0] s_axis_osd_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OSD TVALID" *) input wire s_axis_osd_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OSD TREADY" *) output reg s_axis_osd_tready = 1'b0,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OSD TUSER" *) input wire [1:0] s_axis_osd_tuser,
output wire lcd_spi_scl,
output wire lcd_spi_sda,
output reg lcd_resetn = 1'b0
);
/*----------------------------------------------------------------------------------*/
localparam LCD_INIT_ROM_CMD_ADDR = 6'h00;
localparam LCD_INIT_ROM_CMD_SIZE = 8'd56;
localparam NEW_FRAME_ROM_CMD_ADDR = 6'h38;
localparam NEW_FRAME_ROM_CMD_SIZE = 8'd11;
localparam LCD_REG_ADDR = 2'b00,
LCD_DAT_BYTE = 2'b01,
LCD_CMD_DELAY = 2'b10,
LCD_CMD_RESET = 2'b11;
localparam CMD = 1'b0,
DATA = 1'b1;
localparam TIMER_MS_DELAY = LCD_CLK_HZ / 1000;
/*----------------------------------------------------------------------------------*/
reg oddr_cen = 1'b0;
reg [17:0] lcd_sda_reg = {18{1'b0}};
reg [4:0] bit_cnt = 5'd0;
reg last_pix = 1'b0;
reg [6:0] cmd_cnt = 7'd0;
reg [7:0] cmd_delay = 8'd0;
reg [6:0] cmd_rom_addr = 7'd0;
wire [9:0] cmd_rom_dq;
reg [31:0] timer_ms = {32{1'b0}};
reg timer_ms_hit = 1'b0;
wire img_eof = s_axis_img_tuser;
wire osd_eof = s_axis_osd_tuser[1];
/*----------------------------------------------------------------------------------*/
localparam [2:0] ST_WR_CMD_0 = 3'd0,
ST_WR_CMD_1 = 3'd1,
ST_WR_CMD_2 = 3'd2,
ST_WR_CMD_3 = 3'd3,
ST_WR_CMD_4 = 3'd4,
ST_WR_CMD_5 = 3'd5,
ST_WR_CMD_DONE = 3'd6,
FSM_WR_CMD_RESET_STATE = ST_WR_CMD_0;
reg [2:0] wr_cmd_state = FSM_WR_CMD_RESET_STATE;
wire wr_cmd_done = (wr_cmd_state == ST_WR_CMD_DONE);
task wr_cmd;
input [6:0] start_rom_addr;
input [7:0] cmd_size;
begin
case (wr_cmd_state)
ST_WR_CMD_0: begin
cmd_cnt <= 7'd1;
cmd_rom_addr <= start_rom_addr;
wr_cmd_state <= ST_WR_CMD_2;
end
ST_WR_CMD_1: begin
if (cmd_cnt != cmd_size) begin
cmd_cnt <= cmd_cnt + 1'b1;
cmd_rom_addr <= cmd_rom_addr + 1'b1;
wr_cmd_state <= ST_WR_CMD_2;
end else begin
wr_cmd_state <= ST_WR_CMD_DONE;
end
end
ST_WR_CMD_2: begin
/* ROM single cycle latency */
wr_cmd_state <= ST_WR_CMD_3;
end
ST_WR_CMD_3: begin
case (cmd_rom_dq[9:8])
LCD_REG_ADDR: begin
oddr_cen <= 1'b1;
bit_cnt <= 5'd0;
lcd_sda_reg <= {CMD, cmd_rom_dq[7:0], {9{1'b0}}};
wr_cmd_state <= ST_WR_CMD_4;
end
LCD_DAT_BYTE: begin
oddr_cen <= 1'b1;
bit_cnt <= 5'd0;
lcd_sda_reg <= {DATA, cmd_rom_dq[7:0], {9{1'b0}}};
wr_cmd_state <= ST_WR_CMD_4;
end
LCD_CMD_DELAY: begin
cmd_delay <= 8'd0;
wr_cmd_state <= ST_WR_CMD_5;
end
LCD_CMD_RESET: begin
lcd_resetn <= ~cmd_rom_dq[0];
wr_cmd_state <= ST_WR_CMD_1;
end
endcase
end
ST_WR_CMD_4: begin
if (bit_cnt != 5'd8) begin
bit_cnt <= bit_cnt + 1'b1;
lcd_sda_reg <= {lcd_sda_reg[16:0], lcd_sda_reg[17]};
end else begin
oddr_cen <= 1'b0;
wr_cmd_state <= ST_WR_CMD_1;
end
end
ST_WR_CMD_5: begin
if (cmd_delay != cmd_rom_dq[7:0]) begin
if (timer_ms_hit) begin
cmd_delay <= cmd_delay + 1'b1;
end
end else begin
wr_cmd_state <= ST_WR_CMD_1;
end
end
ST_WR_CMD_DONE: begin
wr_cmd_state <= FSM_WR_CMD_RESET_STATE;
end
default: begin
wr_cmd_state <= FSM_WR_CMD_RESET_STATE;
end
endcase
end
endtask
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [1:0] ST_FILL_SCREEN_0 = 2'd0,
ST_FILL_SCREEN_1 = 2'd1,
ST_FILL_SCREEN_2 = 2'd2,
ST_FILL_SCREEN_DONE = 2'd3,
FSM_FILL_SCREEN_RESET_STATE = ST_FILL_SCREEN_0;
reg [1:0] fill_screen_state = FSM_FILL_SCREEN_RESET_STATE;
wire fill_screen_done = (fill_screen_state == ST_FILL_SCREEN_DONE);
task fill_screen;
begin
case (fill_screen_state)
ST_FILL_SCREEN_0: begin
last_pix <= 1'b0;
s_axis_img_tready <= 1'b0;
s_axis_osd_tready <= 1'b0;
fill_screen_state <= ST_FILL_SCREEN_1;
end
ST_FILL_SCREEN_1: begin
if (~last_pix) begin
if (s_axis_img_tvalid & s_axis_osd_tvalid) begin
last_pix <= img_eof & osd_eof;
s_axis_img_tready <= 1'b1;
s_axis_osd_tready <= 1'b1;
oddr_cen <= 1'b1;
bit_cnt <= 5'd0;
lcd_sda_reg <= (s_axis_osd_tdata == TRANSPARENT_PIX_COLOR)? {DATA, s_axis_img_tdata[15:8], DATA, s_axis_img_tdata[7:0]} :
{DATA, s_axis_osd_tdata[15:8], DATA, s_axis_osd_tdata[7:0]};
fill_screen_state <= ST_FILL_SCREEN_2;
end else begin
oddr_cen <= 1'b0;
end
end else begin
oddr_cen <= 1'b0;
fill_screen_state <= ST_FILL_SCREEN_DONE;
end
end
ST_FILL_SCREEN_2: begin
s_axis_img_tready <= 1'b0;
s_axis_osd_tready <= 1'b0;
if (bit_cnt != 5'd16) begin
bit_cnt <= bit_cnt + 1'b1;
end else begin
fill_screen_state <= ST_FILL_SCREEN_1;
end
lcd_sda_reg <= {lcd_sda_reg[16:0], lcd_sda_reg[17]};
end
ST_FILL_SCREEN_DONE: begin
fill_screen_state <= FSM_FILL_SCREEN_RESET_STATE;
end
endcase
end
endtask
/*-------------------------------------------------------------------------------------------------------------------------------------*/
task local_rst;
begin
wr_cmd_state <= FSM_WR_CMD_RESET_STATE;
fill_screen_state <= FSM_FILL_SCREEN_RESET_STATE;
s_axis_img_tready <= 1'b0;
s_axis_osd_tready <= 1'b0;
oddr_cen <= 1'b0;
last_pix <= 1'b0;
lcd_resetn <= 1'b0;
end
endtask
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [2:0] ST_RESET = 3'd0,
ST_LCD_INIT = 3'd1,
ST_IMG_SYNC = 3'd2,
ST_OSD_SYNC = 3'd3,
ST_WAIT_VSYNC = 3'd4,
ST_SET_START_POS = 3'd5,
ST_FILL_SCREEN = 3'd6;
reg [2:0] state = ST_RESET;
always @(posedge s_axis_aclk) begin
if (~s_axis_aresetn) begin
local_rst();
state <= ST_RESET;
end else begin
case (state)
ST_RESET: begin
local_rst();
state <= ST_LCD_INIT;
end
ST_LCD_INIT: begin
wr_cmd(LCD_INIT_ROM_CMD_ADDR, LCD_INIT_ROM_CMD_SIZE);
state <= (wr_cmd_done)? ST_IMG_SYNC : state;
end
ST_IMG_SYNC: begin
if (s_axis_img_tvalid & s_axis_img_tready & img_eof) begin
s_axis_img_tready <= 1'b0;
state <= ST_OSD_SYNC;
end else begin
s_axis_img_tready <= 1'b1;
end
end
ST_OSD_SYNC: begin
if (s_axis_osd_tvalid & s_axis_osd_tready & osd_eof) begin
s_axis_osd_tready <= 1'b0;
state <= ST_WAIT_VSYNC;
end else begin
s_axis_osd_tready <= 1'b1;
end
end
ST_WAIT_VSYNC: begin
// Wait for tearing strobe here?
state <= ST_SET_START_POS;
end
ST_SET_START_POS: begin
wr_cmd(NEW_FRAME_ROM_CMD_ADDR, NEW_FRAME_ROM_CMD_SIZE);
state <= (wr_cmd_done)? ST_FILL_SCREEN : state;
end
ST_FILL_SCREEN: begin
fill_screen();
state <= (fill_screen_done)? ST_WAIT_VSYNC : state;
end
default: begin
state <= ST_RESET;
end
endcase
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
always @(posedge s_axis_aclk) begin
if (~s_axis_aresetn) begin
timer_ms <= {32{1'b0}};
end else begin
if (timer_ms == TIMER_MS_DELAY) begin
timer_ms <= {32{1'b0}};
timer_ms_hit <= 1'b1;
end else begin
timer_ms <= timer_ms + 1'b1;
timer_ms_hit <= 1'b0;
end
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
/* -----------------------------------------------------
* ROM 64 x 10 bit
* -----------------------------------------------------
* 1. LCD register address:
* cmd[9:8] = 2'h0
* cmd[7:0] = 8'hxx - LCD register address value
*
* 2. LCD data value:
* cmd[9:8] = 2'h1
* cmd[7:0] = 8'hxx - LCD register data value
*
* 3. DELAY command:
* cmd[9:8] = 2'h2
* cmd[7:0] = 8'hxx - delay value in ms
*
* 3. LCD reset pin command:
* cmd[9:8] = 2'h3
* cmd[7:0] = 8'bxxxx_xxx0 - release reset pin
* 8'bxxxx_xxx1 - assert reset pin
* -----------------------------------------------------
*/
rom128xN #
(
.OUTPUT_REG ( "TRUE" ),
.DATA_WIDTH ( 10 ),
.INIT_ROM_00 ( 10'h3_01 ), // assert LCD reset pin
.INIT_ROM_01 ( 10'h2_0A ), // delay 10ms
.INIT_ROM_02 ( 10'h3_00 ), // release LCD reset pin
.INIT_ROM_03 ( 10'h2_78 ), // delay 120ms
.INIT_ROM_04 ( 10'h0_c8 ), // EXTC
.INIT_ROM_05 ( 10'h1_FF ), //
.INIT_ROM_06 ( 10'h1_93 ), //
.INIT_ROM_07 ( 10'h1_42 ), //
.INIT_ROM_08 ( 10'h0_36 ), // Memory Access Control
.INIT_ROM_09 ( 10'h1_c8 ), //
.INIT_ROM_0A ( 10'h0_3A ), // Pixel Format Set
.INIT_ROM_0B ( 10'h1_55 ), //
.INIT_ROM_0C ( 10'h0_C0 ), // Power Control 1
.INIT_ROM_0D ( 10'h1_10 ), //
.INIT_ROM_0E ( 10'h1_10 ), //
.INIT_ROM_0F ( 10'h0_C1 ), // Power Control 2
.INIT_ROM_10 ( 10'h1_36 ), //
.INIT_ROM_11 ( 10'h0_C5 ), // VCOM Control 1
.INIT_ROM_12 ( 10'h1_C3 ), //
.INIT_ROM_13 ( 10'h0_E0 ), // Positive Gamma Correction
.INIT_ROM_14 ( 10'h1_00 ), //
.INIT_ROM_15 ( 10'h1_05 ), //
.INIT_ROM_16 ( 10'h1_08 ), //
.INIT_ROM_17 ( 10'h1_02 ), //
.INIT_ROM_18 ( 10'h1_1A ), //
.INIT_ROM_19 ( 10'h1_0C ), //
.INIT_ROM_1A ( 10'h1_42 ), //
.INIT_ROM_1B ( 10'h1_7A ), //
.INIT_ROM_1C ( 10'h1_54 ), //
.INIT_ROM_1D ( 10'h1_08 ), //
.INIT_ROM_1E ( 10'h1_0D ), //
.INIT_ROM_1F ( 10'h1_0C ), //
.INIT_ROM_20 ( 10'h1_23 ), //
.INIT_ROM_21 ( 10'h1_25 ), //
.INIT_ROM_22 ( 10'h1_0F ), //
.INIT_ROM_23 ( 10'h0_E1 ), // Negative Gamma Correction
.INIT_ROM_24 ( 10'h1_00 ), //
.INIT_ROM_25 ( 10'h1_29 ), //
.INIT_ROM_26 ( 10'h1_2F ), //
.INIT_ROM_27 ( 10'h1_03 ), //
.INIT_ROM_28 ( 10'h1_0F ), //
.INIT_ROM_29 ( 10'h1_05 ), //
.INIT_ROM_2A ( 10'h1_42 ), //
.INIT_ROM_2B ( 10'h1_55 ), //
.INIT_ROM_2C ( 10'h1_53 ), //
.INIT_ROM_2D ( 10'h1_06 ), //
.INIT_ROM_2E ( 10'h1_0F ), //
.INIT_ROM_2F ( 10'h1_0C ), //
.INIT_ROM_30 ( 10'h1_38 ), //
.INIT_ROM_31 ( 10'h1_3A ), //
.INIT_ROM_32 ( 10'h1_0F ), //
.INIT_ROM_33 ( 10'h0_35 ), // Tearing Effect Line ON
.INIT_ROM_34 ( 10'h1_00 ), //
.INIT_ROM_35 ( 10'h0_11 ), // Sleep Out
.INIT_ROM_36 ( 10'h2_78 ), // delay 120ms
.INIT_ROM_37 ( 10'h0_29 ), // Display ON
// Address_set(X1, Y1, X2, Y2) = (0, 0, 239, 319)
.INIT_ROM_38 ( 10'h0_2A ), // Column Address Set (Y1, Y2)
.INIT_ROM_39 ( 10'h1_00 ), //
.INIT_ROM_3A ( 10'h1_00 ), //
.INIT_ROM_3B ( 10'h1_01 ), //
.INIT_ROM_3C ( 10'h1_3F ), //
.INIT_ROM_3D ( 10'h0_2B ), // Page Address Set (X1, X2)
.INIT_ROM_3E ( 10'h1_00 ), //
.INIT_ROM_3F ( 10'h1_00 ), //
.INIT_ROM_40 ( 10'h1_00 ), //
.INIT_ROM_41 ( 10'h1_EF ), //
.INIT_ROM_42 ( 10'h0_2C ) // Memory Write
)
lcd_cmd_rom
(
.clk ( s_axis_aclk ),
.cen ( 1'b1 ),
.addr ( cmd_rom_addr ),
.dout ( cmd_rom_dq )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg oddr_cen_sync = 1'b0;
always @(negedge s_axis_aclk) begin
oddr_cen_sync <= oddr_cen;
end
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_clk
(
.Q ( lcd_spi_scl ), // 1-bit DDR output
.C ( s_axis_aclk ), // 1-bit clock input
.CE ( oddr_cen_sync ), // 1-bit clock enable input
.D1 ( oddr_cen_sync ), // 1-bit data input (positive edge)
.D2 ( 1'b0 ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
ODDR #
(
.DDR_CLK_EDGE ( "OPPOSITE_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT ( 1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ( "ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_dat
(
.Q ( lcd_spi_sda ), // 1-bit DDR output
.C ( s_axis_aclk ), // 1-bit clock input
.CE ( oddr_cen ), // 1-bit clock enable input
.D1 ( lcd_sda_reg[17] ), // 1-bit data input (positive edge)
.D2 ( lcd_sda_reg[17] ), // 1-bit data input (negative edge)
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
endmodule |
module edge_to_pulse #
(
parameter CLK_HZ = 27000000,
parameter PULSE_DURATION_MS = 1,
parameter EDGE_TYPE = "RISING" // RISING / FALLING / BOTH
)
(
input wire clk,
input wire rstn,
input wire edge_in,
output reg pulse_out = 1'b0
);
localparam DELAY_MS = CLK_HZ / 1000;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg in_1 = 1'b0;
reg state = 1'b0;
reg [31:0] delay_tc = 32'd0;
always @(posedge clk) begin
if (~rstn) begin
state <= 1'b0;
in_1 <= 1'b0;
pulse_out <= 1'b0;
end else begin
in_1 <= edge_in;
case (state)
1'b0: begin
delay_tc <= 32'd0;
if (EDGE_TYPE == "BOTH") begin
state <= (edge_in ^ in_1)? 1'b1 : 1'b0;
end else begin
if (EDGE_TYPE == "RISING") begin
state <= (edge_in & ~in_1)? 1'b1 : 1'b0;
end else begin
state <= (~edge_in & in_1)? 1'b1 : 1'b0;
end
end
end
1'b1: begin
if (delay_tc < PULSE_DURATION_MS * DELAY_MS) begin
delay_tc <= delay_tc + 1'b1;
pulse_out <= 1'b1;
end else begin
state <= 1'b0;
pulse_out <= 1'b0;
end
end
endcase
end
end
endmodule |
module s_axis_stub
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS_STUB, ASSOCIATED_RESET s_axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_STUB, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TDATA" *) input wire [31:0] s_axis_stub_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TVALID" *) input wire s_axis_stub_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TREADY" *) output wire s_axis_stub_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TLAST" *) input wire s_axis_stub_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_STUB TUSER" *) input wire [3:0] s_axis_stub_tuser
);
assign s_axis_stub_tready = 1'b0;
endmodule |
module debouncer #
(
parameter CLK_HZ = 0,
parameter DEBOUNCE_MS = 20,
parameter IDLE_STATE = 1'b1
)
(
input wire clk,
input wire rstn,
input wire noisy_in,
output reg filtered_out = IDLE_STATE
);
localparam DELAY_MS = CLK_HZ / 1000;
wire out_sync;
reg out_sync_1 = IDLE_STATE;
reg [31:0] delay_tc = 32'd0;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
xpm_cdc_single #
(
.DEST_SYNC_FF (3), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG (0) // DECIMAL; 0=do not register input, 1=register input
)
xpm_cdc_single_inst
(
.src_clk ( 1'b0 ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.dest_clk ( clk ), // 1-bit input: Clock signal for the destination clock domain.
.src_in ( noisy_in ), // 1-bit input: Input signal to be synchronized to dest_clk domain.
.dest_out ( out_sync ) // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
always @(posedge clk) begin
if (~rstn) begin
filtered_out <= IDLE_STATE;
out_sync_1 <= IDLE_STATE;
end else begin
out_sync_1 <= out_sync;
if (out_sync ^ out_sync_1) begin
delay_tc <= 32'd0;
end else begin
if (delay_tc == DEBOUNCE_MS * DELAY_MS) begin
filtered_out <= out_sync_1;
end else begin
delay_tc <= delay_tc + 1'b1;
end
end
end
end
endmodule |
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