module
stringlengths 21
82.9k
|
|---|
module des(desOut, desIn, key, decrypt, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key;
input decrypt;
input clk;
wire [1:64] IP, FP;
reg [63:0] desIn_r;
reg [55:0] key_r;
reg [63:0] desOut;
reg [1:32] L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
reg [1:32] R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
wire [1:32] out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
// Register the 56 bit key
always @(posedge clk)
key_r <= #1 key;
// Register the 64 bit input
always @(posedge clk)
desIn_r <= #1 desIn;
// XOR 32 bit out15 with 32 bit L14 ( FP 1:32 )
// then concatinate the 32 bit R14 value ( FP 33:64 )
// This value ( FP 1:64 ) is then registered by the desOut[63:0] register
assign FP = { (out15 ^ L14), R14};
// Key schedule provides a linear means of intermixing the 56 bit key to form a
// different 48 bit key for each of the 16 bit rounds
key_sel uk(
.clk( clk ),
.K( key_r ),
.decrypt( decrypt ),
.K1( K1 ),
.K2( K2 ),
.K3( K3 ),
.K4( K4 ),
.K5( K5 ),
.K6( K6 ),
.K7( K7 ),
.K8( K8 ),
.K9( K9 ),
.K10( K10 ),
.K11( K11 ),
.K12( K12 ),
.K13( K13 ),
.K14( K14 ),
.K15( K15 ),
.K16( K16 )
);
// 16 CRP blocks
crp u0( .P(out0), .R(IP[33:64]), .K_sub(K1) );
crp u1( .P(out1), .R(R0), .K_sub(K2) );
crp u2( .P(out2), .R(R1), .K_sub(K3) );
crp u3( .P(out3), .R(R2), .K_sub(K4) );
crp u4( .P(out4), .R(R3), .K_sub(K5) );
crp u5( .P(out5), .R(R4), .K_sub(K6) );
crp u6( .P(out6), .R(R5), .K_sub(K7) );
crp u7( .P(out7), .R(R6), .K_sub(K8) );
crp u8( .P(out8), .R(R7), .K_sub(K9) );
crp u9( .P(out9), .R(R8), .K_sub(K10) );
crp u10( .P(out10), .R(R9), .K_sub(K11) );
crp u11( .P(out11), .R(R10), .K_sub(K12) );
crp u12( .P(out12), .R(R11), .K_sub(K13) );
crp u13( .P(out13), .R(R12), .K_sub(K14) );
crp u14( .P(out14), .R(R13), .K_sub(K15) );
crp u15( .P(out15), .R(R14), .K_sub(K16) );
// 32 bit L0 get upper 32 bits of IP
always @(posedge clk)
L0 <= #1 IP[33:64];
// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0
always @(posedge clk)
R0 <= #1 IP[01:32] ^ out0;
// 32 bit L1 gets 32 bit R0
always @(posedge clk)
L1 <= #1 R0;
// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1
always @(posedge clk)
R1 <= #1 L0 ^ out1;
// 32 bit L2 gets 32 bit R1
always @(posedge clk)
L2 <= #1 R1;
// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2
always @(posedge clk)
R2 <= #1 L1 ^ out2;
always @(posedge clk)
L3 <= #1 R2;
always @(posedge clk)
R3 <= #1 L2 ^ out3;
always @(posedge clk)
L4 <= #1 R3;
always @(posedge clk)
R4 <= #1 L3 ^ out4;
always @(posedge clk)
L5 <= #1 R4;
always @(posedge clk)
R5 <= #1 L4 ^ out5;
always @(posedge clk)
L6 <= #1 R5;
always @(posedge clk)
R6 <= #1 L5 ^ out6;
always @(posedge clk)
L7 <= #1 R6;
always @(posedge clk)
R7 <= #1 L6 ^ out7;
always @(posedge clk)
L8 <= #1 R7;
always @(posedge clk)
R8 <= #1 L7 ^ out8;
always @(posedge clk)
L9 <= #1 R8;
always @(posedge clk)
R9 <= #1 L8 ^ out9;
always @(posedge clk)
L10 <= #1 R9;
always @(posedge clk)
R10 <= #1 L9 ^ out10;
always @(posedge clk)
L11 <= #1 R10;
always @(posedge clk)
R11 <= #1 L10 ^ out11;
always @(posedge clk)
L12 <= #1 R11;
always @(posedge clk)
R12 <= #1 L11 ^ out12;
always @(posedge clk)
L13 <= #1 R12;
always @(posedge clk)
R13 <= #1 L12 ^ out13;
always @(posedge clk)
L14 <= #1 R13;
always @(posedge clk)
R14 <= #1 L13 ^ out14;
// 32 bit L15 gets 32 bit R14
always @(posedge clk)
L15 <= #1 R14;
// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15
always @(posedge clk)
R15 <= #1 L14 ^ out15;
// Perform the initial permutationi with the registerd desIn
assign IP[1:64] = { desIn_r[06], desIn_r[14], desIn_r[22], desIn_r[30], desIn_r[38], desIn_r[46],
desIn_r[54], desIn_r[62], desIn_r[04], desIn_r[12], desIn_r[20], desIn_r[28],
desIn_r[36], desIn_r[44], desIn_r[52], desIn_r[60], desIn_r[02], desIn_r[10],
desIn_r[18], desIn_r[26], desIn_r[34], desIn_r[42], desIn_r[50], desIn_r[58],
desIn_r[00], desIn_r[08], desIn_r[16], desIn_r[24], desIn_r[32], desIn_r[40],
desIn_r[48], desIn_r[56], desIn_r[07], desIn_r[15], desIn_r[23], desIn_r[31],
desIn_r[39], desIn_r[47], desIn_r[55], desIn_r[63], desIn_r[05], desIn_r[13],
desIn_r[21], desIn_r[29], desIn_r[37], desIn_r[45], desIn_r[53], desIn_r[61],
desIn_r[03], desIn_r[11], desIn_r[19], desIn_r[27], desIn_r[35], desIn_r[43],
desIn_r[51], desIn_r[59], desIn_r[01], desIn_r[09], desIn_r[17], desIn_r[25],
desIn_r[33], desIn_r[41], desIn_r[49], desIn_r[57] };
// Perform the final permutation
always @(posedge clk)
desOut <= #1 { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule |
module key_sel(clk, K, decrypt, K1, K2, K3, K4, K5, K6, K7, K8, K9,
K10, K11, K12, K13, K14, K15, K16);
input clk;
input [55:0] K;
input decrypt;
output [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
output [1:48] K10, K11, K12, K13, K14, K15, K16;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
reg [55:0] K_r0, K_r1, K_r2, K_r3, K_r4, K_r5, K_r6, K_r7;
reg [55:0] K_r8, K_r9, K_r10, K_r11, K_r12, K_r13, K_r14;
always @(posedge clk)
begin
K_r0 <= #1 K;
K_r1 <= #1 K_r0;
K_r2 <= #1 K_r1;
K_r3 <= #1 K_r2;
K_r4 <= #1 K_r3;
K_r5 <= #1 K_r4;
K_r6 <= #1 K_r5;
K_r7 <= #1 K_r6;
K_r8 <= #1 K_r7;
K_r9 <= #1 K_r8;
K_r10 <= #1 K_r9;
K_r11 <= #1 K_r10;
K_r12 <= #1 K_r11;
K_r13 <= #1 K_r12;
K_r14 <= #1 K_r13;
end
assign K16[1] = decrypt ? K_r14[47] : K_r14[40];
assign K16[2] = decrypt ? K_r14[11] : K_r14[4];
assign K16[3] = decrypt ? K_r14[26] : K_r14[19];
assign K16[4] = decrypt ? K_r14[3] : K_r14[53];
assign K16[5] = decrypt ? K_r14[13] : K_r14[6];
assign K16[6] = decrypt ? K_r14[41] : K_r14[34];
assign K16[7] = decrypt ? K_r14[27] : K_r14[20];
assign K16[8] = decrypt ? K_r14[6] : K_r14[24];
assign K16[9] = decrypt ? K_r14[54] : K_r14[47];
assign K16[10] = decrypt ? K_r14[48] : K_r14[41];
assign K16[11] = decrypt ? K_r14[39] : K_r14[32];
assign K16[12] = decrypt ? K_r14[19] : K_r14[12];
assign K16[13] = decrypt ? K_r14[53] : K_r14[46];
assign K16[14] = decrypt ? K_r14[25] : K_r14[18];
assign K16[15] = decrypt ? K_r14[33] : K_r14[26];
assign K16[16] = decrypt ? K_r14[34] : K_r14[27];
assign K16[17] = decrypt ? K_r14[17] : K_r14[10];
assign K16[18] = decrypt ? K_r14[5] : K_r14[55];
assign K16[19] = decrypt ? K_r14[4] : K_r14[54];
assign K16[20] = decrypt ? K_r14[55] : K_r14[48];
assign K16[21] = decrypt ? K_r14[24] : K_r14[17];
assign K16[22] = decrypt ? K_r14[32] : K_r14[25];
assign K16[23] = decrypt ? K_r14[40] : K_r14[33];
assign K16[24] = decrypt ? K_r14[20] : K_r14[13];
assign K16[25] = decrypt ? K_r14[36] : K_r14[29];
assign K16[26] = decrypt ? K_r14[31] : K_r14[51];
assign K16[27] = decrypt ? K_r14[21] : K_r14[14];
assign K16[28] = decrypt ? K_r14[8] : K_r14[1];
assign K16[29] = decrypt ? K_r14[23] : K_r14[16];
assign K16[30] = decrypt ? K_r14[52] : K_r14[45];
assign K16[31] = decrypt ? K_r14[14] : K_r14[7];
assign K16[32] = decrypt ? K_r14[29] : K_r14[22];
assign K16[33] = decrypt ? K_r14[51] : K_r14[44];
assign K16[34] = decrypt ? K_r14[9] : K_r14[2];
assign K16[35] = decrypt ? K_r14[35] : K_r14[28];
assign K16[36] = decrypt ? K_r14[30] : K_r14[23];
assign K16[37] = decrypt ? K_r14[2] : K_r14[50];
assign K16[38] = decrypt ? K_r14[37] : K_r14[30];
assign K16[39] = decrypt ? K_r14[22] : K_r14[15];
assign K16[40] = decrypt ? K_r14[0] : K_r14[52];
assign K16[41] = decrypt ? K_r14[42] : K_r14[35];
assign K16[42] = decrypt ? K_r14[38] : K_r14[31];
assign K16[43] = decrypt ? K_r14[16] : K_r14[9];
assign K16[44] = decrypt ? K_r14[43] : K_r14[36];
assign K16[45] = decrypt ? K_r14[44] : K_r14[37];
assign K16[46] = decrypt ? K_r14[1] : K_r14[49];
assign K16[47] = decrypt ? K_r14[7] : K_r14[0];
assign K16[48] = decrypt ? K_r14[28] : K_r14[21];
assign K15[1] = decrypt ? K_r13[54] : K_r13[33];
assign K15[2] = decrypt ? K_r13[18] : K_r13[54];
assign K15[3] = decrypt ? K_r13[33] : K_r13[12];
assign K15[4] = decrypt ? K_r13[10] : K_r13[46];
assign K15[5] = decrypt ? K_r13[20] : K_r13[24];
assign K15[6] = decrypt ? K_r13[48] : K_r13[27];
assign K15[7] = decrypt ? K_r13[34] : K_r13[13];
assign K15[8] = decrypt ? K_r13[13] : K_r13[17];
assign K15[9] = decrypt ? K_r13[4] : K_r13[40];
assign K15[10] = decrypt ? K_r13[55] : K_r13[34];
assign K15[11] = decrypt ? K_r13[46] : K_r13[25];
assign K15[12] = decrypt ? K_r13[26] : K_r13[5];
assign K15[13] = decrypt ? K_r13[3] : K_r13[39];
assign K15[14] = decrypt ? K_r13[32] : K_r13[11];
assign K15[15] = decrypt ? K_r13[40] : K_r13[19];
assign K15[16] = decrypt ? K_r13[41] : K_r13[20];
assign K15[17] = decrypt ? K_r13[24] : K_r13[3];
assign K15[18] = decrypt ? K_r13[12] : K_r13[48];
assign K15[19] = decrypt ? K_r13[11] : K_r13[47];
assign K15[20] = decrypt ? K_r13[5] : K_r13[41];
assign K15[21] = decrypt ? K_r13[6] : K_r13[10];
assign K15[22] = decrypt ? K_r13[39] : K_r13[18];
assign K15[23] = decrypt ? K_r13[47] : K_r13[26];
assign K15[24] = decrypt ? K_r13[27] : K_r13[6];
assign K15[25] = decrypt ? K_r13[43] : K_r13[22];
assign K15[26] = decrypt ? K_r13[38] : K_r13[44];
assign K15[27] = decrypt ? K_r13[28] : K_r13[7];
assign K15[28] = decrypt ? K_r13[15] : K_r13[49];
assign K15[29] = decrypt ? K_r13[30] : K_r13[9];
assign K15[30] = decrypt ? K_r13[0] : K_r13[38];
assign K15[31] = decrypt ? K_r13[21] : K_r13[0];
assign K15[32] = decrypt ? K_r13[36] : K_r13[15];
assign K15[33] = decrypt ? K_r13[31] : K_r13[37];
assign K15[34] = decrypt ? K_r13[16] : K_r13[50];
assign K15[35] = decrypt ? K_r13[42] : K_r13[21];
assign K15[36] = decrypt ? K_r13[37] : K_r13[16];
assign K15[37] = decrypt ? K_r13[9] : K_r13[43];
assign K15[38] = decrypt ? K_r13[44] : K_r13[23];
assign K15[39] = decrypt ? K_r13[29] : K_r13[8];
assign K15[40] = decrypt ? K_r13[7] : K_r13[45];
assign K15[41] = decrypt ? K_r13[49] : K_r13[28];
assign K15[42] = decrypt ? K_r13[45] : K_r13[51];
assign K15[43] = decrypt ? K_r13[23] : K_r13[2];
assign K15[44] = decrypt ? K_r13[50] : K_r13[29];
assign K15[45] = decrypt ? K_r13[51] : K_r13[30];
assign K15[46] = decrypt ? K_r13[8] : K_r13[42];
assign K15[47] = decrypt ? K_r13[14] : K_r13[52];
assign K15[48] = decrypt ? K_r13[35] : K_r13[14];
assign K14[1] = decrypt ? K_r12[11] : K_r12[19];
assign K14[2] = decrypt ? K_r12[32] : K_r12[40];
assign K14[3] = decrypt ? K_r12[47] : K_r12[55];
assign K14[4] = decrypt ? K_r12[24] : K_r12[32];
assign K14[5] = decrypt ? K_r12[34] : K_r12[10];
assign K14[6] = decrypt ? K_r12[5] : K_r12[13];
assign K14[7] = decrypt ? K_r12[48] : K_r12[24];
assign K14[8] = decrypt ? K_r12[27] : K_r12[3];
assign K14[9] = decrypt ? K_r12[18] : K_r12[26];
assign K14[10] = decrypt ? K_r12[12] : K_r12[20];
assign K14[11] = decrypt ? K_r12[3] : K_r12[11];
assign K14[12] = decrypt ? K_r12[40] : K_r12[48];
assign K14[13] = decrypt ? K_r12[17] : K_r12[25];
assign K14[14] = decrypt ? K_r12[46] : K_r12[54];
assign K14[15] = decrypt ? K_r12[54] : K_r12[5];
assign K14[16] = decrypt ? K_r12[55] : K_r12[6];
assign K14[17] = decrypt ? K_r12[13] : K_r12[46];
assign K14[18] = decrypt ? K_r12[26] : K_r12[34];
assign K14[19] = decrypt ? K_r12[25] : K_r12[33];
assign K14[20] = decrypt ? K_r12[19] : K_r12[27];
assign K14[21] = decrypt ? K_r12[20] : K_r12[53];
assign K14[22] = decrypt ? K_r12[53] : K_r12[4];
assign K14[23] = decrypt ? K_r12[4] : K_r12[12];
assign K14[24] = decrypt ? K_r12[41] : K_r12[17];
assign K14[25] = decrypt ? K_r12[2] : K_r12[8];
assign K14[26] = decrypt ? K_r12[52] : K_r12[30];
assign K14[27] = decrypt ? K_r12[42] : K_r12[52];
assign K14[28] = decrypt ? K_r12[29] : K_r12[35];
assign K14[29] = decrypt ? K_r12[44] : K_r12[50];
assign K14[30] = decrypt ? K_r12[14] : K_r12[51];
assign K14[31] = decrypt ? K_r12[35] : K_r12[45];
assign K14[32] = decrypt ? K_r12[50] : K_r12[1];
assign K14[33] = decrypt ? K_r12[45] : K_r12[23];
assign K14[34] = decrypt ? K_r12[30] : K_r12[36];
assign K14[35] = decrypt ? K_r12[1] : K_r12[7];
assign K14[36] = decrypt ? K_r12[51] : K_r12[2];
assign K14[37] = decrypt ? K_r12[23] : K_r12[29];
assign K14[38] = decrypt ? K_r12[31] : K_r12[9];
assign K14[39] = decrypt ? K_r12[43] : K_r12[49];
assign K14[40] = decrypt ? K_r12[21] : K_r12[31];
assign K14[41] = decrypt ? K_r12[8] : K_r12[14];
assign K14[42] = decrypt ? K_r12[0] : K_r12[37];
assign K14[43] = decrypt ? K_r12[37] : K_r12[43];
assign K14[44] = decrypt ? K_r12[9] : K_r12[15];
assign K14[45] = decrypt ? K_r12[38] : K_r12[16];
assign K14[46] = decrypt ? K_r12[22] : K_r12[28];
assign K14[47] = decrypt ? K_r12[28] : K_r12[38];
assign K14[48] = decrypt ? K_r12[49] : K_r12[0];
assign K13[1] = decrypt ? K_r11[25] : K_r11[5];
assign K13[2] = decrypt ? K_r11[46] : K_r11[26];
assign K13[3] = decrypt ? K_r11[4] : K_r11[41];
assign K13[4] = decrypt ? K_r11[13] : K_r11[18];
assign K13[5] = decrypt ? K_r11[48] : K_r11[53];
assign K13[6] = decrypt ? K_r11[19] : K_r11[24];
assign K13[7] = decrypt ? K_r11[5] : K_r11[10];
assign K13[8] = decrypt ? K_r11[41] : K_r11[46];
assign K13[9] = decrypt ? K_r11[32] : K_r11[12];
assign K13[10] = decrypt ? K_r11[26] : K_r11[6];
assign K13[11] = decrypt ? K_r11[17] : K_r11[54];
assign K13[12] = decrypt ? K_r11[54] : K_r11[34];
assign K13[13] = decrypt ? K_r11[6] : K_r11[11];
assign K13[14] = decrypt ? K_r11[3] : K_r11[40];
assign K13[15] = decrypt ? K_r11[11] : K_r11[48];
assign K13[16] = decrypt ? K_r11[12] : K_r11[17];
assign K13[17] = decrypt ? K_r11[27] : K_r11[32];
assign K13[18] = decrypt ? K_r11[40] : K_r11[20];
assign K13[19] = decrypt ? K_r11[39] : K_r11[19];
assign K13[20] = decrypt ? K_r11[33] : K_r11[13];
assign K13[21] = decrypt ? K_r11[34] : K_r11[39];
assign K13[22] = decrypt ? K_r11[10] : K_r11[47];
assign K13[23] = decrypt ? K_r11[18] : K_r11[55];
assign K13[24] = decrypt ? K_r11[55] : K_r11[3];
assign K13[25] = decrypt ? K_r11[16] : K_r11[49];
assign K13[26] = decrypt ? K_r11[7] : K_r11[16];
assign K13[27] = decrypt ? K_r11[1] : K_r11[38];
assign K13[28] = decrypt ? K_r11[43] : K_r11[21];
assign K13[29] = decrypt ? K_r11[31] : K_r11[36];
assign K13[30] = decrypt ? K_r11[28] : K_r11[37];
assign K13[31] = decrypt ? K_r11[49] : K_r11[31];
assign K13[32] = decrypt ? K_r11[9] : K_r11[42];
assign K13[33] = decrypt ? K_r11[0] : K_r11[9];
assign K13[34] = decrypt ? K_r11[44] : K_r11[22];
assign K13[35] = decrypt ? K_r11[15] : K_r11[52];
assign K13[36] = decrypt ? K_r11[38] : K_r11[43];
assign K13[37] = decrypt ? K_r11[37] : K_r11[15];
assign K13[38] = decrypt ? K_r11[45] : K_r11[50];
assign K13[39] = decrypt ? K_r11[2] : K_r11[35];
assign K13[40] = decrypt ? K_r11[35] : K_r11[44];
assign K13[41] = decrypt ? K_r11[22] : K_r11[0];
assign K13[42] = decrypt ? K_r11[14] : K_r11[23];
assign K13[43] = decrypt ? K_r11[51] : K_r11[29];
assign K13[44] = decrypt ? K_r11[23] : K_r11[1];
assign K13[45] = decrypt ? K_r11[52] : K_r11[2];
assign K13[46] = decrypt ? K_r11[36] : K_r11[14];
assign K13[47] = decrypt ? K_r11[42] : K_r11[51];
assign K13[48] = decrypt ? K_r11[8] : K_r11[45];
assign K12[1] = decrypt ? K_r10[39] : K_r10[48];
assign K12[2] = decrypt ? K_r10[3] : K_r10[12];
assign K12[3] = decrypt ? K_r10[18] : K_r10[27];
assign K12[4] = decrypt ? K_r10[27] : K_r10[4];
assign K12[5] = decrypt ? K_r10[5] : K_r10[39];
assign K12[6] = decrypt ? K_r10[33] : K_r10[10];
assign K12[7] = decrypt ? K_r10[19] : K_r10[53];
assign K12[8] = decrypt ? K_r10[55] : K_r10[32];
assign K12[9] = decrypt ? K_r10[46] : K_r10[55];
assign K12[10] = decrypt ? K_r10[40] : K_r10[17];
assign K12[11] = decrypt ? K_r10[6] : K_r10[40];
assign K12[12] = decrypt ? K_r10[11] : K_r10[20];
assign K12[13] = decrypt ? K_r10[20] : K_r10[54];
assign K12[14] = decrypt ? K_r10[17] : K_r10[26];
assign K12[15] = decrypt ? K_r10[25] : K_r10[34];
assign K12[16] = decrypt ? K_r10[26] : K_r10[3];
assign K12[17] = decrypt ? K_r10[41] : K_r10[18];
assign K12[18] = decrypt ? K_r10[54] : K_r10[6];
assign K12[19] = decrypt ? K_r10[53] : K_r10[5];
assign K12[20] = decrypt ? K_r10[47] : K_r10[24];
assign K12[21] = decrypt ? K_r10[48] : K_r10[25];
assign K12[22] = decrypt ? K_r10[24] : K_r10[33];
assign K12[23] = decrypt ? K_r10[32] : K_r10[41];
assign K12[24] = decrypt ? K_r10[12] : K_r10[46];
assign K12[25] = decrypt ? K_r10[30] : K_r10[35];
assign K12[26] = decrypt ? K_r10[21] : K_r10[2];
assign K12[27] = decrypt ? K_r10[15] : K_r10[51];
assign K12[28] = decrypt ? K_r10[2] : K_r10[7];
assign K12[29] = decrypt ? K_r10[45] : K_r10[22];
assign K12[30] = decrypt ? K_r10[42] : K_r10[23];
assign K12[31] = decrypt ? K_r10[8] : K_r10[44];
assign K12[32] = decrypt ? K_r10[23] : K_r10[28];
assign K12[33] = decrypt ? K_r10[14] : K_r10[50];
assign K12[34] = decrypt ? K_r10[31] : K_r10[8];
assign K12[35] = decrypt ? K_r10[29] : K_r10[38];
assign K12[36] = decrypt ? K_r10[52] : K_r10[29];
assign K12[37] = decrypt ? K_r10[51] : K_r10[1];
assign K12[38] = decrypt ? K_r10[0] : K_r10[36];
assign K12[39] = decrypt ? K_r10[16] : K_r10[21];
assign K12[40] = decrypt ? K_r10[49] : K_r10[30];
assign K12[41] = decrypt ? K_r10[36] : K_r10[45];
assign K12[42] = decrypt ? K_r10[28] : K_r10[9];
assign K12[43] = decrypt ? K_r10[38] : K_r10[15];
assign K12[44] = decrypt ? K_r10[37] : K_r10[42];
assign K12[45] = decrypt ? K_r10[7] : K_r10[43];
assign K12[46] = decrypt ? K_r10[50] : K_r10[0];
assign K12[47] = decrypt ? K_r10[1] : K_r10[37];
assign K12[48] = decrypt ? K_r10[22] : K_r10[31];
assign K11[1] = decrypt ? K_r9[53] : K_r9[34];
assign K11[2] = decrypt ? K_r9[17] : K_r9[55];
assign K11[3] = decrypt ? K_r9[32] : K_r9[13];
assign K11[4] = decrypt ? K_r9[41] : K_r9[47];
assign K11[5] = decrypt ? K_r9[19] : K_r9[25];
assign K11[6] = decrypt ? K_r9[47] : K_r9[53];
assign K11[7] = decrypt ? K_r9[33] : K_r9[39];
assign K11[8] = decrypt ? K_r9[12] : K_r9[18];
assign K11[9] = decrypt ? K_r9[3] : K_r9[41];
assign K11[10] = decrypt ? K_r9[54] : K_r9[3];
assign K11[11] = decrypt ? K_r9[20] : K_r9[26];
assign K11[12] = decrypt ? K_r9[25] : K_r9[6];
assign K11[13] = decrypt ? K_r9[34] : K_r9[40];
assign K11[14] = decrypt ? K_r9[6] : K_r9[12];
assign K11[15] = decrypt ? K_r9[39] : K_r9[20];
assign K11[16] = decrypt ? K_r9[40] : K_r9[46];
assign K11[17] = decrypt ? K_r9[55] : K_r9[4];
assign K11[18] = decrypt ? K_r9[11] : K_r9[17];
assign K11[19] = decrypt ? K_r9[10] : K_r9[48];
assign K11[20] = decrypt ? K_r9[4] : K_r9[10];
assign K11[21] = decrypt ? K_r9[5] : K_r9[11];
assign K11[22] = decrypt ? K_r9[13] : K_r9[19];
assign K11[23] = decrypt ? K_r9[46] : K_r9[27];
assign K11[24] = decrypt ? K_r9[26] : K_r9[32];
assign K11[25] = decrypt ? K_r9[44] : K_r9[21];
assign K11[26] = decrypt ? K_r9[35] : K_r9[43];
assign K11[27] = decrypt ? K_r9[29] : K_r9[37];
assign K11[28] = decrypt ? K_r9[16] : K_r9[52];
assign K11[29] = decrypt ? K_r9[0] : K_r9[8];
assign K11[30] = decrypt ? K_r9[1] : K_r9[9];
assign K11[31] = decrypt ? K_r9[22] : K_r9[30];
assign K11[32] = decrypt ? K_r9[37] : K_r9[14];
assign K11[33] = decrypt ? K_r9[28] : K_r9[36];
assign K11[34] = decrypt ? K_r9[45] : K_r9[49];
assign K11[35] = decrypt ? K_r9[43] : K_r9[51];
assign K11[36] = decrypt ? K_r9[7] : K_r9[15];
assign K11[37] = decrypt ? K_r9[38] : K_r9[42];
assign K11[38] = decrypt ? K_r9[14] : K_r9[22];
assign K11[39] = decrypt ? K_r9[30] : K_r9[7];
assign K11[40] = decrypt ? K_r9[8] : K_r9[16];
assign K11[41] = decrypt ? K_r9[50] : K_r9[31];
assign K11[42] = decrypt ? K_r9[42] : K_r9[50];
assign K11[43] = decrypt ? K_r9[52] : K_r9[1];
assign K11[44] = decrypt ? K_r9[51] : K_r9[28];
assign K11[45] = decrypt ? K_r9[21] : K_r9[29];
assign K11[46] = decrypt ? K_r9[9] : K_r9[45];
assign K11[47] = decrypt ? K_r9[15] : K_r9[23];
assign K11[48] = decrypt ? K_r9[36] : K_r9[44];
assign K10[1] = decrypt ? K_r8[10] : K_r8[20];
assign K10[2] = decrypt ? K_r8[6] : K_r8[41];
assign K10[3] = decrypt ? K_r8[46] : K_r8[24];
assign K10[4] = decrypt ? K_r8[55] : K_r8[33];
assign K10[5] = decrypt ? K_r8[33] : K_r8[11];
assign K10[6] = decrypt ? K_r8[4] : K_r8[39];
assign K10[7] = decrypt ? K_r8[47] : K_r8[25];
assign K10[8] = decrypt ? K_r8[26] : K_r8[4];
assign K10[9] = decrypt ? K_r8[17] : K_r8[27];
assign K10[10] = decrypt ? K_r8[11] : K_r8[46];
assign K10[11] = decrypt ? K_r8[34] : K_r8[12];
assign K10[12] = decrypt ? K_r8[39] : K_r8[17];
assign K10[13] = decrypt ? K_r8[48] : K_r8[26];
assign K10[14] = decrypt ? K_r8[20] : K_r8[55];
assign K10[15] = decrypt ? K_r8[53] : K_r8[6];
assign K10[16] = decrypt ? K_r8[54] : K_r8[32];
assign K10[17] = decrypt ? K_r8[12] : K_r8[47];
assign K10[18] = decrypt ? K_r8[25] : K_r8[3];
assign K10[19] = decrypt ? K_r8[24] : K_r8[34];
assign K10[20] = decrypt ? K_r8[18] : K_r8[53];
assign K10[21] = decrypt ? K_r8[19] : K_r8[54];
assign K10[22] = decrypt ? K_r8[27] : K_r8[5];
assign K10[23] = decrypt ? K_r8[3] : K_r8[13];
assign K10[24] = decrypt ? K_r8[40] : K_r8[18];
assign K10[25] = decrypt ? K_r8[31] : K_r8[7];
assign K10[26] = decrypt ? K_r8[49] : K_r8[29];
assign K10[27] = decrypt ? K_r8[43] : K_r8[23];
assign K10[28] = decrypt ? K_r8[30] : K_r8[38];
assign K10[29] = decrypt ? K_r8[14] : K_r8[49];
assign K10[30] = decrypt ? K_r8[15] : K_r8[50];
assign K10[31] = decrypt ? K_r8[36] : K_r8[16];
assign K10[32] = decrypt ? K_r8[51] : K_r8[0];
assign K10[33] = decrypt ? K_r8[42] : K_r8[22];
assign K10[34] = decrypt ? K_r8[0] : K_r8[35];
assign K10[35] = decrypt ? K_r8[2] : K_r8[37];
assign K10[36] = decrypt ? K_r8[21] : K_r8[1];
assign K10[37] = decrypt ? K_r8[52] : K_r8[28];
assign K10[38] = decrypt ? K_r8[28] : K_r8[8];
assign K10[39] = decrypt ? K_r8[44] : K_r8[52];
assign K10[40] = decrypt ? K_r8[22] : K_r8[2];
assign K10[41] = decrypt ? K_r8[9] : K_r8[44];
assign K10[42] = decrypt ? K_r8[1] : K_r8[36];
assign K10[43] = decrypt ? K_r8[7] : K_r8[42];
assign K10[44] = decrypt ? K_r8[38] : K_r8[14];
assign K10[45] = decrypt ? K_r8[35] : K_r8[15];
assign K10[46] = decrypt ? K_r8[23] : K_r8[31];
assign K10[47] = decrypt ? K_r8[29] : K_r8[9];
assign K10[48] = decrypt ? K_r8[50] : K_r8[30];
assign K9[1] = decrypt ? K_r7[24] : K_r7[6];
assign K9[2] = decrypt ? K_r7[20] : K_r7[27];
assign K9[3] = decrypt ? K_r7[3] : K_r7[10];
assign K9[4] = decrypt ? K_r7[12] : K_r7[19];
assign K9[5] = decrypt ? K_r7[47] : K_r7[54];
assign K9[6] = decrypt ? K_r7[18] : K_r7[25];
assign K9[7] = decrypt ? K_r7[4] : K_r7[11];
assign K9[8] = decrypt ? K_r7[40] : K_r7[47];
assign K9[9] = decrypt ? K_r7[6] : K_r7[13];
assign K9[10] = decrypt ? K_r7[25] : K_r7[32];
assign K9[11] = decrypt ? K_r7[48] : K_r7[55];
assign K9[12] = decrypt ? K_r7[53] : K_r7[3];
assign K9[13] = decrypt ? K_r7[5] : K_r7[12];
assign K9[14] = decrypt ? K_r7[34] : K_r7[41];
assign K9[15] = decrypt ? K_r7[10] : K_r7[17];
assign K9[16] = decrypt ? K_r7[11] : K_r7[18];
assign K9[17] = decrypt ? K_r7[26] : K_r7[33];
assign K9[18] = decrypt ? K_r7[39] : K_r7[46];
assign K9[19] = decrypt ? K_r7[13] : K_r7[20];
assign K9[20] = decrypt ? K_r7[32] : K_r7[39];
assign K9[21] = decrypt ? K_r7[33] : K_r7[40];
assign K9[22] = decrypt ? K_r7[41] : K_r7[48];
assign K9[23] = decrypt ? K_r7[17] : K_r7[24];
assign K9[24] = decrypt ? K_r7[54] : K_r7[4];
assign K9[25] = decrypt ? K_r7[45] : K_r7[52];
assign K9[26] = decrypt ? K_r7[8] : K_r7[15];
assign K9[27] = decrypt ? K_r7[2] : K_r7[9];
assign K9[28] = decrypt ? K_r7[44] : K_r7[51];
assign K9[29] = decrypt ? K_r7[28] : K_r7[35];
assign K9[30] = decrypt ? K_r7[29] : K_r7[36];
assign K9[31] = decrypt ? K_r7[50] : K_r7[2];
assign K9[32] = decrypt ? K_r7[38] : K_r7[45];
assign K9[33] = decrypt ? K_r7[1] : K_r7[8];
assign K9[34] = decrypt ? K_r7[14] : K_r7[21];
assign K9[35] = decrypt ? K_r7[16] : K_r7[23];
assign K9[36] = decrypt ? K_r7[35] : K_r7[42];
assign K9[37] = decrypt ? K_r7[7] : K_r7[14];
assign K9[38] = decrypt ? K_r7[42] : K_r7[49];
assign K9[39] = decrypt ? K_r7[31] : K_r7[38];
assign K9[40] = decrypt ? K_r7[36] : K_r7[43];
assign K9[41] = decrypt ? K_r7[23] : K_r7[30];
assign K9[42] = decrypt ? K_r7[15] : K_r7[22];
assign K9[43] = decrypt ? K_r7[21] : K_r7[28];
assign K9[44] = decrypt ? K_r7[52] : K_r7[0];
assign K9[45] = decrypt ? K_r7[49] : K_r7[1];
assign K9[46] = decrypt ? K_r7[37] : K_r7[44];
assign K9[47] = decrypt ? K_r7[43] : K_r7[50];
assign K9[48] = decrypt ? K_r7[9] : K_r7[16];
assign K8[1] = decrypt ? K_r6[6] : K_r6[24];
assign K8[2] = decrypt ? K_r6[27] : K_r6[20];
assign K8[3] = decrypt ? K_r6[10] : K_r6[3];
assign K8[4] = decrypt ? K_r6[19] : K_r6[12];
assign K8[5] = decrypt ? K_r6[54] : K_r6[47];
assign K8[6] = decrypt ? K_r6[25] : K_r6[18];
assign K8[7] = decrypt ? K_r6[11] : K_r6[4];
assign K8[8] = decrypt ? K_r6[47] : K_r6[40];
assign K8[9] = decrypt ? K_r6[13] : K_r6[6];
assign K8[10] = decrypt ? K_r6[32] : K_r6[25];
assign K8[11] = decrypt ? K_r6[55] : K_r6[48];
assign K8[12] = decrypt ? K_r6[3] : K_r6[53];
assign K8[13] = decrypt ? K_r6[12] : K_r6[5];
assign K8[14] = decrypt ? K_r6[41] : K_r6[34];
assign K8[15] = decrypt ? K_r6[17] : K_r6[10];
assign K8[16] = decrypt ? K_r6[18] : K_r6[11];
assign K8[17] = decrypt ? K_r6[33] : K_r6[26];
assign K8[18] = decrypt ? K_r6[46] : K_r6[39];
assign K8[19] = decrypt ? K_r6[20] : K_r6[13];
assign K8[20] = decrypt ? K_r6[39] : K_r6[32];
assign K8[21] = decrypt ? K_r6[40] : K_r6[33];
assign K8[22] = decrypt ? K_r6[48] : K_r6[41];
assign K8[23] = decrypt ? K_r6[24] : K_r6[17];
assign K8[24] = decrypt ? K_r6[4] : K_r6[54];
assign K8[25] = decrypt ? K_r6[52] : K_r6[45];
assign K8[26] = decrypt ? K_r6[15] : K_r6[8];
assign K8[27] = decrypt ? K_r6[9] : K_r6[2];
assign K8[28] = decrypt ? K_r6[51] : K_r6[44];
assign K8[29] = decrypt ? K_r6[35] : K_r6[28];
assign K8[30] = decrypt ? K_r6[36] : K_r6[29];
assign K8[31] = decrypt ? K_r6[2] : K_r6[50];
assign K8[32] = decrypt ? K_r6[45] : K_r6[38];
assign K8[33] = decrypt ? K_r6[8] : K_r6[1];
assign K8[34] = decrypt ? K_r6[21] : K_r6[14];
assign K8[35] = decrypt ? K_r6[23] : K_r6[16];
assign K8[36] = decrypt ? K_r6[42] : K_r6[35];
assign K8[37] = decrypt ? K_r6[14] : K_r6[7];
assign K8[38] = decrypt ? K_r6[49] : K_r6[42];
assign K8[39] = decrypt ? K_r6[38] : K_r6[31];
assign K8[40] = decrypt ? K_r6[43] : K_r6[36];
assign K8[41] = decrypt ? K_r6[30] : K_r6[23];
assign K8[42] = decrypt ? K_r6[22] : K_r6[15];
assign K8[43] = decrypt ? K_r6[28] : K_r6[21];
assign K8[44] = decrypt ? K_r6[0] : K_r6[52];
assign K8[45] = decrypt ? K_r6[1] : K_r6[49];
assign K8[46] = decrypt ? K_r6[44] : K_r6[37];
assign K8[47] = decrypt ? K_r6[50] : K_r6[43];
assign K8[48] = decrypt ? K_r6[16] : K_r6[9];
assign K7[1] = decrypt ? K_r5[20] : K_r5[10];
assign K7[2] = decrypt ? K_r5[41] : K_r5[6];
assign K7[3] = decrypt ? K_r5[24] : K_r5[46];
assign K7[4] = decrypt ? K_r5[33] : K_r5[55];
assign K7[5] = decrypt ? K_r5[11] : K_r5[33];
assign K7[6] = decrypt ? K_r5[39] : K_r5[4];
assign K7[7] = decrypt ? K_r5[25] : K_r5[47];
assign K7[8] = decrypt ? K_r5[4] : K_r5[26];
assign K7[9] = decrypt ? K_r5[27] : K_r5[17];
assign K7[10] = decrypt ? K_r5[46] : K_r5[11];
assign K7[11] = decrypt ? K_r5[12] : K_r5[34];
assign K7[12] = decrypt ? K_r5[17] : K_r5[39];
assign K7[13] = decrypt ? K_r5[26] : K_r5[48];
assign K7[14] = decrypt ? K_r5[55] : K_r5[20];
assign K7[15] = decrypt ? K_r5[6] : K_r5[53];
assign K7[16] = decrypt ? K_r5[32] : K_r5[54];
assign K7[17] = decrypt ? K_r5[47] : K_r5[12];
assign K7[18] = decrypt ? K_r5[3] : K_r5[25];
assign K7[19] = decrypt ? K_r5[34] : K_r5[24];
assign K7[20] = decrypt ? K_r5[53] : K_r5[18];
assign K7[21] = decrypt ? K_r5[54] : K_r5[19];
assign K7[22] = decrypt ? K_r5[5] : K_r5[27];
assign K7[23] = decrypt ? K_r5[13] : K_r5[3];
assign K7[24] = decrypt ? K_r5[18] : K_r5[40];
assign K7[25] = decrypt ? K_r5[7] : K_r5[31];
assign K7[26] = decrypt ? K_r5[29] : K_r5[49];
assign K7[27] = decrypt ? K_r5[23] : K_r5[43];
assign K7[28] = decrypt ? K_r5[38] : K_r5[30];
assign K7[29] = decrypt ? K_r5[49] : K_r5[14];
assign K7[30] = decrypt ? K_r5[50] : K_r5[15];
assign K7[31] = decrypt ? K_r5[16] : K_r5[36];
assign K7[32] = decrypt ? K_r5[0] : K_r5[51];
assign K7[33] = decrypt ? K_r5[22] : K_r5[42];
assign K7[34] = decrypt ? K_r5[35] : K_r5[0];
assign K7[35] = decrypt ? K_r5[37] : K_r5[2];
assign K7[36] = decrypt ? K_r5[1] : K_r5[21];
assign K7[37] = decrypt ? K_r5[28] : K_r5[52];
assign K7[38] = decrypt ? K_r5[8] : K_r5[28];
assign K7[39] = decrypt ? K_r5[52] : K_r5[44];
assign K7[40] = decrypt ? K_r5[2] : K_r5[22];
assign K7[41] = decrypt ? K_r5[44] : K_r5[9];
assign K7[42] = decrypt ? K_r5[36] : K_r5[1];
assign K7[43] = decrypt ? K_r5[42] : K_r5[7];
assign K7[44] = decrypt ? K_r5[14] : K_r5[38];
assign K7[45] = decrypt ? K_r5[15] : K_r5[35];
assign K7[46] = decrypt ? K_r5[31] : K_r5[23];
assign K7[47] = decrypt ? K_r5[9] : K_r5[29];
assign K7[48] = decrypt ? K_r5[30] : K_r5[50];
assign K6[1] = decrypt ? K_r4[34] : K_r4[53];
assign K6[2] = decrypt ? K_r4[55] : K_r4[17];
assign K6[3] = decrypt ? K_r4[13] : K_r4[32];
assign K6[4] = decrypt ? K_r4[47] : K_r4[41];
assign K6[5] = decrypt ? K_r4[25] : K_r4[19];
assign K6[6] = decrypt ? K_r4[53] : K_r4[47];
assign K6[7] = decrypt ? K_r4[39] : K_r4[33];
assign K6[8] = decrypt ? K_r4[18] : K_r4[12];
assign K6[9] = decrypt ? K_r4[41] : K_r4[3];
assign K6[10] = decrypt ? K_r4[3] : K_r4[54];
assign K6[11] = decrypt ? K_r4[26] : K_r4[20];
assign K6[12] = decrypt ? K_r4[6] : K_r4[25];
assign K6[13] = decrypt ? K_r4[40] : K_r4[34];
assign K6[14] = decrypt ? K_r4[12] : K_r4[6];
assign K6[15] = decrypt ? K_r4[20] : K_r4[39];
assign K6[16] = decrypt ? K_r4[46] : K_r4[40];
assign K6[17] = decrypt ? K_r4[4] : K_r4[55];
assign K6[18] = decrypt ? K_r4[17] : K_r4[11];
assign K6[19] = decrypt ? K_r4[48] : K_r4[10];
assign K6[20] = decrypt ? K_r4[10] : K_r4[4];
assign K6[21] = decrypt ? K_r4[11] : K_r4[5];
assign K6[22] = decrypt ? K_r4[19] : K_r4[13];
assign K6[23] = decrypt ? K_r4[27] : K_r4[46];
assign K6[24] = decrypt ? K_r4[32] : K_r4[26];
assign K6[25] = decrypt ? K_r4[21] : K_r4[44];
assign K6[26] = decrypt ? K_r4[43] : K_r4[35];
assign K6[27] = decrypt ? K_r4[37] : K_r4[29];
assign K6[28] = decrypt ? K_r4[52] : K_r4[16];
assign K6[29] = decrypt ? K_r4[8] : K_r4[0];
assign K6[30] = decrypt ? K_r4[9] : K_r4[1];
assign K6[31] = decrypt ? K_r4[30] : K_r4[22];
assign K6[32] = decrypt ? K_r4[14] : K_r4[37];
assign K6[33] = decrypt ? K_r4[36] : K_r4[28];
assign K6[34] = decrypt ? K_r4[49] : K_r4[45];
assign K6[35] = decrypt ? K_r4[51] : K_r4[43];
assign K6[36] = decrypt ? K_r4[15] : K_r4[7];
assign K6[37] = decrypt ? K_r4[42] : K_r4[38];
assign K6[38] = decrypt ? K_r4[22] : K_r4[14];
assign K6[39] = decrypt ? K_r4[7] : K_r4[30];
assign K6[40] = decrypt ? K_r4[16] : K_r4[8];
assign K6[41] = decrypt ? K_r4[31] : K_r4[50];
assign K6[42] = decrypt ? K_r4[50] : K_r4[42];
assign K6[43] = decrypt ? K_r4[1] : K_r4[52];
assign K6[44] = decrypt ? K_r4[28] : K_r4[51];
assign K6[45] = decrypt ? K_r4[29] : K_r4[21];
assign K6[46] = decrypt ? K_r4[45] : K_r4[9];
assign K6[47] = decrypt ? K_r4[23] : K_r4[15];
assign K6[48] = decrypt ? K_r4[44] : K_r4[36];
assign K5[1] = decrypt ? K_r3[48] : K_r3[39];
assign K5[2] = decrypt ? K_r3[12] : K_r3[3];
assign K5[3] = decrypt ? K_r3[27] : K_r3[18];
assign K5[4] = decrypt ? K_r3[4] : K_r3[27];
assign K5[5] = decrypt ? K_r3[39] : K_r3[5];
assign K5[6] = decrypt ? K_r3[10] : K_r3[33];
assign K5[7] = decrypt ? K_r3[53] : K_r3[19];
assign K5[8] = decrypt ? K_r3[32] : K_r3[55];
assign K5[9] = decrypt ? K_r3[55] : K_r3[46];
assign K5[10] = decrypt ? K_r3[17] : K_r3[40];
assign K5[11] = decrypt ? K_r3[40] : K_r3[6];
assign K5[12] = decrypt ? K_r3[20] : K_r3[11];
assign K5[13] = decrypt ? K_r3[54] : K_r3[20];
assign K5[14] = decrypt ? K_r3[26] : K_r3[17];
assign K5[15] = decrypt ? K_r3[34] : K_r3[25];
assign K5[16] = decrypt ? K_r3[3] : K_r3[26];
assign K5[17] = decrypt ? K_r3[18] : K_r3[41];
assign K5[18] = decrypt ? K_r3[6] : K_r3[54];
assign K5[19] = decrypt ? K_r3[5] : K_r3[53];
assign K5[20] = decrypt ? K_r3[24] : K_r3[47];
assign K5[21] = decrypt ? K_r3[25] : K_r3[48];
assign K5[22] = decrypt ? K_r3[33] : K_r3[24];
assign K5[23] = decrypt ? K_r3[41] : K_r3[32];
assign K5[24] = decrypt ? K_r3[46] : K_r3[12];
assign K5[25] = decrypt ? K_r3[35] : K_r3[30];
assign K5[26] = decrypt ? K_r3[2] : K_r3[21];
assign K5[27] = decrypt ? K_r3[51] : K_r3[15];
assign K5[28] = decrypt ? K_r3[7] : K_r3[2];
assign K5[29] = decrypt ? K_r3[22] : K_r3[45];
assign K5[30] = decrypt ? K_r3[23] : K_r3[42];
assign K5[31] = decrypt ? K_r3[44] : K_r3[8];
assign K5[32] = decrypt ? K_r3[28] : K_r3[23];
assign K5[33] = decrypt ? K_r3[50] : K_r3[14];
assign K5[34] = decrypt ? K_r3[8] : K_r3[31];
assign K5[35] = decrypt ? K_r3[38] : K_r3[29];
assign K5[36] = decrypt ? K_r3[29] : K_r3[52];
assign K5[37] = decrypt ? K_r3[1] : K_r3[51];
assign K5[38] = decrypt ? K_r3[36] : K_r3[0];
assign K5[39] = decrypt ? K_r3[21] : K_r3[16];
assign K5[40] = decrypt ? K_r3[30] : K_r3[49];
assign K5[41] = decrypt ? K_r3[45] : K_r3[36];
assign K5[42] = decrypt ? K_r3[9] : K_r3[28];
assign K5[43] = decrypt ? K_r3[15] : K_r3[38];
assign K5[44] = decrypt ? K_r3[42] : K_r3[37];
assign K5[45] = decrypt ? K_r3[43] : K_r3[7];
assign K5[46] = decrypt ? K_r3[0] : K_r3[50];
assign K5[47] = decrypt ? K_r3[37] : K_r3[1];
assign K5[48] = decrypt ? K_r3[31] : K_r3[22];
assign K4[1] = decrypt ? K_r2[5] : K_r2[25];
assign K4[2] = decrypt ? K_r2[26] : K_r2[46];
assign K4[3] = decrypt ? K_r2[41] : K_r2[4];
assign K4[4] = decrypt ? K_r2[18] : K_r2[13];
assign K4[5] = decrypt ? K_r2[53] : K_r2[48];
assign K4[6] = decrypt ? K_r2[24] : K_r2[19];
assign K4[7] = decrypt ? K_r2[10] : K_r2[5];
assign K4[8] = decrypt ? K_r2[46] : K_r2[41];
assign K4[9] = decrypt ? K_r2[12] : K_r2[32];
assign K4[10] = decrypt ? K_r2[6] : K_r2[26];
assign K4[11] = decrypt ? K_r2[54] : K_r2[17];
assign K4[12] = decrypt ? K_r2[34] : K_r2[54];
assign K4[13] = decrypt ? K_r2[11] : K_r2[6];
assign K4[14] = decrypt ? K_r2[40] : K_r2[3];
assign K4[15] = decrypt ? K_r2[48] : K_r2[11];
assign K4[16] = decrypt ? K_r2[17] : K_r2[12];
assign K4[17] = decrypt ? K_r2[32] : K_r2[27];
assign K4[18] = decrypt ? K_r2[20] : K_r2[40];
assign K4[19] = decrypt ? K_r2[19] : K_r2[39];
assign K4[20] = decrypt ? K_r2[13] : K_r2[33];
assign K4[21] = decrypt ? K_r2[39] : K_r2[34];
assign K4[22] = decrypt ? K_r2[47] : K_r2[10];
assign K4[23] = decrypt ? K_r2[55] : K_r2[18];
assign K4[24] = decrypt ? K_r2[3] : K_r2[55];
assign K4[25] = decrypt ? K_r2[49] : K_r2[16];
assign K4[26] = decrypt ? K_r2[16] : K_r2[7];
assign K4[27] = decrypt ? K_r2[38] : K_r2[1];
assign K4[28] = decrypt ? K_r2[21] : K_r2[43];
assign K4[29] = decrypt ? K_r2[36] : K_r2[31];
assign K4[30] = decrypt ? K_r2[37] : K_r2[28];
assign K4[31] = decrypt ? K_r2[31] : K_r2[49];
assign K4[32] = decrypt ? K_r2[42] : K_r2[9];
assign K4[33] = decrypt ? K_r2[9] : K_r2[0];
assign K4[34] = decrypt ? K_r2[22] : K_r2[44];
assign K4[35] = decrypt ? K_r2[52] : K_r2[15];
assign K4[36] = decrypt ? K_r2[43] : K_r2[38];
assign K4[37] = decrypt ? K_r2[15] : K_r2[37];
assign K4[38] = decrypt ? K_r2[50] : K_r2[45];
assign K4[39] = decrypt ? K_r2[35] : K_r2[2];
assign K4[40] = decrypt ? K_r2[44] : K_r2[35];
assign K4[41] = decrypt ? K_r2[0] : K_r2[22];
assign K4[42] = decrypt ? K_r2[23] : K_r2[14];
assign K4[43] = decrypt ? K_r2[29] : K_r2[51];
assign K4[44] = decrypt ? K_r2[1] : K_r2[23];
assign K4[45] = decrypt ? K_r2[2] : K_r2[52];
assign K4[46] = decrypt ? K_r2[14] : K_r2[36];
assign K4[47] = decrypt ? K_r2[51] : K_r2[42];
assign K4[48] = decrypt ? K_r2[45] : K_r2[8];
assign K3[1] = decrypt ? K_r1[19] : K_r1[11];
assign K3[2] = decrypt ? K_r1[40] : K_r1[32];
assign K3[3] = decrypt ? K_r1[55] : K_r1[47];
assign K3[4] = decrypt ? K_r1[32] : K_r1[24];
assign K3[5] = decrypt ? K_r1[10] : K_r1[34];
assign K3[6] = decrypt ? K_r1[13] : K_r1[5];
assign K3[7] = decrypt ? K_r1[24] : K_r1[48];
assign K3[8] = decrypt ? K_r1[3] : K_r1[27];
assign K3[9] = decrypt ? K_r1[26] : K_r1[18];
assign K3[10] = decrypt ? K_r1[20] : K_r1[12];
assign K3[11] = decrypt ? K_r1[11] : K_r1[3];
assign K3[12] = decrypt ? K_r1[48] : K_r1[40];
assign K3[13] = decrypt ? K_r1[25] : K_r1[17];
assign K3[14] = decrypt ? K_r1[54] : K_r1[46];
assign K3[15] = decrypt ? K_r1[5] : K_r1[54];
assign K3[16] = decrypt ? K_r1[6] : K_r1[55];
assign K3[17] = decrypt ? K_r1[46] : K_r1[13];
assign K3[18] = decrypt ? K_r1[34] : K_r1[26];
assign K3[19] = decrypt ? K_r1[33] : K_r1[25];
assign K3[20] = decrypt ? K_r1[27] : K_r1[19];
assign K3[21] = decrypt ? K_r1[53] : K_r1[20];
assign K3[22] = decrypt ? K_r1[4] : K_r1[53];
assign K3[23] = decrypt ? K_r1[12] : K_r1[4];
assign K3[24] = decrypt ? K_r1[17] : K_r1[41];
assign K3[25] = decrypt ? K_r1[8] : K_r1[2];
assign K3[26] = decrypt ? K_r1[30] : K_r1[52];
assign K3[27] = decrypt ? K_r1[52] : K_r1[42];
assign K3[28] = decrypt ? K_r1[35] : K_r1[29];
assign K3[29] = decrypt ? K_r1[50] : K_r1[44];
assign K3[30] = decrypt ? K_r1[51] : K_r1[14];
assign K3[31] = decrypt ? K_r1[45] : K_r1[35];
assign K3[32] = decrypt ? K_r1[1] : K_r1[50];
assign K3[33] = decrypt ? K_r1[23] : K_r1[45];
assign K3[34] = decrypt ? K_r1[36] : K_r1[30];
assign K3[35] = decrypt ? K_r1[7] : K_r1[1];
assign K3[36] = decrypt ? K_r1[2] : K_r1[51];
assign K3[37] = decrypt ? K_r1[29] : K_r1[23];
assign K3[38] = decrypt ? K_r1[9] : K_r1[31];
assign K3[39] = decrypt ? K_r1[49] : K_r1[43];
assign K3[40] = decrypt ? K_r1[31] : K_r1[21];
assign K3[41] = decrypt ? K_r1[14] : K_r1[8];
assign K3[42] = decrypt ? K_r1[37] : K_r1[0];
assign K3[43] = decrypt ? K_r1[43] : K_r1[37];
assign K3[44] = decrypt ? K_r1[15] : K_r1[9];
assign K3[45] = decrypt ? K_r1[16] : K_r1[38];
assign K3[46] = decrypt ? K_r1[28] : K_r1[22];
assign K3[47] = decrypt ? K_r1[38] : K_r1[28];
assign K3[48] = decrypt ? K_r1[0] : K_r1[49];
assign K2[1] = decrypt ? K_r0[33] : K_r0[54];
assign K2[2] = decrypt ? K_r0[54] : K_r0[18];
assign K2[3] = decrypt ? K_r0[12] : K_r0[33];
assign K2[4] = decrypt ? K_r0[46] : K_r0[10];
assign K2[5] = decrypt ? K_r0[24] : K_r0[20];
assign K2[6] = decrypt ? K_r0[27] : K_r0[48];
assign K2[7] = decrypt ? K_r0[13] : K_r0[34];
assign K2[8] = decrypt ? K_r0[17] : K_r0[13];
assign K2[9] = decrypt ? K_r0[40] : K_r0[4];
assign K2[10] = decrypt ? K_r0[34] : K_r0[55];
assign K2[11] = decrypt ? K_r0[25] : K_r0[46];
assign K2[12] = decrypt ? K_r0[5] : K_r0[26];
assign K2[13] = decrypt ? K_r0[39] : K_r0[3];
assign K2[14] = decrypt ? K_r0[11] : K_r0[32];
assign K2[15] = decrypt ? K_r0[19] : K_r0[40];
assign K2[16] = decrypt ? K_r0[20] : K_r0[41];
assign K2[17] = decrypt ? K_r0[3] : K_r0[24];
assign K2[18] = decrypt ? K_r0[48] : K_r0[12];
assign K2[19] = decrypt ? K_r0[47] : K_r0[11];
assign K2[20] = decrypt ? K_r0[41] : K_r0[5];
assign K2[21] = decrypt ? K_r0[10] : K_r0[6];
assign K2[22] = decrypt ? K_r0[18] : K_r0[39];
assign K2[23] = decrypt ? K_r0[26] : K_r0[47];
assign K2[24] = decrypt ? K_r0[6] : K_r0[27];
assign K2[25] = decrypt ? K_r0[22] : K_r0[43];
assign K2[26] = decrypt ? K_r0[44] : K_r0[38];
assign K2[27] = decrypt ? K_r0[7] : K_r0[28];
assign K2[28] = decrypt ? K_r0[49] : K_r0[15];
assign K2[29] = decrypt ? K_r0[9] : K_r0[30];
assign K2[30] = decrypt ? K_r0[38] : K_r0[0];
assign K2[31] = decrypt ? K_r0[0] : K_r0[21];
assign K2[32] = decrypt ? K_r0[15] : K_r0[36];
assign K2[33] = decrypt ? K_r0[37] : K_r0[31];
assign K2[34] = decrypt ? K_r0[50] : K_r0[16];
assign K2[35] = decrypt ? K_r0[21] : K_r0[42];
assign K2[36] = decrypt ? K_r0[16] : K_r0[37];
assign K2[37] = decrypt ? K_r0[43] : K_r0[9];
assign K2[38] = decrypt ? K_r0[23] : K_r0[44];
assign K2[39] = decrypt ? K_r0[8] : K_r0[29];
assign K2[40] = decrypt ? K_r0[45] : K_r0[7];
assign K2[41] = decrypt ? K_r0[28] : K_r0[49];
assign K2[42] = decrypt ? K_r0[51] : K_r0[45];
assign K2[43] = decrypt ? K_r0[2] : K_r0[23];
assign K2[44] = decrypt ? K_r0[29] : K_r0[50];
assign K2[45] = decrypt ? K_r0[30] : K_r0[51];
assign K2[46] = decrypt ? K_r0[42] : K_r0[8];
assign K2[47] = decrypt ? K_r0[52] : K_r0[14];
assign K2[48] = decrypt ? K_r0[14] : K_r0[35];
assign K1[1] = decrypt ? K[40] : K[47];
assign K1[2] = decrypt ? K[4] : K[11];
assign K1[3] = decrypt ? K[19] : K[26];
assign K1[4] = decrypt ? K[53] : K[3];
assign K1[5] = decrypt ? K[6] : K[13];
assign K1[6] = decrypt ? K[34] : K[41];
assign K1[7] = decrypt ? K[20] : K[27];
assign K1[8] = decrypt ? K[24] : K[6];
assign K1[9] = decrypt ? K[47] : K[54];
assign K1[10] = decrypt ? K[41] : K[48];
assign K1[11] = decrypt ? K[32] : K[39];
assign K1[12] = decrypt ? K[12] : K[19];
assign K1[13] = decrypt ? K[46] : K[53];
assign K1[14] = decrypt ? K[18] : K[25];
assign K1[15] = decrypt ? K[26] : K[33];
assign K1[16] = decrypt ? K[27] : K[34];
assign K1[17] = decrypt ? K[10] : K[17];
assign K1[18] = decrypt ? K[55] : K[5];
assign K1[19] = decrypt ? K[54] : K[4];
assign K1[20] = decrypt ? K[48] : K[55];
assign K1[21] = decrypt ? K[17] : K[24];
assign K1[22] = decrypt ? K[25] : K[32];
assign K1[23] = decrypt ? K[33] : K[40];
assign K1[24] = decrypt ? K[13] : K[20];
assign K1[25] = decrypt ? K[29] : K[36];
assign K1[26] = decrypt ? K[51] : K[31];
assign K1[27] = decrypt ? K[14] : K[21];
assign K1[28] = decrypt ? K[1] : K[8];
assign K1[29] = decrypt ? K[16] : K[23];
assign K1[30] = decrypt ? K[45] : K[52];
assign K1[31] = decrypt ? K[7] : K[14];
assign K1[32] = decrypt ? K[22] : K[29];
assign K1[33] = decrypt ? K[44] : K[51];
assign K1[34] = decrypt ? K[2] : K[9];
assign K1[35] = decrypt ? K[28] : K[35];
assign K1[36] = decrypt ? K[23] : K[30];
assign K1[37] = decrypt ? K[50] : K[2];
assign K1[38] = decrypt ? K[30] : K[37];
assign K1[39] = decrypt ? K[15] : K[22];
assign K1[40] = decrypt ? K[52] : K[0];
assign K1[41] = decrypt ? K[35] : K[42];
assign K1[42] = decrypt ? K[31] : K[38];
assign K1[43] = decrypt ? K[9] : K[16];
assign K1[44] = decrypt ? K[36] : K[43];
assign K1[45] = decrypt ? K[37] : K[44];
assign K1[46] = decrypt ? K[49] : K[1];
assign K1[47] = decrypt ? K[0] : K[7];
assign K1[48] = decrypt ? K[21] : K[28];
endmodule |
module des3(desOut, desIn, key1, key2, key3, decrypt, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input clk;
wire [55:0] key_a;
wire [55:0] key_b;
wire [55:0] key_c;
wire [63:0] stage1_out, stage2_out;
reg [55:0] key_b_r [16:0];
reg [55:0] key_c_r [33:0];
integer i;
assign key_a = decrypt ? key3 : key1;
assign key_b = key2;
assign key_c = decrypt ? key1 : key3;
always @(posedge clk)
key_b_r[0] <= #1 key_b;
always @(posedge clk)
for(i=0;i<16;i=i+1)
key_b_r[i+1] <= #1 key_b_r[i];
always @(posedge clk)
key_c_r[0] <= #1 key_c;
always @(posedge clk)
for(i=0;i<33;i=i+1)
key_c_r[i+1] <= #1 key_c_r[i];
des u0( .desOut(stage1_out), .desIn(desIn), .key(key_a), .decrypt(decrypt), .clk(clk) );
des u1( .desOut(stage2_out), .desIn(stage1_out), .key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) );
des u2( .desOut(desOut), .desIn(stage2_out), .key(key_c_r[33]), .decrypt(decrypt), .clk(clk) );
endmodule |
module usbf_top(// WISHBONE Interface
clk_i, rst_i, wb_addr_i, wb_data_i, wb_data_o,
wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, inta_o, intb_o,
dma_req_o, dma_ack_i, susp_o, resume_req_i,
// UTMI Interface
phy_clk_pad_i, phy_rst_pad_o,
DataOut_pad_o, TxValid_pad_o, TxReady_pad_i,
RxValid_pad_i, RxActive_pad_i, RxError_pad_i,
DataIn_pad_i, XcvSelect_pad_o, TermSel_pad_o,
SuspendM_pad_o, LineState_pad_i,
OpMode_pad_o, usb_vbus_pad_i,
VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i,
// Buffer Memory Interface
sram_adr_o, sram_data_i, sram_data_o, sram_re_o, sram_we_o
);
parameter SSRAM_HADR = `USBF_SSRAM_HADR;
input clk_i;
input rst_i;
input [`USBF_UFC_HADR:0] wb_addr_i;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output wb_ack_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output inta_o;
output intb_o;
output [15:0] dma_req_o;
input [15:0] dma_ack_i;
output susp_o;
input resume_req_i;
input phy_clk_pad_i;
output phy_rst_pad_o;
output [7:0] DataOut_pad_o;
output TxValid_pad_o;
input TxReady_pad_i;
input [7:0] DataIn_pad_i;
input RxValid_pad_i;
input RxActive_pad_i;
input RxError_pad_i;
output XcvSelect_pad_o;
output TermSel_pad_o;
output SuspendM_pad_o;
input [1:0] LineState_pad_i;
output [1:0] OpMode_pad_o;
input usb_vbus_pad_i;
output VControl_Load_pad_o;
output [3:0] VControl_pad_o;
input [7:0] VStatus_pad_i;
output [SSRAM_HADR:0] sram_adr_o;
input [31:0] sram_data_i;
output [31:0] sram_data_o;
output sram_re_o;
output sram_we_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
// UTMI Interface
wire [7:0] rx_data;
wire rx_valid, rx_active, rx_err;
wire [7:0] tx_data;
wire tx_valid;
wire tx_ready;
wire tx_first;
wire tx_valid_last;
// Misc UTMI USB status
wire mode_hs; // High Speed Mode
wire usb_reset; // USB Reset
wire usb_suspend; // USB Sleep
wire usb_attached; // Attached to USB
wire resume_req; // Resume Request
// Memory Arbiter Interface
wire [SSRAM_HADR:0] madr; // word address
wire [31:0] mdout;
wire [31:0] mdin;
wire mwe;
wire mreq;
wire mack;
wire rst;
// Wishbone Memory interface
wire [`USBF_UFC_HADR:0] ma_adr;
wire [31:0] ma2wb_d;
wire [31:0] wb2ma_d;
wire ma_we;
wire ma_req;
wire ma_ack;
// WISHBONE Register File interface
wire rf_re;
wire rf_we;
wire [31:0] wb2rf_d;
wire [31:0] rf2wb_d;
// Internal Register File Interface
wire [6:0] funct_adr; // This functions address (set by controller)
wire [31:0] idin; // Data Input
wire [3:0] ep_sel; // Endpoint Number Input
wire match; // Endpoint Matched
wire dma_in_buf_sz1;
wire dma_out_buf_avail;
wire buf0_rl; // Reload Buf 0 with original values
wire buf0_set; // Write to buf 0
wire buf1_set; // Write to buf 1
wire uc_bsel_set; // Write to the uc_bsel field
wire uc_dpd_set; // Write to the uc_dpd field
wire int_buf1_set; // Set buf1 full/empty interrupt
wire int_buf0_set; // Set buf0 full/empty interrupt
wire int_upid_set; // Set unsupported PID interrupt
wire int_crc16_set; // Set CRC16 error interrupt
wire int_to_set; // Set time out interrupt
wire int_seqerr_set; // Set PID sequence error interrupt
wire out_to_small; // OUT packet was to small for DMA operation
wire [31:0] csr; // Internal CSR Output
wire [31:0] buf0; // Internal Buf 0 Output
wire [31:0] buf1; // Internal Buf 1 Output
wire [31:0] frm_nat; // Frame Number and Time Register
wire nse_err; // No Such Endpoint Error
wire pid_cs_err; // PID CS error
wire crc5_err; // CRC5 Error
wire rf_resume_req; // Resume Request From main CSR
reg susp_o;
reg [1:0] LineState_r; // Added to make a full synchronizer
reg [7:0] VStatus_r; // Added to make a full synchronizer
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign rst = rst_i;
assign phy_rst_pad_o = rst_i;
assign resume_req = resume_req_i;
always @(posedge clk_i)
susp_o <= usb_suspend;
always @(posedge phy_clk_pad_i) // First Stage Synchronizer
LineState_r <= LineState_pad_i;
always @(posedge phy_clk_pad_i) // First Stage Synchronizer
VStatus_r <= VStatus_pad_i;
///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//
reg resume_req_r;
reg suspend_clr_wr;
wire suspend_clr;
always @(posedge clk_i)
suspend_clr_wr <= suspend_clr;
`ifdef USBF_ASYNC_RESET
always @(posedge clk_i or negedge rst)
`else
always @(posedge clk_i)
`endif
if(!rst) resume_req_r <= 1'b0;
else
if(suspend_clr_wr) resume_req_r <= 1'b0;
else
if(resume_req) resume_req_r <= 1'b1;
// UTMI Interface
usbf_utmi_if u0(
.phy_clk( phy_clk_pad_i ),
.rst( rst ),
.DataOut( DataOut_pad_o ),
.TxValid( TxValid_pad_o ),
.TxReady( TxReady_pad_i ),
.RxValid( RxValid_pad_i ),
.RxActive( RxActive_pad_i ),
.RxError( RxError_pad_i ),
.DataIn( DataIn_pad_i ),
.XcvSelect( XcvSelect_pad_o ),
.TermSel( TermSel_pad_o ),
.SuspendM( SuspendM_pad_o ),
.LineState( LineState_pad_i ),
.OpMode( OpMode_pad_o ),
.usb_vbus( usb_vbus_pad_i ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.mode_hs( mode_hs ),
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached ),
.resume_req( resume_req_r ),
.suspend_clr( suspend_clr )
);
// Protocol Layer
usbf_pl #(SSRAM_HADR)
u1( .clk( phy_clk_pad_i ),
.rst( rst ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.tx_valid_out( TxValid_pad_o ),
.mode_hs( mode_hs ),
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached ),
.madr( madr ),
.mdout( mdout ),
.mdin( mdin ),
.mwe( mwe ),
.mreq( mreq ),
.mack( mack ),
.fa( funct_adr ),
.dma_in_buf_sz1( dma_in_buf_sz1 ),
.dma_out_buf_avail( dma_out_buf_avail ),
.idin( idin ),
.ep_sel( ep_sel ),
.match( match ),
.buf0_rl( buf0_rl ),
.buf0_set( buf0_set ),
.buf1_set( buf1_set ),
.uc_bsel_set( uc_bsel_set ),
.uc_dpd_set( uc_dpd_set ),
.int_buf1_set( int_buf1_set ),
.int_buf0_set( int_buf0_set ),
.int_upid_set( int_upid_set ),
.int_crc16_set( int_crc16_set ),
.int_to_set( int_to_set ),
.int_seqerr_set( int_seqerr_set ),
.out_to_small( out_to_small ),
.csr( csr ),
.buf0( buf0 ),
.buf1( buf1 ),
.frm_nat( frm_nat ),
.pid_cs_err( pid_cs_err ),
.nse_err( nse_err ),
.crc5_err( crc5_err )
);
// Memory Arbiter
usbf_mem_arb #(SSRAM_HADR)
u2( .phy_clk( phy_clk_pad_i ),
.wclk( clk_i ),
.rst( rst ),
.sram_adr( sram_adr_o ),
.sram_din( sram_data_i ),
.sram_dout( sram_data_o ),
.sram_re( sram_re_o ),
.sram_we( sram_we_o ),
.madr( madr ),
.mdout( mdin ),
.mdin( mdout ),
.mwe( mwe ),
.mreq( mreq ),
.mack( mack ),
.wadr( ma_adr[SSRAM_HADR + 2:2] ),
.wdout( ma2wb_d ),
.wdin( wb2ma_d ),
.wwe( ma_we ),
.wreq( ma_req ),
.wack( ma_ack )
);
// Register File
usbf_rf u4( .clk( phy_clk_pad_i ),
.wclk( clk_i ),
.rst( rst ),
.adr( ma_adr[8:2] ),
.re( rf_re ),
.we( rf_we ),
.din( wb2rf_d ),
.dout( rf2wb_d ),
.inta( inta_o ),
.intb( intb_o ),
.dma_req( dma_req_o ),
.dma_ack( dma_ack_i ),
.idin( idin ),
.ep_sel( ep_sel ),
.match( match ),
.buf0_rl( buf0_rl ),
.buf0_set( buf0_set ),
.buf1_set( buf1_set ),
.uc_bsel_set( uc_bsel_set ),
.uc_dpd_set( uc_dpd_set ),
.int_buf1_set( int_buf1_set ),
.int_buf0_set( int_buf0_set ),
.int_upid_set( int_upid_set ),
.int_crc16_set( int_crc16_set ),
.int_to_set( int_to_set ),
.int_seqerr_set( int_seqerr_set ),
.out_to_small( out_to_small ),
.csr( csr ),
.buf0( buf0 ),
.buf1( buf1 ),
.funct_adr( funct_adr ),
.dma_in_buf_sz1( dma_in_buf_sz1 ),
.dma_out_buf_avail( dma_out_buf_avail ),
.frm_nat( frm_nat ),
.utmi_vend_stat( VStatus_r ),
.utmi_vend_ctrl( VControl_pad_o ),
.utmi_vend_wr( VControl_Load_pad_o ),
.line_stat( LineState_r ),
.usb_attached( usb_attached ),
.mode_hs( mode_hs ),
.suspend( usb_suspend ),
.attached( usb_attached ),
.usb_reset( usb_reset ),
.pid_cs_err( pid_cs_err ),
.nse_err( nse_err ),
.crc5_err( crc5_err ),
.rx_err( rx_err ),
.rf_resume_req( rf_resume_req )
);
// WISHBONE Interface
usbf_wb u5( .phy_clk( phy_clk_pad_i ),
.wb_clk( clk_i ),
.rst( rst ),
.wb_addr_i( wb_addr_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( wb_data_o ),
.wb_ack_o( wb_ack_o ),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.ma_adr( ma_adr ),
.ma_dout( wb2ma_d ),
.ma_din( ma2wb_d ),
.ma_we( ma_we ),
.ma_req( ma_req ),
.ma_ack( ma_ack ),
.rf_re( rf_re ),
.rf_we( rf_we ),
.rf_dout( wb2rf_d ),
.rf_din( rf2wb_d )
);
///////////////////////////////////////////////////////////////////
//
// Initialization
// This section does not add any functionality. It is only provided
// to make sure that the core is configured properly and to provide
// configuration information for simulations.
//
// synopsys translate_off
integer ep_cnt, ep_cnt2;
reg [15:0] ep_check;
initial
begin
$display("\n");
ep_cnt = 1;
ep_cnt2 = 0;
ep_check = 0;
`ifdef USBF_HAVE_EP1
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP2
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP3
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP4
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP5
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP6
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP7
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP8
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP9
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP10
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP11
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP12
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP13
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP14
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
ep_cnt2 = ep_cnt2 + 1;
`ifdef USBF_HAVE_EP15
if(!ep_check[ep_cnt2-1])
$display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1);
ep_cnt = ep_cnt + 1;
ep_check[ep_cnt2] = 1;
`endif
$display("");
$display("INFO: USB Function core instantiated (%m)");
$display(" Supported Endpoints: %0d (0 through %0d)",ep_cnt, ep_cnt-1);
$display(" WISHBONE Address bus size: A%0d:0", `USBF_UFC_HADR );
$display(" SSRAM Address bus size: A%0d:0", SSRAM_HADR );
$display(" Buffer Memory Size: %0d bytes", (1<<SSRAM_HADR+1) * 4 );
$display("");
end
// synopsys translate_on
endmodule |
module usbf_crc5(crc_in, din, crc_out);
input [4:0] crc_in;
input [10:0] din;
output [4:0] crc_out;
assign crc_out[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
assign crc_out[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
crc_in[0] ^ crc_in[1] ^ crc_in[4];
assign crc_out[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
crc_in[2] ^ crc_in[3] ^ crc_in[4];
assign crc_out[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
assign crc_out[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
crc_in[2] ^ crc_in[3] ^ crc_in[4];
endmodule |
module usbf_wb( // WISHBONE Interface
wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o,
wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i,
// Memory Arbiter Interface
ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack,
// Register File interface
rf_re, rf_we, rf_din, rf_dout);
input wb_clk, phy_clk;
input rst;
input [`USBF_UFC_HADR:0] wb_addr_i;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output wb_ack_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
// Memory Arbiter Interface
output [`USBF_UFC_HADR:0] ma_adr;
output [31:0] ma_dout;
input [31:0] ma_din;
output ma_we;
output ma_req;
input ma_ack;
// Register File interface
output rf_re;
output rf_we;
input [31:0] rf_din;
output [31:0] rf_dout;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [5:0] // synopsys enum state
IDLE = 6'b00_0001,
MA_WR = 6'b00_0010,
MA_RD = 6'b00_0100,
W0 = 6'b00_1000,
W1 = 6'b01_0000,
W2 = 6'b10_0000;
reg [5:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg wb_req_s1;
reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2;
reg ma_we;
reg rf_re, rf_we_d;
reg ma_req;
reg wb_ack_o;
reg [31:0] wb_data_o;
///////////////////////////////////////////////////////////////////
//
// Interface Logic
//
assign ma_adr = wb_addr_i;
assign ma_dout = wb_data_i;
assign rf_dout = wb_data_i;
always @(posedge wb_clk)
if( `USBF_RF_SEL ) wb_data_o <= rf_din;
else wb_data_o <= ma_din;
// Sync WISHBONE Request
always @(posedge phy_clk)
wb_req_s1 <= wb_stb_i & wb_cyc_i;
// Sync WISHBONE Ack
always @(posedge wb_clk)
wb_ack_s1 <= wb_ack_d;
always @(posedge wb_clk)
wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
always @(posedge wb_clk)
wb_ack_s1a <= wb_ack_s1;
always @(posedge wb_clk)
wb_ack_s2 <= wb_ack_s1a;
assign rf_we = rf_we_d;
///////////////////////////////////////////////////////////////////
//
// Interface State Machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i)
begin
next_state = state;
ma_req = 1'b0;
ma_we = 1'b0;
wb_ack_d = 1'b0;
rf_re = 1'b0;
rf_we_d = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i)
begin
ma_req = 1'b1;
ma_we = 1'b1;
next_state = MA_WR;
end
if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i)
begin
ma_req = 1'b1;
next_state = MA_RD;
end
if(wb_req_s1 && `USBF_RF_SEL && wb_we_i)
begin
rf_we_d = 1'b1;
next_state = W0;
end
if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i)
begin
rf_re = 1'b1;
next_state = W0;
end
end
MA_WR:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
ma_we = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
MA_RD:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
W0:
begin
wb_ack_d = 1'b1;
next_state = W1;
end
W1:
begin
next_state = W2;
end
W2:
begin
next_state = IDLE;
end
endcase
end
endmodule |
module usbf_ep_rf_dummy(
clk, wclk, rst,
// Wishbone Interface
adr, re, we, din, dout, inta, intb,
dma_req, dma_ack,
// Internal Interface
idin,
ep_sel, ep_match,
buf0_rl, buf0_set, buf1_set,
uc_bsel_set, uc_dpd_set,
int_buf1_set, int_buf0_set, int_upid_set,
int_crc16_set, int_to_set, int_seqerr_set,
out_to_small,
csr, buf0, buf1, dma_in_buf_sz1, dma_out_buf_avail
);
input clk, wclk, rst;
input [1:0] adr;
input re;
input we;
input [31:0] din;
output [31:0] dout;
output inta, intb;
output dma_req;
input dma_ack;
input [31:0] idin; // Data Input
input [3:0] ep_sel; // Endpoint Number Input
output ep_match; // Asserted to indicate a ep no is matched
input buf0_rl; // Reload Buf 0 with original values
input buf0_set; // Write to buf 0
input buf1_set; // Write to buf 1
input uc_bsel_set; // Write to the uc_bsel field
input uc_dpd_set; // Write to the uc_dpd field
input int_buf1_set; // Set buf1 full/empty interrupt
input int_buf0_set; // Set buf0 full/empty interrupt
input int_upid_set; // Set unsupported PID interrupt
input int_crc16_set; // Set CRC16 error interrupt
input int_to_set; // Set time out interrupt
input int_seqerr_set; // Set PID sequence error interrupt
input out_to_small; // OUT packet was to small for DMA operation
output [31:0] csr; // Internal CSR Output
output [31:0] buf0; // Internal Buf 0 Output
output [31:0] buf1; // Internal Buf 1 Output
output dma_in_buf_sz1; // Indicates that the DMA IN buffer has 1 max_pl_sz
// packet available
output dma_out_buf_avail;// Indicates that there is space for at least
// one MAX_PL_SZ packet in the buffer
///////////////////////////////////////////////////////////////////
//
// Internal Access
//
assign dout = 32'h0;
assign inta = 1'b0;
assign intb = 1'b0;
assign dma_req = 1'b0;
assign ep_match = 1'b0;
assign csr = 32'h0;
assign buf0 = 32'hffff_ffff;
assign buf1 = 32'hffff_ffff;
assign dma_in_buf_sz1 = 1'b0;
assign dma_out_buf_avail = 1'b0;
endmodule |
module usbf_utmi_if( // UTMI Interface (EXTERNAL)
phy_clk, rst,
DataOut, TxValid, TxReady,
RxValid, RxActive, RxError, DataIn,
XcvSelect, TermSel, SuspendM, LineState,
OpMode, usb_vbus,
// Internal Interface
rx_data, rx_valid, rx_active, rx_err,
tx_data, tx_valid, tx_valid_last, tx_ready,
tx_first,
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
resume_req, suspend_clr
);
input phy_clk;
//input wclk;
input rst;
output [7:0] DataOut;
output TxValid;
input TxReady;
input [7:0] DataIn;
input RxValid;
input RxActive;
input RxError;
output XcvSelect;
output TermSel;
output SuspendM;
input [1:0] LineState;
output [1:0] OpMode;
input usb_vbus;
output [7:0] rx_data;
output rx_valid, rx_active, rx_err;
input [7:0] tx_data;
input tx_valid;
input tx_valid_last;
output tx_ready;
input tx_first;
output mode_hs; // High Speed Mode
output usb_reset; // USB Reset
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
input resume_req;
output suspend_clr;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [7:0] rx_data;
reg rx_valid, rx_active, rx_err;
reg [7:0] DataOut;
reg tx_ready;
reg TxValid;
wire drive_k;
reg drive_k_r;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
///////////////////////////////////////////////////////////////////
//
// RX Interface Input registers
//
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_valid <= 1'b0;
else rx_valid <= RxValid;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_active <= 1'b0;
else rx_active <= RxActive;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) rx_err <= 1'b0;
else rx_err <= RxError;
always @(posedge phy_clk)
rx_data <= DataIn;
///////////////////////////////////////////////////////////////////
//
// TX Interface Output/Input registers
//
always @(posedge phy_clk)
if(TxReady || tx_first) DataOut <= tx_data;
else
if(drive_k) DataOut <= 8'h00;
always @(posedge phy_clk)
tx_ready <= TxReady;
always @(posedge phy_clk)
drive_k_r <= drive_k;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) TxValid <= 1'b0;
else
TxValid <= tx_valid | drive_k | tx_valid_last | (TxValid & !(TxReady | drive_k_r));
///////////////////////////////////////////////////////////////////
//
// Line Status Signaling & Speed Negotiation Block
//
usbf_utmi_ls u0(
.clk( phy_clk ),
.rst( rst ),
.resume_req( resume_req ),
.rx_active( rx_active ),
.tx_ready( tx_ready ),
.drive_k( drive_k ),
.XcvSelect( XcvSelect ),
.TermSel( TermSel ),
.SuspendM( SuspendM ),
.LineState( LineState ),
.OpMode( OpMode ),
.usb_vbus( usb_vbus ),
.mode_hs( mode_hs ),
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached ),
.suspend_clr( suspend_clr )
);
endmodule |
module usbf_pd( clk, rst,
// UTMI RX I/F
rx_data, rx_valid, rx_active, rx_err,
// PID Information
pid_OUT, pid_IN, pid_SOF, pid_SETUP,
pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA,
pid_ACK, pid_NACK, pid_STALL, pid_NYET,
pid_PRE, pid_ERR, pid_SPLIT, pid_PING,
pid_cks_err,
// Token Information
token_fadr, token_endp, token_valid, crc5_err,
frame_no,
// Receive Data Output
rx_data_st, rx_data_valid, rx_data_done, crc16_err,
// Misc.
seq_err
);
input clk, rst;
//UTMI RX Interface
input [7:0] rx_data;
input rx_valid, rx_active, rx_err;
// Decoded PIDs (used when token_valid is asserted)
output pid_OUT, pid_IN, pid_SOF, pid_SETUP;
output pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
output pid_ACK, pid_NACK, pid_STALL, pid_NYET;
output pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
output pid_cks_err; // Indicates a PID checksum error
output [6:0] token_fadr; // Function address from token
output [3:0] token_endp; // Endpoint number from token
output token_valid; // Token is valid
output crc5_err; // Token crc5 error
output [10:0] frame_no; // Frame number for SOF tokens
output [7:0] rx_data_st; // Data to memory store unit
output rx_data_valid; // Data on rx_data_st is valid
output rx_data_done; // Indicates end of a transfer
output crc16_err; // Data packet CRC 16 error
output seq_err; // State Machine Sequence Error
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [3:0] // synopsys enum state
IDLE = 4'b0001,
ACTIVE = 4'b0010,
TOKEN = 4'b0100,
DATA = 4'b1000;
reg [3:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg [7:0] pid; // Packet PDI
reg pid_le_sm; // PID Load enable from State Machine
wire pid_ld_en; // Enable loading of PID (all conditions)
wire pid_cks_err; // Indicates a pid checksum err
// Decoded PID values
wire pid_OUT, pid_IN, pid_SOF, pid_SETUP;
wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
wire pid_ACK, pid_NACK, pid_STALL, pid_NYET;
wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING, pid_RES;
wire pid_TOKEN; // All TOKEN packet that we recognize
wire pid_DATA; // All DATA packets that we recognize
reg [7:0] token0, token1; // Token Registers
reg token_le_1, token_le_2; // Latch enables for token storage registers
wire [4:0] token_crc5;
reg [7:0] d0, d1, d2; // Data path delay line (used to filter out crcs)
reg data_valid_d; // Data Valid output from State Machine
reg data_done; // Data cycle complete output from State Machine
reg data_valid0; // Data valid delay line
reg rxv1;
reg rxv2;
reg seq_err; // State machine sequence error
reg got_pid_ack;
reg token_valid_r1;
reg token_valid_str1;
reg rx_active_r;
wire [4:0] crc5_out;
wire [4:0] crc5_out2;
wire crc16_clr;
reg [15:0] crc16_sum;
wire [15:0] crc16_out;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
// PID Decoding Logic
assign pid_ld_en = pid_le_sm & rx_active & rx_valid;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) pid <= 8'hf0;
else
if(pid_ld_en) pid <= rx_data;
assign pid_cks_err = (pid[3:0] != ~pid[7:4]);
assign pid_OUT = pid[3:0] == `USBF_T_PID_OUT;
assign pid_IN = pid[3:0] == `USBF_T_PID_IN;
assign pid_SOF = pid[3:0] == `USBF_T_PID_SOF;
assign pid_SETUP = pid[3:0] == `USBF_T_PID_SETUP;
assign pid_DATA0 = pid[3:0] == `USBF_T_PID_DATA0;
assign pid_DATA1 = pid[3:0] == `USBF_T_PID_DATA1;
assign pid_DATA2 = pid[3:0] == `USBF_T_PID_DATA2;
assign pid_MDATA = pid[3:0] == `USBF_T_PID_MDATA;
assign pid_ACK = pid[3:0] == `USBF_T_PID_ACK;
assign pid_NACK = pid[3:0] == `USBF_T_PID_NACK;
assign pid_STALL = pid[3:0] == `USBF_T_PID_STALL;
assign pid_NYET = pid[3:0] == `USBF_T_PID_NYET;
assign pid_PRE = pid[3:0] == `USBF_T_PID_PRE;
assign pid_ERR = pid[3:0] == `USBF_T_PID_ERR;
assign pid_SPLIT = pid[3:0] == `USBF_T_PID_SPLIT;
assign pid_PING = pid[3:0] == `USBF_T_PID_PING;
assign pid_RES = pid[3:0] == `USBF_T_PID_RES;
assign pid_TOKEN = pid_OUT | pid_IN | pid_SOF | pid_SETUP | pid_PING;
assign pid_DATA = pid_DATA0 | pid_DATA1 | pid_DATA2 | pid_MDATA;
// Token Decoding LOGIC
always @(posedge clk)
if(token_le_1) token0 <= rx_data;
always @(posedge clk)
if(token_le_2) token1 <= rx_data;
always @(posedge clk)
token_valid_r1 <= token_le_2;
always @(posedge clk)
token_valid_str1 <= token_valid_r1 | got_pid_ack;
assign token_valid = token_valid_str1;
// CRC 5 should perform the check in one cycle (flow through logic)
// 11 bits and crc5 input, 1 bit output
assign crc5_err = token_valid & (crc5_out2 != token_crc5);
usbf_crc5 u0(
.crc_in( 5'h1f ),
.din( { token_fadr[0],
token_fadr[1],
token_fadr[2],
token_fadr[3],
token_fadr[4],
token_fadr[5],
token_fadr[6],
token_endp[0],
token_endp[1],
token_endp[2],
token_endp[3] } ),
.crc_out( crc5_out ) );
// Invert and reverse result bits
assign crc5_out2 = ~{crc5_out[0], crc5_out[1], crc5_out[2], crc5_out[3],
crc5_out[4]};
assign frame_no = { token1[2:0], token0};
assign token_fadr = token0[6:0];
assign token_endp = {token1[2:0], token0[7]};
assign token_crc5 = token1[7:3];
// Data receiving logic
// build a delay line and stop when we are about to get crc
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) rxv1 <= 1'b0;
else
if(data_valid_d) rxv1 <= 1'b1;
else
if(data_done) rxv1 <= 1'b0;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) rxv2 <= 1'b0;
else
if(rxv1 && data_valid_d)rxv2 <= 1'b1;
else
if(data_done) rxv2 <= 1'b0;
always @(posedge clk)
data_valid0 <= rxv2 & data_valid_d;
always @(posedge clk)
begin
if(data_valid_d) d0 <= rx_data;
if(data_valid_d) d1 <= d0;
if(data_valid_d) d2 <= d1;
end
assign rx_data_st = d2;
assign rx_data_valid = data_valid0;
assign rx_data_done = data_done;
// crc16 accumulates rx_data as long as data_valid_d is asserted.
// when data_done is asserted, crc16 reports status, and resets itself
// next cycle.
always @(posedge clk)
rx_active_r <= rx_active;
assign crc16_clr = rx_active & !rx_active_r;
always @(posedge clk)
if(crc16_clr) crc16_sum <= 16'hffff;
else
if(data_valid_d) crc16_sum <= crc16_out;
usbf_crc16 u1(
.crc_in( crc16_sum ),
.din( {rx_data[0], rx_data[1], rx_data[2], rx_data[3],
rx_data[4], rx_data[5], rx_data[6], rx_data[7]} ),
.crc_out( crc16_out ) );
// Verify against polynomial
assign crc16_err = data_done & (crc16_sum != 16'h800d);
///////////////////////////////////////////////////////////////////
//
// Receive/Decode State machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
always @(state or rx_valid or rx_active or rx_err or pid_ACK or pid_TOKEN
or pid_DATA)
begin
next_state = state; // Default don't change current state
pid_le_sm = 1'b0;
token_le_1 = 1'b0;
token_le_2 = 1'b0;
data_valid_d = 1'b0;
data_done = 1'b0;
seq_err = 1'b0;
got_pid_ack = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
pid_le_sm = 1'b1;
if(rx_valid && rx_active) next_state = ACTIVE;
end
ACTIVE:
begin
// Received a ACK from Host
if(pid_ACK && !rx_err)
begin
got_pid_ack = 1'b1;
if(!rx_active) next_state = IDLE;
end
else
// Receiving a TOKEN
if(pid_TOKEN && rx_valid && rx_active && !rx_err)
begin
token_le_1 = 1'b1;
next_state = TOKEN;
end
else
// Receiving DATA
if(pid_DATA && rx_valid && rx_active && !rx_err)
begin
data_valid_d = 1'b1;
next_state = DATA;
end
else
if( !rx_active || rx_err ||
(rx_valid && !(pid_TOKEN || pid_DATA)) )
begin
seq_err = !rx_err;
if(!rx_active) next_state = IDLE;
end
end
TOKEN:
begin
if(rx_valid && rx_active && !rx_err)
begin
token_le_2 = 1'b1;
next_state = IDLE;
end
else
if(!rx_active || rx_err)
begin
seq_err = !rx_err;
if(!rx_active) next_state = IDLE;
end
end
DATA:
begin
if(rx_valid && rx_active && !rx_err) data_valid_d = 1'b1;
if(!rx_active || rx_err)
begin
data_done = 1'b1;
if(!rx_active) next_state = IDLE;
end
end
endcase
end
endmodule |
module usbf_idma( clk, rst,
// Packet Disassembler/Assembler interface
rx_data_st, rx_data_valid, rx_data_done,
send_data, tx_data_st, rd_next,
// Protocol Engine
rx_dma_en, tx_dma_en,
abort, idma_done,
buf_size, dma_en,
send_zero_length,
// Register File Manager Interface
adr, size, sizu_c,
// Memory Arb interface
madr, mdout, mdin, mwe, mreq, mack
);
parameter SSRAM_HADR = 14;
// Packet Disassembler/Assembler interface
input clk, rst;
input [7:0] rx_data_st;
input rx_data_valid;
input rx_data_done;
output send_data;
output [7:0] tx_data_st;
input rd_next;
// Protocol Engine
input rx_dma_en; // Allows the data to be stored
input tx_dma_en; // Allows for data to be retrieved
input abort; // Abort Transfer (time_out, crc_err or rx_error)
output idma_done; // DMA is done
input [13:0] buf_size; // Actual buffer size
input dma_en; // External DMA enabled
input send_zero_length;
// Register File Manager Interface
input [SSRAM_HADR + 2:0] adr; // Byte Address
input [13:0] size; // Size in bytes
output [10:0] sizu_c; // Up and Down counting size registers, used to update
// Memory Arb interface
output [SSRAM_HADR:0] madr; // word address
output [31:0] mdout;
input [31:0] mdin;
output mwe;
output mreq;
input mack;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [7:0] // synopsys enum state
IDLE = 8'b00000001,
WAIT_MRD = 8'b00000010,
MEM_WR = 8'b00000100,
MEM_WR1 = 8'b00001000,
MEM_WR2 = 8'b00010000,
MEM_RD1 = 8'b00100000,
MEM_RD2 = 8'b01000000,
MEM_RD3 = 8'b10000000;
reg [7:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg tx_dma_en_r, rx_dma_en_r;
reg [SSRAM_HADR:0] adr_cw; // Internal word address counter
reg [2:0] adr_cb; // Internal byte address counter
reg [SSRAM_HADR:0] adrw_next; // next address
reg [SSRAM_HADR:0] adrw_next1; // next address (after overrun check)
reg [SSRAM_HADR:0] last_buf_adr; // Last Buffer Address
reg [2:0] adrb_next; // next byte address
reg [13:0] sizd_c; // Internal size counter
reg [10:0] sizu_c; // Internal size counter
wire adr_incw;
wire adr_incb;
wire siz_dec;
wire siz_inc;
reg word_done; // Indicates that a word has been
// assembled
reg mreq_d; // Memory request from State Machine
reg [31:0] dtmp_r; // Temp data assembly register
reg [31:0] dout_r; // Data output register
reg mwe_d; // Memory Write enable
reg dtmp_sel; // Selects tmp data register for pre-fetch
reg sizd_is_zero; // Indicates when all bytes have been
// transferred
wire sizd_is_zero_d;
reg [7:0] tx_data_st; // Data output to packet assembler
reg [31:0] rd_buf0, rd_buf1; // Mem Rd. buffers for TX
reg rd_first; // Indicates initial fill of buffers
reg idma_done; // DMA transfer is done
reg mack_r;
wire send_data; // Enable UTMI Transmitter
reg send_data_r;
reg word_done_r;
reg wr_last;
reg wr_last_en;
reg wr_done;
reg wr_done_r;
reg dtmp_sel_r;
reg mwe;
reg rx_data_done_r2;
wire fill_buf0, fill_buf1;
wire adrb_is_3;
reg rx_data_done_r;
reg rx_data_valid_r;
reg [7:0] rx_data_st_r;
reg send_zero_length_r;
///////////////////////////////////////////////////////////////////
//
// Memory Arb interface
//
// Memory Request
assign mreq = (mreq_d & !mack_r) | word_done_r;
// Output Data
assign mdout = dout_r;
// Memory Address
assign madr = adr_cw;
always @(posedge clk)
mwe <= mwe_d;
always @(posedge clk)
mack_r <= mreq & mack;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
rx_data_valid_r <= rx_data_valid;
always @(posedge clk)
rx_data_st_r <= rx_data_st;
always @(posedge clk)
rx_data_done_r <= rx_data_done;
always @(posedge clk)
rx_data_done_r2 <= rx_data_done_r;
// Generate one cycle pulses for tx and rx dma enable
always @(posedge clk)
tx_dma_en_r <= tx_dma_en;
always @(posedge clk)
rx_dma_en_r <= rx_dma_en;
always @(posedge clk)
send_zero_length_r <= send_zero_length;
// address counter
always @(posedge clk)
if(rx_dma_en_r || tx_dma_en_r) adr_cw <= adr[SSRAM_HADR + 2:2];
else adr_cw <= adrw_next1;
always @(posedge clk)
last_buf_adr <= adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size };
always @(dma_en or adrw_next or last_buf_adr)
if(adrw_next == last_buf_adr && dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}};
else adrw_next1 = adrw_next;
always @(adr_incw or adr_cw)
if(adr_incw) adrw_next = adr_cw + {{SSRAM_HADR{1'b0}}, 1'b1};
else adrw_next = adr_cw;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) adr_cb <= 3'h0;
else
if(rx_dma_en_r || tx_dma_en_r) adr_cb <= adr[2:0];
else adr_cb <= adrb_next;
always @(adr_incb or adr_cb)
if(adr_incb) adrb_next = adr_cb + 3'h1;
else adrb_next = adr_cb;
assign adr_incb = rx_data_valid_r | rd_next;
assign adr_incw = !dtmp_sel_r & mack_r;
// Size Counter (counting backward from input size)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) sizd_c <= 14'h3fff;
else
if(tx_dma_en || tx_dma_en_r) sizd_c <= size;
else
if(siz_dec) sizd_c <= sizd_c - 14'h1;
assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0));
assign sizd_is_zero_d = sizd_c == 14'h0;
always @(posedge clk)
sizd_is_zero <= sizd_is_zero_d;
// Size Counter (counting up from zero)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) sizu_c <= 11'h0;
else
// Do I need to add "abort" in the next line ???
if(rx_dma_en_r) sizu_c <= 11'h0;
else
if(siz_inc) sizu_c <= sizu_c + 11'h1;
assign siz_inc = rx_data_valid_r;
// DMA Done Indicator
always @(posedge clk)
idma_done <= (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en;
///////////////////////////////////////////////////////////////////
//
// RX Logic
//
always @(posedge clk)
dtmp_sel_r <= dtmp_sel;
// Memory data input
always @(posedge clk)
if(dtmp_sel_r) dtmp_r <= mdin;
else
if(rx_data_valid_r)
begin
if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= rx_data_st_r;
end
always @(posedge clk)
word_done <= ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last;
always @(posedge clk)
word_done_r <= word_done & !word_done_r;
// Store output data and address when we got a word
always @(posedge clk)
if(word_done) dout_r <= dtmp_r;
always @(posedge clk)
wr_last <= (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en;
always @(posedge clk)
wr_done_r <= rx_data_done_r;
always @(posedge clk)
wr_done <= wr_done_r;
///////////////////////////////////////////////////////////////////
//
// TX Logic
//
// Fill TX Buffers
always @(posedge clk)
if(fill_buf0) rd_buf0 <= mdin;
always @(posedge clk)
if(fill_buf1) rd_buf1 <= mdin;
always @(adrb_next or rd_buf0 or rd_buf1)
case(adrb_next[2:0]) // synopsys full_case parallel_case
3'h0: tx_data_st = rd_buf0[07:00];
3'h1: tx_data_st = rd_buf0[15:08];
3'h2: tx_data_st = rd_buf0[23:16];
3'h3: tx_data_st = rd_buf0[31:24];
3'h4: tx_data_st = rd_buf1[07:00];
3'h5: tx_data_st = rd_buf1[15:08];
3'h6: tx_data_st = rd_buf1[23:16];
3'h7: tx_data_st = rd_buf1[31:24];
endcase
assign fill_buf0 = !adr_cw[0] & mack_r;
assign fill_buf1 = adr_cw[0] & mack_r;
assign adrb_is_3 = adr_cb[1:0] == 2'h3;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) send_data_r <= 1'b0;
else
if(rd_first) send_data_r <= 1'b1;
else
if(((sizd_c==14'h1) && rd_next) || sizd_is_zero_d) send_data_r <= 1'b0;
assign send_data = send_data_r | send_zero_length_r;
///////////////////////////////////////////////////////////////////
//
// IDMA Load/Store State Machine
//
// store incoming data to memory until rx_data done
// First pre-fetch data from memory, so that bytes can be stuffed properly
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
always @(state or mack_r or abort or rx_dma_en_r or tx_dma_en_r or
sizd_is_zero or wr_last or wr_done or rx_data_done_r2 or
rd_next or adrb_is_3 or send_zero_length_r)
begin
next_state = state; // Default do not change state
mreq_d = 1'b0;
mwe_d = 1'b0;
rd_first = 1'b0;
dtmp_sel = 1'b0;
wr_last_en = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered IDLE state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(rst)
begin
if(rx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: rx_dma_en_r is unknown. (%t)", $time);
if(tx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: tx_dma_en_r is unknown. (%t)", $time);
if(abort === 1'bx) $display("ERROR: IDMA: IDLE: abort is unknown. (%t)", $time);
end
`endif
// synopsys translate_on
if(rx_dma_en_r && !abort)
begin
next_state = WAIT_MRD;
end
if(tx_dma_en_r && !abort && !send_zero_length_r)
begin
next_state = MEM_RD1;
end
end
WAIT_MRD: // Pre-fetch a word from memory
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered WAIT_MRD state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: WAIT_MRD: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: WAIT_MRD: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_WR;
else
begin
dtmp_sel = 1'b1;
mreq_d = 1'b1;
end
end
MEM_WR:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR: abort is unknown. (%t)", $time);
if(rx_data_done_r2 === 1'bx) $display("ERROR: IDMA: MEM_WR: rx_data_done_r2 is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
if(abort) next_state = IDLE;
else
if(rx_data_done_r2)
begin
wr_last_en = 1'b1;
next_state = MEM_WR1;
end
end
MEM_WR1:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR1 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR1: abort is unknown. (%t)", $time);
if(wr_last === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_last is unknown. (%t)", $time);
if(wr_done === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_done is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
wr_last_en = 1'b1;
if(abort) next_state = IDLE;
else
if(wr_last) next_state = MEM_WR2;
else
if(wr_done) next_state = IDLE;
end
MEM_WR2:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR2 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_WR2: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
if(mack_r) next_state = IDLE;
end
MEM_RD1:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD1 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD1: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD1: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mreq_d = 1'b1;
if(mack_r) rd_first = 1'b1;
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_RD2;
end
MEM_RD2:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD2 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD2: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD2: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mreq_d = 1'b1;
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_RD3;
end
MEM_RD3:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD3 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD3: abort is unknown. (%t)", $time);
if(sizd_is_zero===1'bx) $display("ERROR: IDMA: MEM_RD3: sizd_is_zero is unknown. (%t)", $time);
if(adrb_is_3 === 1'bx) $display("ERROR: IDMA: MEM_RD3: adrb_is_3 is unknown. (%t)", $time);
if(rd_next === 1'bx) $display("ERROR: IDMA: MEM_RD3: rd_next is unknown. (%t)", $time);
`endif
// synopsys translate_on
if(sizd_is_zero || abort) next_state = IDLE;
else
if(adrb_is_3 && rd_next) next_state = MEM_RD2;
end
endcase
end
endmodule |
module usbf_pa( clk, rst,
// UTMI TX I/F
tx_data, tx_valid, tx_valid_last, tx_ready,
tx_first,
// Protocol Engine Interface
send_token, token_pid_sel,
send_data, data_pid_sel,
send_zero_length,
// IDMA Interface
tx_data_st, rd_next
);
input clk, rst;
// UTMI TX Interface
output [7:0] tx_data;
output tx_valid;
output tx_valid_last;
input tx_ready;
output tx_first;
// Protocol Engine Interface
input send_token;
input [1:0] token_pid_sel;
input send_data;
input [1:0] data_pid_sel;
input send_zero_length;
// IDMA Interface
input [7:0] tx_data_st;
output rd_next;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [4:0] // synopsys enum state
IDLE = 5'b00001,
DATA = 5'b00010,
CRC1 = 5'b00100,
CRC2 = 5'b01000,
WAIT = 5'b10000;
reg [4:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg last;
reg rd_next;
reg [7:0] token_pid, data_pid; // PIDs from selectors
reg [7:0] tx_data_d;
reg [7:0] tx_data_data;
reg dsel;
reg tx_valid_d;
reg send_token_r;
reg [7:0] tx_spec_data;
reg crc_sel1, crc_sel2;
reg tx_first_r;
reg send_data_r;
wire crc16_clr;
reg [15:0] crc16;
wire [15:0] crc16_next;
wire [15:0] crc16_rev;
wire crc16_add;
reg send_data_r2;
reg tx_valid_r;
reg tx_valid_r1;
reg zero_length_r;
reg send_zero_length_r;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
send_zero_length_r <= send_zero_length;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) zero_length_r <= 1'b0;
else
if(last) zero_length_r <= 1'b0;
else
if(crc16_clr) zero_length_r <= send_zero_length_r;
always @(posedge clk)
tx_valid_r1 <= tx_valid;
always @(posedge clk)
tx_valid_r <= tx_valid_r1;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) send_token_r <= 1'b0;
else
if(send_token) send_token_r <= 1'b1;
else
if(tx_ready) send_token_r <= 1'b0;
// PID Select
always @(token_pid_sel)
case(token_pid_sel) // synopsys full_case parallel_case
2'd0: token_pid = { ~`USBF_T_PID_ACK, `USBF_T_PID_ACK};
2'd1: token_pid = { ~`USBF_T_PID_NACK, `USBF_T_PID_NACK};
2'd2: token_pid = {~`USBF_T_PID_STALL, `USBF_T_PID_STALL};
2'd3: token_pid = { ~`USBF_T_PID_NYET, `USBF_T_PID_NYET};
endcase
always @(data_pid_sel)
case(data_pid_sel) // synopsys full_case parallel_case
2'd0: data_pid = { ~`USBF_T_PID_DATA0, `USBF_T_PID_DATA0};
2'd1: data_pid = { ~`USBF_T_PID_DATA1, `USBF_T_PID_DATA1};
2'd2: data_pid = { ~`USBF_T_PID_DATA2, `USBF_T_PID_DATA2};
2'd3: data_pid = { ~`USBF_T_PID_MDATA, `USBF_T_PID_MDATA};
endcase
// Data path Muxes
always @(send_token or send_token_r or token_pid or tx_data_data)
if(send_token || send_token_r) tx_data_d = token_pid;
else tx_data_d = tx_data_data;
always @(dsel or tx_data_st or tx_spec_data)
if(dsel) tx_data_data = tx_spec_data;
else tx_data_data = tx_data_st;
always @(crc_sel1 or crc_sel2 or data_pid or crc16_rev)
if(!crc_sel1 && !crc_sel2) tx_spec_data = data_pid;
else
if(crc_sel1) tx_spec_data = crc16_rev[15:8]; // CRC 1
else tx_spec_data = crc16_rev[7:0]; // CRC 2
assign tx_data = tx_data_d;
// TX Valid assignment
assign tx_valid_last = send_token | last;
assign tx_valid = tx_valid_d;
always @(posedge clk)
tx_first_r <= send_token | send_data;
assign tx_first = (send_token | send_data) & ! tx_first_r;
// CRC Logic
always @(posedge clk)
send_data_r <= send_data;
always @(posedge clk)
send_data_r2 <= send_data_r;
assign crc16_clr = send_data & !send_data_r;
assign crc16_add = !zero_length_r & (send_data_r & !send_data_r2) | (rd_next & !crc_sel1);
always @(posedge clk)
if(crc16_clr) crc16 <= 16'hffff;
else
if(crc16_add) crc16 <= crc16_next;
usbf_crc16 u1(
.crc_in( crc16 ),
.din( {tx_data_st[0], tx_data_st[1],
tx_data_st[2], tx_data_st[3],
tx_data_st[4], tx_data_st[5],
tx_data_st[6], tx_data_st[7]} ),
.crc_out( crc16_next ) );
assign crc16_rev[15] = ~crc16[8];
assign crc16_rev[14] = ~crc16[9];
assign crc16_rev[13] = ~crc16[10];
assign crc16_rev[12] = ~crc16[11];
assign crc16_rev[11] = ~crc16[12];
assign crc16_rev[10] = ~crc16[13];
assign crc16_rev[9] = ~crc16[14];
assign crc16_rev[8] = ~crc16[15];
assign crc16_rev[7] = ~crc16[0];
assign crc16_rev[6] = ~crc16[1];
assign crc16_rev[5] = ~crc16[2];
assign crc16_rev[4] = ~crc16[3];
assign crc16_rev[3] = ~crc16[4];
assign crc16_rev[2] = ~crc16[5];
assign crc16_rev[1] = ~crc16[6];
assign crc16_rev[0] = ~crc16[7];
///////////////////////////////////////////////////////////////////
//
// Transmit/Encode state machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
always @(state or send_data or tx_ready or tx_valid_r or send_zero_length_r)
begin
next_state = state; // Default don't change current state
tx_valid_d = 1'b0;
dsel = 1'b0;
rd_next = 1'b0;
last = 1'b0;
crc_sel1 = 1'b0;
crc_sel2 = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
if(send_zero_length_r && send_data)
begin
tx_valid_d = 1'b1;
next_state = WAIT;
dsel = 1'b1;
end
else
if(send_data) // Send DATA packet
begin
tx_valid_d = 1'b1;
next_state = DATA;
dsel = 1'b1;
end
end
DATA:
begin
if(tx_ready && tx_valid_r)
rd_next = 1'b1;
tx_valid_d = 1'b1;
if(!send_data && tx_ready && tx_valid_r)
begin
dsel = 1'b1;
crc_sel1 = 1'b1;
next_state = CRC1;
end
end
WAIT: // In case of early tx_ready ...
begin
crc_sel1 = 1'b1;
dsel = 1'b1;
tx_valid_d = 1'b1;
next_state = CRC1;
end
CRC1:
begin
dsel = 1'b1;
tx_valid_d = 1'b1;
if(tx_ready)
begin
last = 1'b1;
crc_sel2 = 1'b1;
next_state = CRC2;
end
else
begin
tx_valid_d = 1'b1;
crc_sel1 = 1'b1;
end
end
CRC2:
begin
dsel = 1'b1;
crc_sel2 = 1'b1;
if(tx_ready)
begin
next_state = IDLE;
end
else
begin
last = 1'b1;
end
end
endcase
end
endmodule |
module usbf_utmi_ls( clk, rst,
resume_req,
// UTMI Interface
rx_active, tx_ready, drive_k,
XcvSelect, TermSel, SuspendM, LineState, OpMode,
usb_vbus,
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
suspend_clr
);
input clk;
//input wclk;
input rst;
input resume_req;
input rx_active, tx_ready;
output drive_k;
output XcvSelect;
output TermSel;
output SuspendM;
input [1:0] LineState;
output [1:0] OpMode;
input usb_vbus;
output mode_hs; // High Speed Mode
output usb_reset; // USB Reset
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
output suspend_clr;
///////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter [14:0] // synopsys enum state
POR = 15'b000_0000_0000_0001,
NORMAL = 15'b000_0000_0000_0010,
RES_SUSP = 15'b000_0000_0000_0100,
SUSPEND = 15'b000_0000_0000_1000,
RESUME = 15'b000_0000_0001_0000,
RESUME_REQUEST = 15'b000_0000_0010_0000,
RESUME_WAIT = 15'b000_0000_0100_0000,
RESUME_SIG = 15'b000_0000_1000_0000,
ATTACH = 15'b000_0001_0000_0000,
RESET = 15'b000_0010_0000_0000,
SPEED_NEG = 15'b000_0100_0000_0000,
SPEED_NEG_K = 15'b000_1000_0000_0000,
SPEED_NEG_J = 15'b001_0000_0000_0000,
SPEED_NEG_HS = 15'b010_0000_0000_0000,
SPEED_NEG_FS = 15'b100_0000_0000_0000;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [14:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg [1:0] line_state_r;
reg mode_hs, mode_set_hs, mode_set_fs;
reg usb_suspend, suspend_set, suspend_clr;
reg usb_attached, attached_set, attached_clr;
reg TermSel, fs_term_on, fs_term_off;
reg XcvSelect, xcv_set_hs, xcv_set_fs;
reg [1:0] OpMode;
reg bit_stuff_on, bit_stuff_off;
reg usb_reset, usb_reset_d;
wire ls_se0, ls_j, ls_k, ls_se1;
reg ls_k_r, ls_j_r, ls_se0_r;
reg ls_idle_r;
wire ls_idle;
reg idle_long;
wire idle_long_set, idle_long_clr;
wire k_long, j_long, se0_long;
reg drive_k, drive_k_d;
reg [3:0] ps_cnt;
reg ps_cnt_clr;
reg idle_cnt_clr;
reg idle_cnt1_clr;
reg [7:0] idle_cnt1, idle_cnt1_next;
reg T1_gt_2_5_uS, T1_st_3_0_mS, T1_gt_3_0_mS;
reg T1_gt_3_125_mS, T1_gt_5_0_mS;
reg [7:0] me_ps;
reg me_cnt_clr;
reg me_ps_2_5_us;
reg [7:0] me_ps2;
reg me_ps2_0_5_ms;
reg [7:0] me_cnt;
reg me_cnt_100_ms;
reg T2_gt_100_uS, T2_wakeup, T2_gt_1_0_mS, T2_gt_1_2_mS;
reg [2:0] chirp_cnt;
reg chirp_cnt_clr, chirp_cnt_inc;
reg chirp_cnt_is_6;
reg resume_req_s1;
reg resume_req_s;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
drive_k <= drive_k_d;
assign SuspendM = (usb_suspend & !resume_req_s) | (LineState == 2'b10);
always @(posedge clk)
resume_req_s1 <= resume_req;
always @(posedge clk)
resume_req_s <= resume_req_s1;
// ---------------------------------------------------------
// USB State/Operation Mode JK Flops
always @(posedge clk)
if(mode_set_fs) mode_hs <= 1'b0;
else
if(mode_set_hs) mode_hs <= 1'b1;
always @(posedge clk)
if(suspend_clr) usb_suspend <= 1'b0;
else
if(suspend_set) usb_suspend <= 1'b1;
always @(posedge clk)
if(attached_clr) usb_attached <= 1'b0;
else
if(attached_set) usb_attached <= 1'b1;
always @(posedge clk)
if(fs_term_off) TermSel <= 1'b0;
else
if(fs_term_on) TermSel <= 1'b1;
always @(posedge clk)
if(xcv_set_fs) XcvSelect <= 1'b1;
else
if(xcv_set_hs) XcvSelect <= 1'b0;
always @(posedge clk)
if(bit_stuff_off) OpMode <= 2'b10;
else
if(bit_stuff_on) OpMode <= 2'b00;
always @(posedge clk)
usb_reset <= usb_reset_d;
// ---------------------------------------------------------
// Line State Detector
always @(posedge clk)
line_state_r <= LineState;
assign ls_se0 = (line_state_r == 2'b00);
assign ls_j = (line_state_r == 2'b01);
assign ls_k = (line_state_r == 2'b10);
assign ls_se1 = (line_state_r == 2'b11);
assign ls_idle = mode_hs ? ls_se0 : ls_j;
// Idle Detection
// Idle Has to persist for at least two cycles in a roe in the
// same state to recognized
always @(posedge clk)
ls_idle_r <= ls_idle;
assign idle_long_set = ls_idle & ls_idle_r;
assign idle_long_clr = !ls_idle & !ls_idle_r;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) idle_long <= 1'b0;
else
if(idle_long_clr) idle_long <= 1'b0;
else
if(idle_long_set) idle_long <= 1'b1;
// Detect Signals for two cycles ina row before making a transaction ...
always @(posedge clk)
ls_k_r <= ls_k;
always @(posedge clk)
ls_j_r <= ls_j;
always @(posedge clk)
ls_se0_r <= ls_se0;
assign k_long = ls_k & ls_k_r;
assign j_long = ls_j & ls_j_r;
assign se0_long = ls_se0 & ls_se0_r;
///////////////////////////////////////////////////////////////////
//
// Counters
//
// ---------------------------------------------------------
// idle Counter
// Pre-Scaler
// Generates a 0.25 uS Count Enable (ps_cnt_clr)
always @(posedge clk)
if(!idle_long || idle_cnt_clr || ps_cnt_clr) ps_cnt <= 4'd0;
else ps_cnt <= ps_cnt + 4'd1;
always @(posedge clk) // Clear the pre-scaler in 250 nS intervals
ps_cnt_clr <= (ps_cnt == `USBF_T1_PS_250_NS);
// Count uS
always @(posedge clk)
if(!idle_long || idle_cnt1_clr || idle_cnt_clr) idle_cnt1 <= 8'h0;
else
if(!T1_gt_5_0_mS && ps_cnt_clr) idle_cnt1 <= idle_cnt1_next;
always @(posedge clk)
idle_cnt1_next <= idle_cnt1 + 8'h1;
always @(posedge clk) // Clear the uS counter every 62.5 uS
idle_cnt1_clr <= idle_cnt1 == `USBF_T1_C_62_5_US;
always @(posedge clk) // Greater Than 2.5uS (Actual Time will be T0+2.75uS)
T1_gt_2_5_uS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_2_5_US);
always @(posedge clk) // Smaller Than 3 mS (Actual Time will be 0-2.9375mS)
T1_st_3_0_mS <= !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS);
always @(posedge clk) // Greater Than 3 mS (Actual Time will be T0+3.0625mS)
T1_gt_3_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS);
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_3_125_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS);
always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS)
T1_gt_5_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS);
// ---------------------------------------------------------
// Misc Events Counter
// Pre-scaler - 2.5uS
always @(posedge clk)
if(me_cnt_clr || me_ps_2_5_us) me_ps <= 8'h0;
else me_ps <= me_ps + 8'h1;
always @(posedge clk) // Generate a pulse every 2.5 uS
me_ps_2_5_us <= (me_ps == `USBF_T2_C_2_5_US);
// Second Pre-scaler - 0.5mS
always @(posedge clk)
if(me_cnt_clr || me_ps2_0_5_ms ) me_ps2 <= 8'h0;
else
if(me_ps_2_5_us) me_ps2 <= me_ps2 + 8'h1;
always @(posedge clk) // Generate a pulse every 0.5 mS
me_ps2_0_5_ms <= (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms;
// final misc Counter
always @(posedge clk)
if(me_cnt_clr) me_cnt <= 8'h0;
else
if(!me_cnt_100_ms && me_ps2_0_5_ms) me_cnt <= me_cnt + 8'h1;
always @(posedge clk) // Indicate when 100uS have passed
T2_gt_100_uS <= !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS
always @(posedge clk) // Indicate when wakeup period has passed
T2_wakeup <= !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP);
always @(posedge clk) // Indicate when 1 mS has passed
T2_gt_1_0_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS
always @(posedge clk) // Indicate when 1.2 mS has passed
T2_gt_1_2_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS
always @(posedge clk) // Generate a pulse after 100 mS
me_cnt_100_ms <= !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS
// ---------------------------------------------------------
// Chirp Counter
always @(posedge clk)
if(chirp_cnt_clr) chirp_cnt <= 3'h0;
else
if(chirp_cnt_inc) chirp_cnt <= chirp_cnt + 3'h1;
always @(posedge clk)
chirp_cnt_is_6 <= (chirp_cnt == 3'h6);
///////////////////////////////////////////////////////////////////
//
// Main State Machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) state <= POR;
else
if(usb_vbus) state <= POR;
else state <= next_state;
always @(state or mode_hs or idle_long or resume_req_s or me_cnt_100_ms or
j_long or k_long or se0_long or ls_se0 or
T1_gt_2_5_uS or T1_st_3_0_mS or T1_gt_3_0_mS or
T1_gt_5_0_mS or T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or
T2_gt_1_2_mS or chirp_cnt_is_6)
begin
next_state = state; // Default don't change state
mode_set_hs = 1'b0;
mode_set_fs = 1'b0;
suspend_set = 1'b0;
suspend_clr = 1'b0;
attached_set = 1'b0;
attached_clr = 1'b0;
usb_reset_d = 1'b0;
fs_term_on = 1'b0;
fs_term_off = 1'b0;
xcv_set_hs = 1'b0;
xcv_set_fs = 1'b0;
bit_stuff_on = 1'b0;
bit_stuff_off = 1'b0;
idle_cnt_clr = 1'b0;
me_cnt_clr = 1'b0;
drive_k_d = 1'b0;
chirp_cnt_clr = 1'b0;
chirp_cnt_inc = 1'b0;
case(state) // synopsys full_case parallel_case
POR: // Power On/Reset
begin
me_cnt_clr = 1'b1;
xcv_set_fs = 1'b1;
fs_term_on = 1'b1;
mode_set_fs = 1'b1;
attached_clr = 1'b1;
bit_stuff_on = 1'b0;
suspend_clr = 1'b1;
next_state = ATTACH;
end
NORMAL: // Normal Operation
begin
if(!mode_hs && T1_gt_2_5_uS && T1_st_3_0_mS && !idle_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(!mode_hs && T1_gt_3_0_mS)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
next_state = SUSPEND;
end
else
if(mode_hs && T1_gt_3_0_mS)
begin // Switch to FS mode, and decide
// if it's a RESET or SUSPEND
me_cnt_clr = 1'b1;
xcv_set_fs = 1'b1;
fs_term_on = 1'b1;
next_state = RES_SUSP;
end
end
RES_SUSP: // Decide if it's a Reset or Suspend Signaling
begin // We are now in FS mode, wait 100uS first
if(T2_gt_100_uS && se0_long)
begin
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(T2_gt_100_uS && j_long)
begin
idle_cnt_clr = 1'b1;
suspend_set = 1'b1;
next_state = SUSPEND;
end
end
SUSPEND: // In Suspend
begin
if(T1_gt_2_5_uS && se0_long)
begin
suspend_clr = 1'b1;
me_cnt_clr = 1'b1;
next_state = RESET;
end
else
if(k_long) // Start Resuming
next_state = RESUME;
else
if(T1_gt_5_0_mS && resume_req_s)
next_state = RESUME_REQUEST;
end
RESUME:
begin
suspend_clr = 1'b1;
if(ls_se0)
begin
if(mode_hs)
begin // Switch Back to HS mode
xcv_set_hs = 1'b1;
fs_term_off = 1'b1;
end
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_WAIT;
end
end
RESUME_WAIT:
begin
if(T2_gt_100_uS) next_state = NORMAL;
end
RESUME_REQUEST: // Function Resume Request
begin
suspend_clr = 1'b1;
// Wait for internal wake up
if(T2_wakeup)
begin
fs_term_on = 1'b1; // Switch Termination to Full Speed
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
me_cnt_clr = 1'b1;
next_state = RESUME_SIG;
end
end
RESUME_SIG: // Signal resume
begin
// Drive Resume ('K') for 1-15 mS
drive_k_d = 1'b1;
// Stop driving after 1.5 mS
if(T2_gt_1_0_mS) next_state = RESUME;
end
ATTACH: // Attach To USB Detected
begin
idle_cnt_clr = 1'b1;
if(me_cnt_100_ms)
//if(me_cnt_100_ms && j_long)
begin
attached_set = 1'b1;
next_state = NORMAL;
end
/*
if(me_cnt_100_ms && se0_long)
begin
attached_set = 1'b1;
me_cnt_clr = 1'b1;
next_state = RESET;
end
*/
end
RESET: // In Reset
begin
usb_reset_d = 1'b1; // Assert Internal USB Reset
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding
// Get out of reset after 1.5 mS
if(T2_gt_1_0_mS)
begin
me_cnt_clr = 1'b1;
next_state = SPEED_NEG;
end
end
SPEED_NEG: // Speed Negotiation
begin
drive_k_d = 1'b1;
chirp_cnt_clr = 1'b1;
// Start looking for 'K' after 1.5 mS
if(T2_gt_1_2_mS) next_state = SPEED_NEG_K;
end
SPEED_NEG_K:
begin
if(chirp_cnt_is_6) next_state = SPEED_NEG_HS;
else
begin
if(k_long)
begin
chirp_cnt_inc = 1'b1;
next_state = SPEED_NEG_J;
end
if(se0_long)
next_state = SPEED_NEG_FS;
end
end
SPEED_NEG_J:
begin
if(chirp_cnt_is_6) next_state = SPEED_NEG_HS;
else
begin
if(j_long)
begin
chirp_cnt_inc = 1'b1;
next_state = SPEED_NEG_K;
end
if(se0_long)
next_state = SPEED_NEG_FS;
end
end
SPEED_NEG_HS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_hs = 1'b1; // Switch xcvr to HS mode
fs_term_off = 1'b1; // Turn FS termination Off
mode_set_hs = 1'b1; // Change mode to HS
if(se0_long) next_state = NORMAL;
end
SPEED_NEG_FS:
begin
bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding
xcv_set_fs = 1'b1; // Switch xcvr to FS mode
fs_term_on = 1'b1; // Turn FS termination On
mode_set_fs = 1'b1; // Change mode to FS
next_state = NORMAL;
end
endcase
end
endmodule |
module usbf_pl( clk, rst,
// UTMI Interface
rx_data, rx_valid, rx_active, rx_err,
tx_data, tx_valid, tx_valid_last, tx_ready,
tx_first, tx_valid_out,
mode_hs, usb_reset, usb_suspend, usb_attached,
// memory interface
madr, mdout, mdin, mwe, mreq, mack,
// Register File Interface
fa, idin,
ep_sel, match,
dma_in_buf_sz1, dma_out_buf_avail,
buf0_rl, buf0_set, buf1_set,
uc_bsel_set, uc_dpd_set,
int_buf1_set, int_buf0_set, int_upid_set,
int_crc16_set, int_to_set, int_seqerr_set,
out_to_small, csr, buf0, buf1,
// Misc
frm_nat,
pid_cs_err, nse_err,
crc5_err
);
parameter SSRAM_HADR = 14;
// UTMI Interface
input clk, rst;
input [7:0] rx_data;
input rx_valid, rx_active, rx_err;
output [7:0] tx_data;
output tx_valid;
output tx_valid_last;
input tx_ready;
output tx_first;
input tx_valid_out;
input mode_hs; // High Speed Mode
input usb_reset; // USB Reset
input usb_suspend; // USB Suspend
input usb_attached; // Attached to USB
// Memory Arbiter Interface
output [SSRAM_HADR:0] madr; // word address
output [31:0] mdout;
input [31:0] mdin;
output mwe;
output mreq;
input mack;
// Register File interface
input [6:0] fa; // Function Address (as set by the controller)
output [31:0] idin; // Data Input
output [3:0] ep_sel; // Endpoint Number Input
input match; // Endpoint Matched
input dma_in_buf_sz1;
input dma_out_buf_avail;
output nse_err; // no such endpoint error
output buf0_rl; // Reload Buf 0 with original values
output buf0_set; // Write to buf 0
output buf1_set; // Write to buf 1
output uc_bsel_set; // Write to the uc_bsel field
output uc_dpd_set; // Write to the uc_dpd field
output int_buf1_set; // Set buf1 full/empty interrupt
output int_buf0_set; // Set buf0 full/empty interrupt
output int_upid_set; // Set unsupported PID interrupt
output int_crc16_set; // Set CRC16 error interrupt
output int_to_set; // Set time out interrupt
output int_seqerr_set; // Set PID sequence error interrupt
output out_to_small; // OUT packet was to small for DMA operation
input [31:0] csr; // Internal CSR Output
input [31:0] buf0; // Internal Buf 0 Output
input [31:0] buf1; // Internal Buf 1 Output
// Misc
output pid_cs_err; // pid checksum error
output crc5_err; // crc5 error
output [31:0] frm_nat;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
// Packet Disassembler Interface
wire clk, rst;
wire [7:0] rx_data;
wire pid_OUT, pid_IN, pid_SOF, pid_SETUP;
wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;
wire pid_ACK, pid_NACK, pid_STALL, pid_NYET;
wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING;
wire [6:0] token_fadr;
wire token_valid;
wire crc5_err;
wire [10:0] frame_no;
wire [7:0] rx_data_st;
wire rx_data_valid;
wire rx_data_done;
wire crc16_err;
wire rx_seq_err;
// Packet Assembler Interface
wire send_token;
wire [1:0] token_pid_sel;
wire send_data;
wire [1:0] data_pid_sel;
wire [7:0] tx_data_st;
wire rd_next;
// IDMA Interface
wire rx_dma_en; // Allows the data to be stored
wire tx_dma_en; // Allows for data to be retrieved
wire abort; // Abort Transfer (time_out, crc_err or rx_error)
wire idma_done; // DMA is done
wire [SSRAM_HADR + 2:0] adr; // Byte Address
wire [13:0] size; // Size in bytes
wire [10:0] sizu_c; // Up and Down counting size registers, used
// to update
wire [13:0] buf_size; // Actual buffer size
wire dma_en; // external dma enabled
// Memory Arbiter Interface
wire [SSRAM_HADR:0] madr; // word address
wire [31:0] mdout;
wire [31:0] mdin;
wire mwe;
wire mreq;
wire mack;
// Local signals
wire pid_bad, pid_bad1, pid_bad2;
reg hms_clk; // 0.5 Micro Second Clock
reg [4:0] hms_cnt;
reg [10:0] frame_no_r; // Current Frame Number register
wire frame_no_we;
reg frame_no_same; // Indicates current and prev. frame numbers
// are equal
reg [3:0] mfm_cnt; // Micro Frame Counter
reg [11:0] sof_time; // Time since last sof
reg clr_sof_time;
wire fsel; // This Function is selected
wire match_o;
reg frame_no_we_r;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
// PIDs we should never receive
assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE |
pid_ERR | pid_SPLIT;
// PIDs we should never get in full speed mode (high speed mode only)
assign pid_bad2 = !mode_hs & pid_PING;
// All bad pids
assign pid_bad = pid_bad1 | pid_bad2;
assign match_o = !pid_bad & fsel & match & token_valid & !crc5_err;
// Frame Number (from SOF token)
assign frame_no_we = token_valid & !crc5_err & pid_SOF;
always @(posedge clk)
frame_no_we_r <= frame_no_we;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) frame_no_r <= 11'h0;
else
if(frame_no_we_r) frame_no_r <= frame_no;
// Micro Frame Counter
always @(posedge clk)
frame_no_same <= frame_no_we & (frame_no_r == frame_no);
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) mfm_cnt <= 4'h0;
else
if(frame_no_we_r && !frame_no_same)
mfm_cnt <= 4'h0;
else
if(frame_no_same) mfm_cnt <= mfm_cnt + 4'h1;
//SOF delay counter
always @(posedge clk)
clr_sof_time <= frame_no_we;
always @(posedge clk)
if(clr_sof_time) sof_time <= 12'h0;
else
if(hms_clk) sof_time <= sof_time + 12'h1;
assign frm_nat = {mfm_cnt, 1'b0, frame_no_r, 4'h0, sof_time};
// 0.5 Micro Seconds Clock Generator
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) hms_cnt <= 5'h0;
else
if(hms_clk || frame_no_we_r) hms_cnt <= 5'h0;
else hms_cnt <= hms_cnt + 5'h1;
always @(posedge clk)
hms_clk <= (hms_cnt == `USBF_HMS_DEL);
///////////////////////////////////////////////////////////////////
// This function is addressed
assign fsel = (token_fadr == fa);
///////////////////////////////////////////////////////////////////
//
// Module Instantiations
//
//Packet Decoder
usbf_pd u0( .clk( clk ),
.rst( rst ),
.rx_data( rx_data ),
.rx_valid( rx_valid ),
.rx_active( rx_active ),
.rx_err( rx_err ),
.pid_OUT( pid_OUT ),
.pid_IN( pid_IN ),
.pid_SOF( pid_SOF ),
.pid_SETUP( pid_SETUP ),
.pid_DATA0( pid_DATA0 ),
.pid_DATA1( pid_DATA1 ),
.pid_DATA2( pid_DATA2 ),
.pid_MDATA( pid_MDATA ),
.pid_ACK( pid_ACK ),
.pid_NACK( pid_NACK ),
.pid_STALL( pid_STALL ),
.pid_NYET( pid_NYET ),
.pid_PRE( pid_PRE ),
.pid_ERR( pid_ERR ),
.pid_SPLIT( pid_SPLIT ),
.pid_PING( pid_PING ),
.pid_cks_err( pid_cs_err ),
.token_fadr( token_fadr ),
.token_endp( ep_sel ),
.token_valid( token_valid ),
.crc5_err( crc5_err ),
.frame_no( frame_no ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.crc16_err( crc16_err ),
.seq_err( rx_seq_err )
);
// Packet Assembler
usbf_pa u1( .clk( clk ),
.rst( rst ),
.tx_data( tx_data ),
.tx_valid( tx_valid ),
.tx_valid_last( tx_valid_last ),
.tx_ready( tx_ready ),
.tx_first( tx_first ),
.send_token( send_token ),
.token_pid_sel( token_pid_sel ),
.send_data( send_data ),
.data_pid_sel( data_pid_sel ),
.send_zero_length( send_zero_length ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next )
);
// Internal DMA / Memory Arbiter Interface
usbf_idma #(SSRAM_HADR)
u2( .clk( clk ),
.rst( rst ),
.rx_data_st( rx_data_st ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.send_data( send_data ),
.tx_data_st( tx_data_st ),
.rd_next( rd_next ),
.rx_dma_en( rx_dma_en ),
.tx_dma_en( tx_dma_en ),
.abort( abort ),
.idma_done( idma_done ),
.adr( adr ),
.size( size ),
.buf_size( buf_size ),
.dma_en( dma_en ),
.send_zero_length( send_zero_length ),
.madr( madr ),
.sizu_c( sizu_c ),
.mdout( mdout ),
.mdin( mdin ),
.mwe( mwe ),
.mreq( mreq ),
.mack( mack )
);
// Protocol Engine
usbf_pe #(SSRAM_HADR)
u3( .clk( clk ),
.rst( rst ),
.tx_valid( tx_valid_out ),
.rx_active( rx_active ),
.pid_OUT( pid_OUT ),
.pid_IN( pid_IN ),
.pid_SOF( pid_SOF ),
.pid_SETUP( pid_SETUP ),
.pid_DATA0( pid_DATA0 ),
.pid_DATA1( pid_DATA1 ),
.pid_DATA2( pid_DATA2 ),
.pid_MDATA( pid_MDATA ),
.pid_ACK( pid_ACK ),
.pid_NACK( pid_NACK ),
.pid_STALL( pid_STALL ),
.pid_NYET( pid_NYET ),
.pid_PRE( pid_PRE ),
.pid_ERR( pid_ERR ),
.pid_SPLIT( pid_SPLIT ),
.pid_PING( pid_PING ),
.mode_hs( mode_hs ),
.token_valid( token_valid ),
.crc5_err( crc5_err ),
.rx_data_valid( rx_data_valid ),
.rx_data_done( rx_data_done ),
.crc16_err( crc16_err ),
.send_token( send_token ),
.token_pid_sel( token_pid_sel ),
.data_pid_sel( data_pid_sel ),
.send_zero_length( send_zero_length ),
.rx_dma_en( rx_dma_en ),
.tx_dma_en( tx_dma_en ),
.abort( abort ),
.idma_done( idma_done ),
.adr( adr ),
.size( size ),
.buf_size( buf_size ),
.sizu_c( sizu_c ),
.dma_en( dma_en ),
.fsel( fsel ),
.idin( idin ),
.ep_sel( ep_sel ),
.match( match_o ),
.dma_in_buf_sz1( dma_in_buf_sz1 ),
.dma_out_buf_avail( dma_out_buf_avail ),
.nse_err( nse_err ),
.buf0_rl( buf0_rl ),
.buf0_set( buf0_set ),
.buf1_set( buf1_set ),
.uc_bsel_set( uc_bsel_set ),
.uc_dpd_set( uc_dpd_set ),
.int_buf1_set( int_buf1_set ),
.int_buf0_set( int_buf0_set ),
.int_upid_set( int_upid_set ),
.int_crc16_set( int_crc16_set ),
.int_to_set( int_to_set ),
.int_seqerr_set( int_seqerr_set ),
.out_to_small( out_to_small ),
.csr( csr ),
.buf0( buf0 ),
.buf1( buf1 )
);
endmodule |
module usbf_crc16(crc_in, din, crc_out);
input [15:0] crc_in;
input [7:0] din;
output [15:0] crc_out;
assign crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^
din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
crc_in[14] ^ crc_in[15];
assign crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^
crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15];
assign crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9];
assign crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10];
assign crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11];
assign crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12];
assign crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13];
assign crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14];
assign crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15];
assign crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15];
assign crc_out[10] = crc_in[2];
assign crc_out[11] = crc_in[3];
assign crc_out[12] = crc_in[4];
assign crc_out[13] = crc_in[5];
assign crc_out[14] = crc_in[6];
assign crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^
din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^
crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^
crc_in[14] ^ crc_in[15];
endmodule |
module usbf_mem_arb( phy_clk, wclk, rst,
// SSRAM Interface
sram_adr, sram_din, sram_dout, sram_re, sram_we,
// IDMA Memory Interface
madr, mdout, mdin, mwe, mreq, mack,
// WISHBONE Memory Interface
wadr, wdout, wdin, wwe, wreq, wack
);
parameter SSRAM_HADR = 14;
input phy_clk, wclk, rst;
output [SSRAM_HADR:0] sram_adr;
input [31:0] sram_din;
output [31:0] sram_dout;
output sram_re, sram_we;
input [SSRAM_HADR:0] madr;
output [31:0] mdout;
input [31:0] mdin;
input mwe;
input mreq;
output mack;
input [SSRAM_HADR:0] wadr;
output [31:0] wdout;
input [31:0] wdin;
input wwe;
input wreq;
output wack;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire wsel;
reg [SSRAM_HADR:0] sram_adr;
reg [31:0] sram_dout;
reg sram_we;
wire mack;
wire mcyc;
reg wack_r;
///////////////////////////////////////////////////////////////////
//
// Memory Arbiter Logic
//
// IDMA has always first priority
// -----------------------------------------
// Ctrl Signals
assign wsel = (wreq | wack) & !mreq;
// -----------------------------------------
// SSRAM Specific
// Data Path
always @(wsel or wdin or mdin)
if(wsel) sram_dout = wdin;
else sram_dout = mdin;
// Address Path
always @(wsel or wadr or madr)
if(wsel) sram_adr = wadr;
else sram_adr = madr;
// Write Enable Path
always @(wsel or wwe or wreq or mwe or mcyc)
if(wsel) sram_we = wreq & wwe;
else sram_we = mwe & mcyc;
assign sram_re = 1'b1;
// -----------------------------------------
// IDMA specific
assign mdout = sram_din;
assign mack = mreq;
assign mcyc = mack; // Qualifier for writes
// -----------------------------------------
// WISHBONE specific
assign wdout = sram_din;
assign wack = wack_r & !mreq;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
if(!rst) wack_r <= 1'b0;
else wack_r <= wreq & !mreq & !wack;
endmodule |
module keysched(clk,reset,start_i,round_i,last_key_i,new_key_o,ready_o,sbox_access_o,sbox_data_o,sbox_data_i,sbox_decrypt_o);
input clk;
input reset;
input start_i;
input [3:0] round_i;
input [127:0] last_key_i;
output [127:0] new_key_o;
output ready_o;
output sbox_access_o;
output [7:0] sbox_data_o;
input [7:0] sbox_data_i;
output sbox_decrypt_o;
reg [127:0] new_key_o;
reg ready_o;
reg sbox_access_o;
reg [7:0] sbox_data_o;
reg sbox_decrypt_o;
reg [2:0] next_state;
reg [2:0] state;
reg [7:0] rcon_o;
reg [31:0] next_col;
reg [31:0] col;
reg [127:0] key_reg;
reg [127:0] next_key_reg;
reg next_ready_o;
//rcon:
always @( round_i)
begin
case(round_i)
1:
begin
rcon_o = (1);
end
2:
begin
rcon_o = (2);
end
3:
begin
rcon_o = (4);
end
4:
begin
rcon_o = (8);
end
5:
begin
rcon_o = ('h10);
end
6:
begin
rcon_o = ('h20);
end
7:
begin
rcon_o = ('h40);
end
8:
begin
rcon_o = ('h80);
end
9:
begin
rcon_o = ('h1B);
end
10:
begin
rcon_o = ('h36);
end
default:
begin
rcon_o = (0);
end
endcase
end
//registers:
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
state = (0);
col = (0);
key_reg = (0);
ready_o = (0);
end
else
begin
state = (next_state);
col = (next_col);
key_reg = (next_key_reg);
ready_o = (next_ready_o);
end
end
//generate_key:
reg[127:0] K_var,W_var;
reg[31:0] col_t;
reg[23:0] zero;
always @( start_i or last_key_i or sbox_data_i or state or rcon_o or col or key_reg)
begin
zero=0;
col_t=col;
W_var=0;
next_state = (state);
next_col = (col);
next_ready_o = (0);
next_key_reg = (key_reg);
new_key_o = (key_reg);
sbox_decrypt_o = (0);
sbox_access_o = (0);
sbox_data_o = (0);
K_var=last_key_i;
case(state)
//Substitutethebyteswhilerotatingthem
//FouraccessestoSBoxareneeded
0:
begin
if(start_i)
begin
col_t=0;
sbox_access_o = (1);
sbox_data_o = (K_var[31:24]);
next_state = (1);
end
end
1:
begin
sbox_access_o = (1);
sbox_data_o = (K_var[23:16]);
col_t[7:0]=sbox_data_i;
next_col = (col_t);
next_state = (2);
end
2:
begin
sbox_access_o = (1);
sbox_data_o = (K_var[15:8]);
col_t[31:24]=sbox_data_i;
next_col = (col_t);
next_state = (3);
end
3:
begin
sbox_access_o = (1);
sbox_data_o = (K_var[7:0]);
col_t[23:16]=sbox_data_i;
next_col = (col_t);
next_state = (4);
end
4:
begin
sbox_access_o = (1);
col_t[15:8]=sbox_data_i;
next_col = (col_t);
W_var[127:96]=col_t^K_var[127:96]^{rcon_o,zero};
W_var[95:64]=W_var[127:96]^K_var[95:64];
W_var[63:32]=W_var[95:64]^K_var[63:32];
W_var[31:0]=W_var[63:32]^K_var[31:0];
next_ready_o = (1);
next_key_reg = (W_var);
next_state = (0);
end
default:
begin
next_state = (0);
end
endcase
end
endmodule |
module aes(clk,reset,load_i,decrypt_i,data_i,key_i,ready_o,data_o);
input clk;
input reset;
input load_i;
input decrypt_i;
input [127:0] data_i;
input [127:0] key_i;
output ready_o;
output [127:0] data_o;
reg ready_o;
reg [127:0] data_o;
reg next_ready_o;
reg keysched_start_i;
reg [3:0] keysched_round_i;
reg [127:0] keysched_last_key_i;
wire [127:0] keysched_new_key_o;
wire keysched_ready_o;
wire keysched_sbox_access_o;
wire [7:0] keysched_sbox_data_o;
wire keysched_sbox_decrypt_o;
reg mixcol_start_i;
reg [127:0] mixcol_data_i;
wire mixcol_ready_o;
wire [127:0] mixcol_data_o;
reg subbytes_start_i;
reg [127:0] subbytes_data_i;
wire subbytes_ready_o;
wire [127:0] subbytes_data_o;
wire [7:0] subbytes_sbox_data_o;
wire subbytes_sbox_decrypt_o;
wire [7:0] sbox_data_o;
reg [7:0] sbox_data_i;
reg sbox_decrypt_i;
reg state;
reg next_state;
reg [3:0] round;
reg [3:0] next_round;
reg [127:0] addroundkey_data_o;
reg [127:0] next_addroundkey_data_reg;
reg [127:0] addroundkey_data_reg;
reg [127:0] addroundkey_data_i;
reg addroundkey_ready_o;
reg next_addroundkey_ready_o;
reg addroundkey_start_i;
reg next_addroundkey_start_i;
reg [3:0] addroundkey_round;
reg [3:0] next_addroundkey_round;
reg first_round_reg;
reg next_first_round_reg;
sbox sbox1 (.clk(clk), .reset(reset), .data_i(sbox_data_i), .decrypt_i(sbox_decrypt_i), .data_o(sbox_data_o));
subbytes sub1 (.clk(clk), .reset(reset), .start_i(subbytes_start_i), .decrypt_i(decrypt_i), .data_i(subbytes_data_i), .ready_o(subbytes_ready_o), .data_o(subbytes_data_o), .sbox_data_o(subbytes_sbox_data_o), .sbox_data_i(sbox_data_o), .sbox_decrypt_o(subbytes_sbox_decrypt_o));
mixcolum mix1 (.clk(clk), .reset(reset), .decrypt_i(decrypt_i), .start_i(mixcol_start_i), .data_i(mixcol_data_i), .ready_o(mixcol_ready_o), .data_o(mixcol_data_o));
keysched ks1 (.clk(clk), .reset(reset), .start_i(keysched_start_i), .round_i(keysched_round_i), .last_key_i(keysched_last_key_i), .new_key_o(keysched_new_key_o), .ready_o(keysched_ready_o), .sbox_access_o(keysched_sbox_access_o), .sbox_data_o(keysched_sbox_data_o), .sbox_data_i(sbox_data_o), .sbox_decrypt_o(keysched_sbox_decrypt_o));
//registers:
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
state = (0);
ready_o = (0);
round = (0);
addroundkey_round = (0);
addroundkey_data_reg = (0);
addroundkey_ready_o = (0);
addroundkey_start_i = (0);
first_round_reg = (0);
end
else
begin
state = (next_state);
ready_o = (next_ready_o);
round = (next_round);
addroundkey_round = (next_addroundkey_round);
addroundkey_data_reg = (next_addroundkey_data_reg);
addroundkey_ready_o = (next_addroundkey_ready_o);
first_round_reg = (next_first_round_reg);
addroundkey_start_i = (next_addroundkey_start_i);
end
end
//control:
always @( state or round or addroundkey_data_o or data_i or load_i or decrypt_i or addroundkey_ready_o or mixcol_ready_o or subbytes_ready_o or subbytes_data_o or mixcol_data_o or first_round_reg)
begin
next_state = (state);
next_round = (round);
data_o = (addroundkey_data_o);
next_ready_o = (0);
//Tokeyschedulemodule
next_first_round_reg = (0);
subbytes_data_i = (0);
mixcol_data_i = (0);
addroundkey_data_i = (0);
next_addroundkey_start_i = (first_round_reg);
mixcol_start_i = ((addroundkey_ready_o&decrypt_i&round!=10)|(subbytes_ready_o&!decrypt_i));
subbytes_start_i = ((addroundkey_ready_o&!decrypt_i)|(mixcol_ready_o&decrypt_i)|(addroundkey_ready_o&decrypt_i&round==10));
if(decrypt_i&&round!=10)
begin
addroundkey_data_i = (subbytes_data_o);
subbytes_data_i = (mixcol_data_o);
mixcol_data_i = (addroundkey_data_o);
end
else if(!decrypt_i&&round!=0)
begin
addroundkey_data_i = (mixcol_data_o);
subbytes_data_i = (addroundkey_data_o);
mixcol_data_i = (subbytes_data_o);
end
else
begin
mixcol_data_i = (subbytes_data_o);
subbytes_data_i = (addroundkey_data_o);
addroundkey_data_i = (data_i);
end
case(state)
0:
begin
if(load_i)
begin
next_state = (1);
if(decrypt_i)
next_round = (10);
else
next_round = (0);
next_first_round_reg = (1);
end
end
1:
begin
//Counter
if(!decrypt_i&&mixcol_ready_o)
begin
next_addroundkey_start_i = (1);
addroundkey_data_i = (mixcol_data_o);
next_round = (round+1);
end
else if(decrypt_i&&subbytes_ready_o)
begin
next_addroundkey_start_i = (1);
addroundkey_data_i = (subbytes_data_o);
next_round = (round-1);
end
//Output
if((round==9&&!decrypt_i)||(round==0&&decrypt_i))
begin
next_addroundkey_start_i = (0);
mixcol_start_i = (0);
if(subbytes_ready_o)
begin
addroundkey_data_i = (subbytes_data_o);
next_addroundkey_start_i = (1);
next_round = (round+1);
end
end
if((round==10&&!decrypt_i)||(round==0&&decrypt_i))
begin
addroundkey_data_i = (subbytes_data_o);
subbytes_start_i = (0);
if(addroundkey_ready_o)
begin
next_ready_o = (1);
next_state = (0);
next_addroundkey_start_i = (0);
next_round = (0);
end
end
end
default:
begin
next_state = (0);
end
endcase
end
//addroundkey:
reg[127:0] data_var,round_data_var,round_key_var;
always @( addroundkey_data_i or addroundkey_start_i or addroundkey_data_reg or addroundkey_round or keysched_new_key_o or keysched_ready_o or key_i or round)
begin
round_data_var=addroundkey_data_reg;
next_addroundkey_data_reg = (addroundkey_data_reg);
next_addroundkey_ready_o = (0);
next_addroundkey_round = (addroundkey_round);
addroundkey_data_o = (addroundkey_data_reg);
if(addroundkey_round==1||addroundkey_round==0)
keysched_last_key_i = (key_i);
else
keysched_last_key_i = (keysched_new_key_o);
keysched_start_i = (0);
keysched_round_i = (addroundkey_round);
if(round==0&&addroundkey_start_i)
begin
//Taketheinputandxorthemwithdataifround==0;
data_var=addroundkey_data_i;
round_key_var=key_i;
round_data_var=round_key_var^data_var;
next_addroundkey_data_reg = (round_data_var);
next_addroundkey_ready_o = (1);
end
else if(addroundkey_start_i&&round!=0)
begin
keysched_last_key_i = (key_i);
keysched_start_i = (1);
keysched_round_i = (1);
next_addroundkey_round = (1);
end
else if(addroundkey_round!=round&&keysched_ready_o)
begin
next_addroundkey_round = (addroundkey_round+1);
keysched_last_key_i = (keysched_new_key_o);
keysched_start_i = (1);
keysched_round_i = (addroundkey_round+1);
end
else if(addroundkey_round==round&&keysched_ready_o)
begin
data_var=addroundkey_data_i;
round_key_var=keysched_new_key_o;
round_data_var=round_key_var^data_var;
next_addroundkey_data_reg = (round_data_var);
next_addroundkey_ready_o = (1);
next_addroundkey_round = (0);
end
end
//sbox_muxes:
always @( keysched_sbox_access_o or keysched_sbox_decrypt_o or keysched_sbox_data_o or subbytes_sbox_decrypt_o or subbytes_sbox_data_o)
begin
if(keysched_sbox_access_o)
begin
sbox_decrypt_i = (keysched_sbox_decrypt_o);
sbox_data_i = (keysched_sbox_data_o);
end
else
begin
sbox_decrypt_i = (subbytes_sbox_decrypt_o);
sbox_data_i = (subbytes_sbox_data_o);
end
end
endmodule |
module sbox(clk,reset,data_i,decrypt_i,data_o);
input clk;
input reset;
input [7:0] data_i;
input decrypt_i;
output [7:0] data_o;
reg [7:0] data_o;
reg [7:0] inva;
reg [3:0] ah;
reg [3:0] al;
reg [3:0] ah2;
reg [3:0] al2;
reg [3:0] alxh;
reg [3:0] alph;
reg [3:0] d;
reg [3:0] ahp;
reg [3:0] alp;
reg [3:0] to_invert;
reg [3:0] next_to_invert;
reg [3:0] ah_reg;
reg [3:0] next_ah_reg;
reg [3:0] next_alph;
//registers:
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
to_invert = (0);
ah_reg = (0);
alph = (0);
end
else
begin
to_invert = (next_to_invert);
ah_reg = (next_ah_reg);
alph = (next_alph);
end
end
//first_mux:
reg[7:0] first_mux_data_var;
reg[7:0] first_mux_InvInput;
reg[3:0] first_mux_ah_t,first_mux_al_t;
reg first_mux_aA,first_mux_aB,first_mux_aC,first_mux_aD;
always @( data_i or decrypt_i)
begin
first_mux_data_var=data_i;
first_mux_InvInput=first_mux_data_var;
case(decrypt_i)
1:
begin
//Applyinverseaffinetrasformation
first_mux_aA=first_mux_data_var[0]^first_mux_data_var[5];first_mux_aB=first_mux_data_var[1]^first_mux_data_var[4];
first_mux_aC=first_mux_data_var[2]^first_mux_data_var[7];first_mux_aD=first_mux_data_var[3]^first_mux_data_var[6];
first_mux_InvInput[0]=(!first_mux_data_var[5])^first_mux_aC;
first_mux_InvInput[1]=first_mux_data_var[0]^first_mux_aD;
first_mux_InvInput[2]=(!first_mux_data_var[7])^first_mux_aB;
first_mux_InvInput[3]=first_mux_data_var[2]^first_mux_aA;
first_mux_InvInput[4]=first_mux_data_var[1]^first_mux_aD;
first_mux_InvInput[5]=first_mux_data_var[4]^first_mux_aC;
first_mux_InvInput[6]=first_mux_data_var[3]^first_mux_aA;
first_mux_InvInput[7]=first_mux_data_var[6]^first_mux_aB;
end
default:
begin
first_mux_InvInput=first_mux_data_var;
end
endcase
//ConvertelementsfromGF(2^8)intotwoelementsofGF(2^4^2)
first_mux_aA=first_mux_InvInput[1]^first_mux_InvInput[7];
first_mux_aB=first_mux_InvInput[5]^first_mux_InvInput[7];
first_mux_aC=first_mux_InvInput[4]^first_mux_InvInput[6];
first_mux_al_t[0]=first_mux_aC^first_mux_InvInput[0]^first_mux_InvInput[5];
first_mux_al_t[1]=first_mux_InvInput[1]^first_mux_InvInput[2];
first_mux_al_t[2]=first_mux_aA;
first_mux_al_t[3]=first_mux_InvInput[2]^first_mux_InvInput[4];
first_mux_ah_t[0]=first_mux_aC^first_mux_InvInput[5];
first_mux_ah_t[1]=first_mux_aA^first_mux_aC;
first_mux_ah_t[2]=first_mux_aB^first_mux_InvInput[2]^first_mux_InvInput[3];
first_mux_ah_t[3]=first_mux_aB;
al = (first_mux_al_t);
ah = (first_mux_ah_t);
next_ah_reg = (first_mux_ah_t);
end
//end_mux:
reg[7:0] end_mux_data_var,end_mux_data_o_var;
reg end_mux_aA,end_mux_aB,end_mux_aC,end_mux_aD;
always @( decrypt_i or inva)
begin
//Taketheoutputoftheinverter
end_mux_data_var=inva;
case(decrypt_i)
0:
begin
//Applyaffinetrasformation
end_mux_aA=end_mux_data_var[0]^end_mux_data_var[1];end_mux_aB=end_mux_data_var[2]^end_mux_data_var[3];
end_mux_aC=end_mux_data_var[4]^end_mux_data_var[5];end_mux_aD=end_mux_data_var[6]^end_mux_data_var[7];
end_mux_data_o_var[0]=(!end_mux_data_var[0])^end_mux_aC^end_mux_aD;
end_mux_data_o_var[1]=(!end_mux_data_var[5])^end_mux_aA^end_mux_aD;
end_mux_data_o_var[2]=end_mux_data_var[2]^end_mux_aA^end_mux_aD;
end_mux_data_o_var[3]=end_mux_data_var[7]^end_mux_aA^end_mux_aB;
end_mux_data_o_var[4]=end_mux_data_var[4]^end_mux_aA^end_mux_aB;
end_mux_data_o_var[5]=(!end_mux_data_var[1])^end_mux_aB^end_mux_aC;
end_mux_data_o_var[6]=(!end_mux_data_var[6])^end_mux_aB^end_mux_aC;
end_mux_data_o_var[7]=end_mux_data_var[3]^end_mux_aC^end_mux_aD;
data_o = (end_mux_data_o_var);
end
default:
begin
data_o = (end_mux_data_var);
end
endcase
end
//inversemap:
reg[3:0] aA,aB;
reg[3:0] inversemap_alp_t,inversemap_ahp_t;
reg[7:0] inversemap_inva_t;
always @( alp or ahp)
begin
inversemap_alp_t=alp;
inversemap_ahp_t=ahp;
aA=inversemap_alp_t[1]^inversemap_ahp_t[3];
aB=inversemap_ahp_t[0]^inversemap_ahp_t[1];
inversemap_inva_t[0]=inversemap_alp_t[0]^inversemap_ahp_t[0];
inversemap_inva_t[1]=aB^inversemap_ahp_t[3];
inversemap_inva_t[2]=aA^aB;
inversemap_inva_t[3]=aB^inversemap_alp_t[1]^inversemap_ahp_t[2];
inversemap_inva_t[4]=aA^aB^inversemap_alp_t[3];
inversemap_inva_t[5]=aB^inversemap_alp_t[2];
inversemap_inva_t[6]=aA^inversemap_alp_t[2]^inversemap_alp_t[3]^inversemap_ahp_t[0];
inversemap_inva_t[7]=aB^inversemap_alp_t[2]^inversemap_ahp_t[3];
inva = (inversemap_inva_t);
end
//mul1:
reg[3:0] mul1_alxh_t;
reg[3:0] mul1_aA,mul1_a;
always @( ah or al)
begin
//alxah
mul1_aA=al[0]^al[3];
mul1_a=al[2]^al[3];
mul1_alxh_t[0]=(al[0]&ah[0])^(al[3]&ah[1])^(al[2]&ah[2])^(al[1]&ah[3]);
mul1_alxh_t[1]=(al[1]&ah[0])^(mul1_aA&ah[1])^(mul1_a&ah[2])^((al[1]^al[2])&ah[3]);
mul1_alxh_t[2]=(al[2]&ah[0])^(al[1]&ah[1])^(mul1_aA&ah[2])^(mul1_a&ah[3]);
mul1_alxh_t[3]=(al[3]&ah[0])^(al[2]&ah[1])^(al[1]&ah[2])^(mul1_aA&ah[3]);
alxh = (mul1_alxh_t);
end
//mul2:
reg[3:0] mul2_ahp_t;
reg[3:0] mul2_aA,mul2_aB;
always @( d or ah_reg)
begin
//ahxd
mul2_aA=ah_reg[0]^ah_reg[3];
mul2_aB=ah_reg[2]^ah_reg[3];
mul2_ahp_t[0]=(ah_reg[0]&d[0])^(ah_reg[3]&d[1])^(ah_reg[2]&d[2])^(ah_reg[1]&d[3]);
mul2_ahp_t[1]=(ah_reg[1]&d[0])^(mul2_aA&d[1])^(mul2_aB&d[2])^((ah_reg[1]^ah_reg[2])&d[3]);
mul2_ahp_t[2]=(ah_reg[2]&d[0])^(ah_reg[1]&d[1])^(mul2_aA&d[2])^(mul2_aB&d[3]);
mul2_ahp_t[3]=(ah_reg[3]&d[0])^(ah_reg[2]&d[1])^(ah_reg[1]&d[2])^(mul2_aA&d[3]);
ahp = (mul2_ahp_t);
end
//mul3:
reg[3:0] mul3_alp_t;
reg[3:0] mul3_aA,mul3_aB;
always @( d or alph)
begin
//dxal
mul3_aA=d[0]^d[3];
mul3_aB=d[2]^d[3];
mul3_alp_t[0]=(d[0]&alph[0])^(d[3]&alph[1])^(d[2]&alph[2])^(d[1]&alph[3]);
mul3_alp_t[1]=(d[1]&alph[0])^(mul3_aA&alph[1])^(mul3_aB&alph[2])^((d[1]^d[2])&alph[3]);
mul3_alp_t[2]=(d[2]&alph[0])^(d[1]&alph[1])^(mul3_aA&alph[2])^(mul3_aB&alph[3]);
mul3_alp_t[3]=(d[3]&alph[0])^(d[2]&alph[1])^(d[1]&alph[2])^(mul3_aA&alph[3]);
alp = (mul3_alp_t);
end
//intermediate:
reg[3:0] intermediate_aA,intermediate_aB;
reg[3:0] intermediate_ah2e,intermediate_ah2epl2,intermediate_to_invert_var;
always @( ah2 or al2 or alxh)
begin
//ahsquareismultipliedwithe
intermediate_aA=ah2[0]^ah2[1];
intermediate_aB=ah2[2]^ah2[3];
intermediate_ah2e[0]=ah2[1]^intermediate_aB;
intermediate_ah2e[1]=intermediate_aA;
intermediate_ah2e[2]=intermediate_aA^ah2[2];
intermediate_ah2e[3]=intermediate_aA^intermediate_aB;
//Additionofintermediate_ah2eplusal2
intermediate_ah2epl2[0]=intermediate_ah2e[0]^al2[0];
intermediate_ah2epl2[1]=intermediate_ah2e[1]^al2[1];
intermediate_ah2epl2[2]=intermediate_ah2e[2]^al2[2];
intermediate_ah2epl2[3]=intermediate_ah2e[3]^al2[3];
//Additionoflastresultwiththeresultof(alxah)
intermediate_to_invert_var[0]=intermediate_ah2epl2[0]^alxh[0];
intermediate_to_invert_var[1]=intermediate_ah2epl2[1]^alxh[1];
intermediate_to_invert_var[2]=intermediate_ah2epl2[2]^alxh[2];
intermediate_to_invert_var[3]=intermediate_ah2epl2[3]^alxh[3];
//Registers
next_to_invert = (intermediate_to_invert_var);
end
//inversion:
reg[3:0] inversion_to_invert_var;
reg[3:0] inversion_aA,inversion_d_t;
always @( to_invert)
begin
inversion_to_invert_var=to_invert;
//InverttheresultinGF(2^4)
inversion_aA=inversion_to_invert_var[1]^inversion_to_invert_var[2]^inversion_to_invert_var[3]^(inversion_to_invert_var[1]&inversion_to_invert_var[2]&inversion_to_invert_var[3]);
inversion_d_t[0]=inversion_aA^inversion_to_invert_var[0]^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^(inversion_to_invert_var[1]&inversion_to_invert_var[2])^(inversion_to_invert_var[0]&inversion_to_invert_var[1]&inversion_to_invert_var[2]);
inversion_d_t[1]=(inversion_to_invert_var[0]&inversion_to_invert_var[1])^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^(inversion_to_invert_var[1]&inversion_to_invert_var[2])^inversion_to_invert_var[3]^(inversion_to_invert_var[1]&inversion_to_invert_var[3])^(inversion_to_invert_var[0]&inversion_to_invert_var[1]&inversion_to_invert_var[3]);
inversion_d_t[2]=(inversion_to_invert_var[0]&inversion_to_invert_var[1])^inversion_to_invert_var[2]^(inversion_to_invert_var[0]&inversion_to_invert_var[2])^inversion_to_invert_var[3]^(inversion_to_invert_var[0]&inversion_to_invert_var[3])^(inversion_to_invert_var[0]&inversion_to_invert_var[2]&inversion_to_invert_var[3]);
inversion_d_t[3]=inversion_aA^(inversion_to_invert_var[0]&inversion_to_invert_var[3])^(inversion_to_invert_var[1]&inversion_to_invert_var[3])^(inversion_to_invert_var[2]&inversion_to_invert_var[3]);
d = (inversion_d_t);
end
//sum1:
reg[3:0] sum1_alph_t;
always @( ah or al)
begin
sum1_alph_t[0]=al[0]^ah[0];
sum1_alph_t[1]=al[1]^ah[1];
sum1_alph_t[2]=al[2]^ah[2];
sum1_alph_t[3]=al[3]^ah[3];
next_alph = (sum1_alph_t);
end
//square1:
reg[3:0] square1_ah_t;
always @( ah)
begin
square1_ah_t[0]=ah[0]^ah[2];
square1_ah_t[1]=ah[2];
square1_ah_t[2]=ah[1]^ah[3];
square1_ah_t[3]=ah[3];
ah2 = (square1_ah_t);
end
//square2:
reg[3:0] square2_al_t;
always @( al)
begin
square2_al_t[0]=al[0]^al[2];
square2_al_t[1]=al[2];
square2_al_t[2]=al[1]^al[3];
square2_al_t[3]=al[3];
al2 = (square2_al_t);
end
endmodule |
module mixcolum(clk,reset,decrypt_i,start_i,data_i,ready_o,data_o);
input clk;
input reset;
input decrypt_i;
input start_i;
input [127:0] data_i;
output ready_o;
output [127:0] data_o;
reg ready_o;
reg [127:0] data_o;
reg [127:0] data_reg;
reg [127:0] next_data_reg;
reg [127:0] data_o_reg;
reg [127:0] next_data_o;
reg next_ready_o;
reg [1:0] state;
reg [1:0] next_state;
wire [31:0] outx;
wire [31:0] outy;
reg [31:0] mix_word;
reg [31:0] outmux;
word_mixcolum w1 (.in(mix_word), .outx(outx), .outy(outy));
//assign_data_o:
always @( data_o_reg)
begin
data_o = (data_o_reg);
end
//mux:
always @( outx or outy or decrypt_i)
begin
outmux = (decrypt_i?outy:outx);
end
//registers:
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
data_reg = (0);
state = (0);
ready_o = (0);
data_o_reg = (0);
end
else
begin
data_reg = (next_data_reg);
state = (next_state);
ready_o = (next_ready_o);
data_o_reg = (next_data_o);
end
end
//mixcol:
reg[127:0] data_i_var;
reg[31:0] aux;
reg[127:0] data_reg_var;
always @( decrypt_i or start_i or state or data_reg or outmux or data_o_reg or data_i)
begin
data_i_var=data_i;
data_reg_var=data_reg;
next_data_reg = (data_reg);
next_state = (state);
mix_word = (0);
next_ready_o = (0);
next_data_o = (data_o_reg);
case(state)
0:
begin
if(start_i)
begin
aux=data_i_var[127:96];
mix_word = (aux);
data_reg_var[127:96]=outmux;
next_data_reg = (data_reg_var);
next_state = (1);
end
end
1:
begin
aux=data_i_var[95:64];
mix_word = (aux);
data_reg_var[95:64]=outmux;
next_data_reg = (data_reg_var);
next_state = (2);
end
2:
begin
aux=data_i_var[63:32];
mix_word = (aux);
data_reg_var[63:32]=outmux;
next_data_reg = (data_reg_var);
next_state = (3);
end
3:
begin
aux=data_i_var[31:0];
mix_word = (aux);
data_reg_var[31:0]=outmux;
next_data_o = (data_reg_var);
next_ready_o = (1);
next_state = (0);
end
default:
begin
end
endcase
end
endmodule |
module byte_mixcolum(a,b,c,d,outx,outy);
input [7:0] a,b,c,d;
output [7:0] outx, outy;
reg [7:0] outx, outy;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime[7:5] = in[6:4];
xtime_t[3] = in[7];
xtime_t[2] = in[7];
xtime_t[1] = 0;
xtime_t[0] = in[7];
xtime[4:1] =xtime_t^in[3:0];
xtime[0] = in[7];
end
endfunction
reg [7:0] w1,w2,w3,w4,w5,w6,w7,w8,outx_var;
always @ (a, b, c, d)
begin
w1 = a ^b;
w2 = a ^c;
w3 = c ^d;
w4 = xtime(w1);
w5 = xtime(w3);
w6 = w2 ^w4 ^w5;
w7 = xtime(w6);
w8 = xtime(w7);
outx_var = b^w3^w4;
outx=outx_var;
outy=w8^outx_var;
end
endmodule |
module subbytes(clk,reset,start_i,decrypt_i,data_i,ready_o,data_o,sbox_data_o,sbox_data_i,sbox_decrypt_o);
input clk;
input reset;
input start_i;
input decrypt_i;
input [127:0] data_i;
output ready_o;
output [127:0] data_o;
output [7:0] sbox_data_o;
input [7:0] sbox_data_i;
output sbox_decrypt_o;
reg ready_o;
reg [127:0] data_o;
reg [7:0] sbox_data_o;
reg sbox_decrypt_o;
reg [4:0] state;
reg [4:0] next_state;
reg [127:0] data_reg;
reg [127:0] next_data_reg;
reg next_ready_o;
`define assign_array_to_128 \
data_reg_128[127:120]=data_reg_var[0]; \
data_reg_128[119:112]=data_reg_var[1]; \
data_reg_128[111:104]=data_reg_var[2]; \
data_reg_128[103:96]=data_reg_var[3]; \
data_reg_128[95:88]=data_reg_var[4]; \
data_reg_128[87:80]=data_reg_var[5]; \
data_reg_128[79:72]=data_reg_var[6]; \
data_reg_128[71:64]=data_reg_var[7]; \
data_reg_128[63:56]=data_reg_var[8]; \
data_reg_128[55:48]=data_reg_var[9]; \
data_reg_128[47:40]=data_reg_var[10]; \
data_reg_128[39:32]=data_reg_var[11]; \
data_reg_128[31:24]=data_reg_var[12]; \
data_reg_128[23:16]=data_reg_var[13]; \
data_reg_128[15:8]=data_reg_var[14]; \
data_reg_128[7:0]=data_reg_var[15];
`define shift_array_to_128 \
data_reg_128[127:120]=data_reg_var[0]; \
data_reg_128[119:112]=data_reg_var[5]; \
data_reg_128[111:104]=data_reg_var[10]; \
data_reg_128[103:96]=data_reg_var[15]; \
data_reg_128[95:88]=data_reg_var[4]; \
data_reg_128[87:80]=data_reg_var[9]; \
data_reg_128[79:72]=data_reg_var[14]; \
data_reg_128[71:64]=data_reg_var[3]; \
data_reg_128[63:56]=data_reg_var[8]; \
data_reg_128[55:48]=data_reg_var[13]; \
data_reg_128[47:40]=data_reg_var[2]; \
data_reg_128[39:32]=data_reg_var[7]; \
data_reg_128[31:24]=data_reg_var[12]; \
data_reg_128[23:16]=data_reg_var[1]; \
data_reg_128[15:8]=data_reg_var[6]; \
data_reg_128[7:0]=data_reg_var[11];
`define invert_shift_array_to_128 \
data_reg_128[127:120]=data_reg_var[0]; \
data_reg_128[119:112]=data_reg_var[13]; \
data_reg_128[111:104]=data_reg_var[10]; \
data_reg_128[103:96]=data_reg_var[7]; \
data_reg_128[95:88]=data_reg_var[4]; \
data_reg_128[87:80]=data_reg_var[1]; \
data_reg_128[79:72]=data_reg_var[14]; \
data_reg_128[71:64]=data_reg_var[11]; \
data_reg_128[63:56]=data_reg_var[8]; \
data_reg_128[55:48]=data_reg_var[5]; \
data_reg_128[47:40]=data_reg_var[2]; \
data_reg_128[39:32]=data_reg_var[15]; \
data_reg_128[31:24]=data_reg_var[12]; \
data_reg_128[23:16]=data_reg_var[9]; \
data_reg_128[15:8]=data_reg_var[6]; \
data_reg_128[7:0]=data_reg_var[3];
//registers:
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
data_reg = (0);
state = (0);
ready_o = (0);
end
else
begin
data_reg = (next_data_reg);
state = (next_state);
ready_o = (next_ready_o);
end
end
//sub:
reg[127:0] data_i_var,data_reg_128;
reg[7:0] data_array[15:0],data_reg_var[15:0];
always @( decrypt_i or start_i or state or data_i or sbox_data_i or data_reg)
begin
data_i_var=data_i;
data_array[0]=data_i_var[127:120];
data_array[1]=data_i_var[119:112];
data_array[2]=data_i_var[111:104];
data_array[3]=data_i_var[103:96];
data_array[4]=data_i_var[95:88];
data_array[5]=data_i_var[87:80];
data_array[6]=data_i_var[79:72];
data_array[7]=data_i_var[71:64];
data_array[8]=data_i_var[63:56];
data_array[9]=data_i_var[55:48];
data_array[10]=data_i_var[47:40];
data_array[11]=data_i_var[39:32];
data_array[12]=data_i_var[31:24];
data_array[13]=data_i_var[23:16];
data_array[14]=data_i_var[15:8];
data_array[15]=data_i_var[7:0];
data_reg_var[0]=data_reg[127:120];
data_reg_var[1]=data_reg[119:112];
data_reg_var[2]=data_reg[111:104];
data_reg_var[3]=data_reg[103:96];
data_reg_var[4]=data_reg[95:88];
data_reg_var[5]=data_reg[87:80];
data_reg_var[6]=data_reg[79:72];
data_reg_var[7]=data_reg[71:64];
data_reg_var[8]=data_reg[63:56];
data_reg_var[9]=data_reg[55:48];
data_reg_var[10]=data_reg[47:40];
data_reg_var[11]=data_reg[39:32];
data_reg_var[12]=data_reg[31:24];
data_reg_var[13]=data_reg[23:16];
data_reg_var[14]=data_reg[15:8];
data_reg_var[15]=data_reg[7:0];
sbox_decrypt_o = (decrypt_i);
sbox_data_o = (0);
next_state = (state);
next_data_reg = (data_reg);
next_ready_o = (0);
data_o = (data_reg);
case(state)
0:
begin
if(start_i)
begin
sbox_data_o = (data_array[0]);
next_state = (1);
end
end
16:
begin
data_reg_var[15]=sbox_data_i;
//Makeshiftrowsstage
case(decrypt_i)
0:
begin
`shift_array_to_128
end
1:
begin
`invert_shift_array_to_128
end
endcase
next_data_reg = (data_reg_128);
next_ready_o = (1);
next_state = (0);
end
default:
begin
sbox_data_o = (data_array[state]);
data_reg_var[state-1]=sbox_data_i;
`assign_array_to_128
next_data_reg = (data_reg_128);
next_state = (state+1);
end
endcase
end
endmodule |
module word_mixcolum(in,outx,outy);
input [31:0] in;
output [31:0] outx;
output [31:0] outy;
reg [31:0] outx;
reg [31:0] outy;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
wire [7:0] x1;
wire [7:0] x2;
wire [7:0] x3;
wire [7:0] x4;
wire [7:0] y1;
wire [7:0] y2;
wire [7:0] y3;
wire [7:0] y4;
byte_mixcolum bm1 (.a(a), .b(b), .c(c), .d(d), .outx(x1), .outy(y1));
byte_mixcolum bm2 (.a(b), .b(c), .c(d), .d(a), .outx(x2), .outy(y2));
byte_mixcolum bm3 (.a(c), .b(d), .c(a), .d(b), .outx(x3), .outy(y3));
byte_mixcolum bm4 (.a(d), .b(a), .c(b), .d(c), .outx(x4), .outy(y4));
reg[31:0] in_var;
reg[31:0] outx_var,outy_var;
//split:
always @( in)
begin
in_var=in;
a = (in_var[31:24]);
b = (in_var[23:16]);
c = (in_var[15:8]);
d = (in_var[7:0]);
end
//mix:
always @( x1 or x2 or x3 or x4 or y1 or y2 or y3 or y4)
begin
outx_var[31:24]=x1;
outx_var[23:16]=x2;
outx_var[15:8]=x3;
outx_var[7:0]=x4;
outy_var[31:24]=y1;
outy_var[23:16]=y2;
outy_var[15:8]=y3;
outy_var[7:0]=y4;
outx = (outx_var);
outy = (outy_var);
end
endmodule |
module desround(clk,reset,iteration_i,decrypt_i,R_i,L_i,Key_i,R_o,L_o,Key_o,s1_o,s2_o,s3_o,s4_o,s5_o,s6_o,s7_o,s8_o,s1_i,s2_i,s3_i,s4_i,s5_i,s6_i,s7_i,s8_i);
input clk;
input reset;
input [3:0] iteration_i;
input decrypt_i;
input [31:0] R_i;
input [31:0] L_i;
input [55:0] Key_i;
output [31:0] R_o;
output [31:0] L_o;
output [55:0] Key_o;
output [5:0] s1_o;
output [5:0] s2_o;
output [5:0] s3_o;
output [5:0] s4_o;
output [5:0] s5_o;
output [5:0] s6_o;
output [5:0] s7_o;
output [5:0] s8_o;
input [3:0] s1_i;
input [3:0] s2_i;
input [3:0] s3_i;
input [3:0] s4_i;
input [3:0] s5_i;
input [3:0] s6_i;
input [3:0] s7_i;
input [3:0] s8_i;
reg [31:0] R_o;
reg [31:0] L_o;
reg [55:0] Key_o;
reg [5:0] s1_o;
reg [5:0] s2_o;
reg [5:0] s3_o;
reg [5:0] s4_o;
reg [5:0] s5_o;
reg [5:0] s6_o;
reg [5:0] s7_o;
reg [5:0] s8_o;
reg [55:0] previous_key;
reg [3:0] iteration;
reg decrypt;
wire [55:0] non_perm_key;
wire [47:0] new_key;
reg [31:0] next_R;
reg [31:0] expanRSig;
reg[47:0] expandedR;
reg[47:0] round_key;
reg[47:0] KER;
reg[31:0] R_i_var;
reg[31:0] Soutput;
reg[31:0] f;
key_gen kg1 (.previous_key(previous_key), .iteration(iteration), .decrypt(decrypt), .new_key(new_key), .non_perm_key(non_perm_key));
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
L_o = (0);
R_o = (0);
Key_o = (0);
end
else
begin
L_o = (R_i);
R_o = (next_R);
Key_o = (non_perm_key);
end
end
always @( R_i or L_i or Key_i or iteration_i or decrypt_i or new_key or s1_i or s2_i or s3_i or s4_i or s5_i or s6_i or s7_i or s8_i)
begin
R_i_var=R_i;
expandedR[47]=R_i_var[0]; expandedR[46]=R_i_var[31]; expandedR[45]=R_i_var[30]; expandedR[44]=R_i_var[29];
expandedR[43]=R_i_var[28]; expandedR[42]=R_i_var[27]; expandedR[41]=R_i_var[28]; expandedR[40]=R_i_var[27];
expandedR[39]=R_i_var[26]; expandedR[38]=R_i_var[25]; expandedR[37]=R_i_var[24]; expandedR[36]=R_i_var[23];
expandedR[35]=R_i_var[24]; expandedR[34]=R_i_var[23]; expandedR[33]=R_i_var[22]; expandedR[32]=R_i_var[21];
expandedR[31]=R_i_var[20]; expandedR[30]=R_i_var[19]; expandedR[29]=R_i_var[20]; expandedR[28]=R_i_var[19];
expandedR[27]=R_i_var[18]; expandedR[26]=R_i_var[17]; expandedR[25]=R_i_var[16]; expandedR[24]=R_i_var[15];
expandedR[23]=R_i_var[16]; expandedR[22]=R_i_var[15]; expandedR[21]=R_i_var[14]; expandedR[20]=R_i_var[13];
expandedR[19]=R_i_var[12]; expandedR[18]=R_i_var[11]; expandedR[17]=R_i_var[12]; expandedR[16]=R_i_var[11];
expandedR[15]=R_i_var[10]; expandedR[14]=R_i_var[9]; expandedR[13]=R_i_var[8]; expandedR[12]=R_i_var[7];
expandedR[11]=R_i_var[8]; expandedR[10]=R_i_var[7]; expandedR[9]=R_i_var[6]; expandedR[8]=R_i_var[5];
expandedR[7]=R_i_var[4]; expandedR[6]=R_i_var[3]; expandedR[5]=R_i_var[4]; expandedR[4]=R_i_var[3];
expandedR[3]=R_i_var[2]; expandedR[2]=R_i_var[1]; expandedR[1]=R_i_var[0]; expandedR[0]=R_i_var[31];
previous_key = (Key_i);
iteration = (iteration_i);
decrypt = (decrypt_i);
round_key=new_key;
KER=expandedR^round_key;
s1_o = (KER[47:42]);
s2_o = (KER[41:36]);
s3_o = (KER[35:30]);
s4_o = (KER[29:24]);
s5_o = (KER[23:18]);
s6_o = (KER[17:12]);
s7_o = (KER[11:6]);
s8_o = (KER[5:0]);
Soutput[31:28]=s1_i;
Soutput[27:24]=s2_i;
Soutput[23:20]=s3_i;
Soutput[19:16]=s4_i;
Soutput[15:12]=s5_i;
Soutput[11:8]=s6_i;
Soutput[7:4]=s7_i;
Soutput[3:0]=s8_i;
f[31]=Soutput[16]; f[30]=Soutput[25]; f[29]=Soutput[12]; f[28]=Soutput[11];
f[27]=Soutput[3]; f[26]=Soutput[20]; f[25]=Soutput[4]; f[24]=Soutput[15];
f[23]=Soutput[31]; f[22]=Soutput[17]; f[21]=Soutput[9]; f[20]=Soutput[6];
f[19]=Soutput[27]; f[18]=Soutput[14]; f[17]=Soutput[1]; f[16]=Soutput[22];
f[15]=Soutput[30]; f[14]=Soutput[24]; f[13]=Soutput[8]; f[12]=Soutput[18];
f[11]=Soutput[0]; f[10]=Soutput[5]; f[9]=Soutput[29]; f[8]=Soutput[23];
f[7]=Soutput[13]; f[6]=Soutput[19]; f[5]=Soutput[2]; f[4]=Soutput[26];
f[3]=Soutput[10]; f[2]=Soutput[21]; f[1]=Soutput[28]; f[0]=Soutput[7];
next_R = (L_i^f);
expanRSig = (L_i^f);
end
endmodule |
module des(clk,reset,load_i,decrypt_i,data_i,key_i,data_o,ready_o);
input clk;
input reset;
input load_i;
input decrypt_i;
input [63:0] data_i;
input [63:0] key_i;
output [63:0] data_o;
output ready_o;
reg [63:0] data_o;
reg ready_o;
reg [3:0] stage1_iter;
reg [3:0] next_stage1_iter;
reg next_ready_o;
reg[63:0] next_data_o;
reg data_ready;
reg next_data_ready;
reg [31:0] stage1_L_i;
reg [31:0] stage1_R_i;
reg [55:0] stage1_round_key_i;
reg [3:0] stage1_iteration_i;
wire [31:0] stage1_R_o;
wire [31:0] stage1_L_o;
wire [55:0] stage1_round_key_o;
wire [5:0] s1_stag1_i;
wire [5:0] s2_stag1_i;
wire [5:0] s3_stag1_i;
wire [5:0] s4_stag1_i;
wire [5:0] s5_stag1_i;
wire [5:0] s6_stag1_i;
wire [5:0] s7_stag1_i;
wire [5:0] s8_stag1_i;
wire [3:0] s1_stag1_o;
wire [3:0] s2_stag1_o;
wire [3:0] s3_stag1_o;
wire [3:0] s4_stag1_o;
wire [3:0] s5_stag1_o;
wire [3:0] s6_stag1_o;
wire [3:0] s7_stag1_o;
wire [3:0] s8_stag1_o;
reg[31:0] L_i_var,R_i_var;
reg[63:0] data_i_var,data_o_var,data_o_var_t,key_i_var;
reg[55:0] key_var_perm;
desround rd1 (.clk(clk), .reset(reset), .iteration_i(stage1_iteration_i), .decrypt_i(decrypt_i), .R_i(stage1_R_i), .L_i(stage1_L_i), .Key_i(stage1_round_key_i), .R_o(stage1_R_o), .L_o(stage1_L_o), .Key_o(stage1_round_key_o), .s1_o(s1_stag1_i), .s2_o(s2_stag1_i), .s3_o(s3_stag1_i), .s4_o(s4_stag1_i), .s5_o(s5_stag1_i), .s6_o(s6_stag1_i), .s7_o(s7_stag1_i), .s8_o(s8_stag1_i), .s1_i(s1_stag1_o), .s2_i(s2_stag1_o), .s3_i(s3_stag1_o), .s4_i(s4_stag1_o), .s5_i(s5_stag1_o), .s6_i(s6_stag1_o), .s7_i(s7_stag1_o), .s8_i(s8_stag1_o));
s1 sbox1 (.stage1_input(s1_stag1_i), .stage1_output(s1_stag1_o));
s2 sbox2 (.stage1_input(s2_stag1_i), .stage1_output(s2_stag1_o));
s3 sbox3 (.stage1_input(s3_stag1_i), .stage1_output(s3_stag1_o));
s4 sbox4 (.stage1_input(s4_stag1_i), .stage1_output(s4_stag1_o));
s5 sbox5 (.stage1_input(s5_stag1_i), .stage1_output(s5_stag1_o));
s6 sbox6 (.stage1_input(s6_stag1_i), .stage1_output(s6_stag1_o));
s7 sbox7 (.stage1_input(s7_stag1_i), .stage1_output(s7_stag1_o));
s8 sbox8 (.stage1_input(s8_stag1_i), .stage1_output(s8_stag1_o));
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
ready_o = (0);
data_o = (0);
stage1_iter = (0);
data_ready = (1);
end
else
begin
ready_o = (next_ready_o);
data_o = (next_data_o);
stage1_iter = (next_stage1_iter);
data_ready = (next_data_ready);
end
end
always @( data_i or key_i or load_i or stage1_iter or data_ready or stage1_R_o or stage1_L_o or stage1_round_key_o)
begin
L_i_var=0;
R_i_var=0;
data_i_var=0;
next_ready_o = (0);
next_data_ready = (data_ready);
next_stage1_iter = (stage1_iter);
stage1_L_i = (0);
stage1_R_i = (0);
stage1_round_key_i = (0);
key_i_var=key_i;
key_var_perm[55]=key_i_var[7];key_var_perm[54]=key_i_var[15];key_var_perm[53]=key_i_var[23];key_var_perm[52]=key_i_var[31];
key_var_perm[51]=key_i_var[39];key_var_perm[50]=key_i_var[47];key_var_perm[49]=key_i_var[55];key_var_perm[48]=key_i_var[63];
key_var_perm[47]=key_i_var[6];key_var_perm[46]=key_i_var[14];key_var_perm[45]=key_i_var[22];key_var_perm[44]=key_i_var[30];
key_var_perm[43]=key_i_var[38];key_var_perm[42]=key_i_var[46];key_var_perm[41]=key_i_var[54];key_var_perm[40]=key_i_var[62];
key_var_perm[39]=key_i_var[5];key_var_perm[38]=key_i_var[13];key_var_perm[37]=key_i_var[21];key_var_perm[36]=key_i_var[29];
key_var_perm[35]=key_i_var[37];key_var_perm[34]=key_i_var[45];key_var_perm[33]=key_i_var[53];key_var_perm[32]=key_i_var[61];
key_var_perm[31]=key_i_var[4];key_var_perm[30]=key_i_var[12];key_var_perm[29]=key_i_var[20];key_var_perm[28]=key_i_var[28];
key_var_perm[27]=key_i_var[1];key_var_perm[26]=key_i_var[9];key_var_perm[25]=key_i_var[17];key_var_perm[24]=key_i_var[25];
key_var_perm[23]=key_i_var[33];key_var_perm[22]=key_i_var[41];key_var_perm[21]=key_i_var[49];key_var_perm[20]=key_i_var[57];
key_var_perm[19]=key_i_var[2];key_var_perm[18]=key_i_var[10];key_var_perm[17]=key_i_var[18];key_var_perm[16]=key_i_var[26];
key_var_perm[15]=key_i_var[34];key_var_perm[14]=key_i_var[42];key_var_perm[13]=key_i_var[50];key_var_perm[12]=key_i_var[58];
key_var_perm[11]=key_i_var[3];key_var_perm[10]=key_i_var[11];key_var_perm[9]=key_i_var[19];key_var_perm[8]=key_i_var[27];
key_var_perm[7]=key_i_var[35];key_var_perm[6]=key_i_var[43];key_var_perm[5]=key_i_var[51];key_var_perm[4]=key_i_var[59];
key_var_perm[3]=key_i_var[36];key_var_perm[2]=key_i_var[44];key_var_perm[1]=key_i_var[52];key_var_perm[0]=key_i_var[60];
data_i_var=data_i;
L_i_var[31]=data_i_var[6];L_i_var[30]=data_i_var[14];L_i_var[29]=data_i_var[22];L_i_var[28]=data_i_var[30];
L_i_var[27]=data_i_var[38];L_i_var[26]=data_i_var[46];L_i_var[25]=data_i_var[54];L_i_var[24]=data_i_var[62];
L_i_var[23]=data_i_var[4];L_i_var[22]=data_i_var[12];L_i_var[21]=data_i_var[20];L_i_var[20]=data_i_var[28];
L_i_var[19]=data_i_var[36];L_i_var[18]=data_i_var[44];L_i_var[17]=data_i_var[52];L_i_var[16]=data_i_var[60];
L_i_var[15]=data_i_var[2];L_i_var[14]=data_i_var[10];L_i_var[13]=data_i_var[18];L_i_var[12]=data_i_var[26];
L_i_var[11]=data_i_var[34];L_i_var[10]=data_i_var[42];L_i_var[9]=data_i_var[50];L_i_var[8]=data_i_var[58];
L_i_var[7]=data_i_var[0];L_i_var[6]=data_i_var[8];L_i_var[5]=data_i_var[16];L_i_var[4]=data_i_var[24];
L_i_var[3]=data_i_var[32];L_i_var[2]=data_i_var[40];L_i_var[1]=data_i_var[48];L_i_var[0]=data_i_var[56];
R_i_var[31]=data_i_var[7];R_i_var[30]=data_i_var[15];R_i_var[29]=data_i_var[23];R_i_var[28]=data_i_var[31];
R_i_var[27]=data_i_var[39];R_i_var[26]=data_i_var[47];R_i_var[25]=data_i_var[55];R_i_var[24]=data_i_var[63];
R_i_var[23]=data_i_var[5];R_i_var[22]=data_i_var[13];R_i_var[21]=data_i_var[21];R_i_var[20]=data_i_var[29];
R_i_var[19]=data_i_var[37];R_i_var[18]=data_i_var[45];R_i_var[17]=data_i_var[53];R_i_var[16]=data_i_var[61];
R_i_var[15]=data_i_var[3];R_i_var[14]=data_i_var[11];R_i_var[13]=data_i_var[19];R_i_var[12]=data_i_var[27];
R_i_var[11]=data_i_var[35];R_i_var[10]=data_i_var[43];R_i_var[9]=data_i_var[51];R_i_var[8]=data_i_var[59];
R_i_var[7]=data_i_var[1];R_i_var[6]=data_i_var[9];R_i_var[5]=data_i_var[17];R_i_var[4]=data_i_var[25];
R_i_var[3]=data_i_var[33];R_i_var[2]=data_i_var[41];R_i_var[1]=data_i_var[49];R_i_var[0]=data_i_var[57];
data_o_var_t[63:32]=stage1_R_o;
data_o_var_t[31:0]=stage1_L_o;
data_o_var[63]=data_o_var_t[24];data_o_var[62]=data_o_var_t[56];data_o_var[61]=data_o_var_t[16];data_o_var[60]=data_o_var_t[48];
data_o_var[59]=data_o_var_t[8];data_o_var[58]=data_o_var_t[40];data_o_var[57]=data_o_var_t[0];data_o_var[56]=data_o_var_t[32];
data_o_var[55]=data_o_var_t[25];data_o_var[54]=data_o_var_t[57];data_o_var[53]=data_o_var_t[17];data_o_var[52]=data_o_var_t[49];
data_o_var[51]=data_o_var_t[9];data_o_var[50]=data_o_var_t[41];data_o_var[49]=data_o_var_t[1];data_o_var[48]=data_o_var_t[33];
data_o_var[47]=data_o_var_t[26];data_o_var[46]=data_o_var_t[58];data_o_var[45]=data_o_var_t[18];data_o_var[44]=data_o_var_t[50];
data_o_var[43]=data_o_var_t[10];data_o_var[42]=data_o_var_t[42];data_o_var[41]=data_o_var_t[2];data_o_var[40]=data_o_var_t[34];
data_o_var[39]=data_o_var_t[27];data_o_var[38]=data_o_var_t[59];data_o_var[37]=data_o_var_t[19];data_o_var[36]=data_o_var_t[51];
data_o_var[35]=data_o_var_t[11];data_o_var[34]=data_o_var_t[43];data_o_var[33]=data_o_var_t[3];data_o_var[32]=data_o_var_t[35];
data_o_var[31]=data_o_var_t[28];data_o_var[30]=data_o_var_t[60];data_o_var[29]=data_o_var_t[20];data_o_var[28]=data_o_var_t[52];
data_o_var[27]=data_o_var_t[12];data_o_var[26]=data_o_var_t[44];data_o_var[25]=data_o_var_t[4];data_o_var[24]=data_o_var_t[36];
data_o_var[23]=data_o_var_t[29];data_o_var[22]=data_o_var_t[61];data_o_var[21]=data_o_var_t[21];data_o_var[20]=data_o_var_t[53];
data_o_var[19]=data_o_var_t[13];data_o_var[18]=data_o_var_t[45];data_o_var[17]=data_o_var_t[5];data_o_var[16]=data_o_var_t[37];
data_o_var[15]=data_o_var_t[30];data_o_var[14]=data_o_var_t[62];data_o_var[13]=data_o_var_t[22];data_o_var[12]=data_o_var_t[54];
data_o_var[11]=data_o_var_t[14];data_o_var[10]=data_o_var_t[46];data_o_var[9]=data_o_var_t[6];data_o_var[8]=data_o_var_t[38];
data_o_var[7]=data_o_var_t[31];data_o_var[6]=data_o_var_t[63];data_o_var[5]=data_o_var_t[23];data_o_var[4]=data_o_var_t[55];
data_o_var[3]=data_o_var_t[15];data_o_var[2]=data_o_var_t[47];data_o_var[1]=data_o_var_t[7];data_o_var[0]=data_o_var_t[39];
next_data_o = (data_o_var);
stage1_iteration_i = (stage1_iter);
next_ready_o = (0);
stage1_L_i = (stage1_L_o);
stage1_R_i = (stage1_R_o);
stage1_round_key_i = (stage1_round_key_o);
case(stage1_iter)
0:
begin
if(load_i)
begin
next_stage1_iter = (1);
stage1_L_i = (L_i_var);
stage1_R_i = (R_i_var);
stage1_round_key_i = (key_var_perm);
next_data_ready = (0);
end
else if (!data_ready)
begin
next_stage1_iter = (0);
next_ready_o = (1);
next_data_ready = (1);
end
end
15:
next_stage1_iter = (0);
default:
next_stage1_iter = (stage1_iter+1);
endcase
end
endmodule |
module key_gen(previous_key,iteration,decrypt,non_perm_key,new_key);
input [55:0] previous_key;
input [3:0] iteration;
input decrypt;
output [55:0] non_perm_key;
output [47:0] new_key;
reg [55:0] non_perm_key;
reg [47:0] new_key;
reg prev0,prev1;
reg[55:0] prev_key_var,non_perm_key_var;
reg[47:0] new_key_var;
reg[27:0] semi_key;
always @( previous_key or iteration or decrypt)
begin
prev_key_var=previous_key;
new_key_var=0;
new_key = (0);
non_perm_key_var=0;
non_perm_key = (0);
if(!decrypt)
begin
case(iteration)
0, 1, 8, 15:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[27];
semi_key=semi_key<<1;
semi_key[0]=prev0;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[27];
semi_key=semi_key<<1;
semi_key[0]=prev0;
non_perm_key_var[27:0]=semi_key;
end
default:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[27];
prev1=semi_key[26];
semi_key=semi_key<<2;
semi_key[1]=prev0;
semi_key[0]=prev1;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[27];
prev1=semi_key[26];
semi_key=semi_key<<2;
semi_key[1]=prev0;
semi_key[0]=prev1;
non_perm_key_var[27:0]=semi_key;
end
endcase
end
else
begin
case(iteration)
0:
begin
semi_key=prev_key_var[55:28];
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
non_perm_key_var[27:0]=semi_key;
end
1, 8, 15:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[0];
semi_key=semi_key>>1;
semi_key[27]=prev0;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[0];
semi_key=semi_key>>1;
semi_key[27]=prev0;
non_perm_key_var[27:0]=semi_key;
end
default:
begin
semi_key=prev_key_var[55:28];
prev0=semi_key[0];
prev1=semi_key[1];
semi_key=semi_key>>2;
semi_key[26]=prev0;
semi_key[27]=prev1;
non_perm_key_var[55:28]=semi_key;
semi_key=prev_key_var[27:0];
prev0=semi_key[0];
prev1=semi_key[1];
semi_key=semi_key>>2;
semi_key[26]=prev0;
semi_key[27]=prev1;
non_perm_key_var[27:0]=semi_key;
end
endcase
end
non_perm_key = (non_perm_key_var);
new_key_var[47]=non_perm_key_var[42]; new_key_var[46]=non_perm_key_var[39]; new_key_var[45]=non_perm_key_var[45]; new_key_var[44]=non_perm_key_var[32];
new_key_var[43]=non_perm_key_var[55]; new_key_var[42]=non_perm_key_var[51]; new_key_var[41]=non_perm_key_var[53]; new_key_var[40]=non_perm_key_var[28];
new_key_var[39]=non_perm_key_var[41]; new_key_var[38]=non_perm_key_var[50]; new_key_var[37]=non_perm_key_var[35]; new_key_var[36]=non_perm_key_var[46];
new_key_var[35]=non_perm_key_var[33]; new_key_var[34]=non_perm_key_var[37]; new_key_var[33]=non_perm_key_var[44]; new_key_var[32]=non_perm_key_var[52];
new_key_var[31]=non_perm_key_var[30]; new_key_var[30]=non_perm_key_var[48]; new_key_var[29]=non_perm_key_var[40]; new_key_var[28]=non_perm_key_var[49];
new_key_var[27]=non_perm_key_var[29]; new_key_var[26]=non_perm_key_var[36]; new_key_var[25]=non_perm_key_var[43]; new_key_var[24]=non_perm_key_var[54];
new_key_var[23]=non_perm_key_var[15]; new_key_var[22]=non_perm_key_var[4]; new_key_var[21]=non_perm_key_var[25]; new_key_var[20]=non_perm_key_var[19];
new_key_var[19]=non_perm_key_var[9]; new_key_var[18]=non_perm_key_var[1]; new_key_var[17]=non_perm_key_var[26]; new_key_var[16]=non_perm_key_var[16];
new_key_var[15]=non_perm_key_var[5]; new_key_var[14]=non_perm_key_var[11]; new_key_var[13]=non_perm_key_var[23]; new_key_var[12]=non_perm_key_var[8];
new_key_var[11]=non_perm_key_var[12]; new_key_var[10]=non_perm_key_var[7]; new_key_var[9]=non_perm_key_var[17]; new_key_var[8]=non_perm_key_var[0];
new_key_var[7]=non_perm_key_var[22]; new_key_var[6]=non_perm_key_var[3]; new_key_var[5]=non_perm_key_var[10]; new_key_var[4]=non_perm_key_var[14];
new_key_var[3]=non_perm_key_var[6]; new_key_var[2]=non_perm_key_var[20]; new_key_var[1]=non_perm_key_var[27]; new_key_var[0]=non_perm_key_var[24];
new_key = (new_key_var);
end
endmodule |
module clk_on_lut(a, b, q, out, clk);
input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;
always @(posedge clk) begin
q <= a;
end
assign out = b & clk;
endmodule |
module rst_on_lut_8bit(a, b0, b1, b2, b3, b4, b5, b6, b7, q, out0, out1, out2, out3, out4, out5, out6, out7, clk, rst);
input wire rst;
input wire clk;
input wire a;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
input wire b4;
input wire b5;
input wire b6;
input wire b7;
output reg q;
output wire out0;
output wire out1;
output wire out2;
output wire out3;
output wire out4;
output wire out5;
output wire out6;
output wire out7;
always @(posedge rst or posedge clk) begin
if (rst) begin
q <= 0;
end else begin
q <= a;
end
end
assign out0 = b0 & ~rst;
assign out1 = b1 & ~rst;
assign out2 = b2 & ~rst;
assign out3 = b3 & ~rst;
assign out4 = b4 & ~rst;
assign out5 = b5 & ~rst;
assign out6 = b6 & ~rst;
assign out7 = b7 & ~rst;
endmodule |
module rst_on_lut_4bit(a, b0, b1, b2, b3, q, out0, out1, out2, out3, clk, rst);
input wire rst;
input wire clk;
input wire a;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
output reg q;
output wire out0;
output wire out1;
output wire out2;
output wire out3;
always @(posedge rst or posedge clk) begin
if (rst) begin
q <= 0;
end else begin
q <= a;
end
end
assign out0 = b0 & ~rst;
assign out1 = b1 & ~rst;
assign out2 = b2 & ~rst;
assign out3 = b3 & ~rst;
endmodule |
module and4(
a,
b,
c,
d,
e);
input wire a;
input wire b;
input wire c;
input wire d;
output wire e;
assign e = a & b & c & d;
endmodule |
module pipelined_8bit_adder(
input clk,
input ren,
input wen,
input raddr_0_,
input raddr_1_,
input raddr_2_,
input raddr_3_,
input raddr_4_,
input raddr_5_,
input waddr_0_,
input waddr_1_,
input waddr_2_,
input waddr_3_,
input waddr_4_,
input waddr_5_,
input a_0_,
input a_1_,
input a_2_,
input a_3_,
input a_4_,
input a_5_,
input a_6_,
input b_0_,
input b_1_,
input b_2_,
input b_3_,
input b_4_,
input b_5_,
input b_6_,
output q_0_,
output q_1_,
output q_2_,
output q_3_,
output q_4_,
output q_5_,
output q_6_,
output q_7_);
wire [5:0] raddr;
wire [5:0] waddr;
wire [6:0] a;
wire [6:0] b;
wire [7:0] q;
assign raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
assign waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
assign a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
assign b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
assign q_7_ = q[7];
assign q_6_ = q[6];
assign q_5_ = q[5];
assign q_4_ = q[4];
assign q_3_ = q[3];
assign q_2_ = q[2];
assign q_1_ = q[1];
assign q_0_ = q[0];
reg[7:0] ram[63:0];
reg[6:0] a_st0;
reg[6:0] a_st1;
reg[6:0] b_st0;
reg[6:0] b_st1;
reg[8:0] waddr_st0;
reg[8:0] waddr_st1;
reg wen_st0;
reg wen_st1;
reg[7:0] q_int;
wire[7:0] AplusB;
assign AplusB = a_st1 + b_st1;
assign q = q_int;
always@(posedge clk) begin
waddr_st0 <= waddr;
waddr_st1 <= waddr_st0;
a_st0 <= a;
a_st1 <= a_st0;
b_st0 <= b;
b_st1 <= b_st0;
wen_st0 <= wen;
wen_st1 <= wen_st0;
if(wen_st1) begin
ram[waddr_st1] <= AplusB;
end
if(ren) begin
q_int <= ram[raddr];
end
end
endmodule |
module pipelined_8bit_adder_top_formal_verification_random_tb();
reg clk;
reg[5:0] raddr;
reg[5:0] waddr;
reg ren;
reg wen;
reg[6:0] a;
reg[6:0] b;
wire[7:0] q_gfpga;
wire[7:0] q_bench;
reg[7:0] q_flag;
pipelined_8bit_adder_top_formal_verification DUT(
.clk_fm (clk),
.ren_fm (ren),
.wen_fm (wen),
.raddr_0__fm (raddr[0]),
.raddr_1__fm (raddr[1]),
.raddr_2__fm (raddr[2]),
.raddr_3__fm (raddr[3]),
.raddr_4__fm (raddr[4]),
.raddr_5__fm (raddr[5]),
.waddr_0__fm (waddr[0]),
.waddr_1__fm (waddr[1]),
.waddr_2__fm (waddr[2]),
.waddr_3__fm (waddr[3]),
.waddr_4__fm (waddr[4]),
.waddr_5__fm (waddr[5]),
.a_0__fm (a[0]),
.a_1__fm (a[1]),
.a_2__fm (a[2]),
.a_3__fm (a[3]),
.a_4__fm (a[4]),
.a_5__fm (a[5]),
.a_6__fm (a[6]),
.b_0__fm (b[0]),
.b_1__fm (b[1]),
.b_2__fm (b[2]),
.b_3__fm (b[3]),
.b_4__fm (b[4]),
.b_5__fm (b[5]),
.b_6__fm (b[6]),
.out_q_0__fm (q_gfpga[0]),
.out_q_1__fm (q_gfpga[1]),
.out_q_2__fm (q_gfpga[2]),
.out_q_3__fm (q_gfpga[3]),
.out_q_4__fm (q_gfpga[4]),
.out_q_5__fm (q_gfpga[5]),
.out_q_6__fm (q_gfpga[6]),
.out_q_7__fm (q_gfpga[7])
);
pipelined_8bit_adder ref0(
.clk (clk),
.ren (ren),
.wen (wen),
.raddr_0_ (raddr[0]),
.raddr_1_ (raddr[1]),
.raddr_2_ (raddr[2]),
.raddr_3_ (raddr[3]),
.raddr_4_ (raddr[4]),
.raddr_5_ (raddr[5]),
.waddr_0_ (waddr[0]),
.waddr_1_ (waddr[1]),
.waddr_2_ (waddr[2]),
.waddr_3_ (waddr[3]),
.waddr_4_ (waddr[4]),
.waddr_5_ (waddr[5]),
.a_0_ (a[0]),
.a_1_ (a[1]),
.a_2_ (a[2]),
.a_3_ (a[3]),
.a_4_ (a[4]),
.a_5_ (a[5]),
.a_6_ (a[6]),
.b_0_ (b[0]),
.b_1_ (b[1]),
.b_2_ (b[2]),
.b_3_ (b[3]),
.b_4_ (b[4]),
.b_5_ (b[5]),
.b_6_ (b[6]),
.q_0_ (q_bench[0]),
.q_1_ (q_bench[1]),
.q_2_ (q_bench[2]),
.q_3_ (q_bench[3]),
.q_4_ (q_bench[4]),
.q_5_ (q_bench[5]),
.q_6_ (q_bench[6]),
.q_7_ (q_bench[7])
);
integer nb_error = 0;
integer count = 0;
integer lim_max = 64 - 1;
integer write_complete = 0;
//----- Initialization
initial begin
clk <= 1'b0;
a <= 7'h00;
b <= 7'h00;
wen <= 1'b0;
ren <= 1'b0;
waddr <= 6'h00;
raddr <= 6'h00;
while(1) begin
#2.5
clk <= !clk;
end
end
//----- Input Stimulis
always@(negedge clk) begin
if(write_complete == 0) begin
wen <= 1'b1;
ren <= 1'b0;
count <= count + 1;
waddr <= waddr + 1;
if(count == lim_max) begin
write_complete = 1;
end
end else begin
wen <= $random;
ren <= $random;
waddr <= $random;
raddr <= $random;
end
a <= $random;
b <= $random;
end
always@(negedge clk) begin
if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
q_flag[0] <= 1'b1;
end else begin
q_flag[0] <= 1'b0;
end
if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
q_flag[1] <= 1'b1;
end else begin
q_flag[1] <= 1'b0;
end
if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
q_flag[2] <= 1'b1;
end else begin
q_flag[2] <= 1'b0;
end
if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
q_flag[3] <= 1'b1;
end else begin
q_flag[3] <= 1'b0;
end
if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
q_flag[4] <= 1'b1;
end else begin
q_flag[4] <= 1'b0;
end
if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
q_flag[5] <= 1'b1;
end else begin
q_flag[5] <= 1'b0;
end
if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
q_flag[6] <= 1'b1;
end else begin
q_flag[6] <= 1'b0;
end
if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
q_flag[7] <= 1'b1;
end else begin
q_flag[7] <= 1'b0;
end
end
always@(posedge q_flag[0]) begin
if(q_flag[0]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[0] at time = %t", $realtime);
end
end
always@(posedge q_flag[1]) begin
if(q_flag[1]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[1] at time = %t", $realtime);
end
end
always@(posedge q_flag[2]) begin
if(q_flag[2]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[2] at time = %t", $realtime);
end
end
always@(posedge q_flag[3]) begin
if(q_flag[3]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[3] at time = %t", $realtime);
end
end
always@(posedge q_flag[4]) begin
if(q_flag[4]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[4] at time = %t", $realtime);
end
end
always@(posedge q_flag[5]) begin
if(q_flag[5]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[5] at time = %t", $realtime);
end
end
always@(posedge q_flag[6]) begin
if(q_flag[6]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[6] at time = %t", $realtime);
end
end
always@(posedge q_flag[7]) begin
if(q_flag[7]) begin
nb_error = nb_error + 1;
$display("Mismatch on q_gfpga[7] at time = %t", $realtime);
end
end
initial begin
$dumpfile("pipelined_8bit_adder_formal.vcd");
$dumpvars(1, pipelined_8bit_adder_top_formal_verification_random_tb);
end
initial begin
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
#1500 // Can be changed by the user for his need
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule |
module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst);
input wire rst;
input wire clk;
input wire a;
input wire b;
input wire c;
output reg q;
output wire out0;
output wire out1;
always @(posedge rst or posedge clk) begin
if (rst) begin
q <= 0;
end else begin
q <= a;
end
end
assign out0 = b & ~rst;
assign out1 = c & ~clk;
endmodule |
module clk_cond(clk_i, clk_cond_i, d_i, q_o);
input wire clk_cond_i;
input wire clk_i;
input wire d_i;
output reg q_o;
wire int_clk;
assign int_clk = clk_cond_i & clk_i;
always @(posedge int_clk) begin
q_o <= d_i;
end
endmodule |
module dual_port_ram_16k (
input clk,
input wen,
input ren,
input [10:0] waddr,
input [10:0] raddr,
input [7:0] din,
output [7:0] dout
);
dual_port_sram_16kb memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (din),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (dout) );
endmodule |
module dual_port_sram_16kb (
input wclk,
input wen,
input [10:0] waddr,
input [7:0] data_in,
input rclk,
input ren,
input [10:0] raddr,
output [7:0] data_out
);
reg [7:0] ram[2047:0];
reg [7:0] internal;
assign data_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule |
module asyn_spram_4x1(
clk,
addr_0,
addr_1,
d_in,
wr_en,
d_out );
input wire clk;
input wire addr_0;
input wire addr_1;
input wire d_in;
input wire wr_en;
output wire d_out;
wire[1:0] addr;
reg [3:0] mem;
assign addr = {addr_1, addr_0};
assign d_out = (addr == 2'd0)? mem[0]:
(addr == 2'd1)? mem[1]:
(addr == 2'd2)? mem[2]: mem[3];
always@(posedge clk) begin
if(wr_en) begin
mem[addr] <= d_in;
end
end
endmodule |
module discrete_dffn(
clk_ni,
d_i,
d_o);
input wire clk_ni;
input wire d_i;
output reg d_o;
wire int_clk;
assign int_clk = ~clk_ni;
always @(posedge int_clk) begin
d_o <= d_i;
end
endmodule |
module configuration_manager(
input clk_in,
output prog_reset,
output prog_clk,
output ccff_head,
output configuration_done
);
parameter START_CYCLE=3; // Start configuration on cycle 3 of prog_clk
parameter CONFIGURATION_CLK_DIV_SIZE=12; // Divide clk_in (50MHz) by 4096 (2^12) times
wire prog_clk_out; // prog_clk signal from clk_divider
wire ccff_head_out;
assign ccff_head = ccff_head_out & ~prog_reset;
assign prog_clk = prog_clk_out & ~configuration_done; // prog_clk will stop when configuration done
// PRESET
// Programming reset will be enabled until START_CYCLE
reset_generator #(
.INITIAL_VALUE(1),
.ACTIVE_CYCLES(START_CYCLE)
) prog_reset_generator(
.clk(~prog_clk),
.pulse(prog_reset)
);
// PROG_CLK
// Divide pl_clk (50MHz) by 4096 (2^12) times
clock_divider #(
.CLK_DIVIDER_SIZE(CONFIGURATION_CLK_DIV_SIZE)
) prog_clk_divider (
.clk_in(clk_in),
.clk_out(prog_clk_out)
);
// Instantiate bitstream loader
bitstream_loader loader (
.prog_clk(prog_clk),
.config_chain_head(ccff_head_out),
.start(~prog_reset),
.done(configuration_done)
);
endmodule |
module test_mode_low (
a,
b,
clk,
reset,
out );
input wire a;
input wire b;
input wire clk;
input wire reset;
output wire[3:0] out;
reg[1:0] pipe_a;
reg[1:0] pipe_b;
reg[3:0] pipe_sum;
wire[7:0] sum;
assign sum[1:0] = pipe_a[1] + pipe_b[1] + pipe_sum[3];
assign sum[3:2] = pipe_sum[0] + sum[1] + pipe_sum[2];
assign sum[5:4] = pipe_sum[1] + sum[3] + pipe_sum[3];
assign sum[7:6] = pipe_sum[2] + sum[5] + pipe_sum[0];
assign out = pipe_sum;
initial begin
pipe_a <= 2'b00;
pipe_b <= 2'b00;
pipe_sum <= 4'b0000;
end
always @(posedge clk or posedge reset) begin
if(reset) begin
pipe_a <= 2'b00;
pipe_b <= 2'b00;
pipe_sum <= 4'b0000;
end else begin
pipe_a[0] <= a;
pipe_a[1] <= pipe_a[0];
pipe_b[0] <= b;
pipe_b[1] <= pipe_b[0];
pipe_sum <= {sum[6], sum[4], sum[2], sum[0]};
end
end
endmodule |
module clk_divider(clk_i, clk_o);
input wire clk_i;
output reg clk_o;
reg int_clk;
initial begin
clk_o <= 0;
int_clk <= 0;
end
always @(posedge clk_i) begin
int_clk <= ~int_clk;
end
always @(posedge int_clk) begin
clk_o <= ~clk_o;
end
endmodule |
module syn_spram_4x1(
clk,
addr_0,
addr_1,
d_in,
wr_en,
d_out );
input wire clk;
input wire addr_0;
input wire addr_1;
input wire d_in;
input wire wr_en;
output reg d_out;
wire[1:0] addr;
wire tmp;
reg [3:0] mem;
assign addr = {addr_1, addr_0};
assign tmp = (addr == 2'd0)? mem[0]:
(addr == 2'd1)? mem[1]:
(addr == 2'd2)? mem[2]: mem[3];
always@(posedge clk) begin
if(wr_en) begin
mem[addr] <= d_in;
end
d_out <= tmp;
end
endmodule |
module dual_port_ram_1k (
input clk,
input wen,
input ren,
input [6:0] waddr,
input [6:0] raddr,
input [7:0] din,
output [7:0] dout
);
dual_port_sram_1kb memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (din),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (dout) );
endmodule |
module clk_gate(
rst_i,
clk_i,
data_i,
data_o);
input wire rst_i;
input wire clk_i;
input wire data_i;
output wire data_o;
reg q;
always @(posedge clk_i) begin
if (rst_i) begin
q <= 0;
end else begin
q <= 1;
end
end
assign data_o = data_i & q;
endmodule |
module FSM_minute(
input wire rst,
input wire clk,
input wire [5:0] min_in,
input wire min_in_load,
input wire [5:0] sec_count,
output reg [5:0] min_out);
reg [2:0] ps, ns;
wire [5:0] min_data_add;
reg [5:0] min_data;
reg [5:0] min_ps, min_ns;
reg [1:0] min_sel;
wire min_count;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) min_ps <= 6'd0;
else min_ps <= min_ns;
end
always@(*)
begin
min_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(min_in_load) begin
min_sel = 2'd1;
min_out = min_data;
ns = 3'd2;
min_ns = min_data;
end
else ns = 3'd1;
end
3'd2: begin
if(min_count == 1'd1) begin
if(min_data == 6'd59) begin
min_out = min_data;
ns = 3'd2;
min_ns = 6'd0;
end
else begin
min_out = min_data;
ns = 3'd2;
min_ns = min_data_add;
end
end
else begin
min_out = min_data;
min_ns = min_data;
ns = 3'd2;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign min_data_add = min_data + 1;
assign min_count = (sec_count == 6'd59) ? 1'd1 : 1'd0;
always@(*)
begin
case(min_sel)
2'd0: min_data = min_ps;
2'd1: min_data = min_in;
endcase
end
endmodule |
module FSM_top(
input wire rst,
input wire clk,
input wire load_in,
input wire [5:0] sec_in,
input wire [5:0] min_in,
input wire [5:0] hour_in,
output wire [5:0] sec_out,
output wire [5:0] min_out,
output wire [5:0] hour_out
);
FSM_second FSM_sec(
.rst(rst),
.clk(clk),
.sec_in(sec_in),
.sec_in_load(load_in),
.sec_out(sec_out));
FSM_minute FSM_min(
.rst(rst),
.clk(clk),
.min_in(min_in),
.min_in_load(load_in),
.sec_count(sec_out),
.min_out(min_out));
FSM_hour FSM_hr(
.rst(rst),
.clk(clk),
.hour_in(hour_in),
.hour_in_load(load_in),
.min_count(min_out),
.hour_out(hour_out),
.sec_count(sec_out));
endmodule |
module FSM_hour(
input wire rst,
input wire clk,
input wire [5:0] hour_in,
input wire hour_in_load,
input wire [5:0] min_count,
input wire [5:0] sec_count,
output reg [5:0] hour_out);
reg [2:0] ps, ns;
wire [5:0] hour_data_add;
reg [5:0] hour_data;
reg [5:0] hour_ps, hour_ns;
reg [1:0] hour_sel;
wire hour_count;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) hour_ps <= 6'd0;
else hour_ps <= hour_ns;
end
always@(*)
begin
hour_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(hour_in_load) begin
hour_sel = 2'd1;
hour_out = hour_data;
ns = 3'd2;
hour_ns = hour_data;
end
else ns = 3'd1;
end
3'd2: begin
if(hour_count == 1'd1) begin
if(hour_data == 6'd59) begin
hour_out = hour_data;
ns = 3'd2;
hour_ns = 6'd0;
end
else begin
hour_out = hour_data;
ns = 3'd2;
hour_ns = hour_data_add;
end
end
else begin
hour_out = hour_data;
hour_ns = hour_data;
ns = 3'd2;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign hour_data_add = hour_data + 1;
assign hour_count = ((sec_count == 6'd59)&&(min_count == 6'd59)) ? 1'd1 : 1'd0;
always@(*)
begin
case(hour_sel)
2'd0: hour_data = hour_ps;
2'd1: hour_data = hour_in;
endcase
end
endmodule |
module FSM_second(
input wire rst,
input wire clk,
input wire [5:0] sec_in,
input wire sec_in_load,
output reg [5:0] sec_out);
reg [2:0] ps, ns;
wire [5:0] sec_data_add;
reg [5:0] sec_data;
reg [5:0] sec_ps, sec_ns;
reg [1:0] sec_sel;
always@(posedge clk)
begin
if(rst) ps <= 3'd0;
else ps <= ns;
end
always@(posedge clk)
begin
if(rst) sec_ps <= 6'd0;
else sec_ps <= sec_ns;
end
always@(*)
begin
sec_sel = 2'd0;
case(ps)
3'd0: begin
ns = 3'd1;
end
3'd1: begin
if(sec_in_load) begin
sec_sel = 2'd1;
sec_out = sec_data;
ns = 3'd2;
sec_ns = sec_data_add;
end
else ns = 3'd1;
end
3'd2: begin
if(sec_data == 6'd59) begin
sec_out = sec_data;
ns = 3'd2;
sec_ns = 6'd0;
end
else begin
sec_out = sec_data;
ns = 3'd2;
sec_ns = sec_data_add;
end
end
default: begin
ns = 3'd0;
end
endcase
end
assign sec_data_add = sec_data + 1;
always@(*)
begin
case(sec_sel)
2'd0: sec_data = sec_ps;
2'd1: sec_data = sec_in;
endcase
end
endmodule |
module FSM_three_tb;
reg rst;
reg clk;
reg [5:0] sec_in, min_in, hour_in;
reg load_in;
wire [5:0] sec_out, min_out, hour_out;
FSM_top FSM_1(
.rst(rst),
.clk(clk),
.sec_in(sec_in),
.load_in(load_in),
.sec_out(sec_out),
.min_in(min_in),
.min_out(min_out),
.hour_in(hour_in),
.hour_out(hour_out));
initial begin
#0 rst = 1'd1; clk = 1'd0; load_in = 1'd1; sec_in = 6'd33; min_in = 6'd14; hour_in = 6'd5;
#100 rst = 1'd0;
#50 load_in = 1'd0;
end
always begin
#10 clk = ~clk;
end
initial begin
#100000 $stop;
end
endmodule |
module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);
input wire rst_cond_i;
input wire rst_i;
input wire clk_i;
input wire d_i;
output reg q_o;
wire int_rst;
assign int_rst = rst_cond_i & rst_i;
always @(posedge int_rst or posedge clk_i) begin
if (int_rst) begin
q_o <= 0;
end else begin
q_o <= d_i;
end
end
endmodule |
module and2_pipelined(
clk,
a,
b,
c);
input wire clk;
input wire a;
input wire b;
output wire c;
reg a_reg;
reg b_reg;
reg c_reg;
always @(posedge clk) begin
a_reg <= a;
b_reg <= b;
end
always @(posedge clk) begin
c_reg <= a_reg & b_reg;
end
assign c = c_reg;
endmodule |
module or2(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a | b;
endmodule |
module and2_latch_2clock(
a0,
b0,
clk0,
a1,
b1,
clk1,
c0,
d0,
c1,
d1);
input wire clk0;
input wire a0;
input wire b0;
output wire c0;
output reg d0;
input wire clk1;
input wire a1;
input wire b1;
output wire c1;
output reg d1;
assign c0 = a0 & b0;
always @(posedge clk0) begin
d0 <= c0;
end
assign c1 = a1 & b1;
always @(posedge clk1) begin
d1 <= c1;
end
endmodule |
module rst_on_lut(a, b, q, out, clk, rst);
input wire rst;
input wire clk;
input wire a;
input wire b;
output reg q;
output wire out;
always @(posedge rst or posedge clk) begin
if (rst) begin
q <= 0;
end else begin
q <= a;
end
end
assign out = b & ~rst;
endmodule |
module pulse_generator(
input clk_in,
input repeated, // Specify if the pulse should be generated repeatedly
output reg pulse
);
parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
parameter WAIT_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
parameter PULSE_WIDTH=1; // Define the length of the pulse width
parameter PULSE_COUNTER_SIZE=10; // Define the size of the pulse width counter
reg [WAIT_CYCLES<=2 ? 2 : $clog2(WAIT_CYCLES) : 0] wait_cycle_counter; // Size of wait counter is determined by WAIT_CYCLES
reg [PULSE_COUNTER_SIZE - 1 : 0] pulse_width_counter;
reg pulse_start;
reg pulse_end;
`ifdef VIVADO_SYNTHESIS
initial begin
pulse <= INITIAL_VALUE;
pulse_start <= 1'b0;
pulse_end <= 1'b0;
wait_cycle_counter <= 0;
pulse_width_counter <= 0;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin
if (wait_cycle_counter == WAIT_CYCLES) begin
pulse_start <= 1'b1;
end
if (~pulse_start) begin
wait_cycle_counter <= wait_cycle_counter + 1;
end
end
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin
pulse <= INITIAL_VALUE;
if (pulse_start && ~pulse_end) begin
// Reach the pulse width limit, stop counting
if (pulse_width_counter < PULSE_WIDTH) begin
pulse <= ~INITIAL_VALUE;
if (~repeated) begin
pulse_end = 1'b1;
end
end
// When pulse ends, flip to initial value
if (pulse_end) begin
pulse <= INITIAL_VALUE;
end
pulse_width_counter <= pulse_width_counter + 1;
end
end
endmodule |
module reset_generator(
input clk,
output reg pulse
);
parameter INITIAL_VALUE=0; // Define the initial value for the pulse, either 0 or 1; The pulse logic level will be a flip over the initial value
parameter ACTIVE_CYCLES=0; // Define the number of clock cycles to wait before the pulse is applied
reg [ACTIVE_CYCLES<=2 ? 2 : $clog2(ACTIVE_CYCLES) - 1 : 0] active_cycle_counter;
`ifdef VIVADO_SYNTHESIS
initial begin
clkdiv_counter <= 0;
active_cycle_counter <= 0;
pulse <= INITIAL_VALUE;
end
`endif
// Wait a number of clock cycles, hold the initial value
always @(posedge clk) begin
if (active_cycle_counter == ACTIVE_CYCLES) begin
pulse <= ~pulse;
end else begin
active_cycle_counter <= active_cycle_counter + 1;
end
end
endmodule |
module clock_divider (
input clk_in,
output reg clk_out
);
parameter CLK_DIVIDER_SIZE=8;
reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
`ifdef VIVADO_SYNTHESIS
initial begin
clkdiv_counter <= 0;
clk_out <= 0;
end
`endif
// Divide pl_clk (50MHz) to 1MHz
always @(posedge clk_in) begin
if (clkdiv_counter == 1 << CLK_DIVIDER_SIZE - 1) begin
clk_out <= ~clk_out;
end
clkdiv_counter <= clkdiv_counter +1;
end
endmodule |
module test_modes(
clk,
a_0,
a_1,
a_2,
a_3,
b_0,
b_1,
b_2,
b_3,
cin,
e,
f,
g,
sum_0,
sum_1,
sum_2,
sum_3,
cout,
x,
y,
z );
input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g;
output reg sum_0, sum_1, sum_2, sum_3, cout;
output wire x, y, z;
wire d0;
wire [4:0] n0;
wire [3:0] a, b;
reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin;
assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0};
assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0};
assign d0 = (e && g) || !f;
assign n0 = a + b + reg_cin;
assign x = reg3;
assign y = reg7;
assign z = reg11;
always @(posedge clk) begin
reg0 <= d0;
reg1 <= reg0;
reg2 <= reg1;
reg3 <= reg2;
reg4 <= reg3;
reg5 <= reg4;
reg6 <= reg5;
reg7 <= reg6;
reg8 <= reg7;
reg9 <= reg8;
reg10 <= reg9;
reg11 <= reg10;
reg_a_0 <= a_0;
reg_a_1 <= a_1;
reg_a_2 <= a_2;
reg_a_3 <= a_3;
reg_b_0 <= b_0;
reg_b_1 <= b_1;
reg_b_2 <= b_2;
reg_b_3 <= b_3;
reg_cin <= cin;
sum_0 <= n0[0];
sum_1 <= n0[1];
sum_2 <= n0[2];
sum_3 <= n0[3];
cout <= n0[4];
end
endmodule |
module K4n4_test (
clk,
a,
b,
c,
XOR,
XNOR,
AND,
NAND,
OR,
NOR,
XOR_sync,
XNOR_sync,
AND_sync,
NAND_sync,
OR_sync,
NOR_sync );
input wire clk;
input wire a;
input wire b;
input wire c;
output wire XOR;
output wire XNOR;
output wire AND;
output wire NAND;
output wire OR;
output wire NOR;
output reg XOR_sync;
output reg XNOR_sync;
output reg AND_sync;
output reg NAND_sync;
output reg OR_sync;
output reg NOR_sync;
assign XOR = a ^ b ^ c;
assign XNOR = !XOR;
assign OR = a || b || c;
assign NOR = !( a || b || c);
assign AND = a && b && c;
assign NAND = !(a && b && c);
always @(posedge clk) begin
XOR_sync = XOR;
XNOR_sync = XNOR;
OR_sync = OR;
NOR_sync = NOR;
AND_sync = AND;
NAND_sync = NAND;
end
endmodule |
module RISC_testbench;
wire [7:0]bus_1_out;
reg clk,rst;
wire [7:0]Reg_R0_out;
wire [7:0]Reg_R1_out;
wire [7:0]Reg_R2_out;
wire [7:0]Reg_R3_out;
/* wire [7:0]MEMAddress;
wire [7:0]MEMdataout;
wire MEMwrite; */
/* assign MEMAddress = top.MEMAddress;
assign MEMdataout = top.MEMdataout;
assign MEMwrite = top.MEMwrite; */
RISC_core_mem_top top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
always#20 clk=~clk;
initial
begin
clk=0;rst=1;
#30 rst=0;
#6000 $stop;
end
/* //----------
integer fp;
initial
begin
fp = $fopen("RISC_xa.vec");
$fdisplay(fp, "radix 1 1 44 44 44 44 44 1 44 44");
$fdisplay(fp, "vname clk rst Reg_R0_out[[7:0]] Reg_R1_out[[7:0]] Reg_R2_out[[7:0]] Reg_R3_out[[7:0]] bus_1_out[[7:0]] MEMwrite MEMAddress MEMdataout");
$fdisplay(fp, " io i i oo oo oo oo oo o oo ii");
$fdisplay(fp, "slope 0.3");
$fdisplay(fp, " vih 3.3");
$fdisplay(fp, " vil 0");
$fdisplay(fp, "tunit ns");
end
always@(clk)
begin
$fdisplay(fp, "%t %b %b %h %h %h %h %h %b %h %h", $time, clk, rst, Reg_R0_out, Reg_R1_out, Reg_R2_out, Reg_R3_out, bus_1_out, MEMwrite, MEMAddress, MEMdataout);
end
//---------- */
endmodule |
module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
output zero_flag_out;
output reg [7:0]alu_out;
input [7:0]Reg_Y_in,Bus_1_in;
input [7:0]IR_code;
wire [3:0]opcode=IR_code[7:4];
always@(*)
begin
case(opcode)
1: alu_out=Reg_Y_in+Bus_1_in;
2: alu_out=Bus_1_in+~(Reg_Y_in)+1;
3: alu_out=Reg_Y_in&(Bus_1_in);
4: alu_out=~(Bus_1_in);
default:alu_out=8'b0;
endcase
end
assign zero_flag_out=~|alu_out;
endmodule |
module Memory(Data_out,Address);
output [7:0]Data_out;
input [7:0]Address;
reg [7:0]mem[255:0];
assign Data_out=mem[Address];
always@(Address)
begin
case(Address)
//opcode_src_dest
//NOP
0: mem[Address]=8'b0000_00_00;
//rd 00 10 //Read MEM[130] to R2
1: mem[Address]=8'b0101_00_10; //Instruction
2: mem[Address]=130; //Address
//rd 00 11 //Read MEM[131] to R3
3: mem[Address]=8'b0101_00_11; //Instruction
4: mem[Address]=131; //Address
//rd 00 01 //Read MEM[128] to R1
5: mem[Address]=8'b0101_00_01; //Instruction
6: mem[Address]=128; //Address
//rd 00 00 //Read MEM[129] to R0
7: mem[Address]=8'b0101_00_00; //Instruction
8: mem[Address]=129; //Address
//Sub 00 01 //Sub R1-R0 to R1
9: mem[Address]=8'b0010_00_01; //Instruction
//BRZ 00 00
10: mem[Address]=8'b1000_00_00; //Instruction
11: mem[Address]=134; //Address
//Add 10 11 //Add R2+R3 to R3
12: mem[Address]=8'b00011011;
//BR
13: mem[Address]=8'b01110011; //Instruction
14: mem[Address]=140; //Address
128:mem[Address]=6;
129:mem[Address]=1;
130:mem[Address]=2;
131:mem[Address]=0;
134:mem[Address]=139; //Address
135:mem[Address]=0;
//HAL
139:mem[Address]=8'b1111_00_00; //Instruction
140:mem[Address]=9; //Address
default mem[Address]=8'bx;
endcase
end
endmodule |
module RISC_core_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
output [7:0]bus_1_out,MEMAddress;
input clk,rst;
input [7:0]MEMdataout;
output [7:0]Reg_R0_out;
output [7:0]Reg_R1_out;
output [7:0]Reg_R2_out;
output [7:0]Reg_R3_out;
wire [7:0]BUS_2,BUS_1,MEMAddress;
wire [7:0]alu_out;
wire [7:0]MEMdataout;
wire [7:0]Reg_Y_out,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out;
wire [7:0]IR_out;
wire zero_flag_out;
wire [2:0]Sel_Bus1;
wire [1:0]Sel_Bus2;
wire L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,L_IR,L_ADD_R,L_R_Y,L_R_Z,MEMwrite,zero;
assign bus_1_out=BUS_1;
assign bus_2_out=BUS_2;
Controller CON(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,MEMwrite,zero,IR_out,clk,rst);
//module PC(PC_out,PC_in,load,inc,clk,rst);
PC Program_Counter(PC_out,BUS_2,L_PC,Inc_PC,clk,rst);
//module ALU(zero_flag_out,alu_out,Reg_Y_in,Bus_1_in,IR_code);
ALU Arithmetic_Logic_Unit(zero_flag_out,alu_out,Reg_Y_out,BUS_1,IR_out);
//module Memory(Data_out,Data_in,MEMAddress,clk,MEMwrite);
//Memory MEM(MEMdataout,BUS_1,MEMAddress,clk,MEMwrite);
//module Mux_31(Y,A0,A1,A2,sel);
Mux_31 Mux31(BUS_2,alu_out,BUS_1,MEMdataout,Sel_Bus2);
//module Reg_1bit(Q,D,load,clk,rst);
Reg_1bit Reg_Z(zero,zero_flag_out,L_R_Z,clk,rst);
//module Reg_8bit(Q,D,load,clk,rst);
Reg_8bit Reg_Y(Reg_Y_out,BUS_2,L_R_Y,clk,rst);
Reg_8bit Add_R(MEMAddress,BUS_2,L_ADD_R,clk,rst);
//R0~R3
Reg_8bit Reg_R0(Reg_R0_out,BUS_2,L_R0,clk,rst);
Reg_8bit Reg_R1(Reg_R1_out,BUS_2,L_R1,clk,rst);
Reg_8bit Reg_R2(Reg_R2_out,BUS_2,L_R2,clk,rst);
Reg_8bit Reg_R3(Reg_R3_out,BUS_2,L_R3,clk,rst);
//module Mux_51(Y,A0,A1,A2,A3,A4,sel);
Mux_51 Mux51(BUS_1,Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,PC_out,Sel_Bus1);
//module IR(IR_out,IR_in,load,clk,rst);
IR Instruction_Register(IR_out,BUS_2,L_IR,clk,rst);
endmodule |
module Mux_31(Y,A0,A1,A2,sel);
output [7:0]Y;
input [7:0]A2,A1,A0;
input [1:0]sel;
reg [7:0]Y;
always@(*)
begin
case(sel)
0: Y=A0;
1: Y=A1;
2: Y=A2;
default:Y=8'bz;
endcase
end
endmodule |
module RISC_core_mem_top(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst);
output [7:0]bus_1_out;
input clk,rst;
output [7:0]Reg_R0_out;
output [7:0]Reg_R1_out;
output [7:0]Reg_R2_out;
output [7:0]Reg_R3_out;
wire [7:0]bus_1_out,MEMAddress;
wire clk,rst;
wire [7:0]MEMdataout;
wire [7:0]Reg_R0_out;
wire [7:0]Reg_R1_out;
wire [7:0]Reg_R2_out;
wire [7:0]Reg_R3_out;
RISC_core_top core(Reg_R0_out,Reg_R1_out,Reg_R2_out,Reg_R3_out,bus_1_out,clk,rst,MEMdataout,MEMAddress);
Memory MEM(MEMdataout,MEMAddress);
endmodule |
module IR(IR_out,IR_in,load,clk,rst);
output reg [7:0]IR_out;
input [7:0]IR_in;
input load,clk,rst;
always@(posedge clk)
begin
if(rst==1)IR_out<=8'b0;
else if(load==1)IR_out<=IR_in;
end
endmodule |
module Mux_51(Y,A0,A1,A2,A3,A4,sel);
output [7:0]Y;
input [7:0]A4,A3,A2,A1,A0;
input [2:0]sel;
reg [7:0]Y;
always@(*)
begin
case(sel)
0: Y=A0;
1: Y=A1;
2: Y=A2;
3: Y=A3;
4: Y=A4;
default:Y=8'bx;
endcase
end
endmodule |
module Reg_1bit(Q,D,load,clk,rst);
output Q;
input D;
input load,clk,rst;
reg Q;
always@(posedge clk)
begin
if(rst==1)Q<=0;
else if(load==1)Q<=D;
end
endmodule |
module Reg_8bit(Q,D,load,clk,rst);
output [7:0]Q;
input [7:0]D;
input load,clk,rst;
reg [7:0]Q;
always@(posedge clk)
begin
if(rst==1)Q<=8'b0;
else if(load==1)Q<=D;
end
endmodule |
module Controller(L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
Sel_Bus1,L_IR,L_ADD_R,L_R_Y,L_R_Z,Sel_Bus2,write,
zero,instruction,nclk,rst);
//狀態
parameter S_idle=0,S_fet1=1,S_fet2=2,S_dec=3,
S_ex1=4,S_rd1=5,S_rd2=6,S_wr1=7,S_wr2=8,
S_br1=9,S_br2=10,S_halt=11;
//指令
parameter NOP=0,ADD=1,SUB=2,AND=3,NOT=4,
RD=5,WR=6,BR=7,BRZ=8;
output reg L_R0,L_R1,L_R2,L_R3,L_PC,Inc_PC,
L_IR,L_ADD_R,L_R_Y,L_R_Z,write;
output reg[2:0]Sel_Bus1;
output reg [1:0]Sel_Bus2;
input zero,nclk,rst;
input [7:0]instruction;
reg [15:0]Con_out;
reg [3:0]PS,NS;
reg err_flag;
wire [1:0]src=instruction[3:2];
wire [1:0]dest=instruction[1:0];
wire [3:0]opcode=instruction[7:4];
always@(posedge nclk)
begin
if(rst==1)PS<=0;
else PS<=NS;
end
always@(PS,opcode,src,dest,zero)
begin
L_R0=0;
L_R1=0;
L_R2=0;
L_R3=0;
L_PC=0;
Inc_PC=0;
Sel_Bus1=0;
L_IR=0;
L_ADD_R=0;
L_R_Y=0;
L_R_Z=0;
Sel_Bus2=0;
write=0;
err_flag=0;
case(PS)
S_idle: NS=S_fet1;
S_fet1: begin
NS=S_fet2;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=2'b01;//Sel_Bus1
L_ADD_R=1;
end
S_fet2: begin
NS=S_dec;
Sel_Bus2=2'b10;//Sel_Mem
L_IR=1;
Inc_PC=1;
end
S_dec: begin
case(opcode)
NOP:NS=S_fet1;
ADD,SUB,AND:begin
NS=S_ex1;
Sel_Bus2=2'b01;//Sel_Bus1
L_R_Y=1;
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
end//ADD,SUB,AND
NOT:begin
NS=S_fet1;
L_R_Z=1;
Sel_Bus2=2'b00;//Sel_ALU
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
case(dest)
0: L_R0=1;
1: L_R1=1;
2: L_R2=1;
3: L_R3=1;
default err_flag=1;
endcase
end//NOT
RD: begin
NS=S_rd1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//RD
WR: begin
NS=S_wr1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//WR
BR: begin
NS=S_br1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end//BR
BRZ:begin
if(zero==1)begin
NS=S_br1;
Sel_Bus1=3'b100;//Sel_PC
Sel_Bus2=3'b001;//Sel_Bus1
L_ADD_R=1;
end
else begin
NS=S_fet1;
Inc_PC=1;
end
end//BRZ
default NS=S_halt;
endcase//opcode
end
S_ex1: begin
NS=S_fet1;
L_R_Z=1;
Sel_Bus2=2'b00;//Sel_ALU
case(dest)
0: begin Sel_Bus1=3'b000;L_R0=1;end
1: begin Sel_Bus1=3'b001;L_R1=1;end
2: begin Sel_Bus1=3'b010;L_R2=1;end
3: begin Sel_Bus1=3'b011;L_R3=1;end
default err_flag=1;
endcase
end
S_rd1: begin
NS=S_rd2;
Inc_PC=1;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_wr1: begin
NS=S_wr2;
Inc_PC=1;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_rd2: begin
NS=S_fet1;
Sel_Bus2=2'b10;//Sel_Mem
case(dest)
0: L_R0=1;
1: L_R1=1;
2: L_R2=1;
3: L_R3=1;
default err_flag=1;
endcase
end
S_wr2: begin
NS=S_fet1;
write=1;
case(src)
0: Sel_Bus1=3'b000;//R0
1: Sel_Bus1=3'b001;//R1
2: Sel_Bus1=3'b010;//R2
3: Sel_Bus1=3'b011;//R3
default err_flag=1;
endcase
end
S_br1: begin
NS=S_br2;
Sel_Bus2=2'b10;//Sel_Mem
L_ADD_R=1;
end
S_br2: begin
NS=S_fet1;
Sel_Bus2=2'b10;//Sel_Mem
L_PC=1;
end
S_halt: NS=S_halt;
default NS=S_idle;
endcase
end
endmodule |
module PC(PC_out,PC_in,load,inc,clk,rst);
output [7:0]PC_out;
input [7:0]PC_in;
input load,inc,clk,rst;
reg [7:0]PC_out;
always@(posedge clk)
begin
if(rst==1)PC_out<=8'b0;
else if(load==1)PC_out<=PC_in;
else if(inc==1)PC_out<=PC_out+8'b00000001;
end
endmodule |
module testSAPone;
wire [7:0] SAP_out;
wire [11:0] con;
wire [7:0] bus;
// wire clk_out, clr_out;
reg clk, clr_;
always #5 clk = ~clk;
SAPone sapone1(
.SAP_out(SAP_out),
.con(con),
.bus(bus),
// .clk_out(clk_out),
// .clr_out(clr_out),
.clk(clk),
.clr_(clr_)
);
// PC pc1(bus[3:0], clk, clr_, cp, ep);
// MAR mar1(mar, clk, lm_, bus[3:0]);
initial
begin
clk = 0; clr_ = 0;
#10 clr_ = 1;
#990 $stop;
end
endmodule |
module OutputRegister(
output reg [7:0] OutputRegister_out,
input [7:0] OutputRegister_in,
input lo_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) OutputRegister_out <= 8'b0;
else if(~lo_) OutputRegister_out <= OutputRegister_in;
endmodule |
module ACC(
output [7:0] acc_out1,
output [7:0] acc_out2,
input [7:0] acc_in,
input la_,
input clk,
input clr_
);
reg [7:0] q;
always @(posedge clk)
if (~clr_) q <= 8'b0;
else if(~la_) q <= acc_in;
assign acc_out1 = q;
assign acc_out2 = q;
endmodule |
module ROM(
output reg [7:0] rom_out,
input [3:0] rom_in
);
always @(*)
begin
rom_out = 8'bx;
case(rom_in)
4'b0000: rom_out = 8'b0000_1001; //LDA
4'b0001: rom_out = 8'b0001_1010; //ADD
4'b0010: rom_out = 8'b0001_1011; //ADD
4'b0011: rom_out = 8'b0010_1100; //SUB
4'b0100: rom_out = 8'b1110_xxxx; //OUT
4'b0101: rom_out = 8'b1111_xxxx; //HLT
4'b0110: rom_out = 8'bxxxx_xxxx;
4'b0111: rom_out = 8'bxxxx_xxxx;
4'b1000: rom_out = 8'bxxxx_xxxx;
4'b1001: rom_out = 8'b0001_0000;
4'b1010: rom_out = 8'b0001_0100;
4'b1011: rom_out = 8'b0001_1000;
4'b1100: rom_out = 8'b0010_0000;
endcase
end
endmodule |
module BRegister(
output reg [7:0] BRegister_out,
input [7:0] BRegister_in,
input lb_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) BRegister_out <= 8'b0;
else if(~lb_) BRegister_out <= BRegister_in;
endmodule |
module ADDSUB(
output [7:0] ADDSUB_out,
input [7:0] ADDSUB_in1,
input [7:0] ADDSUB_in2,
input su
);
wire [7:0] d;
assign d = su ? ADDSUB_in1 - ADDSUB_in2 : ADDSUB_in1 + ADDSUB_in2;
assign ADDSUB_out = d;
endmodule |
module SAPone(
output wire [7:0] SAP_out,
output wire [11:0] con,
output reg [7:0] bus,
input clk,
input clr_
);
wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_;
wire [7:0] acc_out2, BRegister_out, OutputRegister_out;
wire [3:0] IR_out, mar_out;
wire [4:0] bus_sel;
wire [3:0] pc_out, oprand;
wire [7:0] rom_out, acc_out1, ADDSUB_out;
assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con;
assign bus_sel = {ep, ce_, ei_, ea, eu};
always@(*)
begin
case(bus_sel)
5'b11100: bus[3:0] = pc_out;
5'b00100: bus[7:0] = rom_out;
5'b01000: bus[3:0] = oprand;
5'b01110: bus[7:0] = acc_out1;
5'b01101: bus[7:0] = ADDSUB_out;
default: bus[7:0] = 8'bx;
endcase
end
PC pc1(
.pc_out(pc_out),
.cp(cp),
.clk(clk),
.clr_(clr_)
);
MAR mar1(
.mar_out(mar_out),
.mar_in(bus[3:0]),
.lm_(lm_),
.clk(clk),
.clr_(clr_)
);
ROM roml(
.rom_out(rom_out),
.rom_in(mar_out)
);
IR ir1(
.opcode(IR_out),
.oprand(oprand),
.IR_in(bus[7:0]),
.li_(li_),
.clk(clk),
.clr_(clr_)
);
Controller cont1(
.control_signals(con),
.opcode(IR_out),
.clk(clk),
.clr_(clr_)
);
ACC acc1(
.acc_out1(acc_out1),
.acc_out2(acc_out2),
.acc_in(bus[7:0]),
.la_(la_),
.clk(clk),
.clr_(clr_)
);
ADDSUB addsub1(
.ADDSUB_out(ADDSUB_out),
.ADDSUB_in1(acc_out2),
.ADDSUB_in2(BRegister_out),
.su(su)
);
BRegister bregister1(
.BRegister_out(BRegister_out),
.BRegister_in(bus[7:0]),
.lb_(lb_),
.clk(clk),
.clr_(clr_)
);
OutputRegister outputregister1(
.OutputRegister_out(SAP_out),
.OutputRegister_in(bus[7:0]),
.lo_(lo_),
.clk(clk),
.clr_(clr_)
);
endmodule |
module IR(
output [7:4] opcode,
output [3:0] oprand,
input wire [7:0] IR_in,
input li_,
input clk,
input clr_
);
reg [7:0] q;
always @(posedge clk)
begin
if(~clr_) q <=8'b0;
else if(~li_) q <= IR_in;
end
assign opcode = q[7:4];
assign oprand = q[3:0];
endmodule |
module MAR(
output reg [3:0] mar_out,
input wire [3:0] mar_in,
input lm_,
input clk,
input clr_
);
always @(posedge clk)
if(~clr_) mar_out <= 4'b0;
else if(~lm_) mar_out <= mar_in;
endmodule |
module Controller(
output reg [11:0] control_signals,
input [3:0] opcode,
input clk,
input clr_
);
reg [3:0] ps, ns;
always @(posedge clk)
begin
if(~clr_) ps <= 4'd0;
else ps <= ns;
end
always @(*)
begin
case(ps)
0:
begin
control_signals = 12'h3e3;
ns = 4'd1;
end
1: //T1
begin
control_signals = 12'h5e3;
ns = 4'd2;
end
2: //T2
begin
// control_signals = 12'hbe3;
control_signals = 12'h863;
ns = 4'd3;
end
3: //T3
begin
// control_signals = 12'h263;
control_signals = 12'h3e3;
if(opcode == 4'd0) //LDA
ns = 4'd4;
else if(opcode == 4'd1) //ADD
ns = 4'd6;
else if(opcode == 4'd2) //SUB
ns = 4'd9;
else if(opcode == 4'd14) //OUT
ns = 4'd12;
else if(opcode == 4'd15) //HLT
ns = 4'd13;
end
4: //LDA
begin
control_signals = 12'h1a3;
ns = 4'd5;
end
5: //LDA
begin
control_signals = 12'h2c3;
ns = 4'd1;
end
6: //ADD
begin
control_signals = 12'h1a3;
ns = 4'd7;
end
7: //ADD
begin
control_signals = 12'h2e1;
ns = 4'd8;
end
8: //ADD
begin
control_signals = 12'h3c7;
ns = 4'd1;
end
9: //SUB
begin
control_signals = 12'h1a3;
ns = 4'd10;
end
10: //SUB
begin
control_signals = 12'h2e1;
ns = 4'd11;
end
11: //SUB
begin
control_signals = 12'h3cf;
ns = 4'd1;
end
12: //OUT
begin
control_signals = 12'h3f2;
ns = 4'd1;
end
13: //HLT
ns = 4'd13;
default:
begin
ns = 4'd0;
control_signals = 12'h3e3;
end
endcase
end
endmodule |
module PC(
output reg [3:0] pc_out,
input cp,
input clk,
input clr_
);
always @(posedge clk)
begin
if(~clr_) pc_out <= 0;
else if (cp) pc_out <= pc_out + 1;
end
endmodule |
module adder_4(cout, sum, a, b, cin);
parameter size = 4; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule |
module adder_6(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule |
module adder_8(cout, sum, a, b, cin);
parameter size = 8; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
input [size-1:0] a, b; // 'a' and 'b' use the size parameter
assign {cout, sum} = a + b + cin;
endmodule |
module counter (
clk,
reset,
result
);
input clk;
input reset;
output [127:0] result;
reg [127:0] result;
initial begin
result <= 0;
end
always @(posedge clk or posedge reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule |
module counter_tb;
reg clk, reset;
wire [127:0] result;
counter DUT(
.clk(clk),
.reset(reset),
.result(result)
);
initial begin
#0 reset = 1'b1; clk = 1'b0;
#100 reset = 1'b0;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule |
module counter (
clk,
resetb,
result
);
input clk;
input resetb;
output [127:0] result;
reg [127:0] result;
initial begin
result <= 0;
end
always @(posedge clk or negedge resetb)
begin
if (~resetb)
result = 0;
else
result = result + 1;
end
endmodule |
module counter(clk_counter, q_counter, rst_counter);
input clk_counter;
input rst_counter;
output [7:0] q_counter;
reg [7:0] q_counter;
initial begin
q_counter <= 0;
end
always @ (posedge clk_counter)
begin
if(rst_counter)
q_counter <= 8'b00000000;
else
q_counter <= q_counter + 1;
end
endmodule |
module counter_tb;
reg clk, resetb;
wire [7:0] result;
counter DUT(
.clk(clk),
.resetb(resetb),
.result(result)
);
initial begin
#0 resetb = 1'b0; clk = 1'b0;
#100 resetb = 1'b1;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule |
module counter (
clkn,
reset,
result
);
input clkn;
input reset;
output [7:0] result;
reg [7:0] result;
initial begin
result <= 0;
end
always @(negedge clkn or posedge reset)
begin
if (reset)
result = 0;
else
result = result + 1;
end
endmodule |
module counter_tb;
reg clk, reset;
wire [7:0] result;
counter DUT(
.clkn(clk),
.reset(reset),
.result(result)
);
initial begin
#0 reset = 1'b1; clk = 1'b0;
#100 reset = 1'b0;
end
always begin
#10 clk = ~clk;
end
initial begin
#5000 $stop;
end
endmodule |
module counter_4bit_2clock(clk0, rst, clk1, q0, q1);
input clk0;
input rst;
output [3:0] q0;
reg [3:0] q0;
input clk1;
output [3:0] q1;
reg [3:0] q1;
initial begin
q0 <= 0;
q1 <= 0;
end
always @ (posedge clk0)
begin
if(rst)
q0 <= 4'b0000;
else
q0 <= q0 + 1;
end
always @ (posedge clk1)
begin
if(rst)
q1 <= 4'b0000;
else
q1 <= q1 + 1;
end
endmodule |
module fifo
#( parameter ADDRESS_WIDTH = 4, // number of words in ram
DATA_WIDTH = 4 // number of bits in word
)
// IO ports
(
input wire clk, reset,
input wire read, write,
input wire [DATA_WIDTH-1:0] write_data,
output wire empty, full,
output wire [DATA_WIDTH-1:0] read_data
);
// internal signal declarations
reg [ADDRESS_WIDTH-1:0] write_address_reg, write_address_next, write_address_after;
reg [ADDRESS_WIDTH-1:0] read_address_reg, read_address_next, read_address_after;
reg full_reg, empty_reg, full_next, empty_next;
wire write_en;
// write enable is asserted when write input is asserted and FIFO isn't full
assign write_en = write & ~full_reg;
// instantiate synchronous block ram
sync_dual_port_ram #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) ram
(.clk(clk), .write_en(write_en), .write_address(write_address_reg),
.read_address(read_address_reg), .write_data_in(write_data),
.write_data_out(), .read_data_out(read_data));
// register for address pointers, full/empty status
always @(posedge clk, posedge reset)
if (reset)
begin
write_address_reg <= 0;
read_address_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
write_address_reg <= write_address_next;
read_address_reg <= read_address_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
// next-state logic for address index values after read/write operations
always @*
begin
write_address_after = write_address_reg + 1;
read_address_after = read_address_reg + 1;
end
// next-state logic for address pointers
always @*
begin
// defaults
write_address_next = write_address_reg;
read_address_next = read_address_reg;
full_next = full_reg;
empty_next = empty_reg;
// if read input asserted and FIFO isn't empty
if(read && ~empty_reg && ~write)
begin
read_address_next = read_address_after; // read address moves forward
full_next = 1'b0; // FIFO isn't full if a read occured
if (read_address_after == write_address_reg) // if read address caught up with write address,
empty_next = 1'b1; // FIFO is empty
end
// if write input asserted and FIFO isn't full
else if(write && ~full_reg && ~read)
begin
write_address_next = write_address_after; // write address moves forward
empty_next = 1'b0; // FIFO isn't empty if write occured
if (write_address_after == read_address_reg) // if write address caught up with read address
full_next = 1'b1; // FIFO is full
end
// if write and read are asserted
else if(write && read)
begin
write_address_next = write_address_after; // write address moves forward
read_address_next = read_address_after; // read address moves forward
end
end
// assign full/empty status to output ports
assign full = full_reg;
assign empty = empty_reg;
endmodule |
module sync_dual_port_ram
#( parameter ADDRESS_WIDTH = 4, // number of words in ram
DATA_WIDTH = 4 // number of bits in word
)
// IO ports
(
input wire clk, // clk for synchronous read/write
input wire write_en, // signal to enable synchronous write
input wire [ADDRESS_WIDTH-1:0] read_address, write_address, // inputs for dual port addresses
input wire [DATA_WIDTH-1:0] write_data_in, // input for data to write to ram
output wire [DATA_WIDTH-1:0] read_data_out, write_data_out // outputs for dual data ports
);
// internal signal declarations
reg [DATA_WIDTH-1:0] ram [2**ADDRESS_WIDTH-1:0]; // ADDRESS_WIDTH x DATA_WIDTH RAM declaration
reg [ADDRESS_WIDTH-1:0] read_address_reg, write_address_reg; // dual port address declarations
// synchronous write and address update
always @(posedge clk)
begin
if (write_en) // if write enabled
ram[write_address] <= write_data_in; // write data to ram and write_address
read_address_reg <= read_address; // store read_address to reg
write_address_reg <= write_address; // store write_address to reg
end
// assignments for two data out ports
assign read_data_out = ram[read_address_reg];
assign write_data_out = ram[write_address_reg];
endmodule |
module mac_8(a, b, c, out);
parameter DATA_WIDTH = 8; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_18(a, b, c, out);
parameter DATA_WIDTH = 18; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_20(a, b, c, out);
parameter DATA_WIDTH = 20; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_8_9(a, b, c, out);
parameter DATA_WIDTH = 18; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out[8:0] = a[8:0] * b[8:0] + c[8:0];
assign out[17:9] = a[17:9] * b[17:9] + c[17:9];
endmodule |
module mac_6(a, b, c, out);
parameter DATA_WIDTH = 6; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_36(a, b, c, out);
parameter DATA_WIDTH = 4; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
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