module
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module mac_2(a, b, c, out);
parameter DATA_WIDTH = 2; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_12(a, b, c, out);
parameter DATA_WIDTH = 12; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_16(a, b, c, out);
parameter DATA_WIDTH = 16; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_9(a, b, c, out);
parameter DATA_WIDTH = 9; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_32(a, b, c, out);
parameter DATA_WIDTH = 32; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module mac_4(a, b, c, out);
parameter DATA_WIDTH = 4; /* declare a parameter. default required */
input [DATA_WIDTH - 1 : 0] a, b, c;
output [DATA_WIDTH - 1 : 0] out;
assign out = a * b + c;
endmodule |
module ex5p (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_, o_8_, o_9_, o_10_,
o_11_, o_12_, o_13_, o_14_, o_15_, o_16_, o_17_, o_18_, o_19_, o_20_,
o_21_, o_22_, o_23_, o_24_, o_25_, o_26_, o_27_, o_28_, o_29_, o_30_,
o_31_, o_32_, o_33_, o_34_, o_35_, o_36_, o_37_, o_38_, o_39_, o_40_,
o_41_, o_42_, o_43_, o_44_, o_45_, o_46_, o_47_, o_48_, o_49_, o_50_,
o_51_, o_52_, o_53_, o_54_, o_55_, o_56_, o_57_, o_58_, o_59_, o_60_,
o_61_, o_62_;
wire n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204,
n205, n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228,
n229, n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300,
n301, n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336,
n337, n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444,
n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516,
n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597;
assign o_0_ = ~n365;
assign o_1_ = ~n361;
assign o_2_ = ~n403;
assign o_3_ = ~n370;
assign o_4_ = ~n450;
assign o_5_ = ~n357;
assign o_6_ = ~n136;
assign o_7_ = ~n180;
assign o_8_ = ~n452;
assign o_9_ = ~n491;
assign o_10_ = ~n139;
assign o_11_ = ~n179;
assign o_12_ = ~n385;
assign o_13_ = ~n471;
assign o_14_ = ~n507;
assign o_15_ = ~n138;
assign o_16_ = ~n407;
assign o_17_ = ~n354;
assign o_18_ = ~n421;
assign o_19_ = ~n420;
assign o_20_ = ~n142;
assign o_21_ = ~n145;
assign o_22_ = ~n148;
assign o_23_ = ~n352;
assign o_24_ = ~n504;
assign o_25_ = ~n200;
assign o_26_ = ~n151;
assign o_27_ = ~n260;
assign o_28_ = ~n556;
assign o_29_ = ~n506;
assign o_30_ = ~n150;
assign o_31_ = ~n347;
assign o_32_ = ~n344;
assign o_33_ = ~n340;
assign o_34_ = ~n336;
assign o_35_ = ~n332;
assign o_36_ = ~n328;
assign o_37_ = ~n321;
assign o_38_ = ~n314;
assign o_39_ = ~n308;
assign o_40_ = ~n303;
assign o_41_ = ~n296;
assign o_42_ = ~n291;
assign o_43_ = ~n284;
assign o_44_ = ~n276;
assign o_45_ = ~n274;
assign o_46_ = ~n268;
assign o_47_ = ~n264;
assign o_48_ = ~n259;
assign o_49_ = ~n257;
assign o_50_ = ~n252;
assign o_51_ = ~n245;
assign o_52_ = ~n238;
assign o_53_ = ~n232;
assign o_54_ = ~n226;
assign o_55_ = ~n220;
assign o_56_ = ~n214;
assign o_57_ = ~n205;
assign o_58_ = ~n197;
assign o_59_ = ~n189;
assign o_60_ = ~n182;
assign o_61_ = ~n173;
assign o_62_ = ~n164;
assign n134 = n155 | n439;
assign n135 = n155 | n441;
assign n136 = n134 & n135;
assign n137 = n436 | n339;
assign n138 = n445 | n339;
assign n139 = n137 & n138;
assign n140 = n462 | n152;
assign n141 = n463 | n152;
assign n142 = n140 & n141;
assign n143 = n439 | n152;
assign n144 = n441 | n152;
assign n145 = n143 & n144;
assign n146 = n434 | n152;
assign n147 = n446 | n152;
assign n148 = n146 & n147;
assign n149 = n434 | n373;
assign n150 = n434 | n369;
assign n151 = n149 & n150;
assign n152 = i_2_ | ~i_0_ | i_1_;
assign n153 = n152 | ~n381;
assign n154 = ~i_3_ | ~i_4_ | ~i_5_;
assign n155 = i_0_ | i_1_ | ~i_2_;
assign n156 = n154 | n155;
assign n157 = i_0_ | i_1_ | i_2_;
assign n158 = n157 | ~n366;
assign n159 = n373 & n338;
assign n160 = n514 & n505 & n363;
assign n161 = n515 & n339 & n269 & n195 & n496;
assign n162 = n179 & n458 & n408 & n461 & n374;
assign n163 = n150 & n516 & n517 & n176 & n454;
assign n164 = n159 & n160 & n161 & n162 & n163;
assign n165 = n398 & n533 & n535;
assign n166 = n523 & n524;
assign n167 = n412 & n503;
assign n168 = n504 & n363;
assign n169 = n450 & n556;
assign n170 = n372 & n555 & n180;
assign n171 = n254 & n243 & n400;
assign n172 = n518 & n192 & n554;
assign n173 = n165 & n166 & n167 & n168 & n169 & n170 & n171 & n172;
assign n174 = n208 & n309 & n563 & n421 & n254 & n518;
assign n175 = n410 & n560 & n192 & n165 & n457 & n461 & n150 & n516;
assign n176 = n452 & n451;
assign n177 = n362 & n552 & n454;
assign n178 = n369 | n462;
assign n179 = n436 | n409;
assign n180 = n436 | n270;
assign n181 = n369 | n463;
assign n182 = n174 & n175 & n176 & n177 & n178 & n179 & n180 & n181;
assign n183 = n411 & (n157 | ~n382) & n412;
assign n184 = n548 & n298;
assign n185 = n418 & (n239 | n409);
assign n186 = n569 & n570 & n310 & n345 & n169 & n334 & n255 & n163;
assign n187 = n265 & n573 & n170 & n203;
assign n188 = n594 & n493 & n487 & n483 & n408 & n397 & ~n383 & n387;
assign n189 = n183 & n184 & n185 & n186 & n187 & n188;
assign n190 = n576 & n575 & n532 & n451 & n414 & n140 & n297 & ~n367;
assign n191 = n493 & ~n383 & n492;
assign n192 = n405 & n550 & n404 & n145 & n551 & n549;
assign n193 = n563 & n272;
assign n194 = n421 & n485 & n487;
assign n195 = n478 & n481 & n475 & n477;
assign n196 = n351 & n158 & (n154 | n157);
assign n197 = n190 & n191 & n192 & n193 & n194 & n195 & n138 & n196;
assign n198 = n470 & n468;
assign n199 = n150 & n536;
assign n200 = n270 | n443;
assign n201 = n261 & n471 & n394;
assign n202 = n228 & n414 & (n339 | ~n382);
assign n203 = n179 & n572;
assign n204 = n221 & n215 & n422 & n185 & n423 & n300;
assign n205 = n198 & n199 & n200 & n201 & n166 & n202 & n203 & n204;
assign n206 = n578 & n579 & n554 & n169;
assign n207 = n310 & n577;
assign n208 = n496 & n562;
assign n209 = n580 & ~n395 & n491;
assign n210 = n149 & n378 & n370 & n419 & n306;
assign n211 = n501 & n563;
assign n212 = n180 & n518;
assign n213 = n228 & n171 & n467 & n196 & n594 & n376 & n534 & n471;
assign n214 = n206 & n207 & n208 & n209 & n210 & n211 & n212 & n213;
assign n215 = n563 & n183;
assign n216 = n537 & ~n367 & n451;
assign n217 = n534 & n275 & n139 & n142;
assign n218 = n570 & n571 & n184 & n581 & n337 & n582;
assign n219 = n156 & n171 & n427 & n200;
assign n220 = n215 & n216 & n180 & n166 & n217 & n218 & n219;
assign n221 = n396 & n180 & n159;
assign n222 = n474 & n247;
assign n223 = n519 & n348 & n494;
assign n224 = n472 & n470;
assign n225 = n572 & n575 & n478 & n538 & n158 & n458 & n534 & n468;
assign n226 = n209 & n219 & n193 & n221 & n222 & n223 & n224 & n225;
assign n227 = n449 & n452;
assign n228 = n525 & n526;
assign n229 = n146 & n527 & n528 & n529 & n530;
assign n230 = n391 & n392 & (n393 | n339);
assign n231 = n476 & n583 & n537 & n137 & n141 & n534;
assign n232 = n174 & n218 & n227 & n228 & n229 & n230 & n231;
assign n233 = n351 & n215;
assign n234 = n254 & n494 & n559 & n509 & n262 & n292 & n426;
assign n235 = n387 & n491;
assign n236 = n384 & n385 & (n373 | n386);
assign n237 = n510 & n548;
assign n238 = n233 & n234 & n224 & n235 & n236 & n186 & n162 & n237;
assign n239 = ~n381 & ~n382;
assign n240 = n155 | n239;
assign n241 = n255 & n240 & n389 & n387 & n584 & n491;
assign n242 = n488 & n489;
assign n243 = n421 & n482;
assign n244 = n254 & n494 & n453;
assign n245 = n175 & n212 & n227 & n233 & n241 & n242 & n243 & n244;
assign n246 = n560 & n203;
assign n247 = n408 & ((~n381 & ~n382) | n409);
assign n248 = n200 & n483 & n486;
assign n249 = n540 & n539;
assign n250 = n524 & n192 & n412 & n501 & n168 & n288 & n293;
assign n251 = n535 & n543 & n546 & n477 & n380 & n533;
assign n252 = n246 & n247 & n248 & n249 & n250 & n251;
assign n253 = n288 & n248 & n342 & n586 & n266;
assign n254 = n155 | n446;
assign n255 = n155 | n443;
assign n256 = n350 & n158 & n351 & n520;
assign n257 = n193 & n235 & n253 & n254 & n255 & n256;
assign n258 = n254 & n241 & n135 & n134;
assign n259 = n258 & n253 & n242 & n160;
assign n260 = n443 | n339;
assign n261 = n434 | n339;
assign n262 = n429 & n281 & n248;
assign n263 = n417 & n224 & (n393 | n270);
assign n264 = n260 & n190 & n139 & n261 & n262 & n250 & n263;
assign n265 = n421 & n156 & n468 & n200;
assign n266 = n210 & n585 & n345 & n207;
assign n267 = n196 & n496 & n160 & n396 & n180 & n515;
assign n268 = n265 & n191 & n206 & n263 & n266 & n267;
assign n269 = n493 & n492 & n194 & n196 & ~n383;
assign n270 = i_2_ | i_0_ | ~i_1_;
assign n271 = n260 & n261;
assign n272 = n500 & n330 & n420 & n411 & n497 & n498;
assign n273 = n577 & n206 & n210;
assign n274 = n269 & n168 & n270 & n271 & n272 & n217 & n273;
assign n275 = n530 & n568 & n146 & n529;
assign n276 = n211 & n273 & n161 & n275;
assign n277 = n567 & n530 & n482 & ~n415 & n137 & n228 & ~n395;
assign n278 = n196 & n330 & n451 & n431 & n254 & n491 & n588 & n589;
assign n279 = n484 & n363 & n486 & n502;
assign n280 = n180 & (n270 | n355);
assign n281 = n476 & n583 & n468 & n396;
assign n282 = n298 & n417 & n222;
assign n283 = n511 & n405 & n499 & n508 & n374 & n377 & n179 & n595;
assign n284 = n277 & n278 & n249 & n279 & n280 & n281 & n282 & n283;
assign n285 = n477 & n394 & n471 & n378;
assign n286 = n413 & n423 & n590 & n138 & n144 & n228;
assign n287 = n179 & n553;
assign n288 = n422 & n243;
assign n289 = n419 & n420 & n579;
assign n290 = n549 & n406 & n410 & n563 & n569 & n411 & n380 & n596;
assign n291 = n285 & n286 & n248 & n278 & n287 & n288 & n289 & n290;
assign n292 = n288 & n404 & (n152 | ~n366);
assign n293 = n326 & n426 & n258;
assign n294 = n585 & n586 & n345 & n248;
assign n295 = n547 & n405 & n560 & n542 & n543 & n546;
assign n296 = n292 & n293 & n294 & n193 & n207 & n223 & n295;
assign n297 = n458 & n246 & n247;
assign n298 = n402 & n547;
assign n299 = n356 & n550 & n564;
assign n300 = n254 & n400 & n543;
assign n301 = n405 & n318 & n473 & n536 & n476 & n469 & n474 & n409;
assign n302 = n482 & n411 & n153 & n339 & n380 & n330 & n523;
assign n303 = n275 & n297 & n298 & n299 & n300 & n279 & n301 & n302;
assign n304 = n573 & n185 & n581 & n587 & n315 & n167 & n203 & n591;
assign n305 = n153 & n531;
assign n306 = n356 & n564 & n184;
assign n307 = n470 & n142 & n145 & n194 & n261 & ~n382;
assign n308 = n277 & n285 & n304 & n305 & n306 & n258 & n307;
assign n309 = n196 & n492 & n561;
assign n310 = n142 & n275 & ~n415;
assign n311 = n149 & n298 & n419;
assign n312 = n147 & n370 & n508;
assign n313 = n327 & n503 & n363;
assign n314 = n309 & n310 & n206 & n294 & n311 & n312 & n208 & n313;
assign n315 = n575 & n576 & n457 & n454;
assign n316 = n448 & n513 & n459;
assign n317 = n447 & n512 & n136 & n145 & n526 & n495 & n460;
assign n318 = n525 & n478 & n481;
assign n319 = n405 & n562 & n578 & n230 & n532 & n371;
assign n320 = n541 & n556 & n147 & n449 & n510 & n551 & n565 & n597;
assign n321 = n315 & n316 & n317 & n211 & n234 & n318 & n319 & n320;
assign n322 = n477 & n550 & n342 & n318 & n311 & n471 & n470 & n592;
assign n323 = n146 & n590;
assign n324 = n561 & n548 & n531 & n491 & ~n382 & n387;
assign n325 = n356 & n507;
assign n326 = n242 & n256;
assign n327 = n482 & n254;
assign n328 = n322 & n323 & n193 & n324 & n325 & n326 & n327 & n194;
assign n329 = n325 & n353 & (n152 | ~n381);
assign n330 = n515 & n495;
assign n331 = n531 & n486 & n485;
assign n332 = n243 & n293 & n322 & n323 & n329 & n330 & n211 & n331;
assign n333 = n143 & (n152 | ~n382);
assign n334 = n416 & (n270 | ~n366) & n417;
assign n335 = n518 & n398 & n243 & n180 & n254 & n508;
assign n336 = n286 & n304 & n324 & n298 & n333 & n334 & n335;
assign n337 = n572 & n578 & n287;
assign n338 = n152 & n511 & n312 & n402 & n512 & n513;
assign n339 = ~i_2_ | i_0_ | ~i_1_;
assign n340 = n216 & n301 & n211 & n337 & n338 & n208 & n339 & n269;
assign n341 = n550 & n311 & n329;
assign n342 = n206 & n223;
assign n343 = n180 & n482;
assign n344 = n279 & n341 & n258 & n342 & n326 & n272 & n165 & n343;
assign n345 = n202 & n413 & n567;
assign n346 = n523 & n505 & n229 & n305 & n330 & n363 & ~n415;
assign n347 = n345 & n206 & n171 & n334 & n224 & n262 & n341 & n346;
assign n348 = n157 | n370;
assign n349 = n519 & n520;
assign n350 = n154 | n157;
assign n351 = n445 | n157;
assign n352 = n348 & n349 & n350 & n351;
assign n353 = n152 | ~n366;
assign n354 = n153 & n353;
assign n355 = n435 | n442;
assign n356 = n442 | n444;
assign n357 = n355 & n356;
assign n358 = n157 | n462;
assign n359 = n488 & n515 & n178 & n552 & n316 & n396 & n486 & n593;
assign n360 = (~n366 & ~n381) | n438;
assign n361 = n143 & n358 & n134 & n140 & n359 & n360;
assign n362 = n409 | n463;
assign n363 = n358 & n506;
assign n364 = n468 & n483 & n489 & n142 & n509 & n465;
assign n365 = n181 & n362 & n363 & n317 & n359 & n364;
assign n366 = i_3_ & i_4_ & ~i_5_;
assign n367 = ~n369 & (~n154 | n366);
assign n368 = n369 | (n356 & n378);
assign n369 = ~i_0_ | ~i_1_ | ~i_2_;
assign n370 = n438 | n444;
assign n371 = n368 & (n369 | n370);
assign n372 = n445 | n373;
assign n373 = ~i_2_ | ~i_0_ | i_1_;
assign n374 = n372 & ((n154 & ~n366) | n373);
assign n375 = n339 | n239;
assign n376 = n464 & n465;
assign n377 = n376 & (n270 | n154);
assign n378 = n440 | n444;
assign n379 = n270 | (n356 & n378);
assign n380 = n180 & (n270 | ~n381);
assign n381 = ~i_5_ & ~i_3_ & i_4_;
assign n382 = i_5_ & ~i_3_ & i_4_;
assign n383 = ~n155 & (n381 | n382);
assign n384 = n373 | n355;
assign n385 = n436 | n373;
assign n386 = n435 | n440;
assign n387 = n155 | n436;
assign n388 = n387 & (n155 | ~n381);
assign n389 = n155 | (n355 & n386);
assign n390 = ~n157 & (~n154 | n366);
assign n391 = n378 | n339;
assign n392 = n140 & n138 & n566;
assign n393 = n154 & ~n366;
assign n394 = n260 & n376 & (n393 | n270);
assign n395 = ~n339 & (n381 | n382);
assign n396 = n270 | n439;
assign n397 = n396 & (n270 | ~n382);
assign n398 = n198 & n397 & (n270 | ~n381);
assign n399 = n155 | ~n382;
assign n400 = n136 & (n239 | n155);
assign n401 = n369 | (n355 & n386);
assign n402 = n443 | n373;
assign n403 = n435 | n438;
assign n404 = n149 & n402 & (n373 | n403);
assign n405 = n236 & (n239 | n373);
assign n406 = n372 & (n393 | n373);
assign n407 = n409 | n445;
assign n408 = n459 & n460;
assign n409 = ~i_0_ | ~i_1_ | i_2_;
assign n410 = n407 & n408 & (n393 | n409);
assign n411 = n436 | n157;
assign n412 = n157 | ~n381;
assign n413 = n137 & (n339 | ~n381);
assign n414 = n391 & n565 & n534;
assign n415 = ~n339 & (~n154 | n366);
assign n416 = n271 & n377;
assign n417 = n471 & n379;
assign n418 = n407 & n455 & n456;
assign n419 = n385 & (n373 | ~n381);
assign n420 = n412 & (n157 | ~n382);
assign n421 = n155 | ~n366;
assign n422 = n421 & (n155 | n154);
assign n423 = n339 | (n239 & n393);
assign n424 = n373 | n393;
assign n425 = n155 | (n356 & n378);
assign n426 = n425 & (n155 | n370);
assign n427 = n434 | n270;
assign n428 = n270 | (n386 & n403);
assign n429 = n280 & n427 & n428;
assign n430 = n409 | (n434 & n443);
assign n431 = n386 & n355 & n430;
assign n432 = i_3_ | i_4_ | i_5_;
assign n433 = ~i_6_ | ~i_7_;
assign n434 = n432 | n433;
assign n435 = i_3_ | i_4_ | ~i_5_;
assign n436 = n433 | n435;
assign n437 = i_5_ | ~i_3_ | i_4_;
assign n438 = i_6_ | i_7_;
assign n439 = n437 | n438;
assign n440 = i_6_ | ~i_7_;
assign n441 = n437 | n440;
assign n442 = ~i_6_ | i_7_;
assign n443 = n432 | n442;
assign n444 = ~i_5_ | ~i_3_ | i_4_;
assign n445 = n433 | n444;
assign n446 = n433 | n437;
assign n447 = n369 | n441;
assign n448 = n369 | n439;
assign n449 = n369 | n446;
assign n450 = n437 | n442;
assign n451 = n447 & n448 & n449 & n450;
assign n452 = n436 | n369;
assign n453 = n369 | n445;
assign n454 = ~n367 & n453;
assign n455 = n409 | n356;
assign n456 = n409 | n378;
assign n457 = n409 | n446;
assign n458 = n457 & n418;
assign n459 = n439 | n409;
assign n460 = n441 | n409;
assign n461 = n403 & n431;
assign n462 = n432 | n438;
assign n463 = n432 | n440;
assign n464 = n339 | n462;
assign n465 = n339 | n463;
assign n466 = n403 | n339;
assign n467 = n466 & n271;
assign n468 = n270 | n441;
assign n469 = n468 & n396;
assign n470 = n270 | n446;
assign n471 = n270 | n445;
assign n472 = n270 | n370;
assign n473 = n470 & n379 & n471 & n472;
assign n474 = n270 | ~n366;
assign n475 = n474 & n473;
assign n476 = n270 | ~n382;
assign n477 = n476 & n469;
assign n478 = n377 & n467;
assign n479 = n386 | n339;
assign n480 = n355 | n339;
assign n481 = n479 & n375 & n137 & n480;
assign n482 = n155 | n445;
assign n483 = n270 | n463;
assign n484 = n427 & n200 & n483;
assign n485 = n484 & n380;
assign n486 = n270 | n462;
assign n487 = n486 & n156;
assign n488 = n155 | n462;
assign n489 = n155 | n463;
assign n490 = n255 & n242;
assign n491 = n434 | n155;
assign n492 = n387 & n491 & n490;
assign n493 = n136 & n327;
assign n494 = n446 | n157;
assign n495 = n441 | n157;
assign n496 = n494 & n495;
assign n497 = n355 | n157;
assign n498 = n386 | n157;
assign n499 = n411 & n497 & n498;
assign n500 = n403 | n157;
assign n501 = n500 & n499;
assign n502 = n434 | n157;
assign n503 = n502 & n501;
assign n504 = n443 | n157;
assign n505 = n412 & n504 & n503;
assign n506 = n157 | n463;
assign n507 = n445 | n152;
assign n508 = n378 & n325;
assign n509 = n441 | n373;
assign n510 = n439 | n373;
assign n511 = n509 & n510;
assign n512 = n373 | n463;
assign n513 = n373 | n462;
assign n514 = n157 | ~n382;
assign n515 = n439 | n157;
assign n516 = n369 | n443;
assign n517 = n393 | n409;
assign n518 = n486 & n156 & n484;
assign n519 = n378 | n157;
assign n520 = n356 | n157;
assign n521 = n584 & n491 & n255;
assign n522 = n521 & n489 & n488 & n349 & n351 & n388 & n389 & ~n390;
assign n523 = n494 & n522;
assign n524 = n514 & n330;
assign n525 = n439 | n339;
assign n526 = n441 | n339;
assign n527 = n355 | n152;
assign n528 = n386 | n152;
assign n529 = n403 | n152;
assign n530 = n443 | n152;
assign n531 = n436 | n152;
assign n532 = n141 & n229 & n305;
assign n533 = n137 & n201 & ~n395;
assign n534 = n446 | n339;
assign n535 = n230 & n532 & n534 & n228;
assign n536 = n516 & n181 & n178;
assign n537 = n239 | n369;
assign n538 = n537 & n451 & n454 & n401 & n371;
assign n539 = n407 & n455;
assign n540 = ~n366 | n409;
assign n541 = n409 | n370;
assign n542 = n540 & n408 & n539 & n456 & n541 & n457;
assign n543 = n452 & n538;
assign n544 = n369 | n403;
assign n545 = n154 | n409;
assign n546 = n544 & n545 & n199;
assign n547 = n513 & n512;
assign n548 = n154 | n152;
assign n549 = n325 & n547 & n353 & n548;
assign n550 = n147 & n378 & n370;
assign n551 = n152 | ~n382;
assign n552 = n409 | n462;
assign n553 = n239 | n409;
assign n554 = n543 & n546 & n461 & n542 & n552 & n553 & n179 & n362;
assign n555 = n373 | ~n382;
assign n556 = n446 | n373;
assign n557 = n356 | n373;
assign n558 = n378 | n373;
assign n559 = n373 | n370;
assign n560 = n511 & n169 & n406 & n557 & n558 & n559;
assign n561 = n136 & ~n383;
assign n562 = n515 & n514 & n412;
assign n563 = n502 & n168;
assign n564 = n507 & n353;
assign n565 = n339 | n370;
assign n566 = n356 | n339;
assign n567 = n138 & n566;
assign n568 = n531 & n527 & n528;
assign n569 = n153 & n333;
assign n570 = n144 & n299;
assign n571 = n149 & n419;
assign n572 = n362 & n552 & n461;
assign n573 = n326 & n571 & n524 & n168;
assign n574 = n452 & n537 & n401;
assign n575 = n517 & n199;
assign n576 = n544 & n574;
assign n577 = n153 & n333 & n144 & n147;
assign n578 = n558 & n424 & n372 & n557;
assign n579 = n509 & n510 & n555;
assign n580 = n350 & n490;
assign n581 = n169 & n579;
assign n582 = n473 & n536 & n569 & n150 & n458 & n271;
assign n583 = n270 | ~n381;
assign n584 = n155 | n403;
assign n585 = n466 & n416 & n480 & n479;
assign n586 = n429 & n281 & n263;
assign n587 = n534 & n494;
assign n588 = n457 & n261 & n470;
assign n589 = n580 & n587 & n568 & n574 & n536 & n177 & n388 & n400;
assign n590 = n142 & n530;
assign n591 = n451 & n408 & n374;
assign n592 = n145 & n339 & n474;
assign n593 = n510 & n525 & n464;
assign n594 = n239 | n270;
assign n595 = n545 & n260;
assign n596 = n151 & n402 & n427;
assign n597 = n418 & n475 & n522 & n534 & n348 & n399;
endmodule |
module alu4 (
i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_, i_10_,
i_11_, i_12_, i_13_,
o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_ );
input i_0_, i_1_, i_2_, i_3_, i_4_, i_5_, i_6_, i_7_, i_8_, i_9_,
i_10_, i_11_, i_12_, i_13_;
output o_0_, o_1_, o_2_, o_3_, o_4_, o_5_, o_6_, o_7_;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, n135,
n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194, n195,
n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, n303,
n304, n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398, n399,
n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663,
n664, n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751;
assign o_0_ = ~n42;
assign o_1_ = ~n509;
assign o_2_ = ~n502;
assign o_3_ = ~n488;
assign o_4_ = ~n41;
assign o_5_ = ~n659 | ~n662 | n40 | ~n658 | n38 | n39 | n36 | n37;
assign o_6_ = ~n35;
assign o_7_ = ~n636 | ~n637 | n34 | ~n576 | n32 | n33 | n30 | n31;
assign n30 = ~i_9_ & (~n163 | n165 | n168);
assign n31 = i_9_ & n65 & n419;
assign n32 = ~i_5_ & (~n625 | (~n238 & n250));
assign n33 = i_9_ & (n66 | ~n621 | ~n622);
assign n34 = n244 | n246 | n240 | n242 | ~n630 | ~n632 | n248 | n249;
assign n35 = n278 & n279 & (~i_2_ | n277);
assign n36 = i_11_ & (~n650 | (~n266 & n360));
assign n37 = i_2_ & n361 & n272;
assign n38 = ~n71 & ~n532;
assign n39 = ~n562 & (~n648 | (~i_13_ & ~n532));
assign n40 = ~i_4_ & (~n647 | (~n59 & ~n281));
assign n41 = n473 & n472 & n471 & n470 & n469 & ~n465 & ~n459 & ~n461;
assign n42 = ~n46 & n510 & (~i_0_ | n511);
assign n43 = ~i_1_ | ~i_3_;
assign n44 = ~i_5_ | n43;
assign n45 = ~i_8_ & i_10_;
assign n46 = i_3_ & (n45 | ~n435);
assign n47 = ~n67 & (~i_6_ | ~i_10_);
assign n48 = (n521 | n52) & (n56 | n120);
assign n49 = i_1_ | n445;
assign n50 = i_11_ | n116;
assign n51 = n48 & (n49 | n50);
assign n52 = i_12_ | n116;
assign n53 = i_0_ | n225;
assign n54 = (i_11_ | n53) & (n49 | n52);
assign n55 = ~i_6_ | i_7_;
assign n56 = i_0_ | n212;
assign n57 = ~i_2_ | i_0_ | i_1_;
assign n58 = (i_6_ | n57) & (n55 | n56);
assign n59 = ~i_3_ | n225;
assign n60 = ~i_3_ | n445;
assign n61 = (~i_6_ | n60) & (~i_5_ | n59);
assign n62 = i_0_ | n63;
assign n63 = i_3_ | i_2_;
assign n64 = n62 & (~i_5_ | n63);
assign n65 = ~i_12_ & i_13_;
assign n66 = n65 & (~n613 | (i_8_ & ~n379));
assign n67 = i_6_ & n519;
assign n68 = ~n158 & (~n615 | (n67 & ~n400));
assign n69 = (i_7_ | n200) & (i_6_ | n62);
assign n70 = n69 & (i_8_ | n56);
assign n71 = ~i_12_ | n116;
assign n72 = (~i_1_ | n71) & (~i_6_ | ~n348);
assign n73 = ~i_1_ & i_6_;
assign n74 = (~i_0_ | n73) & (~i_1_ | i_5_);
assign n75 = ~n304 & ~i_9_ & ~n77;
assign n76 = i_3_ & (n75 | (~n71 & ~n98));
assign n77 = ~i_11_ | n116;
assign n78 = i_8_ | i_6_;
assign n79 = n77 | n78 | ~i_2_ | i_9_;
assign n80 = ~i_0_ | n63;
assign n81 = ~i_0_ | n195;
assign n82 = (i_7_ | n81) & (i_6_ | n80);
assign n83 = i_0_ & (n76 | ~n79 | ~n627);
assign n84 = i_3_ | ~i_11_ | n56 | ~n348;
assign n85 = n116 | n400 | ~i_3_ | i_9_;
assign n86 = n178 | ~i_5_ | n72;
assign n87 = n516 | n177 | ~n338;
assign n88 = i_9_ | n74 | n522 | n77;
assign n89 = n88 & n87 & n86 & n85 & ~n83 & n84;
assign n90 = (n99 | n157) & (n134 | n521);
assign n91 = ~i_6_ | n522;
assign n92 = n90 & (n91 | n49);
assign n93 = (~n102 | n521) & (~n67 | n157);
assign n94 = (n518 | n49) & (n520 | n400);
assign n95 = n93 & n94;
assign n96 = (~n103 | n134) & (n53 | n107);
assign n97 = n96 & (n57 | n91);
assign n98 = ~i_6_ | n272;
assign n99 = i_8_ | ~i_6_ | ~i_7_;
assign n100 = n98 & n97 & (n99 | n56);
assign n101 = i_5_ & n365;
assign n102 = ~i_6_ & n519;
assign n103 = ~i_2_ & ~i_0_ & i_1_;
assign n104 = n101 & (~n607 | (n102 & n103));
assign n105 = i_11_ | ~n166;
assign n106 = i_10_ | n304;
assign n107 = i_6_ | n522;
assign n108 = (n107 | n50) & (n105 | n106);
assign n109 = i_12_ | n113;
assign n110 = i_11_ | n113;
assign n111 = (~n67 | n109) & (n99 | n110);
assign n112 = i_11_ | i_12_;
assign n113 = i_9_ | i_13_;
assign n114 = i_3_ | i_10_ | n112 | n113;
assign n115 = i_5_ | n312;
assign n116 = i_10_ | i_13_;
assign n117 = (~i_10_ | n115) & (n116 | ~n164);
assign n118 = i_13_ & (~n600 | (~n547 & ~n548));
assign n119 = i_5_ | n515;
assign n120 = i_12_ | ~n338;
assign n121 = (n119 | n120) & (~n164 | ~n239);
assign n122 = n65 & (~n599 | (~i_3_ & ~i_11_));
assign n123 = n555 | n518 | n554;
assign n124 = n553 | n134 | n552;
assign n125 = n522 | n198 | ~n247;
assign n126 = ~n348 | ~n67 | ~n101;
assign n127 = n449 | n107 | ~n338;
assign n128 = n524 | n99 | ~n319;
assign n129 = (n544 | n546) & (n121 | n520);
assign n130 = n129 & n128 & n127 & n126 & n125 & n124 & ~n122 & n123;
assign n131 = (n107 | ~n419) & (n91 | ~n402);
assign n132 = (n171 | n151) & (n150 | n551);
assign n133 = n597 & n598 & (n545 | n550);
assign n134 = ~i_7_ | n78;
assign n135 = ~n101 | ~n239;
assign n136 = n132 & n133 & (n134 | n135);
assign n137 = i_4_ | ~i_0_ | ~i_1_;
assign n138 = i_4_ | n445;
assign n139 = (~i_6_ | n138) & (~i_7_ | n137);
assign n140 = ~n524 & ~n220 & i_2_ & ~i_8_;
assign n141 = n546 | n549;
assign n142 = n162 | n107 | n158;
assign n143 = n555 | ~n102 | n554;
assign n144 = n553 | n91 | n552;
assign n145 = (n194 | n151) & (n198 | n551);
assign n146 = (n134 | n543) & (n547 | n550);
assign n147 = n146 & n145 & n144 & n143 & n141 & n142;
assign n148 = (n171 | n551) & (n99 | n543);
assign n149 = n595 & n596 & (n545 | n549);
assign n150 = ~i_5_ | n201;
assign n151 = ~n65 | ~n264;
assign n152 = n148 & n149 & (n150 | n151);
assign n153 = (n99 | ~n402) & (n91 | ~n419);
assign n154 = (n544 | n547) & (n172 | n198);
assign n155 = n593 & n594 & (n542 | n546);
assign n156 = n154 & n155 & (n91 | n135);
assign n157 = ~i_0_ | n212;
assign n158 = ~i_5_ | n312;
assign n159 = n158 | n157 | n134;
assign n160 = n115 | n99 | ~n103;
assign n161 = i_2_ | n312;
assign n162 = ~i_10_ | ~n319;
assign n163 = n161 | n162 | ~i_5_ | n91;
assign n164 = ~i_5_ & i_3_ & i_4_;
assign n165 = n164 & ~n77 & i_1_ & ~i_7_;
assign n166 = ~i_12_ & ~i_13_;
assign n167 = i_10_ & i_11_;
assign n168 = n166 & n167 & (~n159 | ~n160);
assign n169 = (n542 | n545) & (n541 | n150);
assign n170 = (n107 | n135) & (~n446 | n544);
assign n171 = i_3_ | n539;
assign n172 = ~n65 | ~n437;
assign n173 = n169 & n170 & (n171 | n172);
assign n174 = (~n446 | n542) & (n171 | n541);
assign n175 = (n544 | n545) & (n91 | n543);
assign n176 = n174 & n175 & (n172 | n150);
assign n177 = i_10_ | n522;
assign n178 = ~i_8_ | n272;
assign n179 = n177 & n178;
assign n180 = (~n460 | n591) & (n179 | ~n463);
assign n181 = n592 & (n533 | n56);
assign n182 = n106 & n98;
assign n183 = n180 & n181 & (n182 | ~n385);
assign n184 = (~n340 | n535) & (n106 | n449);
assign n185 = i_8_ | n534;
assign n186 = ~i_4_ | n212;
assign n187 = n184 & (n185 | n186);
assign n188 = (~n536 | n537) & (n335 | n538);
assign n189 = (n186 | n474) & (n98 | ~n101);
assign n190 = ~i_5_ | n272;
assign n191 = n188 & n189 & (n190 | ~n340);
assign n192 = (n518 | n521) & (n520 | n157);
assign n193 = n192 & (n49 | ~n102);
assign n194 = i_3_ | n214;
assign n195 = i_1_ | i_3_;
assign n196 = n194 & (~i_5_ | n195);
assign n197 = ~i_6_ | i_0_ | i_3_;
assign n198 = i_3_ | n516;
assign n199 = n198 & (i_5_ | n195);
assign n200 = i_0_ | n195;
assign n201 = i_3_ | i_6_;
assign n202 = n200 & n199 & (i_0_ | n201);
assign n203 = ~i_6_ | ~i_0_ | ~i_3_;
assign n204 = i_1_ & ~i_6_;
assign n205 = (i_2_ | ~i_6_) & (~i_7_ | n204);
assign n206 = n517 | i_6_ | n749;
assign n207 = n517 | i_1_ | i_7_;
assign n208 = i_11_ | n435;
assign n209 = n206 & n207 & (n205 | n208);
assign n210 = i_5_ | n63;
assign n211 = i_2_ | n516;
assign n212 = i_1_ | i_2_;
assign n213 = n211 & (i_5_ | n212);
assign n214 = ~i_5_ | ~i_6_;
assign n215 = (~i_5_ | n212) & (i_2_ | n214);
assign n216 = (~i_5_ | n225) & (~i_2_ | n214);
assign n217 = ~i_6_ | n445;
assign n218 = n216 & n217;
assign n219 = ~i_7_ | ~i_1_ | ~i_5_;
assign n220 = ~i_1_ & ~i_6_;
assign n221 = n219 & (~i_0_ | ~i_7_ | n220);
assign n222 = i_10_ & ~n435 & (~n218 | ~n221);
assign n223 = ~i_2_ | n516;
assign n224 = i_6_ | n445;
assign n225 = ~i_1_ | ~i_2_;
assign n226 = n223 & n224 & (i_5_ | n225);
assign n227 = n226 & (i_7_ | n74);
assign n228 = (~i_0_ | i_6_) & (~i_1_ | i_5_);
assign n229 = (i_6_ | n138) & (i_7_ | n137);
assign n230 = n73 | n119 | ~i_2_ | ~i_8_;
assign n231 = n230 & (n229 | ~n475);
assign n232 = (n53 | ~n67) & (~n103 | n518);
assign n233 = n232 & (n57 | ~n102);
assign n234 = ~i_4_ | n225;
assign n235 = ~i_4_ | n557;
assign n236 = (i_6_ | n235) & (i_8_ | n234);
assign n237 = i_4_ & (~n623 | (~i_1_ & ~n177));
assign n238 = ~n237 & (i_6_ | i_10_ | ~n536);
assign n239 = ~i_9_ & n338;
assign n240 = n239 & n164 & ~n233;
assign n241 = n406 & ~i_10_ & ~i_13_;
assign n242 = ~n119 & (~n580 | (~n92 & n241));
assign n243 = ~i_3_ & ~i_8_;
assign n244 = ~n525 & (n140 | (~n139 & n243));
assign n245 = n383 & ~i_9_ & ~i_13_;
assign n246 = ~n524 & (~n582 | (~n193 & n245));
assign n247 = ~i_11_ & i_13_;
assign n248 = n247 & (~n584 | (~n223 & ~n528));
assign n249 = n65 & (~n586 | ~n588 | ~n590);
assign n250 = n338 & i_12_;
assign n251 = n250 & (~n183 | ~n187 | ~n191);
assign n252 = ~n71 & (~n609 | ~n610 | ~n611);
assign n253 = ~n247 & (i_4_ | ~i_8_ | ~n406);
assign n254 = (~i_3_ | n208) & (~n338 | n533);
assign n255 = n253 & n254 & (n120 | ~n475);
assign n256 = ~i_7_ | i_10_;
assign n257 = i_4_ | ~n383;
assign n258 = (~i_7_ | n257) & (n256 | ~n318);
assign n259 = i_7_ & n45;
assign n260 = (i_8_ | n258) & (~n259 | n559);
assign n261 = n260 & ~n731 & (i_7_ | n255);
assign n262 = ~i_7_ | ~i_9_;
assign n263 = n262 & (i_7_ | ~i_10_);
assign n264 = i_10_ & ~i_7_ & i_8_;
assign n265 = i_12_ & (n264 | ~n548);
assign n266 = ~i_10_ | n522;
assign n267 = i_8_ | n262;
assign n268 = ~n265 & (~i_11_ | (n266 & n267));
assign n269 = (n110 | ~n243) & (n109 | ~n475);
assign n270 = ~i_4_ | n116;
assign n271 = n270 & (~i_8_ | n52);
assign n272 = ~i_7_ | i_9_;
assign n273 = ~i_4_ | n272;
assign n274 = (i_7_ | n271) & (i_13_ | n273);
assign n275 = n282 & (i_4_ | n268);
assign n276 = n556 & n638 & (i_3_ | n274);
assign n277 = n275 & n276 & (~i_13_ | n263);
assign n278 = ~n750 & (n548 | n559);
assign n279 = n644 & n645 & (i_2_ | n261);
assign n280 = ~i_6_ | ~i_9_;
assign n281 = n280 & (i_6_ | ~i_10_);
assign n282 = n332 | n116;
assign n283 = (n523 & (~i_7_ | n733)) | (i_7_ & n733);
assign n284 = i_2_ | i_13_;
assign n285 = n282 & (n283 | n284);
assign n286 = i_10_ | i_7_;
assign n287 = i_11_ | n286;
assign n288 = i_11_ | i_13_;
assign n289 = (~n166 | n287) & (n177 | n288);
assign n290 = i_8_ | n272;
assign n291 = (n288 | n290) & (~n166 | n178);
assign n292 = (n289 & (~i_6_ | n291)) | (i_6_ & n291);
assign n293 = (n523 & (~i_8_ | n733)) | (i_8_ & n733);
assign n294 = n292 & (i_13_ | n293);
assign n295 = (~i_7_ & n566) | (n565 & (i_7_ | n566));
assign n296 = i_7_ | n435;
assign n297 = n295 & (~i_6_ | ~i_11_ | n296);
assign n298 = n287 & (i_12_ | n256);
assign n299 = ~i_2_ & ~n751 & (i_6_ | ~n298);
assign n300 = ~n299 & (~i_4_ | ~n578);
assign n301 = n591 | i_2_ | ~i_4_;
assign n302 = n300 & n301 & (n182 | ~n365);
assign n303 = ~i_7_ | n280;
assign n304 = i_6_ | i_7_;
assign n305 = n303 & (~i_10_ | (~i_9_ & n304));
assign n306 = (i_6_ & ~n540) | (~n266 & (~i_6_ | ~n540));
assign n307 = ~i_4_ & (~n577 | (i_11_ & n306));
assign n308 = (n294 & (~i_3_ | n297)) | (i_3_ & n297);
assign n309 = (~i_13_ & n302) | (n281 & (i_13_ | n302));
assign n310 = ~n307 & n656 & (~i_2_ | n305);
assign n311 = n310 & n309 & n308 & n285;
assign n312 = ~i_3_ | i_4_;
assign n313 = (n312 | ~n406) & (n284 | ~n383);
assign n314 = (~i_4_ | ~n338) & (i_3_ | n120);
assign n315 = ~n247 & (~i_3_ | ~n406 | n548);
assign n316 = (~i_2_ | n530) & (~i_7_ | n313);
assign n317 = n315 & n316 & (n314 | n178);
assign n318 = i_4_ & n348;
assign n319 = ~i_11_ & n348;
assign n320 = ~n177 & (n318 | (~i_3_ & n319));
assign n321 = ~n402 | ~i_2_ | i_7_;
assign n322 = ~n319 | n563;
assign n323 = ~n383 | ~i_3_ | n266;
assign n324 = n257 | ~i_2_ | i_8_;
assign n325 = ~n65 & (i_7_ | n312 | ~n383);
assign n326 = n325 & n324 & n323 & n322 & ~n320 & n321;
assign n327 = i_11_ | ~n496 | n558 | ~n563;
assign n328 = (n317 & (~i_6_ | n326)) | (i_6_ & n326);
assign n329 = n327 & n328 & (n91 | n257);
assign n330 = ~i_11_ | n514;
assign n331 = ~n166 | ~n475;
assign n332 = ~i_4_ | i_9_;
assign n333 = (n332 | n77) & (n330 | n331);
assign n334 = ~n517 & i_3_ & i_12_;
assign n335 = i_1_ | n63;
assign n336 = ~i_11_ | ~n166;
assign n337 = (n335 | n336) & (n186 | ~n239);
assign n338 = i_11_ & ~i_13_;
assign n339 = i_4_ & (~n652 | (~n335 & n338));
assign n340 = ~i_1_ & n365;
assign n341 = i_7_ & (n334 | (n340 & n239));
assign n342 = n734 & (~i_8_ | n337);
assign n343 = (n208 | n561) & (n404 | n356);
assign n344 = (n517 | n557) & (~n45 | n59);
assign n345 = n344 & n343 & n342 & ~n341 & n333 & ~n339;
assign n346 = ~i_2_ | i_12_;
assign n347 = (~i_8_ | n59) & (n346 | ~n391);
assign n348 = i_12_ & ~i_13_;
assign n349 = n348 & (~n654 | (i_4_ & ~n335));
assign n350 = n655 & (i_8_ | ~n402 | n561);
assign n351 = ~n349 & n350 & (~i_9_ | n347);
assign n352 = ~i_8_ | i_9_;
assign n353 = (~n263 | ~n340) & (n186 | n352);
assign n354 = i_10_ | n78;
assign n355 = ~i_6_ | n352;
assign n356 = ~i_1_ | n312;
assign n357 = (n303 | n356) & (~n259 | ~n360);
assign n358 = ~n573 & (~i_4_ | i_13_ | ~n496);
assign n359 = ~n512 & (i_6_ | i_11_);
assign n360 = i_3_ & n204;
assign n361 = ~i_6_ & n419;
assign n362 = ~i_9_ | ~i_11_;
assign n363 = ~i_12_ | n362;
assign n364 = ~i_4_ | n113;
assign n365 = ~i_3_ & i_4_;
assign n366 = ~i_9_ | ~i_12_;
assign n367 = n364 & (n365 | n366);
assign n368 = (~i_9_ & n572) | (~i_13_ & (i_9_ | n572));
assign n369 = i_3_ | n111;
assign n370 = ~n166 | i_2_ | n98;
assign n371 = (~i_1_ | n280) & (n363 | ~n391);
assign n372 = (~n67 | n367) & (i_4_ | n363);
assign n373 = ~n737 & n372 & n371 & n370 & n368 & n369;
assign n374 = ~i_4_ & (~n564 | (~n107 & n167));
assign n375 = ~n736 & (~i_10_ | (~i_13_ & ~n204));
assign n376 = ~n374 & n687 & (n107 | n270);
assign n377 = n375 & n376 & (i_3_ | n108);
assign n378 = i_7_ | n516;
assign n379 = ~i_7_ | n214;
assign n380 = (n113 | n379) & (n378 | n116);
assign n381 = ~i_2_ & (~n686 | (~n270 & ~n440));
assign n382 = ~n53 & i_3_ & ~i_8_;
assign n383 = i_11_ & ~i_12_;
assign n384 = n383 & i_10_ & ~i_0_ & i_2_;
assign n385 = ~i_0_ & n365;
assign n386 = ~i_6_ & (n384 | (~n71 & n385));
assign n387 = (n56 | ~n319) & (n53 | ~n402);
assign n388 = i_0_ | n43;
assign n389 = ~n386 & n387 & (n257 | n388);
assign n390 = (~i_7_ | n81) & (~i_6_ | n80);
assign n391 = i_8_ & i_3_;
assign n392 = ~n400 & (i_7_ | n391);
assign n393 = (i_3_ & n553) | (~n241 & (~i_3_ | n553));
assign n394 = n257 & n393 & (~i_4_ | n71);
assign n395 = ~i_12_ | n572;
assign n396 = ~n65 & (i_2_ | n106 | ~n319);
assign n397 = n395 & n396 & (n394 | n107);
assign n398 = ~i_7_ | n362;
assign n399 = (i_2_ | n355) & (n204 | n178);
assign n400 = ~i_1_ | n445;
assign n401 = (~i_8_ | n400) & (~i_6_ | n60);
assign n402 = i_10_ & ~i_12_;
assign n403 = n402 & (n382 | (~i_0_ & n204));
assign n404 = i_7_ | ~n167;
assign n405 = n167 & (~n718 | (~i_8_ & ~n400));
assign n406 = ~i_11_ & i_12_;
assign n407 = n406 & (~n674 | (i_8_ & ~n53));
assign n408 = ~i_0_ | n43;
assign n409 = ~n405 & ~n407 & (n404 | n408);
assign n410 = ~n247 & (~i_1_ | i_11_ | n280);
assign n411 = n672 & (~n67 | (~n423 & n673));
assign n412 = n410 & n411 & (~n73 | n336);
assign n413 = ~n385 | ~i_6_ | ~n239;
assign n414 = ~n166 | ~i_11_ | n56;
assign n415 = n413 & n414 & (n200 | ~n423);
assign n416 = n238 & (~i_4_ | i_6_ | n177);
assign n417 = ~i_7_ & n419;
assign n418 = n417 & i_2_ & i_12_;
assign n419 = i_10_ & ~i_11_;
assign n420 = n116 | ~i_4_ | i_8_;
assign n421 = n420 & (n50 | ~n243);
assign n422 = ~n53 & (~n530 | (i_3_ & ~n208));
assign n423 = i_4_ & n239;
assign n424 = i_6_ & (n418 | (~n62 & n423));
assign n425 = (n517 | n59) & (i_4_ | n409);
assign n426 = (~i_7_ | n415) & (i_0_ | n412);
assign n427 = (n82 | n271) & (~n338 | n416);
assign n428 = (~i_1_ | ~n361) & (~n423 | n671);
assign n429 = (n157 | n421) & (n400 | ~n670);
assign n430 = ~n422 & (n56 | n120 | ~n475);
assign n431 = n430 & n429 & n428 & n427 & n426 & n425 & n333 & ~n424;
assign n432 = n183 & (~i_4_ | i_10_ | n70);
assign n433 = i_7_ | i_9_ | i_11_;
assign n434 = n191 & (n215 | n433);
assign n435 = ~i_8_ | ~i_9_;
assign n436 = i_5_ & ~n558 & (~n540 | ~n568);
assign n437 = i_10_ & n519;
assign n438 = ~i_4_ & ~n539 & (n437 | ~n568);
assign n439 = ~i_8_ | n214;
assign n440 = i_8_ | n516;
assign n441 = (n366 | n439) & (~n167 | n440);
assign n442 = ~i_12_ & (~n158 | n417 | ~n530);
assign n443 = n435 | ~i_3_ | n112;
assign n444 = ~n442 & n443 & (i_11_ | n115);
assign n445 = ~i_0_ | ~i_2_;
assign n446 = ~i_6_ & i_3_ & i_5_;
assign n447 = n383 & (~n684 | (~i_7_ & n446));
assign n448 = n406 & (~n685 | (i_7_ & ~n545));
assign n449 = i_5_ | ~n365;
assign n450 = (~n338 | n449) & (~n101 | ~n348);
assign n451 = i_5_ | n522;
assign n452 = (n80 | n440) & (n81 | n451);
assign n453 = ~i_5_ | ~n519;
assign n454 = (n453 | n81) & (n439 | n80);
assign n455 = n137 & n408;
assign n456 = ~i_0_ | n312;
assign n457 = (n379 | n456) & (n455 | n453);
assign n458 = ~i_5_ & i_0_ & i_3_;
assign n459 = n167 & (~n663 | (~n107 & n458));
assign n460 = i_4_ & ~i_0_ & ~i_2_;
assign n461 = ~n569 & (~n664 | (n239 & n460));
assign n462 = ~i_5_ & n519;
assign n463 = i_4_ & ~i_0_ & ~i_1_;
assign n464 = n462 & (~n665 | (n239 & n463));
assign n465 = ~n570 & (~n666 | (~n71 & n463));
assign n466 = ~n571 & (~n667 | (~n71 & n460));
assign n467 = n406 & (n438 | (n259 & ~n545));
assign n468 = n383 & (n436 | (~n296 & n446));
assign n469 = (n450 | n56) & (n441 | n60);
assign n470 = ~n464 & (~i_9_ | n158 | n400);
assign n471 = n702 & n701 & (n452 | n50);
assign n472 = n699 & n698 & (n457 | n366);
assign n473 = ~n740 & ~n739 & n709 & n707 & n706 & n705 & n703 & n704;
assign n474 = ~i_5_ | n352;
assign n475 = ~i_3_ & i_8_;
assign n476 = ~n56 & (i_7_ | n475);
assign n477 = (i_1_ | n537) & (n589 | n178);
assign n478 = ~n476 & n715 & (n335 | n474);
assign n479 = n477 & n478 & (i_0_ | ~i_5_);
assign n480 = ~n56 & (~i_7_ | n243);
assign n481 = n300 & (i_1_ | n359);
assign n482 = n746 & (i_5_ | n416);
assign n483 = n187 & (i_3_ | n293);
assign n484 = (n56 | ~n365) & (i_12_ | n479);
assign n485 = (n213 | n298) & (n215 | n574);
assign n486 = n716 & (i_1_ | n359 | n534);
assign n487 = n717 & (i_11_ | (n714 & n711));
assign n488 = n487 & n486 & n485 & n484 & n483 & n482 & n432 & n434;
assign n489 = ~i_7_ | n366;
assign n490 = ~i_10_ | ~i_12_;
assign n491 = n489 & ~n496 & (i_7_ | n490);
assign n492 = (n747 & (~i_5_ | n748)) | (i_5_ & n748);
assign n493 = n492 & (~i_0_ | n281);
assign n494 = i_8_ | ~i_11_;
assign n495 = ~n496 & n494 & ~i_3_ & n263;
assign n496 = i_8_ & i_12_;
assign n497 = n496 & (~n221 | ~n379);
assign n498 = (n218 | n491) & (~i_1_ | n493);
assign n499 = n726 & (~i_12_ | (n61 & n723));
assign n500 = n725 & (~i_11_ | (n719 & n722));
assign n501 = n724 & (n494 | (n227 & n378));
assign n502 = n501 & n500 & n498 & n499;
assign n503 = i_12_ | ~n475;
assign n504 = ~n46 & n503 & (i_11_ | ~n243);
assign n505 = (~n243 | ~n338) & (n113 | ~n391);
assign n506 = (~n243 | ~n247) & (~n65 | ~n475);
assign n507 = (n504 & (~i_4_ | n505)) | (i_4_ & n505);
assign n508 = n727 & n728 & (~i_13_ | ~n46);
assign n509 = n508 & n506 & n507;
assign n510 = (~i_1_ | n281) & (~i_2_ | n263);
assign n511 = (~i_5_ & ~i_10_) | (~i_9_ & (i_5_ | ~i_10_));
assign n512 = i_6_ & ~i_12_;
assign n513 = i_9_ & (n392 | (n512 & i_1_));
assign n514 = i_9_ | i_10_;
assign n515 = i_3_ | i_4_;
assign n516 = i_5_ | i_6_;
assign n517 = i_8_ | ~n419;
assign n518 = ~i_8_ | n55;
assign n519 = i_8_ & i_7_;
assign n520 = ~i_8_ | n304;
assign n521 = i_2_ | ~i_0_ | ~i_1_;
assign n522 = i_8_ | i_7_;
assign n523 = i_11_ | n514;
assign n524 = ~i_5_ | n515;
assign n525 = ~n348 | n523;
assign n526 = ~i_9_ | ~i_10_;
assign n527 = i_7_ | n526;
assign n528 = ~i_3_ | n526;
assign n529 = ~i_7_ | n526;
assign n530 = i_11_ | n262;
assign n531 = ~i_5_ | ~i_3_ | ~i_4_;
assign n532 = ~i_6_ | n332;
assign n533 = ~i_8_ | n332;
assign n534 = i_5_ | i_10_;
assign n535 = i_7_ | n534;
assign n536 = ~i_2_ & n365;
assign n537 = i_9_ | n214;
assign n538 = ~i_5_ | n332;
assign n539 = i_5_ | ~i_6_;
assign n540 = ~i_9_ | n522;
assign n541 = ~n247 | n540;
assign n542 = ~n65 | ~n259;
assign n543 = ~n239 | n449;
assign n544 = ~n247 | n296;
assign n545 = ~i_3_ | n539;
assign n546 = ~i_3_ | n516;
assign n547 = ~i_3_ | n214;
assign n548 = ~i_7_ | n435;
assign n549 = ~n247 | n548;
assign n550 = ~n65 | n266;
assign n551 = ~n247 | n267;
assign n552 = i_13_ | n115;
assign n553 = ~i_11_ | ~n402;
assign n554 = i_13_ | n158;
assign n555 = ~i_9_ | ~n406;
assign n556 = n114 & n528;
assign n557 = ~i_2_ | ~i_3_;
assign n558 = i_4_ | i_6_;
assign n559 = ~i_3_ | i_12_;
assign n560 = i_4_ | n225;
assign n561 = i_1_ | n557;
assign n562 = ~i_1_ | n63;
assign n563 = i_7_ | i_2_;
assign n564 = ~i_11_ | n490;
assign n565 = ~i_9_ | n490;
assign n566 = ~i_9_ | ~n167;
assign n567 = ~i_8_ | n286;
assign n568 = i_0_ | n557;
assign n569 = ~i_8_ | n539;
assign n570 = ~i_5_ | n522;
assign n571 = ~i_5_ | n78;
assign n572 = ~n220 | n288;
assign n573 = n243 & n319;
assign n574 = i_12_ | n272;
assign n575 = (~i_5_ & n419) | (n402 & (i_5_ | n419));
assign n576 = (~i_4_ & n729) | (n89 & (i_4_ | n729));
assign n577 = (~i_6_ & n564) | (n363 & (i_6_ | n564));
assign n578 = (i_6_ & ~n178) | (~n177 & (~i_6_ | ~n178));
assign n579 = i_10_ | i_13_ | ~n383 | n520;
assign n580 = n579 & (n233 | ~n245);
assign n581 = i_9_ | i_13_ | n99 | ~n406;
assign n582 = n581 & (n97 | ~n241);
assign n583 = n527 | ~i_3_ | n228;
assign n584 = n583 & (i_8_ | n227 | n526);
assign n585 = (n213 | n517) & (n210 | ~n361);
assign n586 = ~n222 & n585 & (n208 | n215);
assign n587 = n547 & n408 & n44 & n203;
assign n588 = (n587 | n529) & (i_0_ | n209);
assign n589 = n196 & n200 & n197;
assign n590 = (n530 | n589) & (n202 | ~n417);
assign n591 = n355 & n354;
assign n592 = (n273 | n200) & (n62 | n532);
assign n593 = n541 | n194;
assign n594 = n113 | n153 | n158;
assign n595 = ~n402 | n107 | n158;
assign n596 = ~n446 | n550;
assign n597 = ~n446 | n549;
assign n598 = n113 | n131 | n158;
assign n599 = (~n259 | n547) & (n194 | ~n519);
assign n600 = n528 & (n546 | n266);
assign n601 = n531 | ~n67 | n113;
assign n602 = n601 & (n117 | n107);
assign n603 = (n99 | n135) & (n198 | n151);
assign n604 = n602 & n603 & (n194 | n551);
assign n605 = (n108 | n119) & (n111 | n524);
assign n606 = ~n118 & n605 & (i_4_ | n556);
assign n607 = (n518 | n57) & (n53 | n520);
assign n608 = (n95 | n449) & (n92 | ~n164);
assign n609 = ~n104 & n608 & (n100 | n531);
assign n610 = (n537 | n235) & (n474 | n234);
assign n611 = (n273 | n408) & (n538 | n59);
assign n612 = n64 | ~i_6_ | i_11_;
assign n613 = n612 & (~i_10_ | n61);
assign n614 = i_10_ | ~n103 | ~n319 | n520;
assign n615 = n614 & (n58 | n162);
assign n616 = i_10_ | n157 | ~n319 | n518;
assign n617 = n616 & (n47 | n57 | n120);
assign n618 = n617 & (n520 | n521 | n50);
assign n619 = (n54 | ~n67) & (n51 | ~n102);
assign n620 = n161 | n534 | ~n102 | n120;
assign n621 = n620 & (i_4_ | n59 | ~n575);
assign n622 = ~n68 & (n115 | (n618 & n619));
assign n623 = (i_2_ | n354) & (i_10_ | n335);
assign n624 = i_11_ | n266 | n59 | n558;
assign n625 = n624 & (i_9_ | n236 | n77);
assign n626 = n355 | ~i_2_ | n71;
assign n627 = n626 & (n220 | n71 | n178);
assign n628 = n332 | i_10_ | ~n250;
assign n629 = n628 & (~n166 | n231 | n330);
assign n630 = n629 & (~i_13_ | n378 | n517);
assign n631 = n531 | n193 | ~n239;
assign n632 = ~n251 & n631 & (~n103 | n176);
assign n633 = (n156 | n521) & (n173 | n157);
assign n634 = n633 & (n152 | n53);
assign n635 = (n136 | n49) & (n147 | n57);
assign n636 = n635 & n634 & (n130 | n56);
assign n637 = ~n252 & (n400 | (n604 & n606));
assign n638 = n730 & (~i_7_ | n269);
assign n639 = ~n435 | ~i_4_ | n77;
assign n640 = n639 & (i_8_ | i_13_ | n235);
assign n641 = (i_11_ | n161) & (~n338 | ~n536);
assign n642 = n235 | ~i_8_ | i_13_;
assign n643 = n642 & (~n348 | (n533 & ~n536));
assign n644 = n312 | ~i_2_ | n263;
assign n645 = ~n732 & (i_7_ | (n640 & n641));
assign n646 = ~n563 | ~n361 | ~n496;
assign n647 = n646 & (n359 | n561);
assign n648 = (n288 | n354) & (~n166 | n355);
assign n649 = ~i_8_ | i_3_ | i_6_ | n749 | i_10_ | ~n166;
assign n650 = n649 & (~n348 | n353);
assign n651 = i_10_ | i_13_ | n749 | n494;
assign n652 = n651 & (n116 | n562);
assign n653 = i_10_ | i_8_;
assign n654 = (n286 | ~n340) & (n186 | n653);
assign n655 = n335 | i_8_ | ~n319;
assign n656 = n365 | n548 | ~i_6_ | ~i_12_;
assign n657 = ~i_3_ | ~i_9_ | ~n383 | n518;
assign n658 = n657 & (n281 | ~n496 | n560);
assign n659 = (n358 | n98) & (n346 | n303);
assign n660 = (n345 & (~i_6_ | n351)) | (i_6_ & n351);
assign n661 = (~i_1_ & n329) | (n311 & (i_1_ | n329));
assign n662 = n660 & n661 & (~i_12_ | n357);
assign n663 = (n378 | n456) & (n455 | n451);
assign n664 = (n555 | n568) & (n62 | ~n245);
assign n665 = (n388 | n555) & (n200 | ~n245);
assign n666 = (n388 | n553) & (n200 | ~n241);
assign n667 = (n553 | n568) & (n62 | ~n241);
assign n668 = (n288 | n535) & (~n166 | n190);
assign n669 = (n116 | n449) & (~n101 | n113);
assign n670 = i_10_ & (~i_7_ | (i_3_ & ~i_8_));
assign n671 = ~i_8_ | n56;
assign n672 = n741 & (~i_2_ | n303 | ~n406);
assign n673 = (i_3_ & n555) | (~n245 & (~i_3_ | n555));
assign n674 = (~i_7_ | n388) & (i_0_ | ~n67);
assign n675 = ~n383 | i_8_ | n53;
assign n676 = n675 & (n401 | n366);
assign n677 = n157 | ~i_8_ | n113;
assign n678 = n677 & (~n348 | n399);
assign n679 = n346 | i_6_ | n398;
assign n680 = n679 & (n390 | n364);
assign n681 = (~n243 | n525) & (n157 | n269);
assign n682 = n680 & n681 & (n56 | ~n573);
assign n683 = (i_7_ | n389) & (i_0_ | n397);
assign n684 = (~i_2_ | n571) & (~i_1_ | n570);
assign n685 = (~i_2_ | n569) & (~i_1_ | ~n462);
assign n686 = (n364 | n439) & (n105 | n537);
assign n687 = n288 | i_2_ | n106;
assign n688 = (n451 | n270) & (n364 | n453);
assign n689 = n211 | i_10_ | n105;
assign n690 = n689 & (~i_9_ | n536 | n564);
assign n691 = ~n381 & n690 & (~n365 | n380);
assign n692 = i_3_ | i_13_ | n293;
assign n693 = n735 & (~i_6_ | ~i_12_ | n529);
assign n694 = n285 & n692 & (~i_3_ | n693);
assign n695 = (~i_5_ & n377) | (n373 & (i_5_ | n377));
assign n696 = n695 & ~n738 & (~i_1_ | n526);
assign n697 = n564 | i_8_ | ~n458;
assign n698 = n697 & (n213 | n256 | n336);
assign n699 = n400 | ~i_10_ | n115;
assign n700 = n567 | n199 | n120;
assign n701 = n700 & (n454 | n109);
assign n702 = ~n319 | n196 | n290;
assign n703 = ~n466 & (n157 | (n668 & n669));
assign n704 = (n444 | n53) & (n217 | n565);
assign n705 = ~n467 & ~n468 & (n138 | n441);
assign n706 = (~n348 | n434) & (~n250 | n432);
assign n707 = (n538 | n71) & (n566 | n224);
assign n708 = n445 | i_5_ | n512 | n404;
assign n709 = n708 & ~n745 & (i_5_ | n431);
assign n710 = (n589 | n290) & (n202 | n177);
assign n711 = ~n480 & n710 & (n62 | n354);
assign n712 = (n185 | n335) & (n210 | n354);
assign n713 = ~n220 | ~i_5_ | i_9_;
assign n714 = n713 & n712 & (i_0_ | i_5_);
assign n715 = (n202 | n567) & (n64 | n355);
assign n716 = i_10_ | n332;
assign n717 = (i_2_ | n283) & (i_0_ | n481);
assign n718 = i_6_ | n60;
assign n719 = ~i_12_ & n718 & (i_5_ | n59);
assign n720 = n228 | ~i_3_ | i_7_;
assign n721 = n720 & (i_7_ | n408);
assign n722 = n721 & (n546 | (~i_2_ & i_7_));
assign n723 = (~i_7_ | n587) & (~i_2_ | n547);
assign n724 = ~n497 & (n226 | (n398 & n404));
assign n725 = ~i_0_ | n511;
assign n726 = n495 | n400;
assign n727 = ~n435 | ~i_3_ | n270;
assign n728 = ~n365 | ~i_8_ | ~n348;
assign n729 = ~i_5_ | n59 | ~n512 | n548;
assign n730 = ~n243 | i_7_ | n50;
assign n731 = i_7_ & (n573 | n65);
assign n732 = i_7_ & (~n643 | (~i_12_ & ~n161));
assign n733 = i_12_ | n514;
assign n734 = n560 | i_8_ | ~n167;
assign n735 = n527 | i_6_ | ~i_11_;
assign n736 = ~i_10_ & (~n572 | (n73 & n166));
assign n737 = i_2_ & i_12_ & (~n303 | ~n398);
assign n738 = ~i_1_ & (~n688 | (n166 & ~n537));
assign n739 = ~i_0_ & ~i_4_ & (n447 | n448);
assign n740 = i_0_ & (~n691 | ~n694 | ~n696);
assign n741 = i_2_ | n98 | n120;
assign n742 = i_4_ & (~n678 | (~n70 & ~n71));
assign n743 = ~i_4_ & (~n676 | (~n408 & ~n489));
assign n744 = ~n682 | n403 | n513 | n743 | ~n683 | n742;
assign n745 = i_5_ & n744;
assign n746 = n399 | ~i_4_ | ~i_5_;
assign n747 = (i_6_ & n362) | (~n167 & (~i_6_ | n362));
assign n748 = (~i_6_ & n490) | (n366 & (i_6_ | n490));
assign n749 = i_2_ & i_7_;
assign n750 = n417 & n533 & i_3_;
assign n751 = i_6_ & n574 & n433;
endmodule |
module misex3 (
a, b, c, d, e, f, g, h, i, j, k, l, m, n,
r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2 );
input a, b, c, d, e, f, g, h, i, j, k, l, m, n;
output r2, s2, t2, u2, n2, o2, p2, q2, h2, i2, j2, k2, m2, l2;
wire n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216, n217,
n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289,
n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324, n325,
n326, n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421,
n422, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505,
n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685,
n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762;
assign r2 = ~n293;
assign s2 = ~n74;
assign t2 = ~n217;
assign u2 = ~n148;
assign n2 = ~n68;
assign o2 = ~n62;
assign p2 = ~n388;
assign q2 = ~n349;
assign h2 = ~n56;
assign i2 = ~n569;
assign j2 = ~n55;
assign k2 = ~n50;
assign m2 = ~n456;
assign l2 = ~n757 | ~n759 | n46 | ~n747 | n44 | n45 | n42 | n43;
assign n42 = f & (~n680 | ~n739 | ~n740);
assign n43 = ~f & (n475 | n476 | ~n735);
assign n44 = ~n & (~n722 | ~n724 | ~n728);
assign n45 = n & (~n518 | ~n730 | ~n731);
assign n46 = n548 | ~n744 | n544 | n547 | n542 | ~n543 | ~n540 | n541;
assign n47 = n675 | n676 | n372 | i | l;
assign n48 = n438 | n549 | n189;
assign n49 = n434 & n662 & n661 & n51 & n437 & n439;
assign n50 = n49 & n47 & n48;
assign n51 = n657 & n573 & n656 & n431 & n425 & n428;
assign n52 = n443 & n442 & n440 & n441;
assign n53 = n675 | n189 | n438;
assign n54 = n179 | n480 | n550 | n551;
assign n55 = n54 & n53 & n51 & n52;
assign n56 = n579 & n578 & n577 & n576 & n575 & n574 & n572 & n573;
assign n57 = (n95 | n408) & (n409 | n88);
assign n58 = n96 | n121;
assign n59 = n648 & ~n404 & n361 & n402;
assign n60 = n83 | n317;
assign n61 = (n362 | n300) & (n363 | n426);
assign n62 = ~n416 & ~n415 & ~n414 & n61 & n60 & n59 & n57 & n58;
assign n63 = j | n243 | n119 | n591;
assign n64 = (n177 | n362) & (n684 | n409);
assign n65 = ~n297 & (n95 | n253 | n298);
assign n66 = n620 & n619 & n572 & n618 & n617 & n69 & n574 & n211;
assign n67 = ~n422 & (n591 | (n710 & n711));
assign n68 = ~n420 & ~n419 & n67 & n66 & n65 & n64 & n59 & n63;
assign n69 = n92 | n407 | n91;
assign n70 = n595 | n92;
assign n71 = n264 | ~d | n248;
assign n72 = n701 & (n236 | n79);
assign n73 = n232 & (n152 | n632);
assign n74 = ~n267 & ~n266 & ~n265 & n73 & n72 & n71 & n69 & n70;
assign n75 = ~h | ~k;
assign n76 = n75 | l;
assign n77 = n623 | ~n658;
assign n78 = ~n167 & (n77 | ~n586);
assign n79 = ~c | n459;
assign n80 = e | n521;
assign n81 = n612 & n302;
assign n82 = n81 & n79 & n80;
assign n83 = ~k | n199;
assign n84 = m | j | ~l;
assign n85 = n83 & (~n | n84);
assign n86 = n684 | n83;
assign n87 = (n192 | n605) & (n206 | n604);
assign n88 = ~g | n603;
assign n89 = n86 & n87 & (n85 | n88);
assign n90 = (n110 | n156) & (n113 | n275);
assign n91 = ~i | n538;
assign n92 = ~a | n521;
assign n93 = n90 & (n91 | n92);
assign n94 = ~g | n600;
assign n95 = n285 & n397;
assign n96 = ~k | n167;
assign n97 = n96 | n94 | n95;
assign n98 = n601 | n199;
assign n99 = ~i | n368;
assign n100 = n98 & (~n | n99);
assign n101 = ~h | n538;
assign n102 = ~n | n129;
assign n103 = h | n538;
assign n104 = (n100 | n103) & (n101 | n102);
assign n105 = ~g | n249;
assign n106 = h | n197;
assign n107 = (n100 | n106) & (n102 | n105);
assign n108 = ~k | n179;
assign n109 = n108 & (n | n84);
assign n110 = n608 & n287 & n607;
assign n111 = (n101 | n92) & (n110 | n105);
assign n112 = n135 | n119;
assign n113 = n218 & n295;
assign n114 = ~g | n393;
assign n115 = n112 & n111 & (n113 | n114);
assign n116 = (n110 | n164) & (n113 | n189);
assign n117 = e | n609;
assign n118 = n116 & (n92 | n117);
assign n119 = ~a | n271;
assign n120 = ~e | n609;
assign n121 = n118 & (n119 | n120);
assign n122 = (n110 | n106) & (n113 | n202);
assign n123 = n122 & (n92 | n103);
assign n124 = n153 | n399;
assign n125 = ~n610 | ~g | n237;
assign n126 = j | n154;
assign n127 = ~i | n609;
assign n128 = n124 & n125 & (n126 | n127);
assign n129 = n401 & n512 & n527 & n760;
assign n130 = (n106 | n99) & (n129 | n105);
assign n131 = n519 | ~i | n121;
assign n132 = (n123 | n588) & (n95 | n128);
assign n133 = ~e | n271;
assign n134 = n131 & n132 & (n130 | n133);
assign n135 = ~h | n243;
assign n136 = h | n243;
assign n137 = (n100 | n136) & (n135 | n102);
assign n138 = ~n137 & (~n625 | (b & ~n479));
assign n139 = ~n89 & (~n325 | ~n606);
assign n140 = ~n167 & (~n683 | (~n121 & ~n601));
assign n141 = ~n95 & (~n687 | (~n96 & ~n127));
assign n142 = n133 | n601 | n179 | n106;
assign n143 = n590 | n591;
assign n144 = n136 | n587 | n588;
assign n145 = ~n139 & ~n140 & (n | n134);
assign n146 = (n93 | n591) & (n104 | n616);
assign n147 = n688 & (n107 | n269);
assign n148 = n147 & n146 & n145 & n144 & n143 & n142 & n66 & ~n138;
assign n149 = n689 | n108;
assign n150 = (n372 | n193) & (n613 | n624);
assign n151 = ~f | n603;
assign n152 = n149 & n150 & (n109 | n151);
assign n153 = ~m | n611;
assign n154 = ~l | ~m;
assign n155 = n153 & (i | n154);
assign n156 = ~i | n197;
assign n157 = j | n197;
assign n158 = n156 & n157;
assign n159 = (n155 | n105) & (n158 | n589);
assign n160 = n690 & (n164 | n126);
assign n161 = n644 & n647;
assign n162 = i | n197;
assign n163 = n159 & n160 & (n161 | n162);
assign n164 = g | n249;
assign n165 = (n164 | n96) & (n | n163);
assign n166 = n75 | ~m | n;
assign n167 = ~m | n;
assign n168 = ~l | ~h | j;
assign n169 = n166 & (n167 | n168);
assign n170 = ~f | n243;
assign n171 = ~e | n196;
assign n172 = (n169 | n171) & (~n78 | n170);
assign n173 = n196 | d | n169;
assign n174 = d | n197;
assign n175 = n173 & (~n78 | n174);
assign n176 = j | n75;
assign n177 = n176 & (i | n75);
assign n178 = n299 & n300 & n76 & n177;
assign n179 = m | n;
assign n180 = j | n603;
assign n181 = ~l | n179;
assign n182 = (n180 | n181) & (n178 | n179);
assign n183 = ~e | n615;
assign n184 = ~n | n183;
assign n185 = (n99 | n184) & (n98 | n183);
assign n186 = ~n184 & ~n761 & (~n114 | ~n189);
assign n187 = ~n186 & (n185 | (n202 & n676));
assign n188 = n183 | n391;
assign n189 = g | n393;
assign n190 = n187 & (n188 | (n114 & n189));
assign n191 = (n206 | n624) & (n689 | n83);
assign n192 = k | n199;
assign n193 = ~j | n249;
assign n194 = n191 & (n192 | n193);
assign n195 = n194 & (n85 | n151);
assign n196 = ~f | g;
assign n197 = ~f | ~g;
assign n198 = (n169 | n196) & (~n78 | n197);
assign n199 = m | ~n;
assign n200 = ~l | n199;
assign n201 = (n180 | n200) & (n178 | n199);
assign n202 = h | n570;
assign n203 = (n100 | n202) & (n102 | n114);
assign n204 = n203 & (n201 | (n170 & n171));
assign n205 = n691 & n692 & (n85 | n314);
assign n206 = l | n199;
assign n207 = ~k | n393;
assign n208 = n89 & n205 & (n206 | n207);
assign n209 = ~n152 & (~n133 | ~n430);
assign n210 = n595 | n599;
assign n211 = n595 | n353;
assign n212 = n693 & (~e | n195 | n324);
assign n213 = ~n209 & (n285 | (n165 & n595));
assign n214 = n208 | n315;
assign n215 = (n172 | n119) & (n175 | n287);
assign n216 = n694 & (n182 | n302);
assign n217 = n216 & n190 & n215 & n214 & n213 & n212 & n210 & n211;
assign n218 = ~a | n560;
assign n219 = n167 | n218;
assign n220 = (n168 | n219) & (n218 | n166);
assign n221 = ~n658 | ~n586 | n623;
assign n222 = ~f & ~n538;
assign n223 = ~n219 & n221 & (n222 | ~n261);
assign n224 = e | n488;
assign n225 = e | n196;
assign n226 = ~n223 & (n220 | (n224 & n225));
assign n227 = n393 | ~j | n372;
assign n228 = (n613 | n207) & (n109 | n314);
assign n229 = n640 & n643;
assign n230 = n227 & n228 & (n229 | n108);
assign n231 = ~e | n626;
assign n232 = n190 & n226 & (n230 | n231);
assign n233 = ~n83 & (~n252 | ~n639);
assign n234 = (n192 | n322) & (n256 | n206);
assign n235 = g | n603;
assign n236 = ~n233 & n234 & (n85 | n235);
assign n237 = k | n154;
assign n238 = (i | n161) & (~j | n237);
assign n239 = ~n591 & (~n91 | (~j & ~n538));
assign n240 = ~n239 & (n | (n699 & n700));
assign n241 = n165 & n240 & (n96 | n117);
assign n242 = ~i | n243;
assign n243 = ~e | ~g;
assign n244 = n242 & (j | n243);
assign n245 = n96 | n120;
assign n246 = n697 & (n120 | n126);
assign n247 = n696 & n695 & (n244 | n589);
assign n248 = n245 & (n | (n246 & n247));
assign n249 = ~f | ~h;
assign n250 = n249 | n102 | e;
assign n251 = n629 & n88;
assign n252 = j | n609;
assign n253 = i | n602;
assign n254 = ~g | n360;
assign n255 = n254 & n253 & n251 & n252;
assign n256 = g | n75;
assign n257 = n698 & (n376 | (n628 & n649));
assign n258 = (n94 | n96) & (n629 | n630);
assign n259 = ~l | n167;
assign n260 = n257 & n258 & (n255 | n259);
assign n261 = ~f | n538;
assign n262 = (n169 | n225) & (~n78 | n261);
assign n263 = ~n260 & (~n655 | (d & ~n524));
assign n264 = a | ~b;
assign n265 = ~n201 & (~n325 | (~n261 & ~n616));
assign n266 = ~n352 & (~n262 | n263);
assign n267 = ~n526 & (~n250 | (~n100 & ~n631));
assign n268 = n344 & (n83 | n633);
assign n269 = ~b | n598;
assign n270 = n268 & (n194 | n269);
assign n271 = ~c | d;
assign n272 = n79 & (~f | n271);
assign n273 = (n100 | n634) & (n164 | n102);
assign n274 = n273 & n107;
assign n275 = ~i | n570;
assign n276 = j | n570;
assign n277 = n275 & n276;
assign n278 = (n155 | n114) & (n277 | n589);
assign n279 = n749 & (n189 | n126);
assign n280 = i | n570;
assign n281 = n278 & n279 & (n161 | n280);
assign n282 = (n96 | n189) & (n | n281);
assign n283 = n286 | g | n169;
assign n284 = n283 & (d | ~n78 | n243);
assign n285 = ~e | n264;
assign n286 = d | ~e;
assign n287 = c | ~a | ~b;
assign n288 = n285 & (n286 | n287);
assign n289 = (n236 | n635) & (n104 | n616);
assign n290 = (n260 | n288) & (n284 | ~n545);
assign n291 = n107 | n315;
assign n292 = (n182 | n272) & (n274 | n625);
assign n293 = n292 & n291 & n290 & n289 & n270 & n232;
assign n294 = n123 & (n119 | n136);
assign n295 = n596 & n594;
assign n296 = n112 & n111 & (n295 | n114);
assign n297 = ~n636 & (~n355 | (~n167 & ~n296));
assign n298 = n | n126;
assign n299 = ~h | n360;
assign n300 = ~k | n603;
assign n301 = n180 & n300 & n299 & n176;
assign n302 = ~c | n524;
assign n303 = n302 & (~c | n196);
assign n304 = (n113 | n646) & (~j | n645);
assign n305 = ~j | n197;
assign n306 = n304 & (n110 | n305);
assign n307 = n121 & (n95 | n94);
assign n308 = ~n95 & ~n644 & (~n88 | ~n660);
assign n309 = ~n308 & (n329 | n339 | n435);
assign n310 = (n118 | n126) & (n306 | n237);
assign n311 = ~l | n519;
assign n312 = n309 & n310 & (n307 | n311);
assign n313 = n183 & n390;
assign n314 = f | n603;
assign n315 = ~b | n286;
assign n316 = (n314 | n315) & (n313 | n235);
assign n317 = n633 & n316;
assign n318 = (n80 & (~n | n371)) | (n & n371);
assign n319 = (n88 | n318) & (~n | n317);
assign n320 = n393 | ~j | n315;
assign n321 = n269 | n193;
assign n322 = ~j | n609;
assign n323 = n320 & n321 & (n313 | n322);
assign n324 = b | ~c;
assign n325 = ~f | n324;
assign n326 = (n315 | n643) & (n313 | n252);
assign n327 = j | n249;
assign n328 = n326 & (n269 | n327);
assign n329 = ~h | n621;
assign n330 = n328 & (n325 | n329);
assign n331 = (n316 | n84) & (n330 | n435);
assign n332 = m | k | ~l;
assign n333 = n331 & (n323 | n332);
assign n334 = (n315 | n640) & (n313 | n639);
assign n335 = i | n249;
assign n336 = n334 & (n269 | n335);
assign n337 = ~n199 & (~n336 | (~n253 & ~n371));
assign n338 = ~n337 & (n80 | n179 | n253);
assign n339 = n303 & n637;
assign n340 = (n339 | n181) & (n325 | n200);
assign n341 = ~n318 & (~n704 | (~n332 & ~n605));
assign n342 = n243 | n490 | ~j | n119;
assign n343 = n298 | n119 | n120;
assign n344 = n633 | ~n | n84;
assign n345 = n705 & (n301 | n340);
assign n346 = n65 & (n319 | n435);
assign n347 = (n312 & (~n | n333)) | (n & n333);
assign n348 = (n682 | n641) & (n338 | n433);
assign n349 = n348 & n347 & n346 & n345 & n344 & n343 & ~n341 & n342;
assign n350 = (n113 | n280) & (i | n645);
assign n351 = n350 & (n110 | n162);
assign n352 = ~a | n324;
assign n353 = ~b | n597;
assign n354 = n353 & n287 & n352;
assign n355 = n114 | n219;
assign n356 = (n599 | n105) & (n295 | n114);
assign n357 = n112 & (n92 | (n105 & n101));
assign n358 = n355 & (n167 | (n356 & n357));
assign n359 = n707 & (n285 | n630 | n605);
assign n360 = ~j | k;
assign n361 = n359 & (n358 | n360);
assign n362 = (n339 | n179) & (n325 | n199);
assign n363 = (n339 | n108) & (n325 | n83);
assign n364 = ~n88 & (~n706 | (~n167 & ~n433));
assign n365 = ~n364 & (n629 | (n259 & n630));
assign n366 = n365 & (n96 | n322);
assign n367 = n519 | n | n121;
assign n368 = ~k | m;
assign n369 = (n253 | n318) & (~n | n336);
assign n370 = n367 & (n368 | (n369 & n319));
assign n371 = n395 & n315 & n606;
assign n372 = k | n179;
assign n373 = (n372 | n80) & (n371 | n192);
assign n374 = ~i | k | ~l | n167;
assign n375 = ~k | ~n610;
assign n376 = l | n167;
assign n377 = n374 & (n375 | (n376 & n259));
assign n378 = ~j | n603;
assign n379 = n378 & n329;
assign n380 = n644 | n587 | n627;
assign n381 = n647 | n587 | n627;
assign n382 = n351 | n | n161;
assign n383 = (n294 | n377) & (n363 | n379);
assign n384 = n373 | n605;
assign n385 = (n95 | n366) & (~j | n370);
assign n386 = n362 | n299;
assign n387 = n361 & (n323 | n192);
assign n388 = n387 & n386 & n385 & n384 & n383 & n382 & n380 & n381;
assign n389 = ~n372 & (~n303 | ~n637);
assign n390 = n635 & n638;
assign n391 = ~n | n401;
assign n392 = n188 & (n390 | n391);
assign n393 = f | ~h;
assign n394 = (n393 | n315) & (n249 | n269);
assign n395 = n616 & n625;
assign n396 = e | n324;
assign n397 = ~b | n524;
assign n398 = n397 & n396 & n395 & n315;
assign n399 = ~i | n602;
assign n400 = (n398 | n399) & (~i | n394);
assign n401 = m | n360;
assign n402 = n399 | n | n80 | n401;
assign n403 = h & n610;
assign n404 = n403 & (n389 | (~n192 & ~n325));
assign n405 = n253 | n641;
assign n406 = (n256 | n167) & (n376 | n176);
assign n407 = n | n592;
assign n408 = n405 & n406 & (n407 | n399);
assign n409 = (n108 | n80) & (n371 | n83);
assign n410 = i & ~n394;
assign n411 = n & (n410 | (~n127 & ~n313));
assign n412 = j | i;
assign n413 = n412 | ~k | n259;
assign n414 = ~n115 & (~n413 | (n77 & ~n167));
assign n415 = ~n527 & (n411 | (~n318 & ~n399));
assign n416 = ~n591 & (~n709 | (~n110 & ~n327));
assign n417 = ~n433 & (~n351 | (~n119 & ~n627));
assign n418 = ~n311 & ~n & ~n251;
assign n419 = ~n95 & (n418 | (~n376 & ~n649));
assign n420 = ~n83 & (~n328 | ~n336);
assign n421 = i & k;
assign n422 = ~n167 & (n417 | (~n294 & n421));
assign n423 = n654 | ~f | n598;
assign n424 = j | k;
assign n425 = n259 | n399 | n423 | n424;
assign n426 = ~h | n600;
assign n427 = n651 | ~n | n557;
assign n428 = n427 | n426 | n332;
assign n429 = n650 | n114 | n181;
assign n430 = ~e | n521;
assign n431 = n429 | n430;
assign n432 = ~n545 | n655;
assign n433 = ~l | ~j | ~k;
assign n434 = n399 | n167 | n432 | n433;
assign n435 = ~l | n368;
assign n436 = n170 | n526;
assign n437 = n436 | ~n403 | n435;
assign n438 = n181 | n375;
assign n439 = n438 | n231 | n105;
assign n440 = n652 | n202 | n632;
assign n441 = ~n653 | n435 | n445;
assign n442 = n181 | n202 | n430 | ~n473;
assign n443 = n712 & (n332 | n427 | n378);
assign n444 = n106 | n613 | n231 | n658;
assign n445 = h | n621;
assign n446 = m | k | l;
assign n447 = n444 & (n436 | n445 | n446);
assign n448 = n551 | n | n446;
assign n449 = n448 & (n179 | n127 | n433);
assign n450 = k | n189 | n181 | n632;
assign n451 = n332 | n651 | ~h | n224;
assign n452 = n450 & n451;
assign n453 = n641 | n654 | n660 | n477;
assign n454 = n105 | n181 | n549 | n650;
assign n455 = (n449 | n480) & (n452 | n412);
assign n456 = n455 & n454 & n453 & n49 & n52 & n447;
assign n457 = i | n179;
assign n458 = (~k | n457) & (n179 | ~n412);
assign n459 = e | ~f;
assign n460 = a | n526;
assign n461 = j & ~n630 & (n459 | n460);
assign n462 = ~n758 & (~h | n438 | ~n479);
assign n463 = f | ~c | e;
assign n464 = ~n461 & n462 & (n458 | n463);
assign n465 = b | n199;
assign n466 = n200 & n83 & n465 & n298;
assign n467 = (b | n200) & (c | n181);
assign n468 = ~n167 & (~n737 | (~b & ~n479));
assign n469 = h | j | n199;
assign n470 = (j | n83) & (~i | n663);
assign n471 = ~j | n199;
assign n472 = n469 & n470 & (~h | n471);
assign n473 = ~k & n610;
assign n474 = n473 & b & ~n199;
assign n475 = ~h & (n474 | (~i & ~n206));
assign n476 = ~n673 & (~n521 | (~e & n324));
assign n477 = f | n659;
assign n478 = n477 & (f | a | e);
assign n479 = c | d;
assign n480 = f | n479;
assign n481 = n669 | c | e;
assign n482 = b | e | ~n | n669;
assign n483 = n375 | ~n615 | ~h | n259;
assign n484 = (d | n734) & (n457 | n480);
assign n485 = n199 | n675;
assign n486 = ~n762 & n485 & n484 & n483 & n481 & n482;
assign n487 = c & ~n655;
assign n488 = f | g;
assign n489 = b | n488;
assign n490 = n | n237;
assign n491 = (j | n490) & (n199 | ~n626);
assign n492 = ~n199 & (~n741 | (~j & ~n525));
assign n493 = n742 & (n670 | n671);
assign n494 = ~n492 & ~n756 & (i | n491);
assign n495 = n493 & n494 & (n457 | n271);
assign n496 = c | n488;
assign n497 = n664 & n463;
assign n498 = (n106 | n231) & (~j | n497);
assign n499 = (n716 | n167) & (n498 | n179);
assign n500 = n496 | n372;
assign n501 = (n527 | n671) & (n719 | n613);
assign n502 = n718 & (n436 | (n206 & n192));
assign n503 = n502 & n501 & n499 & n500;
assign n504 = ~j & ~n372 & (~n271 | ~n302);
assign n505 = (b | n199) & (c | n179);
assign n506 = ~b | ~e | ~n | n666;
assign n507 = e | n505 | n650;
assign n508 = (n525 | n471) & (n457 | n479);
assign n509 = n478 | n167;
assign n510 = ~n626 | j | n192;
assign n511 = n510 & n509 & n508 & n507 & ~n504 & n506;
assign n512 = i | n368;
assign n513 = m | n603;
assign n514 = i | m;
assign n515 = n512 & n513 & (~l | n514);
assign n516 = n253 & n127;
assign n517 = (n426 | n446) & (n516 | n666);
assign n518 = n517 & (n401 | n151);
assign n519 = ~k | ~m;
assign n520 = n519 & (j | ~m);
assign n521 = c | ~d;
assign n522 = n81 & (g | n521);
assign n523 = ~n311 & n403 & (~n174 | ~n261);
assign n524 = ~e | f;
assign n525 = b | n524;
assign n526 = ~d | n615;
assign n527 = j | n368;
assign n528 = n99 & n527;
assign n529 = n717 & (h | n524 | n636);
assign n530 = (n521 | n525) & (~j | n716);
assign n531 = (i | n432) & (n254 | n665);
assign n532 = n634 & n550 & (n135 | n650);
assign n533 = n532 & n531 & n529 & n530;
assign n534 = ~c & ~n524;
assign n535 = (~n180 | ~n628) & (~n463 | n534);
assign n536 = ~j & (~n660 | (~n156 & ~n231));
assign n537 = n396 & (a | c | e);
assign n538 = e | ~g;
assign n539 = ~n162 & (~n108 | ~n181);
assign n540 = n375 | n259 | n114;
assign n541 = ~n489 & (~n206 | ~n663);
assign n542 = ~n613 & (~n497 | (~c & ~n660));
assign n543 = n438 | n101;
assign n544 = ~n231 & (n539 | (~n156 & ~n613));
assign n545 = a & ~n615;
assign n546 = n545 & ~n655 & (~n630 | ~n672);
assign n547 = ~n457 & (~n631 | (~n105 & ~n231));
assign n548 = ~n179 & (n535 | n536 | ~n715);
assign n549 = ~e | n479;
assign n550 = l | n424;
assign n551 = i | g | h;
assign n552 = n112 | n155 | n;
assign n553 = n119 | n245;
assign n554 = f | n167;
assign n555 = (n168 | n554) & (f | n166);
assign n556 = n555 | ~e | g;
assign n557 = f | n243;
assign n558 = n556 & (~n78 | n557);
assign n559 = ~n99 & ~g & n;
assign n560 = ~b | ~d;
assign n561 = (n203 | n560) & (n526 | ~n748);
assign n562 = (n175 | n287) & (n282 | n594);
assign n563 = n236 | n638;
assign n564 = (n352 | n558) & (~e | n561);
assign n565 = n608 | n172;
assign n566 = n677 & n553 & n552 & n342 & n143 & n63;
assign n567 = n226 & n270 & (n89 | n625);
assign n568 = n750 & n752 & n656 & n661 & n441 & n657 & n440 & n662;
assign n569 = n568 & n567 & n447 & n566 & n565 & n564 & n562 & n563;
assign n570 = f | ~g;
assign n571 = (g | n555) & (~n78 | n570);
assign n572 = n595 | n352;
assign n573 = n652 | n106 | n549;
assign n574 = n593 | n596;
assign n575 = n626 | ~a | n262;
assign n576 = n571 | ~d | ~n545;
assign n577 = n753 & (n654 | (n175 & n248));
assign n578 = n282 | n596;
assign n579 = n566 & (n165 | n352);
assign n580 = l | ~n421;
assign n581 = ~l | ~h | i;
assign n582 = (~l & n622) | (n603 & (l | n622));
assign n583 = ~h | n611;
assign n584 = ~l | n360;
assign n585 = ~l | n621;
assign n586 = n585 & n584 & n583 & n582 & n580 & n581;
assign n587 = n | n119;
assign n588 = ~i | n154;
assign n589 = l | n519;
assign n590 = n119 | n242;
assign n591 = n | n589;
assign n592 = j | n519;
assign n593 = n407 | n275;
assign n594 = ~a | n286;
assign n595 = n156 | n407;
assign n596 = ~e | ~a | ~c;
assign n597 = d | a;
assign n598 = ~d | e;
assign n599 = ~a | n598;
assign n600 = ~i | j;
assign n601 = ~l | n600;
assign n602 = ~g | ~h;
assign n603 = h | ~i;
assign n604 = ~g | n75;
assign n605 = ~j | n602;
assign n606 = n396 & n397;
assign n607 = n599 & n353;
assign n608 = n92 & n352;
assign n609 = g | ~h;
assign n610 = i & j;
assign n611 = ~j | l;
assign n612 = ~f | n521;
assign n613 = l | n179;
assign n614 = ~g | ~n421;
assign n615 = ~b | ~c;
assign n616 = d | n615;
assign n617 = n590 | n407;
assign n618 = n593 | n594;
assign n619 = n97 & n70 & n210;
assign n620 = (n595 | n287) & (n593 | n218);
assign n621 = i | ~j;
assign n622 = j | ~k;
assign n623 = k & ~n600;
assign n624 = ~k | n249;
assign n625 = ~b | n521;
assign n626 = ~c | ~d;
assign n627 = i | n243;
assign n628 = n614 & n605;
assign n629 = ~g | n621;
assign n630 = k | n167;
assign n631 = h | n459;
assign n632 = e | n626;
assign n633 = n269 | n151;
assign n634 = h | n196;
assign n635 = ~b | n459;
assign n636 = ~l | n412;
assign n637 = n612 & n272;
assign n638 = ~f | n560;
assign n639 = i | n609;
assign n640 = i | n393;
assign n641 = n622 | ~l | n167;
assign n642 = j | n602;
assign n643 = j | n393;
assign n644 = ~j | n154;
assign n645 = n538 | n92;
assign n646 = ~j | n570;
assign n647 = ~m | n360;
assign n648 = (n392 | n127) & (n400 | n391);
assign n649 = ~g | n622;
assign n650 = k | n600;
assign n651 = b | n626;
assign n652 = n621 | ~k | n181;
assign n653 = n222 & ~n526;
assign n654 = a | n615;
assign n655 = ~f | ~d | ~e;
assign n656 = ~n653 | n332 | n426;
assign n657 = n632 | n429;
assign n658 = k | n621;
assign n659 = d | e;
assign n660 = i | ~g | h;
assign n661 = n445 | n435 | n427;
assign n662 = n430 | n202 | n652;
assign n663 = n83 & n471;
assign n664 = ~g | n479;
assign n665 = a | n598;
assign n666 = m | n424;
assign n667 = ~h | n514;
assign n668 = k | n514;
assign n669 = h | n514;
assign n670 = m | n600;
assign n671 = n | n479;
assign n672 = h | n167;
assign n673 = g | n199;
assign n674 = h & ~n650;
assign n675 = e | n479;
assign n676 = h | n488;
assign n677 = n343 & n144 & n454 & n617 & n381 & n380;
assign n678 = (e & ~n119) | (~n92 & (~e | ~n119));
assign n679 = (n479 & n674) | (~g & (~n479 | n674));
assign n680 = n755 & (i | n466 | h);
assign n681 = ~n610 | l | n115;
assign n682 = n590 & n93;
assign n683 = n681 & (n682 | n584);
assign n684 = n642 & n253;
assign n685 = (n684 | n108) & (n109 | n88);
assign n686 = (n605 | n372) & (n604 | n613);
assign n687 = (n614 | n376) & (n88 | n259);
assign n688 = ~n141 & (n82 | (n685 & n686));
assign n689 = n335 & n327;
assign n690 = (n588 | n106) & (n237 | n305);
assign n691 = n229 | n83;
assign n692 = n393 | ~j | n192;
assign n693 = ~a | b | ~d | n198;
assign n694 = (n607 | n165) & (n204 | n625);
assign n695 = (n161 | n627) & (n155 | n135);
assign n696 = n243 | ~j | n237;
assign n697 = (n588 | n136) & (n242 | n592);
assign n698 = n256 | n167;
assign n699 = (n155 | n101) & (n238 | n538);
assign n700 = (n588 | n103) & (n117 | n126);
assign n701 = (n182 | n612) & (n241 | n92);
assign n702 = ~n294 & (~n585 | (l & n610));
assign n703 = ~n95 & (~n252 | ~n254 | ~n256);
assign n704 = (n84 | n88) & (n642 | n435);
assign n705 = (n167 | ~n702) & (n259 | ~n703);
assign n706 = n490 & (n96 | n611);
assign n707 = n354 | n360 | n167 | n105;
assign n708 = ~h | j;
assign n709 = (n113 | n643) & (~n678 | n708);
assign n710 = (n95 | n88) & (j | n645);
assign n711 = (n110 | n157) & (n113 | n276);
assign n712 = n167 | n127 | n584 | n423;
assign n713 = (d | n525) & (j | n436);
assign n714 = (b | c) & (n127 | n433);
assign n715 = (n253 | n463) & (n103 | ~n473);
assign n716 = n676 & n478;
assign n717 = a | b;
assign n718 = n433 | n487 | ~h | n199;
assign n719 = n496 & ~n534;
assign n720 = n478 & n665 & n432;
assign n721 = ~n523 & (g | n520 | n720);
assign n722 = n721 & (n670 | (n496 & n480));
assign n723 = (n522 | n669) & (n164 | n666);
assign n724 = n723 & (n668 | (n202 & n664));
assign n725 = n231 | n156 | n401;
assign n726 = n592 | n432;
assign n727 = n725 & n726 & (n719 | n667);
assign n728 = n518 & n727 & (n496 | n515);
assign n729 = (n436 | n667) & (n525 | n528);
assign n730 = n729 & (n515 | n436);
assign n731 = (n669 | n397) & (n525 | n668);
assign n732 = n526 | e | n472;
assign n733 = n672 | ~n597 | n636;
assign n734 = n754 & (~h | n438);
assign n735 = n732 & n733 & (~c | n734);
assign n736 = n | a | ~g;
assign n737 = (i | n665) & (~n545 | n659);
assign n738 = ~n468 & (n311 | ~n403 | n736);
assign n739 = n738 & (n665 | (n672 & n96));
assign n740 = (n549 | n673) & (n179 | ~n679);
assign n741 = n489 & (e | n254);
assign n742 = ~n629 | k | n206;
assign n743 = ~n546 & (n537 | n554);
assign n744 = n743 & (n199 | (n714 & n713));
assign n745 = (n720 | n376) & (n533 | n167);
assign n746 = (n192 | n327) & (~i | n503);
assign n747 = n745 & n746 & (n591 | n445);
assign n748 = ~h & (n559 | (~n601 & ~n673));
assign n749 = (n588 | n202) & (n237 | n646);
assign n750 = n53 & n47 & n618;
assign n751 = n526 | n102 | n120;
assign n752 = n751 & (n651 | (n104 & n195));
assign n753 = n449 | n480;
assign n754 = ~n473 | h | n179;
assign n755 = n467 | ~h | n375;
assign n756 = i & ~k & (~n376 | ~n613);
assign n757 = (n495 & (~h | n511)) | (h & n511);
assign n758 = ~h & (~n96 | (c & ~n457));
assign n759 = (n464 & (~g | n486)) | (g & n486);
assign n760 = l | n368;
assign n761 = n760 & n512 & n527;
assign n762 = n674 & ~n167 & n460;
endmodule |
module s298 ( clock,
G0, G1, G2,
G117, G132, G66, G118, G133, G67 );
input G0, G1, G2, clock;
output G117, G132, G66, G118, G133, G67;
reg G10, G11, G12, G13, G14, G15, G16, G17, G18, G19, G20, G21, G22, G23;
wire n57, n59, n64, n66, n21_1, n26_1, n31_1, n36_1, n41_1, n46_1, n51_1,
n56_1, n61_1, n66_2, n71_1, n76_1, n81_1, n86_1;
assign n21_1 = ~G0 & ~G10;
assign n26_1 = ~G0 & (G10 ? (~G11 & (G12 | ~G13)) : G11);
assign n31_1 = ~G0 & ((G12 & (~G10 | ~G11)) | (G10 & G11 & ~G12));
assign n36_1 = ~G0 & ((G11 & ((~G12 & G13) | (G10 & G12 & ~G13))) | (G13 & (~G10 | (~G11 & G12))));
assign n41_1 = ~G0 & (G14 ^ (G23 | (G10 & G13 & n57)));
assign n57 = ~G11 & ~G12;
assign n46_1 = ~G0 & ~n59;
assign n59 = (G11 & (~G15 | (~G12 & G13 & ~G14 & ~G22))) | (~G15 & (G12 | ~G13 | G14 | ~G22));
assign n51_1 = n59 & ((G13 & (~G14 | G16)) | (G12 & G14 & G16));
assign n56_1 = n59 & ((~G13 & (G11 ? ~G12 : ~G14)) | (G14 & G17 & (G12 | G13)));
assign n61_1 = n59 & ((G14 & G18 & (G12 | G13)) | (~G13 & (~G14 | (G11 & ~G12))));
assign n66_2 = n59 ? n64 : ~G10;
assign n64 = (G13 & (~G14 | G19)) | (G14 & ((~G11 & ~G12 & ~G13) | (G12 & G19)));
assign n71_1 = n59 ? (n66 & (G20 | (~G12 & ~G13))) : ~G10;
assign n66 = G14 & (~G11 | G12 | G13);
assign n76_1 = n59 & ((G12 & ((G11 & ~G13 & ~G14) | (G14 & G21))) | (G13 & G14 & G21));
assign n81_1 = ~G0 & (G2 ^ G22);
assign n86_1 = ~G0 & (G1 ^ G23);
assign G117 = G18;
assign G132 = G20;
assign G66 = G16;
assign G118 = G19;
assign G133 = G21;
assign G67 = G17;
always @ (posedge clock) begin
G10 <= n21_1;
G11 <= n26_1;
G12 <= n31_1;
G13 <= n36_1;
G14 <= n41_1;
G15 <= n46_1;
G16 <= n51_1;
G17 <= n56_1;
G18 <= n61_1;
G19 <= n66_2;
G20 <= n71_1;
G21 <= n76_1;
G22 <= n81_1;
G23 <= n86_1;
end
initial begin
G10 <= 1'b0;
G11 <= 1'b0;
G12 <= 1'b0;
G13 <= 1'b0;
G14 <= 1'b0;
G15 <= 1'b0;
G16 <= 1'b0;
G17 <= 1'b0;
G18 <= 1'b0;
G19 <= 1'b0;
G20 <= 1'b0;
G21 <= 1'b0;
G22 <= 1'b0;
G23 <= 1'b0;
end
endmodule |
module frac_mem_32k (
input [0:14] addr_a,
input [0:14] addr_b,
input [0:31] data_a,
input [0:31] data_b,
input we_a,
input we_b,
output reg [0:31] q_a,
output reg [0:31] q_b,
input clk,
input [0:3] mode);
reg [0:31] ram_a [0:9];
reg [0:31] ram_b [0:9];
always @(posedge clk) begin
// Operating mode: single port RAM 512 x 64
if (4'b0000 == mode) begin
if (we_a) begin
ram_a[addr_a[0:8]] <= data_a;
ram_b[addr_a[0:8]] <= data_b;
q_a <= data_a;
q_b <= data_b;
end else begin
q_a <= ram_a[addr_a[0:8]];
q_b <= ram_b[addr_a[0:8]];
end
// Operating mode: single port RAM 1024 x 32
end else if (4'b0001 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]] <= data_a;
end else begin
q_a <= ram_a[addr_a[0:9]];
end
// Operating mode: single port RAM 2048 x 16
end else if (4'b0010 == mode) begin
if (we_a) begin
case (addr_a[10:10])
1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];
1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];
endcase
end else begin
case (addr_a[10:10])
1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
endcase
end
// Operating mode: single port RAM 4096 x 8
end else if (4'b0011 == mode) begin
if (we_a) begin
case (addr_a[10:11])
2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
endcase
end else begin
case (addr_a[10:11])
2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
endcase
end
// Operating mode: single port RAM 8192 x 4
end else if (4'b0100 == mode) begin
if (we_a) begin
case (addr_a[10:12])
3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
endcase
end else begin
case (addr_a[10:12])
3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
endcase
end
// Operating mode: single port RAM 16384 x 2
end else if (4'b0101 == mode) begin
if (we_a) begin
case (addr_a[10:13])
4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
endcase
end else begin
case (addr_a[10:13])
4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
endcase
end
// Operating mode: single port RAM 32768 x 1
end else if (4'b0110 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]][addr_a[10:14]] <= data_a[0:0];
end else begin
q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
end
// Operating mode: dual port RAM 1024 x 32
end else if (4'b0111 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram_a[addr_a[0:9]];
end
if (we_b) begin
ram_b[addr_b[0:9]] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram_b[addr_b[0:9]];
end
// Operating mode: dual port RAM 2048 x 16
end else if (4'b1000 == mode) begin
if (we_a) begin
case (addr_a[10:10])
1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;
1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;
endcase
end else begin
case (addr_a[10:10])
1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
endcase
end
if (we_b) begin
case (addr_b[10:10])
1'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;
1'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;
endcase
end else begin
case (addr_b[10:10])
1'b0 : q_b <= ram_b[addr_b[0:9]][0:15];
1'b1 : q_b <= ram_b[addr_b[0:9]][16:31];
endcase
end
// Operating mode: dual port RAM 4096 x 8
end else if (4'b1001 == mode) begin
if (we_a) begin
case (addr_a[10:11])
2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
endcase
end else begin
case (addr_a[10:11])
2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
endcase
end
if (we_b) begin
case (addr_b[10:11])
2'b00 : ram_b[addr_b[0:9]][0:7] <= data_b[0:7];
2'b01 : ram_b[addr_b[0:9]][8:15] <= data_b[0:7];
2'b10 : ram_b[addr_b[0:9]][16:23] <= data_b[0:7];
2'b11 : ram_b[addr_b[0:9]][24:31] <= data_b[0:7];
endcase
end else begin
case (addr_b[10:11])
2'b00 : q_b <= ram_b[addr_b[0:9]][0:7];
2'b01 : q_b <= ram_b[addr_b[0:9]][8:15];
2'b10 : q_b <= ram_b[addr_b[0:9]][16:23];
2'b11 : q_b <= ram_b[addr_b[0:9]][24:31];
endcase
end
// Operating mode: dual port RAM 8192 x 4
end else if (4'b1011 == mode) begin
if (we_a) begin
case (addr_a[10:12])
3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
endcase
end else begin
case (addr_a[10:12])
3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
endcase
end
if (we_b) begin
case (addr_b[10:12])
3'b000 : ram_b[addr_b[0:9]][0:3] <= data_b[0:3];
3'b001 : ram_b[addr_b[0:9]][4:7] <= data_b[0:3];
3'b010 : ram_b[addr_b[0:9]][8:11] <= data_b[0:3];
3'b011 : ram_b[addr_b[0:9]][12:15] <= data_b[0:3];
3'b100 : ram_b[addr_b[0:9]][16:19] <= data_b[0:3];
3'b101 : ram_b[addr_b[0:9]][20:23] <= data_b[0:3];
3'b110 : ram_b[addr_b[0:9]][24:27] <= data_b[0:3];
3'b111 : ram_b[addr_b[0:9]][28:31] <= data_b[0:3];
endcase
end else begin
case (addr_b[10:12])
3'b000 : q_b <= ram_b[addr_b[0:9]][0:3];
3'b001 : q_b <= ram_b[addr_b[0:9]][4:7];
3'b010 : q_b <= ram_b[addr_b[0:9]][8:11];
3'b011 : q_b <= ram_b[addr_b[0:9]][12:15];
3'b100 : q_b <= ram_b[addr_b[0:9]][16:19];
3'b101 : q_b <= ram_b[addr_b[0:9]][20:23];
3'b110 : q_b <= ram_b[addr_b[0:9]][24:27];
3'b111 : q_b <= ram_b[addr_b[0:9]][28:31];
endcase
end
// Operating mode: dual port RAM 16384 x 2
end else if (4'b1100 == mode) begin
if (we_a) begin
case (addr_a[10:13])
4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
endcase
end else begin
case (addr_a[10:13])
4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
endcase
end
if (we_b) begin
case (addr_b[10:13])
4'b0000 : ram_b[addr_b[0:9]][0:1] <= data_b[0:1];
4'b0001 : ram_b[addr_b[0:9]][2:3] <= data_b[0:1];
4'b0010 : ram_b[addr_b[0:9]][4:5] <= data_b[0:1];
4'b0011 : ram_b[addr_b[0:9]][6:7] <= data_b[0:1];
4'b0100 : ram_b[addr_b[0:9]][8:9] <= data_b[0:1];
4'b0101 : ram_b[addr_b[0:9]][10:11] <= data_b[0:1];
4'b0110 : ram_b[addr_b[0:9]][12:13] <= data_b[0:1];
4'b0111 : ram_b[addr_b[0:9]][14:15] <= data_b[0:1];
4'b1000 : ram_b[addr_b[0:9]][16:17] <= data_b[0:1];
4'b1001 : ram_b[addr_b[0:9]][18:19] <= data_b[0:1];
4'b1010 : ram_b[addr_b[0:9]][20:21] <= data_b[0:1];
4'b1011 : ram_b[addr_b[0:9]][22:23] <= data_b[0:1];
4'b1100 : ram_b[addr_b[0:9]][24:25] <= data_b[0:1];
4'b1101 : ram_b[addr_b[0:9]][26:27] <= data_b[0:1];
4'b1110 : ram_b[addr_b[0:9]][28:29] <= data_b[0:1];
4'b1111 : ram_b[addr_b[0:9]][30:31] <= data_b[0:1];
endcase
end else begin
case (addr_b[10:13])
4'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];
4'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];
4'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];
4'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];
4'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];
4'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];
4'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];
4'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];
4'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];
4'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];
4'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];
4'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];
4'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];
4'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];
4'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];
4'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];
endcase
end
// Operating mode: dual port RAM 32768 x 1
end else if (4'b1101 == mode) begin
if (we_a) begin
ram_a[addr_a[0:9]][addr_a[10:14]] <= data_a[0:0];
end else begin
q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
end
if (we_b) begin
ram_b[addr_b[0:9]][addr_b[10:14]] <= data_b[0:0];
end else begin
q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];
end
end
end
endmodule |
module ADDF(
input [0:0] A, // Input a
input [0:0] B, // Input b
input [0:0] CI, // Input cin
output [0:0] CO, // Output carry
output [0:0] SUM // Output sum
);
assign SUM = A ^ B ^ CI;
assign CO = (A & B) | (A & CI) | (B & CI);
endmodule |
module dpram_512x32 (
input clk,
input wen,
input ren,
input[0:8] waddr,
input[0:8] raddr,
input[0:31] d_in,
output[0:31] d_out );
dpram_512x32_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (d_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.d_out (d_out) );
endmodule |
module dpram_512x32_core (
input wclk,
input wen,
input[0:8] waddr,
input[0:31] data_in,
input rclk,
input ren,
input[0:8] raddr,
output[0:31] d_out );
reg[0:31] ram[0:511];
reg[0:31] internal;
assign d_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule |
module MUX2(
// iVerilog is buggy on the 'input A' declaration when deposit initial
// values
input [0:0] A, // Data input 0
input [0:0] B, // Data input 1
input [0:0] S0, // Select port
output [0:0] Y // Data output
);
assign Y = S0 ? B : A;
// Note:
// MUX2 appears will appear in LUTs, routing multiplexers,
// being a component in combinational loops
// To help convergence in simulation
// i.e., to avoid the X (undetermined) signals,
// the following timing constraints and signal initialization
// has to be added!
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(A => Y) = (0.001, 0.001);
(B => Y) = (0.001, 0.001);
(S0 => Y) = (0.001, 0.001);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
`ifdef ENABLE_SIGNAL_INITIALIZATION
// ------ BEGIN driver initialization -----
initial begin
`ifdef ENABLE_FORMAL_VERIFICATION
$deposit(A, 1'b0);
$deposit(B, 1'b0);
$deposit(S0, 1'b0);
`else
$deposit(A, $random);
$deposit(B, $random);
$deposit(S0, $random);
`endif
end
// ------ END driver initialization -----
`endif
endmodule |
module CARRY_MUX2(
input [0:0] A0, // Data input 0
input [0:0] A1, // Data input 1
input [0:0] S, // Select port
output [0:0] Y // Data output
);
assign Y = S ? A1 : A0;
// Note:
// MUX2 appears in the datapath logic driven by carry-in and LUT outputs
// where initial values and signal deposit are not required
endmodule |
module spram_4x1 (
input clk,
input[1:0] addr,
input d_in,
input wr_en,
output d_out );
reg[3:0] mem;
assign d_out = mem[addr];
always @(posedge clk) begin
if(wr_en) begin
mem[addr] <= d_in;
end
end
endmodule |
module mult_36x36 (
input [0:35] a,
input [0:35] b,
output [0:71] out,
input [0:1] mode);
reg [0:71] out_reg;
always @(mode, a, b) begin
if (2'b01 == mode) begin
out_reg[0:17] <= a[0:8] * b[0:8];
out_reg[18:35] <= a[9:17] * b[9:17];
out_reg[36:53] <= a[18:26] * b[18:26];
out_reg[54:71] <= a[27:35] * b[27:35];
end else if (2'b10 == mode) begin
out_reg[0:35] <= a[0:17] * b[0:17];
out_reg[36:71] <= a[18:35] * b[18:35];
end else begin
out_reg <= a * b;
end
end
assign out = out_reg;
endmodule |
module DFFQ (
input CK, // Clock Input
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (posedge CK) begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module |
module DFF (
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (posedge CK) begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module |
module DFFR (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module DFFRN (
input RSTN, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or negedge RSTN)
if (~RSTN) begin
q_reg <= 1'b0;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module DFFS (
input SET, // Set input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge SET)
if (SET) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module DFFSN (
input SETN, // Set input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or negedge SETN)
if (~SETN) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module DFFSR (
input SET, // set input
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
output QN // QB output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = ~q_reg;
endmodule //End Of Module |
module MULTI_MODE_DFFSRQ (
input SET, // Set input
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_set = mode[1] ? ~SET : SET;
wire post_rst = mode[0] ? ~RST : RST;
DFFSRQ FF_CORE (.SET(post_set),
.RST(post_rst),
.CK(CK),
.D(D),
.Q(Q)
);
endmodule //End Of Module |
module MULTI_MODE_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_rst = mode ? ~RST : RST;
DFFRQ FF_CORE (.RST(post_rst),
.CK(CK),
.D(D),
.Q(Q)
);
endmodule //End Of Module |
module MULTI_MODE_DFFNRQ (
input RST, // Reset input
input CK, // Clock Input
input D, // Data Input
output Q, // Q output
input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_rst = mode[0] ? ~RST : RST;
wire post_clk = mode[1] ? ~CK : CK;
DFFRQ FF_CORE (.RST(post_rst),
.CK(post_clk),
.D(D),
.Q(Q)
);
endmodule //End Of Module |
module SDFFSR (
input SET, // Set input
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST or posedge SET)
if (RST) begin
q_reg <= 1'b0;
end else if (SET) begin
q_reg <= 1'b1;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign Q = q_reg;
assign QN = !Q;
endmodule //End Of Module |
module SDFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
output Q // Q output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign Q = q_reg;
endmodule //End Of Module |
module CFGDSDFFR (
input RST, // Reset input
input CK, // Clock Input
input SE, // Scan-chain Enable
input D, // Data Input
input SI, // Scan-chain input
input CFGE, // Configure enable
input CFG_DONE, // Configure done
output Q, // Regular Q output
output CFGQ, // Data Q output which is released when configure enable is activated
output CFGQN // Data Qb output which is released when configure enable is activated
);
//------------Internal Variables--------
reg q_reg;
wire QN;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else if (SE) begin
q_reg <= SI;
end else begin
q_reg <= D;
end
assign CFGQ = CFGE ? Q : 1'b0;
assign CFGQN = CFGE ? QN : 1'b1;
assign Q = CFG_DONE ? q_reg : 1'b0;
assign QN = CFG_DONE ? !Q : 1'b1;
endmodule //End Of Module |
module BL_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SIN, // Data Input
output SOUT, // Q output
output BL // BL output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= SIN;
end
assign SOUT = q_reg;
assign BL = q_reg;
endmodule //End Of Module |
module WL_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SIN, // Data Input
input WEN, // Write-enable
output SOUT, // Q output
output WLW // Drive WL write signals
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= SIN;
end
assign SOUT = q_reg;
assign WLW = WEN ? q_reg : 1'b0;
endmodule //End Of Module |
module WLR_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SIN, // Data Input
input WEN, // Write-enable
output SOUT, // Q output
output WLW, // Drive WL write signals
output WLR // Drive WL read signals
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= SIN;
end
assign SOUT = q_reg;
assign WLW = WEN ? q_reg : 1'b0;
assign WLR = 1'b0; // Use a constant output just for simple testing
endmodule //End Of Module |
module frac_mult_16x16 (
input [0:15] a,
input [0:15] b,
output [0:31] out,
input [0:0] mode);
reg [0:31] out_reg;
always @(mode, a, b) begin
if (1'b1 == mode) begin
out_reg[0:15] <= a[0:7] * b[0:7];
out_reg[16:31] <= a[8:15] * b[8:15];
end else begin
out_reg <= a * b;
end
end
assign out = out_reg;
endmodule |
module LATCH (
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (WE or D) begin
if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule |
module LATCHR (
input RST, // Reset signal
input WE, // Write enable
input D, // Data input
output Q, // Q output
output QN // Q negative output
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ (RST or WE or D) begin
if (RST) begin
q_reg <= 1'b0;
end else if (1'b1 == WE) begin
q_reg <= D;
end
end
// Wire q_reg to Q
`ifndef ENABLE_FORMAL_VERIFICATION
assign Q = q_reg;
assign QN = ~q_reg;
`else
assign Q = 1'bZ;
assign QN = !Q;
`endif
endmodule |
module frac_mult_36x36
(
input wire [0:35] a,
input wire [0:35] b,
output wire [0:71] out,
input wire [0:1] mode
);
wire [0:35] mult_ll_out;
wire [0:35] mult_lh_out;
wire [0:35] mult_hl_out;
wire [0:35] mult_hh_out;
wire [0:36] sub_result1; // carry included
wire [0:35] sub_result2;
wire [0:71] result;
assign sub_result1 = mult_lh_out + mult_hl_out + {18'd0, mult_ll_out[0:17]};
assign sub_result2 = mult_hh_out + {17'd0, sub_result1[0:18]};
assign result[54:71] = mult_ll_out[18:35];
assign result[36:53] = sub_result1[19:36];
assign result[0:35] = sub_result2;
assign out[36:71] = (mode[0] == 1'b1) ? mult_ll_out : result[36:71];
assign out[0:35] = (mode[0] == 1'b1) ? mult_hh_out : result[0:35];
frac_mult_18x18 mult_ll (.a(a[18:35]), .b(b[18:35]), .out(mult_ll_out), .mode(mode[1]) ); // A_low*B_low
frac_mult_18x18 mult_lh (.a(a[18:35]), .b(b[0:17]), .out(mult_lh_out), .mode(1'b0) ); // A_low*B_high
frac_mult_18x18 mult_hl (.a(a[0:17]), .b(b[18:35]), .out(mult_hl_out), .mode(1'b0) ); // A_high*B_low
frac_mult_18x18 mult_hh (.a(a[0:17]), .b(b[0:17]), .out(mult_hh_out), .mode(mode[1])); // A_high*B_high
endmodule |
module frac_mult_18x18
(
input wire [0:17] a,
input wire [0:17] b,
output wire [0:35] out,
input wire [0:0] mode
);
wire [0:17] mult_ll_out;
wire [0:17] mult_lh_out;
wire [0:17] mult_hl_out;
wire [0:17] mult_hh_out;
wire [0:18] sub_result1; // carry included
wire [0:17] sub_result2;
wire [0:35] result;
assign sub_result1 = mult_lh_out + mult_hl_out + {9'd0, mult_ll_out[0:8]};
assign sub_result2 = mult_hh_out + {8'd0, sub_result1[0:9]};
assign result[27:35] = mult_ll_out[9:17];
assign result[18:26] = sub_result1[10:18];
assign result[0:17] = sub_result2;
assign out[18:35] = (mode == 1'b1) ? mult_ll_out : result[18:35];
assign out[0:17] = (mode == 1'b1) ? mult_hh_out : result[0:17];
multiplier #(9) mult_ll (.a(a[9:17]), .b(b[9:17]), .out(mult_ll_out) ); // A_low*B_low
multiplier #(9) mult_lh (.a(a[9:17]), .b(b[0:8]), .out(mult_lh_out) ); // A_low*B_high
multiplier #(9) mult_hl (.a(a[0:8]), .b(b[9:17]), .out(mult_hl_out) ); // A_high*B_low
multiplier #(9) mult_hh (.a(a[0:8]), .b(b[0:8]), .out(mult_hh_out) ); // A_high*B_high
endmodule |
module multiplier
#( parameter WIDTH = 9 )
(
input wire [0:WIDTH-1] a,
input wire [0:WIDTH-1] b,
output wire [0:2*WIDTH-1] out
);
assign out = a * b;
endmodule |
module OR2(a,
b,
out);
//----- INPUT PORTS -----
input [0:0] a;
//----- INPUT PORTS -----
input [0:0] b;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Verilog codes of a 2-input 1-output AND gate -----
assign out[0] = a[0] | b[0];
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(a[0] => out[0]) = (0.01, 0.01);
(b[0] => out[0]) = (0.005, 0.005);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
endmodule |
module mult_32x32 (
input [0:31] a,
input [0:31] b,
output [0:63] out,
input [0:1] mode);
reg [0:63] out_reg;
always @(mode, a, b) begin
if (2'b01 == mode) begin
out_reg[0:15] <= a[0:7] * b[0:7];
out_reg[16:31] <= a[8:15] * b[8:15];
out_reg[32:47] <= a[16:23] * b[16:23];
out_reg[48:63] <= a[24:31] * b[24:31];
end else if (2'b10 == mode) begin
out_reg[0:31] <= a[0:15] * b[0:15];
out_reg[32:63] <= a[16:31] * b[16:31];
end else begin
out_reg <= a * b;
end
end
assign out = out_reg;
endmodule |
module dpram_128x8 (
input clk,
input wen,
input ren,
input[0:6] waddr,
input[0:6] raddr,
input[0:7] d_in,
output[0:7] d_out );
dpram_128x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (d_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.d_out (d_out) );
endmodule |
module INVTX1(in, out);
input [0:0] in;
output [0:0] out;
assign out = ~in;
endmodule |
module GPIO (
input A, // Data output
output Y, // Data input
inout PAD, // bi-directional pad
input DIR // direction control
);
//----- when direction enabled, the signal is propagated from PAD to data input
assign Y = DIR ? PAD : 1'bz;
//----- when direction is disabled, the signal is propagated from data out to pad
assign PAD = DIR ? 1'bz : A;
endmodule |
module GPIO_CFGD (
input CONFIG_DONE, // Control signal to block signals
input A, // Data output
output Y, // Data input
inout PAD, // bi-directional pad
input DIR // direction control
);
//----- when direction enabled, the signal is propagated from PAD to data input
assign Y = CONFIG_DONE ? (DIR ? PAD : 1'bz) : 1'bz;
//----- when direction is disabled, the signal is propagated from data out to pad
assign PAD = CONFIG_DONE ? (DIR ? 1'bz : A) : 1'bz;
endmodule |
module GPIN (
inout A, // External PAD signal
output Y // Data input
);
assign Y = A;
endmodule |
module GPOUT (
inout Y, // External PAD signal
input A // Data output
);
assign Y = A;
endmodule |
module EMBEDDED_IO (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR // direction control
);
assign FPGA_IN = SOC_IN;
assign SOC_OUT = FPGA_OUT;
assign SOC_DIR = FPGA_DIR;
endmodule |
module EMBEDDED_IO_ISOLN (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output SOC_DIR, // Output the directionality
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_DIR, // direction control
input IO_ISOL_N // Active-low signal to set the I/O in input mode
);
assign FPGA_IN = IO_ISOL_N ? SOC_IN : 1'bz;
assign SOC_OUT = IO_ISOL_N ? FPGA_OUT : 1'bz;
// Direction signal is set to logic '0' when in input mode
assign SOC_DIR = IO_ISOL_N ? FPGA_DIR : 1'b0;
endmodule |
module AIB (
input TX_CLK,
input RX_CLK,
inout[0:79] PAD,
input[0:79] TX_DATA,
output[0:79] RX_DATA);
// May add the logic function of a real AIB
// Refer to the offical AIB github
// https://github.com/intel/aib-phy-hardware
endmodule |
module mult_8x8 (
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
assign Y = A * B;
endmodule |
module buf4(in,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Verilog codes of a regular inverter -----
//assign out = (in === 1'bz)? $random : in;
assign out = in;
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(in[0] => out[0]) = (0.01, 0.01);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
endmodule |
module frac_lut4_arith (
input [0:3] in,
input [0:0] cin,
output [0:1] lut3_out,
output [0:0] lut4_out,
output [0:0] cout,
input [0:15] sram,
input [0:1] mode);
//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:0] cin;
wire [0:1] lut2_out;
wire [0:1] lut3_out;
wire [0:0] lut4_out;
wire [0:0] cout;
wire [0:0] arith_in2;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] sky130_fd_sc_hd__buf_2_0_X;
wire [0:0] sky130_fd_sc_hd__buf_2_1_X;
wire [0:0] sky130_fd_sc_hd__buf_2_2_X;
wire [0:0] sky130_fd_sc_hd__buf_2_3_X;
wire [0:0] sky130_fd_sc_hd__inv_1_0_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_1_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_2_Y;
wire [0:0] sky130_fd_sc_hd__inv_1_3_Y;
wire [0:0] sky130_fd_sc_hd__or2_1_0_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_1_0_ (
.A(mode[1]),
.B(in[3]),
.X(sky130_fd_sc_hd__or2_1_0_X[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ (
.A(in[0]),
.Y(sky130_fd_sc_hd__inv_1_0_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ (
.A(in[1]),
.Y(sky130_fd_sc_hd__inv_1_1_Y[0]));
assign arith_in2 = mode[0] ? cin : in[2];
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ (
.A(arith_in2),
.Y(sky130_fd_sc_hd__inv_1_2_Y[0]));
sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.Y(sky130_fd_sc_hd__inv_1_3_Y[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(in[0]),
.X(sky130_fd_sc_hd__buf_2_0_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(in[1]),
.X(sky130_fd_sc_hd__buf_2_1_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(arith_in2),
.X(sky130_fd_sc_hd__buf_2_2_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__or2_1_0_X[0]),
.X(sky130_fd_sc_hd__buf_2_3_X[0]));
frac_lut4_mux frac_lut4_mux_0_ (
.in(sram[0:15]),
.sram({sky130_fd_sc_hd__buf_2_0_X[0], sky130_fd_sc_hd__buf_2_1_X[0], sky130_fd_sc_hd__buf_2_2_X[0], sky130_fd_sc_hd__buf_2_3_X[0]}),
.sram_inv({sky130_fd_sc_hd__inv_1_0_Y[0], sky130_fd_sc_hd__inv_1_1_Y[0], sky130_fd_sc_hd__inv_1_2_Y[0], sky130_fd_sc_hd__inv_1_3_Y[0]}),
.lut2_out(lut2_out[0:1]),
.lut3_out(lut3_out[0:1]),
.lut4_out(lut4_out[0]));
assign cout = lut2_out[0] ? cin : lut2_out[1];
endmodule |
module frac_lut4_mux(in,
sram,
sram_inv,
lut2_out,
lut3_out,
lut4_out);
//----- INPUT PORTS -----
input [0:15] in;
//----- INPUT PORTS -----
input [0:3] sram;
//----- INPUT PORTS -----
input [0:3] sram_inv;
//----- OUTPUT PORTS -----
output [0:1] lut2_out;
//----- OUTPUT PORTS -----
output [0:1] lut3_out;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] sky130_fd_sc_hd__buf_2_5_X;
wire [0:0] sky130_fd_sc_hd__buf_2_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_12_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_13_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_14_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X;
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ (
.A(sky130_fd_sc_hd__mux2_1_10_X[0]),
.X(lut2_out[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ (
.A(sky130_fd_sc_hd__mux2_1_11_X[0]),
.X(lut2_out[1]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ (
.A(sky130_fd_sc_hd__mux2_1_12_X[0]),
.X(lut3_out[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ (
.A(sky130_fd_sc_hd__mux2_1_13_X[0]),
.X(lut3_out[1]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ (
.A(sky130_fd_sc_hd__mux2_1_14_X[0]),
.X(lut4_out[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ (
.A(sky130_fd_sc_hd__mux2_1_8_X[0]),
.X(sky130_fd_sc_hd__buf_2_5_X[0]));
sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ (
.A(sky130_fd_sc_hd__mux2_1_9_X[0]),
.X(sky130_fd_sc_hd__buf_2_6_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ (
.A1(in[0]),
.A0(in[1]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_0_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ (
.A1(in[2]),
.A0(in[3]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_1_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ (
.A1(in[4]),
.A0(in[5]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_2_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ (
.A1(in[6]),
.A0(in[7]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_3_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ (
.A1(in[8]),
.A0(in[9]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_4_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ (
.A1(in[10]),
.A0(in[11]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_5_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ (
.A1(in[12]),
.A0(in[13]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_6_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ (
.A1(in[14]),
.A0(in[15]),
.S(sram[0]),
.X(sky130_fd_sc_hd__mux2_1_7_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_0_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_1_X[0]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_8_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_2_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_3_X[0]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_9_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ (
.A1(sky130_fd_sc_hd__mux2_1_4_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_5_X[0]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_10_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ (
.A1(sky130_fd_sc_hd__mux2_1_6_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_7_X[0]),
.S(sram[1]),
.X(sky130_fd_sc_hd__mux2_1_11_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
.A1(sky130_fd_sc_hd__buf_2_5_X[0]),
.A0(sky130_fd_sc_hd__buf_2_6_X[0]),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_12_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
.A1(sky130_fd_sc_hd__mux2_1_10_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_11_X[0]),
.S(sram[2]),
.X(sky130_fd_sc_hd__mux2_1_13_X[0]));
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
.A1(sky130_fd_sc_hd__mux2_1_12_X[0]),
.A0(sky130_fd_sc_hd__mux2_1_13_X[0]),
.S(sram[3]),
.X(sky130_fd_sc_hd__mux2_1_14_X[0]));
endmodule |
module lut6 (
input [5:0] in,
output out,
input [63:0] sram,
input [63:0] sram_inv);
assign out = sram[in];
endmodule |
module dpram_2048x8 (
input clk,
input wen,
input ren,
input[0:10] waddr,
input[0:10] raddr,
input[0:7] data_in,
output[0:7] data_out );
dpram_2048x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (data_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (data_out) );
endmodule |
module dpram_tb ();
reg clk;
reg wen;
reg ren;
reg[0:9] waddr;
reg[0:9] raddr;
reg[0:31] d_in;
wire[0:31] d_out;
integer count;
integer lim_max = 1023;
dpram memory_0 (
.clk (clk),
.wen (wen),
.waddr (waddr),
.d_in (d_in),
.ren (ren),
.raddr (raddr),
.d_out (d_out) );
initial begin
clk <= 1'b0;
ren <= 1'b0;
wen <= 1'b0;
raddr <= 10'h000;
waddr <= 10'h000;
d_in <= 32'h00000000;
for(count = 0; count < lim_max; count = count +1) begin
#5
wen <= 1'b1;
clk <= !clk;
if(clk) begin
waddr <= waddr + 1;
end
end
wen <= 1'b0;
for(count = 0; count < lim_max; count = count +1) begin
#5
ren <= 1'b1;
clk <= !clk;
if(clk) begin
raddr <= raddr + 1;
end
end
$finish;
end
always@(negedge clk) begin
d_in <= $random;
end
endmodule |
module cmos_mux2level_tb;
// Parameters
parameter SIZE_OF_MUX = 50; //---- MUX input size
parameter SIZE_OF_SRAM = 16; //---- MUX input size
parameter op_clk_period = 1; // [ns] half clock period
parameter operating_period = SIZE_OF_MUX * 2 * op_clk_period; // [ns] One full clock period
// voltage sources
wire [0:SIZE_OF_MUX-1] in;
wire out;
wire [0:SIZE_OF_SRAM-1] sram;
wire [0:SIZE_OF_SRAM-1] sram_inv;
// clocks
wire op_clock;
// registered ports
reg op_clock_reg;
reg [0:SIZE_OF_MUX-1] in_reg;
reg [0:SIZE_OF_SRAM-1] sram_reg;
reg [0:SIZE_OF_SRAM-1] sram_inv_reg;
// Config done signal;
reg config_done;
// Temp register for rotating shift
reg temp;
// Unit Under Test
mux_2level_size50 U0 (in, out, sram, sram_inv);
// Task: assign inputs
task op_mux_input;
begin
@(posedge op_clock);
temp = in_reg[SIZE_OF_MUX-1];
in_reg[1:SIZE_OF_MUX-1] = in_reg[0:SIZE_OF_MUX-2];
in_reg[0] = temp;
end
endtask
// Configuration done signal
initial
begin
config_done = 1'b1;
end
// Operating clocks
initial
begin
op_clock_reg = 1'b0;
end
always
begin
#op_clk_period op_clock_reg = ~op_clock_reg;
end
// Programming and Operating clocks
assign op_clock = op_clock_reg & config_done;
// Operating Phase
initial
begin
in_reg = {SIZE_OF_MUX {1'b0}};
in_reg[0] = 1'b1; // Last bit is 1 initially
end
always wait (config_done) // Only invoked when config_done is 1
begin
/* Update inputs */
op_mux_input;
end
// Wire ports
assign in = in_reg;
assign sram[0:7] = 8'b00010000;
assign sram[8:15] = 8'b00010000;
assign sram_inv = ~sram;
endmodule |
module static_dff_tb;
// voltage sources
wire set;
reg reset;
reg clk;
reg D;
wire Q;
// Parameters
parameter clk_period = 2; // [ns] a full clock period
parameter half_clk_period = clk_period / 2; // [ns] a half clock period
parameter d_period = 2 * clk_period; // [ns] two clock period
parameter reset_period = 8 * clk_period; // [ns] a full clock period
// Unit Under Test
static_dff U0 (set, reset, clk, D, Q);
// Voltage stimuli
// Reset : enable in the first clock cycle and then disabled
initial
begin
reset = 1'b1;
#clk_period reset = ~reset;
end
always
begin
#reset_period reset = ~reset;
end
// set : alway disabled
assign set = 1'b0;
// clk: clock generator
initial
begin
clk = 1'b0;
end
always
begin
#half_clk_period clk = ~clk;
end
// D: input, flip every two clock cycles
initial
begin
D = 1'b0;
end
always
begin
#d_period D = ~D;
end
// Q is an output
//
endmodule |
module fpga_top(prog_clk,
set,
reset,
clk,
gfpga_pad_GPIO_PAD,
ccff_head,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- GPIO PORTS -----
inout [0:31] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cbx_1__0__0_ccff_tail;
wire [0:12] cbx_1__0__0_chanx_left_out;
wire [0:12] cbx_1__0__0_chanx_right_out;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
wire [0:0] cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
wire [0:0] cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
wire [0:0] cbx_1__1__0_ccff_tail;
wire [0:12] cbx_1__1__0_chanx_left_out;
wire [0:12] cbx_1__1__0_chanx_right_out;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cby_0__1__0_ccff_tail;
wire [0:12] cby_0__1__0_chany_bottom_out;
wire [0:12] cby_0__1__0_chany_top_out;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
wire [0:0] cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
wire [0:0] cby_1__1__0_ccff_tail;
wire [0:12] cby_1__1__0_chany_bottom_out;
wire [0:12] cby_1__1__0_chany_top_out;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
wire [0:0] cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
wire [0:0] cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
wire [0:0] grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_;
wire [0:0] grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_;
wire [0:0] grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_;
wire [0:0] grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_;
wire [0:0] grid_io_bottom_0_ccff_tail;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_left_0_ccff_tail;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_right_0_ccff_tail;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
wire [0:0] grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
wire [0:0] grid_io_top_0_ccff_tail;
wire [0:0] sb_0__0__0_ccff_tail;
wire [0:12] sb_0__0__0_chanx_right_out;
wire [0:12] sb_0__0__0_chany_top_out;
wire [0:0] sb_0__1__0_ccff_tail;
wire [0:12] sb_0__1__0_chanx_right_out;
wire [0:12] sb_0__1__0_chany_bottom_out;
wire [0:0] sb_1__0__0_ccff_tail;
wire [0:12] sb_1__0__0_chanx_left_out;
wire [0:12] sb_1__0__0_chany_top_out;
wire [0:0] sb_1__1__0_ccff_tail;
wire [0:12] sb_1__1__0_chanx_left_out;
wire [0:12] sb_1__1__0_chany_bottom_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
grid_io_top grid_io_top_1__2_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0:7]),
.bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_top_0_ccff_tail));
grid_io_right grid_io_right_2__1_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[8:15]),
.left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_0_ccff_tail),
.left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_right_0_ccff_tail));
grid_io_bottom grid_io_bottom_1__0_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[16:23]),
.top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_bottom_0_ccff_tail));
grid_io_left grid_io_left_0__1_ (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[24:31]),
.right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
.right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
.right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
.right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
.right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
.right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
.right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cby_0__1__0_ccff_tail),
.right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(grid_io_left_0_ccff_tail));
grid_clb grid_clb_1__1_ (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
.top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
.top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
.right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
.right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
.right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
.bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
.bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
.bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
.left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
.left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
.ccff_head(cby_1__1__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.ccff_tail(ccff_tail));
sb_0__0_ sb_0__0_ (
.prog_clk(prog_clk),
.chany_top_in(cby_0__1__0_chany_bottom_out[0:12]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.chanx_right_in(cbx_1__0__0_chanx_left_out[0:12]),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
.ccff_tail(sb_0__0__0_ccff_tail));
sb_0__1_ sb_0__1_ (
.prog_clk(prog_clk),
.chanx_right_in(cbx_1__1__0_chanx_left_out[0:12]),
.right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.chany_bottom_in(cby_0__1__0_chany_top_out[0:12]),
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_(grid_clb_0_left_width_0_height_0_subtile_0__pin_O_1_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_top_0_ccff_tail),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:12]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_tail(sb_0__1__0_ccff_tail));
sb_1__0_ sb_1__0_ (
.prog_clk(prog_clk),
.chany_top_in(cby_1__1__0_chany_bottom_out[0:12]),
.top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.chanx_left_in(cbx_1__0__0_chanx_right_out[0:12]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_0_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_3__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_4__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__0__0_ccff_tail));
sb_1__1_ sb_1__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(cby_1__1__0_chany_top_out[0:12]),
.bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_2__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_3__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_4__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_right_0_left_width_0_height_0_subtile_7__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_(grid_clb_0_right_width_0_height_0_subtile_0__pin_O_3_),
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:12]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__1__0_ccff_tail));
cbx_1__0_ cbx_1__0_ (
.prog_clk(prog_clk),
.chanx_left_in(sb_0__0__0_chanx_right_out[0:12]),
.chanx_right_in(sb_1__0__0_chanx_left_out[0:12]),
.ccff_head(sb_1__0__0_ccff_tail),
.chanx_left_out(cbx_1__0__0_chanx_left_out[0:12]),
.chanx_right_out(cbx_1__0__0_chanx_right_out[0:12]),
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_),
.top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_),
.top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_(cbx_1__0__0_top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_tail(cbx_1__0__0_ccff_tail));
cbx_1__1_ cbx_1__1_ (
.prog_clk(prog_clk),
.chanx_left_in(sb_0__1__0_chanx_right_out[0:12]),
.chanx_right_in(sb_1__1__0_chanx_left_out[0:12]),
.ccff_head(sb_1__1__0_ccff_tail),
.chanx_left_out(cbx_1__1__0_chanx_left_out[0:12]),
.chanx_right_out(cbx_1__1__0_chanx_right_out[0:12]),
.top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_),
.bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_(cbx_1__1__0_bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_),
.ccff_tail(cbx_1__1__0_ccff_tail));
cby_0__1_ cby_0__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
.right_grid_left_width_0_height_0_subtile_0__pin_I_7_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_7_),
.left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_(cby_0__1__0_left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_tail(cby_0__1__0_ccff_tail));
cby_1__1_ cby_1__1_ (
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_),
.right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_1_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_1_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_5_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_5_),
.left_grid_right_width_0_height_0_subtile_0__pin_I_9_(cby_1__1__0_left_grid_right_width_0_height_0_subtile_0__pin_I_9_),
.ccff_tail(cby_1__1__0_ccff_tail));
endmodule |
module and2_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] c_gfpga;
// ----- Benchmark outputs -------
wire [0:0] c_bench;
// ----- Output vectors checking flags -------
reg [0:0] c_flag;
// ----- Error counter -------
integer nb_error= 0;
// ----- FPGA fabric instanciation -------
and2_top_formal_verification FPGA_DUT(
.a(a),
.b(b),
.c(c_gfpga)
);
// ----- End FPGA Fabric Instanication -------
// ----- Reference Benchmark Instanication -------
and2 REF_DUT(
.a(a),
.b(b),
.c(c_bench)
);
// ----- End reference Benchmark Instanication -------
// ----- Clock 'clk' Initialization -------
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.4880859554
clk[0] <= !clk[0];
end
end
// ----- Begin reset signal generation -----
// ----- End reset signal generation -----
// ----- Input Initialization -------
initial begin
a <= 1'b0;
b <= 1'b0;
c_flag[0] <= 1'b0;
end
// ----- Input Stimulus -------
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else
begin
if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
c_flag <= 1'b1;
end else begin
c_flag<= 1'b0;
end
end
end
always@(posedge c_flag) begin
if(c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on c_gfpga at time = %t", $realtime);
end
end
// ----- Begin output waveform to VCD file-------
initial begin
$dumpfile("and2_formal.vcd");
$dumpvars(1, and2_top_formal_verification_random_tb);
end
// ----- END output waveform to VCD file -------
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#6.833203316
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule |
module sb_1__0_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:12] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chany_top_out;
//----- OUTPUT PORTS -----
output [0:12] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_10_sram;
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_11_sram;
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_7_sram;
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_8_sram;
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_9_sram;
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_6_sram;
wire [0:2] mux_tree_tapbuf_size4_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size4 mux_top_track_2 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[12]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size4 mux_top_track_14 (
.in({top_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size4 mux_left_track_1 (
.in({chany_top_in[0], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size4 mux_left_track_3 (
.in({chany_top_in[12], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size4 mux_left_track_13 (
.in({chany_top_in[7], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size4 mux_left_track_15 (
.in({chany_top_in[6], left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_6_sram_inv[0:2]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size4_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_6_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_top_track_4 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[11]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size3 mux_top_track_6 (
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size3 mux_top_track_8 (
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size3 mux_top_track_10 (
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size3 mux_top_track_12 (
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size3 mux_top_track_16 (
.in({top_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size3 mux_left_track_5 (
.in({chany_top_in[11], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size3 mux_left_track_7 (
.in({chany_top_in[10], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size3 mux_left_track_9 (
.in({chany_top_in[9], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size3 mux_left_track_11 (
.in({chany_top_in[8], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size3 mux_left_track_17 (
.in({chany_top_in[5], left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size3 mux_left_track_25 (
.in({chany_top_in[1], left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
.out(chanx_left_out[12]));
mux_tree_tapbuf_size3_mem mem_top_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_25 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_top_track_18 (
.in({top_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_tree_tapbuf_size2 mux_top_track_20 (
.in({top_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[10]));
mux_tree_tapbuf_size2 mux_top_track_22 (
.in({top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[11]));
mux_tree_tapbuf_size2 mux_top_track_24 (
.in({top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_top_out[12]));
mux_tree_tapbuf_size2 mux_left_track_19 (
.in({chany_top_in[4], left_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_tree_tapbuf_size2 mux_left_track_21 (
.in({chany_top_in[3], left_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_left_out[10]));
mux_tree_tapbuf_size2 mux_left_track_23 (
.in({chany_top_in[2], left_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chanx_left_out[11]));
mux_tree_tapbuf_size2_mem mem_top_track_18 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_20 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_22 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_24 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_21 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_23 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
endmodule |
module cby_0__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_I_3_,
right_grid_left_width_0_height_0_subtile_0__pin_I_7_,
left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chany_bottom_in;
//----- INPUT PORTS -----
input [0:12] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:12] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_3_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_I_7_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_8_sram;
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_9_sram;
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[11] = chany_bottom_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[12] = chany_bottom_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[11] = chany_top_in[11];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[12] = chany_top_in[12];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size6 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_3_));
mux_tree_tapbuf_size6 mux_left_ipin_1 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_I_7_));
mux_tree_tapbuf_size6 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_1 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_2 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_3 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_4 (
.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_5 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_6 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_7 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size6_mem mem_left_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
endmodule |
module cbx_1__0_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chanx_left_in;
//----- INPUT PORTS -----
input [0:12] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:12] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_10_sram;
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_8_sram;
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_9_sram;
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[11] = chanx_left_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[12] = chanx_left_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[11] = chanx_right_in[11];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[12] = chanx_right_in[12];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size6 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));
mux_tree_tapbuf_size6 mux_bottom_ipin_1 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));
mux_tree_tapbuf_size6 mux_bottom_ipin_2 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));
mux_tree_tapbuf_size6 mux_top_ipin_0 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_1 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_2 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_3 (
.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_4 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_5 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_6 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_7 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
endmodule |
module sb_0__0_(prog_clk,
chany_top_in,
top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chany_top_out,
chanx_right_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chany_top_in;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:12] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chany_top_out;
//----- OUTPUT PORTS -----
output [0:12] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_10_sram;
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_11_sram;
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_12_sram;
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_13_sram;
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_7_sram;
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_8_sram;
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_9_sram;
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_5_sram;
wire [0:2] mux_tree_tapbuf_size4_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_top_track_0 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[1]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chany_top_out[0]));
mux_tree_tapbuf_size4 mux_top_track_12 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(chany_top_out[6]));
mux_tree_tapbuf_size4 mux_right_track_0 (
.in({chany_top_in[12], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size4 mux_right_track_2 (
.in({chany_top_in[0], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size4 mux_right_track_12 (
.in({chany_top_in[5], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size4 mux_right_track_14 (
.in({chany_top_in[6], right_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_5_sram_inv[0:2]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size4_mem mem_top_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_top_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_5_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_top_track_2 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, chanx_right_in[2]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_top_out[1]));
mux_tree_tapbuf_size3 mux_top_track_4 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[3]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_top_out[2]));
mux_tree_tapbuf_size3 mux_top_track_6 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[4]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.out(chany_top_out[3]));
mux_tree_tapbuf_size3 mux_top_track_8 (
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[5]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.out(chany_top_out[4]));
mux_tree_tapbuf_size3 mux_top_track_10 (
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[6]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.out(chany_top_out[5]));
mux_tree_tapbuf_size3 mux_top_track_14 (
.in({top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_, chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.out(chany_top_out[7]));
mux_tree_tapbuf_size3 mux_top_track_16 (
.in({top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, top_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
.out(chany_top_out[8]));
mux_tree_tapbuf_size3 mux_top_track_24 (
.in({top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, chanx_right_in[0]}),
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
.out(chany_top_out[12]));
mux_tree_tapbuf_size3 mux_right_track_4 (
.in({chany_top_in[1], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size3 mux_right_track_6 (
.in({chany_top_in[2], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size3 mux_right_track_8 (
.in({chany_top_in[3], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size3 mux_right_track_10 (
.in({chany_top_in[4], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size3 mux_right_track_16 (
.in({chany_top_in[7], right_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size3 mux_right_track_24 (
.in({chany_top_in[11], right_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_, right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
.out(chanx_right_out[12]));
mux_tree_tapbuf_size3_mem mem_top_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_top_track_24 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_24 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_top_track_18 (
.in({top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_top_out[9]));
mux_tree_tapbuf_size2 mux_top_track_20 (
.in({top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, chanx_right_in[11]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_top_out[10]));
mux_tree_tapbuf_size2 mux_top_track_22 (
.in({top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, chanx_right_in[12]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_top_out[11]));
mux_tree_tapbuf_size2 mux_right_track_18 (
.in({chany_top_in[8], right_bottom_grid_top_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_tree_tapbuf_size2 mux_right_track_20 (
.in({chany_top_in[9], right_bottom_grid_top_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_right_out[10]));
mux_tree_tapbuf_size2 mux_right_track_22 (
.in({chany_top_in[10], right_bottom_grid_top_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_right_out[11]));
mux_tree_tapbuf_size2_mem mem_top_track_18 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_20 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_top_track_22 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_18 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_20 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_22 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
endmodule |
module sb_1__1_(prog_clk,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
chanx_left_in,
left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
ccff_head,
chany_bottom_out,
chanx_left_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;
//----- INPUT PORTS -----
input [0:12] chanx_left_in;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:12] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_10_sram;
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_11_sram;
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_12_sram;
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_13_sram;
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_14_sram;
wire [0:1] mux_tree_tapbuf_size3_14_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_15_sram;
wire [0:1] mux_tree_tapbuf_size3_15_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_7_sram;
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_8_sram;
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_9_sram;
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_14_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_bottom_track_1 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size4 mux_bottom_track_13 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size4 mux_left_track_1 (
.in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(chanx_left_out[0]));
mux_tree_tapbuf_size4 mux_left_track_13 (
.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(chanx_left_out[6]));
mux_tree_tapbuf_size4_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_left_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_bottom_track_3 (
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size3 mux_bottom_track_5 (
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size3 mux_bottom_track_7 (
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size3 mux_bottom_track_9 (
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size3 mux_bottom_track_11 (
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size3 mux_bottom_track_15 (
.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size3 mux_bottom_track_17 (
.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size3 mux_bottom_track_25 (
.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
.out(chany_bottom_out[12]));
mux_tree_tapbuf_size3 mux_left_track_3 (
.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
.out(chanx_left_out[1]));
mux_tree_tapbuf_size3 mux_left_track_5 (
.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
.out(chanx_left_out[2]));
mux_tree_tapbuf_size3 mux_left_track_7 (
.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
.out(chanx_left_out[3]));
mux_tree_tapbuf_size3 mux_left_track_9 (
.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
.out(chanx_left_out[4]));
mux_tree_tapbuf_size3 mux_left_track_11 (
.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
.out(chanx_left_out[5]));
mux_tree_tapbuf_size3 mux_left_track_15 (
.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
.out(chanx_left_out[7]));
mux_tree_tapbuf_size3 mux_left_track_17 (
.in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
.sram(mux_tree_tapbuf_size3_14_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_14_sram_inv[0:1]),
.out(chanx_left_out[8]));
mux_tree_tapbuf_size3 mux_left_track_25 (
.in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_15_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_15_sram_inv[0:1]),
.out(chanx_left_out[12]));
mux_tree_tapbuf_size3_mem mem_bottom_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_25 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_14_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_14_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_14_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_left_track_25 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size3_15_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_15_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_bottom_track_19 (
.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chany_bottom_out[9]));
mux_tree_tapbuf_size2 mux_bottom_track_21 (
.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chany_bottom_out[10]));
mux_tree_tapbuf_size2 mux_bottom_track_23 (
.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chany_bottom_out[11]));
mux_tree_tapbuf_size2 mux_left_track_19 (
.in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chanx_left_out[9]));
mux_tree_tapbuf_size2 mux_left_track_21 (
.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chanx_left_out[10]));
mux_tree_tapbuf_size2 mux_left_track_23 (
.in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chanx_left_out[11]));
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_23 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_14_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_21 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_left_track_23 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
endmodule |
module cbx_1__1_(prog_clk,
chanx_left_in,
chanx_right_in,
ccff_head,
chanx_left_out,
chanx_right_out,
top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_,
top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_,
bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chanx_left_in;
//----- INPUT PORTS -----
input [0:12] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chanx_left_out;
//----- OUTPUT PORTS -----
output [0:12] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_;
//----- OUTPUT PORTS -----
output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_10_sram;
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_8_sram;
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_9_sram;
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[0] = chanx_left_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[1] = chanx_left_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[2] = chanx_left_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[3] = chanx_left_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[4] = chanx_left_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[5] = chanx_left_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[6] = chanx_left_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[7] = chanx_left_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[8] = chanx_left_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[9] = chanx_left_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[10] = chanx_left_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[11] = chanx_left_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_right_out[12] = chanx_left_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[0] = chanx_right_in[0];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[1] = chanx_right_in[1];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[2] = chanx_right_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[3] = chanx_right_in[3];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[4] = chanx_right_in[4];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[5] = chanx_right_in[5];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[6] = chanx_right_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[7] = chanx_right_in[7];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[8] = chanx_right_in[8];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[9] = chanx_right_in[9];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[10] = chanx_right_in[10];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[11] = chanx_right_in[11];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chanx_left_out[12] = chanx_right_in[12];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size6 mux_bottom_ipin_0 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_1 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_2 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_3 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_4 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_5 (
.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_6 (
.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_bottom_ipin_7 (
.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
.out(top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_top_ipin_0 (
.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_));
mux_tree_tapbuf_size6 mux_top_ipin_1 (
.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_));
mux_tree_tapbuf_size6 mux_top_ipin_2 (
.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
.out(bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_bottom_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_top_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
endmodule |
module cby_1__1_(prog_clk,
chany_bottom_in,
chany_top_in,
ccff_head,
chany_bottom_out,
chany_top_out,
right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_,
right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_,
left_grid_right_width_0_height_0_subtile_0__pin_I_1_,
left_grid_right_width_0_height_0_subtile_0__pin_I_5_,
left_grid_right_width_0_height_0_subtile_0__pin_I_9_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chany_bottom_in;
//----- INPUT PORTS -----
input [0:12] chany_top_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:12] chany_top_out;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_1_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_5_;
//----- OUTPUT PORTS -----
output [0:0] left_grid_right_width_0_height_0_subtile_0__pin_I_9_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:2] mux_tree_tapbuf_size6_0_sram;
wire [0:2] mux_tree_tapbuf_size6_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_10_sram;
wire [0:2] mux_tree_tapbuf_size6_10_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_1_sram;
wire [0:2] mux_tree_tapbuf_size6_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_2_sram;
wire [0:2] mux_tree_tapbuf_size6_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_3_sram;
wire [0:2] mux_tree_tapbuf_size6_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_4_sram;
wire [0:2] mux_tree_tapbuf_size6_4_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_5_sram;
wire [0:2] mux_tree_tapbuf_size6_5_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_6_sram;
wire [0:2] mux_tree_tapbuf_size6_6_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_7_sram;
wire [0:2] mux_tree_tapbuf_size6_7_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_8_sram;
wire [0:2] mux_tree_tapbuf_size6_8_sram_inv;
wire [0:2] mux_tree_tapbuf_size6_9_sram;
wire [0:2] mux_tree_tapbuf_size6_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- Local connection due to Wire 0 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[0] = chany_bottom_in[0];
// ----- Local connection due to Wire 1 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[1] = chany_bottom_in[1];
// ----- Local connection due to Wire 2 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[2] = chany_bottom_in[2];
// ----- Local connection due to Wire 3 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[3] = chany_bottom_in[3];
// ----- Local connection due to Wire 4 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[4] = chany_bottom_in[4];
// ----- Local connection due to Wire 5 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[5] = chany_bottom_in[5];
// ----- Local connection due to Wire 6 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[6] = chany_bottom_in[6];
// ----- Local connection due to Wire 7 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[7] = chany_bottom_in[7];
// ----- Local connection due to Wire 8 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[8] = chany_bottom_in[8];
// ----- Local connection due to Wire 9 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[9] = chany_bottom_in[9];
// ----- Local connection due to Wire 10 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[10] = chany_bottom_in[10];
// ----- Local connection due to Wire 11 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[11] = chany_bottom_in[11];
// ----- Local connection due to Wire 12 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_top_out[12] = chany_bottom_in[12];
// ----- Local connection due to Wire 13 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[0] = chany_top_in[0];
// ----- Local connection due to Wire 14 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[1] = chany_top_in[1];
// ----- Local connection due to Wire 15 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[2] = chany_top_in[2];
// ----- Local connection due to Wire 16 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[3] = chany_top_in[3];
// ----- Local connection due to Wire 17 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[4] = chany_top_in[4];
// ----- Local connection due to Wire 18 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[5] = chany_top_in[5];
// ----- Local connection due to Wire 19 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[6] = chany_top_in[6];
// ----- Local connection due to Wire 20 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[7] = chany_top_in[7];
// ----- Local connection due to Wire 21 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[8] = chany_top_in[8];
// ----- Local connection due to Wire 22 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[9] = chany_top_in[9];
// ----- Local connection due to Wire 23 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[10] = chany_top_in[10];
// ----- Local connection due to Wire 24 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[11] = chany_top_in[11];
// ----- Local connection due to Wire 25 -----
// ----- Net source id 0 -----
// ----- Net sink id 0 -----
assign chany_bottom_out[12] = chany_top_in[12];
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size6 mux_left_ipin_0 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size6_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_0_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_1 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size6_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_1_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_2 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size6_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_2_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_3 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size6_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_3_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_4 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[4], chany_top_in[4], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size6_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_4_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_5 (
.in({chany_bottom_in[4], chany_top_in[4], chany_bottom_in[5], chany_top_in[5], chany_bottom_in[11], chany_top_in[11]}),
.sram(mux_tree_tapbuf_size6_5_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_5_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_6 (
.in({chany_bottom_in[5], chany_top_in[5], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[12], chany_top_in[12]}),
.sram(mux_tree_tapbuf_size6_6_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_6_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_left_ipin_7 (
.in({chany_bottom_in[0], chany_top_in[0], chany_bottom_in[6], chany_top_in[6], chany_bottom_in[7], chany_top_in[7]}),
.sram(mux_tree_tapbuf_size6_7_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_7_sram_inv[0:2]),
.out(right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_));
mux_tree_tapbuf_size6 mux_right_ipin_0 (
.in({chany_bottom_in[1], chany_top_in[1], chany_bottom_in[7], chany_top_in[7], chany_bottom_in[8], chany_top_in[8]}),
.sram(mux_tree_tapbuf_size6_8_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_8_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_1_));
mux_tree_tapbuf_size6 mux_right_ipin_1 (
.in({chany_bottom_in[2], chany_top_in[2], chany_bottom_in[8], chany_top_in[8], chany_bottom_in[9], chany_top_in[9]}),
.sram(mux_tree_tapbuf_size6_9_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_9_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_5_));
mux_tree_tapbuf_size6 mux_right_ipin_2 (
.in({chany_bottom_in[3], chany_top_in[3], chany_bottom_in[9], chany_top_in[9], chany_bottom_in[10], chany_top_in[10]}),
.sram(mux_tree_tapbuf_size6_10_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size6_10_sram_inv[0:2]),
.out(left_grid_right_width_0_height_0_subtile_0__pin_I_9_));
mux_tree_tapbuf_size6_mem mem_left_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_0_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_1_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_2_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_3_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_4_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_5_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_5_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_6_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_6_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_left_ipin_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_7_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_7_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_8_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_8_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size6_9_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_9_sram_inv[0:2]));
mux_tree_tapbuf_size6_mem mem_right_ipin_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size6_mem_9_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size6_10_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size6_10_sram_inv[0:2]));
endmodule |
module sb_0__1_(prog_clk,
chanx_right_in,
right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
chany_bottom_in,
bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_,
bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_head,
chanx_right_out,
chany_bottom_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:12] chanx_right_in;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;
//----- INPUT PORTS -----
input [0:12] chany_bottom_in;
//----- INPUT PORTS -----
input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:12] chanx_right_out;
//----- OUTPUT PORTS -----
output [0:12] chany_bottom_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_1_sram;
wire [0:1] mux_tree_tapbuf_size2_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_2_sram;
wire [0:1] mux_tree_tapbuf_size2_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_3_sram;
wire [0:1] mux_tree_tapbuf_size2_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_4_sram;
wire [0:1] mux_tree_tapbuf_size2_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_5_sram;
wire [0:1] mux_tree_tapbuf_size2_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size2_6_sram;
wire [0:1] mux_tree_tapbuf_size2_6_sram_inv;
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail;
wire [0:1] mux_tree_tapbuf_size3_0_sram;
wire [0:1] mux_tree_tapbuf_size3_0_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_10_sram;
wire [0:1] mux_tree_tapbuf_size3_10_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_11_sram;
wire [0:1] mux_tree_tapbuf_size3_11_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_12_sram;
wire [0:1] mux_tree_tapbuf_size3_12_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_13_sram;
wire [0:1] mux_tree_tapbuf_size3_13_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_1_sram;
wire [0:1] mux_tree_tapbuf_size3_1_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_2_sram;
wire [0:1] mux_tree_tapbuf_size3_2_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_3_sram;
wire [0:1] mux_tree_tapbuf_size3_3_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_4_sram;
wire [0:1] mux_tree_tapbuf_size3_4_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_5_sram;
wire [0:1] mux_tree_tapbuf_size3_5_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_6_sram;
wire [0:1] mux_tree_tapbuf_size3_6_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_7_sram;
wire [0:1] mux_tree_tapbuf_size3_7_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_8_sram;
wire [0:1] mux_tree_tapbuf_size3_8_sram_inv;
wire [0:1] mux_tree_tapbuf_size3_9_sram;
wire [0:1] mux_tree_tapbuf_size3_9_sram_inv;
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_10_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_11_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_12_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_13_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail;
wire [0:0] mux_tree_tapbuf_size3_mem_9_ccff_tail;
wire [0:2] mux_tree_tapbuf_size4_0_sram;
wire [0:2] mux_tree_tapbuf_size4_0_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_1_sram;
wire [0:2] mux_tree_tapbuf_size4_1_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_2_sram;
wire [0:2] mux_tree_tapbuf_size4_2_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_3_sram;
wire [0:2] mux_tree_tapbuf_size4_3_sram_inv;
wire [0:2] mux_tree_tapbuf_size4_4_sram;
wire [0:2] mux_tree_tapbuf_size4_4_sram_inv;
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail;
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
mux_tree_tapbuf_size4 mux_right_track_0 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[11]}),
.sram(mux_tree_tapbuf_size4_0_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_0_sram_inv[0:2]),
.out(chanx_right_out[0]));
mux_tree_tapbuf_size4 mux_right_track_12 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[5]}),
.sram(mux_tree_tapbuf_size4_1_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_1_sram_inv[0:2]),
.out(chanx_right_out[6]));
mux_tree_tapbuf_size4 mux_bottom_track_1 (
.in({chanx_right_in[11], bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_2_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_2_sram_inv[0:2]),
.out(chany_bottom_out[0]));
mux_tree_tapbuf_size4 mux_bottom_track_3 (
.in({chanx_right_in[10], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_3_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_3_sram_inv[0:2]),
.out(chany_bottom_out[1]));
mux_tree_tapbuf_size4 mux_bottom_track_15 (
.in({chanx_right_in[4], bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size4_4_sram[0:2]),
.sram_inv(mux_tree_tapbuf_size4_4_sram_inv[0:2]),
.out(chany_bottom_out[7]));
mux_tree_tapbuf_size4_mem mem_right_track_0 (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_0_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_0_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_right_track_12 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_1_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_1_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_track_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_2_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_2_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_track_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_3_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_3_sram_inv[0:2]));
mux_tree_tapbuf_size4_mem mem_bottom_track_15 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size4_4_sram[0:2]),
.mem_outb(mux_tree_tapbuf_size4_4_sram_inv[0:2]));
mux_tree_tapbuf_size3 mux_right_track_2 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, chany_bottom_in[10]}),
.sram(mux_tree_tapbuf_size3_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_0_sram_inv[0:1]),
.out(chanx_right_out[1]));
mux_tree_tapbuf_size3 mux_right_track_4 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[9]}),
.sram(mux_tree_tapbuf_size3_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_1_sram_inv[0:1]),
.out(chanx_right_out[2]));
mux_tree_tapbuf_size3 mux_right_track_6 (
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[8]}),
.sram(mux_tree_tapbuf_size3_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_2_sram_inv[0:1]),
.out(chanx_right_out[3]));
mux_tree_tapbuf_size3 mux_right_track_8 (
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[7]}),
.sram(mux_tree_tapbuf_size3_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_3_sram_inv[0:1]),
.out(chanx_right_out[4]));
mux_tree_tapbuf_size3 mux_right_track_10 (
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[6]}),
.sram(mux_tree_tapbuf_size3_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_4_sram_inv[0:1]),
.out(chanx_right_out[5]));
mux_tree_tapbuf_size3 mux_right_track_14 (
.in({right_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_, chany_bottom_in[4]}),
.sram(mux_tree_tapbuf_size3_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_5_sram_inv[0:1]),
.out(chanx_right_out[7]));
mux_tree_tapbuf_size3 mux_right_track_16 (
.in({right_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_, chany_bottom_in[3]}),
.sram(mux_tree_tapbuf_size3_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_6_sram_inv[0:1]),
.out(chanx_right_out[8]));
mux_tree_tapbuf_size3 mux_right_track_24 (
.in({right_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, right_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, chany_bottom_in[12]}),
.sram(mux_tree_tapbuf_size3_7_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_7_sram_inv[0:1]),
.out(chanx_right_out[12]));
mux_tree_tapbuf_size3 mux_bottom_track_5 (
.in({chanx_right_in[9], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_8_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_8_sram_inv[0:1]),
.out(chany_bottom_out[2]));
mux_tree_tapbuf_size3 mux_bottom_track_7 (
.in({chanx_right_in[8], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_9_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_9_sram_inv[0:1]),
.out(chany_bottom_out[3]));
mux_tree_tapbuf_size3 mux_bottom_track_9 (
.in({chanx_right_in[7], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_10_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_10_sram_inv[0:1]),
.out(chany_bottom_out[4]));
mux_tree_tapbuf_size3 mux_bottom_track_11 (
.in({chanx_right_in[6], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_11_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_11_sram_inv[0:1]),
.out(chany_bottom_out[5]));
mux_tree_tapbuf_size3 mux_bottom_track_13 (
.in({chanx_right_in[5], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_12_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_12_sram_inv[0:1]),
.out(chany_bottom_out[6]));
mux_tree_tapbuf_size3 mux_bottom_track_17 (
.in({chanx_right_in[3], bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size3_13_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size3_13_sram_inv[0:1]),
.out(chany_bottom_out[8]));
mux_tree_tapbuf_size3_mem mem_right_track_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_0_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_4 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_1_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_6 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_2_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_8 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_3_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_10 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_4_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_14 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_5_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_16 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_5_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_6_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_right_track_24 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_7_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_7_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_7_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_5 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_8_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_8_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_7 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_8_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_9_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_9_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_9 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_9_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_10_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_10_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_11 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_10_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_11_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_11_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_13 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_11_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_12_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_12_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_12_sram_inv[0:1]));
mux_tree_tapbuf_size3_mem mem_bottom_track_17 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size4_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.mem_out(mux_tree_tapbuf_size3_13_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size3_13_sram_inv[0:1]));
mux_tree_tapbuf_size2 mux_right_track_18 (
.in({right_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, chany_bottom_in[2]}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(chanx_right_out[9]));
mux_tree_tapbuf_size2 mux_right_track_20 (
.in({right_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, chany_bottom_in[1]}),
.sram(mux_tree_tapbuf_size2_1_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_1_sram_inv[0:1]),
.out(chanx_right_out[10]));
mux_tree_tapbuf_size2 mux_right_track_22 (
.in({right_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, chany_bottom_in[0]}),
.sram(mux_tree_tapbuf_size2_2_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_2_sram_inv[0:1]),
.out(chanx_right_out[11]));
mux_tree_tapbuf_size2 mux_bottom_track_19 (
.in({chanx_right_in[2], bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_3_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_3_sram_inv[0:1]),
.out(chany_bottom_out[9]));
mux_tree_tapbuf_size2 mux_bottom_track_21 (
.in({chanx_right_in[1], bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_4_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_4_sram_inv[0:1]),
.out(chany_bottom_out[10]));
mux_tree_tapbuf_size2 mux_bottom_track_23 (
.in({chanx_right_in[0], bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_5_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_5_sram_inv[0:1]),
.out(chany_bottom_out[11]));
mux_tree_tapbuf_size2 mux_bottom_track_25 (
.in({chanx_right_in[12], bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_}),
.sram(mux_tree_tapbuf_size2_6_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_6_sram_inv[0:1]),
.out(chany_bottom_out[12]));
mux_tree_tapbuf_size2_mem mem_right_track_18 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_6_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_20 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_0_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_1_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_1_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_right_track_22 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_1_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_2_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_2_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_2_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_19 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size3_mem_13_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_3_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_3_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_21 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_3_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_4_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_4_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_23 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_4_ccff_tail),
.ccff_tail(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.mem_out(mux_tree_tapbuf_size2_5_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_5_sram_inv[0:1]));
mux_tree_tapbuf_size2_mem mem_bottom_track_25 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_tapbuf_size2_mem_5_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_6_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_6_sram_inv[0:1]));
endmodule |
module grid_io_top(prog_clk,
gfpga_pad_GPIO_PAD,
bottom_width_0_height_0_subtile_0__pin_outpad_0_,
bottom_width_0_height_0_subtile_1__pin_outpad_0_,
bottom_width_0_height_0_subtile_2__pin_outpad_0_,
bottom_width_0_height_0_subtile_3__pin_outpad_0_,
bottom_width_0_height_0_subtile_4__pin_outpad_0_,
bottom_width_0_height_0_subtile_5__pin_outpad_0_,
bottom_width_0_height_0_subtile_6__pin_outpad_0_,
bottom_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
bottom_width_0_height_0_subtile_0__pin_inpad_0_,
bottom_width_0_height_0_subtile_1__pin_inpad_0_,
bottom_width_0_height_0_subtile_2__pin_inpad_0_,
bottom_width_0_height_0_subtile_3__pin_inpad_0_,
bottom_width_0_height_0_subtile_4__pin_inpad_0_,
bottom_width_0_height_0_subtile_5__pin_inpad_0_,
bottom_width_0_height_0_subtile_6__pin_inpad_0_,
bottom_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(bottom_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(bottom_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(bottom_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(bottom_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(bottom_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set,
reset,
clk,
ff_D,
ff_Q,
ff_clk);
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:0] ff_D;
//----- OUTPUT PORTS -----
output [0:0] ff_Q;
//----- CLOCK PORTS -----
input [0:0] ff_clk;
//----- BEGIN wire-connection ports -----
wire [0:0] ff_D;
wire [0:0] ff_Q;
wire [0:0] ff_clk;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
DFFSRQ DFFSRQ_0_ (
.SET(set),
.RST(reset),
.CK(clk),
.D(ff_D),
.Q(ff_Q));
endmodule |
module logical_tile_clb_mode_default__fle(prog_clk,
set,
reset,
clk,
fle_in,
fle_clk,
ccff_head,
fle_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:3] fle_in;
//----- INPUT PORTS -----
input [0:0] fle_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] fle_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] fle_in;
wire [0:0] fle_clk;
wire [0:0] fle_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.ble4_in({direct_interc_1_out, direct_interc_2_out, direct_interc_3_out, direct_interc_4_out}),
.ble4_clk(direct_interc_5_out),
.ccff_head(ccff_head),
.ble4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0_ble4_out),
.out(fle_out));
direct_interc direct_interc_1_ (
.in(fle_in[0]),
.out(direct_interc_1_out));
direct_interc direct_interc_2_ (
.in(fle_in[1]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(fle_in[2]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(fle_in[3]),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(fle_clk),
.out(direct_interc_5_out));
endmodule |
module grid_clb(prog_clk,
set,
reset,
clk,
top_width_0_height_0_subtile_0__pin_I_0_,
top_width_0_height_0_subtile_0__pin_I_4_,
top_width_0_height_0_subtile_0__pin_I_8_,
right_width_0_height_0_subtile_0__pin_I_1_,
right_width_0_height_0_subtile_0__pin_I_5_,
right_width_0_height_0_subtile_0__pin_I_9_,
bottom_width_0_height_0_subtile_0__pin_I_2_,
bottom_width_0_height_0_subtile_0__pin_I_6_,
bottom_width_0_height_0_subtile_0__pin_clk_0_,
left_width_0_height_0_subtile_0__pin_I_3_,
left_width_0_height_0_subtile_0__pin_I_7_,
ccff_head,
top_width_0_height_0_subtile_0__pin_O_2_,
right_width_0_height_0_subtile_0__pin_O_3_,
bottom_width_0_height_0_subtile_0__pin_O_0_,
left_width_0_height_0_subtile_0__pin_O_1_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_4_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_I_8_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_1_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_5_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_I_9_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_2_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_I_6_;
//----- INPUT PORTS -----
input [0:0] bottom_width_0_height_0_subtile_0__pin_clk_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_I_3_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_I_7_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_O_2_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_O_3_;
//----- OUTPUT PORTS -----
output [0:0] bottom_width_0_height_0_subtile_0__pin_O_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_O_1_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.clb_I({top_width_0_height_0_subtile_0__pin_I_0_, right_width_0_height_0_subtile_0__pin_I_1_, bottom_width_0_height_0_subtile_0__pin_I_2_, left_width_0_height_0_subtile_0__pin_I_3_, top_width_0_height_0_subtile_0__pin_I_4_, right_width_0_height_0_subtile_0__pin_I_5_, bottom_width_0_height_0_subtile_0__pin_I_6_, left_width_0_height_0_subtile_0__pin_I_7_, top_width_0_height_0_subtile_0__pin_I_8_, right_width_0_height_0_subtile_0__pin_I_9_}),
.clb_clk(bottom_width_0_height_0_subtile_0__pin_clk_0_),
.ccff_head(ccff_head),
.clb_O({bottom_width_0_height_0_subtile_0__pin_O_0_, left_width_0_height_0_subtile_0__pin_O_1_, top_width_0_height_0_subtile_0__pin_O_2_, right_width_0_height_0_subtile_0__pin_O_3_}),
.ccff_tail(ccff_tail));
endmodule |
module grid_io_left(prog_clk,
gfpga_pad_GPIO_PAD,
right_width_0_height_0_subtile_0__pin_outpad_0_,
right_width_0_height_0_subtile_1__pin_outpad_0_,
right_width_0_height_0_subtile_2__pin_outpad_0_,
right_width_0_height_0_subtile_3__pin_outpad_0_,
right_width_0_height_0_subtile_4__pin_outpad_0_,
right_width_0_height_0_subtile_5__pin_outpad_0_,
right_width_0_height_0_subtile_6__pin_outpad_0_,
right_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
right_width_0_height_0_subtile_0__pin_inpad_0_,
right_width_0_height_0_subtile_1__pin_inpad_0_,
right_width_0_height_0_subtile_2__pin_inpad_0_,
right_width_0_height_0_subtile_3__pin_inpad_0_,
right_width_0_height_0_subtile_4__pin_inpad_0_,
right_width_0_height_0_subtile_5__pin_inpad_0_,
right_width_0_height_0_subtile_6__pin_inpad_0_,
right_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] right_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] right_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(right_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(right_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(right_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(right_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(right_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(right_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(right_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(right_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(right_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_clb_mode_clb_(prog_clk,
set,
reset,
clk,
clb_I,
clb_clk,
ccff_head,
clb_O,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:9] clb_I;
//----- INPUT PORTS -----
input [0:0] clb_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:3] clb_O;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:9] clb_I;
wire [0:0] clb_clk;
wire [0:3] clb_O;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] direct_interc_6_out;
wire [0:0] direct_interc_7_out;
wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_0_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_1_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_2_fle_out;
wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out;
wire [0:0] mux_tree_size14_0_out;
wire [0:3] mux_tree_size14_0_sram;
wire [0:3] mux_tree_size14_0_sram_inv;
wire [0:0] mux_tree_size14_10_out;
wire [0:3] mux_tree_size14_10_sram;
wire [0:3] mux_tree_size14_10_sram_inv;
wire [0:0] mux_tree_size14_11_out;
wire [0:3] mux_tree_size14_11_sram;
wire [0:3] mux_tree_size14_11_sram_inv;
wire [0:0] mux_tree_size14_12_out;
wire [0:3] mux_tree_size14_12_sram;
wire [0:3] mux_tree_size14_12_sram_inv;
wire [0:0] mux_tree_size14_13_out;
wire [0:3] mux_tree_size14_13_sram;
wire [0:3] mux_tree_size14_13_sram_inv;
wire [0:0] mux_tree_size14_14_out;
wire [0:3] mux_tree_size14_14_sram;
wire [0:3] mux_tree_size14_14_sram_inv;
wire [0:0] mux_tree_size14_15_out;
wire [0:3] mux_tree_size14_15_sram;
wire [0:3] mux_tree_size14_15_sram_inv;
wire [0:0] mux_tree_size14_1_out;
wire [0:3] mux_tree_size14_1_sram;
wire [0:3] mux_tree_size14_1_sram_inv;
wire [0:0] mux_tree_size14_2_out;
wire [0:3] mux_tree_size14_2_sram;
wire [0:3] mux_tree_size14_2_sram_inv;
wire [0:0] mux_tree_size14_3_out;
wire [0:3] mux_tree_size14_3_sram;
wire [0:3] mux_tree_size14_3_sram_inv;
wire [0:0] mux_tree_size14_4_out;
wire [0:3] mux_tree_size14_4_sram;
wire [0:3] mux_tree_size14_4_sram_inv;
wire [0:0] mux_tree_size14_5_out;
wire [0:3] mux_tree_size14_5_sram;
wire [0:3] mux_tree_size14_5_sram_inv;
wire [0:0] mux_tree_size14_6_out;
wire [0:3] mux_tree_size14_6_sram;
wire [0:3] mux_tree_size14_6_sram_inv;
wire [0:0] mux_tree_size14_7_out;
wire [0:3] mux_tree_size14_7_sram;
wire [0:3] mux_tree_size14_7_sram_inv;
wire [0:0] mux_tree_size14_8_out;
wire [0:3] mux_tree_size14_8_sram;
wire [0:3] mux_tree_size14_8_sram_inv;
wire [0:0] mux_tree_size14_9_out;
wire [0:3] mux_tree_size14_9_sram;
wire [0:3] mux_tree_size14_9_sram_inv;
wire [0:0] mux_tree_size14_mem_0_ccff_tail;
wire [0:0] mux_tree_size14_mem_10_ccff_tail;
wire [0:0] mux_tree_size14_mem_11_ccff_tail;
wire [0:0] mux_tree_size14_mem_12_ccff_tail;
wire [0:0] mux_tree_size14_mem_13_ccff_tail;
wire [0:0] mux_tree_size14_mem_14_ccff_tail;
wire [0:0] mux_tree_size14_mem_1_ccff_tail;
wire [0:0] mux_tree_size14_mem_2_ccff_tail;
wire [0:0] mux_tree_size14_mem_3_ccff_tail;
wire [0:0] mux_tree_size14_mem_4_ccff_tail;
wire [0:0] mux_tree_size14_mem_5_ccff_tail;
wire [0:0] mux_tree_size14_mem_6_ccff_tail;
wire [0:0] mux_tree_size14_mem_7_ccff_tail;
wire [0:0] mux_tree_size14_mem_8_ccff_tail;
wire [0:0] mux_tree_size14_mem_9_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_0 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_0_out, mux_tree_size14_1_out, mux_tree_size14_2_out, mux_tree_size14_3_out}),
.fle_clk(direct_interc_4_out),
.ccff_head(ccff_head),
.fle_out(logical_tile_clb_mode_default__fle_0_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_0_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_1 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_4_out, mux_tree_size14_5_out, mux_tree_size14_6_out, mux_tree_size14_7_out}),
.fle_clk(direct_interc_5_out),
.ccff_head(logical_tile_clb_mode_default__fle_0_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_1_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_1_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_2 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_8_out, mux_tree_size14_9_out, mux_tree_size14_10_out, mux_tree_size14_11_out}),
.fle_clk(direct_interc_6_out),
.ccff_head(logical_tile_clb_mode_default__fle_1_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_2_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_2_ccff_tail));
logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_3 (
.prog_clk(prog_clk),
.set(set),
.reset(reset),
.clk(clk),
.fle_in({mux_tree_size14_12_out, mux_tree_size14_13_out, mux_tree_size14_14_out, mux_tree_size14_15_out}),
.fle_clk(direct_interc_7_out),
.ccff_head(logical_tile_clb_mode_default__fle_2_ccff_tail),
.fle_out(logical_tile_clb_mode_default__fle_3_fle_out),
.ccff_tail(logical_tile_clb_mode_default__fle_3_ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_clb_mode_default__fle_0_fle_out),
.out(clb_O[0]));
direct_interc direct_interc_1_ (
.in(logical_tile_clb_mode_default__fle_1_fle_out),
.out(clb_O[1]));
direct_interc direct_interc_2_ (
.in(logical_tile_clb_mode_default__fle_2_fle_out),
.out(clb_O[2]));
direct_interc direct_interc_3_ (
.in(logical_tile_clb_mode_default__fle_3_fle_out),
.out(clb_O[3]));
direct_interc direct_interc_4_ (
.in(clb_clk),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(clb_clk),
.out(direct_interc_5_out));
direct_interc direct_interc_6_ (
.in(clb_clk),
.out(direct_interc_6_out));
direct_interc direct_interc_7_ (
.in(clb_clk),
.out(direct_interc_7_out));
mux_tree_size14 mux_fle_0_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_0_sram[0:3]),
.sram_inv(mux_tree_size14_0_sram_inv[0:3]),
.out(mux_tree_size14_0_out));
mux_tree_size14 mux_fle_0_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_1_sram[0:3]),
.sram_inv(mux_tree_size14_1_sram_inv[0:3]),
.out(mux_tree_size14_1_out));
mux_tree_size14 mux_fle_0_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_2_sram[0:3]),
.sram_inv(mux_tree_size14_2_sram_inv[0:3]),
.out(mux_tree_size14_2_out));
mux_tree_size14 mux_fle_0_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_3_sram[0:3]),
.sram_inv(mux_tree_size14_3_sram_inv[0:3]),
.out(mux_tree_size14_3_out));
mux_tree_size14 mux_fle_1_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_4_sram[0:3]),
.sram_inv(mux_tree_size14_4_sram_inv[0:3]),
.out(mux_tree_size14_4_out));
mux_tree_size14 mux_fle_1_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_5_sram[0:3]),
.sram_inv(mux_tree_size14_5_sram_inv[0:3]),
.out(mux_tree_size14_5_out));
mux_tree_size14 mux_fle_1_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_6_sram[0:3]),
.sram_inv(mux_tree_size14_6_sram_inv[0:3]),
.out(mux_tree_size14_6_out));
mux_tree_size14 mux_fle_1_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_7_sram[0:3]),
.sram_inv(mux_tree_size14_7_sram_inv[0:3]),
.out(mux_tree_size14_7_out));
mux_tree_size14 mux_fle_2_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_8_sram[0:3]),
.sram_inv(mux_tree_size14_8_sram_inv[0:3]),
.out(mux_tree_size14_8_out));
mux_tree_size14 mux_fle_2_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_9_sram[0:3]),
.sram_inv(mux_tree_size14_9_sram_inv[0:3]),
.out(mux_tree_size14_9_out));
mux_tree_size14 mux_fle_2_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_10_sram[0:3]),
.sram_inv(mux_tree_size14_10_sram_inv[0:3]),
.out(mux_tree_size14_10_out));
mux_tree_size14 mux_fle_2_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_11_sram[0:3]),
.sram_inv(mux_tree_size14_11_sram_inv[0:3]),
.out(mux_tree_size14_11_out));
mux_tree_size14 mux_fle_3_in_0 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_12_sram[0:3]),
.sram_inv(mux_tree_size14_12_sram_inv[0:3]),
.out(mux_tree_size14_12_out));
mux_tree_size14 mux_fle_3_in_1 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_13_sram[0:3]),
.sram_inv(mux_tree_size14_13_sram_inv[0:3]),
.out(mux_tree_size14_13_out));
mux_tree_size14 mux_fle_3_in_2 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_14_sram[0:3]),
.sram_inv(mux_tree_size14_14_sram_inv[0:3]),
.out(mux_tree_size14_14_out));
mux_tree_size14 mux_fle_3_in_3 (
.in({clb_I[0:9], logical_tile_clb_mode_default__fle_0_fle_out, logical_tile_clb_mode_default__fle_1_fle_out, logical_tile_clb_mode_default__fle_2_fle_out, logical_tile_clb_mode_default__fle_3_fle_out}),
.sram(mux_tree_size14_15_sram[0:3]),
.sram_inv(mux_tree_size14_15_sram_inv[0:3]),
.out(mux_tree_size14_15_out));
mux_tree_size14_mem mem_fle_0_in_0 (
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_3_ccff_tail),
.ccff_tail(mux_tree_size14_mem_0_ccff_tail),
.mem_out(mux_tree_size14_0_sram[0:3]),
.mem_outb(mux_tree_size14_0_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_0_ccff_tail),
.ccff_tail(mux_tree_size14_mem_1_ccff_tail),
.mem_out(mux_tree_size14_1_sram[0:3]),
.mem_outb(mux_tree_size14_1_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_1_ccff_tail),
.ccff_tail(mux_tree_size14_mem_2_ccff_tail),
.mem_out(mux_tree_size14_2_sram[0:3]),
.mem_outb(mux_tree_size14_2_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_0_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_2_ccff_tail),
.ccff_tail(mux_tree_size14_mem_3_ccff_tail),
.mem_out(mux_tree_size14_3_sram[0:3]),
.mem_outb(mux_tree_size14_3_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_3_ccff_tail),
.ccff_tail(mux_tree_size14_mem_4_ccff_tail),
.mem_out(mux_tree_size14_4_sram[0:3]),
.mem_outb(mux_tree_size14_4_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_4_ccff_tail),
.ccff_tail(mux_tree_size14_mem_5_ccff_tail),
.mem_out(mux_tree_size14_5_sram[0:3]),
.mem_outb(mux_tree_size14_5_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_5_ccff_tail),
.ccff_tail(mux_tree_size14_mem_6_ccff_tail),
.mem_out(mux_tree_size14_6_sram[0:3]),
.mem_outb(mux_tree_size14_6_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_1_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_6_ccff_tail),
.ccff_tail(mux_tree_size14_mem_7_ccff_tail),
.mem_out(mux_tree_size14_7_sram[0:3]),
.mem_outb(mux_tree_size14_7_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_7_ccff_tail),
.ccff_tail(mux_tree_size14_mem_8_ccff_tail),
.mem_out(mux_tree_size14_8_sram[0:3]),
.mem_outb(mux_tree_size14_8_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_8_ccff_tail),
.ccff_tail(mux_tree_size14_mem_9_ccff_tail),
.mem_out(mux_tree_size14_9_sram[0:3]),
.mem_outb(mux_tree_size14_9_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_9_ccff_tail),
.ccff_tail(mux_tree_size14_mem_10_ccff_tail),
.mem_out(mux_tree_size14_10_sram[0:3]),
.mem_outb(mux_tree_size14_10_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_2_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_10_ccff_tail),
.ccff_tail(mux_tree_size14_mem_11_ccff_tail),
.mem_out(mux_tree_size14_11_sram[0:3]),
.mem_outb(mux_tree_size14_11_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_0 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_11_ccff_tail),
.ccff_tail(mux_tree_size14_mem_12_ccff_tail),
.mem_out(mux_tree_size14_12_sram[0:3]),
.mem_outb(mux_tree_size14_12_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_1 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_12_ccff_tail),
.ccff_tail(mux_tree_size14_mem_13_ccff_tail),
.mem_out(mux_tree_size14_13_sram[0:3]),
.mem_outb(mux_tree_size14_13_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_2 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_13_ccff_tail),
.ccff_tail(mux_tree_size14_mem_14_ccff_tail),
.mem_out(mux_tree_size14_14_sram[0:3]),
.mem_outb(mux_tree_size14_14_sram_inv[0:3]));
mux_tree_size14_mem mem_fle_3_in_3 (
.prog_clk(prog_clk),
.ccff_head(mux_tree_size14_mem_14_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_size14_15_sram[0:3]),
.mem_outb(mux_tree_size14_15_sram_inv[0:3]));
endmodule |
module grid_io_right(prog_clk,
gfpga_pad_GPIO_PAD,
left_width_0_height_0_subtile_0__pin_outpad_0_,
left_width_0_height_0_subtile_1__pin_outpad_0_,
left_width_0_height_0_subtile_2__pin_outpad_0_,
left_width_0_height_0_subtile_3__pin_outpad_0_,
left_width_0_height_0_subtile_4__pin_outpad_0_,
left_width_0_height_0_subtile_5__pin_outpad_0_,
left_width_0_height_0_subtile_6__pin_outpad_0_,
left_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
left_width_0_height_0_subtile_0__pin_inpad_0_,
left_width_0_height_0_subtile_1__pin_inpad_0_,
left_width_0_height_0_subtile_2__pin_inpad_0_,
left_width_0_height_0_subtile_3__pin_inpad_0_,
left_width_0_height_0_subtile_4__pin_inpad_0_,
left_width_0_height_0_subtile_5__pin_inpad_0_,
left_width_0_height_0_subtile_6__pin_inpad_0_,
left_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] left_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] left_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(left_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(left_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(left_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(left_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(left_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(left_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(left_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(left_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(left_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(left_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_io_mode_io_(prog_clk,
gfpga_pad_GPIO_PAD,
io_outpad,
ccff_head,
io_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:0] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] io_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] io_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] io_outpad;
wire [0:0] io_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_1_out;
wire [0:0] logical_tile_io_mode_physical__iopad_0_iopad_inpad;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD),
.iopad_outpad(direct_interc_1_out),
.ccff_head(ccff_head),
.iopad_inpad(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.ccff_tail(ccff_tail));
direct_interc direct_interc_0_ (
.in(logical_tile_io_mode_physical__iopad_0_iopad_inpad),
.out(io_inpad));
direct_interc direct_interc_1_ (
.in(io_outpad),
.out(direct_interc_1_out));
endmodule |
module grid_io_bottom(prog_clk,
gfpga_pad_GPIO_PAD,
top_width_0_height_0_subtile_0__pin_outpad_0_,
top_width_0_height_0_subtile_1__pin_outpad_0_,
top_width_0_height_0_subtile_2__pin_outpad_0_,
top_width_0_height_0_subtile_3__pin_outpad_0_,
top_width_0_height_0_subtile_4__pin_outpad_0_,
top_width_0_height_0_subtile_5__pin_outpad_0_,
top_width_0_height_0_subtile_6__pin_outpad_0_,
top_width_0_height_0_subtile_7__pin_outpad_0_,
ccff_head,
top_width_0_height_0_subtile_0__pin_inpad_0_,
top_width_0_height_0_subtile_1__pin_inpad_0_,
top_width_0_height_0_subtile_2__pin_inpad_0_,
top_width_0_height_0_subtile_3__pin_inpad_0_,
top_width_0_height_0_subtile_4__pin_inpad_0_,
top_width_0_height_0_subtile_5__pin_inpad_0_,
top_width_0_height_0_subtile_6__pin_inpad_0_,
top_width_0_height_0_subtile_7__pin_inpad_0_,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:7] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_0__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_1__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_2__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_3__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_4__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_5__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_6__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] top_width_0_height_0_subtile_7__pin_outpad_0_;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_0__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_1__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_2__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_3__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_4__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_5__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_6__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] top_width_0_height_0_subtile_7__pin_inpad_0_;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] logical_tile_io_mode_io__0_ccff_tail;
wire [0:0] logical_tile_io_mode_io__1_ccff_tail;
wire [0:0] logical_tile_io_mode_io__2_ccff_tail;
wire [0:0] logical_tile_io_mode_io__3_ccff_tail;
wire [0:0] logical_tile_io_mode_io__4_ccff_tail;
wire [0:0] logical_tile_io_mode_io__5_ccff_tail;
wire [0:0] logical_tile_io_mode_io__6_ccff_tail;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[0]),
.io_outpad(top_width_0_height_0_subtile_0__pin_outpad_0_),
.ccff_head(ccff_head),
.io_inpad(top_width_0_height_0_subtile_0__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__0_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__1 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[1]),
.io_outpad(top_width_0_height_0_subtile_1__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__0_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_1__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__1_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__2 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[2]),
.io_outpad(top_width_0_height_0_subtile_2__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__1_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_2__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__2_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__3 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[3]),
.io_outpad(top_width_0_height_0_subtile_3__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__2_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_3__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__3_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__4 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[4]),
.io_outpad(top_width_0_height_0_subtile_4__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__3_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_4__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__4_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__5 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[5]),
.io_outpad(top_width_0_height_0_subtile_5__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__4_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_5__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__5_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__6 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[6]),
.io_outpad(top_width_0_height_0_subtile_6__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__5_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_6__pin_inpad_0_),
.ccff_tail(logical_tile_io_mode_io__6_ccff_tail));
logical_tile_io_mode_io_ logical_tile_io_mode_io__7 (
.prog_clk(prog_clk),
.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD[7]),
.io_outpad(top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(logical_tile_io_mode_io__6_ccff_tail),
.io_inpad(top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_tail(ccff_tail));
endmodule |
module logical_tile_io_mode_physical__iopad(prog_clk,
gfpga_pad_GPIO_PAD,
iopad_outpad,
ccff_head,
iopad_inpad,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GPIO PORTS -----
inout [0:0] gfpga_pad_GPIO_PAD;
//----- INPUT PORTS -----
input [0:0] iopad_outpad;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] iopad_inpad;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:0] iopad_outpad;
wire [0:0] iopad_inpad;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] GPIO_0_DIR;
wire [0:0] GPIO_DFF_mem_undriven_mem_outb;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
GPIO GPIO_0_ (
.PAD(gfpga_pad_GPIO_PAD),
.A(iopad_outpad),
.DIR(GPIO_0_DIR),
.Y(iopad_inpad));
GPIO_DFF_mem GPIO_DFF_mem (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(GPIO_0_DIR),
.mem_outb(GPIO_DFF_mem_undriven_mem_outb));
endmodule |
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4(prog_clk,
set,
reset,
clk,
ble4_in,
ble4_clk,
ccff_head,
ble4_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- GLOBAL PORTS -----
input [0:0] set;
//----- GLOBAL PORTS -----
input [0:0] reset;
//----- GLOBAL PORTS -----
input [0:0] clk;
//----- INPUT PORTS -----
input [0:3] ble4_in;
//----- INPUT PORTS -----
input [0:0] ble4_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ble4_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] ble4_in;
wire [0:0] ble4_clk;
wire [0:0] ble4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] direct_interc_0_out;
wire [0:0] direct_interc_1_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out;
wire [0:1] mux_tree_tapbuf_size2_0_sram;
wire [0:1] mux_tree_tapbuf_size2_0_sram_inv;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4 logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0 (
.prog_clk(prog_clk),
.lut4_in({direct_interc_0_out, direct_interc_1_out, direct_interc_2_out, direct_interc_3_out}),
.ccff_head(ccff_head),
.lut4_out(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail));
logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0 (
.set(set),
.reset(reset),
.clk(clk),
.ff_D(direct_interc_4_out),
.ff_Q(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q),
.ff_clk(direct_interc_5_out));
mux_tree_tapbuf_size2 mux_ble4_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff_0_ff_Q, logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out}),
.sram(mux_tree_tapbuf_size2_0_sram[0:1]),
.sram_inv(mux_tree_tapbuf_size2_0_sram_inv[0:1]),
.out(ble4_out));
mux_tree_tapbuf_size2_mem mem_ble4_out_0 (
.prog_clk(prog_clk),
.ccff_head(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_ccff_tail),
.ccff_tail(ccff_tail),
.mem_out(mux_tree_tapbuf_size2_0_sram[0:1]),
.mem_outb(mux_tree_tapbuf_size2_0_sram_inv[0:1]));
direct_interc direct_interc_0_ (
.in(ble4_in[0]),
.out(direct_interc_0_out));
direct_interc direct_interc_1_ (
.in(ble4_in[1]),
.out(direct_interc_1_out));
direct_interc direct_interc_2_ (
.in(ble4_in[2]),
.out(direct_interc_2_out));
direct_interc direct_interc_3_ (
.in(ble4_in[3]),
.out(direct_interc_3_out));
direct_interc direct_interc_4_ (
.in(logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4_0_lut4_out),
.out(direct_interc_4_out));
direct_interc direct_interc_5_ (
.in(ble4_clk),
.out(direct_interc_5_out));
endmodule |
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(prog_clk,
lut4_in,
ccff_head,
lut4_out,
ccff_tail);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:3] lut4_in;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] lut4_out;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- BEGIN wire-connection ports -----
wire [0:3] lut4_in;
wire [0:0] lut4_out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:15] lut4_0_sram;
wire [0:15] lut4_0_sram_inv;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
lut4 lut4_0_ (
.in(lut4_in[0:3]),
.sram(lut4_0_sram[0:15]),
.sram_inv(lut4_0_sram_inv[0:15]),
.out(lut4_out));
lut4_DFF_mem lut4_DFF_mem (
.prog_clk(prog_clk),
.ccff_head(ccff_head),
.ccff_tail(ccff_tail),
.mem_out(lut4_0_sram[0:15]),
.mem_outb(lut4_0_sram_inv[0:15]));
endmodule |
module direct_interc(in,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] in;
wire [0:0] out;
assign out[0] = in[0];
endmodule |
module mux_tree_tapbuf_size6_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:2] mem_out;
//----- OUTPUT PORTS -----
output [0:2] mem_outb;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[2];
// ----- END Local output short connections -----
DFF DFF_0_ (
.CK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]),
.QN(mem_outb[0]));
DFF DFF_1_ (
.CK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]),
.QN(mem_outb[1]));
DFF DFF_2_ (
.CK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]),
.QN(mem_outb[2]));
endmodule |
module mux_tree_tapbuf_size3_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:1] mem_out;
//----- OUTPUT PORTS -----
output [0:1] mem_outb;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[1];
// ----- END Local output short connections -----
DFF DFF_0_ (
.CK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]),
.QN(mem_outb[0]));
DFF DFF_1_ (
.CK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]),
.QN(mem_outb[1]));
endmodule |
module lut4_DFF_mem(prog_clk,
ccff_head,
ccff_tail,
mem_out,
mem_outb);
//----- GLOBAL PORTS -----
input [0:0] prog_clk;
//----- INPUT PORTS -----
input [0:0] ccff_head;
//----- OUTPUT PORTS -----
output [0:0] ccff_tail;
//----- OUTPUT PORTS -----
output [0:15] mem_out;
//----- OUTPUT PORTS -----
output [0:15] mem_outb;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
assign ccff_tail[0] = mem_out[15];
// ----- END Local output short connections -----
DFF DFF_0_ (
.CK(prog_clk),
.D(ccff_head),
.Q(mem_out[0]),
.QN(mem_outb[0]));
DFF DFF_1_ (
.CK(prog_clk),
.D(mem_out[0]),
.Q(mem_out[1]),
.QN(mem_outb[1]));
DFF DFF_2_ (
.CK(prog_clk),
.D(mem_out[1]),
.Q(mem_out[2]),
.QN(mem_outb[2]));
DFF DFF_3_ (
.CK(prog_clk),
.D(mem_out[2]),
.Q(mem_out[3]),
.QN(mem_outb[3]));
DFF DFF_4_ (
.CK(prog_clk),
.D(mem_out[3]),
.Q(mem_out[4]),
.QN(mem_outb[4]));
DFF DFF_5_ (
.CK(prog_clk),
.D(mem_out[4]),
.Q(mem_out[5]),
.QN(mem_outb[5]));
DFF DFF_6_ (
.CK(prog_clk),
.D(mem_out[5]),
.Q(mem_out[6]),
.QN(mem_outb[6]));
DFF DFF_7_ (
.CK(prog_clk),
.D(mem_out[6]),
.Q(mem_out[7]),
.QN(mem_outb[7]));
DFF DFF_8_ (
.CK(prog_clk),
.D(mem_out[7]),
.Q(mem_out[8]),
.QN(mem_outb[8]));
DFF DFF_9_ (
.CK(prog_clk),
.D(mem_out[8]),
.Q(mem_out[9]),
.QN(mem_outb[9]));
DFF DFF_10_ (
.CK(prog_clk),
.D(mem_out[9]),
.Q(mem_out[10]),
.QN(mem_outb[10]));
DFF DFF_11_ (
.CK(prog_clk),
.D(mem_out[10]),
.Q(mem_out[11]),
.QN(mem_outb[11]));
DFF DFF_12_ (
.CK(prog_clk),
.D(mem_out[11]),
.Q(mem_out[12]),
.QN(mem_outb[12]));
DFF DFF_13_ (
.CK(prog_clk),
.D(mem_out[12]),
.Q(mem_out[13]),
.QN(mem_outb[13]));
DFF DFF_14_ (
.CK(prog_clk),
.D(mem_out[13]),
.Q(mem_out[14]),
.QN(mem_outb[14]));
DFF DFF_15_ (
.CK(prog_clk),
.D(mem_out[14]),
.Q(mem_out[15]),
.QN(mem_outb[15]));
endmodule |
module lut4(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:15] sram;
//----- INPUT PORTS -----
input [0:15] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
wire [0:3] in;
wire [0:0] out;
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
buf4 buf4_0_ (
.in(in[0]),
.out(buf4_0_out));
buf4 buf4_1_ (
.in(in[1]),
.out(buf4_1_out));
buf4 buf4_2_ (
.in(in[2]),
.out(buf4_2_out));
buf4 buf4_3_ (
.in(in[3]),
.out(buf4_3_out));
lut4_mux lut4_mux_0_ (
.in(sram[0:15]),
.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
.out(out));
endmodule |
module mux_tree_tapbuf_basis_input2_mem1(in,
mem,
mem_inv,
out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:0] mem;
//----- INPUT PORTS -----
input [0:0] mem_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
TGATE TGATE_0_ (
.in(in[0]),
.sel(mem),
.selb(mem_inv),
.out(out));
TGATE TGATE_1_ (
.in(in[1]),
.sel(mem_inv),
.selb(mem),
.out(out));
endmodule |
module DFFSRQ(SET,
RST,
CK,
D,
Q);
//----- GLOBAL PORTS -----
input [0:0] SET;
//----- GLOBAL PORTS -----
input [0:0] RST;
//----- GLOBAL PORTS -----
input [0:0] CK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module DFF(CK,
D,
Q,
QN);
//----- GLOBAL PORTS -----
input [0:0] CK;
//----- INPUT PORTS -----
input [0:0] D;
//----- OUTPUT PORTS -----
output [0:0] Q;
//----- OUTPUT PORTS -----
output [0:0] QN;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module GPIO(PAD,
A,
DIR,
Y);
//----- GPIO PORTS -----
inout [0:0] PAD;
//----- INPUT PORTS -----
input [0:0] A;
//----- INPUT PORTS -----
input [0:0] DIR;
//----- OUTPUT PORTS -----
output [0:0] Y;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Internal logic should start here -----
// ----- Internal logic should end here -----
endmodule |
module mux_tree_tapbuf_size6(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:5] in;
//----- INPUT PORTS -----
input [0:2] sram;
//----- INPUT PORTS -----
input [0:2] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_4_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_5_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
INVTX1 INVTX1_4_ (
.in(in[4]),
.out(INVTX1_4_out));
INVTX1 INVTX1_5_ (
.in(in[5]),
.out(INVTX1_5_out));
const1 const1_0_ (
.const1(const1_0_const1));
tap_buf4 tap_buf4_0_ (
.in(mux_tree_tapbuf_basis_input2_mem1_5_out),
.out(out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ (
.in({INVTX1_2_out, INVTX1_3_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_2_ (
.in({INVTX1_4_out, INVTX1_5_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_3_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ (
.in({mux_tree_tapbuf_basis_input2_mem1_2_out, const1_0_const1}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_4_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_3_out, mux_tree_tapbuf_basis_input2_mem1_4_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(mux_tree_tapbuf_basis_input2_mem1_5_out));
endmodule |
module mux_tree_tapbuf_size4(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:3] in;
//----- INPUT PORTS -----
input [0:2] sram;
//----- INPUT PORTS -----
input [0:2] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_3_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
const1 const1_0_ (
.const1(const1_0_const1));
tap_buf4 tap_buf4_0_ (
.in(mux_tree_tapbuf_basis_input2_mem1_3_out),
.out(out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, INVTX1_2_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_1_ (
.in({INVTX1_3_out, const1_0_const1}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l3_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_1_out, mux_tree_tapbuf_basis_input2_mem1_2_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(mux_tree_tapbuf_basis_input2_mem1_3_out));
endmodule |
module mux_tree_tapbuf_size3(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:2] in;
//----- INPUT PORTS -----
input [0:1] sram;
//----- INPUT PORTS -----
input [0:1] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_2_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
const1 const1_0_ (
.const1(const1_0_const1));
tap_buf4 tap_buf4_0_ (
.in(mux_tree_tapbuf_basis_input2_mem1_2_out),
.out(out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_1_ (
.in({INVTX1_2_out, const1_0_const1}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, mux_tree_tapbuf_basis_input2_mem1_1_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_2_out));
endmodule |
module mux_tree_tapbuf_size2(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:1] in;
//----- INPUT PORTS -----
input [0:1] sram;
//----- INPUT PORTS -----
input [0:1] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_0_out;
wire [0:0] mux_tree_tapbuf_basis_input2_mem1_1_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
const1 const1_0_ (
.const1(const1_0_const1));
tap_buf4 tap_buf4_0_ (
.in(mux_tree_tapbuf_basis_input2_mem1_1_out),
.out(out));
mux_tree_tapbuf_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_tapbuf_basis_input2_mem1_0_out));
mux_tree_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
.in({mux_tree_tapbuf_basis_input2_mem1_0_out, const1_0_const1}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_tapbuf_basis_input2_mem1_1_out));
endmodule |
module mux_tree_size14(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:13] in;
//----- INPUT PORTS -----
input [0:3] sram;
//----- INPUT PORTS -----
input [0:3] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_10_out;
wire [0:0] INVTX1_11_out;
wire [0:0] INVTX1_12_out;
wire [0:0] INVTX1_13_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] INVTX1_6_out;
wire [0:0] INVTX1_7_out;
wire [0:0] INVTX1_8_out;
wire [0:0] INVTX1_9_out;
wire [0:0] const1_0_const1;
wire [0:0] mux_tree_basis_input2_mem1_0_out;
wire [0:0] mux_tree_basis_input2_mem1_10_out;
wire [0:0] mux_tree_basis_input2_mem1_11_out;
wire [0:0] mux_tree_basis_input2_mem1_12_out;
wire [0:0] mux_tree_basis_input2_mem1_13_out;
wire [0:0] mux_tree_basis_input2_mem1_1_out;
wire [0:0] mux_tree_basis_input2_mem1_2_out;
wire [0:0] mux_tree_basis_input2_mem1_3_out;
wire [0:0] mux_tree_basis_input2_mem1_4_out;
wire [0:0] mux_tree_basis_input2_mem1_5_out;
wire [0:0] mux_tree_basis_input2_mem1_6_out;
wire [0:0] mux_tree_basis_input2_mem1_7_out;
wire [0:0] mux_tree_basis_input2_mem1_8_out;
wire [0:0] mux_tree_basis_input2_mem1_9_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
INVTX1 INVTX1_4_ (
.in(in[4]),
.out(INVTX1_4_out));
INVTX1 INVTX1_5_ (
.in(in[5]),
.out(INVTX1_5_out));
INVTX1 INVTX1_6_ (
.in(in[6]),
.out(INVTX1_6_out));
INVTX1 INVTX1_7_ (
.in(in[7]),
.out(INVTX1_7_out));
INVTX1 INVTX1_8_ (
.in(in[8]),
.out(INVTX1_8_out));
INVTX1 INVTX1_9_ (
.in(in[9]),
.out(INVTX1_9_out));
INVTX1 INVTX1_10_ (
.in(in[10]),
.out(INVTX1_10_out));
INVTX1 INVTX1_11_ (
.in(in[11]),
.out(INVTX1_11_out));
INVTX1 INVTX1_12_ (
.in(in[12]),
.out(INVTX1_12_out));
INVTX1 INVTX1_13_ (
.in(in[13]),
.out(INVTX1_13_out));
INVTX1 INVTX1_14_ (
.in(mux_tree_basis_input2_mem1_13_out),
.out(out));
const1 const1_0_ (
.const1(const1_0_const1));
mux_tree_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_0_out));
mux_tree_basis_input2_mem1 mux_l1_in_1_ (
.in({INVTX1_2_out, INVTX1_3_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_1_out));
mux_tree_basis_input2_mem1 mux_l1_in_2_ (
.in({INVTX1_4_out, INVTX1_5_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_2_out));
mux_tree_basis_input2_mem1 mux_l1_in_3_ (
.in({INVTX1_6_out, INVTX1_7_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_3_out));
mux_tree_basis_input2_mem1 mux_l1_in_4_ (
.in({INVTX1_8_out, INVTX1_9_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_4_out));
mux_tree_basis_input2_mem1 mux_l1_in_5_ (
.in({INVTX1_10_out, INVTX1_11_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_5_out));
mux_tree_basis_input2_mem1 mux_l1_in_6_ (
.in({INVTX1_12_out, INVTX1_13_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(mux_tree_basis_input2_mem1_6_out));
mux_tree_basis_input2_mem1 mux_l2_in_0_ (
.in({mux_tree_basis_input2_mem1_0_out, mux_tree_basis_input2_mem1_1_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_basis_input2_mem1_7_out));
mux_tree_basis_input2_mem1 mux_l2_in_1_ (
.in({mux_tree_basis_input2_mem1_2_out, mux_tree_basis_input2_mem1_3_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_basis_input2_mem1_8_out));
mux_tree_basis_input2_mem1 mux_l2_in_2_ (
.in({mux_tree_basis_input2_mem1_4_out, mux_tree_basis_input2_mem1_5_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_basis_input2_mem1_9_out));
mux_tree_basis_input2_mem1 mux_l2_in_3_ (
.in({mux_tree_basis_input2_mem1_6_out, const1_0_const1}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(mux_tree_basis_input2_mem1_10_out));
mux_tree_basis_input2_mem1 mux_l3_in_0_ (
.in({mux_tree_basis_input2_mem1_7_out, mux_tree_basis_input2_mem1_8_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(mux_tree_basis_input2_mem1_11_out));
mux_tree_basis_input2_mem1 mux_l3_in_1_ (
.in({mux_tree_basis_input2_mem1_9_out, mux_tree_basis_input2_mem1_10_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(mux_tree_basis_input2_mem1_12_out));
mux_tree_basis_input2_mem1 mux_l4_in_0_ (
.in({mux_tree_basis_input2_mem1_11_out, mux_tree_basis_input2_mem1_12_out}),
.mem(sram[3]),
.mem_inv(sram_inv[3]),
.out(mux_tree_basis_input2_mem1_13_out));
endmodule |
module lut4_mux(in,
sram,
sram_inv,
out);
//----- INPUT PORTS -----
input [0:15] in;
//----- INPUT PORTS -----
input [0:3] sram;
//----- INPUT PORTS -----
input [0:3] sram_inv;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_10_out;
wire [0:0] INVTX1_11_out;
wire [0:0] INVTX1_12_out;
wire [0:0] INVTX1_13_out;
wire [0:0] INVTX1_14_out;
wire [0:0] INVTX1_15_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] INVTX1_4_out;
wire [0:0] INVTX1_5_out;
wire [0:0] INVTX1_6_out;
wire [0:0] INVTX1_7_out;
wire [0:0] INVTX1_8_out;
wire [0:0] INVTX1_9_out;
wire [0:0] lut4_mux_basis_input2_mem1_0_out;
wire [0:0] lut4_mux_basis_input2_mem1_10_out;
wire [0:0] lut4_mux_basis_input2_mem1_11_out;
wire [0:0] lut4_mux_basis_input2_mem1_12_out;
wire [0:0] lut4_mux_basis_input2_mem1_13_out;
wire [0:0] lut4_mux_basis_input2_mem1_14_out;
wire [0:0] lut4_mux_basis_input2_mem1_1_out;
wire [0:0] lut4_mux_basis_input2_mem1_2_out;
wire [0:0] lut4_mux_basis_input2_mem1_3_out;
wire [0:0] lut4_mux_basis_input2_mem1_4_out;
wire [0:0] lut4_mux_basis_input2_mem1_5_out;
wire [0:0] lut4_mux_basis_input2_mem1_6_out;
wire [0:0] lut4_mux_basis_input2_mem1_7_out;
wire [0:0] lut4_mux_basis_input2_mem1_8_out;
wire [0:0] lut4_mux_basis_input2_mem1_9_out;
// ----- BEGIN Local short connections -----
// ----- END Local short connections -----
// ----- BEGIN Local output short connections -----
// ----- END Local output short connections -----
INVTX1 INVTX1_0_ (
.in(in[0]),
.out(INVTX1_0_out));
INVTX1 INVTX1_1_ (
.in(in[1]),
.out(INVTX1_1_out));
INVTX1 INVTX1_2_ (
.in(in[2]),
.out(INVTX1_2_out));
INVTX1 INVTX1_3_ (
.in(in[3]),
.out(INVTX1_3_out));
INVTX1 INVTX1_4_ (
.in(in[4]),
.out(INVTX1_4_out));
INVTX1 INVTX1_5_ (
.in(in[5]),
.out(INVTX1_5_out));
INVTX1 INVTX1_6_ (
.in(in[6]),
.out(INVTX1_6_out));
INVTX1 INVTX1_7_ (
.in(in[7]),
.out(INVTX1_7_out));
INVTX1 INVTX1_8_ (
.in(in[8]),
.out(INVTX1_8_out));
INVTX1 INVTX1_9_ (
.in(in[9]),
.out(INVTX1_9_out));
INVTX1 INVTX1_10_ (
.in(in[10]),
.out(INVTX1_10_out));
INVTX1 INVTX1_11_ (
.in(in[11]),
.out(INVTX1_11_out));
INVTX1 INVTX1_12_ (
.in(in[12]),
.out(INVTX1_12_out));
INVTX1 INVTX1_13_ (
.in(in[13]),
.out(INVTX1_13_out));
INVTX1 INVTX1_14_ (
.in(in[14]),
.out(INVTX1_14_out));
INVTX1 INVTX1_15_ (
.in(in[15]),
.out(INVTX1_15_out));
INVTX1 INVTX1_16_ (
.in(lut4_mux_basis_input2_mem1_14_out),
.out(out));
lut4_mux_basis_input2_mem1 mux_l1_in_0_ (
.in({INVTX1_0_out, INVTX1_1_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_0_out));
lut4_mux_basis_input2_mem1 mux_l1_in_1_ (
.in({INVTX1_2_out, INVTX1_3_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_1_out));
lut4_mux_basis_input2_mem1 mux_l1_in_2_ (
.in({INVTX1_4_out, INVTX1_5_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_2_out));
lut4_mux_basis_input2_mem1 mux_l1_in_3_ (
.in({INVTX1_6_out, INVTX1_7_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_3_out));
lut4_mux_basis_input2_mem1 mux_l1_in_4_ (
.in({INVTX1_8_out, INVTX1_9_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_4_out));
lut4_mux_basis_input2_mem1 mux_l1_in_5_ (
.in({INVTX1_10_out, INVTX1_11_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_5_out));
lut4_mux_basis_input2_mem1 mux_l1_in_6_ (
.in({INVTX1_12_out, INVTX1_13_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_6_out));
lut4_mux_basis_input2_mem1 mux_l1_in_7_ (
.in({INVTX1_14_out, INVTX1_15_out}),
.mem(sram[0]),
.mem_inv(sram_inv[0]),
.out(lut4_mux_basis_input2_mem1_7_out));
lut4_mux_basis_input2_mem1 mux_l2_in_0_ (
.in({lut4_mux_basis_input2_mem1_0_out, lut4_mux_basis_input2_mem1_1_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(lut4_mux_basis_input2_mem1_8_out));
lut4_mux_basis_input2_mem1 mux_l2_in_1_ (
.in({lut4_mux_basis_input2_mem1_2_out, lut4_mux_basis_input2_mem1_3_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(lut4_mux_basis_input2_mem1_9_out));
lut4_mux_basis_input2_mem1 mux_l2_in_2_ (
.in({lut4_mux_basis_input2_mem1_4_out, lut4_mux_basis_input2_mem1_5_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(lut4_mux_basis_input2_mem1_10_out));
lut4_mux_basis_input2_mem1 mux_l2_in_3_ (
.in({lut4_mux_basis_input2_mem1_6_out, lut4_mux_basis_input2_mem1_7_out}),
.mem(sram[1]),
.mem_inv(sram_inv[1]),
.out(lut4_mux_basis_input2_mem1_11_out));
lut4_mux_basis_input2_mem1 mux_l3_in_0_ (
.in({lut4_mux_basis_input2_mem1_8_out, lut4_mux_basis_input2_mem1_9_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(lut4_mux_basis_input2_mem1_12_out));
lut4_mux_basis_input2_mem1 mux_l3_in_1_ (
.in({lut4_mux_basis_input2_mem1_10_out, lut4_mux_basis_input2_mem1_11_out}),
.mem(sram[2]),
.mem_inv(sram_inv[2]),
.out(lut4_mux_basis_input2_mem1_13_out));
lut4_mux_basis_input2_mem1 mux_l4_in_0_ (
.in({lut4_mux_basis_input2_mem1_12_out, lut4_mux_basis_input2_mem1_13_out}),
.mem(sram[3]),
.mem_inv(sram_inv[3]),
.out(lut4_mux_basis_input2_mem1_14_out));
endmodule |
module const0(const0);
//----- OUTPUT PORTS -----
output [0:0] const0;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
assign const0[0] = 1'b0;
endmodule |
module const1(const1);
//----- OUTPUT PORTS -----
output [0:0] const1;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
assign const1[0] = 1'b1;
endmodule |
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