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module button_state_decoder #
(
parameter CLK_HZ = 0
)
(
input wire clk,
input wire rstn,
input wire btn_in,
output wire btn_out_imm,
output wire btn_out_up,
output wire btn_out_down,
output wire btn_out_shrt,
output wire btn_out_long
);
localparam MS_DELAY = CLK_HZ / 1000;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [1:0] btn_in_pipe = 2'b00;
reg btn_shrt = 1'b0;
reg btn_long = 1'b0;
wire btn_imm = btn_in_pipe[1];
wire btn_up = btn_in_pipe[1] & ~btn_in_pipe[0];
wire btn_down = ~btn_in_pipe[1] & btn_in_pipe[0];
/*-------------------------------------------------------------------------------------------------------------------------------------*/
always @(posedge clk) begin
if (~rstn) begin
btn_in_pipe <= 2'b00;
end else begin
btn_in_pipe <= {btn_in_pipe[0], ~btn_in};
end
end
/*-------------------------------------------------------------------------------------------------------------------------------------*/
localparam [31:0] BTN_DEBOUNCE_VALUE = MS_DELAY * 20, // 20ms
BTN_SHORT_PRESS_VALUE = MS_DELAY * 50, // 50ms
BTN_LONG_PRESS_VALUE = MS_DELAY * 300; // 300ms
localparam ST_WAIT_PRESS = 1'b0,
ST_CALC_DURATION = 1'b1;
reg state = ST_WAIT_PRESS;
reg [31:0] btn_tc = {32{1'b0}};
always @(posedge clk) begin
if (~rstn) begin
btn_shrt <= 1'b0;
btn_long <= 1'b0;
state <= ST_WAIT_PRESS;
end else begin
case (state)
ST_WAIT_PRESS: begin
btn_shrt <= 1'b0;
btn_long <= 1'b0;
if (btn_down) begin
btn_tc <= 32'd0;
state <= ST_CALC_DURATION;
end
end
ST_CALC_DURATION: begin
if (btn_imm) begin
btn_tc <= btn_tc + 1'b1;
if (btn_tc > BTN_LONG_PRESS_VALUE) begin
btn_shrt <= 1'b0;
btn_long <= 1'b1;
state <= ST_WAIT_PRESS;
end
end else begin
state <= ST_WAIT_PRESS;
if (btn_tc > BTN_SHORT_PRESS_VALUE) begin
btn_shrt <= 1'b1;
btn_long <= 1'b0;
end
end
end
endcase
end
end
edge_to_pulse #
(
.CLK_HZ (CLK_HZ),
.PULSE_DURATION_MS (5),
.EDGE_TYPE ("RISING")
)
edge_to_pulse_bnt_up
(
.clk ( clk ),
.rstn ( rstn ),
.edge_in ( btn_up ),
.pulse_out ( btn_out_up )
);
edge_to_pulse #
(
.CLK_HZ (CLK_HZ),
.PULSE_DURATION_MS (5),
.EDGE_TYPE ("RISING")
)
edge_to_pulse_bnt_down
(
.clk ( clk ),
.rstn ( rstn ),
.edge_in ( btn_down ),
.pulse_out ( btn_out_down )
);
edge_to_pulse #
(
.CLK_HZ (CLK_HZ),
.PULSE_DURATION_MS (5),
.EDGE_TYPE ("RISING")
)
edge_to_pulse_bnt_shrt
(
.clk ( clk ),
.rstn ( rstn ),
.edge_in ( btn_shrt ),
.pulse_out ( btn_out_shrt )
);
edge_to_pulse #
(
.CLK_HZ (CLK_HZ),
.PULSE_DURATION_MS (5),
.EDGE_TYPE ("RISING")
)
edge_to_pulse_bnt_long
(
.clk ( clk ),
.rstn ( rstn ),
.edge_in ( btn_long ),
.pulse_out ( btn_out_long )
);
assign btn_out_imm = btn_imm;
endmodule |
module axis_palette_lut #
(
parameter integer COLOR_WIDTH = 16
)
(
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire axis_aresetn,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET axis_aresetn" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire axis_aclk,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) input wire [7:0] s_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input wire s_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output wire s_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TUSER" *) input wire s_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) output wire [COLOR_WIDTH - 1:0] m_axis_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output wire m_axis_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input wire m_axis_tready,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TUSER" *) output wire m_axis_tuser,
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME LUT_RAM, MEM_SIZE 1024, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1, READ_WRITE_MODE READ_WRITE" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM CLK" *) output wire lut_ram_clk,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM RST" *) output wire lut_ram_rst,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM EN " *) output wire lut_ram_ena,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM WE" *) output wire [3:0] lut_ram_we,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM ADDR" *) output wire [31:0] lut_ram_addr,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM DIN" *) output wire [31:0] lut_ram_wdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 LUT_RAM DOUT" *) input wire [31:0] lut_ram_rdata
);
localparam integer PIPE_DATA_IN_WIDTH = 8;
localparam integer PIPE_DATA_OUT_WIDTH = COLOR_WIDTH;
localparam integer PIPE_QUAL_WIDTH = 1;
localparam integer PIPE_STAGES = 1;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire pipe_cen;
wire [PIPE_DATA_IN_WIDTH - 1:0] pipe_in_data;
wire [PIPE_DATA_OUT_WIDTH - 1:0] pipe_out_data;
axis_pipeliner #
(
.PIPE_DATA_IN_WIDTH ( PIPE_DATA_IN_WIDTH ),
.PIPE_DATA_OUT_WIDTH( PIPE_DATA_OUT_WIDTH ),
.PIPE_QUAL_WIDTH ( PIPE_QUAL_WIDTH ),
.PIPE_STAGES ( PIPE_STAGES )
)
axis_pipeliner
(
.axis_aclk ( axis_aclk ),
.axis_aresetn ( axis_aresetn ),
.s_axis_tdata ( s_axis_tdata ),
.s_axis_tuser ( s_axis_tuser ),
.s_axis_tvalid ( s_axis_tvalid ),
.s_axis_tready ( s_axis_tready ),
.s_axis_tlast ( 1'b0 ),
.m_axis_tdata ( m_axis_tdata ),
.m_axis_tuser ( m_axis_tuser ),
.m_axis_tvalid ( m_axis_tvalid ),
.m_axis_tready ( m_axis_tready ),
.m_axis_tlast ( /*---NC---*/ ),
.pipe_cen ( pipe_cen ),
.pipe_in_data ( pipe_in_data ),
.pipe_out_data ( pipe_out_data )
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
assign lut_ram_clk = axis_aclk;
assign lut_ram_rst = 1'b0;
assign lut_ram_ena = pipe_cen;
assign lut_ram_we = 4'b0000;
assign lut_ram_addr = {{22{1'b0}}, pipe_in_data, {2{1'b0}}};
assign lut_ram_wdata = {32{1'b0}};
assign pipe_out_data = lut_ram_rdata[COLOR_WIDTH - 1:0];
endmodule |
module counter(input clk, input reset, input enable,
output [3:0] out);
wire clk, reset, enable;
reg [3:0] out;
always @ (posedge clk) begin
if (reset == 1'b1) begin
out <= 4'b0000;
end else if (enable == 1'b1) begin
out <= out + 1;
end
end
endmodule |
module counter_tb();
reg clk, reset, enable;
wire [3:0] counter1, counter2;
initial begin
$display("Time clk reset enable counter1 counter2");
$monitor("%g %b %b %b %b %b",
$time, clk, reset, enable, counter1, counter2);
clk = 1;
reset = 0;
enable = 0;
#5 reset = 1;
#10 reset = 0;
#5 enable = 1;
#100 enable = 0;
#10 $finish;
end
/* Clock generator */
always begin
#5 clk = ~clk;
end
counter counter_foo(clk, reset, enable, counter1);
counter counter_bar(clk, reset, enable, counter2);
endmodule |
module hello_world;
initial begin
$display("Hello world to where?");
$display("And this is hacked by simulator?");
end
endmodule |
module add4(input [3:0] a, input [3:0] b, output [3:0] c);
assign c = a & b;
endmodule |
module shift_n(input [7:0] in, output [7:0] out);
/*
* The parameter n feels like an argument passed down
* by caller. It truly is, but in a weird way.
*
* And we initialize to 2. GCC has an option to have compile
* error is n is not set before use. Does Verilog compiler
* has similar stuff?
*/
parameter n = 2;
assign out = (in << n);
endmodule |
module foo(input clk, input i1, input i2, input [15:0] i3,
output o1, output reg o2, output reg [7:0] o3);
wire [7:0] shift_in, shift_out;
wire foo_1, foo_2;
reg bar_1, bar_2;
/* Test parameterized module: pass n = 3 */
shift_n #(3) shift_foo(shift_in, shift_out);
/*
* {initial begin} is a one-time init function
* which will be executed at the very beginning.
* It feels like a constructor.
*/
initial begin
bar_1 = 1;
/*
* 1) Delayed assignment: wait 5 cycles before executing
* right-handle statement.
* 2) Intra-assignment delay: after executing right-handle
* statement, wait 5 cycles to assign the value to left-hand.
*
* Both are just used in simulation. Not for synthesis.
*/
#5 bar_1 = 0;
bar_1 = #5 1;
$display("Howdy");
$display("`AAA");
end
/*
* Blocking assignment:
* bar_2 will not be executed until bar_1 was assigned.
* This is like C code.
*/
always @ (posedge clk) begin
bar_1 = i1;
bar_2 = i2;
end
endmodule |
module led(input [3:0]sw, input [3:0]btn,
output [3:0]led, output [3:0]tri_led);
assign led = sw | btn;
assign tri_led = sw | btn;
endmodule |
module led_clk (
input board_clk,
input switch,
output reg [3:0] led);
reg [32:0] counter;
always @ (posedge board_clk)
begin
if (switch == 1'b1)
begin
counter <= counter + 1;
led[0] = counter[26];
end
end
endmodule |
module tri_mode_ethernet_mac_0_support_resets
(
input glbl_rstn,
input refclk,
input idelayctrl_ready,
output idelayctrl_reset_out);
wire glbl_rst;
wire idelayctrl_reset_in; // Used to trigger reset_sync generation in refclk domain.
wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL refclk domain.
reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse.
reg idelayctrl_reset;
assign glbl_rst = !glbl_rstn;
//----------------------------------------------------------------------------
// Reset circuitry associated with the IDELAYCTRL
//----------------------------------------------------------------------------
assign idelayctrl_reset_out = idelayctrl_reset;
assign idelayctrl_reset_in = glbl_rst || !idelayctrl_ready;
// Create a synchronous reset in the IDELAYCTRL refclk clock domain.
tri_mode_ethernet_mac_0_reset_sync idelayctrl_reset_gen (
.clk (refclk),
.enable (1'b1),
.reset_in (idelayctrl_reset_in),
.reset_out (idelayctrl_reset_sync)
);
// Reset circuitry for the IDELAYCTRL reset.
// The IDELAYCTRL must experience a pulse which is at least 50 ns in
// duration. This is ten clock cycles of the 200MHz refclk. Here we
// drive the reset pulse for 12 clock cycles.
always @(posedge refclk)
begin
if (idelayctrl_reset_sync) begin
idelay_reset_cnt <= 4'b0000;
idelayctrl_reset <= 1'b1;
end
else begin
case (idelay_reset_cnt)
4'b0000 : idelay_reset_cnt <= 4'b0001;
4'b0001 : idelay_reset_cnt <= 4'b0010;
4'b0010 : idelay_reset_cnt <= 4'b0011;
4'b0011 : idelay_reset_cnt <= 4'b0100;
4'b0100 : idelay_reset_cnt <= 4'b0101;
4'b0101 : idelay_reset_cnt <= 4'b0110;
4'b0110 : idelay_reset_cnt <= 4'b0111;
4'b0111 : idelay_reset_cnt <= 4'b1000;
4'b1000 : idelay_reset_cnt <= 4'b1001;
4'b1001 : idelay_reset_cnt <= 4'b1010;
4'b1010 : idelay_reset_cnt <= 4'b1011;
4'b1011 : idelay_reset_cnt <= 4'b1100;
default : idelay_reset_cnt <= 4'b1100;
endcase
if (idelay_reset_cnt == 4'b1100) begin
idelayctrl_reset <= 1'b0;
end
else begin
idelayctrl_reset <= 1'b1;
end
end
end
endmodule |
module tri_mode_ethernet_mac_0_example_design
(
// asynchronous reset
input glbl_rst,
/*
// 200MHz clock input from board
input clk_in_p,
input clk_in_n,
*/
// 100MHz clock input from board
input clk_in,
/*
* 125 MHz
* 100 MHz
* Generated Output clocks from MMCM
* We output these two to testbench.
* No needed for real hardware.
*/
//output gtx_clk_bufg_out,
//output s_axi_aclk_out,
/*
* 25 MHZ clock for PHY x1
* specific for arty a7 100 board
* Somehow the PHY does not have any clock input
* and we need to feed it.
*/
output mii_ref_clk_out,
output phy_resetn,
// MII Interface
//---------------
output [3:0] mii_txd,
output mii_tx_en,
//output mii_tx_er,
input [3:0] mii_rxd,
input mii_rx_dv,
input mii_rx_er,
input mii_rx_clk,
input mii_tx_clk,
// MDIO Interface
//---------------
inout mdio,
output mdc,
// Serialised statistics vectors
//------------------------------
output tx_statistics_s,
output rx_statistics_s,
// Serialised Pause interface controls
//------------------------------------
input pause_req_s,
// Main example design controls
//-----------------------------
input [1:0] mac_speed,
input update_speed,
//input serial_command, // tied to pause_req_s
input config_board,
output serial_response,
input gen_tx_data,
input chk_tx_data,
input reset_error,
output frame_error,
output activity_flash,
output user_LED,
/*
* I changed the original one. This one now indicate
* package generation activity.
*/
output activity_flash_gen,
/*
* I added this. This indicates if packet generation is enabled.
* It directly reflects gen_tx_data switch.
* It is now connected to LD3 blue light
*/
output pkt_gen_enabled
);
//----------------------------------------------------------------------------
// internal signals used in this top level wrapper.
//----------------------------------------------------------------------------
// example design clocks
wire gtx_clk_bufg;
wire s_axi_aclk;
wire mii_ref_clk;
wire rx_mac_aclk;
wire tx_mac_aclk;
// resets (and reset generation)
wire s_axi_resetn;
wire chk_resetn;
wire gtx_resetn;
wire rx_reset;
wire tx_reset;
wire dcm_locked;
wire glbl_rst_intn;
// USER side RX AXI-S interface
wire rx_fifo_clock;
wire rx_fifo_resetn;
wire [7:0] rx_axis_fifo_tdata;
wire rx_axis_fifo_tvalid;
wire rx_axis_fifo_tlast;
wire rx_axis_fifo_tready;
// USER side TX AXI-S interface
wire tx_fifo_clock;
wire tx_fifo_resetn;
wire [7:0] tx_axis_fifo_tdata;
wire tx_axis_fifo_tvalid;
wire tx_axis_fifo_tlast;
wire tx_axis_fifo_tready;
// RX Statistics serialisation signals
wire rx_statistics_valid;
reg rx_statistics_valid_reg;
wire [27:0] rx_statistics_vector;
reg [27:0] rx_stats;
reg [29:0] rx_stats_shift;
reg rx_stats_toggle = 0;
wire rx_stats_toggle_sync;
reg rx_stats_toggle_sync_reg = 0;
// TX Statistics serialisation signals
wire tx_statistics_valid;
reg tx_statistics_valid_reg;
wire [31:0] tx_statistics_vector;
reg [31:0] tx_stats;
reg [33:0] tx_stats_shift;
reg tx_stats_toggle = 0;
wire tx_stats_toggle_sync;
reg tx_stats_toggle_sync_reg = 0;
// Pause interface DESerialisation
reg [18:0] pause_shift;
reg pause_req;
reg [15:0] pause_val;
// AXI-Lite interface
wire [11:0] s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_awready;
wire [31:0] s_axi_wdata;
wire s_axi_wvalid;
wire s_axi_wready;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_bready;
wire [11:0] s_axi_araddr;
wire s_axi_arvalid;
wire s_axi_arready;
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rready;
wire int_frame_error;
wire int_activity_flash;
wire int_activity_flash_gen;
// set board defaults - only updated when reprogrammed
reg enable_address_swap = 1;
reg enable_phy_loopback = 0;
// signal tie offs
wire [7:0] tx_ifg_delay = 0; // not used in this example
assign activity_flash = int_activity_flash;
assign activity_flash_gen = int_activity_flash_gen;
wire mdio_i;
wire mdio_o;
wire mdio_t;
wire mii_tx_er;
//----------------------------------------------------------------------------
// Begin the logic description
//----------------------------------------------------------------------------
// want to infer an IOBUF on the mdio port
assign mdio = mdio_t ? 1'bz : mdio_o;
assign mdio_i = mdio;
assign frame_error = int_frame_error;
// when the config_board button is pushed capture and hold the
// state of the gne/chek tx_data inputs. These values will persist until the
// board is reprogrammed or config_board is pushed again
always @(posedge gtx_clk_bufg)
begin
if (config_board) begin
enable_address_swap <= gen_tx_data;
end
end
always @(posedge s_axi_aclk)
begin
if (config_board) begin
enable_phy_loopback <= chk_tx_data;
end
end
//----------------------------------------------------------------------------
// Clock logic to generate required clocks from the 200MHz on board
// if 125MHz is available directly this can be removed
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_example_design_clocks example_clocks
(
// differential clock inputs
//.clk_in_p (clk_in_p),
//.clk_in_n (clk_in_n),
.clk_in (clk_in),
// asynchronous control/resets
.glbl_rst (glbl_rst),
.dcm_locked (dcm_locked),
// clock outputs
.gtx_clk_bufg (gtx_clk_bufg),
.s_axi_aclk (s_axi_aclk),
.mii_ref_clk (mii_ref_clk)
);
/*
* Pass the GTX clock to the Test Bench
* Not needed for real hardware
*/
//assign gtx_clk_bufg_out = gtx_clk_bufg;
//assign s_axi_aclk_out = s_axi_aclk;
assign mii_ref_clk_out = mii_ref_clk;
//----------------------------------------------------------------------------
// Generate the user side clocks for the axi fifos
//----------------------------------------------------------------------------
assign tx_fifo_clock = gtx_clk_bufg;
assign rx_fifo_clock = gtx_clk_bufg;
//----------------------------------------------------------------------------
// Generate resets required for the fifo side signals etc
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_example_design_resets example_resets
(
// clocks
.s_axi_aclk (s_axi_aclk),
.gtx_clk (gtx_clk_bufg),
// asynchronous resets
.glbl_rst (glbl_rst),
.reset_error (reset_error),
.rx_reset (rx_reset),
.tx_reset (tx_reset),
.dcm_locked (dcm_locked),
// synchronous reset outputs
.glbl_rst_intn (glbl_rst_intn),
.gtx_resetn (gtx_resetn),
.s_axi_resetn (s_axi_resetn),
.phy_resetn (phy_resetn),
.chk_resetn (chk_resetn)
);
// generate the user side resets for the axi fifos
assign tx_fifo_resetn = gtx_resetn;
assign rx_fifo_resetn = gtx_resetn;
//----------------------------------------------------------------------------
// Serialize the stats vectors
// This is a single bit approach, retimed onto gtx_clk
// this code is only present to prevent code being stripped..
//----------------------------------------------------------------------------
// RX STATS
// first capture the stats on the appropriate clock
always @(posedge rx_mac_aclk)
begin
rx_statistics_valid_reg <= rx_statistics_valid;
if (!rx_statistics_valid_reg & rx_statistics_valid) begin
rx_stats <= rx_statistics_vector;
rx_stats_toggle <= !rx_stats_toggle;
end
end
tri_mode_ethernet_mac_0_sync_block rx_stats_sync (
.clk (gtx_clk_bufg),
.data_in (rx_stats_toggle),
.data_out (rx_stats_toggle_sync)
);
always @(posedge gtx_clk_bufg)
begin
rx_stats_toggle_sync_reg <= rx_stats_toggle_sync;
end
// when an update is rxd load shifter (plus start/stop bit)
// shifter always runs (no power concerns as this is an example design)
always @(posedge gtx_clk_bufg)
begin
if (rx_stats_toggle_sync_reg != rx_stats_toggle_sync) begin
rx_stats_shift <= {1'b1, rx_stats, 1'b1};
end
else begin
rx_stats_shift <= {rx_stats_shift[28:0], 1'b0};
end
end
assign rx_statistics_s = rx_stats_shift[29];
// TX STATS
// first capture the stats on the appropriate clock
always @(posedge tx_mac_aclk)
begin
tx_statistics_valid_reg <= tx_statistics_valid;
if (!tx_statistics_valid_reg & tx_statistics_valid) begin
tx_stats <= tx_statistics_vector;
tx_stats_toggle <= !tx_stats_toggle;
end
end
tri_mode_ethernet_mac_0_sync_block tx_stats_sync (
.clk (gtx_clk_bufg),
.data_in (tx_stats_toggle),
.data_out (tx_stats_toggle_sync)
);
always @(posedge gtx_clk_bufg)
begin
tx_stats_toggle_sync_reg <= tx_stats_toggle_sync;
end
// when an update is txd load shifter (plus start bit)
// shifter always runs (no power concerns as this is an example design)
always @(posedge gtx_clk_bufg)
begin
if (tx_stats_toggle_sync_reg != tx_stats_toggle_sync) begin
tx_stats_shift <= {1'b1, tx_stats, 1'b1};
end
else begin
tx_stats_shift <= {tx_stats_shift[32:0], 1'b0};
end
end
assign tx_statistics_s = tx_stats_shift[33];
//----------------------------------------------------------------------------
// DSerialize the Pause interface
// This is a single bit approachtimed on gtx_clk
// this code is only present to prevent code being stripped..
//----------------------------------------------------------------------------
// the serialised pause info has a start bit followed by the quanta and a stop bit
// capture the quanta when the start bit hits the msb and the stop bit is in the lsb
always @(posedge gtx_clk_bufg)
begin
pause_shift <= {pause_shift[17:0], pause_req_s};
end
always @(posedge gtx_clk_bufg)
begin
if (pause_shift[18] == 1'b0 & pause_shift[17] == 1'b1 & pause_shift[0] == 1'b1) begin
pause_req <= 1'b1;
pause_val <= pause_shift[16:1];
end
else begin
pause_req <= 1'b0;
pause_val <= 0;
end
end
//----------------------------------------------------------------------------
// Instantiate the AXI-LITE Controller
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_axi_lite_sm axi_lite_controller (
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.mac_speed (mac_speed),
.update_speed (update_speed), // may need glitch protection on this..
.serial_command (pause_req_s),
.serial_response (serial_response),
.phy_loopback (enable_phy_loopback),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready)
);
//----------------------------------------------------------------------------
// Instantiate the TRIMAC core fifo block wrapper
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_fifo_block trimac_fifo_block (
.gtx_clk (gtx_clk_bufg),
// asynchronous reset
.glbl_rstn (glbl_rst_intn),
.rx_axi_rstn (1'b1),
.tx_axi_rstn (1'b1),
// Receiver Statistics Interface
//---------------------------------------
.rx_mac_aclk (rx_mac_aclk),
.rx_reset (rx_reset),
.rx_statistics_vector (rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid),
// Receiver (AXI-S) Interface
//----------------------------------------
.rx_fifo_clock (rx_fifo_clock),
.rx_fifo_resetn (rx_fifo_resetn),
.rx_axis_fifo_tdata (rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid),
.rx_axis_fifo_tready (rx_axis_fifo_tready),
.rx_axis_fifo_tlast (rx_axis_fifo_tlast),
// Transmitter Statistics Interface
//------------------------------------------
.tx_mac_aclk (tx_mac_aclk),
.tx_reset (tx_reset),
.tx_ifg_delay (tx_ifg_delay),
.tx_statistics_vector (tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid),
// Transmitter (AXI-S) Interface
//-------------------------------------------
.tx_fifo_clock (tx_fifo_clock),
.tx_fifo_resetn (tx_fifo_resetn),
.tx_axis_fifo_tdata (tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid),
.tx_axis_fifo_tready (tx_axis_fifo_tready),
.tx_axis_fifo_tlast (tx_axis_fifo_tlast),
// MAC Control Interface
//------------------------
.pause_req (pause_req),
.pause_val (pause_val),
// MII Interface
//---------------
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rx_clk (mii_rx_clk),
.mii_tx_clk (mii_tx_clk),
// MDIO Interface
//---------------
.mdc (mdc),
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
// AXI-Lite Interface
//---------------
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.user_LED (user_LED)
);
//----------------------------------------------------------------------------
// Instantiate the address swapping module and simple pattern generator
//----------------------------------------------------------------------------
/*
tri_mode_ethernet_mac_0_basic_pat_gen basic_pat_gen_inst (
.axi_tclk (tx_fifo_clock),
.axi_tresetn (tx_fifo_resetn),
.check_resetn (chk_resetn),
.enable_pat_gen (gen_tx_data),
.enable_pat_chk (chk_tx_data),
.enable_address_swap (enable_address_swap),
.speed (mac_speed),
.rx_axis_tdata (rx_axis_fifo_tdata),
.rx_axis_tvalid (rx_axis_fifo_tvalid),
.rx_axis_tlast (rx_axis_fifo_tlast),
.rx_axis_tuser (1'b0), // the FIFO drops all bad frames
.rx_axis_tready (rx_axis_fifo_tready),
.tx_axis_tdata (tx_axis_fifo_tdata),
.tx_axis_tvalid (tx_axis_fifo_tvalid),
.tx_axis_tlast (tx_axis_fifo_tlast),
.tx_axis_tready (tx_axis_fifo_tready),
.frame_error (int_frame_error),
.activity_flash (int_activity_flash),
.activity_flash_gen (int_activity_flash_gen),
.pkt_gen_enabled (pkt_gen_enabled)
);
*/
/*
* This is our own HLS-based loopback
* Checkout hls_loopback
*/
top_func_0 loopback (
/*
* Input from FIFO
*/
.input_r_TVALID(rx_axis_fifo_tvalid), // input wire input_r_TVALID
.input_r_TREADY(rx_axis_fifo_tready), // output wire input_r_TREADY
.input_r_TDATA(rx_axis_fifo_tdata), // input wire [31 : 0] input_r_TDATA
.input_r_TLAST(rx_axis_fifo_tlast), // input wire [0 : 0] input_r_TLAST
/*
* Output to FIFO
*/
.output_r_TVALID(tx_axis_fifo_tvalid), // output wire output_r_TVALID
.output_r_TREADY(tx_axis_fifo_tready), // input wire output_r_TREADY
.output_r_TDATA(tx_axis_fifo_tdata), // output wire [31 : 0] output_r_TDATA
.output_r_TLAST(tx_axis_fifo_tlast), // output wire [0 : 0] output_r_TLAST
.ap_clk(tx_fifo_clock), // input wire ap_clk
.ap_rst_n(tx_fifo_resetn) // input wire ap_rst_n
);
endmodule |
module tri_mode_ethernet_mac_0_example_design_clocks
(
// differential clock inputs
//input clk_in_p,
//input clk_in_n,
input clk_in,
// asynchronous control/resets
input glbl_rst,
output dcm_locked,
// clock outputs
output gtx_clk_bufg,
output s_axi_aclk,
// 25MHz for PHY
output mii_ref_clk
);
wire clkin1;
wire mmcm_rst;
wire clkin1_bufg;
wire dcm_locked_int;
wire dcm_locked_sync;
reg dcm_locked_reg = 1;
reg dcm_locked_edge = 1;
/*
// No need for manual buffering
// arty a7 is using single-ended clock
// Input buffering
//------------------------------------
IBUFDS clkin1_buf
(.O (clkin1),
.I (clk_in_p),
.IB (clk_in_n));
*/
assign clkin1 = clk_in;
// route clkin1 through a BUFGCE for the MMCM reset generation logic
BUFGCE bufg_clkin1 (.I(clkin1), .CE (1'b1), .O(clkin1_bufg));
// detect a falling edge on dcm_locked (after resyncing to this domain)
tri_mode_ethernet_mac_0_sync_block lock_sync (
.clk (clkin1_bufg),
.data_in (dcm_locked_int),
.data_out (dcm_locked_sync)
);
// for the falling edge detect we want to force this at power on so init the flop to 1
always @(posedge clkin1_bufg)
begin
dcm_locked_reg <= dcm_locked_sync;
dcm_locked_edge <= dcm_locked_reg & !dcm_locked_sync;
end
// the MMCM reset should be at least 5ns - that is one cycle of the input clock -
// since the source of the input reset is unknown (a push switch in board design)
// this needs to be debounced
tri_mode_ethernet_mac_0_reset_sync mmcm_reset_gen (
.clk (clkin1_bufg),
.enable (1'b1),
.reset_in (glbl_rst | dcm_locked_edge),
.reset_out (mmcm_rst)
);
//----------------------------------------------------------------------------
// Generate clocks using the clock wizard
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_clk_wiz clock_generator
(
// 100MHz Clock in ports
.CLK_IN1 (clkin1),
// Clock out ports
.CLK_OUT1 (gtx_clk_bufg),
.CLK_OUT2 (s_axi_aclk),
.CLK_OUT3 (mii_ref_clk),
// Status and control signals
.RESET (mmcm_rst),
.LOCKED (dcm_locked_int)
);
assign dcm_locked = dcm_locked_int;
endmodule |
module tri_mode_ethernet_mac_0_support
(
input gtx_clk,
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
// Receiver Interface
//--------------------------
output rx_enable,
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
output rx_mac_aclk,
output rx_reset,
output [7:0] rx_axis_mac_tdata,
output rx_axis_mac_tvalid,
output rx_axis_mac_tlast,
output rx_axis_mac_tuser,
// Transmitter Interface
//-----------------------------
output tx_enable,
input [7:0] tx_ifg_delay,
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
output tx_mac_aclk,
output tx_reset,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
input tx_axis_mac_tuser,
output tx_axis_mac_tready,
// MAC Control Interface
//----------------------
input pause_req,
input [15:0] pause_val,
output speedis100,
output speedis10100,
// MII Interface
//---------------
output [3:0] mii_txd,
output mii_tx_en,
output mii_tx_er,
input [3:0] mii_rxd,
input mii_rx_dv,
input mii_rx_er,
input mii_rx_clk,
input mii_tx_clk,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
// AXI-Lite Interface
//---------------
input s_axi_aclk,
input s_axi_resetn,
input [11:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [11:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
output mac_irq
);
//---------------------------------------------------------------------------
// Instantiate the TEMAC core
//---------------------------------------------------------------------------
tri_mode_ethernet_mac_0 tri_mode_ethernet_mac_i (
.gtx_clk (gtx_clk),
// asynchronous reset
.glbl_rstn (glbl_rstn),
.rx_axi_rstn (rx_axi_rstn),
.tx_axi_rstn (tx_axi_rstn),
// Receiver Interface
//--------------------------
.rx_enable (rx_enable),
.rx_statistics_vector (rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid),
.rx_mac_aclk (rx_mac_aclk),
.rx_reset (rx_reset),
.rx_axis_mac_tdata (rx_axis_mac_tdata),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid),
.rx_axis_mac_tlast (rx_axis_mac_tlast),
.rx_axis_mac_tuser (rx_axis_mac_tuser),
// Transmitter Interface
//-----------------------------
.tx_enable (tx_enable),
.tx_ifg_delay (tx_ifg_delay),
.tx_statistics_vector (tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid),
.tx_mac_aclk (tx_mac_aclk),
.tx_reset (tx_reset),
.tx_axis_mac_tdata (tx_axis_mac_tdata),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid),
.tx_axis_mac_tlast (tx_axis_mac_tlast),
.tx_axis_mac_tuser (tx_axis_mac_tuser),
.tx_axis_mac_tready (tx_axis_mac_tready),
// MAC Control Interface
//----------------------
.pause_req (pause_req),
.pause_val (pause_val),
.speedis100 (speedis100),
.speedis10100 (speedis10100),
// MII Interface
//---------------
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rx_clk (mii_rx_clk),
.mii_tx_clk (mii_tx_clk),
// MDIO Interface
//---------------
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
.mdc (mdc),
// AXI-Lite Interface
//---------------
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.mac_irq (mac_irq)
);
endmodule |
module tri_mode_ethernet_mac_0_fifo_block (
input gtx_clk,
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
// Receiver Statistics Interface
//---------------------------------------
output rx_mac_aclk,
output rx_reset,
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
// Receiver (AXI-S) Interface
//----------------------------------------
input rx_fifo_clock,
input rx_fifo_resetn,
output [7:0] rx_axis_fifo_tdata,
output rx_axis_fifo_tvalid,
input rx_axis_fifo_tready,
output rx_axis_fifo_tlast,
// Transmitter Statistics Interface
//------------------------------------------
output tx_mac_aclk,
output tx_reset,
input [7:0] tx_ifg_delay,
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
// Transmitter (AXI-S) Interface
//-------------------------------------------
input tx_fifo_clock,
input tx_fifo_resetn,
input [7:0] tx_axis_fifo_tdata,
input tx_axis_fifo_tvalid,
output tx_axis_fifo_tready,
input tx_axis_fifo_tlast,
// MAC Control Interface
//------------------------
input pause_req,
input [15:0] pause_val,
// MII Interface
//---------------
output [3:0] mii_txd,
output mii_tx_en,
output mii_tx_er,
input [3:0] mii_rxd,
input mii_rx_dv,
input mii_rx_er,
input mii_rx_clk,
input mii_tx_clk,
// MDIO Interface
//---------------
input mdio_i,
output mdio_o,
output mdio_t,
output mdc,
// AXI-Lite Interface
//---------------
input s_axi_aclk,
input s_axi_resetn,
input [11:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [11:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rvalid,
input s_axi_rready,
output user_LED
);
//----------------------------------------------------------------------------
// Internal signals used in this fifo block level wrapper.
//----------------------------------------------------------------------------
wire rx_mac_aclk_int; // MAC Rx clock
wire tx_mac_aclk_int; // MAC Tx clock
wire rx_reset_int; // MAC Rx reset
wire tx_reset_int; // MAC Tx reset
// MAC receiver client I/F
wire [7:0] rx_axis_mac_tdata;
wire rx_axis_mac_tvalid;
wire rx_axis_mac_tlast;
wire rx_axis_mac_tuser;
// MAC transmitter client I/F
wire [7:0] tx_axis_mac_tdata;
wire tx_axis_mac_tvalid;
wire tx_axis_mac_tready;
wire tx_axis_mac_tlast;
wire tx_axis_mac_tuser;
//----------------------------------------------------------------------------
// Connect the output clock signals
//----------------------------------------------------------------------------
assign rx_mac_aclk = rx_mac_aclk_int;
assign tx_mac_aclk = tx_mac_aclk_int;
assign rx_reset = rx_reset_int;
assign tx_reset = tx_reset_int;
//----------------------------------------------------------------------------
// Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_support trimac_sup_block (
.gtx_clk (gtx_clk),
// asynchronous reset
.glbl_rstn (glbl_rstn),
.rx_axi_rstn (rx_axi_rstn),
.tx_axi_rstn (tx_axi_rstn),
// Receiver Interface
.rx_enable (),
.rx_statistics_vector (rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid),
.rx_mac_aclk (rx_mac_aclk_int),
.rx_reset (rx_reset_int),
.rx_axis_mac_tdata (rx_axis_mac_tdata),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid),
.rx_axis_mac_tlast (rx_axis_mac_tlast),
.rx_axis_mac_tuser (rx_axis_mac_tuser),
// Transmitter Interface
.tx_enable (),
.tx_ifg_delay (tx_ifg_delay),
.tx_statistics_vector (tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid),
.tx_mac_aclk (tx_mac_aclk_int),
.tx_reset (tx_reset_int),
.tx_axis_mac_tdata (tx_axis_mac_tdata ),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid),
.tx_axis_mac_tlast (tx_axis_mac_tlast),
.tx_axis_mac_tuser (tx_axis_mac_tuser ),
.tx_axis_mac_tready (tx_axis_mac_tready),
// Flow Control
.pause_req (pause_req),
.pause_val (pause_val),
// Speed Control
.speedis100 (),
.speedis10100 (),
// MII Interface
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rx_clk (mii_rx_clk),
.mii_tx_clk (mii_tx_clk),
// MDIO Interface
//---------------
.mdc (mdc),
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
// AXI lite interface
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.mac_irq ()
);
//----------------------------------------------------------------------------
// Instantiate the user side FIFO
//----------------------------------------------------------------------------
// locally reset sync the mac generated resets - the resets are already fully sync
// so adding a reset sync shouldn't change that
tri_mode_ethernet_mac_0_reset_sync rx_mac_reset_gen (
.clk (rx_mac_aclk_int),
.enable (1'b1),
.reset_in (rx_reset_int),
.reset_out (rx_mac_reset)
);
tri_mode_ethernet_mac_0_reset_sync tx_mac_reset_gen (
.clk (tx_mac_aclk_int),
.enable (1'b1),
.reset_in (tx_reset_int),
.reset_out (tx_mac_reset)
);
// create inverted mac resets as the FIFO expects AXI compliant resets
assign tx_mac_resetn = !tx_mac_reset;
assign rx_mac_resetn = !rx_mac_reset;
tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo #
(
.FULL_DUPLEX_ONLY (1)
)
user_side_FIFO
(
// Transmit FIFO MAC TX Interface
.tx_fifo_aclk (tx_fifo_clock),
.tx_fifo_resetn (tx_fifo_resetn),
.tx_axis_fifo_tdata (tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid),
.tx_axis_fifo_tlast (tx_axis_fifo_tlast),
.tx_axis_fifo_tready (tx_axis_fifo_tready),
.tx_mac_aclk (tx_mac_aclk_int),
.tx_mac_resetn (tx_mac_resetn),
.tx_axis_mac_tdata (tx_axis_mac_tdata),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid),
.tx_axis_mac_tlast (tx_axis_mac_tlast),
.tx_axis_mac_tready (tx_axis_mac_tready),
.tx_axis_mac_tuser (tx_axis_mac_tuser),
.tx_fifo_overflow (),
.tx_fifo_status (),
.tx_collision (1'b0),
.tx_retransmit (1'b0),
.rx_fifo_aclk (rx_fifo_clock),
.rx_fifo_resetn (rx_fifo_resetn),
.rx_axis_fifo_tdata (rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid),
.rx_axis_fifo_tlast (rx_axis_fifo_tlast),
.rx_axis_fifo_tready (rx_axis_fifo_tready),
.rx_mac_aclk (rx_mac_aclk_int),
.rx_mac_resetn (rx_mac_resetn),
.rx_axis_mac_tdata (rx_axis_mac_tdata),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid),
.rx_axis_mac_tlast (rx_axis_mac_tlast),
.rx_axis_mac_tuser (rx_axis_mac_tuser),
.rx_fifo_status (),
.rx_fifo_overflow (),
.user_LED (user_LED)
);
endmodule |
module tri_mode_ethernet_mac_0_axi_lite_sm (
input s_axi_aclk,
input s_axi_resetn,
input [1:0] mac_speed,
input update_speed,
input serial_command,
output serial_response,
input phy_loopback,
output reg [11:0] s_axi_awaddr = 0,
output reg s_axi_awvalid = 0,
input s_axi_awready,
output reg [31:0] s_axi_wdata = 0,
output reg s_axi_wvalid = 0,
input s_axi_wready,
input [1:0] s_axi_bresp,
input s_axi_bvalid,
output reg s_axi_bready = 0,
output reg [11:0] s_axi_araddr = 0,
output reg s_axi_arvalid = 0,
input s_axi_arready,
input [31:0] s_axi_rdata,
input [1:0] s_axi_rresp,
input s_axi_rvalid,
output reg s_axi_rready = 0
);
// main state machine
localparam STARTUP = 0,
UPDATE_SPEED = 1,
MDIO_RD = 2,
MDIO_POLL_CHECK = 3,
MDIO_1G = 4,
MDIO_10_100 = 5,
MDIO_RESTART = 12,
MDIO_LOOPBACK = 13,
MDIO_STATS = 14,
MDIO_STATS_POLL_CHECK = 15,
RESET_MAC_TX = 16,
RESET_MAC_RX = 17,
CNFG_MDIO = 18,
CNFG_FLOW = 19,
CNFG_FILTER = 22,
CNFG_LO_ADDR = 20,
CNFG_HI_ADDR = 21,
CHECK_SPEED = 25;
// MDIO State machine
localparam IDLE = 0,
SET_DATA = 1,
INIT = 2,
POLL = 3;
// AXI State Machine
localparam READ = 1,
WRITE = 2,
DONE = 3;
// Management configuration register address (0x500)
localparam CONFIG_MANAGEMENT_ADD = 17'h500;
// Flow control configuration register address (0x40C)
localparam CONFIG_FLOW_CTRL_ADD = 17'h40C;
// Receiver configuration register address (0x404)
localparam RECEIVER_ADD = 17'h404;
// Transmitter configuration register address (0x408)
localparam TRANSMITTER_ADD = 17'h408;
// Speed configuration register address (0x410)
localparam SPEED_CONFIG_ADD = 17'h410;
// Unicast Word 0 configuration register address (0x700)
localparam CONFIG_UNI0_CTRL_ADD = 17'h700;
// Unicast Word 1 configuration register address (0x704)
localparam CONFIG_UNI1_CTRL_ADD = 17'h704;
// Address Filter configuration register address (0x708)
localparam CONFIG_ADDR_CTRL_ADD = 17'h708;
// MDIO registers
localparam MDIO_CONTROL = 17'h504;
localparam MDIO_TX_DATA = 17'h508;
localparam MDIO_RX_DATA = 17'h50C;
localparam MDIO_OP_RD = 2'b10;
localparam MDIO_OP_WR = 2'b01;
// PHY Registers
// phy address is actually a 6 bit field but other bits are reserved so simpler to specify as 8 bit
localparam PHY_ADDR = 8'h7;
localparam PHY_CONTROL_REG = 8'h0;
localparam PHY_STATUS_REG = 8'h1;
localparam PHY_ABILITY_REG = 8'h4;
localparam PHY_1000BASET_CONTROL_REG = 8'h9;
//-------------------------------------------------
// Wire/reg declarations
reg [4:0] axi_status; // used to keep track of axi transactions
reg mdio_ready; // captured to acknowledge the end of mdio transactions
reg [31:0] axi_rd_data;
reg [31:0] axi_wr_data;
reg [31:0] mdio_wr_data;
reg [4:0] axi_state; // main state machine to configure example design
reg [1:0] mdio_access_sm; // mdio state machine to handle mdio register config
reg [1:0] axi_access_sm; // axi state machine - handles the 5 channels
reg start_access; // used to kick the axi acees state machine
reg start_mdio; // used to kick the mdio state machine
reg drive_mdio; // selects between mdio fields and direct sm control
reg [1:0] mdio_op;
reg [7:0] mdio_reg_addr;
reg writenread;
reg [16:0] addr;
reg [1:0] speed;
wire update_speed_sync;
reg update_speed_reg;
reg [20:0] count_shift = {21{1'b1}};
reg [36:0] serial_command_shift;
reg load_data;
reg capture_data;
reg write_access;
reg read_access;
wire s_axi_reset;
assign s_axi_reset = !s_axi_resetn;
tri_mode_ethernet_mac_0_sync_block update_speed_sync_inst (
.clk (s_axi_aclk),
.data_in (update_speed),
.data_out (update_speed_sync)
);
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
update_speed_reg <= 0;
end
else begin
update_speed_reg <= update_speed_sync;
end
end
//----------------------------------------------------------------------------
// Management process. This process sets up the configuration by
// turning off flow control, then checks gathered statistics at the
// end of transmission
//----------------------------------------------------------------------------
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_state <= STARTUP;
start_access <= 0;
start_mdio <= 0;
drive_mdio <= 0;
mdio_op <= 0;
mdio_reg_addr <= 0;
writenread <= 0;
addr <= 0;
axi_wr_data <= 0;
speed <= mac_speed;
end
// main state machine is kicking off multi cycle accesses in each state so has to
// stall while they take place
else if (axi_access_sm == IDLE && mdio_access_sm == IDLE && !start_access && !start_mdio) begin
case (axi_state)
STARTUP : begin
// this state will be ran after reset to wait for count_shift
if (count_shift[20] == 1'b0) begin
// set up MDC frequency. Write 0x58 to Management configuration
// register (Add=340). This will enable MDIO and set MDC to 2.5MHz
// (set CLOCK_DIVIDE value to 24 dec. for 125MHz s_axi_aclk and
// enable mdio)
$display("** Note: Setting MDC Frequency to 2.5MHZ....");
speed <= mac_speed;
start_access <= 1;
writenread <= 1;
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= 32'h58;
axi_state <= UPDATE_SPEED;
end
end
// program the MAC to the required speed
UPDATE_SPEED : begin
$display("** Note: Programming MAC speed");
drive_mdio <= 0;
start_access <= 1;
writenread <= 1;
addr <= SPEED_CONFIG_ADD;
// bits 31:30 are used
axi_wr_data <= {speed, 30'h0};
axi_state <= MDIO_RD;
end
MDIO_RD : begin
// read phy status - if response is all ones then do not perform any
// further MDIO accesses
$display("** Note: Checking for PHY");
drive_mdio <= 1; // switch axi transactions to use mdio values..
start_mdio <= 1;
writenread <= 0;
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_POLL_CHECK;
end
MDIO_POLL_CHECK : begin
if (axi_rd_data[16:0] == 17'h1ffff) begin
// if status is all ones then no PHY exists at this address
// (this is used by the tri_mode_ethernet_mac_0_demo_tb to avoid performing lots of phy accesses)
axi_state <= RESET_MAC_RX;
end
else begin
axi_state <= MDIO_1G;
end
end
MDIO_1G : begin
// set 1G advertisement
$display("** Note: Setting PHY 1G advertisement");
start_mdio <= 1;
mdio_reg_addr <= PHY_1000BASET_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
// 0x200 is 1G full duplex, 0x100 is 1G half duplex
// only advertise the mode we want..
axi_wr_data <= {16'h0, 6'h0, speed[1], 9'h0};
axi_state <= MDIO_10_100;
end
MDIO_10_100 : begin
// set 10/100 advertisement
$display("** Note: Setting PHY 10/100M advertisement");
start_mdio <= 1;
mdio_reg_addr <= PHY_ABILITY_REG;
mdio_op <= MDIO_OP_WR;
// bit8 : full 100M, bit7 : half 100M, bit6 : full 10M, bit5 : half 10M
// only advertise the mode we want..
axi_wr_data <= {16'h0, 7'h0, !speed[1] & speed[0], 1'b0, !speed[1] & !speed[0], 6'h0};
axi_state <= MDIO_RESTART;
end
MDIO_RESTART : begin
// set autoneg and reset
// if loopback is selected then do not set autonegotiate and program the required speed directly
// otherwise set autonegotiate
$display("** Note: Applying PHY software reset");
start_mdio <= 1;
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
if (phy_loopback) begin
// bit15: software reset, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= {16'h0, 2'b10, !speed[1] & speed[0], 4'h0, 1'b1, 1'b0, speed[1], 6'h0};
axi_state <= MDIO_LOOPBACK;
end
else begin
// bit15: software reset, bit12 : AN enable (set after power up)
axi_wr_data <= {16'h0, 4'h9, 12'h0};
axi_state <= MDIO_STATS;
end
end
MDIO_LOOPBACK : begin
// set phy loopback
$display("** Note: Settling PHY Loopback");
start_mdio <= 1;
mdio_reg_addr <= PHY_CONTROL_REG;
mdio_op <= MDIO_OP_WR;
// bit14: loopback, bit13 : speed LSB, bit 8 : full duplex, bit 6 : speed MSB
axi_wr_data <= {16'h0, 2'b01, !speed[1] & speed[0], 4'h0, 1'b1, 1'b0, speed[1], 6'h0};
axi_state <= RESET_MAC_RX;
end
MDIO_STATS : begin
start_mdio <= 1;
$display("** Note: Wait for Autonegotiation to complete");
mdio_reg_addr <= PHY_STATUS_REG;
mdio_op <= MDIO_OP_RD;
axi_state <= MDIO_STATS_POLL_CHECK;
end
MDIO_STATS_POLL_CHECK : begin
// bit 5 is autoneg complete - assume required speed is selected
if (axi_rd_data[5] == 1'b1 && axi_rd_data[16] == 1'b1)
axi_state <= RESET_MAC_RX;
else
axi_state <= MDIO_STATS;
end
// once here the PHY is ACTIVE - NOTE only IEEE registers are used
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_RX : begin
$display("** Note: Reseting MAC RX");
drive_mdio <= 0;
start_access <= 1;
writenread <= 1;
addr <= RECEIVER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= RESET_MAC_TX;
end
// this state will drive the reset to the example design (apart from this block)
// this will be separately captured and synched into the various clock domains
RESET_MAC_TX : begin
$display("** Note: Reseting MAC TX");
start_access <= 1;
writenread <= 1;
addr <= TRANSMITTER_ADD;
axi_wr_data <= 32'h90000000;
axi_state <= CNFG_MDIO;
end
CNFG_MDIO : begin
// set up MDC frequency. Write 2E to Management configuration
// register (Add=340). This will enable MDIO and set MDC to 2.5MHz
// (set CLOCK_DIVIDE value to 50 dec. for 125MHz s_axi_aclk and
// enable mdio)
$display("** Note: Setting MDC Frequency to 2.5MHZ....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_MANAGEMENT_ADD;
axi_wr_data <= 32'h68;
axi_state <= CNFG_FLOW;
end
CNFG_FLOW : begin
$display("** Note: Disabling Flow control....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_FLOW_CTRL_ADD;
axi_wr_data <= 32'h0;
axi_state <= CNFG_LO_ADDR;
end
CNFG_LO_ADDR : begin
$display("** Note: Configuring unicast address(low word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI0_CTRL_ADD;
axi_wr_data <= 32'h040302DA;
axi_state <= CNFG_HI_ADDR;
end
CNFG_HI_ADDR : begin
$display("** Note: Configuring unicast address(high word)....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_UNI1_CTRL_ADD;
axi_wr_data <= 32'h0605;
axi_state <= CNFG_FILTER;
end
CNFG_FILTER : begin
$display("** Note: Setting core to promiscuous mode....");
start_access <= 1;
writenread <= 1;
addr <= CONFIG_ADDR_CTRL_ADD;
axi_wr_data <= 32'h80000000;
axi_state <= CHECK_SPEED;
end
CHECK_SPEED : begin
if (update_speed_reg) begin
axi_state <= UPDATE_SPEED;
speed <= mac_speed;
end
else begin
if (capture_data)
axi_wr_data <= serial_command_shift[33:2];
if (write_access || read_access) begin
addr <= {5'b0, serial_command_shift[13:2]};
start_access <= 1;
writenread <= write_access;
end
end
end
default : begin
axi_state <= STARTUP;
end
endcase
end
else begin
start_access <= 0;
start_mdio <= 0;
end
end
//------------------------------------------------
// MDIO setup - split from main state machine to make more manageable
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
mdio_access_sm <= IDLE;
end
else if (axi_access_sm == IDLE || axi_access_sm == DONE) begin
case (mdio_access_sm)
IDLE : begin
if (start_mdio) begin
if (mdio_op == MDIO_OP_WR) begin
mdio_access_sm <= SET_DATA;
mdio_wr_data <= axi_wr_data;
end
else begin
mdio_access_sm <= INIT;
mdio_wr_data <= {PHY_ADDR, mdio_reg_addr, mdio_op, 3'h1, 11'h0};
end
end
end
SET_DATA : begin
mdio_access_sm <= INIT;
mdio_wr_data <= {PHY_ADDR, mdio_reg_addr, mdio_op, 3'h1, 11'h0};
end
INIT : begin
mdio_access_sm <= POLL;
end
POLL : begin
if (mdio_ready)
mdio_access_sm <= IDLE;
end
endcase
end
else if (mdio_access_sm == POLL && mdio_ready) begin
mdio_access_sm <= IDLE;
end
end
//-------------------------------------------------------------------------------------------
// processes to generate the axi transactions - only simple reads and write can be generated
always @(posedge s_axi_aclk)
begin
if (s_axi_reset) begin
axi_access_sm <= IDLE;
end
else begin
case (axi_access_sm)
IDLE : begin
if (start_access || start_mdio || mdio_access_sm != IDLE) begin
if (mdio_access_sm == POLL) begin
axi_access_sm <= READ;
end
else if ((start_access && writenread) ||
(mdio_access_sm == SET_DATA || mdio_access_sm == INIT) || start_mdio) begin
axi_access_sm <= WRITE;
end
else begin
axi_access_sm <= READ;
end
end
end
WRITE : begin
// wait in this state until axi_status signals the write is complete
if (axi_status[4:2] == 3'b111)
axi_access_sm <= DONE;
end
READ : begin
// wait in this state until axi_status signals the read is complete
if (axi_status[1:0] == 2'b11)
axi_access_sm <= DONE;
end
DONE : begin
axi_access_sm <= IDLE;
end
endcase
end
end
// need a process per axi interface (i.e 5)
// in each case the interface is driven accordingly and once acknowledged a sticky
// status bit is set and the process waits until the access_sm moves on
// READ ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[0]) begin
if (drive_mdio) begin
s_axi_araddr <= MDIO_RX_DATA;
end
else begin
s_axi_araddr <= addr;
end
s_axi_arvalid <= 1'b1;
if (s_axi_arready == 1'b1 && s_axi_arvalid) begin
axi_status[0] <= 1;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
end
else begin
axi_status[0] <= 0;
s_axi_araddr <= 0;
s_axi_arvalid <= 0;
end
end
// READ DATA/RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == READ) begin
if (!axi_status[1]) begin
s_axi_rready <= 1'b1;
if (s_axi_rvalid == 1'b1 && s_axi_rready) begin
axi_status[1] <= 1;
s_axi_rready <= 0;
axi_rd_data <= s_axi_rdata;
if (drive_mdio & s_axi_rdata[16])
mdio_ready <= 1;
end
end
end
else begin
s_axi_rready <= 0;
axi_status[1] <= 0;
if (axi_access_sm == IDLE & (start_access || start_mdio)) begin
mdio_ready <= 0;
axi_rd_data <= 0;
end
end
end
// WRITE ADDR
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[2]) begin
if (drive_mdio) begin
if (mdio_access_sm == SET_DATA)
s_axi_awaddr <= MDIO_TX_DATA;
else
s_axi_awaddr <= MDIO_CONTROL;
end
else begin
s_axi_awaddr <= addr;
end
s_axi_awvalid <= 1'b1;
if (s_axi_awready == 1'b1 && s_axi_awvalid) begin
axi_status[2] <= 1;
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
end
end
end
else begin
s_axi_awaddr <= 0;
s_axi_awvalid <= 0;
axi_status[2] <= 0;
end
end
// WRITE DATA
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[3]) begin
if (drive_mdio) begin
s_axi_wdata <= mdio_wr_data;
end
else begin
s_axi_wdata <= axi_wr_data;
end
s_axi_wvalid <= 1'b1;
if (s_axi_wready == 1'b1 && s_axi_wvalid) begin
axi_status[3] <= 1;
s_axi_wvalid <= 0;
end
end
end
else begin
s_axi_wdata <= 0;
s_axi_wvalid <= 0;
axi_status[3] <= 0;
end
end
// WRITE RESP
always @(posedge s_axi_aclk)
begin
if (axi_access_sm == WRITE) begin
if (!axi_status[4]) begin
s_axi_bready <= 1'b1;
if (s_axi_bvalid == 1'b1 && s_axi_bready) begin
axi_status[4] <= 1;
s_axi_bready <= 0;
end
end
end
else begin
s_axi_bready <= 0;
axi_status[4] <= 0;
end
end
//-------------------------------------------------------------------------------------------------------
// to avoid logic being stripped a serial input is included which enables an address/data and control to be setup for
// a user config access..
always @(posedge s_axi_aclk)
begin
if (load_data)
serial_command_shift <= {serial_command_shift[35:33], axi_rd_data, serial_command_shift[0], serial_command};
else
serial_command_shift <= {serial_command_shift[35:0], serial_command};
end
// only deassert serial_response once we reach the state in which we can use the serial_command
assign serial_response = (axi_state == CHECK_SPEED) ? serial_command_shift[35] : 1'b1;
// the serial command is expected to have a start and stop bit - to avoid a counter -
// and a two bit code field in the uppper two bits.
// these decode as follows:
// 00 - read address
// 01 - write address
// 10 - write data
// 11 - read data - slightly more involved - when detected the read data is registered into the shift and passed out
// 11 is used for read data as if the input is tied high the output will simply reflect whatever was
// captured but will not result in any activity
// it is expected that the write data is setup BEFORE the write address
always @(posedge s_axi_aclk)
begin
load_data <= 0;
capture_data <= 0;
write_access <= 0;
read_access <= 0;
if (!serial_command_shift[36] & serial_command_shift[35] & serial_command_shift[0])
if (serial_command_shift[34] & serial_command_shift[33]) // READ DATA
load_data <= 1;
else if (serial_command_shift[34] & !serial_command_shift[33]) // WRITE DATA
capture_data <= 1;
else if (!serial_command_shift[34] & serial_command_shift[33]) // WRITE ADDRESS
write_access <= 1;
else // READ ADDRESS
read_access <= 1;
end
// don't reset this - it will always be updated before it is used..
// it does need an init value (all ones)
always @(posedge s_axi_aclk)
begin
count_shift <= {count_shift[19:0], s_axi_reset};
end
endmodule |
module pDPM_top(
input glbl_rst,
input sys_clk_100M,
/*
* Ports group I: network related
* and some LED/switch input/output.
*/
/* 25MHz output clk for PHY */
output mii_ref_clk_out,
output phy_resetn,
/* MII Interface */
output [3:0] mii_txd,
output mii_tx_en,
input [3:0] mii_rxd,
input mii_rx_dv,
input mii_rx_er,
input mii_rx_clk,
input mii_tx_clk,
/* MDIO Interface */
inout mdio,
output mdc,
/* Serialised statistics vectors */
output tx_statistics_s,
output rx_statistics_s,
/* Serialised Pause interface controls */
input pause_req_s,
/* Main example design controls */
input [1:0] mac_speed,
input update_speed,
input config_board,
output serial_response,
input gen_tx_data,
input chk_tx_data,
input reset_error,
output frame_error,
output activity_flash,
output user_LED,
/*
* I changed the original one. This one now indicate
* package generation activity.
*/
output activity_flash_gen,
/*
* I added this. This indicates if packet generation is enabled.
* It directly reflects gen_tx_data switch.
* It is now connected to LD3 blue light
*/
output pkt_gen_enabled,
/*
* Port Group II: memory interface
* mainly the DDR3 signals
*/
output [13:0] ddr3_sdram_addr,
output [2:0] ddr3_sdram_ba,
output ddr3_sdram_cas_n,
output [0:0] ddr3_sdram_ck_n,
output [0:0] ddr3_sdram_ck_p,
output [0:0] ddr3_sdram_cke,
output [0:0] ddr3_sdram_cs_n,
output [1:0] ddr3_sdram_dm,
inout [15:0] ddr3_sdram_dq,
inout [1:0] ddr3_sdram_dqs_n,
inout [1:0] ddr3_sdram_dqs_p,
output [0:0] ddr3_sdram_odt,
output ddr3_sdram_ras_n,
output ddr3_sdram_reset_n,
output ddr3_sdram_we_n
);
/* AXI-S: Network to Memory */
wire rx_fifo_clock;
wire rx_fifo_resetn;
wire [7:0] rx_axis_fifo_tdata;
wire rx_axis_fifo_tvalid;
wire rx_axis_fifo_tlast;
wire rx_axis_fifo_tready;
/* AXI-S: Memory to Network */
wire tx_fifo_clock;
wire tx_fifo_resetn;
wire [7:0] tx_axis_fifo_tdata;
wire tx_axis_fifo_tvalid;
wire tx_axis_fifo_tlast;
wire tx_axis_fifo_tready;
wire mig_166MHZ;
wire mig_ref_200MHZ;
wire mig_sys_rst_n;
wire net_125MHZ;
wire net_25MHZ;
design_1 clock_generator
(
.sys_clock (sys_clk_100M),
.clk_out1_0 (net_125MHZ),
.clk_out2_0 (net_25MHZ),
.clk_out3_0 (mig_166MHZ),
.clk_out4_0 (mig_ref_200MHZ),
/* High when clock output is valid */
.locked_0 (clock_locked)
);
assign mig_sys_rst_n = clock_locked;
/* Output clock to PHY */
assign mii_ref_clk_out = net_25MHZ;
tri_mode_ethernet_mac_0_example_design pdpm_network
(
.glbl_rst (glbl_rst),
.clk_100MHZ (sys_clk_100M),
.clk_125MHZ (net_125MHZ),
.clk_locked (clock_locked),
.phy_resetn (phy_resetn),
/* MII and MDIO */
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rx_clk (mii_rx_clk),
.mii_tx_clk (mii_tx_clk),
.mdio (mdio),
.mdc (mdc),
/* Misc input and output */
.tx_statistics_s (tx_statistics_s),
.rx_statistics_s (rx_statistics_s),
.pause_req_s (pause_req_s),
.mac_speed (mac_speed),
.update_speed (update_speed),
.config_board (config_board),
.serial_response (serial_response),
.gen_tx_data (gen_tx_data),
.chk_tx_data (chk_tx_data),
.reset_error (reset_error),
.frame_error (frame_error),
.activity_flash (activity_flash),
.user_LED (user_LED),
.activity_flash_gen (activity_flash_gen),
.pkt_gen_enabled (pkt_gen_enabled),
/* AXI-S to Memory */
.rx_fifo_clock_ref (rx_fifo_clock),
.rx_fifo_resetn_ref (rx_fifo_resetn),
.rx_axis_fifo_tdata (rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid),
.rx_axis_fifo_tready (rx_axis_fifo_tready),
.rx_axis_fifo_tlast (rx_axis_fifo_tlast),
/* AXI-S from Memory */
.tx_fifo_clock_ref (tx_fifo_clock),
.tx_fifo_resetn_ref (tx_fifo_resetn),
.tx_axis_fifo_tdata (tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid),
.tx_axis_fifo_tready (tx_axis_fifo_tready),
.tx_axis_fifo_tlast (tx_axis_fifo_tlast)
);
pdpm_system_2 pdpm_memory (
.mig_166MHZ (mig_166MHZ),
.mig_ref_200MHZ (mig_ref_200MHZ),
.mig_sys_rst_n (mig_sys_rst_n),
/* AXI-S to Network */
.m_axis_aclk_0 (tx_fifo_clock),
.m_axis_aresetn_0 (tx_fifo_resetn),
.M_AXIS_0_tdata (tx_axis_fifo_tdata),
.M_AXIS_0_tlast (tx_axis_fifo_tlast),
.M_AXIS_0_tready (tx_axis_fifo_tready),
.M_AXIS_0_tvalid (tx_axis_fifo_tvalid),
/* AXI-S from Network */
.s_axis_aclk_0 (rx_fifo_clock),
.s_axis_aresetn_0 (rx_fifo_resetn),
.S_AXIS_0_tdata (rx_axis_fifo_tdata),
.S_AXIS_0_tlast (rx_axis_fifo_tlast),
.S_AXIS_0_tready (rx_axis_fifo_tready),
.S_AXIS_0_tvalid (rx_axis_fifo_tvalid),
/* DDR3 */
.ddr3_sdram_addr (ddr3_sdram_addr),
.ddr3_sdram_ba (ddr3_sdram_ba),
.ddr3_sdram_cas_n (ddr3_sdram_cas_n),
.ddr3_sdram_ck_n (ddr3_sdram_ck_n),
.ddr3_sdram_ck_p (ddr3_sdram_ck_p),
.ddr3_sdram_cke (ddr3_sdram_cke),
.ddr3_sdram_cs_n (ddr3_sdram_cs_n),
.ddr3_sdram_dm (ddr3_sdram_dm),
.ddr3_sdram_dq (ddr3_sdram_dq),
.ddr3_sdram_dqs_n (ddr3_sdram_dqs_n),
.ddr3_sdram_dqs_p (ddr3_sdram_dqs_p),
.ddr3_sdram_odt (ddr3_sdram_odt),
.ddr3_sdram_ras_n (ddr3_sdram_ras_n),
.ddr3_sdram_reset_n (ddr3_sdram_reset_n),
.ddr3_sdram_we_n (ddr3_sdram_we_n)
);
endmodule |
module pdpm_top_tb(
);
endmodule |
module pdpm_mem_tb(
);
endmodule |
module tri_mode_ethernet_mac_0_example_design
(
/* async reset, now it's a button */
input glbl_rst,
input clk_100MHZ,
input clk_125MHZ,
input clk_locked,
output phy_resetn,
// MII Interface
//---------------
output [3:0] mii_txd,
output mii_tx_en,
//output mii_tx_er,
input [3:0] mii_rxd,
input mii_rx_dv,
input mii_rx_er,
input mii_rx_clk,
input mii_tx_clk,
// MDIO Interface
//---------------
inout mdio,
output mdc,
// Serialised statistics vectors
//------------------------------
output tx_statistics_s,
output rx_statistics_s,
// Serialised Pause interface controls
//------------------------------------
input pause_req_s,
// Main example design controls
//-----------------------------
input [1:0] mac_speed,
input update_speed,
//input serial_command, // tied to pause_req_s
input config_board,
output serial_response,
input gen_tx_data,
input chk_tx_data,
input reset_error,
output frame_error,
output activity_flash,
output user_LED,
/*
* I changed the original one. This one now indicate
* package generation activity.
*/
output activity_flash_gen,
/*
* I added this. This indicates if packet generation is enabled.
* It directly reflects gen_tx_data switch.
* It is now connected to LD3 blue light
*/
output pkt_gen_enabled,
/* AXI-S: network to memory, output */
output [7:0] rx_axis_fifo_tdata,
output rx_axis_fifo_tvalid,
input rx_axis_fifo_tready,
output rx_axis_fifo_tlast,
output rx_fifo_clock_ref,
output rx_fifo_resetn_ref,
/* AXI-S: memory to network, input */
input [7:0] tx_axis_fifo_tdata,
input tx_axis_fifo_tvalid,
output tx_axis_fifo_tready,
input tx_axis_fifo_tlast,
output tx_fifo_clock_ref,
output tx_fifo_resetn_ref
);
//----------------------------------------------------------------------------
// internal signals used in this top level wrapper.
//----------------------------------------------------------------------------
// example design clocks
wire gtx_clk_bufg;
wire s_axi_aclk;
wire rx_mac_aclk;
wire tx_mac_aclk;
// resets (and reset generation)
wire s_axi_resetn;
wire chk_resetn;
wire gtx_resetn;
wire rx_reset;
wire tx_reset;
wire dcm_locked;
wire glbl_rst_intn;
// RX Statistics serialisation signals
wire rx_statistics_valid;
reg rx_statistics_valid_reg;
wire [27:0] rx_statistics_vector;
reg [27:0] rx_stats;
reg [29:0] rx_stats_shift;
reg rx_stats_toggle = 0;
wire rx_stats_toggle_sync;
reg rx_stats_toggle_sync_reg = 0;
// TX Statistics serialisation signals
wire tx_statistics_valid;
reg tx_statistics_valid_reg;
wire [31:0] tx_statistics_vector;
reg [31:0] tx_stats;
reg [33:0] tx_stats_shift;
reg tx_stats_toggle = 0;
wire tx_stats_toggle_sync;
reg tx_stats_toggle_sync_reg = 0;
// Pause interface DESerialisation
reg [18:0] pause_shift;
reg pause_req;
reg [15:0] pause_val;
// AXI-Lite interface
wire [11:0] s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_awready;
wire [31:0] s_axi_wdata;
wire s_axi_wvalid;
wire s_axi_wready;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
wire s_axi_bready;
wire [11:0] s_axi_araddr;
wire s_axi_arvalid;
wire s_axi_arready;
wire [31:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rready;
wire int_frame_error;
wire int_activity_flash;
wire int_activity_flash_gen;
// set board defaults - only updated when reprogrammed
reg enable_address_swap = 1;
reg enable_phy_loopback = 0;
// signal tie offs
wire [7:0] tx_ifg_delay = 0; // not used in this example
assign activity_flash = int_activity_flash;
assign activity_flash_gen = int_activity_flash_gen;
wire mdio_i;
wire mdio_o;
wire mdio_t;
wire mii_tx_er;
//----------------------------------------------------------------------------
// Begin the logic description
//----------------------------------------------------------------------------
/* Input clocks */
assign gtx_clk_bufg = clk_125MHZ;
assign s_axi_aclk = clk_100MHZ;
assign dcm_locked = clk_locked;
/* user side clocks for the axi fifos */
assign tx_fifo_clock_ref = gtx_clk_bufg;
assign rx_fifo_clock_ref = gtx_clk_bufg;
// want to infer an IOBUF on the mdio port
assign mdio = mdio_t ? 1'bz : mdio_o;
assign mdio_i = mdio;
assign frame_error = int_frame_error;
// when the config_board button is pushed capture and hold the
// state of the gne/chek tx_data inputs. These values will persist until the
// board is reprogrammed or config_board is pushed again
always @(posedge gtx_clk_bufg)
begin
if (config_board) begin
enable_address_swap <= gen_tx_data;
end
end
always @(posedge s_axi_aclk)
begin
if (config_board) begin
enable_phy_loopback <= chk_tx_data;
end
end
//----------------------------------------------------------------------------
// Generate resets required for the fifo side signals etc
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_example_design_resets example_resets
(
// clocks
.s_axi_aclk (s_axi_aclk),
.gtx_clk (gtx_clk_bufg),
// asynchronous resets
.glbl_rst (glbl_rst),
.reset_error (reset_error),
.rx_reset (rx_reset),
.tx_reset (tx_reset),
.dcm_locked (dcm_locked),
// synchronous reset outputs
.glbl_rst_intn (glbl_rst_intn),
.gtx_resetn (gtx_resetn),
.s_axi_resetn (s_axi_resetn),
.phy_resetn (phy_resetn),
.chk_resetn (chk_resetn)
);
// generate the user side resets for the axi fifos
assign tx_fifo_resetn = gtx_resetn;
assign rx_fifo_resetn = gtx_resetn;
assign tx_fifo_resetn_ref = gtx_resetn;
assign rx_fifo_resetn_ref = gtx_resetn;
//----------------------------------------------------------------------------
// Serialize the stats vectors
// This is a single bit approach, retimed onto gtx_clk
// this code is only present to prevent code being stripped..
//----------------------------------------------------------------------------
// RX STATS
// first capture the stats on the appropriate clock
always @(posedge rx_mac_aclk)
begin
rx_statistics_valid_reg <= rx_statistics_valid;
if (!rx_statistics_valid_reg & rx_statistics_valid) begin
rx_stats <= rx_statistics_vector;
rx_stats_toggle <= !rx_stats_toggle;
end
end
tri_mode_ethernet_mac_0_sync_block rx_stats_sync (
.clk (gtx_clk_bufg),
.data_in (rx_stats_toggle),
.data_out (rx_stats_toggle_sync)
);
always @(posedge gtx_clk_bufg)
begin
rx_stats_toggle_sync_reg <= rx_stats_toggle_sync;
end
// when an update is rxd load shifter (plus start/stop bit)
// shifter always runs (no power concerns as this is an example design)
always @(posedge gtx_clk_bufg)
begin
if (rx_stats_toggle_sync_reg != rx_stats_toggle_sync) begin
rx_stats_shift <= {1'b1, rx_stats, 1'b1};
end
else begin
rx_stats_shift <= {rx_stats_shift[28:0], 1'b0};
end
end
assign rx_statistics_s = rx_stats_shift[29];
// TX STATS
// first capture the stats on the appropriate clock
always @(posedge tx_mac_aclk)
begin
tx_statistics_valid_reg <= tx_statistics_valid;
if (!tx_statistics_valid_reg & tx_statistics_valid) begin
tx_stats <= tx_statistics_vector;
tx_stats_toggle <= !tx_stats_toggle;
end
end
tri_mode_ethernet_mac_0_sync_block tx_stats_sync (
.clk (gtx_clk_bufg),
.data_in (tx_stats_toggle),
.data_out (tx_stats_toggle_sync)
);
always @(posedge gtx_clk_bufg)
begin
tx_stats_toggle_sync_reg <= tx_stats_toggle_sync;
end
// when an update is txd load shifter (plus start bit)
// shifter always runs (no power concerns as this is an example design)
always @(posedge gtx_clk_bufg)
begin
if (tx_stats_toggle_sync_reg != tx_stats_toggle_sync) begin
tx_stats_shift <= {1'b1, tx_stats, 1'b1};
end
else begin
tx_stats_shift <= {tx_stats_shift[32:0], 1'b0};
end
end
assign tx_statistics_s = tx_stats_shift[33];
//----------------------------------------------------------------------------
// DSerialize the Pause interface
// This is a single bit approachtimed on gtx_clk
// this code is only present to prevent code being stripped..
//----------------------------------------------------------------------------
// the serialised pause info has a start bit followed by the quanta and a stop bit
// capture the quanta when the start bit hits the msb and the stop bit is in the lsb
always @(posedge gtx_clk_bufg)
begin
pause_shift <= {pause_shift[17:0], pause_req_s};
end
always @(posedge gtx_clk_bufg)
begin
if (pause_shift[18] == 1'b0 & pause_shift[17] == 1'b1 & pause_shift[0] == 1'b1) begin
pause_req <= 1'b1;
pause_val <= pause_shift[16:1];
end
else begin
pause_req <= 1'b0;
pause_val <= 0;
end
end
//----------------------------------------------------------------------------
// Instantiate the AXI-LITE Controller
//----------------------------------------------------------------------------
tri_mode_ethernet_mac_0_axi_lite_sm axi_lite_controller (
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.mac_speed (mac_speed),
.update_speed (update_speed), // may need glitch protection on this..
.serial_command (pause_req_s),
.serial_response (serial_response),
.phy_loopback (enable_phy_loopback),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready)
);
/*
* The FIFO and MAC block
* Interaction with MAC is taken care of, we want to hack
* the communication with our own logic.
*/
tri_mode_ethernet_mac_0_fifo_block trimac_fifo_block (
.gtx_clk (gtx_clk_bufg),
// asynchronous reset
.glbl_rstn (glbl_rst_intn),
.rx_axi_rstn (1'b1),
.tx_axi_rstn (1'b1),
// Receiver Statistics Interface
//---------------------------------------
.rx_mac_aclk (rx_mac_aclk),
.rx_reset (rx_reset),
.rx_statistics_vector (rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid),
// Receiver (AXI-S) Interface
//----------------------------------------
.rx_fifo_clock (rx_fifo_clock_ref),
.rx_fifo_resetn (rx_fifo_resetn_ref),
.rx_axis_fifo_tdata (rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid),
.rx_axis_fifo_tready (rx_axis_fifo_tready),
.rx_axis_fifo_tlast (rx_axis_fifo_tlast),
// Transmitter (AXI-S) Interface
//-------------------------------------------
.tx_fifo_clock (tx_fifo_clock_ref),
.tx_fifo_resetn (tx_fifo_resetn_ref),
.tx_axis_fifo_tdata (tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid),
.tx_axis_fifo_tready (tx_axis_fifo_tready),
.tx_axis_fifo_tlast (tx_axis_fifo_tlast),
// Transmitter Statistics Interface
//------------------------------------------
.tx_mac_aclk (tx_mac_aclk),
.tx_reset (tx_reset),
.tx_ifg_delay (tx_ifg_delay),
.tx_statistics_vector (tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid),
// MAC Control Interface
//------------------------
.pause_req (pause_req),
.pause_val (pause_val),
// MII Interface
//---------------
.mii_txd (mii_txd),
.mii_tx_en (mii_tx_en),
.mii_tx_er (mii_tx_er),
.mii_rxd (mii_rxd),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rx_clk (mii_rx_clk),
.mii_tx_clk (mii_tx_clk),
// MDIO Interface
//---------------
.mdc (mdc),
.mdio_i (mdio_i),
.mdio_o (mdio_o),
.mdio_t (mdio_t),
// AXI-Lite Interface
//---------------
.s_axi_aclk (s_axi_aclk),
.s_axi_resetn (s_axi_resetn),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
.user_LED (user_LED)
);
endmodule |
module pmu_dummy_top(
cpu_pmu_dfs_ack,
cpu_pmu_sleep_b,
dft_clk,
ehs_pmu_clk,
els_pmu_clk,
pad_core_clk,
pad_core_ctim_refclk,
pad_core_rst_b,
pad_mcurst_b,
paddr,
penable,
pmu_apb0_pclk_en,
pmu_apb0_s3clk,
pmu_apb0_s3rst_b,
pmu_apb1_pclk_en,
pmu_apb1_s3clk,
pmu_apb1_s3rst_b,
pmu_cpu_dfs_req,
pmu_dmac0_hclk,
pmu_dmac0_hrst_b,
pmu_dmemdummy0_hclk,
pmu_dmemdummy0_hrst_b,
pmu_dummy0_hclk,
pmu_dummy0_hrst_b,
pmu_dummy0_s3clk,
pmu_dummy0_s3rst_b,
pmu_dummy1_hclk,
pmu_dummy1_hrst_b,
pmu_dummy1_p0clk,
pmu_dummy1_p0rst_b,
pmu_dummy1_p1clk,
pmu_dummy1_p1rst_b,
pmu_dummy1_s3clk,
pmu_dummy1_s3rst_b,
pmu_dummy2_hclk,
pmu_dummy2_hrst_b,
pmu_dummy2_p0clk,
pmu_dummy2_p0rst_b,
pmu_dummy2_p1clk,
pmu_dummy2_p1rst_b,
pmu_dummy2_s3clk,
pmu_dummy2_s3rst_b,
pmu_dummy3_hclk,
pmu_dummy3_hrst_b,
pmu_dummy3_p0clk,
pmu_dummy3_p0rst_b,
pmu_dummy3_p1clk,
pmu_dummy3_p1rst_b,
pmu_dummy3_s3clk,
pmu_dummy3_s3rst_b,
pmu_dummy4_p0clk,
pmu_dummy4_p0rst_b,
pmu_dummy4_p1clk,
pmu_dummy4_p1rst_b,
pmu_dummy5_p0clk,
pmu_dummy5_p0rst_b,
pmu_dummy5_p1clk,
pmu_dummy5_p1rst_b,
pmu_dummy6_p1clk,
pmu_dummy6_p1rst_b,
pmu_dummy7_p0clk,
pmu_dummy7_p0rst_b,
pmu_dummy7_p1clk,
pmu_dummy7_p1rst_b,
pmu_dummy8_p0clk,
pmu_dummy8_p0rst_b,
pmu_dummy8_p1clk,
pmu_dummy8_p1rst_b,
pmu_dummy9_p0clk,
pmu_dummy9_p0rst_b,
pmu_gpio_p1clk,
pmu_gpio_p1rst_b,
pmu_hmain0_hclk,
pmu_hmain0_hrst_b,
pmu_imemdummy0_hclk,
pmu_imemdummy0_hrst_b,
pmu_lsbus_hclk,
pmu_lsbus_hrst_b,
pmu_mdummy0_hclk,
pmu_mdummy0_hrst_b,
pmu_mdummy1_hclk,
pmu_mdummy1_hrst_b,
pmu_mdummy2_hclk,
pmu_mdummy2_hrst_b,
pmu_pwm_p0clk,
pmu_pwm_p0rst_b,
pmu_rtc_clk,
pmu_rtc_p1clk,
pmu_rtc_p1rst_b,
pmu_smc_hclk,
pmu_smc_hrst_b,
pmu_sub3_s3clk,
pmu_sub3_s3rst_b,
pmu_tim0_p0clk,
pmu_tim0_p0rst_b,
pmu_tim1_p1clk,
pmu_tim1_p1rst_b,
pmu_tim2_p0clk,
pmu_tim2_p0rst_b,
pmu_tim3_p1clk,
pmu_tim3_p1rst_b,
pmu_tim4_p0clk,
pmu_tim4_p0rst_b,
pmu_tim5_p1clk,
pmu_tim5_p1rst_b,
pmu_tim6_p0clk,
pmu_tim6_p0rst_b,
pmu_tim7_p1clk,
pmu_tim7_p1rst_b,
pmu_usi0_p0clk,
pmu_usi0_p0rst_b,
pmu_usi1_p1clk,
pmu_usi1_p1rst_b,
pmu_usi2_p0clk,
pmu_usi2_p0rst_b,
pmu_wdt_p0clk,
pmu_wdt_p0rst_b,
pmu_wic_intr,
pprot,
prdata,
psel,
pwdata,
pwrite,
wdt_pmu_rst_b
);
input cpu_pmu_dfs_ack;
input cpu_pmu_sleep_b;
input ehs_pmu_clk;
input els_pmu_clk;
input pad_mcurst_b;
input [31:0] paddr;
input penable;
input [2 :0] pprot;
input psel;
input [31:0] pwdata;
input pwrite;
input wdt_pmu_rst_b;
output dft_clk;
output pad_core_clk;
output pad_core_ctim_refclk;
output pad_core_rst_b;
output pmu_apb0_pclk_en;
output pmu_apb0_s3clk;
output pmu_apb0_s3rst_b;
output pmu_apb1_pclk_en;
output pmu_apb1_s3clk;
output pmu_apb1_s3rst_b;
output pmu_cpu_dfs_req;
output pmu_dmac0_hclk;
output pmu_dmac0_hrst_b;
output pmu_dmemdummy0_hclk;
output pmu_dmemdummy0_hrst_b;
output pmu_dummy0_hclk;
output pmu_dummy0_hrst_b;
output pmu_dummy0_s3clk;
output pmu_dummy0_s3rst_b;
output pmu_dummy1_hclk;
output pmu_dummy1_hrst_b;
output pmu_dummy1_p0clk;
output pmu_dummy1_p0rst_b;
output pmu_dummy1_p1clk;
output pmu_dummy1_p1rst_b;
output pmu_dummy1_s3clk;
output pmu_dummy1_s3rst_b;
output pmu_dummy2_hclk;
output pmu_dummy2_hrst_b;
output pmu_dummy2_p0clk;
output pmu_dummy2_p0rst_b;
output pmu_dummy2_p1clk;
output pmu_dummy2_p1rst_b;
output pmu_dummy2_s3clk;
output pmu_dummy2_s3rst_b;
output pmu_dummy3_hclk;
output pmu_dummy3_hrst_b;
output pmu_dummy3_p0clk;
output pmu_dummy3_p0rst_b;
output pmu_dummy3_p1clk;
output pmu_dummy3_p1rst_b;
output pmu_dummy3_s3clk;
output pmu_dummy3_s3rst_b;
output pmu_dummy4_p0clk;
output pmu_dummy4_p0rst_b;
output pmu_dummy4_p1clk;
output pmu_dummy4_p1rst_b;
output pmu_dummy5_p0clk;
output pmu_dummy5_p0rst_b;
output pmu_dummy5_p1clk;
output pmu_dummy5_p1rst_b;
output pmu_dummy6_p1clk;
output pmu_dummy6_p1rst_b;
output pmu_dummy7_p0clk;
output pmu_dummy7_p0rst_b;
output pmu_dummy7_p1clk;
output pmu_dummy7_p1rst_b;
output pmu_dummy8_p0clk;
output pmu_dummy8_p0rst_b;
output pmu_dummy8_p1clk;
output pmu_dummy8_p1rst_b;
output pmu_dummy9_p0clk;
output pmu_dummy9_p0rst_b;
output pmu_gpio_p1clk;
output pmu_gpio_p1rst_b;
output pmu_hmain0_hclk;
output pmu_hmain0_hrst_b;
output pmu_imemdummy0_hclk;
output pmu_imemdummy0_hrst_b;
output pmu_lsbus_hclk;
output pmu_lsbus_hrst_b;
output pmu_mdummy0_hclk;
output pmu_mdummy0_hrst_b;
output pmu_mdummy1_hclk;
output pmu_mdummy1_hrst_b;
output pmu_mdummy2_hclk;
output pmu_mdummy2_hrst_b;
output pmu_pwm_p0clk;
output pmu_pwm_p0rst_b;
output pmu_rtc_clk;
output pmu_rtc_p1clk;
output pmu_rtc_p1rst_b;
output pmu_smc_hclk;
output pmu_smc_hrst_b;
output pmu_sub3_s3clk;
output pmu_sub3_s3rst_b;
output pmu_tim0_p0clk;
output pmu_tim0_p0rst_b;
output pmu_tim1_p1clk;
output pmu_tim1_p1rst_b;
output pmu_tim2_p0clk;
output pmu_tim2_p0rst_b;
output pmu_tim3_p1clk;
output pmu_tim3_p1rst_b;
output pmu_tim4_p0clk;
output pmu_tim4_p0rst_b;
output pmu_tim5_p1clk;
output pmu_tim5_p1rst_b;
output pmu_tim6_p0clk;
output pmu_tim6_p0rst_b;
output pmu_tim7_p1clk;
output pmu_tim7_p1rst_b;
output pmu_usi0_p0clk;
output pmu_usi0_p0rst_b;
output pmu_usi1_p1clk;
output pmu_usi1_p1rst_b;
output pmu_usi2_p0clk;
output pmu_usi2_p0rst_b;
output pmu_wdt_p0clk;
output pmu_wdt_p0rst_b;
output pmu_wic_intr;
output [31:0] prdata;
wire dft_clk;
wire ehs_pmu_clk;
wire els_pmu_clk;
wire pad_core_clk;
wire pad_core_ctim_refclk;
wire pad_core_rst_b;
wire pad_mcurst_b;
wire pmu_apb0_pclk_en;
wire pmu_apb0_s3clk;
wire pmu_apb0_s3rst_b;
wire pmu_apb1_pclk_en;
wire pmu_apb1_s3clk;
wire pmu_apb1_s3rst_b;
wire pmu_cpu_dfs_req;
wire pmu_dmac0_hclk;
wire pmu_dmac0_hrst_b;
wire pmu_dmemdummy0_hclk;
wire pmu_dmemdummy0_hrst_b;
wire pmu_dummy0_hclk;
wire pmu_dummy0_hrst_b;
wire pmu_dummy0_s3clk;
wire pmu_dummy0_s3rst_b;
wire pmu_dummy1_hclk;
wire pmu_dummy1_hrst_b;
wire pmu_dummy1_p0clk;
wire pmu_dummy1_p0rst_b;
wire pmu_dummy1_p1clk;
wire pmu_dummy1_p1rst_b;
wire pmu_dummy1_s3clk;
wire pmu_dummy1_s3rst_b;
wire pmu_dummy2_hclk;
wire pmu_dummy2_hrst_b;
wire pmu_dummy2_p0clk;
wire pmu_dummy2_p0rst_b;
wire pmu_dummy2_p1clk;
wire pmu_dummy2_p1rst_b;
wire pmu_dummy2_s3clk;
wire pmu_dummy2_s3rst_b;
wire pmu_dummy3_hclk;
wire pmu_dummy3_hrst_b;
wire pmu_dummy3_p0clk;
wire pmu_dummy3_p0rst_b;
wire pmu_dummy3_p1clk;
wire pmu_dummy3_p1rst_b;
wire pmu_dummy3_s3clk;
wire pmu_dummy3_s3rst_b;
wire pmu_dummy4_p0clk;
wire pmu_dummy4_p0rst_b;
wire pmu_dummy4_p1clk;
wire pmu_dummy4_p1rst_b;
wire pmu_dummy5_p0clk;
wire pmu_dummy5_p0rst_b;
wire pmu_dummy5_p1clk;
wire pmu_dummy5_p1rst_b;
wire pmu_dummy6_p1clk;
wire pmu_dummy6_p1rst_b;
wire pmu_dummy7_p0clk;
wire pmu_dummy7_p0rst_b;
wire pmu_dummy7_p1clk;
wire pmu_dummy7_p1rst_b;
wire pmu_dummy8_p0clk;
wire pmu_dummy8_p0rst_b;
wire pmu_dummy8_p1clk;
wire pmu_dummy8_p1rst_b;
wire pmu_dummy9_p0clk;
wire pmu_dummy9_p0rst_b;
wire pmu_gpio_p1clk;
wire pmu_gpio_p1rst_b;
wire pmu_hmain0_hclk;
wire pmu_hmain0_hrst_b;
wire pmu_imemdummy0_hclk;
wire pmu_imemdummy0_hrst_b;
wire pmu_lsbus_hclk;
wire pmu_lsbus_hrst_b;
wire pmu_mdummy0_hclk;
wire pmu_mdummy0_hrst_b;
wire pmu_mdummy1_hclk;
wire pmu_mdummy1_hrst_b;
wire pmu_mdummy2_hclk;
wire pmu_mdummy2_hrst_b;
wire pmu_pwm_p0clk;
wire pmu_pwm_p0rst_b;
wire pmu_rtc_clk;
wire pmu_rtc_p1clk;
wire pmu_rtc_p1rst_b;
wire pmu_smc_hclk;
wire pmu_smc_hrst_b;
wire pmu_sub3_s3clk;
wire pmu_sub3_s3rst_b;
wire pmu_tim0_p0clk;
wire pmu_tim0_p0rst_b;
wire pmu_tim1_p1clk;
wire pmu_tim1_p1rst_b;
wire pmu_tim2_p0clk;
wire pmu_tim2_p0rst_b;
wire pmu_tim3_p1clk;
wire pmu_tim3_p1rst_b;
wire pmu_tim4_p0clk;
wire pmu_tim4_p0rst_b;
wire pmu_tim5_p1clk;
wire pmu_tim5_p1rst_b;
wire pmu_tim6_p0clk;
wire pmu_tim6_p0rst_b;
wire pmu_tim7_p1clk;
wire pmu_tim7_p1rst_b;
wire pmu_usi0_p0clk;
wire pmu_usi0_p0rst_b;
wire pmu_usi1_p1clk;
wire pmu_usi1_p1rst_b;
wire pmu_usi2_p0clk;
wire pmu_usi2_p0rst_b;
wire pmu_wdt_p0clk;
wire pmu_wdt_p0rst_b;
wire pmu_wic_intr;
wire [31:0] prdata;
wire soc_hclk;
wire soc_hrst_b;
wire soc_p0clk;
wire soc_p0rst_b;
wire soc_p1clk;
wire soc_p1rst_b;
wire soc_s3clk;
wire soc_s3rst_b;
wire sys_rst_b;
wire wdt_pmu_rst_b;
assign pmu_cpu_dfs_req = 1'b0;
assign pmu_wic_intr = 1'b0;
assign prdata[31:0] = 32'h0;
assign pmu_apb0_pclk_en = 1'b1;
assign pmu_apb1_pclk_en = 1'b1;
assign pmu_rtc_clk = els_pmu_clk;
assign soc_hclk = ehs_pmu_clk;
assign soc_p0clk = ehs_pmu_clk;
assign soc_p1clk = ehs_pmu_clk;
assign soc_s3clk = ehs_pmu_clk;
assign dft_clk = ehs_pmu_clk;
assign sys_rst_b = pad_mcurst_b & wdt_pmu_rst_b;
assign soc_hrst_b = sys_rst_b;
assign soc_p0rst_b = sys_rst_b;
assign soc_p1rst_b = sys_rst_b;
assign soc_s3rst_b = sys_rst_b;
assign pad_core_clk = soc_hclk;
assign pad_core_ctim_refclk = soc_hclk;
assign pmu_dmac0_hclk = soc_hclk;
assign pmu_imemdummy0_hclk = soc_hclk;
assign pmu_dmemdummy0_hclk = soc_hclk;
assign pmu_dummy0_hclk = soc_hclk;
assign pmu_dummy1_hclk = soc_hclk;
assign pmu_dummy2_hclk = soc_hclk;
assign pmu_dummy3_hclk = soc_hclk;
assign pmu_hmain0_hclk = soc_hclk;
assign pmu_lsbus_hclk = soc_hclk;
assign pmu_mdummy0_hclk = soc_hclk;
assign pmu_mdummy1_hclk = soc_hclk;
assign pmu_mdummy2_hclk = soc_hclk;
assign pmu_smc_hclk = soc_hclk;
assign pmu_apb0_s3clk = soc_s3clk;
assign pmu_apb1_s3clk = soc_s3clk;
assign pmu_sub3_s3clk = soc_s3clk;
assign pmu_dummy0_s3clk = soc_s3clk;
assign pmu_dummy1_s3clk = soc_s3clk;
assign pmu_dummy2_s3clk = soc_s3clk;
assign pmu_dummy3_s3clk = soc_s3clk;
assign pmu_tim0_p0clk = soc_p0clk;
assign pmu_tim2_p0clk = soc_p0clk;
assign pmu_tim4_p0clk = soc_p0clk;
assign pmu_tim6_p0clk = soc_p0clk;
assign pmu_usi0_p0clk = soc_p0clk;
assign pmu_usi2_p0clk = soc_p0clk;
assign pmu_dummy1_p0clk = soc_p0clk;
assign pmu_wdt_p0clk = soc_p0clk;
assign pmu_dummy2_p0clk = soc_p0clk;
assign pmu_dummy3_p0clk = soc_p0clk;
assign pmu_dummy4_p0clk = soc_p0clk;
assign pmu_dummy5_p0clk = soc_p0clk;
assign pmu_pwm_p0clk = soc_p0clk;
assign pmu_dummy7_p0clk = soc_p0clk;
assign pmu_dummy8_p0clk = soc_p0clk;
assign pmu_dummy9_p0clk = soc_p0clk;
assign pmu_tim1_p1clk = soc_p1clk;
assign pmu_tim3_p1clk = soc_p1clk;
assign pmu_tim5_p1clk = soc_p1clk;
assign pmu_tim7_p1clk = soc_p1clk;
assign pmu_usi1_p1clk = soc_p1clk;
assign pmu_gpio_p1clk = soc_p1clk;
assign pmu_rtc_p1clk = soc_p1clk;
assign pmu_dummy1_p1clk = soc_p1clk;
assign pmu_dummy2_p1clk = soc_p1clk;
assign pmu_dummy3_p1clk = soc_p1clk;
assign pmu_dummy4_p1clk = soc_p1clk;
assign pmu_dummy5_p1clk = soc_p1clk;
assign pmu_dummy6_p1clk = soc_p1clk;
assign pmu_dummy7_p1clk = soc_p1clk;
assign pmu_dummy8_p1clk = soc_p1clk;
assign pad_core_rst_b = soc_hrst_b;
assign pmu_dmac0_hrst_b = soc_hrst_b;
assign pmu_imemdummy0_hrst_b = soc_hrst_b;
assign pmu_dmemdummy0_hrst_b = soc_hrst_b;
assign pmu_dummy0_hrst_b = soc_hrst_b;
assign pmu_dummy1_hrst_b = soc_hrst_b;
assign pmu_dummy2_hrst_b = soc_hrst_b;
assign pmu_dummy3_hrst_b = soc_hrst_b;
assign pmu_hmain0_hrst_b = soc_hrst_b;
assign pmu_lsbus_hrst_b = soc_hrst_b;
assign pmu_mdummy0_hrst_b = soc_hrst_b;
assign pmu_mdummy1_hrst_b = soc_hrst_b;
assign pmu_mdummy2_hrst_b = soc_hrst_b;
assign pmu_smc_hrst_b = soc_hrst_b;
assign pmu_apb0_s3rst_b = soc_s3rst_b;
assign pmu_apb1_s3rst_b = soc_s3rst_b;
assign pmu_dummy0_s3rst_b = soc_s3rst_b;
assign pmu_dummy1_s3rst_b = soc_s3rst_b;
assign pmu_dummy2_s3rst_b = soc_s3rst_b;
assign pmu_dummy3_s3rst_b = soc_s3rst_b;
assign pmu_sub3_s3rst_b = soc_s3rst_b;
assign pmu_dummy1_p0rst_b = soc_p0rst_b;
assign pmu_wdt_p0rst_b = soc_p0rst_b;
assign pmu_dummy2_p0rst_b = soc_p0rst_b;
assign pmu_dummy3_p0rst_b = soc_p0rst_b;
assign pmu_dummy4_p0rst_b = soc_p0rst_b;
assign pmu_dummy5_p0rst_b = soc_p0rst_b;
assign pmu_pwm_p0rst_b = soc_p0rst_b;
assign pmu_dummy7_p0rst_b = soc_p0rst_b;
assign pmu_dummy8_p0rst_b = soc_p0rst_b;
assign pmu_dummy9_p0rst_b = soc_p0rst_b;
assign pmu_tim0_p0rst_b = soc_p0rst_b;
assign pmu_tim2_p0rst_b = soc_p0rst_b;
assign pmu_tim4_p0rst_b = soc_p0rst_b;
assign pmu_tim6_p0rst_b = soc_p0rst_b;
assign pmu_usi0_p0rst_b = soc_p0rst_b;
assign pmu_usi2_p0rst_b = soc_p0rst_b;
assign pmu_rtc_p1rst_b = soc_p1rst_b;
assign pmu_dummy1_p1rst_b = soc_p1rst_b;
assign pmu_dummy2_p1rst_b = soc_p1rst_b;
assign pmu_dummy3_p1rst_b = soc_p1rst_b;
assign pmu_dummy4_p1rst_b = soc_p1rst_b;
assign pmu_dummy5_p1rst_b = soc_p1rst_b;
assign pmu_dummy6_p1rst_b = soc_p1rst_b;
assign pmu_dummy7_p1rst_b = soc_p1rst_b;
assign pmu_dummy8_p1rst_b = soc_p1rst_b;
assign pmu_gpio_p1rst_b = soc_p1rst_b;
assign pmu_tim1_p1rst_b = soc_p1rst_b;
assign pmu_tim3_p1rst_b = soc_p1rst_b;
assign pmu_tim5_p1rst_b = soc_p1rst_b;
assign pmu_tim7_p1rst_b = soc_p1rst_b;
assign pmu_usi1_p1rst_b = soc_p1rst_b;
endmodule |
module core_top(
apb0_dummy1_intr,
apb0_dummy2_intr,
apb0_dummy3_intr,
apb0_dummy4_intr,
apb0_dummy5_intr,
apb0_dummy7_intr,
apb0_dummy8_intr,
apb0_dummy9_intr,
apb1_dummy1_intr,
apb1_dummy2_intr,
apb1_dummy3_intr,
apb1_dummy4_intr,
apb1_dummy5_intr,
apb1_dummy6_intr,
apb1_dummy7_intr,
apb1_dummy8_intr,
bist0_mode,
cpu_hmain0_m0_haddr,
cpu_hmain0_m0_hburst,
cpu_hmain0_m0_hprot,
cpu_hmain0_m0_hsize,
cpu_hmain0_m0_htrans,
cpu_hmain0_m0_hwdata,
cpu_hmain0_m0_hwrite,
cpu_hmain0_m1_haddr,
cpu_hmain0_m1_hburst,
cpu_hmain0_m1_hprot,
cpu_hmain0_m1_hsize,
cpu_hmain0_m1_htrans,
cpu_hmain0_m1_hwdata,
cpu_hmain0_m1_hwrite,
cpu_hmain0_m2_haddr,
cpu_hmain0_m2_hburst,
cpu_hmain0_m2_hprot,
cpu_hmain0_m2_hsize,
cpu_hmain0_m2_htrans,
cpu_hmain0_m2_hwdata,
cpu_hmain0_m2_hwrite,
cpu_padmux_jtg_tms_o,
cpu_padmux_jtg_tms_oe,
cpu_pmu_dfs_ack,
cpu_pmu_sleep_b,
dft_clk,
dmac0_wic_intr,
gpio_wic_intr,
hmain0_cpu_m0_hrdata,
hmain0_cpu_m0_hready,
hmain0_cpu_m0_hresp,
hmain0_cpu_m1_hrdata,
hmain0_cpu_m1_hready,
hmain0_cpu_m1_hresp,
hmain0_cpu_m2_hrdata,
hmain0_cpu_m2_hready,
hmain0_cpu_m2_hresp,
lsbus_dummy0_intr,
lsbus_dummy1_intr,
lsbus_dummy2_intr,
lsbus_dummy3_intr,
main_dmemdummy0_intr,
main_dummy0_intr,
main_dummy1_intr,
main_dummy2_intr,
main_dummy3_intr,
main_imemdummy0_intr,
pad_core_clk,
pad_core_ctim_refclk,
pad_core_rst_b,
padmux_cpu_jtg_tclk,
padmux_cpu_jtg_tms_i,
pmu_cpu_dfs_req,
pmu_wic_intr,
pwm_wic_intr,
rtc_wic_intr,
scan_en,
scan_mode,
test_mode,
tim0_wic_intr,
tim1_wic_intr,
tim2_wic_intr,
tim3_wic_intr,
tim4_wic_intr,
tim5_wic_intr,
tim6_wic_intr,
tim7_wic_intr,
usi0_wic_intr,
usi1_wic_intr,
usi2_wic_intr,
wdt_wic_intr
);
input apb0_dummy1_intr;
input apb0_dummy2_intr;
input apb0_dummy3_intr;
input apb0_dummy4_intr;
input apb0_dummy5_intr;
input apb0_dummy7_intr;
input apb0_dummy8_intr;
input apb0_dummy9_intr;
input apb1_dummy1_intr;
input apb1_dummy2_intr;
input apb1_dummy3_intr;
input apb1_dummy4_intr;
input apb1_dummy5_intr;
input apb1_dummy6_intr;
input apb1_dummy7_intr;
input apb1_dummy8_intr;
input bist0_mode;
input dft_clk;
input dmac0_wic_intr;
input gpio_wic_intr;
input [31:0] hmain0_cpu_m0_hrdata;
input hmain0_cpu_m0_hready;
input [1 :0] hmain0_cpu_m0_hresp;
input [31:0] hmain0_cpu_m1_hrdata;
input hmain0_cpu_m1_hready;
input [1 :0] hmain0_cpu_m1_hresp;
input [31:0] hmain0_cpu_m2_hrdata;
input hmain0_cpu_m2_hready;
input [1 :0] hmain0_cpu_m2_hresp;
input lsbus_dummy0_intr;
input lsbus_dummy1_intr;
input lsbus_dummy2_intr;
input lsbus_dummy3_intr;
input main_dmemdummy0_intr;
input main_dummy0_intr;
input main_dummy1_intr;
input main_dummy2_intr;
input main_dummy3_intr;
input main_imemdummy0_intr;
input pad_core_clk;
input pad_core_ctim_refclk;
input pad_core_rst_b;
input padmux_cpu_jtg_tclk;
input padmux_cpu_jtg_tms_i;
input pmu_cpu_dfs_req;
input pmu_wic_intr;
input pwm_wic_intr;
input rtc_wic_intr;
input scan_en;
input scan_mode;
input test_mode;
input [1 :0] tim0_wic_intr;
input [1 :0] tim1_wic_intr;
input [1 :0] tim2_wic_intr;
input [1 :0] tim3_wic_intr;
input [1 :0] tim4_wic_intr;
input [1 :0] tim5_wic_intr;
input [1 :0] tim6_wic_intr;
input [1 :0] tim7_wic_intr;
input usi0_wic_intr;
input usi1_wic_intr;
input usi2_wic_intr;
input wdt_wic_intr;
output [31:0] cpu_hmain0_m0_haddr;
output [2 :0] cpu_hmain0_m0_hburst;
output [3 :0] cpu_hmain0_m0_hprot;
output [2 :0] cpu_hmain0_m0_hsize;
output [1 :0] cpu_hmain0_m0_htrans;
output [31:0] cpu_hmain0_m0_hwdata;
output cpu_hmain0_m0_hwrite;
output [31:0] cpu_hmain0_m1_haddr;
output [2 :0] cpu_hmain0_m1_hburst;
output [3 :0] cpu_hmain0_m1_hprot;
output [2 :0] cpu_hmain0_m1_hsize;
output [1 :0] cpu_hmain0_m1_htrans;
output [31:0] cpu_hmain0_m1_hwdata;
output cpu_hmain0_m1_hwrite;
output [31:0] cpu_hmain0_m2_haddr;
output [2 :0] cpu_hmain0_m2_hburst;
output [3 :0] cpu_hmain0_m2_hprot;
output [2 :0] cpu_hmain0_m2_hsize;
output [1 :0] cpu_hmain0_m2_htrans;
output [31:0] cpu_hmain0_m2_hwdata;
output cpu_hmain0_m2_hwrite;
output cpu_padmux_jtg_tms_o;
output cpu_padmux_jtg_tms_oe;
output cpu_pmu_dfs_ack;
output cpu_pmu_sleep_b;
reg cpu_pmu_dfs_ack;
reg cpu_pmu_srst_b;
wire apb0_dummy1_intr;
wire apb0_dummy2_intr;
wire apb0_dummy3_intr;
wire apb0_dummy4_intr;
wire apb0_dummy5_intr;
wire apb0_dummy7_intr;
wire apb0_dummy8_intr;
wire apb0_dummy9_intr;
wire apb1_dummy1_intr;
wire apb1_dummy2_intr;
wire apb1_dummy3_intr;
wire apb1_dummy4_intr;
wire apb1_dummy5_intr;
wire apb1_dummy6_intr;
wire apb1_dummy7_intr;
wire apb1_dummy8_intr;
wire bist0_mode;
wire [31:0] biu_pad_haddr;
wire [2 :0] biu_pad_hburst;
wire [3 :0] biu_pad_hprot;
wire [2 :0] biu_pad_hsize;
wire [1 :0] biu_pad_htrans;
wire [31:0] biu_pad_hwdata;
wire biu_pad_hwrite;
wire biu_pad_vec_redrct;
wire clk_en;
wire core_pad_jdb_ack_b;
wire [1 :0] core_pad_jdb_pm;
wire core_pad_jtg_tap_on;
wire core_pad_wakeup_b;
wire core_sysio_pad_dbg_b;
wire core_sysio_pad_idly4_b;
wire core_sysio_pad_ipend_b;
wire [31:0] cp0_pad_mintstatus;
wire [31:0] cp0_pad_mstatus;
wire [31:0] cp0_pad_psr;
wire [31:0] cpu_hmain0_m0_haddr;
wire [2 :0] cpu_hmain0_m0_hburst;
wire [3 :0] cpu_hmain0_m0_hprot;
wire [2 :0] cpu_hmain0_m0_hsize;
wire [1 :0] cpu_hmain0_m0_htrans;
wire [31:0] cpu_hmain0_m0_hwdata;
wire cpu_hmain0_m0_hwrite;
wire [31:0] cpu_hmain0_m1_haddr;
wire [2 :0] cpu_hmain0_m1_hburst;
wire [3 :0] cpu_hmain0_m1_hprot;
wire [2 :0] cpu_hmain0_m1_hsize;
wire [1 :0] cpu_hmain0_m1_htrans;
wire [31:0] cpu_hmain0_m1_hwdata;
wire cpu_hmain0_m1_hwrite;
wire [31:0] cpu_hmain0_m2_haddr;
wire [2 :0] cpu_hmain0_m2_hburst;
wire [3 :0] cpu_hmain0_m2_hprot;
wire [2 :0] cpu_hmain0_m2_hsize;
wire [1 :0] cpu_hmain0_m2_htrans;
wire [31:0] cpu_hmain0_m2_hwdata;
wire cpu_hmain0_m2_hwrite;
wire cpu_pad_dfs_ack;
wire cpu_padmux_jtg_tms_o;
wire cpu_padmux_jtg_tms_oe;
wire cpu_pmu_sleep_b;
wire cpu_retire_vld;
wire cpu_wic_ctim_int_vld;
wire ctim_pad_int_vld;
wire [31:0] dahbl_pad_haddr;
wire [2 :0] dahbl_pad_hburst;
wire [3 :0] dahbl_pad_hprot;
wire [2 :0] dahbl_pad_hsize;
wire [1 :0] dahbl_pad_htrans;
wire [31:0] dahbl_pad_hwdata;
wire dahbl_pad_hwrite;
wire dft_clk;
wire dlite_clk_en;
wire dmac0_wic_intr;
wire gpio_wic_intr;
wire had_pad_jdb_ack_b;
wire [1 :0] had_pad_jdb_pm;
wire had_pad_jtg_tap_on;
wire had_pad_jtg_tms_o;
wire had_pad_jtg_tms_oe;
wire had_pad_wakeup_req_b;
wire [31:0] hmain0_cpu_m0_hrdata;
wire hmain0_cpu_m0_hready;
wire [1 :0] hmain0_cpu_m0_hresp;
wire [31:0] hmain0_cpu_m1_hrdata;
wire hmain0_cpu_m1_hready;
wire [1 :0] hmain0_cpu_m1_hresp;
wire [31:0] hmain0_cpu_m2_hrdata;
wire hmain0_cpu_m2_hready;
wire [1 :0] hmain0_cpu_m2_hresp;
wire [31:0] iahbl_pad_haddr;
wire [2 :0] iahbl_pad_hburst;
wire [3 :0] iahbl_pad_hprot;
wire [2 :0] iahbl_pad_hsize;
wire [1 :0] iahbl_pad_htrans;
wire [31:0] iahbl_pad_hwdata;
wire iahbl_pad_hwrite;
wire iahbl_pad_vec_redrct;
wire ilite_clk_en;
wire [63:0] ip_cpu_int_cfg;
wire [63:0] ip_cpu_int_vld;
wire [31:0] iu_pad_gpr_data;
wire [4 :0] iu_pad_gpr_index;
wire iu_pad_gpr_we;
wire iu_pad_inst_retire;
wire iu_pad_inst_split;
wire [31:0] iu_pad_retire_pc;
wire lsbus_dummy0_intr;
wire lsbus_dummy1_intr;
wire lsbus_dummy2_intr;
wire lsbus_dummy3_intr;
wire main_dmemdummy0_intr;
wire main_dummy0_intr;
wire main_dummy1_intr;
wire main_dummy2_intr;
wire main_dummy3_intr;
wire main_imemdummy0_intr;
wire [31:0] pad_biu_hrdata;
wire pad_biu_hready;
wire pad_biu_hresp;
wire [11:0] pad_bmu_iahbl_base;
wire [11:0] pad_bmu_iahbl_mask;
wire [63:0] pad_clic_int_cfg;
wire [63:0] pad_clic_int_vld;
wire pad_core_clk;
wire pad_core_ctim_refclk;
wire pad_core_jtg_tclk;
wire pad_core_rst_b;
wire pad_cpu_dfs_req;
wire pad_cpu_ext_int_b;
wire pad_cpu_rst_b;
wire [25:0] pad_ctim_calib;
wire pad_ctim_refclk;
wire [31:0] pad_dahbl_hrdata;
wire pad_dahbl_hready;
wire pad_dahbl_hresp;
wire pad_dahbl_hsec;
wire pad_had_jdb_req_b;
wire pad_had_jtg_tap_en;
wire pad_had_jtg_tclk;
wire pad_had_jtg_tms_i;
wire pad_had_jtg_trst_b;
wire pad_had_rst_b;
wire [31:0] pad_iahbl_hrdata;
wire pad_iahbl_hready;
wire pad_iahbl_hresp;
wire pad_sysio_bigend_b;
wire [2 :0] pad_sysio_clkratio;
wire pad_sysio_dbgrq_b;
wire pad_sysio_endian_v2;
wire [63:0] pad_vic_int_cfg;
wire [63:0] pad_vic_int_vld;
wire pad_yy_bist_tst_en;
wire pad_yy_gate_clk_en_b;
wire pad_yy_scan_enable;
wire pad_yy_test_mode;
wire padmux_cpu_jtg_tclk;
wire padmux_cpu_jtg_tms_i;
wire pll_core_cpuclk;
wire pll_cpu_clk;
wire pmu_cpu_dfs_req;
wire pmu_wic_intr;
wire pwm_wic_intr;
wire rtc_wic_intr;
wire rtu_pad_inst_retire;
wire scan_en;
wire scan_mode;
wire sysio_pad_dbg_b;
wire sysio_pad_idly4_b;
wire sysio_pad_ipend_b;
wire [1 :0] sysio_pad_lpmd_b;
wire sysio_pad_srst;
wire sysio_pad_wakeup_b;
wire test_mode;
wire [1 :0] tim0_wic_intr;
wire [1 :0] tim1_wic_intr;
wire [1 :0] tim2_wic_intr;
wire [1 :0] tim3_wic_intr;
wire [1 :0] tim4_wic_intr;
wire [1 :0] tim5_wic_intr;
wire [1 :0] tim6_wic_intr;
wire [1 :0] tim7_wic_intr;
wire usi0_wic_intr;
wire usi1_wic_intr;
wire usi2_wic_intr;
wire wdt_wic_intr;
assign dlite_clk_en = 1'b1;
assign ilite_clk_en = 1'b1;
assign pad_core_jtg_tclk = test_mode ? dft_clk : padmux_cpu_jtg_tclk;
E902_20191018 CPU (
.biu_pad_haddr (biu_pad_haddr ),
.biu_pad_hburst (biu_pad_hburst ),
.biu_pad_hprot (biu_pad_hprot ),
.biu_pad_hsize (biu_pad_hsize ),
.biu_pad_htrans (biu_pad_htrans ),
.biu_pad_hwdata (biu_pad_hwdata ),
.biu_pad_hwrite (biu_pad_hwrite ),
.biu_pad_vec_redrct (biu_pad_vec_redrct ),
.clk_en (clk_en ),
.cp0_pad_mintstatus (cp0_pad_mintstatus ),
.cp0_pad_mstatus (cp0_pad_mstatus ),
.cp0_pad_psr (cp0_pad_psr ),
.cpu_pad_dfs_ack (cpu_pad_dfs_ack ),
.ctim_pad_int_vld (ctim_pad_int_vld ),
.had_pad_jdb_ack_b (had_pad_jdb_ack_b ),
.had_pad_jdb_pm (had_pad_jdb_pm ),
.had_pad_jtg_tap_on (had_pad_jtg_tap_on ),
.had_pad_jtg_tms_o (had_pad_jtg_tms_o ),
.had_pad_jtg_tms_oe (had_pad_jtg_tms_oe ),
.had_pad_wakeup_req_b (had_pad_wakeup_req_b),
.iahbl_pad_haddr (iahbl_pad_haddr ),
.iahbl_pad_hburst (iahbl_pad_hburst ),
.iahbl_pad_hprot (iahbl_pad_hprot ),
.iahbl_pad_hsize (iahbl_pad_hsize ),
.iahbl_pad_htrans (iahbl_pad_htrans ),
.iahbl_pad_hwdata (iahbl_pad_hwdata ),
.iahbl_pad_hwrite (iahbl_pad_hwrite ),
.iahbl_pad_vec_redrct (iahbl_pad_vec_redrct),
.iu_pad_gpr_data (iu_pad_gpr_data ),
.iu_pad_gpr_index (iu_pad_gpr_index ),
.iu_pad_gpr_we (iu_pad_gpr_we ),
.iu_pad_inst_retire (iu_pad_inst_retire ),
.iu_pad_inst_split (iu_pad_inst_split ),
.iu_pad_retire_pc (iu_pad_retire_pc ),
.pad_biu_hrdata (pad_biu_hrdata ),
.pad_biu_hready (pad_biu_hready ),
.pad_biu_hresp (pad_biu_hresp ),
.pad_bmu_iahbl_base (pad_bmu_iahbl_base ),
.pad_bmu_iahbl_mask (pad_bmu_iahbl_mask ),
.pad_clic_int_cfg (pad_clic_int_cfg ),
.pad_clic_int_vld (pad_clic_int_vld ),
.pad_cpu_dfs_req (pad_cpu_dfs_req ),
.pad_cpu_ext_int_b (pad_cpu_ext_int_b ),
.pad_cpu_rst_b (pad_cpu_rst_b ),
.pad_ctim_calib (pad_ctim_calib ),
.pad_ctim_refclk (pad_ctim_refclk ),
.pad_had_jdb_req_b (pad_had_jdb_req_b ),
.pad_had_jtg_tap_en (pad_had_jtg_tap_en ),
.pad_had_jtg_tclk (pad_had_jtg_tclk ),
.pad_had_jtg_tms_i (pad_had_jtg_tms_i ),
.pad_had_jtg_trst_b (pad_had_jtg_trst_b ),
.pad_had_rst_b (pad_had_rst_b ),
.pad_iahbl_hrdata (pad_iahbl_hrdata ),
.pad_iahbl_hready (pad_iahbl_hready ),
.pad_iahbl_hresp (pad_iahbl_hresp ),
.pad_sysio_bigend_b (pad_sysio_bigend_b ),
.pad_sysio_clkratio (pad_sysio_clkratio ),
.pad_sysio_endian_v2 (pad_sysio_endian_v2 ),
.pad_yy_gate_clk_en_b (pad_yy_gate_clk_en_b),
.pad_yy_test_mode (pad_yy_test_mode ),
.pll_core_cpuclk (pll_core_cpuclk ),
.sysio_pad_dbg_b (sysio_pad_dbg_b ),
.sysio_pad_ipend_b (sysio_pad_ipend_b ),
.sysio_pad_lpmd_b (sysio_pad_lpmd_b ),
.sysio_pad_srst (sysio_pad_srst ),
.sysio_pad_wakeup_b (sysio_pad_wakeup_b )
);
gated_clk_cell cpu_gated_clk (
.clk_in (pad_core_clk ),
.clk_out (pll_cpu_clk ),
.external_en (1'b1 ),
.global_en (1'b0 ),
.local_en (1'b0 ),
.module_en (1'b0 ),
.pad_yy_gate_clk_en_b (1'b0 ),
.pad_yy_test_mode (test_mode )
);
assign pad_cpu_dfs_req = pmu_cpu_dfs_req;
always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
cpu_pmu_dfs_ack <= 1'b0;
else
cpu_pmu_dfs_ack <= cpu_pad_dfs_ack;
end
always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b)
begin
if(!pad_cpu_rst_b)
cpu_pmu_srst_b <= 1'b1;
else
cpu_pmu_srst_b <= !sysio_pad_srst;
end
assign pll_core_cpuclk = pll_cpu_clk;
assign pad_cpu_rst_b = pad_core_rst_b;
assign clk_en = 1'b1;
assign pad_bmu_iahbl_base[11:0] = 12'h000;
assign pad_bmu_iahbl_mask[11:0] = 12'he00;
assign cpu_wic_ctim_int_vld = ctim_pad_int_vld;
assign cpu_pmu_sleep_b = & sysio_pad_lpmd_b[1:0];
assign pad_vic_int_cfg[63:0] = ip_cpu_int_cfg[63:0];
assign pad_vic_int_vld[63:0] = ip_cpu_int_vld[63:0];
assign core_pad_wakeup_b = sysio_pad_wakeup_b;
assign pad_yy_gate_clk_en_b = 1'b0;
assign pad_ctim_calib[25:0] = 26'h0;
assign pad_ctim_refclk = pad_core_ctim_refclk;
assign pad_had_jdb_req_b = 1'b1;
assign pad_sysio_bigend_b = 1'b1;
assign pad_sysio_clkratio[2:0] = 2'b0;
assign pad_sysio_dbgrq_b = 1'b1;
assign pad_yy_bist_tst_en = bist0_mode;
assign pad_yy_scan_enable = scan_en;
assign pad_yy_test_mode = scan_mode;
assign core_pad_jdb_ack_b = had_pad_jdb_ack_b;
assign core_pad_jdb_pm[1:0] = had_pad_jdb_pm[1:0];
assign core_sysio_pad_dbg_b = sysio_pad_dbg_b;
assign core_sysio_pad_idly4_b = sysio_pad_idly4_b;
assign core_sysio_pad_ipend_b = sysio_pad_ipend_b;
assign pad_had_jtg_tap_en = 1'b1;
assign pad_had_jtg_trst_b = pad_core_rst_b;
assign pad_had_jtg_tclk = pad_core_jtg_tclk;
assign pad_had_jtg_tms_i = padmux_cpu_jtg_tms_i;
assign core_pad_jtg_tap_on = had_pad_jtg_tap_on;
assign cpu_padmux_jtg_tms_o = had_pad_jtg_tms_o;
assign cpu_padmux_jtg_tms_oe = had_pad_jtg_tms_oe;
assign cpu_hmain0_m2_haddr[31:0] = biu_pad_haddr[31:0];
assign cpu_hmain0_m2_hburst[2:0] = biu_pad_hburst[2:0];
assign cpu_hmain0_m2_hprot[3:0] = biu_pad_hprot[3:0];
assign cpu_hmain0_m2_hsize[2:0] = biu_pad_hsize[2:0];
assign cpu_hmain0_m2_htrans[1:0] = biu_pad_htrans[1:0];
assign cpu_hmain0_m2_hwdata[31:0] = biu_pad_hwdata[31:0];
assign cpu_hmain0_m2_hwrite = biu_pad_hwrite;
assign pad_biu_hrdata[31:0] = hmain0_cpu_m2_hrdata[31:0];
assign pad_biu_hready = hmain0_cpu_m2_hready;
assign pad_biu_hresp = |hmain0_cpu_m2_hresp[1:0];
assign cpu_hmain0_m0_haddr[31:0] = iahbl_pad_haddr[31:0];
assign cpu_hmain0_m0_hburst[2:0] = iahbl_pad_hburst[2:0];
assign cpu_hmain0_m0_hprot[3:0] = iahbl_pad_hprot[3:0];
assign cpu_hmain0_m0_hsize[2:0] = iahbl_pad_hsize[2:0];
assign cpu_hmain0_m0_htrans[1:0] = iahbl_pad_htrans[1:0];
assign cpu_hmain0_m0_hwdata[31:0] = iahbl_pad_hwdata[31:0];
assign cpu_hmain0_m0_hwrite = iahbl_pad_hwrite;
assign pad_iahbl_hrdata[31:0] = hmain0_cpu_m0_hrdata[31:0];
assign pad_iahbl_hready = hmain0_cpu_m0_hready;
assign pad_iahbl_hresp = |hmain0_cpu_m0_hresp[1:0];
assign cpu_hmain0_m1_haddr[31:0] = dahbl_pad_haddr[31:0];
assign cpu_hmain0_m1_hburst[2:0] = dahbl_pad_hburst[2:0];
assign cpu_hmain0_m1_hprot[3:0] = dahbl_pad_hprot[3:0];
assign cpu_hmain0_m1_hsize[2:0] = dahbl_pad_hsize[2:0];
assign cpu_hmain0_m1_htrans[1:0] = dahbl_pad_htrans[1:0];
assign cpu_hmain0_m1_hwdata[31:0] = dahbl_pad_hwdata[31:0];
assign cpu_hmain0_m1_hwrite = dahbl_pad_hwrite;
assign pad_dahbl_hrdata[31:0] = hmain0_cpu_m1_hrdata[31:0];
assign pad_dahbl_hready = hmain0_cpu_m1_hready;
assign pad_dahbl_hresp = |hmain0_cpu_m1_hresp[1:0];
assign pad_dahbl_hsec = 1'b0;
assign cpu_retire_vld = rtu_pad_inst_retire;
assign ip_cpu_int_vld[6:0] = 1'b0;
assign ip_cpu_int_vld[7] = cpu_wic_ctim_int_vld;
assign ip_cpu_int_vld[15:8] = 8'b0;
assign ip_cpu_int_vld[16] = gpio_wic_intr;
assign ip_cpu_int_vld[18:17] = tim0_wic_intr[1:0];
assign ip_cpu_int_vld[20:19] = tim1_wic_intr[1:0];
assign ip_cpu_int_vld[22:21] = tim2_wic_intr[1:0];
assign ip_cpu_int_vld[24:23] = tim3_wic_intr[1:0];
assign ip_cpu_int_vld[25] = pwm_wic_intr;
assign ip_cpu_int_vld[26] = rtc_wic_intr;
assign ip_cpu_int_vld[27] = wdt_wic_intr;
assign ip_cpu_int_vld[28] = usi0_wic_intr;
assign ip_cpu_int_vld[29] = usi1_wic_intr;
assign ip_cpu_int_vld[30] = usi2_wic_intr;
assign ip_cpu_int_vld[31] = pmu_wic_intr;
assign ip_cpu_int_vld[32] = dmac0_wic_intr;
assign ip_cpu_int_vld[34:33] = tim4_wic_intr[1:0];
assign ip_cpu_int_vld[36:35] = tim5_wic_intr[1:0];
assign ip_cpu_int_vld[38:37] = tim6_wic_intr[1:0];
assign ip_cpu_int_vld[40:39] = tim7_wic_intr[1:0];
assign ip_cpu_int_vld[41] = main_imemdummy0_intr | main_dmemdummy0_intr;
assign ip_cpu_int_vld[42] = main_dummy0_intr;
assign ip_cpu_int_vld[43] = main_dummy1_intr;
assign ip_cpu_int_vld[44] = main_dummy2_intr;
assign ip_cpu_int_vld[45] = main_dummy3_intr;
assign ip_cpu_int_vld[46] = lsbus_dummy0_intr;
assign ip_cpu_int_vld[47] = lsbus_dummy1_intr;
assign ip_cpu_int_vld[48] = lsbus_dummy2_intr;
assign ip_cpu_int_vld[49] = lsbus_dummy3_intr;
assign ip_cpu_int_vld[50] = apb0_dummy1_intr;
assign ip_cpu_int_vld[51] = apb0_dummy2_intr;
assign ip_cpu_int_vld[52] = apb0_dummy3_intr;
assign ip_cpu_int_vld[53] = apb0_dummy4_intr;
assign ip_cpu_int_vld[54] = apb0_dummy5_intr;
assign ip_cpu_int_vld[55] = apb0_dummy7_intr;
assign ip_cpu_int_vld[56] = apb0_dummy8_intr;
assign ip_cpu_int_vld[57] = apb0_dummy9_intr;
assign ip_cpu_int_vld[58] = apb1_dummy1_intr;
assign ip_cpu_int_vld[59] = apb1_dummy2_intr;
assign ip_cpu_int_vld[60] = apb1_dummy3_intr;
assign ip_cpu_int_vld[61] = apb1_dummy4_intr;
assign ip_cpu_int_vld[62] = apb1_dummy5_intr | apb1_dummy7_intr;
assign ip_cpu_int_vld[63] = apb1_dummy6_intr | apb1_dummy8_intr;
assign ip_cpu_int_cfg[63:0] = 64'h0;
assign pad_clic_int_cfg[63:0] = pad_vic_int_cfg[63:0];
assign pad_clic_int_vld[63:0] = pad_vic_int_vld[63:0];
assign dahbl_pad_haddr[31:0] = 32'b0;
assign dahbl_pad_hburst[2 :0] = 3'b0;
assign dahbl_pad_hprot[3 :0] = 4'b0;
assign dahbl_pad_hsize[2 :0] = 3'b0;
assign dahbl_pad_htrans[1 :0] = 2'b0;
assign dahbl_pad_hwdata[31:0] = 32'b0;
assign dahbl_pad_hwrite = 1'b0;
assign pad_cpu_ext_int_b = 1'b1;
assign pad_had_rst_b = pad_cpu_rst_b;
assign pad_sysio_endian_v2 = 1'b0;
assign sysio_pad_idly4_b = 1'b1;
assign rtu_pad_inst_retire = 1'b0;
endmodule |
module sms_bank_64k_top(
big_endian_b,
mem_haddr,
mem_hclk,
mem_hprot,
mem_hrdata,
mem_hready,
mem_hready_resp,
mem_hresp,
mem_hrst_b,
mem_hsel,
mem_hsize,
mem_htrans,
mem_hwdata,
mem_hwrite,
region_rd_deny_flag,
region_wr_deny_flag,
sms_idle0
);
input big_endian_b;
input [31:0] mem_haddr;
input mem_hclk;
input [3 :0] mem_hprot;
input mem_hready;
input mem_hrst_b;
input mem_hsel;
input [2 :0] mem_hsize;
input [1 :0] mem_htrans;
input [31:0] mem_hwdata;
input mem_hwrite;
input region_rd_deny_flag;
input region_wr_deny_flag;
output [31:0] mem_hrdata;
output mem_hready_resp;
output [1 :0] mem_hresp;
output sms_idle0;
reg rd_deny_resp;
reg rd_deny_resp_2_cycle;
reg wr_deny_resp;
reg wr_deny_resp_2_cycle;
wire a_act_burst;
wire a_nonseq;
wire a_seq;
wire big_endian_b;
wire deny_hready_resp;
wire [1 :0] deny_hresp;
wire [31:0] mem_haddr;
wire mem_hclk;
wire [3 :0] mem_hprot;
wire [31:0] mem_hrdata;
wire mem_hready;
wire mem_hready_resp;
wire [1 :0] mem_hresp;
wire mem_hrst_b;
wire mem_hsel;
wire mem_hsel_deny;
wire [2 :0] mem_hsize;
wire [1 :0] mem_htrans;
wire [1 :0] mem_htrans_deny;
wire [31:0] mem_hwdata;
wire mem_hwrite;
wire [15:0] ram_addr;
wire [31:0] ram_rdata;
wire ram_sel;
wire [2 :0] ram_size;
wire [31:0] ram_wdata;
wire ram_write;
wire region_rd_deny_flag;
wire region_wr_deny_flag;
wire [3 :0] resp_cfg;
wire sms_idle0;
parameter NONSEQ = 2'b10;
parameter SEQ = 2'b11;
parameter ERROR = 2'b01;
assign a_nonseq = mem_htrans[1:0] == NONSEQ;
assign a_seq = mem_htrans[1:0] == SEQ;
assign a_act_burst = (a_nonseq || a_seq) && mem_hsel && mem_hready;
assign mem_hsel_deny =( (a_act_burst&mem_hwrite®ion_wr_deny_flag) |
(a_act_burst&(~mem_hwrite)®ion_rd_deny_flag) )
? 1'b0 : mem_hsel;
assign mem_htrans_deny[1:0] =( (a_act_burst&mem_hwrite®ion_wr_deny_flag) |
(a_act_burst&(~mem_hwrite)®ion_rd_deny_flag) )
? 2'b0 : mem_htrans[1:0];
always @(posedge mem_hclk or negedge mem_hrst_b)
begin
if(!mem_hrst_b) begin
wr_deny_resp <= 1'b0;
end
else if(wr_deny_resp && wr_deny_resp_2_cycle) begin
wr_deny_resp <= 1'b0;
end
else if(a_act_burst && mem_hwrite && region_wr_deny_flag) begin
wr_deny_resp <= 1'b1;
end
end
always @(posedge mem_hclk or negedge mem_hrst_b)
begin
if(!mem_hrst_b) begin
wr_deny_resp_2_cycle <= 1'b0;
end
else if(wr_deny_resp && wr_deny_resp_2_cycle) begin
wr_deny_resp_2_cycle <= 1'b0;
end
else if(wr_deny_resp) begin
wr_deny_resp_2_cycle <= 1'b1;
end
end
always @(posedge mem_hclk or negedge mem_hrst_b)
begin
if(!mem_hrst_b) begin
rd_deny_resp <= 1'b0;
end
else if(rd_deny_resp && rd_deny_resp_2_cycle) begin
rd_deny_resp <= 1'b0;
end
else if(a_act_burst && (!mem_hwrite) && region_rd_deny_flag) begin
rd_deny_resp <= 1'b1;
end
end
always @(posedge mem_hclk or negedge mem_hrst_b)
begin
if(!mem_hrst_b) begin
rd_deny_resp_2_cycle <= 1'b0;
end
else if(rd_deny_resp && rd_deny_resp_2_cycle) begin
rd_deny_resp_2_cycle <= 1'b0;
end
else if(rd_deny_resp) begin
rd_deny_resp_2_cycle <= 1'b1;
end
end
assign mem_hready_resp = rd_deny_resp ? rd_deny_resp_2_cycle :
(wr_deny_resp ? wr_deny_resp_2_cycle : deny_hready_resp);
assign mem_hresp[1:0] = rd_deny_resp ? ERROR : (wr_deny_resp ? ERROR : deny_hresp);
sms_sms_ahbs_bk2 x_sms_sms_ahbs (
.ahbs_harb_hrdata (mem_hrdata ),
.ahbs_harb_hready (deny_hready_resp ),
.ahbs_harb_hresp (deny_hresp ),
.harb_ahbs_hsel (mem_hsel_deny ),
.harb_xx_haddr (mem_haddr ),
.harb_xx_hready (mem_hready ),
.harb_xx_hsize (mem_hsize ),
.harb_xx_htrans (mem_htrans_deny ),
.harb_xx_hwdata (mem_hwdata ),
.harb_xx_hwrite (mem_hwrite ),
.i_sys_hclk (mem_hclk ),
.i_sys_rst_b (mem_hrst_b ),
.little_endian_trans (big_endian_b ),
.mem_hprot (mem_hprot ),
.ram_addr (ram_addr ),
.ram_idle (sms_idle0 ),
.ram_rdata (ram_rdata ),
.ram_sel (ram_sel ),
.ram_size (ram_size ),
.ram_wdata (ram_wdata ),
.ram_write (ram_write ),
.resp_cfg (resp_cfg )
);
sms_sram_bk2 x_sms_sram (
.hrst_b (mem_hrst_b),
.ram_addr (ram_addr ),
.ram_clk (mem_hclk ),
.ram_rdata (ram_rdata ),
.ram_sel (ram_sel ),
.ram_size (ram_size ),
.ram_wdata (ram_wdata ),
.ram_write (ram_write )
);
assign resp_cfg[3:0] = 4'b1000;
endmodule |
module sms_sms_ahbs_bk2(
ahbs_harb_hrdata,
ahbs_harb_hready,
ahbs_harb_hresp,
harb_ahbs_hsel,
harb_xx_haddr,
harb_xx_hready,
harb_xx_hsize,
harb_xx_htrans,
harb_xx_hwdata,
harb_xx_hwrite,
i_sys_hclk,
i_sys_rst_b,
little_endian_trans,
mem_hprot,
ram_addr,
ram_idle,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write,
resp_cfg
);
input harb_ahbs_hsel;
input [31:0] harb_xx_haddr;
input harb_xx_hready;
input [2 :0] harb_xx_hsize;
input [1 :0] harb_xx_htrans;
input [31:0] harb_xx_hwdata;
input harb_xx_hwrite;
input i_sys_hclk;
input i_sys_rst_b;
input little_endian_trans;
input [3 :0] mem_hprot;
input [31:0] ram_rdata;
input [3 :0] resp_cfg;
output [31:0] ahbs_harb_hrdata;
output ahbs_harb_hready;
output [1 :0] ahbs_harb_hresp;
output [15:0] ram_addr;
output ram_idle;
output ram_sel;
output [2 :0] ram_size;
output [31:0] ram_wdata;
output ram_write;
reg ahbs_harb_hready_s;
reg [1 :0] ahbs_harb_hresp;
reg harb_ahbs_hsel_r;
reg [15:0] harb_xx_haddr_r;
reg [2 :0] harb_xx_hsize_r;
reg read_after_write_access;
reg rty_first;
reg rty_flag;
reg [15:0] w_ram_addr_tmp;
reg w_ram_sel_tmp;
reg [2 :0] w_ram_size_tmp;
reg w_ram_write_tmp;
wire a_act_burst;
wire a_byte;
wire a_halfword;
wire a_nonseq;
wire a_seq;
wire a_word;
wire ahbs_harb_hready;
wire harb_ahbs_hsel;
wire [31:0] harb_xx_haddr;
wire harb_xx_hready;
wire [2 :0] harb_xx_hsize;
wire [1 :0] harb_xx_htrans;
wire harb_xx_hwrite;
wire hready_s;
wire i_sys_hclk;
wire i_sys_rst_b;
wire [15:0] r_ram_addr;
wire r_ram_sel;
wire [2 :0] r_ram_size;
wire r_ram_write;
wire [15:0] ram_addr;
wire ram_idle;
wire [31:0] ram_rdata;
wire ram_sel;
wire [2 :0] ram_size;
wire [31:0] ram_wdata;
wire ram_write;
wire [31:0] reg_slave_rdata;
wire [3 :0] resp_cfg;
wire [31:0] slave_reg_wdata_t;
wire [1 :0] sms_resp;
wire [15:0] w_ram_addr;
wire w_ram_sel;
wire [2 :0] w_ram_size;
wire w_ram_write;
parameter REG_NUM = 64;
parameter BIT_WIDTH = 16;
parameter NONSEQ = 2'b10;
parameter SEQ = 2'b11;
parameter[2:0] BYTE = 3'b000,
HALFWORD = 3'b001,
WORD = 3'b010;
parameter[1:0] OKAY = 2'b00,
ERROR = 2'b01,
RETRY = 2'b10;
assign a_nonseq = harb_xx_htrans[1:0] == NONSEQ;
assign a_seq = harb_xx_htrans[1:0] == SEQ;
always @( posedge i_sys_hclk or negedge i_sys_rst_b)
begin
if(!i_sys_rst_b)
harb_xx_hsize_r[2:0] <= 3'b0;
else if(harb_xx_hready)
harb_xx_hsize_r[2:0] <= harb_xx_hsize[2:0];
else
harb_xx_hsize_r[2:0] <= harb_xx_hsize_r[2:0];
end
assign a_byte = (harb_xx_hsize_r[2:0] == BYTE);
assign a_halfword = (harb_xx_hsize_r[2:0] == HALFWORD);
assign a_word = (harb_xx_hsize_r[2:0] == WORD);
assign a_act_burst = ( a_nonseq || a_seq ) & harb_ahbs_hsel & harb_xx_hready;
always @(posedge i_sys_hclk or negedge i_sys_rst_b)
begin
if(!i_sys_rst_b)
harb_ahbs_hsel_r <= 1'b0;
else if(harb_ahbs_hsel)
harb_ahbs_hsel_r <= 1'b1;
else if(ahbs_harb_hready)
harb_ahbs_hsel_r <= 1'b0;
end
always @( posedge i_sys_hclk or negedge i_sys_rst_b)
begin
if(!i_sys_rst_b)
harb_xx_haddr_r[BIT_WIDTH-1:0] <= {BIT_WIDTH{1'b0}};
else if(ahbs_harb_hready)
harb_xx_haddr_r[BIT_WIDTH-1:0] <= harb_xx_haddr[BIT_WIDTH-1:0];
else
harb_xx_haddr_r[BIT_WIDTH-1:0] <= harb_xx_haddr_r[BIT_WIDTH-1:0];
end
reg [31:0] ahbs_harb_hrdata;
reg [31:0] slave_reg_wdata;
always @(little_endian_trans
or harb_ahbs_hsel_r
or a_byte
or a_halfword
or a_word
or reg_slave_rdata[31:0]
or harb_xx_haddr_r[1:0]
or harb_xx_hwdata[31:0])
begin
if(little_endian_trans & harb_ahbs_hsel_r)
begin
ahbs_harb_hrdata[31:0] = reg_slave_rdata[31:0];
slave_reg_wdata[31:0] = harb_xx_hwdata[31:0];
end
else if (~little_endian_trans & harb_ahbs_hsel_r)
begin
ahbs_harb_hrdata[31:0] = 32'h0;
slave_reg_wdata[31:0] = 32'h0;
case(1'b1)
a_byte :
begin
if(~|harb_xx_haddr_r[1:0])
begin
ahbs_harb_hrdata[31:0] = {reg_slave_rdata[7:0], 24'h0};
slave_reg_wdata[31:0] = {24'h0, harb_xx_hwdata[31:24]};
end
else if(harb_xx_haddr_r[1:0] == 2'b01)
begin
ahbs_harb_hrdata[31:0] = {8'h0, reg_slave_rdata[15:8], 16'h0};
slave_reg_wdata[31:0] = {16'h0, harb_xx_hwdata[23:16],8'h0};
end
else if(harb_xx_haddr_r[1:0] == 2'b10)
begin
ahbs_harb_hrdata[31:0] = {16'h0, reg_slave_rdata[23:16], 8'h0};
slave_reg_wdata[31:0] = {8'h0, harb_xx_hwdata[15:8],16'h0};
end
else
begin
ahbs_harb_hrdata[31:0] = {24'h0,reg_slave_rdata[31:24]};
slave_reg_wdata[31:0] = {harb_xx_hwdata[7:0],24'h0};
end
end
a_halfword :
begin
if(~|harb_xx_haddr_r[1:0])
begin
ahbs_harb_hrdata[31:0] = {reg_slave_rdata[15:0], 16'h0};
slave_reg_wdata[31:0] = {16'h0, harb_xx_hwdata[31:16]};
end
else if(harb_xx_haddr_r[1:0] == 2'b10)
begin
ahbs_harb_hrdata[31:0] = {16'h0, reg_slave_rdata[31:16]};
slave_reg_wdata[31:0] = {harb_xx_hwdata[15:0],16'h0};
end
end
a_word :
begin
ahbs_harb_hrdata[31:0] = reg_slave_rdata[31:0];
slave_reg_wdata[31:0] = harb_xx_hwdata[31:0];
end
endcase
end
else
begin
ahbs_harb_hrdata[31:0] = reg_slave_rdata[31:0];
slave_reg_wdata[31:0] = harb_xx_hwdata[31:0];
end
end
`ifdef RAM_USAGE
assign slave_reg_wdata_t[31:0] = slave_reg_wdata[31:0];
`endif
always @ (posedge i_sys_hclk or negedge i_sys_rst_b)
begin
if(!i_sys_rst_b)
begin
w_ram_sel_tmp <= 1'b0;
w_ram_size_tmp[2:0] <= 3'b0;
w_ram_addr_tmp[BIT_WIDTH-1:0] <= {BIT_WIDTH{1'b0}};
w_ram_write_tmp <= 1'b0;
read_after_write_access <= 1'b0;
end
else if(harb_xx_hwrite)
begin
w_ram_sel_tmp <= a_act_burst;
w_ram_size_tmp[2:0] <= harb_xx_hsize[2:0];
w_ram_addr_tmp[BIT_WIDTH-1:0] <= harb_xx_haddr[BIT_WIDTH-1:0];
w_ram_write_tmp <= 1'b1;
if(read_after_write_access)
read_after_write_access <= 1'b0;
else
read_after_write_access <= read_after_write_access;
end
else if(w_ram_sel & w_ram_write & r_ram_sel)
begin
w_ram_sel_tmp <= a_act_burst;
w_ram_size_tmp[2:0] <= harb_xx_hsize[2:0];
w_ram_addr_tmp[BIT_WIDTH-1:0] <= harb_xx_haddr[BIT_WIDTH-1:0];
w_ram_write_tmp <= 1'b0;
read_after_write_access <= 1'b1;
end
else
begin
w_ram_sel_tmp <= 1'b0;
w_ram_size_tmp[2:0] <= 3'b0;
w_ram_addr_tmp[BIT_WIDTH-1:0] <= {BIT_WIDTH{1'b0}};
w_ram_write_tmp <= 1'b0;
read_after_write_access <= 1'b0;
end
end
assign w_ram_size[2:0] = w_ram_size_tmp[2:0];
assign w_ram_addr[BIT_WIDTH-1:0] = w_ram_addr_tmp[BIT_WIDTH-1:0];
assign w_ram_sel = w_ram_sel_tmp;
assign w_ram_write = w_ram_write_tmp;
assign ram_wdata[31:0] = slave_reg_wdata_t[31:0];
assign r_ram_sel = a_act_burst & ~r_ram_write;
assign r_ram_write = harb_xx_hwrite;
assign r_ram_size[2:0] = harb_xx_hsize[2:0];
assign r_ram_addr[BIT_WIDTH-1:0] = harb_xx_haddr[BIT_WIDTH-1:0];
assign reg_slave_rdata[31:0] = ram_rdata[31:0];
assign ram_sel = w_ram_sel | r_ram_sel;
assign ram_write = w_ram_sel ? w_ram_write : r_ram_write;
assign ram_size[2:0] = w_ram_sel ? w_ram_size[2:0] : r_ram_size[2:0];
assign ram_addr[BIT_WIDTH-1:0] = w_ram_sel ? w_ram_addr[BIT_WIDTH-1:0] : r_ram_addr[BIT_WIDTH-1:0];
assign ram_idle = (~a_act_burst) & (~w_ram_sel);
always @ (posedge i_sys_hclk or negedge i_sys_rst_b)
begin
if(~i_sys_rst_b)
rty_first <= 1'b0;
else
rty_first <= rty_flag;
end
assign ahbs_harb_hready = (~read_after_write_access) & ahbs_harb_hready_s;
assign sms_resp[1:0] = OKAY;
assign hready_s = 1'b1;
always @( hready_s
or sms_resp[1:0]
or resp_cfg[3:0]
or rty_first)
begin
casex ({resp_cfg[3:2], rty_first, resp_cfg[1:0]}) // synopsys parallel_case
5'b1x_x0_x,
5'b1x_x1_0:
begin
rty_flag = 1'b0;
ahbs_harb_hready_s = hready_s;
ahbs_harb_hresp[1:0] = sms_resp[1:0];
end
5'b00_x1_0,
5'b00_x0_x:
begin
rty_flag = 1'b0;
ahbs_harb_hready_s = 1'b0;
ahbs_harb_hresp[1:0] = OKAY;
end
5'b01_00_x,
5'b01_01_0:
begin
rty_flag = 1'b1;
ahbs_harb_hready_s = 1'b0;
ahbs_harb_hresp[1:0] = RETRY;
end
5'b01_10_x,
5'b01_11_0:
begin
rty_flag = 1'b0;
ahbs_harb_hready_s = 1'b1;
ahbs_harb_hresp[1:0] = RETRY;
end
5'bxx_01_1:
begin
rty_flag = 1'b1;
ahbs_harb_hready_s = 1'b0;
ahbs_harb_hresp[1:0] = ERROR;
end
5'bxx_11_1:
begin
rty_flag = 1'b0;
ahbs_harb_hready_s = 1'b1;
ahbs_harb_hresp[1:0] = ERROR;
end
default:
begin
rty_flag = 1'b0;
ahbs_harb_hready_s = 1'b1;
ahbs_harb_hresp[1:0] = OKAY;
end
endcase
end
endmodule |
module sms_sram_bk2(
hrst_b,
ram_addr,
ram_clk,
ram_rdata,
ram_sel,
ram_size,
ram_wdata,
ram_write
);
input hrst_b;
input [15:0] ram_addr;
input ram_clk;
input ram_sel;
input [2 :0] ram_size;
input [31:0] ram_wdata;
input ram_write;
output [31:0] ram_rdata;
reg [3 :0] byte_sel_b;
reg mbk_cen_f_b;
reg [31:0] ram_rdata;
wire [3 :0] byte_wen_b;
wire hrst_b;
wire mbk_cen_b;
wire mbk_wen_b;
wire [31:0] ram0_rdata;
wire [15:0] ram_addr;
wire ram_clk;
wire ram_sel;
wire [2 :0] ram_size;
wire [31:0] ram_wdata;
wire ram_write;
parameter[2:0] BYTE = 3'b000,
HALFWORD = 3'b001,
WORD = 3'b010;
assign mbk_cen_b = ~ram_sel;
always @( ram_addr[1:0]
or ram_size[2:0])
begin
case (ram_size[2:0]) // synopsys parallel_case
BYTE:
case (ram_addr[1:0]) // synopsys parallel_case
2'b00:
byte_sel_b[3:0] = 4'b1110;
2'b01:
byte_sel_b[3:0] = 4'b1101;
2'b10:
byte_sel_b[3:0] = 4'b1011;
2'b11:
byte_sel_b[3:0] = 4'b0111;
endcase
HALFWORD:
case (ram_addr[1]) // synopsys parallel_case
1'b0:
byte_sel_b[3:0] = 4'b1100;
1'b1:
byte_sel_b[3:0] = 4'b0011;
endcase
WORD:
byte_sel_b[3:0] = 4'b0000;
default:
byte_sel_b[3:0] = 4'b1111;
endcase
end
assign mbk_wen_b = ~ram_write;
always @( posedge ram_clk or negedge hrst_b)
begin
if (!hrst_b)
mbk_cen_f_b <= 1'b0;
else
mbk_cen_f_b <= mbk_cen_b;
end
always @( mbk_cen_f_b
or ram0_rdata[31:0])
begin
case (mbk_cen_f_b)
1'b0:
ram_rdata[31:0] = ram0_rdata[31:0];
1'b1:
ram_rdata[31:0] = 32'b0;
endcase
end
parameter DATAWIDTH = 32;
parameter ADDRWIDTH = 14;
parameter MEMDEPTH = 2**(ADDRWIDTH);
assign byte_wen_b[3:0] = byte_sel_b[3:0] | {4{mbk_wen_b}};
fpga_spram #(DATAWIDTH,ADDRWIDTH,MEMDEPTH) x_fpga_spram (
.A (ram_addr[15:2] ),
.BWEN (byte_wen_b[3:0] ),
.CEN (mbk_cen_b ),
.CLK (ram_clk ),
.D (ram_wdata[31:0] ),
.Q (ram0_rdata[31:0])
);
endmodule |
module sms_top(
ahb_sms0_haddr,
ahb_sms0_hprot,
ahb_sms0_hsel,
ahb_sms0_hsize,
ahb_sms0_htrans,
ahb_sms0_hwdata,
ahb_sms0_hwrite,
ahb_sms1_haddr,
ahb_sms1_hprot,
ahb_sms1_hsel,
ahb_sms1_hsize,
ahb_sms1_htrans,
ahb_sms1_hwdata,
ahb_sms1_hwrite,
ahb_sms2_haddr,
ahb_sms2_hprot,
ahb_sms2_hsel,
ahb_sms2_hsize,
ahb_sms2_htrans,
ahb_sms2_hwdata,
ahb_sms2_hwrite,
ahb_sms3_haddr,
ahb_sms3_hprot,
ahb_sms3_hsel,
ahb_sms3_hsize,
ahb_sms3_htrans,
ahb_sms3_hwdata,
ahb_sms3_hwrite,
pmu_sms_hclk,
pmu_sms_hrst_b,
sms0_ahb_hrdata,
sms0_ahb_hready,
sms0_ahb_hresp,
sms0_idle,
sms1_ahb_hrdata,
sms1_ahb_hready,
sms1_ahb_hresp,
sms1_idle,
sms2_ahb_hrdata,
sms2_ahb_hready,
sms2_ahb_hresp,
sms2_idle,
sms3_ahb_hrdata,
sms3_ahb_hready,
sms3_ahb_hresp,
sms3_idle,
sms_big_endian_b
);
input [31:0] ahb_sms0_haddr;
input [3 :0] ahb_sms0_hprot;
input ahb_sms0_hsel;
input [2 :0] ahb_sms0_hsize;
input [1 :0] ahb_sms0_htrans;
input [31:0] ahb_sms0_hwdata;
input ahb_sms0_hwrite;
input [31:0] ahb_sms1_haddr;
input [3 :0] ahb_sms1_hprot;
input ahb_sms1_hsel;
input [2 :0] ahb_sms1_hsize;
input [1 :0] ahb_sms1_htrans;
input [31:0] ahb_sms1_hwdata;
input ahb_sms1_hwrite;
input [31:0] ahb_sms2_haddr;
input [3 :0] ahb_sms2_hprot;
input ahb_sms2_hsel;
input [2 :0] ahb_sms2_hsize;
input [1 :0] ahb_sms2_htrans;
input [31:0] ahb_sms2_hwdata;
input ahb_sms2_hwrite;
input [31:0] ahb_sms3_haddr;
input [3 :0] ahb_sms3_hprot;
input ahb_sms3_hsel;
input [2 :0] ahb_sms3_hsize;
input [1 :0] ahb_sms3_htrans;
input [31:0] ahb_sms3_hwdata;
input ahb_sms3_hwrite;
input pmu_sms_hclk;
input pmu_sms_hrst_b;
input sms_big_endian_b;
output [31:0] sms0_ahb_hrdata;
output sms0_ahb_hready;
output [1 :0] sms0_ahb_hresp;
output sms0_idle;
output [31:0] sms1_ahb_hrdata;
output sms1_ahb_hready;
output [1 :0] sms1_ahb_hresp;
output sms1_idle;
output [31:0] sms2_ahb_hrdata;
output sms2_ahb_hready;
output [1 :0] sms2_ahb_hresp;
output sms2_idle;
output [31:0] sms3_ahb_hrdata;
output sms3_ahb_hready;
output [1 :0] sms3_ahb_hresp;
output sms3_idle;
wire [31:0] ahb_sms0_haddr;
wire [3 :0] ahb_sms0_hprot;
wire ahb_sms0_hsel;
wire [2 :0] ahb_sms0_hsize;
wire [1 :0] ahb_sms0_htrans;
wire [31:0] ahb_sms0_hwdata;
wire ahb_sms0_hwrite;
wire [31:0] ahb_sms1_haddr;
wire [3 :0] ahb_sms1_hprot;
wire ahb_sms1_hsel;
wire [2 :0] ahb_sms1_hsize;
wire [1 :0] ahb_sms1_htrans;
wire [31:0] ahb_sms1_hwdata;
wire ahb_sms1_hwrite;
wire [31:0] ahb_sms2_haddr;
wire [3 :0] ahb_sms2_hprot;
wire ahb_sms2_hsel;
wire [2 :0] ahb_sms2_hsize;
wire [1 :0] ahb_sms2_htrans;
wire [31:0] ahb_sms2_hwdata;
wire ahb_sms2_hwrite;
wire [31:0] ahb_sms3_haddr;
wire [3 :0] ahb_sms3_hprot;
wire ahb_sms3_hsel;
wire [2 :0] ahb_sms3_hsize;
wire [1 :0] ahb_sms3_htrans;
wire [31:0] ahb_sms3_hwdata;
wire ahb_sms3_hwrite;
wire pmu_sms_hclk;
wire pmu_sms_hrst_b;
wire region_rd_deny_flag0;
wire region_rd_deny_flag1;
wire region_rd_deny_flag2;
wire region_rd_deny_flag3;
wire region_wr_deny_flag0;
wire region_wr_deny_flag1;
wire region_wr_deny_flag2;
wire region_wr_deny_flag3;
wire [31:0] sms0_ahb_hrdata;
wire sms0_ahb_hready;
wire [1 :0] sms0_ahb_hresp;
wire sms0_idle;
wire [31:0] sms1_ahb_hrdata;
wire sms1_ahb_hready;
wire [1 :0] sms1_ahb_hresp;
wire sms1_idle;
wire [31:0] sms2_ahb_hrdata;
wire sms2_ahb_hready;
wire [1 :0] sms2_ahb_hresp;
wire sms2_idle;
wire [31:0] sms3_ahb_hrdata;
wire sms3_ahb_hready;
wire [1 :0] sms3_ahb_hresp;
wire sms3_idle;
wire sms_big_endian_b;
sms_bank_64k_top x_sms0_top (
.big_endian_b (sms_big_endian_b ),
.mem_haddr (ahb_sms0_haddr ),
.mem_hclk (pmu_sms_hclk ),
.mem_hprot (ahb_sms0_hprot ),
.mem_hrdata (sms0_ahb_hrdata ),
.mem_hready (1'b1 ),
.mem_hready_resp (sms0_ahb_hready ),
.mem_hresp (sms0_ahb_hresp ),
.mem_hrst_b (pmu_sms_hrst_b ),
.mem_hsel (ahb_sms0_hsel ),
.mem_hsize (ahb_sms0_hsize ),
.mem_htrans (ahb_sms0_htrans ),
.mem_hwdata (ahb_sms0_hwdata ),
.mem_hwrite (ahb_sms0_hwrite ),
.region_rd_deny_flag (region_rd_deny_flag0 ),
.region_wr_deny_flag (region_wr_deny_flag0 ),
.sms_idle0 (sms0_idle )
);
sms_bank_64k_top x_sms1_top (
.big_endian_b (sms_big_endian_b ),
.mem_haddr (ahb_sms1_haddr ),
.mem_hclk (pmu_sms_hclk ),
.mem_hprot (ahb_sms1_hprot ),
.mem_hrdata (sms1_ahb_hrdata ),
.mem_hready (1'b1 ),
.mem_hready_resp (sms1_ahb_hready ),
.mem_hresp (sms1_ahb_hresp ),
.mem_hrst_b (pmu_sms_hrst_b ),
.mem_hsel (ahb_sms1_hsel ),
.mem_hsize (ahb_sms1_hsize ),
.mem_htrans (ahb_sms1_htrans ),
.mem_hwdata (ahb_sms1_hwdata ),
.mem_hwrite (ahb_sms1_hwrite ),
.region_rd_deny_flag (region_rd_deny_flag1 ),
.region_wr_deny_flag (region_wr_deny_flag1 ),
.sms_idle0 (sms1_idle )
);
sms_bank_64k_top x_sms2_top (
.big_endian_b (sms_big_endian_b ),
.mem_haddr (ahb_sms2_haddr ),
.mem_hclk (pmu_sms_hclk ),
.mem_hprot (ahb_sms2_hprot ),
.mem_hrdata (sms2_ahb_hrdata ),
.mem_hready (1'b1 ),
.mem_hready_resp (sms2_ahb_hready ),
.mem_hresp (sms2_ahb_hresp ),
.mem_hrst_b (pmu_sms_hrst_b ),
.mem_hsel (ahb_sms2_hsel ),
.mem_hsize (ahb_sms2_hsize ),
.mem_htrans (ahb_sms2_htrans ),
.mem_hwdata (ahb_sms2_hwdata ),
.mem_hwrite (ahb_sms2_hwrite ),
.region_rd_deny_flag (region_rd_deny_flag2 ),
.region_wr_deny_flag (region_wr_deny_flag2 ),
.sms_idle0 (sms2_idle )
);
sms_bank_64k_top x_isram_top (
.big_endian_b (sms_big_endian_b ),
.mem_haddr (ahb_sms3_haddr ),
.mem_hclk (pmu_sms_hclk ),
.mem_hprot (ahb_sms3_hprot ),
.mem_hrdata (sms3_ahb_hrdata ),
.mem_hready (1'b1 ),
.mem_hready_resp (sms3_ahb_hready ),
.mem_hresp (sms3_ahb_hresp ),
.mem_hrst_b (pmu_sms_hrst_b ),
.mem_hsel (ahb_sms3_hsel ),
.mem_hsize (ahb_sms3_hsize ),
.mem_htrans (ahb_sms3_htrans ),
.mem_hwdata (ahb_sms3_hwdata ),
.mem_hwrite (ahb_sms3_hwrite ),
.region_rd_deny_flag (region_rd_deny_flag3 ),
.region_wr_deny_flag (region_wr_deny_flag3 ),
.sms_idle0 (sms3_idle )
);
assign region_rd_deny_flag0 = 1'b0;
assign region_rd_deny_flag1 = 1'b0;
assign region_rd_deny_flag2 = 1'b0;
assign region_rd_deny_flag3 = 1'b0;
assign region_wr_deny_flag0 = 1'b0;
assign region_wr_deny_flag1 = 1'b0;
assign region_wr_deny_flag2 = 1'b0;
assign region_wr_deny_flag3 = 1'b0;
endmodule |
module tim6_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim6_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim6_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim6_trust;
tim6_tim_top x_tim6_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module tim6_tim_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire [1 :0] timer_en;
wire timer_int_flag;
wire timer_int_flag_n;
wire [1 :0] timer_int_n;
wire [1 :0] timertrig;
timers_top x_timers_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.paddr (paddr[7:0] ),
.pclk (pclk ),
.penable (penable ),
.prdata (prdata ),
.presetn (presetn ),
.psel (psel ),
.pwdata (pwdata ),
.pwrite (pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig ),
.timer_1_clk (pclk ),
.timer_1_resetn (presetn ),
.timer_2_clk (pclk ),
.timer_2_resetn (presetn ),
.timer_en (timer_en ),
.timer_int (intr ),
.timer_int_flag (timer_int_flag ),
.timer_int_flag_n (timer_int_flag_n ),
.timer_int_n (timer_int_n ),
.timertrig (timertrig )
);
endmodule |
module tim5_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim5_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim5_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim5_trust;
tim5_tim_top x_tim5_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module wdt_biu #
(
parameter WDT_ADDR_LHS = 5'd10
)
(
input wire pclk ,
input wire presetn ,
input wire psel ,
input wire [WDT_ADDR_LHS:0] paddr ,
input wire pwrite ,
input wire penable ,
input wire [31:0] pwdata ,
output reg [31:0] prdata ,
input wire [31:0] iprdata ,
output wire wr_en ,
output wire rd_en ,
output wire [WDT_ADDR_LHS-2:0] reg_addr ,
output wire [31:0] ipwdata
);
assign wr_en = psel & penable & pwrite;
assign rd_en = psel & !penable & !pwrite;
assign reg_addr = paddr[WDT_ADDR_LHS:2];
assign ipwdata = pwdata;
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
prdata <= 32'b0;
else if(rd_en == 1'b1)
prdata <= iprdata;
else ;
end
endmodule |
module wdt_cnt #
(
`include "wdt_params.v"
)
(
input wire clk ,
input wire clk_en ,
input wire rst_n ,
input wire [WDT_CNT_WIDTH-1:0] start_val ,
input wire restart ,
input wire cnt_en ,
input wire pause ,
input wire speed_up ,
input wire scan_mode ,
output reg [WDT_CNT_WIDTH-1:0] cnt
);
reg ext_rise_edge ;
reg extend ;
reg prev_cnt_en ;
wire int_cnt_en ;
wire [WDT_CNT_WIDTH-1:0] int_start_val ;
wire ext_init_ld ;
wire ext_restart ;
wire initial_load ;
wire rise_edge_cnt_en ;
wire int_speed_up ;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
cnt <= WDT_CNT_RST;
else if(clk_en) begin
if(initial_load)
cnt <= int_start_val;
else if(ext_restart || (cnt == {WDT_CNT_WIDTH{1'b0}} & (~pause)))
cnt <= int_start_val;
else if(int_cnt_en)
cnt <= cnt - 1'b1;
else ;
end
else ;
end
assign int_start_val[WDT_CNT_WIDTH-1:8] = int_speed_up ? {(WDT_CNT_WIDTH-8){1'b0}} :
start_val[WDT_CNT_WIDTH-1:8];
assign int_start_val[7:0] = int_speed_up ? 8'b11111111 :
start_val[7:0];
assign int_speed_up = scan_mode ? cnt[0] : speed_up;
assign int_cnt_en = cnt_en & (~pause);
assign initial_load = (WDT_DUAL_TOP == 1) ? ext_init_ld : 1'b0;
assign ext_init_ld = (WDT_CLK_EN == 1) ? (rise_edge_cnt_en | ext_rise_edge) : rise_edge_cnt_en;
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
ext_rise_edge <= 1'b0;
else
ext_rise_edge <= ((rise_edge_cnt_en & (~clk_en)) | ext_init_ld) & ~(clk_en & ext_init_ld);
end
assign rise_edge_cnt_en = cnt_en & ~prev_cnt_en;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
prev_cnt_en <= 1'b0;
else
prev_cnt_en <= cnt_en;
end
assign ext_restart = (WDT_CLK_EN == 1) ? (restart | extend) : restart;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
extend <= 1'b0;
else
extend <= ((restart & (~clk_en)) | ext_restart) & ~(clk_en & ext_restart);
end
endmodule |
module wdt_isrc #
(
`include "wdt_params.v"
)
(
input wire pclk ,
input wire presetn ,
input wire wdt_clk_en ,
input wire [WDT_CNT_WIDTH-1:0] top ,
input wire restart ,
input wire wdt_en ,
input wire eoi_en ,
input wire [7:0] rpl ,
input wire rmod ,
input wire pause ,
input wire speed_up ,
input wire scan_mode ,
output wire [WDT_CNT_WIDTH-1:0] cnt ,
output wire wdt_int ,
output wire sys_rst
);
wdt_cnt U_WDT_CNT
(
.clk (pclk ),
.clk_en (wdt_clk_en ),
.rst_n (presetn ),
.start_val (top ),
.restart (restart ),
.cnt_en (wdt_en ),
.pause (pause ),
.speed_up (speed_up ),
.scan_mode (scan_mode ),
.cnt (cnt )
);
wdt_isrg U_WDT_ISRG
(
.clk (pclk ),
.clk_en (wdt_clk_en ),
.rst_n (presetn ),
.cnt_val (cnt ),
.eoi_en (eoi_en ),
.restart (restart ),
.rst_pulse_len (rpl ),
.resp_mod (rmod ),
.pause (pause ),
.wdt_int (wdt_int ),
.sys_rst (sys_rst )
);
endmodule |
module wdt_isrg #
(
`include "wdt_params.v"
)
(
input wire clk ,
input wire rst_n ,
input wire clk_en ,
input wire [WDT_CNT_WIDTH-1:0] cnt_val ,
input wire eoi_en ,
input wire restart ,
input wire [7:0] rst_pulse_len ,
input wire resp_mod ,
input wire pause ,
output reg wdt_int ,
output reg sys_rst
);
reg [7:0] rst_cnt ;
reg extend ;
wire clr_int ;
wire ext_clr_int ;
wire clr_sys_rst ;
wire zero_cnt ;
reg prev_zero_cnt ;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
wdt_int <= 1'b0;
else if(resp_mod) begin
if(ext_clr_int)
wdt_int <= 1'b0;
else if(zero_cnt & clk_en & (~pause))
wdt_int <= 1'b1;
else ;
end
else
wdt_int <= 1'b0;
end
assign ext_clr_int = (WDT_CLK_EN == 1) ? (clr_int | extend) : clr_int;
assign clr_int = restart | eoi_en;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
extend <= 1'b0;
else
extend <= ((clr_int & (~clk_en)) | ext_clr_int) & ~(clk_en & ext_clr_int);
end
assign zero_cnt = (cnt_val == {WDT_CNT_WIDTH{1'b0}}) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
sys_rst <= 1'b0;
else begin
if(clr_sys_rst)
sys_rst <= 1'b0;
else if(zero_cnt & clk_en & (~pause) & (~ext_clr_int)) begin
if(resp_mod)
sys_rst <= wdt_int;
else
sys_rst <= 1'b1;
end
else ;
end
end
assign clr_sys_rst = (rst_cnt >= rst_pulse_len) ? 1'b1 : 1'b0;
always @(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
rst_cnt <= 8'b0;
else begin
if(sys_rst)
rst_cnt <= rst_cnt + 1'b1;
else
rst_cnt <= 8'b0;
end
end
endmodule |
module wdt_regfile #
(
`include "wdt_params.v"
)
(
input wire pclk ,
input wire presetn ,
input wire clk_en ,
input wire wdt_en_external ,
input wire wr_en ,
input wire rd_en ,
input wire [WDT_ADDR_LHS-2:0] reg_addr ,
input wire [31:0] ipwdata ,
output reg [31:0] iprdata ,
input wire [WDT_CNT_WIDTH-1:0] cnt ,
input wire wdt_int ,
output wire [WDT_CNT_WIDTH-1:0] top ,
output wire restart ,
output reg wdt_en ,
output wire eoi_en ,
output reg [7:0] rpl ,
output wire rmod
);
localparam WDT_CR_OFFSET = 0;
localparam WDT_TORR_OFFSET = 1;
localparam WDT_CCVR_OFFSET = 2;
localparam WDT_CRR_OFFSET = 3;
localparam WDT_STAT_OFFSET = 4;
localparam WDT_EOI_OFFSET = 5;
localparam WDT_FIXED_TOP_0 = 32'hffff ;
localparam WDT_FIXED_TOP_1 = 32'h1ffff ;
localparam WDT_FIXED_TOP_2 = 32'h3ffff ;
localparam WDT_FIXED_TOP_3 = 32'h7ffff ;
localparam WDT_FIXED_TOP_4 = 32'hfffff ;
localparam WDT_FIXED_TOP_5 = 32'h1fffff ;
localparam WDT_FIXED_TOP_6 = 32'h3fffff ;
localparam WDT_FIXED_TOP_7 = 32'h7fffff ;
localparam WDT_FIXED_TOP_8 = 32'hffffff ;
localparam WDT_FIXED_TOP_9 = 32'h1ffffff ;
localparam WDT_FIXED_TOP_10 = 32'h3ffffff ;
localparam WDT_FIXED_TOP_11 = 32'h7ffffff ;
localparam WDT_FIXED_TOP_12 = 32'hfffffff ;
localparam WDT_FIXED_TOP_13 = 32'h1fffffff;
localparam WDT_FIXED_TOP_14 = 32'h3fffffff;
localparam WDT_FIXED_TOP_15 = 32'h7fffffff;
localparam WDT_RPL_0 = 1 ;
localparam WDT_RPL_1 = 3 ;
localparam WDT_RPL_2 = 7 ;
localparam WDT_RPL_3 = 15 ;
localparam WDT_RPL_4 = 31 ;
localparam WDT_RPL_5 = 63 ;
localparam WDT_RPL_6 = 127;
localparam WDT_RPL_7 = 255;
wire wdt_cr_en ;
wire wdt_torr_en ;
wire wdt_ccvr_en ;
wire wdt_crr_en ;
wire wdt_stat_en ;
wire wdt_eoi_en ;
wire wdt_cr_we ;
wire wdt_torr_we ;
wire wdt_crr_we ;
reg [ 5:0] wdt_cr_ir ;
wire [ 5:0] wdt_cr ;
reg [ 7:0] wdt_torr_ir ;
wire [ 7:0] wdt_torr ;
wire [31:0] wdt_ccvr ;
wire [ 2:0] dflt_rpl ;
wire dflt_rmod ;
wire dflt_wdt_en ;
wire [ 3:0] dflt_top_init ;
wire [ 3:0] dflt_top_bus ;
wire [ 7:0] int_wdt_torr_ir ;
reg [31:0] int_cnt ;
wire wdt_eoi_rd ;
reg prev_wdt_eoi_rd ;
wire top_sel ;
reg [WDT_CNT_WIDTH-1:0] int_top ;
reg [WDT_CNT_WIDTH-1:0] int_top_init ;
reg been_started ;
reg been_enabled ;
assign wdt_cr_en = (reg_addr == WDT_CR_OFFSET ) ? 1'b1 : 1'b0;
assign wdt_torr_en = (reg_addr == WDT_TORR_OFFSET) ? 1'b1 : 1'b0;
assign wdt_ccvr_en = (reg_addr == WDT_CCVR_OFFSET) ? 1'b1 : 1'b0;
assign wdt_crr_en = (reg_addr == WDT_CRR_OFFSET ) ? 1'b1 : 1'b0;
assign wdt_stat_en = (reg_addr == WDT_STAT_OFFSET) ? 1'b1 : 1'b0;
assign wdt_eoi_en = (reg_addr == WDT_EOI_OFFSET ) ? 1'b1 : 1'b0;
assign wdt_cr_we = wdt_cr_en & wr_en;
assign wdt_torr_we = wdt_torr_en & wr_en;
assign wdt_crr_we = wdt_crr_en & wr_en;
assign dflt_rpl = WDT_DFLT_RPL;
assign dflt_rmod = WDT_DFLT_RMOD;
assign dflt_wdt_en = WDT_ALWAYS_EN;
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
wdt_cr_ir <= {1'b0,dflt_rpl, dflt_rmod, dflt_wdt_en};
else if(wdt_cr_we) begin
wdt_cr_ir[5:1] <= ipwdata[5:1];
wdt_cr_ir[0] <= ipwdata[0];
end
else ;
end
assign wdt_cr[5] = wdt_cr_ir[5];
assign wdt_cr[4:2] = wdt_cr_ir[4:2];
assign wdt_cr[1] = wdt_cr_ir[1];
assign wdt_cr[0] = (WDT_ALWAYS_EN == 1'b0) ? wdt_cr_ir[0] : WDT_ALWAYS_EN;
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
wdt_torr_ir <= WDT_TOP_RST;
else if(wdt_torr_we)
wdt_torr_ir <= ipwdata[7:0];
else ;
end
assign dflt_top_init = WDT_DFLT_TOP_INIT;
assign dflt_top_bus = WDT_DFLT_TOP;
assign int_wdt_torr_ir = (WDT_ALWAYS_EN == 1'b1 && WDT_DUAL_TOP == 1'b1) ? {dflt_top_init, wdt_torr_ir[3:0]} : wdt_torr_ir;
assign wdt_torr = int_wdt_torr_ir;
assign restart = (wdt_crr_we) ? (ipwdata[7:0] == 8'b01110110) : 1'b0;
always @ (*)
begin
int_cnt = 32'b0;
int_cnt[WDT_CNT_WIDTH-1:0] = cnt;
end
assign wdt_ccvr = int_cnt;
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
prev_wdt_eoi_rd <= 1'b0;
else
prev_wdt_eoi_rd <= wdt_eoi_rd;
end
assign wdt_eoi_rd = wdt_eoi_en & rd_en;
assign eoi_en = wdt_eoi_rd & ~prev_wdt_eoi_rd;
always @(*)
begin
iprdata = 32'b0;
if(wdt_cr_en == 1'b1)
iprdata[5:0] = wdt_cr;
else if(wdt_torr_en == 1'b1)
iprdata[7:0] = wdt_torr;
else if(wdt_ccvr_en == 1'b1)
iprdata[WDT_CNT_WIDTH-1:0] = wdt_ccvr[WDT_CNT_WIDTH-1:0];
else if(wdt_stat_en == 1'b1)
iprdata[0] = wdt_int;
end
assign top = top_sel ? int_top : int_top_init;
assign top_sel = (WDT_DUAL_TOP == 1'b1) ? been_started : 1'b1;
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
been_started <= 1'b0;
else if(clk_en)
been_started <= been_enabled;
else ;
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
been_enabled <= 1'b0;
else if(wdt_en)
been_enabled <= 1'b1;
else ;
end
always @(*)
begin
if(WDT_USE_FIX_TOP == 1'b1) begin
case(wdt_torr[7:4])
4'd1 : int_top_init = WDT_FIXED_TOP_1;
4'd2 : int_top_init = WDT_FIXED_TOP_2;
4'd3 : int_top_init = WDT_FIXED_TOP_3;
4'd4 : int_top_init = WDT_FIXED_TOP_4;
4'd5 : int_top_init = WDT_FIXED_TOP_5;
4'd6 : int_top_init = WDT_FIXED_TOP_6;
4'd7 : int_top_init = WDT_FIXED_TOP_7;
4'd8 : int_top_init = WDT_FIXED_TOP_8;
4'd9 : int_top_init = WDT_FIXED_TOP_9;
4'd10 : int_top_init = WDT_FIXED_TOP_10;
4'd11 : int_top_init = WDT_FIXED_TOP_11;
4'd12 : int_top_init = WDT_FIXED_TOP_12;
4'd13 : int_top_init = WDT_FIXED_TOP_13;
4'd14 : int_top_init = WDT_FIXED_TOP_14;
4'd15 : int_top_init = WDT_FIXED_TOP_15;
default : int_top_init = WDT_FIXED_TOP_0;
endcase
end
else begin
case(wdt_torr[7:4])
4'd1 : int_top_init = WDT_USER_TOP_INIT_1;
4'd2 : int_top_init = WDT_USER_TOP_INIT_2;
4'd3 : int_top_init = WDT_USER_TOP_INIT_3;
4'd4 : int_top_init = WDT_USER_TOP_INIT_4;
4'd5 : int_top_init = WDT_USER_TOP_INIT_5;
4'd6 : int_top_init = WDT_USER_TOP_INIT_6;
4'd7 : int_top_init = WDT_USER_TOP_INIT_7;
4'd8 : int_top_init = WDT_USER_TOP_INIT_8;
4'd9 : int_top_init = WDT_USER_TOP_INIT_9;
4'd10 : int_top_init = WDT_USER_TOP_INIT_10;
4'd11 : int_top_init = WDT_USER_TOP_INIT_11;
4'd12 : int_top_init = WDT_USER_TOP_INIT_12;
4'd13 : int_top_init = WDT_USER_TOP_INIT_13;
4'd14 : int_top_init = WDT_USER_TOP_INIT_14;
4'd15 : int_top_init = WDT_USER_TOP_INIT_15;
default : int_top_init = WDT_USER_TOP_INIT_0;
endcase
end
end
always @(*)
begin
if(WDT_USE_FIX_TOP == 1'b1) begin
case(wdt_torr[3:0])
4'd1 : int_top = WDT_FIXED_TOP_1;
4'd2 : int_top = WDT_FIXED_TOP_2;
4'd3 : int_top = WDT_FIXED_TOP_3;
4'd4 : int_top = WDT_FIXED_TOP_4;
4'd5 : int_top = WDT_FIXED_TOP_5;
4'd6 : int_top = WDT_FIXED_TOP_6;
4'd7 : int_top = WDT_FIXED_TOP_7;
4'd8 : int_top = WDT_FIXED_TOP_8;
4'd9 : int_top = WDT_FIXED_TOP_9;
4'd10 : int_top = WDT_FIXED_TOP_10;
4'd11 : int_top = WDT_FIXED_TOP_11;
4'd12 : int_top = WDT_FIXED_TOP_12;
4'd13 : int_top = WDT_FIXED_TOP_13;
4'd14 : int_top = WDT_FIXED_TOP_14;
4'd15 : int_top = WDT_FIXED_TOP_15;
default : int_top = WDT_FIXED_TOP_0;
endcase
end
else begin
case(wdt_torr[3:0])
4'd1 : int_top = WDT_USER_TOP_1;
4'd2 : int_top = WDT_USER_TOP_2;
4'd3 : int_top = WDT_USER_TOP_3;
4'd4 : int_top = WDT_USER_TOP_4;
4'd5 : int_top = WDT_USER_TOP_5;
4'd6 : int_top = WDT_USER_TOP_6;
4'd7 : int_top = WDT_USER_TOP_7;
4'd8 : int_top = WDT_USER_TOP_8;
4'd9 : int_top = WDT_USER_TOP_9;
4'd10 : int_top = WDT_USER_TOP_10;
4'd11 : int_top = WDT_USER_TOP_11;
4'd12 : int_top = WDT_USER_TOP_12;
4'd13 : int_top = WDT_USER_TOP_13;
4'd14 : int_top = WDT_USER_TOP_14;
4'd15 : int_top = WDT_USER_TOP_15;
default : int_top = WDT_USER_TOP_0;
endcase
end
end
always @(*)
begin
case (wdt_cr[4:2])
3'd1 : rpl = WDT_RPL_1;
3'd2 : rpl = WDT_RPL_2;
3'd3 : rpl = WDT_RPL_3;
3'd4 : rpl = WDT_RPL_4;
3'd5 : rpl = WDT_RPL_5;
3'd6 : rpl = WDT_RPL_6;
3'd7 : rpl = WDT_RPL_7;
default : rpl = WDT_RPL_0;
endcase
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
wdt_en <= 1'b0;
else if(wdt_cr[0] == 1'b1)
wdt_en <= 1'b1;
else if(wdt_en_external == 1'b1)
wdt_en <= 1'b1;
else
wdt_en <= 1'b0;
end
assign rmod = wdt_cr[1];
endmodule |
module wdt_sec_top(
intr,
paddr,
pclk,
penable,
pprot,
prdata,
prst_b,
psel,
pwdata,
pwrite,
scan_mode,
sys_rst_b,
tipc_wdt_trust
);
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input prst_b;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_wdt_trust;
output intr;
output [31:0] prdata;
output sys_rst_b;
wire [7 :0] i_paddr;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire prst_b;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire sys_rst_b;
wire tipc_wdt_trust;
wire wdt_int_n;
wire wdt_sys_rst;
wdt x_wdt (
.paddr (i_paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (prst_b ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.speed_up (1'b0 ),
.wdt_en_external (1'b0 ),
.wdt_int (intr ),
.wdt_int_n (wdt_int_n ),
.wdt_sys_rst (wdt_sys_rst ),
.wdt_sys_rst_n (sys_rst_b )
);
assign i_paddr[7:0] = paddr[7:0];
assign prdata[31:0] = i_prdata[31:0] ;
assign i_pwrite = pwrite ;
assign i_psel = psel ;
endmodule |
module wdt(
pclk,
presetn,
penable,
pwrite,
pwdata,
paddr,
psel,
speed_up,
scan_mode,
wdt_en_external,
wdt_int,
wdt_int_n,
wdt_sys_rst,
wdt_sys_rst_n,
prdata
);
input pclk ;
input presetn ;
input penable ;
input pwrite ;
input [31:0] pwdata ;
input [7:0] paddr ;
input psel ;
input speed_up ;
input scan_mode ;
input wdt_en_external ;
output wdt_int ;
output wdt_int_n ;
output wdt_sys_rst ;
output wdt_sys_rst_n ;
output [31:0] prdata ;
wire wr_en ;
wire rd_en ;
wire [3:0] byte_en ;
wire [5:0] reg_addr ;
wire [31:0] ipwdata ;
wire [31:0] iprdata ;
wire [31:0] cnt ;
wire wdt_int ;
wire [31:0] top ;
wire restart ;
wire wdt_en ;
wire eoi_en ;
wire [7:0] rpl ;
wire rmod ;
wire sys_rst ;
wire wdt_int_n ;
wire wdt_sys_rst ;
wire wdt_sys_rst_n ;
wire wdt_clk_en ;
wire int_wdt_clk_en ;
wire pause ;
wire int_pause ;
parameter WDT_ADDR_LHS = 5'd7;
parameter WDT_CLK_EN = 1'b0;
parameter WDT_PAUSE = 1'b0;
wdt_biu #
(
.WDT_ADDR_LHS (WDT_ADDR_LHS )
)
U_WDT_BIU
(
.pclk (pclk ),
.presetn (presetn ),
.psel (psel ),
.penable (penable ),
.pwrite (pwrite ),
.paddr (paddr ),
.pwdata (pwdata ),
.prdata (prdata ),
.wr_en (wr_en ),
.rd_en (rd_en ),
.reg_addr (reg_addr ),
.ipwdata (ipwdata ),
.iprdata (iprdata )
);
wdt_regfile U_WDT_REGFILE
(
.pclk (pclk ),
.presetn (presetn ),
.clk_en (int_wdt_clk_en ),
.wdt_en_external (wdt_en_external ),
.wr_en (wr_en ),
.rd_en (rd_en ),
.reg_addr (reg_addr ),
.cnt (cnt ),
.wdt_int (wdt_int ),
.ipwdata (ipwdata ),
.iprdata (iprdata ),
.top (top ),
.restart (restart ),
.wdt_en (wdt_en ),
.eoi_en (eoi_en ),
.rpl (rpl ),
.rmod (rmod )
);
wdt_isrc
U_WDT_ISRC
(
.pclk (pclk ),
.presetn (presetn ),
.wdt_clk_en (int_wdt_clk_en ),
.top (top ),
.restart (restart ),
.wdt_en (wdt_en ),
.eoi_en (eoi_en ),
.rpl (rpl ),
.rmod (rmod ),
.pause (int_pause ),
.speed_up (speed_up ),
.scan_mode (scan_mode ),
.cnt (cnt ),
.wdt_int (wdt_int ),
.sys_rst (sys_rst )
);
assign int_wdt_clk_en = (WDT_CLK_EN == 1) ? wdt_clk_en : 1'b1;
assign int_pause = (WDT_PAUSE == 1) ? pause : 1'b0;
assign wdt_int_n = ~wdt_int;
assign wdt_sys_rst = sys_rst;
assign wdt_sys_rst_n = ~sys_rst;
endmodule |
module tim7_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim7_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim7_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim7_trust;
tim7_tim_top x_tim7_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module clk_mux2(
clk_sel,
clk_a,
clk_b,
clk_out
);
input clk_sel;
input clk_a;
input clk_b;
output clk_out;
wire clk_sel;
wire clk_a;
wire clk_b;
`ifdef FPGA
reg clk_out;
always @( clk_sel or clk_a or clk_b)
begin
case(clk_sel) // synopsys infer_mux
1'b1: clk_out = clk_b;
1'b0: clk_out = clk_a;
endcase
end
`else
wire clk_out;
Standard_Cell_CLK_MUX2 x_STD_clkmux2 (
.D0 (clk_a),
.D1 (clk_b),
.S (clk_sel),
.X (clk_out)
);
`endif
endmodule |
module_en,
local_en,
external_en,
pad_yy_test_mode,
pad_yy_gate_clk_en_b,
clk_out
);
input clk_in;
input global_en;
input module_en;
input local_en;
input external_en;
input pad_yy_test_mode;
input pad_yy_gate_clk_en_b;
output clk_out;
wire clk_en_bf_latch;
wire SE;
reg clk_en_af_latch;
assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;
assign SE = pad_yy_test_mode | pad_yy_gate_clk_en_b;
`ifdef FPGA
assign clk_out = clk_in;
`else
Standard_Cell_CLK_GATE x_gated_clk_cell(
.CK (clk_in),
.SE (SE),
.EN (clk_en_bf_latch),
.Q (clk_out)
);
`endif
endmodule |
module smu_top(
hmain0_ismc_s0_haddr,
hmain0_ismc_s0_hprot,
hmain0_ismc_s0_hsel,
hmain0_ismc_s0_hsize,
hmain0_ismc_s0_htrans,
hmain0_ismc_s0_hwdata,
hmain0_ismc_s0_hwrite,
hmain0_smc_s2_haddr,
hmain0_smc_s2_hprot,
hmain0_smc_s2_hsel,
hmain0_smc_s2_hsize,
hmain0_smc_s2_htrans,
hmain0_smc_s2_hwdata,
hmain0_smc_s2_hwrite,
hmain0_smc_s3_haddr,
hmain0_smc_s3_hprot,
hmain0_smc_s3_hsel,
hmain0_smc_s3_hsize,
hmain0_smc_s3_htrans,
hmain0_smc_s3_hwdata,
hmain0_smc_s3_hwrite,
hmain0_smc_s4_haddr,
hmain0_smc_s4_hprot,
hmain0_smc_s4_hsel,
hmain0_smc_s4_hsize,
hmain0_smc_s4_htrans,
hmain0_smc_s4_hwdata,
hmain0_smc_s4_hwrite,
ismc_hmain0_s0_hrdata,
ismc_hmain0_s0_hready,
ismc_hmain0_s0_hresp,
pmu_smc_hclk,
pmu_smc_hrst_b,
smc_hmain0_s2_hrdata,
smc_hmain0_s2_hready,
smc_hmain0_s2_hresp,
smc_hmain0_s3_hrdata,
smc_hmain0_s3_hready,
smc_hmain0_s3_hresp,
smc_hmain0_s4_hrdata,
smc_hmain0_s4_hready,
smc_hmain0_s4_hresp
);
input [31:0] hmain0_ismc_s0_haddr;
input [3 :0] hmain0_ismc_s0_hprot;
input hmain0_ismc_s0_hsel;
input [2 :0] hmain0_ismc_s0_hsize;
input [1 :0] hmain0_ismc_s0_htrans;
input [31:0] hmain0_ismc_s0_hwdata;
input hmain0_ismc_s0_hwrite;
input [31:0] hmain0_smc_s2_haddr;
input [3 :0] hmain0_smc_s2_hprot;
input hmain0_smc_s2_hsel;
input [2 :0] hmain0_smc_s2_hsize;
input [1 :0] hmain0_smc_s2_htrans;
input [31:0] hmain0_smc_s2_hwdata;
input hmain0_smc_s2_hwrite;
input [31:0] hmain0_smc_s3_haddr;
input [3 :0] hmain0_smc_s3_hprot;
input hmain0_smc_s3_hsel;
input [2 :0] hmain0_smc_s3_hsize;
input [1 :0] hmain0_smc_s3_htrans;
input [31:0] hmain0_smc_s3_hwdata;
input hmain0_smc_s3_hwrite;
input [31:0] hmain0_smc_s4_haddr;
input [3 :0] hmain0_smc_s4_hprot;
input hmain0_smc_s4_hsel;
input [2 :0] hmain0_smc_s4_hsize;
input [1 :0] hmain0_smc_s4_htrans;
input [31:0] hmain0_smc_s4_hwdata;
input hmain0_smc_s4_hwrite;
input pmu_smc_hclk;
input pmu_smc_hrst_b;
output [31:0] ismc_hmain0_s0_hrdata;
output ismc_hmain0_s0_hready;
output [1 :0] ismc_hmain0_s0_hresp;
output [31:0] smc_hmain0_s2_hrdata;
output smc_hmain0_s2_hready;
output [1 :0] smc_hmain0_s2_hresp;
output [31:0] smc_hmain0_s3_hrdata;
output smc_hmain0_s3_hready;
output [1 :0] smc_hmain0_s3_hresp;
output [31:0] smc_hmain0_s4_hrdata;
output smc_hmain0_s4_hready;
output [1 :0] smc_hmain0_s4_hresp;
wire [31:0] hmain0_ismc_s0_haddr;
wire [3 :0] hmain0_ismc_s0_hprot;
wire hmain0_ismc_s0_hsel;
wire [2 :0] hmain0_ismc_s0_hsize;
wire [1 :0] hmain0_ismc_s0_htrans;
wire [31:0] hmain0_ismc_s0_hwdata;
wire hmain0_ismc_s0_hwrite;
wire [31:0] hmain0_smc_s2_haddr;
wire [3 :0] hmain0_smc_s2_hprot;
wire hmain0_smc_s2_hsel;
wire [2 :0] hmain0_smc_s2_hsize;
wire [1 :0] hmain0_smc_s2_htrans;
wire [31:0] hmain0_smc_s2_hwdata;
wire hmain0_smc_s2_hwrite;
wire [31:0] hmain0_smc_s3_haddr;
wire [3 :0] hmain0_smc_s3_hprot;
wire hmain0_smc_s3_hsel;
wire [2 :0] hmain0_smc_s3_hsize;
wire [1 :0] hmain0_smc_s3_htrans;
wire [31:0] hmain0_smc_s3_hwdata;
wire hmain0_smc_s3_hwrite;
wire [31:0] hmain0_smc_s4_haddr;
wire [3 :0] hmain0_smc_s4_hprot;
wire hmain0_smc_s4_hsel;
wire [2 :0] hmain0_smc_s4_hsize;
wire [1 :0] hmain0_smc_s4_htrans;
wire [31:0] hmain0_smc_s4_hwdata;
wire hmain0_smc_s4_hwrite;
wire [31:0] ismc_hmain0_s0_hrdata;
wire ismc_hmain0_s0_hready;
wire [1 :0] ismc_hmain0_s0_hresp;
wire pmu_smc_hclk;
wire pmu_smc_hrst_b;
wire [31:0] smc_hmain0_s2_hrdata;
wire smc_hmain0_s2_hready;
wire [1 :0] smc_hmain0_s2_hresp;
wire [31:0] smc_hmain0_s3_hrdata;
wire smc_hmain0_s3_hready;
wire [1 :0] smc_hmain0_s3_hresp;
wire [31:0] smc_hmain0_s4_hrdata;
wire smc_hmain0_s4_hready;
wire [1 :0] smc_hmain0_s4_hresp;
wire sms0_idle;
wire sms1_idle;
wire sms2_idle;
wire sms3_idle;
wire sms_big_endian_b;
sms_top x_sms_top (
.ahb_sms0_haddr (hmain0_smc_s2_haddr ),
.ahb_sms0_hprot (hmain0_smc_s2_hprot ),
.ahb_sms0_hsel (hmain0_smc_s2_hsel ),
.ahb_sms0_hsize (hmain0_smc_s2_hsize ),
.ahb_sms0_htrans (hmain0_smc_s2_htrans ),
.ahb_sms0_hwdata (hmain0_smc_s2_hwdata ),
.ahb_sms0_hwrite (hmain0_smc_s2_hwrite ),
.ahb_sms1_haddr (hmain0_smc_s3_haddr ),
.ahb_sms1_hprot (hmain0_smc_s3_hprot ),
.ahb_sms1_hsel (hmain0_smc_s3_hsel ),
.ahb_sms1_hsize (hmain0_smc_s3_hsize ),
.ahb_sms1_htrans (hmain0_smc_s3_htrans ),
.ahb_sms1_hwdata (hmain0_smc_s3_hwdata ),
.ahb_sms1_hwrite (hmain0_smc_s3_hwrite ),
.ahb_sms2_haddr (hmain0_smc_s4_haddr ),
.ahb_sms2_hprot (hmain0_smc_s4_hprot ),
.ahb_sms2_hsel (hmain0_smc_s4_hsel ),
.ahb_sms2_hsize (hmain0_smc_s4_hsize ),
.ahb_sms2_htrans (hmain0_smc_s4_htrans ),
.ahb_sms2_hwdata (hmain0_smc_s4_hwdata ),
.ahb_sms2_hwrite (hmain0_smc_s4_hwrite ),
.ahb_sms3_haddr (hmain0_ismc_s0_haddr ),
.ahb_sms3_hprot (hmain0_ismc_s0_hprot ),
.ahb_sms3_hsel (hmain0_ismc_s0_hsel ),
.ahb_sms3_hsize (hmain0_ismc_s0_hsize ),
.ahb_sms3_htrans (hmain0_ismc_s0_htrans),
.ahb_sms3_hwdata (hmain0_ismc_s0_hwdata),
.ahb_sms3_hwrite (hmain0_ismc_s0_hwrite),
.pmu_sms_hclk (pmu_smc_hclk ),
.pmu_sms_hrst_b (pmu_smc_hrst_b ),
.sms0_ahb_hrdata (smc_hmain0_s2_hrdata ),
.sms0_ahb_hready (smc_hmain0_s2_hready ),
.sms0_ahb_hresp (smc_hmain0_s2_hresp ),
.sms0_idle (sms0_idle ),
.sms1_ahb_hrdata (smc_hmain0_s3_hrdata ),
.sms1_ahb_hready (smc_hmain0_s3_hready ),
.sms1_ahb_hresp (smc_hmain0_s3_hresp ),
.sms1_idle (sms1_idle ),
.sms2_ahb_hrdata (smc_hmain0_s4_hrdata ),
.sms2_ahb_hready (smc_hmain0_s4_hready ),
.sms2_ahb_hresp (smc_hmain0_s4_hresp ),
.sms2_idle (sms2_idle ),
.sms3_ahb_hrdata (ismc_hmain0_s0_hrdata),
.sms3_ahb_hready (ismc_hmain0_s0_hready),
.sms3_ahb_hresp (ismc_hmain0_s0_hresp ),
.sms3_idle (sms3_idle ),
.sms_big_endian_b (sms_big_endian_b )
);
assign sms_big_endian_b = 1'b1;
endmodule |
module retu_top(
hmain0_ismc_s0_haddr,
hmain0_ismc_s0_hprot,
hmain0_ismc_s0_hsel,
hmain0_ismc_s0_hsize,
hmain0_ismc_s0_htrans,
hmain0_ismc_s0_hwdata,
hmain0_ismc_s0_hwrite,
hmain0_smc_s2_haddr,
hmain0_smc_s2_hprot,
hmain0_smc_s2_hsel,
hmain0_smc_s2_hsize,
hmain0_smc_s2_htrans,
hmain0_smc_s2_hwdata,
hmain0_smc_s2_hwrite,
hmain0_smc_s3_haddr,
hmain0_smc_s3_hprot,
hmain0_smc_s3_hsel,
hmain0_smc_s3_hsize,
hmain0_smc_s3_htrans,
hmain0_smc_s3_hwdata,
hmain0_smc_s3_hwrite,
hmain0_smc_s4_haddr,
hmain0_smc_s4_hprot,
hmain0_smc_s4_hsel,
hmain0_smc_s4_hsize,
hmain0_smc_s4_htrans,
hmain0_smc_s4_hwdata,
hmain0_smc_s4_hwrite,
ismc_hmain0_s0_hrdata,
ismc_hmain0_s0_hready,
ismc_hmain0_s0_hresp,
pmu_smc_hclk,
pmu_smc_hrst_b,
smc_hmain0_s2_hrdata,
smc_hmain0_s2_hready,
smc_hmain0_s2_hresp,
smc_hmain0_s3_hrdata,
smc_hmain0_s3_hready,
smc_hmain0_s3_hresp,
smc_hmain0_s4_hrdata,
smc_hmain0_s4_hready,
smc_hmain0_s4_hresp
);
input [31:0] hmain0_ismc_s0_haddr;
input [3 :0] hmain0_ismc_s0_hprot;
input hmain0_ismc_s0_hsel;
input [2 :0] hmain0_ismc_s0_hsize;
input [1 :0] hmain0_ismc_s0_htrans;
input [31:0] hmain0_ismc_s0_hwdata;
input hmain0_ismc_s0_hwrite;
input [31:0] hmain0_smc_s2_haddr;
input [3 :0] hmain0_smc_s2_hprot;
input hmain0_smc_s2_hsel;
input [2 :0] hmain0_smc_s2_hsize;
input [1 :0] hmain0_smc_s2_htrans;
input [31:0] hmain0_smc_s2_hwdata;
input hmain0_smc_s2_hwrite;
input [31:0] hmain0_smc_s3_haddr;
input [3 :0] hmain0_smc_s3_hprot;
input hmain0_smc_s3_hsel;
input [2 :0] hmain0_smc_s3_hsize;
input [1 :0] hmain0_smc_s3_htrans;
input [31:0] hmain0_smc_s3_hwdata;
input hmain0_smc_s3_hwrite;
input [31:0] hmain0_smc_s4_haddr;
input [3 :0] hmain0_smc_s4_hprot;
input hmain0_smc_s4_hsel;
input [2 :0] hmain0_smc_s4_hsize;
input [1 :0] hmain0_smc_s4_htrans;
input [31:0] hmain0_smc_s4_hwdata;
input hmain0_smc_s4_hwrite;
input pmu_smc_hclk;
input pmu_smc_hrst_b;
output [31:0] ismc_hmain0_s0_hrdata;
output ismc_hmain0_s0_hready;
output [1 :0] ismc_hmain0_s0_hresp;
output [31:0] smc_hmain0_s2_hrdata;
output smc_hmain0_s2_hready;
output [1 :0] smc_hmain0_s2_hresp;
output [31:0] smc_hmain0_s3_hrdata;
output smc_hmain0_s3_hready;
output [1 :0] smc_hmain0_s3_hresp;
output [31:0] smc_hmain0_s4_hrdata;
output smc_hmain0_s4_hready;
output [1 :0] smc_hmain0_s4_hresp;
wire [31:0] hmain0_ismc_s0_haddr;
wire [3 :0] hmain0_ismc_s0_hprot;
wire hmain0_ismc_s0_hsel;
wire [2 :0] hmain0_ismc_s0_hsize;
wire [1 :0] hmain0_ismc_s0_htrans;
wire [31:0] hmain0_ismc_s0_hwdata;
wire hmain0_ismc_s0_hwrite;
wire [31:0] hmain0_smc_s2_haddr;
wire [3 :0] hmain0_smc_s2_hprot;
wire hmain0_smc_s2_hsel;
wire [2 :0] hmain0_smc_s2_hsize;
wire [1 :0] hmain0_smc_s2_htrans;
wire [31:0] hmain0_smc_s2_hwdata;
wire hmain0_smc_s2_hwrite;
wire [31:0] hmain0_smc_s3_haddr;
wire [3 :0] hmain0_smc_s3_hprot;
wire hmain0_smc_s3_hsel;
wire [2 :0] hmain0_smc_s3_hsize;
wire [1 :0] hmain0_smc_s3_htrans;
wire [31:0] hmain0_smc_s3_hwdata;
wire hmain0_smc_s3_hwrite;
wire [31:0] hmain0_smc_s4_haddr;
wire [3 :0] hmain0_smc_s4_hprot;
wire hmain0_smc_s4_hsel;
wire [2 :0] hmain0_smc_s4_hsize;
wire [1 :0] hmain0_smc_s4_htrans;
wire [31:0] hmain0_smc_s4_hwdata;
wire hmain0_smc_s4_hwrite;
wire [31:0] ismc_hmain0_s0_hrdata;
wire ismc_hmain0_s0_hready;
wire [1 :0] ismc_hmain0_s0_hresp;
wire pmu_smc_hclk;
wire pmu_smc_hrst_b;
wire [31:0] smc_hmain0_s2_hrdata;
wire smc_hmain0_s2_hready;
wire [1 :0] smc_hmain0_s2_hresp;
wire [31:0] smc_hmain0_s3_hrdata;
wire smc_hmain0_s3_hready;
wire [1 :0] smc_hmain0_s3_hresp;
wire [31:0] smc_hmain0_s4_hrdata;
wire smc_hmain0_s4_hready;
wire [1 :0] smc_hmain0_s4_hresp;
smu_top x_smu_top (
.hmain0_ismc_s0_haddr (hmain0_ismc_s0_haddr ),
.hmain0_ismc_s0_hprot (hmain0_ismc_s0_hprot ),
.hmain0_ismc_s0_hsel (hmain0_ismc_s0_hsel ),
.hmain0_ismc_s0_hsize (hmain0_ismc_s0_hsize ),
.hmain0_ismc_s0_htrans (hmain0_ismc_s0_htrans),
.hmain0_ismc_s0_hwdata (hmain0_ismc_s0_hwdata),
.hmain0_ismc_s0_hwrite (hmain0_ismc_s0_hwrite),
.hmain0_smc_s2_haddr (hmain0_smc_s2_haddr ),
.hmain0_smc_s2_hprot (hmain0_smc_s2_hprot ),
.hmain0_smc_s2_hsel (hmain0_smc_s2_hsel ),
.hmain0_smc_s2_hsize (hmain0_smc_s2_hsize ),
.hmain0_smc_s2_htrans (hmain0_smc_s2_htrans ),
.hmain0_smc_s2_hwdata (hmain0_smc_s2_hwdata ),
.hmain0_smc_s2_hwrite (hmain0_smc_s2_hwrite ),
.hmain0_smc_s3_haddr (hmain0_smc_s3_haddr ),
.hmain0_smc_s3_hprot (hmain0_smc_s3_hprot ),
.hmain0_smc_s3_hsel (hmain0_smc_s3_hsel ),
.hmain0_smc_s3_hsize (hmain0_smc_s3_hsize ),
.hmain0_smc_s3_htrans (hmain0_smc_s3_htrans ),
.hmain0_smc_s3_hwdata (hmain0_smc_s3_hwdata ),
.hmain0_smc_s3_hwrite (hmain0_smc_s3_hwrite ),
.hmain0_smc_s4_haddr (hmain0_smc_s4_haddr ),
.hmain0_smc_s4_hprot (hmain0_smc_s4_hprot ),
.hmain0_smc_s4_hsel (hmain0_smc_s4_hsel ),
.hmain0_smc_s4_hsize (hmain0_smc_s4_hsize ),
.hmain0_smc_s4_htrans (hmain0_smc_s4_htrans ),
.hmain0_smc_s4_hwdata (hmain0_smc_s4_hwdata ),
.hmain0_smc_s4_hwrite (hmain0_smc_s4_hwrite ),
.ismc_hmain0_s0_hrdata (ismc_hmain0_s0_hrdata),
.ismc_hmain0_s0_hready (ismc_hmain0_s0_hready),
.ismc_hmain0_s0_hresp (ismc_hmain0_s0_hresp ),
.pmu_smc_hclk (pmu_smc_hclk ),
.pmu_smc_hrst_b (pmu_smc_hrst_b ),
.smc_hmain0_s2_hrdata (smc_hmain0_s2_hrdata ),
.smc_hmain0_s2_hready (smc_hmain0_s2_hready ),
.smc_hmain0_s2_hresp (smc_hmain0_s2_hresp ),
.smc_hmain0_s3_hrdata (smc_hmain0_s3_hrdata ),
.smc_hmain0_s3_hready (smc_hmain0_s3_hready ),
.smc_hmain0_s3_hresp (smc_hmain0_s3_hresp ),
.smc_hmain0_s4_hrdata (smc_hmain0_s4_hrdata ),
.smc_hmain0_s4_hready (smc_hmain0_s4_hready ),
.smc_hmain0_s4_hresp (smc_hmain0_s4_hresp )
);
endmodule |
module tim0_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim0_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim0_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim0_trust;
tim_top x_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module timers_apbif #
(
`include "timers_params.v"
)
(
input wire pclk ,
input wire presetn ,
input wire penable ,
input wire pwrite ,
input wire [31:0] pwdata ,
input wire [TIMER_ADDR_LHS:0] paddr ,
input wire psel ,
output reg [TIMER1_WIDTH-1:0] timer1loadcount ,
output reg [TIMER2_WIDTH-1:0] timer2loadcount ,
output wire [ 1:0] timer_en ,
output wire [ 1:0] timer_mode ,
output wire [ 1:0] timer_hwen ,
output wire timer_int_flag ,
output wire timer_int_flag_n ,
output wire [ 1:0] timer_int ,
output wire [ 1:0] timer_int_n ,
input wire [63:0] bus_current_value ,
input wire [ 1:0] bus_interrupts ,
output reg [31:0] prdata ,
input wire etb_tim1_trig_en_on ,
input wire etb_tim2_trig_en_on ,
input wire etb_tim1_trig_en_off ,
input wire etb_tim2_trig_en_off ,
output reg tim1_etb_trig ,
output reg tim2_etb_trig
);
localparam TIMER1LC_OFFSET = 8'd0 ;
localparam TIMER1CV_OFFSET = 8'd1 ;
localparam TIMER1CR_OFFSET = 8'd2 ;
localparam TIMER1EOI_OFFSET = 8'd3 ;
localparam TIMER1INTST_OFFSET = 8'd4 ;
localparam TIMER2LC_OFFSET = 8'd5 ;
localparam TIMER2CV_OFFSET = 8'd6 ;
localparam TIMER2CR_OFFSET = 8'd7 ;
localparam TIMER2EOI_OFFSET = 8'd8 ;
localparam TIMER2INTST_OFFSET = 8'd9 ;
localparam TIMERSINTST_OFFSET = 8'd40;
localparam TIMERSEOI_OFFSET = 8'd41;
localparam TIMERSRAW_OFFSET = 8'd42;
reg [TIMER_CTRL_WIDTH-1:0] timer1controlreg ;
reg [TIMER_CTRL_WIDTH-1:0] timer2controlreg ;
reg timer1loadcount_wen ;
reg timer1controlreg_wen ;
reg timer1eoi_ren ;
reg timer2loadcount_wen ;
reg timer2controlreg_wen ;
reg timer2eoi_ren ;
reg timerseoi_ren ;
reg [31:0] ri_timer1loadcount ;
reg [31:0] ri_timer1currentvalue ;
reg [31:0] ri_timer1controlreg ;
reg [31:0] ri_timer1intstatus ;
reg [31:0] ri_timer2loadcount ;
reg [31:0] ri_timer2currentvalue ;
reg [31:0] ri_timer2controlreg ;
reg [31:0] ri_timer2intstatus ;
reg timer1_int_ff1 ;
reg timer1_int_ff2 ;
reg timer2_int_ff1 ;
reg timer2_int_ff2 ;
reg [ 1:0] timer_int_tmp ;
reg [ 1:0] int_sync_ff1 ;
reg [31:0] ri_timer_int ;
reg [31:0] ri_timersintstatus ;
wire [31:0] timer1currentvalue ;
wire [31:0] timer2currentvalue ;
wire [ 1:0] int_sync ;
wire [ 1:0] timereoi ;
wire timerseoi ;
wire [ 1:0] timeren ;
wire [ 1:0] timermode ;
wire [ 1:0] timerhwen ;
wire [ 1:0] timerintmask ;
wire [ 1:0] edge_detected ;
integer i;
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b1) && (pwrite == 1'b1)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER1LC_OFFSET)
timer1loadcount_wen = 1'b1;
else
timer1loadcount_wen = 1'b0;
end
else
timer1loadcount_wen = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b1) && (pwrite == 1'b1)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER1CR_OFFSET)
timer1controlreg_wen = 1'b1;
else
timer1controlreg_wen = 1'b0;
end
else
timer1controlreg_wen = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b0) && (pwrite == 1'b0)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER1EOI_OFFSET)
timer1eoi_ren = 1'b1;
else
timer1eoi_ren = 1'b0;
end
else
timer1eoi_ren = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b1) && (pwrite == 1'b1)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER2LC_OFFSET)
timer2loadcount_wen = 1'b1;
else
timer2loadcount_wen = 1'b0;
end
else
timer2loadcount_wen = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b1) && (pwrite == 1'b1)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER2CR_OFFSET)
timer2controlreg_wen = 1'b1;
else
timer2controlreg_wen = 1'b0;
end
else
timer2controlreg_wen = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b0) && (pwrite == 1'b0)) begin
if(paddr[TIMER_ADDR_LHS:2] == TIMER2EOI_OFFSET)
timer2eoi_ren = 1'b1;
else
timer2eoi_ren = 1'b0;
end
else
timer2eoi_ren = 1'b0;
end
always @(*)
begin
if((psel == 1'b1) && (penable == 1'b0) && (pwrite == 1'b0)) begin
if(paddr[TIMER_ADDR_LHS:0] == TIMERSEOI_OFFSET)
timerseoi_ren = 1'b1;
else
timerseoi_ren = 1'b0;
end
else
timerseoi_ren = 1'b0;
end
always@(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
timer1loadcount <= {TIMER1_WIDTH{1'b0}};
else if(timer1loadcount_wen == 1'b1)
timer1loadcount <= pwdata[TIMER1_WIDTH-1:0];
else ;
end
always @(*)
begin
ri_timer1loadcount = 32'b0;
ri_timer1loadcount[TIMER1_WIDTH-1:0] = timer1loadcount;
end
always @(*)
begin
ri_timer1currentvalue = 32'b0;
ri_timer1currentvalue[TIMER1_WIDTH-1:0] = timer1currentvalue[TIMER1_WIDTH-1:0];
end
always@(posedge pclk or negedge presetn)
begin
if (presetn == 1'b0)
timer1controlreg <= {TIMER_CTRL_WIDTH{1'b0}};
else if(timer1controlreg_wen == 1'b1)
timer1controlreg <= pwdata[TIMER_CTRL_WIDTH-1:0];
else if(etb_tim1_trig_en_off == 1'b1)
timer1controlreg[0] <= 1'b0;
else if(etb_tim1_trig_en_on == 1'b1)
timer1controlreg[0] <= 1'b1;
else ;
end
always @(*)
begin
ri_timer1controlreg = 32'b0;
ri_timer1controlreg[TIMER_CTRL_WIDTH-1:0] = timer1controlreg;
end
always@(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
timer2loadcount <= {TIMER2_WIDTH{1'b0}};
else if(timer2loadcount_wen == 1'b1)
timer2loadcount <= pwdata[TIMER2_WIDTH-1:0];
else ;
end
always @(*)
begin
ri_timer2loadcount = 32'b0;
ri_timer2loadcount[TIMER2_WIDTH-1:0] = timer2loadcount;
end
always @(*)
begin
ri_timer2currentvalue = 32'b0;
ri_timer2currentvalue[TIMER2_WIDTH-1:0] = timer2currentvalue[TIMER2_WIDTH-1:0];
end
always@(posedge pclk or negedge presetn)
begin
if (presetn == 1'b0)
timer2controlreg <= {TIMER_CTRL_WIDTH{1'b0}};
else if(timer2controlreg_wen == 1'b1)
timer2controlreg <= pwdata[TIMER_CTRL_WIDTH-1:0];
else if(etb_tim2_trig_en_off == 1'b1)
timer2controlreg[0] <= 1'b0;
else if(etb_tim2_trig_en_on == 1'b1)
timer2controlreg[0] <= 1'b1;
else ;
end
always @(*)
begin
ri_timer2controlreg = 32'b0;
ri_timer2controlreg[TIMER_CTRL_WIDTH-1:0] = timer2controlreg;
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
prdata <= 32'b0;
else if((pwrite == 1'b0) && (psel == 1'b1) && (penable == 1'b0)) begin
case (paddr[TIMER_ADDR_LHS:2])
TIMER1LC_OFFSET : prdata <= ri_timer1loadcount;
TIMER1CV_OFFSET : prdata <= ri_timer1currentvalue;
TIMER1CR_OFFSET : prdata <= ri_timer1controlreg;
TIMER1INTST_OFFSET: prdata <= ri_timer1intstatus;
TIMER2LC_OFFSET : prdata <= ri_timer2loadcount;
TIMER2CV_OFFSET : prdata <= ri_timer2currentvalue;
TIMER2CR_OFFSET : prdata <= ri_timer2controlreg;
TIMER2INTST_OFFSET: prdata <= ri_timer2intstatus;
TIMERSINTST_OFFSET: prdata <= ri_timersintstatus;
TIMERSRAW_OFFSET : prdata <= ri_timer_int;
default : prdata <= 32'b0;
endcase
end
else ;
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0) begin
timer1_int_ff1 <= 1'b0;
timer1_int_ff2 <= 1'b0;
timer2_int_ff1 <= 1'b0;
timer2_int_ff2 <= 1'b0;
end
else begin
timer1_int_ff1 <= bus_interrupts[0];
timer2_int_ff1 <= bus_interrupts[1];
timer1_int_ff2 <= timer1_int_ff1;
timer2_int_ff2 <= timer2_int_ff1;
end
end
assign int_sync[0] = (TIMER1_METASTABLE==1) ? timer1_int_ff2 : bus_interrupts[0];
assign int_sync[1] = (TIMER2_METASTABLE==1) ? timer2_int_ff2 : bus_interrupts[1];
assign timer1currentvalue = bus_current_value[31:0];
assign timer2currentvalue = bus_current_value[63:32];
always @(posedge pclk or negedge presetn)
begin
if (presetn == 1'b0)
int_sync_ff1 <= 2'b0;
else
int_sync_ff1 <= int_sync;
end
assign edge_detected = int_sync & (~int_sync_ff1);
assign timereoi = {timer2eoi_ren,timer1eoi_ren};
assign timerseoi = timerseoi_ren;
assign timeren = {timer2controlreg[0],timer1controlreg[0]};
assign timermode = {timer2controlreg[1],timer1controlreg[1]};
assign timerhwen = {timer2controlreg[4],timer1controlreg[4]};
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
timer_int_tmp <= 2'b0;
else begin
for(i=0;i<2;i=i+1) begin
if(edge_detected[i] == 1'b1) begin
if(timeren[i]==1'b1)
timer_int_tmp[i] <= 1'b1;
else
timer_int_tmp[i] <= 1'b0;
end
else if((timereoi[i] == 1'b1) || (timerseoi == 1'b1) || (timeren[i]==1'b0))
timer_int_tmp[i] <= 1'b0;
else ;
end
end
end
always @(*)
begin
ri_timer_int = 32'b0;
ri_timer_int[1:0] = timer_int_tmp;
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
tim1_etb_trig <= 1'b0;
else if(edge_detected[0] ==1'b1)
tim1_etb_trig <= 1'b1;
else
tim1_etb_trig <= 1'b0;
end
always @(posedge pclk or negedge presetn)
begin
if(presetn == 1'b0)
tim2_etb_trig <= 1'b0;
else if(edge_detected[1] ==1'b1)
tim2_etb_trig <= 1'b1;
else
tim2_etb_trig <= 1'b0;
end
assign timerintmask[0] = timer1controlreg[2];
assign timerintmask[1] = timer2controlreg[2];
always @(*)
begin
ri_timer1intstatus = 32'b0;
ri_timer2intstatus = 32'b0;
ri_timersintstatus = 32'b0;
ri_timer1intstatus[0] = ri_timer_int[0] & (~timerintmask[0]);
ri_timer2intstatus[0] = ri_timer_int[1] & (~timerintmask[1]);
ri_timersintstatus[1:0] = ri_timer_int[1:0] & (~timerintmask);
end
assign timer_int_flag = |ri_timersintstatus;
assign timer_int_flag_n = ~timer_int_flag;
assign timer_int = ri_timersintstatus[1:0];
assign timer_int_n = ~timer_int;
assign timer_en = timeren;
assign timer_mode = timermode;
assign timer_hwen = timerhwen;
endmodule |
module timers_frc #
(
parameter TIMER_WIDTH = 8,
parameter TIMER_PULSE_EXTD = 0
)
(
input wire timer_clk ,
input wire timer_resetn ,
input wire timer_en ,
input wire timer_mode ,
input wire timerhwen ,
input wire [TIMER_WIDTH-1:0] load_value ,
output reg [31:0] current_value ,
output reg toggle ,
output wire interrupt ,
output wire timertrig
);
reg rising_edge ;
reg atzero ;
reg [TIMER_WIDTH-1:0] timer ;
reg extend1 ;
reg extend2 ;
reg extend3 ;
wire load ;
wire raw_interrupt ;
wire interrupt_extd1 ;
wire interrupt_extd2 ;
wire interrupt_extd3 ;
always @ (posedge timer_clk or negedge timer_resetn)
begin
if(timer_resetn == 1'b0)
rising_edge <= 1'b0;
else
rising_edge <= timer_en;
end
assign load = ((timer_en == 1'b1) & (rising_edge == 1'b0));
always @ (posedge timer_clk or negedge timer_resetn)
begin
if(timer_resetn == 1'b0)
timer <= {TIMER_WIDTH{1'b1}};
else begin
if(timer_en == 1'b1) begin
if(load == 1'b1)
timer <= load_value;
else begin
if(timer == {TIMER_WIDTH{1'b0}}) begin
if(timer_mode == 1'b0)
timer <= {TIMER_WIDTH{1'b1}};
else
timer <= load_value;
end
else
timer <= timer - {{(TIMER_WIDTH-1){1'b0}},{1'b1}};
end
end
else
timer <= {TIMER_WIDTH{1'b1}};
end
end
always @ (posedge timer_clk or negedge timer_resetn)
begin
if(timer_resetn == 1'b0)
atzero <= 1'b0;
else
atzero <= (timer=={TIMER_WIDTH{1'b0}});
end
assign raw_interrupt = atzero;
assign timertrig = atzero & timerhwen;
always @ (posedge timer_clk or negedge timer_resetn)
begin
if(timer_resetn == 1'b0)
toggle <= 1'b0;
else if(timer=={TIMER_WIDTH{1'b0}})
toggle <= ~toggle;
else ;
end
always @(posedge timer_clk or negedge timer_resetn)
begin
if(timer_resetn == 1'b0) begin
extend1 <= 1'b0;
extend2 <= 1'b0;
extend3 <= 1'b0;
end
else begin
extend1 <= raw_interrupt;
extend2 <= extend1;
extend3 <= extend2;
end
end
assign interrupt_extd1 = raw_interrupt | extend1;
assign interrupt_extd2 = interrupt_extd1 | extend2;
assign interrupt_extd3 = interrupt_extd2 | extend3;
always @(*)
begin
current_value = 32'b0;
if(timer_en == 1'b1)
current_value[TIMER_WIDTH-1:0] = timer;
end
assign interrupt = ((TIMER_PULSE_EXTD == 0) ? raw_interrupt :
((TIMER_PULSE_EXTD == 1) ? interrupt_extd1 :
((TIMER_PULSE_EXTD == 2) ? interrupt_extd2 :
interrupt_extd3)));
endmodule |
module timers_top #
(
`include "timers_params.v"
)
(
pclk ,
presetn ,
penable ,
psel ,
pwrite ,
paddr ,
pwdata ,
scan_mode ,
timer_1_clk ,
timer_2_clk ,
timer_1_resetn ,
timer_2_resetn ,
timer_en ,
timertrig ,
timer_int ,
timer_int_n ,
timer_int_flag ,
timer_int_flag_n ,
etb_tim1_trig_en_on ,
etb_tim1_trig_en_off ,
etb_tim2_trig_en_on ,
etb_tim2_trig_en_off ,
tim1_etb_trig ,
tim2_etb_trig ,
prdata
);
input pclk ;
input presetn ;
input penable ;
input psel ;
input pwrite ;
input [7:0] paddr ;
input [31:0] pwdata ;
input scan_mode ;
input timer_1_clk ;
input timer_1_resetn ;
input timer_2_clk ;
input timer_2_resetn ;
input etb_tim1_trig_en_on ;
input etb_tim1_trig_en_off ;
input etb_tim2_trig_en_on ;
input etb_tim2_trig_en_off ;
output tim1_etb_trig ;
output tim2_etb_trig ;
output [ 1:0] timer_en ;
output [ 1:0] timertrig ;
output [ 1:0] timer_int ;
output [ 1:0] timer_int_n ;
output timer_int_flag ;
output timer_int_flag_n ;
output [31:0] prdata ;
wire [63:0] bus_load_value ;
wire [63:0] bus_current_value ;
wire [1:0] bus_interrupt ;
wire timer_1_clk ;
wire timer_1_resetn ;
wire timer_1_toggle ;
wire timer_2_clk ;
wire timer_2_resetn ;
wire timer_2_toggle ;
wire [TIMER1_WIDTH-1:0] timer1loadcount ;
wire [TIMER2_WIDTH-1:0] timer2loadcount ;
wire [1:0] timer_en ;
wire [1:0] timer_mode ;
wire [1:0] timer_hwen ;
wire [1:0] timer_int ;
wire [1:0] timer_int_n ;
wire timer_int_flag ;
wire timer_int_flag_n ;
timers_apbif U_TIMERS_APBIF
(
.pclk (pclk ),
.presetn (presetn ),
.penable (penable ),
.pwrite (pwrite ),
.pwdata (pwdata ),
.paddr (paddr ),
.psel (psel ),
.timer1loadcount (timer1loadcount ),
.timer2loadcount (timer2loadcount ),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim1_trig_en_off (etb_tim1_trig_en_off ),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig ),
.timer_en (timer_en ),
.timer_mode (timer_mode ),
.timer_hwen (timer_hwen ),
.timer_int_flag (timer_int_flag ),
.timer_int_flag_n (timer_int_flag_n ),
.timer_int (timer_int ),
.timer_int_n (timer_int_n ),
.bus_current_value (bus_current_value ),
.bus_interrupts (bus_interrupt ),
.prdata (prdata )
);
timers_frc #
( .TIMER_WIDTH (TIMER1_WIDTH ),
.TIMER_PULSE_EXTD (TIMER1_PULSE_EXTD )
)
U_TIMER0
(
.timer_clk (timer_1_clk ),
.timer_resetn (timer_1_resetn ),
.timer_en (timer_en[0] ),
.timer_mode (timer_mode[0] ),
.load_value (timer1loadcount ),
.current_value (bus_current_value[31:0] ),
.toggle (timer_1_toggle ),
.interrupt (bus_interrupt[0] ),
.timertrig (timertrig[0] ),
.timerhwen (timer_hwen[0] )
);
timers_frc #
( .TIMER_WIDTH (TIMER2_WIDTH ),
.TIMER_PULSE_EXTD (TIMER2_PULSE_EXTD )
)
U_TIMER1
(
.timer_clk (timer_2_clk ),
.timer_resetn (timer_2_resetn ),
.timer_en (timer_en[1] ),
.timer_mode (timer_mode[1] ),
.load_value (timer2loadcount ),
.current_value (bus_current_value[63:32] ),
.toggle (timer_2_toggle ),
.interrupt (bus_interrupt[1] ),
.timertrig (timertrig[1] ),
.timerhwen (timer_hwen[1] )
);
endmodule |
module apb1_sub_top(
apb1_dummy1_intr,
apb1_dummy2_intr,
apb1_dummy3_intr,
apb1_dummy4_intr,
apb1_dummy5_intr,
apb1_dummy6_intr,
apb1_dummy7_intr,
apb1_dummy8_intr,
apb1_gpio_psel_s5,
apb1_lsbus_s3_hrdata,
apb1_lsbus_s3_hready,
apb1_lsbus_s3_hresp,
apb1_pmu_psel_s15,
apb1_rtc_psel_s6,
apb1_xx_paddr,
apb1_xx_penable,
apb1_xx_pprot,
apb1_xx_pwdata,
apb1_xx_pwrite,
gpio_apb1_prdata,
ioctl_usi1_nss_in,
ioctl_usi1_sclk_in,
ioctl_usi1_sd0_in,
ioctl_usi1_sd1_in,
lsbus_apb1_s3_haddr,
lsbus_apb1_s3_hburst,
lsbus_apb1_s3_hprot,
lsbus_apb1_s3_hsel,
lsbus_apb1_s3_hsize,
lsbus_apb1_s3_htrans,
lsbus_apb1_s3_hwdata,
lsbus_apb1_s3_hwrite,
pmu_apb1_pclk_en,
pmu_apb1_prdata,
pmu_apb1_s3clk,
pmu_apb1_s3rst_b,
pmu_dummy1_p1clk,
pmu_dummy1_p1rst_b,
pmu_dummy2_p1clk,
pmu_dummy2_p1rst_b,
pmu_dummy3_p1clk,
pmu_dummy3_p1rst_b,
pmu_dummy4_p1clk,
pmu_dummy4_p1rst_b,
pmu_dummy5_p1clk,
pmu_dummy5_p1rst_b,
pmu_dummy6_p1clk,
pmu_dummy6_p1rst_b,
pmu_dummy7_p1clk,
pmu_dummy7_p1rst_b,
pmu_dummy8_p1clk,
pmu_dummy8_p1rst_b,
pmu_tim1_p1clk,
pmu_tim1_p1rst_b,
pmu_tim3_p1clk,
pmu_tim3_p1rst_b,
pmu_tim5_p1clk,
pmu_tim5_p1rst_b,
pmu_tim7_p1clk,
pmu_tim7_p1rst_b,
pmu_usi1_p1clk,
pmu_usi1_p1rst_b,
rtc_apb1_prdata,
scan_mode,
tim1_wic_intr,
tim3_wic_intr,
tim5_wic_intr,
tim7_wic_intr,
usi1_ioctl_nss_ie_n,
usi1_ioctl_nss_oe_n,
usi1_ioctl_nss_out,
usi1_ioctl_sclk_ie_n,
usi1_ioctl_sclk_oe_n,
usi1_ioctl_sclk_out,
usi1_ioctl_sd0_ie_n,
usi1_ioctl_sd0_oe_n,
usi1_ioctl_sd0_out,
usi1_ioctl_sd1_ie_n,
usi1_ioctl_sd1_oe_n,
usi1_ioctl_sd1_out,
usi1_wic_intr
);
input [31:0] gpio_apb1_prdata;
input ioctl_usi1_nss_in;
input ioctl_usi1_sclk_in;
input ioctl_usi1_sd0_in;
input ioctl_usi1_sd1_in;
input [31:0] lsbus_apb1_s3_haddr;
input [2 :0] lsbus_apb1_s3_hburst;
input [3 :0] lsbus_apb1_s3_hprot;
input lsbus_apb1_s3_hsel;
input [2 :0] lsbus_apb1_s3_hsize;
input [1 :0] lsbus_apb1_s3_htrans;
input [31:0] lsbus_apb1_s3_hwdata;
input lsbus_apb1_s3_hwrite;
input pmu_apb1_pclk_en;
input [31:0] pmu_apb1_prdata;
input pmu_apb1_s3clk;
input pmu_apb1_s3rst_b;
input pmu_dummy1_p1clk;
input pmu_dummy1_p1rst_b;
input pmu_dummy2_p1clk;
input pmu_dummy2_p1rst_b;
input pmu_dummy3_p1clk;
input pmu_dummy3_p1rst_b;
input pmu_dummy4_p1clk;
input pmu_dummy4_p1rst_b;
input pmu_dummy5_p1clk;
input pmu_dummy5_p1rst_b;
input pmu_dummy6_p1clk;
input pmu_dummy6_p1rst_b;
input pmu_dummy7_p1clk;
input pmu_dummy7_p1rst_b;
input pmu_dummy8_p1clk;
input pmu_dummy8_p1rst_b;
input pmu_tim1_p1clk;
input pmu_tim1_p1rst_b;
input pmu_tim3_p1clk;
input pmu_tim3_p1rst_b;
input pmu_tim5_p1clk;
input pmu_tim5_p1rst_b;
input pmu_tim7_p1clk;
input pmu_tim7_p1rst_b;
input pmu_usi1_p1clk;
input pmu_usi1_p1rst_b;
input [31:0] rtc_apb1_prdata;
input scan_mode;
output apb1_dummy1_intr;
output apb1_dummy2_intr;
output apb1_dummy3_intr;
output apb1_dummy4_intr;
output apb1_dummy5_intr;
output apb1_dummy6_intr;
output apb1_dummy7_intr;
output apb1_dummy8_intr;
output apb1_gpio_psel_s5;
output [31:0] apb1_lsbus_s3_hrdata;
output apb1_lsbus_s3_hready;
output [1 :0] apb1_lsbus_s3_hresp;
output apb1_pmu_psel_s15;
output apb1_rtc_psel_s6;
output [31:0] apb1_xx_paddr;
output apb1_xx_penable;
output [2 :0] apb1_xx_pprot;
output [31:0] apb1_xx_pwdata;
output apb1_xx_pwrite;
output [1 :0] tim1_wic_intr;
output [1 :0] tim3_wic_intr;
output [1 :0] tim5_wic_intr;
output [1 :0] tim7_wic_intr;
output usi1_ioctl_nss_ie_n;
output usi1_ioctl_nss_oe_n;
output usi1_ioctl_nss_out;
output usi1_ioctl_sclk_ie_n;
output usi1_ioctl_sclk_oe_n;
output usi1_ioctl_sclk_out;
output usi1_ioctl_sd0_ie_n;
output usi1_ioctl_sd0_oe_n;
output usi1_ioctl_sd0_out;
output usi1_ioctl_sd1_ie_n;
output usi1_ioctl_sd1_oe_n;
output usi1_ioctl_sd1_out;
output usi1_wic_intr;
wire [3 :0] apb1_burst;
wire apb1_dummy1_intr;
wire apb1_dummy1_psel_s7;
wire apb1_dummy2_intr;
wire apb1_dummy2_psel_s8;
wire apb1_dummy3_intr;
wire apb1_dummy3_psel_s9;
wire apb1_dummy4_intr;
wire apb1_dummy4_psel_s10;
wire apb1_dummy5_intr;
wire apb1_dummy5_psel_s11;
wire apb1_dummy6_intr;
wire apb1_dummy6_psel_s12;
wire apb1_dummy7_intr;
wire apb1_dummy7_psel_s13;
wire apb1_dummy8_intr;
wire apb1_dummy8_psel_s14;
wire apb1_gpio_psel_s5;
wire [31:0] apb1_lsbus_s3_hrdata;
wire apb1_lsbus_s3_hready;
wire [1 :0] apb1_lsbus_s3_hresp;
wire apb1_pmu_psel_s15;
wire apb1_rtc_psel_s6;
wire apb1_sec;
wire [31:0] apb1_tim1_paddr;
wire apb1_tim1_penable;
wire apb1_tim1_psel_s0;
wire [31:0] apb1_tim1_pwdata;
wire apb1_tim1_pwrite;
wire [31:0] apb1_tim3_paddr;
wire apb1_tim3_penable;
wire apb1_tim3_psel_s1;
wire [31:0] apb1_tim3_pwdata;
wire apb1_tim3_pwrite;
wire [31:0] apb1_tim5_paddr;
wire apb1_tim5_penable;
wire apb1_tim5_psel_s2;
wire [31:0] apb1_tim5_pwdata;
wire apb1_tim5_pwrite;
wire [31:0] apb1_tim7_paddr;
wire apb1_tim7_penable;
wire apb1_tim7_psel_s3;
wire [31:0] apb1_tim7_pwdata;
wire apb1_tim7_pwrite;
wire [31:0] apb1_usi1_paddr;
wire apb1_usi1_penable;
wire apb1_usi1_psel_s4;
wire [31:0] apb1_usi1_pwdata;
wire apb1_usi1_pwrite;
wire [31:0] apb1_xx_paddr;
wire apb1_xx_penable;
wire [2 :0] apb1_xx_pprot;
wire [3 :0] apb1_xx_pstrb_s;
wire [31:0] apb1_xx_pwdata;
wire apb1_xx_pwrite;
wire dmac0_usi1_rx_ack;
wire dmac0_usi1_tx_ack;
wire [31:0] dummy1_apb1_prdata;
wire [31:0] dummy2_apb1_prdata;
wire [31:0] dummy3_apb1_prdata;
wire [31:0] dummy4_apb1_prdata;
wire [31:0] dummy5_apb1_prdata;
wire [31:0] dummy6_apb1_prdata;
wire [31:0] dummy7_apb1_prdata;
wire [31:0] dummy8_apb1_prdata;
wire etb_tim1_trig_en_off1;
wire etb_tim1_trig_en_off2;
wire etb_tim1_trig_en_on1;
wire etb_tim1_trig_en_on2;
wire etb_tim3_trig_en_off1;
wire etb_tim3_trig_en_off2;
wire etb_tim3_trig_en_on1;
wire etb_tim3_trig_en_on2;
wire etb_tim5_trig_en_off1;
wire etb_tim5_trig_en_off2;
wire etb_tim5_trig_en_on1;
wire etb_tim5_trig_en_on2;
wire etb_tim7_trig_en_off1;
wire etb_tim7_trig_en_off2;
wire etb_tim7_trig_en_on1;
wire etb_tim7_trig_en_on2;
wire [31:0] gpio_apb1_prdata;
wire ioctl_usi1_nss_in;
wire ioctl_usi1_sclk_in;
wire ioctl_usi1_sd0_in;
wire ioctl_usi1_sd1_in;
wire [31:0] lsbus_apb1_s3_haddr;
wire [2 :0] lsbus_apb1_s3_hburst;
wire [3 :0] lsbus_apb1_s3_hprot;
wire lsbus_apb1_s3_hsel;
wire [2 :0] lsbus_apb1_s3_hsize;
wire [1 :0] lsbus_apb1_s3_htrans;
wire [31:0] lsbus_apb1_s3_hwdata;
wire lsbus_apb1_s3_hwrite;
wire pmu_apb1_pclk_en;
wire [31:0] pmu_apb1_prdata;
wire pmu_apb1_s3clk;
wire pmu_apb1_s3rst_b;
wire pmu_dummy1_p1clk;
wire pmu_dummy1_p1rst_b;
wire pmu_dummy2_p1clk;
wire pmu_dummy2_p1rst_b;
wire pmu_dummy3_p1clk;
wire pmu_dummy3_p1rst_b;
wire pmu_dummy4_p1clk;
wire pmu_dummy4_p1rst_b;
wire pmu_dummy5_p1clk;
wire pmu_dummy5_p1rst_b;
wire pmu_dummy6_p1clk;
wire pmu_dummy6_p1rst_b;
wire pmu_dummy7_p1clk;
wire pmu_dummy7_p1rst_b;
wire pmu_dummy8_p1clk;
wire pmu_dummy8_p1rst_b;
wire pmu_tim1_p1clk;
wire pmu_tim1_p1rst_b;
wire pmu_tim3_p1clk;
wire pmu_tim3_p1rst_b;
wire pmu_tim5_p1clk;
wire pmu_tim5_p1rst_b;
wire pmu_tim7_p1clk;
wire pmu_tim7_p1rst_b;
wire pmu_usi1_p1clk;
wire pmu_usi1_p1rst_b;
wire [31:0] rtc_apb1_prdata;
wire scan_mode;
wire sec_usi1_dmac0_dma_rx_req;
wire sec_usi1_dmac0_dma_tx_req;
wire [31:0] tim1_apb1_prdata;
wire [1 :0] tim1_wic_intr;
wire [31:0] tim3_apb1_prdata;
wire [1 :0] tim3_wic_intr;
wire [31:0] tim5_apb1_prdata;
wire [1 :0] tim5_wic_intr;
wire [31:0] tim7_apb1_prdata;
wire [1 :0] tim7_wic_intr;
wire timer1_tim1_etb_trig;
wire timer1_tim2_etb_trig;
wire timer3_tim1_etb_trig;
wire timer3_tim2_etb_trig;
wire timer5_tim1_etb_trig;
wire timer5_tim2_etb_trig;
wire timer7_tim1_etb_trig;
wire timer7_tim2_etb_trig;
wire tipc_tim1_trust;
wire tipc_tim3_trust;
wire tipc_tim5_trust;
wire tipc_tim7_trust;
wire tipc_usi1_trust;
wire [31:0] usi1_apb1_prdata;
wire usi1_dmac0_dma_rx_req;
wire usi1_dmac0_dma_tx_req;
wire usi1_etb_rx_trig;
wire usi1_etb_tx_trig;
wire usi1_ioctl_nss_ie_n;
wire usi1_ioctl_nss_oe_n;
wire usi1_ioctl_nss_out;
wire usi1_ioctl_sclk_ie_n;
wire usi1_ioctl_sclk_oe_n;
wire usi1_ioctl_sclk_out;
wire usi1_ioctl_sd0_ie_n;
wire usi1_ioctl_sd0_oe_n;
wire usi1_ioctl_sd0_out;
wire usi1_ioctl_sd1_ie_n;
wire usi1_ioctl_sd1_oe_n;
wire usi1_ioctl_sd1_out;
wire usi1_wic_intr;
assign apb1_sec = 1'b1;
assign apb1_burst[3:0] = {1'b0,lsbus_apb1_s3_hburst[2:0]};
csky_apb1_top x_apb1_sub_top (
.haddr (lsbus_apb1_s3_haddr ),
.hburst (apb1_burst ),
.hclk (pmu_apb1_s3clk ),
.hprot (lsbus_apb1_s3_hprot ),
.hrdata (apb1_lsbus_s3_hrdata),
.hreadyin (1'b1 ),
.hreadyout (apb1_lsbus_s3_hready),
.hresp (apb1_lsbus_s3_hresp ),
.hrst_n (pmu_apb1_s3rst_b ),
.hsec (apb1_sec ),
.hsel (lsbus_apb1_s3_hsel ),
.hsize (lsbus_apb1_s3_hsize ),
.htrans (lsbus_apb1_s3_htrans),
.hwdata (lsbus_apb1_s3_hwdata),
.hwrite (lsbus_apb1_s3_hwrite),
.paddr_s (apb1_xx_paddr ),
.pclk_en (pmu_apb1_pclk_en ),
.penable_s (apb1_xx_penable ),
.pprot_s (apb1_xx_pprot ),
.prdata_s0 (tim1_apb1_prdata ),
.prdata_s1 (tim3_apb1_prdata ),
.prdata_s10 (dummy4_apb1_prdata ),
.prdata_s11 (dummy5_apb1_prdata ),
.prdata_s12 (dummy6_apb1_prdata ),
.prdata_s13 (dummy7_apb1_prdata ),
.prdata_s14 (dummy8_apb1_prdata ),
.prdata_s15 (pmu_apb1_prdata ),
.prdata_s2 (tim5_apb1_prdata ),
.prdata_s3 (tim7_apb1_prdata ),
.prdata_s4 (usi1_apb1_prdata ),
.prdata_s5 (gpio_apb1_prdata ),
.prdata_s6 (rtc_apb1_prdata ),
.prdata_s7 (dummy1_apb1_prdata ),
.prdata_s8 (dummy2_apb1_prdata ),
.prdata_s9 (dummy3_apb1_prdata ),
.pready_s0 (1'b1 ),
.pready_s1 (1'b1 ),
.pready_s10 (1'b1 ),
.pready_s11 (1'b1 ),
.pready_s12 (1'b1 ),
.pready_s13 (1'b1 ),
.pready_s14 (1'b1 ),
.pready_s15 (1'b1 ),
.pready_s2 (1'b1 ),
.pready_s3 (1'b1 ),
.pready_s4 (1'b1 ),
.pready_s5 (1'b1 ),
.pready_s6 (1'b1 ),
.pready_s7 (1'b1 ),
.pready_s8 (1'b1 ),
.pready_s9 (1'b1 ),
.psel_s0 (apb1_tim1_psel_s0 ),
.psel_s1 (apb1_tim3_psel_s1 ),
.psel_s10 (apb1_dummy4_psel_s10),
.psel_s11 (apb1_dummy5_psel_s11),
.psel_s12 (apb1_dummy6_psel_s12),
.psel_s13 (apb1_dummy7_psel_s13),
.psel_s14 (apb1_dummy8_psel_s14),
.psel_s15 (apb1_pmu_psel_s15 ),
.psel_s2 (apb1_tim5_psel_s2 ),
.psel_s3 (apb1_tim7_psel_s3 ),
.psel_s4 (apb1_usi1_psel_s4 ),
.psel_s5 (apb1_gpio_psel_s5 ),
.psel_s6 (apb1_rtc_psel_s6 ),
.psel_s7 (apb1_dummy1_psel_s7 ),
.psel_s8 (apb1_dummy2_psel_s8 ),
.psel_s9 (apb1_dummy3_psel_s9 ),
.pselverr_s0 (1'b0 ),
.pselverr_s1 (1'b0 ),
.pselverr_s10 (1'b0 ),
.pselverr_s11 (1'b0 ),
.pselverr_s12 (1'b0 ),
.pselverr_s13 (1'b0 ),
.pselverr_s14 (1'b0 ),
.pselverr_s15 (1'b0 ),
.pselverr_s2 (1'b0 ),
.pselverr_s3 (1'b0 ),
.pselverr_s4 (1'b0 ),
.pselverr_s5 (1'b0 ),
.pselverr_s6 (1'b0 ),
.pselverr_s7 (1'b0 ),
.pselverr_s8 (1'b0 ),
.pselverr_s9 (1'b0 ),
.pstrb_s (apb1_xx_pstrb_s ),
.pwdata_s (apb1_xx_pwdata ),
.pwrite_s (apb1_xx_pwrite )
);
tim1_sec_top x_tim1_sec_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off1),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on1 ),
.etb_tim2_trig_en_off (etb_tim1_trig_en_off2),
.etb_tim2_trig_en_on (etb_tim1_trig_en_on2 ),
.intr (tim1_wic_intr ),
.paddr (apb1_tim1_paddr ),
.pclk (pmu_tim1_p1clk ),
.penable (apb1_tim1_penable ),
.pprot (apb1_xx_pprot ),
.prdata (tim1_apb1_prdata ),
.presetn (pmu_tim1_p1rst_b ),
.psel (apb1_tim1_psel_s0 ),
.pwdata (apb1_tim1_pwdata ),
.pwrite (apb1_tim1_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (timer1_tim1_etb_trig ),
.tim2_etb_trig (timer1_tim2_etb_trig ),
.tipc_tim1_trust (tipc_tim1_trust )
);
tim3_sec_top x_tim3_sec_top (
.etb_tim1_trig_en_off (etb_tim3_trig_en_off1),
.etb_tim1_trig_en_on (etb_tim3_trig_en_on1 ),
.etb_tim2_trig_en_off (etb_tim3_trig_en_off2),
.etb_tim2_trig_en_on (etb_tim3_trig_en_on2 ),
.intr (tim3_wic_intr ),
.paddr (apb1_tim3_paddr ),
.pclk (pmu_tim3_p1clk ),
.penable (apb1_tim3_penable ),
.pprot (apb1_xx_pprot ),
.prdata (tim3_apb1_prdata ),
.presetn (pmu_tim3_p1rst_b ),
.psel (apb1_tim3_psel_s1 ),
.pwdata (apb1_tim3_pwdata ),
.pwrite (apb1_tim3_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (timer3_tim1_etb_trig ),
.tim2_etb_trig (timer3_tim2_etb_trig ),
.tipc_tim3_trust (tipc_tim3_trust )
);
tim5_sec_top x_tim5_sec_top (
.etb_tim1_trig_en_off (etb_tim5_trig_en_off1),
.etb_tim1_trig_en_on (etb_tim5_trig_en_on1 ),
.etb_tim2_trig_en_off (etb_tim5_trig_en_off2),
.etb_tim2_trig_en_on (etb_tim5_trig_en_on2 ),
.intr (tim5_wic_intr ),
.paddr (apb1_tim5_paddr ),
.pclk (pmu_tim5_p1clk ),
.penable (apb1_tim5_penable ),
.pprot (apb1_xx_pprot ),
.prdata (tim5_apb1_prdata ),
.presetn (pmu_tim5_p1rst_b ),
.psel (apb1_tim5_psel_s2 ),
.pwdata (apb1_tim5_pwdata ),
.pwrite (apb1_tim5_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (timer5_tim1_etb_trig ),
.tim2_etb_trig (timer5_tim2_etb_trig ),
.tipc_tim5_trust (tipc_tim5_trust )
);
tim7_sec_top x_tim7_sec_top (
.etb_tim1_trig_en_off (etb_tim7_trig_en_off1),
.etb_tim1_trig_en_on (etb_tim7_trig_en_on1 ),
.etb_tim2_trig_en_off (etb_tim7_trig_en_off2),
.etb_tim2_trig_en_on (etb_tim7_trig_en_on2 ),
.intr (tim7_wic_intr ),
.paddr (apb1_tim7_paddr ),
.pclk (pmu_tim7_p1clk ),
.penable (apb1_tim7_penable ),
.pprot (apb1_xx_pprot ),
.prdata (tim7_apb1_prdata ),
.presetn (pmu_tim7_p1rst_b ),
.psel (apb1_tim7_psel_s3 ),
.pwdata (apb1_tim7_pwdata ),
.pwrite (apb1_tim7_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (timer7_tim1_etb_trig ),
.tim2_etb_trig (timer7_tim2_etb_trig ),
.tipc_tim7_trust (tipc_tim7_trust )
);
usi1_sec_top x_usi1_sec_top (
.clk (pmu_usi1_p1clk ),
.dma_ack_rx (dmac0_usi1_rx_ack ),
.dma_ack_tx (dmac0_usi1_tx_ack ),
.dma_req_rx (usi1_dmac0_dma_rx_req ),
.dma_req_tx (usi1_dmac0_dma_tx_req ),
.nss_ie_n (usi1_ioctl_nss_ie_n ),
.nss_in (ioctl_usi1_nss_in ),
.nss_oe_n (usi1_ioctl_nss_oe_n ),
.nss_out (usi1_ioctl_nss_out ),
.paddr (apb1_usi1_paddr ),
.penable (apb1_usi1_penable ),
.pprot (apb1_xx_pprot ),
.prdata (usi1_apb1_prdata ),
.psel (apb1_usi1_psel_s4 ),
.pwdata (apb1_usi1_pwdata ),
.pwrite (apb1_usi1_pwrite ),
.rst_n (pmu_usi1_p1rst_b ),
.sclk_ie_n (usi1_ioctl_sclk_ie_n ),
.sclk_in (ioctl_usi1_sclk_in ),
.sclk_oe_n (usi1_ioctl_sclk_oe_n ),
.sclk_out (usi1_ioctl_sclk_out ),
.sd0_ie_n (usi1_ioctl_sd0_ie_n ),
.sd0_in (ioctl_usi1_sd0_in ),
.sd0_oe_n (usi1_ioctl_sd0_oe_n ),
.sd0_out (usi1_ioctl_sd0_out ),
.sd1_ie_n (usi1_ioctl_sd1_ie_n ),
.sd1_in (ioctl_usi1_sd1_in ),
.sd1_oe_n (usi1_ioctl_sd1_oe_n ),
.sd1_out (usi1_ioctl_sd1_out ),
.sec_rx_req (sec_usi1_dmac0_dma_rx_req),
.sec_tx_req (sec_usi1_dmac0_dma_tx_req),
.tipc_usi1_trust (tipc_usi1_trust ),
.usi_etb_rx_trig (usi1_etb_rx_trig ),
.usi_etb_tx_trig (usi1_etb_tx_trig ),
.usi_intr (usi1_wic_intr )
);
apb_dummy_top x_apb1_dummy_top1 (
.intr (apb1_dummy1_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy1_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy1_apb1_prdata ),
.presetn (pmu_dummy1_p1rst_b ),
.psel (apb1_dummy1_psel_s7),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top2 (
.intr (apb1_dummy2_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy2_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy2_apb1_prdata ),
.presetn (pmu_dummy2_p1rst_b ),
.psel (apb1_dummy2_psel_s8),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top3 (
.intr (apb1_dummy3_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy3_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy3_apb1_prdata ),
.presetn (pmu_dummy3_p1rst_b ),
.psel (apb1_dummy3_psel_s9),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top4 (
.intr (apb1_dummy4_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy4_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy4_apb1_prdata ),
.presetn (pmu_dummy4_p1rst_b ),
.psel (apb1_dummy4_psel_s10),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top5 (
.intr (apb1_dummy5_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy5_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy5_apb1_prdata ),
.presetn (pmu_dummy5_p1rst_b ),
.psel (apb1_dummy5_psel_s11),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top6 (
.intr (apb1_dummy6_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy6_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy6_apb1_prdata ),
.presetn (pmu_dummy6_p1rst_b ),
.psel (apb1_dummy6_psel_s12),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top7 (
.intr (apb1_dummy7_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy7_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy7_apb1_prdata ),
.presetn (pmu_dummy7_p1rst_b ),
.psel (apb1_dummy7_psel_s13),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
apb_dummy_top x_apb1_dummy_top8 (
.intr (apb1_dummy8_intr ),
.paddr (apb1_xx_paddr ),
.pclk (pmu_dummy8_p1clk ),
.penable (apb1_xx_penable ),
.pprot (apb1_xx_pprot ),
.prdata (dummy8_apb1_prdata ),
.presetn (pmu_dummy8_p1rst_b ),
.psel (apb1_dummy8_psel_s14),
.pwdata (apb1_xx_pwdata ),
.pwrite (apb1_xx_pwrite )
);
assign apb1_tim1_pwrite = apb1_xx_pwrite;
assign apb1_tim3_pwrite = apb1_xx_pwrite;
assign apb1_tim5_pwrite = apb1_xx_pwrite;
assign apb1_tim7_pwrite = apb1_xx_pwrite;
assign apb1_usi1_pwrite = apb1_xx_pwrite;
assign apb1_tim1_penable = apb1_xx_penable;
assign apb1_tim3_penable = apb1_xx_penable;
assign apb1_tim5_penable = apb1_xx_penable;
assign apb1_tim7_penable = apb1_xx_penable;
assign apb1_usi1_penable = apb1_xx_penable;
assign apb1_tim1_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_tim3_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_tim5_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_tim7_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_usi1_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_tim1_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_tim3_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_tim5_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_tim7_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_usi1_paddr[31:0] = apb1_xx_paddr[31:0];
assign etb_tim1_trig_en_off1 = 1'b0;
assign etb_tim1_trig_en_off2 = 1'b0;
assign etb_tim1_trig_en_on1 = 1'b0;
assign etb_tim1_trig_en_on2 = 1'b0;
assign etb_tim3_trig_en_off1 = 1'b0;
assign etb_tim3_trig_en_off2 = 1'b0;
assign etb_tim3_trig_en_on1 = 1'b0;
assign etb_tim3_trig_en_on2 = 1'b0;
assign etb_tim5_trig_en_off1 = 1'b0;
assign etb_tim5_trig_en_off2 = 1'b0;
assign etb_tim5_trig_en_on1 = 1'b0;
assign etb_tim5_trig_en_on2 = 1'b0;
assign etb_tim7_trig_en_off1 = 1'b0;
assign etb_tim7_trig_en_off2 = 1'b0;
assign etb_tim7_trig_en_on1 = 1'b0;
assign etb_tim7_trig_en_on2 = 1'b0;
assign dmac0_usi1_rx_ack = 1'b0;
assign dmac0_usi1_tx_ack = 1'b0;
assign tipc_tim1_trust = 1'b0;
assign tipc_tim3_trust = 1'b0;
assign tipc_tim5_trust = 1'b0;
assign tipc_tim7_trust = 1'b0;
assign tipc_usi1_trust = 1'b0;
endmodule |
module tim1_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim1_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim1_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim1_trust;
tim1_tim_top x_tim1_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module apb1_leaf_mux #
(
`include "apb1_params.v"
)
(
input wire i_root_psel ,
input wire [31:0] i_root_paddr ,
input wire i_root_penable ,
input wire [31:0] i_root_pwdata ,
input wire [ 3:0] i_root_pstrb ,
input wire i_root_pwrite ,
input wire [ 2:0] i_root_pprot ,
input wire [ APB_LEAF_SLV_NUM-1:0] i_leaf_slave_pready ,
input wire [ APB_LEAF_SLV_NUM-1:0] i_leaf_slave_pslverr ,
input wire [32*APB_LEAF_SLV_NUM-1:0] i_leaf_slave_prdata ,
output wire o_root_pready ,
output wire o_root_pslverr ,
output reg [31:0] o_root_prdata ,
output wire [ APB_LEAF_SLV_NUM-1:0] o_leaf_slave_psel ,
output wire [31:0] o_leaf_slave_paddr ,
output wire o_leaf_slave_penable ,
output wire [31:0] o_leaf_slave_pwdata ,
output wire [ 3:0] o_leaf_slave_pstrb ,
output wire o_leaf_slave_pwrite ,
output wire [ 2:0] o_leaf_slave_pprot
);
wire [15:0] leaf_psel ;
wire root_pready_normal ;
wire root_pready_abnormal ;
wire root_pslverr_normal ;
wire root_pslverr_abnormal ;
integer i ;
assign leaf_psel[ 0] = (i_root_paddr >= APB_LEAF_SLV0_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV0_END_ADDR);
assign leaf_psel[ 1] = (i_root_paddr >= APB_LEAF_SLV1_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV1_END_ADDR);
assign leaf_psel[ 2] = (i_root_paddr >= APB_LEAF_SLV2_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV2_END_ADDR);
assign leaf_psel[ 3] = (i_root_paddr >= APB_LEAF_SLV3_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV3_END_ADDR);
assign leaf_psel[ 4] = (i_root_paddr >= APB_LEAF_SLV4_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV4_END_ADDR);
assign leaf_psel[ 5] = (i_root_paddr >= APB_LEAF_SLV5_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV5_END_ADDR);
assign leaf_psel[ 6] = (i_root_paddr >= APB_LEAF_SLV6_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV6_END_ADDR);
assign leaf_psel[ 7] = (i_root_paddr >= APB_LEAF_SLV7_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV7_END_ADDR);
assign leaf_psel[ 8] = (i_root_paddr >= APB_LEAF_SLV8_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV8_END_ADDR);
assign leaf_psel[ 9] = (i_root_paddr >= APB_LEAF_SLV9_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV9_END_ADDR);
assign leaf_psel[10] = (i_root_paddr >= APB_LEAF_SLV10_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV10_END_ADDR);
assign leaf_psel[11] = (i_root_paddr >= APB_LEAF_SLV11_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV11_END_ADDR);
assign leaf_psel[12] = (i_root_paddr >= APB_LEAF_SLV12_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV12_END_ADDR);
assign leaf_psel[13] = (i_root_paddr >= APB_LEAF_SLV13_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV13_END_ADDR);
assign leaf_psel[14] = (i_root_paddr >= APB_LEAF_SLV14_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV14_END_ADDR);
assign leaf_psel[15] = (i_root_paddr >= APB_LEAF_SLV15_START_ADDR) & (i_root_paddr <= APB_LEAF_SLV15_END_ADDR);
assign o_leaf_slave_psel = (i_root_psel == 1'b1) ? leaf_psel[APB_LEAF_SLV_NUM-1:0] :
{APB_LEAF_SLV_NUM{1'b0}};
assign root_pready_normal = |(leaf_psel[APB_LEAF_SLV_NUM-1:0] & i_leaf_slave_pready);
assign root_pslverr_normal = |(leaf_psel[APB_LEAF_SLV_NUM-1:0] & i_leaf_slave_pslverr);
assign root_pready_abnormal = i_root_psel & (~(|leaf_psel));
assign root_pslverr_abnormal = root_pready_abnormal;
assign o_root_pready = root_pready_normal | root_pready_abnormal;
assign o_root_pslverr = root_pslverr_normal | root_pslverr_abnormal;
always @(*)
begin: PRDATA_MUX_PROC
o_root_prdata = i_leaf_slave_prdata[31:0];
for(i=1;i<APB_LEAF_SLV_NUM;i=i+1) begin
if(leaf_psel[i]==1'b1) begin
o_root_prdata = i_leaf_slave_prdata >> (i*32);
end
end
end
assign o_leaf_slave_paddr = i_root_paddr;
assign o_leaf_slave_penable = i_root_penable;
assign o_leaf_slave_pwdata = i_root_pwdata;
assign o_leaf_slave_pstrb = i_root_pstrb;
assign o_leaf_slave_pwrite = i_root_pwrite;
assign o_leaf_slave_pprot = i_root_pprot;
endmodule |
module apb1_state_ctrl
(
input wire i_hclk ,
input wire i_hrst_n ,
input wire i_pclk_en ,
input wire i_slave_hsel ,
input wire i_slave_hreadyin ,
input wire [31:0] i_slave_haddr ,
input wire i_slave_hwrite ,
input wire [ 1:0] i_slave_htrans ,
input wire [ 2:0] i_slave_hsize ,
input wire [ 3:0] i_slave_hburst ,
input wire [ 3:0] i_slave_hprot ,
input wire i_slave_hsec ,
input wire [31:0] i_slave_hwdata ,
input wire i_root_pready ,
input wire i_root_pslverr ,
input wire [31:0] i_root_prdata ,
output reg o_slave_hreadyout ,
output wire [ 1:0] o_slave_hresp ,
output reg [31:0] o_slave_hrdata ,
output reg o_root_psel ,
output reg [31:0] o_root_paddr ,
output reg o_root_penable ,
output reg [31:0] o_root_pwdata ,
output reg [ 3:0] o_root_pstrb ,
output reg o_root_pwrite ,
output reg [ 2:0] o_root_pprot
);
parameter IDLE = 7'b0000001;
parameter WTW = 7'b0000010;
parameter SPW = 7'b0000100;
parameter ASW = 7'b0001000;
parameter WTR = 7'b0010000;
parameter SPR = 7'b0100000;
parameter ASR = 7'b1000000;
reg pslverr_ff ;
reg [ 6:0] cstate ;
reg [ 6:0] nstate ;
reg hwdata_vld ;
reg nstate_spw ;
reg nstate_spr ;
reg nstate_asw ;
reg nstate_asr ;
reg [ 3:0] byte_en ;
wire ahb_req ;
assign ahb_req = i_slave_hsel & i_slave_htrans[1] & i_slave_hreadyin;
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_slave_hreadyout <= 1'b1;
else if(o_slave_hreadyout == 1'b1)
o_slave_hreadyout <= ~ahb_req;
else if(o_root_penable == 1'b1 && i_pclk_en == 1'b1)
o_slave_hreadyout <= i_root_pready;
else ;
end
assign pslverr = o_root_psel & o_root_penable & i_root_pready & i_root_pslverr;
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
pslverr_ff <= 1'b0;
else if(i_pclk_en == 1'b1)
pslverr_ff <= pslverr;
else if(o_slave_hreadyout == 1'b1)
pslverr_ff <= 1'b0;
else ;
end
assign o_slave_hresp = {1'b0, (pslverr & i_pclk_en) | pslverr_ff};
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_slave_hrdata <= 32'b0;
else if(i_root_pready == 1'b1 && cstate == ASR)
o_slave_hrdata <= i_root_prdata;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_psel <= 1'b0;
else if(nstate_spw == 1'b1 || nstate_spr == 1'b1)
o_root_psel <= 1'b1;
else if(o_root_penable == 1'b1 && i_root_pready == 1'b1 && i_pclk_en == 1'b1)
o_root_psel <= 1'b0;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_paddr <= 32'b0;
else if(o_slave_hreadyout == 1'b1)
o_root_paddr <= i_slave_haddr;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_penable <= 1'b0;
else if(nstate_asw == 1'b1 || nstate_asr == 1'b1)
o_root_penable <= 1'b1;
else if(i_root_pready == 1'b1 && i_pclk_en == 1'b1)
o_root_penable <= 1'b0;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
hwdata_vld <= 1'b0;
else if(o_slave_hreadyout == 1'b1 && ahb_req == 1'b1 && i_slave_hwrite == 1'b1)
hwdata_vld <= 1'b1;
else
hwdata_vld <= 1'b0;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_pwdata <= 32'b0;
else if(hwdata_vld == 1'b1)
o_root_pwdata <= i_slave_hwdata;
else ;
end
always @(*)
begin
case(i_slave_haddr[1:0])
2'b00: begin
if(i_slave_hsize == 3'b0)
byte_en = 4'b0001;
else if(i_slave_hsize == 3'b001)
byte_en = 4'b0011;
else if(i_slave_hsize == 3'b010)
byte_en = 4'b1111;
else
byte_en = 4'b0;
end
2'b01: begin
if(i_slave_hsize == 3'b0)
byte_en = 4'b0010;
else
byte_en = 4'b0;
end
2'b10: begin
if(i_slave_hsize == 3'b0)
byte_en = 4'b0100;
else if(i_slave_hsize == 3'b001)
byte_en = 4'b1100;
else
byte_en = 4'b0;
end
default: begin
if(i_slave_hsize == 3'b0)
byte_en = 4'b1000;
else
byte_en = 4'b0;
end
endcase
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_pstrb <= 4'b0;
else if(o_slave_hreadyout == 1'b1)
o_root_pstrb <= byte_en;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_pwrite <= 1'b0;
else if(o_slave_hreadyout == 1'b1)
o_root_pwrite <= i_slave_hwrite;
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
o_root_pprot <= 3'b0;
else if(o_slave_hreadyout == 1'b1)
o_root_pprot <= {~i_slave_hprot[0], ~i_slave_hsec, i_slave_hprot[1]};
else ;
end
always @(posedge i_hclk or negedge i_hrst_n)
begin
if(i_hrst_n == 1'b0)
cstate <= IDLE;
else
cstate <= nstate;
end
always @(*)
begin
case(cstate)
IDLE: begin
if(ahb_req == 1'b1 && i_slave_hwrite == 1'b1)
nstate = WTW;
else if(ahb_req == 1'b1 && i_slave_hwrite == 1'b0 && i_pclk_en == 1'b1)
nstate = SPR;
else if(ahb_req == 1'b1 && i_slave_hwrite == 1'b0 && i_pclk_en == 1'b0)
nstate = WTR;
else
nstate = IDLE;
end
WTW: begin
if(i_pclk_en == 1'b1)
nstate = SPW;
else
nstate = WTW;
end
SPW: begin
if(i_pclk_en == 1'b1)
nstate = ASW;
else
nstate = SPW;
end
ASW,
ASR: begin
if(i_root_pready == 1'b1 && i_pclk_en == 1'b1)
nstate = IDLE;
else
nstate = cstate;
end
WTR: begin
if(i_pclk_en == 1'b1)
nstate = SPR;
else
nstate = WTR;
end
SPR: begin
if(i_pclk_en == 1'b1)
nstate = ASR;
else
nstate = SPR;
end
default: nstate = IDLE;
endcase
end
always @(*)
begin
if(cstate == WTW && i_pclk_en == 1'b1)
nstate_spw = 1'b1;
else if(cstate == SPW && i_pclk_en == 1'b0)
nstate_spw = 1'b1;
else
nstate_spw = 1'b0;
end
always @(*)
begin
if(cstate == IDLE && (ahb_req == 1'b1 && i_slave_hwrite == 1'b0 && i_pclk_en == 1'b1))
nstate_spr = 1'b1;
else if(cstate == WTR && i_pclk_en == 1'b1)
nstate_spr = 1'b1;
else if(cstate == SPR && i_pclk_en == 1'b0)
nstate_spr = 1'b1;
else
nstate_spr = 1'b0;
end
always @(*)
begin
if(cstate == SPW && i_pclk_en == 1'b1)
nstate_asw = 1'b1;
else if(cstate == ASW && (i_root_pready == 1'b0 || i_pclk_en == 1'b0))
nstate_asw = 1'b1;
else
nstate_asw = 1'b0;
end
always @(*)
begin
if(cstate == SPR && i_pclk_en == 1'b1)
nstate_asr = 1'b1;
else if(cstate == ASR && (i_root_pready == 1'b0 || i_pclk_en == 1'b0))
nstate_asr = 1'b1;
else
nstate_asr = 1'b0;
end
endmodule |
module csky_apb1_top #
(
`include "apb1_params.v"
)
(
hclk ,
hrst_n ,
pclk_en ,
hsel ,
hreadyin ,
haddr ,
hwrite ,
htrans ,
hsize ,
hburst ,
hprot ,
hsec ,
hwdata ,
psel_s0 ,
pready_s0 ,
pselverr_s0 ,
prdata_s0 ,
psel_s1 ,
pready_s1 ,
pselverr_s1 ,
prdata_s1 ,
psel_s2 ,
pready_s2 ,
pselverr_s2 ,
prdata_s2 ,
psel_s3 ,
pready_s3 ,
pselverr_s3 ,
prdata_s3 ,
psel_s4 ,
pready_s4 ,
pselverr_s4 ,
prdata_s4 ,
psel_s5 ,
pready_s5 ,
pselverr_s5 ,
prdata_s5 ,
psel_s6 ,
pready_s6 ,
pselverr_s6 ,
prdata_s6 ,
psel_s7 ,
pready_s7 ,
pselverr_s7 ,
prdata_s7 ,
psel_s8 ,
pready_s8 ,
pselverr_s8 ,
prdata_s8 ,
psel_s9 ,
pready_s9 ,
pselverr_s9 ,
prdata_s9 ,
psel_s10 ,
pready_s10 ,
pselverr_s10 ,
prdata_s10 ,
psel_s11 ,
pready_s11 ,
pselverr_s11 ,
prdata_s11 ,
psel_s12 ,
pready_s12 ,
pselverr_s12 ,
prdata_s12 ,
psel_s13 ,
pready_s13 ,
pselverr_s13 ,
prdata_s13 ,
psel_s14 ,
pready_s14 ,
pselverr_s14 ,
prdata_s14 ,
psel_s15 ,
pready_s15 ,
pselverr_s15 ,
prdata_s15 ,
hreadyout ,
hresp ,
hrdata ,
paddr_s ,
penable_s ,
pwdata_s ,
pstrb_s ,
pwrite_s ,
pprot_s
);
input hclk ;
input hrst_n ;
input pclk_en ;
input hsel ;
input hreadyin ;
input [31:0] haddr ;
input hwrite ;
input [ 1:0] htrans ;
input [ 2:0] hsize ;
input [ 3:0] hburst ;
input [ 3:0] hprot ;
input hsec ;
input [31:0] hwdata ;
output psel_s0 ;
input pready_s0 ;
input pselverr_s0 ;
input [31:0] prdata_s0 ;
output psel_s1 ;
input pready_s1 ;
input pselverr_s1 ;
input [31:0] prdata_s1 ;
output psel_s2 ;
input pready_s2 ;
input pselverr_s2 ;
input [31:0] prdata_s2 ;
output psel_s3 ;
input pready_s3 ;
input pselverr_s3 ;
input [31:0] prdata_s3 ;
output psel_s4 ;
input pready_s4 ;
input pselverr_s4 ;
input [31:0] prdata_s4 ;
output psel_s5 ;
input pready_s5 ;
input pselverr_s5 ;
input [31:0] prdata_s5 ;
output psel_s6 ;
input pready_s6 ;
input pselverr_s6 ;
input [31:0] prdata_s6 ;
output psel_s7 ;
input pready_s7 ;
input pselverr_s7 ;
input [31:0] prdata_s7 ;
output psel_s8 ;
input pready_s8 ;
input pselverr_s8 ;
input [31:0] prdata_s8 ;
output psel_s9 ;
input pready_s9 ;
input pselverr_s9 ;
input [31:0] prdata_s9 ;
output psel_s10 ;
input pready_s10 ;
input pselverr_s10 ;
input [31:0] prdata_s10 ;
output psel_s11 ;
input pready_s11 ;
input pselverr_s11 ;
input [31:0] prdata_s11 ;
output psel_s12 ;
input pready_s12 ;
input pselverr_s12 ;
input [31:0] prdata_s12 ;
output psel_s13 ;
input pready_s13 ;
input pselverr_s13 ;
input [31:0] prdata_s13 ;
output psel_s14 ;
input pready_s14 ;
input pselverr_s14 ;
input [31:0] prdata_s14 ;
output psel_s15 ;
input pready_s15 ;
input pselverr_s15 ;
input [31:0] prdata_s15 ;
output hreadyout ;
output [ 1:0] hresp ;
output [31:0] hrdata ;
output [31:0] paddr_s ;
output penable_s ;
output [31:0] pwdata_s ;
output [ 3:0] pstrb_s ;
output pwrite_s ;
output [ 2:0] pprot_s ;
wire psel_s0 ;
wire pready_s0 ;
wire pselverr_s0 ;
wire [31:0] prdata_s0 ;
wire psel_s1 ;
wire pready_s1 ;
wire pselverr_s1 ;
wire [31:0] prdata_s1 ;
wire psel_s2 ;
wire pready_s2 ;
wire pselverr_s2 ;
wire [31:0] prdata_s2 ;
wire psel_s3 ;
wire pready_s3 ;
wire pselverr_s3 ;
wire [31:0] prdata_s3 ;
wire psel_s4 ;
wire pready_s4 ;
wire pselverr_s4 ;
wire [31:0] prdata_s4 ;
wire psel_s5 ;
wire pready_s5 ;
wire pselverr_s5 ;
wire [31:0] prdata_s5 ;
wire psel_s6 ;
wire pready_s6 ;
wire pselverr_s6 ;
wire [31:0] prdata_s6 ;
wire psel_s7 ;
wire pready_s7 ;
wire pselverr_s7 ;
wire [31:0] prdata_s7 ;
wire psel_s8 ;
wire pready_s8 ;
wire pselverr_s8 ;
wire [31:0] prdata_s8 ;
wire psel_s9 ;
wire pready_s9 ;
wire pselverr_s9 ;
wire [31:0] prdata_s9 ;
wire psel_s10 ;
wire pready_s10 ;
wire pselverr_s10 ;
wire [31:0] prdata_s10 ;
wire psel_s11 ;
wire pready_s11 ;
wire pselverr_s11 ;
wire [31:0] prdata_s11 ;
wire psel_s12 ;
wire pready_s12 ;
wire pselverr_s12 ;
wire [31:0] prdata_s12 ;
wire psel_s13 ;
wire pready_s13 ;
wire pselverr_s13 ;
wire [31:0] prdata_s13 ;
wire psel_s14 ;
wire pready_s14 ;
wire pselverr_s14 ;
wire [31:0] prdata_s14 ;
wire psel_s15 ;
wire pready_s15 ;
wire pselverr_s15 ;
wire [31:0] prdata_s15 ;
wire hreadyout ;
wire [ 1:0] hresp ;
wire [31:0] hrdata ;
wire [31:0] paddr_s ;
wire penable_s ;
wire [31:0] pwdata_s ;
wire [ 3:0] pstrb_s ;
wire pwrite_s ;
wire [ 2:0] pprot_s ;
wire root_psel ;
wire [31:0] root_paddr ;
wire root_penable ;
wire [31:0] root_pwdata ;
wire [ 3:0] root_pstrb ;
wire root_pwrite ;
wire [ 2:0] root_pprot ;
wire root_pready ;
wire root_pslverr ;
wire [31:0] root_prdata ;
apb1_state_ctrl U_APB1_STATE_CTRL
(
.i_hclk (hclk ),
.i_hrst_n (hrst_n ),
.i_pclk_en (pclk_en ),
.i_slave_hsel (hsel ),
.i_slave_hreadyin (hreadyin ),
.i_slave_haddr (haddr ),
.i_slave_hwrite (hwrite ),
.i_slave_htrans (htrans ),
.i_slave_hsize (hsize ),
.i_slave_hburst (hburst ),
.i_slave_hprot (hprot ),
.i_slave_hsec (hsec ),
.i_slave_hwdata (hwdata ),
.i_root_pready (root_pready ),
.i_root_pslverr (root_pslverr ),
.i_root_prdata (root_prdata ),
.o_slave_hreadyout (hreadyout ),
.o_slave_hresp (hresp ),
.o_slave_hrdata (hrdata ),
.o_root_psel (root_psel ),
.o_root_paddr (root_paddr ),
.o_root_penable (root_penable ),
.o_root_pwdata (root_pwdata ),
.o_root_pstrb (root_pstrb ),
.o_root_pwrite (root_pwrite ),
.o_root_pprot (root_pprot )
);
wire [ APB_LEAF_SLV_NUM-1:0] i_leaf_slave_pready ;
wire [ APB_LEAF_SLV_NUM-1:0] i_leaf_slave_pslverr ;
wire [32*APB_LEAF_SLV_NUM-1:0] i_leaf_slave_prdata ;
wire [ APB_LEAF_SLV_NUM-1:0] o_leaf_slave_psel ;
assign i_leaf_slave_pready[0] = pready_s0 ;
assign i_leaf_slave_pslverr[0]= pselverr_s0 ;
assign psel_s0 = o_leaf_slave_psel[0] ;
assign i_leaf_slave_prdata[31:0] = prdata_s0 ;
assign i_leaf_slave_pready[1] = pready_s1 ;
assign i_leaf_slave_pslverr[1]= pselverr_s1 ;
assign psel_s1 = o_leaf_slave_psel[1] ;
assign i_leaf_slave_prdata[63:32] = prdata_s1 ;
assign i_leaf_slave_pready[2] = pready_s2 ;
assign i_leaf_slave_pslverr[2]= pselverr_s2 ;
assign psel_s2 = o_leaf_slave_psel[2] ;
assign i_leaf_slave_prdata[95:64] = prdata_s2 ;
assign i_leaf_slave_pready[3] = pready_s3 ;
assign i_leaf_slave_pslverr[3]= pselverr_s3 ;
assign psel_s3 = o_leaf_slave_psel[3] ;
assign i_leaf_slave_prdata[127:96] = prdata_s3 ;
assign i_leaf_slave_pready[4] = pready_s4 ;
assign i_leaf_slave_pslverr[4]= pselverr_s4 ;
assign psel_s4 = o_leaf_slave_psel[4] ;
assign i_leaf_slave_prdata[159:128] = prdata_s4 ;
assign i_leaf_slave_pready[5] = pready_s5 ;
assign i_leaf_slave_pslverr[5]= pselverr_s5 ;
assign psel_s5 = o_leaf_slave_psel[5] ;
assign i_leaf_slave_prdata[191:160] = prdata_s5 ;
assign i_leaf_slave_pready[6] = pready_s6 ;
assign i_leaf_slave_pslverr[6]= pselverr_s6 ;
assign psel_s6 = o_leaf_slave_psel[6] ;
assign i_leaf_slave_prdata[223:192] = prdata_s6 ;
assign i_leaf_slave_pready[7] = pready_s7 ;
assign i_leaf_slave_pslverr[7]= pselverr_s7 ;
assign psel_s7 = o_leaf_slave_psel[7] ;
assign i_leaf_slave_prdata[255:224] = prdata_s7 ;
assign i_leaf_slave_pready[8] = pready_s8 ;
assign i_leaf_slave_pslverr[8]= pselverr_s8 ;
assign psel_s8 = o_leaf_slave_psel[8] ;
assign i_leaf_slave_prdata[287:256] = prdata_s8 ;
assign i_leaf_slave_pready[9] = pready_s9 ;
assign i_leaf_slave_pslverr[9]= pselverr_s9 ;
assign psel_s9 = o_leaf_slave_psel[9] ;
assign i_leaf_slave_prdata[319:288] = prdata_s9 ;
assign i_leaf_slave_pready[10] = pready_s10 ;
assign i_leaf_slave_pslverr[10]= pselverr_s10 ;
assign psel_s10 = o_leaf_slave_psel[10] ;
assign i_leaf_slave_prdata[351:320] = prdata_s10 ;
assign i_leaf_slave_pready[11] = pready_s11 ;
assign i_leaf_slave_pslverr[11]= pselverr_s11 ;
assign psel_s11 = o_leaf_slave_psel[11] ;
assign i_leaf_slave_prdata[383:352] = prdata_s11 ;
assign i_leaf_slave_pready[12] = pready_s12 ;
assign i_leaf_slave_pslverr[12]= pselverr_s12 ;
assign psel_s12 = o_leaf_slave_psel[12] ;
assign i_leaf_slave_prdata[415:384] = prdata_s12 ;
assign i_leaf_slave_pready[13] = pready_s13 ;
assign i_leaf_slave_pslverr[13]= pselverr_s13 ;
assign psel_s13 = o_leaf_slave_psel[13] ;
assign i_leaf_slave_prdata[447:416] = prdata_s13 ;
assign i_leaf_slave_pready[14] = pready_s14 ;
assign i_leaf_slave_pslverr[14]= pselverr_s14 ;
assign psel_s14 = o_leaf_slave_psel[14] ;
assign i_leaf_slave_prdata[479:448] = prdata_s14 ;
assign i_leaf_slave_pready[15] = pready_s15 ;
assign i_leaf_slave_pslverr[15]= pselverr_s15 ;
assign psel_s15 = o_leaf_slave_psel[15] ;
assign i_leaf_slave_prdata[511:480] = prdata_s15 ;
apb1_leaf_mux U_APB1_LEAF_MUX
(
.i_root_psel (root_psel ),
.i_root_paddr (root_paddr ),
.i_root_penable (root_penable ),
.i_root_pwdata (root_pwdata ),
.i_root_pstrb (root_pstrb ),
.i_root_pwrite (root_pwrite ),
.i_root_pprot (root_pprot ),
.i_leaf_slave_pready (i_leaf_slave_pready ),
.i_leaf_slave_pslverr (i_leaf_slave_pslverr ),
.i_leaf_slave_prdata (i_leaf_slave_prdata ),
.o_root_pready (root_pready ),
.o_root_pslverr (root_pslverr ),
.o_root_prdata (root_prdata ),
.o_leaf_slave_psel (o_leaf_slave_psel ),
.o_leaf_slave_paddr (paddr_s ),
.o_leaf_slave_penable (penable_s ),
.o_leaf_slave_pwdata (pwdata_s ),
.o_leaf_slave_pstrb (pstrb_s ),
.o_leaf_slave_pwrite (pwrite_s ),
.o_leaf_slave_pprot (pprot_s )
);
endmodule |
module usi1_sec_top(
clk,
dma_ack_rx,
dma_ack_tx,
dma_req_rx,
dma_req_tx,
nss_ie_n,
nss_in,
nss_oe_n,
nss_out,
paddr,
penable,
pprot,
prdata,
psel,
pwdata,
pwrite,
rst_n,
sclk_ie_n,
sclk_in,
sclk_oe_n,
sclk_out,
sd0_ie_n,
sd0_in,
sd0_oe_n,
sd0_out,
sd1_ie_n,
sd1_in,
sd1_oe_n,
sd1_out,
sec_rx_req,
sec_tx_req,
tipc_usi1_trust,
usi_etb_rx_trig,
usi_etb_tx_trig,
usi_intr
);
input clk;
input dma_ack_rx;
input dma_ack_tx;
input nss_in;
input [31:0] paddr;
input penable;
input [2 :0] pprot;
input psel;
input [31:0] pwdata;
input pwrite;
input rst_n;
input sclk_in;
input sd0_in;
input sd1_in;
input tipc_usi1_trust;
output dma_req_rx;
output dma_req_tx;
output nss_ie_n;
output nss_oe_n;
output nss_out;
output [31:0] prdata;
output sclk_ie_n;
output sclk_oe_n;
output sclk_out;
output sd0_ie_n;
output sd0_oe_n;
output sd0_out;
output sd1_ie_n;
output sd1_oe_n;
output sd1_out;
output sec_rx_req;
output sec_tx_req;
output usi_etb_rx_trig;
output usi_etb_tx_trig;
output usi_intr;
wire clk;
wire dma_ack_rx;
wire dma_ack_tx;
wire dma_req_rx;
wire dma_req_tx;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire nss_ie_n;
wire nss_in;
wire nss_oe_n;
wire nss_out;
wire [31:0] paddr;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire rst_n;
wire sclk_ie_n;
wire sclk_in;
wire sclk_oe_n;
wire sclk_out;
wire sd0_ie_n;
wire sd0_in;
wire sd0_oe_n;
wire sd0_out;
wire sd1_ie_n;
wire sd1_in;
wire sd1_oe_n;
wire sd1_out;
wire sec_rx_req;
wire sec_tx_req;
wire tipc_usi1_trust;
wire usi_etb_rx_trig;
wire usi_etb_tx_trig;
wire usi_intr;
usi_top x_usi1 (
.clk (clk ),
.dma_ack_rx (dma_ack_rx ),
.dma_ack_tx (dma_ack_tx ),
.dma_req_rx (dma_req_rx ),
.dma_req_tx (dma_req_tx ),
.nss_ie_n (nss_ie_n ),
.nss_in (nss_in ),
.nss_oe_n (nss_oe_n ),
.nss_out (nss_out ),
.paddr (paddr ),
.penable (penable ),
.prdata (i_prdata ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.rst_n (rst_n ),
.sclk_ie_n (sclk_ie_n ),
.sclk_in (sclk_in ),
.sclk_oe_n (sclk_oe_n ),
.sclk_out (sclk_out ),
.sd0_ie_n (sd0_ie_n ),
.sd0_in (sd0_in ),
.sd0_oe_n (sd0_oe_n ),
.sd0_out (sd0_out ),
.sd1_ie_n (sd1_ie_n ),
.sd1_in (sd1_in ),
.sd1_oe_n (sd1_oe_n ),
.sd1_out (sd1_out ),
.usi_etb_rx_trig (usi_etb_rx_trig),
.usi_etb_tx_trig (usi_etb_tx_trig),
.usi_intr (usi_intr )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
assign sec_rx_req = dma_req_rx;
assign sec_tx_req = dma_req_tx;
endmodule |
module aou_top(
apb1_gpio_psel_s5,
apb1_pmu_psel_s15,
apb1_rtc_psel_s6,
apb1_xx_paddr,
apb1_xx_penable,
apb1_xx_pprot,
apb1_xx_pwdata,
apb1_xx_pwrite,
cpu_pmu_dfs_ack,
cpu_pmu_sleep_b,
dft_clk,
ehs_pmu_clk,
els_pmu_clk,
gpio_apb1_prdata,
gpio_ioctl_porta_dr,
gpio_wic_intr,
ioctl_gpio_ext_porta,
pad_core_clk,
pad_core_ctim_refclk,
pad_core_rst_b,
pad_gpio_ien,
pad_gpio_oen,
pad_mcurst_b,
pmu_apb0_pclk_en,
pmu_apb0_s3clk,
pmu_apb0_s3rst_b,
pmu_apb1_pclk_en,
pmu_apb1_prdata,
pmu_apb1_s3clk,
pmu_apb1_s3rst_b,
pmu_cpu_dfs_req,
pmu_dmac0_hclk,
pmu_dmac0_hrst_b,
pmu_dmemdummy0_hclk,
pmu_dmemdummy0_hrst_b,
pmu_dummy0_hclk,
pmu_dummy0_hrst_b,
pmu_dummy0_s3clk,
pmu_dummy0_s3rst_b,
pmu_dummy1_hclk,
pmu_dummy1_hrst_b,
pmu_dummy1_p0clk,
pmu_dummy1_p0rst_b,
pmu_dummy1_p1clk,
pmu_dummy1_p1rst_b,
pmu_dummy1_s3clk,
pmu_dummy1_s3rst_b,
pmu_dummy2_hclk,
pmu_dummy2_hrst_b,
pmu_dummy2_p0clk,
pmu_dummy2_p0rst_b,
pmu_dummy2_p1clk,
pmu_dummy2_p1rst_b,
pmu_dummy2_s3clk,
pmu_dummy2_s3rst_b,
pmu_dummy3_hclk,
pmu_dummy3_hrst_b,
pmu_dummy3_p0clk,
pmu_dummy3_p0rst_b,
pmu_dummy3_p1clk,
pmu_dummy3_p1rst_b,
pmu_dummy3_s3clk,
pmu_dummy3_s3rst_b,
pmu_dummy4_p0clk,
pmu_dummy4_p0rst_b,
pmu_dummy4_p1clk,
pmu_dummy4_p1rst_b,
pmu_dummy5_p0clk,
pmu_dummy5_p0rst_b,
pmu_dummy5_p1clk,
pmu_dummy5_p1rst_b,
pmu_dummy6_p1clk,
pmu_dummy6_p1rst_b,
pmu_dummy7_p0clk,
pmu_dummy7_p0rst_b,
pmu_dummy7_p1clk,
pmu_dummy7_p1rst_b,
pmu_dummy8_p0clk,
pmu_dummy8_p0rst_b,
pmu_dummy8_p1clk,
pmu_dummy8_p1rst_b,
pmu_dummy9_p0clk,
pmu_dummy9_p0rst_b,
pmu_hmain0_hclk,
pmu_hmain0_hrst_b,
pmu_imemdummy0_hclk,
pmu_imemdummy0_hrst_b,
pmu_lsbus_hclk,
pmu_lsbus_hrst_b,
pmu_mdummy0_hclk,
pmu_mdummy0_hrst_b,
pmu_mdummy1_hclk,
pmu_mdummy1_hrst_b,
pmu_mdummy2_hclk,
pmu_mdummy2_hrst_b,
pmu_pwm_p0clk,
pmu_pwm_p0rst_b,
pmu_smc_hclk,
pmu_smc_hrst_b,
pmu_sub3_s3clk,
pmu_sub3_s3rst_b,
pmu_tim0_p0clk,
pmu_tim0_p0rst_b,
pmu_tim1_p1clk,
pmu_tim1_p1rst_b,
pmu_tim2_p0clk,
pmu_tim2_p0rst_b,
pmu_tim3_p1clk,
pmu_tim3_p1rst_b,
pmu_tim4_p0clk,
pmu_tim4_p0rst_b,
pmu_tim5_p1clk,
pmu_tim5_p1rst_b,
pmu_tim6_p0clk,
pmu_tim6_p0rst_b,
pmu_tim7_p1clk,
pmu_tim7_p1rst_b,
pmu_usi0_p0clk,
pmu_usi0_p0rst_b,
pmu_usi1_p1clk,
pmu_usi1_p1rst_b,
pmu_usi2_p0clk,
pmu_usi2_p0rst_b,
pmu_wdt_p0clk,
pmu_wdt_p0rst_b,
pmu_wic_intr,
rtc_apb1_prdata,
rtc_wic_intr,
test_mode,
wdt_pmu_rst_b
);
input apb1_gpio_psel_s5;
input apb1_pmu_psel_s15;
input apb1_rtc_psel_s6;
input [31:0] apb1_xx_paddr;
input apb1_xx_penable;
input [2 :0] apb1_xx_pprot;
input [31:0] apb1_xx_pwdata;
input apb1_xx_pwrite;
input cpu_pmu_dfs_ack;
input cpu_pmu_sleep_b;
input ehs_pmu_clk;
input els_pmu_clk;
input [31:0] ioctl_gpio_ext_porta;
input pad_mcurst_b;
input test_mode;
input wdt_pmu_rst_b;
output dft_clk;
output [31:0] gpio_apb1_prdata;
output [31:0] gpio_ioctl_porta_dr;
output gpio_wic_intr;
output pad_core_clk;
output pad_core_ctim_refclk;
output pad_core_rst_b;
output [31:0] pad_gpio_ien;
output [31:0] pad_gpio_oen;
output pmu_apb0_pclk_en;
output pmu_apb0_s3clk;
output pmu_apb0_s3rst_b;
output pmu_apb1_pclk_en;
output [31:0] pmu_apb1_prdata;
output pmu_apb1_s3clk;
output pmu_apb1_s3rst_b;
output pmu_cpu_dfs_req;
output pmu_dmac0_hclk;
output pmu_dmac0_hrst_b;
output pmu_dmemdummy0_hclk;
output pmu_dmemdummy0_hrst_b;
output pmu_dummy0_hclk;
output pmu_dummy0_hrst_b;
output pmu_dummy0_s3clk;
output pmu_dummy0_s3rst_b;
output pmu_dummy1_hclk;
output pmu_dummy1_hrst_b;
output pmu_dummy1_p0clk;
output pmu_dummy1_p0rst_b;
output pmu_dummy1_p1clk;
output pmu_dummy1_p1rst_b;
output pmu_dummy1_s3clk;
output pmu_dummy1_s3rst_b;
output pmu_dummy2_hclk;
output pmu_dummy2_hrst_b;
output pmu_dummy2_p0clk;
output pmu_dummy2_p0rst_b;
output pmu_dummy2_p1clk;
output pmu_dummy2_p1rst_b;
output pmu_dummy2_s3clk;
output pmu_dummy2_s3rst_b;
output pmu_dummy3_hclk;
output pmu_dummy3_hrst_b;
output pmu_dummy3_p0clk;
output pmu_dummy3_p0rst_b;
output pmu_dummy3_p1clk;
output pmu_dummy3_p1rst_b;
output pmu_dummy3_s3clk;
output pmu_dummy3_s3rst_b;
output pmu_dummy4_p0clk;
output pmu_dummy4_p0rst_b;
output pmu_dummy4_p1clk;
output pmu_dummy4_p1rst_b;
output pmu_dummy5_p0clk;
output pmu_dummy5_p0rst_b;
output pmu_dummy5_p1clk;
output pmu_dummy5_p1rst_b;
output pmu_dummy6_p1clk;
output pmu_dummy6_p1rst_b;
output pmu_dummy7_p0clk;
output pmu_dummy7_p0rst_b;
output pmu_dummy7_p1clk;
output pmu_dummy7_p1rst_b;
output pmu_dummy8_p0clk;
output pmu_dummy8_p0rst_b;
output pmu_dummy8_p1clk;
output pmu_dummy8_p1rst_b;
output pmu_dummy9_p0clk;
output pmu_dummy9_p0rst_b;
output pmu_hmain0_hclk;
output pmu_hmain0_hrst_b;
output pmu_imemdummy0_hclk;
output pmu_imemdummy0_hrst_b;
output pmu_lsbus_hclk;
output pmu_lsbus_hrst_b;
output pmu_mdummy0_hclk;
output pmu_mdummy0_hrst_b;
output pmu_mdummy1_hclk;
output pmu_mdummy1_hrst_b;
output pmu_mdummy2_hclk;
output pmu_mdummy2_hrst_b;
output pmu_pwm_p0clk;
output pmu_pwm_p0rst_b;
output pmu_smc_hclk;
output pmu_smc_hrst_b;
output pmu_sub3_s3clk;
output pmu_sub3_s3rst_b;
output pmu_tim0_p0clk;
output pmu_tim0_p0rst_b;
output pmu_tim1_p1clk;
output pmu_tim1_p1rst_b;
output pmu_tim2_p0clk;
output pmu_tim2_p0rst_b;
output pmu_tim3_p1clk;
output pmu_tim3_p1rst_b;
output pmu_tim4_p0clk;
output pmu_tim4_p0rst_b;
output pmu_tim5_p1clk;
output pmu_tim5_p1rst_b;
output pmu_tim6_p0clk;
output pmu_tim6_p0rst_b;
output pmu_tim7_p1clk;
output pmu_tim7_p1rst_b;
output pmu_usi0_p0clk;
output pmu_usi0_p0rst_b;
output pmu_usi1_p1clk;
output pmu_usi1_p1rst_b;
output pmu_usi2_p0clk;
output pmu_usi2_p0rst_b;
output pmu_wdt_p0clk;
output pmu_wdt_p0rst_b;
output pmu_wic_intr;
output [31:0] rtc_apb1_prdata;
output rtc_wic_intr;
wire [31:0] apb1_gpio_paddr;
wire apb1_gpio_penable;
wire apb1_gpio_psel_s5;
wire [31:0] apb1_gpio_pwdata;
wire apb1_gpio_pwrite;
wire [31:0] apb1_pmu_paddr;
wire apb1_pmu_penable;
wire apb1_pmu_psel_s15;
wire [31:0] apb1_pmu_pwdata;
wire apb1_pmu_pwrite;
wire [31:0] apb1_rtc_paddr;
wire apb1_rtc_penable;
wire apb1_rtc_psel_s6;
wire [31:0] apb1_rtc_pwdata;
wire apb1_rtc_pwrite;
wire [31:0] apb1_xx_paddr;
wire apb1_xx_penable;
wire [2 :0] apb1_xx_pprot;
wire [31:0] apb1_xx_pwdata;
wire apb1_xx_pwrite;
wire cpu_pmu_dfs_ack;
wire cpu_pmu_sleep_b;
wire dft_clk;
wire ehs_pmu_clk;
wire els_pmu_clk;
wire [31:0] gpio0_etb_trig;
wire [31:0] gpio_apb1_prdata;
wire gpio_gpio_intrclk_en;
wire [31:0] gpio_ioctl_porta_ddr;
wire [31:0] gpio_ioctl_porta_dr;
wire gpio_wic_intr;
wire [31:0] ioctl_gpio_ext_porta;
wire pad_core_clk;
wire pad_core_ctim_refclk;
wire pad_core_rst_b;
wire [31:0] pad_gpio_ien;
wire [31:0] pad_gpio_oen;
wire pad_mcurst_b;
wire pmu_apb0_pclk_en;
wire pmu_apb0_s3clk;
wire pmu_apb0_s3rst_b;
wire pmu_apb1_pclk_en;
wire [31:0] pmu_apb1_prdata;
wire pmu_apb1_s3clk;
wire pmu_apb1_s3rst_b;
wire pmu_cpu_dfs_req;
wire pmu_dmac0_hclk;
wire pmu_dmac0_hrst_b;
wire pmu_dmemdummy0_hclk;
wire pmu_dmemdummy0_hrst_b;
wire pmu_dummy0_hclk;
wire pmu_dummy0_hrst_b;
wire pmu_dummy0_s3clk;
wire pmu_dummy0_s3rst_b;
wire pmu_dummy1_hclk;
wire pmu_dummy1_hrst_b;
wire pmu_dummy1_p0clk;
wire pmu_dummy1_p0rst_b;
wire pmu_dummy1_p1clk;
wire pmu_dummy1_p1rst_b;
wire pmu_dummy1_s3clk;
wire pmu_dummy1_s3rst_b;
wire pmu_dummy2_hclk;
wire pmu_dummy2_hrst_b;
wire pmu_dummy2_p0clk;
wire pmu_dummy2_p0rst_b;
wire pmu_dummy2_p1clk;
wire pmu_dummy2_p1rst_b;
wire pmu_dummy2_s3clk;
wire pmu_dummy2_s3rst_b;
wire pmu_dummy3_hclk;
wire pmu_dummy3_hrst_b;
wire pmu_dummy3_p0clk;
wire pmu_dummy3_p0rst_b;
wire pmu_dummy3_p1clk;
wire pmu_dummy3_p1rst_b;
wire pmu_dummy3_s3clk;
wire pmu_dummy3_s3rst_b;
wire pmu_dummy4_p0clk;
wire pmu_dummy4_p0rst_b;
wire pmu_dummy4_p1clk;
wire pmu_dummy4_p1rst_b;
wire pmu_dummy5_p0clk;
wire pmu_dummy5_p0rst_b;
wire pmu_dummy5_p1clk;
wire pmu_dummy5_p1rst_b;
wire pmu_dummy6_p1clk;
wire pmu_dummy6_p1rst_b;
wire pmu_dummy7_p0clk;
wire pmu_dummy7_p0rst_b;
wire pmu_dummy7_p1clk;
wire pmu_dummy7_p1rst_b;
wire pmu_dummy8_p0clk;
wire pmu_dummy8_p0rst_b;
wire pmu_dummy8_p1clk;
wire pmu_dummy8_p1rst_b;
wire pmu_dummy9_p0clk;
wire pmu_dummy9_p0rst_b;
wire pmu_gpio_p1clk;
wire pmu_gpio_p1rst_b;
wire pmu_hmain0_hclk;
wire pmu_hmain0_hrst_b;
wire pmu_imemdummy0_hclk;
wire pmu_imemdummy0_hrst_b;
wire pmu_lsbus_hclk;
wire pmu_lsbus_hrst_b;
wire pmu_mdummy0_hclk;
wire pmu_mdummy0_hrst_b;
wire pmu_mdummy1_hclk;
wire pmu_mdummy1_hrst_b;
wire pmu_mdummy2_hclk;
wire pmu_mdummy2_hrst_b;
wire pmu_pwm_p0clk;
wire pmu_pwm_p0rst_b;
wire pmu_rtc_clk;
wire pmu_rtc_p1clk;
wire pmu_rtc_p1rst_b;
wire pmu_smc_hclk;
wire pmu_smc_hrst_b;
wire pmu_sub3_s3clk;
wire pmu_sub3_s3rst_b;
wire pmu_tim0_p0clk;
wire pmu_tim0_p0rst_b;
wire pmu_tim1_p1clk;
wire pmu_tim1_p1rst_b;
wire pmu_tim2_p0clk;
wire pmu_tim2_p0rst_b;
wire pmu_tim3_p1clk;
wire pmu_tim3_p1rst_b;
wire pmu_tim4_p0clk;
wire pmu_tim4_p0rst_b;
wire pmu_tim5_p1clk;
wire pmu_tim5_p1rst_b;
wire pmu_tim6_p0clk;
wire pmu_tim6_p0rst_b;
wire pmu_tim7_p1clk;
wire pmu_tim7_p1rst_b;
wire pmu_usi0_p0clk;
wire pmu_usi0_p0rst_b;
wire pmu_usi1_p1clk;
wire pmu_usi1_p1rst_b;
wire pmu_usi2_p0clk;
wire pmu_usi2_p0rst_b;
wire pmu_wdt_p0clk;
wire pmu_wdt_p0rst_b;
wire pmu_wic_intr;
wire [31:0] rtc_apb1_prdata;
wire rtc_etb_trig;
wire rtc_wic_intr;
wire test_mode;
wire tipc_gpio0_trust;
wire tipc_rtc0_trust;
wire wdt_pmu_rst_b;
pmu_dummy_top x_pmu_top (
.cpu_pmu_dfs_ack (cpu_pmu_dfs_ack ),
.cpu_pmu_sleep_b (cpu_pmu_sleep_b ),
.dft_clk (dft_clk ),
.ehs_pmu_clk (ehs_pmu_clk ),
.els_pmu_clk (els_pmu_clk ),
.pad_core_clk (pad_core_clk ),
.pad_core_ctim_refclk (pad_core_ctim_refclk ),
.pad_core_rst_b (pad_core_rst_b ),
.pad_mcurst_b (pad_mcurst_b ),
.paddr (apb1_pmu_paddr ),
.penable (apb1_pmu_penable ),
.pmu_apb0_pclk_en (pmu_apb0_pclk_en ),
.pmu_apb0_s3clk (pmu_apb0_s3clk ),
.pmu_apb0_s3rst_b (pmu_apb0_s3rst_b ),
.pmu_apb1_pclk_en (pmu_apb1_pclk_en ),
.pmu_apb1_s3clk (pmu_apb1_s3clk ),
.pmu_apb1_s3rst_b (pmu_apb1_s3rst_b ),
.pmu_cpu_dfs_req (pmu_cpu_dfs_req ),
.pmu_dmac0_hclk (pmu_dmac0_hclk ),
.pmu_dmac0_hrst_b (pmu_dmac0_hrst_b ),
.pmu_dmemdummy0_hclk (pmu_dmemdummy0_hclk ),
.pmu_dmemdummy0_hrst_b (pmu_dmemdummy0_hrst_b),
.pmu_dummy0_hclk (pmu_dummy0_hclk ),
.pmu_dummy0_hrst_b (pmu_dummy0_hrst_b ),
.pmu_dummy0_s3clk (pmu_dummy0_s3clk ),
.pmu_dummy0_s3rst_b (pmu_dummy0_s3rst_b ),
.pmu_dummy1_hclk (pmu_dummy1_hclk ),
.pmu_dummy1_hrst_b (pmu_dummy1_hrst_b ),
.pmu_dummy1_p0clk (pmu_dummy1_p0clk ),
.pmu_dummy1_p0rst_b (pmu_dummy1_p0rst_b ),
.pmu_dummy1_p1clk (pmu_dummy1_p1clk ),
.pmu_dummy1_p1rst_b (pmu_dummy1_p1rst_b ),
.pmu_dummy1_s3clk (pmu_dummy1_s3clk ),
.pmu_dummy1_s3rst_b (pmu_dummy1_s3rst_b ),
.pmu_dummy2_hclk (pmu_dummy2_hclk ),
.pmu_dummy2_hrst_b (pmu_dummy2_hrst_b ),
.pmu_dummy2_p0clk (pmu_dummy2_p0clk ),
.pmu_dummy2_p0rst_b (pmu_dummy2_p0rst_b ),
.pmu_dummy2_p1clk (pmu_dummy2_p1clk ),
.pmu_dummy2_p1rst_b (pmu_dummy2_p1rst_b ),
.pmu_dummy2_s3clk (pmu_dummy2_s3clk ),
.pmu_dummy2_s3rst_b (pmu_dummy2_s3rst_b ),
.pmu_dummy3_hclk (pmu_dummy3_hclk ),
.pmu_dummy3_hrst_b (pmu_dummy3_hrst_b ),
.pmu_dummy3_p0clk (pmu_dummy3_p0clk ),
.pmu_dummy3_p0rst_b (pmu_dummy3_p0rst_b ),
.pmu_dummy3_p1clk (pmu_dummy3_p1clk ),
.pmu_dummy3_p1rst_b (pmu_dummy3_p1rst_b ),
.pmu_dummy3_s3clk (pmu_dummy3_s3clk ),
.pmu_dummy3_s3rst_b (pmu_dummy3_s3rst_b ),
.pmu_dummy4_p0clk (pmu_dummy4_p0clk ),
.pmu_dummy4_p0rst_b (pmu_dummy4_p0rst_b ),
.pmu_dummy4_p1clk (pmu_dummy4_p1clk ),
.pmu_dummy4_p1rst_b (pmu_dummy4_p1rst_b ),
.pmu_dummy5_p0clk (pmu_dummy5_p0clk ),
.pmu_dummy5_p0rst_b (pmu_dummy5_p0rst_b ),
.pmu_dummy5_p1clk (pmu_dummy5_p1clk ),
.pmu_dummy5_p1rst_b (pmu_dummy5_p1rst_b ),
.pmu_dummy6_p1clk (pmu_dummy6_p1clk ),
.pmu_dummy6_p1rst_b (pmu_dummy6_p1rst_b ),
.pmu_dummy7_p0clk (pmu_dummy7_p0clk ),
.pmu_dummy7_p0rst_b (pmu_dummy7_p0rst_b ),
.pmu_dummy7_p1clk (pmu_dummy7_p1clk ),
.pmu_dummy7_p1rst_b (pmu_dummy7_p1rst_b ),
.pmu_dummy8_p0clk (pmu_dummy8_p0clk ),
.pmu_dummy8_p0rst_b (pmu_dummy8_p0rst_b ),
.pmu_dummy8_p1clk (pmu_dummy8_p1clk ),
.pmu_dummy8_p1rst_b (pmu_dummy8_p1rst_b ),
.pmu_dummy9_p0clk (pmu_dummy9_p0clk ),
.pmu_dummy9_p0rst_b (pmu_dummy9_p0rst_b ),
.pmu_gpio_p1clk (pmu_gpio_p1clk ),
.pmu_gpio_p1rst_b (pmu_gpio_p1rst_b ),
.pmu_hmain0_hclk (pmu_hmain0_hclk ),
.pmu_hmain0_hrst_b (pmu_hmain0_hrst_b ),
.pmu_imemdummy0_hclk (pmu_imemdummy0_hclk ),
.pmu_imemdummy0_hrst_b (pmu_imemdummy0_hrst_b),
.pmu_lsbus_hclk (pmu_lsbus_hclk ),
.pmu_lsbus_hrst_b (pmu_lsbus_hrst_b ),
.pmu_mdummy0_hclk (pmu_mdummy0_hclk ),
.pmu_mdummy0_hrst_b (pmu_mdummy0_hrst_b ),
.pmu_mdummy1_hclk (pmu_mdummy1_hclk ),
.pmu_mdummy1_hrst_b (pmu_mdummy1_hrst_b ),
.pmu_mdummy2_hclk (pmu_mdummy2_hclk ),
.pmu_mdummy2_hrst_b (pmu_mdummy2_hrst_b ),
.pmu_pwm_p0clk (pmu_pwm_p0clk ),
.pmu_pwm_p0rst_b (pmu_pwm_p0rst_b ),
.pmu_rtc_clk (pmu_rtc_clk ),
.pmu_rtc_p1clk (pmu_rtc_p1clk ),
.pmu_rtc_p1rst_b (pmu_rtc_p1rst_b ),
.pmu_smc_hclk (pmu_smc_hclk ),
.pmu_smc_hrst_b (pmu_smc_hrst_b ),
.pmu_sub3_s3clk (pmu_sub3_s3clk ),
.pmu_sub3_s3rst_b (pmu_sub3_s3rst_b ),
.pmu_tim0_p0clk (pmu_tim0_p0clk ),
.pmu_tim0_p0rst_b (pmu_tim0_p0rst_b ),
.pmu_tim1_p1clk (pmu_tim1_p1clk ),
.pmu_tim1_p1rst_b (pmu_tim1_p1rst_b ),
.pmu_tim2_p0clk (pmu_tim2_p0clk ),
.pmu_tim2_p0rst_b (pmu_tim2_p0rst_b ),
.pmu_tim3_p1clk (pmu_tim3_p1clk ),
.pmu_tim3_p1rst_b (pmu_tim3_p1rst_b ),
.pmu_tim4_p0clk (pmu_tim4_p0clk ),
.pmu_tim4_p0rst_b (pmu_tim4_p0rst_b ),
.pmu_tim5_p1clk (pmu_tim5_p1clk ),
.pmu_tim5_p1rst_b (pmu_tim5_p1rst_b ),
.pmu_tim6_p0clk (pmu_tim6_p0clk ),
.pmu_tim6_p0rst_b (pmu_tim6_p0rst_b ),
.pmu_tim7_p1clk (pmu_tim7_p1clk ),
.pmu_tim7_p1rst_b (pmu_tim7_p1rst_b ),
.pmu_usi0_p0clk (pmu_usi0_p0clk ),
.pmu_usi0_p0rst_b (pmu_usi0_p0rst_b ),
.pmu_usi1_p1clk (pmu_usi1_p1clk ),
.pmu_usi1_p1rst_b (pmu_usi1_p1rst_b ),
.pmu_usi2_p0clk (pmu_usi2_p0clk ),
.pmu_usi2_p0rst_b (pmu_usi2_p0rst_b ),
.pmu_wdt_p0clk (pmu_wdt_p0clk ),
.pmu_wdt_p0rst_b (pmu_wdt_p0rst_b ),
.pmu_wic_intr (pmu_wic_intr ),
.pprot (apb1_xx_pprot ),
.prdata (pmu_apb1_prdata ),
.psel (apb1_pmu_psel_s15 ),
.pwdata (apb1_pmu_pwdata ),
.pwrite (apb1_pmu_pwrite ),
.wdt_pmu_rst_b (wdt_pmu_rst_b )
);
gpio0_sec_top x_gpio_sec_top (
.gpio0_etb_trig (gpio0_etb_trig ),
.gpio_ext_porta (ioctl_gpio_ext_porta),
.gpio_intr_flag (gpio_wic_intr ),
.gpio_intrclk_en (gpio_gpio_intrclk_en),
.gpio_porta_ddr (gpio_ioctl_porta_ddr),
.gpio_porta_dr (gpio_ioctl_porta_dr ),
.paddr (apb1_gpio_paddr ),
.pclk (pmu_gpio_p1clk ),
.pclk_intr (pmu_gpio_p1clk ),
.penable (apb1_gpio_penable ),
.pprot (apb1_xx_pprot ),
.prdata (gpio_apb1_prdata ),
.presetn (pmu_gpio_p1rst_b ),
.psel (apb1_gpio_psel_s5 ),
.pwdata (apb1_gpio_pwdata ),
.pwrite (apb1_gpio_pwrite ),
.tipc_gpio0_trust (tipc_gpio0_trust )
);
assign pad_gpio_oen[31:0] = ~gpio_ioctl_porta_ddr[31:0];
assign pad_gpio_ien[31:0] = gpio_ioctl_porta_ddr[31:0];
rtc0_sec_top x_rtc0_sec_top (
.aortc_paddr (apb1_rtc_paddr ),
.aortc_pclk (pmu_rtc_p1clk ),
.aortc_penable (apb1_rtc_penable ),
.aortc_pprot (apb1_xx_pprot[2:0]),
.aortc_prdata (rtc_apb1_prdata ),
.aortc_psel (apb1_rtc_psel_s6 ),
.aortc_pwdata (apb1_rtc_pwdata ),
.aortc_pwrite (apb1_rtc_pwrite ),
.aortc_rst_n (pmu_rtc_p1rst_b ),
.etb_rtc_trig (1'b0 ),
.i_rtc_ext_clk (pmu_rtc_clk ),
.rtc0_vic_intr (rtc_wic_intr ),
.rtc_etb_trig (rtc_etb_trig ),
.test_mode (test_mode ),
.tipc_rtc0_trust (tipc_rtc0_trust )
);
assign tipc_rtc0_trust = 1'b0;
assign tipc_gpio0_trust = 1'b0;
assign apb1_pmu_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_pmu_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_pmu_penable = apb1_xx_penable;
assign apb1_pmu_pwrite = apb1_xx_pwrite;
assign apb1_gpio_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_gpio_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_gpio_penable = apb1_xx_penable;
assign apb1_gpio_pwrite = apb1_xx_pwrite;
assign apb1_rtc_paddr[31:0] = apb1_xx_paddr[31:0];
assign apb1_rtc_pwdata[31:0] = apb1_xx_pwdata[31:0];
assign apb1_rtc_penable = apb1_xx_penable;
assign apb1_rtc_pwrite = apb1_xx_pwrite;
endmodule |
module tim4_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim4_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim4_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim4_trust;
tim4_tim_top x_tim4_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module tim3_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim3_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim3_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim3_trust;
tim3_tim_top x_tim3_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module tim2_sec_top(
etb_tim1_trig_en_off,
etb_tim1_trig_en_on,
etb_tim2_trig_en_off,
etb_tim2_trig_en_on,
intr,
paddr,
pclk,
penable,
pprot,
prdata,
presetn,
psel,
pwdata,
pwrite,
scan_mode,
tim1_etb_trig,
tim2_etb_trig,
tipc_tim2_trust
);
input etb_tim1_trig_en_off;
input etb_tim1_trig_en_on;
input etb_tim2_trig_en_off;
input etb_tim2_trig_en_on;
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input presetn;
input psel;
input [31:0] pwdata;
input pwrite;
input scan_mode;
input tipc_tim2_trust;
output [1 :0] intr;
output [31:0] prdata;
output tim1_etb_trig;
output tim2_etb_trig;
wire etb_tim1_trig_en_off;
wire etb_tim1_trig_en_on;
wire etb_tim2_trig_en_off;
wire etb_tim2_trig_en_on;
wire [31:0] i_prdata;
wire i_psel;
wire i_pwrite;
wire [1 :0] intr;
wire [31:0] paddr;
wire pclk;
wire penable;
wire [2 :0] pprot;
wire [31:0] prdata;
wire presetn;
wire psel;
wire [31:0] pwdata;
wire pwrite;
wire scan_mode;
wire tim1_etb_trig;
wire tim2_etb_trig;
wire tipc_tim2_trust;
tim2_tim_top x_tim2_tim_top (
.etb_tim1_trig_en_off (etb_tim1_trig_en_off),
.etb_tim1_trig_en_on (etb_tim1_trig_en_on ),
.etb_tim2_trig_en_off (etb_tim2_trig_en_off),
.etb_tim2_trig_en_on (etb_tim2_trig_en_on ),
.intr (intr ),
.paddr (paddr ),
.pclk (pclk ),
.penable (penable ),
.prdata (i_prdata ),
.presetn (presetn ),
.psel (i_psel ),
.pwdata (pwdata ),
.pwrite (i_pwrite ),
.scan_mode (scan_mode ),
.tim1_etb_trig (tim1_etb_trig ),
.tim2_etb_trig (tim2_etb_trig )
);
assign prdata[31:0] = i_prdata[31:0];
assign i_pwrite = pwrite;
assign i_psel = psel;
endmodule |
module ls_sub_top(
apb0_lsbus_s2_hrdata,
apb0_lsbus_s2_hready,
apb0_lsbus_s2_hresp,
apb1_lsbus_s3_hrdata,
apb1_lsbus_s3_hready,
apb1_lsbus_s3_hresp,
hmain0_lsbus_s10_haddr,
hmain0_lsbus_s10_hburst,
hmain0_lsbus_s10_hprot,
hmain0_lsbus_s10_hsel,
hmain0_lsbus_s10_hsize,
hmain0_lsbus_s10_htrans,
hmain0_lsbus_s10_hwdata,
hmain0_lsbus_s10_hwrite,
lsbus_apb0_s2_haddr,
lsbus_apb0_s2_hburst,
lsbus_apb0_s2_hprot,
lsbus_apb0_s2_hsel,
lsbus_apb0_s2_hsize,
lsbus_apb0_s2_htrans,
lsbus_apb0_s2_hwdata,
lsbus_apb0_s2_hwrite,
lsbus_apb1_s3_haddr,
lsbus_apb1_s3_hburst,
lsbus_apb1_s3_hprot,
lsbus_apb1_s3_hsel,
lsbus_apb1_s3_hsize,
lsbus_apb1_s3_htrans,
lsbus_apb1_s3_hwdata,
lsbus_apb1_s3_hwrite,
lsbus_dummy0_intr,
lsbus_dummy1_intr,
lsbus_dummy2_intr,
lsbus_dummy3_intr,
lsbus_hmain0_s10_hrdata,
lsbus_hmain0_s10_hready,
lsbus_hmain0_s10_hresp,
pmu_dummy0_s3clk,
pmu_dummy0_s3rst_b,
pmu_dummy1_s3clk,
pmu_dummy1_s3rst_b,
pmu_dummy2_s3clk,
pmu_dummy2_s3rst_b,
pmu_dummy3_s3clk,
pmu_dummy3_s3rst_b,
pmu_lsbus_hclk,
pmu_lsbus_hrst_b,
pmu_sub3_s3clk,
pmu_sub3_s3rst_b
);
input [31:0] apb0_lsbus_s2_hrdata;
input apb0_lsbus_s2_hready;
input [1 :0] apb0_lsbus_s2_hresp;
input [31:0] apb1_lsbus_s3_hrdata;
input apb1_lsbus_s3_hready;
input [1 :0] apb1_lsbus_s3_hresp;
input [31:0] hmain0_lsbus_s10_haddr;
input [2 :0] hmain0_lsbus_s10_hburst;
input [3 :0] hmain0_lsbus_s10_hprot;
input hmain0_lsbus_s10_hsel;
input [2 :0] hmain0_lsbus_s10_hsize;
input [1 :0] hmain0_lsbus_s10_htrans;
input [31:0] hmain0_lsbus_s10_hwdata;
input hmain0_lsbus_s10_hwrite;
input pmu_dummy0_s3clk;
input pmu_dummy0_s3rst_b;
input pmu_dummy1_s3clk;
input pmu_dummy1_s3rst_b;
input pmu_dummy2_s3clk;
input pmu_dummy2_s3rst_b;
input pmu_dummy3_s3clk;
input pmu_dummy3_s3rst_b;
input pmu_lsbus_hclk;
input pmu_lsbus_hrst_b;
input pmu_sub3_s3clk;
input pmu_sub3_s3rst_b;
output [31:0] lsbus_apb0_s2_haddr;
output [2 :0] lsbus_apb0_s2_hburst;
output [3 :0] lsbus_apb0_s2_hprot;
output lsbus_apb0_s2_hsel;
output [2 :0] lsbus_apb0_s2_hsize;
output [1 :0] lsbus_apb0_s2_htrans;
output [31:0] lsbus_apb0_s2_hwdata;
output lsbus_apb0_s2_hwrite;
output [31:0] lsbus_apb1_s3_haddr;
output [2 :0] lsbus_apb1_s3_hburst;
output [3 :0] lsbus_apb1_s3_hprot;
output lsbus_apb1_s3_hsel;
output [2 :0] lsbus_apb1_s3_hsize;
output [1 :0] lsbus_apb1_s3_htrans;
output [31:0] lsbus_apb1_s3_hwdata;
output lsbus_apb1_s3_hwrite;
output lsbus_dummy0_intr;
output lsbus_dummy1_intr;
output lsbus_dummy2_intr;
output lsbus_dummy3_intr;
output [31:0] lsbus_hmain0_s10_hrdata;
output lsbus_hmain0_s10_hready;
output [1 :0] lsbus_hmain0_s10_hresp;
wire [31:0] apb0_lsbus_s2_hrdata;
wire apb0_lsbus_s2_hready;
wire [1 :0] apb0_lsbus_s2_hresp;
wire [31:0] apb1_lsbus_s3_hrdata;
wire apb1_lsbus_s3_hready;
wire [1 :0] apb1_lsbus_s3_hresp;
wire [31:0] dummy0_lsbus_s0_hrdata;
wire dummy0_lsbus_s0_hready;
wire [1 :0] dummy0_lsbus_s0_hresp;
wire [31:0] dummy1_lsbus_s1_hrdata;
wire dummy1_lsbus_s1_hready;
wire [1 :0] dummy1_lsbus_s1_hresp;
wire [31:0] dummy2_lsbus_s4_hrdata;
wire dummy2_lsbus_s4_hready;
wire [1 :0] dummy2_lsbus_s4_hresp;
wire [31:0] dummy3_lsbus_s5_hrdata;
wire dummy3_lsbus_s5_hready;
wire [1 :0] dummy3_lsbus_s5_hresp;
wire [31:0] hmain0_lsbus_s10_haddr;
wire [2 :0] hmain0_lsbus_s10_hburst;
wire [3 :0] hmain0_lsbus_s10_hprot;
wire hmain0_lsbus_s10_hsel;
wire [2 :0] hmain0_lsbus_s10_hsize;
wire [1 :0] hmain0_lsbus_s10_htrans;
wire [31:0] hmain0_lsbus_s10_hwdata;
wire hmain0_lsbus_s10_hwrite;
wire [31:0] lsbus_apb0_s2_haddr;
wire [2 :0] lsbus_apb0_s2_hburst;
wire [3 :0] lsbus_apb0_s2_hprot;
wire lsbus_apb0_s2_hsel;
wire [2 :0] lsbus_apb0_s2_hsize;
wire [1 :0] lsbus_apb0_s2_htrans;
wire [31:0] lsbus_apb0_s2_hwdata;
wire lsbus_apb0_s2_hwrite;
wire [31:0] lsbus_apb1_s3_haddr;
wire [2 :0] lsbus_apb1_s3_hburst;
wire [3 :0] lsbus_apb1_s3_hprot;
wire lsbus_apb1_s3_hsel;
wire [2 :0] lsbus_apb1_s3_hsize;
wire [1 :0] lsbus_apb1_s3_htrans;
wire [31:0] lsbus_apb1_s3_hwdata;
wire lsbus_apb1_s3_hwrite;
wire lsbus_dummy0_intr;
wire [31:0] lsbus_dummy0_s0_haddr;
wire [2 :0] lsbus_dummy0_s0_hburst;
wire [3 :0] lsbus_dummy0_s0_hprot;
wire lsbus_dummy0_s0_hsel;
wire [2 :0] lsbus_dummy0_s0_hsize;
wire [1 :0] lsbus_dummy0_s0_htrans;
wire [31:0] lsbus_dummy0_s0_hwdata;
wire lsbus_dummy0_s0_hwrite;
wire lsbus_dummy1_intr;
wire [31:0] lsbus_dummy1_s1_haddr;
wire [2 :0] lsbus_dummy1_s1_hburst;
wire [3 :0] lsbus_dummy1_s1_hprot;
wire lsbus_dummy1_s1_hsel;
wire [2 :0] lsbus_dummy1_s1_hsize;
wire [1 :0] lsbus_dummy1_s1_htrans;
wire [31:0] lsbus_dummy1_s1_hwdata;
wire lsbus_dummy1_s1_hwrite;
wire lsbus_dummy2_intr;
wire [31:0] lsbus_dummy2_s4_haddr;
wire [2 :0] lsbus_dummy2_s4_hburst;
wire [3 :0] lsbus_dummy2_s4_hprot;
wire lsbus_dummy2_s4_hsel;
wire [2 :0] lsbus_dummy2_s4_hsize;
wire [1 :0] lsbus_dummy2_s4_htrans;
wire [31:0] lsbus_dummy2_s4_hwdata;
wire lsbus_dummy2_s4_hwrite;
wire lsbus_dummy3_intr;
wire [31:0] lsbus_dummy3_s5_haddr;
wire [2 :0] lsbus_dummy3_s5_hburst;
wire [3 :0] lsbus_dummy3_s5_hprot;
wire lsbus_dummy3_s5_hsel;
wire [2 :0] lsbus_dummy3_s5_hsize;
wire [1 :0] lsbus_dummy3_s5_htrans;
wire [31:0] lsbus_dummy3_s5_hwdata;
wire lsbus_dummy3_s5_hwrite;
wire [31:0] lsbus_hmain0_s10_hrdata;
wire lsbus_hmain0_s10_hready;
wire [1 :0] lsbus_hmain0_s10_hresp;
wire pmu_dummy0_s3clk;
wire pmu_dummy0_s3rst_b;
wire pmu_dummy1_s3clk;
wire pmu_dummy1_s3rst_b;
wire pmu_dummy2_s3clk;
wire pmu_dummy2_s3rst_b;
wire pmu_dummy3_s3clk;
wire pmu_dummy3_s3rst_b;
wire pmu_lsbus_hclk;
wire pmu_lsbus_hrst_b;
wire pmu_sub3_s3clk;
wire pmu_sub3_s3rst_b;
ahb_matrix_1_6_sub x_sub_ls_top (
.m_haddr (hmain0_lsbus_s10_haddr ),
.m_hburst (hmain0_lsbus_s10_hburst ),
.m_hprot (hmain0_lsbus_s10_hprot ),
.m_hrdata (lsbus_hmain0_s10_hrdata ),
.m_hready (lsbus_hmain0_s10_hready ),
.m_hresp (lsbus_hmain0_s10_hresp ),
.m_hselx (hmain0_lsbus_s10_hsel ),
.m_hsize (hmain0_lsbus_s10_hsize ),
.m_htrans (hmain0_lsbus_s10_htrans ),
.m_hwdata (hmain0_lsbus_s10_hwdata ),
.m_hwrite (hmain0_lsbus_s10_hwrite ),
.main_hclk (pmu_lsbus_hclk ),
.main_hresetn (pmu_lsbus_hrst_b ),
.pmu_matrix_clkdiv_bypass (1'b1 ),
.s0_haddr (lsbus_dummy0_s0_haddr ),
.s0_hburst (lsbus_dummy0_s0_hburst ),
.s0_hprot (lsbus_dummy0_s0_hprot ),
.s0_hrdata (dummy0_lsbus_s0_hrdata ),
.s0_hready (dummy0_lsbus_s0_hready ),
.s0_hresp (dummy0_lsbus_s0_hresp ),
.s0_hselx (lsbus_dummy0_s0_hsel ),
.s0_hsize (lsbus_dummy0_s0_hsize ),
.s0_htrans (lsbus_dummy0_s0_htrans ),
.s0_hwdata (lsbus_dummy0_s0_hwdata ),
.s0_hwrite (lsbus_dummy0_s0_hwrite ),
.s1_haddr (lsbus_dummy1_s1_haddr ),
.s1_hburst (lsbus_dummy1_s1_hburst ),
.s1_hprot (lsbus_dummy1_s1_hprot ),
.s1_hrdata (dummy1_lsbus_s1_hrdata ),
.s1_hready (dummy1_lsbus_s1_hready ),
.s1_hresp (dummy1_lsbus_s1_hresp ),
.s1_hselx (lsbus_dummy1_s1_hsel ),
.s1_hsize (lsbus_dummy1_s1_hsize ),
.s1_htrans (lsbus_dummy1_s1_htrans ),
.s1_hwdata (lsbus_dummy1_s1_hwdata ),
.s1_hwrite (lsbus_dummy1_s1_hwrite ),
.s2_haddr (lsbus_apb0_s2_haddr ),
.s2_hburst (lsbus_apb0_s2_hburst ),
.s2_hprot (lsbus_apb0_s2_hprot ),
.s2_hrdata (apb0_lsbus_s2_hrdata ),
.s2_hready (apb0_lsbus_s2_hready ),
.s2_hresp (apb0_lsbus_s2_hresp ),
.s2_hselx (lsbus_apb0_s2_hsel ),
.s2_hsize (lsbus_apb0_s2_hsize ),
.s2_htrans (lsbus_apb0_s2_htrans ),
.s2_hwdata (lsbus_apb0_s2_hwdata ),
.s2_hwrite (lsbus_apb0_s2_hwrite ),
.s3_haddr (lsbus_apb1_s3_haddr ),
.s3_hburst (lsbus_apb1_s3_hburst ),
.s3_hprot (lsbus_apb1_s3_hprot ),
.s3_hrdata (apb1_lsbus_s3_hrdata ),
.s3_hready (apb1_lsbus_s3_hready ),
.s3_hresp (apb1_lsbus_s3_hresp ),
.s3_hselx (lsbus_apb1_s3_hsel ),
.s3_hsize (lsbus_apb1_s3_hsize ),
.s3_htrans (lsbus_apb1_s3_htrans ),
.s3_hwdata (lsbus_apb1_s3_hwdata ),
.s3_hwrite (lsbus_apb1_s3_hwrite ),
.s4_haddr (lsbus_dummy2_s4_haddr ),
.s4_hburst (lsbus_dummy2_s4_hburst ),
.s4_hprot (lsbus_dummy2_s4_hprot ),
.s4_hrdata (dummy2_lsbus_s4_hrdata ),
.s4_hready (dummy2_lsbus_s4_hready ),
.s4_hresp (dummy2_lsbus_s4_hresp ),
.s4_hselx (lsbus_dummy2_s4_hsel ),
.s4_hsize (lsbus_dummy2_s4_hsize ),
.s4_htrans (lsbus_dummy2_s4_htrans ),
.s4_hwdata (lsbus_dummy2_s4_hwdata ),
.s4_hwrite (lsbus_dummy2_s4_hwrite ),
.s5_haddr (lsbus_dummy3_s5_haddr ),
.s5_hburst (lsbus_dummy3_s5_hburst ),
.s5_hprot (lsbus_dummy3_s5_hprot ),
.s5_hrdata (dummy3_lsbus_s5_hrdata ),
.s5_hready (dummy3_lsbus_s5_hready ),
.s5_hresp (dummy3_lsbus_s5_hresp ),
.s5_hselx (lsbus_dummy3_s5_hsel ),
.s5_hsize (lsbus_dummy3_s5_hsize ),
.s5_htrans (lsbus_dummy3_s5_htrans ),
.s5_hwdata (lsbus_dummy3_s5_hwdata ),
.s5_hwrite (lsbus_dummy3_s5_hwrite ),
.sub_hclk (pmu_sub3_s3clk ),
.sub_hresetn (pmu_sub3_s3rst_b )
);
ahb_dummy_top x_lsbus_dummy_top0 (
.haddr (lsbus_dummy0_s0_haddr ),
.hclk (pmu_dummy0_s3clk ),
.hprot (lsbus_dummy0_s0_hprot ),
.hrdata (dummy0_lsbus_s0_hrdata),
.hready (dummy0_lsbus_s0_hready),
.hresp (dummy0_lsbus_s0_hresp ),
.hrst_b (pmu_dummy0_s3rst_b ),
.hsel (lsbus_dummy0_s0_hsel ),
.hsize (lsbus_dummy0_s0_hsize ),
.htrans (lsbus_dummy0_s0_htrans),
.hwdata (lsbus_dummy0_s0_hwdata),
.hwrite (lsbus_dummy0_s0_hwrite),
.intr (lsbus_dummy0_intr )
);
ahb_dummy_top x_lsbus_dummy_top1 (
.haddr (lsbus_dummy1_s1_haddr ),
.hclk (pmu_dummy1_s3clk ),
.hprot (lsbus_dummy1_s1_hprot ),
.hrdata (dummy1_lsbus_s1_hrdata),
.hready (dummy1_lsbus_s1_hready),
.hresp (dummy1_lsbus_s1_hresp ),
.hrst_b (pmu_dummy1_s3rst_b ),
.hsel (lsbus_dummy1_s1_hsel ),
.hsize (lsbus_dummy1_s1_hsize ),
.htrans (lsbus_dummy1_s1_htrans),
.hwdata (lsbus_dummy1_s1_hwdata),
.hwrite (lsbus_dummy1_s1_hwrite),
.intr (lsbus_dummy1_intr )
);
ahb_dummy_top x_lsbus_dummy_top2 (
.haddr (lsbus_dummy2_s4_haddr ),
.hclk (pmu_dummy2_s3clk ),
.hprot (lsbus_dummy2_s4_hprot ),
.hrdata (dummy2_lsbus_s4_hrdata),
.hready (dummy2_lsbus_s4_hready),
.hresp (dummy2_lsbus_s4_hresp ),
.hrst_b (pmu_dummy2_s3rst_b ),
.hsel (lsbus_dummy2_s4_hsel ),
.hsize (lsbus_dummy2_s4_hsize ),
.htrans (lsbus_dummy2_s4_htrans),
.hwdata (lsbus_dummy2_s4_hwdata),
.hwrite (lsbus_dummy2_s4_hwrite),
.intr (lsbus_dummy2_intr )
);
ahb_dummy_top x_lsbus_dummy_top3 (
.haddr (lsbus_dummy3_s5_haddr ),
.hclk (pmu_dummy3_s3clk ),
.hprot (lsbus_dummy3_s5_hprot ),
.hrdata (dummy3_lsbus_s5_hrdata),
.hready (dummy3_lsbus_s5_hready),
.hresp (dummy3_lsbus_s5_hresp ),
.hrst_b (pmu_dummy3_s3rst_b ),
.hsel (lsbus_dummy3_s5_hsel ),
.hsize (lsbus_dummy3_s5_hsize ),
.htrans (lsbus_dummy3_s5_htrans),
.hwdata (lsbus_dummy3_s5_hwdata),
.hwrite (lsbus_dummy3_s5_hwrite),
.intr (lsbus_dummy3_intr )
);
endmodule |
module apb_dummy_top(
intr,
paddr,
pclk,
penable,
pprot,
prdata,
psel,
pwdata,
pwrite,
presetn
);
input [31:0] paddr;
input pclk;
input penable;
input [2 :0] pprot;
input psel;
input [31:0] pwdata;
input pwrite;
input presetn;
output [31:0] prdata;
output intr;
assign prdata[31:0] = 32'h0;
assign intr = 1'b0;
endmodule |
module ahb_dummy_top(
haddr,
hclk,
hprot,
hrdata,
hready,
hresp,
hrst_b,
hsel,
hsize,
htrans,
hwdata,
hwrite,
intr
);
input [31:0] haddr;
input hclk;
input [3 :0] hprot;
input hrst_b;
input hsel;
input [2 :0] hsize;
input [1 :0] htrans;
input [31:0] hwdata;
input hwrite;
output [31:0] hrdata;
output hready;
output [1 :0] hresp;
output intr;
wire [31:0] hrdata;
wire hready;
wire [1 :0] hresp;
wire intr;
assign hrdata[31:0] = 32'b0;
assign hready = 1'b1;
assign hresp[1:0] = 2'b0;
assign intr = 1'b0;
endmodule |
module ahbm_dummy_top(
hclk,
hrst_b,
mhrdata,
mhresp,
mhready,
mhgrant,
mhwdata,
mhburst,
mhtrans,
mhwrite,
mhaddr,
mhsize,
mhprot
);
output [31:0] mhaddr;
output [2 :0] mhburst;
output [3 :0] mhprot;
output [2 :0] mhsize;
output [1 :0] mhtrans;
output [31:0] mhwdata;
output mhwrite;
input hclk;
input hrst_b;
input mhgrant;
input [31:0] mhrdata;
input mhready;
input [1 :0] mhresp;
wire [31:0] mhaddr;
wire [2 :0] mhburst;
wire [3 :0] mhprot;
wire [2 :0] mhsize;
wire [1 :0] mhtrans;
wire [31:0] mhwdata;
wire mhwrite;
assign mhaddr[31:0] = 32'b0;
assign mhburst[2 :0] = 3'b0;
assign mhprot[3 :0] = 4'b0;
assign mhsize[2 :0] = 3'b0;
assign mhtrans[1 :0] = 2'b0;
assign mhwdata[31:0] = 32'b0;
assign mhwrite = 1'b0;
endmodule |
module Standard_Cell_CLK_GATE(
Q,
CK,
EN,
SE
);
output Q;
input CK;
input EN;
input SE;
wire E;
reg q_tmp;
assign E = SE | EN;
always @(E or CK)
begin
if(!CK)
q_tmp = E;
end
assign Q = q_tmp & CK;
endmodule |
module Standard_Cell_CLK_MUX2(
X,
S,
D0,
D1
);
output X;
input S;
input D0;
input D1;
assign X = S ? D1 : D0;
endmodule |
module fpga_byte_spram(
A,
CEN,
CLK,
D,
Q,
WEN
);
parameter ADDRWIDTH = 17;
parameter DATAWIDTH = 8;
parameter MEMDEPTH = 2**(ADDRWIDTH);
input [(ADDRWIDTH-1) :0] A;
input CEN;
input CLK;
input [(DATAWIDTH-1):0] D;
input WEN;
output [(DATAWIDTH-1):0] Q;
reg [(DATAWIDTH-1):0] Q;
reg [(DATAWIDTH-1):0] mem[(MEMDEPTH-1):0];
always@(posedge CLK)
begin
if(!CEN)
begin
if(!WEN)
begin
mem[A] <= D;
Q <= D;
end
else
begin
Q <= mem[A];
end
end
end
endmodule |
module fpga_spram(
A,
CEN,
CLK,
D,
Q,
BWEN
);
parameter DATAWIDTH = 32;
parameter ADDRWIDTH = 17;
parameter MEMDEPTH = 2**(ADDRWIDTH);
input [(ADDRWIDTH-1) :0] A;
input CEN;
input CLK;
input [(DATAWIDTH-1):0] D;
input [3:0] BWEN;
output [(DATAWIDTH-1):0] Q;
wire [(DATAWIDTH-1):0] Q;
fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte0_spram(
.A(A),
.CEN(CEN),
.CLK(CLK),
.D(D[7:0]),
.Q(Q[7:0]),
.WEN(BWEN[0])
);
fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte1_spram(
.A(A),
.CEN(CEN),
.CLK(CLK),
.D(D[15:8]),
.Q(Q[15:8]),
.WEN(BWEN[1])
);
fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte2_spram(
.A(A),
.CEN(CEN),
.CLK(CLK),
.D(D[23:16]),
.Q(Q[23:16]),
.WEN(BWEN[2])
);
fpga_byte_spram #(ADDRWIDTH,8,MEMDEPTH) x_fpga_byte3_spram(
.A(A),
.CEN(CEN),
.CLK(CLK),
.D(D[31:24]),
.Q(Q[31:24]),
.WEN(BWEN[3])
);
endmodule |
module PAD_DIG_IO(
OEN,
IEN,
OD,
ID,
PAD
);
input OEN;
input IEN;
output ID;
input OD;
inout PAD;
assign ID = IEN ? 1'bz : PAD;
assign PAD = OEN ? 1'bz : OD;
endmodule |
module PAD_OSC_IO(
EN ,
XOSC_OUT ,
XOSC_IN,
CLK
);
input EN;
input XOSC_IN;
output XOSC_OUT;
output CLK;
assign CLK = EN ? XOSC_IN : 1'b0;
assign XOSC_OUT = EN ? XOSC_IN : 1'b0;
endmodule |
module fifo_reader
#(
parameter WIDTH = 0,
parameter MAX_BLOCK_SIZE = 1024)
(
input clk,
input [WIDTH-1:0] din,
output reg rden = 1'b0,
input empty);
real rate = 0.5;
integer seed = 0;
time timeout = 0;
reg err_timeout = 0;
reg valid = 1'b0;
real randval;
always @(posedge clk) begin
valid <= rden & !empty;
randval = $dist_uniform(seed, 0, 1000) / 1000.0;
rden <= (randval <= rate) & !empty;
end
task read_word;
output [WIDTH-1:0] data_o;
reg rd;
time t0;
begin
t0 = $time;
while(!valid & !err_timeout) begin
@(posedge clk);
if(timeout > 0)
err_timeout = ($time-t0) > timeout;
end
if(err_timeout) begin
$display("%0d : Timeout in FIFO reader", $time);
$finish;
end
data_o = din;
err_timeout = 1'b0;
@(posedge clk);
end
endtask
endmodule |
module CLA_tb;
parameter N_EXP = 16384;
parameter N_PAT = N_EXP;
reg [7:0] gray_mem [0:N_PAT-1];
reg [7:0] exp_mem [0:N_EXP-1];
reg [7:0] ipf_dbg;
reg [7:0] exp_dbg;
wire [7:0] ipf_data;
reg clk = 0;
reg reset = 0;
reg [1:0] mode;
reg result_compare = 0;
integer err = 0;
integer times = 0;
reg over = 0;
integer exp_num = 0;
wire [13:0] gray_addr;
wire [13:0] ipf_addr;
reg [7:0] gray_data;
reg gray_ready = 0;
integer i;
CLA CLA( .clk(clk),
.reset(reset),
.mode(mode),
.gray_addr(gray_addr),
.gray_req(gray_req),
.gray_ready(gray_ready),
.gray_data(gray_data),
.ipf_addr(ipf_addr),
.ipf_valid(ipf_valid),
.ipf_data(ipf_data),
.finish(finish));
ipf_mem u_ipf_mem(.ipf_valid(ipf_valid), .ipf_data(ipf_data), .ipf_addr(ipf_addr), .clk(clk));
initial begin
$readmemh (`PAT, gray_mem);
end
initial begin
`ifdef MODE0
//$display("0");
$readmemh (`EXP0, exp_mem);
`endif
`ifdef MODE1
//$display("1");
$readmemh (`EXP1, exp_mem);
`endif
`ifdef MODE2
//$display("2");
$readmemh (`EXP2, exp_mem);
`endif
end
always begin #(`CYCLE/2) clk = ~clk; end
initial begin
`ifdef SDF
$sdf_annotate(`SDFFILE, CLA);
$fsdbDumpfile("CLA_syn.fsdb");
`else
$fsdbDumpfile("CLA.fsdb");
`endif
$fsdbDumpvars;
end
initial begin // data input
@(negedge clk) reset = 1'b1;
#(`CYCLE*2); reset = 1'b0;
@(negedge clk) gray_ready = 1'b1;
mode = 2'd0;
`ifdef MODE1
mode = 2'd1;
`endif
`ifdef MODE2
mode = 2'd2;
`endif
while (finish == 0) begin
if( gray_req ) begin
gray_data = gray_mem[gray_addr];
end
else begin
gray_data = 'hz;
end
@(negedge clk);
end
gray_ready = 0; gray_data='hz;
@(posedge clk) result_compare = 1;
end
initial begin // result compare
$display("-----------------------------------------------------\n");
$display("START!!! Simulation Start .....\n");
$display("-----------------------------------------------------\n");
#(`CYCLE*3);
wait( finish ) ;
@(posedge clk); @(posedge clk);
for (i=0; i <N_PAT ; i=i+1) begin
//@(posedge clk); // TRY IT ! no comment this line for debugging !!
exp_dbg = exp_mem[i]; ipf_dbg = u_ipf_mem.ipf_M[i];
if (exp_mem[i] == u_ipf_mem.ipf_M[i]) begin
err = err;
end
else begin
//$display("pixel %d is FAIL !!", i);
err = err+1;
if (err <= 10) $display("Output pixel %d are wrong!", i);
if (err == 11) begin $display("Find the wrong pixel reached a total of more than 10 !, Please check the code .....\n"); end
end
if( ((i%1000) === 0) || (i == 16383))begin
if ( err === 0)
$display("Output pixel: 0 ~ %d are correct!\n", i);
else
$display("Output Pixel: 0 ~ %d are wrong ! The wrong pixel reached a total of %d or more ! \n", i, err);
end
exp_num = exp_num + 1;
end
over = 1;
end
initial begin
#`End_CYCLE ;
$display("-----------------------------------------------------\n");
$display("Error!!! Somethings' wrong with your code ...!\n");
$display("-------------------------FAIL------------------------\n");
$display("-----------------------------------------------------\n");
$finish;
end
integer f;
reg check;
initial begin
`ifdef MODE0
f = $fopen("pattern0.txt","w");
`endif
`ifdef MODE1
f = $fopen("pattern1.txt","w");
`endif
`ifdef MODE2
f = $fopen("pattern2.txt","w");
`endif
@(posedge over)
if((over) && (exp_num!='d0)) begin
$display("-----------------------------------------------------\n");
if (err == 0) begin
$display("Congratulations! All data have been generated successfully!\n");
$display("-------------------------PASS------------------------\n");
check = 1;
$fwrite(f, "%d\n", check);
end
else begin
$display("There are %d errors!\n", err);
$display("-----------------------------------------------------\n");
check = 0;
$fwrite(f, "%d\n", check);
end
end
#(`CYCLE/2); $finish;
end
endmodule |
module bs_mult_tb;
initial begin
$fsdbDumpfile("bs_mult");
$fsdbDumpvars;
end
reg clk = 1'b1;
always #10 clk <= ~clk;
reg x = 1'b0;
reg y = 1'b0;
reg fb = 1'b0;
reg lb = 1'b0;
wire p;
integer i = -1;
bs_mult I0(.clk(clk), .x(x), .y(y), .p(p), .firstbit(fb), .lastbit(lb));
initial begin
@(posedge clk);
lb <= 1'b1;
// bit 0
@(posedge clk);
i <= 0;
lb <= 1'b0; fb <= 1'b1;
x <= 1'b1; y <= 1'b1;
// bit 1
@(posedge clk);
i <= 1;
x <= 1'b1; y <= 1'b0;
fb <= 1'b0;
// bit 2
@(posedge clk);
i <= 2;
x <= 1'b1; y <= 1'b1;
// bit 3
@(posedge clk);
i <= 3;
x <= 1'b1; y <= 1'b1;
// bit 4
@(posedge clk);
i <= 4;
x <= 1'b1; y <= 1'b1;
// bit 5
@(posedge clk);
i <= 5;
x <= 1'b1; y <= 1'b1;
// bit 6
@(posedge clk);
i <= 6;
x <= 1'b1; y <= 1'b1;
// bit 7
@(posedge clk);
i <= 7;
x <= 1'b1; y <= 1'b1;
// bit 8
@(posedge clk);
i <= 8;
x <= 1'b1; y <= 1'b1;
// bit 9
@(posedge clk);
i <= 9;
x <= 1'b1; y <= 1'b1;
// bit 10
@(posedge clk);
i <= 10;
x <= 1'b1; y <= 1'b1;
// bit 11
@(posedge clk);
i <= 11;
x <= 1'b1; y <= 1'b1;
// bit 12
@(posedge clk);
i <= 12;
x <= 1'b1; y <= 1'b1;
// bit 13
@(posedge clk);
i <= 13;
x <= 1'b1; y <= 1'b1;
// bit 14
@(posedge clk);
i <= 14;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 15;
x <= 1'b1; y <= 1'b1;
// bit 16
@(posedge clk);
i <= 16;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 17;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 18;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 19;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 20;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 21;
x <= 1'b1; y <= 1'b1;
// bit 22
@(posedge clk);
i <= 22;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 23;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 24;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 25;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 26;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 27;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 28;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 29;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 30;
x <= 1'b1; y <= 1'b1;
// bit 15
@(posedge clk);
i <= 31;
x <= 1'b1; y <= 1'b1;
lb <= 1'b1;
// ends here
@(posedge clk);
i <= 0;
x <= 1'b0; y <= 1'b0;
lb <= 1'b0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish;
end
endmodule |
module dpram2 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module mypll2 (
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
locked,
phasedone);
input inclk0;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [2:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module lp_ram_dp (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [12:0] rdaddress;
input rdclock;
input rden;
input [12:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 rden;
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module processor_slave(clk, rxReady, rxData, txBusy, txStart, txData, readdata, newgotdata, gotdata);
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
output reg[7:0] readdata;//first byte we got
input newgotdata;//from other processor
input[7:0] gotdata;
localparam READ=0, SOLVING=1, WRITE1=2, WRITE2=3;
localparam LEN = 1;
localparam LENMAX = LEN - 1;
integer ioCount;
reg[7:0] data[0:LENMAX];
integer state;
initial begin
state = READ;
end
always @(posedge clk) begin
case (state)
READ: begin
txStart = 0;
if (rxReady) begin
data[ioCount] = rxData;
if (ioCount == 0) readdata = rxData;
if (ioCount == LENMAX) begin
ioCount = 0;
state = SOLVING;
end else begin
ioCount = ioCount + 1;
end
end
if (newgotdata) begin
ioCount = 0;
data[0]=gotdata;
state=WRITE1;
end
end
SOLVING: begin
begin
//if (readdata == 49) get_ext_data=1;
end
state=READ;
//state = WRITE1;
end
WRITE1: begin
if (!txBusy) begin
txData = data[ioCount];
txStart = 1;
state = WRITE2;
end
end
WRITE2: begin
txStart = 0;
if (ioCount != LENMAX) begin
ioCount = ioCount + 1;
state = WRITE1;
end else begin
ioCount = 0;
state = READ;
end
end
endcase
end
endmodule |
module oscillo(clk, RxD, TxD, clk_flash, data_flash);
input clk;
input RxD;
output TxD;
input clk_flash;
input [7:0] data_flash;
///////////////////////////////////////////////////////////////////
//wire [7:0] RxD_data;
//async_receiver async_rxd(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data));
reg startAcquisition;
wire AcquisitionStarted;
always @(posedge clk)
if(~startAcquisition)
//startAcquisition <= RxD_data_ready;
startAcquisition <= RxD;
else
if(AcquisitionStarted)
startAcquisition <= 0;
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition ;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
reg Acquiring;
always @(posedge clk_flash)
if(~Acquiring)
Acquiring <= startAcquisition2;
else
if(&wraddress)
Acquiring <= 0;
reg [8:0] wraddress;
always @(posedge clk_flash) if(Acquiring) wraddress <= wraddress + 1;
reg Acquiring1; always @(posedge clk) Acquiring1 <= Acquiring;
reg Acquiring2; always @(posedge clk) Acquiring2 <= Acquiring1;
assign AcquisitionStarted = Acquiring2;
reg [8:0] rdaddress;
reg Sending;
wire TxD_busy;
always @(posedge clk)
if(~Sending)
Sending <= AcquisitionStarted;
else
if(~TxD_busy)
begin
rdaddress <= rdaddress + 1;
if(&rdaddress) Sending <= 0;
end
wire TxD_start = ~TxD_busy & Sending;
wire rden = TxD_start;
wire [7:0] ram_output;
async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(ram_output));
///////////////////////////////////////////////////////////////////
reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;
LPM_RAM_DP #(.LPM_WIDTH(8), .LPM_WIDTHAD(9)) ram_flash (
.data(data_flash_reg), .wraddress(wraddress), .wren(Acquiring), .wrclock(clk_flash),
.q(ram_output), .rdaddress(rdaddress), .rden(rden), .rdclock(clk)
);
endmodule |
module ram2 (
address,
clock,
data,
wren,
q);
input [9:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule |
module lp_ram_dp_2 (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input [4:0] data;
input [12:0] rdaddress;
input rdclock;
input rden;
input [12:0] wraddress;
input wrclock;
input wren;
output [4:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 rden;
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module pong(clk, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, PaddlePosition);
input clk;
input [7:0] PaddlePosition;
output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B;
wire inDisplayArea;
wire [9:0] CounterX;
wire [8:0] CounterY;
hvsync_generator syncgen(.clk(clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync),
.inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));
/////////////////////////////////////////////////////////////////
wire border = (CounterX[9:3]==0) || (CounterX[9:3]==79) || (CounterY[8:3]==0) || (CounterY[8:3]==59);
wire[10:0] PaddlePosition2 = (PaddlePosition-49)*80;
wire paddle = (CounterX>=PaddlePosition2+8) && (CounterX<=PaddlePosition2+120) && (CounterY[8:4]==27);
wire BouncingObject = border | paddle; // active if the border or paddle is redrawing itself
/////////////////////////////////////////////////////////////////
parameter Nballs = 15;
wire [Nballs:0] inball;
reg [Nballs:0] inotherball;
wire [9:0] ballX [Nballs:0];
wire [8:0] ballY [Nballs:0];
wire [8:0] ballspeed [Nballs:0];
wire [8:0] ballmass [Nballs:0];
generate
genvar i;
for (i=0; i<Nballs; i=i+1) begin : dff
mball #(.startX(20+((131*i)%600)), .startY(29+((7*i)%440)), .pballmass(1), .pballspeed(1)) ball_i (.clk(clk),
.BouncingObject(BouncingObject), .inotherball(inotherball[i]),
.CounterX(CounterX), .CounterY(CounterY), .ballX(ballX[i]), .ballY(ballY[i]),
.inball(inball[i]), .ballspeed(ballspeed[i]), .ballmass(ballmass[i]) );
end
endgenerate
/////////////////////////////////////////////////////////////////
wire inaball = (inball!=0);
wire R = BouncingObject | inaball | (CounterX[3] ^ CounterY[3]);
wire G = BouncingObject | inaball;
wire B = BouncingObject | inaball;
reg [Nballs:0] iball;
reg [Nballs:0] jball;
always @(posedge clk) begin
for (iball=0; iball<Nballs; iball=iball+1) begin
inotherball[iball] = 0;
for (jball=0; jball<Nballs; jball=jball+1) begin
if (inball[iball] & iball!=jball & inball[jball]) inotherball[iball] = 1;//ballmass[jball]*ballspeed[jball];
end
end
end
reg vga_R, vga_G, vga_B;
always @(posedge clk) begin
vga_R <= R & inDisplayArea;
vga_G <= G & inDisplayArea;
vga_B <= B & inDisplayArea;
end
endmodule |
module uniqueid2 (
input wire clkin, // clkin.clk
input wire reset, // reset.reset
output wire data_valid, // output.valid
output wire [63:0] chip_id // .data
);
altchip_id #(
.DEVICE_FAMILY ("MAX 10"),
.ID_VALUE (64'b1111111111111111111111111111111111111111111111111111111111111111),
.ID_VALUE_STR ("00000000ffffffff")
) uniqueid2_inst (
.clkin (clkin), // clkin.clk
.reset (reset), // reset.reset
.data_valid (data_valid), // output.valid
.chip_id (chip_id) // .data
);
endmodule |
module demux1to2( Data_in, sel, Data_out_0, Data_out_1 );
//list the inputs and their sizes
input Data_in;
input sel;
//list the outputs and their sizes
output Data_out_0;
output Data_out_1;
//Internal variables
reg Data_out_0;
reg Data_out_1;
//always block with Data_in and sel in its sensitivity list
always @(Data_in or sel)
begin
case (sel)
1'b0 : begin
Data_out_0 = Data_in;
Data_out_1 = 0;
end
1'b1 : begin
Data_out_0 = 0;
Data_out_1 = Data_in;
end
endcase
end
endmodule |
module ring_counter (clk,out_carry,carryin,carryout,delayin,start,out_delay);
input clk;
output reg [7:0] out_carry;
output reg [7:0] out_delay;
input carryin;
output carryout;
input wire [DELAY-1:0] delayin;
parameter DELAY=100; // about 13-14 per tick (10ns) // actually set in serial bdf design file
wire [DELAY-1:0] delay_line /* synthesis keep */;
output reg start;
reg freeze;
assign carryout = freeze; // set the output high when we freeze
wire freezeline;
// assign freezeline = freeze; // freeze the chain whenever we say to freeze internally
assign freezeline = carryin; // freeze the chain based on external freeze signal
//delay line
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
begin : del
//assign delay_line [i] = delay_line[i-1+freezeline]; // when freeze is 1, it just is assigned to itself... otherwise it is assigned to it's friend from the left
assign delay_line [i] = (freezeline) ? delay_line[i] : delay_line[i-1]; // when freeze is 1, it just is assigned to itself... otherwise it is assigned to it's friend from the left
end
endgenerate
assign delay_line[0] = start; // we trigger the chain with the "start" command
initial begin
start<=0;
freeze<=0;
end
//sync them over to the input clock
integer delay_counter=0;
always @(posedge clk) begin
if (freeze) begin
//count until the first 0
if (delay_line[delay_counter]) delay_counter=delay_counter+1;//keep counting
else out_delay[7:0] = delay_counter;//found the first 0
end
else delay_counter=0;//just wait
end
integer counter=0;
integer delayer=0;
//integer cycles=0;
always @(posedge clk) begin
counter = counter+1;
if (counter==200000000) begin // every 2 seconds, reset to 0 and wait for start
freeze=0;
start=0;
end
if (counter==200000050) begin // 500 ns later, start
start=1;
end
if (counter==200000050+delayer) begin // then freeze, after some delay possibly
freeze=1;
// cycles=cycles+1;
// if (cycles==10) begin //every 3 seconds, increment the delayer time by a tick
// delayer=delayer+1;
// cycles=7;//wait 10 seconds before starting up the incrementing
// end
end
if (counter==200000050+delayer+ 100000) counter=0;//do it again
end
integer delay_counter2=1;
always @(posedge clk) begin
if (counter > 200000050+delayer + 10) begin // give it time to stop
//count until a 1
if (delayin[delay_counter2]) out_carry[7:0] = delay_counter2 - 150;//found a 1
else delay_counter2=delay_counter2+1;//keep counting
end
else delay_counter2=1;//just wait
end
endmodule |
module chain_delay(clk,start,stop,result);
input clk, start, stop;
parameter CHAIN_LEN = 200;
wire [CHAIN_LEN-2:0] input1 = {{CHAIN_LEN-2{1'b0}},start} /* synthesis keep */; // that's ...0000000 or ...00000001
wire [CHAIN_LEN-1:0] chain = {CHAIN_LEN-1{1'b1}} + input1 /* synthesis keep */; // that's 1111...1111, added to 1 or 0
// I think it works like this...
// when start is 0: 011111111 + 0000 = 011111111
// when start goes to 1: 011111111 + 0001 = 100000000 i.e. 255+1=256
// before the operation completes: 011110000, so the more 0's, the longer it ran
// if it got to the end, the last bit should be a 1
output reg [CHAIN_LEN-1:0] result /* synthesis keep */;
always @(posedge stop) result<=chain;
endmodule |
module ram1 (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [11:0] data;
input wren;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule |
module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthreshtwo,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp, trigout, spareright, spareleft,
delaycounter,ext_trig_delay, noselftrig, nselftrigcoincidentreq, selftrigtempholdtime, allowsamechancoin,
trigratecounter,trigratecountreset);
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;//to power up adc, set low
output reg pwr2=0;//to power up adc, set low
output reg shdn_out=0;//Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated on the falling edge of SHDN.
output reg spen_out=0;//Active-Low SPI Enable. Drive high to enable parallel programming mode.
output reg format_sdin_out=0;//0=2's complement, 1=offset binary, unconnected=gray code
output reg div_sclk_out=0;//0=divide clock by 1, 1=divide clock by 2, unconnected=divide clock by 4
output reg outsel_cs_out=1;//0=CMOS (dual bus), 1=MUX CMOS (channel A data bus), unconnected=MUX CMOS (channel b data bus)
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
reg[ram_width-1:0] wraddress_triggerpoint2;//to pass timing (need to send to slow clk domain)
input wire [ram_width-1:0] rdaddress;
input wire rden;//read enable
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthreshtwo;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample; // only record 1 out of every 2^downsample samples
reg [7:0] downsample2; // to pass timing
input [3:0] triggertype;
reg [3:0] triggertype2; // to pass timing
input [ram_width:0] triggertot; // the top bit says whether to do check every sample or only according to downsample
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [ram_width-1:0] nsmp2; // to pass timing
input [4:0] ext_trig_delay; // clk ticks to delay ext trigger by
input noselftrig;
input [1:0] nselftrigcoincidentreq; // number of self trig channels required to be fired simultaneously
input [7:0] selftrigtempholdtime; // how long to fire a channel for
input allowsamechancoin; // whether to allow same channel, firing in the past, to count as coincidence
output reg [3:0] trigout;
output wire spareright;
input wire spareleft;
reg [31:0] SPIcounter=0;//clock counter for SPI
input [15:0] SPIsenddata;//the bits to send
input SPIsend;//start sending
reg [3:0] SPIsendcounter;//which bit to send
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin // we're in SPI mode
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin // this is the beginning
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;//start high
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin // start of sending, note that we wait a full tick (was 4)
div_sclk_out=0;
outsel_cs_out=0;//start sending
format_sdin_out=SPIsenddata[SPIsendcounter];//the data
SPIsendcounter=SPIsendcounter-4'b001;//keep track of how many bits we've sent
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin // sending data on rising edge, note that we wait a full tick
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3; //done
else SPIstate=SPI1;//send next bit
end
end
SPI3: begin
if (SPIcounter[2]) begin // done sending, note that we wait a full tick
outsel_cs_out=1;//back to high
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end // SPI mode
end // clk_spi posedge
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];//keep track of the counter time it was above/below threshold for
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2; // no multiplexing
//reg [7:0] data_flash2_reg; always @(negedge clk_flash) data_flash2_reg <= data_flash1; // for multiplexing
reg [7:0] data_flash3_reg_temp; always @(posedge clk_flash2) data_flash3_reg_temp <= data_flash3;
reg [7:0] data_flash4_reg_temp; always @(posedge clk_flash2) data_flash4_reg_temp <= data_flash4; // no multiplexing
//reg [7:0] data_flash4_reg_temp; always @(negedge clk_flash2) data_flash4_reg_temp <= data_flash3; // for multiplexing
//pipelines the reading in from clk2 to clk1, so we have a full clk1 cycle for calculations below
reg [7:0] data_flash3_reg; always @(posedge clk_flash) data_flash3_reg <= data_flash3_reg_temp;
reg [7:0] data_flash4_reg; always @(posedge clk_flash) data_flash4_reg <= data_flash4_reg_temp; // no multiplexing
//reg [7:0] data_flash4_reg; always @(negedge clk_flash) data_flash4_reg <= data_flash3_reg_temp; // for multiplexing
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
//if (trigchannels[i]) begin // always calculate the trigger, for output, even if we won't self-trigger on it
// above threshold now?
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthreshtwo);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthreshtwo);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthreshtwo);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthreshtwo);
Threshold2[i] <= Threshold1[i]; // was above threshold?
if (triggertype2[0]) begin // if positive edge, trigger! (possibly after demanding a timeout)
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;//assume we are not firing
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin // only check every 2^downsample samples
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been above threshold
else Threshold3[i] <= 0; // reset once it goes below threshold
end
end
else begin // check every sample
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been above threshold
else Threshold3[i] <= 0; // reset once it goes below threshold
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin //fired!
selftrigtemp[i] = 1;
Threshold3[i] <= 0; // reset once it fires
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin // got a positive edge
Threshold3[i] <= 1; // start counting
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);// got a positive edge, just trigger
end
else begin // if negative edge, trigger! (possibly after demanding a timeout)
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;//assume we are not firing
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin // only check every 2^downsample samples
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been below threshold
else Threshold3[i] <= 0; // reset once it goes above threshold
end
end
else begin // check every sample
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been below threshold
else Threshold3[i] <= 0; // reset once it goes above threshold
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin //fired!
selftrigtemp[i] = 1;
Threshold3[i] <= 0; // reset once it fires
end
end
else if (~Threshold1[i] & Threshold2[i]) begin // got a negative edge
Threshold3[i] <= 1; // start counting
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);// got a negative edge, just trigger
end
//end // if (trigchannels[i])
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[ext_trig_delay];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter; // counter for the rolling trigger
reg[1:0] nselftrigstemp[4]; // number of self trig channels fired, other than this one
reg[7:0] selftrigtemphold[4]; // will keep track of which channel have fired
always @(posedge clk_flash) begin
if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
i=0;
while (i<4) begin
if (selftrigtemp[i]) selftrigtemphold[i]<=selftrigtempholdtime; // trigger has fired
else if (selftrigtemphold[i]>0 && downsamplego) selftrigtemphold[i]<=selftrigtemphold[i]-1; // count down (paying attention to downsample) so the trigger stops firing after selftrigtempholdtime
if (allowsamechancoin) nselftrigstemp[i] <= (trigchannels[(i)%4]&&selftrigtemphold[(i)%4]>0) + (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
else nselftrigstemp[i] <= (trigchannels[(i+1)%4]&&selftrigtemphold[(i+1)%4]>0) + (trigchannels[(i+2)%4]&&selftrigtemphold[(i+2)%4]>0) + (trigchannels[(i+3)%4]&&selftrigtemphold[(i+3)%4]>0);
i=i+1;
end
end
wire selfedgetrig; // currently on an edge
assign selfedgetrig = (trigchannels[0]&&selftrigtemp[0]&&nselftrigstemp[0]>=nselftrigcoincidentreq)||
(trigchannels[1]&&selftrigtemp[1]&&nselftrigstemp[1]>=nselftrigcoincidentreq)||
(trigchannels[2]&&selftrigtemp[2]&&nselftrigstemp[2]>=nselftrigcoincidentreq)||
(trigchannels[3]&&selftrigtemp[3]&&nselftrigstemp[3]>=nselftrigcoincidentreq);
wire selftrig; //trigger is an OR of all the channels which are active // also trigger every second or so (rolling)
assign selftrig = selfedgetrig || (rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
// trigger rate counter stuff
output reg[31:0] trigratecounter=0;
input trigratecountreset;
reg [7:0] selfedgetrigdeadtime=0; // to keep track of deadtime for the trigger rate counter
always @(posedge clk_flash) begin
if (selfedgetrig && selfedgetrigdeadtime==0) begin // only count it if the counter is not dead because a trigger fired recently
trigratecounter = trigratecounter+1;
selfedgetrigdeadtime<=selftrigtempholdtime; // trigger has fired, start counting down deadtime, from selftrigtempholdtime (same as used for coincidence trigger)
end
if (selfedgetrigdeadtime>0 && downsamplego) selfedgetrigdeadtime<=selfedgetrigdeadtime-1; // count down deadtime (paying attention to downsample) so the trigger stops being dead after selftrigtempholdtime
if (trigratecountreset) trigratecounter=0;
end
// end trigger rate counter stuff
always @(posedge clk_flash)
if (noselftrig) Trigger = trig_in[1]; // just trigger if we get a trigger in towards to right
else if (imthefirst & imthelast) Trigger = selftrig; // we trigger if we triggered ourselves
else if (imthefirst) Trigger = selftrig||trig_in[1]; // we trigger if we triggered ourselves, or got a trigger in towards the right
else if (imthelast) Trigger = selftrig||trig_in[0]; // we trigger if we triggered ourselves, or got a trigger in towards the left
else Trigger = selftrig||trig_in[0]||trig_in[1]; // we trigger if we triggered ourselves, or got a trigger from the left or right
always @(posedge clk_flash)
if (noselftrig) trig_out[0] = 0; // we don't trigger out to the left
else if (imthefirst) trig_out[0] = selftrig; // we trigger out to the left if we triggered ourselves
else trig_out[0] = trig_in[0]||selftrig; // we trigger out to the left if we got a trig in towards the left, or we triggered ourselves
always @(posedge clk_flash)
if (noselftrig) trig_out[1] = trig_in[1]; // we trigger out to the right if we got a trig in towards the right
else if (imthelast) trig_out[1] = selftrig; // we trigger out to the right if we triggered ourselves
else trig_out[1] = trig_in[1]||selftrig; // we trigger out to the right if we got a trig in towards the right, or we triggered ourselves
reg Ttrig[4]; // whether to fire each of the 4 trigger bits
reg[3:0] Tcounter[4]; // counters for the output trigger bits (to hold them high for a while after a trigger)
reg[7:0] Tcounter_test_countdown; // use for sending 50 test triggers
output reg[7:0] delaycounter;
reg[7:0] spareleftcounter;
always @(posedge clk_flash) begin
if (spareleft) begin
if (spareleftcounter<205) begin
spareleftcounter<=spareleftcounter+1; // delays for 205 ticks, to wait for trigger board to be ready for counting (it was waiting for all normal triggers from all boards to cease)
Ttrig[0]<=0; Ttrig[1]<=0; Ttrig[2]<=0; Ttrig[3]<=0; // no pulses yet
Tcounter[0]<=0; Tcounter[1]<=0; Tcounter[2]<=0; Tcounter[3]<=0; //reset trig counters
end
else begin
Ttrig[0] <= (Tcounter_test_countdown!=0); // for calibration (clock skew) we fire trigger 0
if (Tcounter_test_countdown) Tcounter_test_countdown <= Tcounter_test_countdown-1;
end
end
else begin
i=0; while (i<4) begin
if (selftrigtemp[i]) Tcounter[i]<=4; // will count down from 4 to send the trigger out once
else if (Tcounter[i]) Tcounter[i]<=Tcounter[i]-1;
Ttrig[i] <= (Tcounter[i]>0);
i=i+1;
end
Tcounter_test_countdown <= 219; // should give 54 or 55 pulses (depending on when spareleft fires)
spareleftcounter<=0;
end
end
reg[1:0] Pulsecounter=0;
reg[3:0] trig_ext_out=4'd0;
always @(posedge clk_flash) begin
if (noselftrig) trigout[0]<=(Ttrig[Pulsecounter]);
else begin
if (Trigger) begin
trig_ext_out<=4'd10;//time to fire trig_ext_out for (max 15)
trigout[0]<=1'b1;
end
else if (trig_ext_out>4'd0) begin
trig_ext_out<=trig_ext_out-4'd1;
trigout[0]<=1'b1;
end
else trigout[0]<=1'b0;
end
Pulsecounter<=Pulsecounter+1; // for iterating through the trigger bins
end
assign spareright = spareleft; // pass the calibration signal along to the right
reg startAcquisition;//ready to trigger?
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger; // an input to the module
else if(AcquiringAndTriggered2) startAcquisition <= 0;
//assign trigDebug = startAcquisition;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
reg[2:0] state=INIT;
reg [23:0] downsamplecounter;//max downsample is 22
reg [maxhighres:0] highrescounter;//for counting highres
wire downsamplego;
assign downsamplego = downsamplecounter[downsample2] || downsample2==0; // pay attention to sample when downsamplego is true
always @(posedge clk_flash) begin
nsmp2<=nsmp;//to pass timing
triggertype2<=triggertype;//to pass timing
downsample2<=downsample;//to pass timing
case (state)
INIT: begin // this is the beginning... wait for the go-ahead to start acquiring the pre-trigger samples
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1; // start acquiring?
HaveFullData <= 0;
PreOrPostAcquiring <= 1; // preacquiring
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin // pre-trigger bytes acquired already?
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin // now we wait for the trigger, and then record the triggerpoint
AcquiringAndTriggered <= 1; // Trigger? Start getting the rest of the bytes
PreOrPostAcquiring <= 1;
wraddress_triggerpoint2 <= wraddress; // keep track of where the trigger happened
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp2) begin // got the rest of the bytes? then stop acquiring
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres) begin // doing highres mode (averaging over samples within each downsample)
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample2>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample2;
dout2=highres2>>downsample2;
dout3=highres3>>downsample2;
dout4=highres4>>downsample2;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin // not highres mode, just copy in the data
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin // increment the write address (store new data) every 1/2^downsample samples
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
// go from flash clock to fpga main clock domain
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
wraddress_triggerpoint=wraddress_triggerpoint2; // sends to slow clk domain
if (startAcquisition) data_ready=0; // waiting for trigger
else if (HaveFullData2) data_ready=1; // ready to read out
end
endmodule |
module ram1 (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [11:0] data;
input wren;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY);
input clk;
output vga_h_sync, vga_v_sync;
output inDisplayArea;
output [9:0] CounterX;
output [8:0] CounterY;
//////////////////////////////////////////////////
reg [9:0] CounterX;
reg CounterXflip;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==767);
always @(posedge clk)
if(CounterXmaxed)
CounterX <= 0;
else begin
if (CounterXflip) CounterX <= CounterX + 1;
CounterXflip <= ~CounterXflip;//goes from 0 to 1, so we only increment half the times (for 50Mhz!)
end
always @(posedge clk)
if(CounterXmaxed) CounterY <= CounterY + 1;
reg vga_HS, vga_VS;
always @(posedge clk)
begin
vga_HS <= (CounterX[9:4]==45); // change this value to move the display horizontally
vga_VS <= (CounterY==498); // change this value to move the display vertically
end
reg inDisplayArea;
always @(posedge clk)
if(inDisplayArea==0)
inDisplayArea <= (CounterXmaxed) && (CounterY<480);
else
inDisplayArea <= !(CounterX==639);
assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;
endmodule |
module dpram2 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule |
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 8; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
`ifdef SIMULATION
assign RxD_idle = 0;
`else
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
`endif
endmodule |
module ASSERTION_ERROR();
endmodule |
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule |
module ram2 (
address,
clock,
data,
wren,
q);
input [9:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module mypll2 (
inclk0,
c0,
c1,
c2,
c3,
c4,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
endmodule |
module mypll2 (
inclk0,
c0,
c1,
c2,
c3,
c4,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire9;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [4:4] sub_wire8 = sub_wire3[4:4];
wire [3:3] sub_wire7 = sub_wire3[3:3];
wire [2:2] sub_wire6 = sub_wire3[2:2];
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire c2 = sub_wire6;
wire c3 = sub_wire7;
wire c4 = sub_wire8;
wire locked = sub_wire9;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire9),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 2,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 5,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 5,
altpll_component.clk3_phase_shift = "0",
altpll_component.clk4_divide_by = 2,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 5,
altpll_component.clk4_phase_shift = "4000",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=mypll2",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule |
module oscillo(clk, startTrigger, clk_flash, data_flash1, data_flash2, data_flash3, data_flash4, pwr1, pwr2, shdn_out, spen_out, trig_in, trig_out, rden, rdaddress,
data_ready, wraddress_triggerpoint, imthelast, imthefirst,rollingtrigger,trigDebug,triggerpoint,downsample,
trigthresh,trigchannels,triggertype,triggertot,format_sdin_out,div_sclk_out,outsel_cs_out,clk_spi,SPIsend,SPIsenddata,
wraddress,Acquiring,SPIstate,clk_flash2,trigthresh2,dout1,dout2,dout3,dout4,highres,ext_trig_in,use_ext_trig, nsmp);
input clk,clk_spi;
input startTrigger;
input [1:0] trig_in;
output reg [1:0] trig_out;
output reg pwr1=0;//to power up adc, set low
output reg pwr2=0;//to power up adc, set low
output reg shdn_out=0;//Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated on the falling edge of SHDN.
output reg spen_out=0;//Active-Low SPI Enable. Drive high to enable parallel programming mode.
output reg format_sdin_out=0;//0=2's complement, 1=offset binary, unconnected=gray code
output reg div_sclk_out=0;//0=divide clock by 1, 1=divide clock by 2, unconnected=divide clock by 4
output reg outsel_cs_out=1;//0=CMOS (dual bus), 1=MUX CMOS (channel A data bus), unconnected=MUX CMOS (channel b data bus)
input clk_flash, clk_flash2;
input [7:0] data_flash1, data_flash2, data_flash3, data_flash4;
output reg [7:0] dout1, dout2, dout3, dout4;
parameter ram_width=10;
output reg[ram_width-1:0] wraddress_triggerpoint;
input wire [ram_width-1:0] rdaddress;
input wire rden;//read enable
output reg data_ready=0;
input wire imthelast, imthefirst;
input wire rollingtrigger;
output reg trigDebug=1;
input [7:0] trigthresh, trigthresh2;
input [3:0] trigchannels;
input [ram_width-1:0] triggerpoint;
input [7:0] downsample; // only record 1 out of every 2^downsample samples
input [3:0] triggertype;
input [ram_width:0] triggertot; // the top bit says whether to do check every sample or only according to downsample
input highres;
parameter maxhighres=5;
reg [7+maxhighres:0] highres1, highres2, highres3, highres4;
input ext_trig_in, use_ext_trig;
input [ram_width-1:0] nsmp;
reg [31:0] SPIcounter=0;//clock counter for SPI
input [15:0] SPIsenddata;//the bits to send
input SPIsend;//start sending
reg [3:0] SPIsendcounter;//which bit to send
localparam SPI0=0, SPI1=1, SPI2=2, SPI3=3;
output reg[3:0] SPIstate=SPI0;
always @(posedge clk_spi) begin
if (!spen_out) begin // we're in SPI mode
SPIcounter=SPIcounter+1;
case (SPIstate)
SPI0: begin // this is the beginning
if (SPIsend) begin
SPIcounter=0;
outsel_cs_out=1;//start high
div_sclk_out=1;
SPIsendcounter=4'b1111;
SPIstate=SPI1;
end
end
SPI1: begin
if (SPIcounter[2]) begin // start of sending, note that we wait a full tick (was 4)
div_sclk_out=0;
outsel_cs_out=0;//start sending
format_sdin_out=SPIsenddata[SPIsendcounter];//the data
SPIsendcounter=SPIsendcounter-4'b001;//keep track of how many bits we've sent
SPIstate=SPI2;
end
end
SPI2: begin
if (!SPIcounter[2]) begin // sending data on rising edge, note that we wait a full tick
div_sclk_out=1;
if (SPIsendcounter==4'b1111) SPIstate=SPI3; //done
else SPIstate=SPI1;//send next bit
end
end
SPI3: begin
if (SPIcounter[2]) begin // done sending, note that we wait a full tick
outsel_cs_out=1;//back to high
div_sclk_out=0;
SPIstate=SPI0;
end
end
endcase
end // SPI mode
end // clk_spi posedge
reg Threshold1[3:0], Threshold2[3:0];
reg [ram_width:0] Threshold3[3:0];//keep track of the counter time it was above/below threshold for
reg selftrigtemp[3:0];
reg Trigger;
reg AcquiringAndTriggered=0;
reg HaveFullData=0;
integer i;
initial begin
Threshold3[0]=0;
Threshold3[1]=0;
Threshold3[2]=0;
Threshold3[3]=0;
end
reg [ram_width-1:0] samplecount=0;
output reg [ram_width-1:0] wraddress;
output reg Acquiring;
reg PreOrPostAcquiring;
reg [7:0] data_flash1_reg; always @(posedge clk_flash) data_flash1_reg <= data_flash1;
reg [7:0] data_flash2_reg; always @(posedge clk_flash) data_flash2_reg <= data_flash2; // no multiplexing
//reg [7:0] data_flash2_reg; always @(negedge clk_flash) data_flash2_reg <= data_flash1; // for multiplexing
reg [7:0] data_flash3_reg; always @(posedge clk_flash2) data_flash3_reg <= data_flash3;
reg [7:0] data_flash4_reg; always @(posedge clk_flash2) data_flash4_reg <= data_flash4; // no multiplexing
//reg [7:0] data_flash4_reg; always @(negedge clk_flash2) data_flash4_reg <= data_flash3; // for multiplexing
always @(posedge clk_flash) begin
i=0;
while (i<4) begin
if (trigchannels[i]) begin
// above threshold now?
if (i==0) Threshold1[i] <= (data_flash1_reg>=trigthresh && data_flash1_reg<=trigthresh2);
if (i==1) Threshold1[i] <= (data_flash2_reg>=trigthresh && data_flash2_reg<=trigthresh2);
if (i==2) Threshold1[i] <= (data_flash3_reg>=trigthresh && data_flash3_reg<=trigthresh2);
if (i==3) Threshold1[i] <= (data_flash4_reg>=trigthresh && data_flash4_reg<=trigthresh2);
Threshold2[i] <= Threshold1[i]; // was above threshold?
if (triggertype[0]) begin // if positive edge, trigger! (possibly after demanding a timeout)
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;//assume we are not firing
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin // only check every 2^downsample samples
if (downsamplego) begin
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been above threshold
else Threshold3[i] <= 0; // reset once it goes below threshold
end
end
else begin // check every sample
if (Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been above threshold
else Threshold3[i] <= 0; // reset once it goes below threshold
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin //fired!
selftrigtemp[i] = 1;
Threshold3[i] <= 0; // reset once it fires
end
end
else if (Threshold1[i] & ~Threshold2[i]) begin // got a positive edge
Threshold3[i] <= 1; // start counting
end
end
else selftrigtemp[i] <= (Threshold1[i] & ~Threshold2[i]);// got a positive edge, just trigger
end
else begin // if negative edge, trigger! (possibly after demanding a timeout)
if (triggertot[ram_width-1:0]) begin
selftrigtemp[i] = 0;//assume we are not firing
if (Threshold3[i]) begin
if (triggertot[ram_width]) begin // only check every 2^downsample samples
if (downsamplego) begin
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been below threshold
else Threshold3[i] <= 0; // reset once it goes above threshold
end
end
else begin // check every sample
if (~Threshold1[i]) Threshold3[i] <= Threshold3[i]+1; // keep track of how long it's been below threshold
else Threshold3[i] <= 0; // reset once it goes above threshold
end
if (Threshold3[i]>triggertot[ram_width-1:0]) begin //fired!
selftrigtemp[i] = 1;
Threshold3[i] <= 0; // reset once it fires
end
end
else if (~Threshold1[i] & Threshold2[i]) begin // got a negative edge
Threshold3[i] <= 1; // start counting
end
end
else selftrigtemp[i] <= (~Threshold1[i] & Threshold2[i]);// got a negative edge, just trigger
end
end
i=i+1;
end
end
reg[12:0] ext_trig_in_delay_bits=0;
reg ext_trig_in_delayed;
always @(posedge clk_flash) begin
ext_trig_in_delayed <= ext_trig_in_delay_bits[12];
ext_trig_in_delay_bits <= {ext_trig_in_delay_bits[12-1:0], ext_trig_in};
end
reg[31:0] thecounter; // counter for the rolling trigger
always @(posedge clk_flash) if (Trigger) thecounter<=0; else thecounter<=thecounter+1;
wire selftrig; //trigger is an OR of all the channels which are active // also trigger every second or so (rolling)
assign selftrig = (trigchannels[0]&&selftrigtemp[0])||(trigchannels[1]&&selftrigtemp[1])||(trigchannels[2]&&selftrigtemp[2])||(trigchannels[3]&&selftrigtemp[3]) ||(rollingtrigger&thecounter>=25000000) || (use_ext_trig&ext_trig_in_delayed);
always @(posedge clk_flash)
if (imthefirst & imthelast) Trigger = selftrig; // we trigger if we triggered ourselves
else if (imthefirst) Trigger = selftrig||trig_in[1]; // we trigger if we triggered ourselves, or got a trigger in towards the right
else if (imthelast) Trigger = selftrig||trig_in[0]; // we trigger if we triggered ourselves, or got a trigger in towards the left
else Trigger = selftrig||trig_in[0]||trig_in[1]; // we trigger if we triggered ourselves, or got a trigger from the left or right
always @(posedge clk_flash)
if (imthefirst) trig_out[0] = selftrig; // we trigger out to the left if we triggered ourselves
else trig_out[0] = trig_in[0]||selftrig; // we trigger out to the left if we got a trig in towards the left, or we triggered ourselves
always @(posedge clk_flash)
if (imthelast) trig_out[1] = selftrig; // we trigger out to the right if we triggered ourselves
else trig_out[1] = trig_in[1]||selftrig; // we trigger out to the right if we got a trig in towards the right, or we triggered ourselves
reg startAcquisition;//ready to trigger?
always @(posedge clk) begin
if(~startAcquisition) startAcquisition <= startTrigger; // an input to the module
else if(AcquiringAndTriggered2) startAcquisition <= 0;
//assign trigDebug = startAcquisition;
end
reg startAcquisition1; always @(posedge clk_flash) startAcquisition1 <= startAcquisition;
reg startAcquisition2; always @(posedge clk_flash) startAcquisition2 <= startAcquisition1;
localparam INIT=0, PREACQ=1, WAITING=2, POSTACQ=3;
integer state=INIT;
reg [31:0] downsamplecounter;//max downsample is ?
reg [maxhighres:0] highrescounter;//for counting highres
wire downsamplego;
assign downsamplego = downsamplecounter[downsample] || downsample==0; // pay attention to sample when downsamplego is true
always @(posedge clk_flash) begin
case (state)
INIT: begin // this is the beginning... wait for the go-ahead to start acquiring the pre-trigger samples
if (startAcquisition2) begin
samplecount <= 0;
Acquiring <= 1; // start acquiring?
HaveFullData <= 0;
PreOrPostAcquiring <= 1; // preacquiring
downsamplecounter=1;
highrescounter=0;
highres1=0;
highres2=0;
highres3=0;
highres4=0;
state=PREACQ;
end
end
PREACQ: begin // pre-trigger bytes acquired already?
if( (samplecount==triggerpoint) ) begin
PreOrPostAcquiring <= 0;
state=WAITING;
end
end
WAITING: begin
if(Trigger) begin // now we wait for the trigger, and then record the triggerpoint
AcquiringAndTriggered <= 1; // Trigger? Start getting the rest of the bytes
PreOrPostAcquiring <= 1;
wraddress_triggerpoint <= wraddress; // keep track of where the trigger happened
state=POSTACQ;
end
end
POSTACQ: begin
if(samplecount==nsmp) begin // got the rest of the bytes? then stop acquiring
Acquiring <= 0;
AcquiringAndTriggered <= 0;
HaveFullData <= 1;
PreOrPostAcquiring <= 0;
state=INIT;
end
end
endcase
downsamplecounter=downsamplecounter+1;
if (highres && downsample>0) begin // doing highres mode (averaging over samples within each downsample)
highrescounter=highrescounter+1;
highres1=highres1+data_flash1_reg;
highres2=highres2+data_flash2_reg;
highres3=highres3+data_flash3_reg;
highres4=highres4+data_flash4_reg;
if (downsamplego || highrescounter[maxhighres]) begin
highrescounter=0;
if (downsample>maxhighres) begin
dout1=highres1>>maxhighres;
dout2=highres2>>maxhighres;
dout3=highres3>>maxhighres;
dout4=highres4>>maxhighres;
end
else begin
dout1=highres1>>downsample;
dout2=highres2>>downsample;
dout3=highres3>>downsample;
dout4=highres4>>downsample;
end
highres1=0;
highres2=0;
highres3=0;
highres4=0;
end
end
else begin // not highres mode, just copy in the data
dout1=data_flash1_reg;
dout2=data_flash2_reg;
dout3=data_flash3_reg;
dout4=data_flash4_reg;
end
if (downsamplego) begin // increment the write address (store new data) every 1/2^downsample samples
downsamplecounter=1;
if(Acquiring) wraddress <= wraddress + 1;
if(PreOrPostAcquiring) samplecount <= samplecount + 1;
end
end
// go from flash clock to fpga main clock domain
reg AcquiringAndTriggered1; always @(posedge clk) AcquiringAndTriggered1 <= AcquiringAndTriggered;
reg AcquiringAndTriggered2; always @(posedge clk) AcquiringAndTriggered2 <= AcquiringAndTriggered1;
reg HaveFullData1; always @(posedge clk) HaveFullData1 <= HaveFullData;
reg HaveFullData2; always @(posedge clk) HaveFullData2 <= HaveFullData1;
always @(posedge clk) begin
if (startAcquisition) data_ready=0; // waiting for trigger
else if (HaveFullData2) data_ready=1; // ready to read out
end
endmodule |
module uniqueid (
input wire clkin, // clkin.clk
input wire reset, // reset.reset
output wire data_valid, // output.valid
output wire [63:0] chip_id // .data
);
altchip_id #(
.DEVICE_FAMILY ("MAX 10"),
.ID_VALUE (64'b1111111111111111111111111111111111111111111111111111111111111111),
.ID_VALUE_STR ("00000000ffffffff")
) uniqueid_inst (
.clkin (clkin), // clkin.clk
.reset (reset), // reset.reset
.data_valid (data_valid), // output.valid
.chip_id (chip_id) // .data
);
endmodule |
module myadc (
adc_pll_clock_clk,
adc_pll_locked_export,
clock_clk,
command_valid,
command_channel,
command_startofpacket,
command_endofpacket,
command_ready,
reset_sink_reset_n,
response_valid,
response_channel,
response_data,
response_startofpacket,
response_endofpacket);
input adc_pll_clock_clk;
input adc_pll_locked_export;
input clock_clk;
input command_valid;
input [4:0] command_channel;
input command_startofpacket;
input command_endofpacket;
output command_ready;
input reset_sink_reset_n;
output response_valid;
output [4:0] response_channel;
output [11:0] response_data;
output response_startofpacket;
output response_endofpacket;
endmodule |
module myadc (
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire clock_clk, // clock.clk
input wire command_valid, // command.valid
input wire [4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
input wire reset_sink_reset_n, // reset_sink.reset_n
output wire response_valid, // response.valid
output wire [4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
myadc_modular_adc_0 modular_adc_0 (
.clock_clk (clock_clk), // clock.clk
.reset_sink_reset_n (reset_sink_reset_n), // reset_sink.reset_n
.adc_pll_clock_clk (adc_pll_clock_clk), // adc_pll_clock.clk
.adc_pll_locked_export (adc_pll_locked_export), // adc_pll_locked.export
.command_valid (command_valid), // command.valid
.command_channel (command_channel), // .channel
.command_startofpacket (command_startofpacket), // .startofpacket
.command_endofpacket (command_endofpacket), // .endofpacket
.command_ready (command_ready), // .ready
.response_valid (response_valid), // response.valid
.response_channel (response_channel), // .channel
.response_data (response_data), // .data
.response_startofpacket (response_startofpacket), // .startofpacket
.response_endofpacket (response_endofpacket) // .endofpacket
);
endmodule |
module altera_modular_adc_sample_store_ram #(
parameter DATA_WIDTH = 16
) (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [DATA_WIDTH-1:0] data;
input [5:0] rdaddress;
input rden;
input [5:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 64,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule |
module altera_modular_adc_control #(
parameter clkdiv = 1,
parameter tsclkdiv = 0,
parameter tsclksel = 0,
parameter prescalar = 0,
parameter refsel = 0,
parameter device_partname_fivechar_prefix = "10M08",
parameter is_this_first_or_second_adc = 1,
parameter analog_input_pin_mask = 17'h0,
parameter hard_pwd = 0,
parameter dual_adc_mode = 0,
parameter enable_usr_sim = 0,
parameter reference_voltage_sim = 65536,
parameter simfilename_ch0 = "simfilename_ch0",
parameter simfilename_ch1 = "simfilename_ch1",
parameter simfilename_ch2 = "simfilename_ch2",
parameter simfilename_ch3 = "simfilename_ch3",
parameter simfilename_ch4 = "simfilename_ch4",
parameter simfilename_ch5 = "simfilename_ch5",
parameter simfilename_ch6 = "simfilename_ch6",
parameter simfilename_ch7 = "simfilename_ch7",
parameter simfilename_ch8 = "simfilename_ch8",
parameter simfilename_ch9 = "simfilename_ch9",
parameter simfilename_ch10 = "simfilename_ch10",
parameter simfilename_ch11 = "simfilename_ch11",
parameter simfilename_ch12 = "simfilename_ch12",
parameter simfilename_ch13 = "simfilename_ch13",
parameter simfilename_ch14 = "simfilename_ch14",
parameter simfilename_ch15 = "simfilename_ch15",
parameter simfilename_ch16 = "simfilename_ch16"
) (
input clk,
input rst_n,
input clk_in_pll_c0,
input clk_in_pll_locked,
input cmd_valid,
input [4:0] cmd_channel,
input cmd_sop,
input cmd_eop,
input sync_ready,
output cmd_ready,
output rsp_valid,
output [4:0] rsp_channel,
output [11:0] rsp_data,
output rsp_sop,
output rsp_eop,
output sync_valid
);
wire clkout_adccore;
wire eoc;
wire [11:0] dout;
wire [4:0] chsel;
wire soc;
wire tsen;
wire usr_pwd;
altera_modular_adc_control_fsm #(
.is_this_first_or_second_adc (is_this_first_or_second_adc),
.dual_adc_mode (dual_adc_mode)
) u_control_fsm (
// inputs
.clk (clk),
.rst_n (rst_n),
.clk_in_pll_locked (clk_in_pll_locked),
.cmd_valid (cmd_valid),
.cmd_channel (cmd_channel),
.cmd_sop (cmd_sop),
.cmd_eop (cmd_eop),
.clk_dft (clkout_adccore),
.eoc (eoc),
.dout (dout),
.sync_ready (sync_ready),
// outputs
.rsp_valid (rsp_valid),
.rsp_channel (rsp_channel),
.rsp_data (rsp_data),
.rsp_sop (rsp_sop),
.rsp_eop (rsp_eop),
.cmd_ready (cmd_ready),
.chsel (chsel),
.soc (soc),
.usr_pwd (usr_pwd),
.tsen (tsen),
.sync_valid (sync_valid)
);
fiftyfivenm_adcblock_top_wrapper #(
.device_partname_fivechar_prefix (device_partname_fivechar_prefix),
.clkdiv (clkdiv),
.tsclkdiv (tsclkdiv),
.tsclksel (tsclksel),
.refsel (refsel),
.prescalar (prescalar),
.is_this_first_or_second_adc (is_this_first_or_second_adc),
.analog_input_pin_mask (analog_input_pin_mask),
.hard_pwd (hard_pwd),
.enable_usr_sim (enable_usr_sim),
.reference_voltage_sim (reference_voltage_sim),
.simfilename_ch0 (simfilename_ch0),
.simfilename_ch1 (simfilename_ch1),
.simfilename_ch2 (simfilename_ch2),
.simfilename_ch3 (simfilename_ch3),
.simfilename_ch4 (simfilename_ch4),
.simfilename_ch5 (simfilename_ch5),
.simfilename_ch6 (simfilename_ch6),
.simfilename_ch7 (simfilename_ch7),
.simfilename_ch8 (simfilename_ch8),
.simfilename_ch9 (simfilename_ch9),
.simfilename_ch10 (simfilename_ch10),
.simfilename_ch11 (simfilename_ch11),
.simfilename_ch12 (simfilename_ch12),
.simfilename_ch13 (simfilename_ch13),
.simfilename_ch14 (simfilename_ch14),
.simfilename_ch15 (simfilename_ch15),
.simfilename_ch16 (simfilename_ch16)
) adc_inst (
//.reset (reset),
.chsel (chsel), // 5-bits channel selection.
.soc (soc), // signal Start-of-Conversion to ADC
.eoc (eoc), // signal end of conversion. Data can be latched on the positive edge of clkout_adccore after this signal becomes high. EOC becomes low at every positive edge of the clkout_adccore signal.
.dout (dout), // 12-bits DOUT valid after EOC rise, still valid at falling edge, but not before the next EOC rising edge
.usr_pwd (usr_pwd), // User Power Down during run time. 0 = Power Up; 1 = Power Down.
.tsen (tsen), // MUST power down ADC before changing TSEN. 0 = Normal Mode; 1 = Temperature Sensing Mode.
.clkout_adccore (clkout_adccore), // Output clock from the clock divider
.clkin_from_pll_c0 (clk_in_pll_c0) // Clock source from PLL1/3 c-counter[0]
//.dout_ch (dout_ch) // Indicate dout is for which chsel
);
endmodule |
module altera_modular_adc_sample_store #(
parameter DUAL_ADC_MODE = 0,
parameter RSP_DATA_WIDTH = 12
) (
input clk,
input rst_n,
input [6:0] addr,
input read,
input write,
input [31:0] writedata,
input rsp_valid,
input [4:0] rsp_channel,
input [RSP_DATA_WIDTH-1:0] rsp_data,
input rsp_sop,
input rsp_eop,
output reg [31:0] readdata,
output reg irq
);
localparam RAM_DATA_WIDTH = (DUAL_ADC_MODE == 1) ? 32 : 16;
reg e_eop;
reg s_eop;
reg [31:0] csr_readdata;
reg ram_rd_en_flp;
reg [5:0] slot_num;
wire ier_addr;
wire isr_addr;
wire ram_addr;
wire ier_wr_en;
wire isr_wr_en;
wire ier_rd_en;
wire isr_rd_en;
wire ram_rd_en;
wire set_eop;
wire [31:0] csr_readdata_nxt;
wire [31:0] ier_internal;
wire [31:0] isr_internal;
wire [31:0] readdata_nxt;
wire [RAM_DATA_WIDTH-1:0] q_out;
wire irq_nxt;
wire [RAM_DATA_WIDTH-1:0] ram_datain;
wire [RAM_DATA_WIDTH-1:0] ram_readdata;
//--------------------------------------------------------------------------------------------//
// address decode
//--------------------------------------------------------------------------------------------//
assign ier_addr = (addr == 7'h40);
assign isr_addr = (addr == 7'h41);
assign ram_addr = (addr < 7'h40);
//--------------------------------------------------------------------------------------------//
// write enable
//--------------------------------------------------------------------------------------------//
assign ier_wr_en = ier_addr & write;
assign isr_wr_en = isr_addr & write;
//--------------------------------------------------------------------------------------------//
// read enable
//--------------------------------------------------------------------------------------------//
assign ier_rd_en = ier_addr & read;
assign isr_rd_en = isr_addr & read;
assign ram_rd_en = ram_addr & read;
//--------------------------------------------------------------------------------------------//
// interrupt enable register
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
e_eop <= 1'b1;
else if (ier_wr_en)
e_eop <= writedata[0];
end
//--------------------------------------------------------------------------------------------//
// interrupt status register
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
s_eop <= 1'b0;
else if (set_eop)
s_eop <= 1'b1;
else if (isr_wr_en & writedata[0])
s_eop <= 1'b0;
end
//--------------------------------------------------------------------------------------------//
// Avalon slave readdata path - read latency of 2 due to RAM's address and dataout register
//--------------------------------------------------------------------------------------------//
assign ier_internal = {31'h0, e_eop};
assign isr_internal = {31'h0, s_eop};
assign csr_readdata_nxt = (ier_internal & {32{ier_rd_en}}) |
(isr_internal & {32{isr_rd_en}});
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
csr_readdata <= 32'h0;
else
csr_readdata <= csr_readdata_nxt;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
ram_rd_en_flp <= 1'b0;
else
ram_rd_en_flp <= ram_rd_en;
end
assign readdata_nxt = ram_rd_en_flp ? ram_readdata : csr_readdata;
assign ram_readdata = q_out[RAM_DATA_WIDTH-1:0];
generate
if (DUAL_ADC_MODE) begin
assign ram_datain = {4'h0, rsp_data[23:12], 4'h0, rsp_data[11:0]};
end
else begin
assign ram_datain = {4'h0, rsp_data};
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
readdata <= 32'h0;
else
readdata <= readdata_nxt;
end
//--------------------------------------------------------------------------------------------//
// RAM to store ADC sample
//--------------------------------------------------------------------------------------------//
altera_modular_adc_sample_store_ram #(
.DATA_WIDTH (RAM_DATA_WIDTH)
) u_ss_ram (
.clock (clk),
.data (ram_datain),
.rdaddress (addr[5:0]),
.rden (ram_rd_en),
.wraddress (slot_num),
.wren (rsp_valid),
.q (q_out)
);
//assign ram_datain = (DUAL_ADC_MODE == 1) ? ({8'h0, rsp_data}) : ({4'h0, rsp_data});
//--------------------------------------------------------------------------------------------//
// Sequential counter to indicate which RAM location to store ADC sample
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
slot_num <= 6'h0;
else if (set_eop)
slot_num <= 6'h0;
else if (rsp_valid)
slot_num <= slot_num + 6'h1;
end
//--------------------------------------------------------------------------------------------//
// Set EOP status
//--------------------------------------------------------------------------------------------//
assign set_eop = rsp_valid & rsp_eop;
//--------------------------------------------------------------------------------------------//
// IRQ
//--------------------------------------------------------------------------------------------//
assign irq_nxt = e_eop & s_eop;
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
irq <= 1'b0;
else
irq <= irq_nxt;
end
endmodule |
module altera_modular_adc_sequencer_ctrl #(
parameter CSD_LENGTH = 64,
parameter CSD_ASIZE = 6,
parameter CSD_SLOT_0 = 5'h0,
parameter CSD_SLOT_1 = 5'h0,
parameter CSD_SLOT_2 = 5'h0,
parameter CSD_SLOT_3 = 5'h0,
parameter CSD_SLOT_4 = 5'h0,
parameter CSD_SLOT_5 = 5'h0,
parameter CSD_SLOT_6 = 5'h0,
parameter CSD_SLOT_7 = 5'h0,
parameter CSD_SLOT_8 = 5'h0,
parameter CSD_SLOT_9 = 5'h0,
parameter CSD_SLOT_10 = 5'h0,
parameter CSD_SLOT_11 = 5'h0,
parameter CSD_SLOT_12 = 5'h0,
parameter CSD_SLOT_13 = 5'h0,
parameter CSD_SLOT_14 = 5'h0,
parameter CSD_SLOT_15 = 5'h0,
parameter CSD_SLOT_16 = 5'h0,
parameter CSD_SLOT_17 = 5'h0,
parameter CSD_SLOT_18 = 5'h0,
parameter CSD_SLOT_19 = 5'h0,
parameter CSD_SLOT_20 = 5'h0,
parameter CSD_SLOT_21 = 5'h0,
parameter CSD_SLOT_22 = 5'h0,
parameter CSD_SLOT_23 = 5'h0,
parameter CSD_SLOT_24 = 5'h0,
parameter CSD_SLOT_25 = 5'h0,
parameter CSD_SLOT_26 = 5'h0,
parameter CSD_SLOT_27 = 5'h0,
parameter CSD_SLOT_28 = 5'h0,
parameter CSD_SLOT_29 = 5'h0,
parameter CSD_SLOT_30 = 5'h0,
parameter CSD_SLOT_31 = 5'h0,
parameter CSD_SLOT_32 = 5'h0,
parameter CSD_SLOT_33 = 5'h0,
parameter CSD_SLOT_34 = 5'h0,
parameter CSD_SLOT_35 = 5'h0,
parameter CSD_SLOT_36 = 5'h0,
parameter CSD_SLOT_37 = 5'h0,
parameter CSD_SLOT_38 = 5'h0,
parameter CSD_SLOT_39 = 5'h0,
parameter CSD_SLOT_40 = 5'h0,
parameter CSD_SLOT_41 = 5'h0,
parameter CSD_SLOT_42 = 5'h0,
parameter CSD_SLOT_43 = 5'h0,
parameter CSD_SLOT_44 = 5'h0,
parameter CSD_SLOT_45 = 5'h0,
parameter CSD_SLOT_46 = 5'h0,
parameter CSD_SLOT_47 = 5'h0,
parameter CSD_SLOT_48 = 5'h0,
parameter CSD_SLOT_49 = 5'h0,
parameter CSD_SLOT_50 = 5'h0,
parameter CSD_SLOT_51 = 5'h0,
parameter CSD_SLOT_52 = 5'h0,
parameter CSD_SLOT_53 = 5'h0,
parameter CSD_SLOT_54 = 5'h0,
parameter CSD_SLOT_55 = 5'h0,
parameter CSD_SLOT_56 = 5'h0,
parameter CSD_SLOT_57 = 5'h0,
parameter CSD_SLOT_58 = 5'h0,
parameter CSD_SLOT_59 = 5'h0,
parameter CSD_SLOT_60 = 5'h0,
parameter CSD_SLOT_61 = 5'h0,
parameter CSD_SLOT_62 = 5'h0,
parameter CSD_SLOT_63 = 5'h0
) (
input clk,
input rst_n,
input run,
input sw_clr_run,
input con_mode,
input single_mode,
input recab_mode,
input cmd_ready,
output reg cmd_valid,
output reg [4:0] cmd_channel,
output reg cmd_sop,
output reg cmd_eop,
output reg clr_run
);
reg seq_state;
reg seq_state_nxt;
reg [CSD_ASIZE-1:0] slot_sel;
reg [CSD_ASIZE-1:0] slot_sel_nxt;
reg valid_req;
wire [4:0] csd[0:63];
wire [4:0] csdmem[0:CSD_LENGTH-1];
wire last_slot;
wire done;
wire done_con;
wire done_single;
wire valid_mode;
wire [4:0] cmd_channel_nxt;
wire cmd_sop_nxt;
wire cmd_eop_nxt;
localparam IDLE = 1'b0;
localparam READY = 1'b1;
//--------------------------------------------------------------------------------------------//
// Assign conversion sequence data parameter into a temporary array
//--------------------------------------------------------------------------------------------//
assign csd[0] = CSD_SLOT_0;
assign csd[1] = CSD_SLOT_1;
assign csd[2] = CSD_SLOT_2;
assign csd[3] = CSD_SLOT_3;
assign csd[4] = CSD_SLOT_4;
assign csd[5] = CSD_SLOT_5;
assign csd[6] = CSD_SLOT_6;
assign csd[7] = CSD_SLOT_7;
assign csd[8] = CSD_SLOT_8;
assign csd[9] = CSD_SLOT_9;
assign csd[10] = CSD_SLOT_10;
assign csd[11] = CSD_SLOT_11;
assign csd[12] = CSD_SLOT_12;
assign csd[13] = CSD_SLOT_13;
assign csd[14] = CSD_SLOT_14;
assign csd[15] = CSD_SLOT_15;
assign csd[16] = CSD_SLOT_16;
assign csd[17] = CSD_SLOT_17;
assign csd[18] = CSD_SLOT_18;
assign csd[19] = CSD_SLOT_19;
assign csd[20] = CSD_SLOT_20;
assign csd[21] = CSD_SLOT_21;
assign csd[22] = CSD_SLOT_22;
assign csd[23] = CSD_SLOT_23;
assign csd[24] = CSD_SLOT_24;
assign csd[25] = CSD_SLOT_25;
assign csd[26] = CSD_SLOT_26;
assign csd[27] = CSD_SLOT_27;
assign csd[28] = CSD_SLOT_28;
assign csd[29] = CSD_SLOT_29;
assign csd[30] = CSD_SLOT_30;
assign csd[31] = CSD_SLOT_31;
assign csd[32] = CSD_SLOT_32;
assign csd[33] = CSD_SLOT_33;
assign csd[34] = CSD_SLOT_34;
assign csd[35] = CSD_SLOT_35;
assign csd[36] = CSD_SLOT_36;
assign csd[37] = CSD_SLOT_37;
assign csd[38] = CSD_SLOT_38;
assign csd[39] = CSD_SLOT_39;
assign csd[40] = CSD_SLOT_40;
assign csd[41] = CSD_SLOT_41;
assign csd[42] = CSD_SLOT_42;
assign csd[43] = CSD_SLOT_43;
assign csd[44] = CSD_SLOT_44;
assign csd[45] = CSD_SLOT_45;
assign csd[46] = CSD_SLOT_46;
assign csd[47] = CSD_SLOT_47;
assign csd[48] = CSD_SLOT_48;
assign csd[49] = CSD_SLOT_49;
assign csd[50] = CSD_SLOT_50;
assign csd[51] = CSD_SLOT_51;
assign csd[52] = CSD_SLOT_52;
assign csd[53] = CSD_SLOT_53;
assign csd[54] = CSD_SLOT_54;
assign csd[55] = CSD_SLOT_55;
assign csd[56] = CSD_SLOT_56;
assign csd[57] = CSD_SLOT_57;
assign csd[58] = CSD_SLOT_58;
assign csd[59] = CSD_SLOT_59;
assign csd[60] = CSD_SLOT_60;
assign csd[61] = CSD_SLOT_61;
assign csd[62] = CSD_SLOT_62;
assign csd[63] = CSD_SLOT_63;
//--------------------------------------------------------------------------------------------//
// Assign valid conversion sequence data parameter into an array
//--------------------------------------------------------------------------------------------//
genvar i;
generate
for (i=0; i<CSD_LENGTH; i=i+1) begin : assign_csdmem
assign csdmem[i] = csd[i];
end
endgenerate
//--------------------------------------------------------------------------------------------//
// Sequncer FSM
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
seq_state <= IDLE;
else
seq_state <= seq_state_nxt;
end
always @* begin
case (seq_state)
IDLE: begin
clr_run = 1'b0;
slot_sel_nxt = {CSD_ASIZE{1'b0}};
if (run & valid_mode) begin
seq_state_nxt = READY;
valid_req = 1'b1;
end
else begin
seq_state_nxt = IDLE;
valid_req = 1'b0;
end
end
READY: begin
if (cmd_ready & (recab_mode | done)) begin
seq_state_nxt = IDLE;
valid_req = 1'b0;
slot_sel_nxt = {CSD_ASIZE{1'b0}};
clr_run = 1'b1;
end
else if (cmd_ready) begin
seq_state_nxt = READY;
valid_req = 1'b1;
clr_run = 1'b0;
if (last_slot)
slot_sel_nxt = {CSD_ASIZE{1'b0}};
else
slot_sel_nxt = slot_sel + {{(CSD_ASIZE-1){1'b0}}, 1'b1};
end
else begin
seq_state_nxt = READY;
valid_req = 1'b0;
slot_sel_nxt = slot_sel;
clr_run = 1'b0;
end
end
default: begin
seq_state_nxt = IDLE;
valid_req = 1'b0;
slot_sel_nxt = {CSD_ASIZE{1'b0}};
clr_run = 1'b0;
end
endcase
end
//--------------------------------------------------------------------------------------------//
// Counter for slot selector
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
slot_sel <= {CSD_ASIZE{1'b0}};
else
slot_sel <= slot_sel_nxt;
end
//--------------------------------------------------------------------------------------------//
// Misc logic to detect sequence complete
//--------------------------------------------------------------------------------------------//
assign last_slot = (slot_sel == (CSD_LENGTH-1));
assign done_single = single_mode & last_slot;
assign done_con = last_slot & sw_clr_run;
assign done = done_con | done_single;
assign valid_mode = con_mode | single_mode | recab_mode;
assign cmd_channel_nxt = recab_mode ? 5'h1f : csdmem[slot_sel_nxt];
assign cmd_sop_nxt = recab_mode ? 1'b1 : (slot_sel_nxt == {CSD_ASIZE{1'b0}});
assign cmd_eop_nxt = recab_mode ? 1'b1 : (slot_sel_nxt == (CSD_LENGTH-1));
//--------------------------------------------------------------------------------------------//
// Output register for Avalon ST Command Interface
//--------------------------------------------------------------------------------------------//
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cmd_valid <= 1'b0;
cmd_channel <= 5'h0;
cmd_sop <= 1'b0;
cmd_eop <= 1'b0;
end
else if (valid_req) begin
cmd_valid <= 1'b1;
cmd_channel <= cmd_channel_nxt;
cmd_sop <= cmd_sop_nxt;
cmd_eop <= cmd_eop_nxt;
end
else if (cmd_ready) begin
cmd_valid <= 1'b0;
cmd_channel <= 5'h0;
cmd_sop <= 1'b0;
cmd_eop <= 1'b0;
end
end
endmodule |
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