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module jeff_74x181(
input a0, // WORD 1
input a1, //
input a2, //
input a3, //
input b0, // WORD 2
input b1, //
input b2, //
input b3, //
input s0, // FUNCTION SELECT
input s1, //
input s2, //
input s3, //
input m, // MODE: 0 is arithmetic, 1 is logic
input ci_bar, // CARRY IN
output f0, // OUTPUT
output f1, //
output f2, //
output f3, //
output co_bar, // CARRY OUT
output aeqb, // WHEN A = B
output x, // ALSO PROPAGATE
output y // ALSO GENERATE
);
// I DESIGNED THIS FRO THE 1972 TI SPEC SHEET
wire input3_out1, input3_out2;
wire input2_out1, input2_out2;
wire input1_out1, input1_out2;
wire input0_out1, input0_out2;
wire m_bar;
input_section INPUT3(
.a(a3),
.b(b3),
.s3(s3),
.s2(s2),
.s1(s1),
.s0(s0),
.out1(input3_out1),
.out2(input3_out2)
);
input_section INPUT2(
.a(a2),
.b(b2),
.s3(s3),
.s2(s2),
.s1(s1),
.s0(s0),
.out1(input2_out1),
.out2(input2_out2)
);
input_section INPUT1(
.a(a1),
.b(b1),
.s3(s3),
.s2(s2),
.s1(s1),
.s0(s0),
.out1(input1_out1),
.out2(input1_out2)
);
input_section INPUT0(
.a(a0),
.b(b0),
.s3(s3),
.s2(s2),
.s1(s1),
.s0(s0),
.out1(input0_out1),
.out2(input0_out2)
);
invert_m M_BAR(
.a(m),
.y(m_bar)
);
out_section_f3 OUT_F3(
.m_bar(m_bar),
.ci_bar(ci_bar),
.input3_out1(input3_out1),
.input3_out2(input3_out2),
.input2_out1(input2_out1),
.input2_out2(input2_out2),
.input1_out1(input1_out1),
.input1_out2(input1_out2),
.input0_out1(input0_out1),
.input0_out2(input0_out2),
.f3(f3)
);
out_section_f2 OUT_F2(
.m_bar(m_bar),
.ci_bar(ci_bar),
.input2_out1(input2_out1),
.input2_out2(input2_out2),
.input1_out1(input1_out1),
.input1_out2(input1_out2),
.input0_out1(input0_out1),
.input0_out2(input0_out2),
.f2(f2)
);
out_section_f1 OUT_F1(
.m_bar(m_bar),
.ci_bar(ci_bar),
.input1_out1(input1_out1),
.input1_out2(input1_out2),
.input0_out1(input0_out1),
.input0_out2(input0_out2),
.f1(f1)
);
out_section_f0 OUT_F0(
.m_bar(m_bar),
.ci_bar(ci_bar),
.input0_out1(input0_out1),
.input0_out2(input0_out2),
.f0(f0)
);
g_p_carry_section GPC (
.input3_out1(input3_out1),
.input3_out2(input3_out2),
.input2_out1(input2_out1),
.input2_out2(input2_out2),
.input1_out1(input1_out1),
.input1_out2(input1_out2),
.input0_out1(input0_out1),
.input0_out2(input0_out2),
.ci_bar(ci_bar),
.co_bar(co_bar),
.x(x),
.y(y)
);
aeqb AEQB (
.f3(f3),
.f2(f2),
.f1(f1),
.f0(f0),
.aeqb(aeqb)
);
endmodule |
module JEFF_74x181_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [3:0] A, B, S;
reg M, CI_BAR;
wire [3:0] F;
wire CO_BAR, AEQB, X, Y;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [3:0] FEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (dataflow)
jeff_74x181 UUT_jeff_74x181(
.a3(A[3]), .a2(A[2]), .a1(A[1]), .a0(A[0]),
.b3(B[3]), .b2(B[2]), .b1(B[1]), .b0(B[0]),
.s3(S[3]), .s2(S[2]), .s1(S[1]), .s0(S[0]),
.m(M), .ci_bar(CI_BAR),
.f3(F[3]), .f2(F[2]), .f1(F[1]), .f0(F[0]),
.co_bar(CO_BAR), .aeqb(AEQB), .x(X), .y(Y)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jeff_74x181_tb.vcd");
$dumpvars(0, JEFF_74x181_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jeff_74x181_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %4b %4b %4b %4b", COMMENT, M, CI_BAR, S, A, B, FEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | M | CI_BAR | S | A | B | F |");
$display(" -----------------------------------------------------");
// $monitor("%4d %16s | %8d | %1b | %1b | %4b | %4b | %4b | %4b |", VECTORCOUNT, COMMENT, $time, M, CI_BAR, S, A, B, F);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %4b %4b %4b %4b", COMMENT, M, CI_BAR, S, A, B, FEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %16s | %8d | %1b | %1b | %4b | %4b | %4b | %4b |", VECTORCOUNT, COMMENT, $time, M, CI_BAR, S, A, B, F);
// CHECK EACH VECTOR RESULT
if (F !== FEXPECTED) begin
$display("***ERROR (gate) - Expected F = %b", FEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module out_section_f2 (
input m_bar,
input ci_bar,
input input2_out1,
input input2_out2,
input input1_out1,
input input1_out2,
input input0_out1,
input input0_out2,
output f2);
assign f2 = ((input2_out1 ^ input2_out2) ^ ~((ci_bar & input0_out1 & input1_out1 & m_bar) | (input1_out1 & input0_out2 & m_bar) | (input1_out2 & m_bar)));
endmodule |
module aeqb (
input f3,
input f2,
input f1,
input f0,
output aeqb);
assign aeqb = (f3 & f2 & f1 & f0);
endmodule |
module input_section (
input a,
input b,
input s3,
input s2,
input s1,
input s0,
output out1,
output out2);
assign out1 = ~((b & s3 & a) | (a & s2 & ~b));
assign out2 = ~((~b & s1) | (s0 & b) | (a));
endmodule |
module invert_m (
input a,
output y);
assign y = ~a;
endmodule |
module out_section_f1 (
input m_bar,
input ci_bar,
input input1_out1,
input input1_out2,
input input0_out1,
input input0_out2,
output f1);
assign f1 = ((input1_out1 ^ input1_out2) ^ ~((ci_bar & input0_out1 & m_bar) | (input0_out2 & m_bar)));
endmodule |
module out_section_f3 (
input m_bar,
input ci_bar,
input input3_out1,
input input3_out2,
input input2_out1,
input input2_out2,
input input1_out1,
input input1_out2,
input input0_out1,
input input0_out2,
output f3);
assign f3 = ((input3_out1 ^ input3_out2) ^ ~((ci_bar & input0_out1 & input1_out1 & input2_out1 & m_bar) | (input1_out1 & input2_out1 & input0_out2 & m_bar) | (input2_out1 & input1_out2 & m_bar) | (input2_out2 & m_bar)));
endmodule |
module g_p_carry_section (
input input3_out1,
input input3_out2,
input input2_out1,
input input2_out2,
input input1_out1,
input input1_out2,
input input0_out1,
input input0_out2,
input ci_bar,
output co_bar,
output x,
output y);
assign y = ~((input3_out2) | (input3_out1 & input2_out2) | (input3_out1 & input2_out1 & input1_out2) | (input3_out1 & input2_out1 & input1_out1 & input0_out2));
assign co_bar = (~y | (input3_out1 & input2_out1 & input1_out1 & input0_out1 & ci_bar));
assign x = ~(input3_out1 & input2_out1 & input1_out1 & input0_out1);
endmodule |
module out_section_f0 (
input m_bar,
input ci_bar,
input input0_out1,
input input0_out2,
output f0);
assign f0 = ((input0_out1 ^ input0_out2) ^ ~(ci_bar & m_bar));
endmodule |
module encoder_8_3_behavioral(
input [7:0] in, // 8 Inputs
output reg [2:0] out); // 3 Outputs
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
case(in)
8'b00000001 : out <= 3'b000;
8'b00000010 : out <= 3'b001;
8'b00000100 : out <= 3'b010;
8'b00001000 : out <= 3'b011;
8'b00010000 : out <= 3'b100;
8'b00100000 : out <= 3'b101;
8'b01000000 : out <= 3'b110;
8'b10000000 : out <= 3'b111;
default : out <= 3'b000;
endcase
end
endmodule |
module ENCODER_8_3_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] IN;
wire [2:0] OUT;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg [2:0] OUTEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
encoder_8_3_behavioral UUT_encoder_8_3_behavioral(
.in(IN),
.out(OUT)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("encoder_8_3_tb.vcd");
$dumpvars(0, ENCODER_8_3_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("encoder_8_3_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b", COMMENT, IN, OUTEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | IN | OUT |");
$display(" -----------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b |", VECTORCOUNT, COMMENT, $time, IN, OUT);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, IN, OUTEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1b | %1b |", VECTORCOUNT, COMMENT, $time, IN, OUT);
// CHECK EACH VECTOR RESULT
if (OUT !== OUTEXPECTED) begin
$display("***ERROR (behavioral) - Expected OUT = %b", OUTEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module decoder_3_8_behavioral(
input [2:0] in, // 3 Input
output reg [7:0] out); // 8 Outputs
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( * ) begin
case (in)
3'b000 : out <= 8'b00000001;
3'b001 : out <= 8'b00000010;
3'b010 : out <= 8'b00000100;
3'b011 : out <= 8'b00001000;
3'b100 : out <= 8'b00010000;
3'b101 : out <= 8'b00100000;
3'b110 : out <= 8'b01000000;
3'b111 : out <= 8'b10000000;
endcase
end
endmodule |
module encoder_to_decoder_structural(
input [7:0] in, // 8 Inputs
output [7:0] out // 8 Outputs
);
wire [7:0] connect;
// ENCODER
encoder_8_3_behavioral encoder_8_3 (
.in(in),
.out(connect)
);
// DECODER
decoder_3_8_behavioral decoder_3_8 (
.in(connect),
.out(out)
);
endmodule |
module FULL_ADDER_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg A, B;
reg CIN;
wire SUM_gate, SUM_data, SUM_beh;
wire COUT_gate, COUT_data, COUT_beh;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg COUTEXPECTED, SUMEXPECTED;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (gate)
full_adder_gate UUT_full_adder_gate(
.a(A), .b(B),
.cin(CIN),
.sum(SUM_gate),
.cout(COUT_gate)
);
// UNIT UNDER TEST (dataflow)
full_adder_dataflow UUT_full_adder_dataflow(
.a(A), .b(B),
.cin(CIN),
.sum(SUM_data),
.cout(COUT_data)
);
// UNIT UNDER TEST (behavioral)
full_adder_behavioral UUT_full_adder_behavioral(
.a(A), .b(B),
.cin(CIN),
.sum(SUM_beh),
.cout(COUT_beh)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("full_adder_tb.vcd");
$dumpvars(0, FULL_ADDER_TB);
end
// TICK PERIOD
localparam TICKPERIOD = 20;
// TICK
always begin
#(TICKPERIOD/2) TICK = ~TICK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("full_adder_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, CIN, SUMEXPECTED, COUTEXPECTED);
TICK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" GATE ----- DATA ----- BEH ------");
$display(" | TIME(ns) | A | B | CIN | SUM | COUT | SUM | COUT | SUM | COUT |");
$display(" -----------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, CIN, SUM_gate, COUT_gate, SUM_data, COUT_data, SUM_beh, SUM_beh);
end
// APPLY TEST VECTORS ON NEG EDGE TICK (ADD DELAY)
always @(negedge TICK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, CIN, SUMEXPECTED, COUTEXPECTED);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE TICK
always @(posedge TICK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE TICK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, A, B, CIN, SUM_gate, COUT_gate, SUM_data, COUT_data, SUM_beh, SUM_beh);
// CHECK EACH VECTOR RESULT
if ((SUM_gate !== SUMEXPECTED) | (COUT_gate !== COUTEXPECTED)) begin
$display("***ERROR (gate) - Expected SUM=%b COUT=%b", SUMEXPECTED, COUTEXPECTED);
ERRORS = ERRORS + 1;
end
if ((SUM_data !== SUMEXPECTED) | (COUT_data !== COUTEXPECTED)) begin
$display("***ERROR (dataflow) - Expected SUM=%b COUT=%b", SUMEXPECTED, COUTEXPECTED);
ERRORS = ERRORS + 1;
end
if ((SUM_beh !== SUMEXPECTED) | (COUT_beh !== COUTEXPECTED)) begin
$display("***ERROR (behavioral) - Expected SUM=%b COUT=%b", SUMEXPECTED, COUTEXPECTED);
ERRORS = ERRORS + 1;
end
end
endmodule |
module full_adder_gate(
input a, // Data
input b, // Data
input cin, // Carry in
output sum, // Sum of a + b
output cout); // Carry out
wire w1, w2, w3;
// GATE PRIMITIVE
xor xor1(w1, a, b);
xor xor2(sum, w1, cin);
and and1(w2, w1, cin);
and and2(w3, a, b);
or or1(cout, w2, w3);
endmodule |
module full_adder_dataflow(
input a, // Data
input b, // Data
input cin, // Carry in
output sum, // Sum of a + b
output cout); // Carry out
// CONTINUOUS ASSIGNMENT STATEMENT
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule |
module full_adder_behavioral(
input a, // Data
input b, // Data
input cin, // Carry in
output reg sum, // Sum of a + b
output reg cout); // Carry out
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ ( a or b or cin) begin
{cout, sum} <= a + b + cin;
end
endmodule |
module half_adder_gate(
input a, // Data
input b, // Data
output sum, // Sum of a + b
output cout); // Carry out
// GATE PRIMITIVE
xor xor1(sum, a, b);
and and1(cout, a, b);
endmodule |
module half_adder_dataflow(
input a, // Data
input b, // Data
output sum, // Sum of a + b
output cout); // Carry out
// CONTINUOUS ASSIGNMENT STATEMENT
assign sum = a ^ b;
assign cout = a & b;
endmodule |
module MOORE_STATE_MACHINE_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg RST;
reg CLK;
reg IN;
wire FOUND;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg FOUNDEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
moore_state_machine_behavioral UUT_moore_state_machine_behavioral(
.rst(RST),
.clk(CLK),
.in(IN),
.found(FOUND)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("moore_state_machine_tb.vcd");
$dumpvars(0, MOORE_STATE_MACHINE_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("moore_state_machine_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, IN, FOUNDEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | RST | IN | FOUND |");
$display(" -------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, RST, IN, FOUND);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, IN, FOUNDEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, RST, IN, FOUND);
// CHECK EACH VECTOR RESULT
if (FOUNDEXP !== FOUND) begin
$display("***ERROR (behavioral) - Expected FOUND=%b", FOUNDEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module moore_state_machine_behavioral (
input clk, // clk
input rst, // Reset
input in, // Serial in
output reg found); // Found pattern
// DATA TYPES
reg [2:0] state;
// STATES - BINARY ENCODED STYLE - USE ANY STYLE YOU WANT
parameter [2:0] START = 3'b000;
parameter [2:0] ZERO = 3'b001;
parameter [2:0] WAIT = 3'b010;
parameter [2:0] S1 = 3'b011;
parameter [2:0] S2 = 3'b100;
parameter [2:0] S3 = 3'b101;
parameter [2:0] FOUND = 3'b110;
// MOORE STATE MACHINE
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (rst) begin
state <= START;
found <= 1'b0;
end else begin
case (state)
START: begin
found <= 1'b0;
if (in==0) begin state <= ZERO; end
else begin state <= START; end
end
ZERO: begin
found <= 1'b0;
if (in==0) begin state <= WAIT; end
else begin state <= START; end
end
WAIT: begin
found <= 1'b0;
if (in==1) begin state <= S1; end
else begin state <= WAIT; end
end
S1: begin
found <= 1'b0;
if (in==1) begin state <= S2; end
else begin state <= ZERO; end
end
S2:begin
found <= 1'b0;
if (in==0) begin state <= S3; end
else begin state <= START; end
end
S3:begin
found <= 1'b0;
if (in==1) begin state <= FOUND; end // Found pattern
else begin state <= WAIT; end
end
FOUND:begin
found <= 1'b1;
if (in==1) begin state <= START; end
else begin state <= ZERO; end
end
endcase
end
end
endmodule |
module MEALY_STATE_MACHINE_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg RST;
reg CLK;
reg IN;
wire FOUND;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg FOUNDEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
mealy_state_machine_behavioral UUT_mealy_state_machine_behavioral(
.rst(RST),
.clk(CLK),
.in(IN),
.found(FOUND)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("mealy_state_machine_tb.vcd");
$dumpvars(0, MEALY_STATE_MACHINE_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("mealy_state_machine_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, IN, FOUNDEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | RST | IN | FOUND |");
$display(" -------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, RST, IN, FOUND);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, IN, FOUNDEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, RST, IN, FOUND);
// CHECK EACH VECTOR RESULT
if (FOUNDEXP !== FOUND) begin
$display("***ERROR (behavioral) - Expected FOUND=%b", FOUNDEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module priority_arbiter_behavioral(
input clk, // Clock
input rst, // Reset
input req_0, // Request 0
input req_1, // Request 1
input req_2, // Request 2
output reg gnt_0, // Grant 0
output reg gnt_1, // Grant 1
output reg gnt_2 // Grant 2
);
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk or posedge rst) begin
if (rst) begin
gnt_0 <= 0;
gnt_1 <= 0;
gnt_2 <= 0;
end else if (req_0) begin
gnt_0 <= 1;
gnt_1 <= 0;
gnt_2 <= 0;
end else if (req_1) begin
gnt_0 <= 0;
gnt_1 <= 1;
gnt_2 <= 0;
end else if (req_2) begin
gnt_0 <= 0;
gnt_1 <= 0;
gnt_2 <= 1;
end else begin
gnt_0 <= 0;
gnt_1 <= 0;
gnt_2 <= 0;
end
end
endmodule |
module PRIORITY_ARBITER_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK, RST;
reg REQ_0, REQ_1, REQ_2;
wire GNT_0, GNT_1, GNT_2;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg GNT_2EXP, GNT_1EXP, GNT_0EXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
priority_arbiter_behavioral UUT_priority_arbiter_behavioral(
.clk(CLK),
.rst(RST),
.req_0(REQ_0),
.req_1(REQ_1),
.req_2(REQ_2),
.gnt_0(GNT_0),
.gnt_1(GNT_1),
.gnt_2(GNT_2)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("priority_arbiter_tb.vcd");
$dumpvars(0, PRIORITY_ARBITER_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("priority_arbiter_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, RST, REQ_2, REQ_1, REQ_0, GNT_2EXP, GNT_1EXP, GNT_0EXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | RST | REQ_2 | REQ_1 | REQ_0 | GNT_2EXP | GNT_1EXP | GNT_0EXP |");
$display(" ---------------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |",
// VECTORCOUNT, COMMENT, $time, RST, REQ_2, REQ_1, REQ_0, GNT_2, GNT_1, GNT_0);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, RST, REQ_2, REQ_1, REQ_0, GNT_2EXP, GNT_1EXP, GNT_0EXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |",
VECTORCOUNT, COMMENT, $time, RST, REQ_2, REQ_1, REQ_0, GNT_2, GNT_1, GNT_0);
// CHECK EACH VECTOR RESULT
if ((GNT_2 !== GNT_2EXP) | (GNT_1 !== GNT_1EXP) | (GNT_0 !== GNT_0EXP)) begin
$display("***ERROR (behavioral) - Expected GNT_2=%1b, GNT_1=%1b, GNT_0=%1b", GNT_2EXP, GNT_1EXP, GNT_0EXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module FIFO_SYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg RST;
reg [7:0] DATA_IN;
reg PUSH;
wire FULL;
wire [7:0] DATA_OUT;
reg POP;
wire EMPTY;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg FULLEXP;
reg [7:0] DATA_OUTEXP;
reg EMPTYEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
fifo_synchronous_structural UUT_fifo_synchronous_structural(
.clk(CLK),
.rst(RST),
.data_in(DATA_IN),
.push(PUSH),
.full(FULL),
.data_out(DATA_OUT),
.pop(POP),
.empty(EMPTY)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("fifo_synchronous_tb.vcd");
$dumpvars(0, FIFO_SYNCHRONOUS_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("fifo_synchronous_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, RST, PUSH, FULLEXP, DATA_IN, POP, EMPTYEXP, DATA_OUTEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | RST | PUSH | FULL | DATA_IN | POP | EMPTY | DATA_OUT |");
$display(" ----------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b |",
// VECTORCOUNT, COMMENT, $time, RST, WE, FULL, DATA_IN, RE, EMPTY, DATA_OUT);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, RST, PUSH, FULLEXP, DATA_IN, POP, EMPTYEXP, DATA_OUTEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b |",
VECTORCOUNT, COMMENT, $time, RST, PUSH, FULL, DATA_IN, POP, EMPTY, DATA_OUT);
// CHECK EACH VECTOR RESULT
if ((FULL !== FULLEXP) | (DATA_OUT !== DATA_OUTEXP) |(EMPTY !== EMPTYEXP)) begin
$display("***ERROR - Expected FULL=%b, DATA_OUT=%b, EMPTY=%b", FULLEXP, DATA_OUTEXP, EMPTYEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module fifo_synchronous_structural(
input clk, // Clock
input rst, // Reset
// PUSH
input [7:0] data_in, // DATA In
input push, // Push/Write enable
output full, // Full
// POP
output [7:0] data_out, // DATA Out
input pop, // Pop/Read enable
output empty); // Empty
//FIFO
// parameter DATA_WIDTH = 8;
// parameter ADDR_WIDTH = 4;
// parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// DATA TYPES
wire [3:0] w_ptr;
wire [3:0] r_ptr;
wire w_next;
wire r_next;
parameter zeros = 8'h00;
parameter zero = 1'b0;
// 16x8 dual port RAM
dual_port_ram_synchronous_behavioral dual_port_ram_synchronous(
.clk(clk),
.we_A(push),
.we_B(zero),
.addr_A(w_ptr),
.addr_B(r_ptr),
.data_in_A(data_in),
.data_in_B(zeros),
.data_out_A(),
.data_out_B(data_out)
);
write_logic write_logic(
.we(push),
.full(full),
.w_next(w_next)
);
read_logic read_logic(
.re(pop),
.empty(empty),
.r_next(r_next)
);
write_ptr write_ptr(
.clk(clk),
.rst(rst),
.w_next(w_next),
.w_ptr(w_ptr)
);
read_ptr read_ptr(
.clk(clk),
.rst(rst),
.r_next(r_next),
.r_ptr(r_ptr)
);
compare_and_status_logic compare_and_status_logic(
.w_ptr(w_ptr),
.full(full),
.r_ptr(r_ptr),
.empty(empty)
);
endmodule |
module single_port_ram_synchronous_behavioral(
input clk, // Clock
input we, // Write enable
input [ADDR_WIDTH-1:0] addr, // Address
input [DATA_WIDTH-1:0] data_in, // Data to write
output reg [DATA_WIDTH-1:0] data_out); // Data to read
// PARAMETERS
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 4;
parameter MEM_DEPTH = 16;
// DATA TYPES
reg [DATA_WIDTH-1:0] mem [0:MEM_DEPTH-1]; // RAM (16x8)
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk) begin
// WRITE (DATA PASS)
if (we) begin
mem[addr] <= data_in;
data_out <= data_in;
// READ
end else begin
data_out <= mem[addr];
end
end
endmodule |
module SINGLE_PORT_RAM_SYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg WE;
reg [3:0] ADDR;
reg [7:0] DATA_IN;
wire [7:0] DATA_OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
single_port_ram_synchronous_behavioral UUT_single_port_ram_synchronous_behavioral(
.clk (CLK),
.we (WE),
.addr (ADDR),
.data_in (DATA_IN),
.data_out (DATA_OUT)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("single_port_ram_synchronous_tb.vcd");
$dumpvars(0, SINGLE_PORT_RAM_SYNCHRONOUS_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("single_port_ram_synchronous_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, WE, ADDR, DATA_IN, DATA_OUTEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | WE | ADDR | DATA_IN | DATA_OUT |");
$display(" ----------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, WE, ADDR, DATA_IN, DATA_OUT);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b", COMMENT, WE, ADDR, DATA_IN, DATA_OUTEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, WE, ADDR, DATA_IN, DATA_OUT);
// CHECK EACH VECTOR RESULT
if (DATA_OUTEXP !== DATA_OUT) begin
$display("***ERROR - Expected DATA_OUT=%b", DATA_OUTEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module dual_port_ram_asynchronous_behavioral(
input clk_A, // Clock A
input clk_B, // Clock B
// PORT A
input we_A, // Write enable
input [ADDR_WIDTH-1:0] addr_A, // Address
input [DATA_WIDTH-1:0] data_in_A, // Data to write
output reg [DATA_WIDTH-1:0] data_out_A, // Data to read
// PORT B
input we_B, // Write enable
input [ADDR_WIDTH-1:0] addr_B, // Address
input [DATA_WIDTH-1:0] data_in_B, // Data to write
output reg [DATA_WIDTH-1:0] data_out_B); // Data to read
// PARAMETERS
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 4;
parameter MEM_DEPTH = 16;
// DATA TYPES
reg [DATA_WIDTH-1:0] mem [0:MEM_DEPTH-1]; // RAM (16x8)
// PORT A
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk_A) begin
// WRITE (DATA PASS)
if (we_A) begin
mem[addr_A] <= data_in_A;
data_out_A <= data_in_A;
// READ
end else begin
data_out_A <= mem[addr_A];
end
end
// PORT B - HAS PRECEDENCE FOR WRITE
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk_B) begin
//WRITE (DATA PASS)
if (we_B) begin
mem[addr_B] <= data_in_B;
data_out_B <= data_in_B;
//READ
end else begin
data_out_B <= mem[addr_B];
end
end
endmodule |
module DUAL_PORT_RAM_ASYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK_A, CLK_B;
reg WE_A, WE_B;
reg [3:0] ADDR_A, ADDR_B;
reg [7:0] DATA_IN_A, DATA_IN_B;
wire [7:0] DATA_OUT_A, DATA_OUT_B;
// FOR TESTING
reg [31:0] VECTORCOUNT_A, VECTORCOUNT_B, ERRORS_A, ERRORS_B;
reg [7:0] DATA_OUTEXP_A, DATA_OUTEXP_B;
integer FD_A, FD_B, COUNT_A, COUNT_B;
reg [8*32-1:0] COMMENT_A, COMMENT_B;
integer END_A, END_B;
// UNIT UNDER TEST
dual_port_ram_asynchronous_behavioral UUT_dual_port_ram_asynchronous_behavioral(
.clk_A (CLK_A), .clk_B (CLK_B),
.we_A (WE_A), .we_B (WE_B),
.addr_A (ADDR_A), .addr_B (ADDR_B),
.data_in_A (DATA_IN_A), .data_in_B (DATA_IN_B),
.data_out_A (DATA_OUT_A), .data_out_B (DATA_OUT_B)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("dual_port_ram_asynchronous_tb.vcd");
$dumpvars(0, DUAL_PORT_RAM_ASYNCHRONOUS_TB);
end
// CLK PERIOD
localparam CLKPERIOD_A = 20;
localparam CLKPERIOD_B = 15;
// CLK
always begin
#(CLKPERIOD_A/2) CLK_A = ~CLK_A;
end
always begin
#(CLKPERIOD_B/2) CLK_B = ~CLK_B;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD_A=$fopen("dual_port_ram_asynchronous_tb_A.tv","r");
FD_B=$fopen("dual_port_ram_asynchronous_tb_B.tv","r");
COUNT_A = $fscanf(FD_A, "%s", COMMENT_A);
COUNT_B = $fscanf(FD_B, "%s", COMMENT_B);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT_A = $fscanf(FD_A, "%s %b %b %b %b", COMMENT_A, WE_A, ADDR_A, DATA_IN_A, DATA_OUTEXP_A);
COUNT_B = $fscanf(FD_B, "%s %b %b %b %b", COMMENT_B, WE_B, ADDR_B, DATA_IN_B, DATA_OUTEXP_B);
CLK_A = 0;
CLK_B = 0;
VECTORCOUNT_A = 1;
VECTORCOUNT_B = 1;
ERRORS_A = 0;
ERRORS_B = 0;
END_A = 0;
END_B = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | WE_A | ADDR_A | DATA_IN_A | DATA_OUT_A | WE_B | ADDR_B | DATA_IN_B | DATA_OUT_B |");
$display(" ----------------------------------------------------------------------------------------------");
//$monitor("%4d %4s_%4s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT_A, COMMENT_A, COMMENT_A, $time,
// WE_A, ADDR_A, DATA_IN_A, DATA_OUT_A);
end
initial begin
// WAIT FOR TEST TO FINISH
wait (END_A == 1'b1 && END_B == 1'b1);
$display();
$display(" VECTORS_A: %4d", VECTORCOUNT_A);
$display(" ERRORS_A: %4d", ERRORS_A);
$display(" VECTORS_B: %4d", VECTORCOUNT_B);
$display(" ERRORS_B: %4d", ERRORS_B);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// APPLY TEST VECTORS ON NEG EDGE CLK_A (ADD DELAY)
always @(negedge CLK_A) begin
if (!END_A) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT_A = $fscanf(FD_A, "%s %b %b %b %b", COMMENT_A, WE_A, ADDR_A, DATA_IN_A, DATA_OUTEXP_A);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT_A == -1) begin
$fclose(FD_A);
END_A = 1;
end else begin
// GET ANOTHER VECTOR
VECTORCOUNT_A = VECTORCOUNT_A + 1;
end
end
// $display("Waiting for b to finish");
end
// APPLY TEST VECTORS ON NEG EDGE CLK_B (ADD DELAY)
always @(negedge CLK_B) begin
if (!END_B) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT_B = $fscanf(FD_B, "%s %b %b %b %b", COMMENT_B, WE_B, ADDR_B, DATA_IN_B, DATA_OUTEXP_B);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT_B == -1) begin
$fclose(FD_B);
END_B = 1;
end else begin
// GET ANOTHER VECTOR
VECTORCOUNT_B = VECTORCOUNT_B + 1;
end
end
// $display("Waiting for a to finish");
end
// CHECK TEST VECTORS ON POS EGDE CLK_A
always @(posedge CLK_A) begin
if (!END_A) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK_A
$display ("%4d %8s | %8d | %1b | %1b | %1b | %1b |", VECTORCOUNT_A, COMMENT_A, $time,
WE_A, ADDR_A, DATA_IN_A, DATA_OUT_A);
// CHECK EACH VECTOR RESULT
if (DATA_OUTEXP_A !== DATA_OUT_A) begin
$display("***ERROR - Expected DATA_OUT_A=%b for ADDR_A=%b", DATA_OUTEXP_A, ADDR_A);
ERRORS_A = ERRORS_A + 1;
end
end
end
// CHECK TEST VECTORS ON POS EGDE CLK_B
always @(posedge CLK_B) begin
if (!END_B) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK_B
$display(" %4d %8s | %8d | | %1b | %1b | %1b | %1b |", VECTORCOUNT_B, COMMENT_B, $time,
WE_B, ADDR_B, DATA_IN_B, DATA_OUT_B);
// CHECK EACH VECTOR RESULT
if (DATA_OUTEXP_B !== DATA_OUT_B) begin
$display("***ERROR - Expected DATA_OUT_B=%b for ADDR_B=%b", DATA_OUTEXP_B, ADDR_B);
ERRORS_B = ERRORS_B + 1;
end
end
end
endmodule |
module DUAL_PORT_RAM_SYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg WE_A, WE_B;
reg [3:0] ADDR_A, ADDR_B;
reg [7:0] DATA_IN_A, DATA_IN_B;
wire [7:0] DATA_OUT_A, DATA_OUT_B;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP_A, DATA_OUTEXP_B;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
dual_port_ram_synchronous_behavioral UUT_dual_port_ram_synchronous_behavioral(
.clk (CLK),
.we_A (WE_A), .we_B (WE_B),
.addr_A (ADDR_A), .addr_B (ADDR_B),
.data_in_A (DATA_IN_A), .data_in_B (DATA_IN_B),
.data_out_A (DATA_OUT_A), .data_out_B (DATA_OUT_B)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("dual_port_ram_synchronous_tb.vcd");
$dumpvars(0, DUAL_PORT_RAM_SYNCHRONOUS_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("dual_port_ram_synchronous_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b", COMMENT, WE_A, ADDR_A, DATA_IN_A, DATA_OUTEXP_A, WE_B, ADDR_B, DATA_IN_B, DATA_OUTEXP_B);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | WE_A | ADDR_A | DATA_IN_A | DATA_OUT_A | WE_B | ADDR_B | DATA_IN_B | DATA_OUT_B |");
$display(" ----------------------------------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time,
// WE_A, ADDR_A, DATA_IN_A, DATA_OUT_A, WE_B, ADDR_B, DATA_IN_B, DATA_OUT_B);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b", COMMENT, WE_A, ADDR_A, DATA_IN_A, DATA_OUTEXP_A, WE_B, ADDR_B, DATA_IN_B, DATA_OUTEXP_B);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time,
WE_A, ADDR_A, DATA_IN_A, DATA_OUT_A, WE_B, ADDR_B, DATA_IN_B, DATA_OUT_B);
// CHECK EACH VECTOR RESULT
if ((DATA_OUTEXP_A !== DATA_OUT_A) | (DATA_OUTEXP_B !== DATA_OUT_B)) begin
$display("***ERROR - Expected DATA_OUT_A=%b DATA_OUT_B=%b", DATA_OUTEXP_A, DATA_OUTEXP_B);
ERRORS = ERRORS + 1;
end
end
endmodule |
module fifo_asynchronous_structural(
// PUSH
input wclk, // Write Clock
input wrst, // Write Reset
input [7:0] data_in, // DATA In
input push, // Write enable
output full, // Full
// POP
input rclk, // Read Clock
input rrst, // Read Reset
output [7:0] data_out, // DATA Out
input pop, // Read enable
output empty); // Empty
// DATA TYPES
wire [3:0] w_ptr;
wire [3:0] r_ptr;
wire w_next;
wire r_next;
parameter zeros = 8'h00;
parameter zero = 1'b0;
// 16x8 dual port RAM
dual_port_ram_asynchronous_behavioral dual_port_ram_asynchronous(
.clk_A(wclk),
.clk_B(rclk),
.we_A(push),
.we_B(zero),
.addr_A(w_ptr),
.addr_B(r_ptr),
.data_in_A(data_in),
.data_in_B(zeros),
.data_out_A(),
.data_out_B(data_out)
);
write_logic write_logic(
.we(push),
.full(full),
.w_next(w_next)
);
read_logic read_logic(
.re(pop),
.empty(empty),
.r_next(r_next)
);
write_ptr write_ptr(
.clk(wclk),
.rst(wrst),
.w_next(w_next),
.w_ptr(w_ptr)
);
read_ptr read_ptr(
.clk(rclk),
.rst(rrst),
.r_next(r_next),
.r_ptr(r_ptr)
);
compare_and_status_logic compare_and_status_logic(
.w_ptr(w_ptr),
.full(full),
.r_ptr(r_ptr),
.empty(empty)
);
endmodule |
module FIFO_ASYNCHRONOUS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg WCLK, RCLK;
reg WRST, RRST;
reg [7:0] DATA_IN;
reg PUSH;
wire FULL;
wire [7:0] DATA_OUT;
reg POP;
wire EMPTY;
// FOR TESTING
reg [31:0] PUSHVECTORCOUNT, POPVECTORCOUNT, PUSHERRORS, POPERRORS;
reg FULLEXP;
reg [7:0] DATA_OUTEXP;
reg EMPTYEXP;
integer PUSHFD, POPFD, PUSHCOUNT, POPCOUNT;
reg [8*32-1:0] PUSHCOMMENT, POPCOMMENT;
integer PUSHEND, POPEND;
// UNIT UNDER TEST
fifo_asynchronous_structural UUT_fifo_asynchronous_structural (
.wclk(WCLK),
.rclk(RCLK),
.wrst(WRST),
.rrst(RRST),
.data_in(DATA_IN),
.push(PUSH),
.full(FULL),
.data_out(DATA_OUT),
.pop(POP),
.empty(EMPTY)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("fifo_asynchronous_tb.vcd");
$dumpvars(0, FIFO_ASYNCHRONOUS_TB);
end
// CLK PERIOD
localparam WCLKPERIOD = 20; // WRITE FASTER THAN READ
localparam RCLKPERIOD = 18;
// CLK
always begin
#(WCLKPERIOD/2) WCLK = ~WCLK;
end
always begin
#(RCLKPERIOD/2) RCLK = ~RCLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
PUSHFD=$fopen("fifo_asynchronous_tb_push.tv","r");
POPFD=$fopen("fifo_asynchronous_tb_pop.tv","r");
PUSHCOUNT = $fscanf(PUSHFD, "%s", PUSHCOMMENT);
POPCOUNT = $fscanf(POPFD, "%s", POPCOMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
PUSHCOUNT = $fscanf(PUSHFD, "%s %b %b %b %b", PUSHCOMMENT, WRST, PUSH, FULLEXP, DATA_IN);
POPCOUNT = $fscanf(POPFD, "%s %b %b %b %b", POPCOMMENT, RRST, POP, EMPTYEXP, DATA_OUTEXP);
WCLK = 0;
RCLK = 0;
PUSHVECTORCOUNT = 1;
POPVECTORCOUNT = 1;
PUSHERRORS = 0;
POPERRORS = 0;
PUSHEND = 0;
POPEND = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | WRST | RRST | PUSH | FULL | DATA_IN | POP | EMPTY | DATA_OUT |");
$display(" ----------------------------------------------------------------------------");
// $monitor(" %4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b | %1b |",
// PUSHVECTORCOUNT, PUSHCOMMENT, $time, WRST, RRST, PUSH, FULL, DATA_IN, POP, EMPTY, DATA_OUT);
end
initial begin
// WAIT FOR TEST TO FINISH
wait (PUSHEND == 1'b1 && POPEND == 1'b1);
$display();
$display(" PUSHVECTORS: %4d", PUSHVECTORCOUNT);
$display(" PUSHERRORS: %4d", PUSHERRORS);
$display(" POPVECTORS: %4d", POPVECTORCOUNT);
$display(" POPERRORS: %4d", POPERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// APPLY TEST VECTORS ON NEG EDGE WCLK (ADD DELAY)
always @(negedge WCLK) begin
if (!PUSHEND) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
PUSHCOUNT = $fscanf(PUSHFD, "%s %b %b %b %b", PUSHCOMMENT, WRST, PUSH, FULLEXP, DATA_IN);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (PUSHCOUNT == -1) begin
$fclose(PUSHFD);
PUSHEND = 1;
end else begin
// GET ANOTHER VECTOR
PUSHVECTORCOUNT = PUSHVECTORCOUNT + 1;
end
end
end
// APPLY TEST VECTORS ON NEG EDGE RCLK (ADD DELAY)
always @(negedge RCLK) begin
if (!POPEND) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
POPCOUNT = $fscanf(POPFD, "%s %b %b %b %b", POPCOMMENT, RRST, POP, EMPTYEXP, DATA_OUTEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (POPCOUNT == -1) begin
$fclose(POPFD);
POPEND = 1;
end else begin
// GET ANOTHER VECTOR
POPVECTORCOUNT = POPVECTORCOUNT + 1;
end
end
end
// CHECK TEST VECTORS ON POS EGDE WCLK
always @(posedge WCLK) begin
if (!PUSHEND) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE WCLK
$display ("%4d %8s | %8d | %1b | | %1b | %1b | %1b |", PUSHVECTORCOUNT, PUSHCOMMENT, $time,
WRST, PUSH, FULL, DATA_IN);
// CHECK EACH VECTOR POPSULT
if (FULL !== FULLEXP) begin
$display("***PUSHERROR - Expected FULL=%b", FULLEXP);
PUSHERRORS = PUSHERRORS + 1;
end
end
end
// CHECK TEST VECTORS ON POS EGDE RCLK
always @(posedge RCLK) begin
if (!POPEND) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE RCLK
$display(" %4d %8s | %8d | | %1b | | %1b | %1b | %1b |", POPVECTORCOUNT, POPCOMMENT, $time,
RRST, POP, EMPTY, DATA_OUT);
// CHECK EACH VECTOR RESULT
if ((DATA_OUT !== DATA_OUTEXP) |(EMPTY !== EMPTYEXP)) begin
$display("***POPERROR - Expected DATA_OUT=%b, EMPTY=%b", DATA_OUTEXP, EMPTYEXP);
POPERRORS = POPERRORS + 1;
end
end
end
endmodule |
module lifo_synchronous_structural(
input clk, // Clock
input rst, // Reset
input [7:0] data_in, // DATA In
input push, // Write enable
output full, // Full
output [7:0] data_out, // DATA Out
input pop, // Read enable
output empty); // Empty
//FIFO
// parameter DATA_WIDTH = 8;
// parameter ADDR_WIDTH = 4;
// parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// DATA TYPES
wire [3:0] wrt_ptr, rd_ptr;
wire w_next;
wire r_next;
parameter zeros = 8'h00;
parameter zero = 1'b0;
// 16x8 dual port RAM
dual_port_ram_synchronous_behavioral dual_port_ram_synchronous(
.clk(clk),
.we_A(push),
.we_B(zero),
.addr_A(wrt_ptr),
.addr_B(rd_ptr),
.data_in_A(data_in),
.data_in_B(zeros),
.data_out_A(),
.data_out_B(data_out)
);
write_logic write_logic(
.we(push),
.full(full),
.w_next(w_next)
);
read_logic read_logic(
.re(pop),
.empty(empty),
.r_next(r_next)
);
stack_ptr_control stack_ptr_control(
.clk(clk),
.rst(rst),
.w_next(w_next),
.r_next(r_next),
.wrt_ptr(wrt_ptr),
.rd_ptr(rd_ptr)
);
compare_and_status_logic compare_and_status_logic(
.wrt_ptr(wrt_ptr),
.full(full),
.empty(empty)
);
endmodule |
module write_logic (
input we, // Write enable
input full, // Full
output reg w_next); // Write next
//If FIFO full write counter should not increment
always @(*) begin
if (we && (!full))
w_next=1;
else
w_next=0;
end
endmodule |
module read_ptr (
input clk, // Clock
input rst, // Reset
input r_next, // Read next
output reg [3:0] r_ptr); // Read pointer
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (rst) begin
r_ptr <= 3'b000;
end else if (r_next) begin
r_ptr <= r_ptr + 1;
end else begin
r_ptr <= r_ptr;
end
end
endmodule |
module read_logic (
input re, // Read enable
input empty, // Empty
output reg r_next); // Read next
//If FIFO empty read counter should not increment
always @(*) begin
if (re && (!empty))
r_next=1;
else
r_next=0;
end
endmodule |
module compare_and_status_logic (
input [3:0] w_ptr, // Write pointer
output reg full, // Full
input [3:0] r_ptr, // Read pointer
output reg empty); // Empty
parameter depth = 4'b1111; // Depth of the FIFO
// DATA TYPES
reg [3:0] ptr_diff;
// FULL STATUS
always @(*) begin
if (ptr_diff == depth) begin
full = 1'b1;
end else begin
full = 1'b0;
end
end
// EMPTY STATUS
always @(*) begin
if (ptr_diff == 0) begin
empty = 1'b1;
end else begin
empty = 1'b0;
end
end
// HOW MUCH MEMORY USED
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(*) begin
if (w_ptr > r_ptr) begin
ptr_diff <= w_ptr - r_ptr + 1;
end else if (w_ptr < r_ptr) begin
ptr_diff <= (depth - r_ptr) + w_ptr + 1;
end else if (w_ptr == r_ptr) begin
ptr_diff <= 0;
end
end
endmodule |
module write_ptr (
input clk, // Clock
input rst, // Reset
input w_next, // Write next
output reg [3:0] w_ptr); // Write pointer
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (rst) begin
w_ptr <= 3'b000;
end else if (w_next) begin
w_ptr <= w_ptr + 1;
end else begin
w_ptr <= w_ptr;
end
end
endmodule |
module stack_ptr_control (
input clk, // Clock
input rst, // Reset
input w_next, // Write next
input r_next, // Read next
output reg [3:0] wrt_ptr, // Write pointer
output reg [3:0] rd_ptr); // Read pointer
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
//RESET
if (rst) begin
wrt_ptr <= 4'b0000;
rd_ptr <= 4'b0000;
// BOTTOM - PUSH
end else if ((wrt_ptr == 4'b0000) & (w_next)) begin
wrt_ptr <= wrt_ptr + 1;
// BOTTOM - POP
end else if ((rd_ptr == 4'b0000) & (r_next)) begin
wrt_ptr <= 4'b0000;
// PUSH
end else if (w_next) begin
wrt_ptr <= wrt_ptr + 1;
rd_ptr <= rd_ptr + 1;
// POP
end else if (r_next) begin
wrt_ptr <= wrt_ptr - 1;
rd_ptr <= rd_ptr - 1;
end
end
endmodule |
module compare_and_status_logic (
input [3:0] wrt_ptr, // Stack pointer
output reg full, // Full
output reg empty); // Empty
parameter depth = 4'b1111; // Depth of the FIFO
// HOW MUCH MEMORY USED
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(*) begin
if (wrt_ptr == 0) begin
full <= 1'b0;
empty <= 1'b1;
end else if (wrt_ptr < depth) begin
full <= 1'b0;
empty <= 1'b0;
end else if (wrt_ptr == depth) begin
full <= 1'b1;
empty <= 1'b0;
end
end
endmodule |
module jeff_74x377_structural (
input en_bar, // ENABLE
input clk, // CLOCK
input d0, // DATA IN
input d1, //
input d2, //
input d3, //
input d4, //
input d5, //
input d6, //
input d7, //
output q0, // DATA OUT
output q1, //
output q2, //
output q3, //
output q4, //
output q5, //
output q6, //
output q7); //
wire NOTHING;
// EN AND FEEDBACK
// assign clk_feedback = (clk & ~en_feedback);
// assign en_feedback = (~en_bar & ~clk_feedback);
// d_flip_flop_pos_edge_sync_en_behavioral DFF7 (.clk(clk), .en(en_feedback), .d(d7), .q(q7), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF6 (.clk(clk), .en(en_feedback), .d(d6), .q(q6), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF5 (.clk(clk), .en(en_feedback), .d(d5), .q(q5), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF4 (.clk(clk), .en(en_feedback), .d(d4), .q(q4), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF3 (.clk(clk), .en(en_feedback), .d(d3), .q(q3), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF2 (.clk(clk), .en(en_feedback), .d(d2), .q(q2), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF1 (.clk(clk), .en(en_feedback), .d(d1), .q(q1), .qbar(NOTHING));
// d_flip_flop_pos_edge_sync_en_behavioral DFF0 (.clk(clk), .en(en_feedback), .d(d0), .q(q0), .qbar(NOTHING));
assign en = ~en_bar;
assign high = 1'b1;
assign from_d7 = ((d7 & en) | (en_bar & q7));
assign from_d6 = ((d6 & en) | (en_bar & q6));
assign from_d5 = ((d5 & en) | (en_bar & q5));
assign from_d4 = ((d4 & en) | (en_bar & q4));
assign from_d3 = ((d3 & en) | (en_bar & q3));
assign from_d2 = ((d2 & en) | (en_bar & q2));
assign from_d1 = ((d1 & en) | (en_bar & q1));
assign from_d0 = ((d0 & en) | (en_bar & q0));
d_flip_flop_pos_edge_sync_en_behavioral DFF7 (.clk(clk), .en(high), .d(from_d7), .q(q7), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF6 (.clk(clk), .en(high), .d(from_d6), .q(q6), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF5 (.clk(clk), .en(high), .d(from_d5), .q(q5), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF4 (.clk(clk), .en(high), .d(from_d4), .q(q4), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF3 (.clk(clk), .en(high), .d(from_d3), .q(q3), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF2 (.clk(clk), .en(high), .d(from_d2), .q(q2), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF1 (.clk(clk), .en(high), .d(from_d1), .q(q1), .qbar(NOTHING));
d_flip_flop_pos_edge_sync_en_behavioral DFF0 (.clk(clk), .en(high), .d(from_d0), .q(q0), .qbar(NOTHING));
endmodule |
module JEFF_74x377_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg EN_BAR;
reg D7, D6, D5, D4, D3, D2, D1, D0;
wire Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg Q7EXP, Q6EXP, Q5EXP, Q4EXP, Q3EXP, Q2EXP, Q1EXP, Q0EXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
jeff_74x377_structural UUT_jeff_74x377_structural(
.clk(CLK),
.en_bar(EN_BAR),
.d7(D7), .d6(D6), .d5(D5), .d4(D4), .d3(D3), .d2(D2), .d1(D1), .d0(D0),
.q7(Q7), .q6(Q6), .q5(Q5), .q4(Q4), .q3(Q3), .q2(Q2), .q1(Q1), .q0(Q0)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jeff_74x377_tb.vcd");
$dumpvars(0, JEFF_74x377_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jeff_74x377_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b",
COMMENT, EN_BAR, D7, D6, D5, D4, D3, D2, D1, D0, Q7EXP, Q6EXP, Q5EXP, Q4EXP, Q3EXP, Q2EXP, Q1EXP, Q0EXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | EN_BAR | D7 D6 D5 D4 D3 D2 D1 D0 | Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 |");
$display(" -------------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b %1b %1b %1b %1b %1b %1b %1b | %1b %1b %1b %1b %1b %1b %1b %1b |",
// VECTORCOUNT, COMMENT, $time, EN_BAR, D7, D6, D5, D4, D3, D2, D1, D0, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b",
COMMENT, EN_BAR, D7, D6, D5, D4, D3, D2, D1, D0, Q7EXP, Q6EXP, Q5EXP, Q4EXP, Q3EXP, Q2EXP, Q1EXP, Q0EXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b %1b %1b %1b %1b %1b %1b %1b | %1b %1b %1b %1b %1b %1b %1b %1b |",
VECTORCOUNT, COMMENT, $time, EN_BAR, D7, D6, D5, D4, D3, D2, D1, D0, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
// CHECK EACH VECTOR RESULT
if ((Q7EXP !== Q7) | (Q6EXP !== Q6) | (Q5EXP !== Q5) | (Q4EXP !== Q4) | (Q3EXP !== Q3) | (Q2EXP !== Q2) | (Q1EXP !== Q1) | (Q0EXP !== Q0)) begin
$display("***ERROR (behavioral) - Expected Q7=%b, Q6=%b, Q5=%b, Q4=%b, Q3=%b, Q2=%b, Q1=%b, Q0=%b", Q7EXP, Q6EXP, Q5EXP, Q4EXP, Q3EXP, Q2EXP, Q1EXP, Q0EXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module simple_8_bit_register_behavioral (
input [7:0] data_in, // Data to load
input clk, // Clock
input ld_bar, // Load
input clr_bar, // Clear
output reg [7:0] data_out // Output Data
);
// 8-BIT REGISTER
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (~clr_bar) begin
data_out <= 0;
end else if (~ld_bar) begin
data_out <= data_in;
end
end
endmodule |
module left_shift_register_behavioral (
input clk, // clk
input rst, // Reset
input d, // d
output reg [3:0] out); // out
// LEFT SHIFT REGISTER
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (rst) begin
out <= 4'b0000;
end else begin
out <= {out[2:0], d};
end
end
endmodule |
module LEFT_SHIFT_REGISTER_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg RST;
reg D;
wire [3:0] OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [3:0] OUTEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
left_shift_register_behavioral UUT_left_shift_register_behavioral(
.clk(CLK),
.rst(RST),
.d(D),
.out(OUT)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("left_shift_register_tb.vcd");
$dumpvars(0, LEFT_SHIFT_REGISTER_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("left_shift_register_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, D, OUTEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | RST | D | OUT |");
$display(" -----------------------------");
// $monitor("%4d %10s | %8d | %b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, RST, D, OUT);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b", COMMENT, RST, D, OUTEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, RST, D, OUT);
// CHECK EACH VECTOR RESULT
if (OUT !== OUTEXP) begin
$display("***ERROR (behavioral) - Expected OUT = %b", OUTEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module jeff_74x161(
input clr_bar, // ASYNC CLEAR
input ld_bar, // LOAD
input ent, // ENABLE T
input enp, // ENABLE P
input clk, // CLK
input a, b, c, d, // DATA IN
output qa, qb, qc, qd, // DATA OUT
output rco); // RIPPLE CARRY OUTPUT
wire ld;
wire ent_and_enp;
assign rco = ent & qd & qc & qb & qa;
assign ld = ~ld_bar;
assign ent_and_enp = ent & enp;
assign feedback_qd = ent_and_enp & qc & qb & qa;
output_section OUTPUT_QD (
.clr_bar(clr_bar),
.ld(ld),
.feedback(feedback_qd),
.clk(clk),
.data(d),
.q(qd)
);
assign feedback_qc = ent_and_enp & qb & qa;
output_section OUTPUT_QC (
.clr_bar(clr_bar),
.ld(ld),
.feedback(feedback_qc),
.clk(clk),
.data(c),
.q(qc)
);
assign feedback_qb = ent_and_enp & qa;
output_section OUTPUT_QB (
.clr_bar(clr_bar),
.ld(ld),
.feedback(feedback_qb),
.clk(clk),
.data(b),
.q(qb)
);
assign feedback_qa = ent_and_enp;
output_section OUTPUT_QA (
.clr_bar(clr_bar),
.ld(ld),
.feedback(feedback_qa),
.clk(clk),
.data(a),
.q(qa)
);
endmodule |
module JEFF_74x161_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLR_BAR, LD_BAR;
reg ENT, ENP;
reg CLK;
reg A, B, C, D;
wire QA, QB, QC, QD;
wire RCO;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg QAEXP, QBEXP, QCEXP, QDEXP, RCOEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
jeff_74x161 UUT_jeff_74x161(
.clr_bar(CLR_BAR), .ld_bar(LD_BAR),
.ent(ENT), .enp(ENP),
.clk(CLK),
.a(A), .b(B), .c(C), .d(D),
.qa(QA), .qb(QB), .qc(QC), .qd(QD),
.rco(RCO)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("jeff_74x161_tb.vcd");
$dumpvars(0, JEFF_74x161_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("jeff_74x161_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b %b %b %b", COMMENT, CLR_BAR, LD_BAR, ENT, ENP, D, C, B, A, QDEXP, QCEXP, QBEXP, QAEXP, RCOEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | CLR_BAR | LD_BAR | ENT | ENP | D | C | B | A | QD | QC | QB | QA | RCO |");
$display(" -------------------------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |",
// VECTORCOUNT, COMMENT, $time, CLR_BAR, LD_BAR, ENT, ENP, D, C, B, A, QD, QC, QB, QA, RCO);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b %b %b %b %b %b %b", COMMENT, CLR_BAR, LD_BAR, ENT, ENP, D, C, B, A, QDEXP, QCEXP, QBEXP, QAEXP, RCOEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d | %1d |",
VECTORCOUNT, COMMENT, $time, CLR_BAR, LD_BAR, ENT, ENP, D, C, B, A, QD, QC, QB, QA, RCO);
// CHECK EACH VECTOR RESULT
if ((QDEXP !== QD) | (QCEXP !== QC) | (QBEXP !== QB) | (QAEXP !== QA) | (RCOEXP !== RCO)) begin
$display("***ERROR (behavioral) - Expected QD=%b QC=%b QB=%b QA=%b RCO=%b", QDEXP, QCEXP, QBEXP, QAEXP, RCOEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module output_section (
input clr_bar,
input ld,
input feedback,
input clk,
input data,
output q);
wire NOTHING;
assign to_j_and_k = (feedback | ld);
assign to_j = ~(ld & to_k);
assign to_k = ~(data & ld);
assign j = (to_j & to_j_and_k);
assign k = (to_k & to_j_and_k);
jk_flip_flop_pos_edge_sync_clear_behavioral JK (
.clk(clk),
.clrbar(clr_bar),
.j(j),
.k(k),
.q(q),
.qbar(NOTHING)
);
endmodule |
module button1_sync_push_release_behavioral (
input clk, // CLOCK
input pressed, // BUTTON IN
output reg out); // PULSE FOR 1 CLOCK CYCLE
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk) begin
if (pressed) begin // BUTTON PRESSED
out <= 1'b1;
end else begin // BUTTON NOT PRESSED
out <= 1'b0;
end
end
endmodule |
module button2_sync_clock_pulse_behavioral (
input clk, // CLOCK
input pressed, // BUTTON IN (YOU CAN HOLD AND RELEASE WHENEVER)
output reg out); // PULSE FOR 1 CLOCK CYCLE
reg lock = 0;
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk) begin
if (pressed & ~lock) begin // BUTTON PRESSED
lock <= 1'b1; // - Lock
out <= 1'b1; // - Pulse
end else if (~pressed & lock) begin // RELEASE LOCK
lock <= 1'b0;
out <= 1'b0;
end else begin
out <= 1'b0;
end
end
endmodule |
module button3_sync_two_presses_behavioral (
input clk, // CLOCK
input pressed, // BUTTON IN (YOU CAN HOLD AND RELEASE WHENEVER)
output out); // TWO PRESSES
reg lock = 0;
reg toggle = 0;
assign out = toggle;
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
if (pressed & ~lock) begin // BUTTON PRESSED
lock <= 1'b1; // - Lock
toggle <= ~toggle; // - Toggle
end else if (~pressed & lock) begin // WAIT TILL BUTTON RELEASED
lock <= 1'b0; // - Release Lock
end
end
endmodule |
module button4_async_clock_pulse_behavioral (
input clk, // CLOCK
input pressed, // BUTTON IN (YOU CAN HOLD AND RELEASE WHENEVER)
output out); // PULSE FOR 1 CLOCK CYCLE
reg was_pressed = 0;
reg lock = 0;
reg pre_out = 0;
assign out = pre_out;
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk or posedge pressed) begin
if (pressed & ~was_pressed & ~lock) begin // BUTTON PRESSED - Then forget about it until later
was_pressed <= 1'b1;
end else if (was_pressed & ~lock) begin // OUT HIGH
lock <= 1;
was_pressed <= 0;
pre_out <= 1'b1;
end else if (lock & out) begin // OUT LOW
pre_out <= 1'b0;
end else if (~pressed & lock) begin // WAIT TILL BUTTON RELEASED
lock <= 1'b0;
end
end
endmodule |
module BUTTONS_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg CLK;
reg PRESSED;
wire BUTTON1_SYNC_PUSH_RELEASE;
wire BUTTON2_SYNC_CLOCK_PULSE_OUT;
wire BUTTON3_SYNC_TWO_PRESSES_OUT;
wire BUTTON4_ASYNC_CLOCK_PULSE_OUT;
wire BUTTON5_ASYNC_TWO_PRESSES_OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg OUT1EXP, OUT2EXP, OUT3EXP, OUT4EXP, OUT5EXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// BUTTON 1 - UNIT UNDER TEST
button1_sync_push_release_behavioral SYNC_PUSH_RELEASE (
.clk(CLK),
.pressed(PRESSED),
.out(BUTTON1_SYNC_PUSH_RELEASE)
);
// BUTTON 2 - UNIT UNDER TEST
button2_sync_clock_pulse_behavioral SYNC_CLOCK_PULSE (
.clk(CLK),
.pressed(PRESSED),
.out(BUTTON2_SYNC_CLOCK_PULSE_OUT)
);
// BUTTON 3 - UNIT UNDER TEST
button3_sync_two_presses_behavioral SYNC_TWO_PRESSES (
.clk(CLK),
.pressed(PRESSED),
.out(BUTTON3_SYNC_TWO_PRESSES_OUT)
);
// BUTTON 4 - UNIT UNDER TEST
button4_async_clock_pulse_behavioral ASYNC_CLOCK_PULSE (
.clk(CLK),
.pressed(PRESSED),
.out(BUTTON4_ASYNC_CLOCK_PULSE_OUT)
);
// BUTTON 5 - UNIT UNDER TEST
button5_async_two_presses_behavioral ASYNC_TWO_PRESSES (
.clk(CLK),
.pressed(PRESSED),
.out(BUTTON5_ASYNC_TWO_PRESSES_OUT)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("buttons_tb.vcd");
$dumpvars(0, BUTTONS_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("buttons_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b", COMMENT, PRESSED, OUT1EXP, OUT2EXP, OUT3EXP, OUT4EXP, OUT5EXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" 1 2 3 4 5");
$display(" | TIME(ns) | PRESSED | OUT | OUT | OUT | OUT | OUT |");
$display(" ----------------------------------------------------");
// $monitor("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, PRESSED,
// BUTTON1_SYNC_PUSH_RELEASE, BUTTON2_SYNC_CLOCK_PULSE_OUT, BUTTON3_SYNC_TWO_PRESSES_OUT, BUTTON4_ASYNC_CLOCK_PULSE_OUT, BUTTON5_ASYNC_TWO_PRESSES_OUT);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b", COMMENT, PRESSED, OUT1EXP, OUT2EXP, OUT3EXP, OUT4EXP, OUT5EXP);
// SPECIAL QUICK PULSE TEST
// I COULD OF DONE THIS BETTER - BUT IT'S FINE FOR NOW
if (COMMENT == "ASYNC") begin
PRESSED = 1;
#5
PRESSED = 0;
end
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1d | %1d | %1d | %1d | %1d | %1d |", VECTORCOUNT, COMMENT, $time, PRESSED,
BUTTON1_SYNC_PUSH_RELEASE, BUTTON2_SYNC_CLOCK_PULSE_OUT, BUTTON3_SYNC_TWO_PRESSES_OUT, BUTTON4_ASYNC_CLOCK_PULSE_OUT, BUTTON5_ASYNC_TWO_PRESSES_OUT);
// CHECK EACH VECTOR RESULT
if (BUTTON1_SYNC_PUSH_RELEASE !== OUT1EXP) begin
$display("***ERROR - Expected BUTTON1 = %b", OUT1EXP);
ERRORS = ERRORS + 1;
end
if (BUTTON2_SYNC_CLOCK_PULSE_OUT !== OUT2EXP) begin
$display("***ERROR - Expected BUTTON2 = %b", OUT2EXP);
ERRORS = ERRORS + 1;
end
if (BUTTON3_SYNC_TWO_PRESSES_OUT !== OUT3EXP) begin
$display("***ERROR - Expected BUTTON3 = %b", OUT3EXP);
ERRORS = ERRORS + 1;
end
if (BUTTON4_ASYNC_CLOCK_PULSE_OUT !== OUT4EXP) begin
$display("***ERROR - Expected BUTTON4 = %b", OUT4EXP);
ERRORS = ERRORS + 1;
end
if (BUTTON5_ASYNC_TWO_PRESSES_OUT !== OUT5EXP) begin
$display("***ERROR - Expected BUTTON5 = %b", OUT5EXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module simple_pipeline_behavioral (
input clk, // Clock
input [7:0] a, b, c, d, // Data
output reg [7:0] f); // Output Data
reg [7:0] y1, y2, y3, d1, d2;
// STAGE 1
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
y1 <= a + b;
y2 <= c - d;
d1 <= d;
end
// STAGE 2
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
y3 <= y1 + y2;
d2 <= d1;
end
// STAGE 3
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @ (posedge clk) begin
f <= y3 * d2;
end
endmodule |
module SIMPLE_PIPELINE_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] A, B, C, D;
reg CLK;
wire [7:0] F;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] FEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
simple_pipeline_behavioral UUT_simple_pipeline_behavioral(
.clk(CLK),
.a (A),
.b (B),
.c (C),
.d (D),
.f (F)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("simple_pipeline_tb.vcd");
$dumpvars(0, SIMPLE_PIPELINE_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("simple_pipeline_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, C, D, FEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | A | B | C | D | F |");
$display(" -------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, A, B, C, D, F);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b", COMMENT, A, B, C, D, FEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b |", VECTORCOUNT, COMMENT, $time, A, B, C, D, F);
// CHECK EACH VECTOR RESULT
if (F !== FEXP) begin
$display("***ERROR (behavioral) - Expected F = %b", FEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module PROGRAMABLE_8_BIT_MICROPROCESSOR_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [3:0] OPCODE;
reg [7:0] DATA_IN_A;
reg [7:0] DATA_IN_B;
reg GO_BAR;
reg RESET;
reg JAM;
reg CLK;
wire [23:0] MW;
wire [7:0] MICROADDRESS;
wire [7:0] DATA_OUT;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] DATA_OUTEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST
programable_8_bit_microprocessor UUT_programable_8_bit_microprocessor (
.OPCODE(OPCODE),
.DATA_IN_A(DATA_IN_A),
.DATA_IN_B(DATA_IN_B),
.GO_BAR(GO_BAR),
.RESET(RESET),
.JAM(JAM),
.SYSTEM_CLK(CLK),
.MW(MW),
.MICROADDRESS(MICROADDRESS),
.DATA_OUT(DATA_OUT)
);
// CONTROL_STORE
control_store CS (
.microaddress(MICROADDRESS),
.microword(MW)
);
// SAVE EVERYTHING FROM TOP TB MODULE IN A DUMP FILE
initial begin
$dumpfile("programable_8_bit_microprocessor_tb.vcd");
$dumpvars(0, PROGRAMABLE_8_BIT_MICROPROCESSOR_TB);
end
// CLK PERIOD
localparam CLKPERIOD = 20;
// CLK
always begin
#(CLKPERIOD/2) CLK = ~CLK;
end
// INITIALIZE TESTBENCH
initial begin
// OPEN VECTOR FILE - THROW AWAY FIRST LINE
FD=$fopen("programable_8_bit_microprocessor_tb.tv","r");
COUNT = $fscanf(FD, "%s", COMMENT);
// $display ("FIRST LINE IS: %s", COMMENT);
// INIT TESTBENCH
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, GO_BAR, RESET, JAM, OPCODE, DATA_IN_A, DATA_IN_B, DATA_OUTEXP);
CLK = 0;
VECTORCOUNT = 1;
ERRORS = 0;
// DISPAY OUTPUT AND MONITOR
$display();
$display("TEST START --------------------------------");
$display();
$display(" | TIME(ns) | GO_BAR | RESET | JAM | OPCODE | DATA_IN_A | DATA_IN_B | DATA_OUT |");
$display(" -------------------------------------------------------------------------------");
// $monitor("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b |",
// VECTORCOUNT, COMMENT, $time, GO_BAR, RESET, JAM, OPCODE, DATA_IN_A, DATA_IN_B, DATA_OUT);
end
// APPLY TEST VECTORS ON NEG EDGE CLK (ADD DELAY)
always @(negedge CLK) begin
// WAIT A BIT (AFTER CHECK)
#5;
// GET VECTORS FROM TB FILE
COUNT = $fscanf(FD, "%s %b %b %b %b %b %b %b", COMMENT, GO_BAR, RESET, JAM, OPCODE, DATA_IN_A, DATA_IN_B, DATA_OUTEXP);
// CHECK IF EOF - PRINT SUMMARY, CLOSE VECTOR FILE AND FINISH TB
if (COUNT == -1) begin
$fclose(FD);
$display();
$display(" VECTORS: %4d", VECTORCOUNT);
$display(" ERRORS: %4d", ERRORS);
$display();
$display("TEST END ----------------------------------");
$display();
$finish;
end
// GET ANOTHER VECTOR
VECTORCOUNT = VECTORCOUNT + 1;
end
// CHECK TEST VECTORS ON POS EGDE CLK
always @(posedge CLK) begin
// WAIT A BIT
#5;
// DISPLAY OUTPUT ON POS EDGE CLK
$display("%4d %10s | %8d | %1b | %1b | %1b | %1b | %1b | %1b | %1b |",
VECTORCOUNT, COMMENT, $time, GO_BAR, RESET, JAM, OPCODE, DATA_IN_A, DATA_IN_B, DATA_OUT);
// CHECK EACH VECTOR RESULT
if (DATA_OUT !== DATA_OUTEXP) begin
$display("***ERROR (behavioral) - Expected DATA_OUT = %b", DATA_OUTEXP);
ERRORS = ERRORS + 1;
end
end
endmodule |
module programable_8_bit_microprocessor (
input [3:0] OPCODE, //
input [7:0] DATA_IN_A, //
input [7:0] DATA_IN_B, //
input GO_BAR, //
input RESET, //
input JAM, //
input SYSTEM_CLK, //
input [23:0] MW, //
output [7:0] MICROADDRESS, //
output [7:0] DATA_OUT //
);
// WIRES
wire [3:0] STATUS_BITS;
wire [23:13] CONTROL_BITS;
wire EIL_BAR;
// CONTROL_SECTION
control CONTROL_SECTION (
.OPCODE(OPCODE),
.GO_BAR(GO_BAR),
.RESET(RESET),
.JAM(JAM),
.SYSTEM_CLK(SYSTEM_CLK),
.STATUS_BITS(STATUS_BITS),
.MW(MW),
.MICROADDRESS(MICROADDRESS),
.CONTROL_BITS(CONTROL_BITS), // ORDER DIFFERENT FROM THESIS
.EIL_BAR(EIL_BAR)
);
// PROCESSOR SECTION
processor PROCESSOR_SECTION (
.DATA_IN_A(DATA_IN_A),
.DATA_IN_B(DATA_IN_B),
.SYSTEM_CLK(SYSTEM_CLK),
.EIL_BAR(EIL_BAR),
.CONTROL_BITS(CONTROL_BITS),
.STATUS_BITS(STATUS_BITS),
.DATA_OUT(DATA_OUT)
);
endmodule |
module control_store (
input [7:0] microaddress, // ADDRESS
output [23:0] microword // WORD
);
// THE MICROWORD FIELDS
reg [3:0] MICRO_AD_LOW; // [3:0]
reg [7:4] MICRO_AD_HIGH; // [7:4]
reg COUNT; // [8]
reg [12:9] BOP; // [12:9]
wire [23:11] control_bits;
reg A_SOURCE; // [13]
reg B_SOURCE; // [14]
reg [19:15] ALU_FUNC; // [19:15]
reg CIN; // [20]
reg [23:21] ALU_DEST; // [23:21]
assign control_bits = {ALU_DEST, CIN, ALU_FUNC, B_SOURCE, A_SOURCE};
assign microword = {control_bits, BOP, COUNT, MICRO_AD_HIGH, MICRO_AD_LOW};
always @ (microaddress) begin
case (microaddress)
// 8'h00 - RESET - WAIT FOR GO ************************************************************************
8'h00: begin // START RESET - Flash 11 output
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD (DEFAULT)
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hB; // OB
end
8'h0B: begin // LOAD TEMP REGSITERS WITH 1s - Just so the alu has a known value going into it
ALU_DEST <= 3'b100; // TB_TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'h0C: begin // COUNT - Flash 00 output
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD (DEFAULT)
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'h0D: begin // WAIT FOR GO_BAR - Output is F's
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0100; // G0_BAR
COUNT <= 1'b1; // COUNT_IF_NO_LD (DEFAULT)
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hD; // OD (LOOP)
end
8'h0E: begin // GET OPCODE
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1111; // OPCODE (ALSO LOADS INPUT REG)
COUNT <= 1'b1; // COUNT_IF_NO_LD (DEFAULT)
MICRO_AD_HIGH <= 4'hF; MICRO_AD_LOW <= 4'h1; // X1 - The opcode will be the high
end
// 8'h01 - OPCODE 0000 *********************************************************************************
// 8'h11 - OPCODE 0001 *********************************************************************************
// 8'h21 - OPCODE 0010 ********************************************************************************
// 8'h31 - OPCODE 0011 - ADD **************************************************************************
8'h31: begin // ADD AND WAIT FOR GO TO RELEASE - THEN RESET
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b01001; // A_PLUS_B
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // INPUT_B, INPUT_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'h32: begin // WAIT FOR GO TO BE RELEASED
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1100; // !GO_BAR
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h3; MICRO_AD_LOW <= 4'h2; // 32 (LOOP)
end
8'h33: begin // GOTO RESET - FLASH 00
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hD; // OD (TO RESET)
end
// 8'h41 - OPCODE 0100 *********************************************************************************
// 8'h51 - OPCODE 0101 *********************************************************************************
// 8'h61 - OPCODE 0110 *********************************************************************************
// 8'h71 - OPCODE 0111 - SUBTRACT **********************************************************************
8'h71: begin // SUBTRACT AND WAIT FOR GO TO RELEASE - THEN RESET
ALU_DEST <= 3'b011; // F
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00110; // A_MINUS_B (MUST HAVE CARRY)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // INPUT_B, INPUT_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'h72: begin // WAIT FOR GO TO BE RELEASED
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1100; // !GO_BAR
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h7; MICRO_AD_LOW <= 4'h2; // 72 (LOOP)
end
8'h73: begin // GOTO RESET - FLASH 00
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hD; // OD (TO RESET)
end
// 8'h81 - OPCODE 1000 *********************************************************************************
// 8'h91 - OPCODE 1001 *********************************************************************************
// 8'hA1 - OPCODE 1010 *********************************************************************************
// 8'hB1 - OPCODE 1011 *********************************************************************************
// 8'hC1 - OPCODE 1100 - MULTIPLY **********************************************************************
// THE CONCEPT IS TEMP_REGISTER_A WILL START WITH DATA_IN_B AND COUNT DOWN TO 0
// AND TEMP_REGISTER_B WILL JUST ADD DATA_IN_A TO ITSELF UNTIL THE COUNT DOWN IS 0
8'hC1: begin // LOAD 0 (CLEAR) TO TEMP_REGISTER_B
ALU_DEST <= 3'b101; // TB
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b10011; // 0
B_SOURCE <= 1'b0; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hC2: begin // CHECK IF REGISTER B = 0 WE ARE DONE - (1st LOAD F with B)
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b11010; // B
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // INPUT_B, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hC3: begin // CHECK IF REGISTER B = 0 WE ARE DONE (2nd CHECK OUTPUT F is ALL 0s (zp_bar))
// ALSO LOAD TEMP A WITH INPUT B
ALU_DEST <= 3'b110; // TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b11010; // B
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // INPUT_B, X
BOP <= 4'b1101; // !ZP (all O's from F)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hC; MICRO_AD_LOW <= 4'h7; // C7
end
8'hC4: begin // TEMP_REGISTER_A -1 => TEMP_REGISTER_A (WE NEED TO SET UP THE COUNTER WITH 1 LESS - TRUST ME)
ALU_DEST <= 3'b010; // F_TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01111; // A_MINUS_1
B_SOURCE <= 1'b0; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
// -------------------------------------------------------------------------------------
// OK - LETS KEEP ADDING A FOR HOW MANY TIMES OF B
8'hC5: begin // REGISTER_A + TEMP_REGISTER_B => TEMP_REGISTER_B
ALU_DEST <= 3'b101; // TB
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01001; // A_PLUS_B
B_SOURCE <= 1'b0; A_SOURCE<= 1'b1; // TEMP_B, INPUT_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hC6: begin // DECREMENT TEMP_REGISTER_A AND CHECK FOR 0 IN REGISTER_F
ALU_DEST <= 3'b010; // F_TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01111; // A_MINUS_1
B_SOURCE <= 1'b0; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0101; // ZP (all O's from F)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hC; MICRO_AD_LOW <= 4'h5; // C5
end
// --------------------------------------------------------------------------------------
8'hC7: begin // WAIT FOR GO TO BE RELEASED
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b11010; // B
B_SOURCE <= 1'b0; A_SOURCE<= 1'b0; // TEMP_B, X
BOP <= 4'b1100; // !GO_BAR
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hC; MICRO_AD_LOW <= 4'h7; // C7 (LOOP)
end
8'hC8: begin // GOTO RESET - FLASH 00
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hD; // OD (TO RESET)
end
// 8'hD1 - OPCODE 1101 *********************************************************************************
// 8'hE1 - OPCODE 1110 - DIVIDE ************************************************************************
8'hE1: begin // LOAD DIVIDEND INTO TEMP_REGISTER_A
ALU_DEST <= 3'b110; // TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, INPUT_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hE2: begin // CHECK FOR OVERFLOW - is DIVIDEND EQUAL TOO OR HIGHER THAN DIVISOR - HENCE, SUBTRACT AND LOOK AT C8 (COOL TRICK)
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b1; // CARRY (We need this for the equal too)
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b0011; // C8 (If it's 1 ABORT - ELSE CONTINUE)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hF; MICRO_AD_LOW <= 4'h0; // F0 (ABORT)
end
// --------------------------------------------------------------------------------------
// NOW LETS DO THE LOOP 4 TIMES - WE DON'T HAVE A COUNT SO WE JUST COPY/PASTE
// FIRST LOOP
8'hE3: begin // SHIFT DIVIDEND TEMP_REGISTER_A LEFT
ALU_DEST <= 3'b110; // TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01100; // A PLUS A (bit shift)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hE4: begin // CHECK is DIVIDEND EQUAL TOO OR HIGHER THAN DIVISOR - HENCE, SUBTRACT AND LOOK AT C8 (COOL TRICK)
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b1; // CARRY (We need this for the equal too)
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b1011; // !C8 (If it's 0 THEN JUMP TO 2nd LOOP - ELSE CONTINUE)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hE; MICRO_AD_LOW <= 4'h7; // E7 JUMP TO SECOND LOOP
end
8'hE5: begin // DIVIDEND = DIVIDEND - DIVISOR
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1 (MUST HAVE CARRY)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hE6: begin // ADD ONE TO DIVIDEND
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
// SECOND LOOP
8'hE7: begin // SHIFT DIVIDEND TEMP_REGISTER_A LEFT
ALU_DEST <= 3'b110; // TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01100; // A PLUS A (bit shift)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hE8: begin // CHECK is DIVIDEND EQUAL TOO OR HIGHER THAN DIVISOR - HENCE, SUBTRACT AND LOOK AT C8 (COOL TRICK)
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b1; // CARRY (We need this for the equal too)
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b1011; // !C8 (If it's 0 THEN JUMP TO 3rd LOOP - ELSE CONTINUE)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hE; MICRO_AD_LOW <= 4'hB; // EB JUMP TO THIRD LOOP
end
8'hE9: begin // DIVIDEND = DIVIDEND - DIVISOR
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1 (MUST HAVE CARRY)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hEA: begin // ADD ONE TO DIVIDEND
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // 1
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
// THRID LOOP
8'hEB: begin // SHIFT DIVIDEND TEMP_REGISTER_A LEFT
ALU_DEST <= 3'b110; // TA
CIN <= 1'b0; // NO_CARRY
ALU_FUNC <= 5'b01100; // A PLUS A (bit shift)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hEC: begin // CHECK is DIVIDEND EQUAL TOO OR HIGHER THAN DIVISOR - HENCE, SUBTRACT AND LOOK AT C8 (COOL TRICK)
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b1; // CARRY (We need this for the equal too)
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b1011; // !C8 (If it's 0 THEN JUMP TO END - ELSE CONTINUE)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hE; MICRO_AD_LOW <= 4'hF; // EF JUMP TO END
end
8'hED: begin // DIVIDEND = DIVIDEND - DIVISOR
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00110; // A_MINUS_B_MINUS_1 (MUST HAVE CARRY)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // INPUT_B, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hEE: begin // ADD ONE TO DIVIDEND
ALU_DEST <= 3'b110; // TA
CIN <= 1'b1; // CARRY
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
// LOOP DONE JUMP TO END
8'hEF: begin // WRITE TEMP_REGISTER_A to F AND JUMP TO END
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b0; A_SOURCE<= 1'b0; // X, TEMP_A
BOP <= 4'b1001; // BRANCH ALWAYS
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hF; MICRO_AD_LOW <= 4'h1; // F1
end
// --------------------------------------------------------------------------------------
8'hF0: begin // PART OF ABORT - WRIE ALL 1's to F
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b0; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
// --------------------------------------------------------------------------------------
8'hF1: begin // WAIT FOR GO TO BE RELEASED
ALU_DEST <= 3'b111; // NONE (DEFAULT)
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b00000; // A
B_SOURCE <= 1'b0; A_SOURCE<= 1'b0; // X, X
BOP <= 4'b1100; // !GO_BAR
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hF; MICRO_AD_LOW <= 4'h1; // F1 (LOOP)
end
8'hF2: begin // GOTO RESET - FLASH 00
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'hD; // OD (TO RESET)
end
// 8'hF1 - OPCODE 1111 *********************************************************************************
// NOT USABLE - THIS IS PART OF DIVIDE AND JAM
// 8'hFF - JAM *****************************************************************************************
// WHEN JAM INPUT ENABLED - JUST FLASH FF A FEW TIMES, WHY? FUN FUN
8'hFF: begin // FLASH 1 - WILL HOLD HERE AS LONG AS JAM IS ENABLED
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'hF; MICRO_AD_LOW <= 4'h6; // F6
end
8'hF6: begin // FLASH 0
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hF7: begin // FLASH 1
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hF8: begin // FLASH 0
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hF9: begin // FLASH 1
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hFA: begin // FLASH 0
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hFB: begin // FLASH 1
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hFC: begin // FLASH 0
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hFD: begin // FLASH 1
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b0110; // COUNT (DEFAULT)
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // XX
end
8'hFE: begin // FLASH 0
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b10011; // O
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // 00 (TO START OF RESET)
end
// DEFAULT *********************************************************************************************
default: begin // KICK BACK TO START OF RESET
ALU_DEST <= 3'b011; // F
CIN <= 1'b0; // NO_CARRY (DEFAULT)
ALU_FUNC <= 5'b11100; // 1 (DEFAULT)
B_SOURCE <= 1'b1; A_SOURCE<= 1'b1; // X, X
BOP <= 4'b1110; // BRANCH
COUNT <= 1'b1; // COUNT_IF_NO_LD
MICRO_AD_HIGH <= 4'h0; MICRO_AD_LOW <= 4'h0; // 00 (TO START OF RESET)
end
endcase
end
endmodule |
module ta377_bar(
input EN_BAR, //
input CLK, //
input [7:0] D, //
output [7:0] Q //
);
assign EN = ~EN_BAR;
// 8-bit register, clock enable
// Replaced ta377 in THESIS with jeff_74x377
jeff_74x377_structural U1 (
.en_bar(EN_BAR),
.clk(CLK),
.d0(D[0]),
.d1(D[1]),
.d2(D[2]),
.d3(D[3]),
.d4(D[4]),
.d5(D[5]),
.d6(D[6]),
.d7(D[7]),
.q0(Q[0]),
.q1(Q[1]),
.q2(Q[2]),
.q3(Q[3]),
.q4(Q[4]),
.q5(Q[5]),
.q6(Q[6]),
.q7(Q[7])
);
endmodule |
module ta181_bar(
input A3_BAR, A2_BAR, A1_BAR, A0_BAR, // WORD 1
input B3_BAR, B2_BAR, B1_BAR, B0_BAR, // WORD 2
input S3, S2, S1, S0, // FUNCTION SELECT
input M, // MODE: 0 is arithmetic, 1 is logic
input CI, // CARRY IN
output F3_BAR, F2_BAR, F1_BAR, F0_BAR, // OUTPUT
output CO, // CARRY OUT
output AEQB, // WHEN A = B
output P_BAR, // PROPAGATE - I don't use this
output G_BAR // GENERATE - I don't use this
);
// WIRES REMOVED TO KEEP ALU POSITIVE
// wire A0_SIG, A1_SIG, A2_SIG, A3_SIG;
// wire B0_SIG, B1_SIG, B2_SIG, B3_SIG;
// wire F0_SIG, F1_SIG, F2_SIG, F3_SIG;
assign CO = ~CO_BAR; // NOT IN THESIS
assign CI_BAR = ~CI; // NOT IN THESIS
// 4-bit arithmetic logic unit and function generator
// Replaced ta181 in THESIS with jeff_74x181
jeff_74x181 U1 (
.a3(A3_BAR),
.a2(A2_BAR),
.a1(A1_BAR),
.a0(A0_BAR),
.b3(B3_BAR),
.b2(B2_BAR),
.b1(B1_BAR),
.b0(B0_BAR),
.s3(S3),
.s2(S2),
.s1(S1),
.s0(S0),
.m(M),
.ci_bar(CI_BAR),
.f3(F3_BAR),
.f2(F2_BAR),
.f1(F1_BAR),
.f0(F0_BAR),
.co_bar(CO_BAR),
.aeqb(AEQB),
.x(P_BAR),
.y(G_BAR)
);
//not1 INV1 (.a(A3_BAR), .y(A3_SIG)); // REMOVED THIS TO KEEP IT POSTITVE
//not1 INV2 (.a(A2_BAR), .y(A2_SIG));
//not1 INV3 (.a(A1_BAR), .y(A1_SIG));
//not1 INV4 (.a(A0_BAR), .y(A0_SIG));
//not1 INV5 (.a(B3_BAR), .y(B3_SIG));
//not1 INV6 (.a(B2_BAR), .y(B2_SIG));
//not1 INV7 (.a(B1_BAR), .y(B1_SIG));
//not1 INV8 (.a(B0_BAR), .y(B0_SIG));
//not1 INV9 (.a(F3_SIG), .y(F3_BAR));
//not1 INV10 (.a(F2_SIG), .y(F2_BAR));
//not1 INV11 (.a(F1_SIG), .y(F1_BAR));
//not1 INV12 (.a(F0_SIG), .y(F0_BAR));
endmodule |
module zp_bit (
input [7:0] F8, //
output ZP_BAR //
);
wire [3:0] W;
// Replaced nor2 in THESIS with Jeff's nor2
nor2_behavioral U1 (
.a(F8[0]),
.b(F8[1]),
.y(W[0])
);
nor2_behavioral U2 (
.a(F8[2]),
.b(F8[3]),
.y(W[1])
);
nor2_behavioral U3 (
.a(F8[4]),
.b(F8[5]),
.y(W[2])
);
nor2_behavioral U4 (
.a(F8[6]),
.b(F8[7]),
.y(W[3])
);
// Replaced nand4 in THESIS with Jeff's nand4
nand4_behavioral U5 (
.a(W[0]),
.b(W[1]),
.c(W[2]),
.d(W[3]),
.y(ZP_BAR)
);
endmodule |
module counter8(
input [3:0] COUNTER_IN_LOW, //
input [7:4] COUNTER_IN_HIGH, //
input MPC_LOAD_BAR, //
input RESET, //
input COUNT, //
input SYSTEM_CLK, //
output [7:0] COUNTER_OUT //
);
// WIRES
wire CARRY;
wire NOTHING;
// ASSIGN VALUES
assign HIGH = 1'b1;
// COUNTER1 - 4-bit synchronous counter
ta161_bar COUNTER1 (
.CLR_BAR(RESET),
.LD_BAR(MPC_LOAD_BAR),
.ENT(HIGH),
.ENP(COUNT),
.CLK(SYSTEM_CLK),
.A(COUNTER_IN_LOW[0]),
.B(COUNTER_IN_LOW[1]),
.C(COUNTER_IN_LOW[2]),
.D(COUNTER_IN_LOW[3]),
.QA(COUNTER_OUT[0]),
.QB(COUNTER_OUT[1]),
.QC(COUNTER_OUT[2]),
.QD(COUNTER_OUT[3]),
.RCO(CARRY)
);
// COUNTER2 - 4-bit synchronous counter
ta161_bar COUNTER2 (
.CLR_BAR(RESET),
.LD_BAR(MPC_LOAD_BAR),
.ENT(CARRY),
.ENP(COUNT),
.CLK(SYSTEM_CLK),
.A(COUNTER_IN_HIGH[4]),
.B(COUNTER_IN_HIGH[5]),
.C(COUNTER_IN_HIGH[6]),
.D(COUNTER_IN_HIGH[7]),
.QA(COUNTER_OUT[4]),
.QB(COUNTER_OUT[5]),
.QC(COUNTER_OUT[6]),
.QD(COUNTER_OUT[7]),
.RCO(NOTHING)
);
endmodule |
module register_ab8(
input [7:0] DATA_IN, //
input SYSTEM_CLK, //
input ENABLE_CLK, //
output [7:0] DATA_OUT //
);
// WIRES
wire W1;
// ASSIGN VALUES
assign LOW = 1'b0;
// OR GATE
// Replaced or2 in THESIS with jeff's or2
or2_behavioral OR1 (
.a(SYSTEM_CLK),
.b(ENABLE_CLK),
.y(W1)
);
// 8-bit register, clock enable
ta377_bar DFFS (
.EN_BAR(LOW),
.CLK(W1),
.D(DATA_IN),
.Q(DATA_OUT)
);
endmodule |
module ta157_4(
input [3:0] A4, //
input [3:0] B4, //
input S, //
input EN_BAR, //
output [3:0] Y4 //
);
// Replaced ta157_bar and ta157 in THESIS with jeff_74x157
assign EN = ~EN_BAR;
// Quad 2x1 multiplexers
jeff_74x157_behavioral MUX0 (
.a(A4),
.b(B4),
.s(S),
.en(EN),
.y(Y4)
);
endmodule |
module ta151_bar(
input D0, //
input D1, //
input D2, //
input D3, //
input D4, //
input D5, //
input D6, //
input D7, //
input A, //
input B, //
input C, //
input EN_BAR, //
output Y, //
output W //
);
assign EN = ~EN_BAR;
// 8-line to 1-line data selector/multiplexer
// Replaced ta151 in THESIS with jeff_74x151
jeff_74x151_behavioral U1 (
.d0(D0),
.d1(D1),
.d2(D2),
.d3(D3),
.d4(D4),
.d5(D5),
.d6(D6),
.d7(D7),
.a(A),
.b(B),
.c(C),
.en(EN),
.y(Y),
.w(W)
);
endmodule |
module ta161_bar (
input CLR_BAR, // CLEAR
input LD_BAR, // LOAD
input ENT, // ENABLE T
input ENP, // ENABLE P
input CLK, // CLK
input A, B, C, D, // DATA IN
output QA, QB, QC, QD, // DATA OUT
output RCO // RIPPLE CARRY OUTPUT
);
// 4-bit synchronous counter
// Replaced ta161 in THESIS with jeff_74x161
jeff_74x161 U1 (
.clr_bar(CLR_BAR),
.ld_bar(LD_BAR),
.ent(ENT),
.enp(ENP),
.clk(CLK),
.a(A),
.b(B),
.c(C),
.d(D),
.qa(QA),
.qb(QB),
.qc(QC),
.qd(QD),
.rco(RCO)
);
endmodule |
module ta157_8(
input [7:0] A8, //
input [7:0] B8, //
input S, //
input EN_BAR, //
output [7:0] Y8 //
);
// Replaced ta157_bar and ta157 in THESIS with jeff_74x157
assign EN = ~EN_BAR;
// Lower 4 bits - Quad 2x1 multiplexers
jeff_74x157_behavioral MUX0 (
.a(A8[3:0]),
.b(B8[3:0]),
.s(S),
.en(EN),
.y(Y8[3:0])
);
// Upper 4 bits - Quad 2x1 multiplexers
jeff_74x157_behavioral MUX1 (
.a(A8[7:4]),
.b(B8[7:4]),
.s(S),
.en(EN),
.y(Y8[7:4])
);
endmodule |
module opcodedec (
input [3:0] OPCODE, //
input [7:4] MW_AD_HIGH, //
input [12:9] MW_BOP, //
output [7:4] TO_COUNTER, //
output EIL_BAR //
);
// WIRES
wire W1;
// ASSIGN VALUES
assign LOW = 1'b0;
assign EIL_BAR = W1;
// Four (2x1) multiplexers
ta157_4 U1 (
.A4(OPCODE),
.B4(MW_AD_HIGH),
.S(W1),
.EN_BAR(LOW),
.Y4(TO_COUNTER)
);
// FOUR INPUT NAND GATE
// Replaced nand4 in THESIS with jeff's nand4
nand4_behavioral U2 (
.a(MW_BOP[9]),
.b(MW_BOP[10]),
.c(MW_BOP[11]),
.d(MW_BOP[12]),
.y(W1)
);
endmodule |
module alu (
input [7:0] IN_A, // WORD 1
input [7:0] IN_B, // WORD 2
input CIN, // CARRY IN
input [19:15] ALU_FUNC, // FUNCTION SELECT (19 is MODE: 0 is arithmetic, 1 is logic)
output [7:0] OUT8, // OUTPUT
output C4, // CARRY OUT
output C8, // CARRY OUT
output Z // WHEN A = B
);
//WIRES
wire CARRY;
wire NOTHING1, NOTHING2;
wire NOTHING3, NOTHING4;
wire AEQB1, AEQB2;
assign C4 = CARRY;
ta181_bar U1 (
.A3_BAR(IN_A[3]),
.A2_BAR(IN_A[2]),
.A1_BAR(IN_A[1]),
.A0_BAR(IN_A[0]),
.B3_BAR(IN_B[3]),
.B2_BAR(IN_B[2]),
.B1_BAR(IN_B[1]),
.B0_BAR(IN_B[0]),
.S3(ALU_FUNC[18]),
.S2(ALU_FUNC[17]),
.S1(ALU_FUNC[16]),
.S0(ALU_FUNC[15]),
.M(ALU_FUNC[19]),
.CI(CIN),
.F3_BAR(OUT8[3]),
.F2_BAR(OUT8[2]),
.F1_BAR(OUT8[1]),
.F0_BAR(OUT8[0]),
.CO(CARRY),
.AEQB(AEQB1),
.P_BAR(NOTHING1),
.G_BAR(NOTHING2)
);
ta181_bar U2 (
.A3_BAR(IN_A[7]),
.A2_BAR(IN_A[6]),
.A1_BAR(IN_A[5]),
.A0_BAR(IN_A[4]),
.B3_BAR(IN_B[7]),
.B2_BAR(IN_B[6]),
.B1_BAR(IN_B[5]),
.B0_BAR(IN_B[4]),
.S3(ALU_FUNC[18]),
.S2(ALU_FUNC[17]),
.S1(ALU_FUNC[16]),
.S0(ALU_FUNC[15]),
.M(ALU_FUNC[19]),
.CI(CARRY),
.F3_BAR(OUT8[7]),
.F2_BAR(OUT8[6]),
.F1_BAR(OUT8[5]),
.F0_BAR(OUT8[4]),
.CO(C8),
.AEQB(AEQB2),
.P_BAR(NOTHING3),
.G_BAR(NOTHING4)
);
and2_behavioral AND1 (
.a(AEQB1),
.b(AEQB2),
.y(Z)
);
endmodule |
module control (
input [3:0] OPCODE, //
input GO_BAR, //
input RESET, //
input JAM, //
input SYSTEM_CLK, //
input [3:0] STATUS_BITS, //
input [23:0] MW, //
output [7:0] MICROADDRESS, //
output [23:13] CONTROL_BITS, // PASS THREW FOR MW[23:13]
output EIL_BAR //
);
// WIRES
wire [3:0] MICRO_AD_LOW;
wire [7:4] MICRO_AD_HIGH;
wire COUNT;
wire [12:9] BOP;
wire [7:4] COUNTER_IN_HIGH_SIG;
wire [7:0] BUFFER_IN;
wire MPC_LOAD_BAR;
wire COND_OUT;
wire HIGH;
wire [7:0] HIGH8;
wire LOW;
wire NOTHING;
// BREAK UP THE MICROWORD (MW) INTO FIELDS
assign MICRO_AD_LOW = MW[3:0];
assign MICRO_AD_HIGH = MW[7:4];
assign COUNT = MW[8];
assign BOP = MW[12:9];
assign CONTROL_BITS = MW[23:13];
// ASSIGN VALUES
assign HIGH = 1'b1;
assign HIGH8 = 8'b11111111;
assign LOW = 1'b0;
// COUNTER8 SECTION
counter8 COUNTER_8 (
.COUNTER_IN_LOW(MICRO_AD_LOW),
.COUNTER_IN_HIGH(COUNTER_IN_HIGH_SIG),
.MPC_LOAD_BAR(MPC_LOAD_BAR),
.RESET(RESET),
.COUNT(COUNT),
.SYSTEM_CLK(SYSTEM_CLK),
.COUNTER_OUT(BUFFER_IN)
);
// MUX8 SECTION - Eight (2x1) multiplexers
ta157_8 MUX8 (
.A8(BUFFER_IN),
.B8(HIGH8),
.S(JAM),
.EN_BAR(LOW),
.Y8(MICROADDRESS)
);
// OPCODEDEC SECTION
opcodedec OPCODEDEC0 (
.OPCODE(OPCODE),
.MW_AD_HIGH(MICRO_AD_HIGH),
.MW_BOP(BOP),
.TO_COUNTER(COUNTER_IN_HIGH_SIG),
.EIL_BAR(EIL_BAR)
);
// COND_SELECT SECTION
ta151_bar COND_SELECT (
.D0(STATUS_BITS[2]),
.D1(LOW),
.D2(STATUS_BITS[0]),
.D3(STATUS_BITS[1]),
.D4(GO_BAR),
.D5(STATUS_BITS[3]),
.D6(LOW),
.D7(LOW),
.A(BOP[9]),
.B(BOP[10]),
.C(BOP[11]),
.EN_BAR(LOW),
.Y(NOTHING),
.W(COND_OUT)
);
// Replaced xor2 in THESIS with jeff's xor2
xor2_behavioral XOR_2 (
.a(BOP[12]),
.b(COND_OUT),
.y(MPC_LOAD_BAR)
);
endmodule |
module processor (
input [7:0] DATA_IN_A, //
input [7:0] DATA_IN_B, //
input SYSTEM_CLK, //
input EIL_BAR, //
input [23:13] CONTROL_BITS, //
output [3:0] STATUS_BITS, //
output [7:0] DATA_OUT //
);
// WIRES
wire [7:0] DATA_OUT_A;
wire [7:0] DATA_OUT_B;
wire [7:0] DATA_OUT_TA;
wire [7:0] DATA_OUT_TB;
wire [7:0] ALU_IN_A;
wire [7:0] ALU_IN_B;
wire [7:0] ALU_OUT;
wire A_SOURCE;
wire B_SOURCE;
wire [19:15] ALU_FUNC;
wire CIN;
wire [23:21] ALU_DEST;
wire [7:0] IN_ZP;
wire LOW;
// BREAK UP THE CONTROL_BITS INTO FIELDS
assign A_SOURCE = CONTROL_BITS[13];
assign B_SOURCE = CONTROL_BITS[14];
assign ALU_FUNC = CONTROL_BITS[19:15];
assign CIN = CONTROL_BITS[20];
assign ALU_DEST = CONTROL_BITS[23:21];
// ASSIGN VALUES
assign LOW = 1'b0;
assign DATA_OUT = IN_ZP;
// REGISTERA SECTION
register_ab8 REGISTERA (
.DATA_IN(DATA_IN_A),
.SYSTEM_CLK(SYSTEM_CLK),
.ENABLE_CLK(EIL_BAR),
.DATA_OUT(DATA_OUT_A)
);
// REGISTERB SECTION
register_ab8 REGISTERB (
.DATA_IN(DATA_IN_B),
.SYSTEM_CLK(SYSTEM_CLK),
.ENABLE_CLK(EIL_BAR),
.DATA_OUT(DATA_OUT_B)
);
// TEMP_REGISTER_A SECTION
register_ab8 TEMP_REGISTER_A (
.DATA_IN(ALU_OUT),
.SYSTEM_CLK(SYSTEM_CLK),
.ENABLE_CLK(ALU_DEST[21]),
.DATA_OUT(DATA_OUT_TA)
);
// TEMP_REGISTER_B SECTION
register_ab8 TEMP_REGISTER_B (
.DATA_IN(ALU_OUT),
.SYSTEM_CLK(SYSTEM_CLK),
.ENABLE_CLK(ALU_DEST[22]),
.DATA_OUT(DATA_OUT_TB)
);
// MUX_A SECTION
ta157_8 MUX_A (
.A8(DATA_OUT_TA),
.B8(DATA_OUT_A),
.S(A_SOURCE),
.EN_BAR(LOW),
.Y8(ALU_IN_A)
);
// MUX_B SECTION
ta157_8 MUX_B (
.A8(DATA_OUT_TB),
.B8(DATA_OUT_B),
.S(B_SOURCE),
.EN_BAR(LOW),
.Y8(ALU_IN_B)
);
// ALU1 SECTION
alu ALU1 (
.IN_A(ALU_IN_A),
.IN_B(ALU_IN_B),
.CIN(CIN),
.ALU_FUNC(ALU_FUNC),
.OUT8(ALU_OUT),
.C4(STATUS_BITS[0]),
.C8(STATUS_BITS[1]),
.Z(STATUS_BITS[2])
);
// F_REGISTER SECTION
register_ab8 F_REGISTER (
.DATA_IN(ALU_OUT),
.SYSTEM_CLK(SYSTEM_CLK),
.ENABLE_CLK(ALU_DEST[23]),
.DATA_OUT(IN_ZP)
);
// ZP_BIT1 SECTION
zp_bit ZP_BIT1 (
.F8(IN_ZP),
.ZP_BAR(STATUS_BITS[3])
);
endmodule |
module osc2(
input clk, // 48.0MHz CPU clock
input reset, // Low-true reset
// external toggle switch inputs
input [1:0] range, mod1, mod2,
// SYNC input
input sync,
// PWM LED outputs
output pwm_r, pwm_g, pwm_b,
// Rate LED output
output rate,
// SPI ADC interface
output adc_cs, adc_si, adc_clk,
input adc_so,
// Differentiall PDM outputs
output pdm_l_p, pdm_l_n, pdm_r_p, pdm_r_n,
// diagnostic
output [1:0] diag,
output [11:0] a0, a1, a2, a3
);
// Sample rate enable
reg [2:0] clk_cnt;
reg ena;
always @(posedge clk)
if(reset)
begin
clk_cnt <= 3'b000;
ena <= 1'b1;
end
else
begin
clk_cnt <= clk_cnt + 3'b001;
if(clk_cnt == 3'b010)
begin
clk_cnt <= 3'b000;
ena <= 1'b1;
end
else
ena <= 1'b0;
end
// ADC
//wire [11:0] a0, a1, a2, a3;
wire a0_v, a1_v, a2_v, a3_v;
adc u_adc(
.clk(clk),
.reset(reset),
.adc_cs(adc_cs),
.adc_si(adc_si),
.adc_so(adc_so),
.adc_clko(adc_clk),
.a0(a0), // CV1
.a1(a1), // CV3
.a2(a2), // CV2
.a3(a3), // 1V/Oct
.a0_v(a0_v),
.a1_v(a1_v),
.a2_v(a2_v),
.a3_v(a3_v)
);
// PWMs
pwm u_pwm_r(
.clk(clk),
.val(a0[11:4]),
.pwm(pwm_r)
);
pwm u_pwm_g(
.clk(clk),
.val(a1[11:4]),
.pwm(pwm_g)
);
pwm u_pwm_b(
.clk(clk),
.val(a2[11:4]),
.pwm(pwm_b)
);
// Expo Calculation
wire [31:0] frq;
expo_calc u_expo(
.clk(clk),
.reset(reset),
.range(range),
.in(a3),
.in_v(a3_v),
.out(frq)
);
// detect falling edge of sync
reg sync_d, sync_edge;
always @(posedge clk)
if(ena)
begin
sync_d <= sync;
sync_edge = !sync & sync_d;
end
// NCO
reg [31:0] phs;
always @(posedge clk)
if(reset | sync_edge)
phs <= 0;
else if(ena)
phs <= phs + frq;
// Rate output
assign rate = phs[31];
// waveforms
wire signed [15:0] saw = phs[31:16];
wire signed [15:0] pwm;
wire signed [15:0] sin;
// square / pulse wave
wire pwm_v;
pulse_wave u_pulse(
.clk(clk),
.ena(ena),
.phs(phs),
.width(a1),
.out(pwm),
.valid(pwm_v)
);
// sine wave
sine u_sine(
.clk(clk),
.reset(reset),
.ena(ena),
.phs(phs),
.out(sin),
.valid()
);
// select the outputs
reg signed [15:0] src_l, src_r;
always @(posedge clk)
if(ena)
begin
case(mod1)
2'b00: src_l = sin;
2'b01: src_l = saw;
2'b10: src_l = pwm;
default: src_l = sin;
endcase
case(mod2)
2'b00: src_r = sin;
2'b01: src_r = saw;
2'b10: src_r = pwm;
default: src_r = sin;
endcase
end
// PDM outputs
pdm u_pdm_l(
.clk(clk),
.reset(reset),
.ena(ena),
.in(src_l),
.pdm_p(pdm_l_p),
.pdm_n(pdm_l_n)
);
pdm u_pdm_r(
.clk(clk),
.reset(reset),
.ena(ena),
.in(src_r),
.pdm_p(pdm_r_p),
.pdm_n(pdm_r_n)
);
// diagnostic
assign diag[0] = rate;
assign diag[1] = 1'b0;
endmodule |
module adc(
input clk, // 48MHz CPU clock
input reset, // Low-true reset
output reg adc_cs, adc_si,
output adc_clko,
input adc_so,
output reg [11:0] a0, a1, a2, a3,
output reg a0_v, a1_v, a2_v, a3_v
);
// divide 48MHz clock down to 8MHz max that ADC allows
reg clk_ena, clk_ena_180, adc_clk;
reg [2:0] clk_div;
always @(posedge clk)
if(reset)
begin
clk_div <= 3'd0;
clk_ena <= 1'b1;
clk_ena_180 <= 1'b0;
adc_clk <= 1'b1;
end
else
begin
clk_div <= clk_div + 3'd1;
clk_ena <= 1'b0;
clk_ena_180 <= 1'b0;
if(clk_div == 3'd0)
adc_clk <= 1'b1;
if(clk_div == 3'd2)
clk_ena_180 <= 1'b1;
if(clk_div == 3'd3)
adc_clk <= 1'b0;
if(clk_div == 3'd5)
begin
clk_ena <= 1'b1;
clk_div <= 3'd0;
end
end
// state machine generates cs, si (input to ADC) and assembles result
reg [3:0] adc_cnt;
reg [1:0] adc_chl, adc_pchl, data_chl;
reg [11:0] sreg, data_curr, data_prev;
reg data_valid;
always @(posedge clk)
if(reset)
begin
adc_cs <= 1'b1;
adc_si <= 1'b0;
adc_cnt <= 4'h0;
adc_chl <= 2'b11;
adc_pchl <= 2'b10;
sreg <= 12'h000;
data_curr <= 12'h000;
data_prev <= 12'h000;
data_chl <= 2'b00;
data_valid <= 1'b0;
end
else
begin
// count always advances
if(clk_ena)
adc_cnt <= adc_cnt + 1;
// channel advances at end of cycle
if(clk_ena && (adc_cnt == 4'hf))
begin
adc_chl <= adc_chl + 1;
adc_pchl <= adc_chl;
end
// cs drops after first count cycle
if(clk_ena_180 && (adc_cnt == 4'hf) && adc_cs)
adc_cs <= 1'b0;
// si shifts out chl addr on cycles 3,4 (bits 4, 3)
if(clk_ena)
case(adc_cnt)
4'h1: adc_si <= 1'b1;
4'h2: adc_si <= adc_chl[1];
4'h3: adc_si <= adc_chl[0];
default: adc_si <= 1'b0;
endcase
// input shift register
if(clk_ena_180 & (adc_cnt[3:2]!=2'b00))
sreg[11:0] <= {sreg[10:0],adc_so};
// output holding registers with inversion
if(clk_ena_180 && (adc_cnt == 4'hf))
begin
data_curr <= ~{sreg[10:0],adc_so};
data_prev <= data_curr;
data_chl <= adc_pchl;
data_valid <= 1'b1;
end
else
data_valid <= 1'b0;
end
// crosstalk correction pipeline
reg [2:0] cena_pipe;
reg signed [12:0] cdiff, csum;
always @(posedge clk)
if(reset)
begin
cena_pipe <= 3'b000;
cdiff <= 12'h000;
csum <= 12'h000;
end
else
begin
// pipelined enable from previous valid
cena_pipe <= {cena_pipe[1:0],data_valid};
// compute difference
if(data_valid)
cdiff <= $signed({1'b0,data_curr}) - $signed({1'b0,data_prev});
// add scaled difference to current
if(cena_pipe[0])
csum <= $signed({1'b0,data_curr}) + (cdiff >>> 9);
end
// saturate to proper limits
reg [11:0] corrected;
always @(*)
if(csum[12])
begin
if(data_curr[11])
corrected = 12'hfff;
else
corrected = 12'h000;
end
else
corrected = csum[11:0];
wire corrected_valid = cena_pipe[1];
// demux and final output result
always @(posedge clk)
if(reset)
begin
a0 <= 12'd0;
a1 <= 12'd0;
a2 <= 12'd0;
a3 <= 12'd0;
a0_v <= 1'b0;
a1_v <= 1'b0;
a2_v <= 1'b0;
a3_v <= 1'b0;
end
else
begin
// holding regs
if(corrected_valid)
case(data_chl)
2'b00: a0 <= corrected;
2'b01: a1 <= corrected;
2'b10: a2 <= corrected;
2'b11: a3 <= corrected;
endcase
// output valids
if(corrected_valid)
case(adc_pchl)
2'b00: a0_v <= 1'b1;
2'b01: a1_v <= 1'b1;
2'b10: a2_v <= 1'b1;
2'b11: a3_v <= 1'b1;
endcase
else
begin
a0_v <= 1'b0;
a1_v <= 1'b0;
a2_v <= 1'b0;
a3_v <= 1'b0;
end
end
// disable adc_clko when cs high
assign adc_clko = adc_clk | adc_cs;
endmodule |
module pwm(
input clk,
input [7:0] val,
output reg pwm
);
reg [7:0] cnt;
initial
cnt = 0;
always @(posedge clk)
begin
cnt <= cnt + 1;
pwm <= val > cnt;
end
endmodule |
module toggle3pos(
input [1:0] pkgpin, // raw pin input
output reg [1:0] out
);
always @(*)
case(pkgpin)
2'b00: out = 2'b11; // can't happen
2'b01: out = 2'b00; // top
2'b10: out = 2'b10; // bottom
2'b11: out = 2'b01; // center
endcase
endmodule |
module expo_calc(
input clk, // 16MHz CPU clock
input reset, // Low-true reset
input [1:0] range, // range select
input [11:0] in, // 1V/Oct input
input in_v, // input valid flag
output reg [31:0] out // frequency output
);
reg [3:0] inpipe;
reg [27:0] inscl;
reg [34:0] pout;
wire [7:0] addr = inscl[23:16];
wire [3:0] shf = inscl[27:24];
reg [15:0] LUT[255:0], LUT_reg;
initial
$readmemh("../src/expo.hex",LUT);
always @(posedge clk)
if(reset)
begin
inpipe <= 4'd0;
inscl <= 28'd0;
pout <= 32'd0;
out <= 32'd0;
end
else
begin
// pipeline the valid signal
inpipe <= {inpipe[2:0],in_v};
// scale the input
if(in_v)
inscl <= in * `ADC_cal;
// lookup table
if(inpipe[1])
LUT_reg <= LUT[addr];
// octave shifter
if(inpipe[2])
pout <= LUT_reg << shf;
// range shifter
if(inpipe[3])
case(range)
2'b00: out <= pout >>> 3;
2'b01: out <= pout >>> 9;
2'b10: out <= pout >>> 16;
default out <= pout >>> 3;
endcase
end
endmodule |
module pdm(
input clk, // system clock
input reset, // system reset
input ena, // systetm clock enable
input signed [15:0] in, // signed binary input
output pdm_p, pdm_n // differential pdm output
);
// convert input to offset binary
wire [15:0] ob = in ^ 16'h8000;
// 1st-order sigma-delta
reg [16:0] sd_acc;
always @(posedge clk)
if(reset)
sd_acc = 0;
else if(ena)
sd_acc <= {1'b0,sd_acc[15:0]} + {1'b0,ob};
`define EDGE_BAL
`ifdef EDGE_BAL
// balanced rising/falling edges - does it help distortion?
reg [2:0] ccnt;
reg out;
always @(posedge clk)
if(reset)
begin
ccnt <= 3'b000;
out <= 1'b0;
end
else
begin
if(ena)
begin
ccnt <= 3'b000;
out <= 1'b0;
end
else
begin
ccnt <= ccnt + 1;
case(ccnt)
3'b000: out <= 1'b1;
3'b001: out <= sd_acc[16];
default: out <= out;
endcase
end
end
wire oclk = clk;
`else
// simple output
wire out = sd_acc[16];
// clock for output reg
reg oclk;
always @(posedge clk)
oclk <= ena;
`endif
// Instantiate IO
SB_IO #(
.PIN_TYPE(6'b1001_01), // registered, enabled w/ simple input
.PULLUP(1'b0), // no pullup
.NEG_TRIGGER(1'b0), // positive edge
.IO_STANDARD("SB_LVCMOS")
) io_pdm_p(
.PACKAGE_PIN (pdm_p),
.LATCH_INPUT_VALUE (1'b0),
.CLOCK_ENABLE (1'b1),
.INPUT_CLK (1'b0),
.OUTPUT_CLK (oclk),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (out),
.D_OUT_1 (1'b0),
.D_IN_0 (),
.D_IN_1 ()
);
SB_IO #(
.PIN_TYPE(6'b1001_01), // registered, enabled w/ simple input
.PULLUP(1'b0), // no pullup
.NEG_TRIGGER(1'b0), // positive edge
.IO_STANDARD("SB_LVCMOS")
) io_pdm_n(
.PACKAGE_PIN (pdm_n),
.LATCH_INPUT_VALUE (1'b0),
.CLOCK_ENABLE (1'b1),
.INPUT_CLK (1'b0),
.OUTPUT_CLK (oclk),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (!out),
.D_OUT_1 (1'b0),
.D_IN_0 (),
.D_IN_1 ()
);
endmodule |
module diag_serial(
input clk, // 48MHz CPU clock
input reset, // Low-true reset
input [11:0] a0, a1, a2, a3,
output tx
);
// hard-coded bit-rate
localparam sym_rate = 115200;
localparam clk_freq = 48000000;
localparam sym_cnt = clk_freq / sym_rate;
localparam SCW = $clog2(sym_cnt);
wire [SCW-1:0] sym_cntr = sym_cnt;
// sequencing state machine
reg [1:0] chl;
reg [2:0] char;
reg [7:0] din;
reg [11:0] a_mux;
reg [3:0] nybble;
reg [7:0] digit;
reg tx_start;
wire tx_busy;
always @(posedge clk)
begin
if(reset)
begin
chl <= 2'b00;
char <= 3'b000;
din <= 2'h00;
tx_start <= 1'b0;
end
else
begin
// start next char
tx_start <= !tx_busy;
// advance state
if(!tx_start && !tx_busy)
begin
// choose char
case(char)
3'b000: din <= digit;
3'b001: din <= digit;
3'b010: din <= digit;
3'b011: din <= (chl == 3) ? 8'h0d : 8'h20;
3'b100: din <= (chl == 3) ? 8'h0a : 8'h20;
endcase
char <= char + 3'b001;
if(char == 3'b100)
begin
char <= 3'b000;
chl <= chl + 2'b01;
end
end
// choose channel
case(chl)
2'b00: a_mux <= a0;
2'b01: a_mux <= a1;
2'b10: a_mux <= a2;
2'b11: a_mux <= a3;
endcase
// choose nybble
case(char)
3'b000: nybble <= a_mux[11:8];
3'b001: nybble <= a_mux[7:4];
3'b010: nybble <= a_mux[3:0];
endcase
// convert nybble to hex
if(nybble > 4'h9)
digit = nybble + 8'd55;
else
digit = nybble + 8'd48;
end
end
// Transmitter
acia_tx #(
.SCW(SCW), // rate counter width
.sym_cnt(sym_cnt) // rate count value
)
my_tx(
.clk(clk), // system clock
.rst(reset), // system reset
.tx_dat(din), // transmit data byte
.tx_start(tx_start), // trigger transmission
.tx_serial(tx), // tx serial output
.tx_busy(tx_busy) // tx is active (not ready)
);
endmodule |
module sine(
input clk, // system clock
input reset, // system reset
input ena, // system clock enable
input [31:0] phs, // phase input
output signed [15:0] out, // wave output
output valid
);
// enable pipeline
reg [6:0] ena_pipe;
always @(posedge clk)
if(reset)
ena_pipe <= 6'b000;
else
ena_pipe <= {ena_pipe[6:0],ena};
// select interp components
reg [7:0] idx;
reg signed [15:0] interp;
always @(posedge clk)
if(ena_pipe[0])
begin
idx <= phs[31:24];
interp <= 16'h7fff - phs[23:9];
//interp <= 16'h7fff;
end
else if(ena_pipe[1])
begin
idx <= phs[31:24] + 8'h01;
interp <= {1'b0,phs[23:9]};
//interp <= 16'h0;
end
// sine lookup table
reg [15:0] sine_mem[255:0];
initial
$readmemh("../src/sine.hex",sine_mem);
// look up sine & delay interpolation
reg signed [15:0] interp_d;
reg signed [15:0] sin;
always @(posedge clk)
if(ena_pipe[1] | ena_pipe[2])
begin
sin <= sine_mem[idx];
interp_d <= interp;
end
// sum of products
reg signed [31:0] m;
always @(posedge clk)
if(ena_pipe[2] | ena_pipe[3])
m <= sin * interp_d;
reg signed [31:0] acc;
always @(posedge clk)
if(ena_pipe[2])
acc <= 32'd0;
else if(ena_pipe[3] | ena_pipe[4])
acc <= acc + m;
reg signed [15:0] out;
always @(posedge clk)
if(ena_pipe[5])
out <= acc[30:15];
assign valid = ena_pipe[6];
endmodule |
module pulse_wave(
input clk, // system clock
input ena, // system clock enable
input [31:0] phs, // phase input
input [11:0] width, // width input
output signed [15:0] out, // wave output
output valid
);
// compare threshold
reg signed [15:0] out;
reg valid;
always @(posedge clk)
begin
valid <= ena;
if(ena)
out <= (phs[31:20] > width) ? 16'h7fff : 16'h8001;
end
endmodule |
module tb_system;
reg clk;
reg reset;
reg rx;
wire tx;
reg [11:0] a0, a1, a2, a3;
wire [31:0] gp_out;
// 24 MHz clock source
always
#(2*10.4167) clk = ~clk;
// reset
initial
begin
`ifdef icarus
$dumpfile("tb_system.vcd");
$dumpvars;
`endif
// init regs
clk = 1'b0;
reset = 1'b1;
rx = 1'b1;
a0 = 12'h000;
a1 = 12'h000;
a2 = 12'h000;
a3 = 12'h000;
// release reset
#1000
reset = 1'b0;
`ifdef icarus
// stop after 1 sec
//#12000000 $finish;
#700000 $finish;
`endif
end
// Unit under test
system u_riscv(
.clk24(clk),
.reset(reset),
.RX(rx),
.TX(tx),
.gp_in0({20'h00000,a0}),
.gp_in1({20'h00000,a1}),
.gp_in2({20'h00000,a2}),
.gp_in3({20'h00000,a3}),
.gp_out(gp_out)
);
endmodule |
module up5k_osc_top(
// 12MHz clock osc
input clk_12,
// ADC SPI bus
output adc_cs, adc_si, adc_clk,
input adc_so,
// LEDs
output RGB0, RGB1, RGB2, // RGB LED outs
output LEDR, // discrete LED
// Differential PDM Audio
output pdm_l_p, pdm_l_n, pdm_r_p, pdm_r_n,
// Serial port
output tx,
output rx,
// SYNC input
input SYNC,
// toggle inputs
input [1:0] SW103, SW104, SW105, // mod1, range, mod2
// SPI Flash
output MEM_SPI_MOSI_IO0, MEM_SPI_SCLK, MEM_SPI_CS,
output MEM_SPI_WP_IO2, MEM_SPI_HLD_IO3,
input MEM_SPI_MISO_IO1
);
//------------------------------
// Clock PLL
//------------------------------
// Fin=12, FoutA=24, FoutB=48
wire clk, clk24, pll_lock;
SB_PLL40_2F_PAD #(
.DIVR(4'b0000),
.DIVF(7'b0111111), // 24/48
.DIVQ(3'b100),
.FILTER_RANGE(3'b001),
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT_PORTA("GENCLK_HALF"),
.PLLOUT_SELECT_PORTB("GENCLK"),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0)
)
pll_inst (
.PACKAGEPIN(clk_12),
.PLLOUTCOREA(clk24),
.PLLOUTGLOBALA(),
.PLLOUTCOREB(clk),
.PLLOUTGLOBALB(),
.EXTFEEDBACK(),
.DYNAMICDELAY(8'h00),
.RESETB(1'b1),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(pll_lock),
.SDI(),
.SDO(),
.SCLK()
);
//------------------------------
// reset generator waits > 10us
//------------------------------
reg [8:0] reset_cnt;
reg reset, reset24;
always @(posedge clk or negedge pll_lock)
begin
if(!pll_lock)
begin
reset_cnt <= 9'h000;
reset <= 1'b1;
end
else
begin
if(reset_cnt != 9'h1ff)
begin
reset_cnt <= reset_cnt + 9'h001;
reset <= 1'b1;
end
else
reset <= 1'b0;
end
end
always @(posedge clk24 or negedge pll_lock)
if(!pll_lock)
reset24 <= 1'b1;
else
reset24 <= reset;
//------------------------------
// Instantiate RISC-V system
//------------------------------
wire [31:0] gpo;
wire sys_diag;
system u_riscv(
.clk24(clk24),
.reset(reset24),
.RX(rx),
.TX(tx),
.gp_in0(SW103),
.gp_in1(SW104),
.gp_in2(SW105),
.gp_in3(SYNC),
.gp_out(gpo),
.diag(sys_diag)
);
//------------------------------
// Instantiate RGB DRV
//------------------------------
SB_RGBA_DRV #(
.RGB0_CURRENT("0b000001"),
.RGB1_CURRENT("0b000001"),
.RGB2_CURRENT("0b000001")
) RGBA_DRIVER (
.CURREN (1'b1),
.RGBLEDEN (1'b1), // Enable current for all 3 RGB LED pins
.RGB0PWM (gpo[17]), // Input to drive RGB0 - from LEDD HardIP
.RGB1PWM (gpo[18]), // Input to drive RGB1 - from LEDD HardIP
.RGB2PWM (gpo[19]), // Input to drive RGB2 - from LEDD HardIP
.RGB0 (RGB0),
.RGB1 (RGB1),
.RGB2 (RGB2)
);
assign LEDR = gpo[20];
endmodule |
module system(
// clock, reset
input clk24,
reset,
// serial
input RX,
output TX,
// GPIO
input [31:0] gp_in0, gp_in1, gp_in2, gp_in3,
output reg [31:0] gp_out,
// Diagnostic
output diag
);
// CPU
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
reg [31:0] mem_rdata;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
picorv32 #(
.PROGADDR_RESET(32'h 0000_0000), // start or ROM
.STACKADDR(32'h 1001_0000), // end of SPRAM
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_COUNTERS(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.CATCH_MISALIGN(0),
.CATCH_ILLINSN(0)
) cpu_I (
.clk (clk24),
.resetn (~reset),
.mem_valid (mem_valid),
.mem_instr (mem_instr),
.mem_ready (mem_ready),
.mem_addr (mem_addr),
.mem_wdata (mem_wdata),
.mem_wstrb (mem_wstrb),
.mem_rdata (mem_rdata)
);
// Address decode
wire rom_sel = (mem_addr[31:28]==4'h0)&mem_valid ? 1'b1 : 1'b0;
wire ram_sel = (mem_addr[31:28]==4'h1)&mem_valid ? 1'b1 : 1'b0;
wire gio_sel = (mem_addr[31:28]==4'h2)&mem_valid ? 1'b1 : 1'b0;
wire ser_sel = (mem_addr[31:28]==4'h3)&mem_valid ? 1'b1 : 1'b0;
wire cnt_sel = (mem_addr[31:28]==4'h5)&mem_valid ? 1'b1 : 1'b0;
// 2k x 32 ROM
reg [31:0] rom[2047:0], rom_do;
initial
$readmemh("rom.hex",rom);
always @(posedge clk24)
rom_do <= rom[mem_addr[12:2]];
// RAM, byte addressable
wire [31:0] ram_do;
spram_16kx32 uram(
.clk(clk24),
.sel(ram_sel),
.we(mem_wstrb),
.addr(mem_addr[15:0]),
.wdat(mem_wdata),
.rdat(ram_do)
);
// GPIO Output
always @(posedge clk24)
if(gio_sel)
begin
if(mem_wstrb[0])
gp_out[7:0] <= mem_wdata[7:0];
if(mem_wstrb[1])
gp_out[15:8] <= mem_wdata[15:8];
if(mem_wstrb[2])
gp_out[23:16] <= mem_wdata[23:16];
if(mem_wstrb[3])
gp_out[31:24] <= mem_wdata[31:24];
end
// GPIO input
reg [31:0] gio_do;
always @(posedge clk24)
if(gio_sel)
case(mem_addr[3:2])
2'b00: gio_do <= gp_in0;
2'b01: gio_do <= gp_in1;
2'b10: gio_do <= gp_in2;
2'b11: gio_do <= gp_in3;
endcase
// Serial
wire [7:0] ser_do;
acia uacia(
.clk(clk24), // system clock
.rst(reset), // system reset
.cs(ser_sel), // chip select
.we(mem_wstrb[0]), // write enable
.rs(mem_addr[2]), // address
.rx(RX), // serial receive
.din(mem_wdata[7:0]), // data bus input
.dout(ser_do), // data bus output
.tx(TX), // serial transmit
.irq() // interrupt request
);
// Resettable clock counter
reg [31:0] cnt;
always @(posedge clk24)
if(cnt_sel & |mem_wstrb)
begin
if(mem_wstrb[0])
cnt[7:0] <= mem_wdata[7:0];
if(mem_wstrb[1])
cnt[15:8] <= mem_wdata[15:8];
if(mem_wstrb[2])
cnt[23:16] <= mem_wdata[23:16];
if(mem_wstrb[3])
cnt[31:24] <= mem_wdata[31:24];
end
else
cnt <= cnt + 32'd1;
// Read Mux
always @(*)
casex({cnt_sel,ser_sel,gio_sel,ram_sel,rom_sel})
5'b00001: mem_rdata = rom_do;
5'b0001x: mem_rdata = ram_do;
5'b001xx: mem_rdata = gio_do;
5'b01xxx: mem_rdata = {{24{1'b0}},ser_do};
5'b1xxxx: mem_rdata = cnt;
default: mem_rdata = 32'd0;
endcase
// ready flag
reg mem_rdy;
always @(posedge clk24)
if(reset)
mem_rdy <= 1'b0;
else
mem_rdy <= (cnt_sel|ser_sel|gio_sel|ram_sel|rom_sel) & ~mem_rdy;
assign mem_ready = mem_rdy;
// hook up diag
assign diag = mem_valid;
endmodule |
module bram_512x32(
input clk,
input sel,
input [3:0] we,
input [10:0] addr,
input [31:0] wdat,
output reg [31:0] rdat
);
// memory
reg [31:0] ram[511:0];
// write logic
always @(posedge clk)
if(sel)
begin
if(we[0])
ram[addr[10:2]][7:0] <= wdat[7:0];
if(we[1])
ram[addr[10:2]][15:8] <= wdat[15:8];
if(we[2])
ram[addr[10:2]][23:16] <= wdat[23:16];
if(we[3])
ram[addr[10:2]][31:24] <= wdat[31:24];
end
// read logic
always @(posedge clk)
rdat <= ram[addr[10:2]];
endmodule |
module spram_16kx32(
input clk,
input sel,
input [3:0] we,
input [15:0] addr,
input [31:0] wdat,
output [31:0] rdat
);
// instantiate the big RAMs
SB_SPRAM256KA mem_lo (
.ADDRESS(addr[15:2]),
.DATAIN(wdat[15:0]),
.MASKWREN({we[1],we[1],we[0],we[0]}),
.WREN(|we),
.CHIPSELECT(sel),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdat[15:0])
);
SB_SPRAM256KA mem_hi (
.ADDRESS(addr[15:2]),
.DATAIN(wdat[31:16]),
.MASKWREN({we[3],we[3],we[2],we[2]}),
.WREN(|we),
.CHIPSELECT(sel),
.CLOCK(clk),
.STANDBY(1'b0),
.SLEEP(1'b0),
.POWEROFF(1'b1),
.DATAOUT(rdat[31:16])
);
endmodule |
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule |
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule |
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule |
module \$_DFF_PN0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
endmodule |
module \$_DFF_PN1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
endmodule |
module dpram_1024x8_core (
input wclk,
input wen,
input [0:9] waddr,
input [0:7] data_in,
input rclk,
input ren,
input [0:9] raddr,
output [0:7] data_out );
reg [0:7] ram[0:1023];
reg [0:7] internal;
assign data_out = internal;
always @(posedge wclk) begin
if(wen) begin
ram[waddr] <= data_in;
end
end
always @(posedge rclk) begin
if(ren) begin
internal <= ram[raddr];
end
end
endmodule |
module dpram_1024x8 (
input clk,
input wen,
input ren,
input [0:9] waddr,
input [0:9] raddr,
input [0:7] data_in,
output [0:7] data_out );
dpram_1024x8_core memory_0 (
.wclk (clk),
.wen (wen),
.waddr (waddr),
.data_in (data_in),
.rclk (clk),
.ren (ren),
.raddr (raddr),
.data_out (data_out) );
endmodule |
module mult_36(
input [0:35] A,
input [0:35] B,
output [0:71] Y
);
assign Y = A * B;
endmodule |
module dffrn(
output reg Q,
input D,
input RN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
1'b1:
always @(negedge C or negedge RN)
if (RN == 1'b0)
Q <= 1'b0;
else
Q <= D;
endcase
endmodule |
module dffsn(
output reg Q,
input D,
input SN,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
initial Q = INIT;
case(|IS_C_INVERTED)
1'b0:
always @(posedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
1'b1:
always @(negedge C or negedge SN)
if (SN == 1'b0)
Q <= 1'b1;
else
Q <= D;
endcase
endmodule |
module mult_8(
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
assign Y = A * B;
endmodule |
module mult_8(
input [0:7] A,
input [0:7] B,
output [0:15] Y
);
parameter MODE = 1'b1;
assign Y = A * B;
endmodule |
module mult_16(
input [0:15] A,
input [0:15] B,
output [0:31] Y
);
parameter MODE = 1'b0;
assign Y = A * B;
endmodule |
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